1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright (C) 1989-2021 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 /* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
23 x86_64 support by Jan Hubicka (jh@suse.cz)
24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
29 #include "safe-ctype.h"
31 #include "dwarf2dbg.h"
32 #include "dw2gencfi.h"
33 #include "elf/x86-64.h"
34 #include "opcodes/i386-init.h"
37 #ifndef INFER_ADDR_PREFIX
38 #define INFER_ADDR_PREFIX 1
42 #define DEFAULT_ARCH "i386"
47 #define INLINE __inline__
53 /* Prefixes will be emitted in the order defined below.
54 WAIT_PREFIX must be the first prefix since FWAIT is really is an
55 instruction, and so must come before any prefixes.
56 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
57 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
63 #define HLE_PREFIX REP_PREFIX
64 #define BND_PREFIX REP_PREFIX
66 #define REX_PREFIX 6 /* must come last. */
67 #define MAX_PREFIXES 7 /* max prefixes per opcode */
69 /* we define the syntax here (modulo base,index,scale syntax) */
70 #define REGISTER_PREFIX '%'
71 #define IMMEDIATE_PREFIX '$'
72 #define ABSOLUTE_PREFIX '*'
74 /* these are the instruction mnemonic suffixes in AT&T syntax or
75 memory operand size in Intel syntax. */
76 #define WORD_MNEM_SUFFIX 'w'
77 #define BYTE_MNEM_SUFFIX 'b'
78 #define SHORT_MNEM_SUFFIX 's'
79 #define LONG_MNEM_SUFFIX 'l'
80 #define QWORD_MNEM_SUFFIX 'q'
81 /* Intel Syntax. Use a non-ascii letter since since it never appears
83 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
85 #define END_OF_INSN '\0'
87 /* This matches the C -> StaticRounding alias in the opcode table. */
88 #define commutative staticrounding
91 'templates' is for grouping together 'template' structures for opcodes
92 of the same name. This is only used for storing the insns in the grand
93 ole hash table of insns.
94 The templates themselves start at START and range up to (but not including)
99 const insn_template
*start
;
100 const insn_template
*end
;
104 /* 386 operand encoding bytes: see 386 book for details of this. */
107 unsigned int regmem
; /* codes register or memory operand */
108 unsigned int reg
; /* codes register operand (or extended opcode) */
109 unsigned int mode
; /* how to interpret regmem & reg */
113 /* x86-64 extension prefix. */
114 typedef int rex_byte
;
116 /* 386 opcode byte to code indirect addressing. */
125 /* x86 arch names, types and features */
128 const char *name
; /* arch name */
129 unsigned int len
; /* arch string length */
130 enum processor_type type
; /* arch type */
131 i386_cpu_flags flags
; /* cpu feature flags */
132 unsigned int skip
; /* show_arch should skip this. */
136 /* Used to turn off indicated flags. */
139 const char *name
; /* arch name */
140 unsigned int len
; /* arch string length */
141 i386_cpu_flags flags
; /* cpu feature flags */
145 static void update_code_flag (int, int);
146 static void set_code_flag (int);
147 static void set_16bit_gcc_code_flag (int);
148 static void set_intel_syntax (int);
149 static void set_intel_mnemonic (int);
150 static void set_allow_index_reg (int);
151 static void set_check (int);
152 static void set_cpu_arch (int);
154 static void pe_directive_secrel (int);
156 static void signed_cons (int);
157 static char *output_invalid (int c
);
158 static int i386_finalize_immediate (segT
, expressionS
*, i386_operand_type
,
160 static int i386_finalize_displacement (segT
, expressionS
*, i386_operand_type
,
162 static int i386_att_operand (char *);
163 static int i386_intel_operand (char *, int);
164 static int i386_intel_simplify (expressionS
*);
165 static int i386_intel_parse_name (const char *, expressionS
*);
166 static const reg_entry
*parse_register (char *, char **);
167 static char *parse_insn (char *, char *);
168 static char *parse_operands (char *, const char *);
169 static void swap_operands (void);
170 static void swap_2_operands (unsigned int, unsigned int);
171 static enum flag_code
i386_addressing_mode (void);
172 static void optimize_imm (void);
173 static void optimize_disp (void);
174 static const insn_template
*match_template (char);
175 static int check_string (void);
176 static int process_suffix (void);
177 static int check_byte_reg (void);
178 static int check_long_reg (void);
179 static int check_qword_reg (void);
180 static int check_word_reg (void);
181 static int finalize_imm (void);
182 static int process_operands (void);
183 static const reg_entry
*build_modrm_byte (void);
184 static void output_insn (void);
185 static void output_imm (fragS
*, offsetT
);
186 static void output_disp (fragS
*, offsetT
);
188 static void s_bss (int);
190 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
191 static void handle_large_common (int small ATTRIBUTE_UNUSED
);
193 /* GNU_PROPERTY_X86_ISA_1_USED. */
194 static unsigned int x86_isa_1_used
;
195 /* GNU_PROPERTY_X86_FEATURE_2_USED. */
196 static unsigned int x86_feature_2_used
;
197 /* Generate x86 used ISA and feature properties. */
198 static unsigned int x86_used_note
= DEFAULT_X86_USED_NOTE
;
201 static const char *default_arch
= DEFAULT_ARCH
;
203 /* parse_register() returns this when a register alias cannot be used. */
204 static const reg_entry bad_reg
= { "<bad>", OPERAND_TYPE_NONE
, 0, 0,
205 { Dw2Inval
, Dw2Inval
} };
207 static const reg_entry
*reg_eax
;
208 static const reg_entry
*reg_ds
;
209 static const reg_entry
*reg_es
;
210 static const reg_entry
*reg_ss
;
211 static const reg_entry
*reg_st0
;
212 static const reg_entry
*reg_k0
;
217 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
218 unsigned char bytes
[4];
220 /* Destination or source register specifier. */
221 const reg_entry
*register_specifier
;
224 /* 'md_assemble ()' gathers together information and puts it into a
231 const reg_entry
*regs
;
236 operand_size_mismatch
,
237 operand_type_mismatch
,
238 register_type_mismatch
,
239 number_of_operands_mismatch
,
240 invalid_instruction_suffix
,
242 unsupported_with_intel_mnemonic
,
246 invalid_vsib_address
,
247 invalid_vector_register_set
,
248 invalid_tmm_register_set
,
249 unsupported_vector_index_register
,
250 unsupported_broadcast
,
253 mask_not_on_destination
,
256 rc_sae_operand_not_last_imm
,
257 invalid_register_operand
,
262 /* TM holds the template for the insn were currently assembling. */
265 /* SUFFIX holds the instruction size suffix for byte, word, dword
266 or qword, if given. */
269 /* OPCODE_LENGTH holds the number of base opcode bytes. */
270 unsigned char opcode_length
;
272 /* OPERANDS gives the number of given operands. */
273 unsigned int operands
;
275 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
276 of given register, displacement, memory operands and immediate
278 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
280 /* TYPES [i] is the type (see above #defines) which tells us how to
281 use OP[i] for the corresponding operand. */
282 i386_operand_type types
[MAX_OPERANDS
];
284 /* Displacement expression, immediate expression, or register for each
286 union i386_op op
[MAX_OPERANDS
];
288 /* Flags for operands. */
289 unsigned int flags
[MAX_OPERANDS
];
290 #define Operand_PCrel 1
291 #define Operand_Mem 2
293 /* Relocation type for operand */
294 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
296 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
297 the base index byte below. */
298 const reg_entry
*base_reg
;
299 const reg_entry
*index_reg
;
300 unsigned int log2_scale_factor
;
302 /* SEG gives the seg_entries of this insn. They are zero unless
303 explicit segment overrides are given. */
304 const reg_entry
*seg
[2];
306 /* Copied first memory operand string, for re-checking. */
309 /* PREFIX holds all the given prefix opcodes (usually null).
310 PREFIXES is the number of prefix opcodes. */
311 unsigned int prefixes
;
312 unsigned char prefix
[MAX_PREFIXES
];
314 /* Register is in low 3 bits of opcode. */
317 /* The operand to a branch insn indicates an absolute branch. */
320 /* Extended states. */
328 xstate_ymm
= 1 << 2 | xstate_xmm
,
330 xstate_zmm
= 1 << 3 | xstate_ymm
,
333 /* Use MASK state. */
337 /* Has GOTPC or TLS relocation. */
338 bool has_gotpc_tls_reloc
;
340 /* RM and SIB are the modrm byte and the sib byte where the
341 addressing modes of this insn are encoded. */
348 /* Masking attributes.
350 The struct describes masking, applied to OPERAND in the instruction.
351 REG is a pointer to the corresponding mask register. ZEROING tells
352 whether merging or zeroing mask is used. */
353 struct Mask_Operation
355 const reg_entry
*reg
;
356 unsigned int zeroing
;
357 /* The operand where this operation is associated. */
358 unsigned int operand
;
361 /* Rounding control and SAE attributes. */
374 unsigned int operand
;
377 /* Broadcasting attributes.
379 The struct describes broadcasting, applied to OPERAND. TYPE is
380 expresses the broadcast factor. */
381 struct Broadcast_Operation
383 /* Type of broadcast: {1to2}, {1to4}, {1to8}, or {1to16}. */
386 /* Index of broadcasted operand. */
387 unsigned int operand
;
389 /* Number of bytes to broadcast. */
393 /* Compressed disp8*N attribute. */
394 unsigned int memshift
;
396 /* Prefer load or store in encoding. */
399 dir_encoding_default
= 0,
405 /* Prefer 8bit, 16bit, 32bit displacement in encoding. */
408 disp_encoding_default
= 0,
414 /* Prefer the REX byte in encoding. */
417 /* Disable instruction size optimization. */
420 /* How to encode vector instructions. */
423 vex_encoding_default
= 0,
431 const char *rep_prefix
;
434 const char *hle_prefix
;
436 /* Have BND prefix. */
437 const char *bnd_prefix
;
439 /* Have NOTRACK prefix. */
440 const char *notrack_prefix
;
443 enum i386_error error
;
446 typedef struct _i386_insn i386_insn
;
448 /* Link RC type with corresponding string, that'll be looked for in
457 static const struct RC_name RC_NamesTable
[] =
459 { rne
, STRING_COMMA_LEN ("rn-sae") },
460 { rd
, STRING_COMMA_LEN ("rd-sae") },
461 { ru
, STRING_COMMA_LEN ("ru-sae") },
462 { rz
, STRING_COMMA_LEN ("rz-sae") },
463 { saeonly
, STRING_COMMA_LEN ("sae") },
466 /* List of chars besides those in app.c:symbol_chars that can start an
467 operand. Used to prevent the scrubber eating vital white-space. */
468 const char extra_symbol_chars
[] = "*%-([{}"
477 #if ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
478 && !defined (TE_GNU) \
479 && !defined (TE_LINUX) \
480 && !defined (TE_FreeBSD) \
481 && !defined (TE_DragonFly) \
482 && !defined (TE_NetBSD))
483 /* This array holds the chars that always start a comment. If the
484 pre-processor is disabled, these aren't very useful. The option
485 --divide will remove '/' from this list. */
486 const char *i386_comment_chars
= "#/";
487 #define SVR4_COMMENT_CHARS 1
488 #define PREFIX_SEPARATOR '\\'
491 const char *i386_comment_chars
= "#";
492 #define PREFIX_SEPARATOR '/'
495 /* This array holds the chars that only start a comment at the beginning of
496 a line. If the line seems to have the form '# 123 filename'
497 .line and .file directives will appear in the pre-processed output.
498 Note that input_file.c hand checks for '#' at the beginning of the
499 first line of the input file. This is because the compiler outputs
500 #NO_APP at the beginning of its output.
501 Also note that comments started like this one will always work if
502 '/' isn't otherwise defined. */
503 const char line_comment_chars
[] = "#/";
505 const char line_separator_chars
[] = ";";
507 /* Chars that can be used to separate mant from exp in floating point
509 const char EXP_CHARS
[] = "eE";
511 /* Chars that mean this number is a floating point constant
514 const char FLT_CHARS
[] = "fFdDxX";
516 /* Tables for lexical analysis. */
517 static char mnemonic_chars
[256];
518 static char register_chars
[256];
519 static char operand_chars
[256];
520 static char identifier_chars
[256];
521 static char digit_chars
[256];
523 /* Lexical macros. */
524 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
525 #define is_operand_char(x) (operand_chars[(unsigned char) x])
526 #define is_register_char(x) (register_chars[(unsigned char) x])
527 #define is_space_char(x) ((x) == ' ')
528 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
529 #define is_digit_char(x) (digit_chars[(unsigned char) x])
531 /* All non-digit non-letter characters that may occur in an operand. */
532 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
534 /* md_assemble() always leaves the strings it's passed unaltered. To
535 effect this we maintain a stack of saved characters that we've smashed
536 with '\0's (indicating end of strings for various sub-fields of the
537 assembler instruction). */
538 static char save_stack
[32];
539 static char *save_stack_p
;
540 #define END_STRING_AND_SAVE(s) \
541 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
542 #define RESTORE_END_STRING(s) \
543 do { *(s) = *--save_stack_p; } while (0)
545 /* The instruction we're assembling. */
548 /* Possible templates for current insn. */
549 static const templates
*current_templates
;
551 /* Per instruction expressionS buffers: max displacements & immediates. */
552 static expressionS disp_expressions
[MAX_MEMORY_OPERANDS
];
553 static expressionS im_expressions
[MAX_IMMEDIATE_OPERANDS
];
555 /* Current operand we are working on. */
556 static int this_operand
= -1;
558 /* We support four different modes. FLAG_CODE variable is used to distinguish
566 static enum flag_code flag_code
;
567 static unsigned int object_64bit
;
568 static unsigned int disallow_64bit_reloc
;
569 static int use_rela_relocations
= 0;
570 /* __tls_get_addr/___tls_get_addr symbol for TLS. */
571 static const char *tls_get_addr
;
573 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
574 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
575 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
577 /* The ELF ABI to use. */
585 static enum x86_elf_abi x86_elf_abi
= I386_ABI
;
588 #if defined (TE_PE) || defined (TE_PEP)
589 /* Use big object file format. */
590 static int use_big_obj
= 0;
593 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
594 /* 1 if generating code for a shared library. */
595 static int shared
= 0;
598 /* 1 for intel syntax,
600 static int intel_syntax
= 0;
602 static enum x86_64_isa
604 amd64
= 1, /* AMD64 ISA. */
605 intel64
/* Intel64 ISA. */
608 /* 1 for intel mnemonic,
609 0 if att mnemonic. */
610 static int intel_mnemonic
= !SYSV386_COMPAT
;
612 /* 1 if pseudo registers are permitted. */
613 static int allow_pseudo_reg
= 0;
615 /* 1 if register prefix % not required. */
616 static int allow_naked_reg
= 0;
618 /* 1 if the assembler should add BND prefix for all control-transferring
619 instructions supporting it, even if this prefix wasn't specified
621 static int add_bnd_prefix
= 0;
623 /* 1 if pseudo index register, eiz/riz, is allowed . */
624 static int allow_index_reg
= 0;
626 /* 1 if the assembler should ignore LOCK prefix, even if it was
627 specified explicitly. */
628 static int omit_lock_prefix
= 0;
630 /* 1 if the assembler should encode lfence, mfence, and sfence as
631 "lock addl $0, (%{re}sp)". */
632 static int avoid_fence
= 0;
634 /* 1 if lfence should be inserted after every load. */
635 static int lfence_after_load
= 0;
637 /* Non-zero if lfence should be inserted before indirect branch. */
638 static enum lfence_before_indirect_branch_kind
640 lfence_branch_none
= 0,
641 lfence_branch_register
,
642 lfence_branch_memory
,
645 lfence_before_indirect_branch
;
647 /* Non-zero if lfence should be inserted before ret. */
648 static enum lfence_before_ret_kind
650 lfence_before_ret_none
= 0,
651 lfence_before_ret_not
,
652 lfence_before_ret_or
,
653 lfence_before_ret_shl
657 /* Types of previous instruction is .byte or prefix. */
672 /* 1 if the assembler should generate relax relocations. */
674 static int generate_relax_relocations
675 = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS
;
677 static enum check_kind
683 sse_check
, operand_check
= check_warning
;
685 /* Non-zero if branches should be aligned within power of 2 boundary. */
686 static int align_branch_power
= 0;
688 /* Types of branches to align. */
689 enum align_branch_kind
691 align_branch_none
= 0,
692 align_branch_jcc
= 1,
693 align_branch_fused
= 2,
694 align_branch_jmp
= 3,
695 align_branch_call
= 4,
696 align_branch_indirect
= 5,
700 /* Type bits of branches to align. */
701 enum align_branch_bit
703 align_branch_jcc_bit
= 1 << align_branch_jcc
,
704 align_branch_fused_bit
= 1 << align_branch_fused
,
705 align_branch_jmp_bit
= 1 << align_branch_jmp
,
706 align_branch_call_bit
= 1 << align_branch_call
,
707 align_branch_indirect_bit
= 1 << align_branch_indirect
,
708 align_branch_ret_bit
= 1 << align_branch_ret
711 static unsigned int align_branch
= (align_branch_jcc_bit
712 | align_branch_fused_bit
713 | align_branch_jmp_bit
);
715 /* Types of condition jump used by macro-fusion. */
718 mf_jcc_jo
= 0, /* base opcode 0x70 */
719 mf_jcc_jc
, /* base opcode 0x72 */
720 mf_jcc_je
, /* base opcode 0x74 */
721 mf_jcc_jna
, /* base opcode 0x76 */
722 mf_jcc_js
, /* base opcode 0x78 */
723 mf_jcc_jp
, /* base opcode 0x7a */
724 mf_jcc_jl
, /* base opcode 0x7c */
725 mf_jcc_jle
, /* base opcode 0x7e */
728 /* Types of compare flag-modifying insntructions used by macro-fusion. */
731 mf_cmp_test_and
, /* test/cmp */
732 mf_cmp_alu_cmp
, /* add/sub/cmp */
733 mf_cmp_incdec
/* inc/dec */
736 /* The maximum padding size for fused jcc. CMP like instruction can
737 be 9 bytes and jcc can be 6 bytes. Leave room just in case for
739 #define MAX_FUSED_JCC_PADDING_SIZE 20
741 /* The maximum number of prefixes added for an instruction. */
742 static unsigned int align_branch_prefix_size
= 5;
745 1. Clear the REX_W bit with register operand if possible.
746 2. Above plus use 128bit vector instruction to clear the full vector
749 static int optimize
= 0;
752 1. Clear the REX_W bit with register operand if possible.
753 2. Above plus use 128bit vector instruction to clear the full vector
755 3. Above plus optimize "test{q,l,w} $imm8,%r{64,32,16}" to
758 static int optimize_for_space
= 0;
760 /* Register prefix used for error message. */
761 static const char *register_prefix
= "%";
763 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
764 leave, push, and pop instructions so that gcc has the same stack
765 frame as in 32 bit mode. */
766 static char stackop_size
= '\0';
768 /* Non-zero to optimize code alignment. */
769 int optimize_align_code
= 1;
771 /* Non-zero to quieten some warnings. */
772 static int quiet_warnings
= 0;
775 static const char *cpu_arch_name
= NULL
;
776 static char *cpu_sub_arch_name
= NULL
;
778 /* CPU feature flags. */
779 static i386_cpu_flags cpu_arch_flags
= CPU_UNKNOWN_FLAGS
;
781 /* If we have selected a cpu we are generating instructions for. */
782 static int cpu_arch_tune_set
= 0;
784 /* Cpu we are generating instructions for. */
785 enum processor_type cpu_arch_tune
= PROCESSOR_UNKNOWN
;
787 /* CPU feature flags of cpu we are generating instructions for. */
788 static i386_cpu_flags cpu_arch_tune_flags
;
790 /* CPU instruction set architecture used. */
791 enum processor_type cpu_arch_isa
= PROCESSOR_UNKNOWN
;
793 /* CPU feature flags of instruction set architecture used. */
794 i386_cpu_flags cpu_arch_isa_flags
;
796 /* If set, conditional jumps are not automatically promoted to handle
797 larger than a byte offset. */
798 static unsigned int no_cond_jump_promotion
= 0;
800 /* Encode SSE instructions with VEX prefix. */
801 static unsigned int sse2avx
;
803 /* Encode scalar AVX instructions with specific vector length. */
810 /* Encode VEX WIG instructions with specific vex.w. */
817 /* Encode scalar EVEX LIG instructions with specific vector length. */
825 /* Encode EVEX WIG instructions with specific evex.w. */
832 /* Value to encode in EVEX RC bits, for SAE-only instructions. */
833 static enum rc_type evexrcig
= rne
;
835 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
836 static symbolS
*GOT_symbol
;
838 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
839 unsigned int x86_dwarf2_return_column
;
841 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
842 int x86_cie_data_alignment
;
844 /* Interface to relax_segment.
845 There are 3 major relax states for 386 jump insns because the
846 different types of jumps add different sizes to frags when we're
847 figuring out what sort of jump to choose to reach a given label.
849 BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING are used to align
850 branches which are handled by md_estimate_size_before_relax() and
851 i386_generic_table_relax_frag(). */
854 #define UNCOND_JUMP 0
856 #define COND_JUMP86 2
857 #define BRANCH_PADDING 3
858 #define BRANCH_PREFIX 4
859 #define FUSED_JCC_PADDING 5
864 #define SMALL16 (SMALL | CODE16)
866 #define BIG16 (BIG | CODE16)
870 #define INLINE __inline__
876 #define ENCODE_RELAX_STATE(type, size) \
877 ((relax_substateT) (((type) << 2) | (size)))
878 #define TYPE_FROM_RELAX_STATE(s) \
880 #define DISP_SIZE_FROM_RELAX_STATE(s) \
881 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
883 /* This table is used by relax_frag to promote short jumps to long
884 ones where necessary. SMALL (short) jumps may be promoted to BIG
885 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
886 don't allow a short jump in a 32 bit code segment to be promoted to
887 a 16 bit offset jump because it's slower (requires data size
888 prefix), and doesn't work, unless the destination is in the bottom
889 64k of the code segment (The top 16 bits of eip are zeroed). */
891 const relax_typeS md_relax_table
[] =
894 1) most positive reach of this state,
895 2) most negative reach of this state,
896 3) how many bytes this mode will have in the variable part of the frag
897 4) which index into the table to try if we can't fit into this one. */
899 /* UNCOND_JUMP states. */
900 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
901 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
902 /* dword jmp adds 4 bytes to frag:
903 0 extra opcode bytes, 4 displacement bytes. */
905 /* word jmp adds 2 byte2 to frag:
906 0 extra opcode bytes, 2 displacement bytes. */
909 /* COND_JUMP states. */
910 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
911 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
912 /* dword conditionals adds 5 bytes to frag:
913 1 extra opcode byte, 4 displacement bytes. */
915 /* word conditionals add 3 bytes to frag:
916 1 extra opcode byte, 2 displacement bytes. */
919 /* COND_JUMP86 states. */
920 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
921 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
922 /* dword conditionals adds 5 bytes to frag:
923 1 extra opcode byte, 4 displacement bytes. */
925 /* word conditionals add 4 bytes to frag:
926 1 displacement byte and a 3 byte long branch insn. */
930 static const arch_entry cpu_arch
[] =
932 /* Do not replace the first two entries - i386_target_format()
933 relies on them being there in this order. */
934 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32
,
935 CPU_GENERIC32_FLAGS
, 0 },
936 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64
,
937 CPU_GENERIC64_FLAGS
, 0 },
938 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN
,
940 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN
,
942 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN
,
944 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386
,
946 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486
,
948 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM
,
950 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO
,
952 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM
,
954 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO
,
955 CPU_PENTIUMPRO_FLAGS
, 0 },
956 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO
,
958 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO
,
960 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4
,
962 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA
,
964 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA
,
965 CPU_NOCONA_FLAGS
, 0 },
966 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE
,
968 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE
,
970 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2
,
971 CPU_CORE2_FLAGS
, 1 },
972 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2
,
973 CPU_CORE2_FLAGS
, 0 },
974 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7
,
975 CPU_COREI7_FLAGS
, 0 },
976 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM
,
978 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM
,
980 { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU
,
981 CPU_IAMCU_FLAGS
, 0 },
982 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6
,
984 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6
,
986 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON
,
987 CPU_ATHLON_FLAGS
, 0 },
988 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8
,
990 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8
,
992 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8
,
994 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10
,
995 CPU_AMDFAM10_FLAGS
, 0 },
996 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD
,
997 CPU_BDVER1_FLAGS
, 0 },
998 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD
,
999 CPU_BDVER2_FLAGS
, 0 },
1000 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD
,
1001 CPU_BDVER3_FLAGS
, 0 },
1002 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD
,
1003 CPU_BDVER4_FLAGS
, 0 },
1004 { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER
,
1005 CPU_ZNVER1_FLAGS
, 0 },
1006 { STRING_COMMA_LEN ("znver2"), PROCESSOR_ZNVER
,
1007 CPU_ZNVER2_FLAGS
, 0 },
1008 { STRING_COMMA_LEN ("znver3"), PROCESSOR_ZNVER
,
1009 CPU_ZNVER3_FLAGS
, 0 },
1010 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT
,
1011 CPU_BTVER1_FLAGS
, 0 },
1012 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT
,
1013 CPU_BTVER2_FLAGS
, 0 },
1014 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN
,
1015 CPU_8087_FLAGS
, 0 },
1016 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN
,
1018 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN
,
1020 { STRING_COMMA_LEN (".687"), PROCESSOR_UNKNOWN
,
1022 { STRING_COMMA_LEN (".cmov"), PROCESSOR_UNKNOWN
,
1023 CPU_CMOV_FLAGS
, 0 },
1024 { STRING_COMMA_LEN (".fxsr"), PROCESSOR_UNKNOWN
,
1025 CPU_FXSR_FLAGS
, 0 },
1026 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN
,
1028 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN
,
1030 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN
,
1031 CPU_SSE2_FLAGS
, 0 },
1032 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN
,
1033 CPU_SSE3_FLAGS
, 0 },
1034 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN
,
1035 CPU_SSE4A_FLAGS
, 0 },
1036 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN
,
1037 CPU_SSSE3_FLAGS
, 0 },
1038 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN
,
1039 CPU_SSE4_1_FLAGS
, 0 },
1040 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN
,
1041 CPU_SSE4_2_FLAGS
, 0 },
1042 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN
,
1043 CPU_SSE4_2_FLAGS
, 0 },
1044 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN
,
1046 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN
,
1047 CPU_AVX2_FLAGS
, 0 },
1048 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN
,
1049 CPU_AVX512F_FLAGS
, 0 },
1050 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN
,
1051 CPU_AVX512CD_FLAGS
, 0 },
1052 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN
,
1053 CPU_AVX512ER_FLAGS
, 0 },
1054 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN
,
1055 CPU_AVX512PF_FLAGS
, 0 },
1056 { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN
,
1057 CPU_AVX512DQ_FLAGS
, 0 },
1058 { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN
,
1059 CPU_AVX512BW_FLAGS
, 0 },
1060 { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN
,
1061 CPU_AVX512VL_FLAGS
, 0 },
1062 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN
,
1064 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN
,
1065 CPU_VMFUNC_FLAGS
, 0 },
1066 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN
,
1068 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN
,
1069 CPU_XSAVE_FLAGS
, 0 },
1070 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN
,
1071 CPU_XSAVEOPT_FLAGS
, 0 },
1072 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN
,
1073 CPU_XSAVEC_FLAGS
, 0 },
1074 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN
,
1075 CPU_XSAVES_FLAGS
, 0 },
1076 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN
,
1078 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN
,
1079 CPU_PCLMUL_FLAGS
, 0 },
1080 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN
,
1081 CPU_PCLMUL_FLAGS
, 1 },
1082 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN
,
1083 CPU_FSGSBASE_FLAGS
, 0 },
1084 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN
,
1085 CPU_RDRND_FLAGS
, 0 },
1086 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN
,
1087 CPU_F16C_FLAGS
, 0 },
1088 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN
,
1089 CPU_BMI2_FLAGS
, 0 },
1090 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN
,
1092 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN
,
1093 CPU_FMA4_FLAGS
, 0 },
1094 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN
,
1096 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN
,
1098 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN
,
1099 CPU_MOVBE_FLAGS
, 0 },
1100 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN
,
1101 CPU_CX16_FLAGS
, 0 },
1102 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN
,
1104 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN
,
1105 CPU_LZCNT_FLAGS
, 0 },
1106 { STRING_COMMA_LEN (".popcnt"), PROCESSOR_UNKNOWN
,
1107 CPU_POPCNT_FLAGS
, 0 },
1108 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN
,
1110 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN
,
1112 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN
,
1113 CPU_INVPCID_FLAGS
, 0 },
1114 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN
,
1115 CPU_CLFLUSH_FLAGS
, 0 },
1116 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN
,
1118 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN
,
1119 CPU_SYSCALL_FLAGS
, 0 },
1120 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN
,
1121 CPU_RDTSCP_FLAGS
, 0 },
1122 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN
,
1123 CPU_3DNOW_FLAGS
, 0 },
1124 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN
,
1125 CPU_3DNOWA_FLAGS
, 0 },
1126 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN
,
1127 CPU_PADLOCK_FLAGS
, 0 },
1128 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN
,
1129 CPU_SVME_FLAGS
, 1 },
1130 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN
,
1131 CPU_SVME_FLAGS
, 0 },
1132 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN
,
1133 CPU_SSE4A_FLAGS
, 0 },
1134 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN
,
1136 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN
,
1138 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN
,
1140 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN
,
1142 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN
,
1143 CPU_RDSEED_FLAGS
, 0 },
1144 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN
,
1145 CPU_PRFCHW_FLAGS
, 0 },
1146 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN
,
1147 CPU_SMAP_FLAGS
, 0 },
1148 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN
,
1150 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN
,
1152 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN
,
1153 CPU_CLFLUSHOPT_FLAGS
, 0 },
1154 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN
,
1155 CPU_PREFETCHWT1_FLAGS
, 0 },
1156 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN
,
1158 { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN
,
1159 CPU_CLWB_FLAGS
, 0 },
1160 { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN
,
1161 CPU_AVX512IFMA_FLAGS
, 0 },
1162 { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN
,
1163 CPU_AVX512VBMI_FLAGS
, 0 },
1164 { STRING_COMMA_LEN (".avx512_4fmaps"), PROCESSOR_UNKNOWN
,
1165 CPU_AVX512_4FMAPS_FLAGS
, 0 },
1166 { STRING_COMMA_LEN (".avx512_4vnniw"), PROCESSOR_UNKNOWN
,
1167 CPU_AVX512_4VNNIW_FLAGS
, 0 },
1168 { STRING_COMMA_LEN (".avx512_vpopcntdq"), PROCESSOR_UNKNOWN
,
1169 CPU_AVX512_VPOPCNTDQ_FLAGS
, 0 },
1170 { STRING_COMMA_LEN (".avx512_vbmi2"), PROCESSOR_UNKNOWN
,
1171 CPU_AVX512_VBMI2_FLAGS
, 0 },
1172 { STRING_COMMA_LEN (".avx512_vnni"), PROCESSOR_UNKNOWN
,
1173 CPU_AVX512_VNNI_FLAGS
, 0 },
1174 { STRING_COMMA_LEN (".avx512_bitalg"), PROCESSOR_UNKNOWN
,
1175 CPU_AVX512_BITALG_FLAGS
, 0 },
1176 { STRING_COMMA_LEN (".avx_vnni"), PROCESSOR_UNKNOWN
,
1177 CPU_AVX_VNNI_FLAGS
, 0 },
1178 { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN
,
1179 CPU_CLZERO_FLAGS
, 0 },
1180 { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN
,
1181 CPU_MWAITX_FLAGS
, 0 },
1182 { STRING_COMMA_LEN (".ospke"), PROCESSOR_UNKNOWN
,
1183 CPU_OSPKE_FLAGS
, 0 },
1184 { STRING_COMMA_LEN (".rdpid"), PROCESSOR_UNKNOWN
,
1185 CPU_RDPID_FLAGS
, 0 },
1186 { STRING_COMMA_LEN (".ptwrite"), PROCESSOR_UNKNOWN
,
1187 CPU_PTWRITE_FLAGS
, 0 },
1188 { STRING_COMMA_LEN (".ibt"), PROCESSOR_UNKNOWN
,
1190 { STRING_COMMA_LEN (".shstk"), PROCESSOR_UNKNOWN
,
1191 CPU_SHSTK_FLAGS
, 0 },
1192 { STRING_COMMA_LEN (".gfni"), PROCESSOR_UNKNOWN
,
1193 CPU_GFNI_FLAGS
, 0 },
1194 { STRING_COMMA_LEN (".vaes"), PROCESSOR_UNKNOWN
,
1195 CPU_VAES_FLAGS
, 0 },
1196 { STRING_COMMA_LEN (".vpclmulqdq"), PROCESSOR_UNKNOWN
,
1197 CPU_VPCLMULQDQ_FLAGS
, 0 },
1198 { STRING_COMMA_LEN (".wbnoinvd"), PROCESSOR_UNKNOWN
,
1199 CPU_WBNOINVD_FLAGS
, 0 },
1200 { STRING_COMMA_LEN (".pconfig"), PROCESSOR_UNKNOWN
,
1201 CPU_PCONFIG_FLAGS
, 0 },
1202 { STRING_COMMA_LEN (".waitpkg"), PROCESSOR_UNKNOWN
,
1203 CPU_WAITPKG_FLAGS
, 0 },
1204 { STRING_COMMA_LEN (".cldemote"), PROCESSOR_UNKNOWN
,
1205 CPU_CLDEMOTE_FLAGS
, 0 },
1206 { STRING_COMMA_LEN (".amx_int8"), PROCESSOR_UNKNOWN
,
1207 CPU_AMX_INT8_FLAGS
, 0 },
1208 { STRING_COMMA_LEN (".amx_bf16"), PROCESSOR_UNKNOWN
,
1209 CPU_AMX_BF16_FLAGS
, 0 },
1210 { STRING_COMMA_LEN (".amx_tile"), PROCESSOR_UNKNOWN
,
1211 CPU_AMX_TILE_FLAGS
, 0 },
1212 { STRING_COMMA_LEN (".movdiri"), PROCESSOR_UNKNOWN
,
1213 CPU_MOVDIRI_FLAGS
, 0 },
1214 { STRING_COMMA_LEN (".movdir64b"), PROCESSOR_UNKNOWN
,
1215 CPU_MOVDIR64B_FLAGS
, 0 },
1216 { STRING_COMMA_LEN (".avx512_bf16"), PROCESSOR_UNKNOWN
,
1217 CPU_AVX512_BF16_FLAGS
, 0 },
1218 { STRING_COMMA_LEN (".avx512_vp2intersect"), PROCESSOR_UNKNOWN
,
1219 CPU_AVX512_VP2INTERSECT_FLAGS
, 0 },
1220 { STRING_COMMA_LEN (".tdx"), PROCESSOR_UNKNOWN
,
1222 { STRING_COMMA_LEN (".enqcmd"), PROCESSOR_UNKNOWN
,
1223 CPU_ENQCMD_FLAGS
, 0 },
1224 { STRING_COMMA_LEN (".serialize"), PROCESSOR_UNKNOWN
,
1225 CPU_SERIALIZE_FLAGS
, 0 },
1226 { STRING_COMMA_LEN (".rdpru"), PROCESSOR_UNKNOWN
,
1227 CPU_RDPRU_FLAGS
, 0 },
1228 { STRING_COMMA_LEN (".mcommit"), PROCESSOR_UNKNOWN
,
1229 CPU_MCOMMIT_FLAGS
, 0 },
1230 { STRING_COMMA_LEN (".sev_es"), PROCESSOR_UNKNOWN
,
1231 CPU_SEV_ES_FLAGS
, 0 },
1232 { STRING_COMMA_LEN (".tsxldtrk"), PROCESSOR_UNKNOWN
,
1233 CPU_TSXLDTRK_FLAGS
, 0 },
1234 { STRING_COMMA_LEN (".kl"), PROCESSOR_UNKNOWN
,
1236 { STRING_COMMA_LEN (".widekl"), PROCESSOR_UNKNOWN
,
1237 CPU_WIDEKL_FLAGS
, 0 },
1238 { STRING_COMMA_LEN (".uintr"), PROCESSOR_UNKNOWN
,
1239 CPU_UINTR_FLAGS
, 0 },
1240 { STRING_COMMA_LEN (".hreset"), PROCESSOR_UNKNOWN
,
1241 CPU_HRESET_FLAGS
, 0 },
1244 static const noarch_entry cpu_noarch
[] =
1246 { STRING_COMMA_LEN ("no87"), CPU_ANY_X87_FLAGS
},
1247 { STRING_COMMA_LEN ("no287"), CPU_ANY_287_FLAGS
},
1248 { STRING_COMMA_LEN ("no387"), CPU_ANY_387_FLAGS
},
1249 { STRING_COMMA_LEN ("no687"), CPU_ANY_687_FLAGS
},
1250 { STRING_COMMA_LEN ("nocmov"), CPU_ANY_CMOV_FLAGS
},
1251 { STRING_COMMA_LEN ("nofxsr"), CPU_ANY_FXSR_FLAGS
},
1252 { STRING_COMMA_LEN ("nommx"), CPU_ANY_MMX_FLAGS
},
1253 { STRING_COMMA_LEN ("nosse"), CPU_ANY_SSE_FLAGS
},
1254 { STRING_COMMA_LEN ("nosse2"), CPU_ANY_SSE2_FLAGS
},
1255 { STRING_COMMA_LEN ("nosse3"), CPU_ANY_SSE3_FLAGS
},
1256 { STRING_COMMA_LEN ("nosse4a"), CPU_ANY_SSE4A_FLAGS
},
1257 { STRING_COMMA_LEN ("nossse3"), CPU_ANY_SSSE3_FLAGS
},
1258 { STRING_COMMA_LEN ("nosse4.1"), CPU_ANY_SSE4_1_FLAGS
},
1259 { STRING_COMMA_LEN ("nosse4.2"), CPU_ANY_SSE4_2_FLAGS
},
1260 { STRING_COMMA_LEN ("nosse4"), CPU_ANY_SSE4_1_FLAGS
},
1261 { STRING_COMMA_LEN ("noavx"), CPU_ANY_AVX_FLAGS
},
1262 { STRING_COMMA_LEN ("noavx2"), CPU_ANY_AVX2_FLAGS
},
1263 { STRING_COMMA_LEN ("noavx512f"), CPU_ANY_AVX512F_FLAGS
},
1264 { STRING_COMMA_LEN ("noavx512cd"), CPU_ANY_AVX512CD_FLAGS
},
1265 { STRING_COMMA_LEN ("noavx512er"), CPU_ANY_AVX512ER_FLAGS
},
1266 { STRING_COMMA_LEN ("noavx512pf"), CPU_ANY_AVX512PF_FLAGS
},
1267 { STRING_COMMA_LEN ("noavx512dq"), CPU_ANY_AVX512DQ_FLAGS
},
1268 { STRING_COMMA_LEN ("noavx512bw"), CPU_ANY_AVX512BW_FLAGS
},
1269 { STRING_COMMA_LEN ("noavx512vl"), CPU_ANY_AVX512VL_FLAGS
},
1270 { STRING_COMMA_LEN ("noavx512ifma"), CPU_ANY_AVX512IFMA_FLAGS
},
1271 { STRING_COMMA_LEN ("noavx512vbmi"), CPU_ANY_AVX512VBMI_FLAGS
},
1272 { STRING_COMMA_LEN ("noavx512_4fmaps"), CPU_ANY_AVX512_4FMAPS_FLAGS
},
1273 { STRING_COMMA_LEN ("noavx512_4vnniw"), CPU_ANY_AVX512_4VNNIW_FLAGS
},
1274 { STRING_COMMA_LEN ("noavx512_vpopcntdq"), CPU_ANY_AVX512_VPOPCNTDQ_FLAGS
},
1275 { STRING_COMMA_LEN ("noavx512_vbmi2"), CPU_ANY_AVX512_VBMI2_FLAGS
},
1276 { STRING_COMMA_LEN ("noavx512_vnni"), CPU_ANY_AVX512_VNNI_FLAGS
},
1277 { STRING_COMMA_LEN ("noavx512_bitalg"), CPU_ANY_AVX512_BITALG_FLAGS
},
1278 { STRING_COMMA_LEN ("noavx_vnni"), CPU_ANY_AVX_VNNI_FLAGS
},
1279 { STRING_COMMA_LEN ("noibt"), CPU_ANY_IBT_FLAGS
},
1280 { STRING_COMMA_LEN ("noshstk"), CPU_ANY_SHSTK_FLAGS
},
1281 { STRING_COMMA_LEN ("noamx_int8"), CPU_ANY_AMX_INT8_FLAGS
},
1282 { STRING_COMMA_LEN ("noamx_bf16"), CPU_ANY_AMX_BF16_FLAGS
},
1283 { STRING_COMMA_LEN ("noamx_tile"), CPU_ANY_AMX_TILE_FLAGS
},
1284 { STRING_COMMA_LEN ("nomovdiri"), CPU_ANY_MOVDIRI_FLAGS
},
1285 { STRING_COMMA_LEN ("nomovdir64b"), CPU_ANY_MOVDIR64B_FLAGS
},
1286 { STRING_COMMA_LEN ("noavx512_bf16"), CPU_ANY_AVX512_BF16_FLAGS
},
1287 { STRING_COMMA_LEN ("noavx512_vp2intersect"),
1288 CPU_ANY_AVX512_VP2INTERSECT_FLAGS
},
1289 { STRING_COMMA_LEN ("notdx"), CPU_ANY_TDX_FLAGS
},
1290 { STRING_COMMA_LEN ("noenqcmd"), CPU_ANY_ENQCMD_FLAGS
},
1291 { STRING_COMMA_LEN ("noserialize"), CPU_ANY_SERIALIZE_FLAGS
},
1292 { STRING_COMMA_LEN ("notsxldtrk"), CPU_ANY_TSXLDTRK_FLAGS
},
1293 { STRING_COMMA_LEN ("nokl"), CPU_ANY_KL_FLAGS
},
1294 { STRING_COMMA_LEN ("nowidekl"), CPU_ANY_WIDEKL_FLAGS
},
1295 { STRING_COMMA_LEN ("nouintr"), CPU_ANY_UINTR_FLAGS
},
1296 { STRING_COMMA_LEN ("nohreset"), CPU_ANY_HRESET_FLAGS
},
1300 /* Like s_lcomm_internal in gas/read.c but the alignment string
1301 is allowed to be optional. */
1304 pe_lcomm_internal (int needs_align
, symbolS
*symbolP
, addressT size
)
1311 && *input_line_pointer
== ',')
1313 align
= parse_align (needs_align
- 1);
1315 if (align
== (addressT
) -1)
1330 bss_alloc (symbolP
, size
, align
);
1335 pe_lcomm (int needs_align
)
1337 s_comm_internal (needs_align
* 2, pe_lcomm_internal
);
1341 const pseudo_typeS md_pseudo_table
[] =
1343 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
1344 {"align", s_align_bytes
, 0},
1346 {"align", s_align_ptwo
, 0},
1348 {"arch", set_cpu_arch
, 0},
1352 {"lcomm", pe_lcomm
, 1},
1354 {"ffloat", float_cons
, 'f'},
1355 {"dfloat", float_cons
, 'd'},
1356 {"tfloat", float_cons
, 'x'},
1358 {"slong", signed_cons
, 4},
1359 {"noopt", s_ignore
, 0},
1360 {"optim", s_ignore
, 0},
1361 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
1362 {"code16", set_code_flag
, CODE_16BIT
},
1363 {"code32", set_code_flag
, CODE_32BIT
},
1365 {"code64", set_code_flag
, CODE_64BIT
},
1367 {"intel_syntax", set_intel_syntax
, 1},
1368 {"att_syntax", set_intel_syntax
, 0},
1369 {"intel_mnemonic", set_intel_mnemonic
, 1},
1370 {"att_mnemonic", set_intel_mnemonic
, 0},
1371 {"allow_index_reg", set_allow_index_reg
, 1},
1372 {"disallow_index_reg", set_allow_index_reg
, 0},
1373 {"sse_check", set_check
, 0},
1374 {"operand_check", set_check
, 1},
1375 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1376 {"largecomm", handle_large_common
, 0},
1378 {"file", dwarf2_directive_file
, 0},
1379 {"loc", dwarf2_directive_loc
, 0},
1380 {"loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0},
1383 {"secrel32", pe_directive_secrel
, 0},
1388 /* For interface with expression (). */
1389 extern char *input_line_pointer
;
1391 /* Hash table for instruction mnemonic lookup. */
1392 static htab_t op_hash
;
1394 /* Hash table for register lookup. */
1395 static htab_t reg_hash
;
1397 /* Various efficient no-op patterns for aligning code labels.
1398 Note: Don't try to assemble the instructions in the comments.
1399 0L and 0w are not legal. */
1400 static const unsigned char f32_1
[] =
1402 static const unsigned char f32_2
[] =
1403 {0x66,0x90}; /* xchg %ax,%ax */
1404 static const unsigned char f32_3
[] =
1405 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1406 static const unsigned char f32_4
[] =
1407 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1408 static const unsigned char f32_6
[] =
1409 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1410 static const unsigned char f32_7
[] =
1411 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1412 static const unsigned char f16_3
[] =
1413 {0x8d,0x74,0x00}; /* lea 0(%si),%si */
1414 static const unsigned char f16_4
[] =
1415 {0x8d,0xb4,0x00,0x00}; /* lea 0W(%si),%si */
1416 static const unsigned char jump_disp8
[] =
1417 {0xeb}; /* jmp disp8 */
1418 static const unsigned char jump32_disp32
[] =
1419 {0xe9}; /* jmp disp32 */
1420 static const unsigned char jump16_disp32
[] =
1421 {0x66,0xe9}; /* jmp disp32 */
1422 /* 32-bit NOPs patterns. */
1423 static const unsigned char *const f32_patt
[] = {
1424 f32_1
, f32_2
, f32_3
, f32_4
, NULL
, f32_6
, f32_7
1426 /* 16-bit NOPs patterns. */
1427 static const unsigned char *const f16_patt
[] = {
1428 f32_1
, f32_2
, f16_3
, f16_4
1430 /* nopl (%[re]ax) */
1431 static const unsigned char alt_3
[] =
1433 /* nopl 0(%[re]ax) */
1434 static const unsigned char alt_4
[] =
1435 {0x0f,0x1f,0x40,0x00};
1436 /* nopl 0(%[re]ax,%[re]ax,1) */
1437 static const unsigned char alt_5
[] =
1438 {0x0f,0x1f,0x44,0x00,0x00};
1439 /* nopw 0(%[re]ax,%[re]ax,1) */
1440 static const unsigned char alt_6
[] =
1441 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1442 /* nopl 0L(%[re]ax) */
1443 static const unsigned char alt_7
[] =
1444 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1445 /* nopl 0L(%[re]ax,%[re]ax,1) */
1446 static const unsigned char alt_8
[] =
1447 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1448 /* nopw 0L(%[re]ax,%[re]ax,1) */
1449 static const unsigned char alt_9
[] =
1450 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1451 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1452 static const unsigned char alt_10
[] =
1453 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1454 /* data16 nopw %cs:0L(%eax,%eax,1) */
1455 static const unsigned char alt_11
[] =
1456 {0x66,0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1457 /* 32-bit and 64-bit NOPs patterns. */
1458 static const unsigned char *const alt_patt
[] = {
1459 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
1460 alt_9
, alt_10
, alt_11
1463 /* Genenerate COUNT bytes of NOPs to WHERE from PATT with the maximum
1464 size of a single NOP instruction MAX_SINGLE_NOP_SIZE. */
1467 i386_output_nops (char *where
, const unsigned char *const *patt
,
1468 int count
, int max_single_nop_size
)
1471 /* Place the longer NOP first. */
1474 const unsigned char *nops
;
1476 if (max_single_nop_size
< 1)
1478 as_fatal (_("i386_output_nops called to generate nops of at most %d bytes!"),
1479 max_single_nop_size
);
1483 nops
= patt
[max_single_nop_size
- 1];
1485 /* Use the smaller one if the requsted one isn't available. */
1488 max_single_nop_size
--;
1489 nops
= patt
[max_single_nop_size
- 1];
1492 last
= count
% max_single_nop_size
;
1495 for (offset
= 0; offset
< count
; offset
+= max_single_nop_size
)
1496 memcpy (where
+ offset
, nops
, max_single_nop_size
);
1500 nops
= patt
[last
- 1];
1503 /* Use the smaller one plus one-byte NOP if the needed one
1506 nops
= patt
[last
- 1];
1507 memcpy (where
+ offset
, nops
, last
);
1508 where
[offset
+ last
] = *patt
[0];
1511 memcpy (where
+ offset
, nops
, last
);
1516 fits_in_imm7 (offsetT num
)
1518 return (num
& 0x7f) == num
;
1522 fits_in_imm31 (offsetT num
)
1524 return (num
& 0x7fffffff) == num
;
1527 /* Genenerate COUNT bytes of NOPs to WHERE with the maximum size of a
1528 single NOP instruction LIMIT. */
1531 i386_generate_nops (fragS
*fragP
, char *where
, offsetT count
, int limit
)
1533 const unsigned char *const *patt
= NULL
;
1534 int max_single_nop_size
;
1535 /* Maximum number of NOPs before switching to jump over NOPs. */
1536 int max_number_of_nops
;
1538 switch (fragP
->fr_type
)
1543 case rs_machine_dependent
:
1544 /* Allow NOP padding for jumps and calls. */
1545 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
1546 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
)
1553 /* We need to decide which NOP sequence to use for 32bit and
1554 64bit. When -mtune= is used:
1556 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1557 PROCESSOR_GENERIC32, f32_patt will be used.
1558 2. For the rest, alt_patt will be used.
1560 When -mtune= isn't used, alt_patt will be used if
1561 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
1564 When -march= or .arch is used, we can't use anything beyond
1565 cpu_arch_isa_flags. */
1567 if (flag_code
== CODE_16BIT
)
1570 max_single_nop_size
= sizeof (f16_patt
) / sizeof (f16_patt
[0]);
1571 /* Limit number of NOPs to 2 in 16-bit mode. */
1572 max_number_of_nops
= 2;
1576 if (fragP
->tc_frag_data
.isa
== PROCESSOR_UNKNOWN
)
1578 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1579 switch (cpu_arch_tune
)
1581 case PROCESSOR_UNKNOWN
:
1582 /* We use cpu_arch_isa_flags to check if we SHOULD
1583 optimize with nops. */
1584 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1589 case PROCESSOR_PENTIUM4
:
1590 case PROCESSOR_NOCONA
:
1591 case PROCESSOR_CORE
:
1592 case PROCESSOR_CORE2
:
1593 case PROCESSOR_COREI7
:
1594 case PROCESSOR_L1OM
:
1595 case PROCESSOR_K1OM
:
1596 case PROCESSOR_GENERIC64
:
1598 case PROCESSOR_ATHLON
:
1600 case PROCESSOR_AMDFAM10
:
1602 case PROCESSOR_ZNVER
:
1606 case PROCESSOR_I386
:
1607 case PROCESSOR_I486
:
1608 case PROCESSOR_PENTIUM
:
1609 case PROCESSOR_PENTIUMPRO
:
1610 case PROCESSOR_IAMCU
:
1611 case PROCESSOR_GENERIC32
:
1618 switch (fragP
->tc_frag_data
.tune
)
1620 case PROCESSOR_UNKNOWN
:
1621 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1622 PROCESSOR_UNKNOWN. */
1626 case PROCESSOR_I386
:
1627 case PROCESSOR_I486
:
1628 case PROCESSOR_PENTIUM
:
1629 case PROCESSOR_IAMCU
:
1631 case PROCESSOR_ATHLON
:
1633 case PROCESSOR_AMDFAM10
:
1635 case PROCESSOR_ZNVER
:
1637 case PROCESSOR_GENERIC32
:
1638 /* We use cpu_arch_isa_flags to check if we CAN optimize
1640 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1645 case PROCESSOR_PENTIUMPRO
:
1646 case PROCESSOR_PENTIUM4
:
1647 case PROCESSOR_NOCONA
:
1648 case PROCESSOR_CORE
:
1649 case PROCESSOR_CORE2
:
1650 case PROCESSOR_COREI7
:
1651 case PROCESSOR_L1OM
:
1652 case PROCESSOR_K1OM
:
1653 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1658 case PROCESSOR_GENERIC64
:
1664 if (patt
== f32_patt
)
1666 max_single_nop_size
= sizeof (f32_patt
) / sizeof (f32_patt
[0]);
1667 /* Limit number of NOPs to 2 for older processors. */
1668 max_number_of_nops
= 2;
1672 max_single_nop_size
= sizeof (alt_patt
) / sizeof (alt_patt
[0]);
1673 /* Limit number of NOPs to 7 for newer processors. */
1674 max_number_of_nops
= 7;
1679 limit
= max_single_nop_size
;
1681 if (fragP
->fr_type
== rs_fill_nop
)
1683 /* Output NOPs for .nop directive. */
1684 if (limit
> max_single_nop_size
)
1686 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
1687 _("invalid single nop size: %d "
1688 "(expect within [0, %d])"),
1689 limit
, max_single_nop_size
);
1693 else if (fragP
->fr_type
!= rs_machine_dependent
)
1694 fragP
->fr_var
= count
;
1696 if ((count
/ max_single_nop_size
) > max_number_of_nops
)
1698 /* Generate jump over NOPs. */
1699 offsetT disp
= count
- 2;
1700 if (fits_in_imm7 (disp
))
1702 /* Use "jmp disp8" if possible. */
1704 where
[0] = jump_disp8
[0];
1710 unsigned int size_of_jump
;
1712 if (flag_code
== CODE_16BIT
)
1714 where
[0] = jump16_disp32
[0];
1715 where
[1] = jump16_disp32
[1];
1720 where
[0] = jump32_disp32
[0];
1724 count
-= size_of_jump
+ 4;
1725 if (!fits_in_imm31 (count
))
1727 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
1728 _("jump over nop padding out of range"));
1732 md_number_to_chars (where
+ size_of_jump
, count
, 4);
1733 where
+= size_of_jump
+ 4;
1737 /* Generate multiple NOPs. */
1738 i386_output_nops (where
, patt
, count
, limit
);
1742 operand_type_all_zero (const union i386_operand_type
*x
)
1744 switch (ARRAY_SIZE(x
->array
))
1755 return !x
->array
[0];
1762 operand_type_set (union i386_operand_type
*x
, unsigned int v
)
1764 switch (ARRAY_SIZE(x
->array
))
1780 x
->bitfield
.class = ClassNone
;
1781 x
->bitfield
.instance
= InstanceNone
;
1785 operand_type_equal (const union i386_operand_type
*x
,
1786 const union i386_operand_type
*y
)
1788 switch (ARRAY_SIZE(x
->array
))
1791 if (x
->array
[2] != y
->array
[2])
1795 if (x
->array
[1] != y
->array
[1])
1799 return x
->array
[0] == y
->array
[0];
1807 cpu_flags_all_zero (const union i386_cpu_flags
*x
)
1809 switch (ARRAY_SIZE(x
->array
))
1824 return !x
->array
[0];
1831 cpu_flags_equal (const union i386_cpu_flags
*x
,
1832 const union i386_cpu_flags
*y
)
1834 switch (ARRAY_SIZE(x
->array
))
1837 if (x
->array
[3] != y
->array
[3])
1841 if (x
->array
[2] != y
->array
[2])
1845 if (x
->array
[1] != y
->array
[1])
1849 return x
->array
[0] == y
->array
[0];
1857 cpu_flags_check_cpu64 (i386_cpu_flags f
)
1859 return !((flag_code
== CODE_64BIT
&& f
.bitfield
.cpuno64
)
1860 || (flag_code
!= CODE_64BIT
&& f
.bitfield
.cpu64
));
1863 static INLINE i386_cpu_flags
1864 cpu_flags_and (i386_cpu_flags x
, i386_cpu_flags y
)
1866 switch (ARRAY_SIZE (x
.array
))
1869 x
.array
[3] &= y
.array
[3];
1872 x
.array
[2] &= y
.array
[2];
1875 x
.array
[1] &= y
.array
[1];
1878 x
.array
[0] &= y
.array
[0];
1886 static INLINE i386_cpu_flags
1887 cpu_flags_or (i386_cpu_flags x
, i386_cpu_flags y
)
1889 switch (ARRAY_SIZE (x
.array
))
1892 x
.array
[3] |= y
.array
[3];
1895 x
.array
[2] |= y
.array
[2];
1898 x
.array
[1] |= y
.array
[1];
1901 x
.array
[0] |= y
.array
[0];
1909 static INLINE i386_cpu_flags
1910 cpu_flags_and_not (i386_cpu_flags x
, i386_cpu_flags y
)
1912 switch (ARRAY_SIZE (x
.array
))
1915 x
.array
[3] &= ~y
.array
[3];
1918 x
.array
[2] &= ~y
.array
[2];
1921 x
.array
[1] &= ~y
.array
[1];
1924 x
.array
[0] &= ~y
.array
[0];
1932 static const i386_cpu_flags avx512
= CPU_ANY_AVX512F_FLAGS
;
1934 #define CPU_FLAGS_ARCH_MATCH 0x1
1935 #define CPU_FLAGS_64BIT_MATCH 0x2
1937 #define CPU_FLAGS_PERFECT_MATCH \
1938 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_64BIT_MATCH)
1940 /* Return CPU flags match bits. */
1943 cpu_flags_match (const insn_template
*t
)
1945 i386_cpu_flags x
= t
->cpu_flags
;
1946 int match
= cpu_flags_check_cpu64 (x
) ? CPU_FLAGS_64BIT_MATCH
: 0;
1948 x
.bitfield
.cpu64
= 0;
1949 x
.bitfield
.cpuno64
= 0;
1951 if (cpu_flags_all_zero (&x
))
1953 /* This instruction is available on all archs. */
1954 match
|= CPU_FLAGS_ARCH_MATCH
;
1958 /* This instruction is available only on some archs. */
1959 i386_cpu_flags cpu
= cpu_arch_flags
;
1961 /* AVX512VL is no standalone feature - match it and then strip it. */
1962 if (x
.bitfield
.cpuavx512vl
&& !cpu
.bitfield
.cpuavx512vl
)
1964 x
.bitfield
.cpuavx512vl
= 0;
1966 cpu
= cpu_flags_and (x
, cpu
);
1967 if (!cpu_flags_all_zero (&cpu
))
1969 if (x
.bitfield
.cpuavx
)
1971 /* We need to check a few extra flags with AVX. */
1972 if (cpu
.bitfield
.cpuavx
1973 && (!t
->opcode_modifier
.sse2avx
1974 || (sse2avx
&& !i
.prefix
[DATA_PREFIX
]))
1975 && (!x
.bitfield
.cpuaes
|| cpu
.bitfield
.cpuaes
)
1976 && (!x
.bitfield
.cpugfni
|| cpu
.bitfield
.cpugfni
)
1977 && (!x
.bitfield
.cpupclmul
|| cpu
.bitfield
.cpupclmul
))
1978 match
|= CPU_FLAGS_ARCH_MATCH
;
1980 else if (x
.bitfield
.cpuavx512f
)
1982 /* We need to check a few extra flags with AVX512F. */
1983 if (cpu
.bitfield
.cpuavx512f
1984 && (!x
.bitfield
.cpugfni
|| cpu
.bitfield
.cpugfni
)
1985 && (!x
.bitfield
.cpuvaes
|| cpu
.bitfield
.cpuvaes
)
1986 && (!x
.bitfield
.cpuvpclmulqdq
|| cpu
.bitfield
.cpuvpclmulqdq
))
1987 match
|= CPU_FLAGS_ARCH_MATCH
;
1990 match
|= CPU_FLAGS_ARCH_MATCH
;
1996 static INLINE i386_operand_type
1997 operand_type_and (i386_operand_type x
, i386_operand_type y
)
1999 if (x
.bitfield
.class != y
.bitfield
.class)
2000 x
.bitfield
.class = ClassNone
;
2001 if (x
.bitfield
.instance
!= y
.bitfield
.instance
)
2002 x
.bitfield
.instance
= InstanceNone
;
2004 switch (ARRAY_SIZE (x
.array
))
2007 x
.array
[2] &= y
.array
[2];
2010 x
.array
[1] &= y
.array
[1];
2013 x
.array
[0] &= y
.array
[0];
2021 static INLINE i386_operand_type
2022 operand_type_and_not (i386_operand_type x
, i386_operand_type y
)
2024 gas_assert (y
.bitfield
.class == ClassNone
);
2025 gas_assert (y
.bitfield
.instance
== InstanceNone
);
2027 switch (ARRAY_SIZE (x
.array
))
2030 x
.array
[2] &= ~y
.array
[2];
2033 x
.array
[1] &= ~y
.array
[1];
2036 x
.array
[0] &= ~y
.array
[0];
2044 static INLINE i386_operand_type
2045 operand_type_or (i386_operand_type x
, i386_operand_type y
)
2047 gas_assert (x
.bitfield
.class == ClassNone
||
2048 y
.bitfield
.class == ClassNone
||
2049 x
.bitfield
.class == y
.bitfield
.class);
2050 gas_assert (x
.bitfield
.instance
== InstanceNone
||
2051 y
.bitfield
.instance
== InstanceNone
||
2052 x
.bitfield
.instance
== y
.bitfield
.instance
);
2054 switch (ARRAY_SIZE (x
.array
))
2057 x
.array
[2] |= y
.array
[2];
2060 x
.array
[1] |= y
.array
[1];
2063 x
.array
[0] |= y
.array
[0];
2071 static INLINE i386_operand_type
2072 operand_type_xor (i386_operand_type x
, i386_operand_type y
)
2074 gas_assert (y
.bitfield
.class == ClassNone
);
2075 gas_assert (y
.bitfield
.instance
== InstanceNone
);
2077 switch (ARRAY_SIZE (x
.array
))
2080 x
.array
[2] ^= y
.array
[2];
2083 x
.array
[1] ^= y
.array
[1];
2086 x
.array
[0] ^= y
.array
[0];
2094 static const i386_operand_type disp16
= OPERAND_TYPE_DISP16
;
2095 static const i386_operand_type disp32
= OPERAND_TYPE_DISP32
;
2096 static const i386_operand_type disp32s
= OPERAND_TYPE_DISP32S
;
2097 static const i386_operand_type disp16_32
= OPERAND_TYPE_DISP16_32
;
2098 static const i386_operand_type anydisp
= OPERAND_TYPE_ANYDISP
;
2099 static const i386_operand_type anyimm
= OPERAND_TYPE_ANYIMM
;
2100 static const i386_operand_type regxmm
= OPERAND_TYPE_REGXMM
;
2101 static const i386_operand_type regmask
= OPERAND_TYPE_REGMASK
;
2102 static const i386_operand_type imm8
= OPERAND_TYPE_IMM8
;
2103 static const i386_operand_type imm8s
= OPERAND_TYPE_IMM8S
;
2104 static const i386_operand_type imm16
= OPERAND_TYPE_IMM16
;
2105 static const i386_operand_type imm32
= OPERAND_TYPE_IMM32
;
2106 static const i386_operand_type imm32s
= OPERAND_TYPE_IMM32S
;
2107 static const i386_operand_type imm64
= OPERAND_TYPE_IMM64
;
2108 static const i386_operand_type imm16_32
= OPERAND_TYPE_IMM16_32
;
2109 static const i386_operand_type imm16_32s
= OPERAND_TYPE_IMM16_32S
;
2110 static const i386_operand_type imm16_32_32s
= OPERAND_TYPE_IMM16_32_32S
;
2121 operand_type_check (i386_operand_type t
, enum operand_type c
)
2126 return t
.bitfield
.class == Reg
;
2129 return (t
.bitfield
.imm8
2133 || t
.bitfield
.imm32s
2134 || t
.bitfield
.imm64
);
2137 return (t
.bitfield
.disp8
2138 || t
.bitfield
.disp16
2139 || t
.bitfield
.disp32
2140 || t
.bitfield
.disp32s
2141 || t
.bitfield
.disp64
);
2144 return (t
.bitfield
.disp8
2145 || t
.bitfield
.disp16
2146 || t
.bitfield
.disp32
2147 || t
.bitfield
.disp32s
2148 || t
.bitfield
.disp64
2149 || t
.bitfield
.baseindex
);
2158 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit/80bit size
2159 between operand GIVEN and opeand WANTED for instruction template T. */
2162 match_operand_size (const insn_template
*t
, unsigned int wanted
,
2165 return !((i
.types
[given
].bitfield
.byte
2166 && !t
->operand_types
[wanted
].bitfield
.byte
)
2167 || (i
.types
[given
].bitfield
.word
2168 && !t
->operand_types
[wanted
].bitfield
.word
)
2169 || (i
.types
[given
].bitfield
.dword
2170 && !t
->operand_types
[wanted
].bitfield
.dword
)
2171 || (i
.types
[given
].bitfield
.qword
2172 && !t
->operand_types
[wanted
].bitfield
.qword
)
2173 || (i
.types
[given
].bitfield
.tbyte
2174 && !t
->operand_types
[wanted
].bitfield
.tbyte
));
2177 /* Return 1 if there is no conflict in SIMD register between operand
2178 GIVEN and opeand WANTED for instruction template T. */
2181 match_simd_size (const insn_template
*t
, unsigned int wanted
,
2184 return !((i
.types
[given
].bitfield
.xmmword
2185 && !t
->operand_types
[wanted
].bitfield
.xmmword
)
2186 || (i
.types
[given
].bitfield
.ymmword
2187 && !t
->operand_types
[wanted
].bitfield
.ymmword
)
2188 || (i
.types
[given
].bitfield
.zmmword
2189 && !t
->operand_types
[wanted
].bitfield
.zmmword
)
2190 || (i
.types
[given
].bitfield
.tmmword
2191 && !t
->operand_types
[wanted
].bitfield
.tmmword
));
2194 /* Return 1 if there is no conflict in any size between operand GIVEN
2195 and opeand WANTED for instruction template T. */
2198 match_mem_size (const insn_template
*t
, unsigned int wanted
,
2201 return (match_operand_size (t
, wanted
, given
)
2202 && !((i
.types
[given
].bitfield
.unspecified
2203 && !i
.broadcast
.type
2204 && !t
->operand_types
[wanted
].bitfield
.unspecified
)
2205 || (i
.types
[given
].bitfield
.fword
2206 && !t
->operand_types
[wanted
].bitfield
.fword
)
2207 /* For scalar opcode templates to allow register and memory
2208 operands at the same time, some special casing is needed
2209 here. Also for v{,p}broadcast*, {,v}pmov{s,z}*, and
2210 down-conversion vpmov*. */
2211 || ((t
->operand_types
[wanted
].bitfield
.class == RegSIMD
2212 && t
->operand_types
[wanted
].bitfield
.byte
2213 + t
->operand_types
[wanted
].bitfield
.word
2214 + t
->operand_types
[wanted
].bitfield
.dword
2215 + t
->operand_types
[wanted
].bitfield
.qword
2216 > !!t
->opcode_modifier
.broadcast
)
2217 ? (i
.types
[given
].bitfield
.xmmword
2218 || i
.types
[given
].bitfield
.ymmword
2219 || i
.types
[given
].bitfield
.zmmword
)
2220 : !match_simd_size(t
, wanted
, given
))));
2223 /* Return value has MATCH_STRAIGHT set if there is no size conflict on any
2224 operands for instruction template T, and it has MATCH_REVERSE set if there
2225 is no size conflict on any operands for the template with operands reversed
2226 (and the template allows for reversing in the first place). */
2228 #define MATCH_STRAIGHT 1
2229 #define MATCH_REVERSE 2
2231 static INLINE
unsigned int
2232 operand_size_match (const insn_template
*t
)
2234 unsigned int j
, match
= MATCH_STRAIGHT
;
2236 /* Don't check non-absolute jump instructions. */
2237 if (t
->opcode_modifier
.jump
2238 && t
->opcode_modifier
.jump
!= JUMP_ABSOLUTE
)
2241 /* Check memory and accumulator operand size. */
2242 for (j
= 0; j
< i
.operands
; j
++)
2244 if (i
.types
[j
].bitfield
.class != Reg
2245 && i
.types
[j
].bitfield
.class != RegSIMD
2246 && t
->opcode_modifier
.anysize
)
2249 if (t
->operand_types
[j
].bitfield
.class == Reg
2250 && !match_operand_size (t
, j
, j
))
2256 if (t
->operand_types
[j
].bitfield
.class == RegSIMD
2257 && !match_simd_size (t
, j
, j
))
2263 if (t
->operand_types
[j
].bitfield
.instance
== Accum
2264 && (!match_operand_size (t
, j
, j
) || !match_simd_size (t
, j
, j
)))
2270 if ((i
.flags
[j
] & Operand_Mem
) && !match_mem_size (t
, j
, j
))
2277 if (!t
->opcode_modifier
.d
)
2281 i
.error
= operand_size_mismatch
;
2285 /* Check reverse. */
2286 gas_assert (i
.operands
>= 2 && i
.operands
<= 3);
2288 for (j
= 0; j
< i
.operands
; j
++)
2290 unsigned int given
= i
.operands
- j
- 1;
2292 if (t
->operand_types
[j
].bitfield
.class == Reg
2293 && !match_operand_size (t
, j
, given
))
2296 if (t
->operand_types
[j
].bitfield
.class == RegSIMD
2297 && !match_simd_size (t
, j
, given
))
2300 if (t
->operand_types
[j
].bitfield
.instance
== Accum
2301 && (!match_operand_size (t
, j
, given
)
2302 || !match_simd_size (t
, j
, given
)))
2305 if ((i
.flags
[given
] & Operand_Mem
) && !match_mem_size (t
, j
, given
))
2309 return match
| MATCH_REVERSE
;
2313 operand_type_match (i386_operand_type overlap
,
2314 i386_operand_type given
)
2316 i386_operand_type temp
= overlap
;
2318 temp
.bitfield
.unspecified
= 0;
2319 temp
.bitfield
.byte
= 0;
2320 temp
.bitfield
.word
= 0;
2321 temp
.bitfield
.dword
= 0;
2322 temp
.bitfield
.fword
= 0;
2323 temp
.bitfield
.qword
= 0;
2324 temp
.bitfield
.tbyte
= 0;
2325 temp
.bitfield
.xmmword
= 0;
2326 temp
.bitfield
.ymmword
= 0;
2327 temp
.bitfield
.zmmword
= 0;
2328 temp
.bitfield
.tmmword
= 0;
2329 if (operand_type_all_zero (&temp
))
2332 if (given
.bitfield
.baseindex
== overlap
.bitfield
.baseindex
)
2336 i
.error
= operand_type_mismatch
;
2340 /* If given types g0 and g1 are registers they must be of the same type
2341 unless the expected operand type register overlap is null.
2342 Some Intel syntax memory operand size checking also happens here. */
2345 operand_type_register_match (i386_operand_type g0
,
2346 i386_operand_type t0
,
2347 i386_operand_type g1
,
2348 i386_operand_type t1
)
2350 if (g0
.bitfield
.class != Reg
2351 && g0
.bitfield
.class != RegSIMD
2352 && (!operand_type_check (g0
, anymem
)
2353 || g0
.bitfield
.unspecified
2354 || (t0
.bitfield
.class != Reg
2355 && t0
.bitfield
.class != RegSIMD
)))
2358 if (g1
.bitfield
.class != Reg
2359 && g1
.bitfield
.class != RegSIMD
2360 && (!operand_type_check (g1
, anymem
)
2361 || g1
.bitfield
.unspecified
2362 || (t1
.bitfield
.class != Reg
2363 && t1
.bitfield
.class != RegSIMD
)))
2366 if (g0
.bitfield
.byte
== g1
.bitfield
.byte
2367 && g0
.bitfield
.word
== g1
.bitfield
.word
2368 && g0
.bitfield
.dword
== g1
.bitfield
.dword
2369 && g0
.bitfield
.qword
== g1
.bitfield
.qword
2370 && g0
.bitfield
.xmmword
== g1
.bitfield
.xmmword
2371 && g0
.bitfield
.ymmword
== g1
.bitfield
.ymmword
2372 && g0
.bitfield
.zmmword
== g1
.bitfield
.zmmword
)
2375 if (!(t0
.bitfield
.byte
& t1
.bitfield
.byte
)
2376 && !(t0
.bitfield
.word
& t1
.bitfield
.word
)
2377 && !(t0
.bitfield
.dword
& t1
.bitfield
.dword
)
2378 && !(t0
.bitfield
.qword
& t1
.bitfield
.qword
)
2379 && !(t0
.bitfield
.xmmword
& t1
.bitfield
.xmmword
)
2380 && !(t0
.bitfield
.ymmword
& t1
.bitfield
.ymmword
)
2381 && !(t0
.bitfield
.zmmword
& t1
.bitfield
.zmmword
))
2384 i
.error
= register_type_mismatch
;
2389 static INLINE
unsigned int
2390 register_number (const reg_entry
*r
)
2392 unsigned int nr
= r
->reg_num
;
2394 if (r
->reg_flags
& RegRex
)
2397 if (r
->reg_flags
& RegVRex
)
2403 static INLINE
unsigned int
2404 mode_from_disp_size (i386_operand_type t
)
2406 if (t
.bitfield
.disp8
)
2408 else if (t
.bitfield
.disp16
2409 || t
.bitfield
.disp32
2410 || t
.bitfield
.disp32s
)
2417 fits_in_signed_byte (addressT num
)
2419 return num
+ 0x80 <= 0xff;
2423 fits_in_unsigned_byte (addressT num
)
2429 fits_in_unsigned_word (addressT num
)
2431 return num
<= 0xffff;
2435 fits_in_signed_word (addressT num
)
2437 return num
+ 0x8000 <= 0xffff;
2441 fits_in_signed_long (addressT num ATTRIBUTE_UNUSED
)
2446 return num
+ 0x80000000 <= 0xffffffff;
2448 } /* fits_in_signed_long() */
2451 fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED
)
2456 return num
<= 0xffffffff;
2458 } /* fits_in_unsigned_long() */
2460 static INLINE valueT
extend_to_32bit_address (addressT num
)
2463 if (fits_in_unsigned_long(num
))
2464 return (num
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
2466 if (!fits_in_signed_long (num
))
2467 return num
& 0xffffffff;
2474 fits_in_disp8 (offsetT num
)
2476 int shift
= i
.memshift
;
2482 mask
= (1 << shift
) - 1;
2484 /* Return 0 if NUM isn't properly aligned. */
2488 /* Check if NUM will fit in 8bit after shift. */
2489 return fits_in_signed_byte (num
>> shift
);
2493 fits_in_imm4 (offsetT num
)
2495 return (num
& 0xf) == num
;
2498 static i386_operand_type
2499 smallest_imm_type (offsetT num
)
2501 i386_operand_type t
;
2503 operand_type_set (&t
, 0);
2504 t
.bitfield
.imm64
= 1;
2506 if (cpu_arch_tune
!= PROCESSOR_I486
&& num
== 1)
2508 /* This code is disabled on the 486 because all the Imm1 forms
2509 in the opcode table are slower on the i486. They're the
2510 versions with the implicitly specified single-position
2511 displacement, which has another syntax if you really want to
2513 t
.bitfield
.imm1
= 1;
2514 t
.bitfield
.imm8
= 1;
2515 t
.bitfield
.imm8s
= 1;
2516 t
.bitfield
.imm16
= 1;
2517 t
.bitfield
.imm32
= 1;
2518 t
.bitfield
.imm32s
= 1;
2520 else if (fits_in_signed_byte (num
))
2522 t
.bitfield
.imm8
= 1;
2523 t
.bitfield
.imm8s
= 1;
2524 t
.bitfield
.imm16
= 1;
2525 t
.bitfield
.imm32
= 1;
2526 t
.bitfield
.imm32s
= 1;
2528 else if (fits_in_unsigned_byte (num
))
2530 t
.bitfield
.imm8
= 1;
2531 t
.bitfield
.imm16
= 1;
2532 t
.bitfield
.imm32
= 1;
2533 t
.bitfield
.imm32s
= 1;
2535 else if (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
2537 t
.bitfield
.imm16
= 1;
2538 t
.bitfield
.imm32
= 1;
2539 t
.bitfield
.imm32s
= 1;
2541 else if (fits_in_signed_long (num
))
2543 t
.bitfield
.imm32
= 1;
2544 t
.bitfield
.imm32s
= 1;
2546 else if (fits_in_unsigned_long (num
))
2547 t
.bitfield
.imm32
= 1;
2553 offset_in_range (offsetT val
, int size
)
2559 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
2560 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
2561 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
2563 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
2568 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
2570 char buf1
[40], buf2
[40];
2572 bfd_sprintf_vma (stdoutput
, buf1
, val
);
2573 bfd_sprintf_vma (stdoutput
, buf2
, val
& mask
);
2574 as_warn (_("%s shortened to %s"), buf1
, buf2
);
2589 a. PREFIX_EXIST if attempting to add a prefix where one from the
2590 same class already exists.
2591 b. PREFIX_LOCK if lock prefix is added.
2592 c. PREFIX_REP if rep/repne prefix is added.
2593 d. PREFIX_DS if ds prefix is added.
2594 e. PREFIX_OTHER if other prefix is added.
2597 static enum PREFIX_GROUP
2598 add_prefix (unsigned int prefix
)
2600 enum PREFIX_GROUP ret
= PREFIX_OTHER
;
2603 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
2604 && flag_code
== CODE_64BIT
)
2606 if ((i
.prefix
[REX_PREFIX
] & prefix
& REX_W
)
2607 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_R
)
2608 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_X
)
2609 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_B
))
2620 case DS_PREFIX_OPCODE
:
2623 case CS_PREFIX_OPCODE
:
2624 case ES_PREFIX_OPCODE
:
2625 case FS_PREFIX_OPCODE
:
2626 case GS_PREFIX_OPCODE
:
2627 case SS_PREFIX_OPCODE
:
2631 case REPNE_PREFIX_OPCODE
:
2632 case REPE_PREFIX_OPCODE
:
2637 case LOCK_PREFIX_OPCODE
:
2646 case ADDR_PREFIX_OPCODE
:
2650 case DATA_PREFIX_OPCODE
:
2654 if (i
.prefix
[q
] != 0)
2662 i
.prefix
[q
] |= prefix
;
2665 as_bad (_("same type of prefix used twice"));
2671 update_code_flag (int value
, int check
)
2673 PRINTF_LIKE ((*as_error
));
2675 flag_code
= (enum flag_code
) value
;
2676 if (flag_code
== CODE_64BIT
)
2678 cpu_arch_flags
.bitfield
.cpu64
= 1;
2679 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2683 cpu_arch_flags
.bitfield
.cpu64
= 0;
2684 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2686 if (value
== CODE_64BIT
&& !cpu_arch_flags
.bitfield
.cpulm
)
2689 as_error
= as_fatal
;
2692 (*as_error
) (_("64bit mode not supported on `%s'."),
2693 cpu_arch_name
? cpu_arch_name
: default_arch
);
2695 if (value
== CODE_32BIT
&& !cpu_arch_flags
.bitfield
.cpui386
)
2698 as_error
= as_fatal
;
2701 (*as_error
) (_("32bit mode not supported on `%s'."),
2702 cpu_arch_name
? cpu_arch_name
: default_arch
);
2704 stackop_size
= '\0';
2708 set_code_flag (int value
)
2710 update_code_flag (value
, 0);
2714 set_16bit_gcc_code_flag (int new_code_flag
)
2716 flag_code
= (enum flag_code
) new_code_flag
;
2717 if (flag_code
!= CODE_16BIT
)
2719 cpu_arch_flags
.bitfield
.cpu64
= 0;
2720 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2721 stackop_size
= LONG_MNEM_SUFFIX
;
2725 set_intel_syntax (int syntax_flag
)
2727 /* Find out if register prefixing is specified. */
2728 int ask_naked_reg
= 0;
2731 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2734 int e
= get_symbol_name (&string
);
2736 if (strcmp (string
, "prefix") == 0)
2738 else if (strcmp (string
, "noprefix") == 0)
2741 as_bad (_("bad argument to syntax directive."));
2742 (void) restore_line_pointer (e
);
2744 demand_empty_rest_of_line ();
2746 intel_syntax
= syntax_flag
;
2748 if (ask_naked_reg
== 0)
2749 allow_naked_reg
= (intel_syntax
2750 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
2752 allow_naked_reg
= (ask_naked_reg
< 0);
2754 expr_set_rank (O_full_ptr
, syntax_flag
? 10 : 0);
2756 identifier_chars
['%'] = intel_syntax
&& allow_naked_reg
? '%' : 0;
2757 identifier_chars
['$'] = intel_syntax
? '$' : 0;
2758 register_prefix
= allow_naked_reg
? "" : "%";
2762 set_intel_mnemonic (int mnemonic_flag
)
2764 intel_mnemonic
= mnemonic_flag
;
2768 set_allow_index_reg (int flag
)
2770 allow_index_reg
= flag
;
2774 set_check (int what
)
2776 enum check_kind
*kind
;
2781 kind
= &operand_check
;
2792 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2795 int e
= get_symbol_name (&string
);
2797 if (strcmp (string
, "none") == 0)
2799 else if (strcmp (string
, "warning") == 0)
2800 *kind
= check_warning
;
2801 else if (strcmp (string
, "error") == 0)
2802 *kind
= check_error
;
2804 as_bad (_("bad argument to %s_check directive."), str
);
2805 (void) restore_line_pointer (e
);
2808 as_bad (_("missing argument for %s_check directive"), str
);
2810 demand_empty_rest_of_line ();
2814 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED
,
2815 i386_cpu_flags new_flag ATTRIBUTE_UNUSED
)
2817 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2818 static const char *arch
;
2820 /* Intel LIOM is only supported on ELF. */
2826 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2827 use default_arch. */
2828 arch
= cpu_arch_name
;
2830 arch
= default_arch
;
2833 /* If we are targeting Intel MCU, we must enable it. */
2834 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_IAMCU
2835 || new_flag
.bitfield
.cpuiamcu
)
2838 /* If we are targeting Intel L1OM, we must enable it. */
2839 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_L1OM
2840 || new_flag
.bitfield
.cpul1om
)
2843 /* If we are targeting Intel K1OM, we must enable it. */
2844 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_K1OM
2845 || new_flag
.bitfield
.cpuk1om
)
2848 as_bad (_("`%s' is not supported on `%s'"), name
, arch
);
2853 set_cpu_arch (int dummy ATTRIBUTE_UNUSED
)
2857 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2860 int e
= get_symbol_name (&string
);
2862 i386_cpu_flags flags
;
2864 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
2866 if (strcmp (string
, cpu_arch
[j
].name
) == 0)
2868 check_cpu_arch_compatible (string
, cpu_arch
[j
].flags
);
2872 cpu_arch_name
= cpu_arch
[j
].name
;
2873 cpu_sub_arch_name
= NULL
;
2874 cpu_arch_flags
= cpu_arch
[j
].flags
;
2875 if (flag_code
== CODE_64BIT
)
2877 cpu_arch_flags
.bitfield
.cpu64
= 1;
2878 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2882 cpu_arch_flags
.bitfield
.cpu64
= 0;
2883 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2885 cpu_arch_isa
= cpu_arch
[j
].type
;
2886 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
2887 if (!cpu_arch_tune_set
)
2889 cpu_arch_tune
= cpu_arch_isa
;
2890 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
2895 flags
= cpu_flags_or (cpu_arch_flags
,
2898 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2900 if (cpu_sub_arch_name
)
2902 char *name
= cpu_sub_arch_name
;
2903 cpu_sub_arch_name
= concat (name
,
2905 (const char *) NULL
);
2909 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
2910 cpu_arch_flags
= flags
;
2911 cpu_arch_isa_flags
= flags
;
2915 = cpu_flags_or (cpu_arch_isa_flags
,
2917 (void) restore_line_pointer (e
);
2918 demand_empty_rest_of_line ();
2923 if (*string
== '.' && j
>= ARRAY_SIZE (cpu_arch
))
2925 /* Disable an ISA extension. */
2926 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
2927 if (strcmp (string
+ 1, cpu_noarch
[j
].name
) == 0)
2929 flags
= cpu_flags_and_not (cpu_arch_flags
,
2930 cpu_noarch
[j
].flags
);
2931 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2933 if (cpu_sub_arch_name
)
2935 char *name
= cpu_sub_arch_name
;
2936 cpu_sub_arch_name
= concat (name
, string
,
2937 (const char *) NULL
);
2941 cpu_sub_arch_name
= xstrdup (string
);
2942 cpu_arch_flags
= flags
;
2943 cpu_arch_isa_flags
= flags
;
2945 (void) restore_line_pointer (e
);
2946 demand_empty_rest_of_line ();
2950 j
= ARRAY_SIZE (cpu_arch
);
2953 if (j
>= ARRAY_SIZE (cpu_arch
))
2954 as_bad (_("no such architecture: `%s'"), string
);
2956 *input_line_pointer
= e
;
2959 as_bad (_("missing cpu architecture"));
2961 no_cond_jump_promotion
= 0;
2962 if (*input_line_pointer
== ','
2963 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
2968 ++input_line_pointer
;
2969 e
= get_symbol_name (&string
);
2971 if (strcmp (string
, "nojumps") == 0)
2972 no_cond_jump_promotion
= 1;
2973 else if (strcmp (string
, "jumps") == 0)
2976 as_bad (_("no such architecture modifier: `%s'"), string
);
2978 (void) restore_line_pointer (e
);
2981 demand_empty_rest_of_line ();
2984 enum bfd_architecture
2987 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2989 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2990 || flag_code
!= CODE_64BIT
)
2991 as_fatal (_("Intel L1OM is 64bit ELF only"));
2992 return bfd_arch_l1om
;
2994 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2996 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2997 || flag_code
!= CODE_64BIT
)
2998 as_fatal (_("Intel K1OM is 64bit ELF only"));
2999 return bfd_arch_k1om
;
3001 else if (cpu_arch_isa
== PROCESSOR_IAMCU
)
3003 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
3004 || flag_code
== CODE_64BIT
)
3005 as_fatal (_("Intel MCU is 32bit ELF only"));
3006 return bfd_arch_iamcu
;
3009 return bfd_arch_i386
;
3015 if (startswith (default_arch
, "x86_64"))
3017 if (cpu_arch_isa
== PROCESSOR_L1OM
)
3019 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
3020 || default_arch
[6] != '\0')
3021 as_fatal (_("Intel L1OM is 64bit ELF only"));
3022 return bfd_mach_l1om
;
3024 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
3026 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
3027 || default_arch
[6] != '\0')
3028 as_fatal (_("Intel K1OM is 64bit ELF only"));
3029 return bfd_mach_k1om
;
3031 else if (default_arch
[6] == '\0')
3032 return bfd_mach_x86_64
;
3034 return bfd_mach_x64_32
;
3036 else if (!strcmp (default_arch
, "i386")
3037 || !strcmp (default_arch
, "iamcu"))
3039 if (cpu_arch_isa
== PROCESSOR_IAMCU
)
3041 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
3042 as_fatal (_("Intel MCU is 32bit ELF only"));
3043 return bfd_mach_i386_iamcu
;
3046 return bfd_mach_i386_i386
;
3049 as_fatal (_("unknown architecture"));
3055 /* Support pseudo prefixes like {disp32}. */
3056 lex_type
['{'] = LEX_BEGIN_NAME
;
3058 /* Initialize op_hash hash table. */
3059 op_hash
= str_htab_create ();
3062 const insn_template
*optab
;
3063 templates
*core_optab
;
3065 /* Setup for loop. */
3067 core_optab
= XNEW (templates
);
3068 core_optab
->start
= optab
;
3073 if (optab
->name
== NULL
3074 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
3076 /* different name --> ship out current template list;
3077 add to hash table; & begin anew. */
3078 core_optab
->end
= optab
;
3079 if (str_hash_insert (op_hash
, (optab
- 1)->name
, core_optab
, 0))
3080 as_fatal (_("duplicate %s"), (optab
- 1)->name
);
3082 if (optab
->name
== NULL
)
3084 core_optab
= XNEW (templates
);
3085 core_optab
->start
= optab
;
3090 /* Initialize reg_hash hash table. */
3091 reg_hash
= str_htab_create ();
3093 const reg_entry
*regtab
;
3094 unsigned int regtab_size
= i386_regtab_size
;
3096 for (regtab
= i386_regtab
; regtab_size
--; regtab
++)
3098 switch (regtab
->reg_type
.bitfield
.class)
3101 if (regtab
->reg_type
.bitfield
.dword
)
3103 if (regtab
->reg_type
.bitfield
.instance
== Accum
)
3106 else if (regtab
->reg_type
.bitfield
.tbyte
)
3108 /* There's no point inserting st(<N>) in the hash table, as
3109 parentheses aren't included in register_chars[] anyway. */
3110 if (regtab
->reg_type
.bitfield
.instance
!= Accum
)
3117 switch (regtab
->reg_num
)
3119 case 0: reg_es
= regtab
; break;
3120 case 2: reg_ss
= regtab
; break;
3121 case 3: reg_ds
= regtab
; break;
3126 if (!regtab
->reg_num
)
3131 if (str_hash_insert (reg_hash
, regtab
->reg_name
, regtab
, 0) != NULL
)
3132 as_fatal (_("duplicate %s"), regtab
->reg_name
);
3136 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
3141 for (c
= 0; c
< 256; c
++)
3146 mnemonic_chars
[c
] = c
;
3147 register_chars
[c
] = c
;
3148 operand_chars
[c
] = c
;
3150 else if (ISLOWER (c
))
3152 mnemonic_chars
[c
] = c
;
3153 register_chars
[c
] = c
;
3154 operand_chars
[c
] = c
;
3156 else if (ISUPPER (c
))
3158 mnemonic_chars
[c
] = TOLOWER (c
);
3159 register_chars
[c
] = mnemonic_chars
[c
];
3160 operand_chars
[c
] = c
;
3162 else if (c
== '{' || c
== '}')
3164 mnemonic_chars
[c
] = c
;
3165 operand_chars
[c
] = c
;
3167 #ifdef SVR4_COMMENT_CHARS
3168 else if (c
== '\\' && strchr (i386_comment_chars
, '/'))
3169 operand_chars
[c
] = c
;
3172 if (ISALPHA (c
) || ISDIGIT (c
))
3173 identifier_chars
[c
] = c
;
3176 identifier_chars
[c
] = c
;
3177 operand_chars
[c
] = c
;
3182 identifier_chars
['@'] = '@';
3185 identifier_chars
['?'] = '?';
3186 operand_chars
['?'] = '?';
3188 digit_chars
['-'] = '-';
3189 mnemonic_chars
['_'] = '_';
3190 mnemonic_chars
['-'] = '-';
3191 mnemonic_chars
['.'] = '.';
3192 identifier_chars
['_'] = '_';
3193 identifier_chars
['.'] = '.';
3195 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
3196 operand_chars
[(unsigned char) *p
] = *p
;
3199 if (flag_code
== CODE_64BIT
)
3201 #if defined (OBJ_COFF) && defined (TE_PE)
3202 x86_dwarf2_return_column
= (OUTPUT_FLAVOR
== bfd_target_coff_flavour
3205 x86_dwarf2_return_column
= 16;
3207 x86_cie_data_alignment
= -8;
3211 x86_dwarf2_return_column
= 8;
3212 x86_cie_data_alignment
= -4;
3215 /* NB: FUSED_JCC_PADDING frag must have sufficient room so that it
3216 can be turned into BRANCH_PREFIX frag. */
3217 if (align_branch_prefix_size
> MAX_FUSED_JCC_PADDING_SIZE
)
3222 i386_print_statistics (FILE *file
)
3224 htab_print_statistics (file
, "i386 opcode", op_hash
);
3225 htab_print_statistics (file
, "i386 register", reg_hash
);
3230 /* Debugging routines for md_assemble. */
3231 static void pte (insn_template
*);
3232 static void pt (i386_operand_type
);
3233 static void pe (expressionS
*);
3234 static void ps (symbolS
*);
3237 pi (const char *line
, i386_insn
*x
)
3241 fprintf (stdout
, "%s: template ", line
);
3243 fprintf (stdout
, " address: base %s index %s scale %x\n",
3244 x
->base_reg
? x
->base_reg
->reg_name
: "none",
3245 x
->index_reg
? x
->index_reg
->reg_name
: "none",
3246 x
->log2_scale_factor
);
3247 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
3248 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
3249 fprintf (stdout
, " sib: base %x index %x scale %x\n",
3250 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
3251 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
3252 (x
->rex
& REX_W
) != 0,
3253 (x
->rex
& REX_R
) != 0,
3254 (x
->rex
& REX_X
) != 0,
3255 (x
->rex
& REX_B
) != 0);
3256 for (j
= 0; j
< x
->operands
; j
++)
3258 fprintf (stdout
, " #%d: ", j
+ 1);
3260 fprintf (stdout
, "\n");
3261 if (x
->types
[j
].bitfield
.class == Reg
3262 || x
->types
[j
].bitfield
.class == RegMMX
3263 || x
->types
[j
].bitfield
.class == RegSIMD
3264 || x
->types
[j
].bitfield
.class == RegMask
3265 || x
->types
[j
].bitfield
.class == SReg
3266 || x
->types
[j
].bitfield
.class == RegCR
3267 || x
->types
[j
].bitfield
.class == RegDR
3268 || x
->types
[j
].bitfield
.class == RegTR
3269 || x
->types
[j
].bitfield
.class == RegBND
)
3270 fprintf (stdout
, "%s\n", x
->op
[j
].regs
->reg_name
);
3271 if (operand_type_check (x
->types
[j
], imm
))
3273 if (operand_type_check (x
->types
[j
], disp
))
3274 pe (x
->op
[j
].disps
);
3279 pte (insn_template
*t
)
3281 static const unsigned char opc_pfx
[] = { 0, 0x66, 0xf3, 0xf2 };
3282 static const char *const opc_spc
[] = {
3283 NULL
, "0f", "0f38", "0f3a", NULL
, NULL
, NULL
, NULL
,
3284 "XOP08", "XOP09", "XOP0A",
3288 fprintf (stdout
, " %d operands ", t
->operands
);
3289 if (opc_pfx
[t
->opcode_modifier
.opcodeprefix
])
3290 fprintf (stdout
, "pfx %x ", opc_pfx
[t
->opcode_modifier
.opcodeprefix
]);
3291 if (opc_spc
[t
->opcode_modifier
.opcodespace
])
3292 fprintf (stdout
, "space %s ", opc_spc
[t
->opcode_modifier
.opcodespace
]);
3293 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
3294 if (t
->extension_opcode
!= None
)
3295 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
3296 if (t
->opcode_modifier
.d
)
3297 fprintf (stdout
, "D");
3298 if (t
->opcode_modifier
.w
)
3299 fprintf (stdout
, "W");
3300 fprintf (stdout
, "\n");
3301 for (j
= 0; j
< t
->operands
; j
++)
3303 fprintf (stdout
, " #%d type ", j
+ 1);
3304 pt (t
->operand_types
[j
]);
3305 fprintf (stdout
, "\n");
3312 fprintf (stdout
, " operation %d\n", e
->X_op
);
3313 fprintf (stdout
, " add_number %" BFD_VMA_FMT
"d (%" BFD_VMA_FMT
"x)\n",
3314 e
->X_add_number
, e
->X_add_number
);
3315 if (e
->X_add_symbol
)
3317 fprintf (stdout
, " add_symbol ");
3318 ps (e
->X_add_symbol
);
3319 fprintf (stdout
, "\n");
3323 fprintf (stdout
, " op_symbol ");
3324 ps (e
->X_op_symbol
);
3325 fprintf (stdout
, "\n");
3332 fprintf (stdout
, "%s type %s%s",
3334 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
3335 segment_name (S_GET_SEGMENT (s
)));
3338 static struct type_name
3340 i386_operand_type mask
;
3343 const type_names
[] =
3345 { OPERAND_TYPE_REG8
, "r8" },
3346 { OPERAND_TYPE_REG16
, "r16" },
3347 { OPERAND_TYPE_REG32
, "r32" },
3348 { OPERAND_TYPE_REG64
, "r64" },
3349 { OPERAND_TYPE_ACC8
, "acc8" },
3350 { OPERAND_TYPE_ACC16
, "acc16" },
3351 { OPERAND_TYPE_ACC32
, "acc32" },
3352 { OPERAND_TYPE_ACC64
, "acc64" },
3353 { OPERAND_TYPE_IMM8
, "i8" },
3354 { OPERAND_TYPE_IMM8
, "i8s" },
3355 { OPERAND_TYPE_IMM16
, "i16" },
3356 { OPERAND_TYPE_IMM32
, "i32" },
3357 { OPERAND_TYPE_IMM32S
, "i32s" },
3358 { OPERAND_TYPE_IMM64
, "i64" },
3359 { OPERAND_TYPE_IMM1
, "i1" },
3360 { OPERAND_TYPE_BASEINDEX
, "BaseIndex" },
3361 { OPERAND_TYPE_DISP8
, "d8" },
3362 { OPERAND_TYPE_DISP16
, "d16" },
3363 { OPERAND_TYPE_DISP32
, "d32" },
3364 { OPERAND_TYPE_DISP32S
, "d32s" },
3365 { OPERAND_TYPE_DISP64
, "d64" },
3366 { OPERAND_TYPE_INOUTPORTREG
, "InOutPortReg" },
3367 { OPERAND_TYPE_SHIFTCOUNT
, "ShiftCount" },
3368 { OPERAND_TYPE_CONTROL
, "control reg" },
3369 { OPERAND_TYPE_TEST
, "test reg" },
3370 { OPERAND_TYPE_DEBUG
, "debug reg" },
3371 { OPERAND_TYPE_FLOATREG
, "FReg" },
3372 { OPERAND_TYPE_FLOATACC
, "FAcc" },
3373 { OPERAND_TYPE_SREG
, "SReg" },
3374 { OPERAND_TYPE_REGMMX
, "rMMX" },
3375 { OPERAND_TYPE_REGXMM
, "rXMM" },
3376 { OPERAND_TYPE_REGYMM
, "rYMM" },
3377 { OPERAND_TYPE_REGZMM
, "rZMM" },
3378 { OPERAND_TYPE_REGTMM
, "rTMM" },
3379 { OPERAND_TYPE_REGMASK
, "Mask reg" },
3383 pt (i386_operand_type t
)
3386 i386_operand_type a
;
3388 for (j
= 0; j
< ARRAY_SIZE (type_names
); j
++)
3390 a
= operand_type_and (t
, type_names
[j
].mask
);
3391 if (operand_type_equal (&a
, &type_names
[j
].mask
))
3392 fprintf (stdout
, "%s, ", type_names
[j
].name
);
3397 #endif /* DEBUG386 */
3399 static bfd_reloc_code_real_type
3400 reloc (unsigned int size
,
3403 bfd_reloc_code_real_type other
)
3405 if (other
!= NO_RELOC
)
3407 reloc_howto_type
*rel
;
3412 case BFD_RELOC_X86_64_GOT32
:
3413 return BFD_RELOC_X86_64_GOT64
;
3415 case BFD_RELOC_X86_64_GOTPLT64
:
3416 return BFD_RELOC_X86_64_GOTPLT64
;
3418 case BFD_RELOC_X86_64_PLTOFF64
:
3419 return BFD_RELOC_X86_64_PLTOFF64
;
3421 case BFD_RELOC_X86_64_GOTPC32
:
3422 other
= BFD_RELOC_X86_64_GOTPC64
;
3424 case BFD_RELOC_X86_64_GOTPCREL
:
3425 other
= BFD_RELOC_X86_64_GOTPCREL64
;
3427 case BFD_RELOC_X86_64_TPOFF32
:
3428 other
= BFD_RELOC_X86_64_TPOFF64
;
3430 case BFD_RELOC_X86_64_DTPOFF32
:
3431 other
= BFD_RELOC_X86_64_DTPOFF64
;
3437 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3438 if (other
== BFD_RELOC_SIZE32
)
3441 other
= BFD_RELOC_SIZE64
;
3444 as_bad (_("there are no pc-relative size relocations"));
3450 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
3451 if (size
== 4 && (flag_code
!= CODE_64BIT
|| disallow_64bit_reloc
))
3454 rel
= bfd_reloc_type_lookup (stdoutput
, other
);
3456 as_bad (_("unknown relocation (%u)"), other
);
3457 else if (size
!= bfd_get_reloc_size (rel
))
3458 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
3459 bfd_get_reloc_size (rel
),
3461 else if (pcrel
&& !rel
->pc_relative
)
3462 as_bad (_("non-pc-relative relocation for pc-relative field"));
3463 else if ((rel
->complain_on_overflow
== complain_overflow_signed
3465 || (rel
->complain_on_overflow
== complain_overflow_unsigned
3467 as_bad (_("relocated field and relocation type differ in signedness"));
3476 as_bad (_("there are no unsigned pc-relative relocations"));
3479 case 1: return BFD_RELOC_8_PCREL
;
3480 case 2: return BFD_RELOC_16_PCREL
;
3481 case 4: return BFD_RELOC_32_PCREL
;
3482 case 8: return BFD_RELOC_64_PCREL
;
3484 as_bad (_("cannot do %u byte pc-relative relocation"), size
);
3491 case 4: return BFD_RELOC_X86_64_32S
;
3496 case 1: return BFD_RELOC_8
;
3497 case 2: return BFD_RELOC_16
;
3498 case 4: return BFD_RELOC_32
;
3499 case 8: return BFD_RELOC_64
;
3501 as_bad (_("cannot do %s %u byte relocation"),
3502 sign
> 0 ? "signed" : "unsigned", size
);
3508 /* Here we decide which fixups can be adjusted to make them relative to
3509 the beginning of the section instead of the symbol. Basically we need
3510 to make sure that the dynamic relocations are done correctly, so in
3511 some cases we force the original symbol to be used. */
3514 tc_i386_fix_adjustable (fixS
*fixP ATTRIBUTE_UNUSED
)
3516 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3520 /* Don't adjust pc-relative references to merge sections in 64-bit
3522 if (use_rela_relocations
3523 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
3527 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
3528 and changed later by validate_fix. */
3529 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
3530 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
3533 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
3534 for size relocations. */
3535 if (fixP
->fx_r_type
== BFD_RELOC_SIZE32
3536 || fixP
->fx_r_type
== BFD_RELOC_SIZE64
3537 || fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
3538 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
3539 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32X
3540 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
3541 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
3542 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
3543 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
3544 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
3545 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
3546 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
3547 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
3548 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTDESC
3549 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_DESC_CALL
3550 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
3551 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
3552 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCRELX
3553 || fixP
->fx_r_type
== BFD_RELOC_X86_64_REX_GOTPCRELX
3554 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
3555 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
3556 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
3557 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
3558 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
3559 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
3560 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
3561 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
3562 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPC32_TLSDESC
3563 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSDESC_CALL
3564 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
3565 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
3572 want_disp32 (const insn_template
*t
)
3574 return flag_code
!= CODE_64BIT
3575 || i
.prefix
[ADDR_PREFIX
]
3576 || (t
->base_opcode
== 0x8d
3577 && t
->opcode_modifier
.opcodespace
== SPACE_BASE
3578 && (!i
.types
[1].bitfield
.qword
3579 || t
->opcode_modifier
.size
== SIZE32
));
3583 intel_float_operand (const char *mnemonic
)
3585 /* Note that the value returned is meaningful only for opcodes with (memory)
3586 operands, hence the code here is free to improperly handle opcodes that
3587 have no operands (for better performance and smaller code). */
3589 if (mnemonic
[0] != 'f')
3590 return 0; /* non-math */
3592 switch (mnemonic
[1])
3594 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
3595 the fs segment override prefix not currently handled because no
3596 call path can make opcodes without operands get here */
3598 return 2 /* integer op */;
3600 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
3601 return 3; /* fldcw/fldenv */
3604 if (mnemonic
[2] != 'o' /* fnop */)
3605 return 3; /* non-waiting control op */
3608 if (mnemonic
[2] == 's')
3609 return 3; /* frstor/frstpm */
3612 if (mnemonic
[2] == 'a')
3613 return 3; /* fsave */
3614 if (mnemonic
[2] == 't')
3616 switch (mnemonic
[3])
3618 case 'c': /* fstcw */
3619 case 'd': /* fstdw */
3620 case 'e': /* fstenv */
3621 case 's': /* fsts[gw] */
3627 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
3628 return 0; /* fxsave/fxrstor are not really math ops */
3636 install_template (const insn_template
*t
)
3642 /* Note that for pseudo prefixes this produces a length of 1. But for them
3643 the length isn't interesting at all. */
3644 for (l
= 1; l
< 4; ++l
)
3645 if (!(t
->base_opcode
>> (8 * l
)))
3648 i
.opcode_length
= l
;
3651 /* Build the VEX prefix. */
3654 build_vex_prefix (const insn_template
*t
)
3656 unsigned int register_specifier
;
3657 unsigned int vector_length
;
3660 /* Check register specifier. */
3661 if (i
.vex
.register_specifier
)
3663 register_specifier
=
3664 ~register_number (i
.vex
.register_specifier
) & 0xf;
3665 gas_assert ((i
.vex
.register_specifier
->reg_flags
& RegVRex
) == 0);
3668 register_specifier
= 0xf;
3670 /* Use 2-byte VEX prefix by swapping destination and source operand
3671 if there are more than 1 register operand. */
3672 if (i
.reg_operands
> 1
3673 && i
.vec_encoding
!= vex_encoding_vex3
3674 && i
.dir_encoding
== dir_encoding_default
3675 && i
.operands
== i
.reg_operands
3676 && operand_type_equal (&i
.types
[0], &i
.types
[i
.operands
- 1])
3677 && i
.tm
.opcode_modifier
.opcodespace
== SPACE_0F
3678 && (i
.tm
.opcode_modifier
.load
|| i
.tm
.opcode_modifier
.d
)
3681 unsigned int xchg
= i
.operands
- 1;
3682 union i386_op temp_op
;
3683 i386_operand_type temp_type
;
3685 temp_type
= i
.types
[xchg
];
3686 i
.types
[xchg
] = i
.types
[0];
3687 i
.types
[0] = temp_type
;
3688 temp_op
= i
.op
[xchg
];
3689 i
.op
[xchg
] = i
.op
[0];
3692 gas_assert (i
.rm
.mode
== 3);
3696 i
.rm
.regmem
= i
.rm
.reg
;
3699 if (i
.tm
.opcode_modifier
.d
)
3700 i
.tm
.base_opcode
^= (i
.tm
.base_opcode
& 0xee) != 0x6e
3701 ? Opcode_SIMD_FloatD
: Opcode_SIMD_IntD
;
3702 else /* Use the next insn. */
3703 install_template (&t
[1]);
3706 /* Use 2-byte VEX prefix by swapping commutative source operands if there
3707 are no memory operands and at least 3 register ones. */
3708 if (i
.reg_operands
>= 3
3709 && i
.vec_encoding
!= vex_encoding_vex3
3710 && i
.reg_operands
== i
.operands
- i
.imm_operands
3711 && i
.tm
.opcode_modifier
.vex
3712 && i
.tm
.opcode_modifier
.commutative
3713 && (i
.tm
.opcode_modifier
.sse2avx
|| optimize
> 1)
3715 && i
.vex
.register_specifier
3716 && !(i
.vex
.register_specifier
->reg_flags
& RegRex
))
3718 unsigned int xchg
= i
.operands
- i
.reg_operands
;
3719 union i386_op temp_op
;
3720 i386_operand_type temp_type
;
3722 gas_assert (i
.tm
.opcode_modifier
.opcodespace
== SPACE_0F
);
3723 gas_assert (!i
.tm
.opcode_modifier
.sae
);
3724 gas_assert (operand_type_equal (&i
.types
[i
.operands
- 2],
3725 &i
.types
[i
.operands
- 3]));
3726 gas_assert (i
.rm
.mode
== 3);
3728 temp_type
= i
.types
[xchg
];
3729 i
.types
[xchg
] = i
.types
[xchg
+ 1];
3730 i
.types
[xchg
+ 1] = temp_type
;
3731 temp_op
= i
.op
[xchg
];
3732 i
.op
[xchg
] = i
.op
[xchg
+ 1];
3733 i
.op
[xchg
+ 1] = temp_op
;
3736 xchg
= i
.rm
.regmem
| 8;
3737 i
.rm
.regmem
= ~register_specifier
& 0xf;
3738 gas_assert (!(i
.rm
.regmem
& 8));
3739 i
.vex
.register_specifier
+= xchg
- i
.rm
.regmem
;
3740 register_specifier
= ~xchg
& 0xf;
3743 if (i
.tm
.opcode_modifier
.vex
== VEXScalar
)
3744 vector_length
= avxscalar
;
3745 else if (i
.tm
.opcode_modifier
.vex
== VEX256
)
3751 /* Determine vector length from the last multi-length vector
3754 for (op
= t
->operands
; op
--;)
3755 if (t
->operand_types
[op
].bitfield
.xmmword
3756 && t
->operand_types
[op
].bitfield
.ymmword
3757 && i
.types
[op
].bitfield
.ymmword
)
3764 /* Check the REX.W bit and VEXW. */
3765 if (i
.tm
.opcode_modifier
.vexw
== VEXWIG
)
3766 w
= (vexwig
== vexw1
|| (i
.rex
& REX_W
)) ? 1 : 0;
3767 else if (i
.tm
.opcode_modifier
.vexw
)
3768 w
= i
.tm
.opcode_modifier
.vexw
== VEXW1
? 1 : 0;
3770 w
= (flag_code
== CODE_64BIT
? i
.rex
& REX_W
: vexwig
== vexw1
) ? 1 : 0;
3772 /* Use 2-byte VEX prefix if possible. */
3774 && i
.vec_encoding
!= vex_encoding_vex3
3775 && i
.tm
.opcode_modifier
.opcodespace
== SPACE_0F
3776 && (i
.rex
& (REX_W
| REX_X
| REX_B
)) == 0)
3778 /* 2-byte VEX prefix. */
3782 i
.vex
.bytes
[0] = 0xc5;
3784 /* Check the REX.R bit. */
3785 r
= (i
.rex
& REX_R
) ? 0 : 1;
3786 i
.vex
.bytes
[1] = (r
<< 7
3787 | register_specifier
<< 3
3788 | vector_length
<< 2
3789 | i
.tm
.opcode_modifier
.opcodeprefix
);
3793 /* 3-byte VEX prefix. */
3796 switch (i
.tm
.opcode_modifier
.opcodespace
)
3801 i
.vex
.bytes
[0] = 0xc4;
3806 i
.vex
.bytes
[0] = 0x8f;
3812 /* The high 3 bits of the second VEX byte are 1's compliment
3813 of RXB bits from REX. */
3814 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | i
.tm
.opcode_modifier
.opcodespace
;
3816 i
.vex
.bytes
[2] = (w
<< 7
3817 | register_specifier
<< 3
3818 | vector_length
<< 2
3819 | i
.tm
.opcode_modifier
.opcodeprefix
);
3824 is_evex_encoding (const insn_template
*t
)
3826 return t
->opcode_modifier
.evex
|| t
->opcode_modifier
.disp8memshift
3827 || t
->opcode_modifier
.broadcast
|| t
->opcode_modifier
.masking
3828 || t
->opcode_modifier
.sae
;
3832 is_any_vex_encoding (const insn_template
*t
)
3834 return t
->opcode_modifier
.vex
|| is_evex_encoding (t
);
3837 /* Build the EVEX prefix. */
3840 build_evex_prefix (void)
3842 unsigned int register_specifier
, w
;
3843 rex_byte vrex_used
= 0;
3845 /* Check register specifier. */
3846 if (i
.vex
.register_specifier
)
3848 gas_assert ((i
.vrex
& REX_X
) == 0);
3850 register_specifier
= i
.vex
.register_specifier
->reg_num
;
3851 if ((i
.vex
.register_specifier
->reg_flags
& RegRex
))
3852 register_specifier
+= 8;
3853 /* The upper 16 registers are encoded in the fourth byte of the
3855 if (!(i
.vex
.register_specifier
->reg_flags
& RegVRex
))
3856 i
.vex
.bytes
[3] = 0x8;
3857 register_specifier
= ~register_specifier
& 0xf;
3861 register_specifier
= 0xf;
3863 /* Encode upper 16 vector index register in the fourth byte of
3865 if (!(i
.vrex
& REX_X
))
3866 i
.vex
.bytes
[3] = 0x8;
3871 /* 4 byte EVEX prefix. */
3873 i
.vex
.bytes
[0] = 0x62;
3875 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3877 gas_assert (i
.tm
.opcode_modifier
.opcodespace
>= SPACE_0F
);
3878 gas_assert (i
.tm
.opcode_modifier
.opcodespace
<= SPACE_0F3A
);
3879 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | i
.tm
.opcode_modifier
.opcodespace
;
3881 /* The fifth bit of the second EVEX byte is 1's compliment of the
3882 REX_R bit in VREX. */
3883 if (!(i
.vrex
& REX_R
))
3884 i
.vex
.bytes
[1] |= 0x10;
3888 if ((i
.reg_operands
+ i
.imm_operands
) == i
.operands
)
3890 /* When all operands are registers, the REX_X bit in REX is not
3891 used. We reuse it to encode the upper 16 registers, which is
3892 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3893 as 1's compliment. */
3894 if ((i
.vrex
& REX_B
))
3897 i
.vex
.bytes
[1] &= ~0x40;
3901 /* EVEX instructions shouldn't need the REX prefix. */
3902 i
.vrex
&= ~vrex_used
;
3903 gas_assert (i
.vrex
== 0);
3905 /* Check the REX.W bit and VEXW. */
3906 if (i
.tm
.opcode_modifier
.vexw
== VEXWIG
)
3907 w
= (evexwig
== evexw1
|| (i
.rex
& REX_W
)) ? 1 : 0;
3908 else if (i
.tm
.opcode_modifier
.vexw
)
3909 w
= i
.tm
.opcode_modifier
.vexw
== VEXW1
? 1 : 0;
3911 w
= (flag_code
== CODE_64BIT
? i
.rex
& REX_W
: evexwig
== evexw1
) ? 1 : 0;
3913 /* The third byte of the EVEX prefix. */
3914 i
.vex
.bytes
[2] = ((w
<< 7)
3915 | (register_specifier
<< 3)
3916 | 4 /* Encode the U bit. */
3917 | i
.tm
.opcode_modifier
.opcodeprefix
);
3919 /* The fourth byte of the EVEX prefix. */
3920 /* The zeroing-masking bit. */
3921 if (i
.mask
.reg
&& i
.mask
.zeroing
)
3922 i
.vex
.bytes
[3] |= 0x80;
3924 /* Don't always set the broadcast bit if there is no RC. */
3925 if (i
.rounding
.type
== rc_none
)
3927 /* Encode the vector length. */
3928 unsigned int vec_length
;
3930 if (!i
.tm
.opcode_modifier
.evex
3931 || i
.tm
.opcode_modifier
.evex
== EVEXDYN
)
3935 /* Determine vector length from the last multi-length vector
3937 for (op
= i
.operands
; op
--;)
3938 if (i
.tm
.operand_types
[op
].bitfield
.xmmword
3939 + i
.tm
.operand_types
[op
].bitfield
.ymmword
3940 + i
.tm
.operand_types
[op
].bitfield
.zmmword
> 1)
3942 if (i
.types
[op
].bitfield
.zmmword
)
3944 i
.tm
.opcode_modifier
.evex
= EVEX512
;
3947 else if (i
.types
[op
].bitfield
.ymmword
)
3949 i
.tm
.opcode_modifier
.evex
= EVEX256
;
3952 else if (i
.types
[op
].bitfield
.xmmword
)
3954 i
.tm
.opcode_modifier
.evex
= EVEX128
;
3957 else if (i
.broadcast
.type
&& op
== i
.broadcast
.operand
)
3959 switch (i
.broadcast
.bytes
)
3962 i
.tm
.opcode_modifier
.evex
= EVEX512
;
3965 i
.tm
.opcode_modifier
.evex
= EVEX256
;
3968 i
.tm
.opcode_modifier
.evex
= EVEX128
;
3977 if (op
>= MAX_OPERANDS
)
3981 switch (i
.tm
.opcode_modifier
.evex
)
3983 case EVEXLIG
: /* LL' is ignored */
3984 vec_length
= evexlig
<< 5;
3987 vec_length
= 0 << 5;
3990 vec_length
= 1 << 5;
3993 vec_length
= 2 << 5;
3999 i
.vex
.bytes
[3] |= vec_length
;
4000 /* Encode the broadcast bit. */
4001 if (i
.broadcast
.type
)
4002 i
.vex
.bytes
[3] |= 0x10;
4004 else if (i
.rounding
.type
!= saeonly
)
4005 i
.vex
.bytes
[3] |= 0x10 | (i
.rounding
.type
<< 5);
4007 i
.vex
.bytes
[3] |= 0x10 | (evexrcig
<< 5);
4010 i
.vex
.bytes
[3] |= i
.mask
.reg
->reg_num
;
4014 process_immext (void)
4018 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
4019 which is coded in the same place as an 8-bit immediate field
4020 would be. Here we fake an 8-bit immediate operand from the
4021 opcode suffix stored in tm.extension_opcode.
4023 AVX instructions also use this encoding, for some of
4024 3 argument instructions. */
4026 gas_assert (i
.imm_operands
<= 1
4028 || (is_any_vex_encoding (&i
.tm
)
4029 && i
.operands
<= 4)));
4031 exp
= &im_expressions
[i
.imm_operands
++];
4032 i
.op
[i
.operands
].imms
= exp
;
4033 i
.types
[i
.operands
] = imm8
;
4035 exp
->X_op
= O_constant
;
4036 exp
->X_add_number
= i
.tm
.extension_opcode
;
4037 i
.tm
.extension_opcode
= None
;
4044 switch (i
.tm
.opcode_modifier
.prefixok
)
4052 as_bad (_("invalid instruction `%s' after `%s'"),
4053 i
.tm
.name
, i
.hle_prefix
);
4056 if (i
.prefix
[LOCK_PREFIX
])
4058 as_bad (_("missing `lock' with `%s'"), i
.hle_prefix
);
4062 case PrefixHLERelease
:
4063 if (i
.prefix
[HLE_PREFIX
] != XRELEASE_PREFIX_OPCODE
)
4065 as_bad (_("instruction `%s' after `xacquire' not allowed"),
4069 if (i
.mem_operands
== 0 || !(i
.flags
[i
.operands
- 1] & Operand_Mem
))
4071 as_bad (_("memory destination needed for instruction `%s'"
4072 " after `xrelease'"), i
.tm
.name
);
4079 /* Try the shortest encoding by shortening operand size. */
4082 optimize_encoding (void)
4086 if (i
.tm
.opcode_modifier
.opcodespace
== SPACE_BASE
4087 && i
.tm
.base_opcode
== 0x8d)
4090 lea symbol, %rN -> mov $symbol, %rN
4091 lea (%rM), %rN -> mov %rM, %rN
4092 lea (,%rM,1), %rN -> mov %rM, %rN
4094 and in 32-bit mode for 16-bit addressing
4096 lea (%rM), %rN -> movzx %rM, %rN
4098 and in 64-bit mode zap 32-bit addressing in favor of using a
4099 32-bit (or less) destination.
4101 if (flag_code
== CODE_64BIT
&& i
.prefix
[ADDR_PREFIX
])
4103 if (!i
.op
[1].regs
->reg_type
.bitfield
.word
)
4104 i
.tm
.opcode_modifier
.size
= SIZE32
;
4105 i
.prefix
[ADDR_PREFIX
] = 0;
4108 if (!i
.index_reg
&& !i
.base_reg
)
4111 lea symbol, %rN -> mov $symbol, %rN
4113 if (flag_code
== CODE_64BIT
)
4115 /* Don't transform a relocation to a 16-bit one. */
4117 && i
.op
[0].disps
->X_op
!= O_constant
4118 && i
.op
[1].regs
->reg_type
.bitfield
.word
)
4121 if (!i
.op
[1].regs
->reg_type
.bitfield
.qword
4122 || i
.tm
.opcode_modifier
.size
== SIZE32
)
4124 i
.tm
.base_opcode
= 0xb8;
4125 i
.tm
.opcode_modifier
.modrm
= 0;
4126 if (!i
.op
[1].regs
->reg_type
.bitfield
.word
)
4127 i
.types
[0].bitfield
.imm32
= 1;
4130 i
.tm
.opcode_modifier
.size
= SIZE16
;
4131 i
.types
[0].bitfield
.imm16
= 1;
4136 /* Subject to further optimization below. */
4137 i
.tm
.base_opcode
= 0xc7;
4138 i
.tm
.extension_opcode
= 0;
4139 i
.types
[0].bitfield
.imm32s
= 1;
4140 i
.types
[0].bitfield
.baseindex
= 0;
4143 /* Outside of 64-bit mode address and operand sizes have to match if
4144 a relocation is involved, as otherwise we wouldn't (currently) or
4145 even couldn't express the relocation correctly. */
4146 else if (i
.op
[0].disps
4147 && i
.op
[0].disps
->X_op
!= O_constant
4148 && ((!i
.prefix
[ADDR_PREFIX
])
4149 != (flag_code
== CODE_32BIT
4150 ? i
.op
[1].regs
->reg_type
.bitfield
.dword
4151 : i
.op
[1].regs
->reg_type
.bitfield
.word
)))
4155 i
.tm
.base_opcode
= 0xb8;
4156 i
.tm
.opcode_modifier
.modrm
= 0;
4157 if (i
.op
[1].regs
->reg_type
.bitfield
.dword
)
4158 i
.types
[0].bitfield
.imm32
= 1;
4160 i
.types
[0].bitfield
.imm16
= 1;
4163 && i
.op
[0].disps
->X_op
== O_constant
4164 && i
.op
[1].regs
->reg_type
.bitfield
.dword
4165 /* NB: Add () to !i.prefix[ADDR_PREFIX] to silence
4167 && (!i
.prefix
[ADDR_PREFIX
]) != (flag_code
== CODE_32BIT
))
4168 i
.op
[0].disps
->X_add_number
&= 0xffff;
4171 i
.tm
.operand_types
[0] = i
.types
[0];
4175 i
.op
[0].imms
= &im_expressions
[0];
4176 i
.op
[0].imms
->X_op
= O_absent
;
4179 else if (i
.op
[0].disps
4180 && (i
.op
[0].disps
->X_op
!= O_constant
4181 || i
.op
[0].disps
->X_add_number
))
4186 lea (%rM), %rN -> mov %rM, %rN
4187 lea (,%rM,1), %rN -> mov %rM, %rN
4188 lea (%rM), %rN -> movzx %rM, %rN
4190 const reg_entry
*addr_reg
;
4192 if (!i
.index_reg
&& i
.base_reg
->reg_num
!= RegIP
)
4193 addr_reg
= i
.base_reg
;
4194 else if (!i
.base_reg
4195 && i
.index_reg
->reg_num
!= RegIZ
4196 && !i
.log2_scale_factor
)
4197 addr_reg
= i
.index_reg
;
4201 if (addr_reg
->reg_type
.bitfield
.word
4202 && i
.op
[1].regs
->reg_type
.bitfield
.dword
)
4204 if (flag_code
!= CODE_32BIT
)
4206 i
.tm
.opcode_modifier
.opcodespace
= SPACE_0F
;
4207 i
.tm
.base_opcode
= 0xb7;
4210 i
.tm
.base_opcode
= 0x8b;
4212 if (addr_reg
->reg_type
.bitfield
.dword
4213 && i
.op
[1].regs
->reg_type
.bitfield
.qword
)
4214 i
.tm
.opcode_modifier
.size
= SIZE32
;
4216 i
.op
[0].regs
= addr_reg
;
4221 i
.disp_operands
= 0;
4222 i
.prefix
[ADDR_PREFIX
] = 0;
4223 i
.prefix
[SEG_PREFIX
] = 0;
4227 if (optimize_for_space
4228 && i
.tm
.opcode_modifier
.opcodespace
== SPACE_BASE
4229 && i
.reg_operands
== 1
4230 && i
.imm_operands
== 1
4231 && !i
.types
[1].bitfield
.byte
4232 && i
.op
[0].imms
->X_op
== O_constant
4233 && fits_in_imm7 (i
.op
[0].imms
->X_add_number
)
4234 && (i
.tm
.base_opcode
== 0xa8
4235 || (i
.tm
.base_opcode
== 0xf6
4236 && i
.tm
.extension_opcode
== 0x0)))
4239 test $imm7, %r64/%r32/%r16 -> test $imm7, %r8
4241 unsigned int base_regnum
= i
.op
[1].regs
->reg_num
;
4242 if (flag_code
== CODE_64BIT
|| base_regnum
< 4)
4244 i
.types
[1].bitfield
.byte
= 1;
4245 /* Ignore the suffix. */
4247 /* Convert to byte registers. */
4248 if (i
.types
[1].bitfield
.word
)
4250 else if (i
.types
[1].bitfield
.dword
)
4254 if (!(i
.op
[1].regs
->reg_flags
& RegRex
) && base_regnum
< 4)
4259 else if (flag_code
== CODE_64BIT
4260 && i
.tm
.opcode_modifier
.opcodespace
== SPACE_BASE
4261 && ((i
.types
[1].bitfield
.qword
4262 && i
.reg_operands
== 1
4263 && i
.imm_operands
== 1
4264 && i
.op
[0].imms
->X_op
== O_constant
4265 && ((i
.tm
.base_opcode
== 0xb8
4266 && i
.tm
.extension_opcode
== None
4267 && fits_in_unsigned_long (i
.op
[0].imms
->X_add_number
))
4268 || (fits_in_imm31 (i
.op
[0].imms
->X_add_number
)
4269 && ((i
.tm
.base_opcode
== 0x24
4270 || i
.tm
.base_opcode
== 0xa8)
4271 || (i
.tm
.base_opcode
== 0x80
4272 && i
.tm
.extension_opcode
== 0x4)
4273 || ((i
.tm
.base_opcode
== 0xf6
4274 || (i
.tm
.base_opcode
| 1) == 0xc7)
4275 && i
.tm
.extension_opcode
== 0x0)))
4276 || (fits_in_imm7 (i
.op
[0].imms
->X_add_number
)
4277 && i
.tm
.base_opcode
== 0x83
4278 && i
.tm
.extension_opcode
== 0x4)))
4279 || (i
.types
[0].bitfield
.qword
4280 && ((i
.reg_operands
== 2
4281 && i
.op
[0].regs
== i
.op
[1].regs
4282 && (i
.tm
.base_opcode
== 0x30
4283 || i
.tm
.base_opcode
== 0x28))
4284 || (i
.reg_operands
== 1
4286 && i
.tm
.base_opcode
== 0x30)))))
4289 andq $imm31, %r64 -> andl $imm31, %r32
4290 andq $imm7, %r64 -> andl $imm7, %r32
4291 testq $imm31, %r64 -> testl $imm31, %r32
4292 xorq %r64, %r64 -> xorl %r32, %r32
4293 subq %r64, %r64 -> subl %r32, %r32
4294 movq $imm31, %r64 -> movl $imm31, %r32
4295 movq $imm32, %r64 -> movl $imm32, %r32
4297 i
.tm
.opcode_modifier
.norex64
= 1;
4298 if (i
.tm
.base_opcode
== 0xb8 || (i
.tm
.base_opcode
| 1) == 0xc7)
4301 movq $imm31, %r64 -> movl $imm31, %r32
4302 movq $imm32, %r64 -> movl $imm32, %r32
4304 i
.tm
.operand_types
[0].bitfield
.imm32
= 1;
4305 i
.tm
.operand_types
[0].bitfield
.imm32s
= 0;
4306 i
.tm
.operand_types
[0].bitfield
.imm64
= 0;
4307 i
.types
[0].bitfield
.imm32
= 1;
4308 i
.types
[0].bitfield
.imm32s
= 0;
4309 i
.types
[0].bitfield
.imm64
= 0;
4310 i
.types
[1].bitfield
.dword
= 1;
4311 i
.types
[1].bitfield
.qword
= 0;
4312 if ((i
.tm
.base_opcode
| 1) == 0xc7)
4315 movq $imm31, %r64 -> movl $imm31, %r32
4317 i
.tm
.base_opcode
= 0xb8;
4318 i
.tm
.extension_opcode
= None
;
4319 i
.tm
.opcode_modifier
.w
= 0;
4320 i
.tm
.opcode_modifier
.modrm
= 0;
4324 else if (optimize
> 1
4325 && !optimize_for_space
4326 && i
.tm
.opcode_modifier
.opcodespace
== SPACE_BASE
4327 && i
.reg_operands
== 2
4328 && i
.op
[0].regs
== i
.op
[1].regs
4329 && ((i
.tm
.base_opcode
& ~(Opcode_D
| 1)) == 0x8
4330 || (i
.tm
.base_opcode
& ~(Opcode_D
| 1)) == 0x20)
4331 && (flag_code
!= CODE_64BIT
|| !i
.types
[0].bitfield
.dword
))
4334 andb %rN, %rN -> testb %rN, %rN
4335 andw %rN, %rN -> testw %rN, %rN
4336 andq %rN, %rN -> testq %rN, %rN
4337 orb %rN, %rN -> testb %rN, %rN
4338 orw %rN, %rN -> testw %rN, %rN
4339 orq %rN, %rN -> testq %rN, %rN
4341 and outside of 64-bit mode
4343 andl %rN, %rN -> testl %rN, %rN
4344 orl %rN, %rN -> testl %rN, %rN
4346 i
.tm
.base_opcode
= 0x84 | (i
.tm
.base_opcode
& 1);
4348 else if (i
.reg_operands
== 3
4349 && i
.op
[0].regs
== i
.op
[1].regs
4350 && !i
.types
[2].bitfield
.xmmword
4351 && (i
.tm
.opcode_modifier
.vex
4352 || ((!i
.mask
.reg
|| i
.mask
.zeroing
)
4353 && i
.rounding
.type
== rc_none
4354 && is_evex_encoding (&i
.tm
)
4355 && (i
.vec_encoding
!= vex_encoding_evex
4356 || cpu_arch_isa_flags
.bitfield
.cpuavx512vl
4357 || i
.tm
.cpu_flags
.bitfield
.cpuavx512vl
4358 || (i
.tm
.operand_types
[2].bitfield
.zmmword
4359 && i
.types
[2].bitfield
.ymmword
))))
4360 && ((i
.tm
.base_opcode
== 0x55
4361 || i
.tm
.base_opcode
== 0x57
4362 || i
.tm
.base_opcode
== 0xdf
4363 || i
.tm
.base_opcode
== 0xef
4364 || i
.tm
.base_opcode
== 0xf8
4365 || i
.tm
.base_opcode
== 0xf9
4366 || i
.tm
.base_opcode
== 0xfa
4367 || i
.tm
.base_opcode
== 0xfb
4368 || i
.tm
.base_opcode
== 0x42
4369 || i
.tm
.base_opcode
== 0x47)
4370 && i
.tm
.extension_opcode
== None
))
4373 VOP, one of vandnps, vandnpd, vxorps, vxorpd, vpsubb, vpsubd,
4375 EVEX VOP %zmmM, %zmmM, %zmmN
4376 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
4377 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4378 EVEX VOP %ymmM, %ymmM, %ymmN
4379 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
4380 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4381 VEX VOP %ymmM, %ymmM, %ymmN
4382 -> VEX VOP %xmmM, %xmmM, %xmmN
4383 VOP, one of vpandn and vpxor:
4384 VEX VOP %ymmM, %ymmM, %ymmN
4385 -> VEX VOP %xmmM, %xmmM, %xmmN
4386 VOP, one of vpandnd and vpandnq:
4387 EVEX VOP %zmmM, %zmmM, %zmmN
4388 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
4389 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4390 EVEX VOP %ymmM, %ymmM, %ymmN
4391 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
4392 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4393 VOP, one of vpxord and vpxorq:
4394 EVEX VOP %zmmM, %zmmM, %zmmN
4395 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
4396 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4397 EVEX VOP %ymmM, %ymmM, %ymmN
4398 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
4399 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4400 VOP, one of kxord and kxorq:
4401 VEX VOP %kM, %kM, %kN
4402 -> VEX kxorw %kM, %kM, %kN
4403 VOP, one of kandnd and kandnq:
4404 VEX VOP %kM, %kM, %kN
4405 -> VEX kandnw %kM, %kM, %kN
4407 if (is_evex_encoding (&i
.tm
))
4409 if (i
.vec_encoding
!= vex_encoding_evex
)
4411 i
.tm
.opcode_modifier
.vex
= VEX128
;
4412 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4413 i
.tm
.opcode_modifier
.evex
= 0;
4415 else if (optimize
> 1)
4416 i
.tm
.opcode_modifier
.evex
= EVEX128
;
4420 else if (i
.tm
.operand_types
[0].bitfield
.class == RegMask
)
4422 i
.tm
.opcode_modifier
.opcodeprefix
= PREFIX_NONE
;
4423 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4426 i
.tm
.opcode_modifier
.vex
= VEX128
;
4428 if (i
.tm
.opcode_modifier
.vex
)
4429 for (j
= 0; j
< 3; j
++)
4431 i
.types
[j
].bitfield
.xmmword
= 1;
4432 i
.types
[j
].bitfield
.ymmword
= 0;
4435 else if (i
.vec_encoding
!= vex_encoding_evex
4436 && !i
.types
[0].bitfield
.zmmword
4437 && !i
.types
[1].bitfield
.zmmword
4439 && !i
.broadcast
.type
4440 && is_evex_encoding (&i
.tm
)
4441 && ((i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0x6f
4442 || (i
.tm
.base_opcode
& ~4) == 0xdb
4443 || (i
.tm
.base_opcode
& ~4) == 0xeb)
4444 && i
.tm
.extension_opcode
== None
)
4447 VOP, one of vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16,
4448 vmovdqu32 and vmovdqu64:
4449 EVEX VOP %xmmM, %xmmN
4450 -> VEX vmovdqa|vmovdqu %xmmM, %xmmN (M and N < 16)
4451 EVEX VOP %ymmM, %ymmN
4452 -> VEX vmovdqa|vmovdqu %ymmM, %ymmN (M and N < 16)
4454 -> VEX vmovdqa|vmovdqu %xmmM, mem (M < 16)
4456 -> VEX vmovdqa|vmovdqu %ymmM, mem (M < 16)
4458 -> VEX mvmovdqa|vmovdquem, %xmmN (N < 16)
4460 -> VEX vmovdqa|vmovdqu mem, %ymmN (N < 16)
4461 VOP, one of vpand, vpandn, vpor, vpxor:
4462 EVEX VOP{d,q} %xmmL, %xmmM, %xmmN
4463 -> VEX VOP %xmmL, %xmmM, %xmmN (L, M, and N < 16)
4464 EVEX VOP{d,q} %ymmL, %ymmM, %ymmN
4465 -> VEX VOP %ymmL, %ymmM, %ymmN (L, M, and N < 16)
4466 EVEX VOP{d,q} mem, %xmmM, %xmmN
4467 -> VEX VOP mem, %xmmM, %xmmN (M and N < 16)
4468 EVEX VOP{d,q} mem, %ymmM, %ymmN
4469 -> VEX VOP mem, %ymmM, %ymmN (M and N < 16)
4471 for (j
= 0; j
< i
.operands
; j
++)
4472 if (operand_type_check (i
.types
[j
], disp
)
4473 && i
.op
[j
].disps
->X_op
== O_constant
)
4475 /* Since the VEX prefix has 2 or 3 bytes, the EVEX prefix
4476 has 4 bytes, EVEX Disp8 has 1 byte and VEX Disp32 has 4
4477 bytes, we choose EVEX Disp8 over VEX Disp32. */
4478 int evex_disp8
, vex_disp8
;
4479 unsigned int memshift
= i
.memshift
;
4480 offsetT n
= i
.op
[j
].disps
->X_add_number
;
4482 evex_disp8
= fits_in_disp8 (n
);
4484 vex_disp8
= fits_in_disp8 (n
);
4485 if (evex_disp8
!= vex_disp8
)
4487 i
.memshift
= memshift
;
4491 i
.types
[j
].bitfield
.disp8
= vex_disp8
;
4494 if ((i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0x6f
4495 && i
.tm
.opcode_modifier
.opcodeprefix
== PREFIX_0XF2
)
4496 i
.tm
.opcode_modifier
.opcodeprefix
= PREFIX_0XF3
;
4497 i
.tm
.opcode_modifier
.vex
4498 = i
.types
[0].bitfield
.ymmword
? VEX256
: VEX128
;
4499 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4500 /* VPAND, VPOR, and VPXOR are commutative. */
4501 if (i
.reg_operands
== 3 && i
.tm
.base_opcode
!= 0xdf)
4502 i
.tm
.opcode_modifier
.commutative
= 1;
4503 i
.tm
.opcode_modifier
.evex
= 0;
4504 i
.tm
.opcode_modifier
.masking
= 0;
4505 i
.tm
.opcode_modifier
.broadcast
= 0;
4506 i
.tm
.opcode_modifier
.disp8memshift
= 0;
4509 i
.types
[j
].bitfield
.disp8
4510 = fits_in_disp8 (i
.op
[j
].disps
->X_add_number
);
4514 /* Return non-zero for load instruction. */
4520 int any_vex_p
= is_any_vex_encoding (&i
.tm
);
4521 unsigned int base_opcode
= i
.tm
.base_opcode
| 1;
4525 /* Anysize insns: lea, invlpg, clflush, prefetchnta, prefetcht0,
4526 prefetcht1, prefetcht2, prefetchtw, bndmk, bndcl, bndcu, bndcn,
4527 bndstx, bndldx, prefetchwt1, clflushopt, clwb, cldemote. */
4528 if (i
.tm
.opcode_modifier
.anysize
)
4532 if (strcmp (i
.tm
.name
, "pop") == 0)
4536 if (i
.tm
.opcode_modifier
.opcodespace
== SPACE_BASE
)
4539 if (i
.tm
.base_opcode
== 0x9d
4540 || i
.tm
.base_opcode
== 0x61)
4543 /* movs, cmps, lods, scas. */
4544 if ((i
.tm
.base_opcode
| 0xb) == 0xaf)
4548 if (base_opcode
== 0x6f
4549 || i
.tm
.base_opcode
== 0xd7)
4551 /* NB: For AMD-specific insns with implicit memory operands,
4552 they're intentionally not covered. */
4555 /* No memory operand. */
4556 if (!i
.mem_operands
)
4562 if (i
.tm
.base_opcode
== 0xae
4563 && i
.tm
.opcode_modifier
.vex
4564 && i
.tm
.opcode_modifier
.opcodespace
== SPACE_0F
4565 && i
.tm
.opcode_modifier
.opcodeprefix
== PREFIX_NONE
4566 && i
.tm
.extension_opcode
== 2)
4569 else if (i
.tm
.opcode_modifier
.opcodespace
== SPACE_BASE
)
4571 /* test, not, neg, mul, imul, div, idiv. */
4572 if ((i
.tm
.base_opcode
== 0xf6 || i
.tm
.base_opcode
== 0xf7)
4573 && i
.tm
.extension_opcode
!= 1)
4577 if (base_opcode
== 0xff && i
.tm
.extension_opcode
<= 1)
4580 /* add, or, adc, sbb, and, sub, xor, cmp. */
4581 if (i
.tm
.base_opcode
>= 0x80 && i
.tm
.base_opcode
<= 0x83)
4584 /* rol, ror, rcl, rcr, shl/sal, shr, sar. */
4585 if ((base_opcode
== 0xc1
4586 || (i
.tm
.base_opcode
>= 0xd0 && i
.tm
.base_opcode
<= 0xd3))
4587 && i
.tm
.extension_opcode
!= 6)
4590 /* Check for x87 instructions. */
4591 if (base_opcode
>= 0xd8 && base_opcode
<= 0xdf)
4593 /* Skip fst, fstp, fstenv, fstcw. */
4594 if (i
.tm
.base_opcode
== 0xd9
4595 && (i
.tm
.extension_opcode
== 2
4596 || i
.tm
.extension_opcode
== 3
4597 || i
.tm
.extension_opcode
== 6
4598 || i
.tm
.extension_opcode
== 7))
4601 /* Skip fisttp, fist, fistp, fstp. */
4602 if (i
.tm
.base_opcode
== 0xdb
4603 && (i
.tm
.extension_opcode
== 1
4604 || i
.tm
.extension_opcode
== 2
4605 || i
.tm
.extension_opcode
== 3
4606 || i
.tm
.extension_opcode
== 7))
4609 /* Skip fisttp, fst, fstp, fsave, fstsw. */
4610 if (i
.tm
.base_opcode
== 0xdd
4611 && (i
.tm
.extension_opcode
== 1
4612 || i
.tm
.extension_opcode
== 2
4613 || i
.tm
.extension_opcode
== 3
4614 || i
.tm
.extension_opcode
== 6
4615 || i
.tm
.extension_opcode
== 7))
4618 /* Skip fisttp, fist, fistp, fbstp, fistp. */
4619 if (i
.tm
.base_opcode
== 0xdf
4620 && (i
.tm
.extension_opcode
== 1
4621 || i
.tm
.extension_opcode
== 2
4622 || i
.tm
.extension_opcode
== 3
4623 || i
.tm
.extension_opcode
== 6
4624 || i
.tm
.extension_opcode
== 7))
4630 else if (i
.tm
.opcode_modifier
.opcodespace
== SPACE_0F
)
4632 /* bt, bts, btr, btc. */
4633 if (i
.tm
.base_opcode
== 0xba
4634 && (i
.tm
.extension_opcode
>= 4 && i
.tm
.extension_opcode
<= 7))
4637 /* cmpxchg8b, cmpxchg16b, xrstors, vmptrld. */
4638 if (i
.tm
.base_opcode
== 0xc7
4639 && i
.tm
.opcode_modifier
.opcodeprefix
== PREFIX_NONE
4640 && (i
.tm
.extension_opcode
== 1 || i
.tm
.extension_opcode
== 3
4641 || i
.tm
.extension_opcode
== 6))
4644 /* fxrstor, ldmxcsr, xrstor. */
4645 if (i
.tm
.base_opcode
== 0xae
4646 && (i
.tm
.extension_opcode
== 1
4647 || i
.tm
.extension_opcode
== 2
4648 || i
.tm
.extension_opcode
== 5))
4651 /* lgdt, lidt, lmsw. */
4652 if (i
.tm
.base_opcode
== 0x01
4653 && (i
.tm
.extension_opcode
== 2
4654 || i
.tm
.extension_opcode
== 3
4655 || i
.tm
.extension_opcode
== 6))
4659 dest
= i
.operands
- 1;
4661 /* Check fake imm8 operand and 3 source operands. */
4662 if ((i
.tm
.opcode_modifier
.immext
4663 || i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
)
4664 && i
.types
[dest
].bitfield
.imm8
)
4667 /* add, or, adc, sbb, and, sub, xor, cmp, test, xchg. */
4668 if (i
.tm
.opcode_modifier
.opcodespace
== SPACE_BASE
4669 && (base_opcode
== 0x1
4670 || base_opcode
== 0x9
4671 || base_opcode
== 0x11
4672 || base_opcode
== 0x19
4673 || base_opcode
== 0x21
4674 || base_opcode
== 0x29
4675 || base_opcode
== 0x31
4676 || base_opcode
== 0x39
4677 || (base_opcode
| 2) == 0x87))
4681 if (i
.tm
.opcode_modifier
.opcodespace
== SPACE_0F
4682 && base_opcode
== 0xc1)
4685 /* Check for load instruction. */
4686 return (i
.types
[dest
].bitfield
.class != ClassNone
4687 || i
.types
[dest
].bitfield
.instance
== Accum
);
4690 /* Output lfence, 0xfaee8, after instruction. */
4693 insert_lfence_after (void)
4695 if (lfence_after_load
&& load_insn_p ())
4697 /* There are also two REP string instructions that require
4698 special treatment. Specifically, the compare string (CMPS)
4699 and scan string (SCAS) instructions set EFLAGS in a manner
4700 that depends on the data being compared/scanned. When used
4701 with a REP prefix, the number of iterations may therefore
4702 vary depending on this data. If the data is a program secret
4703 chosen by the adversary using an LVI method,
4704 then this data-dependent behavior may leak some aspect
4706 if (((i
.tm
.base_opcode
| 0x1) == 0xa7
4707 || (i
.tm
.base_opcode
| 0x1) == 0xaf)
4708 && i
.prefix
[REP_PREFIX
])
4710 as_warn (_("`%s` changes flags which would affect control flow behavior"),
4713 char *p
= frag_more (3);
4720 /* Output lfence, 0xfaee8, before instruction. */
4723 insert_lfence_before (void)
4727 if (i
.tm
.opcode_modifier
.opcodespace
!= SPACE_BASE
)
4730 if (i
.tm
.base_opcode
== 0xff
4731 && (i
.tm
.extension_opcode
== 2 || i
.tm
.extension_opcode
== 4))
4733 /* Insert lfence before indirect branch if needed. */
4735 if (lfence_before_indirect_branch
== lfence_branch_none
)
4738 if (i
.operands
!= 1)
4741 if (i
.reg_operands
== 1)
4743 /* Indirect branch via register. Don't insert lfence with
4744 -mlfence-after-load=yes. */
4745 if (lfence_after_load
4746 || lfence_before_indirect_branch
== lfence_branch_memory
)
4749 else if (i
.mem_operands
== 1
4750 && lfence_before_indirect_branch
!= lfence_branch_register
)
4752 as_warn (_("indirect `%s` with memory operand should be avoided"),
4759 if (last_insn
.kind
!= last_insn_other
4760 && last_insn
.seg
== now_seg
)
4762 as_warn_where (last_insn
.file
, last_insn
.line
,
4763 _("`%s` skips -mlfence-before-indirect-branch on `%s`"),
4764 last_insn
.name
, i
.tm
.name
);
4775 /* Output or/not/shl and lfence before near ret. */
4776 if (lfence_before_ret
!= lfence_before_ret_none
4777 && (i
.tm
.base_opcode
== 0xc2
4778 || i
.tm
.base_opcode
== 0xc3))
4780 if (last_insn
.kind
!= last_insn_other
4781 && last_insn
.seg
== now_seg
)
4783 as_warn_where (last_insn
.file
, last_insn
.line
,
4784 _("`%s` skips -mlfence-before-ret on `%s`"),
4785 last_insn
.name
, i
.tm
.name
);
4789 /* Near ret ingore operand size override under CPU64. */
4790 char prefix
= flag_code
== CODE_64BIT
4792 : i
.prefix
[DATA_PREFIX
] ? 0x66 : 0x0;
4794 if (lfence_before_ret
== lfence_before_ret_not
)
4796 /* not: 0xf71424, may add prefix
4797 for operand size override or 64-bit code. */
4798 p
= frag_more ((prefix
? 2 : 0) + 6 + 3);
4812 p
= frag_more ((prefix
? 1 : 0) + 4 + 3);
4815 if (lfence_before_ret
== lfence_before_ret_or
)
4817 /* or: 0x830c2400, may add prefix
4818 for operand size override or 64-bit code. */
4824 /* shl: 0xc1242400, may add prefix
4825 for operand size override or 64-bit code. */
4840 /* This is the guts of the machine-dependent assembler. LINE points to a
4841 machine dependent instruction. This function is supposed to emit
4842 the frags/bytes it assembles to. */
4845 md_assemble (char *line
)
4848 char mnemonic
[MAX_MNEM_SIZE
], mnem_suffix
;
4849 const insn_template
*t
;
4851 /* Initialize globals. */
4852 memset (&i
, '\0', sizeof (i
));
4853 i
.rounding
.type
= rc_none
;
4854 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4855 i
.reloc
[j
] = NO_RELOC
;
4856 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
4857 memset (im_expressions
, '\0', sizeof (im_expressions
));
4858 save_stack_p
= save_stack
;
4860 /* First parse an instruction mnemonic & call i386_operand for the operands.
4861 We assume that the scrubber has arranged it so that line[0] is the valid
4862 start of a (possibly prefixed) mnemonic. */
4864 line
= parse_insn (line
, mnemonic
);
4867 mnem_suffix
= i
.suffix
;
4869 line
= parse_operands (line
, mnemonic
);
4871 xfree (i
.memop1_string
);
4872 i
.memop1_string
= NULL
;
4876 /* Now we've parsed the mnemonic into a set of templates, and have the
4877 operands at hand. */
4879 /* All Intel opcodes have reversed operands except for "bound", "enter",
4880 "invlpg*", "monitor*", "mwait*", "tpause", "umwait", "pvalidate",
4881 "rmpadjust", and "rmpupdate". We also don't reverse intersegment "jmp"
4882 and "call" instructions with 2 immediate operands so that the immediate
4883 segment precedes the offset consistently in Intel and AT&T modes. */
4886 && (strcmp (mnemonic
, "bound") != 0)
4887 && (strncmp (mnemonic
, "invlpg", 6) != 0)
4888 && !startswith (mnemonic
, "monitor")
4889 && !startswith (mnemonic
, "mwait")
4890 && (strcmp (mnemonic
, "pvalidate") != 0)
4891 && !startswith (mnemonic
, "rmp")
4892 && (strcmp (mnemonic
, "tpause") != 0)
4893 && (strcmp (mnemonic
, "umwait") != 0)
4894 && !(operand_type_check (i
.types
[0], imm
)
4895 && operand_type_check (i
.types
[1], imm
)))
4898 /* The order of the immediates should be reversed
4899 for 2 immediates extrq and insertq instructions */
4900 if (i
.imm_operands
== 2
4901 && (strcmp (mnemonic
, "extrq") == 0
4902 || strcmp (mnemonic
, "insertq") == 0))
4903 swap_2_operands (0, 1);
4908 if (i
.disp_operands
&& !want_disp32 (current_templates
->start
))
4910 for (j
= 0; j
< i
.operands
; ++j
)
4912 const expressionS
*exp
= i
.op
[j
].disps
;
4914 if (!operand_type_check (i
.types
[j
], disp
))
4917 if (exp
->X_op
!= O_constant
)
4920 /* Since displacement is signed extended to 64bit, don't allow
4921 disp32 and turn off disp32s if they are out of range. */
4922 i
.types
[j
].bitfield
.disp32
= 0;
4923 if (fits_in_signed_long (exp
->X_add_number
))
4926 i
.types
[j
].bitfield
.disp32s
= 0;
4927 if (i
.types
[j
].bitfield
.baseindex
)
4929 as_bad (_("0x%" BFD_VMA_FMT
"x out of range of signed 32bit displacement"),
4936 /* Don't optimize displacement for movabs since it only takes 64bit
4939 && i
.disp_encoding
!= disp_encoding_32bit
4940 && (flag_code
!= CODE_64BIT
4941 || strcmp (mnemonic
, "movabs") != 0))
4944 /* Next, we find a template that matches the given insn,
4945 making sure the overlap of the given operands types is consistent
4946 with the template operand types. */
4948 if (!(t
= match_template (mnem_suffix
)))
4951 if (sse_check
!= check_none
4952 && !i
.tm
.opcode_modifier
.noavx
4953 && !i
.tm
.cpu_flags
.bitfield
.cpuavx
4954 && !i
.tm
.cpu_flags
.bitfield
.cpuavx512f
4955 && (i
.tm
.cpu_flags
.bitfield
.cpusse
4956 || i
.tm
.cpu_flags
.bitfield
.cpusse2
4957 || i
.tm
.cpu_flags
.bitfield
.cpusse3
4958 || i
.tm
.cpu_flags
.bitfield
.cpussse3
4959 || i
.tm
.cpu_flags
.bitfield
.cpusse4_1
4960 || i
.tm
.cpu_flags
.bitfield
.cpusse4_2
4961 || i
.tm
.cpu_flags
.bitfield
.cpupclmul
4962 || i
.tm
.cpu_flags
.bitfield
.cpuaes
4963 || i
.tm
.cpu_flags
.bitfield
.cpusha
4964 || i
.tm
.cpu_flags
.bitfield
.cpugfni
))
4966 (sse_check
== check_warning
4968 : as_bad
) (_("SSE instruction `%s' is used"), i
.tm
.name
);
4971 if (i
.tm
.opcode_modifier
.fwait
)
4972 if (!add_prefix (FWAIT_OPCODE
))
4975 /* Check if REP prefix is OK. */
4976 if (i
.rep_prefix
&& i
.tm
.opcode_modifier
.prefixok
!= PrefixRep
)
4978 as_bad (_("invalid instruction `%s' after `%s'"),
4979 i
.tm
.name
, i
.rep_prefix
);
4983 /* Check for lock without a lockable instruction. Destination operand
4984 must be memory unless it is xchg (0x86). */
4985 if (i
.prefix
[LOCK_PREFIX
]
4986 && (i
.tm
.opcode_modifier
.prefixok
< PrefixLock
4987 || i
.mem_operands
== 0
4988 || (i
.tm
.base_opcode
!= 0x86
4989 && !(i
.flags
[i
.operands
- 1] & Operand_Mem
))))
4991 as_bad (_("expecting lockable instruction after `lock'"));
4995 /* Check for data size prefix on VEX/XOP/EVEX encoded and SIMD insns. */
4996 if (i
.prefix
[DATA_PREFIX
]
4997 && (is_any_vex_encoding (&i
.tm
)
4998 || i
.tm
.operand_types
[i
.imm_operands
].bitfield
.class >= RegMMX
4999 || i
.tm
.operand_types
[i
.imm_operands
+ 1].bitfield
.class >= RegMMX
))
5001 as_bad (_("data size prefix invalid with `%s'"), i
.tm
.name
);
5005 /* Check if HLE prefix is OK. */
5006 if (i
.hle_prefix
&& !check_hle ())
5009 /* Check BND prefix. */
5010 if (i
.bnd_prefix
&& !i
.tm
.opcode_modifier
.bndprefixok
)
5011 as_bad (_("expecting valid branch instruction after `bnd'"));
5013 /* Check NOTRACK prefix. */
5014 if (i
.notrack_prefix
&& i
.tm
.opcode_modifier
.prefixok
!= PrefixNoTrack
)
5015 as_bad (_("expecting indirect branch instruction after `notrack'"));
5017 if (i
.tm
.cpu_flags
.bitfield
.cpumpx
)
5019 if (flag_code
== CODE_64BIT
&& i
.prefix
[ADDR_PREFIX
])
5020 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
5021 else if (flag_code
!= CODE_16BIT
5022 ? i
.prefix
[ADDR_PREFIX
]
5023 : i
.mem_operands
&& !i
.prefix
[ADDR_PREFIX
])
5024 as_bad (_("16-bit address isn't allowed in MPX instructions"));
5027 /* Insert BND prefix. */
5028 if (add_bnd_prefix
&& i
.tm
.opcode_modifier
.bndprefixok
)
5030 if (!i
.prefix
[BND_PREFIX
])
5031 add_prefix (BND_PREFIX_OPCODE
);
5032 else if (i
.prefix
[BND_PREFIX
] != BND_PREFIX_OPCODE
)
5034 as_warn (_("replacing `rep'/`repe' prefix by `bnd'"));
5035 i
.prefix
[BND_PREFIX
] = BND_PREFIX_OPCODE
;
5039 /* Check string instruction segment overrides. */
5040 if (i
.tm
.opcode_modifier
.isstring
>= IS_STRING_ES_OP0
)
5042 gas_assert (i
.mem_operands
);
5043 if (!check_string ())
5045 i
.disp_operands
= 0;
5048 if (optimize
&& !i
.no_optimize
&& i
.tm
.opcode_modifier
.optimize
)
5049 optimize_encoding ();
5051 if (!process_suffix ())
5054 /* Update operand types and check extended states. */
5055 for (j
= 0; j
< i
.operands
; j
++)
5057 i
.types
[j
] = operand_type_and (i
.types
[j
], i
.tm
.operand_types
[j
]);
5058 switch (i
.tm
.operand_types
[j
].bitfield
.class)
5063 i
.xstate
|= xstate_mmx
;
5066 i
.xstate
|= xstate_mask
;
5069 if (i
.tm
.operand_types
[j
].bitfield
.tmmword
)
5070 i
.xstate
|= xstate_tmm
;
5071 else if (i
.tm
.operand_types
[j
].bitfield
.zmmword
)
5072 i
.xstate
|= xstate_zmm
;
5073 else if (i
.tm
.operand_types
[j
].bitfield
.ymmword
)
5074 i
.xstate
|= xstate_ymm
;
5075 else if (i
.tm
.operand_types
[j
].bitfield
.xmmword
)
5076 i
.xstate
|= xstate_xmm
;
5081 /* Make still unresolved immediate matches conform to size of immediate
5082 given in i.suffix. */
5083 if (!finalize_imm ())
5086 if (i
.types
[0].bitfield
.imm1
)
5087 i
.imm_operands
= 0; /* kludge for shift insns. */
5089 /* We only need to check those implicit registers for instructions
5090 with 3 operands or less. */
5091 if (i
.operands
<= 3)
5092 for (j
= 0; j
< i
.operands
; j
++)
5093 if (i
.types
[j
].bitfield
.instance
!= InstanceNone
5094 && !i
.types
[j
].bitfield
.xmmword
)
5097 /* For insns with operands there are more diddles to do to the opcode. */
5100 if (!process_operands ())
5103 else if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
5105 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
5106 as_warn (_("translating to `%sp'"), i
.tm
.name
);
5109 if (is_any_vex_encoding (&i
.tm
))
5111 if (!cpu_arch_flags
.bitfield
.cpui286
)
5113 as_bad (_("instruction `%s' isn't supported outside of protected mode."),
5118 /* Check for explicit REX prefix. */
5119 if (i
.prefix
[REX_PREFIX
] || i
.rex_encoding
)
5121 as_bad (_("REX prefix invalid with `%s'"), i
.tm
.name
);
5125 if (i
.tm
.opcode_modifier
.vex
)
5126 build_vex_prefix (t
);
5128 build_evex_prefix ();
5130 /* The individual REX.RXBW bits got consumed. */
5131 i
.rex
&= REX_OPCODE
;
5134 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
5135 instructions may define INT_OPCODE as well, so avoid this corner
5136 case for those instructions that use MODRM. */
5137 if (i
.tm
.opcode_modifier
.opcodespace
== SPACE_BASE
5138 && i
.tm
.base_opcode
== INT_OPCODE
5139 && !i
.tm
.opcode_modifier
.modrm
5140 && i
.op
[0].imms
->X_add_number
== 3)
5142 i
.tm
.base_opcode
= INT3_OPCODE
;
5146 if ((i
.tm
.opcode_modifier
.jump
== JUMP
5147 || i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
5148 || i
.tm
.opcode_modifier
.jump
== JUMP_DWORD
)
5149 && i
.op
[0].disps
->X_op
== O_constant
)
5151 /* Convert "jmp constant" (and "call constant") to a jump (call) to
5152 the absolute address given by the constant. Since ix86 jumps and
5153 calls are pc relative, we need to generate a reloc. */
5154 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
5155 i
.op
[0].disps
->X_op
= O_symbol
;
5158 /* For 8 bit registers we need an empty rex prefix. Also if the
5159 instruction already has a prefix, we need to convert old
5160 registers to new ones. */
5162 if ((i
.types
[0].bitfield
.class == Reg
&& i
.types
[0].bitfield
.byte
5163 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
5164 || (i
.types
[1].bitfield
.class == Reg
&& i
.types
[1].bitfield
.byte
5165 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
5166 || (((i
.types
[0].bitfield
.class == Reg
&& i
.types
[0].bitfield
.byte
)
5167 || (i
.types
[1].bitfield
.class == Reg
&& i
.types
[1].bitfield
.byte
))
5172 i
.rex
|= REX_OPCODE
;
5173 for (x
= 0; x
< 2; x
++)
5175 /* Look for 8 bit operand that uses old registers. */
5176 if (i
.types
[x
].bitfield
.class == Reg
&& i
.types
[x
].bitfield
.byte
5177 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
5179 gas_assert (!(i
.op
[x
].regs
->reg_flags
& RegRex
));
5180 /* In case it is "hi" register, give up. */
5181 if (i
.op
[x
].regs
->reg_num
> 3)
5182 as_bad (_("can't encode register '%s%s' in an "
5183 "instruction requiring REX prefix."),
5184 register_prefix
, i
.op
[x
].regs
->reg_name
);
5186 /* Otherwise it is equivalent to the extended register.
5187 Since the encoding doesn't change this is merely
5188 cosmetic cleanup for debug output. */
5190 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
5195 if (i
.rex
== 0 && i
.rex_encoding
)
5197 /* Check if we can add a REX_OPCODE byte. Look for 8 bit operand
5198 that uses legacy register. If it is "hi" register, don't add
5199 the REX_OPCODE byte. */
5201 for (x
= 0; x
< 2; x
++)
5202 if (i
.types
[x
].bitfield
.class == Reg
5203 && i
.types
[x
].bitfield
.byte
5204 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0
5205 && i
.op
[x
].regs
->reg_num
> 3)
5207 gas_assert (!(i
.op
[x
].regs
->reg_flags
& RegRex
));
5208 i
.rex_encoding
= false;
5217 add_prefix (REX_OPCODE
| i
.rex
);
5219 insert_lfence_before ();
5221 /* We are ready to output the insn. */
5224 insert_lfence_after ();
5226 last_insn
.seg
= now_seg
;
5228 if (i
.tm
.opcode_modifier
.isprefix
)
5230 last_insn
.kind
= last_insn_prefix
;
5231 last_insn
.name
= i
.tm
.name
;
5232 last_insn
.file
= as_where (&last_insn
.line
);
5235 last_insn
.kind
= last_insn_other
;
5239 parse_insn (char *line
, char *mnemonic
)
5242 char *token_start
= l
;
5245 const insn_template
*t
;
5251 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
5256 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
5258 as_bad (_("no such instruction: `%s'"), token_start
);
5263 if (!is_space_char (*l
)
5264 && *l
!= END_OF_INSN
5266 || (*l
!= PREFIX_SEPARATOR
5269 as_bad (_("invalid character %s in mnemonic"),
5270 output_invalid (*l
));
5273 if (token_start
== l
)
5275 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
5276 as_bad (_("expecting prefix; got nothing"));
5278 as_bad (_("expecting mnemonic; got nothing"));
5282 /* Look up instruction (or prefix) via hash table. */
5283 current_templates
= (const templates
*) str_hash_find (op_hash
, mnemonic
);
5285 if (*l
!= END_OF_INSN
5286 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
5287 && current_templates
5288 && current_templates
->start
->opcode_modifier
.isprefix
)
5290 if (!cpu_flags_check_cpu64 (current_templates
->start
->cpu_flags
))
5292 as_bad ((flag_code
!= CODE_64BIT
5293 ? _("`%s' is only supported in 64-bit mode")
5294 : _("`%s' is not supported in 64-bit mode")),
5295 current_templates
->start
->name
);
5298 /* If we are in 16-bit mode, do not allow addr16 or data16.
5299 Similarly, in 32-bit mode, do not allow addr32 or data32. */
5300 if ((current_templates
->start
->opcode_modifier
.size
== SIZE16
5301 || current_templates
->start
->opcode_modifier
.size
== SIZE32
)
5302 && flag_code
!= CODE_64BIT
5303 && ((current_templates
->start
->opcode_modifier
.size
== SIZE32
)
5304 ^ (flag_code
== CODE_16BIT
)))
5306 as_bad (_("redundant %s prefix"),
5307 current_templates
->start
->name
);
5311 if (current_templates
->start
->base_opcode
== PSEUDO_PREFIX
)
5313 /* Handle pseudo prefixes. */
5314 switch (current_templates
->start
->extension_opcode
)
5318 i
.disp_encoding
= disp_encoding_8bit
;
5322 i
.disp_encoding
= disp_encoding_16bit
;
5326 i
.disp_encoding
= disp_encoding_32bit
;
5330 i
.dir_encoding
= dir_encoding_load
;
5334 i
.dir_encoding
= dir_encoding_store
;
5338 i
.vec_encoding
= vex_encoding_vex
;
5342 i
.vec_encoding
= vex_encoding_vex3
;
5346 i
.vec_encoding
= vex_encoding_evex
;
5350 i
.rex_encoding
= true;
5352 case Prefix_NoOptimize
:
5354 i
.no_optimize
= true;
5362 /* Add prefix, checking for repeated prefixes. */
5363 switch (add_prefix (current_templates
->start
->base_opcode
))
5368 if (current_templates
->start
->cpu_flags
.bitfield
.cpuibt
)
5369 i
.notrack_prefix
= current_templates
->start
->name
;
5372 if (current_templates
->start
->cpu_flags
.bitfield
.cpuhle
)
5373 i
.hle_prefix
= current_templates
->start
->name
;
5374 else if (current_templates
->start
->cpu_flags
.bitfield
.cpumpx
)
5375 i
.bnd_prefix
= current_templates
->start
->name
;
5377 i
.rep_prefix
= current_templates
->start
->name
;
5383 /* Skip past PREFIX_SEPARATOR and reset token_start. */
5390 if (!current_templates
)
5392 /* Deprecated functionality (new code should use pseudo-prefixes instead):
5393 Check if we should swap operand or force 32bit displacement in
5395 if (mnem_p
- 2 == dot_p
&& dot_p
[1] == 's')
5396 i
.dir_encoding
= dir_encoding_swap
;
5397 else if (mnem_p
- 3 == dot_p
5400 i
.disp_encoding
= disp_encoding_8bit
;
5401 else if (mnem_p
- 4 == dot_p
5405 i
.disp_encoding
= disp_encoding_32bit
;
5410 current_templates
= (const templates
*) str_hash_find (op_hash
, mnemonic
);
5413 if (!current_templates
)
5416 if (mnem_p
> mnemonic
)
5418 /* See if we can get a match by trimming off a suffix. */
5421 case WORD_MNEM_SUFFIX
:
5422 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
5423 i
.suffix
= SHORT_MNEM_SUFFIX
;
5426 case BYTE_MNEM_SUFFIX
:
5427 case QWORD_MNEM_SUFFIX
:
5428 i
.suffix
= mnem_p
[-1];
5431 = (const templates
*) str_hash_find (op_hash
, mnemonic
);
5433 case SHORT_MNEM_SUFFIX
:
5434 case LONG_MNEM_SUFFIX
:
5437 i
.suffix
= mnem_p
[-1];
5440 = (const templates
*) str_hash_find (op_hash
, mnemonic
);
5448 if (intel_float_operand (mnemonic
) == 1)
5449 i
.suffix
= SHORT_MNEM_SUFFIX
;
5451 i
.suffix
= LONG_MNEM_SUFFIX
;
5454 = (const templates
*) str_hash_find (op_hash
, mnemonic
);
5460 if (!current_templates
)
5462 as_bad (_("no such instruction: `%s'"), token_start
);
5467 if (current_templates
->start
->opcode_modifier
.jump
== JUMP
5468 || current_templates
->start
->opcode_modifier
.jump
== JUMP_BYTE
)
5470 /* Check for a branch hint. We allow ",pt" and ",pn" for
5471 predict taken and predict not taken respectively.
5472 I'm not sure that branch hints actually do anything on loop
5473 and jcxz insns (JumpByte) for current Pentium4 chips. They
5474 may work in the future and it doesn't hurt to accept them
5476 if (l
[0] == ',' && l
[1] == 'p')
5480 if (!add_prefix (DS_PREFIX_OPCODE
))
5484 else if (l
[2] == 'n')
5486 if (!add_prefix (CS_PREFIX_OPCODE
))
5492 /* Any other comma loses. */
5495 as_bad (_("invalid character %s in mnemonic"),
5496 output_invalid (*l
));
5500 /* Check if instruction is supported on specified architecture. */
5502 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
5504 supported
|= cpu_flags_match (t
);
5505 if (supported
== CPU_FLAGS_PERFECT_MATCH
)
5507 if (!cpu_arch_flags
.bitfield
.cpui386
&& (flag_code
!= CODE_16BIT
))
5508 as_warn (_("use .code16 to ensure correct addressing mode"));
5514 if (!(supported
& CPU_FLAGS_64BIT_MATCH
))
5515 as_bad (flag_code
== CODE_64BIT
5516 ? _("`%s' is not supported in 64-bit mode")
5517 : _("`%s' is only supported in 64-bit mode"),
5518 current_templates
->start
->name
);
5520 as_bad (_("`%s' is not supported on `%s%s'"),
5521 current_templates
->start
->name
,
5522 cpu_arch_name
? cpu_arch_name
: default_arch
,
5523 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
5529 parse_operands (char *l
, const char *mnemonic
)
5533 /* 1 if operand is pending after ','. */
5534 unsigned int expecting_operand
= 0;
5536 /* Non-zero if operand parens not balanced. */
5537 unsigned int paren_not_balanced
;
5539 while (*l
!= END_OF_INSN
)
5541 /* Skip optional white space before operand. */
5542 if (is_space_char (*l
))
5544 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
&& *l
!= '"')
5546 as_bad (_("invalid character %s before operand %d"),
5547 output_invalid (*l
),
5551 token_start
= l
; /* After white space. */
5552 paren_not_balanced
= 0;
5553 while (paren_not_balanced
|| *l
!= ',')
5555 if (*l
== END_OF_INSN
)
5557 if (paren_not_balanced
)
5560 as_bad (_("unbalanced parenthesis in operand %d."),
5563 as_bad (_("unbalanced brackets in operand %d."),
5568 break; /* we are done */
5570 else if (!is_operand_char (*l
) && !is_space_char (*l
) && *l
!= '"')
5572 as_bad (_("invalid character %s in operand %d"),
5573 output_invalid (*l
),
5580 ++paren_not_balanced
;
5582 --paren_not_balanced
;
5587 ++paren_not_balanced
;
5589 --paren_not_balanced
;
5593 if (l
!= token_start
)
5594 { /* Yes, we've read in another operand. */
5595 unsigned int operand_ok
;
5596 this_operand
= i
.operands
++;
5597 if (i
.operands
> MAX_OPERANDS
)
5599 as_bad (_("spurious operands; (%d operands/instruction max)"),
5603 i
.types
[this_operand
].bitfield
.unspecified
= 1;
5604 /* Now parse operand adding info to 'i' as we go along. */
5605 END_STRING_AND_SAVE (l
);
5607 if (i
.mem_operands
> 1)
5609 as_bad (_("too many memory references for `%s'"),
5616 i386_intel_operand (token_start
,
5617 intel_float_operand (mnemonic
));
5619 operand_ok
= i386_att_operand (token_start
);
5621 RESTORE_END_STRING (l
);
5627 if (expecting_operand
)
5629 expecting_operand_after_comma
:
5630 as_bad (_("expecting operand after ','; got nothing"));
5635 as_bad (_("expecting operand before ','; got nothing"));
5640 /* Now *l must be either ',' or END_OF_INSN. */
5643 if (*++l
== END_OF_INSN
)
5645 /* Just skip it, if it's \n complain. */
5646 goto expecting_operand_after_comma
;
5648 expecting_operand
= 1;
5655 swap_2_operands (unsigned int xchg1
, unsigned int xchg2
)
5657 union i386_op temp_op
;
5658 i386_operand_type temp_type
;
5659 unsigned int temp_flags
;
5660 enum bfd_reloc_code_real temp_reloc
;
5662 temp_type
= i
.types
[xchg2
];
5663 i
.types
[xchg2
] = i
.types
[xchg1
];
5664 i
.types
[xchg1
] = temp_type
;
5666 temp_flags
= i
.flags
[xchg2
];
5667 i
.flags
[xchg2
] = i
.flags
[xchg1
];
5668 i
.flags
[xchg1
] = temp_flags
;
5670 temp_op
= i
.op
[xchg2
];
5671 i
.op
[xchg2
] = i
.op
[xchg1
];
5672 i
.op
[xchg1
] = temp_op
;
5674 temp_reloc
= i
.reloc
[xchg2
];
5675 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
5676 i
.reloc
[xchg1
] = temp_reloc
;
5680 if (i
.mask
.operand
== xchg1
)
5681 i
.mask
.operand
= xchg2
;
5682 else if (i
.mask
.operand
== xchg2
)
5683 i
.mask
.operand
= xchg1
;
5685 if (i
.broadcast
.type
)
5687 if (i
.broadcast
.operand
== xchg1
)
5688 i
.broadcast
.operand
= xchg2
;
5689 else if (i
.broadcast
.operand
== xchg2
)
5690 i
.broadcast
.operand
= xchg1
;
5692 if (i
.rounding
.type
!= rc_none
)
5694 if (i
.rounding
.operand
== xchg1
)
5695 i
.rounding
.operand
= xchg2
;
5696 else if (i
.rounding
.operand
== xchg2
)
5697 i
.rounding
.operand
= xchg1
;
5702 swap_operands (void)
5708 swap_2_operands (1, i
.operands
- 2);
5712 swap_2_operands (0, i
.operands
- 1);
5718 if (i
.mem_operands
== 2)
5720 const reg_entry
*temp_seg
;
5721 temp_seg
= i
.seg
[0];
5722 i
.seg
[0] = i
.seg
[1];
5723 i
.seg
[1] = temp_seg
;
5727 /* Try to ensure constant immediates are represented in the smallest
5732 char guess_suffix
= 0;
5736 guess_suffix
= i
.suffix
;
5737 else if (i
.reg_operands
)
5739 /* Figure out a suffix from the last register operand specified.
5740 We can't do this properly yet, i.e. excluding special register
5741 instances, but the following works for instructions with
5742 immediates. In any case, we can't set i.suffix yet. */
5743 for (op
= i
.operands
; --op
>= 0;)
5744 if (i
.types
[op
].bitfield
.class != Reg
)
5746 else if (i
.types
[op
].bitfield
.byte
)
5748 guess_suffix
= BYTE_MNEM_SUFFIX
;
5751 else if (i
.types
[op
].bitfield
.word
)
5753 guess_suffix
= WORD_MNEM_SUFFIX
;
5756 else if (i
.types
[op
].bitfield
.dword
)
5758 guess_suffix
= LONG_MNEM_SUFFIX
;
5761 else if (i
.types
[op
].bitfield
.qword
)
5763 guess_suffix
= QWORD_MNEM_SUFFIX
;
5767 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
5768 guess_suffix
= WORD_MNEM_SUFFIX
;
5770 for (op
= i
.operands
; --op
>= 0;)
5771 if (operand_type_check (i
.types
[op
], imm
))
5773 switch (i
.op
[op
].imms
->X_op
)
5776 /* If a suffix is given, this operand may be shortened. */
5777 switch (guess_suffix
)
5779 case LONG_MNEM_SUFFIX
:
5780 i
.types
[op
].bitfield
.imm32
= 1;
5781 i
.types
[op
].bitfield
.imm64
= 1;
5783 case WORD_MNEM_SUFFIX
:
5784 i
.types
[op
].bitfield
.imm16
= 1;
5785 i
.types
[op
].bitfield
.imm32
= 1;
5786 i
.types
[op
].bitfield
.imm32s
= 1;
5787 i
.types
[op
].bitfield
.imm64
= 1;
5789 case BYTE_MNEM_SUFFIX
:
5790 i
.types
[op
].bitfield
.imm8
= 1;
5791 i
.types
[op
].bitfield
.imm8s
= 1;
5792 i
.types
[op
].bitfield
.imm16
= 1;
5793 i
.types
[op
].bitfield
.imm32
= 1;
5794 i
.types
[op
].bitfield
.imm32s
= 1;
5795 i
.types
[op
].bitfield
.imm64
= 1;
5799 /* If this operand is at most 16 bits, convert it
5800 to a signed 16 bit number before trying to see
5801 whether it will fit in an even smaller size.
5802 This allows a 16-bit operand such as $0xffe0 to
5803 be recognised as within Imm8S range. */
5804 if ((i
.types
[op
].bitfield
.imm16
)
5805 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
5807 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
5808 ^ 0x8000) - 0x8000);
5811 /* Store 32-bit immediate in 64-bit for 64-bit BFD. */
5812 if ((i
.types
[op
].bitfield
.imm32
)
5813 && ((i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1))
5816 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
5817 ^ ((offsetT
) 1 << 31))
5818 - ((offsetT
) 1 << 31));
5822 = operand_type_or (i
.types
[op
],
5823 smallest_imm_type (i
.op
[op
].imms
->X_add_number
));
5825 /* We must avoid matching of Imm32 templates when 64bit
5826 only immediate is available. */
5827 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
5828 i
.types
[op
].bitfield
.imm32
= 0;
5835 /* Symbols and expressions. */
5837 /* Convert symbolic operand to proper sizes for matching, but don't
5838 prevent matching a set of insns that only supports sizes other
5839 than those matching the insn suffix. */
5841 i386_operand_type mask
, allowed
;
5842 const insn_template
*t
= current_templates
->start
;
5844 operand_type_set (&mask
, 0);
5845 allowed
= t
->operand_types
[op
];
5847 while (++t
< current_templates
->end
)
5849 allowed
= operand_type_and (allowed
, anyimm
);
5850 allowed
= operand_type_or (allowed
, t
->operand_types
[op
]);
5852 switch (guess_suffix
)
5854 case QWORD_MNEM_SUFFIX
:
5855 mask
.bitfield
.imm64
= 1;
5856 mask
.bitfield
.imm32s
= 1;
5858 case LONG_MNEM_SUFFIX
:
5859 mask
.bitfield
.imm32
= 1;
5861 case WORD_MNEM_SUFFIX
:
5862 mask
.bitfield
.imm16
= 1;
5864 case BYTE_MNEM_SUFFIX
:
5865 mask
.bitfield
.imm8
= 1;
5870 allowed
= operand_type_and (mask
, allowed
);
5871 if (!operand_type_all_zero (&allowed
))
5872 i
.types
[op
] = operand_type_and (i
.types
[op
], mask
);
5879 /* Try to use the smallest displacement type too. */
5881 optimize_disp (void)
5885 for (op
= i
.operands
; --op
>= 0;)
5886 if (operand_type_check (i
.types
[op
], disp
))
5888 if (i
.op
[op
].disps
->X_op
== O_constant
)
5890 offsetT op_disp
= i
.op
[op
].disps
->X_add_number
;
5892 if (i
.types
[op
].bitfield
.disp16
5893 && (op_disp
& ~(offsetT
) 0xffff) == 0)
5895 /* If this operand is at most 16 bits, convert
5896 to a signed 16 bit number and don't use 64bit
5898 op_disp
= (((op_disp
& 0xffff) ^ 0x8000) - 0x8000);
5899 i
.types
[op
].bitfield
.disp64
= 0;
5901 if (!op_disp
&& i
.types
[op
].bitfield
.baseindex
)
5903 i
.types
[op
].bitfield
.disp8
= 0;
5904 i
.types
[op
].bitfield
.disp16
= 0;
5905 i
.types
[op
].bitfield
.disp32
= 0;
5906 i
.types
[op
].bitfield
.disp32s
= 0;
5907 i
.types
[op
].bitfield
.disp64
= 0;
5912 else if (flag_code
== CODE_64BIT
)
5914 if (want_disp32 (current_templates
->start
)
5915 && fits_in_unsigned_long (op_disp
))
5916 i
.types
[op
].bitfield
.disp32
= 1;
5918 /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */
5919 if (i
.types
[op
].bitfield
.disp32
5920 && (op_disp
& ~(((offsetT
) 2 << 31) - 1)) == 0)
5922 /* If this operand is at most 32 bits, convert
5923 to a signed 32 bit number and don't use 64bit
5925 op_disp
&= (((offsetT
) 2 << 31) - 1);
5926 op_disp
= (op_disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
5927 i
.types
[op
].bitfield
.disp64
= 0;
5930 if (fits_in_signed_long (op_disp
))
5932 i
.types
[op
].bitfield
.disp64
= 0;
5933 i
.types
[op
].bitfield
.disp32s
= 1;
5937 if ((i
.types
[op
].bitfield
.disp32
5938 || i
.types
[op
].bitfield
.disp32s
5939 || i
.types
[op
].bitfield
.disp16
)
5940 && fits_in_disp8 (op_disp
))
5941 i
.types
[op
].bitfield
.disp8
= 1;
5943 else if (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
5944 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
)
5946 fix_new_exp (frag_now
, frag_more (0) - frag_now
->fr_literal
, 0,
5947 i
.op
[op
].disps
, 0, i
.reloc
[op
]);
5948 i
.types
[op
].bitfield
.disp8
= 0;
5949 i
.types
[op
].bitfield
.disp16
= 0;
5950 i
.types
[op
].bitfield
.disp32
= 0;
5951 i
.types
[op
].bitfield
.disp32s
= 0;
5952 i
.types
[op
].bitfield
.disp64
= 0;
5955 /* We only support 64bit displacement on constants. */
5956 i
.types
[op
].bitfield
.disp64
= 0;
5960 /* Return 1 if there is a match in broadcast bytes between operand
5961 GIVEN and instruction template T. */
5964 match_broadcast_size (const insn_template
*t
, unsigned int given
)
5966 return ((t
->opcode_modifier
.broadcast
== BYTE_BROADCAST
5967 && i
.types
[given
].bitfield
.byte
)
5968 || (t
->opcode_modifier
.broadcast
== WORD_BROADCAST
5969 && i
.types
[given
].bitfield
.word
)
5970 || (t
->opcode_modifier
.broadcast
== DWORD_BROADCAST
5971 && i
.types
[given
].bitfield
.dword
)
5972 || (t
->opcode_modifier
.broadcast
== QWORD_BROADCAST
5973 && i
.types
[given
].bitfield
.qword
));
5976 /* Check if operands are valid for the instruction. */
5979 check_VecOperands (const insn_template
*t
)
5984 /* Templates allowing for ZMMword as well as YMMword and/or XMMword for
5985 any one operand are implicity requiring AVX512VL support if the actual
5986 operand size is YMMword or XMMword. Since this function runs after
5987 template matching, there's no need to check for YMMword/XMMword in
5989 cpu
= cpu_flags_and (t
->cpu_flags
, avx512
);
5990 if (!cpu_flags_all_zero (&cpu
)
5991 && !t
->cpu_flags
.bitfield
.cpuavx512vl
5992 && !cpu_arch_flags
.bitfield
.cpuavx512vl
)
5994 for (op
= 0; op
< t
->operands
; ++op
)
5996 if (t
->operand_types
[op
].bitfield
.zmmword
5997 && (i
.types
[op
].bitfield
.ymmword
5998 || i
.types
[op
].bitfield
.xmmword
))
6000 i
.error
= unsupported
;
6006 /* Without VSIB byte, we can't have a vector register for index. */
6007 if (!t
->opcode_modifier
.sib
6009 && (i
.index_reg
->reg_type
.bitfield
.xmmword
6010 || i
.index_reg
->reg_type
.bitfield
.ymmword
6011 || i
.index_reg
->reg_type
.bitfield
.zmmword
))
6013 i
.error
= unsupported_vector_index_register
;
6017 /* Check if default mask is allowed. */
6018 if (t
->opcode_modifier
.nodefmask
6019 && (!i
.mask
.reg
|| i
.mask
.reg
->reg_num
== 0))
6021 i
.error
= no_default_mask
;
6025 /* For VSIB byte, we need a vector register for index, and all vector
6026 registers must be distinct. */
6027 if (t
->opcode_modifier
.sib
&& t
->opcode_modifier
.sib
!= SIBMEM
)
6030 || !((t
->opcode_modifier
.sib
== VECSIB128
6031 && i
.index_reg
->reg_type
.bitfield
.xmmword
)
6032 || (t
->opcode_modifier
.sib
== VECSIB256
6033 && i
.index_reg
->reg_type
.bitfield
.ymmword
)
6034 || (t
->opcode_modifier
.sib
== VECSIB512
6035 && i
.index_reg
->reg_type
.bitfield
.zmmword
)))
6037 i
.error
= invalid_vsib_address
;
6041 gas_assert (i
.reg_operands
== 2 || i
.mask
.reg
);
6042 if (i
.reg_operands
== 2 && !i
.mask
.reg
)
6044 gas_assert (i
.types
[0].bitfield
.class == RegSIMD
);
6045 gas_assert (i
.types
[0].bitfield
.xmmword
6046 || i
.types
[0].bitfield
.ymmword
);
6047 gas_assert (i
.types
[2].bitfield
.class == RegSIMD
);
6048 gas_assert (i
.types
[2].bitfield
.xmmword
6049 || i
.types
[2].bitfield
.ymmword
);
6050 if (operand_check
== check_none
)
6052 if (register_number (i
.op
[0].regs
)
6053 != register_number (i
.index_reg
)
6054 && register_number (i
.op
[2].regs
)
6055 != register_number (i
.index_reg
)
6056 && register_number (i
.op
[0].regs
)
6057 != register_number (i
.op
[2].regs
))
6059 if (operand_check
== check_error
)
6061 i
.error
= invalid_vector_register_set
;
6064 as_warn (_("mask, index, and destination registers should be distinct"));
6066 else if (i
.reg_operands
== 1 && i
.mask
.reg
)
6068 if (i
.types
[1].bitfield
.class == RegSIMD
6069 && (i
.types
[1].bitfield
.xmmword
6070 || i
.types
[1].bitfield
.ymmword
6071 || i
.types
[1].bitfield
.zmmword
)
6072 && (register_number (i
.op
[1].regs
)
6073 == register_number (i
.index_reg
)))
6075 if (operand_check
== check_error
)
6077 i
.error
= invalid_vector_register_set
;
6080 if (operand_check
!= check_none
)
6081 as_warn (_("index and destination registers should be distinct"));
6086 /* For AMX instructions with three tmmword operands, all tmmword operand must be
6088 if (t
->operand_types
[0].bitfield
.tmmword
6089 && i
.reg_operands
== 3)
6091 if (register_number (i
.op
[0].regs
)
6092 == register_number (i
.op
[1].regs
)
6093 || register_number (i
.op
[0].regs
)
6094 == register_number (i
.op
[2].regs
)
6095 || register_number (i
.op
[1].regs
)
6096 == register_number (i
.op
[2].regs
))
6098 i
.error
= invalid_tmm_register_set
;
6103 /* Check if broadcast is supported by the instruction and is applied
6104 to the memory operand. */
6105 if (i
.broadcast
.type
)
6107 i386_operand_type type
, overlap
;
6109 /* Check if specified broadcast is supported in this instruction,
6110 and its broadcast bytes match the memory operand. */
6111 op
= i
.broadcast
.operand
;
6112 if (!t
->opcode_modifier
.broadcast
6113 || !(i
.flags
[op
] & Operand_Mem
)
6114 || (!i
.types
[op
].bitfield
.unspecified
6115 && !match_broadcast_size (t
, op
)))
6118 i
.error
= unsupported_broadcast
;
6122 i
.broadcast
.bytes
= ((1 << (t
->opcode_modifier
.broadcast
- 1))
6123 * i
.broadcast
.type
);
6124 operand_type_set (&type
, 0);
6125 switch (i
.broadcast
.bytes
)
6128 type
.bitfield
.word
= 1;
6131 type
.bitfield
.dword
= 1;
6134 type
.bitfield
.qword
= 1;
6137 type
.bitfield
.xmmword
= 1;
6140 type
.bitfield
.ymmword
= 1;
6143 type
.bitfield
.zmmword
= 1;
6149 overlap
= operand_type_and (type
, t
->operand_types
[op
]);
6150 if (t
->operand_types
[op
].bitfield
.class == RegSIMD
6151 && t
->operand_types
[op
].bitfield
.byte
6152 + t
->operand_types
[op
].bitfield
.word
6153 + t
->operand_types
[op
].bitfield
.dword
6154 + t
->operand_types
[op
].bitfield
.qword
> 1)
6156 overlap
.bitfield
.xmmword
= 0;
6157 overlap
.bitfield
.ymmword
= 0;
6158 overlap
.bitfield
.zmmword
= 0;
6160 if (operand_type_all_zero (&overlap
))
6163 if (t
->opcode_modifier
.checkregsize
)
6167 type
.bitfield
.baseindex
= 1;
6168 for (j
= 0; j
< i
.operands
; ++j
)
6171 && !operand_type_register_match(i
.types
[j
],
6172 t
->operand_types
[j
],
6174 t
->operand_types
[op
]))
6179 /* If broadcast is supported in this instruction, we need to check if
6180 operand of one-element size isn't specified without broadcast. */
6181 else if (t
->opcode_modifier
.broadcast
&& i
.mem_operands
)
6183 /* Find memory operand. */
6184 for (op
= 0; op
< i
.operands
; op
++)
6185 if (i
.flags
[op
] & Operand_Mem
)
6187 gas_assert (op
< i
.operands
);
6188 /* Check size of the memory operand. */
6189 if (match_broadcast_size (t
, op
))
6191 i
.error
= broadcast_needed
;
6196 op
= MAX_OPERANDS
- 1; /* Avoid uninitialized variable warning. */
6198 /* Check if requested masking is supported. */
6201 switch (t
->opcode_modifier
.masking
)
6205 case MERGING_MASKING
:
6209 i
.error
= unsupported_masking
;
6213 case DYNAMIC_MASKING
:
6214 /* Memory destinations allow only merging masking. */
6215 if (i
.mask
.zeroing
&& i
.mem_operands
)
6217 /* Find memory operand. */
6218 for (op
= 0; op
< i
.operands
; op
++)
6219 if (i
.flags
[op
] & Operand_Mem
)
6221 gas_assert (op
< i
.operands
);
6222 if (op
== i
.operands
- 1)
6224 i
.error
= unsupported_masking
;
6234 /* Check if masking is applied to dest operand. */
6235 if (i
.mask
.reg
&& (i
.mask
.operand
!= i
.operands
- 1))
6237 i
.error
= mask_not_on_destination
;
6242 if (i
.rounding
.type
!= rc_none
)
6244 if (!t
->opcode_modifier
.sae
6245 || (i
.rounding
.type
!= saeonly
&& !t
->opcode_modifier
.staticrounding
))
6247 i
.error
= unsupported_rc_sae
;
6250 /* If the instruction has several immediate operands and one of
6251 them is rounding, the rounding operand should be the last
6252 immediate operand. */
6253 if (i
.imm_operands
> 1
6254 && i
.rounding
.operand
!= i
.imm_operands
- 1)
6256 i
.error
= rc_sae_operand_not_last_imm
;
6261 /* Check the special Imm4 cases; must be the first operand. */
6262 if (t
->cpu_flags
.bitfield
.cpuxop
&& t
->operands
== 5)
6264 if (i
.op
[0].imms
->X_op
!= O_constant
6265 || !fits_in_imm4 (i
.op
[0].imms
->X_add_number
))
6271 /* Turn off Imm<N> so that update_imm won't complain. */
6272 operand_type_set (&i
.types
[0], 0);
6275 /* Check vector Disp8 operand. */
6276 if (t
->opcode_modifier
.disp8memshift
6277 && i
.disp_encoding
!= disp_encoding_32bit
)
6279 if (i
.broadcast
.type
)
6280 i
.memshift
= t
->opcode_modifier
.broadcast
- 1;
6281 else if (t
->opcode_modifier
.disp8memshift
!= DISP8_SHIFT_VL
)
6282 i
.memshift
= t
->opcode_modifier
.disp8memshift
;
6285 const i386_operand_type
*type
= NULL
;
6288 for (op
= 0; op
< i
.operands
; op
++)
6289 if (i
.flags
[op
] & Operand_Mem
)
6291 if (t
->opcode_modifier
.evex
== EVEXLIG
)
6292 i
.memshift
= 2 + (i
.suffix
== QWORD_MNEM_SUFFIX
);
6293 else if (t
->operand_types
[op
].bitfield
.xmmword
6294 + t
->operand_types
[op
].bitfield
.ymmword
6295 + t
->operand_types
[op
].bitfield
.zmmword
<= 1)
6296 type
= &t
->operand_types
[op
];
6297 else if (!i
.types
[op
].bitfield
.unspecified
)
6298 type
= &i
.types
[op
];
6300 else if (i
.types
[op
].bitfield
.class == RegSIMD
6301 && t
->opcode_modifier
.evex
!= EVEXLIG
)
6303 if (i
.types
[op
].bitfield
.zmmword
)
6305 else if (i
.types
[op
].bitfield
.ymmword
&& i
.memshift
< 5)
6307 else if (i
.types
[op
].bitfield
.xmmword
&& i
.memshift
< 4)
6313 if (type
->bitfield
.zmmword
)
6315 else if (type
->bitfield
.ymmword
)
6317 else if (type
->bitfield
.xmmword
)
6321 /* For the check in fits_in_disp8(). */
6322 if (i
.memshift
== 0)
6326 for (op
= 0; op
< i
.operands
; op
++)
6327 if (operand_type_check (i
.types
[op
], disp
)
6328 && i
.op
[op
].disps
->X_op
== O_constant
)
6330 if (fits_in_disp8 (i
.op
[op
].disps
->X_add_number
))
6332 i
.types
[op
].bitfield
.disp8
= 1;
6335 i
.types
[op
].bitfield
.disp8
= 0;
6344 /* Check if encoding requirements are met by the instruction. */
6347 VEX_check_encoding (const insn_template
*t
)
6349 if (i
.vec_encoding
== vex_encoding_error
)
6351 i
.error
= unsupported
;
6355 if (i
.vec_encoding
== vex_encoding_evex
)
6357 /* This instruction must be encoded with EVEX prefix. */
6358 if (!is_evex_encoding (t
))
6360 i
.error
= unsupported
;
6366 if (!t
->opcode_modifier
.vex
)
6368 /* This instruction template doesn't have VEX prefix. */
6369 if (i
.vec_encoding
!= vex_encoding_default
)
6371 i
.error
= unsupported
;
6380 static const insn_template
*
6381 match_template (char mnem_suffix
)
6383 /* Points to template once we've found it. */
6384 const insn_template
*t
;
6385 i386_operand_type overlap0
, overlap1
, overlap2
, overlap3
;
6386 i386_operand_type overlap4
;
6387 unsigned int found_reverse_match
;
6388 i386_opcode_modifier suffix_check
;
6389 i386_operand_type operand_types
[MAX_OPERANDS
];
6390 int addr_prefix_disp
;
6391 unsigned int j
, size_match
, check_register
;
6392 enum i386_error specific_error
= 0;
6394 #if MAX_OPERANDS != 5
6395 # error "MAX_OPERANDS must be 5."
6398 found_reverse_match
= 0;
6399 addr_prefix_disp
= -1;
6401 /* Prepare for mnemonic suffix check. */
6402 memset (&suffix_check
, 0, sizeof (suffix_check
));
6403 switch (mnem_suffix
)
6405 case BYTE_MNEM_SUFFIX
:
6406 suffix_check
.no_bsuf
= 1;
6408 case WORD_MNEM_SUFFIX
:
6409 suffix_check
.no_wsuf
= 1;
6411 case SHORT_MNEM_SUFFIX
:
6412 suffix_check
.no_ssuf
= 1;
6414 case LONG_MNEM_SUFFIX
:
6415 suffix_check
.no_lsuf
= 1;
6417 case QWORD_MNEM_SUFFIX
:
6418 suffix_check
.no_qsuf
= 1;
6421 /* NB: In Intel syntax, normally we can check for memory operand
6422 size when there is no mnemonic suffix. But jmp and call have
6423 2 different encodings with Dword memory operand size, one with
6424 No_ldSuf and the other without. i.suffix is set to
6425 LONG_DOUBLE_MNEM_SUFFIX to skip the one with No_ldSuf. */
6426 if (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
)
6427 suffix_check
.no_ldsuf
= 1;
6430 /* Must have right number of operands. */
6431 i
.error
= number_of_operands_mismatch
;
6433 for (t
= current_templates
->start
; t
< current_templates
->end
; t
++)
6435 addr_prefix_disp
= -1;
6436 found_reverse_match
= 0;
6438 if (i
.operands
!= t
->operands
)
6441 /* Check processor support. */
6442 i
.error
= unsupported
;
6443 if (cpu_flags_match (t
) != CPU_FLAGS_PERFECT_MATCH
)
6446 /* Check Pseudo Prefix. */
6447 i
.error
= unsupported
;
6448 if (t
->opcode_modifier
.pseudovexprefix
6449 && !(i
.vec_encoding
== vex_encoding_vex
6450 || i
.vec_encoding
== vex_encoding_vex3
))
6453 /* Check AT&T mnemonic. */
6454 i
.error
= unsupported_with_intel_mnemonic
;
6455 if (intel_mnemonic
&& t
->opcode_modifier
.attmnemonic
)
6458 /* Check AT&T/Intel syntax. */
6459 i
.error
= unsupported_syntax
;
6460 if ((intel_syntax
&& t
->opcode_modifier
.attsyntax
)
6461 || (!intel_syntax
&& t
->opcode_modifier
.intelsyntax
))
6464 /* Check Intel64/AMD64 ISA. */
6468 /* Default: Don't accept Intel64. */
6469 if (t
->opcode_modifier
.isa64
== INTEL64
)
6473 /* -mamd64: Don't accept Intel64 and Intel64 only. */
6474 if (t
->opcode_modifier
.isa64
>= INTEL64
)
6478 /* -mintel64: Don't accept AMD64. */
6479 if (t
->opcode_modifier
.isa64
== AMD64
&& flag_code
== CODE_64BIT
)
6484 /* Check the suffix. */
6485 i
.error
= invalid_instruction_suffix
;
6486 if ((t
->opcode_modifier
.no_bsuf
&& suffix_check
.no_bsuf
)
6487 || (t
->opcode_modifier
.no_wsuf
&& suffix_check
.no_wsuf
)
6488 || (t
->opcode_modifier
.no_lsuf
&& suffix_check
.no_lsuf
)
6489 || (t
->opcode_modifier
.no_ssuf
&& suffix_check
.no_ssuf
)
6490 || (t
->opcode_modifier
.no_qsuf
&& suffix_check
.no_qsuf
)
6491 || (t
->opcode_modifier
.no_ldsuf
&& suffix_check
.no_ldsuf
))
6494 size_match
= operand_size_match (t
);
6498 /* This is intentionally not
6500 if (i.jumpabsolute != (t->opcode_modifier.jump == JUMP_ABSOLUTE))
6502 as the case of a missing * on the operand is accepted (perhaps with
6503 a warning, issued further down). */
6504 if (i
.jumpabsolute
&& t
->opcode_modifier
.jump
!= JUMP_ABSOLUTE
)
6506 i
.error
= operand_type_mismatch
;
6510 for (j
= 0; j
< MAX_OPERANDS
; j
++)
6511 operand_types
[j
] = t
->operand_types
[j
];
6513 /* In general, don't allow
6514 - 64-bit operands outside of 64-bit mode,
6515 - 32-bit operands on pre-386. */
6516 j
= i
.imm_operands
+ (t
->operands
> i
.imm_operands
+ 1);
6517 if (((i
.suffix
== QWORD_MNEM_SUFFIX
6518 && flag_code
!= CODE_64BIT
6519 && !(t
->opcode_modifier
.opcodespace
== SPACE_0F
6520 && t
->base_opcode
== 0xc7
6521 && t
->opcode_modifier
.opcodeprefix
== PREFIX_NONE
6522 && t
->extension_opcode
== 1) /* cmpxchg8b */)
6523 || (i
.suffix
== LONG_MNEM_SUFFIX
6524 && !cpu_arch_flags
.bitfield
.cpui386
))
6526 ? (t
->opcode_modifier
.mnemonicsize
!= IGNORESIZE
6527 && !intel_float_operand (t
->name
))
6528 : intel_float_operand (t
->name
) != 2)
6529 && (t
->operands
== i
.imm_operands
6530 || (operand_types
[i
.imm_operands
].bitfield
.class != RegMMX
6531 && operand_types
[i
.imm_operands
].bitfield
.class != RegSIMD
6532 && operand_types
[i
.imm_operands
].bitfield
.class != RegMask
)
6533 || (operand_types
[j
].bitfield
.class != RegMMX
6534 && operand_types
[j
].bitfield
.class != RegSIMD
6535 && operand_types
[j
].bitfield
.class != RegMask
))
6536 && !t
->opcode_modifier
.sib
)
6539 /* Do not verify operands when there are none. */
6542 if (VEX_check_encoding (t
))
6544 specific_error
= i
.error
;
6548 /* We've found a match; break out of loop. */
6552 if (!t
->opcode_modifier
.jump
6553 || t
->opcode_modifier
.jump
== JUMP_ABSOLUTE
)
6555 /* There should be only one Disp operand. */
6556 for (j
= 0; j
< MAX_OPERANDS
; j
++)
6557 if (operand_type_check (operand_types
[j
], disp
))
6559 if (j
< MAX_OPERANDS
)
6561 bool override
= (i
.prefix
[ADDR_PREFIX
] != 0);
6563 addr_prefix_disp
= j
;
6565 /* Address size prefix will turn Disp64/Disp32S/Disp32/Disp16
6566 operand into Disp32/Disp32/Disp16/Disp32 operand. */
6570 override
= !override
;
6573 if (operand_types
[j
].bitfield
.disp32
6574 && operand_types
[j
].bitfield
.disp16
)
6576 operand_types
[j
].bitfield
.disp16
= override
;
6577 operand_types
[j
].bitfield
.disp32
= !override
;
6579 operand_types
[j
].bitfield
.disp32s
= 0;
6580 operand_types
[j
].bitfield
.disp64
= 0;
6584 if (operand_types
[j
].bitfield
.disp32s
6585 || operand_types
[j
].bitfield
.disp64
)
6587 operand_types
[j
].bitfield
.disp64
&= !override
;
6588 operand_types
[j
].bitfield
.disp32s
&= !override
;
6589 operand_types
[j
].bitfield
.disp32
= override
;
6591 operand_types
[j
].bitfield
.disp16
= 0;
6597 /* Force 0x8b encoding for "mov foo@GOT, %eax". */
6598 if (i
.reloc
[0] == BFD_RELOC_386_GOT32
6599 && t
->base_opcode
== 0xa0
6600 && t
->opcode_modifier
.opcodespace
== SPACE_BASE
)
6603 /* We check register size if needed. */
6604 if (t
->opcode_modifier
.checkregsize
)
6606 check_register
= (1 << t
->operands
) - 1;
6607 if (i
.broadcast
.type
)
6608 check_register
&= ~(1 << i
.broadcast
.operand
);
6613 overlap0
= operand_type_and (i
.types
[0], operand_types
[0]);
6614 switch (t
->operands
)
6617 if (!operand_type_match (overlap0
, i
.types
[0]))
6621 /* xchg %eax, %eax is a special case. It is an alias for nop
6622 only in 32bit mode and we can use opcode 0x90. In 64bit
6623 mode, we can't use 0x90 for xchg %eax, %eax since it should
6624 zero-extend %eax to %rax. */
6625 if (flag_code
== CODE_64BIT
6626 && t
->base_opcode
== 0x90
6627 && t
->opcode_modifier
.opcodespace
== SPACE_BASE
6628 && i
.types
[0].bitfield
.instance
== Accum
6629 && i
.types
[0].bitfield
.dword
6630 && i
.types
[1].bitfield
.instance
== Accum
6631 && i
.types
[1].bitfield
.dword
)
6633 /* xrelease mov %eax, <disp> is another special case. It must not
6634 match the accumulator-only encoding of mov. */
6635 if (flag_code
!= CODE_64BIT
6637 && t
->base_opcode
== 0xa0
6638 && t
->opcode_modifier
.opcodespace
== SPACE_BASE
6639 && i
.types
[0].bitfield
.instance
== Accum
6640 && (i
.flags
[1] & Operand_Mem
))
6645 if (!(size_match
& MATCH_STRAIGHT
))
6647 /* Reverse direction of operands if swapping is possible in the first
6648 place (operands need to be symmetric) and
6649 - the load form is requested, and the template is a store form,
6650 - the store form is requested, and the template is a load form,
6651 - the non-default (swapped) form is requested. */
6652 overlap1
= operand_type_and (operand_types
[0], operand_types
[1]);
6653 if (t
->opcode_modifier
.d
&& i
.reg_operands
== i
.operands
6654 && !operand_type_all_zero (&overlap1
))
6655 switch (i
.dir_encoding
)
6657 case dir_encoding_load
:
6658 if (operand_type_check (operand_types
[i
.operands
- 1], anymem
)
6659 || t
->opcode_modifier
.regmem
)
6663 case dir_encoding_store
:
6664 if (!operand_type_check (operand_types
[i
.operands
- 1], anymem
)
6665 && !t
->opcode_modifier
.regmem
)
6669 case dir_encoding_swap
:
6672 case dir_encoding_default
:
6675 /* If we want store form, we skip the current load. */
6676 if ((i
.dir_encoding
== dir_encoding_store
6677 || i
.dir_encoding
== dir_encoding_swap
)
6678 && i
.mem_operands
== 0
6679 && t
->opcode_modifier
.load
)
6684 overlap1
= operand_type_and (i
.types
[1], operand_types
[1]);
6685 if (!operand_type_match (overlap0
, i
.types
[0])
6686 || !operand_type_match (overlap1
, i
.types
[1])
6687 || ((check_register
& 3) == 3
6688 && !operand_type_register_match (i
.types
[0],
6693 /* Check if other direction is valid ... */
6694 if (!t
->opcode_modifier
.d
)
6698 if (!(size_match
& MATCH_REVERSE
))
6700 /* Try reversing direction of operands. */
6701 overlap0
= operand_type_and (i
.types
[0], operand_types
[i
.operands
- 1]);
6702 overlap1
= operand_type_and (i
.types
[i
.operands
- 1], operand_types
[0]);
6703 if (!operand_type_match (overlap0
, i
.types
[0])
6704 || !operand_type_match (overlap1
, i
.types
[i
.operands
- 1])
6706 && !operand_type_register_match (i
.types
[0],
6707 operand_types
[i
.operands
- 1],
6708 i
.types
[i
.operands
- 1],
6711 /* Does not match either direction. */
6714 /* found_reverse_match holds which of D or FloatR
6716 if (!t
->opcode_modifier
.d
)
6717 found_reverse_match
= 0;
6718 else if (operand_types
[0].bitfield
.tbyte
)
6719 found_reverse_match
= Opcode_FloatD
;
6720 else if (operand_types
[0].bitfield
.xmmword
6721 || operand_types
[i
.operands
- 1].bitfield
.xmmword
6722 || operand_types
[0].bitfield
.class == RegMMX
6723 || operand_types
[i
.operands
- 1].bitfield
.class == RegMMX
6724 || is_any_vex_encoding(t
))
6725 found_reverse_match
= (t
->base_opcode
& 0xee) != 0x6e
6726 ? Opcode_SIMD_FloatD
: Opcode_SIMD_IntD
;
6728 found_reverse_match
= Opcode_D
;
6729 if (t
->opcode_modifier
.floatr
)
6730 found_reverse_match
|= Opcode_FloatR
;
6734 /* Found a forward 2 operand match here. */
6735 switch (t
->operands
)
6738 overlap4
= operand_type_and (i
.types
[4],
6742 overlap3
= operand_type_and (i
.types
[3],
6746 overlap2
= operand_type_and (i
.types
[2],
6751 switch (t
->operands
)
6754 if (!operand_type_match (overlap4
, i
.types
[4])
6755 || !operand_type_register_match (i
.types
[3],
6762 if (!operand_type_match (overlap3
, i
.types
[3])
6763 || ((check_register
& 0xa) == 0xa
6764 && !operand_type_register_match (i
.types
[1],
6768 || ((check_register
& 0xc) == 0xc
6769 && !operand_type_register_match (i
.types
[2],
6776 /* Here we make use of the fact that there are no
6777 reverse match 3 operand instructions. */
6778 if (!operand_type_match (overlap2
, i
.types
[2])
6779 || ((check_register
& 5) == 5
6780 && !operand_type_register_match (i
.types
[0],
6784 || ((check_register
& 6) == 6
6785 && !operand_type_register_match (i
.types
[1],
6793 /* Found either forward/reverse 2, 3 or 4 operand match here:
6794 slip through to break. */
6797 /* Check if vector operands are valid. */
6798 if (check_VecOperands (t
))
6800 specific_error
= i
.error
;
6804 /* Check if VEX/EVEX encoding requirements can be satisfied. */
6805 if (VEX_check_encoding (t
))
6807 specific_error
= i
.error
;
6811 /* We've found a match; break out of loop. */
6815 if (t
== current_templates
->end
)
6817 /* We found no match. */
6818 const char *err_msg
;
6819 switch (specific_error
? specific_error
: i
.error
)
6823 case operand_size_mismatch
:
6824 err_msg
= _("operand size mismatch");
6826 case operand_type_mismatch
:
6827 err_msg
= _("operand type mismatch");
6829 case register_type_mismatch
:
6830 err_msg
= _("register type mismatch");
6832 case number_of_operands_mismatch
:
6833 err_msg
= _("number of operands mismatch");
6835 case invalid_instruction_suffix
:
6836 err_msg
= _("invalid instruction suffix");
6839 err_msg
= _("constant doesn't fit in 4 bits");
6841 case unsupported_with_intel_mnemonic
:
6842 err_msg
= _("unsupported with Intel mnemonic");
6844 case unsupported_syntax
:
6845 err_msg
= _("unsupported syntax");
6848 as_bad (_("unsupported instruction `%s'"),
6849 current_templates
->start
->name
);
6851 case invalid_sib_address
:
6852 err_msg
= _("invalid SIB address");
6854 case invalid_vsib_address
:
6855 err_msg
= _("invalid VSIB address");
6857 case invalid_vector_register_set
:
6858 err_msg
= _("mask, index, and destination registers must be distinct");
6860 case invalid_tmm_register_set
:
6861 err_msg
= _("all tmm registers must be distinct");
6863 case unsupported_vector_index_register
:
6864 err_msg
= _("unsupported vector index register");
6866 case unsupported_broadcast
:
6867 err_msg
= _("unsupported broadcast");
6869 case broadcast_needed
:
6870 err_msg
= _("broadcast is needed for operand of such type");
6872 case unsupported_masking
:
6873 err_msg
= _("unsupported masking");
6875 case mask_not_on_destination
:
6876 err_msg
= _("mask not on destination operand");
6878 case no_default_mask
:
6879 err_msg
= _("default mask isn't allowed");
6881 case unsupported_rc_sae
:
6882 err_msg
= _("unsupported static rounding/sae");
6884 case rc_sae_operand_not_last_imm
:
6886 err_msg
= _("RC/SAE operand must precede immediate operands");
6888 err_msg
= _("RC/SAE operand must follow immediate operands");
6890 case invalid_register_operand
:
6891 err_msg
= _("invalid register operand");
6894 as_bad (_("%s for `%s'"), err_msg
,
6895 current_templates
->start
->name
);
6899 if (!quiet_warnings
)
6902 && (i
.jumpabsolute
!= (t
->opcode_modifier
.jump
== JUMP_ABSOLUTE
)))
6903 as_warn (_("indirect %s without `*'"), t
->name
);
6905 if (t
->opcode_modifier
.isprefix
6906 && t
->opcode_modifier
.mnemonicsize
== IGNORESIZE
)
6908 /* Warn them that a data or address size prefix doesn't
6909 affect assembly of the next line of code. */
6910 as_warn (_("stand-alone `%s' prefix"), t
->name
);
6914 /* Copy the template we found. */
6915 install_template (t
);
6917 if (addr_prefix_disp
!= -1)
6918 i
.tm
.operand_types
[addr_prefix_disp
]
6919 = operand_types
[addr_prefix_disp
];
6921 if (found_reverse_match
)
6923 /* If we found a reverse match we must alter the opcode direction
6924 bit and clear/flip the regmem modifier one. found_reverse_match
6925 holds bits to change (different for int & float insns). */
6927 i
.tm
.base_opcode
^= found_reverse_match
;
6929 i
.tm
.operand_types
[0] = operand_types
[i
.operands
- 1];
6930 i
.tm
.operand_types
[i
.operands
- 1] = operand_types
[0];
6932 /* Certain SIMD insns have their load forms specified in the opcode
6933 table, and hence we need to _set_ RegMem instead of clearing it.
6934 We need to avoid setting the bit though on insns like KMOVW. */
6935 i
.tm
.opcode_modifier
.regmem
6936 = i
.tm
.opcode_modifier
.modrm
&& i
.tm
.opcode_modifier
.d
6937 && i
.tm
.operands
> 2U - i
.tm
.opcode_modifier
.sse2avx
6938 && !i
.tm
.opcode_modifier
.regmem
;
6947 unsigned int es_op
= i
.tm
.opcode_modifier
.isstring
- IS_STRING_ES_OP0
;
6948 unsigned int op
= i
.tm
.operand_types
[0].bitfield
.baseindex
? es_op
: 0;
6950 if (i
.seg
[op
] != NULL
&& i
.seg
[op
] != reg_es
)
6952 as_bad (_("`%s' operand %u must use `%ses' segment"),
6954 intel_syntax
? i
.tm
.operands
- es_op
: es_op
+ 1,
6959 /* There's only ever one segment override allowed per instruction.
6960 This instruction possibly has a legal segment override on the
6961 second operand, so copy the segment to where non-string
6962 instructions store it, allowing common code. */
6963 i
.seg
[op
] = i
.seg
[1];
6969 process_suffix (void)
6971 bool is_crc32
= false, is_movx
= false;
6973 /* If matched instruction specifies an explicit instruction mnemonic
6975 if (i
.tm
.opcode_modifier
.size
== SIZE16
)
6976 i
.suffix
= WORD_MNEM_SUFFIX
;
6977 else if (i
.tm
.opcode_modifier
.size
== SIZE32
)
6978 i
.suffix
= LONG_MNEM_SUFFIX
;
6979 else if (i
.tm
.opcode_modifier
.size
== SIZE64
)
6980 i
.suffix
= QWORD_MNEM_SUFFIX
;
6981 else if (i
.reg_operands
6982 && (i
.operands
> 1 || i
.types
[0].bitfield
.class == Reg
)
6983 && !i
.tm
.opcode_modifier
.addrprefixopreg
)
6985 unsigned int numop
= i
.operands
;
6988 is_movx
= (i
.tm
.opcode_modifier
.opcodespace
== SPACE_0F
6989 && (i
.tm
.base_opcode
| 8) == 0xbe)
6990 || (i
.tm
.opcode_modifier
.opcodespace
== SPACE_BASE
6991 && i
.tm
.base_opcode
== 0x63
6992 && i
.tm
.cpu_flags
.bitfield
.cpu64
);
6995 is_crc32
= (i
.tm
.base_opcode
== 0xf0
6996 && i
.tm
.opcode_modifier
.opcodespace
== SPACE_0F38
6997 && i
.tm
.opcode_modifier
.opcodeprefix
== PREFIX_0XF2
);
6999 /* movsx/movzx want only their source operand considered here, for the
7000 ambiguity checking below. The suffix will be replaced afterwards
7001 to represent the destination (register). */
7002 if (is_movx
&& (i
.tm
.opcode_modifier
.w
|| i
.tm
.base_opcode
== 0x63))
7005 /* crc32 needs REX.W set regardless of suffix / source operand size. */
7006 if (is_crc32
&& i
.tm
.operand_types
[1].bitfield
.qword
)
7009 /* If there's no instruction mnemonic suffix we try to invent one
7010 based on GPR operands. */
7013 /* We take i.suffix from the last register operand specified,
7014 Destination register type is more significant than source
7015 register type. crc32 in SSE4.2 prefers source register
7017 unsigned int op
= is_crc32
? 1 : i
.operands
;
7020 if (i
.tm
.operand_types
[op
].bitfield
.instance
== InstanceNone
7021 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7023 if (i
.types
[op
].bitfield
.class != Reg
)
7025 if (i
.types
[op
].bitfield
.byte
)
7026 i
.suffix
= BYTE_MNEM_SUFFIX
;
7027 else if (i
.types
[op
].bitfield
.word
)
7028 i
.suffix
= WORD_MNEM_SUFFIX
;
7029 else if (i
.types
[op
].bitfield
.dword
)
7030 i
.suffix
= LONG_MNEM_SUFFIX
;
7031 else if (i
.types
[op
].bitfield
.qword
)
7032 i
.suffix
= QWORD_MNEM_SUFFIX
;
7038 /* As an exception, movsx/movzx silently default to a byte source
7040 if (is_movx
&& i
.tm
.opcode_modifier
.w
&& !i
.suffix
&& !intel_syntax
)
7041 i
.suffix
= BYTE_MNEM_SUFFIX
;
7043 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
7046 && i
.tm
.opcode_modifier
.mnemonicsize
== IGNORESIZE
7047 && i
.tm
.opcode_modifier
.no_bsuf
)
7049 else if (!check_byte_reg ())
7052 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
7055 && i
.tm
.opcode_modifier
.mnemonicsize
== IGNORESIZE
7056 && i
.tm
.opcode_modifier
.no_lsuf
7057 && !i
.tm
.opcode_modifier
.todword
7058 && !i
.tm
.opcode_modifier
.toqword
)
7060 else if (!check_long_reg ())
7063 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
7066 && i
.tm
.opcode_modifier
.mnemonicsize
== IGNORESIZE
7067 && i
.tm
.opcode_modifier
.no_qsuf
7068 && !i
.tm
.opcode_modifier
.todword
7069 && !i
.tm
.opcode_modifier
.toqword
)
7071 else if (!check_qword_reg ())
7074 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
7077 && i
.tm
.opcode_modifier
.mnemonicsize
== IGNORESIZE
7078 && i
.tm
.opcode_modifier
.no_wsuf
)
7080 else if (!check_word_reg ())
7083 else if (intel_syntax
7084 && i
.tm
.opcode_modifier
.mnemonicsize
== IGNORESIZE
)
7085 /* Do nothing if the instruction is going to ignore the prefix. */
7090 /* Undo the movsx/movzx change done above. */
7093 else if (i
.tm
.opcode_modifier
.mnemonicsize
== DEFAULTSIZE
7096 i
.suffix
= stackop_size
;
7097 if (stackop_size
== LONG_MNEM_SUFFIX
)
7099 /* stackop_size is set to LONG_MNEM_SUFFIX for the
7100 .code16gcc directive to support 16-bit mode with
7101 32-bit address. For IRET without a suffix, generate
7102 16-bit IRET (opcode 0xcf) to return from an interrupt
7104 if (i
.tm
.base_opcode
== 0xcf)
7106 i
.suffix
= WORD_MNEM_SUFFIX
;
7107 as_warn (_("generating 16-bit `iret' for .code16gcc directive"));
7109 /* Warn about changed behavior for segment register push/pop. */
7110 else if ((i
.tm
.base_opcode
| 1) == 0x07)
7111 as_warn (_("generating 32-bit `%s', unlike earlier gas versions"),
7116 && (i
.tm
.opcode_modifier
.jump
== JUMP_ABSOLUTE
7117 || i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
7118 || i
.tm
.opcode_modifier
.jump
== JUMP_INTERSEGMENT
7119 || (i
.tm
.opcode_modifier
.opcodespace
== SPACE_0F
7120 && i
.tm
.base_opcode
== 0x01 /* [ls][gi]dt */
7121 && i
.tm
.extension_opcode
<= 3)))
7126 if (!i
.tm
.opcode_modifier
.no_qsuf
)
7128 if (i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
7129 || i
.tm
.opcode_modifier
.no_lsuf
)
7130 i
.suffix
= QWORD_MNEM_SUFFIX
;
7135 if (!i
.tm
.opcode_modifier
.no_lsuf
)
7136 i
.suffix
= LONG_MNEM_SUFFIX
;
7139 if (!i
.tm
.opcode_modifier
.no_wsuf
)
7140 i
.suffix
= WORD_MNEM_SUFFIX
;
7146 && (i
.tm
.opcode_modifier
.mnemonicsize
!= DEFAULTSIZE
7147 /* Also cover lret/retf/iret in 64-bit mode. */
7148 || (flag_code
== CODE_64BIT
7149 && !i
.tm
.opcode_modifier
.no_lsuf
7150 && !i
.tm
.opcode_modifier
.no_qsuf
))
7151 && i
.tm
.opcode_modifier
.mnemonicsize
!= IGNORESIZE
7152 /* Explicit sizing prefixes are assumed to disambiguate insns. */
7153 && !i
.prefix
[DATA_PREFIX
] && !(i
.prefix
[REX_PREFIX
] & REX_W
)
7154 /* Accept FLDENV et al without suffix. */
7155 && (i
.tm
.opcode_modifier
.no_ssuf
|| i
.tm
.opcode_modifier
.floatmf
))
7157 unsigned int suffixes
, evex
= 0;
7159 suffixes
= !i
.tm
.opcode_modifier
.no_bsuf
;
7160 if (!i
.tm
.opcode_modifier
.no_wsuf
)
7162 if (!i
.tm
.opcode_modifier
.no_lsuf
)
7164 if (!i
.tm
.opcode_modifier
.no_ldsuf
)
7166 if (!i
.tm
.opcode_modifier
.no_ssuf
)
7168 if (flag_code
== CODE_64BIT
&& !i
.tm
.opcode_modifier
.no_qsuf
)
7171 /* For [XYZ]MMWORD operands inspect operand sizes. While generally
7172 also suitable for AT&T syntax mode, it was requested that this be
7173 restricted to just Intel syntax. */
7174 if (intel_syntax
&& is_any_vex_encoding (&i
.tm
) && !i
.broadcast
.type
)
7178 for (op
= 0; op
< i
.tm
.operands
; ++op
)
7180 if (is_evex_encoding (&i
.tm
)
7181 && !cpu_arch_flags
.bitfield
.cpuavx512vl
)
7183 if (i
.tm
.operand_types
[op
].bitfield
.ymmword
)
7184 i
.tm
.operand_types
[op
].bitfield
.xmmword
= 0;
7185 if (i
.tm
.operand_types
[op
].bitfield
.zmmword
)
7186 i
.tm
.operand_types
[op
].bitfield
.ymmword
= 0;
7187 if (!i
.tm
.opcode_modifier
.evex
7188 || i
.tm
.opcode_modifier
.evex
== EVEXDYN
)
7189 i
.tm
.opcode_modifier
.evex
= EVEX512
;
7192 if (i
.tm
.operand_types
[op
].bitfield
.xmmword
7193 + i
.tm
.operand_types
[op
].bitfield
.ymmword
7194 + i
.tm
.operand_types
[op
].bitfield
.zmmword
< 2)
7197 /* Any properly sized operand disambiguates the insn. */
7198 if (i
.types
[op
].bitfield
.xmmword
7199 || i
.types
[op
].bitfield
.ymmword
7200 || i
.types
[op
].bitfield
.zmmword
)
7202 suffixes
&= ~(7 << 6);
7207 if ((i
.flags
[op
] & Operand_Mem
)
7208 && i
.tm
.operand_types
[op
].bitfield
.unspecified
)
7210 if (i
.tm
.operand_types
[op
].bitfield
.xmmword
)
7212 if (i
.tm
.operand_types
[op
].bitfield
.ymmword
)
7214 if (i
.tm
.operand_types
[op
].bitfield
.zmmword
)
7216 if (is_evex_encoding (&i
.tm
))
7222 /* Are multiple suffixes / operand sizes allowed? */
7223 if (suffixes
& (suffixes
- 1))
7226 && (i
.tm
.opcode_modifier
.mnemonicsize
!= DEFAULTSIZE
7227 || operand_check
== check_error
))
7229 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
7232 if (operand_check
== check_error
)
7234 as_bad (_("no instruction mnemonic suffix given and "
7235 "no register operands; can't size `%s'"), i
.tm
.name
);
7238 if (operand_check
== check_warning
)
7239 as_warn (_("%s; using default for `%s'"),
7241 ? _("ambiguous operand size")
7242 : _("no instruction mnemonic suffix given and "
7243 "no register operands"),
7246 if (i
.tm
.opcode_modifier
.floatmf
)
7247 i
.suffix
= SHORT_MNEM_SUFFIX
;
7249 /* handled below */;
7251 i
.tm
.opcode_modifier
.evex
= evex
;
7252 else if (flag_code
== CODE_16BIT
)
7253 i
.suffix
= WORD_MNEM_SUFFIX
;
7254 else if (!i
.tm
.opcode_modifier
.no_lsuf
)
7255 i
.suffix
= LONG_MNEM_SUFFIX
;
7257 i
.suffix
= QWORD_MNEM_SUFFIX
;
7263 /* In Intel syntax, movsx/movzx must have a "suffix" (checked above).
7264 In AT&T syntax, if there is no suffix (warned about above), the default
7265 will be byte extension. */
7266 if (i
.tm
.opcode_modifier
.w
&& i
.suffix
&& i
.suffix
!= BYTE_MNEM_SUFFIX
)
7267 i
.tm
.base_opcode
|= 1;
7269 /* For further processing, the suffix should represent the destination
7270 (register). This is already the case when one was used with
7271 mov[sz][bw]*, but we need to replace it for mov[sz]x, or if there was
7272 no suffix to begin with. */
7273 if (i
.tm
.opcode_modifier
.w
|| i
.tm
.base_opcode
== 0x63 || !i
.suffix
)
7275 if (i
.types
[1].bitfield
.word
)
7276 i
.suffix
= WORD_MNEM_SUFFIX
;
7277 else if (i
.types
[1].bitfield
.qword
)
7278 i
.suffix
= QWORD_MNEM_SUFFIX
;
7280 i
.suffix
= LONG_MNEM_SUFFIX
;
7282 i
.tm
.opcode_modifier
.w
= 0;
7286 if (!i
.tm
.opcode_modifier
.modrm
&& i
.reg_operands
&& i
.tm
.operands
< 3)
7287 i
.short_form
= (i
.tm
.operand_types
[0].bitfield
.class == Reg
)
7288 != (i
.tm
.operand_types
[1].bitfield
.class == Reg
);
7290 /* Change the opcode based on the operand size given by i.suffix. */
7293 /* Size floating point instruction. */
7294 case LONG_MNEM_SUFFIX
:
7295 if (i
.tm
.opcode_modifier
.floatmf
)
7297 i
.tm
.base_opcode
^= 4;
7301 case WORD_MNEM_SUFFIX
:
7302 case QWORD_MNEM_SUFFIX
:
7303 /* It's not a byte, select word/dword operation. */
7304 if (i
.tm
.opcode_modifier
.w
)
7307 i
.tm
.base_opcode
|= 8;
7309 i
.tm
.base_opcode
|= 1;
7312 case SHORT_MNEM_SUFFIX
:
7313 /* Now select between word & dword operations via the operand
7314 size prefix, except for instructions that will ignore this
7316 if (i
.suffix
!= QWORD_MNEM_SUFFIX
7317 && i
.tm
.opcode_modifier
.mnemonicsize
!= IGNORESIZE
7318 && !i
.tm
.opcode_modifier
.floatmf
7319 && !is_any_vex_encoding (&i
.tm
)
7320 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
7321 || (flag_code
== CODE_64BIT
7322 && i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
)))
7324 unsigned int prefix
= DATA_PREFIX_OPCODE
;
7326 if (i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
) /* jcxz, loop */
7327 prefix
= ADDR_PREFIX_OPCODE
;
7329 if (!add_prefix (prefix
))
7333 /* Set mode64 for an operand. */
7334 if (i
.suffix
== QWORD_MNEM_SUFFIX
7335 && flag_code
== CODE_64BIT
7336 && !i
.tm
.opcode_modifier
.norex64
7337 && !i
.tm
.opcode_modifier
.vexw
7338 /* Special case for xchg %rax,%rax. It is NOP and doesn't
7340 && ! (i
.operands
== 2
7341 && i
.tm
.base_opcode
== 0x90
7342 && i
.tm
.extension_opcode
== None
7343 && i
.types
[0].bitfield
.instance
== Accum
7344 && i
.types
[0].bitfield
.qword
7345 && i
.types
[1].bitfield
.instance
== Accum
7346 && i
.types
[1].bitfield
.qword
))
7352 /* Select word/dword/qword operation with explicit data sizing prefix
7353 when there are no suitable register operands. */
7354 if (i
.tm
.opcode_modifier
.w
7355 && (i
.prefix
[DATA_PREFIX
] || (i
.prefix
[REX_PREFIX
] & REX_W
))
7357 || (i
.reg_operands
== 1
7359 && (i
.tm
.operand_types
[0].bitfield
.instance
== RegC
7361 || i
.tm
.operand_types
[0].bitfield
.instance
== RegD
7362 || i
.tm
.operand_types
[1].bitfield
.instance
== RegD
7365 i
.tm
.base_opcode
|= 1;
7369 if (i
.tm
.opcode_modifier
.addrprefixopreg
)
7371 gas_assert (!i
.suffix
);
7372 gas_assert (i
.reg_operands
);
7374 if (i
.tm
.operand_types
[0].bitfield
.instance
== Accum
7377 /* The address size override prefix changes the size of the
7379 if (flag_code
== CODE_64BIT
7380 && i
.op
[0].regs
->reg_type
.bitfield
.word
)
7382 as_bad (_("16-bit addressing unavailable for `%s'"),
7387 if ((flag_code
== CODE_32BIT
7388 ? i
.op
[0].regs
->reg_type
.bitfield
.word
7389 : i
.op
[0].regs
->reg_type
.bitfield
.dword
)
7390 && !add_prefix (ADDR_PREFIX_OPCODE
))
7395 /* Check invalid register operand when the address size override
7396 prefix changes the size of register operands. */
7398 enum { need_word
, need_dword
, need_qword
} need
;
7400 /* Check the register operand for the address size prefix if
7401 the memory operand has no real registers, like symbol, DISP
7402 or bogus (x32-only) symbol(%rip) when symbol(%eip) is meant. */
7403 if (i
.mem_operands
== 1
7404 && i
.reg_operands
== 1
7406 && i
.types
[1].bitfield
.class == Reg
7407 && (flag_code
== CODE_32BIT
7408 ? i
.op
[1].regs
->reg_type
.bitfield
.word
7409 : i
.op
[1].regs
->reg_type
.bitfield
.dword
)
7410 && ((i
.base_reg
== NULL
&& i
.index_reg
== NULL
)
7411 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
7412 || (x86_elf_abi
== X86_64_X32_ABI
7414 && i
.base_reg
->reg_num
== RegIP
7415 && i
.base_reg
->reg_type
.bitfield
.qword
))
7419 && !add_prefix (ADDR_PREFIX_OPCODE
))
7422 if (flag_code
== CODE_32BIT
)
7423 need
= i
.prefix
[ADDR_PREFIX
] ? need_word
: need_dword
;
7424 else if (i
.prefix
[ADDR_PREFIX
])
7427 need
= flag_code
== CODE_64BIT
? need_qword
: need_word
;
7429 for (op
= 0; op
< i
.operands
; op
++)
7431 if (i
.types
[op
].bitfield
.class != Reg
)
7437 if (i
.op
[op
].regs
->reg_type
.bitfield
.word
)
7441 if (i
.op
[op
].regs
->reg_type
.bitfield
.dword
)
7445 if (i
.op
[op
].regs
->reg_type
.bitfield
.qword
)
7450 as_bad (_("invalid register operand size for `%s'"),
7461 check_byte_reg (void)
7465 for (op
= i
.operands
; --op
>= 0;)
7467 /* Skip non-register operands. */
7468 if (i
.types
[op
].bitfield
.class != Reg
)
7471 /* If this is an eight bit register, it's OK. If it's the 16 or
7472 32 bit version of an eight bit register, we will just use the
7473 low portion, and that's OK too. */
7474 if (i
.types
[op
].bitfield
.byte
)
7477 /* I/O port address operands are OK too. */
7478 if (i
.tm
.operand_types
[op
].bitfield
.instance
== RegD
7479 && i
.tm
.operand_types
[op
].bitfield
.word
)
7482 /* crc32 only wants its source operand checked here. */
7483 if (i
.tm
.base_opcode
== 0xf0
7484 && i
.tm
.opcode_modifier
.opcodespace
== SPACE_0F38
7485 && i
.tm
.opcode_modifier
.opcodeprefix
== PREFIX_0XF2
7489 /* Any other register is bad. */
7490 as_bad (_("`%s%s' not allowed with `%s%c'"),
7491 register_prefix
, i
.op
[op
].regs
->reg_name
,
7492 i
.tm
.name
, i
.suffix
);
7499 check_long_reg (void)
7503 for (op
= i
.operands
; --op
>= 0;)
7504 /* Skip non-register operands. */
7505 if (i
.types
[op
].bitfield
.class != Reg
)
7507 /* Reject eight bit registers, except where the template requires
7508 them. (eg. movzb) */
7509 else if (i
.types
[op
].bitfield
.byte
7510 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
7511 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7512 && (i
.tm
.operand_types
[op
].bitfield
.word
7513 || i
.tm
.operand_types
[op
].bitfield
.dword
))
7515 as_bad (_("`%s%s' not allowed with `%s%c'"),
7517 i
.op
[op
].regs
->reg_name
,
7522 /* Error if the e prefix on a general reg is missing. */
7523 else if (i
.types
[op
].bitfield
.word
7524 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
7525 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7526 && i
.tm
.operand_types
[op
].bitfield
.dword
)
7528 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
7529 register_prefix
, i
.op
[op
].regs
->reg_name
,
7533 /* Warn if the r prefix on a general reg is present. */
7534 else if (i
.types
[op
].bitfield
.qword
7535 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
7536 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7537 && i
.tm
.operand_types
[op
].bitfield
.dword
)
7540 && i
.tm
.opcode_modifier
.toqword
7541 && i
.types
[0].bitfield
.class != RegSIMD
)
7543 /* Convert to QWORD. We want REX byte. */
7544 i
.suffix
= QWORD_MNEM_SUFFIX
;
7548 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
7549 register_prefix
, i
.op
[op
].regs
->reg_name
,
7558 check_qword_reg (void)
7562 for (op
= i
.operands
; --op
>= 0; )
7563 /* Skip non-register operands. */
7564 if (i
.types
[op
].bitfield
.class != Reg
)
7566 /* Reject eight bit registers, except where the template requires
7567 them. (eg. movzb) */
7568 else if (i
.types
[op
].bitfield
.byte
7569 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
7570 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7571 && (i
.tm
.operand_types
[op
].bitfield
.word
7572 || i
.tm
.operand_types
[op
].bitfield
.dword
))
7574 as_bad (_("`%s%s' not allowed with `%s%c'"),
7576 i
.op
[op
].regs
->reg_name
,
7581 /* Warn if the r prefix on a general reg is missing. */
7582 else if ((i
.types
[op
].bitfield
.word
7583 || i
.types
[op
].bitfield
.dword
)
7584 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
7585 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7586 && i
.tm
.operand_types
[op
].bitfield
.qword
)
7588 /* Prohibit these changes in the 64bit mode, since the
7589 lowering is more complicated. */
7591 && i
.tm
.opcode_modifier
.todword
7592 && i
.types
[0].bitfield
.class != RegSIMD
)
7594 /* Convert to DWORD. We don't want REX byte. */
7595 i
.suffix
= LONG_MNEM_SUFFIX
;
7599 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
7600 register_prefix
, i
.op
[op
].regs
->reg_name
,
7609 check_word_reg (void)
7612 for (op
= i
.operands
; --op
>= 0;)
7613 /* Skip non-register operands. */
7614 if (i
.types
[op
].bitfield
.class != Reg
)
7616 /* Reject eight bit registers, except where the template requires
7617 them. (eg. movzb) */
7618 else if (i
.types
[op
].bitfield
.byte
7619 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
7620 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7621 && (i
.tm
.operand_types
[op
].bitfield
.word
7622 || i
.tm
.operand_types
[op
].bitfield
.dword
))
7624 as_bad (_("`%s%s' not allowed with `%s%c'"),
7626 i
.op
[op
].regs
->reg_name
,
7631 /* Error if the e or r prefix on a general reg is present. */
7632 else if ((i
.types
[op
].bitfield
.dword
7633 || i
.types
[op
].bitfield
.qword
)
7634 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
7635 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7636 && i
.tm
.operand_types
[op
].bitfield
.word
)
7638 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
7639 register_prefix
, i
.op
[op
].regs
->reg_name
,
7647 update_imm (unsigned int j
)
7649 i386_operand_type overlap
= i
.types
[j
];
7650 if ((overlap
.bitfield
.imm8
7651 || overlap
.bitfield
.imm8s
7652 || overlap
.bitfield
.imm16
7653 || overlap
.bitfield
.imm32
7654 || overlap
.bitfield
.imm32s
7655 || overlap
.bitfield
.imm64
)
7656 && !operand_type_equal (&overlap
, &imm8
)
7657 && !operand_type_equal (&overlap
, &imm8s
)
7658 && !operand_type_equal (&overlap
, &imm16
)
7659 && !operand_type_equal (&overlap
, &imm32
)
7660 && !operand_type_equal (&overlap
, &imm32s
)
7661 && !operand_type_equal (&overlap
, &imm64
))
7665 i386_operand_type temp
;
7667 operand_type_set (&temp
, 0);
7668 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
7670 temp
.bitfield
.imm8
= overlap
.bitfield
.imm8
;
7671 temp
.bitfield
.imm8s
= overlap
.bitfield
.imm8s
;
7673 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
7674 temp
.bitfield
.imm16
= overlap
.bitfield
.imm16
;
7675 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
7677 temp
.bitfield
.imm64
= overlap
.bitfield
.imm64
;
7678 temp
.bitfield
.imm32s
= overlap
.bitfield
.imm32s
;
7681 temp
.bitfield
.imm32
= overlap
.bitfield
.imm32
;
7684 else if (operand_type_equal (&overlap
, &imm16_32_32s
)
7685 || operand_type_equal (&overlap
, &imm16_32
)
7686 || operand_type_equal (&overlap
, &imm16_32s
))
7688 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
7693 else if (i
.prefix
[REX_PREFIX
] & REX_W
)
7694 overlap
= operand_type_and (overlap
, imm32s
);
7695 else if (i
.prefix
[DATA_PREFIX
])
7696 overlap
= operand_type_and (overlap
,
7697 flag_code
!= CODE_16BIT
? imm16
: imm32
);
7698 if (!operand_type_equal (&overlap
, &imm8
)
7699 && !operand_type_equal (&overlap
, &imm8s
)
7700 && !operand_type_equal (&overlap
, &imm16
)
7701 && !operand_type_equal (&overlap
, &imm32
)
7702 && !operand_type_equal (&overlap
, &imm32s
)
7703 && !operand_type_equal (&overlap
, &imm64
))
7705 as_bad (_("no instruction mnemonic suffix given; "
7706 "can't determine immediate size"));
7710 i
.types
[j
] = overlap
;
7720 /* Update the first 2 immediate operands. */
7721 n
= i
.operands
> 2 ? 2 : i
.operands
;
7724 for (j
= 0; j
< n
; j
++)
7725 if (update_imm (j
) == 0)
7728 /* The 3rd operand can't be immediate operand. */
7729 gas_assert (operand_type_check (i
.types
[2], imm
) == 0);
7736 process_operands (void)
7738 /* Default segment register this instruction will use for memory
7739 accesses. 0 means unknown. This is only for optimizing out
7740 unnecessary segment overrides. */
7741 const reg_entry
*default_seg
= NULL
;
7743 if (i
.tm
.opcode_modifier
.sse2avx
)
7745 /* Legacy encoded insns allow explicit REX prefixes, so these prefixes
7747 i
.rex
|= i
.prefix
[REX_PREFIX
] & (REX_W
| REX_R
| REX_X
| REX_B
);
7748 i
.prefix
[REX_PREFIX
] = 0;
7751 /* ImmExt should be processed after SSE2AVX. */
7752 else if (i
.tm
.opcode_modifier
.immext
)
7755 if (i
.tm
.opcode_modifier
.sse2avx
&& i
.tm
.opcode_modifier
.vexvvvv
)
7757 unsigned int dupl
= i
.operands
;
7758 unsigned int dest
= dupl
- 1;
7761 /* The destination must be an xmm register. */
7762 gas_assert (i
.reg_operands
7763 && MAX_OPERANDS
> dupl
7764 && operand_type_equal (&i
.types
[dest
], ®xmm
));
7766 if (i
.tm
.operand_types
[0].bitfield
.instance
== Accum
7767 && i
.tm
.operand_types
[0].bitfield
.xmmword
)
7769 if (i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
)
7771 /* Keep xmm0 for instructions with VEX prefix and 3
7773 i
.tm
.operand_types
[0].bitfield
.instance
= InstanceNone
;
7774 i
.tm
.operand_types
[0].bitfield
.class = RegSIMD
;
7779 /* We remove the first xmm0 and keep the number of
7780 operands unchanged, which in fact duplicates the
7782 for (j
= 1; j
< i
.operands
; j
++)
7784 i
.op
[j
- 1] = i
.op
[j
];
7785 i
.types
[j
- 1] = i
.types
[j
];
7786 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
7787 i
.flags
[j
- 1] = i
.flags
[j
];
7791 else if (i
.tm
.opcode_modifier
.implicit1stxmm0
)
7793 gas_assert ((MAX_OPERANDS
- 1) > dupl
7794 && (i
.tm
.opcode_modifier
.vexsources
7797 /* Add the implicit xmm0 for instructions with VEX prefix
7799 for (j
= i
.operands
; j
> 0; j
--)
7801 i
.op
[j
] = i
.op
[j
- 1];
7802 i
.types
[j
] = i
.types
[j
- 1];
7803 i
.tm
.operand_types
[j
] = i
.tm
.operand_types
[j
- 1];
7804 i
.flags
[j
] = i
.flags
[j
- 1];
7807 = (const reg_entry
*) str_hash_find (reg_hash
, "xmm0");
7808 i
.types
[0] = regxmm
;
7809 i
.tm
.operand_types
[0] = regxmm
;
7812 i
.reg_operands
+= 2;
7817 i
.op
[dupl
] = i
.op
[dest
];
7818 i
.types
[dupl
] = i
.types
[dest
];
7819 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
7820 i
.flags
[dupl
] = i
.flags
[dest
];
7829 i
.op
[dupl
] = i
.op
[dest
];
7830 i
.types
[dupl
] = i
.types
[dest
];
7831 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
7832 i
.flags
[dupl
] = i
.flags
[dest
];
7835 if (i
.tm
.opcode_modifier
.immext
)
7838 else if (i
.tm
.operand_types
[0].bitfield
.instance
== Accum
7839 && i
.tm
.operand_types
[0].bitfield
.xmmword
)
7843 for (j
= 1; j
< i
.operands
; j
++)
7845 i
.op
[j
- 1] = i
.op
[j
];
7846 i
.types
[j
- 1] = i
.types
[j
];
7848 /* We need to adjust fields in i.tm since they are used by
7849 build_modrm_byte. */
7850 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
7852 i
.flags
[j
- 1] = i
.flags
[j
];
7859 else if (i
.tm
.opcode_modifier
.implicitquadgroup
)
7861 unsigned int regnum
, first_reg_in_group
, last_reg_in_group
;
7863 /* The second operand must be {x,y,z}mmN, where N is a multiple of 4. */
7864 gas_assert (i
.operands
>= 2 && i
.types
[1].bitfield
.class == RegSIMD
);
7865 regnum
= register_number (i
.op
[1].regs
);
7866 first_reg_in_group
= regnum
& ~3;
7867 last_reg_in_group
= first_reg_in_group
+ 3;
7868 if (regnum
!= first_reg_in_group
)
7869 as_warn (_("source register `%s%s' implicitly denotes"
7870 " `%s%.3s%u' to `%s%.3s%u' source group in `%s'"),
7871 register_prefix
, i
.op
[1].regs
->reg_name
,
7872 register_prefix
, i
.op
[1].regs
->reg_name
, first_reg_in_group
,
7873 register_prefix
, i
.op
[1].regs
->reg_name
, last_reg_in_group
,
7876 else if (i
.tm
.opcode_modifier
.regkludge
)
7878 /* The imul $imm, %reg instruction is converted into
7879 imul $imm, %reg, %reg, and the clr %reg instruction
7880 is converted into xor %reg, %reg. */
7882 unsigned int first_reg_op
;
7884 if (operand_type_check (i
.types
[0], reg
))
7888 /* Pretend we saw the extra register operand. */
7889 gas_assert (i
.reg_operands
== 1
7890 && i
.op
[first_reg_op
+ 1].regs
== 0);
7891 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
7892 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
7897 if (i
.tm
.opcode_modifier
.modrm
)
7899 /* The opcode is completed (modulo i.tm.extension_opcode which
7900 must be put into the modrm byte). Now, we make the modrm and
7901 index base bytes based on all the info we've collected. */
7903 default_seg
= build_modrm_byte ();
7905 else if (i
.types
[0].bitfield
.class == SReg
)
7907 if (flag_code
!= CODE_64BIT
7908 ? i
.tm
.base_opcode
== POP_SEG_SHORT
7909 && i
.op
[0].regs
->reg_num
== 1
7910 : (i
.tm
.base_opcode
| 1) == (POP_SEG386_SHORT
& 0xff)
7911 && i
.op
[0].regs
->reg_num
< 4)
7913 as_bad (_("you can't `%s %s%s'"),
7914 i
.tm
.name
, register_prefix
, i
.op
[0].regs
->reg_name
);
7917 if (i
.op
[0].regs
->reg_num
> 3
7918 && i
.tm
.opcode_modifier
.opcodespace
== SPACE_BASE
)
7920 i
.tm
.base_opcode
^= (POP_SEG_SHORT
^ POP_SEG386_SHORT
) & 0xff;
7921 i
.tm
.opcode_modifier
.opcodespace
= SPACE_0F
;
7923 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
7925 else if (i
.tm
.opcode_modifier
.opcodespace
== SPACE_BASE
7926 && (i
.tm
.base_opcode
& ~3) == MOV_AX_DISP32
)
7928 default_seg
= reg_ds
;
7930 else if (i
.tm
.opcode_modifier
.isstring
)
7932 /* For the string instructions that allow a segment override
7933 on one of their operands, the default segment is ds. */
7934 default_seg
= reg_ds
;
7936 else if (i
.short_form
)
7938 /* The register or float register operand is in operand
7940 unsigned int op
= i
.tm
.operand_types
[0].bitfield
.class != Reg
;
7942 /* Register goes in low 3 bits of opcode. */
7943 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
7944 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
7946 if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
7948 /* Warn about some common errors, but press on regardless.
7949 The first case can be generated by gcc (<= 2.8.1). */
7950 if (i
.operands
== 2)
7952 /* Reversed arguments on faddp, fsubp, etc. */
7953 as_warn (_("translating to `%s %s%s,%s%s'"), i
.tm
.name
,
7954 register_prefix
, i
.op
[!intel_syntax
].regs
->reg_name
,
7955 register_prefix
, i
.op
[intel_syntax
].regs
->reg_name
);
7959 /* Extraneous `l' suffix on fp insn. */
7960 as_warn (_("translating to `%s %s%s'"), i
.tm
.name
,
7961 register_prefix
, i
.op
[0].regs
->reg_name
);
7966 if ((i
.seg
[0] || i
.prefix
[SEG_PREFIX
])
7967 && i
.tm
.base_opcode
== 0x8d /* lea */
7968 && i
.tm
.opcode_modifier
.opcodespace
== SPACE_BASE
7969 && !is_any_vex_encoding(&i
.tm
))
7971 if (!quiet_warnings
)
7972 as_warn (_("segment override on `%s' is ineffectual"), i
.tm
.name
);
7976 i
.prefix
[SEG_PREFIX
] = 0;
7980 /* If a segment was explicitly specified, and the specified segment
7981 is neither the default nor the one already recorded from a prefix,
7982 use an opcode prefix to select it. If we never figured out what
7983 the default segment is, then default_seg will be zero at this
7984 point, and the specified segment prefix will always be used. */
7986 && i
.seg
[0] != default_seg
7987 && i386_seg_prefixes
[i
.seg
[0]->reg_num
] != i
.prefix
[SEG_PREFIX
])
7989 if (!add_prefix (i386_seg_prefixes
[i
.seg
[0]->reg_num
]))
7995 static INLINE
void set_rex_vrex (const reg_entry
*r
, unsigned int rex_bit
,
7998 if (r
->reg_flags
& RegRex
)
8000 if (i
.rex
& rex_bit
)
8001 as_bad (_("same type of prefix used twice"));
8004 else if (do_sse2avx
&& (i
.rex
& rex_bit
) && i
.vex
.register_specifier
)
8006 gas_assert (i
.vex
.register_specifier
== r
);
8007 i
.vex
.register_specifier
+= 8;
8010 if (r
->reg_flags
& RegVRex
)
8014 static const reg_entry
*
8015 build_modrm_byte (void)
8017 const reg_entry
*default_seg
= NULL
;
8018 unsigned int source
, dest
;
8021 vex_3_sources
= i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
;
8024 unsigned int nds
, reg_slot
;
8027 dest
= i
.operands
- 1;
8030 /* There are 2 kinds of instructions:
8031 1. 5 operands: 4 register operands or 3 register operands
8032 plus 1 memory operand plus one Imm4 operand, VexXDS, and
8033 VexW0 or VexW1. The destination must be either XMM, YMM or
8035 2. 4 operands: 4 register operands or 3 register operands
8036 plus 1 memory operand, with VexXDS. */
8037 gas_assert ((i
.reg_operands
== 4
8038 || (i
.reg_operands
== 3 && i
.mem_operands
== 1))
8039 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
8040 && i
.tm
.opcode_modifier
.vexw
8041 && i
.tm
.operand_types
[dest
].bitfield
.class == RegSIMD
);
8043 /* If VexW1 is set, the first non-immediate operand is the source and
8044 the second non-immediate one is encoded in the immediate operand. */
8045 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
8047 source
= i
.imm_operands
;
8048 reg_slot
= i
.imm_operands
+ 1;
8052 source
= i
.imm_operands
+ 1;
8053 reg_slot
= i
.imm_operands
;
8056 if (i
.imm_operands
== 0)
8058 /* When there is no immediate operand, generate an 8bit
8059 immediate operand to encode the first operand. */
8060 exp
= &im_expressions
[i
.imm_operands
++];
8061 i
.op
[i
.operands
].imms
= exp
;
8062 i
.types
[i
.operands
] = imm8
;
8065 gas_assert (i
.tm
.operand_types
[reg_slot
].bitfield
.class == RegSIMD
);
8066 exp
->X_op
= O_constant
;
8067 exp
->X_add_number
= register_number (i
.op
[reg_slot
].regs
) << 4;
8068 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
8072 gas_assert (i
.imm_operands
== 1);
8073 gas_assert (fits_in_imm4 (i
.op
[0].imms
->X_add_number
));
8074 gas_assert (!i
.tm
.opcode_modifier
.immext
);
8076 /* Turn on Imm8 again so that output_imm will generate it. */
8077 i
.types
[0].bitfield
.imm8
= 1;
8079 gas_assert (i
.tm
.operand_types
[reg_slot
].bitfield
.class == RegSIMD
);
8080 i
.op
[0].imms
->X_add_number
8081 |= register_number (i
.op
[reg_slot
].regs
) << 4;
8082 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
8085 gas_assert (i
.tm
.operand_types
[nds
].bitfield
.class == RegSIMD
);
8086 i
.vex
.register_specifier
= i
.op
[nds
].regs
;
8091 /* i.reg_operands MUST be the number of real register operands;
8092 implicit registers do not count. If there are 3 register
8093 operands, it must be a instruction with VexNDS. For a
8094 instruction with VexNDD, the destination register is encoded
8095 in VEX prefix. If there are 4 register operands, it must be
8096 a instruction with VEX prefix and 3 sources. */
8097 if (i
.mem_operands
== 0
8098 && ((i
.reg_operands
== 2
8099 && i
.tm
.opcode_modifier
.vexvvvv
<= VEXXDS
)
8100 || (i
.reg_operands
== 3
8101 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
8102 || (i
.reg_operands
== 4 && vex_3_sources
)))
8110 /* When there are 3 operands, one of them may be immediate,
8111 which may be the first or the last operand. Otherwise,
8112 the first operand must be shift count register (cl) or it
8113 is an instruction with VexNDS. */
8114 gas_assert (i
.imm_operands
== 1
8115 || (i
.imm_operands
== 0
8116 && (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
8117 || (i
.types
[0].bitfield
.instance
== RegC
8118 && i
.types
[0].bitfield
.byte
))));
8119 if (operand_type_check (i
.types
[0], imm
)
8120 || (i
.types
[0].bitfield
.instance
== RegC
8121 && i
.types
[0].bitfield
.byte
))
8127 /* When there are 4 operands, the first two must be 8bit
8128 immediate operands. The source operand will be the 3rd
8131 For instructions with VexNDS, if the first operand
8132 an imm8, the source operand is the 2nd one. If the last
8133 operand is imm8, the source operand is the first one. */
8134 gas_assert ((i
.imm_operands
== 2
8135 && i
.types
[0].bitfield
.imm8
8136 && i
.types
[1].bitfield
.imm8
)
8137 || (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
8138 && i
.imm_operands
== 1
8139 && (i
.types
[0].bitfield
.imm8
8140 || i
.types
[i
.operands
- 1].bitfield
.imm8
8141 || i
.rounding
.type
!= rc_none
)));
8142 if (i
.imm_operands
== 2)
8146 if (i
.types
[0].bitfield
.imm8
)
8153 if (is_evex_encoding (&i
.tm
))
8155 /* For EVEX instructions, when there are 5 operands, the
8156 first one must be immediate operand. If the second one
8157 is immediate operand, the source operand is the 3th
8158 one. If the last one is immediate operand, the source
8159 operand is the 2nd one. */
8160 gas_assert (i
.imm_operands
== 2
8161 && i
.tm
.opcode_modifier
.sae
8162 && operand_type_check (i
.types
[0], imm
));
8163 if (operand_type_check (i
.types
[1], imm
))
8165 else if (operand_type_check (i
.types
[4], imm
))
8179 /* RC/SAE operand could be between DEST and SRC. That happens
8180 when one operand is GPR and the other one is XMM/YMM/ZMM
8182 if (i
.rounding
.type
!= rc_none
&& i
.rounding
.operand
== dest
)
8185 if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
8187 /* For instructions with VexNDS, the register-only source
8188 operand must be a 32/64bit integer, XMM, YMM, ZMM, or mask
8189 register. It is encoded in VEX prefix. */
8191 i386_operand_type op
;
8194 /* Swap two source operands if needed. */
8195 if (i
.tm
.opcode_modifier
.swapsources
)
8203 op
= i
.tm
.operand_types
[vvvv
];
8204 if ((dest
+ 1) >= i
.operands
8205 || ((op
.bitfield
.class != Reg
8206 || (!op
.bitfield
.dword
&& !op
.bitfield
.qword
))
8207 && op
.bitfield
.class != RegSIMD
8208 && !operand_type_equal (&op
, ®mask
)))
8210 i
.vex
.register_specifier
= i
.op
[vvvv
].regs
;
8216 /* One of the register operands will be encoded in the i.rm.reg
8217 field, the other in the combined i.rm.mode and i.rm.regmem
8218 fields. If no form of this instruction supports a memory
8219 destination operand, then we assume the source operand may
8220 sometimes be a memory operand and so we need to store the
8221 destination in the i.rm.reg field. */
8222 if (!i
.tm
.opcode_modifier
.regmem
8223 && operand_type_check (i
.tm
.operand_types
[dest
], anymem
) == 0)
8225 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
8226 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
8227 set_rex_vrex (i
.op
[dest
].regs
, REX_R
, i
.tm
.opcode_modifier
.sse2avx
);
8228 set_rex_vrex (i
.op
[source
].regs
, REX_B
, false);
8232 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
8233 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
8234 set_rex_vrex (i
.op
[dest
].regs
, REX_B
, i
.tm
.opcode_modifier
.sse2avx
);
8235 set_rex_vrex (i
.op
[source
].regs
, REX_R
, false);
8237 if (flag_code
!= CODE_64BIT
&& (i
.rex
& REX_R
))
8239 if (i
.types
[!i
.tm
.opcode_modifier
.regmem
].bitfield
.class != RegCR
)
8242 add_prefix (LOCK_PREFIX_OPCODE
);
8246 { /* If it's not 2 reg operands... */
8251 unsigned int fake_zero_displacement
= 0;
8254 for (op
= 0; op
< i
.operands
; op
++)
8255 if (i
.flags
[op
] & Operand_Mem
)
8257 gas_assert (op
< i
.operands
);
8259 if (i
.tm
.opcode_modifier
.sib
)
8261 /* The index register of VSIB shouldn't be RegIZ. */
8262 if (i
.tm
.opcode_modifier
.sib
!= SIBMEM
8263 && i
.index_reg
->reg_num
== RegIZ
)
8266 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
8269 i
.sib
.base
= NO_BASE_REGISTER
;
8270 i
.sib
.scale
= i
.log2_scale_factor
;
8271 i
.types
[op
].bitfield
.disp8
= 0;
8272 i
.types
[op
].bitfield
.disp16
= 0;
8273 i
.types
[op
].bitfield
.disp64
= 0;
8274 if (want_disp32 (&i
.tm
))
8276 /* Must be 32 bit */
8277 i
.types
[op
].bitfield
.disp32
= 1;
8278 i
.types
[op
].bitfield
.disp32s
= 0;
8282 i
.types
[op
].bitfield
.disp32
= 0;
8283 i
.types
[op
].bitfield
.disp32s
= 1;
8287 /* Since the mandatory SIB always has index register, so
8288 the code logic remains unchanged. The non-mandatory SIB
8289 without index register is allowed and will be handled
8293 if (i
.index_reg
->reg_num
== RegIZ
)
8294 i
.sib
.index
= NO_INDEX_REGISTER
;
8296 i
.sib
.index
= i
.index_reg
->reg_num
;
8297 set_rex_vrex (i
.index_reg
, REX_X
, false);
8301 default_seg
= reg_ds
;
8303 if (i
.base_reg
== 0)
8306 if (!i
.disp_operands
)
8307 fake_zero_displacement
= 1;
8308 if (i
.index_reg
== 0)
8310 i386_operand_type newdisp
;
8312 /* Both check for VSIB and mandatory non-vector SIB. */
8313 gas_assert (!i
.tm
.opcode_modifier
.sib
8314 || i
.tm
.opcode_modifier
.sib
== SIBMEM
);
8315 /* Operand is just <disp> */
8316 if (flag_code
== CODE_64BIT
)
8318 /* 64bit mode overwrites the 32bit absolute
8319 addressing by RIP relative addressing and
8320 absolute addressing is encoded by one of the
8321 redundant SIB forms. */
8322 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
8323 i
.sib
.base
= NO_BASE_REGISTER
;
8324 i
.sib
.index
= NO_INDEX_REGISTER
;
8325 newdisp
= (want_disp32(&i
.tm
) ? disp32
: disp32s
);
8327 else if ((flag_code
== CODE_16BIT
)
8328 ^ (i
.prefix
[ADDR_PREFIX
] != 0))
8330 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
8335 i
.rm
.regmem
= NO_BASE_REGISTER
;
8338 i
.types
[op
] = operand_type_and_not (i
.types
[op
], anydisp
);
8339 i
.types
[op
] = operand_type_or (i
.types
[op
], newdisp
);
8341 else if (!i
.tm
.opcode_modifier
.sib
)
8343 /* !i.base_reg && i.index_reg */
8344 if (i
.index_reg
->reg_num
== RegIZ
)
8345 i
.sib
.index
= NO_INDEX_REGISTER
;
8347 i
.sib
.index
= i
.index_reg
->reg_num
;
8348 i
.sib
.base
= NO_BASE_REGISTER
;
8349 i
.sib
.scale
= i
.log2_scale_factor
;
8350 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
8351 i
.types
[op
].bitfield
.disp8
= 0;
8352 i
.types
[op
].bitfield
.disp16
= 0;
8353 i
.types
[op
].bitfield
.disp64
= 0;
8354 if (want_disp32 (&i
.tm
))
8356 /* Must be 32 bit */
8357 i
.types
[op
].bitfield
.disp32
= 1;
8358 i
.types
[op
].bitfield
.disp32s
= 0;
8362 i
.types
[op
].bitfield
.disp32
= 0;
8363 i
.types
[op
].bitfield
.disp32s
= 1;
8365 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
8369 /* RIP addressing for 64bit mode. */
8370 else if (i
.base_reg
->reg_num
== RegIP
)
8372 gas_assert (!i
.tm
.opcode_modifier
.sib
);
8373 i
.rm
.regmem
= NO_BASE_REGISTER
;
8374 i
.types
[op
].bitfield
.disp8
= 0;
8375 i
.types
[op
].bitfield
.disp16
= 0;
8376 i
.types
[op
].bitfield
.disp32
= 0;
8377 i
.types
[op
].bitfield
.disp32s
= 1;
8378 i
.types
[op
].bitfield
.disp64
= 0;
8379 i
.flags
[op
] |= Operand_PCrel
;
8380 if (! i
.disp_operands
)
8381 fake_zero_displacement
= 1;
8383 else if (i
.base_reg
->reg_type
.bitfield
.word
)
8385 gas_assert (!i
.tm
.opcode_modifier
.sib
);
8386 switch (i
.base_reg
->reg_num
)
8389 if (i
.index_reg
== 0)
8391 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
8392 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
8395 default_seg
= reg_ss
;
8396 if (i
.index_reg
== 0)
8399 if (operand_type_check (i
.types
[op
], disp
) == 0)
8401 /* fake (%bp) into 0(%bp) */
8402 if (i
.disp_encoding
== disp_encoding_16bit
)
8403 i
.types
[op
].bitfield
.disp16
= 1;
8405 i
.types
[op
].bitfield
.disp8
= 1;
8406 fake_zero_displacement
= 1;
8409 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
8410 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
8412 default: /* (%si) -> 4 or (%di) -> 5 */
8413 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
8415 if (!fake_zero_displacement
8419 fake_zero_displacement
= 1;
8420 if (i
.disp_encoding
== disp_encoding_8bit
)
8421 i
.types
[op
].bitfield
.disp8
= 1;
8423 i
.types
[op
].bitfield
.disp16
= 1;
8425 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
8427 else /* i.base_reg and 32/64 bit mode */
8429 if (operand_type_check (i
.types
[op
], disp
))
8431 i
.types
[op
].bitfield
.disp16
= 0;
8432 i
.types
[op
].bitfield
.disp64
= 0;
8433 if (!want_disp32 (&i
.tm
))
8435 i
.types
[op
].bitfield
.disp32
= 0;
8436 i
.types
[op
].bitfield
.disp32s
= 1;
8440 i
.types
[op
].bitfield
.disp32
= 1;
8441 i
.types
[op
].bitfield
.disp32s
= 0;
8445 if (!i
.tm
.opcode_modifier
.sib
)
8446 i
.rm
.regmem
= i
.base_reg
->reg_num
;
8447 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
8449 i
.sib
.base
= i
.base_reg
->reg_num
;
8450 /* x86-64 ignores REX prefix bit here to avoid decoder
8452 if (!(i
.base_reg
->reg_flags
& RegRex
)
8453 && (i
.base_reg
->reg_num
== EBP_REG_NUM
8454 || i
.base_reg
->reg_num
== ESP_REG_NUM
))
8455 default_seg
= reg_ss
;
8456 if (i
.base_reg
->reg_num
== 5 && i
.disp_operands
== 0)
8458 fake_zero_displacement
= 1;
8459 if (i
.disp_encoding
== disp_encoding_32bit
)
8460 i
.types
[op
].bitfield
.disp32
= 1;
8462 i
.types
[op
].bitfield
.disp8
= 1;
8464 i
.sib
.scale
= i
.log2_scale_factor
;
8465 if (i
.index_reg
== 0)
8467 /* Only check for VSIB. */
8468 gas_assert (i
.tm
.opcode_modifier
.sib
!= VECSIB128
8469 && i
.tm
.opcode_modifier
.sib
!= VECSIB256
8470 && i
.tm
.opcode_modifier
.sib
!= VECSIB512
);
8472 /* <disp>(%esp) becomes two byte modrm with no index
8473 register. We've already stored the code for esp
8474 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
8475 Any base register besides %esp will not use the
8476 extra modrm byte. */
8477 i
.sib
.index
= NO_INDEX_REGISTER
;
8479 else if (!i
.tm
.opcode_modifier
.sib
)
8481 if (i
.index_reg
->reg_num
== RegIZ
)
8482 i
.sib
.index
= NO_INDEX_REGISTER
;
8484 i
.sib
.index
= i
.index_reg
->reg_num
;
8485 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
8486 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
8491 && (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
8492 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
))
8496 if (!fake_zero_displacement
8500 fake_zero_displacement
= 1;
8501 if (i
.disp_encoding
== disp_encoding_8bit
)
8502 i
.types
[op
].bitfield
.disp8
= 1;
8504 i
.types
[op
].bitfield
.disp32
= 1;
8506 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
8510 if (fake_zero_displacement
)
8512 /* Fakes a zero displacement assuming that i.types[op]
8513 holds the correct displacement size. */
8516 gas_assert (i
.op
[op
].disps
== 0);
8517 exp
= &disp_expressions
[i
.disp_operands
++];
8518 i
.op
[op
].disps
= exp
;
8519 exp
->X_op
= O_constant
;
8520 exp
->X_add_number
= 0;
8521 exp
->X_add_symbol
= (symbolS
*) 0;
8522 exp
->X_op_symbol
= (symbolS
*) 0;
8530 if (i
.tm
.opcode_modifier
.vexsources
== XOP2SOURCES
)
8532 if (operand_type_check (i
.types
[0], imm
))
8533 i
.vex
.register_specifier
= NULL
;
8536 /* VEX.vvvv encodes one of the sources when the first
8537 operand is not an immediate. */
8538 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
8539 i
.vex
.register_specifier
= i
.op
[0].regs
;
8541 i
.vex
.register_specifier
= i
.op
[1].regs
;
8544 /* Destination is a XMM register encoded in the ModRM.reg
8546 i
.rm
.reg
= i
.op
[2].regs
->reg_num
;
8547 if ((i
.op
[2].regs
->reg_flags
& RegRex
) != 0)
8550 /* ModRM.rm and VEX.B encodes the other source. */
8551 if (!i
.mem_operands
)
8555 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
8556 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
8558 i
.rm
.regmem
= i
.op
[0].regs
->reg_num
;
8560 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
8564 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXLWP
)
8566 i
.vex
.register_specifier
= i
.op
[2].regs
;
8567 if (!i
.mem_operands
)
8570 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
8571 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
8575 /* Fill in i.rm.reg or i.rm.regmem field with register operand
8576 (if any) based on i.tm.extension_opcode. Again, we must be
8577 careful to make sure that segment/control/debug/test/MMX
8578 registers are coded into the i.rm.reg field. */
8579 else if (i
.reg_operands
)
8582 unsigned int vex_reg
= ~0;
8584 for (op
= 0; op
< i
.operands
; op
++)
8585 if (i
.types
[op
].bitfield
.class == Reg
8586 || i
.types
[op
].bitfield
.class == RegBND
8587 || i
.types
[op
].bitfield
.class == RegMask
8588 || i
.types
[op
].bitfield
.class == SReg
8589 || i
.types
[op
].bitfield
.class == RegCR
8590 || i
.types
[op
].bitfield
.class == RegDR
8591 || i
.types
[op
].bitfield
.class == RegTR
8592 || i
.types
[op
].bitfield
.class == RegSIMD
8593 || i
.types
[op
].bitfield
.class == RegMMX
)
8598 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
8600 /* For instructions with VexNDS, the register-only
8601 source operand is encoded in VEX prefix. */
8602 gas_assert (mem
!= (unsigned int) ~0);
8607 gas_assert (op
< i
.operands
);
8611 /* Check register-only source operand when two source
8612 operands are swapped. */
8613 if (!i
.tm
.operand_types
[op
].bitfield
.baseindex
8614 && i
.tm
.operand_types
[op
+ 1].bitfield
.baseindex
)
8618 gas_assert (mem
== (vex_reg
+ 1)
8619 && op
< i
.operands
);
8624 gas_assert (vex_reg
< i
.operands
);
8628 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXNDD
)
8630 /* For instructions with VexNDD, the register destination
8631 is encoded in VEX prefix. */
8632 if (i
.mem_operands
== 0)
8634 /* There is no memory operand. */
8635 gas_assert ((op
+ 2) == i
.operands
);
8640 /* There are only 2 non-immediate operands. */
8641 gas_assert (op
< i
.imm_operands
+ 2
8642 && i
.operands
== i
.imm_operands
+ 2);
8643 vex_reg
= i
.imm_operands
+ 1;
8647 gas_assert (op
< i
.operands
);
8649 if (vex_reg
!= (unsigned int) ~0)
8651 i386_operand_type
*type
= &i
.tm
.operand_types
[vex_reg
];
8653 if ((type
->bitfield
.class != Reg
8654 || (!type
->bitfield
.dword
&& !type
->bitfield
.qword
))
8655 && type
->bitfield
.class != RegSIMD
8656 && !operand_type_equal (type
, ®mask
))
8659 i
.vex
.register_specifier
= i
.op
[vex_reg
].regs
;
8662 /* Don't set OP operand twice. */
8665 /* If there is an extension opcode to put here, the
8666 register number must be put into the regmem field. */
8667 if (i
.tm
.extension_opcode
!= None
)
8669 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
8670 set_rex_vrex (i
.op
[op
].regs
, REX_B
,
8671 i
.tm
.opcode_modifier
.sse2avx
);
8675 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
8676 set_rex_vrex (i
.op
[op
].regs
, REX_R
,
8677 i
.tm
.opcode_modifier
.sse2avx
);
8681 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
8682 must set it to 3 to indicate this is a register operand
8683 in the regmem field. */
8684 if (!i
.mem_operands
)
8688 /* Fill in i.rm.reg field with extension opcode (if any). */
8689 if (i
.tm
.extension_opcode
!= None
)
8690 i
.rm
.reg
= i
.tm
.extension_opcode
;
8696 frag_opcode_byte (unsigned char byte
)
8698 if (now_seg
!= absolute_section
)
8699 FRAG_APPEND_1_CHAR (byte
);
8701 ++abs_section_offset
;
8705 flip_code16 (unsigned int code16
)
8707 gas_assert (i
.tm
.operands
== 1);
8709 return !(i
.prefix
[REX_PREFIX
] & REX_W
)
8710 && (code16
? i
.tm
.operand_types
[0].bitfield
.disp32
8711 || i
.tm
.operand_types
[0].bitfield
.disp32s
8712 : i
.tm
.operand_types
[0].bitfield
.disp16
)
8717 output_branch (void)
8723 relax_substateT subtype
;
8727 if (now_seg
== absolute_section
)
8729 as_bad (_("relaxable branches not supported in absolute section"));
8733 code16
= flag_code
== CODE_16BIT
? CODE16
: 0;
8734 size
= i
.disp_encoding
== disp_encoding_32bit
? BIG
: SMALL
;
8737 if (i
.prefix
[DATA_PREFIX
] != 0)
8741 code16
^= flip_code16(code16
);
8743 /* Pentium4 branch hints. */
8744 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
8745 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
8750 if (i
.prefix
[REX_PREFIX
] != 0)
8756 /* BND prefixed jump. */
8757 if (i
.prefix
[BND_PREFIX
] != 0)
8763 if (i
.prefixes
!= 0)
8764 as_warn (_("skipping prefixes on `%s'"), i
.tm
.name
);
8766 /* It's always a symbol; End frag & setup for relax.
8767 Make sure there is enough room in this frag for the largest
8768 instruction we may generate in md_convert_frag. This is 2
8769 bytes for the opcode and room for the prefix and largest
8771 frag_grow (prefix
+ 2 + 4);
8772 /* Prefix and 1 opcode byte go in fr_fix. */
8773 p
= frag_more (prefix
+ 1);
8774 if (i
.prefix
[DATA_PREFIX
] != 0)
8775 *p
++ = DATA_PREFIX_OPCODE
;
8776 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
8777 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
8778 *p
++ = i
.prefix
[SEG_PREFIX
];
8779 if (i
.prefix
[BND_PREFIX
] != 0)
8780 *p
++ = BND_PREFIX_OPCODE
;
8781 if (i
.prefix
[REX_PREFIX
] != 0)
8782 *p
++ = i
.prefix
[REX_PREFIX
];
8783 *p
= i
.tm
.base_opcode
;
8785 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
8786 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, size
);
8787 else if (cpu_arch_flags
.bitfield
.cpui386
)
8788 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, size
);
8790 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, size
);
8793 sym
= i
.op
[0].disps
->X_add_symbol
;
8794 off
= i
.op
[0].disps
->X_add_number
;
8796 if (i
.op
[0].disps
->X_op
!= O_constant
8797 && i
.op
[0].disps
->X_op
!= O_symbol
)
8799 /* Handle complex expressions. */
8800 sym
= make_expr_symbol (i
.op
[0].disps
);
8804 /* 1 possible extra opcode + 4 byte displacement go in var part.
8805 Pass reloc in fr_var. */
8806 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
8809 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8810 /* Return TRUE iff PLT32 relocation should be used for branching to
8814 need_plt32_p (symbolS
*s
)
8816 /* PLT32 relocation is ELF only. */
8821 /* Don't emit PLT32 relocation on Solaris: neither native linker nor
8822 krtld support it. */
8826 /* Since there is no need to prepare for PLT branch on x86-64, we
8827 can generate R_X86_64_PLT32, instead of R_X86_64_PC32, which can
8828 be used as a marker for 32-bit PC-relative branches. */
8835 /* Weak or undefined symbol need PLT32 relocation. */
8836 if (S_IS_WEAK (s
) || !S_IS_DEFINED (s
))
8839 /* Non-global symbol doesn't need PLT32 relocation. */
8840 if (! S_IS_EXTERNAL (s
))
8843 /* Other global symbols need PLT32 relocation. NB: Symbol with
8844 non-default visibilities are treated as normal global symbol
8845 so that PLT32 relocation can be used as a marker for 32-bit
8846 PC-relative branches. It is useful for linker relaxation. */
8857 bfd_reloc_code_real_type jump_reloc
= i
.reloc
[0];
8859 if (i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
)
8861 /* This is a loop or jecxz type instruction. */
8863 if (i
.prefix
[ADDR_PREFIX
] != 0)
8865 frag_opcode_byte (ADDR_PREFIX_OPCODE
);
8868 /* Pentium4 branch hints. */
8869 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
8870 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
8872 frag_opcode_byte (i
.prefix
[SEG_PREFIX
]);
8881 if (flag_code
== CODE_16BIT
)
8884 if (i
.prefix
[DATA_PREFIX
] != 0)
8886 frag_opcode_byte (DATA_PREFIX_OPCODE
);
8888 code16
^= flip_code16(code16
);
8896 /* BND prefixed jump. */
8897 if (i
.prefix
[BND_PREFIX
] != 0)
8899 frag_opcode_byte (i
.prefix
[BND_PREFIX
]);
8903 if (i
.prefix
[REX_PREFIX
] != 0)
8905 frag_opcode_byte (i
.prefix
[REX_PREFIX
]);
8909 if (i
.prefixes
!= 0)
8910 as_warn (_("skipping prefixes on `%s'"), i
.tm
.name
);
8912 if (now_seg
== absolute_section
)
8914 abs_section_offset
+= i
.opcode_length
+ size
;
8918 p
= frag_more (i
.opcode_length
+ size
);
8919 switch (i
.opcode_length
)
8922 *p
++ = i
.tm
.base_opcode
>> 8;
8925 *p
++ = i
.tm
.base_opcode
;
8931 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8933 && jump_reloc
== NO_RELOC
8934 && need_plt32_p (i
.op
[0].disps
->X_add_symbol
))
8935 jump_reloc
= BFD_RELOC_X86_64_PLT32
;
8938 jump_reloc
= reloc (size
, 1, 1, jump_reloc
);
8940 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
8941 i
.op
[0].disps
, 1, jump_reloc
);
8943 /* All jumps handled here are signed, but don't unconditionally use a
8944 signed limit check for 32 and 16 bit jumps as we want to allow wrap
8945 around at 4G (outside of 64-bit mode) and 64k (except for XBEGIN)
8950 fixP
->fx_signed
= 1;
8954 if (i
.tm
.base_opcode
== 0xc7f8)
8955 fixP
->fx_signed
= 1;
8959 if (flag_code
== CODE_64BIT
)
8960 fixP
->fx_signed
= 1;
8966 output_interseg_jump (void)
8974 if (flag_code
== CODE_16BIT
)
8978 if (i
.prefix
[DATA_PREFIX
] != 0)
8985 gas_assert (!i
.prefix
[REX_PREFIX
]);
8991 if (i
.prefixes
!= 0)
8992 as_warn (_("skipping prefixes on `%s'"), i
.tm
.name
);
8994 if (now_seg
== absolute_section
)
8996 abs_section_offset
+= prefix
+ 1 + 2 + size
;
9000 /* 1 opcode; 2 segment; offset */
9001 p
= frag_more (prefix
+ 1 + 2 + size
);
9003 if (i
.prefix
[DATA_PREFIX
] != 0)
9004 *p
++ = DATA_PREFIX_OPCODE
;
9006 if (i
.prefix
[REX_PREFIX
] != 0)
9007 *p
++ = i
.prefix
[REX_PREFIX
];
9009 *p
++ = i
.tm
.base_opcode
;
9010 if (i
.op
[1].imms
->X_op
== O_constant
)
9012 offsetT n
= i
.op
[1].imms
->X_add_number
;
9015 && !fits_in_unsigned_word (n
)
9016 && !fits_in_signed_word (n
))
9018 as_bad (_("16-bit jump out of range"));
9021 md_number_to_chars (p
, n
, size
);
9024 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
9025 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
9028 if (i
.op
[0].imms
->X_op
== O_constant
)
9029 md_number_to_chars (p
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
9031 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 2,
9032 i
.op
[0].imms
, 0, reloc (2, 0, 0, i
.reloc
[0]));
9035 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9040 asection
*seg
= now_seg
;
9041 subsegT subseg
= now_subseg
;
9043 unsigned int alignment
, align_size_1
;
9044 unsigned int isa_1_descsz
, feature_2_descsz
, descsz
;
9045 unsigned int isa_1_descsz_raw
, feature_2_descsz_raw
;
9046 unsigned int padding
;
9048 if (!IS_ELF
|| !x86_used_note
)
9051 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_X86
;
9053 /* The .note.gnu.property section layout:
9055 Field Length Contents
9058 n_descsz 4 The note descriptor size
9059 n_type 4 NT_GNU_PROPERTY_TYPE_0
9061 n_desc n_descsz The program property array
9065 /* Create the .note.gnu.property section. */
9066 sec
= subseg_new (NOTE_GNU_PROPERTY_SECTION_NAME
, 0);
9067 bfd_set_section_flags (sec
,
9074 if (get_elf_backend_data (stdoutput
)->s
->elfclass
== ELFCLASS64
)
9085 bfd_set_section_alignment (sec
, alignment
);
9086 elf_section_type (sec
) = SHT_NOTE
;
9088 /* GNU_PROPERTY_X86_ISA_1_USED: 4-byte type + 4-byte data size
9090 isa_1_descsz_raw
= 4 + 4 + 4;
9091 /* Align GNU_PROPERTY_X86_ISA_1_USED. */
9092 isa_1_descsz
= (isa_1_descsz_raw
+ align_size_1
) & ~align_size_1
;
9094 feature_2_descsz_raw
= isa_1_descsz
;
9095 /* GNU_PROPERTY_X86_FEATURE_2_USED: 4-byte type + 4-byte data size
9097 feature_2_descsz_raw
+= 4 + 4 + 4;
9098 /* Align GNU_PROPERTY_X86_FEATURE_2_USED. */
9099 feature_2_descsz
= ((feature_2_descsz_raw
+ align_size_1
)
9102 descsz
= feature_2_descsz
;
9103 /* Section size: n_namsz + n_descsz + n_type + n_name + n_descsz. */
9104 p
= frag_more (4 + 4 + 4 + 4 + descsz
);
9106 /* Write n_namsz. */
9107 md_number_to_chars (p
, (valueT
) 4, 4);
9109 /* Write n_descsz. */
9110 md_number_to_chars (p
+ 4, (valueT
) descsz
, 4);
9113 md_number_to_chars (p
+ 4 * 2, (valueT
) NT_GNU_PROPERTY_TYPE_0
, 4);
9116 memcpy (p
+ 4 * 3, "GNU", 4);
9118 /* Write 4-byte type. */
9119 md_number_to_chars (p
+ 4 * 4,
9120 (valueT
) GNU_PROPERTY_X86_ISA_1_USED
, 4);
9122 /* Write 4-byte data size. */
9123 md_number_to_chars (p
+ 4 * 5, (valueT
) 4, 4);
9125 /* Write 4-byte data. */
9126 md_number_to_chars (p
+ 4 * 6, (valueT
) x86_isa_1_used
, 4);
9128 /* Zero out paddings. */
9129 padding
= isa_1_descsz
- isa_1_descsz_raw
;
9131 memset (p
+ 4 * 7, 0, padding
);
9133 /* Write 4-byte type. */
9134 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 4,
9135 (valueT
) GNU_PROPERTY_X86_FEATURE_2_USED
, 4);
9137 /* Write 4-byte data size. */
9138 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 5, (valueT
) 4, 4);
9140 /* Write 4-byte data. */
9141 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 6,
9142 (valueT
) x86_feature_2_used
, 4);
9144 /* Zero out paddings. */
9145 padding
= feature_2_descsz
- feature_2_descsz_raw
;
9147 memset (p
+ isa_1_descsz
+ 4 * 7, 0, padding
);
9149 /* We probably can't restore the current segment, for there likely
9152 subseg_set (seg
, subseg
);
9157 encoding_length (const fragS
*start_frag
, offsetT start_off
,
9158 const char *frag_now_ptr
)
9160 unsigned int len
= 0;
9162 if (start_frag
!= frag_now
)
9164 const fragS
*fr
= start_frag
;
9169 } while (fr
&& fr
!= frag_now
);
9172 return len
- start_off
+ (frag_now_ptr
- frag_now
->fr_literal
);
9175 /* Return 1 for test, and, cmp, add, sub, inc and dec which may
9176 be macro-fused with conditional jumps.
9177 NB: If TEST/AND/CMP/ADD/SUB/INC/DEC is of RIP relative address,
9178 or is one of the following format:
9191 maybe_fused_with_jcc_p (enum mf_cmp_kind
* mf_cmp_p
)
9193 /* No RIP address. */
9194 if (i
.base_reg
&& i
.base_reg
->reg_num
== RegIP
)
9197 /* No opcodes outside of base encoding space. */
9198 if (i
.tm
.opcode_modifier
.opcodespace
!= SPACE_BASE
)
9201 /* add, sub without add/sub m, imm. */
9202 if (i
.tm
.base_opcode
<= 5
9203 || (i
.tm
.base_opcode
>= 0x28 && i
.tm
.base_opcode
<= 0x2d)
9204 || ((i
.tm
.base_opcode
| 3) == 0x83
9205 && (i
.tm
.extension_opcode
== 0x5
9206 || i
.tm
.extension_opcode
== 0x0)))
9208 *mf_cmp_p
= mf_cmp_alu_cmp
;
9209 return !(i
.mem_operands
&& i
.imm_operands
);
9212 /* and without and m, imm. */
9213 if ((i
.tm
.base_opcode
>= 0x20 && i
.tm
.base_opcode
<= 0x25)
9214 || ((i
.tm
.base_opcode
| 3) == 0x83
9215 && i
.tm
.extension_opcode
== 0x4))
9217 *mf_cmp_p
= mf_cmp_test_and
;
9218 return !(i
.mem_operands
&& i
.imm_operands
);
9221 /* test without test m imm. */
9222 if ((i
.tm
.base_opcode
| 1) == 0x85
9223 || (i
.tm
.base_opcode
| 1) == 0xa9
9224 || ((i
.tm
.base_opcode
| 1) == 0xf7
9225 && i
.tm
.extension_opcode
== 0))
9227 *mf_cmp_p
= mf_cmp_test_and
;
9228 return !(i
.mem_operands
&& i
.imm_operands
);
9231 /* cmp without cmp m, imm. */
9232 if ((i
.tm
.base_opcode
>= 0x38 && i
.tm
.base_opcode
<= 0x3d)
9233 || ((i
.tm
.base_opcode
| 3) == 0x83
9234 && (i
.tm
.extension_opcode
== 0x7)))
9236 *mf_cmp_p
= mf_cmp_alu_cmp
;
9237 return !(i
.mem_operands
&& i
.imm_operands
);
9240 /* inc, dec without inc/dec m. */
9241 if ((i
.tm
.cpu_flags
.bitfield
.cpuno64
9242 && (i
.tm
.base_opcode
| 0xf) == 0x4f)
9243 || ((i
.tm
.base_opcode
| 1) == 0xff
9244 && i
.tm
.extension_opcode
<= 0x1))
9246 *mf_cmp_p
= mf_cmp_incdec
;
9247 return !i
.mem_operands
;
9253 /* Return 1 if a FUSED_JCC_PADDING frag should be generated. */
9256 add_fused_jcc_padding_frag_p (enum mf_cmp_kind
* mf_cmp_p
)
9258 /* NB: Don't work with COND_JUMP86 without i386. */
9259 if (!align_branch_power
9260 || now_seg
== absolute_section
9261 || !cpu_arch_flags
.bitfield
.cpui386
9262 || !(align_branch
& align_branch_fused_bit
))
9265 if (maybe_fused_with_jcc_p (mf_cmp_p
))
9267 if (last_insn
.kind
== last_insn_other
9268 || last_insn
.seg
!= now_seg
)
9271 as_warn_where (last_insn
.file
, last_insn
.line
,
9272 _("`%s` skips -malign-branch-boundary on `%s`"),
9273 last_insn
.name
, i
.tm
.name
);
9279 /* Return 1 if a BRANCH_PREFIX frag should be generated. */
9282 add_branch_prefix_frag_p (void)
9284 /* NB: Don't work with COND_JUMP86 without i386. Don't add prefix
9285 to PadLock instructions since they include prefixes in opcode. */
9286 if (!align_branch_power
9287 || !align_branch_prefix_size
9288 || now_seg
== absolute_section
9289 || i
.tm
.cpu_flags
.bitfield
.cpupadlock
9290 || !cpu_arch_flags
.bitfield
.cpui386
)
9293 /* Don't add prefix if it is a prefix or there is no operand in case
9294 that segment prefix is special. */
9295 if (!i
.operands
|| i
.tm
.opcode_modifier
.isprefix
)
9298 if (last_insn
.kind
== last_insn_other
9299 || last_insn
.seg
!= now_seg
)
9303 as_warn_where (last_insn
.file
, last_insn
.line
,
9304 _("`%s` skips -malign-branch-boundary on `%s`"),
9305 last_insn
.name
, i
.tm
.name
);
9310 /* Return 1 if a BRANCH_PADDING frag should be generated. */
9313 add_branch_padding_frag_p (enum align_branch_kind
*branch_p
,
9314 enum mf_jcc_kind
*mf_jcc_p
)
9318 /* NB: Don't work with COND_JUMP86 without i386. */
9319 if (!align_branch_power
9320 || now_seg
== absolute_section
9321 || !cpu_arch_flags
.bitfield
.cpui386
9322 || i
.tm
.opcode_modifier
.opcodespace
!= SPACE_BASE
)
9327 /* Check for jcc and direct jmp. */
9328 if (i
.tm
.opcode_modifier
.jump
== JUMP
)
9330 if (i
.tm
.base_opcode
== JUMP_PC_RELATIVE
)
9332 *branch_p
= align_branch_jmp
;
9333 add_padding
= align_branch
& align_branch_jmp_bit
;
9337 /* Because J<cc> and JN<cc> share same group in macro-fusible table,
9338 igore the lowest bit. */
9339 *mf_jcc_p
= (i
.tm
.base_opcode
& 0x0e) >> 1;
9340 *branch_p
= align_branch_jcc
;
9341 if ((align_branch
& align_branch_jcc_bit
))
9345 else if ((i
.tm
.base_opcode
| 1) == 0xc3)
9348 *branch_p
= align_branch_ret
;
9349 if ((align_branch
& align_branch_ret_bit
))
9354 /* Check for indirect jmp, direct and indirect calls. */
9355 if (i
.tm
.base_opcode
== 0xe8)
9358 *branch_p
= align_branch_call
;
9359 if ((align_branch
& align_branch_call_bit
))
9362 else if (i
.tm
.base_opcode
== 0xff
9363 && (i
.tm
.extension_opcode
== 2
9364 || i
.tm
.extension_opcode
== 4))
9366 /* Indirect call and jmp. */
9367 *branch_p
= align_branch_indirect
;
9368 if ((align_branch
& align_branch_indirect_bit
))
9375 && (i
.op
[0].disps
->X_op
== O_symbol
9376 || (i
.op
[0].disps
->X_op
== O_subtract
9377 && i
.op
[0].disps
->X_op_symbol
== GOT_symbol
)))
9379 symbolS
*s
= i
.op
[0].disps
->X_add_symbol
;
9380 /* No padding to call to global or undefined tls_get_addr. */
9381 if ((S_IS_EXTERNAL (s
) || !S_IS_DEFINED (s
))
9382 && strcmp (S_GET_NAME (s
), tls_get_addr
) == 0)
9388 && last_insn
.kind
!= last_insn_other
9389 && last_insn
.seg
== now_seg
)
9392 as_warn_where (last_insn
.file
, last_insn
.line
,
9393 _("`%s` skips -malign-branch-boundary on `%s`"),
9394 last_insn
.name
, i
.tm
.name
);
9404 fragS
*insn_start_frag
;
9405 offsetT insn_start_off
;
9406 fragS
*fragP
= NULL
;
9407 enum align_branch_kind branch
= align_branch_none
;
9408 /* The initializer is arbitrary just to avoid uninitialized error.
9409 it's actually either assigned in add_branch_padding_frag_p
9410 or never be used. */
9411 enum mf_jcc_kind mf_jcc
= mf_jcc_jo
;
9413 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9414 if (IS_ELF
&& x86_used_note
&& now_seg
!= absolute_section
)
9416 if ((i
.xstate
& xstate_tmm
) == xstate_tmm
9417 || i
.tm
.cpu_flags
.bitfield
.cpuamx_tile
)
9418 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_TMM
;
9420 if (i
.tm
.cpu_flags
.bitfield
.cpu8087
9421 || i
.tm
.cpu_flags
.bitfield
.cpu287
9422 || i
.tm
.cpu_flags
.bitfield
.cpu387
9423 || i
.tm
.cpu_flags
.bitfield
.cpu687
9424 || i
.tm
.cpu_flags
.bitfield
.cpufisttp
)
9425 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_X87
;
9427 if ((i
.xstate
& xstate_mmx
)
9428 || (i
.tm
.opcode_modifier
.opcodespace
== SPACE_0F
9429 && !is_any_vex_encoding (&i
.tm
)
9430 && (i
.tm
.base_opcode
== 0x77 /* emms */
9431 || i
.tm
.base_opcode
== 0x0e /* femms */)))
9432 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_MMX
;
9436 if (i
.index_reg
->reg_type
.bitfield
.zmmword
)
9437 i
.xstate
|= xstate_zmm
;
9438 else if (i
.index_reg
->reg_type
.bitfield
.ymmword
)
9439 i
.xstate
|= xstate_ymm
;
9440 else if (i
.index_reg
->reg_type
.bitfield
.xmmword
)
9441 i
.xstate
|= xstate_xmm
;
9444 /* vzeroall / vzeroupper */
9445 if (i
.tm
.base_opcode
== 0x77 && i
.tm
.cpu_flags
.bitfield
.cpuavx
)
9446 i
.xstate
|= xstate_ymm
;
9448 if ((i
.xstate
& xstate_xmm
)
9449 /* ldmxcsr / stmxcsr / vldmxcsr / vstmxcsr */
9450 || (i
.tm
.base_opcode
== 0xae
9451 && (i
.tm
.cpu_flags
.bitfield
.cpusse
9452 || i
.tm
.cpu_flags
.bitfield
.cpuavx
))
9453 || i
.tm
.cpu_flags
.bitfield
.cpuwidekl
9454 || i
.tm
.cpu_flags
.bitfield
.cpukl
)
9455 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XMM
;
9457 if ((i
.xstate
& xstate_ymm
) == xstate_ymm
)
9458 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_YMM
;
9459 if ((i
.xstate
& xstate_zmm
) == xstate_zmm
)
9460 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_ZMM
;
9461 if (i
.mask
.reg
|| (i
.xstate
& xstate_mask
) == xstate_mask
)
9462 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_MASK
;
9463 if (i
.tm
.cpu_flags
.bitfield
.cpufxsr
)
9464 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_FXSR
;
9465 if (i
.tm
.cpu_flags
.bitfield
.cpuxsave
)
9466 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVE
;
9467 if (i
.tm
.cpu_flags
.bitfield
.cpuxsaveopt
)
9468 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVEOPT
;
9469 if (i
.tm
.cpu_flags
.bitfield
.cpuxsavec
)
9470 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVEC
;
9472 if (x86_feature_2_used
9473 || i
.tm
.cpu_flags
.bitfield
.cpucmov
9474 || i
.tm
.cpu_flags
.bitfield
.cpusyscall
9475 || (i
.tm
.opcode_modifier
.opcodespace
== SPACE_0F
9476 && i
.tm
.base_opcode
== 0xc7
9477 && i
.tm
.opcode_modifier
.opcodeprefix
== PREFIX_NONE
9478 && i
.tm
.extension_opcode
== 1) /* cmpxchg8b */)
9479 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_BASELINE
;
9480 if (i
.tm
.cpu_flags
.bitfield
.cpusse3
9481 || i
.tm
.cpu_flags
.bitfield
.cpussse3
9482 || i
.tm
.cpu_flags
.bitfield
.cpusse4_1
9483 || i
.tm
.cpu_flags
.bitfield
.cpusse4_2
9484 || i
.tm
.cpu_flags
.bitfield
.cpucx16
9485 || i
.tm
.cpu_flags
.bitfield
.cpupopcnt
9486 /* LAHF-SAHF insns in 64-bit mode. */
9487 || (flag_code
== CODE_64BIT
9488 && (i
.tm
.base_opcode
| 1) == 0x9f
9489 && i
.tm
.opcode_modifier
.opcodespace
== SPACE_BASE
))
9490 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_V2
;
9491 if (i
.tm
.cpu_flags
.bitfield
.cpuavx
9492 || i
.tm
.cpu_flags
.bitfield
.cpuavx2
9493 /* Any VEX encoded insns execpt for CpuAVX512F, CpuAVX512BW,
9494 CpuAVX512DQ, LPW, TBM and AMX. */
9495 || (i
.tm
.opcode_modifier
.vex
9496 && !i
.tm
.cpu_flags
.bitfield
.cpuavx512f
9497 && !i
.tm
.cpu_flags
.bitfield
.cpuavx512bw
9498 && !i
.tm
.cpu_flags
.bitfield
.cpuavx512dq
9499 && !i
.tm
.cpu_flags
.bitfield
.cpulwp
9500 && !i
.tm
.cpu_flags
.bitfield
.cputbm
9501 && !(x86_feature_2_used
& GNU_PROPERTY_X86_FEATURE_2_TMM
))
9502 || i
.tm
.cpu_flags
.bitfield
.cpuf16c
9503 || i
.tm
.cpu_flags
.bitfield
.cpufma
9504 || i
.tm
.cpu_flags
.bitfield
.cpulzcnt
9505 || i
.tm
.cpu_flags
.bitfield
.cpumovbe
9506 || i
.tm
.cpu_flags
.bitfield
.cpuxsaves
9507 || (x86_feature_2_used
9508 & (GNU_PROPERTY_X86_FEATURE_2_XSAVE
9509 | GNU_PROPERTY_X86_FEATURE_2_XSAVEOPT
9510 | GNU_PROPERTY_X86_FEATURE_2_XSAVEC
)) != 0)
9511 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_V3
;
9512 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512f
9513 || i
.tm
.cpu_flags
.bitfield
.cpuavx512bw
9514 || i
.tm
.cpu_flags
.bitfield
.cpuavx512dq
9515 || i
.tm
.cpu_flags
.bitfield
.cpuavx512vl
9516 /* Any EVEX encoded insns except for AVX512ER, AVX512PF and
9518 || (i
.tm
.opcode_modifier
.evex
9519 && !i
.tm
.cpu_flags
.bitfield
.cpuavx512er
9520 && !i
.tm
.cpu_flags
.bitfield
.cpuavx512pf
9521 && !i
.tm
.cpu_flags
.bitfield
.cpuavx512_4vnniw
))
9522 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_V4
;
9526 /* Tie dwarf2 debug info to the address at the start of the insn.
9527 We can't do this after the insn has been output as the current
9528 frag may have been closed off. eg. by frag_var. */
9529 dwarf2_emit_insn (0);
9531 insn_start_frag
= frag_now
;
9532 insn_start_off
= frag_now_fix ();
9534 if (add_branch_padding_frag_p (&branch
, &mf_jcc
))
9537 /* Branch can be 8 bytes. Leave some room for prefixes. */
9538 unsigned int max_branch_padding_size
= 14;
9540 /* Align section to boundary. */
9541 record_alignment (now_seg
, align_branch_power
);
9543 /* Make room for padding. */
9544 frag_grow (max_branch_padding_size
);
9546 /* Start of the padding. */
9551 frag_var (rs_machine_dependent
, max_branch_padding_size
, 0,
9552 ENCODE_RELAX_STATE (BRANCH_PADDING
, 0),
9555 fragP
->tc_frag_data
.mf_type
= mf_jcc
;
9556 fragP
->tc_frag_data
.branch_type
= branch
;
9557 fragP
->tc_frag_data
.max_bytes
= max_branch_padding_size
;
9561 if (i
.tm
.opcode_modifier
.jump
== JUMP
)
9563 else if (i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
9564 || i
.tm
.opcode_modifier
.jump
== JUMP_DWORD
)
9566 else if (i
.tm
.opcode_modifier
.jump
== JUMP_INTERSEGMENT
)
9567 output_interseg_jump ();
9570 /* Output normal instructions here. */
9574 enum mf_cmp_kind mf_cmp
;
9577 && (i
.tm
.base_opcode
== 0xaee8
9578 || i
.tm
.base_opcode
== 0xaef0
9579 || i
.tm
.base_opcode
== 0xaef8))
9581 /* Encode lfence, mfence, and sfence as
9582 f0 83 04 24 00 lock addl $0x0, (%{re}sp). */
9583 if (now_seg
!= absolute_section
)
9585 offsetT val
= 0x240483f0ULL
;
9588 md_number_to_chars (p
, val
, 5);
9591 abs_section_offset
+= 5;
9595 /* Some processors fail on LOCK prefix. This options makes
9596 assembler ignore LOCK prefix and serves as a workaround. */
9597 if (omit_lock_prefix
)
9599 if (i
.tm
.base_opcode
== LOCK_PREFIX_OPCODE
9600 && i
.tm
.opcode_modifier
.isprefix
)
9602 i
.prefix
[LOCK_PREFIX
] = 0;
9606 /* Skip if this is a branch. */
9608 else if (add_fused_jcc_padding_frag_p (&mf_cmp
))
9610 /* Make room for padding. */
9611 frag_grow (MAX_FUSED_JCC_PADDING_SIZE
);
9616 frag_var (rs_machine_dependent
, MAX_FUSED_JCC_PADDING_SIZE
, 0,
9617 ENCODE_RELAX_STATE (FUSED_JCC_PADDING
, 0),
9620 fragP
->tc_frag_data
.mf_type
= mf_cmp
;
9621 fragP
->tc_frag_data
.branch_type
= align_branch_fused
;
9622 fragP
->tc_frag_data
.max_bytes
= MAX_FUSED_JCC_PADDING_SIZE
;
9624 else if (add_branch_prefix_frag_p ())
9626 unsigned int max_prefix_size
= align_branch_prefix_size
;
9628 /* Make room for padding. */
9629 frag_grow (max_prefix_size
);
9634 frag_var (rs_machine_dependent
, max_prefix_size
, 0,
9635 ENCODE_RELAX_STATE (BRANCH_PREFIX
, 0),
9638 fragP
->tc_frag_data
.max_bytes
= max_prefix_size
;
9641 /* Since the VEX/EVEX prefix contains the implicit prefix, we
9642 don't need the explicit prefix. */
9643 if (!i
.tm
.opcode_modifier
.vex
&& !i
.tm
.opcode_modifier
.evex
)
9645 switch (i
.tm
.opcode_modifier
.opcodeprefix
)
9654 if (!i
.tm
.cpu_flags
.bitfield
.cpupadlock
9655 || (i
.prefix
[REP_PREFIX
] != 0xf3))
9659 switch (i
.opcode_length
)
9664 /* Check for pseudo prefixes. */
9665 if (!i
.tm
.opcode_modifier
.isprefix
|| i
.tm
.base_opcode
)
9667 as_bad_where (insn_start_frag
->fr_file
,
9668 insn_start_frag
->fr_line
,
9669 _("pseudo prefix without instruction"));
9679 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
9680 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
9681 R_X86_64_GOTTPOFF relocation so that linker can safely
9682 perform IE->LE optimization. A dummy REX_OPCODE prefix
9683 is also needed for lea with R_X86_64_GOTPC32_TLSDESC
9684 relocation for GDesc -> IE/LE optimization. */
9685 if (x86_elf_abi
== X86_64_X32_ABI
9687 && (i
.reloc
[0] == BFD_RELOC_X86_64_GOTTPOFF
9688 || i
.reloc
[0] == BFD_RELOC_X86_64_GOTPC32_TLSDESC
)
9689 && i
.prefix
[REX_PREFIX
] == 0)
9690 add_prefix (REX_OPCODE
);
9693 /* The prefix bytes. */
9694 for (j
= ARRAY_SIZE (i
.prefix
), q
= i
.prefix
; j
> 0; j
--, q
++)
9696 frag_opcode_byte (*q
);
9700 for (j
= 0, q
= i
.prefix
; j
< ARRAY_SIZE (i
.prefix
); j
++, q
++)
9706 frag_opcode_byte (*q
);
9709 /* There should be no other prefixes for instructions
9714 /* For EVEX instructions i.vrex should become 0 after
9715 build_evex_prefix. For VEX instructions upper 16 registers
9716 aren't available, so VREX should be 0. */
9719 /* Now the VEX prefix. */
9720 if (now_seg
!= absolute_section
)
9722 p
= frag_more (i
.vex
.length
);
9723 for (j
= 0; j
< i
.vex
.length
; j
++)
9724 p
[j
] = i
.vex
.bytes
[j
];
9727 abs_section_offset
+= i
.vex
.length
;
9730 /* Now the opcode; be careful about word order here! */
9731 j
= i
.opcode_length
;
9733 switch (i
.tm
.opcode_modifier
.opcodespace
)
9748 if (now_seg
== absolute_section
)
9749 abs_section_offset
+= j
;
9752 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
9758 && i
.tm
.opcode_modifier
.opcodespace
!= SPACE_BASE
)
9761 if (i
.tm
.opcode_modifier
.opcodespace
!= SPACE_0F
)
9762 *p
++ = i
.tm
.opcode_modifier
.opcodespace
== SPACE_0F38
9766 switch (i
.opcode_length
)
9769 /* Put out high byte first: can't use md_number_to_chars! */
9770 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
9773 *p
= i
.tm
.base_opcode
& 0xff;
9782 /* Now the modrm byte and sib byte (if present). */
9783 if (i
.tm
.opcode_modifier
.modrm
)
9785 frag_opcode_byte ((i
.rm
.regmem
<< 0)
9787 | (i
.rm
.mode
<< 6));
9788 /* If i.rm.regmem == ESP (4)
9789 && i.rm.mode != (Register mode)
9791 ==> need second modrm byte. */
9792 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
9794 && !(i
.base_reg
&& i
.base_reg
->reg_type
.bitfield
.word
))
9795 frag_opcode_byte ((i
.sib
.base
<< 0)
9796 | (i
.sib
.index
<< 3)
9797 | (i
.sib
.scale
<< 6));
9800 if (i
.disp_operands
)
9801 output_disp (insn_start_frag
, insn_start_off
);
9804 output_imm (insn_start_frag
, insn_start_off
);
9807 * frag_now_fix () returning plain abs_section_offset when we're in the
9808 * absolute section, and abs_section_offset not getting updated as data
9809 * gets added to the frag breaks the logic below.
9811 if (now_seg
!= absolute_section
)
9813 j
= encoding_length (insn_start_frag
, insn_start_off
, frag_more (0));
9815 as_warn (_("instruction length of %u bytes exceeds the limit of 15"),
9819 /* NB: Don't add prefix with GOTPC relocation since
9820 output_disp() above depends on the fixed encoding
9821 length. Can't add prefix with TLS relocation since
9822 it breaks TLS linker optimization. */
9823 unsigned int max
= i
.has_gotpc_tls_reloc
? 0 : 15 - j
;
9824 /* Prefix count on the current instruction. */
9825 unsigned int count
= i
.vex
.length
;
9827 for (k
= 0; k
< ARRAY_SIZE (i
.prefix
); k
++)
9828 /* REX byte is encoded in VEX/EVEX prefix. */
9829 if (i
.prefix
[k
] && (k
!= REX_PREFIX
|| !i
.vex
.length
))
9832 /* Count prefixes for extended opcode maps. */
9834 switch (i
.tm
.opcode_modifier
.opcodespace
)
9849 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
)
9852 /* Set the maximum prefix size in BRANCH_PREFIX
9854 if (fragP
->tc_frag_data
.max_bytes
> max
)
9855 fragP
->tc_frag_data
.max_bytes
= max
;
9856 if (fragP
->tc_frag_data
.max_bytes
> count
)
9857 fragP
->tc_frag_data
.max_bytes
-= count
;
9859 fragP
->tc_frag_data
.max_bytes
= 0;
9863 /* Remember the maximum prefix size in FUSED_JCC_PADDING
9865 unsigned int max_prefix_size
;
9866 if (align_branch_prefix_size
> max
)
9867 max_prefix_size
= max
;
9869 max_prefix_size
= align_branch_prefix_size
;
9870 if (max_prefix_size
> count
)
9871 fragP
->tc_frag_data
.max_prefix_length
9872 = max_prefix_size
- count
;
9875 /* Use existing segment prefix if possible. Use CS
9876 segment prefix in 64-bit mode. In 32-bit mode, use SS
9877 segment prefix with ESP/EBP base register and use DS
9878 segment prefix without ESP/EBP base register. */
9879 if (i
.prefix
[SEG_PREFIX
])
9880 fragP
->tc_frag_data
.default_prefix
= i
.prefix
[SEG_PREFIX
];
9881 else if (flag_code
== CODE_64BIT
)
9882 fragP
->tc_frag_data
.default_prefix
= CS_PREFIX_OPCODE
;
9884 && (i
.base_reg
->reg_num
== 4
9885 || i
.base_reg
->reg_num
== 5))
9886 fragP
->tc_frag_data
.default_prefix
= SS_PREFIX_OPCODE
;
9888 fragP
->tc_frag_data
.default_prefix
= DS_PREFIX_OPCODE
;
9893 /* NB: Don't work with COND_JUMP86 without i386. */
9894 if (align_branch_power
9895 && now_seg
!= absolute_section
9896 && cpu_arch_flags
.bitfield
.cpui386
)
9898 /* Terminate each frag so that we can add prefix and check for
9900 frag_wane (frag_now
);
9907 pi ("" /*line*/, &i
);
9909 #endif /* DEBUG386 */
9912 /* Return the size of the displacement operand N. */
9915 disp_size (unsigned int n
)
9919 if (i
.types
[n
].bitfield
.disp64
)
9921 else if (i
.types
[n
].bitfield
.disp8
)
9923 else if (i
.types
[n
].bitfield
.disp16
)
9928 /* Return the size of the immediate operand N. */
9931 imm_size (unsigned int n
)
9934 if (i
.types
[n
].bitfield
.imm64
)
9936 else if (i
.types
[n
].bitfield
.imm8
|| i
.types
[n
].bitfield
.imm8s
)
9938 else if (i
.types
[n
].bitfield
.imm16
)
9944 output_disp (fragS
*insn_start_frag
, offsetT insn_start_off
)
9949 for (n
= 0; n
< i
.operands
; n
++)
9951 if (operand_type_check (i
.types
[n
], disp
))
9953 int size
= disp_size (n
);
9955 if (now_seg
== absolute_section
)
9956 abs_section_offset
+= size
;
9957 else if (i
.op
[n
].disps
->X_op
== O_constant
)
9959 offsetT val
= i
.op
[n
].disps
->X_add_number
;
9961 val
= offset_in_range (val
>> (size
== 1 ? i
.memshift
: 0),
9963 p
= frag_more (size
);
9964 md_number_to_chars (p
, val
, size
);
9968 enum bfd_reloc_code_real reloc_type
;
9969 int sign
= i
.types
[n
].bitfield
.disp32s
;
9970 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
9973 /* We can't have 8 bit displacement here. */
9974 gas_assert (!i
.types
[n
].bitfield
.disp8
);
9976 /* The PC relative address is computed relative
9977 to the instruction boundary, so in case immediate
9978 fields follows, we need to adjust the value. */
9979 if (pcrel
&& i
.imm_operands
)
9984 for (n1
= 0; n1
< i
.operands
; n1
++)
9985 if (operand_type_check (i
.types
[n1
], imm
))
9987 /* Only one immediate is allowed for PC
9988 relative address. */
9989 gas_assert (sz
== 0);
9991 i
.op
[n
].disps
->X_add_number
-= sz
;
9993 /* We should find the immediate. */
9994 gas_assert (sz
!= 0);
9997 p
= frag_more (size
);
9998 reloc_type
= reloc (size
, pcrel
, sign
, i
.reloc
[n
]);
10000 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
10001 && (((reloc_type
== BFD_RELOC_32
10002 || reloc_type
== BFD_RELOC_X86_64_32S
10003 || (reloc_type
== BFD_RELOC_64
10005 && (i
.op
[n
].disps
->X_op
== O_symbol
10006 || (i
.op
[n
].disps
->X_op
== O_add
10007 && ((symbol_get_value_expression
10008 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
10010 || reloc_type
== BFD_RELOC_32_PCREL
))
10014 reloc_type
= BFD_RELOC_386_GOTPC
;
10015 i
.has_gotpc_tls_reloc
= true;
10016 i
.op
[n
].disps
->X_add_number
+=
10017 encoding_length (insn_start_frag
, insn_start_off
, p
);
10019 else if (reloc_type
== BFD_RELOC_64
)
10020 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
10022 /* Don't do the adjustment for x86-64, as there
10023 the pcrel addressing is relative to the _next_
10024 insn, and that is taken care of in other code. */
10025 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
10027 else if (align_branch_power
)
10029 switch (reloc_type
)
10031 case BFD_RELOC_386_TLS_GD
:
10032 case BFD_RELOC_386_TLS_LDM
:
10033 case BFD_RELOC_386_TLS_IE
:
10034 case BFD_RELOC_386_TLS_IE_32
:
10035 case BFD_RELOC_386_TLS_GOTIE
:
10036 case BFD_RELOC_386_TLS_GOTDESC
:
10037 case BFD_RELOC_386_TLS_DESC_CALL
:
10038 case BFD_RELOC_X86_64_TLSGD
:
10039 case BFD_RELOC_X86_64_TLSLD
:
10040 case BFD_RELOC_X86_64_GOTTPOFF
:
10041 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
10042 case BFD_RELOC_X86_64_TLSDESC_CALL
:
10043 i
.has_gotpc_tls_reloc
= true;
10048 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
10049 size
, i
.op
[n
].disps
, pcrel
,
10052 if (flag_code
== CODE_64BIT
&& size
== 4 && pcrel
10053 && !i
.prefix
[ADDR_PREFIX
])
10054 fixP
->fx_signed
= 1;
10056 /* Check for "call/jmp *mem", "mov mem, %reg",
10057 "test %reg, mem" and "binop mem, %reg" where binop
10058 is one of adc, add, and, cmp, or, sbb, sub, xor
10059 instructions without data prefix. Always generate
10060 R_386_GOT32X for "sym*GOT" operand in 32-bit mode. */
10061 if (i
.prefix
[DATA_PREFIX
] == 0
10062 && (generate_relax_relocations
10065 && i
.rm
.regmem
== 5))
10067 || (i
.rm
.mode
== 0 && i
.rm
.regmem
== 5))
10068 && i
.tm
.opcode_modifier
.opcodespace
== SPACE_BASE
10069 && ((i
.operands
== 1
10070 && i
.tm
.base_opcode
== 0xff
10071 && (i
.rm
.reg
== 2 || i
.rm
.reg
== 4))
10072 || (i
.operands
== 2
10073 && (i
.tm
.base_opcode
== 0x8b
10074 || i
.tm
.base_opcode
== 0x85
10075 || (i
.tm
.base_opcode
& ~0x38) == 0x03))))
10079 fixP
->fx_tcbit
= i
.rex
!= 0;
10081 && (i
.base_reg
->reg_num
== RegIP
))
10082 fixP
->fx_tcbit2
= 1;
10085 fixP
->fx_tcbit2
= 1;
10093 output_imm (fragS
*insn_start_frag
, offsetT insn_start_off
)
10098 for (n
= 0; n
< i
.operands
; n
++)
10100 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
10101 if (i
.rounding
.type
!= rc_none
&& n
== i
.rounding
.operand
)
10104 if (operand_type_check (i
.types
[n
], imm
))
10106 int size
= imm_size (n
);
10108 if (now_seg
== absolute_section
)
10109 abs_section_offset
+= size
;
10110 else if (i
.op
[n
].imms
->X_op
== O_constant
)
10114 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
10116 p
= frag_more (size
);
10117 md_number_to_chars (p
, val
, size
);
10121 /* Not absolute_section.
10122 Need a 32-bit fixup (don't support 8bit
10123 non-absolute imms). Try to support other
10125 enum bfd_reloc_code_real reloc_type
;
10128 if (i
.types
[n
].bitfield
.imm32s
10129 && (i
.suffix
== QWORD_MNEM_SUFFIX
10130 || (!i
.suffix
&& i
.tm
.opcode_modifier
.no_lsuf
)))
10135 p
= frag_more (size
);
10136 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
10138 /* This is tough to explain. We end up with this one if we
10139 * have operands that look like
10140 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
10141 * obtain the absolute address of the GOT, and it is strongly
10142 * preferable from a performance point of view to avoid using
10143 * a runtime relocation for this. The actual sequence of
10144 * instructions often look something like:
10149 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
10151 * The call and pop essentially return the absolute address
10152 * of the label .L66 and store it in %ebx. The linker itself
10153 * will ultimately change the first operand of the addl so
10154 * that %ebx points to the GOT, but to keep things simple, the
10155 * .o file must have this operand set so that it generates not
10156 * the absolute address of .L66, but the absolute address of
10157 * itself. This allows the linker itself simply treat a GOTPC
10158 * relocation as asking for a pcrel offset to the GOT to be
10159 * added in, and the addend of the relocation is stored in the
10160 * operand field for the instruction itself.
10162 * Our job here is to fix the operand so that it would add
10163 * the correct offset so that %ebx would point to itself. The
10164 * thing that is tricky is that .-.L66 will point to the
10165 * beginning of the instruction, so we need to further modify
10166 * the operand so that it will point to itself. There are
10167 * other cases where you have something like:
10169 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
10171 * and here no correction would be required. Internally in
10172 * the assembler we treat operands of this form as not being
10173 * pcrel since the '.' is explicitly mentioned, and I wonder
10174 * whether it would simplify matters to do it this way. Who
10175 * knows. In earlier versions of the PIC patches, the
10176 * pcrel_adjust field was used to store the correction, but
10177 * since the expression is not pcrel, I felt it would be
10178 * confusing to do it this way. */
10180 if ((reloc_type
== BFD_RELOC_32
10181 || reloc_type
== BFD_RELOC_X86_64_32S
10182 || reloc_type
== BFD_RELOC_64
)
10184 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
10185 && (i
.op
[n
].imms
->X_op
== O_symbol
10186 || (i
.op
[n
].imms
->X_op
== O_add
10187 && ((symbol_get_value_expression
10188 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
10192 reloc_type
= BFD_RELOC_386_GOTPC
;
10193 else if (size
== 4)
10194 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
10195 else if (size
== 8)
10196 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
10197 i
.has_gotpc_tls_reloc
= true;
10198 i
.op
[n
].imms
->X_add_number
+=
10199 encoding_length (insn_start_frag
, insn_start_off
, p
);
10201 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
10202 i
.op
[n
].imms
, 0, reloc_type
);
10208 /* x86_cons_fix_new is called via the expression parsing code when a
10209 reloc is needed. We use this hook to get the correct .got reloc. */
10210 static int cons_sign
= -1;
10213 x86_cons_fix_new (fragS
*frag
, unsigned int off
, unsigned int len
,
10214 expressionS
*exp
, bfd_reloc_code_real_type r
)
10216 r
= reloc (len
, 0, cons_sign
, r
);
10219 if (exp
->X_op
== O_secrel
)
10221 exp
->X_op
= O_symbol
;
10222 r
= BFD_RELOC_32_SECREL
;
10226 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
10229 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
10230 purpose of the `.dc.a' internal pseudo-op. */
10233 x86_address_bytes (void)
10235 if ((stdoutput
->arch_info
->mach
& bfd_mach_x64_32
))
10237 return stdoutput
->arch_info
->bits_per_address
/ 8;
10240 #if (!(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
10241 || defined (LEX_AT)) && !defined (TE_PE)
10242 # define lex_got(reloc, adjust, types) NULL
10244 /* Parse operands of the form
10245 <symbol>@GOTOFF+<nnn>
10246 and similar .plt or .got references.
10248 If we find one, set up the correct relocation in RELOC and copy the
10249 input string, minus the `@GOTOFF' into a malloc'd buffer for
10250 parsing by the calling routine. Return this buffer, and if ADJUST
10251 is non-null set it to the length of the string we removed from the
10252 input line. Otherwise return NULL. */
10254 lex_got (enum bfd_reloc_code_real
*rel
,
10256 i386_operand_type
*types
)
10258 /* Some of the relocations depend on the size of what field is to
10259 be relocated. But in our callers i386_immediate and i386_displacement
10260 we don't yet know the operand size (this will be set by insn
10261 matching). Hence we record the word32 relocation here,
10262 and adjust the reloc according to the real size in reloc(). */
10263 static const struct {
10266 const enum bfd_reloc_code_real rel
[2];
10267 const i386_operand_type types64
;
10268 bool need_GOT_symbol
;
10271 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10272 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32
,
10273 BFD_RELOC_SIZE32
},
10274 OPERAND_TYPE_IMM32_64
, false },
10276 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real
,
10277 BFD_RELOC_X86_64_PLTOFF64
},
10278 OPERAND_TYPE_IMM64
, true },
10279 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32
,
10280 BFD_RELOC_X86_64_PLT32
},
10281 OPERAND_TYPE_IMM32_32S_DISP32
, false },
10282 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real
,
10283 BFD_RELOC_X86_64_GOTPLT64
},
10284 OPERAND_TYPE_IMM64_DISP64
, true },
10285 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF
,
10286 BFD_RELOC_X86_64_GOTOFF64
},
10287 OPERAND_TYPE_IMM64_DISP64
, true },
10288 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real
,
10289 BFD_RELOC_X86_64_GOTPCREL
},
10290 OPERAND_TYPE_IMM32_32S_DISP32
, true },
10291 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD
,
10292 BFD_RELOC_X86_64_TLSGD
},
10293 OPERAND_TYPE_IMM32_32S_DISP32
, true },
10294 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM
,
10295 _dummy_first_bfd_reloc_code_real
},
10296 OPERAND_TYPE_NONE
, true },
10297 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real
,
10298 BFD_RELOC_X86_64_TLSLD
},
10299 OPERAND_TYPE_IMM32_32S_DISP32
, true },
10300 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32
,
10301 BFD_RELOC_X86_64_GOTTPOFF
},
10302 OPERAND_TYPE_IMM32_32S_DISP32
, true },
10303 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32
,
10304 BFD_RELOC_X86_64_TPOFF32
},
10305 OPERAND_TYPE_IMM32_32S_64_DISP32_64
, true },
10306 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE
,
10307 _dummy_first_bfd_reloc_code_real
},
10308 OPERAND_TYPE_NONE
, true },
10309 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32
,
10310 BFD_RELOC_X86_64_DTPOFF32
},
10311 OPERAND_TYPE_IMM32_32S_64_DISP32_64
, true },
10312 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE
,
10313 _dummy_first_bfd_reloc_code_real
},
10314 OPERAND_TYPE_NONE
, true },
10315 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE
,
10316 _dummy_first_bfd_reloc_code_real
},
10317 OPERAND_TYPE_NONE
, true },
10318 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32
,
10319 BFD_RELOC_X86_64_GOT32
},
10320 OPERAND_TYPE_IMM32_32S_64_DISP32
, true },
10321 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC
,
10322 BFD_RELOC_X86_64_GOTPC32_TLSDESC
},
10323 OPERAND_TYPE_IMM32_32S_DISP32
, true },
10324 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL
,
10325 BFD_RELOC_X86_64_TLSDESC_CALL
},
10326 OPERAND_TYPE_IMM32_32S_DISP32
, true },
10328 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL
,
10329 BFD_RELOC_32_SECREL
},
10330 OPERAND_TYPE_IMM32_32S_64_DISP32_64
, false },
10336 #if defined (OBJ_MAYBE_ELF) && !defined (TE_PE)
10341 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
10342 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
10345 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
10347 int len
= gotrel
[j
].len
;
10348 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
10350 if (gotrel
[j
].rel
[object_64bit
] != 0)
10353 char *tmpbuf
, *past_reloc
;
10355 *rel
= gotrel
[j
].rel
[object_64bit
];
10359 if (flag_code
!= CODE_64BIT
)
10361 types
->bitfield
.imm32
= 1;
10362 types
->bitfield
.disp32
= 1;
10365 *types
= gotrel
[j
].types64
;
10368 if (gotrel
[j
].need_GOT_symbol
&& GOT_symbol
== NULL
)
10369 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
10371 /* The length of the first part of our input line. */
10372 first
= cp
- input_line_pointer
;
10374 /* The second part goes from after the reloc token until
10375 (and including) an end_of_line char or comma. */
10376 past_reloc
= cp
+ 1 + len
;
10378 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
10380 second
= cp
+ 1 - past_reloc
;
10382 /* Allocate and copy string. The trailing NUL shouldn't
10383 be necessary, but be safe. */
10384 tmpbuf
= XNEWVEC (char, first
+ second
+ 2);
10385 memcpy (tmpbuf
, input_line_pointer
, first
);
10386 if (second
!= 0 && *past_reloc
!= ' ')
10387 /* Replace the relocation token with ' ', so that
10388 errors like foo@GOTOFF1 will be detected. */
10389 tmpbuf
[first
++] = ' ';
10391 /* Increment length by 1 if the relocation token is
10396 memcpy (tmpbuf
+ first
, past_reloc
, second
);
10397 tmpbuf
[first
+ second
] = '\0';
10401 as_bad (_("@%s reloc is not supported with %d-bit output format"),
10402 gotrel
[j
].str
, 1 << (5 + object_64bit
));
10407 /* Might be a symbol version string. Don't as_bad here. */
10412 bfd_reloc_code_real_type
10413 x86_cons (expressionS
*exp
, int size
)
10415 bfd_reloc_code_real_type got_reloc
= NO_RELOC
;
10417 intel_syntax
= -intel_syntax
;
10420 if (size
== 4 || (object_64bit
&& size
== 8))
10422 /* Handle @GOTOFF and the like in an expression. */
10424 char *gotfree_input_line
;
10427 save
= input_line_pointer
;
10428 gotfree_input_line
= lex_got (&got_reloc
, &adjust
, NULL
);
10429 if (gotfree_input_line
)
10430 input_line_pointer
= gotfree_input_line
;
10434 if (gotfree_input_line
)
10436 /* expression () has merrily parsed up to the end of line,
10437 or a comma - in the wrong buffer. Transfer how far
10438 input_line_pointer has moved to the right buffer. */
10439 input_line_pointer
= (save
10440 + (input_line_pointer
- gotfree_input_line
)
10442 free (gotfree_input_line
);
10443 if (exp
->X_op
== O_constant
10444 || exp
->X_op
== O_absent
10445 || exp
->X_op
== O_illegal
10446 || exp
->X_op
== O_register
10447 || exp
->X_op
== O_big
)
10449 char c
= *input_line_pointer
;
10450 *input_line_pointer
= 0;
10451 as_bad (_("missing or invalid expression `%s'"), save
);
10452 *input_line_pointer
= c
;
10454 else if ((got_reloc
== BFD_RELOC_386_PLT32
10455 || got_reloc
== BFD_RELOC_X86_64_PLT32
)
10456 && exp
->X_op
!= O_symbol
)
10458 char c
= *input_line_pointer
;
10459 *input_line_pointer
= 0;
10460 as_bad (_("invalid PLT expression `%s'"), save
);
10461 *input_line_pointer
= c
;
10468 intel_syntax
= -intel_syntax
;
10471 i386_intel_simplify (exp
);
10473 /* If not 64bit, massage value, to account for wraparound when !BFD64. */
10474 if (size
== 4 && exp
->X_op
== O_constant
&& !object_64bit
)
10475 exp
->X_add_number
= extend_to_32bit_address (exp
->X_add_number
);
10481 signed_cons (int size
)
10491 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
10498 if (exp
.X_op
== O_symbol
)
10499 exp
.X_op
= O_secrel
;
10501 emit_expr (&exp
, 4);
10503 while (*input_line_pointer
++ == ',');
10505 input_line_pointer
--;
10506 demand_empty_rest_of_line ();
10510 /* Handle Vector operations. */
10513 check_VecOperations (char *op_string
, char *op_end
)
10515 const reg_entry
*mask
;
10520 && (op_end
== NULL
|| op_string
< op_end
))
10523 if (*op_string
== '{')
10527 /* Check broadcasts. */
10528 if (startswith (op_string
, "1to"))
10530 unsigned int bcst_type
;
10532 if (i
.broadcast
.type
)
10533 goto duplicated_vec_op
;
10536 if (*op_string
== '8')
10538 else if (*op_string
== '4')
10540 else if (*op_string
== '2')
10542 else if (*op_string
== '1'
10543 && *(op_string
+1) == '6')
10550 as_bad (_("Unsupported broadcast: `%s'"), saved
);
10555 i
.broadcast
.type
= bcst_type
;
10556 i
.broadcast
.operand
= this_operand
;
10558 /* Check masking operation. */
10559 else if ((mask
= parse_register (op_string
, &end_op
)) != NULL
)
10561 if (mask
== &bad_reg
)
10564 /* k0 can't be used for write mask. */
10565 if (mask
->reg_type
.bitfield
.class != RegMask
|| !mask
->reg_num
)
10567 as_bad (_("`%s%s' can't be used for write mask"),
10568 register_prefix
, mask
->reg_name
);
10575 i
.mask
.operand
= this_operand
;
10577 else if (i
.mask
.reg
->reg_num
)
10578 goto duplicated_vec_op
;
10583 /* Only "{z}" is allowed here. No need to check
10584 zeroing mask explicitly. */
10585 if (i
.mask
.operand
!= (unsigned int) this_operand
)
10587 as_bad (_("invalid write mask `%s'"), saved
);
10592 op_string
= end_op
;
10594 /* Check zeroing-flag for masking operation. */
10595 else if (*op_string
== 'z')
10599 i
.mask
.reg
= reg_k0
;
10600 i
.mask
.zeroing
= 1;
10601 i
.mask
.operand
= this_operand
;
10605 if (i
.mask
.zeroing
)
10608 as_bad (_("duplicated `%s'"), saved
);
10612 i
.mask
.zeroing
= 1;
10614 /* Only "{%k}" is allowed here. No need to check mask
10615 register explicitly. */
10616 if (i
.mask
.operand
!= (unsigned int) this_operand
)
10618 as_bad (_("invalid zeroing-masking `%s'"),
10627 goto unknown_vec_op
;
10629 if (*op_string
!= '}')
10631 as_bad (_("missing `}' in `%s'"), saved
);
10636 /* Strip whitespace since the addition of pseudo prefixes
10637 changed how the scrubber treats '{'. */
10638 if (is_space_char (*op_string
))
10644 /* We don't know this one. */
10645 as_bad (_("unknown vector operation: `%s'"), saved
);
10649 if (i
.mask
.reg
&& i
.mask
.zeroing
&& !i
.mask
.reg
->reg_num
)
10651 as_bad (_("zeroing-masking only allowed with write mask"));
10659 i386_immediate (char *imm_start
)
10661 char *save_input_line_pointer
;
10662 char *gotfree_input_line
;
10665 i386_operand_type types
;
10667 operand_type_set (&types
, ~0);
10669 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
10671 as_bad (_("at most %d immediate operands are allowed"),
10672 MAX_IMMEDIATE_OPERANDS
);
10676 exp
= &im_expressions
[i
.imm_operands
++];
10677 i
.op
[this_operand
].imms
= exp
;
10679 if (is_space_char (*imm_start
))
10682 save_input_line_pointer
= input_line_pointer
;
10683 input_line_pointer
= imm_start
;
10685 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
10686 if (gotfree_input_line
)
10687 input_line_pointer
= gotfree_input_line
;
10689 exp_seg
= expression (exp
);
10691 SKIP_WHITESPACE ();
10693 /* Handle vector operations. */
10694 if (*input_line_pointer
== '{')
10696 input_line_pointer
= check_VecOperations (input_line_pointer
,
10698 if (input_line_pointer
== NULL
)
10702 if (*input_line_pointer
)
10703 as_bad (_("junk `%s' after expression"), input_line_pointer
);
10705 input_line_pointer
= save_input_line_pointer
;
10706 if (gotfree_input_line
)
10708 free (gotfree_input_line
);
10710 if (exp
->X_op
== O_constant
)
10711 exp
->X_op
= O_illegal
;
10714 if (exp_seg
== reg_section
)
10716 as_bad (_("illegal immediate register operand %s"), imm_start
);
10720 return i386_finalize_immediate (exp_seg
, exp
, types
, imm_start
);
10724 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
10725 i386_operand_type types
, const char *imm_start
)
10727 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_illegal
|| exp
->X_op
== O_big
)
10730 as_bad (_("missing or invalid immediate expression `%s'"),
10734 else if (exp
->X_op
== O_constant
)
10736 /* Size it properly later. */
10737 i
.types
[this_operand
].bitfield
.imm64
= 1;
10739 /* If not 64bit, sign/zero extend val, to account for wraparound
10741 if (flag_code
!= CODE_64BIT
)
10742 exp
->X_add_number
= extend_to_32bit_address (exp
->X_add_number
);
10744 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
10745 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
10746 && exp_seg
!= absolute_section
10747 && exp_seg
!= text_section
10748 && exp_seg
!= data_section
10749 && exp_seg
!= bss_section
10750 && exp_seg
!= undefined_section
10751 && !bfd_is_com_section (exp_seg
))
10753 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
10759 /* This is an address. The size of the address will be
10760 determined later, depending on destination register,
10761 suffix, or the default for the section. */
10762 i
.types
[this_operand
].bitfield
.imm8
= 1;
10763 i
.types
[this_operand
].bitfield
.imm16
= 1;
10764 i
.types
[this_operand
].bitfield
.imm32
= 1;
10765 i
.types
[this_operand
].bitfield
.imm32s
= 1;
10766 i
.types
[this_operand
].bitfield
.imm64
= 1;
10767 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
10775 i386_scale (char *scale
)
10778 char *save
= input_line_pointer
;
10780 input_line_pointer
= scale
;
10781 val
= get_absolute_expression ();
10786 i
.log2_scale_factor
= 0;
10789 i
.log2_scale_factor
= 1;
10792 i
.log2_scale_factor
= 2;
10795 i
.log2_scale_factor
= 3;
10799 char sep
= *input_line_pointer
;
10801 *input_line_pointer
= '\0';
10802 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
10804 *input_line_pointer
= sep
;
10805 input_line_pointer
= save
;
10809 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
10811 as_warn (_("scale factor of %d without an index register"),
10812 1 << i
.log2_scale_factor
);
10813 i
.log2_scale_factor
= 0;
10815 scale
= input_line_pointer
;
10816 input_line_pointer
= save
;
10821 i386_displacement (char *disp_start
, char *disp_end
)
10825 char *save_input_line_pointer
;
10826 char *gotfree_input_line
;
10828 i386_operand_type bigdisp
, types
= anydisp
;
10831 if (i
.disp_operands
== MAX_MEMORY_OPERANDS
)
10833 as_bad (_("at most %d displacement operands are allowed"),
10834 MAX_MEMORY_OPERANDS
);
10838 operand_type_set (&bigdisp
, 0);
10840 || i
.types
[this_operand
].bitfield
.baseindex
10841 || (current_templates
->start
->opcode_modifier
.jump
!= JUMP
10842 && current_templates
->start
->opcode_modifier
.jump
!= JUMP_DWORD
))
10844 i386_addressing_mode ();
10845 override
= (i
.prefix
[ADDR_PREFIX
] != 0);
10846 if (flag_code
== CODE_64BIT
)
10850 bigdisp
.bitfield
.disp32s
= 1;
10851 bigdisp
.bitfield
.disp64
= 1;
10854 bigdisp
.bitfield
.disp32
= 1;
10856 else if ((flag_code
== CODE_16BIT
) ^ override
)
10857 bigdisp
.bitfield
.disp16
= 1;
10859 bigdisp
.bitfield
.disp32
= 1;
10863 /* For PC-relative branches, the width of the displacement may be
10864 dependent upon data size, but is never dependent upon address size.
10865 Also make sure to not unintentionally match against a non-PC-relative
10866 branch template. */
10867 static templates aux_templates
;
10868 const insn_template
*t
= current_templates
->start
;
10869 bool has_intel64
= false;
10871 aux_templates
.start
= t
;
10872 while (++t
< current_templates
->end
)
10874 if (t
->opcode_modifier
.jump
10875 != current_templates
->start
->opcode_modifier
.jump
)
10877 if ((t
->opcode_modifier
.isa64
>= INTEL64
))
10878 has_intel64
= true;
10880 if (t
< current_templates
->end
)
10882 aux_templates
.end
= t
;
10883 current_templates
= &aux_templates
;
10886 override
= (i
.prefix
[DATA_PREFIX
] != 0);
10887 if (flag_code
== CODE_64BIT
)
10889 if ((override
|| i
.suffix
== WORD_MNEM_SUFFIX
)
10890 && (!intel64
|| !has_intel64
))
10891 bigdisp
.bitfield
.disp16
= 1;
10893 bigdisp
.bitfield
.disp32s
= 1;
10898 override
= (i
.suffix
== (flag_code
!= CODE_16BIT
10900 : LONG_MNEM_SUFFIX
));
10901 bigdisp
.bitfield
.disp32
= 1;
10902 if ((flag_code
== CODE_16BIT
) ^ override
)
10904 bigdisp
.bitfield
.disp32
= 0;
10905 bigdisp
.bitfield
.disp16
= 1;
10909 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
10912 exp
= &disp_expressions
[i
.disp_operands
];
10913 i
.op
[this_operand
].disps
= exp
;
10915 save_input_line_pointer
= input_line_pointer
;
10916 input_line_pointer
= disp_start
;
10917 END_STRING_AND_SAVE (disp_end
);
10919 #ifndef GCC_ASM_O_HACK
10920 #define GCC_ASM_O_HACK 0
10923 END_STRING_AND_SAVE (disp_end
+ 1);
10924 if (i
.types
[this_operand
].bitfield
.baseIndex
10925 && displacement_string_end
[-1] == '+')
10927 /* This hack is to avoid a warning when using the "o"
10928 constraint within gcc asm statements.
10931 #define _set_tssldt_desc(n,addr,limit,type) \
10932 __asm__ __volatile__ ( \
10933 "movw %w2,%0\n\t" \
10934 "movw %w1,2+%0\n\t" \
10935 "rorl $16,%1\n\t" \
10936 "movb %b1,4+%0\n\t" \
10937 "movb %4,5+%0\n\t" \
10938 "movb $0,6+%0\n\t" \
10939 "movb %h1,7+%0\n\t" \
10941 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
10943 This works great except that the output assembler ends
10944 up looking a bit weird if it turns out that there is
10945 no offset. You end up producing code that looks like:
10958 So here we provide the missing zero. */
10960 *displacement_string_end
= '0';
10963 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
10964 if (gotfree_input_line
)
10965 input_line_pointer
= gotfree_input_line
;
10967 exp_seg
= expression (exp
);
10969 SKIP_WHITESPACE ();
10970 if (*input_line_pointer
)
10971 as_bad (_("junk `%s' after expression"), input_line_pointer
);
10973 RESTORE_END_STRING (disp_end
+ 1);
10975 input_line_pointer
= save_input_line_pointer
;
10976 if (gotfree_input_line
)
10978 free (gotfree_input_line
);
10980 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
10981 exp
->X_op
= O_illegal
;
10984 ret
= i386_finalize_displacement (exp_seg
, exp
, types
, disp_start
);
10986 RESTORE_END_STRING (disp_end
);
10992 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
10993 i386_operand_type types
, const char *disp_start
)
10995 i386_operand_type bigdisp
;
10998 /* We do this to make sure that the section symbol is in
10999 the symbol table. We will ultimately change the relocation
11000 to be relative to the beginning of the section. */
11001 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
11002 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
11003 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
11005 if (exp
->X_op
!= O_symbol
)
11008 if (S_IS_LOCAL (exp
->X_add_symbol
)
11009 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
11010 && S_GET_SEGMENT (exp
->X_add_symbol
) != expr_section
)
11011 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
11012 exp
->X_op
= O_subtract
;
11013 exp
->X_op_symbol
= GOT_symbol
;
11014 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
11015 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
11016 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
11017 i
.reloc
[this_operand
] = BFD_RELOC_64
;
11019 i
.reloc
[this_operand
] = BFD_RELOC_32
;
11022 else if (exp
->X_op
== O_absent
11023 || exp
->X_op
== O_illegal
11024 || exp
->X_op
== O_big
)
11027 as_bad (_("missing or invalid displacement expression `%s'"),
11032 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
11033 else if (exp
->X_op
!= O_constant
11034 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
11035 && exp_seg
!= absolute_section
11036 && exp_seg
!= text_section
11037 && exp_seg
!= data_section
11038 && exp_seg
!= bss_section
11039 && exp_seg
!= undefined_section
11040 && !bfd_is_com_section (exp_seg
))
11042 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
11047 if (current_templates
->start
->opcode_modifier
.jump
== JUMP_BYTE
11048 /* Constants get taken care of by optimize_disp(). */
11049 && exp
->X_op
!= O_constant
)
11050 i
.types
[this_operand
].bitfield
.disp8
= 1;
11052 /* Check if this is a displacement only operand. */
11053 bigdisp
= i
.types
[this_operand
];
11054 bigdisp
.bitfield
.disp8
= 0;
11055 bigdisp
.bitfield
.disp16
= 0;
11056 bigdisp
.bitfield
.disp32
= 0;
11057 bigdisp
.bitfield
.disp32s
= 0;
11058 bigdisp
.bitfield
.disp64
= 0;
11059 if (operand_type_all_zero (&bigdisp
))
11060 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
11066 /* Return the active addressing mode, taking address override and
11067 registers forming the address into consideration. Update the
11068 address override prefix if necessary. */
11070 static enum flag_code
11071 i386_addressing_mode (void)
11073 enum flag_code addr_mode
;
11075 if (i
.prefix
[ADDR_PREFIX
])
11076 addr_mode
= flag_code
== CODE_32BIT
? CODE_16BIT
: CODE_32BIT
;
11077 else if (flag_code
== CODE_16BIT
11078 && current_templates
->start
->cpu_flags
.bitfield
.cpumpx
11079 /* Avoid replacing the "16-bit addressing not allowed" diagnostic
11080 from md_assemble() by "is not a valid base/index expression"
11081 when there is a base and/or index. */
11082 && !i
.types
[this_operand
].bitfield
.baseindex
)
11084 /* MPX insn memory operands with neither base nor index must be forced
11085 to use 32-bit addressing in 16-bit mode. */
11086 addr_mode
= CODE_32BIT
;
11087 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
11089 gas_assert (!i
.types
[this_operand
].bitfield
.disp16
);
11090 gas_assert (!i
.types
[this_operand
].bitfield
.disp32
);
11094 addr_mode
= flag_code
;
11096 #if INFER_ADDR_PREFIX
11097 if (i
.mem_operands
== 0)
11099 /* Infer address prefix from the first memory operand. */
11100 const reg_entry
*addr_reg
= i
.base_reg
;
11102 if (addr_reg
== NULL
)
11103 addr_reg
= i
.index_reg
;
11107 if (addr_reg
->reg_type
.bitfield
.dword
)
11108 addr_mode
= CODE_32BIT
;
11109 else if (flag_code
!= CODE_64BIT
11110 && addr_reg
->reg_type
.bitfield
.word
)
11111 addr_mode
= CODE_16BIT
;
11113 if (addr_mode
!= flag_code
)
11115 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
11117 /* Change the size of any displacement too. At most one
11118 of Disp16 or Disp32 is set.
11119 FIXME. There doesn't seem to be any real need for
11120 separate Disp16 and Disp32 flags. The same goes for
11121 Imm16 and Imm32. Removing them would probably clean
11122 up the code quite a lot. */
11123 if (flag_code
!= CODE_64BIT
11124 && (i
.types
[this_operand
].bitfield
.disp16
11125 || i
.types
[this_operand
].bitfield
.disp32
))
11126 i
.types
[this_operand
]
11127 = operand_type_xor (i
.types
[this_operand
], disp16_32
);
11137 /* Make sure the memory operand we've been dealt is valid.
11138 Return 1 on success, 0 on a failure. */
11141 i386_index_check (const char *operand_string
)
11143 const char *kind
= "base/index";
11144 enum flag_code addr_mode
= i386_addressing_mode ();
11145 const insn_template
*t
= current_templates
->start
;
11147 if (t
->opcode_modifier
.isstring
11148 && !t
->cpu_flags
.bitfield
.cpupadlock
11149 && (current_templates
->end
[-1].opcode_modifier
.isstring
11150 || i
.mem_operands
))
11152 /* Memory operands of string insns are special in that they only allow
11153 a single register (rDI, rSI, or rBX) as their memory address. */
11154 const reg_entry
*expected_reg
;
11155 static const char *di_si
[][2] =
11161 static const char *bx
[] = { "ebx", "bx", "rbx" };
11163 kind
= "string address";
11165 if (t
->opcode_modifier
.prefixok
== PrefixRep
)
11167 int es_op
= current_templates
->end
[-1].opcode_modifier
.isstring
11168 - IS_STRING_ES_OP0
;
11171 if (!current_templates
->end
[-1].operand_types
[0].bitfield
.baseindex
11172 || ((!i
.mem_operands
!= !intel_syntax
)
11173 && current_templates
->end
[-1].operand_types
[1]
11174 .bitfield
.baseindex
))
11177 = (const reg_entry
*) str_hash_find (reg_hash
,
11178 di_si
[addr_mode
][op
== es_op
]);
11182 = (const reg_entry
*)str_hash_find (reg_hash
, bx
[addr_mode
]);
11184 if (i
.base_reg
!= expected_reg
11186 || operand_type_check (i
.types
[this_operand
], disp
))
11188 /* The second memory operand must have the same size as
11192 && !((addr_mode
== CODE_64BIT
11193 && i
.base_reg
->reg_type
.bitfield
.qword
)
11194 || (addr_mode
== CODE_32BIT
11195 ? i
.base_reg
->reg_type
.bitfield
.dword
11196 : i
.base_reg
->reg_type
.bitfield
.word
)))
11199 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
11201 intel_syntax
? '[' : '(',
11203 expected_reg
->reg_name
,
11204 intel_syntax
? ']' : ')');
11211 as_bad (_("`%s' is not a valid %s expression"),
11212 operand_string
, kind
);
11217 if (addr_mode
!= CODE_16BIT
)
11219 /* 32-bit/64-bit checks. */
11220 if (i
.disp_encoding
== disp_encoding_16bit
)
11223 as_bad (_("invalid `%s' prefix"),
11224 addr_mode
== CODE_16BIT
? "{disp32}" : "{disp16}");
11229 && ((addr_mode
== CODE_64BIT
11230 ? !i
.base_reg
->reg_type
.bitfield
.qword
11231 : !i
.base_reg
->reg_type
.bitfield
.dword
)
11232 || (i
.index_reg
&& i
.base_reg
->reg_num
== RegIP
)
11233 || i
.base_reg
->reg_num
== RegIZ
))
11235 && !i
.index_reg
->reg_type
.bitfield
.xmmword
11236 && !i
.index_reg
->reg_type
.bitfield
.ymmword
11237 && !i
.index_reg
->reg_type
.bitfield
.zmmword
11238 && ((addr_mode
== CODE_64BIT
11239 ? !i
.index_reg
->reg_type
.bitfield
.qword
11240 : !i
.index_reg
->reg_type
.bitfield
.dword
)
11241 || !i
.index_reg
->reg_type
.bitfield
.baseindex
)))
11244 /* bndmk, bndldx, bndstx and mandatory non-vector SIB have special restrictions. */
11245 if ((t
->opcode_modifier
.opcodeprefix
== PREFIX_0XF3
11246 && t
->opcode_modifier
.opcodespace
== SPACE_0F
11247 && t
->base_opcode
== 0x1b)
11248 || (t
->opcode_modifier
.opcodeprefix
== PREFIX_NONE
11249 && t
->opcode_modifier
.opcodespace
== SPACE_0F
11250 && (t
->base_opcode
& ~1) == 0x1a)
11251 || t
->opcode_modifier
.sib
== SIBMEM
)
11253 /* They cannot use RIP-relative addressing. */
11254 if (i
.base_reg
&& i
.base_reg
->reg_num
== RegIP
)
11256 as_bad (_("`%s' cannot be used here"), operand_string
);
11260 /* bndldx and bndstx ignore their scale factor. */
11261 if (t
->opcode_modifier
.opcodeprefix
== PREFIX_NONE
11262 && t
->opcode_modifier
.opcodespace
== SPACE_0F
11263 && (t
->base_opcode
& ~1) == 0x1a
11264 && i
.log2_scale_factor
)
11265 as_warn (_("register scaling is being ignored here"));
11270 /* 16-bit checks. */
11271 if (i
.disp_encoding
== disp_encoding_32bit
)
11275 && (!i
.base_reg
->reg_type
.bitfield
.word
11276 || !i
.base_reg
->reg_type
.bitfield
.baseindex
))
11278 && (!i
.index_reg
->reg_type
.bitfield
.word
11279 || !i
.index_reg
->reg_type
.bitfield
.baseindex
11281 && i
.base_reg
->reg_num
< 6
11282 && i
.index_reg
->reg_num
>= 6
11283 && i
.log2_scale_factor
== 0))))
11290 /* Handle vector immediates. */
11293 RC_SAE_immediate (const char *imm_start
)
11295 unsigned int match_found
, j
;
11296 const char *pstr
= imm_start
;
11304 for (j
= 0; j
< ARRAY_SIZE (RC_NamesTable
); j
++)
11306 if (!strncmp (pstr
, RC_NamesTable
[j
].name
, RC_NamesTable
[j
].len
))
11308 if (i
.rounding
.type
!= rc_none
)
11310 as_bad (_("duplicated `%s'"), imm_start
);
11314 i
.rounding
.type
= RC_NamesTable
[j
].type
;
11315 i
.rounding
.operand
= this_operand
;
11317 pstr
+= RC_NamesTable
[j
].len
;
11325 if (*pstr
++ != '}')
11327 as_bad (_("Missing '}': '%s'"), imm_start
);
11330 /* RC/SAE immediate string should contain nothing more. */;
11333 as_bad (_("Junk after '}': '%s'"), imm_start
);
11337 exp
= &im_expressions
[i
.imm_operands
++];
11338 i
.op
[this_operand
].imms
= exp
;
11340 exp
->X_op
= O_constant
;
11341 exp
->X_add_number
= 0;
11342 exp
->X_add_symbol
= (symbolS
*) 0;
11343 exp
->X_op_symbol
= (symbolS
*) 0;
11345 i
.types
[this_operand
].bitfield
.imm8
= 1;
11349 /* Only string instructions can have a second memory operand, so
11350 reduce current_templates to just those if it contains any. */
11352 maybe_adjust_templates (void)
11354 const insn_template
*t
;
11356 gas_assert (i
.mem_operands
== 1);
11358 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
11359 if (t
->opcode_modifier
.isstring
)
11362 if (t
< current_templates
->end
)
11364 static templates aux_templates
;
11367 aux_templates
.start
= t
;
11368 for (; t
< current_templates
->end
; ++t
)
11369 if (!t
->opcode_modifier
.isstring
)
11371 aux_templates
.end
= t
;
11373 /* Determine whether to re-check the first memory operand. */
11374 recheck
= (aux_templates
.start
!= current_templates
->start
11375 || t
!= current_templates
->end
);
11377 current_templates
= &aux_templates
;
11381 i
.mem_operands
= 0;
11382 if (i
.memop1_string
!= NULL
11383 && i386_index_check (i
.memop1_string
) == 0)
11385 i
.mem_operands
= 1;
11392 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
11396 i386_att_operand (char *operand_string
)
11398 const reg_entry
*r
;
11400 char *op_string
= operand_string
;
11402 if (is_space_char (*op_string
))
11405 /* We check for an absolute prefix (differentiating,
11406 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
11407 if (*op_string
== ABSOLUTE_PREFIX
)
11410 if (is_space_char (*op_string
))
11412 i
.jumpabsolute
= true;
11415 /* Check if operand is a register. */
11416 if ((r
= parse_register (op_string
, &end_op
)) != NULL
)
11418 i386_operand_type temp
;
11423 /* Check for a segment override by searching for ':' after a
11424 segment register. */
11425 op_string
= end_op
;
11426 if (is_space_char (*op_string
))
11428 if (*op_string
== ':' && r
->reg_type
.bitfield
.class == SReg
)
11430 i
.seg
[i
.mem_operands
] = r
;
11432 /* Skip the ':' and whitespace. */
11434 if (is_space_char (*op_string
))
11437 if (!is_digit_char (*op_string
)
11438 && !is_identifier_char (*op_string
)
11439 && *op_string
!= '('
11440 && *op_string
!= ABSOLUTE_PREFIX
)
11442 as_bad (_("bad memory operand `%s'"), op_string
);
11445 /* Handle case of %es:*foo. */
11446 if (*op_string
== ABSOLUTE_PREFIX
)
11449 if (is_space_char (*op_string
))
11451 i
.jumpabsolute
= true;
11453 goto do_memory_reference
;
11456 /* Handle vector operations. */
11457 if (*op_string
== '{')
11459 op_string
= check_VecOperations (op_string
, NULL
);
11460 if (op_string
== NULL
)
11466 as_bad (_("junk `%s' after register"), op_string
);
11469 temp
= r
->reg_type
;
11470 temp
.bitfield
.baseindex
= 0;
11471 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
11473 i
.types
[this_operand
].bitfield
.unspecified
= 0;
11474 i
.op
[this_operand
].regs
= r
;
11477 else if (*op_string
== REGISTER_PREFIX
)
11479 as_bad (_("bad register name `%s'"), op_string
);
11482 else if (*op_string
== IMMEDIATE_PREFIX
)
11485 if (i
.jumpabsolute
)
11487 as_bad (_("immediate operand illegal with absolute jump"));
11490 if (!i386_immediate (op_string
))
11493 else if (RC_SAE_immediate (operand_string
))
11495 /* If it is a RC or SAE immediate, do nothing. */
11498 else if (is_digit_char (*op_string
)
11499 || is_identifier_char (*op_string
)
11500 || *op_string
== '"'
11501 || *op_string
== '(')
11503 /* This is a memory reference of some sort. */
11506 /* Start and end of displacement string expression (if found). */
11507 char *displacement_string_start
;
11508 char *displacement_string_end
;
11511 do_memory_reference
:
11512 if (i
.mem_operands
== 1 && !maybe_adjust_templates ())
11514 if ((i
.mem_operands
== 1
11515 && !current_templates
->start
->opcode_modifier
.isstring
)
11516 || i
.mem_operands
== 2)
11518 as_bad (_("too many memory references for `%s'"),
11519 current_templates
->start
->name
);
11523 /* Check for base index form. We detect the base index form by
11524 looking for an ')' at the end of the operand, searching
11525 for the '(' matching it, and finding a REGISTER_PREFIX or ','
11527 base_string
= op_string
+ strlen (op_string
);
11529 /* Handle vector operations. */
11530 vop_start
= strchr (op_string
, '{');
11531 if (vop_start
&& vop_start
< base_string
)
11533 if (check_VecOperations (vop_start
, base_string
) == NULL
)
11535 base_string
= vop_start
;
11539 if (is_space_char (*base_string
))
11542 /* If we only have a displacement, set-up for it to be parsed later. */
11543 displacement_string_start
= op_string
;
11544 displacement_string_end
= base_string
+ 1;
11546 if (*base_string
== ')')
11549 unsigned int parens_balanced
= 1;
11550 /* We've already checked that the number of left & right ()'s are
11551 equal, so this loop will not be infinite. */
11555 if (*base_string
== ')')
11557 if (*base_string
== '(')
11560 while (parens_balanced
);
11562 temp_string
= base_string
;
11564 /* Skip past '(' and whitespace. */
11566 if (is_space_char (*base_string
))
11569 if (*base_string
== ','
11570 || ((i
.base_reg
= parse_register (base_string
, &end_op
))
11573 displacement_string_end
= temp_string
;
11575 i
.types
[this_operand
].bitfield
.baseindex
= 1;
11579 if (i
.base_reg
== &bad_reg
)
11581 base_string
= end_op
;
11582 if (is_space_char (*base_string
))
11586 /* There may be an index reg or scale factor here. */
11587 if (*base_string
== ',')
11590 if (is_space_char (*base_string
))
11593 if ((i
.index_reg
= parse_register (base_string
, &end_op
))
11596 if (i
.index_reg
== &bad_reg
)
11598 base_string
= end_op
;
11599 if (is_space_char (*base_string
))
11601 if (*base_string
== ',')
11604 if (is_space_char (*base_string
))
11607 else if (*base_string
!= ')')
11609 as_bad (_("expecting `,' or `)' "
11610 "after index register in `%s'"),
11615 else if (*base_string
== REGISTER_PREFIX
)
11617 end_op
= strchr (base_string
, ',');
11620 as_bad (_("bad register name `%s'"), base_string
);
11624 /* Check for scale factor. */
11625 if (*base_string
!= ')')
11627 char *end_scale
= i386_scale (base_string
);
11632 base_string
= end_scale
;
11633 if (is_space_char (*base_string
))
11635 if (*base_string
!= ')')
11637 as_bad (_("expecting `)' "
11638 "after scale factor in `%s'"),
11643 else if (!i
.index_reg
)
11645 as_bad (_("expecting index register or scale factor "
11646 "after `,'; got '%c'"),
11651 else if (*base_string
!= ')')
11653 as_bad (_("expecting `,' or `)' "
11654 "after base register in `%s'"),
11659 else if (*base_string
== REGISTER_PREFIX
)
11661 end_op
= strchr (base_string
, ',');
11664 as_bad (_("bad register name `%s'"), base_string
);
11669 /* If there's an expression beginning the operand, parse it,
11670 assuming displacement_string_start and
11671 displacement_string_end are meaningful. */
11672 if (displacement_string_start
!= displacement_string_end
)
11674 if (!i386_displacement (displacement_string_start
,
11675 displacement_string_end
))
11679 /* Special case for (%dx) while doing input/output op. */
11681 && i
.base_reg
->reg_type
.bitfield
.instance
== RegD
11682 && i
.base_reg
->reg_type
.bitfield
.word
11683 && i
.index_reg
== 0
11684 && i
.log2_scale_factor
== 0
11685 && i
.seg
[i
.mem_operands
] == 0
11686 && !operand_type_check (i
.types
[this_operand
], disp
))
11688 i
.types
[this_operand
] = i
.base_reg
->reg_type
;
11692 if (i386_index_check (operand_string
) == 0)
11694 i
.flags
[this_operand
] |= Operand_Mem
;
11695 if (i
.mem_operands
== 0)
11696 i
.memop1_string
= xstrdup (operand_string
);
11701 /* It's not a memory operand; argh! */
11702 as_bad (_("invalid char %s beginning operand %d `%s'"),
11703 output_invalid (*op_string
),
11708 return 1; /* Normal return. */
11711 /* Calculate the maximum variable size (i.e., excluding fr_fix)
11712 that an rs_machine_dependent frag may reach. */
11715 i386_frag_max_var (fragS
*frag
)
11717 /* The only relaxable frags are for jumps.
11718 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
11719 gas_assert (frag
->fr_type
== rs_machine_dependent
);
11720 return TYPE_FROM_RELAX_STATE (frag
->fr_subtype
) == UNCOND_JUMP
? 4 : 5;
11723 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11725 elf_symbol_resolved_in_segment_p (symbolS
*fr_symbol
, offsetT fr_var
)
11727 /* STT_GNU_IFUNC symbol must go through PLT. */
11728 if ((symbol_get_bfdsym (fr_symbol
)->flags
11729 & BSF_GNU_INDIRECT_FUNCTION
) != 0)
11732 if (!S_IS_EXTERNAL (fr_symbol
))
11733 /* Symbol may be weak or local. */
11734 return !S_IS_WEAK (fr_symbol
);
11736 /* Global symbols with non-default visibility can't be preempted. */
11737 if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol
)) != STV_DEFAULT
)
11740 if (fr_var
!= NO_RELOC
)
11741 switch ((enum bfd_reloc_code_real
) fr_var
)
11743 case BFD_RELOC_386_PLT32
:
11744 case BFD_RELOC_X86_64_PLT32
:
11745 /* Symbol with PLT relocation may be preempted. */
11751 /* Global symbols with default visibility in a shared library may be
11752 preempted by another definition. */
11757 /* Table 3-2. Macro-Fusible Instructions in Haswell Microarchitecture
11758 Note also work for Skylake and Cascadelake.
11759 ---------------------------------------------------------------------
11760 | JCC | ADD/SUB/CMP | INC/DEC | TEST/AND |
11761 | ------ | ----------- | ------- | -------- |
11763 | Jno | N | N | Y |
11764 | Jc/Jb | Y | N | Y |
11765 | Jae/Jnb | Y | N | Y |
11766 | Je/Jz | Y | Y | Y |
11767 | Jne/Jnz | Y | Y | Y |
11768 | Jna/Jbe | Y | N | Y |
11769 | Ja/Jnbe | Y | N | Y |
11771 | Jns | N | N | Y |
11772 | Jp/Jpe | N | N | Y |
11773 | Jnp/Jpo | N | N | Y |
11774 | Jl/Jnge | Y | Y | Y |
11775 | Jge/Jnl | Y | Y | Y |
11776 | Jle/Jng | Y | Y | Y |
11777 | Jg/Jnle | Y | Y | Y |
11778 --------------------------------------------------------------------- */
11780 i386_macro_fusible_p (enum mf_cmp_kind mf_cmp
, enum mf_jcc_kind mf_jcc
)
11782 if (mf_cmp
== mf_cmp_alu_cmp
)
11783 return ((mf_jcc
>= mf_jcc_jc
&& mf_jcc
<= mf_jcc_jna
)
11784 || mf_jcc
== mf_jcc_jl
|| mf_jcc
== mf_jcc_jle
);
11785 if (mf_cmp
== mf_cmp_incdec
)
11786 return (mf_jcc
== mf_jcc_je
|| mf_jcc
== mf_jcc_jl
11787 || mf_jcc
== mf_jcc_jle
);
11788 if (mf_cmp
== mf_cmp_test_and
)
11793 /* Return the next non-empty frag. */
11796 i386_next_non_empty_frag (fragS
*fragP
)
11798 /* There may be a frag with a ".fill 0" when there is no room in
11799 the current frag for frag_grow in output_insn. */
11800 for (fragP
= fragP
->fr_next
;
11802 && fragP
->fr_type
== rs_fill
11803 && fragP
->fr_fix
== 0);
11804 fragP
= fragP
->fr_next
)
11809 /* Return the next jcc frag after BRANCH_PADDING. */
11812 i386_next_fusible_jcc_frag (fragS
*maybe_cmp_fragP
, fragS
*pad_fragP
)
11814 fragS
*branch_fragP
;
11818 if (pad_fragP
->fr_type
== rs_machine_dependent
11819 && (TYPE_FROM_RELAX_STATE (pad_fragP
->fr_subtype
)
11820 == BRANCH_PADDING
))
11822 branch_fragP
= i386_next_non_empty_frag (pad_fragP
);
11823 if (branch_fragP
->fr_type
!= rs_machine_dependent
)
11825 if (TYPE_FROM_RELAX_STATE (branch_fragP
->fr_subtype
) == COND_JUMP
11826 && i386_macro_fusible_p (maybe_cmp_fragP
->tc_frag_data
.mf_type
,
11827 pad_fragP
->tc_frag_data
.mf_type
))
11828 return branch_fragP
;
11834 /* Classify BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING frags. */
11837 i386_classify_machine_dependent_frag (fragS
*fragP
)
11841 fragS
*branch_fragP
;
11843 unsigned int max_prefix_length
;
11845 if (fragP
->tc_frag_data
.classified
)
11848 /* First scan for BRANCH_PADDING and FUSED_JCC_PADDING. Convert
11849 FUSED_JCC_PADDING and merge BRANCH_PADDING. */
11850 for (next_fragP
= fragP
;
11851 next_fragP
!= NULL
;
11852 next_fragP
= next_fragP
->fr_next
)
11854 next_fragP
->tc_frag_data
.classified
= 1;
11855 if (next_fragP
->fr_type
== rs_machine_dependent
)
11856 switch (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
))
11858 case BRANCH_PADDING
:
11859 /* The BRANCH_PADDING frag must be followed by a branch
11861 branch_fragP
= i386_next_non_empty_frag (next_fragP
);
11862 next_fragP
->tc_frag_data
.u
.branch_fragP
= branch_fragP
;
11864 case FUSED_JCC_PADDING
:
11865 /* Check if this is a fused jcc:
11867 CMP like instruction
11871 cmp_fragP
= i386_next_non_empty_frag (next_fragP
);
11872 pad_fragP
= i386_next_non_empty_frag (cmp_fragP
);
11873 branch_fragP
= i386_next_fusible_jcc_frag (next_fragP
, pad_fragP
);
11876 /* The BRANCH_PADDING frag is merged with the
11877 FUSED_JCC_PADDING frag. */
11878 next_fragP
->tc_frag_data
.u
.branch_fragP
= branch_fragP
;
11879 /* CMP like instruction size. */
11880 next_fragP
->tc_frag_data
.cmp_size
= cmp_fragP
->fr_fix
;
11881 frag_wane (pad_fragP
);
11882 /* Skip to branch_fragP. */
11883 next_fragP
= branch_fragP
;
11885 else if (next_fragP
->tc_frag_data
.max_prefix_length
)
11887 /* Turn FUSED_JCC_PADDING into BRANCH_PREFIX if it isn't
11889 next_fragP
->fr_subtype
11890 = ENCODE_RELAX_STATE (BRANCH_PREFIX
, 0);
11891 next_fragP
->tc_frag_data
.max_bytes
11892 = next_fragP
->tc_frag_data
.max_prefix_length
;
11893 /* This will be updated in the BRANCH_PREFIX scan. */
11894 next_fragP
->tc_frag_data
.max_prefix_length
= 0;
11897 frag_wane (next_fragP
);
11902 /* Stop if there is no BRANCH_PREFIX. */
11903 if (!align_branch_prefix_size
)
11906 /* Scan for BRANCH_PREFIX. */
11907 for (; fragP
!= NULL
; fragP
= fragP
->fr_next
)
11909 if (fragP
->fr_type
!= rs_machine_dependent
11910 || (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
)
11914 /* Count all BRANCH_PREFIX frags before BRANCH_PADDING and
11915 COND_JUMP_PREFIX. */
11916 max_prefix_length
= 0;
11917 for (next_fragP
= fragP
;
11918 next_fragP
!= NULL
;
11919 next_fragP
= next_fragP
->fr_next
)
11921 if (next_fragP
->fr_type
== rs_fill
)
11922 /* Skip rs_fill frags. */
11924 else if (next_fragP
->fr_type
!= rs_machine_dependent
)
11925 /* Stop for all other frags. */
11928 /* rs_machine_dependent frags. */
11929 if (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
11932 /* Count BRANCH_PREFIX frags. */
11933 if (max_prefix_length
>= MAX_FUSED_JCC_PADDING_SIZE
)
11935 max_prefix_length
= MAX_FUSED_JCC_PADDING_SIZE
;
11936 frag_wane (next_fragP
);
11940 += next_fragP
->tc_frag_data
.max_bytes
;
11942 else if ((TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
11944 || (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
11945 == FUSED_JCC_PADDING
))
11947 /* Stop at BRANCH_PADDING and FUSED_JCC_PADDING. */
11948 fragP
->tc_frag_data
.u
.padding_fragP
= next_fragP
;
11952 /* Stop for other rs_machine_dependent frags. */
11956 fragP
->tc_frag_data
.max_prefix_length
= max_prefix_length
;
11958 /* Skip to the next frag. */
11959 fragP
= next_fragP
;
11963 /* Compute padding size for
11966 CMP like instruction
11968 COND_JUMP/UNCOND_JUMP
11973 COND_JUMP/UNCOND_JUMP
11977 i386_branch_padding_size (fragS
*fragP
, offsetT address
)
11979 unsigned int offset
, size
, padding_size
;
11980 fragS
*branch_fragP
= fragP
->tc_frag_data
.u
.branch_fragP
;
11982 /* The start address of the BRANCH_PADDING or FUSED_JCC_PADDING frag. */
11984 address
= fragP
->fr_address
;
11985 address
+= fragP
->fr_fix
;
11987 /* CMP like instrunction size. */
11988 size
= fragP
->tc_frag_data
.cmp_size
;
11990 /* The base size of the branch frag. */
11991 size
+= branch_fragP
->fr_fix
;
11993 /* Add opcode and displacement bytes for the rs_machine_dependent
11995 if (branch_fragP
->fr_type
== rs_machine_dependent
)
11996 size
+= md_relax_table
[branch_fragP
->fr_subtype
].rlx_length
;
11998 /* Check if branch is within boundary and doesn't end at the last
12000 offset
= address
& ((1U << align_branch_power
) - 1);
12001 if ((offset
+ size
) >= (1U << align_branch_power
))
12002 /* Padding needed to avoid crossing boundary. */
12003 padding_size
= (1U << align_branch_power
) - offset
;
12005 /* No padding needed. */
12008 /* The return value may be saved in tc_frag_data.length which is
12010 if (!fits_in_unsigned_byte (padding_size
))
12013 return padding_size
;
12016 /* i386_generic_table_relax_frag()
12018 Handle BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING frags to
12019 grow/shrink padding to align branch frags. Hand others to
12023 i386_generic_table_relax_frag (segT segment
, fragS
*fragP
, long stretch
)
12025 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
12026 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
)
12028 long padding_size
= i386_branch_padding_size (fragP
, 0);
12029 long grow
= padding_size
- fragP
->tc_frag_data
.length
;
12031 /* When the BRANCH_PREFIX frag is used, the computed address
12032 must match the actual address and there should be no padding. */
12033 if (fragP
->tc_frag_data
.padding_address
12034 && (fragP
->tc_frag_data
.padding_address
!= fragP
->fr_address
12038 /* Update the padding size. */
12040 fragP
->tc_frag_data
.length
= padding_size
;
12044 else if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
)
12046 fragS
*padding_fragP
, *next_fragP
;
12047 long padding_size
, left_size
, last_size
;
12049 padding_fragP
= fragP
->tc_frag_data
.u
.padding_fragP
;
12050 if (!padding_fragP
)
12051 /* Use the padding set by the leading BRANCH_PREFIX frag. */
12052 return (fragP
->tc_frag_data
.length
12053 - fragP
->tc_frag_data
.last_length
);
12055 /* Compute the relative address of the padding frag in the very
12056 first time where the BRANCH_PREFIX frag sizes are zero. */
12057 if (!fragP
->tc_frag_data
.padding_address
)
12058 fragP
->tc_frag_data
.padding_address
12059 = padding_fragP
->fr_address
- (fragP
->fr_address
- stretch
);
12061 /* First update the last length from the previous interation. */
12062 left_size
= fragP
->tc_frag_data
.prefix_length
;
12063 for (next_fragP
= fragP
;
12064 next_fragP
!= padding_fragP
;
12065 next_fragP
= next_fragP
->fr_next
)
12066 if (next_fragP
->fr_type
== rs_machine_dependent
12067 && (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
12072 int max
= next_fragP
->tc_frag_data
.max_bytes
;
12076 if (max
> left_size
)
12081 next_fragP
->tc_frag_data
.last_length
= size
;
12085 next_fragP
->tc_frag_data
.last_length
= 0;
12088 /* Check the padding size for the padding frag. */
12089 padding_size
= i386_branch_padding_size
12090 (padding_fragP
, (fragP
->fr_address
12091 + fragP
->tc_frag_data
.padding_address
));
12093 last_size
= fragP
->tc_frag_data
.prefix_length
;
12094 /* Check if there is change from the last interation. */
12095 if (padding_size
== last_size
)
12097 /* Update the expected address of the padding frag. */
12098 padding_fragP
->tc_frag_data
.padding_address
12099 = (fragP
->fr_address
+ padding_size
12100 + fragP
->tc_frag_data
.padding_address
);
12104 if (padding_size
> fragP
->tc_frag_data
.max_prefix_length
)
12106 /* No padding if there is no sufficient room. Clear the
12107 expected address of the padding frag. */
12108 padding_fragP
->tc_frag_data
.padding_address
= 0;
12112 /* Store the expected address of the padding frag. */
12113 padding_fragP
->tc_frag_data
.padding_address
12114 = (fragP
->fr_address
+ padding_size
12115 + fragP
->tc_frag_data
.padding_address
);
12117 fragP
->tc_frag_data
.prefix_length
= padding_size
;
12119 /* Update the length for the current interation. */
12120 left_size
= padding_size
;
12121 for (next_fragP
= fragP
;
12122 next_fragP
!= padding_fragP
;
12123 next_fragP
= next_fragP
->fr_next
)
12124 if (next_fragP
->fr_type
== rs_machine_dependent
12125 && (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
12130 int max
= next_fragP
->tc_frag_data
.max_bytes
;
12134 if (max
> left_size
)
12139 next_fragP
->tc_frag_data
.length
= size
;
12143 next_fragP
->tc_frag_data
.length
= 0;
12146 return (fragP
->tc_frag_data
.length
12147 - fragP
->tc_frag_data
.last_length
);
12149 return relax_frag (segment
, fragP
, stretch
);
12152 /* md_estimate_size_before_relax()
12154 Called just before relax() for rs_machine_dependent frags. The x86
12155 assembler uses these frags to handle variable size jump
12158 Any symbol that is now undefined will not become defined.
12159 Return the correct fr_subtype in the frag.
12160 Return the initial "guess for variable size of frag" to caller.
12161 The guess is actually the growth beyond the fixed part. Whatever
12162 we do to grow the fixed or variable part contributes to our
12166 md_estimate_size_before_relax (fragS
*fragP
, segT segment
)
12168 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
12169 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
12170 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
)
12172 i386_classify_machine_dependent_frag (fragP
);
12173 return fragP
->tc_frag_data
.length
;
12176 /* We've already got fragP->fr_subtype right; all we have to do is
12177 check for un-relaxable symbols. On an ELF system, we can't relax
12178 an externally visible symbol, because it may be overridden by a
12180 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
12181 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12183 && !elf_symbol_resolved_in_segment_p (fragP
->fr_symbol
,
12186 #if defined (OBJ_COFF) && defined (TE_PE)
12187 || (OUTPUT_FLAVOR
== bfd_target_coff_flavour
12188 && S_IS_WEAK (fragP
->fr_symbol
))
12192 /* Symbol is undefined in this segment, or we need to keep a
12193 reloc so that weak symbols can be overridden. */
12194 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
12195 enum bfd_reloc_code_real reloc_type
;
12196 unsigned char *opcode
;
12200 if (fragP
->fr_var
!= NO_RELOC
)
12201 reloc_type
= (enum bfd_reloc_code_real
) fragP
->fr_var
;
12202 else if (size
== 2)
12203 reloc_type
= BFD_RELOC_16_PCREL
;
12204 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12205 else if (need_plt32_p (fragP
->fr_symbol
))
12206 reloc_type
= BFD_RELOC_X86_64_PLT32
;
12209 reloc_type
= BFD_RELOC_32_PCREL
;
12211 old_fr_fix
= fragP
->fr_fix
;
12212 opcode
= (unsigned char *) fragP
->fr_opcode
;
12214 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
12217 /* Make jmp (0xeb) a (d)word displacement jump. */
12219 fragP
->fr_fix
+= size
;
12220 fixP
= fix_new (fragP
, old_fr_fix
, size
,
12222 fragP
->fr_offset
, 1,
12228 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
12230 /* Negate the condition, and branch past an
12231 unconditional jump. */
12234 /* Insert an unconditional jump. */
12236 /* We added two extra opcode bytes, and have a two byte
12238 fragP
->fr_fix
+= 2 + 2;
12239 fix_new (fragP
, old_fr_fix
+ 2, 2,
12241 fragP
->fr_offset
, 1,
12245 /* Fall through. */
12248 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
12250 fragP
->fr_fix
+= 1;
12251 fixP
= fix_new (fragP
, old_fr_fix
, 1,
12253 fragP
->fr_offset
, 1,
12254 BFD_RELOC_8_PCREL
);
12255 fixP
->fx_signed
= 1;
12259 /* This changes the byte-displacement jump 0x7N
12260 to the (d)word-displacement jump 0x0f,0x8N. */
12261 opcode
[1] = opcode
[0] + 0x10;
12262 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
12263 /* We've added an opcode byte. */
12264 fragP
->fr_fix
+= 1 + size
;
12265 fixP
= fix_new (fragP
, old_fr_fix
+ 1, size
,
12267 fragP
->fr_offset
, 1,
12272 BAD_CASE (fragP
->fr_subtype
);
12276 /* All jumps handled here are signed, but don't unconditionally use a
12277 signed limit check for 32 and 16 bit jumps as we want to allow wrap
12278 around at 4G (outside of 64-bit mode) and 64k. */
12279 if (size
== 4 && flag_code
== CODE_64BIT
)
12280 fixP
->fx_signed
= 1;
12283 return fragP
->fr_fix
- old_fr_fix
;
12286 /* Guess size depending on current relax state. Initially the relax
12287 state will correspond to a short jump and we return 1, because
12288 the variable part of the frag (the branch offset) is one byte
12289 long. However, we can relax a section more than once and in that
12290 case we must either set fr_subtype back to the unrelaxed state,
12291 or return the value for the appropriate branch. */
12292 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
12295 /* Called after relax() is finished.
12297 In: Address of frag.
12298 fr_type == rs_machine_dependent.
12299 fr_subtype is what the address relaxed to.
12301 Out: Any fixSs and constants are set up.
12302 Caller will turn frag into a ".space 0". */
12305 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec ATTRIBUTE_UNUSED
,
12308 unsigned char *opcode
;
12309 unsigned char *where_to_put_displacement
= NULL
;
12310 offsetT target_address
;
12311 offsetT opcode_address
;
12312 unsigned int extension
= 0;
12313 offsetT displacement_from_opcode_start
;
12315 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
12316 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
12317 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
)
12319 /* Generate nop padding. */
12320 unsigned int size
= fragP
->tc_frag_data
.length
;
12323 if (size
> fragP
->tc_frag_data
.max_bytes
)
12329 const char *branch
= "branch";
12330 const char *prefix
= "";
12331 fragS
*padding_fragP
;
12332 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
)
12335 padding_fragP
= fragP
->tc_frag_data
.u
.padding_fragP
;
12336 switch (fragP
->tc_frag_data
.default_prefix
)
12341 case CS_PREFIX_OPCODE
:
12344 case DS_PREFIX_OPCODE
:
12347 case ES_PREFIX_OPCODE
:
12350 case FS_PREFIX_OPCODE
:
12353 case GS_PREFIX_OPCODE
:
12356 case SS_PREFIX_OPCODE
:
12361 msg
= _("%s:%u: add %d%s at 0x%llx to align "
12362 "%s within %d-byte boundary\n");
12364 msg
= _("%s:%u: add additional %d%s at 0x%llx to "
12365 "align %s within %d-byte boundary\n");
12369 padding_fragP
= fragP
;
12370 msg
= _("%s:%u: add %d%s-byte nop at 0x%llx to align "
12371 "%s within %d-byte boundary\n");
12375 switch (padding_fragP
->tc_frag_data
.branch_type
)
12377 case align_branch_jcc
:
12380 case align_branch_fused
:
12381 branch
= "fused jcc";
12383 case align_branch_jmp
:
12386 case align_branch_call
:
12389 case align_branch_indirect
:
12390 branch
= "indiret branch";
12392 case align_branch_ret
:
12399 fprintf (stdout
, msg
,
12400 fragP
->fr_file
, fragP
->fr_line
, size
, prefix
,
12401 (long long) fragP
->fr_address
, branch
,
12402 1 << align_branch_power
);
12404 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
)
12405 memset (fragP
->fr_opcode
,
12406 fragP
->tc_frag_data
.default_prefix
, size
);
12408 i386_generate_nops (fragP
, (char *) fragP
->fr_opcode
,
12410 fragP
->fr_fix
+= size
;
12415 opcode
= (unsigned char *) fragP
->fr_opcode
;
12417 /* Address we want to reach in file space. */
12418 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
12420 /* Address opcode resides at in file space. */
12421 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
12423 /* Displacement from opcode start to fill into instruction. */
12424 displacement_from_opcode_start
= target_address
- opcode_address
;
12426 if ((fragP
->fr_subtype
& BIG
) == 0)
12428 /* Don't have to change opcode. */
12429 extension
= 1; /* 1 opcode + 1 displacement */
12430 where_to_put_displacement
= &opcode
[1];
12434 if (no_cond_jump_promotion
12435 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
12436 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
12437 _("long jump required"));
12439 switch (fragP
->fr_subtype
)
12441 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
12442 extension
= 4; /* 1 opcode + 4 displacement */
12444 where_to_put_displacement
= &opcode
[1];
12447 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
12448 extension
= 2; /* 1 opcode + 2 displacement */
12450 where_to_put_displacement
= &opcode
[1];
12453 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
12454 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
12455 extension
= 5; /* 2 opcode + 4 displacement */
12456 opcode
[1] = opcode
[0] + 0x10;
12457 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
12458 where_to_put_displacement
= &opcode
[2];
12461 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
12462 extension
= 3; /* 2 opcode + 2 displacement */
12463 opcode
[1] = opcode
[0] + 0x10;
12464 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
12465 where_to_put_displacement
= &opcode
[2];
12468 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
12473 where_to_put_displacement
= &opcode
[3];
12477 BAD_CASE (fragP
->fr_subtype
);
12482 /* If size if less then four we are sure that the operand fits,
12483 but if it's 4, then it could be that the displacement is larger
12485 if (DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
) == 4
12487 && ((addressT
) (displacement_from_opcode_start
- extension
12488 + ((addressT
) 1 << 31))
12489 > (((addressT
) 2 << 31) - 1)))
12491 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
12492 _("jump target out of range"));
12493 /* Make us emit 0. */
12494 displacement_from_opcode_start
= extension
;
12496 /* Now put displacement after opcode. */
12497 md_number_to_chars ((char *) where_to_put_displacement
,
12498 (valueT
) (displacement_from_opcode_start
- extension
),
12499 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
12500 fragP
->fr_fix
+= extension
;
12503 /* Apply a fixup (fixP) to segment data, once it has been determined
12504 by our caller that we have all the info we need to fix it up.
12506 Parameter valP is the pointer to the value of the bits.
12508 On the 386, immediates, displacements, and data pointers are all in
12509 the same (little-endian) format, so we don't need to care about which
12510 we are handling. */
12513 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
12515 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
12516 valueT value
= *valP
;
12518 #if !defined (TE_Mach)
12519 if (fixP
->fx_pcrel
)
12521 switch (fixP
->fx_r_type
)
12527 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
12530 case BFD_RELOC_X86_64_32S
:
12531 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
12534 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
12537 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
12542 if (fixP
->fx_addsy
!= NULL
12543 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
12544 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
12545 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
12546 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
12547 && !use_rela_relocations
)
12549 /* This is a hack. There should be a better way to handle this.
12550 This covers for the fact that bfd_install_relocation will
12551 subtract the current location (for partial_inplace, PC relative
12552 relocations); see more below. */
12556 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
12559 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
12561 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12564 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
12566 if ((sym_seg
== seg
12567 || (symbol_section_p (fixP
->fx_addsy
)
12568 && sym_seg
!= absolute_section
))
12569 && !generic_force_reloc (fixP
))
12571 /* Yes, we add the values in twice. This is because
12572 bfd_install_relocation subtracts them out again. I think
12573 bfd_install_relocation is broken, but I don't dare change
12575 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
12579 #if defined (OBJ_COFF) && defined (TE_PE)
12580 /* For some reason, the PE format does not store a
12581 section address offset for a PC relative symbol. */
12582 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
12583 || S_IS_WEAK (fixP
->fx_addsy
))
12584 value
+= md_pcrel_from (fixP
);
12587 #if defined (OBJ_COFF) && defined (TE_PE)
12588 if (fixP
->fx_addsy
!= NULL
12589 && S_IS_WEAK (fixP
->fx_addsy
)
12590 /* PR 16858: Do not modify weak function references. */
12591 && ! fixP
->fx_pcrel
)
12593 #if !defined (TE_PEP)
12594 /* For x86 PE weak function symbols are neither PC-relative
12595 nor do they set S_IS_FUNCTION. So the only reliable way
12596 to detect them is to check the flags of their containing
12598 if (S_GET_SEGMENT (fixP
->fx_addsy
) != NULL
12599 && S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_CODE
)
12603 value
-= S_GET_VALUE (fixP
->fx_addsy
);
12607 /* Fix a few things - the dynamic linker expects certain values here,
12608 and we must not disappoint it. */
12609 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12610 if (IS_ELF
&& fixP
->fx_addsy
)
12611 switch (fixP
->fx_r_type
)
12613 case BFD_RELOC_386_PLT32
:
12614 case BFD_RELOC_X86_64_PLT32
:
12615 /* Make the jump instruction point to the address of the operand.
12616 At runtime we merely add the offset to the actual PLT entry.
12617 NB: Subtract the offset size only for jump instructions. */
12618 if (fixP
->fx_pcrel
)
12622 case BFD_RELOC_386_TLS_GD
:
12623 case BFD_RELOC_386_TLS_LDM
:
12624 case BFD_RELOC_386_TLS_IE_32
:
12625 case BFD_RELOC_386_TLS_IE
:
12626 case BFD_RELOC_386_TLS_GOTIE
:
12627 case BFD_RELOC_386_TLS_GOTDESC
:
12628 case BFD_RELOC_X86_64_TLSGD
:
12629 case BFD_RELOC_X86_64_TLSLD
:
12630 case BFD_RELOC_X86_64_GOTTPOFF
:
12631 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
12632 value
= 0; /* Fully resolved at runtime. No addend. */
12634 case BFD_RELOC_386_TLS_LE
:
12635 case BFD_RELOC_386_TLS_LDO_32
:
12636 case BFD_RELOC_386_TLS_LE_32
:
12637 case BFD_RELOC_X86_64_DTPOFF32
:
12638 case BFD_RELOC_X86_64_DTPOFF64
:
12639 case BFD_RELOC_X86_64_TPOFF32
:
12640 case BFD_RELOC_X86_64_TPOFF64
:
12641 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
12644 case BFD_RELOC_386_TLS_DESC_CALL
:
12645 case BFD_RELOC_X86_64_TLSDESC_CALL
:
12646 value
= 0; /* Fully resolved at runtime. No addend. */
12647 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
12651 case BFD_RELOC_VTABLE_INHERIT
:
12652 case BFD_RELOC_VTABLE_ENTRY
:
12659 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
12661 /* If not 64bit, massage value, to account for wraparound when !BFD64. */
12663 value
= extend_to_32bit_address (value
);
12666 #endif /* !defined (TE_Mach) */
12668 /* Are we finished with this relocation now? */
12669 if (fixP
->fx_addsy
== NULL
)
12672 switch (fixP
->fx_r_type
)
12674 case BFD_RELOC_X86_64_32S
:
12675 fixP
->fx_signed
= 1;
12682 #if defined (OBJ_COFF) && defined (TE_PE)
12683 else if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
12686 /* Remember value for tc_gen_reloc. */
12687 fixP
->fx_addnumber
= value
;
12688 /* Clear out the frag for now. */
12692 else if (use_rela_relocations
)
12694 fixP
->fx_no_overflow
= 1;
12695 /* Remember value for tc_gen_reloc. */
12696 fixP
->fx_addnumber
= value
;
12700 md_number_to_chars (p
, value
, fixP
->fx_size
);
12704 md_atof (int type
, char *litP
, int *sizeP
)
12706 /* This outputs the LITTLENUMs in REVERSE order;
12707 in accord with the bigendian 386. */
12708 return ieee_md_atof (type
, litP
, sizeP
, false);
12711 static char output_invalid_buf
[sizeof (unsigned char) * 2 + 6];
12714 output_invalid (int c
)
12717 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
12720 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
12721 "(0x%x)", (unsigned char) c
);
12722 return output_invalid_buf
;
12725 /* Verify that @r can be used in the current context. */
12727 static bool check_register (const reg_entry
*r
)
12729 if (allow_pseudo_reg
)
12732 if (operand_type_all_zero (&r
->reg_type
))
12735 if ((r
->reg_type
.bitfield
.dword
12736 || (r
->reg_type
.bitfield
.class == SReg
&& r
->reg_num
> 3)
12737 || r
->reg_type
.bitfield
.class == RegCR
12738 || r
->reg_type
.bitfield
.class == RegDR
)
12739 && !cpu_arch_flags
.bitfield
.cpui386
)
12742 if (r
->reg_type
.bitfield
.class == RegTR
12743 && (flag_code
== CODE_64BIT
12744 || !cpu_arch_flags
.bitfield
.cpui386
12745 || cpu_arch_isa_flags
.bitfield
.cpui586
12746 || cpu_arch_isa_flags
.bitfield
.cpui686
))
12749 if (r
->reg_type
.bitfield
.class == RegMMX
&& !cpu_arch_flags
.bitfield
.cpummx
)
12752 if (!cpu_arch_flags
.bitfield
.cpuavx512f
)
12754 if (r
->reg_type
.bitfield
.zmmword
12755 || r
->reg_type
.bitfield
.class == RegMask
)
12758 if (!cpu_arch_flags
.bitfield
.cpuavx
)
12760 if (r
->reg_type
.bitfield
.ymmword
)
12763 if (!cpu_arch_flags
.bitfield
.cpusse
&& r
->reg_type
.bitfield
.xmmword
)
12768 if (r
->reg_type
.bitfield
.tmmword
12769 && (!cpu_arch_flags
.bitfield
.cpuamx_tile
12770 || flag_code
!= CODE_64BIT
))
12773 if (r
->reg_type
.bitfield
.class == RegBND
&& !cpu_arch_flags
.bitfield
.cpumpx
)
12776 /* Don't allow fake index register unless allow_index_reg isn't 0. */
12777 if (!allow_index_reg
&& r
->reg_num
== RegIZ
)
12780 /* Upper 16 vector registers are only available with VREX in 64bit
12781 mode, and require EVEX encoding. */
12782 if (r
->reg_flags
& RegVRex
)
12784 if (!cpu_arch_flags
.bitfield
.cpuavx512f
12785 || flag_code
!= CODE_64BIT
)
12788 if (i
.vec_encoding
== vex_encoding_default
)
12789 i
.vec_encoding
= vex_encoding_evex
;
12790 else if (i
.vec_encoding
!= vex_encoding_evex
)
12791 i
.vec_encoding
= vex_encoding_error
;
12794 if (((r
->reg_flags
& (RegRex64
| RegRex
)) || r
->reg_type
.bitfield
.qword
)
12795 && (!cpu_arch_flags
.bitfield
.cpulm
|| r
->reg_type
.bitfield
.class != RegCR
)
12796 && flag_code
!= CODE_64BIT
)
12799 if (r
->reg_type
.bitfield
.class == SReg
&& r
->reg_num
== RegFlat
12806 /* REG_STRING starts *before* REGISTER_PREFIX. */
12808 static const reg_entry
*
12809 parse_real_register (char *reg_string
, char **end_op
)
12811 char *s
= reg_string
;
12813 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
12814 const reg_entry
*r
;
12816 /* Skip possible REGISTER_PREFIX and possible whitespace. */
12817 if (*s
== REGISTER_PREFIX
)
12820 if (is_space_char (*s
))
12823 p
= reg_name_given
;
12824 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
12826 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
12827 return (const reg_entry
*) NULL
;
12831 /* For naked regs, make sure that we are not dealing with an identifier.
12832 This prevents confusing an identifier like `eax_var' with register
12834 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
12835 return (const reg_entry
*) NULL
;
12839 r
= (const reg_entry
*) str_hash_find (reg_hash
, reg_name_given
);
12841 /* Handle floating point regs, allowing spaces in the (i) part. */
12844 if (!cpu_arch_flags
.bitfield
.cpu8087
12845 && !cpu_arch_flags
.bitfield
.cpu287
12846 && !cpu_arch_flags
.bitfield
.cpu387
12847 && !allow_pseudo_reg
)
12848 return (const reg_entry
*) NULL
;
12850 if (is_space_char (*s
))
12855 if (is_space_char (*s
))
12857 if (*s
>= '0' && *s
<= '7')
12859 int fpr
= *s
- '0';
12861 if (is_space_char (*s
))
12866 know (r
[fpr
].reg_num
== fpr
);
12870 /* We have "%st(" then garbage. */
12871 return (const reg_entry
*) NULL
;
12875 return r
&& check_register (r
) ? r
: NULL
;
12878 /* REG_STRING starts *before* REGISTER_PREFIX. */
12880 static const reg_entry
*
12881 parse_register (char *reg_string
, char **end_op
)
12883 const reg_entry
*r
;
12885 if (*reg_string
== REGISTER_PREFIX
|| allow_naked_reg
)
12886 r
= parse_real_register (reg_string
, end_op
);
12891 char *save
= input_line_pointer
;
12895 input_line_pointer
= reg_string
;
12896 c
= get_symbol_name (®_string
);
12897 symbolP
= symbol_find (reg_string
);
12898 if (symbolP
&& S_GET_SEGMENT (symbolP
) == reg_section
)
12900 const expressionS
*e
= symbol_get_value_expression (symbolP
);
12902 know (e
->X_op
== O_register
);
12903 know (e
->X_add_number
>= 0
12904 && (valueT
) e
->X_add_number
< i386_regtab_size
);
12905 r
= i386_regtab
+ e
->X_add_number
;
12906 if (!check_register (r
))
12908 as_bad (_("register '%s%s' cannot be used here"),
12909 register_prefix
, r
->reg_name
);
12912 *end_op
= input_line_pointer
;
12914 *input_line_pointer
= c
;
12915 input_line_pointer
= save
;
12921 i386_parse_name (char *name
, expressionS
*e
, char *nextcharP
)
12923 const reg_entry
*r
;
12924 char *end
= input_line_pointer
;
12927 r
= parse_register (name
, &input_line_pointer
);
12928 if (r
&& end
<= input_line_pointer
)
12930 *nextcharP
= *input_line_pointer
;
12931 *input_line_pointer
= 0;
12934 e
->X_op
= O_register
;
12935 e
->X_add_number
= r
- i386_regtab
;
12938 e
->X_op
= O_illegal
;
12941 input_line_pointer
= end
;
12943 return intel_syntax
? i386_intel_parse_name (name
, e
) : 0;
12947 md_operand (expressionS
*e
)
12950 const reg_entry
*r
;
12952 switch (*input_line_pointer
)
12954 case REGISTER_PREFIX
:
12955 r
= parse_real_register (input_line_pointer
, &end
);
12958 e
->X_op
= O_register
;
12959 e
->X_add_number
= r
- i386_regtab
;
12960 input_line_pointer
= end
;
12965 gas_assert (intel_syntax
);
12966 end
= input_line_pointer
++;
12968 if (*input_line_pointer
== ']')
12970 ++input_line_pointer
;
12971 e
->X_op_symbol
= make_expr_symbol (e
);
12972 e
->X_add_symbol
= NULL
;
12973 e
->X_add_number
= 0;
12978 e
->X_op
= O_absent
;
12979 input_line_pointer
= end
;
12986 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12987 const char *md_shortopts
= "kVQ:sqnO::";
12989 const char *md_shortopts
= "qnO::";
12992 #define OPTION_32 (OPTION_MD_BASE + 0)
12993 #define OPTION_64 (OPTION_MD_BASE + 1)
12994 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
12995 #define OPTION_MARCH (OPTION_MD_BASE + 3)
12996 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
12997 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
12998 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
12999 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
13000 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
13001 #define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 9)
13002 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
13003 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
13004 #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
13005 #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
13006 #define OPTION_X32 (OPTION_MD_BASE + 14)
13007 #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
13008 #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
13009 #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
13010 #define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
13011 #define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
13012 #define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
13013 #define OPTION_MSHARED (OPTION_MD_BASE + 21)
13014 #define OPTION_MAMD64 (OPTION_MD_BASE + 22)
13015 #define OPTION_MINTEL64 (OPTION_MD_BASE + 23)
13016 #define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24)
13017 #define OPTION_X86_USED_NOTE (OPTION_MD_BASE + 25)
13018 #define OPTION_MVEXWIG (OPTION_MD_BASE + 26)
13019 #define OPTION_MALIGN_BRANCH_BOUNDARY (OPTION_MD_BASE + 27)
13020 #define OPTION_MALIGN_BRANCH_PREFIX_SIZE (OPTION_MD_BASE + 28)
13021 #define OPTION_MALIGN_BRANCH (OPTION_MD_BASE + 29)
13022 #define OPTION_MBRANCHES_WITH_32B_BOUNDARIES (OPTION_MD_BASE + 30)
13023 #define OPTION_MLFENCE_AFTER_LOAD (OPTION_MD_BASE + 31)
13024 #define OPTION_MLFENCE_BEFORE_INDIRECT_BRANCH (OPTION_MD_BASE + 32)
13025 #define OPTION_MLFENCE_BEFORE_RET (OPTION_MD_BASE + 33)
13027 struct option md_longopts
[] =
13029 {"32", no_argument
, NULL
, OPTION_32
},
13030 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
13031 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
13032 {"64", no_argument
, NULL
, OPTION_64
},
13034 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13035 {"x32", no_argument
, NULL
, OPTION_X32
},
13036 {"mshared", no_argument
, NULL
, OPTION_MSHARED
},
13037 {"mx86-used-note", required_argument
, NULL
, OPTION_X86_USED_NOTE
},
13039 {"divide", no_argument
, NULL
, OPTION_DIVIDE
},
13040 {"march", required_argument
, NULL
, OPTION_MARCH
},
13041 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
13042 {"mmnemonic", required_argument
, NULL
, OPTION_MMNEMONIC
},
13043 {"msyntax", required_argument
, NULL
, OPTION_MSYNTAX
},
13044 {"mindex-reg", no_argument
, NULL
, OPTION_MINDEX_REG
},
13045 {"mnaked-reg", no_argument
, NULL
, OPTION_MNAKED_REG
},
13046 {"msse2avx", no_argument
, NULL
, OPTION_MSSE2AVX
},
13047 {"msse-check", required_argument
, NULL
, OPTION_MSSE_CHECK
},
13048 {"moperand-check", required_argument
, NULL
, OPTION_MOPERAND_CHECK
},
13049 {"mavxscalar", required_argument
, NULL
, OPTION_MAVXSCALAR
},
13050 {"mvexwig", required_argument
, NULL
, OPTION_MVEXWIG
},
13051 {"madd-bnd-prefix", no_argument
, NULL
, OPTION_MADD_BND_PREFIX
},
13052 {"mevexlig", required_argument
, NULL
, OPTION_MEVEXLIG
},
13053 {"mevexwig", required_argument
, NULL
, OPTION_MEVEXWIG
},
13054 # if defined (TE_PE) || defined (TE_PEP)
13055 {"mbig-obj", no_argument
, NULL
, OPTION_MBIG_OBJ
},
13057 {"momit-lock-prefix", required_argument
, NULL
, OPTION_MOMIT_LOCK_PREFIX
},
13058 {"mfence-as-lock-add", required_argument
, NULL
, OPTION_MFENCE_AS_LOCK_ADD
},
13059 {"mrelax-relocations", required_argument
, NULL
, OPTION_MRELAX_RELOCATIONS
},
13060 {"mevexrcig", required_argument
, NULL
, OPTION_MEVEXRCIG
},
13061 {"malign-branch-boundary", required_argument
, NULL
, OPTION_MALIGN_BRANCH_BOUNDARY
},
13062 {"malign-branch-prefix-size", required_argument
, NULL
, OPTION_MALIGN_BRANCH_PREFIX_SIZE
},
13063 {"malign-branch", required_argument
, NULL
, OPTION_MALIGN_BRANCH
},
13064 {"mbranches-within-32B-boundaries", no_argument
, NULL
, OPTION_MBRANCHES_WITH_32B_BOUNDARIES
},
13065 {"mlfence-after-load", required_argument
, NULL
, OPTION_MLFENCE_AFTER_LOAD
},
13066 {"mlfence-before-indirect-branch", required_argument
, NULL
,
13067 OPTION_MLFENCE_BEFORE_INDIRECT_BRANCH
},
13068 {"mlfence-before-ret", required_argument
, NULL
, OPTION_MLFENCE_BEFORE_RET
},
13069 {"mamd64", no_argument
, NULL
, OPTION_MAMD64
},
13070 {"mintel64", no_argument
, NULL
, OPTION_MINTEL64
},
13071 {NULL
, no_argument
, NULL
, 0}
13073 size_t md_longopts_size
= sizeof (md_longopts
);
13076 md_parse_option (int c
, const char *arg
)
13079 char *arch
, *next
, *saved
, *type
;
13084 optimize_align_code
= 0;
13088 quiet_warnings
= 1;
13091 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13092 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
13093 should be emitted or not. FIXME: Not implemented. */
13095 if ((arg
[0] != 'y' && arg
[0] != 'n') || arg
[1])
13099 /* -V: SVR4 argument to print version ID. */
13101 print_version_id ();
13104 /* -k: Ignore for FreeBSD compatibility. */
13109 /* -s: On i386 Solaris, this tells the native assembler to use
13110 .stab instead of .stab.excl. We always use .stab anyhow. */
13113 case OPTION_MSHARED
:
13117 case OPTION_X86_USED_NOTE
:
13118 if (strcasecmp (arg
, "yes") == 0)
13120 else if (strcasecmp (arg
, "no") == 0)
13123 as_fatal (_("invalid -mx86-used-note= option: `%s'"), arg
);
13128 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
13129 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
13132 const char **list
, **l
;
13134 list
= bfd_target_list ();
13135 for (l
= list
; *l
!= NULL
; l
++)
13136 if (startswith (*l
, "elf64-x86-64")
13137 || strcmp (*l
, "coff-x86-64") == 0
13138 || strcmp (*l
, "pe-x86-64") == 0
13139 || strcmp (*l
, "pei-x86-64") == 0
13140 || strcmp (*l
, "mach-o-x86-64") == 0)
13142 default_arch
= "x86_64";
13146 as_fatal (_("no compiled in support for x86_64"));
13152 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13156 const char **list
, **l
;
13158 list
= bfd_target_list ();
13159 for (l
= list
; *l
!= NULL
; l
++)
13160 if (startswith (*l
, "elf32-x86-64"))
13162 default_arch
= "x86_64:32";
13166 as_fatal (_("no compiled in support for 32bit x86_64"));
13170 as_fatal (_("32bit x86_64 is only supported for ELF"));
13175 default_arch
= "i386";
13178 case OPTION_DIVIDE
:
13179 #ifdef SVR4_COMMENT_CHARS
13184 n
= XNEWVEC (char, strlen (i386_comment_chars
) + 1);
13186 for (s
= i386_comment_chars
; *s
!= '\0'; s
++)
13190 i386_comment_chars
= n
;
13196 saved
= xstrdup (arg
);
13198 /* Allow -march=+nosse. */
13204 as_fatal (_("invalid -march= option: `%s'"), arg
);
13205 next
= strchr (arch
, '+');
13208 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
13210 if (strcmp (arch
, cpu_arch
[j
].name
) == 0)
13213 if (! cpu_arch
[j
].flags
.bitfield
.cpui386
)
13216 cpu_arch_name
= cpu_arch
[j
].name
;
13217 cpu_sub_arch_name
= NULL
;
13218 cpu_arch_flags
= cpu_arch
[j
].flags
;
13219 cpu_arch_isa
= cpu_arch
[j
].type
;
13220 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
13221 if (!cpu_arch_tune_set
)
13223 cpu_arch_tune
= cpu_arch_isa
;
13224 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
13228 else if (*cpu_arch
[j
].name
== '.'
13229 && strcmp (arch
, cpu_arch
[j
].name
+ 1) == 0)
13231 /* ISA extension. */
13232 i386_cpu_flags flags
;
13234 flags
= cpu_flags_or (cpu_arch_flags
,
13235 cpu_arch
[j
].flags
);
13237 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
13239 if (cpu_sub_arch_name
)
13241 char *name
= cpu_sub_arch_name
;
13242 cpu_sub_arch_name
= concat (name
,
13244 (const char *) NULL
);
13248 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
13249 cpu_arch_flags
= flags
;
13250 cpu_arch_isa_flags
= flags
;
13254 = cpu_flags_or (cpu_arch_isa_flags
,
13255 cpu_arch
[j
].flags
);
13260 if (j
>= ARRAY_SIZE (cpu_arch
))
13262 /* Disable an ISA extension. */
13263 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
13264 if (strcmp (arch
, cpu_noarch
[j
].name
) == 0)
13266 i386_cpu_flags flags
;
13268 flags
= cpu_flags_and_not (cpu_arch_flags
,
13269 cpu_noarch
[j
].flags
);
13270 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
13272 if (cpu_sub_arch_name
)
13274 char *name
= cpu_sub_arch_name
;
13275 cpu_sub_arch_name
= concat (arch
,
13276 (const char *) NULL
);
13280 cpu_sub_arch_name
= xstrdup (arch
);
13281 cpu_arch_flags
= flags
;
13282 cpu_arch_isa_flags
= flags
;
13287 if (j
>= ARRAY_SIZE (cpu_noarch
))
13288 j
= ARRAY_SIZE (cpu_arch
);
13291 if (j
>= ARRAY_SIZE (cpu_arch
))
13292 as_fatal (_("invalid -march= option: `%s'"), arg
);
13296 while (next
!= NULL
);
13302 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
13303 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
13305 if (strcmp (arg
, cpu_arch
[j
].name
) == 0)
13307 cpu_arch_tune_set
= 1;
13308 cpu_arch_tune
= cpu_arch
[j
].type
;
13309 cpu_arch_tune_flags
= cpu_arch
[j
].flags
;
13313 if (j
>= ARRAY_SIZE (cpu_arch
))
13314 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
13317 case OPTION_MMNEMONIC
:
13318 if (strcasecmp (arg
, "att") == 0)
13319 intel_mnemonic
= 0;
13320 else if (strcasecmp (arg
, "intel") == 0)
13321 intel_mnemonic
= 1;
13323 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg
);
13326 case OPTION_MSYNTAX
:
13327 if (strcasecmp (arg
, "att") == 0)
13329 else if (strcasecmp (arg
, "intel") == 0)
13332 as_fatal (_("invalid -msyntax= option: `%s'"), arg
);
13335 case OPTION_MINDEX_REG
:
13336 allow_index_reg
= 1;
13339 case OPTION_MNAKED_REG
:
13340 allow_naked_reg
= 1;
13343 case OPTION_MSSE2AVX
:
13347 case OPTION_MSSE_CHECK
:
13348 if (strcasecmp (arg
, "error") == 0)
13349 sse_check
= check_error
;
13350 else if (strcasecmp (arg
, "warning") == 0)
13351 sse_check
= check_warning
;
13352 else if (strcasecmp (arg
, "none") == 0)
13353 sse_check
= check_none
;
13355 as_fatal (_("invalid -msse-check= option: `%s'"), arg
);
13358 case OPTION_MOPERAND_CHECK
:
13359 if (strcasecmp (arg
, "error") == 0)
13360 operand_check
= check_error
;
13361 else if (strcasecmp (arg
, "warning") == 0)
13362 operand_check
= check_warning
;
13363 else if (strcasecmp (arg
, "none") == 0)
13364 operand_check
= check_none
;
13366 as_fatal (_("invalid -moperand-check= option: `%s'"), arg
);
13369 case OPTION_MAVXSCALAR
:
13370 if (strcasecmp (arg
, "128") == 0)
13371 avxscalar
= vex128
;
13372 else if (strcasecmp (arg
, "256") == 0)
13373 avxscalar
= vex256
;
13375 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg
);
13378 case OPTION_MVEXWIG
:
13379 if (strcmp (arg
, "0") == 0)
13381 else if (strcmp (arg
, "1") == 0)
13384 as_fatal (_("invalid -mvexwig= option: `%s'"), arg
);
13387 case OPTION_MADD_BND_PREFIX
:
13388 add_bnd_prefix
= 1;
13391 case OPTION_MEVEXLIG
:
13392 if (strcmp (arg
, "128") == 0)
13393 evexlig
= evexl128
;
13394 else if (strcmp (arg
, "256") == 0)
13395 evexlig
= evexl256
;
13396 else if (strcmp (arg
, "512") == 0)
13397 evexlig
= evexl512
;
13399 as_fatal (_("invalid -mevexlig= option: `%s'"), arg
);
13402 case OPTION_MEVEXRCIG
:
13403 if (strcmp (arg
, "rne") == 0)
13405 else if (strcmp (arg
, "rd") == 0)
13407 else if (strcmp (arg
, "ru") == 0)
13409 else if (strcmp (arg
, "rz") == 0)
13412 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg
);
13415 case OPTION_MEVEXWIG
:
13416 if (strcmp (arg
, "0") == 0)
13418 else if (strcmp (arg
, "1") == 0)
13421 as_fatal (_("invalid -mevexwig= option: `%s'"), arg
);
13424 # if defined (TE_PE) || defined (TE_PEP)
13425 case OPTION_MBIG_OBJ
:
13430 case OPTION_MOMIT_LOCK_PREFIX
:
13431 if (strcasecmp (arg
, "yes") == 0)
13432 omit_lock_prefix
= 1;
13433 else if (strcasecmp (arg
, "no") == 0)
13434 omit_lock_prefix
= 0;
13436 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg
);
13439 case OPTION_MFENCE_AS_LOCK_ADD
:
13440 if (strcasecmp (arg
, "yes") == 0)
13442 else if (strcasecmp (arg
, "no") == 0)
13445 as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg
);
13448 case OPTION_MLFENCE_AFTER_LOAD
:
13449 if (strcasecmp (arg
, "yes") == 0)
13450 lfence_after_load
= 1;
13451 else if (strcasecmp (arg
, "no") == 0)
13452 lfence_after_load
= 0;
13454 as_fatal (_("invalid -mlfence-after-load= option: `%s'"), arg
);
13457 case OPTION_MLFENCE_BEFORE_INDIRECT_BRANCH
:
13458 if (strcasecmp (arg
, "all") == 0)
13460 lfence_before_indirect_branch
= lfence_branch_all
;
13461 if (lfence_before_ret
== lfence_before_ret_none
)
13462 lfence_before_ret
= lfence_before_ret_shl
;
13464 else if (strcasecmp (arg
, "memory") == 0)
13465 lfence_before_indirect_branch
= lfence_branch_memory
;
13466 else if (strcasecmp (arg
, "register") == 0)
13467 lfence_before_indirect_branch
= lfence_branch_register
;
13468 else if (strcasecmp (arg
, "none") == 0)
13469 lfence_before_indirect_branch
= lfence_branch_none
;
13471 as_fatal (_("invalid -mlfence-before-indirect-branch= option: `%s'"),
13475 case OPTION_MLFENCE_BEFORE_RET
:
13476 if (strcasecmp (arg
, "or") == 0)
13477 lfence_before_ret
= lfence_before_ret_or
;
13478 else if (strcasecmp (arg
, "not") == 0)
13479 lfence_before_ret
= lfence_before_ret_not
;
13480 else if (strcasecmp (arg
, "shl") == 0 || strcasecmp (arg
, "yes") == 0)
13481 lfence_before_ret
= lfence_before_ret_shl
;
13482 else if (strcasecmp (arg
, "none") == 0)
13483 lfence_before_ret
= lfence_before_ret_none
;
13485 as_fatal (_("invalid -mlfence-before-ret= option: `%s'"),
13489 case OPTION_MRELAX_RELOCATIONS
:
13490 if (strcasecmp (arg
, "yes") == 0)
13491 generate_relax_relocations
= 1;
13492 else if (strcasecmp (arg
, "no") == 0)
13493 generate_relax_relocations
= 0;
13495 as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg
);
13498 case OPTION_MALIGN_BRANCH_BOUNDARY
:
13501 long int align
= strtoul (arg
, &end
, 0);
13506 align_branch_power
= 0;
13509 else if (align
>= 16)
13512 for (align_power
= 0;
13514 align
>>= 1, align_power
++)
13516 /* Limit alignment power to 31. */
13517 if (align
== 1 && align_power
< 32)
13519 align_branch_power
= align_power
;
13524 as_fatal (_("invalid -malign-branch-boundary= value: %s"), arg
);
13528 case OPTION_MALIGN_BRANCH_PREFIX_SIZE
:
13531 int align
= strtoul (arg
, &end
, 0);
13532 /* Some processors only support 5 prefixes. */
13533 if (*end
== '\0' && align
>= 0 && align
< 6)
13535 align_branch_prefix_size
= align
;
13538 as_fatal (_("invalid -malign-branch-prefix-size= value: %s"),
13543 case OPTION_MALIGN_BRANCH
:
13545 saved
= xstrdup (arg
);
13549 next
= strchr (type
, '+');
13552 if (strcasecmp (type
, "jcc") == 0)
13553 align_branch
|= align_branch_jcc_bit
;
13554 else if (strcasecmp (type
, "fused") == 0)
13555 align_branch
|= align_branch_fused_bit
;
13556 else if (strcasecmp (type
, "jmp") == 0)
13557 align_branch
|= align_branch_jmp_bit
;
13558 else if (strcasecmp (type
, "call") == 0)
13559 align_branch
|= align_branch_call_bit
;
13560 else if (strcasecmp (type
, "ret") == 0)
13561 align_branch
|= align_branch_ret_bit
;
13562 else if (strcasecmp (type
, "indirect") == 0)
13563 align_branch
|= align_branch_indirect_bit
;
13565 as_fatal (_("invalid -malign-branch= option: `%s'"), arg
);
13568 while (next
!= NULL
);
13572 case OPTION_MBRANCHES_WITH_32B_BOUNDARIES
:
13573 align_branch_power
= 5;
13574 align_branch_prefix_size
= 5;
13575 align_branch
= (align_branch_jcc_bit
13576 | align_branch_fused_bit
13577 | align_branch_jmp_bit
);
13580 case OPTION_MAMD64
:
13584 case OPTION_MINTEL64
:
13592 /* Turn off -Os. */
13593 optimize_for_space
= 0;
13595 else if (*arg
== 's')
13597 optimize_for_space
= 1;
13598 /* Turn on all encoding optimizations. */
13599 optimize
= INT_MAX
;
13603 optimize
= atoi (arg
);
13604 /* Turn off -Os. */
13605 optimize_for_space
= 0;
13615 #define MESSAGE_TEMPLATE \
13619 output_message (FILE *stream
, char *p
, char *message
, char *start
,
13620 int *left_p
, const char *name
, int len
)
13622 int size
= sizeof (MESSAGE_TEMPLATE
);
13623 int left
= *left_p
;
13625 /* Reserve 2 spaces for ", " or ",\0" */
13628 /* Check if there is any room. */
13636 p
= mempcpy (p
, name
, len
);
13640 /* Output the current message now and start a new one. */
13643 fprintf (stream
, "%s\n", message
);
13645 left
= size
- (start
- message
) - len
- 2;
13647 gas_assert (left
>= 0);
13649 p
= mempcpy (p
, name
, len
);
13657 show_arch (FILE *stream
, int ext
, int check
)
13659 static char message
[] = MESSAGE_TEMPLATE
;
13660 char *start
= message
+ 27;
13662 int size
= sizeof (MESSAGE_TEMPLATE
);
13669 left
= size
- (start
- message
);
13670 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
13672 /* Should it be skipped? */
13673 if (cpu_arch
[j
].skip
)
13676 name
= cpu_arch
[j
].name
;
13677 len
= cpu_arch
[j
].len
;
13680 /* It is an extension. Skip if we aren't asked to show it. */
13691 /* It is an processor. Skip if we show only extension. */
13694 else if (check
&& ! cpu_arch
[j
].flags
.bitfield
.cpui386
)
13696 /* It is an impossible processor - skip. */
13700 p
= output_message (stream
, p
, message
, start
, &left
, name
, len
);
13703 /* Display disabled extensions. */
13705 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
13707 name
= cpu_noarch
[j
].name
;
13708 len
= cpu_noarch
[j
].len
;
13709 p
= output_message (stream
, p
, message
, start
, &left
, name
,
13714 fprintf (stream
, "%s\n", message
);
13718 md_show_usage (FILE *stream
)
13720 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13721 fprintf (stream
, _("\
13722 -Qy, -Qn ignored\n\
13723 -V print assembler version number\n\
13726 fprintf (stream
, _("\
13727 -n Do not optimize code alignment\n\
13728 -q quieten some warnings\n"));
13729 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13730 fprintf (stream
, _("\
13733 #if defined BFD64 && (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
13734 || defined (TE_PE) || defined (TE_PEP))
13735 fprintf (stream
, _("\
13736 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
13738 #ifdef SVR4_COMMENT_CHARS
13739 fprintf (stream
, _("\
13740 --divide do not treat `/' as a comment character\n"));
13742 fprintf (stream
, _("\
13743 --divide ignored\n"));
13745 fprintf (stream
, _("\
13746 -march=CPU[,+EXTENSION...]\n\
13747 generate code for CPU and EXTENSION, CPU is one of:\n"));
13748 show_arch (stream
, 0, 1);
13749 fprintf (stream
, _("\
13750 EXTENSION is combination of:\n"));
13751 show_arch (stream
, 1, 0);
13752 fprintf (stream
, _("\
13753 -mtune=CPU optimize for CPU, CPU is one of:\n"));
13754 show_arch (stream
, 0, 0);
13755 fprintf (stream
, _("\
13756 -msse2avx encode SSE instructions with VEX prefix\n"));
13757 fprintf (stream
, _("\
13758 -msse-check=[none|error|warning] (default: warning)\n\
13759 check SSE instructions\n"));
13760 fprintf (stream
, _("\
13761 -moperand-check=[none|error|warning] (default: warning)\n\
13762 check operand combinations for validity\n"));
13763 fprintf (stream
, _("\
13764 -mavxscalar=[128|256] (default: 128)\n\
13765 encode scalar AVX instructions with specific vector\n\
13767 fprintf (stream
, _("\
13768 -mvexwig=[0|1] (default: 0)\n\
13769 encode VEX instructions with specific VEX.W value\n\
13770 for VEX.W bit ignored instructions\n"));
13771 fprintf (stream
, _("\
13772 -mevexlig=[128|256|512] (default: 128)\n\
13773 encode scalar EVEX instructions with specific vector\n\
13775 fprintf (stream
, _("\
13776 -mevexwig=[0|1] (default: 0)\n\
13777 encode EVEX instructions with specific EVEX.W value\n\
13778 for EVEX.W bit ignored instructions\n"));
13779 fprintf (stream
, _("\
13780 -mevexrcig=[rne|rd|ru|rz] (default: rne)\n\
13781 encode EVEX instructions with specific EVEX.RC value\n\
13782 for SAE-only ignored instructions\n"));
13783 fprintf (stream
, _("\
13784 -mmnemonic=[att|intel] "));
13785 if (SYSV386_COMPAT
)
13786 fprintf (stream
, _("(default: att)\n"));
13788 fprintf (stream
, _("(default: intel)\n"));
13789 fprintf (stream
, _("\
13790 use AT&T/Intel mnemonic\n"));
13791 fprintf (stream
, _("\
13792 -msyntax=[att|intel] (default: att)\n\
13793 use AT&T/Intel syntax\n"));
13794 fprintf (stream
, _("\
13795 -mindex-reg support pseudo index registers\n"));
13796 fprintf (stream
, _("\
13797 -mnaked-reg don't require `%%' prefix for registers\n"));
13798 fprintf (stream
, _("\
13799 -madd-bnd-prefix add BND prefix for all valid branches\n"));
13800 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13801 fprintf (stream
, _("\
13802 -mshared disable branch optimization for shared code\n"));
13803 fprintf (stream
, _("\
13804 -mx86-used-note=[no|yes] "));
13805 if (DEFAULT_X86_USED_NOTE
)
13806 fprintf (stream
, _("(default: yes)\n"));
13808 fprintf (stream
, _("(default: no)\n"));
13809 fprintf (stream
, _("\
13810 generate x86 used ISA and feature properties\n"));
13812 #if defined (TE_PE) || defined (TE_PEP)
13813 fprintf (stream
, _("\
13814 -mbig-obj generate big object files\n"));
13816 fprintf (stream
, _("\
13817 -momit-lock-prefix=[no|yes] (default: no)\n\
13818 strip all lock prefixes\n"));
13819 fprintf (stream
, _("\
13820 -mfence-as-lock-add=[no|yes] (default: no)\n\
13821 encode lfence, mfence and sfence as\n\
13822 lock addl $0x0, (%%{re}sp)\n"));
13823 fprintf (stream
, _("\
13824 -mrelax-relocations=[no|yes] "));
13825 if (DEFAULT_GENERATE_X86_RELAX_RELOCATIONS
)
13826 fprintf (stream
, _("(default: yes)\n"));
13828 fprintf (stream
, _("(default: no)\n"));
13829 fprintf (stream
, _("\
13830 generate relax relocations\n"));
13831 fprintf (stream
, _("\
13832 -malign-branch-boundary=NUM (default: 0)\n\
13833 align branches within NUM byte boundary\n"));
13834 fprintf (stream
, _("\
13835 -malign-branch=TYPE[+TYPE...] (default: jcc+fused+jmp)\n\
13836 TYPE is combination of jcc, fused, jmp, call, ret,\n\
13838 specify types of branches to align\n"));
13839 fprintf (stream
, _("\
13840 -malign-branch-prefix-size=NUM (default: 5)\n\
13841 align branches with NUM prefixes per instruction\n"));
13842 fprintf (stream
, _("\
13843 -mbranches-within-32B-boundaries\n\
13844 align branches within 32 byte boundary\n"));
13845 fprintf (stream
, _("\
13846 -mlfence-after-load=[no|yes] (default: no)\n\
13847 generate lfence after load\n"));
13848 fprintf (stream
, _("\
13849 -mlfence-before-indirect-branch=[none|all|register|memory] (default: none)\n\
13850 generate lfence before indirect near branch\n"));
13851 fprintf (stream
, _("\
13852 -mlfence-before-ret=[none|or|not|shl|yes] (default: none)\n\
13853 generate lfence before ret\n"));
13854 fprintf (stream
, _("\
13855 -mamd64 accept only AMD64 ISA [default]\n"));
13856 fprintf (stream
, _("\
13857 -mintel64 accept only Intel64 ISA\n"));
13860 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
13861 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
13862 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
13864 /* Pick the target format to use. */
13867 i386_target_format (void)
13869 if (startswith (default_arch
, "x86_64"))
13871 update_code_flag (CODE_64BIT
, 1);
13872 if (default_arch
[6] == '\0')
13873 x86_elf_abi
= X86_64_ABI
;
13875 x86_elf_abi
= X86_64_X32_ABI
;
13877 else if (!strcmp (default_arch
, "i386"))
13878 update_code_flag (CODE_32BIT
, 1);
13879 else if (!strcmp (default_arch
, "iamcu"))
13881 update_code_flag (CODE_32BIT
, 1);
13882 if (cpu_arch_isa
== PROCESSOR_UNKNOWN
)
13884 static const i386_cpu_flags iamcu_flags
= CPU_IAMCU_FLAGS
;
13885 cpu_arch_name
= "iamcu";
13886 cpu_sub_arch_name
= NULL
;
13887 cpu_arch_flags
= iamcu_flags
;
13888 cpu_arch_isa
= PROCESSOR_IAMCU
;
13889 cpu_arch_isa_flags
= iamcu_flags
;
13890 if (!cpu_arch_tune_set
)
13892 cpu_arch_tune
= cpu_arch_isa
;
13893 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
13896 else if (cpu_arch_isa
!= PROCESSOR_IAMCU
)
13897 as_fatal (_("Intel MCU doesn't support `%s' architecture"),
13901 as_fatal (_("unknown architecture"));
13903 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
13904 cpu_arch_isa_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
13905 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
13906 cpu_arch_tune_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
13908 switch (OUTPUT_FLAVOR
)
13910 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
13911 case bfd_target_aout_flavour
:
13912 return AOUT_TARGET_FORMAT
;
13914 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
13915 # if defined (TE_PE) || defined (TE_PEP)
13916 case bfd_target_coff_flavour
:
13917 if (flag_code
== CODE_64BIT
)
13920 return use_big_obj
? "pe-bigobj-x86-64" : "pe-x86-64";
13922 return use_big_obj
? "pe-bigobj-i386" : "pe-i386";
13923 # elif defined (TE_GO32)
13924 case bfd_target_coff_flavour
:
13925 return "coff-go32";
13927 case bfd_target_coff_flavour
:
13928 return "coff-i386";
13931 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
13932 case bfd_target_elf_flavour
:
13934 const char *format
;
13936 switch (x86_elf_abi
)
13939 format
= ELF_TARGET_FORMAT
;
13941 tls_get_addr
= "___tls_get_addr";
13945 use_rela_relocations
= 1;
13948 tls_get_addr
= "__tls_get_addr";
13950 format
= ELF_TARGET_FORMAT64
;
13952 case X86_64_X32_ABI
:
13953 use_rela_relocations
= 1;
13956 tls_get_addr
= "__tls_get_addr";
13958 disallow_64bit_reloc
= 1;
13959 format
= ELF_TARGET_FORMAT32
;
13962 if (cpu_arch_isa
== PROCESSOR_L1OM
)
13964 if (x86_elf_abi
!= X86_64_ABI
)
13965 as_fatal (_("Intel L1OM is 64bit only"));
13966 return ELF_TARGET_L1OM_FORMAT
;
13968 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
13970 if (x86_elf_abi
!= X86_64_ABI
)
13971 as_fatal (_("Intel K1OM is 64bit only"));
13972 return ELF_TARGET_K1OM_FORMAT
;
13974 else if (cpu_arch_isa
== PROCESSOR_IAMCU
)
13976 if (x86_elf_abi
!= I386_ABI
)
13977 as_fatal (_("Intel MCU is 32bit only"));
13978 return ELF_TARGET_IAMCU_FORMAT
;
13984 #if defined (OBJ_MACH_O)
13985 case bfd_target_mach_o_flavour
:
13986 if (flag_code
== CODE_64BIT
)
13988 use_rela_relocations
= 1;
13990 return "mach-o-x86-64";
13993 return "mach-o-i386";
14001 #endif /* OBJ_MAYBE_ more than one */
14004 md_undefined_symbol (char *name
)
14006 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
14007 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
14008 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
14009 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
14013 if (symbol_find (name
))
14014 as_bad (_("GOT already in symbol table"));
14015 GOT_symbol
= symbol_new (name
, undefined_section
,
14016 &zero_address_frag
, 0);
14023 /* Round up a section size to the appropriate boundary. */
14026 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
14028 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
14029 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
14031 /* For a.out, force the section size to be aligned. If we don't do
14032 this, BFD will align it for us, but it will not write out the
14033 final bytes of the section. This may be a bug in BFD, but it is
14034 easier to fix it here since that is how the other a.out targets
14038 align
= bfd_section_alignment (segment
);
14039 size
= ((size
+ (1 << align
) - 1) & (-((valueT
) 1 << align
)));
14046 /* On the i386, PC-relative offsets are relative to the start of the
14047 next instruction. That is, the address of the offset, plus its
14048 size, since the offset is always the last part of the insn. */
14051 md_pcrel_from (fixS
*fixP
)
14053 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
14059 s_bss (int ignore ATTRIBUTE_UNUSED
)
14063 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
14065 obj_elf_section_change_hook ();
14067 temp
= get_absolute_expression ();
14068 subseg_set (bss_section
, (subsegT
) temp
);
14069 demand_empty_rest_of_line ();
14074 /* Remember constant directive. */
14077 i386_cons_align (int ignore ATTRIBUTE_UNUSED
)
14079 if (last_insn
.kind
!= last_insn_directive
14080 && (bfd_section_flags (now_seg
) & SEC_CODE
))
14082 last_insn
.seg
= now_seg
;
14083 last_insn
.kind
= last_insn_directive
;
14084 last_insn
.name
= "constant directive";
14085 last_insn
.file
= as_where (&last_insn
.line
);
14086 if (lfence_before_ret
!= lfence_before_ret_none
)
14088 if (lfence_before_indirect_branch
!= lfence_branch_none
)
14089 as_warn (_("constant directive skips -mlfence-before-ret "
14090 "and -mlfence-before-indirect-branch"));
14092 as_warn (_("constant directive skips -mlfence-before-ret"));
14094 else if (lfence_before_indirect_branch
!= lfence_branch_none
)
14095 as_warn (_("constant directive skips -mlfence-before-indirect-branch"));
14100 i386_validate_fix (fixS
*fixp
)
14102 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
14103 if (fixp
->fx_r_type
== BFD_RELOC_SIZE32
14104 || fixp
->fx_r_type
== BFD_RELOC_SIZE64
)
14105 return IS_ELF
&& fixp
->fx_addsy
14106 && (!S_IS_DEFINED (fixp
->fx_addsy
)
14107 || S_IS_EXTERNAL (fixp
->fx_addsy
));
14110 if (fixp
->fx_subsy
)
14112 if (fixp
->fx_subsy
== GOT_symbol
)
14114 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
14118 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
14119 if (fixp
->fx_tcbit2
)
14120 fixp
->fx_r_type
= (fixp
->fx_tcbit
14121 ? BFD_RELOC_X86_64_REX_GOTPCRELX
14122 : BFD_RELOC_X86_64_GOTPCRELX
);
14125 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
14130 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
14132 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
14134 fixp
->fx_subsy
= 0;
14137 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
14140 /* NB: Commit 292676c1 resolved PLT32 reloc aganst local symbol
14141 to section. Since PLT32 relocation must be against symbols,
14142 turn such PLT32 relocation into PC32 relocation. */
14144 && (fixp
->fx_r_type
== BFD_RELOC_386_PLT32
14145 || fixp
->fx_r_type
== BFD_RELOC_X86_64_PLT32
)
14146 && symbol_section_p (fixp
->fx_addsy
))
14147 fixp
->fx_r_type
= BFD_RELOC_32_PCREL
;
14150 if (fixp
->fx_r_type
== BFD_RELOC_386_GOT32
14151 && fixp
->fx_tcbit2
)
14152 fixp
->fx_r_type
= BFD_RELOC_386_GOT32X
;
14161 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
14164 bfd_reloc_code_real_type code
;
14166 switch (fixp
->fx_r_type
)
14168 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
14171 case BFD_RELOC_SIZE32
:
14172 case BFD_RELOC_SIZE64
:
14174 && !bfd_is_abs_section (S_GET_SEGMENT (fixp
->fx_addsy
))
14175 && (!fixp
->fx_subsy
14176 || bfd_is_abs_section (S_GET_SEGMENT (fixp
->fx_subsy
))))
14177 sym
= fixp
->fx_addsy
;
14178 else if (fixp
->fx_subsy
14179 && !bfd_is_abs_section (S_GET_SEGMENT (fixp
->fx_subsy
))
14180 && (!fixp
->fx_addsy
14181 || bfd_is_abs_section (S_GET_SEGMENT (fixp
->fx_addsy
))))
14182 sym
= fixp
->fx_subsy
;
14185 if (IS_ELF
&& sym
&& S_IS_DEFINED (sym
) && !S_IS_EXTERNAL (sym
))
14187 /* Resolve size relocation against local symbol to size of
14188 the symbol plus addend. */
14189 valueT value
= S_GET_SIZE (sym
);
14191 if (symbol_get_bfdsym (sym
)->flags
& BSF_SECTION_SYM
)
14192 value
= bfd_section_size (S_GET_SEGMENT (sym
));
14193 if (sym
== fixp
->fx_subsy
)
14196 if (fixp
->fx_addsy
)
14197 value
+= S_GET_VALUE (fixp
->fx_addsy
);
14199 else if (fixp
->fx_subsy
)
14200 value
-= S_GET_VALUE (fixp
->fx_subsy
);
14201 value
+= fixp
->fx_offset
;
14202 if (fixp
->fx_r_type
== BFD_RELOC_SIZE32
14204 && !fits_in_unsigned_long (value
))
14205 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
14206 _("symbol size computation overflow"));
14207 fixp
->fx_addsy
= NULL
;
14208 fixp
->fx_subsy
= NULL
;
14209 md_apply_fix (fixp
, (valueT
*) &value
, NULL
);
14212 if (!fixp
->fx_addsy
|| fixp
->fx_subsy
)
14214 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
14215 "unsupported expression involving @size");
14219 /* Fall through. */
14221 case BFD_RELOC_X86_64_PLT32
:
14222 case BFD_RELOC_X86_64_GOT32
:
14223 case BFD_RELOC_X86_64_GOTPCREL
:
14224 case BFD_RELOC_X86_64_GOTPCRELX
:
14225 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
14226 case BFD_RELOC_386_PLT32
:
14227 case BFD_RELOC_386_GOT32
:
14228 case BFD_RELOC_386_GOT32X
:
14229 case BFD_RELOC_386_GOTOFF
:
14230 case BFD_RELOC_386_GOTPC
:
14231 case BFD_RELOC_386_TLS_GD
:
14232 case BFD_RELOC_386_TLS_LDM
:
14233 case BFD_RELOC_386_TLS_LDO_32
:
14234 case BFD_RELOC_386_TLS_IE_32
:
14235 case BFD_RELOC_386_TLS_IE
:
14236 case BFD_RELOC_386_TLS_GOTIE
:
14237 case BFD_RELOC_386_TLS_LE_32
:
14238 case BFD_RELOC_386_TLS_LE
:
14239 case BFD_RELOC_386_TLS_GOTDESC
:
14240 case BFD_RELOC_386_TLS_DESC_CALL
:
14241 case BFD_RELOC_X86_64_TLSGD
:
14242 case BFD_RELOC_X86_64_TLSLD
:
14243 case BFD_RELOC_X86_64_DTPOFF32
:
14244 case BFD_RELOC_X86_64_DTPOFF64
:
14245 case BFD_RELOC_X86_64_GOTTPOFF
:
14246 case BFD_RELOC_X86_64_TPOFF32
:
14247 case BFD_RELOC_X86_64_TPOFF64
:
14248 case BFD_RELOC_X86_64_GOTOFF64
:
14249 case BFD_RELOC_X86_64_GOTPC32
:
14250 case BFD_RELOC_X86_64_GOT64
:
14251 case BFD_RELOC_X86_64_GOTPCREL64
:
14252 case BFD_RELOC_X86_64_GOTPC64
:
14253 case BFD_RELOC_X86_64_GOTPLT64
:
14254 case BFD_RELOC_X86_64_PLTOFF64
:
14255 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
14256 case BFD_RELOC_X86_64_TLSDESC_CALL
:
14257 case BFD_RELOC_RVA
:
14258 case BFD_RELOC_VTABLE_ENTRY
:
14259 case BFD_RELOC_VTABLE_INHERIT
:
14261 case BFD_RELOC_32_SECREL
:
14263 code
= fixp
->fx_r_type
;
14265 case BFD_RELOC_X86_64_32S
:
14266 if (!fixp
->fx_pcrel
)
14268 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
14269 code
= fixp
->fx_r_type
;
14272 /* Fall through. */
14274 if (fixp
->fx_pcrel
)
14276 switch (fixp
->fx_size
)
14279 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
14280 _("can not do %d byte pc-relative relocation"),
14282 code
= BFD_RELOC_32_PCREL
;
14284 case 1: code
= BFD_RELOC_8_PCREL
; break;
14285 case 2: code
= BFD_RELOC_16_PCREL
; break;
14286 case 4: code
= BFD_RELOC_32_PCREL
; break;
14288 case 8: code
= BFD_RELOC_64_PCREL
; break;
14294 switch (fixp
->fx_size
)
14297 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
14298 _("can not do %d byte relocation"),
14300 code
= BFD_RELOC_32
;
14302 case 1: code
= BFD_RELOC_8
; break;
14303 case 2: code
= BFD_RELOC_16
; break;
14304 case 4: code
= BFD_RELOC_32
; break;
14306 case 8: code
= BFD_RELOC_64
; break;
14313 if ((code
== BFD_RELOC_32
14314 || code
== BFD_RELOC_32_PCREL
14315 || code
== BFD_RELOC_X86_64_32S
)
14317 && fixp
->fx_addsy
== GOT_symbol
)
14320 code
= BFD_RELOC_386_GOTPC
;
14322 code
= BFD_RELOC_X86_64_GOTPC32
;
14324 if ((code
== BFD_RELOC_64
|| code
== BFD_RELOC_64_PCREL
)
14326 && fixp
->fx_addsy
== GOT_symbol
)
14328 code
= BFD_RELOC_X86_64_GOTPC64
;
14331 rel
= XNEW (arelent
);
14332 rel
->sym_ptr_ptr
= XNEW (asymbol
*);
14333 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
14335 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
14337 if (!use_rela_relocations
)
14339 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
14340 vtable entry to be used in the relocation's section offset. */
14341 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
14342 rel
->address
= fixp
->fx_offset
;
14343 #if defined (OBJ_COFF) && defined (TE_PE)
14344 else if (fixp
->fx_addsy
&& S_IS_WEAK (fixp
->fx_addsy
))
14345 rel
->addend
= fixp
->fx_addnumber
- (S_GET_VALUE (fixp
->fx_addsy
) * 2);
14350 /* Use the rela in 64bit mode. */
14353 if (disallow_64bit_reloc
)
14356 case BFD_RELOC_X86_64_DTPOFF64
:
14357 case BFD_RELOC_X86_64_TPOFF64
:
14358 case BFD_RELOC_64_PCREL
:
14359 case BFD_RELOC_X86_64_GOTOFF64
:
14360 case BFD_RELOC_X86_64_GOT64
:
14361 case BFD_RELOC_X86_64_GOTPCREL64
:
14362 case BFD_RELOC_X86_64_GOTPC64
:
14363 case BFD_RELOC_X86_64_GOTPLT64
:
14364 case BFD_RELOC_X86_64_PLTOFF64
:
14365 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
14366 _("cannot represent relocation type %s in x32 mode"),
14367 bfd_get_reloc_code_name (code
));
14373 if (!fixp
->fx_pcrel
)
14374 rel
->addend
= fixp
->fx_offset
;
14378 case BFD_RELOC_X86_64_PLT32
:
14379 case BFD_RELOC_X86_64_GOT32
:
14380 case BFD_RELOC_X86_64_GOTPCREL
:
14381 case BFD_RELOC_X86_64_GOTPCRELX
:
14382 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
14383 case BFD_RELOC_X86_64_TLSGD
:
14384 case BFD_RELOC_X86_64_TLSLD
:
14385 case BFD_RELOC_X86_64_GOTTPOFF
:
14386 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
14387 case BFD_RELOC_X86_64_TLSDESC_CALL
:
14388 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
14391 rel
->addend
= (section
->vma
14393 + fixp
->fx_addnumber
14394 + md_pcrel_from (fixp
));
14399 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
14400 if (rel
->howto
== NULL
)
14402 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
14403 _("cannot represent relocation type %s"),
14404 bfd_get_reloc_code_name (code
));
14405 /* Set howto to a garbage value so that we can keep going. */
14406 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
14407 gas_assert (rel
->howto
!= NULL
);
14413 #include "tc-i386-intel.c"
14416 tc_x86_parse_to_dw2regnum (expressionS
*exp
)
14418 int saved_naked_reg
;
14419 char saved_register_dot
;
14421 saved_naked_reg
= allow_naked_reg
;
14422 allow_naked_reg
= 1;
14423 saved_register_dot
= register_chars
['.'];
14424 register_chars
['.'] = '.';
14425 allow_pseudo_reg
= 1;
14426 expression_and_evaluate (exp
);
14427 allow_pseudo_reg
= 0;
14428 register_chars
['.'] = saved_register_dot
;
14429 allow_naked_reg
= saved_naked_reg
;
14431 if (exp
->X_op
== O_register
&& exp
->X_add_number
>= 0)
14433 if ((addressT
) exp
->X_add_number
< i386_regtab_size
)
14435 exp
->X_op
= O_constant
;
14436 exp
->X_add_number
= i386_regtab
[exp
->X_add_number
]
14437 .dw2_regnum
[flag_code
>> 1];
14440 exp
->X_op
= O_illegal
;
14445 tc_x86_frame_initial_instructions (void)
14447 static unsigned int sp_regno
[2];
14449 if (!sp_regno
[flag_code
>> 1])
14451 char *saved_input
= input_line_pointer
;
14452 char sp
[][4] = {"esp", "rsp"};
14455 input_line_pointer
= sp
[flag_code
>> 1];
14456 tc_x86_parse_to_dw2regnum (&exp
);
14457 gas_assert (exp
.X_op
== O_constant
);
14458 sp_regno
[flag_code
>> 1] = exp
.X_add_number
;
14459 input_line_pointer
= saved_input
;
14462 cfi_add_CFA_def_cfa (sp_regno
[flag_code
>> 1], -x86_cie_data_alignment
);
14463 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
14467 x86_dwarf2_addr_size (void)
14469 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
14470 if (x86_elf_abi
== X86_64_X32_ABI
)
14473 return bfd_arch_bits_per_address (stdoutput
) / 8;
14477 i386_elf_section_type (const char *str
, size_t len
)
14479 if (flag_code
== CODE_64BIT
14480 && len
== sizeof ("unwind") - 1
14481 && startswith (str
, "unwind"))
14482 return SHT_X86_64_UNWIND
;
14489 i386_solaris_fix_up_eh_frame (segT sec
)
14491 if (flag_code
== CODE_64BIT
)
14492 elf_section_type (sec
) = SHT_X86_64_UNWIND
;
14498 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
14502 exp
.X_op
= O_secrel
;
14503 exp
.X_add_symbol
= symbol
;
14504 exp
.X_add_number
= 0;
14505 emit_expr (&exp
, size
);
14509 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
14510 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
14513 x86_64_section_letter (int letter
, const char **ptr_msg
)
14515 if (flag_code
== CODE_64BIT
)
14518 return SHF_X86_64_LARGE
;
14520 *ptr_msg
= _("bad .section directive: want a,l,w,x,M,S,G,T in string");
14523 *ptr_msg
= _("bad .section directive: want a,w,x,M,S,G,T in string");
14528 x86_64_section_word (char *str
, size_t len
)
14530 if (len
== 5 && flag_code
== CODE_64BIT
&& startswith (str
, "large"))
14531 return SHF_X86_64_LARGE
;
14537 handle_large_common (int small ATTRIBUTE_UNUSED
)
14539 if (flag_code
!= CODE_64BIT
)
14541 s_comm_internal (0, elf_common_parse
);
14542 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
14546 static segT lbss_section
;
14547 asection
*saved_com_section_ptr
= elf_com_section_ptr
;
14548 asection
*saved_bss_section
= bss_section
;
14550 if (lbss_section
== NULL
)
14552 flagword applicable
;
14553 segT seg
= now_seg
;
14554 subsegT subseg
= now_subseg
;
14556 /* The .lbss section is for local .largecomm symbols. */
14557 lbss_section
= subseg_new (".lbss", 0);
14558 applicable
= bfd_applicable_section_flags (stdoutput
);
14559 bfd_set_section_flags (lbss_section
, applicable
& SEC_ALLOC
);
14560 seg_info (lbss_section
)->bss
= 1;
14562 subseg_set (seg
, subseg
);
14565 elf_com_section_ptr
= &_bfd_elf_large_com_section
;
14566 bss_section
= lbss_section
;
14568 s_comm_internal (0, elf_common_parse
);
14570 elf_com_section_ptr
= saved_com_section_ptr
;
14571 bss_section
= saved_bss_section
;
14574 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */