1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright (C) 1989-2019 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 /* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
23 x86_64 support by Jan Hubicka (jh@suse.cz)
24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
29 #include "safe-ctype.h"
31 #include "dwarf2dbg.h"
32 #include "dw2gencfi.h"
33 #include "elf/x86-64.h"
34 #include "opcodes/i386-init.h"
39 #ifdef HAVE_SYS_PARAM_H
40 #include <sys/param.h>
43 #define INT_MAX (int) (((unsigned) (-1)) >> 1)
47 #ifndef REGISTER_WARNINGS
48 #define REGISTER_WARNINGS 1
51 #ifndef INFER_ADDR_PREFIX
52 #define INFER_ADDR_PREFIX 1
56 #define DEFAULT_ARCH "i386"
61 #define INLINE __inline__
67 /* Prefixes will be emitted in the order defined below.
68 WAIT_PREFIX must be the first prefix since FWAIT is really is an
69 instruction, and so must come before any prefixes.
70 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
71 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
77 #define HLE_PREFIX REP_PREFIX
78 #define BND_PREFIX REP_PREFIX
80 #define REX_PREFIX 6 /* must come last. */
81 #define MAX_PREFIXES 7 /* max prefixes per opcode */
83 /* we define the syntax here (modulo base,index,scale syntax) */
84 #define REGISTER_PREFIX '%'
85 #define IMMEDIATE_PREFIX '$'
86 #define ABSOLUTE_PREFIX '*'
88 /* these are the instruction mnemonic suffixes in AT&T syntax or
89 memory operand size in Intel syntax. */
90 #define WORD_MNEM_SUFFIX 'w'
91 #define BYTE_MNEM_SUFFIX 'b'
92 #define SHORT_MNEM_SUFFIX 's'
93 #define LONG_MNEM_SUFFIX 'l'
94 #define QWORD_MNEM_SUFFIX 'q'
95 /* Intel Syntax. Use a non-ascii letter since since it never appears
97 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
99 #define END_OF_INSN '\0'
101 /* This matches the C -> StaticRounding alias in the opcode table. */
102 #define commutative staticrounding
105 'templates' is for grouping together 'template' structures for opcodes
106 of the same name. This is only used for storing the insns in the grand
107 ole hash table of insns.
108 The templates themselves start at START and range up to (but not including)
113 const insn_template
*start
;
114 const insn_template
*end
;
118 /* 386 operand encoding bytes: see 386 book for details of this. */
121 unsigned int regmem
; /* codes register or memory operand */
122 unsigned int reg
; /* codes register operand (or extended opcode) */
123 unsigned int mode
; /* how to interpret regmem & reg */
127 /* x86-64 extension prefix. */
128 typedef int rex_byte
;
130 /* 386 opcode byte to code indirect addressing. */
139 /* x86 arch names, types and features */
142 const char *name
; /* arch name */
143 unsigned int len
; /* arch string length */
144 enum processor_type type
; /* arch type */
145 i386_cpu_flags flags
; /* cpu feature flags */
146 unsigned int skip
; /* show_arch should skip this. */
150 /* Used to turn off indicated flags. */
153 const char *name
; /* arch name */
154 unsigned int len
; /* arch string length */
155 i386_cpu_flags flags
; /* cpu feature flags */
159 static void update_code_flag (int, int);
160 static void set_code_flag (int);
161 static void set_16bit_gcc_code_flag (int);
162 static void set_intel_syntax (int);
163 static void set_intel_mnemonic (int);
164 static void set_allow_index_reg (int);
165 static void set_check (int);
166 static void set_cpu_arch (int);
168 static void pe_directive_secrel (int);
170 static void signed_cons (int);
171 static char *output_invalid (int c
);
172 static int i386_finalize_immediate (segT
, expressionS
*, i386_operand_type
,
174 static int i386_finalize_displacement (segT
, expressionS
*, i386_operand_type
,
176 static int i386_att_operand (char *);
177 static int i386_intel_operand (char *, int);
178 static int i386_intel_simplify (expressionS
*);
179 static int i386_intel_parse_name (const char *, expressionS
*);
180 static const reg_entry
*parse_register (char *, char **);
181 static char *parse_insn (char *, char *);
182 static char *parse_operands (char *, const char *);
183 static void swap_operands (void);
184 static void swap_2_operands (int, int);
185 static void optimize_imm (void);
186 static void optimize_disp (void);
187 static const insn_template
*match_template (char);
188 static int check_string (void);
189 static int process_suffix (void);
190 static int check_byte_reg (void);
191 static int check_long_reg (void);
192 static int check_qword_reg (void);
193 static int check_word_reg (void);
194 static int finalize_imm (void);
195 static int process_operands (void);
196 static const seg_entry
*build_modrm_byte (void);
197 static void output_insn (void);
198 static void output_imm (fragS
*, offsetT
);
199 static void output_disp (fragS
*, offsetT
);
201 static void s_bss (int);
203 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
204 static void handle_large_common (int small ATTRIBUTE_UNUSED
);
206 /* GNU_PROPERTY_X86_ISA_1_USED. */
207 static unsigned int x86_isa_1_used
;
208 /* GNU_PROPERTY_X86_FEATURE_2_USED. */
209 static unsigned int x86_feature_2_used
;
210 /* Generate x86 used ISA and feature properties. */
211 static unsigned int x86_used_note
= DEFAULT_X86_USED_NOTE
;
214 static const char *default_arch
= DEFAULT_ARCH
;
216 /* This struct describes rounding control and SAE in the instruction. */
230 static struct RC_Operation rc_op
;
232 /* The struct describes masking, applied to OPERAND in the instruction.
233 MASK is a pointer to the corresponding mask register. ZEROING tells
234 whether merging or zeroing mask is used. */
235 struct Mask_Operation
237 const reg_entry
*mask
;
238 unsigned int zeroing
;
239 /* The operand where this operation is associated. */
243 static struct Mask_Operation mask_op
;
245 /* The struct describes broadcasting, applied to OPERAND. FACTOR is
247 struct Broadcast_Operation
249 /* Type of broadcast: {1to2}, {1to4}, {1to8}, or {1to16}. */
252 /* Index of broadcasted operand. */
255 /* Number of bytes to broadcast. */
259 static struct Broadcast_Operation broadcast_op
;
264 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
265 unsigned char bytes
[4];
267 /* Destination or source register specifier. */
268 const reg_entry
*register_specifier
;
271 /* 'md_assemble ()' gathers together information and puts it into a
278 const reg_entry
*regs
;
283 operand_size_mismatch
,
284 operand_type_mismatch
,
285 register_type_mismatch
,
286 number_of_operands_mismatch
,
287 invalid_instruction_suffix
,
289 unsupported_with_intel_mnemonic
,
292 invalid_vsib_address
,
293 invalid_vector_register_set
,
294 unsupported_vector_index_register
,
295 unsupported_broadcast
,
298 mask_not_on_destination
,
301 rc_sae_operand_not_last_imm
,
302 invalid_register_operand
,
307 /* TM holds the template for the insn were currently assembling. */
310 /* SUFFIX holds the instruction size suffix for byte, word, dword
311 or qword, if given. */
314 /* OPERANDS gives the number of given operands. */
315 unsigned int operands
;
317 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
318 of given register, displacement, memory operands and immediate
320 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
322 /* TYPES [i] is the type (see above #defines) which tells us how to
323 use OP[i] for the corresponding operand. */
324 i386_operand_type types
[MAX_OPERANDS
];
326 /* Displacement expression, immediate expression, or register for each
328 union i386_op op
[MAX_OPERANDS
];
330 /* Flags for operands. */
331 unsigned int flags
[MAX_OPERANDS
];
332 #define Operand_PCrel 1
333 #define Operand_Mem 2
335 /* Relocation type for operand */
336 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
338 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
339 the base index byte below. */
340 const reg_entry
*base_reg
;
341 const reg_entry
*index_reg
;
342 unsigned int log2_scale_factor
;
344 /* SEG gives the seg_entries of this insn. They are zero unless
345 explicit segment overrides are given. */
346 const seg_entry
*seg
[2];
348 /* Copied first memory operand string, for re-checking. */
351 /* PREFIX holds all the given prefix opcodes (usually null).
352 PREFIXES is the number of prefix opcodes. */
353 unsigned int prefixes
;
354 unsigned char prefix
[MAX_PREFIXES
];
356 /* Has MMX register operands. */
357 bfd_boolean has_regmmx
;
359 /* Has XMM register operands. */
360 bfd_boolean has_regxmm
;
362 /* Has YMM register operands. */
363 bfd_boolean has_regymm
;
365 /* Has ZMM register operands. */
366 bfd_boolean has_regzmm
;
368 /* RM and SIB are the modrm byte and the sib byte where the
369 addressing modes of this insn are encoded. */
376 /* Masking attributes. */
377 struct Mask_Operation
*mask
;
379 /* Rounding control and SAE attributes. */
380 struct RC_Operation
*rounding
;
382 /* Broadcasting attributes. */
383 struct Broadcast_Operation
*broadcast
;
385 /* Compressed disp8*N attribute. */
386 unsigned int memshift
;
388 /* Prefer load or store in encoding. */
391 dir_encoding_default
= 0,
397 /* Prefer 8bit or 32bit displacement in encoding. */
400 disp_encoding_default
= 0,
405 /* Prefer the REX byte in encoding. */
406 bfd_boolean rex_encoding
;
408 /* Disable instruction size optimization. */
409 bfd_boolean no_optimize
;
411 /* How to encode vector instructions. */
414 vex_encoding_default
= 0,
421 const char *rep_prefix
;
424 const char *hle_prefix
;
426 /* Have BND prefix. */
427 const char *bnd_prefix
;
429 /* Have NOTRACK prefix. */
430 const char *notrack_prefix
;
433 enum i386_error error
;
436 typedef struct _i386_insn i386_insn
;
438 /* Link RC type with corresponding string, that'll be looked for in
447 static const struct RC_name RC_NamesTable
[] =
449 { rne
, STRING_COMMA_LEN ("rn-sae") },
450 { rd
, STRING_COMMA_LEN ("rd-sae") },
451 { ru
, STRING_COMMA_LEN ("ru-sae") },
452 { rz
, STRING_COMMA_LEN ("rz-sae") },
453 { saeonly
, STRING_COMMA_LEN ("sae") },
456 /* List of chars besides those in app.c:symbol_chars that can start an
457 operand. Used to prevent the scrubber eating vital white-space. */
458 const char extra_symbol_chars
[] = "*%-([{}"
467 #if (defined (TE_I386AIX) \
468 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
469 && !defined (TE_GNU) \
470 && !defined (TE_LINUX) \
471 && !defined (TE_NACL) \
472 && !defined (TE_FreeBSD) \
473 && !defined (TE_DragonFly) \
474 && !defined (TE_NetBSD)))
475 /* This array holds the chars that always start a comment. If the
476 pre-processor is disabled, these aren't very useful. The option
477 --divide will remove '/' from this list. */
478 const char *i386_comment_chars
= "#/";
479 #define SVR4_COMMENT_CHARS 1
480 #define PREFIX_SEPARATOR '\\'
483 const char *i386_comment_chars
= "#";
484 #define PREFIX_SEPARATOR '/'
487 /* This array holds the chars that only start a comment at the beginning of
488 a line. If the line seems to have the form '# 123 filename'
489 .line and .file directives will appear in the pre-processed output.
490 Note that input_file.c hand checks for '#' at the beginning of the
491 first line of the input file. This is because the compiler outputs
492 #NO_APP at the beginning of its output.
493 Also note that comments started like this one will always work if
494 '/' isn't otherwise defined. */
495 const char line_comment_chars
[] = "#/";
497 const char line_separator_chars
[] = ";";
499 /* Chars that can be used to separate mant from exp in floating point
501 const char EXP_CHARS
[] = "eE";
503 /* Chars that mean this number is a floating point constant
506 const char FLT_CHARS
[] = "fFdDxX";
508 /* Tables for lexical analysis. */
509 static char mnemonic_chars
[256];
510 static char register_chars
[256];
511 static char operand_chars
[256];
512 static char identifier_chars
[256];
513 static char digit_chars
[256];
515 /* Lexical macros. */
516 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
517 #define is_operand_char(x) (operand_chars[(unsigned char) x])
518 #define is_register_char(x) (register_chars[(unsigned char) x])
519 #define is_space_char(x) ((x) == ' ')
520 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
521 #define is_digit_char(x) (digit_chars[(unsigned char) x])
523 /* All non-digit non-letter characters that may occur in an operand. */
524 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
526 /* md_assemble() always leaves the strings it's passed unaltered. To
527 effect this we maintain a stack of saved characters that we've smashed
528 with '\0's (indicating end of strings for various sub-fields of the
529 assembler instruction). */
530 static char save_stack
[32];
531 static char *save_stack_p
;
532 #define END_STRING_AND_SAVE(s) \
533 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
534 #define RESTORE_END_STRING(s) \
535 do { *(s) = *--save_stack_p; } while (0)
537 /* The instruction we're assembling. */
540 /* Possible templates for current insn. */
541 static const templates
*current_templates
;
543 /* Per instruction expressionS buffers: max displacements & immediates. */
544 static expressionS disp_expressions
[MAX_MEMORY_OPERANDS
];
545 static expressionS im_expressions
[MAX_IMMEDIATE_OPERANDS
];
547 /* Current operand we are working on. */
548 static int this_operand
= -1;
550 /* We support four different modes. FLAG_CODE variable is used to distinguish
558 static enum flag_code flag_code
;
559 static unsigned int object_64bit
;
560 static unsigned int disallow_64bit_reloc
;
561 static int use_rela_relocations
= 0;
563 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
564 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
565 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
567 /* The ELF ABI to use. */
575 static enum x86_elf_abi x86_elf_abi
= I386_ABI
;
578 #if defined (TE_PE) || defined (TE_PEP)
579 /* Use big object file format. */
580 static int use_big_obj
= 0;
583 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
584 /* 1 if generating code for a shared library. */
585 static int shared
= 0;
588 /* 1 for intel syntax,
590 static int intel_syntax
= 0;
592 /* 1 for Intel64 ISA,
596 /* 1 for intel mnemonic,
597 0 if att mnemonic. */
598 static int intel_mnemonic
= !SYSV386_COMPAT
;
600 /* 1 if pseudo registers are permitted. */
601 static int allow_pseudo_reg
= 0;
603 /* 1 if register prefix % not required. */
604 static int allow_naked_reg
= 0;
606 /* 1 if the assembler should add BND prefix for all control-transferring
607 instructions supporting it, even if this prefix wasn't specified
609 static int add_bnd_prefix
= 0;
611 /* 1 if pseudo index register, eiz/riz, is allowed . */
612 static int allow_index_reg
= 0;
614 /* 1 if the assembler should ignore LOCK prefix, even if it was
615 specified explicitly. */
616 static int omit_lock_prefix
= 0;
618 /* 1 if the assembler should encode lfence, mfence, and sfence as
619 "lock addl $0, (%{re}sp)". */
620 static int avoid_fence
= 0;
622 /* 1 if the assembler should generate relax relocations. */
624 static int generate_relax_relocations
625 = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS
;
627 static enum check_kind
633 sse_check
, operand_check
= check_warning
;
636 1. Clear the REX_W bit with register operand if possible.
637 2. Above plus use 128bit vector instruction to clear the full vector
640 static int optimize
= 0;
643 1. Clear the REX_W bit with register operand if possible.
644 2. Above plus use 128bit vector instruction to clear the full vector
646 3. Above plus optimize "test{q,l,w} $imm8,%r{64,32,16}" to
649 static int optimize_for_space
= 0;
651 /* Register prefix used for error message. */
652 static const char *register_prefix
= "%";
654 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
655 leave, push, and pop instructions so that gcc has the same stack
656 frame as in 32 bit mode. */
657 static char stackop_size
= '\0';
659 /* Non-zero to optimize code alignment. */
660 int optimize_align_code
= 1;
662 /* Non-zero to quieten some warnings. */
663 static int quiet_warnings
= 0;
666 static const char *cpu_arch_name
= NULL
;
667 static char *cpu_sub_arch_name
= NULL
;
669 /* CPU feature flags. */
670 static i386_cpu_flags cpu_arch_flags
= CPU_UNKNOWN_FLAGS
;
672 /* If we have selected a cpu we are generating instructions for. */
673 static int cpu_arch_tune_set
= 0;
675 /* Cpu we are generating instructions for. */
676 enum processor_type cpu_arch_tune
= PROCESSOR_UNKNOWN
;
678 /* CPU feature flags of cpu we are generating instructions for. */
679 static i386_cpu_flags cpu_arch_tune_flags
;
681 /* CPU instruction set architecture used. */
682 enum processor_type cpu_arch_isa
= PROCESSOR_UNKNOWN
;
684 /* CPU feature flags of instruction set architecture used. */
685 i386_cpu_flags cpu_arch_isa_flags
;
687 /* If set, conditional jumps are not automatically promoted to handle
688 larger than a byte offset. */
689 static unsigned int no_cond_jump_promotion
= 0;
691 /* Encode SSE instructions with VEX prefix. */
692 static unsigned int sse2avx
;
694 /* Encode scalar AVX instructions with specific vector length. */
701 /* Encode VEX WIG instructions with specific vex.w. */
708 /* Encode scalar EVEX LIG instructions with specific vector length. */
716 /* Encode EVEX WIG instructions with specific evex.w. */
723 /* Value to encode in EVEX RC bits, for SAE-only instructions. */
724 static enum rc_type evexrcig
= rne
;
726 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
727 static symbolS
*GOT_symbol
;
729 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
730 unsigned int x86_dwarf2_return_column
;
732 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
733 int x86_cie_data_alignment
;
735 /* Interface to relax_segment.
736 There are 3 major relax states for 386 jump insns because the
737 different types of jumps add different sizes to frags when we're
738 figuring out what sort of jump to choose to reach a given label. */
741 #define UNCOND_JUMP 0
743 #define COND_JUMP86 2
748 #define SMALL16 (SMALL | CODE16)
750 #define BIG16 (BIG | CODE16)
754 #define INLINE __inline__
760 #define ENCODE_RELAX_STATE(type, size) \
761 ((relax_substateT) (((type) << 2) | (size)))
762 #define TYPE_FROM_RELAX_STATE(s) \
764 #define DISP_SIZE_FROM_RELAX_STATE(s) \
765 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
767 /* This table is used by relax_frag to promote short jumps to long
768 ones where necessary. SMALL (short) jumps may be promoted to BIG
769 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
770 don't allow a short jump in a 32 bit code segment to be promoted to
771 a 16 bit offset jump because it's slower (requires data size
772 prefix), and doesn't work, unless the destination is in the bottom
773 64k of the code segment (The top 16 bits of eip are zeroed). */
775 const relax_typeS md_relax_table
[] =
778 1) most positive reach of this state,
779 2) most negative reach of this state,
780 3) how many bytes this mode will have in the variable part of the frag
781 4) which index into the table to try if we can't fit into this one. */
783 /* UNCOND_JUMP states. */
784 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
785 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
786 /* dword jmp adds 4 bytes to frag:
787 0 extra opcode bytes, 4 displacement bytes. */
789 /* word jmp adds 2 byte2 to frag:
790 0 extra opcode bytes, 2 displacement bytes. */
793 /* COND_JUMP states. */
794 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
795 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
796 /* dword conditionals adds 5 bytes to frag:
797 1 extra opcode byte, 4 displacement bytes. */
799 /* word conditionals add 3 bytes to frag:
800 1 extra opcode byte, 2 displacement bytes. */
803 /* COND_JUMP86 states. */
804 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
805 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
806 /* dword conditionals adds 5 bytes to frag:
807 1 extra opcode byte, 4 displacement bytes. */
809 /* word conditionals add 4 bytes to frag:
810 1 displacement byte and a 3 byte long branch insn. */
814 static const arch_entry cpu_arch
[] =
816 /* Do not replace the first two entries - i386_target_format()
817 relies on them being there in this order. */
818 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32
,
819 CPU_GENERIC32_FLAGS
, 0 },
820 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64
,
821 CPU_GENERIC64_FLAGS
, 0 },
822 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN
,
824 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN
,
826 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN
,
828 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386
,
830 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486
,
832 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM
,
834 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO
,
836 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM
,
838 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO
,
839 CPU_PENTIUMPRO_FLAGS
, 0 },
840 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO
,
842 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO
,
844 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4
,
846 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA
,
848 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA
,
849 CPU_NOCONA_FLAGS
, 0 },
850 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE
,
852 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE
,
854 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2
,
855 CPU_CORE2_FLAGS
, 1 },
856 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2
,
857 CPU_CORE2_FLAGS
, 0 },
858 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7
,
859 CPU_COREI7_FLAGS
, 0 },
860 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM
,
862 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM
,
864 { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU
,
865 CPU_IAMCU_FLAGS
, 0 },
866 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6
,
868 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6
,
870 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON
,
871 CPU_ATHLON_FLAGS
, 0 },
872 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8
,
874 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8
,
876 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8
,
878 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10
,
879 CPU_AMDFAM10_FLAGS
, 0 },
880 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD
,
881 CPU_BDVER1_FLAGS
, 0 },
882 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD
,
883 CPU_BDVER2_FLAGS
, 0 },
884 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD
,
885 CPU_BDVER3_FLAGS
, 0 },
886 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD
,
887 CPU_BDVER4_FLAGS
, 0 },
888 { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER
,
889 CPU_ZNVER1_FLAGS
, 0 },
890 { STRING_COMMA_LEN ("znver2"), PROCESSOR_ZNVER
,
891 CPU_ZNVER2_FLAGS
, 0 },
892 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT
,
893 CPU_BTVER1_FLAGS
, 0 },
894 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT
,
895 CPU_BTVER2_FLAGS
, 0 },
896 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN
,
898 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN
,
900 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN
,
902 { STRING_COMMA_LEN (".687"), PROCESSOR_UNKNOWN
,
904 { STRING_COMMA_LEN (".cmov"), PROCESSOR_UNKNOWN
,
906 { STRING_COMMA_LEN (".fxsr"), PROCESSOR_UNKNOWN
,
908 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN
,
910 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN
,
912 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN
,
914 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN
,
916 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN
,
917 CPU_SSSE3_FLAGS
, 0 },
918 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN
,
919 CPU_SSE4_1_FLAGS
, 0 },
920 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN
,
921 CPU_SSE4_2_FLAGS
, 0 },
922 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN
,
923 CPU_SSE4_2_FLAGS
, 0 },
924 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN
,
926 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN
,
928 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN
,
929 CPU_AVX512F_FLAGS
, 0 },
930 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN
,
931 CPU_AVX512CD_FLAGS
, 0 },
932 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN
,
933 CPU_AVX512ER_FLAGS
, 0 },
934 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN
,
935 CPU_AVX512PF_FLAGS
, 0 },
936 { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN
,
937 CPU_AVX512DQ_FLAGS
, 0 },
938 { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN
,
939 CPU_AVX512BW_FLAGS
, 0 },
940 { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN
,
941 CPU_AVX512VL_FLAGS
, 0 },
942 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN
,
944 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN
,
945 CPU_VMFUNC_FLAGS
, 0 },
946 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN
,
948 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN
,
949 CPU_XSAVE_FLAGS
, 0 },
950 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN
,
951 CPU_XSAVEOPT_FLAGS
, 0 },
952 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN
,
953 CPU_XSAVEC_FLAGS
, 0 },
954 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN
,
955 CPU_XSAVES_FLAGS
, 0 },
956 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN
,
958 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN
,
959 CPU_PCLMUL_FLAGS
, 0 },
960 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN
,
961 CPU_PCLMUL_FLAGS
, 1 },
962 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN
,
963 CPU_FSGSBASE_FLAGS
, 0 },
964 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN
,
965 CPU_RDRND_FLAGS
, 0 },
966 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN
,
968 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN
,
970 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN
,
972 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN
,
974 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN
,
976 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN
,
978 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN
,
979 CPU_MOVBE_FLAGS
, 0 },
980 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN
,
982 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN
,
984 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN
,
985 CPU_LZCNT_FLAGS
, 0 },
986 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN
,
988 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN
,
990 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN
,
991 CPU_INVPCID_FLAGS
, 0 },
992 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN
,
993 CPU_CLFLUSH_FLAGS
, 0 },
994 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN
,
996 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN
,
997 CPU_SYSCALL_FLAGS
, 0 },
998 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN
,
999 CPU_RDTSCP_FLAGS
, 0 },
1000 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN
,
1001 CPU_3DNOW_FLAGS
, 0 },
1002 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN
,
1003 CPU_3DNOWA_FLAGS
, 0 },
1004 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN
,
1005 CPU_PADLOCK_FLAGS
, 0 },
1006 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN
,
1007 CPU_SVME_FLAGS
, 1 },
1008 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN
,
1009 CPU_SVME_FLAGS
, 0 },
1010 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN
,
1011 CPU_SSE4A_FLAGS
, 0 },
1012 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN
,
1014 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN
,
1016 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN
,
1018 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN
,
1020 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN
,
1021 CPU_RDSEED_FLAGS
, 0 },
1022 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN
,
1023 CPU_PRFCHW_FLAGS
, 0 },
1024 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN
,
1025 CPU_SMAP_FLAGS
, 0 },
1026 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN
,
1028 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN
,
1030 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN
,
1031 CPU_CLFLUSHOPT_FLAGS
, 0 },
1032 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN
,
1033 CPU_PREFETCHWT1_FLAGS
, 0 },
1034 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN
,
1036 { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN
,
1037 CPU_CLWB_FLAGS
, 0 },
1038 { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN
,
1039 CPU_AVX512IFMA_FLAGS
, 0 },
1040 { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN
,
1041 CPU_AVX512VBMI_FLAGS
, 0 },
1042 { STRING_COMMA_LEN (".avx512_4fmaps"), PROCESSOR_UNKNOWN
,
1043 CPU_AVX512_4FMAPS_FLAGS
, 0 },
1044 { STRING_COMMA_LEN (".avx512_4vnniw"), PROCESSOR_UNKNOWN
,
1045 CPU_AVX512_4VNNIW_FLAGS
, 0 },
1046 { STRING_COMMA_LEN (".avx512_vpopcntdq"), PROCESSOR_UNKNOWN
,
1047 CPU_AVX512_VPOPCNTDQ_FLAGS
, 0 },
1048 { STRING_COMMA_LEN (".avx512_vbmi2"), PROCESSOR_UNKNOWN
,
1049 CPU_AVX512_VBMI2_FLAGS
, 0 },
1050 { STRING_COMMA_LEN (".avx512_vnni"), PROCESSOR_UNKNOWN
,
1051 CPU_AVX512_VNNI_FLAGS
, 0 },
1052 { STRING_COMMA_LEN (".avx512_bitalg"), PROCESSOR_UNKNOWN
,
1053 CPU_AVX512_BITALG_FLAGS
, 0 },
1054 { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN
,
1055 CPU_CLZERO_FLAGS
, 0 },
1056 { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN
,
1057 CPU_MWAITX_FLAGS
, 0 },
1058 { STRING_COMMA_LEN (".ospke"), PROCESSOR_UNKNOWN
,
1059 CPU_OSPKE_FLAGS
, 0 },
1060 { STRING_COMMA_LEN (".rdpid"), PROCESSOR_UNKNOWN
,
1061 CPU_RDPID_FLAGS
, 0 },
1062 { STRING_COMMA_LEN (".ptwrite"), PROCESSOR_UNKNOWN
,
1063 CPU_PTWRITE_FLAGS
, 0 },
1064 { STRING_COMMA_LEN (".ibt"), PROCESSOR_UNKNOWN
,
1066 { STRING_COMMA_LEN (".shstk"), PROCESSOR_UNKNOWN
,
1067 CPU_SHSTK_FLAGS
, 0 },
1068 { STRING_COMMA_LEN (".gfni"), PROCESSOR_UNKNOWN
,
1069 CPU_GFNI_FLAGS
, 0 },
1070 { STRING_COMMA_LEN (".vaes"), PROCESSOR_UNKNOWN
,
1071 CPU_VAES_FLAGS
, 0 },
1072 { STRING_COMMA_LEN (".vpclmulqdq"), PROCESSOR_UNKNOWN
,
1073 CPU_VPCLMULQDQ_FLAGS
, 0 },
1074 { STRING_COMMA_LEN (".wbnoinvd"), PROCESSOR_UNKNOWN
,
1075 CPU_WBNOINVD_FLAGS
, 0 },
1076 { STRING_COMMA_LEN (".pconfig"), PROCESSOR_UNKNOWN
,
1077 CPU_PCONFIG_FLAGS
, 0 },
1078 { STRING_COMMA_LEN (".waitpkg"), PROCESSOR_UNKNOWN
,
1079 CPU_WAITPKG_FLAGS
, 0 },
1080 { STRING_COMMA_LEN (".cldemote"), PROCESSOR_UNKNOWN
,
1081 CPU_CLDEMOTE_FLAGS
, 0 },
1082 { STRING_COMMA_LEN (".movdiri"), PROCESSOR_UNKNOWN
,
1083 CPU_MOVDIRI_FLAGS
, 0 },
1084 { STRING_COMMA_LEN (".movdir64b"), PROCESSOR_UNKNOWN
,
1085 CPU_MOVDIR64B_FLAGS
, 0 },
1086 { STRING_COMMA_LEN (".avx512_bf16"), PROCESSOR_UNKNOWN
,
1087 CPU_AVX512_BF16_FLAGS
, 0 },
1088 { STRING_COMMA_LEN (".avx512_vp2intersect"), PROCESSOR_UNKNOWN
,
1089 CPU_AVX512_VP2INTERSECT_FLAGS
, 0 },
1090 { STRING_COMMA_LEN (".enqcmd"), PROCESSOR_UNKNOWN
,
1091 CPU_ENQCMD_FLAGS
, 0 },
1092 { STRING_COMMA_LEN (".rdpru"), PROCESSOR_UNKNOWN
,
1093 CPU_RDPRU_FLAGS
, 0 },
1094 { STRING_COMMA_LEN (".mcommit"), PROCESSOR_UNKNOWN
,
1095 CPU_MCOMMIT_FLAGS
, 0 },
1098 static const noarch_entry cpu_noarch
[] =
1100 { STRING_COMMA_LEN ("no87"), CPU_ANY_X87_FLAGS
},
1101 { STRING_COMMA_LEN ("no287"), CPU_ANY_287_FLAGS
},
1102 { STRING_COMMA_LEN ("no387"), CPU_ANY_387_FLAGS
},
1103 { STRING_COMMA_LEN ("no687"), CPU_ANY_687_FLAGS
},
1104 { STRING_COMMA_LEN ("nocmov"), CPU_ANY_CMOV_FLAGS
},
1105 { STRING_COMMA_LEN ("nofxsr"), CPU_ANY_FXSR_FLAGS
},
1106 { STRING_COMMA_LEN ("nommx"), CPU_ANY_MMX_FLAGS
},
1107 { STRING_COMMA_LEN ("nosse"), CPU_ANY_SSE_FLAGS
},
1108 { STRING_COMMA_LEN ("nosse2"), CPU_ANY_SSE2_FLAGS
},
1109 { STRING_COMMA_LEN ("nosse3"), CPU_ANY_SSE3_FLAGS
},
1110 { STRING_COMMA_LEN ("nossse3"), CPU_ANY_SSSE3_FLAGS
},
1111 { STRING_COMMA_LEN ("nosse4.1"), CPU_ANY_SSE4_1_FLAGS
},
1112 { STRING_COMMA_LEN ("nosse4.2"), CPU_ANY_SSE4_2_FLAGS
},
1113 { STRING_COMMA_LEN ("nosse4"), CPU_ANY_SSE4_1_FLAGS
},
1114 { STRING_COMMA_LEN ("noavx"), CPU_ANY_AVX_FLAGS
},
1115 { STRING_COMMA_LEN ("noavx2"), CPU_ANY_AVX2_FLAGS
},
1116 { STRING_COMMA_LEN ("noavx512f"), CPU_ANY_AVX512F_FLAGS
},
1117 { STRING_COMMA_LEN ("noavx512cd"), CPU_ANY_AVX512CD_FLAGS
},
1118 { STRING_COMMA_LEN ("noavx512er"), CPU_ANY_AVX512ER_FLAGS
},
1119 { STRING_COMMA_LEN ("noavx512pf"), CPU_ANY_AVX512PF_FLAGS
},
1120 { STRING_COMMA_LEN ("noavx512dq"), CPU_ANY_AVX512DQ_FLAGS
},
1121 { STRING_COMMA_LEN ("noavx512bw"), CPU_ANY_AVX512BW_FLAGS
},
1122 { STRING_COMMA_LEN ("noavx512vl"), CPU_ANY_AVX512VL_FLAGS
},
1123 { STRING_COMMA_LEN ("noavx512ifma"), CPU_ANY_AVX512IFMA_FLAGS
},
1124 { STRING_COMMA_LEN ("noavx512vbmi"), CPU_ANY_AVX512VBMI_FLAGS
},
1125 { STRING_COMMA_LEN ("noavx512_4fmaps"), CPU_ANY_AVX512_4FMAPS_FLAGS
},
1126 { STRING_COMMA_LEN ("noavx512_4vnniw"), CPU_ANY_AVX512_4VNNIW_FLAGS
},
1127 { STRING_COMMA_LEN ("noavx512_vpopcntdq"), CPU_ANY_AVX512_VPOPCNTDQ_FLAGS
},
1128 { STRING_COMMA_LEN ("noavx512_vbmi2"), CPU_ANY_AVX512_VBMI2_FLAGS
},
1129 { STRING_COMMA_LEN ("noavx512_vnni"), CPU_ANY_AVX512_VNNI_FLAGS
},
1130 { STRING_COMMA_LEN ("noavx512_bitalg"), CPU_ANY_AVX512_BITALG_FLAGS
},
1131 { STRING_COMMA_LEN ("noibt"), CPU_ANY_IBT_FLAGS
},
1132 { STRING_COMMA_LEN ("noshstk"), CPU_ANY_SHSTK_FLAGS
},
1133 { STRING_COMMA_LEN ("nomovdiri"), CPU_ANY_MOVDIRI_FLAGS
},
1134 { STRING_COMMA_LEN ("nomovdir64b"), CPU_ANY_MOVDIR64B_FLAGS
},
1135 { STRING_COMMA_LEN ("noavx512_bf16"), CPU_ANY_AVX512_BF16_FLAGS
},
1136 { STRING_COMMA_LEN ("noavx512_vp2intersect"), CPU_ANY_SHSTK_FLAGS
},
1137 { STRING_COMMA_LEN ("noenqcmd"), CPU_ANY_ENQCMD_FLAGS
},
1141 /* Like s_lcomm_internal in gas/read.c but the alignment string
1142 is allowed to be optional. */
1145 pe_lcomm_internal (int needs_align
, symbolS
*symbolP
, addressT size
)
1152 && *input_line_pointer
== ',')
1154 align
= parse_align (needs_align
- 1);
1156 if (align
== (addressT
) -1)
1171 bss_alloc (symbolP
, size
, align
);
1176 pe_lcomm (int needs_align
)
1178 s_comm_internal (needs_align
* 2, pe_lcomm_internal
);
1182 const pseudo_typeS md_pseudo_table
[] =
1184 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
1185 {"align", s_align_bytes
, 0},
1187 {"align", s_align_ptwo
, 0},
1189 {"arch", set_cpu_arch
, 0},
1193 {"lcomm", pe_lcomm
, 1},
1195 {"ffloat", float_cons
, 'f'},
1196 {"dfloat", float_cons
, 'd'},
1197 {"tfloat", float_cons
, 'x'},
1199 {"slong", signed_cons
, 4},
1200 {"noopt", s_ignore
, 0},
1201 {"optim", s_ignore
, 0},
1202 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
1203 {"code16", set_code_flag
, CODE_16BIT
},
1204 {"code32", set_code_flag
, CODE_32BIT
},
1206 {"code64", set_code_flag
, CODE_64BIT
},
1208 {"intel_syntax", set_intel_syntax
, 1},
1209 {"att_syntax", set_intel_syntax
, 0},
1210 {"intel_mnemonic", set_intel_mnemonic
, 1},
1211 {"att_mnemonic", set_intel_mnemonic
, 0},
1212 {"allow_index_reg", set_allow_index_reg
, 1},
1213 {"disallow_index_reg", set_allow_index_reg
, 0},
1214 {"sse_check", set_check
, 0},
1215 {"operand_check", set_check
, 1},
1216 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1217 {"largecomm", handle_large_common
, 0},
1219 {"file", dwarf2_directive_file
, 0},
1220 {"loc", dwarf2_directive_loc
, 0},
1221 {"loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0},
1224 {"secrel32", pe_directive_secrel
, 0},
1229 /* For interface with expression (). */
1230 extern char *input_line_pointer
;
1232 /* Hash table for instruction mnemonic lookup. */
1233 static struct hash_control
*op_hash
;
1235 /* Hash table for register lookup. */
1236 static struct hash_control
*reg_hash
;
1238 /* Various efficient no-op patterns for aligning code labels.
1239 Note: Don't try to assemble the instructions in the comments.
1240 0L and 0w are not legal. */
1241 static const unsigned char f32_1
[] =
1243 static const unsigned char f32_2
[] =
1244 {0x66,0x90}; /* xchg %ax,%ax */
1245 static const unsigned char f32_3
[] =
1246 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1247 static const unsigned char f32_4
[] =
1248 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1249 static const unsigned char f32_6
[] =
1250 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1251 static const unsigned char f32_7
[] =
1252 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1253 static const unsigned char f16_3
[] =
1254 {0x8d,0x74,0x00}; /* lea 0(%si),%si */
1255 static const unsigned char f16_4
[] =
1256 {0x8d,0xb4,0x00,0x00}; /* lea 0W(%si),%si */
1257 static const unsigned char jump_disp8
[] =
1258 {0xeb}; /* jmp disp8 */
1259 static const unsigned char jump32_disp32
[] =
1260 {0xe9}; /* jmp disp32 */
1261 static const unsigned char jump16_disp32
[] =
1262 {0x66,0xe9}; /* jmp disp32 */
1263 /* 32-bit NOPs patterns. */
1264 static const unsigned char *const f32_patt
[] = {
1265 f32_1
, f32_2
, f32_3
, f32_4
, NULL
, f32_6
, f32_7
1267 /* 16-bit NOPs patterns. */
1268 static const unsigned char *const f16_patt
[] = {
1269 f32_1
, f32_2
, f16_3
, f16_4
1271 /* nopl (%[re]ax) */
1272 static const unsigned char alt_3
[] =
1274 /* nopl 0(%[re]ax) */
1275 static const unsigned char alt_4
[] =
1276 {0x0f,0x1f,0x40,0x00};
1277 /* nopl 0(%[re]ax,%[re]ax,1) */
1278 static const unsigned char alt_5
[] =
1279 {0x0f,0x1f,0x44,0x00,0x00};
1280 /* nopw 0(%[re]ax,%[re]ax,1) */
1281 static const unsigned char alt_6
[] =
1282 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1283 /* nopl 0L(%[re]ax) */
1284 static const unsigned char alt_7
[] =
1285 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1286 /* nopl 0L(%[re]ax,%[re]ax,1) */
1287 static const unsigned char alt_8
[] =
1288 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1289 /* nopw 0L(%[re]ax,%[re]ax,1) */
1290 static const unsigned char alt_9
[] =
1291 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1292 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1293 static const unsigned char alt_10
[] =
1294 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1295 /* data16 nopw %cs:0L(%eax,%eax,1) */
1296 static const unsigned char alt_11
[] =
1297 {0x66,0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1298 /* 32-bit and 64-bit NOPs patterns. */
1299 static const unsigned char *const alt_patt
[] = {
1300 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
1301 alt_9
, alt_10
, alt_11
1304 /* Genenerate COUNT bytes of NOPs to WHERE from PATT with the maximum
1305 size of a single NOP instruction MAX_SINGLE_NOP_SIZE. */
1308 i386_output_nops (char *where
, const unsigned char *const *patt
,
1309 int count
, int max_single_nop_size
)
1312 /* Place the longer NOP first. */
1315 const unsigned char *nops
;
1317 if (max_single_nop_size
< 1)
1319 as_fatal (_("i386_output_nops called to generate nops of at most %d bytes!"),
1320 max_single_nop_size
);
1324 nops
= patt
[max_single_nop_size
- 1];
1326 /* Use the smaller one if the requsted one isn't available. */
1329 max_single_nop_size
--;
1330 nops
= patt
[max_single_nop_size
- 1];
1333 last
= count
% max_single_nop_size
;
1336 for (offset
= 0; offset
< count
; offset
+= max_single_nop_size
)
1337 memcpy (where
+ offset
, nops
, max_single_nop_size
);
1341 nops
= patt
[last
- 1];
1344 /* Use the smaller one plus one-byte NOP if the needed one
1347 nops
= patt
[last
- 1];
1348 memcpy (where
+ offset
, nops
, last
);
1349 where
[offset
+ last
] = *patt
[0];
1352 memcpy (where
+ offset
, nops
, last
);
1357 fits_in_imm7 (offsetT num
)
1359 return (num
& 0x7f) == num
;
1363 fits_in_imm31 (offsetT num
)
1365 return (num
& 0x7fffffff) == num
;
1368 /* Genenerate COUNT bytes of NOPs to WHERE with the maximum size of a
1369 single NOP instruction LIMIT. */
1372 i386_generate_nops (fragS
*fragP
, char *where
, offsetT count
, int limit
)
1374 const unsigned char *const *patt
= NULL
;
1375 int max_single_nop_size
;
1376 /* Maximum number of NOPs before switching to jump over NOPs. */
1377 int max_number_of_nops
;
1379 switch (fragP
->fr_type
)
1388 /* We need to decide which NOP sequence to use for 32bit and
1389 64bit. When -mtune= is used:
1391 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1392 PROCESSOR_GENERIC32, f32_patt will be used.
1393 2. For the rest, alt_patt will be used.
1395 When -mtune= isn't used, alt_patt will be used if
1396 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
1399 When -march= or .arch is used, we can't use anything beyond
1400 cpu_arch_isa_flags. */
1402 if (flag_code
== CODE_16BIT
)
1405 max_single_nop_size
= sizeof (f16_patt
) / sizeof (f16_patt
[0]);
1406 /* Limit number of NOPs to 2 in 16-bit mode. */
1407 max_number_of_nops
= 2;
1411 if (fragP
->tc_frag_data
.isa
== PROCESSOR_UNKNOWN
)
1413 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1414 switch (cpu_arch_tune
)
1416 case PROCESSOR_UNKNOWN
:
1417 /* We use cpu_arch_isa_flags to check if we SHOULD
1418 optimize with nops. */
1419 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1424 case PROCESSOR_PENTIUM4
:
1425 case PROCESSOR_NOCONA
:
1426 case PROCESSOR_CORE
:
1427 case PROCESSOR_CORE2
:
1428 case PROCESSOR_COREI7
:
1429 case PROCESSOR_L1OM
:
1430 case PROCESSOR_K1OM
:
1431 case PROCESSOR_GENERIC64
:
1433 case PROCESSOR_ATHLON
:
1435 case PROCESSOR_AMDFAM10
:
1437 case PROCESSOR_ZNVER
:
1441 case PROCESSOR_I386
:
1442 case PROCESSOR_I486
:
1443 case PROCESSOR_PENTIUM
:
1444 case PROCESSOR_PENTIUMPRO
:
1445 case PROCESSOR_IAMCU
:
1446 case PROCESSOR_GENERIC32
:
1453 switch (fragP
->tc_frag_data
.tune
)
1455 case PROCESSOR_UNKNOWN
:
1456 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1457 PROCESSOR_UNKNOWN. */
1461 case PROCESSOR_I386
:
1462 case PROCESSOR_I486
:
1463 case PROCESSOR_PENTIUM
:
1464 case PROCESSOR_IAMCU
:
1466 case PROCESSOR_ATHLON
:
1468 case PROCESSOR_AMDFAM10
:
1470 case PROCESSOR_ZNVER
:
1472 case PROCESSOR_GENERIC32
:
1473 /* We use cpu_arch_isa_flags to check if we CAN optimize
1475 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1480 case PROCESSOR_PENTIUMPRO
:
1481 case PROCESSOR_PENTIUM4
:
1482 case PROCESSOR_NOCONA
:
1483 case PROCESSOR_CORE
:
1484 case PROCESSOR_CORE2
:
1485 case PROCESSOR_COREI7
:
1486 case PROCESSOR_L1OM
:
1487 case PROCESSOR_K1OM
:
1488 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1493 case PROCESSOR_GENERIC64
:
1499 if (patt
== f32_patt
)
1501 max_single_nop_size
= sizeof (f32_patt
) / sizeof (f32_patt
[0]);
1502 /* Limit number of NOPs to 2 for older processors. */
1503 max_number_of_nops
= 2;
1507 max_single_nop_size
= sizeof (alt_patt
) / sizeof (alt_patt
[0]);
1508 /* Limit number of NOPs to 7 for newer processors. */
1509 max_number_of_nops
= 7;
1514 limit
= max_single_nop_size
;
1516 if (fragP
->fr_type
== rs_fill_nop
)
1518 /* Output NOPs for .nop directive. */
1519 if (limit
> max_single_nop_size
)
1521 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
1522 _("invalid single nop size: %d "
1523 "(expect within [0, %d])"),
1524 limit
, max_single_nop_size
);
1529 fragP
->fr_var
= count
;
1531 if ((count
/ max_single_nop_size
) > max_number_of_nops
)
1533 /* Generate jump over NOPs. */
1534 offsetT disp
= count
- 2;
1535 if (fits_in_imm7 (disp
))
1537 /* Use "jmp disp8" if possible. */
1539 where
[0] = jump_disp8
[0];
1545 unsigned int size_of_jump
;
1547 if (flag_code
== CODE_16BIT
)
1549 where
[0] = jump16_disp32
[0];
1550 where
[1] = jump16_disp32
[1];
1555 where
[0] = jump32_disp32
[0];
1559 count
-= size_of_jump
+ 4;
1560 if (!fits_in_imm31 (count
))
1562 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
1563 _("jump over nop padding out of range"));
1567 md_number_to_chars (where
+ size_of_jump
, count
, 4);
1568 where
+= size_of_jump
+ 4;
1572 /* Generate multiple NOPs. */
1573 i386_output_nops (where
, patt
, count
, limit
);
1577 operand_type_all_zero (const union i386_operand_type
*x
)
1579 switch (ARRAY_SIZE(x
->array
))
1590 return !x
->array
[0];
1597 operand_type_set (union i386_operand_type
*x
, unsigned int v
)
1599 switch (ARRAY_SIZE(x
->array
))
1615 x
->bitfield
.class = ClassNone
;
1619 operand_type_equal (const union i386_operand_type
*x
,
1620 const union i386_operand_type
*y
)
1622 switch (ARRAY_SIZE(x
->array
))
1625 if (x
->array
[2] != y
->array
[2])
1629 if (x
->array
[1] != y
->array
[1])
1633 return x
->array
[0] == y
->array
[0];
1641 cpu_flags_all_zero (const union i386_cpu_flags
*x
)
1643 switch (ARRAY_SIZE(x
->array
))
1658 return !x
->array
[0];
1665 cpu_flags_equal (const union i386_cpu_flags
*x
,
1666 const union i386_cpu_flags
*y
)
1668 switch (ARRAY_SIZE(x
->array
))
1671 if (x
->array
[3] != y
->array
[3])
1675 if (x
->array
[2] != y
->array
[2])
1679 if (x
->array
[1] != y
->array
[1])
1683 return x
->array
[0] == y
->array
[0];
1691 cpu_flags_check_cpu64 (i386_cpu_flags f
)
1693 return !((flag_code
== CODE_64BIT
&& f
.bitfield
.cpuno64
)
1694 || (flag_code
!= CODE_64BIT
&& f
.bitfield
.cpu64
));
1697 static INLINE i386_cpu_flags
1698 cpu_flags_and (i386_cpu_flags x
, i386_cpu_flags y
)
1700 switch (ARRAY_SIZE (x
.array
))
1703 x
.array
[3] &= y
.array
[3];
1706 x
.array
[2] &= y
.array
[2];
1709 x
.array
[1] &= y
.array
[1];
1712 x
.array
[0] &= y
.array
[0];
1720 static INLINE i386_cpu_flags
1721 cpu_flags_or (i386_cpu_flags x
, i386_cpu_flags y
)
1723 switch (ARRAY_SIZE (x
.array
))
1726 x
.array
[3] |= y
.array
[3];
1729 x
.array
[2] |= y
.array
[2];
1732 x
.array
[1] |= y
.array
[1];
1735 x
.array
[0] |= y
.array
[0];
1743 static INLINE i386_cpu_flags
1744 cpu_flags_and_not (i386_cpu_flags x
, i386_cpu_flags y
)
1746 switch (ARRAY_SIZE (x
.array
))
1749 x
.array
[3] &= ~y
.array
[3];
1752 x
.array
[2] &= ~y
.array
[2];
1755 x
.array
[1] &= ~y
.array
[1];
1758 x
.array
[0] &= ~y
.array
[0];
1766 #define CPU_FLAGS_ARCH_MATCH 0x1
1767 #define CPU_FLAGS_64BIT_MATCH 0x2
1769 #define CPU_FLAGS_PERFECT_MATCH \
1770 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_64BIT_MATCH)
1772 /* Return CPU flags match bits. */
1775 cpu_flags_match (const insn_template
*t
)
1777 i386_cpu_flags x
= t
->cpu_flags
;
1778 int match
= cpu_flags_check_cpu64 (x
) ? CPU_FLAGS_64BIT_MATCH
: 0;
1780 x
.bitfield
.cpu64
= 0;
1781 x
.bitfield
.cpuno64
= 0;
1783 if (cpu_flags_all_zero (&x
))
1785 /* This instruction is available on all archs. */
1786 match
|= CPU_FLAGS_ARCH_MATCH
;
1790 /* This instruction is available only on some archs. */
1791 i386_cpu_flags cpu
= cpu_arch_flags
;
1793 /* AVX512VL is no standalone feature - match it and then strip it. */
1794 if (x
.bitfield
.cpuavx512vl
&& !cpu
.bitfield
.cpuavx512vl
)
1796 x
.bitfield
.cpuavx512vl
= 0;
1798 cpu
= cpu_flags_and (x
, cpu
);
1799 if (!cpu_flags_all_zero (&cpu
))
1801 if (x
.bitfield
.cpuavx
)
1803 /* We need to check a few extra flags with AVX. */
1804 if (cpu
.bitfield
.cpuavx
1805 && (!t
->opcode_modifier
.sse2avx
|| sse2avx
)
1806 && (!x
.bitfield
.cpuaes
|| cpu
.bitfield
.cpuaes
)
1807 && (!x
.bitfield
.cpugfni
|| cpu
.bitfield
.cpugfni
)
1808 && (!x
.bitfield
.cpupclmul
|| cpu
.bitfield
.cpupclmul
))
1809 match
|= CPU_FLAGS_ARCH_MATCH
;
1811 else if (x
.bitfield
.cpuavx512f
)
1813 /* We need to check a few extra flags with AVX512F. */
1814 if (cpu
.bitfield
.cpuavx512f
1815 && (!x
.bitfield
.cpugfni
|| cpu
.bitfield
.cpugfni
)
1816 && (!x
.bitfield
.cpuvaes
|| cpu
.bitfield
.cpuvaes
)
1817 && (!x
.bitfield
.cpuvpclmulqdq
|| cpu
.bitfield
.cpuvpclmulqdq
))
1818 match
|= CPU_FLAGS_ARCH_MATCH
;
1821 match
|= CPU_FLAGS_ARCH_MATCH
;
1827 static INLINE i386_operand_type
1828 operand_type_and (i386_operand_type x
, i386_operand_type y
)
1830 if (x
.bitfield
.class != y
.bitfield
.class)
1831 x
.bitfield
.class = ClassNone
;
1833 switch (ARRAY_SIZE (x
.array
))
1836 x
.array
[2] &= y
.array
[2];
1839 x
.array
[1] &= y
.array
[1];
1842 x
.array
[0] &= y
.array
[0];
1850 static INLINE i386_operand_type
1851 operand_type_and_not (i386_operand_type x
, i386_operand_type y
)
1853 gas_assert (y
.bitfield
.class == ClassNone
);
1855 switch (ARRAY_SIZE (x
.array
))
1858 x
.array
[2] &= ~y
.array
[2];
1861 x
.array
[1] &= ~y
.array
[1];
1864 x
.array
[0] &= ~y
.array
[0];
1872 static INLINE i386_operand_type
1873 operand_type_or (i386_operand_type x
, i386_operand_type y
)
1875 gas_assert (x
.bitfield
.class == ClassNone
||
1876 y
.bitfield
.class == ClassNone
||
1877 x
.bitfield
.class == y
.bitfield
.class);
1879 switch (ARRAY_SIZE (x
.array
))
1882 x
.array
[2] |= y
.array
[2];
1885 x
.array
[1] |= y
.array
[1];
1888 x
.array
[0] |= y
.array
[0];
1896 static INLINE i386_operand_type
1897 operand_type_xor (i386_operand_type x
, i386_operand_type y
)
1899 gas_assert (y
.bitfield
.class == ClassNone
);
1901 switch (ARRAY_SIZE (x
.array
))
1904 x
.array
[2] ^= y
.array
[2];
1907 x
.array
[1] ^= y
.array
[1];
1910 x
.array
[0] ^= y
.array
[0];
1918 static const i386_operand_type disp16
= OPERAND_TYPE_DISP16
;
1919 static const i386_operand_type disp32
= OPERAND_TYPE_DISP32
;
1920 static const i386_operand_type disp32s
= OPERAND_TYPE_DISP32S
;
1921 static const i386_operand_type disp16_32
= OPERAND_TYPE_DISP16_32
;
1922 static const i386_operand_type anydisp
= OPERAND_TYPE_ANYDISP
;
1923 static const i386_operand_type anyimm
= OPERAND_TYPE_ANYIMM
;
1924 static const i386_operand_type regxmm
= OPERAND_TYPE_REGXMM
;
1925 static const i386_operand_type regmask
= OPERAND_TYPE_REGMASK
;
1926 static const i386_operand_type imm8
= OPERAND_TYPE_IMM8
;
1927 static const i386_operand_type imm8s
= OPERAND_TYPE_IMM8S
;
1928 static const i386_operand_type imm16
= OPERAND_TYPE_IMM16
;
1929 static const i386_operand_type imm32
= OPERAND_TYPE_IMM32
;
1930 static const i386_operand_type imm32s
= OPERAND_TYPE_IMM32S
;
1931 static const i386_operand_type imm64
= OPERAND_TYPE_IMM64
;
1932 static const i386_operand_type imm16_32
= OPERAND_TYPE_IMM16_32
;
1933 static const i386_operand_type imm16_32s
= OPERAND_TYPE_IMM16_32S
;
1934 static const i386_operand_type imm16_32_32s
= OPERAND_TYPE_IMM16_32_32S
;
1945 operand_type_check (i386_operand_type t
, enum operand_type c
)
1950 return t
.bitfield
.class == Reg
;
1953 return (t
.bitfield
.imm8
1957 || t
.bitfield
.imm32s
1958 || t
.bitfield
.imm64
);
1961 return (t
.bitfield
.disp8
1962 || t
.bitfield
.disp16
1963 || t
.bitfield
.disp32
1964 || t
.bitfield
.disp32s
1965 || t
.bitfield
.disp64
);
1968 return (t
.bitfield
.disp8
1969 || t
.bitfield
.disp16
1970 || t
.bitfield
.disp32
1971 || t
.bitfield
.disp32s
1972 || t
.bitfield
.disp64
1973 || t
.bitfield
.baseindex
);
1982 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit/80bit size
1983 between operand GIVEN and opeand WANTED for instruction template T. */
1986 match_operand_size (const insn_template
*t
, unsigned int wanted
,
1989 return !((i
.types
[given
].bitfield
.byte
1990 && !t
->operand_types
[wanted
].bitfield
.byte
)
1991 || (i
.types
[given
].bitfield
.word
1992 && !t
->operand_types
[wanted
].bitfield
.word
)
1993 || (i
.types
[given
].bitfield
.dword
1994 && !t
->operand_types
[wanted
].bitfield
.dword
)
1995 || (i
.types
[given
].bitfield
.qword
1996 && !t
->operand_types
[wanted
].bitfield
.qword
)
1997 || (i
.types
[given
].bitfield
.tbyte
1998 && !t
->operand_types
[wanted
].bitfield
.tbyte
));
2001 /* Return 1 if there is no conflict in SIMD register between operand
2002 GIVEN and opeand WANTED for instruction template T. */
2005 match_simd_size (const insn_template
*t
, unsigned int wanted
,
2008 return !((i
.types
[given
].bitfield
.xmmword
2009 && !t
->operand_types
[wanted
].bitfield
.xmmword
)
2010 || (i
.types
[given
].bitfield
.ymmword
2011 && !t
->operand_types
[wanted
].bitfield
.ymmword
)
2012 || (i
.types
[given
].bitfield
.zmmword
2013 && !t
->operand_types
[wanted
].bitfield
.zmmword
));
2016 /* Return 1 if there is no conflict in any size between operand GIVEN
2017 and opeand WANTED for instruction template T. */
2020 match_mem_size (const insn_template
*t
, unsigned int wanted
,
2023 return (match_operand_size (t
, wanted
, given
)
2024 && !((i
.types
[given
].bitfield
.unspecified
2026 && !t
->operand_types
[wanted
].bitfield
.unspecified
)
2027 || (i
.types
[given
].bitfield
.fword
2028 && !t
->operand_types
[wanted
].bitfield
.fword
)
2029 /* For scalar opcode templates to allow register and memory
2030 operands at the same time, some special casing is needed
2031 here. Also for v{,p}broadcast*, {,v}pmov{s,z}*, and
2032 down-conversion vpmov*. */
2033 || ((t
->operand_types
[wanted
].bitfield
.class == RegSIMD
2034 && !t
->opcode_modifier
.broadcast
2035 && (t
->operand_types
[wanted
].bitfield
.byte
2036 || t
->operand_types
[wanted
].bitfield
.word
2037 || t
->operand_types
[wanted
].bitfield
.dword
2038 || t
->operand_types
[wanted
].bitfield
.qword
))
2039 ? (i
.types
[given
].bitfield
.xmmword
2040 || i
.types
[given
].bitfield
.ymmword
2041 || i
.types
[given
].bitfield
.zmmword
)
2042 : !match_simd_size(t
, wanted
, given
))));
2045 /* Return value has MATCH_STRAIGHT set if there is no size conflict on any
2046 operands for instruction template T, and it has MATCH_REVERSE set if there
2047 is no size conflict on any operands for the template with operands reversed
2048 (and the template allows for reversing in the first place). */
2050 #define MATCH_STRAIGHT 1
2051 #define MATCH_REVERSE 2
2053 static INLINE
unsigned int
2054 operand_size_match (const insn_template
*t
)
2056 unsigned int j
, match
= MATCH_STRAIGHT
;
2058 /* Don't check jump instructions. */
2059 if (t
->opcode_modifier
.jump
2060 || t
->opcode_modifier
.jumpbyte
2061 || t
->opcode_modifier
.jumpdword
2062 || t
->opcode_modifier
.jumpintersegment
)
2065 /* Check memory and accumulator operand size. */
2066 for (j
= 0; j
< i
.operands
; j
++)
2068 if (i
.types
[j
].bitfield
.class != Reg
2069 && i
.types
[j
].bitfield
.class != RegSIMD
2070 && t
->operand_types
[j
].bitfield
.anysize
)
2073 if (t
->operand_types
[j
].bitfield
.class == Reg
2074 && !match_operand_size (t
, j
, j
))
2080 if (t
->operand_types
[j
].bitfield
.class == RegSIMD
2081 && !match_simd_size (t
, j
, j
))
2087 if (t
->operand_types
[j
].bitfield
.acc
2088 && (!match_operand_size (t
, j
, j
) || !match_simd_size (t
, j
, j
)))
2094 if ((i
.flags
[j
] & Operand_Mem
) && !match_mem_size (t
, j
, j
))
2101 if (!t
->opcode_modifier
.d
)
2105 i
.error
= operand_size_mismatch
;
2109 /* Check reverse. */
2110 gas_assert (i
.operands
>= 2 && i
.operands
<= 3);
2112 for (j
= 0; j
< i
.operands
; j
++)
2114 unsigned int given
= i
.operands
- j
- 1;
2116 if (t
->operand_types
[j
].bitfield
.class == Reg
2117 && !match_operand_size (t
, j
, given
))
2120 if (t
->operand_types
[j
].bitfield
.class == RegSIMD
2121 && !match_simd_size (t
, j
, given
))
2124 if (t
->operand_types
[j
].bitfield
.acc
2125 && (!match_operand_size (t
, j
, given
)
2126 || !match_simd_size (t
, j
, given
)))
2129 if ((i
.flags
[given
] & Operand_Mem
) && !match_mem_size (t
, j
, given
))
2133 return match
| MATCH_REVERSE
;
2137 operand_type_match (i386_operand_type overlap
,
2138 i386_operand_type given
)
2140 i386_operand_type temp
= overlap
;
2142 temp
.bitfield
.jumpabsolute
= 0;
2143 temp
.bitfield
.unspecified
= 0;
2144 temp
.bitfield
.byte
= 0;
2145 temp
.bitfield
.word
= 0;
2146 temp
.bitfield
.dword
= 0;
2147 temp
.bitfield
.fword
= 0;
2148 temp
.bitfield
.qword
= 0;
2149 temp
.bitfield
.tbyte
= 0;
2150 temp
.bitfield
.xmmword
= 0;
2151 temp
.bitfield
.ymmword
= 0;
2152 temp
.bitfield
.zmmword
= 0;
2153 if (operand_type_all_zero (&temp
))
2156 if (given
.bitfield
.baseindex
== overlap
.bitfield
.baseindex
2157 && given
.bitfield
.jumpabsolute
== overlap
.bitfield
.jumpabsolute
)
2161 i
.error
= operand_type_mismatch
;
2165 /* If given types g0 and g1 are registers they must be of the same type
2166 unless the expected operand type register overlap is null.
2167 Memory operand size of certain SIMD instructions is also being checked
2171 operand_type_register_match (i386_operand_type g0
,
2172 i386_operand_type t0
,
2173 i386_operand_type g1
,
2174 i386_operand_type t1
)
2176 if (g0
.bitfield
.class != Reg
2177 && g0
.bitfield
.class != RegSIMD
2178 && (!operand_type_check (g0
, anymem
)
2179 || g0
.bitfield
.unspecified
2180 || t0
.bitfield
.class != RegSIMD
))
2183 if (g1
.bitfield
.class != Reg
2184 && g1
.bitfield
.class != RegSIMD
2185 && (!operand_type_check (g1
, anymem
)
2186 || g1
.bitfield
.unspecified
2187 || t1
.bitfield
.class != RegSIMD
))
2190 if (g0
.bitfield
.byte
== g1
.bitfield
.byte
2191 && g0
.bitfield
.word
== g1
.bitfield
.word
2192 && g0
.bitfield
.dword
== g1
.bitfield
.dword
2193 && g0
.bitfield
.qword
== g1
.bitfield
.qword
2194 && g0
.bitfield
.xmmword
== g1
.bitfield
.xmmword
2195 && g0
.bitfield
.ymmword
== g1
.bitfield
.ymmword
2196 && g0
.bitfield
.zmmword
== g1
.bitfield
.zmmword
)
2199 if (!(t0
.bitfield
.byte
& t1
.bitfield
.byte
)
2200 && !(t0
.bitfield
.word
& t1
.bitfield
.word
)
2201 && !(t0
.bitfield
.dword
& t1
.bitfield
.dword
)
2202 && !(t0
.bitfield
.qword
& t1
.bitfield
.qword
)
2203 && !(t0
.bitfield
.xmmword
& t1
.bitfield
.xmmword
)
2204 && !(t0
.bitfield
.ymmword
& t1
.bitfield
.ymmword
)
2205 && !(t0
.bitfield
.zmmword
& t1
.bitfield
.zmmword
))
2208 i
.error
= register_type_mismatch
;
2213 static INLINE
unsigned int
2214 register_number (const reg_entry
*r
)
2216 unsigned int nr
= r
->reg_num
;
2218 if (r
->reg_flags
& RegRex
)
2221 if (r
->reg_flags
& RegVRex
)
2227 static INLINE
unsigned int
2228 mode_from_disp_size (i386_operand_type t
)
2230 if (t
.bitfield
.disp8
)
2232 else if (t
.bitfield
.disp16
2233 || t
.bitfield
.disp32
2234 || t
.bitfield
.disp32s
)
2241 fits_in_signed_byte (addressT num
)
2243 return num
+ 0x80 <= 0xff;
2247 fits_in_unsigned_byte (addressT num
)
2253 fits_in_unsigned_word (addressT num
)
2255 return num
<= 0xffff;
2259 fits_in_signed_word (addressT num
)
2261 return num
+ 0x8000 <= 0xffff;
2265 fits_in_signed_long (addressT num ATTRIBUTE_UNUSED
)
2270 return num
+ 0x80000000 <= 0xffffffff;
2272 } /* fits_in_signed_long() */
2275 fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED
)
2280 return num
<= 0xffffffff;
2282 } /* fits_in_unsigned_long() */
2285 fits_in_disp8 (offsetT num
)
2287 int shift
= i
.memshift
;
2293 mask
= (1 << shift
) - 1;
2295 /* Return 0 if NUM isn't properly aligned. */
2299 /* Check if NUM will fit in 8bit after shift. */
2300 return fits_in_signed_byte (num
>> shift
);
2304 fits_in_imm4 (offsetT num
)
2306 return (num
& 0xf) == num
;
2309 static i386_operand_type
2310 smallest_imm_type (offsetT num
)
2312 i386_operand_type t
;
2314 operand_type_set (&t
, 0);
2315 t
.bitfield
.imm64
= 1;
2317 if (cpu_arch_tune
!= PROCESSOR_I486
&& num
== 1)
2319 /* This code is disabled on the 486 because all the Imm1 forms
2320 in the opcode table are slower on the i486. They're the
2321 versions with the implicitly specified single-position
2322 displacement, which has another syntax if you really want to
2324 t
.bitfield
.imm1
= 1;
2325 t
.bitfield
.imm8
= 1;
2326 t
.bitfield
.imm8s
= 1;
2327 t
.bitfield
.imm16
= 1;
2328 t
.bitfield
.imm32
= 1;
2329 t
.bitfield
.imm32s
= 1;
2331 else if (fits_in_signed_byte (num
))
2333 t
.bitfield
.imm8
= 1;
2334 t
.bitfield
.imm8s
= 1;
2335 t
.bitfield
.imm16
= 1;
2336 t
.bitfield
.imm32
= 1;
2337 t
.bitfield
.imm32s
= 1;
2339 else if (fits_in_unsigned_byte (num
))
2341 t
.bitfield
.imm8
= 1;
2342 t
.bitfield
.imm16
= 1;
2343 t
.bitfield
.imm32
= 1;
2344 t
.bitfield
.imm32s
= 1;
2346 else if (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
2348 t
.bitfield
.imm16
= 1;
2349 t
.bitfield
.imm32
= 1;
2350 t
.bitfield
.imm32s
= 1;
2352 else if (fits_in_signed_long (num
))
2354 t
.bitfield
.imm32
= 1;
2355 t
.bitfield
.imm32s
= 1;
2357 else if (fits_in_unsigned_long (num
))
2358 t
.bitfield
.imm32
= 1;
2364 offset_in_range (offsetT val
, int size
)
2370 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
2371 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
2372 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
2374 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
2380 /* If BFD64, sign extend val for 32bit address mode. */
2381 if (flag_code
!= CODE_64BIT
2382 || i
.prefix
[ADDR_PREFIX
])
2383 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
2384 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
2387 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
2389 char buf1
[40], buf2
[40];
2391 sprint_value (buf1
, val
);
2392 sprint_value (buf2
, val
& mask
);
2393 as_warn (_("%s shortened to %s"), buf1
, buf2
);
2408 a. PREFIX_EXIST if attempting to add a prefix where one from the
2409 same class already exists.
2410 b. PREFIX_LOCK if lock prefix is added.
2411 c. PREFIX_REP if rep/repne prefix is added.
2412 d. PREFIX_DS if ds prefix is added.
2413 e. PREFIX_OTHER if other prefix is added.
2416 static enum PREFIX_GROUP
2417 add_prefix (unsigned int prefix
)
2419 enum PREFIX_GROUP ret
= PREFIX_OTHER
;
2422 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
2423 && flag_code
== CODE_64BIT
)
2425 if ((i
.prefix
[REX_PREFIX
] & prefix
& REX_W
)
2426 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_R
)
2427 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_X
)
2428 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_B
))
2439 case DS_PREFIX_OPCODE
:
2442 case CS_PREFIX_OPCODE
:
2443 case ES_PREFIX_OPCODE
:
2444 case FS_PREFIX_OPCODE
:
2445 case GS_PREFIX_OPCODE
:
2446 case SS_PREFIX_OPCODE
:
2450 case REPNE_PREFIX_OPCODE
:
2451 case REPE_PREFIX_OPCODE
:
2456 case LOCK_PREFIX_OPCODE
:
2465 case ADDR_PREFIX_OPCODE
:
2469 case DATA_PREFIX_OPCODE
:
2473 if (i
.prefix
[q
] != 0)
2481 i
.prefix
[q
] |= prefix
;
2484 as_bad (_("same type of prefix used twice"));
2490 update_code_flag (int value
, int check
)
2492 PRINTF_LIKE ((*as_error
));
2494 flag_code
= (enum flag_code
) value
;
2495 if (flag_code
== CODE_64BIT
)
2497 cpu_arch_flags
.bitfield
.cpu64
= 1;
2498 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2502 cpu_arch_flags
.bitfield
.cpu64
= 0;
2503 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2505 if (value
== CODE_64BIT
&& !cpu_arch_flags
.bitfield
.cpulm
)
2508 as_error
= as_fatal
;
2511 (*as_error
) (_("64bit mode not supported on `%s'."),
2512 cpu_arch_name
? cpu_arch_name
: default_arch
);
2514 if (value
== CODE_32BIT
&& !cpu_arch_flags
.bitfield
.cpui386
)
2517 as_error
= as_fatal
;
2520 (*as_error
) (_("32bit mode not supported on `%s'."),
2521 cpu_arch_name
? cpu_arch_name
: default_arch
);
2523 stackop_size
= '\0';
2527 set_code_flag (int value
)
2529 update_code_flag (value
, 0);
2533 set_16bit_gcc_code_flag (int new_code_flag
)
2535 flag_code
= (enum flag_code
) new_code_flag
;
2536 if (flag_code
!= CODE_16BIT
)
2538 cpu_arch_flags
.bitfield
.cpu64
= 0;
2539 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2540 stackop_size
= LONG_MNEM_SUFFIX
;
2544 set_intel_syntax (int syntax_flag
)
2546 /* Find out if register prefixing is specified. */
2547 int ask_naked_reg
= 0;
2550 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2553 int e
= get_symbol_name (&string
);
2555 if (strcmp (string
, "prefix") == 0)
2557 else if (strcmp (string
, "noprefix") == 0)
2560 as_bad (_("bad argument to syntax directive."));
2561 (void) restore_line_pointer (e
);
2563 demand_empty_rest_of_line ();
2565 intel_syntax
= syntax_flag
;
2567 if (ask_naked_reg
== 0)
2568 allow_naked_reg
= (intel_syntax
2569 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
2571 allow_naked_reg
= (ask_naked_reg
< 0);
2573 expr_set_rank (O_full_ptr
, syntax_flag
? 10 : 0);
2575 identifier_chars
['%'] = intel_syntax
&& allow_naked_reg
? '%' : 0;
2576 identifier_chars
['$'] = intel_syntax
? '$' : 0;
2577 register_prefix
= allow_naked_reg
? "" : "%";
2581 set_intel_mnemonic (int mnemonic_flag
)
2583 intel_mnemonic
= mnemonic_flag
;
2587 set_allow_index_reg (int flag
)
2589 allow_index_reg
= flag
;
2593 set_check (int what
)
2595 enum check_kind
*kind
;
2600 kind
= &operand_check
;
2611 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2614 int e
= get_symbol_name (&string
);
2616 if (strcmp (string
, "none") == 0)
2618 else if (strcmp (string
, "warning") == 0)
2619 *kind
= check_warning
;
2620 else if (strcmp (string
, "error") == 0)
2621 *kind
= check_error
;
2623 as_bad (_("bad argument to %s_check directive."), str
);
2624 (void) restore_line_pointer (e
);
2627 as_bad (_("missing argument for %s_check directive"), str
);
2629 demand_empty_rest_of_line ();
2633 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED
,
2634 i386_cpu_flags new_flag ATTRIBUTE_UNUSED
)
2636 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2637 static const char *arch
;
2639 /* Intel LIOM is only supported on ELF. */
2645 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2646 use default_arch. */
2647 arch
= cpu_arch_name
;
2649 arch
= default_arch
;
2652 /* If we are targeting Intel MCU, we must enable it. */
2653 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_IAMCU
2654 || new_flag
.bitfield
.cpuiamcu
)
2657 /* If we are targeting Intel L1OM, we must enable it. */
2658 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_L1OM
2659 || new_flag
.bitfield
.cpul1om
)
2662 /* If we are targeting Intel K1OM, we must enable it. */
2663 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_K1OM
2664 || new_flag
.bitfield
.cpuk1om
)
2667 as_bad (_("`%s' is not supported on `%s'"), name
, arch
);
2672 set_cpu_arch (int dummy ATTRIBUTE_UNUSED
)
2676 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2679 int e
= get_symbol_name (&string
);
2681 i386_cpu_flags flags
;
2683 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
2685 if (strcmp (string
, cpu_arch
[j
].name
) == 0)
2687 check_cpu_arch_compatible (string
, cpu_arch
[j
].flags
);
2691 cpu_arch_name
= cpu_arch
[j
].name
;
2692 cpu_sub_arch_name
= NULL
;
2693 cpu_arch_flags
= cpu_arch
[j
].flags
;
2694 if (flag_code
== CODE_64BIT
)
2696 cpu_arch_flags
.bitfield
.cpu64
= 1;
2697 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2701 cpu_arch_flags
.bitfield
.cpu64
= 0;
2702 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2704 cpu_arch_isa
= cpu_arch
[j
].type
;
2705 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
2706 if (!cpu_arch_tune_set
)
2708 cpu_arch_tune
= cpu_arch_isa
;
2709 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
2714 flags
= cpu_flags_or (cpu_arch_flags
,
2717 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2719 if (cpu_sub_arch_name
)
2721 char *name
= cpu_sub_arch_name
;
2722 cpu_sub_arch_name
= concat (name
,
2724 (const char *) NULL
);
2728 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
2729 cpu_arch_flags
= flags
;
2730 cpu_arch_isa_flags
= flags
;
2734 = cpu_flags_or (cpu_arch_isa_flags
,
2736 (void) restore_line_pointer (e
);
2737 demand_empty_rest_of_line ();
2742 if (*string
== '.' && j
>= ARRAY_SIZE (cpu_arch
))
2744 /* Disable an ISA extension. */
2745 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
2746 if (strcmp (string
+ 1, cpu_noarch
[j
].name
) == 0)
2748 flags
= cpu_flags_and_not (cpu_arch_flags
,
2749 cpu_noarch
[j
].flags
);
2750 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2752 if (cpu_sub_arch_name
)
2754 char *name
= cpu_sub_arch_name
;
2755 cpu_sub_arch_name
= concat (name
, string
,
2756 (const char *) NULL
);
2760 cpu_sub_arch_name
= xstrdup (string
);
2761 cpu_arch_flags
= flags
;
2762 cpu_arch_isa_flags
= flags
;
2764 (void) restore_line_pointer (e
);
2765 demand_empty_rest_of_line ();
2769 j
= ARRAY_SIZE (cpu_arch
);
2772 if (j
>= ARRAY_SIZE (cpu_arch
))
2773 as_bad (_("no such architecture: `%s'"), string
);
2775 *input_line_pointer
= e
;
2778 as_bad (_("missing cpu architecture"));
2780 no_cond_jump_promotion
= 0;
2781 if (*input_line_pointer
== ','
2782 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
2787 ++input_line_pointer
;
2788 e
= get_symbol_name (&string
);
2790 if (strcmp (string
, "nojumps") == 0)
2791 no_cond_jump_promotion
= 1;
2792 else if (strcmp (string
, "jumps") == 0)
2795 as_bad (_("no such architecture modifier: `%s'"), string
);
2797 (void) restore_line_pointer (e
);
2800 demand_empty_rest_of_line ();
2803 enum bfd_architecture
2806 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2808 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2809 || flag_code
!= CODE_64BIT
)
2810 as_fatal (_("Intel L1OM is 64bit ELF only"));
2811 return bfd_arch_l1om
;
2813 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2815 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2816 || flag_code
!= CODE_64BIT
)
2817 as_fatal (_("Intel K1OM is 64bit ELF only"));
2818 return bfd_arch_k1om
;
2820 else if (cpu_arch_isa
== PROCESSOR_IAMCU
)
2822 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2823 || flag_code
== CODE_64BIT
)
2824 as_fatal (_("Intel MCU is 32bit ELF only"));
2825 return bfd_arch_iamcu
;
2828 return bfd_arch_i386
;
2834 if (!strncmp (default_arch
, "x86_64", 6))
2836 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2838 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2839 || default_arch
[6] != '\0')
2840 as_fatal (_("Intel L1OM is 64bit ELF only"));
2841 return bfd_mach_l1om
;
2843 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2845 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2846 || default_arch
[6] != '\0')
2847 as_fatal (_("Intel K1OM is 64bit ELF only"));
2848 return bfd_mach_k1om
;
2850 else if (default_arch
[6] == '\0')
2851 return bfd_mach_x86_64
;
2853 return bfd_mach_x64_32
;
2855 else if (!strcmp (default_arch
, "i386")
2856 || !strcmp (default_arch
, "iamcu"))
2858 if (cpu_arch_isa
== PROCESSOR_IAMCU
)
2860 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
2861 as_fatal (_("Intel MCU is 32bit ELF only"));
2862 return bfd_mach_i386_iamcu
;
2865 return bfd_mach_i386_i386
;
2868 as_fatal (_("unknown architecture"));
2874 const char *hash_err
;
2876 /* Support pseudo prefixes like {disp32}. */
2877 lex_type
['{'] = LEX_BEGIN_NAME
;
2879 /* Initialize op_hash hash table. */
2880 op_hash
= hash_new ();
2883 const insn_template
*optab
;
2884 templates
*core_optab
;
2886 /* Setup for loop. */
2888 core_optab
= XNEW (templates
);
2889 core_optab
->start
= optab
;
2894 if (optab
->name
== NULL
2895 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
2897 /* different name --> ship out current template list;
2898 add to hash table; & begin anew. */
2899 core_optab
->end
= optab
;
2900 hash_err
= hash_insert (op_hash
,
2902 (void *) core_optab
);
2905 as_fatal (_("can't hash %s: %s"),
2909 if (optab
->name
== NULL
)
2911 core_optab
= XNEW (templates
);
2912 core_optab
->start
= optab
;
2917 /* Initialize reg_hash hash table. */
2918 reg_hash
= hash_new ();
2920 const reg_entry
*regtab
;
2921 unsigned int regtab_size
= i386_regtab_size
;
2923 for (regtab
= i386_regtab
; regtab_size
--; regtab
++)
2925 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (void *) regtab
);
2927 as_fatal (_("can't hash %s: %s"),
2933 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
2938 for (c
= 0; c
< 256; c
++)
2943 mnemonic_chars
[c
] = c
;
2944 register_chars
[c
] = c
;
2945 operand_chars
[c
] = c
;
2947 else if (ISLOWER (c
))
2949 mnemonic_chars
[c
] = c
;
2950 register_chars
[c
] = c
;
2951 operand_chars
[c
] = c
;
2953 else if (ISUPPER (c
))
2955 mnemonic_chars
[c
] = TOLOWER (c
);
2956 register_chars
[c
] = mnemonic_chars
[c
];
2957 operand_chars
[c
] = c
;
2959 else if (c
== '{' || c
== '}')
2961 mnemonic_chars
[c
] = c
;
2962 operand_chars
[c
] = c
;
2965 if (ISALPHA (c
) || ISDIGIT (c
))
2966 identifier_chars
[c
] = c
;
2969 identifier_chars
[c
] = c
;
2970 operand_chars
[c
] = c
;
2975 identifier_chars
['@'] = '@';
2978 identifier_chars
['?'] = '?';
2979 operand_chars
['?'] = '?';
2981 digit_chars
['-'] = '-';
2982 mnemonic_chars
['_'] = '_';
2983 mnemonic_chars
['-'] = '-';
2984 mnemonic_chars
['.'] = '.';
2985 identifier_chars
['_'] = '_';
2986 identifier_chars
['.'] = '.';
2988 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
2989 operand_chars
[(unsigned char) *p
] = *p
;
2992 if (flag_code
== CODE_64BIT
)
2994 #if defined (OBJ_COFF) && defined (TE_PE)
2995 x86_dwarf2_return_column
= (OUTPUT_FLAVOR
== bfd_target_coff_flavour
2998 x86_dwarf2_return_column
= 16;
3000 x86_cie_data_alignment
= -8;
3004 x86_dwarf2_return_column
= 8;
3005 x86_cie_data_alignment
= -4;
3010 i386_print_statistics (FILE *file
)
3012 hash_print_statistics (file
, "i386 opcode", op_hash
);
3013 hash_print_statistics (file
, "i386 register", reg_hash
);
3018 /* Debugging routines for md_assemble. */
3019 static void pte (insn_template
*);
3020 static void pt (i386_operand_type
);
3021 static void pe (expressionS
*);
3022 static void ps (symbolS
*);
3025 pi (const char *line
, i386_insn
*x
)
3029 fprintf (stdout
, "%s: template ", line
);
3031 fprintf (stdout
, " address: base %s index %s scale %x\n",
3032 x
->base_reg
? x
->base_reg
->reg_name
: "none",
3033 x
->index_reg
? x
->index_reg
->reg_name
: "none",
3034 x
->log2_scale_factor
);
3035 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
3036 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
3037 fprintf (stdout
, " sib: base %x index %x scale %x\n",
3038 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
3039 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
3040 (x
->rex
& REX_W
) != 0,
3041 (x
->rex
& REX_R
) != 0,
3042 (x
->rex
& REX_X
) != 0,
3043 (x
->rex
& REX_B
) != 0);
3044 for (j
= 0; j
< x
->operands
; j
++)
3046 fprintf (stdout
, " #%d: ", j
+ 1);
3048 fprintf (stdout
, "\n");
3049 if (x
->types
[j
].bitfield
.class == Reg
3050 || x
->types
[j
].bitfield
.class == RegMMX
3051 || x
->types
[j
].bitfield
.class == RegSIMD
3052 || x
->types
[j
].bitfield
.class == SReg
3053 || x
->types
[j
].bitfield
.class == RegCR
3054 || x
->types
[j
].bitfield
.class == RegDR
3055 || x
->types
[j
].bitfield
.class == RegTR
)
3056 fprintf (stdout
, "%s\n", x
->op
[j
].regs
->reg_name
);
3057 if (operand_type_check (x
->types
[j
], imm
))
3059 if (operand_type_check (x
->types
[j
], disp
))
3060 pe (x
->op
[j
].disps
);
3065 pte (insn_template
*t
)
3068 fprintf (stdout
, " %d operands ", t
->operands
);
3069 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
3070 if (t
->extension_opcode
!= None
)
3071 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
3072 if (t
->opcode_modifier
.d
)
3073 fprintf (stdout
, "D");
3074 if (t
->opcode_modifier
.w
)
3075 fprintf (stdout
, "W");
3076 fprintf (stdout
, "\n");
3077 for (j
= 0; j
< t
->operands
; j
++)
3079 fprintf (stdout
, " #%d type ", j
+ 1);
3080 pt (t
->operand_types
[j
]);
3081 fprintf (stdout
, "\n");
3088 fprintf (stdout
, " operation %d\n", e
->X_op
);
3089 fprintf (stdout
, " add_number %ld (%lx)\n",
3090 (long) e
->X_add_number
, (long) e
->X_add_number
);
3091 if (e
->X_add_symbol
)
3093 fprintf (stdout
, " add_symbol ");
3094 ps (e
->X_add_symbol
);
3095 fprintf (stdout
, "\n");
3099 fprintf (stdout
, " op_symbol ");
3100 ps (e
->X_op_symbol
);
3101 fprintf (stdout
, "\n");
3108 fprintf (stdout
, "%s type %s%s",
3110 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
3111 segment_name (S_GET_SEGMENT (s
)));
3114 static struct type_name
3116 i386_operand_type mask
;
3119 const type_names
[] =
3121 { OPERAND_TYPE_REG8
, "r8" },
3122 { OPERAND_TYPE_REG16
, "r16" },
3123 { OPERAND_TYPE_REG32
, "r32" },
3124 { OPERAND_TYPE_REG64
, "r64" },
3125 { OPERAND_TYPE_ACC8
, "acc8" },
3126 { OPERAND_TYPE_ACC16
, "acc16" },
3127 { OPERAND_TYPE_ACC32
, "acc32" },
3128 { OPERAND_TYPE_ACC64
, "acc64" },
3129 { OPERAND_TYPE_IMM8
, "i8" },
3130 { OPERAND_TYPE_IMM8
, "i8s" },
3131 { OPERAND_TYPE_IMM16
, "i16" },
3132 { OPERAND_TYPE_IMM32
, "i32" },
3133 { OPERAND_TYPE_IMM32S
, "i32s" },
3134 { OPERAND_TYPE_IMM64
, "i64" },
3135 { OPERAND_TYPE_IMM1
, "i1" },
3136 { OPERAND_TYPE_BASEINDEX
, "BaseIndex" },
3137 { OPERAND_TYPE_DISP8
, "d8" },
3138 { OPERAND_TYPE_DISP16
, "d16" },
3139 { OPERAND_TYPE_DISP32
, "d32" },
3140 { OPERAND_TYPE_DISP32S
, "d32s" },
3141 { OPERAND_TYPE_DISP64
, "d64" },
3142 { OPERAND_TYPE_INOUTPORTREG
, "InOutPortReg" },
3143 { OPERAND_TYPE_SHIFTCOUNT
, "ShiftCount" },
3144 { OPERAND_TYPE_CONTROL
, "control reg" },
3145 { OPERAND_TYPE_TEST
, "test reg" },
3146 { OPERAND_TYPE_DEBUG
, "debug reg" },
3147 { OPERAND_TYPE_FLOATREG
, "FReg" },
3148 { OPERAND_TYPE_FLOATACC
, "FAcc" },
3149 { OPERAND_TYPE_SREG
, "SReg" },
3150 { OPERAND_TYPE_JUMPABSOLUTE
, "Jump Absolute" },
3151 { OPERAND_TYPE_REGMMX
, "rMMX" },
3152 { OPERAND_TYPE_REGXMM
, "rXMM" },
3153 { OPERAND_TYPE_REGYMM
, "rYMM" },
3154 { OPERAND_TYPE_REGZMM
, "rZMM" },
3155 { OPERAND_TYPE_REGMASK
, "Mask reg" },
3156 { OPERAND_TYPE_ESSEG
, "es" },
3160 pt (i386_operand_type t
)
3163 i386_operand_type a
;
3165 for (j
= 0; j
< ARRAY_SIZE (type_names
); j
++)
3167 a
= operand_type_and (t
, type_names
[j
].mask
);
3168 if (operand_type_equal (&a
, &type_names
[j
].mask
))
3169 fprintf (stdout
, "%s, ", type_names
[j
].name
);
3174 #endif /* DEBUG386 */
3176 static bfd_reloc_code_real_type
3177 reloc (unsigned int size
,
3180 bfd_reloc_code_real_type other
)
3182 if (other
!= NO_RELOC
)
3184 reloc_howto_type
*rel
;
3189 case BFD_RELOC_X86_64_GOT32
:
3190 return BFD_RELOC_X86_64_GOT64
;
3192 case BFD_RELOC_X86_64_GOTPLT64
:
3193 return BFD_RELOC_X86_64_GOTPLT64
;
3195 case BFD_RELOC_X86_64_PLTOFF64
:
3196 return BFD_RELOC_X86_64_PLTOFF64
;
3198 case BFD_RELOC_X86_64_GOTPC32
:
3199 other
= BFD_RELOC_X86_64_GOTPC64
;
3201 case BFD_RELOC_X86_64_GOTPCREL
:
3202 other
= BFD_RELOC_X86_64_GOTPCREL64
;
3204 case BFD_RELOC_X86_64_TPOFF32
:
3205 other
= BFD_RELOC_X86_64_TPOFF64
;
3207 case BFD_RELOC_X86_64_DTPOFF32
:
3208 other
= BFD_RELOC_X86_64_DTPOFF64
;
3214 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3215 if (other
== BFD_RELOC_SIZE32
)
3218 other
= BFD_RELOC_SIZE64
;
3221 as_bad (_("there are no pc-relative size relocations"));
3227 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
3228 if (size
== 4 && (flag_code
!= CODE_64BIT
|| disallow_64bit_reloc
))
3231 rel
= bfd_reloc_type_lookup (stdoutput
, other
);
3233 as_bad (_("unknown relocation (%u)"), other
);
3234 else if (size
!= bfd_get_reloc_size (rel
))
3235 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
3236 bfd_get_reloc_size (rel
),
3238 else if (pcrel
&& !rel
->pc_relative
)
3239 as_bad (_("non-pc-relative relocation for pc-relative field"));
3240 else if ((rel
->complain_on_overflow
== complain_overflow_signed
3242 || (rel
->complain_on_overflow
== complain_overflow_unsigned
3244 as_bad (_("relocated field and relocation type differ in signedness"));
3253 as_bad (_("there are no unsigned pc-relative relocations"));
3256 case 1: return BFD_RELOC_8_PCREL
;
3257 case 2: return BFD_RELOC_16_PCREL
;
3258 case 4: return BFD_RELOC_32_PCREL
;
3259 case 8: return BFD_RELOC_64_PCREL
;
3261 as_bad (_("cannot do %u byte pc-relative relocation"), size
);
3268 case 4: return BFD_RELOC_X86_64_32S
;
3273 case 1: return BFD_RELOC_8
;
3274 case 2: return BFD_RELOC_16
;
3275 case 4: return BFD_RELOC_32
;
3276 case 8: return BFD_RELOC_64
;
3278 as_bad (_("cannot do %s %u byte relocation"),
3279 sign
> 0 ? "signed" : "unsigned", size
);
3285 /* Here we decide which fixups can be adjusted to make them relative to
3286 the beginning of the section instead of the symbol. Basically we need
3287 to make sure that the dynamic relocations are done correctly, so in
3288 some cases we force the original symbol to be used. */
3291 tc_i386_fix_adjustable (fixS
*fixP ATTRIBUTE_UNUSED
)
3293 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3297 /* Don't adjust pc-relative references to merge sections in 64-bit
3299 if (use_rela_relocations
3300 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
3304 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
3305 and changed later by validate_fix. */
3306 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
3307 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
3310 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
3311 for size relocations. */
3312 if (fixP
->fx_r_type
== BFD_RELOC_SIZE32
3313 || fixP
->fx_r_type
== BFD_RELOC_SIZE64
3314 || fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
3315 || fixP
->fx_r_type
== BFD_RELOC_386_PLT32
3316 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
3317 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32X
3318 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
3319 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
3320 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
3321 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
3322 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
3323 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
3324 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
3325 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
3326 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTDESC
3327 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_DESC_CALL
3328 || fixP
->fx_r_type
== BFD_RELOC_X86_64_PLT32
3329 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
3330 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
3331 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCRELX
3332 || fixP
->fx_r_type
== BFD_RELOC_X86_64_REX_GOTPCRELX
3333 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
3334 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
3335 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
3336 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
3337 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
3338 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
3339 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
3340 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
3341 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPC32_TLSDESC
3342 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSDESC_CALL
3343 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
3344 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
3351 intel_float_operand (const char *mnemonic
)
3353 /* Note that the value returned is meaningful only for opcodes with (memory)
3354 operands, hence the code here is free to improperly handle opcodes that
3355 have no operands (for better performance and smaller code). */
3357 if (mnemonic
[0] != 'f')
3358 return 0; /* non-math */
3360 switch (mnemonic
[1])
3362 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
3363 the fs segment override prefix not currently handled because no
3364 call path can make opcodes without operands get here */
3366 return 2 /* integer op */;
3368 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
3369 return 3; /* fldcw/fldenv */
3372 if (mnemonic
[2] != 'o' /* fnop */)
3373 return 3; /* non-waiting control op */
3376 if (mnemonic
[2] == 's')
3377 return 3; /* frstor/frstpm */
3380 if (mnemonic
[2] == 'a')
3381 return 3; /* fsave */
3382 if (mnemonic
[2] == 't')
3384 switch (mnemonic
[3])
3386 case 'c': /* fstcw */
3387 case 'd': /* fstdw */
3388 case 'e': /* fstenv */
3389 case 's': /* fsts[gw] */
3395 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
3396 return 0; /* fxsave/fxrstor are not really math ops */
3403 /* Build the VEX prefix. */
3406 build_vex_prefix (const insn_template
*t
)
3408 unsigned int register_specifier
;
3409 unsigned int implied_prefix
;
3410 unsigned int vector_length
;
3413 /* Check register specifier. */
3414 if (i
.vex
.register_specifier
)
3416 register_specifier
=
3417 ~register_number (i
.vex
.register_specifier
) & 0xf;
3418 gas_assert ((i
.vex
.register_specifier
->reg_flags
& RegVRex
) == 0);
3421 register_specifier
= 0xf;
3423 /* Use 2-byte VEX prefix by swapping destination and source operand
3424 if there are more than 1 register operand. */
3425 if (i
.reg_operands
> 1
3426 && i
.vec_encoding
!= vex_encoding_vex3
3427 && i
.dir_encoding
== dir_encoding_default
3428 && i
.operands
== i
.reg_operands
3429 && operand_type_equal (&i
.types
[0], &i
.types
[i
.operands
- 1])
3430 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3431 && (i
.tm
.opcode_modifier
.load
|| i
.tm
.opcode_modifier
.d
)
3434 unsigned int xchg
= i
.operands
- 1;
3435 union i386_op temp_op
;
3436 i386_operand_type temp_type
;
3438 temp_type
= i
.types
[xchg
];
3439 i
.types
[xchg
] = i
.types
[0];
3440 i
.types
[0] = temp_type
;
3441 temp_op
= i
.op
[xchg
];
3442 i
.op
[xchg
] = i
.op
[0];
3445 gas_assert (i
.rm
.mode
== 3);
3449 i
.rm
.regmem
= i
.rm
.reg
;
3452 if (i
.tm
.opcode_modifier
.d
)
3453 i
.tm
.base_opcode
^= (i
.tm
.base_opcode
& 0xee) != 0x6e
3454 ? Opcode_SIMD_FloatD
: Opcode_SIMD_IntD
;
3455 else /* Use the next insn. */
3459 /* Use 2-byte VEX prefix by swapping commutative source operands if there
3460 are no memory operands and at least 3 register ones. */
3461 if (i
.reg_operands
>= 3
3462 && i
.vec_encoding
!= vex_encoding_vex3
3463 && i
.reg_operands
== i
.operands
- i
.imm_operands
3464 && i
.tm
.opcode_modifier
.vex
3465 && i
.tm
.opcode_modifier
.commutative
3466 && (i
.tm
.opcode_modifier
.sse2avx
|| optimize
> 1)
3468 && i
.vex
.register_specifier
3469 && !(i
.vex
.register_specifier
->reg_flags
& RegRex
))
3471 unsigned int xchg
= i
.operands
- i
.reg_operands
;
3472 union i386_op temp_op
;
3473 i386_operand_type temp_type
;
3475 gas_assert (i
.tm
.opcode_modifier
.vexopcode
== VEX0F
);
3476 gas_assert (!i
.tm
.opcode_modifier
.sae
);
3477 gas_assert (operand_type_equal (&i
.types
[i
.operands
- 2],
3478 &i
.types
[i
.operands
- 3]));
3479 gas_assert (i
.rm
.mode
== 3);
3481 temp_type
= i
.types
[xchg
];
3482 i
.types
[xchg
] = i
.types
[xchg
+ 1];
3483 i
.types
[xchg
+ 1] = temp_type
;
3484 temp_op
= i
.op
[xchg
];
3485 i
.op
[xchg
] = i
.op
[xchg
+ 1];
3486 i
.op
[xchg
+ 1] = temp_op
;
3489 xchg
= i
.rm
.regmem
| 8;
3490 i
.rm
.regmem
= ~register_specifier
& 0xf;
3491 gas_assert (!(i
.rm
.regmem
& 8));
3492 i
.vex
.register_specifier
+= xchg
- i
.rm
.regmem
;
3493 register_specifier
= ~xchg
& 0xf;
3496 if (i
.tm
.opcode_modifier
.vex
== VEXScalar
)
3497 vector_length
= avxscalar
;
3498 else if (i
.tm
.opcode_modifier
.vex
== VEX256
)
3504 /* Determine vector length from the last multi-length vector
3507 for (op
= t
->operands
; op
--;)
3508 if (t
->operand_types
[op
].bitfield
.xmmword
3509 && t
->operand_types
[op
].bitfield
.ymmword
3510 && i
.types
[op
].bitfield
.ymmword
)
3517 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3522 case DATA_PREFIX_OPCODE
:
3525 case REPE_PREFIX_OPCODE
:
3528 case REPNE_PREFIX_OPCODE
:
3535 /* Check the REX.W bit and VEXW. */
3536 if (i
.tm
.opcode_modifier
.vexw
== VEXWIG
)
3537 w
= (vexwig
== vexw1
|| (i
.rex
& REX_W
)) ? 1 : 0;
3538 else if (i
.tm
.opcode_modifier
.vexw
)
3539 w
= i
.tm
.opcode_modifier
.vexw
== VEXW1
? 1 : 0;
3541 w
= (flag_code
== CODE_64BIT
? i
.rex
& REX_W
: vexwig
== vexw1
) ? 1 : 0;
3543 /* Use 2-byte VEX prefix if possible. */
3545 && i
.vec_encoding
!= vex_encoding_vex3
3546 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3547 && (i
.rex
& (REX_W
| REX_X
| REX_B
)) == 0)
3549 /* 2-byte VEX prefix. */
3553 i
.vex
.bytes
[0] = 0xc5;
3555 /* Check the REX.R bit. */
3556 r
= (i
.rex
& REX_R
) ? 0 : 1;
3557 i
.vex
.bytes
[1] = (r
<< 7
3558 | register_specifier
<< 3
3559 | vector_length
<< 2
3564 /* 3-byte VEX prefix. */
3569 switch (i
.tm
.opcode_modifier
.vexopcode
)
3573 i
.vex
.bytes
[0] = 0xc4;
3577 i
.vex
.bytes
[0] = 0xc4;
3581 i
.vex
.bytes
[0] = 0xc4;
3585 i
.vex
.bytes
[0] = 0x8f;
3589 i
.vex
.bytes
[0] = 0x8f;
3593 i
.vex
.bytes
[0] = 0x8f;
3599 /* The high 3 bits of the second VEX byte are 1's compliment
3600 of RXB bits from REX. */
3601 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3603 i
.vex
.bytes
[2] = (w
<< 7
3604 | register_specifier
<< 3
3605 | vector_length
<< 2
3610 static INLINE bfd_boolean
3611 is_evex_encoding (const insn_template
*t
)
3613 return t
->opcode_modifier
.evex
|| t
->opcode_modifier
.disp8memshift
3614 || t
->opcode_modifier
.broadcast
|| t
->opcode_modifier
.masking
3615 || t
->opcode_modifier
.sae
;
3618 static INLINE bfd_boolean
3619 is_any_vex_encoding (const insn_template
*t
)
3621 return t
->opcode_modifier
.vex
|| t
->opcode_modifier
.vexopcode
3622 || is_evex_encoding (t
);
3625 /* Build the EVEX prefix. */
3628 build_evex_prefix (void)
3630 unsigned int register_specifier
;
3631 unsigned int implied_prefix
;
3633 rex_byte vrex_used
= 0;
3635 /* Check register specifier. */
3636 if (i
.vex
.register_specifier
)
3638 gas_assert ((i
.vrex
& REX_X
) == 0);
3640 register_specifier
= i
.vex
.register_specifier
->reg_num
;
3641 if ((i
.vex
.register_specifier
->reg_flags
& RegRex
))
3642 register_specifier
+= 8;
3643 /* The upper 16 registers are encoded in the fourth byte of the
3645 if (!(i
.vex
.register_specifier
->reg_flags
& RegVRex
))
3646 i
.vex
.bytes
[3] = 0x8;
3647 register_specifier
= ~register_specifier
& 0xf;
3651 register_specifier
= 0xf;
3653 /* Encode upper 16 vector index register in the fourth byte of
3655 if (!(i
.vrex
& REX_X
))
3656 i
.vex
.bytes
[3] = 0x8;
3661 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3666 case DATA_PREFIX_OPCODE
:
3669 case REPE_PREFIX_OPCODE
:
3672 case REPNE_PREFIX_OPCODE
:
3679 /* 4 byte EVEX prefix. */
3681 i
.vex
.bytes
[0] = 0x62;
3684 switch (i
.tm
.opcode_modifier
.vexopcode
)
3700 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3702 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3704 /* The fifth bit of the second EVEX byte is 1's compliment of the
3705 REX_R bit in VREX. */
3706 if (!(i
.vrex
& REX_R
))
3707 i
.vex
.bytes
[1] |= 0x10;
3711 if ((i
.reg_operands
+ i
.imm_operands
) == i
.operands
)
3713 /* When all operands are registers, the REX_X bit in REX is not
3714 used. We reuse it to encode the upper 16 registers, which is
3715 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3716 as 1's compliment. */
3717 if ((i
.vrex
& REX_B
))
3720 i
.vex
.bytes
[1] &= ~0x40;
3724 /* EVEX instructions shouldn't need the REX prefix. */
3725 i
.vrex
&= ~vrex_used
;
3726 gas_assert (i
.vrex
== 0);
3728 /* Check the REX.W bit and VEXW. */
3729 if (i
.tm
.opcode_modifier
.vexw
== VEXWIG
)
3730 w
= (evexwig
== evexw1
|| (i
.rex
& REX_W
)) ? 1 : 0;
3731 else if (i
.tm
.opcode_modifier
.vexw
)
3732 w
= i
.tm
.opcode_modifier
.vexw
== VEXW1
? 1 : 0;
3734 w
= (flag_code
== CODE_64BIT
? i
.rex
& REX_W
: evexwig
== evexw1
) ? 1 : 0;
3736 /* Encode the U bit. */
3737 implied_prefix
|= 0x4;
3739 /* The third byte of the EVEX prefix. */
3740 i
.vex
.bytes
[2] = (w
<< 7 | register_specifier
<< 3 | implied_prefix
);
3742 /* The fourth byte of the EVEX prefix. */
3743 /* The zeroing-masking bit. */
3744 if (i
.mask
&& i
.mask
->zeroing
)
3745 i
.vex
.bytes
[3] |= 0x80;
3747 /* Don't always set the broadcast bit if there is no RC. */
3750 /* Encode the vector length. */
3751 unsigned int vec_length
;
3753 if (!i
.tm
.opcode_modifier
.evex
3754 || i
.tm
.opcode_modifier
.evex
== EVEXDYN
)
3758 /* Determine vector length from the last multi-length vector
3761 for (op
= i
.operands
; op
--;)
3762 if (i
.tm
.operand_types
[op
].bitfield
.xmmword
3763 + i
.tm
.operand_types
[op
].bitfield
.ymmword
3764 + i
.tm
.operand_types
[op
].bitfield
.zmmword
> 1)
3766 if (i
.types
[op
].bitfield
.zmmword
)
3768 i
.tm
.opcode_modifier
.evex
= EVEX512
;
3771 else if (i
.types
[op
].bitfield
.ymmword
)
3773 i
.tm
.opcode_modifier
.evex
= EVEX256
;
3776 else if (i
.types
[op
].bitfield
.xmmword
)
3778 i
.tm
.opcode_modifier
.evex
= EVEX128
;
3781 else if (i
.broadcast
&& (int) op
== i
.broadcast
->operand
)
3783 switch (i
.broadcast
->bytes
)
3786 i
.tm
.opcode_modifier
.evex
= EVEX512
;
3789 i
.tm
.opcode_modifier
.evex
= EVEX256
;
3792 i
.tm
.opcode_modifier
.evex
= EVEX128
;
3801 if (op
>= MAX_OPERANDS
)
3805 switch (i
.tm
.opcode_modifier
.evex
)
3807 case EVEXLIG
: /* LL' is ignored */
3808 vec_length
= evexlig
<< 5;
3811 vec_length
= 0 << 5;
3814 vec_length
= 1 << 5;
3817 vec_length
= 2 << 5;
3823 i
.vex
.bytes
[3] |= vec_length
;
3824 /* Encode the broadcast bit. */
3826 i
.vex
.bytes
[3] |= 0x10;
3830 if (i
.rounding
->type
!= saeonly
)
3831 i
.vex
.bytes
[3] |= 0x10 | (i
.rounding
->type
<< 5);
3833 i
.vex
.bytes
[3] |= 0x10 | (evexrcig
<< 5);
3836 if (i
.mask
&& i
.mask
->mask
)
3837 i
.vex
.bytes
[3] |= i
.mask
->mask
->reg_num
;
3841 process_immext (void)
3845 if ((i
.tm
.cpu_flags
.bitfield
.cpusse3
|| i
.tm
.cpu_flags
.bitfield
.cpusvme
)
3848 /* MONITOR/MWAIT as well as SVME instructions have fixed operands
3849 with an opcode suffix which is coded in the same place as an
3850 8-bit immediate field would be.
3851 Here we check those operands and remove them afterwards. */
3854 for (x
= 0; x
< i
.operands
; x
++)
3855 if (register_number (i
.op
[x
].regs
) != x
)
3856 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3857 register_prefix
, i
.op
[x
].regs
->reg_name
, x
+ 1,
3863 if (i
.tm
.cpu_flags
.bitfield
.cpumwaitx
&& i
.operands
> 0)
3865 /* MONITORX/MWAITX instructions have fixed operands with an opcode
3866 suffix which is coded in the same place as an 8-bit immediate
3868 Here we check those operands and remove them afterwards. */
3871 if (i
.operands
!= 3)
3874 for (x
= 0; x
< 2; x
++)
3875 if (register_number (i
.op
[x
].regs
) != x
)
3876 goto bad_register_operand
;
3878 /* Check for third operand for mwaitx/monitorx insn. */
3879 if (register_number (i
.op
[x
].regs
)
3880 != (x
+ (i
.tm
.extension_opcode
== 0xfb)))
3882 bad_register_operand
:
3883 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3884 register_prefix
, i
.op
[x
].regs
->reg_name
, x
+1,
3891 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
3892 which is coded in the same place as an 8-bit immediate field
3893 would be. Here we fake an 8-bit immediate operand from the
3894 opcode suffix stored in tm.extension_opcode.
3896 AVX instructions also use this encoding, for some of
3897 3 argument instructions. */
3899 gas_assert (i
.imm_operands
<= 1
3901 || (is_any_vex_encoding (&i
.tm
)
3902 && i
.operands
<= 4)));
3904 exp
= &im_expressions
[i
.imm_operands
++];
3905 i
.op
[i
.operands
].imms
= exp
;
3906 i
.types
[i
.operands
] = imm8
;
3908 exp
->X_op
= O_constant
;
3909 exp
->X_add_number
= i
.tm
.extension_opcode
;
3910 i
.tm
.extension_opcode
= None
;
3917 switch (i
.tm
.opcode_modifier
.hleprefixok
)
3922 as_bad (_("invalid instruction `%s' after `%s'"),
3923 i
.tm
.name
, i
.hle_prefix
);
3926 if (i
.prefix
[LOCK_PREFIX
])
3928 as_bad (_("missing `lock' with `%s'"), i
.hle_prefix
);
3932 case HLEPrefixRelease
:
3933 if (i
.prefix
[HLE_PREFIX
] != XRELEASE_PREFIX_OPCODE
)
3935 as_bad (_("instruction `%s' after `xacquire' not allowed"),
3939 if (i
.mem_operands
== 0 || !(i
.flags
[i
.operands
- 1] & Operand_Mem
))
3941 as_bad (_("memory destination needed for instruction `%s'"
3942 " after `xrelease'"), i
.tm
.name
);
3949 /* Try the shortest encoding by shortening operand size. */
3952 optimize_encoding (void)
3956 if (optimize_for_space
3957 && i
.reg_operands
== 1
3958 && i
.imm_operands
== 1
3959 && !i
.types
[1].bitfield
.byte
3960 && i
.op
[0].imms
->X_op
== O_constant
3961 && fits_in_imm7 (i
.op
[0].imms
->X_add_number
)
3962 && ((i
.tm
.base_opcode
== 0xa8
3963 && i
.tm
.extension_opcode
== None
)
3964 || (i
.tm
.base_opcode
== 0xf6
3965 && i
.tm
.extension_opcode
== 0x0)))
3968 test $imm7, %r64/%r32/%r16 -> test $imm7, %r8
3970 unsigned int base_regnum
= i
.op
[1].regs
->reg_num
;
3971 if (flag_code
== CODE_64BIT
|| base_regnum
< 4)
3973 i
.types
[1].bitfield
.byte
= 1;
3974 /* Ignore the suffix. */
3976 if (base_regnum
>= 4
3977 && !(i
.op
[1].regs
->reg_flags
& RegRex
))
3979 /* Handle SP, BP, SI and DI registers. */
3980 if (i
.types
[1].bitfield
.word
)
3982 else if (i
.types
[1].bitfield
.dword
)
3990 else if (flag_code
== CODE_64BIT
3991 && ((i
.types
[1].bitfield
.qword
3992 && i
.reg_operands
== 1
3993 && i
.imm_operands
== 1
3994 && i
.op
[0].imms
->X_op
== O_constant
3995 && ((i
.tm
.base_opcode
== 0xb8
3996 && i
.tm
.extension_opcode
== None
3997 && fits_in_unsigned_long (i
.op
[0].imms
->X_add_number
))
3998 || (fits_in_imm31 (i
.op
[0].imms
->X_add_number
)
3999 && (((i
.tm
.base_opcode
== 0x24
4000 || i
.tm
.base_opcode
== 0xa8)
4001 && i
.tm
.extension_opcode
== None
)
4002 || (i
.tm
.base_opcode
== 0x80
4003 && i
.tm
.extension_opcode
== 0x4)
4004 || ((i
.tm
.base_opcode
== 0xf6
4005 || (i
.tm
.base_opcode
| 1) == 0xc7)
4006 && i
.tm
.extension_opcode
== 0x0)))
4007 || (fits_in_imm7 (i
.op
[0].imms
->X_add_number
)
4008 && i
.tm
.base_opcode
== 0x83
4009 && i
.tm
.extension_opcode
== 0x4)))
4010 || (i
.types
[0].bitfield
.qword
4011 && ((i
.reg_operands
== 2
4012 && i
.op
[0].regs
== i
.op
[1].regs
4013 && ((i
.tm
.base_opcode
== 0x30
4014 || i
.tm
.base_opcode
== 0x28)
4015 && i
.tm
.extension_opcode
== None
))
4016 || (i
.reg_operands
== 1
4018 && i
.tm
.base_opcode
== 0x30
4019 && i
.tm
.extension_opcode
== None
)))))
4022 andq $imm31, %r64 -> andl $imm31, %r32
4023 andq $imm7, %r64 -> andl $imm7, %r32
4024 testq $imm31, %r64 -> testl $imm31, %r32
4025 xorq %r64, %r64 -> xorl %r32, %r32
4026 subq %r64, %r64 -> subl %r32, %r32
4027 movq $imm31, %r64 -> movl $imm31, %r32
4028 movq $imm32, %r64 -> movl $imm32, %r32
4030 i
.tm
.opcode_modifier
.norex64
= 1;
4031 if (i
.tm
.base_opcode
== 0xb8 || (i
.tm
.base_opcode
| 1) == 0xc7)
4034 movq $imm31, %r64 -> movl $imm31, %r32
4035 movq $imm32, %r64 -> movl $imm32, %r32
4037 i
.tm
.operand_types
[0].bitfield
.imm32
= 1;
4038 i
.tm
.operand_types
[0].bitfield
.imm32s
= 0;
4039 i
.tm
.operand_types
[0].bitfield
.imm64
= 0;
4040 i
.types
[0].bitfield
.imm32
= 1;
4041 i
.types
[0].bitfield
.imm32s
= 0;
4042 i
.types
[0].bitfield
.imm64
= 0;
4043 i
.types
[1].bitfield
.dword
= 1;
4044 i
.types
[1].bitfield
.qword
= 0;
4045 if ((i
.tm
.base_opcode
| 1) == 0xc7)
4048 movq $imm31, %r64 -> movl $imm31, %r32
4050 i
.tm
.base_opcode
= 0xb8;
4051 i
.tm
.extension_opcode
= None
;
4052 i
.tm
.opcode_modifier
.w
= 0;
4053 i
.tm
.opcode_modifier
.shortform
= 1;
4054 i
.tm
.opcode_modifier
.modrm
= 0;
4058 else if (optimize
> 1
4059 && !optimize_for_space
4060 && i
.reg_operands
== 2
4061 && i
.op
[0].regs
== i
.op
[1].regs
4062 && ((i
.tm
.base_opcode
& ~(Opcode_D
| 1)) == 0x8
4063 || (i
.tm
.base_opcode
& ~(Opcode_D
| 1)) == 0x20)
4064 && (flag_code
!= CODE_64BIT
|| !i
.types
[0].bitfield
.dword
))
4067 andb %rN, %rN -> testb %rN, %rN
4068 andw %rN, %rN -> testw %rN, %rN
4069 andq %rN, %rN -> testq %rN, %rN
4070 orb %rN, %rN -> testb %rN, %rN
4071 orw %rN, %rN -> testw %rN, %rN
4072 orq %rN, %rN -> testq %rN, %rN
4074 and outside of 64-bit mode
4076 andl %rN, %rN -> testl %rN, %rN
4077 orl %rN, %rN -> testl %rN, %rN
4079 i
.tm
.base_opcode
= 0x84 | (i
.tm
.base_opcode
& 1);
4081 else if (i
.reg_operands
== 3
4082 && i
.op
[0].regs
== i
.op
[1].regs
4083 && !i
.types
[2].bitfield
.xmmword
4084 && (i
.tm
.opcode_modifier
.vex
4085 || ((!i
.mask
|| i
.mask
->zeroing
)
4087 && is_evex_encoding (&i
.tm
)
4088 && (i
.vec_encoding
!= vex_encoding_evex
4089 || cpu_arch_isa_flags
.bitfield
.cpuavx512vl
4090 || i
.tm
.cpu_flags
.bitfield
.cpuavx512vl
4091 || (i
.tm
.operand_types
[2].bitfield
.zmmword
4092 && i
.types
[2].bitfield
.ymmword
))))
4093 && ((i
.tm
.base_opcode
== 0x55
4094 || i
.tm
.base_opcode
== 0x6655
4095 || i
.tm
.base_opcode
== 0x66df
4096 || i
.tm
.base_opcode
== 0x57
4097 || i
.tm
.base_opcode
== 0x6657
4098 || i
.tm
.base_opcode
== 0x66ef
4099 || i
.tm
.base_opcode
== 0x66f8
4100 || i
.tm
.base_opcode
== 0x66f9
4101 || i
.tm
.base_opcode
== 0x66fa
4102 || i
.tm
.base_opcode
== 0x66fb
4103 || i
.tm
.base_opcode
== 0x42
4104 || i
.tm
.base_opcode
== 0x6642
4105 || i
.tm
.base_opcode
== 0x47
4106 || i
.tm
.base_opcode
== 0x6647)
4107 && i
.tm
.extension_opcode
== None
))
4110 VOP, one of vandnps, vandnpd, vxorps, vxorpd, vpsubb, vpsubd,
4112 EVEX VOP %zmmM, %zmmM, %zmmN
4113 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
4114 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4115 EVEX VOP %ymmM, %ymmM, %ymmN
4116 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
4117 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4118 VEX VOP %ymmM, %ymmM, %ymmN
4119 -> VEX VOP %xmmM, %xmmM, %xmmN
4120 VOP, one of vpandn and vpxor:
4121 VEX VOP %ymmM, %ymmM, %ymmN
4122 -> VEX VOP %xmmM, %xmmM, %xmmN
4123 VOP, one of vpandnd and vpandnq:
4124 EVEX VOP %zmmM, %zmmM, %zmmN
4125 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
4126 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4127 EVEX VOP %ymmM, %ymmM, %ymmN
4128 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
4129 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4130 VOP, one of vpxord and vpxorq:
4131 EVEX VOP %zmmM, %zmmM, %zmmN
4132 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
4133 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4134 EVEX VOP %ymmM, %ymmM, %ymmN
4135 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
4136 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4137 VOP, one of kxord and kxorq:
4138 VEX VOP %kM, %kM, %kN
4139 -> VEX kxorw %kM, %kM, %kN
4140 VOP, one of kandnd and kandnq:
4141 VEX VOP %kM, %kM, %kN
4142 -> VEX kandnw %kM, %kM, %kN
4144 if (is_evex_encoding (&i
.tm
))
4146 if (i
.vec_encoding
!= vex_encoding_evex
)
4148 i
.tm
.opcode_modifier
.vex
= VEX128
;
4149 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4150 i
.tm
.opcode_modifier
.evex
= 0;
4152 else if (optimize
> 1)
4153 i
.tm
.opcode_modifier
.evex
= EVEX128
;
4157 else if (i
.tm
.operand_types
[0].bitfield
.class == RegMask
)
4159 i
.tm
.base_opcode
&= 0xff;
4160 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4163 i
.tm
.opcode_modifier
.vex
= VEX128
;
4165 if (i
.tm
.opcode_modifier
.vex
)
4166 for (j
= 0; j
< 3; j
++)
4168 i
.types
[j
].bitfield
.xmmword
= 1;
4169 i
.types
[j
].bitfield
.ymmword
= 0;
4172 else if (i
.vec_encoding
!= vex_encoding_evex
4173 && !i
.types
[0].bitfield
.zmmword
4174 && !i
.types
[1].bitfield
.zmmword
4177 && is_evex_encoding (&i
.tm
)
4178 && ((i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0x666f
4179 || (i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0xf36f
4180 || (i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0xf26f
4181 || (i
.tm
.base_opcode
& ~4) == 0x66db
4182 || (i
.tm
.base_opcode
& ~4) == 0x66eb)
4183 && i
.tm
.extension_opcode
== None
)
4186 VOP, one of vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16,
4187 vmovdqu32 and vmovdqu64:
4188 EVEX VOP %xmmM, %xmmN
4189 -> VEX vmovdqa|vmovdqu %xmmM, %xmmN (M and N < 16)
4190 EVEX VOP %ymmM, %ymmN
4191 -> VEX vmovdqa|vmovdqu %ymmM, %ymmN (M and N < 16)
4193 -> VEX vmovdqa|vmovdqu %xmmM, mem (M < 16)
4195 -> VEX vmovdqa|vmovdqu %ymmM, mem (M < 16)
4197 -> VEX mvmovdqa|vmovdquem, %xmmN (N < 16)
4199 -> VEX vmovdqa|vmovdqu mem, %ymmN (N < 16)
4200 VOP, one of vpand, vpandn, vpor, vpxor:
4201 EVEX VOP{d,q} %xmmL, %xmmM, %xmmN
4202 -> VEX VOP %xmmL, %xmmM, %xmmN (L, M, and N < 16)
4203 EVEX VOP{d,q} %ymmL, %ymmM, %ymmN
4204 -> VEX VOP %ymmL, %ymmM, %ymmN (L, M, and N < 16)
4205 EVEX VOP{d,q} mem, %xmmM, %xmmN
4206 -> VEX VOP mem, %xmmM, %xmmN (M and N < 16)
4207 EVEX VOP{d,q} mem, %ymmM, %ymmN
4208 -> VEX VOP mem, %ymmM, %ymmN (M and N < 16)
4210 for (j
= 0; j
< i
.operands
; j
++)
4211 if (operand_type_check (i
.types
[j
], disp
)
4212 && i
.op
[j
].disps
->X_op
== O_constant
)
4214 /* Since the VEX prefix has 2 or 3 bytes, the EVEX prefix
4215 has 4 bytes, EVEX Disp8 has 1 byte and VEX Disp32 has 4
4216 bytes, we choose EVEX Disp8 over VEX Disp32. */
4217 int evex_disp8
, vex_disp8
;
4218 unsigned int memshift
= i
.memshift
;
4219 offsetT n
= i
.op
[j
].disps
->X_add_number
;
4221 evex_disp8
= fits_in_disp8 (n
);
4223 vex_disp8
= fits_in_disp8 (n
);
4224 if (evex_disp8
!= vex_disp8
)
4226 i
.memshift
= memshift
;
4230 i
.types
[j
].bitfield
.disp8
= vex_disp8
;
4233 if ((i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0xf26f)
4234 i
.tm
.base_opcode
^= 0xf36f ^ 0xf26f;
4235 i
.tm
.opcode_modifier
.vex
4236 = i
.types
[0].bitfield
.ymmword
? VEX256
: VEX128
;
4237 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4238 /* VPAND, VPOR, and VPXOR are commutative. */
4239 if (i
.reg_operands
== 3 && i
.tm
.base_opcode
!= 0x66df)
4240 i
.tm
.opcode_modifier
.commutative
= 1;
4241 i
.tm
.opcode_modifier
.evex
= 0;
4242 i
.tm
.opcode_modifier
.masking
= 0;
4243 i
.tm
.opcode_modifier
.broadcast
= 0;
4244 i
.tm
.opcode_modifier
.disp8memshift
= 0;
4247 i
.types
[j
].bitfield
.disp8
4248 = fits_in_disp8 (i
.op
[j
].disps
->X_add_number
);
4252 /* This is the guts of the machine-dependent assembler. LINE points to a
4253 machine dependent instruction. This function is supposed to emit
4254 the frags/bytes it assembles to. */
4257 md_assemble (char *line
)
4260 char mnemonic
[MAX_MNEM_SIZE
], mnem_suffix
;
4261 const insn_template
*t
;
4263 /* Initialize globals. */
4264 memset (&i
, '\0', sizeof (i
));
4265 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4266 i
.reloc
[j
] = NO_RELOC
;
4267 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
4268 memset (im_expressions
, '\0', sizeof (im_expressions
));
4269 save_stack_p
= save_stack
;
4271 /* First parse an instruction mnemonic & call i386_operand for the operands.
4272 We assume that the scrubber has arranged it so that line[0] is the valid
4273 start of a (possibly prefixed) mnemonic. */
4275 line
= parse_insn (line
, mnemonic
);
4278 mnem_suffix
= i
.suffix
;
4280 line
= parse_operands (line
, mnemonic
);
4282 xfree (i
.memop1_string
);
4283 i
.memop1_string
= NULL
;
4287 /* Now we've parsed the mnemonic into a set of templates, and have the
4288 operands at hand. */
4290 /* All intel opcodes have reversed operands except for "bound" and
4291 "enter". We also don't reverse intersegment "jmp" and "call"
4292 instructions with 2 immediate operands so that the immediate segment
4293 precedes the offset, as it does when in AT&T mode. */
4296 && (strcmp (mnemonic
, "bound") != 0)
4297 && (strcmp (mnemonic
, "invlpga") != 0)
4298 && !(operand_type_check (i
.types
[0], imm
)
4299 && operand_type_check (i
.types
[1], imm
)))
4302 /* The order of the immediates should be reversed
4303 for 2 immediates extrq and insertq instructions */
4304 if (i
.imm_operands
== 2
4305 && (strcmp (mnemonic
, "extrq") == 0
4306 || strcmp (mnemonic
, "insertq") == 0))
4307 swap_2_operands (0, 1);
4312 /* Don't optimize displacement for movabs since it only takes 64bit
4315 && i
.disp_encoding
!= disp_encoding_32bit
4316 && (flag_code
!= CODE_64BIT
4317 || strcmp (mnemonic
, "movabs") != 0))
4320 /* Next, we find a template that matches the given insn,
4321 making sure the overlap of the given operands types is consistent
4322 with the template operand types. */
4324 if (!(t
= match_template (mnem_suffix
)))
4327 if (sse_check
!= check_none
4328 && !i
.tm
.opcode_modifier
.noavx
4329 && !i
.tm
.cpu_flags
.bitfield
.cpuavx
4330 && (i
.tm
.cpu_flags
.bitfield
.cpusse
4331 || i
.tm
.cpu_flags
.bitfield
.cpusse2
4332 || i
.tm
.cpu_flags
.bitfield
.cpusse3
4333 || i
.tm
.cpu_flags
.bitfield
.cpussse3
4334 || i
.tm
.cpu_flags
.bitfield
.cpusse4_1
4335 || i
.tm
.cpu_flags
.bitfield
.cpusse4_2
4336 || i
.tm
.cpu_flags
.bitfield
.cpupclmul
4337 || i
.tm
.cpu_flags
.bitfield
.cpuaes
4338 || i
.tm
.cpu_flags
.bitfield
.cpugfni
))
4340 (sse_check
== check_warning
4342 : as_bad
) (_("SSE instruction `%s' is used"), i
.tm
.name
);
4345 /* Zap movzx and movsx suffix. The suffix has been set from
4346 "word ptr" or "byte ptr" on the source operand in Intel syntax
4347 or extracted from mnemonic in AT&T syntax. But we'll use
4348 the destination register to choose the suffix for encoding. */
4349 if ((i
.tm
.base_opcode
& ~9) == 0x0fb6)
4351 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
4352 there is no suffix, the default will be byte extension. */
4353 if (i
.reg_operands
!= 2
4356 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
4361 if (i
.tm
.opcode_modifier
.fwait
)
4362 if (!add_prefix (FWAIT_OPCODE
))
4365 /* Check if REP prefix is OK. */
4366 if (i
.rep_prefix
&& !i
.tm
.opcode_modifier
.repprefixok
)
4368 as_bad (_("invalid instruction `%s' after `%s'"),
4369 i
.tm
.name
, i
.rep_prefix
);
4373 /* Check for lock without a lockable instruction. Destination operand
4374 must be memory unless it is xchg (0x86). */
4375 if (i
.prefix
[LOCK_PREFIX
]
4376 && (!i
.tm
.opcode_modifier
.islockable
4377 || i
.mem_operands
== 0
4378 || (i
.tm
.base_opcode
!= 0x86
4379 && !(i
.flags
[i
.operands
- 1] & Operand_Mem
))))
4381 as_bad (_("expecting lockable instruction after `lock'"));
4385 /* Check for data size prefix on VEX/XOP/EVEX encoded insns. */
4386 if (i
.prefix
[DATA_PREFIX
] && is_any_vex_encoding (&i
.tm
))
4388 as_bad (_("data size prefix invalid with `%s'"), i
.tm
.name
);
4392 /* Check if HLE prefix is OK. */
4393 if (i
.hle_prefix
&& !check_hle ())
4396 /* Check BND prefix. */
4397 if (i
.bnd_prefix
&& !i
.tm
.opcode_modifier
.bndprefixok
)
4398 as_bad (_("expecting valid branch instruction after `bnd'"));
4400 /* Check NOTRACK prefix. */
4401 if (i
.notrack_prefix
&& !i
.tm
.opcode_modifier
.notrackprefixok
)
4402 as_bad (_("expecting indirect branch instruction after `notrack'"));
4404 if (i
.tm
.cpu_flags
.bitfield
.cpumpx
)
4406 if (flag_code
== CODE_64BIT
&& i
.prefix
[ADDR_PREFIX
])
4407 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
4408 else if (flag_code
!= CODE_16BIT
4409 ? i
.prefix
[ADDR_PREFIX
]
4410 : i
.mem_operands
&& !i
.prefix
[ADDR_PREFIX
])
4411 as_bad (_("16-bit address isn't allowed in MPX instructions"));
4414 /* Insert BND prefix. */
4415 if (add_bnd_prefix
&& i
.tm
.opcode_modifier
.bndprefixok
)
4417 if (!i
.prefix
[BND_PREFIX
])
4418 add_prefix (BND_PREFIX_OPCODE
);
4419 else if (i
.prefix
[BND_PREFIX
] != BND_PREFIX_OPCODE
)
4421 as_warn (_("replacing `rep'/`repe' prefix by `bnd'"));
4422 i
.prefix
[BND_PREFIX
] = BND_PREFIX_OPCODE
;
4426 /* Check string instruction segment overrides. */
4427 if (i
.tm
.opcode_modifier
.isstring
&& i
.mem_operands
!= 0)
4429 if (!check_string ())
4431 i
.disp_operands
= 0;
4434 if (optimize
&& !i
.no_optimize
&& i
.tm
.opcode_modifier
.optimize
)
4435 optimize_encoding ();
4437 if (!process_suffix ())
4440 /* Update operand types. */
4441 for (j
= 0; j
< i
.operands
; j
++)
4442 i
.types
[j
] = operand_type_and (i
.types
[j
], i
.tm
.operand_types
[j
]);
4444 /* Make still unresolved immediate matches conform to size of immediate
4445 given in i.suffix. */
4446 if (!finalize_imm ())
4449 if (i
.types
[0].bitfield
.imm1
)
4450 i
.imm_operands
= 0; /* kludge for shift insns. */
4452 /* We only need to check those implicit registers for instructions
4453 with 3 operands or less. */
4454 if (i
.operands
<= 3)
4455 for (j
= 0; j
< i
.operands
; j
++)
4456 if (i
.types
[j
].bitfield
.inoutportreg
4457 || i
.types
[j
].bitfield
.shiftcount
4458 || (i
.types
[j
].bitfield
.acc
&& !i
.types
[j
].bitfield
.xmmword
))
4461 /* ImmExt should be processed after SSE2AVX. */
4462 if (!i
.tm
.opcode_modifier
.sse2avx
4463 && i
.tm
.opcode_modifier
.immext
)
4466 /* For insns with operands there are more diddles to do to the opcode. */
4469 if (!process_operands ())
4472 else if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
4474 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
4475 as_warn (_("translating to `%sp'"), i
.tm
.name
);
4478 if (is_any_vex_encoding (&i
.tm
))
4480 if (!cpu_arch_flags
.bitfield
.cpui286
)
4482 as_bad (_("instruction `%s' isn't supported outside of protected mode."),
4487 if (i
.tm
.opcode_modifier
.vex
)
4488 build_vex_prefix (t
);
4490 build_evex_prefix ();
4493 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
4494 instructions may define INT_OPCODE as well, so avoid this corner
4495 case for those instructions that use MODRM. */
4496 if (i
.tm
.base_opcode
== INT_OPCODE
4497 && !i
.tm
.opcode_modifier
.modrm
4498 && i
.op
[0].imms
->X_add_number
== 3)
4500 i
.tm
.base_opcode
= INT3_OPCODE
;
4504 if ((i
.tm
.opcode_modifier
.jump
4505 || i
.tm
.opcode_modifier
.jumpbyte
4506 || i
.tm
.opcode_modifier
.jumpdword
)
4507 && i
.op
[0].disps
->X_op
== O_constant
)
4509 /* Convert "jmp constant" (and "call constant") to a jump (call) to
4510 the absolute address given by the constant. Since ix86 jumps and
4511 calls are pc relative, we need to generate a reloc. */
4512 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
4513 i
.op
[0].disps
->X_op
= O_symbol
;
4516 if (i
.tm
.opcode_modifier
.rex64
)
4519 /* For 8 bit registers we need an empty rex prefix. Also if the
4520 instruction already has a prefix, we need to convert old
4521 registers to new ones. */
4523 if ((i
.types
[0].bitfield
.class == Reg
&& i
.types
[0].bitfield
.byte
4524 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
4525 || (i
.types
[1].bitfield
.class == Reg
&& i
.types
[1].bitfield
.byte
4526 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
4527 || (((i
.types
[0].bitfield
.class == Reg
&& i
.types
[0].bitfield
.byte
)
4528 || (i
.types
[1].bitfield
.class == Reg
&& i
.types
[1].bitfield
.byte
))
4533 i
.rex
|= REX_OPCODE
;
4534 for (x
= 0; x
< 2; x
++)
4536 /* Look for 8 bit operand that uses old registers. */
4537 if (i
.types
[x
].bitfield
.class == Reg
&& i
.types
[x
].bitfield
.byte
4538 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
4540 /* In case it is "hi" register, give up. */
4541 if (i
.op
[x
].regs
->reg_num
> 3)
4542 as_bad (_("can't encode register '%s%s' in an "
4543 "instruction requiring REX prefix."),
4544 register_prefix
, i
.op
[x
].regs
->reg_name
);
4546 /* Otherwise it is equivalent to the extended register.
4547 Since the encoding doesn't change this is merely
4548 cosmetic cleanup for debug output. */
4550 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
4555 if (i
.rex
== 0 && i
.rex_encoding
)
4557 /* Check if we can add a REX_OPCODE byte. Look for 8 bit operand
4558 that uses legacy register. If it is "hi" register, don't add
4559 the REX_OPCODE byte. */
4561 for (x
= 0; x
< 2; x
++)
4562 if (i
.types
[x
].bitfield
.class == Reg
4563 && i
.types
[x
].bitfield
.byte
4564 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0
4565 && i
.op
[x
].regs
->reg_num
> 3)
4567 i
.rex_encoding
= FALSE
;
4576 add_prefix (REX_OPCODE
| i
.rex
);
4578 /* We are ready to output the insn. */
4583 parse_insn (char *line
, char *mnemonic
)
4586 char *token_start
= l
;
4589 const insn_template
*t
;
4595 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
4600 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
4602 as_bad (_("no such instruction: `%s'"), token_start
);
4607 if (!is_space_char (*l
)
4608 && *l
!= END_OF_INSN
4610 || (*l
!= PREFIX_SEPARATOR
4613 as_bad (_("invalid character %s in mnemonic"),
4614 output_invalid (*l
));
4617 if (token_start
== l
)
4619 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
4620 as_bad (_("expecting prefix; got nothing"));
4622 as_bad (_("expecting mnemonic; got nothing"));
4626 /* Look up instruction (or prefix) via hash table. */
4627 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
4629 if (*l
!= END_OF_INSN
4630 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
4631 && current_templates
4632 && current_templates
->start
->opcode_modifier
.isprefix
)
4634 if (!cpu_flags_check_cpu64 (current_templates
->start
->cpu_flags
))
4636 as_bad ((flag_code
!= CODE_64BIT
4637 ? _("`%s' is only supported in 64-bit mode")
4638 : _("`%s' is not supported in 64-bit mode")),
4639 current_templates
->start
->name
);
4642 /* If we are in 16-bit mode, do not allow addr16 or data16.
4643 Similarly, in 32-bit mode, do not allow addr32 or data32. */
4644 if ((current_templates
->start
->opcode_modifier
.size
== SIZE16
4645 || current_templates
->start
->opcode_modifier
.size
== SIZE32
)
4646 && flag_code
!= CODE_64BIT
4647 && ((current_templates
->start
->opcode_modifier
.size
== SIZE32
)
4648 ^ (flag_code
== CODE_16BIT
)))
4650 as_bad (_("redundant %s prefix"),
4651 current_templates
->start
->name
);
4654 if (current_templates
->start
->opcode_length
== 0)
4656 /* Handle pseudo prefixes. */
4657 switch (current_templates
->start
->base_opcode
)
4661 i
.disp_encoding
= disp_encoding_8bit
;
4665 i
.disp_encoding
= disp_encoding_32bit
;
4669 i
.dir_encoding
= dir_encoding_load
;
4673 i
.dir_encoding
= dir_encoding_store
;
4677 i
.vec_encoding
= vex_encoding_vex2
;
4681 i
.vec_encoding
= vex_encoding_vex3
;
4685 i
.vec_encoding
= vex_encoding_evex
;
4689 i
.rex_encoding
= TRUE
;
4693 i
.no_optimize
= TRUE
;
4701 /* Add prefix, checking for repeated prefixes. */
4702 switch (add_prefix (current_templates
->start
->base_opcode
))
4707 if (current_templates
->start
->cpu_flags
.bitfield
.cpuibt
)
4708 i
.notrack_prefix
= current_templates
->start
->name
;
4711 if (current_templates
->start
->cpu_flags
.bitfield
.cpuhle
)
4712 i
.hle_prefix
= current_templates
->start
->name
;
4713 else if (current_templates
->start
->cpu_flags
.bitfield
.cpumpx
)
4714 i
.bnd_prefix
= current_templates
->start
->name
;
4716 i
.rep_prefix
= current_templates
->start
->name
;
4722 /* Skip past PREFIX_SEPARATOR and reset token_start. */
4729 if (!current_templates
)
4731 /* Deprecated functionality (new code should use pseudo-prefixes instead):
4732 Check if we should swap operand or force 32bit displacement in
4734 if (mnem_p
- 2 == dot_p
&& dot_p
[1] == 's')
4735 i
.dir_encoding
= dir_encoding_swap
;
4736 else if (mnem_p
- 3 == dot_p
4739 i
.disp_encoding
= disp_encoding_8bit
;
4740 else if (mnem_p
- 4 == dot_p
4744 i
.disp_encoding
= disp_encoding_32bit
;
4749 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
4752 if (!current_templates
)
4755 if (mnem_p
> mnemonic
)
4757 /* See if we can get a match by trimming off a suffix. */
4760 case WORD_MNEM_SUFFIX
:
4761 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
4762 i
.suffix
= SHORT_MNEM_SUFFIX
;
4765 case BYTE_MNEM_SUFFIX
:
4766 case QWORD_MNEM_SUFFIX
:
4767 i
.suffix
= mnem_p
[-1];
4769 current_templates
= (const templates
*) hash_find (op_hash
,
4772 case SHORT_MNEM_SUFFIX
:
4773 case LONG_MNEM_SUFFIX
:
4776 i
.suffix
= mnem_p
[-1];
4778 current_templates
= (const templates
*) hash_find (op_hash
,
4787 if (intel_float_operand (mnemonic
) == 1)
4788 i
.suffix
= SHORT_MNEM_SUFFIX
;
4790 i
.suffix
= LONG_MNEM_SUFFIX
;
4792 current_templates
= (const templates
*) hash_find (op_hash
,
4799 if (!current_templates
)
4801 as_bad (_("no such instruction: `%s'"), token_start
);
4806 if (current_templates
->start
->opcode_modifier
.jump
4807 || current_templates
->start
->opcode_modifier
.jumpbyte
)
4809 /* Check for a branch hint. We allow ",pt" and ",pn" for
4810 predict taken and predict not taken respectively.
4811 I'm not sure that branch hints actually do anything on loop
4812 and jcxz insns (JumpByte) for current Pentium4 chips. They
4813 may work in the future and it doesn't hurt to accept them
4815 if (l
[0] == ',' && l
[1] == 'p')
4819 if (!add_prefix (DS_PREFIX_OPCODE
))
4823 else if (l
[2] == 'n')
4825 if (!add_prefix (CS_PREFIX_OPCODE
))
4831 /* Any other comma loses. */
4834 as_bad (_("invalid character %s in mnemonic"),
4835 output_invalid (*l
));
4839 /* Check if instruction is supported on specified architecture. */
4841 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
4843 supported
|= cpu_flags_match (t
);
4844 if (supported
== CPU_FLAGS_PERFECT_MATCH
)
4846 if (!cpu_arch_flags
.bitfield
.cpui386
&& (flag_code
!= CODE_16BIT
))
4847 as_warn (_("use .code16 to ensure correct addressing mode"));
4853 if (!(supported
& CPU_FLAGS_64BIT_MATCH
))
4854 as_bad (flag_code
== CODE_64BIT
4855 ? _("`%s' is not supported in 64-bit mode")
4856 : _("`%s' is only supported in 64-bit mode"),
4857 current_templates
->start
->name
);
4859 as_bad (_("`%s' is not supported on `%s%s'"),
4860 current_templates
->start
->name
,
4861 cpu_arch_name
? cpu_arch_name
: default_arch
,
4862 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
4868 parse_operands (char *l
, const char *mnemonic
)
4872 /* 1 if operand is pending after ','. */
4873 unsigned int expecting_operand
= 0;
4875 /* Non-zero if operand parens not balanced. */
4876 unsigned int paren_not_balanced
;
4878 while (*l
!= END_OF_INSN
)
4880 /* Skip optional white space before operand. */
4881 if (is_space_char (*l
))
4883 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
&& *l
!= '"')
4885 as_bad (_("invalid character %s before operand %d"),
4886 output_invalid (*l
),
4890 token_start
= l
; /* After white space. */
4891 paren_not_balanced
= 0;
4892 while (paren_not_balanced
|| *l
!= ',')
4894 if (*l
== END_OF_INSN
)
4896 if (paren_not_balanced
)
4899 as_bad (_("unbalanced parenthesis in operand %d."),
4902 as_bad (_("unbalanced brackets in operand %d."),
4907 break; /* we are done */
4909 else if (!is_operand_char (*l
) && !is_space_char (*l
) && *l
!= '"')
4911 as_bad (_("invalid character %s in operand %d"),
4912 output_invalid (*l
),
4919 ++paren_not_balanced
;
4921 --paren_not_balanced
;
4926 ++paren_not_balanced
;
4928 --paren_not_balanced
;
4932 if (l
!= token_start
)
4933 { /* Yes, we've read in another operand. */
4934 unsigned int operand_ok
;
4935 this_operand
= i
.operands
++;
4936 if (i
.operands
> MAX_OPERANDS
)
4938 as_bad (_("spurious operands; (%d operands/instruction max)"),
4942 i
.types
[this_operand
].bitfield
.unspecified
= 1;
4943 /* Now parse operand adding info to 'i' as we go along. */
4944 END_STRING_AND_SAVE (l
);
4946 if (i
.mem_operands
> 1)
4948 as_bad (_("too many memory references for `%s'"),
4955 i386_intel_operand (token_start
,
4956 intel_float_operand (mnemonic
));
4958 operand_ok
= i386_att_operand (token_start
);
4960 RESTORE_END_STRING (l
);
4966 if (expecting_operand
)
4968 expecting_operand_after_comma
:
4969 as_bad (_("expecting operand after ','; got nothing"));
4974 as_bad (_("expecting operand before ','; got nothing"));
4979 /* Now *l must be either ',' or END_OF_INSN. */
4982 if (*++l
== END_OF_INSN
)
4984 /* Just skip it, if it's \n complain. */
4985 goto expecting_operand_after_comma
;
4987 expecting_operand
= 1;
4994 swap_2_operands (int xchg1
, int xchg2
)
4996 union i386_op temp_op
;
4997 i386_operand_type temp_type
;
4998 unsigned int temp_flags
;
4999 enum bfd_reloc_code_real temp_reloc
;
5001 temp_type
= i
.types
[xchg2
];
5002 i
.types
[xchg2
] = i
.types
[xchg1
];
5003 i
.types
[xchg1
] = temp_type
;
5005 temp_flags
= i
.flags
[xchg2
];
5006 i
.flags
[xchg2
] = i
.flags
[xchg1
];
5007 i
.flags
[xchg1
] = temp_flags
;
5009 temp_op
= i
.op
[xchg2
];
5010 i
.op
[xchg2
] = i
.op
[xchg1
];
5011 i
.op
[xchg1
] = temp_op
;
5013 temp_reloc
= i
.reloc
[xchg2
];
5014 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
5015 i
.reloc
[xchg1
] = temp_reloc
;
5019 if (i
.mask
->operand
== xchg1
)
5020 i
.mask
->operand
= xchg2
;
5021 else if (i
.mask
->operand
== xchg2
)
5022 i
.mask
->operand
= xchg1
;
5026 if (i
.broadcast
->operand
== xchg1
)
5027 i
.broadcast
->operand
= xchg2
;
5028 else if (i
.broadcast
->operand
== xchg2
)
5029 i
.broadcast
->operand
= xchg1
;
5033 if (i
.rounding
->operand
== xchg1
)
5034 i
.rounding
->operand
= xchg2
;
5035 else if (i
.rounding
->operand
== xchg2
)
5036 i
.rounding
->operand
= xchg1
;
5041 swap_operands (void)
5047 swap_2_operands (1, i
.operands
- 2);
5051 swap_2_operands (0, i
.operands
- 1);
5057 if (i
.mem_operands
== 2)
5059 const seg_entry
*temp_seg
;
5060 temp_seg
= i
.seg
[0];
5061 i
.seg
[0] = i
.seg
[1];
5062 i
.seg
[1] = temp_seg
;
5066 /* Try to ensure constant immediates are represented in the smallest
5071 char guess_suffix
= 0;
5075 guess_suffix
= i
.suffix
;
5076 else if (i
.reg_operands
)
5078 /* Figure out a suffix from the last register operand specified.
5079 We can't do this properly yet, ie. excluding InOutPortReg,
5080 but the following works for instructions with immediates.
5081 In any case, we can't set i.suffix yet. */
5082 for (op
= i
.operands
; --op
>= 0;)
5083 if (i
.types
[op
].bitfield
.class != Reg
)
5085 else if (i
.types
[op
].bitfield
.byte
)
5087 guess_suffix
= BYTE_MNEM_SUFFIX
;
5090 else if (i
.types
[op
].bitfield
.word
)
5092 guess_suffix
= WORD_MNEM_SUFFIX
;
5095 else if (i
.types
[op
].bitfield
.dword
)
5097 guess_suffix
= LONG_MNEM_SUFFIX
;
5100 else if (i
.types
[op
].bitfield
.qword
)
5102 guess_suffix
= QWORD_MNEM_SUFFIX
;
5106 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
5107 guess_suffix
= WORD_MNEM_SUFFIX
;
5109 for (op
= i
.operands
; --op
>= 0;)
5110 if (operand_type_check (i
.types
[op
], imm
))
5112 switch (i
.op
[op
].imms
->X_op
)
5115 /* If a suffix is given, this operand may be shortened. */
5116 switch (guess_suffix
)
5118 case LONG_MNEM_SUFFIX
:
5119 i
.types
[op
].bitfield
.imm32
= 1;
5120 i
.types
[op
].bitfield
.imm64
= 1;
5122 case WORD_MNEM_SUFFIX
:
5123 i
.types
[op
].bitfield
.imm16
= 1;
5124 i
.types
[op
].bitfield
.imm32
= 1;
5125 i
.types
[op
].bitfield
.imm32s
= 1;
5126 i
.types
[op
].bitfield
.imm64
= 1;
5128 case BYTE_MNEM_SUFFIX
:
5129 i
.types
[op
].bitfield
.imm8
= 1;
5130 i
.types
[op
].bitfield
.imm8s
= 1;
5131 i
.types
[op
].bitfield
.imm16
= 1;
5132 i
.types
[op
].bitfield
.imm32
= 1;
5133 i
.types
[op
].bitfield
.imm32s
= 1;
5134 i
.types
[op
].bitfield
.imm64
= 1;
5138 /* If this operand is at most 16 bits, convert it
5139 to a signed 16 bit number before trying to see
5140 whether it will fit in an even smaller size.
5141 This allows a 16-bit operand such as $0xffe0 to
5142 be recognised as within Imm8S range. */
5143 if ((i
.types
[op
].bitfield
.imm16
)
5144 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
5146 i
.op
[op
].imms
->X_add_number
=
5147 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
5150 /* Store 32-bit immediate in 64-bit for 64-bit BFD. */
5151 if ((i
.types
[op
].bitfield
.imm32
)
5152 && ((i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1))
5155 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
5156 ^ ((offsetT
) 1 << 31))
5157 - ((offsetT
) 1 << 31));
5161 = operand_type_or (i
.types
[op
],
5162 smallest_imm_type (i
.op
[op
].imms
->X_add_number
));
5164 /* We must avoid matching of Imm32 templates when 64bit
5165 only immediate is available. */
5166 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
5167 i
.types
[op
].bitfield
.imm32
= 0;
5174 /* Symbols and expressions. */
5176 /* Convert symbolic operand to proper sizes for matching, but don't
5177 prevent matching a set of insns that only supports sizes other
5178 than those matching the insn suffix. */
5180 i386_operand_type mask
, allowed
;
5181 const insn_template
*t
;
5183 operand_type_set (&mask
, 0);
5184 operand_type_set (&allowed
, 0);
5186 for (t
= current_templates
->start
;
5187 t
< current_templates
->end
;
5190 allowed
= operand_type_or (allowed
, t
->operand_types
[op
]);
5191 allowed
= operand_type_and (allowed
, anyimm
);
5193 switch (guess_suffix
)
5195 case QWORD_MNEM_SUFFIX
:
5196 mask
.bitfield
.imm64
= 1;
5197 mask
.bitfield
.imm32s
= 1;
5199 case LONG_MNEM_SUFFIX
:
5200 mask
.bitfield
.imm32
= 1;
5202 case WORD_MNEM_SUFFIX
:
5203 mask
.bitfield
.imm16
= 1;
5205 case BYTE_MNEM_SUFFIX
:
5206 mask
.bitfield
.imm8
= 1;
5211 allowed
= operand_type_and (mask
, allowed
);
5212 if (!operand_type_all_zero (&allowed
))
5213 i
.types
[op
] = operand_type_and (i
.types
[op
], mask
);
5220 /* Try to use the smallest displacement type too. */
5222 optimize_disp (void)
5226 for (op
= i
.operands
; --op
>= 0;)
5227 if (operand_type_check (i
.types
[op
], disp
))
5229 if (i
.op
[op
].disps
->X_op
== O_constant
)
5231 offsetT op_disp
= i
.op
[op
].disps
->X_add_number
;
5233 if (i
.types
[op
].bitfield
.disp16
5234 && (op_disp
& ~(offsetT
) 0xffff) == 0)
5236 /* If this operand is at most 16 bits, convert
5237 to a signed 16 bit number and don't use 64bit
5239 op_disp
= (((op_disp
& 0xffff) ^ 0x8000) - 0x8000);
5240 i
.types
[op
].bitfield
.disp64
= 0;
5243 /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */
5244 if (i
.types
[op
].bitfield
.disp32
5245 && (op_disp
& ~(((offsetT
) 2 << 31) - 1)) == 0)
5247 /* If this operand is at most 32 bits, convert
5248 to a signed 32 bit number and don't use 64bit
5250 op_disp
&= (((offsetT
) 2 << 31) - 1);
5251 op_disp
= (op_disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
5252 i
.types
[op
].bitfield
.disp64
= 0;
5255 if (!op_disp
&& i
.types
[op
].bitfield
.baseindex
)
5257 i
.types
[op
].bitfield
.disp8
= 0;
5258 i
.types
[op
].bitfield
.disp16
= 0;
5259 i
.types
[op
].bitfield
.disp32
= 0;
5260 i
.types
[op
].bitfield
.disp32s
= 0;
5261 i
.types
[op
].bitfield
.disp64
= 0;
5265 else if (flag_code
== CODE_64BIT
)
5267 if (fits_in_signed_long (op_disp
))
5269 i
.types
[op
].bitfield
.disp64
= 0;
5270 i
.types
[op
].bitfield
.disp32s
= 1;
5272 if (i
.prefix
[ADDR_PREFIX
]
5273 && fits_in_unsigned_long (op_disp
))
5274 i
.types
[op
].bitfield
.disp32
= 1;
5276 if ((i
.types
[op
].bitfield
.disp32
5277 || i
.types
[op
].bitfield
.disp32s
5278 || i
.types
[op
].bitfield
.disp16
)
5279 && fits_in_disp8 (op_disp
))
5280 i
.types
[op
].bitfield
.disp8
= 1;
5282 else if (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
5283 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
)
5285 fix_new_exp (frag_now
, frag_more (0) - frag_now
->fr_literal
, 0,
5286 i
.op
[op
].disps
, 0, i
.reloc
[op
]);
5287 i
.types
[op
].bitfield
.disp8
= 0;
5288 i
.types
[op
].bitfield
.disp16
= 0;
5289 i
.types
[op
].bitfield
.disp32
= 0;
5290 i
.types
[op
].bitfield
.disp32s
= 0;
5291 i
.types
[op
].bitfield
.disp64
= 0;
5294 /* We only support 64bit displacement on constants. */
5295 i
.types
[op
].bitfield
.disp64
= 0;
5299 /* Return 1 if there is a match in broadcast bytes between operand
5300 GIVEN and instruction template T. */
5303 match_broadcast_size (const insn_template
*t
, unsigned int given
)
5305 return ((t
->opcode_modifier
.broadcast
== BYTE_BROADCAST
5306 && i
.types
[given
].bitfield
.byte
)
5307 || (t
->opcode_modifier
.broadcast
== WORD_BROADCAST
5308 && i
.types
[given
].bitfield
.word
)
5309 || (t
->opcode_modifier
.broadcast
== DWORD_BROADCAST
5310 && i
.types
[given
].bitfield
.dword
)
5311 || (t
->opcode_modifier
.broadcast
== QWORD_BROADCAST
5312 && i
.types
[given
].bitfield
.qword
));
5315 /* Check if operands are valid for the instruction. */
5318 check_VecOperands (const insn_template
*t
)
5322 static const i386_cpu_flags avx512
= CPU_ANY_AVX512F_FLAGS
;
5324 /* Templates allowing for ZMMword as well as YMMword and/or XMMword for
5325 any one operand are implicity requiring AVX512VL support if the actual
5326 operand size is YMMword or XMMword. Since this function runs after
5327 template matching, there's no need to check for YMMword/XMMword in
5329 cpu
= cpu_flags_and (t
->cpu_flags
, avx512
);
5330 if (!cpu_flags_all_zero (&cpu
)
5331 && !t
->cpu_flags
.bitfield
.cpuavx512vl
5332 && !cpu_arch_flags
.bitfield
.cpuavx512vl
)
5334 for (op
= 0; op
< t
->operands
; ++op
)
5336 if (t
->operand_types
[op
].bitfield
.zmmword
5337 && (i
.types
[op
].bitfield
.ymmword
5338 || i
.types
[op
].bitfield
.xmmword
))
5340 i
.error
= unsupported
;
5346 /* Without VSIB byte, we can't have a vector register for index. */
5347 if (!t
->opcode_modifier
.vecsib
5349 && (i
.index_reg
->reg_type
.bitfield
.xmmword
5350 || i
.index_reg
->reg_type
.bitfield
.ymmword
5351 || i
.index_reg
->reg_type
.bitfield
.zmmword
))
5353 i
.error
= unsupported_vector_index_register
;
5357 /* Check if default mask is allowed. */
5358 if (t
->opcode_modifier
.nodefmask
5359 && (!i
.mask
|| i
.mask
->mask
->reg_num
== 0))
5361 i
.error
= no_default_mask
;
5365 /* For VSIB byte, we need a vector register for index, and all vector
5366 registers must be distinct. */
5367 if (t
->opcode_modifier
.vecsib
)
5370 || !((t
->opcode_modifier
.vecsib
== VecSIB128
5371 && i
.index_reg
->reg_type
.bitfield
.xmmword
)
5372 || (t
->opcode_modifier
.vecsib
== VecSIB256
5373 && i
.index_reg
->reg_type
.bitfield
.ymmword
)
5374 || (t
->opcode_modifier
.vecsib
== VecSIB512
5375 && i
.index_reg
->reg_type
.bitfield
.zmmword
)))
5377 i
.error
= invalid_vsib_address
;
5381 gas_assert (i
.reg_operands
== 2 || i
.mask
);
5382 if (i
.reg_operands
== 2 && !i
.mask
)
5384 gas_assert (i
.types
[0].bitfield
.class == RegSIMD
);
5385 gas_assert (i
.types
[0].bitfield
.xmmword
5386 || i
.types
[0].bitfield
.ymmword
);
5387 gas_assert (i
.types
[2].bitfield
.class == RegSIMD
);
5388 gas_assert (i
.types
[2].bitfield
.xmmword
5389 || i
.types
[2].bitfield
.ymmword
);
5390 if (operand_check
== check_none
)
5392 if (register_number (i
.op
[0].regs
)
5393 != register_number (i
.index_reg
)
5394 && register_number (i
.op
[2].regs
)
5395 != register_number (i
.index_reg
)
5396 && register_number (i
.op
[0].regs
)
5397 != register_number (i
.op
[2].regs
))
5399 if (operand_check
== check_error
)
5401 i
.error
= invalid_vector_register_set
;
5404 as_warn (_("mask, index, and destination registers should be distinct"));
5406 else if (i
.reg_operands
== 1 && i
.mask
)
5408 if (i
.types
[1].bitfield
.class == RegSIMD
5409 && (i
.types
[1].bitfield
.xmmword
5410 || i
.types
[1].bitfield
.ymmword
5411 || i
.types
[1].bitfield
.zmmword
)
5412 && (register_number (i
.op
[1].regs
)
5413 == register_number (i
.index_reg
)))
5415 if (operand_check
== check_error
)
5417 i
.error
= invalid_vector_register_set
;
5420 if (operand_check
!= check_none
)
5421 as_warn (_("index and destination registers should be distinct"));
5426 /* Check if broadcast is supported by the instruction and is applied
5427 to the memory operand. */
5430 i386_operand_type type
, overlap
;
5432 /* Check if specified broadcast is supported in this instruction,
5433 and its broadcast bytes match the memory operand. */
5434 op
= i
.broadcast
->operand
;
5435 if (!t
->opcode_modifier
.broadcast
5436 || !(i
.flags
[op
] & Operand_Mem
)
5437 || (!i
.types
[op
].bitfield
.unspecified
5438 && !match_broadcast_size (t
, op
)))
5441 i
.error
= unsupported_broadcast
;
5445 i
.broadcast
->bytes
= ((1 << (t
->opcode_modifier
.broadcast
- 1))
5446 * i
.broadcast
->type
);
5447 operand_type_set (&type
, 0);
5448 switch (i
.broadcast
->bytes
)
5451 type
.bitfield
.word
= 1;
5454 type
.bitfield
.dword
= 1;
5457 type
.bitfield
.qword
= 1;
5460 type
.bitfield
.xmmword
= 1;
5463 type
.bitfield
.ymmword
= 1;
5466 type
.bitfield
.zmmword
= 1;
5472 overlap
= operand_type_and (type
, t
->operand_types
[op
]);
5473 if (operand_type_all_zero (&overlap
))
5476 if (t
->opcode_modifier
.checkregsize
)
5480 type
.bitfield
.baseindex
= 1;
5481 for (j
= 0; j
< i
.operands
; ++j
)
5484 && !operand_type_register_match(i
.types
[j
],
5485 t
->operand_types
[j
],
5487 t
->operand_types
[op
]))
5492 /* If broadcast is supported in this instruction, we need to check if
5493 operand of one-element size isn't specified without broadcast. */
5494 else if (t
->opcode_modifier
.broadcast
&& i
.mem_operands
)
5496 /* Find memory operand. */
5497 for (op
= 0; op
< i
.operands
; op
++)
5498 if (i
.flags
[op
] & Operand_Mem
)
5500 gas_assert (op
< i
.operands
);
5501 /* Check size of the memory operand. */
5502 if (match_broadcast_size (t
, op
))
5504 i
.error
= broadcast_needed
;
5509 op
= MAX_OPERANDS
- 1; /* Avoid uninitialized variable warning. */
5511 /* Check if requested masking is supported. */
5514 switch (t
->opcode_modifier
.masking
)
5518 case MERGING_MASKING
:
5519 if (i
.mask
->zeroing
)
5522 i
.error
= unsupported_masking
;
5526 case DYNAMIC_MASKING
:
5527 /* Memory destinations allow only merging masking. */
5528 if (i
.mask
->zeroing
&& i
.mem_operands
)
5530 /* Find memory operand. */
5531 for (op
= 0; op
< i
.operands
; op
++)
5532 if (i
.flags
[op
] & Operand_Mem
)
5534 gas_assert (op
< i
.operands
);
5535 if (op
== i
.operands
- 1)
5537 i
.error
= unsupported_masking
;
5547 /* Check if masking is applied to dest operand. */
5548 if (i
.mask
&& (i
.mask
->operand
!= (int) (i
.operands
- 1)))
5550 i
.error
= mask_not_on_destination
;
5557 if (!t
->opcode_modifier
.sae
5558 || (i
.rounding
->type
!= saeonly
&& !t
->opcode_modifier
.staticrounding
))
5560 i
.error
= unsupported_rc_sae
;
5563 /* If the instruction has several immediate operands and one of
5564 them is rounding, the rounding operand should be the last
5565 immediate operand. */
5566 if (i
.imm_operands
> 1
5567 && i
.rounding
->operand
!= (int) (i
.imm_operands
- 1))
5569 i
.error
= rc_sae_operand_not_last_imm
;
5574 /* Check vector Disp8 operand. */
5575 if (t
->opcode_modifier
.disp8memshift
5576 && i
.disp_encoding
!= disp_encoding_32bit
)
5579 i
.memshift
= t
->opcode_modifier
.broadcast
- 1;
5580 else if (t
->opcode_modifier
.disp8memshift
!= DISP8_SHIFT_VL
)
5581 i
.memshift
= t
->opcode_modifier
.disp8memshift
;
5584 const i386_operand_type
*type
= NULL
;
5587 for (op
= 0; op
< i
.operands
; op
++)
5588 if (i
.flags
[op
] & Operand_Mem
)
5590 if (t
->opcode_modifier
.evex
== EVEXLIG
)
5591 i
.memshift
= 2 + (i
.suffix
== QWORD_MNEM_SUFFIX
);
5592 else if (t
->operand_types
[op
].bitfield
.xmmword
5593 + t
->operand_types
[op
].bitfield
.ymmword
5594 + t
->operand_types
[op
].bitfield
.zmmword
<= 1)
5595 type
= &t
->operand_types
[op
];
5596 else if (!i
.types
[op
].bitfield
.unspecified
)
5597 type
= &i
.types
[op
];
5599 else if (i
.types
[op
].bitfield
.class == RegSIMD
5600 && t
->opcode_modifier
.evex
!= EVEXLIG
)
5602 if (i
.types
[op
].bitfield
.zmmword
)
5604 else if (i
.types
[op
].bitfield
.ymmword
&& i
.memshift
< 5)
5606 else if (i
.types
[op
].bitfield
.xmmword
&& i
.memshift
< 4)
5612 if (type
->bitfield
.zmmword
)
5614 else if (type
->bitfield
.ymmword
)
5616 else if (type
->bitfield
.xmmword
)
5620 /* For the check in fits_in_disp8(). */
5621 if (i
.memshift
== 0)
5625 for (op
= 0; op
< i
.operands
; op
++)
5626 if (operand_type_check (i
.types
[op
], disp
)
5627 && i
.op
[op
].disps
->X_op
== O_constant
)
5629 if (fits_in_disp8 (i
.op
[op
].disps
->X_add_number
))
5631 i
.types
[op
].bitfield
.disp8
= 1;
5634 i
.types
[op
].bitfield
.disp8
= 0;
5643 /* Check if operands are valid for the instruction. Update VEX
5647 VEX_check_operands (const insn_template
*t
)
5649 if (i
.vec_encoding
== vex_encoding_evex
)
5651 /* This instruction must be encoded with EVEX prefix. */
5652 if (!is_evex_encoding (t
))
5654 i
.error
= unsupported
;
5660 if (!t
->opcode_modifier
.vex
)
5662 /* This instruction template doesn't have VEX prefix. */
5663 if (i
.vec_encoding
!= vex_encoding_default
)
5665 i
.error
= unsupported
;
5671 /* Check the special Imm4 cases; must be the first operand. */
5672 if (t
->cpu_flags
.bitfield
.cpuxop
&& t
->operands
== 5)
5674 if (i
.op
[0].imms
->X_op
!= O_constant
5675 || !fits_in_imm4 (i
.op
[0].imms
->X_add_number
))
5681 /* Turn off Imm<N> so that update_imm won't complain. */
5682 operand_type_set (&i
.types
[0], 0);
5688 static const insn_template
*
5689 match_template (char mnem_suffix
)
5691 /* Points to template once we've found it. */
5692 const insn_template
*t
;
5693 i386_operand_type overlap0
, overlap1
, overlap2
, overlap3
;
5694 i386_operand_type overlap4
;
5695 unsigned int found_reverse_match
;
5696 i386_opcode_modifier suffix_check
;
5697 i386_operand_type operand_types
[MAX_OPERANDS
];
5698 int addr_prefix_disp
;
5700 unsigned int found_cpu_match
, size_match
;
5701 unsigned int check_register
;
5702 enum i386_error specific_error
= 0;
5704 #if MAX_OPERANDS != 5
5705 # error "MAX_OPERANDS must be 5."
5708 found_reverse_match
= 0;
5709 addr_prefix_disp
= -1;
5711 /* Prepare for mnemonic suffix check. */
5712 memset (&suffix_check
, 0, sizeof (suffix_check
));
5713 switch (mnem_suffix
)
5715 case BYTE_MNEM_SUFFIX
:
5716 suffix_check
.no_bsuf
= 1;
5718 case WORD_MNEM_SUFFIX
:
5719 suffix_check
.no_wsuf
= 1;
5721 case SHORT_MNEM_SUFFIX
:
5722 suffix_check
.no_ssuf
= 1;
5724 case LONG_MNEM_SUFFIX
:
5725 suffix_check
.no_lsuf
= 1;
5727 case QWORD_MNEM_SUFFIX
:
5728 suffix_check
.no_qsuf
= 1;
5731 /* NB: In Intel syntax, normally we can check for memory operand
5732 size when there is no mnemonic suffix. But jmp and call have
5733 2 different encodings with Dword memory operand size, one with
5734 No_ldSuf and the other without. i.suffix is set to
5735 LONG_DOUBLE_MNEM_SUFFIX to skip the one with No_ldSuf. */
5736 if (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
)
5737 suffix_check
.no_ldsuf
= 1;
5740 /* Must have right number of operands. */
5741 i
.error
= number_of_operands_mismatch
;
5743 for (t
= current_templates
->start
; t
< current_templates
->end
; t
++)
5745 addr_prefix_disp
= -1;
5746 found_reverse_match
= 0;
5748 if (i
.operands
!= t
->operands
)
5751 /* Check processor support. */
5752 i
.error
= unsupported
;
5753 found_cpu_match
= (cpu_flags_match (t
)
5754 == CPU_FLAGS_PERFECT_MATCH
);
5755 if (!found_cpu_match
)
5758 /* Check AT&T mnemonic. */
5759 i
.error
= unsupported_with_intel_mnemonic
;
5760 if (intel_mnemonic
&& t
->opcode_modifier
.attmnemonic
)
5763 /* Check AT&T/Intel syntax and Intel64/AMD64 ISA. */
5764 i
.error
= unsupported_syntax
;
5765 if ((intel_syntax
&& t
->opcode_modifier
.attsyntax
)
5766 || (!intel_syntax
&& t
->opcode_modifier
.intelsyntax
)
5767 || (intel64
&& t
->opcode_modifier
.amd64
)
5768 || (!intel64
&& t
->opcode_modifier
.intel64
))
5771 /* Check the suffix. */
5772 i
.error
= invalid_instruction_suffix
;
5773 if ((t
->opcode_modifier
.no_bsuf
&& suffix_check
.no_bsuf
)
5774 || (t
->opcode_modifier
.no_wsuf
&& suffix_check
.no_wsuf
)
5775 || (t
->opcode_modifier
.no_lsuf
&& suffix_check
.no_lsuf
)
5776 || (t
->opcode_modifier
.no_ssuf
&& suffix_check
.no_ssuf
)
5777 || (t
->opcode_modifier
.no_qsuf
&& suffix_check
.no_qsuf
)
5778 || (t
->opcode_modifier
.no_ldsuf
&& suffix_check
.no_ldsuf
))
5781 size_match
= operand_size_match (t
);
5785 for (j
= 0; j
< MAX_OPERANDS
; j
++)
5786 operand_types
[j
] = t
->operand_types
[j
];
5788 /* In general, don't allow 64-bit operands in 32-bit mode. */
5789 if (i
.suffix
== QWORD_MNEM_SUFFIX
5790 && flag_code
!= CODE_64BIT
5792 ? (!t
->opcode_modifier
.ignoresize
5793 && !t
->opcode_modifier
.broadcast
5794 && !intel_float_operand (t
->name
))
5795 : intel_float_operand (t
->name
) != 2)
5796 && ((operand_types
[0].bitfield
.class != RegMMX
5797 && operand_types
[0].bitfield
.class != RegSIMD
)
5798 || (operand_types
[t
->operands
> 1].bitfield
.class != RegMMX
5799 && operand_types
[t
->operands
> 1].bitfield
.class != RegSIMD
))
5800 && (t
->base_opcode
!= 0x0fc7
5801 || t
->extension_opcode
!= 1 /* cmpxchg8b */))
5804 /* In general, don't allow 32-bit operands on pre-386. */
5805 else if (i
.suffix
== LONG_MNEM_SUFFIX
5806 && !cpu_arch_flags
.bitfield
.cpui386
5808 ? (!t
->opcode_modifier
.ignoresize
5809 && !intel_float_operand (t
->name
))
5810 : intel_float_operand (t
->name
) != 2)
5811 && ((operand_types
[0].bitfield
.class != RegMMX
5812 && operand_types
[0].bitfield
.class != RegSIMD
)
5813 || (operand_types
[t
->operands
> 1].bitfield
.class != RegMMX
5814 && operand_types
[t
->operands
> 1].bitfield
.class
5818 /* Do not verify operands when there are none. */
5822 /* We've found a match; break out of loop. */
5826 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
5827 into Disp32/Disp16/Disp32 operand. */
5828 if (i
.prefix
[ADDR_PREFIX
] != 0)
5830 /* There should be only one Disp operand. */
5834 for (j
= 0; j
< MAX_OPERANDS
; j
++)
5836 if (operand_types
[j
].bitfield
.disp16
)
5838 addr_prefix_disp
= j
;
5839 operand_types
[j
].bitfield
.disp32
= 1;
5840 operand_types
[j
].bitfield
.disp16
= 0;
5846 for (j
= 0; j
< MAX_OPERANDS
; j
++)
5848 if (operand_types
[j
].bitfield
.disp32
)
5850 addr_prefix_disp
= j
;
5851 operand_types
[j
].bitfield
.disp32
= 0;
5852 operand_types
[j
].bitfield
.disp16
= 1;
5858 for (j
= 0; j
< MAX_OPERANDS
; j
++)
5860 if (operand_types
[j
].bitfield
.disp64
)
5862 addr_prefix_disp
= j
;
5863 operand_types
[j
].bitfield
.disp64
= 0;
5864 operand_types
[j
].bitfield
.disp32
= 1;
5872 /* Force 0x8b encoding for "mov foo@GOT, %eax". */
5873 if (i
.reloc
[0] == BFD_RELOC_386_GOT32
&& t
->base_opcode
== 0xa0)
5876 /* We check register size if needed. */
5877 if (t
->opcode_modifier
.checkregsize
)
5879 check_register
= (1 << t
->operands
) - 1;
5881 check_register
&= ~(1 << i
.broadcast
->operand
);
5886 overlap0
= operand_type_and (i
.types
[0], operand_types
[0]);
5887 switch (t
->operands
)
5890 if (!operand_type_match (overlap0
, i
.types
[0]))
5894 /* xchg %eax, %eax is a special case. It is an alias for nop
5895 only in 32bit mode and we can use opcode 0x90. In 64bit
5896 mode, we can't use 0x90 for xchg %eax, %eax since it should
5897 zero-extend %eax to %rax. */
5898 if (flag_code
== CODE_64BIT
5899 && t
->base_opcode
== 0x90
5900 && i
.types
[0].bitfield
.acc
&& i
.types
[0].bitfield
.dword
5901 && i
.types
[1].bitfield
.acc
&& i
.types
[1].bitfield
.dword
)
5903 /* xrelease mov %eax, <disp> is another special case. It must not
5904 match the accumulator-only encoding of mov. */
5905 if (flag_code
!= CODE_64BIT
5907 && t
->base_opcode
== 0xa0
5908 && i
.types
[0].bitfield
.acc
5909 && (i
.flags
[1] & Operand_Mem
))
5914 if (!(size_match
& MATCH_STRAIGHT
))
5916 /* Reverse direction of operands if swapping is possible in the first
5917 place (operands need to be symmetric) and
5918 - the load form is requested, and the template is a store form,
5919 - the store form is requested, and the template is a load form,
5920 - the non-default (swapped) form is requested. */
5921 overlap1
= operand_type_and (operand_types
[0], operand_types
[1]);
5922 if (t
->opcode_modifier
.d
&& i
.reg_operands
== i
.operands
5923 && !operand_type_all_zero (&overlap1
))
5924 switch (i
.dir_encoding
)
5926 case dir_encoding_load
:
5927 if (operand_type_check (operand_types
[i
.operands
- 1], anymem
)
5928 || t
->opcode_modifier
.regmem
)
5932 case dir_encoding_store
:
5933 if (!operand_type_check (operand_types
[i
.operands
- 1], anymem
)
5934 && !t
->opcode_modifier
.regmem
)
5938 case dir_encoding_swap
:
5941 case dir_encoding_default
:
5944 /* If we want store form, we skip the current load. */
5945 if ((i
.dir_encoding
== dir_encoding_store
5946 || i
.dir_encoding
== dir_encoding_swap
)
5947 && i
.mem_operands
== 0
5948 && t
->opcode_modifier
.load
)
5953 overlap1
= operand_type_and (i
.types
[1], operand_types
[1]);
5954 if (!operand_type_match (overlap0
, i
.types
[0])
5955 || !operand_type_match (overlap1
, i
.types
[1])
5956 || ((check_register
& 3) == 3
5957 && !operand_type_register_match (i
.types
[0],
5962 /* Check if other direction is valid ... */
5963 if (!t
->opcode_modifier
.d
)
5967 if (!(size_match
& MATCH_REVERSE
))
5969 /* Try reversing direction of operands. */
5970 overlap0
= operand_type_and (i
.types
[0], operand_types
[i
.operands
- 1]);
5971 overlap1
= operand_type_and (i
.types
[i
.operands
- 1], operand_types
[0]);
5972 if (!operand_type_match (overlap0
, i
.types
[0])
5973 || !operand_type_match (overlap1
, i
.types
[i
.operands
- 1])
5975 && !operand_type_register_match (i
.types
[0],
5976 operand_types
[i
.operands
- 1],
5977 i
.types
[i
.operands
- 1],
5980 /* Does not match either direction. */
5983 /* found_reverse_match holds which of D or FloatR
5985 if (!t
->opcode_modifier
.d
)
5986 found_reverse_match
= 0;
5987 else if (operand_types
[0].bitfield
.tbyte
)
5988 found_reverse_match
= Opcode_FloatD
;
5989 else if (operand_types
[0].bitfield
.xmmword
5990 || operand_types
[i
.operands
- 1].bitfield
.xmmword
5991 || operand_types
[0].bitfield
.class == RegMMX
5992 || operand_types
[i
.operands
- 1].bitfield
.class == RegMMX
5993 || is_any_vex_encoding(t
))
5994 found_reverse_match
= (t
->base_opcode
& 0xee) != 0x6e
5995 ? Opcode_SIMD_FloatD
: Opcode_SIMD_IntD
;
5997 found_reverse_match
= Opcode_D
;
5998 if (t
->opcode_modifier
.floatr
)
5999 found_reverse_match
|= Opcode_FloatR
;
6003 /* Found a forward 2 operand match here. */
6004 switch (t
->operands
)
6007 overlap4
= operand_type_and (i
.types
[4],
6011 overlap3
= operand_type_and (i
.types
[3],
6015 overlap2
= operand_type_and (i
.types
[2],
6020 switch (t
->operands
)
6023 if (!operand_type_match (overlap4
, i
.types
[4])
6024 || !operand_type_register_match (i
.types
[3],
6031 if (!operand_type_match (overlap3
, i
.types
[3])
6032 || ((check_register
& 0xa) == 0xa
6033 && !operand_type_register_match (i
.types
[1],
6037 || ((check_register
& 0xc) == 0xc
6038 && !operand_type_register_match (i
.types
[2],
6045 /* Here we make use of the fact that there are no
6046 reverse match 3 operand instructions. */
6047 if (!operand_type_match (overlap2
, i
.types
[2])
6048 || ((check_register
& 5) == 5
6049 && !operand_type_register_match (i
.types
[0],
6053 || ((check_register
& 6) == 6
6054 && !operand_type_register_match (i
.types
[1],
6062 /* Found either forward/reverse 2, 3 or 4 operand match here:
6063 slip through to break. */
6065 if (!found_cpu_match
)
6068 /* Check if vector and VEX operands are valid. */
6069 if (check_VecOperands (t
) || VEX_check_operands (t
))
6071 specific_error
= i
.error
;
6075 /* We've found a match; break out of loop. */
6079 if (t
== current_templates
->end
)
6081 /* We found no match. */
6082 const char *err_msg
;
6083 switch (specific_error
? specific_error
: i
.error
)
6087 case operand_size_mismatch
:
6088 err_msg
= _("operand size mismatch");
6090 case operand_type_mismatch
:
6091 err_msg
= _("operand type mismatch");
6093 case register_type_mismatch
:
6094 err_msg
= _("register type mismatch");
6096 case number_of_operands_mismatch
:
6097 err_msg
= _("number of operands mismatch");
6099 case invalid_instruction_suffix
:
6100 err_msg
= _("invalid instruction suffix");
6103 err_msg
= _("constant doesn't fit in 4 bits");
6105 case unsupported_with_intel_mnemonic
:
6106 err_msg
= _("unsupported with Intel mnemonic");
6108 case unsupported_syntax
:
6109 err_msg
= _("unsupported syntax");
6112 as_bad (_("unsupported instruction `%s'"),
6113 current_templates
->start
->name
);
6115 case invalid_vsib_address
:
6116 err_msg
= _("invalid VSIB address");
6118 case invalid_vector_register_set
:
6119 err_msg
= _("mask, index, and destination registers must be distinct");
6121 case unsupported_vector_index_register
:
6122 err_msg
= _("unsupported vector index register");
6124 case unsupported_broadcast
:
6125 err_msg
= _("unsupported broadcast");
6127 case broadcast_needed
:
6128 err_msg
= _("broadcast is needed for operand of such type");
6130 case unsupported_masking
:
6131 err_msg
= _("unsupported masking");
6133 case mask_not_on_destination
:
6134 err_msg
= _("mask not on destination operand");
6136 case no_default_mask
:
6137 err_msg
= _("default mask isn't allowed");
6139 case unsupported_rc_sae
:
6140 err_msg
= _("unsupported static rounding/sae");
6142 case rc_sae_operand_not_last_imm
:
6144 err_msg
= _("RC/SAE operand must precede immediate operands");
6146 err_msg
= _("RC/SAE operand must follow immediate operands");
6148 case invalid_register_operand
:
6149 err_msg
= _("invalid register operand");
6152 as_bad (_("%s for `%s'"), err_msg
,
6153 current_templates
->start
->name
);
6157 if (!quiet_warnings
)
6160 && (i
.types
[0].bitfield
.jumpabsolute
6161 != operand_types
[0].bitfield
.jumpabsolute
))
6163 as_warn (_("indirect %s without `*'"), t
->name
);
6166 if (t
->opcode_modifier
.isprefix
6167 && t
->opcode_modifier
.ignoresize
)
6169 /* Warn them that a data or address size prefix doesn't
6170 affect assembly of the next line of code. */
6171 as_warn (_("stand-alone `%s' prefix"), t
->name
);
6175 /* Copy the template we found. */
6178 if (addr_prefix_disp
!= -1)
6179 i
.tm
.operand_types
[addr_prefix_disp
]
6180 = operand_types
[addr_prefix_disp
];
6182 if (found_reverse_match
)
6184 /* If we found a reverse match we must alter the opcode direction
6185 bit and clear/flip the regmem modifier one. found_reverse_match
6186 holds bits to change (different for int & float insns). */
6188 i
.tm
.base_opcode
^= found_reverse_match
;
6190 i
.tm
.operand_types
[0] = operand_types
[i
.operands
- 1];
6191 i
.tm
.operand_types
[i
.operands
- 1] = operand_types
[0];
6193 /* Certain SIMD insns have their load forms specified in the opcode
6194 table, and hence we need to _set_ RegMem instead of clearing it.
6195 We need to avoid setting the bit though on insns like KMOVW. */
6196 i
.tm
.opcode_modifier
.regmem
6197 = i
.tm
.opcode_modifier
.modrm
&& i
.tm
.opcode_modifier
.d
6198 && i
.tm
.operands
> 2U - i
.tm
.opcode_modifier
.sse2avx
6199 && !i
.tm
.opcode_modifier
.regmem
;
6208 unsigned int mem_op
= i
.flags
[0] & Operand_Mem
? 0 : 1;
6210 if (i
.tm
.operand_types
[mem_op
].bitfield
.esseg
)
6212 if (i
.seg
[0] != NULL
&& i
.seg
[0] != &es
)
6214 as_bad (_("`%s' operand %d must use `%ses' segment"),
6216 intel_syntax
? i
.tm
.operands
- mem_op
: mem_op
+ 1,
6220 /* There's only ever one segment override allowed per instruction.
6221 This instruction possibly has a legal segment override on the
6222 second operand, so copy the segment to where non-string
6223 instructions store it, allowing common code. */
6224 i
.seg
[0] = i
.seg
[1];
6226 else if (i
.tm
.operand_types
[mem_op
+ 1].bitfield
.esseg
)
6228 if (i
.seg
[1] != NULL
&& i
.seg
[1] != &es
)
6230 as_bad (_("`%s' operand %d must use `%ses' segment"),
6232 intel_syntax
? i
.tm
.operands
- mem_op
- 1 : mem_op
+ 2,
6241 process_suffix (void)
6243 /* If matched instruction specifies an explicit instruction mnemonic
6245 if (i
.tm
.opcode_modifier
.size
== SIZE16
)
6246 i
.suffix
= WORD_MNEM_SUFFIX
;
6247 else if (i
.tm
.opcode_modifier
.size
== SIZE32
)
6248 i
.suffix
= LONG_MNEM_SUFFIX
;
6249 else if (i
.tm
.opcode_modifier
.size
== SIZE64
)
6250 i
.suffix
= QWORD_MNEM_SUFFIX
;
6251 else if (i
.reg_operands
)
6253 /* If there's no instruction mnemonic suffix we try to invent one
6254 based on register operands. */
6257 /* We take i.suffix from the last register operand specified,
6258 Destination register type is more significant than source
6259 register type. crc32 in SSE4.2 prefers source register
6261 if (i
.tm
.base_opcode
== 0xf20f38f0
6262 && i
.types
[0].bitfield
.class == Reg
)
6264 if (i
.types
[0].bitfield
.byte
)
6265 i
.suffix
= BYTE_MNEM_SUFFIX
;
6266 else if (i
.types
[0].bitfield
.word
)
6267 i
.suffix
= WORD_MNEM_SUFFIX
;
6268 else if (i
.types
[0].bitfield
.dword
)
6269 i
.suffix
= LONG_MNEM_SUFFIX
;
6270 else if (i
.types
[0].bitfield
.qword
)
6271 i
.suffix
= QWORD_MNEM_SUFFIX
;
6278 if (i
.tm
.base_opcode
== 0xf20f38f0)
6280 /* We have to know the operand size for crc32. */
6281 as_bad (_("ambiguous memory operand size for `%s`"),
6286 for (op
= i
.operands
; --op
>= 0;)
6287 if (!i
.tm
.operand_types
[op
].bitfield
.inoutportreg
6288 && !i
.tm
.operand_types
[op
].bitfield
.shiftcount
)
6290 if (i
.types
[op
].bitfield
.class != Reg
)
6292 if (i
.types
[op
].bitfield
.byte
)
6293 i
.suffix
= BYTE_MNEM_SUFFIX
;
6294 else if (i
.types
[op
].bitfield
.word
)
6295 i
.suffix
= WORD_MNEM_SUFFIX
;
6296 else if (i
.types
[op
].bitfield
.dword
)
6297 i
.suffix
= LONG_MNEM_SUFFIX
;
6298 else if (i
.types
[op
].bitfield
.qword
)
6299 i
.suffix
= QWORD_MNEM_SUFFIX
;
6306 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
6309 && i
.tm
.opcode_modifier
.ignoresize
6310 && i
.tm
.opcode_modifier
.no_bsuf
)
6312 else if (!check_byte_reg ())
6315 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
6318 && i
.tm
.opcode_modifier
.ignoresize
6319 && i
.tm
.opcode_modifier
.no_lsuf
6320 && !i
.tm
.opcode_modifier
.todword
6321 && !i
.tm
.opcode_modifier
.toqword
)
6323 else if (!check_long_reg ())
6326 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
6329 && i
.tm
.opcode_modifier
.ignoresize
6330 && i
.tm
.opcode_modifier
.no_qsuf
6331 && !i
.tm
.opcode_modifier
.todword
6332 && !i
.tm
.opcode_modifier
.toqword
)
6334 else if (!check_qword_reg ())
6337 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
6340 && i
.tm
.opcode_modifier
.ignoresize
6341 && i
.tm
.opcode_modifier
.no_wsuf
)
6343 else if (!check_word_reg ())
6346 else if (intel_syntax
&& i
.tm
.opcode_modifier
.ignoresize
)
6347 /* Do nothing if the instruction is going to ignore the prefix. */
6352 else if (i
.tm
.opcode_modifier
.defaultsize
6354 /* exclude fldenv/frstor/fsave/fstenv */
6355 && i
.tm
.opcode_modifier
.no_ssuf
)
6357 if (stackop_size
== LONG_MNEM_SUFFIX
6358 && i
.tm
.base_opcode
== 0xcf)
6360 /* stackop_size is set to LONG_MNEM_SUFFIX for the
6361 .code16gcc directive to support 16-bit mode with
6362 32-bit address. For IRET without a suffix, generate
6363 16-bit IRET (opcode 0xcf) to return from an interrupt
6365 i
.suffix
= WORD_MNEM_SUFFIX
;
6366 as_warn (_("generating 16-bit `iret' for .code16gcc directive"));
6369 i
.suffix
= stackop_size
;
6371 else if (intel_syntax
6373 && (i
.tm
.operand_types
[0].bitfield
.jumpabsolute
6374 || i
.tm
.opcode_modifier
.jumpbyte
6375 || i
.tm
.opcode_modifier
.jumpintersegment
6376 || (i
.tm
.base_opcode
== 0x0f01 /* [ls][gi]dt */
6377 && i
.tm
.extension_opcode
<= 3)))
6382 if (!i
.tm
.opcode_modifier
.no_qsuf
)
6384 i
.suffix
= QWORD_MNEM_SUFFIX
;
6389 if (!i
.tm
.opcode_modifier
.no_lsuf
)
6390 i
.suffix
= LONG_MNEM_SUFFIX
;
6393 if (!i
.tm
.opcode_modifier
.no_wsuf
)
6394 i
.suffix
= WORD_MNEM_SUFFIX
;
6403 if (i
.tm
.opcode_modifier
.w
)
6405 as_bad (_("no instruction mnemonic suffix given and "
6406 "no register operands; can't size instruction"));
6412 unsigned int suffixes
;
6414 suffixes
= !i
.tm
.opcode_modifier
.no_bsuf
;
6415 if (!i
.tm
.opcode_modifier
.no_wsuf
)
6417 if (!i
.tm
.opcode_modifier
.no_lsuf
)
6419 if (!i
.tm
.opcode_modifier
.no_ldsuf
)
6421 if (!i
.tm
.opcode_modifier
.no_ssuf
)
6423 if (flag_code
== CODE_64BIT
&& !i
.tm
.opcode_modifier
.no_qsuf
)
6426 /* There are more than suffix matches. */
6427 if (i
.tm
.opcode_modifier
.w
6428 || ((suffixes
& (suffixes
- 1))
6429 && !i
.tm
.opcode_modifier
.defaultsize
6430 && !i
.tm
.opcode_modifier
.ignoresize
))
6432 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
6438 /* Change the opcode based on the operand size given by i.suffix. */
6441 /* Size floating point instruction. */
6442 case LONG_MNEM_SUFFIX
:
6443 if (i
.tm
.opcode_modifier
.floatmf
)
6445 i
.tm
.base_opcode
^= 4;
6449 case WORD_MNEM_SUFFIX
:
6450 case QWORD_MNEM_SUFFIX
:
6451 /* It's not a byte, select word/dword operation. */
6452 if (i
.tm
.opcode_modifier
.w
)
6454 if (i
.tm
.opcode_modifier
.shortform
)
6455 i
.tm
.base_opcode
|= 8;
6457 i
.tm
.base_opcode
|= 1;
6460 case SHORT_MNEM_SUFFIX
:
6461 /* Now select between word & dword operations via the operand
6462 size prefix, except for instructions that will ignore this
6464 if (i
.reg_operands
> 0
6465 && i
.types
[0].bitfield
.class == Reg
6466 && i
.tm
.opcode_modifier
.addrprefixopreg
6467 && (i
.tm
.opcode_modifier
.immext
6468 || i
.operands
== 1))
6470 /* The address size override prefix changes the size of the
6472 if ((flag_code
== CODE_32BIT
6473 && i
.op
[0].regs
->reg_type
.bitfield
.word
)
6474 || (flag_code
!= CODE_32BIT
6475 && i
.op
[0].regs
->reg_type
.bitfield
.dword
))
6476 if (!add_prefix (ADDR_PREFIX_OPCODE
))
6479 else if (i
.suffix
!= QWORD_MNEM_SUFFIX
6480 && !i
.tm
.opcode_modifier
.ignoresize
6481 && !i
.tm
.opcode_modifier
.floatmf
6482 && !is_any_vex_encoding (&i
.tm
)
6483 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
6484 || (flag_code
== CODE_64BIT
6485 && i
.tm
.opcode_modifier
.jumpbyte
)))
6487 unsigned int prefix
= DATA_PREFIX_OPCODE
;
6489 if (i
.tm
.opcode_modifier
.jumpbyte
) /* jcxz, loop */
6490 prefix
= ADDR_PREFIX_OPCODE
;
6492 if (!add_prefix (prefix
))
6496 /* Set mode64 for an operand. */
6497 if (i
.suffix
== QWORD_MNEM_SUFFIX
6498 && flag_code
== CODE_64BIT
6499 && !i
.tm
.opcode_modifier
.norex64
6500 /* Special case for xchg %rax,%rax. It is NOP and doesn't
6502 && ! (i
.operands
== 2
6503 && i
.tm
.base_opcode
== 0x90
6504 && i
.tm
.extension_opcode
== None
6505 && i
.types
[0].bitfield
.acc
&& i
.types
[0].bitfield
.qword
6506 && i
.types
[1].bitfield
.acc
&& i
.types
[1].bitfield
.qword
))
6512 if (i
.reg_operands
!= 0
6514 && i
.tm
.opcode_modifier
.addrprefixopreg
6515 && !i
.tm
.opcode_modifier
.immext
)
6517 /* Check invalid register operand when the address size override
6518 prefix changes the size of register operands. */
6520 enum { need_word
, need_dword
, need_qword
} need
;
6522 if (flag_code
== CODE_32BIT
)
6523 need
= i
.prefix
[ADDR_PREFIX
] ? need_word
: need_dword
;
6526 if (i
.prefix
[ADDR_PREFIX
])
6529 need
= flag_code
== CODE_64BIT
? need_qword
: need_word
;
6532 for (op
= 0; op
< i
.operands
; op
++)
6533 if (i
.types
[op
].bitfield
.class == Reg
6534 && ((need
== need_word
6535 && !i
.op
[op
].regs
->reg_type
.bitfield
.word
)
6536 || (need
== need_dword
6537 && !i
.op
[op
].regs
->reg_type
.bitfield
.dword
)
6538 || (need
== need_qword
6539 && !i
.op
[op
].regs
->reg_type
.bitfield
.qword
)))
6541 as_bad (_("invalid register operand size for `%s'"),
6551 check_byte_reg (void)
6555 for (op
= i
.operands
; --op
>= 0;)
6557 /* Skip non-register operands. */
6558 if (i
.types
[op
].bitfield
.class != Reg
)
6561 /* If this is an eight bit register, it's OK. If it's the 16 or
6562 32 bit version of an eight bit register, we will just use the
6563 low portion, and that's OK too. */
6564 if (i
.types
[op
].bitfield
.byte
)
6567 /* I/O port address operands are OK too. */
6568 if (i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
6571 /* crc32 doesn't generate this warning. */
6572 if (i
.tm
.base_opcode
== 0xf20f38f0)
6575 if ((i
.types
[op
].bitfield
.word
6576 || i
.types
[op
].bitfield
.dword
6577 || i
.types
[op
].bitfield
.qword
)
6578 && i
.op
[op
].regs
->reg_num
< 4
6579 /* Prohibit these changes in 64bit mode, since the lowering
6580 would be more complicated. */
6581 && flag_code
!= CODE_64BIT
)
6583 #if REGISTER_WARNINGS
6584 if (!quiet_warnings
)
6585 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6587 (i
.op
[op
].regs
+ (i
.types
[op
].bitfield
.word
6588 ? REGNAM_AL
- REGNAM_AX
6589 : REGNAM_AL
- REGNAM_EAX
))->reg_name
,
6591 i
.op
[op
].regs
->reg_name
,
6596 /* Any other register is bad. */
6597 if (i
.types
[op
].bitfield
.class == Reg
6598 || i
.types
[op
].bitfield
.class == RegMMX
6599 || i
.types
[op
].bitfield
.class == RegSIMD
6600 || i
.types
[op
].bitfield
.class == SReg
6601 || i
.types
[op
].bitfield
.class == RegCR
6602 || i
.types
[op
].bitfield
.class == RegDR
6603 || i
.types
[op
].bitfield
.class == RegTR
)
6605 as_bad (_("`%s%s' not allowed with `%s%c'"),
6607 i
.op
[op
].regs
->reg_name
,
6617 check_long_reg (void)
6621 for (op
= i
.operands
; --op
>= 0;)
6622 /* Skip non-register operands. */
6623 if (i
.types
[op
].bitfield
.class != Reg
)
6625 /* Reject eight bit registers, except where the template requires
6626 them. (eg. movzb) */
6627 else if (i
.types
[op
].bitfield
.byte
6628 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
6629 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6630 && (i
.tm
.operand_types
[op
].bitfield
.word
6631 || i
.tm
.operand_types
[op
].bitfield
.dword
))
6633 as_bad (_("`%s%s' not allowed with `%s%c'"),
6635 i
.op
[op
].regs
->reg_name
,
6640 /* Warn if the e prefix on a general reg is missing. */
6641 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
6642 && i
.types
[op
].bitfield
.word
6643 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
6644 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6645 && i
.tm
.operand_types
[op
].bitfield
.dword
)
6647 /* Prohibit these changes in the 64bit mode, since the
6648 lowering is more complicated. */
6649 if (flag_code
== CODE_64BIT
)
6651 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6652 register_prefix
, i
.op
[op
].regs
->reg_name
,
6656 #if REGISTER_WARNINGS
6657 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6659 (i
.op
[op
].regs
+ REGNAM_EAX
- REGNAM_AX
)->reg_name
,
6660 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
6663 /* Warn if the r prefix on a general reg is present. */
6664 else if (i
.types
[op
].bitfield
.qword
6665 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
6666 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6667 && i
.tm
.operand_types
[op
].bitfield
.dword
)
6670 && i
.tm
.opcode_modifier
.toqword
6671 && i
.types
[0].bitfield
.class != RegSIMD
)
6673 /* Convert to QWORD. We want REX byte. */
6674 i
.suffix
= QWORD_MNEM_SUFFIX
;
6678 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6679 register_prefix
, i
.op
[op
].regs
->reg_name
,
6688 check_qword_reg (void)
6692 for (op
= i
.operands
; --op
>= 0; )
6693 /* Skip non-register operands. */
6694 if (i
.types
[op
].bitfield
.class != Reg
)
6696 /* Reject eight bit registers, except where the template requires
6697 them. (eg. movzb) */
6698 else if (i
.types
[op
].bitfield
.byte
6699 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
6700 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6701 && (i
.tm
.operand_types
[op
].bitfield
.word
6702 || i
.tm
.operand_types
[op
].bitfield
.dword
))
6704 as_bad (_("`%s%s' not allowed with `%s%c'"),
6706 i
.op
[op
].regs
->reg_name
,
6711 /* Warn if the r prefix on a general reg is missing. */
6712 else if ((i
.types
[op
].bitfield
.word
6713 || i
.types
[op
].bitfield
.dword
)
6714 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
6715 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6716 && i
.tm
.operand_types
[op
].bitfield
.qword
)
6718 /* Prohibit these changes in the 64bit mode, since the
6719 lowering is more complicated. */
6721 && i
.tm
.opcode_modifier
.todword
6722 && i
.types
[0].bitfield
.class != RegSIMD
)
6724 /* Convert to DWORD. We don't want REX byte. */
6725 i
.suffix
= LONG_MNEM_SUFFIX
;
6729 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6730 register_prefix
, i
.op
[op
].regs
->reg_name
,
6739 check_word_reg (void)
6742 for (op
= i
.operands
; --op
>= 0;)
6743 /* Skip non-register operands. */
6744 if (i
.types
[op
].bitfield
.class != Reg
)
6746 /* Reject eight bit registers, except where the template requires
6747 them. (eg. movzb) */
6748 else if (i
.types
[op
].bitfield
.byte
6749 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
6750 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6751 && (i
.tm
.operand_types
[op
].bitfield
.word
6752 || i
.tm
.operand_types
[op
].bitfield
.dword
))
6754 as_bad (_("`%s%s' not allowed with `%s%c'"),
6756 i
.op
[op
].regs
->reg_name
,
6761 /* Warn if the e or r prefix on a general reg is present. */
6762 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
6763 && (i
.types
[op
].bitfield
.dword
6764 || i
.types
[op
].bitfield
.qword
)
6765 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
6766 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6767 && i
.tm
.operand_types
[op
].bitfield
.word
)
6769 /* Prohibit these changes in the 64bit mode, since the
6770 lowering is more complicated. */
6771 if (flag_code
== CODE_64BIT
)
6773 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6774 register_prefix
, i
.op
[op
].regs
->reg_name
,
6778 #if REGISTER_WARNINGS
6779 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6781 (i
.op
[op
].regs
+ REGNAM_AX
- REGNAM_EAX
)->reg_name
,
6782 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
6789 update_imm (unsigned int j
)
6791 i386_operand_type overlap
= i
.types
[j
];
6792 if ((overlap
.bitfield
.imm8
6793 || overlap
.bitfield
.imm8s
6794 || overlap
.bitfield
.imm16
6795 || overlap
.bitfield
.imm32
6796 || overlap
.bitfield
.imm32s
6797 || overlap
.bitfield
.imm64
)
6798 && !operand_type_equal (&overlap
, &imm8
)
6799 && !operand_type_equal (&overlap
, &imm8s
)
6800 && !operand_type_equal (&overlap
, &imm16
)
6801 && !operand_type_equal (&overlap
, &imm32
)
6802 && !operand_type_equal (&overlap
, &imm32s
)
6803 && !operand_type_equal (&overlap
, &imm64
))
6807 i386_operand_type temp
;
6809 operand_type_set (&temp
, 0);
6810 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
6812 temp
.bitfield
.imm8
= overlap
.bitfield
.imm8
;
6813 temp
.bitfield
.imm8s
= overlap
.bitfield
.imm8s
;
6815 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
6816 temp
.bitfield
.imm16
= overlap
.bitfield
.imm16
;
6817 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
6819 temp
.bitfield
.imm64
= overlap
.bitfield
.imm64
;
6820 temp
.bitfield
.imm32s
= overlap
.bitfield
.imm32s
;
6823 temp
.bitfield
.imm32
= overlap
.bitfield
.imm32
;
6826 else if (operand_type_equal (&overlap
, &imm16_32_32s
)
6827 || operand_type_equal (&overlap
, &imm16_32
)
6828 || operand_type_equal (&overlap
, &imm16_32s
))
6830 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
6835 if (!operand_type_equal (&overlap
, &imm8
)
6836 && !operand_type_equal (&overlap
, &imm8s
)
6837 && !operand_type_equal (&overlap
, &imm16
)
6838 && !operand_type_equal (&overlap
, &imm32
)
6839 && !operand_type_equal (&overlap
, &imm32s
)
6840 && !operand_type_equal (&overlap
, &imm64
))
6842 as_bad (_("no instruction mnemonic suffix given; "
6843 "can't determine immediate size"));
6847 i
.types
[j
] = overlap
;
6857 /* Update the first 2 immediate operands. */
6858 n
= i
.operands
> 2 ? 2 : i
.operands
;
6861 for (j
= 0; j
< n
; j
++)
6862 if (update_imm (j
) == 0)
6865 /* The 3rd operand can't be immediate operand. */
6866 gas_assert (operand_type_check (i
.types
[2], imm
) == 0);
6873 process_operands (void)
6875 /* Default segment register this instruction will use for memory
6876 accesses. 0 means unknown. This is only for optimizing out
6877 unnecessary segment overrides. */
6878 const seg_entry
*default_seg
= 0;
6880 if (i
.tm
.opcode_modifier
.sse2avx
&& i
.tm
.opcode_modifier
.vexvvvv
)
6882 unsigned int dupl
= i
.operands
;
6883 unsigned int dest
= dupl
- 1;
6886 /* The destination must be an xmm register. */
6887 gas_assert (i
.reg_operands
6888 && MAX_OPERANDS
> dupl
6889 && operand_type_equal (&i
.types
[dest
], ®xmm
));
6891 if (i
.tm
.operand_types
[0].bitfield
.acc
6892 && i
.tm
.operand_types
[0].bitfield
.xmmword
)
6894 if (i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
)
6896 /* Keep xmm0 for instructions with VEX prefix and 3
6898 i
.tm
.operand_types
[0].bitfield
.acc
= 0;
6899 i
.tm
.operand_types
[0].bitfield
.class = RegSIMD
;
6904 /* We remove the first xmm0 and keep the number of
6905 operands unchanged, which in fact duplicates the
6907 for (j
= 1; j
< i
.operands
; j
++)
6909 i
.op
[j
- 1] = i
.op
[j
];
6910 i
.types
[j
- 1] = i
.types
[j
];
6911 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
6912 i
.flags
[j
- 1] = i
.flags
[j
];
6916 else if (i
.tm
.opcode_modifier
.implicit1stxmm0
)
6918 gas_assert ((MAX_OPERANDS
- 1) > dupl
6919 && (i
.tm
.opcode_modifier
.vexsources
6922 /* Add the implicit xmm0 for instructions with VEX prefix
6924 for (j
= i
.operands
; j
> 0; j
--)
6926 i
.op
[j
] = i
.op
[j
- 1];
6927 i
.types
[j
] = i
.types
[j
- 1];
6928 i
.tm
.operand_types
[j
] = i
.tm
.operand_types
[j
- 1];
6929 i
.flags
[j
] = i
.flags
[j
- 1];
6932 = (const reg_entry
*) hash_find (reg_hash
, "xmm0");
6933 i
.types
[0] = regxmm
;
6934 i
.tm
.operand_types
[0] = regxmm
;
6937 i
.reg_operands
+= 2;
6942 i
.op
[dupl
] = i
.op
[dest
];
6943 i
.types
[dupl
] = i
.types
[dest
];
6944 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
6945 i
.flags
[dupl
] = i
.flags
[dest
];
6954 i
.op
[dupl
] = i
.op
[dest
];
6955 i
.types
[dupl
] = i
.types
[dest
];
6956 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
6957 i
.flags
[dupl
] = i
.flags
[dest
];
6960 if (i
.tm
.opcode_modifier
.immext
)
6963 else if (i
.tm
.operand_types
[0].bitfield
.acc
6964 && i
.tm
.operand_types
[0].bitfield
.xmmword
)
6968 for (j
= 1; j
< i
.operands
; j
++)
6970 i
.op
[j
- 1] = i
.op
[j
];
6971 i
.types
[j
- 1] = i
.types
[j
];
6973 /* We need to adjust fields in i.tm since they are used by
6974 build_modrm_byte. */
6975 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
6977 i
.flags
[j
- 1] = i
.flags
[j
];
6984 else if (i
.tm
.opcode_modifier
.implicitquadgroup
)
6986 unsigned int regnum
, first_reg_in_group
, last_reg_in_group
;
6988 /* The second operand must be {x,y,z}mmN, where N is a multiple of 4. */
6989 gas_assert (i
.operands
>= 2 && i
.types
[1].bitfield
.class == RegSIMD
);
6990 regnum
= register_number (i
.op
[1].regs
);
6991 first_reg_in_group
= regnum
& ~3;
6992 last_reg_in_group
= first_reg_in_group
+ 3;
6993 if (regnum
!= first_reg_in_group
)
6994 as_warn (_("source register `%s%s' implicitly denotes"
6995 " `%s%.3s%u' to `%s%.3s%u' source group in `%s'"),
6996 register_prefix
, i
.op
[1].regs
->reg_name
,
6997 register_prefix
, i
.op
[1].regs
->reg_name
, first_reg_in_group
,
6998 register_prefix
, i
.op
[1].regs
->reg_name
, last_reg_in_group
,
7001 else if (i
.tm
.opcode_modifier
.regkludge
)
7003 /* The imul $imm, %reg instruction is converted into
7004 imul $imm, %reg, %reg, and the clr %reg instruction
7005 is converted into xor %reg, %reg. */
7007 unsigned int first_reg_op
;
7009 if (operand_type_check (i
.types
[0], reg
))
7013 /* Pretend we saw the extra register operand. */
7014 gas_assert (i
.reg_operands
== 1
7015 && i
.op
[first_reg_op
+ 1].regs
== 0);
7016 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
7017 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
7022 if (i
.tm
.opcode_modifier
.modrm
)
7024 /* The opcode is completed (modulo i.tm.extension_opcode which
7025 must be put into the modrm byte). Now, we make the modrm and
7026 index base bytes based on all the info we've collected. */
7028 default_seg
= build_modrm_byte ();
7030 else if (i
.types
[0].bitfield
.class == SReg
)
7032 if (flag_code
!= CODE_64BIT
7033 ? i
.tm
.base_opcode
== POP_SEG_SHORT
7034 && i
.op
[0].regs
->reg_num
== 1
7035 : (i
.tm
.base_opcode
| 1) == POP_SEG386_SHORT
7036 && i
.op
[0].regs
->reg_num
< 4)
7038 as_bad (_("you can't `%s %s%s'"),
7039 i
.tm
.name
, register_prefix
, i
.op
[0].regs
->reg_name
);
7042 if ( i
.op
[0].regs
->reg_num
> 3 && i
.tm
.opcode_length
== 1 )
7044 i
.tm
.base_opcode
^= POP_SEG_SHORT
^ POP_SEG386_SHORT
;
7045 i
.tm
.opcode_length
= 2;
7047 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
7049 else if ((i
.tm
.base_opcode
& ~0x3) == MOV_AX_DISP32
)
7053 else if (i
.tm
.opcode_modifier
.isstring
)
7055 /* For the string instructions that allow a segment override
7056 on one of their operands, the default segment is ds. */
7059 else if (i
.tm
.opcode_modifier
.shortform
)
7061 /* The register or float register operand is in operand
7063 unsigned int op
= i
.tm
.operand_types
[0].bitfield
.class != Reg
;
7065 /* Register goes in low 3 bits of opcode. */
7066 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
7067 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
7069 if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
7071 /* Warn about some common errors, but press on regardless.
7072 The first case can be generated by gcc (<= 2.8.1). */
7073 if (i
.operands
== 2)
7075 /* Reversed arguments on faddp, fsubp, etc. */
7076 as_warn (_("translating to `%s %s%s,%s%s'"), i
.tm
.name
,
7077 register_prefix
, i
.op
[!intel_syntax
].regs
->reg_name
,
7078 register_prefix
, i
.op
[intel_syntax
].regs
->reg_name
);
7082 /* Extraneous `l' suffix on fp insn. */
7083 as_warn (_("translating to `%s %s%s'"), i
.tm
.name
,
7084 register_prefix
, i
.op
[0].regs
->reg_name
);
7089 if (i
.tm
.base_opcode
== 0x8d /* lea */
7092 as_warn (_("segment override on `%s' is ineffectual"), i
.tm
.name
);
7094 /* If a segment was explicitly specified, and the specified segment
7095 is not the default, use an opcode prefix to select it. If we
7096 never figured out what the default segment is, then default_seg
7097 will be zero at this point, and the specified segment prefix will
7099 if ((i
.seg
[0]) && (i
.seg
[0] != default_seg
))
7101 if (!add_prefix (i
.seg
[0]->seg_prefix
))
7107 static const seg_entry
*
7108 build_modrm_byte (void)
7110 const seg_entry
*default_seg
= 0;
7111 unsigned int source
, dest
;
7114 vex_3_sources
= i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
;
7117 unsigned int nds
, reg_slot
;
7120 dest
= i
.operands
- 1;
7123 /* There are 2 kinds of instructions:
7124 1. 5 operands: 4 register operands or 3 register operands
7125 plus 1 memory operand plus one Imm4 operand, VexXDS, and
7126 VexW0 or VexW1. The destination must be either XMM, YMM or
7128 2. 4 operands: 4 register operands or 3 register operands
7129 plus 1 memory operand, with VexXDS. */
7130 gas_assert ((i
.reg_operands
== 4
7131 || (i
.reg_operands
== 3 && i
.mem_operands
== 1))
7132 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
7133 && i
.tm
.opcode_modifier
.vexw
7134 && i
.tm
.operand_types
[dest
].bitfield
.class == RegSIMD
);
7136 /* If VexW1 is set, the first non-immediate operand is the source and
7137 the second non-immediate one is encoded in the immediate operand. */
7138 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
7140 source
= i
.imm_operands
;
7141 reg_slot
= i
.imm_operands
+ 1;
7145 source
= i
.imm_operands
+ 1;
7146 reg_slot
= i
.imm_operands
;
7149 if (i
.imm_operands
== 0)
7151 /* When there is no immediate operand, generate an 8bit
7152 immediate operand to encode the first operand. */
7153 exp
= &im_expressions
[i
.imm_operands
++];
7154 i
.op
[i
.operands
].imms
= exp
;
7155 i
.types
[i
.operands
] = imm8
;
7158 gas_assert (i
.tm
.operand_types
[reg_slot
].bitfield
.class == RegSIMD
);
7159 exp
->X_op
= O_constant
;
7160 exp
->X_add_number
= register_number (i
.op
[reg_slot
].regs
) << 4;
7161 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
7165 gas_assert (i
.imm_operands
== 1);
7166 gas_assert (fits_in_imm4 (i
.op
[0].imms
->X_add_number
));
7167 gas_assert (!i
.tm
.opcode_modifier
.immext
);
7169 /* Turn on Imm8 again so that output_imm will generate it. */
7170 i
.types
[0].bitfield
.imm8
= 1;
7172 gas_assert (i
.tm
.operand_types
[reg_slot
].bitfield
.class == RegSIMD
);
7173 i
.op
[0].imms
->X_add_number
7174 |= register_number (i
.op
[reg_slot
].regs
) << 4;
7175 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
7178 gas_assert (i
.tm
.operand_types
[nds
].bitfield
.class == RegSIMD
);
7179 i
.vex
.register_specifier
= i
.op
[nds
].regs
;
7184 /* i.reg_operands MUST be the number of real register operands;
7185 implicit registers do not count. If there are 3 register
7186 operands, it must be a instruction with VexNDS. For a
7187 instruction with VexNDD, the destination register is encoded
7188 in VEX prefix. If there are 4 register operands, it must be
7189 a instruction with VEX prefix and 3 sources. */
7190 if (i
.mem_operands
== 0
7191 && ((i
.reg_operands
== 2
7192 && i
.tm
.opcode_modifier
.vexvvvv
<= VEXXDS
)
7193 || (i
.reg_operands
== 3
7194 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
7195 || (i
.reg_operands
== 4 && vex_3_sources
)))
7203 /* When there are 3 operands, one of them may be immediate,
7204 which may be the first or the last operand. Otherwise,
7205 the first operand must be shift count register (cl) or it
7206 is an instruction with VexNDS. */
7207 gas_assert (i
.imm_operands
== 1
7208 || (i
.imm_operands
== 0
7209 && (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
7210 || i
.types
[0].bitfield
.shiftcount
)));
7211 if (operand_type_check (i
.types
[0], imm
)
7212 || i
.types
[0].bitfield
.shiftcount
)
7218 /* When there are 4 operands, the first two must be 8bit
7219 immediate operands. The source operand will be the 3rd
7222 For instructions with VexNDS, if the first operand
7223 an imm8, the source operand is the 2nd one. If the last
7224 operand is imm8, the source operand is the first one. */
7225 gas_assert ((i
.imm_operands
== 2
7226 && i
.types
[0].bitfield
.imm8
7227 && i
.types
[1].bitfield
.imm8
)
7228 || (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
7229 && i
.imm_operands
== 1
7230 && (i
.types
[0].bitfield
.imm8
7231 || i
.types
[i
.operands
- 1].bitfield
.imm8
7233 if (i
.imm_operands
== 2)
7237 if (i
.types
[0].bitfield
.imm8
)
7244 if (is_evex_encoding (&i
.tm
))
7246 /* For EVEX instructions, when there are 5 operands, the
7247 first one must be immediate operand. If the second one
7248 is immediate operand, the source operand is the 3th
7249 one. If the last one is immediate operand, the source
7250 operand is the 2nd one. */
7251 gas_assert (i
.imm_operands
== 2
7252 && i
.tm
.opcode_modifier
.sae
7253 && operand_type_check (i
.types
[0], imm
));
7254 if (operand_type_check (i
.types
[1], imm
))
7256 else if (operand_type_check (i
.types
[4], imm
))
7270 /* RC/SAE operand could be between DEST and SRC. That happens
7271 when one operand is GPR and the other one is XMM/YMM/ZMM
7273 if (i
.rounding
&& i
.rounding
->operand
== (int) dest
)
7276 if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
7278 /* For instructions with VexNDS, the register-only source
7279 operand must be a 32/64bit integer, XMM, YMM, ZMM, or mask
7280 register. It is encoded in VEX prefix. */
7282 i386_operand_type op
;
7285 /* Check register-only source operand when two source
7286 operands are swapped. */
7287 if (!i
.tm
.operand_types
[source
].bitfield
.baseindex
7288 && i
.tm
.operand_types
[dest
].bitfield
.baseindex
)
7296 op
= i
.tm
.operand_types
[vvvv
];
7297 if ((dest
+ 1) >= i
.operands
7298 || ((op
.bitfield
.class != Reg
7299 || (!op
.bitfield
.dword
&& !op
.bitfield
.qword
))
7300 && op
.bitfield
.class != RegSIMD
7301 && !operand_type_equal (&op
, ®mask
)))
7303 i
.vex
.register_specifier
= i
.op
[vvvv
].regs
;
7309 /* One of the register operands will be encoded in the i.rm.reg
7310 field, the other in the combined i.rm.mode and i.rm.regmem
7311 fields. If no form of this instruction supports a memory
7312 destination operand, then we assume the source operand may
7313 sometimes be a memory operand and so we need to store the
7314 destination in the i.rm.reg field. */
7315 if (!i
.tm
.opcode_modifier
.regmem
7316 && operand_type_check (i
.tm
.operand_types
[dest
], anymem
) == 0)
7318 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
7319 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
7320 if (i
.op
[dest
].regs
->reg_type
.bitfield
.class == RegMMX
7321 || i
.op
[source
].regs
->reg_type
.bitfield
.class == RegMMX
)
7322 i
.has_regmmx
= TRUE
;
7323 else if (i
.op
[dest
].regs
->reg_type
.bitfield
.class == RegSIMD
7324 || i
.op
[source
].regs
->reg_type
.bitfield
.class == RegSIMD
)
7326 if (i
.types
[dest
].bitfield
.zmmword
7327 || i
.types
[source
].bitfield
.zmmword
)
7328 i
.has_regzmm
= TRUE
;
7329 else if (i
.types
[dest
].bitfield
.ymmword
7330 || i
.types
[source
].bitfield
.ymmword
)
7331 i
.has_regymm
= TRUE
;
7333 i
.has_regxmm
= TRUE
;
7335 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
7337 if ((i
.op
[dest
].regs
->reg_flags
& RegVRex
) != 0)
7339 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
7341 if ((i
.op
[source
].regs
->reg_flags
& RegVRex
) != 0)
7346 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
7347 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
7348 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
7350 if ((i
.op
[dest
].regs
->reg_flags
& RegVRex
) != 0)
7352 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
7354 if ((i
.op
[source
].regs
->reg_flags
& RegVRex
) != 0)
7357 if (flag_code
!= CODE_64BIT
&& (i
.rex
& REX_R
))
7359 if (i
.types
[!i
.tm
.opcode_modifier
.regmem
].bitfield
.class != RegCR
)
7362 add_prefix (LOCK_PREFIX_OPCODE
);
7366 { /* If it's not 2 reg operands... */
7371 unsigned int fake_zero_displacement
= 0;
7374 for (op
= 0; op
< i
.operands
; op
++)
7375 if (i
.flags
[op
] & Operand_Mem
)
7377 gas_assert (op
< i
.operands
);
7379 if (i
.tm
.opcode_modifier
.vecsib
)
7381 if (i
.index_reg
->reg_num
== RegIZ
)
7384 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
7387 i
.sib
.base
= NO_BASE_REGISTER
;
7388 i
.sib
.scale
= i
.log2_scale_factor
;
7389 i
.types
[op
].bitfield
.disp8
= 0;
7390 i
.types
[op
].bitfield
.disp16
= 0;
7391 i
.types
[op
].bitfield
.disp64
= 0;
7392 if (flag_code
!= CODE_64BIT
|| i
.prefix
[ADDR_PREFIX
])
7394 /* Must be 32 bit */
7395 i
.types
[op
].bitfield
.disp32
= 1;
7396 i
.types
[op
].bitfield
.disp32s
= 0;
7400 i
.types
[op
].bitfield
.disp32
= 0;
7401 i
.types
[op
].bitfield
.disp32s
= 1;
7404 i
.sib
.index
= i
.index_reg
->reg_num
;
7405 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
7407 if ((i
.index_reg
->reg_flags
& RegVRex
) != 0)
7413 if (i
.base_reg
== 0)
7416 if (!i
.disp_operands
)
7417 fake_zero_displacement
= 1;
7418 if (i
.index_reg
== 0)
7420 i386_operand_type newdisp
;
7422 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
7423 /* Operand is just <disp> */
7424 if (flag_code
== CODE_64BIT
)
7426 /* 64bit mode overwrites the 32bit absolute
7427 addressing by RIP relative addressing and
7428 absolute addressing is encoded by one of the
7429 redundant SIB forms. */
7430 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
7431 i
.sib
.base
= NO_BASE_REGISTER
;
7432 i
.sib
.index
= NO_INDEX_REGISTER
;
7433 newdisp
= (!i
.prefix
[ADDR_PREFIX
] ? disp32s
: disp32
);
7435 else if ((flag_code
== CODE_16BIT
)
7436 ^ (i
.prefix
[ADDR_PREFIX
] != 0))
7438 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
7443 i
.rm
.regmem
= NO_BASE_REGISTER
;
7446 i
.types
[op
] = operand_type_and_not (i
.types
[op
], anydisp
);
7447 i
.types
[op
] = operand_type_or (i
.types
[op
], newdisp
);
7449 else if (!i
.tm
.opcode_modifier
.vecsib
)
7451 /* !i.base_reg && i.index_reg */
7452 if (i
.index_reg
->reg_num
== RegIZ
)
7453 i
.sib
.index
= NO_INDEX_REGISTER
;
7455 i
.sib
.index
= i
.index_reg
->reg_num
;
7456 i
.sib
.base
= NO_BASE_REGISTER
;
7457 i
.sib
.scale
= i
.log2_scale_factor
;
7458 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
7459 i
.types
[op
].bitfield
.disp8
= 0;
7460 i
.types
[op
].bitfield
.disp16
= 0;
7461 i
.types
[op
].bitfield
.disp64
= 0;
7462 if (flag_code
!= CODE_64BIT
|| i
.prefix
[ADDR_PREFIX
])
7464 /* Must be 32 bit */
7465 i
.types
[op
].bitfield
.disp32
= 1;
7466 i
.types
[op
].bitfield
.disp32s
= 0;
7470 i
.types
[op
].bitfield
.disp32
= 0;
7471 i
.types
[op
].bitfield
.disp32s
= 1;
7473 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
7477 /* RIP addressing for 64bit mode. */
7478 else if (i
.base_reg
->reg_num
== RegIP
)
7480 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
7481 i
.rm
.regmem
= NO_BASE_REGISTER
;
7482 i
.types
[op
].bitfield
.disp8
= 0;
7483 i
.types
[op
].bitfield
.disp16
= 0;
7484 i
.types
[op
].bitfield
.disp32
= 0;
7485 i
.types
[op
].bitfield
.disp32s
= 1;
7486 i
.types
[op
].bitfield
.disp64
= 0;
7487 i
.flags
[op
] |= Operand_PCrel
;
7488 if (! i
.disp_operands
)
7489 fake_zero_displacement
= 1;
7491 else if (i
.base_reg
->reg_type
.bitfield
.word
)
7493 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
7494 switch (i
.base_reg
->reg_num
)
7497 if (i
.index_reg
== 0)
7499 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
7500 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
7504 if (i
.index_reg
== 0)
7507 if (operand_type_check (i
.types
[op
], disp
) == 0)
7509 /* fake (%bp) into 0(%bp) */
7510 i
.types
[op
].bitfield
.disp8
= 1;
7511 fake_zero_displacement
= 1;
7514 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
7515 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
7517 default: /* (%si) -> 4 or (%di) -> 5 */
7518 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
7520 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
7522 else /* i.base_reg and 32/64 bit mode */
7524 if (flag_code
== CODE_64BIT
7525 && operand_type_check (i
.types
[op
], disp
))
7527 i
.types
[op
].bitfield
.disp16
= 0;
7528 i
.types
[op
].bitfield
.disp64
= 0;
7529 if (i
.prefix
[ADDR_PREFIX
] == 0)
7531 i
.types
[op
].bitfield
.disp32
= 0;
7532 i
.types
[op
].bitfield
.disp32s
= 1;
7536 i
.types
[op
].bitfield
.disp32
= 1;
7537 i
.types
[op
].bitfield
.disp32s
= 0;
7541 if (!i
.tm
.opcode_modifier
.vecsib
)
7542 i
.rm
.regmem
= i
.base_reg
->reg_num
;
7543 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
7545 i
.sib
.base
= i
.base_reg
->reg_num
;
7546 /* x86-64 ignores REX prefix bit here to avoid decoder
7548 if (!(i
.base_reg
->reg_flags
& RegRex
)
7549 && (i
.base_reg
->reg_num
== EBP_REG_NUM
7550 || i
.base_reg
->reg_num
== ESP_REG_NUM
))
7552 if (i
.base_reg
->reg_num
== 5 && i
.disp_operands
== 0)
7554 fake_zero_displacement
= 1;
7555 i
.types
[op
].bitfield
.disp8
= 1;
7557 i
.sib
.scale
= i
.log2_scale_factor
;
7558 if (i
.index_reg
== 0)
7560 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
7561 /* <disp>(%esp) becomes two byte modrm with no index
7562 register. We've already stored the code for esp
7563 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
7564 Any base register besides %esp will not use the
7565 extra modrm byte. */
7566 i
.sib
.index
= NO_INDEX_REGISTER
;
7568 else if (!i
.tm
.opcode_modifier
.vecsib
)
7570 if (i
.index_reg
->reg_num
== RegIZ
)
7571 i
.sib
.index
= NO_INDEX_REGISTER
;
7573 i
.sib
.index
= i
.index_reg
->reg_num
;
7574 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
7575 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
7580 && (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
7581 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
))
7585 if (!fake_zero_displacement
7589 fake_zero_displacement
= 1;
7590 if (i
.disp_encoding
== disp_encoding_8bit
)
7591 i
.types
[op
].bitfield
.disp8
= 1;
7593 i
.types
[op
].bitfield
.disp32
= 1;
7595 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
7599 if (fake_zero_displacement
)
7601 /* Fakes a zero displacement assuming that i.types[op]
7602 holds the correct displacement size. */
7605 gas_assert (i
.op
[op
].disps
== 0);
7606 exp
= &disp_expressions
[i
.disp_operands
++];
7607 i
.op
[op
].disps
= exp
;
7608 exp
->X_op
= O_constant
;
7609 exp
->X_add_number
= 0;
7610 exp
->X_add_symbol
= (symbolS
*) 0;
7611 exp
->X_op_symbol
= (symbolS
*) 0;
7619 if (i
.tm
.opcode_modifier
.vexsources
== XOP2SOURCES
)
7621 if (operand_type_check (i
.types
[0], imm
))
7622 i
.vex
.register_specifier
= NULL
;
7625 /* VEX.vvvv encodes one of the sources when the first
7626 operand is not an immediate. */
7627 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
7628 i
.vex
.register_specifier
= i
.op
[0].regs
;
7630 i
.vex
.register_specifier
= i
.op
[1].regs
;
7633 /* Destination is a XMM register encoded in the ModRM.reg
7635 i
.rm
.reg
= i
.op
[2].regs
->reg_num
;
7636 if ((i
.op
[2].regs
->reg_flags
& RegRex
) != 0)
7639 /* ModRM.rm and VEX.B encodes the other source. */
7640 if (!i
.mem_operands
)
7644 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
7645 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
7647 i
.rm
.regmem
= i
.op
[0].regs
->reg_num
;
7649 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
7653 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXLWP
)
7655 i
.vex
.register_specifier
= i
.op
[2].regs
;
7656 if (!i
.mem_operands
)
7659 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
7660 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
7664 /* Fill in i.rm.reg or i.rm.regmem field with register operand
7665 (if any) based on i.tm.extension_opcode. Again, we must be
7666 careful to make sure that segment/control/debug/test/MMX
7667 registers are coded into the i.rm.reg field. */
7668 else if (i
.reg_operands
)
7671 unsigned int vex_reg
= ~0;
7673 for (op
= 0; op
< i
.operands
; op
++)
7675 if (i
.types
[op
].bitfield
.class == Reg
7676 || i
.types
[op
].bitfield
.class == RegBND
7677 || i
.types
[op
].bitfield
.class == RegMask
7678 || i
.types
[op
].bitfield
.class == SReg
7679 || i
.types
[op
].bitfield
.class == RegCR
7680 || i
.types
[op
].bitfield
.class == RegDR
7681 || i
.types
[op
].bitfield
.class == RegTR
)
7683 if (i
.types
[op
].bitfield
.class == RegSIMD
)
7685 if (i
.types
[op
].bitfield
.zmmword
)
7686 i
.has_regzmm
= TRUE
;
7687 else if (i
.types
[op
].bitfield
.ymmword
)
7688 i
.has_regymm
= TRUE
;
7690 i
.has_regxmm
= TRUE
;
7693 if (i
.types
[op
].bitfield
.class == RegMMX
)
7695 i
.has_regmmx
= TRUE
;
7702 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
7704 /* For instructions with VexNDS, the register-only
7705 source operand is encoded in VEX prefix. */
7706 gas_assert (mem
!= (unsigned int) ~0);
7711 gas_assert (op
< i
.operands
);
7715 /* Check register-only source operand when two source
7716 operands are swapped. */
7717 if (!i
.tm
.operand_types
[op
].bitfield
.baseindex
7718 && i
.tm
.operand_types
[op
+ 1].bitfield
.baseindex
)
7722 gas_assert (mem
== (vex_reg
+ 1)
7723 && op
< i
.operands
);
7728 gas_assert (vex_reg
< i
.operands
);
7732 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXNDD
)
7734 /* For instructions with VexNDD, the register destination
7735 is encoded in VEX prefix. */
7736 if (i
.mem_operands
== 0)
7738 /* There is no memory operand. */
7739 gas_assert ((op
+ 2) == i
.operands
);
7744 /* There are only 2 non-immediate operands. */
7745 gas_assert (op
< i
.imm_operands
+ 2
7746 && i
.operands
== i
.imm_operands
+ 2);
7747 vex_reg
= i
.imm_operands
+ 1;
7751 gas_assert (op
< i
.operands
);
7753 if (vex_reg
!= (unsigned int) ~0)
7755 i386_operand_type
*type
= &i
.tm
.operand_types
[vex_reg
];
7757 if ((type
->bitfield
.class != Reg
7758 || (!type
->bitfield
.dword
&& !type
->bitfield
.qword
))
7759 && type
->bitfield
.class != RegSIMD
7760 && !operand_type_equal (type
, ®mask
))
7763 i
.vex
.register_specifier
= i
.op
[vex_reg
].regs
;
7766 /* Don't set OP operand twice. */
7769 /* If there is an extension opcode to put here, the
7770 register number must be put into the regmem field. */
7771 if (i
.tm
.extension_opcode
!= None
)
7773 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
7774 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
7776 if ((i
.op
[op
].regs
->reg_flags
& RegVRex
) != 0)
7781 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
7782 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
7784 if ((i
.op
[op
].regs
->reg_flags
& RegVRex
) != 0)
7789 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
7790 must set it to 3 to indicate this is a register operand
7791 in the regmem field. */
7792 if (!i
.mem_operands
)
7796 /* Fill in i.rm.reg field with extension opcode (if any). */
7797 if (i
.tm
.extension_opcode
!= None
)
7798 i
.rm
.reg
= i
.tm
.extension_opcode
;
7804 output_branch (void)
7810 relax_substateT subtype
;
7814 code16
= flag_code
== CODE_16BIT
? CODE16
: 0;
7815 size
= i
.disp_encoding
== disp_encoding_32bit
? BIG
: SMALL
;
7818 if (i
.prefix
[DATA_PREFIX
] != 0)
7824 /* Pentium4 branch hints. */
7825 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
7826 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
7831 if (i
.prefix
[REX_PREFIX
] != 0)
7837 /* BND prefixed jump. */
7838 if (i
.prefix
[BND_PREFIX
] != 0)
7840 FRAG_APPEND_1_CHAR (i
.prefix
[BND_PREFIX
]);
7844 if (i
.prefixes
!= 0 && !intel_syntax
)
7845 as_warn (_("skipping prefixes on this instruction"));
7847 /* It's always a symbol; End frag & setup for relax.
7848 Make sure there is enough room in this frag for the largest
7849 instruction we may generate in md_convert_frag. This is 2
7850 bytes for the opcode and room for the prefix and largest
7852 frag_grow (prefix
+ 2 + 4);
7853 /* Prefix and 1 opcode byte go in fr_fix. */
7854 p
= frag_more (prefix
+ 1);
7855 if (i
.prefix
[DATA_PREFIX
] != 0)
7856 *p
++ = DATA_PREFIX_OPCODE
;
7857 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
7858 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
7859 *p
++ = i
.prefix
[SEG_PREFIX
];
7860 if (i
.prefix
[REX_PREFIX
] != 0)
7861 *p
++ = i
.prefix
[REX_PREFIX
];
7862 *p
= i
.tm
.base_opcode
;
7864 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
7865 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, size
);
7866 else if (cpu_arch_flags
.bitfield
.cpui386
)
7867 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, size
);
7869 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, size
);
7872 sym
= i
.op
[0].disps
->X_add_symbol
;
7873 off
= i
.op
[0].disps
->X_add_number
;
7875 if (i
.op
[0].disps
->X_op
!= O_constant
7876 && i
.op
[0].disps
->X_op
!= O_symbol
)
7878 /* Handle complex expressions. */
7879 sym
= make_expr_symbol (i
.op
[0].disps
);
7883 /* 1 possible extra opcode + 4 byte displacement go in var part.
7884 Pass reloc in fr_var. */
7885 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
7888 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7889 /* Return TRUE iff PLT32 relocation should be used for branching to
7893 need_plt32_p (symbolS
*s
)
7895 /* PLT32 relocation is ELF only. */
7900 /* Don't emit PLT32 relocation on Solaris: neither native linker nor
7901 krtld support it. */
7905 /* Since there is no need to prepare for PLT branch on x86-64, we
7906 can generate R_X86_64_PLT32, instead of R_X86_64_PC32, which can
7907 be used as a marker for 32-bit PC-relative branches. */
7911 /* Weak or undefined symbol need PLT32 relocation. */
7912 if (S_IS_WEAK (s
) || !S_IS_DEFINED (s
))
7915 /* Non-global symbol doesn't need PLT32 relocation. */
7916 if (! S_IS_EXTERNAL (s
))
7919 /* Other global symbols need PLT32 relocation. NB: Symbol with
7920 non-default visibilities are treated as normal global symbol
7921 so that PLT32 relocation can be used as a marker for 32-bit
7922 PC-relative branches. It is useful for linker relaxation. */
7933 bfd_reloc_code_real_type jump_reloc
= i
.reloc
[0];
7935 if (i
.tm
.opcode_modifier
.jumpbyte
)
7937 /* This is a loop or jecxz type instruction. */
7939 if (i
.prefix
[ADDR_PREFIX
] != 0)
7941 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
7944 /* Pentium4 branch hints. */
7945 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
7946 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
7948 FRAG_APPEND_1_CHAR (i
.prefix
[SEG_PREFIX
]);
7957 if (flag_code
== CODE_16BIT
)
7960 if (i
.prefix
[DATA_PREFIX
] != 0)
7962 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
7972 if (i
.prefix
[REX_PREFIX
] != 0)
7974 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
7978 /* BND prefixed jump. */
7979 if (i
.prefix
[BND_PREFIX
] != 0)
7981 FRAG_APPEND_1_CHAR (i
.prefix
[BND_PREFIX
]);
7985 if (i
.prefixes
!= 0 && !intel_syntax
)
7986 as_warn (_("skipping prefixes on this instruction"));
7988 p
= frag_more (i
.tm
.opcode_length
+ size
);
7989 switch (i
.tm
.opcode_length
)
7992 *p
++ = i
.tm
.base_opcode
>> 8;
7995 *p
++ = i
.tm
.base_opcode
;
8001 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8003 && jump_reloc
== NO_RELOC
8004 && need_plt32_p (i
.op
[0].disps
->X_add_symbol
))
8005 jump_reloc
= BFD_RELOC_X86_64_PLT32
;
8008 jump_reloc
= reloc (size
, 1, 1, jump_reloc
);
8010 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
8011 i
.op
[0].disps
, 1, jump_reloc
);
8013 /* All jumps handled here are signed, but don't use a signed limit
8014 check for 32 and 16 bit jumps as we want to allow wrap around at
8015 4G and 64k respectively. */
8017 fixP
->fx_signed
= 1;
8021 output_interseg_jump (void)
8029 if (flag_code
== CODE_16BIT
)
8033 if (i
.prefix
[DATA_PREFIX
] != 0)
8039 if (i
.prefix
[REX_PREFIX
] != 0)
8049 if (i
.prefixes
!= 0 && !intel_syntax
)
8050 as_warn (_("skipping prefixes on this instruction"));
8052 /* 1 opcode; 2 segment; offset */
8053 p
= frag_more (prefix
+ 1 + 2 + size
);
8055 if (i
.prefix
[DATA_PREFIX
] != 0)
8056 *p
++ = DATA_PREFIX_OPCODE
;
8058 if (i
.prefix
[REX_PREFIX
] != 0)
8059 *p
++ = i
.prefix
[REX_PREFIX
];
8061 *p
++ = i
.tm
.base_opcode
;
8062 if (i
.op
[1].imms
->X_op
== O_constant
)
8064 offsetT n
= i
.op
[1].imms
->X_add_number
;
8067 && !fits_in_unsigned_word (n
)
8068 && !fits_in_signed_word (n
))
8070 as_bad (_("16-bit jump out of range"));
8073 md_number_to_chars (p
, n
, size
);
8076 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
8077 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
8078 if (i
.op
[0].imms
->X_op
!= O_constant
)
8079 as_bad (_("can't handle non absolute segment in `%s'"),
8081 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
8084 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8089 asection
*seg
= now_seg
;
8090 subsegT subseg
= now_subseg
;
8092 unsigned int alignment
, align_size_1
;
8093 unsigned int isa_1_descsz
, feature_2_descsz
, descsz
;
8094 unsigned int isa_1_descsz_raw
, feature_2_descsz_raw
;
8095 unsigned int padding
;
8097 if (!IS_ELF
|| !x86_used_note
)
8100 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_X86
;
8102 /* The .note.gnu.property section layout:
8104 Field Length Contents
8107 n_descsz 4 The note descriptor size
8108 n_type 4 NT_GNU_PROPERTY_TYPE_0
8110 n_desc n_descsz The program property array
8114 /* Create the .note.gnu.property section. */
8115 sec
= subseg_new (NOTE_GNU_PROPERTY_SECTION_NAME
, 0);
8116 bfd_set_section_flags (sec
,
8123 if (get_elf_backend_data (stdoutput
)->s
->elfclass
== ELFCLASS64
)
8134 bfd_set_section_alignment (sec
, alignment
);
8135 elf_section_type (sec
) = SHT_NOTE
;
8137 /* GNU_PROPERTY_X86_ISA_1_USED: 4-byte type + 4-byte data size
8139 isa_1_descsz_raw
= 4 + 4 + 4;
8140 /* Align GNU_PROPERTY_X86_ISA_1_USED. */
8141 isa_1_descsz
= (isa_1_descsz_raw
+ align_size_1
) & ~align_size_1
;
8143 feature_2_descsz_raw
= isa_1_descsz
;
8144 /* GNU_PROPERTY_X86_FEATURE_2_USED: 4-byte type + 4-byte data size
8146 feature_2_descsz_raw
+= 4 + 4 + 4;
8147 /* Align GNU_PROPERTY_X86_FEATURE_2_USED. */
8148 feature_2_descsz
= ((feature_2_descsz_raw
+ align_size_1
)
8151 descsz
= feature_2_descsz
;
8152 /* Section size: n_namsz + n_descsz + n_type + n_name + n_descsz. */
8153 p
= frag_more (4 + 4 + 4 + 4 + descsz
);
8155 /* Write n_namsz. */
8156 md_number_to_chars (p
, (valueT
) 4, 4);
8158 /* Write n_descsz. */
8159 md_number_to_chars (p
+ 4, (valueT
) descsz
, 4);
8162 md_number_to_chars (p
+ 4 * 2, (valueT
) NT_GNU_PROPERTY_TYPE_0
, 4);
8165 memcpy (p
+ 4 * 3, "GNU", 4);
8167 /* Write 4-byte type. */
8168 md_number_to_chars (p
+ 4 * 4,
8169 (valueT
) GNU_PROPERTY_X86_ISA_1_USED
, 4);
8171 /* Write 4-byte data size. */
8172 md_number_to_chars (p
+ 4 * 5, (valueT
) 4, 4);
8174 /* Write 4-byte data. */
8175 md_number_to_chars (p
+ 4 * 6, (valueT
) x86_isa_1_used
, 4);
8177 /* Zero out paddings. */
8178 padding
= isa_1_descsz
- isa_1_descsz_raw
;
8180 memset (p
+ 4 * 7, 0, padding
);
8182 /* Write 4-byte type. */
8183 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 4,
8184 (valueT
) GNU_PROPERTY_X86_FEATURE_2_USED
, 4);
8186 /* Write 4-byte data size. */
8187 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 5, (valueT
) 4, 4);
8189 /* Write 4-byte data. */
8190 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 6,
8191 (valueT
) x86_feature_2_used
, 4);
8193 /* Zero out paddings. */
8194 padding
= feature_2_descsz
- feature_2_descsz_raw
;
8196 memset (p
+ isa_1_descsz
+ 4 * 7, 0, padding
);
8198 /* We probably can't restore the current segment, for there likely
8201 subseg_set (seg
, subseg
);
8206 encoding_length (const fragS
*start_frag
, offsetT start_off
,
8207 const char *frag_now_ptr
)
8209 unsigned int len
= 0;
8211 if (start_frag
!= frag_now
)
8213 const fragS
*fr
= start_frag
;
8218 } while (fr
&& fr
!= frag_now
);
8221 return len
- start_off
+ (frag_now_ptr
- frag_now
->fr_literal
);
8227 fragS
*insn_start_frag
;
8228 offsetT insn_start_off
;
8230 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8231 if (IS_ELF
&& x86_used_note
)
8233 if (i
.tm
.cpu_flags
.bitfield
.cpucmov
)
8234 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_CMOV
;
8235 if (i
.tm
.cpu_flags
.bitfield
.cpusse
)
8236 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE
;
8237 if (i
.tm
.cpu_flags
.bitfield
.cpusse2
)
8238 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE2
;
8239 if (i
.tm
.cpu_flags
.bitfield
.cpusse3
)
8240 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE3
;
8241 if (i
.tm
.cpu_flags
.bitfield
.cpussse3
)
8242 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSSE3
;
8243 if (i
.tm
.cpu_flags
.bitfield
.cpusse4_1
)
8244 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE4_1
;
8245 if (i
.tm
.cpu_flags
.bitfield
.cpusse4_2
)
8246 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE4_2
;
8247 if (i
.tm
.cpu_flags
.bitfield
.cpuavx
)
8248 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX
;
8249 if (i
.tm
.cpu_flags
.bitfield
.cpuavx2
)
8250 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX2
;
8251 if (i
.tm
.cpu_flags
.bitfield
.cpufma
)
8252 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_FMA
;
8253 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512f
)
8254 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512F
;
8255 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512cd
)
8256 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512CD
;
8257 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512er
)
8258 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512ER
;
8259 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512pf
)
8260 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512PF
;
8261 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512vl
)
8262 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512VL
;
8263 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512dq
)
8264 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512DQ
;
8265 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512bw
)
8266 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512BW
;
8267 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_4fmaps
)
8268 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_4FMAPS
;
8269 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_4vnniw
)
8270 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_4VNNIW
;
8271 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_bitalg
)
8272 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_BITALG
;
8273 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512ifma
)
8274 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_IFMA
;
8275 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512vbmi
)
8276 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_VBMI
;
8277 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_vbmi2
)
8278 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_VBMI2
;
8279 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_vnni
)
8280 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_VNNI
;
8281 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_bf16
)
8282 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_BF16
;
8284 if (i
.tm
.cpu_flags
.bitfield
.cpu8087
8285 || i
.tm
.cpu_flags
.bitfield
.cpu287
8286 || i
.tm
.cpu_flags
.bitfield
.cpu387
8287 || i
.tm
.cpu_flags
.bitfield
.cpu687
8288 || i
.tm
.cpu_flags
.bitfield
.cpufisttp
)
8289 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_X87
;
8290 /* Don't set GNU_PROPERTY_X86_FEATURE_2_MMX for prefetchtXXX nor
8291 Xfence instructions. */
8292 if (i
.tm
.base_opcode
!= 0xf18
8293 && i
.tm
.base_opcode
!= 0xf0d
8294 && i
.tm
.base_opcode
!= 0xfaef8
8296 || i
.tm
.cpu_flags
.bitfield
.cpummx
8297 || i
.tm
.cpu_flags
.bitfield
.cpua3dnow
8298 || i
.tm
.cpu_flags
.bitfield
.cpua3dnowa
))
8299 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_MMX
;
8301 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XMM
;
8303 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_YMM
;
8305 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_ZMM
;
8306 if (i
.tm
.cpu_flags
.bitfield
.cpufxsr
)
8307 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_FXSR
;
8308 if (i
.tm
.cpu_flags
.bitfield
.cpuxsave
)
8309 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVE
;
8310 if (i
.tm
.cpu_flags
.bitfield
.cpuxsaveopt
)
8311 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVEOPT
;
8312 if (i
.tm
.cpu_flags
.bitfield
.cpuxsavec
)
8313 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVEC
;
8317 /* Tie dwarf2 debug info to the address at the start of the insn.
8318 We can't do this after the insn has been output as the current
8319 frag may have been closed off. eg. by frag_var. */
8320 dwarf2_emit_insn (0);
8322 insn_start_frag
= frag_now
;
8323 insn_start_off
= frag_now_fix ();
8326 if (i
.tm
.opcode_modifier
.jump
)
8328 else if (i
.tm
.opcode_modifier
.jumpbyte
8329 || i
.tm
.opcode_modifier
.jumpdword
)
8331 else if (i
.tm
.opcode_modifier
.jumpintersegment
)
8332 output_interseg_jump ();
8335 /* Output normal instructions here. */
8339 unsigned int prefix
;
8342 && (i
.tm
.base_opcode
== 0xfaee8
8343 || i
.tm
.base_opcode
== 0xfaef0
8344 || i
.tm
.base_opcode
== 0xfaef8))
8346 /* Encode lfence, mfence, and sfence as
8347 f0 83 04 24 00 lock addl $0x0, (%{re}sp). */
8348 offsetT val
= 0x240483f0ULL
;
8350 md_number_to_chars (p
, val
, 5);
8354 /* Some processors fail on LOCK prefix. This options makes
8355 assembler ignore LOCK prefix and serves as a workaround. */
8356 if (omit_lock_prefix
)
8358 if (i
.tm
.base_opcode
== LOCK_PREFIX_OPCODE
)
8360 i
.prefix
[LOCK_PREFIX
] = 0;
8363 /* Since the VEX/EVEX prefix contains the implicit prefix, we
8364 don't need the explicit prefix. */
8365 if (!i
.tm
.opcode_modifier
.vex
&& !i
.tm
.opcode_modifier
.evex
)
8367 switch (i
.tm
.opcode_length
)
8370 if (i
.tm
.base_opcode
& 0xff000000)
8372 prefix
= (i
.tm
.base_opcode
>> 24) & 0xff;
8373 if (!i
.tm
.cpu_flags
.bitfield
.cpupadlock
8374 || prefix
!= REPE_PREFIX_OPCODE
8375 || (i
.prefix
[REP_PREFIX
] != REPE_PREFIX_OPCODE
))
8376 add_prefix (prefix
);
8380 if ((i
.tm
.base_opcode
& 0xff0000) != 0)
8382 prefix
= (i
.tm
.base_opcode
>> 16) & 0xff;
8383 add_prefix (prefix
);
8389 /* Check for pseudo prefixes. */
8390 as_bad_where (insn_start_frag
->fr_file
,
8391 insn_start_frag
->fr_line
,
8392 _("pseudo prefix without instruction"));
8398 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
8399 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
8400 R_X86_64_GOTTPOFF relocation so that linker can safely
8401 perform IE->LE optimization. */
8402 if (x86_elf_abi
== X86_64_X32_ABI
8404 && i
.reloc
[0] == BFD_RELOC_X86_64_GOTTPOFF
8405 && i
.prefix
[REX_PREFIX
] == 0)
8406 add_prefix (REX_OPCODE
);
8409 /* The prefix bytes. */
8410 for (j
= ARRAY_SIZE (i
.prefix
), q
= i
.prefix
; j
> 0; j
--, q
++)
8412 FRAG_APPEND_1_CHAR (*q
);
8416 for (j
= 0, q
= i
.prefix
; j
< ARRAY_SIZE (i
.prefix
); j
++, q
++)
8421 /* REX byte is encoded in VEX prefix. */
8425 FRAG_APPEND_1_CHAR (*q
);
8428 /* There should be no other prefixes for instructions
8433 /* For EVEX instructions i.vrex should become 0 after
8434 build_evex_prefix. For VEX instructions upper 16 registers
8435 aren't available, so VREX should be 0. */
8438 /* Now the VEX prefix. */
8439 p
= frag_more (i
.vex
.length
);
8440 for (j
= 0; j
< i
.vex
.length
; j
++)
8441 p
[j
] = i
.vex
.bytes
[j
];
8444 /* Now the opcode; be careful about word order here! */
8445 if (i
.tm
.opcode_length
== 1)
8447 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
8451 switch (i
.tm
.opcode_length
)
8455 *p
++ = (i
.tm
.base_opcode
>> 24) & 0xff;
8456 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
8460 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
8470 /* Put out high byte first: can't use md_number_to_chars! */
8471 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
8472 *p
= i
.tm
.base_opcode
& 0xff;
8475 /* Now the modrm byte and sib byte (if present). */
8476 if (i
.tm
.opcode_modifier
.modrm
)
8478 FRAG_APPEND_1_CHAR ((i
.rm
.regmem
<< 0
8481 /* If i.rm.regmem == ESP (4)
8482 && i.rm.mode != (Register mode)
8484 ==> need second modrm byte. */
8485 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
8487 && !(i
.base_reg
&& i
.base_reg
->reg_type
.bitfield
.word
))
8488 FRAG_APPEND_1_CHAR ((i
.sib
.base
<< 0
8490 | i
.sib
.scale
<< 6));
8493 if (i
.disp_operands
)
8494 output_disp (insn_start_frag
, insn_start_off
);
8497 output_imm (insn_start_frag
, insn_start_off
);
8500 * frag_now_fix () returning plain abs_section_offset when we're in the
8501 * absolute section, and abs_section_offset not getting updated as data
8502 * gets added to the frag breaks the logic below.
8504 if (now_seg
!= absolute_section
)
8506 j
= encoding_length (insn_start_frag
, insn_start_off
, frag_more (0));
8508 as_warn (_("instruction length of %u bytes exceeds the limit of 15"),
8516 pi ("" /*line*/, &i
);
8518 #endif /* DEBUG386 */
8521 /* Return the size of the displacement operand N. */
8524 disp_size (unsigned int n
)
8528 if (i
.types
[n
].bitfield
.disp64
)
8530 else if (i
.types
[n
].bitfield
.disp8
)
8532 else if (i
.types
[n
].bitfield
.disp16
)
8537 /* Return the size of the immediate operand N. */
8540 imm_size (unsigned int n
)
8543 if (i
.types
[n
].bitfield
.imm64
)
8545 else if (i
.types
[n
].bitfield
.imm8
|| i
.types
[n
].bitfield
.imm8s
)
8547 else if (i
.types
[n
].bitfield
.imm16
)
8553 output_disp (fragS
*insn_start_frag
, offsetT insn_start_off
)
8558 for (n
= 0; n
< i
.operands
; n
++)
8560 if (operand_type_check (i
.types
[n
], disp
))
8562 if (i
.op
[n
].disps
->X_op
== O_constant
)
8564 int size
= disp_size (n
);
8565 offsetT val
= i
.op
[n
].disps
->X_add_number
;
8567 val
= offset_in_range (val
>> (size
== 1 ? i
.memshift
: 0),
8569 p
= frag_more (size
);
8570 md_number_to_chars (p
, val
, size
);
8574 enum bfd_reloc_code_real reloc_type
;
8575 int size
= disp_size (n
);
8576 int sign
= i
.types
[n
].bitfield
.disp32s
;
8577 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
8580 /* We can't have 8 bit displacement here. */
8581 gas_assert (!i
.types
[n
].bitfield
.disp8
);
8583 /* The PC relative address is computed relative
8584 to the instruction boundary, so in case immediate
8585 fields follows, we need to adjust the value. */
8586 if (pcrel
&& i
.imm_operands
)
8591 for (n1
= 0; n1
< i
.operands
; n1
++)
8592 if (operand_type_check (i
.types
[n1
], imm
))
8594 /* Only one immediate is allowed for PC
8595 relative address. */
8596 gas_assert (sz
== 0);
8598 i
.op
[n
].disps
->X_add_number
-= sz
;
8600 /* We should find the immediate. */
8601 gas_assert (sz
!= 0);
8604 p
= frag_more (size
);
8605 reloc_type
= reloc (size
, pcrel
, sign
, i
.reloc
[n
]);
8607 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
8608 && (((reloc_type
== BFD_RELOC_32
8609 || reloc_type
== BFD_RELOC_X86_64_32S
8610 || (reloc_type
== BFD_RELOC_64
8612 && (i
.op
[n
].disps
->X_op
== O_symbol
8613 || (i
.op
[n
].disps
->X_op
== O_add
8614 && ((symbol_get_value_expression
8615 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
8617 || reloc_type
== BFD_RELOC_32_PCREL
))
8621 reloc_type
= BFD_RELOC_386_GOTPC
;
8622 i
.op
[n
].imms
->X_add_number
+=
8623 encoding_length (insn_start_frag
, insn_start_off
, p
);
8625 else if (reloc_type
== BFD_RELOC_64
)
8626 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
8628 /* Don't do the adjustment for x86-64, as there
8629 the pcrel addressing is relative to the _next_
8630 insn, and that is taken care of in other code. */
8631 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
8633 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
8634 size
, i
.op
[n
].disps
, pcrel
,
8636 /* Check for "call/jmp *mem", "mov mem, %reg",
8637 "test %reg, mem" and "binop mem, %reg" where binop
8638 is one of adc, add, and, cmp, or, sbb, sub, xor
8639 instructions without data prefix. Always generate
8640 R_386_GOT32X for "sym*GOT" operand in 32-bit mode. */
8641 if (i
.prefix
[DATA_PREFIX
] == 0
8642 && (generate_relax_relocations
8645 && i
.rm
.regmem
== 5))
8647 || (i
.rm
.mode
== 0 && i
.rm
.regmem
== 5))
8648 && ((i
.operands
== 1
8649 && i
.tm
.base_opcode
== 0xff
8650 && (i
.rm
.reg
== 2 || i
.rm
.reg
== 4))
8652 && (i
.tm
.base_opcode
== 0x8b
8653 || i
.tm
.base_opcode
== 0x85
8654 || (i
.tm
.base_opcode
& 0xc7) == 0x03))))
8658 fixP
->fx_tcbit
= i
.rex
!= 0;
8660 && (i
.base_reg
->reg_num
== RegIP
))
8661 fixP
->fx_tcbit2
= 1;
8664 fixP
->fx_tcbit2
= 1;
8672 output_imm (fragS
*insn_start_frag
, offsetT insn_start_off
)
8677 for (n
= 0; n
< i
.operands
; n
++)
8679 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
8680 if (i
.rounding
&& (int) n
== i
.rounding
->operand
)
8683 if (operand_type_check (i
.types
[n
], imm
))
8685 if (i
.op
[n
].imms
->X_op
== O_constant
)
8687 int size
= imm_size (n
);
8690 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
8692 p
= frag_more (size
);
8693 md_number_to_chars (p
, val
, size
);
8697 /* Not absolute_section.
8698 Need a 32-bit fixup (don't support 8bit
8699 non-absolute imms). Try to support other
8701 enum bfd_reloc_code_real reloc_type
;
8702 int size
= imm_size (n
);
8705 if (i
.types
[n
].bitfield
.imm32s
8706 && (i
.suffix
== QWORD_MNEM_SUFFIX
8707 || (!i
.suffix
&& i
.tm
.opcode_modifier
.no_lsuf
)))
8712 p
= frag_more (size
);
8713 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
8715 /* This is tough to explain. We end up with this one if we
8716 * have operands that look like
8717 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
8718 * obtain the absolute address of the GOT, and it is strongly
8719 * preferable from a performance point of view to avoid using
8720 * a runtime relocation for this. The actual sequence of
8721 * instructions often look something like:
8726 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
8728 * The call and pop essentially return the absolute address
8729 * of the label .L66 and store it in %ebx. The linker itself
8730 * will ultimately change the first operand of the addl so
8731 * that %ebx points to the GOT, but to keep things simple, the
8732 * .o file must have this operand set so that it generates not
8733 * the absolute address of .L66, but the absolute address of
8734 * itself. This allows the linker itself simply treat a GOTPC
8735 * relocation as asking for a pcrel offset to the GOT to be
8736 * added in, and the addend of the relocation is stored in the
8737 * operand field for the instruction itself.
8739 * Our job here is to fix the operand so that it would add
8740 * the correct offset so that %ebx would point to itself. The
8741 * thing that is tricky is that .-.L66 will point to the
8742 * beginning of the instruction, so we need to further modify
8743 * the operand so that it will point to itself. There are
8744 * other cases where you have something like:
8746 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
8748 * and here no correction would be required. Internally in
8749 * the assembler we treat operands of this form as not being
8750 * pcrel since the '.' is explicitly mentioned, and I wonder
8751 * whether it would simplify matters to do it this way. Who
8752 * knows. In earlier versions of the PIC patches, the
8753 * pcrel_adjust field was used to store the correction, but
8754 * since the expression is not pcrel, I felt it would be
8755 * confusing to do it this way. */
8757 if ((reloc_type
== BFD_RELOC_32
8758 || reloc_type
== BFD_RELOC_X86_64_32S
8759 || reloc_type
== BFD_RELOC_64
)
8761 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
8762 && (i
.op
[n
].imms
->X_op
== O_symbol
8763 || (i
.op
[n
].imms
->X_op
== O_add
8764 && ((symbol_get_value_expression
8765 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
8769 reloc_type
= BFD_RELOC_386_GOTPC
;
8771 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
8773 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
8774 i
.op
[n
].imms
->X_add_number
+=
8775 encoding_length (insn_start_frag
, insn_start_off
, p
);
8777 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
8778 i
.op
[n
].imms
, 0, reloc_type
);
8784 /* x86_cons_fix_new is called via the expression parsing code when a
8785 reloc is needed. We use this hook to get the correct .got reloc. */
8786 static int cons_sign
= -1;
8789 x86_cons_fix_new (fragS
*frag
, unsigned int off
, unsigned int len
,
8790 expressionS
*exp
, bfd_reloc_code_real_type r
)
8792 r
= reloc (len
, 0, cons_sign
, r
);
8795 if (exp
->X_op
== O_secrel
)
8797 exp
->X_op
= O_symbol
;
8798 r
= BFD_RELOC_32_SECREL
;
8802 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
8805 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
8806 purpose of the `.dc.a' internal pseudo-op. */
8809 x86_address_bytes (void)
8811 if ((stdoutput
->arch_info
->mach
& bfd_mach_x64_32
))
8813 return stdoutput
->arch_info
->bits_per_address
/ 8;
8816 #if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
8818 # define lex_got(reloc, adjust, types) NULL
8820 /* Parse operands of the form
8821 <symbol>@GOTOFF+<nnn>
8822 and similar .plt or .got references.
8824 If we find one, set up the correct relocation in RELOC and copy the
8825 input string, minus the `@GOTOFF' into a malloc'd buffer for
8826 parsing by the calling routine. Return this buffer, and if ADJUST
8827 is non-null set it to the length of the string we removed from the
8828 input line. Otherwise return NULL. */
8830 lex_got (enum bfd_reloc_code_real
*rel
,
8832 i386_operand_type
*types
)
8834 /* Some of the relocations depend on the size of what field is to
8835 be relocated. But in our callers i386_immediate and i386_displacement
8836 we don't yet know the operand size (this will be set by insn
8837 matching). Hence we record the word32 relocation here,
8838 and adjust the reloc according to the real size in reloc(). */
8839 static const struct {
8842 const enum bfd_reloc_code_real rel
[2];
8843 const i386_operand_type types64
;
8845 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8846 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32
,
8848 OPERAND_TYPE_IMM32_64
},
8850 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real
,
8851 BFD_RELOC_X86_64_PLTOFF64
},
8852 OPERAND_TYPE_IMM64
},
8853 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32
,
8854 BFD_RELOC_X86_64_PLT32
},
8855 OPERAND_TYPE_IMM32_32S_DISP32
},
8856 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real
,
8857 BFD_RELOC_X86_64_GOTPLT64
},
8858 OPERAND_TYPE_IMM64_DISP64
},
8859 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF
,
8860 BFD_RELOC_X86_64_GOTOFF64
},
8861 OPERAND_TYPE_IMM64_DISP64
},
8862 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real
,
8863 BFD_RELOC_X86_64_GOTPCREL
},
8864 OPERAND_TYPE_IMM32_32S_DISP32
},
8865 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD
,
8866 BFD_RELOC_X86_64_TLSGD
},
8867 OPERAND_TYPE_IMM32_32S_DISP32
},
8868 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM
,
8869 _dummy_first_bfd_reloc_code_real
},
8870 OPERAND_TYPE_NONE
},
8871 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real
,
8872 BFD_RELOC_X86_64_TLSLD
},
8873 OPERAND_TYPE_IMM32_32S_DISP32
},
8874 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32
,
8875 BFD_RELOC_X86_64_GOTTPOFF
},
8876 OPERAND_TYPE_IMM32_32S_DISP32
},
8877 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32
,
8878 BFD_RELOC_X86_64_TPOFF32
},
8879 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
8880 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE
,
8881 _dummy_first_bfd_reloc_code_real
},
8882 OPERAND_TYPE_NONE
},
8883 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32
,
8884 BFD_RELOC_X86_64_DTPOFF32
},
8885 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
8886 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE
,
8887 _dummy_first_bfd_reloc_code_real
},
8888 OPERAND_TYPE_NONE
},
8889 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE
,
8890 _dummy_first_bfd_reloc_code_real
},
8891 OPERAND_TYPE_NONE
},
8892 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32
,
8893 BFD_RELOC_X86_64_GOT32
},
8894 OPERAND_TYPE_IMM32_32S_64_DISP32
},
8895 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC
,
8896 BFD_RELOC_X86_64_GOTPC32_TLSDESC
},
8897 OPERAND_TYPE_IMM32_32S_DISP32
},
8898 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL
,
8899 BFD_RELOC_X86_64_TLSDESC_CALL
},
8900 OPERAND_TYPE_IMM32_32S_DISP32
},
8905 #if defined (OBJ_MAYBE_ELF)
8910 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
8911 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
8914 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
8916 int len
= gotrel
[j
].len
;
8917 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
8919 if (gotrel
[j
].rel
[object_64bit
] != 0)
8922 char *tmpbuf
, *past_reloc
;
8924 *rel
= gotrel
[j
].rel
[object_64bit
];
8928 if (flag_code
!= CODE_64BIT
)
8930 types
->bitfield
.imm32
= 1;
8931 types
->bitfield
.disp32
= 1;
8934 *types
= gotrel
[j
].types64
;
8937 if (j
!= 0 && GOT_symbol
== NULL
)
8938 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
8940 /* The length of the first part of our input line. */
8941 first
= cp
- input_line_pointer
;
8943 /* The second part goes from after the reloc token until
8944 (and including) an end_of_line char or comma. */
8945 past_reloc
= cp
+ 1 + len
;
8947 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
8949 second
= cp
+ 1 - past_reloc
;
8951 /* Allocate and copy string. The trailing NUL shouldn't
8952 be necessary, but be safe. */
8953 tmpbuf
= XNEWVEC (char, first
+ second
+ 2);
8954 memcpy (tmpbuf
, input_line_pointer
, first
);
8955 if (second
!= 0 && *past_reloc
!= ' ')
8956 /* Replace the relocation token with ' ', so that
8957 errors like foo@GOTOFF1 will be detected. */
8958 tmpbuf
[first
++] = ' ';
8960 /* Increment length by 1 if the relocation token is
8965 memcpy (tmpbuf
+ first
, past_reloc
, second
);
8966 tmpbuf
[first
+ second
] = '\0';
8970 as_bad (_("@%s reloc is not supported with %d-bit output format"),
8971 gotrel
[j
].str
, 1 << (5 + object_64bit
));
8976 /* Might be a symbol version string. Don't as_bad here. */
8985 /* Parse operands of the form
8986 <symbol>@SECREL32+<nnn>
8988 If we find one, set up the correct relocation in RELOC and copy the
8989 input string, minus the `@SECREL32' into a malloc'd buffer for
8990 parsing by the calling routine. Return this buffer, and if ADJUST
8991 is non-null set it to the length of the string we removed from the
8992 input line. Otherwise return NULL.
8994 This function is copied from the ELF version above adjusted for PE targets. */
8997 lex_got (enum bfd_reloc_code_real
*rel ATTRIBUTE_UNUSED
,
8998 int *adjust ATTRIBUTE_UNUSED
,
8999 i386_operand_type
*types
)
9005 const enum bfd_reloc_code_real rel
[2];
9006 const i386_operand_type types64
;
9010 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL
,
9011 BFD_RELOC_32_SECREL
},
9012 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
9018 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
9019 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
9022 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
9024 int len
= gotrel
[j
].len
;
9026 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
9028 if (gotrel
[j
].rel
[object_64bit
] != 0)
9031 char *tmpbuf
, *past_reloc
;
9033 *rel
= gotrel
[j
].rel
[object_64bit
];
9039 if (flag_code
!= CODE_64BIT
)
9041 types
->bitfield
.imm32
= 1;
9042 types
->bitfield
.disp32
= 1;
9045 *types
= gotrel
[j
].types64
;
9048 /* The length of the first part of our input line. */
9049 first
= cp
- input_line_pointer
;
9051 /* The second part goes from after the reloc token until
9052 (and including) an end_of_line char or comma. */
9053 past_reloc
= cp
+ 1 + len
;
9055 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
9057 second
= cp
+ 1 - past_reloc
;
9059 /* Allocate and copy string. The trailing NUL shouldn't
9060 be necessary, but be safe. */
9061 tmpbuf
= XNEWVEC (char, first
+ second
+ 2);
9062 memcpy (tmpbuf
, input_line_pointer
, first
);
9063 if (second
!= 0 && *past_reloc
!= ' ')
9064 /* Replace the relocation token with ' ', so that
9065 errors like foo@SECLREL321 will be detected. */
9066 tmpbuf
[first
++] = ' ';
9067 memcpy (tmpbuf
+ first
, past_reloc
, second
);
9068 tmpbuf
[first
+ second
] = '\0';
9072 as_bad (_("@%s reloc is not supported with %d-bit output format"),
9073 gotrel
[j
].str
, 1 << (5 + object_64bit
));
9078 /* Might be a symbol version string. Don't as_bad here. */
9084 bfd_reloc_code_real_type
9085 x86_cons (expressionS
*exp
, int size
)
9087 bfd_reloc_code_real_type got_reloc
= NO_RELOC
;
9089 intel_syntax
= -intel_syntax
;
9092 if (size
== 4 || (object_64bit
&& size
== 8))
9094 /* Handle @GOTOFF and the like in an expression. */
9096 char *gotfree_input_line
;
9099 save
= input_line_pointer
;
9100 gotfree_input_line
= lex_got (&got_reloc
, &adjust
, NULL
);
9101 if (gotfree_input_line
)
9102 input_line_pointer
= gotfree_input_line
;
9106 if (gotfree_input_line
)
9108 /* expression () has merrily parsed up to the end of line,
9109 or a comma - in the wrong buffer. Transfer how far
9110 input_line_pointer has moved to the right buffer. */
9111 input_line_pointer
= (save
9112 + (input_line_pointer
- gotfree_input_line
)
9114 free (gotfree_input_line
);
9115 if (exp
->X_op
== O_constant
9116 || exp
->X_op
== O_absent
9117 || exp
->X_op
== O_illegal
9118 || exp
->X_op
== O_register
9119 || exp
->X_op
== O_big
)
9121 char c
= *input_line_pointer
;
9122 *input_line_pointer
= 0;
9123 as_bad (_("missing or invalid expression `%s'"), save
);
9124 *input_line_pointer
= c
;
9126 else if ((got_reloc
== BFD_RELOC_386_PLT32
9127 || got_reloc
== BFD_RELOC_X86_64_PLT32
)
9128 && exp
->X_op
!= O_symbol
)
9130 char c
= *input_line_pointer
;
9131 *input_line_pointer
= 0;
9132 as_bad (_("invalid PLT expression `%s'"), save
);
9133 *input_line_pointer
= c
;
9140 intel_syntax
= -intel_syntax
;
9143 i386_intel_simplify (exp
);
9149 signed_cons (int size
)
9151 if (flag_code
== CODE_64BIT
)
9159 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
9166 if (exp
.X_op
== O_symbol
)
9167 exp
.X_op
= O_secrel
;
9169 emit_expr (&exp
, 4);
9171 while (*input_line_pointer
++ == ',');
9173 input_line_pointer
--;
9174 demand_empty_rest_of_line ();
9178 /* Handle Vector operations. */
9181 check_VecOperations (char *op_string
, char *op_end
)
9183 const reg_entry
*mask
;
9188 && (op_end
== NULL
|| op_string
< op_end
))
9191 if (*op_string
== '{')
9195 /* Check broadcasts. */
9196 if (strncmp (op_string
, "1to", 3) == 0)
9201 goto duplicated_vec_op
;
9204 if (*op_string
== '8')
9206 else if (*op_string
== '4')
9208 else if (*op_string
== '2')
9210 else if (*op_string
== '1'
9211 && *(op_string
+1) == '6')
9218 as_bad (_("Unsupported broadcast: `%s'"), saved
);
9223 broadcast_op
.type
= bcst_type
;
9224 broadcast_op
.operand
= this_operand
;
9225 broadcast_op
.bytes
= 0;
9226 i
.broadcast
= &broadcast_op
;
9228 /* Check masking operation. */
9229 else if ((mask
= parse_register (op_string
, &end_op
)) != NULL
)
9231 /* k0 can't be used for write mask. */
9232 if (mask
->reg_type
.bitfield
.class != RegMask
|| !mask
->reg_num
)
9234 as_bad (_("`%s%s' can't be used for write mask"),
9235 register_prefix
, mask
->reg_name
);
9241 mask_op
.mask
= mask
;
9242 mask_op
.zeroing
= 0;
9243 mask_op
.operand
= this_operand
;
9249 goto duplicated_vec_op
;
9251 i
.mask
->mask
= mask
;
9253 /* Only "{z}" is allowed here. No need to check
9254 zeroing mask explicitly. */
9255 if (i
.mask
->operand
!= this_operand
)
9257 as_bad (_("invalid write mask `%s'"), saved
);
9264 /* Check zeroing-flag for masking operation. */
9265 else if (*op_string
== 'z')
9269 mask_op
.mask
= NULL
;
9270 mask_op
.zeroing
= 1;
9271 mask_op
.operand
= this_operand
;
9276 if (i
.mask
->zeroing
)
9279 as_bad (_("duplicated `%s'"), saved
);
9283 i
.mask
->zeroing
= 1;
9285 /* Only "{%k}" is allowed here. No need to check mask
9286 register explicitly. */
9287 if (i
.mask
->operand
!= this_operand
)
9289 as_bad (_("invalid zeroing-masking `%s'"),
9298 goto unknown_vec_op
;
9300 if (*op_string
!= '}')
9302 as_bad (_("missing `}' in `%s'"), saved
);
9307 /* Strip whitespace since the addition of pseudo prefixes
9308 changed how the scrubber treats '{'. */
9309 if (is_space_char (*op_string
))
9315 /* We don't know this one. */
9316 as_bad (_("unknown vector operation: `%s'"), saved
);
9320 if (i
.mask
&& i
.mask
->zeroing
&& !i
.mask
->mask
)
9322 as_bad (_("zeroing-masking only allowed with write mask"));
9330 i386_immediate (char *imm_start
)
9332 char *save_input_line_pointer
;
9333 char *gotfree_input_line
;
9336 i386_operand_type types
;
9338 operand_type_set (&types
, ~0);
9340 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
9342 as_bad (_("at most %d immediate operands are allowed"),
9343 MAX_IMMEDIATE_OPERANDS
);
9347 exp
= &im_expressions
[i
.imm_operands
++];
9348 i
.op
[this_operand
].imms
= exp
;
9350 if (is_space_char (*imm_start
))
9353 save_input_line_pointer
= input_line_pointer
;
9354 input_line_pointer
= imm_start
;
9356 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
9357 if (gotfree_input_line
)
9358 input_line_pointer
= gotfree_input_line
;
9360 exp_seg
= expression (exp
);
9364 /* Handle vector operations. */
9365 if (*input_line_pointer
== '{')
9367 input_line_pointer
= check_VecOperations (input_line_pointer
,
9369 if (input_line_pointer
== NULL
)
9373 if (*input_line_pointer
)
9374 as_bad (_("junk `%s' after expression"), input_line_pointer
);
9376 input_line_pointer
= save_input_line_pointer
;
9377 if (gotfree_input_line
)
9379 free (gotfree_input_line
);
9381 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
9382 exp
->X_op
= O_illegal
;
9385 return i386_finalize_immediate (exp_seg
, exp
, types
, imm_start
);
9389 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
9390 i386_operand_type types
, const char *imm_start
)
9392 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_illegal
|| exp
->X_op
== O_big
)
9395 as_bad (_("missing or invalid immediate expression `%s'"),
9399 else if (exp
->X_op
== O_constant
)
9401 /* Size it properly later. */
9402 i
.types
[this_operand
].bitfield
.imm64
= 1;
9403 /* If not 64bit, sign extend val. */
9404 if (flag_code
!= CODE_64BIT
9405 && (exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
9407 = (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
9409 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
9410 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
9411 && exp_seg
!= absolute_section
9412 && exp_seg
!= text_section
9413 && exp_seg
!= data_section
9414 && exp_seg
!= bss_section
9415 && exp_seg
!= undefined_section
9416 && !bfd_is_com_section (exp_seg
))
9418 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
9422 else if (!intel_syntax
&& exp_seg
== reg_section
)
9425 as_bad (_("illegal immediate register operand %s"), imm_start
);
9430 /* This is an address. The size of the address will be
9431 determined later, depending on destination register,
9432 suffix, or the default for the section. */
9433 i
.types
[this_operand
].bitfield
.imm8
= 1;
9434 i
.types
[this_operand
].bitfield
.imm16
= 1;
9435 i
.types
[this_operand
].bitfield
.imm32
= 1;
9436 i
.types
[this_operand
].bitfield
.imm32s
= 1;
9437 i
.types
[this_operand
].bitfield
.imm64
= 1;
9438 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
9446 i386_scale (char *scale
)
9449 char *save
= input_line_pointer
;
9451 input_line_pointer
= scale
;
9452 val
= get_absolute_expression ();
9457 i
.log2_scale_factor
= 0;
9460 i
.log2_scale_factor
= 1;
9463 i
.log2_scale_factor
= 2;
9466 i
.log2_scale_factor
= 3;
9470 char sep
= *input_line_pointer
;
9472 *input_line_pointer
= '\0';
9473 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
9475 *input_line_pointer
= sep
;
9476 input_line_pointer
= save
;
9480 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
9482 as_warn (_("scale factor of %d without an index register"),
9483 1 << i
.log2_scale_factor
);
9484 i
.log2_scale_factor
= 0;
9486 scale
= input_line_pointer
;
9487 input_line_pointer
= save
;
9492 i386_displacement (char *disp_start
, char *disp_end
)
9496 char *save_input_line_pointer
;
9497 char *gotfree_input_line
;
9499 i386_operand_type bigdisp
, types
= anydisp
;
9502 if (i
.disp_operands
== MAX_MEMORY_OPERANDS
)
9504 as_bad (_("at most %d displacement operands are allowed"),
9505 MAX_MEMORY_OPERANDS
);
9509 operand_type_set (&bigdisp
, 0);
9510 if ((i
.types
[this_operand
].bitfield
.jumpabsolute
)
9511 || (!current_templates
->start
->opcode_modifier
.jump
9512 && !current_templates
->start
->opcode_modifier
.jumpdword
))
9514 bigdisp
.bitfield
.disp32
= 1;
9515 override
= (i
.prefix
[ADDR_PREFIX
] != 0);
9516 if (flag_code
== CODE_64BIT
)
9520 bigdisp
.bitfield
.disp32s
= 1;
9521 bigdisp
.bitfield
.disp64
= 1;
9524 else if ((flag_code
== CODE_16BIT
) ^ override
)
9526 bigdisp
.bitfield
.disp32
= 0;
9527 bigdisp
.bitfield
.disp16
= 1;
9532 /* For PC-relative branches, the width of the displacement
9533 is dependent upon data size, not address size. */
9534 override
= (i
.prefix
[DATA_PREFIX
] != 0);
9535 if (flag_code
== CODE_64BIT
)
9537 if (override
|| i
.suffix
== WORD_MNEM_SUFFIX
)
9538 bigdisp
.bitfield
.disp16
= 1;
9541 bigdisp
.bitfield
.disp32
= 1;
9542 bigdisp
.bitfield
.disp32s
= 1;
9548 override
= (i
.suffix
== (flag_code
!= CODE_16BIT
9550 : LONG_MNEM_SUFFIX
));
9551 bigdisp
.bitfield
.disp32
= 1;
9552 if ((flag_code
== CODE_16BIT
) ^ override
)
9554 bigdisp
.bitfield
.disp32
= 0;
9555 bigdisp
.bitfield
.disp16
= 1;
9559 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
9562 exp
= &disp_expressions
[i
.disp_operands
];
9563 i
.op
[this_operand
].disps
= exp
;
9565 save_input_line_pointer
= input_line_pointer
;
9566 input_line_pointer
= disp_start
;
9567 END_STRING_AND_SAVE (disp_end
);
9569 #ifndef GCC_ASM_O_HACK
9570 #define GCC_ASM_O_HACK 0
9573 END_STRING_AND_SAVE (disp_end
+ 1);
9574 if (i
.types
[this_operand
].bitfield
.baseIndex
9575 && displacement_string_end
[-1] == '+')
9577 /* This hack is to avoid a warning when using the "o"
9578 constraint within gcc asm statements.
9581 #define _set_tssldt_desc(n,addr,limit,type) \
9582 __asm__ __volatile__ ( \
9584 "movw %w1,2+%0\n\t" \
9586 "movb %b1,4+%0\n\t" \
9587 "movb %4,5+%0\n\t" \
9588 "movb $0,6+%0\n\t" \
9589 "movb %h1,7+%0\n\t" \
9591 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
9593 This works great except that the output assembler ends
9594 up looking a bit weird if it turns out that there is
9595 no offset. You end up producing code that looks like:
9608 So here we provide the missing zero. */
9610 *displacement_string_end
= '0';
9613 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
9614 if (gotfree_input_line
)
9615 input_line_pointer
= gotfree_input_line
;
9617 exp_seg
= expression (exp
);
9620 if (*input_line_pointer
)
9621 as_bad (_("junk `%s' after expression"), input_line_pointer
);
9623 RESTORE_END_STRING (disp_end
+ 1);
9625 input_line_pointer
= save_input_line_pointer
;
9626 if (gotfree_input_line
)
9628 free (gotfree_input_line
);
9630 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
9631 exp
->X_op
= O_illegal
;
9634 ret
= i386_finalize_displacement (exp_seg
, exp
, types
, disp_start
);
9636 RESTORE_END_STRING (disp_end
);
9642 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
9643 i386_operand_type types
, const char *disp_start
)
9645 i386_operand_type bigdisp
;
9648 /* We do this to make sure that the section symbol is in
9649 the symbol table. We will ultimately change the relocation
9650 to be relative to the beginning of the section. */
9651 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
9652 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
9653 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
9655 if (exp
->X_op
!= O_symbol
)
9658 if (S_IS_LOCAL (exp
->X_add_symbol
)
9659 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
9660 && S_GET_SEGMENT (exp
->X_add_symbol
) != expr_section
)
9661 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
9662 exp
->X_op
= O_subtract
;
9663 exp
->X_op_symbol
= GOT_symbol
;
9664 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
9665 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
9666 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
9667 i
.reloc
[this_operand
] = BFD_RELOC_64
;
9669 i
.reloc
[this_operand
] = BFD_RELOC_32
;
9672 else if (exp
->X_op
== O_absent
9673 || exp
->X_op
== O_illegal
9674 || exp
->X_op
== O_big
)
9677 as_bad (_("missing or invalid displacement expression `%s'"),
9682 else if (flag_code
== CODE_64BIT
9683 && !i
.prefix
[ADDR_PREFIX
]
9684 && exp
->X_op
== O_constant
)
9686 /* Since displacement is signed extended to 64bit, don't allow
9687 disp32 and turn off disp32s if they are out of range. */
9688 i
.types
[this_operand
].bitfield
.disp32
= 0;
9689 if (!fits_in_signed_long (exp
->X_add_number
))
9691 i
.types
[this_operand
].bitfield
.disp32s
= 0;
9692 if (i
.types
[this_operand
].bitfield
.baseindex
)
9694 as_bad (_("0x%lx out range of signed 32bit displacement"),
9695 (long) exp
->X_add_number
);
9701 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
9702 else if (exp
->X_op
!= O_constant
9703 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
9704 && exp_seg
!= absolute_section
9705 && exp_seg
!= text_section
9706 && exp_seg
!= data_section
9707 && exp_seg
!= bss_section
9708 && exp_seg
!= undefined_section
9709 && !bfd_is_com_section (exp_seg
))
9711 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
9716 /* Check if this is a displacement only operand. */
9717 bigdisp
= i
.types
[this_operand
];
9718 bigdisp
.bitfield
.disp8
= 0;
9719 bigdisp
.bitfield
.disp16
= 0;
9720 bigdisp
.bitfield
.disp32
= 0;
9721 bigdisp
.bitfield
.disp32s
= 0;
9722 bigdisp
.bitfield
.disp64
= 0;
9723 if (operand_type_all_zero (&bigdisp
))
9724 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
9730 /* Return the active addressing mode, taking address override and
9731 registers forming the address into consideration. Update the
9732 address override prefix if necessary. */
9734 static enum flag_code
9735 i386_addressing_mode (void)
9737 enum flag_code addr_mode
;
9739 if (i
.prefix
[ADDR_PREFIX
])
9740 addr_mode
= flag_code
== CODE_32BIT
? CODE_16BIT
: CODE_32BIT
;
9743 addr_mode
= flag_code
;
9745 #if INFER_ADDR_PREFIX
9746 if (i
.mem_operands
== 0)
9748 /* Infer address prefix from the first memory operand. */
9749 const reg_entry
*addr_reg
= i
.base_reg
;
9751 if (addr_reg
== NULL
)
9752 addr_reg
= i
.index_reg
;
9756 if (addr_reg
->reg_type
.bitfield
.dword
)
9757 addr_mode
= CODE_32BIT
;
9758 else if (flag_code
!= CODE_64BIT
9759 && addr_reg
->reg_type
.bitfield
.word
)
9760 addr_mode
= CODE_16BIT
;
9762 if (addr_mode
!= flag_code
)
9764 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
9766 /* Change the size of any displacement too. At most one
9767 of Disp16 or Disp32 is set.
9768 FIXME. There doesn't seem to be any real need for
9769 separate Disp16 and Disp32 flags. The same goes for
9770 Imm16 and Imm32. Removing them would probably clean
9771 up the code quite a lot. */
9772 if (flag_code
!= CODE_64BIT
9773 && (i
.types
[this_operand
].bitfield
.disp16
9774 || i
.types
[this_operand
].bitfield
.disp32
))
9775 i
.types
[this_operand
]
9776 = operand_type_xor (i
.types
[this_operand
], disp16_32
);
9786 /* Make sure the memory operand we've been dealt is valid.
9787 Return 1 on success, 0 on a failure. */
9790 i386_index_check (const char *operand_string
)
9792 const char *kind
= "base/index";
9793 enum flag_code addr_mode
= i386_addressing_mode ();
9795 if (current_templates
->start
->opcode_modifier
.isstring
9796 && !current_templates
->start
->cpu_flags
.bitfield
.cpupadlock
9797 && (current_templates
->end
[-1].opcode_modifier
.isstring
9800 /* Memory operands of string insns are special in that they only allow
9801 a single register (rDI, rSI, or rBX) as their memory address. */
9802 const reg_entry
*expected_reg
;
9803 static const char *di_si
[][2] =
9809 static const char *bx
[] = { "ebx", "bx", "rbx" };
9811 kind
= "string address";
9813 if (current_templates
->start
->opcode_modifier
.repprefixok
)
9815 i386_operand_type type
= current_templates
->end
[-1].operand_types
[0];
9817 if (!type
.bitfield
.baseindex
9818 || ((!i
.mem_operands
!= !intel_syntax
)
9819 && current_templates
->end
[-1].operand_types
[1]
9820 .bitfield
.baseindex
))
9821 type
= current_templates
->end
[-1].operand_types
[1];
9822 expected_reg
= hash_find (reg_hash
,
9823 di_si
[addr_mode
][type
.bitfield
.esseg
]);
9827 expected_reg
= hash_find (reg_hash
, bx
[addr_mode
]);
9829 if (i
.base_reg
!= expected_reg
9831 || operand_type_check (i
.types
[this_operand
], disp
))
9833 /* The second memory operand must have the same size as
9837 && !((addr_mode
== CODE_64BIT
9838 && i
.base_reg
->reg_type
.bitfield
.qword
)
9839 || (addr_mode
== CODE_32BIT
9840 ? i
.base_reg
->reg_type
.bitfield
.dword
9841 : i
.base_reg
->reg_type
.bitfield
.word
)))
9844 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
9846 intel_syntax
? '[' : '(',
9848 expected_reg
->reg_name
,
9849 intel_syntax
? ']' : ')');
9856 as_bad (_("`%s' is not a valid %s expression"),
9857 operand_string
, kind
);
9862 if (addr_mode
!= CODE_16BIT
)
9864 /* 32-bit/64-bit checks. */
9866 && ((addr_mode
== CODE_64BIT
9867 ? !i
.base_reg
->reg_type
.bitfield
.qword
9868 : !i
.base_reg
->reg_type
.bitfield
.dword
)
9869 || (i
.index_reg
&& i
.base_reg
->reg_num
== RegIP
)
9870 || i
.base_reg
->reg_num
== RegIZ
))
9872 && !i
.index_reg
->reg_type
.bitfield
.xmmword
9873 && !i
.index_reg
->reg_type
.bitfield
.ymmword
9874 && !i
.index_reg
->reg_type
.bitfield
.zmmword
9875 && ((addr_mode
== CODE_64BIT
9876 ? !i
.index_reg
->reg_type
.bitfield
.qword
9877 : !i
.index_reg
->reg_type
.bitfield
.dword
)
9878 || !i
.index_reg
->reg_type
.bitfield
.baseindex
)))
9881 /* bndmk, bndldx, and bndstx have special restrictions. */
9882 if (current_templates
->start
->base_opcode
== 0xf30f1b
9883 || (current_templates
->start
->base_opcode
& ~1) == 0x0f1a)
9885 /* They cannot use RIP-relative addressing. */
9886 if (i
.base_reg
&& i
.base_reg
->reg_num
== RegIP
)
9888 as_bad (_("`%s' cannot be used here"), operand_string
);
9892 /* bndldx and bndstx ignore their scale factor. */
9893 if (current_templates
->start
->base_opcode
!= 0xf30f1b
9894 && i
.log2_scale_factor
)
9895 as_warn (_("register scaling is being ignored here"));
9900 /* 16-bit checks. */
9902 && (!i
.base_reg
->reg_type
.bitfield
.word
9903 || !i
.base_reg
->reg_type
.bitfield
.baseindex
))
9905 && (!i
.index_reg
->reg_type
.bitfield
.word
9906 || !i
.index_reg
->reg_type
.bitfield
.baseindex
9908 && i
.base_reg
->reg_num
< 6
9909 && i
.index_reg
->reg_num
>= 6
9910 && i
.log2_scale_factor
== 0))))
9917 /* Handle vector immediates. */
9920 RC_SAE_immediate (const char *imm_start
)
9922 unsigned int match_found
, j
;
9923 const char *pstr
= imm_start
;
9931 for (j
= 0; j
< ARRAY_SIZE (RC_NamesTable
); j
++)
9933 if (!strncmp (pstr
, RC_NamesTable
[j
].name
, RC_NamesTable
[j
].len
))
9937 rc_op
.type
= RC_NamesTable
[j
].type
;
9938 rc_op
.operand
= this_operand
;
9939 i
.rounding
= &rc_op
;
9943 as_bad (_("duplicated `%s'"), imm_start
);
9946 pstr
+= RC_NamesTable
[j
].len
;
9956 as_bad (_("Missing '}': '%s'"), imm_start
);
9959 /* RC/SAE immediate string should contain nothing more. */;
9962 as_bad (_("Junk after '}': '%s'"), imm_start
);
9966 exp
= &im_expressions
[i
.imm_operands
++];
9967 i
.op
[this_operand
].imms
= exp
;
9969 exp
->X_op
= O_constant
;
9970 exp
->X_add_number
= 0;
9971 exp
->X_add_symbol
= (symbolS
*) 0;
9972 exp
->X_op_symbol
= (symbolS
*) 0;
9974 i
.types
[this_operand
].bitfield
.imm8
= 1;
9978 /* Only string instructions can have a second memory operand, so
9979 reduce current_templates to just those if it contains any. */
9981 maybe_adjust_templates (void)
9983 const insn_template
*t
;
9985 gas_assert (i
.mem_operands
== 1);
9987 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
9988 if (t
->opcode_modifier
.isstring
)
9991 if (t
< current_templates
->end
)
9993 static templates aux_templates
;
9994 bfd_boolean recheck
;
9996 aux_templates
.start
= t
;
9997 for (; t
< current_templates
->end
; ++t
)
9998 if (!t
->opcode_modifier
.isstring
)
10000 aux_templates
.end
= t
;
10002 /* Determine whether to re-check the first memory operand. */
10003 recheck
= (aux_templates
.start
!= current_templates
->start
10004 || t
!= current_templates
->end
);
10006 current_templates
= &aux_templates
;
10010 i
.mem_operands
= 0;
10011 if (i
.memop1_string
!= NULL
10012 && i386_index_check (i
.memop1_string
) == 0)
10014 i
.mem_operands
= 1;
10021 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
10025 i386_att_operand (char *operand_string
)
10027 const reg_entry
*r
;
10029 char *op_string
= operand_string
;
10031 if (is_space_char (*op_string
))
10034 /* We check for an absolute prefix (differentiating,
10035 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
10036 if (*op_string
== ABSOLUTE_PREFIX
)
10039 if (is_space_char (*op_string
))
10041 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
10044 /* Check if operand is a register. */
10045 if ((r
= parse_register (op_string
, &end_op
)) != NULL
)
10047 i386_operand_type temp
;
10049 /* Check for a segment override by searching for ':' after a
10050 segment register. */
10051 op_string
= end_op
;
10052 if (is_space_char (*op_string
))
10054 if (*op_string
== ':' && r
->reg_type
.bitfield
.class == SReg
)
10056 switch (r
->reg_num
)
10059 i
.seg
[i
.mem_operands
] = &es
;
10062 i
.seg
[i
.mem_operands
] = &cs
;
10065 i
.seg
[i
.mem_operands
] = &ss
;
10068 i
.seg
[i
.mem_operands
] = &ds
;
10071 i
.seg
[i
.mem_operands
] = &fs
;
10074 i
.seg
[i
.mem_operands
] = &gs
;
10078 /* Skip the ':' and whitespace. */
10080 if (is_space_char (*op_string
))
10083 if (!is_digit_char (*op_string
)
10084 && !is_identifier_char (*op_string
)
10085 && *op_string
!= '('
10086 && *op_string
!= ABSOLUTE_PREFIX
)
10088 as_bad (_("bad memory operand `%s'"), op_string
);
10091 /* Handle case of %es:*foo. */
10092 if (*op_string
== ABSOLUTE_PREFIX
)
10095 if (is_space_char (*op_string
))
10097 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
10099 goto do_memory_reference
;
10102 /* Handle vector operations. */
10103 if (*op_string
== '{')
10105 op_string
= check_VecOperations (op_string
, NULL
);
10106 if (op_string
== NULL
)
10112 as_bad (_("junk `%s' after register"), op_string
);
10115 temp
= r
->reg_type
;
10116 temp
.bitfield
.baseindex
= 0;
10117 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
10119 i
.types
[this_operand
].bitfield
.unspecified
= 0;
10120 i
.op
[this_operand
].regs
= r
;
10123 else if (*op_string
== REGISTER_PREFIX
)
10125 as_bad (_("bad register name `%s'"), op_string
);
10128 else if (*op_string
== IMMEDIATE_PREFIX
)
10131 if (i
.types
[this_operand
].bitfield
.jumpabsolute
)
10133 as_bad (_("immediate operand illegal with absolute jump"));
10136 if (!i386_immediate (op_string
))
10139 else if (RC_SAE_immediate (operand_string
))
10141 /* If it is a RC or SAE immediate, do nothing. */
10144 else if (is_digit_char (*op_string
)
10145 || is_identifier_char (*op_string
)
10146 || *op_string
== '"'
10147 || *op_string
== '(')
10149 /* This is a memory reference of some sort. */
10152 /* Start and end of displacement string expression (if found). */
10153 char *displacement_string_start
;
10154 char *displacement_string_end
;
10157 do_memory_reference
:
10158 if (i
.mem_operands
== 1 && !maybe_adjust_templates ())
10160 if ((i
.mem_operands
== 1
10161 && !current_templates
->start
->opcode_modifier
.isstring
)
10162 || i
.mem_operands
== 2)
10164 as_bad (_("too many memory references for `%s'"),
10165 current_templates
->start
->name
);
10169 /* Check for base index form. We detect the base index form by
10170 looking for an ')' at the end of the operand, searching
10171 for the '(' matching it, and finding a REGISTER_PREFIX or ','
10173 base_string
= op_string
+ strlen (op_string
);
10175 /* Handle vector operations. */
10176 vop_start
= strchr (op_string
, '{');
10177 if (vop_start
&& vop_start
< base_string
)
10179 if (check_VecOperations (vop_start
, base_string
) == NULL
)
10181 base_string
= vop_start
;
10185 if (is_space_char (*base_string
))
10188 /* If we only have a displacement, set-up for it to be parsed later. */
10189 displacement_string_start
= op_string
;
10190 displacement_string_end
= base_string
+ 1;
10192 if (*base_string
== ')')
10195 unsigned int parens_balanced
= 1;
10196 /* We've already checked that the number of left & right ()'s are
10197 equal, so this loop will not be infinite. */
10201 if (*base_string
== ')')
10203 if (*base_string
== '(')
10206 while (parens_balanced
);
10208 temp_string
= base_string
;
10210 /* Skip past '(' and whitespace. */
10212 if (is_space_char (*base_string
))
10215 if (*base_string
== ','
10216 || ((i
.base_reg
= parse_register (base_string
, &end_op
))
10219 displacement_string_end
= temp_string
;
10221 i
.types
[this_operand
].bitfield
.baseindex
= 1;
10225 base_string
= end_op
;
10226 if (is_space_char (*base_string
))
10230 /* There may be an index reg or scale factor here. */
10231 if (*base_string
== ',')
10234 if (is_space_char (*base_string
))
10237 if ((i
.index_reg
= parse_register (base_string
, &end_op
))
10240 base_string
= end_op
;
10241 if (is_space_char (*base_string
))
10243 if (*base_string
== ',')
10246 if (is_space_char (*base_string
))
10249 else if (*base_string
!= ')')
10251 as_bad (_("expecting `,' or `)' "
10252 "after index register in `%s'"),
10257 else if (*base_string
== REGISTER_PREFIX
)
10259 end_op
= strchr (base_string
, ',');
10262 as_bad (_("bad register name `%s'"), base_string
);
10266 /* Check for scale factor. */
10267 if (*base_string
!= ')')
10269 char *end_scale
= i386_scale (base_string
);
10274 base_string
= end_scale
;
10275 if (is_space_char (*base_string
))
10277 if (*base_string
!= ')')
10279 as_bad (_("expecting `)' "
10280 "after scale factor in `%s'"),
10285 else if (!i
.index_reg
)
10287 as_bad (_("expecting index register or scale factor "
10288 "after `,'; got '%c'"),
10293 else if (*base_string
!= ')')
10295 as_bad (_("expecting `,' or `)' "
10296 "after base register in `%s'"),
10301 else if (*base_string
== REGISTER_PREFIX
)
10303 end_op
= strchr (base_string
, ',');
10306 as_bad (_("bad register name `%s'"), base_string
);
10311 /* If there's an expression beginning the operand, parse it,
10312 assuming displacement_string_start and
10313 displacement_string_end are meaningful. */
10314 if (displacement_string_start
!= displacement_string_end
)
10316 if (!i386_displacement (displacement_string_start
,
10317 displacement_string_end
))
10321 /* Special case for (%dx) while doing input/output op. */
10323 && i
.base_reg
->reg_type
.bitfield
.inoutportreg
10324 && i
.index_reg
== 0
10325 && i
.log2_scale_factor
== 0
10326 && i
.seg
[i
.mem_operands
] == 0
10327 && !operand_type_check (i
.types
[this_operand
], disp
))
10329 i
.types
[this_operand
] = i
.base_reg
->reg_type
;
10333 if (i386_index_check (operand_string
) == 0)
10335 i
.flags
[this_operand
] |= Operand_Mem
;
10336 if (i
.mem_operands
== 0)
10337 i
.memop1_string
= xstrdup (operand_string
);
10342 /* It's not a memory operand; argh! */
10343 as_bad (_("invalid char %s beginning operand %d `%s'"),
10344 output_invalid (*op_string
),
10349 return 1; /* Normal return. */
10352 /* Calculate the maximum variable size (i.e., excluding fr_fix)
10353 that an rs_machine_dependent frag may reach. */
10356 i386_frag_max_var (fragS
*frag
)
10358 /* The only relaxable frags are for jumps.
10359 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
10360 gas_assert (frag
->fr_type
== rs_machine_dependent
);
10361 return TYPE_FROM_RELAX_STATE (frag
->fr_subtype
) == UNCOND_JUMP
? 4 : 5;
10364 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10366 elf_symbol_resolved_in_segment_p (symbolS
*fr_symbol
, offsetT fr_var
)
10368 /* STT_GNU_IFUNC symbol must go through PLT. */
10369 if ((symbol_get_bfdsym (fr_symbol
)->flags
10370 & BSF_GNU_INDIRECT_FUNCTION
) != 0)
10373 if (!S_IS_EXTERNAL (fr_symbol
))
10374 /* Symbol may be weak or local. */
10375 return !S_IS_WEAK (fr_symbol
);
10377 /* Global symbols with non-default visibility can't be preempted. */
10378 if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol
)) != STV_DEFAULT
)
10381 if (fr_var
!= NO_RELOC
)
10382 switch ((enum bfd_reloc_code_real
) fr_var
)
10384 case BFD_RELOC_386_PLT32
:
10385 case BFD_RELOC_X86_64_PLT32
:
10386 /* Symbol with PLT relocation may be preempted. */
10392 /* Global symbols with default visibility in a shared library may be
10393 preempted by another definition. */
10398 /* md_estimate_size_before_relax()
10400 Called just before relax() for rs_machine_dependent frags. The x86
10401 assembler uses these frags to handle variable size jump
10404 Any symbol that is now undefined will not become defined.
10405 Return the correct fr_subtype in the frag.
10406 Return the initial "guess for variable size of frag" to caller.
10407 The guess is actually the growth beyond the fixed part. Whatever
10408 we do to grow the fixed or variable part contributes to our
10412 md_estimate_size_before_relax (fragS
*fragP
, segT segment
)
10414 /* We've already got fragP->fr_subtype right; all we have to do is
10415 check for un-relaxable symbols. On an ELF system, we can't relax
10416 an externally visible symbol, because it may be overridden by a
10418 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
10419 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10421 && !elf_symbol_resolved_in_segment_p (fragP
->fr_symbol
,
10424 #if defined (OBJ_COFF) && defined (TE_PE)
10425 || (OUTPUT_FLAVOR
== bfd_target_coff_flavour
10426 && S_IS_WEAK (fragP
->fr_symbol
))
10430 /* Symbol is undefined in this segment, or we need to keep a
10431 reloc so that weak symbols can be overridden. */
10432 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
10433 enum bfd_reloc_code_real reloc_type
;
10434 unsigned char *opcode
;
10437 if (fragP
->fr_var
!= NO_RELOC
)
10438 reloc_type
= (enum bfd_reloc_code_real
) fragP
->fr_var
;
10439 else if (size
== 2)
10440 reloc_type
= BFD_RELOC_16_PCREL
;
10441 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10442 else if (need_plt32_p (fragP
->fr_symbol
))
10443 reloc_type
= BFD_RELOC_X86_64_PLT32
;
10446 reloc_type
= BFD_RELOC_32_PCREL
;
10448 old_fr_fix
= fragP
->fr_fix
;
10449 opcode
= (unsigned char *) fragP
->fr_opcode
;
10451 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
10454 /* Make jmp (0xeb) a (d)word displacement jump. */
10456 fragP
->fr_fix
+= size
;
10457 fix_new (fragP
, old_fr_fix
, size
,
10459 fragP
->fr_offset
, 1,
10465 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
10467 /* Negate the condition, and branch past an
10468 unconditional jump. */
10471 /* Insert an unconditional jump. */
10473 /* We added two extra opcode bytes, and have a two byte
10475 fragP
->fr_fix
+= 2 + 2;
10476 fix_new (fragP
, old_fr_fix
+ 2, 2,
10478 fragP
->fr_offset
, 1,
10482 /* Fall through. */
10485 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
10489 fragP
->fr_fix
+= 1;
10490 fixP
= fix_new (fragP
, old_fr_fix
, 1,
10492 fragP
->fr_offset
, 1,
10493 BFD_RELOC_8_PCREL
);
10494 fixP
->fx_signed
= 1;
10498 /* This changes the byte-displacement jump 0x7N
10499 to the (d)word-displacement jump 0x0f,0x8N. */
10500 opcode
[1] = opcode
[0] + 0x10;
10501 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
10502 /* We've added an opcode byte. */
10503 fragP
->fr_fix
+= 1 + size
;
10504 fix_new (fragP
, old_fr_fix
+ 1, size
,
10506 fragP
->fr_offset
, 1,
10511 BAD_CASE (fragP
->fr_subtype
);
10515 return fragP
->fr_fix
- old_fr_fix
;
10518 /* Guess size depending on current relax state. Initially the relax
10519 state will correspond to a short jump and we return 1, because
10520 the variable part of the frag (the branch offset) is one byte
10521 long. However, we can relax a section more than once and in that
10522 case we must either set fr_subtype back to the unrelaxed state,
10523 or return the value for the appropriate branch. */
10524 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
10527 /* Called after relax() is finished.
10529 In: Address of frag.
10530 fr_type == rs_machine_dependent.
10531 fr_subtype is what the address relaxed to.
10533 Out: Any fixSs and constants are set up.
10534 Caller will turn frag into a ".space 0". */
10537 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec ATTRIBUTE_UNUSED
,
10540 unsigned char *opcode
;
10541 unsigned char *where_to_put_displacement
= NULL
;
10542 offsetT target_address
;
10543 offsetT opcode_address
;
10544 unsigned int extension
= 0;
10545 offsetT displacement_from_opcode_start
;
10547 opcode
= (unsigned char *) fragP
->fr_opcode
;
10549 /* Address we want to reach in file space. */
10550 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
10552 /* Address opcode resides at in file space. */
10553 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
10555 /* Displacement from opcode start to fill into instruction. */
10556 displacement_from_opcode_start
= target_address
- opcode_address
;
10558 if ((fragP
->fr_subtype
& BIG
) == 0)
10560 /* Don't have to change opcode. */
10561 extension
= 1; /* 1 opcode + 1 displacement */
10562 where_to_put_displacement
= &opcode
[1];
10566 if (no_cond_jump_promotion
10567 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
10568 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
10569 _("long jump required"));
10571 switch (fragP
->fr_subtype
)
10573 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
10574 extension
= 4; /* 1 opcode + 4 displacement */
10576 where_to_put_displacement
= &opcode
[1];
10579 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
10580 extension
= 2; /* 1 opcode + 2 displacement */
10582 where_to_put_displacement
= &opcode
[1];
10585 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
10586 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
10587 extension
= 5; /* 2 opcode + 4 displacement */
10588 opcode
[1] = opcode
[0] + 0x10;
10589 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
10590 where_to_put_displacement
= &opcode
[2];
10593 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
10594 extension
= 3; /* 2 opcode + 2 displacement */
10595 opcode
[1] = opcode
[0] + 0x10;
10596 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
10597 where_to_put_displacement
= &opcode
[2];
10600 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
10605 where_to_put_displacement
= &opcode
[3];
10609 BAD_CASE (fragP
->fr_subtype
);
10614 /* If size if less then four we are sure that the operand fits,
10615 but if it's 4, then it could be that the displacement is larger
10617 if (DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
) == 4
10619 && ((addressT
) (displacement_from_opcode_start
- extension
10620 + ((addressT
) 1 << 31))
10621 > (((addressT
) 2 << 31) - 1)))
10623 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
10624 _("jump target out of range"));
10625 /* Make us emit 0. */
10626 displacement_from_opcode_start
= extension
;
10628 /* Now put displacement after opcode. */
10629 md_number_to_chars ((char *) where_to_put_displacement
,
10630 (valueT
) (displacement_from_opcode_start
- extension
),
10631 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
10632 fragP
->fr_fix
+= extension
;
10635 /* Apply a fixup (fixP) to segment data, once it has been determined
10636 by our caller that we have all the info we need to fix it up.
10638 Parameter valP is the pointer to the value of the bits.
10640 On the 386, immediates, displacements, and data pointers are all in
10641 the same (little-endian) format, so we don't need to care about which
10642 we are handling. */
10645 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
10647 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
10648 valueT value
= *valP
;
10650 #if !defined (TE_Mach)
10651 if (fixP
->fx_pcrel
)
10653 switch (fixP
->fx_r_type
)
10659 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
10662 case BFD_RELOC_X86_64_32S
:
10663 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
10666 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
10669 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
10674 if (fixP
->fx_addsy
!= NULL
10675 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
10676 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
10677 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
10678 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
10679 && !use_rela_relocations
)
10681 /* This is a hack. There should be a better way to handle this.
10682 This covers for the fact that bfd_install_relocation will
10683 subtract the current location (for partial_inplace, PC relative
10684 relocations); see more below. */
10688 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
10691 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
10693 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10696 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
10698 if ((sym_seg
== seg
10699 || (symbol_section_p (fixP
->fx_addsy
)
10700 && sym_seg
!= absolute_section
))
10701 && !generic_force_reloc (fixP
))
10703 /* Yes, we add the values in twice. This is because
10704 bfd_install_relocation subtracts them out again. I think
10705 bfd_install_relocation is broken, but I don't dare change
10707 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
10711 #if defined (OBJ_COFF) && defined (TE_PE)
10712 /* For some reason, the PE format does not store a
10713 section address offset for a PC relative symbol. */
10714 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
10715 || S_IS_WEAK (fixP
->fx_addsy
))
10716 value
+= md_pcrel_from (fixP
);
10719 #if defined (OBJ_COFF) && defined (TE_PE)
10720 if (fixP
->fx_addsy
!= NULL
10721 && S_IS_WEAK (fixP
->fx_addsy
)
10722 /* PR 16858: Do not modify weak function references. */
10723 && ! fixP
->fx_pcrel
)
10725 #if !defined (TE_PEP)
10726 /* For x86 PE weak function symbols are neither PC-relative
10727 nor do they set S_IS_FUNCTION. So the only reliable way
10728 to detect them is to check the flags of their containing
10730 if (S_GET_SEGMENT (fixP
->fx_addsy
) != NULL
10731 && S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_CODE
)
10735 value
-= S_GET_VALUE (fixP
->fx_addsy
);
10739 /* Fix a few things - the dynamic linker expects certain values here,
10740 and we must not disappoint it. */
10741 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10742 if (IS_ELF
&& fixP
->fx_addsy
)
10743 switch (fixP
->fx_r_type
)
10745 case BFD_RELOC_386_PLT32
:
10746 case BFD_RELOC_X86_64_PLT32
:
10747 /* Make the jump instruction point to the address of the operand.
10748 At runtime we merely add the offset to the actual PLT entry.
10749 NB: Subtract the offset size only for jump instructions. */
10750 if (fixP
->fx_pcrel
)
10754 case BFD_RELOC_386_TLS_GD
:
10755 case BFD_RELOC_386_TLS_LDM
:
10756 case BFD_RELOC_386_TLS_IE_32
:
10757 case BFD_RELOC_386_TLS_IE
:
10758 case BFD_RELOC_386_TLS_GOTIE
:
10759 case BFD_RELOC_386_TLS_GOTDESC
:
10760 case BFD_RELOC_X86_64_TLSGD
:
10761 case BFD_RELOC_X86_64_TLSLD
:
10762 case BFD_RELOC_X86_64_GOTTPOFF
:
10763 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
10764 value
= 0; /* Fully resolved at runtime. No addend. */
10766 case BFD_RELOC_386_TLS_LE
:
10767 case BFD_RELOC_386_TLS_LDO_32
:
10768 case BFD_RELOC_386_TLS_LE_32
:
10769 case BFD_RELOC_X86_64_DTPOFF32
:
10770 case BFD_RELOC_X86_64_DTPOFF64
:
10771 case BFD_RELOC_X86_64_TPOFF32
:
10772 case BFD_RELOC_X86_64_TPOFF64
:
10773 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
10776 case BFD_RELOC_386_TLS_DESC_CALL
:
10777 case BFD_RELOC_X86_64_TLSDESC_CALL
:
10778 value
= 0; /* Fully resolved at runtime. No addend. */
10779 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
10783 case BFD_RELOC_VTABLE_INHERIT
:
10784 case BFD_RELOC_VTABLE_ENTRY
:
10791 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
10793 #endif /* !defined (TE_Mach) */
10795 /* Are we finished with this relocation now? */
10796 if (fixP
->fx_addsy
== NULL
)
10798 #if defined (OBJ_COFF) && defined (TE_PE)
10799 else if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
10802 /* Remember value for tc_gen_reloc. */
10803 fixP
->fx_addnumber
= value
;
10804 /* Clear out the frag for now. */
10808 else if (use_rela_relocations
)
10810 fixP
->fx_no_overflow
= 1;
10811 /* Remember value for tc_gen_reloc. */
10812 fixP
->fx_addnumber
= value
;
10816 md_number_to_chars (p
, value
, fixP
->fx_size
);
10820 md_atof (int type
, char *litP
, int *sizeP
)
10822 /* This outputs the LITTLENUMs in REVERSE order;
10823 in accord with the bigendian 386. */
10824 return ieee_md_atof (type
, litP
, sizeP
, FALSE
);
10827 static char output_invalid_buf
[sizeof (unsigned char) * 2 + 6];
10830 output_invalid (int c
)
10833 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
10836 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
10837 "(0x%x)", (unsigned char) c
);
10838 return output_invalid_buf
;
10841 /* REG_STRING starts *before* REGISTER_PREFIX. */
10843 static const reg_entry
*
10844 parse_real_register (char *reg_string
, char **end_op
)
10846 char *s
= reg_string
;
10848 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
10849 const reg_entry
*r
;
10851 /* Skip possible REGISTER_PREFIX and possible whitespace. */
10852 if (*s
== REGISTER_PREFIX
)
10855 if (is_space_char (*s
))
10858 p
= reg_name_given
;
10859 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
10861 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
10862 return (const reg_entry
*) NULL
;
10866 /* For naked regs, make sure that we are not dealing with an identifier.
10867 This prevents confusing an identifier like `eax_var' with register
10869 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
10870 return (const reg_entry
*) NULL
;
10874 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
10876 /* Handle floating point regs, allowing spaces in the (i) part. */
10877 if (r
== i386_regtab
/* %st is first entry of table */)
10879 if (!cpu_arch_flags
.bitfield
.cpu8087
10880 && !cpu_arch_flags
.bitfield
.cpu287
10881 && !cpu_arch_flags
.bitfield
.cpu387
)
10882 return (const reg_entry
*) NULL
;
10884 if (is_space_char (*s
))
10889 if (is_space_char (*s
))
10891 if (*s
>= '0' && *s
<= '7')
10893 int fpr
= *s
- '0';
10895 if (is_space_char (*s
))
10900 r
= (const reg_entry
*) hash_find (reg_hash
, "st(0)");
10905 /* We have "%st(" then garbage. */
10906 return (const reg_entry
*) NULL
;
10910 if (r
== NULL
|| allow_pseudo_reg
)
10913 if (operand_type_all_zero (&r
->reg_type
))
10914 return (const reg_entry
*) NULL
;
10916 if ((r
->reg_type
.bitfield
.dword
10917 || (r
->reg_type
.bitfield
.class == SReg
&& r
->reg_num
> 3)
10918 || r
->reg_type
.bitfield
.class == RegCR
10919 || r
->reg_type
.bitfield
.class == RegDR
10920 || r
->reg_type
.bitfield
.class == RegTR
)
10921 && !cpu_arch_flags
.bitfield
.cpui386
)
10922 return (const reg_entry
*) NULL
;
10924 if (r
->reg_type
.bitfield
.class == RegMMX
&& !cpu_arch_flags
.bitfield
.cpummx
)
10925 return (const reg_entry
*) NULL
;
10927 if (!cpu_arch_flags
.bitfield
.cpuavx512f
)
10929 if (r
->reg_type
.bitfield
.zmmword
10930 || r
->reg_type
.bitfield
.class == RegMask
)
10931 return (const reg_entry
*) NULL
;
10933 if (!cpu_arch_flags
.bitfield
.cpuavx
)
10935 if (r
->reg_type
.bitfield
.ymmword
)
10936 return (const reg_entry
*) NULL
;
10938 if (!cpu_arch_flags
.bitfield
.cpusse
&& r
->reg_type
.bitfield
.xmmword
)
10939 return (const reg_entry
*) NULL
;
10943 if (r
->reg_type
.bitfield
.class == RegBND
&& !cpu_arch_flags
.bitfield
.cpumpx
)
10944 return (const reg_entry
*) NULL
;
10946 /* Don't allow fake index register unless allow_index_reg isn't 0. */
10947 if (!allow_index_reg
&& r
->reg_num
== RegIZ
)
10948 return (const reg_entry
*) NULL
;
10950 /* Upper 16 vector registers are only available with VREX in 64bit
10951 mode, and require EVEX encoding. */
10952 if (r
->reg_flags
& RegVRex
)
10954 if (!cpu_arch_flags
.bitfield
.cpuavx512f
10955 || flag_code
!= CODE_64BIT
)
10956 return (const reg_entry
*) NULL
;
10958 i
.vec_encoding
= vex_encoding_evex
;
10961 if (((r
->reg_flags
& (RegRex64
| RegRex
)) || r
->reg_type
.bitfield
.qword
)
10962 && (!cpu_arch_flags
.bitfield
.cpulm
|| r
->reg_type
.bitfield
.class != RegCR
)
10963 && flag_code
!= CODE_64BIT
)
10964 return (const reg_entry
*) NULL
;
10966 if (r
->reg_type
.bitfield
.class == SReg
&& r
->reg_num
== RegFlat
10968 return (const reg_entry
*) NULL
;
10973 /* REG_STRING starts *before* REGISTER_PREFIX. */
10975 static const reg_entry
*
10976 parse_register (char *reg_string
, char **end_op
)
10978 const reg_entry
*r
;
10980 if (*reg_string
== REGISTER_PREFIX
|| allow_naked_reg
)
10981 r
= parse_real_register (reg_string
, end_op
);
10986 char *save
= input_line_pointer
;
10990 input_line_pointer
= reg_string
;
10991 c
= get_symbol_name (®_string
);
10992 symbolP
= symbol_find (reg_string
);
10993 if (symbolP
&& S_GET_SEGMENT (symbolP
) == reg_section
)
10995 const expressionS
*e
= symbol_get_value_expression (symbolP
);
10997 know (e
->X_op
== O_register
);
10998 know (e
->X_add_number
>= 0
10999 && (valueT
) e
->X_add_number
< i386_regtab_size
);
11000 r
= i386_regtab
+ e
->X_add_number
;
11001 if ((r
->reg_flags
& RegVRex
))
11002 i
.vec_encoding
= vex_encoding_evex
;
11003 *end_op
= input_line_pointer
;
11005 *input_line_pointer
= c
;
11006 input_line_pointer
= save
;
11012 i386_parse_name (char *name
, expressionS
*e
, char *nextcharP
)
11014 const reg_entry
*r
;
11015 char *end
= input_line_pointer
;
11018 r
= parse_register (name
, &input_line_pointer
);
11019 if (r
&& end
<= input_line_pointer
)
11021 *nextcharP
= *input_line_pointer
;
11022 *input_line_pointer
= 0;
11023 e
->X_op
= O_register
;
11024 e
->X_add_number
= r
- i386_regtab
;
11027 input_line_pointer
= end
;
11029 return intel_syntax
? i386_intel_parse_name (name
, e
) : 0;
11033 md_operand (expressionS
*e
)
11036 const reg_entry
*r
;
11038 switch (*input_line_pointer
)
11040 case REGISTER_PREFIX
:
11041 r
= parse_real_register (input_line_pointer
, &end
);
11044 e
->X_op
= O_register
;
11045 e
->X_add_number
= r
- i386_regtab
;
11046 input_line_pointer
= end
;
11051 gas_assert (intel_syntax
);
11052 end
= input_line_pointer
++;
11054 if (*input_line_pointer
== ']')
11056 ++input_line_pointer
;
11057 e
->X_op_symbol
= make_expr_symbol (e
);
11058 e
->X_add_symbol
= NULL
;
11059 e
->X_add_number
= 0;
11064 e
->X_op
= O_absent
;
11065 input_line_pointer
= end
;
11072 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11073 const char *md_shortopts
= "kVQ:sqnO::";
11075 const char *md_shortopts
= "qnO::";
11078 #define OPTION_32 (OPTION_MD_BASE + 0)
11079 #define OPTION_64 (OPTION_MD_BASE + 1)
11080 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
11081 #define OPTION_MARCH (OPTION_MD_BASE + 3)
11082 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
11083 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
11084 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
11085 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
11086 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
11087 #define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 9)
11088 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
11089 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
11090 #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
11091 #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
11092 #define OPTION_X32 (OPTION_MD_BASE + 14)
11093 #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
11094 #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
11095 #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
11096 #define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
11097 #define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
11098 #define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
11099 #define OPTION_MSHARED (OPTION_MD_BASE + 21)
11100 #define OPTION_MAMD64 (OPTION_MD_BASE + 22)
11101 #define OPTION_MINTEL64 (OPTION_MD_BASE + 23)
11102 #define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24)
11103 #define OPTION_X86_USED_NOTE (OPTION_MD_BASE + 25)
11104 #define OPTION_MVEXWIG (OPTION_MD_BASE + 26)
11106 struct option md_longopts
[] =
11108 {"32", no_argument
, NULL
, OPTION_32
},
11109 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
11110 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
11111 {"64", no_argument
, NULL
, OPTION_64
},
11113 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11114 {"x32", no_argument
, NULL
, OPTION_X32
},
11115 {"mshared", no_argument
, NULL
, OPTION_MSHARED
},
11116 {"mx86-used-note", required_argument
, NULL
, OPTION_X86_USED_NOTE
},
11118 {"divide", no_argument
, NULL
, OPTION_DIVIDE
},
11119 {"march", required_argument
, NULL
, OPTION_MARCH
},
11120 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
11121 {"mmnemonic", required_argument
, NULL
, OPTION_MMNEMONIC
},
11122 {"msyntax", required_argument
, NULL
, OPTION_MSYNTAX
},
11123 {"mindex-reg", no_argument
, NULL
, OPTION_MINDEX_REG
},
11124 {"mnaked-reg", no_argument
, NULL
, OPTION_MNAKED_REG
},
11125 {"msse2avx", no_argument
, NULL
, OPTION_MSSE2AVX
},
11126 {"msse-check", required_argument
, NULL
, OPTION_MSSE_CHECK
},
11127 {"moperand-check", required_argument
, NULL
, OPTION_MOPERAND_CHECK
},
11128 {"mavxscalar", required_argument
, NULL
, OPTION_MAVXSCALAR
},
11129 {"mvexwig", required_argument
, NULL
, OPTION_MVEXWIG
},
11130 {"madd-bnd-prefix", no_argument
, NULL
, OPTION_MADD_BND_PREFIX
},
11131 {"mevexlig", required_argument
, NULL
, OPTION_MEVEXLIG
},
11132 {"mevexwig", required_argument
, NULL
, OPTION_MEVEXWIG
},
11133 # if defined (TE_PE) || defined (TE_PEP)
11134 {"mbig-obj", no_argument
, NULL
, OPTION_MBIG_OBJ
},
11136 {"momit-lock-prefix", required_argument
, NULL
, OPTION_MOMIT_LOCK_PREFIX
},
11137 {"mfence-as-lock-add", required_argument
, NULL
, OPTION_MFENCE_AS_LOCK_ADD
},
11138 {"mrelax-relocations", required_argument
, NULL
, OPTION_MRELAX_RELOCATIONS
},
11139 {"mevexrcig", required_argument
, NULL
, OPTION_MEVEXRCIG
},
11140 {"mamd64", no_argument
, NULL
, OPTION_MAMD64
},
11141 {"mintel64", no_argument
, NULL
, OPTION_MINTEL64
},
11142 {NULL
, no_argument
, NULL
, 0}
11144 size_t md_longopts_size
= sizeof (md_longopts
);
11147 md_parse_option (int c
, const char *arg
)
11150 char *arch
, *next
, *saved
;
11155 optimize_align_code
= 0;
11159 quiet_warnings
= 1;
11162 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11163 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
11164 should be emitted or not. FIXME: Not implemented. */
11166 if ((arg
[0] != 'y' && arg
[0] != 'n') || arg
[1])
11170 /* -V: SVR4 argument to print version ID. */
11172 print_version_id ();
11175 /* -k: Ignore for FreeBSD compatibility. */
11180 /* -s: On i386 Solaris, this tells the native assembler to use
11181 .stab instead of .stab.excl. We always use .stab anyhow. */
11184 case OPTION_MSHARED
:
11188 case OPTION_X86_USED_NOTE
:
11189 if (strcasecmp (arg
, "yes") == 0)
11191 else if (strcasecmp (arg
, "no") == 0)
11194 as_fatal (_("invalid -mx86-used-note= option: `%s'"), arg
);
11199 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
11200 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
11203 const char **list
, **l
;
11205 list
= bfd_target_list ();
11206 for (l
= list
; *l
!= NULL
; l
++)
11207 if (CONST_STRNEQ (*l
, "elf64-x86-64")
11208 || strcmp (*l
, "coff-x86-64") == 0
11209 || strcmp (*l
, "pe-x86-64") == 0
11210 || strcmp (*l
, "pei-x86-64") == 0
11211 || strcmp (*l
, "mach-o-x86-64") == 0)
11213 default_arch
= "x86_64";
11217 as_fatal (_("no compiled in support for x86_64"));
11223 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11227 const char **list
, **l
;
11229 list
= bfd_target_list ();
11230 for (l
= list
; *l
!= NULL
; l
++)
11231 if (CONST_STRNEQ (*l
, "elf32-x86-64"))
11233 default_arch
= "x86_64:32";
11237 as_fatal (_("no compiled in support for 32bit x86_64"));
11241 as_fatal (_("32bit x86_64 is only supported for ELF"));
11246 default_arch
= "i386";
11249 case OPTION_DIVIDE
:
11250 #ifdef SVR4_COMMENT_CHARS
11255 n
= XNEWVEC (char, strlen (i386_comment_chars
) + 1);
11257 for (s
= i386_comment_chars
; *s
!= '\0'; s
++)
11261 i386_comment_chars
= n
;
11267 saved
= xstrdup (arg
);
11269 /* Allow -march=+nosse. */
11275 as_fatal (_("invalid -march= option: `%s'"), arg
);
11276 next
= strchr (arch
, '+');
11279 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
11281 if (strcmp (arch
, cpu_arch
[j
].name
) == 0)
11284 if (! cpu_arch
[j
].flags
.bitfield
.cpui386
)
11287 cpu_arch_name
= cpu_arch
[j
].name
;
11288 cpu_sub_arch_name
= NULL
;
11289 cpu_arch_flags
= cpu_arch
[j
].flags
;
11290 cpu_arch_isa
= cpu_arch
[j
].type
;
11291 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
11292 if (!cpu_arch_tune_set
)
11294 cpu_arch_tune
= cpu_arch_isa
;
11295 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
11299 else if (*cpu_arch
[j
].name
== '.'
11300 && strcmp (arch
, cpu_arch
[j
].name
+ 1) == 0)
11302 /* ISA extension. */
11303 i386_cpu_flags flags
;
11305 flags
= cpu_flags_or (cpu_arch_flags
,
11306 cpu_arch
[j
].flags
);
11308 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
11310 if (cpu_sub_arch_name
)
11312 char *name
= cpu_sub_arch_name
;
11313 cpu_sub_arch_name
= concat (name
,
11315 (const char *) NULL
);
11319 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
11320 cpu_arch_flags
= flags
;
11321 cpu_arch_isa_flags
= flags
;
11325 = cpu_flags_or (cpu_arch_isa_flags
,
11326 cpu_arch
[j
].flags
);
11331 if (j
>= ARRAY_SIZE (cpu_arch
))
11333 /* Disable an ISA extension. */
11334 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
11335 if (strcmp (arch
, cpu_noarch
[j
].name
) == 0)
11337 i386_cpu_flags flags
;
11339 flags
= cpu_flags_and_not (cpu_arch_flags
,
11340 cpu_noarch
[j
].flags
);
11341 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
11343 if (cpu_sub_arch_name
)
11345 char *name
= cpu_sub_arch_name
;
11346 cpu_sub_arch_name
= concat (arch
,
11347 (const char *) NULL
);
11351 cpu_sub_arch_name
= xstrdup (arch
);
11352 cpu_arch_flags
= flags
;
11353 cpu_arch_isa_flags
= flags
;
11358 if (j
>= ARRAY_SIZE (cpu_noarch
))
11359 j
= ARRAY_SIZE (cpu_arch
);
11362 if (j
>= ARRAY_SIZE (cpu_arch
))
11363 as_fatal (_("invalid -march= option: `%s'"), arg
);
11367 while (next
!= NULL
);
11373 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
11374 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
11376 if (strcmp (arg
, cpu_arch
[j
].name
) == 0)
11378 cpu_arch_tune_set
= 1;
11379 cpu_arch_tune
= cpu_arch
[j
].type
;
11380 cpu_arch_tune_flags
= cpu_arch
[j
].flags
;
11384 if (j
>= ARRAY_SIZE (cpu_arch
))
11385 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
11388 case OPTION_MMNEMONIC
:
11389 if (strcasecmp (arg
, "att") == 0)
11390 intel_mnemonic
= 0;
11391 else if (strcasecmp (arg
, "intel") == 0)
11392 intel_mnemonic
= 1;
11394 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg
);
11397 case OPTION_MSYNTAX
:
11398 if (strcasecmp (arg
, "att") == 0)
11400 else if (strcasecmp (arg
, "intel") == 0)
11403 as_fatal (_("invalid -msyntax= option: `%s'"), arg
);
11406 case OPTION_MINDEX_REG
:
11407 allow_index_reg
= 1;
11410 case OPTION_MNAKED_REG
:
11411 allow_naked_reg
= 1;
11414 case OPTION_MSSE2AVX
:
11418 case OPTION_MSSE_CHECK
:
11419 if (strcasecmp (arg
, "error") == 0)
11420 sse_check
= check_error
;
11421 else if (strcasecmp (arg
, "warning") == 0)
11422 sse_check
= check_warning
;
11423 else if (strcasecmp (arg
, "none") == 0)
11424 sse_check
= check_none
;
11426 as_fatal (_("invalid -msse-check= option: `%s'"), arg
);
11429 case OPTION_MOPERAND_CHECK
:
11430 if (strcasecmp (arg
, "error") == 0)
11431 operand_check
= check_error
;
11432 else if (strcasecmp (arg
, "warning") == 0)
11433 operand_check
= check_warning
;
11434 else if (strcasecmp (arg
, "none") == 0)
11435 operand_check
= check_none
;
11437 as_fatal (_("invalid -moperand-check= option: `%s'"), arg
);
11440 case OPTION_MAVXSCALAR
:
11441 if (strcasecmp (arg
, "128") == 0)
11442 avxscalar
= vex128
;
11443 else if (strcasecmp (arg
, "256") == 0)
11444 avxscalar
= vex256
;
11446 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg
);
11449 case OPTION_MVEXWIG
:
11450 if (strcmp (arg
, "0") == 0)
11452 else if (strcmp (arg
, "1") == 0)
11455 as_fatal (_("invalid -mvexwig= option: `%s'"), arg
);
11458 case OPTION_MADD_BND_PREFIX
:
11459 add_bnd_prefix
= 1;
11462 case OPTION_MEVEXLIG
:
11463 if (strcmp (arg
, "128") == 0)
11464 evexlig
= evexl128
;
11465 else if (strcmp (arg
, "256") == 0)
11466 evexlig
= evexl256
;
11467 else if (strcmp (arg
, "512") == 0)
11468 evexlig
= evexl512
;
11470 as_fatal (_("invalid -mevexlig= option: `%s'"), arg
);
11473 case OPTION_MEVEXRCIG
:
11474 if (strcmp (arg
, "rne") == 0)
11476 else if (strcmp (arg
, "rd") == 0)
11478 else if (strcmp (arg
, "ru") == 0)
11480 else if (strcmp (arg
, "rz") == 0)
11483 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg
);
11486 case OPTION_MEVEXWIG
:
11487 if (strcmp (arg
, "0") == 0)
11489 else if (strcmp (arg
, "1") == 0)
11492 as_fatal (_("invalid -mevexwig= option: `%s'"), arg
);
11495 # if defined (TE_PE) || defined (TE_PEP)
11496 case OPTION_MBIG_OBJ
:
11501 case OPTION_MOMIT_LOCK_PREFIX
:
11502 if (strcasecmp (arg
, "yes") == 0)
11503 omit_lock_prefix
= 1;
11504 else if (strcasecmp (arg
, "no") == 0)
11505 omit_lock_prefix
= 0;
11507 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg
);
11510 case OPTION_MFENCE_AS_LOCK_ADD
:
11511 if (strcasecmp (arg
, "yes") == 0)
11513 else if (strcasecmp (arg
, "no") == 0)
11516 as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg
);
11519 case OPTION_MRELAX_RELOCATIONS
:
11520 if (strcasecmp (arg
, "yes") == 0)
11521 generate_relax_relocations
= 1;
11522 else if (strcasecmp (arg
, "no") == 0)
11523 generate_relax_relocations
= 0;
11525 as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg
);
11528 case OPTION_MAMD64
:
11532 case OPTION_MINTEL64
:
11540 /* Turn off -Os. */
11541 optimize_for_space
= 0;
11543 else if (*arg
== 's')
11545 optimize_for_space
= 1;
11546 /* Turn on all encoding optimizations. */
11547 optimize
= INT_MAX
;
11551 optimize
= atoi (arg
);
11552 /* Turn off -Os. */
11553 optimize_for_space
= 0;
11563 #define MESSAGE_TEMPLATE \
11567 output_message (FILE *stream
, char *p
, char *message
, char *start
,
11568 int *left_p
, const char *name
, int len
)
11570 int size
= sizeof (MESSAGE_TEMPLATE
);
11571 int left
= *left_p
;
11573 /* Reserve 2 spaces for ", " or ",\0" */
11576 /* Check if there is any room. */
11584 p
= mempcpy (p
, name
, len
);
11588 /* Output the current message now and start a new one. */
11591 fprintf (stream
, "%s\n", message
);
11593 left
= size
- (start
- message
) - len
- 2;
11595 gas_assert (left
>= 0);
11597 p
= mempcpy (p
, name
, len
);
11605 show_arch (FILE *stream
, int ext
, int check
)
11607 static char message
[] = MESSAGE_TEMPLATE
;
11608 char *start
= message
+ 27;
11610 int size
= sizeof (MESSAGE_TEMPLATE
);
11617 left
= size
- (start
- message
);
11618 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
11620 /* Should it be skipped? */
11621 if (cpu_arch
[j
].skip
)
11624 name
= cpu_arch
[j
].name
;
11625 len
= cpu_arch
[j
].len
;
11628 /* It is an extension. Skip if we aren't asked to show it. */
11639 /* It is an processor. Skip if we show only extension. */
11642 else if (check
&& ! cpu_arch
[j
].flags
.bitfield
.cpui386
)
11644 /* It is an impossible processor - skip. */
11648 p
= output_message (stream
, p
, message
, start
, &left
, name
, len
);
11651 /* Display disabled extensions. */
11653 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
11655 name
= cpu_noarch
[j
].name
;
11656 len
= cpu_noarch
[j
].len
;
11657 p
= output_message (stream
, p
, message
, start
, &left
, name
,
11662 fprintf (stream
, "%s\n", message
);
11666 md_show_usage (FILE *stream
)
11668 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11669 fprintf (stream
, _("\
11670 -Qy, -Qn ignored\n\
11671 -V print assembler version number\n\
11674 fprintf (stream
, _("\
11675 -n Do not optimize code alignment\n\
11676 -q quieten some warnings\n"));
11677 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11678 fprintf (stream
, _("\
11681 #if defined BFD64 && (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
11682 || defined (TE_PE) || defined (TE_PEP))
11683 fprintf (stream
, _("\
11684 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
11686 #ifdef SVR4_COMMENT_CHARS
11687 fprintf (stream
, _("\
11688 --divide do not treat `/' as a comment character\n"));
11690 fprintf (stream
, _("\
11691 --divide ignored\n"));
11693 fprintf (stream
, _("\
11694 -march=CPU[,+EXTENSION...]\n\
11695 generate code for CPU and EXTENSION, CPU is one of:\n"));
11696 show_arch (stream
, 0, 1);
11697 fprintf (stream
, _("\
11698 EXTENSION is combination of:\n"));
11699 show_arch (stream
, 1, 0);
11700 fprintf (stream
, _("\
11701 -mtune=CPU optimize for CPU, CPU is one of:\n"));
11702 show_arch (stream
, 0, 0);
11703 fprintf (stream
, _("\
11704 -msse2avx encode SSE instructions with VEX prefix\n"));
11705 fprintf (stream
, _("\
11706 -msse-check=[none|error|warning] (default: warning)\n\
11707 check SSE instructions\n"));
11708 fprintf (stream
, _("\
11709 -moperand-check=[none|error|warning] (default: warning)\n\
11710 check operand combinations for validity\n"));
11711 fprintf (stream
, _("\
11712 -mavxscalar=[128|256] (default: 128)\n\
11713 encode scalar AVX instructions with specific vector\n\
11715 fprintf (stream
, _("\
11716 -mvexwig=[0|1] (default: 0)\n\
11717 encode VEX instructions with specific VEX.W value\n\
11718 for VEX.W bit ignored instructions\n"));
11719 fprintf (stream
, _("\
11720 -mevexlig=[128|256|512] (default: 128)\n\
11721 encode scalar EVEX instructions with specific vector\n\
11723 fprintf (stream
, _("\
11724 -mevexwig=[0|1] (default: 0)\n\
11725 encode EVEX instructions with specific EVEX.W value\n\
11726 for EVEX.W bit ignored instructions\n"));
11727 fprintf (stream
, _("\
11728 -mevexrcig=[rne|rd|ru|rz] (default: rne)\n\
11729 encode EVEX instructions with specific EVEX.RC value\n\
11730 for SAE-only ignored instructions\n"));
11731 fprintf (stream
, _("\
11732 -mmnemonic=[att|intel] "));
11733 if (SYSV386_COMPAT
)
11734 fprintf (stream
, _("(default: att)\n"));
11736 fprintf (stream
, _("(default: intel)\n"));
11737 fprintf (stream
, _("\
11738 use AT&T/Intel mnemonic\n"));
11739 fprintf (stream
, _("\
11740 -msyntax=[att|intel] (default: att)\n\
11741 use AT&T/Intel syntax\n"));
11742 fprintf (stream
, _("\
11743 -mindex-reg support pseudo index registers\n"));
11744 fprintf (stream
, _("\
11745 -mnaked-reg don't require `%%' prefix for registers\n"));
11746 fprintf (stream
, _("\
11747 -madd-bnd-prefix add BND prefix for all valid branches\n"));
11748 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11749 fprintf (stream
, _("\
11750 -mshared disable branch optimization for shared code\n"));
11751 fprintf (stream
, _("\
11752 -mx86-used-note=[no|yes] "));
11753 if (DEFAULT_X86_USED_NOTE
)
11754 fprintf (stream
, _("(default: yes)\n"));
11756 fprintf (stream
, _("(default: no)\n"));
11757 fprintf (stream
, _("\
11758 generate x86 used ISA and feature properties\n"));
11760 #if defined (TE_PE) || defined (TE_PEP)
11761 fprintf (stream
, _("\
11762 -mbig-obj generate big object files\n"));
11764 fprintf (stream
, _("\
11765 -momit-lock-prefix=[no|yes] (default: no)\n\
11766 strip all lock prefixes\n"));
11767 fprintf (stream
, _("\
11768 -mfence-as-lock-add=[no|yes] (default: no)\n\
11769 encode lfence, mfence and sfence as\n\
11770 lock addl $0x0, (%%{re}sp)\n"));
11771 fprintf (stream
, _("\
11772 -mrelax-relocations=[no|yes] "));
11773 if (DEFAULT_GENERATE_X86_RELAX_RELOCATIONS
)
11774 fprintf (stream
, _("(default: yes)\n"));
11776 fprintf (stream
, _("(default: no)\n"));
11777 fprintf (stream
, _("\
11778 generate relax relocations\n"));
11779 fprintf (stream
, _("\
11780 -mamd64 accept only AMD64 ISA [default]\n"));
11781 fprintf (stream
, _("\
11782 -mintel64 accept only Intel64 ISA\n"));
11785 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
11786 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
11787 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
11789 /* Pick the target format to use. */
11792 i386_target_format (void)
11794 if (!strncmp (default_arch
, "x86_64", 6))
11796 update_code_flag (CODE_64BIT
, 1);
11797 if (default_arch
[6] == '\0')
11798 x86_elf_abi
= X86_64_ABI
;
11800 x86_elf_abi
= X86_64_X32_ABI
;
11802 else if (!strcmp (default_arch
, "i386"))
11803 update_code_flag (CODE_32BIT
, 1);
11804 else if (!strcmp (default_arch
, "iamcu"))
11806 update_code_flag (CODE_32BIT
, 1);
11807 if (cpu_arch_isa
== PROCESSOR_UNKNOWN
)
11809 static const i386_cpu_flags iamcu_flags
= CPU_IAMCU_FLAGS
;
11810 cpu_arch_name
= "iamcu";
11811 cpu_sub_arch_name
= NULL
;
11812 cpu_arch_flags
= iamcu_flags
;
11813 cpu_arch_isa
= PROCESSOR_IAMCU
;
11814 cpu_arch_isa_flags
= iamcu_flags
;
11815 if (!cpu_arch_tune_set
)
11817 cpu_arch_tune
= cpu_arch_isa
;
11818 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
11821 else if (cpu_arch_isa
!= PROCESSOR_IAMCU
)
11822 as_fatal (_("Intel MCU doesn't support `%s' architecture"),
11826 as_fatal (_("unknown architecture"));
11828 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
11829 cpu_arch_isa_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
11830 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
11831 cpu_arch_tune_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
11833 switch (OUTPUT_FLAVOR
)
11835 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
11836 case bfd_target_aout_flavour
:
11837 return AOUT_TARGET_FORMAT
;
11839 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
11840 # if defined (TE_PE) || defined (TE_PEP)
11841 case bfd_target_coff_flavour
:
11842 if (flag_code
== CODE_64BIT
)
11843 return use_big_obj
? "pe-bigobj-x86-64" : "pe-x86-64";
11846 # elif defined (TE_GO32)
11847 case bfd_target_coff_flavour
:
11848 return "coff-go32";
11850 case bfd_target_coff_flavour
:
11851 return "coff-i386";
11854 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
11855 case bfd_target_elf_flavour
:
11857 const char *format
;
11859 switch (x86_elf_abi
)
11862 format
= ELF_TARGET_FORMAT
;
11865 use_rela_relocations
= 1;
11867 format
= ELF_TARGET_FORMAT64
;
11869 case X86_64_X32_ABI
:
11870 use_rela_relocations
= 1;
11872 disallow_64bit_reloc
= 1;
11873 format
= ELF_TARGET_FORMAT32
;
11876 if (cpu_arch_isa
== PROCESSOR_L1OM
)
11878 if (x86_elf_abi
!= X86_64_ABI
)
11879 as_fatal (_("Intel L1OM is 64bit only"));
11880 return ELF_TARGET_L1OM_FORMAT
;
11882 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
11884 if (x86_elf_abi
!= X86_64_ABI
)
11885 as_fatal (_("Intel K1OM is 64bit only"));
11886 return ELF_TARGET_K1OM_FORMAT
;
11888 else if (cpu_arch_isa
== PROCESSOR_IAMCU
)
11890 if (x86_elf_abi
!= I386_ABI
)
11891 as_fatal (_("Intel MCU is 32bit only"));
11892 return ELF_TARGET_IAMCU_FORMAT
;
11898 #if defined (OBJ_MACH_O)
11899 case bfd_target_mach_o_flavour
:
11900 if (flag_code
== CODE_64BIT
)
11902 use_rela_relocations
= 1;
11904 return "mach-o-x86-64";
11907 return "mach-o-i386";
11915 #endif /* OBJ_MAYBE_ more than one */
11918 md_undefined_symbol (char *name
)
11920 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
11921 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
11922 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
11923 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
11927 if (symbol_find (name
))
11928 as_bad (_("GOT already in symbol table"));
11929 GOT_symbol
= symbol_new (name
, undefined_section
,
11930 (valueT
) 0, &zero_address_frag
);
11937 /* Round up a section size to the appropriate boundary. */
11940 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
11942 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
11943 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
11945 /* For a.out, force the section size to be aligned. If we don't do
11946 this, BFD will align it for us, but it will not write out the
11947 final bytes of the section. This may be a bug in BFD, but it is
11948 easier to fix it here since that is how the other a.out targets
11952 align
= bfd_section_alignment (segment
);
11953 size
= ((size
+ (1 << align
) - 1) & (-((valueT
) 1 << align
)));
11960 /* On the i386, PC-relative offsets are relative to the start of the
11961 next instruction. That is, the address of the offset, plus its
11962 size, since the offset is always the last part of the insn. */
11965 md_pcrel_from (fixS
*fixP
)
11967 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
11973 s_bss (int ignore ATTRIBUTE_UNUSED
)
11977 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11979 obj_elf_section_change_hook ();
11981 temp
= get_absolute_expression ();
11982 subseg_set (bss_section
, (subsegT
) temp
);
11983 demand_empty_rest_of_line ();
11989 i386_validate_fix (fixS
*fixp
)
11991 if (fixp
->fx_subsy
)
11993 if (fixp
->fx_subsy
== GOT_symbol
)
11995 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
11999 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12000 if (fixp
->fx_tcbit2
)
12001 fixp
->fx_r_type
= (fixp
->fx_tcbit
12002 ? BFD_RELOC_X86_64_REX_GOTPCRELX
12003 : BFD_RELOC_X86_64_GOTPCRELX
);
12006 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
12011 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
12013 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
12015 fixp
->fx_subsy
= 0;
12018 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12019 else if (!object_64bit
)
12021 if (fixp
->fx_r_type
== BFD_RELOC_386_GOT32
12022 && fixp
->fx_tcbit2
)
12023 fixp
->fx_r_type
= BFD_RELOC_386_GOT32X
;
12029 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
12032 bfd_reloc_code_real_type code
;
12034 switch (fixp
->fx_r_type
)
12036 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12037 case BFD_RELOC_SIZE32
:
12038 case BFD_RELOC_SIZE64
:
12039 if (S_IS_DEFINED (fixp
->fx_addsy
)
12040 && !S_IS_EXTERNAL (fixp
->fx_addsy
))
12042 /* Resolve size relocation against local symbol to size of
12043 the symbol plus addend. */
12044 valueT value
= S_GET_SIZE (fixp
->fx_addsy
) + fixp
->fx_offset
;
12045 if (fixp
->fx_r_type
== BFD_RELOC_SIZE32
12046 && !fits_in_unsigned_long (value
))
12047 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
12048 _("symbol size computation overflow"));
12049 fixp
->fx_addsy
= NULL
;
12050 fixp
->fx_subsy
= NULL
;
12051 md_apply_fix (fixp
, (valueT
*) &value
, NULL
);
12055 /* Fall through. */
12057 case BFD_RELOC_X86_64_PLT32
:
12058 case BFD_RELOC_X86_64_GOT32
:
12059 case BFD_RELOC_X86_64_GOTPCREL
:
12060 case BFD_RELOC_X86_64_GOTPCRELX
:
12061 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
12062 case BFD_RELOC_386_PLT32
:
12063 case BFD_RELOC_386_GOT32
:
12064 case BFD_RELOC_386_GOT32X
:
12065 case BFD_RELOC_386_GOTOFF
:
12066 case BFD_RELOC_386_GOTPC
:
12067 case BFD_RELOC_386_TLS_GD
:
12068 case BFD_RELOC_386_TLS_LDM
:
12069 case BFD_RELOC_386_TLS_LDO_32
:
12070 case BFD_RELOC_386_TLS_IE_32
:
12071 case BFD_RELOC_386_TLS_IE
:
12072 case BFD_RELOC_386_TLS_GOTIE
:
12073 case BFD_RELOC_386_TLS_LE_32
:
12074 case BFD_RELOC_386_TLS_LE
:
12075 case BFD_RELOC_386_TLS_GOTDESC
:
12076 case BFD_RELOC_386_TLS_DESC_CALL
:
12077 case BFD_RELOC_X86_64_TLSGD
:
12078 case BFD_RELOC_X86_64_TLSLD
:
12079 case BFD_RELOC_X86_64_DTPOFF32
:
12080 case BFD_RELOC_X86_64_DTPOFF64
:
12081 case BFD_RELOC_X86_64_GOTTPOFF
:
12082 case BFD_RELOC_X86_64_TPOFF32
:
12083 case BFD_RELOC_X86_64_TPOFF64
:
12084 case BFD_RELOC_X86_64_GOTOFF64
:
12085 case BFD_RELOC_X86_64_GOTPC32
:
12086 case BFD_RELOC_X86_64_GOT64
:
12087 case BFD_RELOC_X86_64_GOTPCREL64
:
12088 case BFD_RELOC_X86_64_GOTPC64
:
12089 case BFD_RELOC_X86_64_GOTPLT64
:
12090 case BFD_RELOC_X86_64_PLTOFF64
:
12091 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
12092 case BFD_RELOC_X86_64_TLSDESC_CALL
:
12093 case BFD_RELOC_RVA
:
12094 case BFD_RELOC_VTABLE_ENTRY
:
12095 case BFD_RELOC_VTABLE_INHERIT
:
12097 case BFD_RELOC_32_SECREL
:
12099 code
= fixp
->fx_r_type
;
12101 case BFD_RELOC_X86_64_32S
:
12102 if (!fixp
->fx_pcrel
)
12104 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
12105 code
= fixp
->fx_r_type
;
12108 /* Fall through. */
12110 if (fixp
->fx_pcrel
)
12112 switch (fixp
->fx_size
)
12115 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
12116 _("can not do %d byte pc-relative relocation"),
12118 code
= BFD_RELOC_32_PCREL
;
12120 case 1: code
= BFD_RELOC_8_PCREL
; break;
12121 case 2: code
= BFD_RELOC_16_PCREL
; break;
12122 case 4: code
= BFD_RELOC_32_PCREL
; break;
12124 case 8: code
= BFD_RELOC_64_PCREL
; break;
12130 switch (fixp
->fx_size
)
12133 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
12134 _("can not do %d byte relocation"),
12136 code
= BFD_RELOC_32
;
12138 case 1: code
= BFD_RELOC_8
; break;
12139 case 2: code
= BFD_RELOC_16
; break;
12140 case 4: code
= BFD_RELOC_32
; break;
12142 case 8: code
= BFD_RELOC_64
; break;
12149 if ((code
== BFD_RELOC_32
12150 || code
== BFD_RELOC_32_PCREL
12151 || code
== BFD_RELOC_X86_64_32S
)
12153 && fixp
->fx_addsy
== GOT_symbol
)
12156 code
= BFD_RELOC_386_GOTPC
;
12158 code
= BFD_RELOC_X86_64_GOTPC32
;
12160 if ((code
== BFD_RELOC_64
|| code
== BFD_RELOC_64_PCREL
)
12162 && fixp
->fx_addsy
== GOT_symbol
)
12164 code
= BFD_RELOC_X86_64_GOTPC64
;
12167 rel
= XNEW (arelent
);
12168 rel
->sym_ptr_ptr
= XNEW (asymbol
*);
12169 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
12171 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
12173 if (!use_rela_relocations
)
12175 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
12176 vtable entry to be used in the relocation's section offset. */
12177 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
12178 rel
->address
= fixp
->fx_offset
;
12179 #if defined (OBJ_COFF) && defined (TE_PE)
12180 else if (fixp
->fx_addsy
&& S_IS_WEAK (fixp
->fx_addsy
))
12181 rel
->addend
= fixp
->fx_addnumber
- (S_GET_VALUE (fixp
->fx_addsy
) * 2);
12186 /* Use the rela in 64bit mode. */
12189 if (disallow_64bit_reloc
)
12192 case BFD_RELOC_X86_64_DTPOFF64
:
12193 case BFD_RELOC_X86_64_TPOFF64
:
12194 case BFD_RELOC_64_PCREL
:
12195 case BFD_RELOC_X86_64_GOTOFF64
:
12196 case BFD_RELOC_X86_64_GOT64
:
12197 case BFD_RELOC_X86_64_GOTPCREL64
:
12198 case BFD_RELOC_X86_64_GOTPC64
:
12199 case BFD_RELOC_X86_64_GOTPLT64
:
12200 case BFD_RELOC_X86_64_PLTOFF64
:
12201 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
12202 _("cannot represent relocation type %s in x32 mode"),
12203 bfd_get_reloc_code_name (code
));
12209 if (!fixp
->fx_pcrel
)
12210 rel
->addend
= fixp
->fx_offset
;
12214 case BFD_RELOC_X86_64_PLT32
:
12215 case BFD_RELOC_X86_64_GOT32
:
12216 case BFD_RELOC_X86_64_GOTPCREL
:
12217 case BFD_RELOC_X86_64_GOTPCRELX
:
12218 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
12219 case BFD_RELOC_X86_64_TLSGD
:
12220 case BFD_RELOC_X86_64_TLSLD
:
12221 case BFD_RELOC_X86_64_GOTTPOFF
:
12222 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
12223 case BFD_RELOC_X86_64_TLSDESC_CALL
:
12224 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
12227 rel
->addend
= (section
->vma
12229 + fixp
->fx_addnumber
12230 + md_pcrel_from (fixp
));
12235 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
12236 if (rel
->howto
== NULL
)
12238 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
12239 _("cannot represent relocation type %s"),
12240 bfd_get_reloc_code_name (code
));
12241 /* Set howto to a garbage value so that we can keep going. */
12242 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
12243 gas_assert (rel
->howto
!= NULL
);
12249 #include "tc-i386-intel.c"
12252 tc_x86_parse_to_dw2regnum (expressionS
*exp
)
12254 int saved_naked_reg
;
12255 char saved_register_dot
;
12257 saved_naked_reg
= allow_naked_reg
;
12258 allow_naked_reg
= 1;
12259 saved_register_dot
= register_chars
['.'];
12260 register_chars
['.'] = '.';
12261 allow_pseudo_reg
= 1;
12262 expression_and_evaluate (exp
);
12263 allow_pseudo_reg
= 0;
12264 register_chars
['.'] = saved_register_dot
;
12265 allow_naked_reg
= saved_naked_reg
;
12267 if (exp
->X_op
== O_register
&& exp
->X_add_number
>= 0)
12269 if ((addressT
) exp
->X_add_number
< i386_regtab_size
)
12271 exp
->X_op
= O_constant
;
12272 exp
->X_add_number
= i386_regtab
[exp
->X_add_number
]
12273 .dw2_regnum
[flag_code
>> 1];
12276 exp
->X_op
= O_illegal
;
12281 tc_x86_frame_initial_instructions (void)
12283 static unsigned int sp_regno
[2];
12285 if (!sp_regno
[flag_code
>> 1])
12287 char *saved_input
= input_line_pointer
;
12288 char sp
[][4] = {"esp", "rsp"};
12291 input_line_pointer
= sp
[flag_code
>> 1];
12292 tc_x86_parse_to_dw2regnum (&exp
);
12293 gas_assert (exp
.X_op
== O_constant
);
12294 sp_regno
[flag_code
>> 1] = exp
.X_add_number
;
12295 input_line_pointer
= saved_input
;
12298 cfi_add_CFA_def_cfa (sp_regno
[flag_code
>> 1], -x86_cie_data_alignment
);
12299 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
12303 x86_dwarf2_addr_size (void)
12305 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
12306 if (x86_elf_abi
== X86_64_X32_ABI
)
12309 return bfd_arch_bits_per_address (stdoutput
) / 8;
12313 i386_elf_section_type (const char *str
, size_t len
)
12315 if (flag_code
== CODE_64BIT
12316 && len
== sizeof ("unwind") - 1
12317 && strncmp (str
, "unwind", 6) == 0)
12318 return SHT_X86_64_UNWIND
;
12325 i386_solaris_fix_up_eh_frame (segT sec
)
12327 if (flag_code
== CODE_64BIT
)
12328 elf_section_type (sec
) = SHT_X86_64_UNWIND
;
12334 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
12338 exp
.X_op
= O_secrel
;
12339 exp
.X_add_symbol
= symbol
;
12340 exp
.X_add_number
= 0;
12341 emit_expr (&exp
, size
);
12345 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12346 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
12349 x86_64_section_letter (int letter
, const char **ptr_msg
)
12351 if (flag_code
== CODE_64BIT
)
12354 return SHF_X86_64_LARGE
;
12356 *ptr_msg
= _("bad .section directive: want a,l,w,x,M,S,G,T in string");
12359 *ptr_msg
= _("bad .section directive: want a,w,x,M,S,G,T in string");
12364 x86_64_section_word (char *str
, size_t len
)
12366 if (len
== 5 && flag_code
== CODE_64BIT
&& CONST_STRNEQ (str
, "large"))
12367 return SHF_X86_64_LARGE
;
12373 handle_large_common (int small ATTRIBUTE_UNUSED
)
12375 if (flag_code
!= CODE_64BIT
)
12377 s_comm_internal (0, elf_common_parse
);
12378 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
12382 static segT lbss_section
;
12383 asection
*saved_com_section_ptr
= elf_com_section_ptr
;
12384 asection
*saved_bss_section
= bss_section
;
12386 if (lbss_section
== NULL
)
12388 flagword applicable
;
12389 segT seg
= now_seg
;
12390 subsegT subseg
= now_subseg
;
12392 /* The .lbss section is for local .largecomm symbols. */
12393 lbss_section
= subseg_new (".lbss", 0);
12394 applicable
= bfd_applicable_section_flags (stdoutput
);
12395 bfd_set_section_flags (lbss_section
, applicable
& SEC_ALLOC
);
12396 seg_info (lbss_section
)->bss
= 1;
12398 subseg_set (seg
, subseg
);
12401 elf_com_section_ptr
= &_bfd_elf_large_com_section
;
12402 bss_section
= lbss_section
;
12404 s_comm_internal (0, elf_common_parse
);
12406 elf_com_section_ptr
= saved_com_section_ptr
;
12407 bss_section
= saved_bss_section
;
12410 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */