1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright (C) 1989-2020 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 /* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
23 x86_64 support by Jan Hubicka (jh@suse.cz)
24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
29 #include "safe-ctype.h"
31 #include "dwarf2dbg.h"
32 #include "dw2gencfi.h"
33 #include "elf/x86-64.h"
34 #include "opcodes/i386-init.h"
39 #ifdef HAVE_SYS_PARAM_H
40 #include <sys/param.h>
43 #define INT_MAX (int) (((unsigned) (-1)) >> 1)
47 #ifndef INFER_ADDR_PREFIX
48 #define INFER_ADDR_PREFIX 1
52 #define DEFAULT_ARCH "i386"
57 #define INLINE __inline__
63 /* Prefixes will be emitted in the order defined below.
64 WAIT_PREFIX must be the first prefix since FWAIT is really is an
65 instruction, and so must come before any prefixes.
66 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
67 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
73 #define HLE_PREFIX REP_PREFIX
74 #define BND_PREFIX REP_PREFIX
76 #define REX_PREFIX 6 /* must come last. */
77 #define MAX_PREFIXES 7 /* max prefixes per opcode */
79 /* we define the syntax here (modulo base,index,scale syntax) */
80 #define REGISTER_PREFIX '%'
81 #define IMMEDIATE_PREFIX '$'
82 #define ABSOLUTE_PREFIX '*'
84 /* these are the instruction mnemonic suffixes in AT&T syntax or
85 memory operand size in Intel syntax. */
86 #define WORD_MNEM_SUFFIX 'w'
87 #define BYTE_MNEM_SUFFIX 'b'
88 #define SHORT_MNEM_SUFFIX 's'
89 #define LONG_MNEM_SUFFIX 'l'
90 #define QWORD_MNEM_SUFFIX 'q'
91 /* Intel Syntax. Use a non-ascii letter since since it never appears
93 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
95 #define END_OF_INSN '\0'
97 /* This matches the C -> StaticRounding alias in the opcode table. */
98 #define commutative staticrounding
101 'templates' is for grouping together 'template' structures for opcodes
102 of the same name. This is only used for storing the insns in the grand
103 ole hash table of insns.
104 The templates themselves start at START and range up to (but not including)
109 const insn_template
*start
;
110 const insn_template
*end
;
114 /* 386 operand encoding bytes: see 386 book for details of this. */
117 unsigned int regmem
; /* codes register or memory operand */
118 unsigned int reg
; /* codes register operand (or extended opcode) */
119 unsigned int mode
; /* how to interpret regmem & reg */
123 /* x86-64 extension prefix. */
124 typedef int rex_byte
;
126 /* 386 opcode byte to code indirect addressing. */
135 /* x86 arch names, types and features */
138 const char *name
; /* arch name */
139 unsigned int len
; /* arch string length */
140 enum processor_type type
; /* arch type */
141 i386_cpu_flags flags
; /* cpu feature flags */
142 unsigned int skip
; /* show_arch should skip this. */
146 /* Used to turn off indicated flags. */
149 const char *name
; /* arch name */
150 unsigned int len
; /* arch string length */
151 i386_cpu_flags flags
; /* cpu feature flags */
155 static void update_code_flag (int, int);
156 static void set_code_flag (int);
157 static void set_16bit_gcc_code_flag (int);
158 static void set_intel_syntax (int);
159 static void set_intel_mnemonic (int);
160 static void set_allow_index_reg (int);
161 static void set_check (int);
162 static void set_cpu_arch (int);
164 static void pe_directive_secrel (int);
166 static void signed_cons (int);
167 static char *output_invalid (int c
);
168 static int i386_finalize_immediate (segT
, expressionS
*, i386_operand_type
,
170 static int i386_finalize_displacement (segT
, expressionS
*, i386_operand_type
,
172 static int i386_att_operand (char *);
173 static int i386_intel_operand (char *, int);
174 static int i386_intel_simplify (expressionS
*);
175 static int i386_intel_parse_name (const char *, expressionS
*);
176 static const reg_entry
*parse_register (char *, char **);
177 static char *parse_insn (char *, char *);
178 static char *parse_operands (char *, const char *);
179 static void swap_operands (void);
180 static void swap_2_operands (int, int);
181 static enum flag_code
i386_addressing_mode (void);
182 static void optimize_imm (void);
183 static void optimize_disp (void);
184 static const insn_template
*match_template (char);
185 static int check_string (void);
186 static int process_suffix (void);
187 static int check_byte_reg (void);
188 static int check_long_reg (void);
189 static int check_qword_reg (void);
190 static int check_word_reg (void);
191 static int finalize_imm (void);
192 static int process_operands (void);
193 static const seg_entry
*build_modrm_byte (void);
194 static void output_insn (void);
195 static void output_imm (fragS
*, offsetT
);
196 static void output_disp (fragS
*, offsetT
);
198 static void s_bss (int);
200 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
201 static void handle_large_common (int small ATTRIBUTE_UNUSED
);
203 /* GNU_PROPERTY_X86_ISA_1_USED. */
204 static unsigned int x86_isa_1_used
;
205 /* GNU_PROPERTY_X86_FEATURE_2_USED. */
206 static unsigned int x86_feature_2_used
;
207 /* Generate x86 used ISA and feature properties. */
208 static unsigned int x86_used_note
= DEFAULT_X86_USED_NOTE
;
211 static const char *default_arch
= DEFAULT_ARCH
;
213 /* This struct describes rounding control and SAE in the instruction. */
227 static struct RC_Operation rc_op
;
229 /* The struct describes masking, applied to OPERAND in the instruction.
230 MASK is a pointer to the corresponding mask register. ZEROING tells
231 whether merging or zeroing mask is used. */
232 struct Mask_Operation
234 const reg_entry
*mask
;
235 unsigned int zeroing
;
236 /* The operand where this operation is associated. */
240 static struct Mask_Operation mask_op
;
242 /* The struct describes broadcasting, applied to OPERAND. FACTOR is
244 struct Broadcast_Operation
246 /* Type of broadcast: {1to2}, {1to4}, {1to8}, or {1to16}. */
249 /* Index of broadcasted operand. */
252 /* Number of bytes to broadcast. */
256 static struct Broadcast_Operation broadcast_op
;
261 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
262 unsigned char bytes
[4];
264 /* Destination or source register specifier. */
265 const reg_entry
*register_specifier
;
268 /* 'md_assemble ()' gathers together information and puts it into a
275 const reg_entry
*regs
;
280 operand_size_mismatch
,
281 operand_type_mismatch
,
282 register_type_mismatch
,
283 number_of_operands_mismatch
,
284 invalid_instruction_suffix
,
286 unsupported_with_intel_mnemonic
,
289 invalid_vsib_address
,
290 invalid_vector_register_set
,
291 unsupported_vector_index_register
,
292 unsupported_broadcast
,
295 mask_not_on_destination
,
298 rc_sae_operand_not_last_imm
,
299 invalid_register_operand
,
304 /* TM holds the template for the insn were currently assembling. */
307 /* SUFFIX holds the instruction size suffix for byte, word, dword
308 or qword, if given. */
311 /* OPERANDS gives the number of given operands. */
312 unsigned int operands
;
314 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
315 of given register, displacement, memory operands and immediate
317 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
319 /* TYPES [i] is the type (see above #defines) which tells us how to
320 use OP[i] for the corresponding operand. */
321 i386_operand_type types
[MAX_OPERANDS
];
323 /* Displacement expression, immediate expression, or register for each
325 union i386_op op
[MAX_OPERANDS
];
327 /* Flags for operands. */
328 unsigned int flags
[MAX_OPERANDS
];
329 #define Operand_PCrel 1
330 #define Operand_Mem 2
332 /* Relocation type for operand */
333 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
335 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
336 the base index byte below. */
337 const reg_entry
*base_reg
;
338 const reg_entry
*index_reg
;
339 unsigned int log2_scale_factor
;
341 /* SEG gives the seg_entries of this insn. They are zero unless
342 explicit segment overrides are given. */
343 const seg_entry
*seg
[2];
345 /* Copied first memory operand string, for re-checking. */
348 /* PREFIX holds all the given prefix opcodes (usually null).
349 PREFIXES is the number of prefix opcodes. */
350 unsigned int prefixes
;
351 unsigned char prefix
[MAX_PREFIXES
];
353 /* Register is in low 3 bits of opcode. */
354 bfd_boolean short_form
;
356 /* The operand to a branch insn indicates an absolute branch. */
357 bfd_boolean jumpabsolute
;
359 /* Has MMX register operands. */
360 bfd_boolean has_regmmx
;
362 /* Has XMM register operands. */
363 bfd_boolean has_regxmm
;
365 /* Has YMM register operands. */
366 bfd_boolean has_regymm
;
368 /* Has ZMM register operands. */
369 bfd_boolean has_regzmm
;
371 /* Has GOTPC or TLS relocation. */
372 bfd_boolean has_gotpc_tls_reloc
;
374 /* RM and SIB are the modrm byte and the sib byte where the
375 addressing modes of this insn are encoded. */
382 /* Masking attributes. */
383 struct Mask_Operation
*mask
;
385 /* Rounding control and SAE attributes. */
386 struct RC_Operation
*rounding
;
388 /* Broadcasting attributes. */
389 struct Broadcast_Operation
*broadcast
;
391 /* Compressed disp8*N attribute. */
392 unsigned int memshift
;
394 /* Prefer load or store in encoding. */
397 dir_encoding_default
= 0,
403 /* Prefer 8bit or 32bit displacement in encoding. */
406 disp_encoding_default
= 0,
411 /* Prefer the REX byte in encoding. */
412 bfd_boolean rex_encoding
;
414 /* Disable instruction size optimization. */
415 bfd_boolean no_optimize
;
417 /* How to encode vector instructions. */
420 vex_encoding_default
= 0,
427 const char *rep_prefix
;
430 const char *hle_prefix
;
432 /* Have BND prefix. */
433 const char *bnd_prefix
;
435 /* Have NOTRACK prefix. */
436 const char *notrack_prefix
;
439 enum i386_error error
;
442 typedef struct _i386_insn i386_insn
;
444 /* Link RC type with corresponding string, that'll be looked for in
453 static const struct RC_name RC_NamesTable
[] =
455 { rne
, STRING_COMMA_LEN ("rn-sae") },
456 { rd
, STRING_COMMA_LEN ("rd-sae") },
457 { ru
, STRING_COMMA_LEN ("ru-sae") },
458 { rz
, STRING_COMMA_LEN ("rz-sae") },
459 { saeonly
, STRING_COMMA_LEN ("sae") },
462 /* List of chars besides those in app.c:symbol_chars that can start an
463 operand. Used to prevent the scrubber eating vital white-space. */
464 const char extra_symbol_chars
[] = "*%-([{}"
473 #if (defined (TE_I386AIX) \
474 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
475 && !defined (TE_GNU) \
476 && !defined (TE_LINUX) \
477 && !defined (TE_NACL) \
478 && !defined (TE_FreeBSD) \
479 && !defined (TE_DragonFly) \
480 && !defined (TE_NetBSD)))
481 /* This array holds the chars that always start a comment. If the
482 pre-processor is disabled, these aren't very useful. The option
483 --divide will remove '/' from this list. */
484 const char *i386_comment_chars
= "#/";
485 #define SVR4_COMMENT_CHARS 1
486 #define PREFIX_SEPARATOR '\\'
489 const char *i386_comment_chars
= "#";
490 #define PREFIX_SEPARATOR '/'
493 /* This array holds the chars that only start a comment at the beginning of
494 a line. If the line seems to have the form '# 123 filename'
495 .line and .file directives will appear in the pre-processed output.
496 Note that input_file.c hand checks for '#' at the beginning of the
497 first line of the input file. This is because the compiler outputs
498 #NO_APP at the beginning of its output.
499 Also note that comments started like this one will always work if
500 '/' isn't otherwise defined. */
501 const char line_comment_chars
[] = "#/";
503 const char line_separator_chars
[] = ";";
505 /* Chars that can be used to separate mant from exp in floating point
507 const char EXP_CHARS
[] = "eE";
509 /* Chars that mean this number is a floating point constant
512 const char FLT_CHARS
[] = "fFdDxX";
514 /* Tables for lexical analysis. */
515 static char mnemonic_chars
[256];
516 static char register_chars
[256];
517 static char operand_chars
[256];
518 static char identifier_chars
[256];
519 static char digit_chars
[256];
521 /* Lexical macros. */
522 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
523 #define is_operand_char(x) (operand_chars[(unsigned char) x])
524 #define is_register_char(x) (register_chars[(unsigned char) x])
525 #define is_space_char(x) ((x) == ' ')
526 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
527 #define is_digit_char(x) (digit_chars[(unsigned char) x])
529 /* All non-digit non-letter characters that may occur in an operand. */
530 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
532 /* md_assemble() always leaves the strings it's passed unaltered. To
533 effect this we maintain a stack of saved characters that we've smashed
534 with '\0's (indicating end of strings for various sub-fields of the
535 assembler instruction). */
536 static char save_stack
[32];
537 static char *save_stack_p
;
538 #define END_STRING_AND_SAVE(s) \
539 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
540 #define RESTORE_END_STRING(s) \
541 do { *(s) = *--save_stack_p; } while (0)
543 /* The instruction we're assembling. */
546 /* Possible templates for current insn. */
547 static const templates
*current_templates
;
549 /* Per instruction expressionS buffers: max displacements & immediates. */
550 static expressionS disp_expressions
[MAX_MEMORY_OPERANDS
];
551 static expressionS im_expressions
[MAX_IMMEDIATE_OPERANDS
];
553 /* Current operand we are working on. */
554 static int this_operand
= -1;
556 /* We support four different modes. FLAG_CODE variable is used to distinguish
564 static enum flag_code flag_code
;
565 static unsigned int object_64bit
;
566 static unsigned int disallow_64bit_reloc
;
567 static int use_rela_relocations
= 0;
568 /* __tls_get_addr/___tls_get_addr symbol for TLS. */
569 static const char *tls_get_addr
;
571 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
572 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
573 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
575 /* The ELF ABI to use. */
583 static enum x86_elf_abi x86_elf_abi
= I386_ABI
;
586 #if defined (TE_PE) || defined (TE_PEP)
587 /* Use big object file format. */
588 static int use_big_obj
= 0;
591 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
592 /* 1 if generating code for a shared library. */
593 static int shared
= 0;
596 /* 1 for intel syntax,
598 static int intel_syntax
= 0;
600 static enum x86_64_isa
602 amd64
= 1, /* AMD64 ISA. */
603 intel64
/* Intel64 ISA. */
606 /* 1 for intel mnemonic,
607 0 if att mnemonic. */
608 static int intel_mnemonic
= !SYSV386_COMPAT
;
610 /* 1 if pseudo registers are permitted. */
611 static int allow_pseudo_reg
= 0;
613 /* 1 if register prefix % not required. */
614 static int allow_naked_reg
= 0;
616 /* 1 if the assembler should add BND prefix for all control-transferring
617 instructions supporting it, even if this prefix wasn't specified
619 static int add_bnd_prefix
= 0;
621 /* 1 if pseudo index register, eiz/riz, is allowed . */
622 static int allow_index_reg
= 0;
624 /* 1 if the assembler should ignore LOCK prefix, even if it was
625 specified explicitly. */
626 static int omit_lock_prefix
= 0;
628 /* 1 if the assembler should encode lfence, mfence, and sfence as
629 "lock addl $0, (%{re}sp)". */
630 static int avoid_fence
= 0;
632 /* Type of the previous instruction. */
647 /* 1 if the assembler should generate relax relocations. */
649 static int generate_relax_relocations
650 = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS
;
652 static enum check_kind
658 sse_check
, operand_check
= check_warning
;
660 /* Non-zero if branches should be aligned within power of 2 boundary. */
661 static int align_branch_power
= 0;
663 /* Types of branches to align. */
664 enum align_branch_kind
666 align_branch_none
= 0,
667 align_branch_jcc
= 1,
668 align_branch_fused
= 2,
669 align_branch_jmp
= 3,
670 align_branch_call
= 4,
671 align_branch_indirect
= 5,
675 /* Type bits of branches to align. */
676 enum align_branch_bit
678 align_branch_jcc_bit
= 1 << align_branch_jcc
,
679 align_branch_fused_bit
= 1 << align_branch_fused
,
680 align_branch_jmp_bit
= 1 << align_branch_jmp
,
681 align_branch_call_bit
= 1 << align_branch_call
,
682 align_branch_indirect_bit
= 1 << align_branch_indirect
,
683 align_branch_ret_bit
= 1 << align_branch_ret
686 static unsigned int align_branch
= (align_branch_jcc_bit
687 | align_branch_fused_bit
688 | align_branch_jmp_bit
);
690 /* The maximum padding size for fused jcc. CMP like instruction can
691 be 9 bytes and jcc can be 6 bytes. Leave room just in case for
693 #define MAX_FUSED_JCC_PADDING_SIZE 20
695 /* The maximum number of prefixes added for an instruction. */
696 static unsigned int align_branch_prefix_size
= 5;
699 1. Clear the REX_W bit with register operand if possible.
700 2. Above plus use 128bit vector instruction to clear the full vector
703 static int optimize
= 0;
706 1. Clear the REX_W bit with register operand if possible.
707 2. Above plus use 128bit vector instruction to clear the full vector
709 3. Above plus optimize "test{q,l,w} $imm8,%r{64,32,16}" to
712 static int optimize_for_space
= 0;
714 /* Register prefix used for error message. */
715 static const char *register_prefix
= "%";
717 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
718 leave, push, and pop instructions so that gcc has the same stack
719 frame as in 32 bit mode. */
720 static char stackop_size
= '\0';
722 /* Non-zero to optimize code alignment. */
723 int optimize_align_code
= 1;
725 /* Non-zero to quieten some warnings. */
726 static int quiet_warnings
= 0;
729 static const char *cpu_arch_name
= NULL
;
730 static char *cpu_sub_arch_name
= NULL
;
732 /* CPU feature flags. */
733 static i386_cpu_flags cpu_arch_flags
= CPU_UNKNOWN_FLAGS
;
735 /* If we have selected a cpu we are generating instructions for. */
736 static int cpu_arch_tune_set
= 0;
738 /* Cpu we are generating instructions for. */
739 enum processor_type cpu_arch_tune
= PROCESSOR_UNKNOWN
;
741 /* CPU feature flags of cpu we are generating instructions for. */
742 static i386_cpu_flags cpu_arch_tune_flags
;
744 /* CPU instruction set architecture used. */
745 enum processor_type cpu_arch_isa
= PROCESSOR_UNKNOWN
;
747 /* CPU feature flags of instruction set architecture used. */
748 i386_cpu_flags cpu_arch_isa_flags
;
750 /* If set, conditional jumps are not automatically promoted to handle
751 larger than a byte offset. */
752 static unsigned int no_cond_jump_promotion
= 0;
754 /* Encode SSE instructions with VEX prefix. */
755 static unsigned int sse2avx
;
757 /* Encode scalar AVX instructions with specific vector length. */
764 /* Encode VEX WIG instructions with specific vex.w. */
771 /* Encode scalar EVEX LIG instructions with specific vector length. */
779 /* Encode EVEX WIG instructions with specific evex.w. */
786 /* Value to encode in EVEX RC bits, for SAE-only instructions. */
787 static enum rc_type evexrcig
= rne
;
789 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
790 static symbolS
*GOT_symbol
;
792 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
793 unsigned int x86_dwarf2_return_column
;
795 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
796 int x86_cie_data_alignment
;
798 /* Interface to relax_segment.
799 There are 3 major relax states for 386 jump insns because the
800 different types of jumps add different sizes to frags when we're
801 figuring out what sort of jump to choose to reach a given label.
803 BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING are used to align
804 branches which are handled by md_estimate_size_before_relax() and
805 i386_generic_table_relax_frag(). */
808 #define UNCOND_JUMP 0
810 #define COND_JUMP86 2
811 #define BRANCH_PADDING 3
812 #define BRANCH_PREFIX 4
813 #define FUSED_JCC_PADDING 5
818 #define SMALL16 (SMALL | CODE16)
820 #define BIG16 (BIG | CODE16)
824 #define INLINE __inline__
830 #define ENCODE_RELAX_STATE(type, size) \
831 ((relax_substateT) (((type) << 2) | (size)))
832 #define TYPE_FROM_RELAX_STATE(s) \
834 #define DISP_SIZE_FROM_RELAX_STATE(s) \
835 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
837 /* This table is used by relax_frag to promote short jumps to long
838 ones where necessary. SMALL (short) jumps may be promoted to BIG
839 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
840 don't allow a short jump in a 32 bit code segment to be promoted to
841 a 16 bit offset jump because it's slower (requires data size
842 prefix), and doesn't work, unless the destination is in the bottom
843 64k of the code segment (The top 16 bits of eip are zeroed). */
845 const relax_typeS md_relax_table
[] =
848 1) most positive reach of this state,
849 2) most negative reach of this state,
850 3) how many bytes this mode will have in the variable part of the frag
851 4) which index into the table to try if we can't fit into this one. */
853 /* UNCOND_JUMP states. */
854 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
855 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
856 /* dword jmp adds 4 bytes to frag:
857 0 extra opcode bytes, 4 displacement bytes. */
859 /* word jmp adds 2 byte2 to frag:
860 0 extra opcode bytes, 2 displacement bytes. */
863 /* COND_JUMP states. */
864 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
865 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
866 /* dword conditionals adds 5 bytes to frag:
867 1 extra opcode byte, 4 displacement bytes. */
869 /* word conditionals add 3 bytes to frag:
870 1 extra opcode byte, 2 displacement bytes. */
873 /* COND_JUMP86 states. */
874 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
875 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
876 /* dword conditionals adds 5 bytes to frag:
877 1 extra opcode byte, 4 displacement bytes. */
879 /* word conditionals add 4 bytes to frag:
880 1 displacement byte and a 3 byte long branch insn. */
884 static const arch_entry cpu_arch
[] =
886 /* Do not replace the first two entries - i386_target_format()
887 relies on them being there in this order. */
888 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32
,
889 CPU_GENERIC32_FLAGS
, 0 },
890 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64
,
891 CPU_GENERIC64_FLAGS
, 0 },
892 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN
,
894 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN
,
896 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN
,
898 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386
,
900 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486
,
902 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM
,
904 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO
,
906 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM
,
908 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO
,
909 CPU_PENTIUMPRO_FLAGS
, 0 },
910 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO
,
912 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO
,
914 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4
,
916 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA
,
918 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA
,
919 CPU_NOCONA_FLAGS
, 0 },
920 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE
,
922 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE
,
924 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2
,
925 CPU_CORE2_FLAGS
, 1 },
926 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2
,
927 CPU_CORE2_FLAGS
, 0 },
928 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7
,
929 CPU_COREI7_FLAGS
, 0 },
930 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM
,
932 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM
,
934 { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU
,
935 CPU_IAMCU_FLAGS
, 0 },
936 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6
,
938 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6
,
940 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON
,
941 CPU_ATHLON_FLAGS
, 0 },
942 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8
,
944 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8
,
946 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8
,
948 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10
,
949 CPU_AMDFAM10_FLAGS
, 0 },
950 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD
,
951 CPU_BDVER1_FLAGS
, 0 },
952 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD
,
953 CPU_BDVER2_FLAGS
, 0 },
954 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD
,
955 CPU_BDVER3_FLAGS
, 0 },
956 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD
,
957 CPU_BDVER4_FLAGS
, 0 },
958 { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER
,
959 CPU_ZNVER1_FLAGS
, 0 },
960 { STRING_COMMA_LEN ("znver2"), PROCESSOR_ZNVER
,
961 CPU_ZNVER2_FLAGS
, 0 },
962 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT
,
963 CPU_BTVER1_FLAGS
, 0 },
964 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT
,
965 CPU_BTVER2_FLAGS
, 0 },
966 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN
,
968 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN
,
970 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN
,
972 { STRING_COMMA_LEN (".687"), PROCESSOR_UNKNOWN
,
974 { STRING_COMMA_LEN (".cmov"), PROCESSOR_UNKNOWN
,
976 { STRING_COMMA_LEN (".fxsr"), PROCESSOR_UNKNOWN
,
978 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN
,
980 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN
,
982 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN
,
984 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN
,
986 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN
,
987 CPU_SSSE3_FLAGS
, 0 },
988 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN
,
989 CPU_SSE4_1_FLAGS
, 0 },
990 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN
,
991 CPU_SSE4_2_FLAGS
, 0 },
992 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN
,
993 CPU_SSE4_2_FLAGS
, 0 },
994 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN
,
996 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN
,
998 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN
,
999 CPU_AVX512F_FLAGS
, 0 },
1000 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN
,
1001 CPU_AVX512CD_FLAGS
, 0 },
1002 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN
,
1003 CPU_AVX512ER_FLAGS
, 0 },
1004 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN
,
1005 CPU_AVX512PF_FLAGS
, 0 },
1006 { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN
,
1007 CPU_AVX512DQ_FLAGS
, 0 },
1008 { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN
,
1009 CPU_AVX512BW_FLAGS
, 0 },
1010 { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN
,
1011 CPU_AVX512VL_FLAGS
, 0 },
1012 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN
,
1014 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN
,
1015 CPU_VMFUNC_FLAGS
, 0 },
1016 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN
,
1018 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN
,
1019 CPU_XSAVE_FLAGS
, 0 },
1020 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN
,
1021 CPU_XSAVEOPT_FLAGS
, 0 },
1022 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN
,
1023 CPU_XSAVEC_FLAGS
, 0 },
1024 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN
,
1025 CPU_XSAVES_FLAGS
, 0 },
1026 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN
,
1028 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN
,
1029 CPU_PCLMUL_FLAGS
, 0 },
1030 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN
,
1031 CPU_PCLMUL_FLAGS
, 1 },
1032 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN
,
1033 CPU_FSGSBASE_FLAGS
, 0 },
1034 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN
,
1035 CPU_RDRND_FLAGS
, 0 },
1036 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN
,
1037 CPU_F16C_FLAGS
, 0 },
1038 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN
,
1039 CPU_BMI2_FLAGS
, 0 },
1040 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN
,
1042 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN
,
1043 CPU_FMA4_FLAGS
, 0 },
1044 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN
,
1046 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN
,
1048 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN
,
1049 CPU_MOVBE_FLAGS
, 0 },
1050 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN
,
1051 CPU_CX16_FLAGS
, 0 },
1052 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN
,
1054 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN
,
1055 CPU_LZCNT_FLAGS
, 0 },
1056 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN
,
1058 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN
,
1060 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN
,
1061 CPU_INVPCID_FLAGS
, 0 },
1062 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN
,
1063 CPU_CLFLUSH_FLAGS
, 0 },
1064 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN
,
1066 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN
,
1067 CPU_SYSCALL_FLAGS
, 0 },
1068 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN
,
1069 CPU_RDTSCP_FLAGS
, 0 },
1070 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN
,
1071 CPU_3DNOW_FLAGS
, 0 },
1072 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN
,
1073 CPU_3DNOWA_FLAGS
, 0 },
1074 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN
,
1075 CPU_PADLOCK_FLAGS
, 0 },
1076 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN
,
1077 CPU_SVME_FLAGS
, 1 },
1078 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN
,
1079 CPU_SVME_FLAGS
, 0 },
1080 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN
,
1081 CPU_SSE4A_FLAGS
, 0 },
1082 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN
,
1084 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN
,
1086 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN
,
1088 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN
,
1090 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN
,
1091 CPU_RDSEED_FLAGS
, 0 },
1092 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN
,
1093 CPU_PRFCHW_FLAGS
, 0 },
1094 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN
,
1095 CPU_SMAP_FLAGS
, 0 },
1096 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN
,
1098 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN
,
1100 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN
,
1101 CPU_CLFLUSHOPT_FLAGS
, 0 },
1102 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN
,
1103 CPU_PREFETCHWT1_FLAGS
, 0 },
1104 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN
,
1106 { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN
,
1107 CPU_CLWB_FLAGS
, 0 },
1108 { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN
,
1109 CPU_AVX512IFMA_FLAGS
, 0 },
1110 { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN
,
1111 CPU_AVX512VBMI_FLAGS
, 0 },
1112 { STRING_COMMA_LEN (".avx512_4fmaps"), PROCESSOR_UNKNOWN
,
1113 CPU_AVX512_4FMAPS_FLAGS
, 0 },
1114 { STRING_COMMA_LEN (".avx512_4vnniw"), PROCESSOR_UNKNOWN
,
1115 CPU_AVX512_4VNNIW_FLAGS
, 0 },
1116 { STRING_COMMA_LEN (".avx512_vpopcntdq"), PROCESSOR_UNKNOWN
,
1117 CPU_AVX512_VPOPCNTDQ_FLAGS
, 0 },
1118 { STRING_COMMA_LEN (".avx512_vbmi2"), PROCESSOR_UNKNOWN
,
1119 CPU_AVX512_VBMI2_FLAGS
, 0 },
1120 { STRING_COMMA_LEN (".avx512_vnni"), PROCESSOR_UNKNOWN
,
1121 CPU_AVX512_VNNI_FLAGS
, 0 },
1122 { STRING_COMMA_LEN (".avx512_bitalg"), PROCESSOR_UNKNOWN
,
1123 CPU_AVX512_BITALG_FLAGS
, 0 },
1124 { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN
,
1125 CPU_CLZERO_FLAGS
, 0 },
1126 { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN
,
1127 CPU_MWAITX_FLAGS
, 0 },
1128 { STRING_COMMA_LEN (".ospke"), PROCESSOR_UNKNOWN
,
1129 CPU_OSPKE_FLAGS
, 0 },
1130 { STRING_COMMA_LEN (".rdpid"), PROCESSOR_UNKNOWN
,
1131 CPU_RDPID_FLAGS
, 0 },
1132 { STRING_COMMA_LEN (".ptwrite"), PROCESSOR_UNKNOWN
,
1133 CPU_PTWRITE_FLAGS
, 0 },
1134 { STRING_COMMA_LEN (".ibt"), PROCESSOR_UNKNOWN
,
1136 { STRING_COMMA_LEN (".shstk"), PROCESSOR_UNKNOWN
,
1137 CPU_SHSTK_FLAGS
, 0 },
1138 { STRING_COMMA_LEN (".gfni"), PROCESSOR_UNKNOWN
,
1139 CPU_GFNI_FLAGS
, 0 },
1140 { STRING_COMMA_LEN (".vaes"), PROCESSOR_UNKNOWN
,
1141 CPU_VAES_FLAGS
, 0 },
1142 { STRING_COMMA_LEN (".vpclmulqdq"), PROCESSOR_UNKNOWN
,
1143 CPU_VPCLMULQDQ_FLAGS
, 0 },
1144 { STRING_COMMA_LEN (".wbnoinvd"), PROCESSOR_UNKNOWN
,
1145 CPU_WBNOINVD_FLAGS
, 0 },
1146 { STRING_COMMA_LEN (".pconfig"), PROCESSOR_UNKNOWN
,
1147 CPU_PCONFIG_FLAGS
, 0 },
1148 { STRING_COMMA_LEN (".waitpkg"), PROCESSOR_UNKNOWN
,
1149 CPU_WAITPKG_FLAGS
, 0 },
1150 { STRING_COMMA_LEN (".cldemote"), PROCESSOR_UNKNOWN
,
1151 CPU_CLDEMOTE_FLAGS
, 0 },
1152 { STRING_COMMA_LEN (".movdiri"), PROCESSOR_UNKNOWN
,
1153 CPU_MOVDIRI_FLAGS
, 0 },
1154 { STRING_COMMA_LEN (".movdir64b"), PROCESSOR_UNKNOWN
,
1155 CPU_MOVDIR64B_FLAGS
, 0 },
1156 { STRING_COMMA_LEN (".avx512_bf16"), PROCESSOR_UNKNOWN
,
1157 CPU_AVX512_BF16_FLAGS
, 0 },
1158 { STRING_COMMA_LEN (".avx512_vp2intersect"), PROCESSOR_UNKNOWN
,
1159 CPU_AVX512_VP2INTERSECT_FLAGS
, 0 },
1160 { STRING_COMMA_LEN (".enqcmd"), PROCESSOR_UNKNOWN
,
1161 CPU_ENQCMD_FLAGS
, 0 },
1162 { STRING_COMMA_LEN (".rdpru"), PROCESSOR_UNKNOWN
,
1163 CPU_RDPRU_FLAGS
, 0 },
1164 { STRING_COMMA_LEN (".mcommit"), PROCESSOR_UNKNOWN
,
1165 CPU_MCOMMIT_FLAGS
, 0 },
1168 static const noarch_entry cpu_noarch
[] =
1170 { STRING_COMMA_LEN ("no87"), CPU_ANY_X87_FLAGS
},
1171 { STRING_COMMA_LEN ("no287"), CPU_ANY_287_FLAGS
},
1172 { STRING_COMMA_LEN ("no387"), CPU_ANY_387_FLAGS
},
1173 { STRING_COMMA_LEN ("no687"), CPU_ANY_687_FLAGS
},
1174 { STRING_COMMA_LEN ("nocmov"), CPU_ANY_CMOV_FLAGS
},
1175 { STRING_COMMA_LEN ("nofxsr"), CPU_ANY_FXSR_FLAGS
},
1176 { STRING_COMMA_LEN ("nommx"), CPU_ANY_MMX_FLAGS
},
1177 { STRING_COMMA_LEN ("nosse"), CPU_ANY_SSE_FLAGS
},
1178 { STRING_COMMA_LEN ("nosse2"), CPU_ANY_SSE2_FLAGS
},
1179 { STRING_COMMA_LEN ("nosse3"), CPU_ANY_SSE3_FLAGS
},
1180 { STRING_COMMA_LEN ("nossse3"), CPU_ANY_SSSE3_FLAGS
},
1181 { STRING_COMMA_LEN ("nosse4.1"), CPU_ANY_SSE4_1_FLAGS
},
1182 { STRING_COMMA_LEN ("nosse4.2"), CPU_ANY_SSE4_2_FLAGS
},
1183 { STRING_COMMA_LEN ("nosse4"), CPU_ANY_SSE4_1_FLAGS
},
1184 { STRING_COMMA_LEN ("noavx"), CPU_ANY_AVX_FLAGS
},
1185 { STRING_COMMA_LEN ("noavx2"), CPU_ANY_AVX2_FLAGS
},
1186 { STRING_COMMA_LEN ("noavx512f"), CPU_ANY_AVX512F_FLAGS
},
1187 { STRING_COMMA_LEN ("noavx512cd"), CPU_ANY_AVX512CD_FLAGS
},
1188 { STRING_COMMA_LEN ("noavx512er"), CPU_ANY_AVX512ER_FLAGS
},
1189 { STRING_COMMA_LEN ("noavx512pf"), CPU_ANY_AVX512PF_FLAGS
},
1190 { STRING_COMMA_LEN ("noavx512dq"), CPU_ANY_AVX512DQ_FLAGS
},
1191 { STRING_COMMA_LEN ("noavx512bw"), CPU_ANY_AVX512BW_FLAGS
},
1192 { STRING_COMMA_LEN ("noavx512vl"), CPU_ANY_AVX512VL_FLAGS
},
1193 { STRING_COMMA_LEN ("noavx512ifma"), CPU_ANY_AVX512IFMA_FLAGS
},
1194 { STRING_COMMA_LEN ("noavx512vbmi"), CPU_ANY_AVX512VBMI_FLAGS
},
1195 { STRING_COMMA_LEN ("noavx512_4fmaps"), CPU_ANY_AVX512_4FMAPS_FLAGS
},
1196 { STRING_COMMA_LEN ("noavx512_4vnniw"), CPU_ANY_AVX512_4VNNIW_FLAGS
},
1197 { STRING_COMMA_LEN ("noavx512_vpopcntdq"), CPU_ANY_AVX512_VPOPCNTDQ_FLAGS
},
1198 { STRING_COMMA_LEN ("noavx512_vbmi2"), CPU_ANY_AVX512_VBMI2_FLAGS
},
1199 { STRING_COMMA_LEN ("noavx512_vnni"), CPU_ANY_AVX512_VNNI_FLAGS
},
1200 { STRING_COMMA_LEN ("noavx512_bitalg"), CPU_ANY_AVX512_BITALG_FLAGS
},
1201 { STRING_COMMA_LEN ("noibt"), CPU_ANY_IBT_FLAGS
},
1202 { STRING_COMMA_LEN ("noshstk"), CPU_ANY_SHSTK_FLAGS
},
1203 { STRING_COMMA_LEN ("nomovdiri"), CPU_ANY_MOVDIRI_FLAGS
},
1204 { STRING_COMMA_LEN ("nomovdir64b"), CPU_ANY_MOVDIR64B_FLAGS
},
1205 { STRING_COMMA_LEN ("noavx512_bf16"), CPU_ANY_AVX512_BF16_FLAGS
},
1206 { STRING_COMMA_LEN ("noavx512_vp2intersect"), CPU_ANY_SHSTK_FLAGS
},
1207 { STRING_COMMA_LEN ("noenqcmd"), CPU_ANY_ENQCMD_FLAGS
},
1211 /* Like s_lcomm_internal in gas/read.c but the alignment string
1212 is allowed to be optional. */
1215 pe_lcomm_internal (int needs_align
, symbolS
*symbolP
, addressT size
)
1222 && *input_line_pointer
== ',')
1224 align
= parse_align (needs_align
- 1);
1226 if (align
== (addressT
) -1)
1241 bss_alloc (symbolP
, size
, align
);
1246 pe_lcomm (int needs_align
)
1248 s_comm_internal (needs_align
* 2, pe_lcomm_internal
);
1252 const pseudo_typeS md_pseudo_table
[] =
1254 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
1255 {"align", s_align_bytes
, 0},
1257 {"align", s_align_ptwo
, 0},
1259 {"arch", set_cpu_arch
, 0},
1263 {"lcomm", pe_lcomm
, 1},
1265 {"ffloat", float_cons
, 'f'},
1266 {"dfloat", float_cons
, 'd'},
1267 {"tfloat", float_cons
, 'x'},
1269 {"slong", signed_cons
, 4},
1270 {"noopt", s_ignore
, 0},
1271 {"optim", s_ignore
, 0},
1272 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
1273 {"code16", set_code_flag
, CODE_16BIT
},
1274 {"code32", set_code_flag
, CODE_32BIT
},
1276 {"code64", set_code_flag
, CODE_64BIT
},
1278 {"intel_syntax", set_intel_syntax
, 1},
1279 {"att_syntax", set_intel_syntax
, 0},
1280 {"intel_mnemonic", set_intel_mnemonic
, 1},
1281 {"att_mnemonic", set_intel_mnemonic
, 0},
1282 {"allow_index_reg", set_allow_index_reg
, 1},
1283 {"disallow_index_reg", set_allow_index_reg
, 0},
1284 {"sse_check", set_check
, 0},
1285 {"operand_check", set_check
, 1},
1286 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1287 {"largecomm", handle_large_common
, 0},
1289 {"file", dwarf2_directive_file
, 0},
1290 {"loc", dwarf2_directive_loc
, 0},
1291 {"loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0},
1294 {"secrel32", pe_directive_secrel
, 0},
1299 /* For interface with expression (). */
1300 extern char *input_line_pointer
;
1302 /* Hash table for instruction mnemonic lookup. */
1303 static struct hash_control
*op_hash
;
1305 /* Hash table for register lookup. */
1306 static struct hash_control
*reg_hash
;
1308 /* Various efficient no-op patterns for aligning code labels.
1309 Note: Don't try to assemble the instructions in the comments.
1310 0L and 0w are not legal. */
1311 static const unsigned char f32_1
[] =
1313 static const unsigned char f32_2
[] =
1314 {0x66,0x90}; /* xchg %ax,%ax */
1315 static const unsigned char f32_3
[] =
1316 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1317 static const unsigned char f32_4
[] =
1318 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1319 static const unsigned char f32_6
[] =
1320 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1321 static const unsigned char f32_7
[] =
1322 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1323 static const unsigned char f16_3
[] =
1324 {0x8d,0x74,0x00}; /* lea 0(%si),%si */
1325 static const unsigned char f16_4
[] =
1326 {0x8d,0xb4,0x00,0x00}; /* lea 0W(%si),%si */
1327 static const unsigned char jump_disp8
[] =
1328 {0xeb}; /* jmp disp8 */
1329 static const unsigned char jump32_disp32
[] =
1330 {0xe9}; /* jmp disp32 */
1331 static const unsigned char jump16_disp32
[] =
1332 {0x66,0xe9}; /* jmp disp32 */
1333 /* 32-bit NOPs patterns. */
1334 static const unsigned char *const f32_patt
[] = {
1335 f32_1
, f32_2
, f32_3
, f32_4
, NULL
, f32_6
, f32_7
1337 /* 16-bit NOPs patterns. */
1338 static const unsigned char *const f16_patt
[] = {
1339 f32_1
, f32_2
, f16_3
, f16_4
1341 /* nopl (%[re]ax) */
1342 static const unsigned char alt_3
[] =
1344 /* nopl 0(%[re]ax) */
1345 static const unsigned char alt_4
[] =
1346 {0x0f,0x1f,0x40,0x00};
1347 /* nopl 0(%[re]ax,%[re]ax,1) */
1348 static const unsigned char alt_5
[] =
1349 {0x0f,0x1f,0x44,0x00,0x00};
1350 /* nopw 0(%[re]ax,%[re]ax,1) */
1351 static const unsigned char alt_6
[] =
1352 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1353 /* nopl 0L(%[re]ax) */
1354 static const unsigned char alt_7
[] =
1355 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1356 /* nopl 0L(%[re]ax,%[re]ax,1) */
1357 static const unsigned char alt_8
[] =
1358 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1359 /* nopw 0L(%[re]ax,%[re]ax,1) */
1360 static const unsigned char alt_9
[] =
1361 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1362 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1363 static const unsigned char alt_10
[] =
1364 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1365 /* data16 nopw %cs:0L(%eax,%eax,1) */
1366 static const unsigned char alt_11
[] =
1367 {0x66,0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1368 /* 32-bit and 64-bit NOPs patterns. */
1369 static const unsigned char *const alt_patt
[] = {
1370 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
1371 alt_9
, alt_10
, alt_11
1374 /* Genenerate COUNT bytes of NOPs to WHERE from PATT with the maximum
1375 size of a single NOP instruction MAX_SINGLE_NOP_SIZE. */
1378 i386_output_nops (char *where
, const unsigned char *const *patt
,
1379 int count
, int max_single_nop_size
)
1382 /* Place the longer NOP first. */
1385 const unsigned char *nops
;
1387 if (max_single_nop_size
< 1)
1389 as_fatal (_("i386_output_nops called to generate nops of at most %d bytes!"),
1390 max_single_nop_size
);
1394 nops
= patt
[max_single_nop_size
- 1];
1396 /* Use the smaller one if the requsted one isn't available. */
1399 max_single_nop_size
--;
1400 nops
= patt
[max_single_nop_size
- 1];
1403 last
= count
% max_single_nop_size
;
1406 for (offset
= 0; offset
< count
; offset
+= max_single_nop_size
)
1407 memcpy (where
+ offset
, nops
, max_single_nop_size
);
1411 nops
= patt
[last
- 1];
1414 /* Use the smaller one plus one-byte NOP if the needed one
1417 nops
= patt
[last
- 1];
1418 memcpy (where
+ offset
, nops
, last
);
1419 where
[offset
+ last
] = *patt
[0];
1422 memcpy (where
+ offset
, nops
, last
);
1427 fits_in_imm7 (offsetT num
)
1429 return (num
& 0x7f) == num
;
1433 fits_in_imm31 (offsetT num
)
1435 return (num
& 0x7fffffff) == num
;
1438 /* Genenerate COUNT bytes of NOPs to WHERE with the maximum size of a
1439 single NOP instruction LIMIT. */
1442 i386_generate_nops (fragS
*fragP
, char *where
, offsetT count
, int limit
)
1444 const unsigned char *const *patt
= NULL
;
1445 int max_single_nop_size
;
1446 /* Maximum number of NOPs before switching to jump over NOPs. */
1447 int max_number_of_nops
;
1449 switch (fragP
->fr_type
)
1454 case rs_machine_dependent
:
1455 /* Allow NOP padding for jumps and calls. */
1456 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
1457 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
)
1464 /* We need to decide which NOP sequence to use for 32bit and
1465 64bit. When -mtune= is used:
1467 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1468 PROCESSOR_GENERIC32, f32_patt will be used.
1469 2. For the rest, alt_patt will be used.
1471 When -mtune= isn't used, alt_patt will be used if
1472 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
1475 When -march= or .arch is used, we can't use anything beyond
1476 cpu_arch_isa_flags. */
1478 if (flag_code
== CODE_16BIT
)
1481 max_single_nop_size
= sizeof (f16_patt
) / sizeof (f16_patt
[0]);
1482 /* Limit number of NOPs to 2 in 16-bit mode. */
1483 max_number_of_nops
= 2;
1487 if (fragP
->tc_frag_data
.isa
== PROCESSOR_UNKNOWN
)
1489 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1490 switch (cpu_arch_tune
)
1492 case PROCESSOR_UNKNOWN
:
1493 /* We use cpu_arch_isa_flags to check if we SHOULD
1494 optimize with nops. */
1495 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1500 case PROCESSOR_PENTIUM4
:
1501 case PROCESSOR_NOCONA
:
1502 case PROCESSOR_CORE
:
1503 case PROCESSOR_CORE2
:
1504 case PROCESSOR_COREI7
:
1505 case PROCESSOR_L1OM
:
1506 case PROCESSOR_K1OM
:
1507 case PROCESSOR_GENERIC64
:
1509 case PROCESSOR_ATHLON
:
1511 case PROCESSOR_AMDFAM10
:
1513 case PROCESSOR_ZNVER
:
1517 case PROCESSOR_I386
:
1518 case PROCESSOR_I486
:
1519 case PROCESSOR_PENTIUM
:
1520 case PROCESSOR_PENTIUMPRO
:
1521 case PROCESSOR_IAMCU
:
1522 case PROCESSOR_GENERIC32
:
1529 switch (fragP
->tc_frag_data
.tune
)
1531 case PROCESSOR_UNKNOWN
:
1532 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1533 PROCESSOR_UNKNOWN. */
1537 case PROCESSOR_I386
:
1538 case PROCESSOR_I486
:
1539 case PROCESSOR_PENTIUM
:
1540 case PROCESSOR_IAMCU
:
1542 case PROCESSOR_ATHLON
:
1544 case PROCESSOR_AMDFAM10
:
1546 case PROCESSOR_ZNVER
:
1548 case PROCESSOR_GENERIC32
:
1549 /* We use cpu_arch_isa_flags to check if we CAN optimize
1551 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1556 case PROCESSOR_PENTIUMPRO
:
1557 case PROCESSOR_PENTIUM4
:
1558 case PROCESSOR_NOCONA
:
1559 case PROCESSOR_CORE
:
1560 case PROCESSOR_CORE2
:
1561 case PROCESSOR_COREI7
:
1562 case PROCESSOR_L1OM
:
1563 case PROCESSOR_K1OM
:
1564 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1569 case PROCESSOR_GENERIC64
:
1575 if (patt
== f32_patt
)
1577 max_single_nop_size
= sizeof (f32_patt
) / sizeof (f32_patt
[0]);
1578 /* Limit number of NOPs to 2 for older processors. */
1579 max_number_of_nops
= 2;
1583 max_single_nop_size
= sizeof (alt_patt
) / sizeof (alt_patt
[0]);
1584 /* Limit number of NOPs to 7 for newer processors. */
1585 max_number_of_nops
= 7;
1590 limit
= max_single_nop_size
;
1592 if (fragP
->fr_type
== rs_fill_nop
)
1594 /* Output NOPs for .nop directive. */
1595 if (limit
> max_single_nop_size
)
1597 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
1598 _("invalid single nop size: %d "
1599 "(expect within [0, %d])"),
1600 limit
, max_single_nop_size
);
1604 else if (fragP
->fr_type
!= rs_machine_dependent
)
1605 fragP
->fr_var
= count
;
1607 if ((count
/ max_single_nop_size
) > max_number_of_nops
)
1609 /* Generate jump over NOPs. */
1610 offsetT disp
= count
- 2;
1611 if (fits_in_imm7 (disp
))
1613 /* Use "jmp disp8" if possible. */
1615 where
[0] = jump_disp8
[0];
1621 unsigned int size_of_jump
;
1623 if (flag_code
== CODE_16BIT
)
1625 where
[0] = jump16_disp32
[0];
1626 where
[1] = jump16_disp32
[1];
1631 where
[0] = jump32_disp32
[0];
1635 count
-= size_of_jump
+ 4;
1636 if (!fits_in_imm31 (count
))
1638 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
1639 _("jump over nop padding out of range"));
1643 md_number_to_chars (where
+ size_of_jump
, count
, 4);
1644 where
+= size_of_jump
+ 4;
1648 /* Generate multiple NOPs. */
1649 i386_output_nops (where
, patt
, count
, limit
);
1653 operand_type_all_zero (const union i386_operand_type
*x
)
1655 switch (ARRAY_SIZE(x
->array
))
1666 return !x
->array
[0];
1673 operand_type_set (union i386_operand_type
*x
, unsigned int v
)
1675 switch (ARRAY_SIZE(x
->array
))
1691 x
->bitfield
.class = ClassNone
;
1692 x
->bitfield
.instance
= InstanceNone
;
1696 operand_type_equal (const union i386_operand_type
*x
,
1697 const union i386_operand_type
*y
)
1699 switch (ARRAY_SIZE(x
->array
))
1702 if (x
->array
[2] != y
->array
[2])
1706 if (x
->array
[1] != y
->array
[1])
1710 return x
->array
[0] == y
->array
[0];
1718 cpu_flags_all_zero (const union i386_cpu_flags
*x
)
1720 switch (ARRAY_SIZE(x
->array
))
1735 return !x
->array
[0];
1742 cpu_flags_equal (const union i386_cpu_flags
*x
,
1743 const union i386_cpu_flags
*y
)
1745 switch (ARRAY_SIZE(x
->array
))
1748 if (x
->array
[3] != y
->array
[3])
1752 if (x
->array
[2] != y
->array
[2])
1756 if (x
->array
[1] != y
->array
[1])
1760 return x
->array
[0] == y
->array
[0];
1768 cpu_flags_check_cpu64 (i386_cpu_flags f
)
1770 return !((flag_code
== CODE_64BIT
&& f
.bitfield
.cpuno64
)
1771 || (flag_code
!= CODE_64BIT
&& f
.bitfield
.cpu64
));
1774 static INLINE i386_cpu_flags
1775 cpu_flags_and (i386_cpu_flags x
, i386_cpu_flags y
)
1777 switch (ARRAY_SIZE (x
.array
))
1780 x
.array
[3] &= y
.array
[3];
1783 x
.array
[2] &= y
.array
[2];
1786 x
.array
[1] &= y
.array
[1];
1789 x
.array
[0] &= y
.array
[0];
1797 static INLINE i386_cpu_flags
1798 cpu_flags_or (i386_cpu_flags x
, i386_cpu_flags y
)
1800 switch (ARRAY_SIZE (x
.array
))
1803 x
.array
[3] |= y
.array
[3];
1806 x
.array
[2] |= y
.array
[2];
1809 x
.array
[1] |= y
.array
[1];
1812 x
.array
[0] |= y
.array
[0];
1820 static INLINE i386_cpu_flags
1821 cpu_flags_and_not (i386_cpu_flags x
, i386_cpu_flags y
)
1823 switch (ARRAY_SIZE (x
.array
))
1826 x
.array
[3] &= ~y
.array
[3];
1829 x
.array
[2] &= ~y
.array
[2];
1832 x
.array
[1] &= ~y
.array
[1];
1835 x
.array
[0] &= ~y
.array
[0];
1843 #define CPU_FLAGS_ARCH_MATCH 0x1
1844 #define CPU_FLAGS_64BIT_MATCH 0x2
1846 #define CPU_FLAGS_PERFECT_MATCH \
1847 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_64BIT_MATCH)
1849 /* Return CPU flags match bits. */
1852 cpu_flags_match (const insn_template
*t
)
1854 i386_cpu_flags x
= t
->cpu_flags
;
1855 int match
= cpu_flags_check_cpu64 (x
) ? CPU_FLAGS_64BIT_MATCH
: 0;
1857 x
.bitfield
.cpu64
= 0;
1858 x
.bitfield
.cpuno64
= 0;
1860 if (cpu_flags_all_zero (&x
))
1862 /* This instruction is available on all archs. */
1863 match
|= CPU_FLAGS_ARCH_MATCH
;
1867 /* This instruction is available only on some archs. */
1868 i386_cpu_flags cpu
= cpu_arch_flags
;
1870 /* AVX512VL is no standalone feature - match it and then strip it. */
1871 if (x
.bitfield
.cpuavx512vl
&& !cpu
.bitfield
.cpuavx512vl
)
1873 x
.bitfield
.cpuavx512vl
= 0;
1875 cpu
= cpu_flags_and (x
, cpu
);
1876 if (!cpu_flags_all_zero (&cpu
))
1878 if (x
.bitfield
.cpuavx
)
1880 /* We need to check a few extra flags with AVX. */
1881 if (cpu
.bitfield
.cpuavx
1882 && (!t
->opcode_modifier
.sse2avx
|| sse2avx
)
1883 && (!x
.bitfield
.cpuaes
|| cpu
.bitfield
.cpuaes
)
1884 && (!x
.bitfield
.cpugfni
|| cpu
.bitfield
.cpugfni
)
1885 && (!x
.bitfield
.cpupclmul
|| cpu
.bitfield
.cpupclmul
))
1886 match
|= CPU_FLAGS_ARCH_MATCH
;
1888 else if (x
.bitfield
.cpuavx512f
)
1890 /* We need to check a few extra flags with AVX512F. */
1891 if (cpu
.bitfield
.cpuavx512f
1892 && (!x
.bitfield
.cpugfni
|| cpu
.bitfield
.cpugfni
)
1893 && (!x
.bitfield
.cpuvaes
|| cpu
.bitfield
.cpuvaes
)
1894 && (!x
.bitfield
.cpuvpclmulqdq
|| cpu
.bitfield
.cpuvpclmulqdq
))
1895 match
|= CPU_FLAGS_ARCH_MATCH
;
1898 match
|= CPU_FLAGS_ARCH_MATCH
;
1904 static INLINE i386_operand_type
1905 operand_type_and (i386_operand_type x
, i386_operand_type y
)
1907 if (x
.bitfield
.class != y
.bitfield
.class)
1908 x
.bitfield
.class = ClassNone
;
1909 if (x
.bitfield
.instance
!= y
.bitfield
.instance
)
1910 x
.bitfield
.instance
= InstanceNone
;
1912 switch (ARRAY_SIZE (x
.array
))
1915 x
.array
[2] &= y
.array
[2];
1918 x
.array
[1] &= y
.array
[1];
1921 x
.array
[0] &= y
.array
[0];
1929 static INLINE i386_operand_type
1930 operand_type_and_not (i386_operand_type x
, i386_operand_type y
)
1932 gas_assert (y
.bitfield
.class == ClassNone
);
1933 gas_assert (y
.bitfield
.instance
== InstanceNone
);
1935 switch (ARRAY_SIZE (x
.array
))
1938 x
.array
[2] &= ~y
.array
[2];
1941 x
.array
[1] &= ~y
.array
[1];
1944 x
.array
[0] &= ~y
.array
[0];
1952 static INLINE i386_operand_type
1953 operand_type_or (i386_operand_type x
, i386_operand_type y
)
1955 gas_assert (x
.bitfield
.class == ClassNone
||
1956 y
.bitfield
.class == ClassNone
||
1957 x
.bitfield
.class == y
.bitfield
.class);
1958 gas_assert (x
.bitfield
.instance
== InstanceNone
||
1959 y
.bitfield
.instance
== InstanceNone
||
1960 x
.bitfield
.instance
== y
.bitfield
.instance
);
1962 switch (ARRAY_SIZE (x
.array
))
1965 x
.array
[2] |= y
.array
[2];
1968 x
.array
[1] |= y
.array
[1];
1971 x
.array
[0] |= y
.array
[0];
1979 static INLINE i386_operand_type
1980 operand_type_xor (i386_operand_type x
, i386_operand_type y
)
1982 gas_assert (y
.bitfield
.class == ClassNone
);
1983 gas_assert (y
.bitfield
.instance
== InstanceNone
);
1985 switch (ARRAY_SIZE (x
.array
))
1988 x
.array
[2] ^= y
.array
[2];
1991 x
.array
[1] ^= y
.array
[1];
1994 x
.array
[0] ^= y
.array
[0];
2002 static const i386_operand_type disp16
= OPERAND_TYPE_DISP16
;
2003 static const i386_operand_type disp32
= OPERAND_TYPE_DISP32
;
2004 static const i386_operand_type disp32s
= OPERAND_TYPE_DISP32S
;
2005 static const i386_operand_type disp16_32
= OPERAND_TYPE_DISP16_32
;
2006 static const i386_operand_type anydisp
= OPERAND_TYPE_ANYDISP
;
2007 static const i386_operand_type anyimm
= OPERAND_TYPE_ANYIMM
;
2008 static const i386_operand_type regxmm
= OPERAND_TYPE_REGXMM
;
2009 static const i386_operand_type regmask
= OPERAND_TYPE_REGMASK
;
2010 static const i386_operand_type imm8
= OPERAND_TYPE_IMM8
;
2011 static const i386_operand_type imm8s
= OPERAND_TYPE_IMM8S
;
2012 static const i386_operand_type imm16
= OPERAND_TYPE_IMM16
;
2013 static const i386_operand_type imm32
= OPERAND_TYPE_IMM32
;
2014 static const i386_operand_type imm32s
= OPERAND_TYPE_IMM32S
;
2015 static const i386_operand_type imm64
= OPERAND_TYPE_IMM64
;
2016 static const i386_operand_type imm16_32
= OPERAND_TYPE_IMM16_32
;
2017 static const i386_operand_type imm16_32s
= OPERAND_TYPE_IMM16_32S
;
2018 static const i386_operand_type imm16_32_32s
= OPERAND_TYPE_IMM16_32_32S
;
2029 operand_type_check (i386_operand_type t
, enum operand_type c
)
2034 return t
.bitfield
.class == Reg
;
2037 return (t
.bitfield
.imm8
2041 || t
.bitfield
.imm32s
2042 || t
.bitfield
.imm64
);
2045 return (t
.bitfield
.disp8
2046 || t
.bitfield
.disp16
2047 || t
.bitfield
.disp32
2048 || t
.bitfield
.disp32s
2049 || t
.bitfield
.disp64
);
2052 return (t
.bitfield
.disp8
2053 || t
.bitfield
.disp16
2054 || t
.bitfield
.disp32
2055 || t
.bitfield
.disp32s
2056 || t
.bitfield
.disp64
2057 || t
.bitfield
.baseindex
);
2066 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit/80bit size
2067 between operand GIVEN and opeand WANTED for instruction template T. */
2070 match_operand_size (const insn_template
*t
, unsigned int wanted
,
2073 return !((i
.types
[given
].bitfield
.byte
2074 && !t
->operand_types
[wanted
].bitfield
.byte
)
2075 || (i
.types
[given
].bitfield
.word
2076 && !t
->operand_types
[wanted
].bitfield
.word
)
2077 || (i
.types
[given
].bitfield
.dword
2078 && !t
->operand_types
[wanted
].bitfield
.dword
)
2079 || (i
.types
[given
].bitfield
.qword
2080 && !t
->operand_types
[wanted
].bitfield
.qword
)
2081 || (i
.types
[given
].bitfield
.tbyte
2082 && !t
->operand_types
[wanted
].bitfield
.tbyte
));
2085 /* Return 1 if there is no conflict in SIMD register between operand
2086 GIVEN and opeand WANTED for instruction template T. */
2089 match_simd_size (const insn_template
*t
, unsigned int wanted
,
2092 return !((i
.types
[given
].bitfield
.xmmword
2093 && !t
->operand_types
[wanted
].bitfield
.xmmword
)
2094 || (i
.types
[given
].bitfield
.ymmword
2095 && !t
->operand_types
[wanted
].bitfield
.ymmword
)
2096 || (i
.types
[given
].bitfield
.zmmword
2097 && !t
->operand_types
[wanted
].bitfield
.zmmword
));
2100 /* Return 1 if there is no conflict in any size between operand GIVEN
2101 and opeand WANTED for instruction template T. */
2104 match_mem_size (const insn_template
*t
, unsigned int wanted
,
2107 return (match_operand_size (t
, wanted
, given
)
2108 && !((i
.types
[given
].bitfield
.unspecified
2110 && !t
->operand_types
[wanted
].bitfield
.unspecified
)
2111 || (i
.types
[given
].bitfield
.fword
2112 && !t
->operand_types
[wanted
].bitfield
.fword
)
2113 /* For scalar opcode templates to allow register and memory
2114 operands at the same time, some special casing is needed
2115 here. Also for v{,p}broadcast*, {,v}pmov{s,z}*, and
2116 down-conversion vpmov*. */
2117 || ((t
->operand_types
[wanted
].bitfield
.class == RegSIMD
2118 && !t
->opcode_modifier
.broadcast
2119 && (t
->operand_types
[wanted
].bitfield
.byte
2120 || t
->operand_types
[wanted
].bitfield
.word
2121 || t
->operand_types
[wanted
].bitfield
.dword
2122 || t
->operand_types
[wanted
].bitfield
.qword
))
2123 ? (i
.types
[given
].bitfield
.xmmword
2124 || i
.types
[given
].bitfield
.ymmword
2125 || i
.types
[given
].bitfield
.zmmword
)
2126 : !match_simd_size(t
, wanted
, given
))));
2129 /* Return value has MATCH_STRAIGHT set if there is no size conflict on any
2130 operands for instruction template T, and it has MATCH_REVERSE set if there
2131 is no size conflict on any operands for the template with operands reversed
2132 (and the template allows for reversing in the first place). */
2134 #define MATCH_STRAIGHT 1
2135 #define MATCH_REVERSE 2
2137 static INLINE
unsigned int
2138 operand_size_match (const insn_template
*t
)
2140 unsigned int j
, match
= MATCH_STRAIGHT
;
2142 /* Don't check non-absolute jump instructions. */
2143 if (t
->opcode_modifier
.jump
2144 && t
->opcode_modifier
.jump
!= JUMP_ABSOLUTE
)
2147 /* Check memory and accumulator operand size. */
2148 for (j
= 0; j
< i
.operands
; j
++)
2150 if (i
.types
[j
].bitfield
.class != Reg
2151 && i
.types
[j
].bitfield
.class != RegSIMD
2152 && t
->opcode_modifier
.anysize
)
2155 if (t
->operand_types
[j
].bitfield
.class == Reg
2156 && !match_operand_size (t
, j
, j
))
2162 if (t
->operand_types
[j
].bitfield
.class == RegSIMD
2163 && !match_simd_size (t
, j
, j
))
2169 if (t
->operand_types
[j
].bitfield
.instance
== Accum
2170 && (!match_operand_size (t
, j
, j
) || !match_simd_size (t
, j
, j
)))
2176 if ((i
.flags
[j
] & Operand_Mem
) && !match_mem_size (t
, j
, j
))
2183 if (!t
->opcode_modifier
.d
)
2187 i
.error
= operand_size_mismatch
;
2191 /* Check reverse. */
2192 gas_assert (i
.operands
>= 2 && i
.operands
<= 3);
2194 for (j
= 0; j
< i
.operands
; j
++)
2196 unsigned int given
= i
.operands
- j
- 1;
2198 if (t
->operand_types
[j
].bitfield
.class == Reg
2199 && !match_operand_size (t
, j
, given
))
2202 if (t
->operand_types
[j
].bitfield
.class == RegSIMD
2203 && !match_simd_size (t
, j
, given
))
2206 if (t
->operand_types
[j
].bitfield
.instance
== Accum
2207 && (!match_operand_size (t
, j
, given
)
2208 || !match_simd_size (t
, j
, given
)))
2211 if ((i
.flags
[given
] & Operand_Mem
) && !match_mem_size (t
, j
, given
))
2215 return match
| MATCH_REVERSE
;
2219 operand_type_match (i386_operand_type overlap
,
2220 i386_operand_type given
)
2222 i386_operand_type temp
= overlap
;
2224 temp
.bitfield
.unspecified
= 0;
2225 temp
.bitfield
.byte
= 0;
2226 temp
.bitfield
.word
= 0;
2227 temp
.bitfield
.dword
= 0;
2228 temp
.bitfield
.fword
= 0;
2229 temp
.bitfield
.qword
= 0;
2230 temp
.bitfield
.tbyte
= 0;
2231 temp
.bitfield
.xmmword
= 0;
2232 temp
.bitfield
.ymmword
= 0;
2233 temp
.bitfield
.zmmword
= 0;
2234 if (operand_type_all_zero (&temp
))
2237 if (given
.bitfield
.baseindex
== overlap
.bitfield
.baseindex
)
2241 i
.error
= operand_type_mismatch
;
2245 /* If given types g0 and g1 are registers they must be of the same type
2246 unless the expected operand type register overlap is null.
2247 Some Intel syntax memory operand size checking also happens here. */
2250 operand_type_register_match (i386_operand_type g0
,
2251 i386_operand_type t0
,
2252 i386_operand_type g1
,
2253 i386_operand_type t1
)
2255 if (g0
.bitfield
.class != Reg
2256 && g0
.bitfield
.class != RegSIMD
2257 && (!operand_type_check (g0
, anymem
)
2258 || g0
.bitfield
.unspecified
2259 || (t0
.bitfield
.class != Reg
2260 && t0
.bitfield
.class != RegSIMD
)))
2263 if (g1
.bitfield
.class != Reg
2264 && g1
.bitfield
.class != RegSIMD
2265 && (!operand_type_check (g1
, anymem
)
2266 || g1
.bitfield
.unspecified
2267 || (t1
.bitfield
.class != Reg
2268 && t1
.bitfield
.class != RegSIMD
)))
2271 if (g0
.bitfield
.byte
== g1
.bitfield
.byte
2272 && g0
.bitfield
.word
== g1
.bitfield
.word
2273 && g0
.bitfield
.dword
== g1
.bitfield
.dword
2274 && g0
.bitfield
.qword
== g1
.bitfield
.qword
2275 && g0
.bitfield
.xmmword
== g1
.bitfield
.xmmword
2276 && g0
.bitfield
.ymmword
== g1
.bitfield
.ymmword
2277 && g0
.bitfield
.zmmword
== g1
.bitfield
.zmmword
)
2280 if (!(t0
.bitfield
.byte
& t1
.bitfield
.byte
)
2281 && !(t0
.bitfield
.word
& t1
.bitfield
.word
)
2282 && !(t0
.bitfield
.dword
& t1
.bitfield
.dword
)
2283 && !(t0
.bitfield
.qword
& t1
.bitfield
.qword
)
2284 && !(t0
.bitfield
.xmmword
& t1
.bitfield
.xmmword
)
2285 && !(t0
.bitfield
.ymmword
& t1
.bitfield
.ymmword
)
2286 && !(t0
.bitfield
.zmmword
& t1
.bitfield
.zmmword
))
2289 i
.error
= register_type_mismatch
;
2294 static INLINE
unsigned int
2295 register_number (const reg_entry
*r
)
2297 unsigned int nr
= r
->reg_num
;
2299 if (r
->reg_flags
& RegRex
)
2302 if (r
->reg_flags
& RegVRex
)
2308 static INLINE
unsigned int
2309 mode_from_disp_size (i386_operand_type t
)
2311 if (t
.bitfield
.disp8
)
2313 else if (t
.bitfield
.disp16
2314 || t
.bitfield
.disp32
2315 || t
.bitfield
.disp32s
)
2322 fits_in_signed_byte (addressT num
)
2324 return num
+ 0x80 <= 0xff;
2328 fits_in_unsigned_byte (addressT num
)
2334 fits_in_unsigned_word (addressT num
)
2336 return num
<= 0xffff;
2340 fits_in_signed_word (addressT num
)
2342 return num
+ 0x8000 <= 0xffff;
2346 fits_in_signed_long (addressT num ATTRIBUTE_UNUSED
)
2351 return num
+ 0x80000000 <= 0xffffffff;
2353 } /* fits_in_signed_long() */
2356 fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED
)
2361 return num
<= 0xffffffff;
2363 } /* fits_in_unsigned_long() */
2366 fits_in_disp8 (offsetT num
)
2368 int shift
= i
.memshift
;
2374 mask
= (1 << shift
) - 1;
2376 /* Return 0 if NUM isn't properly aligned. */
2380 /* Check if NUM will fit in 8bit after shift. */
2381 return fits_in_signed_byte (num
>> shift
);
2385 fits_in_imm4 (offsetT num
)
2387 return (num
& 0xf) == num
;
2390 static i386_operand_type
2391 smallest_imm_type (offsetT num
)
2393 i386_operand_type t
;
2395 operand_type_set (&t
, 0);
2396 t
.bitfield
.imm64
= 1;
2398 if (cpu_arch_tune
!= PROCESSOR_I486
&& num
== 1)
2400 /* This code is disabled on the 486 because all the Imm1 forms
2401 in the opcode table are slower on the i486. They're the
2402 versions with the implicitly specified single-position
2403 displacement, which has another syntax if you really want to
2405 t
.bitfield
.imm1
= 1;
2406 t
.bitfield
.imm8
= 1;
2407 t
.bitfield
.imm8s
= 1;
2408 t
.bitfield
.imm16
= 1;
2409 t
.bitfield
.imm32
= 1;
2410 t
.bitfield
.imm32s
= 1;
2412 else if (fits_in_signed_byte (num
))
2414 t
.bitfield
.imm8
= 1;
2415 t
.bitfield
.imm8s
= 1;
2416 t
.bitfield
.imm16
= 1;
2417 t
.bitfield
.imm32
= 1;
2418 t
.bitfield
.imm32s
= 1;
2420 else if (fits_in_unsigned_byte (num
))
2422 t
.bitfield
.imm8
= 1;
2423 t
.bitfield
.imm16
= 1;
2424 t
.bitfield
.imm32
= 1;
2425 t
.bitfield
.imm32s
= 1;
2427 else if (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
2429 t
.bitfield
.imm16
= 1;
2430 t
.bitfield
.imm32
= 1;
2431 t
.bitfield
.imm32s
= 1;
2433 else if (fits_in_signed_long (num
))
2435 t
.bitfield
.imm32
= 1;
2436 t
.bitfield
.imm32s
= 1;
2438 else if (fits_in_unsigned_long (num
))
2439 t
.bitfield
.imm32
= 1;
2445 offset_in_range (offsetT val
, int size
)
2451 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
2452 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
2453 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
2455 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
2461 /* If BFD64, sign extend val for 32bit address mode. */
2462 if (flag_code
!= CODE_64BIT
2463 || i
.prefix
[ADDR_PREFIX
])
2464 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
2465 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
2468 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
2470 char buf1
[40], buf2
[40];
2472 sprint_value (buf1
, val
);
2473 sprint_value (buf2
, val
& mask
);
2474 as_warn (_("%s shortened to %s"), buf1
, buf2
);
2489 a. PREFIX_EXIST if attempting to add a prefix where one from the
2490 same class already exists.
2491 b. PREFIX_LOCK if lock prefix is added.
2492 c. PREFIX_REP if rep/repne prefix is added.
2493 d. PREFIX_DS if ds prefix is added.
2494 e. PREFIX_OTHER if other prefix is added.
2497 static enum PREFIX_GROUP
2498 add_prefix (unsigned int prefix
)
2500 enum PREFIX_GROUP ret
= PREFIX_OTHER
;
2503 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
2504 && flag_code
== CODE_64BIT
)
2506 if ((i
.prefix
[REX_PREFIX
] & prefix
& REX_W
)
2507 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_R
)
2508 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_X
)
2509 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_B
))
2520 case DS_PREFIX_OPCODE
:
2523 case CS_PREFIX_OPCODE
:
2524 case ES_PREFIX_OPCODE
:
2525 case FS_PREFIX_OPCODE
:
2526 case GS_PREFIX_OPCODE
:
2527 case SS_PREFIX_OPCODE
:
2531 case REPNE_PREFIX_OPCODE
:
2532 case REPE_PREFIX_OPCODE
:
2537 case LOCK_PREFIX_OPCODE
:
2546 case ADDR_PREFIX_OPCODE
:
2550 case DATA_PREFIX_OPCODE
:
2554 if (i
.prefix
[q
] != 0)
2562 i
.prefix
[q
] |= prefix
;
2565 as_bad (_("same type of prefix used twice"));
2571 update_code_flag (int value
, int check
)
2573 PRINTF_LIKE ((*as_error
));
2575 flag_code
= (enum flag_code
) value
;
2576 if (flag_code
== CODE_64BIT
)
2578 cpu_arch_flags
.bitfield
.cpu64
= 1;
2579 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2583 cpu_arch_flags
.bitfield
.cpu64
= 0;
2584 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2586 if (value
== CODE_64BIT
&& !cpu_arch_flags
.bitfield
.cpulm
)
2589 as_error
= as_fatal
;
2592 (*as_error
) (_("64bit mode not supported on `%s'."),
2593 cpu_arch_name
? cpu_arch_name
: default_arch
);
2595 if (value
== CODE_32BIT
&& !cpu_arch_flags
.bitfield
.cpui386
)
2598 as_error
= as_fatal
;
2601 (*as_error
) (_("32bit mode not supported on `%s'."),
2602 cpu_arch_name
? cpu_arch_name
: default_arch
);
2604 stackop_size
= '\0';
2608 set_code_flag (int value
)
2610 update_code_flag (value
, 0);
2614 set_16bit_gcc_code_flag (int new_code_flag
)
2616 flag_code
= (enum flag_code
) new_code_flag
;
2617 if (flag_code
!= CODE_16BIT
)
2619 cpu_arch_flags
.bitfield
.cpu64
= 0;
2620 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2621 stackop_size
= LONG_MNEM_SUFFIX
;
2625 set_intel_syntax (int syntax_flag
)
2627 /* Find out if register prefixing is specified. */
2628 int ask_naked_reg
= 0;
2631 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2634 int e
= get_symbol_name (&string
);
2636 if (strcmp (string
, "prefix") == 0)
2638 else if (strcmp (string
, "noprefix") == 0)
2641 as_bad (_("bad argument to syntax directive."));
2642 (void) restore_line_pointer (e
);
2644 demand_empty_rest_of_line ();
2646 intel_syntax
= syntax_flag
;
2648 if (ask_naked_reg
== 0)
2649 allow_naked_reg
= (intel_syntax
2650 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
2652 allow_naked_reg
= (ask_naked_reg
< 0);
2654 expr_set_rank (O_full_ptr
, syntax_flag
? 10 : 0);
2656 identifier_chars
['%'] = intel_syntax
&& allow_naked_reg
? '%' : 0;
2657 identifier_chars
['$'] = intel_syntax
? '$' : 0;
2658 register_prefix
= allow_naked_reg
? "" : "%";
2662 set_intel_mnemonic (int mnemonic_flag
)
2664 intel_mnemonic
= mnemonic_flag
;
2668 set_allow_index_reg (int flag
)
2670 allow_index_reg
= flag
;
2674 set_check (int what
)
2676 enum check_kind
*kind
;
2681 kind
= &operand_check
;
2692 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2695 int e
= get_symbol_name (&string
);
2697 if (strcmp (string
, "none") == 0)
2699 else if (strcmp (string
, "warning") == 0)
2700 *kind
= check_warning
;
2701 else if (strcmp (string
, "error") == 0)
2702 *kind
= check_error
;
2704 as_bad (_("bad argument to %s_check directive."), str
);
2705 (void) restore_line_pointer (e
);
2708 as_bad (_("missing argument for %s_check directive"), str
);
2710 demand_empty_rest_of_line ();
2714 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED
,
2715 i386_cpu_flags new_flag ATTRIBUTE_UNUSED
)
2717 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2718 static const char *arch
;
2720 /* Intel LIOM is only supported on ELF. */
2726 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2727 use default_arch. */
2728 arch
= cpu_arch_name
;
2730 arch
= default_arch
;
2733 /* If we are targeting Intel MCU, we must enable it. */
2734 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_IAMCU
2735 || new_flag
.bitfield
.cpuiamcu
)
2738 /* If we are targeting Intel L1OM, we must enable it. */
2739 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_L1OM
2740 || new_flag
.bitfield
.cpul1om
)
2743 /* If we are targeting Intel K1OM, we must enable it. */
2744 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_K1OM
2745 || new_flag
.bitfield
.cpuk1om
)
2748 as_bad (_("`%s' is not supported on `%s'"), name
, arch
);
2753 set_cpu_arch (int dummy ATTRIBUTE_UNUSED
)
2757 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2760 int e
= get_symbol_name (&string
);
2762 i386_cpu_flags flags
;
2764 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
2766 if (strcmp (string
, cpu_arch
[j
].name
) == 0)
2768 check_cpu_arch_compatible (string
, cpu_arch
[j
].flags
);
2772 cpu_arch_name
= cpu_arch
[j
].name
;
2773 cpu_sub_arch_name
= NULL
;
2774 cpu_arch_flags
= cpu_arch
[j
].flags
;
2775 if (flag_code
== CODE_64BIT
)
2777 cpu_arch_flags
.bitfield
.cpu64
= 1;
2778 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2782 cpu_arch_flags
.bitfield
.cpu64
= 0;
2783 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2785 cpu_arch_isa
= cpu_arch
[j
].type
;
2786 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
2787 if (!cpu_arch_tune_set
)
2789 cpu_arch_tune
= cpu_arch_isa
;
2790 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
2795 flags
= cpu_flags_or (cpu_arch_flags
,
2798 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2800 if (cpu_sub_arch_name
)
2802 char *name
= cpu_sub_arch_name
;
2803 cpu_sub_arch_name
= concat (name
,
2805 (const char *) NULL
);
2809 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
2810 cpu_arch_flags
= flags
;
2811 cpu_arch_isa_flags
= flags
;
2815 = cpu_flags_or (cpu_arch_isa_flags
,
2817 (void) restore_line_pointer (e
);
2818 demand_empty_rest_of_line ();
2823 if (*string
== '.' && j
>= ARRAY_SIZE (cpu_arch
))
2825 /* Disable an ISA extension. */
2826 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
2827 if (strcmp (string
+ 1, cpu_noarch
[j
].name
) == 0)
2829 flags
= cpu_flags_and_not (cpu_arch_flags
,
2830 cpu_noarch
[j
].flags
);
2831 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2833 if (cpu_sub_arch_name
)
2835 char *name
= cpu_sub_arch_name
;
2836 cpu_sub_arch_name
= concat (name
, string
,
2837 (const char *) NULL
);
2841 cpu_sub_arch_name
= xstrdup (string
);
2842 cpu_arch_flags
= flags
;
2843 cpu_arch_isa_flags
= flags
;
2845 (void) restore_line_pointer (e
);
2846 demand_empty_rest_of_line ();
2850 j
= ARRAY_SIZE (cpu_arch
);
2853 if (j
>= ARRAY_SIZE (cpu_arch
))
2854 as_bad (_("no such architecture: `%s'"), string
);
2856 *input_line_pointer
= e
;
2859 as_bad (_("missing cpu architecture"));
2861 no_cond_jump_promotion
= 0;
2862 if (*input_line_pointer
== ','
2863 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
2868 ++input_line_pointer
;
2869 e
= get_symbol_name (&string
);
2871 if (strcmp (string
, "nojumps") == 0)
2872 no_cond_jump_promotion
= 1;
2873 else if (strcmp (string
, "jumps") == 0)
2876 as_bad (_("no such architecture modifier: `%s'"), string
);
2878 (void) restore_line_pointer (e
);
2881 demand_empty_rest_of_line ();
2884 enum bfd_architecture
2887 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2889 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2890 || flag_code
!= CODE_64BIT
)
2891 as_fatal (_("Intel L1OM is 64bit ELF only"));
2892 return bfd_arch_l1om
;
2894 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2896 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2897 || flag_code
!= CODE_64BIT
)
2898 as_fatal (_("Intel K1OM is 64bit ELF only"));
2899 return bfd_arch_k1om
;
2901 else if (cpu_arch_isa
== PROCESSOR_IAMCU
)
2903 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2904 || flag_code
== CODE_64BIT
)
2905 as_fatal (_("Intel MCU is 32bit ELF only"));
2906 return bfd_arch_iamcu
;
2909 return bfd_arch_i386
;
2915 if (!strncmp (default_arch
, "x86_64", 6))
2917 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2919 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2920 || default_arch
[6] != '\0')
2921 as_fatal (_("Intel L1OM is 64bit ELF only"));
2922 return bfd_mach_l1om
;
2924 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2926 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2927 || default_arch
[6] != '\0')
2928 as_fatal (_("Intel K1OM is 64bit ELF only"));
2929 return bfd_mach_k1om
;
2931 else if (default_arch
[6] == '\0')
2932 return bfd_mach_x86_64
;
2934 return bfd_mach_x64_32
;
2936 else if (!strcmp (default_arch
, "i386")
2937 || !strcmp (default_arch
, "iamcu"))
2939 if (cpu_arch_isa
== PROCESSOR_IAMCU
)
2941 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
2942 as_fatal (_("Intel MCU is 32bit ELF only"));
2943 return bfd_mach_i386_iamcu
;
2946 return bfd_mach_i386_i386
;
2949 as_fatal (_("unknown architecture"));
2955 const char *hash_err
;
2957 /* Support pseudo prefixes like {disp32}. */
2958 lex_type
['{'] = LEX_BEGIN_NAME
;
2960 /* Initialize op_hash hash table. */
2961 op_hash
= hash_new ();
2964 const insn_template
*optab
;
2965 templates
*core_optab
;
2967 /* Setup for loop. */
2969 core_optab
= XNEW (templates
);
2970 core_optab
->start
= optab
;
2975 if (optab
->name
== NULL
2976 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
2978 /* different name --> ship out current template list;
2979 add to hash table; & begin anew. */
2980 core_optab
->end
= optab
;
2981 hash_err
= hash_insert (op_hash
,
2983 (void *) core_optab
);
2986 as_fatal (_("can't hash %s: %s"),
2990 if (optab
->name
== NULL
)
2992 core_optab
= XNEW (templates
);
2993 core_optab
->start
= optab
;
2998 /* Initialize reg_hash hash table. */
2999 reg_hash
= hash_new ();
3001 const reg_entry
*regtab
;
3002 unsigned int regtab_size
= i386_regtab_size
;
3004 for (regtab
= i386_regtab
; regtab_size
--; regtab
++)
3006 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (void *) regtab
);
3008 as_fatal (_("can't hash %s: %s"),
3014 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
3019 for (c
= 0; c
< 256; c
++)
3024 mnemonic_chars
[c
] = c
;
3025 register_chars
[c
] = c
;
3026 operand_chars
[c
] = c
;
3028 else if (ISLOWER (c
))
3030 mnemonic_chars
[c
] = c
;
3031 register_chars
[c
] = c
;
3032 operand_chars
[c
] = c
;
3034 else if (ISUPPER (c
))
3036 mnemonic_chars
[c
] = TOLOWER (c
);
3037 register_chars
[c
] = mnemonic_chars
[c
];
3038 operand_chars
[c
] = c
;
3040 else if (c
== '{' || c
== '}')
3042 mnemonic_chars
[c
] = c
;
3043 operand_chars
[c
] = c
;
3046 if (ISALPHA (c
) || ISDIGIT (c
))
3047 identifier_chars
[c
] = c
;
3050 identifier_chars
[c
] = c
;
3051 operand_chars
[c
] = c
;
3056 identifier_chars
['@'] = '@';
3059 identifier_chars
['?'] = '?';
3060 operand_chars
['?'] = '?';
3062 digit_chars
['-'] = '-';
3063 mnemonic_chars
['_'] = '_';
3064 mnemonic_chars
['-'] = '-';
3065 mnemonic_chars
['.'] = '.';
3066 identifier_chars
['_'] = '_';
3067 identifier_chars
['.'] = '.';
3069 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
3070 operand_chars
[(unsigned char) *p
] = *p
;
3073 if (flag_code
== CODE_64BIT
)
3075 #if defined (OBJ_COFF) && defined (TE_PE)
3076 x86_dwarf2_return_column
= (OUTPUT_FLAVOR
== bfd_target_coff_flavour
3079 x86_dwarf2_return_column
= 16;
3081 x86_cie_data_alignment
= -8;
3085 x86_dwarf2_return_column
= 8;
3086 x86_cie_data_alignment
= -4;
3089 /* NB: FUSED_JCC_PADDING frag must have sufficient room so that it
3090 can be turned into BRANCH_PREFIX frag. */
3091 if (align_branch_prefix_size
> MAX_FUSED_JCC_PADDING_SIZE
)
3096 i386_print_statistics (FILE *file
)
3098 hash_print_statistics (file
, "i386 opcode", op_hash
);
3099 hash_print_statistics (file
, "i386 register", reg_hash
);
3104 /* Debugging routines for md_assemble. */
3105 static void pte (insn_template
*);
3106 static void pt (i386_operand_type
);
3107 static void pe (expressionS
*);
3108 static void ps (symbolS
*);
3111 pi (const char *line
, i386_insn
*x
)
3115 fprintf (stdout
, "%s: template ", line
);
3117 fprintf (stdout
, " address: base %s index %s scale %x\n",
3118 x
->base_reg
? x
->base_reg
->reg_name
: "none",
3119 x
->index_reg
? x
->index_reg
->reg_name
: "none",
3120 x
->log2_scale_factor
);
3121 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
3122 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
3123 fprintf (stdout
, " sib: base %x index %x scale %x\n",
3124 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
3125 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
3126 (x
->rex
& REX_W
) != 0,
3127 (x
->rex
& REX_R
) != 0,
3128 (x
->rex
& REX_X
) != 0,
3129 (x
->rex
& REX_B
) != 0);
3130 for (j
= 0; j
< x
->operands
; j
++)
3132 fprintf (stdout
, " #%d: ", j
+ 1);
3134 fprintf (stdout
, "\n");
3135 if (x
->types
[j
].bitfield
.class == Reg
3136 || x
->types
[j
].bitfield
.class == RegMMX
3137 || x
->types
[j
].bitfield
.class == RegSIMD
3138 || x
->types
[j
].bitfield
.class == SReg
3139 || x
->types
[j
].bitfield
.class == RegCR
3140 || x
->types
[j
].bitfield
.class == RegDR
3141 || x
->types
[j
].bitfield
.class == RegTR
)
3142 fprintf (stdout
, "%s\n", x
->op
[j
].regs
->reg_name
);
3143 if (operand_type_check (x
->types
[j
], imm
))
3145 if (operand_type_check (x
->types
[j
], disp
))
3146 pe (x
->op
[j
].disps
);
3151 pte (insn_template
*t
)
3154 fprintf (stdout
, " %d operands ", t
->operands
);
3155 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
3156 if (t
->extension_opcode
!= None
)
3157 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
3158 if (t
->opcode_modifier
.d
)
3159 fprintf (stdout
, "D");
3160 if (t
->opcode_modifier
.w
)
3161 fprintf (stdout
, "W");
3162 fprintf (stdout
, "\n");
3163 for (j
= 0; j
< t
->operands
; j
++)
3165 fprintf (stdout
, " #%d type ", j
+ 1);
3166 pt (t
->operand_types
[j
]);
3167 fprintf (stdout
, "\n");
3174 fprintf (stdout
, " operation %d\n", e
->X_op
);
3175 fprintf (stdout
, " add_number %ld (%lx)\n",
3176 (long) e
->X_add_number
, (long) e
->X_add_number
);
3177 if (e
->X_add_symbol
)
3179 fprintf (stdout
, " add_symbol ");
3180 ps (e
->X_add_symbol
);
3181 fprintf (stdout
, "\n");
3185 fprintf (stdout
, " op_symbol ");
3186 ps (e
->X_op_symbol
);
3187 fprintf (stdout
, "\n");
3194 fprintf (stdout
, "%s type %s%s",
3196 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
3197 segment_name (S_GET_SEGMENT (s
)));
3200 static struct type_name
3202 i386_operand_type mask
;
3205 const type_names
[] =
3207 { OPERAND_TYPE_REG8
, "r8" },
3208 { OPERAND_TYPE_REG16
, "r16" },
3209 { OPERAND_TYPE_REG32
, "r32" },
3210 { OPERAND_TYPE_REG64
, "r64" },
3211 { OPERAND_TYPE_ACC8
, "acc8" },
3212 { OPERAND_TYPE_ACC16
, "acc16" },
3213 { OPERAND_TYPE_ACC32
, "acc32" },
3214 { OPERAND_TYPE_ACC64
, "acc64" },
3215 { OPERAND_TYPE_IMM8
, "i8" },
3216 { OPERAND_TYPE_IMM8
, "i8s" },
3217 { OPERAND_TYPE_IMM16
, "i16" },
3218 { OPERAND_TYPE_IMM32
, "i32" },
3219 { OPERAND_TYPE_IMM32S
, "i32s" },
3220 { OPERAND_TYPE_IMM64
, "i64" },
3221 { OPERAND_TYPE_IMM1
, "i1" },
3222 { OPERAND_TYPE_BASEINDEX
, "BaseIndex" },
3223 { OPERAND_TYPE_DISP8
, "d8" },
3224 { OPERAND_TYPE_DISP16
, "d16" },
3225 { OPERAND_TYPE_DISP32
, "d32" },
3226 { OPERAND_TYPE_DISP32S
, "d32s" },
3227 { OPERAND_TYPE_DISP64
, "d64" },
3228 { OPERAND_TYPE_INOUTPORTREG
, "InOutPortReg" },
3229 { OPERAND_TYPE_SHIFTCOUNT
, "ShiftCount" },
3230 { OPERAND_TYPE_CONTROL
, "control reg" },
3231 { OPERAND_TYPE_TEST
, "test reg" },
3232 { OPERAND_TYPE_DEBUG
, "debug reg" },
3233 { OPERAND_TYPE_FLOATREG
, "FReg" },
3234 { OPERAND_TYPE_FLOATACC
, "FAcc" },
3235 { OPERAND_TYPE_SREG
, "SReg" },
3236 { OPERAND_TYPE_REGMMX
, "rMMX" },
3237 { OPERAND_TYPE_REGXMM
, "rXMM" },
3238 { OPERAND_TYPE_REGYMM
, "rYMM" },
3239 { OPERAND_TYPE_REGZMM
, "rZMM" },
3240 { OPERAND_TYPE_REGMASK
, "Mask reg" },
3244 pt (i386_operand_type t
)
3247 i386_operand_type a
;
3249 for (j
= 0; j
< ARRAY_SIZE (type_names
); j
++)
3251 a
= operand_type_and (t
, type_names
[j
].mask
);
3252 if (operand_type_equal (&a
, &type_names
[j
].mask
))
3253 fprintf (stdout
, "%s, ", type_names
[j
].name
);
3258 #endif /* DEBUG386 */
3260 static bfd_reloc_code_real_type
3261 reloc (unsigned int size
,
3264 bfd_reloc_code_real_type other
)
3266 if (other
!= NO_RELOC
)
3268 reloc_howto_type
*rel
;
3273 case BFD_RELOC_X86_64_GOT32
:
3274 return BFD_RELOC_X86_64_GOT64
;
3276 case BFD_RELOC_X86_64_GOTPLT64
:
3277 return BFD_RELOC_X86_64_GOTPLT64
;
3279 case BFD_RELOC_X86_64_PLTOFF64
:
3280 return BFD_RELOC_X86_64_PLTOFF64
;
3282 case BFD_RELOC_X86_64_GOTPC32
:
3283 other
= BFD_RELOC_X86_64_GOTPC64
;
3285 case BFD_RELOC_X86_64_GOTPCREL
:
3286 other
= BFD_RELOC_X86_64_GOTPCREL64
;
3288 case BFD_RELOC_X86_64_TPOFF32
:
3289 other
= BFD_RELOC_X86_64_TPOFF64
;
3291 case BFD_RELOC_X86_64_DTPOFF32
:
3292 other
= BFD_RELOC_X86_64_DTPOFF64
;
3298 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3299 if (other
== BFD_RELOC_SIZE32
)
3302 other
= BFD_RELOC_SIZE64
;
3305 as_bad (_("there are no pc-relative size relocations"));
3311 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
3312 if (size
== 4 && (flag_code
!= CODE_64BIT
|| disallow_64bit_reloc
))
3315 rel
= bfd_reloc_type_lookup (stdoutput
, other
);
3317 as_bad (_("unknown relocation (%u)"), other
);
3318 else if (size
!= bfd_get_reloc_size (rel
))
3319 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
3320 bfd_get_reloc_size (rel
),
3322 else if (pcrel
&& !rel
->pc_relative
)
3323 as_bad (_("non-pc-relative relocation for pc-relative field"));
3324 else if ((rel
->complain_on_overflow
== complain_overflow_signed
3326 || (rel
->complain_on_overflow
== complain_overflow_unsigned
3328 as_bad (_("relocated field and relocation type differ in signedness"));
3337 as_bad (_("there are no unsigned pc-relative relocations"));
3340 case 1: return BFD_RELOC_8_PCREL
;
3341 case 2: return BFD_RELOC_16_PCREL
;
3342 case 4: return BFD_RELOC_32_PCREL
;
3343 case 8: return BFD_RELOC_64_PCREL
;
3345 as_bad (_("cannot do %u byte pc-relative relocation"), size
);
3352 case 4: return BFD_RELOC_X86_64_32S
;
3357 case 1: return BFD_RELOC_8
;
3358 case 2: return BFD_RELOC_16
;
3359 case 4: return BFD_RELOC_32
;
3360 case 8: return BFD_RELOC_64
;
3362 as_bad (_("cannot do %s %u byte relocation"),
3363 sign
> 0 ? "signed" : "unsigned", size
);
3369 /* Here we decide which fixups can be adjusted to make them relative to
3370 the beginning of the section instead of the symbol. Basically we need
3371 to make sure that the dynamic relocations are done correctly, so in
3372 some cases we force the original symbol to be used. */
3375 tc_i386_fix_adjustable (fixS
*fixP ATTRIBUTE_UNUSED
)
3377 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3381 /* Don't adjust pc-relative references to merge sections in 64-bit
3383 if (use_rela_relocations
3384 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
3388 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
3389 and changed later by validate_fix. */
3390 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
3391 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
3394 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
3395 for size relocations. */
3396 if (fixP
->fx_r_type
== BFD_RELOC_SIZE32
3397 || fixP
->fx_r_type
== BFD_RELOC_SIZE64
3398 || fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
3399 || fixP
->fx_r_type
== BFD_RELOC_386_PLT32
3400 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
3401 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32X
3402 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
3403 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
3404 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
3405 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
3406 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
3407 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
3408 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
3409 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
3410 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTDESC
3411 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_DESC_CALL
3412 || fixP
->fx_r_type
== BFD_RELOC_X86_64_PLT32
3413 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
3414 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
3415 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCRELX
3416 || fixP
->fx_r_type
== BFD_RELOC_X86_64_REX_GOTPCRELX
3417 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
3418 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
3419 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
3420 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
3421 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
3422 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
3423 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
3424 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
3425 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPC32_TLSDESC
3426 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSDESC_CALL
3427 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
3428 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
3435 intel_float_operand (const char *mnemonic
)
3437 /* Note that the value returned is meaningful only for opcodes with (memory)
3438 operands, hence the code here is free to improperly handle opcodes that
3439 have no operands (for better performance and smaller code). */
3441 if (mnemonic
[0] != 'f')
3442 return 0; /* non-math */
3444 switch (mnemonic
[1])
3446 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
3447 the fs segment override prefix not currently handled because no
3448 call path can make opcodes without operands get here */
3450 return 2 /* integer op */;
3452 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
3453 return 3; /* fldcw/fldenv */
3456 if (mnemonic
[2] != 'o' /* fnop */)
3457 return 3; /* non-waiting control op */
3460 if (mnemonic
[2] == 's')
3461 return 3; /* frstor/frstpm */
3464 if (mnemonic
[2] == 'a')
3465 return 3; /* fsave */
3466 if (mnemonic
[2] == 't')
3468 switch (mnemonic
[3])
3470 case 'c': /* fstcw */
3471 case 'd': /* fstdw */
3472 case 'e': /* fstenv */
3473 case 's': /* fsts[gw] */
3479 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
3480 return 0; /* fxsave/fxrstor are not really math ops */
3487 /* Build the VEX prefix. */
3490 build_vex_prefix (const insn_template
*t
)
3492 unsigned int register_specifier
;
3493 unsigned int implied_prefix
;
3494 unsigned int vector_length
;
3497 /* Check register specifier. */
3498 if (i
.vex
.register_specifier
)
3500 register_specifier
=
3501 ~register_number (i
.vex
.register_specifier
) & 0xf;
3502 gas_assert ((i
.vex
.register_specifier
->reg_flags
& RegVRex
) == 0);
3505 register_specifier
= 0xf;
3507 /* Use 2-byte VEX prefix by swapping destination and source operand
3508 if there are more than 1 register operand. */
3509 if (i
.reg_operands
> 1
3510 && i
.vec_encoding
!= vex_encoding_vex3
3511 && i
.dir_encoding
== dir_encoding_default
3512 && i
.operands
== i
.reg_operands
3513 && operand_type_equal (&i
.types
[0], &i
.types
[i
.operands
- 1])
3514 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3515 && (i
.tm
.opcode_modifier
.load
|| i
.tm
.opcode_modifier
.d
)
3518 unsigned int xchg
= i
.operands
- 1;
3519 union i386_op temp_op
;
3520 i386_operand_type temp_type
;
3522 temp_type
= i
.types
[xchg
];
3523 i
.types
[xchg
] = i
.types
[0];
3524 i
.types
[0] = temp_type
;
3525 temp_op
= i
.op
[xchg
];
3526 i
.op
[xchg
] = i
.op
[0];
3529 gas_assert (i
.rm
.mode
== 3);
3533 i
.rm
.regmem
= i
.rm
.reg
;
3536 if (i
.tm
.opcode_modifier
.d
)
3537 i
.tm
.base_opcode
^= (i
.tm
.base_opcode
& 0xee) != 0x6e
3538 ? Opcode_SIMD_FloatD
: Opcode_SIMD_IntD
;
3539 else /* Use the next insn. */
3543 /* Use 2-byte VEX prefix by swapping commutative source operands if there
3544 are no memory operands and at least 3 register ones. */
3545 if (i
.reg_operands
>= 3
3546 && i
.vec_encoding
!= vex_encoding_vex3
3547 && i
.reg_operands
== i
.operands
- i
.imm_operands
3548 && i
.tm
.opcode_modifier
.vex
3549 && i
.tm
.opcode_modifier
.commutative
3550 && (i
.tm
.opcode_modifier
.sse2avx
|| optimize
> 1)
3552 && i
.vex
.register_specifier
3553 && !(i
.vex
.register_specifier
->reg_flags
& RegRex
))
3555 unsigned int xchg
= i
.operands
- i
.reg_operands
;
3556 union i386_op temp_op
;
3557 i386_operand_type temp_type
;
3559 gas_assert (i
.tm
.opcode_modifier
.vexopcode
== VEX0F
);
3560 gas_assert (!i
.tm
.opcode_modifier
.sae
);
3561 gas_assert (operand_type_equal (&i
.types
[i
.operands
- 2],
3562 &i
.types
[i
.operands
- 3]));
3563 gas_assert (i
.rm
.mode
== 3);
3565 temp_type
= i
.types
[xchg
];
3566 i
.types
[xchg
] = i
.types
[xchg
+ 1];
3567 i
.types
[xchg
+ 1] = temp_type
;
3568 temp_op
= i
.op
[xchg
];
3569 i
.op
[xchg
] = i
.op
[xchg
+ 1];
3570 i
.op
[xchg
+ 1] = temp_op
;
3573 xchg
= i
.rm
.regmem
| 8;
3574 i
.rm
.regmem
= ~register_specifier
& 0xf;
3575 gas_assert (!(i
.rm
.regmem
& 8));
3576 i
.vex
.register_specifier
+= xchg
- i
.rm
.regmem
;
3577 register_specifier
= ~xchg
& 0xf;
3580 if (i
.tm
.opcode_modifier
.vex
== VEXScalar
)
3581 vector_length
= avxscalar
;
3582 else if (i
.tm
.opcode_modifier
.vex
== VEX256
)
3588 /* Determine vector length from the last multi-length vector
3591 for (op
= t
->operands
; op
--;)
3592 if (t
->operand_types
[op
].bitfield
.xmmword
3593 && t
->operand_types
[op
].bitfield
.ymmword
3594 && i
.types
[op
].bitfield
.ymmword
)
3601 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3606 case DATA_PREFIX_OPCODE
:
3609 case REPE_PREFIX_OPCODE
:
3612 case REPNE_PREFIX_OPCODE
:
3619 /* Check the REX.W bit and VEXW. */
3620 if (i
.tm
.opcode_modifier
.vexw
== VEXWIG
)
3621 w
= (vexwig
== vexw1
|| (i
.rex
& REX_W
)) ? 1 : 0;
3622 else if (i
.tm
.opcode_modifier
.vexw
)
3623 w
= i
.tm
.opcode_modifier
.vexw
== VEXW1
? 1 : 0;
3625 w
= (flag_code
== CODE_64BIT
? i
.rex
& REX_W
: vexwig
== vexw1
) ? 1 : 0;
3627 /* Use 2-byte VEX prefix if possible. */
3629 && i
.vec_encoding
!= vex_encoding_vex3
3630 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3631 && (i
.rex
& (REX_W
| REX_X
| REX_B
)) == 0)
3633 /* 2-byte VEX prefix. */
3637 i
.vex
.bytes
[0] = 0xc5;
3639 /* Check the REX.R bit. */
3640 r
= (i
.rex
& REX_R
) ? 0 : 1;
3641 i
.vex
.bytes
[1] = (r
<< 7
3642 | register_specifier
<< 3
3643 | vector_length
<< 2
3648 /* 3-byte VEX prefix. */
3653 switch (i
.tm
.opcode_modifier
.vexopcode
)
3657 i
.vex
.bytes
[0] = 0xc4;
3661 i
.vex
.bytes
[0] = 0xc4;
3665 i
.vex
.bytes
[0] = 0xc4;
3669 i
.vex
.bytes
[0] = 0x8f;
3673 i
.vex
.bytes
[0] = 0x8f;
3677 i
.vex
.bytes
[0] = 0x8f;
3683 /* The high 3 bits of the second VEX byte are 1's compliment
3684 of RXB bits from REX. */
3685 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3687 i
.vex
.bytes
[2] = (w
<< 7
3688 | register_specifier
<< 3
3689 | vector_length
<< 2
3694 static INLINE bfd_boolean
3695 is_evex_encoding (const insn_template
*t
)
3697 return t
->opcode_modifier
.evex
|| t
->opcode_modifier
.disp8memshift
3698 || t
->opcode_modifier
.broadcast
|| t
->opcode_modifier
.masking
3699 || t
->opcode_modifier
.sae
;
3702 static INLINE bfd_boolean
3703 is_any_vex_encoding (const insn_template
*t
)
3705 return t
->opcode_modifier
.vex
|| t
->opcode_modifier
.vexopcode
3706 || is_evex_encoding (t
);
3709 /* Build the EVEX prefix. */
3712 build_evex_prefix (void)
3714 unsigned int register_specifier
;
3715 unsigned int implied_prefix
;
3717 rex_byte vrex_used
= 0;
3719 /* Check register specifier. */
3720 if (i
.vex
.register_specifier
)
3722 gas_assert ((i
.vrex
& REX_X
) == 0);
3724 register_specifier
= i
.vex
.register_specifier
->reg_num
;
3725 if ((i
.vex
.register_specifier
->reg_flags
& RegRex
))
3726 register_specifier
+= 8;
3727 /* The upper 16 registers are encoded in the fourth byte of the
3729 if (!(i
.vex
.register_specifier
->reg_flags
& RegVRex
))
3730 i
.vex
.bytes
[3] = 0x8;
3731 register_specifier
= ~register_specifier
& 0xf;
3735 register_specifier
= 0xf;
3737 /* Encode upper 16 vector index register in the fourth byte of
3739 if (!(i
.vrex
& REX_X
))
3740 i
.vex
.bytes
[3] = 0x8;
3745 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3750 case DATA_PREFIX_OPCODE
:
3753 case REPE_PREFIX_OPCODE
:
3756 case REPNE_PREFIX_OPCODE
:
3763 /* 4 byte EVEX prefix. */
3765 i
.vex
.bytes
[0] = 0x62;
3768 switch (i
.tm
.opcode_modifier
.vexopcode
)
3784 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3786 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3788 /* The fifth bit of the second EVEX byte is 1's compliment of the
3789 REX_R bit in VREX. */
3790 if (!(i
.vrex
& REX_R
))
3791 i
.vex
.bytes
[1] |= 0x10;
3795 if ((i
.reg_operands
+ i
.imm_operands
) == i
.operands
)
3797 /* When all operands are registers, the REX_X bit in REX is not
3798 used. We reuse it to encode the upper 16 registers, which is
3799 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3800 as 1's compliment. */
3801 if ((i
.vrex
& REX_B
))
3804 i
.vex
.bytes
[1] &= ~0x40;
3808 /* EVEX instructions shouldn't need the REX prefix. */
3809 i
.vrex
&= ~vrex_used
;
3810 gas_assert (i
.vrex
== 0);
3812 /* Check the REX.W bit and VEXW. */
3813 if (i
.tm
.opcode_modifier
.vexw
== VEXWIG
)
3814 w
= (evexwig
== evexw1
|| (i
.rex
& REX_W
)) ? 1 : 0;
3815 else if (i
.tm
.opcode_modifier
.vexw
)
3816 w
= i
.tm
.opcode_modifier
.vexw
== VEXW1
? 1 : 0;
3818 w
= (flag_code
== CODE_64BIT
? i
.rex
& REX_W
: evexwig
== evexw1
) ? 1 : 0;
3820 /* Encode the U bit. */
3821 implied_prefix
|= 0x4;
3823 /* The third byte of the EVEX prefix. */
3824 i
.vex
.bytes
[2] = (w
<< 7 | register_specifier
<< 3 | implied_prefix
);
3826 /* The fourth byte of the EVEX prefix. */
3827 /* The zeroing-masking bit. */
3828 if (i
.mask
&& i
.mask
->zeroing
)
3829 i
.vex
.bytes
[3] |= 0x80;
3831 /* Don't always set the broadcast bit if there is no RC. */
3834 /* Encode the vector length. */
3835 unsigned int vec_length
;
3837 if (!i
.tm
.opcode_modifier
.evex
3838 || i
.tm
.opcode_modifier
.evex
== EVEXDYN
)
3842 /* Determine vector length from the last multi-length vector
3845 for (op
= i
.operands
; op
--;)
3846 if (i
.tm
.operand_types
[op
].bitfield
.xmmword
3847 + i
.tm
.operand_types
[op
].bitfield
.ymmword
3848 + i
.tm
.operand_types
[op
].bitfield
.zmmword
> 1)
3850 if (i
.types
[op
].bitfield
.zmmword
)
3852 i
.tm
.opcode_modifier
.evex
= EVEX512
;
3855 else if (i
.types
[op
].bitfield
.ymmword
)
3857 i
.tm
.opcode_modifier
.evex
= EVEX256
;
3860 else if (i
.types
[op
].bitfield
.xmmword
)
3862 i
.tm
.opcode_modifier
.evex
= EVEX128
;
3865 else if (i
.broadcast
&& (int) op
== i
.broadcast
->operand
)
3867 switch (i
.broadcast
->bytes
)
3870 i
.tm
.opcode_modifier
.evex
= EVEX512
;
3873 i
.tm
.opcode_modifier
.evex
= EVEX256
;
3876 i
.tm
.opcode_modifier
.evex
= EVEX128
;
3885 if (op
>= MAX_OPERANDS
)
3889 switch (i
.tm
.opcode_modifier
.evex
)
3891 case EVEXLIG
: /* LL' is ignored */
3892 vec_length
= evexlig
<< 5;
3895 vec_length
= 0 << 5;
3898 vec_length
= 1 << 5;
3901 vec_length
= 2 << 5;
3907 i
.vex
.bytes
[3] |= vec_length
;
3908 /* Encode the broadcast bit. */
3910 i
.vex
.bytes
[3] |= 0x10;
3914 if (i
.rounding
->type
!= saeonly
)
3915 i
.vex
.bytes
[3] |= 0x10 | (i
.rounding
->type
<< 5);
3917 i
.vex
.bytes
[3] |= 0x10 | (evexrcig
<< 5);
3920 if (i
.mask
&& i
.mask
->mask
)
3921 i
.vex
.bytes
[3] |= i
.mask
->mask
->reg_num
;
3925 process_immext (void)
3929 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
3930 which is coded in the same place as an 8-bit immediate field
3931 would be. Here we fake an 8-bit immediate operand from the
3932 opcode suffix stored in tm.extension_opcode.
3934 AVX instructions also use this encoding, for some of
3935 3 argument instructions. */
3937 gas_assert (i
.imm_operands
<= 1
3939 || (is_any_vex_encoding (&i
.tm
)
3940 && i
.operands
<= 4)));
3942 exp
= &im_expressions
[i
.imm_operands
++];
3943 i
.op
[i
.operands
].imms
= exp
;
3944 i
.types
[i
.operands
] = imm8
;
3946 exp
->X_op
= O_constant
;
3947 exp
->X_add_number
= i
.tm
.extension_opcode
;
3948 i
.tm
.extension_opcode
= None
;
3955 switch (i
.tm
.opcode_modifier
.hleprefixok
)
3960 as_bad (_("invalid instruction `%s' after `%s'"),
3961 i
.tm
.name
, i
.hle_prefix
);
3964 if (i
.prefix
[LOCK_PREFIX
])
3966 as_bad (_("missing `lock' with `%s'"), i
.hle_prefix
);
3970 case HLEPrefixRelease
:
3971 if (i
.prefix
[HLE_PREFIX
] != XRELEASE_PREFIX_OPCODE
)
3973 as_bad (_("instruction `%s' after `xacquire' not allowed"),
3977 if (i
.mem_operands
== 0 || !(i
.flags
[i
.operands
- 1] & Operand_Mem
))
3979 as_bad (_("memory destination needed for instruction `%s'"
3980 " after `xrelease'"), i
.tm
.name
);
3987 /* Try the shortest encoding by shortening operand size. */
3990 optimize_encoding (void)
3994 if (optimize_for_space
3995 && !is_any_vex_encoding (&i
.tm
)
3996 && i
.reg_operands
== 1
3997 && i
.imm_operands
== 1
3998 && !i
.types
[1].bitfield
.byte
3999 && i
.op
[0].imms
->X_op
== O_constant
4000 && fits_in_imm7 (i
.op
[0].imms
->X_add_number
)
4001 && (i
.tm
.base_opcode
== 0xa8
4002 || (i
.tm
.base_opcode
== 0xf6
4003 && i
.tm
.extension_opcode
== 0x0)))
4006 test $imm7, %r64/%r32/%r16 -> test $imm7, %r8
4008 unsigned int base_regnum
= i
.op
[1].regs
->reg_num
;
4009 if (flag_code
== CODE_64BIT
|| base_regnum
< 4)
4011 i
.types
[1].bitfield
.byte
= 1;
4012 /* Ignore the suffix. */
4014 /* Convert to byte registers. */
4015 if (i
.types
[1].bitfield
.word
)
4017 else if (i
.types
[1].bitfield
.dword
)
4021 if (!(i
.op
[1].regs
->reg_flags
& RegRex
) && base_regnum
< 4)
4026 else if (flag_code
== CODE_64BIT
4027 && !is_any_vex_encoding (&i
.tm
)
4028 && ((i
.types
[1].bitfield
.qword
4029 && i
.reg_operands
== 1
4030 && i
.imm_operands
== 1
4031 && i
.op
[0].imms
->X_op
== O_constant
4032 && ((i
.tm
.base_opcode
== 0xb8
4033 && i
.tm
.extension_opcode
== None
4034 && fits_in_unsigned_long (i
.op
[0].imms
->X_add_number
))
4035 || (fits_in_imm31 (i
.op
[0].imms
->X_add_number
)
4036 && ((i
.tm
.base_opcode
== 0x24
4037 || i
.tm
.base_opcode
== 0xa8)
4038 || (i
.tm
.base_opcode
== 0x80
4039 && i
.tm
.extension_opcode
== 0x4)
4040 || ((i
.tm
.base_opcode
== 0xf6
4041 || (i
.tm
.base_opcode
| 1) == 0xc7)
4042 && i
.tm
.extension_opcode
== 0x0)))
4043 || (fits_in_imm7 (i
.op
[0].imms
->X_add_number
)
4044 && i
.tm
.base_opcode
== 0x83
4045 && i
.tm
.extension_opcode
== 0x4)))
4046 || (i
.types
[0].bitfield
.qword
4047 && ((i
.reg_operands
== 2
4048 && i
.op
[0].regs
== i
.op
[1].regs
4049 && (i
.tm
.base_opcode
== 0x30
4050 || i
.tm
.base_opcode
== 0x28))
4051 || (i
.reg_operands
== 1
4053 && i
.tm
.base_opcode
== 0x30)))))
4056 andq $imm31, %r64 -> andl $imm31, %r32
4057 andq $imm7, %r64 -> andl $imm7, %r32
4058 testq $imm31, %r64 -> testl $imm31, %r32
4059 xorq %r64, %r64 -> xorl %r32, %r32
4060 subq %r64, %r64 -> subl %r32, %r32
4061 movq $imm31, %r64 -> movl $imm31, %r32
4062 movq $imm32, %r64 -> movl $imm32, %r32
4064 i
.tm
.opcode_modifier
.norex64
= 1;
4065 if (i
.tm
.base_opcode
== 0xb8 || (i
.tm
.base_opcode
| 1) == 0xc7)
4068 movq $imm31, %r64 -> movl $imm31, %r32
4069 movq $imm32, %r64 -> movl $imm32, %r32
4071 i
.tm
.operand_types
[0].bitfield
.imm32
= 1;
4072 i
.tm
.operand_types
[0].bitfield
.imm32s
= 0;
4073 i
.tm
.operand_types
[0].bitfield
.imm64
= 0;
4074 i
.types
[0].bitfield
.imm32
= 1;
4075 i
.types
[0].bitfield
.imm32s
= 0;
4076 i
.types
[0].bitfield
.imm64
= 0;
4077 i
.types
[1].bitfield
.dword
= 1;
4078 i
.types
[1].bitfield
.qword
= 0;
4079 if ((i
.tm
.base_opcode
| 1) == 0xc7)
4082 movq $imm31, %r64 -> movl $imm31, %r32
4084 i
.tm
.base_opcode
= 0xb8;
4085 i
.tm
.extension_opcode
= None
;
4086 i
.tm
.opcode_modifier
.w
= 0;
4087 i
.tm
.opcode_modifier
.modrm
= 0;
4091 else if (optimize
> 1
4092 && !optimize_for_space
4093 && !is_any_vex_encoding (&i
.tm
)
4094 && i
.reg_operands
== 2
4095 && i
.op
[0].regs
== i
.op
[1].regs
4096 && ((i
.tm
.base_opcode
& ~(Opcode_D
| 1)) == 0x8
4097 || (i
.tm
.base_opcode
& ~(Opcode_D
| 1)) == 0x20)
4098 && (flag_code
!= CODE_64BIT
|| !i
.types
[0].bitfield
.dword
))
4101 andb %rN, %rN -> testb %rN, %rN
4102 andw %rN, %rN -> testw %rN, %rN
4103 andq %rN, %rN -> testq %rN, %rN
4104 orb %rN, %rN -> testb %rN, %rN
4105 orw %rN, %rN -> testw %rN, %rN
4106 orq %rN, %rN -> testq %rN, %rN
4108 and outside of 64-bit mode
4110 andl %rN, %rN -> testl %rN, %rN
4111 orl %rN, %rN -> testl %rN, %rN
4113 i
.tm
.base_opcode
= 0x84 | (i
.tm
.base_opcode
& 1);
4115 else if (i
.reg_operands
== 3
4116 && i
.op
[0].regs
== i
.op
[1].regs
4117 && !i
.types
[2].bitfield
.xmmword
4118 && (i
.tm
.opcode_modifier
.vex
4119 || ((!i
.mask
|| i
.mask
->zeroing
)
4121 && is_evex_encoding (&i
.tm
)
4122 && (i
.vec_encoding
!= vex_encoding_evex
4123 || cpu_arch_isa_flags
.bitfield
.cpuavx512vl
4124 || i
.tm
.cpu_flags
.bitfield
.cpuavx512vl
4125 || (i
.tm
.operand_types
[2].bitfield
.zmmword
4126 && i
.types
[2].bitfield
.ymmword
))))
4127 && ((i
.tm
.base_opcode
== 0x55
4128 || i
.tm
.base_opcode
== 0x6655
4129 || i
.tm
.base_opcode
== 0x66df
4130 || i
.tm
.base_opcode
== 0x57
4131 || i
.tm
.base_opcode
== 0x6657
4132 || i
.tm
.base_opcode
== 0x66ef
4133 || i
.tm
.base_opcode
== 0x66f8
4134 || i
.tm
.base_opcode
== 0x66f9
4135 || i
.tm
.base_opcode
== 0x66fa
4136 || i
.tm
.base_opcode
== 0x66fb
4137 || i
.tm
.base_opcode
== 0x42
4138 || i
.tm
.base_opcode
== 0x6642
4139 || i
.tm
.base_opcode
== 0x47
4140 || i
.tm
.base_opcode
== 0x6647)
4141 && i
.tm
.extension_opcode
== None
))
4144 VOP, one of vandnps, vandnpd, vxorps, vxorpd, vpsubb, vpsubd,
4146 EVEX VOP %zmmM, %zmmM, %zmmN
4147 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
4148 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4149 EVEX VOP %ymmM, %ymmM, %ymmN
4150 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
4151 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4152 VEX VOP %ymmM, %ymmM, %ymmN
4153 -> VEX VOP %xmmM, %xmmM, %xmmN
4154 VOP, one of vpandn and vpxor:
4155 VEX VOP %ymmM, %ymmM, %ymmN
4156 -> VEX VOP %xmmM, %xmmM, %xmmN
4157 VOP, one of vpandnd and vpandnq:
4158 EVEX VOP %zmmM, %zmmM, %zmmN
4159 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
4160 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4161 EVEX VOP %ymmM, %ymmM, %ymmN
4162 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
4163 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4164 VOP, one of vpxord and vpxorq:
4165 EVEX VOP %zmmM, %zmmM, %zmmN
4166 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
4167 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4168 EVEX VOP %ymmM, %ymmM, %ymmN
4169 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
4170 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4171 VOP, one of kxord and kxorq:
4172 VEX VOP %kM, %kM, %kN
4173 -> VEX kxorw %kM, %kM, %kN
4174 VOP, one of kandnd and kandnq:
4175 VEX VOP %kM, %kM, %kN
4176 -> VEX kandnw %kM, %kM, %kN
4178 if (is_evex_encoding (&i
.tm
))
4180 if (i
.vec_encoding
!= vex_encoding_evex
)
4182 i
.tm
.opcode_modifier
.vex
= VEX128
;
4183 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4184 i
.tm
.opcode_modifier
.evex
= 0;
4186 else if (optimize
> 1)
4187 i
.tm
.opcode_modifier
.evex
= EVEX128
;
4191 else if (i
.tm
.operand_types
[0].bitfield
.class == RegMask
)
4193 i
.tm
.base_opcode
&= 0xff;
4194 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4197 i
.tm
.opcode_modifier
.vex
= VEX128
;
4199 if (i
.tm
.opcode_modifier
.vex
)
4200 for (j
= 0; j
< 3; j
++)
4202 i
.types
[j
].bitfield
.xmmword
= 1;
4203 i
.types
[j
].bitfield
.ymmword
= 0;
4206 else if (i
.vec_encoding
!= vex_encoding_evex
4207 && !i
.types
[0].bitfield
.zmmword
4208 && !i
.types
[1].bitfield
.zmmword
4211 && is_evex_encoding (&i
.tm
)
4212 && ((i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0x666f
4213 || (i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0xf36f
4214 || (i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0xf26f
4215 || (i
.tm
.base_opcode
& ~4) == 0x66db
4216 || (i
.tm
.base_opcode
& ~4) == 0x66eb)
4217 && i
.tm
.extension_opcode
== None
)
4220 VOP, one of vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16,
4221 vmovdqu32 and vmovdqu64:
4222 EVEX VOP %xmmM, %xmmN
4223 -> VEX vmovdqa|vmovdqu %xmmM, %xmmN (M and N < 16)
4224 EVEX VOP %ymmM, %ymmN
4225 -> VEX vmovdqa|vmovdqu %ymmM, %ymmN (M and N < 16)
4227 -> VEX vmovdqa|vmovdqu %xmmM, mem (M < 16)
4229 -> VEX vmovdqa|vmovdqu %ymmM, mem (M < 16)
4231 -> VEX mvmovdqa|vmovdquem, %xmmN (N < 16)
4233 -> VEX vmovdqa|vmovdqu mem, %ymmN (N < 16)
4234 VOP, one of vpand, vpandn, vpor, vpxor:
4235 EVEX VOP{d,q} %xmmL, %xmmM, %xmmN
4236 -> VEX VOP %xmmL, %xmmM, %xmmN (L, M, and N < 16)
4237 EVEX VOP{d,q} %ymmL, %ymmM, %ymmN
4238 -> VEX VOP %ymmL, %ymmM, %ymmN (L, M, and N < 16)
4239 EVEX VOP{d,q} mem, %xmmM, %xmmN
4240 -> VEX VOP mem, %xmmM, %xmmN (M and N < 16)
4241 EVEX VOP{d,q} mem, %ymmM, %ymmN
4242 -> VEX VOP mem, %ymmM, %ymmN (M and N < 16)
4244 for (j
= 0; j
< i
.operands
; j
++)
4245 if (operand_type_check (i
.types
[j
], disp
)
4246 && i
.op
[j
].disps
->X_op
== O_constant
)
4248 /* Since the VEX prefix has 2 or 3 bytes, the EVEX prefix
4249 has 4 bytes, EVEX Disp8 has 1 byte and VEX Disp32 has 4
4250 bytes, we choose EVEX Disp8 over VEX Disp32. */
4251 int evex_disp8
, vex_disp8
;
4252 unsigned int memshift
= i
.memshift
;
4253 offsetT n
= i
.op
[j
].disps
->X_add_number
;
4255 evex_disp8
= fits_in_disp8 (n
);
4257 vex_disp8
= fits_in_disp8 (n
);
4258 if (evex_disp8
!= vex_disp8
)
4260 i
.memshift
= memshift
;
4264 i
.types
[j
].bitfield
.disp8
= vex_disp8
;
4267 if ((i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0xf26f)
4268 i
.tm
.base_opcode
^= 0xf36f ^ 0xf26f;
4269 i
.tm
.opcode_modifier
.vex
4270 = i
.types
[0].bitfield
.ymmword
? VEX256
: VEX128
;
4271 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4272 /* VPAND, VPOR, and VPXOR are commutative. */
4273 if (i
.reg_operands
== 3 && i
.tm
.base_opcode
!= 0x66df)
4274 i
.tm
.opcode_modifier
.commutative
= 1;
4275 i
.tm
.opcode_modifier
.evex
= 0;
4276 i
.tm
.opcode_modifier
.masking
= 0;
4277 i
.tm
.opcode_modifier
.broadcast
= 0;
4278 i
.tm
.opcode_modifier
.disp8memshift
= 0;
4281 i
.types
[j
].bitfield
.disp8
4282 = fits_in_disp8 (i
.op
[j
].disps
->X_add_number
);
4286 /* This is the guts of the machine-dependent assembler. LINE points to a
4287 machine dependent instruction. This function is supposed to emit
4288 the frags/bytes it assembles to. */
4291 md_assemble (char *line
)
4294 char mnemonic
[MAX_MNEM_SIZE
], mnem_suffix
;
4295 const insn_template
*t
;
4297 /* Initialize globals. */
4298 memset (&i
, '\0', sizeof (i
));
4299 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4300 i
.reloc
[j
] = NO_RELOC
;
4301 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
4302 memset (im_expressions
, '\0', sizeof (im_expressions
));
4303 save_stack_p
= save_stack
;
4305 /* First parse an instruction mnemonic & call i386_operand for the operands.
4306 We assume that the scrubber has arranged it so that line[0] is the valid
4307 start of a (possibly prefixed) mnemonic. */
4309 line
= parse_insn (line
, mnemonic
);
4312 mnem_suffix
= i
.suffix
;
4314 line
= parse_operands (line
, mnemonic
);
4316 xfree (i
.memop1_string
);
4317 i
.memop1_string
= NULL
;
4321 /* Now we've parsed the mnemonic into a set of templates, and have the
4322 operands at hand. */
4324 /* All intel opcodes have reversed operands except for "bound" and
4325 "enter". We also don't reverse intersegment "jmp" and "call"
4326 instructions with 2 immediate operands so that the immediate segment
4327 precedes the offset, as it does when in AT&T mode. */
4330 && (strcmp (mnemonic
, "bound") != 0)
4331 && (strcmp (mnemonic
, "invlpga") != 0)
4332 && !(operand_type_check (i
.types
[0], imm
)
4333 && operand_type_check (i
.types
[1], imm
)))
4336 /* The order of the immediates should be reversed
4337 for 2 immediates extrq and insertq instructions */
4338 if (i
.imm_operands
== 2
4339 && (strcmp (mnemonic
, "extrq") == 0
4340 || strcmp (mnemonic
, "insertq") == 0))
4341 swap_2_operands (0, 1);
4346 /* Don't optimize displacement for movabs since it only takes 64bit
4349 && i
.disp_encoding
!= disp_encoding_32bit
4350 && (flag_code
!= CODE_64BIT
4351 || strcmp (mnemonic
, "movabs") != 0))
4354 /* Next, we find a template that matches the given insn,
4355 making sure the overlap of the given operands types is consistent
4356 with the template operand types. */
4358 if (!(t
= match_template (mnem_suffix
)))
4361 if (sse_check
!= check_none
4362 && !i
.tm
.opcode_modifier
.noavx
4363 && !i
.tm
.cpu_flags
.bitfield
.cpuavx
4364 && !i
.tm
.cpu_flags
.bitfield
.cpuavx512f
4365 && (i
.tm
.cpu_flags
.bitfield
.cpusse
4366 || i
.tm
.cpu_flags
.bitfield
.cpusse2
4367 || i
.tm
.cpu_flags
.bitfield
.cpusse3
4368 || i
.tm
.cpu_flags
.bitfield
.cpussse3
4369 || i
.tm
.cpu_flags
.bitfield
.cpusse4_1
4370 || i
.tm
.cpu_flags
.bitfield
.cpusse4_2
4371 || i
.tm
.cpu_flags
.bitfield
.cpusse4a
4372 || i
.tm
.cpu_flags
.bitfield
.cpupclmul
4373 || i
.tm
.cpu_flags
.bitfield
.cpuaes
4374 || i
.tm
.cpu_flags
.bitfield
.cpusha
4375 || i
.tm
.cpu_flags
.bitfield
.cpugfni
))
4377 (sse_check
== check_warning
4379 : as_bad
) (_("SSE instruction `%s' is used"), i
.tm
.name
);
4382 /* Zap movzx and movsx suffix. The suffix has been set from
4383 "word ptr" or "byte ptr" on the source operand in Intel syntax
4384 or extracted from mnemonic in AT&T syntax. But we'll use
4385 the destination register to choose the suffix for encoding. */
4386 if ((i
.tm
.base_opcode
& ~9) == 0x0fb6)
4388 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
4389 there is no suffix, the default will be byte extension. */
4390 if (i
.reg_operands
!= 2
4393 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
4398 if (i
.tm
.opcode_modifier
.fwait
)
4399 if (!add_prefix (FWAIT_OPCODE
))
4402 /* Check if REP prefix is OK. */
4403 if (i
.rep_prefix
&& !i
.tm
.opcode_modifier
.repprefixok
)
4405 as_bad (_("invalid instruction `%s' after `%s'"),
4406 i
.tm
.name
, i
.rep_prefix
);
4410 /* Check for lock without a lockable instruction. Destination operand
4411 must be memory unless it is xchg (0x86). */
4412 if (i
.prefix
[LOCK_PREFIX
]
4413 && (!i
.tm
.opcode_modifier
.islockable
4414 || i
.mem_operands
== 0
4415 || (i
.tm
.base_opcode
!= 0x86
4416 && !(i
.flags
[i
.operands
- 1] & Operand_Mem
))))
4418 as_bad (_("expecting lockable instruction after `lock'"));
4422 /* Check for data size prefix on VEX/XOP/EVEX encoded insns. */
4423 if (i
.prefix
[DATA_PREFIX
] && is_any_vex_encoding (&i
.tm
))
4425 as_bad (_("data size prefix invalid with `%s'"), i
.tm
.name
);
4429 /* Check if HLE prefix is OK. */
4430 if (i
.hle_prefix
&& !check_hle ())
4433 /* Check BND prefix. */
4434 if (i
.bnd_prefix
&& !i
.tm
.opcode_modifier
.bndprefixok
)
4435 as_bad (_("expecting valid branch instruction after `bnd'"));
4437 /* Check NOTRACK prefix. */
4438 if (i
.notrack_prefix
&& !i
.tm
.opcode_modifier
.notrackprefixok
)
4439 as_bad (_("expecting indirect branch instruction after `notrack'"));
4441 if (i
.tm
.cpu_flags
.bitfield
.cpumpx
)
4443 if (flag_code
== CODE_64BIT
&& i
.prefix
[ADDR_PREFIX
])
4444 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
4445 else if (flag_code
!= CODE_16BIT
4446 ? i
.prefix
[ADDR_PREFIX
]
4447 : i
.mem_operands
&& !i
.prefix
[ADDR_PREFIX
])
4448 as_bad (_("16-bit address isn't allowed in MPX instructions"));
4451 /* Insert BND prefix. */
4452 if (add_bnd_prefix
&& i
.tm
.opcode_modifier
.bndprefixok
)
4454 if (!i
.prefix
[BND_PREFIX
])
4455 add_prefix (BND_PREFIX_OPCODE
);
4456 else if (i
.prefix
[BND_PREFIX
] != BND_PREFIX_OPCODE
)
4458 as_warn (_("replacing `rep'/`repe' prefix by `bnd'"));
4459 i
.prefix
[BND_PREFIX
] = BND_PREFIX_OPCODE
;
4463 /* Check string instruction segment overrides. */
4464 if (i
.tm
.opcode_modifier
.isstring
>= IS_STRING_ES_OP0
)
4466 gas_assert (i
.mem_operands
);
4467 if (!check_string ())
4469 i
.disp_operands
= 0;
4472 if (optimize
&& !i
.no_optimize
&& i
.tm
.opcode_modifier
.optimize
)
4473 optimize_encoding ();
4475 if (!process_suffix ())
4478 /* Update operand types. */
4479 for (j
= 0; j
< i
.operands
; j
++)
4480 i
.types
[j
] = operand_type_and (i
.types
[j
], i
.tm
.operand_types
[j
]);
4482 /* Make still unresolved immediate matches conform to size of immediate
4483 given in i.suffix. */
4484 if (!finalize_imm ())
4487 if (i
.types
[0].bitfield
.imm1
)
4488 i
.imm_operands
= 0; /* kludge for shift insns. */
4490 /* We only need to check those implicit registers for instructions
4491 with 3 operands or less. */
4492 if (i
.operands
<= 3)
4493 for (j
= 0; j
< i
.operands
; j
++)
4494 if (i
.types
[j
].bitfield
.instance
!= InstanceNone
4495 && !i
.types
[j
].bitfield
.xmmword
)
4498 /* ImmExt should be processed after SSE2AVX. */
4499 if (!i
.tm
.opcode_modifier
.sse2avx
4500 && i
.tm
.opcode_modifier
.immext
)
4503 /* For insns with operands there are more diddles to do to the opcode. */
4506 if (!process_operands ())
4509 else if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
4511 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
4512 as_warn (_("translating to `%sp'"), i
.tm
.name
);
4515 if (is_any_vex_encoding (&i
.tm
))
4517 if (!cpu_arch_flags
.bitfield
.cpui286
)
4519 as_bad (_("instruction `%s' isn't supported outside of protected mode."),
4524 if (i
.tm
.opcode_modifier
.vex
)
4525 build_vex_prefix (t
);
4527 build_evex_prefix ();
4530 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
4531 instructions may define INT_OPCODE as well, so avoid this corner
4532 case for those instructions that use MODRM. */
4533 if (i
.tm
.base_opcode
== INT_OPCODE
4534 && !i
.tm
.opcode_modifier
.modrm
4535 && i
.op
[0].imms
->X_add_number
== 3)
4537 i
.tm
.base_opcode
= INT3_OPCODE
;
4541 if ((i
.tm
.opcode_modifier
.jump
== JUMP
4542 || i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
4543 || i
.tm
.opcode_modifier
.jump
== JUMP_DWORD
)
4544 && i
.op
[0].disps
->X_op
== O_constant
)
4546 /* Convert "jmp constant" (and "call constant") to a jump (call) to
4547 the absolute address given by the constant. Since ix86 jumps and
4548 calls are pc relative, we need to generate a reloc. */
4549 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
4550 i
.op
[0].disps
->X_op
= O_symbol
;
4553 if (i
.tm
.opcode_modifier
.rex64
)
4556 /* For 8 bit registers we need an empty rex prefix. Also if the
4557 instruction already has a prefix, we need to convert old
4558 registers to new ones. */
4560 if ((i
.types
[0].bitfield
.class == Reg
&& i
.types
[0].bitfield
.byte
4561 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
4562 || (i
.types
[1].bitfield
.class == Reg
&& i
.types
[1].bitfield
.byte
4563 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
4564 || (((i
.types
[0].bitfield
.class == Reg
&& i
.types
[0].bitfield
.byte
)
4565 || (i
.types
[1].bitfield
.class == Reg
&& i
.types
[1].bitfield
.byte
))
4570 i
.rex
|= REX_OPCODE
;
4571 for (x
= 0; x
< 2; x
++)
4573 /* Look for 8 bit operand that uses old registers. */
4574 if (i
.types
[x
].bitfield
.class == Reg
&& i
.types
[x
].bitfield
.byte
4575 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
4577 gas_assert (!(i
.op
[x
].regs
->reg_flags
& RegRex
));
4578 /* In case it is "hi" register, give up. */
4579 if (i
.op
[x
].regs
->reg_num
> 3)
4580 as_bad (_("can't encode register '%s%s' in an "
4581 "instruction requiring REX prefix."),
4582 register_prefix
, i
.op
[x
].regs
->reg_name
);
4584 /* Otherwise it is equivalent to the extended register.
4585 Since the encoding doesn't change this is merely
4586 cosmetic cleanup for debug output. */
4588 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
4593 if (i
.rex
== 0 && i
.rex_encoding
)
4595 /* Check if we can add a REX_OPCODE byte. Look for 8 bit operand
4596 that uses legacy register. If it is "hi" register, don't add
4597 the REX_OPCODE byte. */
4599 for (x
= 0; x
< 2; x
++)
4600 if (i
.types
[x
].bitfield
.class == Reg
4601 && i
.types
[x
].bitfield
.byte
4602 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0
4603 && i
.op
[x
].regs
->reg_num
> 3)
4605 gas_assert (!(i
.op
[x
].regs
->reg_flags
& RegRex
));
4606 i
.rex_encoding
= FALSE
;
4615 add_prefix (REX_OPCODE
| i
.rex
);
4617 /* We are ready to output the insn. */
4620 last_insn
.seg
= now_seg
;
4622 if (i
.tm
.opcode_modifier
.isprefix
)
4624 last_insn
.kind
= last_insn_prefix
;
4625 last_insn
.name
= i
.tm
.name
;
4626 last_insn
.file
= as_where (&last_insn
.line
);
4629 last_insn
.kind
= last_insn_other
;
4633 parse_insn (char *line
, char *mnemonic
)
4636 char *token_start
= l
;
4639 const insn_template
*t
;
4645 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
4650 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
4652 as_bad (_("no such instruction: `%s'"), token_start
);
4657 if (!is_space_char (*l
)
4658 && *l
!= END_OF_INSN
4660 || (*l
!= PREFIX_SEPARATOR
4663 as_bad (_("invalid character %s in mnemonic"),
4664 output_invalid (*l
));
4667 if (token_start
== l
)
4669 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
4670 as_bad (_("expecting prefix; got nothing"));
4672 as_bad (_("expecting mnemonic; got nothing"));
4676 /* Look up instruction (or prefix) via hash table. */
4677 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
4679 if (*l
!= END_OF_INSN
4680 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
4681 && current_templates
4682 && current_templates
->start
->opcode_modifier
.isprefix
)
4684 if (!cpu_flags_check_cpu64 (current_templates
->start
->cpu_flags
))
4686 as_bad ((flag_code
!= CODE_64BIT
4687 ? _("`%s' is only supported in 64-bit mode")
4688 : _("`%s' is not supported in 64-bit mode")),
4689 current_templates
->start
->name
);
4692 /* If we are in 16-bit mode, do not allow addr16 or data16.
4693 Similarly, in 32-bit mode, do not allow addr32 or data32. */
4694 if ((current_templates
->start
->opcode_modifier
.size
== SIZE16
4695 || current_templates
->start
->opcode_modifier
.size
== SIZE32
)
4696 && flag_code
!= CODE_64BIT
4697 && ((current_templates
->start
->opcode_modifier
.size
== SIZE32
)
4698 ^ (flag_code
== CODE_16BIT
)))
4700 as_bad (_("redundant %s prefix"),
4701 current_templates
->start
->name
);
4704 if (current_templates
->start
->opcode_length
== 0)
4706 /* Handle pseudo prefixes. */
4707 switch (current_templates
->start
->base_opcode
)
4711 i
.disp_encoding
= disp_encoding_8bit
;
4715 i
.disp_encoding
= disp_encoding_32bit
;
4719 i
.dir_encoding
= dir_encoding_load
;
4723 i
.dir_encoding
= dir_encoding_store
;
4727 i
.vec_encoding
= vex_encoding_vex
;
4731 i
.vec_encoding
= vex_encoding_vex3
;
4735 i
.vec_encoding
= vex_encoding_evex
;
4739 i
.rex_encoding
= TRUE
;
4743 i
.no_optimize
= TRUE
;
4751 /* Add prefix, checking for repeated prefixes. */
4752 switch (add_prefix (current_templates
->start
->base_opcode
))
4757 if (current_templates
->start
->cpu_flags
.bitfield
.cpuibt
)
4758 i
.notrack_prefix
= current_templates
->start
->name
;
4761 if (current_templates
->start
->cpu_flags
.bitfield
.cpuhle
)
4762 i
.hle_prefix
= current_templates
->start
->name
;
4763 else if (current_templates
->start
->cpu_flags
.bitfield
.cpumpx
)
4764 i
.bnd_prefix
= current_templates
->start
->name
;
4766 i
.rep_prefix
= current_templates
->start
->name
;
4772 /* Skip past PREFIX_SEPARATOR and reset token_start. */
4779 if (!current_templates
)
4781 /* Deprecated functionality (new code should use pseudo-prefixes instead):
4782 Check if we should swap operand or force 32bit displacement in
4784 if (mnem_p
- 2 == dot_p
&& dot_p
[1] == 's')
4785 i
.dir_encoding
= dir_encoding_swap
;
4786 else if (mnem_p
- 3 == dot_p
4789 i
.disp_encoding
= disp_encoding_8bit
;
4790 else if (mnem_p
- 4 == dot_p
4794 i
.disp_encoding
= disp_encoding_32bit
;
4799 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
4802 if (!current_templates
)
4805 if (mnem_p
> mnemonic
)
4807 /* See if we can get a match by trimming off a suffix. */
4810 case WORD_MNEM_SUFFIX
:
4811 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
4812 i
.suffix
= SHORT_MNEM_SUFFIX
;
4815 case BYTE_MNEM_SUFFIX
:
4816 case QWORD_MNEM_SUFFIX
:
4817 i
.suffix
= mnem_p
[-1];
4819 current_templates
= (const templates
*) hash_find (op_hash
,
4822 case SHORT_MNEM_SUFFIX
:
4823 case LONG_MNEM_SUFFIX
:
4826 i
.suffix
= mnem_p
[-1];
4828 current_templates
= (const templates
*) hash_find (op_hash
,
4837 if (intel_float_operand (mnemonic
) == 1)
4838 i
.suffix
= SHORT_MNEM_SUFFIX
;
4840 i
.suffix
= LONG_MNEM_SUFFIX
;
4842 current_templates
= (const templates
*) hash_find (op_hash
,
4849 if (!current_templates
)
4851 as_bad (_("no such instruction: `%s'"), token_start
);
4856 if (current_templates
->start
->opcode_modifier
.jump
== JUMP
4857 || current_templates
->start
->opcode_modifier
.jump
== JUMP_BYTE
)
4859 /* Check for a branch hint. We allow ",pt" and ",pn" for
4860 predict taken and predict not taken respectively.
4861 I'm not sure that branch hints actually do anything on loop
4862 and jcxz insns (JumpByte) for current Pentium4 chips. They
4863 may work in the future and it doesn't hurt to accept them
4865 if (l
[0] == ',' && l
[1] == 'p')
4869 if (!add_prefix (DS_PREFIX_OPCODE
))
4873 else if (l
[2] == 'n')
4875 if (!add_prefix (CS_PREFIX_OPCODE
))
4881 /* Any other comma loses. */
4884 as_bad (_("invalid character %s in mnemonic"),
4885 output_invalid (*l
));
4889 /* Check if instruction is supported on specified architecture. */
4891 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
4893 supported
|= cpu_flags_match (t
);
4894 if (supported
== CPU_FLAGS_PERFECT_MATCH
)
4896 if (!cpu_arch_flags
.bitfield
.cpui386
&& (flag_code
!= CODE_16BIT
))
4897 as_warn (_("use .code16 to ensure correct addressing mode"));
4903 if (!(supported
& CPU_FLAGS_64BIT_MATCH
))
4904 as_bad (flag_code
== CODE_64BIT
4905 ? _("`%s' is not supported in 64-bit mode")
4906 : _("`%s' is only supported in 64-bit mode"),
4907 current_templates
->start
->name
);
4909 as_bad (_("`%s' is not supported on `%s%s'"),
4910 current_templates
->start
->name
,
4911 cpu_arch_name
? cpu_arch_name
: default_arch
,
4912 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
4918 parse_operands (char *l
, const char *mnemonic
)
4922 /* 1 if operand is pending after ','. */
4923 unsigned int expecting_operand
= 0;
4925 /* Non-zero if operand parens not balanced. */
4926 unsigned int paren_not_balanced
;
4928 while (*l
!= END_OF_INSN
)
4930 /* Skip optional white space before operand. */
4931 if (is_space_char (*l
))
4933 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
&& *l
!= '"')
4935 as_bad (_("invalid character %s before operand %d"),
4936 output_invalid (*l
),
4940 token_start
= l
; /* After white space. */
4941 paren_not_balanced
= 0;
4942 while (paren_not_balanced
|| *l
!= ',')
4944 if (*l
== END_OF_INSN
)
4946 if (paren_not_balanced
)
4949 as_bad (_("unbalanced parenthesis in operand %d."),
4952 as_bad (_("unbalanced brackets in operand %d."),
4957 break; /* we are done */
4959 else if (!is_operand_char (*l
) && !is_space_char (*l
) && *l
!= '"')
4961 as_bad (_("invalid character %s in operand %d"),
4962 output_invalid (*l
),
4969 ++paren_not_balanced
;
4971 --paren_not_balanced
;
4976 ++paren_not_balanced
;
4978 --paren_not_balanced
;
4982 if (l
!= token_start
)
4983 { /* Yes, we've read in another operand. */
4984 unsigned int operand_ok
;
4985 this_operand
= i
.operands
++;
4986 if (i
.operands
> MAX_OPERANDS
)
4988 as_bad (_("spurious operands; (%d operands/instruction max)"),
4992 i
.types
[this_operand
].bitfield
.unspecified
= 1;
4993 /* Now parse operand adding info to 'i' as we go along. */
4994 END_STRING_AND_SAVE (l
);
4996 if (i
.mem_operands
> 1)
4998 as_bad (_("too many memory references for `%s'"),
5005 i386_intel_operand (token_start
,
5006 intel_float_operand (mnemonic
));
5008 operand_ok
= i386_att_operand (token_start
);
5010 RESTORE_END_STRING (l
);
5016 if (expecting_operand
)
5018 expecting_operand_after_comma
:
5019 as_bad (_("expecting operand after ','; got nothing"));
5024 as_bad (_("expecting operand before ','; got nothing"));
5029 /* Now *l must be either ',' or END_OF_INSN. */
5032 if (*++l
== END_OF_INSN
)
5034 /* Just skip it, if it's \n complain. */
5035 goto expecting_operand_after_comma
;
5037 expecting_operand
= 1;
5044 swap_2_operands (int xchg1
, int xchg2
)
5046 union i386_op temp_op
;
5047 i386_operand_type temp_type
;
5048 unsigned int temp_flags
;
5049 enum bfd_reloc_code_real temp_reloc
;
5051 temp_type
= i
.types
[xchg2
];
5052 i
.types
[xchg2
] = i
.types
[xchg1
];
5053 i
.types
[xchg1
] = temp_type
;
5055 temp_flags
= i
.flags
[xchg2
];
5056 i
.flags
[xchg2
] = i
.flags
[xchg1
];
5057 i
.flags
[xchg1
] = temp_flags
;
5059 temp_op
= i
.op
[xchg2
];
5060 i
.op
[xchg2
] = i
.op
[xchg1
];
5061 i
.op
[xchg1
] = temp_op
;
5063 temp_reloc
= i
.reloc
[xchg2
];
5064 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
5065 i
.reloc
[xchg1
] = temp_reloc
;
5069 if (i
.mask
->operand
== xchg1
)
5070 i
.mask
->operand
= xchg2
;
5071 else if (i
.mask
->operand
== xchg2
)
5072 i
.mask
->operand
= xchg1
;
5076 if (i
.broadcast
->operand
== xchg1
)
5077 i
.broadcast
->operand
= xchg2
;
5078 else if (i
.broadcast
->operand
== xchg2
)
5079 i
.broadcast
->operand
= xchg1
;
5083 if (i
.rounding
->operand
== xchg1
)
5084 i
.rounding
->operand
= xchg2
;
5085 else if (i
.rounding
->operand
== xchg2
)
5086 i
.rounding
->operand
= xchg1
;
5091 swap_operands (void)
5097 swap_2_operands (1, i
.operands
- 2);
5101 swap_2_operands (0, i
.operands
- 1);
5107 if (i
.mem_operands
== 2)
5109 const seg_entry
*temp_seg
;
5110 temp_seg
= i
.seg
[0];
5111 i
.seg
[0] = i
.seg
[1];
5112 i
.seg
[1] = temp_seg
;
5116 /* Try to ensure constant immediates are represented in the smallest
5121 char guess_suffix
= 0;
5125 guess_suffix
= i
.suffix
;
5126 else if (i
.reg_operands
)
5128 /* Figure out a suffix from the last register operand specified.
5129 We can't do this properly yet, i.e. excluding special register
5130 instances, but the following works for instructions with
5131 immediates. In any case, we can't set i.suffix yet. */
5132 for (op
= i
.operands
; --op
>= 0;)
5133 if (i
.types
[op
].bitfield
.class != Reg
)
5135 else if (i
.types
[op
].bitfield
.byte
)
5137 guess_suffix
= BYTE_MNEM_SUFFIX
;
5140 else if (i
.types
[op
].bitfield
.word
)
5142 guess_suffix
= WORD_MNEM_SUFFIX
;
5145 else if (i
.types
[op
].bitfield
.dword
)
5147 guess_suffix
= LONG_MNEM_SUFFIX
;
5150 else if (i
.types
[op
].bitfield
.qword
)
5152 guess_suffix
= QWORD_MNEM_SUFFIX
;
5156 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
5157 guess_suffix
= WORD_MNEM_SUFFIX
;
5159 for (op
= i
.operands
; --op
>= 0;)
5160 if (operand_type_check (i
.types
[op
], imm
))
5162 switch (i
.op
[op
].imms
->X_op
)
5165 /* If a suffix is given, this operand may be shortened. */
5166 switch (guess_suffix
)
5168 case LONG_MNEM_SUFFIX
:
5169 i
.types
[op
].bitfield
.imm32
= 1;
5170 i
.types
[op
].bitfield
.imm64
= 1;
5172 case WORD_MNEM_SUFFIX
:
5173 i
.types
[op
].bitfield
.imm16
= 1;
5174 i
.types
[op
].bitfield
.imm32
= 1;
5175 i
.types
[op
].bitfield
.imm32s
= 1;
5176 i
.types
[op
].bitfield
.imm64
= 1;
5178 case BYTE_MNEM_SUFFIX
:
5179 i
.types
[op
].bitfield
.imm8
= 1;
5180 i
.types
[op
].bitfield
.imm8s
= 1;
5181 i
.types
[op
].bitfield
.imm16
= 1;
5182 i
.types
[op
].bitfield
.imm32
= 1;
5183 i
.types
[op
].bitfield
.imm32s
= 1;
5184 i
.types
[op
].bitfield
.imm64
= 1;
5188 /* If this operand is at most 16 bits, convert it
5189 to a signed 16 bit number before trying to see
5190 whether it will fit in an even smaller size.
5191 This allows a 16-bit operand such as $0xffe0 to
5192 be recognised as within Imm8S range. */
5193 if ((i
.types
[op
].bitfield
.imm16
)
5194 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
5196 i
.op
[op
].imms
->X_add_number
=
5197 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
5200 /* Store 32-bit immediate in 64-bit for 64-bit BFD. */
5201 if ((i
.types
[op
].bitfield
.imm32
)
5202 && ((i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1))
5205 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
5206 ^ ((offsetT
) 1 << 31))
5207 - ((offsetT
) 1 << 31));
5211 = operand_type_or (i
.types
[op
],
5212 smallest_imm_type (i
.op
[op
].imms
->X_add_number
));
5214 /* We must avoid matching of Imm32 templates when 64bit
5215 only immediate is available. */
5216 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
5217 i
.types
[op
].bitfield
.imm32
= 0;
5224 /* Symbols and expressions. */
5226 /* Convert symbolic operand to proper sizes for matching, but don't
5227 prevent matching a set of insns that only supports sizes other
5228 than those matching the insn suffix. */
5230 i386_operand_type mask
, allowed
;
5231 const insn_template
*t
;
5233 operand_type_set (&mask
, 0);
5234 operand_type_set (&allowed
, 0);
5236 for (t
= current_templates
->start
;
5237 t
< current_templates
->end
;
5240 allowed
= operand_type_or (allowed
, t
->operand_types
[op
]);
5241 allowed
= operand_type_and (allowed
, anyimm
);
5243 switch (guess_suffix
)
5245 case QWORD_MNEM_SUFFIX
:
5246 mask
.bitfield
.imm64
= 1;
5247 mask
.bitfield
.imm32s
= 1;
5249 case LONG_MNEM_SUFFIX
:
5250 mask
.bitfield
.imm32
= 1;
5252 case WORD_MNEM_SUFFIX
:
5253 mask
.bitfield
.imm16
= 1;
5255 case BYTE_MNEM_SUFFIX
:
5256 mask
.bitfield
.imm8
= 1;
5261 allowed
= operand_type_and (mask
, allowed
);
5262 if (!operand_type_all_zero (&allowed
))
5263 i
.types
[op
] = operand_type_and (i
.types
[op
], mask
);
5270 /* Try to use the smallest displacement type too. */
5272 optimize_disp (void)
5276 for (op
= i
.operands
; --op
>= 0;)
5277 if (operand_type_check (i
.types
[op
], disp
))
5279 if (i
.op
[op
].disps
->X_op
== O_constant
)
5281 offsetT op_disp
= i
.op
[op
].disps
->X_add_number
;
5283 if (i
.types
[op
].bitfield
.disp16
5284 && (op_disp
& ~(offsetT
) 0xffff) == 0)
5286 /* If this operand is at most 16 bits, convert
5287 to a signed 16 bit number and don't use 64bit
5289 op_disp
= (((op_disp
& 0xffff) ^ 0x8000) - 0x8000);
5290 i
.types
[op
].bitfield
.disp64
= 0;
5293 /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */
5294 if (i
.types
[op
].bitfield
.disp32
5295 && (op_disp
& ~(((offsetT
) 2 << 31) - 1)) == 0)
5297 /* If this operand is at most 32 bits, convert
5298 to a signed 32 bit number and don't use 64bit
5300 op_disp
&= (((offsetT
) 2 << 31) - 1);
5301 op_disp
= (op_disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
5302 i
.types
[op
].bitfield
.disp64
= 0;
5305 if (!op_disp
&& i
.types
[op
].bitfield
.baseindex
)
5307 i
.types
[op
].bitfield
.disp8
= 0;
5308 i
.types
[op
].bitfield
.disp16
= 0;
5309 i
.types
[op
].bitfield
.disp32
= 0;
5310 i
.types
[op
].bitfield
.disp32s
= 0;
5311 i
.types
[op
].bitfield
.disp64
= 0;
5315 else if (flag_code
== CODE_64BIT
)
5317 if (fits_in_signed_long (op_disp
))
5319 i
.types
[op
].bitfield
.disp64
= 0;
5320 i
.types
[op
].bitfield
.disp32s
= 1;
5322 if (i
.prefix
[ADDR_PREFIX
]
5323 && fits_in_unsigned_long (op_disp
))
5324 i
.types
[op
].bitfield
.disp32
= 1;
5326 if ((i
.types
[op
].bitfield
.disp32
5327 || i
.types
[op
].bitfield
.disp32s
5328 || i
.types
[op
].bitfield
.disp16
)
5329 && fits_in_disp8 (op_disp
))
5330 i
.types
[op
].bitfield
.disp8
= 1;
5332 else if (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
5333 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
)
5335 fix_new_exp (frag_now
, frag_more (0) - frag_now
->fr_literal
, 0,
5336 i
.op
[op
].disps
, 0, i
.reloc
[op
]);
5337 i
.types
[op
].bitfield
.disp8
= 0;
5338 i
.types
[op
].bitfield
.disp16
= 0;
5339 i
.types
[op
].bitfield
.disp32
= 0;
5340 i
.types
[op
].bitfield
.disp32s
= 0;
5341 i
.types
[op
].bitfield
.disp64
= 0;
5344 /* We only support 64bit displacement on constants. */
5345 i
.types
[op
].bitfield
.disp64
= 0;
5349 /* Return 1 if there is a match in broadcast bytes between operand
5350 GIVEN and instruction template T. */
5353 match_broadcast_size (const insn_template
*t
, unsigned int given
)
5355 return ((t
->opcode_modifier
.broadcast
== BYTE_BROADCAST
5356 && i
.types
[given
].bitfield
.byte
)
5357 || (t
->opcode_modifier
.broadcast
== WORD_BROADCAST
5358 && i
.types
[given
].bitfield
.word
)
5359 || (t
->opcode_modifier
.broadcast
== DWORD_BROADCAST
5360 && i
.types
[given
].bitfield
.dword
)
5361 || (t
->opcode_modifier
.broadcast
== QWORD_BROADCAST
5362 && i
.types
[given
].bitfield
.qword
));
5365 /* Check if operands are valid for the instruction. */
5368 check_VecOperands (const insn_template
*t
)
5372 static const i386_cpu_flags avx512
= CPU_ANY_AVX512F_FLAGS
;
5374 /* Templates allowing for ZMMword as well as YMMword and/or XMMword for
5375 any one operand are implicity requiring AVX512VL support if the actual
5376 operand size is YMMword or XMMword. Since this function runs after
5377 template matching, there's no need to check for YMMword/XMMword in
5379 cpu
= cpu_flags_and (t
->cpu_flags
, avx512
);
5380 if (!cpu_flags_all_zero (&cpu
)
5381 && !t
->cpu_flags
.bitfield
.cpuavx512vl
5382 && !cpu_arch_flags
.bitfield
.cpuavx512vl
)
5384 for (op
= 0; op
< t
->operands
; ++op
)
5386 if (t
->operand_types
[op
].bitfield
.zmmword
5387 && (i
.types
[op
].bitfield
.ymmword
5388 || i
.types
[op
].bitfield
.xmmword
))
5390 i
.error
= unsupported
;
5396 /* Without VSIB byte, we can't have a vector register for index. */
5397 if (!t
->opcode_modifier
.vecsib
5399 && (i
.index_reg
->reg_type
.bitfield
.xmmword
5400 || i
.index_reg
->reg_type
.bitfield
.ymmword
5401 || i
.index_reg
->reg_type
.bitfield
.zmmword
))
5403 i
.error
= unsupported_vector_index_register
;
5407 /* Check if default mask is allowed. */
5408 if (t
->opcode_modifier
.nodefmask
5409 && (!i
.mask
|| i
.mask
->mask
->reg_num
== 0))
5411 i
.error
= no_default_mask
;
5415 /* For VSIB byte, we need a vector register for index, and all vector
5416 registers must be distinct. */
5417 if (t
->opcode_modifier
.vecsib
)
5420 || !((t
->opcode_modifier
.vecsib
== VecSIB128
5421 && i
.index_reg
->reg_type
.bitfield
.xmmword
)
5422 || (t
->opcode_modifier
.vecsib
== VecSIB256
5423 && i
.index_reg
->reg_type
.bitfield
.ymmword
)
5424 || (t
->opcode_modifier
.vecsib
== VecSIB512
5425 && i
.index_reg
->reg_type
.bitfield
.zmmword
)))
5427 i
.error
= invalid_vsib_address
;
5431 gas_assert (i
.reg_operands
== 2 || i
.mask
);
5432 if (i
.reg_operands
== 2 && !i
.mask
)
5434 gas_assert (i
.types
[0].bitfield
.class == RegSIMD
);
5435 gas_assert (i
.types
[0].bitfield
.xmmword
5436 || i
.types
[0].bitfield
.ymmword
);
5437 gas_assert (i
.types
[2].bitfield
.class == RegSIMD
);
5438 gas_assert (i
.types
[2].bitfield
.xmmword
5439 || i
.types
[2].bitfield
.ymmword
);
5440 if (operand_check
== check_none
)
5442 if (register_number (i
.op
[0].regs
)
5443 != register_number (i
.index_reg
)
5444 && register_number (i
.op
[2].regs
)
5445 != register_number (i
.index_reg
)
5446 && register_number (i
.op
[0].regs
)
5447 != register_number (i
.op
[2].regs
))
5449 if (operand_check
== check_error
)
5451 i
.error
= invalid_vector_register_set
;
5454 as_warn (_("mask, index, and destination registers should be distinct"));
5456 else if (i
.reg_operands
== 1 && i
.mask
)
5458 if (i
.types
[1].bitfield
.class == RegSIMD
5459 && (i
.types
[1].bitfield
.xmmword
5460 || i
.types
[1].bitfield
.ymmword
5461 || i
.types
[1].bitfield
.zmmword
)
5462 && (register_number (i
.op
[1].regs
)
5463 == register_number (i
.index_reg
)))
5465 if (operand_check
== check_error
)
5467 i
.error
= invalid_vector_register_set
;
5470 if (operand_check
!= check_none
)
5471 as_warn (_("index and destination registers should be distinct"));
5476 /* Check if broadcast is supported by the instruction and is applied
5477 to the memory operand. */
5480 i386_operand_type type
, overlap
;
5482 /* Check if specified broadcast is supported in this instruction,
5483 and its broadcast bytes match the memory operand. */
5484 op
= i
.broadcast
->operand
;
5485 if (!t
->opcode_modifier
.broadcast
5486 || !(i
.flags
[op
] & Operand_Mem
)
5487 || (!i
.types
[op
].bitfield
.unspecified
5488 && !match_broadcast_size (t
, op
)))
5491 i
.error
= unsupported_broadcast
;
5495 i
.broadcast
->bytes
= ((1 << (t
->opcode_modifier
.broadcast
- 1))
5496 * i
.broadcast
->type
);
5497 operand_type_set (&type
, 0);
5498 switch (i
.broadcast
->bytes
)
5501 type
.bitfield
.word
= 1;
5504 type
.bitfield
.dword
= 1;
5507 type
.bitfield
.qword
= 1;
5510 type
.bitfield
.xmmword
= 1;
5513 type
.bitfield
.ymmword
= 1;
5516 type
.bitfield
.zmmword
= 1;
5522 overlap
= operand_type_and (type
, t
->operand_types
[op
]);
5523 if (operand_type_all_zero (&overlap
))
5526 if (t
->opcode_modifier
.checkregsize
)
5530 type
.bitfield
.baseindex
= 1;
5531 for (j
= 0; j
< i
.operands
; ++j
)
5534 && !operand_type_register_match(i
.types
[j
],
5535 t
->operand_types
[j
],
5537 t
->operand_types
[op
]))
5542 /* If broadcast is supported in this instruction, we need to check if
5543 operand of one-element size isn't specified without broadcast. */
5544 else if (t
->opcode_modifier
.broadcast
&& i
.mem_operands
)
5546 /* Find memory operand. */
5547 for (op
= 0; op
< i
.operands
; op
++)
5548 if (i
.flags
[op
] & Operand_Mem
)
5550 gas_assert (op
< i
.operands
);
5551 /* Check size of the memory operand. */
5552 if (match_broadcast_size (t
, op
))
5554 i
.error
= broadcast_needed
;
5559 op
= MAX_OPERANDS
- 1; /* Avoid uninitialized variable warning. */
5561 /* Check if requested masking is supported. */
5564 switch (t
->opcode_modifier
.masking
)
5568 case MERGING_MASKING
:
5569 if (i
.mask
->zeroing
)
5572 i
.error
= unsupported_masking
;
5576 case DYNAMIC_MASKING
:
5577 /* Memory destinations allow only merging masking. */
5578 if (i
.mask
->zeroing
&& i
.mem_operands
)
5580 /* Find memory operand. */
5581 for (op
= 0; op
< i
.operands
; op
++)
5582 if (i
.flags
[op
] & Operand_Mem
)
5584 gas_assert (op
< i
.operands
);
5585 if (op
== i
.operands
- 1)
5587 i
.error
= unsupported_masking
;
5597 /* Check if masking is applied to dest operand. */
5598 if (i
.mask
&& (i
.mask
->operand
!= (int) (i
.operands
- 1)))
5600 i
.error
= mask_not_on_destination
;
5607 if (!t
->opcode_modifier
.sae
5608 || (i
.rounding
->type
!= saeonly
&& !t
->opcode_modifier
.staticrounding
))
5610 i
.error
= unsupported_rc_sae
;
5613 /* If the instruction has several immediate operands and one of
5614 them is rounding, the rounding operand should be the last
5615 immediate operand. */
5616 if (i
.imm_operands
> 1
5617 && i
.rounding
->operand
!= (int) (i
.imm_operands
- 1))
5619 i
.error
= rc_sae_operand_not_last_imm
;
5624 /* Check vector Disp8 operand. */
5625 if (t
->opcode_modifier
.disp8memshift
5626 && i
.disp_encoding
!= disp_encoding_32bit
)
5629 i
.memshift
= t
->opcode_modifier
.broadcast
- 1;
5630 else if (t
->opcode_modifier
.disp8memshift
!= DISP8_SHIFT_VL
)
5631 i
.memshift
= t
->opcode_modifier
.disp8memshift
;
5634 const i386_operand_type
*type
= NULL
;
5637 for (op
= 0; op
< i
.operands
; op
++)
5638 if (i
.flags
[op
] & Operand_Mem
)
5640 if (t
->opcode_modifier
.evex
== EVEXLIG
)
5641 i
.memshift
= 2 + (i
.suffix
== QWORD_MNEM_SUFFIX
);
5642 else if (t
->operand_types
[op
].bitfield
.xmmword
5643 + t
->operand_types
[op
].bitfield
.ymmword
5644 + t
->operand_types
[op
].bitfield
.zmmword
<= 1)
5645 type
= &t
->operand_types
[op
];
5646 else if (!i
.types
[op
].bitfield
.unspecified
)
5647 type
= &i
.types
[op
];
5649 else if (i
.types
[op
].bitfield
.class == RegSIMD
5650 && t
->opcode_modifier
.evex
!= EVEXLIG
)
5652 if (i
.types
[op
].bitfield
.zmmword
)
5654 else if (i
.types
[op
].bitfield
.ymmword
&& i
.memshift
< 5)
5656 else if (i
.types
[op
].bitfield
.xmmword
&& i
.memshift
< 4)
5662 if (type
->bitfield
.zmmword
)
5664 else if (type
->bitfield
.ymmword
)
5666 else if (type
->bitfield
.xmmword
)
5670 /* For the check in fits_in_disp8(). */
5671 if (i
.memshift
== 0)
5675 for (op
= 0; op
< i
.operands
; op
++)
5676 if (operand_type_check (i
.types
[op
], disp
)
5677 && i
.op
[op
].disps
->X_op
== O_constant
)
5679 if (fits_in_disp8 (i
.op
[op
].disps
->X_add_number
))
5681 i
.types
[op
].bitfield
.disp8
= 1;
5684 i
.types
[op
].bitfield
.disp8
= 0;
5693 /* Check if operands are valid for the instruction. Update VEX
5697 VEX_check_operands (const insn_template
*t
)
5699 if (i
.vec_encoding
== vex_encoding_evex
)
5701 /* This instruction must be encoded with EVEX prefix. */
5702 if (!is_evex_encoding (t
))
5704 i
.error
= unsupported
;
5710 if (!t
->opcode_modifier
.vex
)
5712 /* This instruction template doesn't have VEX prefix. */
5713 if (i
.vec_encoding
!= vex_encoding_default
)
5715 i
.error
= unsupported
;
5721 /* Check the special Imm4 cases; must be the first operand. */
5722 if (t
->cpu_flags
.bitfield
.cpuxop
&& t
->operands
== 5)
5724 if (i
.op
[0].imms
->X_op
!= O_constant
5725 || !fits_in_imm4 (i
.op
[0].imms
->X_add_number
))
5731 /* Turn off Imm<N> so that update_imm won't complain. */
5732 operand_type_set (&i
.types
[0], 0);
5738 static const insn_template
*
5739 match_template (char mnem_suffix
)
5741 /* Points to template once we've found it. */
5742 const insn_template
*t
;
5743 i386_operand_type overlap0
, overlap1
, overlap2
, overlap3
;
5744 i386_operand_type overlap4
;
5745 unsigned int found_reverse_match
;
5746 i386_opcode_modifier suffix_check
;
5747 i386_operand_type operand_types
[MAX_OPERANDS
];
5748 int addr_prefix_disp
;
5749 unsigned int j
, size_match
, check_register
;
5750 enum i386_error specific_error
= 0;
5752 #if MAX_OPERANDS != 5
5753 # error "MAX_OPERANDS must be 5."
5756 found_reverse_match
= 0;
5757 addr_prefix_disp
= -1;
5759 /* Prepare for mnemonic suffix check. */
5760 memset (&suffix_check
, 0, sizeof (suffix_check
));
5761 switch (mnem_suffix
)
5763 case BYTE_MNEM_SUFFIX
:
5764 suffix_check
.no_bsuf
= 1;
5766 case WORD_MNEM_SUFFIX
:
5767 suffix_check
.no_wsuf
= 1;
5769 case SHORT_MNEM_SUFFIX
:
5770 suffix_check
.no_ssuf
= 1;
5772 case LONG_MNEM_SUFFIX
:
5773 suffix_check
.no_lsuf
= 1;
5775 case QWORD_MNEM_SUFFIX
:
5776 suffix_check
.no_qsuf
= 1;
5779 /* NB: In Intel syntax, normally we can check for memory operand
5780 size when there is no mnemonic suffix. But jmp and call have
5781 2 different encodings with Dword memory operand size, one with
5782 No_ldSuf and the other without. i.suffix is set to
5783 LONG_DOUBLE_MNEM_SUFFIX to skip the one with No_ldSuf. */
5784 if (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
)
5785 suffix_check
.no_ldsuf
= 1;
5788 /* Must have right number of operands. */
5789 i
.error
= number_of_operands_mismatch
;
5791 for (t
= current_templates
->start
; t
< current_templates
->end
; t
++)
5793 addr_prefix_disp
= -1;
5794 found_reverse_match
= 0;
5796 if (i
.operands
!= t
->operands
)
5799 /* Check processor support. */
5800 i
.error
= unsupported
;
5801 if (cpu_flags_match (t
) != CPU_FLAGS_PERFECT_MATCH
)
5804 /* Check AT&T mnemonic. */
5805 i
.error
= unsupported_with_intel_mnemonic
;
5806 if (intel_mnemonic
&& t
->opcode_modifier
.attmnemonic
)
5809 /* Check AT&T/Intel syntax. */
5810 i
.error
= unsupported_syntax
;
5811 if ((intel_syntax
&& t
->opcode_modifier
.attsyntax
)
5812 || (!intel_syntax
&& t
->opcode_modifier
.intelsyntax
))
5815 /* Check Intel64/AMD64 ISA. */
5819 /* Default: Don't accept Intel64. */
5820 if (t
->opcode_modifier
.isa64
== INTEL64
)
5824 /* -mamd64: Don't accept Intel64 and Intel64 only. */
5825 if (t
->opcode_modifier
.isa64
>= INTEL64
)
5829 /* -mintel64: Don't accept AMD64. */
5830 if (t
->opcode_modifier
.isa64
== AMD64
&& flag_code
== CODE_64BIT
)
5835 /* Check the suffix. */
5836 i
.error
= invalid_instruction_suffix
;
5837 if ((t
->opcode_modifier
.no_bsuf
&& suffix_check
.no_bsuf
)
5838 || (t
->opcode_modifier
.no_wsuf
&& suffix_check
.no_wsuf
)
5839 || (t
->opcode_modifier
.no_lsuf
&& suffix_check
.no_lsuf
)
5840 || (t
->opcode_modifier
.no_ssuf
&& suffix_check
.no_ssuf
)
5841 || (t
->opcode_modifier
.no_qsuf
&& suffix_check
.no_qsuf
)
5842 || (t
->opcode_modifier
.no_ldsuf
&& suffix_check
.no_ldsuf
))
5845 size_match
= operand_size_match (t
);
5849 /* This is intentionally not
5851 if (i.jumpabsolute != (t->opcode_modifier.jump == JUMP_ABSOLUTE))
5853 as the case of a missing * on the operand is accepted (perhaps with
5854 a warning, issued further down). */
5855 if (i
.jumpabsolute
&& t
->opcode_modifier
.jump
!= JUMP_ABSOLUTE
)
5857 i
.error
= operand_type_mismatch
;
5861 for (j
= 0; j
< MAX_OPERANDS
; j
++)
5862 operand_types
[j
] = t
->operand_types
[j
];
5864 /* In general, don't allow 64-bit operands in 32-bit mode. */
5865 if (i
.suffix
== QWORD_MNEM_SUFFIX
5866 && flag_code
!= CODE_64BIT
5868 ? (!t
->opcode_modifier
.ignoresize
5869 && !t
->opcode_modifier
.broadcast
5870 && !intel_float_operand (t
->name
))
5871 : intel_float_operand (t
->name
) != 2)
5872 && ((operand_types
[0].bitfield
.class != RegMMX
5873 && operand_types
[0].bitfield
.class != RegSIMD
)
5874 || (operand_types
[t
->operands
> 1].bitfield
.class != RegMMX
5875 && operand_types
[t
->operands
> 1].bitfield
.class != RegSIMD
))
5876 && (t
->base_opcode
!= 0x0fc7
5877 || t
->extension_opcode
!= 1 /* cmpxchg8b */))
5880 /* In general, don't allow 32-bit operands on pre-386. */
5881 else if (i
.suffix
== LONG_MNEM_SUFFIX
5882 && !cpu_arch_flags
.bitfield
.cpui386
5884 ? (!t
->opcode_modifier
.ignoresize
5885 && !intel_float_operand (t
->name
))
5886 : intel_float_operand (t
->name
) != 2)
5887 && ((operand_types
[0].bitfield
.class != RegMMX
5888 && operand_types
[0].bitfield
.class != RegSIMD
)
5889 || (operand_types
[t
->operands
> 1].bitfield
.class != RegMMX
5890 && operand_types
[t
->operands
> 1].bitfield
.class
5894 /* Do not verify operands when there are none. */
5898 /* We've found a match; break out of loop. */
5902 if (!t
->opcode_modifier
.jump
5903 || t
->opcode_modifier
.jump
== JUMP_ABSOLUTE
)
5905 /* There should be only one Disp operand. */
5906 for (j
= 0; j
< MAX_OPERANDS
; j
++)
5907 if (operand_type_check (operand_types
[j
], disp
))
5909 if (j
< MAX_OPERANDS
)
5911 bfd_boolean override
= (i
.prefix
[ADDR_PREFIX
] != 0);
5913 addr_prefix_disp
= j
;
5915 /* Address size prefix will turn Disp64/Disp32S/Disp32/Disp16
5916 operand into Disp32/Disp32/Disp16/Disp32 operand. */
5920 override
= !override
;
5923 if (operand_types
[j
].bitfield
.disp32
5924 && operand_types
[j
].bitfield
.disp16
)
5926 operand_types
[j
].bitfield
.disp16
= override
;
5927 operand_types
[j
].bitfield
.disp32
= !override
;
5929 operand_types
[j
].bitfield
.disp32s
= 0;
5930 operand_types
[j
].bitfield
.disp64
= 0;
5934 if (operand_types
[j
].bitfield
.disp32s
5935 || operand_types
[j
].bitfield
.disp64
)
5937 operand_types
[j
].bitfield
.disp64
&= !override
;
5938 operand_types
[j
].bitfield
.disp32s
&= !override
;
5939 operand_types
[j
].bitfield
.disp32
= override
;
5941 operand_types
[j
].bitfield
.disp16
= 0;
5947 /* Force 0x8b encoding for "mov foo@GOT, %eax". */
5948 if (i
.reloc
[0] == BFD_RELOC_386_GOT32
&& t
->base_opcode
== 0xa0)
5951 /* We check register size if needed. */
5952 if (t
->opcode_modifier
.checkregsize
)
5954 check_register
= (1 << t
->operands
) - 1;
5956 check_register
&= ~(1 << i
.broadcast
->operand
);
5961 overlap0
= operand_type_and (i
.types
[0], operand_types
[0]);
5962 switch (t
->operands
)
5965 if (!operand_type_match (overlap0
, i
.types
[0]))
5969 /* xchg %eax, %eax is a special case. It is an alias for nop
5970 only in 32bit mode and we can use opcode 0x90. In 64bit
5971 mode, we can't use 0x90 for xchg %eax, %eax since it should
5972 zero-extend %eax to %rax. */
5973 if (flag_code
== CODE_64BIT
5974 && t
->base_opcode
== 0x90
5975 && i
.types
[0].bitfield
.instance
== Accum
5976 && i
.types
[0].bitfield
.dword
5977 && i
.types
[1].bitfield
.instance
== Accum
5978 && i
.types
[1].bitfield
.dword
)
5980 /* xrelease mov %eax, <disp> is another special case. It must not
5981 match the accumulator-only encoding of mov. */
5982 if (flag_code
!= CODE_64BIT
5984 && t
->base_opcode
== 0xa0
5985 && i
.types
[0].bitfield
.instance
== Accum
5986 && (i
.flags
[1] & Operand_Mem
))
5991 if (!(size_match
& MATCH_STRAIGHT
))
5993 /* Reverse direction of operands if swapping is possible in the first
5994 place (operands need to be symmetric) and
5995 - the load form is requested, and the template is a store form,
5996 - the store form is requested, and the template is a load form,
5997 - the non-default (swapped) form is requested. */
5998 overlap1
= operand_type_and (operand_types
[0], operand_types
[1]);
5999 if (t
->opcode_modifier
.d
&& i
.reg_operands
== i
.operands
6000 && !operand_type_all_zero (&overlap1
))
6001 switch (i
.dir_encoding
)
6003 case dir_encoding_load
:
6004 if (operand_type_check (operand_types
[i
.operands
- 1], anymem
)
6005 || t
->opcode_modifier
.regmem
)
6009 case dir_encoding_store
:
6010 if (!operand_type_check (operand_types
[i
.operands
- 1], anymem
)
6011 && !t
->opcode_modifier
.regmem
)
6015 case dir_encoding_swap
:
6018 case dir_encoding_default
:
6021 /* If we want store form, we skip the current load. */
6022 if ((i
.dir_encoding
== dir_encoding_store
6023 || i
.dir_encoding
== dir_encoding_swap
)
6024 && i
.mem_operands
== 0
6025 && t
->opcode_modifier
.load
)
6030 overlap1
= operand_type_and (i
.types
[1], operand_types
[1]);
6031 if (!operand_type_match (overlap0
, i
.types
[0])
6032 || !operand_type_match (overlap1
, i
.types
[1])
6033 || ((check_register
& 3) == 3
6034 && !operand_type_register_match (i
.types
[0],
6039 /* Check if other direction is valid ... */
6040 if (!t
->opcode_modifier
.d
)
6044 if (!(size_match
& MATCH_REVERSE
))
6046 /* Try reversing direction of operands. */
6047 overlap0
= operand_type_and (i
.types
[0], operand_types
[i
.operands
- 1]);
6048 overlap1
= operand_type_and (i
.types
[i
.operands
- 1], operand_types
[0]);
6049 if (!operand_type_match (overlap0
, i
.types
[0])
6050 || !operand_type_match (overlap1
, i
.types
[i
.operands
- 1])
6052 && !operand_type_register_match (i
.types
[0],
6053 operand_types
[i
.operands
- 1],
6054 i
.types
[i
.operands
- 1],
6057 /* Does not match either direction. */
6060 /* found_reverse_match holds which of D or FloatR
6062 if (!t
->opcode_modifier
.d
)
6063 found_reverse_match
= 0;
6064 else if (operand_types
[0].bitfield
.tbyte
)
6065 found_reverse_match
= Opcode_FloatD
;
6066 else if (operand_types
[0].bitfield
.xmmword
6067 || operand_types
[i
.operands
- 1].bitfield
.xmmword
6068 || operand_types
[0].bitfield
.class == RegMMX
6069 || operand_types
[i
.operands
- 1].bitfield
.class == RegMMX
6070 || is_any_vex_encoding(t
))
6071 found_reverse_match
= (t
->base_opcode
& 0xee) != 0x6e
6072 ? Opcode_SIMD_FloatD
: Opcode_SIMD_IntD
;
6074 found_reverse_match
= Opcode_D
;
6075 if (t
->opcode_modifier
.floatr
)
6076 found_reverse_match
|= Opcode_FloatR
;
6080 /* Found a forward 2 operand match here. */
6081 switch (t
->operands
)
6084 overlap4
= operand_type_and (i
.types
[4],
6088 overlap3
= operand_type_and (i
.types
[3],
6092 overlap2
= operand_type_and (i
.types
[2],
6097 switch (t
->operands
)
6100 if (!operand_type_match (overlap4
, i
.types
[4])
6101 || !operand_type_register_match (i
.types
[3],
6108 if (!operand_type_match (overlap3
, i
.types
[3])
6109 || ((check_register
& 0xa) == 0xa
6110 && !operand_type_register_match (i
.types
[1],
6114 || ((check_register
& 0xc) == 0xc
6115 && !operand_type_register_match (i
.types
[2],
6122 /* Here we make use of the fact that there are no
6123 reverse match 3 operand instructions. */
6124 if (!operand_type_match (overlap2
, i
.types
[2])
6125 || ((check_register
& 5) == 5
6126 && !operand_type_register_match (i
.types
[0],
6130 || ((check_register
& 6) == 6
6131 && !operand_type_register_match (i
.types
[1],
6139 /* Found either forward/reverse 2, 3 or 4 operand match here:
6140 slip through to break. */
6143 /* Check if vector and VEX operands are valid. */
6144 if (check_VecOperands (t
) || VEX_check_operands (t
))
6146 specific_error
= i
.error
;
6150 /* We've found a match; break out of loop. */
6154 if (t
== current_templates
->end
)
6156 /* We found no match. */
6157 const char *err_msg
;
6158 switch (specific_error
? specific_error
: i
.error
)
6162 case operand_size_mismatch
:
6163 err_msg
= _("operand size mismatch");
6165 case operand_type_mismatch
:
6166 err_msg
= _("operand type mismatch");
6168 case register_type_mismatch
:
6169 err_msg
= _("register type mismatch");
6171 case number_of_operands_mismatch
:
6172 err_msg
= _("number of operands mismatch");
6174 case invalid_instruction_suffix
:
6175 err_msg
= _("invalid instruction suffix");
6178 err_msg
= _("constant doesn't fit in 4 bits");
6180 case unsupported_with_intel_mnemonic
:
6181 err_msg
= _("unsupported with Intel mnemonic");
6183 case unsupported_syntax
:
6184 err_msg
= _("unsupported syntax");
6187 as_bad (_("unsupported instruction `%s'"),
6188 current_templates
->start
->name
);
6190 case invalid_vsib_address
:
6191 err_msg
= _("invalid VSIB address");
6193 case invalid_vector_register_set
:
6194 err_msg
= _("mask, index, and destination registers must be distinct");
6196 case unsupported_vector_index_register
:
6197 err_msg
= _("unsupported vector index register");
6199 case unsupported_broadcast
:
6200 err_msg
= _("unsupported broadcast");
6202 case broadcast_needed
:
6203 err_msg
= _("broadcast is needed for operand of such type");
6205 case unsupported_masking
:
6206 err_msg
= _("unsupported masking");
6208 case mask_not_on_destination
:
6209 err_msg
= _("mask not on destination operand");
6211 case no_default_mask
:
6212 err_msg
= _("default mask isn't allowed");
6214 case unsupported_rc_sae
:
6215 err_msg
= _("unsupported static rounding/sae");
6217 case rc_sae_operand_not_last_imm
:
6219 err_msg
= _("RC/SAE operand must precede immediate operands");
6221 err_msg
= _("RC/SAE operand must follow immediate operands");
6223 case invalid_register_operand
:
6224 err_msg
= _("invalid register operand");
6227 as_bad (_("%s for `%s'"), err_msg
,
6228 current_templates
->start
->name
);
6232 if (!quiet_warnings
)
6235 && (i
.jumpabsolute
!= (t
->opcode_modifier
.jump
== JUMP_ABSOLUTE
)))
6236 as_warn (_("indirect %s without `*'"), t
->name
);
6238 if (t
->opcode_modifier
.isprefix
6239 && t
->opcode_modifier
.ignoresize
)
6241 /* Warn them that a data or address size prefix doesn't
6242 affect assembly of the next line of code. */
6243 as_warn (_("stand-alone `%s' prefix"), t
->name
);
6247 /* Copy the template we found. */
6250 if (addr_prefix_disp
!= -1)
6251 i
.tm
.operand_types
[addr_prefix_disp
]
6252 = operand_types
[addr_prefix_disp
];
6254 if (found_reverse_match
)
6256 /* If we found a reverse match we must alter the opcode direction
6257 bit and clear/flip the regmem modifier one. found_reverse_match
6258 holds bits to change (different for int & float insns). */
6260 i
.tm
.base_opcode
^= found_reverse_match
;
6262 i
.tm
.operand_types
[0] = operand_types
[i
.operands
- 1];
6263 i
.tm
.operand_types
[i
.operands
- 1] = operand_types
[0];
6265 /* Certain SIMD insns have their load forms specified in the opcode
6266 table, and hence we need to _set_ RegMem instead of clearing it.
6267 We need to avoid setting the bit though on insns like KMOVW. */
6268 i
.tm
.opcode_modifier
.regmem
6269 = i
.tm
.opcode_modifier
.modrm
&& i
.tm
.opcode_modifier
.d
6270 && i
.tm
.operands
> 2U - i
.tm
.opcode_modifier
.sse2avx
6271 && !i
.tm
.opcode_modifier
.regmem
;
6280 unsigned int es_op
= i
.tm
.opcode_modifier
.isstring
- IS_STRING_ES_OP0
;
6281 unsigned int op
= i
.tm
.operand_types
[0].bitfield
.baseindex
? es_op
: 0;
6283 if (i
.seg
[op
] != NULL
&& i
.seg
[op
] != &es
)
6285 as_bad (_("`%s' operand %u must use `%ses' segment"),
6287 intel_syntax
? i
.tm
.operands
- es_op
: es_op
+ 1,
6292 /* There's only ever one segment override allowed per instruction.
6293 This instruction possibly has a legal segment override on the
6294 second operand, so copy the segment to where non-string
6295 instructions store it, allowing common code. */
6296 i
.seg
[op
] = i
.seg
[1];
6302 process_suffix (void)
6304 /* If matched instruction specifies an explicit instruction mnemonic
6306 if (i
.tm
.opcode_modifier
.size
== SIZE16
)
6307 i
.suffix
= WORD_MNEM_SUFFIX
;
6308 else if (i
.tm
.opcode_modifier
.size
== SIZE32
)
6309 i
.suffix
= LONG_MNEM_SUFFIX
;
6310 else if (i
.tm
.opcode_modifier
.size
== SIZE64
)
6311 i
.suffix
= QWORD_MNEM_SUFFIX
;
6312 else if (i
.reg_operands
6313 && (i
.operands
> 1 || i
.types
[0].bitfield
.class == Reg
))
6315 /* If there's no instruction mnemonic suffix we try to invent one
6316 based on GPR operands. */
6319 /* We take i.suffix from the last register operand specified,
6320 Destination register type is more significant than source
6321 register type. crc32 in SSE4.2 prefers source register
6323 unsigned int op
= i
.tm
.base_opcode
!= 0xf20f38f0 ? i
.operands
: 1;
6326 if (i
.tm
.operand_types
[op
].bitfield
.instance
== InstanceNone
6327 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
6329 if (i
.types
[op
].bitfield
.class != Reg
)
6331 if (i
.types
[op
].bitfield
.byte
)
6332 i
.suffix
= BYTE_MNEM_SUFFIX
;
6333 else if (i
.types
[op
].bitfield
.word
)
6334 i
.suffix
= WORD_MNEM_SUFFIX
;
6335 else if (i
.types
[op
].bitfield
.dword
)
6336 i
.suffix
= LONG_MNEM_SUFFIX
;
6337 else if (i
.types
[op
].bitfield
.qword
)
6338 i
.suffix
= QWORD_MNEM_SUFFIX
;
6344 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
6347 && i
.tm
.opcode_modifier
.ignoresize
6348 && i
.tm
.opcode_modifier
.no_bsuf
)
6350 else if (!check_byte_reg ())
6353 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
6356 && i
.tm
.opcode_modifier
.ignoresize
6357 && i
.tm
.opcode_modifier
.no_lsuf
6358 && !i
.tm
.opcode_modifier
.todword
6359 && !i
.tm
.opcode_modifier
.toqword
)
6361 else if (!check_long_reg ())
6364 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
6367 && i
.tm
.opcode_modifier
.ignoresize
6368 && i
.tm
.opcode_modifier
.no_qsuf
6369 && !i
.tm
.opcode_modifier
.todword
6370 && !i
.tm
.opcode_modifier
.toqword
)
6372 else if (!check_qword_reg ())
6375 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
6378 && i
.tm
.opcode_modifier
.ignoresize
6379 && i
.tm
.opcode_modifier
.no_wsuf
)
6381 else if (!check_word_reg ())
6384 else if (intel_syntax
&& i
.tm
.opcode_modifier
.ignoresize
)
6385 /* Do nothing if the instruction is going to ignore the prefix. */
6390 else if (i
.tm
.opcode_modifier
.defaultsize
&& !i
.suffix
)
6392 i
.suffix
= stackop_size
;
6393 if (stackop_size
== LONG_MNEM_SUFFIX
)
6395 /* stackop_size is set to LONG_MNEM_SUFFIX for the
6396 .code16gcc directive to support 16-bit mode with
6397 32-bit address. For IRET without a suffix, generate
6398 16-bit IRET (opcode 0xcf) to return from an interrupt
6400 if (i
.tm
.base_opcode
== 0xcf)
6402 i
.suffix
= WORD_MNEM_SUFFIX
;
6403 as_warn (_("generating 16-bit `iret' for .code16gcc directive"));
6405 /* Warn about changed behavior for segment register push/pop. */
6406 else if ((i
.tm
.base_opcode
| 1) == 0x07)
6407 as_warn (_("generating 32-bit `%s', unlike earlier gas versions"),
6412 && (i
.tm
.opcode_modifier
.jump
== JUMP_ABSOLUTE
6413 || i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
6414 || i
.tm
.opcode_modifier
.jump
== JUMP_INTERSEGMENT
6415 || (i
.tm
.base_opcode
== 0x0f01 /* [ls][gi]dt */
6416 && i
.tm
.extension_opcode
<= 3)))
6421 if (!i
.tm
.opcode_modifier
.no_qsuf
)
6423 i
.suffix
= QWORD_MNEM_SUFFIX
;
6428 if (!i
.tm
.opcode_modifier
.no_lsuf
)
6429 i
.suffix
= LONG_MNEM_SUFFIX
;
6432 if (!i
.tm
.opcode_modifier
.no_wsuf
)
6433 i
.suffix
= WORD_MNEM_SUFFIX
;
6439 && (!i
.tm
.opcode_modifier
.defaultsize
6440 /* Also cover lret/retf/iret in 64-bit mode. */
6441 || (flag_code
== CODE_64BIT
6442 && !i
.tm
.opcode_modifier
.no_lsuf
6443 && !i
.tm
.opcode_modifier
.no_qsuf
))
6444 && !i
.tm
.opcode_modifier
.ignoresize
6445 /* Accept FLDENV et al without suffix. */
6446 && (i
.tm
.opcode_modifier
.no_ssuf
|| i
.tm
.opcode_modifier
.floatmf
))
6448 unsigned int suffixes
;
6450 suffixes
= !i
.tm
.opcode_modifier
.no_bsuf
;
6451 if (!i
.tm
.opcode_modifier
.no_wsuf
)
6453 if (!i
.tm
.opcode_modifier
.no_lsuf
)
6455 if (!i
.tm
.opcode_modifier
.no_ldsuf
)
6457 if (!i
.tm
.opcode_modifier
.no_ssuf
)
6459 if (flag_code
== CODE_64BIT
&& !i
.tm
.opcode_modifier
.no_qsuf
)
6462 /* Are multiple suffixes allowed? */
6463 if (suffixes
& (suffixes
- 1))
6466 && (!i
.tm
.opcode_modifier
.defaultsize
6467 || operand_check
== check_error
))
6469 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
6472 if (operand_check
== check_error
)
6474 as_bad (_("no instruction mnemonic suffix given and "
6475 "no register operands; can't size `%s'"), i
.tm
.name
);
6478 if (operand_check
== check_warning
)
6479 as_warn (_("%s; using default for `%s'"),
6481 ? _("ambiguous operand size")
6482 : _("no instruction mnemonic suffix given and "
6483 "no register operands"),
6486 if (i
.tm
.opcode_modifier
.floatmf
)
6487 i
.suffix
= SHORT_MNEM_SUFFIX
;
6488 else if (flag_code
== CODE_16BIT
)
6489 i
.suffix
= WORD_MNEM_SUFFIX
;
6490 else if (!i
.tm
.opcode_modifier
.no_lsuf
)
6491 i
.suffix
= LONG_MNEM_SUFFIX
;
6493 i
.suffix
= QWORD_MNEM_SUFFIX
;
6497 if (!i
.tm
.opcode_modifier
.modrm
&& i
.reg_operands
&& i
.tm
.operands
< 3)
6498 i
.short_form
= (i
.tm
.operand_types
[0].bitfield
.class == Reg
)
6499 != (i
.tm
.operand_types
[1].bitfield
.class == Reg
);
6501 /* Change the opcode based on the operand size given by i.suffix. */
6504 /* Size floating point instruction. */
6505 case LONG_MNEM_SUFFIX
:
6506 if (i
.tm
.opcode_modifier
.floatmf
)
6508 i
.tm
.base_opcode
^= 4;
6512 case WORD_MNEM_SUFFIX
:
6513 case QWORD_MNEM_SUFFIX
:
6514 /* It's not a byte, select word/dword operation. */
6515 if (i
.tm
.opcode_modifier
.w
)
6518 i
.tm
.base_opcode
|= 8;
6520 i
.tm
.base_opcode
|= 1;
6523 case SHORT_MNEM_SUFFIX
:
6524 /* Now select between word & dword operations via the operand
6525 size prefix, except for instructions that will ignore this
6527 if (i
.reg_operands
> 0
6528 && i
.types
[0].bitfield
.class == Reg
6529 && i
.tm
.opcode_modifier
.addrprefixopreg
6530 && (i
.tm
.operand_types
[0].bitfield
.instance
== Accum
6531 || i
.operands
== 1))
6533 /* The address size override prefix changes the size of the
6535 if ((flag_code
== CODE_32BIT
6536 && i
.op
[0].regs
->reg_type
.bitfield
.word
)
6537 || (flag_code
!= CODE_32BIT
6538 && i
.op
[0].regs
->reg_type
.bitfield
.dword
))
6539 if (!add_prefix (ADDR_PREFIX_OPCODE
))
6542 else if (i
.suffix
!= QWORD_MNEM_SUFFIX
6543 && !i
.tm
.opcode_modifier
.ignoresize
6544 && !i
.tm
.opcode_modifier
.floatmf
6545 && !is_any_vex_encoding (&i
.tm
)
6546 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
6547 || (flag_code
== CODE_64BIT
6548 && i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
)))
6550 unsigned int prefix
= DATA_PREFIX_OPCODE
;
6552 if (i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
) /* jcxz, loop */
6553 prefix
= ADDR_PREFIX_OPCODE
;
6555 if (!add_prefix (prefix
))
6559 /* Set mode64 for an operand. */
6560 if (i
.suffix
== QWORD_MNEM_SUFFIX
6561 && flag_code
== CODE_64BIT
6562 && !i
.tm
.opcode_modifier
.norex64
6563 /* Special case for xchg %rax,%rax. It is NOP and doesn't
6565 && ! (i
.operands
== 2
6566 && i
.tm
.base_opcode
== 0x90
6567 && i
.tm
.extension_opcode
== None
6568 && i
.types
[0].bitfield
.instance
== Accum
6569 && i
.types
[0].bitfield
.qword
6570 && i
.types
[1].bitfield
.instance
== Accum
6571 && i
.types
[1].bitfield
.qword
))
6577 if (i
.reg_operands
!= 0
6579 && i
.tm
.opcode_modifier
.addrprefixopreg
6580 && i
.tm
.operand_types
[0].bitfield
.instance
!= Accum
)
6582 /* Check invalid register operand when the address size override
6583 prefix changes the size of register operands. */
6585 enum { need_word
, need_dword
, need_qword
} need
;
6587 if (flag_code
== CODE_32BIT
)
6588 need
= i
.prefix
[ADDR_PREFIX
] ? need_word
: need_dword
;
6591 if (i
.prefix
[ADDR_PREFIX
])
6594 need
= flag_code
== CODE_64BIT
? need_qword
: need_word
;
6597 for (op
= 0; op
< i
.operands
; op
++)
6598 if (i
.types
[op
].bitfield
.class == Reg
6599 && ((need
== need_word
6600 && !i
.op
[op
].regs
->reg_type
.bitfield
.word
)
6601 || (need
== need_dword
6602 && !i
.op
[op
].regs
->reg_type
.bitfield
.dword
)
6603 || (need
== need_qword
6604 && !i
.op
[op
].regs
->reg_type
.bitfield
.qword
)))
6606 as_bad (_("invalid register operand size for `%s'"),
6616 check_byte_reg (void)
6620 for (op
= i
.operands
; --op
>= 0;)
6622 /* Skip non-register operands. */
6623 if (i
.types
[op
].bitfield
.class != Reg
)
6626 /* If this is an eight bit register, it's OK. If it's the 16 or
6627 32 bit version of an eight bit register, we will just use the
6628 low portion, and that's OK too. */
6629 if (i
.types
[op
].bitfield
.byte
)
6632 /* I/O port address operands are OK too. */
6633 if (i
.tm
.operand_types
[op
].bitfield
.instance
== RegD
6634 && i
.tm
.operand_types
[op
].bitfield
.word
)
6637 /* crc32 only wants its source operand checked here. */
6638 if (i
.tm
.base_opcode
== 0xf20f38f0 && op
)
6641 /* Any other register is bad. */
6642 if (i
.types
[op
].bitfield
.class == Reg
6643 || i
.types
[op
].bitfield
.class == RegMMX
6644 || i
.types
[op
].bitfield
.class == RegSIMD
6645 || i
.types
[op
].bitfield
.class == SReg
6646 || i
.types
[op
].bitfield
.class == RegCR
6647 || i
.types
[op
].bitfield
.class == RegDR
6648 || i
.types
[op
].bitfield
.class == RegTR
)
6650 as_bad (_("`%s%s' not allowed with `%s%c'"),
6652 i
.op
[op
].regs
->reg_name
,
6662 check_long_reg (void)
6666 for (op
= i
.operands
; --op
>= 0;)
6667 /* Skip non-register operands. */
6668 if (i
.types
[op
].bitfield
.class != Reg
)
6670 /* Reject eight bit registers, except where the template requires
6671 them. (eg. movzb) */
6672 else if (i
.types
[op
].bitfield
.byte
6673 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
6674 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
6675 && (i
.tm
.operand_types
[op
].bitfield
.word
6676 || i
.tm
.operand_types
[op
].bitfield
.dword
))
6678 as_bad (_("`%s%s' not allowed with `%s%c'"),
6680 i
.op
[op
].regs
->reg_name
,
6685 /* Error if the e prefix on a general reg is missing. */
6686 else if (i
.types
[op
].bitfield
.word
6687 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
6688 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
6689 && i
.tm
.operand_types
[op
].bitfield
.dword
)
6691 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6692 register_prefix
, i
.op
[op
].regs
->reg_name
,
6696 /* Warn if the r prefix on a general reg is present. */
6697 else if (i
.types
[op
].bitfield
.qword
6698 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
6699 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
6700 && i
.tm
.operand_types
[op
].bitfield
.dword
)
6703 && (i
.tm
.opcode_modifier
.toqword
6704 /* Also convert to QWORD for MOVSXD. */
6705 || i
.tm
.base_opcode
== 0x63)
6706 && i
.types
[0].bitfield
.class != RegSIMD
)
6708 /* Convert to QWORD. We want REX byte. */
6709 i
.suffix
= QWORD_MNEM_SUFFIX
;
6713 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6714 register_prefix
, i
.op
[op
].regs
->reg_name
,
6723 check_qword_reg (void)
6727 for (op
= i
.operands
; --op
>= 0; )
6728 /* Skip non-register operands. */
6729 if (i
.types
[op
].bitfield
.class != Reg
)
6731 /* Reject eight bit registers, except where the template requires
6732 them. (eg. movzb) */
6733 else if (i
.types
[op
].bitfield
.byte
6734 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
6735 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
6736 && (i
.tm
.operand_types
[op
].bitfield
.word
6737 || i
.tm
.operand_types
[op
].bitfield
.dword
))
6739 as_bad (_("`%s%s' not allowed with `%s%c'"),
6741 i
.op
[op
].regs
->reg_name
,
6746 /* Warn if the r prefix on a general reg is missing. */
6747 else if ((i
.types
[op
].bitfield
.word
6748 || i
.types
[op
].bitfield
.dword
)
6749 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
6750 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
6751 && i
.tm
.operand_types
[op
].bitfield
.qword
)
6753 /* Prohibit these changes in the 64bit mode, since the
6754 lowering is more complicated. */
6756 && i
.tm
.opcode_modifier
.todword
6757 && i
.types
[0].bitfield
.class != RegSIMD
)
6759 /* Convert to DWORD. We don't want REX byte. */
6760 i
.suffix
= LONG_MNEM_SUFFIX
;
6764 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6765 register_prefix
, i
.op
[op
].regs
->reg_name
,
6774 check_word_reg (void)
6777 for (op
= i
.operands
; --op
>= 0;)
6778 /* Skip non-register operands. */
6779 if (i
.types
[op
].bitfield
.class != Reg
)
6781 /* Reject eight bit registers, except where the template requires
6782 them. (eg. movzb) */
6783 else if (i
.types
[op
].bitfield
.byte
6784 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
6785 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
6786 && (i
.tm
.operand_types
[op
].bitfield
.word
6787 || i
.tm
.operand_types
[op
].bitfield
.dword
))
6789 as_bad (_("`%s%s' not allowed with `%s%c'"),
6791 i
.op
[op
].regs
->reg_name
,
6796 /* Error if the e or r prefix on a general reg is present. */
6797 else if ((i
.types
[op
].bitfield
.dword
6798 || i
.types
[op
].bitfield
.qword
)
6799 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
6800 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
6801 && i
.tm
.operand_types
[op
].bitfield
.word
)
6803 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6804 register_prefix
, i
.op
[op
].regs
->reg_name
,
6812 update_imm (unsigned int j
)
6814 i386_operand_type overlap
= i
.types
[j
];
6815 if ((overlap
.bitfield
.imm8
6816 || overlap
.bitfield
.imm8s
6817 || overlap
.bitfield
.imm16
6818 || overlap
.bitfield
.imm32
6819 || overlap
.bitfield
.imm32s
6820 || overlap
.bitfield
.imm64
)
6821 && !operand_type_equal (&overlap
, &imm8
)
6822 && !operand_type_equal (&overlap
, &imm8s
)
6823 && !operand_type_equal (&overlap
, &imm16
)
6824 && !operand_type_equal (&overlap
, &imm32
)
6825 && !operand_type_equal (&overlap
, &imm32s
)
6826 && !operand_type_equal (&overlap
, &imm64
))
6830 i386_operand_type temp
;
6832 operand_type_set (&temp
, 0);
6833 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
6835 temp
.bitfield
.imm8
= overlap
.bitfield
.imm8
;
6836 temp
.bitfield
.imm8s
= overlap
.bitfield
.imm8s
;
6838 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
6839 temp
.bitfield
.imm16
= overlap
.bitfield
.imm16
;
6840 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
6842 temp
.bitfield
.imm64
= overlap
.bitfield
.imm64
;
6843 temp
.bitfield
.imm32s
= overlap
.bitfield
.imm32s
;
6846 temp
.bitfield
.imm32
= overlap
.bitfield
.imm32
;
6849 else if (operand_type_equal (&overlap
, &imm16_32_32s
)
6850 || operand_type_equal (&overlap
, &imm16_32
)
6851 || operand_type_equal (&overlap
, &imm16_32s
))
6853 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
6858 if (!operand_type_equal (&overlap
, &imm8
)
6859 && !operand_type_equal (&overlap
, &imm8s
)
6860 && !operand_type_equal (&overlap
, &imm16
)
6861 && !operand_type_equal (&overlap
, &imm32
)
6862 && !operand_type_equal (&overlap
, &imm32s
)
6863 && !operand_type_equal (&overlap
, &imm64
))
6865 as_bad (_("no instruction mnemonic suffix given; "
6866 "can't determine immediate size"));
6870 i
.types
[j
] = overlap
;
6880 /* Update the first 2 immediate operands. */
6881 n
= i
.operands
> 2 ? 2 : i
.operands
;
6884 for (j
= 0; j
< n
; j
++)
6885 if (update_imm (j
) == 0)
6888 /* The 3rd operand can't be immediate operand. */
6889 gas_assert (operand_type_check (i
.types
[2], imm
) == 0);
6896 process_operands (void)
6898 /* Default segment register this instruction will use for memory
6899 accesses. 0 means unknown. This is only for optimizing out
6900 unnecessary segment overrides. */
6901 const seg_entry
*default_seg
= 0;
6903 if (i
.tm
.opcode_modifier
.sse2avx
&& i
.tm
.opcode_modifier
.vexvvvv
)
6905 unsigned int dupl
= i
.operands
;
6906 unsigned int dest
= dupl
- 1;
6909 /* The destination must be an xmm register. */
6910 gas_assert (i
.reg_operands
6911 && MAX_OPERANDS
> dupl
6912 && operand_type_equal (&i
.types
[dest
], ®xmm
));
6914 if (i
.tm
.operand_types
[0].bitfield
.instance
== Accum
6915 && i
.tm
.operand_types
[0].bitfield
.xmmword
)
6917 if (i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
)
6919 /* Keep xmm0 for instructions with VEX prefix and 3
6921 i
.tm
.operand_types
[0].bitfield
.instance
= InstanceNone
;
6922 i
.tm
.operand_types
[0].bitfield
.class = RegSIMD
;
6927 /* We remove the first xmm0 and keep the number of
6928 operands unchanged, which in fact duplicates the
6930 for (j
= 1; j
< i
.operands
; j
++)
6932 i
.op
[j
- 1] = i
.op
[j
];
6933 i
.types
[j
- 1] = i
.types
[j
];
6934 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
6935 i
.flags
[j
- 1] = i
.flags
[j
];
6939 else if (i
.tm
.opcode_modifier
.implicit1stxmm0
)
6941 gas_assert ((MAX_OPERANDS
- 1) > dupl
6942 && (i
.tm
.opcode_modifier
.vexsources
6945 /* Add the implicit xmm0 for instructions with VEX prefix
6947 for (j
= i
.operands
; j
> 0; j
--)
6949 i
.op
[j
] = i
.op
[j
- 1];
6950 i
.types
[j
] = i
.types
[j
- 1];
6951 i
.tm
.operand_types
[j
] = i
.tm
.operand_types
[j
- 1];
6952 i
.flags
[j
] = i
.flags
[j
- 1];
6955 = (const reg_entry
*) hash_find (reg_hash
, "xmm0");
6956 i
.types
[0] = regxmm
;
6957 i
.tm
.operand_types
[0] = regxmm
;
6960 i
.reg_operands
+= 2;
6965 i
.op
[dupl
] = i
.op
[dest
];
6966 i
.types
[dupl
] = i
.types
[dest
];
6967 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
6968 i
.flags
[dupl
] = i
.flags
[dest
];
6977 i
.op
[dupl
] = i
.op
[dest
];
6978 i
.types
[dupl
] = i
.types
[dest
];
6979 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
6980 i
.flags
[dupl
] = i
.flags
[dest
];
6983 if (i
.tm
.opcode_modifier
.immext
)
6986 else if (i
.tm
.operand_types
[0].bitfield
.instance
== Accum
6987 && i
.tm
.operand_types
[0].bitfield
.xmmword
)
6991 for (j
= 1; j
< i
.operands
; j
++)
6993 i
.op
[j
- 1] = i
.op
[j
];
6994 i
.types
[j
- 1] = i
.types
[j
];
6996 /* We need to adjust fields in i.tm since they are used by
6997 build_modrm_byte. */
6998 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
7000 i
.flags
[j
- 1] = i
.flags
[j
];
7007 else if (i
.tm
.opcode_modifier
.implicitquadgroup
)
7009 unsigned int regnum
, first_reg_in_group
, last_reg_in_group
;
7011 /* The second operand must be {x,y,z}mmN, where N is a multiple of 4. */
7012 gas_assert (i
.operands
>= 2 && i
.types
[1].bitfield
.class == RegSIMD
);
7013 regnum
= register_number (i
.op
[1].regs
);
7014 first_reg_in_group
= regnum
& ~3;
7015 last_reg_in_group
= first_reg_in_group
+ 3;
7016 if (regnum
!= first_reg_in_group
)
7017 as_warn (_("source register `%s%s' implicitly denotes"
7018 " `%s%.3s%u' to `%s%.3s%u' source group in `%s'"),
7019 register_prefix
, i
.op
[1].regs
->reg_name
,
7020 register_prefix
, i
.op
[1].regs
->reg_name
, first_reg_in_group
,
7021 register_prefix
, i
.op
[1].regs
->reg_name
, last_reg_in_group
,
7024 else if (i
.tm
.opcode_modifier
.regkludge
)
7026 /* The imul $imm, %reg instruction is converted into
7027 imul $imm, %reg, %reg, and the clr %reg instruction
7028 is converted into xor %reg, %reg. */
7030 unsigned int first_reg_op
;
7032 if (operand_type_check (i
.types
[0], reg
))
7036 /* Pretend we saw the extra register operand. */
7037 gas_assert (i
.reg_operands
== 1
7038 && i
.op
[first_reg_op
+ 1].regs
== 0);
7039 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
7040 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
7045 if (i
.tm
.opcode_modifier
.modrm
)
7047 /* The opcode is completed (modulo i.tm.extension_opcode which
7048 must be put into the modrm byte). Now, we make the modrm and
7049 index base bytes based on all the info we've collected. */
7051 default_seg
= build_modrm_byte ();
7053 else if (i
.types
[0].bitfield
.class == SReg
)
7055 if (flag_code
!= CODE_64BIT
7056 ? i
.tm
.base_opcode
== POP_SEG_SHORT
7057 && i
.op
[0].regs
->reg_num
== 1
7058 : (i
.tm
.base_opcode
| 1) == POP_SEG386_SHORT
7059 && i
.op
[0].regs
->reg_num
< 4)
7061 as_bad (_("you can't `%s %s%s'"),
7062 i
.tm
.name
, register_prefix
, i
.op
[0].regs
->reg_name
);
7065 if ( i
.op
[0].regs
->reg_num
> 3 && i
.tm
.opcode_length
== 1 )
7067 i
.tm
.base_opcode
^= POP_SEG_SHORT
^ POP_SEG386_SHORT
;
7068 i
.tm
.opcode_length
= 2;
7070 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
7072 else if ((i
.tm
.base_opcode
& ~0x3) == MOV_AX_DISP32
)
7076 else if (i
.tm
.opcode_modifier
.isstring
)
7078 /* For the string instructions that allow a segment override
7079 on one of their operands, the default segment is ds. */
7082 else if (i
.short_form
)
7084 /* The register or float register operand is in operand
7086 unsigned int op
= i
.tm
.operand_types
[0].bitfield
.class != Reg
;
7088 /* Register goes in low 3 bits of opcode. */
7089 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
7090 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
7092 if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
7094 /* Warn about some common errors, but press on regardless.
7095 The first case can be generated by gcc (<= 2.8.1). */
7096 if (i
.operands
== 2)
7098 /* Reversed arguments on faddp, fsubp, etc. */
7099 as_warn (_("translating to `%s %s%s,%s%s'"), i
.tm
.name
,
7100 register_prefix
, i
.op
[!intel_syntax
].regs
->reg_name
,
7101 register_prefix
, i
.op
[intel_syntax
].regs
->reg_name
);
7105 /* Extraneous `l' suffix on fp insn. */
7106 as_warn (_("translating to `%s %s%s'"), i
.tm
.name
,
7107 register_prefix
, i
.op
[0].regs
->reg_name
);
7112 if (i
.tm
.base_opcode
== 0x8d /* lea */
7115 as_warn (_("segment override on `%s' is ineffectual"), i
.tm
.name
);
7117 /* If a segment was explicitly specified, and the specified segment
7118 is not the default, use an opcode prefix to select it. If we
7119 never figured out what the default segment is, then default_seg
7120 will be zero at this point, and the specified segment prefix will
7122 if ((i
.seg
[0]) && (i
.seg
[0] != default_seg
))
7124 if (!add_prefix (i
.seg
[0]->seg_prefix
))
7130 static const seg_entry
*
7131 build_modrm_byte (void)
7133 const seg_entry
*default_seg
= 0;
7134 unsigned int source
, dest
;
7137 vex_3_sources
= i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
;
7140 unsigned int nds
, reg_slot
;
7143 dest
= i
.operands
- 1;
7146 /* There are 2 kinds of instructions:
7147 1. 5 operands: 4 register operands or 3 register operands
7148 plus 1 memory operand plus one Imm4 operand, VexXDS, and
7149 VexW0 or VexW1. The destination must be either XMM, YMM or
7151 2. 4 operands: 4 register operands or 3 register operands
7152 plus 1 memory operand, with VexXDS. */
7153 gas_assert ((i
.reg_operands
== 4
7154 || (i
.reg_operands
== 3 && i
.mem_operands
== 1))
7155 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
7156 && i
.tm
.opcode_modifier
.vexw
7157 && i
.tm
.operand_types
[dest
].bitfield
.class == RegSIMD
);
7159 /* If VexW1 is set, the first non-immediate operand is the source and
7160 the second non-immediate one is encoded in the immediate operand. */
7161 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
7163 source
= i
.imm_operands
;
7164 reg_slot
= i
.imm_operands
+ 1;
7168 source
= i
.imm_operands
+ 1;
7169 reg_slot
= i
.imm_operands
;
7172 if (i
.imm_operands
== 0)
7174 /* When there is no immediate operand, generate an 8bit
7175 immediate operand to encode the first operand. */
7176 exp
= &im_expressions
[i
.imm_operands
++];
7177 i
.op
[i
.operands
].imms
= exp
;
7178 i
.types
[i
.operands
] = imm8
;
7181 gas_assert (i
.tm
.operand_types
[reg_slot
].bitfield
.class == RegSIMD
);
7182 exp
->X_op
= O_constant
;
7183 exp
->X_add_number
= register_number (i
.op
[reg_slot
].regs
) << 4;
7184 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
7188 gas_assert (i
.imm_operands
== 1);
7189 gas_assert (fits_in_imm4 (i
.op
[0].imms
->X_add_number
));
7190 gas_assert (!i
.tm
.opcode_modifier
.immext
);
7192 /* Turn on Imm8 again so that output_imm will generate it. */
7193 i
.types
[0].bitfield
.imm8
= 1;
7195 gas_assert (i
.tm
.operand_types
[reg_slot
].bitfield
.class == RegSIMD
);
7196 i
.op
[0].imms
->X_add_number
7197 |= register_number (i
.op
[reg_slot
].regs
) << 4;
7198 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
7201 gas_assert (i
.tm
.operand_types
[nds
].bitfield
.class == RegSIMD
);
7202 i
.vex
.register_specifier
= i
.op
[nds
].regs
;
7207 /* i.reg_operands MUST be the number of real register operands;
7208 implicit registers do not count. If there are 3 register
7209 operands, it must be a instruction with VexNDS. For a
7210 instruction with VexNDD, the destination register is encoded
7211 in VEX prefix. If there are 4 register operands, it must be
7212 a instruction with VEX prefix and 3 sources. */
7213 if (i
.mem_operands
== 0
7214 && ((i
.reg_operands
== 2
7215 && i
.tm
.opcode_modifier
.vexvvvv
<= VEXXDS
)
7216 || (i
.reg_operands
== 3
7217 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
7218 || (i
.reg_operands
== 4 && vex_3_sources
)))
7226 /* When there are 3 operands, one of them may be immediate,
7227 which may be the first or the last operand. Otherwise,
7228 the first operand must be shift count register (cl) or it
7229 is an instruction with VexNDS. */
7230 gas_assert (i
.imm_operands
== 1
7231 || (i
.imm_operands
== 0
7232 && (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
7233 || (i
.types
[0].bitfield
.instance
== RegC
7234 && i
.types
[0].bitfield
.byte
))));
7235 if (operand_type_check (i
.types
[0], imm
)
7236 || (i
.types
[0].bitfield
.instance
== RegC
7237 && i
.types
[0].bitfield
.byte
))
7243 /* When there are 4 operands, the first two must be 8bit
7244 immediate operands. The source operand will be the 3rd
7247 For instructions with VexNDS, if the first operand
7248 an imm8, the source operand is the 2nd one. If the last
7249 operand is imm8, the source operand is the first one. */
7250 gas_assert ((i
.imm_operands
== 2
7251 && i
.types
[0].bitfield
.imm8
7252 && i
.types
[1].bitfield
.imm8
)
7253 || (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
7254 && i
.imm_operands
== 1
7255 && (i
.types
[0].bitfield
.imm8
7256 || i
.types
[i
.operands
- 1].bitfield
.imm8
7258 if (i
.imm_operands
== 2)
7262 if (i
.types
[0].bitfield
.imm8
)
7269 if (is_evex_encoding (&i
.tm
))
7271 /* For EVEX instructions, when there are 5 operands, the
7272 first one must be immediate operand. If the second one
7273 is immediate operand, the source operand is the 3th
7274 one. If the last one is immediate operand, the source
7275 operand is the 2nd one. */
7276 gas_assert (i
.imm_operands
== 2
7277 && i
.tm
.opcode_modifier
.sae
7278 && operand_type_check (i
.types
[0], imm
));
7279 if (operand_type_check (i
.types
[1], imm
))
7281 else if (operand_type_check (i
.types
[4], imm
))
7295 /* RC/SAE operand could be between DEST and SRC. That happens
7296 when one operand is GPR and the other one is XMM/YMM/ZMM
7298 if (i
.rounding
&& i
.rounding
->operand
== (int) dest
)
7301 if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
7303 /* For instructions with VexNDS, the register-only source
7304 operand must be a 32/64bit integer, XMM, YMM, ZMM, or mask
7305 register. It is encoded in VEX prefix. */
7307 i386_operand_type op
;
7310 /* Check register-only source operand when two source
7311 operands are swapped. */
7312 if (!i
.tm
.operand_types
[source
].bitfield
.baseindex
7313 && i
.tm
.operand_types
[dest
].bitfield
.baseindex
)
7321 op
= i
.tm
.operand_types
[vvvv
];
7322 if ((dest
+ 1) >= i
.operands
7323 || ((op
.bitfield
.class != Reg
7324 || (!op
.bitfield
.dword
&& !op
.bitfield
.qword
))
7325 && op
.bitfield
.class != RegSIMD
7326 && !operand_type_equal (&op
, ®mask
)))
7328 i
.vex
.register_specifier
= i
.op
[vvvv
].regs
;
7334 /* One of the register operands will be encoded in the i.rm.reg
7335 field, the other in the combined i.rm.mode and i.rm.regmem
7336 fields. If no form of this instruction supports a memory
7337 destination operand, then we assume the source operand may
7338 sometimes be a memory operand and so we need to store the
7339 destination in the i.rm.reg field. */
7340 if (!i
.tm
.opcode_modifier
.regmem
7341 && operand_type_check (i
.tm
.operand_types
[dest
], anymem
) == 0)
7343 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
7344 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
7345 if (i
.op
[dest
].regs
->reg_type
.bitfield
.class == RegMMX
7346 || i
.op
[source
].regs
->reg_type
.bitfield
.class == RegMMX
)
7347 i
.has_regmmx
= TRUE
;
7348 else if (i
.op
[dest
].regs
->reg_type
.bitfield
.class == RegSIMD
7349 || i
.op
[source
].regs
->reg_type
.bitfield
.class == RegSIMD
)
7351 if (i
.types
[dest
].bitfield
.zmmword
7352 || i
.types
[source
].bitfield
.zmmword
)
7353 i
.has_regzmm
= TRUE
;
7354 else if (i
.types
[dest
].bitfield
.ymmword
7355 || i
.types
[source
].bitfield
.ymmword
)
7356 i
.has_regymm
= TRUE
;
7358 i
.has_regxmm
= TRUE
;
7360 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
7362 if ((i
.op
[dest
].regs
->reg_flags
& RegVRex
) != 0)
7364 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
7366 if ((i
.op
[source
].regs
->reg_flags
& RegVRex
) != 0)
7371 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
7372 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
7373 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
7375 if ((i
.op
[dest
].regs
->reg_flags
& RegVRex
) != 0)
7377 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
7379 if ((i
.op
[source
].regs
->reg_flags
& RegVRex
) != 0)
7382 if (flag_code
!= CODE_64BIT
&& (i
.rex
& REX_R
))
7384 if (i
.types
[!i
.tm
.opcode_modifier
.regmem
].bitfield
.class != RegCR
)
7387 add_prefix (LOCK_PREFIX_OPCODE
);
7391 { /* If it's not 2 reg operands... */
7396 unsigned int fake_zero_displacement
= 0;
7399 for (op
= 0; op
< i
.operands
; op
++)
7400 if (i
.flags
[op
] & Operand_Mem
)
7402 gas_assert (op
< i
.operands
);
7404 if (i
.tm
.opcode_modifier
.vecsib
)
7406 if (i
.index_reg
->reg_num
== RegIZ
)
7409 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
7412 i
.sib
.base
= NO_BASE_REGISTER
;
7413 i
.sib
.scale
= i
.log2_scale_factor
;
7414 i
.types
[op
].bitfield
.disp8
= 0;
7415 i
.types
[op
].bitfield
.disp16
= 0;
7416 i
.types
[op
].bitfield
.disp64
= 0;
7417 if (flag_code
!= CODE_64BIT
|| i
.prefix
[ADDR_PREFIX
])
7419 /* Must be 32 bit */
7420 i
.types
[op
].bitfield
.disp32
= 1;
7421 i
.types
[op
].bitfield
.disp32s
= 0;
7425 i
.types
[op
].bitfield
.disp32
= 0;
7426 i
.types
[op
].bitfield
.disp32s
= 1;
7429 i
.sib
.index
= i
.index_reg
->reg_num
;
7430 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
7432 if ((i
.index_reg
->reg_flags
& RegVRex
) != 0)
7438 if (i
.base_reg
== 0)
7441 if (!i
.disp_operands
)
7442 fake_zero_displacement
= 1;
7443 if (i
.index_reg
== 0)
7445 i386_operand_type newdisp
;
7447 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
7448 /* Operand is just <disp> */
7449 if (flag_code
== CODE_64BIT
)
7451 /* 64bit mode overwrites the 32bit absolute
7452 addressing by RIP relative addressing and
7453 absolute addressing is encoded by one of the
7454 redundant SIB forms. */
7455 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
7456 i
.sib
.base
= NO_BASE_REGISTER
;
7457 i
.sib
.index
= NO_INDEX_REGISTER
;
7458 newdisp
= (!i
.prefix
[ADDR_PREFIX
] ? disp32s
: disp32
);
7460 else if ((flag_code
== CODE_16BIT
)
7461 ^ (i
.prefix
[ADDR_PREFIX
] != 0))
7463 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
7468 i
.rm
.regmem
= NO_BASE_REGISTER
;
7471 i
.types
[op
] = operand_type_and_not (i
.types
[op
], anydisp
);
7472 i
.types
[op
] = operand_type_or (i
.types
[op
], newdisp
);
7474 else if (!i
.tm
.opcode_modifier
.vecsib
)
7476 /* !i.base_reg && i.index_reg */
7477 if (i
.index_reg
->reg_num
== RegIZ
)
7478 i
.sib
.index
= NO_INDEX_REGISTER
;
7480 i
.sib
.index
= i
.index_reg
->reg_num
;
7481 i
.sib
.base
= NO_BASE_REGISTER
;
7482 i
.sib
.scale
= i
.log2_scale_factor
;
7483 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
7484 i
.types
[op
].bitfield
.disp8
= 0;
7485 i
.types
[op
].bitfield
.disp16
= 0;
7486 i
.types
[op
].bitfield
.disp64
= 0;
7487 if (flag_code
!= CODE_64BIT
|| i
.prefix
[ADDR_PREFIX
])
7489 /* Must be 32 bit */
7490 i
.types
[op
].bitfield
.disp32
= 1;
7491 i
.types
[op
].bitfield
.disp32s
= 0;
7495 i
.types
[op
].bitfield
.disp32
= 0;
7496 i
.types
[op
].bitfield
.disp32s
= 1;
7498 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
7502 /* RIP addressing for 64bit mode. */
7503 else if (i
.base_reg
->reg_num
== RegIP
)
7505 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
7506 i
.rm
.regmem
= NO_BASE_REGISTER
;
7507 i
.types
[op
].bitfield
.disp8
= 0;
7508 i
.types
[op
].bitfield
.disp16
= 0;
7509 i
.types
[op
].bitfield
.disp32
= 0;
7510 i
.types
[op
].bitfield
.disp32s
= 1;
7511 i
.types
[op
].bitfield
.disp64
= 0;
7512 i
.flags
[op
] |= Operand_PCrel
;
7513 if (! i
.disp_operands
)
7514 fake_zero_displacement
= 1;
7516 else if (i
.base_reg
->reg_type
.bitfield
.word
)
7518 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
7519 switch (i
.base_reg
->reg_num
)
7522 if (i
.index_reg
== 0)
7524 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
7525 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
7529 if (i
.index_reg
== 0)
7532 if (operand_type_check (i
.types
[op
], disp
) == 0)
7534 /* fake (%bp) into 0(%bp) */
7535 i
.types
[op
].bitfield
.disp8
= 1;
7536 fake_zero_displacement
= 1;
7539 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
7540 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
7542 default: /* (%si) -> 4 or (%di) -> 5 */
7543 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
7545 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
7547 else /* i.base_reg and 32/64 bit mode */
7549 if (flag_code
== CODE_64BIT
7550 && operand_type_check (i
.types
[op
], disp
))
7552 i
.types
[op
].bitfield
.disp16
= 0;
7553 i
.types
[op
].bitfield
.disp64
= 0;
7554 if (i
.prefix
[ADDR_PREFIX
] == 0)
7556 i
.types
[op
].bitfield
.disp32
= 0;
7557 i
.types
[op
].bitfield
.disp32s
= 1;
7561 i
.types
[op
].bitfield
.disp32
= 1;
7562 i
.types
[op
].bitfield
.disp32s
= 0;
7566 if (!i
.tm
.opcode_modifier
.vecsib
)
7567 i
.rm
.regmem
= i
.base_reg
->reg_num
;
7568 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
7570 i
.sib
.base
= i
.base_reg
->reg_num
;
7571 /* x86-64 ignores REX prefix bit here to avoid decoder
7573 if (!(i
.base_reg
->reg_flags
& RegRex
)
7574 && (i
.base_reg
->reg_num
== EBP_REG_NUM
7575 || i
.base_reg
->reg_num
== ESP_REG_NUM
))
7577 if (i
.base_reg
->reg_num
== 5 && i
.disp_operands
== 0)
7579 fake_zero_displacement
= 1;
7580 i
.types
[op
].bitfield
.disp8
= 1;
7582 i
.sib
.scale
= i
.log2_scale_factor
;
7583 if (i
.index_reg
== 0)
7585 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
7586 /* <disp>(%esp) becomes two byte modrm with no index
7587 register. We've already stored the code for esp
7588 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
7589 Any base register besides %esp will not use the
7590 extra modrm byte. */
7591 i
.sib
.index
= NO_INDEX_REGISTER
;
7593 else if (!i
.tm
.opcode_modifier
.vecsib
)
7595 if (i
.index_reg
->reg_num
== RegIZ
)
7596 i
.sib
.index
= NO_INDEX_REGISTER
;
7598 i
.sib
.index
= i
.index_reg
->reg_num
;
7599 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
7600 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
7605 && (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
7606 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
))
7610 if (!fake_zero_displacement
7614 fake_zero_displacement
= 1;
7615 if (i
.disp_encoding
== disp_encoding_8bit
)
7616 i
.types
[op
].bitfield
.disp8
= 1;
7618 i
.types
[op
].bitfield
.disp32
= 1;
7620 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
7624 if (fake_zero_displacement
)
7626 /* Fakes a zero displacement assuming that i.types[op]
7627 holds the correct displacement size. */
7630 gas_assert (i
.op
[op
].disps
== 0);
7631 exp
= &disp_expressions
[i
.disp_operands
++];
7632 i
.op
[op
].disps
= exp
;
7633 exp
->X_op
= O_constant
;
7634 exp
->X_add_number
= 0;
7635 exp
->X_add_symbol
= (symbolS
*) 0;
7636 exp
->X_op_symbol
= (symbolS
*) 0;
7644 if (i
.tm
.opcode_modifier
.vexsources
== XOP2SOURCES
)
7646 if (operand_type_check (i
.types
[0], imm
))
7647 i
.vex
.register_specifier
= NULL
;
7650 /* VEX.vvvv encodes one of the sources when the first
7651 operand is not an immediate. */
7652 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
7653 i
.vex
.register_specifier
= i
.op
[0].regs
;
7655 i
.vex
.register_specifier
= i
.op
[1].regs
;
7658 /* Destination is a XMM register encoded in the ModRM.reg
7660 i
.rm
.reg
= i
.op
[2].regs
->reg_num
;
7661 if ((i
.op
[2].regs
->reg_flags
& RegRex
) != 0)
7664 /* ModRM.rm and VEX.B encodes the other source. */
7665 if (!i
.mem_operands
)
7669 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
7670 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
7672 i
.rm
.regmem
= i
.op
[0].regs
->reg_num
;
7674 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
7678 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXLWP
)
7680 i
.vex
.register_specifier
= i
.op
[2].regs
;
7681 if (!i
.mem_operands
)
7684 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
7685 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
7689 /* Fill in i.rm.reg or i.rm.regmem field with register operand
7690 (if any) based on i.tm.extension_opcode. Again, we must be
7691 careful to make sure that segment/control/debug/test/MMX
7692 registers are coded into the i.rm.reg field. */
7693 else if (i
.reg_operands
)
7696 unsigned int vex_reg
= ~0;
7698 for (op
= 0; op
< i
.operands
; op
++)
7700 if (i
.types
[op
].bitfield
.class == Reg
7701 || i
.types
[op
].bitfield
.class == RegBND
7702 || i
.types
[op
].bitfield
.class == RegMask
7703 || i
.types
[op
].bitfield
.class == SReg
7704 || i
.types
[op
].bitfield
.class == RegCR
7705 || i
.types
[op
].bitfield
.class == RegDR
7706 || i
.types
[op
].bitfield
.class == RegTR
)
7708 if (i
.types
[op
].bitfield
.class == RegSIMD
)
7710 if (i
.types
[op
].bitfield
.zmmword
)
7711 i
.has_regzmm
= TRUE
;
7712 else if (i
.types
[op
].bitfield
.ymmword
)
7713 i
.has_regymm
= TRUE
;
7715 i
.has_regxmm
= TRUE
;
7718 if (i
.types
[op
].bitfield
.class == RegMMX
)
7720 i
.has_regmmx
= TRUE
;
7727 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
7729 /* For instructions with VexNDS, the register-only
7730 source operand is encoded in VEX prefix. */
7731 gas_assert (mem
!= (unsigned int) ~0);
7736 gas_assert (op
< i
.operands
);
7740 /* Check register-only source operand when two source
7741 operands are swapped. */
7742 if (!i
.tm
.operand_types
[op
].bitfield
.baseindex
7743 && i
.tm
.operand_types
[op
+ 1].bitfield
.baseindex
)
7747 gas_assert (mem
== (vex_reg
+ 1)
7748 && op
< i
.operands
);
7753 gas_assert (vex_reg
< i
.operands
);
7757 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXNDD
)
7759 /* For instructions with VexNDD, the register destination
7760 is encoded in VEX prefix. */
7761 if (i
.mem_operands
== 0)
7763 /* There is no memory operand. */
7764 gas_assert ((op
+ 2) == i
.operands
);
7769 /* There are only 2 non-immediate operands. */
7770 gas_assert (op
< i
.imm_operands
+ 2
7771 && i
.operands
== i
.imm_operands
+ 2);
7772 vex_reg
= i
.imm_operands
+ 1;
7776 gas_assert (op
< i
.operands
);
7778 if (vex_reg
!= (unsigned int) ~0)
7780 i386_operand_type
*type
= &i
.tm
.operand_types
[vex_reg
];
7782 if ((type
->bitfield
.class != Reg
7783 || (!type
->bitfield
.dword
&& !type
->bitfield
.qword
))
7784 && type
->bitfield
.class != RegSIMD
7785 && !operand_type_equal (type
, ®mask
))
7788 i
.vex
.register_specifier
= i
.op
[vex_reg
].regs
;
7791 /* Don't set OP operand twice. */
7794 /* If there is an extension opcode to put here, the
7795 register number must be put into the regmem field. */
7796 if (i
.tm
.extension_opcode
!= None
)
7798 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
7799 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
7801 if ((i
.op
[op
].regs
->reg_flags
& RegVRex
) != 0)
7806 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
7807 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
7809 if ((i
.op
[op
].regs
->reg_flags
& RegVRex
) != 0)
7814 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
7815 must set it to 3 to indicate this is a register operand
7816 in the regmem field. */
7817 if (!i
.mem_operands
)
7821 /* Fill in i.rm.reg field with extension opcode (if any). */
7822 if (i
.tm
.extension_opcode
!= None
)
7823 i
.rm
.reg
= i
.tm
.extension_opcode
;
7829 flip_code16 (unsigned int code16
)
7831 gas_assert (i
.tm
.operands
== 1);
7833 return !(i
.prefix
[REX_PREFIX
] & REX_W
)
7834 && (code16
? i
.tm
.operand_types
[0].bitfield
.disp32
7835 || i
.tm
.operand_types
[0].bitfield
.disp32s
7836 : i
.tm
.operand_types
[0].bitfield
.disp16
)
7841 output_branch (void)
7847 relax_substateT subtype
;
7851 code16
= flag_code
== CODE_16BIT
? CODE16
: 0;
7852 size
= i
.disp_encoding
== disp_encoding_32bit
? BIG
: SMALL
;
7855 if (i
.prefix
[DATA_PREFIX
] != 0)
7859 code16
^= flip_code16(code16
);
7861 /* Pentium4 branch hints. */
7862 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
7863 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
7868 if (i
.prefix
[REX_PREFIX
] != 0)
7874 /* BND prefixed jump. */
7875 if (i
.prefix
[BND_PREFIX
] != 0)
7881 if (i
.prefixes
!= 0)
7882 as_warn (_("skipping prefixes on `%s'"), i
.tm
.name
);
7884 /* It's always a symbol; End frag & setup for relax.
7885 Make sure there is enough room in this frag for the largest
7886 instruction we may generate in md_convert_frag. This is 2
7887 bytes for the opcode and room for the prefix and largest
7889 frag_grow (prefix
+ 2 + 4);
7890 /* Prefix and 1 opcode byte go in fr_fix. */
7891 p
= frag_more (prefix
+ 1);
7892 if (i
.prefix
[DATA_PREFIX
] != 0)
7893 *p
++ = DATA_PREFIX_OPCODE
;
7894 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
7895 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
7896 *p
++ = i
.prefix
[SEG_PREFIX
];
7897 if (i
.prefix
[BND_PREFIX
] != 0)
7898 *p
++ = BND_PREFIX_OPCODE
;
7899 if (i
.prefix
[REX_PREFIX
] != 0)
7900 *p
++ = i
.prefix
[REX_PREFIX
];
7901 *p
= i
.tm
.base_opcode
;
7903 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
7904 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, size
);
7905 else if (cpu_arch_flags
.bitfield
.cpui386
)
7906 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, size
);
7908 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, size
);
7911 sym
= i
.op
[0].disps
->X_add_symbol
;
7912 off
= i
.op
[0].disps
->X_add_number
;
7914 if (i
.op
[0].disps
->X_op
!= O_constant
7915 && i
.op
[0].disps
->X_op
!= O_symbol
)
7917 /* Handle complex expressions. */
7918 sym
= make_expr_symbol (i
.op
[0].disps
);
7922 /* 1 possible extra opcode + 4 byte displacement go in var part.
7923 Pass reloc in fr_var. */
7924 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
7927 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7928 /* Return TRUE iff PLT32 relocation should be used for branching to
7932 need_plt32_p (symbolS
*s
)
7934 /* PLT32 relocation is ELF only. */
7939 /* Don't emit PLT32 relocation on Solaris: neither native linker nor
7940 krtld support it. */
7944 /* Since there is no need to prepare for PLT branch on x86-64, we
7945 can generate R_X86_64_PLT32, instead of R_X86_64_PC32, which can
7946 be used as a marker for 32-bit PC-relative branches. */
7950 /* Weak or undefined symbol need PLT32 relocation. */
7951 if (S_IS_WEAK (s
) || !S_IS_DEFINED (s
))
7954 /* Non-global symbol doesn't need PLT32 relocation. */
7955 if (! S_IS_EXTERNAL (s
))
7958 /* Other global symbols need PLT32 relocation. NB: Symbol with
7959 non-default visibilities are treated as normal global symbol
7960 so that PLT32 relocation can be used as a marker for 32-bit
7961 PC-relative branches. It is useful for linker relaxation. */
7972 bfd_reloc_code_real_type jump_reloc
= i
.reloc
[0];
7974 if (i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
)
7976 /* This is a loop or jecxz type instruction. */
7978 if (i
.prefix
[ADDR_PREFIX
] != 0)
7980 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
7983 /* Pentium4 branch hints. */
7984 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
7985 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
7987 FRAG_APPEND_1_CHAR (i
.prefix
[SEG_PREFIX
]);
7996 if (flag_code
== CODE_16BIT
)
7999 if (i
.prefix
[DATA_PREFIX
] != 0)
8001 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
8003 code16
^= flip_code16(code16
);
8011 /* BND prefixed jump. */
8012 if (i
.prefix
[BND_PREFIX
] != 0)
8014 FRAG_APPEND_1_CHAR (i
.prefix
[BND_PREFIX
]);
8018 if (i
.prefix
[REX_PREFIX
] != 0)
8020 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
8024 if (i
.prefixes
!= 0)
8025 as_warn (_("skipping prefixes on `%s'"), i
.tm
.name
);
8027 p
= frag_more (i
.tm
.opcode_length
+ size
);
8028 switch (i
.tm
.opcode_length
)
8031 *p
++ = i
.tm
.base_opcode
>> 8;
8034 *p
++ = i
.tm
.base_opcode
;
8040 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8042 && jump_reloc
== NO_RELOC
8043 && need_plt32_p (i
.op
[0].disps
->X_add_symbol
))
8044 jump_reloc
= BFD_RELOC_X86_64_PLT32
;
8047 jump_reloc
= reloc (size
, 1, 1, jump_reloc
);
8049 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
8050 i
.op
[0].disps
, 1, jump_reloc
);
8052 /* All jumps handled here are signed, but don't use a signed limit
8053 check for 32 and 16 bit jumps as we want to allow wrap around at
8054 4G and 64k respectively. */
8056 fixP
->fx_signed
= 1;
8060 output_interseg_jump (void)
8068 if (flag_code
== CODE_16BIT
)
8072 if (i
.prefix
[DATA_PREFIX
] != 0)
8079 gas_assert (!i
.prefix
[REX_PREFIX
]);
8085 if (i
.prefixes
!= 0)
8086 as_warn (_("skipping prefixes on `%s'"), i
.tm
.name
);
8088 /* 1 opcode; 2 segment; offset */
8089 p
= frag_more (prefix
+ 1 + 2 + size
);
8091 if (i
.prefix
[DATA_PREFIX
] != 0)
8092 *p
++ = DATA_PREFIX_OPCODE
;
8094 if (i
.prefix
[REX_PREFIX
] != 0)
8095 *p
++ = i
.prefix
[REX_PREFIX
];
8097 *p
++ = i
.tm
.base_opcode
;
8098 if (i
.op
[1].imms
->X_op
== O_constant
)
8100 offsetT n
= i
.op
[1].imms
->X_add_number
;
8103 && !fits_in_unsigned_word (n
)
8104 && !fits_in_signed_word (n
))
8106 as_bad (_("16-bit jump out of range"));
8109 md_number_to_chars (p
, n
, size
);
8112 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
8113 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
8114 if (i
.op
[0].imms
->X_op
!= O_constant
)
8115 as_bad (_("can't handle non absolute segment in `%s'"),
8117 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
8120 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8125 asection
*seg
= now_seg
;
8126 subsegT subseg
= now_subseg
;
8128 unsigned int alignment
, align_size_1
;
8129 unsigned int isa_1_descsz
, feature_2_descsz
, descsz
;
8130 unsigned int isa_1_descsz_raw
, feature_2_descsz_raw
;
8131 unsigned int padding
;
8133 if (!IS_ELF
|| !x86_used_note
)
8136 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_X86
;
8138 /* The .note.gnu.property section layout:
8140 Field Length Contents
8143 n_descsz 4 The note descriptor size
8144 n_type 4 NT_GNU_PROPERTY_TYPE_0
8146 n_desc n_descsz The program property array
8150 /* Create the .note.gnu.property section. */
8151 sec
= subseg_new (NOTE_GNU_PROPERTY_SECTION_NAME
, 0);
8152 bfd_set_section_flags (sec
,
8159 if (get_elf_backend_data (stdoutput
)->s
->elfclass
== ELFCLASS64
)
8170 bfd_set_section_alignment (sec
, alignment
);
8171 elf_section_type (sec
) = SHT_NOTE
;
8173 /* GNU_PROPERTY_X86_ISA_1_USED: 4-byte type + 4-byte data size
8175 isa_1_descsz_raw
= 4 + 4 + 4;
8176 /* Align GNU_PROPERTY_X86_ISA_1_USED. */
8177 isa_1_descsz
= (isa_1_descsz_raw
+ align_size_1
) & ~align_size_1
;
8179 feature_2_descsz_raw
= isa_1_descsz
;
8180 /* GNU_PROPERTY_X86_FEATURE_2_USED: 4-byte type + 4-byte data size
8182 feature_2_descsz_raw
+= 4 + 4 + 4;
8183 /* Align GNU_PROPERTY_X86_FEATURE_2_USED. */
8184 feature_2_descsz
= ((feature_2_descsz_raw
+ align_size_1
)
8187 descsz
= feature_2_descsz
;
8188 /* Section size: n_namsz + n_descsz + n_type + n_name + n_descsz. */
8189 p
= frag_more (4 + 4 + 4 + 4 + descsz
);
8191 /* Write n_namsz. */
8192 md_number_to_chars (p
, (valueT
) 4, 4);
8194 /* Write n_descsz. */
8195 md_number_to_chars (p
+ 4, (valueT
) descsz
, 4);
8198 md_number_to_chars (p
+ 4 * 2, (valueT
) NT_GNU_PROPERTY_TYPE_0
, 4);
8201 memcpy (p
+ 4 * 3, "GNU", 4);
8203 /* Write 4-byte type. */
8204 md_number_to_chars (p
+ 4 * 4,
8205 (valueT
) GNU_PROPERTY_X86_ISA_1_USED
, 4);
8207 /* Write 4-byte data size. */
8208 md_number_to_chars (p
+ 4 * 5, (valueT
) 4, 4);
8210 /* Write 4-byte data. */
8211 md_number_to_chars (p
+ 4 * 6, (valueT
) x86_isa_1_used
, 4);
8213 /* Zero out paddings. */
8214 padding
= isa_1_descsz
- isa_1_descsz_raw
;
8216 memset (p
+ 4 * 7, 0, padding
);
8218 /* Write 4-byte type. */
8219 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 4,
8220 (valueT
) GNU_PROPERTY_X86_FEATURE_2_USED
, 4);
8222 /* Write 4-byte data size. */
8223 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 5, (valueT
) 4, 4);
8225 /* Write 4-byte data. */
8226 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 6,
8227 (valueT
) x86_feature_2_used
, 4);
8229 /* Zero out paddings. */
8230 padding
= feature_2_descsz
- feature_2_descsz_raw
;
8232 memset (p
+ isa_1_descsz
+ 4 * 7, 0, padding
);
8234 /* We probably can't restore the current segment, for there likely
8237 subseg_set (seg
, subseg
);
8242 encoding_length (const fragS
*start_frag
, offsetT start_off
,
8243 const char *frag_now_ptr
)
8245 unsigned int len
= 0;
8247 if (start_frag
!= frag_now
)
8249 const fragS
*fr
= start_frag
;
8254 } while (fr
&& fr
!= frag_now
);
8257 return len
- start_off
+ (frag_now_ptr
- frag_now
->fr_literal
);
8260 /* Return 1 for test, and, cmp, add, sub, inc and dec which may
8261 be macro-fused with conditional jumps. */
8264 maybe_fused_with_jcc_p (void)
8266 /* No RIP address. */
8267 if (i
.base_reg
&& i
.base_reg
->reg_num
== RegIP
)
8270 /* No VEX/EVEX encoding. */
8271 if (is_any_vex_encoding (&i
.tm
))
8274 /* and, add, sub with destination register. */
8275 if ((i
.tm
.base_opcode
>= 0x20 && i
.tm
.base_opcode
<= 0x25)
8276 || i
.tm
.base_opcode
<= 5
8277 || (i
.tm
.base_opcode
>= 0x28 && i
.tm
.base_opcode
<= 0x2d)
8278 || ((i
.tm
.base_opcode
| 3) == 0x83
8279 && ((i
.tm
.extension_opcode
| 1) == 0x5
8280 || i
.tm
.extension_opcode
== 0x0)))
8281 return (i
.types
[1].bitfield
.class == Reg
8282 || i
.types
[1].bitfield
.instance
== Accum
);
8284 /* test, cmp with any register. */
8285 if ((i
.tm
.base_opcode
| 1) == 0x85
8286 || (i
.tm
.base_opcode
| 1) == 0xa9
8287 || ((i
.tm
.base_opcode
| 1) == 0xf7
8288 && i
.tm
.extension_opcode
== 0)
8289 || (i
.tm
.base_opcode
>= 0x38 && i
.tm
.base_opcode
<= 0x3d)
8290 || ((i
.tm
.base_opcode
| 3) == 0x83
8291 && (i
.tm
.extension_opcode
== 0x7)))
8292 return (i
.types
[0].bitfield
.class == Reg
8293 || i
.types
[0].bitfield
.instance
== Accum
8294 || i
.types
[1].bitfield
.class == Reg
8295 || i
.types
[1].bitfield
.instance
== Accum
);
8297 /* inc, dec with any register. */
8298 if ((i
.tm
.cpu_flags
.bitfield
.cpuno64
8299 && (i
.tm
.base_opcode
| 0xf) == 0x4f)
8300 || ((i
.tm
.base_opcode
| 1) == 0xff
8301 && i
.tm
.extension_opcode
<= 0x1))
8302 return (i
.types
[0].bitfield
.class == Reg
8303 || i
.types
[0].bitfield
.instance
== Accum
);
8308 /* Return 1 if a FUSED_JCC_PADDING frag should be generated. */
8311 add_fused_jcc_padding_frag_p (void)
8313 /* NB: Don't work with COND_JUMP86 without i386. */
8314 if (!align_branch_power
8315 || now_seg
== absolute_section
8316 || !cpu_arch_flags
.bitfield
.cpui386
8317 || !(align_branch
& align_branch_fused_bit
))
8320 if (maybe_fused_with_jcc_p ())
8322 if (last_insn
.kind
== last_insn_other
8323 || last_insn
.seg
!= now_seg
)
8326 as_warn_where (last_insn
.file
, last_insn
.line
,
8327 _("`%s` skips -malign-branch-boundary on `%s`"),
8328 last_insn
.name
, i
.tm
.name
);
8334 /* Return 1 if a BRANCH_PREFIX frag should be generated. */
8337 add_branch_prefix_frag_p (void)
8339 /* NB: Don't work with COND_JUMP86 without i386. Don't add prefix
8340 to PadLock instructions since they include prefixes in opcode. */
8341 if (!align_branch_power
8342 || !align_branch_prefix_size
8343 || now_seg
== absolute_section
8344 || i
.tm
.cpu_flags
.bitfield
.cpupadlock
8345 || !cpu_arch_flags
.bitfield
.cpui386
)
8348 /* Don't add prefix if it is a prefix or there is no operand in case
8349 that segment prefix is special. */
8350 if (!i
.operands
|| i
.tm
.opcode_modifier
.isprefix
)
8353 if (last_insn
.kind
== last_insn_other
8354 || last_insn
.seg
!= now_seg
)
8358 as_warn_where (last_insn
.file
, last_insn
.line
,
8359 _("`%s` skips -malign-branch-boundary on `%s`"),
8360 last_insn
.name
, i
.tm
.name
);
8365 /* Return 1 if a BRANCH_PADDING frag should be generated. */
8368 add_branch_padding_frag_p (enum align_branch_kind
*branch_p
)
8372 /* NB: Don't work with COND_JUMP86 without i386. */
8373 if (!align_branch_power
8374 || now_seg
== absolute_section
8375 || !cpu_arch_flags
.bitfield
.cpui386
)
8380 /* Check for jcc and direct jmp. */
8381 if (i
.tm
.opcode_modifier
.jump
== JUMP
)
8383 if (i
.tm
.base_opcode
== JUMP_PC_RELATIVE
)
8385 *branch_p
= align_branch_jmp
;
8386 add_padding
= align_branch
& align_branch_jmp_bit
;
8390 *branch_p
= align_branch_jcc
;
8391 if ((align_branch
& align_branch_jcc_bit
))
8395 else if (is_any_vex_encoding (&i
.tm
))
8397 else if ((i
.tm
.base_opcode
| 1) == 0xc3)
8400 *branch_p
= align_branch_ret
;
8401 if ((align_branch
& align_branch_ret_bit
))
8406 /* Check for indirect jmp, direct and indirect calls. */
8407 if (i
.tm
.base_opcode
== 0xe8)
8410 *branch_p
= align_branch_call
;
8411 if ((align_branch
& align_branch_call_bit
))
8414 else if (i
.tm
.base_opcode
== 0xff
8415 && (i
.tm
.extension_opcode
== 2
8416 || i
.tm
.extension_opcode
== 4))
8418 /* Indirect call and jmp. */
8419 *branch_p
= align_branch_indirect
;
8420 if ((align_branch
& align_branch_indirect_bit
))
8427 && (i
.op
[0].disps
->X_op
== O_symbol
8428 || (i
.op
[0].disps
->X_op
== O_subtract
8429 && i
.op
[0].disps
->X_op_symbol
== GOT_symbol
)))
8431 symbolS
*s
= i
.op
[0].disps
->X_add_symbol
;
8432 /* No padding to call to global or undefined tls_get_addr. */
8433 if ((S_IS_EXTERNAL (s
) || !S_IS_DEFINED (s
))
8434 && strcmp (S_GET_NAME (s
), tls_get_addr
) == 0)
8440 && last_insn
.kind
!= last_insn_other
8441 && last_insn
.seg
== now_seg
)
8444 as_warn_where (last_insn
.file
, last_insn
.line
,
8445 _("`%s` skips -malign-branch-boundary on `%s`"),
8446 last_insn
.name
, i
.tm
.name
);
8456 fragS
*insn_start_frag
;
8457 offsetT insn_start_off
;
8458 fragS
*fragP
= NULL
;
8459 enum align_branch_kind branch
= align_branch_none
;
8461 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8462 if (IS_ELF
&& x86_used_note
)
8464 if (i
.tm
.cpu_flags
.bitfield
.cpucmov
)
8465 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_CMOV
;
8466 if (i
.tm
.cpu_flags
.bitfield
.cpusse
)
8467 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE
;
8468 if (i
.tm
.cpu_flags
.bitfield
.cpusse2
)
8469 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE2
;
8470 if (i
.tm
.cpu_flags
.bitfield
.cpusse3
)
8471 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE3
;
8472 if (i
.tm
.cpu_flags
.bitfield
.cpussse3
)
8473 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSSE3
;
8474 if (i
.tm
.cpu_flags
.bitfield
.cpusse4_1
)
8475 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE4_1
;
8476 if (i
.tm
.cpu_flags
.bitfield
.cpusse4_2
)
8477 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE4_2
;
8478 if (i
.tm
.cpu_flags
.bitfield
.cpuavx
)
8479 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX
;
8480 if (i
.tm
.cpu_flags
.bitfield
.cpuavx2
)
8481 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX2
;
8482 if (i
.tm
.cpu_flags
.bitfield
.cpufma
)
8483 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_FMA
;
8484 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512f
)
8485 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512F
;
8486 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512cd
)
8487 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512CD
;
8488 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512er
)
8489 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512ER
;
8490 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512pf
)
8491 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512PF
;
8492 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512vl
)
8493 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512VL
;
8494 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512dq
)
8495 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512DQ
;
8496 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512bw
)
8497 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512BW
;
8498 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_4fmaps
)
8499 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_4FMAPS
;
8500 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_4vnniw
)
8501 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_4VNNIW
;
8502 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_bitalg
)
8503 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_BITALG
;
8504 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512ifma
)
8505 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_IFMA
;
8506 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512vbmi
)
8507 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_VBMI
;
8508 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_vbmi2
)
8509 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_VBMI2
;
8510 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_vnni
)
8511 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_VNNI
;
8512 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_bf16
)
8513 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_BF16
;
8515 if (i
.tm
.cpu_flags
.bitfield
.cpu8087
8516 || i
.tm
.cpu_flags
.bitfield
.cpu287
8517 || i
.tm
.cpu_flags
.bitfield
.cpu387
8518 || i
.tm
.cpu_flags
.bitfield
.cpu687
8519 || i
.tm
.cpu_flags
.bitfield
.cpufisttp
)
8520 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_X87
;
8522 || i
.tm
.base_opcode
== 0xf77 /* emms */
8523 || i
.tm
.base_opcode
== 0xf0e /* femms */)
8524 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_MMX
;
8526 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XMM
;
8528 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_YMM
;
8530 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_ZMM
;
8531 if (i
.tm
.cpu_flags
.bitfield
.cpufxsr
)
8532 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_FXSR
;
8533 if (i
.tm
.cpu_flags
.bitfield
.cpuxsave
)
8534 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVE
;
8535 if (i
.tm
.cpu_flags
.bitfield
.cpuxsaveopt
)
8536 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVEOPT
;
8537 if (i
.tm
.cpu_flags
.bitfield
.cpuxsavec
)
8538 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVEC
;
8542 /* Tie dwarf2 debug info to the address at the start of the insn.
8543 We can't do this after the insn has been output as the current
8544 frag may have been closed off. eg. by frag_var. */
8545 dwarf2_emit_insn (0);
8547 insn_start_frag
= frag_now
;
8548 insn_start_off
= frag_now_fix ();
8550 if (add_branch_padding_frag_p (&branch
))
8553 /* Branch can be 8 bytes. Leave some room for prefixes. */
8554 unsigned int max_branch_padding_size
= 14;
8556 /* Align section to boundary. */
8557 record_alignment (now_seg
, align_branch_power
);
8559 /* Make room for padding. */
8560 frag_grow (max_branch_padding_size
);
8562 /* Start of the padding. */
8567 frag_var (rs_machine_dependent
, max_branch_padding_size
, 0,
8568 ENCODE_RELAX_STATE (BRANCH_PADDING
, 0),
8571 fragP
->tc_frag_data
.branch_type
= branch
;
8572 fragP
->tc_frag_data
.max_bytes
= max_branch_padding_size
;
8576 if (i
.tm
.opcode_modifier
.jump
== JUMP
)
8578 else if (i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
8579 || i
.tm
.opcode_modifier
.jump
== JUMP_DWORD
)
8581 else if (i
.tm
.opcode_modifier
.jump
== JUMP_INTERSEGMENT
)
8582 output_interseg_jump ();
8585 /* Output normal instructions here. */
8589 unsigned int prefix
;
8592 && (i
.tm
.base_opcode
== 0xfaee8
8593 || i
.tm
.base_opcode
== 0xfaef0
8594 || i
.tm
.base_opcode
== 0xfaef8))
8596 /* Encode lfence, mfence, and sfence as
8597 f0 83 04 24 00 lock addl $0x0, (%{re}sp). */
8598 offsetT val
= 0x240483f0ULL
;
8600 md_number_to_chars (p
, val
, 5);
8604 /* Some processors fail on LOCK prefix. This options makes
8605 assembler ignore LOCK prefix and serves as a workaround. */
8606 if (omit_lock_prefix
)
8608 if (i
.tm
.base_opcode
== LOCK_PREFIX_OPCODE
)
8610 i
.prefix
[LOCK_PREFIX
] = 0;
8614 /* Skip if this is a branch. */
8616 else if (add_fused_jcc_padding_frag_p ())
8618 /* Make room for padding. */
8619 frag_grow (MAX_FUSED_JCC_PADDING_SIZE
);
8624 frag_var (rs_machine_dependent
, MAX_FUSED_JCC_PADDING_SIZE
, 0,
8625 ENCODE_RELAX_STATE (FUSED_JCC_PADDING
, 0),
8628 fragP
->tc_frag_data
.branch_type
= align_branch_fused
;
8629 fragP
->tc_frag_data
.max_bytes
= MAX_FUSED_JCC_PADDING_SIZE
;
8631 else if (add_branch_prefix_frag_p ())
8633 unsigned int max_prefix_size
= align_branch_prefix_size
;
8635 /* Make room for padding. */
8636 frag_grow (max_prefix_size
);
8641 frag_var (rs_machine_dependent
, max_prefix_size
, 0,
8642 ENCODE_RELAX_STATE (BRANCH_PREFIX
, 0),
8645 fragP
->tc_frag_data
.max_bytes
= max_prefix_size
;
8648 /* Since the VEX/EVEX prefix contains the implicit prefix, we
8649 don't need the explicit prefix. */
8650 if (!i
.tm
.opcode_modifier
.vex
&& !i
.tm
.opcode_modifier
.evex
)
8652 switch (i
.tm
.opcode_length
)
8655 if (i
.tm
.base_opcode
& 0xff000000)
8657 prefix
= (i
.tm
.base_opcode
>> 24) & 0xff;
8658 if (!i
.tm
.cpu_flags
.bitfield
.cpupadlock
8659 || prefix
!= REPE_PREFIX_OPCODE
8660 || (i
.prefix
[REP_PREFIX
] != REPE_PREFIX_OPCODE
))
8661 add_prefix (prefix
);
8665 if ((i
.tm
.base_opcode
& 0xff0000) != 0)
8667 prefix
= (i
.tm
.base_opcode
>> 16) & 0xff;
8668 add_prefix (prefix
);
8674 /* Check for pseudo prefixes. */
8675 as_bad_where (insn_start_frag
->fr_file
,
8676 insn_start_frag
->fr_line
,
8677 _("pseudo prefix without instruction"));
8683 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
8684 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
8685 R_X86_64_GOTTPOFF relocation so that linker can safely
8686 perform IE->LE optimization. A dummy REX_OPCODE prefix
8687 is also needed for lea with R_X86_64_GOTPC32_TLSDESC
8688 relocation for GDesc -> IE/LE optimization. */
8689 if (x86_elf_abi
== X86_64_X32_ABI
8691 && (i
.reloc
[0] == BFD_RELOC_X86_64_GOTTPOFF
8692 || i
.reloc
[0] == BFD_RELOC_X86_64_GOTPC32_TLSDESC
)
8693 && i
.prefix
[REX_PREFIX
] == 0)
8694 add_prefix (REX_OPCODE
);
8697 /* The prefix bytes. */
8698 for (j
= ARRAY_SIZE (i
.prefix
), q
= i
.prefix
; j
> 0; j
--, q
++)
8700 FRAG_APPEND_1_CHAR (*q
);
8704 for (j
= 0, q
= i
.prefix
; j
< ARRAY_SIZE (i
.prefix
); j
++, q
++)
8709 /* REX byte is encoded in VEX prefix. */
8713 FRAG_APPEND_1_CHAR (*q
);
8716 /* There should be no other prefixes for instructions
8721 /* For EVEX instructions i.vrex should become 0 after
8722 build_evex_prefix. For VEX instructions upper 16 registers
8723 aren't available, so VREX should be 0. */
8726 /* Now the VEX prefix. */
8727 p
= frag_more (i
.vex
.length
);
8728 for (j
= 0; j
< i
.vex
.length
; j
++)
8729 p
[j
] = i
.vex
.bytes
[j
];
8732 /* Now the opcode; be careful about word order here! */
8733 if (i
.tm
.opcode_length
== 1)
8735 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
8739 switch (i
.tm
.opcode_length
)
8743 *p
++ = (i
.tm
.base_opcode
>> 24) & 0xff;
8744 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
8748 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
8758 /* Put out high byte first: can't use md_number_to_chars! */
8759 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
8760 *p
= i
.tm
.base_opcode
& 0xff;
8763 /* Now the modrm byte and sib byte (if present). */
8764 if (i
.tm
.opcode_modifier
.modrm
)
8766 FRAG_APPEND_1_CHAR ((i
.rm
.regmem
<< 0
8769 /* If i.rm.regmem == ESP (4)
8770 && i.rm.mode != (Register mode)
8772 ==> need second modrm byte. */
8773 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
8775 && !(i
.base_reg
&& i
.base_reg
->reg_type
.bitfield
.word
))
8776 FRAG_APPEND_1_CHAR ((i
.sib
.base
<< 0
8778 | i
.sib
.scale
<< 6));
8781 if (i
.disp_operands
)
8782 output_disp (insn_start_frag
, insn_start_off
);
8785 output_imm (insn_start_frag
, insn_start_off
);
8788 * frag_now_fix () returning plain abs_section_offset when we're in the
8789 * absolute section, and abs_section_offset not getting updated as data
8790 * gets added to the frag breaks the logic below.
8792 if (now_seg
!= absolute_section
)
8794 j
= encoding_length (insn_start_frag
, insn_start_off
, frag_more (0));
8796 as_warn (_("instruction length of %u bytes exceeds the limit of 15"),
8800 /* NB: Don't add prefix with GOTPC relocation since
8801 output_disp() above depends on the fixed encoding
8802 length. Can't add prefix with TLS relocation since
8803 it breaks TLS linker optimization. */
8804 unsigned int max
= i
.has_gotpc_tls_reloc
? 0 : 15 - j
;
8805 /* Prefix count on the current instruction. */
8806 unsigned int count
= i
.vex
.length
;
8808 for (k
= 0; k
< ARRAY_SIZE (i
.prefix
); k
++)
8809 /* REX byte is encoded in VEX/EVEX prefix. */
8810 if (i
.prefix
[k
] && (k
!= REX_PREFIX
|| !i
.vex
.length
))
8813 /* Count prefixes for extended opcode maps. */
8815 switch (i
.tm
.opcode_length
)
8818 if (((i
.tm
.base_opcode
>> 16) & 0xff) == 0xf)
8821 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
8833 if (((i
.tm
.base_opcode
>> 8) & 0xff) == 0xf)
8842 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
)
8845 /* Set the maximum prefix size in BRANCH_PREFIX
8847 if (fragP
->tc_frag_data
.max_bytes
> max
)
8848 fragP
->tc_frag_data
.max_bytes
= max
;
8849 if (fragP
->tc_frag_data
.max_bytes
> count
)
8850 fragP
->tc_frag_data
.max_bytes
-= count
;
8852 fragP
->tc_frag_data
.max_bytes
= 0;
8856 /* Remember the maximum prefix size in FUSED_JCC_PADDING
8858 unsigned int max_prefix_size
;
8859 if (align_branch_prefix_size
> max
)
8860 max_prefix_size
= max
;
8862 max_prefix_size
= align_branch_prefix_size
;
8863 if (max_prefix_size
> count
)
8864 fragP
->tc_frag_data
.max_prefix_length
8865 = max_prefix_size
- count
;
8868 /* Use existing segment prefix if possible. Use CS
8869 segment prefix in 64-bit mode. In 32-bit mode, use SS
8870 segment prefix with ESP/EBP base register and use DS
8871 segment prefix without ESP/EBP base register. */
8872 if (i
.prefix
[SEG_PREFIX
])
8873 fragP
->tc_frag_data
.default_prefix
= i
.prefix
[SEG_PREFIX
];
8874 else if (flag_code
== CODE_64BIT
)
8875 fragP
->tc_frag_data
.default_prefix
= CS_PREFIX_OPCODE
;
8877 && (i
.base_reg
->reg_num
== 4
8878 || i
.base_reg
->reg_num
== 5))
8879 fragP
->tc_frag_data
.default_prefix
= SS_PREFIX_OPCODE
;
8881 fragP
->tc_frag_data
.default_prefix
= DS_PREFIX_OPCODE
;
8886 /* NB: Don't work with COND_JUMP86 without i386. */
8887 if (align_branch_power
8888 && now_seg
!= absolute_section
8889 && cpu_arch_flags
.bitfield
.cpui386
)
8891 /* Terminate each frag so that we can add prefix and check for
8893 frag_wane (frag_now
);
8900 pi ("" /*line*/, &i
);
8902 #endif /* DEBUG386 */
8905 /* Return the size of the displacement operand N. */
8908 disp_size (unsigned int n
)
8912 if (i
.types
[n
].bitfield
.disp64
)
8914 else if (i
.types
[n
].bitfield
.disp8
)
8916 else if (i
.types
[n
].bitfield
.disp16
)
8921 /* Return the size of the immediate operand N. */
8924 imm_size (unsigned int n
)
8927 if (i
.types
[n
].bitfield
.imm64
)
8929 else if (i
.types
[n
].bitfield
.imm8
|| i
.types
[n
].bitfield
.imm8s
)
8931 else if (i
.types
[n
].bitfield
.imm16
)
8937 output_disp (fragS
*insn_start_frag
, offsetT insn_start_off
)
8942 for (n
= 0; n
< i
.operands
; n
++)
8944 if (operand_type_check (i
.types
[n
], disp
))
8946 if (i
.op
[n
].disps
->X_op
== O_constant
)
8948 int size
= disp_size (n
);
8949 offsetT val
= i
.op
[n
].disps
->X_add_number
;
8951 val
= offset_in_range (val
>> (size
== 1 ? i
.memshift
: 0),
8953 p
= frag_more (size
);
8954 md_number_to_chars (p
, val
, size
);
8958 enum bfd_reloc_code_real reloc_type
;
8959 int size
= disp_size (n
);
8960 int sign
= i
.types
[n
].bitfield
.disp32s
;
8961 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
8964 /* We can't have 8 bit displacement here. */
8965 gas_assert (!i
.types
[n
].bitfield
.disp8
);
8967 /* The PC relative address is computed relative
8968 to the instruction boundary, so in case immediate
8969 fields follows, we need to adjust the value. */
8970 if (pcrel
&& i
.imm_operands
)
8975 for (n1
= 0; n1
< i
.operands
; n1
++)
8976 if (operand_type_check (i
.types
[n1
], imm
))
8978 /* Only one immediate is allowed for PC
8979 relative address. */
8980 gas_assert (sz
== 0);
8982 i
.op
[n
].disps
->X_add_number
-= sz
;
8984 /* We should find the immediate. */
8985 gas_assert (sz
!= 0);
8988 p
= frag_more (size
);
8989 reloc_type
= reloc (size
, pcrel
, sign
, i
.reloc
[n
]);
8991 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
8992 && (((reloc_type
== BFD_RELOC_32
8993 || reloc_type
== BFD_RELOC_X86_64_32S
8994 || (reloc_type
== BFD_RELOC_64
8996 && (i
.op
[n
].disps
->X_op
== O_symbol
8997 || (i
.op
[n
].disps
->X_op
== O_add
8998 && ((symbol_get_value_expression
8999 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
9001 || reloc_type
== BFD_RELOC_32_PCREL
))
9005 reloc_type
= BFD_RELOC_386_GOTPC
;
9006 i
.has_gotpc_tls_reloc
= TRUE
;
9007 i
.op
[n
].imms
->X_add_number
+=
9008 encoding_length (insn_start_frag
, insn_start_off
, p
);
9010 else if (reloc_type
== BFD_RELOC_64
)
9011 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
9013 /* Don't do the adjustment for x86-64, as there
9014 the pcrel addressing is relative to the _next_
9015 insn, and that is taken care of in other code. */
9016 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
9018 else if (align_branch_power
)
9022 case BFD_RELOC_386_TLS_GD
:
9023 case BFD_RELOC_386_TLS_LDM
:
9024 case BFD_RELOC_386_TLS_IE
:
9025 case BFD_RELOC_386_TLS_IE_32
:
9026 case BFD_RELOC_386_TLS_GOTIE
:
9027 case BFD_RELOC_386_TLS_GOTDESC
:
9028 case BFD_RELOC_386_TLS_DESC_CALL
:
9029 case BFD_RELOC_X86_64_TLSGD
:
9030 case BFD_RELOC_X86_64_TLSLD
:
9031 case BFD_RELOC_X86_64_GOTTPOFF
:
9032 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
9033 case BFD_RELOC_X86_64_TLSDESC_CALL
:
9034 i
.has_gotpc_tls_reloc
= TRUE
;
9039 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
9040 size
, i
.op
[n
].disps
, pcrel
,
9042 /* Check for "call/jmp *mem", "mov mem, %reg",
9043 "test %reg, mem" and "binop mem, %reg" where binop
9044 is one of adc, add, and, cmp, or, sbb, sub, xor
9045 instructions without data prefix. Always generate
9046 R_386_GOT32X for "sym*GOT" operand in 32-bit mode. */
9047 if (i
.prefix
[DATA_PREFIX
] == 0
9048 && (generate_relax_relocations
9051 && i
.rm
.regmem
== 5))
9053 || (i
.rm
.mode
== 0 && i
.rm
.regmem
== 5))
9054 && !is_any_vex_encoding(&i
.tm
)
9055 && ((i
.operands
== 1
9056 && i
.tm
.base_opcode
== 0xff
9057 && (i
.rm
.reg
== 2 || i
.rm
.reg
== 4))
9059 && (i
.tm
.base_opcode
== 0x8b
9060 || i
.tm
.base_opcode
== 0x85
9061 || (i
.tm
.base_opcode
& ~0x38) == 0x03))))
9065 fixP
->fx_tcbit
= i
.rex
!= 0;
9067 && (i
.base_reg
->reg_num
== RegIP
))
9068 fixP
->fx_tcbit2
= 1;
9071 fixP
->fx_tcbit2
= 1;
9079 output_imm (fragS
*insn_start_frag
, offsetT insn_start_off
)
9084 for (n
= 0; n
< i
.operands
; n
++)
9086 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
9087 if (i
.rounding
&& (int) n
== i
.rounding
->operand
)
9090 if (operand_type_check (i
.types
[n
], imm
))
9092 if (i
.op
[n
].imms
->X_op
== O_constant
)
9094 int size
= imm_size (n
);
9097 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
9099 p
= frag_more (size
);
9100 md_number_to_chars (p
, val
, size
);
9104 /* Not absolute_section.
9105 Need a 32-bit fixup (don't support 8bit
9106 non-absolute imms). Try to support other
9108 enum bfd_reloc_code_real reloc_type
;
9109 int size
= imm_size (n
);
9112 if (i
.types
[n
].bitfield
.imm32s
9113 && (i
.suffix
== QWORD_MNEM_SUFFIX
9114 || (!i
.suffix
&& i
.tm
.opcode_modifier
.no_lsuf
)))
9119 p
= frag_more (size
);
9120 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
9122 /* This is tough to explain. We end up with this one if we
9123 * have operands that look like
9124 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
9125 * obtain the absolute address of the GOT, and it is strongly
9126 * preferable from a performance point of view to avoid using
9127 * a runtime relocation for this. The actual sequence of
9128 * instructions often look something like:
9133 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
9135 * The call and pop essentially return the absolute address
9136 * of the label .L66 and store it in %ebx. The linker itself
9137 * will ultimately change the first operand of the addl so
9138 * that %ebx points to the GOT, but to keep things simple, the
9139 * .o file must have this operand set so that it generates not
9140 * the absolute address of .L66, but the absolute address of
9141 * itself. This allows the linker itself simply treat a GOTPC
9142 * relocation as asking for a pcrel offset to the GOT to be
9143 * added in, and the addend of the relocation is stored in the
9144 * operand field for the instruction itself.
9146 * Our job here is to fix the operand so that it would add
9147 * the correct offset so that %ebx would point to itself. The
9148 * thing that is tricky is that .-.L66 will point to the
9149 * beginning of the instruction, so we need to further modify
9150 * the operand so that it will point to itself. There are
9151 * other cases where you have something like:
9153 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
9155 * and here no correction would be required. Internally in
9156 * the assembler we treat operands of this form as not being
9157 * pcrel since the '.' is explicitly mentioned, and I wonder
9158 * whether it would simplify matters to do it this way. Who
9159 * knows. In earlier versions of the PIC patches, the
9160 * pcrel_adjust field was used to store the correction, but
9161 * since the expression is not pcrel, I felt it would be
9162 * confusing to do it this way. */
9164 if ((reloc_type
== BFD_RELOC_32
9165 || reloc_type
== BFD_RELOC_X86_64_32S
9166 || reloc_type
== BFD_RELOC_64
)
9168 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
9169 && (i
.op
[n
].imms
->X_op
== O_symbol
9170 || (i
.op
[n
].imms
->X_op
== O_add
9171 && ((symbol_get_value_expression
9172 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
9176 reloc_type
= BFD_RELOC_386_GOTPC
;
9178 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
9180 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
9181 i
.has_gotpc_tls_reloc
= TRUE
;
9182 i
.op
[n
].imms
->X_add_number
+=
9183 encoding_length (insn_start_frag
, insn_start_off
, p
);
9185 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
9186 i
.op
[n
].imms
, 0, reloc_type
);
9192 /* x86_cons_fix_new is called via the expression parsing code when a
9193 reloc is needed. We use this hook to get the correct .got reloc. */
9194 static int cons_sign
= -1;
9197 x86_cons_fix_new (fragS
*frag
, unsigned int off
, unsigned int len
,
9198 expressionS
*exp
, bfd_reloc_code_real_type r
)
9200 r
= reloc (len
, 0, cons_sign
, r
);
9203 if (exp
->X_op
== O_secrel
)
9205 exp
->X_op
= O_symbol
;
9206 r
= BFD_RELOC_32_SECREL
;
9210 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
9213 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
9214 purpose of the `.dc.a' internal pseudo-op. */
9217 x86_address_bytes (void)
9219 if ((stdoutput
->arch_info
->mach
& bfd_mach_x64_32
))
9221 return stdoutput
->arch_info
->bits_per_address
/ 8;
9224 #if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
9226 # define lex_got(reloc, adjust, types) NULL
9228 /* Parse operands of the form
9229 <symbol>@GOTOFF+<nnn>
9230 and similar .plt or .got references.
9232 If we find one, set up the correct relocation in RELOC and copy the
9233 input string, minus the `@GOTOFF' into a malloc'd buffer for
9234 parsing by the calling routine. Return this buffer, and if ADJUST
9235 is non-null set it to the length of the string we removed from the
9236 input line. Otherwise return NULL. */
9238 lex_got (enum bfd_reloc_code_real
*rel
,
9240 i386_operand_type
*types
)
9242 /* Some of the relocations depend on the size of what field is to
9243 be relocated. But in our callers i386_immediate and i386_displacement
9244 we don't yet know the operand size (this will be set by insn
9245 matching). Hence we record the word32 relocation here,
9246 and adjust the reloc according to the real size in reloc(). */
9247 static const struct {
9250 const enum bfd_reloc_code_real rel
[2];
9251 const i386_operand_type types64
;
9253 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9254 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32
,
9256 OPERAND_TYPE_IMM32_64
},
9258 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real
,
9259 BFD_RELOC_X86_64_PLTOFF64
},
9260 OPERAND_TYPE_IMM64
},
9261 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32
,
9262 BFD_RELOC_X86_64_PLT32
},
9263 OPERAND_TYPE_IMM32_32S_DISP32
},
9264 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real
,
9265 BFD_RELOC_X86_64_GOTPLT64
},
9266 OPERAND_TYPE_IMM64_DISP64
},
9267 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF
,
9268 BFD_RELOC_X86_64_GOTOFF64
},
9269 OPERAND_TYPE_IMM64_DISP64
},
9270 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real
,
9271 BFD_RELOC_X86_64_GOTPCREL
},
9272 OPERAND_TYPE_IMM32_32S_DISP32
},
9273 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD
,
9274 BFD_RELOC_X86_64_TLSGD
},
9275 OPERAND_TYPE_IMM32_32S_DISP32
},
9276 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM
,
9277 _dummy_first_bfd_reloc_code_real
},
9278 OPERAND_TYPE_NONE
},
9279 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real
,
9280 BFD_RELOC_X86_64_TLSLD
},
9281 OPERAND_TYPE_IMM32_32S_DISP32
},
9282 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32
,
9283 BFD_RELOC_X86_64_GOTTPOFF
},
9284 OPERAND_TYPE_IMM32_32S_DISP32
},
9285 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32
,
9286 BFD_RELOC_X86_64_TPOFF32
},
9287 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
9288 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE
,
9289 _dummy_first_bfd_reloc_code_real
},
9290 OPERAND_TYPE_NONE
},
9291 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32
,
9292 BFD_RELOC_X86_64_DTPOFF32
},
9293 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
9294 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE
,
9295 _dummy_first_bfd_reloc_code_real
},
9296 OPERAND_TYPE_NONE
},
9297 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE
,
9298 _dummy_first_bfd_reloc_code_real
},
9299 OPERAND_TYPE_NONE
},
9300 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32
,
9301 BFD_RELOC_X86_64_GOT32
},
9302 OPERAND_TYPE_IMM32_32S_64_DISP32
},
9303 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC
,
9304 BFD_RELOC_X86_64_GOTPC32_TLSDESC
},
9305 OPERAND_TYPE_IMM32_32S_DISP32
},
9306 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL
,
9307 BFD_RELOC_X86_64_TLSDESC_CALL
},
9308 OPERAND_TYPE_IMM32_32S_DISP32
},
9313 #if defined (OBJ_MAYBE_ELF)
9318 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
9319 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
9322 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
9324 int len
= gotrel
[j
].len
;
9325 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
9327 if (gotrel
[j
].rel
[object_64bit
] != 0)
9330 char *tmpbuf
, *past_reloc
;
9332 *rel
= gotrel
[j
].rel
[object_64bit
];
9336 if (flag_code
!= CODE_64BIT
)
9338 types
->bitfield
.imm32
= 1;
9339 types
->bitfield
.disp32
= 1;
9342 *types
= gotrel
[j
].types64
;
9345 if (j
!= 0 && GOT_symbol
== NULL
)
9346 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
9348 /* The length of the first part of our input line. */
9349 first
= cp
- input_line_pointer
;
9351 /* The second part goes from after the reloc token until
9352 (and including) an end_of_line char or comma. */
9353 past_reloc
= cp
+ 1 + len
;
9355 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
9357 second
= cp
+ 1 - past_reloc
;
9359 /* Allocate and copy string. The trailing NUL shouldn't
9360 be necessary, but be safe. */
9361 tmpbuf
= XNEWVEC (char, first
+ second
+ 2);
9362 memcpy (tmpbuf
, input_line_pointer
, first
);
9363 if (second
!= 0 && *past_reloc
!= ' ')
9364 /* Replace the relocation token with ' ', so that
9365 errors like foo@GOTOFF1 will be detected. */
9366 tmpbuf
[first
++] = ' ';
9368 /* Increment length by 1 if the relocation token is
9373 memcpy (tmpbuf
+ first
, past_reloc
, second
);
9374 tmpbuf
[first
+ second
] = '\0';
9378 as_bad (_("@%s reloc is not supported with %d-bit output format"),
9379 gotrel
[j
].str
, 1 << (5 + object_64bit
));
9384 /* Might be a symbol version string. Don't as_bad here. */
9393 /* Parse operands of the form
9394 <symbol>@SECREL32+<nnn>
9396 If we find one, set up the correct relocation in RELOC and copy the
9397 input string, minus the `@SECREL32' into a malloc'd buffer for
9398 parsing by the calling routine. Return this buffer, and if ADJUST
9399 is non-null set it to the length of the string we removed from the
9400 input line. Otherwise return NULL.
9402 This function is copied from the ELF version above adjusted for PE targets. */
9405 lex_got (enum bfd_reloc_code_real
*rel ATTRIBUTE_UNUSED
,
9406 int *adjust ATTRIBUTE_UNUSED
,
9407 i386_operand_type
*types
)
9413 const enum bfd_reloc_code_real rel
[2];
9414 const i386_operand_type types64
;
9418 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL
,
9419 BFD_RELOC_32_SECREL
},
9420 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
9426 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
9427 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
9430 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
9432 int len
= gotrel
[j
].len
;
9434 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
9436 if (gotrel
[j
].rel
[object_64bit
] != 0)
9439 char *tmpbuf
, *past_reloc
;
9441 *rel
= gotrel
[j
].rel
[object_64bit
];
9447 if (flag_code
!= CODE_64BIT
)
9449 types
->bitfield
.imm32
= 1;
9450 types
->bitfield
.disp32
= 1;
9453 *types
= gotrel
[j
].types64
;
9456 /* The length of the first part of our input line. */
9457 first
= cp
- input_line_pointer
;
9459 /* The second part goes from after the reloc token until
9460 (and including) an end_of_line char or comma. */
9461 past_reloc
= cp
+ 1 + len
;
9463 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
9465 second
= cp
+ 1 - past_reloc
;
9467 /* Allocate and copy string. The trailing NUL shouldn't
9468 be necessary, but be safe. */
9469 tmpbuf
= XNEWVEC (char, first
+ second
+ 2);
9470 memcpy (tmpbuf
, input_line_pointer
, first
);
9471 if (second
!= 0 && *past_reloc
!= ' ')
9472 /* Replace the relocation token with ' ', so that
9473 errors like foo@SECLREL321 will be detected. */
9474 tmpbuf
[first
++] = ' ';
9475 memcpy (tmpbuf
+ first
, past_reloc
, second
);
9476 tmpbuf
[first
+ second
] = '\0';
9480 as_bad (_("@%s reloc is not supported with %d-bit output format"),
9481 gotrel
[j
].str
, 1 << (5 + object_64bit
));
9486 /* Might be a symbol version string. Don't as_bad here. */
9492 bfd_reloc_code_real_type
9493 x86_cons (expressionS
*exp
, int size
)
9495 bfd_reloc_code_real_type got_reloc
= NO_RELOC
;
9497 intel_syntax
= -intel_syntax
;
9500 if (size
== 4 || (object_64bit
&& size
== 8))
9502 /* Handle @GOTOFF and the like in an expression. */
9504 char *gotfree_input_line
;
9507 save
= input_line_pointer
;
9508 gotfree_input_line
= lex_got (&got_reloc
, &adjust
, NULL
);
9509 if (gotfree_input_line
)
9510 input_line_pointer
= gotfree_input_line
;
9514 if (gotfree_input_line
)
9516 /* expression () has merrily parsed up to the end of line,
9517 or a comma - in the wrong buffer. Transfer how far
9518 input_line_pointer has moved to the right buffer. */
9519 input_line_pointer
= (save
9520 + (input_line_pointer
- gotfree_input_line
)
9522 free (gotfree_input_line
);
9523 if (exp
->X_op
== O_constant
9524 || exp
->X_op
== O_absent
9525 || exp
->X_op
== O_illegal
9526 || exp
->X_op
== O_register
9527 || exp
->X_op
== O_big
)
9529 char c
= *input_line_pointer
;
9530 *input_line_pointer
= 0;
9531 as_bad (_("missing or invalid expression `%s'"), save
);
9532 *input_line_pointer
= c
;
9534 else if ((got_reloc
== BFD_RELOC_386_PLT32
9535 || got_reloc
== BFD_RELOC_X86_64_PLT32
)
9536 && exp
->X_op
!= O_symbol
)
9538 char c
= *input_line_pointer
;
9539 *input_line_pointer
= 0;
9540 as_bad (_("invalid PLT expression `%s'"), save
);
9541 *input_line_pointer
= c
;
9548 intel_syntax
= -intel_syntax
;
9551 i386_intel_simplify (exp
);
9557 signed_cons (int size
)
9559 if (flag_code
== CODE_64BIT
)
9567 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
9574 if (exp
.X_op
== O_symbol
)
9575 exp
.X_op
= O_secrel
;
9577 emit_expr (&exp
, 4);
9579 while (*input_line_pointer
++ == ',');
9581 input_line_pointer
--;
9582 demand_empty_rest_of_line ();
9586 /* Handle Vector operations. */
9589 check_VecOperations (char *op_string
, char *op_end
)
9591 const reg_entry
*mask
;
9596 && (op_end
== NULL
|| op_string
< op_end
))
9599 if (*op_string
== '{')
9603 /* Check broadcasts. */
9604 if (strncmp (op_string
, "1to", 3) == 0)
9609 goto duplicated_vec_op
;
9612 if (*op_string
== '8')
9614 else if (*op_string
== '4')
9616 else if (*op_string
== '2')
9618 else if (*op_string
== '1'
9619 && *(op_string
+1) == '6')
9626 as_bad (_("Unsupported broadcast: `%s'"), saved
);
9631 broadcast_op
.type
= bcst_type
;
9632 broadcast_op
.operand
= this_operand
;
9633 broadcast_op
.bytes
= 0;
9634 i
.broadcast
= &broadcast_op
;
9636 /* Check masking operation. */
9637 else if ((mask
= parse_register (op_string
, &end_op
)) != NULL
)
9639 /* k0 can't be used for write mask. */
9640 if (mask
->reg_type
.bitfield
.class != RegMask
|| !mask
->reg_num
)
9642 as_bad (_("`%s%s' can't be used for write mask"),
9643 register_prefix
, mask
->reg_name
);
9649 mask_op
.mask
= mask
;
9650 mask_op
.zeroing
= 0;
9651 mask_op
.operand
= this_operand
;
9657 goto duplicated_vec_op
;
9659 i
.mask
->mask
= mask
;
9661 /* Only "{z}" is allowed here. No need to check
9662 zeroing mask explicitly. */
9663 if (i
.mask
->operand
!= this_operand
)
9665 as_bad (_("invalid write mask `%s'"), saved
);
9672 /* Check zeroing-flag for masking operation. */
9673 else if (*op_string
== 'z')
9677 mask_op
.mask
= NULL
;
9678 mask_op
.zeroing
= 1;
9679 mask_op
.operand
= this_operand
;
9684 if (i
.mask
->zeroing
)
9687 as_bad (_("duplicated `%s'"), saved
);
9691 i
.mask
->zeroing
= 1;
9693 /* Only "{%k}" is allowed here. No need to check mask
9694 register explicitly. */
9695 if (i
.mask
->operand
!= this_operand
)
9697 as_bad (_("invalid zeroing-masking `%s'"),
9706 goto unknown_vec_op
;
9708 if (*op_string
!= '}')
9710 as_bad (_("missing `}' in `%s'"), saved
);
9715 /* Strip whitespace since the addition of pseudo prefixes
9716 changed how the scrubber treats '{'. */
9717 if (is_space_char (*op_string
))
9723 /* We don't know this one. */
9724 as_bad (_("unknown vector operation: `%s'"), saved
);
9728 if (i
.mask
&& i
.mask
->zeroing
&& !i
.mask
->mask
)
9730 as_bad (_("zeroing-masking only allowed with write mask"));
9738 i386_immediate (char *imm_start
)
9740 char *save_input_line_pointer
;
9741 char *gotfree_input_line
;
9744 i386_operand_type types
;
9746 operand_type_set (&types
, ~0);
9748 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
9750 as_bad (_("at most %d immediate operands are allowed"),
9751 MAX_IMMEDIATE_OPERANDS
);
9755 exp
= &im_expressions
[i
.imm_operands
++];
9756 i
.op
[this_operand
].imms
= exp
;
9758 if (is_space_char (*imm_start
))
9761 save_input_line_pointer
= input_line_pointer
;
9762 input_line_pointer
= imm_start
;
9764 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
9765 if (gotfree_input_line
)
9766 input_line_pointer
= gotfree_input_line
;
9768 exp_seg
= expression (exp
);
9772 /* Handle vector operations. */
9773 if (*input_line_pointer
== '{')
9775 input_line_pointer
= check_VecOperations (input_line_pointer
,
9777 if (input_line_pointer
== NULL
)
9781 if (*input_line_pointer
)
9782 as_bad (_("junk `%s' after expression"), input_line_pointer
);
9784 input_line_pointer
= save_input_line_pointer
;
9785 if (gotfree_input_line
)
9787 free (gotfree_input_line
);
9789 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
9790 exp
->X_op
= O_illegal
;
9793 return i386_finalize_immediate (exp_seg
, exp
, types
, imm_start
);
9797 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
9798 i386_operand_type types
, const char *imm_start
)
9800 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_illegal
|| exp
->X_op
== O_big
)
9803 as_bad (_("missing or invalid immediate expression `%s'"),
9807 else if (exp
->X_op
== O_constant
)
9809 /* Size it properly later. */
9810 i
.types
[this_operand
].bitfield
.imm64
= 1;
9811 /* If not 64bit, sign extend val. */
9812 if (flag_code
!= CODE_64BIT
9813 && (exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
9815 = (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
9817 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
9818 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
9819 && exp_seg
!= absolute_section
9820 && exp_seg
!= text_section
9821 && exp_seg
!= data_section
9822 && exp_seg
!= bss_section
9823 && exp_seg
!= undefined_section
9824 && !bfd_is_com_section (exp_seg
))
9826 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
9830 else if (!intel_syntax
&& exp_seg
== reg_section
)
9833 as_bad (_("illegal immediate register operand %s"), imm_start
);
9838 /* This is an address. The size of the address will be
9839 determined later, depending on destination register,
9840 suffix, or the default for the section. */
9841 i
.types
[this_operand
].bitfield
.imm8
= 1;
9842 i
.types
[this_operand
].bitfield
.imm16
= 1;
9843 i
.types
[this_operand
].bitfield
.imm32
= 1;
9844 i
.types
[this_operand
].bitfield
.imm32s
= 1;
9845 i
.types
[this_operand
].bitfield
.imm64
= 1;
9846 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
9854 i386_scale (char *scale
)
9857 char *save
= input_line_pointer
;
9859 input_line_pointer
= scale
;
9860 val
= get_absolute_expression ();
9865 i
.log2_scale_factor
= 0;
9868 i
.log2_scale_factor
= 1;
9871 i
.log2_scale_factor
= 2;
9874 i
.log2_scale_factor
= 3;
9878 char sep
= *input_line_pointer
;
9880 *input_line_pointer
= '\0';
9881 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
9883 *input_line_pointer
= sep
;
9884 input_line_pointer
= save
;
9888 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
9890 as_warn (_("scale factor of %d without an index register"),
9891 1 << i
.log2_scale_factor
);
9892 i
.log2_scale_factor
= 0;
9894 scale
= input_line_pointer
;
9895 input_line_pointer
= save
;
9900 i386_displacement (char *disp_start
, char *disp_end
)
9904 char *save_input_line_pointer
;
9905 char *gotfree_input_line
;
9907 i386_operand_type bigdisp
, types
= anydisp
;
9910 if (i
.disp_operands
== MAX_MEMORY_OPERANDS
)
9912 as_bad (_("at most %d displacement operands are allowed"),
9913 MAX_MEMORY_OPERANDS
);
9917 operand_type_set (&bigdisp
, 0);
9919 || i
.types
[this_operand
].bitfield
.baseindex
9920 || (current_templates
->start
->opcode_modifier
.jump
!= JUMP
9921 && current_templates
->start
->opcode_modifier
.jump
!= JUMP_DWORD
))
9923 i386_addressing_mode ();
9924 override
= (i
.prefix
[ADDR_PREFIX
] != 0);
9925 if (flag_code
== CODE_64BIT
)
9929 bigdisp
.bitfield
.disp32s
= 1;
9930 bigdisp
.bitfield
.disp64
= 1;
9933 bigdisp
.bitfield
.disp32
= 1;
9935 else if ((flag_code
== CODE_16BIT
) ^ override
)
9936 bigdisp
.bitfield
.disp16
= 1;
9938 bigdisp
.bitfield
.disp32
= 1;
9942 /* For PC-relative branches, the width of the displacement may be
9943 dependent upon data size, but is never dependent upon address size.
9944 Also make sure to not unintentionally match against a non-PC-relative
9946 static templates aux_templates
;
9947 const insn_template
*t
= current_templates
->start
;
9948 bfd_boolean has_intel64
= FALSE
;
9950 aux_templates
.start
= t
;
9951 while (++t
< current_templates
->end
)
9953 if (t
->opcode_modifier
.jump
9954 != current_templates
->start
->opcode_modifier
.jump
)
9956 if ((t
->opcode_modifier
.isa64
>= INTEL64
))
9959 if (t
< current_templates
->end
)
9961 aux_templates
.end
= t
;
9962 current_templates
= &aux_templates
;
9965 override
= (i
.prefix
[DATA_PREFIX
] != 0);
9966 if (flag_code
== CODE_64BIT
)
9968 if ((override
|| i
.suffix
== WORD_MNEM_SUFFIX
)
9969 && (!intel64
|| !has_intel64
))
9970 bigdisp
.bitfield
.disp16
= 1;
9972 bigdisp
.bitfield
.disp32s
= 1;
9977 override
= (i
.suffix
== (flag_code
!= CODE_16BIT
9979 : LONG_MNEM_SUFFIX
));
9980 bigdisp
.bitfield
.disp32
= 1;
9981 if ((flag_code
== CODE_16BIT
) ^ override
)
9983 bigdisp
.bitfield
.disp32
= 0;
9984 bigdisp
.bitfield
.disp16
= 1;
9988 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
9991 exp
= &disp_expressions
[i
.disp_operands
];
9992 i
.op
[this_operand
].disps
= exp
;
9994 save_input_line_pointer
= input_line_pointer
;
9995 input_line_pointer
= disp_start
;
9996 END_STRING_AND_SAVE (disp_end
);
9998 #ifndef GCC_ASM_O_HACK
9999 #define GCC_ASM_O_HACK 0
10002 END_STRING_AND_SAVE (disp_end
+ 1);
10003 if (i
.types
[this_operand
].bitfield
.baseIndex
10004 && displacement_string_end
[-1] == '+')
10006 /* This hack is to avoid a warning when using the "o"
10007 constraint within gcc asm statements.
10010 #define _set_tssldt_desc(n,addr,limit,type) \
10011 __asm__ __volatile__ ( \
10012 "movw %w2,%0\n\t" \
10013 "movw %w1,2+%0\n\t" \
10014 "rorl $16,%1\n\t" \
10015 "movb %b1,4+%0\n\t" \
10016 "movb %4,5+%0\n\t" \
10017 "movb $0,6+%0\n\t" \
10018 "movb %h1,7+%0\n\t" \
10020 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
10022 This works great except that the output assembler ends
10023 up looking a bit weird if it turns out that there is
10024 no offset. You end up producing code that looks like:
10037 So here we provide the missing zero. */
10039 *displacement_string_end
= '0';
10042 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
10043 if (gotfree_input_line
)
10044 input_line_pointer
= gotfree_input_line
;
10046 exp_seg
= expression (exp
);
10048 SKIP_WHITESPACE ();
10049 if (*input_line_pointer
)
10050 as_bad (_("junk `%s' after expression"), input_line_pointer
);
10052 RESTORE_END_STRING (disp_end
+ 1);
10054 input_line_pointer
= save_input_line_pointer
;
10055 if (gotfree_input_line
)
10057 free (gotfree_input_line
);
10059 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
10060 exp
->X_op
= O_illegal
;
10063 ret
= i386_finalize_displacement (exp_seg
, exp
, types
, disp_start
);
10065 RESTORE_END_STRING (disp_end
);
10071 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
10072 i386_operand_type types
, const char *disp_start
)
10074 i386_operand_type bigdisp
;
10077 /* We do this to make sure that the section symbol is in
10078 the symbol table. We will ultimately change the relocation
10079 to be relative to the beginning of the section. */
10080 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
10081 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
10082 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
10084 if (exp
->X_op
!= O_symbol
)
10087 if (S_IS_LOCAL (exp
->X_add_symbol
)
10088 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
10089 && S_GET_SEGMENT (exp
->X_add_symbol
) != expr_section
)
10090 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
10091 exp
->X_op
= O_subtract
;
10092 exp
->X_op_symbol
= GOT_symbol
;
10093 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
10094 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
10095 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
10096 i
.reloc
[this_operand
] = BFD_RELOC_64
;
10098 i
.reloc
[this_operand
] = BFD_RELOC_32
;
10101 else if (exp
->X_op
== O_absent
10102 || exp
->X_op
== O_illegal
10103 || exp
->X_op
== O_big
)
10106 as_bad (_("missing or invalid displacement expression `%s'"),
10111 else if (flag_code
== CODE_64BIT
10112 && !i
.prefix
[ADDR_PREFIX
]
10113 && exp
->X_op
== O_constant
)
10115 /* Since displacement is signed extended to 64bit, don't allow
10116 disp32 and turn off disp32s if they are out of range. */
10117 i
.types
[this_operand
].bitfield
.disp32
= 0;
10118 if (!fits_in_signed_long (exp
->X_add_number
))
10120 i
.types
[this_operand
].bitfield
.disp32s
= 0;
10121 if (i
.types
[this_operand
].bitfield
.baseindex
)
10123 as_bad (_("0x%lx out range of signed 32bit displacement"),
10124 (long) exp
->X_add_number
);
10130 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
10131 else if (exp
->X_op
!= O_constant
10132 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
10133 && exp_seg
!= absolute_section
10134 && exp_seg
!= text_section
10135 && exp_seg
!= data_section
10136 && exp_seg
!= bss_section
10137 && exp_seg
!= undefined_section
10138 && !bfd_is_com_section (exp_seg
))
10140 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
10145 if (current_templates
->start
->opcode_modifier
.jump
== JUMP_BYTE
10146 /* Constants get taken care of by optimize_disp(). */
10147 && exp
->X_op
!= O_constant
)
10148 i
.types
[this_operand
].bitfield
.disp8
= 1;
10150 /* Check if this is a displacement only operand. */
10151 bigdisp
= i
.types
[this_operand
];
10152 bigdisp
.bitfield
.disp8
= 0;
10153 bigdisp
.bitfield
.disp16
= 0;
10154 bigdisp
.bitfield
.disp32
= 0;
10155 bigdisp
.bitfield
.disp32s
= 0;
10156 bigdisp
.bitfield
.disp64
= 0;
10157 if (operand_type_all_zero (&bigdisp
))
10158 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
10164 /* Return the active addressing mode, taking address override and
10165 registers forming the address into consideration. Update the
10166 address override prefix if necessary. */
10168 static enum flag_code
10169 i386_addressing_mode (void)
10171 enum flag_code addr_mode
;
10173 if (i
.prefix
[ADDR_PREFIX
])
10174 addr_mode
= flag_code
== CODE_32BIT
? CODE_16BIT
: CODE_32BIT
;
10177 addr_mode
= flag_code
;
10179 #if INFER_ADDR_PREFIX
10180 if (i
.mem_operands
== 0)
10182 /* Infer address prefix from the first memory operand. */
10183 const reg_entry
*addr_reg
= i
.base_reg
;
10185 if (addr_reg
== NULL
)
10186 addr_reg
= i
.index_reg
;
10190 if (addr_reg
->reg_type
.bitfield
.dword
)
10191 addr_mode
= CODE_32BIT
;
10192 else if (flag_code
!= CODE_64BIT
10193 && addr_reg
->reg_type
.bitfield
.word
)
10194 addr_mode
= CODE_16BIT
;
10196 if (addr_mode
!= flag_code
)
10198 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
10200 /* Change the size of any displacement too. At most one
10201 of Disp16 or Disp32 is set.
10202 FIXME. There doesn't seem to be any real need for
10203 separate Disp16 and Disp32 flags. The same goes for
10204 Imm16 and Imm32. Removing them would probably clean
10205 up the code quite a lot. */
10206 if (flag_code
!= CODE_64BIT
10207 && (i
.types
[this_operand
].bitfield
.disp16
10208 || i
.types
[this_operand
].bitfield
.disp32
))
10209 i
.types
[this_operand
]
10210 = operand_type_xor (i
.types
[this_operand
], disp16_32
);
10220 /* Make sure the memory operand we've been dealt is valid.
10221 Return 1 on success, 0 on a failure. */
10224 i386_index_check (const char *operand_string
)
10226 const char *kind
= "base/index";
10227 enum flag_code addr_mode
= i386_addressing_mode ();
10229 if (current_templates
->start
->opcode_modifier
.isstring
10230 && !current_templates
->start
->cpu_flags
.bitfield
.cpupadlock
10231 && (current_templates
->end
[-1].opcode_modifier
.isstring
10232 || i
.mem_operands
))
10234 /* Memory operands of string insns are special in that they only allow
10235 a single register (rDI, rSI, or rBX) as their memory address. */
10236 const reg_entry
*expected_reg
;
10237 static const char *di_si
[][2] =
10243 static const char *bx
[] = { "ebx", "bx", "rbx" };
10245 kind
= "string address";
10247 if (current_templates
->start
->opcode_modifier
.repprefixok
)
10249 int es_op
= current_templates
->end
[-1].opcode_modifier
.isstring
10250 - IS_STRING_ES_OP0
;
10253 if (!current_templates
->end
[-1].operand_types
[0].bitfield
.baseindex
10254 || ((!i
.mem_operands
!= !intel_syntax
)
10255 && current_templates
->end
[-1].operand_types
[1]
10256 .bitfield
.baseindex
))
10258 expected_reg
= hash_find (reg_hash
, di_si
[addr_mode
][op
== es_op
]);
10261 expected_reg
= hash_find (reg_hash
, bx
[addr_mode
]);
10263 if (i
.base_reg
!= expected_reg
10265 || operand_type_check (i
.types
[this_operand
], disp
))
10267 /* The second memory operand must have the same size as
10271 && !((addr_mode
== CODE_64BIT
10272 && i
.base_reg
->reg_type
.bitfield
.qword
)
10273 || (addr_mode
== CODE_32BIT
10274 ? i
.base_reg
->reg_type
.bitfield
.dword
10275 : i
.base_reg
->reg_type
.bitfield
.word
)))
10278 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
10280 intel_syntax
? '[' : '(',
10282 expected_reg
->reg_name
,
10283 intel_syntax
? ']' : ')');
10290 as_bad (_("`%s' is not a valid %s expression"),
10291 operand_string
, kind
);
10296 if (addr_mode
!= CODE_16BIT
)
10298 /* 32-bit/64-bit checks. */
10300 && ((addr_mode
== CODE_64BIT
10301 ? !i
.base_reg
->reg_type
.bitfield
.qword
10302 : !i
.base_reg
->reg_type
.bitfield
.dword
)
10303 || (i
.index_reg
&& i
.base_reg
->reg_num
== RegIP
)
10304 || i
.base_reg
->reg_num
== RegIZ
))
10306 && !i
.index_reg
->reg_type
.bitfield
.xmmword
10307 && !i
.index_reg
->reg_type
.bitfield
.ymmword
10308 && !i
.index_reg
->reg_type
.bitfield
.zmmword
10309 && ((addr_mode
== CODE_64BIT
10310 ? !i
.index_reg
->reg_type
.bitfield
.qword
10311 : !i
.index_reg
->reg_type
.bitfield
.dword
)
10312 || !i
.index_reg
->reg_type
.bitfield
.baseindex
)))
10315 /* bndmk, bndldx, and bndstx have special restrictions. */
10316 if (current_templates
->start
->base_opcode
== 0xf30f1b
10317 || (current_templates
->start
->base_opcode
& ~1) == 0x0f1a)
10319 /* They cannot use RIP-relative addressing. */
10320 if (i
.base_reg
&& i
.base_reg
->reg_num
== RegIP
)
10322 as_bad (_("`%s' cannot be used here"), operand_string
);
10326 /* bndldx and bndstx ignore their scale factor. */
10327 if (current_templates
->start
->base_opcode
!= 0xf30f1b
10328 && i
.log2_scale_factor
)
10329 as_warn (_("register scaling is being ignored here"));
10334 /* 16-bit checks. */
10336 && (!i
.base_reg
->reg_type
.bitfield
.word
10337 || !i
.base_reg
->reg_type
.bitfield
.baseindex
))
10339 && (!i
.index_reg
->reg_type
.bitfield
.word
10340 || !i
.index_reg
->reg_type
.bitfield
.baseindex
10342 && i
.base_reg
->reg_num
< 6
10343 && i
.index_reg
->reg_num
>= 6
10344 && i
.log2_scale_factor
== 0))))
10351 /* Handle vector immediates. */
10354 RC_SAE_immediate (const char *imm_start
)
10356 unsigned int match_found
, j
;
10357 const char *pstr
= imm_start
;
10365 for (j
= 0; j
< ARRAY_SIZE (RC_NamesTable
); j
++)
10367 if (!strncmp (pstr
, RC_NamesTable
[j
].name
, RC_NamesTable
[j
].len
))
10371 rc_op
.type
= RC_NamesTable
[j
].type
;
10372 rc_op
.operand
= this_operand
;
10373 i
.rounding
= &rc_op
;
10377 as_bad (_("duplicated `%s'"), imm_start
);
10380 pstr
+= RC_NamesTable
[j
].len
;
10388 if (*pstr
++ != '}')
10390 as_bad (_("Missing '}': '%s'"), imm_start
);
10393 /* RC/SAE immediate string should contain nothing more. */;
10396 as_bad (_("Junk after '}': '%s'"), imm_start
);
10400 exp
= &im_expressions
[i
.imm_operands
++];
10401 i
.op
[this_operand
].imms
= exp
;
10403 exp
->X_op
= O_constant
;
10404 exp
->X_add_number
= 0;
10405 exp
->X_add_symbol
= (symbolS
*) 0;
10406 exp
->X_op_symbol
= (symbolS
*) 0;
10408 i
.types
[this_operand
].bitfield
.imm8
= 1;
10412 /* Only string instructions can have a second memory operand, so
10413 reduce current_templates to just those if it contains any. */
10415 maybe_adjust_templates (void)
10417 const insn_template
*t
;
10419 gas_assert (i
.mem_operands
== 1);
10421 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
10422 if (t
->opcode_modifier
.isstring
)
10425 if (t
< current_templates
->end
)
10427 static templates aux_templates
;
10428 bfd_boolean recheck
;
10430 aux_templates
.start
= t
;
10431 for (; t
< current_templates
->end
; ++t
)
10432 if (!t
->opcode_modifier
.isstring
)
10434 aux_templates
.end
= t
;
10436 /* Determine whether to re-check the first memory operand. */
10437 recheck
= (aux_templates
.start
!= current_templates
->start
10438 || t
!= current_templates
->end
);
10440 current_templates
= &aux_templates
;
10444 i
.mem_operands
= 0;
10445 if (i
.memop1_string
!= NULL
10446 && i386_index_check (i
.memop1_string
) == 0)
10448 i
.mem_operands
= 1;
10455 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
10459 i386_att_operand (char *operand_string
)
10461 const reg_entry
*r
;
10463 char *op_string
= operand_string
;
10465 if (is_space_char (*op_string
))
10468 /* We check for an absolute prefix (differentiating,
10469 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
10470 if (*op_string
== ABSOLUTE_PREFIX
)
10473 if (is_space_char (*op_string
))
10475 i
.jumpabsolute
= TRUE
;
10478 /* Check if operand is a register. */
10479 if ((r
= parse_register (op_string
, &end_op
)) != NULL
)
10481 i386_operand_type temp
;
10483 /* Check for a segment override by searching for ':' after a
10484 segment register. */
10485 op_string
= end_op
;
10486 if (is_space_char (*op_string
))
10488 if (*op_string
== ':' && r
->reg_type
.bitfield
.class == SReg
)
10490 switch (r
->reg_num
)
10493 i
.seg
[i
.mem_operands
] = &es
;
10496 i
.seg
[i
.mem_operands
] = &cs
;
10499 i
.seg
[i
.mem_operands
] = &ss
;
10502 i
.seg
[i
.mem_operands
] = &ds
;
10505 i
.seg
[i
.mem_operands
] = &fs
;
10508 i
.seg
[i
.mem_operands
] = &gs
;
10512 /* Skip the ':' and whitespace. */
10514 if (is_space_char (*op_string
))
10517 if (!is_digit_char (*op_string
)
10518 && !is_identifier_char (*op_string
)
10519 && *op_string
!= '('
10520 && *op_string
!= ABSOLUTE_PREFIX
)
10522 as_bad (_("bad memory operand `%s'"), op_string
);
10525 /* Handle case of %es:*foo. */
10526 if (*op_string
== ABSOLUTE_PREFIX
)
10529 if (is_space_char (*op_string
))
10531 i
.jumpabsolute
= TRUE
;
10533 goto do_memory_reference
;
10536 /* Handle vector operations. */
10537 if (*op_string
== '{')
10539 op_string
= check_VecOperations (op_string
, NULL
);
10540 if (op_string
== NULL
)
10546 as_bad (_("junk `%s' after register"), op_string
);
10549 temp
= r
->reg_type
;
10550 temp
.bitfield
.baseindex
= 0;
10551 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
10553 i
.types
[this_operand
].bitfield
.unspecified
= 0;
10554 i
.op
[this_operand
].regs
= r
;
10557 else if (*op_string
== REGISTER_PREFIX
)
10559 as_bad (_("bad register name `%s'"), op_string
);
10562 else if (*op_string
== IMMEDIATE_PREFIX
)
10565 if (i
.jumpabsolute
)
10567 as_bad (_("immediate operand illegal with absolute jump"));
10570 if (!i386_immediate (op_string
))
10573 else if (RC_SAE_immediate (operand_string
))
10575 /* If it is a RC or SAE immediate, do nothing. */
10578 else if (is_digit_char (*op_string
)
10579 || is_identifier_char (*op_string
)
10580 || *op_string
== '"'
10581 || *op_string
== '(')
10583 /* This is a memory reference of some sort. */
10586 /* Start and end of displacement string expression (if found). */
10587 char *displacement_string_start
;
10588 char *displacement_string_end
;
10591 do_memory_reference
:
10592 if (i
.mem_operands
== 1 && !maybe_adjust_templates ())
10594 if ((i
.mem_operands
== 1
10595 && !current_templates
->start
->opcode_modifier
.isstring
)
10596 || i
.mem_operands
== 2)
10598 as_bad (_("too many memory references for `%s'"),
10599 current_templates
->start
->name
);
10603 /* Check for base index form. We detect the base index form by
10604 looking for an ')' at the end of the operand, searching
10605 for the '(' matching it, and finding a REGISTER_PREFIX or ','
10607 base_string
= op_string
+ strlen (op_string
);
10609 /* Handle vector operations. */
10610 vop_start
= strchr (op_string
, '{');
10611 if (vop_start
&& vop_start
< base_string
)
10613 if (check_VecOperations (vop_start
, base_string
) == NULL
)
10615 base_string
= vop_start
;
10619 if (is_space_char (*base_string
))
10622 /* If we only have a displacement, set-up for it to be parsed later. */
10623 displacement_string_start
= op_string
;
10624 displacement_string_end
= base_string
+ 1;
10626 if (*base_string
== ')')
10629 unsigned int parens_balanced
= 1;
10630 /* We've already checked that the number of left & right ()'s are
10631 equal, so this loop will not be infinite. */
10635 if (*base_string
== ')')
10637 if (*base_string
== '(')
10640 while (parens_balanced
);
10642 temp_string
= base_string
;
10644 /* Skip past '(' and whitespace. */
10646 if (is_space_char (*base_string
))
10649 if (*base_string
== ','
10650 || ((i
.base_reg
= parse_register (base_string
, &end_op
))
10653 displacement_string_end
= temp_string
;
10655 i
.types
[this_operand
].bitfield
.baseindex
= 1;
10659 base_string
= end_op
;
10660 if (is_space_char (*base_string
))
10664 /* There may be an index reg or scale factor here. */
10665 if (*base_string
== ',')
10668 if (is_space_char (*base_string
))
10671 if ((i
.index_reg
= parse_register (base_string
, &end_op
))
10674 base_string
= end_op
;
10675 if (is_space_char (*base_string
))
10677 if (*base_string
== ',')
10680 if (is_space_char (*base_string
))
10683 else if (*base_string
!= ')')
10685 as_bad (_("expecting `,' or `)' "
10686 "after index register in `%s'"),
10691 else if (*base_string
== REGISTER_PREFIX
)
10693 end_op
= strchr (base_string
, ',');
10696 as_bad (_("bad register name `%s'"), base_string
);
10700 /* Check for scale factor. */
10701 if (*base_string
!= ')')
10703 char *end_scale
= i386_scale (base_string
);
10708 base_string
= end_scale
;
10709 if (is_space_char (*base_string
))
10711 if (*base_string
!= ')')
10713 as_bad (_("expecting `)' "
10714 "after scale factor in `%s'"),
10719 else if (!i
.index_reg
)
10721 as_bad (_("expecting index register or scale factor "
10722 "after `,'; got '%c'"),
10727 else if (*base_string
!= ')')
10729 as_bad (_("expecting `,' or `)' "
10730 "after base register in `%s'"),
10735 else if (*base_string
== REGISTER_PREFIX
)
10737 end_op
= strchr (base_string
, ',');
10740 as_bad (_("bad register name `%s'"), base_string
);
10745 /* If there's an expression beginning the operand, parse it,
10746 assuming displacement_string_start and
10747 displacement_string_end are meaningful. */
10748 if (displacement_string_start
!= displacement_string_end
)
10750 if (!i386_displacement (displacement_string_start
,
10751 displacement_string_end
))
10755 /* Special case for (%dx) while doing input/output op. */
10757 && i
.base_reg
->reg_type
.bitfield
.instance
== RegD
10758 && i
.base_reg
->reg_type
.bitfield
.word
10759 && i
.index_reg
== 0
10760 && i
.log2_scale_factor
== 0
10761 && i
.seg
[i
.mem_operands
] == 0
10762 && !operand_type_check (i
.types
[this_operand
], disp
))
10764 i
.types
[this_operand
] = i
.base_reg
->reg_type
;
10768 if (i386_index_check (operand_string
) == 0)
10770 i
.flags
[this_operand
] |= Operand_Mem
;
10771 if (i
.mem_operands
== 0)
10772 i
.memop1_string
= xstrdup (operand_string
);
10777 /* It's not a memory operand; argh! */
10778 as_bad (_("invalid char %s beginning operand %d `%s'"),
10779 output_invalid (*op_string
),
10784 return 1; /* Normal return. */
10787 /* Calculate the maximum variable size (i.e., excluding fr_fix)
10788 that an rs_machine_dependent frag may reach. */
10791 i386_frag_max_var (fragS
*frag
)
10793 /* The only relaxable frags are for jumps.
10794 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
10795 gas_assert (frag
->fr_type
== rs_machine_dependent
);
10796 return TYPE_FROM_RELAX_STATE (frag
->fr_subtype
) == UNCOND_JUMP
? 4 : 5;
10799 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10801 elf_symbol_resolved_in_segment_p (symbolS
*fr_symbol
, offsetT fr_var
)
10803 /* STT_GNU_IFUNC symbol must go through PLT. */
10804 if ((symbol_get_bfdsym (fr_symbol
)->flags
10805 & BSF_GNU_INDIRECT_FUNCTION
) != 0)
10808 if (!S_IS_EXTERNAL (fr_symbol
))
10809 /* Symbol may be weak or local. */
10810 return !S_IS_WEAK (fr_symbol
);
10812 /* Global symbols with non-default visibility can't be preempted. */
10813 if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol
)) != STV_DEFAULT
)
10816 if (fr_var
!= NO_RELOC
)
10817 switch ((enum bfd_reloc_code_real
) fr_var
)
10819 case BFD_RELOC_386_PLT32
:
10820 case BFD_RELOC_X86_64_PLT32
:
10821 /* Symbol with PLT relocation may be preempted. */
10827 /* Global symbols with default visibility in a shared library may be
10828 preempted by another definition. */
10833 /* Return the next non-empty frag. */
10836 i386_next_non_empty_frag (fragS
*fragP
)
10838 /* There may be a frag with a ".fill 0" when there is no room in
10839 the current frag for frag_grow in output_insn. */
10840 for (fragP
= fragP
->fr_next
;
10842 && fragP
->fr_type
== rs_fill
10843 && fragP
->fr_fix
== 0);
10844 fragP
= fragP
->fr_next
)
10849 /* Return the next jcc frag after BRANCH_PADDING. */
10852 i386_next_jcc_frag (fragS
*fragP
)
10857 if (fragP
->fr_type
== rs_machine_dependent
10858 && (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
)
10859 == BRANCH_PADDING
))
10861 fragP
= i386_next_non_empty_frag (fragP
);
10862 if (fragP
->fr_type
!= rs_machine_dependent
)
10864 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == COND_JUMP
)
10871 /* Classify BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING frags. */
10874 i386_classify_machine_dependent_frag (fragS
*fragP
)
10878 fragS
*branch_fragP
;
10880 unsigned int max_prefix_length
;
10882 if (fragP
->tc_frag_data
.classified
)
10885 /* First scan for BRANCH_PADDING and FUSED_JCC_PADDING. Convert
10886 FUSED_JCC_PADDING and merge BRANCH_PADDING. */
10887 for (next_fragP
= fragP
;
10888 next_fragP
!= NULL
;
10889 next_fragP
= next_fragP
->fr_next
)
10891 next_fragP
->tc_frag_data
.classified
= 1;
10892 if (next_fragP
->fr_type
== rs_machine_dependent
)
10893 switch (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
))
10895 case BRANCH_PADDING
:
10896 /* The BRANCH_PADDING frag must be followed by a branch
10898 branch_fragP
= i386_next_non_empty_frag (next_fragP
);
10899 next_fragP
->tc_frag_data
.u
.branch_fragP
= branch_fragP
;
10901 case FUSED_JCC_PADDING
:
10902 /* Check if this is a fused jcc:
10904 CMP like instruction
10908 cmp_fragP
= i386_next_non_empty_frag (next_fragP
);
10909 pad_fragP
= i386_next_non_empty_frag (cmp_fragP
);
10910 branch_fragP
= i386_next_jcc_frag (pad_fragP
);
10913 /* The BRANCH_PADDING frag is merged with the
10914 FUSED_JCC_PADDING frag. */
10915 next_fragP
->tc_frag_data
.u
.branch_fragP
= branch_fragP
;
10916 /* CMP like instruction size. */
10917 next_fragP
->tc_frag_data
.cmp_size
= cmp_fragP
->fr_fix
;
10918 frag_wane (pad_fragP
);
10919 /* Skip to branch_fragP. */
10920 next_fragP
= branch_fragP
;
10922 else if (next_fragP
->tc_frag_data
.max_prefix_length
)
10924 /* Turn FUSED_JCC_PADDING into BRANCH_PREFIX if it isn't
10926 next_fragP
->fr_subtype
10927 = ENCODE_RELAX_STATE (BRANCH_PREFIX
, 0);
10928 next_fragP
->tc_frag_data
.max_bytes
10929 = next_fragP
->tc_frag_data
.max_prefix_length
;
10930 /* This will be updated in the BRANCH_PREFIX scan. */
10931 next_fragP
->tc_frag_data
.max_prefix_length
= 0;
10934 frag_wane (next_fragP
);
10939 /* Stop if there is no BRANCH_PREFIX. */
10940 if (!align_branch_prefix_size
)
10943 /* Scan for BRANCH_PREFIX. */
10944 for (; fragP
!= NULL
; fragP
= fragP
->fr_next
)
10946 if (fragP
->fr_type
!= rs_machine_dependent
10947 || (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
)
10951 /* Count all BRANCH_PREFIX frags before BRANCH_PADDING and
10952 COND_JUMP_PREFIX. */
10953 max_prefix_length
= 0;
10954 for (next_fragP
= fragP
;
10955 next_fragP
!= NULL
;
10956 next_fragP
= next_fragP
->fr_next
)
10958 if (next_fragP
->fr_type
== rs_fill
)
10959 /* Skip rs_fill frags. */
10961 else if (next_fragP
->fr_type
!= rs_machine_dependent
)
10962 /* Stop for all other frags. */
10965 /* rs_machine_dependent frags. */
10966 if (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
10969 /* Count BRANCH_PREFIX frags. */
10970 if (max_prefix_length
>= MAX_FUSED_JCC_PADDING_SIZE
)
10972 max_prefix_length
= MAX_FUSED_JCC_PADDING_SIZE
;
10973 frag_wane (next_fragP
);
10977 += next_fragP
->tc_frag_data
.max_bytes
;
10979 else if ((TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
10981 || (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
10982 == FUSED_JCC_PADDING
))
10984 /* Stop at BRANCH_PADDING and FUSED_JCC_PADDING. */
10985 fragP
->tc_frag_data
.u
.padding_fragP
= next_fragP
;
10989 /* Stop for other rs_machine_dependent frags. */
10993 fragP
->tc_frag_data
.max_prefix_length
= max_prefix_length
;
10995 /* Skip to the next frag. */
10996 fragP
= next_fragP
;
11000 /* Compute padding size for
11003 CMP like instruction
11005 COND_JUMP/UNCOND_JUMP
11010 COND_JUMP/UNCOND_JUMP
11014 i386_branch_padding_size (fragS
*fragP
, offsetT address
)
11016 unsigned int offset
, size
, padding_size
;
11017 fragS
*branch_fragP
= fragP
->tc_frag_data
.u
.branch_fragP
;
11019 /* The start address of the BRANCH_PADDING or FUSED_JCC_PADDING frag. */
11021 address
= fragP
->fr_address
;
11022 address
+= fragP
->fr_fix
;
11024 /* CMP like instrunction size. */
11025 size
= fragP
->tc_frag_data
.cmp_size
;
11027 /* The base size of the branch frag. */
11028 size
+= branch_fragP
->fr_fix
;
11030 /* Add opcode and displacement bytes for the rs_machine_dependent
11032 if (branch_fragP
->fr_type
== rs_machine_dependent
)
11033 size
+= md_relax_table
[branch_fragP
->fr_subtype
].rlx_length
;
11035 /* Check if branch is within boundary and doesn't end at the last
11037 offset
= address
& ((1U << align_branch_power
) - 1);
11038 if ((offset
+ size
) >= (1U << align_branch_power
))
11039 /* Padding needed to avoid crossing boundary. */
11040 padding_size
= (1U << align_branch_power
) - offset
;
11042 /* No padding needed. */
11045 /* The return value may be saved in tc_frag_data.length which is
11047 if (!fits_in_unsigned_byte (padding_size
))
11050 return padding_size
;
11053 /* i386_generic_table_relax_frag()
11055 Handle BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING frags to
11056 grow/shrink padding to align branch frags. Hand others to
11060 i386_generic_table_relax_frag (segT segment
, fragS
*fragP
, long stretch
)
11062 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
11063 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
)
11065 long padding_size
= i386_branch_padding_size (fragP
, 0);
11066 long grow
= padding_size
- fragP
->tc_frag_data
.length
;
11068 /* When the BRANCH_PREFIX frag is used, the computed address
11069 must match the actual address and there should be no padding. */
11070 if (fragP
->tc_frag_data
.padding_address
11071 && (fragP
->tc_frag_data
.padding_address
!= fragP
->fr_address
11075 /* Update the padding size. */
11077 fragP
->tc_frag_data
.length
= padding_size
;
11081 else if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
)
11083 fragS
*padding_fragP
, *next_fragP
;
11084 long padding_size
, left_size
, last_size
;
11086 padding_fragP
= fragP
->tc_frag_data
.u
.padding_fragP
;
11087 if (!padding_fragP
)
11088 /* Use the padding set by the leading BRANCH_PREFIX frag. */
11089 return (fragP
->tc_frag_data
.length
11090 - fragP
->tc_frag_data
.last_length
);
11092 /* Compute the relative address of the padding frag in the very
11093 first time where the BRANCH_PREFIX frag sizes are zero. */
11094 if (!fragP
->tc_frag_data
.padding_address
)
11095 fragP
->tc_frag_data
.padding_address
11096 = padding_fragP
->fr_address
- (fragP
->fr_address
- stretch
);
11098 /* First update the last length from the previous interation. */
11099 left_size
= fragP
->tc_frag_data
.prefix_length
;
11100 for (next_fragP
= fragP
;
11101 next_fragP
!= padding_fragP
;
11102 next_fragP
= next_fragP
->fr_next
)
11103 if (next_fragP
->fr_type
== rs_machine_dependent
11104 && (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
11109 int max
= next_fragP
->tc_frag_data
.max_bytes
;
11113 if (max
> left_size
)
11118 next_fragP
->tc_frag_data
.last_length
= size
;
11122 next_fragP
->tc_frag_data
.last_length
= 0;
11125 /* Check the padding size for the padding frag. */
11126 padding_size
= i386_branch_padding_size
11127 (padding_fragP
, (fragP
->fr_address
11128 + fragP
->tc_frag_data
.padding_address
));
11130 last_size
= fragP
->tc_frag_data
.prefix_length
;
11131 /* Check if there is change from the last interation. */
11132 if (padding_size
== last_size
)
11134 /* Update the expected address of the padding frag. */
11135 padding_fragP
->tc_frag_data
.padding_address
11136 = (fragP
->fr_address
+ padding_size
11137 + fragP
->tc_frag_data
.padding_address
);
11141 if (padding_size
> fragP
->tc_frag_data
.max_prefix_length
)
11143 /* No padding if there is no sufficient room. Clear the
11144 expected address of the padding frag. */
11145 padding_fragP
->tc_frag_data
.padding_address
= 0;
11149 /* Store the expected address of the padding frag. */
11150 padding_fragP
->tc_frag_data
.padding_address
11151 = (fragP
->fr_address
+ padding_size
11152 + fragP
->tc_frag_data
.padding_address
);
11154 fragP
->tc_frag_data
.prefix_length
= padding_size
;
11156 /* Update the length for the current interation. */
11157 left_size
= padding_size
;
11158 for (next_fragP
= fragP
;
11159 next_fragP
!= padding_fragP
;
11160 next_fragP
= next_fragP
->fr_next
)
11161 if (next_fragP
->fr_type
== rs_machine_dependent
11162 && (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
11167 int max
= next_fragP
->tc_frag_data
.max_bytes
;
11171 if (max
> left_size
)
11176 next_fragP
->tc_frag_data
.length
= size
;
11180 next_fragP
->tc_frag_data
.length
= 0;
11183 return (fragP
->tc_frag_data
.length
11184 - fragP
->tc_frag_data
.last_length
);
11186 return relax_frag (segment
, fragP
, stretch
);
11189 /* md_estimate_size_before_relax()
11191 Called just before relax() for rs_machine_dependent frags. The x86
11192 assembler uses these frags to handle variable size jump
11195 Any symbol that is now undefined will not become defined.
11196 Return the correct fr_subtype in the frag.
11197 Return the initial "guess for variable size of frag" to caller.
11198 The guess is actually the growth beyond the fixed part. Whatever
11199 we do to grow the fixed or variable part contributes to our
11203 md_estimate_size_before_relax (fragS
*fragP
, segT segment
)
11205 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
11206 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
11207 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
)
11209 i386_classify_machine_dependent_frag (fragP
);
11210 return fragP
->tc_frag_data
.length
;
11213 /* We've already got fragP->fr_subtype right; all we have to do is
11214 check for un-relaxable symbols. On an ELF system, we can't relax
11215 an externally visible symbol, because it may be overridden by a
11217 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
11218 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11220 && !elf_symbol_resolved_in_segment_p (fragP
->fr_symbol
,
11223 #if defined (OBJ_COFF) && defined (TE_PE)
11224 || (OUTPUT_FLAVOR
== bfd_target_coff_flavour
11225 && S_IS_WEAK (fragP
->fr_symbol
))
11229 /* Symbol is undefined in this segment, or we need to keep a
11230 reloc so that weak symbols can be overridden. */
11231 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
11232 enum bfd_reloc_code_real reloc_type
;
11233 unsigned char *opcode
;
11236 if (fragP
->fr_var
!= NO_RELOC
)
11237 reloc_type
= (enum bfd_reloc_code_real
) fragP
->fr_var
;
11238 else if (size
== 2)
11239 reloc_type
= BFD_RELOC_16_PCREL
;
11240 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11241 else if (need_plt32_p (fragP
->fr_symbol
))
11242 reloc_type
= BFD_RELOC_X86_64_PLT32
;
11245 reloc_type
= BFD_RELOC_32_PCREL
;
11247 old_fr_fix
= fragP
->fr_fix
;
11248 opcode
= (unsigned char *) fragP
->fr_opcode
;
11250 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
11253 /* Make jmp (0xeb) a (d)word displacement jump. */
11255 fragP
->fr_fix
+= size
;
11256 fix_new (fragP
, old_fr_fix
, size
,
11258 fragP
->fr_offset
, 1,
11264 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
11266 /* Negate the condition, and branch past an
11267 unconditional jump. */
11270 /* Insert an unconditional jump. */
11272 /* We added two extra opcode bytes, and have a two byte
11274 fragP
->fr_fix
+= 2 + 2;
11275 fix_new (fragP
, old_fr_fix
+ 2, 2,
11277 fragP
->fr_offset
, 1,
11281 /* Fall through. */
11284 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
11288 fragP
->fr_fix
+= 1;
11289 fixP
= fix_new (fragP
, old_fr_fix
, 1,
11291 fragP
->fr_offset
, 1,
11292 BFD_RELOC_8_PCREL
);
11293 fixP
->fx_signed
= 1;
11297 /* This changes the byte-displacement jump 0x7N
11298 to the (d)word-displacement jump 0x0f,0x8N. */
11299 opcode
[1] = opcode
[0] + 0x10;
11300 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
11301 /* We've added an opcode byte. */
11302 fragP
->fr_fix
+= 1 + size
;
11303 fix_new (fragP
, old_fr_fix
+ 1, size
,
11305 fragP
->fr_offset
, 1,
11310 BAD_CASE (fragP
->fr_subtype
);
11314 return fragP
->fr_fix
- old_fr_fix
;
11317 /* Guess size depending on current relax state. Initially the relax
11318 state will correspond to a short jump and we return 1, because
11319 the variable part of the frag (the branch offset) is one byte
11320 long. However, we can relax a section more than once and in that
11321 case we must either set fr_subtype back to the unrelaxed state,
11322 or return the value for the appropriate branch. */
11323 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
11326 /* Called after relax() is finished.
11328 In: Address of frag.
11329 fr_type == rs_machine_dependent.
11330 fr_subtype is what the address relaxed to.
11332 Out: Any fixSs and constants are set up.
11333 Caller will turn frag into a ".space 0". */
11336 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec ATTRIBUTE_UNUSED
,
11339 unsigned char *opcode
;
11340 unsigned char *where_to_put_displacement
= NULL
;
11341 offsetT target_address
;
11342 offsetT opcode_address
;
11343 unsigned int extension
= 0;
11344 offsetT displacement_from_opcode_start
;
11346 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
11347 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
11348 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
)
11350 /* Generate nop padding. */
11351 unsigned int size
= fragP
->tc_frag_data
.length
;
11354 if (size
> fragP
->tc_frag_data
.max_bytes
)
11360 const char *branch
= "branch";
11361 const char *prefix
= "";
11362 fragS
*padding_fragP
;
11363 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
)
11366 padding_fragP
= fragP
->tc_frag_data
.u
.padding_fragP
;
11367 switch (fragP
->tc_frag_data
.default_prefix
)
11372 case CS_PREFIX_OPCODE
:
11375 case DS_PREFIX_OPCODE
:
11378 case ES_PREFIX_OPCODE
:
11381 case FS_PREFIX_OPCODE
:
11384 case GS_PREFIX_OPCODE
:
11387 case SS_PREFIX_OPCODE
:
11392 msg
= _("%s:%u: add %d%s at 0x%llx to align "
11393 "%s within %d-byte boundary\n");
11395 msg
= _("%s:%u: add additional %d%s at 0x%llx to "
11396 "align %s within %d-byte boundary\n");
11400 padding_fragP
= fragP
;
11401 msg
= _("%s:%u: add %d%s-byte nop at 0x%llx to align "
11402 "%s within %d-byte boundary\n");
11406 switch (padding_fragP
->tc_frag_data
.branch_type
)
11408 case align_branch_jcc
:
11411 case align_branch_fused
:
11412 branch
= "fused jcc";
11414 case align_branch_jmp
:
11417 case align_branch_call
:
11420 case align_branch_indirect
:
11421 branch
= "indiret branch";
11423 case align_branch_ret
:
11430 fprintf (stdout
, msg
,
11431 fragP
->fr_file
, fragP
->fr_line
, size
, prefix
,
11432 (long long) fragP
->fr_address
, branch
,
11433 1 << align_branch_power
);
11435 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
)
11436 memset (fragP
->fr_opcode
,
11437 fragP
->tc_frag_data
.default_prefix
, size
);
11439 i386_generate_nops (fragP
, (char *) fragP
->fr_opcode
,
11441 fragP
->fr_fix
+= size
;
11446 opcode
= (unsigned char *) fragP
->fr_opcode
;
11448 /* Address we want to reach in file space. */
11449 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
11451 /* Address opcode resides at in file space. */
11452 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
11454 /* Displacement from opcode start to fill into instruction. */
11455 displacement_from_opcode_start
= target_address
- opcode_address
;
11457 if ((fragP
->fr_subtype
& BIG
) == 0)
11459 /* Don't have to change opcode. */
11460 extension
= 1; /* 1 opcode + 1 displacement */
11461 where_to_put_displacement
= &opcode
[1];
11465 if (no_cond_jump_promotion
11466 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
11467 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
11468 _("long jump required"));
11470 switch (fragP
->fr_subtype
)
11472 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
11473 extension
= 4; /* 1 opcode + 4 displacement */
11475 where_to_put_displacement
= &opcode
[1];
11478 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
11479 extension
= 2; /* 1 opcode + 2 displacement */
11481 where_to_put_displacement
= &opcode
[1];
11484 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
11485 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
11486 extension
= 5; /* 2 opcode + 4 displacement */
11487 opcode
[1] = opcode
[0] + 0x10;
11488 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
11489 where_to_put_displacement
= &opcode
[2];
11492 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
11493 extension
= 3; /* 2 opcode + 2 displacement */
11494 opcode
[1] = opcode
[0] + 0x10;
11495 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
11496 where_to_put_displacement
= &opcode
[2];
11499 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
11504 where_to_put_displacement
= &opcode
[3];
11508 BAD_CASE (fragP
->fr_subtype
);
11513 /* If size if less then four we are sure that the operand fits,
11514 but if it's 4, then it could be that the displacement is larger
11516 if (DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
) == 4
11518 && ((addressT
) (displacement_from_opcode_start
- extension
11519 + ((addressT
) 1 << 31))
11520 > (((addressT
) 2 << 31) - 1)))
11522 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
11523 _("jump target out of range"));
11524 /* Make us emit 0. */
11525 displacement_from_opcode_start
= extension
;
11527 /* Now put displacement after opcode. */
11528 md_number_to_chars ((char *) where_to_put_displacement
,
11529 (valueT
) (displacement_from_opcode_start
- extension
),
11530 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
11531 fragP
->fr_fix
+= extension
;
11534 /* Apply a fixup (fixP) to segment data, once it has been determined
11535 by our caller that we have all the info we need to fix it up.
11537 Parameter valP is the pointer to the value of the bits.
11539 On the 386, immediates, displacements, and data pointers are all in
11540 the same (little-endian) format, so we don't need to care about which
11541 we are handling. */
11544 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
11546 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
11547 valueT value
= *valP
;
11549 #if !defined (TE_Mach)
11550 if (fixP
->fx_pcrel
)
11552 switch (fixP
->fx_r_type
)
11558 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
11561 case BFD_RELOC_X86_64_32S
:
11562 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
11565 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
11568 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
11573 if (fixP
->fx_addsy
!= NULL
11574 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
11575 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
11576 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
11577 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
11578 && !use_rela_relocations
)
11580 /* This is a hack. There should be a better way to handle this.
11581 This covers for the fact that bfd_install_relocation will
11582 subtract the current location (for partial_inplace, PC relative
11583 relocations); see more below. */
11587 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
11590 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
11592 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11595 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
11597 if ((sym_seg
== seg
11598 || (symbol_section_p (fixP
->fx_addsy
)
11599 && sym_seg
!= absolute_section
))
11600 && !generic_force_reloc (fixP
))
11602 /* Yes, we add the values in twice. This is because
11603 bfd_install_relocation subtracts them out again. I think
11604 bfd_install_relocation is broken, but I don't dare change
11606 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
11610 #if defined (OBJ_COFF) && defined (TE_PE)
11611 /* For some reason, the PE format does not store a
11612 section address offset for a PC relative symbol. */
11613 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
11614 || S_IS_WEAK (fixP
->fx_addsy
))
11615 value
+= md_pcrel_from (fixP
);
11618 #if defined (OBJ_COFF) && defined (TE_PE)
11619 if (fixP
->fx_addsy
!= NULL
11620 && S_IS_WEAK (fixP
->fx_addsy
)
11621 /* PR 16858: Do not modify weak function references. */
11622 && ! fixP
->fx_pcrel
)
11624 #if !defined (TE_PEP)
11625 /* For x86 PE weak function symbols are neither PC-relative
11626 nor do they set S_IS_FUNCTION. So the only reliable way
11627 to detect them is to check the flags of their containing
11629 if (S_GET_SEGMENT (fixP
->fx_addsy
) != NULL
11630 && S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_CODE
)
11634 value
-= S_GET_VALUE (fixP
->fx_addsy
);
11638 /* Fix a few things - the dynamic linker expects certain values here,
11639 and we must not disappoint it. */
11640 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11641 if (IS_ELF
&& fixP
->fx_addsy
)
11642 switch (fixP
->fx_r_type
)
11644 case BFD_RELOC_386_PLT32
:
11645 case BFD_RELOC_X86_64_PLT32
:
11646 /* Make the jump instruction point to the address of the operand.
11647 At runtime we merely add the offset to the actual PLT entry.
11648 NB: Subtract the offset size only for jump instructions. */
11649 if (fixP
->fx_pcrel
)
11653 case BFD_RELOC_386_TLS_GD
:
11654 case BFD_RELOC_386_TLS_LDM
:
11655 case BFD_RELOC_386_TLS_IE_32
:
11656 case BFD_RELOC_386_TLS_IE
:
11657 case BFD_RELOC_386_TLS_GOTIE
:
11658 case BFD_RELOC_386_TLS_GOTDESC
:
11659 case BFD_RELOC_X86_64_TLSGD
:
11660 case BFD_RELOC_X86_64_TLSLD
:
11661 case BFD_RELOC_X86_64_GOTTPOFF
:
11662 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
11663 value
= 0; /* Fully resolved at runtime. No addend. */
11665 case BFD_RELOC_386_TLS_LE
:
11666 case BFD_RELOC_386_TLS_LDO_32
:
11667 case BFD_RELOC_386_TLS_LE_32
:
11668 case BFD_RELOC_X86_64_DTPOFF32
:
11669 case BFD_RELOC_X86_64_DTPOFF64
:
11670 case BFD_RELOC_X86_64_TPOFF32
:
11671 case BFD_RELOC_X86_64_TPOFF64
:
11672 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
11675 case BFD_RELOC_386_TLS_DESC_CALL
:
11676 case BFD_RELOC_X86_64_TLSDESC_CALL
:
11677 value
= 0; /* Fully resolved at runtime. No addend. */
11678 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
11682 case BFD_RELOC_VTABLE_INHERIT
:
11683 case BFD_RELOC_VTABLE_ENTRY
:
11690 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
11692 #endif /* !defined (TE_Mach) */
11694 /* Are we finished with this relocation now? */
11695 if (fixP
->fx_addsy
== NULL
)
11697 #if defined (OBJ_COFF) && defined (TE_PE)
11698 else if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
11701 /* Remember value for tc_gen_reloc. */
11702 fixP
->fx_addnumber
= value
;
11703 /* Clear out the frag for now. */
11707 else if (use_rela_relocations
)
11709 fixP
->fx_no_overflow
= 1;
11710 /* Remember value for tc_gen_reloc. */
11711 fixP
->fx_addnumber
= value
;
11715 md_number_to_chars (p
, value
, fixP
->fx_size
);
11719 md_atof (int type
, char *litP
, int *sizeP
)
11721 /* This outputs the LITTLENUMs in REVERSE order;
11722 in accord with the bigendian 386. */
11723 return ieee_md_atof (type
, litP
, sizeP
, FALSE
);
11726 static char output_invalid_buf
[sizeof (unsigned char) * 2 + 6];
11729 output_invalid (int c
)
11732 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
11735 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
11736 "(0x%x)", (unsigned char) c
);
11737 return output_invalid_buf
;
11740 /* REG_STRING starts *before* REGISTER_PREFIX. */
11742 static const reg_entry
*
11743 parse_real_register (char *reg_string
, char **end_op
)
11745 char *s
= reg_string
;
11747 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
11748 const reg_entry
*r
;
11750 /* Skip possible REGISTER_PREFIX and possible whitespace. */
11751 if (*s
== REGISTER_PREFIX
)
11754 if (is_space_char (*s
))
11757 p
= reg_name_given
;
11758 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
11760 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
11761 return (const reg_entry
*) NULL
;
11765 /* For naked regs, make sure that we are not dealing with an identifier.
11766 This prevents confusing an identifier like `eax_var' with register
11768 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
11769 return (const reg_entry
*) NULL
;
11773 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
11775 /* Handle floating point regs, allowing spaces in the (i) part. */
11776 if (r
== i386_regtab
/* %st is first entry of table */)
11778 if (!cpu_arch_flags
.bitfield
.cpu8087
11779 && !cpu_arch_flags
.bitfield
.cpu287
11780 && !cpu_arch_flags
.bitfield
.cpu387
)
11781 return (const reg_entry
*) NULL
;
11783 if (is_space_char (*s
))
11788 if (is_space_char (*s
))
11790 if (*s
>= '0' && *s
<= '7')
11792 int fpr
= *s
- '0';
11794 if (is_space_char (*s
))
11799 r
= (const reg_entry
*) hash_find (reg_hash
, "st(0)");
11804 /* We have "%st(" then garbage. */
11805 return (const reg_entry
*) NULL
;
11809 if (r
== NULL
|| allow_pseudo_reg
)
11812 if (operand_type_all_zero (&r
->reg_type
))
11813 return (const reg_entry
*) NULL
;
11815 if ((r
->reg_type
.bitfield
.dword
11816 || (r
->reg_type
.bitfield
.class == SReg
&& r
->reg_num
> 3)
11817 || r
->reg_type
.bitfield
.class == RegCR
11818 || r
->reg_type
.bitfield
.class == RegDR
11819 || r
->reg_type
.bitfield
.class == RegTR
)
11820 && !cpu_arch_flags
.bitfield
.cpui386
)
11821 return (const reg_entry
*) NULL
;
11823 if (r
->reg_type
.bitfield
.class == RegMMX
&& !cpu_arch_flags
.bitfield
.cpummx
)
11824 return (const reg_entry
*) NULL
;
11826 if (!cpu_arch_flags
.bitfield
.cpuavx512f
)
11828 if (r
->reg_type
.bitfield
.zmmword
11829 || r
->reg_type
.bitfield
.class == RegMask
)
11830 return (const reg_entry
*) NULL
;
11832 if (!cpu_arch_flags
.bitfield
.cpuavx
)
11834 if (r
->reg_type
.bitfield
.ymmword
)
11835 return (const reg_entry
*) NULL
;
11837 if (!cpu_arch_flags
.bitfield
.cpusse
&& r
->reg_type
.bitfield
.xmmword
)
11838 return (const reg_entry
*) NULL
;
11842 if (r
->reg_type
.bitfield
.class == RegBND
&& !cpu_arch_flags
.bitfield
.cpumpx
)
11843 return (const reg_entry
*) NULL
;
11845 /* Don't allow fake index register unless allow_index_reg isn't 0. */
11846 if (!allow_index_reg
&& r
->reg_num
== RegIZ
)
11847 return (const reg_entry
*) NULL
;
11849 /* Upper 16 vector registers are only available with VREX in 64bit
11850 mode, and require EVEX encoding. */
11851 if (r
->reg_flags
& RegVRex
)
11853 if (!cpu_arch_flags
.bitfield
.cpuavx512f
11854 || flag_code
!= CODE_64BIT
)
11855 return (const reg_entry
*) NULL
;
11857 i
.vec_encoding
= vex_encoding_evex
;
11860 if (((r
->reg_flags
& (RegRex64
| RegRex
)) || r
->reg_type
.bitfield
.qword
)
11861 && (!cpu_arch_flags
.bitfield
.cpulm
|| r
->reg_type
.bitfield
.class != RegCR
)
11862 && flag_code
!= CODE_64BIT
)
11863 return (const reg_entry
*) NULL
;
11865 if (r
->reg_type
.bitfield
.class == SReg
&& r
->reg_num
== RegFlat
11867 return (const reg_entry
*) NULL
;
11872 /* REG_STRING starts *before* REGISTER_PREFIX. */
11874 static const reg_entry
*
11875 parse_register (char *reg_string
, char **end_op
)
11877 const reg_entry
*r
;
11879 if (*reg_string
== REGISTER_PREFIX
|| allow_naked_reg
)
11880 r
= parse_real_register (reg_string
, end_op
);
11885 char *save
= input_line_pointer
;
11889 input_line_pointer
= reg_string
;
11890 c
= get_symbol_name (®_string
);
11891 symbolP
= symbol_find (reg_string
);
11892 if (symbolP
&& S_GET_SEGMENT (symbolP
) == reg_section
)
11894 const expressionS
*e
= symbol_get_value_expression (symbolP
);
11896 know (e
->X_op
== O_register
);
11897 know (e
->X_add_number
>= 0
11898 && (valueT
) e
->X_add_number
< i386_regtab_size
);
11899 r
= i386_regtab
+ e
->X_add_number
;
11900 if ((r
->reg_flags
& RegVRex
))
11901 i
.vec_encoding
= vex_encoding_evex
;
11902 *end_op
= input_line_pointer
;
11904 *input_line_pointer
= c
;
11905 input_line_pointer
= save
;
11911 i386_parse_name (char *name
, expressionS
*e
, char *nextcharP
)
11913 const reg_entry
*r
;
11914 char *end
= input_line_pointer
;
11917 r
= parse_register (name
, &input_line_pointer
);
11918 if (r
&& end
<= input_line_pointer
)
11920 *nextcharP
= *input_line_pointer
;
11921 *input_line_pointer
= 0;
11922 e
->X_op
= O_register
;
11923 e
->X_add_number
= r
- i386_regtab
;
11926 input_line_pointer
= end
;
11928 return intel_syntax
? i386_intel_parse_name (name
, e
) : 0;
11932 md_operand (expressionS
*e
)
11935 const reg_entry
*r
;
11937 switch (*input_line_pointer
)
11939 case REGISTER_PREFIX
:
11940 r
= parse_real_register (input_line_pointer
, &end
);
11943 e
->X_op
= O_register
;
11944 e
->X_add_number
= r
- i386_regtab
;
11945 input_line_pointer
= end
;
11950 gas_assert (intel_syntax
);
11951 end
= input_line_pointer
++;
11953 if (*input_line_pointer
== ']')
11955 ++input_line_pointer
;
11956 e
->X_op_symbol
= make_expr_symbol (e
);
11957 e
->X_add_symbol
= NULL
;
11958 e
->X_add_number
= 0;
11963 e
->X_op
= O_absent
;
11964 input_line_pointer
= end
;
11971 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11972 const char *md_shortopts
= "kVQ:sqnO::";
11974 const char *md_shortopts
= "qnO::";
11977 #define OPTION_32 (OPTION_MD_BASE + 0)
11978 #define OPTION_64 (OPTION_MD_BASE + 1)
11979 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
11980 #define OPTION_MARCH (OPTION_MD_BASE + 3)
11981 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
11982 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
11983 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
11984 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
11985 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
11986 #define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 9)
11987 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
11988 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
11989 #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
11990 #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
11991 #define OPTION_X32 (OPTION_MD_BASE + 14)
11992 #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
11993 #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
11994 #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
11995 #define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
11996 #define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
11997 #define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
11998 #define OPTION_MSHARED (OPTION_MD_BASE + 21)
11999 #define OPTION_MAMD64 (OPTION_MD_BASE + 22)
12000 #define OPTION_MINTEL64 (OPTION_MD_BASE + 23)
12001 #define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24)
12002 #define OPTION_X86_USED_NOTE (OPTION_MD_BASE + 25)
12003 #define OPTION_MVEXWIG (OPTION_MD_BASE + 26)
12004 #define OPTION_MALIGN_BRANCH_BOUNDARY (OPTION_MD_BASE + 27)
12005 #define OPTION_MALIGN_BRANCH_PREFIX_SIZE (OPTION_MD_BASE + 28)
12006 #define OPTION_MALIGN_BRANCH (OPTION_MD_BASE + 29)
12007 #define OPTION_MBRANCHES_WITH_32B_BOUNDARIES (OPTION_MD_BASE + 30)
12009 struct option md_longopts
[] =
12011 {"32", no_argument
, NULL
, OPTION_32
},
12012 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
12013 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
12014 {"64", no_argument
, NULL
, OPTION_64
},
12016 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12017 {"x32", no_argument
, NULL
, OPTION_X32
},
12018 {"mshared", no_argument
, NULL
, OPTION_MSHARED
},
12019 {"mx86-used-note", required_argument
, NULL
, OPTION_X86_USED_NOTE
},
12021 {"divide", no_argument
, NULL
, OPTION_DIVIDE
},
12022 {"march", required_argument
, NULL
, OPTION_MARCH
},
12023 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
12024 {"mmnemonic", required_argument
, NULL
, OPTION_MMNEMONIC
},
12025 {"msyntax", required_argument
, NULL
, OPTION_MSYNTAX
},
12026 {"mindex-reg", no_argument
, NULL
, OPTION_MINDEX_REG
},
12027 {"mnaked-reg", no_argument
, NULL
, OPTION_MNAKED_REG
},
12028 {"msse2avx", no_argument
, NULL
, OPTION_MSSE2AVX
},
12029 {"msse-check", required_argument
, NULL
, OPTION_MSSE_CHECK
},
12030 {"moperand-check", required_argument
, NULL
, OPTION_MOPERAND_CHECK
},
12031 {"mavxscalar", required_argument
, NULL
, OPTION_MAVXSCALAR
},
12032 {"mvexwig", required_argument
, NULL
, OPTION_MVEXWIG
},
12033 {"madd-bnd-prefix", no_argument
, NULL
, OPTION_MADD_BND_PREFIX
},
12034 {"mevexlig", required_argument
, NULL
, OPTION_MEVEXLIG
},
12035 {"mevexwig", required_argument
, NULL
, OPTION_MEVEXWIG
},
12036 # if defined (TE_PE) || defined (TE_PEP)
12037 {"mbig-obj", no_argument
, NULL
, OPTION_MBIG_OBJ
},
12039 {"momit-lock-prefix", required_argument
, NULL
, OPTION_MOMIT_LOCK_PREFIX
},
12040 {"mfence-as-lock-add", required_argument
, NULL
, OPTION_MFENCE_AS_LOCK_ADD
},
12041 {"mrelax-relocations", required_argument
, NULL
, OPTION_MRELAX_RELOCATIONS
},
12042 {"mevexrcig", required_argument
, NULL
, OPTION_MEVEXRCIG
},
12043 {"malign-branch-boundary", required_argument
, NULL
, OPTION_MALIGN_BRANCH_BOUNDARY
},
12044 {"malign-branch-prefix-size", required_argument
, NULL
, OPTION_MALIGN_BRANCH_PREFIX_SIZE
},
12045 {"malign-branch", required_argument
, NULL
, OPTION_MALIGN_BRANCH
},
12046 {"mbranches-within-32B-boundaries", no_argument
, NULL
, OPTION_MBRANCHES_WITH_32B_BOUNDARIES
},
12047 {"mamd64", no_argument
, NULL
, OPTION_MAMD64
},
12048 {"mintel64", no_argument
, NULL
, OPTION_MINTEL64
},
12049 {NULL
, no_argument
, NULL
, 0}
12051 size_t md_longopts_size
= sizeof (md_longopts
);
12054 md_parse_option (int c
, const char *arg
)
12057 char *arch
, *next
, *saved
, *type
;
12062 optimize_align_code
= 0;
12066 quiet_warnings
= 1;
12069 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12070 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
12071 should be emitted or not. FIXME: Not implemented. */
12073 if ((arg
[0] != 'y' && arg
[0] != 'n') || arg
[1])
12077 /* -V: SVR4 argument to print version ID. */
12079 print_version_id ();
12082 /* -k: Ignore for FreeBSD compatibility. */
12087 /* -s: On i386 Solaris, this tells the native assembler to use
12088 .stab instead of .stab.excl. We always use .stab anyhow. */
12091 case OPTION_MSHARED
:
12095 case OPTION_X86_USED_NOTE
:
12096 if (strcasecmp (arg
, "yes") == 0)
12098 else if (strcasecmp (arg
, "no") == 0)
12101 as_fatal (_("invalid -mx86-used-note= option: `%s'"), arg
);
12106 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
12107 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
12110 const char **list
, **l
;
12112 list
= bfd_target_list ();
12113 for (l
= list
; *l
!= NULL
; l
++)
12114 if (CONST_STRNEQ (*l
, "elf64-x86-64")
12115 || strcmp (*l
, "coff-x86-64") == 0
12116 || strcmp (*l
, "pe-x86-64") == 0
12117 || strcmp (*l
, "pei-x86-64") == 0
12118 || strcmp (*l
, "mach-o-x86-64") == 0)
12120 default_arch
= "x86_64";
12124 as_fatal (_("no compiled in support for x86_64"));
12130 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12134 const char **list
, **l
;
12136 list
= bfd_target_list ();
12137 for (l
= list
; *l
!= NULL
; l
++)
12138 if (CONST_STRNEQ (*l
, "elf32-x86-64"))
12140 default_arch
= "x86_64:32";
12144 as_fatal (_("no compiled in support for 32bit x86_64"));
12148 as_fatal (_("32bit x86_64 is only supported for ELF"));
12153 default_arch
= "i386";
12156 case OPTION_DIVIDE
:
12157 #ifdef SVR4_COMMENT_CHARS
12162 n
= XNEWVEC (char, strlen (i386_comment_chars
) + 1);
12164 for (s
= i386_comment_chars
; *s
!= '\0'; s
++)
12168 i386_comment_chars
= n
;
12174 saved
= xstrdup (arg
);
12176 /* Allow -march=+nosse. */
12182 as_fatal (_("invalid -march= option: `%s'"), arg
);
12183 next
= strchr (arch
, '+');
12186 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
12188 if (strcmp (arch
, cpu_arch
[j
].name
) == 0)
12191 if (! cpu_arch
[j
].flags
.bitfield
.cpui386
)
12194 cpu_arch_name
= cpu_arch
[j
].name
;
12195 cpu_sub_arch_name
= NULL
;
12196 cpu_arch_flags
= cpu_arch
[j
].flags
;
12197 cpu_arch_isa
= cpu_arch
[j
].type
;
12198 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
12199 if (!cpu_arch_tune_set
)
12201 cpu_arch_tune
= cpu_arch_isa
;
12202 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
12206 else if (*cpu_arch
[j
].name
== '.'
12207 && strcmp (arch
, cpu_arch
[j
].name
+ 1) == 0)
12209 /* ISA extension. */
12210 i386_cpu_flags flags
;
12212 flags
= cpu_flags_or (cpu_arch_flags
,
12213 cpu_arch
[j
].flags
);
12215 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
12217 if (cpu_sub_arch_name
)
12219 char *name
= cpu_sub_arch_name
;
12220 cpu_sub_arch_name
= concat (name
,
12222 (const char *) NULL
);
12226 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
12227 cpu_arch_flags
= flags
;
12228 cpu_arch_isa_flags
= flags
;
12232 = cpu_flags_or (cpu_arch_isa_flags
,
12233 cpu_arch
[j
].flags
);
12238 if (j
>= ARRAY_SIZE (cpu_arch
))
12240 /* Disable an ISA extension. */
12241 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
12242 if (strcmp (arch
, cpu_noarch
[j
].name
) == 0)
12244 i386_cpu_flags flags
;
12246 flags
= cpu_flags_and_not (cpu_arch_flags
,
12247 cpu_noarch
[j
].flags
);
12248 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
12250 if (cpu_sub_arch_name
)
12252 char *name
= cpu_sub_arch_name
;
12253 cpu_sub_arch_name
= concat (arch
,
12254 (const char *) NULL
);
12258 cpu_sub_arch_name
= xstrdup (arch
);
12259 cpu_arch_flags
= flags
;
12260 cpu_arch_isa_flags
= flags
;
12265 if (j
>= ARRAY_SIZE (cpu_noarch
))
12266 j
= ARRAY_SIZE (cpu_arch
);
12269 if (j
>= ARRAY_SIZE (cpu_arch
))
12270 as_fatal (_("invalid -march= option: `%s'"), arg
);
12274 while (next
!= NULL
);
12280 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
12281 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
12283 if (strcmp (arg
, cpu_arch
[j
].name
) == 0)
12285 cpu_arch_tune_set
= 1;
12286 cpu_arch_tune
= cpu_arch
[j
].type
;
12287 cpu_arch_tune_flags
= cpu_arch
[j
].flags
;
12291 if (j
>= ARRAY_SIZE (cpu_arch
))
12292 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
12295 case OPTION_MMNEMONIC
:
12296 if (strcasecmp (arg
, "att") == 0)
12297 intel_mnemonic
= 0;
12298 else if (strcasecmp (arg
, "intel") == 0)
12299 intel_mnemonic
= 1;
12301 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg
);
12304 case OPTION_MSYNTAX
:
12305 if (strcasecmp (arg
, "att") == 0)
12307 else if (strcasecmp (arg
, "intel") == 0)
12310 as_fatal (_("invalid -msyntax= option: `%s'"), arg
);
12313 case OPTION_MINDEX_REG
:
12314 allow_index_reg
= 1;
12317 case OPTION_MNAKED_REG
:
12318 allow_naked_reg
= 1;
12321 case OPTION_MSSE2AVX
:
12325 case OPTION_MSSE_CHECK
:
12326 if (strcasecmp (arg
, "error") == 0)
12327 sse_check
= check_error
;
12328 else if (strcasecmp (arg
, "warning") == 0)
12329 sse_check
= check_warning
;
12330 else if (strcasecmp (arg
, "none") == 0)
12331 sse_check
= check_none
;
12333 as_fatal (_("invalid -msse-check= option: `%s'"), arg
);
12336 case OPTION_MOPERAND_CHECK
:
12337 if (strcasecmp (arg
, "error") == 0)
12338 operand_check
= check_error
;
12339 else if (strcasecmp (arg
, "warning") == 0)
12340 operand_check
= check_warning
;
12341 else if (strcasecmp (arg
, "none") == 0)
12342 operand_check
= check_none
;
12344 as_fatal (_("invalid -moperand-check= option: `%s'"), arg
);
12347 case OPTION_MAVXSCALAR
:
12348 if (strcasecmp (arg
, "128") == 0)
12349 avxscalar
= vex128
;
12350 else if (strcasecmp (arg
, "256") == 0)
12351 avxscalar
= vex256
;
12353 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg
);
12356 case OPTION_MVEXWIG
:
12357 if (strcmp (arg
, "0") == 0)
12359 else if (strcmp (arg
, "1") == 0)
12362 as_fatal (_("invalid -mvexwig= option: `%s'"), arg
);
12365 case OPTION_MADD_BND_PREFIX
:
12366 add_bnd_prefix
= 1;
12369 case OPTION_MEVEXLIG
:
12370 if (strcmp (arg
, "128") == 0)
12371 evexlig
= evexl128
;
12372 else if (strcmp (arg
, "256") == 0)
12373 evexlig
= evexl256
;
12374 else if (strcmp (arg
, "512") == 0)
12375 evexlig
= evexl512
;
12377 as_fatal (_("invalid -mevexlig= option: `%s'"), arg
);
12380 case OPTION_MEVEXRCIG
:
12381 if (strcmp (arg
, "rne") == 0)
12383 else if (strcmp (arg
, "rd") == 0)
12385 else if (strcmp (arg
, "ru") == 0)
12387 else if (strcmp (arg
, "rz") == 0)
12390 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg
);
12393 case OPTION_MEVEXWIG
:
12394 if (strcmp (arg
, "0") == 0)
12396 else if (strcmp (arg
, "1") == 0)
12399 as_fatal (_("invalid -mevexwig= option: `%s'"), arg
);
12402 # if defined (TE_PE) || defined (TE_PEP)
12403 case OPTION_MBIG_OBJ
:
12408 case OPTION_MOMIT_LOCK_PREFIX
:
12409 if (strcasecmp (arg
, "yes") == 0)
12410 omit_lock_prefix
= 1;
12411 else if (strcasecmp (arg
, "no") == 0)
12412 omit_lock_prefix
= 0;
12414 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg
);
12417 case OPTION_MFENCE_AS_LOCK_ADD
:
12418 if (strcasecmp (arg
, "yes") == 0)
12420 else if (strcasecmp (arg
, "no") == 0)
12423 as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg
);
12426 case OPTION_MRELAX_RELOCATIONS
:
12427 if (strcasecmp (arg
, "yes") == 0)
12428 generate_relax_relocations
= 1;
12429 else if (strcasecmp (arg
, "no") == 0)
12430 generate_relax_relocations
= 0;
12432 as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg
);
12435 case OPTION_MALIGN_BRANCH_BOUNDARY
:
12438 long int align
= strtoul (arg
, &end
, 0);
12443 align_branch_power
= 0;
12446 else if (align
>= 16)
12449 for (align_power
= 0;
12451 align
>>= 1, align_power
++)
12453 /* Limit alignment power to 31. */
12454 if (align
== 1 && align_power
< 32)
12456 align_branch_power
= align_power
;
12461 as_fatal (_("invalid -malign-branch-boundary= value: %s"), arg
);
12465 case OPTION_MALIGN_BRANCH_PREFIX_SIZE
:
12468 int align
= strtoul (arg
, &end
, 0);
12469 /* Some processors only support 5 prefixes. */
12470 if (*end
== '\0' && align
>= 0 && align
< 6)
12472 align_branch_prefix_size
= align
;
12475 as_fatal (_("invalid -malign-branch-prefix-size= value: %s"),
12480 case OPTION_MALIGN_BRANCH
:
12482 saved
= xstrdup (arg
);
12486 next
= strchr (type
, '+');
12489 if (strcasecmp (type
, "jcc") == 0)
12490 align_branch
|= align_branch_jcc_bit
;
12491 else if (strcasecmp (type
, "fused") == 0)
12492 align_branch
|= align_branch_fused_bit
;
12493 else if (strcasecmp (type
, "jmp") == 0)
12494 align_branch
|= align_branch_jmp_bit
;
12495 else if (strcasecmp (type
, "call") == 0)
12496 align_branch
|= align_branch_call_bit
;
12497 else if (strcasecmp (type
, "ret") == 0)
12498 align_branch
|= align_branch_ret_bit
;
12499 else if (strcasecmp (type
, "indirect") == 0)
12500 align_branch
|= align_branch_indirect_bit
;
12502 as_fatal (_("invalid -malign-branch= option: `%s'"), arg
);
12505 while (next
!= NULL
);
12509 case OPTION_MBRANCHES_WITH_32B_BOUNDARIES
:
12510 align_branch_power
= 5;
12511 align_branch_prefix_size
= 5;
12512 align_branch
= (align_branch_jcc_bit
12513 | align_branch_fused_bit
12514 | align_branch_jmp_bit
);
12517 case OPTION_MAMD64
:
12521 case OPTION_MINTEL64
:
12529 /* Turn off -Os. */
12530 optimize_for_space
= 0;
12532 else if (*arg
== 's')
12534 optimize_for_space
= 1;
12535 /* Turn on all encoding optimizations. */
12536 optimize
= INT_MAX
;
12540 optimize
= atoi (arg
);
12541 /* Turn off -Os. */
12542 optimize_for_space
= 0;
12552 #define MESSAGE_TEMPLATE \
12556 output_message (FILE *stream
, char *p
, char *message
, char *start
,
12557 int *left_p
, const char *name
, int len
)
12559 int size
= sizeof (MESSAGE_TEMPLATE
);
12560 int left
= *left_p
;
12562 /* Reserve 2 spaces for ", " or ",\0" */
12565 /* Check if there is any room. */
12573 p
= mempcpy (p
, name
, len
);
12577 /* Output the current message now and start a new one. */
12580 fprintf (stream
, "%s\n", message
);
12582 left
= size
- (start
- message
) - len
- 2;
12584 gas_assert (left
>= 0);
12586 p
= mempcpy (p
, name
, len
);
12594 show_arch (FILE *stream
, int ext
, int check
)
12596 static char message
[] = MESSAGE_TEMPLATE
;
12597 char *start
= message
+ 27;
12599 int size
= sizeof (MESSAGE_TEMPLATE
);
12606 left
= size
- (start
- message
);
12607 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
12609 /* Should it be skipped? */
12610 if (cpu_arch
[j
].skip
)
12613 name
= cpu_arch
[j
].name
;
12614 len
= cpu_arch
[j
].len
;
12617 /* It is an extension. Skip if we aren't asked to show it. */
12628 /* It is an processor. Skip if we show only extension. */
12631 else if (check
&& ! cpu_arch
[j
].flags
.bitfield
.cpui386
)
12633 /* It is an impossible processor - skip. */
12637 p
= output_message (stream
, p
, message
, start
, &left
, name
, len
);
12640 /* Display disabled extensions. */
12642 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
12644 name
= cpu_noarch
[j
].name
;
12645 len
= cpu_noarch
[j
].len
;
12646 p
= output_message (stream
, p
, message
, start
, &left
, name
,
12651 fprintf (stream
, "%s\n", message
);
12655 md_show_usage (FILE *stream
)
12657 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12658 fprintf (stream
, _("\
12659 -Qy, -Qn ignored\n\
12660 -V print assembler version number\n\
12663 fprintf (stream
, _("\
12664 -n Do not optimize code alignment\n\
12665 -q quieten some warnings\n"));
12666 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12667 fprintf (stream
, _("\
12670 #if defined BFD64 && (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
12671 || defined (TE_PE) || defined (TE_PEP))
12672 fprintf (stream
, _("\
12673 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
12675 #ifdef SVR4_COMMENT_CHARS
12676 fprintf (stream
, _("\
12677 --divide do not treat `/' as a comment character\n"));
12679 fprintf (stream
, _("\
12680 --divide ignored\n"));
12682 fprintf (stream
, _("\
12683 -march=CPU[,+EXTENSION...]\n\
12684 generate code for CPU and EXTENSION, CPU is one of:\n"));
12685 show_arch (stream
, 0, 1);
12686 fprintf (stream
, _("\
12687 EXTENSION is combination of:\n"));
12688 show_arch (stream
, 1, 0);
12689 fprintf (stream
, _("\
12690 -mtune=CPU optimize for CPU, CPU is one of:\n"));
12691 show_arch (stream
, 0, 0);
12692 fprintf (stream
, _("\
12693 -msse2avx encode SSE instructions with VEX prefix\n"));
12694 fprintf (stream
, _("\
12695 -msse-check=[none|error|warning] (default: warning)\n\
12696 check SSE instructions\n"));
12697 fprintf (stream
, _("\
12698 -moperand-check=[none|error|warning] (default: warning)\n\
12699 check operand combinations for validity\n"));
12700 fprintf (stream
, _("\
12701 -mavxscalar=[128|256] (default: 128)\n\
12702 encode scalar AVX instructions with specific vector\n\
12704 fprintf (stream
, _("\
12705 -mvexwig=[0|1] (default: 0)\n\
12706 encode VEX instructions with specific VEX.W value\n\
12707 for VEX.W bit ignored instructions\n"));
12708 fprintf (stream
, _("\
12709 -mevexlig=[128|256|512] (default: 128)\n\
12710 encode scalar EVEX instructions with specific vector\n\
12712 fprintf (stream
, _("\
12713 -mevexwig=[0|1] (default: 0)\n\
12714 encode EVEX instructions with specific EVEX.W value\n\
12715 for EVEX.W bit ignored instructions\n"));
12716 fprintf (stream
, _("\
12717 -mevexrcig=[rne|rd|ru|rz] (default: rne)\n\
12718 encode EVEX instructions with specific EVEX.RC value\n\
12719 for SAE-only ignored instructions\n"));
12720 fprintf (stream
, _("\
12721 -mmnemonic=[att|intel] "));
12722 if (SYSV386_COMPAT
)
12723 fprintf (stream
, _("(default: att)\n"));
12725 fprintf (stream
, _("(default: intel)\n"));
12726 fprintf (stream
, _("\
12727 use AT&T/Intel mnemonic\n"));
12728 fprintf (stream
, _("\
12729 -msyntax=[att|intel] (default: att)\n\
12730 use AT&T/Intel syntax\n"));
12731 fprintf (stream
, _("\
12732 -mindex-reg support pseudo index registers\n"));
12733 fprintf (stream
, _("\
12734 -mnaked-reg don't require `%%' prefix for registers\n"));
12735 fprintf (stream
, _("\
12736 -madd-bnd-prefix add BND prefix for all valid branches\n"));
12737 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12738 fprintf (stream
, _("\
12739 -mshared disable branch optimization for shared code\n"));
12740 fprintf (stream
, _("\
12741 -mx86-used-note=[no|yes] "));
12742 if (DEFAULT_X86_USED_NOTE
)
12743 fprintf (stream
, _("(default: yes)\n"));
12745 fprintf (stream
, _("(default: no)\n"));
12746 fprintf (stream
, _("\
12747 generate x86 used ISA and feature properties\n"));
12749 #if defined (TE_PE) || defined (TE_PEP)
12750 fprintf (stream
, _("\
12751 -mbig-obj generate big object files\n"));
12753 fprintf (stream
, _("\
12754 -momit-lock-prefix=[no|yes] (default: no)\n\
12755 strip all lock prefixes\n"));
12756 fprintf (stream
, _("\
12757 -mfence-as-lock-add=[no|yes] (default: no)\n\
12758 encode lfence, mfence and sfence as\n\
12759 lock addl $0x0, (%%{re}sp)\n"));
12760 fprintf (stream
, _("\
12761 -mrelax-relocations=[no|yes] "));
12762 if (DEFAULT_GENERATE_X86_RELAX_RELOCATIONS
)
12763 fprintf (stream
, _("(default: yes)\n"));
12765 fprintf (stream
, _("(default: no)\n"));
12766 fprintf (stream
, _("\
12767 generate relax relocations\n"));
12768 fprintf (stream
, _("\
12769 -malign-branch-boundary=NUM (default: 0)\n\
12770 align branches within NUM byte boundary\n"));
12771 fprintf (stream
, _("\
12772 -malign-branch=TYPE[+TYPE...] (default: jcc+fused+jmp)\n\
12773 TYPE is combination of jcc, fused, jmp, call, ret,\n\
12775 specify types of branches to align\n"));
12776 fprintf (stream
, _("\
12777 -malign-branch-prefix-size=NUM (default: 5)\n\
12778 align branches with NUM prefixes per instruction\n"));
12779 fprintf (stream
, _("\
12780 -mbranches-within-32B-boundaries\n\
12781 align branches within 32 byte boundary\n"));
12782 fprintf (stream
, _("\
12783 -mamd64 accept only AMD64 ISA [default]\n"));
12784 fprintf (stream
, _("\
12785 -mintel64 accept only Intel64 ISA\n"));
12788 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
12789 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
12790 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
12792 /* Pick the target format to use. */
12795 i386_target_format (void)
12797 if (!strncmp (default_arch
, "x86_64", 6))
12799 update_code_flag (CODE_64BIT
, 1);
12800 if (default_arch
[6] == '\0')
12801 x86_elf_abi
= X86_64_ABI
;
12803 x86_elf_abi
= X86_64_X32_ABI
;
12805 else if (!strcmp (default_arch
, "i386"))
12806 update_code_flag (CODE_32BIT
, 1);
12807 else if (!strcmp (default_arch
, "iamcu"))
12809 update_code_flag (CODE_32BIT
, 1);
12810 if (cpu_arch_isa
== PROCESSOR_UNKNOWN
)
12812 static const i386_cpu_flags iamcu_flags
= CPU_IAMCU_FLAGS
;
12813 cpu_arch_name
= "iamcu";
12814 cpu_sub_arch_name
= NULL
;
12815 cpu_arch_flags
= iamcu_flags
;
12816 cpu_arch_isa
= PROCESSOR_IAMCU
;
12817 cpu_arch_isa_flags
= iamcu_flags
;
12818 if (!cpu_arch_tune_set
)
12820 cpu_arch_tune
= cpu_arch_isa
;
12821 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
12824 else if (cpu_arch_isa
!= PROCESSOR_IAMCU
)
12825 as_fatal (_("Intel MCU doesn't support `%s' architecture"),
12829 as_fatal (_("unknown architecture"));
12831 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
12832 cpu_arch_isa_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
12833 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
12834 cpu_arch_tune_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
12836 switch (OUTPUT_FLAVOR
)
12838 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
12839 case bfd_target_aout_flavour
:
12840 return AOUT_TARGET_FORMAT
;
12842 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
12843 # if defined (TE_PE) || defined (TE_PEP)
12844 case bfd_target_coff_flavour
:
12845 if (flag_code
== CODE_64BIT
)
12846 return use_big_obj
? "pe-bigobj-x86-64" : "pe-x86-64";
12849 # elif defined (TE_GO32)
12850 case bfd_target_coff_flavour
:
12851 return "coff-go32";
12853 case bfd_target_coff_flavour
:
12854 return "coff-i386";
12857 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
12858 case bfd_target_elf_flavour
:
12860 const char *format
;
12862 switch (x86_elf_abi
)
12865 format
= ELF_TARGET_FORMAT
;
12867 tls_get_addr
= "___tls_get_addr";
12871 use_rela_relocations
= 1;
12874 tls_get_addr
= "__tls_get_addr";
12876 format
= ELF_TARGET_FORMAT64
;
12878 case X86_64_X32_ABI
:
12879 use_rela_relocations
= 1;
12882 tls_get_addr
= "__tls_get_addr";
12884 disallow_64bit_reloc
= 1;
12885 format
= ELF_TARGET_FORMAT32
;
12888 if (cpu_arch_isa
== PROCESSOR_L1OM
)
12890 if (x86_elf_abi
!= X86_64_ABI
)
12891 as_fatal (_("Intel L1OM is 64bit only"));
12892 return ELF_TARGET_L1OM_FORMAT
;
12894 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
12896 if (x86_elf_abi
!= X86_64_ABI
)
12897 as_fatal (_("Intel K1OM is 64bit only"));
12898 return ELF_TARGET_K1OM_FORMAT
;
12900 else if (cpu_arch_isa
== PROCESSOR_IAMCU
)
12902 if (x86_elf_abi
!= I386_ABI
)
12903 as_fatal (_("Intel MCU is 32bit only"));
12904 return ELF_TARGET_IAMCU_FORMAT
;
12910 #if defined (OBJ_MACH_O)
12911 case bfd_target_mach_o_flavour
:
12912 if (flag_code
== CODE_64BIT
)
12914 use_rela_relocations
= 1;
12916 return "mach-o-x86-64";
12919 return "mach-o-i386";
12927 #endif /* OBJ_MAYBE_ more than one */
12930 md_undefined_symbol (char *name
)
12932 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
12933 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
12934 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
12935 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
12939 if (symbol_find (name
))
12940 as_bad (_("GOT already in symbol table"));
12941 GOT_symbol
= symbol_new (name
, undefined_section
,
12942 (valueT
) 0, &zero_address_frag
);
12949 /* Round up a section size to the appropriate boundary. */
12952 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
12954 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
12955 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
12957 /* For a.out, force the section size to be aligned. If we don't do
12958 this, BFD will align it for us, but it will not write out the
12959 final bytes of the section. This may be a bug in BFD, but it is
12960 easier to fix it here since that is how the other a.out targets
12964 align
= bfd_section_alignment (segment
);
12965 size
= ((size
+ (1 << align
) - 1) & (-((valueT
) 1 << align
)));
12972 /* On the i386, PC-relative offsets are relative to the start of the
12973 next instruction. That is, the address of the offset, plus its
12974 size, since the offset is always the last part of the insn. */
12977 md_pcrel_from (fixS
*fixP
)
12979 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
12985 s_bss (int ignore ATTRIBUTE_UNUSED
)
12989 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12991 obj_elf_section_change_hook ();
12993 temp
= get_absolute_expression ();
12994 subseg_set (bss_section
, (subsegT
) temp
);
12995 demand_empty_rest_of_line ();
13000 /* Remember constant directive. */
13003 i386_cons_align (int ignore ATTRIBUTE_UNUSED
)
13005 if (last_insn
.kind
!= last_insn_directive
13006 && (bfd_section_flags (now_seg
) & SEC_CODE
))
13008 last_insn
.seg
= now_seg
;
13009 last_insn
.kind
= last_insn_directive
;
13010 last_insn
.name
= "constant directive";
13011 last_insn
.file
= as_where (&last_insn
.line
);
13016 i386_validate_fix (fixS
*fixp
)
13018 if (fixp
->fx_subsy
)
13020 if (fixp
->fx_subsy
== GOT_symbol
)
13022 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
13026 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13027 if (fixp
->fx_tcbit2
)
13028 fixp
->fx_r_type
= (fixp
->fx_tcbit
13029 ? BFD_RELOC_X86_64_REX_GOTPCRELX
13030 : BFD_RELOC_X86_64_GOTPCRELX
);
13033 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
13038 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
13040 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
13042 fixp
->fx_subsy
= 0;
13045 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13046 else if (!object_64bit
)
13048 if (fixp
->fx_r_type
== BFD_RELOC_386_GOT32
13049 && fixp
->fx_tcbit2
)
13050 fixp
->fx_r_type
= BFD_RELOC_386_GOT32X
;
13056 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
13059 bfd_reloc_code_real_type code
;
13061 switch (fixp
->fx_r_type
)
13063 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13064 case BFD_RELOC_SIZE32
:
13065 case BFD_RELOC_SIZE64
:
13066 if (S_IS_DEFINED (fixp
->fx_addsy
)
13067 && !S_IS_EXTERNAL (fixp
->fx_addsy
))
13069 /* Resolve size relocation against local symbol to size of
13070 the symbol plus addend. */
13071 valueT value
= S_GET_SIZE (fixp
->fx_addsy
) + fixp
->fx_offset
;
13072 if (fixp
->fx_r_type
== BFD_RELOC_SIZE32
13073 && !fits_in_unsigned_long (value
))
13074 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
13075 _("symbol size computation overflow"));
13076 fixp
->fx_addsy
= NULL
;
13077 fixp
->fx_subsy
= NULL
;
13078 md_apply_fix (fixp
, (valueT
*) &value
, NULL
);
13082 /* Fall through. */
13084 case BFD_RELOC_X86_64_PLT32
:
13085 case BFD_RELOC_X86_64_GOT32
:
13086 case BFD_RELOC_X86_64_GOTPCREL
:
13087 case BFD_RELOC_X86_64_GOTPCRELX
:
13088 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
13089 case BFD_RELOC_386_PLT32
:
13090 case BFD_RELOC_386_GOT32
:
13091 case BFD_RELOC_386_GOT32X
:
13092 case BFD_RELOC_386_GOTOFF
:
13093 case BFD_RELOC_386_GOTPC
:
13094 case BFD_RELOC_386_TLS_GD
:
13095 case BFD_RELOC_386_TLS_LDM
:
13096 case BFD_RELOC_386_TLS_LDO_32
:
13097 case BFD_RELOC_386_TLS_IE_32
:
13098 case BFD_RELOC_386_TLS_IE
:
13099 case BFD_RELOC_386_TLS_GOTIE
:
13100 case BFD_RELOC_386_TLS_LE_32
:
13101 case BFD_RELOC_386_TLS_LE
:
13102 case BFD_RELOC_386_TLS_GOTDESC
:
13103 case BFD_RELOC_386_TLS_DESC_CALL
:
13104 case BFD_RELOC_X86_64_TLSGD
:
13105 case BFD_RELOC_X86_64_TLSLD
:
13106 case BFD_RELOC_X86_64_DTPOFF32
:
13107 case BFD_RELOC_X86_64_DTPOFF64
:
13108 case BFD_RELOC_X86_64_GOTTPOFF
:
13109 case BFD_RELOC_X86_64_TPOFF32
:
13110 case BFD_RELOC_X86_64_TPOFF64
:
13111 case BFD_RELOC_X86_64_GOTOFF64
:
13112 case BFD_RELOC_X86_64_GOTPC32
:
13113 case BFD_RELOC_X86_64_GOT64
:
13114 case BFD_RELOC_X86_64_GOTPCREL64
:
13115 case BFD_RELOC_X86_64_GOTPC64
:
13116 case BFD_RELOC_X86_64_GOTPLT64
:
13117 case BFD_RELOC_X86_64_PLTOFF64
:
13118 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
13119 case BFD_RELOC_X86_64_TLSDESC_CALL
:
13120 case BFD_RELOC_RVA
:
13121 case BFD_RELOC_VTABLE_ENTRY
:
13122 case BFD_RELOC_VTABLE_INHERIT
:
13124 case BFD_RELOC_32_SECREL
:
13126 code
= fixp
->fx_r_type
;
13128 case BFD_RELOC_X86_64_32S
:
13129 if (!fixp
->fx_pcrel
)
13131 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
13132 code
= fixp
->fx_r_type
;
13135 /* Fall through. */
13137 if (fixp
->fx_pcrel
)
13139 switch (fixp
->fx_size
)
13142 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
13143 _("can not do %d byte pc-relative relocation"),
13145 code
= BFD_RELOC_32_PCREL
;
13147 case 1: code
= BFD_RELOC_8_PCREL
; break;
13148 case 2: code
= BFD_RELOC_16_PCREL
; break;
13149 case 4: code
= BFD_RELOC_32_PCREL
; break;
13151 case 8: code
= BFD_RELOC_64_PCREL
; break;
13157 switch (fixp
->fx_size
)
13160 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
13161 _("can not do %d byte relocation"),
13163 code
= BFD_RELOC_32
;
13165 case 1: code
= BFD_RELOC_8
; break;
13166 case 2: code
= BFD_RELOC_16
; break;
13167 case 4: code
= BFD_RELOC_32
; break;
13169 case 8: code
= BFD_RELOC_64
; break;
13176 if ((code
== BFD_RELOC_32
13177 || code
== BFD_RELOC_32_PCREL
13178 || code
== BFD_RELOC_X86_64_32S
)
13180 && fixp
->fx_addsy
== GOT_symbol
)
13183 code
= BFD_RELOC_386_GOTPC
;
13185 code
= BFD_RELOC_X86_64_GOTPC32
;
13187 if ((code
== BFD_RELOC_64
|| code
== BFD_RELOC_64_PCREL
)
13189 && fixp
->fx_addsy
== GOT_symbol
)
13191 code
= BFD_RELOC_X86_64_GOTPC64
;
13194 rel
= XNEW (arelent
);
13195 rel
->sym_ptr_ptr
= XNEW (asymbol
*);
13196 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
13198 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
13200 if (!use_rela_relocations
)
13202 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
13203 vtable entry to be used in the relocation's section offset. */
13204 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
13205 rel
->address
= fixp
->fx_offset
;
13206 #if defined (OBJ_COFF) && defined (TE_PE)
13207 else if (fixp
->fx_addsy
&& S_IS_WEAK (fixp
->fx_addsy
))
13208 rel
->addend
= fixp
->fx_addnumber
- (S_GET_VALUE (fixp
->fx_addsy
) * 2);
13213 /* Use the rela in 64bit mode. */
13216 if (disallow_64bit_reloc
)
13219 case BFD_RELOC_X86_64_DTPOFF64
:
13220 case BFD_RELOC_X86_64_TPOFF64
:
13221 case BFD_RELOC_64_PCREL
:
13222 case BFD_RELOC_X86_64_GOTOFF64
:
13223 case BFD_RELOC_X86_64_GOT64
:
13224 case BFD_RELOC_X86_64_GOTPCREL64
:
13225 case BFD_RELOC_X86_64_GOTPC64
:
13226 case BFD_RELOC_X86_64_GOTPLT64
:
13227 case BFD_RELOC_X86_64_PLTOFF64
:
13228 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
13229 _("cannot represent relocation type %s in x32 mode"),
13230 bfd_get_reloc_code_name (code
));
13236 if (!fixp
->fx_pcrel
)
13237 rel
->addend
= fixp
->fx_offset
;
13241 case BFD_RELOC_X86_64_PLT32
:
13242 case BFD_RELOC_X86_64_GOT32
:
13243 case BFD_RELOC_X86_64_GOTPCREL
:
13244 case BFD_RELOC_X86_64_GOTPCRELX
:
13245 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
13246 case BFD_RELOC_X86_64_TLSGD
:
13247 case BFD_RELOC_X86_64_TLSLD
:
13248 case BFD_RELOC_X86_64_GOTTPOFF
:
13249 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
13250 case BFD_RELOC_X86_64_TLSDESC_CALL
:
13251 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
13254 rel
->addend
= (section
->vma
13256 + fixp
->fx_addnumber
13257 + md_pcrel_from (fixp
));
13262 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
13263 if (rel
->howto
== NULL
)
13265 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
13266 _("cannot represent relocation type %s"),
13267 bfd_get_reloc_code_name (code
));
13268 /* Set howto to a garbage value so that we can keep going. */
13269 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
13270 gas_assert (rel
->howto
!= NULL
);
13276 #include "tc-i386-intel.c"
13279 tc_x86_parse_to_dw2regnum (expressionS
*exp
)
13281 int saved_naked_reg
;
13282 char saved_register_dot
;
13284 saved_naked_reg
= allow_naked_reg
;
13285 allow_naked_reg
= 1;
13286 saved_register_dot
= register_chars
['.'];
13287 register_chars
['.'] = '.';
13288 allow_pseudo_reg
= 1;
13289 expression_and_evaluate (exp
);
13290 allow_pseudo_reg
= 0;
13291 register_chars
['.'] = saved_register_dot
;
13292 allow_naked_reg
= saved_naked_reg
;
13294 if (exp
->X_op
== O_register
&& exp
->X_add_number
>= 0)
13296 if ((addressT
) exp
->X_add_number
< i386_regtab_size
)
13298 exp
->X_op
= O_constant
;
13299 exp
->X_add_number
= i386_regtab
[exp
->X_add_number
]
13300 .dw2_regnum
[flag_code
>> 1];
13303 exp
->X_op
= O_illegal
;
13308 tc_x86_frame_initial_instructions (void)
13310 static unsigned int sp_regno
[2];
13312 if (!sp_regno
[flag_code
>> 1])
13314 char *saved_input
= input_line_pointer
;
13315 char sp
[][4] = {"esp", "rsp"};
13318 input_line_pointer
= sp
[flag_code
>> 1];
13319 tc_x86_parse_to_dw2regnum (&exp
);
13320 gas_assert (exp
.X_op
== O_constant
);
13321 sp_regno
[flag_code
>> 1] = exp
.X_add_number
;
13322 input_line_pointer
= saved_input
;
13325 cfi_add_CFA_def_cfa (sp_regno
[flag_code
>> 1], -x86_cie_data_alignment
);
13326 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
13330 x86_dwarf2_addr_size (void)
13332 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
13333 if (x86_elf_abi
== X86_64_X32_ABI
)
13336 return bfd_arch_bits_per_address (stdoutput
) / 8;
13340 i386_elf_section_type (const char *str
, size_t len
)
13342 if (flag_code
== CODE_64BIT
13343 && len
== sizeof ("unwind") - 1
13344 && strncmp (str
, "unwind", 6) == 0)
13345 return SHT_X86_64_UNWIND
;
13352 i386_solaris_fix_up_eh_frame (segT sec
)
13354 if (flag_code
== CODE_64BIT
)
13355 elf_section_type (sec
) = SHT_X86_64_UNWIND
;
13361 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
13365 exp
.X_op
= O_secrel
;
13366 exp
.X_add_symbol
= symbol
;
13367 exp
.X_add_number
= 0;
13368 emit_expr (&exp
, size
);
13372 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13373 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
13376 x86_64_section_letter (int letter
, const char **ptr_msg
)
13378 if (flag_code
== CODE_64BIT
)
13381 return SHF_X86_64_LARGE
;
13383 *ptr_msg
= _("bad .section directive: want a,l,w,x,M,S,G,T in string");
13386 *ptr_msg
= _("bad .section directive: want a,w,x,M,S,G,T in string");
13391 x86_64_section_word (char *str
, size_t len
)
13393 if (len
== 5 && flag_code
== CODE_64BIT
&& CONST_STRNEQ (str
, "large"))
13394 return SHF_X86_64_LARGE
;
13400 handle_large_common (int small ATTRIBUTE_UNUSED
)
13402 if (flag_code
!= CODE_64BIT
)
13404 s_comm_internal (0, elf_common_parse
);
13405 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
13409 static segT lbss_section
;
13410 asection
*saved_com_section_ptr
= elf_com_section_ptr
;
13411 asection
*saved_bss_section
= bss_section
;
13413 if (lbss_section
== NULL
)
13415 flagword applicable
;
13416 segT seg
= now_seg
;
13417 subsegT subseg
= now_subseg
;
13419 /* The .lbss section is for local .largecomm symbols. */
13420 lbss_section
= subseg_new (".lbss", 0);
13421 applicable
= bfd_applicable_section_flags (stdoutput
);
13422 bfd_set_section_flags (lbss_section
, applicable
& SEC_ALLOC
);
13423 seg_info (lbss_section
)->bss
= 1;
13425 subseg_set (seg
, subseg
);
13428 elf_com_section_ptr
= &_bfd_elf_large_com_section
;
13429 bss_section
= lbss_section
;
13431 s_comm_internal (0, elf_common_parse
);
13433 elf_com_section_ptr
= saved_com_section_ptr
;
13434 bss_section
= saved_bss_section
;
13437 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */