1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright (C) 1989-2018 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 /* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
23 x86_64 support by Jan Hubicka (jh@suse.cz)
24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
29 #include "safe-ctype.h"
31 #include "dwarf2dbg.h"
32 #include "dw2gencfi.h"
33 #include "elf/x86-64.h"
34 #include "opcodes/i386-init.h"
36 #ifndef REGISTER_WARNINGS
37 #define REGISTER_WARNINGS 1
40 #ifndef INFER_ADDR_PREFIX
41 #define INFER_ADDR_PREFIX 1
45 #define DEFAULT_ARCH "i386"
50 #define INLINE __inline__
56 /* Prefixes will be emitted in the order defined below.
57 WAIT_PREFIX must be the first prefix since FWAIT is really is an
58 instruction, and so must come before any prefixes.
59 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
60 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
66 #define HLE_PREFIX REP_PREFIX
67 #define BND_PREFIX REP_PREFIX
69 #define REX_PREFIX 6 /* must come last. */
70 #define MAX_PREFIXES 7 /* max prefixes per opcode */
72 /* we define the syntax here (modulo base,index,scale syntax) */
73 #define REGISTER_PREFIX '%'
74 #define IMMEDIATE_PREFIX '$'
75 #define ABSOLUTE_PREFIX '*'
77 /* these are the instruction mnemonic suffixes in AT&T syntax or
78 memory operand size in Intel syntax. */
79 #define WORD_MNEM_SUFFIX 'w'
80 #define BYTE_MNEM_SUFFIX 'b'
81 #define SHORT_MNEM_SUFFIX 's'
82 #define LONG_MNEM_SUFFIX 'l'
83 #define QWORD_MNEM_SUFFIX 'q'
84 /* Intel Syntax. Use a non-ascii letter since since it never appears
86 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
88 #define END_OF_INSN '\0'
91 'templates' is for grouping together 'template' structures for opcodes
92 of the same name. This is only used for storing the insns in the grand
93 ole hash table of insns.
94 The templates themselves start at START and range up to (but not including)
99 const insn_template
*start
;
100 const insn_template
*end
;
104 /* 386 operand encoding bytes: see 386 book for details of this. */
107 unsigned int regmem
; /* codes register or memory operand */
108 unsigned int reg
; /* codes register operand (or extended opcode) */
109 unsigned int mode
; /* how to interpret regmem & reg */
113 /* x86-64 extension prefix. */
114 typedef int rex_byte
;
116 /* 386 opcode byte to code indirect addressing. */
125 /* x86 arch names, types and features */
128 const char *name
; /* arch name */
129 unsigned int len
; /* arch string length */
130 enum processor_type type
; /* arch type */
131 i386_cpu_flags flags
; /* cpu feature flags */
132 unsigned int skip
; /* show_arch should skip this. */
136 /* Used to turn off indicated flags. */
139 const char *name
; /* arch name */
140 unsigned int len
; /* arch string length */
141 i386_cpu_flags flags
; /* cpu feature flags */
145 static void update_code_flag (int, int);
146 static void set_code_flag (int);
147 static void set_16bit_gcc_code_flag (int);
148 static void set_intel_syntax (int);
149 static void set_intel_mnemonic (int);
150 static void set_allow_index_reg (int);
151 static void set_check (int);
152 static void set_cpu_arch (int);
154 static void pe_directive_secrel (int);
156 static void signed_cons (int);
157 static char *output_invalid (int c
);
158 static int i386_finalize_immediate (segT
, expressionS
*, i386_operand_type
,
160 static int i386_finalize_displacement (segT
, expressionS
*, i386_operand_type
,
162 static int i386_att_operand (char *);
163 static int i386_intel_operand (char *, int);
164 static int i386_intel_simplify (expressionS
*);
165 static int i386_intel_parse_name (const char *, expressionS
*);
166 static const reg_entry
*parse_register (char *, char **);
167 static char *parse_insn (char *, char *);
168 static char *parse_operands (char *, const char *);
169 static void swap_operands (void);
170 static void swap_2_operands (int, int);
171 static void optimize_imm (void);
172 static void optimize_disp (void);
173 static const insn_template
*match_template (char);
174 static int check_string (void);
175 static int process_suffix (void);
176 static int check_byte_reg (void);
177 static int check_long_reg (void);
178 static int check_qword_reg (void);
179 static int check_word_reg (void);
180 static int finalize_imm (void);
181 static int process_operands (void);
182 static const seg_entry
*build_modrm_byte (void);
183 static void output_insn (void);
184 static void output_imm (fragS
*, offsetT
);
185 static void output_disp (fragS
*, offsetT
);
187 static void s_bss (int);
189 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
190 static void handle_large_common (int small ATTRIBUTE_UNUSED
);
192 /* GNU_PROPERTY_X86_ISA_1_USED. */
193 static unsigned int x86_isa_1_used
;
194 /* GNU_PROPERTY_X86_FEATURE_2_USED. */
195 static unsigned int x86_feature_2_used
;
196 /* Generate x86 used ISA and feature properties. */
197 static unsigned int x86_used_note
= DEFAULT_X86_USED_NOTE
;
200 static const char *default_arch
= DEFAULT_ARCH
;
202 /* This struct describes rounding control and SAE in the instruction. */
216 static struct RC_Operation rc_op
;
218 /* The struct describes masking, applied to OPERAND in the instruction.
219 MASK is a pointer to the corresponding mask register. ZEROING tells
220 whether merging or zeroing mask is used. */
221 struct Mask_Operation
223 const reg_entry
*mask
;
224 unsigned int zeroing
;
225 /* The operand where this operation is associated. */
229 static struct Mask_Operation mask_op
;
231 /* The struct describes broadcasting, applied to OPERAND. FACTOR is
233 struct Broadcast_Operation
235 /* Type of broadcast: {1to2}, {1to4}, {1to8}, or {1to16}. */
238 /* Index of broadcasted operand. */
241 /* Number of bytes to broadcast. */
245 static struct Broadcast_Operation broadcast_op
;
250 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
251 unsigned char bytes
[4];
253 /* Destination or source register specifier. */
254 const reg_entry
*register_specifier
;
257 /* 'md_assemble ()' gathers together information and puts it into a
264 const reg_entry
*regs
;
269 operand_size_mismatch
,
270 operand_type_mismatch
,
271 register_type_mismatch
,
272 number_of_operands_mismatch
,
273 invalid_instruction_suffix
,
275 unsupported_with_intel_mnemonic
,
278 invalid_vsib_address
,
279 invalid_vector_register_set
,
280 unsupported_vector_index_register
,
281 unsupported_broadcast
,
284 mask_not_on_destination
,
287 rc_sae_operand_not_last_imm
,
288 invalid_register_operand
,
293 /* TM holds the template for the insn were currently assembling. */
296 /* SUFFIX holds the instruction size suffix for byte, word, dword
297 or qword, if given. */
300 /* OPERANDS gives the number of given operands. */
301 unsigned int operands
;
303 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
304 of given register, displacement, memory operands and immediate
306 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
308 /* TYPES [i] is the type (see above #defines) which tells us how to
309 use OP[i] for the corresponding operand. */
310 i386_operand_type types
[MAX_OPERANDS
];
312 /* Displacement expression, immediate expression, or register for each
314 union i386_op op
[MAX_OPERANDS
];
316 /* Flags for operands. */
317 unsigned int flags
[MAX_OPERANDS
];
318 #define Operand_PCrel 1
319 #define Operand_Mem 2
321 /* Relocation type for operand */
322 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
324 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
325 the base index byte below. */
326 const reg_entry
*base_reg
;
327 const reg_entry
*index_reg
;
328 unsigned int log2_scale_factor
;
330 /* SEG gives the seg_entries of this insn. They are zero unless
331 explicit segment overrides are given. */
332 const seg_entry
*seg
[2];
334 /* Copied first memory operand string, for re-checking. */
337 /* PREFIX holds all the given prefix opcodes (usually null).
338 PREFIXES is the number of prefix opcodes. */
339 unsigned int prefixes
;
340 unsigned char prefix
[MAX_PREFIXES
];
342 /* Has MMX register operands. */
343 bfd_boolean has_regmmx
;
345 /* Has XMM register operands. */
346 bfd_boolean has_regxmm
;
348 /* Has YMM register operands. */
349 bfd_boolean has_regymm
;
351 /* Has ZMM register operands. */
352 bfd_boolean has_regzmm
;
354 /* RM and SIB are the modrm byte and the sib byte where the
355 addressing modes of this insn are encoded. */
362 /* Masking attributes. */
363 struct Mask_Operation
*mask
;
365 /* Rounding control and SAE attributes. */
366 struct RC_Operation
*rounding
;
368 /* Broadcasting attributes. */
369 struct Broadcast_Operation
*broadcast
;
371 /* Compressed disp8*N attribute. */
372 unsigned int memshift
;
374 /* Prefer load or store in encoding. */
377 dir_encoding_default
= 0,
382 /* Prefer 8bit or 32bit displacement in encoding. */
385 disp_encoding_default
= 0,
390 /* Prefer the REX byte in encoding. */
391 bfd_boolean rex_encoding
;
393 /* Disable instruction size optimization. */
394 bfd_boolean no_optimize
;
396 /* How to encode vector instructions. */
399 vex_encoding_default
= 0,
406 const char *rep_prefix
;
409 const char *hle_prefix
;
411 /* Have BND prefix. */
412 const char *bnd_prefix
;
414 /* Have NOTRACK prefix. */
415 const char *notrack_prefix
;
418 enum i386_error error
;
421 typedef struct _i386_insn i386_insn
;
423 /* Link RC type with corresponding string, that'll be looked for in
432 static const struct RC_name RC_NamesTable
[] =
434 { rne
, STRING_COMMA_LEN ("rn-sae") },
435 { rd
, STRING_COMMA_LEN ("rd-sae") },
436 { ru
, STRING_COMMA_LEN ("ru-sae") },
437 { rz
, STRING_COMMA_LEN ("rz-sae") },
438 { saeonly
, STRING_COMMA_LEN ("sae") },
441 /* List of chars besides those in app.c:symbol_chars that can start an
442 operand. Used to prevent the scrubber eating vital white-space. */
443 const char extra_symbol_chars
[] = "*%-([{}"
452 #if (defined (TE_I386AIX) \
453 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
454 && !defined (TE_GNU) \
455 && !defined (TE_LINUX) \
456 && !defined (TE_NACL) \
457 && !defined (TE_FreeBSD) \
458 && !defined (TE_DragonFly) \
459 && !defined (TE_NetBSD)))
460 /* This array holds the chars that always start a comment. If the
461 pre-processor is disabled, these aren't very useful. The option
462 --divide will remove '/' from this list. */
463 const char *i386_comment_chars
= "#/";
464 #define SVR4_COMMENT_CHARS 1
465 #define PREFIX_SEPARATOR '\\'
468 const char *i386_comment_chars
= "#";
469 #define PREFIX_SEPARATOR '/'
472 /* This array holds the chars that only start a comment at the beginning of
473 a line. If the line seems to have the form '# 123 filename'
474 .line and .file directives will appear in the pre-processed output.
475 Note that input_file.c hand checks for '#' at the beginning of the
476 first line of the input file. This is because the compiler outputs
477 #NO_APP at the beginning of its output.
478 Also note that comments started like this one will always work if
479 '/' isn't otherwise defined. */
480 const char line_comment_chars
[] = "#/";
482 const char line_separator_chars
[] = ";";
484 /* Chars that can be used to separate mant from exp in floating point
486 const char EXP_CHARS
[] = "eE";
488 /* Chars that mean this number is a floating point constant
491 const char FLT_CHARS
[] = "fFdDxX";
493 /* Tables for lexical analysis. */
494 static char mnemonic_chars
[256];
495 static char register_chars
[256];
496 static char operand_chars
[256];
497 static char identifier_chars
[256];
498 static char digit_chars
[256];
500 /* Lexical macros. */
501 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
502 #define is_operand_char(x) (operand_chars[(unsigned char) x])
503 #define is_register_char(x) (register_chars[(unsigned char) x])
504 #define is_space_char(x) ((x) == ' ')
505 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
506 #define is_digit_char(x) (digit_chars[(unsigned char) x])
508 /* All non-digit non-letter characters that may occur in an operand. */
509 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
511 /* md_assemble() always leaves the strings it's passed unaltered. To
512 effect this we maintain a stack of saved characters that we've smashed
513 with '\0's (indicating end of strings for various sub-fields of the
514 assembler instruction). */
515 static char save_stack
[32];
516 static char *save_stack_p
;
517 #define END_STRING_AND_SAVE(s) \
518 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
519 #define RESTORE_END_STRING(s) \
520 do { *(s) = *--save_stack_p; } while (0)
522 /* The instruction we're assembling. */
525 /* Possible templates for current insn. */
526 static const templates
*current_templates
;
528 /* Per instruction expressionS buffers: max displacements & immediates. */
529 static expressionS disp_expressions
[MAX_MEMORY_OPERANDS
];
530 static expressionS im_expressions
[MAX_IMMEDIATE_OPERANDS
];
532 /* Current operand we are working on. */
533 static int this_operand
= -1;
535 /* We support four different modes. FLAG_CODE variable is used to distinguish
543 static enum flag_code flag_code
;
544 static unsigned int object_64bit
;
545 static unsigned int disallow_64bit_reloc
;
546 static int use_rela_relocations
= 0;
548 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
549 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
550 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
552 /* The ELF ABI to use. */
560 static enum x86_elf_abi x86_elf_abi
= I386_ABI
;
563 #if defined (TE_PE) || defined (TE_PEP)
564 /* Use big object file format. */
565 static int use_big_obj
= 0;
568 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
569 /* 1 if generating code for a shared library. */
570 static int shared
= 0;
573 /* 1 for intel syntax,
575 static int intel_syntax
= 0;
577 /* 1 for Intel64 ISA,
581 /* 1 for intel mnemonic,
582 0 if att mnemonic. */
583 static int intel_mnemonic
= !SYSV386_COMPAT
;
585 /* 1 if pseudo registers are permitted. */
586 static int allow_pseudo_reg
= 0;
588 /* 1 if register prefix % not required. */
589 static int allow_naked_reg
= 0;
591 /* 1 if the assembler should add BND prefix for all control-transferring
592 instructions supporting it, even if this prefix wasn't specified
594 static int add_bnd_prefix
= 0;
596 /* 1 if pseudo index register, eiz/riz, is allowed . */
597 static int allow_index_reg
= 0;
599 /* 1 if the assembler should ignore LOCK prefix, even if it was
600 specified explicitly. */
601 static int omit_lock_prefix
= 0;
603 /* 1 if the assembler should encode lfence, mfence, and sfence as
604 "lock addl $0, (%{re}sp)". */
605 static int avoid_fence
= 0;
607 /* 1 if the assembler should generate relax relocations. */
609 static int generate_relax_relocations
610 = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS
;
612 static enum check_kind
618 sse_check
, operand_check
= check_warning
;
621 1. Clear the REX_W bit with register operand if possible.
622 2. Above plus use 128bit vector instruction to clear the full vector
625 static int optimize
= 0;
628 1. Clear the REX_W bit with register operand if possible.
629 2. Above plus use 128bit vector instruction to clear the full vector
631 3. Above plus optimize "test{q,l,w} $imm8,%r{64,32,16}" to
634 static int optimize_for_space
= 0;
636 /* Register prefix used for error message. */
637 static const char *register_prefix
= "%";
639 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
640 leave, push, and pop instructions so that gcc has the same stack
641 frame as in 32 bit mode. */
642 static char stackop_size
= '\0';
644 /* Non-zero to optimize code alignment. */
645 int optimize_align_code
= 1;
647 /* Non-zero to quieten some warnings. */
648 static int quiet_warnings
= 0;
651 static const char *cpu_arch_name
= NULL
;
652 static char *cpu_sub_arch_name
= NULL
;
654 /* CPU feature flags. */
655 static i386_cpu_flags cpu_arch_flags
= CPU_UNKNOWN_FLAGS
;
657 /* If we have selected a cpu we are generating instructions for. */
658 static int cpu_arch_tune_set
= 0;
660 /* Cpu we are generating instructions for. */
661 enum processor_type cpu_arch_tune
= PROCESSOR_UNKNOWN
;
663 /* CPU feature flags of cpu we are generating instructions for. */
664 static i386_cpu_flags cpu_arch_tune_flags
;
666 /* CPU instruction set architecture used. */
667 enum processor_type cpu_arch_isa
= PROCESSOR_UNKNOWN
;
669 /* CPU feature flags of instruction set architecture used. */
670 i386_cpu_flags cpu_arch_isa_flags
;
672 /* If set, conditional jumps are not automatically promoted to handle
673 larger than a byte offset. */
674 static unsigned int no_cond_jump_promotion
= 0;
676 /* Encode SSE instructions with VEX prefix. */
677 static unsigned int sse2avx
;
679 /* Encode scalar AVX instructions with specific vector length. */
686 /* Encode scalar EVEX LIG instructions with specific vector length. */
694 /* Encode EVEX WIG instructions with specific evex.w. */
701 /* Value to encode in EVEX RC bits, for SAE-only instructions. */
702 static enum rc_type evexrcig
= rne
;
704 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
705 static symbolS
*GOT_symbol
;
707 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
708 unsigned int x86_dwarf2_return_column
;
710 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
711 int x86_cie_data_alignment
;
713 /* Interface to relax_segment.
714 There are 3 major relax states for 386 jump insns because the
715 different types of jumps add different sizes to frags when we're
716 figuring out what sort of jump to choose to reach a given label. */
719 #define UNCOND_JUMP 0
721 #define COND_JUMP86 2
726 #define SMALL16 (SMALL | CODE16)
728 #define BIG16 (BIG | CODE16)
732 #define INLINE __inline__
738 #define ENCODE_RELAX_STATE(type, size) \
739 ((relax_substateT) (((type) << 2) | (size)))
740 #define TYPE_FROM_RELAX_STATE(s) \
742 #define DISP_SIZE_FROM_RELAX_STATE(s) \
743 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
745 /* This table is used by relax_frag to promote short jumps to long
746 ones where necessary. SMALL (short) jumps may be promoted to BIG
747 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
748 don't allow a short jump in a 32 bit code segment to be promoted to
749 a 16 bit offset jump because it's slower (requires data size
750 prefix), and doesn't work, unless the destination is in the bottom
751 64k of the code segment (The top 16 bits of eip are zeroed). */
753 const relax_typeS md_relax_table
[] =
756 1) most positive reach of this state,
757 2) most negative reach of this state,
758 3) how many bytes this mode will have in the variable part of the frag
759 4) which index into the table to try if we can't fit into this one. */
761 /* UNCOND_JUMP states. */
762 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
763 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
764 /* dword jmp adds 4 bytes to frag:
765 0 extra opcode bytes, 4 displacement bytes. */
767 /* word jmp adds 2 byte2 to frag:
768 0 extra opcode bytes, 2 displacement bytes. */
771 /* COND_JUMP states. */
772 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
773 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
774 /* dword conditionals adds 5 bytes to frag:
775 1 extra opcode byte, 4 displacement bytes. */
777 /* word conditionals add 3 bytes to frag:
778 1 extra opcode byte, 2 displacement bytes. */
781 /* COND_JUMP86 states. */
782 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
783 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
784 /* dword conditionals adds 5 bytes to frag:
785 1 extra opcode byte, 4 displacement bytes. */
787 /* word conditionals add 4 bytes to frag:
788 1 displacement byte and a 3 byte long branch insn. */
792 static const arch_entry cpu_arch
[] =
794 /* Do not replace the first two entries - i386_target_format()
795 relies on them being there in this order. */
796 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32
,
797 CPU_GENERIC32_FLAGS
, 0 },
798 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64
,
799 CPU_GENERIC64_FLAGS
, 0 },
800 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN
,
802 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN
,
804 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN
,
806 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386
,
808 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486
,
810 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM
,
812 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO
,
814 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM
,
816 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO
,
817 CPU_PENTIUMPRO_FLAGS
, 0 },
818 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO
,
820 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO
,
822 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4
,
824 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA
,
826 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA
,
827 CPU_NOCONA_FLAGS
, 0 },
828 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE
,
830 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE
,
832 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2
,
833 CPU_CORE2_FLAGS
, 1 },
834 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2
,
835 CPU_CORE2_FLAGS
, 0 },
836 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7
,
837 CPU_COREI7_FLAGS
, 0 },
838 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM
,
840 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM
,
842 { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU
,
843 CPU_IAMCU_FLAGS
, 0 },
844 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6
,
846 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6
,
848 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON
,
849 CPU_ATHLON_FLAGS
, 0 },
850 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8
,
852 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8
,
854 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8
,
856 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10
,
857 CPU_AMDFAM10_FLAGS
, 0 },
858 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD
,
859 CPU_BDVER1_FLAGS
, 0 },
860 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD
,
861 CPU_BDVER2_FLAGS
, 0 },
862 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD
,
863 CPU_BDVER3_FLAGS
, 0 },
864 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD
,
865 CPU_BDVER4_FLAGS
, 0 },
866 { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER
,
867 CPU_ZNVER1_FLAGS
, 0 },
868 { STRING_COMMA_LEN ("znver2"), PROCESSOR_ZNVER
,
869 CPU_ZNVER2_FLAGS
, 0 },
870 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT
,
871 CPU_BTVER1_FLAGS
, 0 },
872 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT
,
873 CPU_BTVER2_FLAGS
, 0 },
874 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN
,
876 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN
,
878 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN
,
880 { STRING_COMMA_LEN (".687"), PROCESSOR_UNKNOWN
,
882 { STRING_COMMA_LEN (".cmov"), PROCESSOR_UNKNOWN
,
884 { STRING_COMMA_LEN (".fxsr"), PROCESSOR_UNKNOWN
,
886 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN
,
888 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN
,
890 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN
,
892 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN
,
894 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN
,
895 CPU_SSSE3_FLAGS
, 0 },
896 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN
,
897 CPU_SSE4_1_FLAGS
, 0 },
898 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN
,
899 CPU_SSE4_2_FLAGS
, 0 },
900 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN
,
901 CPU_SSE4_2_FLAGS
, 0 },
902 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN
,
904 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN
,
906 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN
,
907 CPU_AVX512F_FLAGS
, 0 },
908 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN
,
909 CPU_AVX512CD_FLAGS
, 0 },
910 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN
,
911 CPU_AVX512ER_FLAGS
, 0 },
912 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN
,
913 CPU_AVX512PF_FLAGS
, 0 },
914 { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN
,
915 CPU_AVX512DQ_FLAGS
, 0 },
916 { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN
,
917 CPU_AVX512BW_FLAGS
, 0 },
918 { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN
,
919 CPU_AVX512VL_FLAGS
, 0 },
920 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN
,
922 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN
,
923 CPU_VMFUNC_FLAGS
, 0 },
924 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN
,
926 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN
,
927 CPU_XSAVE_FLAGS
, 0 },
928 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN
,
929 CPU_XSAVEOPT_FLAGS
, 0 },
930 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN
,
931 CPU_XSAVEC_FLAGS
, 0 },
932 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN
,
933 CPU_XSAVES_FLAGS
, 0 },
934 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN
,
936 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN
,
937 CPU_PCLMUL_FLAGS
, 0 },
938 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN
,
939 CPU_PCLMUL_FLAGS
, 1 },
940 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN
,
941 CPU_FSGSBASE_FLAGS
, 0 },
942 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN
,
943 CPU_RDRND_FLAGS
, 0 },
944 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN
,
946 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN
,
948 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN
,
950 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN
,
952 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN
,
954 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN
,
956 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN
,
957 CPU_MOVBE_FLAGS
, 0 },
958 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN
,
960 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN
,
962 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN
,
963 CPU_LZCNT_FLAGS
, 0 },
964 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN
,
966 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN
,
968 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN
,
969 CPU_INVPCID_FLAGS
, 0 },
970 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN
,
971 CPU_CLFLUSH_FLAGS
, 0 },
972 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN
,
974 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN
,
975 CPU_SYSCALL_FLAGS
, 0 },
976 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN
,
977 CPU_RDTSCP_FLAGS
, 0 },
978 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN
,
979 CPU_3DNOW_FLAGS
, 0 },
980 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN
,
981 CPU_3DNOWA_FLAGS
, 0 },
982 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN
,
983 CPU_PADLOCK_FLAGS
, 0 },
984 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN
,
986 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN
,
988 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN
,
989 CPU_SSE4A_FLAGS
, 0 },
990 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN
,
992 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN
,
994 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN
,
996 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN
,
998 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN
,
999 CPU_RDSEED_FLAGS
, 0 },
1000 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN
,
1001 CPU_PRFCHW_FLAGS
, 0 },
1002 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN
,
1003 CPU_SMAP_FLAGS
, 0 },
1004 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN
,
1006 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN
,
1008 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN
,
1009 CPU_CLFLUSHOPT_FLAGS
, 0 },
1010 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN
,
1011 CPU_PREFETCHWT1_FLAGS
, 0 },
1012 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN
,
1014 { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN
,
1015 CPU_CLWB_FLAGS
, 0 },
1016 { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN
,
1017 CPU_AVX512IFMA_FLAGS
, 0 },
1018 { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN
,
1019 CPU_AVX512VBMI_FLAGS
, 0 },
1020 { STRING_COMMA_LEN (".avx512_4fmaps"), PROCESSOR_UNKNOWN
,
1021 CPU_AVX512_4FMAPS_FLAGS
, 0 },
1022 { STRING_COMMA_LEN (".avx512_4vnniw"), PROCESSOR_UNKNOWN
,
1023 CPU_AVX512_4VNNIW_FLAGS
, 0 },
1024 { STRING_COMMA_LEN (".avx512_vpopcntdq"), PROCESSOR_UNKNOWN
,
1025 CPU_AVX512_VPOPCNTDQ_FLAGS
, 0 },
1026 { STRING_COMMA_LEN (".avx512_vbmi2"), PROCESSOR_UNKNOWN
,
1027 CPU_AVX512_VBMI2_FLAGS
, 0 },
1028 { STRING_COMMA_LEN (".avx512_vnni"), PROCESSOR_UNKNOWN
,
1029 CPU_AVX512_VNNI_FLAGS
, 0 },
1030 { STRING_COMMA_LEN (".avx512_bitalg"), PROCESSOR_UNKNOWN
,
1031 CPU_AVX512_BITALG_FLAGS
, 0 },
1032 { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN
,
1033 CPU_CLZERO_FLAGS
, 0 },
1034 { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN
,
1035 CPU_MWAITX_FLAGS
, 0 },
1036 { STRING_COMMA_LEN (".ospke"), PROCESSOR_UNKNOWN
,
1037 CPU_OSPKE_FLAGS
, 0 },
1038 { STRING_COMMA_LEN (".rdpid"), PROCESSOR_UNKNOWN
,
1039 CPU_RDPID_FLAGS
, 0 },
1040 { STRING_COMMA_LEN (".ptwrite"), PROCESSOR_UNKNOWN
,
1041 CPU_PTWRITE_FLAGS
, 0 },
1042 { STRING_COMMA_LEN (".ibt"), PROCESSOR_UNKNOWN
,
1044 { STRING_COMMA_LEN (".shstk"), PROCESSOR_UNKNOWN
,
1045 CPU_SHSTK_FLAGS
, 0 },
1046 { STRING_COMMA_LEN (".gfni"), PROCESSOR_UNKNOWN
,
1047 CPU_GFNI_FLAGS
, 0 },
1048 { STRING_COMMA_LEN (".vaes"), PROCESSOR_UNKNOWN
,
1049 CPU_VAES_FLAGS
, 0 },
1050 { STRING_COMMA_LEN (".vpclmulqdq"), PROCESSOR_UNKNOWN
,
1051 CPU_VPCLMULQDQ_FLAGS
, 0 },
1052 { STRING_COMMA_LEN (".wbnoinvd"), PROCESSOR_UNKNOWN
,
1053 CPU_WBNOINVD_FLAGS
, 0 },
1054 { STRING_COMMA_LEN (".pconfig"), PROCESSOR_UNKNOWN
,
1055 CPU_PCONFIG_FLAGS
, 0 },
1056 { STRING_COMMA_LEN (".waitpkg"), PROCESSOR_UNKNOWN
,
1057 CPU_WAITPKG_FLAGS
, 0 },
1058 { STRING_COMMA_LEN (".cldemote"), PROCESSOR_UNKNOWN
,
1059 CPU_CLDEMOTE_FLAGS
, 0 },
1060 { STRING_COMMA_LEN (".movdiri"), PROCESSOR_UNKNOWN
,
1061 CPU_MOVDIRI_FLAGS
, 0 },
1062 { STRING_COMMA_LEN (".movdir64b"), PROCESSOR_UNKNOWN
,
1063 CPU_MOVDIR64B_FLAGS
, 0 },
1066 static const noarch_entry cpu_noarch
[] =
1068 { STRING_COMMA_LEN ("no87"), CPU_ANY_X87_FLAGS
},
1069 { STRING_COMMA_LEN ("no287"), CPU_ANY_287_FLAGS
},
1070 { STRING_COMMA_LEN ("no387"), CPU_ANY_387_FLAGS
},
1071 { STRING_COMMA_LEN ("no687"), CPU_ANY_687_FLAGS
},
1072 { STRING_COMMA_LEN ("nocmov"), CPU_ANY_CMOV_FLAGS
},
1073 { STRING_COMMA_LEN ("nofxsr"), CPU_ANY_FXSR_FLAGS
},
1074 { STRING_COMMA_LEN ("nommx"), CPU_ANY_MMX_FLAGS
},
1075 { STRING_COMMA_LEN ("nosse"), CPU_ANY_SSE_FLAGS
},
1076 { STRING_COMMA_LEN ("nosse2"), CPU_ANY_SSE2_FLAGS
},
1077 { STRING_COMMA_LEN ("nosse3"), CPU_ANY_SSE3_FLAGS
},
1078 { STRING_COMMA_LEN ("nossse3"), CPU_ANY_SSSE3_FLAGS
},
1079 { STRING_COMMA_LEN ("nosse4.1"), CPU_ANY_SSE4_1_FLAGS
},
1080 { STRING_COMMA_LEN ("nosse4.2"), CPU_ANY_SSE4_2_FLAGS
},
1081 { STRING_COMMA_LEN ("nosse4"), CPU_ANY_SSE4_1_FLAGS
},
1082 { STRING_COMMA_LEN ("noavx"), CPU_ANY_AVX_FLAGS
},
1083 { STRING_COMMA_LEN ("noavx2"), CPU_ANY_AVX2_FLAGS
},
1084 { STRING_COMMA_LEN ("noavx512f"), CPU_ANY_AVX512F_FLAGS
},
1085 { STRING_COMMA_LEN ("noavx512cd"), CPU_ANY_AVX512CD_FLAGS
},
1086 { STRING_COMMA_LEN ("noavx512er"), CPU_ANY_AVX512ER_FLAGS
},
1087 { STRING_COMMA_LEN ("noavx512pf"), CPU_ANY_AVX512PF_FLAGS
},
1088 { STRING_COMMA_LEN ("noavx512dq"), CPU_ANY_AVX512DQ_FLAGS
},
1089 { STRING_COMMA_LEN ("noavx512bw"), CPU_ANY_AVX512BW_FLAGS
},
1090 { STRING_COMMA_LEN ("noavx512vl"), CPU_ANY_AVX512VL_FLAGS
},
1091 { STRING_COMMA_LEN ("noavx512ifma"), CPU_ANY_AVX512IFMA_FLAGS
},
1092 { STRING_COMMA_LEN ("noavx512vbmi"), CPU_ANY_AVX512VBMI_FLAGS
},
1093 { STRING_COMMA_LEN ("noavx512_4fmaps"), CPU_ANY_AVX512_4FMAPS_FLAGS
},
1094 { STRING_COMMA_LEN ("noavx512_4vnniw"), CPU_ANY_AVX512_4VNNIW_FLAGS
},
1095 { STRING_COMMA_LEN ("noavx512_vpopcntdq"), CPU_ANY_AVX512_VPOPCNTDQ_FLAGS
},
1096 { STRING_COMMA_LEN ("noavx512_vbmi2"), CPU_ANY_AVX512_VBMI2_FLAGS
},
1097 { STRING_COMMA_LEN ("noavx512_vnni"), CPU_ANY_AVX512_VNNI_FLAGS
},
1098 { STRING_COMMA_LEN ("noavx512_bitalg"), CPU_ANY_AVX512_BITALG_FLAGS
},
1099 { STRING_COMMA_LEN ("noibt"), CPU_ANY_IBT_FLAGS
},
1100 { STRING_COMMA_LEN ("noshstk"), CPU_ANY_SHSTK_FLAGS
},
1101 { STRING_COMMA_LEN ("nomovdiri"), CPU_ANY_MOVDIRI_FLAGS
},
1102 { STRING_COMMA_LEN ("nomovdir64b"), CPU_ANY_MOVDIR64B_FLAGS
},
1106 /* Like s_lcomm_internal in gas/read.c but the alignment string
1107 is allowed to be optional. */
1110 pe_lcomm_internal (int needs_align
, symbolS
*symbolP
, addressT size
)
1117 && *input_line_pointer
== ',')
1119 align
= parse_align (needs_align
- 1);
1121 if (align
== (addressT
) -1)
1136 bss_alloc (symbolP
, size
, align
);
1141 pe_lcomm (int needs_align
)
1143 s_comm_internal (needs_align
* 2, pe_lcomm_internal
);
1147 const pseudo_typeS md_pseudo_table
[] =
1149 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
1150 {"align", s_align_bytes
, 0},
1152 {"align", s_align_ptwo
, 0},
1154 {"arch", set_cpu_arch
, 0},
1158 {"lcomm", pe_lcomm
, 1},
1160 {"ffloat", float_cons
, 'f'},
1161 {"dfloat", float_cons
, 'd'},
1162 {"tfloat", float_cons
, 'x'},
1164 {"slong", signed_cons
, 4},
1165 {"noopt", s_ignore
, 0},
1166 {"optim", s_ignore
, 0},
1167 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
1168 {"code16", set_code_flag
, CODE_16BIT
},
1169 {"code32", set_code_flag
, CODE_32BIT
},
1171 {"code64", set_code_flag
, CODE_64BIT
},
1173 {"intel_syntax", set_intel_syntax
, 1},
1174 {"att_syntax", set_intel_syntax
, 0},
1175 {"intel_mnemonic", set_intel_mnemonic
, 1},
1176 {"att_mnemonic", set_intel_mnemonic
, 0},
1177 {"allow_index_reg", set_allow_index_reg
, 1},
1178 {"disallow_index_reg", set_allow_index_reg
, 0},
1179 {"sse_check", set_check
, 0},
1180 {"operand_check", set_check
, 1},
1181 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1182 {"largecomm", handle_large_common
, 0},
1184 {"file", dwarf2_directive_file
, 0},
1185 {"loc", dwarf2_directive_loc
, 0},
1186 {"loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0},
1189 {"secrel32", pe_directive_secrel
, 0},
1194 /* For interface with expression (). */
1195 extern char *input_line_pointer
;
1197 /* Hash table for instruction mnemonic lookup. */
1198 static struct hash_control
*op_hash
;
1200 /* Hash table for register lookup. */
1201 static struct hash_control
*reg_hash
;
1203 /* Various efficient no-op patterns for aligning code labels.
1204 Note: Don't try to assemble the instructions in the comments.
1205 0L and 0w are not legal. */
1206 static const unsigned char f32_1
[] =
1208 static const unsigned char f32_2
[] =
1209 {0x66,0x90}; /* xchg %ax,%ax */
1210 static const unsigned char f32_3
[] =
1211 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1212 static const unsigned char f32_4
[] =
1213 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1214 static const unsigned char f32_6
[] =
1215 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1216 static const unsigned char f32_7
[] =
1217 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1218 static const unsigned char f16_3
[] =
1219 {0x8d,0x74,0x00}; /* lea 0(%si),%si */
1220 static const unsigned char f16_4
[] =
1221 {0x8d,0xb4,0x00,0x00}; /* lea 0W(%si),%si */
1222 static const unsigned char jump_disp8
[] =
1223 {0xeb}; /* jmp disp8 */
1224 static const unsigned char jump32_disp32
[] =
1225 {0xe9}; /* jmp disp32 */
1226 static const unsigned char jump16_disp32
[] =
1227 {0x66,0xe9}; /* jmp disp32 */
1228 /* 32-bit NOPs patterns. */
1229 static const unsigned char *const f32_patt
[] = {
1230 f32_1
, f32_2
, f32_3
, f32_4
, NULL
, f32_6
, f32_7
1232 /* 16-bit NOPs patterns. */
1233 static const unsigned char *const f16_patt
[] = {
1234 f32_1
, f32_2
, f16_3
, f16_4
1236 /* nopl (%[re]ax) */
1237 static const unsigned char alt_3
[] =
1239 /* nopl 0(%[re]ax) */
1240 static const unsigned char alt_4
[] =
1241 {0x0f,0x1f,0x40,0x00};
1242 /* nopl 0(%[re]ax,%[re]ax,1) */
1243 static const unsigned char alt_5
[] =
1244 {0x0f,0x1f,0x44,0x00,0x00};
1245 /* nopw 0(%[re]ax,%[re]ax,1) */
1246 static const unsigned char alt_6
[] =
1247 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1248 /* nopl 0L(%[re]ax) */
1249 static const unsigned char alt_7
[] =
1250 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1251 /* nopl 0L(%[re]ax,%[re]ax,1) */
1252 static const unsigned char alt_8
[] =
1253 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1254 /* nopw 0L(%[re]ax,%[re]ax,1) */
1255 static const unsigned char alt_9
[] =
1256 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1257 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1258 static const unsigned char alt_10
[] =
1259 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1260 /* data16 nopw %cs:0L(%eax,%eax,1) */
1261 static const unsigned char alt_11
[] =
1262 {0x66,0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1263 /* 32-bit and 64-bit NOPs patterns. */
1264 static const unsigned char *const alt_patt
[] = {
1265 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
1266 alt_9
, alt_10
, alt_11
1269 /* Genenerate COUNT bytes of NOPs to WHERE from PATT with the maximum
1270 size of a single NOP instruction MAX_SINGLE_NOP_SIZE. */
1273 i386_output_nops (char *where
, const unsigned char *const *patt
,
1274 int count
, int max_single_nop_size
)
1277 /* Place the longer NOP first. */
1280 const unsigned char *nops
= patt
[max_single_nop_size
- 1];
1282 /* Use the smaller one if the requsted one isn't available. */
1285 max_single_nop_size
--;
1286 nops
= patt
[max_single_nop_size
- 1];
1289 last
= count
% max_single_nop_size
;
1292 for (offset
= 0; offset
< count
; offset
+= max_single_nop_size
)
1293 memcpy (where
+ offset
, nops
, max_single_nop_size
);
1297 nops
= patt
[last
- 1];
1300 /* Use the smaller one plus one-byte NOP if the needed one
1303 nops
= patt
[last
- 1];
1304 memcpy (where
+ offset
, nops
, last
);
1305 where
[offset
+ last
] = *patt
[0];
1308 memcpy (where
+ offset
, nops
, last
);
1313 fits_in_imm7 (offsetT num
)
1315 return (num
& 0x7f) == num
;
1319 fits_in_imm31 (offsetT num
)
1321 return (num
& 0x7fffffff) == num
;
1324 /* Genenerate COUNT bytes of NOPs to WHERE with the maximum size of a
1325 single NOP instruction LIMIT. */
1328 i386_generate_nops (fragS
*fragP
, char *where
, offsetT count
, int limit
)
1330 const unsigned char *const *patt
= NULL
;
1331 int max_single_nop_size
;
1332 /* Maximum number of NOPs before switching to jump over NOPs. */
1333 int max_number_of_nops
;
1335 switch (fragP
->fr_type
)
1344 /* We need to decide which NOP sequence to use for 32bit and
1345 64bit. When -mtune= is used:
1347 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1348 PROCESSOR_GENERIC32, f32_patt will be used.
1349 2. For the rest, alt_patt will be used.
1351 When -mtune= isn't used, alt_patt will be used if
1352 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
1355 When -march= or .arch is used, we can't use anything beyond
1356 cpu_arch_isa_flags. */
1358 if (flag_code
== CODE_16BIT
)
1361 max_single_nop_size
= sizeof (f16_patt
) / sizeof (f16_patt
[0]);
1362 /* Limit number of NOPs to 2 in 16-bit mode. */
1363 max_number_of_nops
= 2;
1367 if (fragP
->tc_frag_data
.isa
== PROCESSOR_UNKNOWN
)
1369 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1370 switch (cpu_arch_tune
)
1372 case PROCESSOR_UNKNOWN
:
1373 /* We use cpu_arch_isa_flags to check if we SHOULD
1374 optimize with nops. */
1375 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1380 case PROCESSOR_PENTIUM4
:
1381 case PROCESSOR_NOCONA
:
1382 case PROCESSOR_CORE
:
1383 case PROCESSOR_CORE2
:
1384 case PROCESSOR_COREI7
:
1385 case PROCESSOR_L1OM
:
1386 case PROCESSOR_K1OM
:
1387 case PROCESSOR_GENERIC64
:
1389 case PROCESSOR_ATHLON
:
1391 case PROCESSOR_AMDFAM10
:
1393 case PROCESSOR_ZNVER
:
1397 case PROCESSOR_I386
:
1398 case PROCESSOR_I486
:
1399 case PROCESSOR_PENTIUM
:
1400 case PROCESSOR_PENTIUMPRO
:
1401 case PROCESSOR_IAMCU
:
1402 case PROCESSOR_GENERIC32
:
1409 switch (fragP
->tc_frag_data
.tune
)
1411 case PROCESSOR_UNKNOWN
:
1412 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1413 PROCESSOR_UNKNOWN. */
1417 case PROCESSOR_I386
:
1418 case PROCESSOR_I486
:
1419 case PROCESSOR_PENTIUM
:
1420 case PROCESSOR_IAMCU
:
1422 case PROCESSOR_ATHLON
:
1424 case PROCESSOR_AMDFAM10
:
1426 case PROCESSOR_ZNVER
:
1428 case PROCESSOR_GENERIC32
:
1429 /* We use cpu_arch_isa_flags to check if we CAN optimize
1431 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1436 case PROCESSOR_PENTIUMPRO
:
1437 case PROCESSOR_PENTIUM4
:
1438 case PROCESSOR_NOCONA
:
1439 case PROCESSOR_CORE
:
1440 case PROCESSOR_CORE2
:
1441 case PROCESSOR_COREI7
:
1442 case PROCESSOR_L1OM
:
1443 case PROCESSOR_K1OM
:
1444 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1449 case PROCESSOR_GENERIC64
:
1455 if (patt
== f32_patt
)
1457 max_single_nop_size
= sizeof (f32_patt
) / sizeof (f32_patt
[0]);
1458 /* Limit number of NOPs to 2 for older processors. */
1459 max_number_of_nops
= 2;
1463 max_single_nop_size
= sizeof (alt_patt
) / sizeof (alt_patt
[0]);
1464 /* Limit number of NOPs to 7 for newer processors. */
1465 max_number_of_nops
= 7;
1470 limit
= max_single_nop_size
;
1472 if (fragP
->fr_type
== rs_fill_nop
)
1474 /* Output NOPs for .nop directive. */
1475 if (limit
> max_single_nop_size
)
1477 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
1478 _("invalid single nop size: %d "
1479 "(expect within [0, %d])"),
1480 limit
, max_single_nop_size
);
1485 fragP
->fr_var
= count
;
1487 if ((count
/ max_single_nop_size
) > max_number_of_nops
)
1489 /* Generate jump over NOPs. */
1490 offsetT disp
= count
- 2;
1491 if (fits_in_imm7 (disp
))
1493 /* Use "jmp disp8" if possible. */
1495 where
[0] = jump_disp8
[0];
1501 unsigned int size_of_jump
;
1503 if (flag_code
== CODE_16BIT
)
1505 where
[0] = jump16_disp32
[0];
1506 where
[1] = jump16_disp32
[1];
1511 where
[0] = jump32_disp32
[0];
1515 count
-= size_of_jump
+ 4;
1516 if (!fits_in_imm31 (count
))
1518 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
1519 _("jump over nop padding out of range"));
1523 md_number_to_chars (where
+ size_of_jump
, count
, 4);
1524 where
+= size_of_jump
+ 4;
1528 /* Generate multiple NOPs. */
1529 i386_output_nops (where
, patt
, count
, limit
);
1533 operand_type_all_zero (const union i386_operand_type
*x
)
1535 switch (ARRAY_SIZE(x
->array
))
1546 return !x
->array
[0];
1553 operand_type_set (union i386_operand_type
*x
, unsigned int v
)
1555 switch (ARRAY_SIZE(x
->array
))
1573 operand_type_equal (const union i386_operand_type
*x
,
1574 const union i386_operand_type
*y
)
1576 switch (ARRAY_SIZE(x
->array
))
1579 if (x
->array
[2] != y
->array
[2])
1583 if (x
->array
[1] != y
->array
[1])
1587 return x
->array
[0] == y
->array
[0];
1595 cpu_flags_all_zero (const union i386_cpu_flags
*x
)
1597 switch (ARRAY_SIZE(x
->array
))
1612 return !x
->array
[0];
1619 cpu_flags_equal (const union i386_cpu_flags
*x
,
1620 const union i386_cpu_flags
*y
)
1622 switch (ARRAY_SIZE(x
->array
))
1625 if (x
->array
[3] != y
->array
[3])
1629 if (x
->array
[2] != y
->array
[2])
1633 if (x
->array
[1] != y
->array
[1])
1637 return x
->array
[0] == y
->array
[0];
1645 cpu_flags_check_cpu64 (i386_cpu_flags f
)
1647 return !((flag_code
== CODE_64BIT
&& f
.bitfield
.cpuno64
)
1648 || (flag_code
!= CODE_64BIT
&& f
.bitfield
.cpu64
));
1651 static INLINE i386_cpu_flags
1652 cpu_flags_and (i386_cpu_flags x
, i386_cpu_flags y
)
1654 switch (ARRAY_SIZE (x
.array
))
1657 x
.array
[3] &= y
.array
[3];
1660 x
.array
[2] &= y
.array
[2];
1663 x
.array
[1] &= y
.array
[1];
1666 x
.array
[0] &= y
.array
[0];
1674 static INLINE i386_cpu_flags
1675 cpu_flags_or (i386_cpu_flags x
, i386_cpu_flags y
)
1677 switch (ARRAY_SIZE (x
.array
))
1680 x
.array
[3] |= y
.array
[3];
1683 x
.array
[2] |= y
.array
[2];
1686 x
.array
[1] |= y
.array
[1];
1689 x
.array
[0] |= y
.array
[0];
1697 static INLINE i386_cpu_flags
1698 cpu_flags_and_not (i386_cpu_flags x
, i386_cpu_flags y
)
1700 switch (ARRAY_SIZE (x
.array
))
1703 x
.array
[3] &= ~y
.array
[3];
1706 x
.array
[2] &= ~y
.array
[2];
1709 x
.array
[1] &= ~y
.array
[1];
1712 x
.array
[0] &= ~y
.array
[0];
1720 #define CPU_FLAGS_ARCH_MATCH 0x1
1721 #define CPU_FLAGS_64BIT_MATCH 0x2
1723 #define CPU_FLAGS_PERFECT_MATCH \
1724 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_64BIT_MATCH)
1726 /* Return CPU flags match bits. */
1729 cpu_flags_match (const insn_template
*t
)
1731 i386_cpu_flags x
= t
->cpu_flags
;
1732 int match
= cpu_flags_check_cpu64 (x
) ? CPU_FLAGS_64BIT_MATCH
: 0;
1734 x
.bitfield
.cpu64
= 0;
1735 x
.bitfield
.cpuno64
= 0;
1737 if (cpu_flags_all_zero (&x
))
1739 /* This instruction is available on all archs. */
1740 match
|= CPU_FLAGS_ARCH_MATCH
;
1744 /* This instruction is available only on some archs. */
1745 i386_cpu_flags cpu
= cpu_arch_flags
;
1747 /* AVX512VL is no standalone feature - match it and then strip it. */
1748 if (x
.bitfield
.cpuavx512vl
&& !cpu
.bitfield
.cpuavx512vl
)
1750 x
.bitfield
.cpuavx512vl
= 0;
1752 cpu
= cpu_flags_and (x
, cpu
);
1753 if (!cpu_flags_all_zero (&cpu
))
1755 if (x
.bitfield
.cpuavx
)
1757 /* We need to check a few extra flags with AVX. */
1758 if (cpu
.bitfield
.cpuavx
1759 && (!t
->opcode_modifier
.sse2avx
|| sse2avx
)
1760 && (!x
.bitfield
.cpuaes
|| cpu
.bitfield
.cpuaes
)
1761 && (!x
.bitfield
.cpugfni
|| cpu
.bitfield
.cpugfni
)
1762 && (!x
.bitfield
.cpupclmul
|| cpu
.bitfield
.cpupclmul
))
1763 match
|= CPU_FLAGS_ARCH_MATCH
;
1765 else if (x
.bitfield
.cpuavx512f
)
1767 /* We need to check a few extra flags with AVX512F. */
1768 if (cpu
.bitfield
.cpuavx512f
1769 && (!x
.bitfield
.cpugfni
|| cpu
.bitfield
.cpugfni
)
1770 && (!x
.bitfield
.cpuvaes
|| cpu
.bitfield
.cpuvaes
)
1771 && (!x
.bitfield
.cpuvpclmulqdq
|| cpu
.bitfield
.cpuvpclmulqdq
))
1772 match
|= CPU_FLAGS_ARCH_MATCH
;
1775 match
|= CPU_FLAGS_ARCH_MATCH
;
1781 static INLINE i386_operand_type
1782 operand_type_and (i386_operand_type x
, i386_operand_type y
)
1784 switch (ARRAY_SIZE (x
.array
))
1787 x
.array
[2] &= y
.array
[2];
1790 x
.array
[1] &= y
.array
[1];
1793 x
.array
[0] &= y
.array
[0];
1801 static INLINE i386_operand_type
1802 operand_type_and_not (i386_operand_type x
, i386_operand_type y
)
1804 switch (ARRAY_SIZE (x
.array
))
1807 x
.array
[2] &= ~y
.array
[2];
1810 x
.array
[1] &= ~y
.array
[1];
1813 x
.array
[0] &= ~y
.array
[0];
1821 static INLINE i386_operand_type
1822 operand_type_or (i386_operand_type x
, i386_operand_type y
)
1824 switch (ARRAY_SIZE (x
.array
))
1827 x
.array
[2] |= y
.array
[2];
1830 x
.array
[1] |= y
.array
[1];
1833 x
.array
[0] |= y
.array
[0];
1841 static INLINE i386_operand_type
1842 operand_type_xor (i386_operand_type x
, i386_operand_type y
)
1844 switch (ARRAY_SIZE (x
.array
))
1847 x
.array
[2] ^= y
.array
[2];
1850 x
.array
[1] ^= y
.array
[1];
1853 x
.array
[0] ^= y
.array
[0];
1861 static const i386_operand_type acc32
= OPERAND_TYPE_ACC32
;
1862 static const i386_operand_type acc64
= OPERAND_TYPE_ACC64
;
1863 static const i386_operand_type disp16
= OPERAND_TYPE_DISP16
;
1864 static const i386_operand_type disp32
= OPERAND_TYPE_DISP32
;
1865 static const i386_operand_type disp32s
= OPERAND_TYPE_DISP32S
;
1866 static const i386_operand_type disp16_32
= OPERAND_TYPE_DISP16_32
;
1867 static const i386_operand_type anydisp
1868 = OPERAND_TYPE_ANYDISP
;
1869 static const i386_operand_type regxmm
= OPERAND_TYPE_REGXMM
;
1870 static const i386_operand_type regmask
= OPERAND_TYPE_REGMASK
;
1871 static const i386_operand_type imm8
= OPERAND_TYPE_IMM8
;
1872 static const i386_operand_type imm8s
= OPERAND_TYPE_IMM8S
;
1873 static const i386_operand_type imm16
= OPERAND_TYPE_IMM16
;
1874 static const i386_operand_type imm32
= OPERAND_TYPE_IMM32
;
1875 static const i386_operand_type imm32s
= OPERAND_TYPE_IMM32S
;
1876 static const i386_operand_type imm64
= OPERAND_TYPE_IMM64
;
1877 static const i386_operand_type imm16_32
= OPERAND_TYPE_IMM16_32
;
1878 static const i386_operand_type imm16_32s
= OPERAND_TYPE_IMM16_32S
;
1879 static const i386_operand_type imm16_32_32s
= OPERAND_TYPE_IMM16_32_32S
;
1880 static const i386_operand_type vec_imm4
= OPERAND_TYPE_VEC_IMM4
;
1891 operand_type_check (i386_operand_type t
, enum operand_type c
)
1896 return t
.bitfield
.reg
;
1899 return (t
.bitfield
.imm8
1903 || t
.bitfield
.imm32s
1904 || t
.bitfield
.imm64
);
1907 return (t
.bitfield
.disp8
1908 || t
.bitfield
.disp16
1909 || t
.bitfield
.disp32
1910 || t
.bitfield
.disp32s
1911 || t
.bitfield
.disp64
);
1914 return (t
.bitfield
.disp8
1915 || t
.bitfield
.disp16
1916 || t
.bitfield
.disp32
1917 || t
.bitfield
.disp32s
1918 || t
.bitfield
.disp64
1919 || t
.bitfield
.baseindex
);
1928 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit/80bit size
1929 between operand GIVEN and opeand WANTED for instruction template T. */
1932 match_operand_size (const insn_template
*t
, unsigned int wanted
,
1935 return !((i
.types
[given
].bitfield
.byte
1936 && !t
->operand_types
[wanted
].bitfield
.byte
)
1937 || (i
.types
[given
].bitfield
.word
1938 && !t
->operand_types
[wanted
].bitfield
.word
)
1939 || (i
.types
[given
].bitfield
.dword
1940 && !t
->operand_types
[wanted
].bitfield
.dword
)
1941 || (i
.types
[given
].bitfield
.qword
1942 && !t
->operand_types
[wanted
].bitfield
.qword
)
1943 || (i
.types
[given
].bitfield
.tbyte
1944 && !t
->operand_types
[wanted
].bitfield
.tbyte
));
1947 /* Return 1 if there is no conflict in SIMD register between operand
1948 GIVEN and opeand WANTED for instruction template T. */
1951 match_simd_size (const insn_template
*t
, unsigned int wanted
,
1954 return !((i
.types
[given
].bitfield
.xmmword
1955 && !t
->operand_types
[wanted
].bitfield
.xmmword
)
1956 || (i
.types
[given
].bitfield
.ymmword
1957 && !t
->operand_types
[wanted
].bitfield
.ymmword
)
1958 || (i
.types
[given
].bitfield
.zmmword
1959 && !t
->operand_types
[wanted
].bitfield
.zmmword
));
1962 /* Return 1 if there is no conflict in any size between operand GIVEN
1963 and opeand WANTED for instruction template T. */
1966 match_mem_size (const insn_template
*t
, unsigned int wanted
,
1969 return (match_operand_size (t
, wanted
, given
)
1970 && !((i
.types
[given
].bitfield
.unspecified
1972 && !t
->operand_types
[wanted
].bitfield
.unspecified
)
1973 || (i
.types
[given
].bitfield
.fword
1974 && !t
->operand_types
[wanted
].bitfield
.fword
)
1975 /* For scalar opcode templates to allow register and memory
1976 operands at the same time, some special casing is needed
1977 here. Also for v{,p}broadcast*, {,v}pmov{s,z}*, and
1978 down-conversion vpmov*. */
1979 || ((t
->operand_types
[wanted
].bitfield
.regsimd
1980 && !t
->opcode_modifier
.broadcast
1981 && (t
->operand_types
[wanted
].bitfield
.byte
1982 || t
->operand_types
[wanted
].bitfield
.word
1983 || t
->operand_types
[wanted
].bitfield
.dword
1984 || t
->operand_types
[wanted
].bitfield
.qword
))
1985 ? (i
.types
[given
].bitfield
.xmmword
1986 || i
.types
[given
].bitfield
.ymmword
1987 || i
.types
[given
].bitfield
.zmmword
)
1988 : !match_simd_size(t
, wanted
, given
))));
1991 /* Return value has MATCH_STRAIGHT set if there is no size conflict on any
1992 operands for instruction template T, and it has MATCH_REVERSE set if there
1993 is no size conflict on any operands for the template with operands reversed
1994 (and the template allows for reversing in the first place). */
1996 #define MATCH_STRAIGHT 1
1997 #define MATCH_REVERSE 2
1999 static INLINE
unsigned int
2000 operand_size_match (const insn_template
*t
)
2002 unsigned int j
, match
= MATCH_STRAIGHT
;
2004 /* Don't check jump instructions. */
2005 if (t
->opcode_modifier
.jump
2006 || t
->opcode_modifier
.jumpbyte
2007 || t
->opcode_modifier
.jumpdword
2008 || t
->opcode_modifier
.jumpintersegment
)
2011 /* Check memory and accumulator operand size. */
2012 for (j
= 0; j
< i
.operands
; j
++)
2014 if (!i
.types
[j
].bitfield
.reg
&& !i
.types
[j
].bitfield
.regsimd
2015 && t
->operand_types
[j
].bitfield
.anysize
)
2018 if (t
->operand_types
[j
].bitfield
.reg
2019 && !match_operand_size (t
, j
, j
))
2025 if (t
->operand_types
[j
].bitfield
.regsimd
2026 && !match_simd_size (t
, j
, j
))
2032 if (t
->operand_types
[j
].bitfield
.acc
2033 && (!match_operand_size (t
, j
, j
) || !match_simd_size (t
, j
, j
)))
2039 if ((i
.flags
[j
] & Operand_Mem
) && !match_mem_size (t
, j
, j
))
2046 if (!t
->opcode_modifier
.d
)
2050 i
.error
= operand_size_mismatch
;
2054 /* Check reverse. */
2055 gas_assert (i
.operands
== 2);
2057 for (j
= 0; j
< 2; j
++)
2059 if ((t
->operand_types
[j
].bitfield
.reg
2060 || t
->operand_types
[j
].bitfield
.acc
)
2061 && !match_operand_size (t
, j
, !j
))
2064 if ((i
.flags
[!j
] & Operand_Mem
) && !match_mem_size (t
, j
, !j
))
2068 return match
| MATCH_REVERSE
;
2072 operand_type_match (i386_operand_type overlap
,
2073 i386_operand_type given
)
2075 i386_operand_type temp
= overlap
;
2077 temp
.bitfield
.jumpabsolute
= 0;
2078 temp
.bitfield
.unspecified
= 0;
2079 temp
.bitfield
.byte
= 0;
2080 temp
.bitfield
.word
= 0;
2081 temp
.bitfield
.dword
= 0;
2082 temp
.bitfield
.fword
= 0;
2083 temp
.bitfield
.qword
= 0;
2084 temp
.bitfield
.tbyte
= 0;
2085 temp
.bitfield
.xmmword
= 0;
2086 temp
.bitfield
.ymmword
= 0;
2087 temp
.bitfield
.zmmword
= 0;
2088 if (operand_type_all_zero (&temp
))
2091 if (given
.bitfield
.baseindex
== overlap
.bitfield
.baseindex
2092 && given
.bitfield
.jumpabsolute
== overlap
.bitfield
.jumpabsolute
)
2096 i
.error
= operand_type_mismatch
;
2100 /* If given types g0 and g1 are registers they must be of the same type
2101 unless the expected operand type register overlap is null.
2102 Memory operand size of certain SIMD instructions is also being checked
2106 operand_type_register_match (i386_operand_type g0
,
2107 i386_operand_type t0
,
2108 i386_operand_type g1
,
2109 i386_operand_type t1
)
2111 if (!g0
.bitfield
.reg
2112 && !g0
.bitfield
.regsimd
2113 && (!operand_type_check (g0
, anymem
)
2114 || g0
.bitfield
.unspecified
2115 || !t0
.bitfield
.regsimd
))
2118 if (!g1
.bitfield
.reg
2119 && !g1
.bitfield
.regsimd
2120 && (!operand_type_check (g1
, anymem
)
2121 || g1
.bitfield
.unspecified
2122 || !t1
.bitfield
.regsimd
))
2125 if (g0
.bitfield
.byte
== g1
.bitfield
.byte
2126 && g0
.bitfield
.word
== g1
.bitfield
.word
2127 && g0
.bitfield
.dword
== g1
.bitfield
.dword
2128 && g0
.bitfield
.qword
== g1
.bitfield
.qword
2129 && g0
.bitfield
.xmmword
== g1
.bitfield
.xmmword
2130 && g0
.bitfield
.ymmword
== g1
.bitfield
.ymmword
2131 && g0
.bitfield
.zmmword
== g1
.bitfield
.zmmword
)
2134 if (!(t0
.bitfield
.byte
& t1
.bitfield
.byte
)
2135 && !(t0
.bitfield
.word
& t1
.bitfield
.word
)
2136 && !(t0
.bitfield
.dword
& t1
.bitfield
.dword
)
2137 && !(t0
.bitfield
.qword
& t1
.bitfield
.qword
)
2138 && !(t0
.bitfield
.xmmword
& t1
.bitfield
.xmmword
)
2139 && !(t0
.bitfield
.ymmword
& t1
.bitfield
.ymmword
)
2140 && !(t0
.bitfield
.zmmword
& t1
.bitfield
.zmmword
))
2143 i
.error
= register_type_mismatch
;
2148 static INLINE
unsigned int
2149 register_number (const reg_entry
*r
)
2151 unsigned int nr
= r
->reg_num
;
2153 if (r
->reg_flags
& RegRex
)
2156 if (r
->reg_flags
& RegVRex
)
2162 static INLINE
unsigned int
2163 mode_from_disp_size (i386_operand_type t
)
2165 if (t
.bitfield
.disp8
)
2167 else if (t
.bitfield
.disp16
2168 || t
.bitfield
.disp32
2169 || t
.bitfield
.disp32s
)
2176 fits_in_signed_byte (addressT num
)
2178 return num
+ 0x80 <= 0xff;
2182 fits_in_unsigned_byte (addressT num
)
2188 fits_in_unsigned_word (addressT num
)
2190 return num
<= 0xffff;
2194 fits_in_signed_word (addressT num
)
2196 return num
+ 0x8000 <= 0xffff;
2200 fits_in_signed_long (addressT num ATTRIBUTE_UNUSED
)
2205 return num
+ 0x80000000 <= 0xffffffff;
2207 } /* fits_in_signed_long() */
2210 fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED
)
2215 return num
<= 0xffffffff;
2217 } /* fits_in_unsigned_long() */
2220 fits_in_disp8 (offsetT num
)
2222 int shift
= i
.memshift
;
2228 mask
= (1 << shift
) - 1;
2230 /* Return 0 if NUM isn't properly aligned. */
2234 /* Check if NUM will fit in 8bit after shift. */
2235 return fits_in_signed_byte (num
>> shift
);
2239 fits_in_imm4 (offsetT num
)
2241 return (num
& 0xf) == num
;
2244 static i386_operand_type
2245 smallest_imm_type (offsetT num
)
2247 i386_operand_type t
;
2249 operand_type_set (&t
, 0);
2250 t
.bitfield
.imm64
= 1;
2252 if (cpu_arch_tune
!= PROCESSOR_I486
&& num
== 1)
2254 /* This code is disabled on the 486 because all the Imm1 forms
2255 in the opcode table are slower on the i486. They're the
2256 versions with the implicitly specified single-position
2257 displacement, which has another syntax if you really want to
2259 t
.bitfield
.imm1
= 1;
2260 t
.bitfield
.imm8
= 1;
2261 t
.bitfield
.imm8s
= 1;
2262 t
.bitfield
.imm16
= 1;
2263 t
.bitfield
.imm32
= 1;
2264 t
.bitfield
.imm32s
= 1;
2266 else if (fits_in_signed_byte (num
))
2268 t
.bitfield
.imm8
= 1;
2269 t
.bitfield
.imm8s
= 1;
2270 t
.bitfield
.imm16
= 1;
2271 t
.bitfield
.imm32
= 1;
2272 t
.bitfield
.imm32s
= 1;
2274 else if (fits_in_unsigned_byte (num
))
2276 t
.bitfield
.imm8
= 1;
2277 t
.bitfield
.imm16
= 1;
2278 t
.bitfield
.imm32
= 1;
2279 t
.bitfield
.imm32s
= 1;
2281 else if (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
2283 t
.bitfield
.imm16
= 1;
2284 t
.bitfield
.imm32
= 1;
2285 t
.bitfield
.imm32s
= 1;
2287 else if (fits_in_signed_long (num
))
2289 t
.bitfield
.imm32
= 1;
2290 t
.bitfield
.imm32s
= 1;
2292 else if (fits_in_unsigned_long (num
))
2293 t
.bitfield
.imm32
= 1;
2299 offset_in_range (offsetT val
, int size
)
2305 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
2306 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
2307 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
2309 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
2315 /* If BFD64, sign extend val for 32bit address mode. */
2316 if (flag_code
!= CODE_64BIT
2317 || i
.prefix
[ADDR_PREFIX
])
2318 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
2319 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
2322 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
2324 char buf1
[40], buf2
[40];
2326 sprint_value (buf1
, val
);
2327 sprint_value (buf2
, val
& mask
);
2328 as_warn (_("%s shortened to %s"), buf1
, buf2
);
2343 a. PREFIX_EXIST if attempting to add a prefix where one from the
2344 same class already exists.
2345 b. PREFIX_LOCK if lock prefix is added.
2346 c. PREFIX_REP if rep/repne prefix is added.
2347 d. PREFIX_DS if ds prefix is added.
2348 e. PREFIX_OTHER if other prefix is added.
2351 static enum PREFIX_GROUP
2352 add_prefix (unsigned int prefix
)
2354 enum PREFIX_GROUP ret
= PREFIX_OTHER
;
2357 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
2358 && flag_code
== CODE_64BIT
)
2360 if ((i
.prefix
[REX_PREFIX
] & prefix
& REX_W
)
2361 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_R
)
2362 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_X
)
2363 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_B
))
2374 case DS_PREFIX_OPCODE
:
2377 case CS_PREFIX_OPCODE
:
2378 case ES_PREFIX_OPCODE
:
2379 case FS_PREFIX_OPCODE
:
2380 case GS_PREFIX_OPCODE
:
2381 case SS_PREFIX_OPCODE
:
2385 case REPNE_PREFIX_OPCODE
:
2386 case REPE_PREFIX_OPCODE
:
2391 case LOCK_PREFIX_OPCODE
:
2400 case ADDR_PREFIX_OPCODE
:
2404 case DATA_PREFIX_OPCODE
:
2408 if (i
.prefix
[q
] != 0)
2416 i
.prefix
[q
] |= prefix
;
2419 as_bad (_("same type of prefix used twice"));
2425 update_code_flag (int value
, int check
)
2427 PRINTF_LIKE ((*as_error
));
2429 flag_code
= (enum flag_code
) value
;
2430 if (flag_code
== CODE_64BIT
)
2432 cpu_arch_flags
.bitfield
.cpu64
= 1;
2433 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2437 cpu_arch_flags
.bitfield
.cpu64
= 0;
2438 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2440 if (value
== CODE_64BIT
&& !cpu_arch_flags
.bitfield
.cpulm
)
2443 as_error
= as_fatal
;
2446 (*as_error
) (_("64bit mode not supported on `%s'."),
2447 cpu_arch_name
? cpu_arch_name
: default_arch
);
2449 if (value
== CODE_32BIT
&& !cpu_arch_flags
.bitfield
.cpui386
)
2452 as_error
= as_fatal
;
2455 (*as_error
) (_("32bit mode not supported on `%s'."),
2456 cpu_arch_name
? cpu_arch_name
: default_arch
);
2458 stackop_size
= '\0';
2462 set_code_flag (int value
)
2464 update_code_flag (value
, 0);
2468 set_16bit_gcc_code_flag (int new_code_flag
)
2470 flag_code
= (enum flag_code
) new_code_flag
;
2471 if (flag_code
!= CODE_16BIT
)
2473 cpu_arch_flags
.bitfield
.cpu64
= 0;
2474 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2475 stackop_size
= LONG_MNEM_SUFFIX
;
2479 set_intel_syntax (int syntax_flag
)
2481 /* Find out if register prefixing is specified. */
2482 int ask_naked_reg
= 0;
2485 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2488 int e
= get_symbol_name (&string
);
2490 if (strcmp (string
, "prefix") == 0)
2492 else if (strcmp (string
, "noprefix") == 0)
2495 as_bad (_("bad argument to syntax directive."));
2496 (void) restore_line_pointer (e
);
2498 demand_empty_rest_of_line ();
2500 intel_syntax
= syntax_flag
;
2502 if (ask_naked_reg
== 0)
2503 allow_naked_reg
= (intel_syntax
2504 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
2506 allow_naked_reg
= (ask_naked_reg
< 0);
2508 expr_set_rank (O_full_ptr
, syntax_flag
? 10 : 0);
2510 identifier_chars
['%'] = intel_syntax
&& allow_naked_reg
? '%' : 0;
2511 identifier_chars
['$'] = intel_syntax
? '$' : 0;
2512 register_prefix
= allow_naked_reg
? "" : "%";
2516 set_intel_mnemonic (int mnemonic_flag
)
2518 intel_mnemonic
= mnemonic_flag
;
2522 set_allow_index_reg (int flag
)
2524 allow_index_reg
= flag
;
2528 set_check (int what
)
2530 enum check_kind
*kind
;
2535 kind
= &operand_check
;
2546 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2549 int e
= get_symbol_name (&string
);
2551 if (strcmp (string
, "none") == 0)
2553 else if (strcmp (string
, "warning") == 0)
2554 *kind
= check_warning
;
2555 else if (strcmp (string
, "error") == 0)
2556 *kind
= check_error
;
2558 as_bad (_("bad argument to %s_check directive."), str
);
2559 (void) restore_line_pointer (e
);
2562 as_bad (_("missing argument for %s_check directive"), str
);
2564 demand_empty_rest_of_line ();
2568 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED
,
2569 i386_cpu_flags new_flag ATTRIBUTE_UNUSED
)
2571 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2572 static const char *arch
;
2574 /* Intel LIOM is only supported on ELF. */
2580 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2581 use default_arch. */
2582 arch
= cpu_arch_name
;
2584 arch
= default_arch
;
2587 /* If we are targeting Intel MCU, we must enable it. */
2588 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_IAMCU
2589 || new_flag
.bitfield
.cpuiamcu
)
2592 /* If we are targeting Intel L1OM, we must enable it. */
2593 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_L1OM
2594 || new_flag
.bitfield
.cpul1om
)
2597 /* If we are targeting Intel K1OM, we must enable it. */
2598 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_K1OM
2599 || new_flag
.bitfield
.cpuk1om
)
2602 as_bad (_("`%s' is not supported on `%s'"), name
, arch
);
2607 set_cpu_arch (int dummy ATTRIBUTE_UNUSED
)
2611 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2614 int e
= get_symbol_name (&string
);
2616 i386_cpu_flags flags
;
2618 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
2620 if (strcmp (string
, cpu_arch
[j
].name
) == 0)
2622 check_cpu_arch_compatible (string
, cpu_arch
[j
].flags
);
2626 cpu_arch_name
= cpu_arch
[j
].name
;
2627 cpu_sub_arch_name
= NULL
;
2628 cpu_arch_flags
= cpu_arch
[j
].flags
;
2629 if (flag_code
== CODE_64BIT
)
2631 cpu_arch_flags
.bitfield
.cpu64
= 1;
2632 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2636 cpu_arch_flags
.bitfield
.cpu64
= 0;
2637 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2639 cpu_arch_isa
= cpu_arch
[j
].type
;
2640 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
2641 if (!cpu_arch_tune_set
)
2643 cpu_arch_tune
= cpu_arch_isa
;
2644 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
2649 flags
= cpu_flags_or (cpu_arch_flags
,
2652 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2654 if (cpu_sub_arch_name
)
2656 char *name
= cpu_sub_arch_name
;
2657 cpu_sub_arch_name
= concat (name
,
2659 (const char *) NULL
);
2663 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
2664 cpu_arch_flags
= flags
;
2665 cpu_arch_isa_flags
= flags
;
2669 = cpu_flags_or (cpu_arch_isa_flags
,
2671 (void) restore_line_pointer (e
);
2672 demand_empty_rest_of_line ();
2677 if (*string
== '.' && j
>= ARRAY_SIZE (cpu_arch
))
2679 /* Disable an ISA extension. */
2680 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
2681 if (strcmp (string
+ 1, cpu_noarch
[j
].name
) == 0)
2683 flags
= cpu_flags_and_not (cpu_arch_flags
,
2684 cpu_noarch
[j
].flags
);
2685 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2687 if (cpu_sub_arch_name
)
2689 char *name
= cpu_sub_arch_name
;
2690 cpu_sub_arch_name
= concat (name
, string
,
2691 (const char *) NULL
);
2695 cpu_sub_arch_name
= xstrdup (string
);
2696 cpu_arch_flags
= flags
;
2697 cpu_arch_isa_flags
= flags
;
2699 (void) restore_line_pointer (e
);
2700 demand_empty_rest_of_line ();
2704 j
= ARRAY_SIZE (cpu_arch
);
2707 if (j
>= ARRAY_SIZE (cpu_arch
))
2708 as_bad (_("no such architecture: `%s'"), string
);
2710 *input_line_pointer
= e
;
2713 as_bad (_("missing cpu architecture"));
2715 no_cond_jump_promotion
= 0;
2716 if (*input_line_pointer
== ','
2717 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
2722 ++input_line_pointer
;
2723 e
= get_symbol_name (&string
);
2725 if (strcmp (string
, "nojumps") == 0)
2726 no_cond_jump_promotion
= 1;
2727 else if (strcmp (string
, "jumps") == 0)
2730 as_bad (_("no such architecture modifier: `%s'"), string
);
2732 (void) restore_line_pointer (e
);
2735 demand_empty_rest_of_line ();
2738 enum bfd_architecture
2741 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2743 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2744 || flag_code
!= CODE_64BIT
)
2745 as_fatal (_("Intel L1OM is 64bit ELF only"));
2746 return bfd_arch_l1om
;
2748 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2750 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2751 || flag_code
!= CODE_64BIT
)
2752 as_fatal (_("Intel K1OM is 64bit ELF only"));
2753 return bfd_arch_k1om
;
2755 else if (cpu_arch_isa
== PROCESSOR_IAMCU
)
2757 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2758 || flag_code
== CODE_64BIT
)
2759 as_fatal (_("Intel MCU is 32bit ELF only"));
2760 return bfd_arch_iamcu
;
2763 return bfd_arch_i386
;
2769 if (!strncmp (default_arch
, "x86_64", 6))
2771 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2773 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2774 || default_arch
[6] != '\0')
2775 as_fatal (_("Intel L1OM is 64bit ELF only"));
2776 return bfd_mach_l1om
;
2778 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2780 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2781 || default_arch
[6] != '\0')
2782 as_fatal (_("Intel K1OM is 64bit ELF only"));
2783 return bfd_mach_k1om
;
2785 else if (default_arch
[6] == '\0')
2786 return bfd_mach_x86_64
;
2788 return bfd_mach_x64_32
;
2790 else if (!strcmp (default_arch
, "i386")
2791 || !strcmp (default_arch
, "iamcu"))
2793 if (cpu_arch_isa
== PROCESSOR_IAMCU
)
2795 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
2796 as_fatal (_("Intel MCU is 32bit ELF only"));
2797 return bfd_mach_i386_iamcu
;
2800 return bfd_mach_i386_i386
;
2803 as_fatal (_("unknown architecture"));
2809 const char *hash_err
;
2811 /* Support pseudo prefixes like {disp32}. */
2812 lex_type
['{'] = LEX_BEGIN_NAME
;
2814 /* Initialize op_hash hash table. */
2815 op_hash
= hash_new ();
2818 const insn_template
*optab
;
2819 templates
*core_optab
;
2821 /* Setup for loop. */
2823 core_optab
= XNEW (templates
);
2824 core_optab
->start
= optab
;
2829 if (optab
->name
== NULL
2830 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
2832 /* different name --> ship out current template list;
2833 add to hash table; & begin anew. */
2834 core_optab
->end
= optab
;
2835 hash_err
= hash_insert (op_hash
,
2837 (void *) core_optab
);
2840 as_fatal (_("can't hash %s: %s"),
2844 if (optab
->name
== NULL
)
2846 core_optab
= XNEW (templates
);
2847 core_optab
->start
= optab
;
2852 /* Initialize reg_hash hash table. */
2853 reg_hash
= hash_new ();
2855 const reg_entry
*regtab
;
2856 unsigned int regtab_size
= i386_regtab_size
;
2858 for (regtab
= i386_regtab
; regtab_size
--; regtab
++)
2860 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (void *) regtab
);
2862 as_fatal (_("can't hash %s: %s"),
2868 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
2873 for (c
= 0; c
< 256; c
++)
2878 mnemonic_chars
[c
] = c
;
2879 register_chars
[c
] = c
;
2880 operand_chars
[c
] = c
;
2882 else if (ISLOWER (c
))
2884 mnemonic_chars
[c
] = c
;
2885 register_chars
[c
] = c
;
2886 operand_chars
[c
] = c
;
2888 else if (ISUPPER (c
))
2890 mnemonic_chars
[c
] = TOLOWER (c
);
2891 register_chars
[c
] = mnemonic_chars
[c
];
2892 operand_chars
[c
] = c
;
2894 else if (c
== '{' || c
== '}')
2896 mnemonic_chars
[c
] = c
;
2897 operand_chars
[c
] = c
;
2900 if (ISALPHA (c
) || ISDIGIT (c
))
2901 identifier_chars
[c
] = c
;
2904 identifier_chars
[c
] = c
;
2905 operand_chars
[c
] = c
;
2910 identifier_chars
['@'] = '@';
2913 identifier_chars
['?'] = '?';
2914 operand_chars
['?'] = '?';
2916 digit_chars
['-'] = '-';
2917 mnemonic_chars
['_'] = '_';
2918 mnemonic_chars
['-'] = '-';
2919 mnemonic_chars
['.'] = '.';
2920 identifier_chars
['_'] = '_';
2921 identifier_chars
['.'] = '.';
2923 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
2924 operand_chars
[(unsigned char) *p
] = *p
;
2927 if (flag_code
== CODE_64BIT
)
2929 #if defined (OBJ_COFF) && defined (TE_PE)
2930 x86_dwarf2_return_column
= (OUTPUT_FLAVOR
== bfd_target_coff_flavour
2933 x86_dwarf2_return_column
= 16;
2935 x86_cie_data_alignment
= -8;
2939 x86_dwarf2_return_column
= 8;
2940 x86_cie_data_alignment
= -4;
2945 i386_print_statistics (FILE *file
)
2947 hash_print_statistics (file
, "i386 opcode", op_hash
);
2948 hash_print_statistics (file
, "i386 register", reg_hash
);
2953 /* Debugging routines for md_assemble. */
2954 static void pte (insn_template
*);
2955 static void pt (i386_operand_type
);
2956 static void pe (expressionS
*);
2957 static void ps (symbolS
*);
2960 pi (char *line
, i386_insn
*x
)
2964 fprintf (stdout
, "%s: template ", line
);
2966 fprintf (stdout
, " address: base %s index %s scale %x\n",
2967 x
->base_reg
? x
->base_reg
->reg_name
: "none",
2968 x
->index_reg
? x
->index_reg
->reg_name
: "none",
2969 x
->log2_scale_factor
);
2970 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
2971 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
2972 fprintf (stdout
, " sib: base %x index %x scale %x\n",
2973 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
2974 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
2975 (x
->rex
& REX_W
) != 0,
2976 (x
->rex
& REX_R
) != 0,
2977 (x
->rex
& REX_X
) != 0,
2978 (x
->rex
& REX_B
) != 0);
2979 for (j
= 0; j
< x
->operands
; j
++)
2981 fprintf (stdout
, " #%d: ", j
+ 1);
2983 fprintf (stdout
, "\n");
2984 if (x
->types
[j
].bitfield
.reg
2985 || x
->types
[j
].bitfield
.regmmx
2986 || x
->types
[j
].bitfield
.regsimd
2987 || x
->types
[j
].bitfield
.sreg2
2988 || x
->types
[j
].bitfield
.sreg3
2989 || x
->types
[j
].bitfield
.control
2990 || x
->types
[j
].bitfield
.debug
2991 || x
->types
[j
].bitfield
.test
)
2992 fprintf (stdout
, "%s\n", x
->op
[j
].regs
->reg_name
);
2993 if (operand_type_check (x
->types
[j
], imm
))
2995 if (operand_type_check (x
->types
[j
], disp
))
2996 pe (x
->op
[j
].disps
);
3001 pte (insn_template
*t
)
3004 fprintf (stdout
, " %d operands ", t
->operands
);
3005 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
3006 if (t
->extension_opcode
!= None
)
3007 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
3008 if (t
->opcode_modifier
.d
)
3009 fprintf (stdout
, "D");
3010 if (t
->opcode_modifier
.w
)
3011 fprintf (stdout
, "W");
3012 fprintf (stdout
, "\n");
3013 for (j
= 0; j
< t
->operands
; j
++)
3015 fprintf (stdout
, " #%d type ", j
+ 1);
3016 pt (t
->operand_types
[j
]);
3017 fprintf (stdout
, "\n");
3024 fprintf (stdout
, " operation %d\n", e
->X_op
);
3025 fprintf (stdout
, " add_number %ld (%lx)\n",
3026 (long) e
->X_add_number
, (long) e
->X_add_number
);
3027 if (e
->X_add_symbol
)
3029 fprintf (stdout
, " add_symbol ");
3030 ps (e
->X_add_symbol
);
3031 fprintf (stdout
, "\n");
3035 fprintf (stdout
, " op_symbol ");
3036 ps (e
->X_op_symbol
);
3037 fprintf (stdout
, "\n");
3044 fprintf (stdout
, "%s type %s%s",
3046 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
3047 segment_name (S_GET_SEGMENT (s
)));
3050 static struct type_name
3052 i386_operand_type mask
;
3055 const type_names
[] =
3057 { OPERAND_TYPE_REG8
, "r8" },
3058 { OPERAND_TYPE_REG16
, "r16" },
3059 { OPERAND_TYPE_REG32
, "r32" },
3060 { OPERAND_TYPE_REG64
, "r64" },
3061 { OPERAND_TYPE_IMM8
, "i8" },
3062 { OPERAND_TYPE_IMM8
, "i8s" },
3063 { OPERAND_TYPE_IMM16
, "i16" },
3064 { OPERAND_TYPE_IMM32
, "i32" },
3065 { OPERAND_TYPE_IMM32S
, "i32s" },
3066 { OPERAND_TYPE_IMM64
, "i64" },
3067 { OPERAND_TYPE_IMM1
, "i1" },
3068 { OPERAND_TYPE_BASEINDEX
, "BaseIndex" },
3069 { OPERAND_TYPE_DISP8
, "d8" },
3070 { OPERAND_TYPE_DISP16
, "d16" },
3071 { OPERAND_TYPE_DISP32
, "d32" },
3072 { OPERAND_TYPE_DISP32S
, "d32s" },
3073 { OPERAND_TYPE_DISP64
, "d64" },
3074 { OPERAND_TYPE_INOUTPORTREG
, "InOutPortReg" },
3075 { OPERAND_TYPE_SHIFTCOUNT
, "ShiftCount" },
3076 { OPERAND_TYPE_CONTROL
, "control reg" },
3077 { OPERAND_TYPE_TEST
, "test reg" },
3078 { OPERAND_TYPE_DEBUG
, "debug reg" },
3079 { OPERAND_TYPE_FLOATREG
, "FReg" },
3080 { OPERAND_TYPE_FLOATACC
, "FAcc" },
3081 { OPERAND_TYPE_SREG2
, "SReg2" },
3082 { OPERAND_TYPE_SREG3
, "SReg3" },
3083 { OPERAND_TYPE_ACC
, "Acc" },
3084 { OPERAND_TYPE_JUMPABSOLUTE
, "Jump Absolute" },
3085 { OPERAND_TYPE_REGMMX
, "rMMX" },
3086 { OPERAND_TYPE_REGXMM
, "rXMM" },
3087 { OPERAND_TYPE_REGYMM
, "rYMM" },
3088 { OPERAND_TYPE_REGZMM
, "rZMM" },
3089 { OPERAND_TYPE_REGMASK
, "Mask reg" },
3090 { OPERAND_TYPE_ESSEG
, "es" },
3094 pt (i386_operand_type t
)
3097 i386_operand_type a
;
3099 for (j
= 0; j
< ARRAY_SIZE (type_names
); j
++)
3101 a
= operand_type_and (t
, type_names
[j
].mask
);
3102 if (!operand_type_all_zero (&a
))
3103 fprintf (stdout
, "%s, ", type_names
[j
].name
);
3108 #endif /* DEBUG386 */
3110 static bfd_reloc_code_real_type
3111 reloc (unsigned int size
,
3114 bfd_reloc_code_real_type other
)
3116 if (other
!= NO_RELOC
)
3118 reloc_howto_type
*rel
;
3123 case BFD_RELOC_X86_64_GOT32
:
3124 return BFD_RELOC_X86_64_GOT64
;
3126 case BFD_RELOC_X86_64_GOTPLT64
:
3127 return BFD_RELOC_X86_64_GOTPLT64
;
3129 case BFD_RELOC_X86_64_PLTOFF64
:
3130 return BFD_RELOC_X86_64_PLTOFF64
;
3132 case BFD_RELOC_X86_64_GOTPC32
:
3133 other
= BFD_RELOC_X86_64_GOTPC64
;
3135 case BFD_RELOC_X86_64_GOTPCREL
:
3136 other
= BFD_RELOC_X86_64_GOTPCREL64
;
3138 case BFD_RELOC_X86_64_TPOFF32
:
3139 other
= BFD_RELOC_X86_64_TPOFF64
;
3141 case BFD_RELOC_X86_64_DTPOFF32
:
3142 other
= BFD_RELOC_X86_64_DTPOFF64
;
3148 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3149 if (other
== BFD_RELOC_SIZE32
)
3152 other
= BFD_RELOC_SIZE64
;
3155 as_bad (_("there are no pc-relative size relocations"));
3161 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
3162 if (size
== 4 && (flag_code
!= CODE_64BIT
|| disallow_64bit_reloc
))
3165 rel
= bfd_reloc_type_lookup (stdoutput
, other
);
3167 as_bad (_("unknown relocation (%u)"), other
);
3168 else if (size
!= bfd_get_reloc_size (rel
))
3169 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
3170 bfd_get_reloc_size (rel
),
3172 else if (pcrel
&& !rel
->pc_relative
)
3173 as_bad (_("non-pc-relative relocation for pc-relative field"));
3174 else if ((rel
->complain_on_overflow
== complain_overflow_signed
3176 || (rel
->complain_on_overflow
== complain_overflow_unsigned
3178 as_bad (_("relocated field and relocation type differ in signedness"));
3187 as_bad (_("there are no unsigned pc-relative relocations"));
3190 case 1: return BFD_RELOC_8_PCREL
;
3191 case 2: return BFD_RELOC_16_PCREL
;
3192 case 4: return BFD_RELOC_32_PCREL
;
3193 case 8: return BFD_RELOC_64_PCREL
;
3195 as_bad (_("cannot do %u byte pc-relative relocation"), size
);
3202 case 4: return BFD_RELOC_X86_64_32S
;
3207 case 1: return BFD_RELOC_8
;
3208 case 2: return BFD_RELOC_16
;
3209 case 4: return BFD_RELOC_32
;
3210 case 8: return BFD_RELOC_64
;
3212 as_bad (_("cannot do %s %u byte relocation"),
3213 sign
> 0 ? "signed" : "unsigned", size
);
3219 /* Here we decide which fixups can be adjusted to make them relative to
3220 the beginning of the section instead of the symbol. Basically we need
3221 to make sure that the dynamic relocations are done correctly, so in
3222 some cases we force the original symbol to be used. */
3225 tc_i386_fix_adjustable (fixS
*fixP ATTRIBUTE_UNUSED
)
3227 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3231 /* Don't adjust pc-relative references to merge sections in 64-bit
3233 if (use_rela_relocations
3234 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
3238 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
3239 and changed later by validate_fix. */
3240 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
3241 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
3244 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
3245 for size relocations. */
3246 if (fixP
->fx_r_type
== BFD_RELOC_SIZE32
3247 || fixP
->fx_r_type
== BFD_RELOC_SIZE64
3248 || fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
3249 || fixP
->fx_r_type
== BFD_RELOC_386_PLT32
3250 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
3251 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32X
3252 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
3253 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
3254 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
3255 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
3256 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
3257 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
3258 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
3259 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
3260 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTDESC
3261 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_DESC_CALL
3262 || fixP
->fx_r_type
== BFD_RELOC_X86_64_PLT32
3263 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
3264 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
3265 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCRELX
3266 || fixP
->fx_r_type
== BFD_RELOC_X86_64_REX_GOTPCRELX
3267 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
3268 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
3269 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
3270 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
3271 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
3272 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
3273 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
3274 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
3275 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPC32_TLSDESC
3276 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSDESC_CALL
3277 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
3278 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
3285 intel_float_operand (const char *mnemonic
)
3287 /* Note that the value returned is meaningful only for opcodes with (memory)
3288 operands, hence the code here is free to improperly handle opcodes that
3289 have no operands (for better performance and smaller code). */
3291 if (mnemonic
[0] != 'f')
3292 return 0; /* non-math */
3294 switch (mnemonic
[1])
3296 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
3297 the fs segment override prefix not currently handled because no
3298 call path can make opcodes without operands get here */
3300 return 2 /* integer op */;
3302 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
3303 return 3; /* fldcw/fldenv */
3306 if (mnemonic
[2] != 'o' /* fnop */)
3307 return 3; /* non-waiting control op */
3310 if (mnemonic
[2] == 's')
3311 return 3; /* frstor/frstpm */
3314 if (mnemonic
[2] == 'a')
3315 return 3; /* fsave */
3316 if (mnemonic
[2] == 't')
3318 switch (mnemonic
[3])
3320 case 'c': /* fstcw */
3321 case 'd': /* fstdw */
3322 case 'e': /* fstenv */
3323 case 's': /* fsts[gw] */
3329 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
3330 return 0; /* fxsave/fxrstor are not really math ops */
3337 /* Build the VEX prefix. */
3340 build_vex_prefix (const insn_template
*t
)
3342 unsigned int register_specifier
;
3343 unsigned int implied_prefix
;
3344 unsigned int vector_length
;
3346 /* Check register specifier. */
3347 if (i
.vex
.register_specifier
)
3349 register_specifier
=
3350 ~register_number (i
.vex
.register_specifier
) & 0xf;
3351 gas_assert ((i
.vex
.register_specifier
->reg_flags
& RegVRex
) == 0);
3354 register_specifier
= 0xf;
3356 /* Use 2-byte VEX prefix by swapping destination and source
3358 if (i
.vec_encoding
!= vex_encoding_vex3
3359 && i
.dir_encoding
== dir_encoding_default
3360 && i
.operands
== i
.reg_operands
3361 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3362 && i
.tm
.opcode_modifier
.load
3365 unsigned int xchg
= i
.operands
- 1;
3366 union i386_op temp_op
;
3367 i386_operand_type temp_type
;
3369 temp_type
= i
.types
[xchg
];
3370 i
.types
[xchg
] = i
.types
[0];
3371 i
.types
[0] = temp_type
;
3372 temp_op
= i
.op
[xchg
];
3373 i
.op
[xchg
] = i
.op
[0];
3376 gas_assert (i
.rm
.mode
== 3);
3380 i
.rm
.regmem
= i
.rm
.reg
;
3383 /* Use the next insn. */
3387 if (i
.tm
.opcode_modifier
.vex
== VEXScalar
)
3388 vector_length
= avxscalar
;
3389 else if (i
.tm
.opcode_modifier
.vex
== VEX256
)
3395 /* Determine vector length from the last multi-length vector
3398 for (op
= t
->operands
; op
--;)
3399 if (t
->operand_types
[op
].bitfield
.xmmword
3400 && t
->operand_types
[op
].bitfield
.ymmword
3401 && i
.types
[op
].bitfield
.ymmword
)
3408 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3413 case DATA_PREFIX_OPCODE
:
3416 case REPE_PREFIX_OPCODE
:
3419 case REPNE_PREFIX_OPCODE
:
3426 /* Use 2-byte VEX prefix if possible. */
3427 if (i
.vec_encoding
!= vex_encoding_vex3
3428 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3429 && i
.tm
.opcode_modifier
.vexw
!= VEXW1
3430 && (i
.rex
& (REX_W
| REX_X
| REX_B
)) == 0)
3432 /* 2-byte VEX prefix. */
3436 i
.vex
.bytes
[0] = 0xc5;
3438 /* Check the REX.R bit. */
3439 r
= (i
.rex
& REX_R
) ? 0 : 1;
3440 i
.vex
.bytes
[1] = (r
<< 7
3441 | register_specifier
<< 3
3442 | vector_length
<< 2
3447 /* 3-byte VEX prefix. */
3452 switch (i
.tm
.opcode_modifier
.vexopcode
)
3456 i
.vex
.bytes
[0] = 0xc4;
3460 i
.vex
.bytes
[0] = 0xc4;
3464 i
.vex
.bytes
[0] = 0xc4;
3468 i
.vex
.bytes
[0] = 0x8f;
3472 i
.vex
.bytes
[0] = 0x8f;
3476 i
.vex
.bytes
[0] = 0x8f;
3482 /* The high 3 bits of the second VEX byte are 1's compliment
3483 of RXB bits from REX. */
3484 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3486 /* Check the REX.W bit. */
3487 w
= (i
.rex
& REX_W
) ? 1 : 0;
3488 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
3491 i
.vex
.bytes
[2] = (w
<< 7
3492 | register_specifier
<< 3
3493 | vector_length
<< 2
3498 static INLINE bfd_boolean
3499 is_evex_encoding (const insn_template
*t
)
3501 return t
->opcode_modifier
.evex
|| t
->opcode_modifier
.disp8memshift
3502 || t
->opcode_modifier
.broadcast
|| t
->opcode_modifier
.masking
3503 || t
->opcode_modifier
.staticrounding
|| t
->opcode_modifier
.sae
;
3506 static INLINE bfd_boolean
3507 is_any_vex_encoding (const insn_template
*t
)
3509 return t
->opcode_modifier
.vex
|| t
->opcode_modifier
.vexopcode
3510 || is_evex_encoding (t
);
3513 /* Build the EVEX prefix. */
3516 build_evex_prefix (void)
3518 unsigned int register_specifier
;
3519 unsigned int implied_prefix
;
3521 rex_byte vrex_used
= 0;
3523 /* Check register specifier. */
3524 if (i
.vex
.register_specifier
)
3526 gas_assert ((i
.vrex
& REX_X
) == 0);
3528 register_specifier
= i
.vex
.register_specifier
->reg_num
;
3529 if ((i
.vex
.register_specifier
->reg_flags
& RegRex
))
3530 register_specifier
+= 8;
3531 /* The upper 16 registers are encoded in the fourth byte of the
3533 if (!(i
.vex
.register_specifier
->reg_flags
& RegVRex
))
3534 i
.vex
.bytes
[3] = 0x8;
3535 register_specifier
= ~register_specifier
& 0xf;
3539 register_specifier
= 0xf;
3541 /* Encode upper 16 vector index register in the fourth byte of
3543 if (!(i
.vrex
& REX_X
))
3544 i
.vex
.bytes
[3] = 0x8;
3549 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3554 case DATA_PREFIX_OPCODE
:
3557 case REPE_PREFIX_OPCODE
:
3560 case REPNE_PREFIX_OPCODE
:
3567 /* 4 byte EVEX prefix. */
3569 i
.vex
.bytes
[0] = 0x62;
3572 switch (i
.tm
.opcode_modifier
.vexopcode
)
3588 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3590 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3592 /* The fifth bit of the second EVEX byte is 1's compliment of the
3593 REX_R bit in VREX. */
3594 if (!(i
.vrex
& REX_R
))
3595 i
.vex
.bytes
[1] |= 0x10;
3599 if ((i
.reg_operands
+ i
.imm_operands
) == i
.operands
)
3601 /* When all operands are registers, the REX_X bit in REX is not
3602 used. We reuse it to encode the upper 16 registers, which is
3603 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3604 as 1's compliment. */
3605 if ((i
.vrex
& REX_B
))
3608 i
.vex
.bytes
[1] &= ~0x40;
3612 /* EVEX instructions shouldn't need the REX prefix. */
3613 i
.vrex
&= ~vrex_used
;
3614 gas_assert (i
.vrex
== 0);
3616 /* Check the REX.W bit. */
3617 w
= (i
.rex
& REX_W
) ? 1 : 0;
3618 if (i
.tm
.opcode_modifier
.vexw
)
3620 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
3623 /* If w is not set it means we are dealing with WIG instruction. */
3626 if (evexwig
== evexw1
)
3630 /* Encode the U bit. */
3631 implied_prefix
|= 0x4;
3633 /* The third byte of the EVEX prefix. */
3634 i
.vex
.bytes
[2] = (w
<< 7 | register_specifier
<< 3 | implied_prefix
);
3636 /* The fourth byte of the EVEX prefix. */
3637 /* The zeroing-masking bit. */
3638 if (i
.mask
&& i
.mask
->zeroing
)
3639 i
.vex
.bytes
[3] |= 0x80;
3641 /* Don't always set the broadcast bit if there is no RC. */
3644 /* Encode the vector length. */
3645 unsigned int vec_length
;
3647 if (!i
.tm
.opcode_modifier
.evex
3648 || i
.tm
.opcode_modifier
.evex
== EVEXDYN
)
3652 /* Determine vector length from the last multi-length vector
3655 for (op
= i
.operands
; op
--;)
3656 if (i
.tm
.operand_types
[op
].bitfield
.xmmword
3657 + i
.tm
.operand_types
[op
].bitfield
.ymmword
3658 + i
.tm
.operand_types
[op
].bitfield
.zmmword
> 1)
3660 if (i
.types
[op
].bitfield
.zmmword
)
3662 i
.tm
.opcode_modifier
.evex
= EVEX512
;
3665 else if (i
.types
[op
].bitfield
.ymmword
)
3667 i
.tm
.opcode_modifier
.evex
= EVEX256
;
3670 else if (i
.types
[op
].bitfield
.xmmword
)
3672 i
.tm
.opcode_modifier
.evex
= EVEX128
;
3675 else if (i
.broadcast
&& (int) op
== i
.broadcast
->operand
)
3677 switch (i
.broadcast
->bytes
)
3680 i
.tm
.opcode_modifier
.evex
= EVEX512
;
3683 i
.tm
.opcode_modifier
.evex
= EVEX256
;
3686 i
.tm
.opcode_modifier
.evex
= EVEX128
;
3695 if (op
>= MAX_OPERANDS
)
3699 switch (i
.tm
.opcode_modifier
.evex
)
3701 case EVEXLIG
: /* LL' is ignored */
3702 vec_length
= evexlig
<< 5;
3705 vec_length
= 0 << 5;
3708 vec_length
= 1 << 5;
3711 vec_length
= 2 << 5;
3717 i
.vex
.bytes
[3] |= vec_length
;
3718 /* Encode the broadcast bit. */
3720 i
.vex
.bytes
[3] |= 0x10;
3724 if (i
.rounding
->type
!= saeonly
)
3725 i
.vex
.bytes
[3] |= 0x10 | (i
.rounding
->type
<< 5);
3727 i
.vex
.bytes
[3] |= 0x10 | (evexrcig
<< 5);
3730 if (i
.mask
&& i
.mask
->mask
)
3731 i
.vex
.bytes
[3] |= i
.mask
->mask
->reg_num
;
3735 process_immext (void)
3739 if ((i
.tm
.cpu_flags
.bitfield
.cpusse3
|| i
.tm
.cpu_flags
.bitfield
.cpusvme
)
3742 /* MONITOR/MWAIT as well as SVME instructions have fixed operands
3743 with an opcode suffix which is coded in the same place as an
3744 8-bit immediate field would be.
3745 Here we check those operands and remove them afterwards. */
3748 for (x
= 0; x
< i
.operands
; x
++)
3749 if (register_number (i
.op
[x
].regs
) != x
)
3750 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3751 register_prefix
, i
.op
[x
].regs
->reg_name
, x
+ 1,
3757 if (i
.tm
.cpu_flags
.bitfield
.cpumwaitx
&& i
.operands
> 0)
3759 /* MONITORX/MWAITX instructions have fixed operands with an opcode
3760 suffix which is coded in the same place as an 8-bit immediate
3762 Here we check those operands and remove them afterwards. */
3765 if (i
.operands
!= 3)
3768 for (x
= 0; x
< 2; x
++)
3769 if (register_number (i
.op
[x
].regs
) != x
)
3770 goto bad_register_operand
;
3772 /* Check for third operand for mwaitx/monitorx insn. */
3773 if (register_number (i
.op
[x
].regs
)
3774 != (x
+ (i
.tm
.extension_opcode
== 0xfb)))
3776 bad_register_operand
:
3777 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3778 register_prefix
, i
.op
[x
].regs
->reg_name
, x
+1,
3785 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
3786 which is coded in the same place as an 8-bit immediate field
3787 would be. Here we fake an 8-bit immediate operand from the
3788 opcode suffix stored in tm.extension_opcode.
3790 AVX instructions also use this encoding, for some of
3791 3 argument instructions. */
3793 gas_assert (i
.imm_operands
<= 1
3795 || (is_any_vex_encoding (&i
.tm
)
3796 && i
.operands
<= 4)));
3798 exp
= &im_expressions
[i
.imm_operands
++];
3799 i
.op
[i
.operands
].imms
= exp
;
3800 i
.types
[i
.operands
] = imm8
;
3802 exp
->X_op
= O_constant
;
3803 exp
->X_add_number
= i
.tm
.extension_opcode
;
3804 i
.tm
.extension_opcode
= None
;
3811 switch (i
.tm
.opcode_modifier
.hleprefixok
)
3816 as_bad (_("invalid instruction `%s' after `%s'"),
3817 i
.tm
.name
, i
.hle_prefix
);
3820 if (i
.prefix
[LOCK_PREFIX
])
3822 as_bad (_("missing `lock' with `%s'"), i
.hle_prefix
);
3826 case HLEPrefixRelease
:
3827 if (i
.prefix
[HLE_PREFIX
] != XRELEASE_PREFIX_OPCODE
)
3829 as_bad (_("instruction `%s' after `xacquire' not allowed"),
3833 if (i
.mem_operands
== 0
3834 || !operand_type_check (i
.types
[i
.operands
- 1], anymem
))
3836 as_bad (_("memory destination needed for instruction `%s'"
3837 " after `xrelease'"), i
.tm
.name
);
3844 /* Try the shortest encoding by shortening operand size. */
3847 optimize_encoding (void)
3851 if (optimize_for_space
3852 && i
.reg_operands
== 1
3853 && i
.imm_operands
== 1
3854 && !i
.types
[1].bitfield
.byte
3855 && i
.op
[0].imms
->X_op
== O_constant
3856 && fits_in_imm7 (i
.op
[0].imms
->X_add_number
)
3857 && ((i
.tm
.base_opcode
== 0xa8
3858 && i
.tm
.extension_opcode
== None
)
3859 || (i
.tm
.base_opcode
== 0xf6
3860 && i
.tm
.extension_opcode
== 0x0)))
3863 test $imm7, %r64/%r32/%r16 -> test $imm7, %r8
3865 unsigned int base_regnum
= i
.op
[1].regs
->reg_num
;
3866 if (flag_code
== CODE_64BIT
|| base_regnum
< 4)
3868 i
.types
[1].bitfield
.byte
= 1;
3869 /* Ignore the suffix. */
3871 if (base_regnum
>= 4
3872 && !(i
.op
[1].regs
->reg_flags
& RegRex
))
3874 /* Handle SP, BP, SI and DI registers. */
3875 if (i
.types
[1].bitfield
.word
)
3877 else if (i
.types
[1].bitfield
.dword
)
3885 else if (flag_code
== CODE_64BIT
3886 && ((i
.types
[1].bitfield
.qword
3887 && i
.reg_operands
== 1
3888 && i
.imm_operands
== 1
3889 && i
.op
[0].imms
->X_op
== O_constant
3890 && ((i
.tm
.base_opcode
== 0xb0
3891 && i
.tm
.extension_opcode
== None
3892 && fits_in_unsigned_long (i
.op
[0].imms
->X_add_number
))
3893 || (fits_in_imm31 (i
.op
[0].imms
->X_add_number
)
3894 && (((i
.tm
.base_opcode
== 0x24
3895 || i
.tm
.base_opcode
== 0xa8)
3896 && i
.tm
.extension_opcode
== None
)
3897 || (i
.tm
.base_opcode
== 0x80
3898 && i
.tm
.extension_opcode
== 0x4)
3899 || ((i
.tm
.base_opcode
== 0xf6
3900 || i
.tm
.base_opcode
== 0xc6)
3901 && i
.tm
.extension_opcode
== 0x0)))))
3902 || (i
.types
[0].bitfield
.qword
3903 && ((i
.reg_operands
== 2
3904 && i
.op
[0].regs
== i
.op
[1].regs
3905 && ((i
.tm
.base_opcode
== 0x30
3906 || i
.tm
.base_opcode
== 0x28)
3907 && i
.tm
.extension_opcode
== None
))
3908 || (i
.reg_operands
== 1
3910 && i
.tm
.base_opcode
== 0x30
3911 && i
.tm
.extension_opcode
== None
)))))
3914 andq $imm31, %r64 -> andl $imm31, %r32
3915 testq $imm31, %r64 -> testl $imm31, %r32
3916 xorq %r64, %r64 -> xorl %r32, %r32
3917 subq %r64, %r64 -> subl %r32, %r32
3918 movq $imm31, %r64 -> movl $imm31, %r32
3919 movq $imm32, %r64 -> movl $imm32, %r32
3921 i
.tm
.opcode_modifier
.norex64
= 1;
3922 if (i
.tm
.base_opcode
== 0xb0 || i
.tm
.base_opcode
== 0xc6)
3925 movq $imm31, %r64 -> movl $imm31, %r32
3926 movq $imm32, %r64 -> movl $imm32, %r32
3928 i
.tm
.operand_types
[0].bitfield
.imm32
= 1;
3929 i
.tm
.operand_types
[0].bitfield
.imm32s
= 0;
3930 i
.tm
.operand_types
[0].bitfield
.imm64
= 0;
3931 i
.types
[0].bitfield
.imm32
= 1;
3932 i
.types
[0].bitfield
.imm32s
= 0;
3933 i
.types
[0].bitfield
.imm64
= 0;
3934 i
.types
[1].bitfield
.dword
= 1;
3935 i
.types
[1].bitfield
.qword
= 0;
3936 if (i
.tm
.base_opcode
== 0xc6)
3939 movq $imm31, %r64 -> movl $imm31, %r32
3941 i
.tm
.base_opcode
= 0xb0;
3942 i
.tm
.extension_opcode
= None
;
3943 i
.tm
.opcode_modifier
.shortform
= 1;
3944 i
.tm
.opcode_modifier
.modrm
= 0;
3948 else if (optimize
> 1
3949 && i
.reg_operands
== 3
3950 && i
.op
[0].regs
== i
.op
[1].regs
3951 && !i
.types
[2].bitfield
.xmmword
3952 && (i
.tm
.opcode_modifier
.vex
3953 || ((!i
.mask
|| i
.mask
->zeroing
)
3955 && is_evex_encoding (&i
.tm
)
3956 && (i
.vec_encoding
!= vex_encoding_evex
3957 || i
.tm
.cpu_flags
.bitfield
.cpuavx512vl
3958 || (i
.tm
.operand_types
[2].bitfield
.zmmword
3959 && i
.types
[2].bitfield
.ymmword
)
3960 || cpu_arch_isa_flags
.bitfield
.cpuavx512vl
)))
3961 && ((i
.tm
.base_opcode
== 0x55
3962 || i
.tm
.base_opcode
== 0x6655
3963 || i
.tm
.base_opcode
== 0x66df
3964 || i
.tm
.base_opcode
== 0x57
3965 || i
.tm
.base_opcode
== 0x6657
3966 || i
.tm
.base_opcode
== 0x66ef
3967 || i
.tm
.base_opcode
== 0x66f8
3968 || i
.tm
.base_opcode
== 0x66f9
3969 || i
.tm
.base_opcode
== 0x66fa
3970 || i
.tm
.base_opcode
== 0x66fb
3971 || i
.tm
.base_opcode
== 0x42
3972 || i
.tm
.base_opcode
== 0x6642
3973 || i
.tm
.base_opcode
== 0x47
3974 || i
.tm
.base_opcode
== 0x6647)
3975 && i
.tm
.extension_opcode
== None
))
3978 VOP, one of vandnps, vandnpd, vxorps, vxorpd, vpsubb, vpsubd,
3980 EVEX VOP %zmmM, %zmmM, %zmmN
3981 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
3982 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3983 EVEX VOP %ymmM, %ymmM, %ymmN
3984 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
3985 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3986 VEX VOP %ymmM, %ymmM, %ymmN
3987 -> VEX VOP %xmmM, %xmmM, %xmmN
3988 VOP, one of vpandn and vpxor:
3989 VEX VOP %ymmM, %ymmM, %ymmN
3990 -> VEX VOP %xmmM, %xmmM, %xmmN
3991 VOP, one of vpandnd and vpandnq:
3992 EVEX VOP %zmmM, %zmmM, %zmmN
3993 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
3994 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3995 EVEX VOP %ymmM, %ymmM, %ymmN
3996 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
3997 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3998 VOP, one of vpxord and vpxorq:
3999 EVEX VOP %zmmM, %zmmM, %zmmN
4000 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
4001 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
4002 EVEX VOP %ymmM, %ymmM, %ymmN
4003 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
4004 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
4005 VOP, one of kxord and kxorq:
4006 VEX VOP %kM, %kM, %kN
4007 -> VEX kxorw %kM, %kM, %kN
4008 VOP, one of kandnd and kandnq:
4009 VEX VOP %kM, %kM, %kN
4010 -> VEX kandnw %kM, %kM, %kN
4012 if (is_evex_encoding (&i
.tm
))
4014 if (i
.vec_encoding
== vex_encoding_evex
)
4015 i
.tm
.opcode_modifier
.evex
= EVEX128
;
4018 i
.tm
.opcode_modifier
.vex
= VEX128
;
4019 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4020 i
.tm
.opcode_modifier
.evex
= 0;
4023 else if (i
.tm
.operand_types
[0].bitfield
.regmask
)
4025 i
.tm
.base_opcode
&= 0xff;
4026 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4029 i
.tm
.opcode_modifier
.vex
= VEX128
;
4031 if (i
.tm
.opcode_modifier
.vex
)
4032 for (j
= 0; j
< 3; j
++)
4034 i
.types
[j
].bitfield
.xmmword
= 1;
4035 i
.types
[j
].bitfield
.ymmword
= 0;
4040 /* This is the guts of the machine-dependent assembler. LINE points to a
4041 machine dependent instruction. This function is supposed to emit
4042 the frags/bytes it assembles to. */
4045 md_assemble (char *line
)
4048 char mnemonic
[MAX_MNEM_SIZE
], mnem_suffix
;
4049 const insn_template
*t
;
4051 /* Initialize globals. */
4052 memset (&i
, '\0', sizeof (i
));
4053 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4054 i
.reloc
[j
] = NO_RELOC
;
4055 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
4056 memset (im_expressions
, '\0', sizeof (im_expressions
));
4057 save_stack_p
= save_stack
;
4059 /* First parse an instruction mnemonic & call i386_operand for the operands.
4060 We assume that the scrubber has arranged it so that line[0] is the valid
4061 start of a (possibly prefixed) mnemonic. */
4063 line
= parse_insn (line
, mnemonic
);
4066 mnem_suffix
= i
.suffix
;
4068 line
= parse_operands (line
, mnemonic
);
4070 xfree (i
.memop1_string
);
4071 i
.memop1_string
= NULL
;
4075 /* Now we've parsed the mnemonic into a set of templates, and have the
4076 operands at hand. */
4078 /* All intel opcodes have reversed operands except for "bound" and
4079 "enter". We also don't reverse intersegment "jmp" and "call"
4080 instructions with 2 immediate operands so that the immediate segment
4081 precedes the offset, as it does when in AT&T mode. */
4084 && (strcmp (mnemonic
, "bound") != 0)
4085 && (strcmp (mnemonic
, "invlpga") != 0)
4086 && !(operand_type_check (i
.types
[0], imm
)
4087 && operand_type_check (i
.types
[1], imm
)))
4090 /* The order of the immediates should be reversed
4091 for 2 immediates extrq and insertq instructions */
4092 if (i
.imm_operands
== 2
4093 && (strcmp (mnemonic
, "extrq") == 0
4094 || strcmp (mnemonic
, "insertq") == 0))
4095 swap_2_operands (0, 1);
4100 /* Don't optimize displacement for movabs since it only takes 64bit
4103 && i
.disp_encoding
!= disp_encoding_32bit
4104 && (flag_code
!= CODE_64BIT
4105 || strcmp (mnemonic
, "movabs") != 0))
4108 /* Next, we find a template that matches the given insn,
4109 making sure the overlap of the given operands types is consistent
4110 with the template operand types. */
4112 if (!(t
= match_template (mnem_suffix
)))
4115 if (sse_check
!= check_none
4116 && !i
.tm
.opcode_modifier
.noavx
4117 && !i
.tm
.cpu_flags
.bitfield
.cpuavx
4118 && (i
.tm
.cpu_flags
.bitfield
.cpusse
4119 || i
.tm
.cpu_flags
.bitfield
.cpusse2
4120 || i
.tm
.cpu_flags
.bitfield
.cpusse3
4121 || i
.tm
.cpu_flags
.bitfield
.cpussse3
4122 || i
.tm
.cpu_flags
.bitfield
.cpusse4_1
4123 || i
.tm
.cpu_flags
.bitfield
.cpusse4_2
4124 || i
.tm
.cpu_flags
.bitfield
.cpupclmul
4125 || i
.tm
.cpu_flags
.bitfield
.cpuaes
4126 || i
.tm
.cpu_flags
.bitfield
.cpugfni
))
4128 (sse_check
== check_warning
4130 : as_bad
) (_("SSE instruction `%s' is used"), i
.tm
.name
);
4133 /* Zap movzx and movsx suffix. The suffix has been set from
4134 "word ptr" or "byte ptr" on the source operand in Intel syntax
4135 or extracted from mnemonic in AT&T syntax. But we'll use
4136 the destination register to choose the suffix for encoding. */
4137 if ((i
.tm
.base_opcode
& ~9) == 0x0fb6)
4139 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
4140 there is no suffix, the default will be byte extension. */
4141 if (i
.reg_operands
!= 2
4144 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
4149 if (i
.tm
.opcode_modifier
.fwait
)
4150 if (!add_prefix (FWAIT_OPCODE
))
4153 /* Check if REP prefix is OK. */
4154 if (i
.rep_prefix
&& !i
.tm
.opcode_modifier
.repprefixok
)
4156 as_bad (_("invalid instruction `%s' after `%s'"),
4157 i
.tm
.name
, i
.rep_prefix
);
4161 /* Check for lock without a lockable instruction. Destination operand
4162 must be memory unless it is xchg (0x86). */
4163 if (i
.prefix
[LOCK_PREFIX
]
4164 && (!i
.tm
.opcode_modifier
.islockable
4165 || i
.mem_operands
== 0
4166 || (i
.tm
.base_opcode
!= 0x86
4167 && !operand_type_check (i
.types
[i
.operands
- 1], anymem
))))
4169 as_bad (_("expecting lockable instruction after `lock'"));
4173 /* Check for data size prefix on VEX/XOP/EVEX encoded insns. */
4174 if (i
.prefix
[DATA_PREFIX
] && is_any_vex_encoding (&i
.tm
))
4176 as_bad (_("data size prefix invalid with `%s'"), i
.tm
.name
);
4180 /* Check if HLE prefix is OK. */
4181 if (i
.hle_prefix
&& !check_hle ())
4184 /* Check BND prefix. */
4185 if (i
.bnd_prefix
&& !i
.tm
.opcode_modifier
.bndprefixok
)
4186 as_bad (_("expecting valid branch instruction after `bnd'"));
4188 /* Check NOTRACK prefix. */
4189 if (i
.notrack_prefix
&& !i
.tm
.opcode_modifier
.notrackprefixok
)
4190 as_bad (_("expecting indirect branch instruction after `notrack'"));
4192 if (i
.tm
.cpu_flags
.bitfield
.cpumpx
)
4194 if (flag_code
== CODE_64BIT
&& i
.prefix
[ADDR_PREFIX
])
4195 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
4196 else if (flag_code
!= CODE_16BIT
4197 ? i
.prefix
[ADDR_PREFIX
]
4198 : i
.mem_operands
&& !i
.prefix
[ADDR_PREFIX
])
4199 as_bad (_("16-bit address isn't allowed in MPX instructions"));
4202 /* Insert BND prefix. */
4203 if (add_bnd_prefix
&& i
.tm
.opcode_modifier
.bndprefixok
)
4205 if (!i
.prefix
[BND_PREFIX
])
4206 add_prefix (BND_PREFIX_OPCODE
);
4207 else if (i
.prefix
[BND_PREFIX
] != BND_PREFIX_OPCODE
)
4209 as_warn (_("replacing `rep'/`repe' prefix by `bnd'"));
4210 i
.prefix
[BND_PREFIX
] = BND_PREFIX_OPCODE
;
4214 /* Check string instruction segment overrides. */
4215 if (i
.tm
.opcode_modifier
.isstring
&& i
.mem_operands
!= 0)
4217 if (!check_string ())
4219 i
.disp_operands
= 0;
4222 if (optimize
&& !i
.no_optimize
&& i
.tm
.opcode_modifier
.optimize
)
4223 optimize_encoding ();
4225 if (!process_suffix ())
4228 /* Update operand types. */
4229 for (j
= 0; j
< i
.operands
; j
++)
4230 i
.types
[j
] = operand_type_and (i
.types
[j
], i
.tm
.operand_types
[j
]);
4232 /* Make still unresolved immediate matches conform to size of immediate
4233 given in i.suffix. */
4234 if (!finalize_imm ())
4237 if (i
.types
[0].bitfield
.imm1
)
4238 i
.imm_operands
= 0; /* kludge for shift insns. */
4240 /* We only need to check those implicit registers for instructions
4241 with 3 operands or less. */
4242 if (i
.operands
<= 3)
4243 for (j
= 0; j
< i
.operands
; j
++)
4244 if (i
.types
[j
].bitfield
.inoutportreg
4245 || i
.types
[j
].bitfield
.shiftcount
4246 || (i
.types
[j
].bitfield
.acc
&& !i
.types
[j
].bitfield
.xmmword
))
4249 /* ImmExt should be processed after SSE2AVX. */
4250 if (!i
.tm
.opcode_modifier
.sse2avx
4251 && i
.tm
.opcode_modifier
.immext
)
4254 /* For insns with operands there are more diddles to do to the opcode. */
4257 if (!process_operands ())
4260 else if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
4262 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
4263 as_warn (_("translating to `%sp'"), i
.tm
.name
);
4266 if (is_any_vex_encoding (&i
.tm
))
4268 if (flag_code
== CODE_16BIT
)
4270 as_bad (_("instruction `%s' isn't supported in 16-bit mode."),
4275 if (i
.tm
.opcode_modifier
.vex
)
4276 build_vex_prefix (t
);
4278 build_evex_prefix ();
4281 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
4282 instructions may define INT_OPCODE as well, so avoid this corner
4283 case for those instructions that use MODRM. */
4284 if (i
.tm
.base_opcode
== INT_OPCODE
4285 && !i
.tm
.opcode_modifier
.modrm
4286 && i
.op
[0].imms
->X_add_number
== 3)
4288 i
.tm
.base_opcode
= INT3_OPCODE
;
4292 if ((i
.tm
.opcode_modifier
.jump
4293 || i
.tm
.opcode_modifier
.jumpbyte
4294 || i
.tm
.opcode_modifier
.jumpdword
)
4295 && i
.op
[0].disps
->X_op
== O_constant
)
4297 /* Convert "jmp constant" (and "call constant") to a jump (call) to
4298 the absolute address given by the constant. Since ix86 jumps and
4299 calls are pc relative, we need to generate a reloc. */
4300 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
4301 i
.op
[0].disps
->X_op
= O_symbol
;
4304 if (i
.tm
.opcode_modifier
.rex64
)
4307 /* For 8 bit registers we need an empty rex prefix. Also if the
4308 instruction already has a prefix, we need to convert old
4309 registers to new ones. */
4311 if ((i
.types
[0].bitfield
.reg
&& i
.types
[0].bitfield
.byte
4312 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
4313 || (i
.types
[1].bitfield
.reg
&& i
.types
[1].bitfield
.byte
4314 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
4315 || (((i
.types
[0].bitfield
.reg
&& i
.types
[0].bitfield
.byte
)
4316 || (i
.types
[1].bitfield
.reg
&& i
.types
[1].bitfield
.byte
))
4321 i
.rex
|= REX_OPCODE
;
4322 for (x
= 0; x
< 2; x
++)
4324 /* Look for 8 bit operand that uses old registers. */
4325 if (i
.types
[x
].bitfield
.reg
&& i
.types
[x
].bitfield
.byte
4326 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
4328 /* In case it is "hi" register, give up. */
4329 if (i
.op
[x
].regs
->reg_num
> 3)
4330 as_bad (_("can't encode register '%s%s' in an "
4331 "instruction requiring REX prefix."),
4332 register_prefix
, i
.op
[x
].regs
->reg_name
);
4334 /* Otherwise it is equivalent to the extended register.
4335 Since the encoding doesn't change this is merely
4336 cosmetic cleanup for debug output. */
4338 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
4343 if (i
.rex
== 0 && i
.rex_encoding
)
4345 /* Check if we can add a REX_OPCODE byte. Look for 8 bit operand
4346 that uses legacy register. If it is "hi" register, don't add
4347 the REX_OPCODE byte. */
4349 for (x
= 0; x
< 2; x
++)
4350 if (i
.types
[x
].bitfield
.reg
4351 && i
.types
[x
].bitfield
.byte
4352 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0
4353 && i
.op
[x
].regs
->reg_num
> 3)
4355 i
.rex_encoding
= FALSE
;
4364 add_prefix (REX_OPCODE
| i
.rex
);
4366 /* We are ready to output the insn. */
4371 parse_insn (char *line
, char *mnemonic
)
4374 char *token_start
= l
;
4377 const insn_template
*t
;
4383 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
4388 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
4390 as_bad (_("no such instruction: `%s'"), token_start
);
4395 if (!is_space_char (*l
)
4396 && *l
!= END_OF_INSN
4398 || (*l
!= PREFIX_SEPARATOR
4401 as_bad (_("invalid character %s in mnemonic"),
4402 output_invalid (*l
));
4405 if (token_start
== l
)
4407 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
4408 as_bad (_("expecting prefix; got nothing"));
4410 as_bad (_("expecting mnemonic; got nothing"));
4414 /* Look up instruction (or prefix) via hash table. */
4415 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
4417 if (*l
!= END_OF_INSN
4418 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
4419 && current_templates
4420 && current_templates
->start
->opcode_modifier
.isprefix
)
4422 if (!cpu_flags_check_cpu64 (current_templates
->start
->cpu_flags
))
4424 as_bad ((flag_code
!= CODE_64BIT
4425 ? _("`%s' is only supported in 64-bit mode")
4426 : _("`%s' is not supported in 64-bit mode")),
4427 current_templates
->start
->name
);
4430 /* If we are in 16-bit mode, do not allow addr16 or data16.
4431 Similarly, in 32-bit mode, do not allow addr32 or data32. */
4432 if ((current_templates
->start
->opcode_modifier
.size16
4433 || current_templates
->start
->opcode_modifier
.size32
)
4434 && flag_code
!= CODE_64BIT
4435 && (current_templates
->start
->opcode_modifier
.size32
4436 ^ (flag_code
== CODE_16BIT
)))
4438 as_bad (_("redundant %s prefix"),
4439 current_templates
->start
->name
);
4442 if (current_templates
->start
->opcode_length
== 0)
4444 /* Handle pseudo prefixes. */
4445 switch (current_templates
->start
->base_opcode
)
4449 i
.disp_encoding
= disp_encoding_8bit
;
4453 i
.disp_encoding
= disp_encoding_32bit
;
4457 i
.dir_encoding
= dir_encoding_load
;
4461 i
.dir_encoding
= dir_encoding_store
;
4465 i
.vec_encoding
= vex_encoding_vex2
;
4469 i
.vec_encoding
= vex_encoding_vex3
;
4473 i
.vec_encoding
= vex_encoding_evex
;
4477 i
.rex_encoding
= TRUE
;
4481 i
.no_optimize
= TRUE
;
4489 /* Add prefix, checking for repeated prefixes. */
4490 switch (add_prefix (current_templates
->start
->base_opcode
))
4495 if (current_templates
->start
->cpu_flags
.bitfield
.cpuibt
)
4496 i
.notrack_prefix
= current_templates
->start
->name
;
4499 if (current_templates
->start
->cpu_flags
.bitfield
.cpuhle
)
4500 i
.hle_prefix
= current_templates
->start
->name
;
4501 else if (current_templates
->start
->cpu_flags
.bitfield
.cpumpx
)
4502 i
.bnd_prefix
= current_templates
->start
->name
;
4504 i
.rep_prefix
= current_templates
->start
->name
;
4510 /* Skip past PREFIX_SEPARATOR and reset token_start. */
4517 if (!current_templates
)
4519 /* Check if we should swap operand or force 32bit displacement in
4521 if (mnem_p
- 2 == dot_p
&& dot_p
[1] == 's')
4522 i
.dir_encoding
= dir_encoding_store
;
4523 else if (mnem_p
- 3 == dot_p
4526 i
.disp_encoding
= disp_encoding_8bit
;
4527 else if (mnem_p
- 4 == dot_p
4531 i
.disp_encoding
= disp_encoding_32bit
;
4536 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
4539 if (!current_templates
)
4542 /* See if we can get a match by trimming off a suffix. */
4545 case WORD_MNEM_SUFFIX
:
4546 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
4547 i
.suffix
= SHORT_MNEM_SUFFIX
;
4550 case BYTE_MNEM_SUFFIX
:
4551 case QWORD_MNEM_SUFFIX
:
4552 i
.suffix
= mnem_p
[-1];
4554 current_templates
= (const templates
*) hash_find (op_hash
,
4557 case SHORT_MNEM_SUFFIX
:
4558 case LONG_MNEM_SUFFIX
:
4561 i
.suffix
= mnem_p
[-1];
4563 current_templates
= (const templates
*) hash_find (op_hash
,
4572 if (intel_float_operand (mnemonic
) == 1)
4573 i
.suffix
= SHORT_MNEM_SUFFIX
;
4575 i
.suffix
= LONG_MNEM_SUFFIX
;
4577 current_templates
= (const templates
*) hash_find (op_hash
,
4582 if (!current_templates
)
4584 as_bad (_("no such instruction: `%s'"), token_start
);
4589 if (current_templates
->start
->opcode_modifier
.jump
4590 || current_templates
->start
->opcode_modifier
.jumpbyte
)
4592 /* Check for a branch hint. We allow ",pt" and ",pn" for
4593 predict taken and predict not taken respectively.
4594 I'm not sure that branch hints actually do anything on loop
4595 and jcxz insns (JumpByte) for current Pentium4 chips. They
4596 may work in the future and it doesn't hurt to accept them
4598 if (l
[0] == ',' && l
[1] == 'p')
4602 if (!add_prefix (DS_PREFIX_OPCODE
))
4606 else if (l
[2] == 'n')
4608 if (!add_prefix (CS_PREFIX_OPCODE
))
4614 /* Any other comma loses. */
4617 as_bad (_("invalid character %s in mnemonic"),
4618 output_invalid (*l
));
4622 /* Check if instruction is supported on specified architecture. */
4624 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
4626 supported
|= cpu_flags_match (t
);
4627 if (supported
== CPU_FLAGS_PERFECT_MATCH
)
4629 if (!cpu_arch_flags
.bitfield
.cpui386
&& (flag_code
!= CODE_16BIT
))
4630 as_warn (_("use .code16 to ensure correct addressing mode"));
4636 if (!(supported
& CPU_FLAGS_64BIT_MATCH
))
4637 as_bad (flag_code
== CODE_64BIT
4638 ? _("`%s' is not supported in 64-bit mode")
4639 : _("`%s' is only supported in 64-bit mode"),
4640 current_templates
->start
->name
);
4642 as_bad (_("`%s' is not supported on `%s%s'"),
4643 current_templates
->start
->name
,
4644 cpu_arch_name
? cpu_arch_name
: default_arch
,
4645 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
4651 parse_operands (char *l
, const char *mnemonic
)
4655 /* 1 if operand is pending after ','. */
4656 unsigned int expecting_operand
= 0;
4658 /* Non-zero if operand parens not balanced. */
4659 unsigned int paren_not_balanced
;
4661 while (*l
!= END_OF_INSN
)
4663 /* Skip optional white space before operand. */
4664 if (is_space_char (*l
))
4666 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
&& *l
!= '"')
4668 as_bad (_("invalid character %s before operand %d"),
4669 output_invalid (*l
),
4673 token_start
= l
; /* After white space. */
4674 paren_not_balanced
= 0;
4675 while (paren_not_balanced
|| *l
!= ',')
4677 if (*l
== END_OF_INSN
)
4679 if (paren_not_balanced
)
4682 as_bad (_("unbalanced parenthesis in operand %d."),
4685 as_bad (_("unbalanced brackets in operand %d."),
4690 break; /* we are done */
4692 else if (!is_operand_char (*l
) && !is_space_char (*l
) && *l
!= '"')
4694 as_bad (_("invalid character %s in operand %d"),
4695 output_invalid (*l
),
4702 ++paren_not_balanced
;
4704 --paren_not_balanced
;
4709 ++paren_not_balanced
;
4711 --paren_not_balanced
;
4715 if (l
!= token_start
)
4716 { /* Yes, we've read in another operand. */
4717 unsigned int operand_ok
;
4718 this_operand
= i
.operands
++;
4719 if (i
.operands
> MAX_OPERANDS
)
4721 as_bad (_("spurious operands; (%d operands/instruction max)"),
4725 i
.types
[this_operand
].bitfield
.unspecified
= 1;
4726 /* Now parse operand adding info to 'i' as we go along. */
4727 END_STRING_AND_SAVE (l
);
4729 if (i
.mem_operands
> 1)
4731 as_bad (_("too many memory references for `%s'"),
4738 i386_intel_operand (token_start
,
4739 intel_float_operand (mnemonic
));
4741 operand_ok
= i386_att_operand (token_start
);
4743 RESTORE_END_STRING (l
);
4749 if (expecting_operand
)
4751 expecting_operand_after_comma
:
4752 as_bad (_("expecting operand after ','; got nothing"));
4757 as_bad (_("expecting operand before ','; got nothing"));
4762 /* Now *l must be either ',' or END_OF_INSN. */
4765 if (*++l
== END_OF_INSN
)
4767 /* Just skip it, if it's \n complain. */
4768 goto expecting_operand_after_comma
;
4770 expecting_operand
= 1;
4777 swap_2_operands (int xchg1
, int xchg2
)
4779 union i386_op temp_op
;
4780 i386_operand_type temp_type
;
4781 unsigned int temp_flags
;
4782 enum bfd_reloc_code_real temp_reloc
;
4784 temp_type
= i
.types
[xchg2
];
4785 i
.types
[xchg2
] = i
.types
[xchg1
];
4786 i
.types
[xchg1
] = temp_type
;
4788 temp_flags
= i
.flags
[xchg2
];
4789 i
.flags
[xchg2
] = i
.flags
[xchg1
];
4790 i
.flags
[xchg1
] = temp_flags
;
4792 temp_op
= i
.op
[xchg2
];
4793 i
.op
[xchg2
] = i
.op
[xchg1
];
4794 i
.op
[xchg1
] = temp_op
;
4796 temp_reloc
= i
.reloc
[xchg2
];
4797 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
4798 i
.reloc
[xchg1
] = temp_reloc
;
4802 if (i
.mask
->operand
== xchg1
)
4803 i
.mask
->operand
= xchg2
;
4804 else if (i
.mask
->operand
== xchg2
)
4805 i
.mask
->operand
= xchg1
;
4809 if (i
.broadcast
->operand
== xchg1
)
4810 i
.broadcast
->operand
= xchg2
;
4811 else if (i
.broadcast
->operand
== xchg2
)
4812 i
.broadcast
->operand
= xchg1
;
4816 if (i
.rounding
->operand
== xchg1
)
4817 i
.rounding
->operand
= xchg2
;
4818 else if (i
.rounding
->operand
== xchg2
)
4819 i
.rounding
->operand
= xchg1
;
4824 swap_operands (void)
4830 swap_2_operands (1, i
.operands
- 2);
4834 swap_2_operands (0, i
.operands
- 1);
4840 if (i
.mem_operands
== 2)
4842 const seg_entry
*temp_seg
;
4843 temp_seg
= i
.seg
[0];
4844 i
.seg
[0] = i
.seg
[1];
4845 i
.seg
[1] = temp_seg
;
4849 /* Try to ensure constant immediates are represented in the smallest
4854 char guess_suffix
= 0;
4858 guess_suffix
= i
.suffix
;
4859 else if (i
.reg_operands
)
4861 /* Figure out a suffix from the last register operand specified.
4862 We can't do this properly yet, ie. excluding InOutPortReg,
4863 but the following works for instructions with immediates.
4864 In any case, we can't set i.suffix yet. */
4865 for (op
= i
.operands
; --op
>= 0;)
4866 if (i
.types
[op
].bitfield
.reg
&& i
.types
[op
].bitfield
.byte
)
4868 guess_suffix
= BYTE_MNEM_SUFFIX
;
4871 else if (i
.types
[op
].bitfield
.reg
&& i
.types
[op
].bitfield
.word
)
4873 guess_suffix
= WORD_MNEM_SUFFIX
;
4876 else if (i
.types
[op
].bitfield
.reg
&& i
.types
[op
].bitfield
.dword
)
4878 guess_suffix
= LONG_MNEM_SUFFIX
;
4881 else if (i
.types
[op
].bitfield
.reg
&& i
.types
[op
].bitfield
.qword
)
4883 guess_suffix
= QWORD_MNEM_SUFFIX
;
4887 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
4888 guess_suffix
= WORD_MNEM_SUFFIX
;
4890 for (op
= i
.operands
; --op
>= 0;)
4891 if (operand_type_check (i
.types
[op
], imm
))
4893 switch (i
.op
[op
].imms
->X_op
)
4896 /* If a suffix is given, this operand may be shortened. */
4897 switch (guess_suffix
)
4899 case LONG_MNEM_SUFFIX
:
4900 i
.types
[op
].bitfield
.imm32
= 1;
4901 i
.types
[op
].bitfield
.imm64
= 1;
4903 case WORD_MNEM_SUFFIX
:
4904 i
.types
[op
].bitfield
.imm16
= 1;
4905 i
.types
[op
].bitfield
.imm32
= 1;
4906 i
.types
[op
].bitfield
.imm32s
= 1;
4907 i
.types
[op
].bitfield
.imm64
= 1;
4909 case BYTE_MNEM_SUFFIX
:
4910 i
.types
[op
].bitfield
.imm8
= 1;
4911 i
.types
[op
].bitfield
.imm8s
= 1;
4912 i
.types
[op
].bitfield
.imm16
= 1;
4913 i
.types
[op
].bitfield
.imm32
= 1;
4914 i
.types
[op
].bitfield
.imm32s
= 1;
4915 i
.types
[op
].bitfield
.imm64
= 1;
4919 /* If this operand is at most 16 bits, convert it
4920 to a signed 16 bit number before trying to see
4921 whether it will fit in an even smaller size.
4922 This allows a 16-bit operand such as $0xffe0 to
4923 be recognised as within Imm8S range. */
4924 if ((i
.types
[op
].bitfield
.imm16
)
4925 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
4927 i
.op
[op
].imms
->X_add_number
=
4928 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
4931 /* Store 32-bit immediate in 64-bit for 64-bit BFD. */
4932 if ((i
.types
[op
].bitfield
.imm32
)
4933 && ((i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1))
4936 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
4937 ^ ((offsetT
) 1 << 31))
4938 - ((offsetT
) 1 << 31));
4942 = operand_type_or (i
.types
[op
],
4943 smallest_imm_type (i
.op
[op
].imms
->X_add_number
));
4945 /* We must avoid matching of Imm32 templates when 64bit
4946 only immediate is available. */
4947 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
4948 i
.types
[op
].bitfield
.imm32
= 0;
4955 /* Symbols and expressions. */
4957 /* Convert symbolic operand to proper sizes for matching, but don't
4958 prevent matching a set of insns that only supports sizes other
4959 than those matching the insn suffix. */
4961 i386_operand_type mask
, allowed
;
4962 const insn_template
*t
;
4964 operand_type_set (&mask
, 0);
4965 operand_type_set (&allowed
, 0);
4967 for (t
= current_templates
->start
;
4968 t
< current_templates
->end
;
4970 allowed
= operand_type_or (allowed
,
4971 t
->operand_types
[op
]);
4972 switch (guess_suffix
)
4974 case QWORD_MNEM_SUFFIX
:
4975 mask
.bitfield
.imm64
= 1;
4976 mask
.bitfield
.imm32s
= 1;
4978 case LONG_MNEM_SUFFIX
:
4979 mask
.bitfield
.imm32
= 1;
4981 case WORD_MNEM_SUFFIX
:
4982 mask
.bitfield
.imm16
= 1;
4984 case BYTE_MNEM_SUFFIX
:
4985 mask
.bitfield
.imm8
= 1;
4990 allowed
= operand_type_and (mask
, allowed
);
4991 if (!operand_type_all_zero (&allowed
))
4992 i
.types
[op
] = operand_type_and (i
.types
[op
], mask
);
4999 /* Try to use the smallest displacement type too. */
5001 optimize_disp (void)
5005 for (op
= i
.operands
; --op
>= 0;)
5006 if (operand_type_check (i
.types
[op
], disp
))
5008 if (i
.op
[op
].disps
->X_op
== O_constant
)
5010 offsetT op_disp
= i
.op
[op
].disps
->X_add_number
;
5012 if (i
.types
[op
].bitfield
.disp16
5013 && (op_disp
& ~(offsetT
) 0xffff) == 0)
5015 /* If this operand is at most 16 bits, convert
5016 to a signed 16 bit number and don't use 64bit
5018 op_disp
= (((op_disp
& 0xffff) ^ 0x8000) - 0x8000);
5019 i
.types
[op
].bitfield
.disp64
= 0;
5022 /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */
5023 if (i
.types
[op
].bitfield
.disp32
5024 && (op_disp
& ~(((offsetT
) 2 << 31) - 1)) == 0)
5026 /* If this operand is at most 32 bits, convert
5027 to a signed 32 bit number and don't use 64bit
5029 op_disp
&= (((offsetT
) 2 << 31) - 1);
5030 op_disp
= (op_disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
5031 i
.types
[op
].bitfield
.disp64
= 0;
5034 if (!op_disp
&& i
.types
[op
].bitfield
.baseindex
)
5036 i
.types
[op
].bitfield
.disp8
= 0;
5037 i
.types
[op
].bitfield
.disp16
= 0;
5038 i
.types
[op
].bitfield
.disp32
= 0;
5039 i
.types
[op
].bitfield
.disp32s
= 0;
5040 i
.types
[op
].bitfield
.disp64
= 0;
5044 else if (flag_code
== CODE_64BIT
)
5046 if (fits_in_signed_long (op_disp
))
5048 i
.types
[op
].bitfield
.disp64
= 0;
5049 i
.types
[op
].bitfield
.disp32s
= 1;
5051 if (i
.prefix
[ADDR_PREFIX
]
5052 && fits_in_unsigned_long (op_disp
))
5053 i
.types
[op
].bitfield
.disp32
= 1;
5055 if ((i
.types
[op
].bitfield
.disp32
5056 || i
.types
[op
].bitfield
.disp32s
5057 || i
.types
[op
].bitfield
.disp16
)
5058 && fits_in_disp8 (op_disp
))
5059 i
.types
[op
].bitfield
.disp8
= 1;
5061 else if (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
5062 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
)
5064 fix_new_exp (frag_now
, frag_more (0) - frag_now
->fr_literal
, 0,
5065 i
.op
[op
].disps
, 0, i
.reloc
[op
]);
5066 i
.types
[op
].bitfield
.disp8
= 0;
5067 i
.types
[op
].bitfield
.disp16
= 0;
5068 i
.types
[op
].bitfield
.disp32
= 0;
5069 i
.types
[op
].bitfield
.disp32s
= 0;
5070 i
.types
[op
].bitfield
.disp64
= 0;
5073 /* We only support 64bit displacement on constants. */
5074 i
.types
[op
].bitfield
.disp64
= 0;
5078 /* Return 1 if there is a match in broadcast bytes between operand
5079 GIVEN and instruction template T. */
5082 match_broadcast_size (const insn_template
*t
, unsigned int given
)
5084 return ((t
->opcode_modifier
.broadcast
== BYTE_BROADCAST
5085 && i
.types
[given
].bitfield
.byte
)
5086 || (t
->opcode_modifier
.broadcast
== WORD_BROADCAST
5087 && i
.types
[given
].bitfield
.word
)
5088 || (t
->opcode_modifier
.broadcast
== DWORD_BROADCAST
5089 && i
.types
[given
].bitfield
.dword
)
5090 || (t
->opcode_modifier
.broadcast
== QWORD_BROADCAST
5091 && i
.types
[given
].bitfield
.qword
));
5094 /* Check if operands are valid for the instruction. */
5097 check_VecOperands (const insn_template
*t
)
5101 static const i386_cpu_flags avx512
= CPU_ANY_AVX512F_FLAGS
;
5103 /* Templates allowing for ZMMword as well as YMMword and/or XMMword for
5104 any one operand are implicity requiring AVX512VL support if the actual
5105 operand size is YMMword or XMMword. Since this function runs after
5106 template matching, there's no need to check for YMMword/XMMword in
5108 cpu
= cpu_flags_and (t
->cpu_flags
, avx512
);
5109 if (!cpu_flags_all_zero (&cpu
)
5110 && !t
->cpu_flags
.bitfield
.cpuavx512vl
5111 && !cpu_arch_flags
.bitfield
.cpuavx512vl
)
5113 for (op
= 0; op
< t
->operands
; ++op
)
5115 if (t
->operand_types
[op
].bitfield
.zmmword
5116 && (i
.types
[op
].bitfield
.ymmword
5117 || i
.types
[op
].bitfield
.xmmword
))
5119 i
.error
= unsupported
;
5125 /* Without VSIB byte, we can't have a vector register for index. */
5126 if (!t
->opcode_modifier
.vecsib
5128 && (i
.index_reg
->reg_type
.bitfield
.xmmword
5129 || i
.index_reg
->reg_type
.bitfield
.ymmword
5130 || i
.index_reg
->reg_type
.bitfield
.zmmword
))
5132 i
.error
= unsupported_vector_index_register
;
5136 /* Check if default mask is allowed. */
5137 if (t
->opcode_modifier
.nodefmask
5138 && (!i
.mask
|| i
.mask
->mask
->reg_num
== 0))
5140 i
.error
= no_default_mask
;
5144 /* For VSIB byte, we need a vector register for index, and all vector
5145 registers must be distinct. */
5146 if (t
->opcode_modifier
.vecsib
)
5149 || !((t
->opcode_modifier
.vecsib
== VecSIB128
5150 && i
.index_reg
->reg_type
.bitfield
.xmmword
)
5151 || (t
->opcode_modifier
.vecsib
== VecSIB256
5152 && i
.index_reg
->reg_type
.bitfield
.ymmword
)
5153 || (t
->opcode_modifier
.vecsib
== VecSIB512
5154 && i
.index_reg
->reg_type
.bitfield
.zmmword
)))
5156 i
.error
= invalid_vsib_address
;
5160 gas_assert (i
.reg_operands
== 2 || i
.mask
);
5161 if (i
.reg_operands
== 2 && !i
.mask
)
5163 gas_assert (i
.types
[0].bitfield
.regsimd
);
5164 gas_assert (i
.types
[0].bitfield
.xmmword
5165 || i
.types
[0].bitfield
.ymmword
);
5166 gas_assert (i
.types
[2].bitfield
.regsimd
);
5167 gas_assert (i
.types
[2].bitfield
.xmmword
5168 || i
.types
[2].bitfield
.ymmword
);
5169 if (operand_check
== check_none
)
5171 if (register_number (i
.op
[0].regs
)
5172 != register_number (i
.index_reg
)
5173 && register_number (i
.op
[2].regs
)
5174 != register_number (i
.index_reg
)
5175 && register_number (i
.op
[0].regs
)
5176 != register_number (i
.op
[2].regs
))
5178 if (operand_check
== check_error
)
5180 i
.error
= invalid_vector_register_set
;
5183 as_warn (_("mask, index, and destination registers should be distinct"));
5185 else if (i
.reg_operands
== 1 && i
.mask
)
5187 if (i
.types
[1].bitfield
.regsimd
5188 && (i
.types
[1].bitfield
.xmmword
5189 || i
.types
[1].bitfield
.ymmword
5190 || i
.types
[1].bitfield
.zmmword
)
5191 && (register_number (i
.op
[1].regs
)
5192 == register_number (i
.index_reg
)))
5194 if (operand_check
== check_error
)
5196 i
.error
= invalid_vector_register_set
;
5199 if (operand_check
!= check_none
)
5200 as_warn (_("index and destination registers should be distinct"));
5205 /* Check if broadcast is supported by the instruction and is applied
5206 to the memory operand. */
5209 i386_operand_type type
, overlap
;
5211 /* Check if specified broadcast is supported in this instruction,
5212 and its broadcast bytes match the memory operand. */
5213 op
= i
.broadcast
->operand
;
5214 if (!t
->opcode_modifier
.broadcast
5215 || !(i
.flags
[op
] & Operand_Mem
)
5216 || (!i
.types
[op
].bitfield
.unspecified
5217 && !match_broadcast_size (t
, op
)))
5220 i
.error
= unsupported_broadcast
;
5224 i
.broadcast
->bytes
= ((1 << (t
->opcode_modifier
.broadcast
- 1))
5225 * i
.broadcast
->type
);
5226 operand_type_set (&type
, 0);
5227 switch (i
.broadcast
->bytes
)
5230 type
.bitfield
.word
= 1;
5233 type
.bitfield
.dword
= 1;
5236 type
.bitfield
.qword
= 1;
5239 type
.bitfield
.xmmword
= 1;
5242 type
.bitfield
.ymmword
= 1;
5245 type
.bitfield
.zmmword
= 1;
5251 overlap
= operand_type_and (type
, t
->operand_types
[op
]);
5252 if (operand_type_all_zero (&overlap
))
5255 if (t
->opcode_modifier
.checkregsize
)
5259 type
.bitfield
.baseindex
= 1;
5260 for (j
= 0; j
< i
.operands
; ++j
)
5263 && !operand_type_register_match(i
.types
[j
],
5264 t
->operand_types
[j
],
5266 t
->operand_types
[op
]))
5271 /* If broadcast is supported in this instruction, we need to check if
5272 operand of one-element size isn't specified without broadcast. */
5273 else if (t
->opcode_modifier
.broadcast
&& i
.mem_operands
)
5275 /* Find memory operand. */
5276 for (op
= 0; op
< i
.operands
; op
++)
5277 if (operand_type_check (i
.types
[op
], anymem
))
5279 gas_assert (op
< i
.operands
);
5280 /* Check size of the memory operand. */
5281 if (match_broadcast_size (t
, op
))
5283 i
.error
= broadcast_needed
;
5288 op
= MAX_OPERANDS
- 1; /* Avoid uninitialized variable warning. */
5290 /* Check if requested masking is supported. */
5293 switch (t
->opcode_modifier
.masking
)
5297 case MERGING_MASKING
:
5298 if (i
.mask
->zeroing
)
5301 i
.error
= unsupported_masking
;
5305 case DYNAMIC_MASKING
:
5306 /* Memory destinations allow only merging masking. */
5307 if (i
.mask
->zeroing
&& i
.mem_operands
)
5309 /* Find memory operand. */
5310 for (op
= 0; op
< i
.operands
; op
++)
5311 if (i
.flags
[op
] & Operand_Mem
)
5313 gas_assert (op
< i
.operands
);
5314 if (op
== i
.operands
- 1)
5316 i
.error
= unsupported_masking
;
5326 /* Check if masking is applied to dest operand. */
5327 if (i
.mask
&& (i
.mask
->operand
!= (int) (i
.operands
- 1)))
5329 i
.error
= mask_not_on_destination
;
5336 if ((i
.rounding
->type
!= saeonly
5337 && !t
->opcode_modifier
.staticrounding
)
5338 || (i
.rounding
->type
== saeonly
5339 && (t
->opcode_modifier
.staticrounding
5340 || !t
->opcode_modifier
.sae
)))
5342 i
.error
= unsupported_rc_sae
;
5345 /* If the instruction has several immediate operands and one of
5346 them is rounding, the rounding operand should be the last
5347 immediate operand. */
5348 if (i
.imm_operands
> 1
5349 && i
.rounding
->operand
!= (int) (i
.imm_operands
- 1))
5351 i
.error
= rc_sae_operand_not_last_imm
;
5356 /* Check vector Disp8 operand. */
5357 if (t
->opcode_modifier
.disp8memshift
5358 && i
.disp_encoding
!= disp_encoding_32bit
)
5361 i
.memshift
= t
->opcode_modifier
.broadcast
- 1;
5362 else if (t
->opcode_modifier
.disp8memshift
!= DISP8_SHIFT_VL
)
5363 i
.memshift
= t
->opcode_modifier
.disp8memshift
;
5366 const i386_operand_type
*type
= NULL
;
5369 for (op
= 0; op
< i
.operands
; op
++)
5370 if (operand_type_check (i
.types
[op
], anymem
))
5372 if (t
->opcode_modifier
.evex
== EVEXLIG
)
5373 i
.memshift
= 2 + (i
.suffix
== QWORD_MNEM_SUFFIX
);
5374 else if (t
->operand_types
[op
].bitfield
.xmmword
5375 + t
->operand_types
[op
].bitfield
.ymmword
5376 + t
->operand_types
[op
].bitfield
.zmmword
<= 1)
5377 type
= &t
->operand_types
[op
];
5378 else if (!i
.types
[op
].bitfield
.unspecified
)
5379 type
= &i
.types
[op
];
5381 else if (i
.types
[op
].bitfield
.regsimd
5382 && t
->opcode_modifier
.evex
!= EVEXLIG
)
5384 if (i
.types
[op
].bitfield
.zmmword
)
5386 else if (i
.types
[op
].bitfield
.ymmword
&& i
.memshift
< 5)
5388 else if (i
.types
[op
].bitfield
.xmmword
&& i
.memshift
< 4)
5394 if (type
->bitfield
.zmmword
)
5396 else if (type
->bitfield
.ymmword
)
5398 else if (type
->bitfield
.xmmword
)
5402 /* For the check in fits_in_disp8(). */
5403 if (i
.memshift
== 0)
5407 for (op
= 0; op
< i
.operands
; op
++)
5408 if (operand_type_check (i
.types
[op
], disp
)
5409 && i
.op
[op
].disps
->X_op
== O_constant
)
5411 if (fits_in_disp8 (i
.op
[op
].disps
->X_add_number
))
5413 i
.types
[op
].bitfield
.disp8
= 1;
5416 i
.types
[op
].bitfield
.disp8
= 0;
5425 /* Check if operands are valid for the instruction. Update VEX
5429 VEX_check_operands (const insn_template
*t
)
5431 if (i
.vec_encoding
== vex_encoding_evex
)
5433 /* This instruction must be encoded with EVEX prefix. */
5434 if (!is_evex_encoding (t
))
5436 i
.error
= unsupported
;
5442 if (!t
->opcode_modifier
.vex
)
5444 /* This instruction template doesn't have VEX prefix. */
5445 if (i
.vec_encoding
!= vex_encoding_default
)
5447 i
.error
= unsupported
;
5453 /* Only check VEX_Imm4, which must be the first operand. */
5454 if (t
->operand_types
[0].bitfield
.vec_imm4
)
5456 if (i
.op
[0].imms
->X_op
!= O_constant
5457 || !fits_in_imm4 (i
.op
[0].imms
->X_add_number
))
5463 /* Turn off Imm8 so that update_imm won't complain. */
5464 i
.types
[0] = vec_imm4
;
5470 static const insn_template
*
5471 match_template (char mnem_suffix
)
5473 /* Points to template once we've found it. */
5474 const insn_template
*t
;
5475 i386_operand_type overlap0
, overlap1
, overlap2
, overlap3
;
5476 i386_operand_type overlap4
;
5477 unsigned int found_reverse_match
;
5478 i386_opcode_modifier suffix_check
, mnemsuf_check
;
5479 i386_operand_type operand_types
[MAX_OPERANDS
];
5480 int addr_prefix_disp
;
5482 unsigned int found_cpu_match
, size_match
;
5483 unsigned int check_register
;
5484 enum i386_error specific_error
= 0;
5486 #if MAX_OPERANDS != 5
5487 # error "MAX_OPERANDS must be 5."
5490 found_reverse_match
= 0;
5491 addr_prefix_disp
= -1;
5493 memset (&suffix_check
, 0, sizeof (suffix_check
));
5494 if (intel_syntax
&& i
.broadcast
)
5496 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
5497 suffix_check
.no_bsuf
= 1;
5498 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
5499 suffix_check
.no_wsuf
= 1;
5500 else if (i
.suffix
== SHORT_MNEM_SUFFIX
)
5501 suffix_check
.no_ssuf
= 1;
5502 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
5503 suffix_check
.no_lsuf
= 1;
5504 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
5505 suffix_check
.no_qsuf
= 1;
5506 else if (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
)
5507 suffix_check
.no_ldsuf
= 1;
5509 memset (&mnemsuf_check
, 0, sizeof (mnemsuf_check
));
5512 switch (mnem_suffix
)
5514 case BYTE_MNEM_SUFFIX
: mnemsuf_check
.no_bsuf
= 1; break;
5515 case WORD_MNEM_SUFFIX
: mnemsuf_check
.no_wsuf
= 1; break;
5516 case SHORT_MNEM_SUFFIX
: mnemsuf_check
.no_ssuf
= 1; break;
5517 case LONG_MNEM_SUFFIX
: mnemsuf_check
.no_lsuf
= 1; break;
5518 case QWORD_MNEM_SUFFIX
: mnemsuf_check
.no_qsuf
= 1; break;
5522 /* Must have right number of operands. */
5523 i
.error
= number_of_operands_mismatch
;
5525 for (t
= current_templates
->start
; t
< current_templates
->end
; t
++)
5527 addr_prefix_disp
= -1;
5529 if (i
.operands
!= t
->operands
)
5532 /* Check processor support. */
5533 i
.error
= unsupported
;
5534 found_cpu_match
= (cpu_flags_match (t
)
5535 == CPU_FLAGS_PERFECT_MATCH
);
5536 if (!found_cpu_match
)
5539 /* Check AT&T mnemonic. */
5540 i
.error
= unsupported_with_intel_mnemonic
;
5541 if (intel_mnemonic
&& t
->opcode_modifier
.attmnemonic
)
5544 /* Check AT&T/Intel syntax and Intel64/AMD64 ISA. */
5545 i
.error
= unsupported_syntax
;
5546 if ((intel_syntax
&& t
->opcode_modifier
.attsyntax
)
5547 || (!intel_syntax
&& t
->opcode_modifier
.intelsyntax
)
5548 || (intel64
&& t
->opcode_modifier
.amd64
)
5549 || (!intel64
&& t
->opcode_modifier
.intel64
))
5552 /* Check the suffix, except for some instructions in intel mode. */
5553 i
.error
= invalid_instruction_suffix
;
5554 if ((!intel_syntax
|| !t
->opcode_modifier
.ignoresize
)
5555 && ((t
->opcode_modifier
.no_bsuf
&& suffix_check
.no_bsuf
)
5556 || (t
->opcode_modifier
.no_wsuf
&& suffix_check
.no_wsuf
)
5557 || (t
->opcode_modifier
.no_lsuf
&& suffix_check
.no_lsuf
)
5558 || (t
->opcode_modifier
.no_ssuf
&& suffix_check
.no_ssuf
)
5559 || (t
->opcode_modifier
.no_qsuf
&& suffix_check
.no_qsuf
)
5560 || (t
->opcode_modifier
.no_ldsuf
&& suffix_check
.no_ldsuf
)))
5562 /* In Intel mode all mnemonic suffixes must be explicitly allowed. */
5563 if ((t
->opcode_modifier
.no_bsuf
&& mnemsuf_check
.no_bsuf
)
5564 || (t
->opcode_modifier
.no_wsuf
&& mnemsuf_check
.no_wsuf
)
5565 || (t
->opcode_modifier
.no_lsuf
&& mnemsuf_check
.no_lsuf
)
5566 || (t
->opcode_modifier
.no_ssuf
&& mnemsuf_check
.no_ssuf
)
5567 || (t
->opcode_modifier
.no_qsuf
&& mnemsuf_check
.no_qsuf
)
5568 || (t
->opcode_modifier
.no_ldsuf
&& mnemsuf_check
.no_ldsuf
))
5571 size_match
= operand_size_match (t
);
5575 for (j
= 0; j
< MAX_OPERANDS
; j
++)
5576 operand_types
[j
] = t
->operand_types
[j
];
5578 /* In general, don't allow 64-bit operands in 32-bit mode. */
5579 if (i
.suffix
== QWORD_MNEM_SUFFIX
5580 && flag_code
!= CODE_64BIT
5582 ? (!t
->opcode_modifier
.ignoresize
5583 && !t
->opcode_modifier
.broadcast
5584 && !intel_float_operand (t
->name
))
5585 : intel_float_operand (t
->name
) != 2)
5586 && ((!operand_types
[0].bitfield
.regmmx
5587 && !operand_types
[0].bitfield
.regsimd
)
5588 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
5589 && !operand_types
[t
->operands
> 1].bitfield
.regsimd
))
5590 && (t
->base_opcode
!= 0x0fc7
5591 || t
->extension_opcode
!= 1 /* cmpxchg8b */))
5594 /* In general, don't allow 32-bit operands on pre-386. */
5595 else if (i
.suffix
== LONG_MNEM_SUFFIX
5596 && !cpu_arch_flags
.bitfield
.cpui386
5598 ? (!t
->opcode_modifier
.ignoresize
5599 && !intel_float_operand (t
->name
))
5600 : intel_float_operand (t
->name
) != 2)
5601 && ((!operand_types
[0].bitfield
.regmmx
5602 && !operand_types
[0].bitfield
.regsimd
)
5603 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
5604 && !operand_types
[t
->operands
> 1].bitfield
.regsimd
)))
5607 /* Do not verify operands when there are none. */
5611 /* We've found a match; break out of loop. */
5615 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
5616 into Disp32/Disp16/Disp32 operand. */
5617 if (i
.prefix
[ADDR_PREFIX
] != 0)
5619 /* There should be only one Disp operand. */
5623 for (j
= 0; j
< MAX_OPERANDS
; j
++)
5625 if (operand_types
[j
].bitfield
.disp16
)
5627 addr_prefix_disp
= j
;
5628 operand_types
[j
].bitfield
.disp32
= 1;
5629 operand_types
[j
].bitfield
.disp16
= 0;
5635 for (j
= 0; j
< MAX_OPERANDS
; j
++)
5637 if (operand_types
[j
].bitfield
.disp32
)
5639 addr_prefix_disp
= j
;
5640 operand_types
[j
].bitfield
.disp32
= 0;
5641 operand_types
[j
].bitfield
.disp16
= 1;
5647 for (j
= 0; j
< MAX_OPERANDS
; j
++)
5649 if (operand_types
[j
].bitfield
.disp64
)
5651 addr_prefix_disp
= j
;
5652 operand_types
[j
].bitfield
.disp64
= 0;
5653 operand_types
[j
].bitfield
.disp32
= 1;
5661 /* Force 0x8b encoding for "mov foo@GOT, %eax". */
5662 if (i
.reloc
[0] == BFD_RELOC_386_GOT32
&& t
->base_opcode
== 0xa0)
5665 /* We check register size if needed. */
5666 if (t
->opcode_modifier
.checkregsize
)
5668 check_register
= (1 << t
->operands
) - 1;
5670 check_register
&= ~(1 << i
.broadcast
->operand
);
5675 overlap0
= operand_type_and (i
.types
[0], operand_types
[0]);
5676 switch (t
->operands
)
5679 if (!operand_type_match (overlap0
, i
.types
[0]))
5683 /* xchg %eax, %eax is a special case. It is an alias for nop
5684 only in 32bit mode and we can use opcode 0x90. In 64bit
5685 mode, we can't use 0x90 for xchg %eax, %eax since it should
5686 zero-extend %eax to %rax. */
5687 if (flag_code
== CODE_64BIT
5688 && t
->base_opcode
== 0x90
5689 && operand_type_equal (&i
.types
[0], &acc32
)
5690 && operand_type_equal (&i
.types
[1], &acc32
))
5692 /* xrelease mov %eax, <disp> is another special case. It must not
5693 match the accumulator-only encoding of mov. */
5694 if (flag_code
!= CODE_64BIT
5696 && t
->base_opcode
== 0xa0
5697 && i
.types
[0].bitfield
.acc
5698 && operand_type_check (i
.types
[1], anymem
))
5700 if (!(size_match
& MATCH_STRAIGHT
))
5702 /* If we want store form, we reverse direction of operands. */
5703 if (i
.dir_encoding
== dir_encoding_store
5704 && t
->opcode_modifier
.d
)
5709 /* If we want store form, we skip the current load. */
5710 if (i
.dir_encoding
== dir_encoding_store
5711 && i
.mem_operands
== 0
5712 && t
->opcode_modifier
.load
)
5717 overlap1
= operand_type_and (i
.types
[1], operand_types
[1]);
5718 if (!operand_type_match (overlap0
, i
.types
[0])
5719 || !operand_type_match (overlap1
, i
.types
[1])
5720 || ((check_register
& 3) == 3
5721 && !operand_type_register_match (i
.types
[0],
5726 /* Check if other direction is valid ... */
5727 if (!t
->opcode_modifier
.d
)
5731 if (!(size_match
& MATCH_REVERSE
))
5733 /* Try reversing direction of operands. */
5734 overlap0
= operand_type_and (i
.types
[0], operand_types
[1]);
5735 overlap1
= operand_type_and (i
.types
[1], operand_types
[0]);
5736 if (!operand_type_match (overlap0
, i
.types
[0])
5737 || !operand_type_match (overlap1
, i
.types
[1])
5739 && !operand_type_register_match (i
.types
[0],
5744 /* Does not match either direction. */
5747 /* found_reverse_match holds which of D or FloatR
5749 if (!t
->opcode_modifier
.d
)
5750 found_reverse_match
= 0;
5751 else if (operand_types
[0].bitfield
.tbyte
)
5752 found_reverse_match
= Opcode_FloatD
;
5754 found_reverse_match
= Opcode_D
;
5755 if (t
->opcode_modifier
.floatr
)
5756 found_reverse_match
|= Opcode_FloatR
;
5760 /* Found a forward 2 operand match here. */
5761 switch (t
->operands
)
5764 overlap4
= operand_type_and (i
.types
[4],
5768 overlap3
= operand_type_and (i
.types
[3],
5772 overlap2
= operand_type_and (i
.types
[2],
5777 switch (t
->operands
)
5780 if (!operand_type_match (overlap4
, i
.types
[4])
5781 || !operand_type_register_match (i
.types
[3],
5788 if (!operand_type_match (overlap3
, i
.types
[3])
5789 || ((check_register
& 0xa) == 0xa
5790 && !operand_type_register_match (i
.types
[1],
5794 || ((check_register
& 0xc) == 0xc
5795 && !operand_type_register_match (i
.types
[2],
5802 /* Here we make use of the fact that there are no
5803 reverse match 3 operand instructions. */
5804 if (!operand_type_match (overlap2
, i
.types
[2])
5805 || ((check_register
& 5) == 5
5806 && !operand_type_register_match (i
.types
[0],
5810 || ((check_register
& 6) == 6
5811 && !operand_type_register_match (i
.types
[1],
5819 /* Found either forward/reverse 2, 3 or 4 operand match here:
5820 slip through to break. */
5822 if (!found_cpu_match
)
5824 found_reverse_match
= 0;
5828 /* Check if vector and VEX operands are valid. */
5829 if (check_VecOperands (t
) || VEX_check_operands (t
))
5831 specific_error
= i
.error
;
5835 /* We've found a match; break out of loop. */
5839 if (t
== current_templates
->end
)
5841 /* We found no match. */
5842 const char *err_msg
;
5843 switch (specific_error
? specific_error
: i
.error
)
5847 case operand_size_mismatch
:
5848 err_msg
= _("operand size mismatch");
5850 case operand_type_mismatch
:
5851 err_msg
= _("operand type mismatch");
5853 case register_type_mismatch
:
5854 err_msg
= _("register type mismatch");
5856 case number_of_operands_mismatch
:
5857 err_msg
= _("number of operands mismatch");
5859 case invalid_instruction_suffix
:
5860 err_msg
= _("invalid instruction suffix");
5863 err_msg
= _("constant doesn't fit in 4 bits");
5865 case unsupported_with_intel_mnemonic
:
5866 err_msg
= _("unsupported with Intel mnemonic");
5868 case unsupported_syntax
:
5869 err_msg
= _("unsupported syntax");
5872 as_bad (_("unsupported instruction `%s'"),
5873 current_templates
->start
->name
);
5875 case invalid_vsib_address
:
5876 err_msg
= _("invalid VSIB address");
5878 case invalid_vector_register_set
:
5879 err_msg
= _("mask, index, and destination registers must be distinct");
5881 case unsupported_vector_index_register
:
5882 err_msg
= _("unsupported vector index register");
5884 case unsupported_broadcast
:
5885 err_msg
= _("unsupported broadcast");
5887 case broadcast_needed
:
5888 err_msg
= _("broadcast is needed for operand of such type");
5890 case unsupported_masking
:
5891 err_msg
= _("unsupported masking");
5893 case mask_not_on_destination
:
5894 err_msg
= _("mask not on destination operand");
5896 case no_default_mask
:
5897 err_msg
= _("default mask isn't allowed");
5899 case unsupported_rc_sae
:
5900 err_msg
= _("unsupported static rounding/sae");
5902 case rc_sae_operand_not_last_imm
:
5904 err_msg
= _("RC/SAE operand must precede immediate operands");
5906 err_msg
= _("RC/SAE operand must follow immediate operands");
5908 case invalid_register_operand
:
5909 err_msg
= _("invalid register operand");
5912 as_bad (_("%s for `%s'"), err_msg
,
5913 current_templates
->start
->name
);
5917 if (!quiet_warnings
)
5920 && (i
.types
[0].bitfield
.jumpabsolute
5921 != operand_types
[0].bitfield
.jumpabsolute
))
5923 as_warn (_("indirect %s without `*'"), t
->name
);
5926 if (t
->opcode_modifier
.isprefix
5927 && t
->opcode_modifier
.ignoresize
)
5929 /* Warn them that a data or address size prefix doesn't
5930 affect assembly of the next line of code. */
5931 as_warn (_("stand-alone `%s' prefix"), t
->name
);
5935 /* Copy the template we found. */
5938 if (addr_prefix_disp
!= -1)
5939 i
.tm
.operand_types
[addr_prefix_disp
]
5940 = operand_types
[addr_prefix_disp
];
5942 if (found_reverse_match
)
5944 /* If we found a reverse match we must alter the opcode
5945 direction bit. found_reverse_match holds bits to change
5946 (different for int & float insns). */
5948 i
.tm
.base_opcode
^= found_reverse_match
;
5950 i
.tm
.operand_types
[0] = operand_types
[1];
5951 i
.tm
.operand_types
[1] = operand_types
[0];
5960 int mem_op
= operand_type_check (i
.types
[0], anymem
) ? 0 : 1;
5961 if (i
.tm
.operand_types
[mem_op
].bitfield
.esseg
)
5963 if (i
.seg
[0] != NULL
&& i
.seg
[0] != &es
)
5965 as_bad (_("`%s' operand %d must use `%ses' segment"),
5971 /* There's only ever one segment override allowed per instruction.
5972 This instruction possibly has a legal segment override on the
5973 second operand, so copy the segment to where non-string
5974 instructions store it, allowing common code. */
5975 i
.seg
[0] = i
.seg
[1];
5977 else if (i
.tm
.operand_types
[mem_op
+ 1].bitfield
.esseg
)
5979 if (i
.seg
[1] != NULL
&& i
.seg
[1] != &es
)
5981 as_bad (_("`%s' operand %d must use `%ses' segment"),
5992 process_suffix (void)
5994 /* If matched instruction specifies an explicit instruction mnemonic
5996 if (i
.tm
.opcode_modifier
.size16
)
5997 i
.suffix
= WORD_MNEM_SUFFIX
;
5998 else if (i
.tm
.opcode_modifier
.size32
)
5999 i
.suffix
= LONG_MNEM_SUFFIX
;
6000 else if (i
.tm
.opcode_modifier
.size64
)
6001 i
.suffix
= QWORD_MNEM_SUFFIX
;
6002 else if (i
.reg_operands
)
6004 /* If there's no instruction mnemonic suffix we try to invent one
6005 based on register operands. */
6008 /* We take i.suffix from the last register operand specified,
6009 Destination register type is more significant than source
6010 register type. crc32 in SSE4.2 prefers source register
6012 if (i
.tm
.base_opcode
== 0xf20f38f1)
6014 if (i
.types
[0].bitfield
.reg
&& i
.types
[0].bitfield
.word
)
6015 i
.suffix
= WORD_MNEM_SUFFIX
;
6016 else if (i
.types
[0].bitfield
.reg
&& i
.types
[0].bitfield
.dword
)
6017 i
.suffix
= LONG_MNEM_SUFFIX
;
6018 else if (i
.types
[0].bitfield
.reg
&& i
.types
[0].bitfield
.qword
)
6019 i
.suffix
= QWORD_MNEM_SUFFIX
;
6021 else if (i
.tm
.base_opcode
== 0xf20f38f0)
6023 if (i
.types
[0].bitfield
.reg
&& i
.types
[0].bitfield
.byte
)
6024 i
.suffix
= BYTE_MNEM_SUFFIX
;
6031 if (i
.tm
.base_opcode
== 0xf20f38f1
6032 || i
.tm
.base_opcode
== 0xf20f38f0)
6034 /* We have to know the operand size for crc32. */
6035 as_bad (_("ambiguous memory operand size for `%s`"),
6040 for (op
= i
.operands
; --op
>= 0;)
6041 if (!i
.tm
.operand_types
[op
].bitfield
.inoutportreg
6042 && !i
.tm
.operand_types
[op
].bitfield
.shiftcount
)
6044 if (!i
.types
[op
].bitfield
.reg
)
6046 if (i
.types
[op
].bitfield
.byte
)
6047 i
.suffix
= BYTE_MNEM_SUFFIX
;
6048 else if (i
.types
[op
].bitfield
.word
)
6049 i
.suffix
= WORD_MNEM_SUFFIX
;
6050 else if (i
.types
[op
].bitfield
.dword
)
6051 i
.suffix
= LONG_MNEM_SUFFIX
;
6052 else if (i
.types
[op
].bitfield
.qword
)
6053 i
.suffix
= QWORD_MNEM_SUFFIX
;
6060 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
6063 && i
.tm
.opcode_modifier
.ignoresize
6064 && i
.tm
.opcode_modifier
.no_bsuf
)
6066 else if (!check_byte_reg ())
6069 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
6072 && i
.tm
.opcode_modifier
.ignoresize
6073 && i
.tm
.opcode_modifier
.no_lsuf
6074 && !i
.tm
.opcode_modifier
.todword
6075 && !i
.tm
.opcode_modifier
.toqword
)
6077 else if (!check_long_reg ())
6080 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
6083 && i
.tm
.opcode_modifier
.ignoresize
6084 && i
.tm
.opcode_modifier
.no_qsuf
6085 && !i
.tm
.opcode_modifier
.todword
6086 && !i
.tm
.opcode_modifier
.toqword
)
6088 else if (!check_qword_reg ())
6091 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
6094 && i
.tm
.opcode_modifier
.ignoresize
6095 && i
.tm
.opcode_modifier
.no_wsuf
)
6097 else if (!check_word_reg ())
6100 else if (intel_syntax
&& i
.tm
.opcode_modifier
.ignoresize
)
6101 /* Do nothing if the instruction is going to ignore the prefix. */
6106 else if (i
.tm
.opcode_modifier
.defaultsize
6108 /* exclude fldenv/frstor/fsave/fstenv */
6109 && i
.tm
.opcode_modifier
.no_ssuf
)
6111 i
.suffix
= stackop_size
;
6113 else if (intel_syntax
6115 && (i
.tm
.operand_types
[0].bitfield
.jumpabsolute
6116 || i
.tm
.opcode_modifier
.jumpbyte
6117 || i
.tm
.opcode_modifier
.jumpintersegment
6118 || (i
.tm
.base_opcode
== 0x0f01 /* [ls][gi]dt */
6119 && i
.tm
.extension_opcode
<= 3)))
6124 if (!i
.tm
.opcode_modifier
.no_qsuf
)
6126 i
.suffix
= QWORD_MNEM_SUFFIX
;
6131 if (!i
.tm
.opcode_modifier
.no_lsuf
)
6132 i
.suffix
= LONG_MNEM_SUFFIX
;
6135 if (!i
.tm
.opcode_modifier
.no_wsuf
)
6136 i
.suffix
= WORD_MNEM_SUFFIX
;
6145 if (i
.tm
.opcode_modifier
.w
)
6147 as_bad (_("no instruction mnemonic suffix given and "
6148 "no register operands; can't size instruction"));
6154 unsigned int suffixes
;
6156 suffixes
= !i
.tm
.opcode_modifier
.no_bsuf
;
6157 if (!i
.tm
.opcode_modifier
.no_wsuf
)
6159 if (!i
.tm
.opcode_modifier
.no_lsuf
)
6161 if (!i
.tm
.opcode_modifier
.no_ldsuf
)
6163 if (!i
.tm
.opcode_modifier
.no_ssuf
)
6165 if (flag_code
== CODE_64BIT
&& !i
.tm
.opcode_modifier
.no_qsuf
)
6168 /* There are more than suffix matches. */
6169 if (i
.tm
.opcode_modifier
.w
6170 || ((suffixes
& (suffixes
- 1))
6171 && !i
.tm
.opcode_modifier
.defaultsize
6172 && !i
.tm
.opcode_modifier
.ignoresize
))
6174 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
6180 /* Change the opcode based on the operand size given by i.suffix. */
6183 /* Size floating point instruction. */
6184 case LONG_MNEM_SUFFIX
:
6185 if (i
.tm
.opcode_modifier
.floatmf
)
6187 i
.tm
.base_opcode
^= 4;
6191 case WORD_MNEM_SUFFIX
:
6192 case QWORD_MNEM_SUFFIX
:
6193 /* It's not a byte, select word/dword operation. */
6194 if (i
.tm
.opcode_modifier
.w
)
6196 if (i
.tm
.opcode_modifier
.shortform
)
6197 i
.tm
.base_opcode
|= 8;
6199 i
.tm
.base_opcode
|= 1;
6202 case SHORT_MNEM_SUFFIX
:
6203 /* Now select between word & dword operations via the operand
6204 size prefix, except for instructions that will ignore this
6206 if (i
.reg_operands
> 0
6207 && i
.types
[0].bitfield
.reg
6208 && i
.tm
.opcode_modifier
.addrprefixopreg
6209 && (i
.tm
.opcode_modifier
.immext
6210 || i
.operands
== 1))
6212 /* The address size override prefix changes the size of the
6214 if ((flag_code
== CODE_32BIT
6215 && i
.op
[0].regs
->reg_type
.bitfield
.word
)
6216 || (flag_code
!= CODE_32BIT
6217 && i
.op
[0].regs
->reg_type
.bitfield
.dword
))
6218 if (!add_prefix (ADDR_PREFIX_OPCODE
))
6221 else if (i
.suffix
!= QWORD_MNEM_SUFFIX
6222 && !i
.tm
.opcode_modifier
.ignoresize
6223 && !i
.tm
.opcode_modifier
.floatmf
6224 && !i
.tm
.opcode_modifier
.vex
6225 && !i
.tm
.opcode_modifier
.vexopcode
6226 && !is_evex_encoding (&i
.tm
)
6227 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
6228 || (flag_code
== CODE_64BIT
6229 && i
.tm
.opcode_modifier
.jumpbyte
)))
6231 unsigned int prefix
= DATA_PREFIX_OPCODE
;
6233 if (i
.tm
.opcode_modifier
.jumpbyte
) /* jcxz, loop */
6234 prefix
= ADDR_PREFIX_OPCODE
;
6236 if (!add_prefix (prefix
))
6240 /* Set mode64 for an operand. */
6241 if (i
.suffix
== QWORD_MNEM_SUFFIX
6242 && flag_code
== CODE_64BIT
6243 && !i
.tm
.opcode_modifier
.norex64
6244 /* Special case for xchg %rax,%rax. It is NOP and doesn't
6246 && ! (i
.operands
== 2
6247 && i
.tm
.base_opcode
== 0x90
6248 && i
.tm
.extension_opcode
== None
6249 && operand_type_equal (&i
.types
[0], &acc64
)
6250 && operand_type_equal (&i
.types
[1], &acc64
)))
6256 if (i
.reg_operands
!= 0
6258 && i
.tm
.opcode_modifier
.addrprefixopreg
6259 && !i
.tm
.opcode_modifier
.immext
)
6261 /* Check invalid register operand when the address size override
6262 prefix changes the size of register operands. */
6264 enum { need_word
, need_dword
, need_qword
} need
;
6266 if (flag_code
== CODE_32BIT
)
6267 need
= i
.prefix
[ADDR_PREFIX
] ? need_word
: need_dword
;
6270 if (i
.prefix
[ADDR_PREFIX
])
6273 need
= flag_code
== CODE_64BIT
? need_qword
: need_word
;
6276 for (op
= 0; op
< i
.operands
; op
++)
6277 if (i
.types
[op
].bitfield
.reg
6278 && ((need
== need_word
6279 && !i
.op
[op
].regs
->reg_type
.bitfield
.word
)
6280 || (need
== need_dword
6281 && !i
.op
[op
].regs
->reg_type
.bitfield
.dword
)
6282 || (need
== need_qword
6283 && !i
.op
[op
].regs
->reg_type
.bitfield
.qword
)))
6285 as_bad (_("invalid register operand size for `%s'"),
6295 check_byte_reg (void)
6299 for (op
= i
.operands
; --op
>= 0;)
6301 /* Skip non-register operands. */
6302 if (!i
.types
[op
].bitfield
.reg
)
6305 /* If this is an eight bit register, it's OK. If it's the 16 or
6306 32 bit version of an eight bit register, we will just use the
6307 low portion, and that's OK too. */
6308 if (i
.types
[op
].bitfield
.byte
)
6311 /* I/O port address operands are OK too. */
6312 if (i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
6315 /* crc32 doesn't generate this warning. */
6316 if (i
.tm
.base_opcode
== 0xf20f38f0)
6319 if ((i
.types
[op
].bitfield
.word
6320 || i
.types
[op
].bitfield
.dword
6321 || i
.types
[op
].bitfield
.qword
)
6322 && i
.op
[op
].regs
->reg_num
< 4
6323 /* Prohibit these changes in 64bit mode, since the lowering
6324 would be more complicated. */
6325 && flag_code
!= CODE_64BIT
)
6327 #if REGISTER_WARNINGS
6328 if (!quiet_warnings
)
6329 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6331 (i
.op
[op
].regs
+ (i
.types
[op
].bitfield
.word
6332 ? REGNAM_AL
- REGNAM_AX
6333 : REGNAM_AL
- REGNAM_EAX
))->reg_name
,
6335 i
.op
[op
].regs
->reg_name
,
6340 /* Any other register is bad. */
6341 if (i
.types
[op
].bitfield
.reg
6342 || i
.types
[op
].bitfield
.regmmx
6343 || i
.types
[op
].bitfield
.regsimd
6344 || i
.types
[op
].bitfield
.sreg2
6345 || i
.types
[op
].bitfield
.sreg3
6346 || i
.types
[op
].bitfield
.control
6347 || i
.types
[op
].bitfield
.debug
6348 || i
.types
[op
].bitfield
.test
)
6350 as_bad (_("`%s%s' not allowed with `%s%c'"),
6352 i
.op
[op
].regs
->reg_name
,
6362 check_long_reg (void)
6366 for (op
= i
.operands
; --op
>= 0;)
6367 /* Skip non-register operands. */
6368 if (!i
.types
[op
].bitfield
.reg
)
6370 /* Reject eight bit registers, except where the template requires
6371 them. (eg. movzb) */
6372 else if (i
.types
[op
].bitfield
.byte
6373 && (i
.tm
.operand_types
[op
].bitfield
.reg
6374 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6375 && (i
.tm
.operand_types
[op
].bitfield
.word
6376 || i
.tm
.operand_types
[op
].bitfield
.dword
))
6378 as_bad (_("`%s%s' not allowed with `%s%c'"),
6380 i
.op
[op
].regs
->reg_name
,
6385 /* Warn if the e prefix on a general reg is missing. */
6386 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
6387 && i
.types
[op
].bitfield
.word
6388 && (i
.tm
.operand_types
[op
].bitfield
.reg
6389 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6390 && i
.tm
.operand_types
[op
].bitfield
.dword
)
6392 /* Prohibit these changes in the 64bit mode, since the
6393 lowering is more complicated. */
6394 if (flag_code
== CODE_64BIT
)
6396 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6397 register_prefix
, i
.op
[op
].regs
->reg_name
,
6401 #if REGISTER_WARNINGS
6402 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6404 (i
.op
[op
].regs
+ REGNAM_EAX
- REGNAM_AX
)->reg_name
,
6405 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
6408 /* Warn if the r prefix on a general reg is present. */
6409 else if (i
.types
[op
].bitfield
.qword
6410 && (i
.tm
.operand_types
[op
].bitfield
.reg
6411 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6412 && i
.tm
.operand_types
[op
].bitfield
.dword
)
6415 && i
.tm
.opcode_modifier
.toqword
6416 && !i
.types
[0].bitfield
.regsimd
)
6418 /* Convert to QWORD. We want REX byte. */
6419 i
.suffix
= QWORD_MNEM_SUFFIX
;
6423 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6424 register_prefix
, i
.op
[op
].regs
->reg_name
,
6433 check_qword_reg (void)
6437 for (op
= i
.operands
; --op
>= 0; )
6438 /* Skip non-register operands. */
6439 if (!i
.types
[op
].bitfield
.reg
)
6441 /* Reject eight bit registers, except where the template requires
6442 them. (eg. movzb) */
6443 else if (i
.types
[op
].bitfield
.byte
6444 && (i
.tm
.operand_types
[op
].bitfield
.reg
6445 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6446 && (i
.tm
.operand_types
[op
].bitfield
.word
6447 || i
.tm
.operand_types
[op
].bitfield
.dword
))
6449 as_bad (_("`%s%s' not allowed with `%s%c'"),
6451 i
.op
[op
].regs
->reg_name
,
6456 /* Warn if the r prefix on a general reg is missing. */
6457 else if ((i
.types
[op
].bitfield
.word
6458 || i
.types
[op
].bitfield
.dword
)
6459 && (i
.tm
.operand_types
[op
].bitfield
.reg
6460 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6461 && i
.tm
.operand_types
[op
].bitfield
.qword
)
6463 /* Prohibit these changes in the 64bit mode, since the
6464 lowering is more complicated. */
6466 && i
.tm
.opcode_modifier
.todword
6467 && !i
.types
[0].bitfield
.regsimd
)
6469 /* Convert to DWORD. We don't want REX byte. */
6470 i
.suffix
= LONG_MNEM_SUFFIX
;
6474 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6475 register_prefix
, i
.op
[op
].regs
->reg_name
,
6484 check_word_reg (void)
6487 for (op
= i
.operands
; --op
>= 0;)
6488 /* Skip non-register operands. */
6489 if (!i
.types
[op
].bitfield
.reg
)
6491 /* Reject eight bit registers, except where the template requires
6492 them. (eg. movzb) */
6493 else if (i
.types
[op
].bitfield
.byte
6494 && (i
.tm
.operand_types
[op
].bitfield
.reg
6495 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6496 && (i
.tm
.operand_types
[op
].bitfield
.word
6497 || i
.tm
.operand_types
[op
].bitfield
.dword
))
6499 as_bad (_("`%s%s' not allowed with `%s%c'"),
6501 i
.op
[op
].regs
->reg_name
,
6506 /* Warn if the e or r prefix on a general reg is present. */
6507 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
6508 && (i
.types
[op
].bitfield
.dword
6509 || i
.types
[op
].bitfield
.qword
)
6510 && (i
.tm
.operand_types
[op
].bitfield
.reg
6511 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6512 && i
.tm
.operand_types
[op
].bitfield
.word
)
6514 /* Prohibit these changes in the 64bit mode, since the
6515 lowering is more complicated. */
6516 if (flag_code
== CODE_64BIT
)
6518 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6519 register_prefix
, i
.op
[op
].regs
->reg_name
,
6523 #if REGISTER_WARNINGS
6524 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6526 (i
.op
[op
].regs
+ REGNAM_AX
- REGNAM_EAX
)->reg_name
,
6527 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
6534 update_imm (unsigned int j
)
6536 i386_operand_type overlap
= i
.types
[j
];
6537 if ((overlap
.bitfield
.imm8
6538 || overlap
.bitfield
.imm8s
6539 || overlap
.bitfield
.imm16
6540 || overlap
.bitfield
.imm32
6541 || overlap
.bitfield
.imm32s
6542 || overlap
.bitfield
.imm64
)
6543 && !operand_type_equal (&overlap
, &imm8
)
6544 && !operand_type_equal (&overlap
, &imm8s
)
6545 && !operand_type_equal (&overlap
, &imm16
)
6546 && !operand_type_equal (&overlap
, &imm32
)
6547 && !operand_type_equal (&overlap
, &imm32s
)
6548 && !operand_type_equal (&overlap
, &imm64
))
6552 i386_operand_type temp
;
6554 operand_type_set (&temp
, 0);
6555 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
6557 temp
.bitfield
.imm8
= overlap
.bitfield
.imm8
;
6558 temp
.bitfield
.imm8s
= overlap
.bitfield
.imm8s
;
6560 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
6561 temp
.bitfield
.imm16
= overlap
.bitfield
.imm16
;
6562 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
6564 temp
.bitfield
.imm64
= overlap
.bitfield
.imm64
;
6565 temp
.bitfield
.imm32s
= overlap
.bitfield
.imm32s
;
6568 temp
.bitfield
.imm32
= overlap
.bitfield
.imm32
;
6571 else if (operand_type_equal (&overlap
, &imm16_32_32s
)
6572 || operand_type_equal (&overlap
, &imm16_32
)
6573 || operand_type_equal (&overlap
, &imm16_32s
))
6575 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
6580 if (!operand_type_equal (&overlap
, &imm8
)
6581 && !operand_type_equal (&overlap
, &imm8s
)
6582 && !operand_type_equal (&overlap
, &imm16
)
6583 && !operand_type_equal (&overlap
, &imm32
)
6584 && !operand_type_equal (&overlap
, &imm32s
)
6585 && !operand_type_equal (&overlap
, &imm64
))
6587 as_bad (_("no instruction mnemonic suffix given; "
6588 "can't determine immediate size"));
6592 i
.types
[j
] = overlap
;
6602 /* Update the first 2 immediate operands. */
6603 n
= i
.operands
> 2 ? 2 : i
.operands
;
6606 for (j
= 0; j
< n
; j
++)
6607 if (update_imm (j
) == 0)
6610 /* The 3rd operand can't be immediate operand. */
6611 gas_assert (operand_type_check (i
.types
[2], imm
) == 0);
6618 process_operands (void)
6620 /* Default segment register this instruction will use for memory
6621 accesses. 0 means unknown. This is only for optimizing out
6622 unnecessary segment overrides. */
6623 const seg_entry
*default_seg
= 0;
6625 if (i
.tm
.opcode_modifier
.sse2avx
&& i
.tm
.opcode_modifier
.vexvvvv
)
6627 unsigned int dupl
= i
.operands
;
6628 unsigned int dest
= dupl
- 1;
6631 /* The destination must be an xmm register. */
6632 gas_assert (i
.reg_operands
6633 && MAX_OPERANDS
> dupl
6634 && operand_type_equal (&i
.types
[dest
], ®xmm
));
6636 if (i
.tm
.operand_types
[0].bitfield
.acc
6637 && i
.tm
.operand_types
[0].bitfield
.xmmword
)
6639 if (i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
)
6641 /* Keep xmm0 for instructions with VEX prefix and 3
6643 i
.tm
.operand_types
[0].bitfield
.acc
= 0;
6644 i
.tm
.operand_types
[0].bitfield
.regsimd
= 1;
6649 /* We remove the first xmm0 and keep the number of
6650 operands unchanged, which in fact duplicates the
6652 for (j
= 1; j
< i
.operands
; j
++)
6654 i
.op
[j
- 1] = i
.op
[j
];
6655 i
.types
[j
- 1] = i
.types
[j
];
6656 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
6660 else if (i
.tm
.opcode_modifier
.implicit1stxmm0
)
6662 gas_assert ((MAX_OPERANDS
- 1) > dupl
6663 && (i
.tm
.opcode_modifier
.vexsources
6666 /* Add the implicit xmm0 for instructions with VEX prefix
6668 for (j
= i
.operands
; j
> 0; j
--)
6670 i
.op
[j
] = i
.op
[j
- 1];
6671 i
.types
[j
] = i
.types
[j
- 1];
6672 i
.tm
.operand_types
[j
] = i
.tm
.operand_types
[j
- 1];
6675 = (const reg_entry
*) hash_find (reg_hash
, "xmm0");
6676 i
.types
[0] = regxmm
;
6677 i
.tm
.operand_types
[0] = regxmm
;
6680 i
.reg_operands
+= 2;
6685 i
.op
[dupl
] = i
.op
[dest
];
6686 i
.types
[dupl
] = i
.types
[dest
];
6687 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
6696 i
.op
[dupl
] = i
.op
[dest
];
6697 i
.types
[dupl
] = i
.types
[dest
];
6698 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
6701 if (i
.tm
.opcode_modifier
.immext
)
6704 else if (i
.tm
.operand_types
[0].bitfield
.acc
6705 && i
.tm
.operand_types
[0].bitfield
.xmmword
)
6709 for (j
= 1; j
< i
.operands
; j
++)
6711 i
.op
[j
- 1] = i
.op
[j
];
6712 i
.types
[j
- 1] = i
.types
[j
];
6714 /* We need to adjust fields in i.tm since they are used by
6715 build_modrm_byte. */
6716 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
6723 else if (i
.tm
.opcode_modifier
.implicitquadgroup
)
6725 unsigned int regnum
, first_reg_in_group
, last_reg_in_group
;
6727 /* The second operand must be {x,y,z}mmN, where N is a multiple of 4. */
6728 gas_assert (i
.operands
>= 2 && i
.types
[1].bitfield
.regsimd
);
6729 regnum
= register_number (i
.op
[1].regs
);
6730 first_reg_in_group
= regnum
& ~3;
6731 last_reg_in_group
= first_reg_in_group
+ 3;
6732 if (regnum
!= first_reg_in_group
)
6733 as_warn (_("source register `%s%s' implicitly denotes"
6734 " `%s%.3s%u' to `%s%.3s%u' source group in `%s'"),
6735 register_prefix
, i
.op
[1].regs
->reg_name
,
6736 register_prefix
, i
.op
[1].regs
->reg_name
, first_reg_in_group
,
6737 register_prefix
, i
.op
[1].regs
->reg_name
, last_reg_in_group
,
6740 else if (i
.tm
.opcode_modifier
.regkludge
)
6742 /* The imul $imm, %reg instruction is converted into
6743 imul $imm, %reg, %reg, and the clr %reg instruction
6744 is converted into xor %reg, %reg. */
6746 unsigned int first_reg_op
;
6748 if (operand_type_check (i
.types
[0], reg
))
6752 /* Pretend we saw the extra register operand. */
6753 gas_assert (i
.reg_operands
== 1
6754 && i
.op
[first_reg_op
+ 1].regs
== 0);
6755 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
6756 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
6761 if (i
.tm
.opcode_modifier
.shortform
)
6763 if (i
.types
[0].bitfield
.sreg2
6764 || i
.types
[0].bitfield
.sreg3
)
6766 if (i
.tm
.base_opcode
== POP_SEG_SHORT
6767 && i
.op
[0].regs
->reg_num
== 1)
6769 as_bad (_("you can't `pop %scs'"), register_prefix
);
6772 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
6773 if ((i
.op
[0].regs
->reg_flags
& RegRex
) != 0)
6778 /* The register or float register operand is in operand
6782 if ((i
.types
[0].bitfield
.reg
&& i
.types
[0].bitfield
.tbyte
)
6783 || operand_type_check (i
.types
[0], reg
))
6787 /* Register goes in low 3 bits of opcode. */
6788 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
6789 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
6791 if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
6793 /* Warn about some common errors, but press on regardless.
6794 The first case can be generated by gcc (<= 2.8.1). */
6795 if (i
.operands
== 2)
6797 /* Reversed arguments on faddp, fsubp, etc. */
6798 as_warn (_("translating to `%s %s%s,%s%s'"), i
.tm
.name
,
6799 register_prefix
, i
.op
[!intel_syntax
].regs
->reg_name
,
6800 register_prefix
, i
.op
[intel_syntax
].regs
->reg_name
);
6804 /* Extraneous `l' suffix on fp insn. */
6805 as_warn (_("translating to `%s %s%s'"), i
.tm
.name
,
6806 register_prefix
, i
.op
[0].regs
->reg_name
);
6811 else if (i
.tm
.opcode_modifier
.modrm
)
6813 /* The opcode is completed (modulo i.tm.extension_opcode which
6814 must be put into the modrm byte). Now, we make the modrm and
6815 index base bytes based on all the info we've collected. */
6817 default_seg
= build_modrm_byte ();
6819 else if ((i
.tm
.base_opcode
& ~0x3) == MOV_AX_DISP32
)
6823 else if (i
.tm
.opcode_modifier
.isstring
)
6825 /* For the string instructions that allow a segment override
6826 on one of their operands, the default segment is ds. */
6830 if (i
.tm
.base_opcode
== 0x8d /* lea */
6833 as_warn (_("segment override on `%s' is ineffectual"), i
.tm
.name
);
6835 /* If a segment was explicitly specified, and the specified segment
6836 is not the default, use an opcode prefix to select it. If we
6837 never figured out what the default segment is, then default_seg
6838 will be zero at this point, and the specified segment prefix will
6840 if ((i
.seg
[0]) && (i
.seg
[0] != default_seg
))
6842 if (!add_prefix (i
.seg
[0]->seg_prefix
))
6848 static const seg_entry
*
6849 build_modrm_byte (void)
6851 const seg_entry
*default_seg
= 0;
6852 unsigned int source
, dest
;
6855 vex_3_sources
= i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
;
6858 unsigned int nds
, reg_slot
;
6861 dest
= i
.operands
- 1;
6864 /* There are 2 kinds of instructions:
6865 1. 5 operands: 4 register operands or 3 register operands
6866 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
6867 VexW0 or VexW1. The destination must be either XMM, YMM or
6869 2. 4 operands: 4 register operands or 3 register operands
6870 plus 1 memory operand, with VexXDS. */
6871 gas_assert ((i
.reg_operands
== 4
6872 || (i
.reg_operands
== 3 && i
.mem_operands
== 1))
6873 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
6874 && i
.tm
.opcode_modifier
.vexw
6875 && i
.tm
.operand_types
[dest
].bitfield
.regsimd
);
6877 /* If VexW1 is set, the first non-immediate operand is the source and
6878 the second non-immediate one is encoded in the immediate operand. */
6879 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
6881 source
= i
.imm_operands
;
6882 reg_slot
= i
.imm_operands
+ 1;
6886 source
= i
.imm_operands
+ 1;
6887 reg_slot
= i
.imm_operands
;
6890 if (i
.imm_operands
== 0)
6892 /* When there is no immediate operand, generate an 8bit
6893 immediate operand to encode the first operand. */
6894 exp
= &im_expressions
[i
.imm_operands
++];
6895 i
.op
[i
.operands
].imms
= exp
;
6896 i
.types
[i
.operands
] = imm8
;
6899 gas_assert (i
.tm
.operand_types
[reg_slot
].bitfield
.regsimd
);
6900 exp
->X_op
= O_constant
;
6901 exp
->X_add_number
= register_number (i
.op
[reg_slot
].regs
) << 4;
6902 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
6906 unsigned int imm_slot
;
6908 gas_assert (i
.imm_operands
== 1 && i
.types
[0].bitfield
.vec_imm4
);
6910 if (i
.tm
.opcode_modifier
.immext
)
6912 /* When ImmExt is set, the immediate byte is the last
6914 imm_slot
= i
.operands
- 1;
6922 /* Turn on Imm8 so that output_imm will generate it. */
6923 i
.types
[imm_slot
].bitfield
.imm8
= 1;
6926 gas_assert (i
.tm
.operand_types
[reg_slot
].bitfield
.regsimd
);
6927 i
.op
[imm_slot
].imms
->X_add_number
6928 |= register_number (i
.op
[reg_slot
].regs
) << 4;
6929 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
6932 gas_assert (i
.tm
.operand_types
[nds
].bitfield
.regsimd
);
6933 i
.vex
.register_specifier
= i
.op
[nds
].regs
;
6938 /* i.reg_operands MUST be the number of real register operands;
6939 implicit registers do not count. If there are 3 register
6940 operands, it must be a instruction with VexNDS. For a
6941 instruction with VexNDD, the destination register is encoded
6942 in VEX prefix. If there are 4 register operands, it must be
6943 a instruction with VEX prefix and 3 sources. */
6944 if (i
.mem_operands
== 0
6945 && ((i
.reg_operands
== 2
6946 && i
.tm
.opcode_modifier
.vexvvvv
<= VEXXDS
)
6947 || (i
.reg_operands
== 3
6948 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
6949 || (i
.reg_operands
== 4 && vex_3_sources
)))
6957 /* When there are 3 operands, one of them may be immediate,
6958 which may be the first or the last operand. Otherwise,
6959 the first operand must be shift count register (cl) or it
6960 is an instruction with VexNDS. */
6961 gas_assert (i
.imm_operands
== 1
6962 || (i
.imm_operands
== 0
6963 && (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
6964 || i
.types
[0].bitfield
.shiftcount
)));
6965 if (operand_type_check (i
.types
[0], imm
)
6966 || i
.types
[0].bitfield
.shiftcount
)
6972 /* When there are 4 operands, the first two must be 8bit
6973 immediate operands. The source operand will be the 3rd
6976 For instructions with VexNDS, if the first operand
6977 an imm8, the source operand is the 2nd one. If the last
6978 operand is imm8, the source operand is the first one. */
6979 gas_assert ((i
.imm_operands
== 2
6980 && i
.types
[0].bitfield
.imm8
6981 && i
.types
[1].bitfield
.imm8
)
6982 || (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
6983 && i
.imm_operands
== 1
6984 && (i
.types
[0].bitfield
.imm8
6985 || i
.types
[i
.operands
- 1].bitfield
.imm8
6987 if (i
.imm_operands
== 2)
6991 if (i
.types
[0].bitfield
.imm8
)
6998 if (is_evex_encoding (&i
.tm
))
7000 /* For EVEX instructions, when there are 5 operands, the
7001 first one must be immediate operand. If the second one
7002 is immediate operand, the source operand is the 3th
7003 one. If the last one is immediate operand, the source
7004 operand is the 2nd one. */
7005 gas_assert (i
.imm_operands
== 2
7006 && i
.tm
.opcode_modifier
.sae
7007 && operand_type_check (i
.types
[0], imm
));
7008 if (operand_type_check (i
.types
[1], imm
))
7010 else if (operand_type_check (i
.types
[4], imm
))
7024 /* RC/SAE operand could be between DEST and SRC. That happens
7025 when one operand is GPR and the other one is XMM/YMM/ZMM
7027 if (i
.rounding
&& i
.rounding
->operand
== (int) dest
)
7030 if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
7032 /* For instructions with VexNDS, the register-only source
7033 operand must be a 32/64bit integer, XMM, YMM, ZMM, or mask
7034 register. It is encoded in VEX prefix. We need to
7035 clear RegMem bit before calling operand_type_equal. */
7037 i386_operand_type op
;
7040 /* Check register-only source operand when two source
7041 operands are swapped. */
7042 if (!i
.tm
.operand_types
[source
].bitfield
.baseindex
7043 && i
.tm
.operand_types
[dest
].bitfield
.baseindex
)
7051 op
= i
.tm
.operand_types
[vvvv
];
7052 op
.bitfield
.regmem
= 0;
7053 if ((dest
+ 1) >= i
.operands
7054 || ((!op
.bitfield
.reg
7055 || (!op
.bitfield
.dword
&& !op
.bitfield
.qword
))
7056 && !op
.bitfield
.regsimd
7057 && !operand_type_equal (&op
, ®mask
)))
7059 i
.vex
.register_specifier
= i
.op
[vvvv
].regs
;
7065 /* One of the register operands will be encoded in the i.tm.reg
7066 field, the other in the combined i.tm.mode and i.tm.regmem
7067 fields. If no form of this instruction supports a memory
7068 destination operand, then we assume the source operand may
7069 sometimes be a memory operand and so we need to store the
7070 destination in the i.rm.reg field. */
7071 if (!i
.tm
.operand_types
[dest
].bitfield
.regmem
7072 && operand_type_check (i
.tm
.operand_types
[dest
], anymem
) == 0)
7074 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
7075 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
7076 if (i
.op
[dest
].regs
->reg_type
.bitfield
.regmmx
7077 || i
.op
[source
].regs
->reg_type
.bitfield
.regmmx
)
7078 i
.has_regmmx
= TRUE
;
7079 else if (i
.op
[dest
].regs
->reg_type
.bitfield
.regsimd
7080 || i
.op
[source
].regs
->reg_type
.bitfield
.regsimd
)
7082 if (i
.types
[dest
].bitfield
.zmmword
7083 || i
.types
[source
].bitfield
.zmmword
)
7084 i
.has_regzmm
= TRUE
;
7085 else if (i
.types
[dest
].bitfield
.ymmword
7086 || i
.types
[source
].bitfield
.ymmword
)
7087 i
.has_regymm
= TRUE
;
7089 i
.has_regxmm
= TRUE
;
7091 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
7093 if ((i
.op
[dest
].regs
->reg_flags
& RegVRex
) != 0)
7095 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
7097 if ((i
.op
[source
].regs
->reg_flags
& RegVRex
) != 0)
7102 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
7103 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
7104 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
7106 if ((i
.op
[dest
].regs
->reg_flags
& RegVRex
) != 0)
7108 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
7110 if ((i
.op
[source
].regs
->reg_flags
& RegVRex
) != 0)
7113 if (flag_code
!= CODE_64BIT
&& (i
.rex
& REX_R
))
7115 if (!i
.types
[i
.tm
.operand_types
[0].bitfield
.regmem
].bitfield
.control
)
7118 add_prefix (LOCK_PREFIX_OPCODE
);
7122 { /* If it's not 2 reg operands... */
7127 unsigned int fake_zero_displacement
= 0;
7130 for (op
= 0; op
< i
.operands
; op
++)
7131 if (operand_type_check (i
.types
[op
], anymem
))
7133 gas_assert (op
< i
.operands
);
7135 if (i
.tm
.opcode_modifier
.vecsib
)
7137 if (i
.index_reg
->reg_num
== RegIZ
)
7140 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
7143 i
.sib
.base
= NO_BASE_REGISTER
;
7144 i
.sib
.scale
= i
.log2_scale_factor
;
7145 i
.types
[op
].bitfield
.disp8
= 0;
7146 i
.types
[op
].bitfield
.disp16
= 0;
7147 i
.types
[op
].bitfield
.disp64
= 0;
7148 if (flag_code
!= CODE_64BIT
|| i
.prefix
[ADDR_PREFIX
])
7150 /* Must be 32 bit */
7151 i
.types
[op
].bitfield
.disp32
= 1;
7152 i
.types
[op
].bitfield
.disp32s
= 0;
7156 i
.types
[op
].bitfield
.disp32
= 0;
7157 i
.types
[op
].bitfield
.disp32s
= 1;
7160 i
.sib
.index
= i
.index_reg
->reg_num
;
7161 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
7163 if ((i
.index_reg
->reg_flags
& RegVRex
) != 0)
7169 if (i
.base_reg
== 0)
7172 if (!i
.disp_operands
)
7173 fake_zero_displacement
= 1;
7174 if (i
.index_reg
== 0)
7176 i386_operand_type newdisp
;
7178 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
7179 /* Operand is just <disp> */
7180 if (flag_code
== CODE_64BIT
)
7182 /* 64bit mode overwrites the 32bit absolute
7183 addressing by RIP relative addressing and
7184 absolute addressing is encoded by one of the
7185 redundant SIB forms. */
7186 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
7187 i
.sib
.base
= NO_BASE_REGISTER
;
7188 i
.sib
.index
= NO_INDEX_REGISTER
;
7189 newdisp
= (!i
.prefix
[ADDR_PREFIX
] ? disp32s
: disp32
);
7191 else if ((flag_code
== CODE_16BIT
)
7192 ^ (i
.prefix
[ADDR_PREFIX
] != 0))
7194 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
7199 i
.rm
.regmem
= NO_BASE_REGISTER
;
7202 i
.types
[op
] = operand_type_and_not (i
.types
[op
], anydisp
);
7203 i
.types
[op
] = operand_type_or (i
.types
[op
], newdisp
);
7205 else if (!i
.tm
.opcode_modifier
.vecsib
)
7207 /* !i.base_reg && i.index_reg */
7208 if (i
.index_reg
->reg_num
== RegIZ
)
7209 i
.sib
.index
= NO_INDEX_REGISTER
;
7211 i
.sib
.index
= i
.index_reg
->reg_num
;
7212 i
.sib
.base
= NO_BASE_REGISTER
;
7213 i
.sib
.scale
= i
.log2_scale_factor
;
7214 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
7215 i
.types
[op
].bitfield
.disp8
= 0;
7216 i
.types
[op
].bitfield
.disp16
= 0;
7217 i
.types
[op
].bitfield
.disp64
= 0;
7218 if (flag_code
!= CODE_64BIT
|| i
.prefix
[ADDR_PREFIX
])
7220 /* Must be 32 bit */
7221 i
.types
[op
].bitfield
.disp32
= 1;
7222 i
.types
[op
].bitfield
.disp32s
= 0;
7226 i
.types
[op
].bitfield
.disp32
= 0;
7227 i
.types
[op
].bitfield
.disp32s
= 1;
7229 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
7233 /* RIP addressing for 64bit mode. */
7234 else if (i
.base_reg
->reg_num
== RegIP
)
7236 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
7237 i
.rm
.regmem
= NO_BASE_REGISTER
;
7238 i
.types
[op
].bitfield
.disp8
= 0;
7239 i
.types
[op
].bitfield
.disp16
= 0;
7240 i
.types
[op
].bitfield
.disp32
= 0;
7241 i
.types
[op
].bitfield
.disp32s
= 1;
7242 i
.types
[op
].bitfield
.disp64
= 0;
7243 i
.flags
[op
] |= Operand_PCrel
;
7244 if (! i
.disp_operands
)
7245 fake_zero_displacement
= 1;
7247 else if (i
.base_reg
->reg_type
.bitfield
.word
)
7249 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
7250 switch (i
.base_reg
->reg_num
)
7253 if (i
.index_reg
== 0)
7255 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
7256 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
7260 if (i
.index_reg
== 0)
7263 if (operand_type_check (i
.types
[op
], disp
) == 0)
7265 /* fake (%bp) into 0(%bp) */
7266 i
.types
[op
].bitfield
.disp8
= 1;
7267 fake_zero_displacement
= 1;
7270 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
7271 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
7273 default: /* (%si) -> 4 or (%di) -> 5 */
7274 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
7276 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
7278 else /* i.base_reg and 32/64 bit mode */
7280 if (flag_code
== CODE_64BIT
7281 && operand_type_check (i
.types
[op
], disp
))
7283 i
.types
[op
].bitfield
.disp16
= 0;
7284 i
.types
[op
].bitfield
.disp64
= 0;
7285 if (i
.prefix
[ADDR_PREFIX
] == 0)
7287 i
.types
[op
].bitfield
.disp32
= 0;
7288 i
.types
[op
].bitfield
.disp32s
= 1;
7292 i
.types
[op
].bitfield
.disp32
= 1;
7293 i
.types
[op
].bitfield
.disp32s
= 0;
7297 if (!i
.tm
.opcode_modifier
.vecsib
)
7298 i
.rm
.regmem
= i
.base_reg
->reg_num
;
7299 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
7301 i
.sib
.base
= i
.base_reg
->reg_num
;
7302 /* x86-64 ignores REX prefix bit here to avoid decoder
7304 if (!(i
.base_reg
->reg_flags
& RegRex
)
7305 && (i
.base_reg
->reg_num
== EBP_REG_NUM
7306 || i
.base_reg
->reg_num
== ESP_REG_NUM
))
7308 if (i
.base_reg
->reg_num
== 5 && i
.disp_operands
== 0)
7310 fake_zero_displacement
= 1;
7311 i
.types
[op
].bitfield
.disp8
= 1;
7313 i
.sib
.scale
= i
.log2_scale_factor
;
7314 if (i
.index_reg
== 0)
7316 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
7317 /* <disp>(%esp) becomes two byte modrm with no index
7318 register. We've already stored the code for esp
7319 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
7320 Any base register besides %esp will not use the
7321 extra modrm byte. */
7322 i
.sib
.index
= NO_INDEX_REGISTER
;
7324 else if (!i
.tm
.opcode_modifier
.vecsib
)
7326 if (i
.index_reg
->reg_num
== RegIZ
)
7327 i
.sib
.index
= NO_INDEX_REGISTER
;
7329 i
.sib
.index
= i
.index_reg
->reg_num
;
7330 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
7331 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
7336 && (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
7337 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
))
7341 if (!fake_zero_displacement
7345 fake_zero_displacement
= 1;
7346 if (i
.disp_encoding
== disp_encoding_8bit
)
7347 i
.types
[op
].bitfield
.disp8
= 1;
7349 i
.types
[op
].bitfield
.disp32
= 1;
7351 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
7355 if (fake_zero_displacement
)
7357 /* Fakes a zero displacement assuming that i.types[op]
7358 holds the correct displacement size. */
7361 gas_assert (i
.op
[op
].disps
== 0);
7362 exp
= &disp_expressions
[i
.disp_operands
++];
7363 i
.op
[op
].disps
= exp
;
7364 exp
->X_op
= O_constant
;
7365 exp
->X_add_number
= 0;
7366 exp
->X_add_symbol
= (symbolS
*) 0;
7367 exp
->X_op_symbol
= (symbolS
*) 0;
7375 if (i
.tm
.opcode_modifier
.vexsources
== XOP2SOURCES
)
7377 if (operand_type_check (i
.types
[0], imm
))
7378 i
.vex
.register_specifier
= NULL
;
7381 /* VEX.vvvv encodes one of the sources when the first
7382 operand is not an immediate. */
7383 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
7384 i
.vex
.register_specifier
= i
.op
[0].regs
;
7386 i
.vex
.register_specifier
= i
.op
[1].regs
;
7389 /* Destination is a XMM register encoded in the ModRM.reg
7391 i
.rm
.reg
= i
.op
[2].regs
->reg_num
;
7392 if ((i
.op
[2].regs
->reg_flags
& RegRex
) != 0)
7395 /* ModRM.rm and VEX.B encodes the other source. */
7396 if (!i
.mem_operands
)
7400 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
7401 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
7403 i
.rm
.regmem
= i
.op
[0].regs
->reg_num
;
7405 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
7409 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXLWP
)
7411 i
.vex
.register_specifier
= i
.op
[2].regs
;
7412 if (!i
.mem_operands
)
7415 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
7416 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
7420 /* Fill in i.rm.reg or i.rm.regmem field with register operand
7421 (if any) based on i.tm.extension_opcode. Again, we must be
7422 careful to make sure that segment/control/debug/test/MMX
7423 registers are coded into the i.rm.reg field. */
7424 else if (i
.reg_operands
)
7427 unsigned int vex_reg
= ~0;
7429 for (op
= 0; op
< i
.operands
; op
++)
7431 if (i
.types
[op
].bitfield
.reg
7432 || i
.types
[op
].bitfield
.regbnd
7433 || i
.types
[op
].bitfield
.regmask
7434 || i
.types
[op
].bitfield
.sreg2
7435 || i
.types
[op
].bitfield
.sreg3
7436 || i
.types
[op
].bitfield
.control
7437 || i
.types
[op
].bitfield
.debug
7438 || i
.types
[op
].bitfield
.test
)
7440 if (i
.types
[op
].bitfield
.regsimd
)
7442 if (i
.types
[op
].bitfield
.zmmword
)
7443 i
.has_regzmm
= TRUE
;
7444 else if (i
.types
[op
].bitfield
.ymmword
)
7445 i
.has_regymm
= TRUE
;
7447 i
.has_regxmm
= TRUE
;
7450 if (i
.types
[op
].bitfield
.regmmx
)
7452 i
.has_regmmx
= TRUE
;
7459 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
7461 /* For instructions with VexNDS, the register-only
7462 source operand is encoded in VEX prefix. */
7463 gas_assert (mem
!= (unsigned int) ~0);
7468 gas_assert (op
< i
.operands
);
7472 /* Check register-only source operand when two source
7473 operands are swapped. */
7474 if (!i
.tm
.operand_types
[op
].bitfield
.baseindex
7475 && i
.tm
.operand_types
[op
+ 1].bitfield
.baseindex
)
7479 gas_assert (mem
== (vex_reg
+ 1)
7480 && op
< i
.operands
);
7485 gas_assert (vex_reg
< i
.operands
);
7489 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXNDD
)
7491 /* For instructions with VexNDD, the register destination
7492 is encoded in VEX prefix. */
7493 if (i
.mem_operands
== 0)
7495 /* There is no memory operand. */
7496 gas_assert ((op
+ 2) == i
.operands
);
7501 /* There are only 2 non-immediate operands. */
7502 gas_assert (op
< i
.imm_operands
+ 2
7503 && i
.operands
== i
.imm_operands
+ 2);
7504 vex_reg
= i
.imm_operands
+ 1;
7508 gas_assert (op
< i
.operands
);
7510 if (vex_reg
!= (unsigned int) ~0)
7512 i386_operand_type
*type
= &i
.tm
.operand_types
[vex_reg
];
7514 if ((!type
->bitfield
.reg
7515 || (!type
->bitfield
.dword
&& !type
->bitfield
.qword
))
7516 && !type
->bitfield
.regsimd
7517 && !operand_type_equal (type
, ®mask
))
7520 i
.vex
.register_specifier
= i
.op
[vex_reg
].regs
;
7523 /* Don't set OP operand twice. */
7526 /* If there is an extension opcode to put here, the
7527 register number must be put into the regmem field. */
7528 if (i
.tm
.extension_opcode
!= None
)
7530 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
7531 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
7533 if ((i
.op
[op
].regs
->reg_flags
& RegVRex
) != 0)
7538 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
7539 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
7541 if ((i
.op
[op
].regs
->reg_flags
& RegVRex
) != 0)
7546 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
7547 must set it to 3 to indicate this is a register operand
7548 in the regmem field. */
7549 if (!i
.mem_operands
)
7553 /* Fill in i.rm.reg field with extension opcode (if any). */
7554 if (i
.tm
.extension_opcode
!= None
)
7555 i
.rm
.reg
= i
.tm
.extension_opcode
;
7561 output_branch (void)
7567 relax_substateT subtype
;
7571 code16
= flag_code
== CODE_16BIT
? CODE16
: 0;
7572 size
= i
.disp_encoding
== disp_encoding_32bit
? BIG
: SMALL
;
7575 if (i
.prefix
[DATA_PREFIX
] != 0)
7581 /* Pentium4 branch hints. */
7582 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
7583 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
7588 if (i
.prefix
[REX_PREFIX
] != 0)
7594 /* BND prefixed jump. */
7595 if (i
.prefix
[BND_PREFIX
] != 0)
7597 FRAG_APPEND_1_CHAR (i
.prefix
[BND_PREFIX
]);
7601 if (i
.prefixes
!= 0 && !intel_syntax
)
7602 as_warn (_("skipping prefixes on this instruction"));
7604 /* It's always a symbol; End frag & setup for relax.
7605 Make sure there is enough room in this frag for the largest
7606 instruction we may generate in md_convert_frag. This is 2
7607 bytes for the opcode and room for the prefix and largest
7609 frag_grow (prefix
+ 2 + 4);
7610 /* Prefix and 1 opcode byte go in fr_fix. */
7611 p
= frag_more (prefix
+ 1);
7612 if (i
.prefix
[DATA_PREFIX
] != 0)
7613 *p
++ = DATA_PREFIX_OPCODE
;
7614 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
7615 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
7616 *p
++ = i
.prefix
[SEG_PREFIX
];
7617 if (i
.prefix
[REX_PREFIX
] != 0)
7618 *p
++ = i
.prefix
[REX_PREFIX
];
7619 *p
= i
.tm
.base_opcode
;
7621 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
7622 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, size
);
7623 else if (cpu_arch_flags
.bitfield
.cpui386
)
7624 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, size
);
7626 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, size
);
7629 sym
= i
.op
[0].disps
->X_add_symbol
;
7630 off
= i
.op
[0].disps
->X_add_number
;
7632 if (i
.op
[0].disps
->X_op
!= O_constant
7633 && i
.op
[0].disps
->X_op
!= O_symbol
)
7635 /* Handle complex expressions. */
7636 sym
= make_expr_symbol (i
.op
[0].disps
);
7640 /* 1 possible extra opcode + 4 byte displacement go in var part.
7641 Pass reloc in fr_var. */
7642 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
7645 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7646 /* Return TRUE iff PLT32 relocation should be used for branching to
7650 need_plt32_p (symbolS
*s
)
7652 /* PLT32 relocation is ELF only. */
7656 /* Since there is no need to prepare for PLT branch on x86-64, we
7657 can generate R_X86_64_PLT32, instead of R_X86_64_PC32, which can
7658 be used as a marker for 32-bit PC-relative branches. */
7662 /* Weak or undefined symbol need PLT32 relocation. */
7663 if (S_IS_WEAK (s
) || !S_IS_DEFINED (s
))
7666 /* Non-global symbol doesn't need PLT32 relocation. */
7667 if (! S_IS_EXTERNAL (s
))
7670 /* Other global symbols need PLT32 relocation. NB: Symbol with
7671 non-default visibilities are treated as normal global symbol
7672 so that PLT32 relocation can be used as a marker for 32-bit
7673 PC-relative branches. It is useful for linker relaxation. */
7684 bfd_reloc_code_real_type jump_reloc
= i
.reloc
[0];
7686 if (i
.tm
.opcode_modifier
.jumpbyte
)
7688 /* This is a loop or jecxz type instruction. */
7690 if (i
.prefix
[ADDR_PREFIX
] != 0)
7692 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
7695 /* Pentium4 branch hints. */
7696 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
7697 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
7699 FRAG_APPEND_1_CHAR (i
.prefix
[SEG_PREFIX
]);
7708 if (flag_code
== CODE_16BIT
)
7711 if (i
.prefix
[DATA_PREFIX
] != 0)
7713 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
7723 if (i
.prefix
[REX_PREFIX
] != 0)
7725 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
7729 /* BND prefixed jump. */
7730 if (i
.prefix
[BND_PREFIX
] != 0)
7732 FRAG_APPEND_1_CHAR (i
.prefix
[BND_PREFIX
]);
7736 if (i
.prefixes
!= 0 && !intel_syntax
)
7737 as_warn (_("skipping prefixes on this instruction"));
7739 p
= frag_more (i
.tm
.opcode_length
+ size
);
7740 switch (i
.tm
.opcode_length
)
7743 *p
++ = i
.tm
.base_opcode
>> 8;
7746 *p
++ = i
.tm
.base_opcode
;
7752 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7754 && jump_reloc
== NO_RELOC
7755 && need_plt32_p (i
.op
[0].disps
->X_add_symbol
))
7756 jump_reloc
= BFD_RELOC_X86_64_PLT32
;
7759 jump_reloc
= reloc (size
, 1, 1, jump_reloc
);
7761 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
7762 i
.op
[0].disps
, 1, jump_reloc
);
7764 /* All jumps handled here are signed, but don't use a signed limit
7765 check for 32 and 16 bit jumps as we want to allow wrap around at
7766 4G and 64k respectively. */
7768 fixP
->fx_signed
= 1;
7772 output_interseg_jump (void)
7780 if (flag_code
== CODE_16BIT
)
7784 if (i
.prefix
[DATA_PREFIX
] != 0)
7790 if (i
.prefix
[REX_PREFIX
] != 0)
7800 if (i
.prefixes
!= 0 && !intel_syntax
)
7801 as_warn (_("skipping prefixes on this instruction"));
7803 /* 1 opcode; 2 segment; offset */
7804 p
= frag_more (prefix
+ 1 + 2 + size
);
7806 if (i
.prefix
[DATA_PREFIX
] != 0)
7807 *p
++ = DATA_PREFIX_OPCODE
;
7809 if (i
.prefix
[REX_PREFIX
] != 0)
7810 *p
++ = i
.prefix
[REX_PREFIX
];
7812 *p
++ = i
.tm
.base_opcode
;
7813 if (i
.op
[1].imms
->X_op
== O_constant
)
7815 offsetT n
= i
.op
[1].imms
->X_add_number
;
7818 && !fits_in_unsigned_word (n
)
7819 && !fits_in_signed_word (n
))
7821 as_bad (_("16-bit jump out of range"));
7824 md_number_to_chars (p
, n
, size
);
7827 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
7828 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
7829 if (i
.op
[0].imms
->X_op
!= O_constant
)
7830 as_bad (_("can't handle non absolute segment in `%s'"),
7832 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
7835 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7840 asection
*seg
= now_seg
;
7841 subsegT subseg
= now_subseg
;
7843 unsigned int alignment
, align_size_1
;
7844 unsigned int isa_1_descsz
, feature_2_descsz
, descsz
;
7845 unsigned int isa_1_descsz_raw
, feature_2_descsz_raw
;
7846 unsigned int padding
;
7848 if (!IS_ELF
|| !x86_used_note
)
7851 x86_isa_1_used
|= GNU_PROPERTY_X86_UINT32_VALID
;
7852 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_X86
;
7854 /* The .note.gnu.property section layout:
7856 Field Length Contents
7859 n_descsz 4 The note descriptor size
7860 n_type 4 NT_GNU_PROPERTY_TYPE_0
7862 n_desc n_descsz The program property array
7866 /* Create the .note.gnu.property section. */
7867 sec
= subseg_new (NOTE_GNU_PROPERTY_SECTION_NAME
, 0);
7868 bfd_set_section_flags (stdoutput
, sec
,
7875 if (get_elf_backend_data (stdoutput
)->s
->elfclass
== ELFCLASS64
)
7886 bfd_set_section_alignment (stdoutput
, sec
, alignment
);
7887 elf_section_type (sec
) = SHT_NOTE
;
7889 /* GNU_PROPERTY_X86_ISA_1_USED: 4-byte type + 4-byte data size
7891 isa_1_descsz_raw
= 4 + 4 + 4;
7892 /* Align GNU_PROPERTY_X86_ISA_1_USED. */
7893 isa_1_descsz
= (isa_1_descsz_raw
+ align_size_1
) & ~align_size_1
;
7895 feature_2_descsz_raw
= isa_1_descsz
;
7896 /* GNU_PROPERTY_X86_FEATURE_2_USED: 4-byte type + 4-byte data size
7898 feature_2_descsz_raw
+= 4 + 4 + 4;
7899 /* Align GNU_PROPERTY_X86_FEATURE_2_USED. */
7900 feature_2_descsz
= ((feature_2_descsz_raw
+ align_size_1
)
7903 descsz
= feature_2_descsz
;
7904 /* Section size: n_namsz + n_descsz + n_type + n_name + n_descsz. */
7905 p
= frag_more (4 + 4 + 4 + 4 + descsz
);
7907 /* Write n_namsz. */
7908 md_number_to_chars (p
, (valueT
) 4, 4);
7910 /* Write n_descsz. */
7911 md_number_to_chars (p
+ 4, (valueT
) descsz
, 4);
7914 md_number_to_chars (p
+ 4 * 2, (valueT
) NT_GNU_PROPERTY_TYPE_0
, 4);
7917 memcpy (p
+ 4 * 3, "GNU", 4);
7919 /* Write 4-byte type. */
7920 md_number_to_chars (p
+ 4 * 4,
7921 (valueT
) GNU_PROPERTY_X86_ISA_1_USED
, 4);
7923 /* Write 4-byte data size. */
7924 md_number_to_chars (p
+ 4 * 5, (valueT
) 4, 4);
7926 /* Write 4-byte data. */
7927 md_number_to_chars (p
+ 4 * 6, (valueT
) x86_isa_1_used
, 4);
7929 /* Zero out paddings. */
7930 padding
= isa_1_descsz
- isa_1_descsz_raw
;
7932 memset (p
+ 4 * 7, 0, padding
);
7934 /* Write 4-byte type. */
7935 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 4,
7936 (valueT
) GNU_PROPERTY_X86_FEATURE_2_USED
, 4);
7938 /* Write 4-byte data size. */
7939 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 5, (valueT
) 4, 4);
7941 /* Write 4-byte data. */
7942 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 6,
7943 (valueT
) x86_feature_2_used
, 4);
7945 /* Zero out paddings. */
7946 padding
= feature_2_descsz
- feature_2_descsz_raw
;
7948 memset (p
+ isa_1_descsz
+ 4 * 7, 0, padding
);
7950 /* We probably can't restore the current segment, for there likely
7953 subseg_set (seg
, subseg
);
7960 fragS
*insn_start_frag
;
7961 offsetT insn_start_off
;
7963 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7964 if (IS_ELF
&& x86_used_note
)
7966 if (i
.tm
.cpu_flags
.bitfield
.cpucmov
)
7967 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_CMOV
;
7968 if (i
.tm
.cpu_flags
.bitfield
.cpusse
)
7969 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE
;
7970 if (i
.tm
.cpu_flags
.bitfield
.cpusse2
)
7971 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE2
;
7972 if (i
.tm
.cpu_flags
.bitfield
.cpusse3
)
7973 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE3
;
7974 if (i
.tm
.cpu_flags
.bitfield
.cpussse3
)
7975 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSSE3
;
7976 if (i
.tm
.cpu_flags
.bitfield
.cpusse4_1
)
7977 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE4_1
;
7978 if (i
.tm
.cpu_flags
.bitfield
.cpusse4_2
)
7979 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE4_2
;
7980 if (i
.tm
.cpu_flags
.bitfield
.cpuavx
)
7981 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX
;
7982 if (i
.tm
.cpu_flags
.bitfield
.cpuavx2
)
7983 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX2
;
7984 if (i
.tm
.cpu_flags
.bitfield
.cpufma
)
7985 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_FMA
;
7986 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512f
)
7987 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512F
;
7988 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512cd
)
7989 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512CD
;
7990 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512er
)
7991 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512ER
;
7992 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512pf
)
7993 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512PF
;
7994 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512vl
)
7995 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512VL
;
7996 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512dq
)
7997 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512DQ
;
7998 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512bw
)
7999 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512BW
;
8000 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_4fmaps
)
8001 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_4FMAPS
;
8002 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_4vnniw
)
8003 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_4VNNIW
;
8004 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_bitalg
)
8005 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_BITALG
;
8006 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512ifma
)
8007 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_IFMA
;
8008 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512vbmi
)
8009 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_VBMI
;
8010 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_vbmi2
)
8011 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_VBMI2
;
8012 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_vnni
)
8013 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_VNNI
;
8015 if (i
.tm
.cpu_flags
.bitfield
.cpu8087
8016 || i
.tm
.cpu_flags
.bitfield
.cpu287
8017 || i
.tm
.cpu_flags
.bitfield
.cpu387
8018 || i
.tm
.cpu_flags
.bitfield
.cpu687
8019 || i
.tm
.cpu_flags
.bitfield
.cpufisttp
)
8020 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_X87
;
8021 /* Don't set GNU_PROPERTY_X86_FEATURE_2_MMX for prefetchtXXX nor
8022 Xfence instructions. */
8023 if (i
.tm
.base_opcode
!= 0xf18
8024 && i
.tm
.base_opcode
!= 0xf0d
8025 && i
.tm
.base_opcode
!= 0xfae
8027 || i
.tm
.cpu_flags
.bitfield
.cpummx
8028 || i
.tm
.cpu_flags
.bitfield
.cpua3dnow
8029 || i
.tm
.cpu_flags
.bitfield
.cpua3dnowa
))
8030 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_MMX
;
8032 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XMM
;
8034 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_YMM
;
8036 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_ZMM
;
8037 if (i
.tm
.cpu_flags
.bitfield
.cpufxsr
)
8038 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_FXSR
;
8039 if (i
.tm
.cpu_flags
.bitfield
.cpuxsave
)
8040 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVE
;
8041 if (i
.tm
.cpu_flags
.bitfield
.cpuxsaveopt
)
8042 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVEOPT
;
8043 if (i
.tm
.cpu_flags
.bitfield
.cpuxsavec
)
8044 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVEC
;
8048 /* Tie dwarf2 debug info to the address at the start of the insn.
8049 We can't do this after the insn has been output as the current
8050 frag may have been closed off. eg. by frag_var. */
8051 dwarf2_emit_insn (0);
8053 insn_start_frag
= frag_now
;
8054 insn_start_off
= frag_now_fix ();
8057 if (i
.tm
.opcode_modifier
.jump
)
8059 else if (i
.tm
.opcode_modifier
.jumpbyte
8060 || i
.tm
.opcode_modifier
.jumpdword
)
8062 else if (i
.tm
.opcode_modifier
.jumpintersegment
)
8063 output_interseg_jump ();
8066 /* Output normal instructions here. */
8070 unsigned int prefix
;
8073 && i
.tm
.base_opcode
== 0xfae
8075 && i
.imm_operands
== 1
8076 && (i
.op
[0].imms
->X_add_number
== 0xe8
8077 || i
.op
[0].imms
->X_add_number
== 0xf0
8078 || i
.op
[0].imms
->X_add_number
== 0xf8))
8080 /* Encode lfence, mfence, and sfence as
8081 f0 83 04 24 00 lock addl $0x0, (%{re}sp). */
8082 offsetT val
= 0x240483f0ULL
;
8084 md_number_to_chars (p
, val
, 5);
8088 /* Some processors fail on LOCK prefix. This options makes
8089 assembler ignore LOCK prefix and serves as a workaround. */
8090 if (omit_lock_prefix
)
8092 if (i
.tm
.base_opcode
== LOCK_PREFIX_OPCODE
)
8094 i
.prefix
[LOCK_PREFIX
] = 0;
8097 /* Since the VEX/EVEX prefix contains the implicit prefix, we
8098 don't need the explicit prefix. */
8099 if (!i
.tm
.opcode_modifier
.vex
&& !i
.tm
.opcode_modifier
.evex
)
8101 switch (i
.tm
.opcode_length
)
8104 if (i
.tm
.base_opcode
& 0xff000000)
8106 prefix
= (i
.tm
.base_opcode
>> 24) & 0xff;
8107 add_prefix (prefix
);
8111 if ((i
.tm
.base_opcode
& 0xff0000) != 0)
8113 prefix
= (i
.tm
.base_opcode
>> 16) & 0xff;
8114 if (!i
.tm
.cpu_flags
.bitfield
.cpupadlock
8115 || prefix
!= REPE_PREFIX_OPCODE
8116 || (i
.prefix
[REP_PREFIX
] != REPE_PREFIX_OPCODE
))
8117 add_prefix (prefix
);
8123 /* Check for pseudo prefixes. */
8124 as_bad_where (insn_start_frag
->fr_file
,
8125 insn_start_frag
->fr_line
,
8126 _("pseudo prefix without instruction"));
8132 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
8133 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
8134 R_X86_64_GOTTPOFF relocation so that linker can safely
8135 perform IE->LE optimization. */
8136 if (x86_elf_abi
== X86_64_X32_ABI
8138 && i
.reloc
[0] == BFD_RELOC_X86_64_GOTTPOFF
8139 && i
.prefix
[REX_PREFIX
] == 0)
8140 add_prefix (REX_OPCODE
);
8143 /* The prefix bytes. */
8144 for (j
= ARRAY_SIZE (i
.prefix
), q
= i
.prefix
; j
> 0; j
--, q
++)
8146 FRAG_APPEND_1_CHAR (*q
);
8150 for (j
= 0, q
= i
.prefix
; j
< ARRAY_SIZE (i
.prefix
); j
++, q
++)
8155 /* REX byte is encoded in VEX prefix. */
8159 FRAG_APPEND_1_CHAR (*q
);
8162 /* There should be no other prefixes for instructions
8167 /* For EVEX instructions i.vrex should become 0 after
8168 build_evex_prefix. For VEX instructions upper 16 registers
8169 aren't available, so VREX should be 0. */
8172 /* Now the VEX prefix. */
8173 p
= frag_more (i
.vex
.length
);
8174 for (j
= 0; j
< i
.vex
.length
; j
++)
8175 p
[j
] = i
.vex
.bytes
[j
];
8178 /* Now the opcode; be careful about word order here! */
8179 if (i
.tm
.opcode_length
== 1)
8181 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
8185 switch (i
.tm
.opcode_length
)
8189 *p
++ = (i
.tm
.base_opcode
>> 24) & 0xff;
8190 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
8194 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
8204 /* Put out high byte first: can't use md_number_to_chars! */
8205 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
8206 *p
= i
.tm
.base_opcode
& 0xff;
8209 /* Now the modrm byte and sib byte (if present). */
8210 if (i
.tm
.opcode_modifier
.modrm
)
8212 FRAG_APPEND_1_CHAR ((i
.rm
.regmem
<< 0
8215 /* If i.rm.regmem == ESP (4)
8216 && i.rm.mode != (Register mode)
8218 ==> need second modrm byte. */
8219 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
8221 && !(i
.base_reg
&& i
.base_reg
->reg_type
.bitfield
.word
))
8222 FRAG_APPEND_1_CHAR ((i
.sib
.base
<< 0
8224 | i
.sib
.scale
<< 6));
8227 if (i
.disp_operands
)
8228 output_disp (insn_start_frag
, insn_start_off
);
8231 output_imm (insn_start_frag
, insn_start_off
);
8237 pi ("" /*line*/, &i
);
8239 #endif /* DEBUG386 */
8242 /* Return the size of the displacement operand N. */
8245 disp_size (unsigned int n
)
8249 if (i
.types
[n
].bitfield
.disp64
)
8251 else if (i
.types
[n
].bitfield
.disp8
)
8253 else if (i
.types
[n
].bitfield
.disp16
)
8258 /* Return the size of the immediate operand N. */
8261 imm_size (unsigned int n
)
8264 if (i
.types
[n
].bitfield
.imm64
)
8266 else if (i
.types
[n
].bitfield
.imm8
|| i
.types
[n
].bitfield
.imm8s
)
8268 else if (i
.types
[n
].bitfield
.imm16
)
8274 output_disp (fragS
*insn_start_frag
, offsetT insn_start_off
)
8279 for (n
= 0; n
< i
.operands
; n
++)
8281 if (operand_type_check (i
.types
[n
], disp
))
8283 if (i
.op
[n
].disps
->X_op
== O_constant
)
8285 int size
= disp_size (n
);
8286 offsetT val
= i
.op
[n
].disps
->X_add_number
;
8288 val
= offset_in_range (val
>> (size
== 1 ? i
.memshift
: 0),
8290 p
= frag_more (size
);
8291 md_number_to_chars (p
, val
, size
);
8295 enum bfd_reloc_code_real reloc_type
;
8296 int size
= disp_size (n
);
8297 int sign
= i
.types
[n
].bitfield
.disp32s
;
8298 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
8301 /* We can't have 8 bit displacement here. */
8302 gas_assert (!i
.types
[n
].bitfield
.disp8
);
8304 /* The PC relative address is computed relative
8305 to the instruction boundary, so in case immediate
8306 fields follows, we need to adjust the value. */
8307 if (pcrel
&& i
.imm_operands
)
8312 for (n1
= 0; n1
< i
.operands
; n1
++)
8313 if (operand_type_check (i
.types
[n1
], imm
))
8315 /* Only one immediate is allowed for PC
8316 relative address. */
8317 gas_assert (sz
== 0);
8319 i
.op
[n
].disps
->X_add_number
-= sz
;
8321 /* We should find the immediate. */
8322 gas_assert (sz
!= 0);
8325 p
= frag_more (size
);
8326 reloc_type
= reloc (size
, pcrel
, sign
, i
.reloc
[n
]);
8328 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
8329 && (((reloc_type
== BFD_RELOC_32
8330 || reloc_type
== BFD_RELOC_X86_64_32S
8331 || (reloc_type
== BFD_RELOC_64
8333 && (i
.op
[n
].disps
->X_op
== O_symbol
8334 || (i
.op
[n
].disps
->X_op
== O_add
8335 && ((symbol_get_value_expression
8336 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
8338 || reloc_type
== BFD_RELOC_32_PCREL
))
8342 if (insn_start_frag
== frag_now
)
8343 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
8348 add
= insn_start_frag
->fr_fix
- insn_start_off
;
8349 for (fr
= insn_start_frag
->fr_next
;
8350 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
8352 add
+= p
- frag_now
->fr_literal
;
8357 reloc_type
= BFD_RELOC_386_GOTPC
;
8358 i
.op
[n
].imms
->X_add_number
+= add
;
8360 else if (reloc_type
== BFD_RELOC_64
)
8361 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
8363 /* Don't do the adjustment for x86-64, as there
8364 the pcrel addressing is relative to the _next_
8365 insn, and that is taken care of in other code. */
8366 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
8368 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
8369 size
, i
.op
[n
].disps
, pcrel
,
8371 /* Check for "call/jmp *mem", "mov mem, %reg",
8372 "test %reg, mem" and "binop mem, %reg" where binop
8373 is one of adc, add, and, cmp, or, sbb, sub, xor
8374 instructions. Always generate R_386_GOT32X for
8375 "sym*GOT" operand in 32-bit mode. */
8376 if ((generate_relax_relocations
8379 && i
.rm
.regmem
== 5))
8381 || (i
.rm
.mode
== 0 && i
.rm
.regmem
== 5))
8382 && ((i
.operands
== 1
8383 && i
.tm
.base_opcode
== 0xff
8384 && (i
.rm
.reg
== 2 || i
.rm
.reg
== 4))
8386 && (i
.tm
.base_opcode
== 0x8b
8387 || i
.tm
.base_opcode
== 0x85
8388 || (i
.tm
.base_opcode
& 0xc7) == 0x03))))
8392 fixP
->fx_tcbit
= i
.rex
!= 0;
8394 && (i
.base_reg
->reg_num
== RegIP
))
8395 fixP
->fx_tcbit2
= 1;
8398 fixP
->fx_tcbit2
= 1;
8406 output_imm (fragS
*insn_start_frag
, offsetT insn_start_off
)
8411 for (n
= 0; n
< i
.operands
; n
++)
8413 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
8414 if (i
.rounding
&& (int) n
== i
.rounding
->operand
)
8417 if (operand_type_check (i
.types
[n
], imm
))
8419 if (i
.op
[n
].imms
->X_op
== O_constant
)
8421 int size
= imm_size (n
);
8424 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
8426 p
= frag_more (size
);
8427 md_number_to_chars (p
, val
, size
);
8431 /* Not absolute_section.
8432 Need a 32-bit fixup (don't support 8bit
8433 non-absolute imms). Try to support other
8435 enum bfd_reloc_code_real reloc_type
;
8436 int size
= imm_size (n
);
8439 if (i
.types
[n
].bitfield
.imm32s
8440 && (i
.suffix
== QWORD_MNEM_SUFFIX
8441 || (!i
.suffix
&& i
.tm
.opcode_modifier
.no_lsuf
)))
8446 p
= frag_more (size
);
8447 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
8449 /* This is tough to explain. We end up with this one if we
8450 * have operands that look like
8451 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
8452 * obtain the absolute address of the GOT, and it is strongly
8453 * preferable from a performance point of view to avoid using
8454 * a runtime relocation for this. The actual sequence of
8455 * instructions often look something like:
8460 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
8462 * The call and pop essentially return the absolute address
8463 * of the label .L66 and store it in %ebx. The linker itself
8464 * will ultimately change the first operand of the addl so
8465 * that %ebx points to the GOT, but to keep things simple, the
8466 * .o file must have this operand set so that it generates not
8467 * the absolute address of .L66, but the absolute address of
8468 * itself. This allows the linker itself simply treat a GOTPC
8469 * relocation as asking for a pcrel offset to the GOT to be
8470 * added in, and the addend of the relocation is stored in the
8471 * operand field for the instruction itself.
8473 * Our job here is to fix the operand so that it would add
8474 * the correct offset so that %ebx would point to itself. The
8475 * thing that is tricky is that .-.L66 will point to the
8476 * beginning of the instruction, so we need to further modify
8477 * the operand so that it will point to itself. There are
8478 * other cases where you have something like:
8480 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
8482 * and here no correction would be required. Internally in
8483 * the assembler we treat operands of this form as not being
8484 * pcrel since the '.' is explicitly mentioned, and I wonder
8485 * whether it would simplify matters to do it this way. Who
8486 * knows. In earlier versions of the PIC patches, the
8487 * pcrel_adjust field was used to store the correction, but
8488 * since the expression is not pcrel, I felt it would be
8489 * confusing to do it this way. */
8491 if ((reloc_type
== BFD_RELOC_32
8492 || reloc_type
== BFD_RELOC_X86_64_32S
8493 || reloc_type
== BFD_RELOC_64
)
8495 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
8496 && (i
.op
[n
].imms
->X_op
== O_symbol
8497 || (i
.op
[n
].imms
->X_op
== O_add
8498 && ((symbol_get_value_expression
8499 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
8504 if (insn_start_frag
== frag_now
)
8505 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
8510 add
= insn_start_frag
->fr_fix
- insn_start_off
;
8511 for (fr
= insn_start_frag
->fr_next
;
8512 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
8514 add
+= p
- frag_now
->fr_literal
;
8518 reloc_type
= BFD_RELOC_386_GOTPC
;
8520 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
8522 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
8523 i
.op
[n
].imms
->X_add_number
+= add
;
8525 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
8526 i
.op
[n
].imms
, 0, reloc_type
);
8532 /* x86_cons_fix_new is called via the expression parsing code when a
8533 reloc is needed. We use this hook to get the correct .got reloc. */
8534 static int cons_sign
= -1;
8537 x86_cons_fix_new (fragS
*frag
, unsigned int off
, unsigned int len
,
8538 expressionS
*exp
, bfd_reloc_code_real_type r
)
8540 r
= reloc (len
, 0, cons_sign
, r
);
8543 if (exp
->X_op
== O_secrel
)
8545 exp
->X_op
= O_symbol
;
8546 r
= BFD_RELOC_32_SECREL
;
8550 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
8553 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
8554 purpose of the `.dc.a' internal pseudo-op. */
8557 x86_address_bytes (void)
8559 if ((stdoutput
->arch_info
->mach
& bfd_mach_x64_32
))
8561 return stdoutput
->arch_info
->bits_per_address
/ 8;
8564 #if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
8566 # define lex_got(reloc, adjust, types) NULL
8568 /* Parse operands of the form
8569 <symbol>@GOTOFF+<nnn>
8570 and similar .plt or .got references.
8572 If we find one, set up the correct relocation in RELOC and copy the
8573 input string, minus the `@GOTOFF' into a malloc'd buffer for
8574 parsing by the calling routine. Return this buffer, and if ADJUST
8575 is non-null set it to the length of the string we removed from the
8576 input line. Otherwise return NULL. */
8578 lex_got (enum bfd_reloc_code_real
*rel
,
8580 i386_operand_type
*types
)
8582 /* Some of the relocations depend on the size of what field is to
8583 be relocated. But in our callers i386_immediate and i386_displacement
8584 we don't yet know the operand size (this will be set by insn
8585 matching). Hence we record the word32 relocation here,
8586 and adjust the reloc according to the real size in reloc(). */
8587 static const struct {
8590 const enum bfd_reloc_code_real rel
[2];
8591 const i386_operand_type types64
;
8593 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8594 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32
,
8596 OPERAND_TYPE_IMM32_64
},
8598 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real
,
8599 BFD_RELOC_X86_64_PLTOFF64
},
8600 OPERAND_TYPE_IMM64
},
8601 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32
,
8602 BFD_RELOC_X86_64_PLT32
},
8603 OPERAND_TYPE_IMM32_32S_DISP32
},
8604 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real
,
8605 BFD_RELOC_X86_64_GOTPLT64
},
8606 OPERAND_TYPE_IMM64_DISP64
},
8607 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF
,
8608 BFD_RELOC_X86_64_GOTOFF64
},
8609 OPERAND_TYPE_IMM64_DISP64
},
8610 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real
,
8611 BFD_RELOC_X86_64_GOTPCREL
},
8612 OPERAND_TYPE_IMM32_32S_DISP32
},
8613 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD
,
8614 BFD_RELOC_X86_64_TLSGD
},
8615 OPERAND_TYPE_IMM32_32S_DISP32
},
8616 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM
,
8617 _dummy_first_bfd_reloc_code_real
},
8618 OPERAND_TYPE_NONE
},
8619 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real
,
8620 BFD_RELOC_X86_64_TLSLD
},
8621 OPERAND_TYPE_IMM32_32S_DISP32
},
8622 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32
,
8623 BFD_RELOC_X86_64_GOTTPOFF
},
8624 OPERAND_TYPE_IMM32_32S_DISP32
},
8625 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32
,
8626 BFD_RELOC_X86_64_TPOFF32
},
8627 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
8628 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE
,
8629 _dummy_first_bfd_reloc_code_real
},
8630 OPERAND_TYPE_NONE
},
8631 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32
,
8632 BFD_RELOC_X86_64_DTPOFF32
},
8633 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
8634 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE
,
8635 _dummy_first_bfd_reloc_code_real
},
8636 OPERAND_TYPE_NONE
},
8637 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE
,
8638 _dummy_first_bfd_reloc_code_real
},
8639 OPERAND_TYPE_NONE
},
8640 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32
,
8641 BFD_RELOC_X86_64_GOT32
},
8642 OPERAND_TYPE_IMM32_32S_64_DISP32
},
8643 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC
,
8644 BFD_RELOC_X86_64_GOTPC32_TLSDESC
},
8645 OPERAND_TYPE_IMM32_32S_DISP32
},
8646 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL
,
8647 BFD_RELOC_X86_64_TLSDESC_CALL
},
8648 OPERAND_TYPE_IMM32_32S_DISP32
},
8653 #if defined (OBJ_MAYBE_ELF)
8658 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
8659 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
8662 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
8664 int len
= gotrel
[j
].len
;
8665 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
8667 if (gotrel
[j
].rel
[object_64bit
] != 0)
8670 char *tmpbuf
, *past_reloc
;
8672 *rel
= gotrel
[j
].rel
[object_64bit
];
8676 if (flag_code
!= CODE_64BIT
)
8678 types
->bitfield
.imm32
= 1;
8679 types
->bitfield
.disp32
= 1;
8682 *types
= gotrel
[j
].types64
;
8685 if (j
!= 0 && GOT_symbol
== NULL
)
8686 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
8688 /* The length of the first part of our input line. */
8689 first
= cp
- input_line_pointer
;
8691 /* The second part goes from after the reloc token until
8692 (and including) an end_of_line char or comma. */
8693 past_reloc
= cp
+ 1 + len
;
8695 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
8697 second
= cp
+ 1 - past_reloc
;
8699 /* Allocate and copy string. The trailing NUL shouldn't
8700 be necessary, but be safe. */
8701 tmpbuf
= XNEWVEC (char, first
+ second
+ 2);
8702 memcpy (tmpbuf
, input_line_pointer
, first
);
8703 if (second
!= 0 && *past_reloc
!= ' ')
8704 /* Replace the relocation token with ' ', so that
8705 errors like foo@GOTOFF1 will be detected. */
8706 tmpbuf
[first
++] = ' ';
8708 /* Increment length by 1 if the relocation token is
8713 memcpy (tmpbuf
+ first
, past_reloc
, second
);
8714 tmpbuf
[first
+ second
] = '\0';
8718 as_bad (_("@%s reloc is not supported with %d-bit output format"),
8719 gotrel
[j
].str
, 1 << (5 + object_64bit
));
8724 /* Might be a symbol version string. Don't as_bad here. */
8733 /* Parse operands of the form
8734 <symbol>@SECREL32+<nnn>
8736 If we find one, set up the correct relocation in RELOC and copy the
8737 input string, minus the `@SECREL32' into a malloc'd buffer for
8738 parsing by the calling routine. Return this buffer, and if ADJUST
8739 is non-null set it to the length of the string we removed from the
8740 input line. Otherwise return NULL.
8742 This function is copied from the ELF version above adjusted for PE targets. */
8745 lex_got (enum bfd_reloc_code_real
*rel ATTRIBUTE_UNUSED
,
8746 int *adjust ATTRIBUTE_UNUSED
,
8747 i386_operand_type
*types
)
8753 const enum bfd_reloc_code_real rel
[2];
8754 const i386_operand_type types64
;
8758 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL
,
8759 BFD_RELOC_32_SECREL
},
8760 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
8766 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
8767 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
8770 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
8772 int len
= gotrel
[j
].len
;
8774 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
8776 if (gotrel
[j
].rel
[object_64bit
] != 0)
8779 char *tmpbuf
, *past_reloc
;
8781 *rel
= gotrel
[j
].rel
[object_64bit
];
8787 if (flag_code
!= CODE_64BIT
)
8789 types
->bitfield
.imm32
= 1;
8790 types
->bitfield
.disp32
= 1;
8793 *types
= gotrel
[j
].types64
;
8796 /* The length of the first part of our input line. */
8797 first
= cp
- input_line_pointer
;
8799 /* The second part goes from after the reloc token until
8800 (and including) an end_of_line char or comma. */
8801 past_reloc
= cp
+ 1 + len
;
8803 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
8805 second
= cp
+ 1 - past_reloc
;
8807 /* Allocate and copy string. The trailing NUL shouldn't
8808 be necessary, but be safe. */
8809 tmpbuf
= XNEWVEC (char, first
+ second
+ 2);
8810 memcpy (tmpbuf
, input_line_pointer
, first
);
8811 if (second
!= 0 && *past_reloc
!= ' ')
8812 /* Replace the relocation token with ' ', so that
8813 errors like foo@SECLREL321 will be detected. */
8814 tmpbuf
[first
++] = ' ';
8815 memcpy (tmpbuf
+ first
, past_reloc
, second
);
8816 tmpbuf
[first
+ second
] = '\0';
8820 as_bad (_("@%s reloc is not supported with %d-bit output format"),
8821 gotrel
[j
].str
, 1 << (5 + object_64bit
));
8826 /* Might be a symbol version string. Don't as_bad here. */
8832 bfd_reloc_code_real_type
8833 x86_cons (expressionS
*exp
, int size
)
8835 bfd_reloc_code_real_type got_reloc
= NO_RELOC
;
8837 intel_syntax
= -intel_syntax
;
8840 if (size
== 4 || (object_64bit
&& size
== 8))
8842 /* Handle @GOTOFF and the like in an expression. */
8844 char *gotfree_input_line
;
8847 save
= input_line_pointer
;
8848 gotfree_input_line
= lex_got (&got_reloc
, &adjust
, NULL
);
8849 if (gotfree_input_line
)
8850 input_line_pointer
= gotfree_input_line
;
8854 if (gotfree_input_line
)
8856 /* expression () has merrily parsed up to the end of line,
8857 or a comma - in the wrong buffer. Transfer how far
8858 input_line_pointer has moved to the right buffer. */
8859 input_line_pointer
= (save
8860 + (input_line_pointer
- gotfree_input_line
)
8862 free (gotfree_input_line
);
8863 if (exp
->X_op
== O_constant
8864 || exp
->X_op
== O_absent
8865 || exp
->X_op
== O_illegal
8866 || exp
->X_op
== O_register
8867 || exp
->X_op
== O_big
)
8869 char c
= *input_line_pointer
;
8870 *input_line_pointer
= 0;
8871 as_bad (_("missing or invalid expression `%s'"), save
);
8872 *input_line_pointer
= c
;
8879 intel_syntax
= -intel_syntax
;
8882 i386_intel_simplify (exp
);
8888 signed_cons (int size
)
8890 if (flag_code
== CODE_64BIT
)
8898 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
8905 if (exp
.X_op
== O_symbol
)
8906 exp
.X_op
= O_secrel
;
8908 emit_expr (&exp
, 4);
8910 while (*input_line_pointer
++ == ',');
8912 input_line_pointer
--;
8913 demand_empty_rest_of_line ();
8917 /* Handle Vector operations. */
8920 check_VecOperations (char *op_string
, char *op_end
)
8922 const reg_entry
*mask
;
8927 && (op_end
== NULL
|| op_string
< op_end
))
8930 if (*op_string
== '{')
8934 /* Check broadcasts. */
8935 if (strncmp (op_string
, "1to", 3) == 0)
8940 goto duplicated_vec_op
;
8943 if (*op_string
== '8')
8945 else if (*op_string
== '4')
8947 else if (*op_string
== '2')
8949 else if (*op_string
== '1'
8950 && *(op_string
+1) == '6')
8957 as_bad (_("Unsupported broadcast: `%s'"), saved
);
8962 broadcast_op
.type
= bcst_type
;
8963 broadcast_op
.operand
= this_operand
;
8964 broadcast_op
.bytes
= 0;
8965 i
.broadcast
= &broadcast_op
;
8967 /* Check masking operation. */
8968 else if ((mask
= parse_register (op_string
, &end_op
)) != NULL
)
8970 /* k0 can't be used for write mask. */
8971 if (!mask
->reg_type
.bitfield
.regmask
|| mask
->reg_num
== 0)
8973 as_bad (_("`%s%s' can't be used for write mask"),
8974 register_prefix
, mask
->reg_name
);
8980 mask_op
.mask
= mask
;
8981 mask_op
.zeroing
= 0;
8982 mask_op
.operand
= this_operand
;
8988 goto duplicated_vec_op
;
8990 i
.mask
->mask
= mask
;
8992 /* Only "{z}" is allowed here. No need to check
8993 zeroing mask explicitly. */
8994 if (i
.mask
->operand
!= this_operand
)
8996 as_bad (_("invalid write mask `%s'"), saved
);
9003 /* Check zeroing-flag for masking operation. */
9004 else if (*op_string
== 'z')
9008 mask_op
.mask
= NULL
;
9009 mask_op
.zeroing
= 1;
9010 mask_op
.operand
= this_operand
;
9015 if (i
.mask
->zeroing
)
9018 as_bad (_("duplicated `%s'"), saved
);
9022 i
.mask
->zeroing
= 1;
9024 /* Only "{%k}" is allowed here. No need to check mask
9025 register explicitly. */
9026 if (i
.mask
->operand
!= this_operand
)
9028 as_bad (_("invalid zeroing-masking `%s'"),
9037 goto unknown_vec_op
;
9039 if (*op_string
!= '}')
9041 as_bad (_("missing `}' in `%s'"), saved
);
9046 /* Strip whitespace since the addition of pseudo prefixes
9047 changed how the scrubber treats '{'. */
9048 if (is_space_char (*op_string
))
9054 /* We don't know this one. */
9055 as_bad (_("unknown vector operation: `%s'"), saved
);
9059 if (i
.mask
&& i
.mask
->zeroing
&& !i
.mask
->mask
)
9061 as_bad (_("zeroing-masking only allowed with write mask"));
9069 i386_immediate (char *imm_start
)
9071 char *save_input_line_pointer
;
9072 char *gotfree_input_line
;
9075 i386_operand_type types
;
9077 operand_type_set (&types
, ~0);
9079 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
9081 as_bad (_("at most %d immediate operands are allowed"),
9082 MAX_IMMEDIATE_OPERANDS
);
9086 exp
= &im_expressions
[i
.imm_operands
++];
9087 i
.op
[this_operand
].imms
= exp
;
9089 if (is_space_char (*imm_start
))
9092 save_input_line_pointer
= input_line_pointer
;
9093 input_line_pointer
= imm_start
;
9095 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
9096 if (gotfree_input_line
)
9097 input_line_pointer
= gotfree_input_line
;
9099 exp_seg
= expression (exp
);
9103 /* Handle vector operations. */
9104 if (*input_line_pointer
== '{')
9106 input_line_pointer
= check_VecOperations (input_line_pointer
,
9108 if (input_line_pointer
== NULL
)
9112 if (*input_line_pointer
)
9113 as_bad (_("junk `%s' after expression"), input_line_pointer
);
9115 input_line_pointer
= save_input_line_pointer
;
9116 if (gotfree_input_line
)
9118 free (gotfree_input_line
);
9120 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
9121 exp
->X_op
= O_illegal
;
9124 return i386_finalize_immediate (exp_seg
, exp
, types
, imm_start
);
9128 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
9129 i386_operand_type types
, const char *imm_start
)
9131 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_illegal
|| exp
->X_op
== O_big
)
9134 as_bad (_("missing or invalid immediate expression `%s'"),
9138 else if (exp
->X_op
== O_constant
)
9140 /* Size it properly later. */
9141 i
.types
[this_operand
].bitfield
.imm64
= 1;
9142 /* If not 64bit, sign extend val. */
9143 if (flag_code
!= CODE_64BIT
9144 && (exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
9146 = (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
9148 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
9149 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
9150 && exp_seg
!= absolute_section
9151 && exp_seg
!= text_section
9152 && exp_seg
!= data_section
9153 && exp_seg
!= bss_section
9154 && exp_seg
!= undefined_section
9155 && !bfd_is_com_section (exp_seg
))
9157 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
9161 else if (!intel_syntax
&& exp_seg
== reg_section
)
9164 as_bad (_("illegal immediate register operand %s"), imm_start
);
9169 /* This is an address. The size of the address will be
9170 determined later, depending on destination register,
9171 suffix, or the default for the section. */
9172 i
.types
[this_operand
].bitfield
.imm8
= 1;
9173 i
.types
[this_operand
].bitfield
.imm16
= 1;
9174 i
.types
[this_operand
].bitfield
.imm32
= 1;
9175 i
.types
[this_operand
].bitfield
.imm32s
= 1;
9176 i
.types
[this_operand
].bitfield
.imm64
= 1;
9177 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
9185 i386_scale (char *scale
)
9188 char *save
= input_line_pointer
;
9190 input_line_pointer
= scale
;
9191 val
= get_absolute_expression ();
9196 i
.log2_scale_factor
= 0;
9199 i
.log2_scale_factor
= 1;
9202 i
.log2_scale_factor
= 2;
9205 i
.log2_scale_factor
= 3;
9209 char sep
= *input_line_pointer
;
9211 *input_line_pointer
= '\0';
9212 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
9214 *input_line_pointer
= sep
;
9215 input_line_pointer
= save
;
9219 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
9221 as_warn (_("scale factor of %d without an index register"),
9222 1 << i
.log2_scale_factor
);
9223 i
.log2_scale_factor
= 0;
9225 scale
= input_line_pointer
;
9226 input_line_pointer
= save
;
9231 i386_displacement (char *disp_start
, char *disp_end
)
9235 char *save_input_line_pointer
;
9236 char *gotfree_input_line
;
9238 i386_operand_type bigdisp
, types
= anydisp
;
9241 if (i
.disp_operands
== MAX_MEMORY_OPERANDS
)
9243 as_bad (_("at most %d displacement operands are allowed"),
9244 MAX_MEMORY_OPERANDS
);
9248 operand_type_set (&bigdisp
, 0);
9249 if ((i
.types
[this_operand
].bitfield
.jumpabsolute
)
9250 || (!current_templates
->start
->opcode_modifier
.jump
9251 && !current_templates
->start
->opcode_modifier
.jumpdword
))
9253 bigdisp
.bitfield
.disp32
= 1;
9254 override
= (i
.prefix
[ADDR_PREFIX
] != 0);
9255 if (flag_code
== CODE_64BIT
)
9259 bigdisp
.bitfield
.disp32s
= 1;
9260 bigdisp
.bitfield
.disp64
= 1;
9263 else if ((flag_code
== CODE_16BIT
) ^ override
)
9265 bigdisp
.bitfield
.disp32
= 0;
9266 bigdisp
.bitfield
.disp16
= 1;
9271 /* For PC-relative branches, the width of the displacement
9272 is dependent upon data size, not address size. */
9273 override
= (i
.prefix
[DATA_PREFIX
] != 0);
9274 if (flag_code
== CODE_64BIT
)
9276 if (override
|| i
.suffix
== WORD_MNEM_SUFFIX
)
9277 bigdisp
.bitfield
.disp16
= 1;
9280 bigdisp
.bitfield
.disp32
= 1;
9281 bigdisp
.bitfield
.disp32s
= 1;
9287 override
= (i
.suffix
== (flag_code
!= CODE_16BIT
9289 : LONG_MNEM_SUFFIX
));
9290 bigdisp
.bitfield
.disp32
= 1;
9291 if ((flag_code
== CODE_16BIT
) ^ override
)
9293 bigdisp
.bitfield
.disp32
= 0;
9294 bigdisp
.bitfield
.disp16
= 1;
9298 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
9301 exp
= &disp_expressions
[i
.disp_operands
];
9302 i
.op
[this_operand
].disps
= exp
;
9304 save_input_line_pointer
= input_line_pointer
;
9305 input_line_pointer
= disp_start
;
9306 END_STRING_AND_SAVE (disp_end
);
9308 #ifndef GCC_ASM_O_HACK
9309 #define GCC_ASM_O_HACK 0
9312 END_STRING_AND_SAVE (disp_end
+ 1);
9313 if (i
.types
[this_operand
].bitfield
.baseIndex
9314 && displacement_string_end
[-1] == '+')
9316 /* This hack is to avoid a warning when using the "o"
9317 constraint within gcc asm statements.
9320 #define _set_tssldt_desc(n,addr,limit,type) \
9321 __asm__ __volatile__ ( \
9323 "movw %w1,2+%0\n\t" \
9325 "movb %b1,4+%0\n\t" \
9326 "movb %4,5+%0\n\t" \
9327 "movb $0,6+%0\n\t" \
9328 "movb %h1,7+%0\n\t" \
9330 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
9332 This works great except that the output assembler ends
9333 up looking a bit weird if it turns out that there is
9334 no offset. You end up producing code that looks like:
9347 So here we provide the missing zero. */
9349 *displacement_string_end
= '0';
9352 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
9353 if (gotfree_input_line
)
9354 input_line_pointer
= gotfree_input_line
;
9356 exp_seg
= expression (exp
);
9359 if (*input_line_pointer
)
9360 as_bad (_("junk `%s' after expression"), input_line_pointer
);
9362 RESTORE_END_STRING (disp_end
+ 1);
9364 input_line_pointer
= save_input_line_pointer
;
9365 if (gotfree_input_line
)
9367 free (gotfree_input_line
);
9369 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
9370 exp
->X_op
= O_illegal
;
9373 ret
= i386_finalize_displacement (exp_seg
, exp
, types
, disp_start
);
9375 RESTORE_END_STRING (disp_end
);
9381 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
9382 i386_operand_type types
, const char *disp_start
)
9384 i386_operand_type bigdisp
;
9387 /* We do this to make sure that the section symbol is in
9388 the symbol table. We will ultimately change the relocation
9389 to be relative to the beginning of the section. */
9390 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
9391 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
9392 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
9394 if (exp
->X_op
!= O_symbol
)
9397 if (S_IS_LOCAL (exp
->X_add_symbol
)
9398 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
9399 && S_GET_SEGMENT (exp
->X_add_symbol
) != expr_section
)
9400 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
9401 exp
->X_op
= O_subtract
;
9402 exp
->X_op_symbol
= GOT_symbol
;
9403 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
9404 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
9405 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
9406 i
.reloc
[this_operand
] = BFD_RELOC_64
;
9408 i
.reloc
[this_operand
] = BFD_RELOC_32
;
9411 else if (exp
->X_op
== O_absent
9412 || exp
->X_op
== O_illegal
9413 || exp
->X_op
== O_big
)
9416 as_bad (_("missing or invalid displacement expression `%s'"),
9421 else if (flag_code
== CODE_64BIT
9422 && !i
.prefix
[ADDR_PREFIX
]
9423 && exp
->X_op
== O_constant
)
9425 /* Since displacement is signed extended to 64bit, don't allow
9426 disp32 and turn off disp32s if they are out of range. */
9427 i
.types
[this_operand
].bitfield
.disp32
= 0;
9428 if (!fits_in_signed_long (exp
->X_add_number
))
9430 i
.types
[this_operand
].bitfield
.disp32s
= 0;
9431 if (i
.types
[this_operand
].bitfield
.baseindex
)
9433 as_bad (_("0x%lx out range of signed 32bit displacement"),
9434 (long) exp
->X_add_number
);
9440 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
9441 else if (exp
->X_op
!= O_constant
9442 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
9443 && exp_seg
!= absolute_section
9444 && exp_seg
!= text_section
9445 && exp_seg
!= data_section
9446 && exp_seg
!= bss_section
9447 && exp_seg
!= undefined_section
9448 && !bfd_is_com_section (exp_seg
))
9450 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
9455 /* Check if this is a displacement only operand. */
9456 bigdisp
= i
.types
[this_operand
];
9457 bigdisp
.bitfield
.disp8
= 0;
9458 bigdisp
.bitfield
.disp16
= 0;
9459 bigdisp
.bitfield
.disp32
= 0;
9460 bigdisp
.bitfield
.disp32s
= 0;
9461 bigdisp
.bitfield
.disp64
= 0;
9462 if (operand_type_all_zero (&bigdisp
))
9463 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
9469 /* Return the active addressing mode, taking address override and
9470 registers forming the address into consideration. Update the
9471 address override prefix if necessary. */
9473 static enum flag_code
9474 i386_addressing_mode (void)
9476 enum flag_code addr_mode
;
9478 if (i
.prefix
[ADDR_PREFIX
])
9479 addr_mode
= flag_code
== CODE_32BIT
? CODE_16BIT
: CODE_32BIT
;
9482 addr_mode
= flag_code
;
9484 #if INFER_ADDR_PREFIX
9485 if (i
.mem_operands
== 0)
9487 /* Infer address prefix from the first memory operand. */
9488 const reg_entry
*addr_reg
= i
.base_reg
;
9490 if (addr_reg
== NULL
)
9491 addr_reg
= i
.index_reg
;
9495 if (addr_reg
->reg_type
.bitfield
.dword
)
9496 addr_mode
= CODE_32BIT
;
9497 else if (flag_code
!= CODE_64BIT
9498 && addr_reg
->reg_type
.bitfield
.word
)
9499 addr_mode
= CODE_16BIT
;
9501 if (addr_mode
!= flag_code
)
9503 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
9505 /* Change the size of any displacement too. At most one
9506 of Disp16 or Disp32 is set.
9507 FIXME. There doesn't seem to be any real need for
9508 separate Disp16 and Disp32 flags. The same goes for
9509 Imm16 and Imm32. Removing them would probably clean
9510 up the code quite a lot. */
9511 if (flag_code
!= CODE_64BIT
9512 && (i
.types
[this_operand
].bitfield
.disp16
9513 || i
.types
[this_operand
].bitfield
.disp32
))
9514 i
.types
[this_operand
]
9515 = operand_type_xor (i
.types
[this_operand
], disp16_32
);
9525 /* Make sure the memory operand we've been dealt is valid.
9526 Return 1 on success, 0 on a failure. */
9529 i386_index_check (const char *operand_string
)
9531 const char *kind
= "base/index";
9532 enum flag_code addr_mode
= i386_addressing_mode ();
9534 if (current_templates
->start
->opcode_modifier
.isstring
9535 && !current_templates
->start
->opcode_modifier
.immext
9536 && (current_templates
->end
[-1].opcode_modifier
.isstring
9539 /* Memory operands of string insns are special in that they only allow
9540 a single register (rDI, rSI, or rBX) as their memory address. */
9541 const reg_entry
*expected_reg
;
9542 static const char *di_si
[][2] =
9548 static const char *bx
[] = { "ebx", "bx", "rbx" };
9550 kind
= "string address";
9552 if (current_templates
->start
->opcode_modifier
.repprefixok
)
9554 i386_operand_type type
= current_templates
->end
[-1].operand_types
[0];
9556 if (!type
.bitfield
.baseindex
9557 || ((!i
.mem_operands
!= !intel_syntax
)
9558 && current_templates
->end
[-1].operand_types
[1]
9559 .bitfield
.baseindex
))
9560 type
= current_templates
->end
[-1].operand_types
[1];
9561 expected_reg
= hash_find (reg_hash
,
9562 di_si
[addr_mode
][type
.bitfield
.esseg
]);
9566 expected_reg
= hash_find (reg_hash
, bx
[addr_mode
]);
9568 if (i
.base_reg
!= expected_reg
9570 || operand_type_check (i
.types
[this_operand
], disp
))
9572 /* The second memory operand must have the same size as
9576 && !((addr_mode
== CODE_64BIT
9577 && i
.base_reg
->reg_type
.bitfield
.qword
)
9578 || (addr_mode
== CODE_32BIT
9579 ? i
.base_reg
->reg_type
.bitfield
.dword
9580 : i
.base_reg
->reg_type
.bitfield
.word
)))
9583 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
9585 intel_syntax
? '[' : '(',
9587 expected_reg
->reg_name
,
9588 intel_syntax
? ']' : ')');
9595 as_bad (_("`%s' is not a valid %s expression"),
9596 operand_string
, kind
);
9601 if (addr_mode
!= CODE_16BIT
)
9603 /* 32-bit/64-bit checks. */
9605 && ((addr_mode
== CODE_64BIT
9606 ? !i
.base_reg
->reg_type
.bitfield
.qword
9607 : !i
.base_reg
->reg_type
.bitfield
.dword
)
9608 || (i
.index_reg
&& i
.base_reg
->reg_num
== RegIP
)
9609 || i
.base_reg
->reg_num
== RegIZ
))
9611 && !i
.index_reg
->reg_type
.bitfield
.xmmword
9612 && !i
.index_reg
->reg_type
.bitfield
.ymmword
9613 && !i
.index_reg
->reg_type
.bitfield
.zmmword
9614 && ((addr_mode
== CODE_64BIT
9615 ? !i
.index_reg
->reg_type
.bitfield
.qword
9616 : !i
.index_reg
->reg_type
.bitfield
.dword
)
9617 || !i
.index_reg
->reg_type
.bitfield
.baseindex
)))
9620 /* bndmk, bndldx, and bndstx have special restrictions. */
9621 if (current_templates
->start
->base_opcode
== 0xf30f1b
9622 || (current_templates
->start
->base_opcode
& ~1) == 0x0f1a)
9624 /* They cannot use RIP-relative addressing. */
9625 if (i
.base_reg
&& i
.base_reg
->reg_num
== RegIP
)
9627 as_bad (_("`%s' cannot be used here"), operand_string
);
9631 /* bndldx and bndstx ignore their scale factor. */
9632 if (current_templates
->start
->base_opcode
!= 0xf30f1b
9633 && i
.log2_scale_factor
)
9634 as_warn (_("register scaling is being ignored here"));
9639 /* 16-bit checks. */
9641 && (!i
.base_reg
->reg_type
.bitfield
.word
9642 || !i
.base_reg
->reg_type
.bitfield
.baseindex
))
9644 && (!i
.index_reg
->reg_type
.bitfield
.word
9645 || !i
.index_reg
->reg_type
.bitfield
.baseindex
9647 && i
.base_reg
->reg_num
< 6
9648 && i
.index_reg
->reg_num
>= 6
9649 && i
.log2_scale_factor
== 0))))
9656 /* Handle vector immediates. */
9659 RC_SAE_immediate (const char *imm_start
)
9661 unsigned int match_found
, j
;
9662 const char *pstr
= imm_start
;
9670 for (j
= 0; j
< ARRAY_SIZE (RC_NamesTable
); j
++)
9672 if (!strncmp (pstr
, RC_NamesTable
[j
].name
, RC_NamesTable
[j
].len
))
9676 rc_op
.type
= RC_NamesTable
[j
].type
;
9677 rc_op
.operand
= this_operand
;
9678 i
.rounding
= &rc_op
;
9682 as_bad (_("duplicated `%s'"), imm_start
);
9685 pstr
+= RC_NamesTable
[j
].len
;
9695 as_bad (_("Missing '}': '%s'"), imm_start
);
9698 /* RC/SAE immediate string should contain nothing more. */;
9701 as_bad (_("Junk after '}': '%s'"), imm_start
);
9705 exp
= &im_expressions
[i
.imm_operands
++];
9706 i
.op
[this_operand
].imms
= exp
;
9708 exp
->X_op
= O_constant
;
9709 exp
->X_add_number
= 0;
9710 exp
->X_add_symbol
= (symbolS
*) 0;
9711 exp
->X_op_symbol
= (symbolS
*) 0;
9713 i
.types
[this_operand
].bitfield
.imm8
= 1;
9717 /* Only string instructions can have a second memory operand, so
9718 reduce current_templates to just those if it contains any. */
9720 maybe_adjust_templates (void)
9722 const insn_template
*t
;
9724 gas_assert (i
.mem_operands
== 1);
9726 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
9727 if (t
->opcode_modifier
.isstring
)
9730 if (t
< current_templates
->end
)
9732 static templates aux_templates
;
9733 bfd_boolean recheck
;
9735 aux_templates
.start
= t
;
9736 for (; t
< current_templates
->end
; ++t
)
9737 if (!t
->opcode_modifier
.isstring
)
9739 aux_templates
.end
= t
;
9741 /* Determine whether to re-check the first memory operand. */
9742 recheck
= (aux_templates
.start
!= current_templates
->start
9743 || t
!= current_templates
->end
);
9745 current_templates
= &aux_templates
;
9750 if (i
.memop1_string
!= NULL
9751 && i386_index_check (i
.memop1_string
) == 0)
9760 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
9764 i386_att_operand (char *operand_string
)
9768 char *op_string
= operand_string
;
9770 if (is_space_char (*op_string
))
9773 /* We check for an absolute prefix (differentiating,
9774 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
9775 if (*op_string
== ABSOLUTE_PREFIX
)
9778 if (is_space_char (*op_string
))
9780 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
9783 /* Check if operand is a register. */
9784 if ((r
= parse_register (op_string
, &end_op
)) != NULL
)
9786 i386_operand_type temp
;
9788 /* Check for a segment override by searching for ':' after a
9789 segment register. */
9791 if (is_space_char (*op_string
))
9793 if (*op_string
== ':'
9794 && (r
->reg_type
.bitfield
.sreg2
9795 || r
->reg_type
.bitfield
.sreg3
))
9800 i
.seg
[i
.mem_operands
] = &es
;
9803 i
.seg
[i
.mem_operands
] = &cs
;
9806 i
.seg
[i
.mem_operands
] = &ss
;
9809 i
.seg
[i
.mem_operands
] = &ds
;
9812 i
.seg
[i
.mem_operands
] = &fs
;
9815 i
.seg
[i
.mem_operands
] = &gs
;
9819 /* Skip the ':' and whitespace. */
9821 if (is_space_char (*op_string
))
9824 if (!is_digit_char (*op_string
)
9825 && !is_identifier_char (*op_string
)
9826 && *op_string
!= '('
9827 && *op_string
!= ABSOLUTE_PREFIX
)
9829 as_bad (_("bad memory operand `%s'"), op_string
);
9832 /* Handle case of %es:*foo. */
9833 if (*op_string
== ABSOLUTE_PREFIX
)
9836 if (is_space_char (*op_string
))
9838 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
9840 goto do_memory_reference
;
9843 /* Handle vector operations. */
9844 if (*op_string
== '{')
9846 op_string
= check_VecOperations (op_string
, NULL
);
9847 if (op_string
== NULL
)
9853 as_bad (_("junk `%s' after register"), op_string
);
9857 temp
.bitfield
.baseindex
= 0;
9858 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
9860 i
.types
[this_operand
].bitfield
.unspecified
= 0;
9861 i
.op
[this_operand
].regs
= r
;
9864 else if (*op_string
== REGISTER_PREFIX
)
9866 as_bad (_("bad register name `%s'"), op_string
);
9869 else if (*op_string
== IMMEDIATE_PREFIX
)
9872 if (i
.types
[this_operand
].bitfield
.jumpabsolute
)
9874 as_bad (_("immediate operand illegal with absolute jump"));
9877 if (!i386_immediate (op_string
))
9880 else if (RC_SAE_immediate (operand_string
))
9882 /* If it is a RC or SAE immediate, do nothing. */
9885 else if (is_digit_char (*op_string
)
9886 || is_identifier_char (*op_string
)
9887 || *op_string
== '"'
9888 || *op_string
== '(')
9890 /* This is a memory reference of some sort. */
9893 /* Start and end of displacement string expression (if found). */
9894 char *displacement_string_start
;
9895 char *displacement_string_end
;
9898 do_memory_reference
:
9899 if (i
.mem_operands
== 1 && !maybe_adjust_templates ())
9901 if ((i
.mem_operands
== 1
9902 && !current_templates
->start
->opcode_modifier
.isstring
)
9903 || i
.mem_operands
== 2)
9905 as_bad (_("too many memory references for `%s'"),
9906 current_templates
->start
->name
);
9910 /* Check for base index form. We detect the base index form by
9911 looking for an ')' at the end of the operand, searching
9912 for the '(' matching it, and finding a REGISTER_PREFIX or ','
9914 base_string
= op_string
+ strlen (op_string
);
9916 /* Handle vector operations. */
9917 vop_start
= strchr (op_string
, '{');
9918 if (vop_start
&& vop_start
< base_string
)
9920 if (check_VecOperations (vop_start
, base_string
) == NULL
)
9922 base_string
= vop_start
;
9926 if (is_space_char (*base_string
))
9929 /* If we only have a displacement, set-up for it to be parsed later. */
9930 displacement_string_start
= op_string
;
9931 displacement_string_end
= base_string
+ 1;
9933 if (*base_string
== ')')
9936 unsigned int parens_balanced
= 1;
9937 /* We've already checked that the number of left & right ()'s are
9938 equal, so this loop will not be infinite. */
9942 if (*base_string
== ')')
9944 if (*base_string
== '(')
9947 while (parens_balanced
);
9949 temp_string
= base_string
;
9951 /* Skip past '(' and whitespace. */
9953 if (is_space_char (*base_string
))
9956 if (*base_string
== ','
9957 || ((i
.base_reg
= parse_register (base_string
, &end_op
))
9960 displacement_string_end
= temp_string
;
9962 i
.types
[this_operand
].bitfield
.baseindex
= 1;
9966 base_string
= end_op
;
9967 if (is_space_char (*base_string
))
9971 /* There may be an index reg or scale factor here. */
9972 if (*base_string
== ',')
9975 if (is_space_char (*base_string
))
9978 if ((i
.index_reg
= parse_register (base_string
, &end_op
))
9981 base_string
= end_op
;
9982 if (is_space_char (*base_string
))
9984 if (*base_string
== ',')
9987 if (is_space_char (*base_string
))
9990 else if (*base_string
!= ')')
9992 as_bad (_("expecting `,' or `)' "
9993 "after index register in `%s'"),
9998 else if (*base_string
== REGISTER_PREFIX
)
10000 end_op
= strchr (base_string
, ',');
10003 as_bad (_("bad register name `%s'"), base_string
);
10007 /* Check for scale factor. */
10008 if (*base_string
!= ')')
10010 char *end_scale
= i386_scale (base_string
);
10015 base_string
= end_scale
;
10016 if (is_space_char (*base_string
))
10018 if (*base_string
!= ')')
10020 as_bad (_("expecting `)' "
10021 "after scale factor in `%s'"),
10026 else if (!i
.index_reg
)
10028 as_bad (_("expecting index register or scale factor "
10029 "after `,'; got '%c'"),
10034 else if (*base_string
!= ')')
10036 as_bad (_("expecting `,' or `)' "
10037 "after base register in `%s'"),
10042 else if (*base_string
== REGISTER_PREFIX
)
10044 end_op
= strchr (base_string
, ',');
10047 as_bad (_("bad register name `%s'"), base_string
);
10052 /* If there's an expression beginning the operand, parse it,
10053 assuming displacement_string_start and
10054 displacement_string_end are meaningful. */
10055 if (displacement_string_start
!= displacement_string_end
)
10057 if (!i386_displacement (displacement_string_start
,
10058 displacement_string_end
))
10062 /* Special case for (%dx) while doing input/output op. */
10064 && i
.base_reg
->reg_type
.bitfield
.inoutportreg
10065 && i
.index_reg
== 0
10066 && i
.log2_scale_factor
== 0
10067 && i
.seg
[i
.mem_operands
] == 0
10068 && !operand_type_check (i
.types
[this_operand
], disp
))
10070 i
.types
[this_operand
] = i
.base_reg
->reg_type
;
10074 if (i386_index_check (operand_string
) == 0)
10076 i
.flags
[this_operand
] |= Operand_Mem
;
10077 if (i
.mem_operands
== 0)
10078 i
.memop1_string
= xstrdup (operand_string
);
10083 /* It's not a memory operand; argh! */
10084 as_bad (_("invalid char %s beginning operand %d `%s'"),
10085 output_invalid (*op_string
),
10090 return 1; /* Normal return. */
10093 /* Calculate the maximum variable size (i.e., excluding fr_fix)
10094 that an rs_machine_dependent frag may reach. */
10097 i386_frag_max_var (fragS
*frag
)
10099 /* The only relaxable frags are for jumps.
10100 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
10101 gas_assert (frag
->fr_type
== rs_machine_dependent
);
10102 return TYPE_FROM_RELAX_STATE (frag
->fr_subtype
) == UNCOND_JUMP
? 4 : 5;
10105 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10107 elf_symbol_resolved_in_segment_p (symbolS
*fr_symbol
, offsetT fr_var
)
10109 /* STT_GNU_IFUNC symbol must go through PLT. */
10110 if ((symbol_get_bfdsym (fr_symbol
)->flags
10111 & BSF_GNU_INDIRECT_FUNCTION
) != 0)
10114 if (!S_IS_EXTERNAL (fr_symbol
))
10115 /* Symbol may be weak or local. */
10116 return !S_IS_WEAK (fr_symbol
);
10118 /* Global symbols with non-default visibility can't be preempted. */
10119 if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol
)) != STV_DEFAULT
)
10122 if (fr_var
!= NO_RELOC
)
10123 switch ((enum bfd_reloc_code_real
) fr_var
)
10125 case BFD_RELOC_386_PLT32
:
10126 case BFD_RELOC_X86_64_PLT32
:
10127 /* Symbol with PLT relocation may be preempted. */
10133 /* Global symbols with default visibility in a shared library may be
10134 preempted by another definition. */
10139 /* md_estimate_size_before_relax()
10141 Called just before relax() for rs_machine_dependent frags. The x86
10142 assembler uses these frags to handle variable size jump
10145 Any symbol that is now undefined will not become defined.
10146 Return the correct fr_subtype in the frag.
10147 Return the initial "guess for variable size of frag" to caller.
10148 The guess is actually the growth beyond the fixed part. Whatever
10149 we do to grow the fixed or variable part contributes to our
10153 md_estimate_size_before_relax (fragS
*fragP
, segT segment
)
10155 /* We've already got fragP->fr_subtype right; all we have to do is
10156 check for un-relaxable symbols. On an ELF system, we can't relax
10157 an externally visible symbol, because it may be overridden by a
10159 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
10160 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10162 && !elf_symbol_resolved_in_segment_p (fragP
->fr_symbol
,
10165 #if defined (OBJ_COFF) && defined (TE_PE)
10166 || (OUTPUT_FLAVOR
== bfd_target_coff_flavour
10167 && S_IS_WEAK (fragP
->fr_symbol
))
10171 /* Symbol is undefined in this segment, or we need to keep a
10172 reloc so that weak symbols can be overridden. */
10173 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
10174 enum bfd_reloc_code_real reloc_type
;
10175 unsigned char *opcode
;
10178 if (fragP
->fr_var
!= NO_RELOC
)
10179 reloc_type
= (enum bfd_reloc_code_real
) fragP
->fr_var
;
10180 else if (size
== 2)
10181 reloc_type
= BFD_RELOC_16_PCREL
;
10182 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10183 else if (need_plt32_p (fragP
->fr_symbol
))
10184 reloc_type
= BFD_RELOC_X86_64_PLT32
;
10187 reloc_type
= BFD_RELOC_32_PCREL
;
10189 old_fr_fix
= fragP
->fr_fix
;
10190 opcode
= (unsigned char *) fragP
->fr_opcode
;
10192 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
10195 /* Make jmp (0xeb) a (d)word displacement jump. */
10197 fragP
->fr_fix
+= size
;
10198 fix_new (fragP
, old_fr_fix
, size
,
10200 fragP
->fr_offset
, 1,
10206 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
10208 /* Negate the condition, and branch past an
10209 unconditional jump. */
10212 /* Insert an unconditional jump. */
10214 /* We added two extra opcode bytes, and have a two byte
10216 fragP
->fr_fix
+= 2 + 2;
10217 fix_new (fragP
, old_fr_fix
+ 2, 2,
10219 fragP
->fr_offset
, 1,
10223 /* Fall through. */
10226 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
10230 fragP
->fr_fix
+= 1;
10231 fixP
= fix_new (fragP
, old_fr_fix
, 1,
10233 fragP
->fr_offset
, 1,
10234 BFD_RELOC_8_PCREL
);
10235 fixP
->fx_signed
= 1;
10239 /* This changes the byte-displacement jump 0x7N
10240 to the (d)word-displacement jump 0x0f,0x8N. */
10241 opcode
[1] = opcode
[0] + 0x10;
10242 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
10243 /* We've added an opcode byte. */
10244 fragP
->fr_fix
+= 1 + size
;
10245 fix_new (fragP
, old_fr_fix
+ 1, size
,
10247 fragP
->fr_offset
, 1,
10252 BAD_CASE (fragP
->fr_subtype
);
10256 return fragP
->fr_fix
- old_fr_fix
;
10259 /* Guess size depending on current relax state. Initially the relax
10260 state will correspond to a short jump and we return 1, because
10261 the variable part of the frag (the branch offset) is one byte
10262 long. However, we can relax a section more than once and in that
10263 case we must either set fr_subtype back to the unrelaxed state,
10264 or return the value for the appropriate branch. */
10265 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
10268 /* Called after relax() is finished.
10270 In: Address of frag.
10271 fr_type == rs_machine_dependent.
10272 fr_subtype is what the address relaxed to.
10274 Out: Any fixSs and constants are set up.
10275 Caller will turn frag into a ".space 0". */
10278 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec ATTRIBUTE_UNUSED
,
10281 unsigned char *opcode
;
10282 unsigned char *where_to_put_displacement
= NULL
;
10283 offsetT target_address
;
10284 offsetT opcode_address
;
10285 unsigned int extension
= 0;
10286 offsetT displacement_from_opcode_start
;
10288 opcode
= (unsigned char *) fragP
->fr_opcode
;
10290 /* Address we want to reach in file space. */
10291 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
10293 /* Address opcode resides at in file space. */
10294 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
10296 /* Displacement from opcode start to fill into instruction. */
10297 displacement_from_opcode_start
= target_address
- opcode_address
;
10299 if ((fragP
->fr_subtype
& BIG
) == 0)
10301 /* Don't have to change opcode. */
10302 extension
= 1; /* 1 opcode + 1 displacement */
10303 where_to_put_displacement
= &opcode
[1];
10307 if (no_cond_jump_promotion
10308 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
10309 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
10310 _("long jump required"));
10312 switch (fragP
->fr_subtype
)
10314 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
10315 extension
= 4; /* 1 opcode + 4 displacement */
10317 where_to_put_displacement
= &opcode
[1];
10320 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
10321 extension
= 2; /* 1 opcode + 2 displacement */
10323 where_to_put_displacement
= &opcode
[1];
10326 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
10327 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
10328 extension
= 5; /* 2 opcode + 4 displacement */
10329 opcode
[1] = opcode
[0] + 0x10;
10330 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
10331 where_to_put_displacement
= &opcode
[2];
10334 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
10335 extension
= 3; /* 2 opcode + 2 displacement */
10336 opcode
[1] = opcode
[0] + 0x10;
10337 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
10338 where_to_put_displacement
= &opcode
[2];
10341 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
10346 where_to_put_displacement
= &opcode
[3];
10350 BAD_CASE (fragP
->fr_subtype
);
10355 /* If size if less then four we are sure that the operand fits,
10356 but if it's 4, then it could be that the displacement is larger
10358 if (DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
) == 4
10360 && ((addressT
) (displacement_from_opcode_start
- extension
10361 + ((addressT
) 1 << 31))
10362 > (((addressT
) 2 << 31) - 1)))
10364 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
10365 _("jump target out of range"));
10366 /* Make us emit 0. */
10367 displacement_from_opcode_start
= extension
;
10369 /* Now put displacement after opcode. */
10370 md_number_to_chars ((char *) where_to_put_displacement
,
10371 (valueT
) (displacement_from_opcode_start
- extension
),
10372 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
10373 fragP
->fr_fix
+= extension
;
10376 /* Apply a fixup (fixP) to segment data, once it has been determined
10377 by our caller that we have all the info we need to fix it up.
10379 Parameter valP is the pointer to the value of the bits.
10381 On the 386, immediates, displacements, and data pointers are all in
10382 the same (little-endian) format, so we don't need to care about which
10383 we are handling. */
10386 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
10388 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
10389 valueT value
= *valP
;
10391 #if !defined (TE_Mach)
10392 if (fixP
->fx_pcrel
)
10394 switch (fixP
->fx_r_type
)
10400 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
10403 case BFD_RELOC_X86_64_32S
:
10404 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
10407 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
10410 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
10415 if (fixP
->fx_addsy
!= NULL
10416 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
10417 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
10418 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
10419 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
10420 && !use_rela_relocations
)
10422 /* This is a hack. There should be a better way to handle this.
10423 This covers for the fact that bfd_install_relocation will
10424 subtract the current location (for partial_inplace, PC relative
10425 relocations); see more below. */
10429 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
10432 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
10434 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10437 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
10439 if ((sym_seg
== seg
10440 || (symbol_section_p (fixP
->fx_addsy
)
10441 && sym_seg
!= absolute_section
))
10442 && !generic_force_reloc (fixP
))
10444 /* Yes, we add the values in twice. This is because
10445 bfd_install_relocation subtracts them out again. I think
10446 bfd_install_relocation is broken, but I don't dare change
10448 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
10452 #if defined (OBJ_COFF) && defined (TE_PE)
10453 /* For some reason, the PE format does not store a
10454 section address offset for a PC relative symbol. */
10455 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
10456 || S_IS_WEAK (fixP
->fx_addsy
))
10457 value
+= md_pcrel_from (fixP
);
10460 #if defined (OBJ_COFF) && defined (TE_PE)
10461 if (fixP
->fx_addsy
!= NULL
10462 && S_IS_WEAK (fixP
->fx_addsy
)
10463 /* PR 16858: Do not modify weak function references. */
10464 && ! fixP
->fx_pcrel
)
10466 #if !defined (TE_PEP)
10467 /* For x86 PE weak function symbols are neither PC-relative
10468 nor do they set S_IS_FUNCTION. So the only reliable way
10469 to detect them is to check the flags of their containing
10471 if (S_GET_SEGMENT (fixP
->fx_addsy
) != NULL
10472 && S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_CODE
)
10476 value
-= S_GET_VALUE (fixP
->fx_addsy
);
10480 /* Fix a few things - the dynamic linker expects certain values here,
10481 and we must not disappoint it. */
10482 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10483 if (IS_ELF
&& fixP
->fx_addsy
)
10484 switch (fixP
->fx_r_type
)
10486 case BFD_RELOC_386_PLT32
:
10487 case BFD_RELOC_X86_64_PLT32
:
10488 /* Make the jump instruction point to the address of the operand. At
10489 runtime we merely add the offset to the actual PLT entry. */
10493 case BFD_RELOC_386_TLS_GD
:
10494 case BFD_RELOC_386_TLS_LDM
:
10495 case BFD_RELOC_386_TLS_IE_32
:
10496 case BFD_RELOC_386_TLS_IE
:
10497 case BFD_RELOC_386_TLS_GOTIE
:
10498 case BFD_RELOC_386_TLS_GOTDESC
:
10499 case BFD_RELOC_X86_64_TLSGD
:
10500 case BFD_RELOC_X86_64_TLSLD
:
10501 case BFD_RELOC_X86_64_GOTTPOFF
:
10502 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
10503 value
= 0; /* Fully resolved at runtime. No addend. */
10505 case BFD_RELOC_386_TLS_LE
:
10506 case BFD_RELOC_386_TLS_LDO_32
:
10507 case BFD_RELOC_386_TLS_LE_32
:
10508 case BFD_RELOC_X86_64_DTPOFF32
:
10509 case BFD_RELOC_X86_64_DTPOFF64
:
10510 case BFD_RELOC_X86_64_TPOFF32
:
10511 case BFD_RELOC_X86_64_TPOFF64
:
10512 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
10515 case BFD_RELOC_386_TLS_DESC_CALL
:
10516 case BFD_RELOC_X86_64_TLSDESC_CALL
:
10517 value
= 0; /* Fully resolved at runtime. No addend. */
10518 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
10522 case BFD_RELOC_VTABLE_INHERIT
:
10523 case BFD_RELOC_VTABLE_ENTRY
:
10530 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
10532 #endif /* !defined (TE_Mach) */
10534 /* Are we finished with this relocation now? */
10535 if (fixP
->fx_addsy
== NULL
)
10537 #if defined (OBJ_COFF) && defined (TE_PE)
10538 else if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
10541 /* Remember value for tc_gen_reloc. */
10542 fixP
->fx_addnumber
= value
;
10543 /* Clear out the frag for now. */
10547 else if (use_rela_relocations
)
10549 fixP
->fx_no_overflow
= 1;
10550 /* Remember value for tc_gen_reloc. */
10551 fixP
->fx_addnumber
= value
;
10555 md_number_to_chars (p
, value
, fixP
->fx_size
);
10559 md_atof (int type
, char *litP
, int *sizeP
)
10561 /* This outputs the LITTLENUMs in REVERSE order;
10562 in accord with the bigendian 386. */
10563 return ieee_md_atof (type
, litP
, sizeP
, FALSE
);
10566 static char output_invalid_buf
[sizeof (unsigned char) * 2 + 6];
10569 output_invalid (int c
)
10572 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
10575 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
10576 "(0x%x)", (unsigned char) c
);
10577 return output_invalid_buf
;
10580 /* REG_STRING starts *before* REGISTER_PREFIX. */
10582 static const reg_entry
*
10583 parse_real_register (char *reg_string
, char **end_op
)
10585 char *s
= reg_string
;
10587 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
10588 const reg_entry
*r
;
10590 /* Skip possible REGISTER_PREFIX and possible whitespace. */
10591 if (*s
== REGISTER_PREFIX
)
10594 if (is_space_char (*s
))
10597 p
= reg_name_given
;
10598 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
10600 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
10601 return (const reg_entry
*) NULL
;
10605 /* For naked regs, make sure that we are not dealing with an identifier.
10606 This prevents confusing an identifier like `eax_var' with register
10608 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
10609 return (const reg_entry
*) NULL
;
10613 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
10615 /* Handle floating point regs, allowing spaces in the (i) part. */
10616 if (r
== i386_regtab
/* %st is first entry of table */)
10618 if (!cpu_arch_flags
.bitfield
.cpu8087
10619 && !cpu_arch_flags
.bitfield
.cpu287
10620 && !cpu_arch_flags
.bitfield
.cpu387
)
10621 return (const reg_entry
*) NULL
;
10623 if (is_space_char (*s
))
10628 if (is_space_char (*s
))
10630 if (*s
>= '0' && *s
<= '7')
10632 int fpr
= *s
- '0';
10634 if (is_space_char (*s
))
10639 r
= (const reg_entry
*) hash_find (reg_hash
, "st(0)");
10644 /* We have "%st(" then garbage. */
10645 return (const reg_entry
*) NULL
;
10649 if (r
== NULL
|| allow_pseudo_reg
)
10652 if (operand_type_all_zero (&r
->reg_type
))
10653 return (const reg_entry
*) NULL
;
10655 if ((r
->reg_type
.bitfield
.dword
10656 || r
->reg_type
.bitfield
.sreg3
10657 || r
->reg_type
.bitfield
.control
10658 || r
->reg_type
.bitfield
.debug
10659 || r
->reg_type
.bitfield
.test
)
10660 && !cpu_arch_flags
.bitfield
.cpui386
)
10661 return (const reg_entry
*) NULL
;
10663 if (r
->reg_type
.bitfield
.regmmx
&& !cpu_arch_flags
.bitfield
.cpummx
)
10664 return (const reg_entry
*) NULL
;
10666 if (!cpu_arch_flags
.bitfield
.cpuavx512f
)
10668 if (r
->reg_type
.bitfield
.zmmword
|| r
->reg_type
.bitfield
.regmask
)
10669 return (const reg_entry
*) NULL
;
10671 if (!cpu_arch_flags
.bitfield
.cpuavx
)
10673 if (r
->reg_type
.bitfield
.ymmword
)
10674 return (const reg_entry
*) NULL
;
10676 if (!cpu_arch_flags
.bitfield
.cpusse
&& r
->reg_type
.bitfield
.xmmword
)
10677 return (const reg_entry
*) NULL
;
10681 if (r
->reg_type
.bitfield
.regbnd
&& !cpu_arch_flags
.bitfield
.cpumpx
)
10682 return (const reg_entry
*) NULL
;
10684 /* Don't allow fake index register unless allow_index_reg isn't 0. */
10685 if (!allow_index_reg
&& r
->reg_num
== RegIZ
)
10686 return (const reg_entry
*) NULL
;
10688 /* Upper 16 vector registers are only available with VREX in 64bit
10689 mode, and require EVEX encoding. */
10690 if (r
->reg_flags
& RegVRex
)
10692 if (!cpu_arch_flags
.bitfield
.cpuavx512f
10693 || flag_code
!= CODE_64BIT
)
10694 return (const reg_entry
*) NULL
;
10696 i
.vec_encoding
= vex_encoding_evex
;
10699 if (((r
->reg_flags
& (RegRex64
| RegRex
)) || r
->reg_type
.bitfield
.qword
)
10700 && (!cpu_arch_flags
.bitfield
.cpulm
|| !r
->reg_type
.bitfield
.control
)
10701 && flag_code
!= CODE_64BIT
)
10702 return (const reg_entry
*) NULL
;
10704 if (r
->reg_type
.bitfield
.sreg3
&& r
->reg_num
== RegFlat
&& !intel_syntax
)
10705 return (const reg_entry
*) NULL
;
10710 /* REG_STRING starts *before* REGISTER_PREFIX. */
10712 static const reg_entry
*
10713 parse_register (char *reg_string
, char **end_op
)
10715 const reg_entry
*r
;
10717 if (*reg_string
== REGISTER_PREFIX
|| allow_naked_reg
)
10718 r
= parse_real_register (reg_string
, end_op
);
10723 char *save
= input_line_pointer
;
10727 input_line_pointer
= reg_string
;
10728 c
= get_symbol_name (®_string
);
10729 symbolP
= symbol_find (reg_string
);
10730 if (symbolP
&& S_GET_SEGMENT (symbolP
) == reg_section
)
10732 const expressionS
*e
= symbol_get_value_expression (symbolP
);
10734 know (e
->X_op
== O_register
);
10735 know (e
->X_add_number
>= 0
10736 && (valueT
) e
->X_add_number
< i386_regtab_size
);
10737 r
= i386_regtab
+ e
->X_add_number
;
10738 if ((r
->reg_flags
& RegVRex
))
10739 i
.vec_encoding
= vex_encoding_evex
;
10740 *end_op
= input_line_pointer
;
10742 *input_line_pointer
= c
;
10743 input_line_pointer
= save
;
10749 i386_parse_name (char *name
, expressionS
*e
, char *nextcharP
)
10751 const reg_entry
*r
;
10752 char *end
= input_line_pointer
;
10755 r
= parse_register (name
, &input_line_pointer
);
10756 if (r
&& end
<= input_line_pointer
)
10758 *nextcharP
= *input_line_pointer
;
10759 *input_line_pointer
= 0;
10760 e
->X_op
= O_register
;
10761 e
->X_add_number
= r
- i386_regtab
;
10764 input_line_pointer
= end
;
10766 return intel_syntax
? i386_intel_parse_name (name
, e
) : 0;
10770 md_operand (expressionS
*e
)
10773 const reg_entry
*r
;
10775 switch (*input_line_pointer
)
10777 case REGISTER_PREFIX
:
10778 r
= parse_real_register (input_line_pointer
, &end
);
10781 e
->X_op
= O_register
;
10782 e
->X_add_number
= r
- i386_regtab
;
10783 input_line_pointer
= end
;
10788 gas_assert (intel_syntax
);
10789 end
= input_line_pointer
++;
10791 if (*input_line_pointer
== ']')
10793 ++input_line_pointer
;
10794 e
->X_op_symbol
= make_expr_symbol (e
);
10795 e
->X_add_symbol
= NULL
;
10796 e
->X_add_number
= 0;
10801 e
->X_op
= O_absent
;
10802 input_line_pointer
= end
;
10809 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10810 const char *md_shortopts
= "kVQ:sqnO::";
10812 const char *md_shortopts
= "qnO::";
10815 #define OPTION_32 (OPTION_MD_BASE + 0)
10816 #define OPTION_64 (OPTION_MD_BASE + 1)
10817 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
10818 #define OPTION_MARCH (OPTION_MD_BASE + 3)
10819 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
10820 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
10821 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
10822 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
10823 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
10824 #define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 9)
10825 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
10826 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
10827 #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
10828 #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
10829 #define OPTION_X32 (OPTION_MD_BASE + 14)
10830 #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
10831 #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
10832 #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
10833 #define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
10834 #define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
10835 #define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
10836 #define OPTION_MSHARED (OPTION_MD_BASE + 21)
10837 #define OPTION_MAMD64 (OPTION_MD_BASE + 22)
10838 #define OPTION_MINTEL64 (OPTION_MD_BASE + 23)
10839 #define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24)
10840 #define OPTION_X86_USED_NOTE (OPTION_MD_BASE + 25)
10842 struct option md_longopts
[] =
10844 {"32", no_argument
, NULL
, OPTION_32
},
10845 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10846 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
10847 {"64", no_argument
, NULL
, OPTION_64
},
10849 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10850 {"x32", no_argument
, NULL
, OPTION_X32
},
10851 {"mshared", no_argument
, NULL
, OPTION_MSHARED
},
10852 {"mx86-used-note", required_argument
, NULL
, OPTION_X86_USED_NOTE
},
10854 {"divide", no_argument
, NULL
, OPTION_DIVIDE
},
10855 {"march", required_argument
, NULL
, OPTION_MARCH
},
10856 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
10857 {"mmnemonic", required_argument
, NULL
, OPTION_MMNEMONIC
},
10858 {"msyntax", required_argument
, NULL
, OPTION_MSYNTAX
},
10859 {"mindex-reg", no_argument
, NULL
, OPTION_MINDEX_REG
},
10860 {"mnaked-reg", no_argument
, NULL
, OPTION_MNAKED_REG
},
10861 {"msse2avx", no_argument
, NULL
, OPTION_MSSE2AVX
},
10862 {"msse-check", required_argument
, NULL
, OPTION_MSSE_CHECK
},
10863 {"moperand-check", required_argument
, NULL
, OPTION_MOPERAND_CHECK
},
10864 {"mavxscalar", required_argument
, NULL
, OPTION_MAVXSCALAR
},
10865 {"madd-bnd-prefix", no_argument
, NULL
, OPTION_MADD_BND_PREFIX
},
10866 {"mevexlig", required_argument
, NULL
, OPTION_MEVEXLIG
},
10867 {"mevexwig", required_argument
, NULL
, OPTION_MEVEXWIG
},
10868 # if defined (TE_PE) || defined (TE_PEP)
10869 {"mbig-obj", no_argument
, NULL
, OPTION_MBIG_OBJ
},
10871 {"momit-lock-prefix", required_argument
, NULL
, OPTION_MOMIT_LOCK_PREFIX
},
10872 {"mfence-as-lock-add", required_argument
, NULL
, OPTION_MFENCE_AS_LOCK_ADD
},
10873 {"mrelax-relocations", required_argument
, NULL
, OPTION_MRELAX_RELOCATIONS
},
10874 {"mevexrcig", required_argument
, NULL
, OPTION_MEVEXRCIG
},
10875 {"mamd64", no_argument
, NULL
, OPTION_MAMD64
},
10876 {"mintel64", no_argument
, NULL
, OPTION_MINTEL64
},
10877 {NULL
, no_argument
, NULL
, 0}
10879 size_t md_longopts_size
= sizeof (md_longopts
);
10882 md_parse_option (int c
, const char *arg
)
10885 char *arch
, *next
, *saved
;
10890 optimize_align_code
= 0;
10894 quiet_warnings
= 1;
10897 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10898 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
10899 should be emitted or not. FIXME: Not implemented. */
10903 /* -V: SVR4 argument to print version ID. */
10905 print_version_id ();
10908 /* -k: Ignore for FreeBSD compatibility. */
10913 /* -s: On i386 Solaris, this tells the native assembler to use
10914 .stab instead of .stab.excl. We always use .stab anyhow. */
10917 case OPTION_MSHARED
:
10921 case OPTION_X86_USED_NOTE
:
10922 if (strcasecmp (arg
, "yes") == 0)
10924 else if (strcasecmp (arg
, "no") == 0)
10927 as_fatal (_("invalid -mx86-used-note= option: `%s'"), arg
);
10932 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10933 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
10936 const char **list
, **l
;
10938 list
= bfd_target_list ();
10939 for (l
= list
; *l
!= NULL
; l
++)
10940 if (CONST_STRNEQ (*l
, "elf64-x86-64")
10941 || strcmp (*l
, "coff-x86-64") == 0
10942 || strcmp (*l
, "pe-x86-64") == 0
10943 || strcmp (*l
, "pei-x86-64") == 0
10944 || strcmp (*l
, "mach-o-x86-64") == 0)
10946 default_arch
= "x86_64";
10950 as_fatal (_("no compiled in support for x86_64"));
10956 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10960 const char **list
, **l
;
10962 list
= bfd_target_list ();
10963 for (l
= list
; *l
!= NULL
; l
++)
10964 if (CONST_STRNEQ (*l
, "elf32-x86-64"))
10966 default_arch
= "x86_64:32";
10970 as_fatal (_("no compiled in support for 32bit x86_64"));
10974 as_fatal (_("32bit x86_64 is only supported for ELF"));
10979 default_arch
= "i386";
10982 case OPTION_DIVIDE
:
10983 #ifdef SVR4_COMMENT_CHARS
10988 n
= XNEWVEC (char, strlen (i386_comment_chars
) + 1);
10990 for (s
= i386_comment_chars
; *s
!= '\0'; s
++)
10994 i386_comment_chars
= n
;
11000 saved
= xstrdup (arg
);
11002 /* Allow -march=+nosse. */
11008 as_fatal (_("invalid -march= option: `%s'"), arg
);
11009 next
= strchr (arch
, '+');
11012 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
11014 if (strcmp (arch
, cpu_arch
[j
].name
) == 0)
11017 if (! cpu_arch
[j
].flags
.bitfield
.cpui386
)
11020 cpu_arch_name
= cpu_arch
[j
].name
;
11021 cpu_sub_arch_name
= NULL
;
11022 cpu_arch_flags
= cpu_arch
[j
].flags
;
11023 cpu_arch_isa
= cpu_arch
[j
].type
;
11024 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
11025 if (!cpu_arch_tune_set
)
11027 cpu_arch_tune
= cpu_arch_isa
;
11028 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
11032 else if (*cpu_arch
[j
].name
== '.'
11033 && strcmp (arch
, cpu_arch
[j
].name
+ 1) == 0)
11035 /* ISA extension. */
11036 i386_cpu_flags flags
;
11038 flags
= cpu_flags_or (cpu_arch_flags
,
11039 cpu_arch
[j
].flags
);
11041 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
11043 if (cpu_sub_arch_name
)
11045 char *name
= cpu_sub_arch_name
;
11046 cpu_sub_arch_name
= concat (name
,
11048 (const char *) NULL
);
11052 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
11053 cpu_arch_flags
= flags
;
11054 cpu_arch_isa_flags
= flags
;
11058 = cpu_flags_or (cpu_arch_isa_flags
,
11059 cpu_arch
[j
].flags
);
11064 if (j
>= ARRAY_SIZE (cpu_arch
))
11066 /* Disable an ISA extension. */
11067 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
11068 if (strcmp (arch
, cpu_noarch
[j
].name
) == 0)
11070 i386_cpu_flags flags
;
11072 flags
= cpu_flags_and_not (cpu_arch_flags
,
11073 cpu_noarch
[j
].flags
);
11074 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
11076 if (cpu_sub_arch_name
)
11078 char *name
= cpu_sub_arch_name
;
11079 cpu_sub_arch_name
= concat (arch
,
11080 (const char *) NULL
);
11084 cpu_sub_arch_name
= xstrdup (arch
);
11085 cpu_arch_flags
= flags
;
11086 cpu_arch_isa_flags
= flags
;
11091 if (j
>= ARRAY_SIZE (cpu_noarch
))
11092 j
= ARRAY_SIZE (cpu_arch
);
11095 if (j
>= ARRAY_SIZE (cpu_arch
))
11096 as_fatal (_("invalid -march= option: `%s'"), arg
);
11100 while (next
!= NULL
);
11106 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
11107 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
11109 if (strcmp (arg
, cpu_arch
[j
].name
) == 0)
11111 cpu_arch_tune_set
= 1;
11112 cpu_arch_tune
= cpu_arch
[j
].type
;
11113 cpu_arch_tune_flags
= cpu_arch
[j
].flags
;
11117 if (j
>= ARRAY_SIZE (cpu_arch
))
11118 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
11121 case OPTION_MMNEMONIC
:
11122 if (strcasecmp (arg
, "att") == 0)
11123 intel_mnemonic
= 0;
11124 else if (strcasecmp (arg
, "intel") == 0)
11125 intel_mnemonic
= 1;
11127 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg
);
11130 case OPTION_MSYNTAX
:
11131 if (strcasecmp (arg
, "att") == 0)
11133 else if (strcasecmp (arg
, "intel") == 0)
11136 as_fatal (_("invalid -msyntax= option: `%s'"), arg
);
11139 case OPTION_MINDEX_REG
:
11140 allow_index_reg
= 1;
11143 case OPTION_MNAKED_REG
:
11144 allow_naked_reg
= 1;
11147 case OPTION_MSSE2AVX
:
11151 case OPTION_MSSE_CHECK
:
11152 if (strcasecmp (arg
, "error") == 0)
11153 sse_check
= check_error
;
11154 else if (strcasecmp (arg
, "warning") == 0)
11155 sse_check
= check_warning
;
11156 else if (strcasecmp (arg
, "none") == 0)
11157 sse_check
= check_none
;
11159 as_fatal (_("invalid -msse-check= option: `%s'"), arg
);
11162 case OPTION_MOPERAND_CHECK
:
11163 if (strcasecmp (arg
, "error") == 0)
11164 operand_check
= check_error
;
11165 else if (strcasecmp (arg
, "warning") == 0)
11166 operand_check
= check_warning
;
11167 else if (strcasecmp (arg
, "none") == 0)
11168 operand_check
= check_none
;
11170 as_fatal (_("invalid -moperand-check= option: `%s'"), arg
);
11173 case OPTION_MAVXSCALAR
:
11174 if (strcasecmp (arg
, "128") == 0)
11175 avxscalar
= vex128
;
11176 else if (strcasecmp (arg
, "256") == 0)
11177 avxscalar
= vex256
;
11179 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg
);
11182 case OPTION_MADD_BND_PREFIX
:
11183 add_bnd_prefix
= 1;
11186 case OPTION_MEVEXLIG
:
11187 if (strcmp (arg
, "128") == 0)
11188 evexlig
= evexl128
;
11189 else if (strcmp (arg
, "256") == 0)
11190 evexlig
= evexl256
;
11191 else if (strcmp (arg
, "512") == 0)
11192 evexlig
= evexl512
;
11194 as_fatal (_("invalid -mevexlig= option: `%s'"), arg
);
11197 case OPTION_MEVEXRCIG
:
11198 if (strcmp (arg
, "rne") == 0)
11200 else if (strcmp (arg
, "rd") == 0)
11202 else if (strcmp (arg
, "ru") == 0)
11204 else if (strcmp (arg
, "rz") == 0)
11207 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg
);
11210 case OPTION_MEVEXWIG
:
11211 if (strcmp (arg
, "0") == 0)
11213 else if (strcmp (arg
, "1") == 0)
11216 as_fatal (_("invalid -mevexwig= option: `%s'"), arg
);
11219 # if defined (TE_PE) || defined (TE_PEP)
11220 case OPTION_MBIG_OBJ
:
11225 case OPTION_MOMIT_LOCK_PREFIX
:
11226 if (strcasecmp (arg
, "yes") == 0)
11227 omit_lock_prefix
= 1;
11228 else if (strcasecmp (arg
, "no") == 0)
11229 omit_lock_prefix
= 0;
11231 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg
);
11234 case OPTION_MFENCE_AS_LOCK_ADD
:
11235 if (strcasecmp (arg
, "yes") == 0)
11237 else if (strcasecmp (arg
, "no") == 0)
11240 as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg
);
11243 case OPTION_MRELAX_RELOCATIONS
:
11244 if (strcasecmp (arg
, "yes") == 0)
11245 generate_relax_relocations
= 1;
11246 else if (strcasecmp (arg
, "no") == 0)
11247 generate_relax_relocations
= 0;
11249 as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg
);
11252 case OPTION_MAMD64
:
11256 case OPTION_MINTEL64
:
11264 /* Turn off -Os. */
11265 optimize_for_space
= 0;
11267 else if (*arg
== 's')
11269 optimize_for_space
= 1;
11270 /* Turn on all encoding optimizations. */
11275 optimize
= atoi (arg
);
11276 /* Turn off -Os. */
11277 optimize_for_space
= 0;
11287 #define MESSAGE_TEMPLATE \
11291 output_message (FILE *stream
, char *p
, char *message
, char *start
,
11292 int *left_p
, const char *name
, int len
)
11294 int size
= sizeof (MESSAGE_TEMPLATE
);
11295 int left
= *left_p
;
11297 /* Reserve 2 spaces for ", " or ",\0" */
11300 /* Check if there is any room. */
11308 p
= mempcpy (p
, name
, len
);
11312 /* Output the current message now and start a new one. */
11315 fprintf (stream
, "%s\n", message
);
11317 left
= size
- (start
- message
) - len
- 2;
11319 gas_assert (left
>= 0);
11321 p
= mempcpy (p
, name
, len
);
11329 show_arch (FILE *stream
, int ext
, int check
)
11331 static char message
[] = MESSAGE_TEMPLATE
;
11332 char *start
= message
+ 27;
11334 int size
= sizeof (MESSAGE_TEMPLATE
);
11341 left
= size
- (start
- message
);
11342 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
11344 /* Should it be skipped? */
11345 if (cpu_arch
[j
].skip
)
11348 name
= cpu_arch
[j
].name
;
11349 len
= cpu_arch
[j
].len
;
11352 /* It is an extension. Skip if we aren't asked to show it. */
11363 /* It is an processor. Skip if we show only extension. */
11366 else if (check
&& ! cpu_arch
[j
].flags
.bitfield
.cpui386
)
11368 /* It is an impossible processor - skip. */
11372 p
= output_message (stream
, p
, message
, start
, &left
, name
, len
);
11375 /* Display disabled extensions. */
11377 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
11379 name
= cpu_noarch
[j
].name
;
11380 len
= cpu_noarch
[j
].len
;
11381 p
= output_message (stream
, p
, message
, start
, &left
, name
,
11386 fprintf (stream
, "%s\n", message
);
11390 md_show_usage (FILE *stream
)
11392 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11393 fprintf (stream
, _("\
11395 -V print assembler version number\n\
11398 fprintf (stream
, _("\
11399 -n Do not optimize code alignment\n\
11400 -q quieten some warnings\n"));
11401 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11402 fprintf (stream
, _("\
11405 #if defined BFD64 && (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
11406 || defined (TE_PE) || defined (TE_PEP))
11407 fprintf (stream
, _("\
11408 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
11410 #ifdef SVR4_COMMENT_CHARS
11411 fprintf (stream
, _("\
11412 --divide do not treat `/' as a comment character\n"));
11414 fprintf (stream
, _("\
11415 --divide ignored\n"));
11417 fprintf (stream
, _("\
11418 -march=CPU[,+EXTENSION...]\n\
11419 generate code for CPU and EXTENSION, CPU is one of:\n"));
11420 show_arch (stream
, 0, 1);
11421 fprintf (stream
, _("\
11422 EXTENSION is combination of:\n"));
11423 show_arch (stream
, 1, 0);
11424 fprintf (stream
, _("\
11425 -mtune=CPU optimize for CPU, CPU is one of:\n"));
11426 show_arch (stream
, 0, 0);
11427 fprintf (stream
, _("\
11428 -msse2avx encode SSE instructions with VEX prefix\n"));
11429 fprintf (stream
, _("\
11430 -msse-check=[none|error|warning] (default: warning)\n\
11431 check SSE instructions\n"));
11432 fprintf (stream
, _("\
11433 -moperand-check=[none|error|warning] (default: warning)\n\
11434 check operand combinations for validity\n"));
11435 fprintf (stream
, _("\
11436 -mavxscalar=[128|256] (default: 128)\n\
11437 encode scalar AVX instructions with specific vector\n\
11439 fprintf (stream
, _("\
11440 -mevexlig=[128|256|512] (default: 128)\n\
11441 encode scalar EVEX instructions with specific vector\n\
11443 fprintf (stream
, _("\
11444 -mevexwig=[0|1] (default: 0)\n\
11445 encode EVEX instructions with specific EVEX.W value\n\
11446 for EVEX.W bit ignored instructions\n"));
11447 fprintf (stream
, _("\
11448 -mevexrcig=[rne|rd|ru|rz] (default: rne)\n\
11449 encode EVEX instructions with specific EVEX.RC value\n\
11450 for SAE-only ignored instructions\n"));
11451 fprintf (stream
, _("\
11452 -mmnemonic=[att|intel] "));
11453 if (SYSV386_COMPAT
)
11454 fprintf (stream
, _("(default: att)\n"));
11456 fprintf (stream
, _("(default: intel)\n"));
11457 fprintf (stream
, _("\
11458 use AT&T/Intel mnemonic\n"));
11459 fprintf (stream
, _("\
11460 -msyntax=[att|intel] (default: att)\n\
11461 use AT&T/Intel syntax\n"));
11462 fprintf (stream
, _("\
11463 -mindex-reg support pseudo index registers\n"));
11464 fprintf (stream
, _("\
11465 -mnaked-reg don't require `%%' prefix for registers\n"));
11466 fprintf (stream
, _("\
11467 -madd-bnd-prefix add BND prefix for all valid branches\n"));
11468 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11469 fprintf (stream
, _("\
11470 -mshared disable branch optimization for shared code\n"));
11471 fprintf (stream
, _("\
11472 -mx86-used-note=[no|yes] "));
11473 if (DEFAULT_X86_USED_NOTE
)
11474 fprintf (stream
, _("(default: yes)\n"));
11476 fprintf (stream
, _("(default: no)\n"));
11477 fprintf (stream
, _("\
11478 generate x86 used ISA and feature properties\n"));
11480 #if defined (TE_PE) || defined (TE_PEP)
11481 fprintf (stream
, _("\
11482 -mbig-obj generate big object files\n"));
11484 fprintf (stream
, _("\
11485 -momit-lock-prefix=[no|yes] (default: no)\n\
11486 strip all lock prefixes\n"));
11487 fprintf (stream
, _("\
11488 -mfence-as-lock-add=[no|yes] (default: no)\n\
11489 encode lfence, mfence and sfence as\n\
11490 lock addl $0x0, (%%{re}sp)\n"));
11491 fprintf (stream
, _("\
11492 -mrelax-relocations=[no|yes] "));
11493 if (DEFAULT_GENERATE_X86_RELAX_RELOCATIONS
)
11494 fprintf (stream
, _("(default: yes)\n"));
11496 fprintf (stream
, _("(default: no)\n"));
11497 fprintf (stream
, _("\
11498 generate relax relocations\n"));
11499 fprintf (stream
, _("\
11500 -mamd64 accept only AMD64 ISA [default]\n"));
11501 fprintf (stream
, _("\
11502 -mintel64 accept only Intel64 ISA\n"));
11505 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
11506 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
11507 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
11509 /* Pick the target format to use. */
11512 i386_target_format (void)
11514 if (!strncmp (default_arch
, "x86_64", 6))
11516 update_code_flag (CODE_64BIT
, 1);
11517 if (default_arch
[6] == '\0')
11518 x86_elf_abi
= X86_64_ABI
;
11520 x86_elf_abi
= X86_64_X32_ABI
;
11522 else if (!strcmp (default_arch
, "i386"))
11523 update_code_flag (CODE_32BIT
, 1);
11524 else if (!strcmp (default_arch
, "iamcu"))
11526 update_code_flag (CODE_32BIT
, 1);
11527 if (cpu_arch_isa
== PROCESSOR_UNKNOWN
)
11529 static const i386_cpu_flags iamcu_flags
= CPU_IAMCU_FLAGS
;
11530 cpu_arch_name
= "iamcu";
11531 cpu_sub_arch_name
= NULL
;
11532 cpu_arch_flags
= iamcu_flags
;
11533 cpu_arch_isa
= PROCESSOR_IAMCU
;
11534 cpu_arch_isa_flags
= iamcu_flags
;
11535 if (!cpu_arch_tune_set
)
11537 cpu_arch_tune
= cpu_arch_isa
;
11538 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
11541 else if (cpu_arch_isa
!= PROCESSOR_IAMCU
)
11542 as_fatal (_("Intel MCU doesn't support `%s' architecture"),
11546 as_fatal (_("unknown architecture"));
11548 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
11549 cpu_arch_isa_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
11550 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
11551 cpu_arch_tune_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
11553 switch (OUTPUT_FLAVOR
)
11555 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
11556 case bfd_target_aout_flavour
:
11557 return AOUT_TARGET_FORMAT
;
11559 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
11560 # if defined (TE_PE) || defined (TE_PEP)
11561 case bfd_target_coff_flavour
:
11562 if (flag_code
== CODE_64BIT
)
11563 return use_big_obj
? "pe-bigobj-x86-64" : "pe-x86-64";
11566 # elif defined (TE_GO32)
11567 case bfd_target_coff_flavour
:
11568 return "coff-go32";
11570 case bfd_target_coff_flavour
:
11571 return "coff-i386";
11574 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
11575 case bfd_target_elf_flavour
:
11577 const char *format
;
11579 switch (x86_elf_abi
)
11582 format
= ELF_TARGET_FORMAT
;
11585 use_rela_relocations
= 1;
11587 format
= ELF_TARGET_FORMAT64
;
11589 case X86_64_X32_ABI
:
11590 use_rela_relocations
= 1;
11592 disallow_64bit_reloc
= 1;
11593 format
= ELF_TARGET_FORMAT32
;
11596 if (cpu_arch_isa
== PROCESSOR_L1OM
)
11598 if (x86_elf_abi
!= X86_64_ABI
)
11599 as_fatal (_("Intel L1OM is 64bit only"));
11600 return ELF_TARGET_L1OM_FORMAT
;
11602 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
11604 if (x86_elf_abi
!= X86_64_ABI
)
11605 as_fatal (_("Intel K1OM is 64bit only"));
11606 return ELF_TARGET_K1OM_FORMAT
;
11608 else if (cpu_arch_isa
== PROCESSOR_IAMCU
)
11610 if (x86_elf_abi
!= I386_ABI
)
11611 as_fatal (_("Intel MCU is 32bit only"));
11612 return ELF_TARGET_IAMCU_FORMAT
;
11618 #if defined (OBJ_MACH_O)
11619 case bfd_target_mach_o_flavour
:
11620 if (flag_code
== CODE_64BIT
)
11622 use_rela_relocations
= 1;
11624 return "mach-o-x86-64";
11627 return "mach-o-i386";
11635 #endif /* OBJ_MAYBE_ more than one */
11638 md_undefined_symbol (char *name
)
11640 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
11641 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
11642 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
11643 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
11647 if (symbol_find (name
))
11648 as_bad (_("GOT already in symbol table"));
11649 GOT_symbol
= symbol_new (name
, undefined_section
,
11650 (valueT
) 0, &zero_address_frag
);
11657 /* Round up a section size to the appropriate boundary. */
11660 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
11662 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
11663 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
11665 /* For a.out, force the section size to be aligned. If we don't do
11666 this, BFD will align it for us, but it will not write out the
11667 final bytes of the section. This may be a bug in BFD, but it is
11668 easier to fix it here since that is how the other a.out targets
11672 align
= bfd_get_section_alignment (stdoutput
, segment
);
11673 size
= ((size
+ (1 << align
) - 1) & (-((valueT
) 1 << align
)));
11680 /* On the i386, PC-relative offsets are relative to the start of the
11681 next instruction. That is, the address of the offset, plus its
11682 size, since the offset is always the last part of the insn. */
11685 md_pcrel_from (fixS
*fixP
)
11687 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
11693 s_bss (int ignore ATTRIBUTE_UNUSED
)
11697 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11699 obj_elf_section_change_hook ();
11701 temp
= get_absolute_expression ();
11702 subseg_set (bss_section
, (subsegT
) temp
);
11703 demand_empty_rest_of_line ();
11709 i386_validate_fix (fixS
*fixp
)
11711 if (fixp
->fx_subsy
)
11713 if (fixp
->fx_subsy
== GOT_symbol
)
11715 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
11719 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11720 if (fixp
->fx_tcbit2
)
11721 fixp
->fx_r_type
= (fixp
->fx_tcbit
11722 ? BFD_RELOC_X86_64_REX_GOTPCRELX
11723 : BFD_RELOC_X86_64_GOTPCRELX
);
11726 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
11731 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
11733 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
11735 fixp
->fx_subsy
= 0;
11738 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11739 else if (!object_64bit
)
11741 if (fixp
->fx_r_type
== BFD_RELOC_386_GOT32
11742 && fixp
->fx_tcbit2
)
11743 fixp
->fx_r_type
= BFD_RELOC_386_GOT32X
;
11749 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
11752 bfd_reloc_code_real_type code
;
11754 switch (fixp
->fx_r_type
)
11756 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11757 case BFD_RELOC_SIZE32
:
11758 case BFD_RELOC_SIZE64
:
11759 if (S_IS_DEFINED (fixp
->fx_addsy
)
11760 && !S_IS_EXTERNAL (fixp
->fx_addsy
))
11762 /* Resolve size relocation against local symbol to size of
11763 the symbol plus addend. */
11764 valueT value
= S_GET_SIZE (fixp
->fx_addsy
) + fixp
->fx_offset
;
11765 if (fixp
->fx_r_type
== BFD_RELOC_SIZE32
11766 && !fits_in_unsigned_long (value
))
11767 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
11768 _("symbol size computation overflow"));
11769 fixp
->fx_addsy
= NULL
;
11770 fixp
->fx_subsy
= NULL
;
11771 md_apply_fix (fixp
, (valueT
*) &value
, NULL
);
11775 /* Fall through. */
11777 case BFD_RELOC_X86_64_PLT32
:
11778 case BFD_RELOC_X86_64_GOT32
:
11779 case BFD_RELOC_X86_64_GOTPCREL
:
11780 case BFD_RELOC_X86_64_GOTPCRELX
:
11781 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
11782 case BFD_RELOC_386_PLT32
:
11783 case BFD_RELOC_386_GOT32
:
11784 case BFD_RELOC_386_GOT32X
:
11785 case BFD_RELOC_386_GOTOFF
:
11786 case BFD_RELOC_386_GOTPC
:
11787 case BFD_RELOC_386_TLS_GD
:
11788 case BFD_RELOC_386_TLS_LDM
:
11789 case BFD_RELOC_386_TLS_LDO_32
:
11790 case BFD_RELOC_386_TLS_IE_32
:
11791 case BFD_RELOC_386_TLS_IE
:
11792 case BFD_RELOC_386_TLS_GOTIE
:
11793 case BFD_RELOC_386_TLS_LE_32
:
11794 case BFD_RELOC_386_TLS_LE
:
11795 case BFD_RELOC_386_TLS_GOTDESC
:
11796 case BFD_RELOC_386_TLS_DESC_CALL
:
11797 case BFD_RELOC_X86_64_TLSGD
:
11798 case BFD_RELOC_X86_64_TLSLD
:
11799 case BFD_RELOC_X86_64_DTPOFF32
:
11800 case BFD_RELOC_X86_64_DTPOFF64
:
11801 case BFD_RELOC_X86_64_GOTTPOFF
:
11802 case BFD_RELOC_X86_64_TPOFF32
:
11803 case BFD_RELOC_X86_64_TPOFF64
:
11804 case BFD_RELOC_X86_64_GOTOFF64
:
11805 case BFD_RELOC_X86_64_GOTPC32
:
11806 case BFD_RELOC_X86_64_GOT64
:
11807 case BFD_RELOC_X86_64_GOTPCREL64
:
11808 case BFD_RELOC_X86_64_GOTPC64
:
11809 case BFD_RELOC_X86_64_GOTPLT64
:
11810 case BFD_RELOC_X86_64_PLTOFF64
:
11811 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
11812 case BFD_RELOC_X86_64_TLSDESC_CALL
:
11813 case BFD_RELOC_RVA
:
11814 case BFD_RELOC_VTABLE_ENTRY
:
11815 case BFD_RELOC_VTABLE_INHERIT
:
11817 case BFD_RELOC_32_SECREL
:
11819 code
= fixp
->fx_r_type
;
11821 case BFD_RELOC_X86_64_32S
:
11822 if (!fixp
->fx_pcrel
)
11824 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
11825 code
= fixp
->fx_r_type
;
11828 /* Fall through. */
11830 if (fixp
->fx_pcrel
)
11832 switch (fixp
->fx_size
)
11835 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
11836 _("can not do %d byte pc-relative relocation"),
11838 code
= BFD_RELOC_32_PCREL
;
11840 case 1: code
= BFD_RELOC_8_PCREL
; break;
11841 case 2: code
= BFD_RELOC_16_PCREL
; break;
11842 case 4: code
= BFD_RELOC_32_PCREL
; break;
11844 case 8: code
= BFD_RELOC_64_PCREL
; break;
11850 switch (fixp
->fx_size
)
11853 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
11854 _("can not do %d byte relocation"),
11856 code
= BFD_RELOC_32
;
11858 case 1: code
= BFD_RELOC_8
; break;
11859 case 2: code
= BFD_RELOC_16
; break;
11860 case 4: code
= BFD_RELOC_32
; break;
11862 case 8: code
= BFD_RELOC_64
; break;
11869 if ((code
== BFD_RELOC_32
11870 || code
== BFD_RELOC_32_PCREL
11871 || code
== BFD_RELOC_X86_64_32S
)
11873 && fixp
->fx_addsy
== GOT_symbol
)
11876 code
= BFD_RELOC_386_GOTPC
;
11878 code
= BFD_RELOC_X86_64_GOTPC32
;
11880 if ((code
== BFD_RELOC_64
|| code
== BFD_RELOC_64_PCREL
)
11882 && fixp
->fx_addsy
== GOT_symbol
)
11884 code
= BFD_RELOC_X86_64_GOTPC64
;
11887 rel
= XNEW (arelent
);
11888 rel
->sym_ptr_ptr
= XNEW (asymbol
*);
11889 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
11891 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
11893 if (!use_rela_relocations
)
11895 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
11896 vtable entry to be used in the relocation's section offset. */
11897 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
11898 rel
->address
= fixp
->fx_offset
;
11899 #if defined (OBJ_COFF) && defined (TE_PE)
11900 else if (fixp
->fx_addsy
&& S_IS_WEAK (fixp
->fx_addsy
))
11901 rel
->addend
= fixp
->fx_addnumber
- (S_GET_VALUE (fixp
->fx_addsy
) * 2);
11906 /* Use the rela in 64bit mode. */
11909 if (disallow_64bit_reloc
)
11912 case BFD_RELOC_X86_64_DTPOFF64
:
11913 case BFD_RELOC_X86_64_TPOFF64
:
11914 case BFD_RELOC_64_PCREL
:
11915 case BFD_RELOC_X86_64_GOTOFF64
:
11916 case BFD_RELOC_X86_64_GOT64
:
11917 case BFD_RELOC_X86_64_GOTPCREL64
:
11918 case BFD_RELOC_X86_64_GOTPC64
:
11919 case BFD_RELOC_X86_64_GOTPLT64
:
11920 case BFD_RELOC_X86_64_PLTOFF64
:
11921 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
11922 _("cannot represent relocation type %s in x32 mode"),
11923 bfd_get_reloc_code_name (code
));
11929 if (!fixp
->fx_pcrel
)
11930 rel
->addend
= fixp
->fx_offset
;
11934 case BFD_RELOC_X86_64_PLT32
:
11935 case BFD_RELOC_X86_64_GOT32
:
11936 case BFD_RELOC_X86_64_GOTPCREL
:
11937 case BFD_RELOC_X86_64_GOTPCRELX
:
11938 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
11939 case BFD_RELOC_X86_64_TLSGD
:
11940 case BFD_RELOC_X86_64_TLSLD
:
11941 case BFD_RELOC_X86_64_GOTTPOFF
:
11942 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
11943 case BFD_RELOC_X86_64_TLSDESC_CALL
:
11944 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
11947 rel
->addend
= (section
->vma
11949 + fixp
->fx_addnumber
11950 + md_pcrel_from (fixp
));
11955 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
11956 if (rel
->howto
== NULL
)
11958 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
11959 _("cannot represent relocation type %s"),
11960 bfd_get_reloc_code_name (code
));
11961 /* Set howto to a garbage value so that we can keep going. */
11962 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
11963 gas_assert (rel
->howto
!= NULL
);
11969 #include "tc-i386-intel.c"
11972 tc_x86_parse_to_dw2regnum (expressionS
*exp
)
11974 int saved_naked_reg
;
11975 char saved_register_dot
;
11977 saved_naked_reg
= allow_naked_reg
;
11978 allow_naked_reg
= 1;
11979 saved_register_dot
= register_chars
['.'];
11980 register_chars
['.'] = '.';
11981 allow_pseudo_reg
= 1;
11982 expression_and_evaluate (exp
);
11983 allow_pseudo_reg
= 0;
11984 register_chars
['.'] = saved_register_dot
;
11985 allow_naked_reg
= saved_naked_reg
;
11987 if (exp
->X_op
== O_register
&& exp
->X_add_number
>= 0)
11989 if ((addressT
) exp
->X_add_number
< i386_regtab_size
)
11991 exp
->X_op
= O_constant
;
11992 exp
->X_add_number
= i386_regtab
[exp
->X_add_number
]
11993 .dw2_regnum
[flag_code
>> 1];
11996 exp
->X_op
= O_illegal
;
12001 tc_x86_frame_initial_instructions (void)
12003 static unsigned int sp_regno
[2];
12005 if (!sp_regno
[flag_code
>> 1])
12007 char *saved_input
= input_line_pointer
;
12008 char sp
[][4] = {"esp", "rsp"};
12011 input_line_pointer
= sp
[flag_code
>> 1];
12012 tc_x86_parse_to_dw2regnum (&exp
);
12013 gas_assert (exp
.X_op
== O_constant
);
12014 sp_regno
[flag_code
>> 1] = exp
.X_add_number
;
12015 input_line_pointer
= saved_input
;
12018 cfi_add_CFA_def_cfa (sp_regno
[flag_code
>> 1], -x86_cie_data_alignment
);
12019 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
12023 x86_dwarf2_addr_size (void)
12025 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
12026 if (x86_elf_abi
== X86_64_X32_ABI
)
12029 return bfd_arch_bits_per_address (stdoutput
) / 8;
12033 i386_elf_section_type (const char *str
, size_t len
)
12035 if (flag_code
== CODE_64BIT
12036 && len
== sizeof ("unwind") - 1
12037 && strncmp (str
, "unwind", 6) == 0)
12038 return SHT_X86_64_UNWIND
;
12045 i386_solaris_fix_up_eh_frame (segT sec
)
12047 if (flag_code
== CODE_64BIT
)
12048 elf_section_type (sec
) = SHT_X86_64_UNWIND
;
12054 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
12058 exp
.X_op
= O_secrel
;
12059 exp
.X_add_symbol
= symbol
;
12060 exp
.X_add_number
= 0;
12061 emit_expr (&exp
, size
);
12065 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12066 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
12069 x86_64_section_letter (int letter
, const char **ptr_msg
)
12071 if (flag_code
== CODE_64BIT
)
12074 return SHF_X86_64_LARGE
;
12076 *ptr_msg
= _("bad .section directive: want a,l,w,x,M,S,G,T in string");
12079 *ptr_msg
= _("bad .section directive: want a,w,x,M,S,G,T in string");
12084 x86_64_section_word (char *str
, size_t len
)
12086 if (len
== 5 && flag_code
== CODE_64BIT
&& CONST_STRNEQ (str
, "large"))
12087 return SHF_X86_64_LARGE
;
12093 handle_large_common (int small ATTRIBUTE_UNUSED
)
12095 if (flag_code
!= CODE_64BIT
)
12097 s_comm_internal (0, elf_common_parse
);
12098 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
12102 static segT lbss_section
;
12103 asection
*saved_com_section_ptr
= elf_com_section_ptr
;
12104 asection
*saved_bss_section
= bss_section
;
12106 if (lbss_section
== NULL
)
12108 flagword applicable
;
12109 segT seg
= now_seg
;
12110 subsegT subseg
= now_subseg
;
12112 /* The .lbss section is for local .largecomm symbols. */
12113 lbss_section
= subseg_new (".lbss", 0);
12114 applicable
= bfd_applicable_section_flags (stdoutput
);
12115 bfd_set_section_flags (stdoutput
, lbss_section
,
12116 applicable
& SEC_ALLOC
);
12117 seg_info (lbss_section
)->bss
= 1;
12119 subseg_set (seg
, subseg
);
12122 elf_com_section_ptr
= &_bfd_elf_large_com_section
;
12123 bss_section
= lbss_section
;
12125 s_comm_internal (0, elf_common_parse
);
12127 elf_com_section_ptr
= saved_com_section_ptr
;
12128 bss_section
= saved_bss_section
;
12131 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */