1 /* i386.c -- Assemble code for the Intel 80386
2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005, 2006
4 Free Software Foundation, Inc.
6 This file is part of GAS, the GNU Assembler.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
23 /* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
25 x86_64 support by Jan Hubicka (jh@suse.cz)
26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
27 Bugs & suggestions are completely welcome. This is free software.
28 Please help us make it better. */
31 #include "safe-ctype.h"
33 #include "dwarf2dbg.h"
34 #include "dw2gencfi.h"
35 #include "opcode/i386.h"
36 #include "elf/x86-64.h"
38 #ifndef REGISTER_WARNINGS
39 #define REGISTER_WARNINGS 1
42 #ifndef INFER_ADDR_PREFIX
43 #define INFER_ADDR_PREFIX 1
46 #ifndef SCALE1_WHEN_NO_INDEX
47 /* Specifying a scale factor besides 1 when there is no index is
48 futile. eg. `mov (%ebx,2),%al' does exactly the same as
49 `mov (%ebx),%al'. To slavishly follow what the programmer
50 specified, set SCALE1_WHEN_NO_INDEX to 0. */
51 #define SCALE1_WHEN_NO_INDEX 1
55 #define DEFAULT_ARCH "i386"
60 #define INLINE __inline__
66 static INLINE
unsigned int mode_from_disp_size
PARAMS ((unsigned int));
67 static INLINE
int fits_in_signed_byte
PARAMS ((offsetT
));
68 static INLINE
int fits_in_unsigned_byte
PARAMS ((offsetT
));
69 static INLINE
int fits_in_unsigned_word
PARAMS ((offsetT
));
70 static INLINE
int fits_in_signed_word
PARAMS ((offsetT
));
71 static INLINE
int fits_in_unsigned_long
PARAMS ((offsetT
));
72 static INLINE
int fits_in_signed_long
PARAMS ((offsetT
));
73 static int smallest_imm_type
PARAMS ((offsetT
));
74 static offsetT offset_in_range
PARAMS ((offsetT
, int));
75 static int add_prefix
PARAMS ((unsigned int));
76 static void set_code_flag
PARAMS ((int));
77 static void set_16bit_gcc_code_flag
PARAMS ((int));
78 static void set_intel_syntax
PARAMS ((int));
79 static void set_cpu_arch
PARAMS ((int));
81 static void pe_directive_secrel
PARAMS ((int));
83 static void signed_cons
PARAMS ((int));
84 static char *output_invalid
PARAMS ((int c
));
85 static int i386_operand
PARAMS ((char *operand_string
));
86 static int i386_intel_operand
PARAMS ((char *operand_string
, int got_a_float
));
87 static const reg_entry
*parse_register
PARAMS ((char *reg_string
,
89 static char *parse_insn
PARAMS ((char *, char *));
90 static char *parse_operands
PARAMS ((char *, const char *));
91 static void swap_operands
PARAMS ((void));
92 static void optimize_imm
PARAMS ((void));
93 static void optimize_disp
PARAMS ((void));
94 static int match_template
PARAMS ((void));
95 static int check_string
PARAMS ((void));
96 static int process_suffix
PARAMS ((void));
97 static int check_byte_reg
PARAMS ((void));
98 static int check_long_reg
PARAMS ((void));
99 static int check_qword_reg
PARAMS ((void));
100 static int check_word_reg
PARAMS ((void));
101 static int finalize_imm
PARAMS ((void));
102 static int process_operands
PARAMS ((void));
103 static const seg_entry
*build_modrm_byte
PARAMS ((void));
104 static void output_insn
PARAMS ((void));
105 static void output_branch
PARAMS ((void));
106 static void output_jump
PARAMS ((void));
107 static void output_interseg_jump
PARAMS ((void));
108 static void output_imm
PARAMS ((fragS
*insn_start_frag
,
109 offsetT insn_start_off
));
110 static void output_disp
PARAMS ((fragS
*insn_start_frag
,
111 offsetT insn_start_off
));
113 static void s_bss
PARAMS ((int));
115 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
116 static void handle_large_common (int small ATTRIBUTE_UNUSED
);
119 static const char *default_arch
= DEFAULT_ARCH
;
121 /* 'md_assemble ()' gathers together information and puts it into a
128 const reg_entry
*regs
;
133 /* TM holds the template for the insn were currently assembling. */
136 /* SUFFIX holds the instruction mnemonic suffix if given.
137 (e.g. 'l' for 'movl') */
140 /* OPERANDS gives the number of given operands. */
141 unsigned int operands
;
143 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
144 of given register, displacement, memory operands and immediate
146 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
148 /* TYPES [i] is the type (see above #defines) which tells us how to
149 use OP[i] for the corresponding operand. */
150 unsigned int types
[MAX_OPERANDS
];
152 /* Displacement expression, immediate expression, or register for each
154 union i386_op op
[MAX_OPERANDS
];
156 /* Flags for operands. */
157 unsigned int flags
[MAX_OPERANDS
];
158 #define Operand_PCrel 1
160 /* Relocation type for operand */
161 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
163 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
164 the base index byte below. */
165 const reg_entry
*base_reg
;
166 const reg_entry
*index_reg
;
167 unsigned int log2_scale_factor
;
169 /* SEG gives the seg_entries of this insn. They are zero unless
170 explicit segment overrides are given. */
171 const seg_entry
*seg
[2];
173 /* PREFIX holds all the given prefix opcodes (usually null).
174 PREFIXES is the number of prefix opcodes. */
175 unsigned int prefixes
;
176 unsigned char prefix
[MAX_PREFIXES
];
178 /* RM and SIB are the modrm byte and the sib byte where the
179 addressing modes of this insn are encoded. */
186 typedef struct _i386_insn i386_insn
;
188 /* List of chars besides those in app.c:symbol_chars that can start an
189 operand. Used to prevent the scrubber eating vital white-space. */
190 const char extra_symbol_chars
[] = "*%-(["
199 #if (defined (TE_I386AIX) \
200 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
201 && !defined (TE_GNU) \
202 && !defined (TE_LINUX) \
203 && !defined (TE_NETWARE) \
204 && !defined (TE_FreeBSD) \
205 && !defined (TE_NetBSD)))
206 /* This array holds the chars that always start a comment. If the
207 pre-processor is disabled, these aren't very useful. The option
208 --divide will remove '/' from this list. */
209 const char *i386_comment_chars
= "#/";
210 #define SVR4_COMMENT_CHARS 1
211 #define PREFIX_SEPARATOR '\\'
214 const char *i386_comment_chars
= "#";
215 #define PREFIX_SEPARATOR '/'
218 /* This array holds the chars that only start a comment at the beginning of
219 a line. If the line seems to have the form '# 123 filename'
220 .line and .file directives will appear in the pre-processed output.
221 Note that input_file.c hand checks for '#' at the beginning of the
222 first line of the input file. This is because the compiler outputs
223 #NO_APP at the beginning of its output.
224 Also note that comments started like this one will always work if
225 '/' isn't otherwise defined. */
226 const char line_comment_chars
[] = "#/";
228 const char line_separator_chars
[] = ";";
230 /* Chars that can be used to separate mant from exp in floating point
232 const char EXP_CHARS
[] = "eE";
234 /* Chars that mean this number is a floating point constant
237 const char FLT_CHARS
[] = "fFdDxX";
239 /* Tables for lexical analysis. */
240 static char mnemonic_chars
[256];
241 static char register_chars
[256];
242 static char operand_chars
[256];
243 static char identifier_chars
[256];
244 static char digit_chars
[256];
246 /* Lexical macros. */
247 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
248 #define is_operand_char(x) (operand_chars[(unsigned char) x])
249 #define is_register_char(x) (register_chars[(unsigned char) x])
250 #define is_space_char(x) ((x) == ' ')
251 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
252 #define is_digit_char(x) (digit_chars[(unsigned char) x])
254 /* All non-digit non-letter characters that may occur in an operand. */
255 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
257 /* md_assemble() always leaves the strings it's passed unaltered. To
258 effect this we maintain a stack of saved characters that we've smashed
259 with '\0's (indicating end of strings for various sub-fields of the
260 assembler instruction). */
261 static char save_stack
[32];
262 static char *save_stack_p
;
263 #define END_STRING_AND_SAVE(s) \
264 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
265 #define RESTORE_END_STRING(s) \
266 do { *(s) = *--save_stack_p; } while (0)
268 /* The instruction we're assembling. */
271 /* Possible templates for current insn. */
272 static const templates
*current_templates
;
274 /* Per instruction expressionS buffers: 2 displacements & 2 immediate max. */
275 static expressionS disp_expressions
[2], im_expressions
[2];
277 /* Current operand we are working on. */
278 static int this_operand
;
280 /* We support four different modes. FLAG_CODE variable is used to distinguish
287 #define NUM_FLAG_CODE ((int) CODE_64BIT + 1)
289 static enum flag_code flag_code
;
290 static unsigned int object_64bit
;
291 static int use_rela_relocations
= 0;
293 /* The names used to print error messages. */
294 static const char *flag_code_names
[] =
301 /* 1 for intel syntax,
303 static int intel_syntax
= 0;
305 /* 1 if register prefix % not required. */
306 static int allow_naked_reg
= 0;
308 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
309 leave, push, and pop instructions so that gcc has the same stack
310 frame as in 32 bit mode. */
311 static char stackop_size
= '\0';
313 /* Non-zero to optimize code alignment. */
314 int optimize_align_code
= 1;
316 /* Non-zero to quieten some warnings. */
317 static int quiet_warnings
= 0;
320 static const char *cpu_arch_name
= NULL
;
321 static const char *cpu_sub_arch_name
= NULL
;
323 /* CPU feature flags. */
324 static unsigned int cpu_arch_flags
= CpuUnknownFlags
| CpuNo64
;
326 /* If set, conditional jumps are not automatically promoted to handle
327 larger than a byte offset. */
328 static unsigned int no_cond_jump_promotion
= 0;
330 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
331 static symbolS
*GOT_symbol
;
333 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
334 unsigned int x86_dwarf2_return_column
;
336 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
337 int x86_cie_data_alignment
;
339 /* Interface to relax_segment.
340 There are 3 major relax states for 386 jump insns because the
341 different types of jumps add different sizes to frags when we're
342 figuring out what sort of jump to choose to reach a given label. */
345 #define UNCOND_JUMP 0
347 #define COND_JUMP86 2
352 #define SMALL16 (SMALL | CODE16)
354 #define BIG16 (BIG | CODE16)
358 #define INLINE __inline__
364 #define ENCODE_RELAX_STATE(type, size) \
365 ((relax_substateT) (((type) << 2) | (size)))
366 #define TYPE_FROM_RELAX_STATE(s) \
368 #define DISP_SIZE_FROM_RELAX_STATE(s) \
369 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
371 /* This table is used by relax_frag to promote short jumps to long
372 ones where necessary. SMALL (short) jumps may be promoted to BIG
373 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
374 don't allow a short jump in a 32 bit code segment to be promoted to
375 a 16 bit offset jump because it's slower (requires data size
376 prefix), and doesn't work, unless the destination is in the bottom
377 64k of the code segment (The top 16 bits of eip are zeroed). */
379 const relax_typeS md_relax_table
[] =
382 1) most positive reach of this state,
383 2) most negative reach of this state,
384 3) how many bytes this mode will have in the variable part of the frag
385 4) which index into the table to try if we can't fit into this one. */
387 /* UNCOND_JUMP states. */
388 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
389 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
390 /* dword jmp adds 4 bytes to frag:
391 0 extra opcode bytes, 4 displacement bytes. */
393 /* word jmp adds 2 byte2 to frag:
394 0 extra opcode bytes, 2 displacement bytes. */
397 /* COND_JUMP states. */
398 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
399 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
400 /* dword conditionals adds 5 bytes to frag:
401 1 extra opcode byte, 4 displacement bytes. */
403 /* word conditionals add 3 bytes to frag:
404 1 extra opcode byte, 2 displacement bytes. */
407 /* COND_JUMP86 states. */
408 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
409 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
410 /* dword conditionals adds 5 bytes to frag:
411 1 extra opcode byte, 4 displacement bytes. */
413 /* word conditionals add 4 bytes to frag:
414 1 displacement byte and a 3 byte long branch insn. */
418 static const arch_entry cpu_arch
[] = {
420 {"i186", Cpu086
|Cpu186
},
421 {"i286", Cpu086
|Cpu186
|Cpu286
},
422 {"i386", Cpu086
|Cpu186
|Cpu286
|Cpu386
},
423 {"i486", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
},
424 {"i586", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
},
425 {"i686", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
},
426 {"pentium", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
},
427 {"pentiumpro",Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
},
428 {"pentiumii", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuMMX
},
429 {"pentiumiii",Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuMMX
|CpuMMX2
|CpuSSE
},
430 {"pentium4", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuP4
|CpuMMX
|CpuMMX2
|CpuSSE
|CpuSSE2
},
431 {"prescott", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuP4
|CpuMMX
|CpuMMX2
|CpuSSE
|CpuSSE2
|CpuPNI
},
432 {"k6", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|CpuK6
|CpuMMX
},
433 {"k6_2", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|CpuK6
|CpuMMX
|Cpu3dnow
},
434 {"athlon", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuK6
|CpuAthlon
|CpuMMX
|CpuMMX2
|Cpu3dnow
|Cpu3dnowA
},
435 {"sledgehammer",Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuK6
|CpuAthlon
|CpuSledgehammer
|CpuMMX
|CpuMMX2
|Cpu3dnow
|Cpu3dnowA
|CpuSSE
|CpuSSE2
},
436 {"opteron", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuK6
|CpuAthlon
|CpuSledgehammer
|CpuMMX
|CpuMMX2
|Cpu3dnow
|Cpu3dnowA
|CpuSSE
|CpuSSE2
},
438 {".sse", CpuMMX
|CpuMMX2
|CpuSSE
},
439 {".sse2", CpuMMX
|CpuMMX2
|CpuSSE
|CpuSSE2
},
440 {".sse3", CpuMMX
|CpuMMX2
|CpuSSE
|CpuSSE2
|CpuSSE3
},
441 {".3dnow", CpuMMX
|Cpu3dnow
},
442 {".3dnowa", CpuMMX
|CpuMMX2
|Cpu3dnow
|Cpu3dnowA
},
443 {".padlock", CpuPadLock
},
444 {".pacifica", CpuSVME
},
449 const pseudo_typeS md_pseudo_table
[] =
451 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
452 {"align", s_align_bytes
, 0},
454 {"align", s_align_ptwo
, 0},
456 {"arch", set_cpu_arch
, 0},
460 {"ffloat", float_cons
, 'f'},
461 {"dfloat", float_cons
, 'd'},
462 {"tfloat", float_cons
, 'x'},
464 {"slong", signed_cons
, 4},
465 {"noopt", s_ignore
, 0},
466 {"optim", s_ignore
, 0},
467 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
468 {"code16", set_code_flag
, CODE_16BIT
},
469 {"code32", set_code_flag
, CODE_32BIT
},
470 {"code64", set_code_flag
, CODE_64BIT
},
471 {"intel_syntax", set_intel_syntax
, 1},
472 {"att_syntax", set_intel_syntax
, 0},
473 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
474 {"largecomm", handle_large_common
, 0},
476 {"file", (void (*) PARAMS ((int))) dwarf2_directive_file
, 0},
477 {"loc", dwarf2_directive_loc
, 0},
478 {"loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0},
481 {"secrel32", pe_directive_secrel
, 0},
486 /* For interface with expression (). */
487 extern char *input_line_pointer
;
489 /* Hash table for instruction mnemonic lookup. */
490 static struct hash_control
*op_hash
;
492 /* Hash table for register lookup. */
493 static struct hash_control
*reg_hash
;
496 i386_align_code (fragP
, count
)
500 /* Various efficient no-op patterns for aligning code labels.
501 Note: Don't try to assemble the instructions in the comments.
502 0L and 0w are not legal. */
503 static const char f32_1
[] =
505 static const char f32_2
[] =
506 {0x89,0xf6}; /* movl %esi,%esi */
507 static const char f32_3
[] =
508 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
509 static const char f32_4
[] =
510 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
511 static const char f32_5
[] =
513 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
514 static const char f32_6
[] =
515 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
516 static const char f32_7
[] =
517 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
518 static const char f32_8
[] =
520 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
521 static const char f32_9
[] =
522 {0x89,0xf6, /* movl %esi,%esi */
523 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
524 static const char f32_10
[] =
525 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
526 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
527 static const char f32_11
[] =
528 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
529 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
530 static const char f32_12
[] =
531 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
532 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
533 static const char f32_13
[] =
534 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
535 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
536 static const char f32_14
[] =
537 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
538 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
539 static const char f32_15
[] =
540 {0xeb,0x0d,0x90,0x90,0x90,0x90,0x90, /* jmp .+15; lotsa nops */
541 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
542 static const char f16_3
[] =
543 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
544 static const char f16_4
[] =
545 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
546 static const char f16_5
[] =
548 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
549 static const char f16_6
[] =
550 {0x89,0xf6, /* mov %si,%si */
551 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
552 static const char f16_7
[] =
553 {0x8d,0x74,0x00, /* lea 0(%si),%si */
554 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
555 static const char f16_8
[] =
556 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
557 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
558 static const char *const f32_patt
[] = {
559 f32_1
, f32_2
, f32_3
, f32_4
, f32_5
, f32_6
, f32_7
, f32_8
,
560 f32_9
, f32_10
, f32_11
, f32_12
, f32_13
, f32_14
, f32_15
562 static const char *const f16_patt
[] = {
563 f32_1
, f32_2
, f16_3
, f16_4
, f16_5
, f16_6
, f16_7
, f16_8
,
564 f32_15
, f32_15
, f32_15
, f32_15
, f32_15
, f32_15
, f32_15
567 if (count
<= 0 || count
> 15)
570 /* The recommended way to pad 64bit code is to use NOPs preceded by
571 maximally four 0x66 prefixes. Balance the size of nops. */
572 if (flag_code
== CODE_64BIT
)
575 int nnops
= (count
+ 3) / 4;
576 int len
= count
/ nnops
;
577 int remains
= count
- nnops
* len
;
580 for (i
= 0; i
< remains
; i
++)
582 memset (fragP
->fr_literal
+ fragP
->fr_fix
+ pos
, 0x66, len
);
583 fragP
->fr_literal
[fragP
->fr_fix
+ pos
+ len
] = 0x90;
586 for (; i
< nnops
; i
++)
588 memset (fragP
->fr_literal
+ fragP
->fr_fix
+ pos
, 0x66, len
- 1);
589 fragP
->fr_literal
[fragP
->fr_fix
+ pos
+ len
- 1] = 0x90;
594 if (flag_code
== CODE_16BIT
)
596 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
597 f16_patt
[count
- 1], count
);
599 /* Adjust jump offset. */
600 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
603 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
604 f32_patt
[count
- 1], count
);
605 fragP
->fr_var
= count
;
608 static INLINE
unsigned int
609 mode_from_disp_size (t
)
612 return (t
& Disp8
) ? 1 : (t
& (Disp16
| Disp32
| Disp32S
)) ? 2 : 0;
616 fits_in_signed_byte (num
)
619 return (num
>= -128) && (num
<= 127);
623 fits_in_unsigned_byte (num
)
626 return (num
& 0xff) == num
;
630 fits_in_unsigned_word (num
)
633 return (num
& 0xffff) == num
;
637 fits_in_signed_word (num
)
640 return (-32768 <= num
) && (num
<= 32767);
643 fits_in_signed_long (num
)
644 offsetT num ATTRIBUTE_UNUSED
;
649 return (!(((offsetT
) -1 << 31) & num
)
650 || (((offsetT
) -1 << 31) & num
) == ((offsetT
) -1 << 31));
652 } /* fits_in_signed_long() */
654 fits_in_unsigned_long (num
)
655 offsetT num ATTRIBUTE_UNUSED
;
660 return (num
& (((offsetT
) 2 << 31) - 1)) == num
;
662 } /* fits_in_unsigned_long() */
665 smallest_imm_type (num
)
668 if (cpu_arch_flags
!= (Cpu086
| Cpu186
| Cpu286
| Cpu386
| Cpu486
| CpuNo64
))
670 /* This code is disabled on the 486 because all the Imm1 forms
671 in the opcode table are slower on the i486. They're the
672 versions with the implicitly specified single-position
673 displacement, which has another syntax if you really want to
676 return Imm1
| Imm8
| Imm8S
| Imm16
| Imm32
| Imm32S
| Imm64
;
678 return (fits_in_signed_byte (num
)
679 ? (Imm8S
| Imm8
| Imm16
| Imm32
| Imm32S
| Imm64
)
680 : fits_in_unsigned_byte (num
)
681 ? (Imm8
| Imm16
| Imm32
| Imm32S
| Imm64
)
682 : (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
683 ? (Imm16
| Imm32
| Imm32S
| Imm64
)
684 : fits_in_signed_long (num
)
685 ? (Imm32
| Imm32S
| Imm64
)
686 : fits_in_unsigned_long (num
)
692 offset_in_range (val
, size
)
700 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
701 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
702 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
704 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
709 /* If BFD64, sign extend val. */
710 if (!use_rela_relocations
)
711 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
712 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
714 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
716 char buf1
[40], buf2
[40];
718 sprint_value (buf1
, val
);
719 sprint_value (buf2
, val
& mask
);
720 as_warn (_("%s shortened to %s"), buf1
, buf2
);
725 /* Returns 0 if attempting to add a prefix where one from the same
726 class already exists, 1 if non rep/repne added, 2 if rep/repne
735 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
736 && flag_code
== CODE_64BIT
)
738 if ((i
.prefix
[REX_PREFIX
] & prefix
& REX_MODE64
)
739 || ((i
.prefix
[REX_PREFIX
] & (REX_EXTX
| REX_EXTY
| REX_EXTZ
))
740 && (prefix
& (REX_EXTX
| REX_EXTY
| REX_EXTZ
))))
751 case CS_PREFIX_OPCODE
:
752 case DS_PREFIX_OPCODE
:
753 case ES_PREFIX_OPCODE
:
754 case FS_PREFIX_OPCODE
:
755 case GS_PREFIX_OPCODE
:
756 case SS_PREFIX_OPCODE
:
760 case REPNE_PREFIX_OPCODE
:
761 case REPE_PREFIX_OPCODE
:
764 case LOCK_PREFIX_OPCODE
:
772 case ADDR_PREFIX_OPCODE
:
776 case DATA_PREFIX_OPCODE
:
780 if (i
.prefix
[q
] != 0)
788 i
.prefix
[q
] |= prefix
;
791 as_bad (_("same type of prefix used twice"));
797 set_code_flag (value
)
801 cpu_arch_flags
&= ~(Cpu64
| CpuNo64
);
802 cpu_arch_flags
|= (flag_code
== CODE_64BIT
? Cpu64
: CpuNo64
);
803 if (value
== CODE_64BIT
&& !(cpu_arch_flags
& CpuSledgehammer
))
805 as_bad (_("64bit mode not supported on this CPU."));
807 if (value
== CODE_32BIT
&& !(cpu_arch_flags
& Cpu386
))
809 as_bad (_("32bit mode not supported on this CPU."));
815 set_16bit_gcc_code_flag (new_code_flag
)
818 flag_code
= new_code_flag
;
819 cpu_arch_flags
&= ~(Cpu64
| CpuNo64
);
820 cpu_arch_flags
|= (flag_code
== CODE_64BIT
? Cpu64
: CpuNo64
);
821 stackop_size
= LONG_MNEM_SUFFIX
;
825 set_intel_syntax (syntax_flag
)
828 /* Find out if register prefixing is specified. */
829 int ask_naked_reg
= 0;
832 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
834 char *string
= input_line_pointer
;
835 int e
= get_symbol_end ();
837 if (strcmp (string
, "prefix") == 0)
839 else if (strcmp (string
, "noprefix") == 0)
842 as_bad (_("bad argument to syntax directive."));
843 *input_line_pointer
= e
;
845 demand_empty_rest_of_line ();
847 intel_syntax
= syntax_flag
;
849 if (ask_naked_reg
== 0)
850 allow_naked_reg
= (intel_syntax
851 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
853 allow_naked_reg
= (ask_naked_reg
< 0);
855 identifier_chars
['%'] = intel_syntax
&& allow_naked_reg
? '%' : 0;
856 identifier_chars
['$'] = intel_syntax
? '$' : 0;
861 int dummy ATTRIBUTE_UNUSED
;
865 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
867 char *string
= input_line_pointer
;
868 int e
= get_symbol_end ();
871 for (i
= 0; cpu_arch
[i
].name
; i
++)
873 if (strcmp (string
, cpu_arch
[i
].name
) == 0)
877 cpu_arch_name
= cpu_arch
[i
].name
;
878 cpu_sub_arch_name
= NULL
;
879 cpu_arch_flags
= (cpu_arch
[i
].flags
880 | (flag_code
== CODE_64BIT
? Cpu64
: CpuNo64
));
883 if ((cpu_arch_flags
| cpu_arch
[i
].flags
) != cpu_arch_flags
)
885 cpu_sub_arch_name
= cpu_arch
[i
].name
;
886 cpu_arch_flags
|= cpu_arch
[i
].flags
;
888 *input_line_pointer
= e
;
889 demand_empty_rest_of_line ();
893 if (!cpu_arch
[i
].name
)
894 as_bad (_("no such architecture: `%s'"), string
);
896 *input_line_pointer
= e
;
899 as_bad (_("missing cpu architecture"));
901 no_cond_jump_promotion
= 0;
902 if (*input_line_pointer
== ','
903 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
905 char *string
= ++input_line_pointer
;
906 int e
= get_symbol_end ();
908 if (strcmp (string
, "nojumps") == 0)
909 no_cond_jump_promotion
= 1;
910 else if (strcmp (string
, "jumps") == 0)
913 as_bad (_("no such architecture modifier: `%s'"), string
);
915 *input_line_pointer
= e
;
918 demand_empty_rest_of_line ();
924 if (!strcmp (default_arch
, "x86_64"))
925 return bfd_mach_x86_64
;
926 else if (!strcmp (default_arch
, "i386"))
927 return bfd_mach_i386_i386
;
929 as_fatal (_("Unknown architecture"));
935 const char *hash_err
;
937 /* Initialize op_hash hash table. */
938 op_hash
= hash_new ();
941 const template *optab
;
942 templates
*core_optab
;
944 /* Setup for loop. */
946 core_optab
= (templates
*) xmalloc (sizeof (templates
));
947 core_optab
->start
= optab
;
952 if (optab
->name
== NULL
953 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
955 /* different name --> ship out current template list;
956 add to hash table; & begin anew. */
957 core_optab
->end
= optab
;
958 hash_err
= hash_insert (op_hash
,
963 as_fatal (_("Internal Error: Can't hash %s: %s"),
967 if (optab
->name
== NULL
)
969 core_optab
= (templates
*) xmalloc (sizeof (templates
));
970 core_optab
->start
= optab
;
975 /* Initialize reg_hash hash table. */
976 reg_hash
= hash_new ();
978 const reg_entry
*regtab
;
980 for (regtab
= i386_regtab
;
981 regtab
< i386_regtab
+ sizeof (i386_regtab
) / sizeof (i386_regtab
[0]);
984 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (PTR
) regtab
);
986 as_fatal (_("Internal Error: Can't hash %s: %s"),
992 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
997 for (c
= 0; c
< 256; c
++)
1002 mnemonic_chars
[c
] = c
;
1003 register_chars
[c
] = c
;
1004 operand_chars
[c
] = c
;
1006 else if (ISLOWER (c
))
1008 mnemonic_chars
[c
] = c
;
1009 register_chars
[c
] = c
;
1010 operand_chars
[c
] = c
;
1012 else if (ISUPPER (c
))
1014 mnemonic_chars
[c
] = TOLOWER (c
);
1015 register_chars
[c
] = mnemonic_chars
[c
];
1016 operand_chars
[c
] = c
;
1019 if (ISALPHA (c
) || ISDIGIT (c
))
1020 identifier_chars
[c
] = c
;
1023 identifier_chars
[c
] = c
;
1024 operand_chars
[c
] = c
;
1029 identifier_chars
['@'] = '@';
1032 identifier_chars
['?'] = '?';
1033 operand_chars
['?'] = '?';
1035 digit_chars
['-'] = '-';
1036 mnemonic_chars
['-'] = '-';
1037 identifier_chars
['_'] = '_';
1038 identifier_chars
['.'] = '.';
1040 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
1041 operand_chars
[(unsigned char) *p
] = *p
;
1044 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1047 record_alignment (text_section
, 2);
1048 record_alignment (data_section
, 2);
1049 record_alignment (bss_section
, 2);
1053 if (flag_code
== CODE_64BIT
)
1055 x86_dwarf2_return_column
= 16;
1056 x86_cie_data_alignment
= -8;
1060 x86_dwarf2_return_column
= 8;
1061 x86_cie_data_alignment
= -4;
1066 i386_print_statistics (file
)
1069 hash_print_statistics (file
, "i386 opcode", op_hash
);
1070 hash_print_statistics (file
, "i386 register", reg_hash
);
1075 /* Debugging routines for md_assemble. */
1076 static void pi
PARAMS ((char *, i386_insn
*));
1077 static void pte
PARAMS ((template *));
1078 static void pt
PARAMS ((unsigned int));
1079 static void pe
PARAMS ((expressionS
*));
1080 static void ps
PARAMS ((symbolS
*));
1089 fprintf (stdout
, "%s: template ", line
);
1091 fprintf (stdout
, " address: base %s index %s scale %x\n",
1092 x
->base_reg
? x
->base_reg
->reg_name
: "none",
1093 x
->index_reg
? x
->index_reg
->reg_name
: "none",
1094 x
->log2_scale_factor
);
1095 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
1096 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
1097 fprintf (stdout
, " sib: base %x index %x scale %x\n",
1098 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
1099 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
1100 (x
->rex
& REX_MODE64
) != 0,
1101 (x
->rex
& REX_EXTX
) != 0,
1102 (x
->rex
& REX_EXTY
) != 0,
1103 (x
->rex
& REX_EXTZ
) != 0);
1104 for (i
= 0; i
< x
->operands
; i
++)
1106 fprintf (stdout
, " #%d: ", i
+ 1);
1108 fprintf (stdout
, "\n");
1110 & (Reg
| SReg2
| SReg3
| Control
| Debug
| Test
| RegMMX
| RegXMM
))
1111 fprintf (stdout
, "%s\n", x
->op
[i
].regs
->reg_name
);
1112 if (x
->types
[i
] & Imm
)
1114 if (x
->types
[i
] & Disp
)
1115 pe (x
->op
[i
].disps
);
1124 fprintf (stdout
, " %d operands ", t
->operands
);
1125 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
1126 if (t
->extension_opcode
!= None
)
1127 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
1128 if (t
->opcode_modifier
& D
)
1129 fprintf (stdout
, "D");
1130 if (t
->opcode_modifier
& W
)
1131 fprintf (stdout
, "W");
1132 fprintf (stdout
, "\n");
1133 for (i
= 0; i
< t
->operands
; i
++)
1135 fprintf (stdout
, " #%d type ", i
+ 1);
1136 pt (t
->operand_types
[i
]);
1137 fprintf (stdout
, "\n");
1145 fprintf (stdout
, " operation %d\n", e
->X_op
);
1146 fprintf (stdout
, " add_number %ld (%lx)\n",
1147 (long) e
->X_add_number
, (long) e
->X_add_number
);
1148 if (e
->X_add_symbol
)
1150 fprintf (stdout
, " add_symbol ");
1151 ps (e
->X_add_symbol
);
1152 fprintf (stdout
, "\n");
1156 fprintf (stdout
, " op_symbol ");
1157 ps (e
->X_op_symbol
);
1158 fprintf (stdout
, "\n");
1166 fprintf (stdout
, "%s type %s%s",
1168 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
1169 segment_name (S_GET_SEGMENT (s
)));
1172 static struct type_name
1177 const type_names
[] =
1190 { BaseIndex
, "BaseIndex" },
1194 { Disp32S
, "d32s" },
1196 { InOutPortReg
, "InOutPortReg" },
1197 { ShiftCount
, "ShiftCount" },
1198 { Control
, "control reg" },
1199 { Test
, "test reg" },
1200 { Debug
, "debug reg" },
1201 { FloatReg
, "FReg" },
1202 { FloatAcc
, "FAcc" },
1206 { JumpAbsolute
, "Jump Absolute" },
1217 const struct type_name
*ty
;
1219 for (ty
= type_names
; ty
->mask
; ty
++)
1221 fprintf (stdout
, "%s, ", ty
->tname
);
1225 #endif /* DEBUG386 */
1227 static bfd_reloc_code_real_type
1228 reloc (unsigned int size
,
1231 bfd_reloc_code_real_type other
)
1233 if (other
!= NO_RELOC
)
1235 reloc_howto_type
*reloc
;
1240 case BFD_RELOC_X86_64_GOT32
:
1241 return BFD_RELOC_X86_64_GOT64
;
1243 case BFD_RELOC_X86_64_PLTOFF64
:
1244 return BFD_RELOC_X86_64_PLTOFF64
;
1246 case BFD_RELOC_X86_64_GOTPC32
:
1247 other
= BFD_RELOC_X86_64_GOTPC64
;
1249 case BFD_RELOC_X86_64_GOTPCREL
:
1250 other
= BFD_RELOC_X86_64_GOTPCREL64
;
1252 case BFD_RELOC_X86_64_TPOFF32
:
1253 other
= BFD_RELOC_X86_64_TPOFF64
;
1255 case BFD_RELOC_X86_64_DTPOFF32
:
1256 other
= BFD_RELOC_X86_64_DTPOFF64
;
1262 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
1263 if (size
== 4 && flag_code
!= CODE_64BIT
)
1266 reloc
= bfd_reloc_type_lookup (stdoutput
, other
);
1268 as_bad (_("unknown relocation (%u)"), other
);
1269 else if (size
!= bfd_get_reloc_size (reloc
))
1270 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
1271 bfd_get_reloc_size (reloc
),
1273 else if (pcrel
&& !reloc
->pc_relative
)
1274 as_bad (_("non-pc-relative relocation for pc-relative field"));
1275 else if ((reloc
->complain_on_overflow
== complain_overflow_signed
1277 || (reloc
->complain_on_overflow
== complain_overflow_unsigned
1279 as_bad (_("relocated field and relocation type differ in signedness"));
1288 as_bad (_("there are no unsigned pc-relative relocations"));
1291 case 1: return BFD_RELOC_8_PCREL
;
1292 case 2: return BFD_RELOC_16_PCREL
;
1293 case 4: return BFD_RELOC_32_PCREL
;
1294 case 8: return BFD_RELOC_64_PCREL
;
1296 as_bad (_("cannot do %u byte pc-relative relocation"), size
);
1303 case 4: return BFD_RELOC_X86_64_32S
;
1308 case 1: return BFD_RELOC_8
;
1309 case 2: return BFD_RELOC_16
;
1310 case 4: return BFD_RELOC_32
;
1311 case 8: return BFD_RELOC_64
;
1313 as_bad (_("cannot do %s %u byte relocation"),
1314 sign
> 0 ? "signed" : "unsigned", size
);
1318 return BFD_RELOC_NONE
;
1321 /* Here we decide which fixups can be adjusted to make them relative to
1322 the beginning of the section instead of the symbol. Basically we need
1323 to make sure that the dynamic relocations are done correctly, so in
1324 some cases we force the original symbol to be used. */
1327 tc_i386_fix_adjustable (fixP
)
1328 fixS
*fixP ATTRIBUTE_UNUSED
;
1330 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1334 /* Don't adjust pc-relative references to merge sections in 64-bit
1336 if (use_rela_relocations
1337 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
1341 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
1342 and changed later by validate_fix. */
1343 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
1344 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
1347 /* adjust_reloc_syms doesn't know about the GOT. */
1348 if (fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
1349 || fixP
->fx_r_type
== BFD_RELOC_386_PLT32
1350 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
1351 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
1352 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
1353 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
1354 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
1355 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
1356 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
1357 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
1358 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
1359 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTDESC
1360 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_DESC_CALL
1361 || fixP
->fx_r_type
== BFD_RELOC_X86_64_PLT32
1362 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
1363 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
1364 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
1365 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
1366 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
1367 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
1368 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
1369 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
1370 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
1371 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
1372 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPC32_TLSDESC
1373 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSDESC_CALL
1374 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
1375 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
1381 static int intel_float_operand
PARAMS ((const char *mnemonic
));
1384 intel_float_operand (mnemonic
)
1385 const char *mnemonic
;
1387 /* Note that the value returned is meaningful only for opcodes with (memory)
1388 operands, hence the code here is free to improperly handle opcodes that
1389 have no operands (for better performance and smaller code). */
1391 if (mnemonic
[0] != 'f')
1392 return 0; /* non-math */
1394 switch (mnemonic
[1])
1396 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
1397 the fs segment override prefix not currently handled because no
1398 call path can make opcodes without operands get here */
1400 return 2 /* integer op */;
1402 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
1403 return 3; /* fldcw/fldenv */
1406 if (mnemonic
[2] != 'o' /* fnop */)
1407 return 3; /* non-waiting control op */
1410 if (mnemonic
[2] == 's')
1411 return 3; /* frstor/frstpm */
1414 if (mnemonic
[2] == 'a')
1415 return 3; /* fsave */
1416 if (mnemonic
[2] == 't')
1418 switch (mnemonic
[3])
1420 case 'c': /* fstcw */
1421 case 'd': /* fstdw */
1422 case 'e': /* fstenv */
1423 case 's': /* fsts[gw] */
1429 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
1430 return 0; /* fxsave/fxrstor are not really math ops */
1437 /* This is the guts of the machine-dependent assembler. LINE points to a
1438 machine dependent instruction. This function is supposed to emit
1439 the frags/bytes it assembles to. */
1446 char mnemonic
[MAX_MNEM_SIZE
];
1448 /* Initialize globals. */
1449 memset (&i
, '\0', sizeof (i
));
1450 for (j
= 0; j
< MAX_OPERANDS
; j
++)
1451 i
.reloc
[j
] = NO_RELOC
;
1452 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
1453 memset (im_expressions
, '\0', sizeof (im_expressions
));
1454 save_stack_p
= save_stack
;
1456 /* First parse an instruction mnemonic & call i386_operand for the operands.
1457 We assume that the scrubber has arranged it so that line[0] is the valid
1458 start of a (possibly prefixed) mnemonic. */
1460 line
= parse_insn (line
, mnemonic
);
1464 line
= parse_operands (line
, mnemonic
);
1468 /* Now we've parsed the mnemonic into a set of templates, and have the
1469 operands at hand. */
1471 /* All intel opcodes have reversed operands except for "bound" and
1472 "enter". We also don't reverse intersegment "jmp" and "call"
1473 instructions with 2 immediate operands so that the immediate segment
1474 precedes the offset, as it does when in AT&T mode. "enter" and the
1475 intersegment "jmp" and "call" instructions are the only ones that
1476 have two immediate operands. */
1477 if (intel_syntax
&& i
.operands
> 1
1478 && (strcmp (mnemonic
, "bound") != 0)
1479 && (strcmp (mnemonic
, "invlpga") != 0)
1480 && !((i
.types
[0] & Imm
) && (i
.types
[1] & Imm
)))
1486 /* Don't optimize displacement for movabs since it only takes 64bit
1489 && (flag_code
!= CODE_64BIT
1490 || strcmp (mnemonic
, "movabs") != 0))
1493 /* Next, we find a template that matches the given insn,
1494 making sure the overlap of the given operands types is consistent
1495 with the template operand types. */
1497 if (!match_template ())
1502 /* Undo SYSV386_COMPAT brokenness when in Intel mode. See i386.h */
1504 && (i
.tm
.base_opcode
& 0xfffffde0) == 0xdce0)
1505 i
.tm
.base_opcode
^= FloatR
;
1507 /* Zap movzx and movsx suffix. The suffix may have been set from
1508 "word ptr" or "byte ptr" on the source operand, but we'll use
1509 the suffix later to choose the destination register. */
1510 if ((i
.tm
.base_opcode
& ~9) == 0x0fb6)
1512 if (i
.reg_operands
< 2
1514 && (~i
.tm
.opcode_modifier
1521 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
1527 if (i
.tm
.opcode_modifier
& FWait
)
1528 if (!add_prefix (FWAIT_OPCODE
))
1531 /* Check string instruction segment overrides. */
1532 if ((i
.tm
.opcode_modifier
& IsString
) != 0 && i
.mem_operands
!= 0)
1534 if (!check_string ())
1538 if (!process_suffix ())
1541 /* Make still unresolved immediate matches conform to size of immediate
1542 given in i.suffix. */
1543 if (!finalize_imm ())
1546 if (i
.types
[0] & Imm1
)
1547 i
.imm_operands
= 0; /* kludge for shift insns. */
1548 if (i
.types
[0] & ImplicitRegister
)
1550 if (i
.types
[1] & ImplicitRegister
)
1552 if (i
.types
[2] & ImplicitRegister
)
1555 if (i
.tm
.opcode_modifier
& ImmExt
)
1559 if ((i
.tm
.cpu_flags
& CpuPNI
) && i
.operands
> 0)
1561 /* These Intel Prescott New Instructions have the fixed
1562 operands with an opcode suffix which is coded in the same
1563 place as an 8-bit immediate field would be. Here we check
1564 those operands and remove them afterwards. */
1567 for (x
= 0; x
< i
.operands
; x
++)
1568 if (i
.op
[x
].regs
->reg_num
!= x
)
1569 as_bad (_("can't use register '%%%s' as operand %d in '%s'."),
1570 i
.op
[x
].regs
->reg_name
, x
+ 1, i
.tm
.name
);
1574 /* These AMD 3DNow! and Intel Katmai New Instructions have an
1575 opcode suffix which is coded in the same place as an 8-bit
1576 immediate field would be. Here we fake an 8-bit immediate
1577 operand from the opcode suffix stored in tm.extension_opcode. */
1579 assert (i
.imm_operands
== 0 && i
.operands
<= 2 && 2 < MAX_OPERANDS
);
1581 exp
= &im_expressions
[i
.imm_operands
++];
1582 i
.op
[i
.operands
].imms
= exp
;
1583 i
.types
[i
.operands
++] = Imm8
;
1584 exp
->X_op
= O_constant
;
1585 exp
->X_add_number
= i
.tm
.extension_opcode
;
1586 i
.tm
.extension_opcode
= None
;
1589 /* For insns with operands there are more diddles to do to the opcode. */
1592 if (!process_operands ())
1595 else if (!quiet_warnings
&& (i
.tm
.opcode_modifier
& Ugh
) != 0)
1597 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
1598 as_warn (_("translating to `%sp'"), i
.tm
.name
);
1601 /* Handle conversion of 'int $3' --> special int3 insn. */
1602 if (i
.tm
.base_opcode
== INT_OPCODE
&& i
.op
[0].imms
->X_add_number
== 3)
1604 i
.tm
.base_opcode
= INT3_OPCODE
;
1608 if ((i
.tm
.opcode_modifier
& (Jump
| JumpByte
| JumpDword
))
1609 && i
.op
[0].disps
->X_op
== O_constant
)
1611 /* Convert "jmp constant" (and "call constant") to a jump (call) to
1612 the absolute address given by the constant. Since ix86 jumps and
1613 calls are pc relative, we need to generate a reloc. */
1614 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
1615 i
.op
[0].disps
->X_op
= O_symbol
;
1618 if ((i
.tm
.opcode_modifier
& Rex64
) != 0)
1619 i
.rex
|= REX_MODE64
;
1621 /* For 8 bit registers we need an empty rex prefix. Also if the
1622 instruction already has a prefix, we need to convert old
1623 registers to new ones. */
1625 if (((i
.types
[0] & Reg8
) != 0
1626 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
1627 || ((i
.types
[1] & Reg8
) != 0
1628 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
1629 || (((i
.types
[0] & Reg8
) != 0 || (i
.types
[1] & Reg8
) != 0)
1634 i
.rex
|= REX_OPCODE
;
1635 for (x
= 0; x
< 2; x
++)
1637 /* Look for 8 bit operand that uses old registers. */
1638 if ((i
.types
[x
] & Reg8
) != 0
1639 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
1641 /* In case it is "hi" register, give up. */
1642 if (i
.op
[x
].regs
->reg_num
> 3)
1643 as_bad (_("can't encode register '%%%s' in an instruction requiring REX prefix."),
1644 i
.op
[x
].regs
->reg_name
);
1646 /* Otherwise it is equivalent to the extended register.
1647 Since the encoding doesn't change this is merely
1648 cosmetic cleanup for debug output. */
1650 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
1656 add_prefix (REX_OPCODE
| i
.rex
);
1658 /* We are ready to output the insn. */
1663 parse_insn (line
, mnemonic
)
1668 char *token_start
= l
;
1673 /* Non-zero if we found a prefix only acceptable with string insns. */
1674 const char *expecting_string_instruction
= NULL
;
1679 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
1682 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
1684 as_bad (_("no such instruction: `%s'"), token_start
);
1689 if (!is_space_char (*l
)
1690 && *l
!= END_OF_INSN
1692 || (*l
!= PREFIX_SEPARATOR
1695 as_bad (_("invalid character %s in mnemonic"),
1696 output_invalid (*l
));
1699 if (token_start
== l
)
1701 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
1702 as_bad (_("expecting prefix; got nothing"));
1704 as_bad (_("expecting mnemonic; got nothing"));
1708 /* Look up instruction (or prefix) via hash table. */
1709 current_templates
= hash_find (op_hash
, mnemonic
);
1711 if (*l
!= END_OF_INSN
1712 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
1713 && current_templates
1714 && (current_templates
->start
->opcode_modifier
& IsPrefix
))
1716 if (current_templates
->start
->cpu_flags
1717 & (flag_code
!= CODE_64BIT
? Cpu64
: CpuNo64
))
1719 as_bad ((flag_code
!= CODE_64BIT
1720 ? _("`%s' is only supported in 64-bit mode")
1721 : _("`%s' is not supported in 64-bit mode")),
1722 current_templates
->start
->name
);
1725 /* If we are in 16-bit mode, do not allow addr16 or data16.
1726 Similarly, in 32-bit mode, do not allow addr32 or data32. */
1727 if ((current_templates
->start
->opcode_modifier
& (Size16
| Size32
))
1728 && flag_code
!= CODE_64BIT
1729 && (((current_templates
->start
->opcode_modifier
& Size32
) != 0)
1730 ^ (flag_code
== CODE_16BIT
)))
1732 as_bad (_("redundant %s prefix"),
1733 current_templates
->start
->name
);
1736 /* Add prefix, checking for repeated prefixes. */
1737 switch (add_prefix (current_templates
->start
->base_opcode
))
1742 expecting_string_instruction
= current_templates
->start
->name
;
1745 /* Skip past PREFIX_SEPARATOR and reset token_start. */
1752 if (!current_templates
)
1754 /* See if we can get a match by trimming off a suffix. */
1757 case WORD_MNEM_SUFFIX
:
1758 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
1759 i
.suffix
= SHORT_MNEM_SUFFIX
;
1761 case BYTE_MNEM_SUFFIX
:
1762 case QWORD_MNEM_SUFFIX
:
1763 i
.suffix
= mnem_p
[-1];
1765 current_templates
= hash_find (op_hash
, mnemonic
);
1767 case SHORT_MNEM_SUFFIX
:
1768 case LONG_MNEM_SUFFIX
:
1771 i
.suffix
= mnem_p
[-1];
1773 current_templates
= hash_find (op_hash
, mnemonic
);
1781 if (intel_float_operand (mnemonic
) == 1)
1782 i
.suffix
= SHORT_MNEM_SUFFIX
;
1784 i
.suffix
= LONG_MNEM_SUFFIX
;
1786 current_templates
= hash_find (op_hash
, mnemonic
);
1790 if (!current_templates
)
1792 as_bad (_("no such instruction: `%s'"), token_start
);
1797 if (current_templates
->start
->opcode_modifier
& (Jump
| JumpByte
))
1799 /* Check for a branch hint. We allow ",pt" and ",pn" for
1800 predict taken and predict not taken respectively.
1801 I'm not sure that branch hints actually do anything on loop
1802 and jcxz insns (JumpByte) for current Pentium4 chips. They
1803 may work in the future and it doesn't hurt to accept them
1805 if (l
[0] == ',' && l
[1] == 'p')
1809 if (!add_prefix (DS_PREFIX_OPCODE
))
1813 else if (l
[2] == 'n')
1815 if (!add_prefix (CS_PREFIX_OPCODE
))
1821 /* Any other comma loses. */
1824 as_bad (_("invalid character %s in mnemonic"),
1825 output_invalid (*l
));
1829 /* Check if instruction is supported on specified architecture. */
1831 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
1833 if (!((t
->cpu_flags
& ~(Cpu64
| CpuNo64
))
1834 & ~(cpu_arch_flags
& ~(Cpu64
| CpuNo64
))))
1836 if (!(t
->cpu_flags
& (flag_code
== CODE_64BIT
? CpuNo64
: Cpu64
)))
1839 if (!(supported
& 2))
1841 as_bad (flag_code
== CODE_64BIT
1842 ? _("`%s' is not supported in 64-bit mode")
1843 : _("`%s' is only supported in 64-bit mode"),
1844 current_templates
->start
->name
);
1847 if (!(supported
& 1))
1849 as_warn (_("`%s' is not supported on `%s%s'"),
1850 current_templates
->start
->name
,
1852 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
1854 else if ((Cpu386
& ~cpu_arch_flags
) && (flag_code
!= CODE_16BIT
))
1856 as_warn (_("use .code16 to ensure correct addressing mode"));
1859 /* Check for rep/repne without a string instruction. */
1860 if (expecting_string_instruction
)
1862 static templates override
;
1864 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
1865 if (t
->opcode_modifier
& IsString
)
1867 if (t
>= current_templates
->end
)
1869 as_bad (_("expecting string instruction after `%s'"),
1870 expecting_string_instruction
);
1873 for (override
.start
= t
; t
< current_templates
->end
; ++t
)
1874 if (!(t
->opcode_modifier
& IsString
))
1877 current_templates
= &override
;
1884 parse_operands (l
, mnemonic
)
1886 const char *mnemonic
;
1890 /* 1 if operand is pending after ','. */
1891 unsigned int expecting_operand
= 0;
1893 /* Non-zero if operand parens not balanced. */
1894 unsigned int paren_not_balanced
;
1896 while (*l
!= END_OF_INSN
)
1898 /* Skip optional white space before operand. */
1899 if (is_space_char (*l
))
1901 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
)
1903 as_bad (_("invalid character %s before operand %d"),
1904 output_invalid (*l
),
1908 token_start
= l
; /* after white space */
1909 paren_not_balanced
= 0;
1910 while (paren_not_balanced
|| *l
!= ',')
1912 if (*l
== END_OF_INSN
)
1914 if (paren_not_balanced
)
1917 as_bad (_("unbalanced parenthesis in operand %d."),
1920 as_bad (_("unbalanced brackets in operand %d."),
1925 break; /* we are done */
1927 else if (!is_operand_char (*l
) && !is_space_char (*l
))
1929 as_bad (_("invalid character %s in operand %d"),
1930 output_invalid (*l
),
1937 ++paren_not_balanced
;
1939 --paren_not_balanced
;
1944 ++paren_not_balanced
;
1946 --paren_not_balanced
;
1950 if (l
!= token_start
)
1951 { /* Yes, we've read in another operand. */
1952 unsigned int operand_ok
;
1953 this_operand
= i
.operands
++;
1954 if (i
.operands
> MAX_OPERANDS
)
1956 as_bad (_("spurious operands; (%d operands/instruction max)"),
1960 /* Now parse operand adding info to 'i' as we go along. */
1961 END_STRING_AND_SAVE (l
);
1965 i386_intel_operand (token_start
,
1966 intel_float_operand (mnemonic
));
1968 operand_ok
= i386_operand (token_start
);
1970 RESTORE_END_STRING (l
);
1976 if (expecting_operand
)
1978 expecting_operand_after_comma
:
1979 as_bad (_("expecting operand after ','; got nothing"));
1984 as_bad (_("expecting operand before ','; got nothing"));
1989 /* Now *l must be either ',' or END_OF_INSN. */
1992 if (*++l
== END_OF_INSN
)
1994 /* Just skip it, if it's \n complain. */
1995 goto expecting_operand_after_comma
;
1997 expecting_operand
= 1;
2006 union i386_op temp_op
;
2007 unsigned int temp_type
;
2008 enum bfd_reloc_code_real temp_reloc
;
2012 if (i
.operands
== 2)
2017 else if (i
.operands
== 3)
2022 temp_type
= i
.types
[xchg2
];
2023 i
.types
[xchg2
] = i
.types
[xchg1
];
2024 i
.types
[xchg1
] = temp_type
;
2025 temp_op
= i
.op
[xchg2
];
2026 i
.op
[xchg2
] = i
.op
[xchg1
];
2027 i
.op
[xchg1
] = temp_op
;
2028 temp_reloc
= i
.reloc
[xchg2
];
2029 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
2030 i
.reloc
[xchg1
] = temp_reloc
;
2032 if (i
.mem_operands
== 2)
2034 const seg_entry
*temp_seg
;
2035 temp_seg
= i
.seg
[0];
2036 i
.seg
[0] = i
.seg
[1];
2037 i
.seg
[1] = temp_seg
;
2041 /* Try to ensure constant immediates are represented in the smallest
2046 char guess_suffix
= 0;
2050 guess_suffix
= i
.suffix
;
2051 else if (i
.reg_operands
)
2053 /* Figure out a suffix from the last register operand specified.
2054 We can't do this properly yet, ie. excluding InOutPortReg,
2055 but the following works for instructions with immediates.
2056 In any case, we can't set i.suffix yet. */
2057 for (op
= i
.operands
; --op
>= 0;)
2058 if (i
.types
[op
] & Reg
)
2060 if (i
.types
[op
] & Reg8
)
2061 guess_suffix
= BYTE_MNEM_SUFFIX
;
2062 else if (i
.types
[op
] & Reg16
)
2063 guess_suffix
= WORD_MNEM_SUFFIX
;
2064 else if (i
.types
[op
] & Reg32
)
2065 guess_suffix
= LONG_MNEM_SUFFIX
;
2066 else if (i
.types
[op
] & Reg64
)
2067 guess_suffix
= QWORD_MNEM_SUFFIX
;
2071 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
2072 guess_suffix
= WORD_MNEM_SUFFIX
;
2074 for (op
= i
.operands
; --op
>= 0;)
2075 if (i
.types
[op
] & Imm
)
2077 switch (i
.op
[op
].imms
->X_op
)
2080 /* If a suffix is given, this operand may be shortened. */
2081 switch (guess_suffix
)
2083 case LONG_MNEM_SUFFIX
:
2084 i
.types
[op
] |= Imm32
| Imm64
;
2086 case WORD_MNEM_SUFFIX
:
2087 i
.types
[op
] |= Imm16
| Imm32S
| Imm32
| Imm64
;
2089 case BYTE_MNEM_SUFFIX
:
2090 i
.types
[op
] |= Imm16
| Imm8
| Imm8S
| Imm32S
| Imm32
| Imm64
;
2094 /* If this operand is at most 16 bits, convert it
2095 to a signed 16 bit number before trying to see
2096 whether it will fit in an even smaller size.
2097 This allows a 16-bit operand such as $0xffe0 to
2098 be recognised as within Imm8S range. */
2099 if ((i
.types
[op
] & Imm16
)
2100 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
2102 i
.op
[op
].imms
->X_add_number
=
2103 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
2105 if ((i
.types
[op
] & Imm32
)
2106 && ((i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1))
2109 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
2110 ^ ((offsetT
) 1 << 31))
2111 - ((offsetT
) 1 << 31));
2113 i
.types
[op
] |= smallest_imm_type (i
.op
[op
].imms
->X_add_number
);
2115 /* We must avoid matching of Imm32 templates when 64bit
2116 only immediate is available. */
2117 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
2118 i
.types
[op
] &= ~Imm32
;
2125 /* Symbols and expressions. */
2127 /* Convert symbolic operand to proper sizes for matching, but don't
2128 prevent matching a set of insns that only supports sizes other
2129 than those matching the insn suffix. */
2131 unsigned int mask
, allowed
= 0;
2134 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
2135 allowed
|= t
->operand_types
[op
];
2136 switch (guess_suffix
)
2138 case QWORD_MNEM_SUFFIX
:
2139 mask
= Imm64
| Imm32S
;
2141 case LONG_MNEM_SUFFIX
:
2144 case WORD_MNEM_SUFFIX
:
2147 case BYTE_MNEM_SUFFIX
:
2155 i
.types
[op
] &= mask
;
2162 /* Try to use the smallest displacement type too. */
2168 for (op
= i
.operands
; --op
>= 0;)
2169 if (i
.types
[op
] & Disp
)
2171 if (i
.op
[op
].disps
->X_op
== O_constant
)
2173 offsetT disp
= i
.op
[op
].disps
->X_add_number
;
2175 if ((i
.types
[op
] & Disp16
)
2176 && (disp
& ~(offsetT
) 0xffff) == 0)
2178 /* If this operand is at most 16 bits, convert
2179 to a signed 16 bit number and don't use 64bit
2181 disp
= (((disp
& 0xffff) ^ 0x8000) - 0x8000);
2182 i
.types
[op
] &= ~Disp64
;
2184 if ((i
.types
[op
] & Disp32
)
2185 && (disp
& ~(((offsetT
) 2 << 31) - 1)) == 0)
2187 /* If this operand is at most 32 bits, convert
2188 to a signed 32 bit number and don't use 64bit
2190 disp
&= (((offsetT
) 2 << 31) - 1);
2191 disp
= (disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
2192 i
.types
[op
] &= ~Disp64
;
2194 if (!disp
&& (i
.types
[op
] & BaseIndex
))
2196 i
.types
[op
] &= ~Disp
;
2200 else if (flag_code
== CODE_64BIT
)
2202 if (fits_in_signed_long (disp
))
2204 i
.types
[op
] &= ~Disp64
;
2205 i
.types
[op
] |= Disp32S
;
2207 if (fits_in_unsigned_long (disp
))
2208 i
.types
[op
] |= Disp32
;
2210 if ((i
.types
[op
] & (Disp32
| Disp32S
| Disp16
))
2211 && fits_in_signed_byte (disp
))
2212 i
.types
[op
] |= Disp8
;
2214 else if (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
2215 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
)
2217 fix_new_exp (frag_now
, frag_more (0) - frag_now
->fr_literal
, 0,
2218 i
.op
[op
].disps
, 0, i
.reloc
[op
]);
2219 i
.types
[op
] &= ~Disp
;
2222 /* We only support 64bit displacement on constants. */
2223 i
.types
[op
] &= ~Disp64
;
2230 /* Points to template once we've found it. */
2232 unsigned int overlap0
, overlap1
, overlap2
;
2233 unsigned int found_reverse_match
;
2236 #define MATCH(overlap, given, template) \
2237 ((overlap & ~JumpAbsolute) \
2238 && (((given) & (BaseIndex | JumpAbsolute)) \
2239 == ((overlap) & (BaseIndex | JumpAbsolute))))
2241 /* If given types r0 and r1 are registers they must be of the same type
2242 unless the expected operand type register overlap is null.
2243 Note that Acc in a template matches every size of reg. */
2244 #define CONSISTENT_REGISTER_MATCH(m0, g0, t0, m1, g1, t1) \
2245 (((g0) & Reg) == 0 || ((g1) & Reg) == 0 \
2246 || ((g0) & Reg) == ((g1) & Reg) \
2247 || ((((m0) & Acc) ? Reg : (t0)) & (((m1) & Acc) ? Reg : (t1)) & Reg) == 0 )
2252 found_reverse_match
= 0;
2253 suffix_check
= (i
.suffix
== BYTE_MNEM_SUFFIX
2255 : (i
.suffix
== WORD_MNEM_SUFFIX
2257 : (i
.suffix
== SHORT_MNEM_SUFFIX
2259 : (i
.suffix
== LONG_MNEM_SUFFIX
2261 : (i
.suffix
== QWORD_MNEM_SUFFIX
2263 : (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
2264 ? No_xSuf
: 0))))));
2266 for (t
= current_templates
->start
; t
< current_templates
->end
; t
++)
2268 /* Must have right number of operands. */
2269 if (i
.operands
!= t
->operands
)
2272 /* Check the suffix, except for some instructions in intel mode. */
2273 if ((t
->opcode_modifier
& suffix_check
)
2275 && (t
->opcode_modifier
& IgnoreSize
)))
2278 /* In general, don't allow 64-bit operands in 32-bit mode. */
2279 if (i
.suffix
== QWORD_MNEM_SUFFIX
2280 && flag_code
!= CODE_64BIT
2282 ? (!(t
->opcode_modifier
& IgnoreSize
)
2283 && !intel_float_operand (t
->name
))
2284 : intel_float_operand (t
->name
) != 2)
2285 && (!(t
->operand_types
[0] & (RegMMX
| RegXMM
))
2286 || !(t
->operand_types
[t
->operands
> 1] & (RegMMX
| RegXMM
)))
2287 && (t
->base_opcode
!= 0x0fc7
2288 || t
->extension_opcode
!= 1 /* cmpxchg8b */))
2291 /* Do not verify operands when there are none. */
2292 else if (!t
->operands
)
2294 if (t
->cpu_flags
& ~cpu_arch_flags
)
2296 /* We've found a match; break out of loop. */
2300 overlap0
= i
.types
[0] & t
->operand_types
[0];
2301 switch (t
->operands
)
2304 if (!MATCH (overlap0
, i
.types
[0], t
->operand_types
[0]))
2309 overlap1
= i
.types
[1] & t
->operand_types
[1];
2310 if (!MATCH (overlap0
, i
.types
[0], t
->operand_types
[0])
2311 || !MATCH (overlap1
, i
.types
[1], t
->operand_types
[1])
2312 /* monitor in SSE3 is a very special case. The first
2313 register and the second register may have differnet
2315 || !((t
->base_opcode
== 0x0f01
2316 && t
->extension_opcode
== 0xc8)
2317 || CONSISTENT_REGISTER_MATCH (overlap0
, i
.types
[0],
2318 t
->operand_types
[0],
2319 overlap1
, i
.types
[1],
2320 t
->operand_types
[1])))
2322 /* Check if other direction is valid ... */
2323 if ((t
->opcode_modifier
& (D
| FloatD
)) == 0)
2326 /* Try reversing direction of operands. */
2327 overlap0
= i
.types
[0] & t
->operand_types
[1];
2328 overlap1
= i
.types
[1] & t
->operand_types
[0];
2329 if (!MATCH (overlap0
, i
.types
[0], t
->operand_types
[1])
2330 || !MATCH (overlap1
, i
.types
[1], t
->operand_types
[0])
2331 || !CONSISTENT_REGISTER_MATCH (overlap0
, i
.types
[0],
2332 t
->operand_types
[1],
2333 overlap1
, i
.types
[1],
2334 t
->operand_types
[0]))
2336 /* Does not match either direction. */
2339 /* found_reverse_match holds which of D or FloatDR
2341 found_reverse_match
= t
->opcode_modifier
& (D
| FloatDR
);
2343 /* Found a forward 2 operand match here. */
2344 else if (t
->operands
== 3)
2346 /* Here we make use of the fact that there are no
2347 reverse match 3 operand instructions, and all 3
2348 operand instructions only need to be checked for
2349 register consistency between operands 2 and 3. */
2350 overlap2
= i
.types
[2] & t
->operand_types
[2];
2351 if (!MATCH (overlap2
, i
.types
[2], t
->operand_types
[2])
2352 || !CONSISTENT_REGISTER_MATCH (overlap1
, i
.types
[1],
2353 t
->operand_types
[1],
2354 overlap2
, i
.types
[2],
2355 t
->operand_types
[2]))
2359 /* Found either forward/reverse 2 or 3 operand match here:
2360 slip through to break. */
2362 if (t
->cpu_flags
& ~cpu_arch_flags
)
2364 found_reverse_match
= 0;
2367 /* We've found a match; break out of loop. */
2371 if (t
== current_templates
->end
)
2373 /* We found no match. */
2374 as_bad (_("suffix or operands invalid for `%s'"),
2375 current_templates
->start
->name
);
2379 if (!quiet_warnings
)
2382 && ((i
.types
[0] & JumpAbsolute
)
2383 != (t
->operand_types
[0] & JumpAbsolute
)))
2385 as_warn (_("indirect %s without `*'"), t
->name
);
2388 if ((t
->opcode_modifier
& (IsPrefix
| IgnoreSize
))
2389 == (IsPrefix
| IgnoreSize
))
2391 /* Warn them that a data or address size prefix doesn't
2392 affect assembly of the next line of code. */
2393 as_warn (_("stand-alone `%s' prefix"), t
->name
);
2397 /* Copy the template we found. */
2399 if (found_reverse_match
)
2401 /* If we found a reverse match we must alter the opcode
2402 direction bit. found_reverse_match holds bits to change
2403 (different for int & float insns). */
2405 i
.tm
.base_opcode
^= found_reverse_match
;
2407 i
.tm
.operand_types
[0] = t
->operand_types
[1];
2408 i
.tm
.operand_types
[1] = t
->operand_types
[0];
2417 int mem_op
= (i
.types
[0] & AnyMem
) ? 0 : 1;
2418 if ((i
.tm
.operand_types
[mem_op
] & EsSeg
) != 0)
2420 if (i
.seg
[0] != NULL
&& i
.seg
[0] != &es
)
2422 as_bad (_("`%s' operand %d must use `%%es' segment"),
2427 /* There's only ever one segment override allowed per instruction.
2428 This instruction possibly has a legal segment override on the
2429 second operand, so copy the segment to where non-string
2430 instructions store it, allowing common code. */
2431 i
.seg
[0] = i
.seg
[1];
2433 else if ((i
.tm
.operand_types
[mem_op
+ 1] & EsSeg
) != 0)
2435 if (i
.seg
[1] != NULL
&& i
.seg
[1] != &es
)
2437 as_bad (_("`%s' operand %d must use `%%es' segment"),
2447 process_suffix (void)
2449 /* If matched instruction specifies an explicit instruction mnemonic
2451 if (i
.tm
.opcode_modifier
& (Size16
| Size32
| Size64
))
2453 if (i
.tm
.opcode_modifier
& Size16
)
2454 i
.suffix
= WORD_MNEM_SUFFIX
;
2455 else if (i
.tm
.opcode_modifier
& Size64
)
2456 i
.suffix
= QWORD_MNEM_SUFFIX
;
2458 i
.suffix
= LONG_MNEM_SUFFIX
;
2460 else if (i
.reg_operands
)
2462 /* If there's no instruction mnemonic suffix we try to invent one
2463 based on register operands. */
2466 /* We take i.suffix from the last register operand specified,
2467 Destination register type is more significant than source
2471 for (op
= i
.operands
; --op
>= 0;)
2472 if ((i
.types
[op
] & Reg
)
2473 && !(i
.tm
.operand_types
[op
] & InOutPortReg
))
2475 i
.suffix
= ((i
.types
[op
] & Reg8
) ? BYTE_MNEM_SUFFIX
:
2476 (i
.types
[op
] & Reg16
) ? WORD_MNEM_SUFFIX
:
2477 (i
.types
[op
] & Reg64
) ? QWORD_MNEM_SUFFIX
:
2482 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
2484 if (!check_byte_reg ())
2487 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
2489 if (!check_long_reg ())
2492 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
2494 if (!check_qword_reg ())
2497 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
2499 if (!check_word_reg ())
2502 else if (intel_syntax
&& (i
.tm
.opcode_modifier
& IgnoreSize
))
2503 /* Do nothing if the instruction is going to ignore the prefix. */
2508 else if ((i
.tm
.opcode_modifier
& DefaultSize
)
2510 /* exclude fldenv/frstor/fsave/fstenv */
2511 && (i
.tm
.opcode_modifier
& No_sSuf
))
2513 i
.suffix
= stackop_size
;
2515 else if (intel_syntax
2517 && ((i
.tm
.operand_types
[0] & JumpAbsolute
)
2518 || (i
.tm
.opcode_modifier
& (JumpByte
|JumpInterSegment
))
2519 || (i
.tm
.base_opcode
== 0x0f01 /* [ls][gi]dt */
2520 && i
.tm
.extension_opcode
<= 3)))
2525 if (!(i
.tm
.opcode_modifier
& No_qSuf
))
2527 i
.suffix
= QWORD_MNEM_SUFFIX
;
2531 if (!(i
.tm
.opcode_modifier
& No_lSuf
))
2532 i
.suffix
= LONG_MNEM_SUFFIX
;
2535 if (!(i
.tm
.opcode_modifier
& No_wSuf
))
2536 i
.suffix
= WORD_MNEM_SUFFIX
;
2545 if (i
.tm
.opcode_modifier
& W
)
2547 as_bad (_("no instruction mnemonic suffix given and no register operands; can't size instruction"));
2553 unsigned int suffixes
= (~i
.tm
.opcode_modifier
2561 if ((i
.tm
.opcode_modifier
& W
)
2562 || ((suffixes
& (suffixes
- 1))
2563 && !(i
.tm
.opcode_modifier
& (DefaultSize
| IgnoreSize
))))
2565 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
2571 /* Change the opcode based on the operand size given by i.suffix;
2572 We don't need to change things for byte insns. */
2574 if (i
.suffix
&& i
.suffix
!= BYTE_MNEM_SUFFIX
)
2576 /* It's not a byte, select word/dword operation. */
2577 if (i
.tm
.opcode_modifier
& W
)
2579 if (i
.tm
.opcode_modifier
& ShortForm
)
2580 i
.tm
.base_opcode
|= 8;
2582 i
.tm
.base_opcode
|= 1;
2585 /* Now select between word & dword operations via the operand
2586 size prefix, except for instructions that will ignore this
2588 if (i
.tm
.base_opcode
== 0x0f01 && i
.tm
.extension_opcode
== 0xc8)
2590 /* monitor in SSE3 is a very special case. The default size
2591 of AX is the size of mode. The address size override
2592 prefix will change the size of AX. */
2593 if (i
.op
->regs
[0].reg_type
&
2594 (flag_code
== CODE_32BIT
? Reg16
: Reg32
))
2595 if (!add_prefix (ADDR_PREFIX_OPCODE
))
2598 else if (i
.suffix
!= QWORD_MNEM_SUFFIX
2599 && i
.suffix
!= LONG_DOUBLE_MNEM_SUFFIX
2600 && !(i
.tm
.opcode_modifier
& (IgnoreSize
| FloatMF
))
2601 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
2602 || (flag_code
== CODE_64BIT
2603 && (i
.tm
.opcode_modifier
& JumpByte
))))
2605 unsigned int prefix
= DATA_PREFIX_OPCODE
;
2607 if (i
.tm
.opcode_modifier
& JumpByte
) /* jcxz, loop */
2608 prefix
= ADDR_PREFIX_OPCODE
;
2610 if (!add_prefix (prefix
))
2614 /* Set mode64 for an operand. */
2615 if (i
.suffix
== QWORD_MNEM_SUFFIX
2616 && flag_code
== CODE_64BIT
2617 && (i
.tm
.opcode_modifier
& NoRex64
) == 0)
2618 i
.rex
|= REX_MODE64
;
2620 /* Size floating point instruction. */
2621 if (i
.suffix
== LONG_MNEM_SUFFIX
)
2622 if (i
.tm
.opcode_modifier
& FloatMF
)
2623 i
.tm
.base_opcode
^= 4;
2630 check_byte_reg (void)
2634 for (op
= i
.operands
; --op
>= 0;)
2636 /* If this is an eight bit register, it's OK. If it's the 16 or
2637 32 bit version of an eight bit register, we will just use the
2638 low portion, and that's OK too. */
2639 if (i
.types
[op
] & Reg8
)
2642 /* movzx and movsx should not generate this warning. */
2644 && (i
.tm
.base_opcode
== 0xfb7
2645 || i
.tm
.base_opcode
== 0xfb6
2646 || i
.tm
.base_opcode
== 0x63
2647 || i
.tm
.base_opcode
== 0xfbe
2648 || i
.tm
.base_opcode
== 0xfbf))
2651 if ((i
.types
[op
] & WordReg
) && i
.op
[op
].regs
->reg_num
< 4)
2653 /* Prohibit these changes in the 64bit mode, since the
2654 lowering is more complicated. */
2655 if (flag_code
== CODE_64BIT
2656 && (i
.tm
.operand_types
[op
] & InOutPortReg
) == 0)
2658 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
2659 i
.op
[op
].regs
->reg_name
,
2663 #if REGISTER_WARNINGS
2665 && (i
.tm
.operand_types
[op
] & InOutPortReg
) == 0)
2666 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2667 (i
.op
[op
].regs
+ (i
.types
[op
] & Reg16
2668 ? REGNAM_AL
- REGNAM_AX
2669 : REGNAM_AL
- REGNAM_EAX
))->reg_name
,
2670 i
.op
[op
].regs
->reg_name
,
2675 /* Any other register is bad. */
2676 if (i
.types
[op
] & (Reg
| RegMMX
| RegXMM
2678 | Control
| Debug
| Test
2679 | FloatReg
| FloatAcc
))
2681 as_bad (_("`%%%s' not allowed with `%s%c'"),
2682 i
.op
[op
].regs
->reg_name
,
2696 for (op
= i
.operands
; --op
>= 0;)
2697 /* Reject eight bit registers, except where the template requires
2698 them. (eg. movzb) */
2699 if ((i
.types
[op
] & Reg8
) != 0
2700 && (i
.tm
.operand_types
[op
] & (Reg16
| Reg32
| Acc
)) != 0)
2702 as_bad (_("`%%%s' not allowed with `%s%c'"),
2703 i
.op
[op
].regs
->reg_name
,
2708 /* Warn if the e prefix on a general reg is missing. */
2709 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
2710 && (i
.types
[op
] & Reg16
) != 0
2711 && (i
.tm
.operand_types
[op
] & (Reg32
| Acc
)) != 0)
2713 /* Prohibit these changes in the 64bit mode, since the
2714 lowering is more complicated. */
2715 if (flag_code
== CODE_64BIT
)
2717 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
2718 i
.op
[op
].regs
->reg_name
,
2722 #if REGISTER_WARNINGS
2724 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2725 (i
.op
[op
].regs
+ REGNAM_EAX
- REGNAM_AX
)->reg_name
,
2726 i
.op
[op
].regs
->reg_name
,
2730 /* Warn if the r prefix on a general reg is missing. */
2731 else if ((i
.types
[op
] & Reg64
) != 0
2732 && (i
.tm
.operand_types
[op
] & (Reg32
| Acc
)) != 0)
2734 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
2735 i
.op
[op
].regs
->reg_name
,
2747 for (op
= i
.operands
; --op
>= 0; )
2748 /* Reject eight bit registers, except where the template requires
2749 them. (eg. movzb) */
2750 if ((i
.types
[op
] & Reg8
) != 0
2751 && (i
.tm
.operand_types
[op
] & (Reg16
| Reg32
| Acc
)) != 0)
2753 as_bad (_("`%%%s' not allowed with `%s%c'"),
2754 i
.op
[op
].regs
->reg_name
,
2759 /* Warn if the e prefix on a general reg is missing. */
2760 else if (((i
.types
[op
] & Reg16
) != 0
2761 || (i
.types
[op
] & Reg32
) != 0)
2762 && (i
.tm
.operand_types
[op
] & (Reg32
| Acc
)) != 0)
2764 /* Prohibit these changes in the 64bit mode, since the
2765 lowering is more complicated. */
2766 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
2767 i
.op
[op
].regs
->reg_name
,
2778 for (op
= i
.operands
; --op
>= 0;)
2779 /* Reject eight bit registers, except where the template requires
2780 them. (eg. movzb) */
2781 if ((i
.types
[op
] & Reg8
) != 0
2782 && (i
.tm
.operand_types
[op
] & (Reg16
| Reg32
| Acc
)) != 0)
2784 as_bad (_("`%%%s' not allowed with `%s%c'"),
2785 i
.op
[op
].regs
->reg_name
,
2790 /* Warn if the e prefix on a general reg is present. */
2791 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
2792 && (i
.types
[op
] & Reg32
) != 0
2793 && (i
.tm
.operand_types
[op
] & (Reg16
| Acc
)) != 0)
2795 /* Prohibit these changes in the 64bit mode, since the
2796 lowering is more complicated. */
2797 if (flag_code
== CODE_64BIT
)
2799 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
2800 i
.op
[op
].regs
->reg_name
,
2805 #if REGISTER_WARNINGS
2806 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2807 (i
.op
[op
].regs
+ REGNAM_AX
- REGNAM_EAX
)->reg_name
,
2808 i
.op
[op
].regs
->reg_name
,
2818 unsigned int overlap0
, overlap1
, overlap2
;
2820 overlap0
= i
.types
[0] & i
.tm
.operand_types
[0];
2821 if ((overlap0
& (Imm8
| Imm8S
| Imm16
| Imm32
| Imm32S
| Imm64
))
2822 && overlap0
!= Imm8
&& overlap0
!= Imm8S
2823 && overlap0
!= Imm16
&& overlap0
!= Imm32S
2824 && overlap0
!= Imm32
&& overlap0
!= Imm64
)
2828 overlap0
&= (i
.suffix
== BYTE_MNEM_SUFFIX
2830 : (i
.suffix
== WORD_MNEM_SUFFIX
2832 : (i
.suffix
== QWORD_MNEM_SUFFIX
2836 else if (overlap0
== (Imm16
| Imm32S
| Imm32
)
2837 || overlap0
== (Imm16
| Imm32
)
2838 || overlap0
== (Imm16
| Imm32S
))
2840 overlap0
= ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0)
2843 if (overlap0
!= Imm8
&& overlap0
!= Imm8S
2844 && overlap0
!= Imm16
&& overlap0
!= Imm32S
2845 && overlap0
!= Imm32
&& overlap0
!= Imm64
)
2847 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size"));
2851 i
.types
[0] = overlap0
;
2853 overlap1
= i
.types
[1] & i
.tm
.operand_types
[1];
2854 if ((overlap1
& (Imm8
| Imm8S
| Imm16
| Imm32S
| Imm32
| Imm64
))
2855 && overlap1
!= Imm8
&& overlap1
!= Imm8S
2856 && overlap1
!= Imm16
&& overlap1
!= Imm32S
2857 && overlap1
!= Imm32
&& overlap1
!= Imm64
)
2861 overlap1
&= (i
.suffix
== BYTE_MNEM_SUFFIX
2863 : (i
.suffix
== WORD_MNEM_SUFFIX
2865 : (i
.suffix
== QWORD_MNEM_SUFFIX
2869 else if (overlap1
== (Imm16
| Imm32
| Imm32S
)
2870 || overlap1
== (Imm16
| Imm32
)
2871 || overlap1
== (Imm16
| Imm32S
))
2873 overlap1
= ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0)
2876 if (overlap1
!= Imm8
&& overlap1
!= Imm8S
2877 && overlap1
!= Imm16
&& overlap1
!= Imm32S
2878 && overlap1
!= Imm32
&& overlap1
!= Imm64
)
2880 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size %x %c"),overlap1
, i
.suffix
);
2884 i
.types
[1] = overlap1
;
2886 overlap2
= i
.types
[2] & i
.tm
.operand_types
[2];
2887 assert ((overlap2
& Imm
) == 0);
2888 i
.types
[2] = overlap2
;
2896 /* Default segment register this instruction will use for memory
2897 accesses. 0 means unknown. This is only for optimizing out
2898 unnecessary segment overrides. */
2899 const seg_entry
*default_seg
= 0;
2901 /* The imul $imm, %reg instruction is converted into
2902 imul $imm, %reg, %reg, and the clr %reg instruction
2903 is converted into xor %reg, %reg. */
2904 if (i
.tm
.opcode_modifier
& regKludge
)
2906 unsigned int first_reg_op
= (i
.types
[0] & Reg
) ? 0 : 1;
2907 /* Pretend we saw the extra register operand. */
2908 assert (i
.op
[first_reg_op
+ 1].regs
== 0);
2909 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
2910 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
2914 if (i
.tm
.opcode_modifier
& ShortForm
)
2916 /* The register or float register operand is in operand 0 or 1. */
2917 unsigned int op
= (i
.types
[0] & (Reg
| FloatReg
)) ? 0 : 1;
2918 /* Register goes in low 3 bits of opcode. */
2919 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
2920 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
2922 if (!quiet_warnings
&& (i
.tm
.opcode_modifier
& Ugh
) != 0)
2924 /* Warn about some common errors, but press on regardless.
2925 The first case can be generated by gcc (<= 2.8.1). */
2926 if (i
.operands
== 2)
2928 /* Reversed arguments on faddp, fsubp, etc. */
2929 as_warn (_("translating to `%s %%%s,%%%s'"), i
.tm
.name
,
2930 i
.op
[1].regs
->reg_name
,
2931 i
.op
[0].regs
->reg_name
);
2935 /* Extraneous `l' suffix on fp insn. */
2936 as_warn (_("translating to `%s %%%s'"), i
.tm
.name
,
2937 i
.op
[0].regs
->reg_name
);
2941 else if (i
.tm
.opcode_modifier
& Modrm
)
2943 /* The opcode is completed (modulo i.tm.extension_opcode which
2944 must be put into the modrm byte). Now, we make the modrm and
2945 index base bytes based on all the info we've collected. */
2947 default_seg
= build_modrm_byte ();
2949 else if (i
.tm
.opcode_modifier
& (Seg2ShortForm
| Seg3ShortForm
))
2951 if (i
.tm
.base_opcode
== POP_SEG_SHORT
2952 && i
.op
[0].regs
->reg_num
== 1)
2954 as_bad (_("you can't `pop %%cs'"));
2957 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
2958 if ((i
.op
[0].regs
->reg_flags
& RegRex
) != 0)
2961 else if ((i
.tm
.base_opcode
& ~(D
| W
)) == MOV_AX_DISP32
)
2965 else if ((i
.tm
.opcode_modifier
& IsString
) != 0)
2967 /* For the string instructions that allow a segment override
2968 on one of their operands, the default segment is ds. */
2972 if ((i
.tm
.base_opcode
== 0x8d /* lea */
2973 || (i
.tm
.cpu_flags
& CpuSVME
))
2974 && i
.seg
[0] && !quiet_warnings
)
2975 as_warn (_("segment override on `%s' is ineffectual"), i
.tm
.name
);
2977 /* If a segment was explicitly specified, and the specified segment
2978 is not the default, use an opcode prefix to select it. If we
2979 never figured out what the default segment is, then default_seg
2980 will be zero at this point, and the specified segment prefix will
2982 if ((i
.seg
[0]) && (i
.seg
[0] != default_seg
))
2984 if (!add_prefix (i
.seg
[0]->seg_prefix
))
2990 static const seg_entry
*
2993 const seg_entry
*default_seg
= 0;
2995 /* i.reg_operands MUST be the number of real register operands;
2996 implicit registers do not count. */
2997 if (i
.reg_operands
== 2)
2999 unsigned int source
, dest
;
3000 source
= ((i
.types
[0]
3001 & (Reg
| RegMMX
| RegXMM
3003 | Control
| Debug
| Test
))
3008 /* One of the register operands will be encoded in the i.tm.reg
3009 field, the other in the combined i.tm.mode and i.tm.regmem
3010 fields. If no form of this instruction supports a memory
3011 destination operand, then we assume the source operand may
3012 sometimes be a memory operand and so we need to store the
3013 destination in the i.rm.reg field. */
3014 if ((i
.tm
.operand_types
[dest
] & AnyMem
) == 0)
3016 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
3017 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
3018 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
3020 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
3025 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
3026 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
3027 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
3029 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
3032 if (flag_code
!= CODE_64BIT
&& (i
.rex
& (REX_EXTX
| REX_EXTZ
)))
3034 if (!((i
.types
[0] | i
.types
[1]) & Control
))
3036 i
.rex
&= ~(REX_EXTX
| REX_EXTZ
);
3037 add_prefix (LOCK_PREFIX_OPCODE
);
3041 { /* If it's not 2 reg operands... */
3044 unsigned int fake_zero_displacement
= 0;
3045 unsigned int op
= ((i
.types
[0] & AnyMem
)
3047 : (i
.types
[1] & AnyMem
) ? 1 : 2);
3051 if (i
.base_reg
== 0)
3054 if (!i
.disp_operands
)
3055 fake_zero_displacement
= 1;
3056 if (i
.index_reg
== 0)
3058 /* Operand is just <disp> */
3059 if (flag_code
== CODE_64BIT
)
3061 /* 64bit mode overwrites the 32bit absolute
3062 addressing by RIP relative addressing and
3063 absolute addressing is encoded by one of the
3064 redundant SIB forms. */
3065 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
3066 i
.sib
.base
= NO_BASE_REGISTER
;
3067 i
.sib
.index
= NO_INDEX_REGISTER
;
3068 i
.types
[op
] = ((i
.prefix
[ADDR_PREFIX
] == 0) ? Disp32S
: Disp32
);
3070 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[ADDR_PREFIX
] != 0))
3072 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
3073 i
.types
[op
] = Disp16
;
3077 i
.rm
.regmem
= NO_BASE_REGISTER
;
3078 i
.types
[op
] = Disp32
;
3081 else /* !i.base_reg && i.index_reg */
3083 i
.sib
.index
= i
.index_reg
->reg_num
;
3084 i
.sib
.base
= NO_BASE_REGISTER
;
3085 i
.sib
.scale
= i
.log2_scale_factor
;
3086 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
3087 i
.types
[op
] &= ~Disp
;
3088 if (flag_code
!= CODE_64BIT
)
3089 i
.types
[op
] |= Disp32
; /* Must be 32 bit */
3091 i
.types
[op
] |= Disp32S
;
3092 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
3096 /* RIP addressing for 64bit mode. */
3097 else if (i
.base_reg
->reg_type
== BaseIndex
)
3099 i
.rm
.regmem
= NO_BASE_REGISTER
;
3100 i
.types
[op
] &= ~ Disp
;
3101 i
.types
[op
] |= Disp32S
;
3102 i
.flags
[op
] = Operand_PCrel
;
3103 if (! i
.disp_operands
)
3104 fake_zero_displacement
= 1;
3106 else if (i
.base_reg
->reg_type
& Reg16
)
3108 switch (i
.base_reg
->reg_num
)
3111 if (i
.index_reg
== 0)
3113 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
3114 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
3118 if (i
.index_reg
== 0)
3121 if ((i
.types
[op
] & Disp
) == 0)
3123 /* fake (%bp) into 0(%bp) */
3124 i
.types
[op
] |= Disp8
;
3125 fake_zero_displacement
= 1;
3128 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
3129 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
3131 default: /* (%si) -> 4 or (%di) -> 5 */
3132 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
3134 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
3136 else /* i.base_reg and 32/64 bit mode */
3138 if (flag_code
== CODE_64BIT
3139 && (i
.types
[op
] & Disp
))
3140 i
.types
[op
] = (i
.types
[op
] & Disp8
) | (i
.prefix
[ADDR_PREFIX
] == 0 ? Disp32S
: Disp32
);
3142 i
.rm
.regmem
= i
.base_reg
->reg_num
;
3143 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
3145 i
.sib
.base
= i
.base_reg
->reg_num
;
3146 /* x86-64 ignores REX prefix bit here to avoid decoder
3148 if ((i
.base_reg
->reg_num
& 7) == EBP_REG_NUM
)
3151 if (i
.disp_operands
== 0)
3153 fake_zero_displacement
= 1;
3154 i
.types
[op
] |= Disp8
;
3157 else if (i
.base_reg
->reg_num
== ESP_REG_NUM
)
3161 i
.sib
.scale
= i
.log2_scale_factor
;
3162 if (i
.index_reg
== 0)
3164 /* <disp>(%esp) becomes two byte modrm with no index
3165 register. We've already stored the code for esp
3166 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
3167 Any base register besides %esp will not use the
3168 extra modrm byte. */
3169 i
.sib
.index
= NO_INDEX_REGISTER
;
3170 #if !SCALE1_WHEN_NO_INDEX
3171 /* Another case where we force the second modrm byte. */
3172 if (i
.log2_scale_factor
)
3173 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
3178 i
.sib
.index
= i
.index_reg
->reg_num
;
3179 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
3180 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
3185 && (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
3186 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
))
3189 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
3192 if (fake_zero_displacement
)
3194 /* Fakes a zero displacement assuming that i.types[op]
3195 holds the correct displacement size. */
3198 assert (i
.op
[op
].disps
== 0);
3199 exp
= &disp_expressions
[i
.disp_operands
++];
3200 i
.op
[op
].disps
= exp
;
3201 exp
->X_op
= O_constant
;
3202 exp
->X_add_number
= 0;
3203 exp
->X_add_symbol
= (symbolS
*) 0;
3204 exp
->X_op_symbol
= (symbolS
*) 0;
3208 /* Fill in i.rm.reg or i.rm.regmem field with register operand
3209 (if any) based on i.tm.extension_opcode. Again, we must be
3210 careful to make sure that segment/control/debug/test/MMX
3211 registers are coded into the i.rm.reg field. */
3216 & (Reg
| RegMMX
| RegXMM
3218 | Control
| Debug
| Test
))
3221 & (Reg
| RegMMX
| RegXMM
3223 | Control
| Debug
| Test
))
3226 /* If there is an extension opcode to put here, the register
3227 number must be put into the regmem field. */
3228 if (i
.tm
.extension_opcode
!= None
)
3230 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
3231 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
3236 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
3237 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
3241 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
3242 must set it to 3 to indicate this is a register operand
3243 in the regmem field. */
3244 if (!i
.mem_operands
)
3248 /* Fill in i.rm.reg field with extension opcode (if any). */
3249 if (i
.tm
.extension_opcode
!= None
)
3250 i
.rm
.reg
= i
.tm
.extension_opcode
;
3261 relax_substateT subtype
;
3266 if (flag_code
== CODE_16BIT
)
3270 if (i
.prefix
[DATA_PREFIX
] != 0)
3276 /* Pentium4 branch hints. */
3277 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
3278 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
3283 if (i
.prefix
[REX_PREFIX
] != 0)
3289 if (i
.prefixes
!= 0 && !intel_syntax
)
3290 as_warn (_("skipping prefixes on this instruction"));
3292 /* It's always a symbol; End frag & setup for relax.
3293 Make sure there is enough room in this frag for the largest
3294 instruction we may generate in md_convert_frag. This is 2
3295 bytes for the opcode and room for the prefix and largest
3297 frag_grow (prefix
+ 2 + 4);
3298 /* Prefix and 1 opcode byte go in fr_fix. */
3299 p
= frag_more (prefix
+ 1);
3300 if (i
.prefix
[DATA_PREFIX
] != 0)
3301 *p
++ = DATA_PREFIX_OPCODE
;
3302 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
3303 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
3304 *p
++ = i
.prefix
[SEG_PREFIX
];
3305 if (i
.prefix
[REX_PREFIX
] != 0)
3306 *p
++ = i
.prefix
[REX_PREFIX
];
3307 *p
= i
.tm
.base_opcode
;
3309 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
3310 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, SMALL
);
3311 else if ((cpu_arch_flags
& Cpu386
) != 0)
3312 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, SMALL
);
3314 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, SMALL
);
3317 sym
= i
.op
[0].disps
->X_add_symbol
;
3318 off
= i
.op
[0].disps
->X_add_number
;
3320 if (i
.op
[0].disps
->X_op
!= O_constant
3321 && i
.op
[0].disps
->X_op
!= O_symbol
)
3323 /* Handle complex expressions. */
3324 sym
= make_expr_symbol (i
.op
[0].disps
);
3328 /* 1 possible extra opcode + 4 byte displacement go in var part.
3329 Pass reloc in fr_var. */
3330 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
3340 if (i
.tm
.opcode_modifier
& JumpByte
)
3342 /* This is a loop or jecxz type instruction. */
3344 if (i
.prefix
[ADDR_PREFIX
] != 0)
3346 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
3349 /* Pentium4 branch hints. */
3350 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
3351 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
3353 FRAG_APPEND_1_CHAR (i
.prefix
[SEG_PREFIX
]);
3362 if (flag_code
== CODE_16BIT
)
3365 if (i
.prefix
[DATA_PREFIX
] != 0)
3367 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
3377 if (i
.prefix
[REX_PREFIX
] != 0)
3379 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
3383 if (i
.prefixes
!= 0 && !intel_syntax
)
3384 as_warn (_("skipping prefixes on this instruction"));
3386 p
= frag_more (1 + size
);
3387 *p
++ = i
.tm
.base_opcode
;
3389 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
3390 i
.op
[0].disps
, 1, reloc (size
, 1, 1, i
.reloc
[0]));
3392 /* All jumps handled here are signed, but don't use a signed limit
3393 check for 32 and 16 bit jumps as we want to allow wrap around at
3394 4G and 64k respectively. */
3396 fixP
->fx_signed
= 1;
3400 output_interseg_jump ()
3408 if (flag_code
== CODE_16BIT
)
3412 if (i
.prefix
[DATA_PREFIX
] != 0)
3418 if (i
.prefix
[REX_PREFIX
] != 0)
3428 if (i
.prefixes
!= 0 && !intel_syntax
)
3429 as_warn (_("skipping prefixes on this instruction"));
3431 /* 1 opcode; 2 segment; offset */
3432 p
= frag_more (prefix
+ 1 + 2 + size
);
3434 if (i
.prefix
[DATA_PREFIX
] != 0)
3435 *p
++ = DATA_PREFIX_OPCODE
;
3437 if (i
.prefix
[REX_PREFIX
] != 0)
3438 *p
++ = i
.prefix
[REX_PREFIX
];
3440 *p
++ = i
.tm
.base_opcode
;
3441 if (i
.op
[1].imms
->X_op
== O_constant
)
3443 offsetT n
= i
.op
[1].imms
->X_add_number
;
3446 && !fits_in_unsigned_word (n
)
3447 && !fits_in_signed_word (n
))
3449 as_bad (_("16-bit jump out of range"));
3452 md_number_to_chars (p
, n
, size
);
3455 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
3456 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
3457 if (i
.op
[0].imms
->X_op
!= O_constant
)
3458 as_bad (_("can't handle non absolute segment in `%s'"),
3460 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
3466 fragS
*insn_start_frag
;
3467 offsetT insn_start_off
;
3469 /* Tie dwarf2 debug info to the address at the start of the insn.
3470 We can't do this after the insn has been output as the current
3471 frag may have been closed off. eg. by frag_var. */
3472 dwarf2_emit_insn (0);
3474 insn_start_frag
= frag_now
;
3475 insn_start_off
= frag_now_fix ();
3478 if (i
.tm
.opcode_modifier
& Jump
)
3480 else if (i
.tm
.opcode_modifier
& (JumpByte
| JumpDword
))
3482 else if (i
.tm
.opcode_modifier
& JumpInterSegment
)
3483 output_interseg_jump ();
3486 /* Output normal instructions here. */
3489 unsigned int prefix
;
3491 /* All opcodes on i386 have either 1 or 2 bytes. Merom New
3492 Instructions have 3 bytes. We may use one more higher byte
3493 to specify a prefix the instruction requires. */
3494 if ((i
.tm
.cpu_flags
& CpuMNI
) != 0)
3496 if (i
.tm
.base_opcode
& 0xff000000)
3498 prefix
= (i
.tm
.base_opcode
>> 24) & 0xff;
3502 else if ((i
.tm
.base_opcode
& 0xff0000) != 0)
3504 prefix
= (i
.tm
.base_opcode
>> 16) & 0xff;
3505 if ((i
.tm
.cpu_flags
& CpuPadLock
) != 0)
3508 if (prefix
!= REPE_PREFIX_OPCODE
3509 || i
.prefix
[LOCKREP_PREFIX
] != REPE_PREFIX_OPCODE
)
3510 add_prefix (prefix
);
3513 add_prefix (prefix
);
3516 /* The prefix bytes. */
3518 q
< i
.prefix
+ sizeof (i
.prefix
) / sizeof (i
.prefix
[0]);
3524 md_number_to_chars (p
, (valueT
) *q
, 1);
3528 /* Now the opcode; be careful about word order here! */
3529 if (fits_in_unsigned_byte (i
.tm
.base_opcode
))
3531 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
3535 if ((i
.tm
.cpu_flags
& CpuMNI
) != 0)
3538 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
3543 /* Put out high byte first: can't use md_number_to_chars! */
3544 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
3545 *p
= i
.tm
.base_opcode
& 0xff;
3548 /* Now the modrm byte and sib byte (if present). */
3549 if (i
.tm
.opcode_modifier
& Modrm
)
3552 md_number_to_chars (p
,
3553 (valueT
) (i
.rm
.regmem
<< 0
3557 /* If i.rm.regmem == ESP (4)
3558 && i.rm.mode != (Register mode)
3560 ==> need second modrm byte. */
3561 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
3563 && !(i
.base_reg
&& (i
.base_reg
->reg_type
& Reg16
) != 0))
3566 md_number_to_chars (p
,
3567 (valueT
) (i
.sib
.base
<< 0
3569 | i
.sib
.scale
<< 6),
3574 if (i
.disp_operands
)
3575 output_disp (insn_start_frag
, insn_start_off
);
3578 output_imm (insn_start_frag
, insn_start_off
);
3584 pi ("" /*line*/, &i
);
3586 #endif /* DEBUG386 */
3590 output_disp (fragS
*insn_start_frag
, offsetT insn_start_off
)
3595 for (n
= 0; n
< i
.operands
; n
++)
3597 if (i
.types
[n
] & Disp
)
3599 if (i
.op
[n
].disps
->X_op
== O_constant
)
3605 if (i
.types
[n
] & (Disp8
| Disp16
| Disp64
))
3608 if (i
.types
[n
] & Disp8
)
3610 if (i
.types
[n
] & Disp64
)
3613 val
= offset_in_range (i
.op
[n
].disps
->X_add_number
,
3615 p
= frag_more (size
);
3616 md_number_to_chars (p
, val
, size
);
3620 enum bfd_reloc_code_real reloc_type
;
3623 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
3625 /* The PC relative address is computed relative
3626 to the instruction boundary, so in case immediate
3627 fields follows, we need to adjust the value. */
3628 if (pcrel
&& i
.imm_operands
)
3633 for (n1
= 0; n1
< i
.operands
; n1
++)
3634 if (i
.types
[n1
] & Imm
)
3636 if (i
.types
[n1
] & (Imm8
| Imm8S
| Imm16
| Imm64
))
3639 if (i
.types
[n1
] & (Imm8
| Imm8S
))
3641 if (i
.types
[n1
] & Imm64
)
3646 /* We should find the immediate. */
3647 if (n1
== i
.operands
)
3649 i
.op
[n
].disps
->X_add_number
-= imm_size
;
3652 if (i
.types
[n
] & Disp32S
)
3655 if (i
.types
[n
] & (Disp16
| Disp64
))
3658 if (i
.types
[n
] & Disp64
)
3662 p
= frag_more (size
);
3663 reloc_type
= reloc (size
, pcrel
, sign
, i
.reloc
[n
]);
3665 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
3666 && (((reloc_type
== BFD_RELOC_32
3667 || reloc_type
== BFD_RELOC_X86_64_32S
3668 || (reloc_type
== BFD_RELOC_64
3670 && (i
.op
[n
].disps
->X_op
== O_symbol
3671 || (i
.op
[n
].disps
->X_op
== O_add
3672 && ((symbol_get_value_expression
3673 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
3675 || reloc_type
== BFD_RELOC_32_PCREL
))
3679 if (insn_start_frag
== frag_now
)
3680 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
3685 add
= insn_start_frag
->fr_fix
- insn_start_off
;
3686 for (fr
= insn_start_frag
->fr_next
;
3687 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
3689 add
+= p
- frag_now
->fr_literal
;
3694 reloc_type
= BFD_RELOC_386_GOTPC
;
3695 i
.op
[n
].imms
->X_add_number
+= add
;
3697 else if (reloc_type
== BFD_RELOC_64
)
3698 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
3700 /* Don't do the adjustment for x86-64, as there
3701 the pcrel addressing is relative to the _next_
3702 insn, and that is taken care of in other code. */
3703 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
3705 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
3706 i
.op
[n
].disps
, pcrel
, reloc_type
);
3713 output_imm (fragS
*insn_start_frag
, offsetT insn_start_off
)
3718 for (n
= 0; n
< i
.operands
; n
++)
3720 if (i
.types
[n
] & Imm
)
3722 if (i
.op
[n
].imms
->X_op
== O_constant
)
3728 if (i
.types
[n
] & (Imm8
| Imm8S
| Imm16
| Imm64
))
3731 if (i
.types
[n
] & (Imm8
| Imm8S
))
3733 else if (i
.types
[n
] & Imm64
)
3736 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
3738 p
= frag_more (size
);
3739 md_number_to_chars (p
, val
, size
);
3743 /* Not absolute_section.
3744 Need a 32-bit fixup (don't support 8bit
3745 non-absolute imms). Try to support other
3747 enum bfd_reloc_code_real reloc_type
;
3751 if ((i
.types
[n
] & (Imm32S
))
3752 && (i
.suffix
== QWORD_MNEM_SUFFIX
3753 || (!i
.suffix
&& (i
.tm
.opcode_modifier
& No_lSuf
))))
3755 if (i
.types
[n
] & (Imm8
| Imm8S
| Imm16
| Imm64
))
3758 if (i
.types
[n
] & (Imm8
| Imm8S
))
3760 if (i
.types
[n
] & Imm64
)
3764 p
= frag_more (size
);
3765 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
3767 /* This is tough to explain. We end up with this one if we
3768 * have operands that look like
3769 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
3770 * obtain the absolute address of the GOT, and it is strongly
3771 * preferable from a performance point of view to avoid using
3772 * a runtime relocation for this. The actual sequence of
3773 * instructions often look something like:
3778 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
3780 * The call and pop essentially return the absolute address
3781 * of the label .L66 and store it in %ebx. The linker itself
3782 * will ultimately change the first operand of the addl so
3783 * that %ebx points to the GOT, but to keep things simple, the
3784 * .o file must have this operand set so that it generates not
3785 * the absolute address of .L66, but the absolute address of
3786 * itself. This allows the linker itself simply treat a GOTPC
3787 * relocation as asking for a pcrel offset to the GOT to be
3788 * added in, and the addend of the relocation is stored in the
3789 * operand field for the instruction itself.
3791 * Our job here is to fix the operand so that it would add
3792 * the correct offset so that %ebx would point to itself. The
3793 * thing that is tricky is that .-.L66 will point to the
3794 * beginning of the instruction, so we need to further modify
3795 * the operand so that it will point to itself. There are
3796 * other cases where you have something like:
3798 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
3800 * and here no correction would be required. Internally in
3801 * the assembler we treat operands of this form as not being
3802 * pcrel since the '.' is explicitly mentioned, and I wonder
3803 * whether it would simplify matters to do it this way. Who
3804 * knows. In earlier versions of the PIC patches, the
3805 * pcrel_adjust field was used to store the correction, but
3806 * since the expression is not pcrel, I felt it would be
3807 * confusing to do it this way. */
3809 if ((reloc_type
== BFD_RELOC_32
3810 || reloc_type
== BFD_RELOC_X86_64_32S
3811 || reloc_type
== BFD_RELOC_64
)
3813 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
3814 && (i
.op
[n
].imms
->X_op
== O_symbol
3815 || (i
.op
[n
].imms
->X_op
== O_add
3816 && ((symbol_get_value_expression
3817 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
3822 if (insn_start_frag
== frag_now
)
3823 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
3828 add
= insn_start_frag
->fr_fix
- insn_start_off
;
3829 for (fr
= insn_start_frag
->fr_next
;
3830 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
3832 add
+= p
- frag_now
->fr_literal
;
3836 reloc_type
= BFD_RELOC_386_GOTPC
;
3838 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
3840 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
3841 i
.op
[n
].imms
->X_add_number
+= add
;
3843 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
3844 i
.op
[n
].imms
, 0, reloc_type
);
3850 /* x86_cons_fix_new is called via the expression parsing code when a
3851 reloc is needed. We use this hook to get the correct .got reloc. */
3852 static enum bfd_reloc_code_real got_reloc
= NO_RELOC
;
3853 static int cons_sign
= -1;
3856 x86_cons_fix_new (fragS
*frag
,
3861 enum bfd_reloc_code_real r
= reloc (len
, 0, cons_sign
, got_reloc
);
3863 got_reloc
= NO_RELOC
;
3866 if (exp
->X_op
== O_secrel
)
3868 exp
->X_op
= O_symbol
;
3869 r
= BFD_RELOC_32_SECREL
;
3873 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
3876 #if (!defined (OBJ_ELF) && !defined (OBJ_MAYBE_ELF)) || defined (LEX_AT)
3877 # define lex_got(reloc, adjust, types) NULL
3879 /* Parse operands of the form
3880 <symbol>@GOTOFF+<nnn>
3881 and similar .plt or .got references.
3883 If we find one, set up the correct relocation in RELOC and copy the
3884 input string, minus the `@GOTOFF' into a malloc'd buffer for
3885 parsing by the calling routine. Return this buffer, and if ADJUST
3886 is non-null set it to the length of the string we removed from the
3887 input line. Otherwise return NULL. */
3889 lex_got (enum bfd_reloc_code_real
*reloc
,
3891 unsigned int *types
)
3893 /* Some of the relocations depend on the size of what field is to
3894 be relocated. But in our callers i386_immediate and i386_displacement
3895 we don't yet know the operand size (this will be set by insn
3896 matching). Hence we record the word32 relocation here,
3897 and adjust the reloc according to the real size in reloc(). */
3898 static const struct {
3900 const enum bfd_reloc_code_real rel
[2];
3901 const unsigned int types64
;
3903 { "PLTOFF", { 0, BFD_RELOC_X86_64_PLTOFF64
}, Imm64
},
3904 { "PLT", { BFD_RELOC_386_PLT32
, BFD_RELOC_X86_64_PLT32
}, Imm32
|Imm32S
|Disp32
},
3905 { "GOTPLT", { 0, BFD_RELOC_X86_64_GOTPLT64
}, Imm64
|Disp64
},
3906 { "GOTOFF", { BFD_RELOC_386_GOTOFF
, BFD_RELOC_X86_64_GOTOFF64
}, Imm64
|Disp64
},
3907 { "GOTPCREL", { 0, BFD_RELOC_X86_64_GOTPCREL
}, Imm32
|Imm32S
|Disp32
},
3908 { "TLSGD", { BFD_RELOC_386_TLS_GD
, BFD_RELOC_X86_64_TLSGD
}, Imm32
|Imm32S
|Disp32
},
3909 { "TLSLDM", { BFD_RELOC_386_TLS_LDM
, 0 }, 0 },
3910 { "TLSLD", { 0, BFD_RELOC_X86_64_TLSLD
}, Imm32
|Imm32S
|Disp32
},
3911 { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32
, BFD_RELOC_X86_64_GOTTPOFF
}, Imm32
|Imm32S
|Disp32
},
3912 { "TPOFF", { BFD_RELOC_386_TLS_LE_32
, BFD_RELOC_X86_64_TPOFF32
}, Imm32
|Imm32S
|Imm64
|Disp32
|Disp64
},
3913 { "NTPOFF", { BFD_RELOC_386_TLS_LE
, 0 }, 0 },
3914 { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32
, BFD_RELOC_X86_64_DTPOFF32
}, Imm32
|Imm32S
|Imm64
|Disp32
|Disp64
},
3915 { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE
, 0 }, 0 },
3916 { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE
, 0 }, 0 },
3917 { "GOT", { BFD_RELOC_386_GOT32
, BFD_RELOC_X86_64_GOT32
}, Imm32
|Imm32S
|Disp32
|Imm64
},
3918 { "TLSDESC", { BFD_RELOC_386_TLS_GOTDESC
, BFD_RELOC_X86_64_GOTPC32_TLSDESC
}, Imm32
|Imm32S
|Disp32
},
3919 { "TLSCALL", { BFD_RELOC_386_TLS_DESC_CALL
, BFD_RELOC_X86_64_TLSDESC_CALL
}, Imm32
|Imm32S
|Disp32
}
3927 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
3928 if (is_end_of_line
[(unsigned char) *cp
])
3931 for (j
= 0; j
< sizeof (gotrel
) / sizeof (gotrel
[0]); j
++)
3935 len
= strlen (gotrel
[j
].str
);
3936 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
3938 if (gotrel
[j
].rel
[object_64bit
] != 0)
3941 char *tmpbuf
, *past_reloc
;
3943 *reloc
= gotrel
[j
].rel
[object_64bit
];
3949 if (flag_code
!= CODE_64BIT
)
3950 *types
= Imm32
|Disp32
;
3952 *types
= gotrel
[j
].types64
;
3955 if (GOT_symbol
== NULL
)
3956 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
3958 /* Replace the relocation token with ' ', so that
3959 errors like foo@GOTOFF1 will be detected. */
3961 /* The length of the first part of our input line. */
3962 first
= cp
- input_line_pointer
;
3964 /* The second part goes from after the reloc token until
3965 (and including) an end_of_line char. Don't use strlen
3966 here as the end_of_line char may not be a NUL. */
3967 past_reloc
= cp
+ 1 + len
;
3968 for (cp
= past_reloc
; !is_end_of_line
[(unsigned char) *cp
++]; )
3970 second
= cp
- past_reloc
;
3972 /* Allocate and copy string. The trailing NUL shouldn't
3973 be necessary, but be safe. */
3974 tmpbuf
= xmalloc (first
+ second
+ 2);
3975 memcpy (tmpbuf
, input_line_pointer
, first
);
3976 tmpbuf
[first
] = ' ';
3977 memcpy (tmpbuf
+ first
+ 1, past_reloc
, second
);
3978 tmpbuf
[first
+ second
+ 1] = '\0';
3982 as_bad (_("@%s reloc is not supported with %d-bit output format"),
3983 gotrel
[j
].str
, 1 << (5 + object_64bit
));
3988 /* Might be a symbol version string. Don't as_bad here. */
3993 x86_cons (exp
, size
)
3997 if (size
== 4 || (object_64bit
&& size
== 8))
3999 /* Handle @GOTOFF and the like in an expression. */
4001 char *gotfree_input_line
;
4004 save
= input_line_pointer
;
4005 gotfree_input_line
= lex_got (&got_reloc
, &adjust
, NULL
);
4006 if (gotfree_input_line
)
4007 input_line_pointer
= gotfree_input_line
;
4011 if (gotfree_input_line
)
4013 /* expression () has merrily parsed up to the end of line,
4014 or a comma - in the wrong buffer. Transfer how far
4015 input_line_pointer has moved to the right buffer. */
4016 input_line_pointer
= (save
4017 + (input_line_pointer
- gotfree_input_line
)
4019 free (gotfree_input_line
);
4027 static void signed_cons (int size
)
4029 if (flag_code
== CODE_64BIT
)
4037 pe_directive_secrel (dummy
)
4038 int dummy ATTRIBUTE_UNUSED
;
4045 if (exp
.X_op
== O_symbol
)
4046 exp
.X_op
= O_secrel
;
4048 emit_expr (&exp
, 4);
4050 while (*input_line_pointer
++ == ',');
4052 input_line_pointer
--;
4053 demand_empty_rest_of_line ();
4057 static int i386_immediate
PARAMS ((char *));
4060 i386_immediate (imm_start
)
4063 char *save_input_line_pointer
;
4064 char *gotfree_input_line
;
4067 unsigned int types
= ~0U;
4069 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
4071 as_bad (_("only 1 or 2 immediate operands are allowed"));
4075 exp
= &im_expressions
[i
.imm_operands
++];
4076 i
.op
[this_operand
].imms
= exp
;
4078 if (is_space_char (*imm_start
))
4081 save_input_line_pointer
= input_line_pointer
;
4082 input_line_pointer
= imm_start
;
4084 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
4085 if (gotfree_input_line
)
4086 input_line_pointer
= gotfree_input_line
;
4088 exp_seg
= expression (exp
);
4091 if (*input_line_pointer
)
4092 as_bad (_("junk `%s' after expression"), input_line_pointer
);
4094 input_line_pointer
= save_input_line_pointer
;
4095 if (gotfree_input_line
)
4096 free (gotfree_input_line
);
4098 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_big
)
4100 /* Missing or bad expr becomes absolute 0. */
4101 as_bad (_("missing or invalid immediate expression `%s' taken as 0"),
4103 exp
->X_op
= O_constant
;
4104 exp
->X_add_number
= 0;
4105 exp
->X_add_symbol
= (symbolS
*) 0;
4106 exp
->X_op_symbol
= (symbolS
*) 0;
4108 else if (exp
->X_op
== O_constant
)
4110 /* Size it properly later. */
4111 i
.types
[this_operand
] |= Imm64
;
4112 /* If BFD64, sign extend val. */
4113 if (!use_rela_relocations
)
4114 if ((exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
4115 exp
->X_add_number
= (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
4117 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
4118 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
4119 && exp_seg
!= absolute_section
4120 && exp_seg
!= text_section
4121 && exp_seg
!= data_section
4122 && exp_seg
!= bss_section
4123 && exp_seg
!= undefined_section
4124 && !bfd_is_com_section (exp_seg
))
4126 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
4132 /* This is an address. The size of the address will be
4133 determined later, depending on destination register,
4134 suffix, or the default for the section. */
4135 i
.types
[this_operand
] |= Imm8
| Imm16
| Imm32
| Imm32S
| Imm64
;
4136 i
.types
[this_operand
] &= types
;
4142 static char *i386_scale
PARAMS ((char *));
4149 char *save
= input_line_pointer
;
4151 input_line_pointer
= scale
;
4152 val
= get_absolute_expression ();
4157 i
.log2_scale_factor
= 0;
4160 i
.log2_scale_factor
= 1;
4163 i
.log2_scale_factor
= 2;
4166 i
.log2_scale_factor
= 3;
4170 char sep
= *input_line_pointer
;
4172 *input_line_pointer
= '\0';
4173 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
4175 *input_line_pointer
= sep
;
4176 input_line_pointer
= save
;
4180 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
4182 as_warn (_("scale factor of %d without an index register"),
4183 1 << i
.log2_scale_factor
);
4184 #if SCALE1_WHEN_NO_INDEX
4185 i
.log2_scale_factor
= 0;
4188 scale
= input_line_pointer
;
4189 input_line_pointer
= save
;
4193 static int i386_displacement
PARAMS ((char *, char *));
4196 i386_displacement (disp_start
, disp_end
)
4202 char *save_input_line_pointer
;
4203 char *gotfree_input_line
;
4204 int bigdisp
, override
;
4205 unsigned int types
= Disp
;
4207 if ((i
.types
[this_operand
] & JumpAbsolute
)
4208 || !(current_templates
->start
->opcode_modifier
& (Jump
| JumpDword
)))
4211 override
= (i
.prefix
[ADDR_PREFIX
] != 0);
4215 /* For PC-relative branches, the width of the displacement
4216 is dependent upon data size, not address size. */
4218 override
= (i
.prefix
[DATA_PREFIX
] != 0);
4220 if (flag_code
== CODE_64BIT
)
4223 bigdisp
= ((override
|| i
.suffix
== WORD_MNEM_SUFFIX
)
4225 : Disp32S
| Disp32
);
4227 bigdisp
= Disp64
| Disp32S
| Disp32
;
4234 override
= (i
.suffix
== (flag_code
!= CODE_16BIT
4236 : LONG_MNEM_SUFFIX
));
4239 if ((flag_code
== CODE_16BIT
) ^ override
)
4242 i
.types
[this_operand
] |= bigdisp
;
4244 exp
= &disp_expressions
[i
.disp_operands
];
4245 i
.op
[this_operand
].disps
= exp
;
4247 save_input_line_pointer
= input_line_pointer
;
4248 input_line_pointer
= disp_start
;
4249 END_STRING_AND_SAVE (disp_end
);
4251 #ifndef GCC_ASM_O_HACK
4252 #define GCC_ASM_O_HACK 0
4255 END_STRING_AND_SAVE (disp_end
+ 1);
4256 if ((i
.types
[this_operand
] & BaseIndex
) != 0
4257 && displacement_string_end
[-1] == '+')
4259 /* This hack is to avoid a warning when using the "o"
4260 constraint within gcc asm statements.
4263 #define _set_tssldt_desc(n,addr,limit,type) \
4264 __asm__ __volatile__ ( \
4266 "movw %w1,2+%0\n\t" \
4268 "movb %b1,4+%0\n\t" \
4269 "movb %4,5+%0\n\t" \
4270 "movb $0,6+%0\n\t" \
4271 "movb %h1,7+%0\n\t" \
4273 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
4275 This works great except that the output assembler ends
4276 up looking a bit weird if it turns out that there is
4277 no offset. You end up producing code that looks like:
4290 So here we provide the missing zero. */
4292 *displacement_string_end
= '0';
4295 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
4296 if (gotfree_input_line
)
4297 input_line_pointer
= gotfree_input_line
;
4299 exp_seg
= expression (exp
);
4302 if (*input_line_pointer
)
4303 as_bad (_("junk `%s' after expression"), input_line_pointer
);
4305 RESTORE_END_STRING (disp_end
+ 1);
4307 RESTORE_END_STRING (disp_end
);
4308 input_line_pointer
= save_input_line_pointer
;
4309 if (gotfree_input_line
)
4310 free (gotfree_input_line
);
4312 /* We do this to make sure that the section symbol is in
4313 the symbol table. We will ultimately change the relocation
4314 to be relative to the beginning of the section. */
4315 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
4316 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
4317 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
4319 if (exp
->X_op
!= O_symbol
)
4321 as_bad (_("bad expression used with @%s"),
4322 (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
4328 if (S_IS_LOCAL (exp
->X_add_symbol
)
4329 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
)
4330 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
4331 exp
->X_op
= O_subtract
;
4332 exp
->X_op_symbol
= GOT_symbol
;
4333 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
4334 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
4335 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
4336 i
.reloc
[this_operand
] = BFD_RELOC_64
;
4338 i
.reloc
[this_operand
] = BFD_RELOC_32
;
4341 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_big
)
4343 /* Missing or bad expr becomes absolute 0. */
4344 as_bad (_("missing or invalid displacement expression `%s' taken as 0"),
4346 exp
->X_op
= O_constant
;
4347 exp
->X_add_number
= 0;
4348 exp
->X_add_symbol
= (symbolS
*) 0;
4349 exp
->X_op_symbol
= (symbolS
*) 0;
4352 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
4353 if (exp
->X_op
!= O_constant
4354 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
4355 && exp_seg
!= absolute_section
4356 && exp_seg
!= text_section
4357 && exp_seg
!= data_section
4358 && exp_seg
!= bss_section
4359 && exp_seg
!= undefined_section
4360 && !bfd_is_com_section (exp_seg
))
4362 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
4367 if (!(i
.types
[this_operand
] & ~Disp
))
4368 i
.types
[this_operand
] &= types
;
4373 static int i386_index_check
PARAMS ((const char *));
4375 /* Make sure the memory operand we've been dealt is valid.
4376 Return 1 on success, 0 on a failure. */
4379 i386_index_check (operand_string
)
4380 const char *operand_string
;
4383 #if INFER_ADDR_PREFIX
4389 if ((current_templates
->start
->cpu_flags
& CpuSVME
)
4390 && current_templates
->end
[-1].operand_types
[0] == AnyMem
)
4392 /* Memory operands of SVME insns are special in that they only allow
4393 rAX as their memory address and ignore any segment override. */
4396 /* SKINIT is even more restrictive: it always requires EAX. */
4397 if (strcmp (current_templates
->start
->name
, "skinit") == 0)
4399 else if (flag_code
== CODE_64BIT
)
4400 RegXX
= i
.prefix
[ADDR_PREFIX
] == 0 ? Reg64
: Reg32
;
4402 RegXX
= ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[ADDR_PREFIX
] != 0)
4406 || !(i
.base_reg
->reg_type
& Acc
)
4407 || !(i
.base_reg
->reg_type
& RegXX
)
4409 || (i
.types
[0] & Disp
))
4412 else if (flag_code
== CODE_64BIT
)
4414 unsigned RegXX
= (i
.prefix
[ADDR_PREFIX
] == 0 ? Reg64
: Reg32
);
4417 && ((i
.base_reg
->reg_type
& RegXX
) == 0)
4418 && (i
.base_reg
->reg_type
!= BaseIndex
4421 && ((i
.index_reg
->reg_type
& (RegXX
| BaseIndex
))
4422 != (RegXX
| BaseIndex
))))
4427 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[ADDR_PREFIX
] != 0))
4431 && ((i
.base_reg
->reg_type
& (Reg16
| BaseIndex
| RegRex
))
4432 != (Reg16
| BaseIndex
)))
4434 && (((i
.index_reg
->reg_type
& (Reg16
| BaseIndex
))
4435 != (Reg16
| BaseIndex
))
4437 && i
.base_reg
->reg_num
< 6
4438 && i
.index_reg
->reg_num
>= 6
4439 && i
.log2_scale_factor
== 0))))
4446 && (i
.base_reg
->reg_type
& (Reg32
| RegRex
)) != Reg32
)
4448 && ((i
.index_reg
->reg_type
& (Reg32
| BaseIndex
| RegRex
))
4449 != (Reg32
| BaseIndex
))))
4455 #if INFER_ADDR_PREFIX
4456 if (i
.prefix
[ADDR_PREFIX
] == 0)
4458 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
4460 /* Change the size of any displacement too. At most one of
4461 Disp16 or Disp32 is set.
4462 FIXME. There doesn't seem to be any real need for separate
4463 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
4464 Removing them would probably clean up the code quite a lot. */
4465 if (flag_code
!= CODE_64BIT
&& (i
.types
[this_operand
] & (Disp16
| Disp32
)))
4466 i
.types
[this_operand
] ^= (Disp16
| Disp32
);
4471 as_bad (_("`%s' is not a valid base/index expression"),
4475 as_bad (_("`%s' is not a valid %s bit base/index expression"),
4477 flag_code_names
[flag_code
]);
4482 /* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero
4486 i386_operand (operand_string
)
4487 char *operand_string
;
4491 char *op_string
= operand_string
;
4493 if (is_space_char (*op_string
))
4496 /* We check for an absolute prefix (differentiating,
4497 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
4498 if (*op_string
== ABSOLUTE_PREFIX
)
4501 if (is_space_char (*op_string
))
4503 i
.types
[this_operand
] |= JumpAbsolute
;
4506 /* Check if operand is a register. */
4507 if ((r
= parse_register (op_string
, &end_op
)) != NULL
)
4509 /* Check for a segment override by searching for ':' after a
4510 segment register. */
4512 if (is_space_char (*op_string
))
4514 if (*op_string
== ':' && (r
->reg_type
& (SReg2
| SReg3
)))
4519 i
.seg
[i
.mem_operands
] = &es
;
4522 i
.seg
[i
.mem_operands
] = &cs
;
4525 i
.seg
[i
.mem_operands
] = &ss
;
4528 i
.seg
[i
.mem_operands
] = &ds
;
4531 i
.seg
[i
.mem_operands
] = &fs
;
4534 i
.seg
[i
.mem_operands
] = &gs
;
4538 /* Skip the ':' and whitespace. */
4540 if (is_space_char (*op_string
))
4543 if (!is_digit_char (*op_string
)
4544 && !is_identifier_char (*op_string
)
4545 && *op_string
!= '('
4546 && *op_string
!= ABSOLUTE_PREFIX
)
4548 as_bad (_("bad memory operand `%s'"), op_string
);
4551 /* Handle case of %es:*foo. */
4552 if (*op_string
== ABSOLUTE_PREFIX
)
4555 if (is_space_char (*op_string
))
4557 i
.types
[this_operand
] |= JumpAbsolute
;
4559 goto do_memory_reference
;
4563 as_bad (_("junk `%s' after register"), op_string
);
4566 i
.types
[this_operand
] |= r
->reg_type
& ~BaseIndex
;
4567 i
.op
[this_operand
].regs
= r
;
4570 else if (*op_string
== REGISTER_PREFIX
)
4572 as_bad (_("bad register name `%s'"), op_string
);
4575 else if (*op_string
== IMMEDIATE_PREFIX
)
4578 if (i
.types
[this_operand
] & JumpAbsolute
)
4580 as_bad (_("immediate operand illegal with absolute jump"));
4583 if (!i386_immediate (op_string
))
4586 else if (is_digit_char (*op_string
)
4587 || is_identifier_char (*op_string
)
4588 || *op_string
== '(')
4590 /* This is a memory reference of some sort. */
4593 /* Start and end of displacement string expression (if found). */
4594 char *displacement_string_start
;
4595 char *displacement_string_end
;
4597 do_memory_reference
:
4598 if ((i
.mem_operands
== 1
4599 && (current_templates
->start
->opcode_modifier
& IsString
) == 0)
4600 || i
.mem_operands
== 2)
4602 as_bad (_("too many memory references for `%s'"),
4603 current_templates
->start
->name
);
4607 /* Check for base index form. We detect the base index form by
4608 looking for an ')' at the end of the operand, searching
4609 for the '(' matching it, and finding a REGISTER_PREFIX or ','
4611 base_string
= op_string
+ strlen (op_string
);
4614 if (is_space_char (*base_string
))
4617 /* If we only have a displacement, set-up for it to be parsed later. */
4618 displacement_string_start
= op_string
;
4619 displacement_string_end
= base_string
+ 1;
4621 if (*base_string
== ')')
4624 unsigned int parens_balanced
= 1;
4625 /* We've already checked that the number of left & right ()'s are
4626 equal, so this loop will not be infinite. */
4630 if (*base_string
== ')')
4632 if (*base_string
== '(')
4635 while (parens_balanced
);
4637 temp_string
= base_string
;
4639 /* Skip past '(' and whitespace. */
4641 if (is_space_char (*base_string
))
4644 if (*base_string
== ','
4645 || ((i
.base_reg
= parse_register (base_string
, &end_op
)) != NULL
))
4647 displacement_string_end
= temp_string
;
4649 i
.types
[this_operand
] |= BaseIndex
;
4653 base_string
= end_op
;
4654 if (is_space_char (*base_string
))
4658 /* There may be an index reg or scale factor here. */
4659 if (*base_string
== ',')
4662 if (is_space_char (*base_string
))
4665 if ((i
.index_reg
= parse_register (base_string
, &end_op
)) != NULL
)
4667 base_string
= end_op
;
4668 if (is_space_char (*base_string
))
4670 if (*base_string
== ',')
4673 if (is_space_char (*base_string
))
4676 else if (*base_string
!= ')')
4678 as_bad (_("expecting `,' or `)' after index register in `%s'"),
4683 else if (*base_string
== REGISTER_PREFIX
)
4685 as_bad (_("bad register name `%s'"), base_string
);
4689 /* Check for scale factor. */
4690 if (*base_string
!= ')')
4692 char *end_scale
= i386_scale (base_string
);
4697 base_string
= end_scale
;
4698 if (is_space_char (*base_string
))
4700 if (*base_string
!= ')')
4702 as_bad (_("expecting `)' after scale factor in `%s'"),
4707 else if (!i
.index_reg
)
4709 as_bad (_("expecting index register or scale factor after `,'; got '%c'"),
4714 else if (*base_string
!= ')')
4716 as_bad (_("expecting `,' or `)' after base register in `%s'"),
4721 else if (*base_string
== REGISTER_PREFIX
)
4723 as_bad (_("bad register name `%s'"), base_string
);
4728 /* If there's an expression beginning the operand, parse it,
4729 assuming displacement_string_start and
4730 displacement_string_end are meaningful. */
4731 if (displacement_string_start
!= displacement_string_end
)
4733 if (!i386_displacement (displacement_string_start
,
4734 displacement_string_end
))
4738 /* Special case for (%dx) while doing input/output op. */
4740 && i
.base_reg
->reg_type
== (Reg16
| InOutPortReg
)
4742 && i
.log2_scale_factor
== 0
4743 && i
.seg
[i
.mem_operands
] == 0
4744 && (i
.types
[this_operand
] & Disp
) == 0)
4746 i
.types
[this_operand
] = InOutPortReg
;
4750 if (i386_index_check (operand_string
) == 0)
4756 /* It's not a memory operand; argh! */
4757 as_bad (_("invalid char %s beginning operand %d `%s'"),
4758 output_invalid (*op_string
),
4763 return 1; /* Normal return. */
4766 /* md_estimate_size_before_relax()
4768 Called just before relax() for rs_machine_dependent frags. The x86
4769 assembler uses these frags to handle variable size jump
4772 Any symbol that is now undefined will not become defined.
4773 Return the correct fr_subtype in the frag.
4774 Return the initial "guess for variable size of frag" to caller.
4775 The guess is actually the growth beyond the fixed part. Whatever
4776 we do to grow the fixed or variable part contributes to our
4780 md_estimate_size_before_relax (fragP
, segment
)
4784 /* We've already got fragP->fr_subtype right; all we have to do is
4785 check for un-relaxable symbols. On an ELF system, we can't relax
4786 an externally visible symbol, because it may be overridden by a
4788 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
4789 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4791 && (S_IS_EXTERNAL (fragP
->fr_symbol
)
4792 || S_IS_WEAK (fragP
->fr_symbol
)))
4796 /* Symbol is undefined in this segment, or we need to keep a
4797 reloc so that weak symbols can be overridden. */
4798 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
4799 enum bfd_reloc_code_real reloc_type
;
4800 unsigned char *opcode
;
4803 if (fragP
->fr_var
!= NO_RELOC
)
4804 reloc_type
= fragP
->fr_var
;
4806 reloc_type
= BFD_RELOC_16_PCREL
;
4808 reloc_type
= BFD_RELOC_32_PCREL
;
4810 old_fr_fix
= fragP
->fr_fix
;
4811 opcode
= (unsigned char *) fragP
->fr_opcode
;
4813 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
4816 /* Make jmp (0xeb) a (d)word displacement jump. */
4818 fragP
->fr_fix
+= size
;
4819 fix_new (fragP
, old_fr_fix
, size
,
4821 fragP
->fr_offset
, 1,
4827 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
4829 /* Negate the condition, and branch past an
4830 unconditional jump. */
4833 /* Insert an unconditional jump. */
4835 /* We added two extra opcode bytes, and have a two byte
4837 fragP
->fr_fix
+= 2 + 2;
4838 fix_new (fragP
, old_fr_fix
+ 2, 2,
4840 fragP
->fr_offset
, 1,
4847 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
4852 fixP
= fix_new (fragP
, old_fr_fix
, 1,
4854 fragP
->fr_offset
, 1,
4856 fixP
->fx_signed
= 1;
4860 /* This changes the byte-displacement jump 0x7N
4861 to the (d)word-displacement jump 0x0f,0x8N. */
4862 opcode
[1] = opcode
[0] + 0x10;
4863 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
4864 /* We've added an opcode byte. */
4865 fragP
->fr_fix
+= 1 + size
;
4866 fix_new (fragP
, old_fr_fix
+ 1, size
,
4868 fragP
->fr_offset
, 1,
4873 BAD_CASE (fragP
->fr_subtype
);
4877 return fragP
->fr_fix
- old_fr_fix
;
4880 /* Guess size depending on current relax state. Initially the relax
4881 state will correspond to a short jump and we return 1, because
4882 the variable part of the frag (the branch offset) is one byte
4883 long. However, we can relax a section more than once and in that
4884 case we must either set fr_subtype back to the unrelaxed state,
4885 or return the value for the appropriate branch. */
4886 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
4889 /* Called after relax() is finished.
4891 In: Address of frag.
4892 fr_type == rs_machine_dependent.
4893 fr_subtype is what the address relaxed to.
4895 Out: Any fixSs and constants are set up.
4896 Caller will turn frag into a ".space 0". */
4899 md_convert_frag (abfd
, sec
, fragP
)
4900 bfd
*abfd ATTRIBUTE_UNUSED
;
4901 segT sec ATTRIBUTE_UNUSED
;
4904 unsigned char *opcode
;
4905 unsigned char *where_to_put_displacement
= NULL
;
4906 offsetT target_address
;
4907 offsetT opcode_address
;
4908 unsigned int extension
= 0;
4909 offsetT displacement_from_opcode_start
;
4911 opcode
= (unsigned char *) fragP
->fr_opcode
;
4913 /* Address we want to reach in file space. */
4914 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
4916 /* Address opcode resides at in file space. */
4917 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
4919 /* Displacement from opcode start to fill into instruction. */
4920 displacement_from_opcode_start
= target_address
- opcode_address
;
4922 if ((fragP
->fr_subtype
& BIG
) == 0)
4924 /* Don't have to change opcode. */
4925 extension
= 1; /* 1 opcode + 1 displacement */
4926 where_to_put_displacement
= &opcode
[1];
4930 if (no_cond_jump_promotion
4931 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
4932 as_warn_where (fragP
->fr_file
, fragP
->fr_line
, _("long jump required"));
4934 switch (fragP
->fr_subtype
)
4936 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
4937 extension
= 4; /* 1 opcode + 4 displacement */
4939 where_to_put_displacement
= &opcode
[1];
4942 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
4943 extension
= 2; /* 1 opcode + 2 displacement */
4945 where_to_put_displacement
= &opcode
[1];
4948 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
4949 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
4950 extension
= 5; /* 2 opcode + 4 displacement */
4951 opcode
[1] = opcode
[0] + 0x10;
4952 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
4953 where_to_put_displacement
= &opcode
[2];
4956 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
4957 extension
= 3; /* 2 opcode + 2 displacement */
4958 opcode
[1] = opcode
[0] + 0x10;
4959 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
4960 where_to_put_displacement
= &opcode
[2];
4963 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
4968 where_to_put_displacement
= &opcode
[3];
4972 BAD_CASE (fragP
->fr_subtype
);
4977 /* If size if less then four we are sure that the operand fits,
4978 but if it's 4, then it could be that the displacement is larger
4980 if (DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
) == 4
4982 && ((addressT
) (displacement_from_opcode_start
- extension
4983 + ((addressT
) 1 << 31))
4984 > (((addressT
) 2 << 31) - 1)))
4986 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
4987 _("jump target out of range"));
4988 /* Make us emit 0. */
4989 displacement_from_opcode_start
= extension
;
4991 /* Now put displacement after opcode. */
4992 md_number_to_chars ((char *) where_to_put_displacement
,
4993 (valueT
) (displacement_from_opcode_start
- extension
),
4994 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
4995 fragP
->fr_fix
+= extension
;
4998 /* Size of byte displacement jmp. */
4999 int md_short_jump_size
= 2;
5001 /* Size of dword displacement jmp. */
5002 int md_long_jump_size
= 5;
5005 md_create_short_jump (ptr
, from_addr
, to_addr
, frag
, to_symbol
)
5007 addressT from_addr
, to_addr
;
5008 fragS
*frag ATTRIBUTE_UNUSED
;
5009 symbolS
*to_symbol ATTRIBUTE_UNUSED
;
5013 offset
= to_addr
- (from_addr
+ 2);
5014 /* Opcode for byte-disp jump. */
5015 md_number_to_chars (ptr
, (valueT
) 0xeb, 1);
5016 md_number_to_chars (ptr
+ 1, (valueT
) offset
, 1);
5020 md_create_long_jump (ptr
, from_addr
, to_addr
, frag
, to_symbol
)
5022 addressT from_addr
, to_addr
;
5023 fragS
*frag ATTRIBUTE_UNUSED
;
5024 symbolS
*to_symbol ATTRIBUTE_UNUSED
;
5028 offset
= to_addr
- (from_addr
+ 5);
5029 md_number_to_chars (ptr
, (valueT
) 0xe9, 1);
5030 md_number_to_chars (ptr
+ 1, (valueT
) offset
, 4);
5033 /* Apply a fixup (fixS) to segment data, once it has been determined
5034 by our caller that we have all the info we need to fix it up.
5036 On the 386, immediates, displacements, and data pointers are all in
5037 the same (little-endian) format, so we don't need to care about which
5041 md_apply_fix (fixP
, valP
, seg
)
5042 /* The fix we're to put in. */
5044 /* Pointer to the value of the bits. */
5046 /* Segment fix is from. */
5047 segT seg ATTRIBUTE_UNUSED
;
5049 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
5050 valueT value
= *valP
;
5052 #if !defined (TE_Mach)
5055 switch (fixP
->fx_r_type
)
5061 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
5064 case BFD_RELOC_X86_64_32S
:
5065 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
5068 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
5071 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
5076 if (fixP
->fx_addsy
!= NULL
5077 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
5078 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
5079 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
5080 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
5081 && !use_rela_relocations
)
5083 /* This is a hack. There should be a better way to handle this.
5084 This covers for the fact that bfd_install_relocation will
5085 subtract the current location (for partial_inplace, PC relative
5086 relocations); see more below. */
5090 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
5093 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
5095 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5098 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
5101 || (symbol_section_p (fixP
->fx_addsy
)
5102 && sym_seg
!= absolute_section
))
5103 && !generic_force_reloc (fixP
))
5105 /* Yes, we add the values in twice. This is because
5106 bfd_install_relocation subtracts them out again. I think
5107 bfd_install_relocation is broken, but I don't dare change
5109 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
5113 #if defined (OBJ_COFF) && defined (TE_PE)
5114 /* For some reason, the PE format does not store a
5115 section address offset for a PC relative symbol. */
5116 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
5117 || S_IS_WEAK (fixP
->fx_addsy
))
5118 value
+= md_pcrel_from (fixP
);
5122 /* Fix a few things - the dynamic linker expects certain values here,
5123 and we must not disappoint it. */
5124 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5125 if (IS_ELF
&& fixP
->fx_addsy
)
5126 switch (fixP
->fx_r_type
)
5128 case BFD_RELOC_386_PLT32
:
5129 case BFD_RELOC_X86_64_PLT32
:
5130 /* Make the jump instruction point to the address of the operand. At
5131 runtime we merely add the offset to the actual PLT entry. */
5135 case BFD_RELOC_386_TLS_GD
:
5136 case BFD_RELOC_386_TLS_LDM
:
5137 case BFD_RELOC_386_TLS_IE_32
:
5138 case BFD_RELOC_386_TLS_IE
:
5139 case BFD_RELOC_386_TLS_GOTIE
:
5140 case BFD_RELOC_386_TLS_GOTDESC
:
5141 case BFD_RELOC_X86_64_TLSGD
:
5142 case BFD_RELOC_X86_64_TLSLD
:
5143 case BFD_RELOC_X86_64_GOTTPOFF
:
5144 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
5145 value
= 0; /* Fully resolved at runtime. No addend. */
5147 case BFD_RELOC_386_TLS_LE
:
5148 case BFD_RELOC_386_TLS_LDO_32
:
5149 case BFD_RELOC_386_TLS_LE_32
:
5150 case BFD_RELOC_X86_64_DTPOFF32
:
5151 case BFD_RELOC_X86_64_DTPOFF64
:
5152 case BFD_RELOC_X86_64_TPOFF32
:
5153 case BFD_RELOC_X86_64_TPOFF64
:
5154 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
5157 case BFD_RELOC_386_TLS_DESC_CALL
:
5158 case BFD_RELOC_X86_64_TLSDESC_CALL
:
5159 value
= 0; /* Fully resolved at runtime. No addend. */
5160 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
5164 case BFD_RELOC_386_GOT32
:
5165 case BFD_RELOC_X86_64_GOT32
:
5166 value
= 0; /* Fully resolved at runtime. No addend. */
5169 case BFD_RELOC_VTABLE_INHERIT
:
5170 case BFD_RELOC_VTABLE_ENTRY
:
5177 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
5179 #endif /* !defined (TE_Mach) */
5181 /* Are we finished with this relocation now? */
5182 if (fixP
->fx_addsy
== NULL
)
5184 else if (use_rela_relocations
)
5186 fixP
->fx_no_overflow
= 1;
5187 /* Remember value for tc_gen_reloc. */
5188 fixP
->fx_addnumber
= value
;
5192 md_number_to_chars (p
, value
, fixP
->fx_size
);
5195 #define MAX_LITTLENUMS 6
5197 /* Turn the string pointed to by litP into a floating point constant
5198 of type TYPE, and emit the appropriate bytes. The number of
5199 LITTLENUMS emitted is stored in *SIZEP. An error message is
5200 returned, or NULL on OK. */
5203 md_atof (type
, litP
, sizeP
)
5209 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
5210 LITTLENUM_TYPE
*wordP
;
5232 return _("Bad call to md_atof ()");
5234 t
= atof_ieee (input_line_pointer
, type
, words
);
5236 input_line_pointer
= t
;
5238 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
5239 /* This loops outputs the LITTLENUMs in REVERSE order; in accord with
5240 the bigendian 386. */
5241 for (wordP
= words
+ prec
- 1; prec
--;)
5243 md_number_to_chars (litP
, (valueT
) (*wordP
--), sizeof (LITTLENUM_TYPE
));
5244 litP
+= sizeof (LITTLENUM_TYPE
);
5249 static char output_invalid_buf
[8];
5256 sprintf (output_invalid_buf
, "'%c'", c
);
5258 sprintf (output_invalid_buf
, "(0x%x)", (unsigned) c
);
5259 return output_invalid_buf
;
5262 /* REG_STRING starts *before* REGISTER_PREFIX. */
5264 static const reg_entry
*
5265 parse_real_register (char *reg_string
, char **end_op
)
5267 char *s
= reg_string
;
5269 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
5272 /* Skip possible REGISTER_PREFIX and possible whitespace. */
5273 if (*s
== REGISTER_PREFIX
)
5276 if (is_space_char (*s
))
5280 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
5282 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
5283 return (const reg_entry
*) NULL
;
5287 /* For naked regs, make sure that we are not dealing with an identifier.
5288 This prevents confusing an identifier like `eax_var' with register
5290 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
5291 return (const reg_entry
*) NULL
;
5295 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
5297 /* Handle floating point regs, allowing spaces in the (i) part. */
5298 if (r
== i386_regtab
/* %st is first entry of table */)
5300 if (is_space_char (*s
))
5305 if (is_space_char (*s
))
5307 if (*s
>= '0' && *s
<= '7')
5309 r
= &i386_float_regtab
[*s
- '0'];
5311 if (is_space_char (*s
))
5319 /* We have "%st(" then garbage. */
5320 return (const reg_entry
*) NULL
;
5325 && ((r
->reg_flags
& (RegRex64
| RegRex
)) | (r
->reg_type
& Reg64
)) != 0
5326 && (r
->reg_type
!= Control
|| !(cpu_arch_flags
& CpuSledgehammer
))
5327 && flag_code
!= CODE_64BIT
)
5328 return (const reg_entry
*) NULL
;
5333 /* REG_STRING starts *before* REGISTER_PREFIX. */
5335 static const reg_entry
*
5336 parse_register (char *reg_string
, char **end_op
)
5340 if (*reg_string
== REGISTER_PREFIX
|| allow_naked_reg
)
5341 r
= parse_real_register (reg_string
, end_op
);
5346 char *save
= input_line_pointer
;
5350 input_line_pointer
= reg_string
;
5351 c
= get_symbol_end ();
5352 symbolP
= symbol_find (reg_string
);
5353 if (symbolP
&& S_GET_SEGMENT (symbolP
) == reg_section
)
5355 const expressionS
*e
= symbol_get_value_expression (symbolP
);
5357 know (e
->X_op
== O_register
);
5358 know (e
->X_add_number
>= 0 && (valueT
) e
->X_add_number
< ARRAY_SIZE (i386_regtab
));
5359 r
= i386_regtab
+ e
->X_add_number
;
5360 *end_op
= input_line_pointer
;
5362 *input_line_pointer
= c
;
5363 input_line_pointer
= save
;
5369 i386_parse_name (char *name
, expressionS
*e
, char *nextcharP
)
5372 char *end
= input_line_pointer
;
5375 r
= parse_register (name
, &input_line_pointer
);
5376 if (r
&& end
<= input_line_pointer
)
5378 *nextcharP
= *input_line_pointer
;
5379 *input_line_pointer
= 0;
5380 e
->X_op
= O_register
;
5381 e
->X_add_number
= r
- i386_regtab
;
5384 input_line_pointer
= end
;
5390 md_operand (expressionS
*e
)
5392 if (*input_line_pointer
== REGISTER_PREFIX
)
5395 const reg_entry
*r
= parse_real_register (input_line_pointer
, &end
);
5399 e
->X_op
= O_register
;
5400 e
->X_add_number
= r
- i386_regtab
;
5401 input_line_pointer
= end
;
5407 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5408 const char *md_shortopts
= "kVQ:sqn";
5410 const char *md_shortopts
= "qn";
5413 #define OPTION_32 (OPTION_MD_BASE + 0)
5414 #define OPTION_64 (OPTION_MD_BASE + 1)
5415 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
5417 struct option md_longopts
[] = {
5418 {"32", no_argument
, NULL
, OPTION_32
},
5419 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5420 {"64", no_argument
, NULL
, OPTION_64
},
5422 {"divide", no_argument
, NULL
, OPTION_DIVIDE
},
5423 {NULL
, no_argument
, NULL
, 0}
5425 size_t md_longopts_size
= sizeof (md_longopts
);
5428 md_parse_option (c
, arg
)
5430 char *arg ATTRIBUTE_UNUSED
;
5435 optimize_align_code
= 0;
5442 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5443 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
5444 should be emitted or not. FIXME: Not implemented. */
5448 /* -V: SVR4 argument to print version ID. */
5450 print_version_id ();
5453 /* -k: Ignore for FreeBSD compatibility. */
5458 /* -s: On i386 Solaris, this tells the native assembler to use
5459 .stab instead of .stab.excl. We always use .stab anyhow. */
5464 const char **list
, **l
;
5466 list
= bfd_target_list ();
5467 for (l
= list
; *l
!= NULL
; l
++)
5468 if (strcmp (*l
, "elf64-x86-64") == 0)
5470 default_arch
= "x86_64";
5474 as_fatal (_("No compiled in support for x86_64"));
5481 default_arch
= "i386";
5485 #ifdef SVR4_COMMENT_CHARS
5490 n
= (char *) xmalloc (strlen (i386_comment_chars
) + 1);
5492 for (s
= i386_comment_chars
; *s
!= '\0'; s
++)
5496 i386_comment_chars
= n
;
5508 md_show_usage (stream
)
5511 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5512 fprintf (stream
, _("\
5514 -V print assembler version number\n\
5517 fprintf (stream
, _("\
5518 -n Do not optimize code alignment\n\
5519 -q quieten some warnings\n"));
5520 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5521 fprintf (stream
, _("\
5524 #ifdef SVR4_COMMENT_CHARS
5525 fprintf (stream
, _("\
5526 --divide do not treat `/' as a comment character\n"));
5528 fprintf (stream
, _("\
5529 --divide ignored\n"));
5533 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
5534 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
5536 /* Pick the target format to use. */
5539 i386_target_format ()
5541 if (!strcmp (default_arch
, "x86_64"))
5542 set_code_flag (CODE_64BIT
);
5543 else if (!strcmp (default_arch
, "i386"))
5544 set_code_flag (CODE_32BIT
);
5546 as_fatal (_("Unknown architecture"));
5547 switch (OUTPUT_FLAVOR
)
5549 #ifdef OBJ_MAYBE_AOUT
5550 case bfd_target_aout_flavour
:
5551 return AOUT_TARGET_FORMAT
;
5553 #ifdef OBJ_MAYBE_COFF
5554 case bfd_target_coff_flavour
:
5557 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
5558 case bfd_target_elf_flavour
:
5560 if (flag_code
== CODE_64BIT
)
5563 use_rela_relocations
= 1;
5565 return flag_code
== CODE_64BIT
? "elf64-x86-64" : ELF_TARGET_FORMAT
;
5574 #endif /* OBJ_MAYBE_ more than one */
5576 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
5577 void i386_elf_emit_arch_note ()
5579 if (IS_ELF
&& cpu_arch_name
!= NULL
)
5582 asection
*seg
= now_seg
;
5583 subsegT subseg
= now_subseg
;
5584 Elf_Internal_Note i_note
;
5585 Elf_External_Note e_note
;
5586 asection
*note_secp
;
5589 /* Create the .note section. */
5590 note_secp
= subseg_new (".note", 0);
5591 bfd_set_section_flags (stdoutput
,
5593 SEC_HAS_CONTENTS
| SEC_READONLY
);
5595 /* Process the arch string. */
5596 len
= strlen (cpu_arch_name
);
5598 i_note
.namesz
= len
+ 1;
5600 i_note
.type
= NT_ARCH
;
5601 p
= frag_more (sizeof (e_note
.namesz
));
5602 md_number_to_chars (p
, (valueT
) i_note
.namesz
, sizeof (e_note
.namesz
));
5603 p
= frag_more (sizeof (e_note
.descsz
));
5604 md_number_to_chars (p
, (valueT
) i_note
.descsz
, sizeof (e_note
.descsz
));
5605 p
= frag_more (sizeof (e_note
.type
));
5606 md_number_to_chars (p
, (valueT
) i_note
.type
, sizeof (e_note
.type
));
5607 p
= frag_more (len
+ 1);
5608 strcpy (p
, cpu_arch_name
);
5610 frag_align (2, 0, 0);
5612 subseg_set (seg
, subseg
);
5618 md_undefined_symbol (name
)
5621 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
5622 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
5623 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
5624 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
5628 if (symbol_find (name
))
5629 as_bad (_("GOT already in symbol table"));
5630 GOT_symbol
= symbol_new (name
, undefined_section
,
5631 (valueT
) 0, &zero_address_frag
);
5638 /* Round up a section size to the appropriate boundary. */
5641 md_section_align (segment
, size
)
5642 segT segment ATTRIBUTE_UNUSED
;
5645 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
5646 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
5648 /* For a.out, force the section size to be aligned. If we don't do
5649 this, BFD will align it for us, but it will not write out the
5650 final bytes of the section. This may be a bug in BFD, but it is
5651 easier to fix it here since that is how the other a.out targets
5655 align
= bfd_get_section_alignment (stdoutput
, segment
);
5656 size
= ((size
+ (1 << align
) - 1) & ((valueT
) -1 << align
));
5663 /* On the i386, PC-relative offsets are relative to the start of the
5664 next instruction. That is, the address of the offset, plus its
5665 size, since the offset is always the last part of the insn. */
5668 md_pcrel_from (fixP
)
5671 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
5678 int ignore ATTRIBUTE_UNUSED
;
5682 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5684 obj_elf_section_change_hook ();
5686 temp
= get_absolute_expression ();
5687 subseg_set (bss_section
, (subsegT
) temp
);
5688 demand_empty_rest_of_line ();
5694 i386_validate_fix (fixp
)
5697 if (fixp
->fx_subsy
&& fixp
->fx_subsy
== GOT_symbol
)
5699 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
5703 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
5708 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
5710 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
5717 tc_gen_reloc (section
, fixp
)
5718 asection
*section ATTRIBUTE_UNUSED
;
5722 bfd_reloc_code_real_type code
;
5724 switch (fixp
->fx_r_type
)
5726 case BFD_RELOC_X86_64_PLT32
:
5727 case BFD_RELOC_X86_64_GOT32
:
5728 case BFD_RELOC_X86_64_GOTPCREL
:
5729 case BFD_RELOC_386_PLT32
:
5730 case BFD_RELOC_386_GOT32
:
5731 case BFD_RELOC_386_GOTOFF
:
5732 case BFD_RELOC_386_GOTPC
:
5733 case BFD_RELOC_386_TLS_GD
:
5734 case BFD_RELOC_386_TLS_LDM
:
5735 case BFD_RELOC_386_TLS_LDO_32
:
5736 case BFD_RELOC_386_TLS_IE_32
:
5737 case BFD_RELOC_386_TLS_IE
:
5738 case BFD_RELOC_386_TLS_GOTIE
:
5739 case BFD_RELOC_386_TLS_LE_32
:
5740 case BFD_RELOC_386_TLS_LE
:
5741 case BFD_RELOC_386_TLS_GOTDESC
:
5742 case BFD_RELOC_386_TLS_DESC_CALL
:
5743 case BFD_RELOC_X86_64_TLSGD
:
5744 case BFD_RELOC_X86_64_TLSLD
:
5745 case BFD_RELOC_X86_64_DTPOFF32
:
5746 case BFD_RELOC_X86_64_DTPOFF64
:
5747 case BFD_RELOC_X86_64_GOTTPOFF
:
5748 case BFD_RELOC_X86_64_TPOFF32
:
5749 case BFD_RELOC_X86_64_TPOFF64
:
5750 case BFD_RELOC_X86_64_GOTOFF64
:
5751 case BFD_RELOC_X86_64_GOTPC32
:
5752 case BFD_RELOC_X86_64_GOT64
:
5753 case BFD_RELOC_X86_64_GOTPCREL64
:
5754 case BFD_RELOC_X86_64_GOTPC64
:
5755 case BFD_RELOC_X86_64_GOTPLT64
:
5756 case BFD_RELOC_X86_64_PLTOFF64
:
5757 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
5758 case BFD_RELOC_X86_64_TLSDESC_CALL
:
5760 case BFD_RELOC_VTABLE_ENTRY
:
5761 case BFD_RELOC_VTABLE_INHERIT
:
5763 case BFD_RELOC_32_SECREL
:
5765 code
= fixp
->fx_r_type
;
5767 case BFD_RELOC_X86_64_32S
:
5768 if (!fixp
->fx_pcrel
)
5770 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
5771 code
= fixp
->fx_r_type
;
5777 switch (fixp
->fx_size
)
5780 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
5781 _("can not do %d byte pc-relative relocation"),
5783 code
= BFD_RELOC_32_PCREL
;
5785 case 1: code
= BFD_RELOC_8_PCREL
; break;
5786 case 2: code
= BFD_RELOC_16_PCREL
; break;
5787 case 4: code
= BFD_RELOC_32_PCREL
; break;
5789 case 8: code
= BFD_RELOC_64_PCREL
; break;
5795 switch (fixp
->fx_size
)
5798 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
5799 _("can not do %d byte relocation"),
5801 code
= BFD_RELOC_32
;
5803 case 1: code
= BFD_RELOC_8
; break;
5804 case 2: code
= BFD_RELOC_16
; break;
5805 case 4: code
= BFD_RELOC_32
; break;
5807 case 8: code
= BFD_RELOC_64
; break;
5814 if ((code
== BFD_RELOC_32
5815 || code
== BFD_RELOC_32_PCREL
5816 || code
== BFD_RELOC_X86_64_32S
)
5818 && fixp
->fx_addsy
== GOT_symbol
)
5821 code
= BFD_RELOC_386_GOTPC
;
5823 code
= BFD_RELOC_X86_64_GOTPC32
;
5825 if ((code
== BFD_RELOC_64
|| code
== BFD_RELOC_64_PCREL
)
5827 && fixp
->fx_addsy
== GOT_symbol
)
5829 code
= BFD_RELOC_X86_64_GOTPC64
;
5832 rel
= (arelent
*) xmalloc (sizeof (arelent
));
5833 rel
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
5834 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
5836 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
5838 if (!use_rela_relocations
)
5840 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
5841 vtable entry to be used in the relocation's section offset. */
5842 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
5843 rel
->address
= fixp
->fx_offset
;
5847 /* Use the rela in 64bit mode. */
5850 if (!fixp
->fx_pcrel
)
5851 rel
->addend
= fixp
->fx_offset
;
5855 case BFD_RELOC_X86_64_PLT32
:
5856 case BFD_RELOC_X86_64_GOT32
:
5857 case BFD_RELOC_X86_64_GOTPCREL
:
5858 case BFD_RELOC_X86_64_TLSGD
:
5859 case BFD_RELOC_X86_64_TLSLD
:
5860 case BFD_RELOC_X86_64_GOTTPOFF
:
5861 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
5862 case BFD_RELOC_X86_64_TLSDESC_CALL
:
5863 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
5866 rel
->addend
= (section
->vma
5868 + fixp
->fx_addnumber
5869 + md_pcrel_from (fixp
));
5874 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
5875 if (rel
->howto
== NULL
)
5877 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
5878 _("cannot represent relocation type %s"),
5879 bfd_get_reloc_code_name (code
));
5880 /* Set howto to a garbage value so that we can keep going. */
5881 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
5882 assert (rel
->howto
!= NULL
);
5889 /* Parse operands using Intel syntax. This implements a recursive descent
5890 parser based on the BNF grammar published in Appendix B of the MASM 6.1
5893 FIXME: We do not recognize the full operand grammar defined in the MASM
5894 documentation. In particular, all the structure/union and
5895 high-level macro operands are missing.
5897 Uppercase words are terminals, lower case words are non-terminals.
5898 Objects surrounded by double brackets '[[' ']]' are optional. Vertical
5899 bars '|' denote choices. Most grammar productions are implemented in
5900 functions called 'intel_<production>'.
5902 Initial production is 'expr'.
5908 binOp & | AND | \| | OR | ^ | XOR
5910 byteRegister AL | AH | BL | BH | CL | CH | DL | DH
5912 constant digits [[ radixOverride ]]
5914 dataType BYTE | WORD | DWORD | FWORD | QWORD | TBYTE | OWORD | XMMWORD
5952 => expr expr cmpOp e04
5955 gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX
5956 | BP | EBP | SP | ESP | DI | EDI | SI | ESI
5958 hexdigit a | b | c | d | e | f
5959 | A | B | C | D | E | F
5965 mulOp * | / | % | MOD | << | SHL | >> | SHR
5969 register specialRegister
5973 segmentRegister CS | DS | ES | FS | GS | SS
5975 specialRegister CR0 | CR2 | CR3 | CR4
5976 | DR0 | DR1 | DR2 | DR3 | DR6 | DR7
5977 | TR3 | TR4 | TR5 | TR6 | TR7
5979 We simplify the grammar in obvious places (e.g., register parsing is
5980 done by calling parse_register) and eliminate immediate left recursion
5981 to implement a recursive-descent parser.
5985 expr' cmpOp e04 expr'
6036 /* Parsing structure for the intel syntax parser. Used to implement the
6037 semantic actions for the operand grammar. */
6038 struct intel_parser_s
6040 char *op_string
; /* The string being parsed. */
6041 int got_a_float
; /* Whether the operand is a float. */
6042 int op_modifier
; /* Operand modifier. */
6043 int is_mem
; /* 1 if operand is memory reference. */
6044 int in_offset
; /* >=1 if parsing operand of offset. */
6045 int in_bracket
; /* >=1 if parsing operand in brackets. */
6046 const reg_entry
*reg
; /* Last register reference found. */
6047 char *disp
; /* Displacement string being built. */
6048 char *next_operand
; /* Resume point when splitting operands. */
6051 static struct intel_parser_s intel_parser
;
6053 /* Token structure for parsing intel syntax. */
6056 int code
; /* Token code. */
6057 const reg_entry
*reg
; /* Register entry for register tokens. */
6058 char *str
; /* String representation. */
6061 static struct intel_token cur_token
, prev_token
;
6063 /* Token codes for the intel parser. Since T_SHORT is already used
6064 by COFF, undefine it first to prevent a warning. */
6083 /* Prototypes for intel parser functions. */
6084 static int intel_match_token
PARAMS ((int code
));
6085 static void intel_get_token
PARAMS ((void));
6086 static void intel_putback_token
PARAMS ((void));
6087 static int intel_expr
PARAMS ((void));
6088 static int intel_e04
PARAMS ((void));
6089 static int intel_e05
PARAMS ((void));
6090 static int intel_e06
PARAMS ((void));
6091 static int intel_e09
PARAMS ((void));
6092 static int intel_bracket_expr
PARAMS ((void));
6093 static int intel_e10
PARAMS ((void));
6094 static int intel_e11
PARAMS ((void));
6097 i386_intel_operand (operand_string
, got_a_float
)
6098 char *operand_string
;
6104 p
= intel_parser
.op_string
= xstrdup (operand_string
);
6105 intel_parser
.disp
= (char *) xmalloc (strlen (operand_string
) + 1);
6109 /* Initialize token holders. */
6110 cur_token
.code
= prev_token
.code
= T_NIL
;
6111 cur_token
.reg
= prev_token
.reg
= NULL
;
6112 cur_token
.str
= prev_token
.str
= NULL
;
6114 /* Initialize parser structure. */
6115 intel_parser
.got_a_float
= got_a_float
;
6116 intel_parser
.op_modifier
= 0;
6117 intel_parser
.is_mem
= 0;
6118 intel_parser
.in_offset
= 0;
6119 intel_parser
.in_bracket
= 0;
6120 intel_parser
.reg
= NULL
;
6121 intel_parser
.disp
[0] = '\0';
6122 intel_parser
.next_operand
= NULL
;
6124 /* Read the first token and start the parser. */
6126 ret
= intel_expr ();
6131 if (cur_token
.code
!= T_NIL
)
6133 as_bad (_("invalid operand for '%s' ('%s' unexpected)"),
6134 current_templates
->start
->name
, cur_token
.str
);
6137 /* If we found a memory reference, hand it over to i386_displacement
6138 to fill in the rest of the operand fields. */
6139 else if (intel_parser
.is_mem
)
6141 if ((i
.mem_operands
== 1
6142 && (current_templates
->start
->opcode_modifier
& IsString
) == 0)
6143 || i
.mem_operands
== 2)
6145 as_bad (_("too many memory references for '%s'"),
6146 current_templates
->start
->name
);
6151 char *s
= intel_parser
.disp
;
6154 if (!quiet_warnings
&& intel_parser
.is_mem
< 0)
6155 /* See the comments in intel_bracket_expr. */
6156 as_warn (_("Treating `%s' as memory reference"), operand_string
);
6158 /* Add the displacement expression. */
6160 ret
= i386_displacement (s
, s
+ strlen (s
));
6163 /* Swap base and index in 16-bit memory operands like
6164 [si+bx]. Since i386_index_check is also used in AT&T
6165 mode we have to do that here. */
6168 && (i
.base_reg
->reg_type
& Reg16
)
6169 && (i
.index_reg
->reg_type
& Reg16
)
6170 && i
.base_reg
->reg_num
>= 6
6171 && i
.index_reg
->reg_num
< 6)
6173 const reg_entry
*base
= i
.index_reg
;
6175 i
.index_reg
= i
.base_reg
;
6178 ret
= i386_index_check (operand_string
);
6183 /* Constant and OFFSET expressions are handled by i386_immediate. */
6184 else if ((intel_parser
.op_modifier
& (1 << T_OFFSET
))
6185 || intel_parser
.reg
== NULL
)
6186 ret
= i386_immediate (intel_parser
.disp
);
6188 if (intel_parser
.next_operand
&& this_operand
>= MAX_OPERANDS
- 1)
6190 if (!ret
|| !intel_parser
.next_operand
)
6192 intel_parser
.op_string
= intel_parser
.next_operand
;
6193 this_operand
= i
.operands
++;
6197 free (intel_parser
.disp
);
6202 #define NUM_ADDRESS_REGS (!!i.base_reg + !!i.index_reg)
6206 expr' cmpOp e04 expr'
6211 /* XXX Implement the comparison operators. */
6212 return intel_e04 ();
6229 if (nregs
>= 0 && NUM_ADDRESS_REGS
> nregs
)
6230 i
.base_reg
= i386_regtab
+ REGNAM_AL
; /* al is invalid as base */
6232 if (cur_token
.code
== '+')
6234 else if (cur_token
.code
== '-')
6235 nregs
= NUM_ADDRESS_REGS
;
6239 strcat (intel_parser
.disp
, cur_token
.str
);
6240 intel_match_token (cur_token
.code
);
6251 int nregs
= ~NUM_ADDRESS_REGS
;
6258 if (cur_token
.code
== '&' || cur_token
.code
== '|' || cur_token
.code
== '^')
6262 str
[0] = cur_token
.code
;
6264 strcat (intel_parser
.disp
, str
);
6269 intel_match_token (cur_token
.code
);
6274 if (nregs
>= 0 && NUM_ADDRESS_REGS
> nregs
)
6275 i
.base_reg
= i386_regtab
+ REGNAM_AL
+ 1; /* cl is invalid as base */
6286 int nregs
= ~NUM_ADDRESS_REGS
;
6293 if (cur_token
.code
== '*' || cur_token
.code
== '/' || cur_token
.code
== '%')
6297 str
[0] = cur_token
.code
;
6299 strcat (intel_parser
.disp
, str
);
6301 else if (cur_token
.code
== T_SHL
)
6302 strcat (intel_parser
.disp
, "<<");
6303 else if (cur_token
.code
== T_SHR
)
6304 strcat (intel_parser
.disp
, ">>");
6308 intel_match_token (cur_token
.code
);
6313 if (nregs
>= 0 && NUM_ADDRESS_REGS
> nregs
)
6314 i
.base_reg
= i386_regtab
+ REGNAM_AL
+ 2; /* dl is invalid as base */
6332 int nregs
= ~NUM_ADDRESS_REGS
;
6337 /* Don't consume constants here. */
6338 if (cur_token
.code
== '+' || cur_token
.code
== '-')
6340 /* Need to look one token ahead - if the next token
6341 is a constant, the current token is its sign. */
6344 intel_match_token (cur_token
.code
);
6345 next_code
= cur_token
.code
;
6346 intel_putback_token ();
6347 if (next_code
== T_CONST
)
6351 /* e09 OFFSET e09 */
6352 if (cur_token
.code
== T_OFFSET
)
6355 ++intel_parser
.in_offset
;
6359 else if (cur_token
.code
== T_SHORT
)
6360 intel_parser
.op_modifier
|= 1 << T_SHORT
;
6363 else if (cur_token
.code
== '+')
6364 strcat (intel_parser
.disp
, "+");
6369 else if (cur_token
.code
== '-' || cur_token
.code
== '~')
6375 str
[0] = cur_token
.code
;
6377 strcat (intel_parser
.disp
, str
);
6384 intel_match_token (cur_token
.code
);
6392 /* e09' PTR e10 e09' */
6393 if (cur_token
.code
== T_PTR
)
6397 if (prev_token
.code
== T_BYTE
)
6398 suffix
= BYTE_MNEM_SUFFIX
;
6400 else if (prev_token
.code
== T_WORD
)
6402 if (current_templates
->start
->name
[0] == 'l'
6403 && current_templates
->start
->name
[2] == 's'
6404 && current_templates
->start
->name
[3] == 0)
6405 suffix
= BYTE_MNEM_SUFFIX
; /* so it will cause an error */
6406 else if (intel_parser
.got_a_float
== 2) /* "fi..." */
6407 suffix
= SHORT_MNEM_SUFFIX
;
6409 suffix
= WORD_MNEM_SUFFIX
;
6412 else if (prev_token
.code
== T_DWORD
)
6414 if (current_templates
->start
->name
[0] == 'l'
6415 && current_templates
->start
->name
[2] == 's'
6416 && current_templates
->start
->name
[3] == 0)
6417 suffix
= WORD_MNEM_SUFFIX
;
6418 else if (flag_code
== CODE_16BIT
6419 && (current_templates
->start
->opcode_modifier
6420 & (Jump
| JumpDword
)))
6421 suffix
= LONG_DOUBLE_MNEM_SUFFIX
;
6422 else if (intel_parser
.got_a_float
== 1) /* "f..." */
6423 suffix
= SHORT_MNEM_SUFFIX
;
6425 suffix
= LONG_MNEM_SUFFIX
;
6428 else if (prev_token
.code
== T_FWORD
)
6430 if (current_templates
->start
->name
[0] == 'l'
6431 && current_templates
->start
->name
[2] == 's'
6432 && current_templates
->start
->name
[3] == 0)
6433 suffix
= LONG_MNEM_SUFFIX
;
6434 else if (!intel_parser
.got_a_float
)
6436 if (flag_code
== CODE_16BIT
)
6437 add_prefix (DATA_PREFIX_OPCODE
);
6438 suffix
= LONG_DOUBLE_MNEM_SUFFIX
;
6441 suffix
= BYTE_MNEM_SUFFIX
; /* so it will cause an error */
6444 else if (prev_token
.code
== T_QWORD
)
6446 if (intel_parser
.got_a_float
== 1) /* "f..." */
6447 suffix
= LONG_MNEM_SUFFIX
;
6449 suffix
= QWORD_MNEM_SUFFIX
;
6452 else if (prev_token
.code
== T_TBYTE
)
6454 if (intel_parser
.got_a_float
== 1)
6455 suffix
= LONG_DOUBLE_MNEM_SUFFIX
;
6457 suffix
= BYTE_MNEM_SUFFIX
; /* so it will cause an error */
6460 else if (prev_token
.code
== T_XMMWORD
)
6462 /* XXX ignored for now, but accepted since gcc uses it */
6468 as_bad (_("Unknown operand modifier `%s'"), prev_token
.str
);
6472 /* Operands for jump/call using 'ptr' notation denote absolute
6474 if (current_templates
->start
->opcode_modifier
& (Jump
| JumpDword
))
6475 i
.types
[this_operand
] |= JumpAbsolute
;
6477 if (current_templates
->start
->base_opcode
== 0x8d /* lea */)
6481 else if (i
.suffix
!= suffix
)
6483 as_bad (_("Conflicting operand modifiers"));
6489 /* e09' : e10 e09' */
6490 else if (cur_token
.code
== ':')
6492 if (prev_token
.code
!= T_REG
)
6494 /* While {call,jmp} SSSS:OOOO is MASM syntax only when SSSS is a
6495 segment/group identifier (which we don't have), using comma
6496 as the operand separator there is even less consistent, since
6497 there all branches only have a single operand. */
6498 if (this_operand
!= 0
6499 || intel_parser
.in_offset
6500 || intel_parser
.in_bracket
6501 || (!(current_templates
->start
->opcode_modifier
6502 & (Jump
|JumpDword
|JumpInterSegment
))
6503 && !(current_templates
->start
->operand_types
[0]
6505 return intel_match_token (T_NIL
);
6506 /* Remember the start of the 2nd operand and terminate 1st
6508 XXX This isn't right, yet (when SSSS:OOOO is right operand of
6509 another expression), but it gets at least the simplest case
6510 (a plain number or symbol on the left side) right. */
6511 intel_parser
.next_operand
= intel_parser
.op_string
;
6512 *--intel_parser
.op_string
= '\0';
6513 return intel_match_token (':');
6521 intel_match_token (cur_token
.code
);
6527 --intel_parser
.in_offset
;
6530 if (NUM_ADDRESS_REGS
> nregs
)
6532 as_bad (_("Invalid operand to `OFFSET'"));
6535 intel_parser
.op_modifier
|= 1 << T_OFFSET
;
6538 if (nregs
>= 0 && NUM_ADDRESS_REGS
> nregs
)
6539 i
.base_reg
= i386_regtab
+ REGNAM_AL
+ 3; /* bl is invalid as base */
6544 intel_bracket_expr ()
6546 int was_offset
= intel_parser
.op_modifier
& (1 << T_OFFSET
);
6547 const char *start
= intel_parser
.op_string
;
6550 if (i
.op
[this_operand
].regs
)
6551 return intel_match_token (T_NIL
);
6553 intel_match_token ('[');
6555 /* Mark as a memory operand only if it's not already known to be an
6556 offset expression. If it's an offset expression, we need to keep
6558 if (!intel_parser
.in_offset
)
6560 ++intel_parser
.in_bracket
;
6562 /* Operands for jump/call inside brackets denote absolute addresses. */
6563 if (current_templates
->start
->opcode_modifier
& (Jump
| JumpDword
))
6564 i
.types
[this_operand
] |= JumpAbsolute
;
6566 /* Unfortunately gas always diverged from MASM in a respect that can't
6567 be easily fixed without risking to break code sequences likely to be
6568 encountered (the testsuite even check for this): MASM doesn't consider
6569 an expression inside brackets unconditionally as a memory reference.
6570 When that is e.g. a constant, an offset expression, or the sum of the
6571 two, this is still taken as a constant load. gas, however, always
6572 treated these as memory references. As a compromise, we'll try to make
6573 offset expressions inside brackets work the MASM way (since that's
6574 less likely to be found in real world code), but make constants alone
6575 continue to work the traditional gas way. In either case, issue a
6577 intel_parser
.op_modifier
&= ~was_offset
;
6580 strcat (intel_parser
.disp
, "[");
6582 /* Add a '+' to the displacement string if necessary. */
6583 if (*intel_parser
.disp
!= '\0'
6584 && *(intel_parser
.disp
+ strlen (intel_parser
.disp
) - 1) != '+')
6585 strcat (intel_parser
.disp
, "+");
6588 && (len
= intel_parser
.op_string
- start
- 1,
6589 intel_match_token (']')))
6591 /* Preserve brackets when the operand is an offset expression. */
6592 if (intel_parser
.in_offset
)
6593 strcat (intel_parser
.disp
, "]");
6596 --intel_parser
.in_bracket
;
6597 if (i
.base_reg
|| i
.index_reg
)
6598 intel_parser
.is_mem
= 1;
6599 if (!intel_parser
.is_mem
)
6601 if (!(intel_parser
.op_modifier
& (1 << T_OFFSET
)))
6602 /* Defer the warning until all of the operand was parsed. */
6603 intel_parser
.is_mem
= -1;
6604 else if (!quiet_warnings
)
6605 as_warn (_("`[%.*s]' taken to mean just `%.*s'"), len
, start
, len
, start
);
6608 intel_parser
.op_modifier
|= was_offset
;
6625 while (cur_token
.code
== '[')
6627 if (!intel_bracket_expr ())
6652 switch (cur_token
.code
)
6656 intel_match_token ('(');
6657 strcat (intel_parser
.disp
, "(");
6659 if (intel_expr () && intel_match_token (')'))
6661 strcat (intel_parser
.disp
, ")");
6668 return intel_bracket_expr ();
6673 strcat (intel_parser
.disp
, cur_token
.str
);
6674 intel_match_token (cur_token
.code
);
6676 /* Mark as a memory operand only if it's not already known to be an
6677 offset expression. */
6678 if (!intel_parser
.in_offset
)
6679 intel_parser
.is_mem
= 1;
6686 const reg_entry
*reg
= intel_parser
.reg
= cur_token
.reg
;
6688 intel_match_token (T_REG
);
6690 /* Check for segment change. */
6691 if (cur_token
.code
== ':')
6693 if (!(reg
->reg_type
& (SReg2
| SReg3
)))
6695 as_bad (_("`%s' is not a valid segment register"), reg
->reg_name
);
6698 else if (i
.seg
[i
.mem_operands
])
6699 as_warn (_("Extra segment override ignored"));
6702 if (!intel_parser
.in_offset
)
6703 intel_parser
.is_mem
= 1;
6704 switch (reg
->reg_num
)
6707 i
.seg
[i
.mem_operands
] = &es
;
6710 i
.seg
[i
.mem_operands
] = &cs
;
6713 i
.seg
[i
.mem_operands
] = &ss
;
6716 i
.seg
[i
.mem_operands
] = &ds
;
6719 i
.seg
[i
.mem_operands
] = &fs
;
6722 i
.seg
[i
.mem_operands
] = &gs
;
6728 /* Not a segment register. Check for register scaling. */
6729 else if (cur_token
.code
== '*')
6731 if (!intel_parser
.in_bracket
)
6733 as_bad (_("Register scaling only allowed in memory operands"));
6737 if (reg
->reg_type
& Reg16
) /* Disallow things like [si*1]. */
6738 reg
= i386_regtab
+ REGNAM_AX
+ 4; /* sp is invalid as index */
6739 else if (i
.index_reg
)
6740 reg
= i386_regtab
+ REGNAM_EAX
+ 4; /* esp is invalid as index */
6742 /* What follows must be a valid scale. */
6743 intel_match_token ('*');
6745 i
.types
[this_operand
] |= BaseIndex
;
6747 /* Set the scale after setting the register (otherwise,
6748 i386_scale will complain) */
6749 if (cur_token
.code
== '+' || cur_token
.code
== '-')
6751 char *str
, sign
= cur_token
.code
;
6752 intel_match_token (cur_token
.code
);
6753 if (cur_token
.code
!= T_CONST
)
6755 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
6759 str
= (char *) xmalloc (strlen (cur_token
.str
) + 2);
6760 strcpy (str
+ 1, cur_token
.str
);
6762 if (!i386_scale (str
))
6766 else if (!i386_scale (cur_token
.str
))
6768 intel_match_token (cur_token
.code
);
6771 /* No scaling. If this is a memory operand, the register is either a
6772 base register (first occurrence) or an index register (second
6774 else if (intel_parser
.in_bracket
)
6779 else if (!i
.index_reg
)
6783 as_bad (_("Too many register references in memory operand"));
6787 i
.types
[this_operand
] |= BaseIndex
;
6790 /* It's neither base nor index. */
6791 else if (!intel_parser
.in_offset
&& !intel_parser
.is_mem
)
6793 i
.types
[this_operand
] |= reg
->reg_type
& ~BaseIndex
;
6794 i
.op
[this_operand
].regs
= reg
;
6799 as_bad (_("Invalid use of register"));
6803 /* Since registers are not part of the displacement string (except
6804 when we're parsing offset operands), we may need to remove any
6805 preceding '+' from the displacement string. */
6806 if (*intel_parser
.disp
!= '\0'
6807 && !intel_parser
.in_offset
)
6809 char *s
= intel_parser
.disp
;
6810 s
+= strlen (s
) - 1;
6833 intel_match_token (cur_token
.code
);
6835 if (cur_token
.code
== T_PTR
)
6838 /* It must have been an identifier. */
6839 intel_putback_token ();
6840 cur_token
.code
= T_ID
;
6846 if (!intel_parser
.in_offset
&& intel_parser
.is_mem
<= 0)
6850 /* The identifier represents a memory reference only if it's not
6851 preceded by an offset modifier and if it's not an equate. */
6852 symbolP
= symbol_find(cur_token
.str
);
6853 if (!symbolP
|| S_GET_SEGMENT(symbolP
) != absolute_section
)
6854 intel_parser
.is_mem
= 1;
6862 char *save_str
, sign
= 0;
6864 /* Allow constants that start with `+' or `-'. */
6865 if (cur_token
.code
== '-' || cur_token
.code
== '+')
6867 sign
= cur_token
.code
;
6868 intel_match_token (cur_token
.code
);
6869 if (cur_token
.code
!= T_CONST
)
6871 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
6877 save_str
= (char *) xmalloc (strlen (cur_token
.str
) + 2);
6878 strcpy (save_str
+ !!sign
, cur_token
.str
);
6882 /* Get the next token to check for register scaling. */
6883 intel_match_token (cur_token
.code
);
6885 /* Check if this constant is a scaling factor for an index register. */
6886 if (cur_token
.code
== '*')
6888 if (intel_match_token ('*') && cur_token
.code
== T_REG
)
6890 const reg_entry
*reg
= cur_token
.reg
;
6892 if (!intel_parser
.in_bracket
)
6894 as_bad (_("Register scaling only allowed in memory operands"));
6898 if (reg
->reg_type
& Reg16
) /* Disallow things like [1*si]. */
6899 reg
= i386_regtab
+ REGNAM_AX
+ 4; /* sp is invalid as index */
6900 else if (i
.index_reg
)
6901 reg
= i386_regtab
+ REGNAM_EAX
+ 4; /* esp is invalid as index */
6903 /* The constant is followed by `* reg', so it must be
6906 i
.types
[this_operand
] |= BaseIndex
;
6908 /* Set the scale after setting the register (otherwise,
6909 i386_scale will complain) */
6910 if (!i386_scale (save_str
))
6912 intel_match_token (T_REG
);
6914 /* Since registers are not part of the displacement
6915 string, we may need to remove any preceding '+' from
6916 the displacement string. */
6917 if (*intel_parser
.disp
!= '\0')
6919 char *s
= intel_parser
.disp
;
6920 s
+= strlen (s
) - 1;
6930 /* The constant was not used for register scaling. Since we have
6931 already consumed the token following `*' we now need to put it
6932 back in the stream. */
6933 intel_putback_token ();
6936 /* Add the constant to the displacement string. */
6937 strcat (intel_parser
.disp
, save_str
);
6944 as_bad (_("Unrecognized token '%s'"), cur_token
.str
);
6948 /* Match the given token against cur_token. If they match, read the next
6949 token from the operand string. */
6951 intel_match_token (code
)
6954 if (cur_token
.code
== code
)
6961 as_bad (_("Unexpected token `%s'"), cur_token
.str
);
6966 /* Read a new token from intel_parser.op_string and store it in cur_token. */
6971 const reg_entry
*reg
;
6972 struct intel_token new_token
;
6974 new_token
.code
= T_NIL
;
6975 new_token
.reg
= NULL
;
6976 new_token
.str
= NULL
;
6978 /* Free the memory allocated to the previous token and move
6979 cur_token to prev_token. */
6981 free (prev_token
.str
);
6983 prev_token
= cur_token
;
6985 /* Skip whitespace. */
6986 while (is_space_char (*intel_parser
.op_string
))
6987 intel_parser
.op_string
++;
6989 /* Return an empty token if we find nothing else on the line. */
6990 if (*intel_parser
.op_string
== '\0')
6992 cur_token
= new_token
;
6996 /* The new token cannot be larger than the remainder of the operand
6998 new_token
.str
= (char *) xmalloc (strlen (intel_parser
.op_string
) + 1);
6999 new_token
.str
[0] = '\0';
7001 if (strchr ("0123456789", *intel_parser
.op_string
))
7003 char *p
= new_token
.str
;
7004 char *q
= intel_parser
.op_string
;
7005 new_token
.code
= T_CONST
;
7007 /* Allow any kind of identifier char to encompass floating point and
7008 hexadecimal numbers. */
7009 while (is_identifier_char (*q
))
7013 /* Recognize special symbol names [0-9][bf]. */
7014 if (strlen (intel_parser
.op_string
) == 2
7015 && (intel_parser
.op_string
[1] == 'b'
7016 || intel_parser
.op_string
[1] == 'f'))
7017 new_token
.code
= T_ID
;
7020 else if ((reg
= parse_register (intel_parser
.op_string
, &end_op
)) != NULL
)
7022 size_t len
= end_op
- intel_parser
.op_string
;
7024 new_token
.code
= T_REG
;
7025 new_token
.reg
= reg
;
7027 memcpy (new_token
.str
, intel_parser
.op_string
, len
);
7028 new_token
.str
[len
] = '\0';
7031 else if (is_identifier_char (*intel_parser
.op_string
))
7033 char *p
= new_token
.str
;
7034 char *q
= intel_parser
.op_string
;
7036 /* A '.' or '$' followed by an identifier char is an identifier.
7037 Otherwise, it's operator '.' followed by an expression. */
7038 if ((*q
== '.' || *q
== '$') && !is_identifier_char (*(q
+ 1)))
7040 new_token
.code
= '.';
7041 new_token
.str
[0] = '.';
7042 new_token
.str
[1] = '\0';
7046 while (is_identifier_char (*q
) || *q
== '@')
7050 if (strcasecmp (new_token
.str
, "NOT") == 0)
7051 new_token
.code
= '~';
7053 else if (strcasecmp (new_token
.str
, "MOD") == 0)
7054 new_token
.code
= '%';
7056 else if (strcasecmp (new_token
.str
, "AND") == 0)
7057 new_token
.code
= '&';
7059 else if (strcasecmp (new_token
.str
, "OR") == 0)
7060 new_token
.code
= '|';
7062 else if (strcasecmp (new_token
.str
, "XOR") == 0)
7063 new_token
.code
= '^';
7065 else if (strcasecmp (new_token
.str
, "SHL") == 0)
7066 new_token
.code
= T_SHL
;
7068 else if (strcasecmp (new_token
.str
, "SHR") == 0)
7069 new_token
.code
= T_SHR
;
7071 else if (strcasecmp (new_token
.str
, "BYTE") == 0)
7072 new_token
.code
= T_BYTE
;
7074 else if (strcasecmp (new_token
.str
, "WORD") == 0)
7075 new_token
.code
= T_WORD
;
7077 else if (strcasecmp (new_token
.str
, "DWORD") == 0)
7078 new_token
.code
= T_DWORD
;
7080 else if (strcasecmp (new_token
.str
, "FWORD") == 0)
7081 new_token
.code
= T_FWORD
;
7083 else if (strcasecmp (new_token
.str
, "QWORD") == 0)
7084 new_token
.code
= T_QWORD
;
7086 else if (strcasecmp (new_token
.str
, "TBYTE") == 0
7087 /* XXX remove (gcc still uses it) */
7088 || strcasecmp (new_token
.str
, "XWORD") == 0)
7089 new_token
.code
= T_TBYTE
;
7091 else if (strcasecmp (new_token
.str
, "XMMWORD") == 0
7092 || strcasecmp (new_token
.str
, "OWORD") == 0)
7093 new_token
.code
= T_XMMWORD
;
7095 else if (strcasecmp (new_token
.str
, "PTR") == 0)
7096 new_token
.code
= T_PTR
;
7098 else if (strcasecmp (new_token
.str
, "SHORT") == 0)
7099 new_token
.code
= T_SHORT
;
7101 else if (strcasecmp (new_token
.str
, "OFFSET") == 0)
7103 new_token
.code
= T_OFFSET
;
7105 /* ??? This is not mentioned in the MASM grammar but gcc
7106 makes use of it with -mintel-syntax. OFFSET may be
7107 followed by FLAT: */
7108 if (strncasecmp (q
, " FLAT:", 6) == 0)
7109 strcat (new_token
.str
, " FLAT:");
7112 /* ??? This is not mentioned in the MASM grammar. */
7113 else if (strcasecmp (new_token
.str
, "FLAT") == 0)
7115 new_token
.code
= T_OFFSET
;
7117 strcat (new_token
.str
, ":");
7119 as_bad (_("`:' expected"));
7123 new_token
.code
= T_ID
;
7127 else if (strchr ("+-/*%|&^:[]()~", *intel_parser
.op_string
))
7129 new_token
.code
= *intel_parser
.op_string
;
7130 new_token
.str
[0] = *intel_parser
.op_string
;
7131 new_token
.str
[1] = '\0';
7134 else if (strchr ("<>", *intel_parser
.op_string
)
7135 && *intel_parser
.op_string
== *(intel_parser
.op_string
+ 1))
7137 new_token
.code
= *intel_parser
.op_string
== '<' ? T_SHL
: T_SHR
;
7138 new_token
.str
[0] = *intel_parser
.op_string
;
7139 new_token
.str
[1] = *intel_parser
.op_string
;
7140 new_token
.str
[2] = '\0';
7144 as_bad (_("Unrecognized token `%s'"), intel_parser
.op_string
);
7146 intel_parser
.op_string
+= strlen (new_token
.str
);
7147 cur_token
= new_token
;
7150 /* Put cur_token back into the token stream and make cur_token point to
7153 intel_putback_token ()
7155 if (cur_token
.code
!= T_NIL
)
7157 intel_parser
.op_string
-= strlen (cur_token
.str
);
7158 free (cur_token
.str
);
7160 cur_token
= prev_token
;
7162 /* Forget prev_token. */
7163 prev_token
.code
= T_NIL
;
7164 prev_token
.reg
= NULL
;
7165 prev_token
.str
= NULL
;
7169 tc_x86_regname_to_dw2regnum (const char *regname
)
7171 unsigned int regnum
;
7172 unsigned int regnames_count
;
7173 static const char *const regnames_32
[] =
7175 "eax", "ecx", "edx", "ebx",
7176 "esp", "ebp", "esi", "edi",
7177 "eip", "eflags", NULL
,
7178 "st0", "st1", "st2", "st3",
7179 "st4", "st5", "st6", "st7",
7181 "xmm0", "xmm1", "xmm2", "xmm3",
7182 "xmm4", "xmm5", "xmm6", "xmm7",
7183 "mm0", "mm1", "mm2", "mm3",
7184 "mm4", "mm5", "mm6", "mm7",
7185 "fcw", "fsw", "mxcsr",
7186 "es", "cs", "ss", "ds", "fs", "gs", NULL
, NULL
,
7189 static const char *const regnames_64
[] =
7191 "rax", "rdx", "rcx", "rbx",
7192 "rsi", "rdi", "rbp", "rsp",
7193 "r8", "r9", "r10", "r11",
7194 "r12", "r13", "r14", "r15",
7196 "xmm0", "xmm1", "xmm2", "xmm3",
7197 "xmm4", "xmm5", "xmm6", "xmm7",
7198 "xmm8", "xmm9", "xmm10", "xmm11",
7199 "xmm12", "xmm13", "xmm14", "xmm15",
7200 "st0", "st1", "st2", "st3",
7201 "st4", "st5", "st6", "st7",
7202 "mm0", "mm1", "mm2", "mm3",
7203 "mm4", "mm5", "mm6", "mm7",
7205 "es", "cs", "ss", "ds", "fs", "gs", NULL
, NULL
,
7206 "fs.base", "gs.base", NULL
, NULL
,
7208 "mxcsr", "fcw", "fsw"
7210 const char *const *regnames
;
7212 if (flag_code
== CODE_64BIT
)
7214 regnames
= regnames_64
;
7215 regnames_count
= ARRAY_SIZE (regnames_64
);
7219 regnames
= regnames_32
;
7220 regnames_count
= ARRAY_SIZE (regnames_32
);
7223 for (regnum
= 0; regnum
< regnames_count
; regnum
++)
7224 if (regnames
[regnum
] != NULL
7225 && strcmp (regname
, regnames
[regnum
]) == 0)
7232 tc_x86_frame_initial_instructions (void)
7234 static unsigned int sp_regno
;
7237 sp_regno
= tc_x86_regname_to_dw2regnum (flag_code
== CODE_64BIT
7240 cfi_add_CFA_def_cfa (sp_regno
, -x86_cie_data_alignment
);
7241 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
7245 i386_elf_section_type (const char *str
, size_t len
)
7247 if (flag_code
== CODE_64BIT
7248 && len
== sizeof ("unwind") - 1
7249 && strncmp (str
, "unwind", 6) == 0)
7250 return SHT_X86_64_UNWIND
;
7257 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
7261 expr
.X_op
= O_secrel
;
7262 expr
.X_add_symbol
= symbol
;
7263 expr
.X_add_number
= 0;
7264 emit_expr (&expr
, size
);
7268 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7269 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
7272 x86_64_section_letter (int letter
, char **ptr_msg
)
7274 if (flag_code
== CODE_64BIT
)
7277 return SHF_X86_64_LARGE
;
7279 *ptr_msg
= _("Bad .section directive: want a,l,w,x,M,S,G,T in string");
7282 *ptr_msg
= _("Bad .section directive: want a,w,x,M,S,G,T in string");
7287 x86_64_section_word (char *str
, size_t len
)
7289 if (len
== 5 && flag_code
== CODE_64BIT
&& strncmp (str
, "large", 5) == 0)
7290 return SHF_X86_64_LARGE
;
7296 handle_large_common (int small ATTRIBUTE_UNUSED
)
7298 if (flag_code
!= CODE_64BIT
)
7300 s_comm_internal (0, elf_common_parse
);
7301 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
7305 static segT lbss_section
;
7306 asection
*saved_com_section_ptr
= elf_com_section_ptr
;
7307 asection
*saved_bss_section
= bss_section
;
7309 if (lbss_section
== NULL
)
7311 flagword applicable
;
7313 subsegT subseg
= now_subseg
;
7315 /* The .lbss section is for local .largecomm symbols. */
7316 lbss_section
= subseg_new (".lbss", 0);
7317 applicable
= bfd_applicable_section_flags (stdoutput
);
7318 bfd_set_section_flags (stdoutput
, lbss_section
,
7319 applicable
& SEC_ALLOC
);
7320 seg_info (lbss_section
)->bss
= 1;
7322 subseg_set (seg
, subseg
);
7325 elf_com_section_ptr
= &_bfd_elf_large_com_section
;
7326 bss_section
= lbss_section
;
7328 s_comm_internal (0, elf_common_parse
);
7330 elf_com_section_ptr
= saved_com_section_ptr
;
7331 bss_section
= saved_bss_section
;
7334 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */