1 /* i386.c -- Assemble code for the Intel 80386
2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005
4 Free Software Foundation, Inc.
6 This file is part of GAS, the GNU Assembler.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
23 /* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
25 x86_64 support by Jan Hubicka (jh@suse.cz)
26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
27 Bugs & suggestions are completely welcome. This is free software.
28 Please help us make it better. */
31 #include "safe-ctype.h"
33 #include "dwarf2dbg.h"
34 #include "dw2gencfi.h"
35 #include "opcode/i386.h"
36 #include "elf/x86-64.h"
38 #ifndef REGISTER_WARNINGS
39 #define REGISTER_WARNINGS 1
42 #ifndef INFER_ADDR_PREFIX
43 #define INFER_ADDR_PREFIX 1
46 #ifndef SCALE1_WHEN_NO_INDEX
47 /* Specifying a scale factor besides 1 when there is no index is
48 futile. eg. `mov (%ebx,2),%al' does exactly the same as
49 `mov (%ebx),%al'. To slavishly follow what the programmer
50 specified, set SCALE1_WHEN_NO_INDEX to 0. */
51 #define SCALE1_WHEN_NO_INDEX 1
55 #define DEFAULT_ARCH "i386"
60 #define INLINE __inline__
66 static INLINE
unsigned int mode_from_disp_size
PARAMS ((unsigned int));
67 static INLINE
int fits_in_signed_byte
PARAMS ((offsetT
));
68 static INLINE
int fits_in_unsigned_byte
PARAMS ((offsetT
));
69 static INLINE
int fits_in_unsigned_word
PARAMS ((offsetT
));
70 static INLINE
int fits_in_signed_word
PARAMS ((offsetT
));
71 static INLINE
int fits_in_unsigned_long
PARAMS ((offsetT
));
72 static INLINE
int fits_in_signed_long
PARAMS ((offsetT
));
73 static int smallest_imm_type
PARAMS ((offsetT
));
74 static offsetT offset_in_range
PARAMS ((offsetT
, int));
75 static int add_prefix
PARAMS ((unsigned int));
76 static void set_code_flag
PARAMS ((int));
77 static void set_16bit_gcc_code_flag
PARAMS ((int));
78 static void set_intel_syntax
PARAMS ((int));
79 static void set_cpu_arch
PARAMS ((int));
81 static void pe_directive_secrel
PARAMS ((int));
83 static char *output_invalid
PARAMS ((int c
));
84 static int i386_operand
PARAMS ((char *operand_string
));
85 static int i386_intel_operand
PARAMS ((char *operand_string
, int got_a_float
));
86 static const reg_entry
*parse_register
PARAMS ((char *reg_string
,
88 static char *parse_insn
PARAMS ((char *, char *));
89 static char *parse_operands
PARAMS ((char *, const char *));
90 static void swap_operands
PARAMS ((void));
91 static void optimize_imm
PARAMS ((void));
92 static void optimize_disp
PARAMS ((void));
93 static int match_template
PARAMS ((void));
94 static int check_string
PARAMS ((void));
95 static int process_suffix
PARAMS ((void));
96 static int check_byte_reg
PARAMS ((void));
97 static int check_long_reg
PARAMS ((void));
98 static int check_qword_reg
PARAMS ((void));
99 static int check_word_reg
PARAMS ((void));
100 static int finalize_imm
PARAMS ((void));
101 static int process_operands
PARAMS ((void));
102 static const seg_entry
*build_modrm_byte
PARAMS ((void));
103 static void output_insn
PARAMS ((void));
104 static void output_branch
PARAMS ((void));
105 static void output_jump
PARAMS ((void));
106 static void output_interseg_jump
PARAMS ((void));
107 static void output_imm
PARAMS ((fragS
*insn_start_frag
,
108 offsetT insn_start_off
));
109 static void output_disp
PARAMS ((fragS
*insn_start_frag
,
110 offsetT insn_start_off
));
112 static void s_bss
PARAMS ((int));
115 static const char *default_arch
= DEFAULT_ARCH
;
117 /* 'md_assemble ()' gathers together information and puts it into a
124 const reg_entry
*regs
;
129 /* TM holds the template for the insn were currently assembling. */
132 /* SUFFIX holds the instruction mnemonic suffix if given.
133 (e.g. 'l' for 'movl') */
136 /* OPERANDS gives the number of given operands. */
137 unsigned int operands
;
139 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
140 of given register, displacement, memory operands and immediate
142 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
144 /* TYPES [i] is the type (see above #defines) which tells us how to
145 use OP[i] for the corresponding operand. */
146 unsigned int types
[MAX_OPERANDS
];
148 /* Displacement expression, immediate expression, or register for each
150 union i386_op op
[MAX_OPERANDS
];
152 /* Flags for operands. */
153 unsigned int flags
[MAX_OPERANDS
];
154 #define Operand_PCrel 1
156 /* Relocation type for operand */
157 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
159 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
160 the base index byte below. */
161 const reg_entry
*base_reg
;
162 const reg_entry
*index_reg
;
163 unsigned int log2_scale_factor
;
165 /* SEG gives the seg_entries of this insn. They are zero unless
166 explicit segment overrides are given. */
167 const seg_entry
*seg
[2];
169 /* PREFIX holds all the given prefix opcodes (usually null).
170 PREFIXES is the number of prefix opcodes. */
171 unsigned int prefixes
;
172 unsigned char prefix
[MAX_PREFIXES
];
174 /* RM and SIB are the modrm byte and the sib byte where the
175 addressing modes of this insn are encoded. */
182 typedef struct _i386_insn i386_insn
;
184 /* List of chars besides those in app.c:symbol_chars that can start an
185 operand. Used to prevent the scrubber eating vital white-space. */
186 const char extra_symbol_chars
[] = "*%-(["
195 #if (defined (TE_I386AIX) \
196 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
197 && !defined (TE_LINUX) \
198 && !defined (TE_NETWARE) \
199 && !defined (TE_FreeBSD) \
200 && !defined (TE_NetBSD)))
201 /* This array holds the chars that always start a comment. If the
202 pre-processor is disabled, these aren't very useful. */
203 const char comment_chars
[] = "#/";
204 #define PREFIX_SEPARATOR '\\'
206 /* This array holds the chars that only start a comment at the beginning of
207 a line. If the line seems to have the form '# 123 filename'
208 .line and .file directives will appear in the pre-processed output.
209 Note that input_file.c hand checks for '#' at the beginning of the
210 first line of the input file. This is because the compiler outputs
211 #NO_APP at the beginning of its output.
212 Also note that comments started like this one will always work if
213 '/' isn't otherwise defined. */
214 const char line_comment_chars
[] = "#";
217 /* Putting '/' here makes it impossible to use the divide operator.
218 However, we need it for compatibility with SVR4 systems. */
219 const char comment_chars
[] = "#";
220 #define PREFIX_SEPARATOR '/'
222 const char line_comment_chars
[] = "/#";
225 const char line_separator_chars
[] = ";";
227 /* Chars that can be used to separate mant from exp in floating point
229 const char EXP_CHARS
[] = "eE";
231 /* Chars that mean this number is a floating point constant
234 const char FLT_CHARS
[] = "fFdDxX";
236 /* Tables for lexical analysis. */
237 static char mnemonic_chars
[256];
238 static char register_chars
[256];
239 static char operand_chars
[256];
240 static char identifier_chars
[256];
241 static char digit_chars
[256];
243 /* Lexical macros. */
244 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
245 #define is_operand_char(x) (operand_chars[(unsigned char) x])
246 #define is_register_char(x) (register_chars[(unsigned char) x])
247 #define is_space_char(x) ((x) == ' ')
248 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
249 #define is_digit_char(x) (digit_chars[(unsigned char) x])
251 /* All non-digit non-letter characters that may occur in an operand. */
252 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
254 /* md_assemble() always leaves the strings it's passed unaltered. To
255 effect this we maintain a stack of saved characters that we've smashed
256 with '\0's (indicating end of strings for various sub-fields of the
257 assembler instruction). */
258 static char save_stack
[32];
259 static char *save_stack_p
;
260 #define END_STRING_AND_SAVE(s) \
261 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
262 #define RESTORE_END_STRING(s) \
263 do { *(s) = *--save_stack_p; } while (0)
265 /* The instruction we're assembling. */
268 /* Possible templates for current insn. */
269 static const templates
*current_templates
;
271 /* Per instruction expressionS buffers: 2 displacements & 2 immediate max. */
272 static expressionS disp_expressions
[2], im_expressions
[2];
274 /* Current operand we are working on. */
275 static int this_operand
;
277 /* We support four different modes. FLAG_CODE variable is used to distinguish
284 #define NUM_FLAG_CODE ((int) CODE_64BIT + 1)
286 static enum flag_code flag_code
;
287 static int use_rela_relocations
= 0;
289 /* The names used to print error messages. */
290 static const char *flag_code_names
[] =
297 /* 1 for intel syntax,
299 static int intel_syntax
= 0;
301 /* 1 if register prefix % not required. */
302 static int allow_naked_reg
= 0;
304 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
305 leave, push, and pop instructions so that gcc has the same stack
306 frame as in 32 bit mode. */
307 static char stackop_size
= '\0';
309 /* Non-zero to optimize code alignment. */
310 int optimize_align_code
= 1;
312 /* Non-zero to quieten some warnings. */
313 static int quiet_warnings
= 0;
316 static const char *cpu_arch_name
= NULL
;
317 static const char *cpu_sub_arch_name
= NULL
;
319 /* CPU feature flags. */
320 static unsigned int cpu_arch_flags
= CpuUnknownFlags
| CpuNo64
;
322 /* If set, conditional jumps are not automatically promoted to handle
323 larger than a byte offset. */
324 static unsigned int no_cond_jump_promotion
= 0;
326 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
327 static symbolS
*GOT_symbol
;
329 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
330 unsigned int x86_dwarf2_return_column
;
332 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
333 int x86_cie_data_alignment
;
335 /* Interface to relax_segment.
336 There are 3 major relax states for 386 jump insns because the
337 different types of jumps add different sizes to frags when we're
338 figuring out what sort of jump to choose to reach a given label. */
341 #define UNCOND_JUMP 0
343 #define COND_JUMP86 2
348 #define SMALL16 (SMALL | CODE16)
350 #define BIG16 (BIG | CODE16)
354 #define INLINE __inline__
360 #define ENCODE_RELAX_STATE(type, size) \
361 ((relax_substateT) (((type) << 2) | (size)))
362 #define TYPE_FROM_RELAX_STATE(s) \
364 #define DISP_SIZE_FROM_RELAX_STATE(s) \
365 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
367 /* This table is used by relax_frag to promote short jumps to long
368 ones where necessary. SMALL (short) jumps may be promoted to BIG
369 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
370 don't allow a short jump in a 32 bit code segment to be promoted to
371 a 16 bit offset jump because it's slower (requires data size
372 prefix), and doesn't work, unless the destination is in the bottom
373 64k of the code segment (The top 16 bits of eip are zeroed). */
375 const relax_typeS md_relax_table
[] =
378 1) most positive reach of this state,
379 2) most negative reach of this state,
380 3) how many bytes this mode will have in the variable part of the frag
381 4) which index into the table to try if we can't fit into this one. */
383 /* UNCOND_JUMP states. */
384 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
385 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
386 /* dword jmp adds 4 bytes to frag:
387 0 extra opcode bytes, 4 displacement bytes. */
389 /* word jmp adds 2 byte2 to frag:
390 0 extra opcode bytes, 2 displacement bytes. */
393 /* COND_JUMP states. */
394 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
395 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
396 /* dword conditionals adds 5 bytes to frag:
397 1 extra opcode byte, 4 displacement bytes. */
399 /* word conditionals add 3 bytes to frag:
400 1 extra opcode byte, 2 displacement bytes. */
403 /* COND_JUMP86 states. */
404 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
405 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
406 /* dword conditionals adds 5 bytes to frag:
407 1 extra opcode byte, 4 displacement bytes. */
409 /* word conditionals add 4 bytes to frag:
410 1 displacement byte and a 3 byte long branch insn. */
414 static const arch_entry cpu_arch
[] = {
416 {"i186", Cpu086
|Cpu186
},
417 {"i286", Cpu086
|Cpu186
|Cpu286
},
418 {"i386", Cpu086
|Cpu186
|Cpu286
|Cpu386
},
419 {"i486", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
},
420 {"i586", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
},
421 {"i686", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
},
422 {"pentium", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
},
423 {"pentiumpro",Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
},
424 {"pentiumii", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuMMX
},
425 {"pentiumiii",Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuMMX
|CpuMMX2
|CpuSSE
},
426 {"pentium4", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuP4
|CpuMMX
|CpuMMX2
|CpuSSE
|CpuSSE2
},
427 {"prescott", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuP4
|CpuMMX
|CpuMMX2
|CpuSSE
|CpuSSE2
|CpuPNI
},
428 {"k6", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|CpuK6
|CpuMMX
},
429 {"k6_2", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|CpuK6
|CpuMMX
|Cpu3dnow
},
430 {"athlon", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuK6
|CpuAthlon
|CpuMMX
|CpuMMX2
|Cpu3dnow
|Cpu3dnowA
},
431 {"sledgehammer",Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuK6
|CpuAthlon
|CpuSledgehammer
|CpuMMX
|CpuMMX2
|Cpu3dnow
|Cpu3dnowA
|CpuSSE
|CpuSSE2
},
432 {"opteron", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuK6
|CpuAthlon
|CpuSledgehammer
|CpuMMX
|CpuMMX2
|Cpu3dnow
|Cpu3dnowA
|CpuSSE
|CpuSSE2
},
434 {".sse", CpuMMX
|CpuMMX2
|CpuSSE
},
435 {".sse2", CpuMMX
|CpuMMX2
|CpuSSE
|CpuSSE2
},
436 {".sse3", CpuMMX
|CpuMMX2
|CpuSSE
|CpuSSE2
|CpuSSE3
},
437 {".3dnow", CpuMMX
|Cpu3dnow
},
438 {".3dnowa", CpuMMX
|CpuMMX2
|Cpu3dnow
|Cpu3dnowA
},
439 {".padlock", CpuPadLock
},
440 {".pacifica", CpuSVME
},
445 const pseudo_typeS md_pseudo_table
[] =
447 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
448 {"align", s_align_bytes
, 0},
450 {"align", s_align_ptwo
, 0},
452 {"arch", set_cpu_arch
, 0},
456 {"ffloat", float_cons
, 'f'},
457 {"dfloat", float_cons
, 'd'},
458 {"tfloat", float_cons
, 'x'},
460 {"noopt", s_ignore
, 0},
461 {"optim", s_ignore
, 0},
462 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
463 {"code16", set_code_flag
, CODE_16BIT
},
464 {"code32", set_code_flag
, CODE_32BIT
},
465 {"code64", set_code_flag
, CODE_64BIT
},
466 {"intel_syntax", set_intel_syntax
, 1},
467 {"att_syntax", set_intel_syntax
, 0},
468 {"file", (void (*) PARAMS ((int))) dwarf2_directive_file
, 0},
469 {"loc", dwarf2_directive_loc
, 0},
471 {"secrel32", pe_directive_secrel
, 0},
476 /* For interface with expression (). */
477 extern char *input_line_pointer
;
479 /* Hash table for instruction mnemonic lookup. */
480 static struct hash_control
*op_hash
;
482 /* Hash table for register lookup. */
483 static struct hash_control
*reg_hash
;
486 i386_align_code (fragP
, count
)
490 /* Various efficient no-op patterns for aligning code labels.
491 Note: Don't try to assemble the instructions in the comments.
492 0L and 0w are not legal. */
493 static const char f32_1
[] =
495 static const char f32_2
[] =
496 {0x89,0xf6}; /* movl %esi,%esi */
497 static const char f32_3
[] =
498 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
499 static const char f32_4
[] =
500 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
501 static const char f32_5
[] =
503 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
504 static const char f32_6
[] =
505 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
506 static const char f32_7
[] =
507 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
508 static const char f32_8
[] =
510 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
511 static const char f32_9
[] =
512 {0x89,0xf6, /* movl %esi,%esi */
513 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
514 static const char f32_10
[] =
515 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
516 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
517 static const char f32_11
[] =
518 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
519 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
520 static const char f32_12
[] =
521 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
522 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
523 static const char f32_13
[] =
524 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
525 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
526 static const char f32_14
[] =
527 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
528 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
529 static const char f32_15
[] =
530 {0xeb,0x0d,0x90,0x90,0x90,0x90,0x90, /* jmp .+15; lotsa nops */
531 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
532 static const char f16_3
[] =
533 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
534 static const char f16_4
[] =
535 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
536 static const char f16_5
[] =
538 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
539 static const char f16_6
[] =
540 {0x89,0xf6, /* mov %si,%si */
541 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
542 static const char f16_7
[] =
543 {0x8d,0x74,0x00, /* lea 0(%si),%si */
544 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
545 static const char f16_8
[] =
546 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
547 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
548 static const char *const f32_patt
[] = {
549 f32_1
, f32_2
, f32_3
, f32_4
, f32_5
, f32_6
, f32_7
, f32_8
,
550 f32_9
, f32_10
, f32_11
, f32_12
, f32_13
, f32_14
, f32_15
552 static const char *const f16_patt
[] = {
553 f32_1
, f32_2
, f16_3
, f16_4
, f16_5
, f16_6
, f16_7
, f16_8
,
554 f32_15
, f32_15
, f32_15
, f32_15
, f32_15
, f32_15
, f32_15
557 if (count
<= 0 || count
> 15)
560 /* The recommended way to pad 64bit code is to use NOPs preceded by
561 maximally four 0x66 prefixes. Balance the size of nops. */
562 if (flag_code
== CODE_64BIT
)
565 int nnops
= (count
+ 3) / 4;
566 int len
= count
/ nnops
;
567 int remains
= count
- nnops
* len
;
570 for (i
= 0; i
< remains
; i
++)
572 memset (fragP
->fr_literal
+ fragP
->fr_fix
+ pos
, 0x66, len
);
573 fragP
->fr_literal
[fragP
->fr_fix
+ pos
+ len
] = 0x90;
576 for (; i
< nnops
; i
++)
578 memset (fragP
->fr_literal
+ fragP
->fr_fix
+ pos
, 0x66, len
- 1);
579 fragP
->fr_literal
[fragP
->fr_fix
+ pos
+ len
- 1] = 0x90;
584 if (flag_code
== CODE_16BIT
)
586 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
587 f16_patt
[count
- 1], count
);
589 /* Adjust jump offset. */
590 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
593 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
594 f32_patt
[count
- 1], count
);
595 fragP
->fr_var
= count
;
598 static INLINE
unsigned int
599 mode_from_disp_size (t
)
602 return (t
& Disp8
) ? 1 : (t
& (Disp16
| Disp32
| Disp32S
)) ? 2 : 0;
606 fits_in_signed_byte (num
)
609 return (num
>= -128) && (num
<= 127);
613 fits_in_unsigned_byte (num
)
616 return (num
& 0xff) == num
;
620 fits_in_unsigned_word (num
)
623 return (num
& 0xffff) == num
;
627 fits_in_signed_word (num
)
630 return (-32768 <= num
) && (num
<= 32767);
633 fits_in_signed_long (num
)
634 offsetT num ATTRIBUTE_UNUSED
;
639 return (!(((offsetT
) -1 << 31) & num
)
640 || (((offsetT
) -1 << 31) & num
) == ((offsetT
) -1 << 31));
642 } /* fits_in_signed_long() */
644 fits_in_unsigned_long (num
)
645 offsetT num ATTRIBUTE_UNUSED
;
650 return (num
& (((offsetT
) 2 << 31) - 1)) == num
;
652 } /* fits_in_unsigned_long() */
655 smallest_imm_type (num
)
658 if (cpu_arch_flags
!= (Cpu086
| Cpu186
| Cpu286
| Cpu386
| Cpu486
| CpuNo64
))
660 /* This code is disabled on the 486 because all the Imm1 forms
661 in the opcode table are slower on the i486. They're the
662 versions with the implicitly specified single-position
663 displacement, which has another syntax if you really want to
666 return Imm1
| Imm8
| Imm8S
| Imm16
| Imm32
| Imm32S
| Imm64
;
668 return (fits_in_signed_byte (num
)
669 ? (Imm8S
| Imm8
| Imm16
| Imm32
| Imm32S
| Imm64
)
670 : fits_in_unsigned_byte (num
)
671 ? (Imm8
| Imm16
| Imm32
| Imm32S
| Imm64
)
672 : (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
673 ? (Imm16
| Imm32
| Imm32S
| Imm64
)
674 : fits_in_signed_long (num
)
675 ? (Imm32
| Imm32S
| Imm64
)
676 : fits_in_unsigned_long (num
)
682 offset_in_range (val
, size
)
690 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
691 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
692 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
694 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
699 /* If BFD64, sign extend val. */
700 if (!use_rela_relocations
)
701 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
702 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
704 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
706 char buf1
[40], buf2
[40];
708 sprint_value (buf1
, val
);
709 sprint_value (buf2
, val
& mask
);
710 as_warn (_("%s shortened to %s"), buf1
, buf2
);
715 /* Returns 0 if attempting to add a prefix where one from the same
716 class already exists, 1 if non rep/repne added, 2 if rep/repne
725 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
726 && flag_code
== CODE_64BIT
)
734 case CS_PREFIX_OPCODE
:
735 case DS_PREFIX_OPCODE
:
736 case ES_PREFIX_OPCODE
:
737 case FS_PREFIX_OPCODE
:
738 case GS_PREFIX_OPCODE
:
739 case SS_PREFIX_OPCODE
:
743 case REPNE_PREFIX_OPCODE
:
744 case REPE_PREFIX_OPCODE
:
747 case LOCK_PREFIX_OPCODE
:
755 case ADDR_PREFIX_OPCODE
:
759 case DATA_PREFIX_OPCODE
:
764 if (i
.prefix
[q
] != 0)
766 as_bad (_("same type of prefix used twice"));
771 i
.prefix
[q
] = prefix
;
776 set_code_flag (value
)
780 cpu_arch_flags
&= ~(Cpu64
| CpuNo64
);
781 cpu_arch_flags
|= (flag_code
== CODE_64BIT
? Cpu64
: CpuNo64
);
782 if (value
== CODE_64BIT
&& !(cpu_arch_flags
& CpuSledgehammer
))
784 as_bad (_("64bit mode not supported on this CPU."));
786 if (value
== CODE_32BIT
&& !(cpu_arch_flags
& Cpu386
))
788 as_bad (_("32bit mode not supported on this CPU."));
794 set_16bit_gcc_code_flag (new_code_flag
)
797 flag_code
= new_code_flag
;
798 cpu_arch_flags
&= ~(Cpu64
| CpuNo64
);
799 cpu_arch_flags
|= (flag_code
== CODE_64BIT
? Cpu64
: CpuNo64
);
800 stackop_size
= LONG_MNEM_SUFFIX
;
804 set_intel_syntax (syntax_flag
)
807 /* Find out if register prefixing is specified. */
808 int ask_naked_reg
= 0;
811 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
813 char *string
= input_line_pointer
;
814 int e
= get_symbol_end ();
816 if (strcmp (string
, "prefix") == 0)
818 else if (strcmp (string
, "noprefix") == 0)
821 as_bad (_("bad argument to syntax directive."));
822 *input_line_pointer
= e
;
824 demand_empty_rest_of_line ();
826 intel_syntax
= syntax_flag
;
828 if (ask_naked_reg
== 0)
829 allow_naked_reg
= (intel_syntax
830 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
832 allow_naked_reg
= (ask_naked_reg
< 0);
834 identifier_chars
['%'] = intel_syntax
&& allow_naked_reg
? '%' : 0;
835 identifier_chars
['$'] = intel_syntax
? '$' : 0;
840 int dummy ATTRIBUTE_UNUSED
;
844 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
846 char *string
= input_line_pointer
;
847 int e
= get_symbol_end ();
850 for (i
= 0; cpu_arch
[i
].name
; i
++)
852 if (strcmp (string
, cpu_arch
[i
].name
) == 0)
856 cpu_arch_name
= cpu_arch
[i
].name
;
857 cpu_sub_arch_name
= NULL
;
858 cpu_arch_flags
= (cpu_arch
[i
].flags
859 | (flag_code
== CODE_64BIT
? Cpu64
: CpuNo64
));
862 if ((cpu_arch_flags
| cpu_arch
[i
].flags
) != cpu_arch_flags
)
864 cpu_sub_arch_name
= cpu_arch
[i
].name
;
865 cpu_arch_flags
|= cpu_arch
[i
].flags
;
867 *input_line_pointer
= e
;
868 demand_empty_rest_of_line ();
872 if (!cpu_arch
[i
].name
)
873 as_bad (_("no such architecture: `%s'"), string
);
875 *input_line_pointer
= e
;
878 as_bad (_("missing cpu architecture"));
880 no_cond_jump_promotion
= 0;
881 if (*input_line_pointer
== ','
882 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
884 char *string
= ++input_line_pointer
;
885 int e
= get_symbol_end ();
887 if (strcmp (string
, "nojumps") == 0)
888 no_cond_jump_promotion
= 1;
889 else if (strcmp (string
, "jumps") == 0)
892 as_bad (_("no such architecture modifier: `%s'"), string
);
894 *input_line_pointer
= e
;
897 demand_empty_rest_of_line ();
903 if (!strcmp (default_arch
, "x86_64"))
904 return bfd_mach_x86_64
;
905 else if (!strcmp (default_arch
, "i386"))
906 return bfd_mach_i386_i386
;
908 as_fatal (_("Unknown architecture"));
914 const char *hash_err
;
916 /* Initialize op_hash hash table. */
917 op_hash
= hash_new ();
920 const template *optab
;
921 templates
*core_optab
;
923 /* Setup for loop. */
925 core_optab
= (templates
*) xmalloc (sizeof (templates
));
926 core_optab
->start
= optab
;
931 if (optab
->name
== NULL
932 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
934 /* different name --> ship out current template list;
935 add to hash table; & begin anew. */
936 core_optab
->end
= optab
;
937 hash_err
= hash_insert (op_hash
,
942 as_fatal (_("Internal Error: Can't hash %s: %s"),
946 if (optab
->name
== NULL
)
948 core_optab
= (templates
*) xmalloc (sizeof (templates
));
949 core_optab
->start
= optab
;
954 /* Initialize reg_hash hash table. */
955 reg_hash
= hash_new ();
957 const reg_entry
*regtab
;
959 for (regtab
= i386_regtab
;
960 regtab
< i386_regtab
+ sizeof (i386_regtab
) / sizeof (i386_regtab
[0]);
963 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (PTR
) regtab
);
965 as_fatal (_("Internal Error: Can't hash %s: %s"),
971 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
976 for (c
= 0; c
< 256; c
++)
981 mnemonic_chars
[c
] = c
;
982 register_chars
[c
] = c
;
983 operand_chars
[c
] = c
;
985 else if (ISLOWER (c
))
987 mnemonic_chars
[c
] = c
;
988 register_chars
[c
] = c
;
989 operand_chars
[c
] = c
;
991 else if (ISUPPER (c
))
993 mnemonic_chars
[c
] = TOLOWER (c
);
994 register_chars
[c
] = mnemonic_chars
[c
];
995 operand_chars
[c
] = c
;
998 if (ISALPHA (c
) || ISDIGIT (c
))
999 identifier_chars
[c
] = c
;
1002 identifier_chars
[c
] = c
;
1003 operand_chars
[c
] = c
;
1008 identifier_chars
['@'] = '@';
1011 identifier_chars
['?'] = '?';
1012 operand_chars
['?'] = '?';
1014 digit_chars
['-'] = '-';
1015 mnemonic_chars
['-'] = '-';
1016 identifier_chars
['_'] = '_';
1017 identifier_chars
['.'] = '.';
1019 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
1020 operand_chars
[(unsigned char) *p
] = *p
;
1023 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1024 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
1026 record_alignment (text_section
, 2);
1027 record_alignment (data_section
, 2);
1028 record_alignment (bss_section
, 2);
1032 if (flag_code
== CODE_64BIT
)
1034 x86_dwarf2_return_column
= 16;
1035 x86_cie_data_alignment
= -8;
1039 x86_dwarf2_return_column
= 8;
1040 x86_cie_data_alignment
= -4;
1045 i386_print_statistics (file
)
1048 hash_print_statistics (file
, "i386 opcode", op_hash
);
1049 hash_print_statistics (file
, "i386 register", reg_hash
);
1054 /* Debugging routines for md_assemble. */
1055 static void pi
PARAMS ((char *, i386_insn
*));
1056 static void pte
PARAMS ((template *));
1057 static void pt
PARAMS ((unsigned int));
1058 static void pe
PARAMS ((expressionS
*));
1059 static void ps
PARAMS ((symbolS
*));
1068 fprintf (stdout
, "%s: template ", line
);
1070 fprintf (stdout
, " address: base %s index %s scale %x\n",
1071 x
->base_reg
? x
->base_reg
->reg_name
: "none",
1072 x
->index_reg
? x
->index_reg
->reg_name
: "none",
1073 x
->log2_scale_factor
);
1074 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
1075 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
1076 fprintf (stdout
, " sib: base %x index %x scale %x\n",
1077 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
1078 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
1079 (x
->rex
& REX_MODE64
) != 0,
1080 (x
->rex
& REX_EXTX
) != 0,
1081 (x
->rex
& REX_EXTY
) != 0,
1082 (x
->rex
& REX_EXTZ
) != 0);
1083 for (i
= 0; i
< x
->operands
; i
++)
1085 fprintf (stdout
, " #%d: ", i
+ 1);
1087 fprintf (stdout
, "\n");
1089 & (Reg
| SReg2
| SReg3
| Control
| Debug
| Test
| RegMMX
| RegXMM
))
1090 fprintf (stdout
, "%s\n", x
->op
[i
].regs
->reg_name
);
1091 if (x
->types
[i
] & Imm
)
1093 if (x
->types
[i
] & Disp
)
1094 pe (x
->op
[i
].disps
);
1103 fprintf (stdout
, " %d operands ", t
->operands
);
1104 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
1105 if (t
->extension_opcode
!= None
)
1106 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
1107 if (t
->opcode_modifier
& D
)
1108 fprintf (stdout
, "D");
1109 if (t
->opcode_modifier
& W
)
1110 fprintf (stdout
, "W");
1111 fprintf (stdout
, "\n");
1112 for (i
= 0; i
< t
->operands
; i
++)
1114 fprintf (stdout
, " #%d type ", i
+ 1);
1115 pt (t
->operand_types
[i
]);
1116 fprintf (stdout
, "\n");
1124 fprintf (stdout
, " operation %d\n", e
->X_op
);
1125 fprintf (stdout
, " add_number %ld (%lx)\n",
1126 (long) e
->X_add_number
, (long) e
->X_add_number
);
1127 if (e
->X_add_symbol
)
1129 fprintf (stdout
, " add_symbol ");
1130 ps (e
->X_add_symbol
);
1131 fprintf (stdout
, "\n");
1135 fprintf (stdout
, " op_symbol ");
1136 ps (e
->X_op_symbol
);
1137 fprintf (stdout
, "\n");
1145 fprintf (stdout
, "%s type %s%s",
1147 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
1148 segment_name (S_GET_SEGMENT (s
)));
1157 static const type_names
[] =
1170 { BaseIndex
, "BaseIndex" },
1174 { Disp32S
, "d32s" },
1176 { InOutPortReg
, "InOutPortReg" },
1177 { ShiftCount
, "ShiftCount" },
1178 { Control
, "control reg" },
1179 { Test
, "test reg" },
1180 { Debug
, "debug reg" },
1181 { FloatReg
, "FReg" },
1182 { FloatAcc
, "FAcc" },
1186 { JumpAbsolute
, "Jump Absolute" },
1197 const struct type_name
*ty
;
1199 for (ty
= type_names
; ty
->mask
; ty
++)
1201 fprintf (stdout
, "%s, ", ty
->tname
);
1205 #endif /* DEBUG386 */
1207 static bfd_reloc_code_real_type
1208 reloc (unsigned int size
,
1211 bfd_reloc_code_real_type other
)
1213 if (other
!= NO_RELOC
)
1215 reloc_howto_type
*reloc
;
1220 case BFD_RELOC_X86_64_TPOFF32
:
1221 other
= BFD_RELOC_X86_64_TPOFF64
;
1223 case BFD_RELOC_X86_64_DTPOFF32
:
1224 other
= BFD_RELOC_X86_64_DTPOFF64
;
1229 reloc
= bfd_reloc_type_lookup (stdoutput
, other
);
1231 as_bad (_("unknown relocation (%u)"), other
);
1232 else if (size
!= bfd_get_reloc_size (reloc
))
1233 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
1234 bfd_get_reloc_size (reloc
),
1236 else if (pcrel
&& !reloc
->pc_relative
)
1237 as_bad (_("non-pc-relative relocation for pc-relative field"));
1238 else if ((reloc
->complain_on_overflow
== complain_overflow_signed
1240 || (reloc
->complain_on_overflow
== complain_overflow_unsigned
1242 as_bad (_("relocated field and relocation type differ in signedness"));
1251 as_bad (_("there are no unsigned pc-relative relocations"));
1254 case 1: return BFD_RELOC_8_PCREL
;
1255 case 2: return BFD_RELOC_16_PCREL
;
1256 case 4: return BFD_RELOC_32_PCREL
;
1257 case 8: return BFD_RELOC_64_PCREL
;
1259 as_bad (_("cannot do %u byte pc-relative relocation"), size
);
1266 case 4: return BFD_RELOC_X86_64_32S
;
1271 case 1: return BFD_RELOC_8
;
1272 case 2: return BFD_RELOC_16
;
1273 case 4: return BFD_RELOC_32
;
1274 case 8: return BFD_RELOC_64
;
1276 as_bad (_("cannot do %s %u byte relocation"),
1277 sign
> 0 ? "signed" : "unsigned", size
);
1281 return BFD_RELOC_NONE
;
1284 /* Here we decide which fixups can be adjusted to make them relative to
1285 the beginning of the section instead of the symbol. Basically we need
1286 to make sure that the dynamic relocations are done correctly, so in
1287 some cases we force the original symbol to be used. */
1290 tc_i386_fix_adjustable (fixP
)
1291 fixS
*fixP ATTRIBUTE_UNUSED
;
1293 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1294 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
1297 /* Don't adjust pc-relative references to merge sections in 64-bit
1299 if (use_rela_relocations
1300 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
1304 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
1305 and changed later by validate_fix. */
1306 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
1307 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
1310 /* adjust_reloc_syms doesn't know about the GOT. */
1311 if (fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
1312 || fixP
->fx_r_type
== BFD_RELOC_386_PLT32
1313 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
1314 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
1315 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
1316 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
1317 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
1318 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
1319 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
1320 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
1321 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
1322 || fixP
->fx_r_type
== BFD_RELOC_X86_64_PLT32
1323 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
1324 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
1325 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
1326 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
1327 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
1328 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
1329 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
1330 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
1331 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
1332 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
1333 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
1334 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
1340 static int intel_float_operand
PARAMS ((const char *mnemonic
));
1343 intel_float_operand (mnemonic
)
1344 const char *mnemonic
;
1346 /* Note that the value returned is meaningful only for opcodes with (memory)
1347 operands, hence the code here is free to improperly handle opcodes that
1348 have no operands (for better performance and smaller code). */
1350 if (mnemonic
[0] != 'f')
1351 return 0; /* non-math */
1353 switch (mnemonic
[1])
1355 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
1356 the fs segment override prefix not currently handled because no
1357 call path can make opcodes without operands get here */
1359 return 2 /* integer op */;
1361 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
1362 return 3; /* fldcw/fldenv */
1365 if (mnemonic
[2] != 'o' /* fnop */)
1366 return 3; /* non-waiting control op */
1369 if (mnemonic
[2] == 's')
1370 return 3; /* frstor/frstpm */
1373 if (mnemonic
[2] == 'a')
1374 return 3; /* fsave */
1375 if (mnemonic
[2] == 't')
1377 switch (mnemonic
[3])
1379 case 'c': /* fstcw */
1380 case 'd': /* fstdw */
1381 case 'e': /* fstenv */
1382 case 's': /* fsts[gw] */
1388 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
1389 return 0; /* fxsave/fxrstor are not really math ops */
1396 /* This is the guts of the machine-dependent assembler. LINE points to a
1397 machine dependent instruction. This function is supposed to emit
1398 the frags/bytes it assembles to. */
1405 char mnemonic
[MAX_MNEM_SIZE
];
1407 /* Initialize globals. */
1408 memset (&i
, '\0', sizeof (i
));
1409 for (j
= 0; j
< MAX_OPERANDS
; j
++)
1410 i
.reloc
[j
] = NO_RELOC
;
1411 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
1412 memset (im_expressions
, '\0', sizeof (im_expressions
));
1413 save_stack_p
= save_stack
;
1415 /* First parse an instruction mnemonic & call i386_operand for the operands.
1416 We assume that the scrubber has arranged it so that line[0] is the valid
1417 start of a (possibly prefixed) mnemonic. */
1419 line
= parse_insn (line
, mnemonic
);
1423 line
= parse_operands (line
, mnemonic
);
1427 /* Now we've parsed the mnemonic into a set of templates, and have the
1428 operands at hand. */
1430 /* All intel opcodes have reversed operands except for "bound" and
1431 "enter". We also don't reverse intersegment "jmp" and "call"
1432 instructions with 2 immediate operands so that the immediate segment
1433 precedes the offset, as it does when in AT&T mode. "enter" and the
1434 intersegment "jmp" and "call" instructions are the only ones that
1435 have two immediate operands. */
1436 if (intel_syntax
&& i
.operands
> 1
1437 && (strcmp (mnemonic
, "bound") != 0)
1438 && (strcmp (mnemonic
, "invlpga") != 0)
1439 && !((i
.types
[0] & Imm
) && (i
.types
[1] & Imm
)))
1445 /* Don't optimize displacement for movabs since it only takes 64bit
1448 && (flag_code
!= CODE_64BIT
1449 || strcmp (mnemonic
, "movabs") != 0))
1452 /* Next, we find a template that matches the given insn,
1453 making sure the overlap of the given operands types is consistent
1454 with the template operand types. */
1456 if (!match_template ())
1461 /* Undo SYSV386_COMPAT brokenness when in Intel mode. See i386.h */
1463 && (i
.tm
.base_opcode
& 0xfffffde0) == 0xdce0)
1464 i
.tm
.base_opcode
^= FloatR
;
1466 /* Zap movzx and movsx suffix. The suffix may have been set from
1467 "word ptr" or "byte ptr" on the source operand, but we'll use
1468 the suffix later to choose the destination register. */
1469 if ((i
.tm
.base_opcode
& ~9) == 0x0fb6)
1471 if (i
.reg_operands
< 2
1473 && (~i
.tm
.opcode_modifier
1480 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
1486 if (i
.tm
.opcode_modifier
& FWait
)
1487 if (!add_prefix (FWAIT_OPCODE
))
1490 /* Check string instruction segment overrides. */
1491 if ((i
.tm
.opcode_modifier
& IsString
) != 0 && i
.mem_operands
!= 0)
1493 if (!check_string ())
1497 if (!process_suffix ())
1500 /* Make still unresolved immediate matches conform to size of immediate
1501 given in i.suffix. */
1502 if (!finalize_imm ())
1505 if (i
.types
[0] & Imm1
)
1506 i
.imm_operands
= 0; /* kludge for shift insns. */
1507 if (i
.types
[0] & ImplicitRegister
)
1509 if (i
.types
[1] & ImplicitRegister
)
1511 if (i
.types
[2] & ImplicitRegister
)
1514 if (i
.tm
.opcode_modifier
& ImmExt
)
1518 if ((i
.tm
.cpu_flags
& CpuPNI
) && i
.operands
> 0)
1520 /* These Intel Prescott New Instructions have the fixed
1521 operands with an opcode suffix which is coded in the same
1522 place as an 8-bit immediate field would be. Here we check
1523 those operands and remove them afterwards. */
1526 for (x
= 0; x
< i
.operands
; x
++)
1527 if (i
.op
[x
].regs
->reg_num
!= x
)
1528 as_bad (_("can't use register '%%%s' as operand %d in '%s'."),
1529 i
.op
[x
].regs
->reg_name
, x
+ 1, i
.tm
.name
);
1533 /* These AMD 3DNow! and Intel Katmai New Instructions have an
1534 opcode suffix which is coded in the same place as an 8-bit
1535 immediate field would be. Here we fake an 8-bit immediate
1536 operand from the opcode suffix stored in tm.extension_opcode. */
1538 assert (i
.imm_operands
== 0 && i
.operands
<= 2 && 2 < MAX_OPERANDS
);
1540 exp
= &im_expressions
[i
.imm_operands
++];
1541 i
.op
[i
.operands
].imms
= exp
;
1542 i
.types
[i
.operands
++] = Imm8
;
1543 exp
->X_op
= O_constant
;
1544 exp
->X_add_number
= i
.tm
.extension_opcode
;
1545 i
.tm
.extension_opcode
= None
;
1548 /* For insns with operands there are more diddles to do to the opcode. */
1551 if (!process_operands ())
1554 else if (!quiet_warnings
&& (i
.tm
.opcode_modifier
& Ugh
) != 0)
1556 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
1557 as_warn (_("translating to `%sp'"), i
.tm
.name
);
1560 /* Handle conversion of 'int $3' --> special int3 insn. */
1561 if (i
.tm
.base_opcode
== INT_OPCODE
&& i
.op
[0].imms
->X_add_number
== 3)
1563 i
.tm
.base_opcode
= INT3_OPCODE
;
1567 if ((i
.tm
.opcode_modifier
& (Jump
| JumpByte
| JumpDword
))
1568 && i
.op
[0].disps
->X_op
== O_constant
)
1570 /* Convert "jmp constant" (and "call constant") to a jump (call) to
1571 the absolute address given by the constant. Since ix86 jumps and
1572 calls are pc relative, we need to generate a reloc. */
1573 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
1574 i
.op
[0].disps
->X_op
= O_symbol
;
1577 if ((i
.tm
.opcode_modifier
& Rex64
) != 0)
1578 i
.rex
|= REX_MODE64
;
1580 /* For 8 bit registers we need an empty rex prefix. Also if the
1581 instruction already has a prefix, we need to convert old
1582 registers to new ones. */
1584 if (((i
.types
[0] & Reg8
) != 0
1585 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
1586 || ((i
.types
[1] & Reg8
) != 0
1587 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
1588 || (((i
.types
[0] & Reg8
) != 0 || (i
.types
[1] & Reg8
) != 0)
1593 i
.rex
|= REX_OPCODE
;
1594 for (x
= 0; x
< 2; x
++)
1596 /* Look for 8 bit operand that uses old registers. */
1597 if ((i
.types
[x
] & Reg8
) != 0
1598 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
1600 /* In case it is "hi" register, give up. */
1601 if (i
.op
[x
].regs
->reg_num
> 3)
1602 as_bad (_("can't encode register '%%%s' in an instruction requiring REX prefix."),
1603 i
.op
[x
].regs
->reg_name
);
1605 /* Otherwise it is equivalent to the extended register.
1606 Since the encoding doesn't change this is merely
1607 cosmetic cleanup for debug output. */
1609 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
1615 add_prefix (REX_OPCODE
| i
.rex
);
1617 /* We are ready to output the insn. */
1622 parse_insn (line
, mnemonic
)
1627 char *token_start
= l
;
1632 /* Non-zero if we found a prefix only acceptable with string insns. */
1633 const char *expecting_string_instruction
= NULL
;
1638 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
1641 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
1643 as_bad (_("no such instruction: `%s'"), token_start
);
1648 if (!is_space_char (*l
)
1649 && *l
!= END_OF_INSN
1651 || (*l
!= PREFIX_SEPARATOR
1654 as_bad (_("invalid character %s in mnemonic"),
1655 output_invalid (*l
));
1658 if (token_start
== l
)
1660 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
1661 as_bad (_("expecting prefix; got nothing"));
1663 as_bad (_("expecting mnemonic; got nothing"));
1667 /* Look up instruction (or prefix) via hash table. */
1668 current_templates
= hash_find (op_hash
, mnemonic
);
1670 if (*l
!= END_OF_INSN
1671 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
1672 && current_templates
1673 && (current_templates
->start
->opcode_modifier
& IsPrefix
))
1675 if (current_templates
->start
->cpu_flags
1676 & (flag_code
!= CODE_64BIT
? Cpu64
: CpuNo64
))
1678 as_bad ((flag_code
!= CODE_64BIT
1679 ? _("`%s' is only supported in 64-bit mode")
1680 : _("`%s' is not supported in 64-bit mode")),
1681 current_templates
->start
->name
);
1684 /* If we are in 16-bit mode, do not allow addr16 or data16.
1685 Similarly, in 32-bit mode, do not allow addr32 or data32. */
1686 if ((current_templates
->start
->opcode_modifier
& (Size16
| Size32
))
1687 && flag_code
!= CODE_64BIT
1688 && (((current_templates
->start
->opcode_modifier
& Size32
) != 0)
1689 ^ (flag_code
== CODE_16BIT
)))
1691 as_bad (_("redundant %s prefix"),
1692 current_templates
->start
->name
);
1695 /* Add prefix, checking for repeated prefixes. */
1696 switch (add_prefix (current_templates
->start
->base_opcode
))
1701 expecting_string_instruction
= current_templates
->start
->name
;
1704 /* Skip past PREFIX_SEPARATOR and reset token_start. */
1711 if (!current_templates
)
1713 /* See if we can get a match by trimming off a suffix. */
1716 case WORD_MNEM_SUFFIX
:
1717 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
1718 i
.suffix
= SHORT_MNEM_SUFFIX
;
1720 case BYTE_MNEM_SUFFIX
:
1721 case QWORD_MNEM_SUFFIX
:
1722 i
.suffix
= mnem_p
[-1];
1724 current_templates
= hash_find (op_hash
, mnemonic
);
1726 case SHORT_MNEM_SUFFIX
:
1727 case LONG_MNEM_SUFFIX
:
1730 i
.suffix
= mnem_p
[-1];
1732 current_templates
= hash_find (op_hash
, mnemonic
);
1740 if (intel_float_operand (mnemonic
) == 1)
1741 i
.suffix
= SHORT_MNEM_SUFFIX
;
1743 i
.suffix
= LONG_MNEM_SUFFIX
;
1745 current_templates
= hash_find (op_hash
, mnemonic
);
1749 if (!current_templates
)
1751 as_bad (_("no such instruction: `%s'"), token_start
);
1756 if (current_templates
->start
->opcode_modifier
& (Jump
| JumpByte
))
1758 /* Check for a branch hint. We allow ",pt" and ",pn" for
1759 predict taken and predict not taken respectively.
1760 I'm not sure that branch hints actually do anything on loop
1761 and jcxz insns (JumpByte) for current Pentium4 chips. They
1762 may work in the future and it doesn't hurt to accept them
1764 if (l
[0] == ',' && l
[1] == 'p')
1768 if (!add_prefix (DS_PREFIX_OPCODE
))
1772 else if (l
[2] == 'n')
1774 if (!add_prefix (CS_PREFIX_OPCODE
))
1780 /* Any other comma loses. */
1783 as_bad (_("invalid character %s in mnemonic"),
1784 output_invalid (*l
));
1788 /* Check if instruction is supported on specified architecture. */
1790 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
1792 if (!((t
->cpu_flags
& ~(Cpu64
| CpuNo64
))
1793 & ~(cpu_arch_flags
& ~(Cpu64
| CpuNo64
))))
1795 if (!(t
->cpu_flags
& (flag_code
== CODE_64BIT
? CpuNo64
: Cpu64
)))
1798 if (!(supported
& 2))
1800 as_bad (flag_code
== CODE_64BIT
1801 ? _("`%s' is not supported in 64-bit mode")
1802 : _("`%s' is only supported in 64-bit mode"),
1803 current_templates
->start
->name
);
1806 if (!(supported
& 1))
1808 as_warn (_("`%s' is not supported on `%s%s'"),
1809 current_templates
->start
->name
,
1811 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
1813 else if ((Cpu386
& ~cpu_arch_flags
) && (flag_code
!= CODE_16BIT
))
1815 as_warn (_("use .code16 to ensure correct addressing mode"));
1818 /* Check for rep/repne without a string instruction. */
1819 if (expecting_string_instruction
)
1821 static templates override
;
1823 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
1824 if (t
->opcode_modifier
& IsString
)
1826 if (t
>= current_templates
->end
)
1828 as_bad (_("expecting string instruction after `%s'"),
1829 expecting_string_instruction
);
1832 for (override
.start
= t
; t
< current_templates
->end
; ++t
)
1833 if (!(t
->opcode_modifier
& IsString
))
1836 current_templates
= &override
;
1843 parse_operands (l
, mnemonic
)
1845 const char *mnemonic
;
1849 /* 1 if operand is pending after ','. */
1850 unsigned int expecting_operand
= 0;
1852 /* Non-zero if operand parens not balanced. */
1853 unsigned int paren_not_balanced
;
1855 while (*l
!= END_OF_INSN
)
1857 /* Skip optional white space before operand. */
1858 if (is_space_char (*l
))
1860 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
)
1862 as_bad (_("invalid character %s before operand %d"),
1863 output_invalid (*l
),
1867 token_start
= l
; /* after white space */
1868 paren_not_balanced
= 0;
1869 while (paren_not_balanced
|| *l
!= ',')
1871 if (*l
== END_OF_INSN
)
1873 if (paren_not_balanced
)
1876 as_bad (_("unbalanced parenthesis in operand %d."),
1879 as_bad (_("unbalanced brackets in operand %d."),
1884 break; /* we are done */
1886 else if (!is_operand_char (*l
) && !is_space_char (*l
))
1888 as_bad (_("invalid character %s in operand %d"),
1889 output_invalid (*l
),
1896 ++paren_not_balanced
;
1898 --paren_not_balanced
;
1903 ++paren_not_balanced
;
1905 --paren_not_balanced
;
1909 if (l
!= token_start
)
1910 { /* Yes, we've read in another operand. */
1911 unsigned int operand_ok
;
1912 this_operand
= i
.operands
++;
1913 if (i
.operands
> MAX_OPERANDS
)
1915 as_bad (_("spurious operands; (%d operands/instruction max)"),
1919 /* Now parse operand adding info to 'i' as we go along. */
1920 END_STRING_AND_SAVE (l
);
1924 i386_intel_operand (token_start
,
1925 intel_float_operand (mnemonic
));
1927 operand_ok
= i386_operand (token_start
);
1929 RESTORE_END_STRING (l
);
1935 if (expecting_operand
)
1937 expecting_operand_after_comma
:
1938 as_bad (_("expecting operand after ','; got nothing"));
1943 as_bad (_("expecting operand before ','; got nothing"));
1948 /* Now *l must be either ',' or END_OF_INSN. */
1951 if (*++l
== END_OF_INSN
)
1953 /* Just skip it, if it's \n complain. */
1954 goto expecting_operand_after_comma
;
1956 expecting_operand
= 1;
1965 union i386_op temp_op
;
1966 unsigned int temp_type
;
1967 enum bfd_reloc_code_real temp_reloc
;
1971 if (i
.operands
== 2)
1976 else if (i
.operands
== 3)
1981 temp_type
= i
.types
[xchg2
];
1982 i
.types
[xchg2
] = i
.types
[xchg1
];
1983 i
.types
[xchg1
] = temp_type
;
1984 temp_op
= i
.op
[xchg2
];
1985 i
.op
[xchg2
] = i
.op
[xchg1
];
1986 i
.op
[xchg1
] = temp_op
;
1987 temp_reloc
= i
.reloc
[xchg2
];
1988 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
1989 i
.reloc
[xchg1
] = temp_reloc
;
1991 if (i
.mem_operands
== 2)
1993 const seg_entry
*temp_seg
;
1994 temp_seg
= i
.seg
[0];
1995 i
.seg
[0] = i
.seg
[1];
1996 i
.seg
[1] = temp_seg
;
2000 /* Try to ensure constant immediates are represented in the smallest
2005 char guess_suffix
= 0;
2009 guess_suffix
= i
.suffix
;
2010 else if (i
.reg_operands
)
2012 /* Figure out a suffix from the last register operand specified.
2013 We can't do this properly yet, ie. excluding InOutPortReg,
2014 but the following works for instructions with immediates.
2015 In any case, we can't set i.suffix yet. */
2016 for (op
= i
.operands
; --op
>= 0;)
2017 if (i
.types
[op
] & Reg
)
2019 if (i
.types
[op
] & Reg8
)
2020 guess_suffix
= BYTE_MNEM_SUFFIX
;
2021 else if (i
.types
[op
] & Reg16
)
2022 guess_suffix
= WORD_MNEM_SUFFIX
;
2023 else if (i
.types
[op
] & Reg32
)
2024 guess_suffix
= LONG_MNEM_SUFFIX
;
2025 else if (i
.types
[op
] & Reg64
)
2026 guess_suffix
= QWORD_MNEM_SUFFIX
;
2030 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
2031 guess_suffix
= WORD_MNEM_SUFFIX
;
2033 for (op
= i
.operands
; --op
>= 0;)
2034 if (i
.types
[op
] & Imm
)
2036 switch (i
.op
[op
].imms
->X_op
)
2039 /* If a suffix is given, this operand may be shortened. */
2040 switch (guess_suffix
)
2042 case LONG_MNEM_SUFFIX
:
2043 i
.types
[op
] |= Imm32
| Imm64
;
2045 case WORD_MNEM_SUFFIX
:
2046 i
.types
[op
] |= Imm16
| Imm32S
| Imm32
| Imm64
;
2048 case BYTE_MNEM_SUFFIX
:
2049 i
.types
[op
] |= Imm16
| Imm8
| Imm8S
| Imm32S
| Imm32
| Imm64
;
2053 /* If this operand is at most 16 bits, convert it
2054 to a signed 16 bit number before trying to see
2055 whether it will fit in an even smaller size.
2056 This allows a 16-bit operand such as $0xffe0 to
2057 be recognised as within Imm8S range. */
2058 if ((i
.types
[op
] & Imm16
)
2059 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
2061 i
.op
[op
].imms
->X_add_number
=
2062 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
2064 if ((i
.types
[op
] & Imm32
)
2065 && ((i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1))
2068 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
2069 ^ ((offsetT
) 1 << 31))
2070 - ((offsetT
) 1 << 31));
2072 i
.types
[op
] |= smallest_imm_type (i
.op
[op
].imms
->X_add_number
);
2074 /* We must avoid matching of Imm32 templates when 64bit
2075 only immediate is available. */
2076 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
2077 i
.types
[op
] &= ~Imm32
;
2084 /* Symbols and expressions. */
2086 /* Convert symbolic operand to proper sizes for matching. */
2087 switch (guess_suffix
)
2089 case QWORD_MNEM_SUFFIX
:
2090 i
.types
[op
] &= Imm64
| Imm32S
;
2092 case LONG_MNEM_SUFFIX
:
2093 i
.types
[op
] &= Imm32
;
2095 case WORD_MNEM_SUFFIX
:
2096 i
.types
[op
] &= Imm16
;
2098 case BYTE_MNEM_SUFFIX
:
2099 i
.types
[op
] &= Imm8
| Imm8S
;
2107 /* Try to use the smallest displacement type too. */
2113 for (op
= i
.operands
; --op
>= 0;)
2114 if (i
.types
[op
] & Disp
)
2116 if (i
.op
[op
].disps
->X_op
== O_constant
)
2118 offsetT disp
= i
.op
[op
].disps
->X_add_number
;
2120 if ((i
.types
[op
] & Disp16
)
2121 && (disp
& ~(offsetT
) 0xffff) == 0)
2123 /* If this operand is at most 16 bits, convert
2124 to a signed 16 bit number and don't use 64bit
2126 disp
= (((disp
& 0xffff) ^ 0x8000) - 0x8000);
2127 i
.types
[op
] &= ~Disp64
;
2129 if ((i
.types
[op
] & Disp32
)
2130 && (disp
& ~(((offsetT
) 2 << 31) - 1)) == 0)
2132 /* If this operand is at most 32 bits, convert
2133 to a signed 32 bit number and don't use 64bit
2135 disp
&= (((offsetT
) 2 << 31) - 1);
2136 disp
= (disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
2137 i
.types
[op
] &= ~Disp64
;
2139 if (!disp
&& (i
.types
[op
] & BaseIndex
))
2141 i
.types
[op
] &= ~Disp
;
2145 else if (flag_code
== CODE_64BIT
)
2147 if (fits_in_signed_long (disp
))
2149 i
.types
[op
] &= ~Disp64
;
2150 i
.types
[op
] |= Disp32S
;
2152 if (fits_in_unsigned_long (disp
))
2153 i
.types
[op
] |= Disp32
;
2155 if ((i
.types
[op
] & (Disp32
| Disp32S
| Disp16
))
2156 && fits_in_signed_byte (disp
))
2157 i
.types
[op
] |= Disp8
;
2160 /* We only support 64bit displacement on constants. */
2161 i
.types
[op
] &= ~Disp64
;
2168 /* Points to template once we've found it. */
2170 unsigned int overlap0
, overlap1
, overlap2
;
2171 unsigned int found_reverse_match
;
2174 #define MATCH(overlap, given, template) \
2175 ((overlap & ~JumpAbsolute) \
2176 && (((given) & (BaseIndex | JumpAbsolute)) \
2177 == ((overlap) & (BaseIndex | JumpAbsolute))))
2179 /* If given types r0 and r1 are registers they must be of the same type
2180 unless the expected operand type register overlap is null.
2181 Note that Acc in a template matches every size of reg. */
2182 #define CONSISTENT_REGISTER_MATCH(m0, g0, t0, m1, g1, t1) \
2183 (((g0) & Reg) == 0 || ((g1) & Reg) == 0 \
2184 || ((g0) & Reg) == ((g1) & Reg) \
2185 || ((((m0) & Acc) ? Reg : (t0)) & (((m1) & Acc) ? Reg : (t1)) & Reg) == 0 )
2190 found_reverse_match
= 0;
2191 suffix_check
= (i
.suffix
== BYTE_MNEM_SUFFIX
2193 : (i
.suffix
== WORD_MNEM_SUFFIX
2195 : (i
.suffix
== SHORT_MNEM_SUFFIX
2197 : (i
.suffix
== LONG_MNEM_SUFFIX
2199 : (i
.suffix
== QWORD_MNEM_SUFFIX
2201 : (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
2202 ? No_xSuf
: 0))))));
2204 t
= current_templates
->start
;
2205 if (i
.suffix
== QWORD_MNEM_SUFFIX
2206 && flag_code
!= CODE_64BIT
2208 ? !(t
->opcode_modifier
& IgnoreSize
)
2209 && !intel_float_operand (t
->name
)
2210 : intel_float_operand (t
->name
) != 2)
2211 && (!(t
->operand_types
[0] & (RegMMX
| RegXMM
))
2212 || !(t
->operand_types
[t
->operands
> 1] & (RegMMX
| RegXMM
)))
2213 && (t
->base_opcode
!= 0x0fc7
2214 || t
->extension_opcode
!= 1 /* cmpxchg8b */))
2215 t
= current_templates
->end
;
2216 for (; t
< current_templates
->end
; t
++)
2218 /* Must have right number of operands. */
2219 if (i
.operands
!= t
->operands
)
2222 /* Check the suffix, except for some instructions in intel mode. */
2223 if ((t
->opcode_modifier
& suffix_check
)
2225 && (t
->opcode_modifier
& IgnoreSize
)))
2228 /* Do not verify operands when there are none. */
2229 else if (!t
->operands
)
2231 if (t
->cpu_flags
& ~cpu_arch_flags
)
2233 /* We've found a match; break out of loop. */
2237 overlap0
= i
.types
[0] & t
->operand_types
[0];
2238 switch (t
->operands
)
2241 if (!MATCH (overlap0
, i
.types
[0], t
->operand_types
[0]))
2246 overlap1
= i
.types
[1] & t
->operand_types
[1];
2247 if (!MATCH (overlap0
, i
.types
[0], t
->operand_types
[0])
2248 || !MATCH (overlap1
, i
.types
[1], t
->operand_types
[1])
2249 || !CONSISTENT_REGISTER_MATCH (overlap0
, i
.types
[0],
2250 t
->operand_types
[0],
2251 overlap1
, i
.types
[1],
2252 t
->operand_types
[1]))
2254 /* Check if other direction is valid ... */
2255 if ((t
->opcode_modifier
& (D
| FloatD
)) == 0)
2258 /* Try reversing direction of operands. */
2259 overlap0
= i
.types
[0] & t
->operand_types
[1];
2260 overlap1
= i
.types
[1] & t
->operand_types
[0];
2261 if (!MATCH (overlap0
, i
.types
[0], t
->operand_types
[1])
2262 || !MATCH (overlap1
, i
.types
[1], t
->operand_types
[0])
2263 || !CONSISTENT_REGISTER_MATCH (overlap0
, i
.types
[0],
2264 t
->operand_types
[1],
2265 overlap1
, i
.types
[1],
2266 t
->operand_types
[0]))
2268 /* Does not match either direction. */
2271 /* found_reverse_match holds which of D or FloatDR
2273 found_reverse_match
= t
->opcode_modifier
& (D
| FloatDR
);
2275 /* Found a forward 2 operand match here. */
2276 else if (t
->operands
== 3)
2278 /* Here we make use of the fact that there are no
2279 reverse match 3 operand instructions, and all 3
2280 operand instructions only need to be checked for
2281 register consistency between operands 2 and 3. */
2282 overlap2
= i
.types
[2] & t
->operand_types
[2];
2283 if (!MATCH (overlap2
, i
.types
[2], t
->operand_types
[2])
2284 || !CONSISTENT_REGISTER_MATCH (overlap1
, i
.types
[1],
2285 t
->operand_types
[1],
2286 overlap2
, i
.types
[2],
2287 t
->operand_types
[2]))
2291 /* Found either forward/reverse 2 or 3 operand match here:
2292 slip through to break. */
2294 if (t
->cpu_flags
& ~cpu_arch_flags
)
2296 found_reverse_match
= 0;
2299 /* We've found a match; break out of loop. */
2303 if (t
== current_templates
->end
)
2305 /* We found no match. */
2306 as_bad (_("suffix or operands invalid for `%s'"),
2307 current_templates
->start
->name
);
2311 if (!quiet_warnings
)
2314 && ((i
.types
[0] & JumpAbsolute
)
2315 != (t
->operand_types
[0] & JumpAbsolute
)))
2317 as_warn (_("indirect %s without `*'"), t
->name
);
2320 if ((t
->opcode_modifier
& (IsPrefix
| IgnoreSize
))
2321 == (IsPrefix
| IgnoreSize
))
2323 /* Warn them that a data or address size prefix doesn't
2324 affect assembly of the next line of code. */
2325 as_warn (_("stand-alone `%s' prefix"), t
->name
);
2329 /* Copy the template we found. */
2331 if (found_reverse_match
)
2333 /* If we found a reverse match we must alter the opcode
2334 direction bit. found_reverse_match holds bits to change
2335 (different for int & float insns). */
2337 i
.tm
.base_opcode
^= found_reverse_match
;
2339 i
.tm
.operand_types
[0] = t
->operand_types
[1];
2340 i
.tm
.operand_types
[1] = t
->operand_types
[0];
2349 int mem_op
= (i
.types
[0] & AnyMem
) ? 0 : 1;
2350 if ((i
.tm
.operand_types
[mem_op
] & EsSeg
) != 0)
2352 if (i
.seg
[0] != NULL
&& i
.seg
[0] != &es
)
2354 as_bad (_("`%s' operand %d must use `%%es' segment"),
2359 /* There's only ever one segment override allowed per instruction.
2360 This instruction possibly has a legal segment override on the
2361 second operand, so copy the segment to where non-string
2362 instructions store it, allowing common code. */
2363 i
.seg
[0] = i
.seg
[1];
2365 else if ((i
.tm
.operand_types
[mem_op
+ 1] & EsSeg
) != 0)
2367 if (i
.seg
[1] != NULL
&& i
.seg
[1] != &es
)
2369 as_bad (_("`%s' operand %d must use `%%es' segment"),
2379 process_suffix (void)
2381 /* If matched instruction specifies an explicit instruction mnemonic
2383 if (i
.tm
.opcode_modifier
& (Size16
| Size32
| Size64
))
2385 if (i
.tm
.opcode_modifier
& Size16
)
2386 i
.suffix
= WORD_MNEM_SUFFIX
;
2387 else if (i
.tm
.opcode_modifier
& Size64
)
2388 i
.suffix
= QWORD_MNEM_SUFFIX
;
2390 i
.suffix
= LONG_MNEM_SUFFIX
;
2392 else if (i
.reg_operands
)
2394 /* If there's no instruction mnemonic suffix we try to invent one
2395 based on register operands. */
2398 /* We take i.suffix from the last register operand specified,
2399 Destination register type is more significant than source
2403 for (op
= i
.operands
; --op
>= 0;)
2404 if ((i
.types
[op
] & Reg
)
2405 && !(i
.tm
.operand_types
[op
] & InOutPortReg
))
2407 i
.suffix
= ((i
.types
[op
] & Reg8
) ? BYTE_MNEM_SUFFIX
:
2408 (i
.types
[op
] & Reg16
) ? WORD_MNEM_SUFFIX
:
2409 (i
.types
[op
] & Reg64
) ? QWORD_MNEM_SUFFIX
:
2414 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
2416 if (!check_byte_reg ())
2419 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
2421 if (!check_long_reg ())
2424 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
2426 if (!check_qword_reg ())
2429 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
2431 if (!check_word_reg ())
2434 else if (intel_syntax
&& (i
.tm
.opcode_modifier
& IgnoreSize
))
2435 /* Do nothing if the instruction is going to ignore the prefix. */
2440 else if ((i
.tm
.opcode_modifier
& DefaultSize
)
2442 /* exclude fldenv/frstor/fsave/fstenv */
2443 && (i
.tm
.opcode_modifier
& No_sSuf
))
2445 i
.suffix
= stackop_size
;
2447 else if (intel_syntax
2449 && ((i
.tm
.operand_types
[0] & JumpAbsolute
)
2450 || (i
.tm
.opcode_modifier
& (JumpByte
|JumpInterSegment
))
2451 || (i
.tm
.base_opcode
== 0x0f01 /* [ls][gi]dt */
2452 && i
.tm
.extension_opcode
<= 3)))
2457 if (!(i
.tm
.opcode_modifier
& No_qSuf
))
2459 i
.suffix
= QWORD_MNEM_SUFFIX
;
2463 if (!(i
.tm
.opcode_modifier
& No_lSuf
))
2464 i
.suffix
= LONG_MNEM_SUFFIX
;
2467 if (!(i
.tm
.opcode_modifier
& No_wSuf
))
2468 i
.suffix
= WORD_MNEM_SUFFIX
;
2477 if (i
.tm
.opcode_modifier
& W
)
2479 as_bad (_("no instruction mnemonic suffix given and no register operands; can't size instruction"));
2485 unsigned int suffixes
= ~i
.tm
.opcode_modifier
2493 if ((i
.tm
.opcode_modifier
& W
)
2494 || ((suffixes
& (suffixes
- 1))
2495 && !(i
.tm
.opcode_modifier
& (DefaultSize
| IgnoreSize
))))
2497 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
2503 /* Change the opcode based on the operand size given by i.suffix;
2504 We don't need to change things for byte insns. */
2506 if (i
.suffix
&& i
.suffix
!= BYTE_MNEM_SUFFIX
)
2508 /* It's not a byte, select word/dword operation. */
2509 if (i
.tm
.opcode_modifier
& W
)
2511 if (i
.tm
.opcode_modifier
& ShortForm
)
2512 i
.tm
.base_opcode
|= 8;
2514 i
.tm
.base_opcode
|= 1;
2517 /* Now select between word & dword operations via the operand
2518 size prefix, except for instructions that will ignore this
2520 if (i
.suffix
!= QWORD_MNEM_SUFFIX
2521 && i
.suffix
!= LONG_DOUBLE_MNEM_SUFFIX
2522 && !(i
.tm
.opcode_modifier
& (IgnoreSize
| FloatMF
))
2523 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
2524 || (flag_code
== CODE_64BIT
2525 && (i
.tm
.opcode_modifier
& JumpByte
))))
2527 unsigned int prefix
= DATA_PREFIX_OPCODE
;
2529 if (i
.tm
.opcode_modifier
& JumpByte
) /* jcxz, loop */
2530 prefix
= ADDR_PREFIX_OPCODE
;
2532 if (!add_prefix (prefix
))
2536 /* Set mode64 for an operand. */
2537 if (i
.suffix
== QWORD_MNEM_SUFFIX
2538 && flag_code
== CODE_64BIT
2539 && (i
.tm
.opcode_modifier
& NoRex64
) == 0)
2540 i
.rex
|= REX_MODE64
;
2542 /* Size floating point instruction. */
2543 if (i
.suffix
== LONG_MNEM_SUFFIX
)
2544 if (i
.tm
.opcode_modifier
& FloatMF
)
2545 i
.tm
.base_opcode
^= 4;
2552 check_byte_reg (void)
2556 for (op
= i
.operands
; --op
>= 0;)
2558 /* If this is an eight bit register, it's OK. If it's the 16 or
2559 32 bit version of an eight bit register, we will just use the
2560 low portion, and that's OK too. */
2561 if (i
.types
[op
] & Reg8
)
2564 /* movzx and movsx should not generate this warning. */
2566 && (i
.tm
.base_opcode
== 0xfb7
2567 || i
.tm
.base_opcode
== 0xfb6
2568 || i
.tm
.base_opcode
== 0x63
2569 || i
.tm
.base_opcode
== 0xfbe
2570 || i
.tm
.base_opcode
== 0xfbf))
2573 if ((i
.types
[op
] & WordReg
) && i
.op
[op
].regs
->reg_num
< 4)
2575 /* Prohibit these changes in the 64bit mode, since the
2576 lowering is more complicated. */
2577 if (flag_code
== CODE_64BIT
2578 && (i
.tm
.operand_types
[op
] & InOutPortReg
) == 0)
2580 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
2581 i
.op
[op
].regs
->reg_name
,
2585 #if REGISTER_WARNINGS
2587 && (i
.tm
.operand_types
[op
] & InOutPortReg
) == 0)
2588 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2589 (i
.op
[op
].regs
+ (i
.types
[op
] & Reg16
2590 ? REGNAM_AL
- REGNAM_AX
2591 : REGNAM_AL
- REGNAM_EAX
))->reg_name
,
2592 i
.op
[op
].regs
->reg_name
,
2597 /* Any other register is bad. */
2598 if (i
.types
[op
] & (Reg
| RegMMX
| RegXMM
2600 | Control
| Debug
| Test
2601 | FloatReg
| FloatAcc
))
2603 as_bad (_("`%%%s' not allowed with `%s%c'"),
2604 i
.op
[op
].regs
->reg_name
,
2618 for (op
= i
.operands
; --op
>= 0;)
2619 /* Reject eight bit registers, except where the template requires
2620 them. (eg. movzb) */
2621 if ((i
.types
[op
] & Reg8
) != 0
2622 && (i
.tm
.operand_types
[op
] & (Reg16
| Reg32
| Acc
)) != 0)
2624 as_bad (_("`%%%s' not allowed with `%s%c'"),
2625 i
.op
[op
].regs
->reg_name
,
2630 /* Warn if the e prefix on a general reg is missing. */
2631 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
2632 && (i
.types
[op
] & Reg16
) != 0
2633 && (i
.tm
.operand_types
[op
] & (Reg32
| Acc
)) != 0)
2635 /* Prohibit these changes in the 64bit mode, since the
2636 lowering is more complicated. */
2637 if (flag_code
== CODE_64BIT
)
2639 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
2640 i
.op
[op
].regs
->reg_name
,
2644 #if REGISTER_WARNINGS
2646 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2647 (i
.op
[op
].regs
+ REGNAM_EAX
- REGNAM_AX
)->reg_name
,
2648 i
.op
[op
].regs
->reg_name
,
2652 /* Warn if the r prefix on a general reg is missing. */
2653 else if ((i
.types
[op
] & Reg64
) != 0
2654 && (i
.tm
.operand_types
[op
] & (Reg32
| Acc
)) != 0)
2656 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
2657 i
.op
[op
].regs
->reg_name
,
2669 for (op
= i
.operands
; --op
>= 0; )
2670 /* Reject eight bit registers, except where the template requires
2671 them. (eg. movzb) */
2672 if ((i
.types
[op
] & Reg8
) != 0
2673 && (i
.tm
.operand_types
[op
] & (Reg16
| Reg32
| Acc
)) != 0)
2675 as_bad (_("`%%%s' not allowed with `%s%c'"),
2676 i
.op
[op
].regs
->reg_name
,
2681 /* Warn if the e prefix on a general reg is missing. */
2682 else if (((i
.types
[op
] & Reg16
) != 0
2683 || (i
.types
[op
] & Reg32
) != 0)
2684 && (i
.tm
.operand_types
[op
] & (Reg32
| Acc
)) != 0)
2686 /* Prohibit these changes in the 64bit mode, since the
2687 lowering is more complicated. */
2688 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
2689 i
.op
[op
].regs
->reg_name
,
2700 for (op
= i
.operands
; --op
>= 0;)
2701 /* Reject eight bit registers, except where the template requires
2702 them. (eg. movzb) */
2703 if ((i
.types
[op
] & Reg8
) != 0
2704 && (i
.tm
.operand_types
[op
] & (Reg16
| Reg32
| Acc
)) != 0)
2706 as_bad (_("`%%%s' not allowed with `%s%c'"),
2707 i
.op
[op
].regs
->reg_name
,
2712 /* Warn if the e prefix on a general reg is present. */
2713 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
2714 && (i
.types
[op
] & Reg32
) != 0
2715 && (i
.tm
.operand_types
[op
] & (Reg16
| Acc
)) != 0)
2717 /* Prohibit these changes in the 64bit mode, since the
2718 lowering is more complicated. */
2719 if (flag_code
== CODE_64BIT
)
2721 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
2722 i
.op
[op
].regs
->reg_name
,
2727 #if REGISTER_WARNINGS
2728 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2729 (i
.op
[op
].regs
+ REGNAM_AX
- REGNAM_EAX
)->reg_name
,
2730 i
.op
[op
].regs
->reg_name
,
2740 unsigned int overlap0
, overlap1
, overlap2
;
2742 overlap0
= i
.types
[0] & i
.tm
.operand_types
[0];
2743 if ((overlap0
& (Imm8
| Imm8S
| Imm16
| Imm32
| Imm32S
| Imm64
))
2744 && overlap0
!= Imm8
&& overlap0
!= Imm8S
2745 && overlap0
!= Imm16
&& overlap0
!= Imm32S
2746 && overlap0
!= Imm32
&& overlap0
!= Imm64
)
2750 overlap0
&= (i
.suffix
== BYTE_MNEM_SUFFIX
2752 : (i
.suffix
== WORD_MNEM_SUFFIX
2754 : (i
.suffix
== QWORD_MNEM_SUFFIX
2758 else if (overlap0
== (Imm16
| Imm32S
| Imm32
)
2759 || overlap0
== (Imm16
| Imm32
)
2760 || overlap0
== (Imm16
| Imm32S
))
2762 overlap0
= ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0)
2765 if (overlap0
!= Imm8
&& overlap0
!= Imm8S
2766 && overlap0
!= Imm16
&& overlap0
!= Imm32S
2767 && overlap0
!= Imm32
&& overlap0
!= Imm64
)
2769 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size"));
2773 i
.types
[0] = overlap0
;
2775 overlap1
= i
.types
[1] & i
.tm
.operand_types
[1];
2776 if ((overlap1
& (Imm8
| Imm8S
| Imm16
| Imm32S
| Imm32
| Imm64
))
2777 && overlap1
!= Imm8
&& overlap1
!= Imm8S
2778 && overlap1
!= Imm16
&& overlap1
!= Imm32S
2779 && overlap1
!= Imm32
&& overlap1
!= Imm64
)
2783 overlap1
&= (i
.suffix
== BYTE_MNEM_SUFFIX
2785 : (i
.suffix
== WORD_MNEM_SUFFIX
2787 : (i
.suffix
== QWORD_MNEM_SUFFIX
2791 else if (overlap1
== (Imm16
| Imm32
| Imm32S
)
2792 || overlap1
== (Imm16
| Imm32
)
2793 || overlap1
== (Imm16
| Imm32S
))
2795 overlap1
= ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0)
2798 if (overlap1
!= Imm8
&& overlap1
!= Imm8S
2799 && overlap1
!= Imm16
&& overlap1
!= Imm32S
2800 && overlap1
!= Imm32
&& overlap1
!= Imm64
)
2802 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size %x %c"),overlap1
, i
.suffix
);
2806 i
.types
[1] = overlap1
;
2808 overlap2
= i
.types
[2] & i
.tm
.operand_types
[2];
2809 assert ((overlap2
& Imm
) == 0);
2810 i
.types
[2] = overlap2
;
2818 /* Default segment register this instruction will use for memory
2819 accesses. 0 means unknown. This is only for optimizing out
2820 unnecessary segment overrides. */
2821 const seg_entry
*default_seg
= 0;
2823 /* The imul $imm, %reg instruction is converted into
2824 imul $imm, %reg, %reg, and the clr %reg instruction
2825 is converted into xor %reg, %reg. */
2826 if (i
.tm
.opcode_modifier
& regKludge
)
2828 unsigned int first_reg_op
= (i
.types
[0] & Reg
) ? 0 : 1;
2829 /* Pretend we saw the extra register operand. */
2830 assert (i
.op
[first_reg_op
+ 1].regs
== 0);
2831 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
2832 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
2836 if (i
.tm
.opcode_modifier
& ShortForm
)
2838 /* The register or float register operand is in operand 0 or 1. */
2839 unsigned int op
= (i
.types
[0] & (Reg
| FloatReg
)) ? 0 : 1;
2840 /* Register goes in low 3 bits of opcode. */
2841 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
2842 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
2844 if (!quiet_warnings
&& (i
.tm
.opcode_modifier
& Ugh
) != 0)
2846 /* Warn about some common errors, but press on regardless.
2847 The first case can be generated by gcc (<= 2.8.1). */
2848 if (i
.operands
== 2)
2850 /* Reversed arguments on faddp, fsubp, etc. */
2851 as_warn (_("translating to `%s %%%s,%%%s'"), i
.tm
.name
,
2852 i
.op
[1].regs
->reg_name
,
2853 i
.op
[0].regs
->reg_name
);
2857 /* Extraneous `l' suffix on fp insn. */
2858 as_warn (_("translating to `%s %%%s'"), i
.tm
.name
,
2859 i
.op
[0].regs
->reg_name
);
2863 else if (i
.tm
.opcode_modifier
& Modrm
)
2865 /* The opcode is completed (modulo i.tm.extension_opcode which
2866 must be put into the modrm byte). Now, we make the modrm and
2867 index base bytes based on all the info we've collected. */
2869 default_seg
= build_modrm_byte ();
2871 else if (i
.tm
.opcode_modifier
& (Seg2ShortForm
| Seg3ShortForm
))
2873 if (i
.tm
.base_opcode
== POP_SEG_SHORT
2874 && i
.op
[0].regs
->reg_num
== 1)
2876 as_bad (_("you can't `pop %%cs'"));
2879 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
2880 if ((i
.op
[0].regs
->reg_flags
& RegRex
) != 0)
2883 else if ((i
.tm
.base_opcode
& ~(D
| W
)) == MOV_AX_DISP32
)
2887 else if ((i
.tm
.opcode_modifier
& IsString
) != 0)
2889 /* For the string instructions that allow a segment override
2890 on one of their operands, the default segment is ds. */
2894 if ((i
.tm
.base_opcode
== 0x8d /* lea */
2895 || (i
.tm
.cpu_flags
& CpuSVME
))
2896 && i
.seg
[0] && !quiet_warnings
)
2897 as_warn (_("segment override on `%s' is ineffectual"), i
.tm
.name
);
2899 /* If a segment was explicitly specified, and the specified segment
2900 is not the default, use an opcode prefix to select it. If we
2901 never figured out what the default segment is, then default_seg
2902 will be zero at this point, and the specified segment prefix will
2904 if ((i
.seg
[0]) && (i
.seg
[0] != default_seg
))
2906 if (!add_prefix (i
.seg
[0]->seg_prefix
))
2912 static const seg_entry
*
2915 const seg_entry
*default_seg
= 0;
2917 /* i.reg_operands MUST be the number of real register operands;
2918 implicit registers do not count. */
2919 if (i
.reg_operands
== 2)
2921 unsigned int source
, dest
;
2922 source
= ((i
.types
[0]
2923 & (Reg
| RegMMX
| RegXMM
2925 | Control
| Debug
| Test
))
2930 /* One of the register operands will be encoded in the i.tm.reg
2931 field, the other in the combined i.tm.mode and i.tm.regmem
2932 fields. If no form of this instruction supports a memory
2933 destination operand, then we assume the source operand may
2934 sometimes be a memory operand and so we need to store the
2935 destination in the i.rm.reg field. */
2936 if ((i
.tm
.operand_types
[dest
] & AnyMem
) == 0)
2938 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
2939 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
2940 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
2942 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
2947 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
2948 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
2949 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
2951 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
2954 if (flag_code
!= CODE_64BIT
&& (i
.rex
& (REX_EXTX
| REX_EXTZ
)))
2956 if (!((i
.types
[0] | i
.types
[1]) & Control
))
2958 i
.rex
&= ~(REX_EXTX
| REX_EXTZ
);
2959 add_prefix (LOCK_PREFIX_OPCODE
);
2963 { /* If it's not 2 reg operands... */
2966 unsigned int fake_zero_displacement
= 0;
2967 unsigned int op
= ((i
.types
[0] & AnyMem
)
2969 : (i
.types
[1] & AnyMem
) ? 1 : 2);
2973 if (i
.base_reg
== 0)
2976 if (!i
.disp_operands
)
2977 fake_zero_displacement
= 1;
2978 if (i
.index_reg
== 0)
2980 /* Operand is just <disp> */
2981 if (flag_code
== CODE_64BIT
)
2983 /* 64bit mode overwrites the 32bit absolute
2984 addressing by RIP relative addressing and
2985 absolute addressing is encoded by one of the
2986 redundant SIB forms. */
2987 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
2988 i
.sib
.base
= NO_BASE_REGISTER
;
2989 i
.sib
.index
= NO_INDEX_REGISTER
;
2990 i
.types
[op
] = ((i
.prefix
[ADDR_PREFIX
] == 0) ? Disp32S
: Disp32
);
2992 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[ADDR_PREFIX
] != 0))
2994 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
2995 i
.types
[op
] = Disp16
;
2999 i
.rm
.regmem
= NO_BASE_REGISTER
;
3000 i
.types
[op
] = Disp32
;
3003 else /* !i.base_reg && i.index_reg */
3005 i
.sib
.index
= i
.index_reg
->reg_num
;
3006 i
.sib
.base
= NO_BASE_REGISTER
;
3007 i
.sib
.scale
= i
.log2_scale_factor
;
3008 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
3009 i
.types
[op
] &= ~Disp
;
3010 if (flag_code
!= CODE_64BIT
)
3011 i
.types
[op
] |= Disp32
; /* Must be 32 bit */
3013 i
.types
[op
] |= Disp32S
;
3014 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
3018 /* RIP addressing for 64bit mode. */
3019 else if (i
.base_reg
->reg_type
== BaseIndex
)
3021 i
.rm
.regmem
= NO_BASE_REGISTER
;
3022 i
.types
[op
] &= ~ Disp
;
3023 i
.types
[op
] |= Disp32S
;
3024 i
.flags
[op
] = Operand_PCrel
;
3025 if (! i
.disp_operands
)
3026 fake_zero_displacement
= 1;
3028 else if (i
.base_reg
->reg_type
& Reg16
)
3030 switch (i
.base_reg
->reg_num
)
3033 if (i
.index_reg
== 0)
3035 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
3036 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
3040 if (i
.index_reg
== 0)
3043 if ((i
.types
[op
] & Disp
) == 0)
3045 /* fake (%bp) into 0(%bp) */
3046 i
.types
[op
] |= Disp8
;
3047 fake_zero_displacement
= 1;
3050 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
3051 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
3053 default: /* (%si) -> 4 or (%di) -> 5 */
3054 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
3056 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
3058 else /* i.base_reg and 32/64 bit mode */
3060 if (flag_code
== CODE_64BIT
3061 && (i
.types
[op
] & Disp
))
3062 i
.types
[op
] = (i
.types
[op
] & Disp8
) | (i
.prefix
[ADDR_PREFIX
] == 0 ? Disp32S
: Disp32
);
3064 i
.rm
.regmem
= i
.base_reg
->reg_num
;
3065 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
3067 i
.sib
.base
= i
.base_reg
->reg_num
;
3068 /* x86-64 ignores REX prefix bit here to avoid decoder
3070 if ((i
.base_reg
->reg_num
& 7) == EBP_REG_NUM
)
3073 if (i
.disp_operands
== 0)
3075 fake_zero_displacement
= 1;
3076 i
.types
[op
] |= Disp8
;
3079 else if (i
.base_reg
->reg_num
== ESP_REG_NUM
)
3083 i
.sib
.scale
= i
.log2_scale_factor
;
3084 if (i
.index_reg
== 0)
3086 /* <disp>(%esp) becomes two byte modrm with no index
3087 register. We've already stored the code for esp
3088 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
3089 Any base register besides %esp will not use the
3090 extra modrm byte. */
3091 i
.sib
.index
= NO_INDEX_REGISTER
;
3092 #if !SCALE1_WHEN_NO_INDEX
3093 /* Another case where we force the second modrm byte. */
3094 if (i
.log2_scale_factor
)
3095 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
3100 i
.sib
.index
= i
.index_reg
->reg_num
;
3101 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
3102 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
3105 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
3108 if (fake_zero_displacement
)
3110 /* Fakes a zero displacement assuming that i.types[op]
3111 holds the correct displacement size. */
3114 assert (i
.op
[op
].disps
== 0);
3115 exp
= &disp_expressions
[i
.disp_operands
++];
3116 i
.op
[op
].disps
= exp
;
3117 exp
->X_op
= O_constant
;
3118 exp
->X_add_number
= 0;
3119 exp
->X_add_symbol
= (symbolS
*) 0;
3120 exp
->X_op_symbol
= (symbolS
*) 0;
3124 /* Fill in i.rm.reg or i.rm.regmem field with register operand
3125 (if any) based on i.tm.extension_opcode. Again, we must be
3126 careful to make sure that segment/control/debug/test/MMX
3127 registers are coded into the i.rm.reg field. */
3132 & (Reg
| RegMMX
| RegXMM
3134 | Control
| Debug
| Test
))
3137 & (Reg
| RegMMX
| RegXMM
3139 | Control
| Debug
| Test
))
3142 /* If there is an extension opcode to put here, the register
3143 number must be put into the regmem field. */
3144 if (i
.tm
.extension_opcode
!= None
)
3146 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
3147 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
3152 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
3153 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
3157 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
3158 must set it to 3 to indicate this is a register operand
3159 in the regmem field. */
3160 if (!i
.mem_operands
)
3164 /* Fill in i.rm.reg field with extension opcode (if any). */
3165 if (i
.tm
.extension_opcode
!= None
)
3166 i
.rm
.reg
= i
.tm
.extension_opcode
;
3177 relax_substateT subtype
;
3182 if (flag_code
== CODE_16BIT
)
3186 if (i
.prefix
[DATA_PREFIX
] != 0)
3192 /* Pentium4 branch hints. */
3193 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
3194 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
3199 if (i
.prefix
[REX_PREFIX
] != 0)
3205 if (i
.prefixes
!= 0 && !intel_syntax
)
3206 as_warn (_("skipping prefixes on this instruction"));
3208 /* It's always a symbol; End frag & setup for relax.
3209 Make sure there is enough room in this frag for the largest
3210 instruction we may generate in md_convert_frag. This is 2
3211 bytes for the opcode and room for the prefix and largest
3213 frag_grow (prefix
+ 2 + 4);
3214 /* Prefix and 1 opcode byte go in fr_fix. */
3215 p
= frag_more (prefix
+ 1);
3216 if (i
.prefix
[DATA_PREFIX
] != 0)
3217 *p
++ = DATA_PREFIX_OPCODE
;
3218 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
3219 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
3220 *p
++ = i
.prefix
[SEG_PREFIX
];
3221 if (i
.prefix
[REX_PREFIX
] != 0)
3222 *p
++ = i
.prefix
[REX_PREFIX
];
3223 *p
= i
.tm
.base_opcode
;
3225 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
3226 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, SMALL
);
3227 else if ((cpu_arch_flags
& Cpu386
) != 0)
3228 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, SMALL
);
3230 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, SMALL
);
3233 sym
= i
.op
[0].disps
->X_add_symbol
;
3234 off
= i
.op
[0].disps
->X_add_number
;
3236 if (i
.op
[0].disps
->X_op
!= O_constant
3237 && i
.op
[0].disps
->X_op
!= O_symbol
)
3239 /* Handle complex expressions. */
3240 sym
= make_expr_symbol (i
.op
[0].disps
);
3244 /* 1 possible extra opcode + 4 byte displacement go in var part.
3245 Pass reloc in fr_var. */
3246 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
3256 if (i
.tm
.opcode_modifier
& JumpByte
)
3258 /* This is a loop or jecxz type instruction. */
3260 if (i
.prefix
[ADDR_PREFIX
] != 0)
3262 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
3265 /* Pentium4 branch hints. */
3266 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
3267 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
3269 FRAG_APPEND_1_CHAR (i
.prefix
[SEG_PREFIX
]);
3278 if (flag_code
== CODE_16BIT
)
3281 if (i
.prefix
[DATA_PREFIX
] != 0)
3283 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
3293 if (i
.prefix
[REX_PREFIX
] != 0)
3295 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
3299 if (i
.prefixes
!= 0 && !intel_syntax
)
3300 as_warn (_("skipping prefixes on this instruction"));
3302 p
= frag_more (1 + size
);
3303 *p
++ = i
.tm
.base_opcode
;
3305 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
3306 i
.op
[0].disps
, 1, reloc (size
, 1, 1, i
.reloc
[0]));
3308 /* All jumps handled here are signed, but don't use a signed limit
3309 check for 32 and 16 bit jumps as we want to allow wrap around at
3310 4G and 64k respectively. */
3312 fixP
->fx_signed
= 1;
3316 output_interseg_jump ()
3324 if (flag_code
== CODE_16BIT
)
3328 if (i
.prefix
[DATA_PREFIX
] != 0)
3334 if (i
.prefix
[REX_PREFIX
] != 0)
3344 if (i
.prefixes
!= 0 && !intel_syntax
)
3345 as_warn (_("skipping prefixes on this instruction"));
3347 /* 1 opcode; 2 segment; offset */
3348 p
= frag_more (prefix
+ 1 + 2 + size
);
3350 if (i
.prefix
[DATA_PREFIX
] != 0)
3351 *p
++ = DATA_PREFIX_OPCODE
;
3353 if (i
.prefix
[REX_PREFIX
] != 0)
3354 *p
++ = i
.prefix
[REX_PREFIX
];
3356 *p
++ = i
.tm
.base_opcode
;
3357 if (i
.op
[1].imms
->X_op
== O_constant
)
3359 offsetT n
= i
.op
[1].imms
->X_add_number
;
3362 && !fits_in_unsigned_word (n
)
3363 && !fits_in_signed_word (n
))
3365 as_bad (_("16-bit jump out of range"));
3368 md_number_to_chars (p
, n
, size
);
3371 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
3372 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
3373 if (i
.op
[0].imms
->X_op
!= O_constant
)
3374 as_bad (_("can't handle non absolute segment in `%s'"),
3376 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
3382 fragS
*insn_start_frag
;
3383 offsetT insn_start_off
;
3385 /* Tie dwarf2 debug info to the address at the start of the insn.
3386 We can't do this after the insn has been output as the current
3387 frag may have been closed off. eg. by frag_var. */
3388 dwarf2_emit_insn (0);
3390 insn_start_frag
= frag_now
;
3391 insn_start_off
= frag_now_fix ();
3394 if (i
.tm
.opcode_modifier
& Jump
)
3396 else if (i
.tm
.opcode_modifier
& (JumpByte
| JumpDword
))
3398 else if (i
.tm
.opcode_modifier
& JumpInterSegment
)
3399 output_interseg_jump ();
3402 /* Output normal instructions here. */
3406 /* All opcodes on i386 have either 1 or 2 bytes. We may use one
3407 more higher byte to specify a prefix the instruction
3409 if ((i
.tm
.base_opcode
& 0xff0000) != 0)
3411 if ((i
.tm
.cpu_flags
& CpuPadLock
) != 0)
3413 unsigned int prefix
;
3414 prefix
= (i
.tm
.base_opcode
>> 16) & 0xff;
3416 if (prefix
!= REPE_PREFIX_OPCODE
3417 || i
.prefix
[LOCKREP_PREFIX
] != REPE_PREFIX_OPCODE
)
3418 add_prefix (prefix
);
3421 add_prefix ((i
.tm
.base_opcode
>> 16) & 0xff);
3424 /* The prefix bytes. */
3426 q
< i
.prefix
+ sizeof (i
.prefix
) / sizeof (i
.prefix
[0]);
3432 md_number_to_chars (p
, (valueT
) *q
, 1);
3436 /* Now the opcode; be careful about word order here! */
3437 if (fits_in_unsigned_byte (i
.tm
.base_opcode
))
3439 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
3445 /* Put out high byte first: can't use md_number_to_chars! */
3446 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
3447 *p
= i
.tm
.base_opcode
& 0xff;
3450 /* Now the modrm byte and sib byte (if present). */
3451 if (i
.tm
.opcode_modifier
& Modrm
)
3454 md_number_to_chars (p
,
3455 (valueT
) (i
.rm
.regmem
<< 0
3459 /* If i.rm.regmem == ESP (4)
3460 && i.rm.mode != (Register mode)
3462 ==> need second modrm byte. */
3463 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
3465 && !(i
.base_reg
&& (i
.base_reg
->reg_type
& Reg16
) != 0))
3468 md_number_to_chars (p
,
3469 (valueT
) (i
.sib
.base
<< 0
3471 | i
.sib
.scale
<< 6),
3476 if (i
.disp_operands
)
3477 output_disp (insn_start_frag
, insn_start_off
);
3480 output_imm (insn_start_frag
, insn_start_off
);
3488 #endif /* DEBUG386 */
3492 output_disp (insn_start_frag
, insn_start_off
)
3493 fragS
*insn_start_frag
;
3494 offsetT insn_start_off
;
3499 for (n
= 0; n
< i
.operands
; n
++)
3501 if (i
.types
[n
] & Disp
)
3503 if (i
.op
[n
].disps
->X_op
== O_constant
)
3509 if (i
.types
[n
] & (Disp8
| Disp16
| Disp64
))
3512 if (i
.types
[n
] & Disp8
)
3514 if (i
.types
[n
] & Disp64
)
3517 val
= offset_in_range (i
.op
[n
].disps
->X_add_number
,
3519 p
= frag_more (size
);
3520 md_number_to_chars (p
, val
, size
);
3524 enum bfd_reloc_code_real reloc_type
;
3527 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
3529 /* The PC relative address is computed relative
3530 to the instruction boundary, so in case immediate
3531 fields follows, we need to adjust the value. */
3532 if (pcrel
&& i
.imm_operands
)
3537 for (n1
= 0; n1
< i
.operands
; n1
++)
3538 if (i
.types
[n1
] & Imm
)
3540 if (i
.types
[n1
] & (Imm8
| Imm8S
| Imm16
| Imm64
))
3543 if (i
.types
[n1
] & (Imm8
| Imm8S
))
3545 if (i
.types
[n1
] & Imm64
)
3550 /* We should find the immediate. */
3551 if (n1
== i
.operands
)
3553 i
.op
[n
].disps
->X_add_number
-= imm_size
;
3556 if (i
.types
[n
] & Disp32S
)
3559 if (i
.types
[n
] & (Disp16
| Disp64
))
3562 if (i
.types
[n
] & Disp64
)
3566 p
= frag_more (size
);
3567 reloc_type
= reloc (size
, pcrel
, sign
, i
.reloc
[n
]);
3569 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
3570 && (((reloc_type
== BFD_RELOC_32
3571 || reloc_type
== BFD_RELOC_X86_64_32S
)
3572 && (i
.op
[n
].disps
->X_op
== O_symbol
3573 || (i
.op
[n
].disps
->X_op
== O_add
3574 && ((symbol_get_value_expression
3575 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
3577 || reloc_type
== BFD_RELOC_32_PCREL
))
3581 if (insn_start_frag
== frag_now
)
3582 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
3587 add
= insn_start_frag
->fr_fix
- insn_start_off
;
3588 for (fr
= insn_start_frag
->fr_next
;
3589 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
3591 add
+= p
- frag_now
->fr_literal
;
3594 if (flag_code
!= CODE_64BIT
)
3595 reloc_type
= BFD_RELOC_386_GOTPC
;
3597 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
3598 i
.op
[n
].disps
->X_add_number
+= add
;
3600 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
3601 i
.op
[n
].disps
, pcrel
, reloc_type
);
3608 output_imm (insn_start_frag
, insn_start_off
)
3609 fragS
*insn_start_frag
;
3610 offsetT insn_start_off
;
3615 for (n
= 0; n
< i
.operands
; n
++)
3617 if (i
.types
[n
] & Imm
)
3619 if (i
.op
[n
].imms
->X_op
== O_constant
)
3625 if (i
.types
[n
] & (Imm8
| Imm8S
| Imm16
| Imm64
))
3628 if (i
.types
[n
] & (Imm8
| Imm8S
))
3630 else if (i
.types
[n
] & Imm64
)
3633 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
3635 p
= frag_more (size
);
3636 md_number_to_chars (p
, val
, size
);
3640 /* Not absolute_section.
3641 Need a 32-bit fixup (don't support 8bit
3642 non-absolute imms). Try to support other
3644 enum bfd_reloc_code_real reloc_type
;
3648 if ((i
.types
[n
] & (Imm32S
))
3649 && (i
.suffix
== QWORD_MNEM_SUFFIX
3650 || (!i
.suffix
&& (i
.tm
.opcode_modifier
& No_lSuf
))))
3652 if (i
.types
[n
] & (Imm8
| Imm8S
| Imm16
| Imm64
))
3655 if (i
.types
[n
] & (Imm8
| Imm8S
))
3657 if (i
.types
[n
] & Imm64
)
3661 p
= frag_more (size
);
3662 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
3664 /* This is tough to explain. We end up with this one if we
3665 * have operands that look like
3666 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
3667 * obtain the absolute address of the GOT, and it is strongly
3668 * preferable from a performance point of view to avoid using
3669 * a runtime relocation for this. The actual sequence of
3670 * instructions often look something like:
3675 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
3677 * The call and pop essentially return the absolute address
3678 * of the label .L66 and store it in %ebx. The linker itself
3679 * will ultimately change the first operand of the addl so
3680 * that %ebx points to the GOT, but to keep things simple, the
3681 * .o file must have this operand set so that it generates not
3682 * the absolute address of .L66, but the absolute address of
3683 * itself. This allows the linker itself simply treat a GOTPC
3684 * relocation as asking for a pcrel offset to the GOT to be
3685 * added in, and the addend of the relocation is stored in the
3686 * operand field for the instruction itself.
3688 * Our job here is to fix the operand so that it would add
3689 * the correct offset so that %ebx would point to itself. The
3690 * thing that is tricky is that .-.L66 will point to the
3691 * beginning of the instruction, so we need to further modify
3692 * the operand so that it will point to itself. There are
3693 * other cases where you have something like:
3695 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
3697 * and here no correction would be required. Internally in
3698 * the assembler we treat operands of this form as not being
3699 * pcrel since the '.' is explicitly mentioned, and I wonder
3700 * whether it would simplify matters to do it this way. Who
3701 * knows. In earlier versions of the PIC patches, the
3702 * pcrel_adjust field was used to store the correction, but
3703 * since the expression is not pcrel, I felt it would be
3704 * confusing to do it this way. */
3706 if ((reloc_type
== BFD_RELOC_32
3707 || reloc_type
== BFD_RELOC_X86_64_32S
)
3709 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
3710 && (i
.op
[n
].imms
->X_op
== O_symbol
3711 || (i
.op
[n
].imms
->X_op
== O_add
3712 && ((symbol_get_value_expression
3713 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
3718 if (insn_start_frag
== frag_now
)
3719 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
3724 add
= insn_start_frag
->fr_fix
- insn_start_off
;
3725 for (fr
= insn_start_frag
->fr_next
;
3726 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
3728 add
+= p
- frag_now
->fr_literal
;
3731 if (flag_code
!= CODE_64BIT
)
3732 reloc_type
= BFD_RELOC_386_GOTPC
;
3734 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
3735 i
.op
[n
].imms
->X_add_number
+= add
;
3737 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
3738 i
.op
[n
].imms
, 0, reloc_type
);
3745 /* Parse operands of the form
3746 <symbol>@GOTOFF+<nnn>
3747 and similar .plt or .got references.
3749 If we find one, set up the correct relocation in RELOC and copy the
3750 input string, minus the `@GOTOFF' into a malloc'd buffer for
3751 parsing by the calling routine. Return this buffer, and if ADJUST
3752 is non-null set it to the length of the string we removed from the
3753 input line. Otherwise return NULL. */
3755 lex_got (enum bfd_reloc_code_real
*reloc
,
3757 unsigned int *types
)
3759 static const char * const mode_name
[NUM_FLAG_CODE
] = { "32", "16", "64" };
3760 static const struct {
3762 const enum bfd_reloc_code_real rel
[NUM_FLAG_CODE
];
3763 const unsigned int types64
;
3765 { "PLT", { BFD_RELOC_386_PLT32
, 0, BFD_RELOC_X86_64_PLT32
}, Imm32
|Imm32S
|Disp32
},
3766 { "GOTOFF", { BFD_RELOC_386_GOTOFF
, 0, BFD_RELOC_X86_64_GOTOFF64
}, Imm64
|Disp64
},
3767 { "GOTPCREL", { 0, 0, BFD_RELOC_X86_64_GOTPCREL
}, Imm32
|Imm32S
|Disp32
},
3768 { "TLSGD", { BFD_RELOC_386_TLS_GD
, 0, BFD_RELOC_X86_64_TLSGD
}, Imm32
|Imm32S
|Disp32
},
3769 { "TLSLDM", { BFD_RELOC_386_TLS_LDM
, 0, 0 }, 0 },
3770 { "TLSLD", { 0, 0, BFD_RELOC_X86_64_TLSLD
}, Imm32
|Imm32S
|Disp32
},
3771 { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32
, 0, BFD_RELOC_X86_64_GOTTPOFF
}, Imm32
|Imm32S
|Disp32
},
3772 { "TPOFF", { BFD_RELOC_386_TLS_LE_32
, 0, BFD_RELOC_X86_64_TPOFF32
}, Imm32
|Imm32S
|Imm64
|Disp32
|Disp64
},
3773 { "NTPOFF", { BFD_RELOC_386_TLS_LE
, 0, 0 }, 0 },
3774 { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32
, 0, BFD_RELOC_X86_64_DTPOFF32
}, Imm32
|Imm32S
|Imm64
|Disp32
|Disp64
},
3775 { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE
, 0, 0 }, 0 },
3776 { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE
, 0, 0 }, 0 },
3777 { "GOT", { BFD_RELOC_386_GOT32
, 0, BFD_RELOC_X86_64_GOT32
}, Imm32
|Imm32S
|Disp32
}
3782 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
3783 if (is_end_of_line
[(unsigned char) *cp
])
3786 for (j
= 0; j
< sizeof (gotrel
) / sizeof (gotrel
[0]); j
++)
3790 len
= strlen (gotrel
[j
].str
);
3791 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
3793 if (gotrel
[j
].rel
[(unsigned int) flag_code
] != 0)
3796 char *tmpbuf
, *past_reloc
;
3798 *reloc
= gotrel
[j
].rel
[(unsigned int) flag_code
];
3804 if (flag_code
!= CODE_64BIT
)
3805 *types
= Imm32
|Disp32
;
3807 *types
= gotrel
[j
].types64
;
3810 if (GOT_symbol
== NULL
)
3811 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
3813 /* Replace the relocation token with ' ', so that
3814 errors like foo@GOTOFF1 will be detected. */
3816 /* The length of the first part of our input line. */
3817 first
= cp
- input_line_pointer
;
3819 /* The second part goes from after the reloc token until
3820 (and including) an end_of_line char. Don't use strlen
3821 here as the end_of_line char may not be a NUL. */
3822 past_reloc
= cp
+ 1 + len
;
3823 for (cp
= past_reloc
; !is_end_of_line
[(unsigned char) *cp
++]; )
3825 second
= cp
- past_reloc
;
3827 /* Allocate and copy string. The trailing NUL shouldn't
3828 be necessary, but be safe. */
3829 tmpbuf
= xmalloc (first
+ second
+ 2);
3830 memcpy (tmpbuf
, input_line_pointer
, first
);
3831 tmpbuf
[first
] = ' ';
3832 memcpy (tmpbuf
+ first
+ 1, past_reloc
, second
);
3833 tmpbuf
[first
+ second
+ 1] = '\0';
3837 as_bad (_("@%s reloc is not supported in %s bit mode"),
3838 gotrel
[j
].str
, mode_name
[(unsigned int) flag_code
]);
3843 /* Might be a symbol version string. Don't as_bad here. */
3847 /* x86_cons_fix_new is called via the expression parsing code when a
3848 reloc is needed. We use this hook to get the correct .got reloc. */
3849 static enum bfd_reloc_code_real got_reloc
= NO_RELOC
;
3852 x86_cons_fix_new (frag
, off
, len
, exp
)
3858 enum bfd_reloc_code_real r
= reloc (len
, 0, -1, got_reloc
);
3859 got_reloc
= NO_RELOC
;
3860 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
3864 x86_cons (exp
, size
)
3868 if (size
== 4 || (flag_code
== CODE_64BIT
&& size
== 8))
3870 /* Handle @GOTOFF and the like in an expression. */
3872 char *gotfree_input_line
;
3875 save
= input_line_pointer
;
3876 gotfree_input_line
= lex_got (&got_reloc
, &adjust
, NULL
);
3877 if (gotfree_input_line
)
3878 input_line_pointer
= gotfree_input_line
;
3882 if (gotfree_input_line
)
3884 /* expression () has merrily parsed up to the end of line,
3885 or a comma - in the wrong buffer. Transfer how far
3886 input_line_pointer has moved to the right buffer. */
3887 input_line_pointer
= (save
3888 + (input_line_pointer
- gotfree_input_line
)
3890 free (gotfree_input_line
);
3901 x86_pe_cons_fix_new (frag
, off
, len
, exp
)
3907 enum bfd_reloc_code_real r
= reloc (len
, 0, -1, NO_RELOC
);
3909 if (exp
->X_op
== O_secrel
)
3911 exp
->X_op
= O_symbol
;
3912 r
= BFD_RELOC_32_SECREL
;
3915 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
3919 pe_directive_secrel (dummy
)
3920 int dummy ATTRIBUTE_UNUSED
;
3927 if (exp
.X_op
== O_symbol
)
3928 exp
.X_op
= O_secrel
;
3930 emit_expr (&exp
, 4);
3932 while (*input_line_pointer
++ == ',');
3934 input_line_pointer
--;
3935 demand_empty_rest_of_line ();
3940 static int i386_immediate
PARAMS ((char *));
3943 i386_immediate (imm_start
)
3946 char *save_input_line_pointer
;
3948 char *gotfree_input_line
;
3952 unsigned int types
= ~0U;
3954 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
3956 as_bad (_("only 1 or 2 immediate operands are allowed"));
3960 exp
= &im_expressions
[i
.imm_operands
++];
3961 i
.op
[this_operand
].imms
= exp
;
3963 if (is_space_char (*imm_start
))
3966 save_input_line_pointer
= input_line_pointer
;
3967 input_line_pointer
= imm_start
;
3970 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
3971 if (gotfree_input_line
)
3972 input_line_pointer
= gotfree_input_line
;
3975 exp_seg
= expression (exp
);
3978 if (*input_line_pointer
)
3979 as_bad (_("junk `%s' after expression"), input_line_pointer
);
3981 input_line_pointer
= save_input_line_pointer
;
3983 if (gotfree_input_line
)
3984 free (gotfree_input_line
);
3987 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_big
)
3989 /* Missing or bad expr becomes absolute 0. */
3990 as_bad (_("missing or invalid immediate expression `%s' taken as 0"),
3992 exp
->X_op
= O_constant
;
3993 exp
->X_add_number
= 0;
3994 exp
->X_add_symbol
= (symbolS
*) 0;
3995 exp
->X_op_symbol
= (symbolS
*) 0;
3997 else if (exp
->X_op
== O_constant
)
3999 /* Size it properly later. */
4000 i
.types
[this_operand
] |= Imm64
;
4001 /* If BFD64, sign extend val. */
4002 if (!use_rela_relocations
)
4003 if ((exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
4004 exp
->X_add_number
= (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
4006 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
4007 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
4008 && exp_seg
!= absolute_section
4009 && exp_seg
!= text_section
4010 && exp_seg
!= data_section
4011 && exp_seg
!= bss_section
4012 && exp_seg
!= undefined_section
4013 && !bfd_is_com_section (exp_seg
))
4015 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
4021 /* This is an address. The size of the address will be
4022 determined later, depending on destination register,
4023 suffix, or the default for the section. */
4024 i
.types
[this_operand
] |= Imm8
| Imm16
| Imm32
| Imm32S
| Imm64
;
4025 i
.types
[this_operand
] &= types
;
4031 static char *i386_scale
PARAMS ((char *));
4038 char *save
= input_line_pointer
;
4040 input_line_pointer
= scale
;
4041 val
= get_absolute_expression ();
4046 i
.log2_scale_factor
= 0;
4049 i
.log2_scale_factor
= 1;
4052 i
.log2_scale_factor
= 2;
4055 i
.log2_scale_factor
= 3;
4059 char sep
= *input_line_pointer
;
4061 *input_line_pointer
= '\0';
4062 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
4064 *input_line_pointer
= sep
;
4065 input_line_pointer
= save
;
4069 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
4071 as_warn (_("scale factor of %d without an index register"),
4072 1 << i
.log2_scale_factor
);
4073 #if SCALE1_WHEN_NO_INDEX
4074 i
.log2_scale_factor
= 0;
4077 scale
= input_line_pointer
;
4078 input_line_pointer
= save
;
4082 static int i386_displacement
PARAMS ((char *, char *));
4085 i386_displacement (disp_start
, disp_end
)
4091 char *save_input_line_pointer
;
4093 char *gotfree_input_line
;
4095 int bigdisp
= Disp32
;
4096 unsigned int types
= Disp
;
4098 if (flag_code
== CODE_64BIT
)
4100 if (i
.prefix
[ADDR_PREFIX
] == 0)
4101 bigdisp
= Disp64
| Disp32S
| Disp32
;
4103 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[ADDR_PREFIX
] != 0))
4105 i
.types
[this_operand
] |= bigdisp
;
4107 exp
= &disp_expressions
[i
.disp_operands
];
4108 i
.op
[this_operand
].disps
= exp
;
4110 save_input_line_pointer
= input_line_pointer
;
4111 input_line_pointer
= disp_start
;
4112 END_STRING_AND_SAVE (disp_end
);
4114 #ifndef GCC_ASM_O_HACK
4115 #define GCC_ASM_O_HACK 0
4118 END_STRING_AND_SAVE (disp_end
+ 1);
4119 if ((i
.types
[this_operand
] & BaseIndex
) != 0
4120 && displacement_string_end
[-1] == '+')
4122 /* This hack is to avoid a warning when using the "o"
4123 constraint within gcc asm statements.
4126 #define _set_tssldt_desc(n,addr,limit,type) \
4127 __asm__ __volatile__ ( \
4129 "movw %w1,2+%0\n\t" \
4131 "movb %b1,4+%0\n\t" \
4132 "movb %4,5+%0\n\t" \
4133 "movb $0,6+%0\n\t" \
4134 "movb %h1,7+%0\n\t" \
4136 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
4138 This works great except that the output assembler ends
4139 up looking a bit weird if it turns out that there is
4140 no offset. You end up producing code that looks like:
4153 So here we provide the missing zero. */
4155 *displacement_string_end
= '0';
4159 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
4160 if (gotfree_input_line
)
4161 input_line_pointer
= gotfree_input_line
;
4164 exp_seg
= expression (exp
);
4167 if (*input_line_pointer
)
4168 as_bad (_("junk `%s' after expression"), input_line_pointer
);
4170 RESTORE_END_STRING (disp_end
+ 1);
4172 RESTORE_END_STRING (disp_end
);
4173 input_line_pointer
= save_input_line_pointer
;
4175 if (gotfree_input_line
)
4176 free (gotfree_input_line
);
4179 /* We do this to make sure that the section symbol is in
4180 the symbol table. We will ultimately change the relocation
4181 to be relative to the beginning of the section. */
4182 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
4183 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
4184 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
4186 if (exp
->X_op
!= O_symbol
)
4188 as_bad (_("bad expression used with @%s"),
4189 (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
4195 if (S_IS_LOCAL (exp
->X_add_symbol
)
4196 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
)
4197 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
4198 exp
->X_op
= O_subtract
;
4199 exp
->X_op_symbol
= GOT_symbol
;
4200 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
4201 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
4202 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
4203 i
.reloc
[this_operand
] = BFD_RELOC_64
;
4205 i
.reloc
[this_operand
] = BFD_RELOC_32
;
4208 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_big
)
4210 /* Missing or bad expr becomes absolute 0. */
4211 as_bad (_("missing or invalid displacement expression `%s' taken as 0"),
4213 exp
->X_op
= O_constant
;
4214 exp
->X_add_number
= 0;
4215 exp
->X_add_symbol
= (symbolS
*) 0;
4216 exp
->X_op_symbol
= (symbolS
*) 0;
4219 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
4220 if (exp
->X_op
!= O_constant
4221 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
4222 && exp_seg
!= absolute_section
4223 && exp_seg
!= text_section
4224 && exp_seg
!= data_section
4225 && exp_seg
!= bss_section
4226 && exp_seg
!= undefined_section
4227 && !bfd_is_com_section (exp_seg
))
4229 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
4234 if (!(i
.types
[this_operand
] & ~Disp
))
4235 i
.types
[this_operand
] &= types
;
4240 static int i386_index_check
PARAMS ((const char *));
4242 /* Make sure the memory operand we've been dealt is valid.
4243 Return 1 on success, 0 on a failure. */
4246 i386_index_check (operand_string
)
4247 const char *operand_string
;
4250 #if INFER_ADDR_PREFIX
4256 if ((current_templates
->start
->cpu_flags
& CpuSVME
)
4257 && current_templates
->end
[-1].operand_types
[0] == AnyMem
)
4259 /* Memory operands of SVME insns are special in that they only allow
4260 rAX as their memory address and ignore any segment override. */
4263 /* SKINIT is even more restrictive: it always requires EAX. */
4264 if (strcmp (current_templates
->start
->name
, "skinit") == 0)
4266 else if (flag_code
== CODE_64BIT
)
4267 RegXX
= i
.prefix
[ADDR_PREFIX
] == 0 ? Reg64
: Reg32
;
4269 RegXX
= (flag_code
== CODE_16BIT
) ^ (i
.prefix
[ADDR_PREFIX
] != 0)
4273 || !(i
.base_reg
->reg_type
& Acc
)
4274 || !(i
.base_reg
->reg_type
& RegXX
)
4276 || (i
.types
[0] & Disp
))
4279 else if (flag_code
== CODE_64BIT
)
4281 unsigned RegXX
= (i
.prefix
[ADDR_PREFIX
] == 0 ? Reg64
: Reg32
);
4284 && ((i
.base_reg
->reg_type
& RegXX
) == 0)
4285 && (i
.base_reg
->reg_type
!= BaseIndex
4288 && ((i
.index_reg
->reg_type
& (RegXX
| BaseIndex
))
4289 != (RegXX
| BaseIndex
))))
4294 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[ADDR_PREFIX
] != 0))
4298 && ((i
.base_reg
->reg_type
& (Reg16
| BaseIndex
| RegRex
))
4299 != (Reg16
| BaseIndex
)))
4301 && (((i
.index_reg
->reg_type
& (Reg16
| BaseIndex
))
4302 != (Reg16
| BaseIndex
))
4304 && i
.base_reg
->reg_num
< 6
4305 && i
.index_reg
->reg_num
>= 6
4306 && i
.log2_scale_factor
== 0))))
4313 && (i
.base_reg
->reg_type
& (Reg32
| RegRex
)) != Reg32
)
4315 && ((i
.index_reg
->reg_type
& (Reg32
| BaseIndex
| RegRex
))
4316 != (Reg32
| BaseIndex
))))
4322 #if INFER_ADDR_PREFIX
4323 if (i
.prefix
[ADDR_PREFIX
] == 0)
4325 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
4327 /* Change the size of any displacement too. At most one of
4328 Disp16 or Disp32 is set.
4329 FIXME. There doesn't seem to be any real need for separate
4330 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
4331 Removing them would probably clean up the code quite a lot. */
4332 if (flag_code
!= CODE_64BIT
&& (i
.types
[this_operand
] & (Disp16
| Disp32
)))
4333 i
.types
[this_operand
] ^= (Disp16
| Disp32
);
4338 as_bad (_("`%s' is not a valid base/index expression"),
4342 as_bad (_("`%s' is not a valid %s bit base/index expression"),
4344 flag_code_names
[flag_code
]);
4349 /* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero
4353 i386_operand (operand_string
)
4354 char *operand_string
;
4358 char *op_string
= operand_string
;
4360 if (is_space_char (*op_string
))
4363 /* We check for an absolute prefix (differentiating,
4364 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
4365 if (*op_string
== ABSOLUTE_PREFIX
)
4368 if (is_space_char (*op_string
))
4370 i
.types
[this_operand
] |= JumpAbsolute
;
4373 /* Check if operand is a register. */
4374 if ((*op_string
== REGISTER_PREFIX
|| allow_naked_reg
)
4375 && (r
= parse_register (op_string
, &end_op
)) != NULL
)
4377 /* Check for a segment override by searching for ':' after a
4378 segment register. */
4380 if (is_space_char (*op_string
))
4382 if (*op_string
== ':' && (r
->reg_type
& (SReg2
| SReg3
)))
4387 i
.seg
[i
.mem_operands
] = &es
;
4390 i
.seg
[i
.mem_operands
] = &cs
;
4393 i
.seg
[i
.mem_operands
] = &ss
;
4396 i
.seg
[i
.mem_operands
] = &ds
;
4399 i
.seg
[i
.mem_operands
] = &fs
;
4402 i
.seg
[i
.mem_operands
] = &gs
;
4406 /* Skip the ':' and whitespace. */
4408 if (is_space_char (*op_string
))
4411 if (!is_digit_char (*op_string
)
4412 && !is_identifier_char (*op_string
)
4413 && *op_string
!= '('
4414 && *op_string
!= ABSOLUTE_PREFIX
)
4416 as_bad (_("bad memory operand `%s'"), op_string
);
4419 /* Handle case of %es:*foo. */
4420 if (*op_string
== ABSOLUTE_PREFIX
)
4423 if (is_space_char (*op_string
))
4425 i
.types
[this_operand
] |= JumpAbsolute
;
4427 goto do_memory_reference
;
4431 as_bad (_("junk `%s' after register"), op_string
);
4434 i
.types
[this_operand
] |= r
->reg_type
& ~BaseIndex
;
4435 i
.op
[this_operand
].regs
= r
;
4438 else if (*op_string
== REGISTER_PREFIX
)
4440 as_bad (_("bad register name `%s'"), op_string
);
4443 else if (*op_string
== IMMEDIATE_PREFIX
)
4446 if (i
.types
[this_operand
] & JumpAbsolute
)
4448 as_bad (_("immediate operand illegal with absolute jump"));
4451 if (!i386_immediate (op_string
))
4454 else if (is_digit_char (*op_string
)
4455 || is_identifier_char (*op_string
)
4456 || *op_string
== '(')
4458 /* This is a memory reference of some sort. */
4461 /* Start and end of displacement string expression (if found). */
4462 char *displacement_string_start
;
4463 char *displacement_string_end
;
4465 do_memory_reference
:
4466 if ((i
.mem_operands
== 1
4467 && (current_templates
->start
->opcode_modifier
& IsString
) == 0)
4468 || i
.mem_operands
== 2)
4470 as_bad (_("too many memory references for `%s'"),
4471 current_templates
->start
->name
);
4475 /* Check for base index form. We detect the base index form by
4476 looking for an ')' at the end of the operand, searching
4477 for the '(' matching it, and finding a REGISTER_PREFIX or ','
4479 base_string
= op_string
+ strlen (op_string
);
4482 if (is_space_char (*base_string
))
4485 /* If we only have a displacement, set-up for it to be parsed later. */
4486 displacement_string_start
= op_string
;
4487 displacement_string_end
= base_string
+ 1;
4489 if (*base_string
== ')')
4492 unsigned int parens_balanced
= 1;
4493 /* We've already checked that the number of left & right ()'s are
4494 equal, so this loop will not be infinite. */
4498 if (*base_string
== ')')
4500 if (*base_string
== '(')
4503 while (parens_balanced
);
4505 temp_string
= base_string
;
4507 /* Skip past '(' and whitespace. */
4509 if (is_space_char (*base_string
))
4512 if (*base_string
== ','
4513 || ((*base_string
== REGISTER_PREFIX
|| allow_naked_reg
)
4514 && (i
.base_reg
= parse_register (base_string
, &end_op
)) != NULL
))
4516 displacement_string_end
= temp_string
;
4518 i
.types
[this_operand
] |= BaseIndex
;
4522 base_string
= end_op
;
4523 if (is_space_char (*base_string
))
4527 /* There may be an index reg or scale factor here. */
4528 if (*base_string
== ',')
4531 if (is_space_char (*base_string
))
4534 if ((*base_string
== REGISTER_PREFIX
|| allow_naked_reg
)
4535 && (i
.index_reg
= parse_register (base_string
, &end_op
)) != NULL
)
4537 base_string
= end_op
;
4538 if (is_space_char (*base_string
))
4540 if (*base_string
== ',')
4543 if (is_space_char (*base_string
))
4546 else if (*base_string
!= ')')
4548 as_bad (_("expecting `,' or `)' after index register in `%s'"),
4553 else if (*base_string
== REGISTER_PREFIX
)
4555 as_bad (_("bad register name `%s'"), base_string
);
4559 /* Check for scale factor. */
4560 if (*base_string
!= ')')
4562 char *end_scale
= i386_scale (base_string
);
4567 base_string
= end_scale
;
4568 if (is_space_char (*base_string
))
4570 if (*base_string
!= ')')
4572 as_bad (_("expecting `)' after scale factor in `%s'"),
4577 else if (!i
.index_reg
)
4579 as_bad (_("expecting index register or scale factor after `,'; got '%c'"),
4584 else if (*base_string
!= ')')
4586 as_bad (_("expecting `,' or `)' after base register in `%s'"),
4591 else if (*base_string
== REGISTER_PREFIX
)
4593 as_bad (_("bad register name `%s'"), base_string
);
4598 /* If there's an expression beginning the operand, parse it,
4599 assuming displacement_string_start and
4600 displacement_string_end are meaningful. */
4601 if (displacement_string_start
!= displacement_string_end
)
4603 if (!i386_displacement (displacement_string_start
,
4604 displacement_string_end
))
4608 /* Special case for (%dx) while doing input/output op. */
4610 && i
.base_reg
->reg_type
== (Reg16
| InOutPortReg
)
4612 && i
.log2_scale_factor
== 0
4613 && i
.seg
[i
.mem_operands
] == 0
4614 && (i
.types
[this_operand
] & Disp
) == 0)
4616 i
.types
[this_operand
] = InOutPortReg
;
4620 if (i386_index_check (operand_string
) == 0)
4626 /* It's not a memory operand; argh! */
4627 as_bad (_("invalid char %s beginning operand %d `%s'"),
4628 output_invalid (*op_string
),
4633 return 1; /* Normal return. */
4636 /* md_estimate_size_before_relax()
4638 Called just before relax() for rs_machine_dependent frags. The x86
4639 assembler uses these frags to handle variable size jump
4642 Any symbol that is now undefined will not become defined.
4643 Return the correct fr_subtype in the frag.
4644 Return the initial "guess for variable size of frag" to caller.
4645 The guess is actually the growth beyond the fixed part. Whatever
4646 we do to grow the fixed or variable part contributes to our
4650 md_estimate_size_before_relax (fragP
, segment
)
4654 /* We've already got fragP->fr_subtype right; all we have to do is
4655 check for un-relaxable symbols. On an ELF system, we can't relax
4656 an externally visible symbol, because it may be overridden by a
4658 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
4659 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4660 || (OUTPUT_FLAVOR
== bfd_target_elf_flavour
4661 && (S_IS_EXTERNAL (fragP
->fr_symbol
)
4662 || S_IS_WEAK (fragP
->fr_symbol
)))
4666 /* Symbol is undefined in this segment, or we need to keep a
4667 reloc so that weak symbols can be overridden. */
4668 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
4669 enum bfd_reloc_code_real reloc_type
;
4670 unsigned char *opcode
;
4673 if (fragP
->fr_var
!= NO_RELOC
)
4674 reloc_type
= fragP
->fr_var
;
4676 reloc_type
= BFD_RELOC_16_PCREL
;
4678 reloc_type
= BFD_RELOC_32_PCREL
;
4680 old_fr_fix
= fragP
->fr_fix
;
4681 opcode
= (unsigned char *) fragP
->fr_opcode
;
4683 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
4686 /* Make jmp (0xeb) a (d)word displacement jump. */
4688 fragP
->fr_fix
+= size
;
4689 fix_new (fragP
, old_fr_fix
, size
,
4691 fragP
->fr_offset
, 1,
4697 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
4699 /* Negate the condition, and branch past an
4700 unconditional jump. */
4703 /* Insert an unconditional jump. */
4705 /* We added two extra opcode bytes, and have a two byte
4707 fragP
->fr_fix
+= 2 + 2;
4708 fix_new (fragP
, old_fr_fix
+ 2, 2,
4710 fragP
->fr_offset
, 1,
4717 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
4722 fixP
= fix_new (fragP
, old_fr_fix
, 1,
4724 fragP
->fr_offset
, 1,
4726 fixP
->fx_signed
= 1;
4730 /* This changes the byte-displacement jump 0x7N
4731 to the (d)word-displacement jump 0x0f,0x8N. */
4732 opcode
[1] = opcode
[0] + 0x10;
4733 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
4734 /* We've added an opcode byte. */
4735 fragP
->fr_fix
+= 1 + size
;
4736 fix_new (fragP
, old_fr_fix
+ 1, size
,
4738 fragP
->fr_offset
, 1,
4743 BAD_CASE (fragP
->fr_subtype
);
4747 return fragP
->fr_fix
- old_fr_fix
;
4750 /* Guess size depending on current relax state. Initially the relax
4751 state will correspond to a short jump and we return 1, because
4752 the variable part of the frag (the branch offset) is one byte
4753 long. However, we can relax a section more than once and in that
4754 case we must either set fr_subtype back to the unrelaxed state,
4755 or return the value for the appropriate branch. */
4756 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
4759 /* Called after relax() is finished.
4761 In: Address of frag.
4762 fr_type == rs_machine_dependent.
4763 fr_subtype is what the address relaxed to.
4765 Out: Any fixSs and constants are set up.
4766 Caller will turn frag into a ".space 0". */
4769 md_convert_frag (abfd
, sec
, fragP
)
4770 bfd
*abfd ATTRIBUTE_UNUSED
;
4771 segT sec ATTRIBUTE_UNUSED
;
4774 unsigned char *opcode
;
4775 unsigned char *where_to_put_displacement
= NULL
;
4776 offsetT target_address
;
4777 offsetT opcode_address
;
4778 unsigned int extension
= 0;
4779 offsetT displacement_from_opcode_start
;
4781 opcode
= (unsigned char *) fragP
->fr_opcode
;
4783 /* Address we want to reach in file space. */
4784 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
4786 /* Address opcode resides at in file space. */
4787 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
4789 /* Displacement from opcode start to fill into instruction. */
4790 displacement_from_opcode_start
= target_address
- opcode_address
;
4792 if ((fragP
->fr_subtype
& BIG
) == 0)
4794 /* Don't have to change opcode. */
4795 extension
= 1; /* 1 opcode + 1 displacement */
4796 where_to_put_displacement
= &opcode
[1];
4800 if (no_cond_jump_promotion
4801 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
4802 as_warn_where (fragP
->fr_file
, fragP
->fr_line
, _("long jump required"));
4804 switch (fragP
->fr_subtype
)
4806 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
4807 extension
= 4; /* 1 opcode + 4 displacement */
4809 where_to_put_displacement
= &opcode
[1];
4812 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
4813 extension
= 2; /* 1 opcode + 2 displacement */
4815 where_to_put_displacement
= &opcode
[1];
4818 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
4819 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
4820 extension
= 5; /* 2 opcode + 4 displacement */
4821 opcode
[1] = opcode
[0] + 0x10;
4822 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
4823 where_to_put_displacement
= &opcode
[2];
4826 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
4827 extension
= 3; /* 2 opcode + 2 displacement */
4828 opcode
[1] = opcode
[0] + 0x10;
4829 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
4830 where_to_put_displacement
= &opcode
[2];
4833 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
4838 where_to_put_displacement
= &opcode
[3];
4842 BAD_CASE (fragP
->fr_subtype
);
4847 /* Now put displacement after opcode. */
4848 md_number_to_chars ((char *) where_to_put_displacement
,
4849 (valueT
) (displacement_from_opcode_start
- extension
),
4850 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
4851 fragP
->fr_fix
+= extension
;
4854 /* Size of byte displacement jmp. */
4855 int md_short_jump_size
= 2;
4857 /* Size of dword displacement jmp. */
4858 int md_long_jump_size
= 5;
4860 /* Size of relocation record. */
4861 const int md_reloc_size
= 8;
4864 md_create_short_jump (ptr
, from_addr
, to_addr
, frag
, to_symbol
)
4866 addressT from_addr
, to_addr
;
4867 fragS
*frag ATTRIBUTE_UNUSED
;
4868 symbolS
*to_symbol ATTRIBUTE_UNUSED
;
4872 offset
= to_addr
- (from_addr
+ 2);
4873 /* Opcode for byte-disp jump. */
4874 md_number_to_chars (ptr
, (valueT
) 0xeb, 1);
4875 md_number_to_chars (ptr
+ 1, (valueT
) offset
, 1);
4879 md_create_long_jump (ptr
, from_addr
, to_addr
, frag
, to_symbol
)
4881 addressT from_addr
, to_addr
;
4882 fragS
*frag ATTRIBUTE_UNUSED
;
4883 symbolS
*to_symbol ATTRIBUTE_UNUSED
;
4887 offset
= to_addr
- (from_addr
+ 5);
4888 md_number_to_chars (ptr
, (valueT
) 0xe9, 1);
4889 md_number_to_chars (ptr
+ 1, (valueT
) offset
, 4);
4892 /* Apply a fixup (fixS) to segment data, once it has been determined
4893 by our caller that we have all the info we need to fix it up.
4895 On the 386, immediates, displacements, and data pointers are all in
4896 the same (little-endian) format, so we don't need to care about which
4900 md_apply_fix (fixP
, valP
, seg
)
4901 /* The fix we're to put in. */
4903 /* Pointer to the value of the bits. */
4905 /* Segment fix is from. */
4906 segT seg ATTRIBUTE_UNUSED
;
4908 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
4909 valueT value
= *valP
;
4911 #if !defined (TE_Mach)
4914 switch (fixP
->fx_r_type
)
4920 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
4923 case BFD_RELOC_X86_64_32S
:
4924 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
4927 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
4930 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
4935 if (fixP
->fx_addsy
!= NULL
4936 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
4937 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
4938 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
4939 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
4940 && !use_rela_relocations
)
4942 /* This is a hack. There should be a better way to handle this.
4943 This covers for the fact that bfd_install_relocation will
4944 subtract the current location (for partial_inplace, PC relative
4945 relocations); see more below. */
4947 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
4949 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
4952 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
4954 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4955 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
4957 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
4960 || (symbol_section_p (fixP
->fx_addsy
)
4961 && sym_seg
!= absolute_section
))
4962 && !generic_force_reloc (fixP
))
4964 /* Yes, we add the values in twice. This is because
4965 bfd_install_relocation subtracts them out again. I think
4966 bfd_install_relocation is broken, but I don't dare change
4968 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
4972 #if defined (OBJ_COFF) && defined (TE_PE)
4973 /* For some reason, the PE format does not store a
4974 section address offset for a PC relative symbol. */
4975 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
4976 #if defined(BFD_ASSEMBLER) || defined(S_IS_WEAK)
4977 || S_IS_WEAK (fixP
->fx_addsy
)
4980 value
+= md_pcrel_from (fixP
);
4984 /* Fix a few things - the dynamic linker expects certain values here,
4985 and we must not disappoint it. */
4986 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4987 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
4989 switch (fixP
->fx_r_type
)
4991 case BFD_RELOC_386_PLT32
:
4992 case BFD_RELOC_X86_64_PLT32
:
4993 /* Make the jump instruction point to the address of the operand. At
4994 runtime we merely add the offset to the actual PLT entry. */
4998 case BFD_RELOC_386_TLS_GD
:
4999 case BFD_RELOC_386_TLS_LDM
:
5000 case BFD_RELOC_386_TLS_IE_32
:
5001 case BFD_RELOC_386_TLS_IE
:
5002 case BFD_RELOC_386_TLS_GOTIE
:
5003 case BFD_RELOC_X86_64_TLSGD
:
5004 case BFD_RELOC_X86_64_TLSLD
:
5005 case BFD_RELOC_X86_64_GOTTPOFF
:
5006 value
= 0; /* Fully resolved at runtime. No addend. */
5008 case BFD_RELOC_386_TLS_LE
:
5009 case BFD_RELOC_386_TLS_LDO_32
:
5010 case BFD_RELOC_386_TLS_LE_32
:
5011 case BFD_RELOC_X86_64_DTPOFF32
:
5012 case BFD_RELOC_X86_64_DTPOFF64
:
5013 case BFD_RELOC_X86_64_TPOFF32
:
5014 case BFD_RELOC_X86_64_TPOFF64
:
5015 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
5018 case BFD_RELOC_386_GOT32
:
5019 case BFD_RELOC_X86_64_GOT32
:
5020 value
= 0; /* Fully resolved at runtime. No addend. */
5023 case BFD_RELOC_VTABLE_INHERIT
:
5024 case BFD_RELOC_VTABLE_ENTRY
:
5031 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
5033 #endif /* !defined (TE_Mach) */
5035 /* Are we finished with this relocation now? */
5036 if (fixP
->fx_addsy
== NULL
)
5038 else if (use_rela_relocations
)
5040 fixP
->fx_no_overflow
= 1;
5041 /* Remember value for tc_gen_reloc. */
5042 fixP
->fx_addnumber
= value
;
5046 md_number_to_chars (p
, value
, fixP
->fx_size
);
5049 #define MAX_LITTLENUMS 6
5051 /* Turn the string pointed to by litP into a floating point constant
5052 of type TYPE, and emit the appropriate bytes. The number of
5053 LITTLENUMS emitted is stored in *SIZEP. An error message is
5054 returned, or NULL on OK. */
5057 md_atof (type
, litP
, sizeP
)
5063 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
5064 LITTLENUM_TYPE
*wordP
;
5086 return _("Bad call to md_atof ()");
5088 t
= atof_ieee (input_line_pointer
, type
, words
);
5090 input_line_pointer
= t
;
5092 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
5093 /* This loops outputs the LITTLENUMs in REVERSE order; in accord with
5094 the bigendian 386. */
5095 for (wordP
= words
+ prec
- 1; prec
--;)
5097 md_number_to_chars (litP
, (valueT
) (*wordP
--), sizeof (LITTLENUM_TYPE
));
5098 litP
+= sizeof (LITTLENUM_TYPE
);
5103 static char output_invalid_buf
[8];
5110 sprintf (output_invalid_buf
, "'%c'", c
);
5112 sprintf (output_invalid_buf
, "(0x%x)", (unsigned) c
);
5113 return output_invalid_buf
;
5116 /* REG_STRING starts *before* REGISTER_PREFIX. */
5118 static const reg_entry
*
5119 parse_register (reg_string
, end_op
)
5123 char *s
= reg_string
;
5125 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
5128 /* Skip possible REGISTER_PREFIX and possible whitespace. */
5129 if (*s
== REGISTER_PREFIX
)
5132 if (is_space_char (*s
))
5136 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
5138 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
5139 return (const reg_entry
*) NULL
;
5143 /* For naked regs, make sure that we are not dealing with an identifier.
5144 This prevents confusing an identifier like `eax_var' with register
5146 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
5147 return (const reg_entry
*) NULL
;
5151 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
5153 /* Handle floating point regs, allowing spaces in the (i) part. */
5154 if (r
== i386_regtab
/* %st is first entry of table */)
5156 if (is_space_char (*s
))
5161 if (is_space_char (*s
))
5163 if (*s
>= '0' && *s
<= '7')
5165 r
= &i386_float_regtab
[*s
- '0'];
5167 if (is_space_char (*s
))
5175 /* We have "%st(" then garbage. */
5176 return (const reg_entry
*) NULL
;
5181 && ((r
->reg_flags
& (RegRex64
| RegRex
)) | (r
->reg_type
& Reg64
)) != 0
5182 && (r
->reg_type
!= Control
|| !(cpu_arch_flags
& CpuSledgehammer
))
5183 && flag_code
!= CODE_64BIT
)
5184 return (const reg_entry
*) NULL
;
5189 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5190 const char *md_shortopts
= "kVQ:sqn";
5192 const char *md_shortopts
= "qn";
5195 struct option md_longopts
[] = {
5196 #define OPTION_32 (OPTION_MD_BASE + 0)
5197 {"32", no_argument
, NULL
, OPTION_32
},
5198 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5199 #define OPTION_64 (OPTION_MD_BASE + 1)
5200 {"64", no_argument
, NULL
, OPTION_64
},
5202 {NULL
, no_argument
, NULL
, 0}
5204 size_t md_longopts_size
= sizeof (md_longopts
);
5207 md_parse_option (c
, arg
)
5209 char *arg ATTRIBUTE_UNUSED
;
5214 optimize_align_code
= 0;
5221 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5222 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
5223 should be emitted or not. FIXME: Not implemented. */
5227 /* -V: SVR4 argument to print version ID. */
5229 print_version_id ();
5232 /* -k: Ignore for FreeBSD compatibility. */
5237 /* -s: On i386 Solaris, this tells the native assembler to use
5238 .stab instead of .stab.excl. We always use .stab anyhow. */
5243 const char **list
, **l
;
5245 list
= bfd_target_list ();
5246 for (l
= list
; *l
!= NULL
; l
++)
5247 if (strcmp (*l
, "elf64-x86-64") == 0)
5249 default_arch
= "x86_64";
5253 as_fatal (_("No compiled in support for x86_64"));
5260 default_arch
= "i386";
5270 md_show_usage (stream
)
5273 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5274 fprintf (stream
, _("\
5276 -V print assembler version number\n\
5278 -n Do not optimize code alignment\n\
5279 -q quieten some warnings\n\
5282 fprintf (stream
, _("\
5283 -n Do not optimize code alignment\n\
5284 -q quieten some warnings\n"));
5288 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
5289 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
5291 /* Pick the target format to use. */
5294 i386_target_format ()
5296 if (!strcmp (default_arch
, "x86_64"))
5297 set_code_flag (CODE_64BIT
);
5298 else if (!strcmp (default_arch
, "i386"))
5299 set_code_flag (CODE_32BIT
);
5301 as_fatal (_("Unknown architecture"));
5302 switch (OUTPUT_FLAVOR
)
5304 #ifdef OBJ_MAYBE_AOUT
5305 case bfd_target_aout_flavour
:
5306 return AOUT_TARGET_FORMAT
;
5308 #ifdef OBJ_MAYBE_COFF
5309 case bfd_target_coff_flavour
:
5312 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
5313 case bfd_target_elf_flavour
:
5315 if (flag_code
== CODE_64BIT
)
5316 use_rela_relocations
= 1;
5317 return flag_code
== CODE_64BIT
? "elf64-x86-64" : ELF_TARGET_FORMAT
;
5326 #endif /* OBJ_MAYBE_ more than one */
5328 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
5329 void i386_elf_emit_arch_note ()
5331 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
5332 && cpu_arch_name
!= NULL
)
5335 asection
*seg
= now_seg
;
5336 subsegT subseg
= now_subseg
;
5337 Elf_Internal_Note i_note
;
5338 Elf_External_Note e_note
;
5339 asection
*note_secp
;
5342 /* Create the .note section. */
5343 note_secp
= subseg_new (".note", 0);
5344 bfd_set_section_flags (stdoutput
,
5346 SEC_HAS_CONTENTS
| SEC_READONLY
);
5348 /* Process the arch string. */
5349 len
= strlen (cpu_arch_name
);
5351 i_note
.namesz
= len
+ 1;
5353 i_note
.type
= NT_ARCH
;
5354 p
= frag_more (sizeof (e_note
.namesz
));
5355 md_number_to_chars (p
, (valueT
) i_note
.namesz
, sizeof (e_note
.namesz
));
5356 p
= frag_more (sizeof (e_note
.descsz
));
5357 md_number_to_chars (p
, (valueT
) i_note
.descsz
, sizeof (e_note
.descsz
));
5358 p
= frag_more (sizeof (e_note
.type
));
5359 md_number_to_chars (p
, (valueT
) i_note
.type
, sizeof (e_note
.type
));
5360 p
= frag_more (len
+ 1);
5361 strcpy (p
, cpu_arch_name
);
5363 frag_align (2, 0, 0);
5365 subseg_set (seg
, subseg
);
5371 md_undefined_symbol (name
)
5374 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
5375 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
5376 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
5377 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
5381 if (symbol_find (name
))
5382 as_bad (_("GOT already in symbol table"));
5383 GOT_symbol
= symbol_new (name
, undefined_section
,
5384 (valueT
) 0, &zero_address_frag
);
5391 /* Round up a section size to the appropriate boundary. */
5394 md_section_align (segment
, size
)
5395 segT segment ATTRIBUTE_UNUSED
;
5398 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
5399 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
5401 /* For a.out, force the section size to be aligned. If we don't do
5402 this, BFD will align it for us, but it will not write out the
5403 final bytes of the section. This may be a bug in BFD, but it is
5404 easier to fix it here since that is how the other a.out targets
5408 align
= bfd_get_section_alignment (stdoutput
, segment
);
5409 size
= ((size
+ (1 << align
) - 1) & ((valueT
) -1 << align
));
5416 /* On the i386, PC-relative offsets are relative to the start of the
5417 next instruction. That is, the address of the offset, plus its
5418 size, since the offset is always the last part of the insn. */
5421 md_pcrel_from (fixP
)
5424 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
5431 int ignore ATTRIBUTE_UNUSED
;
5435 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5437 obj_elf_section_change_hook ();
5439 temp
= get_absolute_expression ();
5440 subseg_set (bss_section
, (subsegT
) temp
);
5441 demand_empty_rest_of_line ();
5447 i386_validate_fix (fixp
)
5450 if (fixp
->fx_subsy
&& fixp
->fx_subsy
== GOT_symbol
)
5452 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
5454 if (flag_code
!= CODE_64BIT
)
5456 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
5460 if (flag_code
!= CODE_64BIT
)
5461 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
5463 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
5470 tc_gen_reloc (section
, fixp
)
5471 asection
*section ATTRIBUTE_UNUSED
;
5475 bfd_reloc_code_real_type code
;
5477 switch (fixp
->fx_r_type
)
5479 case BFD_RELOC_X86_64_PLT32
:
5480 case BFD_RELOC_X86_64_GOT32
:
5481 case BFD_RELOC_X86_64_GOTPCREL
:
5482 case BFD_RELOC_386_PLT32
:
5483 case BFD_RELOC_386_GOT32
:
5484 case BFD_RELOC_386_GOTOFF
:
5485 case BFD_RELOC_386_GOTPC
:
5486 case BFD_RELOC_386_TLS_GD
:
5487 case BFD_RELOC_386_TLS_LDM
:
5488 case BFD_RELOC_386_TLS_LDO_32
:
5489 case BFD_RELOC_386_TLS_IE_32
:
5490 case BFD_RELOC_386_TLS_IE
:
5491 case BFD_RELOC_386_TLS_GOTIE
:
5492 case BFD_RELOC_386_TLS_LE_32
:
5493 case BFD_RELOC_386_TLS_LE
:
5494 case BFD_RELOC_X86_64_TLSGD
:
5495 case BFD_RELOC_X86_64_TLSLD
:
5496 case BFD_RELOC_X86_64_DTPOFF32
:
5497 case BFD_RELOC_X86_64_DTPOFF64
:
5498 case BFD_RELOC_X86_64_GOTTPOFF
:
5499 case BFD_RELOC_X86_64_TPOFF32
:
5500 case BFD_RELOC_X86_64_TPOFF64
:
5501 case BFD_RELOC_X86_64_GOTOFF64
:
5502 case BFD_RELOC_X86_64_GOTPC32
:
5504 case BFD_RELOC_VTABLE_ENTRY
:
5505 case BFD_RELOC_VTABLE_INHERIT
:
5507 case BFD_RELOC_32_SECREL
:
5509 code
= fixp
->fx_r_type
;
5511 case BFD_RELOC_X86_64_32S
:
5512 if (!fixp
->fx_pcrel
)
5514 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
5515 code
= fixp
->fx_r_type
;
5521 switch (fixp
->fx_size
)
5524 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
5525 _("can not do %d byte pc-relative relocation"),
5527 code
= BFD_RELOC_32_PCREL
;
5529 case 1: code
= BFD_RELOC_8_PCREL
; break;
5530 case 2: code
= BFD_RELOC_16_PCREL
; break;
5531 case 4: code
= BFD_RELOC_32_PCREL
; break;
5533 case 8: code
= BFD_RELOC_64_PCREL
; break;
5539 switch (fixp
->fx_size
)
5542 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
5543 _("can not do %d byte relocation"),
5545 code
= BFD_RELOC_32
;
5547 case 1: code
= BFD_RELOC_8
; break;
5548 case 2: code
= BFD_RELOC_16
; break;
5549 case 4: code
= BFD_RELOC_32
; break;
5551 case 8: code
= BFD_RELOC_64
; break;
5558 if ((code
== BFD_RELOC_32
|| code
== BFD_RELOC_32_PCREL
)
5560 && fixp
->fx_addsy
== GOT_symbol
)
5562 if (flag_code
!= CODE_64BIT
)
5563 code
= BFD_RELOC_386_GOTPC
;
5565 code
= BFD_RELOC_X86_64_GOTPC32
;
5568 rel
= (arelent
*) xmalloc (sizeof (arelent
));
5569 rel
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
5570 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
5572 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
5574 if (!use_rela_relocations
)
5576 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
5577 vtable entry to be used in the relocation's section offset. */
5578 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
5579 rel
->address
= fixp
->fx_offset
;
5583 /* Use the rela in 64bit mode. */
5586 if (!fixp
->fx_pcrel
)
5587 rel
->addend
= fixp
->fx_offset
;
5591 case BFD_RELOC_X86_64_PLT32
:
5592 case BFD_RELOC_X86_64_GOT32
:
5593 case BFD_RELOC_X86_64_GOTPCREL
:
5594 case BFD_RELOC_X86_64_TLSGD
:
5595 case BFD_RELOC_X86_64_TLSLD
:
5596 case BFD_RELOC_X86_64_GOTTPOFF
:
5597 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
5600 rel
->addend
= (section
->vma
5602 + fixp
->fx_addnumber
5603 + md_pcrel_from (fixp
));
5608 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
5609 if (rel
->howto
== NULL
)
5611 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
5612 _("cannot represent relocation type %s"),
5613 bfd_get_reloc_code_name (code
));
5614 /* Set howto to a garbage value so that we can keep going. */
5615 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
5616 assert (rel
->howto
!= NULL
);
5623 /* Parse operands using Intel syntax. This implements a recursive descent
5624 parser based on the BNF grammar published in Appendix B of the MASM 6.1
5627 FIXME: We do not recognize the full operand grammar defined in the MASM
5628 documentation. In particular, all the structure/union and
5629 high-level macro operands are missing.
5631 Uppercase words are terminals, lower case words are non-terminals.
5632 Objects surrounded by double brackets '[[' ']]' are optional. Vertical
5633 bars '|' denote choices. Most grammar productions are implemented in
5634 functions called 'intel_<production>'.
5636 Initial production is 'expr'.
5642 binOp & | AND | \| | OR | ^ | XOR
5644 byteRegister AL | AH | BL | BH | CL | CH | DL | DH
5646 constant digits [[ radixOverride ]]
5648 dataType BYTE | WORD | DWORD | FWORD | QWORD | TBYTE | OWORD | XMMWORD
5686 => expr expr cmpOp e04
5689 gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX
5690 | BP | EBP | SP | ESP | DI | EDI | SI | ESI
5692 hexdigit a | b | c | d | e | f
5693 | A | B | C | D | E | F
5699 mulOp * | / | % | MOD | << | SHL | >> | SHR
5703 register specialRegister
5707 segmentRegister CS | DS | ES | FS | GS | SS
5709 specialRegister CR0 | CR2 | CR3 | CR4
5710 | DR0 | DR1 | DR2 | DR3 | DR6 | DR7
5711 | TR3 | TR4 | TR5 | TR6 | TR7
5713 We simplify the grammar in obvious places (e.g., register parsing is
5714 done by calling parse_register) and eliminate immediate left recursion
5715 to implement a recursive-descent parser.
5719 expr' cmpOp e04 expr'
5770 /* Parsing structure for the intel syntax parser. Used to implement the
5771 semantic actions for the operand grammar. */
5772 struct intel_parser_s
5774 char *op_string
; /* The string being parsed. */
5775 int got_a_float
; /* Whether the operand is a float. */
5776 int op_modifier
; /* Operand modifier. */
5777 int is_mem
; /* 1 if operand is memory reference. */
5778 int in_offset
; /* >=1 if parsing operand of offset. */
5779 int in_bracket
; /* >=1 if parsing operand in brackets. */
5780 const reg_entry
*reg
; /* Last register reference found. */
5781 char *disp
; /* Displacement string being built. */
5782 char *next_operand
; /* Resume point when splitting operands. */
5785 static struct intel_parser_s intel_parser
;
5787 /* Token structure for parsing intel syntax. */
5790 int code
; /* Token code. */
5791 const reg_entry
*reg
; /* Register entry for register tokens. */
5792 char *str
; /* String representation. */
5795 static struct intel_token cur_token
, prev_token
;
5797 /* Token codes for the intel parser. Since T_SHORT is already used
5798 by COFF, undefine it first to prevent a warning. */
5817 /* Prototypes for intel parser functions. */
5818 static int intel_match_token
PARAMS ((int code
));
5819 static void intel_get_token
PARAMS ((void));
5820 static void intel_putback_token
PARAMS ((void));
5821 static int intel_expr
PARAMS ((void));
5822 static int intel_e04
PARAMS ((void));
5823 static int intel_e05
PARAMS ((void));
5824 static int intel_e06
PARAMS ((void));
5825 static int intel_e09
PARAMS ((void));
5826 static int intel_bracket_expr
PARAMS ((void));
5827 static int intel_e10
PARAMS ((void));
5828 static int intel_e11
PARAMS ((void));
5831 i386_intel_operand (operand_string
, got_a_float
)
5832 char *operand_string
;
5838 p
= intel_parser
.op_string
= xstrdup (operand_string
);
5839 intel_parser
.disp
= (char *) xmalloc (strlen (operand_string
) + 1);
5843 /* Initialize token holders. */
5844 cur_token
.code
= prev_token
.code
= T_NIL
;
5845 cur_token
.reg
= prev_token
.reg
= NULL
;
5846 cur_token
.str
= prev_token
.str
= NULL
;
5848 /* Initialize parser structure. */
5849 intel_parser
.got_a_float
= got_a_float
;
5850 intel_parser
.op_modifier
= 0;
5851 intel_parser
.is_mem
= 0;
5852 intel_parser
.in_offset
= 0;
5853 intel_parser
.in_bracket
= 0;
5854 intel_parser
.reg
= NULL
;
5855 intel_parser
.disp
[0] = '\0';
5856 intel_parser
.next_operand
= NULL
;
5858 /* Read the first token and start the parser. */
5860 ret
= intel_expr ();
5865 if (cur_token
.code
!= T_NIL
)
5867 as_bad (_("invalid operand for '%s' ('%s' unexpected)"),
5868 current_templates
->start
->name
, cur_token
.str
);
5871 /* If we found a memory reference, hand it over to i386_displacement
5872 to fill in the rest of the operand fields. */
5873 else if (intel_parser
.is_mem
)
5875 if ((i
.mem_operands
== 1
5876 && (current_templates
->start
->opcode_modifier
& IsString
) == 0)
5877 || i
.mem_operands
== 2)
5879 as_bad (_("too many memory references for '%s'"),
5880 current_templates
->start
->name
);
5885 char *s
= intel_parser
.disp
;
5888 if (!quiet_warnings
&& intel_parser
.is_mem
< 0)
5889 /* See the comments in intel_bracket_expr. */
5890 as_warn (_("Treating `%s' as memory reference"), operand_string
);
5892 /* Add the displacement expression. */
5894 ret
= i386_displacement (s
, s
+ strlen (s
));
5897 /* Swap base and index in 16-bit memory operands like
5898 [si+bx]. Since i386_index_check is also used in AT&T
5899 mode we have to do that here. */
5902 && (i
.base_reg
->reg_type
& Reg16
)
5903 && (i
.index_reg
->reg_type
& Reg16
)
5904 && i
.base_reg
->reg_num
>= 6
5905 && i
.index_reg
->reg_num
< 6)
5907 const reg_entry
*base
= i
.index_reg
;
5909 i
.index_reg
= i
.base_reg
;
5912 ret
= i386_index_check (operand_string
);
5917 /* Constant and OFFSET expressions are handled by i386_immediate. */
5918 else if ((intel_parser
.op_modifier
& (1 << T_OFFSET
))
5919 || intel_parser
.reg
== NULL
)
5920 ret
= i386_immediate (intel_parser
.disp
);
5922 if (intel_parser
.next_operand
&& this_operand
>= MAX_OPERANDS
- 1)
5924 if (!ret
|| !intel_parser
.next_operand
)
5926 intel_parser
.op_string
= intel_parser
.next_operand
;
5927 this_operand
= i
.operands
++;
5931 free (intel_parser
.disp
);
5936 #define NUM_ADDRESS_REGS (!!i.base_reg + !!i.index_reg)
5940 expr' cmpOp e04 expr'
5945 /* XXX Implement the comparison operators. */
5946 return intel_e04 ();
5963 if (nregs
>= 0 && NUM_ADDRESS_REGS
> nregs
)
5964 i
.base_reg
= i386_regtab
+ REGNAM_AL
; /* al is invalid as base */
5966 if (cur_token
.code
== '+')
5968 else if (cur_token
.code
== '-')
5969 nregs
= NUM_ADDRESS_REGS
;
5973 strcat (intel_parser
.disp
, cur_token
.str
);
5974 intel_match_token (cur_token
.code
);
5985 int nregs
= ~NUM_ADDRESS_REGS
;
5992 if (cur_token
.code
== '&' || cur_token
.code
== '|' || cur_token
.code
== '^')
5996 str
[0] = cur_token
.code
;
5998 strcat (intel_parser
.disp
, str
);
6003 intel_match_token (cur_token
.code
);
6008 if (nregs
>= 0 && NUM_ADDRESS_REGS
> nregs
)
6009 i
.base_reg
= i386_regtab
+ REGNAM_AL
+ 1; /* cl is invalid as base */
6020 int nregs
= ~NUM_ADDRESS_REGS
;
6027 if (cur_token
.code
== '*' || cur_token
.code
== '/' || cur_token
.code
== '%')
6031 str
[0] = cur_token
.code
;
6033 strcat (intel_parser
.disp
, str
);
6035 else if (cur_token
.code
== T_SHL
)
6036 strcat (intel_parser
.disp
, "<<");
6037 else if (cur_token
.code
== T_SHR
)
6038 strcat (intel_parser
.disp
, ">>");
6042 intel_match_token (cur_token
.code
);
6047 if (nregs
>= 0 && NUM_ADDRESS_REGS
> nregs
)
6048 i
.base_reg
= i386_regtab
+ REGNAM_AL
+ 2; /* dl is invalid as base */
6066 int nregs
= ~NUM_ADDRESS_REGS
;
6071 /* Don't consume constants here. */
6072 if (cur_token
.code
== '+' || cur_token
.code
== '-')
6074 /* Need to look one token ahead - if the next token
6075 is a constant, the current token is its sign. */
6078 intel_match_token (cur_token
.code
);
6079 next_code
= cur_token
.code
;
6080 intel_putback_token ();
6081 if (next_code
== T_CONST
)
6085 /* e09 OFFSET e09 */
6086 if (cur_token
.code
== T_OFFSET
)
6089 ++intel_parser
.in_offset
;
6093 else if (cur_token
.code
== T_SHORT
)
6094 intel_parser
.op_modifier
|= 1 << T_SHORT
;
6097 else if (cur_token
.code
== '+')
6098 strcat (intel_parser
.disp
, "+");
6103 else if (cur_token
.code
== '-' || cur_token
.code
== '~')
6109 str
[0] = cur_token
.code
;
6111 strcat (intel_parser
.disp
, str
);
6118 intel_match_token (cur_token
.code
);
6126 /* e09' PTR e10 e09' */
6127 if (cur_token
.code
== T_PTR
)
6131 if (prev_token
.code
== T_BYTE
)
6132 suffix
= BYTE_MNEM_SUFFIX
;
6134 else if (prev_token
.code
== T_WORD
)
6136 if (current_templates
->start
->name
[0] == 'l'
6137 && current_templates
->start
->name
[2] == 's'
6138 && current_templates
->start
->name
[3] == 0)
6139 suffix
= BYTE_MNEM_SUFFIX
; /* so it will cause an error */
6140 else if (intel_parser
.got_a_float
== 2) /* "fi..." */
6141 suffix
= SHORT_MNEM_SUFFIX
;
6143 suffix
= WORD_MNEM_SUFFIX
;
6146 else if (prev_token
.code
== T_DWORD
)
6148 if (current_templates
->start
->name
[0] == 'l'
6149 && current_templates
->start
->name
[2] == 's'
6150 && current_templates
->start
->name
[3] == 0)
6151 suffix
= WORD_MNEM_SUFFIX
;
6152 else if (flag_code
== CODE_16BIT
6153 && (current_templates
->start
->opcode_modifier
6154 & (Jump
|JumpDword
|JumpInterSegment
)))
6155 suffix
= LONG_DOUBLE_MNEM_SUFFIX
;
6156 else if (intel_parser
.got_a_float
== 1) /* "f..." */
6157 suffix
= SHORT_MNEM_SUFFIX
;
6159 suffix
= LONG_MNEM_SUFFIX
;
6162 else if (prev_token
.code
== T_FWORD
)
6164 if (current_templates
->start
->name
[0] == 'l'
6165 && current_templates
->start
->name
[2] == 's'
6166 && current_templates
->start
->name
[3] == 0)
6167 suffix
= LONG_MNEM_SUFFIX
;
6168 else if (!intel_parser
.got_a_float
)
6170 if (flag_code
== CODE_16BIT
)
6171 add_prefix (DATA_PREFIX_OPCODE
);
6172 suffix
= LONG_DOUBLE_MNEM_SUFFIX
;
6175 suffix
= BYTE_MNEM_SUFFIX
; /* so it will cause an error */
6178 else if (prev_token
.code
== T_QWORD
)
6180 if (intel_parser
.got_a_float
== 1) /* "f..." */
6181 suffix
= LONG_MNEM_SUFFIX
;
6183 suffix
= QWORD_MNEM_SUFFIX
;
6186 else if (prev_token
.code
== T_TBYTE
)
6188 if (intel_parser
.got_a_float
== 1)
6189 suffix
= LONG_DOUBLE_MNEM_SUFFIX
;
6191 suffix
= BYTE_MNEM_SUFFIX
; /* so it will cause an error */
6194 else if (prev_token
.code
== T_XMMWORD
)
6196 /* XXX ignored for now, but accepted since gcc uses it */
6202 as_bad (_("Unknown operand modifier `%s'"), prev_token
.str
);
6206 if (current_templates
->start
->base_opcode
== 0x8d /* lea */)
6210 else if (i
.suffix
!= suffix
)
6212 as_bad (_("Conflicting operand modifiers"));
6218 /* e09' : e10 e09' */
6219 else if (cur_token
.code
== ':')
6221 if (prev_token
.code
!= T_REG
)
6223 /* While {call,jmp} SSSS:OOOO is MASM syntax only when SSSS is a
6224 segment/group identifier (which we don't have), using comma
6225 as the operand separator there is even less consistent, since
6226 there all branches only have a single operand. */
6227 if (this_operand
!= 0
6228 || intel_parser
.in_offset
6229 || intel_parser
.in_bracket
6230 || (!(current_templates
->start
->opcode_modifier
6231 & (Jump
|JumpDword
|JumpInterSegment
))
6232 && !(current_templates
->start
->operand_types
[0]
6234 return intel_match_token (T_NIL
);
6235 /* Remember the start of the 2nd operand and terminate 1st
6237 XXX This isn't right, yet (when SSSS:OOOO is right operand of
6238 another expression), but it gets at least the simplest case
6239 (a plain number or symbol on the left side) right. */
6240 intel_parser
.next_operand
= intel_parser
.op_string
;
6241 *--intel_parser
.op_string
= '\0';
6242 return intel_match_token (':');
6250 intel_match_token (cur_token
.code
);
6256 --intel_parser
.in_offset
;
6259 if (NUM_ADDRESS_REGS
> nregs
)
6261 as_bad (_("Invalid operand to `OFFSET'"));
6264 intel_parser
.op_modifier
|= 1 << T_OFFSET
;
6267 if (nregs
>= 0 && NUM_ADDRESS_REGS
> nregs
)
6268 i
.base_reg
= i386_regtab
+ REGNAM_AL
+ 3; /* bl is invalid as base */
6273 intel_bracket_expr ()
6275 int was_offset
= intel_parser
.op_modifier
& (1 << T_OFFSET
);
6276 const char *start
= intel_parser
.op_string
;
6279 if (i
.op
[this_operand
].regs
)
6280 return intel_match_token (T_NIL
);
6282 intel_match_token ('[');
6284 /* Mark as a memory operand only if it's not already known to be an
6285 offset expression. If it's an offset expression, we need to keep
6287 if (!intel_parser
.in_offset
)
6289 ++intel_parser
.in_bracket
;
6290 /* Unfortunately gas always diverged from MASM in a respect that can't
6291 be easily fixed without risking to break code sequences likely to be
6292 encountered (the testsuite even check for this): MASM doesn't consider
6293 an expression inside brackets unconditionally as a memory reference.
6294 When that is e.g. a constant, an offset expression, or the sum of the
6295 two, this is still taken as a constant load. gas, however, always
6296 treated these as memory references. As a compromise, we'll try to make
6297 offset expressions inside brackets work the MASM way (since that's
6298 less likely to be found in real world code), but make constants alone
6299 continue to work the traditional gas way. In either case, issue a
6301 intel_parser
.op_modifier
&= ~was_offset
;
6304 strcat (intel_parser
.disp
, "[");
6306 /* Add a '+' to the displacement string if necessary. */
6307 if (*intel_parser
.disp
!= '\0'
6308 && *(intel_parser
.disp
+ strlen (intel_parser
.disp
) - 1) != '+')
6309 strcat (intel_parser
.disp
, "+");
6312 && (len
= intel_parser
.op_string
- start
- 1,
6313 intel_match_token (']')))
6315 /* Preserve brackets when the operand is an offset expression. */
6316 if (intel_parser
.in_offset
)
6317 strcat (intel_parser
.disp
, "]");
6320 --intel_parser
.in_bracket
;
6321 if (i
.base_reg
|| i
.index_reg
)
6322 intel_parser
.is_mem
= 1;
6323 if (!intel_parser
.is_mem
)
6325 if (!(intel_parser
.op_modifier
& (1 << T_OFFSET
)))
6326 /* Defer the warning until all of the operand was parsed. */
6327 intel_parser
.is_mem
= -1;
6328 else if (!quiet_warnings
)
6329 as_warn (_("`[%.*s]' taken to mean just `%.*s'"), len
, start
, len
, start
);
6332 intel_parser
.op_modifier
|= was_offset
;
6349 while (cur_token
.code
== '[')
6351 if (!intel_bracket_expr ())
6376 switch (cur_token
.code
)
6380 intel_match_token ('(');
6381 strcat (intel_parser
.disp
, "(");
6383 if (intel_expr () && intel_match_token (')'))
6385 strcat (intel_parser
.disp
, ")");
6392 /* Operands for jump/call inside brackets denote absolute addresses.
6393 XXX This shouldn't be needed anymore (or if it should rather live
6394 in intel_bracket_expr). */
6395 if (current_templates
->start
->opcode_modifier
6396 & (Jump
|JumpDword
|JumpByte
|JumpInterSegment
))
6397 i
.types
[this_operand
] |= JumpAbsolute
;
6399 return intel_bracket_expr ();
6404 strcat (intel_parser
.disp
, cur_token
.str
);
6405 intel_match_token (cur_token
.code
);
6407 /* Mark as a memory operand only if it's not already known to be an
6408 offset expression. */
6409 if (!intel_parser
.in_offset
)
6410 intel_parser
.is_mem
= 1;
6417 const reg_entry
*reg
= intel_parser
.reg
= cur_token
.reg
;
6419 intel_match_token (T_REG
);
6421 /* Check for segment change. */
6422 if (cur_token
.code
== ':')
6424 if (!(reg
->reg_type
& (SReg2
| SReg3
)))
6426 as_bad (_("`%s' is not a valid segment register"), reg
->reg_name
);
6429 else if (i
.seg
[i
.mem_operands
])
6430 as_warn (_("Extra segment override ignored"));
6433 if (!intel_parser
.in_offset
)
6434 intel_parser
.is_mem
= 1;
6435 switch (reg
->reg_num
)
6438 i
.seg
[i
.mem_operands
] = &es
;
6441 i
.seg
[i
.mem_operands
] = &cs
;
6444 i
.seg
[i
.mem_operands
] = &ss
;
6447 i
.seg
[i
.mem_operands
] = &ds
;
6450 i
.seg
[i
.mem_operands
] = &fs
;
6453 i
.seg
[i
.mem_operands
] = &gs
;
6459 /* Not a segment register. Check for register scaling. */
6460 else if (cur_token
.code
== '*')
6462 if (!intel_parser
.in_bracket
)
6464 as_bad (_("Register scaling only allowed in memory operands"));
6468 if (reg
->reg_type
& Reg16
) /* Disallow things like [si*1]. */
6469 reg
= i386_regtab
+ REGNAM_AX
+ 4; /* sp is invalid as index */
6470 else if (i
.index_reg
)
6471 reg
= i386_regtab
+ REGNAM_EAX
+ 4; /* esp is invalid as index */
6473 /* What follows must be a valid scale. */
6474 intel_match_token ('*');
6476 i
.types
[this_operand
] |= BaseIndex
;
6478 /* Set the scale after setting the register (otherwise,
6479 i386_scale will complain) */
6480 if (cur_token
.code
== '+' || cur_token
.code
== '-')
6482 char *str
, sign
= cur_token
.code
;
6483 intel_match_token (cur_token
.code
);
6484 if (cur_token
.code
!= T_CONST
)
6486 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
6490 str
= (char *) xmalloc (strlen (cur_token
.str
) + 2);
6491 strcpy (str
+ 1, cur_token
.str
);
6493 if (!i386_scale (str
))
6497 else if (!i386_scale (cur_token
.str
))
6499 intel_match_token (cur_token
.code
);
6502 /* No scaling. If this is a memory operand, the register is either a
6503 base register (first occurrence) or an index register (second
6505 else if (intel_parser
.in_bracket
&& !(reg
->reg_type
& (SReg2
| SReg3
)))
6510 else if (!i
.index_reg
)
6514 as_bad (_("Too many register references in memory operand"));
6518 i
.types
[this_operand
] |= BaseIndex
;
6521 /* Offset modifier. Add the register to the displacement string to be
6522 parsed as an immediate expression after we're done. */
6523 else if (intel_parser
.in_offset
)
6525 as_warn (_("Using register names in OFFSET expressions is deprecated"));
6526 strcat (intel_parser
.disp
, reg
->reg_name
);
6529 /* It's neither base nor index nor offset. */
6530 else if (!intel_parser
.is_mem
)
6532 i
.types
[this_operand
] |= reg
->reg_type
& ~BaseIndex
;
6533 i
.op
[this_operand
].regs
= reg
;
6538 as_bad (_("Invalid use of register"));
6542 /* Since registers are not part of the displacement string (except
6543 when we're parsing offset operands), we may need to remove any
6544 preceding '+' from the displacement string. */
6545 if (*intel_parser
.disp
!= '\0'
6546 && !intel_parser
.in_offset
)
6548 char *s
= intel_parser
.disp
;
6549 s
+= strlen (s
) - 1;
6572 intel_match_token (cur_token
.code
);
6574 if (cur_token
.code
== T_PTR
)
6577 /* It must have been an identifier. */
6578 intel_putback_token ();
6579 cur_token
.code
= T_ID
;
6585 if (!intel_parser
.in_offset
&& intel_parser
.is_mem
<= 0)
6589 /* The identifier represents a memory reference only if it's not
6590 preceded by an offset modifier and if it's not an equate. */
6591 symbolP
= symbol_find(cur_token
.str
);
6592 if (!symbolP
|| S_GET_SEGMENT(symbolP
) != absolute_section
)
6593 intel_parser
.is_mem
= 1;
6601 char *save_str
, sign
= 0;
6603 /* Allow constants that start with `+' or `-'. */
6604 if (cur_token
.code
== '-' || cur_token
.code
== '+')
6606 sign
= cur_token
.code
;
6607 intel_match_token (cur_token
.code
);
6608 if (cur_token
.code
!= T_CONST
)
6610 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
6616 save_str
= (char *) xmalloc (strlen (cur_token
.str
) + 2);
6617 strcpy (save_str
+ !!sign
, cur_token
.str
);
6621 /* Get the next token to check for register scaling. */
6622 intel_match_token (cur_token
.code
);
6624 /* Check if this constant is a scaling factor for an index register. */
6625 if (cur_token
.code
== '*')
6627 if (intel_match_token ('*') && cur_token
.code
== T_REG
)
6629 const reg_entry
*reg
= cur_token
.reg
;
6631 if (!intel_parser
.in_bracket
)
6633 as_bad (_("Register scaling only allowed in memory operands"));
6637 if (reg
->reg_type
& Reg16
) /* Disallow things like [1*si]. */
6638 reg
= i386_regtab
+ REGNAM_AX
+ 4; /* sp is invalid as index */
6639 else if (i
.index_reg
)
6640 reg
= i386_regtab
+ REGNAM_EAX
+ 4; /* esp is invalid as index */
6642 /* The constant is followed by `* reg', so it must be
6645 i
.types
[this_operand
] |= BaseIndex
;
6647 /* Set the scale after setting the register (otherwise,
6648 i386_scale will complain) */
6649 if (!i386_scale (save_str
))
6651 intel_match_token (T_REG
);
6653 /* Since registers are not part of the displacement
6654 string, we may need to remove any preceding '+' from
6655 the displacement string. */
6656 if (*intel_parser
.disp
!= '\0')
6658 char *s
= intel_parser
.disp
;
6659 s
+= strlen (s
) - 1;
6669 /* The constant was not used for register scaling. Since we have
6670 already consumed the token following `*' we now need to put it
6671 back in the stream. */
6672 intel_putback_token ();
6675 /* Add the constant to the displacement string. */
6676 strcat (intel_parser
.disp
, save_str
);
6683 as_bad (_("Unrecognized token '%s'"), cur_token
.str
);
6687 /* Match the given token against cur_token. If they match, read the next
6688 token from the operand string. */
6690 intel_match_token (code
)
6693 if (cur_token
.code
== code
)
6700 as_bad (_("Unexpected token `%s'"), cur_token
.str
);
6705 /* Read a new token from intel_parser.op_string and store it in cur_token. */
6710 const reg_entry
*reg
;
6711 struct intel_token new_token
;
6713 new_token
.code
= T_NIL
;
6714 new_token
.reg
= NULL
;
6715 new_token
.str
= NULL
;
6717 /* Free the memory allocated to the previous token and move
6718 cur_token to prev_token. */
6720 free (prev_token
.str
);
6722 prev_token
= cur_token
;
6724 /* Skip whitespace. */
6725 while (is_space_char (*intel_parser
.op_string
))
6726 intel_parser
.op_string
++;
6728 /* Return an empty token if we find nothing else on the line. */
6729 if (*intel_parser
.op_string
== '\0')
6731 cur_token
= new_token
;
6735 /* The new token cannot be larger than the remainder of the operand
6737 new_token
.str
= (char *) xmalloc (strlen (intel_parser
.op_string
) + 1);
6738 new_token
.str
[0] = '\0';
6740 if (strchr ("0123456789", *intel_parser
.op_string
))
6742 char *p
= new_token
.str
;
6743 char *q
= intel_parser
.op_string
;
6744 new_token
.code
= T_CONST
;
6746 /* Allow any kind of identifier char to encompass floating point and
6747 hexadecimal numbers. */
6748 while (is_identifier_char (*q
))
6752 /* Recognize special symbol names [0-9][bf]. */
6753 if (strlen (intel_parser
.op_string
) == 2
6754 && (intel_parser
.op_string
[1] == 'b'
6755 || intel_parser
.op_string
[1] == 'f'))
6756 new_token
.code
= T_ID
;
6759 else if ((*intel_parser
.op_string
== REGISTER_PREFIX
|| allow_naked_reg
)
6760 && ((reg
= parse_register (intel_parser
.op_string
, &end_op
)) != NULL
))
6762 new_token
.code
= T_REG
;
6763 new_token
.reg
= reg
;
6765 if (*intel_parser
.op_string
== REGISTER_PREFIX
)
6767 new_token
.str
[0] = REGISTER_PREFIX
;
6768 new_token
.str
[1] = '\0';
6771 strcat (new_token
.str
, reg
->reg_name
);
6774 else if (is_identifier_char (*intel_parser
.op_string
))
6776 char *p
= new_token
.str
;
6777 char *q
= intel_parser
.op_string
;
6779 /* A '.' or '$' followed by an identifier char is an identifier.
6780 Otherwise, it's operator '.' followed by an expression. */
6781 if ((*q
== '.' || *q
== '$') && !is_identifier_char (*(q
+ 1)))
6783 new_token
.code
= '.';
6784 new_token
.str
[0] = '.';
6785 new_token
.str
[1] = '\0';
6789 while (is_identifier_char (*q
) || *q
== '@')
6793 if (strcasecmp (new_token
.str
, "NOT") == 0)
6794 new_token
.code
= '~';
6796 else if (strcasecmp (new_token
.str
, "MOD") == 0)
6797 new_token
.code
= '%';
6799 else if (strcasecmp (new_token
.str
, "AND") == 0)
6800 new_token
.code
= '&';
6802 else if (strcasecmp (new_token
.str
, "OR") == 0)
6803 new_token
.code
= '|';
6805 else if (strcasecmp (new_token
.str
, "XOR") == 0)
6806 new_token
.code
= '^';
6808 else if (strcasecmp (new_token
.str
, "SHL") == 0)
6809 new_token
.code
= T_SHL
;
6811 else if (strcasecmp (new_token
.str
, "SHR") == 0)
6812 new_token
.code
= T_SHR
;
6814 else if (strcasecmp (new_token
.str
, "BYTE") == 0)
6815 new_token
.code
= T_BYTE
;
6817 else if (strcasecmp (new_token
.str
, "WORD") == 0)
6818 new_token
.code
= T_WORD
;
6820 else if (strcasecmp (new_token
.str
, "DWORD") == 0)
6821 new_token
.code
= T_DWORD
;
6823 else if (strcasecmp (new_token
.str
, "FWORD") == 0)
6824 new_token
.code
= T_FWORD
;
6826 else if (strcasecmp (new_token
.str
, "QWORD") == 0)
6827 new_token
.code
= T_QWORD
;
6829 else if (strcasecmp (new_token
.str
, "TBYTE") == 0
6830 /* XXX remove (gcc still uses it) */
6831 || strcasecmp (new_token
.str
, "XWORD") == 0)
6832 new_token
.code
= T_TBYTE
;
6834 else if (strcasecmp (new_token
.str
, "XMMWORD") == 0
6835 || strcasecmp (new_token
.str
, "OWORD") == 0)
6836 new_token
.code
= T_XMMWORD
;
6838 else if (strcasecmp (new_token
.str
, "PTR") == 0)
6839 new_token
.code
= T_PTR
;
6841 else if (strcasecmp (new_token
.str
, "SHORT") == 0)
6842 new_token
.code
= T_SHORT
;
6844 else if (strcasecmp (new_token
.str
, "OFFSET") == 0)
6846 new_token
.code
= T_OFFSET
;
6848 /* ??? This is not mentioned in the MASM grammar but gcc
6849 makes use of it with -mintel-syntax. OFFSET may be
6850 followed by FLAT: */
6851 if (strncasecmp (q
, " FLAT:", 6) == 0)
6852 strcat (new_token
.str
, " FLAT:");
6855 /* ??? This is not mentioned in the MASM grammar. */
6856 else if (strcasecmp (new_token
.str
, "FLAT") == 0)
6858 new_token
.code
= T_OFFSET
;
6860 strcat (new_token
.str
, ":");
6862 as_bad (_("`:' expected"));
6866 new_token
.code
= T_ID
;
6870 else if (strchr ("+-/*%|&^:[]()~", *intel_parser
.op_string
))
6872 new_token
.code
= *intel_parser
.op_string
;
6873 new_token
.str
[0] = *intel_parser
.op_string
;
6874 new_token
.str
[1] = '\0';
6877 else if (strchr ("<>", *intel_parser
.op_string
)
6878 && *intel_parser
.op_string
== *(intel_parser
.op_string
+ 1))
6880 new_token
.code
= *intel_parser
.op_string
== '<' ? T_SHL
: T_SHR
;
6881 new_token
.str
[0] = *intel_parser
.op_string
;
6882 new_token
.str
[1] = *intel_parser
.op_string
;
6883 new_token
.str
[2] = '\0';
6887 as_bad (_("Unrecognized token `%s'"), intel_parser
.op_string
);
6889 intel_parser
.op_string
+= strlen (new_token
.str
);
6890 cur_token
= new_token
;
6893 /* Put cur_token back into the token stream and make cur_token point to
6896 intel_putback_token ()
6898 if (cur_token
.code
!= T_NIL
)
6900 intel_parser
.op_string
-= strlen (cur_token
.str
);
6901 free (cur_token
.str
);
6903 cur_token
= prev_token
;
6905 /* Forget prev_token. */
6906 prev_token
.code
= T_NIL
;
6907 prev_token
.reg
= NULL
;
6908 prev_token
.str
= NULL
;
6912 tc_x86_regname_to_dw2regnum (const char *regname
)
6914 unsigned int regnum
;
6915 unsigned int regnames_count
;
6916 static const char *const regnames_32
[] =
6918 "eax", "ecx", "edx", "ebx",
6919 "esp", "ebp", "esi", "edi",
6920 "eip", "eflags", NULL
,
6921 "st0", "st1", "st2", "st3",
6922 "st4", "st5", "st6", "st7",
6924 "xmm0", "xmm1", "xmm2", "xmm3",
6925 "xmm4", "xmm5", "xmm6", "xmm7",
6926 "mm0", "mm1", "mm2", "mm3",
6927 "mm4", "mm5", "mm6", "mm7"
6929 static const char *const regnames_64
[] =
6931 "rax", "rdx", "rcx", "rbx",
6932 "rsi", "rdi", "rbp", "rsp",
6933 "r8", "r9", "r10", "r11",
6934 "r12", "r13", "r14", "r15",
6936 "xmm0", "xmm1", "xmm2", "xmm3",
6937 "xmm4", "xmm5", "xmm6", "xmm7",
6938 "xmm8", "xmm9", "xmm10", "xmm11",
6939 "xmm12", "xmm13", "xmm14", "xmm15",
6940 "st0", "st1", "st2", "st3",
6941 "st4", "st5", "st6", "st7",
6942 "mm0", "mm1", "mm2", "mm3",
6943 "mm4", "mm5", "mm6", "mm7"
6945 const char *const *regnames
;
6947 if (flag_code
== CODE_64BIT
)
6949 regnames
= regnames_64
;
6950 regnames_count
= ARRAY_SIZE (regnames_64
);
6954 regnames
= regnames_32
;
6955 regnames_count
= ARRAY_SIZE (regnames_32
);
6958 for (regnum
= 0; regnum
< regnames_count
; regnum
++)
6959 if (regnames
[regnum
] != NULL
6960 && strcmp (regname
, regnames
[regnum
]) == 0)
6967 tc_x86_frame_initial_instructions (void)
6969 static unsigned int sp_regno
;
6972 sp_regno
= tc_x86_regname_to_dw2regnum (flag_code
== CODE_64BIT
6975 cfi_add_CFA_def_cfa (sp_regno
, -x86_cie_data_alignment
);
6976 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
6980 i386_elf_section_type (const char *str
, size_t len
)
6982 if (flag_code
== CODE_64BIT
6983 && len
== sizeof ("unwind") - 1
6984 && strncmp (str
, "unwind", 6) == 0)
6985 return SHT_X86_64_UNWIND
;
6992 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
6996 expr
.X_op
= O_secrel
;
6997 expr
.X_add_symbol
= symbol
;
6998 expr
.X_add_number
= 0;
6999 emit_expr (&expr
, size
);