1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright (C) 1989-2014 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 /* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
23 x86_64 support by Jan Hubicka (jh@suse.cz)
24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
29 #include "safe-ctype.h"
31 #include "dwarf2dbg.h"
32 #include "dw2gencfi.h"
33 #include "elf/x86-64.h"
34 #include "opcodes/i386-init.h"
36 #ifndef REGISTER_WARNINGS
37 #define REGISTER_WARNINGS 1
40 #ifndef INFER_ADDR_PREFIX
41 #define INFER_ADDR_PREFIX 1
45 #define DEFAULT_ARCH "i386"
50 #define INLINE __inline__
56 /* Prefixes will be emitted in the order defined below.
57 WAIT_PREFIX must be the first prefix since FWAIT is really is an
58 instruction, and so must come before any prefixes.
59 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
60 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
66 #define HLE_PREFIX REP_PREFIX
67 #define BND_PREFIX REP_PREFIX
69 #define REX_PREFIX 6 /* must come last. */
70 #define MAX_PREFIXES 7 /* max prefixes per opcode */
72 /* we define the syntax here (modulo base,index,scale syntax) */
73 #define REGISTER_PREFIX '%'
74 #define IMMEDIATE_PREFIX '$'
75 #define ABSOLUTE_PREFIX '*'
77 /* these are the instruction mnemonic suffixes in AT&T syntax or
78 memory operand size in Intel syntax. */
79 #define WORD_MNEM_SUFFIX 'w'
80 #define BYTE_MNEM_SUFFIX 'b'
81 #define SHORT_MNEM_SUFFIX 's'
82 #define LONG_MNEM_SUFFIX 'l'
83 #define QWORD_MNEM_SUFFIX 'q'
84 #define XMMWORD_MNEM_SUFFIX 'x'
85 #define YMMWORD_MNEM_SUFFIX 'y'
86 #define ZMMWORD_MNEM_SUFFIX 'z'
87 /* Intel Syntax. Use a non-ascii letter since since it never appears
89 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
91 #define END_OF_INSN '\0'
94 'templates' is for grouping together 'template' structures for opcodes
95 of the same name. This is only used for storing the insns in the grand
96 ole hash table of insns.
97 The templates themselves start at START and range up to (but not including)
102 const insn_template
*start
;
103 const insn_template
*end
;
107 /* 386 operand encoding bytes: see 386 book for details of this. */
110 unsigned int regmem
; /* codes register or memory operand */
111 unsigned int reg
; /* codes register operand (or extended opcode) */
112 unsigned int mode
; /* how to interpret regmem & reg */
116 /* x86-64 extension prefix. */
117 typedef int rex_byte
;
119 /* 386 opcode byte to code indirect addressing. */
128 /* x86 arch names, types and features */
131 const char *name
; /* arch name */
132 unsigned int len
; /* arch string length */
133 enum processor_type type
; /* arch type */
134 i386_cpu_flags flags
; /* cpu feature flags */
135 unsigned int skip
; /* show_arch should skip this. */
136 unsigned int negated
; /* turn off indicated flags. */
140 static void update_code_flag (int, int);
141 static void set_code_flag (int);
142 static void set_16bit_gcc_code_flag (int);
143 static void set_intel_syntax (int);
144 static void set_intel_mnemonic (int);
145 static void set_allow_index_reg (int);
146 static void set_check (int);
147 static void set_cpu_arch (int);
149 static void pe_directive_secrel (int);
151 static void signed_cons (int);
152 static char *output_invalid (int c
);
153 static int i386_finalize_immediate (segT
, expressionS
*, i386_operand_type
,
155 static int i386_finalize_displacement (segT
, expressionS
*, i386_operand_type
,
157 static int i386_att_operand (char *);
158 static int i386_intel_operand (char *, int);
159 static int i386_intel_simplify (expressionS
*);
160 static int i386_intel_parse_name (const char *, expressionS
*);
161 static const reg_entry
*parse_register (char *, char **);
162 static char *parse_insn (char *, char *);
163 static char *parse_operands (char *, const char *);
164 static void swap_operands (void);
165 static void swap_2_operands (int, int);
166 static void optimize_imm (void);
167 static void optimize_disp (void);
168 static const insn_template
*match_template (void);
169 static int check_string (void);
170 static int process_suffix (void);
171 static int check_byte_reg (void);
172 static int check_long_reg (void);
173 static int check_qword_reg (void);
174 static int check_word_reg (void);
175 static int finalize_imm (void);
176 static int process_operands (void);
177 static const seg_entry
*build_modrm_byte (void);
178 static void output_insn (void);
179 static void output_imm (fragS
*, offsetT
);
180 static void output_disp (fragS
*, offsetT
);
182 static void s_bss (int);
184 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
185 static void handle_large_common (int small ATTRIBUTE_UNUSED
);
188 static const char *default_arch
= DEFAULT_ARCH
;
190 /* This struct describes rounding control and SAE in the instruction. */
204 static struct RC_Operation rc_op
;
206 /* The struct describes masking, applied to OPERAND in the instruction.
207 MASK is a pointer to the corresponding mask register. ZEROING tells
208 whether merging or zeroing mask is used. */
209 struct Mask_Operation
211 const reg_entry
*mask
;
212 unsigned int zeroing
;
213 /* The operand where this operation is associated. */
217 static struct Mask_Operation mask_op
;
219 /* The struct describes broadcasting, applied to OPERAND. FACTOR is
221 struct Broadcast_Operation
223 /* Type of broadcast: no broadcast, {1to8}, or {1to16}. */
226 /* Index of broadcasted operand. */
230 static struct Broadcast_Operation broadcast_op
;
235 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
236 unsigned char bytes
[4];
238 /* Destination or source register specifier. */
239 const reg_entry
*register_specifier
;
242 /* 'md_assemble ()' gathers together information and puts it into a
249 const reg_entry
*regs
;
254 operand_size_mismatch
,
255 operand_type_mismatch
,
256 register_type_mismatch
,
257 number_of_operands_mismatch
,
258 invalid_instruction_suffix
,
261 unsupported_with_intel_mnemonic
,
264 invalid_vsib_address
,
265 invalid_vector_register_set
,
266 unsupported_vector_index_register
,
267 unsupported_broadcast
,
268 broadcast_not_on_src_operand
,
271 mask_not_on_destination
,
274 rc_sae_operand_not_last_imm
,
275 invalid_register_operand
,
281 /* TM holds the template for the insn were currently assembling. */
284 /* SUFFIX holds the instruction size suffix for byte, word, dword
285 or qword, if given. */
288 /* OPERANDS gives the number of given operands. */
289 unsigned int operands
;
291 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
292 of given register, displacement, memory operands and immediate
294 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
296 /* TYPES [i] is the type (see above #defines) which tells us how to
297 use OP[i] for the corresponding operand. */
298 i386_operand_type types
[MAX_OPERANDS
];
300 /* Displacement expression, immediate expression, or register for each
302 union i386_op op
[MAX_OPERANDS
];
304 /* Flags for operands. */
305 unsigned int flags
[MAX_OPERANDS
];
306 #define Operand_PCrel 1
308 /* Relocation type for operand */
309 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
311 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
312 the base index byte below. */
313 const reg_entry
*base_reg
;
314 const reg_entry
*index_reg
;
315 unsigned int log2_scale_factor
;
317 /* SEG gives the seg_entries of this insn. They are zero unless
318 explicit segment overrides are given. */
319 const seg_entry
*seg
[2];
321 /* PREFIX holds all the given prefix opcodes (usually null).
322 PREFIXES is the number of prefix opcodes. */
323 unsigned int prefixes
;
324 unsigned char prefix
[MAX_PREFIXES
];
326 /* RM and SIB are the modrm byte and the sib byte where the
327 addressing modes of this insn are encoded. */
334 /* Masking attributes. */
335 struct Mask_Operation
*mask
;
337 /* Rounding control and SAE attributes. */
338 struct RC_Operation
*rounding
;
340 /* Broadcasting attributes. */
341 struct Broadcast_Operation
*broadcast
;
343 /* Compressed disp8*N attribute. */
344 unsigned int memshift
;
346 /* Swap operand in encoding. */
347 unsigned int swap_operand
;
349 /* Prefer 8bit or 32bit displacement in encoding. */
352 disp_encoding_default
= 0,
358 const char *rep_prefix
;
361 const char *hle_prefix
;
363 /* Have BND prefix. */
364 const char *bnd_prefix
;
366 /* Need VREX to support upper 16 registers. */
370 enum i386_error error
;
373 typedef struct _i386_insn i386_insn
;
375 /* Link RC type with corresponding string, that'll be looked for in
384 static const struct RC_name RC_NamesTable
[] =
386 { rne
, STRING_COMMA_LEN ("rn-sae") },
387 { rd
, STRING_COMMA_LEN ("rd-sae") },
388 { ru
, STRING_COMMA_LEN ("ru-sae") },
389 { rz
, STRING_COMMA_LEN ("rz-sae") },
390 { saeonly
, STRING_COMMA_LEN ("sae") },
393 /* List of chars besides those in app.c:symbol_chars that can start an
394 operand. Used to prevent the scrubber eating vital white-space. */
395 const char extra_symbol_chars
[] = "*%-([{"
404 #if (defined (TE_I386AIX) \
405 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
406 && !defined (TE_GNU) \
407 && !defined (TE_LINUX) \
408 && !defined (TE_NACL) \
409 && !defined (TE_NETWARE) \
410 && !defined (TE_FreeBSD) \
411 && !defined (TE_DragonFly) \
412 && !defined (TE_NetBSD)))
413 /* This array holds the chars that always start a comment. If the
414 pre-processor is disabled, these aren't very useful. The option
415 --divide will remove '/' from this list. */
416 const char *i386_comment_chars
= "#/";
417 #define SVR4_COMMENT_CHARS 1
418 #define PREFIX_SEPARATOR '\\'
421 const char *i386_comment_chars
= "#";
422 #define PREFIX_SEPARATOR '/'
425 /* This array holds the chars that only start a comment at the beginning of
426 a line. If the line seems to have the form '# 123 filename'
427 .line and .file directives will appear in the pre-processed output.
428 Note that input_file.c hand checks for '#' at the beginning of the
429 first line of the input file. This is because the compiler outputs
430 #NO_APP at the beginning of its output.
431 Also note that comments started like this one will always work if
432 '/' isn't otherwise defined. */
433 const char line_comment_chars
[] = "#/";
435 const char line_separator_chars
[] = ";";
437 /* Chars that can be used to separate mant from exp in floating point
439 const char EXP_CHARS
[] = "eE";
441 /* Chars that mean this number is a floating point constant
444 const char FLT_CHARS
[] = "fFdDxX";
446 /* Tables for lexical analysis. */
447 static char mnemonic_chars
[256];
448 static char register_chars
[256];
449 static char operand_chars
[256];
450 static char identifier_chars
[256];
451 static char digit_chars
[256];
453 /* Lexical macros. */
454 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
455 #define is_operand_char(x) (operand_chars[(unsigned char) x])
456 #define is_register_char(x) (register_chars[(unsigned char) x])
457 #define is_space_char(x) ((x) == ' ')
458 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
459 #define is_digit_char(x) (digit_chars[(unsigned char) x])
461 /* All non-digit non-letter characters that may occur in an operand. */
462 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
464 /* md_assemble() always leaves the strings it's passed unaltered. To
465 effect this we maintain a stack of saved characters that we've smashed
466 with '\0's (indicating end of strings for various sub-fields of the
467 assembler instruction). */
468 static char save_stack
[32];
469 static char *save_stack_p
;
470 #define END_STRING_AND_SAVE(s) \
471 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
472 #define RESTORE_END_STRING(s) \
473 do { *(s) = *--save_stack_p; } while (0)
475 /* The instruction we're assembling. */
478 /* Possible templates for current insn. */
479 static const templates
*current_templates
;
481 /* Per instruction expressionS buffers: max displacements & immediates. */
482 static expressionS disp_expressions
[MAX_MEMORY_OPERANDS
];
483 static expressionS im_expressions
[MAX_IMMEDIATE_OPERANDS
];
485 /* Current operand we are working on. */
486 static int this_operand
= -1;
488 /* We support four different modes. FLAG_CODE variable is used to distinguish
496 static enum flag_code flag_code
;
497 static unsigned int object_64bit
;
498 static unsigned int disallow_64bit_reloc
;
499 static int use_rela_relocations
= 0;
501 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
502 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
503 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
505 /* The ELF ABI to use. */
513 static enum x86_elf_abi x86_elf_abi
= I386_ABI
;
516 #if defined (TE_PE) || defined (TE_PEP)
517 /* Use big object file format. */
518 static int use_big_obj
= 0;
521 /* 1 for intel syntax,
523 static int intel_syntax
= 0;
525 /* 1 for intel mnemonic,
526 0 if att mnemonic. */
527 static int intel_mnemonic
= !SYSV386_COMPAT
;
529 /* 1 if support old (<= 2.8.1) versions of gcc. */
530 static int old_gcc
= OLDGCC_COMPAT
;
532 /* 1 if pseudo registers are permitted. */
533 static int allow_pseudo_reg
= 0;
535 /* 1 if register prefix % not required. */
536 static int allow_naked_reg
= 0;
538 /* 1 if the assembler should add BND prefix for all control-tranferring
539 instructions supporting it, even if this prefix wasn't specified
541 static int add_bnd_prefix
= 0;
543 /* 1 if pseudo index register, eiz/riz, is allowed . */
544 static int allow_index_reg
= 0;
546 /* 1 if the assembler should ignore LOCK prefix, even if it was
547 specified explicitly. */
548 static int omit_lock_prefix
= 0;
550 static enum check_kind
556 sse_check
, operand_check
= check_warning
;
558 /* Register prefix used for error message. */
559 static const char *register_prefix
= "%";
561 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
562 leave, push, and pop instructions so that gcc has the same stack
563 frame as in 32 bit mode. */
564 static char stackop_size
= '\0';
566 /* Non-zero to optimize code alignment. */
567 int optimize_align_code
= 1;
569 /* Non-zero to quieten some warnings. */
570 static int quiet_warnings
= 0;
573 static const char *cpu_arch_name
= NULL
;
574 static char *cpu_sub_arch_name
= NULL
;
576 /* CPU feature flags. */
577 static i386_cpu_flags cpu_arch_flags
= CPU_UNKNOWN_FLAGS
;
579 /* If we have selected a cpu we are generating instructions for. */
580 static int cpu_arch_tune_set
= 0;
582 /* Cpu we are generating instructions for. */
583 enum processor_type cpu_arch_tune
= PROCESSOR_UNKNOWN
;
585 /* CPU feature flags of cpu we are generating instructions for. */
586 static i386_cpu_flags cpu_arch_tune_flags
;
588 /* CPU instruction set architecture used. */
589 enum processor_type cpu_arch_isa
= PROCESSOR_UNKNOWN
;
591 /* CPU feature flags of instruction set architecture used. */
592 i386_cpu_flags cpu_arch_isa_flags
;
594 /* If set, conditional jumps are not automatically promoted to handle
595 larger than a byte offset. */
596 static unsigned int no_cond_jump_promotion
= 0;
598 /* Encode SSE instructions with VEX prefix. */
599 static unsigned int sse2avx
;
601 /* Encode scalar AVX instructions with specific vector length. */
608 /* Encode scalar EVEX LIG instructions with specific vector length. */
616 /* Encode EVEX WIG instructions with specific evex.w. */
623 /* Value to encode in EVEX RC bits, for SAE-only instructions. */
624 static enum rc_type evexrcig
= rne
;
626 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
627 static symbolS
*GOT_symbol
;
629 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
630 unsigned int x86_dwarf2_return_column
;
632 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
633 int x86_cie_data_alignment
;
635 /* Interface to relax_segment.
636 There are 3 major relax states for 386 jump insns because the
637 different types of jumps add different sizes to frags when we're
638 figuring out what sort of jump to choose to reach a given label. */
641 #define UNCOND_JUMP 0
643 #define COND_JUMP86 2
648 #define SMALL16 (SMALL | CODE16)
650 #define BIG16 (BIG | CODE16)
654 #define INLINE __inline__
660 #define ENCODE_RELAX_STATE(type, size) \
661 ((relax_substateT) (((type) << 2) | (size)))
662 #define TYPE_FROM_RELAX_STATE(s) \
664 #define DISP_SIZE_FROM_RELAX_STATE(s) \
665 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
667 /* This table is used by relax_frag to promote short jumps to long
668 ones where necessary. SMALL (short) jumps may be promoted to BIG
669 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
670 don't allow a short jump in a 32 bit code segment to be promoted to
671 a 16 bit offset jump because it's slower (requires data size
672 prefix), and doesn't work, unless the destination is in the bottom
673 64k of the code segment (The top 16 bits of eip are zeroed). */
675 const relax_typeS md_relax_table
[] =
678 1) most positive reach of this state,
679 2) most negative reach of this state,
680 3) how many bytes this mode will have in the variable part of the frag
681 4) which index into the table to try if we can't fit into this one. */
683 /* UNCOND_JUMP states. */
684 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
685 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
686 /* dword jmp adds 4 bytes to frag:
687 0 extra opcode bytes, 4 displacement bytes. */
689 /* word jmp adds 2 byte2 to frag:
690 0 extra opcode bytes, 2 displacement bytes. */
693 /* COND_JUMP states. */
694 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
695 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
696 /* dword conditionals adds 5 bytes to frag:
697 1 extra opcode byte, 4 displacement bytes. */
699 /* word conditionals add 3 bytes to frag:
700 1 extra opcode byte, 2 displacement bytes. */
703 /* COND_JUMP86 states. */
704 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
705 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
706 /* dword conditionals adds 5 bytes to frag:
707 1 extra opcode byte, 4 displacement bytes. */
709 /* word conditionals add 4 bytes to frag:
710 1 displacement byte and a 3 byte long branch insn. */
714 static const arch_entry cpu_arch
[] =
716 /* Do not replace the first two entries - i386_target_format()
717 relies on them being there in this order. */
718 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32
,
719 CPU_GENERIC32_FLAGS
, 0, 0 },
720 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64
,
721 CPU_GENERIC64_FLAGS
, 0, 0 },
722 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN
,
723 CPU_NONE_FLAGS
, 0, 0 },
724 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN
,
725 CPU_I186_FLAGS
, 0, 0 },
726 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN
,
727 CPU_I286_FLAGS
, 0, 0 },
728 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386
,
729 CPU_I386_FLAGS
, 0, 0 },
730 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486
,
731 CPU_I486_FLAGS
, 0, 0 },
732 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM
,
733 CPU_I586_FLAGS
, 0, 0 },
734 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO
,
735 CPU_I686_FLAGS
, 0, 0 },
736 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM
,
737 CPU_I586_FLAGS
, 0, 0 },
738 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO
,
739 CPU_PENTIUMPRO_FLAGS
, 0, 0 },
740 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO
,
741 CPU_P2_FLAGS
, 0, 0 },
742 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO
,
743 CPU_P3_FLAGS
, 0, 0 },
744 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4
,
745 CPU_P4_FLAGS
, 0, 0 },
746 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA
,
747 CPU_CORE_FLAGS
, 0, 0 },
748 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA
,
749 CPU_NOCONA_FLAGS
, 0, 0 },
750 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE
,
751 CPU_CORE_FLAGS
, 1, 0 },
752 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE
,
753 CPU_CORE_FLAGS
, 0, 0 },
754 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2
,
755 CPU_CORE2_FLAGS
, 1, 0 },
756 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2
,
757 CPU_CORE2_FLAGS
, 0, 0 },
758 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7
,
759 CPU_COREI7_FLAGS
, 0, 0 },
760 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM
,
761 CPU_L1OM_FLAGS
, 0, 0 },
762 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM
,
763 CPU_K1OM_FLAGS
, 0, 0 },
764 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6
,
765 CPU_K6_FLAGS
, 0, 0 },
766 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6
,
767 CPU_K6_2_FLAGS
, 0, 0 },
768 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON
,
769 CPU_ATHLON_FLAGS
, 0, 0 },
770 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8
,
771 CPU_K8_FLAGS
, 1, 0 },
772 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8
,
773 CPU_K8_FLAGS
, 0, 0 },
774 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8
,
775 CPU_K8_FLAGS
, 0, 0 },
776 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10
,
777 CPU_AMDFAM10_FLAGS
, 0, 0 },
778 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD
,
779 CPU_BDVER1_FLAGS
, 0, 0 },
780 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD
,
781 CPU_BDVER2_FLAGS
, 0, 0 },
782 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD
,
783 CPU_BDVER3_FLAGS
, 0, 0 },
784 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD
,
785 CPU_BDVER4_FLAGS
, 0, 0 },
786 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT
,
787 CPU_BTVER1_FLAGS
, 0, 0 },
788 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT
,
789 CPU_BTVER2_FLAGS
, 0, 0 },
790 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN
,
791 CPU_8087_FLAGS
, 0, 0 },
792 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN
,
793 CPU_287_FLAGS
, 0, 0 },
794 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN
,
795 CPU_387_FLAGS
, 0, 0 },
796 { STRING_COMMA_LEN (".no87"), PROCESSOR_UNKNOWN
,
797 CPU_ANY87_FLAGS
, 0, 1 },
798 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN
,
799 CPU_MMX_FLAGS
, 0, 0 },
800 { STRING_COMMA_LEN (".nommx"), PROCESSOR_UNKNOWN
,
801 CPU_3DNOWA_FLAGS
, 0, 1 },
802 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN
,
803 CPU_SSE_FLAGS
, 0, 0 },
804 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN
,
805 CPU_SSE2_FLAGS
, 0, 0 },
806 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN
,
807 CPU_SSE3_FLAGS
, 0, 0 },
808 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN
,
809 CPU_SSSE3_FLAGS
, 0, 0 },
810 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN
,
811 CPU_SSE4_1_FLAGS
, 0, 0 },
812 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN
,
813 CPU_SSE4_2_FLAGS
, 0, 0 },
814 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN
,
815 CPU_SSE4_2_FLAGS
, 0, 0 },
816 { STRING_COMMA_LEN (".nosse"), PROCESSOR_UNKNOWN
,
817 CPU_ANY_SSE_FLAGS
, 0, 1 },
818 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN
,
819 CPU_AVX_FLAGS
, 0, 0 },
820 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN
,
821 CPU_AVX2_FLAGS
, 0, 0 },
822 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN
,
823 CPU_AVX512F_FLAGS
, 0, 0 },
824 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN
,
825 CPU_AVX512CD_FLAGS
, 0, 0 },
826 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN
,
827 CPU_AVX512ER_FLAGS
, 0, 0 },
828 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN
,
829 CPU_AVX512PF_FLAGS
, 0, 0 },
830 { STRING_COMMA_LEN (".noavx"), PROCESSOR_UNKNOWN
,
831 CPU_ANY_AVX_FLAGS
, 0, 1 },
832 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN
,
833 CPU_VMX_FLAGS
, 0, 0 },
834 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN
,
835 CPU_VMFUNC_FLAGS
, 0, 0 },
836 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN
,
837 CPU_SMX_FLAGS
, 0, 0 },
838 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN
,
839 CPU_XSAVE_FLAGS
, 0, 0 },
840 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN
,
841 CPU_XSAVEOPT_FLAGS
, 0, 0 },
842 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN
,
843 CPU_AES_FLAGS
, 0, 0 },
844 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN
,
845 CPU_PCLMUL_FLAGS
, 0, 0 },
846 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN
,
847 CPU_PCLMUL_FLAGS
, 1, 0 },
848 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN
,
849 CPU_FSGSBASE_FLAGS
, 0, 0 },
850 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN
,
851 CPU_RDRND_FLAGS
, 0, 0 },
852 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN
,
853 CPU_F16C_FLAGS
, 0, 0 },
854 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN
,
855 CPU_BMI2_FLAGS
, 0, 0 },
856 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN
,
857 CPU_FMA_FLAGS
, 0, 0 },
858 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN
,
859 CPU_FMA4_FLAGS
, 0, 0 },
860 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN
,
861 CPU_XOP_FLAGS
, 0, 0 },
862 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN
,
863 CPU_LWP_FLAGS
, 0, 0 },
864 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN
,
865 CPU_MOVBE_FLAGS
, 0, 0 },
866 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN
,
867 CPU_CX16_FLAGS
, 0, 0 },
868 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN
,
869 CPU_EPT_FLAGS
, 0, 0 },
870 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN
,
871 CPU_LZCNT_FLAGS
, 0, 0 },
872 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN
,
873 CPU_HLE_FLAGS
, 0, 0 },
874 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN
,
875 CPU_RTM_FLAGS
, 0, 0 },
876 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN
,
877 CPU_INVPCID_FLAGS
, 0, 0 },
878 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN
,
879 CPU_CLFLUSH_FLAGS
, 0, 0 },
880 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN
,
881 CPU_NOP_FLAGS
, 0, 0 },
882 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN
,
883 CPU_SYSCALL_FLAGS
, 0, 0 },
884 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN
,
885 CPU_RDTSCP_FLAGS
, 0, 0 },
886 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN
,
887 CPU_3DNOW_FLAGS
, 0, 0 },
888 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN
,
889 CPU_3DNOWA_FLAGS
, 0, 0 },
890 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN
,
891 CPU_PADLOCK_FLAGS
, 0, 0 },
892 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN
,
893 CPU_SVME_FLAGS
, 1, 0 },
894 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN
,
895 CPU_SVME_FLAGS
, 0, 0 },
896 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN
,
897 CPU_SSE4A_FLAGS
, 0, 0 },
898 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN
,
899 CPU_ABM_FLAGS
, 0, 0 },
900 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN
,
901 CPU_BMI_FLAGS
, 0, 0 },
902 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN
,
903 CPU_TBM_FLAGS
, 0, 0 },
904 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN
,
905 CPU_ADX_FLAGS
, 0, 0 },
906 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN
,
907 CPU_RDSEED_FLAGS
, 0, 0 },
908 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN
,
909 CPU_PRFCHW_FLAGS
, 0, 0 },
910 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN
,
911 CPU_SMAP_FLAGS
, 0, 0 },
912 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN
,
913 CPU_MPX_FLAGS
, 0, 0 },
914 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN
,
915 CPU_SHA_FLAGS
, 0, 0 },
916 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN
,
917 CPU_CLFLUSHOPT_FLAGS
, 0, 0 },
918 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN
,
919 CPU_XSAVEC_FLAGS
, 0, 0 },
920 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN
,
921 CPU_XSAVES_FLAGS
, 0, 0 },
922 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN
,
923 CPU_PREFETCHWT1_FLAGS
, 0, 0 },
924 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN
,
925 CPU_SE1_FLAGS
, 0, 0 },
926 { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN
,
927 CPU_AVX512DQ_FLAGS
, 0, 0 },
928 { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN
,
929 CPU_AVX512BW_FLAGS
, 0, 0 },
930 { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN
,
931 CPU_AVX512VL_FLAGS
, 0, 0 },
935 /* Like s_lcomm_internal in gas/read.c but the alignment string
936 is allowed to be optional. */
939 pe_lcomm_internal (int needs_align
, symbolS
*symbolP
, addressT size
)
946 && *input_line_pointer
== ',')
948 align
= parse_align (needs_align
- 1);
950 if (align
== (addressT
) -1)
965 bss_alloc (symbolP
, size
, align
);
970 pe_lcomm (int needs_align
)
972 s_comm_internal (needs_align
* 2, pe_lcomm_internal
);
976 const pseudo_typeS md_pseudo_table
[] =
978 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
979 {"align", s_align_bytes
, 0},
981 {"align", s_align_ptwo
, 0},
983 {"arch", set_cpu_arch
, 0},
987 {"lcomm", pe_lcomm
, 1},
989 {"ffloat", float_cons
, 'f'},
990 {"dfloat", float_cons
, 'd'},
991 {"tfloat", float_cons
, 'x'},
993 {"slong", signed_cons
, 4},
994 {"noopt", s_ignore
, 0},
995 {"optim", s_ignore
, 0},
996 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
997 {"code16", set_code_flag
, CODE_16BIT
},
998 {"code32", set_code_flag
, CODE_32BIT
},
999 {"code64", set_code_flag
, CODE_64BIT
},
1000 {"intel_syntax", set_intel_syntax
, 1},
1001 {"att_syntax", set_intel_syntax
, 0},
1002 {"intel_mnemonic", set_intel_mnemonic
, 1},
1003 {"att_mnemonic", set_intel_mnemonic
, 0},
1004 {"allow_index_reg", set_allow_index_reg
, 1},
1005 {"disallow_index_reg", set_allow_index_reg
, 0},
1006 {"sse_check", set_check
, 0},
1007 {"operand_check", set_check
, 1},
1008 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1009 {"largecomm", handle_large_common
, 0},
1011 {"file", (void (*) (int)) dwarf2_directive_file
, 0},
1012 {"loc", dwarf2_directive_loc
, 0},
1013 {"loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0},
1016 {"secrel32", pe_directive_secrel
, 0},
1021 /* For interface with expression (). */
1022 extern char *input_line_pointer
;
1024 /* Hash table for instruction mnemonic lookup. */
1025 static struct hash_control
*op_hash
;
1027 /* Hash table for register lookup. */
1028 static struct hash_control
*reg_hash
;
1031 i386_align_code (fragS
*fragP
, int count
)
1033 /* Various efficient no-op patterns for aligning code labels.
1034 Note: Don't try to assemble the instructions in the comments.
1035 0L and 0w are not legal. */
1036 static const char f32_1
[] =
1038 static const char f32_2
[] =
1039 {0x66,0x90}; /* xchg %ax,%ax */
1040 static const char f32_3
[] =
1041 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1042 static const char f32_4
[] =
1043 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1044 static const char f32_5
[] =
1046 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1047 static const char f32_6
[] =
1048 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1049 static const char f32_7
[] =
1050 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1051 static const char f32_8
[] =
1053 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1054 static const char f32_9
[] =
1055 {0x89,0xf6, /* movl %esi,%esi */
1056 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1057 static const char f32_10
[] =
1058 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
1059 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1060 static const char f32_11
[] =
1061 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
1062 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1063 static const char f32_12
[] =
1064 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1065 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
1066 static const char f32_13
[] =
1067 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1068 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1069 static const char f32_14
[] =
1070 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
1071 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1072 static const char f16_3
[] =
1073 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
1074 static const char f16_4
[] =
1075 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
1076 static const char f16_5
[] =
1078 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
1079 static const char f16_6
[] =
1080 {0x89,0xf6, /* mov %si,%si */
1081 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1082 static const char f16_7
[] =
1083 {0x8d,0x74,0x00, /* lea 0(%si),%si */
1084 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1085 static const char f16_8
[] =
1086 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
1087 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1088 static const char jump_31
[] =
1089 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
1090 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1091 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1092 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
1093 static const char *const f32_patt
[] = {
1094 f32_1
, f32_2
, f32_3
, f32_4
, f32_5
, f32_6
, f32_7
, f32_8
,
1095 f32_9
, f32_10
, f32_11
, f32_12
, f32_13
, f32_14
1097 static const char *const f16_patt
[] = {
1098 f32_1
, f32_2
, f16_3
, f16_4
, f16_5
, f16_6
, f16_7
, f16_8
1100 /* nopl (%[re]ax) */
1101 static const char alt_3
[] =
1103 /* nopl 0(%[re]ax) */
1104 static const char alt_4
[] =
1105 {0x0f,0x1f,0x40,0x00};
1106 /* nopl 0(%[re]ax,%[re]ax,1) */
1107 static const char alt_5
[] =
1108 {0x0f,0x1f,0x44,0x00,0x00};
1109 /* nopw 0(%[re]ax,%[re]ax,1) */
1110 static const char alt_6
[] =
1111 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1112 /* nopl 0L(%[re]ax) */
1113 static const char alt_7
[] =
1114 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1115 /* nopl 0L(%[re]ax,%[re]ax,1) */
1116 static const char alt_8
[] =
1117 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1118 /* nopw 0L(%[re]ax,%[re]ax,1) */
1119 static const char alt_9
[] =
1120 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1121 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1122 static const char alt_10
[] =
1123 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1125 nopw %cs:0L(%[re]ax,%[re]ax,1) */
1126 static const char alt_long_11
[] =
1128 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1131 nopw %cs:0L(%[re]ax,%[re]ax,1) */
1132 static const char alt_long_12
[] =
1135 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1139 nopw %cs:0L(%[re]ax,%[re]ax,1) */
1140 static const char alt_long_13
[] =
1144 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1149 nopw %cs:0L(%[re]ax,%[re]ax,1) */
1150 static const char alt_long_14
[] =
1155 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1161 nopw %cs:0L(%[re]ax,%[re]ax,1) */
1162 static const char alt_long_15
[] =
1168 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1169 /* nopl 0(%[re]ax,%[re]ax,1)
1170 nopw 0(%[re]ax,%[re]ax,1) */
1171 static const char alt_short_11
[] =
1172 {0x0f,0x1f,0x44,0x00,0x00,
1173 0x66,0x0f,0x1f,0x44,0x00,0x00};
1174 /* nopw 0(%[re]ax,%[re]ax,1)
1175 nopw 0(%[re]ax,%[re]ax,1) */
1176 static const char alt_short_12
[] =
1177 {0x66,0x0f,0x1f,0x44,0x00,0x00,
1178 0x66,0x0f,0x1f,0x44,0x00,0x00};
1179 /* nopw 0(%[re]ax,%[re]ax,1)
1181 static const char alt_short_13
[] =
1182 {0x66,0x0f,0x1f,0x44,0x00,0x00,
1183 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1186 static const char alt_short_14
[] =
1187 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
1188 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1190 nopl 0L(%[re]ax,%[re]ax,1) */
1191 static const char alt_short_15
[] =
1192 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
1193 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1194 static const char *const alt_short_patt
[] = {
1195 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
1196 alt_9
, alt_10
, alt_short_11
, alt_short_12
, alt_short_13
,
1197 alt_short_14
, alt_short_15
1199 static const char *const alt_long_patt
[] = {
1200 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
1201 alt_9
, alt_10
, alt_long_11
, alt_long_12
, alt_long_13
,
1202 alt_long_14
, alt_long_15
1205 /* Only align for at least a positive non-zero boundary. */
1206 if (count
<= 0 || count
> MAX_MEM_FOR_RS_ALIGN_CODE
)
1209 /* We need to decide which NOP sequence to use for 32bit and
1210 64bit. When -mtune= is used:
1212 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1213 PROCESSOR_GENERIC32, f32_patt will be used.
1214 2. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
1215 PROCESSOR_CORE, PROCESSOR_CORE2, PROCESSOR_COREI7, and
1216 PROCESSOR_GENERIC64, alt_long_patt will be used.
1217 3. For PROCESSOR_ATHLON, PROCESSOR_K6, PROCESSOR_K8 and
1218 PROCESSOR_AMDFAM10, PROCESSOR_BD and PROCESSOR_BT, alt_short_patt
1221 When -mtune= isn't used, alt_long_patt will be used if
1222 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
1225 When -march= or .arch is used, we can't use anything beyond
1226 cpu_arch_isa_flags. */
1228 if (flag_code
== CODE_16BIT
)
1232 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1234 /* Adjust jump offset. */
1235 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
1238 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1239 f16_patt
[count
- 1], count
);
1243 const char *const *patt
= NULL
;
1245 if (fragP
->tc_frag_data
.isa
== PROCESSOR_UNKNOWN
)
1247 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1248 switch (cpu_arch_tune
)
1250 case PROCESSOR_UNKNOWN
:
1251 /* We use cpu_arch_isa_flags to check if we SHOULD
1252 optimize with nops. */
1253 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1254 patt
= alt_long_patt
;
1258 case PROCESSOR_PENTIUM4
:
1259 case PROCESSOR_NOCONA
:
1260 case PROCESSOR_CORE
:
1261 case PROCESSOR_CORE2
:
1262 case PROCESSOR_COREI7
:
1263 case PROCESSOR_L1OM
:
1264 case PROCESSOR_K1OM
:
1265 case PROCESSOR_GENERIC64
:
1266 patt
= alt_long_patt
;
1269 case PROCESSOR_ATHLON
:
1271 case PROCESSOR_AMDFAM10
:
1274 patt
= alt_short_patt
;
1276 case PROCESSOR_I386
:
1277 case PROCESSOR_I486
:
1278 case PROCESSOR_PENTIUM
:
1279 case PROCESSOR_PENTIUMPRO
:
1280 case PROCESSOR_GENERIC32
:
1287 switch (fragP
->tc_frag_data
.tune
)
1289 case PROCESSOR_UNKNOWN
:
1290 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1291 PROCESSOR_UNKNOWN. */
1295 case PROCESSOR_I386
:
1296 case PROCESSOR_I486
:
1297 case PROCESSOR_PENTIUM
:
1299 case PROCESSOR_ATHLON
:
1301 case PROCESSOR_AMDFAM10
:
1304 case PROCESSOR_GENERIC32
:
1305 /* We use cpu_arch_isa_flags to check if we CAN optimize
1307 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1308 patt
= alt_short_patt
;
1312 case PROCESSOR_PENTIUMPRO
:
1313 case PROCESSOR_PENTIUM4
:
1314 case PROCESSOR_NOCONA
:
1315 case PROCESSOR_CORE
:
1316 case PROCESSOR_CORE2
:
1317 case PROCESSOR_COREI7
:
1318 case PROCESSOR_L1OM
:
1319 case PROCESSOR_K1OM
:
1320 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1321 patt
= alt_long_patt
;
1325 case PROCESSOR_GENERIC64
:
1326 patt
= alt_long_patt
;
1331 if (patt
== f32_patt
)
1333 /* If the padding is less than 15 bytes, we use the normal
1334 ones. Otherwise, we use a jump instruction and adjust
1338 /* For 64bit, the limit is 3 bytes. */
1339 if (flag_code
== CODE_64BIT
1340 && fragP
->tc_frag_data
.isa_flags
.bitfield
.cpulm
)
1345 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1346 patt
[count
- 1], count
);
1349 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1351 /* Adjust jump offset. */
1352 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
1357 /* Maximum length of an instruction is 15 byte. If the
1358 padding is greater than 15 bytes and we don't use jump,
1359 we have to break it into smaller pieces. */
1360 int padding
= count
;
1361 while (padding
> 15)
1364 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
+ padding
,
1369 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1370 patt
[padding
- 1], padding
);
1373 fragP
->fr_var
= count
;
1377 operand_type_all_zero (const union i386_operand_type
*x
)
1379 switch (ARRAY_SIZE(x
->array
))
1388 return !x
->array
[0];
1395 operand_type_set (union i386_operand_type
*x
, unsigned int v
)
1397 switch (ARRAY_SIZE(x
->array
))
1412 operand_type_equal (const union i386_operand_type
*x
,
1413 const union i386_operand_type
*y
)
1415 switch (ARRAY_SIZE(x
->array
))
1418 if (x
->array
[2] != y
->array
[2])
1421 if (x
->array
[1] != y
->array
[1])
1424 return x
->array
[0] == y
->array
[0];
1432 cpu_flags_all_zero (const union i386_cpu_flags
*x
)
1434 switch (ARRAY_SIZE(x
->array
))
1443 return !x
->array
[0];
1450 cpu_flags_set (union i386_cpu_flags
*x
, unsigned int v
)
1452 switch (ARRAY_SIZE(x
->array
))
1467 cpu_flags_equal (const union i386_cpu_flags
*x
,
1468 const union i386_cpu_flags
*y
)
1470 switch (ARRAY_SIZE(x
->array
))
1473 if (x
->array
[2] != y
->array
[2])
1476 if (x
->array
[1] != y
->array
[1])
1479 return x
->array
[0] == y
->array
[0];
1487 cpu_flags_check_cpu64 (i386_cpu_flags f
)
1489 return !((flag_code
== CODE_64BIT
&& f
.bitfield
.cpuno64
)
1490 || (flag_code
!= CODE_64BIT
&& f
.bitfield
.cpu64
));
1493 static INLINE i386_cpu_flags
1494 cpu_flags_and (i386_cpu_flags x
, i386_cpu_flags y
)
1496 switch (ARRAY_SIZE (x
.array
))
1499 x
.array
[2] &= y
.array
[2];
1501 x
.array
[1] &= y
.array
[1];
1503 x
.array
[0] &= y
.array
[0];
1511 static INLINE i386_cpu_flags
1512 cpu_flags_or (i386_cpu_flags x
, i386_cpu_flags y
)
1514 switch (ARRAY_SIZE (x
.array
))
1517 x
.array
[2] |= y
.array
[2];
1519 x
.array
[1] |= y
.array
[1];
1521 x
.array
[0] |= y
.array
[0];
1529 static INLINE i386_cpu_flags
1530 cpu_flags_and_not (i386_cpu_flags x
, i386_cpu_flags y
)
1532 switch (ARRAY_SIZE (x
.array
))
1535 x
.array
[2] &= ~y
.array
[2];
1537 x
.array
[1] &= ~y
.array
[1];
1539 x
.array
[0] &= ~y
.array
[0];
1547 #define CPU_FLAGS_ARCH_MATCH 0x1
1548 #define CPU_FLAGS_64BIT_MATCH 0x2
1549 #define CPU_FLAGS_AES_MATCH 0x4
1550 #define CPU_FLAGS_PCLMUL_MATCH 0x8
1551 #define CPU_FLAGS_AVX_MATCH 0x10
1553 #define CPU_FLAGS_32BIT_MATCH \
1554 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH \
1555 | CPU_FLAGS_PCLMUL_MATCH | CPU_FLAGS_AVX_MATCH)
1556 #define CPU_FLAGS_PERFECT_MATCH \
1557 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)
1559 /* Return CPU flags match bits. */
1562 cpu_flags_match (const insn_template
*t
)
1564 i386_cpu_flags x
= t
->cpu_flags
;
1565 int match
= cpu_flags_check_cpu64 (x
) ? CPU_FLAGS_64BIT_MATCH
: 0;
1567 x
.bitfield
.cpu64
= 0;
1568 x
.bitfield
.cpuno64
= 0;
1570 if (cpu_flags_all_zero (&x
))
1572 /* This instruction is available on all archs. */
1573 match
|= CPU_FLAGS_32BIT_MATCH
;
1577 /* This instruction is available only on some archs. */
1578 i386_cpu_flags cpu
= cpu_arch_flags
;
1580 cpu
.bitfield
.cpu64
= 0;
1581 cpu
.bitfield
.cpuno64
= 0;
1582 cpu
= cpu_flags_and (x
, cpu
);
1583 if (!cpu_flags_all_zero (&cpu
))
1585 if (x
.bitfield
.cpuavx
)
1587 /* We only need to check AES/PCLMUL/SSE2AVX with AVX. */
1588 if (cpu
.bitfield
.cpuavx
)
1590 /* Check SSE2AVX. */
1591 if (!t
->opcode_modifier
.sse2avx
|| sse2avx
)
1593 match
|= (CPU_FLAGS_ARCH_MATCH
1594 | CPU_FLAGS_AVX_MATCH
);
1596 if (!x
.bitfield
.cpuaes
|| cpu
.bitfield
.cpuaes
)
1597 match
|= CPU_FLAGS_AES_MATCH
;
1599 if (!x
.bitfield
.cpupclmul
1600 || cpu
.bitfield
.cpupclmul
)
1601 match
|= CPU_FLAGS_PCLMUL_MATCH
;
1605 match
|= CPU_FLAGS_ARCH_MATCH
;
1608 match
|= CPU_FLAGS_32BIT_MATCH
;
1614 static INLINE i386_operand_type
1615 operand_type_and (i386_operand_type x
, i386_operand_type y
)
1617 switch (ARRAY_SIZE (x
.array
))
1620 x
.array
[2] &= y
.array
[2];
1622 x
.array
[1] &= y
.array
[1];
1624 x
.array
[0] &= y
.array
[0];
1632 static INLINE i386_operand_type
1633 operand_type_or (i386_operand_type x
, i386_operand_type y
)
1635 switch (ARRAY_SIZE (x
.array
))
1638 x
.array
[2] |= y
.array
[2];
1640 x
.array
[1] |= y
.array
[1];
1642 x
.array
[0] |= y
.array
[0];
1650 static INLINE i386_operand_type
1651 operand_type_xor (i386_operand_type x
, i386_operand_type y
)
1653 switch (ARRAY_SIZE (x
.array
))
1656 x
.array
[2] ^= y
.array
[2];
1658 x
.array
[1] ^= y
.array
[1];
1660 x
.array
[0] ^= y
.array
[0];
1668 static const i386_operand_type acc32
= OPERAND_TYPE_ACC32
;
1669 static const i386_operand_type acc64
= OPERAND_TYPE_ACC64
;
1670 static const i386_operand_type control
= OPERAND_TYPE_CONTROL
;
1671 static const i386_operand_type inoutportreg
1672 = OPERAND_TYPE_INOUTPORTREG
;
1673 static const i386_operand_type reg16_inoutportreg
1674 = OPERAND_TYPE_REG16_INOUTPORTREG
;
1675 static const i386_operand_type disp16
= OPERAND_TYPE_DISP16
;
1676 static const i386_operand_type disp32
= OPERAND_TYPE_DISP32
;
1677 static const i386_operand_type disp32s
= OPERAND_TYPE_DISP32S
;
1678 static const i386_operand_type disp16_32
= OPERAND_TYPE_DISP16_32
;
1679 static const i386_operand_type anydisp
1680 = OPERAND_TYPE_ANYDISP
;
1681 static const i386_operand_type regxmm
= OPERAND_TYPE_REGXMM
;
1682 static const i386_operand_type regymm
= OPERAND_TYPE_REGYMM
;
1683 static const i386_operand_type regzmm
= OPERAND_TYPE_REGZMM
;
1684 static const i386_operand_type regmask
= OPERAND_TYPE_REGMASK
;
1685 static const i386_operand_type imm8
= OPERAND_TYPE_IMM8
;
1686 static const i386_operand_type imm8s
= OPERAND_TYPE_IMM8S
;
1687 static const i386_operand_type imm16
= OPERAND_TYPE_IMM16
;
1688 static const i386_operand_type imm32
= OPERAND_TYPE_IMM32
;
1689 static const i386_operand_type imm32s
= OPERAND_TYPE_IMM32S
;
1690 static const i386_operand_type imm64
= OPERAND_TYPE_IMM64
;
1691 static const i386_operand_type imm16_32
= OPERAND_TYPE_IMM16_32
;
1692 static const i386_operand_type imm16_32s
= OPERAND_TYPE_IMM16_32S
;
1693 static const i386_operand_type imm16_32_32s
= OPERAND_TYPE_IMM16_32_32S
;
1694 static const i386_operand_type vec_imm4
= OPERAND_TYPE_VEC_IMM4
;
1705 operand_type_check (i386_operand_type t
, enum operand_type c
)
1710 return (t
.bitfield
.reg8
1713 || t
.bitfield
.reg64
);
1716 return (t
.bitfield
.imm8
1720 || t
.bitfield
.imm32s
1721 || t
.bitfield
.imm64
);
1724 return (t
.bitfield
.disp8
1725 || t
.bitfield
.disp16
1726 || t
.bitfield
.disp32
1727 || t
.bitfield
.disp32s
1728 || t
.bitfield
.disp64
);
1731 return (t
.bitfield
.disp8
1732 || t
.bitfield
.disp16
1733 || t
.bitfield
.disp32
1734 || t
.bitfield
.disp32s
1735 || t
.bitfield
.disp64
1736 || t
.bitfield
.baseindex
);
1745 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1746 operand J for instruction template T. */
1749 match_reg_size (const insn_template
*t
, unsigned int j
)
1751 return !((i
.types
[j
].bitfield
.byte
1752 && !t
->operand_types
[j
].bitfield
.byte
)
1753 || (i
.types
[j
].bitfield
.word
1754 && !t
->operand_types
[j
].bitfield
.word
)
1755 || (i
.types
[j
].bitfield
.dword
1756 && !t
->operand_types
[j
].bitfield
.dword
)
1757 || (i
.types
[j
].bitfield
.qword
1758 && !t
->operand_types
[j
].bitfield
.qword
));
1761 /* Return 1 if there is no conflict in any size on operand J for
1762 instruction template T. */
1765 match_mem_size (const insn_template
*t
, unsigned int j
)
1767 return (match_reg_size (t
, j
)
1768 && !((i
.types
[j
].bitfield
.unspecified
1769 && !t
->operand_types
[j
].bitfield
.unspecified
)
1770 || (i
.types
[j
].bitfield
.fword
1771 && !t
->operand_types
[j
].bitfield
.fword
)
1772 || (i
.types
[j
].bitfield
.tbyte
1773 && !t
->operand_types
[j
].bitfield
.tbyte
)
1774 || (i
.types
[j
].bitfield
.xmmword
1775 && !t
->operand_types
[j
].bitfield
.xmmword
)
1776 || (i
.types
[j
].bitfield
.ymmword
1777 && !t
->operand_types
[j
].bitfield
.ymmword
)
1778 || (i
.types
[j
].bitfield
.zmmword
1779 && !t
->operand_types
[j
].bitfield
.zmmword
)));
1782 /* Return 1 if there is no size conflict on any operands for
1783 instruction template T. */
1786 operand_size_match (const insn_template
*t
)
1791 /* Don't check jump instructions. */
1792 if (t
->opcode_modifier
.jump
1793 || t
->opcode_modifier
.jumpbyte
1794 || t
->opcode_modifier
.jumpdword
1795 || t
->opcode_modifier
.jumpintersegment
)
1798 /* Check memory and accumulator operand size. */
1799 for (j
= 0; j
< i
.operands
; j
++)
1801 if (t
->operand_types
[j
].bitfield
.anysize
)
1804 if (t
->operand_types
[j
].bitfield
.acc
&& !match_reg_size (t
, j
))
1810 if (i
.types
[j
].bitfield
.mem
&& !match_mem_size (t
, j
))
1819 else if (!t
->opcode_modifier
.d
&& !t
->opcode_modifier
.floatd
)
1822 i
.error
= operand_size_mismatch
;
1826 /* Check reverse. */
1827 gas_assert (i
.operands
== 2);
1830 for (j
= 0; j
< 2; j
++)
1832 if (t
->operand_types
[j
].bitfield
.acc
1833 && !match_reg_size (t
, j
? 0 : 1))
1836 if (i
.types
[j
].bitfield
.mem
1837 && !match_mem_size (t
, j
? 0 : 1))
1845 operand_type_match (i386_operand_type overlap
,
1846 i386_operand_type given
)
1848 i386_operand_type temp
= overlap
;
1850 temp
.bitfield
.jumpabsolute
= 0;
1851 temp
.bitfield
.unspecified
= 0;
1852 temp
.bitfield
.byte
= 0;
1853 temp
.bitfield
.word
= 0;
1854 temp
.bitfield
.dword
= 0;
1855 temp
.bitfield
.fword
= 0;
1856 temp
.bitfield
.qword
= 0;
1857 temp
.bitfield
.tbyte
= 0;
1858 temp
.bitfield
.xmmword
= 0;
1859 temp
.bitfield
.ymmword
= 0;
1860 temp
.bitfield
.zmmword
= 0;
1861 if (operand_type_all_zero (&temp
))
1864 if (given
.bitfield
.baseindex
== overlap
.bitfield
.baseindex
1865 && given
.bitfield
.jumpabsolute
== overlap
.bitfield
.jumpabsolute
)
1869 i
.error
= operand_type_mismatch
;
1873 /* If given types g0 and g1 are registers they must be of the same type
1874 unless the expected operand type register overlap is null.
1875 Note that Acc in a template matches every size of reg. */
1878 operand_type_register_match (i386_operand_type m0
,
1879 i386_operand_type g0
,
1880 i386_operand_type t0
,
1881 i386_operand_type m1
,
1882 i386_operand_type g1
,
1883 i386_operand_type t1
)
1885 if (!operand_type_check (g0
, reg
))
1888 if (!operand_type_check (g1
, reg
))
1891 if (g0
.bitfield
.reg8
== g1
.bitfield
.reg8
1892 && g0
.bitfield
.reg16
== g1
.bitfield
.reg16
1893 && g0
.bitfield
.reg32
== g1
.bitfield
.reg32
1894 && g0
.bitfield
.reg64
== g1
.bitfield
.reg64
)
1897 if (m0
.bitfield
.acc
)
1899 t0
.bitfield
.reg8
= 1;
1900 t0
.bitfield
.reg16
= 1;
1901 t0
.bitfield
.reg32
= 1;
1902 t0
.bitfield
.reg64
= 1;
1905 if (m1
.bitfield
.acc
)
1907 t1
.bitfield
.reg8
= 1;
1908 t1
.bitfield
.reg16
= 1;
1909 t1
.bitfield
.reg32
= 1;
1910 t1
.bitfield
.reg64
= 1;
1913 if (!(t0
.bitfield
.reg8
& t1
.bitfield
.reg8
)
1914 && !(t0
.bitfield
.reg16
& t1
.bitfield
.reg16
)
1915 && !(t0
.bitfield
.reg32
& t1
.bitfield
.reg32
)
1916 && !(t0
.bitfield
.reg64
& t1
.bitfield
.reg64
))
1919 i
.error
= register_type_mismatch
;
1924 static INLINE
unsigned int
1925 register_number (const reg_entry
*r
)
1927 unsigned int nr
= r
->reg_num
;
1929 if (r
->reg_flags
& RegRex
)
1935 static INLINE
unsigned int
1936 mode_from_disp_size (i386_operand_type t
)
1938 if (t
.bitfield
.disp8
|| t
.bitfield
.vec_disp8
)
1940 else if (t
.bitfield
.disp16
1941 || t
.bitfield
.disp32
1942 || t
.bitfield
.disp32s
)
1949 fits_in_signed_byte (addressT num
)
1951 return num
+ 0x80 <= 0xff;
1955 fits_in_unsigned_byte (addressT num
)
1961 fits_in_unsigned_word (addressT num
)
1963 return num
<= 0xffff;
1967 fits_in_signed_word (addressT num
)
1969 return num
+ 0x8000 <= 0xffff;
1973 fits_in_signed_long (addressT num ATTRIBUTE_UNUSED
)
1978 return num
+ 0x80000000 <= 0xffffffff;
1980 } /* fits_in_signed_long() */
1983 fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED
)
1988 return num
<= 0xffffffff;
1990 } /* fits_in_unsigned_long() */
1993 fits_in_vec_disp8 (offsetT num
)
1995 int shift
= i
.memshift
;
2001 mask
= (1 << shift
) - 1;
2003 /* Return 0 if NUM isn't properly aligned. */
2007 /* Check if NUM will fit in 8bit after shift. */
2008 return fits_in_signed_byte (num
>> shift
);
2012 fits_in_imm4 (offsetT num
)
2014 return (num
& 0xf) == num
;
2017 static i386_operand_type
2018 smallest_imm_type (offsetT num
)
2020 i386_operand_type t
;
2022 operand_type_set (&t
, 0);
2023 t
.bitfield
.imm64
= 1;
2025 if (cpu_arch_tune
!= PROCESSOR_I486
&& num
== 1)
2027 /* This code is disabled on the 486 because all the Imm1 forms
2028 in the opcode table are slower on the i486. They're the
2029 versions with the implicitly specified single-position
2030 displacement, which has another syntax if you really want to
2032 t
.bitfield
.imm1
= 1;
2033 t
.bitfield
.imm8
= 1;
2034 t
.bitfield
.imm8s
= 1;
2035 t
.bitfield
.imm16
= 1;
2036 t
.bitfield
.imm32
= 1;
2037 t
.bitfield
.imm32s
= 1;
2039 else if (fits_in_signed_byte (num
))
2041 t
.bitfield
.imm8
= 1;
2042 t
.bitfield
.imm8s
= 1;
2043 t
.bitfield
.imm16
= 1;
2044 t
.bitfield
.imm32
= 1;
2045 t
.bitfield
.imm32s
= 1;
2047 else if (fits_in_unsigned_byte (num
))
2049 t
.bitfield
.imm8
= 1;
2050 t
.bitfield
.imm16
= 1;
2051 t
.bitfield
.imm32
= 1;
2052 t
.bitfield
.imm32s
= 1;
2054 else if (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
2056 t
.bitfield
.imm16
= 1;
2057 t
.bitfield
.imm32
= 1;
2058 t
.bitfield
.imm32s
= 1;
2060 else if (fits_in_signed_long (num
))
2062 t
.bitfield
.imm32
= 1;
2063 t
.bitfield
.imm32s
= 1;
2065 else if (fits_in_unsigned_long (num
))
2066 t
.bitfield
.imm32
= 1;
2072 offset_in_range (offsetT val
, int size
)
2078 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
2079 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
2080 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
2082 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
2088 /* If BFD64, sign extend val for 32bit address mode. */
2089 if (flag_code
!= CODE_64BIT
2090 || i
.prefix
[ADDR_PREFIX
])
2091 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
2092 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
2095 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
2097 char buf1
[40], buf2
[40];
2099 sprint_value (buf1
, val
);
2100 sprint_value (buf2
, val
& mask
);
2101 as_warn (_("%s shortened to %s"), buf1
, buf2
);
2115 a. PREFIX_EXIST if attempting to add a prefix where one from the
2116 same class already exists.
2117 b. PREFIX_LOCK if lock prefix is added.
2118 c. PREFIX_REP if rep/repne prefix is added.
2119 d. PREFIX_OTHER if other prefix is added.
2122 static enum PREFIX_GROUP
2123 add_prefix (unsigned int prefix
)
2125 enum PREFIX_GROUP ret
= PREFIX_OTHER
;
2128 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
2129 && flag_code
== CODE_64BIT
)
2131 if ((i
.prefix
[REX_PREFIX
] & prefix
& REX_W
)
2132 || ((i
.prefix
[REX_PREFIX
] & (REX_R
| REX_X
| REX_B
))
2133 && (prefix
& (REX_R
| REX_X
| REX_B
))))
2144 case CS_PREFIX_OPCODE
:
2145 case DS_PREFIX_OPCODE
:
2146 case ES_PREFIX_OPCODE
:
2147 case FS_PREFIX_OPCODE
:
2148 case GS_PREFIX_OPCODE
:
2149 case SS_PREFIX_OPCODE
:
2153 case REPNE_PREFIX_OPCODE
:
2154 case REPE_PREFIX_OPCODE
:
2159 case LOCK_PREFIX_OPCODE
:
2168 case ADDR_PREFIX_OPCODE
:
2172 case DATA_PREFIX_OPCODE
:
2176 if (i
.prefix
[q
] != 0)
2184 i
.prefix
[q
] |= prefix
;
2187 as_bad (_("same type of prefix used twice"));
2193 update_code_flag (int value
, int check
)
2195 PRINTF_LIKE ((*as_error
));
2197 flag_code
= (enum flag_code
) value
;
2198 if (flag_code
== CODE_64BIT
)
2200 cpu_arch_flags
.bitfield
.cpu64
= 1;
2201 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2205 cpu_arch_flags
.bitfield
.cpu64
= 0;
2206 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2208 if (value
== CODE_64BIT
&& !cpu_arch_flags
.bitfield
.cpulm
)
2211 as_error
= as_fatal
;
2214 (*as_error
) (_("64bit mode not supported on `%s'."),
2215 cpu_arch_name
? cpu_arch_name
: default_arch
);
2217 if (value
== CODE_32BIT
&& !cpu_arch_flags
.bitfield
.cpui386
)
2220 as_error
= as_fatal
;
2223 (*as_error
) (_("32bit mode not supported on `%s'."),
2224 cpu_arch_name
? cpu_arch_name
: default_arch
);
2226 stackop_size
= '\0';
2230 set_code_flag (int value
)
2232 update_code_flag (value
, 0);
2236 set_16bit_gcc_code_flag (int new_code_flag
)
2238 flag_code
= (enum flag_code
) new_code_flag
;
2239 if (flag_code
!= CODE_16BIT
)
2241 cpu_arch_flags
.bitfield
.cpu64
= 0;
2242 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2243 stackop_size
= LONG_MNEM_SUFFIX
;
2247 set_intel_syntax (int syntax_flag
)
2249 /* Find out if register prefixing is specified. */
2250 int ask_naked_reg
= 0;
2253 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2255 char *string
= input_line_pointer
;
2256 int e
= get_symbol_end ();
2258 if (strcmp (string
, "prefix") == 0)
2260 else if (strcmp (string
, "noprefix") == 0)
2263 as_bad (_("bad argument to syntax directive."));
2264 *input_line_pointer
= e
;
2266 demand_empty_rest_of_line ();
2268 intel_syntax
= syntax_flag
;
2270 if (ask_naked_reg
== 0)
2271 allow_naked_reg
= (intel_syntax
2272 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
2274 allow_naked_reg
= (ask_naked_reg
< 0);
2276 expr_set_rank (O_full_ptr
, syntax_flag
? 10 : 0);
2278 identifier_chars
['%'] = intel_syntax
&& allow_naked_reg
? '%' : 0;
2279 identifier_chars
['$'] = intel_syntax
? '$' : 0;
2280 register_prefix
= allow_naked_reg
? "" : "%";
2284 set_intel_mnemonic (int mnemonic_flag
)
2286 intel_mnemonic
= mnemonic_flag
;
2290 set_allow_index_reg (int flag
)
2292 allow_index_reg
= flag
;
2296 set_check (int what
)
2298 enum check_kind
*kind
;
2303 kind
= &operand_check
;
2314 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2316 char *string
= input_line_pointer
;
2317 int e
= get_symbol_end ();
2319 if (strcmp (string
, "none") == 0)
2321 else if (strcmp (string
, "warning") == 0)
2322 *kind
= check_warning
;
2323 else if (strcmp (string
, "error") == 0)
2324 *kind
= check_error
;
2326 as_bad (_("bad argument to %s_check directive."), str
);
2327 *input_line_pointer
= e
;
2330 as_bad (_("missing argument for %s_check directive"), str
);
2332 demand_empty_rest_of_line ();
2336 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED
,
2337 i386_cpu_flags new_flag ATTRIBUTE_UNUSED
)
2339 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2340 static const char *arch
;
2342 /* Intel LIOM is only supported on ELF. */
2348 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2349 use default_arch. */
2350 arch
= cpu_arch_name
;
2352 arch
= default_arch
;
2355 /* If we are targeting Intel L1OM, we must enable it. */
2356 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_L1OM
2357 || new_flag
.bitfield
.cpul1om
)
2360 /* If we are targeting Intel K1OM, we must enable it. */
2361 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_K1OM
2362 || new_flag
.bitfield
.cpuk1om
)
2365 as_bad (_("`%s' is not supported on `%s'"), name
, arch
);
2370 set_cpu_arch (int dummy ATTRIBUTE_UNUSED
)
2374 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2376 char *string
= input_line_pointer
;
2377 int e
= get_symbol_end ();
2379 i386_cpu_flags flags
;
2381 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
2383 if (strcmp (string
, cpu_arch
[j
].name
) == 0)
2385 check_cpu_arch_compatible (string
, cpu_arch
[j
].flags
);
2389 cpu_arch_name
= cpu_arch
[j
].name
;
2390 cpu_sub_arch_name
= NULL
;
2391 cpu_arch_flags
= cpu_arch
[j
].flags
;
2392 if (flag_code
== CODE_64BIT
)
2394 cpu_arch_flags
.bitfield
.cpu64
= 1;
2395 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2399 cpu_arch_flags
.bitfield
.cpu64
= 0;
2400 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2402 cpu_arch_isa
= cpu_arch
[j
].type
;
2403 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
2404 if (!cpu_arch_tune_set
)
2406 cpu_arch_tune
= cpu_arch_isa
;
2407 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
2412 if (!cpu_arch
[j
].negated
)
2413 flags
= cpu_flags_or (cpu_arch_flags
,
2416 flags
= cpu_flags_and_not (cpu_arch_flags
,
2418 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2420 if (cpu_sub_arch_name
)
2422 char *name
= cpu_sub_arch_name
;
2423 cpu_sub_arch_name
= concat (name
,
2425 (const char *) NULL
);
2429 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
2430 cpu_arch_flags
= flags
;
2431 cpu_arch_isa_flags
= flags
;
2433 *input_line_pointer
= e
;
2434 demand_empty_rest_of_line ();
2438 if (j
>= ARRAY_SIZE (cpu_arch
))
2439 as_bad (_("no such architecture: `%s'"), string
);
2441 *input_line_pointer
= e
;
2444 as_bad (_("missing cpu architecture"));
2446 no_cond_jump_promotion
= 0;
2447 if (*input_line_pointer
== ','
2448 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
2450 char *string
= ++input_line_pointer
;
2451 int e
= get_symbol_end ();
2453 if (strcmp (string
, "nojumps") == 0)
2454 no_cond_jump_promotion
= 1;
2455 else if (strcmp (string
, "jumps") == 0)
2458 as_bad (_("no such architecture modifier: `%s'"), string
);
2460 *input_line_pointer
= e
;
2463 demand_empty_rest_of_line ();
2466 enum bfd_architecture
2469 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2471 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2472 || flag_code
!= CODE_64BIT
)
2473 as_fatal (_("Intel L1OM is 64bit ELF only"));
2474 return bfd_arch_l1om
;
2476 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2478 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2479 || flag_code
!= CODE_64BIT
)
2480 as_fatal (_("Intel K1OM is 64bit ELF only"));
2481 return bfd_arch_k1om
;
2484 return bfd_arch_i386
;
2490 if (!strncmp (default_arch
, "x86_64", 6))
2492 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2494 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2495 || default_arch
[6] != '\0')
2496 as_fatal (_("Intel L1OM is 64bit ELF only"));
2497 return bfd_mach_l1om
;
2499 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2501 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2502 || default_arch
[6] != '\0')
2503 as_fatal (_("Intel K1OM is 64bit ELF only"));
2504 return bfd_mach_k1om
;
2506 else if (default_arch
[6] == '\0')
2507 return bfd_mach_x86_64
;
2509 return bfd_mach_x64_32
;
2511 else if (!strcmp (default_arch
, "i386"))
2512 return bfd_mach_i386_i386
;
2514 as_fatal (_("unknown architecture"));
2520 const char *hash_err
;
2522 /* Initialize op_hash hash table. */
2523 op_hash
= hash_new ();
2526 const insn_template
*optab
;
2527 templates
*core_optab
;
2529 /* Setup for loop. */
2531 core_optab
= (templates
*) xmalloc (sizeof (templates
));
2532 core_optab
->start
= optab
;
2537 if (optab
->name
== NULL
2538 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
2540 /* different name --> ship out current template list;
2541 add to hash table; & begin anew. */
2542 core_optab
->end
= optab
;
2543 hash_err
= hash_insert (op_hash
,
2545 (void *) core_optab
);
2548 as_fatal (_("can't hash %s: %s"),
2552 if (optab
->name
== NULL
)
2554 core_optab
= (templates
*) xmalloc (sizeof (templates
));
2555 core_optab
->start
= optab
;
2560 /* Initialize reg_hash hash table. */
2561 reg_hash
= hash_new ();
2563 const reg_entry
*regtab
;
2564 unsigned int regtab_size
= i386_regtab_size
;
2566 for (regtab
= i386_regtab
; regtab_size
--; regtab
++)
2568 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (void *) regtab
);
2570 as_fatal (_("can't hash %s: %s"),
2576 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
2581 for (c
= 0; c
< 256; c
++)
2586 mnemonic_chars
[c
] = c
;
2587 register_chars
[c
] = c
;
2588 operand_chars
[c
] = c
;
2590 else if (ISLOWER (c
))
2592 mnemonic_chars
[c
] = c
;
2593 register_chars
[c
] = c
;
2594 operand_chars
[c
] = c
;
2596 else if (ISUPPER (c
))
2598 mnemonic_chars
[c
] = TOLOWER (c
);
2599 register_chars
[c
] = mnemonic_chars
[c
];
2600 operand_chars
[c
] = c
;
2602 else if (c
== '{' || c
== '}')
2603 operand_chars
[c
] = c
;
2605 if (ISALPHA (c
) || ISDIGIT (c
))
2606 identifier_chars
[c
] = c
;
2609 identifier_chars
[c
] = c
;
2610 operand_chars
[c
] = c
;
2615 identifier_chars
['@'] = '@';
2618 identifier_chars
['?'] = '?';
2619 operand_chars
['?'] = '?';
2621 digit_chars
['-'] = '-';
2622 mnemonic_chars
['_'] = '_';
2623 mnemonic_chars
['-'] = '-';
2624 mnemonic_chars
['.'] = '.';
2625 identifier_chars
['_'] = '_';
2626 identifier_chars
['.'] = '.';
2628 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
2629 operand_chars
[(unsigned char) *p
] = *p
;
2632 if (flag_code
== CODE_64BIT
)
2634 #if defined (OBJ_COFF) && defined (TE_PE)
2635 x86_dwarf2_return_column
= (OUTPUT_FLAVOR
== bfd_target_coff_flavour
2638 x86_dwarf2_return_column
= 16;
2640 x86_cie_data_alignment
= -8;
2644 x86_dwarf2_return_column
= 8;
2645 x86_cie_data_alignment
= -4;
2650 i386_print_statistics (FILE *file
)
2652 hash_print_statistics (file
, "i386 opcode", op_hash
);
2653 hash_print_statistics (file
, "i386 register", reg_hash
);
2658 /* Debugging routines for md_assemble. */
2659 static void pte (insn_template
*);
2660 static void pt (i386_operand_type
);
2661 static void pe (expressionS
*);
2662 static void ps (symbolS
*);
2665 pi (char *line
, i386_insn
*x
)
2669 fprintf (stdout
, "%s: template ", line
);
2671 fprintf (stdout
, " address: base %s index %s scale %x\n",
2672 x
->base_reg
? x
->base_reg
->reg_name
: "none",
2673 x
->index_reg
? x
->index_reg
->reg_name
: "none",
2674 x
->log2_scale_factor
);
2675 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
2676 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
2677 fprintf (stdout
, " sib: base %x index %x scale %x\n",
2678 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
2679 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
2680 (x
->rex
& REX_W
) != 0,
2681 (x
->rex
& REX_R
) != 0,
2682 (x
->rex
& REX_X
) != 0,
2683 (x
->rex
& REX_B
) != 0);
2684 for (j
= 0; j
< x
->operands
; j
++)
2686 fprintf (stdout
, " #%d: ", j
+ 1);
2688 fprintf (stdout
, "\n");
2689 if (x
->types
[j
].bitfield
.reg8
2690 || x
->types
[j
].bitfield
.reg16
2691 || x
->types
[j
].bitfield
.reg32
2692 || x
->types
[j
].bitfield
.reg64
2693 || x
->types
[j
].bitfield
.regmmx
2694 || x
->types
[j
].bitfield
.regxmm
2695 || x
->types
[j
].bitfield
.regymm
2696 || x
->types
[j
].bitfield
.regzmm
2697 || x
->types
[j
].bitfield
.sreg2
2698 || x
->types
[j
].bitfield
.sreg3
2699 || x
->types
[j
].bitfield
.control
2700 || x
->types
[j
].bitfield
.debug
2701 || x
->types
[j
].bitfield
.test
)
2702 fprintf (stdout
, "%s\n", x
->op
[j
].regs
->reg_name
);
2703 if (operand_type_check (x
->types
[j
], imm
))
2705 if (operand_type_check (x
->types
[j
], disp
))
2706 pe (x
->op
[j
].disps
);
2711 pte (insn_template
*t
)
2714 fprintf (stdout
, " %d operands ", t
->operands
);
2715 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
2716 if (t
->extension_opcode
!= None
)
2717 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
2718 if (t
->opcode_modifier
.d
)
2719 fprintf (stdout
, "D");
2720 if (t
->opcode_modifier
.w
)
2721 fprintf (stdout
, "W");
2722 fprintf (stdout
, "\n");
2723 for (j
= 0; j
< t
->operands
; j
++)
2725 fprintf (stdout
, " #%d type ", j
+ 1);
2726 pt (t
->operand_types
[j
]);
2727 fprintf (stdout
, "\n");
2734 fprintf (stdout
, " operation %d\n", e
->X_op
);
2735 fprintf (stdout
, " add_number %ld (%lx)\n",
2736 (long) e
->X_add_number
, (long) e
->X_add_number
);
2737 if (e
->X_add_symbol
)
2739 fprintf (stdout
, " add_symbol ");
2740 ps (e
->X_add_symbol
);
2741 fprintf (stdout
, "\n");
2745 fprintf (stdout
, " op_symbol ");
2746 ps (e
->X_op_symbol
);
2747 fprintf (stdout
, "\n");
2754 fprintf (stdout
, "%s type %s%s",
2756 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
2757 segment_name (S_GET_SEGMENT (s
)));
2760 static struct type_name
2762 i386_operand_type mask
;
2765 const type_names
[] =
2767 { OPERAND_TYPE_REG8
, "r8" },
2768 { OPERAND_TYPE_REG16
, "r16" },
2769 { OPERAND_TYPE_REG32
, "r32" },
2770 { OPERAND_TYPE_REG64
, "r64" },
2771 { OPERAND_TYPE_IMM8
, "i8" },
2772 { OPERAND_TYPE_IMM8
, "i8s" },
2773 { OPERAND_TYPE_IMM16
, "i16" },
2774 { OPERAND_TYPE_IMM32
, "i32" },
2775 { OPERAND_TYPE_IMM32S
, "i32s" },
2776 { OPERAND_TYPE_IMM64
, "i64" },
2777 { OPERAND_TYPE_IMM1
, "i1" },
2778 { OPERAND_TYPE_BASEINDEX
, "BaseIndex" },
2779 { OPERAND_TYPE_DISP8
, "d8" },
2780 { OPERAND_TYPE_DISP16
, "d16" },
2781 { OPERAND_TYPE_DISP32
, "d32" },
2782 { OPERAND_TYPE_DISP32S
, "d32s" },
2783 { OPERAND_TYPE_DISP64
, "d64" },
2784 { OPERAND_TYPE_VEC_DISP8
, "Vector d8" },
2785 { OPERAND_TYPE_INOUTPORTREG
, "InOutPortReg" },
2786 { OPERAND_TYPE_SHIFTCOUNT
, "ShiftCount" },
2787 { OPERAND_TYPE_CONTROL
, "control reg" },
2788 { OPERAND_TYPE_TEST
, "test reg" },
2789 { OPERAND_TYPE_DEBUG
, "debug reg" },
2790 { OPERAND_TYPE_FLOATREG
, "FReg" },
2791 { OPERAND_TYPE_FLOATACC
, "FAcc" },
2792 { OPERAND_TYPE_SREG2
, "SReg2" },
2793 { OPERAND_TYPE_SREG3
, "SReg3" },
2794 { OPERAND_TYPE_ACC
, "Acc" },
2795 { OPERAND_TYPE_JUMPABSOLUTE
, "Jump Absolute" },
2796 { OPERAND_TYPE_REGMMX
, "rMMX" },
2797 { OPERAND_TYPE_REGXMM
, "rXMM" },
2798 { OPERAND_TYPE_REGYMM
, "rYMM" },
2799 { OPERAND_TYPE_REGZMM
, "rZMM" },
2800 { OPERAND_TYPE_REGMASK
, "Mask reg" },
2801 { OPERAND_TYPE_ESSEG
, "es" },
2805 pt (i386_operand_type t
)
2808 i386_operand_type a
;
2810 for (j
= 0; j
< ARRAY_SIZE (type_names
); j
++)
2812 a
= operand_type_and (t
, type_names
[j
].mask
);
2813 if (!operand_type_all_zero (&a
))
2814 fprintf (stdout
, "%s, ", type_names
[j
].name
);
2819 #endif /* DEBUG386 */
2821 static bfd_reloc_code_real_type
2822 reloc (unsigned int size
,
2826 bfd_reloc_code_real_type other
)
2828 if (other
!= NO_RELOC
)
2830 reloc_howto_type
*rel
;
2835 case BFD_RELOC_X86_64_GOT32
:
2836 return BFD_RELOC_X86_64_GOT64
;
2838 case BFD_RELOC_X86_64_PLTOFF64
:
2839 return BFD_RELOC_X86_64_PLTOFF64
;
2841 case BFD_RELOC_X86_64_GOTPC32
:
2842 other
= BFD_RELOC_X86_64_GOTPC64
;
2844 case BFD_RELOC_X86_64_GOTPCREL
:
2845 other
= BFD_RELOC_X86_64_GOTPCREL64
;
2847 case BFD_RELOC_X86_64_TPOFF32
:
2848 other
= BFD_RELOC_X86_64_TPOFF64
;
2850 case BFD_RELOC_X86_64_DTPOFF32
:
2851 other
= BFD_RELOC_X86_64_DTPOFF64
;
2857 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2858 if (other
== BFD_RELOC_SIZE32
)
2861 other
= BFD_RELOC_SIZE64
;
2864 as_bad (_("there are no pc-relative size relocations"));
2870 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
2871 if (size
== 4 && (flag_code
!= CODE_64BIT
|| disallow_64bit_reloc
))
2874 rel
= bfd_reloc_type_lookup (stdoutput
, other
);
2876 as_bad (_("unknown relocation (%u)"), other
);
2877 else if (size
!= bfd_get_reloc_size (rel
))
2878 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
2879 bfd_get_reloc_size (rel
),
2881 else if (pcrel
&& !rel
->pc_relative
)
2882 as_bad (_("non-pc-relative relocation for pc-relative field"));
2883 else if ((rel
->complain_on_overflow
== complain_overflow_signed
2885 || (rel
->complain_on_overflow
== complain_overflow_unsigned
2887 as_bad (_("relocated field and relocation type differ in signedness"));
2896 as_bad (_("there are no unsigned pc-relative relocations"));
2899 case 1: return BFD_RELOC_8_PCREL
;
2900 case 2: return BFD_RELOC_16_PCREL
;
2901 case 4: return (bnd_prefix
&& object_64bit
2902 ? BFD_RELOC_X86_64_PC32_BND
2903 : BFD_RELOC_32_PCREL
);
2904 case 8: return BFD_RELOC_64_PCREL
;
2906 as_bad (_("cannot do %u byte pc-relative relocation"), size
);
2913 case 4: return BFD_RELOC_X86_64_32S
;
2918 case 1: return BFD_RELOC_8
;
2919 case 2: return BFD_RELOC_16
;
2920 case 4: return BFD_RELOC_32
;
2921 case 8: return BFD_RELOC_64
;
2923 as_bad (_("cannot do %s %u byte relocation"),
2924 sign
> 0 ? "signed" : "unsigned", size
);
2930 /* Here we decide which fixups can be adjusted to make them relative to
2931 the beginning of the section instead of the symbol. Basically we need
2932 to make sure that the dynamic relocations are done correctly, so in
2933 some cases we force the original symbol to be used. */
2936 tc_i386_fix_adjustable (fixS
*fixP ATTRIBUTE_UNUSED
)
2938 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2942 /* Don't adjust pc-relative references to merge sections in 64-bit
2944 if (use_rela_relocations
2945 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
2949 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
2950 and changed later by validate_fix. */
2951 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
2952 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
2955 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
2956 for size relocations. */
2957 if (fixP
->fx_r_type
== BFD_RELOC_SIZE32
2958 || fixP
->fx_r_type
== BFD_RELOC_SIZE64
2959 || fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
2960 || fixP
->fx_r_type
== BFD_RELOC_386_PLT32
2961 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
2962 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
2963 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
2964 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
2965 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
2966 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
2967 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
2968 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
2969 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
2970 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTDESC
2971 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_DESC_CALL
2972 || fixP
->fx_r_type
== BFD_RELOC_X86_64_PLT32
2973 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
2974 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
2975 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
2976 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
2977 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
2978 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
2979 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
2980 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
2981 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
2982 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
2983 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPC32_TLSDESC
2984 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSDESC_CALL
2985 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
2986 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
2993 intel_float_operand (const char *mnemonic
)
2995 /* Note that the value returned is meaningful only for opcodes with (memory)
2996 operands, hence the code here is free to improperly handle opcodes that
2997 have no operands (for better performance and smaller code). */
2999 if (mnemonic
[0] != 'f')
3000 return 0; /* non-math */
3002 switch (mnemonic
[1])
3004 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
3005 the fs segment override prefix not currently handled because no
3006 call path can make opcodes without operands get here */
3008 return 2 /* integer op */;
3010 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
3011 return 3; /* fldcw/fldenv */
3014 if (mnemonic
[2] != 'o' /* fnop */)
3015 return 3; /* non-waiting control op */
3018 if (mnemonic
[2] == 's')
3019 return 3; /* frstor/frstpm */
3022 if (mnemonic
[2] == 'a')
3023 return 3; /* fsave */
3024 if (mnemonic
[2] == 't')
3026 switch (mnemonic
[3])
3028 case 'c': /* fstcw */
3029 case 'd': /* fstdw */
3030 case 'e': /* fstenv */
3031 case 's': /* fsts[gw] */
3037 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
3038 return 0; /* fxsave/fxrstor are not really math ops */
3045 /* Build the VEX prefix. */
3048 build_vex_prefix (const insn_template
*t
)
3050 unsigned int register_specifier
;
3051 unsigned int implied_prefix
;
3052 unsigned int vector_length
;
3054 /* Check register specifier. */
3055 if (i
.vex
.register_specifier
)
3057 register_specifier
=
3058 ~register_number (i
.vex
.register_specifier
) & 0xf;
3059 gas_assert ((i
.vex
.register_specifier
->reg_flags
& RegVRex
) == 0);
3062 register_specifier
= 0xf;
3064 /* Use 2-byte VEX prefix by swappping destination and source
3067 && i
.operands
== i
.reg_operands
3068 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3069 && i
.tm
.opcode_modifier
.s
3072 unsigned int xchg
= i
.operands
- 1;
3073 union i386_op temp_op
;
3074 i386_operand_type temp_type
;
3076 temp_type
= i
.types
[xchg
];
3077 i
.types
[xchg
] = i
.types
[0];
3078 i
.types
[0] = temp_type
;
3079 temp_op
= i
.op
[xchg
];
3080 i
.op
[xchg
] = i
.op
[0];
3083 gas_assert (i
.rm
.mode
== 3);
3087 i
.rm
.regmem
= i
.rm
.reg
;
3090 /* Use the next insn. */
3094 if (i
.tm
.opcode_modifier
.vex
== VEXScalar
)
3095 vector_length
= avxscalar
;
3097 vector_length
= i
.tm
.opcode_modifier
.vex
== VEX256
? 1 : 0;
3099 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3104 case DATA_PREFIX_OPCODE
:
3107 case REPE_PREFIX_OPCODE
:
3110 case REPNE_PREFIX_OPCODE
:
3117 /* Use 2-byte VEX prefix if possible. */
3118 if (i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3119 && i
.tm
.opcode_modifier
.vexw
!= VEXW1
3120 && (i
.rex
& (REX_W
| REX_X
| REX_B
)) == 0)
3122 /* 2-byte VEX prefix. */
3126 i
.vex
.bytes
[0] = 0xc5;
3128 /* Check the REX.R bit. */
3129 r
= (i
.rex
& REX_R
) ? 0 : 1;
3130 i
.vex
.bytes
[1] = (r
<< 7
3131 | register_specifier
<< 3
3132 | vector_length
<< 2
3137 /* 3-byte VEX prefix. */
3142 switch (i
.tm
.opcode_modifier
.vexopcode
)
3146 i
.vex
.bytes
[0] = 0xc4;
3150 i
.vex
.bytes
[0] = 0xc4;
3154 i
.vex
.bytes
[0] = 0xc4;
3158 i
.vex
.bytes
[0] = 0x8f;
3162 i
.vex
.bytes
[0] = 0x8f;
3166 i
.vex
.bytes
[0] = 0x8f;
3172 /* The high 3 bits of the second VEX byte are 1's compliment
3173 of RXB bits from REX. */
3174 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3176 /* Check the REX.W bit. */
3177 w
= (i
.rex
& REX_W
) ? 1 : 0;
3178 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
3181 i
.vex
.bytes
[2] = (w
<< 7
3182 | register_specifier
<< 3
3183 | vector_length
<< 2
3188 /* Build the EVEX prefix. */
3191 build_evex_prefix (void)
3193 unsigned int register_specifier
;
3194 unsigned int implied_prefix
;
3196 rex_byte vrex_used
= 0;
3198 /* Check register specifier. */
3199 if (i
.vex
.register_specifier
)
3201 gas_assert ((i
.vrex
& REX_X
) == 0);
3203 register_specifier
= i
.vex
.register_specifier
->reg_num
;
3204 if ((i
.vex
.register_specifier
->reg_flags
& RegRex
))
3205 register_specifier
+= 8;
3206 /* The upper 16 registers are encoded in the fourth byte of the
3208 if (!(i
.vex
.register_specifier
->reg_flags
& RegVRex
))
3209 i
.vex
.bytes
[3] = 0x8;
3210 register_specifier
= ~register_specifier
& 0xf;
3214 register_specifier
= 0xf;
3216 /* Encode upper 16 vector index register in the fourth byte of
3218 if (!(i
.vrex
& REX_X
))
3219 i
.vex
.bytes
[3] = 0x8;
3224 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3229 case DATA_PREFIX_OPCODE
:
3232 case REPE_PREFIX_OPCODE
:
3235 case REPNE_PREFIX_OPCODE
:
3242 /* 4 byte EVEX prefix. */
3244 i
.vex
.bytes
[0] = 0x62;
3247 switch (i
.tm
.opcode_modifier
.vexopcode
)
3263 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3265 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3267 /* The fifth bit of the second EVEX byte is 1's compliment of the
3268 REX_R bit in VREX. */
3269 if (!(i
.vrex
& REX_R
))
3270 i
.vex
.bytes
[1] |= 0x10;
3274 if ((i
.reg_operands
+ i
.imm_operands
) == i
.operands
)
3276 /* When all operands are registers, the REX_X bit in REX is not
3277 used. We reuse it to encode the upper 16 registers, which is
3278 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3279 as 1's compliment. */
3280 if ((i
.vrex
& REX_B
))
3283 i
.vex
.bytes
[1] &= ~0x40;
3287 /* EVEX instructions shouldn't need the REX prefix. */
3288 i
.vrex
&= ~vrex_used
;
3289 gas_assert (i
.vrex
== 0);
3291 /* Check the REX.W bit. */
3292 w
= (i
.rex
& REX_W
) ? 1 : 0;
3293 if (i
.tm
.opcode_modifier
.vexw
)
3295 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
3298 /* If w is not set it means we are dealing with WIG instruction. */
3301 if (evexwig
== evexw1
)
3305 /* Encode the U bit. */
3306 implied_prefix
|= 0x4;
3308 /* The third byte of the EVEX prefix. */
3309 i
.vex
.bytes
[2] = (w
<< 7 | register_specifier
<< 3 | implied_prefix
);
3311 /* The fourth byte of the EVEX prefix. */
3312 /* The zeroing-masking bit. */
3313 if (i
.mask
&& i
.mask
->zeroing
)
3314 i
.vex
.bytes
[3] |= 0x80;
3316 /* Don't always set the broadcast bit if there is no RC. */
3319 /* Encode the vector length. */
3320 unsigned int vec_length
;
3322 switch (i
.tm
.opcode_modifier
.evex
)
3324 case EVEXLIG
: /* LL' is ignored */
3325 vec_length
= evexlig
<< 5;
3328 vec_length
= 0 << 5;
3331 vec_length
= 1 << 5;
3334 vec_length
= 2 << 5;
3340 i
.vex
.bytes
[3] |= vec_length
;
3341 /* Encode the broadcast bit. */
3343 i
.vex
.bytes
[3] |= 0x10;
3347 if (i
.rounding
->type
!= saeonly
)
3348 i
.vex
.bytes
[3] |= 0x10 | (i
.rounding
->type
<< 5);
3350 i
.vex
.bytes
[3] |= 0x10 | (evexrcig
<< 5);
3353 if (i
.mask
&& i
.mask
->mask
)
3354 i
.vex
.bytes
[3] |= i
.mask
->mask
->reg_num
;
3358 process_immext (void)
3362 if ((i
.tm
.cpu_flags
.bitfield
.cpusse3
|| i
.tm
.cpu_flags
.bitfield
.cpusvme
)
3365 /* MONITOR/MWAIT as well as SVME instructions have fixed operands
3366 with an opcode suffix which is coded in the same place as an
3367 8-bit immediate field would be.
3368 Here we check those operands and remove them afterwards. */
3371 for (x
= 0; x
< i
.operands
; x
++)
3372 if (register_number (i
.op
[x
].regs
) != x
)
3373 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3374 register_prefix
, i
.op
[x
].regs
->reg_name
, x
+ 1,
3380 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
3381 which is coded in the same place as an 8-bit immediate field
3382 would be. Here we fake an 8-bit immediate operand from the
3383 opcode suffix stored in tm.extension_opcode.
3385 AVX instructions also use this encoding, for some of
3386 3 argument instructions. */
3388 gas_assert (i
.imm_operands
<= 1
3390 || ((i
.tm
.opcode_modifier
.vex
3391 || i
.tm
.opcode_modifier
.evex
)
3392 && i
.operands
<= 4)));
3394 exp
= &im_expressions
[i
.imm_operands
++];
3395 i
.op
[i
.operands
].imms
= exp
;
3396 i
.types
[i
.operands
] = imm8
;
3398 exp
->X_op
= O_constant
;
3399 exp
->X_add_number
= i
.tm
.extension_opcode
;
3400 i
.tm
.extension_opcode
= None
;
3407 switch (i
.tm
.opcode_modifier
.hleprefixok
)
3412 as_bad (_("invalid instruction `%s' after `%s'"),
3413 i
.tm
.name
, i
.hle_prefix
);
3416 if (i
.prefix
[LOCK_PREFIX
])
3418 as_bad (_("missing `lock' with `%s'"), i
.hle_prefix
);
3422 case HLEPrefixRelease
:
3423 if (i
.prefix
[HLE_PREFIX
] != XRELEASE_PREFIX_OPCODE
)
3425 as_bad (_("instruction `%s' after `xacquire' not allowed"),
3429 if (i
.mem_operands
== 0
3430 || !operand_type_check (i
.types
[i
.operands
- 1], anymem
))
3432 as_bad (_("memory destination needed for instruction `%s'"
3433 " after `xrelease'"), i
.tm
.name
);
3440 /* This is the guts of the machine-dependent assembler. LINE points to a
3441 machine dependent instruction. This function is supposed to emit
3442 the frags/bytes it assembles to. */
3445 md_assemble (char *line
)
3448 char mnemonic
[MAX_MNEM_SIZE
];
3449 const insn_template
*t
;
3451 /* Initialize globals. */
3452 memset (&i
, '\0', sizeof (i
));
3453 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3454 i
.reloc
[j
] = NO_RELOC
;
3455 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
3456 memset (im_expressions
, '\0', sizeof (im_expressions
));
3457 save_stack_p
= save_stack
;
3459 /* First parse an instruction mnemonic & call i386_operand for the operands.
3460 We assume that the scrubber has arranged it so that line[0] is the valid
3461 start of a (possibly prefixed) mnemonic. */
3463 line
= parse_insn (line
, mnemonic
);
3467 line
= parse_operands (line
, mnemonic
);
3472 /* Now we've parsed the mnemonic into a set of templates, and have the
3473 operands at hand. */
3475 /* All intel opcodes have reversed operands except for "bound" and
3476 "enter". We also don't reverse intersegment "jmp" and "call"
3477 instructions with 2 immediate operands so that the immediate segment
3478 precedes the offset, as it does when in AT&T mode. */
3481 && (strcmp (mnemonic
, "bound") != 0)
3482 && (strcmp (mnemonic
, "invlpga") != 0)
3483 && !(operand_type_check (i
.types
[0], imm
)
3484 && operand_type_check (i
.types
[1], imm
)))
3487 /* The order of the immediates should be reversed
3488 for 2 immediates extrq and insertq instructions */
3489 if (i
.imm_operands
== 2
3490 && (strcmp (mnemonic
, "extrq") == 0
3491 || strcmp (mnemonic
, "insertq") == 0))
3492 swap_2_operands (0, 1);
3497 /* Don't optimize displacement for movabs since it only takes 64bit
3500 && i
.disp_encoding
!= disp_encoding_32bit
3501 && (flag_code
!= CODE_64BIT
3502 || strcmp (mnemonic
, "movabs") != 0))
3505 /* Next, we find a template that matches the given insn,
3506 making sure the overlap of the given operands types is consistent
3507 with the template operand types. */
3509 if (!(t
= match_template ()))
3512 if (sse_check
!= check_none
3513 && !i
.tm
.opcode_modifier
.noavx
3514 && (i
.tm
.cpu_flags
.bitfield
.cpusse
3515 || i
.tm
.cpu_flags
.bitfield
.cpusse2
3516 || i
.tm
.cpu_flags
.bitfield
.cpusse3
3517 || i
.tm
.cpu_flags
.bitfield
.cpussse3
3518 || i
.tm
.cpu_flags
.bitfield
.cpusse4_1
3519 || i
.tm
.cpu_flags
.bitfield
.cpusse4_2
))
3521 (sse_check
== check_warning
3523 : as_bad
) (_("SSE instruction `%s' is used"), i
.tm
.name
);
3526 /* Zap movzx and movsx suffix. The suffix has been set from
3527 "word ptr" or "byte ptr" on the source operand in Intel syntax
3528 or extracted from mnemonic in AT&T syntax. But we'll use
3529 the destination register to choose the suffix for encoding. */
3530 if ((i
.tm
.base_opcode
& ~9) == 0x0fb6)
3532 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
3533 there is no suffix, the default will be byte extension. */
3534 if (i
.reg_operands
!= 2
3537 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
3542 if (i
.tm
.opcode_modifier
.fwait
)
3543 if (!add_prefix (FWAIT_OPCODE
))
3546 /* Check if REP prefix is OK. */
3547 if (i
.rep_prefix
&& !i
.tm
.opcode_modifier
.repprefixok
)
3549 as_bad (_("invalid instruction `%s' after `%s'"),
3550 i
.tm
.name
, i
.rep_prefix
);
3554 /* Check for lock without a lockable instruction. Destination operand
3555 must be memory unless it is xchg (0x86). */
3556 if (i
.prefix
[LOCK_PREFIX
]
3557 && (!i
.tm
.opcode_modifier
.islockable
3558 || i
.mem_operands
== 0
3559 || (i
.tm
.base_opcode
!= 0x86
3560 && !operand_type_check (i
.types
[i
.operands
- 1], anymem
))))
3562 as_bad (_("expecting lockable instruction after `lock'"));
3566 /* Check if HLE prefix is OK. */
3567 if (i
.hle_prefix
&& !check_hle ())
3570 /* Check BND prefix. */
3571 if (i
.bnd_prefix
&& !i
.tm
.opcode_modifier
.bndprefixok
)
3572 as_bad (_("expecting valid branch instruction after `bnd'"));
3574 if (i
.tm
.cpu_flags
.bitfield
.cpumpx
3575 && flag_code
== CODE_64BIT
3576 && i
.prefix
[ADDR_PREFIX
])
3577 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
3579 /* Insert BND prefix. */
3581 && i
.tm
.opcode_modifier
.bndprefixok
3582 && !i
.prefix
[BND_PREFIX
])
3583 add_prefix (BND_PREFIX_OPCODE
);
3585 /* Check string instruction segment overrides. */
3586 if (i
.tm
.opcode_modifier
.isstring
&& i
.mem_operands
!= 0)
3588 if (!check_string ())
3590 i
.disp_operands
= 0;
3593 if (!process_suffix ())
3596 /* Update operand types. */
3597 for (j
= 0; j
< i
.operands
; j
++)
3598 i
.types
[j
] = operand_type_and (i
.types
[j
], i
.tm
.operand_types
[j
]);
3600 /* Make still unresolved immediate matches conform to size of immediate
3601 given in i.suffix. */
3602 if (!finalize_imm ())
3605 if (i
.types
[0].bitfield
.imm1
)
3606 i
.imm_operands
= 0; /* kludge for shift insns. */
3608 /* We only need to check those implicit registers for instructions
3609 with 3 operands or less. */
3610 if (i
.operands
<= 3)
3611 for (j
= 0; j
< i
.operands
; j
++)
3612 if (i
.types
[j
].bitfield
.inoutportreg
3613 || i
.types
[j
].bitfield
.shiftcount
3614 || i
.types
[j
].bitfield
.acc
3615 || i
.types
[j
].bitfield
.floatacc
)
3618 /* ImmExt should be processed after SSE2AVX. */
3619 if (!i
.tm
.opcode_modifier
.sse2avx
3620 && i
.tm
.opcode_modifier
.immext
)
3623 /* For insns with operands there are more diddles to do to the opcode. */
3626 if (!process_operands ())
3629 else if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
3631 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
3632 as_warn (_("translating to `%sp'"), i
.tm
.name
);
3635 if (i
.tm
.opcode_modifier
.vex
|| i
.tm
.opcode_modifier
.evex
)
3637 if (flag_code
== CODE_16BIT
)
3639 as_bad (_("instruction `%s' isn't supported in 16-bit mode."),
3644 if (i
.tm
.opcode_modifier
.vex
)
3645 build_vex_prefix (t
);
3647 build_evex_prefix ();
3650 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
3651 instructions may define INT_OPCODE as well, so avoid this corner
3652 case for those instructions that use MODRM. */
3653 if (i
.tm
.base_opcode
== INT_OPCODE
3654 && !i
.tm
.opcode_modifier
.modrm
3655 && i
.op
[0].imms
->X_add_number
== 3)
3657 i
.tm
.base_opcode
= INT3_OPCODE
;
3661 if ((i
.tm
.opcode_modifier
.jump
3662 || i
.tm
.opcode_modifier
.jumpbyte
3663 || i
.tm
.opcode_modifier
.jumpdword
)
3664 && i
.op
[0].disps
->X_op
== O_constant
)
3666 /* Convert "jmp constant" (and "call constant") to a jump (call) to
3667 the absolute address given by the constant. Since ix86 jumps and
3668 calls are pc relative, we need to generate a reloc. */
3669 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
3670 i
.op
[0].disps
->X_op
= O_symbol
;
3673 if (i
.tm
.opcode_modifier
.rex64
)
3676 /* For 8 bit registers we need an empty rex prefix. Also if the
3677 instruction already has a prefix, we need to convert old
3678 registers to new ones. */
3680 if ((i
.types
[0].bitfield
.reg8
3681 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
3682 || (i
.types
[1].bitfield
.reg8
3683 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
3684 || ((i
.types
[0].bitfield
.reg8
3685 || i
.types
[1].bitfield
.reg8
)
3690 i
.rex
|= REX_OPCODE
;
3691 for (x
= 0; x
< 2; x
++)
3693 /* Look for 8 bit operand that uses old registers. */
3694 if (i
.types
[x
].bitfield
.reg8
3695 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
3697 /* In case it is "hi" register, give up. */
3698 if (i
.op
[x
].regs
->reg_num
> 3)
3699 as_bad (_("can't encode register '%s%s' in an "
3700 "instruction requiring REX prefix."),
3701 register_prefix
, i
.op
[x
].regs
->reg_name
);
3703 /* Otherwise it is equivalent to the extended register.
3704 Since the encoding doesn't change this is merely
3705 cosmetic cleanup for debug output. */
3707 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
3713 add_prefix (REX_OPCODE
| i
.rex
);
3715 /* We are ready to output the insn. */
3720 parse_insn (char *line
, char *mnemonic
)
3723 char *token_start
= l
;
3726 const insn_template
*t
;
3732 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
3737 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
3739 as_bad (_("no such instruction: `%s'"), token_start
);
3744 if (!is_space_char (*l
)
3745 && *l
!= END_OF_INSN
3747 || (*l
!= PREFIX_SEPARATOR
3750 as_bad (_("invalid character %s in mnemonic"),
3751 output_invalid (*l
));
3754 if (token_start
== l
)
3756 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
3757 as_bad (_("expecting prefix; got nothing"));
3759 as_bad (_("expecting mnemonic; got nothing"));
3763 /* Look up instruction (or prefix) via hash table. */
3764 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
3766 if (*l
!= END_OF_INSN
3767 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
3768 && current_templates
3769 && current_templates
->start
->opcode_modifier
.isprefix
)
3771 if (!cpu_flags_check_cpu64 (current_templates
->start
->cpu_flags
))
3773 as_bad ((flag_code
!= CODE_64BIT
3774 ? _("`%s' is only supported in 64-bit mode")
3775 : _("`%s' is not supported in 64-bit mode")),
3776 current_templates
->start
->name
);
3779 /* If we are in 16-bit mode, do not allow addr16 or data16.
3780 Similarly, in 32-bit mode, do not allow addr32 or data32. */
3781 if ((current_templates
->start
->opcode_modifier
.size16
3782 || current_templates
->start
->opcode_modifier
.size32
)
3783 && flag_code
!= CODE_64BIT
3784 && (current_templates
->start
->opcode_modifier
.size32
3785 ^ (flag_code
== CODE_16BIT
)))
3787 as_bad (_("redundant %s prefix"),
3788 current_templates
->start
->name
);
3791 /* Add prefix, checking for repeated prefixes. */
3792 switch (add_prefix (current_templates
->start
->base_opcode
))
3797 if (current_templates
->start
->cpu_flags
.bitfield
.cpuhle
)
3798 i
.hle_prefix
= current_templates
->start
->name
;
3799 else if (current_templates
->start
->cpu_flags
.bitfield
.cpumpx
)
3800 i
.bnd_prefix
= current_templates
->start
->name
;
3802 i
.rep_prefix
= current_templates
->start
->name
;
3807 /* Skip past PREFIX_SEPARATOR and reset token_start. */
3814 if (!current_templates
)
3816 /* Check if we should swap operand or force 32bit displacement in
3818 if (mnem_p
- 2 == dot_p
&& dot_p
[1] == 's')
3820 else if (mnem_p
- 3 == dot_p
3823 i
.disp_encoding
= disp_encoding_8bit
;
3824 else if (mnem_p
- 4 == dot_p
3828 i
.disp_encoding
= disp_encoding_32bit
;
3833 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
3836 if (!current_templates
)
3839 /* See if we can get a match by trimming off a suffix. */
3842 case WORD_MNEM_SUFFIX
:
3843 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
3844 i
.suffix
= SHORT_MNEM_SUFFIX
;
3846 case BYTE_MNEM_SUFFIX
:
3847 case QWORD_MNEM_SUFFIX
:
3848 i
.suffix
= mnem_p
[-1];
3850 current_templates
= (const templates
*) hash_find (op_hash
,
3853 case SHORT_MNEM_SUFFIX
:
3854 case LONG_MNEM_SUFFIX
:
3857 i
.suffix
= mnem_p
[-1];
3859 current_templates
= (const templates
*) hash_find (op_hash
,
3868 if (intel_float_operand (mnemonic
) == 1)
3869 i
.suffix
= SHORT_MNEM_SUFFIX
;
3871 i
.suffix
= LONG_MNEM_SUFFIX
;
3873 current_templates
= (const templates
*) hash_find (op_hash
,
3878 if (!current_templates
)
3880 as_bad (_("no such instruction: `%s'"), token_start
);
3885 if (current_templates
->start
->opcode_modifier
.jump
3886 || current_templates
->start
->opcode_modifier
.jumpbyte
)
3888 /* Check for a branch hint. We allow ",pt" and ",pn" for
3889 predict taken and predict not taken respectively.
3890 I'm not sure that branch hints actually do anything on loop
3891 and jcxz insns (JumpByte) for current Pentium4 chips. They
3892 may work in the future and it doesn't hurt to accept them
3894 if (l
[0] == ',' && l
[1] == 'p')
3898 if (!add_prefix (DS_PREFIX_OPCODE
))
3902 else if (l
[2] == 'n')
3904 if (!add_prefix (CS_PREFIX_OPCODE
))
3910 /* Any other comma loses. */
3913 as_bad (_("invalid character %s in mnemonic"),
3914 output_invalid (*l
));
3918 /* Check if instruction is supported on specified architecture. */
3920 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
3922 supported
|= cpu_flags_match (t
);
3923 if (supported
== CPU_FLAGS_PERFECT_MATCH
)
3927 if (!(supported
& CPU_FLAGS_64BIT_MATCH
))
3929 as_bad (flag_code
== CODE_64BIT
3930 ? _("`%s' is not supported in 64-bit mode")
3931 : _("`%s' is only supported in 64-bit mode"),
3932 current_templates
->start
->name
);
3935 if (supported
!= CPU_FLAGS_PERFECT_MATCH
)
3937 as_bad (_("`%s' is not supported on `%s%s'"),
3938 current_templates
->start
->name
,
3939 cpu_arch_name
? cpu_arch_name
: default_arch
,
3940 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
3945 if (!cpu_arch_flags
.bitfield
.cpui386
3946 && (flag_code
!= CODE_16BIT
))
3948 as_warn (_("use .code16 to ensure correct addressing mode"));
3955 parse_operands (char *l
, const char *mnemonic
)
3959 /* 1 if operand is pending after ','. */
3960 unsigned int expecting_operand
= 0;
3962 /* Non-zero if operand parens not balanced. */
3963 unsigned int paren_not_balanced
;
3965 while (*l
!= END_OF_INSN
)
3967 /* Skip optional white space before operand. */
3968 if (is_space_char (*l
))
3970 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
)
3972 as_bad (_("invalid character %s before operand %d"),
3973 output_invalid (*l
),
3977 token_start
= l
; /* after white space */
3978 paren_not_balanced
= 0;
3979 while (paren_not_balanced
|| *l
!= ',')
3981 if (*l
== END_OF_INSN
)
3983 if (paren_not_balanced
)
3986 as_bad (_("unbalanced parenthesis in operand %d."),
3989 as_bad (_("unbalanced brackets in operand %d."),
3994 break; /* we are done */
3996 else if (!is_operand_char (*l
) && !is_space_char (*l
))
3998 as_bad (_("invalid character %s in operand %d"),
3999 output_invalid (*l
),
4006 ++paren_not_balanced
;
4008 --paren_not_balanced
;
4013 ++paren_not_balanced
;
4015 --paren_not_balanced
;
4019 if (l
!= token_start
)
4020 { /* Yes, we've read in another operand. */
4021 unsigned int operand_ok
;
4022 this_operand
= i
.operands
++;
4023 i
.types
[this_operand
].bitfield
.unspecified
= 1;
4024 if (i
.operands
> MAX_OPERANDS
)
4026 as_bad (_("spurious operands; (%d operands/instruction max)"),
4030 /* Now parse operand adding info to 'i' as we go along. */
4031 END_STRING_AND_SAVE (l
);
4035 i386_intel_operand (token_start
,
4036 intel_float_operand (mnemonic
));
4038 operand_ok
= i386_att_operand (token_start
);
4040 RESTORE_END_STRING (l
);
4046 if (expecting_operand
)
4048 expecting_operand_after_comma
:
4049 as_bad (_("expecting operand after ','; got nothing"));
4054 as_bad (_("expecting operand before ','; got nothing"));
4059 /* Now *l must be either ',' or END_OF_INSN. */
4062 if (*++l
== END_OF_INSN
)
4064 /* Just skip it, if it's \n complain. */
4065 goto expecting_operand_after_comma
;
4067 expecting_operand
= 1;
4074 swap_2_operands (int xchg1
, int xchg2
)
4076 union i386_op temp_op
;
4077 i386_operand_type temp_type
;
4078 enum bfd_reloc_code_real temp_reloc
;
4080 temp_type
= i
.types
[xchg2
];
4081 i
.types
[xchg2
] = i
.types
[xchg1
];
4082 i
.types
[xchg1
] = temp_type
;
4083 temp_op
= i
.op
[xchg2
];
4084 i
.op
[xchg2
] = i
.op
[xchg1
];
4085 i
.op
[xchg1
] = temp_op
;
4086 temp_reloc
= i
.reloc
[xchg2
];
4087 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
4088 i
.reloc
[xchg1
] = temp_reloc
;
4092 if (i
.mask
->operand
== xchg1
)
4093 i
.mask
->operand
= xchg2
;
4094 else if (i
.mask
->operand
== xchg2
)
4095 i
.mask
->operand
= xchg1
;
4099 if (i
.broadcast
->operand
== xchg1
)
4100 i
.broadcast
->operand
= xchg2
;
4101 else if (i
.broadcast
->operand
== xchg2
)
4102 i
.broadcast
->operand
= xchg1
;
4106 if (i
.rounding
->operand
== xchg1
)
4107 i
.rounding
->operand
= xchg2
;
4108 else if (i
.rounding
->operand
== xchg2
)
4109 i
.rounding
->operand
= xchg1
;
4114 swap_operands (void)
4120 swap_2_operands (1, i
.operands
- 2);
4123 swap_2_operands (0, i
.operands
- 1);
4129 if (i
.mem_operands
== 2)
4131 const seg_entry
*temp_seg
;
4132 temp_seg
= i
.seg
[0];
4133 i
.seg
[0] = i
.seg
[1];
4134 i
.seg
[1] = temp_seg
;
4138 /* Try to ensure constant immediates are represented in the smallest
4143 char guess_suffix
= 0;
4147 guess_suffix
= i
.suffix
;
4148 else if (i
.reg_operands
)
4150 /* Figure out a suffix from the last register operand specified.
4151 We can't do this properly yet, ie. excluding InOutPortReg,
4152 but the following works for instructions with immediates.
4153 In any case, we can't set i.suffix yet. */
4154 for (op
= i
.operands
; --op
>= 0;)
4155 if (i
.types
[op
].bitfield
.reg8
)
4157 guess_suffix
= BYTE_MNEM_SUFFIX
;
4160 else if (i
.types
[op
].bitfield
.reg16
)
4162 guess_suffix
= WORD_MNEM_SUFFIX
;
4165 else if (i
.types
[op
].bitfield
.reg32
)
4167 guess_suffix
= LONG_MNEM_SUFFIX
;
4170 else if (i
.types
[op
].bitfield
.reg64
)
4172 guess_suffix
= QWORD_MNEM_SUFFIX
;
4176 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
4177 guess_suffix
= WORD_MNEM_SUFFIX
;
4179 for (op
= i
.operands
; --op
>= 0;)
4180 if (operand_type_check (i
.types
[op
], imm
))
4182 switch (i
.op
[op
].imms
->X_op
)
4185 /* If a suffix is given, this operand may be shortened. */
4186 switch (guess_suffix
)
4188 case LONG_MNEM_SUFFIX
:
4189 i
.types
[op
].bitfield
.imm32
= 1;
4190 i
.types
[op
].bitfield
.imm64
= 1;
4192 case WORD_MNEM_SUFFIX
:
4193 i
.types
[op
].bitfield
.imm16
= 1;
4194 i
.types
[op
].bitfield
.imm32
= 1;
4195 i
.types
[op
].bitfield
.imm32s
= 1;
4196 i
.types
[op
].bitfield
.imm64
= 1;
4198 case BYTE_MNEM_SUFFIX
:
4199 i
.types
[op
].bitfield
.imm8
= 1;
4200 i
.types
[op
].bitfield
.imm8s
= 1;
4201 i
.types
[op
].bitfield
.imm16
= 1;
4202 i
.types
[op
].bitfield
.imm32
= 1;
4203 i
.types
[op
].bitfield
.imm32s
= 1;
4204 i
.types
[op
].bitfield
.imm64
= 1;
4208 /* If this operand is at most 16 bits, convert it
4209 to a signed 16 bit number before trying to see
4210 whether it will fit in an even smaller size.
4211 This allows a 16-bit operand such as $0xffe0 to
4212 be recognised as within Imm8S range. */
4213 if ((i
.types
[op
].bitfield
.imm16
)
4214 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
4216 i
.op
[op
].imms
->X_add_number
=
4217 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
4219 if ((i
.types
[op
].bitfield
.imm32
)
4220 && ((i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1))
4223 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
4224 ^ ((offsetT
) 1 << 31))
4225 - ((offsetT
) 1 << 31));
4228 = operand_type_or (i
.types
[op
],
4229 smallest_imm_type (i
.op
[op
].imms
->X_add_number
));
4231 /* We must avoid matching of Imm32 templates when 64bit
4232 only immediate is available. */
4233 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
4234 i
.types
[op
].bitfield
.imm32
= 0;
4241 /* Symbols and expressions. */
4243 /* Convert symbolic operand to proper sizes for matching, but don't
4244 prevent matching a set of insns that only supports sizes other
4245 than those matching the insn suffix. */
4247 i386_operand_type mask
, allowed
;
4248 const insn_template
*t
;
4250 operand_type_set (&mask
, 0);
4251 operand_type_set (&allowed
, 0);
4253 for (t
= current_templates
->start
;
4254 t
< current_templates
->end
;
4256 allowed
= operand_type_or (allowed
,
4257 t
->operand_types
[op
]);
4258 switch (guess_suffix
)
4260 case QWORD_MNEM_SUFFIX
:
4261 mask
.bitfield
.imm64
= 1;
4262 mask
.bitfield
.imm32s
= 1;
4264 case LONG_MNEM_SUFFIX
:
4265 mask
.bitfield
.imm32
= 1;
4267 case WORD_MNEM_SUFFIX
:
4268 mask
.bitfield
.imm16
= 1;
4270 case BYTE_MNEM_SUFFIX
:
4271 mask
.bitfield
.imm8
= 1;
4276 allowed
= operand_type_and (mask
, allowed
);
4277 if (!operand_type_all_zero (&allowed
))
4278 i
.types
[op
] = operand_type_and (i
.types
[op
], mask
);
4285 /* Try to use the smallest displacement type too. */
4287 optimize_disp (void)
4291 for (op
= i
.operands
; --op
>= 0;)
4292 if (operand_type_check (i
.types
[op
], disp
))
4294 if (i
.op
[op
].disps
->X_op
== O_constant
)
4296 offsetT op_disp
= i
.op
[op
].disps
->X_add_number
;
4298 if (i
.types
[op
].bitfield
.disp16
4299 && (op_disp
& ~(offsetT
) 0xffff) == 0)
4301 /* If this operand is at most 16 bits, convert
4302 to a signed 16 bit number and don't use 64bit
4304 op_disp
= (((op_disp
& 0xffff) ^ 0x8000) - 0x8000);
4305 i
.types
[op
].bitfield
.disp64
= 0;
4307 if (i
.types
[op
].bitfield
.disp32
4308 && (op_disp
& ~(((offsetT
) 2 << 31) - 1)) == 0)
4310 /* If this operand is at most 32 bits, convert
4311 to a signed 32 bit number and don't use 64bit
4313 op_disp
&= (((offsetT
) 2 << 31) - 1);
4314 op_disp
= (op_disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
4315 i
.types
[op
].bitfield
.disp64
= 0;
4317 if (!op_disp
&& i
.types
[op
].bitfield
.baseindex
)
4319 i
.types
[op
].bitfield
.disp8
= 0;
4320 i
.types
[op
].bitfield
.disp16
= 0;
4321 i
.types
[op
].bitfield
.disp32
= 0;
4322 i
.types
[op
].bitfield
.disp32s
= 0;
4323 i
.types
[op
].bitfield
.disp64
= 0;
4327 else if (flag_code
== CODE_64BIT
)
4329 if (fits_in_signed_long (op_disp
))
4331 i
.types
[op
].bitfield
.disp64
= 0;
4332 i
.types
[op
].bitfield
.disp32s
= 1;
4334 if (i
.prefix
[ADDR_PREFIX
]
4335 && fits_in_unsigned_long (op_disp
))
4336 i
.types
[op
].bitfield
.disp32
= 1;
4338 if ((i
.types
[op
].bitfield
.disp32
4339 || i
.types
[op
].bitfield
.disp32s
4340 || i
.types
[op
].bitfield
.disp16
)
4341 && fits_in_signed_byte (op_disp
))
4342 i
.types
[op
].bitfield
.disp8
= 1;
4344 else if (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
4345 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
)
4347 fix_new_exp (frag_now
, frag_more (0) - frag_now
->fr_literal
, 0,
4348 i
.op
[op
].disps
, 0, i
.reloc
[op
]);
4349 i
.types
[op
].bitfield
.disp8
= 0;
4350 i
.types
[op
].bitfield
.disp16
= 0;
4351 i
.types
[op
].bitfield
.disp32
= 0;
4352 i
.types
[op
].bitfield
.disp32s
= 0;
4353 i
.types
[op
].bitfield
.disp64
= 0;
4356 /* We only support 64bit displacement on constants. */
4357 i
.types
[op
].bitfield
.disp64
= 0;
4361 /* Check if operands are valid for the instruction. */
4364 check_VecOperands (const insn_template
*t
)
4368 /* Without VSIB byte, we can't have a vector register for index. */
4369 if (!t
->opcode_modifier
.vecsib
4371 && (i
.index_reg
->reg_type
.bitfield
.regxmm
4372 || i
.index_reg
->reg_type
.bitfield
.regymm
4373 || i
.index_reg
->reg_type
.bitfield
.regzmm
))
4375 i
.error
= unsupported_vector_index_register
;
4379 /* Check if default mask is allowed. */
4380 if (t
->opcode_modifier
.nodefmask
4381 && (!i
.mask
|| i
.mask
->mask
->reg_num
== 0))
4383 i
.error
= no_default_mask
;
4387 /* For VSIB byte, we need a vector register for index, and all vector
4388 registers must be distinct. */
4389 if (t
->opcode_modifier
.vecsib
)
4392 || !((t
->opcode_modifier
.vecsib
== VecSIB128
4393 && i
.index_reg
->reg_type
.bitfield
.regxmm
)
4394 || (t
->opcode_modifier
.vecsib
== VecSIB256
4395 && i
.index_reg
->reg_type
.bitfield
.regymm
)
4396 || (t
->opcode_modifier
.vecsib
== VecSIB512
4397 && i
.index_reg
->reg_type
.bitfield
.regzmm
)))
4399 i
.error
= invalid_vsib_address
;
4403 gas_assert (i
.reg_operands
== 2 || i
.mask
);
4404 if (i
.reg_operands
== 2 && !i
.mask
)
4406 gas_assert (i
.types
[0].bitfield
.regxmm
4407 || i
.types
[0].bitfield
.regymm
);
4408 gas_assert (i
.types
[2].bitfield
.regxmm
4409 || i
.types
[2].bitfield
.regymm
);
4410 if (operand_check
== check_none
)
4412 if (register_number (i
.op
[0].regs
)
4413 != register_number (i
.index_reg
)
4414 && register_number (i
.op
[2].regs
)
4415 != register_number (i
.index_reg
)
4416 && register_number (i
.op
[0].regs
)
4417 != register_number (i
.op
[2].regs
))
4419 if (operand_check
== check_error
)
4421 i
.error
= invalid_vector_register_set
;
4424 as_warn (_("mask, index, and destination registers should be distinct"));
4426 else if (i
.reg_operands
== 1 && i
.mask
)
4428 if ((i
.types
[1].bitfield
.regymm
4429 || i
.types
[1].bitfield
.regzmm
)
4430 && (register_number (i
.op
[1].regs
)
4431 == register_number (i
.index_reg
)))
4433 if (operand_check
== check_error
)
4435 i
.error
= invalid_vector_register_set
;
4438 if (operand_check
!= check_none
)
4439 as_warn (_("index and destination registers should be distinct"));
4444 /* Check if broadcast is supported by the instruction and is applied
4445 to the memory operand. */
4448 int broadcasted_opnd_size
;
4450 /* Check if specified broadcast is supported in this instruction,
4451 and it's applied to memory operand of DWORD or QWORD type,
4452 depending on VecESize. */
4453 if (i
.broadcast
->type
!= t
->opcode_modifier
.broadcast
4454 || !i
.types
[i
.broadcast
->operand
].bitfield
.mem
4455 || (t
->opcode_modifier
.vecesize
== 0
4456 && !i
.types
[i
.broadcast
->operand
].bitfield
.dword
4457 && !i
.types
[i
.broadcast
->operand
].bitfield
.unspecified
)
4458 || (t
->opcode_modifier
.vecesize
== 1
4459 && !i
.types
[i
.broadcast
->operand
].bitfield
.qword
4460 && !i
.types
[i
.broadcast
->operand
].bitfield
.unspecified
))
4463 broadcasted_opnd_size
= t
->opcode_modifier
.vecesize
? 64 : 32;
4464 if (i
.broadcast
->type
== BROADCAST_1TO16
)
4465 broadcasted_opnd_size
<<= 4; /* Broadcast 1to16. */
4466 else if (i
.broadcast
->type
== BROADCAST_1TO8
)
4467 broadcasted_opnd_size
<<= 3; /* Broadcast 1to8. */
4468 else if (i
.broadcast
->type
== BROADCAST_1TO4
)
4469 broadcasted_opnd_size
<<= 2; /* Broadcast 1to4. */
4470 else if (i
.broadcast
->type
== BROADCAST_1TO2
)
4471 broadcasted_opnd_size
<<= 1; /* Broadcast 1to2. */
4475 if ((broadcasted_opnd_size
== 256
4476 && !t
->operand_types
[i
.broadcast
->operand
].bitfield
.ymmword
)
4477 || (broadcasted_opnd_size
== 512
4478 && !t
->operand_types
[i
.broadcast
->operand
].bitfield
.zmmword
))
4481 i
.error
= unsupported_broadcast
;
4485 /* If broadcast is supported in this instruction, we need to check if
4486 operand of one-element size isn't specified without broadcast. */
4487 else if (t
->opcode_modifier
.broadcast
&& i
.mem_operands
)
4489 /* Find memory operand. */
4490 for (op
= 0; op
< i
.operands
; op
++)
4491 if (operand_type_check (i
.types
[op
], anymem
))
4493 gas_assert (op
< i
.operands
);
4494 /* Check size of the memory operand. */
4495 if ((t
->opcode_modifier
.vecesize
== 0
4496 && i
.types
[op
].bitfield
.dword
)
4497 || (t
->opcode_modifier
.vecesize
== 1
4498 && i
.types
[op
].bitfield
.qword
))
4500 i
.error
= broadcast_needed
;
4505 /* Check if requested masking is supported. */
4507 && (!t
->opcode_modifier
.masking
4509 && t
->opcode_modifier
.masking
== MERGING_MASKING
)))
4511 i
.error
= unsupported_masking
;
4515 /* Check if masking is applied to dest operand. */
4516 if (i
.mask
&& (i
.mask
->operand
!= (int) (i
.operands
- 1)))
4518 i
.error
= mask_not_on_destination
;
4525 if ((i
.rounding
->type
!= saeonly
4526 && !t
->opcode_modifier
.staticrounding
)
4527 || (i
.rounding
->type
== saeonly
4528 && (t
->opcode_modifier
.staticrounding
4529 || !t
->opcode_modifier
.sae
)))
4531 i
.error
= unsupported_rc_sae
;
4534 /* If the instruction has several immediate operands and one of
4535 them is rounding, the rounding operand should be the last
4536 immediate operand. */
4537 if (i
.imm_operands
> 1
4538 && i
.rounding
->operand
!= (int) (i
.imm_operands
- 1))
4540 i
.error
= rc_sae_operand_not_last_imm
;
4545 /* Check vector Disp8 operand. */
4546 if (t
->opcode_modifier
.disp8memshift
)
4549 i
.memshift
= t
->opcode_modifier
.vecesize
? 3 : 2;
4551 i
.memshift
= t
->opcode_modifier
.disp8memshift
;
4553 for (op
= 0; op
< i
.operands
; op
++)
4554 if (operand_type_check (i
.types
[op
], disp
)
4555 && i
.op
[op
].disps
->X_op
== O_constant
)
4557 offsetT value
= i
.op
[op
].disps
->X_add_number
;
4558 int vec_disp8_ok
= fits_in_vec_disp8 (value
);
4559 if (t
->operand_types
[op
].bitfield
.vec_disp8
)
4562 i
.types
[op
].bitfield
.vec_disp8
= 1;
4565 /* Vector insn can only have Vec_Disp8/Disp32 in
4566 32/64bit modes, and Vec_Disp8/Disp16 in 16bit
4568 i
.types
[op
].bitfield
.disp8
= 0;
4569 if (flag_code
!= CODE_16BIT
)
4570 i
.types
[op
].bitfield
.disp16
= 0;
4573 else if (flag_code
!= CODE_16BIT
)
4575 /* One form of this instruction supports vector Disp8.
4576 Try vector Disp8 if we need to use Disp32. */
4577 if (vec_disp8_ok
&& !fits_in_signed_byte (value
))
4579 i
.error
= try_vector_disp8
;
4591 /* Check if operands are valid for the instruction. Update VEX
4595 VEX_check_operands (const insn_template
*t
)
4597 /* VREX is only valid with EVEX prefix. */
4598 if (i
.need_vrex
&& !t
->opcode_modifier
.evex
)
4600 i
.error
= invalid_register_operand
;
4604 if (!t
->opcode_modifier
.vex
)
4607 /* Only check VEX_Imm4, which must be the first operand. */
4608 if (t
->operand_types
[0].bitfield
.vec_imm4
)
4610 if (i
.op
[0].imms
->X_op
!= O_constant
4611 || !fits_in_imm4 (i
.op
[0].imms
->X_add_number
))
4617 /* Turn off Imm8 so that update_imm won't complain. */
4618 i
.types
[0] = vec_imm4
;
4624 static const insn_template
*
4625 match_template (void)
4627 /* Points to template once we've found it. */
4628 const insn_template
*t
;
4629 i386_operand_type overlap0
, overlap1
, overlap2
, overlap3
;
4630 i386_operand_type overlap4
;
4631 unsigned int found_reverse_match
;
4632 i386_opcode_modifier suffix_check
;
4633 i386_operand_type operand_types
[MAX_OPERANDS
];
4634 int addr_prefix_disp
;
4636 unsigned int found_cpu_match
;
4637 unsigned int check_register
;
4638 enum i386_error specific_error
= 0;
4640 #if MAX_OPERANDS != 5
4641 # error "MAX_OPERANDS must be 5."
4644 found_reverse_match
= 0;
4645 addr_prefix_disp
= -1;
4647 memset (&suffix_check
, 0, sizeof (suffix_check
));
4648 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
4649 suffix_check
.no_bsuf
= 1;
4650 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
4651 suffix_check
.no_wsuf
= 1;
4652 else if (i
.suffix
== SHORT_MNEM_SUFFIX
)
4653 suffix_check
.no_ssuf
= 1;
4654 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
4655 suffix_check
.no_lsuf
= 1;
4656 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
4657 suffix_check
.no_qsuf
= 1;
4658 else if (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
)
4659 suffix_check
.no_ldsuf
= 1;
4661 /* Must have right number of operands. */
4662 i
.error
= number_of_operands_mismatch
;
4664 for (t
= current_templates
->start
; t
< current_templates
->end
; t
++)
4666 addr_prefix_disp
= -1;
4668 if (i
.operands
!= t
->operands
)
4671 /* Check processor support. */
4672 i
.error
= unsupported
;
4673 found_cpu_match
= (cpu_flags_match (t
)
4674 == CPU_FLAGS_PERFECT_MATCH
);
4675 if (!found_cpu_match
)
4678 /* Check old gcc support. */
4679 i
.error
= old_gcc_only
;
4680 if (!old_gcc
&& t
->opcode_modifier
.oldgcc
)
4683 /* Check AT&T mnemonic. */
4684 i
.error
= unsupported_with_intel_mnemonic
;
4685 if (intel_mnemonic
&& t
->opcode_modifier
.attmnemonic
)
4688 /* Check AT&T/Intel syntax. */
4689 i
.error
= unsupported_syntax
;
4690 if ((intel_syntax
&& t
->opcode_modifier
.attsyntax
)
4691 || (!intel_syntax
&& t
->opcode_modifier
.intelsyntax
))
4694 /* Check the suffix, except for some instructions in intel mode. */
4695 i
.error
= invalid_instruction_suffix
;
4696 if ((!intel_syntax
|| !t
->opcode_modifier
.ignoresize
)
4697 && ((t
->opcode_modifier
.no_bsuf
&& suffix_check
.no_bsuf
)
4698 || (t
->opcode_modifier
.no_wsuf
&& suffix_check
.no_wsuf
)
4699 || (t
->opcode_modifier
.no_lsuf
&& suffix_check
.no_lsuf
)
4700 || (t
->opcode_modifier
.no_ssuf
&& suffix_check
.no_ssuf
)
4701 || (t
->opcode_modifier
.no_qsuf
&& suffix_check
.no_qsuf
)
4702 || (t
->opcode_modifier
.no_ldsuf
&& suffix_check
.no_ldsuf
)))
4705 if (!operand_size_match (t
))
4708 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4709 operand_types
[j
] = t
->operand_types
[j
];
4711 /* In general, don't allow 64-bit operands in 32-bit mode. */
4712 if (i
.suffix
== QWORD_MNEM_SUFFIX
4713 && flag_code
!= CODE_64BIT
4715 ? (!t
->opcode_modifier
.ignoresize
4716 && !intel_float_operand (t
->name
))
4717 : intel_float_operand (t
->name
) != 2)
4718 && ((!operand_types
[0].bitfield
.regmmx
4719 && !operand_types
[0].bitfield
.regxmm
4720 && !operand_types
[0].bitfield
.regymm
4721 && !operand_types
[0].bitfield
.regzmm
)
4722 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
4723 && operand_types
[t
->operands
> 1].bitfield
.regxmm
4724 && operand_types
[t
->operands
> 1].bitfield
.regymm
4725 && operand_types
[t
->operands
> 1].bitfield
.regzmm
))
4726 && (t
->base_opcode
!= 0x0fc7
4727 || t
->extension_opcode
!= 1 /* cmpxchg8b */))
4730 /* In general, don't allow 32-bit operands on pre-386. */
4731 else if (i
.suffix
== LONG_MNEM_SUFFIX
4732 && !cpu_arch_flags
.bitfield
.cpui386
4734 ? (!t
->opcode_modifier
.ignoresize
4735 && !intel_float_operand (t
->name
))
4736 : intel_float_operand (t
->name
) != 2)
4737 && ((!operand_types
[0].bitfield
.regmmx
4738 && !operand_types
[0].bitfield
.regxmm
)
4739 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
4740 && operand_types
[t
->operands
> 1].bitfield
.regxmm
)))
4743 /* Do not verify operands when there are none. */
4747 /* We've found a match; break out of loop. */
4751 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
4752 into Disp32/Disp16/Disp32 operand. */
4753 if (i
.prefix
[ADDR_PREFIX
] != 0)
4755 /* There should be only one Disp operand. */
4759 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4761 if (operand_types
[j
].bitfield
.disp16
)
4763 addr_prefix_disp
= j
;
4764 operand_types
[j
].bitfield
.disp32
= 1;
4765 operand_types
[j
].bitfield
.disp16
= 0;
4771 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4773 if (operand_types
[j
].bitfield
.disp32
)
4775 addr_prefix_disp
= j
;
4776 operand_types
[j
].bitfield
.disp32
= 0;
4777 operand_types
[j
].bitfield
.disp16
= 1;
4783 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4785 if (operand_types
[j
].bitfield
.disp64
)
4787 addr_prefix_disp
= j
;
4788 operand_types
[j
].bitfield
.disp64
= 0;
4789 operand_types
[j
].bitfield
.disp32
= 1;
4797 /* We check register size if needed. */
4798 check_register
= t
->opcode_modifier
.checkregsize
;
4799 overlap0
= operand_type_and (i
.types
[0], operand_types
[0]);
4800 switch (t
->operands
)
4803 if (!operand_type_match (overlap0
, i
.types
[0]))
4807 /* xchg %eax, %eax is a special case. It is an aliase for nop
4808 only in 32bit mode and we can use opcode 0x90. In 64bit
4809 mode, we can't use 0x90 for xchg %eax, %eax since it should
4810 zero-extend %eax to %rax. */
4811 if (flag_code
== CODE_64BIT
4812 && t
->base_opcode
== 0x90
4813 && operand_type_equal (&i
.types
[0], &acc32
)
4814 && operand_type_equal (&i
.types
[1], &acc32
))
4818 /* If we swap operand in encoding, we either match
4819 the next one or reverse direction of operands. */
4820 if (t
->opcode_modifier
.s
)
4822 else if (t
->opcode_modifier
.d
)
4827 /* If we swap operand in encoding, we match the next one. */
4828 if (i
.swap_operand
&& t
->opcode_modifier
.s
)
4832 overlap1
= operand_type_and (i
.types
[1], operand_types
[1]);
4833 if (!operand_type_match (overlap0
, i
.types
[0])
4834 || !operand_type_match (overlap1
, i
.types
[1])
4836 && !operand_type_register_match (overlap0
, i
.types
[0],
4838 overlap1
, i
.types
[1],
4841 /* Check if other direction is valid ... */
4842 if (!t
->opcode_modifier
.d
&& !t
->opcode_modifier
.floatd
)
4846 /* Try reversing direction of operands. */
4847 overlap0
= operand_type_and (i
.types
[0], operand_types
[1]);
4848 overlap1
= operand_type_and (i
.types
[1], operand_types
[0]);
4849 if (!operand_type_match (overlap0
, i
.types
[0])
4850 || !operand_type_match (overlap1
, i
.types
[1])
4852 && !operand_type_register_match (overlap0
,
4859 /* Does not match either direction. */
4862 /* found_reverse_match holds which of D or FloatDR
4864 if (t
->opcode_modifier
.d
)
4865 found_reverse_match
= Opcode_D
;
4866 else if (t
->opcode_modifier
.floatd
)
4867 found_reverse_match
= Opcode_FloatD
;
4869 found_reverse_match
= 0;
4870 if (t
->opcode_modifier
.floatr
)
4871 found_reverse_match
|= Opcode_FloatR
;
4875 /* Found a forward 2 operand match here. */
4876 switch (t
->operands
)
4879 overlap4
= operand_type_and (i
.types
[4],
4882 overlap3
= operand_type_and (i
.types
[3],
4885 overlap2
= operand_type_and (i
.types
[2],
4890 switch (t
->operands
)
4893 if (!operand_type_match (overlap4
, i
.types
[4])
4894 || !operand_type_register_match (overlap3
,
4902 if (!operand_type_match (overlap3
, i
.types
[3])
4904 && !operand_type_register_match (overlap2
,
4912 /* Here we make use of the fact that there are no
4913 reverse match 3 operand instructions, and all 3
4914 operand instructions only need to be checked for
4915 register consistency between operands 2 and 3. */
4916 if (!operand_type_match (overlap2
, i
.types
[2])
4918 && !operand_type_register_match (overlap1
,
4928 /* Found either forward/reverse 2, 3 or 4 operand match here:
4929 slip through to break. */
4931 if (!found_cpu_match
)
4933 found_reverse_match
= 0;
4937 /* Check if vector and VEX operands are valid. */
4938 if (check_VecOperands (t
) || VEX_check_operands (t
))
4940 specific_error
= i
.error
;
4944 /* We've found a match; break out of loop. */
4948 if (t
== current_templates
->end
)
4950 /* We found no match. */
4951 const char *err_msg
;
4952 switch (specific_error
? specific_error
: i
.error
)
4956 case operand_size_mismatch
:
4957 err_msg
= _("operand size mismatch");
4959 case operand_type_mismatch
:
4960 err_msg
= _("operand type mismatch");
4962 case register_type_mismatch
:
4963 err_msg
= _("register type mismatch");
4965 case number_of_operands_mismatch
:
4966 err_msg
= _("number of operands mismatch");
4968 case invalid_instruction_suffix
:
4969 err_msg
= _("invalid instruction suffix");
4972 err_msg
= _("constant doesn't fit in 4 bits");
4975 err_msg
= _("only supported with old gcc");
4977 case unsupported_with_intel_mnemonic
:
4978 err_msg
= _("unsupported with Intel mnemonic");
4980 case unsupported_syntax
:
4981 err_msg
= _("unsupported syntax");
4984 as_bad (_("unsupported instruction `%s'"),
4985 current_templates
->start
->name
);
4987 case invalid_vsib_address
:
4988 err_msg
= _("invalid VSIB address");
4990 case invalid_vector_register_set
:
4991 err_msg
= _("mask, index, and destination registers must be distinct");
4993 case unsupported_vector_index_register
:
4994 err_msg
= _("unsupported vector index register");
4996 case unsupported_broadcast
:
4997 err_msg
= _("unsupported broadcast");
4999 case broadcast_not_on_src_operand
:
5000 err_msg
= _("broadcast not on source memory operand");
5002 case broadcast_needed
:
5003 err_msg
= _("broadcast is needed for operand of such type");
5005 case unsupported_masking
:
5006 err_msg
= _("unsupported masking");
5008 case mask_not_on_destination
:
5009 err_msg
= _("mask not on destination operand");
5011 case no_default_mask
:
5012 err_msg
= _("default mask isn't allowed");
5014 case unsupported_rc_sae
:
5015 err_msg
= _("unsupported static rounding/sae");
5017 case rc_sae_operand_not_last_imm
:
5019 err_msg
= _("RC/SAE operand must precede immediate operands");
5021 err_msg
= _("RC/SAE operand must follow immediate operands");
5023 case invalid_register_operand
:
5024 err_msg
= _("invalid register operand");
5027 as_bad (_("%s for `%s'"), err_msg
,
5028 current_templates
->start
->name
);
5032 if (!quiet_warnings
)
5035 && (i
.types
[0].bitfield
.jumpabsolute
5036 != operand_types
[0].bitfield
.jumpabsolute
))
5038 as_warn (_("indirect %s without `*'"), t
->name
);
5041 if (t
->opcode_modifier
.isprefix
5042 && t
->opcode_modifier
.ignoresize
)
5044 /* Warn them that a data or address size prefix doesn't
5045 affect assembly of the next line of code. */
5046 as_warn (_("stand-alone `%s' prefix"), t
->name
);
5050 /* Copy the template we found. */
5053 if (addr_prefix_disp
!= -1)
5054 i
.tm
.operand_types
[addr_prefix_disp
]
5055 = operand_types
[addr_prefix_disp
];
5057 if (found_reverse_match
)
5059 /* If we found a reverse match we must alter the opcode
5060 direction bit. found_reverse_match holds bits to change
5061 (different for int & float insns). */
5063 i
.tm
.base_opcode
^= found_reverse_match
;
5065 i
.tm
.operand_types
[0] = operand_types
[1];
5066 i
.tm
.operand_types
[1] = operand_types
[0];
5075 int mem_op
= operand_type_check (i
.types
[0], anymem
) ? 0 : 1;
5076 if (i
.tm
.operand_types
[mem_op
].bitfield
.esseg
)
5078 if (i
.seg
[0] != NULL
&& i
.seg
[0] != &es
)
5080 as_bad (_("`%s' operand %d must use `%ses' segment"),
5086 /* There's only ever one segment override allowed per instruction.
5087 This instruction possibly has a legal segment override on the
5088 second operand, so copy the segment to where non-string
5089 instructions store it, allowing common code. */
5090 i
.seg
[0] = i
.seg
[1];
5092 else if (i
.tm
.operand_types
[mem_op
+ 1].bitfield
.esseg
)
5094 if (i
.seg
[1] != NULL
&& i
.seg
[1] != &es
)
5096 as_bad (_("`%s' operand %d must use `%ses' segment"),
5107 process_suffix (void)
5109 /* If matched instruction specifies an explicit instruction mnemonic
5111 if (i
.tm
.opcode_modifier
.size16
)
5112 i
.suffix
= WORD_MNEM_SUFFIX
;
5113 else if (i
.tm
.opcode_modifier
.size32
)
5114 i
.suffix
= LONG_MNEM_SUFFIX
;
5115 else if (i
.tm
.opcode_modifier
.size64
)
5116 i
.suffix
= QWORD_MNEM_SUFFIX
;
5117 else if (i
.reg_operands
)
5119 /* If there's no instruction mnemonic suffix we try to invent one
5120 based on register operands. */
5123 /* We take i.suffix from the last register operand specified,
5124 Destination register type is more significant than source
5125 register type. crc32 in SSE4.2 prefers source register
5127 if (i
.tm
.base_opcode
== 0xf20f38f1)
5129 if (i
.types
[0].bitfield
.reg16
)
5130 i
.suffix
= WORD_MNEM_SUFFIX
;
5131 else if (i
.types
[0].bitfield
.reg32
)
5132 i
.suffix
= LONG_MNEM_SUFFIX
;
5133 else if (i
.types
[0].bitfield
.reg64
)
5134 i
.suffix
= QWORD_MNEM_SUFFIX
;
5136 else if (i
.tm
.base_opcode
== 0xf20f38f0)
5138 if (i
.types
[0].bitfield
.reg8
)
5139 i
.suffix
= BYTE_MNEM_SUFFIX
;
5146 if (i
.tm
.base_opcode
== 0xf20f38f1
5147 || i
.tm
.base_opcode
== 0xf20f38f0)
5149 /* We have to know the operand size for crc32. */
5150 as_bad (_("ambiguous memory operand size for `%s`"),
5155 for (op
= i
.operands
; --op
>= 0;)
5156 if (!i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
5158 if (i
.types
[op
].bitfield
.reg8
)
5160 i
.suffix
= BYTE_MNEM_SUFFIX
;
5163 else if (i
.types
[op
].bitfield
.reg16
)
5165 i
.suffix
= WORD_MNEM_SUFFIX
;
5168 else if (i
.types
[op
].bitfield
.reg32
)
5170 i
.suffix
= LONG_MNEM_SUFFIX
;
5173 else if (i
.types
[op
].bitfield
.reg64
)
5175 i
.suffix
= QWORD_MNEM_SUFFIX
;
5181 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
5184 && i
.tm
.opcode_modifier
.ignoresize
5185 && i
.tm
.opcode_modifier
.no_bsuf
)
5187 else if (!check_byte_reg ())
5190 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
5193 && i
.tm
.opcode_modifier
.ignoresize
5194 && i
.tm
.opcode_modifier
.no_lsuf
)
5196 else if (!check_long_reg ())
5199 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
5202 && i
.tm
.opcode_modifier
.ignoresize
5203 && i
.tm
.opcode_modifier
.no_qsuf
)
5205 else if (!check_qword_reg ())
5208 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
5211 && i
.tm
.opcode_modifier
.ignoresize
5212 && i
.tm
.opcode_modifier
.no_wsuf
)
5214 else if (!check_word_reg ())
5217 else if (i
.suffix
== XMMWORD_MNEM_SUFFIX
5218 || i
.suffix
== YMMWORD_MNEM_SUFFIX
5219 || i
.suffix
== ZMMWORD_MNEM_SUFFIX
)
5221 /* Skip if the instruction has x/y/z suffix. match_template
5222 should check if it is a valid suffix. */
5224 else if (intel_syntax
&& i
.tm
.opcode_modifier
.ignoresize
)
5225 /* Do nothing if the instruction is going to ignore the prefix. */
5230 else if (i
.tm
.opcode_modifier
.defaultsize
5232 /* exclude fldenv/frstor/fsave/fstenv */
5233 && i
.tm
.opcode_modifier
.no_ssuf
)
5235 i
.suffix
= stackop_size
;
5237 else if (intel_syntax
5239 && (i
.tm
.operand_types
[0].bitfield
.jumpabsolute
5240 || i
.tm
.opcode_modifier
.jumpbyte
5241 || i
.tm
.opcode_modifier
.jumpintersegment
5242 || (i
.tm
.base_opcode
== 0x0f01 /* [ls][gi]dt */
5243 && i
.tm
.extension_opcode
<= 3)))
5248 if (!i
.tm
.opcode_modifier
.no_qsuf
)
5250 i
.suffix
= QWORD_MNEM_SUFFIX
;
5254 if (!i
.tm
.opcode_modifier
.no_lsuf
)
5255 i
.suffix
= LONG_MNEM_SUFFIX
;
5258 if (!i
.tm
.opcode_modifier
.no_wsuf
)
5259 i
.suffix
= WORD_MNEM_SUFFIX
;
5268 if (i
.tm
.opcode_modifier
.w
)
5270 as_bad (_("no instruction mnemonic suffix given and "
5271 "no register operands; can't size instruction"));
5277 unsigned int suffixes
;
5279 suffixes
= !i
.tm
.opcode_modifier
.no_bsuf
;
5280 if (!i
.tm
.opcode_modifier
.no_wsuf
)
5282 if (!i
.tm
.opcode_modifier
.no_lsuf
)
5284 if (!i
.tm
.opcode_modifier
.no_ldsuf
)
5286 if (!i
.tm
.opcode_modifier
.no_ssuf
)
5288 if (!i
.tm
.opcode_modifier
.no_qsuf
)
5291 /* There are more than suffix matches. */
5292 if (i
.tm
.opcode_modifier
.w
5293 || ((suffixes
& (suffixes
- 1))
5294 && !i
.tm
.opcode_modifier
.defaultsize
5295 && !i
.tm
.opcode_modifier
.ignoresize
))
5297 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
5303 /* Change the opcode based on the operand size given by i.suffix;
5304 We don't need to change things for byte insns. */
5307 && i
.suffix
!= BYTE_MNEM_SUFFIX
5308 && i
.suffix
!= XMMWORD_MNEM_SUFFIX
5309 && i
.suffix
!= YMMWORD_MNEM_SUFFIX
5310 && i
.suffix
!= ZMMWORD_MNEM_SUFFIX
)
5312 /* It's not a byte, select word/dword operation. */
5313 if (i
.tm
.opcode_modifier
.w
)
5315 if (i
.tm
.opcode_modifier
.shortform
)
5316 i
.tm
.base_opcode
|= 8;
5318 i
.tm
.base_opcode
|= 1;
5321 /* Now select between word & dword operations via the operand
5322 size prefix, except for instructions that will ignore this
5324 if (i
.tm
.opcode_modifier
.addrprefixop0
)
5326 /* The address size override prefix changes the size of the
5328 if ((flag_code
== CODE_32BIT
5329 && i
.op
->regs
[0].reg_type
.bitfield
.reg16
)
5330 || (flag_code
!= CODE_32BIT
5331 && i
.op
->regs
[0].reg_type
.bitfield
.reg32
))
5332 if (!add_prefix (ADDR_PREFIX_OPCODE
))
5335 else if (i
.suffix
!= QWORD_MNEM_SUFFIX
5336 && i
.suffix
!= LONG_DOUBLE_MNEM_SUFFIX
5337 && !i
.tm
.opcode_modifier
.ignoresize
5338 && !i
.tm
.opcode_modifier
.floatmf
5339 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
5340 || (flag_code
== CODE_64BIT
5341 && i
.tm
.opcode_modifier
.jumpbyte
)))
5343 unsigned int prefix
= DATA_PREFIX_OPCODE
;
5345 if (i
.tm
.opcode_modifier
.jumpbyte
) /* jcxz, loop */
5346 prefix
= ADDR_PREFIX_OPCODE
;
5348 if (!add_prefix (prefix
))
5352 /* Set mode64 for an operand. */
5353 if (i
.suffix
== QWORD_MNEM_SUFFIX
5354 && flag_code
== CODE_64BIT
5355 && !i
.tm
.opcode_modifier
.norex64
)
5357 /* Special case for xchg %rax,%rax. It is NOP and doesn't
5358 need rex64. cmpxchg8b is also a special case. */
5359 if (! (i
.operands
== 2
5360 && i
.tm
.base_opcode
== 0x90
5361 && i
.tm
.extension_opcode
== None
5362 && operand_type_equal (&i
.types
[0], &acc64
)
5363 && operand_type_equal (&i
.types
[1], &acc64
))
5364 && ! (i
.operands
== 1
5365 && i
.tm
.base_opcode
== 0xfc7
5366 && i
.tm
.extension_opcode
== 1
5367 && !operand_type_check (i
.types
[0], reg
)
5368 && operand_type_check (i
.types
[0], anymem
)))
5372 /* Size floating point instruction. */
5373 if (i
.suffix
== LONG_MNEM_SUFFIX
)
5374 if (i
.tm
.opcode_modifier
.floatmf
)
5375 i
.tm
.base_opcode
^= 4;
5382 check_byte_reg (void)
5386 for (op
= i
.operands
; --op
>= 0;)
5388 /* If this is an eight bit register, it's OK. If it's the 16 or
5389 32 bit version of an eight bit register, we will just use the
5390 low portion, and that's OK too. */
5391 if (i
.types
[op
].bitfield
.reg8
)
5394 /* I/O port address operands are OK too. */
5395 if (i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
5398 /* crc32 doesn't generate this warning. */
5399 if (i
.tm
.base_opcode
== 0xf20f38f0)
5402 if ((i
.types
[op
].bitfield
.reg16
5403 || i
.types
[op
].bitfield
.reg32
5404 || i
.types
[op
].bitfield
.reg64
)
5405 && i
.op
[op
].regs
->reg_num
< 4
5406 /* Prohibit these changes in 64bit mode, since the lowering
5407 would be more complicated. */
5408 && flag_code
!= CODE_64BIT
)
5410 #if REGISTER_WARNINGS
5411 if (!quiet_warnings
)
5412 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5414 (i
.op
[op
].regs
+ (i
.types
[op
].bitfield
.reg16
5415 ? REGNAM_AL
- REGNAM_AX
5416 : REGNAM_AL
- REGNAM_EAX
))->reg_name
,
5418 i
.op
[op
].regs
->reg_name
,
5423 /* Any other register is bad. */
5424 if (i
.types
[op
].bitfield
.reg16
5425 || i
.types
[op
].bitfield
.reg32
5426 || i
.types
[op
].bitfield
.reg64
5427 || i
.types
[op
].bitfield
.regmmx
5428 || i
.types
[op
].bitfield
.regxmm
5429 || i
.types
[op
].bitfield
.regymm
5430 || i
.types
[op
].bitfield
.regzmm
5431 || i
.types
[op
].bitfield
.sreg2
5432 || i
.types
[op
].bitfield
.sreg3
5433 || i
.types
[op
].bitfield
.control
5434 || i
.types
[op
].bitfield
.debug
5435 || i
.types
[op
].bitfield
.test
5436 || i
.types
[op
].bitfield
.floatreg
5437 || i
.types
[op
].bitfield
.floatacc
)
5439 as_bad (_("`%s%s' not allowed with `%s%c'"),
5441 i
.op
[op
].regs
->reg_name
,
5451 check_long_reg (void)
5455 for (op
= i
.operands
; --op
>= 0;)
5456 /* Reject eight bit registers, except where the template requires
5457 them. (eg. movzb) */
5458 if (i
.types
[op
].bitfield
.reg8
5459 && (i
.tm
.operand_types
[op
].bitfield
.reg16
5460 || i
.tm
.operand_types
[op
].bitfield
.reg32
5461 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5463 as_bad (_("`%s%s' not allowed with `%s%c'"),
5465 i
.op
[op
].regs
->reg_name
,
5470 /* Warn if the e prefix on a general reg is missing. */
5471 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
5472 && i
.types
[op
].bitfield
.reg16
5473 && (i
.tm
.operand_types
[op
].bitfield
.reg32
5474 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5476 /* Prohibit these changes in the 64bit mode, since the
5477 lowering is more complicated. */
5478 if (flag_code
== CODE_64BIT
)
5480 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5481 register_prefix
, i
.op
[op
].regs
->reg_name
,
5485 #if REGISTER_WARNINGS
5486 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5488 (i
.op
[op
].regs
+ REGNAM_EAX
- REGNAM_AX
)->reg_name
,
5489 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
5492 /* Warn if the r prefix on a general reg is present. */
5493 else if (i
.types
[op
].bitfield
.reg64
5494 && (i
.tm
.operand_types
[op
].bitfield
.reg32
5495 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5498 && i
.tm
.opcode_modifier
.toqword
5499 && !i
.types
[0].bitfield
.regxmm
)
5501 /* Convert to QWORD. We want REX byte. */
5502 i
.suffix
= QWORD_MNEM_SUFFIX
;
5506 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5507 register_prefix
, i
.op
[op
].regs
->reg_name
,
5516 check_qword_reg (void)
5520 for (op
= i
.operands
; --op
>= 0; )
5521 /* Reject eight bit registers, except where the template requires
5522 them. (eg. movzb) */
5523 if (i
.types
[op
].bitfield
.reg8
5524 && (i
.tm
.operand_types
[op
].bitfield
.reg16
5525 || i
.tm
.operand_types
[op
].bitfield
.reg32
5526 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5528 as_bad (_("`%s%s' not allowed with `%s%c'"),
5530 i
.op
[op
].regs
->reg_name
,
5535 /* Warn if the r prefix on a general reg is missing. */
5536 else if ((i
.types
[op
].bitfield
.reg16
5537 || i
.types
[op
].bitfield
.reg32
)
5538 && (i
.tm
.operand_types
[op
].bitfield
.reg32
5539 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5541 /* Prohibit these changes in the 64bit mode, since the
5542 lowering is more complicated. */
5544 && i
.tm
.opcode_modifier
.todword
5545 && !i
.types
[0].bitfield
.regxmm
)
5547 /* Convert to DWORD. We don't want REX byte. */
5548 i
.suffix
= LONG_MNEM_SUFFIX
;
5552 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5553 register_prefix
, i
.op
[op
].regs
->reg_name
,
5562 check_word_reg (void)
5565 for (op
= i
.operands
; --op
>= 0;)
5566 /* Reject eight bit registers, except where the template requires
5567 them. (eg. movzb) */
5568 if (i
.types
[op
].bitfield
.reg8
5569 && (i
.tm
.operand_types
[op
].bitfield
.reg16
5570 || i
.tm
.operand_types
[op
].bitfield
.reg32
5571 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5573 as_bad (_("`%s%s' not allowed with `%s%c'"),
5575 i
.op
[op
].regs
->reg_name
,
5580 /* Warn if the e or r prefix on a general reg is present. */
5581 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
5582 && (i
.types
[op
].bitfield
.reg32
5583 || i
.types
[op
].bitfield
.reg64
)
5584 && (i
.tm
.operand_types
[op
].bitfield
.reg16
5585 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5587 /* Prohibit these changes in the 64bit mode, since the
5588 lowering is more complicated. */
5589 if (flag_code
== CODE_64BIT
)
5591 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5592 register_prefix
, i
.op
[op
].regs
->reg_name
,
5596 #if REGISTER_WARNINGS
5597 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5599 (i
.op
[op
].regs
+ REGNAM_AX
- REGNAM_EAX
)->reg_name
,
5600 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
5607 update_imm (unsigned int j
)
5609 i386_operand_type overlap
= i
.types
[j
];
5610 if ((overlap
.bitfield
.imm8
5611 || overlap
.bitfield
.imm8s
5612 || overlap
.bitfield
.imm16
5613 || overlap
.bitfield
.imm32
5614 || overlap
.bitfield
.imm32s
5615 || overlap
.bitfield
.imm64
)
5616 && !operand_type_equal (&overlap
, &imm8
)
5617 && !operand_type_equal (&overlap
, &imm8s
)
5618 && !operand_type_equal (&overlap
, &imm16
)
5619 && !operand_type_equal (&overlap
, &imm32
)
5620 && !operand_type_equal (&overlap
, &imm32s
)
5621 && !operand_type_equal (&overlap
, &imm64
))
5625 i386_operand_type temp
;
5627 operand_type_set (&temp
, 0);
5628 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
5630 temp
.bitfield
.imm8
= overlap
.bitfield
.imm8
;
5631 temp
.bitfield
.imm8s
= overlap
.bitfield
.imm8s
;
5633 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
5634 temp
.bitfield
.imm16
= overlap
.bitfield
.imm16
;
5635 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
5637 temp
.bitfield
.imm64
= overlap
.bitfield
.imm64
;
5638 temp
.bitfield
.imm32s
= overlap
.bitfield
.imm32s
;
5641 temp
.bitfield
.imm32
= overlap
.bitfield
.imm32
;
5644 else if (operand_type_equal (&overlap
, &imm16_32_32s
)
5645 || operand_type_equal (&overlap
, &imm16_32
)
5646 || operand_type_equal (&overlap
, &imm16_32s
))
5648 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
5653 if (!operand_type_equal (&overlap
, &imm8
)
5654 && !operand_type_equal (&overlap
, &imm8s
)
5655 && !operand_type_equal (&overlap
, &imm16
)
5656 && !operand_type_equal (&overlap
, &imm32
)
5657 && !operand_type_equal (&overlap
, &imm32s
)
5658 && !operand_type_equal (&overlap
, &imm64
))
5660 as_bad (_("no instruction mnemonic suffix given; "
5661 "can't determine immediate size"));
5665 i
.types
[j
] = overlap
;
5675 /* Update the first 2 immediate operands. */
5676 n
= i
.operands
> 2 ? 2 : i
.operands
;
5679 for (j
= 0; j
< n
; j
++)
5680 if (update_imm (j
) == 0)
5683 /* The 3rd operand can't be immediate operand. */
5684 gas_assert (operand_type_check (i
.types
[2], imm
) == 0);
5691 bad_implicit_operand (int xmm
)
5693 const char *ireg
= xmm
? "xmm0" : "ymm0";
5696 as_bad (_("the last operand of `%s' must be `%s%s'"),
5697 i
.tm
.name
, register_prefix
, ireg
);
5699 as_bad (_("the first operand of `%s' must be `%s%s'"),
5700 i
.tm
.name
, register_prefix
, ireg
);
5705 process_operands (void)
5707 /* Default segment register this instruction will use for memory
5708 accesses. 0 means unknown. This is only for optimizing out
5709 unnecessary segment overrides. */
5710 const seg_entry
*default_seg
= 0;
5712 if (i
.tm
.opcode_modifier
.sse2avx
&& i
.tm
.opcode_modifier
.vexvvvv
)
5714 unsigned int dupl
= i
.operands
;
5715 unsigned int dest
= dupl
- 1;
5718 /* The destination must be an xmm register. */
5719 gas_assert (i
.reg_operands
5720 && MAX_OPERANDS
> dupl
5721 && operand_type_equal (&i
.types
[dest
], ®xmm
));
5723 if (i
.tm
.opcode_modifier
.firstxmm0
)
5725 /* The first operand is implicit and must be xmm0. */
5726 gas_assert (operand_type_equal (&i
.types
[0], ®xmm
));
5727 if (register_number (i
.op
[0].regs
) != 0)
5728 return bad_implicit_operand (1);
5730 if (i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
)
5732 /* Keep xmm0 for instructions with VEX prefix and 3
5738 /* We remove the first xmm0 and keep the number of
5739 operands unchanged, which in fact duplicates the
5741 for (j
= 1; j
< i
.operands
; j
++)
5743 i
.op
[j
- 1] = i
.op
[j
];
5744 i
.types
[j
- 1] = i
.types
[j
];
5745 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
5749 else if (i
.tm
.opcode_modifier
.implicit1stxmm0
)
5751 gas_assert ((MAX_OPERANDS
- 1) > dupl
5752 && (i
.tm
.opcode_modifier
.vexsources
5755 /* Add the implicit xmm0 for instructions with VEX prefix
5757 for (j
= i
.operands
; j
> 0; j
--)
5759 i
.op
[j
] = i
.op
[j
- 1];
5760 i
.types
[j
] = i
.types
[j
- 1];
5761 i
.tm
.operand_types
[j
] = i
.tm
.operand_types
[j
- 1];
5764 = (const reg_entry
*) hash_find (reg_hash
, "xmm0");
5765 i
.types
[0] = regxmm
;
5766 i
.tm
.operand_types
[0] = regxmm
;
5769 i
.reg_operands
+= 2;
5774 i
.op
[dupl
] = i
.op
[dest
];
5775 i
.types
[dupl
] = i
.types
[dest
];
5776 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
5785 i
.op
[dupl
] = i
.op
[dest
];
5786 i
.types
[dupl
] = i
.types
[dest
];
5787 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
5790 if (i
.tm
.opcode_modifier
.immext
)
5793 else if (i
.tm
.opcode_modifier
.firstxmm0
)
5797 /* The first operand is implicit and must be xmm0/ymm0/zmm0. */
5798 gas_assert (i
.reg_operands
5799 && (operand_type_equal (&i
.types
[0], ®xmm
)
5800 || operand_type_equal (&i
.types
[0], ®ymm
)
5801 || operand_type_equal (&i
.types
[0], ®zmm
)));
5802 if (register_number (i
.op
[0].regs
) != 0)
5803 return bad_implicit_operand (i
.types
[0].bitfield
.regxmm
);
5805 for (j
= 1; j
< i
.operands
; j
++)
5807 i
.op
[j
- 1] = i
.op
[j
];
5808 i
.types
[j
- 1] = i
.types
[j
];
5810 /* We need to adjust fields in i.tm since they are used by
5811 build_modrm_byte. */
5812 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
5819 else if (i
.tm
.opcode_modifier
.regkludge
)
5821 /* The imul $imm, %reg instruction is converted into
5822 imul $imm, %reg, %reg, and the clr %reg instruction
5823 is converted into xor %reg, %reg. */
5825 unsigned int first_reg_op
;
5827 if (operand_type_check (i
.types
[0], reg
))
5831 /* Pretend we saw the extra register operand. */
5832 gas_assert (i
.reg_operands
== 1
5833 && i
.op
[first_reg_op
+ 1].regs
== 0);
5834 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
5835 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
5840 if (i
.tm
.opcode_modifier
.shortform
)
5842 if (i
.types
[0].bitfield
.sreg2
5843 || i
.types
[0].bitfield
.sreg3
)
5845 if (i
.tm
.base_opcode
== POP_SEG_SHORT
5846 && i
.op
[0].regs
->reg_num
== 1)
5848 as_bad (_("you can't `pop %scs'"), register_prefix
);
5851 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
5852 if ((i
.op
[0].regs
->reg_flags
& RegRex
) != 0)
5857 /* The register or float register operand is in operand
5861 if (i
.types
[0].bitfield
.floatreg
5862 || operand_type_check (i
.types
[0], reg
))
5866 /* Register goes in low 3 bits of opcode. */
5867 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
5868 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
5870 if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
5872 /* Warn about some common errors, but press on regardless.
5873 The first case can be generated by gcc (<= 2.8.1). */
5874 if (i
.operands
== 2)
5876 /* Reversed arguments on faddp, fsubp, etc. */
5877 as_warn (_("translating to `%s %s%s,%s%s'"), i
.tm
.name
,
5878 register_prefix
, i
.op
[!intel_syntax
].regs
->reg_name
,
5879 register_prefix
, i
.op
[intel_syntax
].regs
->reg_name
);
5883 /* Extraneous `l' suffix on fp insn. */
5884 as_warn (_("translating to `%s %s%s'"), i
.tm
.name
,
5885 register_prefix
, i
.op
[0].regs
->reg_name
);
5890 else if (i
.tm
.opcode_modifier
.modrm
)
5892 /* The opcode is completed (modulo i.tm.extension_opcode which
5893 must be put into the modrm byte). Now, we make the modrm and
5894 index base bytes based on all the info we've collected. */
5896 default_seg
= build_modrm_byte ();
5898 else if ((i
.tm
.base_opcode
& ~0x3) == MOV_AX_DISP32
)
5902 else if (i
.tm
.opcode_modifier
.isstring
)
5904 /* For the string instructions that allow a segment override
5905 on one of their operands, the default segment is ds. */
5909 if (i
.tm
.base_opcode
== 0x8d /* lea */
5912 as_warn (_("segment override on `%s' is ineffectual"), i
.tm
.name
);
5914 /* If a segment was explicitly specified, and the specified segment
5915 is not the default, use an opcode prefix to select it. If we
5916 never figured out what the default segment is, then default_seg
5917 will be zero at this point, and the specified segment prefix will
5919 if ((i
.seg
[0]) && (i
.seg
[0] != default_seg
))
5921 if (!add_prefix (i
.seg
[0]->seg_prefix
))
5927 static const seg_entry
*
5928 build_modrm_byte (void)
5930 const seg_entry
*default_seg
= 0;
5931 unsigned int source
, dest
;
5934 /* The first operand of instructions with VEX prefix and 3 sources
5935 must be VEX_Imm4. */
5936 vex_3_sources
= i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
;
5939 unsigned int nds
, reg_slot
;
5942 if (i
.tm
.opcode_modifier
.veximmext
5943 && i
.tm
.opcode_modifier
.immext
)
5945 dest
= i
.operands
- 2;
5946 gas_assert (dest
== 3);
5949 dest
= i
.operands
- 1;
5952 /* There are 2 kinds of instructions:
5953 1. 5 operands: 4 register operands or 3 register operands
5954 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
5955 VexW0 or VexW1. The destination must be either XMM, YMM or
5957 2. 4 operands: 4 register operands or 3 register operands
5958 plus 1 memory operand, VexXDS, and VexImmExt */
5959 gas_assert ((i
.reg_operands
== 4
5960 || (i
.reg_operands
== 3 && i
.mem_operands
== 1))
5961 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
5962 && (i
.tm
.opcode_modifier
.veximmext
5963 || (i
.imm_operands
== 1
5964 && i
.types
[0].bitfield
.vec_imm4
5965 && (i
.tm
.opcode_modifier
.vexw
== VEXW0
5966 || i
.tm
.opcode_modifier
.vexw
== VEXW1
)
5967 && (operand_type_equal (&i
.tm
.operand_types
[dest
], ®xmm
)
5968 || operand_type_equal (&i
.tm
.operand_types
[dest
], ®ymm
)
5969 || operand_type_equal (&i
.tm
.operand_types
[dest
], ®zmm
)))));
5971 if (i
.imm_operands
== 0)
5973 /* When there is no immediate operand, generate an 8bit
5974 immediate operand to encode the first operand. */
5975 exp
= &im_expressions
[i
.imm_operands
++];
5976 i
.op
[i
.operands
].imms
= exp
;
5977 i
.types
[i
.operands
] = imm8
;
5979 /* If VexW1 is set, the first operand is the source and
5980 the second operand is encoded in the immediate operand. */
5981 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
5992 /* FMA swaps REG and NDS. */
5993 if (i
.tm
.cpu_flags
.bitfield
.cpufma
)
6001 gas_assert (operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6003 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6005 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6007 exp
->X_op
= O_constant
;
6008 exp
->X_add_number
= register_number (i
.op
[reg_slot
].regs
) << 4;
6009 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
6013 unsigned int imm_slot
;
6015 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
6017 /* If VexW0 is set, the third operand is the source and
6018 the second operand is encoded in the immediate
6025 /* VexW1 is set, the second operand is the source and
6026 the third operand is encoded in the immediate
6032 if (i
.tm
.opcode_modifier
.immext
)
6034 /* When ImmExt is set, the immdiate byte is the last
6036 imm_slot
= i
.operands
- 1;
6044 /* Turn on Imm8 so that output_imm will generate it. */
6045 i
.types
[imm_slot
].bitfield
.imm8
= 1;
6048 gas_assert (operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6050 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6052 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6054 i
.op
[imm_slot
].imms
->X_add_number
6055 |= register_number (i
.op
[reg_slot
].regs
) << 4;
6056 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
6059 gas_assert (operand_type_equal (&i
.tm
.operand_types
[nds
], ®xmm
)
6060 || operand_type_equal (&i
.tm
.operand_types
[nds
],
6062 || operand_type_equal (&i
.tm
.operand_types
[nds
],
6064 i
.vex
.register_specifier
= i
.op
[nds
].regs
;
6069 /* i.reg_operands MUST be the number of real register operands;
6070 implicit registers do not count. If there are 3 register
6071 operands, it must be a instruction with VexNDS. For a
6072 instruction with VexNDD, the destination register is encoded
6073 in VEX prefix. If there are 4 register operands, it must be
6074 a instruction with VEX prefix and 3 sources. */
6075 if (i
.mem_operands
== 0
6076 && ((i
.reg_operands
== 2
6077 && i
.tm
.opcode_modifier
.vexvvvv
<= VEXXDS
)
6078 || (i
.reg_operands
== 3
6079 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
6080 || (i
.reg_operands
== 4 && vex_3_sources
)))
6088 /* When there are 3 operands, one of them may be immediate,
6089 which may be the first or the last operand. Otherwise,
6090 the first operand must be shift count register (cl) or it
6091 is an instruction with VexNDS. */
6092 gas_assert (i
.imm_operands
== 1
6093 || (i
.imm_operands
== 0
6094 && (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
6095 || i
.types
[0].bitfield
.shiftcount
)));
6096 if (operand_type_check (i
.types
[0], imm
)
6097 || i
.types
[0].bitfield
.shiftcount
)
6103 /* When there are 4 operands, the first two must be 8bit
6104 immediate operands. The source operand will be the 3rd
6107 For instructions with VexNDS, if the first operand
6108 an imm8, the source operand is the 2nd one. If the last
6109 operand is imm8, the source operand is the first one. */
6110 gas_assert ((i
.imm_operands
== 2
6111 && i
.types
[0].bitfield
.imm8
6112 && i
.types
[1].bitfield
.imm8
)
6113 || (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
6114 && i
.imm_operands
== 1
6115 && (i
.types
[0].bitfield
.imm8
6116 || i
.types
[i
.operands
- 1].bitfield
.imm8
6118 if (i
.imm_operands
== 2)
6122 if (i
.types
[0].bitfield
.imm8
)
6129 if (i
.tm
.opcode_modifier
.evex
)
6131 /* For EVEX instructions, when there are 5 operands, the
6132 first one must be immediate operand. If the second one
6133 is immediate operand, the source operand is the 3th
6134 one. If the last one is immediate operand, the source
6135 operand is the 2nd one. */
6136 gas_assert (i
.imm_operands
== 2
6137 && i
.tm
.opcode_modifier
.sae
6138 && operand_type_check (i
.types
[0], imm
));
6139 if (operand_type_check (i
.types
[1], imm
))
6141 else if (operand_type_check (i
.types
[4], imm
))
6155 /* RC/SAE operand could be between DEST and SRC. That happens
6156 when one operand is GPR and the other one is XMM/YMM/ZMM
6158 if (i
.rounding
&& i
.rounding
->operand
== (int) dest
)
6161 if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
6163 /* For instructions with VexNDS, the register-only source
6164 operand must be 32/64bit integer, XMM, YMM or ZMM
6165 register. It is encoded in VEX prefix. We need to
6166 clear RegMem bit before calling operand_type_equal. */
6168 i386_operand_type op
;
6171 /* Check register-only source operand when two source
6172 operands are swapped. */
6173 if (!i
.tm
.operand_types
[source
].bitfield
.baseindex
6174 && i
.tm
.operand_types
[dest
].bitfield
.baseindex
)
6182 op
= i
.tm
.operand_types
[vvvv
];
6183 op
.bitfield
.regmem
= 0;
6184 if ((dest
+ 1) >= i
.operands
6185 || (!op
.bitfield
.reg32
6186 && op
.bitfield
.reg64
6187 && !operand_type_equal (&op
, ®xmm
)
6188 && !operand_type_equal (&op
, ®ymm
)
6189 && !operand_type_equal (&op
, ®zmm
)
6190 && !operand_type_equal (&op
, ®mask
)))
6192 i
.vex
.register_specifier
= i
.op
[vvvv
].regs
;
6198 /* One of the register operands will be encoded in the i.tm.reg
6199 field, the other in the combined i.tm.mode and i.tm.regmem
6200 fields. If no form of this instruction supports a memory
6201 destination operand, then we assume the source operand may
6202 sometimes be a memory operand and so we need to store the
6203 destination in the i.rm.reg field. */
6204 if (!i
.tm
.operand_types
[dest
].bitfield
.regmem
6205 && operand_type_check (i
.tm
.operand_types
[dest
], anymem
) == 0)
6207 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
6208 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
6209 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
6211 if ((i
.op
[dest
].regs
->reg_flags
& RegVRex
) != 0)
6213 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
6215 if ((i
.op
[source
].regs
->reg_flags
& RegVRex
) != 0)
6220 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
6221 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
6222 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
6224 if ((i
.op
[dest
].regs
->reg_flags
& RegVRex
) != 0)
6226 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
6228 if ((i
.op
[source
].regs
->reg_flags
& RegVRex
) != 0)
6231 if (flag_code
!= CODE_64BIT
&& (i
.rex
& (REX_R
| REX_B
)))
6233 if (!i
.types
[0].bitfield
.control
6234 && !i
.types
[1].bitfield
.control
)
6236 i
.rex
&= ~(REX_R
| REX_B
);
6237 add_prefix (LOCK_PREFIX_OPCODE
);
6241 { /* If it's not 2 reg operands... */
6246 unsigned int fake_zero_displacement
= 0;
6249 for (op
= 0; op
< i
.operands
; op
++)
6250 if (operand_type_check (i
.types
[op
], anymem
))
6252 gas_assert (op
< i
.operands
);
6254 if (i
.tm
.opcode_modifier
.vecsib
)
6256 if (i
.index_reg
->reg_num
== RegEiz
6257 || i
.index_reg
->reg_num
== RegRiz
)
6260 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6263 i
.sib
.base
= NO_BASE_REGISTER
;
6264 i
.sib
.scale
= i
.log2_scale_factor
;
6265 /* No Vec_Disp8 if there is no base. */
6266 i
.types
[op
].bitfield
.vec_disp8
= 0;
6267 i
.types
[op
].bitfield
.disp8
= 0;
6268 i
.types
[op
].bitfield
.disp16
= 0;
6269 i
.types
[op
].bitfield
.disp64
= 0;
6270 if (flag_code
!= CODE_64BIT
)
6272 /* Must be 32 bit */
6273 i
.types
[op
].bitfield
.disp32
= 1;
6274 i
.types
[op
].bitfield
.disp32s
= 0;
6278 i
.types
[op
].bitfield
.disp32
= 0;
6279 i
.types
[op
].bitfield
.disp32s
= 1;
6282 i
.sib
.index
= i
.index_reg
->reg_num
;
6283 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
6285 if ((i
.index_reg
->reg_flags
& RegVRex
) != 0)
6291 if (i
.base_reg
== 0)
6294 if (!i
.disp_operands
)
6296 fake_zero_displacement
= 1;
6297 /* Instructions with VSIB byte need 32bit displacement
6298 if there is no base register. */
6299 if (i
.tm
.opcode_modifier
.vecsib
)
6300 i
.types
[op
].bitfield
.disp32
= 1;
6302 if (i
.index_reg
== 0)
6304 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6305 /* Operand is just <disp> */
6306 if (flag_code
== CODE_64BIT
)
6308 /* 64bit mode overwrites the 32bit absolute
6309 addressing by RIP relative addressing and
6310 absolute addressing is encoded by one of the
6311 redundant SIB forms. */
6312 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6313 i
.sib
.base
= NO_BASE_REGISTER
;
6314 i
.sib
.index
= NO_INDEX_REGISTER
;
6315 i
.types
[op
] = ((i
.prefix
[ADDR_PREFIX
] == 0)
6316 ? disp32s
: disp32
);
6318 else if ((flag_code
== CODE_16BIT
)
6319 ^ (i
.prefix
[ADDR_PREFIX
] != 0))
6321 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
6322 i
.types
[op
] = disp16
;
6326 i
.rm
.regmem
= NO_BASE_REGISTER
;
6327 i
.types
[op
] = disp32
;
6330 else if (!i
.tm
.opcode_modifier
.vecsib
)
6332 /* !i.base_reg && i.index_reg */
6333 if (i
.index_reg
->reg_num
== RegEiz
6334 || i
.index_reg
->reg_num
== RegRiz
)
6335 i
.sib
.index
= NO_INDEX_REGISTER
;
6337 i
.sib
.index
= i
.index_reg
->reg_num
;
6338 i
.sib
.base
= NO_BASE_REGISTER
;
6339 i
.sib
.scale
= i
.log2_scale_factor
;
6340 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6341 /* No Vec_Disp8 if there is no base. */
6342 i
.types
[op
].bitfield
.vec_disp8
= 0;
6343 i
.types
[op
].bitfield
.disp8
= 0;
6344 i
.types
[op
].bitfield
.disp16
= 0;
6345 i
.types
[op
].bitfield
.disp64
= 0;
6346 if (flag_code
!= CODE_64BIT
)
6348 /* Must be 32 bit */
6349 i
.types
[op
].bitfield
.disp32
= 1;
6350 i
.types
[op
].bitfield
.disp32s
= 0;
6354 i
.types
[op
].bitfield
.disp32
= 0;
6355 i
.types
[op
].bitfield
.disp32s
= 1;
6357 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
6361 /* RIP addressing for 64bit mode. */
6362 else if (i
.base_reg
->reg_num
== RegRip
||
6363 i
.base_reg
->reg_num
== RegEip
)
6365 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6366 i
.rm
.regmem
= NO_BASE_REGISTER
;
6367 i
.types
[op
].bitfield
.disp8
= 0;
6368 i
.types
[op
].bitfield
.disp16
= 0;
6369 i
.types
[op
].bitfield
.disp32
= 0;
6370 i
.types
[op
].bitfield
.disp32s
= 1;
6371 i
.types
[op
].bitfield
.disp64
= 0;
6372 i
.types
[op
].bitfield
.vec_disp8
= 0;
6373 i
.flags
[op
] |= Operand_PCrel
;
6374 if (! i
.disp_operands
)
6375 fake_zero_displacement
= 1;
6377 else if (i
.base_reg
->reg_type
.bitfield
.reg16
)
6379 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6380 switch (i
.base_reg
->reg_num
)
6383 if (i
.index_reg
== 0)
6385 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
6386 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
6390 if (i
.index_reg
== 0)
6393 if (operand_type_check (i
.types
[op
], disp
) == 0)
6395 /* fake (%bp) into 0(%bp) */
6396 if (i
.tm
.operand_types
[op
].bitfield
.vec_disp8
)
6397 i
.types
[op
].bitfield
.vec_disp8
= 1;
6399 i
.types
[op
].bitfield
.disp8
= 1;
6400 fake_zero_displacement
= 1;
6403 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
6404 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
6406 default: /* (%si) -> 4 or (%di) -> 5 */
6407 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
6409 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
6411 else /* i.base_reg and 32/64 bit mode */
6413 if (flag_code
== CODE_64BIT
6414 && operand_type_check (i
.types
[op
], disp
))
6416 i386_operand_type temp
;
6417 operand_type_set (&temp
, 0);
6418 temp
.bitfield
.disp8
= i
.types
[op
].bitfield
.disp8
;
6419 temp
.bitfield
.vec_disp8
6420 = i
.types
[op
].bitfield
.vec_disp8
;
6422 if (i
.prefix
[ADDR_PREFIX
] == 0)
6423 i
.types
[op
].bitfield
.disp32s
= 1;
6425 i
.types
[op
].bitfield
.disp32
= 1;
6428 if (!i
.tm
.opcode_modifier
.vecsib
)
6429 i
.rm
.regmem
= i
.base_reg
->reg_num
;
6430 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
6432 i
.sib
.base
= i
.base_reg
->reg_num
;
6433 /* x86-64 ignores REX prefix bit here to avoid decoder
6435 if (!(i
.base_reg
->reg_flags
& RegRex
)
6436 && (i
.base_reg
->reg_num
== EBP_REG_NUM
6437 || i
.base_reg
->reg_num
== ESP_REG_NUM
))
6439 if (i
.base_reg
->reg_num
== 5 && i
.disp_operands
== 0)
6441 fake_zero_displacement
= 1;
6442 if (i
.tm
.operand_types
[op
].bitfield
.vec_disp8
)
6443 i
.types
[op
].bitfield
.vec_disp8
= 1;
6445 i
.types
[op
].bitfield
.disp8
= 1;
6447 i
.sib
.scale
= i
.log2_scale_factor
;
6448 if (i
.index_reg
== 0)
6450 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6451 /* <disp>(%esp) becomes two byte modrm with no index
6452 register. We've already stored the code for esp
6453 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
6454 Any base register besides %esp will not use the
6455 extra modrm byte. */
6456 i
.sib
.index
= NO_INDEX_REGISTER
;
6458 else if (!i
.tm
.opcode_modifier
.vecsib
)
6460 if (i
.index_reg
->reg_num
== RegEiz
6461 || i
.index_reg
->reg_num
== RegRiz
)
6462 i
.sib
.index
= NO_INDEX_REGISTER
;
6464 i
.sib
.index
= i
.index_reg
->reg_num
;
6465 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6466 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
6471 && (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
6472 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
))
6476 if (!fake_zero_displacement
6480 fake_zero_displacement
= 1;
6481 if (i
.disp_encoding
== disp_encoding_8bit
)
6482 i
.types
[op
].bitfield
.disp8
= 1;
6484 i
.types
[op
].bitfield
.disp32
= 1;
6486 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
6490 if (fake_zero_displacement
)
6492 /* Fakes a zero displacement assuming that i.types[op]
6493 holds the correct displacement size. */
6496 gas_assert (i
.op
[op
].disps
== 0);
6497 exp
= &disp_expressions
[i
.disp_operands
++];
6498 i
.op
[op
].disps
= exp
;
6499 exp
->X_op
= O_constant
;
6500 exp
->X_add_number
= 0;
6501 exp
->X_add_symbol
= (symbolS
*) 0;
6502 exp
->X_op_symbol
= (symbolS
*) 0;
6510 if (i
.tm
.opcode_modifier
.vexsources
== XOP2SOURCES
)
6512 if (operand_type_check (i
.types
[0], imm
))
6513 i
.vex
.register_specifier
= NULL
;
6516 /* VEX.vvvv encodes one of the sources when the first
6517 operand is not an immediate. */
6518 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
6519 i
.vex
.register_specifier
= i
.op
[0].regs
;
6521 i
.vex
.register_specifier
= i
.op
[1].regs
;
6524 /* Destination is a XMM register encoded in the ModRM.reg
6526 i
.rm
.reg
= i
.op
[2].regs
->reg_num
;
6527 if ((i
.op
[2].regs
->reg_flags
& RegRex
) != 0)
6530 /* ModRM.rm and VEX.B encodes the other source. */
6531 if (!i
.mem_operands
)
6535 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
6536 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
6538 i
.rm
.regmem
= i
.op
[0].regs
->reg_num
;
6540 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
6544 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXLWP
)
6546 i
.vex
.register_specifier
= i
.op
[2].regs
;
6547 if (!i
.mem_operands
)
6550 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
6551 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
6555 /* Fill in i.rm.reg or i.rm.regmem field with register operand
6556 (if any) based on i.tm.extension_opcode. Again, we must be
6557 careful to make sure that segment/control/debug/test/MMX
6558 registers are coded into the i.rm.reg field. */
6559 else if (i
.reg_operands
)
6562 unsigned int vex_reg
= ~0;
6564 for (op
= 0; op
< i
.operands
; op
++)
6565 if (i
.types
[op
].bitfield
.reg8
6566 || i
.types
[op
].bitfield
.reg16
6567 || i
.types
[op
].bitfield
.reg32
6568 || i
.types
[op
].bitfield
.reg64
6569 || i
.types
[op
].bitfield
.regmmx
6570 || i
.types
[op
].bitfield
.regxmm
6571 || i
.types
[op
].bitfield
.regymm
6572 || i
.types
[op
].bitfield
.regbnd
6573 || i
.types
[op
].bitfield
.regzmm
6574 || i
.types
[op
].bitfield
.regmask
6575 || i
.types
[op
].bitfield
.sreg2
6576 || i
.types
[op
].bitfield
.sreg3
6577 || i
.types
[op
].bitfield
.control
6578 || i
.types
[op
].bitfield
.debug
6579 || i
.types
[op
].bitfield
.test
)
6584 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
6586 /* For instructions with VexNDS, the register-only
6587 source operand is encoded in VEX prefix. */
6588 gas_assert (mem
!= (unsigned int) ~0);
6593 gas_assert (op
< i
.operands
);
6597 /* Check register-only source operand when two source
6598 operands are swapped. */
6599 if (!i
.tm
.operand_types
[op
].bitfield
.baseindex
6600 && i
.tm
.operand_types
[op
+ 1].bitfield
.baseindex
)
6604 gas_assert (mem
== (vex_reg
+ 1)
6605 && op
< i
.operands
);
6610 gas_assert (vex_reg
< i
.operands
);
6614 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXNDD
)
6616 /* For instructions with VexNDD, the register destination
6617 is encoded in VEX prefix. */
6618 if (i
.mem_operands
== 0)
6620 /* There is no memory operand. */
6621 gas_assert ((op
+ 2) == i
.operands
);
6626 /* There are only 2 operands. */
6627 gas_assert (op
< 2 && i
.operands
== 2);
6632 gas_assert (op
< i
.operands
);
6634 if (vex_reg
!= (unsigned int) ~0)
6636 i386_operand_type
*type
= &i
.tm
.operand_types
[vex_reg
];
6638 if (type
->bitfield
.reg32
!= 1
6639 && type
->bitfield
.reg64
!= 1
6640 && !operand_type_equal (type
, ®xmm
)
6641 && !operand_type_equal (type
, ®ymm
)
6642 && !operand_type_equal (type
, ®zmm
)
6643 && !operand_type_equal (type
, ®mask
))
6646 i
.vex
.register_specifier
= i
.op
[vex_reg
].regs
;
6649 /* Don't set OP operand twice. */
6652 /* If there is an extension opcode to put here, the
6653 register number must be put into the regmem field. */
6654 if (i
.tm
.extension_opcode
!= None
)
6656 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
6657 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
6659 if ((i
.op
[op
].regs
->reg_flags
& RegVRex
) != 0)
6664 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
6665 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
6667 if ((i
.op
[op
].regs
->reg_flags
& RegVRex
) != 0)
6672 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
6673 must set it to 3 to indicate this is a register operand
6674 in the regmem field. */
6675 if (!i
.mem_operands
)
6679 /* Fill in i.rm.reg field with extension opcode (if any). */
6680 if (i
.tm
.extension_opcode
!= None
)
6681 i
.rm
.reg
= i
.tm
.extension_opcode
;
6687 output_branch (void)
6693 relax_substateT subtype
;
6697 code16
= flag_code
== CODE_16BIT
? CODE16
: 0;
6698 size
= i
.disp_encoding
== disp_encoding_32bit
? BIG
: SMALL
;
6701 if (i
.prefix
[DATA_PREFIX
] != 0)
6707 /* Pentium4 branch hints. */
6708 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
6709 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
6714 if (i
.prefix
[REX_PREFIX
] != 0)
6720 /* BND prefixed jump. */
6721 if (i
.prefix
[BND_PREFIX
] != 0)
6723 FRAG_APPEND_1_CHAR (i
.prefix
[BND_PREFIX
]);
6727 if (i
.prefixes
!= 0 && !intel_syntax
)
6728 as_warn (_("skipping prefixes on this instruction"));
6730 /* It's always a symbol; End frag & setup for relax.
6731 Make sure there is enough room in this frag for the largest
6732 instruction we may generate in md_convert_frag. This is 2
6733 bytes for the opcode and room for the prefix and largest
6735 frag_grow (prefix
+ 2 + 4);
6736 /* Prefix and 1 opcode byte go in fr_fix. */
6737 p
= frag_more (prefix
+ 1);
6738 if (i
.prefix
[DATA_PREFIX
] != 0)
6739 *p
++ = DATA_PREFIX_OPCODE
;
6740 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
6741 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
6742 *p
++ = i
.prefix
[SEG_PREFIX
];
6743 if (i
.prefix
[REX_PREFIX
] != 0)
6744 *p
++ = i
.prefix
[REX_PREFIX
];
6745 *p
= i
.tm
.base_opcode
;
6747 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
6748 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, size
);
6749 else if (cpu_arch_flags
.bitfield
.cpui386
)
6750 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, size
);
6752 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, size
);
6755 sym
= i
.op
[0].disps
->X_add_symbol
;
6756 off
= i
.op
[0].disps
->X_add_number
;
6758 if (i
.op
[0].disps
->X_op
!= O_constant
6759 && i
.op
[0].disps
->X_op
!= O_symbol
)
6761 /* Handle complex expressions. */
6762 sym
= make_expr_symbol (i
.op
[0].disps
);
6766 /* 1 possible extra opcode + 4 byte displacement go in var part.
6767 Pass reloc in fr_var. */
6768 frag_var (rs_machine_dependent
, 5,
6770 || i
.reloc
[0] != NO_RELOC
6771 || (i
.bnd_prefix
== NULL
&& !add_bnd_prefix
))
6773 : BFD_RELOC_X86_64_PC32_BND
),
6774 subtype
, sym
, off
, p
);
6784 if (i
.tm
.opcode_modifier
.jumpbyte
)
6786 /* This is a loop or jecxz type instruction. */
6788 if (i
.prefix
[ADDR_PREFIX
] != 0)
6790 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
6793 /* Pentium4 branch hints. */
6794 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
6795 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
6797 FRAG_APPEND_1_CHAR (i
.prefix
[SEG_PREFIX
]);
6806 if (flag_code
== CODE_16BIT
)
6809 if (i
.prefix
[DATA_PREFIX
] != 0)
6811 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
6821 if (i
.prefix
[REX_PREFIX
] != 0)
6823 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
6827 /* BND prefixed jump. */
6828 if (i
.prefix
[BND_PREFIX
] != 0)
6830 FRAG_APPEND_1_CHAR (i
.prefix
[BND_PREFIX
]);
6834 if (i
.prefixes
!= 0 && !intel_syntax
)
6835 as_warn (_("skipping prefixes on this instruction"));
6837 p
= frag_more (i
.tm
.opcode_length
+ size
);
6838 switch (i
.tm
.opcode_length
)
6841 *p
++ = i
.tm
.base_opcode
>> 8;
6843 *p
++ = i
.tm
.base_opcode
;
6849 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
6850 i
.op
[0].disps
, 1, reloc (size
, 1, 1,
6851 (i
.bnd_prefix
!= NULL
6855 /* All jumps handled here are signed, but don't use a signed limit
6856 check for 32 and 16 bit jumps as we want to allow wrap around at
6857 4G and 64k respectively. */
6859 fixP
->fx_signed
= 1;
6863 output_interseg_jump (void)
6871 if (flag_code
== CODE_16BIT
)
6875 if (i
.prefix
[DATA_PREFIX
] != 0)
6881 if (i
.prefix
[REX_PREFIX
] != 0)
6891 if (i
.prefixes
!= 0 && !intel_syntax
)
6892 as_warn (_("skipping prefixes on this instruction"));
6894 /* 1 opcode; 2 segment; offset */
6895 p
= frag_more (prefix
+ 1 + 2 + size
);
6897 if (i
.prefix
[DATA_PREFIX
] != 0)
6898 *p
++ = DATA_PREFIX_OPCODE
;
6900 if (i
.prefix
[REX_PREFIX
] != 0)
6901 *p
++ = i
.prefix
[REX_PREFIX
];
6903 *p
++ = i
.tm
.base_opcode
;
6904 if (i
.op
[1].imms
->X_op
== O_constant
)
6906 offsetT n
= i
.op
[1].imms
->X_add_number
;
6909 && !fits_in_unsigned_word (n
)
6910 && !fits_in_signed_word (n
))
6912 as_bad (_("16-bit jump out of range"));
6915 md_number_to_chars (p
, n
, size
);
6918 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
6919 i
.op
[1].imms
, 0, reloc (size
, 0, 0, 0, i
.reloc
[1]));
6920 if (i
.op
[0].imms
->X_op
!= O_constant
)
6921 as_bad (_("can't handle non absolute segment in `%s'"),
6923 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
6929 fragS
*insn_start_frag
;
6930 offsetT insn_start_off
;
6932 /* Tie dwarf2 debug info to the address at the start of the insn.
6933 We can't do this after the insn has been output as the current
6934 frag may have been closed off. eg. by frag_var. */
6935 dwarf2_emit_insn (0);
6937 insn_start_frag
= frag_now
;
6938 insn_start_off
= frag_now_fix ();
6941 if (i
.tm
.opcode_modifier
.jump
)
6943 else if (i
.tm
.opcode_modifier
.jumpbyte
6944 || i
.tm
.opcode_modifier
.jumpdword
)
6946 else if (i
.tm
.opcode_modifier
.jumpintersegment
)
6947 output_interseg_jump ();
6950 /* Output normal instructions here. */
6954 unsigned int prefix
;
6956 /* Some processors fail on LOCK prefix. This options makes
6957 assembler ignore LOCK prefix and serves as a workaround. */
6958 if (omit_lock_prefix
)
6960 if (i
.tm
.base_opcode
== LOCK_PREFIX_OPCODE
)
6962 i
.prefix
[LOCK_PREFIX
] = 0;
6965 /* Since the VEX/EVEX prefix contains the implicit prefix, we
6966 don't need the explicit prefix. */
6967 if (!i
.tm
.opcode_modifier
.vex
&& !i
.tm
.opcode_modifier
.evex
)
6969 switch (i
.tm
.opcode_length
)
6972 if (i
.tm
.base_opcode
& 0xff000000)
6974 prefix
= (i
.tm
.base_opcode
>> 24) & 0xff;
6979 if ((i
.tm
.base_opcode
& 0xff0000) != 0)
6981 prefix
= (i
.tm
.base_opcode
>> 16) & 0xff;
6982 if (i
.tm
.cpu_flags
.bitfield
.cpupadlock
)
6985 if (prefix
!= REPE_PREFIX_OPCODE
6986 || (i
.prefix
[REP_PREFIX
]
6987 != REPE_PREFIX_OPCODE
))
6988 add_prefix (prefix
);
6991 add_prefix (prefix
);
7000 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
7001 R_X86_64_GOTTPOFF relocation so that linker can safely
7002 perform IE->LE optimization. */
7003 if (x86_elf_abi
== X86_64_X32_ABI
7005 && i
.reloc
[0] == BFD_RELOC_X86_64_GOTTPOFF
7006 && i
.prefix
[REX_PREFIX
] == 0)
7007 add_prefix (REX_OPCODE
);
7009 /* The prefix bytes. */
7010 for (j
= ARRAY_SIZE (i
.prefix
), q
= i
.prefix
; j
> 0; j
--, q
++)
7012 FRAG_APPEND_1_CHAR (*q
);
7016 for (j
= 0, q
= i
.prefix
; j
< ARRAY_SIZE (i
.prefix
); j
++, q
++)
7021 /* REX byte is encoded in VEX prefix. */
7025 FRAG_APPEND_1_CHAR (*q
);
7028 /* There should be no other prefixes for instructions
7033 /* For EVEX instructions i.vrex should become 0 after
7034 build_evex_prefix. For VEX instructions upper 16 registers
7035 aren't available, so VREX should be 0. */
7038 /* Now the VEX prefix. */
7039 p
= frag_more (i
.vex
.length
);
7040 for (j
= 0; j
< i
.vex
.length
; j
++)
7041 p
[j
] = i
.vex
.bytes
[j
];
7044 /* Now the opcode; be careful about word order here! */
7045 if (i
.tm
.opcode_length
== 1)
7047 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
7051 switch (i
.tm
.opcode_length
)
7055 *p
++ = (i
.tm
.base_opcode
>> 24) & 0xff;
7056 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
7060 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
7070 /* Put out high byte first: can't use md_number_to_chars! */
7071 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
7072 *p
= i
.tm
.base_opcode
& 0xff;
7075 /* Now the modrm byte and sib byte (if present). */
7076 if (i
.tm
.opcode_modifier
.modrm
)
7078 FRAG_APPEND_1_CHAR ((i
.rm
.regmem
<< 0
7081 /* If i.rm.regmem == ESP (4)
7082 && i.rm.mode != (Register mode)
7084 ==> need second modrm byte. */
7085 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
7087 && !(i
.base_reg
&& i
.base_reg
->reg_type
.bitfield
.reg16
))
7088 FRAG_APPEND_1_CHAR ((i
.sib
.base
<< 0
7090 | i
.sib
.scale
<< 6));
7093 if (i
.disp_operands
)
7094 output_disp (insn_start_frag
, insn_start_off
);
7097 output_imm (insn_start_frag
, insn_start_off
);
7103 pi ("" /*line*/, &i
);
7105 #endif /* DEBUG386 */
7108 /* Return the size of the displacement operand N. */
7111 disp_size (unsigned int n
)
7115 /* Vec_Disp8 has to be 8bit. */
7116 if (i
.types
[n
].bitfield
.vec_disp8
)
7118 else if (i
.types
[n
].bitfield
.disp64
)
7120 else if (i
.types
[n
].bitfield
.disp8
)
7122 else if (i
.types
[n
].bitfield
.disp16
)
7127 /* Return the size of the immediate operand N. */
7130 imm_size (unsigned int n
)
7133 if (i
.types
[n
].bitfield
.imm64
)
7135 else if (i
.types
[n
].bitfield
.imm8
|| i
.types
[n
].bitfield
.imm8s
)
7137 else if (i
.types
[n
].bitfield
.imm16
)
7143 output_disp (fragS
*insn_start_frag
, offsetT insn_start_off
)
7148 for (n
= 0; n
< i
.operands
; n
++)
7150 if (i
.types
[n
].bitfield
.vec_disp8
7151 || operand_type_check (i
.types
[n
], disp
))
7153 if (i
.op
[n
].disps
->X_op
== O_constant
)
7155 int size
= disp_size (n
);
7156 offsetT val
= i
.op
[n
].disps
->X_add_number
;
7158 if (i
.types
[n
].bitfield
.vec_disp8
)
7160 val
= offset_in_range (val
, size
);
7161 p
= frag_more (size
);
7162 md_number_to_chars (p
, val
, size
);
7166 enum bfd_reloc_code_real reloc_type
;
7167 int size
= disp_size (n
);
7168 int sign
= i
.types
[n
].bitfield
.disp32s
;
7169 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
7171 /* We can't have 8 bit displacement here. */
7172 gas_assert (!i
.types
[n
].bitfield
.disp8
);
7174 /* The PC relative address is computed relative
7175 to the instruction boundary, so in case immediate
7176 fields follows, we need to adjust the value. */
7177 if (pcrel
&& i
.imm_operands
)
7182 for (n1
= 0; n1
< i
.operands
; n1
++)
7183 if (operand_type_check (i
.types
[n1
], imm
))
7185 /* Only one immediate is allowed for PC
7186 relative address. */
7187 gas_assert (sz
== 0);
7189 i
.op
[n
].disps
->X_add_number
-= sz
;
7191 /* We should find the immediate. */
7192 gas_assert (sz
!= 0);
7195 p
= frag_more (size
);
7196 reloc_type
= reloc (size
, pcrel
, sign
,
7197 (i
.bnd_prefix
!= NULL
7201 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
7202 && (((reloc_type
== BFD_RELOC_32
7203 || reloc_type
== BFD_RELOC_X86_64_32S
7204 || (reloc_type
== BFD_RELOC_64
7206 && (i
.op
[n
].disps
->X_op
== O_symbol
7207 || (i
.op
[n
].disps
->X_op
== O_add
7208 && ((symbol_get_value_expression
7209 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
7211 || reloc_type
== BFD_RELOC_32_PCREL
))
7215 if (insn_start_frag
== frag_now
)
7216 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
7221 add
= insn_start_frag
->fr_fix
- insn_start_off
;
7222 for (fr
= insn_start_frag
->fr_next
;
7223 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
7225 add
+= p
- frag_now
->fr_literal
;
7230 reloc_type
= BFD_RELOC_386_GOTPC
;
7231 i
.op
[n
].imms
->X_add_number
+= add
;
7233 else if (reloc_type
== BFD_RELOC_64
)
7234 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
7236 /* Don't do the adjustment for x86-64, as there
7237 the pcrel addressing is relative to the _next_
7238 insn, and that is taken care of in other code. */
7239 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
7241 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
7242 i
.op
[n
].disps
, pcrel
, reloc_type
);
7249 output_imm (fragS
*insn_start_frag
, offsetT insn_start_off
)
7254 for (n
= 0; n
< i
.operands
; n
++)
7256 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
7257 if (i
.rounding
&& (int) n
== i
.rounding
->operand
)
7260 if (operand_type_check (i
.types
[n
], imm
))
7262 if (i
.op
[n
].imms
->X_op
== O_constant
)
7264 int size
= imm_size (n
);
7267 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
7269 p
= frag_more (size
);
7270 md_number_to_chars (p
, val
, size
);
7274 /* Not absolute_section.
7275 Need a 32-bit fixup (don't support 8bit
7276 non-absolute imms). Try to support other
7278 enum bfd_reloc_code_real reloc_type
;
7279 int size
= imm_size (n
);
7282 if (i
.types
[n
].bitfield
.imm32s
7283 && (i
.suffix
== QWORD_MNEM_SUFFIX
7284 || (!i
.suffix
&& i
.tm
.opcode_modifier
.no_lsuf
)))
7289 p
= frag_more (size
);
7290 reloc_type
= reloc (size
, 0, sign
, 0, i
.reloc
[n
]);
7292 /* This is tough to explain. We end up with this one if we
7293 * have operands that look like
7294 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
7295 * obtain the absolute address of the GOT, and it is strongly
7296 * preferable from a performance point of view to avoid using
7297 * a runtime relocation for this. The actual sequence of
7298 * instructions often look something like:
7303 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
7305 * The call and pop essentially return the absolute address
7306 * of the label .L66 and store it in %ebx. The linker itself
7307 * will ultimately change the first operand of the addl so
7308 * that %ebx points to the GOT, but to keep things simple, the
7309 * .o file must have this operand set so that it generates not
7310 * the absolute address of .L66, but the absolute address of
7311 * itself. This allows the linker itself simply treat a GOTPC
7312 * relocation as asking for a pcrel offset to the GOT to be
7313 * added in, and the addend of the relocation is stored in the
7314 * operand field for the instruction itself.
7316 * Our job here is to fix the operand so that it would add
7317 * the correct offset so that %ebx would point to itself. The
7318 * thing that is tricky is that .-.L66 will point to the
7319 * beginning of the instruction, so we need to further modify
7320 * the operand so that it will point to itself. There are
7321 * other cases where you have something like:
7323 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
7325 * and here no correction would be required. Internally in
7326 * the assembler we treat operands of this form as not being
7327 * pcrel since the '.' is explicitly mentioned, and I wonder
7328 * whether it would simplify matters to do it this way. Who
7329 * knows. In earlier versions of the PIC patches, the
7330 * pcrel_adjust field was used to store the correction, but
7331 * since the expression is not pcrel, I felt it would be
7332 * confusing to do it this way. */
7334 if ((reloc_type
== BFD_RELOC_32
7335 || reloc_type
== BFD_RELOC_X86_64_32S
7336 || reloc_type
== BFD_RELOC_64
)
7338 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
7339 && (i
.op
[n
].imms
->X_op
== O_symbol
7340 || (i
.op
[n
].imms
->X_op
== O_add
7341 && ((symbol_get_value_expression
7342 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
7347 if (insn_start_frag
== frag_now
)
7348 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
7353 add
= insn_start_frag
->fr_fix
- insn_start_off
;
7354 for (fr
= insn_start_frag
->fr_next
;
7355 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
7357 add
+= p
- frag_now
->fr_literal
;
7361 reloc_type
= BFD_RELOC_386_GOTPC
;
7363 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
7365 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
7366 i
.op
[n
].imms
->X_add_number
+= add
;
7368 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
7369 i
.op
[n
].imms
, 0, reloc_type
);
7375 /* x86_cons_fix_new is called via the expression parsing code when a
7376 reloc is needed. We use this hook to get the correct .got reloc. */
7377 static int cons_sign
= -1;
7380 x86_cons_fix_new (fragS
*frag
, unsigned int off
, unsigned int len
,
7381 expressionS
*exp
, bfd_reloc_code_real_type r
)
7383 r
= reloc (len
, 0, cons_sign
, 0, r
);
7386 if (exp
->X_op
== O_secrel
)
7388 exp
->X_op
= O_symbol
;
7389 r
= BFD_RELOC_32_SECREL
;
7393 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
7396 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
7397 purpose of the `.dc.a' internal pseudo-op. */
7400 x86_address_bytes (void)
7402 if ((stdoutput
->arch_info
->mach
& bfd_mach_x64_32
))
7404 return stdoutput
->arch_info
->bits_per_address
/ 8;
7407 #if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
7409 # define lex_got(reloc, adjust, types, bnd_prefix) NULL
7411 /* Parse operands of the form
7412 <symbol>@GOTOFF+<nnn>
7413 and similar .plt or .got references.
7415 If we find one, set up the correct relocation in RELOC and copy the
7416 input string, minus the `@GOTOFF' into a malloc'd buffer for
7417 parsing by the calling routine. Return this buffer, and if ADJUST
7418 is non-null set it to the length of the string we removed from the
7419 input line. Otherwise return NULL. */
7421 lex_got (enum bfd_reloc_code_real
*rel
,
7423 i386_operand_type
*types
,
7426 /* Some of the relocations depend on the size of what field is to
7427 be relocated. But in our callers i386_immediate and i386_displacement
7428 we don't yet know the operand size (this will be set by insn
7429 matching). Hence we record the word32 relocation here,
7430 and adjust the reloc according to the real size in reloc(). */
7431 static const struct {
7434 const enum bfd_reloc_code_real rel
[2];
7435 const i386_operand_type types64
;
7437 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7438 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32
,
7440 OPERAND_TYPE_IMM32_64
},
7442 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real
,
7443 BFD_RELOC_X86_64_PLTOFF64
},
7444 OPERAND_TYPE_IMM64
},
7445 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32
,
7446 BFD_RELOC_X86_64_PLT32
},
7447 OPERAND_TYPE_IMM32_32S_DISP32
},
7448 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real
,
7449 BFD_RELOC_X86_64_GOTPLT64
},
7450 OPERAND_TYPE_IMM64_DISP64
},
7451 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF
,
7452 BFD_RELOC_X86_64_GOTOFF64
},
7453 OPERAND_TYPE_IMM64_DISP64
},
7454 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real
,
7455 BFD_RELOC_X86_64_GOTPCREL
},
7456 OPERAND_TYPE_IMM32_32S_DISP32
},
7457 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD
,
7458 BFD_RELOC_X86_64_TLSGD
},
7459 OPERAND_TYPE_IMM32_32S_DISP32
},
7460 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM
,
7461 _dummy_first_bfd_reloc_code_real
},
7462 OPERAND_TYPE_NONE
},
7463 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real
,
7464 BFD_RELOC_X86_64_TLSLD
},
7465 OPERAND_TYPE_IMM32_32S_DISP32
},
7466 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32
,
7467 BFD_RELOC_X86_64_GOTTPOFF
},
7468 OPERAND_TYPE_IMM32_32S_DISP32
},
7469 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32
,
7470 BFD_RELOC_X86_64_TPOFF32
},
7471 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
7472 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE
,
7473 _dummy_first_bfd_reloc_code_real
},
7474 OPERAND_TYPE_NONE
},
7475 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32
,
7476 BFD_RELOC_X86_64_DTPOFF32
},
7477 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
7478 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE
,
7479 _dummy_first_bfd_reloc_code_real
},
7480 OPERAND_TYPE_NONE
},
7481 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE
,
7482 _dummy_first_bfd_reloc_code_real
},
7483 OPERAND_TYPE_NONE
},
7484 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32
,
7485 BFD_RELOC_X86_64_GOT32
},
7486 OPERAND_TYPE_IMM32_32S_64_DISP32
},
7487 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC
,
7488 BFD_RELOC_X86_64_GOTPC32_TLSDESC
},
7489 OPERAND_TYPE_IMM32_32S_DISP32
},
7490 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL
,
7491 BFD_RELOC_X86_64_TLSDESC_CALL
},
7492 OPERAND_TYPE_IMM32_32S_DISP32
},
7497 #if defined (OBJ_MAYBE_ELF)
7502 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
7503 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
7506 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
7508 int len
= gotrel
[j
].len
;
7509 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
7511 if (gotrel
[j
].rel
[object_64bit
] != 0)
7514 char *tmpbuf
, *past_reloc
;
7516 *rel
= gotrel
[j
].rel
[object_64bit
];
7520 if (flag_code
!= CODE_64BIT
)
7522 types
->bitfield
.imm32
= 1;
7523 types
->bitfield
.disp32
= 1;
7526 *types
= gotrel
[j
].types64
;
7529 if (j
!= 0 && GOT_symbol
== NULL
)
7530 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
7532 /* The length of the first part of our input line. */
7533 first
= cp
- input_line_pointer
;
7535 /* The second part goes from after the reloc token until
7536 (and including) an end_of_line char or comma. */
7537 past_reloc
= cp
+ 1 + len
;
7539 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
7541 second
= cp
+ 1 - past_reloc
;
7543 /* Allocate and copy string. The trailing NUL shouldn't
7544 be necessary, but be safe. */
7545 tmpbuf
= (char *) xmalloc (first
+ second
+ 2);
7546 memcpy (tmpbuf
, input_line_pointer
, first
);
7547 if (second
!= 0 && *past_reloc
!= ' ')
7548 /* Replace the relocation token with ' ', so that
7549 errors like foo@GOTOFF1 will be detected. */
7550 tmpbuf
[first
++] = ' ';
7552 /* Increment length by 1 if the relocation token is
7557 memcpy (tmpbuf
+ first
, past_reloc
, second
);
7558 tmpbuf
[first
+ second
] = '\0';
7559 if (bnd_prefix
&& *rel
== BFD_RELOC_X86_64_PLT32
)
7560 *rel
= BFD_RELOC_X86_64_PLT32_BND
;
7564 as_bad (_("@%s reloc is not supported with %d-bit output format"),
7565 gotrel
[j
].str
, 1 << (5 + object_64bit
));
7570 /* Might be a symbol version string. Don't as_bad here. */
7579 /* Parse operands of the form
7580 <symbol>@SECREL32+<nnn>
7582 If we find one, set up the correct relocation in RELOC and copy the
7583 input string, minus the `@SECREL32' into a malloc'd buffer for
7584 parsing by the calling routine. Return this buffer, and if ADJUST
7585 is non-null set it to the length of the string we removed from the
7586 input line. Otherwise return NULL.
7588 This function is copied from the ELF version above adjusted for PE targets. */
7591 lex_got (enum bfd_reloc_code_real
*rel ATTRIBUTE_UNUSED
,
7592 int *adjust ATTRIBUTE_UNUSED
,
7593 i386_operand_type
*types
,
7594 int bnd_prefix ATTRIBUTE_UNUSED
)
7600 const enum bfd_reloc_code_real rel
[2];
7601 const i386_operand_type types64
;
7605 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL
,
7606 BFD_RELOC_32_SECREL
},
7607 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
7613 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
7614 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
7617 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
7619 int len
= gotrel
[j
].len
;
7621 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
7623 if (gotrel
[j
].rel
[object_64bit
] != 0)
7626 char *tmpbuf
, *past_reloc
;
7628 *rel
= gotrel
[j
].rel
[object_64bit
];
7634 if (flag_code
!= CODE_64BIT
)
7636 types
->bitfield
.imm32
= 1;
7637 types
->bitfield
.disp32
= 1;
7640 *types
= gotrel
[j
].types64
;
7643 /* The length of the first part of our input line. */
7644 first
= cp
- input_line_pointer
;
7646 /* The second part goes from after the reloc token until
7647 (and including) an end_of_line char or comma. */
7648 past_reloc
= cp
+ 1 + len
;
7650 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
7652 second
= cp
+ 1 - past_reloc
;
7654 /* Allocate and copy string. The trailing NUL shouldn't
7655 be necessary, but be safe. */
7656 tmpbuf
= (char *) xmalloc (first
+ second
+ 2);
7657 memcpy (tmpbuf
, input_line_pointer
, first
);
7658 if (second
!= 0 && *past_reloc
!= ' ')
7659 /* Replace the relocation token with ' ', so that
7660 errors like foo@SECLREL321 will be detected. */
7661 tmpbuf
[first
++] = ' ';
7662 memcpy (tmpbuf
+ first
, past_reloc
, second
);
7663 tmpbuf
[first
+ second
] = '\0';
7667 as_bad (_("@%s reloc is not supported with %d-bit output format"),
7668 gotrel
[j
].str
, 1 << (5 + object_64bit
));
7673 /* Might be a symbol version string. Don't as_bad here. */
7679 bfd_reloc_code_real_type
7680 x86_cons (expressionS
*exp
, int size
)
7682 bfd_reloc_code_real_type got_reloc
= NO_RELOC
;
7684 intel_syntax
= -intel_syntax
;
7687 if (size
== 4 || (object_64bit
&& size
== 8))
7689 /* Handle @GOTOFF and the like in an expression. */
7691 char *gotfree_input_line
;
7694 save
= input_line_pointer
;
7695 gotfree_input_line
= lex_got (&got_reloc
, &adjust
, NULL
, 0);
7696 if (gotfree_input_line
)
7697 input_line_pointer
= gotfree_input_line
;
7701 if (gotfree_input_line
)
7703 /* expression () has merrily parsed up to the end of line,
7704 or a comma - in the wrong buffer. Transfer how far
7705 input_line_pointer has moved to the right buffer. */
7706 input_line_pointer
= (save
7707 + (input_line_pointer
- gotfree_input_line
)
7709 free (gotfree_input_line
);
7710 if (exp
->X_op
== O_constant
7711 || exp
->X_op
== O_absent
7712 || exp
->X_op
== O_illegal
7713 || exp
->X_op
== O_register
7714 || exp
->X_op
== O_big
)
7716 char c
= *input_line_pointer
;
7717 *input_line_pointer
= 0;
7718 as_bad (_("missing or invalid expression `%s'"), save
);
7719 *input_line_pointer
= c
;
7726 intel_syntax
= -intel_syntax
;
7729 i386_intel_simplify (exp
);
7735 signed_cons (int size
)
7737 if (flag_code
== CODE_64BIT
)
7745 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
7752 if (exp
.X_op
== O_symbol
)
7753 exp
.X_op
= O_secrel
;
7755 emit_expr (&exp
, 4);
7757 while (*input_line_pointer
++ == ',');
7759 input_line_pointer
--;
7760 demand_empty_rest_of_line ();
7764 /* Handle Vector operations. */
7767 check_VecOperations (char *op_string
, char *op_end
)
7769 const reg_entry
*mask
;
7774 && (op_end
== NULL
|| op_string
< op_end
))
7777 if (*op_string
== '{')
7781 /* Check broadcasts. */
7782 if (strncmp (op_string
, "1to", 3) == 0)
7787 goto duplicated_vec_op
;
7790 if (*op_string
== '8')
7791 bcst_type
= BROADCAST_1TO8
;
7792 else if (*op_string
== '4')
7793 bcst_type
= BROADCAST_1TO4
;
7794 else if (*op_string
== '2')
7795 bcst_type
= BROADCAST_1TO2
;
7796 else if (*op_string
== '1'
7797 && *(op_string
+1) == '6')
7799 bcst_type
= BROADCAST_1TO16
;
7804 as_bad (_("Unsupported broadcast: `%s'"), saved
);
7809 broadcast_op
.type
= bcst_type
;
7810 broadcast_op
.operand
= this_operand
;
7811 i
.broadcast
= &broadcast_op
;
7813 /* Check masking operation. */
7814 else if ((mask
= parse_register (op_string
, &end_op
)) != NULL
)
7816 /* k0 can't be used for write mask. */
7817 if (mask
->reg_num
== 0)
7819 as_bad (_("`%s' can't be used for write mask"),
7826 mask_op
.mask
= mask
;
7827 mask_op
.zeroing
= 0;
7828 mask_op
.operand
= this_operand
;
7834 goto duplicated_vec_op
;
7836 i
.mask
->mask
= mask
;
7838 /* Only "{z}" is allowed here. No need to check
7839 zeroing mask explicitly. */
7840 if (i
.mask
->operand
!= this_operand
)
7842 as_bad (_("invalid write mask `%s'"), saved
);
7849 /* Check zeroing-flag for masking operation. */
7850 else if (*op_string
== 'z')
7854 mask_op
.mask
= NULL
;
7855 mask_op
.zeroing
= 1;
7856 mask_op
.operand
= this_operand
;
7861 if (i
.mask
->zeroing
)
7864 as_bad (_("duplicated `%s'"), saved
);
7868 i
.mask
->zeroing
= 1;
7870 /* Only "{%k}" is allowed here. No need to check mask
7871 register explicitly. */
7872 if (i
.mask
->operand
!= this_operand
)
7874 as_bad (_("invalid zeroing-masking `%s'"),
7883 goto unknown_vec_op
;
7885 if (*op_string
!= '}')
7887 as_bad (_("missing `}' in `%s'"), saved
);
7894 /* We don't know this one. */
7895 as_bad (_("unknown vector operation: `%s'"), saved
);
7903 i386_immediate (char *imm_start
)
7905 char *save_input_line_pointer
;
7906 char *gotfree_input_line
;
7909 i386_operand_type types
;
7911 operand_type_set (&types
, ~0);
7913 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
7915 as_bad (_("at most %d immediate operands are allowed"),
7916 MAX_IMMEDIATE_OPERANDS
);
7920 exp
= &im_expressions
[i
.imm_operands
++];
7921 i
.op
[this_operand
].imms
= exp
;
7923 if (is_space_char (*imm_start
))
7926 save_input_line_pointer
= input_line_pointer
;
7927 input_line_pointer
= imm_start
;
7929 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
,
7930 (i
.bnd_prefix
!= NULL
7931 || add_bnd_prefix
));
7932 if (gotfree_input_line
)
7933 input_line_pointer
= gotfree_input_line
;
7935 exp_seg
= expression (exp
);
7939 /* Handle vector operations. */
7940 if (*input_line_pointer
== '{')
7942 input_line_pointer
= check_VecOperations (input_line_pointer
,
7944 if (input_line_pointer
== NULL
)
7948 if (*input_line_pointer
)
7949 as_bad (_("junk `%s' after expression"), input_line_pointer
);
7951 input_line_pointer
= save_input_line_pointer
;
7952 if (gotfree_input_line
)
7954 free (gotfree_input_line
);
7956 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
7957 exp
->X_op
= O_illegal
;
7960 return i386_finalize_immediate (exp_seg
, exp
, types
, imm_start
);
7964 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
7965 i386_operand_type types
, const char *imm_start
)
7967 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_illegal
|| exp
->X_op
== O_big
)
7970 as_bad (_("missing or invalid immediate expression `%s'"),
7974 else if (exp
->X_op
== O_constant
)
7976 /* Size it properly later. */
7977 i
.types
[this_operand
].bitfield
.imm64
= 1;
7978 /* If not 64bit, sign extend val. */
7979 if (flag_code
!= CODE_64BIT
7980 && (exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
7982 = (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
7984 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
7985 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
7986 && exp_seg
!= absolute_section
7987 && exp_seg
!= text_section
7988 && exp_seg
!= data_section
7989 && exp_seg
!= bss_section
7990 && exp_seg
!= undefined_section
7991 && !bfd_is_com_section (exp_seg
))
7993 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
7997 else if (!intel_syntax
&& exp_seg
== reg_section
)
8000 as_bad (_("illegal immediate register operand %s"), imm_start
);
8005 /* This is an address. The size of the address will be
8006 determined later, depending on destination register,
8007 suffix, or the default for the section. */
8008 i
.types
[this_operand
].bitfield
.imm8
= 1;
8009 i
.types
[this_operand
].bitfield
.imm16
= 1;
8010 i
.types
[this_operand
].bitfield
.imm32
= 1;
8011 i
.types
[this_operand
].bitfield
.imm32s
= 1;
8012 i
.types
[this_operand
].bitfield
.imm64
= 1;
8013 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
8021 i386_scale (char *scale
)
8024 char *save
= input_line_pointer
;
8026 input_line_pointer
= scale
;
8027 val
= get_absolute_expression ();
8032 i
.log2_scale_factor
= 0;
8035 i
.log2_scale_factor
= 1;
8038 i
.log2_scale_factor
= 2;
8041 i
.log2_scale_factor
= 3;
8045 char sep
= *input_line_pointer
;
8047 *input_line_pointer
= '\0';
8048 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
8050 *input_line_pointer
= sep
;
8051 input_line_pointer
= save
;
8055 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
8057 as_warn (_("scale factor of %d without an index register"),
8058 1 << i
.log2_scale_factor
);
8059 i
.log2_scale_factor
= 0;
8061 scale
= input_line_pointer
;
8062 input_line_pointer
= save
;
8067 i386_displacement (char *disp_start
, char *disp_end
)
8071 char *save_input_line_pointer
;
8072 char *gotfree_input_line
;
8074 i386_operand_type bigdisp
, types
= anydisp
;
8077 if (i
.disp_operands
== MAX_MEMORY_OPERANDS
)
8079 as_bad (_("at most %d displacement operands are allowed"),
8080 MAX_MEMORY_OPERANDS
);
8084 operand_type_set (&bigdisp
, 0);
8085 if ((i
.types
[this_operand
].bitfield
.jumpabsolute
)
8086 || (!current_templates
->start
->opcode_modifier
.jump
8087 && !current_templates
->start
->opcode_modifier
.jumpdword
))
8089 bigdisp
.bitfield
.disp32
= 1;
8090 override
= (i
.prefix
[ADDR_PREFIX
] != 0);
8091 if (flag_code
== CODE_64BIT
)
8095 bigdisp
.bitfield
.disp32s
= 1;
8096 bigdisp
.bitfield
.disp64
= 1;
8099 else if ((flag_code
== CODE_16BIT
) ^ override
)
8101 bigdisp
.bitfield
.disp32
= 0;
8102 bigdisp
.bitfield
.disp16
= 1;
8107 /* For PC-relative branches, the width of the displacement
8108 is dependent upon data size, not address size. */
8109 override
= (i
.prefix
[DATA_PREFIX
] != 0);
8110 if (flag_code
== CODE_64BIT
)
8112 if (override
|| i
.suffix
== WORD_MNEM_SUFFIX
)
8113 bigdisp
.bitfield
.disp16
= 1;
8116 bigdisp
.bitfield
.disp32
= 1;
8117 bigdisp
.bitfield
.disp32s
= 1;
8123 override
= (i
.suffix
== (flag_code
!= CODE_16BIT
8125 : LONG_MNEM_SUFFIX
));
8126 bigdisp
.bitfield
.disp32
= 1;
8127 if ((flag_code
== CODE_16BIT
) ^ override
)
8129 bigdisp
.bitfield
.disp32
= 0;
8130 bigdisp
.bitfield
.disp16
= 1;
8134 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
8137 exp
= &disp_expressions
[i
.disp_operands
];
8138 i
.op
[this_operand
].disps
= exp
;
8140 save_input_line_pointer
= input_line_pointer
;
8141 input_line_pointer
= disp_start
;
8142 END_STRING_AND_SAVE (disp_end
);
8144 #ifndef GCC_ASM_O_HACK
8145 #define GCC_ASM_O_HACK 0
8148 END_STRING_AND_SAVE (disp_end
+ 1);
8149 if (i
.types
[this_operand
].bitfield
.baseIndex
8150 && displacement_string_end
[-1] == '+')
8152 /* This hack is to avoid a warning when using the "o"
8153 constraint within gcc asm statements.
8156 #define _set_tssldt_desc(n,addr,limit,type) \
8157 __asm__ __volatile__ ( \
8159 "movw %w1,2+%0\n\t" \
8161 "movb %b1,4+%0\n\t" \
8162 "movb %4,5+%0\n\t" \
8163 "movb $0,6+%0\n\t" \
8164 "movb %h1,7+%0\n\t" \
8166 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
8168 This works great except that the output assembler ends
8169 up looking a bit weird if it turns out that there is
8170 no offset. You end up producing code that looks like:
8183 So here we provide the missing zero. */
8185 *displacement_string_end
= '0';
8188 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
,
8189 (i
.bnd_prefix
!= NULL
8190 || add_bnd_prefix
));
8191 if (gotfree_input_line
)
8192 input_line_pointer
= gotfree_input_line
;
8194 exp_seg
= expression (exp
);
8197 if (*input_line_pointer
)
8198 as_bad (_("junk `%s' after expression"), input_line_pointer
);
8200 RESTORE_END_STRING (disp_end
+ 1);
8202 input_line_pointer
= save_input_line_pointer
;
8203 if (gotfree_input_line
)
8205 free (gotfree_input_line
);
8207 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
8208 exp
->X_op
= O_illegal
;
8211 ret
= i386_finalize_displacement (exp_seg
, exp
, types
, disp_start
);
8213 RESTORE_END_STRING (disp_end
);
8219 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
8220 i386_operand_type types
, const char *disp_start
)
8222 i386_operand_type bigdisp
;
8225 /* We do this to make sure that the section symbol is in
8226 the symbol table. We will ultimately change the relocation
8227 to be relative to the beginning of the section. */
8228 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
8229 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
8230 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
8232 if (exp
->X_op
!= O_symbol
)
8235 if (S_IS_LOCAL (exp
->X_add_symbol
)
8236 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
8237 && S_GET_SEGMENT (exp
->X_add_symbol
) != expr_section
)
8238 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
8239 exp
->X_op
= O_subtract
;
8240 exp
->X_op_symbol
= GOT_symbol
;
8241 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
8242 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
8243 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
8244 i
.reloc
[this_operand
] = BFD_RELOC_64
;
8246 i
.reloc
[this_operand
] = BFD_RELOC_32
;
8249 else if (exp
->X_op
== O_absent
8250 || exp
->X_op
== O_illegal
8251 || exp
->X_op
== O_big
)
8254 as_bad (_("missing or invalid displacement expression `%s'"),
8259 else if (flag_code
== CODE_64BIT
8260 && !i
.prefix
[ADDR_PREFIX
]
8261 && exp
->X_op
== O_constant
)
8263 /* Since displacement is signed extended to 64bit, don't allow
8264 disp32 and turn off disp32s if they are out of range. */
8265 i
.types
[this_operand
].bitfield
.disp32
= 0;
8266 if (!fits_in_signed_long (exp
->X_add_number
))
8268 i
.types
[this_operand
].bitfield
.disp32s
= 0;
8269 if (i
.types
[this_operand
].bitfield
.baseindex
)
8271 as_bad (_("0x%lx out range of signed 32bit displacement"),
8272 (long) exp
->X_add_number
);
8278 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8279 else if (exp
->X_op
!= O_constant
8280 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
8281 && exp_seg
!= absolute_section
8282 && exp_seg
!= text_section
8283 && exp_seg
!= data_section
8284 && exp_seg
!= bss_section
8285 && exp_seg
!= undefined_section
8286 && !bfd_is_com_section (exp_seg
))
8288 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
8293 /* Check if this is a displacement only operand. */
8294 bigdisp
= i
.types
[this_operand
];
8295 bigdisp
.bitfield
.disp8
= 0;
8296 bigdisp
.bitfield
.disp16
= 0;
8297 bigdisp
.bitfield
.disp32
= 0;
8298 bigdisp
.bitfield
.disp32s
= 0;
8299 bigdisp
.bitfield
.disp64
= 0;
8300 if (operand_type_all_zero (&bigdisp
))
8301 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
8307 /* Make sure the memory operand we've been dealt is valid.
8308 Return 1 on success, 0 on a failure. */
8311 i386_index_check (const char *operand_string
)
8313 const char *kind
= "base/index";
8314 enum flag_code addr_mode
;
8316 if (i
.prefix
[ADDR_PREFIX
])
8317 addr_mode
= flag_code
== CODE_32BIT
? CODE_16BIT
: CODE_32BIT
;
8320 addr_mode
= flag_code
;
8322 #if INFER_ADDR_PREFIX
8323 if (i
.mem_operands
== 0)
8325 /* Infer address prefix from the first memory operand. */
8326 const reg_entry
*addr_reg
= i
.base_reg
;
8328 if (addr_reg
== NULL
)
8329 addr_reg
= i
.index_reg
;
8333 if (addr_reg
->reg_num
== RegEip
8334 || addr_reg
->reg_num
== RegEiz
8335 || addr_reg
->reg_type
.bitfield
.reg32
)
8336 addr_mode
= CODE_32BIT
;
8337 else if (flag_code
!= CODE_64BIT
8338 && addr_reg
->reg_type
.bitfield
.reg16
)
8339 addr_mode
= CODE_16BIT
;
8341 if (addr_mode
!= flag_code
)
8343 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
8345 /* Change the size of any displacement too. At most one
8346 of Disp16 or Disp32 is set.
8347 FIXME. There doesn't seem to be any real need for
8348 separate Disp16 and Disp32 flags. The same goes for
8349 Imm16 and Imm32. Removing them would probably clean
8350 up the code quite a lot. */
8351 if (flag_code
!= CODE_64BIT
8352 && (i
.types
[this_operand
].bitfield
.disp16
8353 || i
.types
[this_operand
].bitfield
.disp32
))
8354 i
.types
[this_operand
]
8355 = operand_type_xor (i
.types
[this_operand
], disp16_32
);
8362 if (current_templates
->start
->opcode_modifier
.isstring
8363 && !current_templates
->start
->opcode_modifier
.immext
8364 && (current_templates
->end
[-1].opcode_modifier
.isstring
8367 /* Memory operands of string insns are special in that they only allow
8368 a single register (rDI, rSI, or rBX) as their memory address. */
8369 const reg_entry
*expected_reg
;
8370 static const char *di_si
[][2] =
8376 static const char *bx
[] = { "ebx", "bx", "rbx" };
8378 kind
= "string address";
8380 if (current_templates
->start
->opcode_modifier
.w
)
8382 i386_operand_type type
= current_templates
->end
[-1].operand_types
[0];
8384 if (!type
.bitfield
.baseindex
8385 || ((!i
.mem_operands
!= !intel_syntax
)
8386 && current_templates
->end
[-1].operand_types
[1]
8387 .bitfield
.baseindex
))
8388 type
= current_templates
->end
[-1].operand_types
[1];
8389 expected_reg
= hash_find (reg_hash
,
8390 di_si
[addr_mode
][type
.bitfield
.esseg
]);
8394 expected_reg
= hash_find (reg_hash
, bx
[addr_mode
]);
8396 if (i
.base_reg
!= expected_reg
8398 || operand_type_check (i
.types
[this_operand
], disp
))
8400 /* The second memory operand must have the same size as
8404 && !((addr_mode
== CODE_64BIT
8405 && i
.base_reg
->reg_type
.bitfield
.reg64
)
8406 || (addr_mode
== CODE_32BIT
8407 ? i
.base_reg
->reg_type
.bitfield
.reg32
8408 : i
.base_reg
->reg_type
.bitfield
.reg16
)))
8411 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
8413 intel_syntax
? '[' : '(',
8415 expected_reg
->reg_name
,
8416 intel_syntax
? ']' : ')');
8423 as_bad (_("`%s' is not a valid %s expression"),
8424 operand_string
, kind
);
8429 if (addr_mode
!= CODE_16BIT
)
8431 /* 32-bit/64-bit checks. */
8433 && (addr_mode
== CODE_64BIT
8434 ? !i
.base_reg
->reg_type
.bitfield
.reg64
8435 : !i
.base_reg
->reg_type
.bitfield
.reg32
)
8437 || (i
.base_reg
->reg_num
8438 != (addr_mode
== CODE_64BIT
? RegRip
: RegEip
))))
8440 && !i
.index_reg
->reg_type
.bitfield
.regxmm
8441 && !i
.index_reg
->reg_type
.bitfield
.regymm
8442 && !i
.index_reg
->reg_type
.bitfield
.regzmm
8443 && ((addr_mode
== CODE_64BIT
8444 ? !(i
.index_reg
->reg_type
.bitfield
.reg64
8445 || i
.index_reg
->reg_num
== RegRiz
)
8446 : !(i
.index_reg
->reg_type
.bitfield
.reg32
8447 || i
.index_reg
->reg_num
== RegEiz
))
8448 || !i
.index_reg
->reg_type
.bitfield
.baseindex
)))
8453 /* 16-bit checks. */
8455 && (!i
.base_reg
->reg_type
.bitfield
.reg16
8456 || !i
.base_reg
->reg_type
.bitfield
.baseindex
))
8458 && (!i
.index_reg
->reg_type
.bitfield
.reg16
8459 || !i
.index_reg
->reg_type
.bitfield
.baseindex
8461 && i
.base_reg
->reg_num
< 6
8462 && i
.index_reg
->reg_num
>= 6
8463 && i
.log2_scale_factor
== 0))))
8470 /* Handle vector immediates. */
8473 RC_SAE_immediate (const char *imm_start
)
8475 unsigned int match_found
, j
;
8476 const char *pstr
= imm_start
;
8484 for (j
= 0; j
< ARRAY_SIZE (RC_NamesTable
); j
++)
8486 if (!strncmp (pstr
, RC_NamesTable
[j
].name
, RC_NamesTable
[j
].len
))
8490 rc_op
.type
= RC_NamesTable
[j
].type
;
8491 rc_op
.operand
= this_operand
;
8492 i
.rounding
= &rc_op
;
8496 as_bad (_("duplicated `%s'"), imm_start
);
8499 pstr
+= RC_NamesTable
[j
].len
;
8509 as_bad (_("Missing '}': '%s'"), imm_start
);
8512 /* RC/SAE immediate string should contain nothing more. */;
8515 as_bad (_("Junk after '}': '%s'"), imm_start
);
8519 exp
= &im_expressions
[i
.imm_operands
++];
8520 i
.op
[this_operand
].imms
= exp
;
8522 exp
->X_op
= O_constant
;
8523 exp
->X_add_number
= 0;
8524 exp
->X_add_symbol
= (symbolS
*) 0;
8525 exp
->X_op_symbol
= (symbolS
*) 0;
8527 i
.types
[this_operand
].bitfield
.imm8
= 1;
8531 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
8535 i386_att_operand (char *operand_string
)
8539 char *op_string
= operand_string
;
8541 if (is_space_char (*op_string
))
8544 /* We check for an absolute prefix (differentiating,
8545 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
8546 if (*op_string
== ABSOLUTE_PREFIX
)
8549 if (is_space_char (*op_string
))
8551 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
8554 /* Check if operand is a register. */
8555 if ((r
= parse_register (op_string
, &end_op
)) != NULL
)
8557 i386_operand_type temp
;
8559 /* Check for a segment override by searching for ':' after a
8560 segment register. */
8562 if (is_space_char (*op_string
))
8564 if (*op_string
== ':'
8565 && (r
->reg_type
.bitfield
.sreg2
8566 || r
->reg_type
.bitfield
.sreg3
))
8571 i
.seg
[i
.mem_operands
] = &es
;
8574 i
.seg
[i
.mem_operands
] = &cs
;
8577 i
.seg
[i
.mem_operands
] = &ss
;
8580 i
.seg
[i
.mem_operands
] = &ds
;
8583 i
.seg
[i
.mem_operands
] = &fs
;
8586 i
.seg
[i
.mem_operands
] = &gs
;
8590 /* Skip the ':' and whitespace. */
8592 if (is_space_char (*op_string
))
8595 if (!is_digit_char (*op_string
)
8596 && !is_identifier_char (*op_string
)
8597 && *op_string
!= '('
8598 && *op_string
!= ABSOLUTE_PREFIX
)
8600 as_bad (_("bad memory operand `%s'"), op_string
);
8603 /* Handle case of %es:*foo. */
8604 if (*op_string
== ABSOLUTE_PREFIX
)
8607 if (is_space_char (*op_string
))
8609 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
8611 goto do_memory_reference
;
8614 /* Handle vector operations. */
8615 if (*op_string
== '{')
8617 op_string
= check_VecOperations (op_string
, NULL
);
8618 if (op_string
== NULL
)
8624 as_bad (_("junk `%s' after register"), op_string
);
8628 temp
.bitfield
.baseindex
= 0;
8629 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
8631 i
.types
[this_operand
].bitfield
.unspecified
= 0;
8632 i
.op
[this_operand
].regs
= r
;
8635 else if (*op_string
== REGISTER_PREFIX
)
8637 as_bad (_("bad register name `%s'"), op_string
);
8640 else if (*op_string
== IMMEDIATE_PREFIX
)
8643 if (i
.types
[this_operand
].bitfield
.jumpabsolute
)
8645 as_bad (_("immediate operand illegal with absolute jump"));
8648 if (!i386_immediate (op_string
))
8651 else if (RC_SAE_immediate (operand_string
))
8653 /* If it is a RC or SAE immediate, do nothing. */
8656 else if (is_digit_char (*op_string
)
8657 || is_identifier_char (*op_string
)
8658 || *op_string
== '(')
8660 /* This is a memory reference of some sort. */
8663 /* Start and end of displacement string expression (if found). */
8664 char *displacement_string_start
;
8665 char *displacement_string_end
;
8668 do_memory_reference
:
8669 if ((i
.mem_operands
== 1
8670 && !current_templates
->start
->opcode_modifier
.isstring
)
8671 || i
.mem_operands
== 2)
8673 as_bad (_("too many memory references for `%s'"),
8674 current_templates
->start
->name
);
8678 /* Check for base index form. We detect the base index form by
8679 looking for an ')' at the end of the operand, searching
8680 for the '(' matching it, and finding a REGISTER_PREFIX or ','
8682 base_string
= op_string
+ strlen (op_string
);
8684 /* Handle vector operations. */
8685 vop_start
= strchr (op_string
, '{');
8686 if (vop_start
&& vop_start
< base_string
)
8688 if (check_VecOperations (vop_start
, base_string
) == NULL
)
8690 base_string
= vop_start
;
8694 if (is_space_char (*base_string
))
8697 /* If we only have a displacement, set-up for it to be parsed later. */
8698 displacement_string_start
= op_string
;
8699 displacement_string_end
= base_string
+ 1;
8701 if (*base_string
== ')')
8704 unsigned int parens_balanced
= 1;
8705 /* We've already checked that the number of left & right ()'s are
8706 equal, so this loop will not be infinite. */
8710 if (*base_string
== ')')
8712 if (*base_string
== '(')
8715 while (parens_balanced
);
8717 temp_string
= base_string
;
8719 /* Skip past '(' and whitespace. */
8721 if (is_space_char (*base_string
))
8724 if (*base_string
== ','
8725 || ((i
.base_reg
= parse_register (base_string
, &end_op
))
8728 displacement_string_end
= temp_string
;
8730 i
.types
[this_operand
].bitfield
.baseindex
= 1;
8734 base_string
= end_op
;
8735 if (is_space_char (*base_string
))
8739 /* There may be an index reg or scale factor here. */
8740 if (*base_string
== ',')
8743 if (is_space_char (*base_string
))
8746 if ((i
.index_reg
= parse_register (base_string
, &end_op
))
8749 base_string
= end_op
;
8750 if (is_space_char (*base_string
))
8752 if (*base_string
== ',')
8755 if (is_space_char (*base_string
))
8758 else if (*base_string
!= ')')
8760 as_bad (_("expecting `,' or `)' "
8761 "after index register in `%s'"),
8766 else if (*base_string
== REGISTER_PREFIX
)
8768 end_op
= strchr (base_string
, ',');
8771 as_bad (_("bad register name `%s'"), base_string
);
8775 /* Check for scale factor. */
8776 if (*base_string
!= ')')
8778 char *end_scale
= i386_scale (base_string
);
8783 base_string
= end_scale
;
8784 if (is_space_char (*base_string
))
8786 if (*base_string
!= ')')
8788 as_bad (_("expecting `)' "
8789 "after scale factor in `%s'"),
8794 else if (!i
.index_reg
)
8796 as_bad (_("expecting index register or scale factor "
8797 "after `,'; got '%c'"),
8802 else if (*base_string
!= ')')
8804 as_bad (_("expecting `,' or `)' "
8805 "after base register in `%s'"),
8810 else if (*base_string
== REGISTER_PREFIX
)
8812 end_op
= strchr (base_string
, ',');
8815 as_bad (_("bad register name `%s'"), base_string
);
8820 /* If there's an expression beginning the operand, parse it,
8821 assuming displacement_string_start and
8822 displacement_string_end are meaningful. */
8823 if (displacement_string_start
!= displacement_string_end
)
8825 if (!i386_displacement (displacement_string_start
,
8826 displacement_string_end
))
8830 /* Special case for (%dx) while doing input/output op. */
8832 && operand_type_equal (&i
.base_reg
->reg_type
,
8833 ®16_inoutportreg
)
8835 && i
.log2_scale_factor
== 0
8836 && i
.seg
[i
.mem_operands
] == 0
8837 && !operand_type_check (i
.types
[this_operand
], disp
))
8839 i
.types
[this_operand
] = inoutportreg
;
8843 if (i386_index_check (operand_string
) == 0)
8845 i
.types
[this_operand
].bitfield
.mem
= 1;
8850 /* It's not a memory operand; argh! */
8851 as_bad (_("invalid char %s beginning operand %d `%s'"),
8852 output_invalid (*op_string
),
8857 return 1; /* Normal return. */
8860 /* Calculate the maximum variable size (i.e., excluding fr_fix)
8861 that an rs_machine_dependent frag may reach. */
8864 i386_frag_max_var (fragS
*frag
)
8866 /* The only relaxable frags are for jumps.
8867 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
8868 gas_assert (frag
->fr_type
== rs_machine_dependent
);
8869 return TYPE_FROM_RELAX_STATE (frag
->fr_subtype
) == UNCOND_JUMP
? 4 : 5;
8872 /* md_estimate_size_before_relax()
8874 Called just before relax() for rs_machine_dependent frags. The x86
8875 assembler uses these frags to handle variable size jump
8878 Any symbol that is now undefined will not become defined.
8879 Return the correct fr_subtype in the frag.
8880 Return the initial "guess for variable size of frag" to caller.
8881 The guess is actually the growth beyond the fixed part. Whatever
8882 we do to grow the fixed or variable part contributes to our
8886 md_estimate_size_before_relax (fragS
*fragP
, segT segment
)
8888 /* We've already got fragP->fr_subtype right; all we have to do is
8889 check for un-relaxable symbols. On an ELF system, we can't relax
8890 an externally visible symbol, because it may be overridden by a
8892 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
8893 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8895 && (S_IS_EXTERNAL (fragP
->fr_symbol
)
8896 || S_IS_WEAK (fragP
->fr_symbol
)
8897 || ((symbol_get_bfdsym (fragP
->fr_symbol
)->flags
8898 & BSF_GNU_INDIRECT_FUNCTION
))))
8900 #if defined (OBJ_COFF) && defined (TE_PE)
8901 || (OUTPUT_FLAVOR
== bfd_target_coff_flavour
8902 && S_IS_WEAK (fragP
->fr_symbol
))
8906 /* Symbol is undefined in this segment, or we need to keep a
8907 reloc so that weak symbols can be overridden. */
8908 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
8909 enum bfd_reloc_code_real reloc_type
;
8910 unsigned char *opcode
;
8913 if (fragP
->fr_var
!= NO_RELOC
)
8914 reloc_type
= (enum bfd_reloc_code_real
) fragP
->fr_var
;
8916 reloc_type
= BFD_RELOC_16_PCREL
;
8918 reloc_type
= BFD_RELOC_32_PCREL
;
8920 old_fr_fix
= fragP
->fr_fix
;
8921 opcode
= (unsigned char *) fragP
->fr_opcode
;
8923 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
8926 /* Make jmp (0xeb) a (d)word displacement jump. */
8928 fragP
->fr_fix
+= size
;
8929 fix_new (fragP
, old_fr_fix
, size
,
8931 fragP
->fr_offset
, 1,
8937 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
8939 /* Negate the condition, and branch past an
8940 unconditional jump. */
8943 /* Insert an unconditional jump. */
8945 /* We added two extra opcode bytes, and have a two byte
8947 fragP
->fr_fix
+= 2 + 2;
8948 fix_new (fragP
, old_fr_fix
+ 2, 2,
8950 fragP
->fr_offset
, 1,
8957 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
8962 fixP
= fix_new (fragP
, old_fr_fix
, 1,
8964 fragP
->fr_offset
, 1,
8966 fixP
->fx_signed
= 1;
8970 /* This changes the byte-displacement jump 0x7N
8971 to the (d)word-displacement jump 0x0f,0x8N. */
8972 opcode
[1] = opcode
[0] + 0x10;
8973 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
8974 /* We've added an opcode byte. */
8975 fragP
->fr_fix
+= 1 + size
;
8976 fix_new (fragP
, old_fr_fix
+ 1, size
,
8978 fragP
->fr_offset
, 1,
8983 BAD_CASE (fragP
->fr_subtype
);
8987 return fragP
->fr_fix
- old_fr_fix
;
8990 /* Guess size depending on current relax state. Initially the relax
8991 state will correspond to a short jump and we return 1, because
8992 the variable part of the frag (the branch offset) is one byte
8993 long. However, we can relax a section more than once and in that
8994 case we must either set fr_subtype back to the unrelaxed state,
8995 or return the value for the appropriate branch. */
8996 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
8999 /* Called after relax() is finished.
9001 In: Address of frag.
9002 fr_type == rs_machine_dependent.
9003 fr_subtype is what the address relaxed to.
9005 Out: Any fixSs and constants are set up.
9006 Caller will turn frag into a ".space 0". */
9009 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec ATTRIBUTE_UNUSED
,
9012 unsigned char *opcode
;
9013 unsigned char *where_to_put_displacement
= NULL
;
9014 offsetT target_address
;
9015 offsetT opcode_address
;
9016 unsigned int extension
= 0;
9017 offsetT displacement_from_opcode_start
;
9019 opcode
= (unsigned char *) fragP
->fr_opcode
;
9021 /* Address we want to reach in file space. */
9022 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
9024 /* Address opcode resides at in file space. */
9025 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
9027 /* Displacement from opcode start to fill into instruction. */
9028 displacement_from_opcode_start
= target_address
- opcode_address
;
9030 if ((fragP
->fr_subtype
& BIG
) == 0)
9032 /* Don't have to change opcode. */
9033 extension
= 1; /* 1 opcode + 1 displacement */
9034 where_to_put_displacement
= &opcode
[1];
9038 if (no_cond_jump_promotion
9039 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
9040 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
9041 _("long jump required"));
9043 switch (fragP
->fr_subtype
)
9045 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
9046 extension
= 4; /* 1 opcode + 4 displacement */
9048 where_to_put_displacement
= &opcode
[1];
9051 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
9052 extension
= 2; /* 1 opcode + 2 displacement */
9054 where_to_put_displacement
= &opcode
[1];
9057 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
9058 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
9059 extension
= 5; /* 2 opcode + 4 displacement */
9060 opcode
[1] = opcode
[0] + 0x10;
9061 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
9062 where_to_put_displacement
= &opcode
[2];
9065 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
9066 extension
= 3; /* 2 opcode + 2 displacement */
9067 opcode
[1] = opcode
[0] + 0x10;
9068 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
9069 where_to_put_displacement
= &opcode
[2];
9072 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
9077 where_to_put_displacement
= &opcode
[3];
9081 BAD_CASE (fragP
->fr_subtype
);
9086 /* If size if less then four we are sure that the operand fits,
9087 but if it's 4, then it could be that the displacement is larger
9089 if (DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
) == 4
9091 && ((addressT
) (displacement_from_opcode_start
- extension
9092 + ((addressT
) 1 << 31))
9093 > (((addressT
) 2 << 31) - 1)))
9095 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
9096 _("jump target out of range"));
9097 /* Make us emit 0. */
9098 displacement_from_opcode_start
= extension
;
9100 /* Now put displacement after opcode. */
9101 md_number_to_chars ((char *) where_to_put_displacement
,
9102 (valueT
) (displacement_from_opcode_start
- extension
),
9103 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
9104 fragP
->fr_fix
+= extension
;
9107 /* Apply a fixup (fixP) to segment data, once it has been determined
9108 by our caller that we have all the info we need to fix it up.
9110 Parameter valP is the pointer to the value of the bits.
9112 On the 386, immediates, displacements, and data pointers are all in
9113 the same (little-endian) format, so we don't need to care about which
9117 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
9119 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
9120 valueT value
= *valP
;
9122 #if !defined (TE_Mach)
9125 switch (fixP
->fx_r_type
)
9131 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
9134 case BFD_RELOC_X86_64_32S
:
9135 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
9138 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
9141 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
9146 if (fixP
->fx_addsy
!= NULL
9147 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
9148 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
9149 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
9150 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
9151 || fixP
->fx_r_type
== BFD_RELOC_X86_64_PC32_BND
)
9152 && !use_rela_relocations
)
9154 /* This is a hack. There should be a better way to handle this.
9155 This covers for the fact that bfd_install_relocation will
9156 subtract the current location (for partial_inplace, PC relative
9157 relocations); see more below. */
9161 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
9164 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
9166 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9169 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
9172 || (symbol_section_p (fixP
->fx_addsy
)
9173 && sym_seg
!= absolute_section
))
9174 && !generic_force_reloc (fixP
))
9176 /* Yes, we add the values in twice. This is because
9177 bfd_install_relocation subtracts them out again. I think
9178 bfd_install_relocation is broken, but I don't dare change
9180 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
9184 #if defined (OBJ_COFF) && defined (TE_PE)
9185 /* For some reason, the PE format does not store a
9186 section address offset for a PC relative symbol. */
9187 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
9188 || S_IS_WEAK (fixP
->fx_addsy
))
9189 value
+= md_pcrel_from (fixP
);
9192 #if defined (OBJ_COFF) && defined (TE_PE)
9193 if (fixP
->fx_addsy
!= NULL
9194 && S_IS_WEAK (fixP
->fx_addsy
)
9195 /* PR 16858: Do not modify weak function references. */
9196 && ! fixP
->fx_pcrel
)
9198 #if !defined (TE_PEP)
9199 /* For x86 PE weak function symbols are neither PC-relative
9200 nor do they set S_IS_FUNCTION. So the only reliable way
9201 to detect them is to check the flags of their containing
9203 if (S_GET_SEGMENT (fixP
->fx_addsy
) != NULL
9204 && S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_CODE
)
9208 value
-= S_GET_VALUE (fixP
->fx_addsy
);
9212 /* Fix a few things - the dynamic linker expects certain values here,
9213 and we must not disappoint it. */
9214 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9215 if (IS_ELF
&& fixP
->fx_addsy
)
9216 switch (fixP
->fx_r_type
)
9218 case BFD_RELOC_386_PLT32
:
9219 case BFD_RELOC_X86_64_PLT32
:
9220 case BFD_RELOC_X86_64_PLT32_BND
:
9221 /* Make the jump instruction point to the address of the operand. At
9222 runtime we merely add the offset to the actual PLT entry. */
9226 case BFD_RELOC_386_TLS_GD
:
9227 case BFD_RELOC_386_TLS_LDM
:
9228 case BFD_RELOC_386_TLS_IE_32
:
9229 case BFD_RELOC_386_TLS_IE
:
9230 case BFD_RELOC_386_TLS_GOTIE
:
9231 case BFD_RELOC_386_TLS_GOTDESC
:
9232 case BFD_RELOC_X86_64_TLSGD
:
9233 case BFD_RELOC_X86_64_TLSLD
:
9234 case BFD_RELOC_X86_64_GOTTPOFF
:
9235 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
9236 value
= 0; /* Fully resolved at runtime. No addend. */
9238 case BFD_RELOC_386_TLS_LE
:
9239 case BFD_RELOC_386_TLS_LDO_32
:
9240 case BFD_RELOC_386_TLS_LE_32
:
9241 case BFD_RELOC_X86_64_DTPOFF32
:
9242 case BFD_RELOC_X86_64_DTPOFF64
:
9243 case BFD_RELOC_X86_64_TPOFF32
:
9244 case BFD_RELOC_X86_64_TPOFF64
:
9245 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
9248 case BFD_RELOC_386_TLS_DESC_CALL
:
9249 case BFD_RELOC_X86_64_TLSDESC_CALL
:
9250 value
= 0; /* Fully resolved at runtime. No addend. */
9251 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
9255 case BFD_RELOC_386_GOT32
:
9256 case BFD_RELOC_X86_64_GOT32
:
9257 value
= 0; /* Fully resolved at runtime. No addend. */
9260 case BFD_RELOC_VTABLE_INHERIT
:
9261 case BFD_RELOC_VTABLE_ENTRY
:
9268 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
9270 #endif /* !defined (TE_Mach) */
9272 /* Are we finished with this relocation now? */
9273 if (fixP
->fx_addsy
== NULL
)
9275 #if defined (OBJ_COFF) && defined (TE_PE)
9276 else if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
9279 /* Remember value for tc_gen_reloc. */
9280 fixP
->fx_addnumber
= value
;
9281 /* Clear out the frag for now. */
9285 else if (use_rela_relocations
)
9287 fixP
->fx_no_overflow
= 1;
9288 /* Remember value for tc_gen_reloc. */
9289 fixP
->fx_addnumber
= value
;
9293 md_number_to_chars (p
, value
, fixP
->fx_size
);
9297 md_atof (int type
, char *litP
, int *sizeP
)
9299 /* This outputs the LITTLENUMs in REVERSE order;
9300 in accord with the bigendian 386. */
9301 return ieee_md_atof (type
, litP
, sizeP
, FALSE
);
9304 static char output_invalid_buf
[sizeof (unsigned char) * 2 + 6];
9307 output_invalid (int c
)
9310 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
9313 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
9314 "(0x%x)", (unsigned char) c
);
9315 return output_invalid_buf
;
9318 /* REG_STRING starts *before* REGISTER_PREFIX. */
9320 static const reg_entry
*
9321 parse_real_register (char *reg_string
, char **end_op
)
9323 char *s
= reg_string
;
9325 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
9328 /* Skip possible REGISTER_PREFIX and possible whitespace. */
9329 if (*s
== REGISTER_PREFIX
)
9332 if (is_space_char (*s
))
9336 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
9338 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
9339 return (const reg_entry
*) NULL
;
9343 /* For naked regs, make sure that we are not dealing with an identifier.
9344 This prevents confusing an identifier like `eax_var' with register
9346 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
9347 return (const reg_entry
*) NULL
;
9351 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
9353 /* Handle floating point regs, allowing spaces in the (i) part. */
9354 if (r
== i386_regtab
/* %st is first entry of table */)
9356 if (is_space_char (*s
))
9361 if (is_space_char (*s
))
9363 if (*s
>= '0' && *s
<= '7')
9367 if (is_space_char (*s
))
9372 r
= (const reg_entry
*) hash_find (reg_hash
, "st(0)");
9377 /* We have "%st(" then garbage. */
9378 return (const reg_entry
*) NULL
;
9382 if (r
== NULL
|| allow_pseudo_reg
)
9385 if (operand_type_all_zero (&r
->reg_type
))
9386 return (const reg_entry
*) NULL
;
9388 if ((r
->reg_type
.bitfield
.reg32
9389 || r
->reg_type
.bitfield
.sreg3
9390 || r
->reg_type
.bitfield
.control
9391 || r
->reg_type
.bitfield
.debug
9392 || r
->reg_type
.bitfield
.test
)
9393 && !cpu_arch_flags
.bitfield
.cpui386
)
9394 return (const reg_entry
*) NULL
;
9396 if (r
->reg_type
.bitfield
.floatreg
9397 && !cpu_arch_flags
.bitfield
.cpu8087
9398 && !cpu_arch_flags
.bitfield
.cpu287
9399 && !cpu_arch_flags
.bitfield
.cpu387
)
9400 return (const reg_entry
*) NULL
;
9402 if (r
->reg_type
.bitfield
.regmmx
&& !cpu_arch_flags
.bitfield
.cpummx
)
9403 return (const reg_entry
*) NULL
;
9405 if (r
->reg_type
.bitfield
.regxmm
&& !cpu_arch_flags
.bitfield
.cpusse
)
9406 return (const reg_entry
*) NULL
;
9408 if (r
->reg_type
.bitfield
.regymm
&& !cpu_arch_flags
.bitfield
.cpuavx
)
9409 return (const reg_entry
*) NULL
;
9411 if ((r
->reg_type
.bitfield
.regzmm
|| r
->reg_type
.bitfield
.regmask
)
9412 && !cpu_arch_flags
.bitfield
.cpuavx512f
)
9413 return (const reg_entry
*) NULL
;
9415 /* Don't allow fake index register unless allow_index_reg isn't 0. */
9416 if (!allow_index_reg
9417 && (r
->reg_num
== RegEiz
|| r
->reg_num
== RegRiz
))
9418 return (const reg_entry
*) NULL
;
9420 /* Upper 16 vector register is only available with VREX in 64bit
9422 if ((r
->reg_flags
& RegVRex
))
9424 if (!cpu_arch_flags
.bitfield
.cpuvrex
9425 || flag_code
!= CODE_64BIT
)
9426 return (const reg_entry
*) NULL
;
9431 if (((r
->reg_flags
& (RegRex64
| RegRex
))
9432 || r
->reg_type
.bitfield
.reg64
)
9433 && (!cpu_arch_flags
.bitfield
.cpulm
9434 || !operand_type_equal (&r
->reg_type
, &control
))
9435 && flag_code
!= CODE_64BIT
)
9436 return (const reg_entry
*) NULL
;
9438 if (r
->reg_type
.bitfield
.sreg3
&& r
->reg_num
== RegFlat
&& !intel_syntax
)
9439 return (const reg_entry
*) NULL
;
9444 /* REG_STRING starts *before* REGISTER_PREFIX. */
9446 static const reg_entry
*
9447 parse_register (char *reg_string
, char **end_op
)
9451 if (*reg_string
== REGISTER_PREFIX
|| allow_naked_reg
)
9452 r
= parse_real_register (reg_string
, end_op
);
9457 char *save
= input_line_pointer
;
9461 input_line_pointer
= reg_string
;
9462 c
= get_symbol_end ();
9463 symbolP
= symbol_find (reg_string
);
9464 if (symbolP
&& S_GET_SEGMENT (symbolP
) == reg_section
)
9466 const expressionS
*e
= symbol_get_value_expression (symbolP
);
9468 know (e
->X_op
== O_register
);
9469 know (e
->X_add_number
>= 0
9470 && (valueT
) e
->X_add_number
< i386_regtab_size
);
9471 r
= i386_regtab
+ e
->X_add_number
;
9472 if ((r
->reg_flags
& RegVRex
))
9474 *end_op
= input_line_pointer
;
9476 *input_line_pointer
= c
;
9477 input_line_pointer
= save
;
9483 i386_parse_name (char *name
, expressionS
*e
, char *nextcharP
)
9486 char *end
= input_line_pointer
;
9489 r
= parse_register (name
, &input_line_pointer
);
9490 if (r
&& end
<= input_line_pointer
)
9492 *nextcharP
= *input_line_pointer
;
9493 *input_line_pointer
= 0;
9494 e
->X_op
= O_register
;
9495 e
->X_add_number
= r
- i386_regtab
;
9498 input_line_pointer
= end
;
9500 return intel_syntax
? i386_intel_parse_name (name
, e
) : 0;
9504 md_operand (expressionS
*e
)
9509 switch (*input_line_pointer
)
9511 case REGISTER_PREFIX
:
9512 r
= parse_real_register (input_line_pointer
, &end
);
9515 e
->X_op
= O_register
;
9516 e
->X_add_number
= r
- i386_regtab
;
9517 input_line_pointer
= end
;
9522 gas_assert (intel_syntax
);
9523 end
= input_line_pointer
++;
9525 if (*input_line_pointer
== ']')
9527 ++input_line_pointer
;
9528 e
->X_op_symbol
= make_expr_symbol (e
);
9529 e
->X_add_symbol
= NULL
;
9530 e
->X_add_number
= 0;
9536 input_line_pointer
= end
;
9543 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9544 const char *md_shortopts
= "kVQ:sqn";
9546 const char *md_shortopts
= "qn";
9549 #define OPTION_32 (OPTION_MD_BASE + 0)
9550 #define OPTION_64 (OPTION_MD_BASE + 1)
9551 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
9552 #define OPTION_MARCH (OPTION_MD_BASE + 3)
9553 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
9554 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
9555 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
9556 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
9557 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
9558 #define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
9559 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
9560 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
9561 #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
9562 #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
9563 #define OPTION_X32 (OPTION_MD_BASE + 14)
9564 #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
9565 #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
9566 #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
9567 #define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
9568 #define OPTION_OMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
9569 #define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
9571 struct option md_longopts
[] =
9573 {"32", no_argument
, NULL
, OPTION_32
},
9574 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
9575 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
9576 {"64", no_argument
, NULL
, OPTION_64
},
9578 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9579 {"x32", no_argument
, NULL
, OPTION_X32
},
9581 {"divide", no_argument
, NULL
, OPTION_DIVIDE
},
9582 {"march", required_argument
, NULL
, OPTION_MARCH
},
9583 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
9584 {"mmnemonic", required_argument
, NULL
, OPTION_MMNEMONIC
},
9585 {"msyntax", required_argument
, NULL
, OPTION_MSYNTAX
},
9586 {"mindex-reg", no_argument
, NULL
, OPTION_MINDEX_REG
},
9587 {"mnaked-reg", no_argument
, NULL
, OPTION_MNAKED_REG
},
9588 {"mold-gcc", no_argument
, NULL
, OPTION_MOLD_GCC
},
9589 {"msse2avx", no_argument
, NULL
, OPTION_MSSE2AVX
},
9590 {"msse-check", required_argument
, NULL
, OPTION_MSSE_CHECK
},
9591 {"moperand-check", required_argument
, NULL
, OPTION_MOPERAND_CHECK
},
9592 {"mavxscalar", required_argument
, NULL
, OPTION_MAVXSCALAR
},
9593 {"madd-bnd-prefix", no_argument
, NULL
, OPTION_MADD_BND_PREFIX
},
9594 {"mevexlig", required_argument
, NULL
, OPTION_MEVEXLIG
},
9595 {"mevexwig", required_argument
, NULL
, OPTION_MEVEXWIG
},
9596 # if defined (TE_PE) || defined (TE_PEP)
9597 {"mbig-obj", no_argument
, NULL
, OPTION_MBIG_OBJ
},
9599 {"momit-lock-prefix", required_argument
, NULL
, OPTION_OMIT_LOCK_PREFIX
},
9600 {"mevexrcig", required_argument
, NULL
, OPTION_MEVEXRCIG
},
9601 {NULL
, no_argument
, NULL
, 0}
9603 size_t md_longopts_size
= sizeof (md_longopts
);
9606 md_parse_option (int c
, char *arg
)
9614 optimize_align_code
= 0;
9621 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9622 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
9623 should be emitted or not. FIXME: Not implemented. */
9627 /* -V: SVR4 argument to print version ID. */
9629 print_version_id ();
9632 /* -k: Ignore for FreeBSD compatibility. */
9637 /* -s: On i386 Solaris, this tells the native assembler to use
9638 .stab instead of .stab.excl. We always use .stab anyhow. */
9641 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
9642 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
9645 const char **list
, **l
;
9647 list
= bfd_target_list ();
9648 for (l
= list
; *l
!= NULL
; l
++)
9649 if (CONST_STRNEQ (*l
, "elf64-x86-64")
9650 || strcmp (*l
, "coff-x86-64") == 0
9651 || strcmp (*l
, "pe-x86-64") == 0
9652 || strcmp (*l
, "pei-x86-64") == 0
9653 || strcmp (*l
, "mach-o-x86-64") == 0)
9655 default_arch
= "x86_64";
9659 as_fatal (_("no compiled in support for x86_64"));
9665 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9669 const char **list
, **l
;
9671 list
= bfd_target_list ();
9672 for (l
= list
; *l
!= NULL
; l
++)
9673 if (CONST_STRNEQ (*l
, "elf32-x86-64"))
9675 default_arch
= "x86_64:32";
9679 as_fatal (_("no compiled in support for 32bit x86_64"));
9683 as_fatal (_("32bit x86_64 is only supported for ELF"));
9688 default_arch
= "i386";
9692 #ifdef SVR4_COMMENT_CHARS
9697 n
= (char *) xmalloc (strlen (i386_comment_chars
) + 1);
9699 for (s
= i386_comment_chars
; *s
!= '\0'; s
++)
9703 i386_comment_chars
= n
;
9709 arch
= xstrdup (arg
);
9713 as_fatal (_("invalid -march= option: `%s'"), arg
);
9714 next
= strchr (arch
, '+');
9717 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
9719 if (strcmp (arch
, cpu_arch
[j
].name
) == 0)
9722 if (! cpu_arch
[j
].flags
.bitfield
.cpui386
)
9725 cpu_arch_name
= cpu_arch
[j
].name
;
9726 cpu_sub_arch_name
= NULL
;
9727 cpu_arch_flags
= cpu_arch
[j
].flags
;
9728 cpu_arch_isa
= cpu_arch
[j
].type
;
9729 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
9730 if (!cpu_arch_tune_set
)
9732 cpu_arch_tune
= cpu_arch_isa
;
9733 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
9737 else if (*cpu_arch
[j
].name
== '.'
9738 && strcmp (arch
, cpu_arch
[j
].name
+ 1) == 0)
9740 /* ISA entension. */
9741 i386_cpu_flags flags
;
9743 if (!cpu_arch
[j
].negated
)
9744 flags
= cpu_flags_or (cpu_arch_flags
,
9747 flags
= cpu_flags_and_not (cpu_arch_flags
,
9749 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
9751 if (cpu_sub_arch_name
)
9753 char *name
= cpu_sub_arch_name
;
9754 cpu_sub_arch_name
= concat (name
,
9756 (const char *) NULL
);
9760 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
9761 cpu_arch_flags
= flags
;
9762 cpu_arch_isa_flags
= flags
;
9768 if (j
>= ARRAY_SIZE (cpu_arch
))
9769 as_fatal (_("invalid -march= option: `%s'"), arg
);
9773 while (next
!= NULL
);
9778 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
9779 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
9781 if (strcmp (arg
, cpu_arch
[j
].name
) == 0)
9783 cpu_arch_tune_set
= 1;
9784 cpu_arch_tune
= cpu_arch
[j
].type
;
9785 cpu_arch_tune_flags
= cpu_arch
[j
].flags
;
9789 if (j
>= ARRAY_SIZE (cpu_arch
))
9790 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
9793 case OPTION_MMNEMONIC
:
9794 if (strcasecmp (arg
, "att") == 0)
9796 else if (strcasecmp (arg
, "intel") == 0)
9799 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg
);
9802 case OPTION_MSYNTAX
:
9803 if (strcasecmp (arg
, "att") == 0)
9805 else if (strcasecmp (arg
, "intel") == 0)
9808 as_fatal (_("invalid -msyntax= option: `%s'"), arg
);
9811 case OPTION_MINDEX_REG
:
9812 allow_index_reg
= 1;
9815 case OPTION_MNAKED_REG
:
9816 allow_naked_reg
= 1;
9819 case OPTION_MOLD_GCC
:
9823 case OPTION_MSSE2AVX
:
9827 case OPTION_MSSE_CHECK
:
9828 if (strcasecmp (arg
, "error") == 0)
9829 sse_check
= check_error
;
9830 else if (strcasecmp (arg
, "warning") == 0)
9831 sse_check
= check_warning
;
9832 else if (strcasecmp (arg
, "none") == 0)
9833 sse_check
= check_none
;
9835 as_fatal (_("invalid -msse-check= option: `%s'"), arg
);
9838 case OPTION_MOPERAND_CHECK
:
9839 if (strcasecmp (arg
, "error") == 0)
9840 operand_check
= check_error
;
9841 else if (strcasecmp (arg
, "warning") == 0)
9842 operand_check
= check_warning
;
9843 else if (strcasecmp (arg
, "none") == 0)
9844 operand_check
= check_none
;
9846 as_fatal (_("invalid -moperand-check= option: `%s'"), arg
);
9849 case OPTION_MAVXSCALAR
:
9850 if (strcasecmp (arg
, "128") == 0)
9852 else if (strcasecmp (arg
, "256") == 0)
9855 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg
);
9858 case OPTION_MADD_BND_PREFIX
:
9862 case OPTION_MEVEXLIG
:
9863 if (strcmp (arg
, "128") == 0)
9865 else if (strcmp (arg
, "256") == 0)
9867 else if (strcmp (arg
, "512") == 0)
9870 as_fatal (_("invalid -mevexlig= option: `%s'"), arg
);
9873 case OPTION_MEVEXRCIG
:
9874 if (strcmp (arg
, "rne") == 0)
9876 else if (strcmp (arg
, "rd") == 0)
9878 else if (strcmp (arg
, "ru") == 0)
9880 else if (strcmp (arg
, "rz") == 0)
9883 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg
);
9886 case OPTION_MEVEXWIG
:
9887 if (strcmp (arg
, "0") == 0)
9889 else if (strcmp (arg
, "1") == 0)
9892 as_fatal (_("invalid -mevexwig= option: `%s'"), arg
);
9895 # if defined (TE_PE) || defined (TE_PEP)
9896 case OPTION_MBIG_OBJ
:
9901 case OPTION_OMIT_LOCK_PREFIX
:
9902 if (strcasecmp (arg
, "yes") == 0)
9903 omit_lock_prefix
= 1;
9904 else if (strcasecmp (arg
, "no") == 0)
9905 omit_lock_prefix
= 0;
9907 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg
);
9916 #define MESSAGE_TEMPLATE \
9920 show_arch (FILE *stream
, int ext
, int check
)
9922 static char message
[] = MESSAGE_TEMPLATE
;
9923 char *start
= message
+ 27;
9925 int size
= sizeof (MESSAGE_TEMPLATE
);
9932 left
= size
- (start
- message
);
9933 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
9935 /* Should it be skipped? */
9936 if (cpu_arch
[j
].skip
)
9939 name
= cpu_arch
[j
].name
;
9940 len
= cpu_arch
[j
].len
;
9943 /* It is an extension. Skip if we aren't asked to show it. */
9954 /* It is an processor. Skip if we show only extension. */
9957 else if (check
&& ! cpu_arch
[j
].flags
.bitfield
.cpui386
)
9959 /* It is an impossible processor - skip. */
9963 /* Reserve 2 spaces for ", " or ",\0" */
9966 /* Check if there is any room. */
9974 p
= mempcpy (p
, name
, len
);
9978 /* Output the current message now and start a new one. */
9981 fprintf (stream
, "%s\n", message
);
9983 left
= size
- (start
- message
) - len
- 2;
9985 gas_assert (left
>= 0);
9987 p
= mempcpy (p
, name
, len
);
9992 fprintf (stream
, "%s\n", message
);
9996 md_show_usage (FILE *stream
)
9998 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9999 fprintf (stream
, _("\
10001 -V print assembler version number\n\
10004 fprintf (stream
, _("\
10005 -n Do not optimize code alignment\n\
10006 -q quieten some warnings\n"));
10007 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10008 fprintf (stream
, _("\
10011 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10012 || defined (TE_PE) || defined (TE_PEP))
10013 fprintf (stream
, _("\
10014 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
10016 #ifdef SVR4_COMMENT_CHARS
10017 fprintf (stream
, _("\
10018 --divide do not treat `/' as a comment character\n"));
10020 fprintf (stream
, _("\
10021 --divide ignored\n"));
10023 fprintf (stream
, _("\
10024 -march=CPU[,+EXTENSION...]\n\
10025 generate code for CPU and EXTENSION, CPU is one of:\n"));
10026 show_arch (stream
, 0, 1);
10027 fprintf (stream
, _("\
10028 EXTENSION is combination of:\n"));
10029 show_arch (stream
, 1, 0);
10030 fprintf (stream
, _("\
10031 -mtune=CPU optimize for CPU, CPU is one of:\n"));
10032 show_arch (stream
, 0, 0);
10033 fprintf (stream
, _("\
10034 -msse2avx encode SSE instructions with VEX prefix\n"));
10035 fprintf (stream
, _("\
10036 -msse-check=[none|error|warning]\n\
10037 check SSE instructions\n"));
10038 fprintf (stream
, _("\
10039 -moperand-check=[none|error|warning]\n\
10040 check operand combinations for validity\n"));
10041 fprintf (stream
, _("\
10042 -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n\
10044 fprintf (stream
, _("\
10045 -mevexlig=[128|256|512] encode scalar EVEX instructions with specific vector\n\
10047 fprintf (stream
, _("\
10048 -mevexwig=[0|1] encode EVEX instructions with specific EVEX.W value\n\
10049 for EVEX.W bit ignored instructions\n"));
10050 fprintf (stream
, _("\
10051 -mevexrcig=[rne|rd|ru|rz]\n\
10052 encode EVEX instructions with specific EVEX.RC value\n\
10053 for SAE-only ignored instructions\n"));
10054 fprintf (stream
, _("\
10055 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
10056 fprintf (stream
, _("\
10057 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
10058 fprintf (stream
, _("\
10059 -mindex-reg support pseudo index registers\n"));
10060 fprintf (stream
, _("\
10061 -mnaked-reg don't require `%%' prefix for registers\n"));
10062 fprintf (stream
, _("\
10063 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
10064 fprintf (stream
, _("\
10065 -madd-bnd-prefix add BND prefix for all valid branches\n"));
10066 # if defined (TE_PE) || defined (TE_PEP)
10067 fprintf (stream
, _("\
10068 -mbig-obj generate big object files\n"));
10070 fprintf (stream
, _("\
10071 -momit-lock-prefix=[no|yes]\n\
10072 strip all lock prefixes\n"));
10075 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
10076 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10077 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
10079 /* Pick the target format to use. */
10082 i386_target_format (void)
10084 if (!strncmp (default_arch
, "x86_64", 6))
10086 update_code_flag (CODE_64BIT
, 1);
10087 if (default_arch
[6] == '\0')
10088 x86_elf_abi
= X86_64_ABI
;
10090 x86_elf_abi
= X86_64_X32_ABI
;
10092 else if (!strcmp (default_arch
, "i386"))
10093 update_code_flag (CODE_32BIT
, 1);
10095 as_fatal (_("unknown architecture"));
10097 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
10098 cpu_arch_isa_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
10099 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
10100 cpu_arch_tune_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
10102 switch (OUTPUT_FLAVOR
)
10104 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
10105 case bfd_target_aout_flavour
:
10106 return AOUT_TARGET_FORMAT
;
10108 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
10109 # if defined (TE_PE) || defined (TE_PEP)
10110 case bfd_target_coff_flavour
:
10111 if (flag_code
== CODE_64BIT
)
10112 return use_big_obj
? "pe-bigobj-x86-64" : "pe-x86-64";
10115 # elif defined (TE_GO32)
10116 case bfd_target_coff_flavour
:
10117 return "coff-go32";
10119 case bfd_target_coff_flavour
:
10120 return "coff-i386";
10123 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
10124 case bfd_target_elf_flavour
:
10126 const char *format
;
10128 switch (x86_elf_abi
)
10131 format
= ELF_TARGET_FORMAT
;
10134 use_rela_relocations
= 1;
10136 format
= ELF_TARGET_FORMAT64
;
10138 case X86_64_X32_ABI
:
10139 use_rela_relocations
= 1;
10141 disallow_64bit_reloc
= 1;
10142 format
= ELF_TARGET_FORMAT32
;
10145 if (cpu_arch_isa
== PROCESSOR_L1OM
)
10147 if (x86_elf_abi
!= X86_64_ABI
)
10148 as_fatal (_("Intel L1OM is 64bit only"));
10149 return ELF_TARGET_L1OM_FORMAT
;
10151 if (cpu_arch_isa
== PROCESSOR_K1OM
)
10153 if (x86_elf_abi
!= X86_64_ABI
)
10154 as_fatal (_("Intel K1OM is 64bit only"));
10155 return ELF_TARGET_K1OM_FORMAT
;
10161 #if defined (OBJ_MACH_O)
10162 case bfd_target_mach_o_flavour
:
10163 if (flag_code
== CODE_64BIT
)
10165 use_rela_relocations
= 1;
10167 return "mach-o-x86-64";
10170 return "mach-o-i386";
10178 #endif /* OBJ_MAYBE_ more than one */
10180 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
10182 i386_elf_emit_arch_note (void)
10184 if (IS_ELF
&& cpu_arch_name
!= NULL
)
10187 asection
*seg
= now_seg
;
10188 subsegT subseg
= now_subseg
;
10189 Elf_Internal_Note i_note
;
10190 Elf_External_Note e_note
;
10191 asection
*note_secp
;
10194 /* Create the .note section. */
10195 note_secp
= subseg_new (".note", 0);
10196 bfd_set_section_flags (stdoutput
,
10198 SEC_HAS_CONTENTS
| SEC_READONLY
);
10200 /* Process the arch string. */
10201 len
= strlen (cpu_arch_name
);
10203 i_note
.namesz
= len
+ 1;
10205 i_note
.type
= NT_ARCH
;
10206 p
= frag_more (sizeof (e_note
.namesz
));
10207 md_number_to_chars (p
, (valueT
) i_note
.namesz
, sizeof (e_note
.namesz
));
10208 p
= frag_more (sizeof (e_note
.descsz
));
10209 md_number_to_chars (p
, (valueT
) i_note
.descsz
, sizeof (e_note
.descsz
));
10210 p
= frag_more (sizeof (e_note
.type
));
10211 md_number_to_chars (p
, (valueT
) i_note
.type
, sizeof (e_note
.type
));
10212 p
= frag_more (len
+ 1);
10213 strcpy (p
, cpu_arch_name
);
10215 frag_align (2, 0, 0);
10217 subseg_set (seg
, subseg
);
10223 md_undefined_symbol (char *name
)
10225 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
10226 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
10227 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
10228 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
10232 if (symbol_find (name
))
10233 as_bad (_("GOT already in symbol table"));
10234 GOT_symbol
= symbol_new (name
, undefined_section
,
10235 (valueT
) 0, &zero_address_frag
);
10242 /* Round up a section size to the appropriate boundary. */
10245 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
10247 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
10248 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
10250 /* For a.out, force the section size to be aligned. If we don't do
10251 this, BFD will align it for us, but it will not write out the
10252 final bytes of the section. This may be a bug in BFD, but it is
10253 easier to fix it here since that is how the other a.out targets
10257 align
= bfd_get_section_alignment (stdoutput
, segment
);
10258 size
= ((size
+ (1 << align
) - 1) & ((valueT
) -1 << align
));
10265 /* On the i386, PC-relative offsets are relative to the start of the
10266 next instruction. That is, the address of the offset, plus its
10267 size, since the offset is always the last part of the insn. */
10270 md_pcrel_from (fixS
*fixP
)
10272 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
10278 s_bss (int ignore ATTRIBUTE_UNUSED
)
10282 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10284 obj_elf_section_change_hook ();
10286 temp
= get_absolute_expression ();
10287 subseg_set (bss_section
, (subsegT
) temp
);
10288 demand_empty_rest_of_line ();
10294 i386_validate_fix (fixS
*fixp
)
10296 if (fixp
->fx_subsy
&& fixp
->fx_subsy
== GOT_symbol
)
10298 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
10302 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
10307 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
10309 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
10311 fixp
->fx_subsy
= 0;
10316 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
10319 bfd_reloc_code_real_type code
;
10321 switch (fixp
->fx_r_type
)
10323 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10324 case BFD_RELOC_SIZE32
:
10325 case BFD_RELOC_SIZE64
:
10326 if (S_IS_DEFINED (fixp
->fx_addsy
)
10327 && !S_IS_EXTERNAL (fixp
->fx_addsy
))
10329 /* Resolve size relocation against local symbol to size of
10330 the symbol plus addend. */
10331 valueT value
= S_GET_SIZE (fixp
->fx_addsy
) + fixp
->fx_offset
;
10332 if (fixp
->fx_r_type
== BFD_RELOC_SIZE32
10333 && !fits_in_unsigned_long (value
))
10334 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10335 _("symbol size computation overflow"));
10336 fixp
->fx_addsy
= NULL
;
10337 fixp
->fx_subsy
= NULL
;
10338 md_apply_fix (fixp
, (valueT
*) &value
, NULL
);
10343 case BFD_RELOC_X86_64_PLT32
:
10344 case BFD_RELOC_X86_64_PLT32_BND
:
10345 case BFD_RELOC_X86_64_GOT32
:
10346 case BFD_RELOC_X86_64_GOTPCREL
:
10347 case BFD_RELOC_386_PLT32
:
10348 case BFD_RELOC_386_GOT32
:
10349 case BFD_RELOC_386_GOTOFF
:
10350 case BFD_RELOC_386_GOTPC
:
10351 case BFD_RELOC_386_TLS_GD
:
10352 case BFD_RELOC_386_TLS_LDM
:
10353 case BFD_RELOC_386_TLS_LDO_32
:
10354 case BFD_RELOC_386_TLS_IE_32
:
10355 case BFD_RELOC_386_TLS_IE
:
10356 case BFD_RELOC_386_TLS_GOTIE
:
10357 case BFD_RELOC_386_TLS_LE_32
:
10358 case BFD_RELOC_386_TLS_LE
:
10359 case BFD_RELOC_386_TLS_GOTDESC
:
10360 case BFD_RELOC_386_TLS_DESC_CALL
:
10361 case BFD_RELOC_X86_64_TLSGD
:
10362 case BFD_RELOC_X86_64_TLSLD
:
10363 case BFD_RELOC_X86_64_DTPOFF32
:
10364 case BFD_RELOC_X86_64_DTPOFF64
:
10365 case BFD_RELOC_X86_64_GOTTPOFF
:
10366 case BFD_RELOC_X86_64_TPOFF32
:
10367 case BFD_RELOC_X86_64_TPOFF64
:
10368 case BFD_RELOC_X86_64_GOTOFF64
:
10369 case BFD_RELOC_X86_64_GOTPC32
:
10370 case BFD_RELOC_X86_64_GOT64
:
10371 case BFD_RELOC_X86_64_GOTPCREL64
:
10372 case BFD_RELOC_X86_64_GOTPC64
:
10373 case BFD_RELOC_X86_64_GOTPLT64
:
10374 case BFD_RELOC_X86_64_PLTOFF64
:
10375 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
10376 case BFD_RELOC_X86_64_TLSDESC_CALL
:
10377 case BFD_RELOC_RVA
:
10378 case BFD_RELOC_VTABLE_ENTRY
:
10379 case BFD_RELOC_VTABLE_INHERIT
:
10381 case BFD_RELOC_32_SECREL
:
10383 code
= fixp
->fx_r_type
;
10385 case BFD_RELOC_X86_64_32S
:
10386 if (!fixp
->fx_pcrel
)
10388 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
10389 code
= fixp
->fx_r_type
;
10393 if (fixp
->fx_pcrel
)
10395 switch (fixp
->fx_size
)
10398 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10399 _("can not do %d byte pc-relative relocation"),
10401 code
= BFD_RELOC_32_PCREL
;
10403 case 1: code
= BFD_RELOC_8_PCREL
; break;
10404 case 2: code
= BFD_RELOC_16_PCREL
; break;
10406 code
= (fixp
->fx_r_type
== BFD_RELOC_X86_64_PC32_BND
10407 ? fixp
-> fx_r_type
: BFD_RELOC_32_PCREL
);
10410 case 8: code
= BFD_RELOC_64_PCREL
; break;
10416 switch (fixp
->fx_size
)
10419 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10420 _("can not do %d byte relocation"),
10422 code
= BFD_RELOC_32
;
10424 case 1: code
= BFD_RELOC_8
; break;
10425 case 2: code
= BFD_RELOC_16
; break;
10426 case 4: code
= BFD_RELOC_32
; break;
10428 case 8: code
= BFD_RELOC_64
; break;
10435 if ((code
== BFD_RELOC_32
10436 || code
== BFD_RELOC_32_PCREL
10437 || code
== BFD_RELOC_X86_64_32S
)
10439 && fixp
->fx_addsy
== GOT_symbol
)
10442 code
= BFD_RELOC_386_GOTPC
;
10444 code
= BFD_RELOC_X86_64_GOTPC32
;
10446 if ((code
== BFD_RELOC_64
|| code
== BFD_RELOC_64_PCREL
)
10448 && fixp
->fx_addsy
== GOT_symbol
)
10450 code
= BFD_RELOC_X86_64_GOTPC64
;
10453 rel
= (arelent
*) xmalloc (sizeof (arelent
));
10454 rel
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
10455 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
10457 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
10459 if (!use_rela_relocations
)
10461 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
10462 vtable entry to be used in the relocation's section offset. */
10463 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
10464 rel
->address
= fixp
->fx_offset
;
10465 #if defined (OBJ_COFF) && defined (TE_PE)
10466 else if (fixp
->fx_addsy
&& S_IS_WEAK (fixp
->fx_addsy
))
10467 rel
->addend
= fixp
->fx_addnumber
- (S_GET_VALUE (fixp
->fx_addsy
) * 2);
10472 /* Use the rela in 64bit mode. */
10475 if (disallow_64bit_reloc
)
10478 case BFD_RELOC_X86_64_DTPOFF64
:
10479 case BFD_RELOC_X86_64_TPOFF64
:
10480 case BFD_RELOC_64_PCREL
:
10481 case BFD_RELOC_X86_64_GOTOFF64
:
10482 case BFD_RELOC_X86_64_GOT64
:
10483 case BFD_RELOC_X86_64_GOTPCREL64
:
10484 case BFD_RELOC_X86_64_GOTPC64
:
10485 case BFD_RELOC_X86_64_GOTPLT64
:
10486 case BFD_RELOC_X86_64_PLTOFF64
:
10487 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10488 _("cannot represent relocation type %s in x32 mode"),
10489 bfd_get_reloc_code_name (code
));
10495 if (!fixp
->fx_pcrel
)
10496 rel
->addend
= fixp
->fx_offset
;
10500 case BFD_RELOC_X86_64_PLT32
:
10501 case BFD_RELOC_X86_64_PLT32_BND
:
10502 case BFD_RELOC_X86_64_GOT32
:
10503 case BFD_RELOC_X86_64_GOTPCREL
:
10504 case BFD_RELOC_X86_64_TLSGD
:
10505 case BFD_RELOC_X86_64_TLSLD
:
10506 case BFD_RELOC_X86_64_GOTTPOFF
:
10507 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
10508 case BFD_RELOC_X86_64_TLSDESC_CALL
:
10509 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
10512 rel
->addend
= (section
->vma
10514 + fixp
->fx_addnumber
10515 + md_pcrel_from (fixp
));
10520 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
10521 if (rel
->howto
== NULL
)
10523 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10524 _("cannot represent relocation type %s"),
10525 bfd_get_reloc_code_name (code
));
10526 /* Set howto to a garbage value so that we can keep going. */
10527 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
10528 gas_assert (rel
->howto
!= NULL
);
10534 #include "tc-i386-intel.c"
10537 tc_x86_parse_to_dw2regnum (expressionS
*exp
)
10539 int saved_naked_reg
;
10540 char saved_register_dot
;
10542 saved_naked_reg
= allow_naked_reg
;
10543 allow_naked_reg
= 1;
10544 saved_register_dot
= register_chars
['.'];
10545 register_chars
['.'] = '.';
10546 allow_pseudo_reg
= 1;
10547 expression_and_evaluate (exp
);
10548 allow_pseudo_reg
= 0;
10549 register_chars
['.'] = saved_register_dot
;
10550 allow_naked_reg
= saved_naked_reg
;
10552 if (exp
->X_op
== O_register
&& exp
->X_add_number
>= 0)
10554 if ((addressT
) exp
->X_add_number
< i386_regtab_size
)
10556 exp
->X_op
= O_constant
;
10557 exp
->X_add_number
= i386_regtab
[exp
->X_add_number
]
10558 .dw2_regnum
[flag_code
>> 1];
10561 exp
->X_op
= O_illegal
;
10566 tc_x86_frame_initial_instructions (void)
10568 static unsigned int sp_regno
[2];
10570 if (!sp_regno
[flag_code
>> 1])
10572 char *saved_input
= input_line_pointer
;
10573 char sp
[][4] = {"esp", "rsp"};
10576 input_line_pointer
= sp
[flag_code
>> 1];
10577 tc_x86_parse_to_dw2regnum (&exp
);
10578 gas_assert (exp
.X_op
== O_constant
);
10579 sp_regno
[flag_code
>> 1] = exp
.X_add_number
;
10580 input_line_pointer
= saved_input
;
10583 cfi_add_CFA_def_cfa (sp_regno
[flag_code
>> 1], -x86_cie_data_alignment
);
10584 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
10588 x86_dwarf2_addr_size (void)
10590 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
10591 if (x86_elf_abi
== X86_64_X32_ABI
)
10594 return bfd_arch_bits_per_address (stdoutput
) / 8;
10598 i386_elf_section_type (const char *str
, size_t len
)
10600 if (flag_code
== CODE_64BIT
10601 && len
== sizeof ("unwind") - 1
10602 && strncmp (str
, "unwind", 6) == 0)
10603 return SHT_X86_64_UNWIND
;
10610 i386_solaris_fix_up_eh_frame (segT sec
)
10612 if (flag_code
== CODE_64BIT
)
10613 elf_section_type (sec
) = SHT_X86_64_UNWIND
;
10619 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
10623 exp
.X_op
= O_secrel
;
10624 exp
.X_add_symbol
= symbol
;
10625 exp
.X_add_number
= 0;
10626 emit_expr (&exp
, size
);
10630 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10631 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
10634 x86_64_section_letter (int letter
, char **ptr_msg
)
10636 if (flag_code
== CODE_64BIT
)
10639 return SHF_X86_64_LARGE
;
10641 *ptr_msg
= _("bad .section directive: want a,l,w,x,M,S,G,T in string");
10644 *ptr_msg
= _("bad .section directive: want a,w,x,M,S,G,T in string");
10649 x86_64_section_word (char *str
, size_t len
)
10651 if (len
== 5 && flag_code
== CODE_64BIT
&& CONST_STRNEQ (str
, "large"))
10652 return SHF_X86_64_LARGE
;
10658 handle_large_common (int small ATTRIBUTE_UNUSED
)
10660 if (flag_code
!= CODE_64BIT
)
10662 s_comm_internal (0, elf_common_parse
);
10663 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
10667 static segT lbss_section
;
10668 asection
*saved_com_section_ptr
= elf_com_section_ptr
;
10669 asection
*saved_bss_section
= bss_section
;
10671 if (lbss_section
== NULL
)
10673 flagword applicable
;
10674 segT seg
= now_seg
;
10675 subsegT subseg
= now_subseg
;
10677 /* The .lbss section is for local .largecomm symbols. */
10678 lbss_section
= subseg_new (".lbss", 0);
10679 applicable
= bfd_applicable_section_flags (stdoutput
);
10680 bfd_set_section_flags (stdoutput
, lbss_section
,
10681 applicable
& SEC_ALLOC
);
10682 seg_info (lbss_section
)->bss
= 1;
10684 subseg_set (seg
, subseg
);
10687 elf_com_section_ptr
= &_bfd_elf_large_com_section
;
10688 bss_section
= lbss_section
;
10690 s_comm_internal (0, elf_common_parse
);
10692 elf_com_section_ptr
= saved_com_section_ptr
;
10693 bss_section
= saved_bss_section
;
10696 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */