1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright (C) 1989-2018 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 /* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
23 x86_64 support by Jan Hubicka (jh@suse.cz)
24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
29 #include "safe-ctype.h"
31 #include "dwarf2dbg.h"
32 #include "dw2gencfi.h"
33 #include "elf/x86-64.h"
34 #include "opcodes/i386-init.h"
36 #ifndef REGISTER_WARNINGS
37 #define REGISTER_WARNINGS 1
40 #ifndef INFER_ADDR_PREFIX
41 #define INFER_ADDR_PREFIX 1
45 #define DEFAULT_ARCH "i386"
50 #define INLINE __inline__
56 /* Prefixes will be emitted in the order defined below.
57 WAIT_PREFIX must be the first prefix since FWAIT is really is an
58 instruction, and so must come before any prefixes.
59 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
60 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
66 #define HLE_PREFIX REP_PREFIX
67 #define BND_PREFIX REP_PREFIX
69 #define REX_PREFIX 6 /* must come last. */
70 #define MAX_PREFIXES 7 /* max prefixes per opcode */
72 /* we define the syntax here (modulo base,index,scale syntax) */
73 #define REGISTER_PREFIX '%'
74 #define IMMEDIATE_PREFIX '$'
75 #define ABSOLUTE_PREFIX '*'
77 /* these are the instruction mnemonic suffixes in AT&T syntax or
78 memory operand size in Intel syntax. */
79 #define WORD_MNEM_SUFFIX 'w'
80 #define BYTE_MNEM_SUFFIX 'b'
81 #define SHORT_MNEM_SUFFIX 's'
82 #define LONG_MNEM_SUFFIX 'l'
83 #define QWORD_MNEM_SUFFIX 'q'
84 /* Intel Syntax. Use a non-ascii letter since since it never appears
86 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
88 #define END_OF_INSN '\0'
91 'templates' is for grouping together 'template' structures for opcodes
92 of the same name. This is only used for storing the insns in the grand
93 ole hash table of insns.
94 The templates themselves start at START and range up to (but not including)
99 const insn_template
*start
;
100 const insn_template
*end
;
104 /* 386 operand encoding bytes: see 386 book for details of this. */
107 unsigned int regmem
; /* codes register or memory operand */
108 unsigned int reg
; /* codes register operand (or extended opcode) */
109 unsigned int mode
; /* how to interpret regmem & reg */
113 /* x86-64 extension prefix. */
114 typedef int rex_byte
;
116 /* 386 opcode byte to code indirect addressing. */
125 /* x86 arch names, types and features */
128 const char *name
; /* arch name */
129 unsigned int len
; /* arch string length */
130 enum processor_type type
; /* arch type */
131 i386_cpu_flags flags
; /* cpu feature flags */
132 unsigned int skip
; /* show_arch should skip this. */
136 /* Used to turn off indicated flags. */
139 const char *name
; /* arch name */
140 unsigned int len
; /* arch string length */
141 i386_cpu_flags flags
; /* cpu feature flags */
145 static void update_code_flag (int, int);
146 static void set_code_flag (int);
147 static void set_16bit_gcc_code_flag (int);
148 static void set_intel_syntax (int);
149 static void set_intel_mnemonic (int);
150 static void set_allow_index_reg (int);
151 static void set_check (int);
152 static void set_cpu_arch (int);
154 static void pe_directive_secrel (int);
156 static void signed_cons (int);
157 static char *output_invalid (int c
);
158 static int i386_finalize_immediate (segT
, expressionS
*, i386_operand_type
,
160 static int i386_finalize_displacement (segT
, expressionS
*, i386_operand_type
,
162 static int i386_att_operand (char *);
163 static int i386_intel_operand (char *, int);
164 static int i386_intel_simplify (expressionS
*);
165 static int i386_intel_parse_name (const char *, expressionS
*);
166 static const reg_entry
*parse_register (char *, char **);
167 static char *parse_insn (char *, char *);
168 static char *parse_operands (char *, const char *);
169 static void swap_operands (void);
170 static void swap_2_operands (int, int);
171 static void optimize_imm (void);
172 static void optimize_disp (void);
173 static const insn_template
*match_template (char);
174 static int check_string (void);
175 static int process_suffix (void);
176 static int check_byte_reg (void);
177 static int check_long_reg (void);
178 static int check_qword_reg (void);
179 static int check_word_reg (void);
180 static int finalize_imm (void);
181 static int process_operands (void);
182 static const seg_entry
*build_modrm_byte (void);
183 static void output_insn (void);
184 static void output_imm (fragS
*, offsetT
);
185 static void output_disp (fragS
*, offsetT
);
187 static void s_bss (int);
189 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
190 static void handle_large_common (int small ATTRIBUTE_UNUSED
);
192 /* GNU_PROPERTY_X86_ISA_1_USED. */
193 static unsigned int x86_isa_1_used
;
194 /* GNU_PROPERTY_X86_FEATURE_2_USED. */
195 static unsigned int x86_feature_2_used
;
196 /* Generate x86 used ISA and feature properties. */
197 static unsigned int x86_used_note
= DEFAULT_X86_USED_NOTE
;
200 static const char *default_arch
= DEFAULT_ARCH
;
202 /* This struct describes rounding control and SAE in the instruction. */
216 static struct RC_Operation rc_op
;
218 /* The struct describes masking, applied to OPERAND in the instruction.
219 MASK is a pointer to the corresponding mask register. ZEROING tells
220 whether merging or zeroing mask is used. */
221 struct Mask_Operation
223 const reg_entry
*mask
;
224 unsigned int zeroing
;
225 /* The operand where this operation is associated. */
229 static struct Mask_Operation mask_op
;
231 /* The struct describes broadcasting, applied to OPERAND. FACTOR is
233 struct Broadcast_Operation
235 /* Type of broadcast: {1to2}, {1to4}, {1to8}, or {1to16}. */
238 /* Index of broadcasted operand. */
241 /* Number of bytes to broadcast. */
245 static struct Broadcast_Operation broadcast_op
;
250 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
251 unsigned char bytes
[4];
253 /* Destination or source register specifier. */
254 const reg_entry
*register_specifier
;
257 /* 'md_assemble ()' gathers together information and puts it into a
264 const reg_entry
*regs
;
269 operand_size_mismatch
,
270 operand_type_mismatch
,
271 register_type_mismatch
,
272 number_of_operands_mismatch
,
273 invalid_instruction_suffix
,
275 unsupported_with_intel_mnemonic
,
278 invalid_vsib_address
,
279 invalid_vector_register_set
,
280 unsupported_vector_index_register
,
281 unsupported_broadcast
,
284 mask_not_on_destination
,
287 rc_sae_operand_not_last_imm
,
288 invalid_register_operand
,
293 /* TM holds the template for the insn were currently assembling. */
296 /* SUFFIX holds the instruction size suffix for byte, word, dword
297 or qword, if given. */
300 /* OPERANDS gives the number of given operands. */
301 unsigned int operands
;
303 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
304 of given register, displacement, memory operands and immediate
306 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
308 /* TYPES [i] is the type (see above #defines) which tells us how to
309 use OP[i] for the corresponding operand. */
310 i386_operand_type types
[MAX_OPERANDS
];
312 /* Displacement expression, immediate expression, or register for each
314 union i386_op op
[MAX_OPERANDS
];
316 /* Flags for operands. */
317 unsigned int flags
[MAX_OPERANDS
];
318 #define Operand_PCrel 1
319 #define Operand_Mem 2
321 /* Relocation type for operand */
322 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
324 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
325 the base index byte below. */
326 const reg_entry
*base_reg
;
327 const reg_entry
*index_reg
;
328 unsigned int log2_scale_factor
;
330 /* SEG gives the seg_entries of this insn. They are zero unless
331 explicit segment overrides are given. */
332 const seg_entry
*seg
[2];
334 /* Copied first memory operand string, for re-checking. */
337 /* PREFIX holds all the given prefix opcodes (usually null).
338 PREFIXES is the number of prefix opcodes. */
339 unsigned int prefixes
;
340 unsigned char prefix
[MAX_PREFIXES
];
342 /* Has MMX register operands. */
343 bfd_boolean has_regmmx
;
345 /* Has XMM register operands. */
346 bfd_boolean has_regxmm
;
348 /* Has YMM register operands. */
349 bfd_boolean has_regymm
;
351 /* Has ZMM register operands. */
352 bfd_boolean has_regzmm
;
354 /* RM and SIB are the modrm byte and the sib byte where the
355 addressing modes of this insn are encoded. */
362 /* Masking attributes. */
363 struct Mask_Operation
*mask
;
365 /* Rounding control and SAE attributes. */
366 struct RC_Operation
*rounding
;
368 /* Broadcasting attributes. */
369 struct Broadcast_Operation
*broadcast
;
371 /* Compressed disp8*N attribute. */
372 unsigned int memshift
;
374 /* Prefer load or store in encoding. */
377 dir_encoding_default
= 0,
383 /* Prefer 8bit or 32bit displacement in encoding. */
386 disp_encoding_default
= 0,
391 /* Prefer the REX byte in encoding. */
392 bfd_boolean rex_encoding
;
394 /* Disable instruction size optimization. */
395 bfd_boolean no_optimize
;
397 /* How to encode vector instructions. */
400 vex_encoding_default
= 0,
407 const char *rep_prefix
;
410 const char *hle_prefix
;
412 /* Have BND prefix. */
413 const char *bnd_prefix
;
415 /* Have NOTRACK prefix. */
416 const char *notrack_prefix
;
419 enum i386_error error
;
422 typedef struct _i386_insn i386_insn
;
424 /* Link RC type with corresponding string, that'll be looked for in
433 static const struct RC_name RC_NamesTable
[] =
435 { rne
, STRING_COMMA_LEN ("rn-sae") },
436 { rd
, STRING_COMMA_LEN ("rd-sae") },
437 { ru
, STRING_COMMA_LEN ("ru-sae") },
438 { rz
, STRING_COMMA_LEN ("rz-sae") },
439 { saeonly
, STRING_COMMA_LEN ("sae") },
442 /* List of chars besides those in app.c:symbol_chars that can start an
443 operand. Used to prevent the scrubber eating vital white-space. */
444 const char extra_symbol_chars
[] = "*%-([{}"
453 #if (defined (TE_I386AIX) \
454 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
455 && !defined (TE_GNU) \
456 && !defined (TE_LINUX) \
457 && !defined (TE_NACL) \
458 && !defined (TE_FreeBSD) \
459 && !defined (TE_DragonFly) \
460 && !defined (TE_NetBSD)))
461 /* This array holds the chars that always start a comment. If the
462 pre-processor is disabled, these aren't very useful. The option
463 --divide will remove '/' from this list. */
464 const char *i386_comment_chars
= "#/";
465 #define SVR4_COMMENT_CHARS 1
466 #define PREFIX_SEPARATOR '\\'
469 const char *i386_comment_chars
= "#";
470 #define PREFIX_SEPARATOR '/'
473 /* This array holds the chars that only start a comment at the beginning of
474 a line. If the line seems to have the form '# 123 filename'
475 .line and .file directives will appear in the pre-processed output.
476 Note that input_file.c hand checks for '#' at the beginning of the
477 first line of the input file. This is because the compiler outputs
478 #NO_APP at the beginning of its output.
479 Also note that comments started like this one will always work if
480 '/' isn't otherwise defined. */
481 const char line_comment_chars
[] = "#/";
483 const char line_separator_chars
[] = ";";
485 /* Chars that can be used to separate mant from exp in floating point
487 const char EXP_CHARS
[] = "eE";
489 /* Chars that mean this number is a floating point constant
492 const char FLT_CHARS
[] = "fFdDxX";
494 /* Tables for lexical analysis. */
495 static char mnemonic_chars
[256];
496 static char register_chars
[256];
497 static char operand_chars
[256];
498 static char identifier_chars
[256];
499 static char digit_chars
[256];
501 /* Lexical macros. */
502 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
503 #define is_operand_char(x) (operand_chars[(unsigned char) x])
504 #define is_register_char(x) (register_chars[(unsigned char) x])
505 #define is_space_char(x) ((x) == ' ')
506 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
507 #define is_digit_char(x) (digit_chars[(unsigned char) x])
509 /* All non-digit non-letter characters that may occur in an operand. */
510 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
512 /* md_assemble() always leaves the strings it's passed unaltered. To
513 effect this we maintain a stack of saved characters that we've smashed
514 with '\0's (indicating end of strings for various sub-fields of the
515 assembler instruction). */
516 static char save_stack
[32];
517 static char *save_stack_p
;
518 #define END_STRING_AND_SAVE(s) \
519 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
520 #define RESTORE_END_STRING(s) \
521 do { *(s) = *--save_stack_p; } while (0)
523 /* The instruction we're assembling. */
526 /* Possible templates for current insn. */
527 static const templates
*current_templates
;
529 /* Per instruction expressionS buffers: max displacements & immediates. */
530 static expressionS disp_expressions
[MAX_MEMORY_OPERANDS
];
531 static expressionS im_expressions
[MAX_IMMEDIATE_OPERANDS
];
533 /* Current operand we are working on. */
534 static int this_operand
= -1;
536 /* We support four different modes. FLAG_CODE variable is used to distinguish
544 static enum flag_code flag_code
;
545 static unsigned int object_64bit
;
546 static unsigned int disallow_64bit_reloc
;
547 static int use_rela_relocations
= 0;
549 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
550 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
551 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
553 /* The ELF ABI to use. */
561 static enum x86_elf_abi x86_elf_abi
= I386_ABI
;
564 #if defined (TE_PE) || defined (TE_PEP)
565 /* Use big object file format. */
566 static int use_big_obj
= 0;
569 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
570 /* 1 if generating code for a shared library. */
571 static int shared
= 0;
574 /* 1 for intel syntax,
576 static int intel_syntax
= 0;
578 /* 1 for Intel64 ISA,
582 /* 1 for intel mnemonic,
583 0 if att mnemonic. */
584 static int intel_mnemonic
= !SYSV386_COMPAT
;
586 /* 1 if pseudo registers are permitted. */
587 static int allow_pseudo_reg
= 0;
589 /* 1 if register prefix % not required. */
590 static int allow_naked_reg
= 0;
592 /* 1 if the assembler should add BND prefix for all control-transferring
593 instructions supporting it, even if this prefix wasn't specified
595 static int add_bnd_prefix
= 0;
597 /* 1 if pseudo index register, eiz/riz, is allowed . */
598 static int allow_index_reg
= 0;
600 /* 1 if the assembler should ignore LOCK prefix, even if it was
601 specified explicitly. */
602 static int omit_lock_prefix
= 0;
604 /* 1 if the assembler should encode lfence, mfence, and sfence as
605 "lock addl $0, (%{re}sp)". */
606 static int avoid_fence
= 0;
608 /* 1 if the assembler should generate relax relocations. */
610 static int generate_relax_relocations
611 = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS
;
613 static enum check_kind
619 sse_check
, operand_check
= check_warning
;
622 1. Clear the REX_W bit with register operand if possible.
623 2. Above plus use 128bit vector instruction to clear the full vector
626 static int optimize
= 0;
629 1. Clear the REX_W bit with register operand if possible.
630 2. Above plus use 128bit vector instruction to clear the full vector
632 3. Above plus optimize "test{q,l,w} $imm8,%r{64,32,16}" to
635 static int optimize_for_space
= 0;
637 /* Register prefix used for error message. */
638 static const char *register_prefix
= "%";
640 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
641 leave, push, and pop instructions so that gcc has the same stack
642 frame as in 32 bit mode. */
643 static char stackop_size
= '\0';
645 /* Non-zero to optimize code alignment. */
646 int optimize_align_code
= 1;
648 /* Non-zero to quieten some warnings. */
649 static int quiet_warnings
= 0;
652 static const char *cpu_arch_name
= NULL
;
653 static char *cpu_sub_arch_name
= NULL
;
655 /* CPU feature flags. */
656 static i386_cpu_flags cpu_arch_flags
= CPU_UNKNOWN_FLAGS
;
658 /* If we have selected a cpu we are generating instructions for. */
659 static int cpu_arch_tune_set
= 0;
661 /* Cpu we are generating instructions for. */
662 enum processor_type cpu_arch_tune
= PROCESSOR_UNKNOWN
;
664 /* CPU feature flags of cpu we are generating instructions for. */
665 static i386_cpu_flags cpu_arch_tune_flags
;
667 /* CPU instruction set architecture used. */
668 enum processor_type cpu_arch_isa
= PROCESSOR_UNKNOWN
;
670 /* CPU feature flags of instruction set architecture used. */
671 i386_cpu_flags cpu_arch_isa_flags
;
673 /* If set, conditional jumps are not automatically promoted to handle
674 larger than a byte offset. */
675 static unsigned int no_cond_jump_promotion
= 0;
677 /* Encode SSE instructions with VEX prefix. */
678 static unsigned int sse2avx
;
680 /* Encode scalar AVX instructions with specific vector length. */
687 /* Encode scalar EVEX LIG instructions with specific vector length. */
695 /* Encode EVEX WIG instructions with specific evex.w. */
702 /* Value to encode in EVEX RC bits, for SAE-only instructions. */
703 static enum rc_type evexrcig
= rne
;
705 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
706 static symbolS
*GOT_symbol
;
708 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
709 unsigned int x86_dwarf2_return_column
;
711 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
712 int x86_cie_data_alignment
;
714 /* Interface to relax_segment.
715 There are 3 major relax states for 386 jump insns because the
716 different types of jumps add different sizes to frags when we're
717 figuring out what sort of jump to choose to reach a given label. */
720 #define UNCOND_JUMP 0
722 #define COND_JUMP86 2
727 #define SMALL16 (SMALL | CODE16)
729 #define BIG16 (BIG | CODE16)
733 #define INLINE __inline__
739 #define ENCODE_RELAX_STATE(type, size) \
740 ((relax_substateT) (((type) << 2) | (size)))
741 #define TYPE_FROM_RELAX_STATE(s) \
743 #define DISP_SIZE_FROM_RELAX_STATE(s) \
744 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
746 /* This table is used by relax_frag to promote short jumps to long
747 ones where necessary. SMALL (short) jumps may be promoted to BIG
748 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
749 don't allow a short jump in a 32 bit code segment to be promoted to
750 a 16 bit offset jump because it's slower (requires data size
751 prefix), and doesn't work, unless the destination is in the bottom
752 64k of the code segment (The top 16 bits of eip are zeroed). */
754 const relax_typeS md_relax_table
[] =
757 1) most positive reach of this state,
758 2) most negative reach of this state,
759 3) how many bytes this mode will have in the variable part of the frag
760 4) which index into the table to try if we can't fit into this one. */
762 /* UNCOND_JUMP states. */
763 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
764 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
765 /* dword jmp adds 4 bytes to frag:
766 0 extra opcode bytes, 4 displacement bytes. */
768 /* word jmp adds 2 byte2 to frag:
769 0 extra opcode bytes, 2 displacement bytes. */
772 /* COND_JUMP states. */
773 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
774 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
775 /* dword conditionals adds 5 bytes to frag:
776 1 extra opcode byte, 4 displacement bytes. */
778 /* word conditionals add 3 bytes to frag:
779 1 extra opcode byte, 2 displacement bytes. */
782 /* COND_JUMP86 states. */
783 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
784 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
785 /* dword conditionals adds 5 bytes to frag:
786 1 extra opcode byte, 4 displacement bytes. */
788 /* word conditionals add 4 bytes to frag:
789 1 displacement byte and a 3 byte long branch insn. */
793 static const arch_entry cpu_arch
[] =
795 /* Do not replace the first two entries - i386_target_format()
796 relies on them being there in this order. */
797 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32
,
798 CPU_GENERIC32_FLAGS
, 0 },
799 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64
,
800 CPU_GENERIC64_FLAGS
, 0 },
801 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN
,
803 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN
,
805 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN
,
807 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386
,
809 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486
,
811 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM
,
813 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO
,
815 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM
,
817 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO
,
818 CPU_PENTIUMPRO_FLAGS
, 0 },
819 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO
,
821 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO
,
823 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4
,
825 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA
,
827 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA
,
828 CPU_NOCONA_FLAGS
, 0 },
829 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE
,
831 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE
,
833 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2
,
834 CPU_CORE2_FLAGS
, 1 },
835 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2
,
836 CPU_CORE2_FLAGS
, 0 },
837 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7
,
838 CPU_COREI7_FLAGS
, 0 },
839 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM
,
841 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM
,
843 { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU
,
844 CPU_IAMCU_FLAGS
, 0 },
845 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6
,
847 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6
,
849 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON
,
850 CPU_ATHLON_FLAGS
, 0 },
851 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8
,
853 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8
,
855 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8
,
857 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10
,
858 CPU_AMDFAM10_FLAGS
, 0 },
859 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD
,
860 CPU_BDVER1_FLAGS
, 0 },
861 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD
,
862 CPU_BDVER2_FLAGS
, 0 },
863 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD
,
864 CPU_BDVER3_FLAGS
, 0 },
865 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD
,
866 CPU_BDVER4_FLAGS
, 0 },
867 { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER
,
868 CPU_ZNVER1_FLAGS
, 0 },
869 { STRING_COMMA_LEN ("znver2"), PROCESSOR_ZNVER
,
870 CPU_ZNVER2_FLAGS
, 0 },
871 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT
,
872 CPU_BTVER1_FLAGS
, 0 },
873 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT
,
874 CPU_BTVER2_FLAGS
, 0 },
875 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN
,
877 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN
,
879 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN
,
881 { STRING_COMMA_LEN (".687"), PROCESSOR_UNKNOWN
,
883 { STRING_COMMA_LEN (".cmov"), PROCESSOR_UNKNOWN
,
885 { STRING_COMMA_LEN (".fxsr"), PROCESSOR_UNKNOWN
,
887 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN
,
889 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN
,
891 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN
,
893 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN
,
895 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN
,
896 CPU_SSSE3_FLAGS
, 0 },
897 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN
,
898 CPU_SSE4_1_FLAGS
, 0 },
899 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN
,
900 CPU_SSE4_2_FLAGS
, 0 },
901 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN
,
902 CPU_SSE4_2_FLAGS
, 0 },
903 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN
,
905 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN
,
907 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN
,
908 CPU_AVX512F_FLAGS
, 0 },
909 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN
,
910 CPU_AVX512CD_FLAGS
, 0 },
911 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN
,
912 CPU_AVX512ER_FLAGS
, 0 },
913 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN
,
914 CPU_AVX512PF_FLAGS
, 0 },
915 { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN
,
916 CPU_AVX512DQ_FLAGS
, 0 },
917 { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN
,
918 CPU_AVX512BW_FLAGS
, 0 },
919 { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN
,
920 CPU_AVX512VL_FLAGS
, 0 },
921 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN
,
923 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN
,
924 CPU_VMFUNC_FLAGS
, 0 },
925 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN
,
927 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN
,
928 CPU_XSAVE_FLAGS
, 0 },
929 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN
,
930 CPU_XSAVEOPT_FLAGS
, 0 },
931 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN
,
932 CPU_XSAVEC_FLAGS
, 0 },
933 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN
,
934 CPU_XSAVES_FLAGS
, 0 },
935 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN
,
937 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN
,
938 CPU_PCLMUL_FLAGS
, 0 },
939 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN
,
940 CPU_PCLMUL_FLAGS
, 1 },
941 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN
,
942 CPU_FSGSBASE_FLAGS
, 0 },
943 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN
,
944 CPU_RDRND_FLAGS
, 0 },
945 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN
,
947 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN
,
949 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN
,
951 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN
,
953 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN
,
955 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN
,
957 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN
,
958 CPU_MOVBE_FLAGS
, 0 },
959 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN
,
961 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN
,
963 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN
,
964 CPU_LZCNT_FLAGS
, 0 },
965 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN
,
967 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN
,
969 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN
,
970 CPU_INVPCID_FLAGS
, 0 },
971 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN
,
972 CPU_CLFLUSH_FLAGS
, 0 },
973 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN
,
975 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN
,
976 CPU_SYSCALL_FLAGS
, 0 },
977 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN
,
978 CPU_RDTSCP_FLAGS
, 0 },
979 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN
,
980 CPU_3DNOW_FLAGS
, 0 },
981 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN
,
982 CPU_3DNOWA_FLAGS
, 0 },
983 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN
,
984 CPU_PADLOCK_FLAGS
, 0 },
985 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN
,
987 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN
,
989 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN
,
990 CPU_SSE4A_FLAGS
, 0 },
991 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN
,
993 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN
,
995 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN
,
997 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN
,
999 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN
,
1000 CPU_RDSEED_FLAGS
, 0 },
1001 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN
,
1002 CPU_PRFCHW_FLAGS
, 0 },
1003 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN
,
1004 CPU_SMAP_FLAGS
, 0 },
1005 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN
,
1007 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN
,
1009 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN
,
1010 CPU_CLFLUSHOPT_FLAGS
, 0 },
1011 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN
,
1012 CPU_PREFETCHWT1_FLAGS
, 0 },
1013 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN
,
1015 { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN
,
1016 CPU_CLWB_FLAGS
, 0 },
1017 { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN
,
1018 CPU_AVX512IFMA_FLAGS
, 0 },
1019 { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN
,
1020 CPU_AVX512VBMI_FLAGS
, 0 },
1021 { STRING_COMMA_LEN (".avx512_4fmaps"), PROCESSOR_UNKNOWN
,
1022 CPU_AVX512_4FMAPS_FLAGS
, 0 },
1023 { STRING_COMMA_LEN (".avx512_4vnniw"), PROCESSOR_UNKNOWN
,
1024 CPU_AVX512_4VNNIW_FLAGS
, 0 },
1025 { STRING_COMMA_LEN (".avx512_vpopcntdq"), PROCESSOR_UNKNOWN
,
1026 CPU_AVX512_VPOPCNTDQ_FLAGS
, 0 },
1027 { STRING_COMMA_LEN (".avx512_vbmi2"), PROCESSOR_UNKNOWN
,
1028 CPU_AVX512_VBMI2_FLAGS
, 0 },
1029 { STRING_COMMA_LEN (".avx512_vnni"), PROCESSOR_UNKNOWN
,
1030 CPU_AVX512_VNNI_FLAGS
, 0 },
1031 { STRING_COMMA_LEN (".avx512_bitalg"), PROCESSOR_UNKNOWN
,
1032 CPU_AVX512_BITALG_FLAGS
, 0 },
1033 { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN
,
1034 CPU_CLZERO_FLAGS
, 0 },
1035 { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN
,
1036 CPU_MWAITX_FLAGS
, 0 },
1037 { STRING_COMMA_LEN (".ospke"), PROCESSOR_UNKNOWN
,
1038 CPU_OSPKE_FLAGS
, 0 },
1039 { STRING_COMMA_LEN (".rdpid"), PROCESSOR_UNKNOWN
,
1040 CPU_RDPID_FLAGS
, 0 },
1041 { STRING_COMMA_LEN (".ptwrite"), PROCESSOR_UNKNOWN
,
1042 CPU_PTWRITE_FLAGS
, 0 },
1043 { STRING_COMMA_LEN (".ibt"), PROCESSOR_UNKNOWN
,
1045 { STRING_COMMA_LEN (".shstk"), PROCESSOR_UNKNOWN
,
1046 CPU_SHSTK_FLAGS
, 0 },
1047 { STRING_COMMA_LEN (".gfni"), PROCESSOR_UNKNOWN
,
1048 CPU_GFNI_FLAGS
, 0 },
1049 { STRING_COMMA_LEN (".vaes"), PROCESSOR_UNKNOWN
,
1050 CPU_VAES_FLAGS
, 0 },
1051 { STRING_COMMA_LEN (".vpclmulqdq"), PROCESSOR_UNKNOWN
,
1052 CPU_VPCLMULQDQ_FLAGS
, 0 },
1053 { STRING_COMMA_LEN (".wbnoinvd"), PROCESSOR_UNKNOWN
,
1054 CPU_WBNOINVD_FLAGS
, 0 },
1055 { STRING_COMMA_LEN (".pconfig"), PROCESSOR_UNKNOWN
,
1056 CPU_PCONFIG_FLAGS
, 0 },
1057 { STRING_COMMA_LEN (".waitpkg"), PROCESSOR_UNKNOWN
,
1058 CPU_WAITPKG_FLAGS
, 0 },
1059 { STRING_COMMA_LEN (".cldemote"), PROCESSOR_UNKNOWN
,
1060 CPU_CLDEMOTE_FLAGS
, 0 },
1061 { STRING_COMMA_LEN (".movdiri"), PROCESSOR_UNKNOWN
,
1062 CPU_MOVDIRI_FLAGS
, 0 },
1063 { STRING_COMMA_LEN (".movdir64b"), PROCESSOR_UNKNOWN
,
1064 CPU_MOVDIR64B_FLAGS
, 0 },
1067 static const noarch_entry cpu_noarch
[] =
1069 { STRING_COMMA_LEN ("no87"), CPU_ANY_X87_FLAGS
},
1070 { STRING_COMMA_LEN ("no287"), CPU_ANY_287_FLAGS
},
1071 { STRING_COMMA_LEN ("no387"), CPU_ANY_387_FLAGS
},
1072 { STRING_COMMA_LEN ("no687"), CPU_ANY_687_FLAGS
},
1073 { STRING_COMMA_LEN ("nocmov"), CPU_ANY_CMOV_FLAGS
},
1074 { STRING_COMMA_LEN ("nofxsr"), CPU_ANY_FXSR_FLAGS
},
1075 { STRING_COMMA_LEN ("nommx"), CPU_ANY_MMX_FLAGS
},
1076 { STRING_COMMA_LEN ("nosse"), CPU_ANY_SSE_FLAGS
},
1077 { STRING_COMMA_LEN ("nosse2"), CPU_ANY_SSE2_FLAGS
},
1078 { STRING_COMMA_LEN ("nosse3"), CPU_ANY_SSE3_FLAGS
},
1079 { STRING_COMMA_LEN ("nossse3"), CPU_ANY_SSSE3_FLAGS
},
1080 { STRING_COMMA_LEN ("nosse4.1"), CPU_ANY_SSE4_1_FLAGS
},
1081 { STRING_COMMA_LEN ("nosse4.2"), CPU_ANY_SSE4_2_FLAGS
},
1082 { STRING_COMMA_LEN ("nosse4"), CPU_ANY_SSE4_1_FLAGS
},
1083 { STRING_COMMA_LEN ("noavx"), CPU_ANY_AVX_FLAGS
},
1084 { STRING_COMMA_LEN ("noavx2"), CPU_ANY_AVX2_FLAGS
},
1085 { STRING_COMMA_LEN ("noavx512f"), CPU_ANY_AVX512F_FLAGS
},
1086 { STRING_COMMA_LEN ("noavx512cd"), CPU_ANY_AVX512CD_FLAGS
},
1087 { STRING_COMMA_LEN ("noavx512er"), CPU_ANY_AVX512ER_FLAGS
},
1088 { STRING_COMMA_LEN ("noavx512pf"), CPU_ANY_AVX512PF_FLAGS
},
1089 { STRING_COMMA_LEN ("noavx512dq"), CPU_ANY_AVX512DQ_FLAGS
},
1090 { STRING_COMMA_LEN ("noavx512bw"), CPU_ANY_AVX512BW_FLAGS
},
1091 { STRING_COMMA_LEN ("noavx512vl"), CPU_ANY_AVX512VL_FLAGS
},
1092 { STRING_COMMA_LEN ("noavx512ifma"), CPU_ANY_AVX512IFMA_FLAGS
},
1093 { STRING_COMMA_LEN ("noavx512vbmi"), CPU_ANY_AVX512VBMI_FLAGS
},
1094 { STRING_COMMA_LEN ("noavx512_4fmaps"), CPU_ANY_AVX512_4FMAPS_FLAGS
},
1095 { STRING_COMMA_LEN ("noavx512_4vnniw"), CPU_ANY_AVX512_4VNNIW_FLAGS
},
1096 { STRING_COMMA_LEN ("noavx512_vpopcntdq"), CPU_ANY_AVX512_VPOPCNTDQ_FLAGS
},
1097 { STRING_COMMA_LEN ("noavx512_vbmi2"), CPU_ANY_AVX512_VBMI2_FLAGS
},
1098 { STRING_COMMA_LEN ("noavx512_vnni"), CPU_ANY_AVX512_VNNI_FLAGS
},
1099 { STRING_COMMA_LEN ("noavx512_bitalg"), CPU_ANY_AVX512_BITALG_FLAGS
},
1100 { STRING_COMMA_LEN ("noibt"), CPU_ANY_IBT_FLAGS
},
1101 { STRING_COMMA_LEN ("noshstk"), CPU_ANY_SHSTK_FLAGS
},
1102 { STRING_COMMA_LEN ("nomovdiri"), CPU_ANY_MOVDIRI_FLAGS
},
1103 { STRING_COMMA_LEN ("nomovdir64b"), CPU_ANY_MOVDIR64B_FLAGS
},
1107 /* Like s_lcomm_internal in gas/read.c but the alignment string
1108 is allowed to be optional. */
1111 pe_lcomm_internal (int needs_align
, symbolS
*symbolP
, addressT size
)
1118 && *input_line_pointer
== ',')
1120 align
= parse_align (needs_align
- 1);
1122 if (align
== (addressT
) -1)
1137 bss_alloc (symbolP
, size
, align
);
1142 pe_lcomm (int needs_align
)
1144 s_comm_internal (needs_align
* 2, pe_lcomm_internal
);
1148 const pseudo_typeS md_pseudo_table
[] =
1150 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
1151 {"align", s_align_bytes
, 0},
1153 {"align", s_align_ptwo
, 0},
1155 {"arch", set_cpu_arch
, 0},
1159 {"lcomm", pe_lcomm
, 1},
1161 {"ffloat", float_cons
, 'f'},
1162 {"dfloat", float_cons
, 'd'},
1163 {"tfloat", float_cons
, 'x'},
1165 {"slong", signed_cons
, 4},
1166 {"noopt", s_ignore
, 0},
1167 {"optim", s_ignore
, 0},
1168 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
1169 {"code16", set_code_flag
, CODE_16BIT
},
1170 {"code32", set_code_flag
, CODE_32BIT
},
1172 {"code64", set_code_flag
, CODE_64BIT
},
1174 {"intel_syntax", set_intel_syntax
, 1},
1175 {"att_syntax", set_intel_syntax
, 0},
1176 {"intel_mnemonic", set_intel_mnemonic
, 1},
1177 {"att_mnemonic", set_intel_mnemonic
, 0},
1178 {"allow_index_reg", set_allow_index_reg
, 1},
1179 {"disallow_index_reg", set_allow_index_reg
, 0},
1180 {"sse_check", set_check
, 0},
1181 {"operand_check", set_check
, 1},
1182 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1183 {"largecomm", handle_large_common
, 0},
1185 {"file", dwarf2_directive_file
, 0},
1186 {"loc", dwarf2_directive_loc
, 0},
1187 {"loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0},
1190 {"secrel32", pe_directive_secrel
, 0},
1195 /* For interface with expression (). */
1196 extern char *input_line_pointer
;
1198 /* Hash table for instruction mnemonic lookup. */
1199 static struct hash_control
*op_hash
;
1201 /* Hash table for register lookup. */
1202 static struct hash_control
*reg_hash
;
1204 /* Various efficient no-op patterns for aligning code labels.
1205 Note: Don't try to assemble the instructions in the comments.
1206 0L and 0w are not legal. */
1207 static const unsigned char f32_1
[] =
1209 static const unsigned char f32_2
[] =
1210 {0x66,0x90}; /* xchg %ax,%ax */
1211 static const unsigned char f32_3
[] =
1212 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1213 static const unsigned char f32_4
[] =
1214 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1215 static const unsigned char f32_6
[] =
1216 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1217 static const unsigned char f32_7
[] =
1218 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1219 static const unsigned char f16_3
[] =
1220 {0x8d,0x74,0x00}; /* lea 0(%si),%si */
1221 static const unsigned char f16_4
[] =
1222 {0x8d,0xb4,0x00,0x00}; /* lea 0W(%si),%si */
1223 static const unsigned char jump_disp8
[] =
1224 {0xeb}; /* jmp disp8 */
1225 static const unsigned char jump32_disp32
[] =
1226 {0xe9}; /* jmp disp32 */
1227 static const unsigned char jump16_disp32
[] =
1228 {0x66,0xe9}; /* jmp disp32 */
1229 /* 32-bit NOPs patterns. */
1230 static const unsigned char *const f32_patt
[] = {
1231 f32_1
, f32_2
, f32_3
, f32_4
, NULL
, f32_6
, f32_7
1233 /* 16-bit NOPs patterns. */
1234 static const unsigned char *const f16_patt
[] = {
1235 f32_1
, f32_2
, f16_3
, f16_4
1237 /* nopl (%[re]ax) */
1238 static const unsigned char alt_3
[] =
1240 /* nopl 0(%[re]ax) */
1241 static const unsigned char alt_4
[] =
1242 {0x0f,0x1f,0x40,0x00};
1243 /* nopl 0(%[re]ax,%[re]ax,1) */
1244 static const unsigned char alt_5
[] =
1245 {0x0f,0x1f,0x44,0x00,0x00};
1246 /* nopw 0(%[re]ax,%[re]ax,1) */
1247 static const unsigned char alt_6
[] =
1248 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1249 /* nopl 0L(%[re]ax) */
1250 static const unsigned char alt_7
[] =
1251 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1252 /* nopl 0L(%[re]ax,%[re]ax,1) */
1253 static const unsigned char alt_8
[] =
1254 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1255 /* nopw 0L(%[re]ax,%[re]ax,1) */
1256 static const unsigned char alt_9
[] =
1257 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1258 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1259 static const unsigned char alt_10
[] =
1260 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1261 /* data16 nopw %cs:0L(%eax,%eax,1) */
1262 static const unsigned char alt_11
[] =
1263 {0x66,0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1264 /* 32-bit and 64-bit NOPs patterns. */
1265 static const unsigned char *const alt_patt
[] = {
1266 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
1267 alt_9
, alt_10
, alt_11
1270 /* Genenerate COUNT bytes of NOPs to WHERE from PATT with the maximum
1271 size of a single NOP instruction MAX_SINGLE_NOP_SIZE. */
1274 i386_output_nops (char *where
, const unsigned char *const *patt
,
1275 int count
, int max_single_nop_size
)
1278 /* Place the longer NOP first. */
1281 const unsigned char *nops
= patt
[max_single_nop_size
- 1];
1283 /* Use the smaller one if the requsted one isn't available. */
1286 max_single_nop_size
--;
1287 nops
= patt
[max_single_nop_size
- 1];
1290 last
= count
% max_single_nop_size
;
1293 for (offset
= 0; offset
< count
; offset
+= max_single_nop_size
)
1294 memcpy (where
+ offset
, nops
, max_single_nop_size
);
1298 nops
= patt
[last
- 1];
1301 /* Use the smaller one plus one-byte NOP if the needed one
1304 nops
= patt
[last
- 1];
1305 memcpy (where
+ offset
, nops
, last
);
1306 where
[offset
+ last
] = *patt
[0];
1309 memcpy (where
+ offset
, nops
, last
);
1314 fits_in_imm7 (offsetT num
)
1316 return (num
& 0x7f) == num
;
1320 fits_in_imm31 (offsetT num
)
1322 return (num
& 0x7fffffff) == num
;
1325 /* Genenerate COUNT bytes of NOPs to WHERE with the maximum size of a
1326 single NOP instruction LIMIT. */
1329 i386_generate_nops (fragS
*fragP
, char *where
, offsetT count
, int limit
)
1331 const unsigned char *const *patt
= NULL
;
1332 int max_single_nop_size
;
1333 /* Maximum number of NOPs before switching to jump over NOPs. */
1334 int max_number_of_nops
;
1336 switch (fragP
->fr_type
)
1345 /* We need to decide which NOP sequence to use for 32bit and
1346 64bit. When -mtune= is used:
1348 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1349 PROCESSOR_GENERIC32, f32_patt will be used.
1350 2. For the rest, alt_patt will be used.
1352 When -mtune= isn't used, alt_patt will be used if
1353 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
1356 When -march= or .arch is used, we can't use anything beyond
1357 cpu_arch_isa_flags. */
1359 if (flag_code
== CODE_16BIT
)
1362 max_single_nop_size
= sizeof (f16_patt
) / sizeof (f16_patt
[0]);
1363 /* Limit number of NOPs to 2 in 16-bit mode. */
1364 max_number_of_nops
= 2;
1368 if (fragP
->tc_frag_data
.isa
== PROCESSOR_UNKNOWN
)
1370 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1371 switch (cpu_arch_tune
)
1373 case PROCESSOR_UNKNOWN
:
1374 /* We use cpu_arch_isa_flags to check if we SHOULD
1375 optimize with nops. */
1376 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1381 case PROCESSOR_PENTIUM4
:
1382 case PROCESSOR_NOCONA
:
1383 case PROCESSOR_CORE
:
1384 case PROCESSOR_CORE2
:
1385 case PROCESSOR_COREI7
:
1386 case PROCESSOR_L1OM
:
1387 case PROCESSOR_K1OM
:
1388 case PROCESSOR_GENERIC64
:
1390 case PROCESSOR_ATHLON
:
1392 case PROCESSOR_AMDFAM10
:
1394 case PROCESSOR_ZNVER
:
1398 case PROCESSOR_I386
:
1399 case PROCESSOR_I486
:
1400 case PROCESSOR_PENTIUM
:
1401 case PROCESSOR_PENTIUMPRO
:
1402 case PROCESSOR_IAMCU
:
1403 case PROCESSOR_GENERIC32
:
1410 switch (fragP
->tc_frag_data
.tune
)
1412 case PROCESSOR_UNKNOWN
:
1413 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1414 PROCESSOR_UNKNOWN. */
1418 case PROCESSOR_I386
:
1419 case PROCESSOR_I486
:
1420 case PROCESSOR_PENTIUM
:
1421 case PROCESSOR_IAMCU
:
1423 case PROCESSOR_ATHLON
:
1425 case PROCESSOR_AMDFAM10
:
1427 case PROCESSOR_ZNVER
:
1429 case PROCESSOR_GENERIC32
:
1430 /* We use cpu_arch_isa_flags to check if we CAN optimize
1432 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1437 case PROCESSOR_PENTIUMPRO
:
1438 case PROCESSOR_PENTIUM4
:
1439 case PROCESSOR_NOCONA
:
1440 case PROCESSOR_CORE
:
1441 case PROCESSOR_CORE2
:
1442 case PROCESSOR_COREI7
:
1443 case PROCESSOR_L1OM
:
1444 case PROCESSOR_K1OM
:
1445 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1450 case PROCESSOR_GENERIC64
:
1456 if (patt
== f32_patt
)
1458 max_single_nop_size
= sizeof (f32_patt
) / sizeof (f32_patt
[0]);
1459 /* Limit number of NOPs to 2 for older processors. */
1460 max_number_of_nops
= 2;
1464 max_single_nop_size
= sizeof (alt_patt
) / sizeof (alt_patt
[0]);
1465 /* Limit number of NOPs to 7 for newer processors. */
1466 max_number_of_nops
= 7;
1471 limit
= max_single_nop_size
;
1473 if (fragP
->fr_type
== rs_fill_nop
)
1475 /* Output NOPs for .nop directive. */
1476 if (limit
> max_single_nop_size
)
1478 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
1479 _("invalid single nop size: %d "
1480 "(expect within [0, %d])"),
1481 limit
, max_single_nop_size
);
1486 fragP
->fr_var
= count
;
1488 if ((count
/ max_single_nop_size
) > max_number_of_nops
)
1490 /* Generate jump over NOPs. */
1491 offsetT disp
= count
- 2;
1492 if (fits_in_imm7 (disp
))
1494 /* Use "jmp disp8" if possible. */
1496 where
[0] = jump_disp8
[0];
1502 unsigned int size_of_jump
;
1504 if (flag_code
== CODE_16BIT
)
1506 where
[0] = jump16_disp32
[0];
1507 where
[1] = jump16_disp32
[1];
1512 where
[0] = jump32_disp32
[0];
1516 count
-= size_of_jump
+ 4;
1517 if (!fits_in_imm31 (count
))
1519 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
1520 _("jump over nop padding out of range"));
1524 md_number_to_chars (where
+ size_of_jump
, count
, 4);
1525 where
+= size_of_jump
+ 4;
1529 /* Generate multiple NOPs. */
1530 i386_output_nops (where
, patt
, count
, limit
);
1534 operand_type_all_zero (const union i386_operand_type
*x
)
1536 switch (ARRAY_SIZE(x
->array
))
1547 return !x
->array
[0];
1554 operand_type_set (union i386_operand_type
*x
, unsigned int v
)
1556 switch (ARRAY_SIZE(x
->array
))
1574 operand_type_equal (const union i386_operand_type
*x
,
1575 const union i386_operand_type
*y
)
1577 switch (ARRAY_SIZE(x
->array
))
1580 if (x
->array
[2] != y
->array
[2])
1584 if (x
->array
[1] != y
->array
[1])
1588 return x
->array
[0] == y
->array
[0];
1596 cpu_flags_all_zero (const union i386_cpu_flags
*x
)
1598 switch (ARRAY_SIZE(x
->array
))
1613 return !x
->array
[0];
1620 cpu_flags_equal (const union i386_cpu_flags
*x
,
1621 const union i386_cpu_flags
*y
)
1623 switch (ARRAY_SIZE(x
->array
))
1626 if (x
->array
[3] != y
->array
[3])
1630 if (x
->array
[2] != y
->array
[2])
1634 if (x
->array
[1] != y
->array
[1])
1638 return x
->array
[0] == y
->array
[0];
1646 cpu_flags_check_cpu64 (i386_cpu_flags f
)
1648 return !((flag_code
== CODE_64BIT
&& f
.bitfield
.cpuno64
)
1649 || (flag_code
!= CODE_64BIT
&& f
.bitfield
.cpu64
));
1652 static INLINE i386_cpu_flags
1653 cpu_flags_and (i386_cpu_flags x
, i386_cpu_flags y
)
1655 switch (ARRAY_SIZE (x
.array
))
1658 x
.array
[3] &= y
.array
[3];
1661 x
.array
[2] &= y
.array
[2];
1664 x
.array
[1] &= y
.array
[1];
1667 x
.array
[0] &= y
.array
[0];
1675 static INLINE i386_cpu_flags
1676 cpu_flags_or (i386_cpu_flags x
, i386_cpu_flags y
)
1678 switch (ARRAY_SIZE (x
.array
))
1681 x
.array
[3] |= y
.array
[3];
1684 x
.array
[2] |= y
.array
[2];
1687 x
.array
[1] |= y
.array
[1];
1690 x
.array
[0] |= y
.array
[0];
1698 static INLINE i386_cpu_flags
1699 cpu_flags_and_not (i386_cpu_flags x
, i386_cpu_flags y
)
1701 switch (ARRAY_SIZE (x
.array
))
1704 x
.array
[3] &= ~y
.array
[3];
1707 x
.array
[2] &= ~y
.array
[2];
1710 x
.array
[1] &= ~y
.array
[1];
1713 x
.array
[0] &= ~y
.array
[0];
1721 #define CPU_FLAGS_ARCH_MATCH 0x1
1722 #define CPU_FLAGS_64BIT_MATCH 0x2
1724 #define CPU_FLAGS_PERFECT_MATCH \
1725 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_64BIT_MATCH)
1727 /* Return CPU flags match bits. */
1730 cpu_flags_match (const insn_template
*t
)
1732 i386_cpu_flags x
= t
->cpu_flags
;
1733 int match
= cpu_flags_check_cpu64 (x
) ? CPU_FLAGS_64BIT_MATCH
: 0;
1735 x
.bitfield
.cpu64
= 0;
1736 x
.bitfield
.cpuno64
= 0;
1738 if (cpu_flags_all_zero (&x
))
1740 /* This instruction is available on all archs. */
1741 match
|= CPU_FLAGS_ARCH_MATCH
;
1745 /* This instruction is available only on some archs. */
1746 i386_cpu_flags cpu
= cpu_arch_flags
;
1748 /* AVX512VL is no standalone feature - match it and then strip it. */
1749 if (x
.bitfield
.cpuavx512vl
&& !cpu
.bitfield
.cpuavx512vl
)
1751 x
.bitfield
.cpuavx512vl
= 0;
1753 cpu
= cpu_flags_and (x
, cpu
);
1754 if (!cpu_flags_all_zero (&cpu
))
1756 if (x
.bitfield
.cpuavx
)
1758 /* We need to check a few extra flags with AVX. */
1759 if (cpu
.bitfield
.cpuavx
1760 && (!t
->opcode_modifier
.sse2avx
|| sse2avx
)
1761 && (!x
.bitfield
.cpuaes
|| cpu
.bitfield
.cpuaes
)
1762 && (!x
.bitfield
.cpugfni
|| cpu
.bitfield
.cpugfni
)
1763 && (!x
.bitfield
.cpupclmul
|| cpu
.bitfield
.cpupclmul
))
1764 match
|= CPU_FLAGS_ARCH_MATCH
;
1766 else if (x
.bitfield
.cpuavx512f
)
1768 /* We need to check a few extra flags with AVX512F. */
1769 if (cpu
.bitfield
.cpuavx512f
1770 && (!x
.bitfield
.cpugfni
|| cpu
.bitfield
.cpugfni
)
1771 && (!x
.bitfield
.cpuvaes
|| cpu
.bitfield
.cpuvaes
)
1772 && (!x
.bitfield
.cpuvpclmulqdq
|| cpu
.bitfield
.cpuvpclmulqdq
))
1773 match
|= CPU_FLAGS_ARCH_MATCH
;
1776 match
|= CPU_FLAGS_ARCH_MATCH
;
1782 static INLINE i386_operand_type
1783 operand_type_and (i386_operand_type x
, i386_operand_type y
)
1785 switch (ARRAY_SIZE (x
.array
))
1788 x
.array
[2] &= y
.array
[2];
1791 x
.array
[1] &= y
.array
[1];
1794 x
.array
[0] &= y
.array
[0];
1802 static INLINE i386_operand_type
1803 operand_type_and_not (i386_operand_type x
, i386_operand_type y
)
1805 switch (ARRAY_SIZE (x
.array
))
1808 x
.array
[2] &= ~y
.array
[2];
1811 x
.array
[1] &= ~y
.array
[1];
1814 x
.array
[0] &= ~y
.array
[0];
1822 static INLINE i386_operand_type
1823 operand_type_or (i386_operand_type x
, i386_operand_type y
)
1825 switch (ARRAY_SIZE (x
.array
))
1828 x
.array
[2] |= y
.array
[2];
1831 x
.array
[1] |= y
.array
[1];
1834 x
.array
[0] |= y
.array
[0];
1842 static INLINE i386_operand_type
1843 operand_type_xor (i386_operand_type x
, i386_operand_type y
)
1845 switch (ARRAY_SIZE (x
.array
))
1848 x
.array
[2] ^= y
.array
[2];
1851 x
.array
[1] ^= y
.array
[1];
1854 x
.array
[0] ^= y
.array
[0];
1862 static const i386_operand_type acc32
= OPERAND_TYPE_ACC32
;
1863 static const i386_operand_type acc64
= OPERAND_TYPE_ACC64
;
1864 static const i386_operand_type disp16
= OPERAND_TYPE_DISP16
;
1865 static const i386_operand_type disp32
= OPERAND_TYPE_DISP32
;
1866 static const i386_operand_type disp32s
= OPERAND_TYPE_DISP32S
;
1867 static const i386_operand_type disp16_32
= OPERAND_TYPE_DISP16_32
;
1868 static const i386_operand_type anydisp
1869 = OPERAND_TYPE_ANYDISP
;
1870 static const i386_operand_type regxmm
= OPERAND_TYPE_REGXMM
;
1871 static const i386_operand_type regmask
= OPERAND_TYPE_REGMASK
;
1872 static const i386_operand_type imm8
= OPERAND_TYPE_IMM8
;
1873 static const i386_operand_type imm8s
= OPERAND_TYPE_IMM8S
;
1874 static const i386_operand_type imm16
= OPERAND_TYPE_IMM16
;
1875 static const i386_operand_type imm32
= OPERAND_TYPE_IMM32
;
1876 static const i386_operand_type imm32s
= OPERAND_TYPE_IMM32S
;
1877 static const i386_operand_type imm64
= OPERAND_TYPE_IMM64
;
1878 static const i386_operand_type imm16_32
= OPERAND_TYPE_IMM16_32
;
1879 static const i386_operand_type imm16_32s
= OPERAND_TYPE_IMM16_32S
;
1880 static const i386_operand_type imm16_32_32s
= OPERAND_TYPE_IMM16_32_32S
;
1881 static const i386_operand_type vec_imm4
= OPERAND_TYPE_VEC_IMM4
;
1892 operand_type_check (i386_operand_type t
, enum operand_type c
)
1897 return t
.bitfield
.reg
;
1900 return (t
.bitfield
.imm8
1904 || t
.bitfield
.imm32s
1905 || t
.bitfield
.imm64
);
1908 return (t
.bitfield
.disp8
1909 || t
.bitfield
.disp16
1910 || t
.bitfield
.disp32
1911 || t
.bitfield
.disp32s
1912 || t
.bitfield
.disp64
);
1915 return (t
.bitfield
.disp8
1916 || t
.bitfield
.disp16
1917 || t
.bitfield
.disp32
1918 || t
.bitfield
.disp32s
1919 || t
.bitfield
.disp64
1920 || t
.bitfield
.baseindex
);
1929 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit/80bit size
1930 between operand GIVEN and opeand WANTED for instruction template T. */
1933 match_operand_size (const insn_template
*t
, unsigned int wanted
,
1936 return !((i
.types
[given
].bitfield
.byte
1937 && !t
->operand_types
[wanted
].bitfield
.byte
)
1938 || (i
.types
[given
].bitfield
.word
1939 && !t
->operand_types
[wanted
].bitfield
.word
)
1940 || (i
.types
[given
].bitfield
.dword
1941 && !t
->operand_types
[wanted
].bitfield
.dword
)
1942 || (i
.types
[given
].bitfield
.qword
1943 && !t
->operand_types
[wanted
].bitfield
.qword
)
1944 || (i
.types
[given
].bitfield
.tbyte
1945 && !t
->operand_types
[wanted
].bitfield
.tbyte
));
1948 /* Return 1 if there is no conflict in SIMD register between operand
1949 GIVEN and opeand WANTED for instruction template T. */
1952 match_simd_size (const insn_template
*t
, unsigned int wanted
,
1955 return !((i
.types
[given
].bitfield
.xmmword
1956 && !t
->operand_types
[wanted
].bitfield
.xmmword
)
1957 || (i
.types
[given
].bitfield
.ymmword
1958 && !t
->operand_types
[wanted
].bitfield
.ymmword
)
1959 || (i
.types
[given
].bitfield
.zmmword
1960 && !t
->operand_types
[wanted
].bitfield
.zmmword
));
1963 /* Return 1 if there is no conflict in any size between operand GIVEN
1964 and opeand WANTED for instruction template T. */
1967 match_mem_size (const insn_template
*t
, unsigned int wanted
,
1970 return (match_operand_size (t
, wanted
, given
)
1971 && !((i
.types
[given
].bitfield
.unspecified
1973 && !t
->operand_types
[wanted
].bitfield
.unspecified
)
1974 || (i
.types
[given
].bitfield
.fword
1975 && !t
->operand_types
[wanted
].bitfield
.fword
)
1976 /* For scalar opcode templates to allow register and memory
1977 operands at the same time, some special casing is needed
1978 here. Also for v{,p}broadcast*, {,v}pmov{s,z}*, and
1979 down-conversion vpmov*. */
1980 || ((t
->operand_types
[wanted
].bitfield
.regsimd
1981 && !t
->opcode_modifier
.broadcast
1982 && (t
->operand_types
[wanted
].bitfield
.byte
1983 || t
->operand_types
[wanted
].bitfield
.word
1984 || t
->operand_types
[wanted
].bitfield
.dword
1985 || t
->operand_types
[wanted
].bitfield
.qword
))
1986 ? (i
.types
[given
].bitfield
.xmmword
1987 || i
.types
[given
].bitfield
.ymmword
1988 || i
.types
[given
].bitfield
.zmmword
)
1989 : !match_simd_size(t
, wanted
, given
))));
1992 /* Return value has MATCH_STRAIGHT set if there is no size conflict on any
1993 operands for instruction template T, and it has MATCH_REVERSE set if there
1994 is no size conflict on any operands for the template with operands reversed
1995 (and the template allows for reversing in the first place). */
1997 #define MATCH_STRAIGHT 1
1998 #define MATCH_REVERSE 2
2000 static INLINE
unsigned int
2001 operand_size_match (const insn_template
*t
)
2003 unsigned int j
, match
= MATCH_STRAIGHT
;
2005 /* Don't check jump instructions. */
2006 if (t
->opcode_modifier
.jump
2007 || t
->opcode_modifier
.jumpbyte
2008 || t
->opcode_modifier
.jumpdword
2009 || t
->opcode_modifier
.jumpintersegment
)
2012 /* Check memory and accumulator operand size. */
2013 for (j
= 0; j
< i
.operands
; j
++)
2015 if (!i
.types
[j
].bitfield
.reg
&& !i
.types
[j
].bitfield
.regsimd
2016 && t
->operand_types
[j
].bitfield
.anysize
)
2019 if (t
->operand_types
[j
].bitfield
.reg
2020 && !match_operand_size (t
, j
, j
))
2026 if (t
->operand_types
[j
].bitfield
.regsimd
2027 && !match_simd_size (t
, j
, j
))
2033 if (t
->operand_types
[j
].bitfield
.acc
2034 && (!match_operand_size (t
, j
, j
) || !match_simd_size (t
, j
, j
)))
2040 if ((i
.flags
[j
] & Operand_Mem
) && !match_mem_size (t
, j
, j
))
2047 if (!t
->opcode_modifier
.d
)
2051 i
.error
= operand_size_mismatch
;
2055 /* Check reverse. */
2056 gas_assert (i
.operands
>= 2 && i
.operands
<= 3);
2058 for (j
= 0; j
< i
.operands
; j
++)
2060 unsigned int given
= i
.operands
- j
- 1;
2062 if (t
->operand_types
[j
].bitfield
.reg
2063 && !match_operand_size (t
, j
, given
))
2066 if (t
->operand_types
[j
].bitfield
.regsimd
2067 && !match_simd_size (t
, j
, given
))
2070 if (t
->operand_types
[j
].bitfield
.acc
2071 && (!match_operand_size (t
, j
, given
)
2072 || !match_simd_size (t
, j
, given
)))
2075 if ((i
.flags
[given
] & Operand_Mem
) && !match_mem_size (t
, j
, given
))
2079 return match
| MATCH_REVERSE
;
2083 operand_type_match (i386_operand_type overlap
,
2084 i386_operand_type given
)
2086 i386_operand_type temp
= overlap
;
2088 temp
.bitfield
.jumpabsolute
= 0;
2089 temp
.bitfield
.unspecified
= 0;
2090 temp
.bitfield
.byte
= 0;
2091 temp
.bitfield
.word
= 0;
2092 temp
.bitfield
.dword
= 0;
2093 temp
.bitfield
.fword
= 0;
2094 temp
.bitfield
.qword
= 0;
2095 temp
.bitfield
.tbyte
= 0;
2096 temp
.bitfield
.xmmword
= 0;
2097 temp
.bitfield
.ymmword
= 0;
2098 temp
.bitfield
.zmmword
= 0;
2099 if (operand_type_all_zero (&temp
))
2102 if (given
.bitfield
.baseindex
== overlap
.bitfield
.baseindex
2103 && given
.bitfield
.jumpabsolute
== overlap
.bitfield
.jumpabsolute
)
2107 i
.error
= operand_type_mismatch
;
2111 /* If given types g0 and g1 are registers they must be of the same type
2112 unless the expected operand type register overlap is null.
2113 Memory operand size of certain SIMD instructions is also being checked
2117 operand_type_register_match (i386_operand_type g0
,
2118 i386_operand_type t0
,
2119 i386_operand_type g1
,
2120 i386_operand_type t1
)
2122 if (!g0
.bitfield
.reg
2123 && !g0
.bitfield
.regsimd
2124 && (!operand_type_check (g0
, anymem
)
2125 || g0
.bitfield
.unspecified
2126 || !t0
.bitfield
.regsimd
))
2129 if (!g1
.bitfield
.reg
2130 && !g1
.bitfield
.regsimd
2131 && (!operand_type_check (g1
, anymem
)
2132 || g1
.bitfield
.unspecified
2133 || !t1
.bitfield
.regsimd
))
2136 if (g0
.bitfield
.byte
== g1
.bitfield
.byte
2137 && g0
.bitfield
.word
== g1
.bitfield
.word
2138 && g0
.bitfield
.dword
== g1
.bitfield
.dword
2139 && g0
.bitfield
.qword
== g1
.bitfield
.qword
2140 && g0
.bitfield
.xmmword
== g1
.bitfield
.xmmword
2141 && g0
.bitfield
.ymmword
== g1
.bitfield
.ymmword
2142 && g0
.bitfield
.zmmword
== g1
.bitfield
.zmmword
)
2145 if (!(t0
.bitfield
.byte
& t1
.bitfield
.byte
)
2146 && !(t0
.bitfield
.word
& t1
.bitfield
.word
)
2147 && !(t0
.bitfield
.dword
& t1
.bitfield
.dword
)
2148 && !(t0
.bitfield
.qword
& t1
.bitfield
.qword
)
2149 && !(t0
.bitfield
.xmmword
& t1
.bitfield
.xmmword
)
2150 && !(t0
.bitfield
.ymmword
& t1
.bitfield
.ymmword
)
2151 && !(t0
.bitfield
.zmmword
& t1
.bitfield
.zmmword
))
2154 i
.error
= register_type_mismatch
;
2159 static INLINE
unsigned int
2160 register_number (const reg_entry
*r
)
2162 unsigned int nr
= r
->reg_num
;
2164 if (r
->reg_flags
& RegRex
)
2167 if (r
->reg_flags
& RegVRex
)
2173 static INLINE
unsigned int
2174 mode_from_disp_size (i386_operand_type t
)
2176 if (t
.bitfield
.disp8
)
2178 else if (t
.bitfield
.disp16
2179 || t
.bitfield
.disp32
2180 || t
.bitfield
.disp32s
)
2187 fits_in_signed_byte (addressT num
)
2189 return num
+ 0x80 <= 0xff;
2193 fits_in_unsigned_byte (addressT num
)
2199 fits_in_unsigned_word (addressT num
)
2201 return num
<= 0xffff;
2205 fits_in_signed_word (addressT num
)
2207 return num
+ 0x8000 <= 0xffff;
2211 fits_in_signed_long (addressT num ATTRIBUTE_UNUSED
)
2216 return num
+ 0x80000000 <= 0xffffffff;
2218 } /* fits_in_signed_long() */
2221 fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED
)
2226 return num
<= 0xffffffff;
2228 } /* fits_in_unsigned_long() */
2231 fits_in_disp8 (offsetT num
)
2233 int shift
= i
.memshift
;
2239 mask
= (1 << shift
) - 1;
2241 /* Return 0 if NUM isn't properly aligned. */
2245 /* Check if NUM will fit in 8bit after shift. */
2246 return fits_in_signed_byte (num
>> shift
);
2250 fits_in_imm4 (offsetT num
)
2252 return (num
& 0xf) == num
;
2255 static i386_operand_type
2256 smallest_imm_type (offsetT num
)
2258 i386_operand_type t
;
2260 operand_type_set (&t
, 0);
2261 t
.bitfield
.imm64
= 1;
2263 if (cpu_arch_tune
!= PROCESSOR_I486
&& num
== 1)
2265 /* This code is disabled on the 486 because all the Imm1 forms
2266 in the opcode table are slower on the i486. They're the
2267 versions with the implicitly specified single-position
2268 displacement, which has another syntax if you really want to
2270 t
.bitfield
.imm1
= 1;
2271 t
.bitfield
.imm8
= 1;
2272 t
.bitfield
.imm8s
= 1;
2273 t
.bitfield
.imm16
= 1;
2274 t
.bitfield
.imm32
= 1;
2275 t
.bitfield
.imm32s
= 1;
2277 else if (fits_in_signed_byte (num
))
2279 t
.bitfield
.imm8
= 1;
2280 t
.bitfield
.imm8s
= 1;
2281 t
.bitfield
.imm16
= 1;
2282 t
.bitfield
.imm32
= 1;
2283 t
.bitfield
.imm32s
= 1;
2285 else if (fits_in_unsigned_byte (num
))
2287 t
.bitfield
.imm8
= 1;
2288 t
.bitfield
.imm16
= 1;
2289 t
.bitfield
.imm32
= 1;
2290 t
.bitfield
.imm32s
= 1;
2292 else if (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
2294 t
.bitfield
.imm16
= 1;
2295 t
.bitfield
.imm32
= 1;
2296 t
.bitfield
.imm32s
= 1;
2298 else if (fits_in_signed_long (num
))
2300 t
.bitfield
.imm32
= 1;
2301 t
.bitfield
.imm32s
= 1;
2303 else if (fits_in_unsigned_long (num
))
2304 t
.bitfield
.imm32
= 1;
2310 offset_in_range (offsetT val
, int size
)
2316 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
2317 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
2318 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
2320 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
2326 /* If BFD64, sign extend val for 32bit address mode. */
2327 if (flag_code
!= CODE_64BIT
2328 || i
.prefix
[ADDR_PREFIX
])
2329 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
2330 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
2333 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
2335 char buf1
[40], buf2
[40];
2337 sprint_value (buf1
, val
);
2338 sprint_value (buf2
, val
& mask
);
2339 as_warn (_("%s shortened to %s"), buf1
, buf2
);
2354 a. PREFIX_EXIST if attempting to add a prefix where one from the
2355 same class already exists.
2356 b. PREFIX_LOCK if lock prefix is added.
2357 c. PREFIX_REP if rep/repne prefix is added.
2358 d. PREFIX_DS if ds prefix is added.
2359 e. PREFIX_OTHER if other prefix is added.
2362 static enum PREFIX_GROUP
2363 add_prefix (unsigned int prefix
)
2365 enum PREFIX_GROUP ret
= PREFIX_OTHER
;
2368 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
2369 && flag_code
== CODE_64BIT
)
2371 if ((i
.prefix
[REX_PREFIX
] & prefix
& REX_W
)
2372 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_R
)
2373 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_X
)
2374 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_B
))
2385 case DS_PREFIX_OPCODE
:
2388 case CS_PREFIX_OPCODE
:
2389 case ES_PREFIX_OPCODE
:
2390 case FS_PREFIX_OPCODE
:
2391 case GS_PREFIX_OPCODE
:
2392 case SS_PREFIX_OPCODE
:
2396 case REPNE_PREFIX_OPCODE
:
2397 case REPE_PREFIX_OPCODE
:
2402 case LOCK_PREFIX_OPCODE
:
2411 case ADDR_PREFIX_OPCODE
:
2415 case DATA_PREFIX_OPCODE
:
2419 if (i
.prefix
[q
] != 0)
2427 i
.prefix
[q
] |= prefix
;
2430 as_bad (_("same type of prefix used twice"));
2436 update_code_flag (int value
, int check
)
2438 PRINTF_LIKE ((*as_error
));
2440 flag_code
= (enum flag_code
) value
;
2441 if (flag_code
== CODE_64BIT
)
2443 cpu_arch_flags
.bitfield
.cpu64
= 1;
2444 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2448 cpu_arch_flags
.bitfield
.cpu64
= 0;
2449 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2451 if (value
== CODE_64BIT
&& !cpu_arch_flags
.bitfield
.cpulm
)
2454 as_error
= as_fatal
;
2457 (*as_error
) (_("64bit mode not supported on `%s'."),
2458 cpu_arch_name
? cpu_arch_name
: default_arch
);
2460 if (value
== CODE_32BIT
&& !cpu_arch_flags
.bitfield
.cpui386
)
2463 as_error
= as_fatal
;
2466 (*as_error
) (_("32bit mode not supported on `%s'."),
2467 cpu_arch_name
? cpu_arch_name
: default_arch
);
2469 stackop_size
= '\0';
2473 set_code_flag (int value
)
2475 update_code_flag (value
, 0);
2479 set_16bit_gcc_code_flag (int new_code_flag
)
2481 flag_code
= (enum flag_code
) new_code_flag
;
2482 if (flag_code
!= CODE_16BIT
)
2484 cpu_arch_flags
.bitfield
.cpu64
= 0;
2485 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2486 stackop_size
= LONG_MNEM_SUFFIX
;
2490 set_intel_syntax (int syntax_flag
)
2492 /* Find out if register prefixing is specified. */
2493 int ask_naked_reg
= 0;
2496 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2499 int e
= get_symbol_name (&string
);
2501 if (strcmp (string
, "prefix") == 0)
2503 else if (strcmp (string
, "noprefix") == 0)
2506 as_bad (_("bad argument to syntax directive."));
2507 (void) restore_line_pointer (e
);
2509 demand_empty_rest_of_line ();
2511 intel_syntax
= syntax_flag
;
2513 if (ask_naked_reg
== 0)
2514 allow_naked_reg
= (intel_syntax
2515 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
2517 allow_naked_reg
= (ask_naked_reg
< 0);
2519 expr_set_rank (O_full_ptr
, syntax_flag
? 10 : 0);
2521 identifier_chars
['%'] = intel_syntax
&& allow_naked_reg
? '%' : 0;
2522 identifier_chars
['$'] = intel_syntax
? '$' : 0;
2523 register_prefix
= allow_naked_reg
? "" : "%";
2527 set_intel_mnemonic (int mnemonic_flag
)
2529 intel_mnemonic
= mnemonic_flag
;
2533 set_allow_index_reg (int flag
)
2535 allow_index_reg
= flag
;
2539 set_check (int what
)
2541 enum check_kind
*kind
;
2546 kind
= &operand_check
;
2557 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2560 int e
= get_symbol_name (&string
);
2562 if (strcmp (string
, "none") == 0)
2564 else if (strcmp (string
, "warning") == 0)
2565 *kind
= check_warning
;
2566 else if (strcmp (string
, "error") == 0)
2567 *kind
= check_error
;
2569 as_bad (_("bad argument to %s_check directive."), str
);
2570 (void) restore_line_pointer (e
);
2573 as_bad (_("missing argument for %s_check directive"), str
);
2575 demand_empty_rest_of_line ();
2579 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED
,
2580 i386_cpu_flags new_flag ATTRIBUTE_UNUSED
)
2582 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2583 static const char *arch
;
2585 /* Intel LIOM is only supported on ELF. */
2591 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2592 use default_arch. */
2593 arch
= cpu_arch_name
;
2595 arch
= default_arch
;
2598 /* If we are targeting Intel MCU, we must enable it. */
2599 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_IAMCU
2600 || new_flag
.bitfield
.cpuiamcu
)
2603 /* If we are targeting Intel L1OM, we must enable it. */
2604 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_L1OM
2605 || new_flag
.bitfield
.cpul1om
)
2608 /* If we are targeting Intel K1OM, we must enable it. */
2609 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_K1OM
2610 || new_flag
.bitfield
.cpuk1om
)
2613 as_bad (_("`%s' is not supported on `%s'"), name
, arch
);
2618 set_cpu_arch (int dummy ATTRIBUTE_UNUSED
)
2622 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2625 int e
= get_symbol_name (&string
);
2627 i386_cpu_flags flags
;
2629 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
2631 if (strcmp (string
, cpu_arch
[j
].name
) == 0)
2633 check_cpu_arch_compatible (string
, cpu_arch
[j
].flags
);
2637 cpu_arch_name
= cpu_arch
[j
].name
;
2638 cpu_sub_arch_name
= NULL
;
2639 cpu_arch_flags
= cpu_arch
[j
].flags
;
2640 if (flag_code
== CODE_64BIT
)
2642 cpu_arch_flags
.bitfield
.cpu64
= 1;
2643 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2647 cpu_arch_flags
.bitfield
.cpu64
= 0;
2648 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2650 cpu_arch_isa
= cpu_arch
[j
].type
;
2651 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
2652 if (!cpu_arch_tune_set
)
2654 cpu_arch_tune
= cpu_arch_isa
;
2655 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
2660 flags
= cpu_flags_or (cpu_arch_flags
,
2663 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2665 if (cpu_sub_arch_name
)
2667 char *name
= cpu_sub_arch_name
;
2668 cpu_sub_arch_name
= concat (name
,
2670 (const char *) NULL
);
2674 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
2675 cpu_arch_flags
= flags
;
2676 cpu_arch_isa_flags
= flags
;
2680 = cpu_flags_or (cpu_arch_isa_flags
,
2682 (void) restore_line_pointer (e
);
2683 demand_empty_rest_of_line ();
2688 if (*string
== '.' && j
>= ARRAY_SIZE (cpu_arch
))
2690 /* Disable an ISA extension. */
2691 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
2692 if (strcmp (string
+ 1, cpu_noarch
[j
].name
) == 0)
2694 flags
= cpu_flags_and_not (cpu_arch_flags
,
2695 cpu_noarch
[j
].flags
);
2696 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2698 if (cpu_sub_arch_name
)
2700 char *name
= cpu_sub_arch_name
;
2701 cpu_sub_arch_name
= concat (name
, string
,
2702 (const char *) NULL
);
2706 cpu_sub_arch_name
= xstrdup (string
);
2707 cpu_arch_flags
= flags
;
2708 cpu_arch_isa_flags
= flags
;
2710 (void) restore_line_pointer (e
);
2711 demand_empty_rest_of_line ();
2715 j
= ARRAY_SIZE (cpu_arch
);
2718 if (j
>= ARRAY_SIZE (cpu_arch
))
2719 as_bad (_("no such architecture: `%s'"), string
);
2721 *input_line_pointer
= e
;
2724 as_bad (_("missing cpu architecture"));
2726 no_cond_jump_promotion
= 0;
2727 if (*input_line_pointer
== ','
2728 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
2733 ++input_line_pointer
;
2734 e
= get_symbol_name (&string
);
2736 if (strcmp (string
, "nojumps") == 0)
2737 no_cond_jump_promotion
= 1;
2738 else if (strcmp (string
, "jumps") == 0)
2741 as_bad (_("no such architecture modifier: `%s'"), string
);
2743 (void) restore_line_pointer (e
);
2746 demand_empty_rest_of_line ();
2749 enum bfd_architecture
2752 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2754 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2755 || flag_code
!= CODE_64BIT
)
2756 as_fatal (_("Intel L1OM is 64bit ELF only"));
2757 return bfd_arch_l1om
;
2759 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2761 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2762 || flag_code
!= CODE_64BIT
)
2763 as_fatal (_("Intel K1OM is 64bit ELF only"));
2764 return bfd_arch_k1om
;
2766 else if (cpu_arch_isa
== PROCESSOR_IAMCU
)
2768 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2769 || flag_code
== CODE_64BIT
)
2770 as_fatal (_("Intel MCU is 32bit ELF only"));
2771 return bfd_arch_iamcu
;
2774 return bfd_arch_i386
;
2780 if (!strncmp (default_arch
, "x86_64", 6))
2782 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2784 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2785 || default_arch
[6] != '\0')
2786 as_fatal (_("Intel L1OM is 64bit ELF only"));
2787 return bfd_mach_l1om
;
2789 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2791 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2792 || default_arch
[6] != '\0')
2793 as_fatal (_("Intel K1OM is 64bit ELF only"));
2794 return bfd_mach_k1om
;
2796 else if (default_arch
[6] == '\0')
2797 return bfd_mach_x86_64
;
2799 return bfd_mach_x64_32
;
2801 else if (!strcmp (default_arch
, "i386")
2802 || !strcmp (default_arch
, "iamcu"))
2804 if (cpu_arch_isa
== PROCESSOR_IAMCU
)
2806 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
2807 as_fatal (_("Intel MCU is 32bit ELF only"));
2808 return bfd_mach_i386_iamcu
;
2811 return bfd_mach_i386_i386
;
2814 as_fatal (_("unknown architecture"));
2820 const char *hash_err
;
2822 /* Support pseudo prefixes like {disp32}. */
2823 lex_type
['{'] = LEX_BEGIN_NAME
;
2825 /* Initialize op_hash hash table. */
2826 op_hash
= hash_new ();
2829 const insn_template
*optab
;
2830 templates
*core_optab
;
2832 /* Setup for loop. */
2834 core_optab
= XNEW (templates
);
2835 core_optab
->start
= optab
;
2840 if (optab
->name
== NULL
2841 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
2843 /* different name --> ship out current template list;
2844 add to hash table; & begin anew. */
2845 core_optab
->end
= optab
;
2846 hash_err
= hash_insert (op_hash
,
2848 (void *) core_optab
);
2851 as_fatal (_("can't hash %s: %s"),
2855 if (optab
->name
== NULL
)
2857 core_optab
= XNEW (templates
);
2858 core_optab
->start
= optab
;
2863 /* Initialize reg_hash hash table. */
2864 reg_hash
= hash_new ();
2866 const reg_entry
*regtab
;
2867 unsigned int regtab_size
= i386_regtab_size
;
2869 for (regtab
= i386_regtab
; regtab_size
--; regtab
++)
2871 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (void *) regtab
);
2873 as_fatal (_("can't hash %s: %s"),
2879 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
2884 for (c
= 0; c
< 256; c
++)
2889 mnemonic_chars
[c
] = c
;
2890 register_chars
[c
] = c
;
2891 operand_chars
[c
] = c
;
2893 else if (ISLOWER (c
))
2895 mnemonic_chars
[c
] = c
;
2896 register_chars
[c
] = c
;
2897 operand_chars
[c
] = c
;
2899 else if (ISUPPER (c
))
2901 mnemonic_chars
[c
] = TOLOWER (c
);
2902 register_chars
[c
] = mnemonic_chars
[c
];
2903 operand_chars
[c
] = c
;
2905 else if (c
== '{' || c
== '}')
2907 mnemonic_chars
[c
] = c
;
2908 operand_chars
[c
] = c
;
2911 if (ISALPHA (c
) || ISDIGIT (c
))
2912 identifier_chars
[c
] = c
;
2915 identifier_chars
[c
] = c
;
2916 operand_chars
[c
] = c
;
2921 identifier_chars
['@'] = '@';
2924 identifier_chars
['?'] = '?';
2925 operand_chars
['?'] = '?';
2927 digit_chars
['-'] = '-';
2928 mnemonic_chars
['_'] = '_';
2929 mnemonic_chars
['-'] = '-';
2930 mnemonic_chars
['.'] = '.';
2931 identifier_chars
['_'] = '_';
2932 identifier_chars
['.'] = '.';
2934 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
2935 operand_chars
[(unsigned char) *p
] = *p
;
2938 if (flag_code
== CODE_64BIT
)
2940 #if defined (OBJ_COFF) && defined (TE_PE)
2941 x86_dwarf2_return_column
= (OUTPUT_FLAVOR
== bfd_target_coff_flavour
2944 x86_dwarf2_return_column
= 16;
2946 x86_cie_data_alignment
= -8;
2950 x86_dwarf2_return_column
= 8;
2951 x86_cie_data_alignment
= -4;
2956 i386_print_statistics (FILE *file
)
2958 hash_print_statistics (file
, "i386 opcode", op_hash
);
2959 hash_print_statistics (file
, "i386 register", reg_hash
);
2964 /* Debugging routines for md_assemble. */
2965 static void pte (insn_template
*);
2966 static void pt (i386_operand_type
);
2967 static void pe (expressionS
*);
2968 static void ps (symbolS
*);
2971 pi (char *line
, i386_insn
*x
)
2975 fprintf (stdout
, "%s: template ", line
);
2977 fprintf (stdout
, " address: base %s index %s scale %x\n",
2978 x
->base_reg
? x
->base_reg
->reg_name
: "none",
2979 x
->index_reg
? x
->index_reg
->reg_name
: "none",
2980 x
->log2_scale_factor
);
2981 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
2982 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
2983 fprintf (stdout
, " sib: base %x index %x scale %x\n",
2984 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
2985 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
2986 (x
->rex
& REX_W
) != 0,
2987 (x
->rex
& REX_R
) != 0,
2988 (x
->rex
& REX_X
) != 0,
2989 (x
->rex
& REX_B
) != 0);
2990 for (j
= 0; j
< x
->operands
; j
++)
2992 fprintf (stdout
, " #%d: ", j
+ 1);
2994 fprintf (stdout
, "\n");
2995 if (x
->types
[j
].bitfield
.reg
2996 || x
->types
[j
].bitfield
.regmmx
2997 || x
->types
[j
].bitfield
.regsimd
2998 || x
->types
[j
].bitfield
.sreg2
2999 || x
->types
[j
].bitfield
.sreg3
3000 || x
->types
[j
].bitfield
.control
3001 || x
->types
[j
].bitfield
.debug
3002 || x
->types
[j
].bitfield
.test
)
3003 fprintf (stdout
, "%s\n", x
->op
[j
].regs
->reg_name
);
3004 if (operand_type_check (x
->types
[j
], imm
))
3006 if (operand_type_check (x
->types
[j
], disp
))
3007 pe (x
->op
[j
].disps
);
3012 pte (insn_template
*t
)
3015 fprintf (stdout
, " %d operands ", t
->operands
);
3016 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
3017 if (t
->extension_opcode
!= None
)
3018 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
3019 if (t
->opcode_modifier
.d
)
3020 fprintf (stdout
, "D");
3021 if (t
->opcode_modifier
.w
)
3022 fprintf (stdout
, "W");
3023 fprintf (stdout
, "\n");
3024 for (j
= 0; j
< t
->operands
; j
++)
3026 fprintf (stdout
, " #%d type ", j
+ 1);
3027 pt (t
->operand_types
[j
]);
3028 fprintf (stdout
, "\n");
3035 fprintf (stdout
, " operation %d\n", e
->X_op
);
3036 fprintf (stdout
, " add_number %ld (%lx)\n",
3037 (long) e
->X_add_number
, (long) e
->X_add_number
);
3038 if (e
->X_add_symbol
)
3040 fprintf (stdout
, " add_symbol ");
3041 ps (e
->X_add_symbol
);
3042 fprintf (stdout
, "\n");
3046 fprintf (stdout
, " op_symbol ");
3047 ps (e
->X_op_symbol
);
3048 fprintf (stdout
, "\n");
3055 fprintf (stdout
, "%s type %s%s",
3057 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
3058 segment_name (S_GET_SEGMENT (s
)));
3061 static struct type_name
3063 i386_operand_type mask
;
3066 const type_names
[] =
3068 { OPERAND_TYPE_REG8
, "r8" },
3069 { OPERAND_TYPE_REG16
, "r16" },
3070 { OPERAND_TYPE_REG32
, "r32" },
3071 { OPERAND_TYPE_REG64
, "r64" },
3072 { OPERAND_TYPE_IMM8
, "i8" },
3073 { OPERAND_TYPE_IMM8
, "i8s" },
3074 { OPERAND_TYPE_IMM16
, "i16" },
3075 { OPERAND_TYPE_IMM32
, "i32" },
3076 { OPERAND_TYPE_IMM32S
, "i32s" },
3077 { OPERAND_TYPE_IMM64
, "i64" },
3078 { OPERAND_TYPE_IMM1
, "i1" },
3079 { OPERAND_TYPE_BASEINDEX
, "BaseIndex" },
3080 { OPERAND_TYPE_DISP8
, "d8" },
3081 { OPERAND_TYPE_DISP16
, "d16" },
3082 { OPERAND_TYPE_DISP32
, "d32" },
3083 { OPERAND_TYPE_DISP32S
, "d32s" },
3084 { OPERAND_TYPE_DISP64
, "d64" },
3085 { OPERAND_TYPE_INOUTPORTREG
, "InOutPortReg" },
3086 { OPERAND_TYPE_SHIFTCOUNT
, "ShiftCount" },
3087 { OPERAND_TYPE_CONTROL
, "control reg" },
3088 { OPERAND_TYPE_TEST
, "test reg" },
3089 { OPERAND_TYPE_DEBUG
, "debug reg" },
3090 { OPERAND_TYPE_FLOATREG
, "FReg" },
3091 { OPERAND_TYPE_FLOATACC
, "FAcc" },
3092 { OPERAND_TYPE_SREG2
, "SReg2" },
3093 { OPERAND_TYPE_SREG3
, "SReg3" },
3094 { OPERAND_TYPE_ACC
, "Acc" },
3095 { OPERAND_TYPE_JUMPABSOLUTE
, "Jump Absolute" },
3096 { OPERAND_TYPE_REGMMX
, "rMMX" },
3097 { OPERAND_TYPE_REGXMM
, "rXMM" },
3098 { OPERAND_TYPE_REGYMM
, "rYMM" },
3099 { OPERAND_TYPE_REGZMM
, "rZMM" },
3100 { OPERAND_TYPE_REGMASK
, "Mask reg" },
3101 { OPERAND_TYPE_ESSEG
, "es" },
3105 pt (i386_operand_type t
)
3108 i386_operand_type a
;
3110 for (j
= 0; j
< ARRAY_SIZE (type_names
); j
++)
3112 a
= operand_type_and (t
, type_names
[j
].mask
);
3113 if (!operand_type_all_zero (&a
))
3114 fprintf (stdout
, "%s, ", type_names
[j
].name
);
3119 #endif /* DEBUG386 */
3121 static bfd_reloc_code_real_type
3122 reloc (unsigned int size
,
3125 bfd_reloc_code_real_type other
)
3127 if (other
!= NO_RELOC
)
3129 reloc_howto_type
*rel
;
3134 case BFD_RELOC_X86_64_GOT32
:
3135 return BFD_RELOC_X86_64_GOT64
;
3137 case BFD_RELOC_X86_64_GOTPLT64
:
3138 return BFD_RELOC_X86_64_GOTPLT64
;
3140 case BFD_RELOC_X86_64_PLTOFF64
:
3141 return BFD_RELOC_X86_64_PLTOFF64
;
3143 case BFD_RELOC_X86_64_GOTPC32
:
3144 other
= BFD_RELOC_X86_64_GOTPC64
;
3146 case BFD_RELOC_X86_64_GOTPCREL
:
3147 other
= BFD_RELOC_X86_64_GOTPCREL64
;
3149 case BFD_RELOC_X86_64_TPOFF32
:
3150 other
= BFD_RELOC_X86_64_TPOFF64
;
3152 case BFD_RELOC_X86_64_DTPOFF32
:
3153 other
= BFD_RELOC_X86_64_DTPOFF64
;
3159 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3160 if (other
== BFD_RELOC_SIZE32
)
3163 other
= BFD_RELOC_SIZE64
;
3166 as_bad (_("there are no pc-relative size relocations"));
3172 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
3173 if (size
== 4 && (flag_code
!= CODE_64BIT
|| disallow_64bit_reloc
))
3176 rel
= bfd_reloc_type_lookup (stdoutput
, other
);
3178 as_bad (_("unknown relocation (%u)"), other
);
3179 else if (size
!= bfd_get_reloc_size (rel
))
3180 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
3181 bfd_get_reloc_size (rel
),
3183 else if (pcrel
&& !rel
->pc_relative
)
3184 as_bad (_("non-pc-relative relocation for pc-relative field"));
3185 else if ((rel
->complain_on_overflow
== complain_overflow_signed
3187 || (rel
->complain_on_overflow
== complain_overflow_unsigned
3189 as_bad (_("relocated field and relocation type differ in signedness"));
3198 as_bad (_("there are no unsigned pc-relative relocations"));
3201 case 1: return BFD_RELOC_8_PCREL
;
3202 case 2: return BFD_RELOC_16_PCREL
;
3203 case 4: return BFD_RELOC_32_PCREL
;
3204 case 8: return BFD_RELOC_64_PCREL
;
3206 as_bad (_("cannot do %u byte pc-relative relocation"), size
);
3213 case 4: return BFD_RELOC_X86_64_32S
;
3218 case 1: return BFD_RELOC_8
;
3219 case 2: return BFD_RELOC_16
;
3220 case 4: return BFD_RELOC_32
;
3221 case 8: return BFD_RELOC_64
;
3223 as_bad (_("cannot do %s %u byte relocation"),
3224 sign
> 0 ? "signed" : "unsigned", size
);
3230 /* Here we decide which fixups can be adjusted to make them relative to
3231 the beginning of the section instead of the symbol. Basically we need
3232 to make sure that the dynamic relocations are done correctly, so in
3233 some cases we force the original symbol to be used. */
3236 tc_i386_fix_adjustable (fixS
*fixP ATTRIBUTE_UNUSED
)
3238 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3242 /* Don't adjust pc-relative references to merge sections in 64-bit
3244 if (use_rela_relocations
3245 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
3249 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
3250 and changed later by validate_fix. */
3251 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
3252 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
3255 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
3256 for size relocations. */
3257 if (fixP
->fx_r_type
== BFD_RELOC_SIZE32
3258 || fixP
->fx_r_type
== BFD_RELOC_SIZE64
3259 || fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
3260 || fixP
->fx_r_type
== BFD_RELOC_386_PLT32
3261 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
3262 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32X
3263 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
3264 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
3265 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
3266 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
3267 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
3268 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
3269 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
3270 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
3271 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTDESC
3272 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_DESC_CALL
3273 || fixP
->fx_r_type
== BFD_RELOC_X86_64_PLT32
3274 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
3275 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
3276 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCRELX
3277 || fixP
->fx_r_type
== BFD_RELOC_X86_64_REX_GOTPCRELX
3278 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
3279 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
3280 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
3281 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
3282 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
3283 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
3284 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
3285 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
3286 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPC32_TLSDESC
3287 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSDESC_CALL
3288 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
3289 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
3296 intel_float_operand (const char *mnemonic
)
3298 /* Note that the value returned is meaningful only for opcodes with (memory)
3299 operands, hence the code here is free to improperly handle opcodes that
3300 have no operands (for better performance and smaller code). */
3302 if (mnemonic
[0] != 'f')
3303 return 0; /* non-math */
3305 switch (mnemonic
[1])
3307 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
3308 the fs segment override prefix not currently handled because no
3309 call path can make opcodes without operands get here */
3311 return 2 /* integer op */;
3313 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
3314 return 3; /* fldcw/fldenv */
3317 if (mnemonic
[2] != 'o' /* fnop */)
3318 return 3; /* non-waiting control op */
3321 if (mnemonic
[2] == 's')
3322 return 3; /* frstor/frstpm */
3325 if (mnemonic
[2] == 'a')
3326 return 3; /* fsave */
3327 if (mnemonic
[2] == 't')
3329 switch (mnemonic
[3])
3331 case 'c': /* fstcw */
3332 case 'd': /* fstdw */
3333 case 'e': /* fstenv */
3334 case 's': /* fsts[gw] */
3340 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
3341 return 0; /* fxsave/fxrstor are not really math ops */
3348 /* Build the VEX prefix. */
3351 build_vex_prefix (const insn_template
*t
)
3353 unsigned int register_specifier
;
3354 unsigned int implied_prefix
;
3355 unsigned int vector_length
;
3357 /* Check register specifier. */
3358 if (i
.vex
.register_specifier
)
3360 register_specifier
=
3361 ~register_number (i
.vex
.register_specifier
) & 0xf;
3362 gas_assert ((i
.vex
.register_specifier
->reg_flags
& RegVRex
) == 0);
3365 register_specifier
= 0xf;
3367 /* Use 2-byte VEX prefix by swapping destination and source operand
3368 if there are more than 1 register operand. */
3369 if (i
.reg_operands
> 1
3370 && i
.vec_encoding
!= vex_encoding_vex3
3371 && i
.dir_encoding
== dir_encoding_default
3372 && i
.operands
== i
.reg_operands
3373 && operand_type_equal (&i
.types
[0], &i
.types
[i
.operands
- 1])
3374 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3375 && (i
.tm
.opcode_modifier
.load
|| i
.tm
.opcode_modifier
.d
)
3378 unsigned int xchg
= i
.operands
- 1;
3379 union i386_op temp_op
;
3380 i386_operand_type temp_type
;
3382 temp_type
= i
.types
[xchg
];
3383 i
.types
[xchg
] = i
.types
[0];
3384 i
.types
[0] = temp_type
;
3385 temp_op
= i
.op
[xchg
];
3386 i
.op
[xchg
] = i
.op
[0];
3389 gas_assert (i
.rm
.mode
== 3);
3393 i
.rm
.regmem
= i
.rm
.reg
;
3396 if (i
.tm
.opcode_modifier
.d
)
3397 i
.tm
.base_opcode
^= (i
.tm
.base_opcode
& 0xee) != 0x6e
3398 ? Opcode_SIMD_FloatD
: Opcode_SIMD_IntD
;
3399 else /* Use the next insn. */
3403 if (i
.tm
.opcode_modifier
.vex
== VEXScalar
)
3404 vector_length
= avxscalar
;
3405 else if (i
.tm
.opcode_modifier
.vex
== VEX256
)
3411 /* Determine vector length from the last multi-length vector
3414 for (op
= t
->operands
; op
--;)
3415 if (t
->operand_types
[op
].bitfield
.xmmword
3416 && t
->operand_types
[op
].bitfield
.ymmword
3417 && i
.types
[op
].bitfield
.ymmword
)
3424 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3429 case DATA_PREFIX_OPCODE
:
3432 case REPE_PREFIX_OPCODE
:
3435 case REPNE_PREFIX_OPCODE
:
3442 /* Use 2-byte VEX prefix if possible. */
3443 if (i
.vec_encoding
!= vex_encoding_vex3
3444 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3445 && i
.tm
.opcode_modifier
.vexw
!= VEXW1
3446 && (i
.rex
& (REX_W
| REX_X
| REX_B
)) == 0)
3448 /* 2-byte VEX prefix. */
3452 i
.vex
.bytes
[0] = 0xc5;
3454 /* Check the REX.R bit. */
3455 r
= (i
.rex
& REX_R
) ? 0 : 1;
3456 i
.vex
.bytes
[1] = (r
<< 7
3457 | register_specifier
<< 3
3458 | vector_length
<< 2
3463 /* 3-byte VEX prefix. */
3468 switch (i
.tm
.opcode_modifier
.vexopcode
)
3472 i
.vex
.bytes
[0] = 0xc4;
3476 i
.vex
.bytes
[0] = 0xc4;
3480 i
.vex
.bytes
[0] = 0xc4;
3484 i
.vex
.bytes
[0] = 0x8f;
3488 i
.vex
.bytes
[0] = 0x8f;
3492 i
.vex
.bytes
[0] = 0x8f;
3498 /* The high 3 bits of the second VEX byte are 1's compliment
3499 of RXB bits from REX. */
3500 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3502 /* Check the REX.W bit and VEXW. */
3503 if (i
.tm
.opcode_modifier
.vexw
== VEXWIG
)
3504 w
= (i
.rex
& REX_W
) ? 1 : 0;
3505 else if (i
.tm
.opcode_modifier
.vexw
)
3506 w
= i
.tm
.opcode_modifier
.vexw
== VEXW1
? 1 : 0;
3508 w
= (i
.rex
& REX_W
) ? 1 : 0;
3510 i
.vex
.bytes
[2] = (w
<< 7
3511 | register_specifier
<< 3
3512 | vector_length
<< 2
3517 static INLINE bfd_boolean
3518 is_evex_encoding (const insn_template
*t
)
3520 return t
->opcode_modifier
.evex
|| t
->opcode_modifier
.disp8memshift
3521 || t
->opcode_modifier
.broadcast
|| t
->opcode_modifier
.masking
3522 || t
->opcode_modifier
.staticrounding
|| t
->opcode_modifier
.sae
;
3525 static INLINE bfd_boolean
3526 is_any_vex_encoding (const insn_template
*t
)
3528 return t
->opcode_modifier
.vex
|| t
->opcode_modifier
.vexopcode
3529 || is_evex_encoding (t
);
3532 /* Build the EVEX prefix. */
3535 build_evex_prefix (void)
3537 unsigned int register_specifier
;
3538 unsigned int implied_prefix
;
3540 rex_byte vrex_used
= 0;
3542 /* Check register specifier. */
3543 if (i
.vex
.register_specifier
)
3545 gas_assert ((i
.vrex
& REX_X
) == 0);
3547 register_specifier
= i
.vex
.register_specifier
->reg_num
;
3548 if ((i
.vex
.register_specifier
->reg_flags
& RegRex
))
3549 register_specifier
+= 8;
3550 /* The upper 16 registers are encoded in the fourth byte of the
3552 if (!(i
.vex
.register_specifier
->reg_flags
& RegVRex
))
3553 i
.vex
.bytes
[3] = 0x8;
3554 register_specifier
= ~register_specifier
& 0xf;
3558 register_specifier
= 0xf;
3560 /* Encode upper 16 vector index register in the fourth byte of
3562 if (!(i
.vrex
& REX_X
))
3563 i
.vex
.bytes
[3] = 0x8;
3568 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3573 case DATA_PREFIX_OPCODE
:
3576 case REPE_PREFIX_OPCODE
:
3579 case REPNE_PREFIX_OPCODE
:
3586 /* 4 byte EVEX prefix. */
3588 i
.vex
.bytes
[0] = 0x62;
3591 switch (i
.tm
.opcode_modifier
.vexopcode
)
3607 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3609 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3611 /* The fifth bit of the second EVEX byte is 1's compliment of the
3612 REX_R bit in VREX. */
3613 if (!(i
.vrex
& REX_R
))
3614 i
.vex
.bytes
[1] |= 0x10;
3618 if ((i
.reg_operands
+ i
.imm_operands
) == i
.operands
)
3620 /* When all operands are registers, the REX_X bit in REX is not
3621 used. We reuse it to encode the upper 16 registers, which is
3622 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3623 as 1's compliment. */
3624 if ((i
.vrex
& REX_B
))
3627 i
.vex
.bytes
[1] &= ~0x40;
3631 /* EVEX instructions shouldn't need the REX prefix. */
3632 i
.vrex
&= ~vrex_used
;
3633 gas_assert (i
.vrex
== 0);
3635 /* Check the REX.W bit and VEXW. */
3636 if (i
.tm
.opcode_modifier
.vexw
== VEXWIG
)
3637 w
= (evexwig
== evexw1
|| (i
.rex
& REX_W
)) ? 1 : 0;
3638 else if (i
.tm
.opcode_modifier
.vexw
)
3639 w
= i
.tm
.opcode_modifier
.vexw
== VEXW1
? 1 : 0;
3641 w
= (i
.rex
& REX_W
) ? 1 : 0;
3643 /* Encode the U bit. */
3644 implied_prefix
|= 0x4;
3646 /* The third byte of the EVEX prefix. */
3647 i
.vex
.bytes
[2] = (w
<< 7 | register_specifier
<< 3 | implied_prefix
);
3649 /* The fourth byte of the EVEX prefix. */
3650 /* The zeroing-masking bit. */
3651 if (i
.mask
&& i
.mask
->zeroing
)
3652 i
.vex
.bytes
[3] |= 0x80;
3654 /* Don't always set the broadcast bit if there is no RC. */
3657 /* Encode the vector length. */
3658 unsigned int vec_length
;
3660 if (!i
.tm
.opcode_modifier
.evex
3661 || i
.tm
.opcode_modifier
.evex
== EVEXDYN
)
3665 /* Determine vector length from the last multi-length vector
3668 for (op
= i
.operands
; op
--;)
3669 if (i
.tm
.operand_types
[op
].bitfield
.xmmword
3670 + i
.tm
.operand_types
[op
].bitfield
.ymmword
3671 + i
.tm
.operand_types
[op
].bitfield
.zmmword
> 1)
3673 if (i
.types
[op
].bitfield
.zmmword
)
3675 i
.tm
.opcode_modifier
.evex
= EVEX512
;
3678 else if (i
.types
[op
].bitfield
.ymmword
)
3680 i
.tm
.opcode_modifier
.evex
= EVEX256
;
3683 else if (i
.types
[op
].bitfield
.xmmword
)
3685 i
.tm
.opcode_modifier
.evex
= EVEX128
;
3688 else if (i
.broadcast
&& (int) op
== i
.broadcast
->operand
)
3690 switch (i
.broadcast
->bytes
)
3693 i
.tm
.opcode_modifier
.evex
= EVEX512
;
3696 i
.tm
.opcode_modifier
.evex
= EVEX256
;
3699 i
.tm
.opcode_modifier
.evex
= EVEX128
;
3708 if (op
>= MAX_OPERANDS
)
3712 switch (i
.tm
.opcode_modifier
.evex
)
3714 case EVEXLIG
: /* LL' is ignored */
3715 vec_length
= evexlig
<< 5;
3718 vec_length
= 0 << 5;
3721 vec_length
= 1 << 5;
3724 vec_length
= 2 << 5;
3730 i
.vex
.bytes
[3] |= vec_length
;
3731 /* Encode the broadcast bit. */
3733 i
.vex
.bytes
[3] |= 0x10;
3737 if (i
.rounding
->type
!= saeonly
)
3738 i
.vex
.bytes
[3] |= 0x10 | (i
.rounding
->type
<< 5);
3740 i
.vex
.bytes
[3] |= 0x10 | (evexrcig
<< 5);
3743 if (i
.mask
&& i
.mask
->mask
)
3744 i
.vex
.bytes
[3] |= i
.mask
->mask
->reg_num
;
3748 process_immext (void)
3752 if ((i
.tm
.cpu_flags
.bitfield
.cpusse3
|| i
.tm
.cpu_flags
.bitfield
.cpusvme
)
3755 /* MONITOR/MWAIT as well as SVME instructions have fixed operands
3756 with an opcode suffix which is coded in the same place as an
3757 8-bit immediate field would be.
3758 Here we check those operands and remove them afterwards. */
3761 for (x
= 0; x
< i
.operands
; x
++)
3762 if (register_number (i
.op
[x
].regs
) != x
)
3763 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3764 register_prefix
, i
.op
[x
].regs
->reg_name
, x
+ 1,
3770 if (i
.tm
.cpu_flags
.bitfield
.cpumwaitx
&& i
.operands
> 0)
3772 /* MONITORX/MWAITX instructions have fixed operands with an opcode
3773 suffix which is coded in the same place as an 8-bit immediate
3775 Here we check those operands and remove them afterwards. */
3778 if (i
.operands
!= 3)
3781 for (x
= 0; x
< 2; x
++)
3782 if (register_number (i
.op
[x
].regs
) != x
)
3783 goto bad_register_operand
;
3785 /* Check for third operand for mwaitx/monitorx insn. */
3786 if (register_number (i
.op
[x
].regs
)
3787 != (x
+ (i
.tm
.extension_opcode
== 0xfb)))
3789 bad_register_operand
:
3790 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3791 register_prefix
, i
.op
[x
].regs
->reg_name
, x
+1,
3798 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
3799 which is coded in the same place as an 8-bit immediate field
3800 would be. Here we fake an 8-bit immediate operand from the
3801 opcode suffix stored in tm.extension_opcode.
3803 AVX instructions also use this encoding, for some of
3804 3 argument instructions. */
3806 gas_assert (i
.imm_operands
<= 1
3808 || (is_any_vex_encoding (&i
.tm
)
3809 && i
.operands
<= 4)));
3811 exp
= &im_expressions
[i
.imm_operands
++];
3812 i
.op
[i
.operands
].imms
= exp
;
3813 i
.types
[i
.operands
] = imm8
;
3815 exp
->X_op
= O_constant
;
3816 exp
->X_add_number
= i
.tm
.extension_opcode
;
3817 i
.tm
.extension_opcode
= None
;
3824 switch (i
.tm
.opcode_modifier
.hleprefixok
)
3829 as_bad (_("invalid instruction `%s' after `%s'"),
3830 i
.tm
.name
, i
.hle_prefix
);
3833 if (i
.prefix
[LOCK_PREFIX
])
3835 as_bad (_("missing `lock' with `%s'"), i
.hle_prefix
);
3839 case HLEPrefixRelease
:
3840 if (i
.prefix
[HLE_PREFIX
] != XRELEASE_PREFIX_OPCODE
)
3842 as_bad (_("instruction `%s' after `xacquire' not allowed"),
3846 if (i
.mem_operands
== 0
3847 || !operand_type_check (i
.types
[i
.operands
- 1], anymem
))
3849 as_bad (_("memory destination needed for instruction `%s'"
3850 " after `xrelease'"), i
.tm
.name
);
3857 /* Try the shortest encoding by shortening operand size. */
3860 optimize_encoding (void)
3864 if (optimize_for_space
3865 && i
.reg_operands
== 1
3866 && i
.imm_operands
== 1
3867 && !i
.types
[1].bitfield
.byte
3868 && i
.op
[0].imms
->X_op
== O_constant
3869 && fits_in_imm7 (i
.op
[0].imms
->X_add_number
)
3870 && ((i
.tm
.base_opcode
== 0xa8
3871 && i
.tm
.extension_opcode
== None
)
3872 || (i
.tm
.base_opcode
== 0xf6
3873 && i
.tm
.extension_opcode
== 0x0)))
3876 test $imm7, %r64/%r32/%r16 -> test $imm7, %r8
3878 unsigned int base_regnum
= i
.op
[1].regs
->reg_num
;
3879 if (flag_code
== CODE_64BIT
|| base_regnum
< 4)
3881 i
.types
[1].bitfield
.byte
= 1;
3882 /* Ignore the suffix. */
3884 if (base_regnum
>= 4
3885 && !(i
.op
[1].regs
->reg_flags
& RegRex
))
3887 /* Handle SP, BP, SI and DI registers. */
3888 if (i
.types
[1].bitfield
.word
)
3890 else if (i
.types
[1].bitfield
.dword
)
3898 else if (flag_code
== CODE_64BIT
3899 && ((i
.types
[1].bitfield
.qword
3900 && i
.reg_operands
== 1
3901 && i
.imm_operands
== 1
3902 && i
.op
[0].imms
->X_op
== O_constant
3903 && ((i
.tm
.base_opcode
== 0xb0
3904 && i
.tm
.extension_opcode
== None
3905 && fits_in_unsigned_long (i
.op
[0].imms
->X_add_number
))
3906 || (fits_in_imm31 (i
.op
[0].imms
->X_add_number
)
3907 && (((i
.tm
.base_opcode
== 0x24
3908 || i
.tm
.base_opcode
== 0xa8)
3909 && i
.tm
.extension_opcode
== None
)
3910 || (i
.tm
.base_opcode
== 0x80
3911 && i
.tm
.extension_opcode
== 0x4)
3912 || ((i
.tm
.base_opcode
== 0xf6
3913 || i
.tm
.base_opcode
== 0xc6)
3914 && i
.tm
.extension_opcode
== 0x0)))))
3915 || (i
.types
[0].bitfield
.qword
3916 && ((i
.reg_operands
== 2
3917 && i
.op
[0].regs
== i
.op
[1].regs
3918 && ((i
.tm
.base_opcode
== 0x30
3919 || i
.tm
.base_opcode
== 0x28)
3920 && i
.tm
.extension_opcode
== None
))
3921 || (i
.reg_operands
== 1
3923 && i
.tm
.base_opcode
== 0x30
3924 && i
.tm
.extension_opcode
== None
)))))
3927 andq $imm31, %r64 -> andl $imm31, %r32
3928 testq $imm31, %r64 -> testl $imm31, %r32
3929 xorq %r64, %r64 -> xorl %r32, %r32
3930 subq %r64, %r64 -> subl %r32, %r32
3931 movq $imm31, %r64 -> movl $imm31, %r32
3932 movq $imm32, %r64 -> movl $imm32, %r32
3934 i
.tm
.opcode_modifier
.norex64
= 1;
3935 if (i
.tm
.base_opcode
== 0xb0 || i
.tm
.base_opcode
== 0xc6)
3938 movq $imm31, %r64 -> movl $imm31, %r32
3939 movq $imm32, %r64 -> movl $imm32, %r32
3941 i
.tm
.operand_types
[0].bitfield
.imm32
= 1;
3942 i
.tm
.operand_types
[0].bitfield
.imm32s
= 0;
3943 i
.tm
.operand_types
[0].bitfield
.imm64
= 0;
3944 i
.types
[0].bitfield
.imm32
= 1;
3945 i
.types
[0].bitfield
.imm32s
= 0;
3946 i
.types
[0].bitfield
.imm64
= 0;
3947 i
.types
[1].bitfield
.dword
= 1;
3948 i
.types
[1].bitfield
.qword
= 0;
3949 if (i
.tm
.base_opcode
== 0xc6)
3952 movq $imm31, %r64 -> movl $imm31, %r32
3954 i
.tm
.base_opcode
= 0xb0;
3955 i
.tm
.extension_opcode
= None
;
3956 i
.tm
.opcode_modifier
.shortform
= 1;
3957 i
.tm
.opcode_modifier
.modrm
= 0;
3961 else if (optimize
> 1
3962 && i
.reg_operands
== 3
3963 && i
.op
[0].regs
== i
.op
[1].regs
3964 && !i
.types
[2].bitfield
.xmmword
3965 && (i
.tm
.opcode_modifier
.vex
3966 || ((!i
.mask
|| i
.mask
->zeroing
)
3968 && is_evex_encoding (&i
.tm
)
3969 && (i
.vec_encoding
!= vex_encoding_evex
3970 || i
.tm
.cpu_flags
.bitfield
.cpuavx512vl
3971 || (i
.tm
.operand_types
[2].bitfield
.zmmword
3972 && i
.types
[2].bitfield
.ymmword
)
3973 || cpu_arch_isa_flags
.bitfield
.cpuavx512vl
)))
3974 && ((i
.tm
.base_opcode
== 0x55
3975 || i
.tm
.base_opcode
== 0x6655
3976 || i
.tm
.base_opcode
== 0x66df
3977 || i
.tm
.base_opcode
== 0x57
3978 || i
.tm
.base_opcode
== 0x6657
3979 || i
.tm
.base_opcode
== 0x66ef
3980 || i
.tm
.base_opcode
== 0x66f8
3981 || i
.tm
.base_opcode
== 0x66f9
3982 || i
.tm
.base_opcode
== 0x66fa
3983 || i
.tm
.base_opcode
== 0x66fb
3984 || i
.tm
.base_opcode
== 0x42
3985 || i
.tm
.base_opcode
== 0x6642
3986 || i
.tm
.base_opcode
== 0x47
3987 || i
.tm
.base_opcode
== 0x6647)
3988 && i
.tm
.extension_opcode
== None
))
3991 VOP, one of vandnps, vandnpd, vxorps, vxorpd, vpsubb, vpsubd,
3993 EVEX VOP %zmmM, %zmmM, %zmmN
3994 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
3995 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3996 EVEX VOP %ymmM, %ymmM, %ymmN
3997 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
3998 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3999 VEX VOP %ymmM, %ymmM, %ymmN
4000 -> VEX VOP %xmmM, %xmmM, %xmmN
4001 VOP, one of vpandn and vpxor:
4002 VEX VOP %ymmM, %ymmM, %ymmN
4003 -> VEX VOP %xmmM, %xmmM, %xmmN
4004 VOP, one of vpandnd and vpandnq:
4005 EVEX VOP %zmmM, %zmmM, %zmmN
4006 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
4007 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
4008 EVEX VOP %ymmM, %ymmM, %ymmN
4009 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
4010 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
4011 VOP, one of vpxord and vpxorq:
4012 EVEX VOP %zmmM, %zmmM, %zmmN
4013 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
4014 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
4015 EVEX VOP %ymmM, %ymmM, %ymmN
4016 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
4017 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
4018 VOP, one of kxord and kxorq:
4019 VEX VOP %kM, %kM, %kN
4020 -> VEX kxorw %kM, %kM, %kN
4021 VOP, one of kandnd and kandnq:
4022 VEX VOP %kM, %kM, %kN
4023 -> VEX kandnw %kM, %kM, %kN
4025 if (is_evex_encoding (&i
.tm
))
4027 if (i
.vec_encoding
== vex_encoding_evex
)
4028 i
.tm
.opcode_modifier
.evex
= EVEX128
;
4031 i
.tm
.opcode_modifier
.vex
= VEX128
;
4032 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4033 i
.tm
.opcode_modifier
.evex
= 0;
4036 else if (i
.tm
.operand_types
[0].bitfield
.regmask
)
4038 i
.tm
.base_opcode
&= 0xff;
4039 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4042 i
.tm
.opcode_modifier
.vex
= VEX128
;
4044 if (i
.tm
.opcode_modifier
.vex
)
4045 for (j
= 0; j
< 3; j
++)
4047 i
.types
[j
].bitfield
.xmmword
= 1;
4048 i
.types
[j
].bitfield
.ymmword
= 0;
4053 /* This is the guts of the machine-dependent assembler. LINE points to a
4054 machine dependent instruction. This function is supposed to emit
4055 the frags/bytes it assembles to. */
4058 md_assemble (char *line
)
4061 char mnemonic
[MAX_MNEM_SIZE
], mnem_suffix
;
4062 const insn_template
*t
;
4064 /* Initialize globals. */
4065 memset (&i
, '\0', sizeof (i
));
4066 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4067 i
.reloc
[j
] = NO_RELOC
;
4068 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
4069 memset (im_expressions
, '\0', sizeof (im_expressions
));
4070 save_stack_p
= save_stack
;
4072 /* First parse an instruction mnemonic & call i386_operand for the operands.
4073 We assume that the scrubber has arranged it so that line[0] is the valid
4074 start of a (possibly prefixed) mnemonic. */
4076 line
= parse_insn (line
, mnemonic
);
4079 mnem_suffix
= i
.suffix
;
4081 line
= parse_operands (line
, mnemonic
);
4083 xfree (i
.memop1_string
);
4084 i
.memop1_string
= NULL
;
4088 /* Now we've parsed the mnemonic into a set of templates, and have the
4089 operands at hand. */
4091 /* All intel opcodes have reversed operands except for "bound" and
4092 "enter". We also don't reverse intersegment "jmp" and "call"
4093 instructions with 2 immediate operands so that the immediate segment
4094 precedes the offset, as it does when in AT&T mode. */
4097 && (strcmp (mnemonic
, "bound") != 0)
4098 && (strcmp (mnemonic
, "invlpga") != 0)
4099 && !(operand_type_check (i
.types
[0], imm
)
4100 && operand_type_check (i
.types
[1], imm
)))
4103 /* The order of the immediates should be reversed
4104 for 2 immediates extrq and insertq instructions */
4105 if (i
.imm_operands
== 2
4106 && (strcmp (mnemonic
, "extrq") == 0
4107 || strcmp (mnemonic
, "insertq") == 0))
4108 swap_2_operands (0, 1);
4113 /* Don't optimize displacement for movabs since it only takes 64bit
4116 && i
.disp_encoding
!= disp_encoding_32bit
4117 && (flag_code
!= CODE_64BIT
4118 || strcmp (mnemonic
, "movabs") != 0))
4121 /* Next, we find a template that matches the given insn,
4122 making sure the overlap of the given operands types is consistent
4123 with the template operand types. */
4125 if (!(t
= match_template (mnem_suffix
)))
4128 if (sse_check
!= check_none
4129 && !i
.tm
.opcode_modifier
.noavx
4130 && !i
.tm
.cpu_flags
.bitfield
.cpuavx
4131 && (i
.tm
.cpu_flags
.bitfield
.cpusse
4132 || i
.tm
.cpu_flags
.bitfield
.cpusse2
4133 || i
.tm
.cpu_flags
.bitfield
.cpusse3
4134 || i
.tm
.cpu_flags
.bitfield
.cpussse3
4135 || i
.tm
.cpu_flags
.bitfield
.cpusse4_1
4136 || i
.tm
.cpu_flags
.bitfield
.cpusse4_2
4137 || i
.tm
.cpu_flags
.bitfield
.cpupclmul
4138 || i
.tm
.cpu_flags
.bitfield
.cpuaes
4139 || i
.tm
.cpu_flags
.bitfield
.cpugfni
))
4141 (sse_check
== check_warning
4143 : as_bad
) (_("SSE instruction `%s' is used"), i
.tm
.name
);
4146 /* Zap movzx and movsx suffix. The suffix has been set from
4147 "word ptr" or "byte ptr" on the source operand in Intel syntax
4148 or extracted from mnemonic in AT&T syntax. But we'll use
4149 the destination register to choose the suffix for encoding. */
4150 if ((i
.tm
.base_opcode
& ~9) == 0x0fb6)
4152 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
4153 there is no suffix, the default will be byte extension. */
4154 if (i
.reg_operands
!= 2
4157 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
4162 if (i
.tm
.opcode_modifier
.fwait
)
4163 if (!add_prefix (FWAIT_OPCODE
))
4166 /* Check if REP prefix is OK. */
4167 if (i
.rep_prefix
&& !i
.tm
.opcode_modifier
.repprefixok
)
4169 as_bad (_("invalid instruction `%s' after `%s'"),
4170 i
.tm
.name
, i
.rep_prefix
);
4174 /* Check for lock without a lockable instruction. Destination operand
4175 must be memory unless it is xchg (0x86). */
4176 if (i
.prefix
[LOCK_PREFIX
]
4177 && (!i
.tm
.opcode_modifier
.islockable
4178 || i
.mem_operands
== 0
4179 || (i
.tm
.base_opcode
!= 0x86
4180 && !operand_type_check (i
.types
[i
.operands
- 1], anymem
))))
4182 as_bad (_("expecting lockable instruction after `lock'"));
4186 /* Check for data size prefix on VEX/XOP/EVEX encoded insns. */
4187 if (i
.prefix
[DATA_PREFIX
] && is_any_vex_encoding (&i
.tm
))
4189 as_bad (_("data size prefix invalid with `%s'"), i
.tm
.name
);
4193 /* Check if HLE prefix is OK. */
4194 if (i
.hle_prefix
&& !check_hle ())
4197 /* Check BND prefix. */
4198 if (i
.bnd_prefix
&& !i
.tm
.opcode_modifier
.bndprefixok
)
4199 as_bad (_("expecting valid branch instruction after `bnd'"));
4201 /* Check NOTRACK prefix. */
4202 if (i
.notrack_prefix
&& !i
.tm
.opcode_modifier
.notrackprefixok
)
4203 as_bad (_("expecting indirect branch instruction after `notrack'"));
4205 if (i
.tm
.cpu_flags
.bitfield
.cpumpx
)
4207 if (flag_code
== CODE_64BIT
&& i
.prefix
[ADDR_PREFIX
])
4208 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
4209 else if (flag_code
!= CODE_16BIT
4210 ? i
.prefix
[ADDR_PREFIX
]
4211 : i
.mem_operands
&& !i
.prefix
[ADDR_PREFIX
])
4212 as_bad (_("16-bit address isn't allowed in MPX instructions"));
4215 /* Insert BND prefix. */
4216 if (add_bnd_prefix
&& i
.tm
.opcode_modifier
.bndprefixok
)
4218 if (!i
.prefix
[BND_PREFIX
])
4219 add_prefix (BND_PREFIX_OPCODE
);
4220 else if (i
.prefix
[BND_PREFIX
] != BND_PREFIX_OPCODE
)
4222 as_warn (_("replacing `rep'/`repe' prefix by `bnd'"));
4223 i
.prefix
[BND_PREFIX
] = BND_PREFIX_OPCODE
;
4227 /* Check string instruction segment overrides. */
4228 if (i
.tm
.opcode_modifier
.isstring
&& i
.mem_operands
!= 0)
4230 if (!check_string ())
4232 i
.disp_operands
= 0;
4235 if (optimize
&& !i
.no_optimize
&& i
.tm
.opcode_modifier
.optimize
)
4236 optimize_encoding ();
4238 if (!process_suffix ())
4241 /* Update operand types. */
4242 for (j
= 0; j
< i
.operands
; j
++)
4243 i
.types
[j
] = operand_type_and (i
.types
[j
], i
.tm
.operand_types
[j
]);
4245 /* Make still unresolved immediate matches conform to size of immediate
4246 given in i.suffix. */
4247 if (!finalize_imm ())
4250 if (i
.types
[0].bitfield
.imm1
)
4251 i
.imm_operands
= 0; /* kludge for shift insns. */
4253 /* We only need to check those implicit registers for instructions
4254 with 3 operands or less. */
4255 if (i
.operands
<= 3)
4256 for (j
= 0; j
< i
.operands
; j
++)
4257 if (i
.types
[j
].bitfield
.inoutportreg
4258 || i
.types
[j
].bitfield
.shiftcount
4259 || (i
.types
[j
].bitfield
.acc
&& !i
.types
[j
].bitfield
.xmmword
))
4262 /* ImmExt should be processed after SSE2AVX. */
4263 if (!i
.tm
.opcode_modifier
.sse2avx
4264 && i
.tm
.opcode_modifier
.immext
)
4267 /* For insns with operands there are more diddles to do to the opcode. */
4270 if (!process_operands ())
4273 else if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
4275 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
4276 as_warn (_("translating to `%sp'"), i
.tm
.name
);
4279 if (is_any_vex_encoding (&i
.tm
))
4281 if (flag_code
== CODE_16BIT
)
4283 as_bad (_("instruction `%s' isn't supported in 16-bit mode."),
4288 if (i
.tm
.opcode_modifier
.vex
)
4289 build_vex_prefix (t
);
4291 build_evex_prefix ();
4294 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
4295 instructions may define INT_OPCODE as well, so avoid this corner
4296 case for those instructions that use MODRM. */
4297 if (i
.tm
.base_opcode
== INT_OPCODE
4298 && !i
.tm
.opcode_modifier
.modrm
4299 && i
.op
[0].imms
->X_add_number
== 3)
4301 i
.tm
.base_opcode
= INT3_OPCODE
;
4305 if ((i
.tm
.opcode_modifier
.jump
4306 || i
.tm
.opcode_modifier
.jumpbyte
4307 || i
.tm
.opcode_modifier
.jumpdword
)
4308 && i
.op
[0].disps
->X_op
== O_constant
)
4310 /* Convert "jmp constant" (and "call constant") to a jump (call) to
4311 the absolute address given by the constant. Since ix86 jumps and
4312 calls are pc relative, we need to generate a reloc. */
4313 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
4314 i
.op
[0].disps
->X_op
= O_symbol
;
4317 if (i
.tm
.opcode_modifier
.rex64
)
4320 /* For 8 bit registers we need an empty rex prefix. Also if the
4321 instruction already has a prefix, we need to convert old
4322 registers to new ones. */
4324 if ((i
.types
[0].bitfield
.reg
&& i
.types
[0].bitfield
.byte
4325 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
4326 || (i
.types
[1].bitfield
.reg
&& i
.types
[1].bitfield
.byte
4327 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
4328 || (((i
.types
[0].bitfield
.reg
&& i
.types
[0].bitfield
.byte
)
4329 || (i
.types
[1].bitfield
.reg
&& i
.types
[1].bitfield
.byte
))
4334 i
.rex
|= REX_OPCODE
;
4335 for (x
= 0; x
< 2; x
++)
4337 /* Look for 8 bit operand that uses old registers. */
4338 if (i
.types
[x
].bitfield
.reg
&& i
.types
[x
].bitfield
.byte
4339 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
4341 /* In case it is "hi" register, give up. */
4342 if (i
.op
[x
].regs
->reg_num
> 3)
4343 as_bad (_("can't encode register '%s%s' in an "
4344 "instruction requiring REX prefix."),
4345 register_prefix
, i
.op
[x
].regs
->reg_name
);
4347 /* Otherwise it is equivalent to the extended register.
4348 Since the encoding doesn't change this is merely
4349 cosmetic cleanup for debug output. */
4351 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
4356 if (i
.rex
== 0 && i
.rex_encoding
)
4358 /* Check if we can add a REX_OPCODE byte. Look for 8 bit operand
4359 that uses legacy register. If it is "hi" register, don't add
4360 the REX_OPCODE byte. */
4362 for (x
= 0; x
< 2; x
++)
4363 if (i
.types
[x
].bitfield
.reg
4364 && i
.types
[x
].bitfield
.byte
4365 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0
4366 && i
.op
[x
].regs
->reg_num
> 3)
4368 i
.rex_encoding
= FALSE
;
4377 add_prefix (REX_OPCODE
| i
.rex
);
4379 /* We are ready to output the insn. */
4384 parse_insn (char *line
, char *mnemonic
)
4387 char *token_start
= l
;
4390 const insn_template
*t
;
4396 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
4401 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
4403 as_bad (_("no such instruction: `%s'"), token_start
);
4408 if (!is_space_char (*l
)
4409 && *l
!= END_OF_INSN
4411 || (*l
!= PREFIX_SEPARATOR
4414 as_bad (_("invalid character %s in mnemonic"),
4415 output_invalid (*l
));
4418 if (token_start
== l
)
4420 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
4421 as_bad (_("expecting prefix; got nothing"));
4423 as_bad (_("expecting mnemonic; got nothing"));
4427 /* Look up instruction (or prefix) via hash table. */
4428 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
4430 if (*l
!= END_OF_INSN
4431 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
4432 && current_templates
4433 && current_templates
->start
->opcode_modifier
.isprefix
)
4435 if (!cpu_flags_check_cpu64 (current_templates
->start
->cpu_flags
))
4437 as_bad ((flag_code
!= CODE_64BIT
4438 ? _("`%s' is only supported in 64-bit mode")
4439 : _("`%s' is not supported in 64-bit mode")),
4440 current_templates
->start
->name
);
4443 /* If we are in 16-bit mode, do not allow addr16 or data16.
4444 Similarly, in 32-bit mode, do not allow addr32 or data32. */
4445 if ((current_templates
->start
->opcode_modifier
.size16
4446 || current_templates
->start
->opcode_modifier
.size32
)
4447 && flag_code
!= CODE_64BIT
4448 && (current_templates
->start
->opcode_modifier
.size32
4449 ^ (flag_code
== CODE_16BIT
)))
4451 as_bad (_("redundant %s prefix"),
4452 current_templates
->start
->name
);
4455 if (current_templates
->start
->opcode_length
== 0)
4457 /* Handle pseudo prefixes. */
4458 switch (current_templates
->start
->base_opcode
)
4462 i
.disp_encoding
= disp_encoding_8bit
;
4466 i
.disp_encoding
= disp_encoding_32bit
;
4470 i
.dir_encoding
= dir_encoding_load
;
4474 i
.dir_encoding
= dir_encoding_store
;
4478 i
.vec_encoding
= vex_encoding_vex2
;
4482 i
.vec_encoding
= vex_encoding_vex3
;
4486 i
.vec_encoding
= vex_encoding_evex
;
4490 i
.rex_encoding
= TRUE
;
4494 i
.no_optimize
= TRUE
;
4502 /* Add prefix, checking for repeated prefixes. */
4503 switch (add_prefix (current_templates
->start
->base_opcode
))
4508 if (current_templates
->start
->cpu_flags
.bitfield
.cpuibt
)
4509 i
.notrack_prefix
= current_templates
->start
->name
;
4512 if (current_templates
->start
->cpu_flags
.bitfield
.cpuhle
)
4513 i
.hle_prefix
= current_templates
->start
->name
;
4514 else if (current_templates
->start
->cpu_flags
.bitfield
.cpumpx
)
4515 i
.bnd_prefix
= current_templates
->start
->name
;
4517 i
.rep_prefix
= current_templates
->start
->name
;
4523 /* Skip past PREFIX_SEPARATOR and reset token_start. */
4530 if (!current_templates
)
4532 /* Deprecated functionality (new code should use pseudo-prefixes instead):
4533 Check if we should swap operand or force 32bit displacement in
4535 if (mnem_p
- 2 == dot_p
&& dot_p
[1] == 's')
4536 i
.dir_encoding
= dir_encoding_swap
;
4537 else if (mnem_p
- 3 == dot_p
4540 i
.disp_encoding
= disp_encoding_8bit
;
4541 else if (mnem_p
- 4 == dot_p
4545 i
.disp_encoding
= disp_encoding_32bit
;
4550 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
4553 if (!current_templates
)
4556 /* See if we can get a match by trimming off a suffix. */
4559 case WORD_MNEM_SUFFIX
:
4560 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
4561 i
.suffix
= SHORT_MNEM_SUFFIX
;
4564 case BYTE_MNEM_SUFFIX
:
4565 case QWORD_MNEM_SUFFIX
:
4566 i
.suffix
= mnem_p
[-1];
4568 current_templates
= (const templates
*) hash_find (op_hash
,
4571 case SHORT_MNEM_SUFFIX
:
4572 case LONG_MNEM_SUFFIX
:
4575 i
.suffix
= mnem_p
[-1];
4577 current_templates
= (const templates
*) hash_find (op_hash
,
4586 if (intel_float_operand (mnemonic
) == 1)
4587 i
.suffix
= SHORT_MNEM_SUFFIX
;
4589 i
.suffix
= LONG_MNEM_SUFFIX
;
4591 current_templates
= (const templates
*) hash_find (op_hash
,
4596 if (!current_templates
)
4598 as_bad (_("no such instruction: `%s'"), token_start
);
4603 if (current_templates
->start
->opcode_modifier
.jump
4604 || current_templates
->start
->opcode_modifier
.jumpbyte
)
4606 /* Check for a branch hint. We allow ",pt" and ",pn" for
4607 predict taken and predict not taken respectively.
4608 I'm not sure that branch hints actually do anything on loop
4609 and jcxz insns (JumpByte) for current Pentium4 chips. They
4610 may work in the future and it doesn't hurt to accept them
4612 if (l
[0] == ',' && l
[1] == 'p')
4616 if (!add_prefix (DS_PREFIX_OPCODE
))
4620 else if (l
[2] == 'n')
4622 if (!add_prefix (CS_PREFIX_OPCODE
))
4628 /* Any other comma loses. */
4631 as_bad (_("invalid character %s in mnemonic"),
4632 output_invalid (*l
));
4636 /* Check if instruction is supported on specified architecture. */
4638 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
4640 supported
|= cpu_flags_match (t
);
4641 if (supported
== CPU_FLAGS_PERFECT_MATCH
)
4643 if (!cpu_arch_flags
.bitfield
.cpui386
&& (flag_code
!= CODE_16BIT
))
4644 as_warn (_("use .code16 to ensure correct addressing mode"));
4650 if (!(supported
& CPU_FLAGS_64BIT_MATCH
))
4651 as_bad (flag_code
== CODE_64BIT
4652 ? _("`%s' is not supported in 64-bit mode")
4653 : _("`%s' is only supported in 64-bit mode"),
4654 current_templates
->start
->name
);
4656 as_bad (_("`%s' is not supported on `%s%s'"),
4657 current_templates
->start
->name
,
4658 cpu_arch_name
? cpu_arch_name
: default_arch
,
4659 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
4665 parse_operands (char *l
, const char *mnemonic
)
4669 /* 1 if operand is pending after ','. */
4670 unsigned int expecting_operand
= 0;
4672 /* Non-zero if operand parens not balanced. */
4673 unsigned int paren_not_balanced
;
4675 while (*l
!= END_OF_INSN
)
4677 /* Skip optional white space before operand. */
4678 if (is_space_char (*l
))
4680 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
&& *l
!= '"')
4682 as_bad (_("invalid character %s before operand %d"),
4683 output_invalid (*l
),
4687 token_start
= l
; /* After white space. */
4688 paren_not_balanced
= 0;
4689 while (paren_not_balanced
|| *l
!= ',')
4691 if (*l
== END_OF_INSN
)
4693 if (paren_not_balanced
)
4696 as_bad (_("unbalanced parenthesis in operand %d."),
4699 as_bad (_("unbalanced brackets in operand %d."),
4704 break; /* we are done */
4706 else if (!is_operand_char (*l
) && !is_space_char (*l
) && *l
!= '"')
4708 as_bad (_("invalid character %s in operand %d"),
4709 output_invalid (*l
),
4716 ++paren_not_balanced
;
4718 --paren_not_balanced
;
4723 ++paren_not_balanced
;
4725 --paren_not_balanced
;
4729 if (l
!= token_start
)
4730 { /* Yes, we've read in another operand. */
4731 unsigned int operand_ok
;
4732 this_operand
= i
.operands
++;
4733 if (i
.operands
> MAX_OPERANDS
)
4735 as_bad (_("spurious operands; (%d operands/instruction max)"),
4739 i
.types
[this_operand
].bitfield
.unspecified
= 1;
4740 /* Now parse operand adding info to 'i' as we go along. */
4741 END_STRING_AND_SAVE (l
);
4743 if (i
.mem_operands
> 1)
4745 as_bad (_("too many memory references for `%s'"),
4752 i386_intel_operand (token_start
,
4753 intel_float_operand (mnemonic
));
4755 operand_ok
= i386_att_operand (token_start
);
4757 RESTORE_END_STRING (l
);
4763 if (expecting_operand
)
4765 expecting_operand_after_comma
:
4766 as_bad (_("expecting operand after ','; got nothing"));
4771 as_bad (_("expecting operand before ','; got nothing"));
4776 /* Now *l must be either ',' or END_OF_INSN. */
4779 if (*++l
== END_OF_INSN
)
4781 /* Just skip it, if it's \n complain. */
4782 goto expecting_operand_after_comma
;
4784 expecting_operand
= 1;
4791 swap_2_operands (int xchg1
, int xchg2
)
4793 union i386_op temp_op
;
4794 i386_operand_type temp_type
;
4795 unsigned int temp_flags
;
4796 enum bfd_reloc_code_real temp_reloc
;
4798 temp_type
= i
.types
[xchg2
];
4799 i
.types
[xchg2
] = i
.types
[xchg1
];
4800 i
.types
[xchg1
] = temp_type
;
4802 temp_flags
= i
.flags
[xchg2
];
4803 i
.flags
[xchg2
] = i
.flags
[xchg1
];
4804 i
.flags
[xchg1
] = temp_flags
;
4806 temp_op
= i
.op
[xchg2
];
4807 i
.op
[xchg2
] = i
.op
[xchg1
];
4808 i
.op
[xchg1
] = temp_op
;
4810 temp_reloc
= i
.reloc
[xchg2
];
4811 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
4812 i
.reloc
[xchg1
] = temp_reloc
;
4816 if (i
.mask
->operand
== xchg1
)
4817 i
.mask
->operand
= xchg2
;
4818 else if (i
.mask
->operand
== xchg2
)
4819 i
.mask
->operand
= xchg1
;
4823 if (i
.broadcast
->operand
== xchg1
)
4824 i
.broadcast
->operand
= xchg2
;
4825 else if (i
.broadcast
->operand
== xchg2
)
4826 i
.broadcast
->operand
= xchg1
;
4830 if (i
.rounding
->operand
== xchg1
)
4831 i
.rounding
->operand
= xchg2
;
4832 else if (i
.rounding
->operand
== xchg2
)
4833 i
.rounding
->operand
= xchg1
;
4838 swap_operands (void)
4844 swap_2_operands (1, i
.operands
- 2);
4848 swap_2_operands (0, i
.operands
- 1);
4854 if (i
.mem_operands
== 2)
4856 const seg_entry
*temp_seg
;
4857 temp_seg
= i
.seg
[0];
4858 i
.seg
[0] = i
.seg
[1];
4859 i
.seg
[1] = temp_seg
;
4863 /* Try to ensure constant immediates are represented in the smallest
4868 char guess_suffix
= 0;
4872 guess_suffix
= i
.suffix
;
4873 else if (i
.reg_operands
)
4875 /* Figure out a suffix from the last register operand specified.
4876 We can't do this properly yet, ie. excluding InOutPortReg,
4877 but the following works for instructions with immediates.
4878 In any case, we can't set i.suffix yet. */
4879 for (op
= i
.operands
; --op
>= 0;)
4880 if (i
.types
[op
].bitfield
.reg
&& i
.types
[op
].bitfield
.byte
)
4882 guess_suffix
= BYTE_MNEM_SUFFIX
;
4885 else if (i
.types
[op
].bitfield
.reg
&& i
.types
[op
].bitfield
.word
)
4887 guess_suffix
= WORD_MNEM_SUFFIX
;
4890 else if (i
.types
[op
].bitfield
.reg
&& i
.types
[op
].bitfield
.dword
)
4892 guess_suffix
= LONG_MNEM_SUFFIX
;
4895 else if (i
.types
[op
].bitfield
.reg
&& i
.types
[op
].bitfield
.qword
)
4897 guess_suffix
= QWORD_MNEM_SUFFIX
;
4901 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
4902 guess_suffix
= WORD_MNEM_SUFFIX
;
4904 for (op
= i
.operands
; --op
>= 0;)
4905 if (operand_type_check (i
.types
[op
], imm
))
4907 switch (i
.op
[op
].imms
->X_op
)
4910 /* If a suffix is given, this operand may be shortened. */
4911 switch (guess_suffix
)
4913 case LONG_MNEM_SUFFIX
:
4914 i
.types
[op
].bitfield
.imm32
= 1;
4915 i
.types
[op
].bitfield
.imm64
= 1;
4917 case WORD_MNEM_SUFFIX
:
4918 i
.types
[op
].bitfield
.imm16
= 1;
4919 i
.types
[op
].bitfield
.imm32
= 1;
4920 i
.types
[op
].bitfield
.imm32s
= 1;
4921 i
.types
[op
].bitfield
.imm64
= 1;
4923 case BYTE_MNEM_SUFFIX
:
4924 i
.types
[op
].bitfield
.imm8
= 1;
4925 i
.types
[op
].bitfield
.imm8s
= 1;
4926 i
.types
[op
].bitfield
.imm16
= 1;
4927 i
.types
[op
].bitfield
.imm32
= 1;
4928 i
.types
[op
].bitfield
.imm32s
= 1;
4929 i
.types
[op
].bitfield
.imm64
= 1;
4933 /* If this operand is at most 16 bits, convert it
4934 to a signed 16 bit number before trying to see
4935 whether it will fit in an even smaller size.
4936 This allows a 16-bit operand such as $0xffe0 to
4937 be recognised as within Imm8S range. */
4938 if ((i
.types
[op
].bitfield
.imm16
)
4939 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
4941 i
.op
[op
].imms
->X_add_number
=
4942 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
4945 /* Store 32-bit immediate in 64-bit for 64-bit BFD. */
4946 if ((i
.types
[op
].bitfield
.imm32
)
4947 && ((i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1))
4950 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
4951 ^ ((offsetT
) 1 << 31))
4952 - ((offsetT
) 1 << 31));
4956 = operand_type_or (i
.types
[op
],
4957 smallest_imm_type (i
.op
[op
].imms
->X_add_number
));
4959 /* We must avoid matching of Imm32 templates when 64bit
4960 only immediate is available. */
4961 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
4962 i
.types
[op
].bitfield
.imm32
= 0;
4969 /* Symbols and expressions. */
4971 /* Convert symbolic operand to proper sizes for matching, but don't
4972 prevent matching a set of insns that only supports sizes other
4973 than those matching the insn suffix. */
4975 i386_operand_type mask
, allowed
;
4976 const insn_template
*t
;
4978 operand_type_set (&mask
, 0);
4979 operand_type_set (&allowed
, 0);
4981 for (t
= current_templates
->start
;
4982 t
< current_templates
->end
;
4984 allowed
= operand_type_or (allowed
,
4985 t
->operand_types
[op
]);
4986 switch (guess_suffix
)
4988 case QWORD_MNEM_SUFFIX
:
4989 mask
.bitfield
.imm64
= 1;
4990 mask
.bitfield
.imm32s
= 1;
4992 case LONG_MNEM_SUFFIX
:
4993 mask
.bitfield
.imm32
= 1;
4995 case WORD_MNEM_SUFFIX
:
4996 mask
.bitfield
.imm16
= 1;
4998 case BYTE_MNEM_SUFFIX
:
4999 mask
.bitfield
.imm8
= 1;
5004 allowed
= operand_type_and (mask
, allowed
);
5005 if (!operand_type_all_zero (&allowed
))
5006 i
.types
[op
] = operand_type_and (i
.types
[op
], mask
);
5013 /* Try to use the smallest displacement type too. */
5015 optimize_disp (void)
5019 for (op
= i
.operands
; --op
>= 0;)
5020 if (operand_type_check (i
.types
[op
], disp
))
5022 if (i
.op
[op
].disps
->X_op
== O_constant
)
5024 offsetT op_disp
= i
.op
[op
].disps
->X_add_number
;
5026 if (i
.types
[op
].bitfield
.disp16
5027 && (op_disp
& ~(offsetT
) 0xffff) == 0)
5029 /* If this operand is at most 16 bits, convert
5030 to a signed 16 bit number and don't use 64bit
5032 op_disp
= (((op_disp
& 0xffff) ^ 0x8000) - 0x8000);
5033 i
.types
[op
].bitfield
.disp64
= 0;
5036 /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */
5037 if (i
.types
[op
].bitfield
.disp32
5038 && (op_disp
& ~(((offsetT
) 2 << 31) - 1)) == 0)
5040 /* If this operand is at most 32 bits, convert
5041 to a signed 32 bit number and don't use 64bit
5043 op_disp
&= (((offsetT
) 2 << 31) - 1);
5044 op_disp
= (op_disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
5045 i
.types
[op
].bitfield
.disp64
= 0;
5048 if (!op_disp
&& i
.types
[op
].bitfield
.baseindex
)
5050 i
.types
[op
].bitfield
.disp8
= 0;
5051 i
.types
[op
].bitfield
.disp16
= 0;
5052 i
.types
[op
].bitfield
.disp32
= 0;
5053 i
.types
[op
].bitfield
.disp32s
= 0;
5054 i
.types
[op
].bitfield
.disp64
= 0;
5058 else if (flag_code
== CODE_64BIT
)
5060 if (fits_in_signed_long (op_disp
))
5062 i
.types
[op
].bitfield
.disp64
= 0;
5063 i
.types
[op
].bitfield
.disp32s
= 1;
5065 if (i
.prefix
[ADDR_PREFIX
]
5066 && fits_in_unsigned_long (op_disp
))
5067 i
.types
[op
].bitfield
.disp32
= 1;
5069 if ((i
.types
[op
].bitfield
.disp32
5070 || i
.types
[op
].bitfield
.disp32s
5071 || i
.types
[op
].bitfield
.disp16
)
5072 && fits_in_disp8 (op_disp
))
5073 i
.types
[op
].bitfield
.disp8
= 1;
5075 else if (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
5076 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
)
5078 fix_new_exp (frag_now
, frag_more (0) - frag_now
->fr_literal
, 0,
5079 i
.op
[op
].disps
, 0, i
.reloc
[op
]);
5080 i
.types
[op
].bitfield
.disp8
= 0;
5081 i
.types
[op
].bitfield
.disp16
= 0;
5082 i
.types
[op
].bitfield
.disp32
= 0;
5083 i
.types
[op
].bitfield
.disp32s
= 0;
5084 i
.types
[op
].bitfield
.disp64
= 0;
5087 /* We only support 64bit displacement on constants. */
5088 i
.types
[op
].bitfield
.disp64
= 0;
5092 /* Return 1 if there is a match in broadcast bytes between operand
5093 GIVEN and instruction template T. */
5096 match_broadcast_size (const insn_template
*t
, unsigned int given
)
5098 return ((t
->opcode_modifier
.broadcast
== BYTE_BROADCAST
5099 && i
.types
[given
].bitfield
.byte
)
5100 || (t
->opcode_modifier
.broadcast
== WORD_BROADCAST
5101 && i
.types
[given
].bitfield
.word
)
5102 || (t
->opcode_modifier
.broadcast
== DWORD_BROADCAST
5103 && i
.types
[given
].bitfield
.dword
)
5104 || (t
->opcode_modifier
.broadcast
== QWORD_BROADCAST
5105 && i
.types
[given
].bitfield
.qword
));
5108 /* Check if operands are valid for the instruction. */
5111 check_VecOperands (const insn_template
*t
)
5115 static const i386_cpu_flags avx512
= CPU_ANY_AVX512F_FLAGS
;
5117 /* Templates allowing for ZMMword as well as YMMword and/or XMMword for
5118 any one operand are implicity requiring AVX512VL support if the actual
5119 operand size is YMMword or XMMword. Since this function runs after
5120 template matching, there's no need to check for YMMword/XMMword in
5122 cpu
= cpu_flags_and (t
->cpu_flags
, avx512
);
5123 if (!cpu_flags_all_zero (&cpu
)
5124 && !t
->cpu_flags
.bitfield
.cpuavx512vl
5125 && !cpu_arch_flags
.bitfield
.cpuavx512vl
)
5127 for (op
= 0; op
< t
->operands
; ++op
)
5129 if (t
->operand_types
[op
].bitfield
.zmmword
5130 && (i
.types
[op
].bitfield
.ymmword
5131 || i
.types
[op
].bitfield
.xmmword
))
5133 i
.error
= unsupported
;
5139 /* Without VSIB byte, we can't have a vector register for index. */
5140 if (!t
->opcode_modifier
.vecsib
5142 && (i
.index_reg
->reg_type
.bitfield
.xmmword
5143 || i
.index_reg
->reg_type
.bitfield
.ymmword
5144 || i
.index_reg
->reg_type
.bitfield
.zmmword
))
5146 i
.error
= unsupported_vector_index_register
;
5150 /* Check if default mask is allowed. */
5151 if (t
->opcode_modifier
.nodefmask
5152 && (!i
.mask
|| i
.mask
->mask
->reg_num
== 0))
5154 i
.error
= no_default_mask
;
5158 /* For VSIB byte, we need a vector register for index, and all vector
5159 registers must be distinct. */
5160 if (t
->opcode_modifier
.vecsib
)
5163 || !((t
->opcode_modifier
.vecsib
== VecSIB128
5164 && i
.index_reg
->reg_type
.bitfield
.xmmword
)
5165 || (t
->opcode_modifier
.vecsib
== VecSIB256
5166 && i
.index_reg
->reg_type
.bitfield
.ymmword
)
5167 || (t
->opcode_modifier
.vecsib
== VecSIB512
5168 && i
.index_reg
->reg_type
.bitfield
.zmmword
)))
5170 i
.error
= invalid_vsib_address
;
5174 gas_assert (i
.reg_operands
== 2 || i
.mask
);
5175 if (i
.reg_operands
== 2 && !i
.mask
)
5177 gas_assert (i
.types
[0].bitfield
.regsimd
);
5178 gas_assert (i
.types
[0].bitfield
.xmmword
5179 || i
.types
[0].bitfield
.ymmword
);
5180 gas_assert (i
.types
[2].bitfield
.regsimd
);
5181 gas_assert (i
.types
[2].bitfield
.xmmword
5182 || i
.types
[2].bitfield
.ymmword
);
5183 if (operand_check
== check_none
)
5185 if (register_number (i
.op
[0].regs
)
5186 != register_number (i
.index_reg
)
5187 && register_number (i
.op
[2].regs
)
5188 != register_number (i
.index_reg
)
5189 && register_number (i
.op
[0].regs
)
5190 != register_number (i
.op
[2].regs
))
5192 if (operand_check
== check_error
)
5194 i
.error
= invalid_vector_register_set
;
5197 as_warn (_("mask, index, and destination registers should be distinct"));
5199 else if (i
.reg_operands
== 1 && i
.mask
)
5201 if (i
.types
[1].bitfield
.regsimd
5202 && (i
.types
[1].bitfield
.xmmword
5203 || i
.types
[1].bitfield
.ymmword
5204 || i
.types
[1].bitfield
.zmmword
)
5205 && (register_number (i
.op
[1].regs
)
5206 == register_number (i
.index_reg
)))
5208 if (operand_check
== check_error
)
5210 i
.error
= invalid_vector_register_set
;
5213 if (operand_check
!= check_none
)
5214 as_warn (_("index and destination registers should be distinct"));
5219 /* Check if broadcast is supported by the instruction and is applied
5220 to the memory operand. */
5223 i386_operand_type type
, overlap
;
5225 /* Check if specified broadcast is supported in this instruction,
5226 and its broadcast bytes match the memory operand. */
5227 op
= i
.broadcast
->operand
;
5228 if (!t
->opcode_modifier
.broadcast
5229 || !(i
.flags
[op
] & Operand_Mem
)
5230 || (!i
.types
[op
].bitfield
.unspecified
5231 && !match_broadcast_size (t
, op
)))
5234 i
.error
= unsupported_broadcast
;
5238 i
.broadcast
->bytes
= ((1 << (t
->opcode_modifier
.broadcast
- 1))
5239 * i
.broadcast
->type
);
5240 operand_type_set (&type
, 0);
5241 switch (i
.broadcast
->bytes
)
5244 type
.bitfield
.word
= 1;
5247 type
.bitfield
.dword
= 1;
5250 type
.bitfield
.qword
= 1;
5253 type
.bitfield
.xmmword
= 1;
5256 type
.bitfield
.ymmword
= 1;
5259 type
.bitfield
.zmmword
= 1;
5265 overlap
= operand_type_and (type
, t
->operand_types
[op
]);
5266 if (operand_type_all_zero (&overlap
))
5269 if (t
->opcode_modifier
.checkregsize
)
5273 type
.bitfield
.baseindex
= 1;
5274 for (j
= 0; j
< i
.operands
; ++j
)
5277 && !operand_type_register_match(i
.types
[j
],
5278 t
->operand_types
[j
],
5280 t
->operand_types
[op
]))
5285 /* If broadcast is supported in this instruction, we need to check if
5286 operand of one-element size isn't specified without broadcast. */
5287 else if (t
->opcode_modifier
.broadcast
&& i
.mem_operands
)
5289 /* Find memory operand. */
5290 for (op
= 0; op
< i
.operands
; op
++)
5291 if (operand_type_check (i
.types
[op
], anymem
))
5293 gas_assert (op
< i
.operands
);
5294 /* Check size of the memory operand. */
5295 if (match_broadcast_size (t
, op
))
5297 i
.error
= broadcast_needed
;
5302 op
= MAX_OPERANDS
- 1; /* Avoid uninitialized variable warning. */
5304 /* Check if requested masking is supported. */
5307 switch (t
->opcode_modifier
.masking
)
5311 case MERGING_MASKING
:
5312 if (i
.mask
->zeroing
)
5315 i
.error
= unsupported_masking
;
5319 case DYNAMIC_MASKING
:
5320 /* Memory destinations allow only merging masking. */
5321 if (i
.mask
->zeroing
&& i
.mem_operands
)
5323 /* Find memory operand. */
5324 for (op
= 0; op
< i
.operands
; op
++)
5325 if (i
.flags
[op
] & Operand_Mem
)
5327 gas_assert (op
< i
.operands
);
5328 if (op
== i
.operands
- 1)
5330 i
.error
= unsupported_masking
;
5340 /* Check if masking is applied to dest operand. */
5341 if (i
.mask
&& (i
.mask
->operand
!= (int) (i
.operands
- 1)))
5343 i
.error
= mask_not_on_destination
;
5350 if ((i
.rounding
->type
!= saeonly
5351 && !t
->opcode_modifier
.staticrounding
)
5352 || (i
.rounding
->type
== saeonly
5353 && (t
->opcode_modifier
.staticrounding
5354 || !t
->opcode_modifier
.sae
)))
5356 i
.error
= unsupported_rc_sae
;
5359 /* If the instruction has several immediate operands and one of
5360 them is rounding, the rounding operand should be the last
5361 immediate operand. */
5362 if (i
.imm_operands
> 1
5363 && i
.rounding
->operand
!= (int) (i
.imm_operands
- 1))
5365 i
.error
= rc_sae_operand_not_last_imm
;
5370 /* Check vector Disp8 operand. */
5371 if (t
->opcode_modifier
.disp8memshift
5372 && i
.disp_encoding
!= disp_encoding_32bit
)
5375 i
.memshift
= t
->opcode_modifier
.broadcast
- 1;
5376 else if (t
->opcode_modifier
.disp8memshift
!= DISP8_SHIFT_VL
)
5377 i
.memshift
= t
->opcode_modifier
.disp8memshift
;
5380 const i386_operand_type
*type
= NULL
;
5383 for (op
= 0; op
< i
.operands
; op
++)
5384 if (operand_type_check (i
.types
[op
], anymem
))
5386 if (t
->opcode_modifier
.evex
== EVEXLIG
)
5387 i
.memshift
= 2 + (i
.suffix
== QWORD_MNEM_SUFFIX
);
5388 else if (t
->operand_types
[op
].bitfield
.xmmword
5389 + t
->operand_types
[op
].bitfield
.ymmword
5390 + t
->operand_types
[op
].bitfield
.zmmword
<= 1)
5391 type
= &t
->operand_types
[op
];
5392 else if (!i
.types
[op
].bitfield
.unspecified
)
5393 type
= &i
.types
[op
];
5395 else if (i
.types
[op
].bitfield
.regsimd
5396 && t
->opcode_modifier
.evex
!= EVEXLIG
)
5398 if (i
.types
[op
].bitfield
.zmmword
)
5400 else if (i
.types
[op
].bitfield
.ymmword
&& i
.memshift
< 5)
5402 else if (i
.types
[op
].bitfield
.xmmword
&& i
.memshift
< 4)
5408 if (type
->bitfield
.zmmword
)
5410 else if (type
->bitfield
.ymmword
)
5412 else if (type
->bitfield
.xmmword
)
5416 /* For the check in fits_in_disp8(). */
5417 if (i
.memshift
== 0)
5421 for (op
= 0; op
< i
.operands
; op
++)
5422 if (operand_type_check (i
.types
[op
], disp
)
5423 && i
.op
[op
].disps
->X_op
== O_constant
)
5425 if (fits_in_disp8 (i
.op
[op
].disps
->X_add_number
))
5427 i
.types
[op
].bitfield
.disp8
= 1;
5430 i
.types
[op
].bitfield
.disp8
= 0;
5439 /* Check if operands are valid for the instruction. Update VEX
5443 VEX_check_operands (const insn_template
*t
)
5445 if (i
.vec_encoding
== vex_encoding_evex
)
5447 /* This instruction must be encoded with EVEX prefix. */
5448 if (!is_evex_encoding (t
))
5450 i
.error
= unsupported
;
5456 if (!t
->opcode_modifier
.vex
)
5458 /* This instruction template doesn't have VEX prefix. */
5459 if (i
.vec_encoding
!= vex_encoding_default
)
5461 i
.error
= unsupported
;
5467 /* Only check VEX_Imm4, which must be the first operand. */
5468 if (t
->operand_types
[0].bitfield
.vec_imm4
)
5470 if (i
.op
[0].imms
->X_op
!= O_constant
5471 || !fits_in_imm4 (i
.op
[0].imms
->X_add_number
))
5477 /* Turn off Imm8 so that update_imm won't complain. */
5478 i
.types
[0] = vec_imm4
;
5484 static const insn_template
*
5485 match_template (char mnem_suffix
)
5487 /* Points to template once we've found it. */
5488 const insn_template
*t
;
5489 i386_operand_type overlap0
, overlap1
, overlap2
, overlap3
;
5490 i386_operand_type overlap4
;
5491 unsigned int found_reverse_match
;
5492 i386_opcode_modifier suffix_check
, mnemsuf_check
;
5493 i386_operand_type operand_types
[MAX_OPERANDS
];
5494 int addr_prefix_disp
;
5496 unsigned int found_cpu_match
, size_match
;
5497 unsigned int check_register
;
5498 enum i386_error specific_error
= 0;
5500 #if MAX_OPERANDS != 5
5501 # error "MAX_OPERANDS must be 5."
5504 found_reverse_match
= 0;
5505 addr_prefix_disp
= -1;
5507 memset (&suffix_check
, 0, sizeof (suffix_check
));
5508 if (intel_syntax
&& i
.broadcast
)
5510 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
5511 suffix_check
.no_bsuf
= 1;
5512 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
5513 suffix_check
.no_wsuf
= 1;
5514 else if (i
.suffix
== SHORT_MNEM_SUFFIX
)
5515 suffix_check
.no_ssuf
= 1;
5516 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
5517 suffix_check
.no_lsuf
= 1;
5518 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
5519 suffix_check
.no_qsuf
= 1;
5520 else if (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
)
5521 suffix_check
.no_ldsuf
= 1;
5523 memset (&mnemsuf_check
, 0, sizeof (mnemsuf_check
));
5526 switch (mnem_suffix
)
5528 case BYTE_MNEM_SUFFIX
: mnemsuf_check
.no_bsuf
= 1; break;
5529 case WORD_MNEM_SUFFIX
: mnemsuf_check
.no_wsuf
= 1; break;
5530 case SHORT_MNEM_SUFFIX
: mnemsuf_check
.no_ssuf
= 1; break;
5531 case LONG_MNEM_SUFFIX
: mnemsuf_check
.no_lsuf
= 1; break;
5532 case QWORD_MNEM_SUFFIX
: mnemsuf_check
.no_qsuf
= 1; break;
5536 /* Must have right number of operands. */
5537 i
.error
= number_of_operands_mismatch
;
5539 for (t
= current_templates
->start
; t
< current_templates
->end
; t
++)
5541 addr_prefix_disp
= -1;
5542 found_reverse_match
= 0;
5544 if (i
.operands
!= t
->operands
)
5547 /* Check processor support. */
5548 i
.error
= unsupported
;
5549 found_cpu_match
= (cpu_flags_match (t
)
5550 == CPU_FLAGS_PERFECT_MATCH
);
5551 if (!found_cpu_match
)
5554 /* Check AT&T mnemonic. */
5555 i
.error
= unsupported_with_intel_mnemonic
;
5556 if (intel_mnemonic
&& t
->opcode_modifier
.attmnemonic
)
5559 /* Check AT&T/Intel syntax and Intel64/AMD64 ISA. */
5560 i
.error
= unsupported_syntax
;
5561 if ((intel_syntax
&& t
->opcode_modifier
.attsyntax
)
5562 || (!intel_syntax
&& t
->opcode_modifier
.intelsyntax
)
5563 || (intel64
&& t
->opcode_modifier
.amd64
)
5564 || (!intel64
&& t
->opcode_modifier
.intel64
))
5567 /* Check the suffix, except for some instructions in intel mode. */
5568 i
.error
= invalid_instruction_suffix
;
5569 if ((!intel_syntax
|| !t
->opcode_modifier
.ignoresize
)
5570 && ((t
->opcode_modifier
.no_bsuf
&& suffix_check
.no_bsuf
)
5571 || (t
->opcode_modifier
.no_wsuf
&& suffix_check
.no_wsuf
)
5572 || (t
->opcode_modifier
.no_lsuf
&& suffix_check
.no_lsuf
)
5573 || (t
->opcode_modifier
.no_ssuf
&& suffix_check
.no_ssuf
)
5574 || (t
->opcode_modifier
.no_qsuf
&& suffix_check
.no_qsuf
)
5575 || (t
->opcode_modifier
.no_ldsuf
&& suffix_check
.no_ldsuf
)))
5577 /* In Intel mode all mnemonic suffixes must be explicitly allowed. */
5578 if ((t
->opcode_modifier
.no_bsuf
&& mnemsuf_check
.no_bsuf
)
5579 || (t
->opcode_modifier
.no_wsuf
&& mnemsuf_check
.no_wsuf
)
5580 || (t
->opcode_modifier
.no_lsuf
&& mnemsuf_check
.no_lsuf
)
5581 || (t
->opcode_modifier
.no_ssuf
&& mnemsuf_check
.no_ssuf
)
5582 || (t
->opcode_modifier
.no_qsuf
&& mnemsuf_check
.no_qsuf
)
5583 || (t
->opcode_modifier
.no_ldsuf
&& mnemsuf_check
.no_ldsuf
))
5586 size_match
= operand_size_match (t
);
5590 for (j
= 0; j
< MAX_OPERANDS
; j
++)
5591 operand_types
[j
] = t
->operand_types
[j
];
5593 /* In general, don't allow 64-bit operands in 32-bit mode. */
5594 if (i
.suffix
== QWORD_MNEM_SUFFIX
5595 && flag_code
!= CODE_64BIT
5597 ? (!t
->opcode_modifier
.ignoresize
5598 && !t
->opcode_modifier
.broadcast
5599 && !intel_float_operand (t
->name
))
5600 : intel_float_operand (t
->name
) != 2)
5601 && ((!operand_types
[0].bitfield
.regmmx
5602 && !operand_types
[0].bitfield
.regsimd
)
5603 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
5604 && !operand_types
[t
->operands
> 1].bitfield
.regsimd
))
5605 && (t
->base_opcode
!= 0x0fc7
5606 || t
->extension_opcode
!= 1 /* cmpxchg8b */))
5609 /* In general, don't allow 32-bit operands on pre-386. */
5610 else if (i
.suffix
== LONG_MNEM_SUFFIX
5611 && !cpu_arch_flags
.bitfield
.cpui386
5613 ? (!t
->opcode_modifier
.ignoresize
5614 && !intel_float_operand (t
->name
))
5615 : intel_float_operand (t
->name
) != 2)
5616 && ((!operand_types
[0].bitfield
.regmmx
5617 && !operand_types
[0].bitfield
.regsimd
)
5618 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
5619 && !operand_types
[t
->operands
> 1].bitfield
.regsimd
)))
5622 /* Do not verify operands when there are none. */
5626 /* We've found a match; break out of loop. */
5630 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
5631 into Disp32/Disp16/Disp32 operand. */
5632 if (i
.prefix
[ADDR_PREFIX
] != 0)
5634 /* There should be only one Disp operand. */
5638 for (j
= 0; j
< MAX_OPERANDS
; j
++)
5640 if (operand_types
[j
].bitfield
.disp16
)
5642 addr_prefix_disp
= j
;
5643 operand_types
[j
].bitfield
.disp32
= 1;
5644 operand_types
[j
].bitfield
.disp16
= 0;
5650 for (j
= 0; j
< MAX_OPERANDS
; j
++)
5652 if (operand_types
[j
].bitfield
.disp32
)
5654 addr_prefix_disp
= j
;
5655 operand_types
[j
].bitfield
.disp32
= 0;
5656 operand_types
[j
].bitfield
.disp16
= 1;
5662 for (j
= 0; j
< MAX_OPERANDS
; j
++)
5664 if (operand_types
[j
].bitfield
.disp64
)
5666 addr_prefix_disp
= j
;
5667 operand_types
[j
].bitfield
.disp64
= 0;
5668 operand_types
[j
].bitfield
.disp32
= 1;
5676 /* Force 0x8b encoding for "mov foo@GOT, %eax". */
5677 if (i
.reloc
[0] == BFD_RELOC_386_GOT32
&& t
->base_opcode
== 0xa0)
5680 /* We check register size if needed. */
5681 if (t
->opcode_modifier
.checkregsize
)
5683 check_register
= (1 << t
->operands
) - 1;
5685 check_register
&= ~(1 << i
.broadcast
->operand
);
5690 overlap0
= operand_type_and (i
.types
[0], operand_types
[0]);
5691 switch (t
->operands
)
5694 if (!operand_type_match (overlap0
, i
.types
[0]))
5698 /* xchg %eax, %eax is a special case. It is an alias for nop
5699 only in 32bit mode and we can use opcode 0x90. In 64bit
5700 mode, we can't use 0x90 for xchg %eax, %eax since it should
5701 zero-extend %eax to %rax. */
5702 if (flag_code
== CODE_64BIT
5703 && t
->base_opcode
== 0x90
5704 && operand_type_equal (&i
.types
[0], &acc32
)
5705 && operand_type_equal (&i
.types
[1], &acc32
))
5707 /* xrelease mov %eax, <disp> is another special case. It must not
5708 match the accumulator-only encoding of mov. */
5709 if (flag_code
!= CODE_64BIT
5711 && t
->base_opcode
== 0xa0
5712 && i
.types
[0].bitfield
.acc
5713 && operand_type_check (i
.types
[1], anymem
))
5718 if (!(size_match
& MATCH_STRAIGHT
))
5720 /* Reverse direction of operands if swapping is possible in the first
5721 place (operands need to be symmetric) and
5722 - the load form is requested, and the template is a store form,
5723 - the store form is requested, and the template is a load form,
5724 - the non-default (swapped) form is requested. */
5725 overlap1
= operand_type_and (operand_types
[0], operand_types
[1]);
5726 if (t
->opcode_modifier
.d
&& i
.reg_operands
== i
.operands
5727 && !operand_type_all_zero (&overlap1
))
5728 switch (i
.dir_encoding
)
5730 case dir_encoding_load
:
5731 if (operand_type_check (operand_types
[i
.operands
- 1], anymem
)
5732 || operand_types
[i
.operands
- 1].bitfield
.regmem
)
5736 case dir_encoding_store
:
5737 if (!operand_type_check (operand_types
[i
.operands
- 1], anymem
)
5738 && !operand_types
[i
.operands
- 1].bitfield
.regmem
)
5742 case dir_encoding_swap
:
5745 case dir_encoding_default
:
5748 /* If we want store form, we skip the current load. */
5749 if ((i
.dir_encoding
== dir_encoding_store
5750 || i
.dir_encoding
== dir_encoding_swap
)
5751 && i
.mem_operands
== 0
5752 && t
->opcode_modifier
.load
)
5757 overlap1
= operand_type_and (i
.types
[1], operand_types
[1]);
5758 if (!operand_type_match (overlap0
, i
.types
[0])
5759 || !operand_type_match (overlap1
, i
.types
[1])
5760 || ((check_register
& 3) == 3
5761 && !operand_type_register_match (i
.types
[0],
5766 /* Check if other direction is valid ... */
5767 if (!t
->opcode_modifier
.d
)
5771 if (!(size_match
& MATCH_REVERSE
))
5773 /* Try reversing direction of operands. */
5774 overlap0
= operand_type_and (i
.types
[0], operand_types
[i
.operands
- 1]);
5775 overlap1
= operand_type_and (i
.types
[i
.operands
- 1], operand_types
[0]);
5776 if (!operand_type_match (overlap0
, i
.types
[0])
5777 || !operand_type_match (overlap1
, i
.types
[i
.operands
- 1])
5779 && !operand_type_register_match (i
.types
[0],
5780 operand_types
[i
.operands
- 1],
5781 i
.types
[i
.operands
- 1],
5784 /* Does not match either direction. */
5787 /* found_reverse_match holds which of D or FloatR
5789 if (!t
->opcode_modifier
.d
)
5790 found_reverse_match
= 0;
5791 else if (operand_types
[0].bitfield
.tbyte
)
5792 found_reverse_match
= Opcode_FloatD
;
5793 else if (operand_types
[0].bitfield
.xmmword
5794 || operand_types
[i
.operands
- 1].bitfield
.xmmword
5795 || operand_types
[0].bitfield
.regmmx
5796 || operand_types
[i
.operands
- 1].bitfield
.regmmx
5797 || is_any_vex_encoding(t
))
5798 found_reverse_match
= (t
->base_opcode
& 0xee) != 0x6e
5799 ? Opcode_SIMD_FloatD
: Opcode_SIMD_IntD
;
5801 found_reverse_match
= Opcode_D
;
5802 if (t
->opcode_modifier
.floatr
)
5803 found_reverse_match
|= Opcode_FloatR
;
5807 /* Found a forward 2 operand match here. */
5808 switch (t
->operands
)
5811 overlap4
= operand_type_and (i
.types
[4],
5815 overlap3
= operand_type_and (i
.types
[3],
5819 overlap2
= operand_type_and (i
.types
[2],
5824 switch (t
->operands
)
5827 if (!operand_type_match (overlap4
, i
.types
[4])
5828 || !operand_type_register_match (i
.types
[3],
5835 if (!operand_type_match (overlap3
, i
.types
[3])
5836 || ((check_register
& 0xa) == 0xa
5837 && !operand_type_register_match (i
.types
[1],
5841 || ((check_register
& 0xc) == 0xc
5842 && !operand_type_register_match (i
.types
[2],
5849 /* Here we make use of the fact that there are no
5850 reverse match 3 operand instructions. */
5851 if (!operand_type_match (overlap2
, i
.types
[2])
5852 || ((check_register
& 5) == 5
5853 && !operand_type_register_match (i
.types
[0],
5857 || ((check_register
& 6) == 6
5858 && !operand_type_register_match (i
.types
[1],
5866 /* Found either forward/reverse 2, 3 or 4 operand match here:
5867 slip through to break. */
5869 if (!found_cpu_match
)
5872 /* Check if vector and VEX operands are valid. */
5873 if (check_VecOperands (t
) || VEX_check_operands (t
))
5875 specific_error
= i
.error
;
5879 /* We've found a match; break out of loop. */
5883 if (t
== current_templates
->end
)
5885 /* We found no match. */
5886 const char *err_msg
;
5887 switch (specific_error
? specific_error
: i
.error
)
5891 case operand_size_mismatch
:
5892 err_msg
= _("operand size mismatch");
5894 case operand_type_mismatch
:
5895 err_msg
= _("operand type mismatch");
5897 case register_type_mismatch
:
5898 err_msg
= _("register type mismatch");
5900 case number_of_operands_mismatch
:
5901 err_msg
= _("number of operands mismatch");
5903 case invalid_instruction_suffix
:
5904 err_msg
= _("invalid instruction suffix");
5907 err_msg
= _("constant doesn't fit in 4 bits");
5909 case unsupported_with_intel_mnemonic
:
5910 err_msg
= _("unsupported with Intel mnemonic");
5912 case unsupported_syntax
:
5913 err_msg
= _("unsupported syntax");
5916 as_bad (_("unsupported instruction `%s'"),
5917 current_templates
->start
->name
);
5919 case invalid_vsib_address
:
5920 err_msg
= _("invalid VSIB address");
5922 case invalid_vector_register_set
:
5923 err_msg
= _("mask, index, and destination registers must be distinct");
5925 case unsupported_vector_index_register
:
5926 err_msg
= _("unsupported vector index register");
5928 case unsupported_broadcast
:
5929 err_msg
= _("unsupported broadcast");
5931 case broadcast_needed
:
5932 err_msg
= _("broadcast is needed for operand of such type");
5934 case unsupported_masking
:
5935 err_msg
= _("unsupported masking");
5937 case mask_not_on_destination
:
5938 err_msg
= _("mask not on destination operand");
5940 case no_default_mask
:
5941 err_msg
= _("default mask isn't allowed");
5943 case unsupported_rc_sae
:
5944 err_msg
= _("unsupported static rounding/sae");
5946 case rc_sae_operand_not_last_imm
:
5948 err_msg
= _("RC/SAE operand must precede immediate operands");
5950 err_msg
= _("RC/SAE operand must follow immediate operands");
5952 case invalid_register_operand
:
5953 err_msg
= _("invalid register operand");
5956 as_bad (_("%s for `%s'"), err_msg
,
5957 current_templates
->start
->name
);
5961 if (!quiet_warnings
)
5964 && (i
.types
[0].bitfield
.jumpabsolute
5965 != operand_types
[0].bitfield
.jumpabsolute
))
5967 as_warn (_("indirect %s without `*'"), t
->name
);
5970 if (t
->opcode_modifier
.isprefix
5971 && t
->opcode_modifier
.ignoresize
)
5973 /* Warn them that a data or address size prefix doesn't
5974 affect assembly of the next line of code. */
5975 as_warn (_("stand-alone `%s' prefix"), t
->name
);
5979 /* Copy the template we found. */
5982 if (addr_prefix_disp
!= -1)
5983 i
.tm
.operand_types
[addr_prefix_disp
]
5984 = operand_types
[addr_prefix_disp
];
5986 if (found_reverse_match
)
5988 /* If we found a reverse match we must alter the opcode
5989 direction bit. found_reverse_match holds bits to change
5990 (different for int & float insns). */
5992 i
.tm
.base_opcode
^= found_reverse_match
;
5994 i
.tm
.operand_types
[0] = operand_types
[i
.operands
- 1];
5995 i
.tm
.operand_types
[i
.operands
- 1] = operand_types
[0];
6004 int mem_op
= operand_type_check (i
.types
[0], anymem
) ? 0 : 1;
6005 if (i
.tm
.operand_types
[mem_op
].bitfield
.esseg
)
6007 if (i
.seg
[0] != NULL
&& i
.seg
[0] != &es
)
6009 as_bad (_("`%s' operand %d must use `%ses' segment"),
6015 /* There's only ever one segment override allowed per instruction.
6016 This instruction possibly has a legal segment override on the
6017 second operand, so copy the segment to where non-string
6018 instructions store it, allowing common code. */
6019 i
.seg
[0] = i
.seg
[1];
6021 else if (i
.tm
.operand_types
[mem_op
+ 1].bitfield
.esseg
)
6023 if (i
.seg
[1] != NULL
&& i
.seg
[1] != &es
)
6025 as_bad (_("`%s' operand %d must use `%ses' segment"),
6036 process_suffix (void)
6038 /* If matched instruction specifies an explicit instruction mnemonic
6040 if (i
.tm
.opcode_modifier
.size16
)
6041 i
.suffix
= WORD_MNEM_SUFFIX
;
6042 else if (i
.tm
.opcode_modifier
.size32
)
6043 i
.suffix
= LONG_MNEM_SUFFIX
;
6044 else if (i
.tm
.opcode_modifier
.size64
)
6045 i
.suffix
= QWORD_MNEM_SUFFIX
;
6046 else if (i
.reg_operands
)
6048 /* If there's no instruction mnemonic suffix we try to invent one
6049 based on register operands. */
6052 /* We take i.suffix from the last register operand specified,
6053 Destination register type is more significant than source
6054 register type. crc32 in SSE4.2 prefers source register
6056 if (i
.tm
.base_opcode
== 0xf20f38f0 && i
.types
[0].bitfield
.reg
)
6058 if (i
.types
[0].bitfield
.byte
)
6059 i
.suffix
= BYTE_MNEM_SUFFIX
;
6060 else if (i
.types
[0].bitfield
.word
)
6061 i
.suffix
= WORD_MNEM_SUFFIX
;
6062 else if (i
.types
[0].bitfield
.dword
)
6063 i
.suffix
= LONG_MNEM_SUFFIX
;
6064 else if (i
.types
[0].bitfield
.qword
)
6065 i
.suffix
= QWORD_MNEM_SUFFIX
;
6072 if (i
.tm
.base_opcode
== 0xf20f38f0)
6074 /* We have to know the operand size for crc32. */
6075 as_bad (_("ambiguous memory operand size for `%s`"),
6080 for (op
= i
.operands
; --op
>= 0;)
6081 if (!i
.tm
.operand_types
[op
].bitfield
.inoutportreg
6082 && !i
.tm
.operand_types
[op
].bitfield
.shiftcount
)
6084 if (!i
.types
[op
].bitfield
.reg
)
6086 if (i
.types
[op
].bitfield
.byte
)
6087 i
.suffix
= BYTE_MNEM_SUFFIX
;
6088 else if (i
.types
[op
].bitfield
.word
)
6089 i
.suffix
= WORD_MNEM_SUFFIX
;
6090 else if (i
.types
[op
].bitfield
.dword
)
6091 i
.suffix
= LONG_MNEM_SUFFIX
;
6092 else if (i
.types
[op
].bitfield
.qword
)
6093 i
.suffix
= QWORD_MNEM_SUFFIX
;
6100 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
6103 && i
.tm
.opcode_modifier
.ignoresize
6104 && i
.tm
.opcode_modifier
.no_bsuf
)
6106 else if (!check_byte_reg ())
6109 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
6112 && i
.tm
.opcode_modifier
.ignoresize
6113 && i
.tm
.opcode_modifier
.no_lsuf
6114 && !i
.tm
.opcode_modifier
.todword
6115 && !i
.tm
.opcode_modifier
.toqword
)
6117 else if (!check_long_reg ())
6120 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
6123 && i
.tm
.opcode_modifier
.ignoresize
6124 && i
.tm
.opcode_modifier
.no_qsuf
6125 && !i
.tm
.opcode_modifier
.todword
6126 && !i
.tm
.opcode_modifier
.toqword
)
6128 else if (!check_qword_reg ())
6131 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
6134 && i
.tm
.opcode_modifier
.ignoresize
6135 && i
.tm
.opcode_modifier
.no_wsuf
)
6137 else if (!check_word_reg ())
6140 else if (intel_syntax
&& i
.tm
.opcode_modifier
.ignoresize
)
6141 /* Do nothing if the instruction is going to ignore the prefix. */
6146 else if (i
.tm
.opcode_modifier
.defaultsize
6148 /* exclude fldenv/frstor/fsave/fstenv */
6149 && i
.tm
.opcode_modifier
.no_ssuf
)
6151 i
.suffix
= stackop_size
;
6153 else if (intel_syntax
6155 && (i
.tm
.operand_types
[0].bitfield
.jumpabsolute
6156 || i
.tm
.opcode_modifier
.jumpbyte
6157 || i
.tm
.opcode_modifier
.jumpintersegment
6158 || (i
.tm
.base_opcode
== 0x0f01 /* [ls][gi]dt */
6159 && i
.tm
.extension_opcode
<= 3)))
6164 if (!i
.tm
.opcode_modifier
.no_qsuf
)
6166 i
.suffix
= QWORD_MNEM_SUFFIX
;
6171 if (!i
.tm
.opcode_modifier
.no_lsuf
)
6172 i
.suffix
= LONG_MNEM_SUFFIX
;
6175 if (!i
.tm
.opcode_modifier
.no_wsuf
)
6176 i
.suffix
= WORD_MNEM_SUFFIX
;
6185 if (i
.tm
.opcode_modifier
.w
)
6187 as_bad (_("no instruction mnemonic suffix given and "
6188 "no register operands; can't size instruction"));
6194 unsigned int suffixes
;
6196 suffixes
= !i
.tm
.opcode_modifier
.no_bsuf
;
6197 if (!i
.tm
.opcode_modifier
.no_wsuf
)
6199 if (!i
.tm
.opcode_modifier
.no_lsuf
)
6201 if (!i
.tm
.opcode_modifier
.no_ldsuf
)
6203 if (!i
.tm
.opcode_modifier
.no_ssuf
)
6205 if (flag_code
== CODE_64BIT
&& !i
.tm
.opcode_modifier
.no_qsuf
)
6208 /* There are more than suffix matches. */
6209 if (i
.tm
.opcode_modifier
.w
6210 || ((suffixes
& (suffixes
- 1))
6211 && !i
.tm
.opcode_modifier
.defaultsize
6212 && !i
.tm
.opcode_modifier
.ignoresize
))
6214 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
6220 /* Change the opcode based on the operand size given by i.suffix. */
6223 /* Size floating point instruction. */
6224 case LONG_MNEM_SUFFIX
:
6225 if (i
.tm
.opcode_modifier
.floatmf
)
6227 i
.tm
.base_opcode
^= 4;
6231 case WORD_MNEM_SUFFIX
:
6232 case QWORD_MNEM_SUFFIX
:
6233 /* It's not a byte, select word/dword operation. */
6234 if (i
.tm
.opcode_modifier
.w
)
6236 if (i
.tm
.opcode_modifier
.shortform
)
6237 i
.tm
.base_opcode
|= 8;
6239 i
.tm
.base_opcode
|= 1;
6242 case SHORT_MNEM_SUFFIX
:
6243 /* Now select between word & dword operations via the operand
6244 size prefix, except for instructions that will ignore this
6246 if (i
.reg_operands
> 0
6247 && i
.types
[0].bitfield
.reg
6248 && i
.tm
.opcode_modifier
.addrprefixopreg
6249 && (i
.tm
.opcode_modifier
.immext
6250 || i
.operands
== 1))
6252 /* The address size override prefix changes the size of the
6254 if ((flag_code
== CODE_32BIT
6255 && i
.op
[0].regs
->reg_type
.bitfield
.word
)
6256 || (flag_code
!= CODE_32BIT
6257 && i
.op
[0].regs
->reg_type
.bitfield
.dword
))
6258 if (!add_prefix (ADDR_PREFIX_OPCODE
))
6261 else if (i
.suffix
!= QWORD_MNEM_SUFFIX
6262 && !i
.tm
.opcode_modifier
.ignoresize
6263 && !i
.tm
.opcode_modifier
.floatmf
6264 && !i
.tm
.opcode_modifier
.vex
6265 && !i
.tm
.opcode_modifier
.vexopcode
6266 && !is_evex_encoding (&i
.tm
)
6267 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
6268 || (flag_code
== CODE_64BIT
6269 && i
.tm
.opcode_modifier
.jumpbyte
)))
6271 unsigned int prefix
= DATA_PREFIX_OPCODE
;
6273 if (i
.tm
.opcode_modifier
.jumpbyte
) /* jcxz, loop */
6274 prefix
= ADDR_PREFIX_OPCODE
;
6276 if (!add_prefix (prefix
))
6280 /* Set mode64 for an operand. */
6281 if (i
.suffix
== QWORD_MNEM_SUFFIX
6282 && flag_code
== CODE_64BIT
6283 && !i
.tm
.opcode_modifier
.norex64
6284 /* Special case for xchg %rax,%rax. It is NOP and doesn't
6286 && ! (i
.operands
== 2
6287 && i
.tm
.base_opcode
== 0x90
6288 && i
.tm
.extension_opcode
== None
6289 && operand_type_equal (&i
.types
[0], &acc64
)
6290 && operand_type_equal (&i
.types
[1], &acc64
)))
6296 if (i
.reg_operands
!= 0
6298 && i
.tm
.opcode_modifier
.addrprefixopreg
6299 && !i
.tm
.opcode_modifier
.immext
)
6301 /* Check invalid register operand when the address size override
6302 prefix changes the size of register operands. */
6304 enum { need_word
, need_dword
, need_qword
} need
;
6306 if (flag_code
== CODE_32BIT
)
6307 need
= i
.prefix
[ADDR_PREFIX
] ? need_word
: need_dword
;
6310 if (i
.prefix
[ADDR_PREFIX
])
6313 need
= flag_code
== CODE_64BIT
? need_qword
: need_word
;
6316 for (op
= 0; op
< i
.operands
; op
++)
6317 if (i
.types
[op
].bitfield
.reg
6318 && ((need
== need_word
6319 && !i
.op
[op
].regs
->reg_type
.bitfield
.word
)
6320 || (need
== need_dword
6321 && !i
.op
[op
].regs
->reg_type
.bitfield
.dword
)
6322 || (need
== need_qword
6323 && !i
.op
[op
].regs
->reg_type
.bitfield
.qword
)))
6325 as_bad (_("invalid register operand size for `%s'"),
6335 check_byte_reg (void)
6339 for (op
= i
.operands
; --op
>= 0;)
6341 /* Skip non-register operands. */
6342 if (!i
.types
[op
].bitfield
.reg
)
6345 /* If this is an eight bit register, it's OK. If it's the 16 or
6346 32 bit version of an eight bit register, we will just use the
6347 low portion, and that's OK too. */
6348 if (i
.types
[op
].bitfield
.byte
)
6351 /* I/O port address operands are OK too. */
6352 if (i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
6355 /* crc32 doesn't generate this warning. */
6356 if (i
.tm
.base_opcode
== 0xf20f38f0)
6359 if ((i
.types
[op
].bitfield
.word
6360 || i
.types
[op
].bitfield
.dword
6361 || i
.types
[op
].bitfield
.qword
)
6362 && i
.op
[op
].regs
->reg_num
< 4
6363 /* Prohibit these changes in 64bit mode, since the lowering
6364 would be more complicated. */
6365 && flag_code
!= CODE_64BIT
)
6367 #if REGISTER_WARNINGS
6368 if (!quiet_warnings
)
6369 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6371 (i
.op
[op
].regs
+ (i
.types
[op
].bitfield
.word
6372 ? REGNAM_AL
- REGNAM_AX
6373 : REGNAM_AL
- REGNAM_EAX
))->reg_name
,
6375 i
.op
[op
].regs
->reg_name
,
6380 /* Any other register is bad. */
6381 if (i
.types
[op
].bitfield
.reg
6382 || i
.types
[op
].bitfield
.regmmx
6383 || i
.types
[op
].bitfield
.regsimd
6384 || i
.types
[op
].bitfield
.sreg2
6385 || i
.types
[op
].bitfield
.sreg3
6386 || i
.types
[op
].bitfield
.control
6387 || i
.types
[op
].bitfield
.debug
6388 || i
.types
[op
].bitfield
.test
)
6390 as_bad (_("`%s%s' not allowed with `%s%c'"),
6392 i
.op
[op
].regs
->reg_name
,
6402 check_long_reg (void)
6406 for (op
= i
.operands
; --op
>= 0;)
6407 /* Skip non-register operands. */
6408 if (!i
.types
[op
].bitfield
.reg
)
6410 /* Reject eight bit registers, except where the template requires
6411 them. (eg. movzb) */
6412 else if (i
.types
[op
].bitfield
.byte
6413 && (i
.tm
.operand_types
[op
].bitfield
.reg
6414 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6415 && (i
.tm
.operand_types
[op
].bitfield
.word
6416 || i
.tm
.operand_types
[op
].bitfield
.dword
))
6418 as_bad (_("`%s%s' not allowed with `%s%c'"),
6420 i
.op
[op
].regs
->reg_name
,
6425 /* Warn if the e prefix on a general reg is missing. */
6426 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
6427 && i
.types
[op
].bitfield
.word
6428 && (i
.tm
.operand_types
[op
].bitfield
.reg
6429 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6430 && i
.tm
.operand_types
[op
].bitfield
.dword
)
6432 /* Prohibit these changes in the 64bit mode, since the
6433 lowering is more complicated. */
6434 if (flag_code
== CODE_64BIT
)
6436 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6437 register_prefix
, i
.op
[op
].regs
->reg_name
,
6441 #if REGISTER_WARNINGS
6442 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6444 (i
.op
[op
].regs
+ REGNAM_EAX
- REGNAM_AX
)->reg_name
,
6445 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
6448 /* Warn if the r prefix on a general reg is present. */
6449 else if (i
.types
[op
].bitfield
.qword
6450 && (i
.tm
.operand_types
[op
].bitfield
.reg
6451 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6452 && i
.tm
.operand_types
[op
].bitfield
.dword
)
6455 && i
.tm
.opcode_modifier
.toqword
6456 && !i
.types
[0].bitfield
.regsimd
)
6458 /* Convert to QWORD. We want REX byte. */
6459 i
.suffix
= QWORD_MNEM_SUFFIX
;
6463 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6464 register_prefix
, i
.op
[op
].regs
->reg_name
,
6473 check_qword_reg (void)
6477 for (op
= i
.operands
; --op
>= 0; )
6478 /* Skip non-register operands. */
6479 if (!i
.types
[op
].bitfield
.reg
)
6481 /* Reject eight bit registers, except where the template requires
6482 them. (eg. movzb) */
6483 else if (i
.types
[op
].bitfield
.byte
6484 && (i
.tm
.operand_types
[op
].bitfield
.reg
6485 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6486 && (i
.tm
.operand_types
[op
].bitfield
.word
6487 || i
.tm
.operand_types
[op
].bitfield
.dword
))
6489 as_bad (_("`%s%s' not allowed with `%s%c'"),
6491 i
.op
[op
].regs
->reg_name
,
6496 /* Warn if the r prefix on a general reg is missing. */
6497 else if ((i
.types
[op
].bitfield
.word
6498 || i
.types
[op
].bitfield
.dword
)
6499 && (i
.tm
.operand_types
[op
].bitfield
.reg
6500 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6501 && i
.tm
.operand_types
[op
].bitfield
.qword
)
6503 /* Prohibit these changes in the 64bit mode, since the
6504 lowering is more complicated. */
6506 && i
.tm
.opcode_modifier
.todword
6507 && !i
.types
[0].bitfield
.regsimd
)
6509 /* Convert to DWORD. We don't want REX byte. */
6510 i
.suffix
= LONG_MNEM_SUFFIX
;
6514 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6515 register_prefix
, i
.op
[op
].regs
->reg_name
,
6524 check_word_reg (void)
6527 for (op
= i
.operands
; --op
>= 0;)
6528 /* Skip non-register operands. */
6529 if (!i
.types
[op
].bitfield
.reg
)
6531 /* Reject eight bit registers, except where the template requires
6532 them. (eg. movzb) */
6533 else if (i
.types
[op
].bitfield
.byte
6534 && (i
.tm
.operand_types
[op
].bitfield
.reg
6535 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6536 && (i
.tm
.operand_types
[op
].bitfield
.word
6537 || i
.tm
.operand_types
[op
].bitfield
.dword
))
6539 as_bad (_("`%s%s' not allowed with `%s%c'"),
6541 i
.op
[op
].regs
->reg_name
,
6546 /* Warn if the e or r prefix on a general reg is present. */
6547 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
6548 && (i
.types
[op
].bitfield
.dword
6549 || i
.types
[op
].bitfield
.qword
)
6550 && (i
.tm
.operand_types
[op
].bitfield
.reg
6551 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6552 && i
.tm
.operand_types
[op
].bitfield
.word
)
6554 /* Prohibit these changes in the 64bit mode, since the
6555 lowering is more complicated. */
6556 if (flag_code
== CODE_64BIT
)
6558 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6559 register_prefix
, i
.op
[op
].regs
->reg_name
,
6563 #if REGISTER_WARNINGS
6564 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6566 (i
.op
[op
].regs
+ REGNAM_AX
- REGNAM_EAX
)->reg_name
,
6567 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
6574 update_imm (unsigned int j
)
6576 i386_operand_type overlap
= i
.types
[j
];
6577 if ((overlap
.bitfield
.imm8
6578 || overlap
.bitfield
.imm8s
6579 || overlap
.bitfield
.imm16
6580 || overlap
.bitfield
.imm32
6581 || overlap
.bitfield
.imm32s
6582 || overlap
.bitfield
.imm64
)
6583 && !operand_type_equal (&overlap
, &imm8
)
6584 && !operand_type_equal (&overlap
, &imm8s
)
6585 && !operand_type_equal (&overlap
, &imm16
)
6586 && !operand_type_equal (&overlap
, &imm32
)
6587 && !operand_type_equal (&overlap
, &imm32s
)
6588 && !operand_type_equal (&overlap
, &imm64
))
6592 i386_operand_type temp
;
6594 operand_type_set (&temp
, 0);
6595 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
6597 temp
.bitfield
.imm8
= overlap
.bitfield
.imm8
;
6598 temp
.bitfield
.imm8s
= overlap
.bitfield
.imm8s
;
6600 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
6601 temp
.bitfield
.imm16
= overlap
.bitfield
.imm16
;
6602 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
6604 temp
.bitfield
.imm64
= overlap
.bitfield
.imm64
;
6605 temp
.bitfield
.imm32s
= overlap
.bitfield
.imm32s
;
6608 temp
.bitfield
.imm32
= overlap
.bitfield
.imm32
;
6611 else if (operand_type_equal (&overlap
, &imm16_32_32s
)
6612 || operand_type_equal (&overlap
, &imm16_32
)
6613 || operand_type_equal (&overlap
, &imm16_32s
))
6615 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
6620 if (!operand_type_equal (&overlap
, &imm8
)
6621 && !operand_type_equal (&overlap
, &imm8s
)
6622 && !operand_type_equal (&overlap
, &imm16
)
6623 && !operand_type_equal (&overlap
, &imm32
)
6624 && !operand_type_equal (&overlap
, &imm32s
)
6625 && !operand_type_equal (&overlap
, &imm64
))
6627 as_bad (_("no instruction mnemonic suffix given; "
6628 "can't determine immediate size"));
6632 i
.types
[j
] = overlap
;
6642 /* Update the first 2 immediate operands. */
6643 n
= i
.operands
> 2 ? 2 : i
.operands
;
6646 for (j
= 0; j
< n
; j
++)
6647 if (update_imm (j
) == 0)
6650 /* The 3rd operand can't be immediate operand. */
6651 gas_assert (operand_type_check (i
.types
[2], imm
) == 0);
6658 process_operands (void)
6660 /* Default segment register this instruction will use for memory
6661 accesses. 0 means unknown. This is only for optimizing out
6662 unnecessary segment overrides. */
6663 const seg_entry
*default_seg
= 0;
6665 if (i
.tm
.opcode_modifier
.sse2avx
&& i
.tm
.opcode_modifier
.vexvvvv
)
6667 unsigned int dupl
= i
.operands
;
6668 unsigned int dest
= dupl
- 1;
6671 /* The destination must be an xmm register. */
6672 gas_assert (i
.reg_operands
6673 && MAX_OPERANDS
> dupl
6674 && operand_type_equal (&i
.types
[dest
], ®xmm
));
6676 if (i
.tm
.operand_types
[0].bitfield
.acc
6677 && i
.tm
.operand_types
[0].bitfield
.xmmword
)
6679 if (i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
)
6681 /* Keep xmm0 for instructions with VEX prefix and 3
6683 i
.tm
.operand_types
[0].bitfield
.acc
= 0;
6684 i
.tm
.operand_types
[0].bitfield
.regsimd
= 1;
6689 /* We remove the first xmm0 and keep the number of
6690 operands unchanged, which in fact duplicates the
6692 for (j
= 1; j
< i
.operands
; j
++)
6694 i
.op
[j
- 1] = i
.op
[j
];
6695 i
.types
[j
- 1] = i
.types
[j
];
6696 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
6700 else if (i
.tm
.opcode_modifier
.implicit1stxmm0
)
6702 gas_assert ((MAX_OPERANDS
- 1) > dupl
6703 && (i
.tm
.opcode_modifier
.vexsources
6706 /* Add the implicit xmm0 for instructions with VEX prefix
6708 for (j
= i
.operands
; j
> 0; j
--)
6710 i
.op
[j
] = i
.op
[j
- 1];
6711 i
.types
[j
] = i
.types
[j
- 1];
6712 i
.tm
.operand_types
[j
] = i
.tm
.operand_types
[j
- 1];
6715 = (const reg_entry
*) hash_find (reg_hash
, "xmm0");
6716 i
.types
[0] = regxmm
;
6717 i
.tm
.operand_types
[0] = regxmm
;
6720 i
.reg_operands
+= 2;
6725 i
.op
[dupl
] = i
.op
[dest
];
6726 i
.types
[dupl
] = i
.types
[dest
];
6727 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
6736 i
.op
[dupl
] = i
.op
[dest
];
6737 i
.types
[dupl
] = i
.types
[dest
];
6738 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
6741 if (i
.tm
.opcode_modifier
.immext
)
6744 else if (i
.tm
.operand_types
[0].bitfield
.acc
6745 && i
.tm
.operand_types
[0].bitfield
.xmmword
)
6749 for (j
= 1; j
< i
.operands
; j
++)
6751 i
.op
[j
- 1] = i
.op
[j
];
6752 i
.types
[j
- 1] = i
.types
[j
];
6754 /* We need to adjust fields in i.tm since they are used by
6755 build_modrm_byte. */
6756 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
6763 else if (i
.tm
.opcode_modifier
.implicitquadgroup
)
6765 unsigned int regnum
, first_reg_in_group
, last_reg_in_group
;
6767 /* The second operand must be {x,y,z}mmN, where N is a multiple of 4. */
6768 gas_assert (i
.operands
>= 2 && i
.types
[1].bitfield
.regsimd
);
6769 regnum
= register_number (i
.op
[1].regs
);
6770 first_reg_in_group
= regnum
& ~3;
6771 last_reg_in_group
= first_reg_in_group
+ 3;
6772 if (regnum
!= first_reg_in_group
)
6773 as_warn (_("source register `%s%s' implicitly denotes"
6774 " `%s%.3s%u' to `%s%.3s%u' source group in `%s'"),
6775 register_prefix
, i
.op
[1].regs
->reg_name
,
6776 register_prefix
, i
.op
[1].regs
->reg_name
, first_reg_in_group
,
6777 register_prefix
, i
.op
[1].regs
->reg_name
, last_reg_in_group
,
6780 else if (i
.tm
.opcode_modifier
.regkludge
)
6782 /* The imul $imm, %reg instruction is converted into
6783 imul $imm, %reg, %reg, and the clr %reg instruction
6784 is converted into xor %reg, %reg. */
6786 unsigned int first_reg_op
;
6788 if (operand_type_check (i
.types
[0], reg
))
6792 /* Pretend we saw the extra register operand. */
6793 gas_assert (i
.reg_operands
== 1
6794 && i
.op
[first_reg_op
+ 1].regs
== 0);
6795 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
6796 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
6801 if (i
.tm
.opcode_modifier
.shortform
)
6803 if (i
.types
[0].bitfield
.sreg2
6804 || i
.types
[0].bitfield
.sreg3
)
6806 if (i
.tm
.base_opcode
== POP_SEG_SHORT
6807 && i
.op
[0].regs
->reg_num
== 1)
6809 as_bad (_("you can't `pop %scs'"), register_prefix
);
6812 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
6813 if ((i
.op
[0].regs
->reg_flags
& RegRex
) != 0)
6818 /* The register or float register operand is in operand
6822 if ((i
.types
[0].bitfield
.reg
&& i
.types
[0].bitfield
.tbyte
)
6823 || operand_type_check (i
.types
[0], reg
))
6827 /* Register goes in low 3 bits of opcode. */
6828 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
6829 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
6831 if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
6833 /* Warn about some common errors, but press on regardless.
6834 The first case can be generated by gcc (<= 2.8.1). */
6835 if (i
.operands
== 2)
6837 /* Reversed arguments on faddp, fsubp, etc. */
6838 as_warn (_("translating to `%s %s%s,%s%s'"), i
.tm
.name
,
6839 register_prefix
, i
.op
[!intel_syntax
].regs
->reg_name
,
6840 register_prefix
, i
.op
[intel_syntax
].regs
->reg_name
);
6844 /* Extraneous `l' suffix on fp insn. */
6845 as_warn (_("translating to `%s %s%s'"), i
.tm
.name
,
6846 register_prefix
, i
.op
[0].regs
->reg_name
);
6851 else if (i
.tm
.opcode_modifier
.modrm
)
6853 /* The opcode is completed (modulo i.tm.extension_opcode which
6854 must be put into the modrm byte). Now, we make the modrm and
6855 index base bytes based on all the info we've collected. */
6857 default_seg
= build_modrm_byte ();
6859 else if ((i
.tm
.base_opcode
& ~0x3) == MOV_AX_DISP32
)
6863 else if (i
.tm
.opcode_modifier
.isstring
)
6865 /* For the string instructions that allow a segment override
6866 on one of their operands, the default segment is ds. */
6870 if (i
.tm
.base_opcode
== 0x8d /* lea */
6873 as_warn (_("segment override on `%s' is ineffectual"), i
.tm
.name
);
6875 /* If a segment was explicitly specified, and the specified segment
6876 is not the default, use an opcode prefix to select it. If we
6877 never figured out what the default segment is, then default_seg
6878 will be zero at this point, and the specified segment prefix will
6880 if ((i
.seg
[0]) && (i
.seg
[0] != default_seg
))
6882 if (!add_prefix (i
.seg
[0]->seg_prefix
))
6888 static const seg_entry
*
6889 build_modrm_byte (void)
6891 const seg_entry
*default_seg
= 0;
6892 unsigned int source
, dest
;
6895 vex_3_sources
= i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
;
6898 unsigned int nds
, reg_slot
;
6901 dest
= i
.operands
- 1;
6904 /* There are 2 kinds of instructions:
6905 1. 5 operands: 4 register operands or 3 register operands
6906 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
6907 VexW0 or VexW1. The destination must be either XMM, YMM or
6909 2. 4 operands: 4 register operands or 3 register operands
6910 plus 1 memory operand, with VexXDS. */
6911 gas_assert ((i
.reg_operands
== 4
6912 || (i
.reg_operands
== 3 && i
.mem_operands
== 1))
6913 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
6914 && i
.tm
.opcode_modifier
.vexw
6915 && i
.tm
.operand_types
[dest
].bitfield
.regsimd
);
6917 /* If VexW1 is set, the first non-immediate operand is the source and
6918 the second non-immediate one is encoded in the immediate operand. */
6919 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
6921 source
= i
.imm_operands
;
6922 reg_slot
= i
.imm_operands
+ 1;
6926 source
= i
.imm_operands
+ 1;
6927 reg_slot
= i
.imm_operands
;
6930 if (i
.imm_operands
== 0)
6932 /* When there is no immediate operand, generate an 8bit
6933 immediate operand to encode the first operand. */
6934 exp
= &im_expressions
[i
.imm_operands
++];
6935 i
.op
[i
.operands
].imms
= exp
;
6936 i
.types
[i
.operands
] = imm8
;
6939 gas_assert (i
.tm
.operand_types
[reg_slot
].bitfield
.regsimd
);
6940 exp
->X_op
= O_constant
;
6941 exp
->X_add_number
= register_number (i
.op
[reg_slot
].regs
) << 4;
6942 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
6946 unsigned int imm_slot
;
6948 gas_assert (i
.imm_operands
== 1 && i
.types
[0].bitfield
.vec_imm4
);
6950 if (i
.tm
.opcode_modifier
.immext
)
6952 /* When ImmExt is set, the immediate byte is the last
6954 imm_slot
= i
.operands
- 1;
6962 /* Turn on Imm8 so that output_imm will generate it. */
6963 i
.types
[imm_slot
].bitfield
.imm8
= 1;
6966 gas_assert (i
.tm
.operand_types
[reg_slot
].bitfield
.regsimd
);
6967 i
.op
[imm_slot
].imms
->X_add_number
6968 |= register_number (i
.op
[reg_slot
].regs
) << 4;
6969 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
6972 gas_assert (i
.tm
.operand_types
[nds
].bitfield
.regsimd
);
6973 i
.vex
.register_specifier
= i
.op
[nds
].regs
;
6978 /* i.reg_operands MUST be the number of real register operands;
6979 implicit registers do not count. If there are 3 register
6980 operands, it must be a instruction with VexNDS. For a
6981 instruction with VexNDD, the destination register is encoded
6982 in VEX prefix. If there are 4 register operands, it must be
6983 a instruction with VEX prefix and 3 sources. */
6984 if (i
.mem_operands
== 0
6985 && ((i
.reg_operands
== 2
6986 && i
.tm
.opcode_modifier
.vexvvvv
<= VEXXDS
)
6987 || (i
.reg_operands
== 3
6988 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
6989 || (i
.reg_operands
== 4 && vex_3_sources
)))
6997 /* When there are 3 operands, one of them may be immediate,
6998 which may be the first or the last operand. Otherwise,
6999 the first operand must be shift count register (cl) or it
7000 is an instruction with VexNDS. */
7001 gas_assert (i
.imm_operands
== 1
7002 || (i
.imm_operands
== 0
7003 && (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
7004 || i
.types
[0].bitfield
.shiftcount
)));
7005 if (operand_type_check (i
.types
[0], imm
)
7006 || i
.types
[0].bitfield
.shiftcount
)
7012 /* When there are 4 operands, the first two must be 8bit
7013 immediate operands. The source operand will be the 3rd
7016 For instructions with VexNDS, if the first operand
7017 an imm8, the source operand is the 2nd one. If the last
7018 operand is imm8, the source operand is the first one. */
7019 gas_assert ((i
.imm_operands
== 2
7020 && i
.types
[0].bitfield
.imm8
7021 && i
.types
[1].bitfield
.imm8
)
7022 || (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
7023 && i
.imm_operands
== 1
7024 && (i
.types
[0].bitfield
.imm8
7025 || i
.types
[i
.operands
- 1].bitfield
.imm8
7027 if (i
.imm_operands
== 2)
7031 if (i
.types
[0].bitfield
.imm8
)
7038 if (is_evex_encoding (&i
.tm
))
7040 /* For EVEX instructions, when there are 5 operands, the
7041 first one must be immediate operand. If the second one
7042 is immediate operand, the source operand is the 3th
7043 one. If the last one is immediate operand, the source
7044 operand is the 2nd one. */
7045 gas_assert (i
.imm_operands
== 2
7046 && i
.tm
.opcode_modifier
.sae
7047 && operand_type_check (i
.types
[0], imm
));
7048 if (operand_type_check (i
.types
[1], imm
))
7050 else if (operand_type_check (i
.types
[4], imm
))
7064 /* RC/SAE operand could be between DEST and SRC. That happens
7065 when one operand is GPR and the other one is XMM/YMM/ZMM
7067 if (i
.rounding
&& i
.rounding
->operand
== (int) dest
)
7070 if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
7072 /* For instructions with VexNDS, the register-only source
7073 operand must be a 32/64bit integer, XMM, YMM, ZMM, or mask
7074 register. It is encoded in VEX prefix. We need to
7075 clear RegMem bit before calling operand_type_equal. */
7077 i386_operand_type op
;
7080 /* Check register-only source operand when two source
7081 operands are swapped. */
7082 if (!i
.tm
.operand_types
[source
].bitfield
.baseindex
7083 && i
.tm
.operand_types
[dest
].bitfield
.baseindex
)
7091 op
= i
.tm
.operand_types
[vvvv
];
7092 op
.bitfield
.regmem
= 0;
7093 if ((dest
+ 1) >= i
.operands
7094 || ((!op
.bitfield
.reg
7095 || (!op
.bitfield
.dword
&& !op
.bitfield
.qword
))
7096 && !op
.bitfield
.regsimd
7097 && !operand_type_equal (&op
, ®mask
)))
7099 i
.vex
.register_specifier
= i
.op
[vvvv
].regs
;
7105 /* One of the register operands will be encoded in the i.tm.reg
7106 field, the other in the combined i.tm.mode and i.tm.regmem
7107 fields. If no form of this instruction supports a memory
7108 destination operand, then we assume the source operand may
7109 sometimes be a memory operand and so we need to store the
7110 destination in the i.rm.reg field. */
7111 if (!i
.tm
.operand_types
[dest
].bitfield
.regmem
7112 && operand_type_check (i
.tm
.operand_types
[dest
], anymem
) == 0)
7114 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
7115 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
7116 if (i
.op
[dest
].regs
->reg_type
.bitfield
.regmmx
7117 || i
.op
[source
].regs
->reg_type
.bitfield
.regmmx
)
7118 i
.has_regmmx
= TRUE
;
7119 else if (i
.op
[dest
].regs
->reg_type
.bitfield
.regsimd
7120 || i
.op
[source
].regs
->reg_type
.bitfield
.regsimd
)
7122 if (i
.types
[dest
].bitfield
.zmmword
7123 || i
.types
[source
].bitfield
.zmmword
)
7124 i
.has_regzmm
= TRUE
;
7125 else if (i
.types
[dest
].bitfield
.ymmword
7126 || i
.types
[source
].bitfield
.ymmword
)
7127 i
.has_regymm
= TRUE
;
7129 i
.has_regxmm
= TRUE
;
7131 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
7133 if ((i
.op
[dest
].regs
->reg_flags
& RegVRex
) != 0)
7135 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
7137 if ((i
.op
[source
].regs
->reg_flags
& RegVRex
) != 0)
7142 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
7143 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
7144 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
7146 if ((i
.op
[dest
].regs
->reg_flags
& RegVRex
) != 0)
7148 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
7150 if ((i
.op
[source
].regs
->reg_flags
& RegVRex
) != 0)
7153 if (flag_code
!= CODE_64BIT
&& (i
.rex
& REX_R
))
7155 if (!i
.types
[i
.tm
.operand_types
[0].bitfield
.regmem
].bitfield
.control
)
7158 add_prefix (LOCK_PREFIX_OPCODE
);
7162 { /* If it's not 2 reg operands... */
7167 unsigned int fake_zero_displacement
= 0;
7170 for (op
= 0; op
< i
.operands
; op
++)
7171 if (operand_type_check (i
.types
[op
], anymem
))
7173 gas_assert (op
< i
.operands
);
7175 if (i
.tm
.opcode_modifier
.vecsib
)
7177 if (i
.index_reg
->reg_num
== RegIZ
)
7180 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
7183 i
.sib
.base
= NO_BASE_REGISTER
;
7184 i
.sib
.scale
= i
.log2_scale_factor
;
7185 i
.types
[op
].bitfield
.disp8
= 0;
7186 i
.types
[op
].bitfield
.disp16
= 0;
7187 i
.types
[op
].bitfield
.disp64
= 0;
7188 if (flag_code
!= CODE_64BIT
|| i
.prefix
[ADDR_PREFIX
])
7190 /* Must be 32 bit */
7191 i
.types
[op
].bitfield
.disp32
= 1;
7192 i
.types
[op
].bitfield
.disp32s
= 0;
7196 i
.types
[op
].bitfield
.disp32
= 0;
7197 i
.types
[op
].bitfield
.disp32s
= 1;
7200 i
.sib
.index
= i
.index_reg
->reg_num
;
7201 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
7203 if ((i
.index_reg
->reg_flags
& RegVRex
) != 0)
7209 if (i
.base_reg
== 0)
7212 if (!i
.disp_operands
)
7213 fake_zero_displacement
= 1;
7214 if (i
.index_reg
== 0)
7216 i386_operand_type newdisp
;
7218 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
7219 /* Operand is just <disp> */
7220 if (flag_code
== CODE_64BIT
)
7222 /* 64bit mode overwrites the 32bit absolute
7223 addressing by RIP relative addressing and
7224 absolute addressing is encoded by one of the
7225 redundant SIB forms. */
7226 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
7227 i
.sib
.base
= NO_BASE_REGISTER
;
7228 i
.sib
.index
= NO_INDEX_REGISTER
;
7229 newdisp
= (!i
.prefix
[ADDR_PREFIX
] ? disp32s
: disp32
);
7231 else if ((flag_code
== CODE_16BIT
)
7232 ^ (i
.prefix
[ADDR_PREFIX
] != 0))
7234 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
7239 i
.rm
.regmem
= NO_BASE_REGISTER
;
7242 i
.types
[op
] = operand_type_and_not (i
.types
[op
], anydisp
);
7243 i
.types
[op
] = operand_type_or (i
.types
[op
], newdisp
);
7245 else if (!i
.tm
.opcode_modifier
.vecsib
)
7247 /* !i.base_reg && i.index_reg */
7248 if (i
.index_reg
->reg_num
== RegIZ
)
7249 i
.sib
.index
= NO_INDEX_REGISTER
;
7251 i
.sib
.index
= i
.index_reg
->reg_num
;
7252 i
.sib
.base
= NO_BASE_REGISTER
;
7253 i
.sib
.scale
= i
.log2_scale_factor
;
7254 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
7255 i
.types
[op
].bitfield
.disp8
= 0;
7256 i
.types
[op
].bitfield
.disp16
= 0;
7257 i
.types
[op
].bitfield
.disp64
= 0;
7258 if (flag_code
!= CODE_64BIT
|| i
.prefix
[ADDR_PREFIX
])
7260 /* Must be 32 bit */
7261 i
.types
[op
].bitfield
.disp32
= 1;
7262 i
.types
[op
].bitfield
.disp32s
= 0;
7266 i
.types
[op
].bitfield
.disp32
= 0;
7267 i
.types
[op
].bitfield
.disp32s
= 1;
7269 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
7273 /* RIP addressing for 64bit mode. */
7274 else if (i
.base_reg
->reg_num
== RegIP
)
7276 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
7277 i
.rm
.regmem
= NO_BASE_REGISTER
;
7278 i
.types
[op
].bitfield
.disp8
= 0;
7279 i
.types
[op
].bitfield
.disp16
= 0;
7280 i
.types
[op
].bitfield
.disp32
= 0;
7281 i
.types
[op
].bitfield
.disp32s
= 1;
7282 i
.types
[op
].bitfield
.disp64
= 0;
7283 i
.flags
[op
] |= Operand_PCrel
;
7284 if (! i
.disp_operands
)
7285 fake_zero_displacement
= 1;
7287 else if (i
.base_reg
->reg_type
.bitfield
.word
)
7289 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
7290 switch (i
.base_reg
->reg_num
)
7293 if (i
.index_reg
== 0)
7295 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
7296 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
7300 if (i
.index_reg
== 0)
7303 if (operand_type_check (i
.types
[op
], disp
) == 0)
7305 /* fake (%bp) into 0(%bp) */
7306 i
.types
[op
].bitfield
.disp8
= 1;
7307 fake_zero_displacement
= 1;
7310 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
7311 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
7313 default: /* (%si) -> 4 or (%di) -> 5 */
7314 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
7316 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
7318 else /* i.base_reg and 32/64 bit mode */
7320 if (flag_code
== CODE_64BIT
7321 && operand_type_check (i
.types
[op
], disp
))
7323 i
.types
[op
].bitfield
.disp16
= 0;
7324 i
.types
[op
].bitfield
.disp64
= 0;
7325 if (i
.prefix
[ADDR_PREFIX
] == 0)
7327 i
.types
[op
].bitfield
.disp32
= 0;
7328 i
.types
[op
].bitfield
.disp32s
= 1;
7332 i
.types
[op
].bitfield
.disp32
= 1;
7333 i
.types
[op
].bitfield
.disp32s
= 0;
7337 if (!i
.tm
.opcode_modifier
.vecsib
)
7338 i
.rm
.regmem
= i
.base_reg
->reg_num
;
7339 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
7341 i
.sib
.base
= i
.base_reg
->reg_num
;
7342 /* x86-64 ignores REX prefix bit here to avoid decoder
7344 if (!(i
.base_reg
->reg_flags
& RegRex
)
7345 && (i
.base_reg
->reg_num
== EBP_REG_NUM
7346 || i
.base_reg
->reg_num
== ESP_REG_NUM
))
7348 if (i
.base_reg
->reg_num
== 5 && i
.disp_operands
== 0)
7350 fake_zero_displacement
= 1;
7351 i
.types
[op
].bitfield
.disp8
= 1;
7353 i
.sib
.scale
= i
.log2_scale_factor
;
7354 if (i
.index_reg
== 0)
7356 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
7357 /* <disp>(%esp) becomes two byte modrm with no index
7358 register. We've already stored the code for esp
7359 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
7360 Any base register besides %esp will not use the
7361 extra modrm byte. */
7362 i
.sib
.index
= NO_INDEX_REGISTER
;
7364 else if (!i
.tm
.opcode_modifier
.vecsib
)
7366 if (i
.index_reg
->reg_num
== RegIZ
)
7367 i
.sib
.index
= NO_INDEX_REGISTER
;
7369 i
.sib
.index
= i
.index_reg
->reg_num
;
7370 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
7371 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
7376 && (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
7377 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
))
7381 if (!fake_zero_displacement
7385 fake_zero_displacement
= 1;
7386 if (i
.disp_encoding
== disp_encoding_8bit
)
7387 i
.types
[op
].bitfield
.disp8
= 1;
7389 i
.types
[op
].bitfield
.disp32
= 1;
7391 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
7395 if (fake_zero_displacement
)
7397 /* Fakes a zero displacement assuming that i.types[op]
7398 holds the correct displacement size. */
7401 gas_assert (i
.op
[op
].disps
== 0);
7402 exp
= &disp_expressions
[i
.disp_operands
++];
7403 i
.op
[op
].disps
= exp
;
7404 exp
->X_op
= O_constant
;
7405 exp
->X_add_number
= 0;
7406 exp
->X_add_symbol
= (symbolS
*) 0;
7407 exp
->X_op_symbol
= (symbolS
*) 0;
7415 if (i
.tm
.opcode_modifier
.vexsources
== XOP2SOURCES
)
7417 if (operand_type_check (i
.types
[0], imm
))
7418 i
.vex
.register_specifier
= NULL
;
7421 /* VEX.vvvv encodes one of the sources when the first
7422 operand is not an immediate. */
7423 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
7424 i
.vex
.register_specifier
= i
.op
[0].regs
;
7426 i
.vex
.register_specifier
= i
.op
[1].regs
;
7429 /* Destination is a XMM register encoded in the ModRM.reg
7431 i
.rm
.reg
= i
.op
[2].regs
->reg_num
;
7432 if ((i
.op
[2].regs
->reg_flags
& RegRex
) != 0)
7435 /* ModRM.rm and VEX.B encodes the other source. */
7436 if (!i
.mem_operands
)
7440 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
7441 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
7443 i
.rm
.regmem
= i
.op
[0].regs
->reg_num
;
7445 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
7449 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXLWP
)
7451 i
.vex
.register_specifier
= i
.op
[2].regs
;
7452 if (!i
.mem_operands
)
7455 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
7456 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
7460 /* Fill in i.rm.reg or i.rm.regmem field with register operand
7461 (if any) based on i.tm.extension_opcode. Again, we must be
7462 careful to make sure that segment/control/debug/test/MMX
7463 registers are coded into the i.rm.reg field. */
7464 else if (i
.reg_operands
)
7467 unsigned int vex_reg
= ~0;
7469 for (op
= 0; op
< i
.operands
; op
++)
7471 if (i
.types
[op
].bitfield
.reg
7472 || i
.types
[op
].bitfield
.regbnd
7473 || i
.types
[op
].bitfield
.regmask
7474 || i
.types
[op
].bitfield
.sreg2
7475 || i
.types
[op
].bitfield
.sreg3
7476 || i
.types
[op
].bitfield
.control
7477 || i
.types
[op
].bitfield
.debug
7478 || i
.types
[op
].bitfield
.test
)
7480 if (i
.types
[op
].bitfield
.regsimd
)
7482 if (i
.types
[op
].bitfield
.zmmword
)
7483 i
.has_regzmm
= TRUE
;
7484 else if (i
.types
[op
].bitfield
.ymmword
)
7485 i
.has_regymm
= TRUE
;
7487 i
.has_regxmm
= TRUE
;
7490 if (i
.types
[op
].bitfield
.regmmx
)
7492 i
.has_regmmx
= TRUE
;
7499 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
7501 /* For instructions with VexNDS, the register-only
7502 source operand is encoded in VEX prefix. */
7503 gas_assert (mem
!= (unsigned int) ~0);
7508 gas_assert (op
< i
.operands
);
7512 /* Check register-only source operand when two source
7513 operands are swapped. */
7514 if (!i
.tm
.operand_types
[op
].bitfield
.baseindex
7515 && i
.tm
.operand_types
[op
+ 1].bitfield
.baseindex
)
7519 gas_assert (mem
== (vex_reg
+ 1)
7520 && op
< i
.operands
);
7525 gas_assert (vex_reg
< i
.operands
);
7529 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXNDD
)
7531 /* For instructions with VexNDD, the register destination
7532 is encoded in VEX prefix. */
7533 if (i
.mem_operands
== 0)
7535 /* There is no memory operand. */
7536 gas_assert ((op
+ 2) == i
.operands
);
7541 /* There are only 2 non-immediate operands. */
7542 gas_assert (op
< i
.imm_operands
+ 2
7543 && i
.operands
== i
.imm_operands
+ 2);
7544 vex_reg
= i
.imm_operands
+ 1;
7548 gas_assert (op
< i
.operands
);
7550 if (vex_reg
!= (unsigned int) ~0)
7552 i386_operand_type
*type
= &i
.tm
.operand_types
[vex_reg
];
7554 if ((!type
->bitfield
.reg
7555 || (!type
->bitfield
.dword
&& !type
->bitfield
.qword
))
7556 && !type
->bitfield
.regsimd
7557 && !operand_type_equal (type
, ®mask
))
7560 i
.vex
.register_specifier
= i
.op
[vex_reg
].regs
;
7563 /* Don't set OP operand twice. */
7566 /* If there is an extension opcode to put here, the
7567 register number must be put into the regmem field. */
7568 if (i
.tm
.extension_opcode
!= None
)
7570 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
7571 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
7573 if ((i
.op
[op
].regs
->reg_flags
& RegVRex
) != 0)
7578 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
7579 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
7581 if ((i
.op
[op
].regs
->reg_flags
& RegVRex
) != 0)
7586 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
7587 must set it to 3 to indicate this is a register operand
7588 in the regmem field. */
7589 if (!i
.mem_operands
)
7593 /* Fill in i.rm.reg field with extension opcode (if any). */
7594 if (i
.tm
.extension_opcode
!= None
)
7595 i
.rm
.reg
= i
.tm
.extension_opcode
;
7601 output_branch (void)
7607 relax_substateT subtype
;
7611 code16
= flag_code
== CODE_16BIT
? CODE16
: 0;
7612 size
= i
.disp_encoding
== disp_encoding_32bit
? BIG
: SMALL
;
7615 if (i
.prefix
[DATA_PREFIX
] != 0)
7621 /* Pentium4 branch hints. */
7622 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
7623 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
7628 if (i
.prefix
[REX_PREFIX
] != 0)
7634 /* BND prefixed jump. */
7635 if (i
.prefix
[BND_PREFIX
] != 0)
7637 FRAG_APPEND_1_CHAR (i
.prefix
[BND_PREFIX
]);
7641 if (i
.prefixes
!= 0 && !intel_syntax
)
7642 as_warn (_("skipping prefixes on this instruction"));
7644 /* It's always a symbol; End frag & setup for relax.
7645 Make sure there is enough room in this frag for the largest
7646 instruction we may generate in md_convert_frag. This is 2
7647 bytes for the opcode and room for the prefix and largest
7649 frag_grow (prefix
+ 2 + 4);
7650 /* Prefix and 1 opcode byte go in fr_fix. */
7651 p
= frag_more (prefix
+ 1);
7652 if (i
.prefix
[DATA_PREFIX
] != 0)
7653 *p
++ = DATA_PREFIX_OPCODE
;
7654 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
7655 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
7656 *p
++ = i
.prefix
[SEG_PREFIX
];
7657 if (i
.prefix
[REX_PREFIX
] != 0)
7658 *p
++ = i
.prefix
[REX_PREFIX
];
7659 *p
= i
.tm
.base_opcode
;
7661 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
7662 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, size
);
7663 else if (cpu_arch_flags
.bitfield
.cpui386
)
7664 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, size
);
7666 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, size
);
7669 sym
= i
.op
[0].disps
->X_add_symbol
;
7670 off
= i
.op
[0].disps
->X_add_number
;
7672 if (i
.op
[0].disps
->X_op
!= O_constant
7673 && i
.op
[0].disps
->X_op
!= O_symbol
)
7675 /* Handle complex expressions. */
7676 sym
= make_expr_symbol (i
.op
[0].disps
);
7680 /* 1 possible extra opcode + 4 byte displacement go in var part.
7681 Pass reloc in fr_var. */
7682 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
7685 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7686 /* Return TRUE iff PLT32 relocation should be used for branching to
7690 need_plt32_p (symbolS
*s
)
7692 /* PLT32 relocation is ELF only. */
7696 /* Since there is no need to prepare for PLT branch on x86-64, we
7697 can generate R_X86_64_PLT32, instead of R_X86_64_PC32, which can
7698 be used as a marker for 32-bit PC-relative branches. */
7702 /* Weak or undefined symbol need PLT32 relocation. */
7703 if (S_IS_WEAK (s
) || !S_IS_DEFINED (s
))
7706 /* Non-global symbol doesn't need PLT32 relocation. */
7707 if (! S_IS_EXTERNAL (s
))
7710 /* Other global symbols need PLT32 relocation. NB: Symbol with
7711 non-default visibilities are treated as normal global symbol
7712 so that PLT32 relocation can be used as a marker for 32-bit
7713 PC-relative branches. It is useful for linker relaxation. */
7724 bfd_reloc_code_real_type jump_reloc
= i
.reloc
[0];
7726 if (i
.tm
.opcode_modifier
.jumpbyte
)
7728 /* This is a loop or jecxz type instruction. */
7730 if (i
.prefix
[ADDR_PREFIX
] != 0)
7732 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
7735 /* Pentium4 branch hints. */
7736 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
7737 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
7739 FRAG_APPEND_1_CHAR (i
.prefix
[SEG_PREFIX
]);
7748 if (flag_code
== CODE_16BIT
)
7751 if (i
.prefix
[DATA_PREFIX
] != 0)
7753 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
7763 if (i
.prefix
[REX_PREFIX
] != 0)
7765 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
7769 /* BND prefixed jump. */
7770 if (i
.prefix
[BND_PREFIX
] != 0)
7772 FRAG_APPEND_1_CHAR (i
.prefix
[BND_PREFIX
]);
7776 if (i
.prefixes
!= 0 && !intel_syntax
)
7777 as_warn (_("skipping prefixes on this instruction"));
7779 p
= frag_more (i
.tm
.opcode_length
+ size
);
7780 switch (i
.tm
.opcode_length
)
7783 *p
++ = i
.tm
.base_opcode
>> 8;
7786 *p
++ = i
.tm
.base_opcode
;
7792 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7794 && jump_reloc
== NO_RELOC
7795 && need_plt32_p (i
.op
[0].disps
->X_add_symbol
))
7796 jump_reloc
= BFD_RELOC_X86_64_PLT32
;
7799 jump_reloc
= reloc (size
, 1, 1, jump_reloc
);
7801 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
7802 i
.op
[0].disps
, 1, jump_reloc
);
7804 /* All jumps handled here are signed, but don't use a signed limit
7805 check for 32 and 16 bit jumps as we want to allow wrap around at
7806 4G and 64k respectively. */
7808 fixP
->fx_signed
= 1;
7812 output_interseg_jump (void)
7820 if (flag_code
== CODE_16BIT
)
7824 if (i
.prefix
[DATA_PREFIX
] != 0)
7830 if (i
.prefix
[REX_PREFIX
] != 0)
7840 if (i
.prefixes
!= 0 && !intel_syntax
)
7841 as_warn (_("skipping prefixes on this instruction"));
7843 /* 1 opcode; 2 segment; offset */
7844 p
= frag_more (prefix
+ 1 + 2 + size
);
7846 if (i
.prefix
[DATA_PREFIX
] != 0)
7847 *p
++ = DATA_PREFIX_OPCODE
;
7849 if (i
.prefix
[REX_PREFIX
] != 0)
7850 *p
++ = i
.prefix
[REX_PREFIX
];
7852 *p
++ = i
.tm
.base_opcode
;
7853 if (i
.op
[1].imms
->X_op
== O_constant
)
7855 offsetT n
= i
.op
[1].imms
->X_add_number
;
7858 && !fits_in_unsigned_word (n
)
7859 && !fits_in_signed_word (n
))
7861 as_bad (_("16-bit jump out of range"));
7864 md_number_to_chars (p
, n
, size
);
7867 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
7868 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
7869 if (i
.op
[0].imms
->X_op
!= O_constant
)
7870 as_bad (_("can't handle non absolute segment in `%s'"),
7872 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
7875 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7880 asection
*seg
= now_seg
;
7881 subsegT subseg
= now_subseg
;
7883 unsigned int alignment
, align_size_1
;
7884 unsigned int isa_1_descsz
, feature_2_descsz
, descsz
;
7885 unsigned int isa_1_descsz_raw
, feature_2_descsz_raw
;
7886 unsigned int padding
;
7888 if (!IS_ELF
|| !x86_used_note
)
7891 x86_isa_1_used
|= GNU_PROPERTY_X86_UINT32_VALID
;
7892 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_X86
;
7894 /* The .note.gnu.property section layout:
7896 Field Length Contents
7899 n_descsz 4 The note descriptor size
7900 n_type 4 NT_GNU_PROPERTY_TYPE_0
7902 n_desc n_descsz The program property array
7906 /* Create the .note.gnu.property section. */
7907 sec
= subseg_new (NOTE_GNU_PROPERTY_SECTION_NAME
, 0);
7908 bfd_set_section_flags (stdoutput
, sec
,
7915 if (get_elf_backend_data (stdoutput
)->s
->elfclass
== ELFCLASS64
)
7926 bfd_set_section_alignment (stdoutput
, sec
, alignment
);
7927 elf_section_type (sec
) = SHT_NOTE
;
7929 /* GNU_PROPERTY_X86_ISA_1_USED: 4-byte type + 4-byte data size
7931 isa_1_descsz_raw
= 4 + 4 + 4;
7932 /* Align GNU_PROPERTY_X86_ISA_1_USED. */
7933 isa_1_descsz
= (isa_1_descsz_raw
+ align_size_1
) & ~align_size_1
;
7935 feature_2_descsz_raw
= isa_1_descsz
;
7936 /* GNU_PROPERTY_X86_FEATURE_2_USED: 4-byte type + 4-byte data size
7938 feature_2_descsz_raw
+= 4 + 4 + 4;
7939 /* Align GNU_PROPERTY_X86_FEATURE_2_USED. */
7940 feature_2_descsz
= ((feature_2_descsz_raw
+ align_size_1
)
7943 descsz
= feature_2_descsz
;
7944 /* Section size: n_namsz + n_descsz + n_type + n_name + n_descsz. */
7945 p
= frag_more (4 + 4 + 4 + 4 + descsz
);
7947 /* Write n_namsz. */
7948 md_number_to_chars (p
, (valueT
) 4, 4);
7950 /* Write n_descsz. */
7951 md_number_to_chars (p
+ 4, (valueT
) descsz
, 4);
7954 md_number_to_chars (p
+ 4 * 2, (valueT
) NT_GNU_PROPERTY_TYPE_0
, 4);
7957 memcpy (p
+ 4 * 3, "GNU", 4);
7959 /* Write 4-byte type. */
7960 md_number_to_chars (p
+ 4 * 4,
7961 (valueT
) GNU_PROPERTY_X86_ISA_1_USED
, 4);
7963 /* Write 4-byte data size. */
7964 md_number_to_chars (p
+ 4 * 5, (valueT
) 4, 4);
7966 /* Write 4-byte data. */
7967 md_number_to_chars (p
+ 4 * 6, (valueT
) x86_isa_1_used
, 4);
7969 /* Zero out paddings. */
7970 padding
= isa_1_descsz
- isa_1_descsz_raw
;
7972 memset (p
+ 4 * 7, 0, padding
);
7974 /* Write 4-byte type. */
7975 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 4,
7976 (valueT
) GNU_PROPERTY_X86_FEATURE_2_USED
, 4);
7978 /* Write 4-byte data size. */
7979 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 5, (valueT
) 4, 4);
7981 /* Write 4-byte data. */
7982 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 6,
7983 (valueT
) x86_feature_2_used
, 4);
7985 /* Zero out paddings. */
7986 padding
= feature_2_descsz
- feature_2_descsz_raw
;
7988 memset (p
+ isa_1_descsz
+ 4 * 7, 0, padding
);
7990 /* We probably can't restore the current segment, for there likely
7993 subseg_set (seg
, subseg
);
8000 fragS
*insn_start_frag
;
8001 offsetT insn_start_off
;
8003 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8004 if (IS_ELF
&& x86_used_note
)
8006 if (i
.tm
.cpu_flags
.bitfield
.cpucmov
)
8007 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_CMOV
;
8008 if (i
.tm
.cpu_flags
.bitfield
.cpusse
)
8009 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE
;
8010 if (i
.tm
.cpu_flags
.bitfield
.cpusse2
)
8011 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE2
;
8012 if (i
.tm
.cpu_flags
.bitfield
.cpusse3
)
8013 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE3
;
8014 if (i
.tm
.cpu_flags
.bitfield
.cpussse3
)
8015 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSSE3
;
8016 if (i
.tm
.cpu_flags
.bitfield
.cpusse4_1
)
8017 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE4_1
;
8018 if (i
.tm
.cpu_flags
.bitfield
.cpusse4_2
)
8019 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE4_2
;
8020 if (i
.tm
.cpu_flags
.bitfield
.cpuavx
)
8021 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX
;
8022 if (i
.tm
.cpu_flags
.bitfield
.cpuavx2
)
8023 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX2
;
8024 if (i
.tm
.cpu_flags
.bitfield
.cpufma
)
8025 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_FMA
;
8026 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512f
)
8027 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512F
;
8028 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512cd
)
8029 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512CD
;
8030 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512er
)
8031 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512ER
;
8032 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512pf
)
8033 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512PF
;
8034 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512vl
)
8035 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512VL
;
8036 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512dq
)
8037 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512DQ
;
8038 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512bw
)
8039 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512BW
;
8040 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_4fmaps
)
8041 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_4FMAPS
;
8042 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_4vnniw
)
8043 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_4VNNIW
;
8044 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_bitalg
)
8045 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_BITALG
;
8046 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512ifma
)
8047 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_IFMA
;
8048 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512vbmi
)
8049 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_VBMI
;
8050 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_vbmi2
)
8051 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_VBMI2
;
8052 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_vnni
)
8053 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_VNNI
;
8055 if (i
.tm
.cpu_flags
.bitfield
.cpu8087
8056 || i
.tm
.cpu_flags
.bitfield
.cpu287
8057 || i
.tm
.cpu_flags
.bitfield
.cpu387
8058 || i
.tm
.cpu_flags
.bitfield
.cpu687
8059 || i
.tm
.cpu_flags
.bitfield
.cpufisttp
)
8060 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_X87
;
8061 /* Don't set GNU_PROPERTY_X86_FEATURE_2_MMX for prefetchtXXX nor
8062 Xfence instructions. */
8063 if (i
.tm
.base_opcode
!= 0xf18
8064 && i
.tm
.base_opcode
!= 0xf0d
8065 && i
.tm
.base_opcode
!= 0xfae
8067 || i
.tm
.cpu_flags
.bitfield
.cpummx
8068 || i
.tm
.cpu_flags
.bitfield
.cpua3dnow
8069 || i
.tm
.cpu_flags
.bitfield
.cpua3dnowa
))
8070 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_MMX
;
8072 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XMM
;
8074 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_YMM
;
8076 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_ZMM
;
8077 if (i
.tm
.cpu_flags
.bitfield
.cpufxsr
)
8078 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_FXSR
;
8079 if (i
.tm
.cpu_flags
.bitfield
.cpuxsave
)
8080 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVE
;
8081 if (i
.tm
.cpu_flags
.bitfield
.cpuxsaveopt
)
8082 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVEOPT
;
8083 if (i
.tm
.cpu_flags
.bitfield
.cpuxsavec
)
8084 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVEC
;
8088 /* Tie dwarf2 debug info to the address at the start of the insn.
8089 We can't do this after the insn has been output as the current
8090 frag may have been closed off. eg. by frag_var. */
8091 dwarf2_emit_insn (0);
8093 insn_start_frag
= frag_now
;
8094 insn_start_off
= frag_now_fix ();
8097 if (i
.tm
.opcode_modifier
.jump
)
8099 else if (i
.tm
.opcode_modifier
.jumpbyte
8100 || i
.tm
.opcode_modifier
.jumpdword
)
8102 else if (i
.tm
.opcode_modifier
.jumpintersegment
)
8103 output_interseg_jump ();
8106 /* Output normal instructions here. */
8110 unsigned int prefix
;
8113 && i
.tm
.base_opcode
== 0xfae
8115 && i
.imm_operands
== 1
8116 && (i
.op
[0].imms
->X_add_number
== 0xe8
8117 || i
.op
[0].imms
->X_add_number
== 0xf0
8118 || i
.op
[0].imms
->X_add_number
== 0xf8))
8120 /* Encode lfence, mfence, and sfence as
8121 f0 83 04 24 00 lock addl $0x0, (%{re}sp). */
8122 offsetT val
= 0x240483f0ULL
;
8124 md_number_to_chars (p
, val
, 5);
8128 /* Some processors fail on LOCK prefix. This options makes
8129 assembler ignore LOCK prefix and serves as a workaround. */
8130 if (omit_lock_prefix
)
8132 if (i
.tm
.base_opcode
== LOCK_PREFIX_OPCODE
)
8134 i
.prefix
[LOCK_PREFIX
] = 0;
8137 /* Since the VEX/EVEX prefix contains the implicit prefix, we
8138 don't need the explicit prefix. */
8139 if (!i
.tm
.opcode_modifier
.vex
&& !i
.tm
.opcode_modifier
.evex
)
8141 switch (i
.tm
.opcode_length
)
8144 if (i
.tm
.base_opcode
& 0xff000000)
8146 prefix
= (i
.tm
.base_opcode
>> 24) & 0xff;
8147 add_prefix (prefix
);
8151 if ((i
.tm
.base_opcode
& 0xff0000) != 0)
8153 prefix
= (i
.tm
.base_opcode
>> 16) & 0xff;
8154 if (!i
.tm
.cpu_flags
.bitfield
.cpupadlock
8155 || prefix
!= REPE_PREFIX_OPCODE
8156 || (i
.prefix
[REP_PREFIX
] != REPE_PREFIX_OPCODE
))
8157 add_prefix (prefix
);
8163 /* Check for pseudo prefixes. */
8164 as_bad_where (insn_start_frag
->fr_file
,
8165 insn_start_frag
->fr_line
,
8166 _("pseudo prefix without instruction"));
8172 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
8173 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
8174 R_X86_64_GOTTPOFF relocation so that linker can safely
8175 perform IE->LE optimization. */
8176 if (x86_elf_abi
== X86_64_X32_ABI
8178 && i
.reloc
[0] == BFD_RELOC_X86_64_GOTTPOFF
8179 && i
.prefix
[REX_PREFIX
] == 0)
8180 add_prefix (REX_OPCODE
);
8183 /* The prefix bytes. */
8184 for (j
= ARRAY_SIZE (i
.prefix
), q
= i
.prefix
; j
> 0; j
--, q
++)
8186 FRAG_APPEND_1_CHAR (*q
);
8190 for (j
= 0, q
= i
.prefix
; j
< ARRAY_SIZE (i
.prefix
); j
++, q
++)
8195 /* REX byte is encoded in VEX prefix. */
8199 FRAG_APPEND_1_CHAR (*q
);
8202 /* There should be no other prefixes for instructions
8207 /* For EVEX instructions i.vrex should become 0 after
8208 build_evex_prefix. For VEX instructions upper 16 registers
8209 aren't available, so VREX should be 0. */
8212 /* Now the VEX prefix. */
8213 p
= frag_more (i
.vex
.length
);
8214 for (j
= 0; j
< i
.vex
.length
; j
++)
8215 p
[j
] = i
.vex
.bytes
[j
];
8218 /* Now the opcode; be careful about word order here! */
8219 if (i
.tm
.opcode_length
== 1)
8221 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
8225 switch (i
.tm
.opcode_length
)
8229 *p
++ = (i
.tm
.base_opcode
>> 24) & 0xff;
8230 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
8234 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
8244 /* Put out high byte first: can't use md_number_to_chars! */
8245 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
8246 *p
= i
.tm
.base_opcode
& 0xff;
8249 /* Now the modrm byte and sib byte (if present). */
8250 if (i
.tm
.opcode_modifier
.modrm
)
8252 FRAG_APPEND_1_CHAR ((i
.rm
.regmem
<< 0
8255 /* If i.rm.regmem == ESP (4)
8256 && i.rm.mode != (Register mode)
8258 ==> need second modrm byte. */
8259 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
8261 && !(i
.base_reg
&& i
.base_reg
->reg_type
.bitfield
.word
))
8262 FRAG_APPEND_1_CHAR ((i
.sib
.base
<< 0
8264 | i
.sib
.scale
<< 6));
8267 if (i
.disp_operands
)
8268 output_disp (insn_start_frag
, insn_start_off
);
8271 output_imm (insn_start_frag
, insn_start_off
);
8277 pi ("" /*line*/, &i
);
8279 #endif /* DEBUG386 */
8282 /* Return the size of the displacement operand N. */
8285 disp_size (unsigned int n
)
8289 if (i
.types
[n
].bitfield
.disp64
)
8291 else if (i
.types
[n
].bitfield
.disp8
)
8293 else if (i
.types
[n
].bitfield
.disp16
)
8298 /* Return the size of the immediate operand N. */
8301 imm_size (unsigned int n
)
8304 if (i
.types
[n
].bitfield
.imm64
)
8306 else if (i
.types
[n
].bitfield
.imm8
|| i
.types
[n
].bitfield
.imm8s
)
8308 else if (i
.types
[n
].bitfield
.imm16
)
8314 output_disp (fragS
*insn_start_frag
, offsetT insn_start_off
)
8319 for (n
= 0; n
< i
.operands
; n
++)
8321 if (operand_type_check (i
.types
[n
], disp
))
8323 if (i
.op
[n
].disps
->X_op
== O_constant
)
8325 int size
= disp_size (n
);
8326 offsetT val
= i
.op
[n
].disps
->X_add_number
;
8328 val
= offset_in_range (val
>> (size
== 1 ? i
.memshift
: 0),
8330 p
= frag_more (size
);
8331 md_number_to_chars (p
, val
, size
);
8335 enum bfd_reloc_code_real reloc_type
;
8336 int size
= disp_size (n
);
8337 int sign
= i
.types
[n
].bitfield
.disp32s
;
8338 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
8341 /* We can't have 8 bit displacement here. */
8342 gas_assert (!i
.types
[n
].bitfield
.disp8
);
8344 /* The PC relative address is computed relative
8345 to the instruction boundary, so in case immediate
8346 fields follows, we need to adjust the value. */
8347 if (pcrel
&& i
.imm_operands
)
8352 for (n1
= 0; n1
< i
.operands
; n1
++)
8353 if (operand_type_check (i
.types
[n1
], imm
))
8355 /* Only one immediate is allowed for PC
8356 relative address. */
8357 gas_assert (sz
== 0);
8359 i
.op
[n
].disps
->X_add_number
-= sz
;
8361 /* We should find the immediate. */
8362 gas_assert (sz
!= 0);
8365 p
= frag_more (size
);
8366 reloc_type
= reloc (size
, pcrel
, sign
, i
.reloc
[n
]);
8368 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
8369 && (((reloc_type
== BFD_RELOC_32
8370 || reloc_type
== BFD_RELOC_X86_64_32S
8371 || (reloc_type
== BFD_RELOC_64
8373 && (i
.op
[n
].disps
->X_op
== O_symbol
8374 || (i
.op
[n
].disps
->X_op
== O_add
8375 && ((symbol_get_value_expression
8376 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
8378 || reloc_type
== BFD_RELOC_32_PCREL
))
8382 if (insn_start_frag
== frag_now
)
8383 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
8388 add
= insn_start_frag
->fr_fix
- insn_start_off
;
8389 for (fr
= insn_start_frag
->fr_next
;
8390 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
8392 add
+= p
- frag_now
->fr_literal
;
8397 reloc_type
= BFD_RELOC_386_GOTPC
;
8398 i
.op
[n
].imms
->X_add_number
+= add
;
8400 else if (reloc_type
== BFD_RELOC_64
)
8401 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
8403 /* Don't do the adjustment for x86-64, as there
8404 the pcrel addressing is relative to the _next_
8405 insn, and that is taken care of in other code. */
8406 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
8408 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
8409 size
, i
.op
[n
].disps
, pcrel
,
8411 /* Check for "call/jmp *mem", "mov mem, %reg",
8412 "test %reg, mem" and "binop mem, %reg" where binop
8413 is one of adc, add, and, cmp, or, sbb, sub, xor
8414 instructions. Always generate R_386_GOT32X for
8415 "sym*GOT" operand in 32-bit mode. */
8416 if ((generate_relax_relocations
8419 && i
.rm
.regmem
== 5))
8421 || (i
.rm
.mode
== 0 && i
.rm
.regmem
== 5))
8422 && ((i
.operands
== 1
8423 && i
.tm
.base_opcode
== 0xff
8424 && (i
.rm
.reg
== 2 || i
.rm
.reg
== 4))
8426 && (i
.tm
.base_opcode
== 0x8b
8427 || i
.tm
.base_opcode
== 0x85
8428 || (i
.tm
.base_opcode
& 0xc7) == 0x03))))
8432 fixP
->fx_tcbit
= i
.rex
!= 0;
8434 && (i
.base_reg
->reg_num
== RegIP
))
8435 fixP
->fx_tcbit2
= 1;
8438 fixP
->fx_tcbit2
= 1;
8446 output_imm (fragS
*insn_start_frag
, offsetT insn_start_off
)
8451 for (n
= 0; n
< i
.operands
; n
++)
8453 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
8454 if (i
.rounding
&& (int) n
== i
.rounding
->operand
)
8457 if (operand_type_check (i
.types
[n
], imm
))
8459 if (i
.op
[n
].imms
->X_op
== O_constant
)
8461 int size
= imm_size (n
);
8464 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
8466 p
= frag_more (size
);
8467 md_number_to_chars (p
, val
, size
);
8471 /* Not absolute_section.
8472 Need a 32-bit fixup (don't support 8bit
8473 non-absolute imms). Try to support other
8475 enum bfd_reloc_code_real reloc_type
;
8476 int size
= imm_size (n
);
8479 if (i
.types
[n
].bitfield
.imm32s
8480 && (i
.suffix
== QWORD_MNEM_SUFFIX
8481 || (!i
.suffix
&& i
.tm
.opcode_modifier
.no_lsuf
)))
8486 p
= frag_more (size
);
8487 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
8489 /* This is tough to explain. We end up with this one if we
8490 * have operands that look like
8491 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
8492 * obtain the absolute address of the GOT, and it is strongly
8493 * preferable from a performance point of view to avoid using
8494 * a runtime relocation for this. The actual sequence of
8495 * instructions often look something like:
8500 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
8502 * The call and pop essentially return the absolute address
8503 * of the label .L66 and store it in %ebx. The linker itself
8504 * will ultimately change the first operand of the addl so
8505 * that %ebx points to the GOT, but to keep things simple, the
8506 * .o file must have this operand set so that it generates not
8507 * the absolute address of .L66, but the absolute address of
8508 * itself. This allows the linker itself simply treat a GOTPC
8509 * relocation as asking for a pcrel offset to the GOT to be
8510 * added in, and the addend of the relocation is stored in the
8511 * operand field for the instruction itself.
8513 * Our job here is to fix the operand so that it would add
8514 * the correct offset so that %ebx would point to itself. The
8515 * thing that is tricky is that .-.L66 will point to the
8516 * beginning of the instruction, so we need to further modify
8517 * the operand so that it will point to itself. There are
8518 * other cases where you have something like:
8520 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
8522 * and here no correction would be required. Internally in
8523 * the assembler we treat operands of this form as not being
8524 * pcrel since the '.' is explicitly mentioned, and I wonder
8525 * whether it would simplify matters to do it this way. Who
8526 * knows. In earlier versions of the PIC patches, the
8527 * pcrel_adjust field was used to store the correction, but
8528 * since the expression is not pcrel, I felt it would be
8529 * confusing to do it this way. */
8531 if ((reloc_type
== BFD_RELOC_32
8532 || reloc_type
== BFD_RELOC_X86_64_32S
8533 || reloc_type
== BFD_RELOC_64
)
8535 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
8536 && (i
.op
[n
].imms
->X_op
== O_symbol
8537 || (i
.op
[n
].imms
->X_op
== O_add
8538 && ((symbol_get_value_expression
8539 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
8544 if (insn_start_frag
== frag_now
)
8545 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
8550 add
= insn_start_frag
->fr_fix
- insn_start_off
;
8551 for (fr
= insn_start_frag
->fr_next
;
8552 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
8554 add
+= p
- frag_now
->fr_literal
;
8558 reloc_type
= BFD_RELOC_386_GOTPC
;
8560 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
8562 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
8563 i
.op
[n
].imms
->X_add_number
+= add
;
8565 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
8566 i
.op
[n
].imms
, 0, reloc_type
);
8572 /* x86_cons_fix_new is called via the expression parsing code when a
8573 reloc is needed. We use this hook to get the correct .got reloc. */
8574 static int cons_sign
= -1;
8577 x86_cons_fix_new (fragS
*frag
, unsigned int off
, unsigned int len
,
8578 expressionS
*exp
, bfd_reloc_code_real_type r
)
8580 r
= reloc (len
, 0, cons_sign
, r
);
8583 if (exp
->X_op
== O_secrel
)
8585 exp
->X_op
= O_symbol
;
8586 r
= BFD_RELOC_32_SECREL
;
8590 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
8593 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
8594 purpose of the `.dc.a' internal pseudo-op. */
8597 x86_address_bytes (void)
8599 if ((stdoutput
->arch_info
->mach
& bfd_mach_x64_32
))
8601 return stdoutput
->arch_info
->bits_per_address
/ 8;
8604 #if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
8606 # define lex_got(reloc, adjust, types) NULL
8608 /* Parse operands of the form
8609 <symbol>@GOTOFF+<nnn>
8610 and similar .plt or .got references.
8612 If we find one, set up the correct relocation in RELOC and copy the
8613 input string, minus the `@GOTOFF' into a malloc'd buffer for
8614 parsing by the calling routine. Return this buffer, and if ADJUST
8615 is non-null set it to the length of the string we removed from the
8616 input line. Otherwise return NULL. */
8618 lex_got (enum bfd_reloc_code_real
*rel
,
8620 i386_operand_type
*types
)
8622 /* Some of the relocations depend on the size of what field is to
8623 be relocated. But in our callers i386_immediate and i386_displacement
8624 we don't yet know the operand size (this will be set by insn
8625 matching). Hence we record the word32 relocation here,
8626 and adjust the reloc according to the real size in reloc(). */
8627 static const struct {
8630 const enum bfd_reloc_code_real rel
[2];
8631 const i386_operand_type types64
;
8633 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8634 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32
,
8636 OPERAND_TYPE_IMM32_64
},
8638 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real
,
8639 BFD_RELOC_X86_64_PLTOFF64
},
8640 OPERAND_TYPE_IMM64
},
8641 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32
,
8642 BFD_RELOC_X86_64_PLT32
},
8643 OPERAND_TYPE_IMM32_32S_DISP32
},
8644 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real
,
8645 BFD_RELOC_X86_64_GOTPLT64
},
8646 OPERAND_TYPE_IMM64_DISP64
},
8647 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF
,
8648 BFD_RELOC_X86_64_GOTOFF64
},
8649 OPERAND_TYPE_IMM64_DISP64
},
8650 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real
,
8651 BFD_RELOC_X86_64_GOTPCREL
},
8652 OPERAND_TYPE_IMM32_32S_DISP32
},
8653 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD
,
8654 BFD_RELOC_X86_64_TLSGD
},
8655 OPERAND_TYPE_IMM32_32S_DISP32
},
8656 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM
,
8657 _dummy_first_bfd_reloc_code_real
},
8658 OPERAND_TYPE_NONE
},
8659 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real
,
8660 BFD_RELOC_X86_64_TLSLD
},
8661 OPERAND_TYPE_IMM32_32S_DISP32
},
8662 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32
,
8663 BFD_RELOC_X86_64_GOTTPOFF
},
8664 OPERAND_TYPE_IMM32_32S_DISP32
},
8665 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32
,
8666 BFD_RELOC_X86_64_TPOFF32
},
8667 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
8668 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE
,
8669 _dummy_first_bfd_reloc_code_real
},
8670 OPERAND_TYPE_NONE
},
8671 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32
,
8672 BFD_RELOC_X86_64_DTPOFF32
},
8673 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
8674 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE
,
8675 _dummy_first_bfd_reloc_code_real
},
8676 OPERAND_TYPE_NONE
},
8677 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE
,
8678 _dummy_first_bfd_reloc_code_real
},
8679 OPERAND_TYPE_NONE
},
8680 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32
,
8681 BFD_RELOC_X86_64_GOT32
},
8682 OPERAND_TYPE_IMM32_32S_64_DISP32
},
8683 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC
,
8684 BFD_RELOC_X86_64_GOTPC32_TLSDESC
},
8685 OPERAND_TYPE_IMM32_32S_DISP32
},
8686 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL
,
8687 BFD_RELOC_X86_64_TLSDESC_CALL
},
8688 OPERAND_TYPE_IMM32_32S_DISP32
},
8693 #if defined (OBJ_MAYBE_ELF)
8698 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
8699 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
8702 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
8704 int len
= gotrel
[j
].len
;
8705 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
8707 if (gotrel
[j
].rel
[object_64bit
] != 0)
8710 char *tmpbuf
, *past_reloc
;
8712 *rel
= gotrel
[j
].rel
[object_64bit
];
8716 if (flag_code
!= CODE_64BIT
)
8718 types
->bitfield
.imm32
= 1;
8719 types
->bitfield
.disp32
= 1;
8722 *types
= gotrel
[j
].types64
;
8725 if (j
!= 0 && GOT_symbol
== NULL
)
8726 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
8728 /* The length of the first part of our input line. */
8729 first
= cp
- input_line_pointer
;
8731 /* The second part goes from after the reloc token until
8732 (and including) an end_of_line char or comma. */
8733 past_reloc
= cp
+ 1 + len
;
8735 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
8737 second
= cp
+ 1 - past_reloc
;
8739 /* Allocate and copy string. The trailing NUL shouldn't
8740 be necessary, but be safe. */
8741 tmpbuf
= XNEWVEC (char, first
+ second
+ 2);
8742 memcpy (tmpbuf
, input_line_pointer
, first
);
8743 if (second
!= 0 && *past_reloc
!= ' ')
8744 /* Replace the relocation token with ' ', so that
8745 errors like foo@GOTOFF1 will be detected. */
8746 tmpbuf
[first
++] = ' ';
8748 /* Increment length by 1 if the relocation token is
8753 memcpy (tmpbuf
+ first
, past_reloc
, second
);
8754 tmpbuf
[first
+ second
] = '\0';
8758 as_bad (_("@%s reloc is not supported with %d-bit output format"),
8759 gotrel
[j
].str
, 1 << (5 + object_64bit
));
8764 /* Might be a symbol version string. Don't as_bad here. */
8773 /* Parse operands of the form
8774 <symbol>@SECREL32+<nnn>
8776 If we find one, set up the correct relocation in RELOC and copy the
8777 input string, minus the `@SECREL32' into a malloc'd buffer for
8778 parsing by the calling routine. Return this buffer, and if ADJUST
8779 is non-null set it to the length of the string we removed from the
8780 input line. Otherwise return NULL.
8782 This function is copied from the ELF version above adjusted for PE targets. */
8785 lex_got (enum bfd_reloc_code_real
*rel ATTRIBUTE_UNUSED
,
8786 int *adjust ATTRIBUTE_UNUSED
,
8787 i386_operand_type
*types
)
8793 const enum bfd_reloc_code_real rel
[2];
8794 const i386_operand_type types64
;
8798 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL
,
8799 BFD_RELOC_32_SECREL
},
8800 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
8806 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
8807 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
8810 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
8812 int len
= gotrel
[j
].len
;
8814 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
8816 if (gotrel
[j
].rel
[object_64bit
] != 0)
8819 char *tmpbuf
, *past_reloc
;
8821 *rel
= gotrel
[j
].rel
[object_64bit
];
8827 if (flag_code
!= CODE_64BIT
)
8829 types
->bitfield
.imm32
= 1;
8830 types
->bitfield
.disp32
= 1;
8833 *types
= gotrel
[j
].types64
;
8836 /* The length of the first part of our input line. */
8837 first
= cp
- input_line_pointer
;
8839 /* The second part goes from after the reloc token until
8840 (and including) an end_of_line char or comma. */
8841 past_reloc
= cp
+ 1 + len
;
8843 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
8845 second
= cp
+ 1 - past_reloc
;
8847 /* Allocate and copy string. The trailing NUL shouldn't
8848 be necessary, but be safe. */
8849 tmpbuf
= XNEWVEC (char, first
+ second
+ 2);
8850 memcpy (tmpbuf
, input_line_pointer
, first
);
8851 if (second
!= 0 && *past_reloc
!= ' ')
8852 /* Replace the relocation token with ' ', so that
8853 errors like foo@SECLREL321 will be detected. */
8854 tmpbuf
[first
++] = ' ';
8855 memcpy (tmpbuf
+ first
, past_reloc
, second
);
8856 tmpbuf
[first
+ second
] = '\0';
8860 as_bad (_("@%s reloc is not supported with %d-bit output format"),
8861 gotrel
[j
].str
, 1 << (5 + object_64bit
));
8866 /* Might be a symbol version string. Don't as_bad here. */
8872 bfd_reloc_code_real_type
8873 x86_cons (expressionS
*exp
, int size
)
8875 bfd_reloc_code_real_type got_reloc
= NO_RELOC
;
8877 intel_syntax
= -intel_syntax
;
8880 if (size
== 4 || (object_64bit
&& size
== 8))
8882 /* Handle @GOTOFF and the like in an expression. */
8884 char *gotfree_input_line
;
8887 save
= input_line_pointer
;
8888 gotfree_input_line
= lex_got (&got_reloc
, &adjust
, NULL
);
8889 if (gotfree_input_line
)
8890 input_line_pointer
= gotfree_input_line
;
8894 if (gotfree_input_line
)
8896 /* expression () has merrily parsed up to the end of line,
8897 or a comma - in the wrong buffer. Transfer how far
8898 input_line_pointer has moved to the right buffer. */
8899 input_line_pointer
= (save
8900 + (input_line_pointer
- gotfree_input_line
)
8902 free (gotfree_input_line
);
8903 if (exp
->X_op
== O_constant
8904 || exp
->X_op
== O_absent
8905 || exp
->X_op
== O_illegal
8906 || exp
->X_op
== O_register
8907 || exp
->X_op
== O_big
)
8909 char c
= *input_line_pointer
;
8910 *input_line_pointer
= 0;
8911 as_bad (_("missing or invalid expression `%s'"), save
);
8912 *input_line_pointer
= c
;
8919 intel_syntax
= -intel_syntax
;
8922 i386_intel_simplify (exp
);
8928 signed_cons (int size
)
8930 if (flag_code
== CODE_64BIT
)
8938 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
8945 if (exp
.X_op
== O_symbol
)
8946 exp
.X_op
= O_secrel
;
8948 emit_expr (&exp
, 4);
8950 while (*input_line_pointer
++ == ',');
8952 input_line_pointer
--;
8953 demand_empty_rest_of_line ();
8957 /* Handle Vector operations. */
8960 check_VecOperations (char *op_string
, char *op_end
)
8962 const reg_entry
*mask
;
8967 && (op_end
== NULL
|| op_string
< op_end
))
8970 if (*op_string
== '{')
8974 /* Check broadcasts. */
8975 if (strncmp (op_string
, "1to", 3) == 0)
8980 goto duplicated_vec_op
;
8983 if (*op_string
== '8')
8985 else if (*op_string
== '4')
8987 else if (*op_string
== '2')
8989 else if (*op_string
== '1'
8990 && *(op_string
+1) == '6')
8997 as_bad (_("Unsupported broadcast: `%s'"), saved
);
9002 broadcast_op
.type
= bcst_type
;
9003 broadcast_op
.operand
= this_operand
;
9004 broadcast_op
.bytes
= 0;
9005 i
.broadcast
= &broadcast_op
;
9007 /* Check masking operation. */
9008 else if ((mask
= parse_register (op_string
, &end_op
)) != NULL
)
9010 /* k0 can't be used for write mask. */
9011 if (!mask
->reg_type
.bitfield
.regmask
|| mask
->reg_num
== 0)
9013 as_bad (_("`%s%s' can't be used for write mask"),
9014 register_prefix
, mask
->reg_name
);
9020 mask_op
.mask
= mask
;
9021 mask_op
.zeroing
= 0;
9022 mask_op
.operand
= this_operand
;
9028 goto duplicated_vec_op
;
9030 i
.mask
->mask
= mask
;
9032 /* Only "{z}" is allowed here. No need to check
9033 zeroing mask explicitly. */
9034 if (i
.mask
->operand
!= this_operand
)
9036 as_bad (_("invalid write mask `%s'"), saved
);
9043 /* Check zeroing-flag for masking operation. */
9044 else if (*op_string
== 'z')
9048 mask_op
.mask
= NULL
;
9049 mask_op
.zeroing
= 1;
9050 mask_op
.operand
= this_operand
;
9055 if (i
.mask
->zeroing
)
9058 as_bad (_("duplicated `%s'"), saved
);
9062 i
.mask
->zeroing
= 1;
9064 /* Only "{%k}" is allowed here. No need to check mask
9065 register explicitly. */
9066 if (i
.mask
->operand
!= this_operand
)
9068 as_bad (_("invalid zeroing-masking `%s'"),
9077 goto unknown_vec_op
;
9079 if (*op_string
!= '}')
9081 as_bad (_("missing `}' in `%s'"), saved
);
9086 /* Strip whitespace since the addition of pseudo prefixes
9087 changed how the scrubber treats '{'. */
9088 if (is_space_char (*op_string
))
9094 /* We don't know this one. */
9095 as_bad (_("unknown vector operation: `%s'"), saved
);
9099 if (i
.mask
&& i
.mask
->zeroing
&& !i
.mask
->mask
)
9101 as_bad (_("zeroing-masking only allowed with write mask"));
9109 i386_immediate (char *imm_start
)
9111 char *save_input_line_pointer
;
9112 char *gotfree_input_line
;
9115 i386_operand_type types
;
9117 operand_type_set (&types
, ~0);
9119 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
9121 as_bad (_("at most %d immediate operands are allowed"),
9122 MAX_IMMEDIATE_OPERANDS
);
9126 exp
= &im_expressions
[i
.imm_operands
++];
9127 i
.op
[this_operand
].imms
= exp
;
9129 if (is_space_char (*imm_start
))
9132 save_input_line_pointer
= input_line_pointer
;
9133 input_line_pointer
= imm_start
;
9135 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
9136 if (gotfree_input_line
)
9137 input_line_pointer
= gotfree_input_line
;
9139 exp_seg
= expression (exp
);
9143 /* Handle vector operations. */
9144 if (*input_line_pointer
== '{')
9146 input_line_pointer
= check_VecOperations (input_line_pointer
,
9148 if (input_line_pointer
== NULL
)
9152 if (*input_line_pointer
)
9153 as_bad (_("junk `%s' after expression"), input_line_pointer
);
9155 input_line_pointer
= save_input_line_pointer
;
9156 if (gotfree_input_line
)
9158 free (gotfree_input_line
);
9160 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
9161 exp
->X_op
= O_illegal
;
9164 return i386_finalize_immediate (exp_seg
, exp
, types
, imm_start
);
9168 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
9169 i386_operand_type types
, const char *imm_start
)
9171 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_illegal
|| exp
->X_op
== O_big
)
9174 as_bad (_("missing or invalid immediate expression `%s'"),
9178 else if (exp
->X_op
== O_constant
)
9180 /* Size it properly later. */
9181 i
.types
[this_operand
].bitfield
.imm64
= 1;
9182 /* If not 64bit, sign extend val. */
9183 if (flag_code
!= CODE_64BIT
9184 && (exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
9186 = (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
9188 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
9189 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
9190 && exp_seg
!= absolute_section
9191 && exp_seg
!= text_section
9192 && exp_seg
!= data_section
9193 && exp_seg
!= bss_section
9194 && exp_seg
!= undefined_section
9195 && !bfd_is_com_section (exp_seg
))
9197 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
9201 else if (!intel_syntax
&& exp_seg
== reg_section
)
9204 as_bad (_("illegal immediate register operand %s"), imm_start
);
9209 /* This is an address. The size of the address will be
9210 determined later, depending on destination register,
9211 suffix, or the default for the section. */
9212 i
.types
[this_operand
].bitfield
.imm8
= 1;
9213 i
.types
[this_operand
].bitfield
.imm16
= 1;
9214 i
.types
[this_operand
].bitfield
.imm32
= 1;
9215 i
.types
[this_operand
].bitfield
.imm32s
= 1;
9216 i
.types
[this_operand
].bitfield
.imm64
= 1;
9217 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
9225 i386_scale (char *scale
)
9228 char *save
= input_line_pointer
;
9230 input_line_pointer
= scale
;
9231 val
= get_absolute_expression ();
9236 i
.log2_scale_factor
= 0;
9239 i
.log2_scale_factor
= 1;
9242 i
.log2_scale_factor
= 2;
9245 i
.log2_scale_factor
= 3;
9249 char sep
= *input_line_pointer
;
9251 *input_line_pointer
= '\0';
9252 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
9254 *input_line_pointer
= sep
;
9255 input_line_pointer
= save
;
9259 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
9261 as_warn (_("scale factor of %d without an index register"),
9262 1 << i
.log2_scale_factor
);
9263 i
.log2_scale_factor
= 0;
9265 scale
= input_line_pointer
;
9266 input_line_pointer
= save
;
9271 i386_displacement (char *disp_start
, char *disp_end
)
9275 char *save_input_line_pointer
;
9276 char *gotfree_input_line
;
9278 i386_operand_type bigdisp
, types
= anydisp
;
9281 if (i
.disp_operands
== MAX_MEMORY_OPERANDS
)
9283 as_bad (_("at most %d displacement operands are allowed"),
9284 MAX_MEMORY_OPERANDS
);
9288 operand_type_set (&bigdisp
, 0);
9289 if ((i
.types
[this_operand
].bitfield
.jumpabsolute
)
9290 || (!current_templates
->start
->opcode_modifier
.jump
9291 && !current_templates
->start
->opcode_modifier
.jumpdword
))
9293 bigdisp
.bitfield
.disp32
= 1;
9294 override
= (i
.prefix
[ADDR_PREFIX
] != 0);
9295 if (flag_code
== CODE_64BIT
)
9299 bigdisp
.bitfield
.disp32s
= 1;
9300 bigdisp
.bitfield
.disp64
= 1;
9303 else if ((flag_code
== CODE_16BIT
) ^ override
)
9305 bigdisp
.bitfield
.disp32
= 0;
9306 bigdisp
.bitfield
.disp16
= 1;
9311 /* For PC-relative branches, the width of the displacement
9312 is dependent upon data size, not address size. */
9313 override
= (i
.prefix
[DATA_PREFIX
] != 0);
9314 if (flag_code
== CODE_64BIT
)
9316 if (override
|| i
.suffix
== WORD_MNEM_SUFFIX
)
9317 bigdisp
.bitfield
.disp16
= 1;
9320 bigdisp
.bitfield
.disp32
= 1;
9321 bigdisp
.bitfield
.disp32s
= 1;
9327 override
= (i
.suffix
== (flag_code
!= CODE_16BIT
9329 : LONG_MNEM_SUFFIX
));
9330 bigdisp
.bitfield
.disp32
= 1;
9331 if ((flag_code
== CODE_16BIT
) ^ override
)
9333 bigdisp
.bitfield
.disp32
= 0;
9334 bigdisp
.bitfield
.disp16
= 1;
9338 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
9341 exp
= &disp_expressions
[i
.disp_operands
];
9342 i
.op
[this_operand
].disps
= exp
;
9344 save_input_line_pointer
= input_line_pointer
;
9345 input_line_pointer
= disp_start
;
9346 END_STRING_AND_SAVE (disp_end
);
9348 #ifndef GCC_ASM_O_HACK
9349 #define GCC_ASM_O_HACK 0
9352 END_STRING_AND_SAVE (disp_end
+ 1);
9353 if (i
.types
[this_operand
].bitfield
.baseIndex
9354 && displacement_string_end
[-1] == '+')
9356 /* This hack is to avoid a warning when using the "o"
9357 constraint within gcc asm statements.
9360 #define _set_tssldt_desc(n,addr,limit,type) \
9361 __asm__ __volatile__ ( \
9363 "movw %w1,2+%0\n\t" \
9365 "movb %b1,4+%0\n\t" \
9366 "movb %4,5+%0\n\t" \
9367 "movb $0,6+%0\n\t" \
9368 "movb %h1,7+%0\n\t" \
9370 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
9372 This works great except that the output assembler ends
9373 up looking a bit weird if it turns out that there is
9374 no offset. You end up producing code that looks like:
9387 So here we provide the missing zero. */
9389 *displacement_string_end
= '0';
9392 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
9393 if (gotfree_input_line
)
9394 input_line_pointer
= gotfree_input_line
;
9396 exp_seg
= expression (exp
);
9399 if (*input_line_pointer
)
9400 as_bad (_("junk `%s' after expression"), input_line_pointer
);
9402 RESTORE_END_STRING (disp_end
+ 1);
9404 input_line_pointer
= save_input_line_pointer
;
9405 if (gotfree_input_line
)
9407 free (gotfree_input_line
);
9409 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
9410 exp
->X_op
= O_illegal
;
9413 ret
= i386_finalize_displacement (exp_seg
, exp
, types
, disp_start
);
9415 RESTORE_END_STRING (disp_end
);
9421 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
9422 i386_operand_type types
, const char *disp_start
)
9424 i386_operand_type bigdisp
;
9427 /* We do this to make sure that the section symbol is in
9428 the symbol table. We will ultimately change the relocation
9429 to be relative to the beginning of the section. */
9430 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
9431 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
9432 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
9434 if (exp
->X_op
!= O_symbol
)
9437 if (S_IS_LOCAL (exp
->X_add_symbol
)
9438 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
9439 && S_GET_SEGMENT (exp
->X_add_symbol
) != expr_section
)
9440 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
9441 exp
->X_op
= O_subtract
;
9442 exp
->X_op_symbol
= GOT_symbol
;
9443 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
9444 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
9445 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
9446 i
.reloc
[this_operand
] = BFD_RELOC_64
;
9448 i
.reloc
[this_operand
] = BFD_RELOC_32
;
9451 else if (exp
->X_op
== O_absent
9452 || exp
->X_op
== O_illegal
9453 || exp
->X_op
== O_big
)
9456 as_bad (_("missing or invalid displacement expression `%s'"),
9461 else if (flag_code
== CODE_64BIT
9462 && !i
.prefix
[ADDR_PREFIX
]
9463 && exp
->X_op
== O_constant
)
9465 /* Since displacement is signed extended to 64bit, don't allow
9466 disp32 and turn off disp32s if they are out of range. */
9467 i
.types
[this_operand
].bitfield
.disp32
= 0;
9468 if (!fits_in_signed_long (exp
->X_add_number
))
9470 i
.types
[this_operand
].bitfield
.disp32s
= 0;
9471 if (i
.types
[this_operand
].bitfield
.baseindex
)
9473 as_bad (_("0x%lx out range of signed 32bit displacement"),
9474 (long) exp
->X_add_number
);
9480 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
9481 else if (exp
->X_op
!= O_constant
9482 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
9483 && exp_seg
!= absolute_section
9484 && exp_seg
!= text_section
9485 && exp_seg
!= data_section
9486 && exp_seg
!= bss_section
9487 && exp_seg
!= undefined_section
9488 && !bfd_is_com_section (exp_seg
))
9490 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
9495 /* Check if this is a displacement only operand. */
9496 bigdisp
= i
.types
[this_operand
];
9497 bigdisp
.bitfield
.disp8
= 0;
9498 bigdisp
.bitfield
.disp16
= 0;
9499 bigdisp
.bitfield
.disp32
= 0;
9500 bigdisp
.bitfield
.disp32s
= 0;
9501 bigdisp
.bitfield
.disp64
= 0;
9502 if (operand_type_all_zero (&bigdisp
))
9503 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
9509 /* Return the active addressing mode, taking address override and
9510 registers forming the address into consideration. Update the
9511 address override prefix if necessary. */
9513 static enum flag_code
9514 i386_addressing_mode (void)
9516 enum flag_code addr_mode
;
9518 if (i
.prefix
[ADDR_PREFIX
])
9519 addr_mode
= flag_code
== CODE_32BIT
? CODE_16BIT
: CODE_32BIT
;
9522 addr_mode
= flag_code
;
9524 #if INFER_ADDR_PREFIX
9525 if (i
.mem_operands
== 0)
9527 /* Infer address prefix from the first memory operand. */
9528 const reg_entry
*addr_reg
= i
.base_reg
;
9530 if (addr_reg
== NULL
)
9531 addr_reg
= i
.index_reg
;
9535 if (addr_reg
->reg_type
.bitfield
.dword
)
9536 addr_mode
= CODE_32BIT
;
9537 else if (flag_code
!= CODE_64BIT
9538 && addr_reg
->reg_type
.bitfield
.word
)
9539 addr_mode
= CODE_16BIT
;
9541 if (addr_mode
!= flag_code
)
9543 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
9545 /* Change the size of any displacement too. At most one
9546 of Disp16 or Disp32 is set.
9547 FIXME. There doesn't seem to be any real need for
9548 separate Disp16 and Disp32 flags. The same goes for
9549 Imm16 and Imm32. Removing them would probably clean
9550 up the code quite a lot. */
9551 if (flag_code
!= CODE_64BIT
9552 && (i
.types
[this_operand
].bitfield
.disp16
9553 || i
.types
[this_operand
].bitfield
.disp32
))
9554 i
.types
[this_operand
]
9555 = operand_type_xor (i
.types
[this_operand
], disp16_32
);
9565 /* Make sure the memory operand we've been dealt is valid.
9566 Return 1 on success, 0 on a failure. */
9569 i386_index_check (const char *operand_string
)
9571 const char *kind
= "base/index";
9572 enum flag_code addr_mode
= i386_addressing_mode ();
9574 if (current_templates
->start
->opcode_modifier
.isstring
9575 && !current_templates
->start
->opcode_modifier
.immext
9576 && (current_templates
->end
[-1].opcode_modifier
.isstring
9579 /* Memory operands of string insns are special in that they only allow
9580 a single register (rDI, rSI, or rBX) as their memory address. */
9581 const reg_entry
*expected_reg
;
9582 static const char *di_si
[][2] =
9588 static const char *bx
[] = { "ebx", "bx", "rbx" };
9590 kind
= "string address";
9592 if (current_templates
->start
->opcode_modifier
.repprefixok
)
9594 i386_operand_type type
= current_templates
->end
[-1].operand_types
[0];
9596 if (!type
.bitfield
.baseindex
9597 || ((!i
.mem_operands
!= !intel_syntax
)
9598 && current_templates
->end
[-1].operand_types
[1]
9599 .bitfield
.baseindex
))
9600 type
= current_templates
->end
[-1].operand_types
[1];
9601 expected_reg
= hash_find (reg_hash
,
9602 di_si
[addr_mode
][type
.bitfield
.esseg
]);
9606 expected_reg
= hash_find (reg_hash
, bx
[addr_mode
]);
9608 if (i
.base_reg
!= expected_reg
9610 || operand_type_check (i
.types
[this_operand
], disp
))
9612 /* The second memory operand must have the same size as
9616 && !((addr_mode
== CODE_64BIT
9617 && i
.base_reg
->reg_type
.bitfield
.qword
)
9618 || (addr_mode
== CODE_32BIT
9619 ? i
.base_reg
->reg_type
.bitfield
.dword
9620 : i
.base_reg
->reg_type
.bitfield
.word
)))
9623 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
9625 intel_syntax
? '[' : '(',
9627 expected_reg
->reg_name
,
9628 intel_syntax
? ']' : ')');
9635 as_bad (_("`%s' is not a valid %s expression"),
9636 operand_string
, kind
);
9641 if (addr_mode
!= CODE_16BIT
)
9643 /* 32-bit/64-bit checks. */
9645 && ((addr_mode
== CODE_64BIT
9646 ? !i
.base_reg
->reg_type
.bitfield
.qword
9647 : !i
.base_reg
->reg_type
.bitfield
.dword
)
9648 || (i
.index_reg
&& i
.base_reg
->reg_num
== RegIP
)
9649 || i
.base_reg
->reg_num
== RegIZ
))
9651 && !i
.index_reg
->reg_type
.bitfield
.xmmword
9652 && !i
.index_reg
->reg_type
.bitfield
.ymmword
9653 && !i
.index_reg
->reg_type
.bitfield
.zmmword
9654 && ((addr_mode
== CODE_64BIT
9655 ? !i
.index_reg
->reg_type
.bitfield
.qword
9656 : !i
.index_reg
->reg_type
.bitfield
.dword
)
9657 || !i
.index_reg
->reg_type
.bitfield
.baseindex
)))
9660 /* bndmk, bndldx, and bndstx have special restrictions. */
9661 if (current_templates
->start
->base_opcode
== 0xf30f1b
9662 || (current_templates
->start
->base_opcode
& ~1) == 0x0f1a)
9664 /* They cannot use RIP-relative addressing. */
9665 if (i
.base_reg
&& i
.base_reg
->reg_num
== RegIP
)
9667 as_bad (_("`%s' cannot be used here"), operand_string
);
9671 /* bndldx and bndstx ignore their scale factor. */
9672 if (current_templates
->start
->base_opcode
!= 0xf30f1b
9673 && i
.log2_scale_factor
)
9674 as_warn (_("register scaling is being ignored here"));
9679 /* 16-bit checks. */
9681 && (!i
.base_reg
->reg_type
.bitfield
.word
9682 || !i
.base_reg
->reg_type
.bitfield
.baseindex
))
9684 && (!i
.index_reg
->reg_type
.bitfield
.word
9685 || !i
.index_reg
->reg_type
.bitfield
.baseindex
9687 && i
.base_reg
->reg_num
< 6
9688 && i
.index_reg
->reg_num
>= 6
9689 && i
.log2_scale_factor
== 0))))
9696 /* Handle vector immediates. */
9699 RC_SAE_immediate (const char *imm_start
)
9701 unsigned int match_found
, j
;
9702 const char *pstr
= imm_start
;
9710 for (j
= 0; j
< ARRAY_SIZE (RC_NamesTable
); j
++)
9712 if (!strncmp (pstr
, RC_NamesTable
[j
].name
, RC_NamesTable
[j
].len
))
9716 rc_op
.type
= RC_NamesTable
[j
].type
;
9717 rc_op
.operand
= this_operand
;
9718 i
.rounding
= &rc_op
;
9722 as_bad (_("duplicated `%s'"), imm_start
);
9725 pstr
+= RC_NamesTable
[j
].len
;
9735 as_bad (_("Missing '}': '%s'"), imm_start
);
9738 /* RC/SAE immediate string should contain nothing more. */;
9741 as_bad (_("Junk after '}': '%s'"), imm_start
);
9745 exp
= &im_expressions
[i
.imm_operands
++];
9746 i
.op
[this_operand
].imms
= exp
;
9748 exp
->X_op
= O_constant
;
9749 exp
->X_add_number
= 0;
9750 exp
->X_add_symbol
= (symbolS
*) 0;
9751 exp
->X_op_symbol
= (symbolS
*) 0;
9753 i
.types
[this_operand
].bitfield
.imm8
= 1;
9757 /* Only string instructions can have a second memory operand, so
9758 reduce current_templates to just those if it contains any. */
9760 maybe_adjust_templates (void)
9762 const insn_template
*t
;
9764 gas_assert (i
.mem_operands
== 1);
9766 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
9767 if (t
->opcode_modifier
.isstring
)
9770 if (t
< current_templates
->end
)
9772 static templates aux_templates
;
9773 bfd_boolean recheck
;
9775 aux_templates
.start
= t
;
9776 for (; t
< current_templates
->end
; ++t
)
9777 if (!t
->opcode_modifier
.isstring
)
9779 aux_templates
.end
= t
;
9781 /* Determine whether to re-check the first memory operand. */
9782 recheck
= (aux_templates
.start
!= current_templates
->start
9783 || t
!= current_templates
->end
);
9785 current_templates
= &aux_templates
;
9790 if (i
.memop1_string
!= NULL
9791 && i386_index_check (i
.memop1_string
) == 0)
9800 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
9804 i386_att_operand (char *operand_string
)
9808 char *op_string
= operand_string
;
9810 if (is_space_char (*op_string
))
9813 /* We check for an absolute prefix (differentiating,
9814 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
9815 if (*op_string
== ABSOLUTE_PREFIX
)
9818 if (is_space_char (*op_string
))
9820 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
9823 /* Check if operand is a register. */
9824 if ((r
= parse_register (op_string
, &end_op
)) != NULL
)
9826 i386_operand_type temp
;
9828 /* Check for a segment override by searching for ':' after a
9829 segment register. */
9831 if (is_space_char (*op_string
))
9833 if (*op_string
== ':'
9834 && (r
->reg_type
.bitfield
.sreg2
9835 || r
->reg_type
.bitfield
.sreg3
))
9840 i
.seg
[i
.mem_operands
] = &es
;
9843 i
.seg
[i
.mem_operands
] = &cs
;
9846 i
.seg
[i
.mem_operands
] = &ss
;
9849 i
.seg
[i
.mem_operands
] = &ds
;
9852 i
.seg
[i
.mem_operands
] = &fs
;
9855 i
.seg
[i
.mem_operands
] = &gs
;
9859 /* Skip the ':' and whitespace. */
9861 if (is_space_char (*op_string
))
9864 if (!is_digit_char (*op_string
)
9865 && !is_identifier_char (*op_string
)
9866 && *op_string
!= '('
9867 && *op_string
!= ABSOLUTE_PREFIX
)
9869 as_bad (_("bad memory operand `%s'"), op_string
);
9872 /* Handle case of %es:*foo. */
9873 if (*op_string
== ABSOLUTE_PREFIX
)
9876 if (is_space_char (*op_string
))
9878 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
9880 goto do_memory_reference
;
9883 /* Handle vector operations. */
9884 if (*op_string
== '{')
9886 op_string
= check_VecOperations (op_string
, NULL
);
9887 if (op_string
== NULL
)
9893 as_bad (_("junk `%s' after register"), op_string
);
9897 temp
.bitfield
.baseindex
= 0;
9898 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
9900 i
.types
[this_operand
].bitfield
.unspecified
= 0;
9901 i
.op
[this_operand
].regs
= r
;
9904 else if (*op_string
== REGISTER_PREFIX
)
9906 as_bad (_("bad register name `%s'"), op_string
);
9909 else if (*op_string
== IMMEDIATE_PREFIX
)
9912 if (i
.types
[this_operand
].bitfield
.jumpabsolute
)
9914 as_bad (_("immediate operand illegal with absolute jump"));
9917 if (!i386_immediate (op_string
))
9920 else if (RC_SAE_immediate (operand_string
))
9922 /* If it is a RC or SAE immediate, do nothing. */
9925 else if (is_digit_char (*op_string
)
9926 || is_identifier_char (*op_string
)
9927 || *op_string
== '"'
9928 || *op_string
== '(')
9930 /* This is a memory reference of some sort. */
9933 /* Start and end of displacement string expression (if found). */
9934 char *displacement_string_start
;
9935 char *displacement_string_end
;
9938 do_memory_reference
:
9939 if (i
.mem_operands
== 1 && !maybe_adjust_templates ())
9941 if ((i
.mem_operands
== 1
9942 && !current_templates
->start
->opcode_modifier
.isstring
)
9943 || i
.mem_operands
== 2)
9945 as_bad (_("too many memory references for `%s'"),
9946 current_templates
->start
->name
);
9950 /* Check for base index form. We detect the base index form by
9951 looking for an ')' at the end of the operand, searching
9952 for the '(' matching it, and finding a REGISTER_PREFIX or ','
9954 base_string
= op_string
+ strlen (op_string
);
9956 /* Handle vector operations. */
9957 vop_start
= strchr (op_string
, '{');
9958 if (vop_start
&& vop_start
< base_string
)
9960 if (check_VecOperations (vop_start
, base_string
) == NULL
)
9962 base_string
= vop_start
;
9966 if (is_space_char (*base_string
))
9969 /* If we only have a displacement, set-up for it to be parsed later. */
9970 displacement_string_start
= op_string
;
9971 displacement_string_end
= base_string
+ 1;
9973 if (*base_string
== ')')
9976 unsigned int parens_balanced
= 1;
9977 /* We've already checked that the number of left & right ()'s are
9978 equal, so this loop will not be infinite. */
9982 if (*base_string
== ')')
9984 if (*base_string
== '(')
9987 while (parens_balanced
);
9989 temp_string
= base_string
;
9991 /* Skip past '(' and whitespace. */
9993 if (is_space_char (*base_string
))
9996 if (*base_string
== ','
9997 || ((i
.base_reg
= parse_register (base_string
, &end_op
))
10000 displacement_string_end
= temp_string
;
10002 i
.types
[this_operand
].bitfield
.baseindex
= 1;
10006 base_string
= end_op
;
10007 if (is_space_char (*base_string
))
10011 /* There may be an index reg or scale factor here. */
10012 if (*base_string
== ',')
10015 if (is_space_char (*base_string
))
10018 if ((i
.index_reg
= parse_register (base_string
, &end_op
))
10021 base_string
= end_op
;
10022 if (is_space_char (*base_string
))
10024 if (*base_string
== ',')
10027 if (is_space_char (*base_string
))
10030 else if (*base_string
!= ')')
10032 as_bad (_("expecting `,' or `)' "
10033 "after index register in `%s'"),
10038 else if (*base_string
== REGISTER_PREFIX
)
10040 end_op
= strchr (base_string
, ',');
10043 as_bad (_("bad register name `%s'"), base_string
);
10047 /* Check for scale factor. */
10048 if (*base_string
!= ')')
10050 char *end_scale
= i386_scale (base_string
);
10055 base_string
= end_scale
;
10056 if (is_space_char (*base_string
))
10058 if (*base_string
!= ')')
10060 as_bad (_("expecting `)' "
10061 "after scale factor in `%s'"),
10066 else if (!i
.index_reg
)
10068 as_bad (_("expecting index register or scale factor "
10069 "after `,'; got '%c'"),
10074 else if (*base_string
!= ')')
10076 as_bad (_("expecting `,' or `)' "
10077 "after base register in `%s'"),
10082 else if (*base_string
== REGISTER_PREFIX
)
10084 end_op
= strchr (base_string
, ',');
10087 as_bad (_("bad register name `%s'"), base_string
);
10092 /* If there's an expression beginning the operand, parse it,
10093 assuming displacement_string_start and
10094 displacement_string_end are meaningful. */
10095 if (displacement_string_start
!= displacement_string_end
)
10097 if (!i386_displacement (displacement_string_start
,
10098 displacement_string_end
))
10102 /* Special case for (%dx) while doing input/output op. */
10104 && i
.base_reg
->reg_type
.bitfield
.inoutportreg
10105 && i
.index_reg
== 0
10106 && i
.log2_scale_factor
== 0
10107 && i
.seg
[i
.mem_operands
] == 0
10108 && !operand_type_check (i
.types
[this_operand
], disp
))
10110 i
.types
[this_operand
] = i
.base_reg
->reg_type
;
10114 if (i386_index_check (operand_string
) == 0)
10116 i
.flags
[this_operand
] |= Operand_Mem
;
10117 if (i
.mem_operands
== 0)
10118 i
.memop1_string
= xstrdup (operand_string
);
10123 /* It's not a memory operand; argh! */
10124 as_bad (_("invalid char %s beginning operand %d `%s'"),
10125 output_invalid (*op_string
),
10130 return 1; /* Normal return. */
10133 /* Calculate the maximum variable size (i.e., excluding fr_fix)
10134 that an rs_machine_dependent frag may reach. */
10137 i386_frag_max_var (fragS
*frag
)
10139 /* The only relaxable frags are for jumps.
10140 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
10141 gas_assert (frag
->fr_type
== rs_machine_dependent
);
10142 return TYPE_FROM_RELAX_STATE (frag
->fr_subtype
) == UNCOND_JUMP
? 4 : 5;
10145 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10147 elf_symbol_resolved_in_segment_p (symbolS
*fr_symbol
, offsetT fr_var
)
10149 /* STT_GNU_IFUNC symbol must go through PLT. */
10150 if ((symbol_get_bfdsym (fr_symbol
)->flags
10151 & BSF_GNU_INDIRECT_FUNCTION
) != 0)
10154 if (!S_IS_EXTERNAL (fr_symbol
))
10155 /* Symbol may be weak or local. */
10156 return !S_IS_WEAK (fr_symbol
);
10158 /* Global symbols with non-default visibility can't be preempted. */
10159 if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol
)) != STV_DEFAULT
)
10162 if (fr_var
!= NO_RELOC
)
10163 switch ((enum bfd_reloc_code_real
) fr_var
)
10165 case BFD_RELOC_386_PLT32
:
10166 case BFD_RELOC_X86_64_PLT32
:
10167 /* Symbol with PLT relocation may be preempted. */
10173 /* Global symbols with default visibility in a shared library may be
10174 preempted by another definition. */
10179 /* md_estimate_size_before_relax()
10181 Called just before relax() for rs_machine_dependent frags. The x86
10182 assembler uses these frags to handle variable size jump
10185 Any symbol that is now undefined will not become defined.
10186 Return the correct fr_subtype in the frag.
10187 Return the initial "guess for variable size of frag" to caller.
10188 The guess is actually the growth beyond the fixed part. Whatever
10189 we do to grow the fixed or variable part contributes to our
10193 md_estimate_size_before_relax (fragS
*fragP
, segT segment
)
10195 /* We've already got fragP->fr_subtype right; all we have to do is
10196 check for un-relaxable symbols. On an ELF system, we can't relax
10197 an externally visible symbol, because it may be overridden by a
10199 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
10200 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10202 && !elf_symbol_resolved_in_segment_p (fragP
->fr_symbol
,
10205 #if defined (OBJ_COFF) && defined (TE_PE)
10206 || (OUTPUT_FLAVOR
== bfd_target_coff_flavour
10207 && S_IS_WEAK (fragP
->fr_symbol
))
10211 /* Symbol is undefined in this segment, or we need to keep a
10212 reloc so that weak symbols can be overridden. */
10213 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
10214 enum bfd_reloc_code_real reloc_type
;
10215 unsigned char *opcode
;
10218 if (fragP
->fr_var
!= NO_RELOC
)
10219 reloc_type
= (enum bfd_reloc_code_real
) fragP
->fr_var
;
10220 else if (size
== 2)
10221 reloc_type
= BFD_RELOC_16_PCREL
;
10222 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10223 else if (need_plt32_p (fragP
->fr_symbol
))
10224 reloc_type
= BFD_RELOC_X86_64_PLT32
;
10227 reloc_type
= BFD_RELOC_32_PCREL
;
10229 old_fr_fix
= fragP
->fr_fix
;
10230 opcode
= (unsigned char *) fragP
->fr_opcode
;
10232 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
10235 /* Make jmp (0xeb) a (d)word displacement jump. */
10237 fragP
->fr_fix
+= size
;
10238 fix_new (fragP
, old_fr_fix
, size
,
10240 fragP
->fr_offset
, 1,
10246 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
10248 /* Negate the condition, and branch past an
10249 unconditional jump. */
10252 /* Insert an unconditional jump. */
10254 /* We added two extra opcode bytes, and have a two byte
10256 fragP
->fr_fix
+= 2 + 2;
10257 fix_new (fragP
, old_fr_fix
+ 2, 2,
10259 fragP
->fr_offset
, 1,
10263 /* Fall through. */
10266 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
10270 fragP
->fr_fix
+= 1;
10271 fixP
= fix_new (fragP
, old_fr_fix
, 1,
10273 fragP
->fr_offset
, 1,
10274 BFD_RELOC_8_PCREL
);
10275 fixP
->fx_signed
= 1;
10279 /* This changes the byte-displacement jump 0x7N
10280 to the (d)word-displacement jump 0x0f,0x8N. */
10281 opcode
[1] = opcode
[0] + 0x10;
10282 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
10283 /* We've added an opcode byte. */
10284 fragP
->fr_fix
+= 1 + size
;
10285 fix_new (fragP
, old_fr_fix
+ 1, size
,
10287 fragP
->fr_offset
, 1,
10292 BAD_CASE (fragP
->fr_subtype
);
10296 return fragP
->fr_fix
- old_fr_fix
;
10299 /* Guess size depending on current relax state. Initially the relax
10300 state will correspond to a short jump and we return 1, because
10301 the variable part of the frag (the branch offset) is one byte
10302 long. However, we can relax a section more than once and in that
10303 case we must either set fr_subtype back to the unrelaxed state,
10304 or return the value for the appropriate branch. */
10305 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
10308 /* Called after relax() is finished.
10310 In: Address of frag.
10311 fr_type == rs_machine_dependent.
10312 fr_subtype is what the address relaxed to.
10314 Out: Any fixSs and constants are set up.
10315 Caller will turn frag into a ".space 0". */
10318 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec ATTRIBUTE_UNUSED
,
10321 unsigned char *opcode
;
10322 unsigned char *where_to_put_displacement
= NULL
;
10323 offsetT target_address
;
10324 offsetT opcode_address
;
10325 unsigned int extension
= 0;
10326 offsetT displacement_from_opcode_start
;
10328 opcode
= (unsigned char *) fragP
->fr_opcode
;
10330 /* Address we want to reach in file space. */
10331 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
10333 /* Address opcode resides at in file space. */
10334 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
10336 /* Displacement from opcode start to fill into instruction. */
10337 displacement_from_opcode_start
= target_address
- opcode_address
;
10339 if ((fragP
->fr_subtype
& BIG
) == 0)
10341 /* Don't have to change opcode. */
10342 extension
= 1; /* 1 opcode + 1 displacement */
10343 where_to_put_displacement
= &opcode
[1];
10347 if (no_cond_jump_promotion
10348 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
10349 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
10350 _("long jump required"));
10352 switch (fragP
->fr_subtype
)
10354 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
10355 extension
= 4; /* 1 opcode + 4 displacement */
10357 where_to_put_displacement
= &opcode
[1];
10360 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
10361 extension
= 2; /* 1 opcode + 2 displacement */
10363 where_to_put_displacement
= &opcode
[1];
10366 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
10367 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
10368 extension
= 5; /* 2 opcode + 4 displacement */
10369 opcode
[1] = opcode
[0] + 0x10;
10370 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
10371 where_to_put_displacement
= &opcode
[2];
10374 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
10375 extension
= 3; /* 2 opcode + 2 displacement */
10376 opcode
[1] = opcode
[0] + 0x10;
10377 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
10378 where_to_put_displacement
= &opcode
[2];
10381 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
10386 where_to_put_displacement
= &opcode
[3];
10390 BAD_CASE (fragP
->fr_subtype
);
10395 /* If size if less then four we are sure that the operand fits,
10396 but if it's 4, then it could be that the displacement is larger
10398 if (DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
) == 4
10400 && ((addressT
) (displacement_from_opcode_start
- extension
10401 + ((addressT
) 1 << 31))
10402 > (((addressT
) 2 << 31) - 1)))
10404 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
10405 _("jump target out of range"));
10406 /* Make us emit 0. */
10407 displacement_from_opcode_start
= extension
;
10409 /* Now put displacement after opcode. */
10410 md_number_to_chars ((char *) where_to_put_displacement
,
10411 (valueT
) (displacement_from_opcode_start
- extension
),
10412 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
10413 fragP
->fr_fix
+= extension
;
10416 /* Apply a fixup (fixP) to segment data, once it has been determined
10417 by our caller that we have all the info we need to fix it up.
10419 Parameter valP is the pointer to the value of the bits.
10421 On the 386, immediates, displacements, and data pointers are all in
10422 the same (little-endian) format, so we don't need to care about which
10423 we are handling. */
10426 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
10428 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
10429 valueT value
= *valP
;
10431 #if !defined (TE_Mach)
10432 if (fixP
->fx_pcrel
)
10434 switch (fixP
->fx_r_type
)
10440 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
10443 case BFD_RELOC_X86_64_32S
:
10444 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
10447 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
10450 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
10455 if (fixP
->fx_addsy
!= NULL
10456 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
10457 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
10458 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
10459 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
10460 && !use_rela_relocations
)
10462 /* This is a hack. There should be a better way to handle this.
10463 This covers for the fact that bfd_install_relocation will
10464 subtract the current location (for partial_inplace, PC relative
10465 relocations); see more below. */
10469 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
10472 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
10474 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10477 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
10479 if ((sym_seg
== seg
10480 || (symbol_section_p (fixP
->fx_addsy
)
10481 && sym_seg
!= absolute_section
))
10482 && !generic_force_reloc (fixP
))
10484 /* Yes, we add the values in twice. This is because
10485 bfd_install_relocation subtracts them out again. I think
10486 bfd_install_relocation is broken, but I don't dare change
10488 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
10492 #if defined (OBJ_COFF) && defined (TE_PE)
10493 /* For some reason, the PE format does not store a
10494 section address offset for a PC relative symbol. */
10495 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
10496 || S_IS_WEAK (fixP
->fx_addsy
))
10497 value
+= md_pcrel_from (fixP
);
10500 #if defined (OBJ_COFF) && defined (TE_PE)
10501 if (fixP
->fx_addsy
!= NULL
10502 && S_IS_WEAK (fixP
->fx_addsy
)
10503 /* PR 16858: Do not modify weak function references. */
10504 && ! fixP
->fx_pcrel
)
10506 #if !defined (TE_PEP)
10507 /* For x86 PE weak function symbols are neither PC-relative
10508 nor do they set S_IS_FUNCTION. So the only reliable way
10509 to detect them is to check the flags of their containing
10511 if (S_GET_SEGMENT (fixP
->fx_addsy
) != NULL
10512 && S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_CODE
)
10516 value
-= S_GET_VALUE (fixP
->fx_addsy
);
10520 /* Fix a few things - the dynamic linker expects certain values here,
10521 and we must not disappoint it. */
10522 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10523 if (IS_ELF
&& fixP
->fx_addsy
)
10524 switch (fixP
->fx_r_type
)
10526 case BFD_RELOC_386_PLT32
:
10527 case BFD_RELOC_X86_64_PLT32
:
10528 /* Make the jump instruction point to the address of the operand. At
10529 runtime we merely add the offset to the actual PLT entry. */
10533 case BFD_RELOC_386_TLS_GD
:
10534 case BFD_RELOC_386_TLS_LDM
:
10535 case BFD_RELOC_386_TLS_IE_32
:
10536 case BFD_RELOC_386_TLS_IE
:
10537 case BFD_RELOC_386_TLS_GOTIE
:
10538 case BFD_RELOC_386_TLS_GOTDESC
:
10539 case BFD_RELOC_X86_64_TLSGD
:
10540 case BFD_RELOC_X86_64_TLSLD
:
10541 case BFD_RELOC_X86_64_GOTTPOFF
:
10542 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
10543 value
= 0; /* Fully resolved at runtime. No addend. */
10545 case BFD_RELOC_386_TLS_LE
:
10546 case BFD_RELOC_386_TLS_LDO_32
:
10547 case BFD_RELOC_386_TLS_LE_32
:
10548 case BFD_RELOC_X86_64_DTPOFF32
:
10549 case BFD_RELOC_X86_64_DTPOFF64
:
10550 case BFD_RELOC_X86_64_TPOFF32
:
10551 case BFD_RELOC_X86_64_TPOFF64
:
10552 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
10555 case BFD_RELOC_386_TLS_DESC_CALL
:
10556 case BFD_RELOC_X86_64_TLSDESC_CALL
:
10557 value
= 0; /* Fully resolved at runtime. No addend. */
10558 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
10562 case BFD_RELOC_VTABLE_INHERIT
:
10563 case BFD_RELOC_VTABLE_ENTRY
:
10570 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
10572 #endif /* !defined (TE_Mach) */
10574 /* Are we finished with this relocation now? */
10575 if (fixP
->fx_addsy
== NULL
)
10577 #if defined (OBJ_COFF) && defined (TE_PE)
10578 else if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
10581 /* Remember value for tc_gen_reloc. */
10582 fixP
->fx_addnumber
= value
;
10583 /* Clear out the frag for now. */
10587 else if (use_rela_relocations
)
10589 fixP
->fx_no_overflow
= 1;
10590 /* Remember value for tc_gen_reloc. */
10591 fixP
->fx_addnumber
= value
;
10595 md_number_to_chars (p
, value
, fixP
->fx_size
);
10599 md_atof (int type
, char *litP
, int *sizeP
)
10601 /* This outputs the LITTLENUMs in REVERSE order;
10602 in accord with the bigendian 386. */
10603 return ieee_md_atof (type
, litP
, sizeP
, FALSE
);
10606 static char output_invalid_buf
[sizeof (unsigned char) * 2 + 6];
10609 output_invalid (int c
)
10612 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
10615 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
10616 "(0x%x)", (unsigned char) c
);
10617 return output_invalid_buf
;
10620 /* REG_STRING starts *before* REGISTER_PREFIX. */
10622 static const reg_entry
*
10623 parse_real_register (char *reg_string
, char **end_op
)
10625 char *s
= reg_string
;
10627 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
10628 const reg_entry
*r
;
10630 /* Skip possible REGISTER_PREFIX and possible whitespace. */
10631 if (*s
== REGISTER_PREFIX
)
10634 if (is_space_char (*s
))
10637 p
= reg_name_given
;
10638 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
10640 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
10641 return (const reg_entry
*) NULL
;
10645 /* For naked regs, make sure that we are not dealing with an identifier.
10646 This prevents confusing an identifier like `eax_var' with register
10648 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
10649 return (const reg_entry
*) NULL
;
10653 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
10655 /* Handle floating point regs, allowing spaces in the (i) part. */
10656 if (r
== i386_regtab
/* %st is first entry of table */)
10658 if (!cpu_arch_flags
.bitfield
.cpu8087
10659 && !cpu_arch_flags
.bitfield
.cpu287
10660 && !cpu_arch_flags
.bitfield
.cpu387
)
10661 return (const reg_entry
*) NULL
;
10663 if (is_space_char (*s
))
10668 if (is_space_char (*s
))
10670 if (*s
>= '0' && *s
<= '7')
10672 int fpr
= *s
- '0';
10674 if (is_space_char (*s
))
10679 r
= (const reg_entry
*) hash_find (reg_hash
, "st(0)");
10684 /* We have "%st(" then garbage. */
10685 return (const reg_entry
*) NULL
;
10689 if (r
== NULL
|| allow_pseudo_reg
)
10692 if (operand_type_all_zero (&r
->reg_type
))
10693 return (const reg_entry
*) NULL
;
10695 if ((r
->reg_type
.bitfield
.dword
10696 || r
->reg_type
.bitfield
.sreg3
10697 || r
->reg_type
.bitfield
.control
10698 || r
->reg_type
.bitfield
.debug
10699 || r
->reg_type
.bitfield
.test
)
10700 && !cpu_arch_flags
.bitfield
.cpui386
)
10701 return (const reg_entry
*) NULL
;
10703 if (r
->reg_type
.bitfield
.regmmx
&& !cpu_arch_flags
.bitfield
.cpummx
)
10704 return (const reg_entry
*) NULL
;
10706 if (!cpu_arch_flags
.bitfield
.cpuavx512f
)
10708 if (r
->reg_type
.bitfield
.zmmword
|| r
->reg_type
.bitfield
.regmask
)
10709 return (const reg_entry
*) NULL
;
10711 if (!cpu_arch_flags
.bitfield
.cpuavx
)
10713 if (r
->reg_type
.bitfield
.ymmword
)
10714 return (const reg_entry
*) NULL
;
10716 if (!cpu_arch_flags
.bitfield
.cpusse
&& r
->reg_type
.bitfield
.xmmword
)
10717 return (const reg_entry
*) NULL
;
10721 if (r
->reg_type
.bitfield
.regbnd
&& !cpu_arch_flags
.bitfield
.cpumpx
)
10722 return (const reg_entry
*) NULL
;
10724 /* Don't allow fake index register unless allow_index_reg isn't 0. */
10725 if (!allow_index_reg
&& r
->reg_num
== RegIZ
)
10726 return (const reg_entry
*) NULL
;
10728 /* Upper 16 vector registers are only available with VREX in 64bit
10729 mode, and require EVEX encoding. */
10730 if (r
->reg_flags
& RegVRex
)
10732 if (!cpu_arch_flags
.bitfield
.cpuavx512f
10733 || flag_code
!= CODE_64BIT
)
10734 return (const reg_entry
*) NULL
;
10736 i
.vec_encoding
= vex_encoding_evex
;
10739 if (((r
->reg_flags
& (RegRex64
| RegRex
)) || r
->reg_type
.bitfield
.qword
)
10740 && (!cpu_arch_flags
.bitfield
.cpulm
|| !r
->reg_type
.bitfield
.control
)
10741 && flag_code
!= CODE_64BIT
)
10742 return (const reg_entry
*) NULL
;
10744 if (r
->reg_type
.bitfield
.sreg3
&& r
->reg_num
== RegFlat
&& !intel_syntax
)
10745 return (const reg_entry
*) NULL
;
10750 /* REG_STRING starts *before* REGISTER_PREFIX. */
10752 static const reg_entry
*
10753 parse_register (char *reg_string
, char **end_op
)
10755 const reg_entry
*r
;
10757 if (*reg_string
== REGISTER_PREFIX
|| allow_naked_reg
)
10758 r
= parse_real_register (reg_string
, end_op
);
10763 char *save
= input_line_pointer
;
10767 input_line_pointer
= reg_string
;
10768 c
= get_symbol_name (®_string
);
10769 symbolP
= symbol_find (reg_string
);
10770 if (symbolP
&& S_GET_SEGMENT (symbolP
) == reg_section
)
10772 const expressionS
*e
= symbol_get_value_expression (symbolP
);
10774 know (e
->X_op
== O_register
);
10775 know (e
->X_add_number
>= 0
10776 && (valueT
) e
->X_add_number
< i386_regtab_size
);
10777 r
= i386_regtab
+ e
->X_add_number
;
10778 if ((r
->reg_flags
& RegVRex
))
10779 i
.vec_encoding
= vex_encoding_evex
;
10780 *end_op
= input_line_pointer
;
10782 *input_line_pointer
= c
;
10783 input_line_pointer
= save
;
10789 i386_parse_name (char *name
, expressionS
*e
, char *nextcharP
)
10791 const reg_entry
*r
;
10792 char *end
= input_line_pointer
;
10795 r
= parse_register (name
, &input_line_pointer
);
10796 if (r
&& end
<= input_line_pointer
)
10798 *nextcharP
= *input_line_pointer
;
10799 *input_line_pointer
= 0;
10800 e
->X_op
= O_register
;
10801 e
->X_add_number
= r
- i386_regtab
;
10804 input_line_pointer
= end
;
10806 return intel_syntax
? i386_intel_parse_name (name
, e
) : 0;
10810 md_operand (expressionS
*e
)
10813 const reg_entry
*r
;
10815 switch (*input_line_pointer
)
10817 case REGISTER_PREFIX
:
10818 r
= parse_real_register (input_line_pointer
, &end
);
10821 e
->X_op
= O_register
;
10822 e
->X_add_number
= r
- i386_regtab
;
10823 input_line_pointer
= end
;
10828 gas_assert (intel_syntax
);
10829 end
= input_line_pointer
++;
10831 if (*input_line_pointer
== ']')
10833 ++input_line_pointer
;
10834 e
->X_op_symbol
= make_expr_symbol (e
);
10835 e
->X_add_symbol
= NULL
;
10836 e
->X_add_number
= 0;
10841 e
->X_op
= O_absent
;
10842 input_line_pointer
= end
;
10849 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10850 const char *md_shortopts
= "kVQ:sqnO::";
10852 const char *md_shortopts
= "qnO::";
10855 #define OPTION_32 (OPTION_MD_BASE + 0)
10856 #define OPTION_64 (OPTION_MD_BASE + 1)
10857 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
10858 #define OPTION_MARCH (OPTION_MD_BASE + 3)
10859 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
10860 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
10861 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
10862 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
10863 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
10864 #define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 9)
10865 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
10866 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
10867 #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
10868 #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
10869 #define OPTION_X32 (OPTION_MD_BASE + 14)
10870 #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
10871 #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
10872 #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
10873 #define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
10874 #define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
10875 #define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
10876 #define OPTION_MSHARED (OPTION_MD_BASE + 21)
10877 #define OPTION_MAMD64 (OPTION_MD_BASE + 22)
10878 #define OPTION_MINTEL64 (OPTION_MD_BASE + 23)
10879 #define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24)
10880 #define OPTION_X86_USED_NOTE (OPTION_MD_BASE + 25)
10882 struct option md_longopts
[] =
10884 {"32", no_argument
, NULL
, OPTION_32
},
10885 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10886 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
10887 {"64", no_argument
, NULL
, OPTION_64
},
10889 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10890 {"x32", no_argument
, NULL
, OPTION_X32
},
10891 {"mshared", no_argument
, NULL
, OPTION_MSHARED
},
10892 {"mx86-used-note", required_argument
, NULL
, OPTION_X86_USED_NOTE
},
10894 {"divide", no_argument
, NULL
, OPTION_DIVIDE
},
10895 {"march", required_argument
, NULL
, OPTION_MARCH
},
10896 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
10897 {"mmnemonic", required_argument
, NULL
, OPTION_MMNEMONIC
},
10898 {"msyntax", required_argument
, NULL
, OPTION_MSYNTAX
},
10899 {"mindex-reg", no_argument
, NULL
, OPTION_MINDEX_REG
},
10900 {"mnaked-reg", no_argument
, NULL
, OPTION_MNAKED_REG
},
10901 {"msse2avx", no_argument
, NULL
, OPTION_MSSE2AVX
},
10902 {"msse-check", required_argument
, NULL
, OPTION_MSSE_CHECK
},
10903 {"moperand-check", required_argument
, NULL
, OPTION_MOPERAND_CHECK
},
10904 {"mavxscalar", required_argument
, NULL
, OPTION_MAVXSCALAR
},
10905 {"madd-bnd-prefix", no_argument
, NULL
, OPTION_MADD_BND_PREFIX
},
10906 {"mevexlig", required_argument
, NULL
, OPTION_MEVEXLIG
},
10907 {"mevexwig", required_argument
, NULL
, OPTION_MEVEXWIG
},
10908 # if defined (TE_PE) || defined (TE_PEP)
10909 {"mbig-obj", no_argument
, NULL
, OPTION_MBIG_OBJ
},
10911 {"momit-lock-prefix", required_argument
, NULL
, OPTION_MOMIT_LOCK_PREFIX
},
10912 {"mfence-as-lock-add", required_argument
, NULL
, OPTION_MFENCE_AS_LOCK_ADD
},
10913 {"mrelax-relocations", required_argument
, NULL
, OPTION_MRELAX_RELOCATIONS
},
10914 {"mevexrcig", required_argument
, NULL
, OPTION_MEVEXRCIG
},
10915 {"mamd64", no_argument
, NULL
, OPTION_MAMD64
},
10916 {"mintel64", no_argument
, NULL
, OPTION_MINTEL64
},
10917 {NULL
, no_argument
, NULL
, 0}
10919 size_t md_longopts_size
= sizeof (md_longopts
);
10922 md_parse_option (int c
, const char *arg
)
10925 char *arch
, *next
, *saved
;
10930 optimize_align_code
= 0;
10934 quiet_warnings
= 1;
10937 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10938 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
10939 should be emitted or not. FIXME: Not implemented. */
10943 /* -V: SVR4 argument to print version ID. */
10945 print_version_id ();
10948 /* -k: Ignore for FreeBSD compatibility. */
10953 /* -s: On i386 Solaris, this tells the native assembler to use
10954 .stab instead of .stab.excl. We always use .stab anyhow. */
10957 case OPTION_MSHARED
:
10961 case OPTION_X86_USED_NOTE
:
10962 if (strcasecmp (arg
, "yes") == 0)
10964 else if (strcasecmp (arg
, "no") == 0)
10967 as_fatal (_("invalid -mx86-used-note= option: `%s'"), arg
);
10972 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10973 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
10976 const char **list
, **l
;
10978 list
= bfd_target_list ();
10979 for (l
= list
; *l
!= NULL
; l
++)
10980 if (CONST_STRNEQ (*l
, "elf64-x86-64")
10981 || strcmp (*l
, "coff-x86-64") == 0
10982 || strcmp (*l
, "pe-x86-64") == 0
10983 || strcmp (*l
, "pei-x86-64") == 0
10984 || strcmp (*l
, "mach-o-x86-64") == 0)
10986 default_arch
= "x86_64";
10990 as_fatal (_("no compiled in support for x86_64"));
10996 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11000 const char **list
, **l
;
11002 list
= bfd_target_list ();
11003 for (l
= list
; *l
!= NULL
; l
++)
11004 if (CONST_STRNEQ (*l
, "elf32-x86-64"))
11006 default_arch
= "x86_64:32";
11010 as_fatal (_("no compiled in support for 32bit x86_64"));
11014 as_fatal (_("32bit x86_64 is only supported for ELF"));
11019 default_arch
= "i386";
11022 case OPTION_DIVIDE
:
11023 #ifdef SVR4_COMMENT_CHARS
11028 n
= XNEWVEC (char, strlen (i386_comment_chars
) + 1);
11030 for (s
= i386_comment_chars
; *s
!= '\0'; s
++)
11034 i386_comment_chars
= n
;
11040 saved
= xstrdup (arg
);
11042 /* Allow -march=+nosse. */
11048 as_fatal (_("invalid -march= option: `%s'"), arg
);
11049 next
= strchr (arch
, '+');
11052 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
11054 if (strcmp (arch
, cpu_arch
[j
].name
) == 0)
11057 if (! cpu_arch
[j
].flags
.bitfield
.cpui386
)
11060 cpu_arch_name
= cpu_arch
[j
].name
;
11061 cpu_sub_arch_name
= NULL
;
11062 cpu_arch_flags
= cpu_arch
[j
].flags
;
11063 cpu_arch_isa
= cpu_arch
[j
].type
;
11064 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
11065 if (!cpu_arch_tune_set
)
11067 cpu_arch_tune
= cpu_arch_isa
;
11068 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
11072 else if (*cpu_arch
[j
].name
== '.'
11073 && strcmp (arch
, cpu_arch
[j
].name
+ 1) == 0)
11075 /* ISA extension. */
11076 i386_cpu_flags flags
;
11078 flags
= cpu_flags_or (cpu_arch_flags
,
11079 cpu_arch
[j
].flags
);
11081 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
11083 if (cpu_sub_arch_name
)
11085 char *name
= cpu_sub_arch_name
;
11086 cpu_sub_arch_name
= concat (name
,
11088 (const char *) NULL
);
11092 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
11093 cpu_arch_flags
= flags
;
11094 cpu_arch_isa_flags
= flags
;
11098 = cpu_flags_or (cpu_arch_isa_flags
,
11099 cpu_arch
[j
].flags
);
11104 if (j
>= ARRAY_SIZE (cpu_arch
))
11106 /* Disable an ISA extension. */
11107 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
11108 if (strcmp (arch
, cpu_noarch
[j
].name
) == 0)
11110 i386_cpu_flags flags
;
11112 flags
= cpu_flags_and_not (cpu_arch_flags
,
11113 cpu_noarch
[j
].flags
);
11114 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
11116 if (cpu_sub_arch_name
)
11118 char *name
= cpu_sub_arch_name
;
11119 cpu_sub_arch_name
= concat (arch
,
11120 (const char *) NULL
);
11124 cpu_sub_arch_name
= xstrdup (arch
);
11125 cpu_arch_flags
= flags
;
11126 cpu_arch_isa_flags
= flags
;
11131 if (j
>= ARRAY_SIZE (cpu_noarch
))
11132 j
= ARRAY_SIZE (cpu_arch
);
11135 if (j
>= ARRAY_SIZE (cpu_arch
))
11136 as_fatal (_("invalid -march= option: `%s'"), arg
);
11140 while (next
!= NULL
);
11146 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
11147 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
11149 if (strcmp (arg
, cpu_arch
[j
].name
) == 0)
11151 cpu_arch_tune_set
= 1;
11152 cpu_arch_tune
= cpu_arch
[j
].type
;
11153 cpu_arch_tune_flags
= cpu_arch
[j
].flags
;
11157 if (j
>= ARRAY_SIZE (cpu_arch
))
11158 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
11161 case OPTION_MMNEMONIC
:
11162 if (strcasecmp (arg
, "att") == 0)
11163 intel_mnemonic
= 0;
11164 else if (strcasecmp (arg
, "intel") == 0)
11165 intel_mnemonic
= 1;
11167 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg
);
11170 case OPTION_MSYNTAX
:
11171 if (strcasecmp (arg
, "att") == 0)
11173 else if (strcasecmp (arg
, "intel") == 0)
11176 as_fatal (_("invalid -msyntax= option: `%s'"), arg
);
11179 case OPTION_MINDEX_REG
:
11180 allow_index_reg
= 1;
11183 case OPTION_MNAKED_REG
:
11184 allow_naked_reg
= 1;
11187 case OPTION_MSSE2AVX
:
11191 case OPTION_MSSE_CHECK
:
11192 if (strcasecmp (arg
, "error") == 0)
11193 sse_check
= check_error
;
11194 else if (strcasecmp (arg
, "warning") == 0)
11195 sse_check
= check_warning
;
11196 else if (strcasecmp (arg
, "none") == 0)
11197 sse_check
= check_none
;
11199 as_fatal (_("invalid -msse-check= option: `%s'"), arg
);
11202 case OPTION_MOPERAND_CHECK
:
11203 if (strcasecmp (arg
, "error") == 0)
11204 operand_check
= check_error
;
11205 else if (strcasecmp (arg
, "warning") == 0)
11206 operand_check
= check_warning
;
11207 else if (strcasecmp (arg
, "none") == 0)
11208 operand_check
= check_none
;
11210 as_fatal (_("invalid -moperand-check= option: `%s'"), arg
);
11213 case OPTION_MAVXSCALAR
:
11214 if (strcasecmp (arg
, "128") == 0)
11215 avxscalar
= vex128
;
11216 else if (strcasecmp (arg
, "256") == 0)
11217 avxscalar
= vex256
;
11219 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg
);
11222 case OPTION_MADD_BND_PREFIX
:
11223 add_bnd_prefix
= 1;
11226 case OPTION_MEVEXLIG
:
11227 if (strcmp (arg
, "128") == 0)
11228 evexlig
= evexl128
;
11229 else if (strcmp (arg
, "256") == 0)
11230 evexlig
= evexl256
;
11231 else if (strcmp (arg
, "512") == 0)
11232 evexlig
= evexl512
;
11234 as_fatal (_("invalid -mevexlig= option: `%s'"), arg
);
11237 case OPTION_MEVEXRCIG
:
11238 if (strcmp (arg
, "rne") == 0)
11240 else if (strcmp (arg
, "rd") == 0)
11242 else if (strcmp (arg
, "ru") == 0)
11244 else if (strcmp (arg
, "rz") == 0)
11247 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg
);
11250 case OPTION_MEVEXWIG
:
11251 if (strcmp (arg
, "0") == 0)
11253 else if (strcmp (arg
, "1") == 0)
11256 as_fatal (_("invalid -mevexwig= option: `%s'"), arg
);
11259 # if defined (TE_PE) || defined (TE_PEP)
11260 case OPTION_MBIG_OBJ
:
11265 case OPTION_MOMIT_LOCK_PREFIX
:
11266 if (strcasecmp (arg
, "yes") == 0)
11267 omit_lock_prefix
= 1;
11268 else if (strcasecmp (arg
, "no") == 0)
11269 omit_lock_prefix
= 0;
11271 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg
);
11274 case OPTION_MFENCE_AS_LOCK_ADD
:
11275 if (strcasecmp (arg
, "yes") == 0)
11277 else if (strcasecmp (arg
, "no") == 0)
11280 as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg
);
11283 case OPTION_MRELAX_RELOCATIONS
:
11284 if (strcasecmp (arg
, "yes") == 0)
11285 generate_relax_relocations
= 1;
11286 else if (strcasecmp (arg
, "no") == 0)
11287 generate_relax_relocations
= 0;
11289 as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg
);
11292 case OPTION_MAMD64
:
11296 case OPTION_MINTEL64
:
11304 /* Turn off -Os. */
11305 optimize_for_space
= 0;
11307 else if (*arg
== 's')
11309 optimize_for_space
= 1;
11310 /* Turn on all encoding optimizations. */
11315 optimize
= atoi (arg
);
11316 /* Turn off -Os. */
11317 optimize_for_space
= 0;
11327 #define MESSAGE_TEMPLATE \
11331 output_message (FILE *stream
, char *p
, char *message
, char *start
,
11332 int *left_p
, const char *name
, int len
)
11334 int size
= sizeof (MESSAGE_TEMPLATE
);
11335 int left
= *left_p
;
11337 /* Reserve 2 spaces for ", " or ",\0" */
11340 /* Check if there is any room. */
11348 p
= mempcpy (p
, name
, len
);
11352 /* Output the current message now and start a new one. */
11355 fprintf (stream
, "%s\n", message
);
11357 left
= size
- (start
- message
) - len
- 2;
11359 gas_assert (left
>= 0);
11361 p
= mempcpy (p
, name
, len
);
11369 show_arch (FILE *stream
, int ext
, int check
)
11371 static char message
[] = MESSAGE_TEMPLATE
;
11372 char *start
= message
+ 27;
11374 int size
= sizeof (MESSAGE_TEMPLATE
);
11381 left
= size
- (start
- message
);
11382 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
11384 /* Should it be skipped? */
11385 if (cpu_arch
[j
].skip
)
11388 name
= cpu_arch
[j
].name
;
11389 len
= cpu_arch
[j
].len
;
11392 /* It is an extension. Skip if we aren't asked to show it. */
11403 /* It is an processor. Skip if we show only extension. */
11406 else if (check
&& ! cpu_arch
[j
].flags
.bitfield
.cpui386
)
11408 /* It is an impossible processor - skip. */
11412 p
= output_message (stream
, p
, message
, start
, &left
, name
, len
);
11415 /* Display disabled extensions. */
11417 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
11419 name
= cpu_noarch
[j
].name
;
11420 len
= cpu_noarch
[j
].len
;
11421 p
= output_message (stream
, p
, message
, start
, &left
, name
,
11426 fprintf (stream
, "%s\n", message
);
11430 md_show_usage (FILE *stream
)
11432 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11433 fprintf (stream
, _("\
11435 -V print assembler version number\n\
11438 fprintf (stream
, _("\
11439 -n Do not optimize code alignment\n\
11440 -q quieten some warnings\n"));
11441 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11442 fprintf (stream
, _("\
11445 #if defined BFD64 && (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
11446 || defined (TE_PE) || defined (TE_PEP))
11447 fprintf (stream
, _("\
11448 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
11450 #ifdef SVR4_COMMENT_CHARS
11451 fprintf (stream
, _("\
11452 --divide do not treat `/' as a comment character\n"));
11454 fprintf (stream
, _("\
11455 --divide ignored\n"));
11457 fprintf (stream
, _("\
11458 -march=CPU[,+EXTENSION...]\n\
11459 generate code for CPU and EXTENSION, CPU is one of:\n"));
11460 show_arch (stream
, 0, 1);
11461 fprintf (stream
, _("\
11462 EXTENSION is combination of:\n"));
11463 show_arch (stream
, 1, 0);
11464 fprintf (stream
, _("\
11465 -mtune=CPU optimize for CPU, CPU is one of:\n"));
11466 show_arch (stream
, 0, 0);
11467 fprintf (stream
, _("\
11468 -msse2avx encode SSE instructions with VEX prefix\n"));
11469 fprintf (stream
, _("\
11470 -msse-check=[none|error|warning] (default: warning)\n\
11471 check SSE instructions\n"));
11472 fprintf (stream
, _("\
11473 -moperand-check=[none|error|warning] (default: warning)\n\
11474 check operand combinations for validity\n"));
11475 fprintf (stream
, _("\
11476 -mavxscalar=[128|256] (default: 128)\n\
11477 encode scalar AVX instructions with specific vector\n\
11479 fprintf (stream
, _("\
11480 -mevexlig=[128|256|512] (default: 128)\n\
11481 encode scalar EVEX instructions with specific vector\n\
11483 fprintf (stream
, _("\
11484 -mevexwig=[0|1] (default: 0)\n\
11485 encode EVEX instructions with specific EVEX.W value\n\
11486 for EVEX.W bit ignored instructions\n"));
11487 fprintf (stream
, _("\
11488 -mevexrcig=[rne|rd|ru|rz] (default: rne)\n\
11489 encode EVEX instructions with specific EVEX.RC value\n\
11490 for SAE-only ignored instructions\n"));
11491 fprintf (stream
, _("\
11492 -mmnemonic=[att|intel] "));
11493 if (SYSV386_COMPAT
)
11494 fprintf (stream
, _("(default: att)\n"));
11496 fprintf (stream
, _("(default: intel)\n"));
11497 fprintf (stream
, _("\
11498 use AT&T/Intel mnemonic\n"));
11499 fprintf (stream
, _("\
11500 -msyntax=[att|intel] (default: att)\n\
11501 use AT&T/Intel syntax\n"));
11502 fprintf (stream
, _("\
11503 -mindex-reg support pseudo index registers\n"));
11504 fprintf (stream
, _("\
11505 -mnaked-reg don't require `%%' prefix for registers\n"));
11506 fprintf (stream
, _("\
11507 -madd-bnd-prefix add BND prefix for all valid branches\n"));
11508 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11509 fprintf (stream
, _("\
11510 -mshared disable branch optimization for shared code\n"));
11511 fprintf (stream
, _("\
11512 -mx86-used-note=[no|yes] "));
11513 if (DEFAULT_X86_USED_NOTE
)
11514 fprintf (stream
, _("(default: yes)\n"));
11516 fprintf (stream
, _("(default: no)\n"));
11517 fprintf (stream
, _("\
11518 generate x86 used ISA and feature properties\n"));
11520 #if defined (TE_PE) || defined (TE_PEP)
11521 fprintf (stream
, _("\
11522 -mbig-obj generate big object files\n"));
11524 fprintf (stream
, _("\
11525 -momit-lock-prefix=[no|yes] (default: no)\n\
11526 strip all lock prefixes\n"));
11527 fprintf (stream
, _("\
11528 -mfence-as-lock-add=[no|yes] (default: no)\n\
11529 encode lfence, mfence and sfence as\n\
11530 lock addl $0x0, (%%{re}sp)\n"));
11531 fprintf (stream
, _("\
11532 -mrelax-relocations=[no|yes] "));
11533 if (DEFAULT_GENERATE_X86_RELAX_RELOCATIONS
)
11534 fprintf (stream
, _("(default: yes)\n"));
11536 fprintf (stream
, _("(default: no)\n"));
11537 fprintf (stream
, _("\
11538 generate relax relocations\n"));
11539 fprintf (stream
, _("\
11540 -mamd64 accept only AMD64 ISA [default]\n"));
11541 fprintf (stream
, _("\
11542 -mintel64 accept only Intel64 ISA\n"));
11545 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
11546 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
11547 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
11549 /* Pick the target format to use. */
11552 i386_target_format (void)
11554 if (!strncmp (default_arch
, "x86_64", 6))
11556 update_code_flag (CODE_64BIT
, 1);
11557 if (default_arch
[6] == '\0')
11558 x86_elf_abi
= X86_64_ABI
;
11560 x86_elf_abi
= X86_64_X32_ABI
;
11562 else if (!strcmp (default_arch
, "i386"))
11563 update_code_flag (CODE_32BIT
, 1);
11564 else if (!strcmp (default_arch
, "iamcu"))
11566 update_code_flag (CODE_32BIT
, 1);
11567 if (cpu_arch_isa
== PROCESSOR_UNKNOWN
)
11569 static const i386_cpu_flags iamcu_flags
= CPU_IAMCU_FLAGS
;
11570 cpu_arch_name
= "iamcu";
11571 cpu_sub_arch_name
= NULL
;
11572 cpu_arch_flags
= iamcu_flags
;
11573 cpu_arch_isa
= PROCESSOR_IAMCU
;
11574 cpu_arch_isa_flags
= iamcu_flags
;
11575 if (!cpu_arch_tune_set
)
11577 cpu_arch_tune
= cpu_arch_isa
;
11578 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
11581 else if (cpu_arch_isa
!= PROCESSOR_IAMCU
)
11582 as_fatal (_("Intel MCU doesn't support `%s' architecture"),
11586 as_fatal (_("unknown architecture"));
11588 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
11589 cpu_arch_isa_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
11590 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
11591 cpu_arch_tune_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
11593 switch (OUTPUT_FLAVOR
)
11595 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
11596 case bfd_target_aout_flavour
:
11597 return AOUT_TARGET_FORMAT
;
11599 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
11600 # if defined (TE_PE) || defined (TE_PEP)
11601 case bfd_target_coff_flavour
:
11602 if (flag_code
== CODE_64BIT
)
11603 return use_big_obj
? "pe-bigobj-x86-64" : "pe-x86-64";
11606 # elif defined (TE_GO32)
11607 case bfd_target_coff_flavour
:
11608 return "coff-go32";
11610 case bfd_target_coff_flavour
:
11611 return "coff-i386";
11614 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
11615 case bfd_target_elf_flavour
:
11617 const char *format
;
11619 switch (x86_elf_abi
)
11622 format
= ELF_TARGET_FORMAT
;
11625 use_rela_relocations
= 1;
11627 format
= ELF_TARGET_FORMAT64
;
11629 case X86_64_X32_ABI
:
11630 use_rela_relocations
= 1;
11632 disallow_64bit_reloc
= 1;
11633 format
= ELF_TARGET_FORMAT32
;
11636 if (cpu_arch_isa
== PROCESSOR_L1OM
)
11638 if (x86_elf_abi
!= X86_64_ABI
)
11639 as_fatal (_("Intel L1OM is 64bit only"));
11640 return ELF_TARGET_L1OM_FORMAT
;
11642 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
11644 if (x86_elf_abi
!= X86_64_ABI
)
11645 as_fatal (_("Intel K1OM is 64bit only"));
11646 return ELF_TARGET_K1OM_FORMAT
;
11648 else if (cpu_arch_isa
== PROCESSOR_IAMCU
)
11650 if (x86_elf_abi
!= I386_ABI
)
11651 as_fatal (_("Intel MCU is 32bit only"));
11652 return ELF_TARGET_IAMCU_FORMAT
;
11658 #if defined (OBJ_MACH_O)
11659 case bfd_target_mach_o_flavour
:
11660 if (flag_code
== CODE_64BIT
)
11662 use_rela_relocations
= 1;
11664 return "mach-o-x86-64";
11667 return "mach-o-i386";
11675 #endif /* OBJ_MAYBE_ more than one */
11678 md_undefined_symbol (char *name
)
11680 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
11681 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
11682 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
11683 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
11687 if (symbol_find (name
))
11688 as_bad (_("GOT already in symbol table"));
11689 GOT_symbol
= symbol_new (name
, undefined_section
,
11690 (valueT
) 0, &zero_address_frag
);
11697 /* Round up a section size to the appropriate boundary. */
11700 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
11702 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
11703 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
11705 /* For a.out, force the section size to be aligned. If we don't do
11706 this, BFD will align it for us, but it will not write out the
11707 final bytes of the section. This may be a bug in BFD, but it is
11708 easier to fix it here since that is how the other a.out targets
11712 align
= bfd_get_section_alignment (stdoutput
, segment
);
11713 size
= ((size
+ (1 << align
) - 1) & (-((valueT
) 1 << align
)));
11720 /* On the i386, PC-relative offsets are relative to the start of the
11721 next instruction. That is, the address of the offset, plus its
11722 size, since the offset is always the last part of the insn. */
11725 md_pcrel_from (fixS
*fixP
)
11727 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
11733 s_bss (int ignore ATTRIBUTE_UNUSED
)
11737 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11739 obj_elf_section_change_hook ();
11741 temp
= get_absolute_expression ();
11742 subseg_set (bss_section
, (subsegT
) temp
);
11743 demand_empty_rest_of_line ();
11749 i386_validate_fix (fixS
*fixp
)
11751 if (fixp
->fx_subsy
)
11753 if (fixp
->fx_subsy
== GOT_symbol
)
11755 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
11759 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11760 if (fixp
->fx_tcbit2
)
11761 fixp
->fx_r_type
= (fixp
->fx_tcbit
11762 ? BFD_RELOC_X86_64_REX_GOTPCRELX
11763 : BFD_RELOC_X86_64_GOTPCRELX
);
11766 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
11771 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
11773 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
11775 fixp
->fx_subsy
= 0;
11778 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11779 else if (!object_64bit
)
11781 if (fixp
->fx_r_type
== BFD_RELOC_386_GOT32
11782 && fixp
->fx_tcbit2
)
11783 fixp
->fx_r_type
= BFD_RELOC_386_GOT32X
;
11789 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
11792 bfd_reloc_code_real_type code
;
11794 switch (fixp
->fx_r_type
)
11796 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11797 case BFD_RELOC_SIZE32
:
11798 case BFD_RELOC_SIZE64
:
11799 if (S_IS_DEFINED (fixp
->fx_addsy
)
11800 && !S_IS_EXTERNAL (fixp
->fx_addsy
))
11802 /* Resolve size relocation against local symbol to size of
11803 the symbol plus addend. */
11804 valueT value
= S_GET_SIZE (fixp
->fx_addsy
) + fixp
->fx_offset
;
11805 if (fixp
->fx_r_type
== BFD_RELOC_SIZE32
11806 && !fits_in_unsigned_long (value
))
11807 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
11808 _("symbol size computation overflow"));
11809 fixp
->fx_addsy
= NULL
;
11810 fixp
->fx_subsy
= NULL
;
11811 md_apply_fix (fixp
, (valueT
*) &value
, NULL
);
11815 /* Fall through. */
11817 case BFD_RELOC_X86_64_PLT32
:
11818 case BFD_RELOC_X86_64_GOT32
:
11819 case BFD_RELOC_X86_64_GOTPCREL
:
11820 case BFD_RELOC_X86_64_GOTPCRELX
:
11821 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
11822 case BFD_RELOC_386_PLT32
:
11823 case BFD_RELOC_386_GOT32
:
11824 case BFD_RELOC_386_GOT32X
:
11825 case BFD_RELOC_386_GOTOFF
:
11826 case BFD_RELOC_386_GOTPC
:
11827 case BFD_RELOC_386_TLS_GD
:
11828 case BFD_RELOC_386_TLS_LDM
:
11829 case BFD_RELOC_386_TLS_LDO_32
:
11830 case BFD_RELOC_386_TLS_IE_32
:
11831 case BFD_RELOC_386_TLS_IE
:
11832 case BFD_RELOC_386_TLS_GOTIE
:
11833 case BFD_RELOC_386_TLS_LE_32
:
11834 case BFD_RELOC_386_TLS_LE
:
11835 case BFD_RELOC_386_TLS_GOTDESC
:
11836 case BFD_RELOC_386_TLS_DESC_CALL
:
11837 case BFD_RELOC_X86_64_TLSGD
:
11838 case BFD_RELOC_X86_64_TLSLD
:
11839 case BFD_RELOC_X86_64_DTPOFF32
:
11840 case BFD_RELOC_X86_64_DTPOFF64
:
11841 case BFD_RELOC_X86_64_GOTTPOFF
:
11842 case BFD_RELOC_X86_64_TPOFF32
:
11843 case BFD_RELOC_X86_64_TPOFF64
:
11844 case BFD_RELOC_X86_64_GOTOFF64
:
11845 case BFD_RELOC_X86_64_GOTPC32
:
11846 case BFD_RELOC_X86_64_GOT64
:
11847 case BFD_RELOC_X86_64_GOTPCREL64
:
11848 case BFD_RELOC_X86_64_GOTPC64
:
11849 case BFD_RELOC_X86_64_GOTPLT64
:
11850 case BFD_RELOC_X86_64_PLTOFF64
:
11851 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
11852 case BFD_RELOC_X86_64_TLSDESC_CALL
:
11853 case BFD_RELOC_RVA
:
11854 case BFD_RELOC_VTABLE_ENTRY
:
11855 case BFD_RELOC_VTABLE_INHERIT
:
11857 case BFD_RELOC_32_SECREL
:
11859 code
= fixp
->fx_r_type
;
11861 case BFD_RELOC_X86_64_32S
:
11862 if (!fixp
->fx_pcrel
)
11864 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
11865 code
= fixp
->fx_r_type
;
11868 /* Fall through. */
11870 if (fixp
->fx_pcrel
)
11872 switch (fixp
->fx_size
)
11875 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
11876 _("can not do %d byte pc-relative relocation"),
11878 code
= BFD_RELOC_32_PCREL
;
11880 case 1: code
= BFD_RELOC_8_PCREL
; break;
11881 case 2: code
= BFD_RELOC_16_PCREL
; break;
11882 case 4: code
= BFD_RELOC_32_PCREL
; break;
11884 case 8: code
= BFD_RELOC_64_PCREL
; break;
11890 switch (fixp
->fx_size
)
11893 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
11894 _("can not do %d byte relocation"),
11896 code
= BFD_RELOC_32
;
11898 case 1: code
= BFD_RELOC_8
; break;
11899 case 2: code
= BFD_RELOC_16
; break;
11900 case 4: code
= BFD_RELOC_32
; break;
11902 case 8: code
= BFD_RELOC_64
; break;
11909 if ((code
== BFD_RELOC_32
11910 || code
== BFD_RELOC_32_PCREL
11911 || code
== BFD_RELOC_X86_64_32S
)
11913 && fixp
->fx_addsy
== GOT_symbol
)
11916 code
= BFD_RELOC_386_GOTPC
;
11918 code
= BFD_RELOC_X86_64_GOTPC32
;
11920 if ((code
== BFD_RELOC_64
|| code
== BFD_RELOC_64_PCREL
)
11922 && fixp
->fx_addsy
== GOT_symbol
)
11924 code
= BFD_RELOC_X86_64_GOTPC64
;
11927 rel
= XNEW (arelent
);
11928 rel
->sym_ptr_ptr
= XNEW (asymbol
*);
11929 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
11931 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
11933 if (!use_rela_relocations
)
11935 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
11936 vtable entry to be used in the relocation's section offset. */
11937 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
11938 rel
->address
= fixp
->fx_offset
;
11939 #if defined (OBJ_COFF) && defined (TE_PE)
11940 else if (fixp
->fx_addsy
&& S_IS_WEAK (fixp
->fx_addsy
))
11941 rel
->addend
= fixp
->fx_addnumber
- (S_GET_VALUE (fixp
->fx_addsy
) * 2);
11946 /* Use the rela in 64bit mode. */
11949 if (disallow_64bit_reloc
)
11952 case BFD_RELOC_X86_64_DTPOFF64
:
11953 case BFD_RELOC_X86_64_TPOFF64
:
11954 case BFD_RELOC_64_PCREL
:
11955 case BFD_RELOC_X86_64_GOTOFF64
:
11956 case BFD_RELOC_X86_64_GOT64
:
11957 case BFD_RELOC_X86_64_GOTPCREL64
:
11958 case BFD_RELOC_X86_64_GOTPC64
:
11959 case BFD_RELOC_X86_64_GOTPLT64
:
11960 case BFD_RELOC_X86_64_PLTOFF64
:
11961 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
11962 _("cannot represent relocation type %s in x32 mode"),
11963 bfd_get_reloc_code_name (code
));
11969 if (!fixp
->fx_pcrel
)
11970 rel
->addend
= fixp
->fx_offset
;
11974 case BFD_RELOC_X86_64_PLT32
:
11975 case BFD_RELOC_X86_64_GOT32
:
11976 case BFD_RELOC_X86_64_GOTPCREL
:
11977 case BFD_RELOC_X86_64_GOTPCRELX
:
11978 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
11979 case BFD_RELOC_X86_64_TLSGD
:
11980 case BFD_RELOC_X86_64_TLSLD
:
11981 case BFD_RELOC_X86_64_GOTTPOFF
:
11982 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
11983 case BFD_RELOC_X86_64_TLSDESC_CALL
:
11984 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
11987 rel
->addend
= (section
->vma
11989 + fixp
->fx_addnumber
11990 + md_pcrel_from (fixp
));
11995 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
11996 if (rel
->howto
== NULL
)
11998 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
11999 _("cannot represent relocation type %s"),
12000 bfd_get_reloc_code_name (code
));
12001 /* Set howto to a garbage value so that we can keep going. */
12002 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
12003 gas_assert (rel
->howto
!= NULL
);
12009 #include "tc-i386-intel.c"
12012 tc_x86_parse_to_dw2regnum (expressionS
*exp
)
12014 int saved_naked_reg
;
12015 char saved_register_dot
;
12017 saved_naked_reg
= allow_naked_reg
;
12018 allow_naked_reg
= 1;
12019 saved_register_dot
= register_chars
['.'];
12020 register_chars
['.'] = '.';
12021 allow_pseudo_reg
= 1;
12022 expression_and_evaluate (exp
);
12023 allow_pseudo_reg
= 0;
12024 register_chars
['.'] = saved_register_dot
;
12025 allow_naked_reg
= saved_naked_reg
;
12027 if (exp
->X_op
== O_register
&& exp
->X_add_number
>= 0)
12029 if ((addressT
) exp
->X_add_number
< i386_regtab_size
)
12031 exp
->X_op
= O_constant
;
12032 exp
->X_add_number
= i386_regtab
[exp
->X_add_number
]
12033 .dw2_regnum
[flag_code
>> 1];
12036 exp
->X_op
= O_illegal
;
12041 tc_x86_frame_initial_instructions (void)
12043 static unsigned int sp_regno
[2];
12045 if (!sp_regno
[flag_code
>> 1])
12047 char *saved_input
= input_line_pointer
;
12048 char sp
[][4] = {"esp", "rsp"};
12051 input_line_pointer
= sp
[flag_code
>> 1];
12052 tc_x86_parse_to_dw2regnum (&exp
);
12053 gas_assert (exp
.X_op
== O_constant
);
12054 sp_regno
[flag_code
>> 1] = exp
.X_add_number
;
12055 input_line_pointer
= saved_input
;
12058 cfi_add_CFA_def_cfa (sp_regno
[flag_code
>> 1], -x86_cie_data_alignment
);
12059 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
12063 x86_dwarf2_addr_size (void)
12065 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
12066 if (x86_elf_abi
== X86_64_X32_ABI
)
12069 return bfd_arch_bits_per_address (stdoutput
) / 8;
12073 i386_elf_section_type (const char *str
, size_t len
)
12075 if (flag_code
== CODE_64BIT
12076 && len
== sizeof ("unwind") - 1
12077 && strncmp (str
, "unwind", 6) == 0)
12078 return SHT_X86_64_UNWIND
;
12085 i386_solaris_fix_up_eh_frame (segT sec
)
12087 if (flag_code
== CODE_64BIT
)
12088 elf_section_type (sec
) = SHT_X86_64_UNWIND
;
12094 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
12098 exp
.X_op
= O_secrel
;
12099 exp
.X_add_symbol
= symbol
;
12100 exp
.X_add_number
= 0;
12101 emit_expr (&exp
, size
);
12105 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12106 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
12109 x86_64_section_letter (int letter
, const char **ptr_msg
)
12111 if (flag_code
== CODE_64BIT
)
12114 return SHF_X86_64_LARGE
;
12116 *ptr_msg
= _("bad .section directive: want a,l,w,x,M,S,G,T in string");
12119 *ptr_msg
= _("bad .section directive: want a,w,x,M,S,G,T in string");
12124 x86_64_section_word (char *str
, size_t len
)
12126 if (len
== 5 && flag_code
== CODE_64BIT
&& CONST_STRNEQ (str
, "large"))
12127 return SHF_X86_64_LARGE
;
12133 handle_large_common (int small ATTRIBUTE_UNUSED
)
12135 if (flag_code
!= CODE_64BIT
)
12137 s_comm_internal (0, elf_common_parse
);
12138 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
12142 static segT lbss_section
;
12143 asection
*saved_com_section_ptr
= elf_com_section_ptr
;
12144 asection
*saved_bss_section
= bss_section
;
12146 if (lbss_section
== NULL
)
12148 flagword applicable
;
12149 segT seg
= now_seg
;
12150 subsegT subseg
= now_subseg
;
12152 /* The .lbss section is for local .largecomm symbols. */
12153 lbss_section
= subseg_new (".lbss", 0);
12154 applicable
= bfd_applicable_section_flags (stdoutput
);
12155 bfd_set_section_flags (stdoutput
, lbss_section
,
12156 applicable
& SEC_ALLOC
);
12157 seg_info (lbss_section
)->bss
= 1;
12159 subseg_set (seg
, subseg
);
12162 elf_com_section_ptr
= &_bfd_elf_large_com_section
;
12163 bss_section
= lbss_section
;
12165 s_comm_internal (0, elf_common_parse
);
12167 elf_com_section_ptr
= saved_com_section_ptr
;
12168 bss_section
= saved_bss_section
;
12171 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */