1 /* i386.c -- Assemble code for the Intel 80386
2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005, 2006
4 Free Software Foundation, Inc.
6 This file is part of GAS, the GNU Assembler.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
23 /* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
25 x86_64 support by Jan Hubicka (jh@suse.cz)
26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
27 Bugs & suggestions are completely welcome. This is free software.
28 Please help us make it better. */
31 #include "safe-ctype.h"
33 #include "dwarf2dbg.h"
34 #include "dw2gencfi.h"
35 #include "opcode/i386.h"
36 #include "elf/x86-64.h"
38 #ifndef REGISTER_WARNINGS
39 #define REGISTER_WARNINGS 1
42 #ifndef INFER_ADDR_PREFIX
43 #define INFER_ADDR_PREFIX 1
46 #ifndef SCALE1_WHEN_NO_INDEX
47 /* Specifying a scale factor besides 1 when there is no index is
48 futile. eg. `mov (%ebx,2),%al' does exactly the same as
49 `mov (%ebx),%al'. To slavishly follow what the programmer
50 specified, set SCALE1_WHEN_NO_INDEX to 0. */
51 #define SCALE1_WHEN_NO_INDEX 1
55 #define DEFAULT_ARCH "i386"
60 #define INLINE __inline__
66 static INLINE
unsigned int mode_from_disp_size
PARAMS ((unsigned int));
67 static INLINE
int fits_in_signed_byte
PARAMS ((offsetT
));
68 static INLINE
int fits_in_unsigned_byte
PARAMS ((offsetT
));
69 static INLINE
int fits_in_unsigned_word
PARAMS ((offsetT
));
70 static INLINE
int fits_in_signed_word
PARAMS ((offsetT
));
71 static INLINE
int fits_in_unsigned_long
PARAMS ((offsetT
));
72 static INLINE
int fits_in_signed_long
PARAMS ((offsetT
));
73 static int smallest_imm_type
PARAMS ((offsetT
));
74 static offsetT offset_in_range
PARAMS ((offsetT
, int));
75 static int add_prefix
PARAMS ((unsigned int));
76 static void set_code_flag
PARAMS ((int));
77 static void set_16bit_gcc_code_flag
PARAMS ((int));
78 static void set_intel_syntax
PARAMS ((int));
79 static void set_cpu_arch
PARAMS ((int));
81 static void pe_directive_secrel
PARAMS ((int));
83 static void signed_cons
PARAMS ((int));
84 static char *output_invalid
PARAMS ((int c
));
85 static int i386_operand
PARAMS ((char *operand_string
));
86 static int i386_intel_operand
PARAMS ((char *operand_string
, int got_a_float
));
87 static const reg_entry
*parse_register
PARAMS ((char *reg_string
,
89 static char *parse_insn
PARAMS ((char *, char *));
90 static char *parse_operands
PARAMS ((char *, const char *));
91 static void swap_operands
PARAMS ((void));
92 static void swap_imm_operands
PARAMS ((void));
93 static void optimize_imm
PARAMS ((void));
94 static void optimize_disp
PARAMS ((void));
95 static int match_template
PARAMS ((void));
96 static int check_string
PARAMS ((void));
97 static int process_suffix
PARAMS ((void));
98 static int check_byte_reg
PARAMS ((void));
99 static int check_long_reg
PARAMS ((void));
100 static int check_qword_reg
PARAMS ((void));
101 static int check_word_reg
PARAMS ((void));
102 static int finalize_imm
PARAMS ((void));
103 static int process_operands
PARAMS ((void));
104 static const seg_entry
*build_modrm_byte
PARAMS ((void));
105 static void output_insn
PARAMS ((void));
106 static void output_branch
PARAMS ((void));
107 static void output_jump
PARAMS ((void));
108 static void output_interseg_jump
PARAMS ((void));
109 static void output_imm
PARAMS ((fragS
*insn_start_frag
,
110 offsetT insn_start_off
));
111 static void output_disp
PARAMS ((fragS
*insn_start_frag
,
112 offsetT insn_start_off
));
114 static void s_bss
PARAMS ((int));
116 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
117 static void handle_large_common (int small ATTRIBUTE_UNUSED
);
120 static const char *default_arch
= DEFAULT_ARCH
;
122 /* 'md_assemble ()' gathers together information and puts it into a
129 const reg_entry
*regs
;
134 /* TM holds the template for the insn were currently assembling. */
137 /* SUFFIX holds the instruction mnemonic suffix if given.
138 (e.g. 'l' for 'movl') */
141 /* OPERANDS gives the number of given operands. */
142 unsigned int operands
;
144 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
145 of given register, displacement, memory operands and immediate
147 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
149 /* TYPES [i] is the type (see above #defines) which tells us how to
150 use OP[i] for the corresponding operand. */
151 unsigned int types
[MAX_OPERANDS
];
153 /* Displacement expression, immediate expression, or register for each
155 union i386_op op
[MAX_OPERANDS
];
157 /* Flags for operands. */
158 unsigned int flags
[MAX_OPERANDS
];
159 #define Operand_PCrel 1
161 /* Relocation type for operand */
162 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
164 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
165 the base index byte below. */
166 const reg_entry
*base_reg
;
167 const reg_entry
*index_reg
;
168 unsigned int log2_scale_factor
;
170 /* SEG gives the seg_entries of this insn. They are zero unless
171 explicit segment overrides are given. */
172 const seg_entry
*seg
[2];
174 /* PREFIX holds all the given prefix opcodes (usually null).
175 PREFIXES is the number of prefix opcodes. */
176 unsigned int prefixes
;
177 unsigned char prefix
[MAX_PREFIXES
];
179 /* RM and SIB are the modrm byte and the sib byte where the
180 addressing modes of this insn are encoded. */
187 typedef struct _i386_insn i386_insn
;
189 /* List of chars besides those in app.c:symbol_chars that can start an
190 operand. Used to prevent the scrubber eating vital white-space. */
191 const char extra_symbol_chars
[] = "*%-(["
200 #if (defined (TE_I386AIX) \
201 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
202 && !defined (TE_GNU) \
203 && !defined (TE_LINUX) \
204 && !defined (TE_NETWARE) \
205 && !defined (TE_FreeBSD) \
206 && !defined (TE_NetBSD)))
207 /* This array holds the chars that always start a comment. If the
208 pre-processor is disabled, these aren't very useful. The option
209 --divide will remove '/' from this list. */
210 const char *i386_comment_chars
= "#/";
211 #define SVR4_COMMENT_CHARS 1
212 #define PREFIX_SEPARATOR '\\'
215 const char *i386_comment_chars
= "#";
216 #define PREFIX_SEPARATOR '/'
219 /* This array holds the chars that only start a comment at the beginning of
220 a line. If the line seems to have the form '# 123 filename'
221 .line and .file directives will appear in the pre-processed output.
222 Note that input_file.c hand checks for '#' at the beginning of the
223 first line of the input file. This is because the compiler outputs
224 #NO_APP at the beginning of its output.
225 Also note that comments started like this one will always work if
226 '/' isn't otherwise defined. */
227 const char line_comment_chars
[] = "#/";
229 const char line_separator_chars
[] = ";";
231 /* Chars that can be used to separate mant from exp in floating point
233 const char EXP_CHARS
[] = "eE";
235 /* Chars that mean this number is a floating point constant
238 const char FLT_CHARS
[] = "fFdDxX";
240 /* Tables for lexical analysis. */
241 static char mnemonic_chars
[256];
242 static char register_chars
[256];
243 static char operand_chars
[256];
244 static char identifier_chars
[256];
245 static char digit_chars
[256];
247 /* Lexical macros. */
248 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
249 #define is_operand_char(x) (operand_chars[(unsigned char) x])
250 #define is_register_char(x) (register_chars[(unsigned char) x])
251 #define is_space_char(x) ((x) == ' ')
252 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
253 #define is_digit_char(x) (digit_chars[(unsigned char) x])
255 /* All non-digit non-letter characters that may occur in an operand. */
256 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
258 /* md_assemble() always leaves the strings it's passed unaltered. To
259 effect this we maintain a stack of saved characters that we've smashed
260 with '\0's (indicating end of strings for various sub-fields of the
261 assembler instruction). */
262 static char save_stack
[32];
263 static char *save_stack_p
;
264 #define END_STRING_AND_SAVE(s) \
265 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
266 #define RESTORE_END_STRING(s) \
267 do { *(s) = *--save_stack_p; } while (0)
269 /* The instruction we're assembling. */
272 /* Possible templates for current insn. */
273 static const templates
*current_templates
;
275 /* Per instruction expressionS buffers: 2 displacements & 2 immediate max. */
276 static expressionS disp_expressions
[2], im_expressions
[2];
278 /* Current operand we are working on. */
279 static int this_operand
;
281 /* We support four different modes. FLAG_CODE variable is used to distinguish
288 #define NUM_FLAG_CODE ((int) CODE_64BIT + 1)
290 static enum flag_code flag_code
;
291 static unsigned int object_64bit
;
292 static int use_rela_relocations
= 0;
294 /* The names used to print error messages. */
295 static const char *flag_code_names
[] =
302 /* 1 for intel syntax,
304 static int intel_syntax
= 0;
306 /* 1 if register prefix % not required. */
307 static int allow_naked_reg
= 0;
309 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
310 leave, push, and pop instructions so that gcc has the same stack
311 frame as in 32 bit mode. */
312 static char stackop_size
= '\0';
314 /* Non-zero to optimize code alignment. */
315 int optimize_align_code
= 1;
317 /* Non-zero to quieten some warnings. */
318 static int quiet_warnings
= 0;
321 static const char *cpu_arch_name
= NULL
;
322 static const char *cpu_sub_arch_name
= NULL
;
324 /* CPU feature flags. */
325 static unsigned int cpu_arch_flags
= CpuUnknownFlags
| CpuNo64
;
327 /* If we have selected a cpu we are generating instructions for. */
328 static int cpu_arch_tune_set
= 0;
330 /* Cpu we are generating instructions for. */
331 static enum processor_type cpu_arch_tune
= PROCESSOR_UNKNOWN
;
333 /* CPU feature flags of cpu we are generating instructions for. */
334 static unsigned int cpu_arch_tune_flags
= 0;
336 /* CPU instruction set architecture used. */
337 static enum processor_type cpu_arch_isa
= PROCESSOR_UNKNOWN
;
339 /* CPU feature flags of instruction set architecture used. */
340 static unsigned int cpu_arch_isa_flags
= 0;
342 /* If set, conditional jumps are not automatically promoted to handle
343 larger than a byte offset. */
344 static unsigned int no_cond_jump_promotion
= 0;
346 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
347 static symbolS
*GOT_symbol
;
349 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
350 unsigned int x86_dwarf2_return_column
;
352 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
353 int x86_cie_data_alignment
;
355 /* Interface to relax_segment.
356 There are 3 major relax states for 386 jump insns because the
357 different types of jumps add different sizes to frags when we're
358 figuring out what sort of jump to choose to reach a given label. */
361 #define UNCOND_JUMP 0
363 #define COND_JUMP86 2
368 #define SMALL16 (SMALL | CODE16)
370 #define BIG16 (BIG | CODE16)
374 #define INLINE __inline__
380 #define ENCODE_RELAX_STATE(type, size) \
381 ((relax_substateT) (((type) << 2) | (size)))
382 #define TYPE_FROM_RELAX_STATE(s) \
384 #define DISP_SIZE_FROM_RELAX_STATE(s) \
385 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
387 /* This table is used by relax_frag to promote short jumps to long
388 ones where necessary. SMALL (short) jumps may be promoted to BIG
389 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
390 don't allow a short jump in a 32 bit code segment to be promoted to
391 a 16 bit offset jump because it's slower (requires data size
392 prefix), and doesn't work, unless the destination is in the bottom
393 64k of the code segment (The top 16 bits of eip are zeroed). */
395 const relax_typeS md_relax_table
[] =
398 1) most positive reach of this state,
399 2) most negative reach of this state,
400 3) how many bytes this mode will have in the variable part of the frag
401 4) which index into the table to try if we can't fit into this one. */
403 /* UNCOND_JUMP states. */
404 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
405 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
406 /* dword jmp adds 4 bytes to frag:
407 0 extra opcode bytes, 4 displacement bytes. */
409 /* word jmp adds 2 byte2 to frag:
410 0 extra opcode bytes, 2 displacement bytes. */
413 /* COND_JUMP states. */
414 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
415 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
416 /* dword conditionals adds 5 bytes to frag:
417 1 extra opcode byte, 4 displacement bytes. */
419 /* word conditionals add 3 bytes to frag:
420 1 extra opcode byte, 2 displacement bytes. */
423 /* COND_JUMP86 states. */
424 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
425 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
426 /* dword conditionals adds 5 bytes to frag:
427 1 extra opcode byte, 4 displacement bytes. */
429 /* word conditionals add 4 bytes to frag:
430 1 displacement byte and a 3 byte long branch insn. */
434 static const arch_entry cpu_arch
[] =
436 {"generic32", PROCESSOR_GENERIC32
,
437 Cpu186
|Cpu286
|Cpu386
},
438 {"generic64", PROCESSOR_GENERIC64
,
439 Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuP4
|CpuMMX
440 |CpuMMX2
|CpuSSE
|CpuSSE2
},
441 {"i8086", PROCESSOR_UNKNOWN
,
443 {"i186", PROCESSOR_UNKNOWN
,
445 {"i286", PROCESSOR_UNKNOWN
,
447 {"i386", PROCESSOR_GENERIC32
,
448 Cpu186
|Cpu286
|Cpu386
},
449 {"i486", PROCESSOR_I486
,
450 Cpu186
|Cpu286
|Cpu386
|Cpu486
},
451 {"i586", PROCESSOR_PENTIUM
,
452 Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
},
453 {"i686", PROCESSOR_PENTIUMPRO
,
454 Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
},
455 {"pentium", PROCESSOR_PENTIUM
,
456 Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
},
457 {"pentiumpro",PROCESSOR_PENTIUMPRO
,
458 Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
},
459 {"pentiumii", PROCESSOR_PENTIUMPRO
,
460 Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuMMX
},
461 {"pentiumiii",PROCESSOR_PENTIUMPRO
,
462 Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuMMX
|CpuMMX2
|CpuSSE
},
463 {"pentium4", PROCESSOR_PENTIUM4
,
464 Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuP4
|CpuMMX
465 |CpuMMX2
|CpuSSE
|CpuSSE2
},
466 {"prescott", PROCESSOR_NOCONA
,
467 Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuP4
|CpuMMX
468 |CpuMMX2
|CpuSSE
|CpuSSE2
|CpuSSE3
},
469 {"nocona", PROCESSOR_NOCONA
,
470 Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuP4
|CpuMMX
471 |CpuMMX2
|CpuSSE
|CpuSSE2
|CpuSSE3
},
472 {"yonah", PROCESSOR_CORE
,
473 Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuP4
|CpuMMX
474 |CpuMMX2
|CpuSSE
|CpuSSE2
|CpuSSE3
},
475 {"core", PROCESSOR_CORE
,
476 Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuP4
|CpuMMX
477 |CpuMMX2
|CpuSSE
|CpuSSE2
|CpuSSE3
},
478 {"merom", PROCESSOR_CORE2
,
479 Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuP4
|CpuMMX
480 |CpuMMX2
|CpuSSE
|CpuSSE2
|CpuSSE3
|CpuSSSE3
},
481 {"core2", PROCESSOR_CORE2
,
482 Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuP4
|CpuMMX
483 |CpuMMX2
|CpuSSE
|CpuSSE2
|CpuSSE3
|CpuSSSE3
},
485 Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|CpuK6
|CpuMMX
},
486 {"k6_2", PROCESSOR_K6
,
487 Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|CpuK6
|CpuMMX
|Cpu3dnow
},
488 {"athlon", PROCESSOR_ATHLON
,
489 Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuK6
490 |CpuMMX
|CpuMMX2
|Cpu3dnow
|Cpu3dnowA
},
491 {"sledgehammer", PROCESSOR_K8
,
492 Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuK6
493 |CpuSledgehammer
|CpuMMX
|CpuMMX2
|Cpu3dnow
|Cpu3dnowA
|CpuSSE
|CpuSSE2
},
494 {"opteron", PROCESSOR_K8
,
495 Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuK6
496 |CpuSledgehammer
|CpuMMX
|CpuMMX2
|Cpu3dnow
|Cpu3dnowA
|CpuSSE
|CpuSSE2
},
498 Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuK6
499 |CpuSledgehammer
|CpuMMX
|CpuMMX2
|Cpu3dnow
|Cpu3dnowA
|CpuSSE
|CpuSSE2
},
500 {"amdfam10", PROCESSOR_AMDFAM10
,
501 Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuK6
|CpuSledgehammer
502 |CpuMMX
|CpuMMX2
|Cpu3dnow
|Cpu3dnowA
|CpuSSE
|CpuSSE2
|CpuSSE3
|CpuSSE4a
504 {".mmx", PROCESSOR_UNKNOWN
,
506 {".sse", PROCESSOR_UNKNOWN
,
507 CpuMMX
|CpuMMX2
|CpuSSE
},
508 {".sse2", PROCESSOR_UNKNOWN
,
509 CpuMMX
|CpuMMX2
|CpuSSE
|CpuSSE2
},
510 {".sse3", PROCESSOR_UNKNOWN
,
511 CpuMMX
|CpuMMX2
|CpuSSE
|CpuSSE2
|CpuSSE3
},
512 {".ssse3", PROCESSOR_UNKNOWN
,
513 CpuMMX
|CpuMMX2
|CpuSSE
|CpuSSE2
|CpuSSE3
|CpuSSSE3
},
514 {".3dnow", PROCESSOR_UNKNOWN
,
516 {".3dnowa", PROCESSOR_UNKNOWN
,
517 CpuMMX
|CpuMMX2
|Cpu3dnow
|Cpu3dnowA
},
518 {".padlock", PROCESSOR_UNKNOWN
,
520 {".pacifica", PROCESSOR_UNKNOWN
,
522 {".svme", PROCESSOR_UNKNOWN
,
524 {".sse4a", PROCESSOR_UNKNOWN
,
525 CpuMMX
|CpuMMX2
|CpuSSE
|CpuSSE2
|CpuSSE3
|CpuSSE4a
},
526 {".abm", PROCESSOR_UNKNOWN
,
530 const pseudo_typeS md_pseudo_table
[] =
532 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
533 {"align", s_align_bytes
, 0},
535 {"align", s_align_ptwo
, 0},
537 {"arch", set_cpu_arch
, 0},
541 {"ffloat", float_cons
, 'f'},
542 {"dfloat", float_cons
, 'd'},
543 {"tfloat", float_cons
, 'x'},
545 {"slong", signed_cons
, 4},
546 {"noopt", s_ignore
, 0},
547 {"optim", s_ignore
, 0},
548 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
549 {"code16", set_code_flag
, CODE_16BIT
},
550 {"code32", set_code_flag
, CODE_32BIT
},
551 {"code64", set_code_flag
, CODE_64BIT
},
552 {"intel_syntax", set_intel_syntax
, 1},
553 {"att_syntax", set_intel_syntax
, 0},
554 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
555 {"largecomm", handle_large_common
, 0},
557 {"file", (void (*) PARAMS ((int))) dwarf2_directive_file
, 0},
558 {"loc", dwarf2_directive_loc
, 0},
559 {"loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0},
562 {"secrel32", pe_directive_secrel
, 0},
567 /* For interface with expression (). */
568 extern char *input_line_pointer
;
570 /* Hash table for instruction mnemonic lookup. */
571 static struct hash_control
*op_hash
;
573 /* Hash table for register lookup. */
574 static struct hash_control
*reg_hash
;
577 i386_align_code (fragP
, count
)
581 /* Various efficient no-op patterns for aligning code labels.
582 Note: Don't try to assemble the instructions in the comments.
583 0L and 0w are not legal. */
584 static const char f32_1
[] =
586 static const char f32_2
[] =
587 {0x66,0x90}; /* xchg %ax,%ax */
588 static const char f32_3
[] =
589 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
590 static const char f32_4
[] =
591 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
592 static const char f32_5
[] =
594 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
595 static const char f32_6
[] =
596 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
597 static const char f32_7
[] =
598 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
599 static const char f32_8
[] =
601 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
602 static const char f32_9
[] =
603 {0x89,0xf6, /* movl %esi,%esi */
604 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
605 static const char f32_10
[] =
606 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
607 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
608 static const char f32_11
[] =
609 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
610 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
611 static const char f32_12
[] =
612 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
613 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
614 static const char f32_13
[] =
615 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
616 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
617 static const char f32_14
[] =
618 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
619 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
620 static const char f32_15
[] =
621 {0xeb,0x0d,0x90,0x90,0x90,0x90,0x90, /* jmp .+15; lotsa nops */
622 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
623 static const char f16_3
[] =
624 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
625 static const char f16_4
[] =
626 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
627 static const char f16_5
[] =
629 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
630 static const char f16_6
[] =
631 {0x89,0xf6, /* mov %si,%si */
632 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
633 static const char f16_7
[] =
634 {0x8d,0x74,0x00, /* lea 0(%si),%si */
635 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
636 static const char f16_8
[] =
637 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
638 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
639 static const char *const f32_patt
[] = {
640 f32_1
, f32_2
, f32_3
, f32_4
, f32_5
, f32_6
, f32_7
, f32_8
,
641 f32_9
, f32_10
, f32_11
, f32_12
, f32_13
, f32_14
, f32_15
643 static const char *const f16_patt
[] = {
644 f32_1
, f32_2
, f16_3
, f16_4
, f16_5
, f16_6
, f16_7
, f16_8
,
645 f32_15
, f32_15
, f32_15
, f32_15
, f32_15
, f32_15
, f32_15
648 static const char alt_3
[] =
650 /* nopl 0(%[re]ax) */
651 static const char alt_4
[] =
652 {0x0f,0x1f,0x40,0x00};
653 /* nopl 0(%[re]ax,%[re]ax,1) */
654 static const char alt_5
[] =
655 {0x0f,0x1f,0x44,0x00,0x00};
656 /* nopw 0(%[re]ax,%[re]ax,1) */
657 static const char alt_6
[] =
658 {0x66,0x0f,0x1f,0x44,0x00,0x00};
659 /* nopl 0L(%[re]ax) */
660 static const char alt_7
[] =
661 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
662 /* nopl 0L(%[re]ax,%[re]ax,1) */
663 static const char alt_8
[] =
664 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
665 /* nopw 0L(%[re]ax,%[re]ax,1) */
666 static const char alt_9
[] =
667 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
668 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
669 static const char alt_10
[] =
670 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
672 nopw %cs:0L(%[re]ax,%[re]ax,1) */
673 static const char alt_long_11
[] =
675 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
678 nopw %cs:0L(%[re]ax,%[re]ax,1) */
679 static const char alt_long_12
[] =
682 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
686 nopw %cs:0L(%[re]ax,%[re]ax,1) */
687 static const char alt_long_13
[] =
691 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
696 nopw %cs:0L(%[re]ax,%[re]ax,1) */
697 static const char alt_long_14
[] =
702 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
708 nopw %cs:0L(%[re]ax,%[re]ax,1) */
709 static const char alt_long_15
[] =
715 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
716 /* nopl 0(%[re]ax,%[re]ax,1)
717 nopw 0(%[re]ax,%[re]ax,1) */
718 static const char alt_short_11
[] =
719 {0x0f,0x1f,0x44,0x00,0x00,
720 0x66,0x0f,0x1f,0x44,0x00,0x00};
721 /* nopw 0(%[re]ax,%[re]ax,1)
722 nopw 0(%[re]ax,%[re]ax,1) */
723 static const char alt_short_12
[] =
724 {0x66,0x0f,0x1f,0x44,0x00,0x00,
725 0x66,0x0f,0x1f,0x44,0x00,0x00};
726 /* nopw 0(%[re]ax,%[re]ax,1)
728 static const char alt_short_13
[] =
729 {0x66,0x0f,0x1f,0x44,0x00,0x00,
730 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
733 static const char alt_short_14
[] =
734 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
735 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
737 nopl 0L(%[re]ax,%[re]ax,1) */
738 static const char alt_short_15
[] =
739 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
740 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
741 static const char *const alt_short_patt
[] = {
742 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
743 alt_9
, alt_10
, alt_short_11
, alt_short_12
, alt_short_13
,
744 alt_short_14
, alt_short_15
746 static const char *const alt_long_patt
[] = {
747 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
748 alt_9
, alt_10
, alt_long_11
, alt_long_12
, alt_long_13
,
749 alt_long_14
, alt_long_15
752 if (count
<= 0 || count
> 15)
755 /* We need to decide which NOP sequence to use for 32bit and
756 64bit. When -mtune= is used:
758 1. For PROCESSOR_I486, PROCESSOR_PENTIUM and PROCESSOR_GENERIC32,
759 f32_patt will be used.
760 2. For PROCESSOR_K8 and PROCESSOR_AMDFAM10 in 64bit, NOPs with 0x66 prefix will be used.
761 3. For PROCESSOR_CORE2, alt_long_patt will be used.
762 4. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
763 PROCESSOR_CORE, PROCESSOR_CORE2, PROCESSOR_K6, PROCESSOR_ATHLON
764 and PROCESSOR_GENERIC64, alt_short_patt will be used.
766 When -mtune= isn't used, alt_short_patt will be used if
767 cpu_arch_isa_flags has Cpu686. Otherwise, f32_patt will be used.
769 When -march= or .arch is used, we can't use anything beyond
770 cpu_arch_isa_flags. */
772 if (flag_code
== CODE_16BIT
)
774 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
775 f16_patt
[count
- 1], count
);
777 /* Adjust jump offset. */
778 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
780 else if (flag_code
== CODE_64BIT
&& cpu_arch_tune
== PROCESSOR_K8
)
783 int nnops
= (count
+ 3) / 4;
784 int len
= count
/ nnops
;
785 int remains
= count
- nnops
* len
;
788 /* The recommended way to pad 64bit code is to use NOPs preceded
789 by maximally four 0x66 prefixes. Balance the size of nops. */
790 for (i
= 0; i
< remains
; i
++)
792 memset (fragP
->fr_literal
+ fragP
->fr_fix
+ pos
, 0x66, len
);
793 fragP
->fr_literal
[fragP
->fr_fix
+ pos
+ len
] = 0x90;
796 for (; i
< nnops
; i
++)
798 memset (fragP
->fr_literal
+ fragP
->fr_fix
+ pos
, 0x66, len
- 1);
799 fragP
->fr_literal
[fragP
->fr_fix
+ pos
+ len
- 1] = 0x90;
805 const char *const *patt
= NULL
;
807 if (cpu_arch_isa
== PROCESSOR_UNKNOWN
)
809 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
810 switch (cpu_arch_tune
)
812 case PROCESSOR_UNKNOWN
:
813 /* We use cpu_arch_isa_flags to check if we SHOULD
814 optimize for Cpu686. */
815 if ((cpu_arch_isa_flags
& Cpu686
) != 0)
816 patt
= alt_short_patt
;
820 case PROCESSOR_CORE2
:
821 patt
= alt_long_patt
;
823 case PROCESSOR_PENTIUMPRO
:
824 case PROCESSOR_PENTIUM4
:
825 case PROCESSOR_NOCONA
:
828 case PROCESSOR_ATHLON
:
830 case PROCESSOR_GENERIC64
:
831 case PROCESSOR_AMDFAM10
:
832 patt
= alt_short_patt
;
835 case PROCESSOR_PENTIUM
:
836 case PROCESSOR_GENERIC32
:
843 switch (cpu_arch_tune
)
845 case PROCESSOR_UNKNOWN
:
846 /* When cpu_arch_isa is net, cpu_arch_tune shouldn't be
847 PROCESSOR_UNKNOWN. */
852 case PROCESSOR_PENTIUM
:
853 case PROCESSOR_PENTIUMPRO
:
854 case PROCESSOR_PENTIUM4
:
855 case PROCESSOR_NOCONA
:
858 case PROCESSOR_ATHLON
:
860 case PROCESSOR_AMDFAM10
:
861 case PROCESSOR_GENERIC32
:
862 /* We use cpu_arch_isa_flags to check if we CAN optimize
864 if ((cpu_arch_isa_flags
& Cpu686
) != 0)
865 patt
= alt_short_patt
;
869 case PROCESSOR_CORE2
:
870 if ((cpu_arch_isa_flags
& Cpu686
) != 0)
871 patt
= alt_long_patt
;
875 case PROCESSOR_GENERIC64
:
876 patt
= alt_short_patt
;
881 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
882 patt
[count
- 1], count
);
884 fragP
->fr_var
= count
;
887 static INLINE
unsigned int
888 mode_from_disp_size (t
)
891 return (t
& Disp8
) ? 1 : (t
& (Disp16
| Disp32
| Disp32S
)) ? 2 : 0;
895 fits_in_signed_byte (num
)
898 return (num
>= -128) && (num
<= 127);
902 fits_in_unsigned_byte (num
)
905 return (num
& 0xff) == num
;
909 fits_in_unsigned_word (num
)
912 return (num
& 0xffff) == num
;
916 fits_in_signed_word (num
)
919 return (-32768 <= num
) && (num
<= 32767);
922 fits_in_signed_long (num
)
923 offsetT num ATTRIBUTE_UNUSED
;
928 return (!(((offsetT
) -1 << 31) & num
)
929 || (((offsetT
) -1 << 31) & num
) == ((offsetT
) -1 << 31));
931 } /* fits_in_signed_long() */
933 fits_in_unsigned_long (num
)
934 offsetT num ATTRIBUTE_UNUSED
;
939 return (num
& (((offsetT
) 2 << 31) - 1)) == num
;
941 } /* fits_in_unsigned_long() */
944 smallest_imm_type (num
)
947 if (cpu_arch_flags
!= (Cpu186
| Cpu286
| Cpu386
| Cpu486
| CpuNo64
))
949 /* This code is disabled on the 486 because all the Imm1 forms
950 in the opcode table are slower on the i486. They're the
951 versions with the implicitly specified single-position
952 displacement, which has another syntax if you really want to
955 return Imm1
| Imm8
| Imm8S
| Imm16
| Imm32
| Imm32S
| Imm64
;
957 return (fits_in_signed_byte (num
)
958 ? (Imm8S
| Imm8
| Imm16
| Imm32
| Imm32S
| Imm64
)
959 : fits_in_unsigned_byte (num
)
960 ? (Imm8
| Imm16
| Imm32
| Imm32S
| Imm64
)
961 : (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
962 ? (Imm16
| Imm32
| Imm32S
| Imm64
)
963 : fits_in_signed_long (num
)
964 ? (Imm32
| Imm32S
| Imm64
)
965 : fits_in_unsigned_long (num
)
971 offset_in_range (val
, size
)
979 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
980 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
981 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
983 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
988 /* If BFD64, sign extend val. */
989 if (!use_rela_relocations
)
990 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
991 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
993 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
995 char buf1
[40], buf2
[40];
997 sprint_value (buf1
, val
);
998 sprint_value (buf2
, val
& mask
);
999 as_warn (_("%s shortened to %s"), buf1
, buf2
);
1004 /* Returns 0 if attempting to add a prefix where one from the same
1005 class already exists, 1 if non rep/repne added, 2 if rep/repne
1009 unsigned int prefix
;
1014 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
1015 && flag_code
== CODE_64BIT
)
1017 if ((i
.prefix
[REX_PREFIX
] & prefix
& REX_MODE64
)
1018 || ((i
.prefix
[REX_PREFIX
] & (REX_EXTX
| REX_EXTY
| REX_EXTZ
))
1019 && (prefix
& (REX_EXTX
| REX_EXTY
| REX_EXTZ
))))
1030 case CS_PREFIX_OPCODE
:
1031 case DS_PREFIX_OPCODE
:
1032 case ES_PREFIX_OPCODE
:
1033 case FS_PREFIX_OPCODE
:
1034 case GS_PREFIX_OPCODE
:
1035 case SS_PREFIX_OPCODE
:
1039 case REPNE_PREFIX_OPCODE
:
1040 case REPE_PREFIX_OPCODE
:
1043 case LOCK_PREFIX_OPCODE
:
1051 case ADDR_PREFIX_OPCODE
:
1055 case DATA_PREFIX_OPCODE
:
1059 if (i
.prefix
[q
] != 0)
1067 i
.prefix
[q
] |= prefix
;
1070 as_bad (_("same type of prefix used twice"));
1076 set_code_flag (value
)
1080 cpu_arch_flags
&= ~(Cpu64
| CpuNo64
);
1081 cpu_arch_flags
|= (flag_code
== CODE_64BIT
? Cpu64
: CpuNo64
);
1082 if (value
== CODE_64BIT
&& !(cpu_arch_flags
& CpuSledgehammer
))
1084 as_bad (_("64bit mode not supported on this CPU."));
1086 if (value
== CODE_32BIT
&& !(cpu_arch_flags
& Cpu386
))
1088 as_bad (_("32bit mode not supported on this CPU."));
1090 stackop_size
= '\0';
1094 set_16bit_gcc_code_flag (new_code_flag
)
1097 flag_code
= new_code_flag
;
1098 cpu_arch_flags
&= ~(Cpu64
| CpuNo64
);
1099 cpu_arch_flags
|= (flag_code
== CODE_64BIT
? Cpu64
: CpuNo64
);
1100 stackop_size
= LONG_MNEM_SUFFIX
;
1104 set_intel_syntax (syntax_flag
)
1107 /* Find out if register prefixing is specified. */
1108 int ask_naked_reg
= 0;
1111 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
1113 char *string
= input_line_pointer
;
1114 int e
= get_symbol_end ();
1116 if (strcmp (string
, "prefix") == 0)
1118 else if (strcmp (string
, "noprefix") == 0)
1121 as_bad (_("bad argument to syntax directive."));
1122 *input_line_pointer
= e
;
1124 demand_empty_rest_of_line ();
1126 intel_syntax
= syntax_flag
;
1128 if (ask_naked_reg
== 0)
1129 allow_naked_reg
= (intel_syntax
1130 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
1132 allow_naked_reg
= (ask_naked_reg
< 0);
1134 identifier_chars
['%'] = intel_syntax
&& allow_naked_reg
? '%' : 0;
1135 identifier_chars
['$'] = intel_syntax
? '$' : 0;
1139 set_cpu_arch (dummy
)
1140 int dummy ATTRIBUTE_UNUSED
;
1144 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
1146 char *string
= input_line_pointer
;
1147 int e
= get_symbol_end ();
1150 for (i
= 0; i
< ARRAY_SIZE (cpu_arch
); i
++)
1152 if (strcmp (string
, cpu_arch
[i
].name
) == 0)
1156 cpu_arch_name
= cpu_arch
[i
].name
;
1157 cpu_sub_arch_name
= NULL
;
1158 cpu_arch_flags
= (cpu_arch
[i
].flags
1159 | (flag_code
== CODE_64BIT
? Cpu64
: CpuNo64
));
1160 cpu_arch_isa
= cpu_arch
[i
].type
;
1161 cpu_arch_isa_flags
= cpu_arch
[i
].flags
;
1162 if (!cpu_arch_tune_set
)
1164 cpu_arch_tune
= cpu_arch_isa
;
1165 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
1169 if ((cpu_arch_flags
| cpu_arch
[i
].flags
) != cpu_arch_flags
)
1171 cpu_sub_arch_name
= cpu_arch
[i
].name
;
1172 cpu_arch_flags
|= cpu_arch
[i
].flags
;
1174 *input_line_pointer
= e
;
1175 demand_empty_rest_of_line ();
1179 if (i
>= ARRAY_SIZE (cpu_arch
))
1180 as_bad (_("no such architecture: `%s'"), string
);
1182 *input_line_pointer
= e
;
1185 as_bad (_("missing cpu architecture"));
1187 no_cond_jump_promotion
= 0;
1188 if (*input_line_pointer
== ','
1189 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
1191 char *string
= ++input_line_pointer
;
1192 int e
= get_symbol_end ();
1194 if (strcmp (string
, "nojumps") == 0)
1195 no_cond_jump_promotion
= 1;
1196 else if (strcmp (string
, "jumps") == 0)
1199 as_bad (_("no such architecture modifier: `%s'"), string
);
1201 *input_line_pointer
= e
;
1204 demand_empty_rest_of_line ();
1210 if (!strcmp (default_arch
, "x86_64"))
1211 return bfd_mach_x86_64
;
1212 else if (!strcmp (default_arch
, "i386"))
1213 return bfd_mach_i386_i386
;
1215 as_fatal (_("Unknown architecture"));
1221 const char *hash_err
;
1223 /* Initialize op_hash hash table. */
1224 op_hash
= hash_new ();
1227 const template *optab
;
1228 templates
*core_optab
;
1230 /* Setup for loop. */
1232 core_optab
= (templates
*) xmalloc (sizeof (templates
));
1233 core_optab
->start
= optab
;
1238 if (optab
->name
== NULL
1239 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
1241 /* different name --> ship out current template list;
1242 add to hash table; & begin anew. */
1243 core_optab
->end
= optab
;
1244 hash_err
= hash_insert (op_hash
,
1249 as_fatal (_("Internal Error: Can't hash %s: %s"),
1253 if (optab
->name
== NULL
)
1255 core_optab
= (templates
*) xmalloc (sizeof (templates
));
1256 core_optab
->start
= optab
;
1261 /* Initialize reg_hash hash table. */
1262 reg_hash
= hash_new ();
1264 const reg_entry
*regtab
;
1266 for (regtab
= i386_regtab
;
1267 regtab
< i386_regtab
+ sizeof (i386_regtab
) / sizeof (i386_regtab
[0]);
1270 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (PTR
) regtab
);
1272 as_fatal (_("Internal Error: Can't hash %s: %s"),
1278 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
1283 for (c
= 0; c
< 256; c
++)
1288 mnemonic_chars
[c
] = c
;
1289 register_chars
[c
] = c
;
1290 operand_chars
[c
] = c
;
1292 else if (ISLOWER (c
))
1294 mnemonic_chars
[c
] = c
;
1295 register_chars
[c
] = c
;
1296 operand_chars
[c
] = c
;
1298 else if (ISUPPER (c
))
1300 mnemonic_chars
[c
] = TOLOWER (c
);
1301 register_chars
[c
] = mnemonic_chars
[c
];
1302 operand_chars
[c
] = c
;
1305 if (ISALPHA (c
) || ISDIGIT (c
))
1306 identifier_chars
[c
] = c
;
1309 identifier_chars
[c
] = c
;
1310 operand_chars
[c
] = c
;
1315 identifier_chars
['@'] = '@';
1318 identifier_chars
['?'] = '?';
1319 operand_chars
['?'] = '?';
1321 digit_chars
['-'] = '-';
1322 mnemonic_chars
['-'] = '-';
1323 identifier_chars
['_'] = '_';
1324 identifier_chars
['.'] = '.';
1326 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
1327 operand_chars
[(unsigned char) *p
] = *p
;
1330 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1333 record_alignment (text_section
, 2);
1334 record_alignment (data_section
, 2);
1335 record_alignment (bss_section
, 2);
1339 if (flag_code
== CODE_64BIT
)
1341 x86_dwarf2_return_column
= 16;
1342 x86_cie_data_alignment
= -8;
1346 x86_dwarf2_return_column
= 8;
1347 x86_cie_data_alignment
= -4;
1352 i386_print_statistics (file
)
1355 hash_print_statistics (file
, "i386 opcode", op_hash
);
1356 hash_print_statistics (file
, "i386 register", reg_hash
);
1361 /* Debugging routines for md_assemble. */
1362 static void pi
PARAMS ((char *, i386_insn
*));
1363 static void pte
PARAMS ((template *));
1364 static void pt
PARAMS ((unsigned int));
1365 static void pe
PARAMS ((expressionS
*));
1366 static void ps
PARAMS ((symbolS
*));
1375 fprintf (stdout
, "%s: template ", line
);
1377 fprintf (stdout
, " address: base %s index %s scale %x\n",
1378 x
->base_reg
? x
->base_reg
->reg_name
: "none",
1379 x
->index_reg
? x
->index_reg
->reg_name
: "none",
1380 x
->log2_scale_factor
);
1381 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
1382 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
1383 fprintf (stdout
, " sib: base %x index %x scale %x\n",
1384 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
1385 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
1386 (x
->rex
& REX_MODE64
) != 0,
1387 (x
->rex
& REX_EXTX
) != 0,
1388 (x
->rex
& REX_EXTY
) != 0,
1389 (x
->rex
& REX_EXTZ
) != 0);
1390 for (i
= 0; i
< x
->operands
; i
++)
1392 fprintf (stdout
, " #%d: ", i
+ 1);
1394 fprintf (stdout
, "\n");
1396 & (Reg
| SReg2
| SReg3
| Control
| Debug
| Test
| RegMMX
| RegXMM
))
1397 fprintf (stdout
, "%s\n", x
->op
[i
].regs
->reg_name
);
1398 if (x
->types
[i
] & Imm
)
1400 if (x
->types
[i
] & Disp
)
1401 pe (x
->op
[i
].disps
);
1410 fprintf (stdout
, " %d operands ", t
->operands
);
1411 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
1412 if (t
->extension_opcode
!= None
)
1413 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
1414 if (t
->opcode_modifier
& D
)
1415 fprintf (stdout
, "D");
1416 if (t
->opcode_modifier
& W
)
1417 fprintf (stdout
, "W");
1418 fprintf (stdout
, "\n");
1419 for (i
= 0; i
< t
->operands
; i
++)
1421 fprintf (stdout
, " #%d type ", i
+ 1);
1422 pt (t
->operand_types
[i
]);
1423 fprintf (stdout
, "\n");
1431 fprintf (stdout
, " operation %d\n", e
->X_op
);
1432 fprintf (stdout
, " add_number %ld (%lx)\n",
1433 (long) e
->X_add_number
, (long) e
->X_add_number
);
1434 if (e
->X_add_symbol
)
1436 fprintf (stdout
, " add_symbol ");
1437 ps (e
->X_add_symbol
);
1438 fprintf (stdout
, "\n");
1442 fprintf (stdout
, " op_symbol ");
1443 ps (e
->X_op_symbol
);
1444 fprintf (stdout
, "\n");
1452 fprintf (stdout
, "%s type %s%s",
1454 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
1455 segment_name (S_GET_SEGMENT (s
)));
1458 static struct type_name
1463 const type_names
[] =
1476 { BaseIndex
, "BaseIndex" },
1480 { Disp32S
, "d32s" },
1482 { InOutPortReg
, "InOutPortReg" },
1483 { ShiftCount
, "ShiftCount" },
1484 { Control
, "control reg" },
1485 { Test
, "test reg" },
1486 { Debug
, "debug reg" },
1487 { FloatReg
, "FReg" },
1488 { FloatAcc
, "FAcc" },
1492 { JumpAbsolute
, "Jump Absolute" },
1503 const struct type_name
*ty
;
1505 for (ty
= type_names
; ty
->mask
; ty
++)
1507 fprintf (stdout
, "%s, ", ty
->tname
);
1511 #endif /* DEBUG386 */
1513 static bfd_reloc_code_real_type
1514 reloc (unsigned int size
,
1517 bfd_reloc_code_real_type other
)
1519 if (other
!= NO_RELOC
)
1521 reloc_howto_type
*reloc
;
1526 case BFD_RELOC_X86_64_GOT32
:
1527 return BFD_RELOC_X86_64_GOT64
;
1529 case BFD_RELOC_X86_64_PLTOFF64
:
1530 return BFD_RELOC_X86_64_PLTOFF64
;
1532 case BFD_RELOC_X86_64_GOTPC32
:
1533 other
= BFD_RELOC_X86_64_GOTPC64
;
1535 case BFD_RELOC_X86_64_GOTPCREL
:
1536 other
= BFD_RELOC_X86_64_GOTPCREL64
;
1538 case BFD_RELOC_X86_64_TPOFF32
:
1539 other
= BFD_RELOC_X86_64_TPOFF64
;
1541 case BFD_RELOC_X86_64_DTPOFF32
:
1542 other
= BFD_RELOC_X86_64_DTPOFF64
;
1548 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
1549 if (size
== 4 && flag_code
!= CODE_64BIT
)
1552 reloc
= bfd_reloc_type_lookup (stdoutput
, other
);
1554 as_bad (_("unknown relocation (%u)"), other
);
1555 else if (size
!= bfd_get_reloc_size (reloc
))
1556 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
1557 bfd_get_reloc_size (reloc
),
1559 else if (pcrel
&& !reloc
->pc_relative
)
1560 as_bad (_("non-pc-relative relocation for pc-relative field"));
1561 else if ((reloc
->complain_on_overflow
== complain_overflow_signed
1563 || (reloc
->complain_on_overflow
== complain_overflow_unsigned
1565 as_bad (_("relocated field and relocation type differ in signedness"));
1574 as_bad (_("there are no unsigned pc-relative relocations"));
1577 case 1: return BFD_RELOC_8_PCREL
;
1578 case 2: return BFD_RELOC_16_PCREL
;
1579 case 4: return BFD_RELOC_32_PCREL
;
1580 case 8: return BFD_RELOC_64_PCREL
;
1582 as_bad (_("cannot do %u byte pc-relative relocation"), size
);
1589 case 4: return BFD_RELOC_X86_64_32S
;
1594 case 1: return BFD_RELOC_8
;
1595 case 2: return BFD_RELOC_16
;
1596 case 4: return BFD_RELOC_32
;
1597 case 8: return BFD_RELOC_64
;
1599 as_bad (_("cannot do %s %u byte relocation"),
1600 sign
> 0 ? "signed" : "unsigned", size
);
1604 return BFD_RELOC_NONE
;
1607 /* Here we decide which fixups can be adjusted to make them relative to
1608 the beginning of the section instead of the symbol. Basically we need
1609 to make sure that the dynamic relocations are done correctly, so in
1610 some cases we force the original symbol to be used. */
1613 tc_i386_fix_adjustable (fixP
)
1614 fixS
*fixP ATTRIBUTE_UNUSED
;
1616 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1620 /* Don't adjust pc-relative references to merge sections in 64-bit
1622 if (use_rela_relocations
1623 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
1627 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
1628 and changed later by validate_fix. */
1629 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
1630 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
1633 /* adjust_reloc_syms doesn't know about the GOT. */
1634 if (fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
1635 || fixP
->fx_r_type
== BFD_RELOC_386_PLT32
1636 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
1637 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
1638 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
1639 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
1640 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
1641 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
1642 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
1643 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
1644 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
1645 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTDESC
1646 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_DESC_CALL
1647 || fixP
->fx_r_type
== BFD_RELOC_X86_64_PLT32
1648 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
1649 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
1650 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
1651 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
1652 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
1653 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
1654 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
1655 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
1656 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
1657 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
1658 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPC32_TLSDESC
1659 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSDESC_CALL
1660 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
1661 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
1667 static int intel_float_operand
PARAMS ((const char *mnemonic
));
1670 intel_float_operand (mnemonic
)
1671 const char *mnemonic
;
1673 /* Note that the value returned is meaningful only for opcodes with (memory)
1674 operands, hence the code here is free to improperly handle opcodes that
1675 have no operands (for better performance and smaller code). */
1677 if (mnemonic
[0] != 'f')
1678 return 0; /* non-math */
1680 switch (mnemonic
[1])
1682 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
1683 the fs segment override prefix not currently handled because no
1684 call path can make opcodes without operands get here */
1686 return 2 /* integer op */;
1688 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
1689 return 3; /* fldcw/fldenv */
1692 if (mnemonic
[2] != 'o' /* fnop */)
1693 return 3; /* non-waiting control op */
1696 if (mnemonic
[2] == 's')
1697 return 3; /* frstor/frstpm */
1700 if (mnemonic
[2] == 'a')
1701 return 3; /* fsave */
1702 if (mnemonic
[2] == 't')
1704 switch (mnemonic
[3])
1706 case 'c': /* fstcw */
1707 case 'd': /* fstdw */
1708 case 'e': /* fstenv */
1709 case 's': /* fsts[gw] */
1715 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
1716 return 0; /* fxsave/fxrstor are not really math ops */
1723 /* This is the guts of the machine-dependent assembler. LINE points to a
1724 machine dependent instruction. This function is supposed to emit
1725 the frags/bytes it assembles to. */
1732 char mnemonic
[MAX_MNEM_SIZE
];
1734 /* Initialize globals. */
1735 memset (&i
, '\0', sizeof (i
));
1736 for (j
= 0; j
< MAX_OPERANDS
; j
++)
1737 i
.reloc
[j
] = NO_RELOC
;
1738 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
1739 memset (im_expressions
, '\0', sizeof (im_expressions
));
1740 save_stack_p
= save_stack
;
1742 /* First parse an instruction mnemonic & call i386_operand for the operands.
1743 We assume that the scrubber has arranged it so that line[0] is the valid
1744 start of a (possibly prefixed) mnemonic. */
1746 line
= parse_insn (line
, mnemonic
);
1750 line
= parse_operands (line
, mnemonic
);
1754 /* The order of the immediates should be reversed
1755 for 2 immediates extrq and insertq instructions */
1756 if ((i
.imm_operands
== 2) &&
1757 ((strcmp (mnemonic
, "extrq") == 0)
1758 || (strcmp (mnemonic
, "insertq") == 0)))
1760 swap_imm_operands ();
1761 /* "extrq" and insertq" are the only two instructions whose operands
1762 have to be reversed even though they have two immediate operands.
1768 /* Now we've parsed the mnemonic into a set of templates, and have the
1769 operands at hand. */
1771 /* All intel opcodes have reversed operands except for "bound" and
1772 "enter". We also don't reverse intersegment "jmp" and "call"
1773 instructions with 2 immediate operands so that the immediate segment
1774 precedes the offset, as it does when in AT&T mode. */
1775 if (intel_syntax
&& i
.operands
> 1
1776 && (strcmp (mnemonic
, "bound") != 0)
1777 && (strcmp (mnemonic
, "invlpga") != 0)
1778 && !((i
.types
[0] & Imm
) && (i
.types
[1] & Imm
)))
1784 /* Don't optimize displacement for movabs since it only takes 64bit
1787 && (flag_code
!= CODE_64BIT
1788 || strcmp (mnemonic
, "movabs") != 0))
1791 /* Next, we find a template that matches the given insn,
1792 making sure the overlap of the given operands types is consistent
1793 with the template operand types. */
1795 if (!match_template ())
1800 /* Undo SYSV386_COMPAT brokenness when in Intel mode. See i386.h */
1802 && (i
.tm
.base_opcode
& 0xfffffde0) == 0xdce0)
1803 i
.tm
.base_opcode
^= FloatR
;
1805 /* Zap movzx and movsx suffix. The suffix may have been set from
1806 "word ptr" or "byte ptr" on the source operand, but we'll use
1807 the suffix later to choose the destination register. */
1808 if ((i
.tm
.base_opcode
& ~9) == 0x0fb6)
1810 if (i
.reg_operands
< 2
1812 && (~i
.tm
.opcode_modifier
1819 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
1825 if (i
.tm
.opcode_modifier
& FWait
)
1826 if (!add_prefix (FWAIT_OPCODE
))
1829 /* Check string instruction segment overrides. */
1830 if ((i
.tm
.opcode_modifier
& IsString
) != 0 && i
.mem_operands
!= 0)
1832 if (!check_string ())
1836 if (!process_suffix ())
1839 /* Make still unresolved immediate matches conform to size of immediate
1840 given in i.suffix. */
1841 if (!finalize_imm ())
1844 if (i
.types
[0] & Imm1
)
1845 i
.imm_operands
= 0; /* kludge for shift insns. */
1846 if (i
.types
[0] & ImplicitRegister
)
1848 if (i
.types
[1] & ImplicitRegister
)
1850 if (i
.types
[2] & ImplicitRegister
)
1853 if (i
.tm
.opcode_modifier
& ImmExt
)
1857 if ((i
.tm
.cpu_flags
& CpuSSE3
) && i
.operands
> 0)
1859 /* Streaming SIMD extensions 3 Instructions have the fixed
1860 operands with an opcode suffix which is coded in the same
1861 place as an 8-bit immediate field would be. Here we check
1862 those operands and remove them afterwards. */
1865 for (x
= 0; x
< i
.operands
; x
++)
1866 if (i
.op
[x
].regs
->reg_num
!= x
)
1867 as_bad (_("can't use register '%%%s' as operand %d in '%s'."),
1868 i
.op
[x
].regs
->reg_name
, x
+ 1, i
.tm
.name
);
1872 /* These AMD 3DNow! and Intel Katmai New Instructions have an
1873 opcode suffix which is coded in the same place as an 8-bit
1874 immediate field would be. Here we fake an 8-bit immediate
1875 operand from the opcode suffix stored in tm.extension_opcode. */
1877 assert (i
.imm_operands
== 0 && i
.operands
<= 2 && 2 < MAX_OPERANDS
);
1879 exp
= &im_expressions
[i
.imm_operands
++];
1880 i
.op
[i
.operands
].imms
= exp
;
1881 i
.types
[i
.operands
++] = Imm8
;
1882 exp
->X_op
= O_constant
;
1883 exp
->X_add_number
= i
.tm
.extension_opcode
;
1884 i
.tm
.extension_opcode
= None
;
1887 /* For insns with operands there are more diddles to do to the opcode. */
1890 if (!process_operands ())
1893 else if (!quiet_warnings
&& (i
.tm
.opcode_modifier
& Ugh
) != 0)
1895 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
1896 as_warn (_("translating to `%sp'"), i
.tm
.name
);
1899 /* Handle conversion of 'int $3' --> special int3 insn. */
1900 if (i
.tm
.base_opcode
== INT_OPCODE
&& i
.op
[0].imms
->X_add_number
== 3)
1902 i
.tm
.base_opcode
= INT3_OPCODE
;
1906 if ((i
.tm
.opcode_modifier
& (Jump
| JumpByte
| JumpDword
))
1907 && i
.op
[0].disps
->X_op
== O_constant
)
1909 /* Convert "jmp constant" (and "call constant") to a jump (call) to
1910 the absolute address given by the constant. Since ix86 jumps and
1911 calls are pc relative, we need to generate a reloc. */
1912 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
1913 i
.op
[0].disps
->X_op
= O_symbol
;
1916 if ((i
.tm
.opcode_modifier
& Rex64
) != 0)
1917 i
.rex
|= REX_MODE64
;
1919 /* For 8 bit registers we need an empty rex prefix. Also if the
1920 instruction already has a prefix, we need to convert old
1921 registers to new ones. */
1923 if (((i
.types
[0] & Reg8
) != 0
1924 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
1925 || ((i
.types
[1] & Reg8
) != 0
1926 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
1927 || (((i
.types
[0] & Reg8
) != 0 || (i
.types
[1] & Reg8
) != 0)
1932 i
.rex
|= REX_OPCODE
;
1933 for (x
= 0; x
< 2; x
++)
1935 /* Look for 8 bit operand that uses old registers. */
1936 if ((i
.types
[x
] & Reg8
) != 0
1937 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
1939 /* In case it is "hi" register, give up. */
1940 if (i
.op
[x
].regs
->reg_num
> 3)
1941 as_bad (_("can't encode register '%%%s' in an instruction requiring REX prefix."),
1942 i
.op
[x
].regs
->reg_name
);
1944 /* Otherwise it is equivalent to the extended register.
1945 Since the encoding doesn't change this is merely
1946 cosmetic cleanup for debug output. */
1948 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
1954 add_prefix (REX_OPCODE
| i
.rex
);
1956 /* We are ready to output the insn. */
1961 parse_insn (line
, mnemonic
)
1966 char *token_start
= l
;
1971 /* Non-zero if we found a prefix only acceptable with string insns. */
1972 const char *expecting_string_instruction
= NULL
;
1977 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
1980 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
1982 as_bad (_("no such instruction: `%s'"), token_start
);
1987 if (!is_space_char (*l
)
1988 && *l
!= END_OF_INSN
1990 || (*l
!= PREFIX_SEPARATOR
1993 as_bad (_("invalid character %s in mnemonic"),
1994 output_invalid (*l
));
1997 if (token_start
== l
)
1999 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
2000 as_bad (_("expecting prefix; got nothing"));
2002 as_bad (_("expecting mnemonic; got nothing"));
2006 /* Look up instruction (or prefix) via hash table. */
2007 current_templates
= hash_find (op_hash
, mnemonic
);
2009 if (*l
!= END_OF_INSN
2010 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
2011 && current_templates
2012 && (current_templates
->start
->opcode_modifier
& IsPrefix
))
2014 if (current_templates
->start
->cpu_flags
2015 & (flag_code
!= CODE_64BIT
? Cpu64
: CpuNo64
))
2017 as_bad ((flag_code
!= CODE_64BIT
2018 ? _("`%s' is only supported in 64-bit mode")
2019 : _("`%s' is not supported in 64-bit mode")),
2020 current_templates
->start
->name
);
2023 /* If we are in 16-bit mode, do not allow addr16 or data16.
2024 Similarly, in 32-bit mode, do not allow addr32 or data32. */
2025 if ((current_templates
->start
->opcode_modifier
& (Size16
| Size32
))
2026 && flag_code
!= CODE_64BIT
2027 && (((current_templates
->start
->opcode_modifier
& Size32
) != 0)
2028 ^ (flag_code
== CODE_16BIT
)))
2030 as_bad (_("redundant %s prefix"),
2031 current_templates
->start
->name
);
2034 /* Add prefix, checking for repeated prefixes. */
2035 switch (add_prefix (current_templates
->start
->base_opcode
))
2040 expecting_string_instruction
= current_templates
->start
->name
;
2043 /* Skip past PREFIX_SEPARATOR and reset token_start. */
2050 if (!current_templates
)
2052 /* See if we can get a match by trimming off a suffix. */
2055 case WORD_MNEM_SUFFIX
:
2056 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
2057 i
.suffix
= SHORT_MNEM_SUFFIX
;
2059 case BYTE_MNEM_SUFFIX
:
2060 case QWORD_MNEM_SUFFIX
:
2061 i
.suffix
= mnem_p
[-1];
2063 current_templates
= hash_find (op_hash
, mnemonic
);
2065 case SHORT_MNEM_SUFFIX
:
2066 case LONG_MNEM_SUFFIX
:
2069 i
.suffix
= mnem_p
[-1];
2071 current_templates
= hash_find (op_hash
, mnemonic
);
2079 if (intel_float_operand (mnemonic
) == 1)
2080 i
.suffix
= SHORT_MNEM_SUFFIX
;
2082 i
.suffix
= LONG_MNEM_SUFFIX
;
2084 current_templates
= hash_find (op_hash
, mnemonic
);
2088 if (!current_templates
)
2090 as_bad (_("no such instruction: `%s'"), token_start
);
2095 if (current_templates
->start
->opcode_modifier
& (Jump
| JumpByte
))
2097 /* Check for a branch hint. We allow ",pt" and ",pn" for
2098 predict taken and predict not taken respectively.
2099 I'm not sure that branch hints actually do anything on loop
2100 and jcxz insns (JumpByte) for current Pentium4 chips. They
2101 may work in the future and it doesn't hurt to accept them
2103 if (l
[0] == ',' && l
[1] == 'p')
2107 if (!add_prefix (DS_PREFIX_OPCODE
))
2111 else if (l
[2] == 'n')
2113 if (!add_prefix (CS_PREFIX_OPCODE
))
2119 /* Any other comma loses. */
2122 as_bad (_("invalid character %s in mnemonic"),
2123 output_invalid (*l
));
2127 /* Check if instruction is supported on specified architecture. */
2129 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
2131 if (!((t
->cpu_flags
& ~(Cpu64
| CpuNo64
))
2132 & ~(cpu_arch_flags
& ~(Cpu64
| CpuNo64
))))
2134 if (!(t
->cpu_flags
& (flag_code
== CODE_64BIT
? CpuNo64
: Cpu64
)))
2137 if (!(supported
& 2))
2139 as_bad (flag_code
== CODE_64BIT
2140 ? _("`%s' is not supported in 64-bit mode")
2141 : _("`%s' is only supported in 64-bit mode"),
2142 current_templates
->start
->name
);
2145 if (!(supported
& 1))
2147 as_warn (_("`%s' is not supported on `%s%s'"),
2148 current_templates
->start
->name
,
2150 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
2152 else if ((Cpu386
& ~cpu_arch_flags
) && (flag_code
!= CODE_16BIT
))
2154 as_warn (_("use .code16 to ensure correct addressing mode"));
2157 /* Check for rep/repne without a string instruction. */
2158 if (expecting_string_instruction
)
2160 static templates override
;
2162 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
2163 if (t
->opcode_modifier
& IsString
)
2165 if (t
>= current_templates
->end
)
2167 as_bad (_("expecting string instruction after `%s'"),
2168 expecting_string_instruction
);
2171 for (override
.start
= t
; t
< current_templates
->end
; ++t
)
2172 if (!(t
->opcode_modifier
& IsString
))
2175 current_templates
= &override
;
2182 parse_operands (l
, mnemonic
)
2184 const char *mnemonic
;
2188 /* 1 if operand is pending after ','. */
2189 unsigned int expecting_operand
= 0;
2191 /* Non-zero if operand parens not balanced. */
2192 unsigned int paren_not_balanced
;
2194 while (*l
!= END_OF_INSN
)
2196 /* Skip optional white space before operand. */
2197 if (is_space_char (*l
))
2199 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
)
2201 as_bad (_("invalid character %s before operand %d"),
2202 output_invalid (*l
),
2206 token_start
= l
; /* after white space */
2207 paren_not_balanced
= 0;
2208 while (paren_not_balanced
|| *l
!= ',')
2210 if (*l
== END_OF_INSN
)
2212 if (paren_not_balanced
)
2215 as_bad (_("unbalanced parenthesis in operand %d."),
2218 as_bad (_("unbalanced brackets in operand %d."),
2223 break; /* we are done */
2225 else if (!is_operand_char (*l
) && !is_space_char (*l
))
2227 as_bad (_("invalid character %s in operand %d"),
2228 output_invalid (*l
),
2235 ++paren_not_balanced
;
2237 --paren_not_balanced
;
2242 ++paren_not_balanced
;
2244 --paren_not_balanced
;
2248 if (l
!= token_start
)
2249 { /* Yes, we've read in another operand. */
2250 unsigned int operand_ok
;
2251 this_operand
= i
.operands
++;
2252 if (i
.operands
> MAX_OPERANDS
)
2254 as_bad (_("spurious operands; (%d operands/instruction max)"),
2258 /* Now parse operand adding info to 'i' as we go along. */
2259 END_STRING_AND_SAVE (l
);
2263 i386_intel_operand (token_start
,
2264 intel_float_operand (mnemonic
));
2266 operand_ok
= i386_operand (token_start
);
2268 RESTORE_END_STRING (l
);
2274 if (expecting_operand
)
2276 expecting_operand_after_comma
:
2277 as_bad (_("expecting operand after ','; got nothing"));
2282 as_bad (_("expecting operand before ','; got nothing"));
2287 /* Now *l must be either ',' or END_OF_INSN. */
2290 if (*++l
== END_OF_INSN
)
2292 /* Just skip it, if it's \n complain. */
2293 goto expecting_operand_after_comma
;
2295 expecting_operand
= 1;
2302 swap_imm_operands ()
2304 union i386_op temp_op
;
2305 unsigned int temp_type
;
2306 enum bfd_reloc_code_real temp_reloc
;
2310 temp_type
= i
.types
[xchg2
];
2311 i
.types
[xchg2
] = i
.types
[xchg1
];
2312 i
.types
[xchg1
] = temp_type
;
2313 temp_op
= i
.op
[xchg2
];
2314 i
.op
[xchg2
] = i
.op
[xchg1
];
2315 i
.op
[xchg1
] = temp_op
;
2316 temp_reloc
= i
.reloc
[xchg2
];
2317 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
2318 i
.reloc
[xchg1
] = temp_reloc
;
2325 union i386_op temp_op
;
2326 unsigned int temp_type
;
2327 enum bfd_reloc_code_real temp_reloc
;
2331 if (i
.operands
== 4)
2332 /* There will be two exchanges in a 4 operand instruction.
2333 First exchange is the done inside this block.(1st and 4rth operand)
2334 The next exchange is done outside this block.(2nd and 3rd operand) */
2338 temp_type
= i
.types
[xchg2
];
2339 i
.types
[xchg2
] = i
.types
[xchg1
];
2340 i
.types
[xchg1
] = temp_type
;
2341 temp_op
= i
.op
[xchg2
];
2342 i
.op
[xchg2
] = i
.op
[xchg1
];
2343 i
.op
[xchg1
] = temp_op
;
2344 temp_reloc
= i
.reloc
[xchg2
];
2345 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
2346 i
.reloc
[xchg1
] = temp_reloc
;
2351 if (i
.operands
== 2)
2356 else if (i
.operands
== 3)
2361 temp_type
= i
.types
[xchg2
];
2362 i
.types
[xchg2
] = i
.types
[xchg1
];
2363 i
.types
[xchg1
] = temp_type
;
2364 temp_op
= i
.op
[xchg2
];
2365 i
.op
[xchg2
] = i
.op
[xchg1
];
2366 i
.op
[xchg1
] = temp_op
;
2367 temp_reloc
= i
.reloc
[xchg2
];
2368 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
2369 i
.reloc
[xchg1
] = temp_reloc
;
2371 if (i
.mem_operands
== 2)
2373 const seg_entry
*temp_seg
;
2374 temp_seg
= i
.seg
[0];
2375 i
.seg
[0] = i
.seg
[1];
2376 i
.seg
[1] = temp_seg
;
2380 /* Try to ensure constant immediates are represented in the smallest
2385 char guess_suffix
= 0;
2389 guess_suffix
= i
.suffix
;
2390 else if (i
.reg_operands
)
2392 /* Figure out a suffix from the last register operand specified.
2393 We can't do this properly yet, ie. excluding InOutPortReg,
2394 but the following works for instructions with immediates.
2395 In any case, we can't set i.suffix yet. */
2396 for (op
= i
.operands
; --op
>= 0;)
2397 if (i
.types
[op
] & Reg
)
2399 if (i
.types
[op
] & Reg8
)
2400 guess_suffix
= BYTE_MNEM_SUFFIX
;
2401 else if (i
.types
[op
] & Reg16
)
2402 guess_suffix
= WORD_MNEM_SUFFIX
;
2403 else if (i
.types
[op
] & Reg32
)
2404 guess_suffix
= LONG_MNEM_SUFFIX
;
2405 else if (i
.types
[op
] & Reg64
)
2406 guess_suffix
= QWORD_MNEM_SUFFIX
;
2410 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
2411 guess_suffix
= WORD_MNEM_SUFFIX
;
2413 for (op
= i
.operands
; --op
>= 0;)
2414 if (i
.types
[op
] & Imm
)
2416 switch (i
.op
[op
].imms
->X_op
)
2419 /* If a suffix is given, this operand may be shortened. */
2420 switch (guess_suffix
)
2422 case LONG_MNEM_SUFFIX
:
2423 i
.types
[op
] |= Imm32
| Imm64
;
2425 case WORD_MNEM_SUFFIX
:
2426 i
.types
[op
] |= Imm16
| Imm32S
| Imm32
| Imm64
;
2428 case BYTE_MNEM_SUFFIX
:
2429 i
.types
[op
] |= Imm16
| Imm8
| Imm8S
| Imm32S
| Imm32
| Imm64
;
2433 /* If this operand is at most 16 bits, convert it
2434 to a signed 16 bit number before trying to see
2435 whether it will fit in an even smaller size.
2436 This allows a 16-bit operand such as $0xffe0 to
2437 be recognised as within Imm8S range. */
2438 if ((i
.types
[op
] & Imm16
)
2439 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
2441 i
.op
[op
].imms
->X_add_number
=
2442 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
2444 if ((i
.types
[op
] & Imm32
)
2445 && ((i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1))
2448 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
2449 ^ ((offsetT
) 1 << 31))
2450 - ((offsetT
) 1 << 31));
2452 i
.types
[op
] |= smallest_imm_type (i
.op
[op
].imms
->X_add_number
);
2454 /* We must avoid matching of Imm32 templates when 64bit
2455 only immediate is available. */
2456 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
2457 i
.types
[op
] &= ~Imm32
;
2464 /* Symbols and expressions. */
2466 /* Convert symbolic operand to proper sizes for matching, but don't
2467 prevent matching a set of insns that only supports sizes other
2468 than those matching the insn suffix. */
2470 unsigned int mask
, allowed
= 0;
2473 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
2474 allowed
|= t
->operand_types
[op
];
2475 switch (guess_suffix
)
2477 case QWORD_MNEM_SUFFIX
:
2478 mask
= Imm64
| Imm32S
;
2480 case LONG_MNEM_SUFFIX
:
2483 case WORD_MNEM_SUFFIX
:
2486 case BYTE_MNEM_SUFFIX
:
2494 i
.types
[op
] &= mask
;
2501 /* Try to use the smallest displacement type too. */
2507 for (op
= i
.operands
; --op
>= 0;)
2508 if (i
.types
[op
] & Disp
)
2510 if (i
.op
[op
].disps
->X_op
== O_constant
)
2512 offsetT disp
= i
.op
[op
].disps
->X_add_number
;
2514 if ((i
.types
[op
] & Disp16
)
2515 && (disp
& ~(offsetT
) 0xffff) == 0)
2517 /* If this operand is at most 16 bits, convert
2518 to a signed 16 bit number and don't use 64bit
2520 disp
= (((disp
& 0xffff) ^ 0x8000) - 0x8000);
2521 i
.types
[op
] &= ~Disp64
;
2523 if ((i
.types
[op
] & Disp32
)
2524 && (disp
& ~(((offsetT
) 2 << 31) - 1)) == 0)
2526 /* If this operand is at most 32 bits, convert
2527 to a signed 32 bit number and don't use 64bit
2529 disp
&= (((offsetT
) 2 << 31) - 1);
2530 disp
= (disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
2531 i
.types
[op
] &= ~Disp64
;
2533 if (!disp
&& (i
.types
[op
] & BaseIndex
))
2535 i
.types
[op
] &= ~Disp
;
2539 else if (flag_code
== CODE_64BIT
)
2541 if (fits_in_signed_long (disp
))
2543 i
.types
[op
] &= ~Disp64
;
2544 i
.types
[op
] |= Disp32S
;
2546 if (fits_in_unsigned_long (disp
))
2547 i
.types
[op
] |= Disp32
;
2549 if ((i
.types
[op
] & (Disp32
| Disp32S
| Disp16
))
2550 && fits_in_signed_byte (disp
))
2551 i
.types
[op
] |= Disp8
;
2553 else if (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
2554 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
)
2556 fix_new_exp (frag_now
, frag_more (0) - frag_now
->fr_literal
, 0,
2557 i
.op
[op
].disps
, 0, i
.reloc
[op
]);
2558 i
.types
[op
] &= ~Disp
;
2561 /* We only support 64bit displacement on constants. */
2562 i
.types
[op
] &= ~Disp64
;
2569 /* Points to template once we've found it. */
2571 unsigned int overlap0
, overlap1
, overlap2
, overlap3
;
2572 unsigned int found_reverse_match
;
2574 unsigned int operand_types
[MAX_OPERANDS
];
2575 int addr_prefix_disp
;
2578 #if MAX_OPERANDS != 4
2579 # error "MAX_OPERANDS must be 4."
2582 #define MATCH(overlap, given, template) \
2583 ((overlap & ~JumpAbsolute) \
2584 && (((given) & (BaseIndex | JumpAbsolute)) \
2585 == ((overlap) & (BaseIndex | JumpAbsolute))))
2587 /* If given types r0 and r1 are registers they must be of the same type
2588 unless the expected operand type register overlap is null.
2589 Note that Acc in a template matches every size of reg. */
2590 #define CONSISTENT_REGISTER_MATCH(m0, g0, t0, m1, g1, t1) \
2591 (((g0) & Reg) == 0 || ((g1) & Reg) == 0 \
2592 || ((g0) & Reg) == ((g1) & Reg) \
2593 || ((((m0) & Acc) ? Reg : (t0)) & (((m1) & Acc) ? Reg : (t1)) & Reg) == 0 )
2599 found_reverse_match
= 0;
2600 for (j
= 0; j
< MAX_OPERANDS
; j
++)
2601 operand_types
[j
] = 0;
2602 addr_prefix_disp
= -1;
2603 suffix_check
= (i
.suffix
== BYTE_MNEM_SUFFIX
2605 : (i
.suffix
== WORD_MNEM_SUFFIX
2607 : (i
.suffix
== SHORT_MNEM_SUFFIX
2609 : (i
.suffix
== LONG_MNEM_SUFFIX
2611 : (i
.suffix
== QWORD_MNEM_SUFFIX
2613 : (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
2614 ? No_xSuf
: 0))))));
2616 for (t
= current_templates
->start
; t
< current_templates
->end
; t
++)
2618 addr_prefix_disp
= -1;
2620 /* Must have right number of operands. */
2621 if (i
.operands
!= t
->operands
)
2624 /* Check the suffix, except for some instructions in intel mode. */
2625 if ((t
->opcode_modifier
& suffix_check
)
2627 && (t
->opcode_modifier
& IgnoreSize
)))
2630 for (j
= 0; j
< MAX_OPERANDS
; j
++)
2631 operand_types
[j
] = t
->operand_types
[j
];
2633 /* In general, don't allow 64-bit operands in 32-bit mode. */
2634 if (i
.suffix
== QWORD_MNEM_SUFFIX
2635 && flag_code
!= CODE_64BIT
2637 ? (!(t
->opcode_modifier
& IgnoreSize
)
2638 && !intel_float_operand (t
->name
))
2639 : intel_float_operand (t
->name
) != 2)
2640 && (!(operand_types
[0] & (RegMMX
| RegXMM
))
2641 || !(operand_types
[t
->operands
> 1] & (RegMMX
| RegXMM
)))
2642 && (t
->base_opcode
!= 0x0fc7
2643 || t
->extension_opcode
!= 1 /* cmpxchg8b */))
2646 /* Do not verify operands when there are none. */
2647 else if (!t
->operands
)
2649 if (t
->cpu_flags
& ~cpu_arch_flags
)
2651 /* We've found a match; break out of loop. */
2655 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
2656 into Disp32/Disp16/Disp32 operand. */
2657 if (i
.prefix
[ADDR_PREFIX
] != 0)
2659 unsigned int DispOn
= 0, DispOff
= 0;
2677 for (j
= 0; j
< MAX_OPERANDS
; j
++)
2679 /* There should be only one Disp operand. */
2680 if ((operand_types
[j
] & DispOff
))
2682 addr_prefix_disp
= j
;
2683 operand_types
[j
] |= DispOn
;
2684 operand_types
[j
] &= ~DispOff
;
2690 overlap0
= i
.types
[0] & operand_types
[0];
2691 switch (t
->operands
)
2694 if (!MATCH (overlap0
, i
.types
[0], operand_types
[0]))
2700 overlap1
= i
.types
[1] & operand_types
[1];
2701 if (!MATCH (overlap0
, i
.types
[0], operand_types
[0])
2702 || !MATCH (overlap1
, i
.types
[1], operand_types
[1])
2703 /* monitor in SSE3 is a very special case. The first
2704 register and the second register may have different
2706 || !((t
->base_opcode
== 0x0f01
2707 && t
->extension_opcode
== 0xc8)
2708 || CONSISTENT_REGISTER_MATCH (overlap0
, i
.types
[0],
2710 overlap1
, i
.types
[1],
2713 /* Check if other direction is valid ... */
2714 if ((t
->opcode_modifier
& (D
| FloatD
)) == 0)
2717 /* Try reversing direction of operands. */
2718 overlap0
= i
.types
[0] & operand_types
[1];
2719 overlap1
= i
.types
[1] & operand_types
[0];
2720 if (!MATCH (overlap0
, i
.types
[0], operand_types
[1])
2721 || !MATCH (overlap1
, i
.types
[1], operand_types
[0])
2722 || !CONSISTENT_REGISTER_MATCH (overlap0
, i
.types
[0],
2724 overlap1
, i
.types
[1],
2727 /* Does not match either direction. */
2730 /* found_reverse_match holds which of D or FloatDR
2732 found_reverse_match
= t
->opcode_modifier
& (D
| FloatDR
);
2736 /* Found a forward 2 operand match here. */
2737 switch (t
->operands
)
2740 overlap3
= i
.types
[3] & operand_types
[3];
2742 overlap2
= i
.types
[2] & operand_types
[2];
2746 switch (t
->operands
)
2749 if (!MATCH (overlap3
, i
.types
[3], operand_types
[3])
2750 || !CONSISTENT_REGISTER_MATCH (overlap2
,
2758 /* Here we make use of the fact that there are no
2759 reverse match 3 operand instructions, and all 3
2760 operand instructions only need to be checked for
2761 register consistency between operands 2 and 3. */
2762 if (!MATCH (overlap2
, i
.types
[2], operand_types
[2])
2763 || !CONSISTENT_REGISTER_MATCH (overlap1
,
2773 /* Found either forward/reverse 2, 3 or 4 operand match here:
2774 slip through to break. */
2776 if (t
->cpu_flags
& ~cpu_arch_flags
)
2778 found_reverse_match
= 0;
2781 /* We've found a match; break out of loop. */
2785 if (t
== current_templates
->end
)
2787 /* We found no match. */
2788 as_bad (_("suffix or operands invalid for `%s'"),
2789 current_templates
->start
->name
);
2793 if (!quiet_warnings
)
2796 && ((i
.types
[0] & JumpAbsolute
)
2797 != (operand_types
[0] & JumpAbsolute
)))
2799 as_warn (_("indirect %s without `*'"), t
->name
);
2802 if ((t
->opcode_modifier
& (IsPrefix
| IgnoreSize
))
2803 == (IsPrefix
| IgnoreSize
))
2805 /* Warn them that a data or address size prefix doesn't
2806 affect assembly of the next line of code. */
2807 as_warn (_("stand-alone `%s' prefix"), t
->name
);
2811 /* Copy the template we found. */
2814 if (addr_prefix_disp
!= -1)
2815 i
.tm
.operand_types
[addr_prefix_disp
]
2816 = operand_types
[addr_prefix_disp
];
2818 if (found_reverse_match
)
2820 /* If we found a reverse match we must alter the opcode
2821 direction bit. found_reverse_match holds bits to change
2822 (different for int & float insns). */
2824 i
.tm
.base_opcode
^= found_reverse_match
;
2826 i
.tm
.operand_types
[0] = operand_types
[1];
2827 i
.tm
.operand_types
[1] = operand_types
[0];
2836 int mem_op
= (i
.types
[0] & AnyMem
) ? 0 : 1;
2837 if ((i
.tm
.operand_types
[mem_op
] & EsSeg
) != 0)
2839 if (i
.seg
[0] != NULL
&& i
.seg
[0] != &es
)
2841 as_bad (_("`%s' operand %d must use `%%es' segment"),
2846 /* There's only ever one segment override allowed per instruction.
2847 This instruction possibly has a legal segment override on the
2848 second operand, so copy the segment to where non-string
2849 instructions store it, allowing common code. */
2850 i
.seg
[0] = i
.seg
[1];
2852 else if ((i
.tm
.operand_types
[mem_op
+ 1] & EsSeg
) != 0)
2854 if (i
.seg
[1] != NULL
&& i
.seg
[1] != &es
)
2856 as_bad (_("`%s' operand %d must use `%%es' segment"),
2866 process_suffix (void)
2868 /* If matched instruction specifies an explicit instruction mnemonic
2870 if (i
.tm
.opcode_modifier
& (Size16
| Size32
| Size64
))
2872 if (i
.tm
.opcode_modifier
& Size16
)
2873 i
.suffix
= WORD_MNEM_SUFFIX
;
2874 else if (i
.tm
.opcode_modifier
& Size64
)
2875 i
.suffix
= QWORD_MNEM_SUFFIX
;
2877 i
.suffix
= LONG_MNEM_SUFFIX
;
2879 else if (i
.reg_operands
)
2881 /* If there's no instruction mnemonic suffix we try to invent one
2882 based on register operands. */
2885 /* We take i.suffix from the last register operand specified,
2886 Destination register type is more significant than source
2890 for (op
= i
.operands
; --op
>= 0;)
2891 if ((i
.types
[op
] & Reg
)
2892 && !(i
.tm
.operand_types
[op
] & InOutPortReg
))
2894 i
.suffix
= ((i
.types
[op
] & Reg8
) ? BYTE_MNEM_SUFFIX
:
2895 (i
.types
[op
] & Reg16
) ? WORD_MNEM_SUFFIX
:
2896 (i
.types
[op
] & Reg64
) ? QWORD_MNEM_SUFFIX
:
2901 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
2903 if (!check_byte_reg ())
2906 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
2908 if (!check_long_reg ())
2911 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
2913 if (!check_qword_reg ())
2916 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
2918 if (!check_word_reg ())
2921 else if (intel_syntax
&& (i
.tm
.opcode_modifier
& IgnoreSize
))
2922 /* Do nothing if the instruction is going to ignore the prefix. */
2927 else if ((i
.tm
.opcode_modifier
& DefaultSize
)
2929 /* exclude fldenv/frstor/fsave/fstenv */
2930 && (i
.tm
.opcode_modifier
& No_sSuf
))
2932 i
.suffix
= stackop_size
;
2934 else if (intel_syntax
2936 && ((i
.tm
.operand_types
[0] & JumpAbsolute
)
2937 || (i
.tm
.opcode_modifier
& (JumpByte
|JumpInterSegment
))
2938 || (i
.tm
.base_opcode
== 0x0f01 /* [ls][gi]dt */
2939 && i
.tm
.extension_opcode
<= 3)))
2944 if (!(i
.tm
.opcode_modifier
& No_qSuf
))
2946 i
.suffix
= QWORD_MNEM_SUFFIX
;
2950 if (!(i
.tm
.opcode_modifier
& No_lSuf
))
2951 i
.suffix
= LONG_MNEM_SUFFIX
;
2954 if (!(i
.tm
.opcode_modifier
& No_wSuf
))
2955 i
.suffix
= WORD_MNEM_SUFFIX
;
2964 if (i
.tm
.opcode_modifier
& W
)
2966 as_bad (_("no instruction mnemonic suffix given and no register operands; can't size instruction"));
2972 unsigned int suffixes
= (~i
.tm
.opcode_modifier
2980 if ((i
.tm
.opcode_modifier
& W
)
2981 || ((suffixes
& (suffixes
- 1))
2982 && !(i
.tm
.opcode_modifier
& (DefaultSize
| IgnoreSize
))))
2984 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
2990 /* Change the opcode based on the operand size given by i.suffix;
2991 We don't need to change things for byte insns. */
2993 if (i
.suffix
&& i
.suffix
!= BYTE_MNEM_SUFFIX
)
2995 /* It's not a byte, select word/dword operation. */
2996 if (i
.tm
.opcode_modifier
& W
)
2998 if (i
.tm
.opcode_modifier
& ShortForm
)
2999 i
.tm
.base_opcode
|= 8;
3001 i
.tm
.base_opcode
|= 1;
3004 /* Now select between word & dword operations via the operand
3005 size prefix, except for instructions that will ignore this
3007 if (i
.tm
.base_opcode
== 0x0f01 && i
.tm
.extension_opcode
== 0xc8)
3009 /* monitor in SSE3 is a very special case. The default size
3010 of AX is the size of mode. The address size override
3011 prefix will change the size of AX. */
3012 if (i
.op
->regs
[0].reg_type
&
3013 (flag_code
== CODE_32BIT
? Reg16
: Reg32
))
3014 if (!add_prefix (ADDR_PREFIX_OPCODE
))
3017 else if (i
.suffix
!= QWORD_MNEM_SUFFIX
3018 && i
.suffix
!= LONG_DOUBLE_MNEM_SUFFIX
3019 && !(i
.tm
.opcode_modifier
& (IgnoreSize
| FloatMF
))
3020 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
3021 || (flag_code
== CODE_64BIT
3022 && (i
.tm
.opcode_modifier
& JumpByte
))))
3024 unsigned int prefix
= DATA_PREFIX_OPCODE
;
3026 if (i
.tm
.opcode_modifier
& JumpByte
) /* jcxz, loop */
3027 prefix
= ADDR_PREFIX_OPCODE
;
3029 if (!add_prefix (prefix
))
3033 /* Set mode64 for an operand. */
3034 if (i
.suffix
== QWORD_MNEM_SUFFIX
3035 && flag_code
== CODE_64BIT
3036 && (i
.tm
.opcode_modifier
& NoRex64
) == 0)
3038 /* Special case for xchg %rax,%rax. It is NOP and doesn't
3041 || i
.types
[0] != (Acc
| Reg64
)
3042 || i
.types
[1] != (Acc
| Reg64
)
3043 || strcmp (i
.tm
.name
, "xchg") != 0)
3044 i
.rex
|= REX_MODE64
;
3047 /* Size floating point instruction. */
3048 if (i
.suffix
== LONG_MNEM_SUFFIX
)
3049 if (i
.tm
.opcode_modifier
& FloatMF
)
3050 i
.tm
.base_opcode
^= 4;
3057 check_byte_reg (void)
3061 for (op
= i
.operands
; --op
>= 0;)
3063 /* If this is an eight bit register, it's OK. If it's the 16 or
3064 32 bit version of an eight bit register, we will just use the
3065 low portion, and that's OK too. */
3066 if (i
.types
[op
] & Reg8
)
3069 /* movzx and movsx should not generate this warning. */
3071 && (i
.tm
.base_opcode
== 0xfb7
3072 || i
.tm
.base_opcode
== 0xfb6
3073 || i
.tm
.base_opcode
== 0x63
3074 || i
.tm
.base_opcode
== 0xfbe
3075 || i
.tm
.base_opcode
== 0xfbf))
3078 if ((i
.types
[op
] & WordReg
) && i
.op
[op
].regs
->reg_num
< 4)
3080 /* Prohibit these changes in the 64bit mode, since the
3081 lowering is more complicated. */
3082 if (flag_code
== CODE_64BIT
3083 && (i
.tm
.operand_types
[op
] & InOutPortReg
) == 0)
3085 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
3086 i
.op
[op
].regs
->reg_name
,
3090 #if REGISTER_WARNINGS
3092 && (i
.tm
.operand_types
[op
] & InOutPortReg
) == 0)
3093 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
3094 (i
.op
[op
].regs
+ (i
.types
[op
] & Reg16
3095 ? REGNAM_AL
- REGNAM_AX
3096 : REGNAM_AL
- REGNAM_EAX
))->reg_name
,
3097 i
.op
[op
].regs
->reg_name
,
3102 /* Any other register is bad. */
3103 if (i
.types
[op
] & (Reg
| RegMMX
| RegXMM
3105 | Control
| Debug
| Test
3106 | FloatReg
| FloatAcc
))
3108 as_bad (_("`%%%s' not allowed with `%s%c'"),
3109 i
.op
[op
].regs
->reg_name
,
3123 for (op
= i
.operands
; --op
>= 0;)
3124 /* Reject eight bit registers, except where the template requires
3125 them. (eg. movzb) */
3126 if ((i
.types
[op
] & Reg8
) != 0
3127 && (i
.tm
.operand_types
[op
] & (Reg16
| Reg32
| Acc
)) != 0)
3129 as_bad (_("`%%%s' not allowed with `%s%c'"),
3130 i
.op
[op
].regs
->reg_name
,
3135 /* Warn if the e prefix on a general reg is missing. */
3136 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
3137 && (i
.types
[op
] & Reg16
) != 0
3138 && (i
.tm
.operand_types
[op
] & (Reg32
| Acc
)) != 0)
3140 /* Prohibit these changes in the 64bit mode, since the
3141 lowering is more complicated. */
3142 if (flag_code
== CODE_64BIT
)
3144 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
3145 i
.op
[op
].regs
->reg_name
,
3149 #if REGISTER_WARNINGS
3151 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
3152 (i
.op
[op
].regs
+ REGNAM_EAX
- REGNAM_AX
)->reg_name
,
3153 i
.op
[op
].regs
->reg_name
,
3157 /* Warn if the r prefix on a general reg is missing. */
3158 else if ((i
.types
[op
] & Reg64
) != 0
3159 && (i
.tm
.operand_types
[op
] & (Reg32
| Acc
)) != 0)
3161 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
3162 i
.op
[op
].regs
->reg_name
,
3174 for (op
= i
.operands
; --op
>= 0; )
3175 /* Reject eight bit registers, except where the template requires
3176 them. (eg. movzb) */
3177 if ((i
.types
[op
] & Reg8
) != 0
3178 && (i
.tm
.operand_types
[op
] & (Reg16
| Reg32
| Acc
)) != 0)
3180 as_bad (_("`%%%s' not allowed with `%s%c'"),
3181 i
.op
[op
].regs
->reg_name
,
3186 /* Warn if the e prefix on a general reg is missing. */
3187 else if (((i
.types
[op
] & Reg16
) != 0
3188 || (i
.types
[op
] & Reg32
) != 0)
3189 && (i
.tm
.operand_types
[op
] & (Reg32
| Acc
)) != 0)
3191 /* Prohibit these changes in the 64bit mode, since the
3192 lowering is more complicated. */
3193 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
3194 i
.op
[op
].regs
->reg_name
,
3205 for (op
= i
.operands
; --op
>= 0;)
3206 /* Reject eight bit registers, except where the template requires
3207 them. (eg. movzb) */
3208 if ((i
.types
[op
] & Reg8
) != 0
3209 && (i
.tm
.operand_types
[op
] & (Reg16
| Reg32
| Acc
)) != 0)
3211 as_bad (_("`%%%s' not allowed with `%s%c'"),
3212 i
.op
[op
].regs
->reg_name
,
3217 /* Warn if the e prefix on a general reg is present. */
3218 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
3219 && (i
.types
[op
] & Reg32
) != 0
3220 && (i
.tm
.operand_types
[op
] & (Reg16
| Acc
)) != 0)
3222 /* Prohibit these changes in the 64bit mode, since the
3223 lowering is more complicated. */
3224 if (flag_code
== CODE_64BIT
)
3226 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
3227 i
.op
[op
].regs
->reg_name
,
3232 #if REGISTER_WARNINGS
3233 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
3234 (i
.op
[op
].regs
+ REGNAM_AX
- REGNAM_EAX
)->reg_name
,
3235 i
.op
[op
].regs
->reg_name
,
3245 unsigned int overlap0
, overlap1
, overlap2
;
3247 overlap0
= i
.types
[0] & i
.tm
.operand_types
[0];
3248 if ((overlap0
& (Imm8
| Imm8S
| Imm16
| Imm32
| Imm32S
| Imm64
))
3249 && overlap0
!= Imm8
&& overlap0
!= Imm8S
3250 && overlap0
!= Imm16
&& overlap0
!= Imm32S
3251 && overlap0
!= Imm32
&& overlap0
!= Imm64
)
3255 overlap0
&= (i
.suffix
== BYTE_MNEM_SUFFIX
3257 : (i
.suffix
== WORD_MNEM_SUFFIX
3259 : (i
.suffix
== QWORD_MNEM_SUFFIX
3263 else if (overlap0
== (Imm16
| Imm32S
| Imm32
)
3264 || overlap0
== (Imm16
| Imm32
)
3265 || overlap0
== (Imm16
| Imm32S
))
3267 overlap0
= ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0)
3270 if (overlap0
!= Imm8
&& overlap0
!= Imm8S
3271 && overlap0
!= Imm16
&& overlap0
!= Imm32S
3272 && overlap0
!= Imm32
&& overlap0
!= Imm64
)
3274 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size"));
3278 i
.types
[0] = overlap0
;
3280 overlap1
= i
.types
[1] & i
.tm
.operand_types
[1];
3281 if ((overlap1
& (Imm8
| Imm8S
| Imm16
| Imm32S
| Imm32
| Imm64
))
3282 && overlap1
!= Imm8
&& overlap1
!= Imm8S
3283 && overlap1
!= Imm16
&& overlap1
!= Imm32S
3284 && overlap1
!= Imm32
&& overlap1
!= Imm64
)
3288 overlap1
&= (i
.suffix
== BYTE_MNEM_SUFFIX
3290 : (i
.suffix
== WORD_MNEM_SUFFIX
3292 : (i
.suffix
== QWORD_MNEM_SUFFIX
3296 else if (overlap1
== (Imm16
| Imm32
| Imm32S
)
3297 || overlap1
== (Imm16
| Imm32
)
3298 || overlap1
== (Imm16
| Imm32S
))
3300 overlap1
= ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0)
3303 if (overlap1
!= Imm8
&& overlap1
!= Imm8S
3304 && overlap1
!= Imm16
&& overlap1
!= Imm32S
3305 && overlap1
!= Imm32
&& overlap1
!= Imm64
)
3307 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size %x %c"),overlap1
, i
.suffix
);
3311 i
.types
[1] = overlap1
;
3313 overlap2
= i
.types
[2] & i
.tm
.operand_types
[2];
3314 assert ((overlap2
& Imm
) == 0);
3315 i
.types
[2] = overlap2
;
3323 /* Default segment register this instruction will use for memory
3324 accesses. 0 means unknown. This is only for optimizing out
3325 unnecessary segment overrides. */
3326 const seg_entry
*default_seg
= 0;
3328 /* The imul $imm, %reg instruction is converted into
3329 imul $imm, %reg, %reg, and the clr %reg instruction
3330 is converted into xor %reg, %reg. */
3331 if (i
.tm
.opcode_modifier
& regKludge
)
3333 unsigned int first_reg_op
= (i
.types
[0] & Reg
) ? 0 : 1;
3334 /* Pretend we saw the extra register operand. */
3335 assert (i
.op
[first_reg_op
+ 1].regs
== 0);
3336 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
3337 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
3341 if (i
.tm
.opcode_modifier
& ShortForm
)
3343 /* The register or float register operand is in operand 0 or 1. */
3344 unsigned int op
= (i
.types
[0] & (Reg
| FloatReg
)) ? 0 : 1;
3345 /* Register goes in low 3 bits of opcode. */
3346 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
3347 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
3349 if (!quiet_warnings
&& (i
.tm
.opcode_modifier
& Ugh
) != 0)
3351 /* Warn about some common errors, but press on regardless.
3352 The first case can be generated by gcc (<= 2.8.1). */
3353 if (i
.operands
== 2)
3355 /* Reversed arguments on faddp, fsubp, etc. */
3356 as_warn (_("translating to `%s %%%s,%%%s'"), i
.tm
.name
,
3357 i
.op
[1].regs
->reg_name
,
3358 i
.op
[0].regs
->reg_name
);
3362 /* Extraneous `l' suffix on fp insn. */
3363 as_warn (_("translating to `%s %%%s'"), i
.tm
.name
,
3364 i
.op
[0].regs
->reg_name
);
3368 else if (i
.tm
.opcode_modifier
& Modrm
)
3370 /* The opcode is completed (modulo i.tm.extension_opcode which
3371 must be put into the modrm byte). Now, we make the modrm and
3372 index base bytes based on all the info we've collected. */
3374 default_seg
= build_modrm_byte ();
3376 else if (i
.tm
.opcode_modifier
& (Seg2ShortForm
| Seg3ShortForm
))
3378 if (i
.tm
.base_opcode
== POP_SEG_SHORT
3379 && i
.op
[0].regs
->reg_num
== 1)
3381 as_bad (_("you can't `pop %%cs'"));
3384 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
3385 if ((i
.op
[0].regs
->reg_flags
& RegRex
) != 0)
3388 else if ((i
.tm
.base_opcode
& ~(D
| W
)) == MOV_AX_DISP32
)
3392 else if ((i
.tm
.opcode_modifier
& IsString
) != 0)
3394 /* For the string instructions that allow a segment override
3395 on one of their operands, the default segment is ds. */
3399 if ((i
.tm
.base_opcode
== 0x8d /* lea */
3400 || (i
.tm
.cpu_flags
& CpuSVME
))
3401 && i
.seg
[0] && !quiet_warnings
)
3402 as_warn (_("segment override on `%s' is ineffectual"), i
.tm
.name
);
3404 /* If a segment was explicitly specified, and the specified segment
3405 is not the default, use an opcode prefix to select it. If we
3406 never figured out what the default segment is, then default_seg
3407 will be zero at this point, and the specified segment prefix will
3409 if ((i
.seg
[0]) && (i
.seg
[0] != default_seg
))
3411 if (!add_prefix (i
.seg
[0]->seg_prefix
))
3417 static const seg_entry
*
3420 const seg_entry
*default_seg
= 0;
3422 /* i.reg_operands MUST be the number of real register operands;
3423 implicit registers do not count. */
3424 if (i
.reg_operands
== 2)
3426 unsigned int source
, dest
;
3427 source
= ((i
.types
[0]
3428 & (Reg
| RegMMX
| RegXMM
3430 | Control
| Debug
| Test
))
3433 /* In 4 operands instructions with 2 immediate operands, the first
3434 two are immediate bytes and hence source operand will be in the
3435 next byte after the immediates */
3436 if ((i
.operands
== 4)&&(i
.imm_operands
=2)) source
++;
3440 /* One of the register operands will be encoded in the i.tm.reg
3441 field, the other in the combined i.tm.mode and i.tm.regmem
3442 fields. If no form of this instruction supports a memory
3443 destination operand, then we assume the source operand may
3444 sometimes be a memory operand and so we need to store the
3445 destination in the i.rm.reg field. */
3446 if ((i
.tm
.operand_types
[dest
] & AnyMem
) == 0)
3448 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
3449 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
3450 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
3452 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
3457 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
3458 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
3459 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
3461 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
3464 if (flag_code
!= CODE_64BIT
&& (i
.rex
& (REX_EXTX
| REX_EXTZ
)))
3466 if (!((i
.types
[0] | i
.types
[1]) & Control
))
3468 i
.rex
&= ~(REX_EXTX
| REX_EXTZ
);
3469 add_prefix (LOCK_PREFIX_OPCODE
);
3473 { /* If it's not 2 reg operands... */
3476 unsigned int fake_zero_displacement
= 0;
3477 unsigned int op
= ((i
.types
[0] & AnyMem
)
3479 : (i
.types
[1] & AnyMem
) ? 1 : 2);
3483 if (i
.base_reg
== 0)
3486 if (!i
.disp_operands
)
3487 fake_zero_displacement
= 1;
3488 if (i
.index_reg
== 0)
3490 /* Operand is just <disp> */
3491 if (flag_code
== CODE_64BIT
)
3493 /* 64bit mode overwrites the 32bit absolute
3494 addressing by RIP relative addressing and
3495 absolute addressing is encoded by one of the
3496 redundant SIB forms. */
3497 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
3498 i
.sib
.base
= NO_BASE_REGISTER
;
3499 i
.sib
.index
= NO_INDEX_REGISTER
;
3500 i
.types
[op
] = ((i
.prefix
[ADDR_PREFIX
] == 0)
3501 ? Disp32S
: Disp32
);
3503 else if ((flag_code
== CODE_16BIT
)
3504 ^ (i
.prefix
[ADDR_PREFIX
] != 0))
3506 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
3507 i
.types
[op
] = Disp16
;
3511 i
.rm
.regmem
= NO_BASE_REGISTER
;
3512 i
.types
[op
] = Disp32
;
3515 else /* !i.base_reg && i.index_reg */
3517 i
.sib
.index
= i
.index_reg
->reg_num
;
3518 i
.sib
.base
= NO_BASE_REGISTER
;
3519 i
.sib
.scale
= i
.log2_scale_factor
;
3520 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
3521 i
.types
[op
] &= ~Disp
;
3522 if (flag_code
!= CODE_64BIT
)
3523 i
.types
[op
] |= Disp32
; /* Must be 32 bit */
3525 i
.types
[op
] |= Disp32S
;
3526 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
3530 /* RIP addressing for 64bit mode. */
3531 else if (i
.base_reg
->reg_type
== BaseIndex
)
3533 i
.rm
.regmem
= NO_BASE_REGISTER
;
3534 i
.types
[op
] &= ~ Disp
;
3535 i
.types
[op
] |= Disp32S
;
3536 i
.flags
[op
] |= Operand_PCrel
;
3537 if (! i
.disp_operands
)
3538 fake_zero_displacement
= 1;
3540 else if (i
.base_reg
->reg_type
& Reg16
)
3542 switch (i
.base_reg
->reg_num
)
3545 if (i
.index_reg
== 0)
3547 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
3548 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
3552 if (i
.index_reg
== 0)
3555 if ((i
.types
[op
] & Disp
) == 0)
3557 /* fake (%bp) into 0(%bp) */
3558 i
.types
[op
] |= Disp8
;
3559 fake_zero_displacement
= 1;
3562 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
3563 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
3565 default: /* (%si) -> 4 or (%di) -> 5 */
3566 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
3568 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
3570 else /* i.base_reg and 32/64 bit mode */
3572 if (flag_code
== CODE_64BIT
3573 && (i
.types
[op
] & Disp
))
3574 i
.types
[op
] = ((i
.types
[op
] & Disp8
)
3575 | (i
.prefix
[ADDR_PREFIX
] == 0
3576 ? Disp32S
: Disp32
));
3578 i
.rm
.regmem
= i
.base_reg
->reg_num
;
3579 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
3581 i
.sib
.base
= i
.base_reg
->reg_num
;
3582 /* x86-64 ignores REX prefix bit here to avoid decoder
3584 if ((i
.base_reg
->reg_num
& 7) == EBP_REG_NUM
)
3587 if (i
.disp_operands
== 0)
3589 fake_zero_displacement
= 1;
3590 i
.types
[op
] |= Disp8
;
3593 else if (i
.base_reg
->reg_num
== ESP_REG_NUM
)
3597 i
.sib
.scale
= i
.log2_scale_factor
;
3598 if (i
.index_reg
== 0)
3600 /* <disp>(%esp) becomes two byte modrm with no index
3601 register. We've already stored the code for esp
3602 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
3603 Any base register besides %esp will not use the
3604 extra modrm byte. */
3605 i
.sib
.index
= NO_INDEX_REGISTER
;
3606 #if !SCALE1_WHEN_NO_INDEX
3607 /* Another case where we force the second modrm byte. */
3608 if (i
.log2_scale_factor
)
3609 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
3614 i
.sib
.index
= i
.index_reg
->reg_num
;
3615 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
3616 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
3621 && (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
3622 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
))
3625 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
3628 if (fake_zero_displacement
)
3630 /* Fakes a zero displacement assuming that i.types[op]
3631 holds the correct displacement size. */
3634 assert (i
.op
[op
].disps
== 0);
3635 exp
= &disp_expressions
[i
.disp_operands
++];
3636 i
.op
[op
].disps
= exp
;
3637 exp
->X_op
= O_constant
;
3638 exp
->X_add_number
= 0;
3639 exp
->X_add_symbol
= (symbolS
*) 0;
3640 exp
->X_op_symbol
= (symbolS
*) 0;
3644 /* Fill in i.rm.reg or i.rm.regmem field with register operand
3645 (if any) based on i.tm.extension_opcode. Again, we must be
3646 careful to make sure that segment/control/debug/test/MMX
3647 registers are coded into the i.rm.reg field. */
3652 & (Reg
| RegMMX
| RegXMM
3654 | Control
| Debug
| Test
))
3657 & (Reg
| RegMMX
| RegXMM
3659 | Control
| Debug
| Test
))
3662 /* If there is an extension opcode to put here, the register
3663 number must be put into the regmem field. */
3664 if (i
.tm
.extension_opcode
!= None
)
3666 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
3667 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
3672 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
3673 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
3677 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
3678 must set it to 3 to indicate this is a register operand
3679 in the regmem field. */
3680 if (!i
.mem_operands
)
3684 /* Fill in i.rm.reg field with extension opcode (if any). */
3685 if (i
.tm
.extension_opcode
!= None
)
3686 i
.rm
.reg
= i
.tm
.extension_opcode
;
3697 relax_substateT subtype
;
3702 if (flag_code
== CODE_16BIT
)
3706 if (i
.prefix
[DATA_PREFIX
] != 0)
3712 /* Pentium4 branch hints. */
3713 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
3714 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
3719 if (i
.prefix
[REX_PREFIX
] != 0)
3725 if (i
.prefixes
!= 0 && !intel_syntax
)
3726 as_warn (_("skipping prefixes on this instruction"));
3728 /* It's always a symbol; End frag & setup for relax.
3729 Make sure there is enough room in this frag for the largest
3730 instruction we may generate in md_convert_frag. This is 2
3731 bytes for the opcode and room for the prefix and largest
3733 frag_grow (prefix
+ 2 + 4);
3734 /* Prefix and 1 opcode byte go in fr_fix. */
3735 p
= frag_more (prefix
+ 1);
3736 if (i
.prefix
[DATA_PREFIX
] != 0)
3737 *p
++ = DATA_PREFIX_OPCODE
;
3738 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
3739 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
3740 *p
++ = i
.prefix
[SEG_PREFIX
];
3741 if (i
.prefix
[REX_PREFIX
] != 0)
3742 *p
++ = i
.prefix
[REX_PREFIX
];
3743 *p
= i
.tm
.base_opcode
;
3745 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
3746 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, SMALL
);
3747 else if ((cpu_arch_flags
& Cpu386
) != 0)
3748 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, SMALL
);
3750 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, SMALL
);
3753 sym
= i
.op
[0].disps
->X_add_symbol
;
3754 off
= i
.op
[0].disps
->X_add_number
;
3756 if (i
.op
[0].disps
->X_op
!= O_constant
3757 && i
.op
[0].disps
->X_op
!= O_symbol
)
3759 /* Handle complex expressions. */
3760 sym
= make_expr_symbol (i
.op
[0].disps
);
3764 /* 1 possible extra opcode + 4 byte displacement go in var part.
3765 Pass reloc in fr_var. */
3766 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
3776 if (i
.tm
.opcode_modifier
& JumpByte
)
3778 /* This is a loop or jecxz type instruction. */
3780 if (i
.prefix
[ADDR_PREFIX
] != 0)
3782 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
3785 /* Pentium4 branch hints. */
3786 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
3787 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
3789 FRAG_APPEND_1_CHAR (i
.prefix
[SEG_PREFIX
]);
3798 if (flag_code
== CODE_16BIT
)
3801 if (i
.prefix
[DATA_PREFIX
] != 0)
3803 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
3813 if (i
.prefix
[REX_PREFIX
] != 0)
3815 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
3819 if (i
.prefixes
!= 0 && !intel_syntax
)
3820 as_warn (_("skipping prefixes on this instruction"));
3822 p
= frag_more (1 + size
);
3823 *p
++ = i
.tm
.base_opcode
;
3825 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
3826 i
.op
[0].disps
, 1, reloc (size
, 1, 1, i
.reloc
[0]));
3828 /* All jumps handled here are signed, but don't use a signed limit
3829 check for 32 and 16 bit jumps as we want to allow wrap around at
3830 4G and 64k respectively. */
3832 fixP
->fx_signed
= 1;
3836 output_interseg_jump ()
3844 if (flag_code
== CODE_16BIT
)
3848 if (i
.prefix
[DATA_PREFIX
] != 0)
3854 if (i
.prefix
[REX_PREFIX
] != 0)
3864 if (i
.prefixes
!= 0 && !intel_syntax
)
3865 as_warn (_("skipping prefixes on this instruction"));
3867 /* 1 opcode; 2 segment; offset */
3868 p
= frag_more (prefix
+ 1 + 2 + size
);
3870 if (i
.prefix
[DATA_PREFIX
] != 0)
3871 *p
++ = DATA_PREFIX_OPCODE
;
3873 if (i
.prefix
[REX_PREFIX
] != 0)
3874 *p
++ = i
.prefix
[REX_PREFIX
];
3876 *p
++ = i
.tm
.base_opcode
;
3877 if (i
.op
[1].imms
->X_op
== O_constant
)
3879 offsetT n
= i
.op
[1].imms
->X_add_number
;
3882 && !fits_in_unsigned_word (n
)
3883 && !fits_in_signed_word (n
))
3885 as_bad (_("16-bit jump out of range"));
3888 md_number_to_chars (p
, n
, size
);
3891 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
3892 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
3893 if (i
.op
[0].imms
->X_op
!= O_constant
)
3894 as_bad (_("can't handle non absolute segment in `%s'"),
3896 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
3902 fragS
*insn_start_frag
;
3903 offsetT insn_start_off
;
3905 /* Tie dwarf2 debug info to the address at the start of the insn.
3906 We can't do this after the insn has been output as the current
3907 frag may have been closed off. eg. by frag_var. */
3908 dwarf2_emit_insn (0);
3910 insn_start_frag
= frag_now
;
3911 insn_start_off
= frag_now_fix ();
3914 if (i
.tm
.opcode_modifier
& Jump
)
3916 else if (i
.tm
.opcode_modifier
& (JumpByte
| JumpDword
))
3918 else if (i
.tm
.opcode_modifier
& JumpInterSegment
)
3919 output_interseg_jump ();
3922 /* Output normal instructions here. */
3925 unsigned int prefix
;
3927 /* All opcodes on i386 have either 1 or 2 bytes. Supplemental
3928 Streaming SIMD extensions 3 Instructions have 3 bytes. We may
3929 use one more higher byte to specify a prefix the instruction
3931 if ((i
.tm
.cpu_flags
& CpuSSSE3
) != 0)
3933 if (i
.tm
.base_opcode
& 0xff000000)
3935 prefix
= (i
.tm
.base_opcode
>> 24) & 0xff;
3939 else if ((i
.tm
.base_opcode
& 0xff0000) != 0)
3941 prefix
= (i
.tm
.base_opcode
>> 16) & 0xff;
3942 if ((i
.tm
.cpu_flags
& CpuPadLock
) != 0)
3945 if (prefix
!= REPE_PREFIX_OPCODE
3946 || i
.prefix
[LOCKREP_PREFIX
] != REPE_PREFIX_OPCODE
)
3947 add_prefix (prefix
);
3950 add_prefix (prefix
);
3953 /* The prefix bytes. */
3955 q
< i
.prefix
+ sizeof (i
.prefix
) / sizeof (i
.prefix
[0]);
3961 md_number_to_chars (p
, (valueT
) *q
, 1);
3965 /* Now the opcode; be careful about word order here! */
3966 if (fits_in_unsigned_byte (i
.tm
.base_opcode
))
3968 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
3972 if ((i
.tm
.cpu_flags
& CpuSSSE3
) != 0)
3975 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
3980 /* Put out high byte first: can't use md_number_to_chars! */
3981 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
3982 *p
= i
.tm
.base_opcode
& 0xff;
3985 /* Now the modrm byte and sib byte (if present). */
3986 if (i
.tm
.opcode_modifier
& Modrm
)
3989 md_number_to_chars (p
,
3990 (valueT
) (i
.rm
.regmem
<< 0
3994 /* If i.rm.regmem == ESP (4)
3995 && i.rm.mode != (Register mode)
3997 ==> need second modrm byte. */
3998 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
4000 && !(i
.base_reg
&& (i
.base_reg
->reg_type
& Reg16
) != 0))
4003 md_number_to_chars (p
,
4004 (valueT
) (i
.sib
.base
<< 0
4006 | i
.sib
.scale
<< 6),
4011 if (i
.disp_operands
)
4012 output_disp (insn_start_frag
, insn_start_off
);
4015 output_imm (insn_start_frag
, insn_start_off
);
4021 pi ("" /*line*/, &i
);
4023 #endif /* DEBUG386 */
4027 output_disp (fragS
*insn_start_frag
, offsetT insn_start_off
)
4032 for (n
= 0; n
< i
.operands
; n
++)
4034 if (i
.types
[n
] & Disp
)
4036 if (i
.op
[n
].disps
->X_op
== O_constant
)
4042 if (i
.types
[n
] & (Disp8
| Disp16
| Disp64
))
4045 if (i
.types
[n
] & Disp8
)
4047 if (i
.types
[n
] & Disp64
)
4050 val
= offset_in_range (i
.op
[n
].disps
->X_add_number
,
4052 p
= frag_more (size
);
4053 md_number_to_chars (p
, val
, size
);
4057 enum bfd_reloc_code_real reloc_type
;
4060 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
4062 /* The PC relative address is computed relative
4063 to the instruction boundary, so in case immediate
4064 fields follows, we need to adjust the value. */
4065 if (pcrel
&& i
.imm_operands
)
4070 for (n1
= 0; n1
< i
.operands
; n1
++)
4071 if (i
.types
[n1
] & Imm
)
4073 if (i
.types
[n1
] & (Imm8
| Imm8S
| Imm16
| Imm64
))
4076 if (i
.types
[n1
] & (Imm8
| Imm8S
))
4078 if (i
.types
[n1
] & Imm64
)
4083 /* We should find the immediate. */
4084 if (n1
== i
.operands
)
4086 i
.op
[n
].disps
->X_add_number
-= imm_size
;
4089 if (i
.types
[n
] & Disp32S
)
4092 if (i
.types
[n
] & (Disp16
| Disp64
))
4095 if (i
.types
[n
] & Disp64
)
4099 p
= frag_more (size
);
4100 reloc_type
= reloc (size
, pcrel
, sign
, i
.reloc
[n
]);
4102 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
4103 && (((reloc_type
== BFD_RELOC_32
4104 || reloc_type
== BFD_RELOC_X86_64_32S
4105 || (reloc_type
== BFD_RELOC_64
4107 && (i
.op
[n
].disps
->X_op
== O_symbol
4108 || (i
.op
[n
].disps
->X_op
== O_add
4109 && ((symbol_get_value_expression
4110 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
4112 || reloc_type
== BFD_RELOC_32_PCREL
))
4116 if (insn_start_frag
== frag_now
)
4117 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
4122 add
= insn_start_frag
->fr_fix
- insn_start_off
;
4123 for (fr
= insn_start_frag
->fr_next
;
4124 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
4126 add
+= p
- frag_now
->fr_literal
;
4131 reloc_type
= BFD_RELOC_386_GOTPC
;
4132 i
.op
[n
].imms
->X_add_number
+= add
;
4134 else if (reloc_type
== BFD_RELOC_64
)
4135 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
4137 /* Don't do the adjustment for x86-64, as there
4138 the pcrel addressing is relative to the _next_
4139 insn, and that is taken care of in other code. */
4140 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
4142 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
4143 i
.op
[n
].disps
, pcrel
, reloc_type
);
4150 output_imm (fragS
*insn_start_frag
, offsetT insn_start_off
)
4155 for (n
= 0; n
< i
.operands
; n
++)
4157 if (i
.types
[n
] & Imm
)
4159 if (i
.op
[n
].imms
->X_op
== O_constant
)
4165 if (i
.types
[n
] & (Imm8
| Imm8S
| Imm16
| Imm64
))
4168 if (i
.types
[n
] & (Imm8
| Imm8S
))
4170 else if (i
.types
[n
] & Imm64
)
4173 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
4175 p
= frag_more (size
);
4176 md_number_to_chars (p
, val
, size
);
4180 /* Not absolute_section.
4181 Need a 32-bit fixup (don't support 8bit
4182 non-absolute imms). Try to support other
4184 enum bfd_reloc_code_real reloc_type
;
4188 if ((i
.types
[n
] & (Imm32S
))
4189 && (i
.suffix
== QWORD_MNEM_SUFFIX
4190 || (!i
.suffix
&& (i
.tm
.opcode_modifier
& No_lSuf
))))
4192 if (i
.types
[n
] & (Imm8
| Imm8S
| Imm16
| Imm64
))
4195 if (i
.types
[n
] & (Imm8
| Imm8S
))
4197 if (i
.types
[n
] & Imm64
)
4201 p
= frag_more (size
);
4202 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
4204 /* This is tough to explain. We end up with this one if we
4205 * have operands that look like
4206 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
4207 * obtain the absolute address of the GOT, and it is strongly
4208 * preferable from a performance point of view to avoid using
4209 * a runtime relocation for this. The actual sequence of
4210 * instructions often look something like:
4215 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
4217 * The call and pop essentially return the absolute address
4218 * of the label .L66 and store it in %ebx. The linker itself
4219 * will ultimately change the first operand of the addl so
4220 * that %ebx points to the GOT, but to keep things simple, the
4221 * .o file must have this operand set so that it generates not
4222 * the absolute address of .L66, but the absolute address of
4223 * itself. This allows the linker itself simply treat a GOTPC
4224 * relocation as asking for a pcrel offset to the GOT to be
4225 * added in, and the addend of the relocation is stored in the
4226 * operand field for the instruction itself.
4228 * Our job here is to fix the operand so that it would add
4229 * the correct offset so that %ebx would point to itself. The
4230 * thing that is tricky is that .-.L66 will point to the
4231 * beginning of the instruction, so we need to further modify
4232 * the operand so that it will point to itself. There are
4233 * other cases where you have something like:
4235 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
4237 * and here no correction would be required. Internally in
4238 * the assembler we treat operands of this form as not being
4239 * pcrel since the '.' is explicitly mentioned, and I wonder
4240 * whether it would simplify matters to do it this way. Who
4241 * knows. In earlier versions of the PIC patches, the
4242 * pcrel_adjust field was used to store the correction, but
4243 * since the expression is not pcrel, I felt it would be
4244 * confusing to do it this way. */
4246 if ((reloc_type
== BFD_RELOC_32
4247 || reloc_type
== BFD_RELOC_X86_64_32S
4248 || reloc_type
== BFD_RELOC_64
)
4250 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
4251 && (i
.op
[n
].imms
->X_op
== O_symbol
4252 || (i
.op
[n
].imms
->X_op
== O_add
4253 && ((symbol_get_value_expression
4254 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
4259 if (insn_start_frag
== frag_now
)
4260 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
4265 add
= insn_start_frag
->fr_fix
- insn_start_off
;
4266 for (fr
= insn_start_frag
->fr_next
;
4267 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
4269 add
+= p
- frag_now
->fr_literal
;
4273 reloc_type
= BFD_RELOC_386_GOTPC
;
4275 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
4277 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
4278 i
.op
[n
].imms
->X_add_number
+= add
;
4280 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
4281 i
.op
[n
].imms
, 0, reloc_type
);
4287 /* x86_cons_fix_new is called via the expression parsing code when a
4288 reloc is needed. We use this hook to get the correct .got reloc. */
4289 static enum bfd_reloc_code_real got_reloc
= NO_RELOC
;
4290 static int cons_sign
= -1;
4293 x86_cons_fix_new (fragS
*frag
,
4298 enum bfd_reloc_code_real r
= reloc (len
, 0, cons_sign
, got_reloc
);
4300 got_reloc
= NO_RELOC
;
4303 if (exp
->X_op
== O_secrel
)
4305 exp
->X_op
= O_symbol
;
4306 r
= BFD_RELOC_32_SECREL
;
4310 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
4313 #if (!defined (OBJ_ELF) && !defined (OBJ_MAYBE_ELF)) || defined (LEX_AT)
4314 # define lex_got(reloc, adjust, types) NULL
4316 /* Parse operands of the form
4317 <symbol>@GOTOFF+<nnn>
4318 and similar .plt or .got references.
4320 If we find one, set up the correct relocation in RELOC and copy the
4321 input string, minus the `@GOTOFF' into a malloc'd buffer for
4322 parsing by the calling routine. Return this buffer, and if ADJUST
4323 is non-null set it to the length of the string we removed from the
4324 input line. Otherwise return NULL. */
4326 lex_got (enum bfd_reloc_code_real
*reloc
,
4328 unsigned int *types
)
4330 /* Some of the relocations depend on the size of what field is to
4331 be relocated. But in our callers i386_immediate and i386_displacement
4332 we don't yet know the operand size (this will be set by insn
4333 matching). Hence we record the word32 relocation here,
4334 and adjust the reloc according to the real size in reloc(). */
4335 static const struct {
4337 const enum bfd_reloc_code_real rel
[2];
4338 const unsigned int types64
;
4340 { "PLTOFF", { 0, BFD_RELOC_X86_64_PLTOFF64
}, Imm64
},
4341 { "PLT", { BFD_RELOC_386_PLT32
, BFD_RELOC_X86_64_PLT32
}, Imm32
|Imm32S
|Disp32
},
4342 { "GOTPLT", { 0, BFD_RELOC_X86_64_GOTPLT64
}, Imm64
|Disp64
},
4343 { "GOTOFF", { BFD_RELOC_386_GOTOFF
, BFD_RELOC_X86_64_GOTOFF64
}, Imm64
|Disp64
},
4344 { "GOTPCREL", { 0, BFD_RELOC_X86_64_GOTPCREL
}, Imm32
|Imm32S
|Disp32
},
4345 { "TLSGD", { BFD_RELOC_386_TLS_GD
, BFD_RELOC_X86_64_TLSGD
}, Imm32
|Imm32S
|Disp32
},
4346 { "TLSLDM", { BFD_RELOC_386_TLS_LDM
, 0 }, 0 },
4347 { "TLSLD", { 0, BFD_RELOC_X86_64_TLSLD
}, Imm32
|Imm32S
|Disp32
},
4348 { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32
, BFD_RELOC_X86_64_GOTTPOFF
}, Imm32
|Imm32S
|Disp32
},
4349 { "TPOFF", { BFD_RELOC_386_TLS_LE_32
, BFD_RELOC_X86_64_TPOFF32
}, Imm32
|Imm32S
|Imm64
|Disp32
|Disp64
},
4350 { "NTPOFF", { BFD_RELOC_386_TLS_LE
, 0 }, 0 },
4351 { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32
, BFD_RELOC_X86_64_DTPOFF32
}, Imm32
|Imm32S
|Imm64
|Disp32
|Disp64
},
4352 { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE
, 0 }, 0 },
4353 { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE
, 0 }, 0 },
4354 { "GOT", { BFD_RELOC_386_GOT32
, BFD_RELOC_X86_64_GOT32
}, Imm32
|Imm32S
|Disp32
|Imm64
},
4355 { "TLSDESC", { BFD_RELOC_386_TLS_GOTDESC
, BFD_RELOC_X86_64_GOTPC32_TLSDESC
}, Imm32
|Imm32S
|Disp32
},
4356 { "TLSCALL", { BFD_RELOC_386_TLS_DESC_CALL
, BFD_RELOC_X86_64_TLSDESC_CALL
}, Imm32
|Imm32S
|Disp32
}
4364 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
4365 if (is_end_of_line
[(unsigned char) *cp
])
4368 for (j
= 0; j
< sizeof (gotrel
) / sizeof (gotrel
[0]); j
++)
4372 len
= strlen (gotrel
[j
].str
);
4373 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
4375 if (gotrel
[j
].rel
[object_64bit
] != 0)
4378 char *tmpbuf
, *past_reloc
;
4380 *reloc
= gotrel
[j
].rel
[object_64bit
];
4386 if (flag_code
!= CODE_64BIT
)
4387 *types
= Imm32
|Disp32
;
4389 *types
= gotrel
[j
].types64
;
4392 if (GOT_symbol
== NULL
)
4393 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
4395 /* Replace the relocation token with ' ', so that
4396 errors like foo@GOTOFF1 will be detected. */
4398 /* The length of the first part of our input line. */
4399 first
= cp
- input_line_pointer
;
4401 /* The second part goes from after the reloc token until
4402 (and including) an end_of_line char. Don't use strlen
4403 here as the end_of_line char may not be a NUL. */
4404 past_reloc
= cp
+ 1 + len
;
4405 for (cp
= past_reloc
; !is_end_of_line
[(unsigned char) *cp
++]; )
4407 second
= cp
- past_reloc
;
4409 /* Allocate and copy string. The trailing NUL shouldn't
4410 be necessary, but be safe. */
4411 tmpbuf
= xmalloc (first
+ second
+ 2);
4412 memcpy (tmpbuf
, input_line_pointer
, first
);
4413 tmpbuf
[first
] = ' ';
4414 memcpy (tmpbuf
+ first
+ 1, past_reloc
, second
);
4415 tmpbuf
[first
+ second
+ 1] = '\0';
4419 as_bad (_("@%s reloc is not supported with %d-bit output format"),
4420 gotrel
[j
].str
, 1 << (5 + object_64bit
));
4425 /* Might be a symbol version string. Don't as_bad here. */
4430 x86_cons (exp
, size
)
4434 if (size
== 4 || (object_64bit
&& size
== 8))
4436 /* Handle @GOTOFF and the like in an expression. */
4438 char *gotfree_input_line
;
4441 save
= input_line_pointer
;
4442 gotfree_input_line
= lex_got (&got_reloc
, &adjust
, NULL
);
4443 if (gotfree_input_line
)
4444 input_line_pointer
= gotfree_input_line
;
4448 if (gotfree_input_line
)
4450 /* expression () has merrily parsed up to the end of line,
4451 or a comma - in the wrong buffer. Transfer how far
4452 input_line_pointer has moved to the right buffer. */
4453 input_line_pointer
= (save
4454 + (input_line_pointer
- gotfree_input_line
)
4456 free (gotfree_input_line
);
4464 static void signed_cons (int size
)
4466 if (flag_code
== CODE_64BIT
)
4474 pe_directive_secrel (dummy
)
4475 int dummy ATTRIBUTE_UNUSED
;
4482 if (exp
.X_op
== O_symbol
)
4483 exp
.X_op
= O_secrel
;
4485 emit_expr (&exp
, 4);
4487 while (*input_line_pointer
++ == ',');
4489 input_line_pointer
--;
4490 demand_empty_rest_of_line ();
4494 static int i386_immediate
PARAMS ((char *));
4497 i386_immediate (imm_start
)
4500 char *save_input_line_pointer
;
4501 char *gotfree_input_line
;
4504 unsigned int types
= ~0U;
4506 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
4508 as_bad (_("only 1 or 2 immediate operands are allowed"));
4512 exp
= &im_expressions
[i
.imm_operands
++];
4513 i
.op
[this_operand
].imms
= exp
;
4515 if (is_space_char (*imm_start
))
4518 save_input_line_pointer
= input_line_pointer
;
4519 input_line_pointer
= imm_start
;
4521 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
4522 if (gotfree_input_line
)
4523 input_line_pointer
= gotfree_input_line
;
4525 exp_seg
= expression (exp
);
4528 if (*input_line_pointer
)
4529 as_bad (_("junk `%s' after expression"), input_line_pointer
);
4531 input_line_pointer
= save_input_line_pointer
;
4532 if (gotfree_input_line
)
4533 free (gotfree_input_line
);
4535 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_big
)
4537 /* Missing or bad expr becomes absolute 0. */
4538 as_bad (_("missing or invalid immediate expression `%s' taken as 0"),
4540 exp
->X_op
= O_constant
;
4541 exp
->X_add_number
= 0;
4542 exp
->X_add_symbol
= (symbolS
*) 0;
4543 exp
->X_op_symbol
= (symbolS
*) 0;
4545 else if (exp
->X_op
== O_constant
)
4547 /* Size it properly later. */
4548 i
.types
[this_operand
] |= Imm64
;
4549 /* If BFD64, sign extend val. */
4550 if (!use_rela_relocations
)
4551 if ((exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
4552 exp
->X_add_number
= (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
4554 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
4555 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
4556 && exp_seg
!= absolute_section
4557 && exp_seg
!= text_section
4558 && exp_seg
!= data_section
4559 && exp_seg
!= bss_section
4560 && exp_seg
!= undefined_section
4561 && !bfd_is_com_section (exp_seg
))
4563 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
4567 else if (!intel_syntax
&& exp
->X_op
== O_register
)
4569 as_bad (_("illegal immediate register operand %s"), imm_start
);
4574 /* This is an address. The size of the address will be
4575 determined later, depending on destination register,
4576 suffix, or the default for the section. */
4577 i
.types
[this_operand
] |= Imm8
| Imm16
| Imm32
| Imm32S
| Imm64
;
4578 i
.types
[this_operand
] &= types
;
4584 static char *i386_scale
PARAMS ((char *));
4591 char *save
= input_line_pointer
;
4593 input_line_pointer
= scale
;
4594 val
= get_absolute_expression ();
4599 i
.log2_scale_factor
= 0;
4602 i
.log2_scale_factor
= 1;
4605 i
.log2_scale_factor
= 2;
4608 i
.log2_scale_factor
= 3;
4612 char sep
= *input_line_pointer
;
4614 *input_line_pointer
= '\0';
4615 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
4617 *input_line_pointer
= sep
;
4618 input_line_pointer
= save
;
4622 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
4624 as_warn (_("scale factor of %d without an index register"),
4625 1 << i
.log2_scale_factor
);
4626 #if SCALE1_WHEN_NO_INDEX
4627 i
.log2_scale_factor
= 0;
4630 scale
= input_line_pointer
;
4631 input_line_pointer
= save
;
4635 static int i386_displacement
PARAMS ((char *, char *));
4638 i386_displacement (disp_start
, disp_end
)
4644 char *save_input_line_pointer
;
4645 char *gotfree_input_line
;
4646 int bigdisp
, override
;
4647 unsigned int types
= Disp
;
4649 if ((i
.types
[this_operand
] & JumpAbsolute
)
4650 || !(current_templates
->start
->opcode_modifier
& (Jump
| JumpDword
)))
4653 override
= (i
.prefix
[ADDR_PREFIX
] != 0);
4657 /* For PC-relative branches, the width of the displacement
4658 is dependent upon data size, not address size. */
4660 override
= (i
.prefix
[DATA_PREFIX
] != 0);
4662 if (flag_code
== CODE_64BIT
)
4665 bigdisp
= ((override
|| i
.suffix
== WORD_MNEM_SUFFIX
)
4667 : Disp32S
| Disp32
);
4669 bigdisp
= Disp64
| Disp32S
| Disp32
;
4676 override
= (i
.suffix
== (flag_code
!= CODE_16BIT
4678 : LONG_MNEM_SUFFIX
));
4681 if ((flag_code
== CODE_16BIT
) ^ override
)
4684 i
.types
[this_operand
] |= bigdisp
;
4686 exp
= &disp_expressions
[i
.disp_operands
];
4687 i
.op
[this_operand
].disps
= exp
;
4689 save_input_line_pointer
= input_line_pointer
;
4690 input_line_pointer
= disp_start
;
4691 END_STRING_AND_SAVE (disp_end
);
4693 #ifndef GCC_ASM_O_HACK
4694 #define GCC_ASM_O_HACK 0
4697 END_STRING_AND_SAVE (disp_end
+ 1);
4698 if ((i
.types
[this_operand
] & BaseIndex
) != 0
4699 && displacement_string_end
[-1] == '+')
4701 /* This hack is to avoid a warning when using the "o"
4702 constraint within gcc asm statements.
4705 #define _set_tssldt_desc(n,addr,limit,type) \
4706 __asm__ __volatile__ ( \
4708 "movw %w1,2+%0\n\t" \
4710 "movb %b1,4+%0\n\t" \
4711 "movb %4,5+%0\n\t" \
4712 "movb $0,6+%0\n\t" \
4713 "movb %h1,7+%0\n\t" \
4715 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
4717 This works great except that the output assembler ends
4718 up looking a bit weird if it turns out that there is
4719 no offset. You end up producing code that looks like:
4732 So here we provide the missing zero. */
4734 *displacement_string_end
= '0';
4737 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
4738 if (gotfree_input_line
)
4739 input_line_pointer
= gotfree_input_line
;
4741 exp_seg
= expression (exp
);
4744 if (*input_line_pointer
)
4745 as_bad (_("junk `%s' after expression"), input_line_pointer
);
4747 RESTORE_END_STRING (disp_end
+ 1);
4749 RESTORE_END_STRING (disp_end
);
4750 input_line_pointer
= save_input_line_pointer
;
4751 if (gotfree_input_line
)
4752 free (gotfree_input_line
);
4754 /* We do this to make sure that the section symbol is in
4755 the symbol table. We will ultimately change the relocation
4756 to be relative to the beginning of the section. */
4757 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
4758 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
4759 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
4761 if (exp
->X_op
!= O_symbol
)
4763 as_bad (_("bad expression used with @%s"),
4764 (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
4770 if (S_IS_LOCAL (exp
->X_add_symbol
)
4771 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
)
4772 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
4773 exp
->X_op
= O_subtract
;
4774 exp
->X_op_symbol
= GOT_symbol
;
4775 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
4776 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
4777 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
4778 i
.reloc
[this_operand
] = BFD_RELOC_64
;
4780 i
.reloc
[this_operand
] = BFD_RELOC_32
;
4783 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_big
)
4785 /* Missing or bad expr becomes absolute 0. */
4786 as_bad (_("missing or invalid displacement expression `%s' taken as 0"),
4788 exp
->X_op
= O_constant
;
4789 exp
->X_add_number
= 0;
4790 exp
->X_add_symbol
= (symbolS
*) 0;
4791 exp
->X_op_symbol
= (symbolS
*) 0;
4794 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
4795 if (exp
->X_op
!= O_constant
4796 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
4797 && exp_seg
!= absolute_section
4798 && exp_seg
!= text_section
4799 && exp_seg
!= data_section
4800 && exp_seg
!= bss_section
4801 && exp_seg
!= undefined_section
4802 && !bfd_is_com_section (exp_seg
))
4804 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
4809 if (!(i
.types
[this_operand
] & ~Disp
))
4810 i
.types
[this_operand
] &= types
;
4815 static int i386_index_check
PARAMS ((const char *));
4817 /* Make sure the memory operand we've been dealt is valid.
4818 Return 1 on success, 0 on a failure. */
4821 i386_index_check (operand_string
)
4822 const char *operand_string
;
4825 #if INFER_ADDR_PREFIX
4831 if ((current_templates
->start
->cpu_flags
& CpuSVME
)
4832 && current_templates
->end
[-1].operand_types
[0] == AnyMem
)
4834 /* Memory operands of SVME insns are special in that they only allow
4835 rAX as their memory address and ignore any segment override. */
4838 /* SKINIT is even more restrictive: it always requires EAX. */
4839 if (strcmp (current_templates
->start
->name
, "skinit") == 0)
4841 else if (flag_code
== CODE_64BIT
)
4842 RegXX
= i
.prefix
[ADDR_PREFIX
] == 0 ? Reg64
: Reg32
;
4844 RegXX
= ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[ADDR_PREFIX
] != 0)
4848 || !(i
.base_reg
->reg_type
& Acc
)
4849 || !(i
.base_reg
->reg_type
& RegXX
)
4851 || (i
.types
[0] & Disp
))
4854 else if (flag_code
== CODE_64BIT
)
4856 unsigned RegXX
= (i
.prefix
[ADDR_PREFIX
] == 0 ? Reg64
: Reg32
);
4859 && ((i
.base_reg
->reg_type
& RegXX
) == 0)
4860 && (i
.base_reg
->reg_type
!= BaseIndex
4863 && ((i
.index_reg
->reg_type
& (RegXX
| BaseIndex
))
4864 != (RegXX
| BaseIndex
))))
4869 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[ADDR_PREFIX
] != 0))
4873 && ((i
.base_reg
->reg_type
& (Reg16
| BaseIndex
| RegRex
))
4874 != (Reg16
| BaseIndex
)))
4876 && (((i
.index_reg
->reg_type
& (Reg16
| BaseIndex
))
4877 != (Reg16
| BaseIndex
))
4879 && i
.base_reg
->reg_num
< 6
4880 && i
.index_reg
->reg_num
>= 6
4881 && i
.log2_scale_factor
== 0))))
4888 && (i
.base_reg
->reg_type
& (Reg32
| RegRex
)) != Reg32
)
4890 && ((i
.index_reg
->reg_type
& (Reg32
| BaseIndex
| RegRex
))
4891 != (Reg32
| BaseIndex
))))
4897 #if INFER_ADDR_PREFIX
4898 if (i
.prefix
[ADDR_PREFIX
] == 0)
4900 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
4902 /* Change the size of any displacement too. At most one of
4903 Disp16 or Disp32 is set.
4904 FIXME. There doesn't seem to be any real need for separate
4905 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
4906 Removing them would probably clean up the code quite a lot. */
4907 if (flag_code
!= CODE_64BIT
&& (i
.types
[this_operand
] & (Disp16
| Disp32
)))
4908 i
.types
[this_operand
] ^= (Disp16
| Disp32
);
4913 as_bad (_("`%s' is not a valid base/index expression"),
4917 as_bad (_("`%s' is not a valid %s bit base/index expression"),
4919 flag_code_names
[flag_code
]);
4924 /* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero
4928 i386_operand (operand_string
)
4929 char *operand_string
;
4933 char *op_string
= operand_string
;
4935 if (is_space_char (*op_string
))
4938 /* We check for an absolute prefix (differentiating,
4939 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
4940 if (*op_string
== ABSOLUTE_PREFIX
)
4943 if (is_space_char (*op_string
))
4945 i
.types
[this_operand
] |= JumpAbsolute
;
4948 /* Check if operand is a register. */
4949 if ((r
= parse_register (op_string
, &end_op
)) != NULL
)
4951 /* Check for a segment override by searching for ':' after a
4952 segment register. */
4954 if (is_space_char (*op_string
))
4956 if (*op_string
== ':' && (r
->reg_type
& (SReg2
| SReg3
)))
4961 i
.seg
[i
.mem_operands
] = &es
;
4964 i
.seg
[i
.mem_operands
] = &cs
;
4967 i
.seg
[i
.mem_operands
] = &ss
;
4970 i
.seg
[i
.mem_operands
] = &ds
;
4973 i
.seg
[i
.mem_operands
] = &fs
;
4976 i
.seg
[i
.mem_operands
] = &gs
;
4980 /* Skip the ':' and whitespace. */
4982 if (is_space_char (*op_string
))
4985 if (!is_digit_char (*op_string
)
4986 && !is_identifier_char (*op_string
)
4987 && *op_string
!= '('
4988 && *op_string
!= ABSOLUTE_PREFIX
)
4990 as_bad (_("bad memory operand `%s'"), op_string
);
4993 /* Handle case of %es:*foo. */
4994 if (*op_string
== ABSOLUTE_PREFIX
)
4997 if (is_space_char (*op_string
))
4999 i
.types
[this_operand
] |= JumpAbsolute
;
5001 goto do_memory_reference
;
5005 as_bad (_("junk `%s' after register"), op_string
);
5008 i
.types
[this_operand
] |= r
->reg_type
& ~BaseIndex
;
5009 i
.op
[this_operand
].regs
= r
;
5012 else if (*op_string
== REGISTER_PREFIX
)
5014 as_bad (_("bad register name `%s'"), op_string
);
5017 else if (*op_string
== IMMEDIATE_PREFIX
)
5020 if (i
.types
[this_operand
] & JumpAbsolute
)
5022 as_bad (_("immediate operand illegal with absolute jump"));
5025 if (!i386_immediate (op_string
))
5028 else if (is_digit_char (*op_string
)
5029 || is_identifier_char (*op_string
)
5030 || *op_string
== '(')
5032 /* This is a memory reference of some sort. */
5035 /* Start and end of displacement string expression (if found). */
5036 char *displacement_string_start
;
5037 char *displacement_string_end
;
5039 do_memory_reference
:
5040 if ((i
.mem_operands
== 1
5041 && (current_templates
->start
->opcode_modifier
& IsString
) == 0)
5042 || i
.mem_operands
== 2)
5044 as_bad (_("too many memory references for `%s'"),
5045 current_templates
->start
->name
);
5049 /* Check for base index form. We detect the base index form by
5050 looking for an ')' at the end of the operand, searching
5051 for the '(' matching it, and finding a REGISTER_PREFIX or ','
5053 base_string
= op_string
+ strlen (op_string
);
5056 if (is_space_char (*base_string
))
5059 /* If we only have a displacement, set-up for it to be parsed later. */
5060 displacement_string_start
= op_string
;
5061 displacement_string_end
= base_string
+ 1;
5063 if (*base_string
== ')')
5066 unsigned int parens_balanced
= 1;
5067 /* We've already checked that the number of left & right ()'s are
5068 equal, so this loop will not be infinite. */
5072 if (*base_string
== ')')
5074 if (*base_string
== '(')
5077 while (parens_balanced
);
5079 temp_string
= base_string
;
5081 /* Skip past '(' and whitespace. */
5083 if (is_space_char (*base_string
))
5086 if (*base_string
== ','
5087 || ((i
.base_reg
= parse_register (base_string
, &end_op
)) != NULL
))
5089 displacement_string_end
= temp_string
;
5091 i
.types
[this_operand
] |= BaseIndex
;
5095 base_string
= end_op
;
5096 if (is_space_char (*base_string
))
5100 /* There may be an index reg or scale factor here. */
5101 if (*base_string
== ',')
5104 if (is_space_char (*base_string
))
5107 if ((i
.index_reg
= parse_register (base_string
, &end_op
)) != NULL
)
5109 base_string
= end_op
;
5110 if (is_space_char (*base_string
))
5112 if (*base_string
== ',')
5115 if (is_space_char (*base_string
))
5118 else if (*base_string
!= ')')
5120 as_bad (_("expecting `,' or `)' after index register in `%s'"),
5125 else if (*base_string
== REGISTER_PREFIX
)
5127 as_bad (_("bad register name `%s'"), base_string
);
5131 /* Check for scale factor. */
5132 if (*base_string
!= ')')
5134 char *end_scale
= i386_scale (base_string
);
5139 base_string
= end_scale
;
5140 if (is_space_char (*base_string
))
5142 if (*base_string
!= ')')
5144 as_bad (_("expecting `)' after scale factor in `%s'"),
5149 else if (!i
.index_reg
)
5151 as_bad (_("expecting index register or scale factor after `,'; got '%c'"),
5156 else if (*base_string
!= ')')
5158 as_bad (_("expecting `,' or `)' after base register in `%s'"),
5163 else if (*base_string
== REGISTER_PREFIX
)
5165 as_bad (_("bad register name `%s'"), base_string
);
5170 /* If there's an expression beginning the operand, parse it,
5171 assuming displacement_string_start and
5172 displacement_string_end are meaningful. */
5173 if (displacement_string_start
!= displacement_string_end
)
5175 if (!i386_displacement (displacement_string_start
,
5176 displacement_string_end
))
5180 /* Special case for (%dx) while doing input/output op. */
5182 && i
.base_reg
->reg_type
== (Reg16
| InOutPortReg
)
5184 && i
.log2_scale_factor
== 0
5185 && i
.seg
[i
.mem_operands
] == 0
5186 && (i
.types
[this_operand
] & Disp
) == 0)
5188 i
.types
[this_operand
] = InOutPortReg
;
5192 if (i386_index_check (operand_string
) == 0)
5198 /* It's not a memory operand; argh! */
5199 as_bad (_("invalid char %s beginning operand %d `%s'"),
5200 output_invalid (*op_string
),
5205 return 1; /* Normal return. */
5208 /* md_estimate_size_before_relax()
5210 Called just before relax() for rs_machine_dependent frags. The x86
5211 assembler uses these frags to handle variable size jump
5214 Any symbol that is now undefined will not become defined.
5215 Return the correct fr_subtype in the frag.
5216 Return the initial "guess for variable size of frag" to caller.
5217 The guess is actually the growth beyond the fixed part. Whatever
5218 we do to grow the fixed or variable part contributes to our
5222 md_estimate_size_before_relax (fragP
, segment
)
5226 /* We've already got fragP->fr_subtype right; all we have to do is
5227 check for un-relaxable symbols. On an ELF system, we can't relax
5228 an externally visible symbol, because it may be overridden by a
5230 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
5231 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5233 && (S_IS_EXTERNAL (fragP
->fr_symbol
)
5234 || S_IS_WEAK (fragP
->fr_symbol
)))
5238 /* Symbol is undefined in this segment, or we need to keep a
5239 reloc so that weak symbols can be overridden. */
5240 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
5241 enum bfd_reloc_code_real reloc_type
;
5242 unsigned char *opcode
;
5245 if (fragP
->fr_var
!= NO_RELOC
)
5246 reloc_type
= fragP
->fr_var
;
5248 reloc_type
= BFD_RELOC_16_PCREL
;
5250 reloc_type
= BFD_RELOC_32_PCREL
;
5252 old_fr_fix
= fragP
->fr_fix
;
5253 opcode
= (unsigned char *) fragP
->fr_opcode
;
5255 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
5258 /* Make jmp (0xeb) a (d)word displacement jump. */
5260 fragP
->fr_fix
+= size
;
5261 fix_new (fragP
, old_fr_fix
, size
,
5263 fragP
->fr_offset
, 1,
5269 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
5271 /* Negate the condition, and branch past an
5272 unconditional jump. */
5275 /* Insert an unconditional jump. */
5277 /* We added two extra opcode bytes, and have a two byte
5279 fragP
->fr_fix
+= 2 + 2;
5280 fix_new (fragP
, old_fr_fix
+ 2, 2,
5282 fragP
->fr_offset
, 1,
5289 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
5294 fixP
= fix_new (fragP
, old_fr_fix
, 1,
5296 fragP
->fr_offset
, 1,
5298 fixP
->fx_signed
= 1;
5302 /* This changes the byte-displacement jump 0x7N
5303 to the (d)word-displacement jump 0x0f,0x8N. */
5304 opcode
[1] = opcode
[0] + 0x10;
5305 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
5306 /* We've added an opcode byte. */
5307 fragP
->fr_fix
+= 1 + size
;
5308 fix_new (fragP
, old_fr_fix
+ 1, size
,
5310 fragP
->fr_offset
, 1,
5315 BAD_CASE (fragP
->fr_subtype
);
5319 return fragP
->fr_fix
- old_fr_fix
;
5322 /* Guess size depending on current relax state. Initially the relax
5323 state will correspond to a short jump and we return 1, because
5324 the variable part of the frag (the branch offset) is one byte
5325 long. However, we can relax a section more than once and in that
5326 case we must either set fr_subtype back to the unrelaxed state,
5327 or return the value for the appropriate branch. */
5328 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
5331 /* Called after relax() is finished.
5333 In: Address of frag.
5334 fr_type == rs_machine_dependent.
5335 fr_subtype is what the address relaxed to.
5337 Out: Any fixSs and constants are set up.
5338 Caller will turn frag into a ".space 0". */
5341 md_convert_frag (abfd
, sec
, fragP
)
5342 bfd
*abfd ATTRIBUTE_UNUSED
;
5343 segT sec ATTRIBUTE_UNUSED
;
5346 unsigned char *opcode
;
5347 unsigned char *where_to_put_displacement
= NULL
;
5348 offsetT target_address
;
5349 offsetT opcode_address
;
5350 unsigned int extension
= 0;
5351 offsetT displacement_from_opcode_start
;
5353 opcode
= (unsigned char *) fragP
->fr_opcode
;
5355 /* Address we want to reach in file space. */
5356 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
5358 /* Address opcode resides at in file space. */
5359 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
5361 /* Displacement from opcode start to fill into instruction. */
5362 displacement_from_opcode_start
= target_address
- opcode_address
;
5364 if ((fragP
->fr_subtype
& BIG
) == 0)
5366 /* Don't have to change opcode. */
5367 extension
= 1; /* 1 opcode + 1 displacement */
5368 where_to_put_displacement
= &opcode
[1];
5372 if (no_cond_jump_promotion
5373 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
5374 as_warn_where (fragP
->fr_file
, fragP
->fr_line
, _("long jump required"));
5376 switch (fragP
->fr_subtype
)
5378 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
5379 extension
= 4; /* 1 opcode + 4 displacement */
5381 where_to_put_displacement
= &opcode
[1];
5384 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
5385 extension
= 2; /* 1 opcode + 2 displacement */
5387 where_to_put_displacement
= &opcode
[1];
5390 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
5391 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
5392 extension
= 5; /* 2 opcode + 4 displacement */
5393 opcode
[1] = opcode
[0] + 0x10;
5394 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
5395 where_to_put_displacement
= &opcode
[2];
5398 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
5399 extension
= 3; /* 2 opcode + 2 displacement */
5400 opcode
[1] = opcode
[0] + 0x10;
5401 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
5402 where_to_put_displacement
= &opcode
[2];
5405 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
5410 where_to_put_displacement
= &opcode
[3];
5414 BAD_CASE (fragP
->fr_subtype
);
5419 /* If size if less then four we are sure that the operand fits,
5420 but if it's 4, then it could be that the displacement is larger
5422 if (DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
) == 4
5424 && ((addressT
) (displacement_from_opcode_start
- extension
5425 + ((addressT
) 1 << 31))
5426 > (((addressT
) 2 << 31) - 1)))
5428 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
5429 _("jump target out of range"));
5430 /* Make us emit 0. */
5431 displacement_from_opcode_start
= extension
;
5433 /* Now put displacement after opcode. */
5434 md_number_to_chars ((char *) where_to_put_displacement
,
5435 (valueT
) (displacement_from_opcode_start
- extension
),
5436 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
5437 fragP
->fr_fix
+= extension
;
5440 /* Size of byte displacement jmp. */
5441 int md_short_jump_size
= 2;
5443 /* Size of dword displacement jmp. */
5444 int md_long_jump_size
= 5;
5447 md_create_short_jump (ptr
, from_addr
, to_addr
, frag
, to_symbol
)
5449 addressT from_addr
, to_addr
;
5450 fragS
*frag ATTRIBUTE_UNUSED
;
5451 symbolS
*to_symbol ATTRIBUTE_UNUSED
;
5455 offset
= to_addr
- (from_addr
+ 2);
5456 /* Opcode for byte-disp jump. */
5457 md_number_to_chars (ptr
, (valueT
) 0xeb, 1);
5458 md_number_to_chars (ptr
+ 1, (valueT
) offset
, 1);
5462 md_create_long_jump (ptr
, from_addr
, to_addr
, frag
, to_symbol
)
5464 addressT from_addr
, to_addr
;
5465 fragS
*frag ATTRIBUTE_UNUSED
;
5466 symbolS
*to_symbol ATTRIBUTE_UNUSED
;
5470 offset
= to_addr
- (from_addr
+ 5);
5471 md_number_to_chars (ptr
, (valueT
) 0xe9, 1);
5472 md_number_to_chars (ptr
+ 1, (valueT
) offset
, 4);
5475 /* Apply a fixup (fixS) to segment data, once it has been determined
5476 by our caller that we have all the info we need to fix it up.
5478 On the 386, immediates, displacements, and data pointers are all in
5479 the same (little-endian) format, so we don't need to care about which
5483 md_apply_fix (fixP
, valP
, seg
)
5484 /* The fix we're to put in. */
5486 /* Pointer to the value of the bits. */
5488 /* Segment fix is from. */
5489 segT seg ATTRIBUTE_UNUSED
;
5491 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
5492 valueT value
= *valP
;
5494 #if !defined (TE_Mach)
5497 switch (fixP
->fx_r_type
)
5503 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
5506 case BFD_RELOC_X86_64_32S
:
5507 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
5510 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
5513 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
5518 if (fixP
->fx_addsy
!= NULL
5519 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
5520 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
5521 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
5522 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
5523 && !use_rela_relocations
)
5525 /* This is a hack. There should be a better way to handle this.
5526 This covers for the fact that bfd_install_relocation will
5527 subtract the current location (for partial_inplace, PC relative
5528 relocations); see more below. */
5532 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
5535 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
5537 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5540 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
5543 || (symbol_section_p (fixP
->fx_addsy
)
5544 && sym_seg
!= absolute_section
))
5545 && !generic_force_reloc (fixP
))
5547 /* Yes, we add the values in twice. This is because
5548 bfd_install_relocation subtracts them out again. I think
5549 bfd_install_relocation is broken, but I don't dare change
5551 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
5555 #if defined (OBJ_COFF) && defined (TE_PE)
5556 /* For some reason, the PE format does not store a
5557 section address offset for a PC relative symbol. */
5558 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
5559 || S_IS_WEAK (fixP
->fx_addsy
))
5560 value
+= md_pcrel_from (fixP
);
5564 /* Fix a few things - the dynamic linker expects certain values here,
5565 and we must not disappoint it. */
5566 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5567 if (IS_ELF
&& fixP
->fx_addsy
)
5568 switch (fixP
->fx_r_type
)
5570 case BFD_RELOC_386_PLT32
:
5571 case BFD_RELOC_X86_64_PLT32
:
5572 /* Make the jump instruction point to the address of the operand. At
5573 runtime we merely add the offset to the actual PLT entry. */
5577 case BFD_RELOC_386_TLS_GD
:
5578 case BFD_RELOC_386_TLS_LDM
:
5579 case BFD_RELOC_386_TLS_IE_32
:
5580 case BFD_RELOC_386_TLS_IE
:
5581 case BFD_RELOC_386_TLS_GOTIE
:
5582 case BFD_RELOC_386_TLS_GOTDESC
:
5583 case BFD_RELOC_X86_64_TLSGD
:
5584 case BFD_RELOC_X86_64_TLSLD
:
5585 case BFD_RELOC_X86_64_GOTTPOFF
:
5586 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
5587 value
= 0; /* Fully resolved at runtime. No addend. */
5589 case BFD_RELOC_386_TLS_LE
:
5590 case BFD_RELOC_386_TLS_LDO_32
:
5591 case BFD_RELOC_386_TLS_LE_32
:
5592 case BFD_RELOC_X86_64_DTPOFF32
:
5593 case BFD_RELOC_X86_64_DTPOFF64
:
5594 case BFD_RELOC_X86_64_TPOFF32
:
5595 case BFD_RELOC_X86_64_TPOFF64
:
5596 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
5599 case BFD_RELOC_386_TLS_DESC_CALL
:
5600 case BFD_RELOC_X86_64_TLSDESC_CALL
:
5601 value
= 0; /* Fully resolved at runtime. No addend. */
5602 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
5606 case BFD_RELOC_386_GOT32
:
5607 case BFD_RELOC_X86_64_GOT32
:
5608 value
= 0; /* Fully resolved at runtime. No addend. */
5611 case BFD_RELOC_VTABLE_INHERIT
:
5612 case BFD_RELOC_VTABLE_ENTRY
:
5619 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
5621 #endif /* !defined (TE_Mach) */
5623 /* Are we finished with this relocation now? */
5624 if (fixP
->fx_addsy
== NULL
)
5626 else if (use_rela_relocations
)
5628 fixP
->fx_no_overflow
= 1;
5629 /* Remember value for tc_gen_reloc. */
5630 fixP
->fx_addnumber
= value
;
5634 md_number_to_chars (p
, value
, fixP
->fx_size
);
5637 #define MAX_LITTLENUMS 6
5639 /* Turn the string pointed to by litP into a floating point constant
5640 of type TYPE, and emit the appropriate bytes. The number of
5641 LITTLENUMS emitted is stored in *SIZEP. An error message is
5642 returned, or NULL on OK. */
5645 md_atof (type
, litP
, sizeP
)
5651 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
5652 LITTLENUM_TYPE
*wordP
;
5674 return _("Bad call to md_atof ()");
5676 t
= atof_ieee (input_line_pointer
, type
, words
);
5678 input_line_pointer
= t
;
5680 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
5681 /* This loops outputs the LITTLENUMs in REVERSE order; in accord with
5682 the bigendian 386. */
5683 for (wordP
= words
+ prec
- 1; prec
--;)
5685 md_number_to_chars (litP
, (valueT
) (*wordP
--), sizeof (LITTLENUM_TYPE
));
5686 litP
+= sizeof (LITTLENUM_TYPE
);
5691 static char output_invalid_buf
[sizeof (unsigned char) * 2 + 6];
5698 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
5701 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
5702 "(0x%x)", (unsigned char) c
);
5703 return output_invalid_buf
;
5706 /* REG_STRING starts *before* REGISTER_PREFIX. */
5708 static const reg_entry
*
5709 parse_real_register (char *reg_string
, char **end_op
)
5711 char *s
= reg_string
;
5713 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
5716 /* Skip possible REGISTER_PREFIX and possible whitespace. */
5717 if (*s
== REGISTER_PREFIX
)
5720 if (is_space_char (*s
))
5724 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
5726 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
5727 return (const reg_entry
*) NULL
;
5731 /* For naked regs, make sure that we are not dealing with an identifier.
5732 This prevents confusing an identifier like `eax_var' with register
5734 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
5735 return (const reg_entry
*) NULL
;
5739 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
5741 /* Handle floating point regs, allowing spaces in the (i) part. */
5742 if (r
== i386_regtab
/* %st is first entry of table */)
5744 if (is_space_char (*s
))
5749 if (is_space_char (*s
))
5751 if (*s
>= '0' && *s
<= '7')
5753 r
= &i386_float_regtab
[*s
- '0'];
5755 if (is_space_char (*s
))
5763 /* We have "%st(" then garbage. */
5764 return (const reg_entry
*) NULL
;
5769 && ((r
->reg_flags
& (RegRex64
| RegRex
)) | (r
->reg_type
& Reg64
)) != 0
5770 && (r
->reg_type
!= Control
|| !(cpu_arch_flags
& CpuSledgehammer
))
5771 && flag_code
!= CODE_64BIT
)
5772 return (const reg_entry
*) NULL
;
5777 /* REG_STRING starts *before* REGISTER_PREFIX. */
5779 static const reg_entry
*
5780 parse_register (char *reg_string
, char **end_op
)
5784 if (*reg_string
== REGISTER_PREFIX
|| allow_naked_reg
)
5785 r
= parse_real_register (reg_string
, end_op
);
5790 char *save
= input_line_pointer
;
5794 input_line_pointer
= reg_string
;
5795 c
= get_symbol_end ();
5796 symbolP
= symbol_find (reg_string
);
5797 if (symbolP
&& S_GET_SEGMENT (symbolP
) == reg_section
)
5799 const expressionS
*e
= symbol_get_value_expression (symbolP
);
5801 know (e
->X_op
== O_register
);
5802 know (e
->X_add_number
>= 0 && (valueT
) e
->X_add_number
< ARRAY_SIZE (i386_regtab
));
5803 r
= i386_regtab
+ e
->X_add_number
;
5804 *end_op
= input_line_pointer
;
5806 *input_line_pointer
= c
;
5807 input_line_pointer
= save
;
5813 i386_parse_name (char *name
, expressionS
*e
, char *nextcharP
)
5816 char *end
= input_line_pointer
;
5819 r
= parse_register (name
, &input_line_pointer
);
5820 if (r
&& end
<= input_line_pointer
)
5822 *nextcharP
= *input_line_pointer
;
5823 *input_line_pointer
= 0;
5824 e
->X_op
= O_register
;
5825 e
->X_add_number
= r
- i386_regtab
;
5828 input_line_pointer
= end
;
5834 md_operand (expressionS
*e
)
5836 if (*input_line_pointer
== REGISTER_PREFIX
)
5839 const reg_entry
*r
= parse_real_register (input_line_pointer
, &end
);
5843 e
->X_op
= O_register
;
5844 e
->X_add_number
= r
- i386_regtab
;
5845 input_line_pointer
= end
;
5851 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5852 const char *md_shortopts
= "kVQ:sqn";
5854 const char *md_shortopts
= "qn";
5857 #define OPTION_32 (OPTION_MD_BASE + 0)
5858 #define OPTION_64 (OPTION_MD_BASE + 1)
5859 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
5860 #define OPTION_MARCH (OPTION_MD_BASE + 3)
5861 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
5863 struct option md_longopts
[] =
5865 {"32", no_argument
, NULL
, OPTION_32
},
5866 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
5867 {"64", no_argument
, NULL
, OPTION_64
},
5869 {"divide", no_argument
, NULL
, OPTION_DIVIDE
},
5870 {"march", required_argument
, NULL
, OPTION_MARCH
},
5871 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
5872 {NULL
, no_argument
, NULL
, 0}
5874 size_t md_longopts_size
= sizeof (md_longopts
);
5877 md_parse_option (int c
, char *arg
)
5884 optimize_align_code
= 0;
5891 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5892 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
5893 should be emitted or not. FIXME: Not implemented. */
5897 /* -V: SVR4 argument to print version ID. */
5899 print_version_id ();
5902 /* -k: Ignore for FreeBSD compatibility. */
5907 /* -s: On i386 Solaris, this tells the native assembler to use
5908 .stab instead of .stab.excl. We always use .stab anyhow. */
5911 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
5914 const char **list
, **l
;
5916 list
= bfd_target_list ();
5917 for (l
= list
; *l
!= NULL
; l
++)
5918 if (CONST_STRNEQ (*l
, "elf64-x86-64")
5919 || strcmp (*l
, "coff-x86-64") == 0
5920 || strcmp (*l
, "pe-x86-64") == 0
5921 || strcmp (*l
, "pei-x86-64") == 0)
5923 default_arch
= "x86_64";
5927 as_fatal (_("No compiled in support for x86_64"));
5934 default_arch
= "i386";
5938 #ifdef SVR4_COMMENT_CHARS
5943 n
= (char *) xmalloc (strlen (i386_comment_chars
) + 1);
5945 for (s
= i386_comment_chars
; *s
!= '\0'; s
++)
5949 i386_comment_chars
= n
;
5956 as_fatal (_("Invalid -march= option: `%s'"), arg
);
5957 for (i
= 0; i
< ARRAY_SIZE (cpu_arch
); i
++)
5959 if (strcmp (arg
, cpu_arch
[i
].name
) == 0)
5961 cpu_arch_isa
= cpu_arch
[i
].type
;
5962 cpu_arch_isa_flags
= cpu_arch
[i
].flags
;
5963 if (!cpu_arch_tune_set
)
5965 cpu_arch_tune
= cpu_arch_isa
;
5966 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
5971 if (i
>= ARRAY_SIZE (cpu_arch
))
5972 as_fatal (_("Invalid -march= option: `%s'"), arg
);
5977 as_fatal (_("Invalid -mtune= option: `%s'"), arg
);
5978 for (i
= 0; i
< ARRAY_SIZE (cpu_arch
); i
++)
5980 if (strcmp (arg
, cpu_arch
[i
].name
) == 0)
5982 cpu_arch_tune_set
= 1;
5983 cpu_arch_tune
= cpu_arch
[i
].type
;
5984 cpu_arch_tune_flags
= cpu_arch
[i
].flags
;
5988 if (i
>= ARRAY_SIZE (cpu_arch
))
5989 as_fatal (_("Invalid -mtune= option: `%s'"), arg
);
5999 md_show_usage (stream
)
6002 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
6003 fprintf (stream
, _("\
6005 -V print assembler version number\n\
6008 fprintf (stream
, _("\
6009 -n Do not optimize code alignment\n\
6010 -q quieten some warnings\n"));
6011 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
6012 fprintf (stream
, _("\
6015 #ifdef SVR4_COMMENT_CHARS
6016 fprintf (stream
, _("\
6017 --divide do not treat `/' as a comment character\n"));
6019 fprintf (stream
, _("\
6020 --divide ignored\n"));
6022 fprintf (stream
, _("\
6023 -march=CPU/-mtune=CPU generate code/optimize for CPU, where CPU is one of:\n\
6024 i386, i486, pentium, pentiumpro, pentium4, nocona,\n\
6025 core, core2, k6, athlon, k8, generic32, generic64\n"));
6031 x86_64_target_format (void)
6033 if (strcmp (default_arch
, "x86_64") == 0)
6035 set_code_flag (CODE_64BIT
);
6036 return COFF_TARGET_FORMAT
;
6038 else if (strcmp (default_arch
, "i386") == 0)
6040 set_code_flag (CODE_32BIT
);
6044 as_fatal (_("Unknown architecture"));
6049 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
6050 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
6052 /* Pick the target format to use. */
6055 i386_target_format ()
6057 if (!strcmp (default_arch
, "x86_64"))
6059 set_code_flag (CODE_64BIT
);
6060 if (cpu_arch_isa_flags
== 0)
6061 cpu_arch_isa_flags
= Cpu186
|Cpu286
|Cpu386
|Cpu486
6062 |Cpu586
|Cpu686
|CpuP4
|CpuMMX
|CpuMMX2
6064 if (cpu_arch_tune_flags
== 0)
6065 cpu_arch_tune_flags
= Cpu186
|Cpu286
|Cpu386
|Cpu486
6066 |Cpu586
|Cpu686
|CpuP4
|CpuMMX
|CpuMMX2
6069 else if (!strcmp (default_arch
, "i386"))
6071 set_code_flag (CODE_32BIT
);
6072 if (cpu_arch_isa_flags
== 0)
6073 cpu_arch_isa_flags
= Cpu186
|Cpu286
|Cpu386
;
6074 if (cpu_arch_tune_flags
== 0)
6075 cpu_arch_tune_flags
= Cpu186
|Cpu286
|Cpu386
;
6078 as_fatal (_("Unknown architecture"));
6079 switch (OUTPUT_FLAVOR
)
6081 #ifdef OBJ_MAYBE_AOUT
6082 case bfd_target_aout_flavour
:
6083 return AOUT_TARGET_FORMAT
;
6085 #ifdef OBJ_MAYBE_COFF
6086 case bfd_target_coff_flavour
:
6089 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
6090 case bfd_target_elf_flavour
:
6092 if (flag_code
== CODE_64BIT
)
6095 use_rela_relocations
= 1;
6097 return flag_code
== CODE_64BIT
? ELF_TARGET_FORMAT64
: ELF_TARGET_FORMAT
;
6106 #endif /* OBJ_MAYBE_ more than one */
6108 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
6109 void i386_elf_emit_arch_note ()
6111 if (IS_ELF
&& cpu_arch_name
!= NULL
)
6114 asection
*seg
= now_seg
;
6115 subsegT subseg
= now_subseg
;
6116 Elf_Internal_Note i_note
;
6117 Elf_External_Note e_note
;
6118 asection
*note_secp
;
6121 /* Create the .note section. */
6122 note_secp
= subseg_new (".note", 0);
6123 bfd_set_section_flags (stdoutput
,
6125 SEC_HAS_CONTENTS
| SEC_READONLY
);
6127 /* Process the arch string. */
6128 len
= strlen (cpu_arch_name
);
6130 i_note
.namesz
= len
+ 1;
6132 i_note
.type
= NT_ARCH
;
6133 p
= frag_more (sizeof (e_note
.namesz
));
6134 md_number_to_chars (p
, (valueT
) i_note
.namesz
, sizeof (e_note
.namesz
));
6135 p
= frag_more (sizeof (e_note
.descsz
));
6136 md_number_to_chars (p
, (valueT
) i_note
.descsz
, sizeof (e_note
.descsz
));
6137 p
= frag_more (sizeof (e_note
.type
));
6138 md_number_to_chars (p
, (valueT
) i_note
.type
, sizeof (e_note
.type
));
6139 p
= frag_more (len
+ 1);
6140 strcpy (p
, cpu_arch_name
);
6142 frag_align (2, 0, 0);
6144 subseg_set (seg
, subseg
);
6150 md_undefined_symbol (name
)
6153 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
6154 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
6155 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
6156 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
6160 if (symbol_find (name
))
6161 as_bad (_("GOT already in symbol table"));
6162 GOT_symbol
= symbol_new (name
, undefined_section
,
6163 (valueT
) 0, &zero_address_frag
);
6170 /* Round up a section size to the appropriate boundary. */
6173 md_section_align (segment
, size
)
6174 segT segment ATTRIBUTE_UNUSED
;
6177 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
6178 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
6180 /* For a.out, force the section size to be aligned. If we don't do
6181 this, BFD will align it for us, but it will not write out the
6182 final bytes of the section. This may be a bug in BFD, but it is
6183 easier to fix it here since that is how the other a.out targets
6187 align
= bfd_get_section_alignment (stdoutput
, segment
);
6188 size
= ((size
+ (1 << align
) - 1) & ((valueT
) -1 << align
));
6195 /* On the i386, PC-relative offsets are relative to the start of the
6196 next instruction. That is, the address of the offset, plus its
6197 size, since the offset is always the last part of the insn. */
6200 md_pcrel_from (fixP
)
6203 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
6210 int ignore ATTRIBUTE_UNUSED
;
6214 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
6216 obj_elf_section_change_hook ();
6218 temp
= get_absolute_expression ();
6219 subseg_set (bss_section
, (subsegT
) temp
);
6220 demand_empty_rest_of_line ();
6226 i386_validate_fix (fixp
)
6229 if (fixp
->fx_subsy
&& fixp
->fx_subsy
== GOT_symbol
)
6231 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
6235 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
6240 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
6242 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
6249 tc_gen_reloc (section
, fixp
)
6250 asection
*section ATTRIBUTE_UNUSED
;
6254 bfd_reloc_code_real_type code
;
6256 switch (fixp
->fx_r_type
)
6258 case BFD_RELOC_X86_64_PLT32
:
6259 case BFD_RELOC_X86_64_GOT32
:
6260 case BFD_RELOC_X86_64_GOTPCREL
:
6261 case BFD_RELOC_386_PLT32
:
6262 case BFD_RELOC_386_GOT32
:
6263 case BFD_RELOC_386_GOTOFF
:
6264 case BFD_RELOC_386_GOTPC
:
6265 case BFD_RELOC_386_TLS_GD
:
6266 case BFD_RELOC_386_TLS_LDM
:
6267 case BFD_RELOC_386_TLS_LDO_32
:
6268 case BFD_RELOC_386_TLS_IE_32
:
6269 case BFD_RELOC_386_TLS_IE
:
6270 case BFD_RELOC_386_TLS_GOTIE
:
6271 case BFD_RELOC_386_TLS_LE_32
:
6272 case BFD_RELOC_386_TLS_LE
:
6273 case BFD_RELOC_386_TLS_GOTDESC
:
6274 case BFD_RELOC_386_TLS_DESC_CALL
:
6275 case BFD_RELOC_X86_64_TLSGD
:
6276 case BFD_RELOC_X86_64_TLSLD
:
6277 case BFD_RELOC_X86_64_DTPOFF32
:
6278 case BFD_RELOC_X86_64_DTPOFF64
:
6279 case BFD_RELOC_X86_64_GOTTPOFF
:
6280 case BFD_RELOC_X86_64_TPOFF32
:
6281 case BFD_RELOC_X86_64_TPOFF64
:
6282 case BFD_RELOC_X86_64_GOTOFF64
:
6283 case BFD_RELOC_X86_64_GOTPC32
:
6284 case BFD_RELOC_X86_64_GOT64
:
6285 case BFD_RELOC_X86_64_GOTPCREL64
:
6286 case BFD_RELOC_X86_64_GOTPC64
:
6287 case BFD_RELOC_X86_64_GOTPLT64
:
6288 case BFD_RELOC_X86_64_PLTOFF64
:
6289 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
6290 case BFD_RELOC_X86_64_TLSDESC_CALL
:
6292 case BFD_RELOC_VTABLE_ENTRY
:
6293 case BFD_RELOC_VTABLE_INHERIT
:
6295 case BFD_RELOC_32_SECREL
:
6297 code
= fixp
->fx_r_type
;
6299 case BFD_RELOC_X86_64_32S
:
6300 if (!fixp
->fx_pcrel
)
6302 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
6303 code
= fixp
->fx_r_type
;
6309 switch (fixp
->fx_size
)
6312 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
6313 _("can not do %d byte pc-relative relocation"),
6315 code
= BFD_RELOC_32_PCREL
;
6317 case 1: code
= BFD_RELOC_8_PCREL
; break;
6318 case 2: code
= BFD_RELOC_16_PCREL
; break;
6319 case 4: code
= BFD_RELOC_32_PCREL
; break;
6321 case 8: code
= BFD_RELOC_64_PCREL
; break;
6327 switch (fixp
->fx_size
)
6330 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
6331 _("can not do %d byte relocation"),
6333 code
= BFD_RELOC_32
;
6335 case 1: code
= BFD_RELOC_8
; break;
6336 case 2: code
= BFD_RELOC_16
; break;
6337 case 4: code
= BFD_RELOC_32
; break;
6339 case 8: code
= BFD_RELOC_64
; break;
6346 if ((code
== BFD_RELOC_32
6347 || code
== BFD_RELOC_32_PCREL
6348 || code
== BFD_RELOC_X86_64_32S
)
6350 && fixp
->fx_addsy
== GOT_symbol
)
6353 code
= BFD_RELOC_386_GOTPC
;
6355 code
= BFD_RELOC_X86_64_GOTPC32
;
6357 if ((code
== BFD_RELOC_64
|| code
== BFD_RELOC_64_PCREL
)
6359 && fixp
->fx_addsy
== GOT_symbol
)
6361 code
= BFD_RELOC_X86_64_GOTPC64
;
6364 rel
= (arelent
*) xmalloc (sizeof (arelent
));
6365 rel
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
6366 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
6368 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
6370 if (!use_rela_relocations
)
6372 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
6373 vtable entry to be used in the relocation's section offset. */
6374 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
6375 rel
->address
= fixp
->fx_offset
;
6379 /* Use the rela in 64bit mode. */
6382 if (!fixp
->fx_pcrel
)
6383 rel
->addend
= fixp
->fx_offset
;
6387 case BFD_RELOC_X86_64_PLT32
:
6388 case BFD_RELOC_X86_64_GOT32
:
6389 case BFD_RELOC_X86_64_GOTPCREL
:
6390 case BFD_RELOC_X86_64_TLSGD
:
6391 case BFD_RELOC_X86_64_TLSLD
:
6392 case BFD_RELOC_X86_64_GOTTPOFF
:
6393 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
6394 case BFD_RELOC_X86_64_TLSDESC_CALL
:
6395 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
6398 rel
->addend
= (section
->vma
6400 + fixp
->fx_addnumber
6401 + md_pcrel_from (fixp
));
6406 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
6407 if (rel
->howto
== NULL
)
6409 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
6410 _("cannot represent relocation type %s"),
6411 bfd_get_reloc_code_name (code
));
6412 /* Set howto to a garbage value so that we can keep going. */
6413 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
6414 assert (rel
->howto
!= NULL
);
6421 /* Parse operands using Intel syntax. This implements a recursive descent
6422 parser based on the BNF grammar published in Appendix B of the MASM 6.1
6425 FIXME: We do not recognize the full operand grammar defined in the MASM
6426 documentation. In particular, all the structure/union and
6427 high-level macro operands are missing.
6429 Uppercase words are terminals, lower case words are non-terminals.
6430 Objects surrounded by double brackets '[[' ']]' are optional. Vertical
6431 bars '|' denote choices. Most grammar productions are implemented in
6432 functions called 'intel_<production>'.
6434 Initial production is 'expr'.
6440 binOp & | AND | \| | OR | ^ | XOR
6442 byteRegister AL | AH | BL | BH | CL | CH | DL | DH
6444 constant digits [[ radixOverride ]]
6446 dataType BYTE | WORD | DWORD | FWORD | QWORD | TBYTE | OWORD | XMMWORD
6484 => expr expr cmpOp e04
6487 gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX
6488 | BP | EBP | SP | ESP | DI | EDI | SI | ESI
6490 hexdigit a | b | c | d | e | f
6491 | A | B | C | D | E | F
6497 mulOp * | / | % | MOD | << | SHL | >> | SHR
6501 register specialRegister
6505 segmentRegister CS | DS | ES | FS | GS | SS
6507 specialRegister CR0 | CR2 | CR3 | CR4
6508 | DR0 | DR1 | DR2 | DR3 | DR6 | DR7
6509 | TR3 | TR4 | TR5 | TR6 | TR7
6511 We simplify the grammar in obvious places (e.g., register parsing is
6512 done by calling parse_register) and eliminate immediate left recursion
6513 to implement a recursive-descent parser.
6517 expr' cmpOp e04 expr'
6568 /* Parsing structure for the intel syntax parser. Used to implement the
6569 semantic actions for the operand grammar. */
6570 struct intel_parser_s
6572 char *op_string
; /* The string being parsed. */
6573 int got_a_float
; /* Whether the operand is a float. */
6574 int op_modifier
; /* Operand modifier. */
6575 int is_mem
; /* 1 if operand is memory reference. */
6576 int in_offset
; /* >=1 if parsing operand of offset. */
6577 int in_bracket
; /* >=1 if parsing operand in brackets. */
6578 const reg_entry
*reg
; /* Last register reference found. */
6579 char *disp
; /* Displacement string being built. */
6580 char *next_operand
; /* Resume point when splitting operands. */
6583 static struct intel_parser_s intel_parser
;
6585 /* Token structure for parsing intel syntax. */
6588 int code
; /* Token code. */
6589 const reg_entry
*reg
; /* Register entry for register tokens. */
6590 char *str
; /* String representation. */
6593 static struct intel_token cur_token
, prev_token
;
6595 /* Token codes for the intel parser. Since T_SHORT is already used
6596 by COFF, undefine it first to prevent a warning. */
6615 /* Prototypes for intel parser functions. */
6616 static int intel_match_token
PARAMS ((int code
));
6617 static void intel_get_token
PARAMS ((void));
6618 static void intel_putback_token
PARAMS ((void));
6619 static int intel_expr
PARAMS ((void));
6620 static int intel_e04
PARAMS ((void));
6621 static int intel_e05
PARAMS ((void));
6622 static int intel_e06
PARAMS ((void));
6623 static int intel_e09
PARAMS ((void));
6624 static int intel_bracket_expr
PARAMS ((void));
6625 static int intel_e10
PARAMS ((void));
6626 static int intel_e11
PARAMS ((void));
6629 i386_intel_operand (operand_string
, got_a_float
)
6630 char *operand_string
;
6636 p
= intel_parser
.op_string
= xstrdup (operand_string
);
6637 intel_parser
.disp
= (char *) xmalloc (strlen (operand_string
) + 1);
6641 /* Initialize token holders. */
6642 cur_token
.code
= prev_token
.code
= T_NIL
;
6643 cur_token
.reg
= prev_token
.reg
= NULL
;
6644 cur_token
.str
= prev_token
.str
= NULL
;
6646 /* Initialize parser structure. */
6647 intel_parser
.got_a_float
= got_a_float
;
6648 intel_parser
.op_modifier
= 0;
6649 intel_parser
.is_mem
= 0;
6650 intel_parser
.in_offset
= 0;
6651 intel_parser
.in_bracket
= 0;
6652 intel_parser
.reg
= NULL
;
6653 intel_parser
.disp
[0] = '\0';
6654 intel_parser
.next_operand
= NULL
;
6656 /* Read the first token and start the parser. */
6658 ret
= intel_expr ();
6663 if (cur_token
.code
!= T_NIL
)
6665 as_bad (_("invalid operand for '%s' ('%s' unexpected)"),
6666 current_templates
->start
->name
, cur_token
.str
);
6669 /* If we found a memory reference, hand it over to i386_displacement
6670 to fill in the rest of the operand fields. */
6671 else if (intel_parser
.is_mem
)
6673 if ((i
.mem_operands
== 1
6674 && (current_templates
->start
->opcode_modifier
& IsString
) == 0)
6675 || i
.mem_operands
== 2)
6677 as_bad (_("too many memory references for '%s'"),
6678 current_templates
->start
->name
);
6683 char *s
= intel_parser
.disp
;
6686 if (!quiet_warnings
&& intel_parser
.is_mem
< 0)
6687 /* See the comments in intel_bracket_expr. */
6688 as_warn (_("Treating `%s' as memory reference"), operand_string
);
6690 /* Add the displacement expression. */
6692 ret
= i386_displacement (s
, s
+ strlen (s
));
6695 /* Swap base and index in 16-bit memory operands like
6696 [si+bx]. Since i386_index_check is also used in AT&T
6697 mode we have to do that here. */
6700 && (i
.base_reg
->reg_type
& Reg16
)
6701 && (i
.index_reg
->reg_type
& Reg16
)
6702 && i
.base_reg
->reg_num
>= 6
6703 && i
.index_reg
->reg_num
< 6)
6705 const reg_entry
*base
= i
.index_reg
;
6707 i
.index_reg
= i
.base_reg
;
6710 ret
= i386_index_check (operand_string
);
6715 /* Constant and OFFSET expressions are handled by i386_immediate. */
6716 else if ((intel_parser
.op_modifier
& (1 << T_OFFSET
))
6717 || intel_parser
.reg
== NULL
)
6718 ret
= i386_immediate (intel_parser
.disp
);
6720 if (intel_parser
.next_operand
&& this_operand
>= MAX_OPERANDS
- 1)
6722 if (!ret
|| !intel_parser
.next_operand
)
6724 intel_parser
.op_string
= intel_parser
.next_operand
;
6725 this_operand
= i
.operands
++;
6729 free (intel_parser
.disp
);
6734 #define NUM_ADDRESS_REGS (!!i.base_reg + !!i.index_reg)
6738 expr' cmpOp e04 expr'
6743 /* XXX Implement the comparison operators. */
6744 return intel_e04 ();
6761 if (nregs
>= 0 && NUM_ADDRESS_REGS
> nregs
)
6762 i
.base_reg
= i386_regtab
+ REGNAM_AL
; /* al is invalid as base */
6764 if (cur_token
.code
== '+')
6766 else if (cur_token
.code
== '-')
6767 nregs
= NUM_ADDRESS_REGS
;
6771 strcat (intel_parser
.disp
, cur_token
.str
);
6772 intel_match_token (cur_token
.code
);
6783 int nregs
= ~NUM_ADDRESS_REGS
;
6790 if (cur_token
.code
== '&' || cur_token
.code
== '|' || cur_token
.code
== '^')
6794 str
[0] = cur_token
.code
;
6796 strcat (intel_parser
.disp
, str
);
6801 intel_match_token (cur_token
.code
);
6806 if (nregs
>= 0 && NUM_ADDRESS_REGS
> nregs
)
6807 i
.base_reg
= i386_regtab
+ REGNAM_AL
+ 1; /* cl is invalid as base */
6818 int nregs
= ~NUM_ADDRESS_REGS
;
6825 if (cur_token
.code
== '*' || cur_token
.code
== '/' || cur_token
.code
== '%')
6829 str
[0] = cur_token
.code
;
6831 strcat (intel_parser
.disp
, str
);
6833 else if (cur_token
.code
== T_SHL
)
6834 strcat (intel_parser
.disp
, "<<");
6835 else if (cur_token
.code
== T_SHR
)
6836 strcat (intel_parser
.disp
, ">>");
6840 intel_match_token (cur_token
.code
);
6845 if (nregs
>= 0 && NUM_ADDRESS_REGS
> nregs
)
6846 i
.base_reg
= i386_regtab
+ REGNAM_AL
+ 2; /* dl is invalid as base */
6864 int nregs
= ~NUM_ADDRESS_REGS
;
6869 /* Don't consume constants here. */
6870 if (cur_token
.code
== '+' || cur_token
.code
== '-')
6872 /* Need to look one token ahead - if the next token
6873 is a constant, the current token is its sign. */
6876 intel_match_token (cur_token
.code
);
6877 next_code
= cur_token
.code
;
6878 intel_putback_token ();
6879 if (next_code
== T_CONST
)
6883 /* e09 OFFSET e09 */
6884 if (cur_token
.code
== T_OFFSET
)
6887 ++intel_parser
.in_offset
;
6891 else if (cur_token
.code
== T_SHORT
)
6892 intel_parser
.op_modifier
|= 1 << T_SHORT
;
6895 else if (cur_token
.code
== '+')
6896 strcat (intel_parser
.disp
, "+");
6901 else if (cur_token
.code
== '-' || cur_token
.code
== '~')
6907 str
[0] = cur_token
.code
;
6909 strcat (intel_parser
.disp
, str
);
6916 intel_match_token (cur_token
.code
);
6924 /* e09' PTR e10 e09' */
6925 if (cur_token
.code
== T_PTR
)
6929 if (prev_token
.code
== T_BYTE
)
6930 suffix
= BYTE_MNEM_SUFFIX
;
6932 else if (prev_token
.code
== T_WORD
)
6934 if (current_templates
->start
->name
[0] == 'l'
6935 && current_templates
->start
->name
[2] == 's'
6936 && current_templates
->start
->name
[3] == 0)
6937 suffix
= BYTE_MNEM_SUFFIX
; /* so it will cause an error */
6938 else if (intel_parser
.got_a_float
== 2) /* "fi..." */
6939 suffix
= SHORT_MNEM_SUFFIX
;
6941 suffix
= WORD_MNEM_SUFFIX
;
6944 else if (prev_token
.code
== T_DWORD
)
6946 if (current_templates
->start
->name
[0] == 'l'
6947 && current_templates
->start
->name
[2] == 's'
6948 && current_templates
->start
->name
[3] == 0)
6949 suffix
= WORD_MNEM_SUFFIX
;
6950 else if (flag_code
== CODE_16BIT
6951 && (current_templates
->start
->opcode_modifier
6952 & (Jump
| JumpDword
)))
6953 suffix
= LONG_DOUBLE_MNEM_SUFFIX
;
6954 else if (intel_parser
.got_a_float
== 1) /* "f..." */
6955 suffix
= SHORT_MNEM_SUFFIX
;
6957 suffix
= LONG_MNEM_SUFFIX
;
6960 else if (prev_token
.code
== T_FWORD
)
6962 if (current_templates
->start
->name
[0] == 'l'
6963 && current_templates
->start
->name
[2] == 's'
6964 && current_templates
->start
->name
[3] == 0)
6965 suffix
= LONG_MNEM_SUFFIX
;
6966 else if (!intel_parser
.got_a_float
)
6968 if (flag_code
== CODE_16BIT
)
6969 add_prefix (DATA_PREFIX_OPCODE
);
6970 suffix
= LONG_DOUBLE_MNEM_SUFFIX
;
6973 suffix
= BYTE_MNEM_SUFFIX
; /* so it will cause an error */
6976 else if (prev_token
.code
== T_QWORD
)
6978 if (intel_parser
.got_a_float
== 1) /* "f..." */
6979 suffix
= LONG_MNEM_SUFFIX
;
6981 suffix
= QWORD_MNEM_SUFFIX
;
6984 else if (prev_token
.code
== T_TBYTE
)
6986 if (intel_parser
.got_a_float
== 1)
6987 suffix
= LONG_DOUBLE_MNEM_SUFFIX
;
6989 suffix
= BYTE_MNEM_SUFFIX
; /* so it will cause an error */
6992 else if (prev_token
.code
== T_XMMWORD
)
6994 /* XXX ignored for now, but accepted since gcc uses it */
7000 as_bad (_("Unknown operand modifier `%s'"), prev_token
.str
);
7004 /* Operands for jump/call using 'ptr' notation denote absolute
7006 if (current_templates
->start
->opcode_modifier
& (Jump
| JumpDword
))
7007 i
.types
[this_operand
] |= JumpAbsolute
;
7009 if (current_templates
->start
->base_opcode
== 0x8d /* lea */)
7013 else if (i
.suffix
!= suffix
)
7015 as_bad (_("Conflicting operand modifiers"));
7021 /* e09' : e10 e09' */
7022 else if (cur_token
.code
== ':')
7024 if (prev_token
.code
!= T_REG
)
7026 /* While {call,jmp} SSSS:OOOO is MASM syntax only when SSSS is a
7027 segment/group identifier (which we don't have), using comma
7028 as the operand separator there is even less consistent, since
7029 there all branches only have a single operand. */
7030 if (this_operand
!= 0
7031 || intel_parser
.in_offset
7032 || intel_parser
.in_bracket
7033 || (!(current_templates
->start
->opcode_modifier
7034 & (Jump
|JumpDword
|JumpInterSegment
))
7035 && !(current_templates
->start
->operand_types
[0]
7037 return intel_match_token (T_NIL
);
7038 /* Remember the start of the 2nd operand and terminate 1st
7040 XXX This isn't right, yet (when SSSS:OOOO is right operand of
7041 another expression), but it gets at least the simplest case
7042 (a plain number or symbol on the left side) right. */
7043 intel_parser
.next_operand
= intel_parser
.op_string
;
7044 *--intel_parser
.op_string
= '\0';
7045 return intel_match_token (':');
7053 intel_match_token (cur_token
.code
);
7059 --intel_parser
.in_offset
;
7062 if (NUM_ADDRESS_REGS
> nregs
)
7064 as_bad (_("Invalid operand to `OFFSET'"));
7067 intel_parser
.op_modifier
|= 1 << T_OFFSET
;
7070 if (nregs
>= 0 && NUM_ADDRESS_REGS
> nregs
)
7071 i
.base_reg
= i386_regtab
+ REGNAM_AL
+ 3; /* bl is invalid as base */
7076 intel_bracket_expr ()
7078 int was_offset
= intel_parser
.op_modifier
& (1 << T_OFFSET
);
7079 const char *start
= intel_parser
.op_string
;
7082 if (i
.op
[this_operand
].regs
)
7083 return intel_match_token (T_NIL
);
7085 intel_match_token ('[');
7087 /* Mark as a memory operand only if it's not already known to be an
7088 offset expression. If it's an offset expression, we need to keep
7090 if (!intel_parser
.in_offset
)
7092 ++intel_parser
.in_bracket
;
7094 /* Operands for jump/call inside brackets denote absolute addresses. */
7095 if (current_templates
->start
->opcode_modifier
& (Jump
| JumpDword
))
7096 i
.types
[this_operand
] |= JumpAbsolute
;
7098 /* Unfortunately gas always diverged from MASM in a respect that can't
7099 be easily fixed without risking to break code sequences likely to be
7100 encountered (the testsuite even check for this): MASM doesn't consider
7101 an expression inside brackets unconditionally as a memory reference.
7102 When that is e.g. a constant, an offset expression, or the sum of the
7103 two, this is still taken as a constant load. gas, however, always
7104 treated these as memory references. As a compromise, we'll try to make
7105 offset expressions inside brackets work the MASM way (since that's
7106 less likely to be found in real world code), but make constants alone
7107 continue to work the traditional gas way. In either case, issue a
7109 intel_parser
.op_modifier
&= ~was_offset
;
7112 strcat (intel_parser
.disp
, "[");
7114 /* Add a '+' to the displacement string if necessary. */
7115 if (*intel_parser
.disp
!= '\0'
7116 && *(intel_parser
.disp
+ strlen (intel_parser
.disp
) - 1) != '+')
7117 strcat (intel_parser
.disp
, "+");
7120 && (len
= intel_parser
.op_string
- start
- 1,
7121 intel_match_token (']')))
7123 /* Preserve brackets when the operand is an offset expression. */
7124 if (intel_parser
.in_offset
)
7125 strcat (intel_parser
.disp
, "]");
7128 --intel_parser
.in_bracket
;
7129 if (i
.base_reg
|| i
.index_reg
)
7130 intel_parser
.is_mem
= 1;
7131 if (!intel_parser
.is_mem
)
7133 if (!(intel_parser
.op_modifier
& (1 << T_OFFSET
)))
7134 /* Defer the warning until all of the operand was parsed. */
7135 intel_parser
.is_mem
= -1;
7136 else if (!quiet_warnings
)
7137 as_warn (_("`[%.*s]' taken to mean just `%.*s'"), len
, start
, len
, start
);
7140 intel_parser
.op_modifier
|= was_offset
;
7157 while (cur_token
.code
== '[')
7159 if (!intel_bracket_expr ())
7184 switch (cur_token
.code
)
7188 intel_match_token ('(');
7189 strcat (intel_parser
.disp
, "(");
7191 if (intel_expr () && intel_match_token (')'))
7193 strcat (intel_parser
.disp
, ")");
7200 return intel_bracket_expr ();
7205 strcat (intel_parser
.disp
, cur_token
.str
);
7206 intel_match_token (cur_token
.code
);
7208 /* Mark as a memory operand only if it's not already known to be an
7209 offset expression. */
7210 if (!intel_parser
.in_offset
)
7211 intel_parser
.is_mem
= 1;
7218 const reg_entry
*reg
= intel_parser
.reg
= cur_token
.reg
;
7220 intel_match_token (T_REG
);
7222 /* Check for segment change. */
7223 if (cur_token
.code
== ':')
7225 if (!(reg
->reg_type
& (SReg2
| SReg3
)))
7227 as_bad (_("`%s' is not a valid segment register"), reg
->reg_name
);
7230 else if (i
.seg
[i
.mem_operands
])
7231 as_warn (_("Extra segment override ignored"));
7234 if (!intel_parser
.in_offset
)
7235 intel_parser
.is_mem
= 1;
7236 switch (reg
->reg_num
)
7239 i
.seg
[i
.mem_operands
] = &es
;
7242 i
.seg
[i
.mem_operands
] = &cs
;
7245 i
.seg
[i
.mem_operands
] = &ss
;
7248 i
.seg
[i
.mem_operands
] = &ds
;
7251 i
.seg
[i
.mem_operands
] = &fs
;
7254 i
.seg
[i
.mem_operands
] = &gs
;
7260 /* Not a segment register. Check for register scaling. */
7261 else if (cur_token
.code
== '*')
7263 if (!intel_parser
.in_bracket
)
7265 as_bad (_("Register scaling only allowed in memory operands"));
7269 if (reg
->reg_type
& Reg16
) /* Disallow things like [si*1]. */
7270 reg
= i386_regtab
+ REGNAM_AX
+ 4; /* sp is invalid as index */
7271 else if (i
.index_reg
)
7272 reg
= i386_regtab
+ REGNAM_EAX
+ 4; /* esp is invalid as index */
7274 /* What follows must be a valid scale. */
7275 intel_match_token ('*');
7277 i
.types
[this_operand
] |= BaseIndex
;
7279 /* Set the scale after setting the register (otherwise,
7280 i386_scale will complain) */
7281 if (cur_token
.code
== '+' || cur_token
.code
== '-')
7283 char *str
, sign
= cur_token
.code
;
7284 intel_match_token (cur_token
.code
);
7285 if (cur_token
.code
!= T_CONST
)
7287 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
7291 str
= (char *) xmalloc (strlen (cur_token
.str
) + 2);
7292 strcpy (str
+ 1, cur_token
.str
);
7294 if (!i386_scale (str
))
7298 else if (!i386_scale (cur_token
.str
))
7300 intel_match_token (cur_token
.code
);
7303 /* No scaling. If this is a memory operand, the register is either a
7304 base register (first occurrence) or an index register (second
7306 else if (intel_parser
.in_bracket
)
7311 else if (!i
.index_reg
)
7315 as_bad (_("Too many register references in memory operand"));
7319 i
.types
[this_operand
] |= BaseIndex
;
7322 /* It's neither base nor index. */
7323 else if (!intel_parser
.in_offset
&& !intel_parser
.is_mem
)
7325 i
.types
[this_operand
] |= reg
->reg_type
& ~BaseIndex
;
7326 i
.op
[this_operand
].regs
= reg
;
7331 as_bad (_("Invalid use of register"));
7335 /* Since registers are not part of the displacement string (except
7336 when we're parsing offset operands), we may need to remove any
7337 preceding '+' from the displacement string. */
7338 if (*intel_parser
.disp
!= '\0'
7339 && !intel_parser
.in_offset
)
7341 char *s
= intel_parser
.disp
;
7342 s
+= strlen (s
) - 1;
7365 intel_match_token (cur_token
.code
);
7367 if (cur_token
.code
== T_PTR
)
7370 /* It must have been an identifier. */
7371 intel_putback_token ();
7372 cur_token
.code
= T_ID
;
7378 if (!intel_parser
.in_offset
&& intel_parser
.is_mem
<= 0)
7382 /* The identifier represents a memory reference only if it's not
7383 preceded by an offset modifier and if it's not an equate. */
7384 symbolP
= symbol_find(cur_token
.str
);
7385 if (!symbolP
|| S_GET_SEGMENT(symbolP
) != absolute_section
)
7386 intel_parser
.is_mem
= 1;
7394 char *save_str
, sign
= 0;
7396 /* Allow constants that start with `+' or `-'. */
7397 if (cur_token
.code
== '-' || cur_token
.code
== '+')
7399 sign
= cur_token
.code
;
7400 intel_match_token (cur_token
.code
);
7401 if (cur_token
.code
!= T_CONST
)
7403 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
7409 save_str
= (char *) xmalloc (strlen (cur_token
.str
) + 2);
7410 strcpy (save_str
+ !!sign
, cur_token
.str
);
7414 /* Get the next token to check for register scaling. */
7415 intel_match_token (cur_token
.code
);
7417 /* Check if this constant is a scaling factor for an index register. */
7418 if (cur_token
.code
== '*')
7420 if (intel_match_token ('*') && cur_token
.code
== T_REG
)
7422 const reg_entry
*reg
= cur_token
.reg
;
7424 if (!intel_parser
.in_bracket
)
7426 as_bad (_("Register scaling only allowed in memory operands"));
7430 if (reg
->reg_type
& Reg16
) /* Disallow things like [1*si]. */
7431 reg
= i386_regtab
+ REGNAM_AX
+ 4; /* sp is invalid as index */
7432 else if (i
.index_reg
)
7433 reg
= i386_regtab
+ REGNAM_EAX
+ 4; /* esp is invalid as index */
7435 /* The constant is followed by `* reg', so it must be
7438 i
.types
[this_operand
] |= BaseIndex
;
7440 /* Set the scale after setting the register (otherwise,
7441 i386_scale will complain) */
7442 if (!i386_scale (save_str
))
7444 intel_match_token (T_REG
);
7446 /* Since registers are not part of the displacement
7447 string, we may need to remove any preceding '+' from
7448 the displacement string. */
7449 if (*intel_parser
.disp
!= '\0')
7451 char *s
= intel_parser
.disp
;
7452 s
+= strlen (s
) - 1;
7462 /* The constant was not used for register scaling. Since we have
7463 already consumed the token following `*' we now need to put it
7464 back in the stream. */
7465 intel_putback_token ();
7468 /* Add the constant to the displacement string. */
7469 strcat (intel_parser
.disp
, save_str
);
7476 as_bad (_("Unrecognized token '%s'"), cur_token
.str
);
7480 /* Match the given token against cur_token. If they match, read the next
7481 token from the operand string. */
7483 intel_match_token (code
)
7486 if (cur_token
.code
== code
)
7493 as_bad (_("Unexpected token `%s'"), cur_token
.str
);
7498 /* Read a new token from intel_parser.op_string and store it in cur_token. */
7503 const reg_entry
*reg
;
7504 struct intel_token new_token
;
7506 new_token
.code
= T_NIL
;
7507 new_token
.reg
= NULL
;
7508 new_token
.str
= NULL
;
7510 /* Free the memory allocated to the previous token and move
7511 cur_token to prev_token. */
7513 free (prev_token
.str
);
7515 prev_token
= cur_token
;
7517 /* Skip whitespace. */
7518 while (is_space_char (*intel_parser
.op_string
))
7519 intel_parser
.op_string
++;
7521 /* Return an empty token if we find nothing else on the line. */
7522 if (*intel_parser
.op_string
== '\0')
7524 cur_token
= new_token
;
7528 /* The new token cannot be larger than the remainder of the operand
7530 new_token
.str
= (char *) xmalloc (strlen (intel_parser
.op_string
) + 1);
7531 new_token
.str
[0] = '\0';
7533 if (strchr ("0123456789", *intel_parser
.op_string
))
7535 char *p
= new_token
.str
;
7536 char *q
= intel_parser
.op_string
;
7537 new_token
.code
= T_CONST
;
7539 /* Allow any kind of identifier char to encompass floating point and
7540 hexadecimal numbers. */
7541 while (is_identifier_char (*q
))
7545 /* Recognize special symbol names [0-9][bf]. */
7546 if (strlen (intel_parser
.op_string
) == 2
7547 && (intel_parser
.op_string
[1] == 'b'
7548 || intel_parser
.op_string
[1] == 'f'))
7549 new_token
.code
= T_ID
;
7552 else if ((reg
= parse_register (intel_parser
.op_string
, &end_op
)) != NULL
)
7554 size_t len
= end_op
- intel_parser
.op_string
;
7556 new_token
.code
= T_REG
;
7557 new_token
.reg
= reg
;
7559 memcpy (new_token
.str
, intel_parser
.op_string
, len
);
7560 new_token
.str
[len
] = '\0';
7563 else if (is_identifier_char (*intel_parser
.op_string
))
7565 char *p
= new_token
.str
;
7566 char *q
= intel_parser
.op_string
;
7568 /* A '.' or '$' followed by an identifier char is an identifier.
7569 Otherwise, it's operator '.' followed by an expression. */
7570 if ((*q
== '.' || *q
== '$') && !is_identifier_char (*(q
+ 1)))
7572 new_token
.code
= '.';
7573 new_token
.str
[0] = '.';
7574 new_token
.str
[1] = '\0';
7578 while (is_identifier_char (*q
) || *q
== '@')
7582 if (strcasecmp (new_token
.str
, "NOT") == 0)
7583 new_token
.code
= '~';
7585 else if (strcasecmp (new_token
.str
, "MOD") == 0)
7586 new_token
.code
= '%';
7588 else if (strcasecmp (new_token
.str
, "AND") == 0)
7589 new_token
.code
= '&';
7591 else if (strcasecmp (new_token
.str
, "OR") == 0)
7592 new_token
.code
= '|';
7594 else if (strcasecmp (new_token
.str
, "XOR") == 0)
7595 new_token
.code
= '^';
7597 else if (strcasecmp (new_token
.str
, "SHL") == 0)
7598 new_token
.code
= T_SHL
;
7600 else if (strcasecmp (new_token
.str
, "SHR") == 0)
7601 new_token
.code
= T_SHR
;
7603 else if (strcasecmp (new_token
.str
, "BYTE") == 0)
7604 new_token
.code
= T_BYTE
;
7606 else if (strcasecmp (new_token
.str
, "WORD") == 0)
7607 new_token
.code
= T_WORD
;
7609 else if (strcasecmp (new_token
.str
, "DWORD") == 0)
7610 new_token
.code
= T_DWORD
;
7612 else if (strcasecmp (new_token
.str
, "FWORD") == 0)
7613 new_token
.code
= T_FWORD
;
7615 else if (strcasecmp (new_token
.str
, "QWORD") == 0)
7616 new_token
.code
= T_QWORD
;
7618 else if (strcasecmp (new_token
.str
, "TBYTE") == 0
7619 /* XXX remove (gcc still uses it) */
7620 || strcasecmp (new_token
.str
, "XWORD") == 0)
7621 new_token
.code
= T_TBYTE
;
7623 else if (strcasecmp (new_token
.str
, "XMMWORD") == 0
7624 || strcasecmp (new_token
.str
, "OWORD") == 0)
7625 new_token
.code
= T_XMMWORD
;
7627 else if (strcasecmp (new_token
.str
, "PTR") == 0)
7628 new_token
.code
= T_PTR
;
7630 else if (strcasecmp (new_token
.str
, "SHORT") == 0)
7631 new_token
.code
= T_SHORT
;
7633 else if (strcasecmp (new_token
.str
, "OFFSET") == 0)
7635 new_token
.code
= T_OFFSET
;
7637 /* ??? This is not mentioned in the MASM grammar but gcc
7638 makes use of it with -mintel-syntax. OFFSET may be
7639 followed by FLAT: */
7640 if (strncasecmp (q
, " FLAT:", 6) == 0)
7641 strcat (new_token
.str
, " FLAT:");
7644 /* ??? This is not mentioned in the MASM grammar. */
7645 else if (strcasecmp (new_token
.str
, "FLAT") == 0)
7647 new_token
.code
= T_OFFSET
;
7649 strcat (new_token
.str
, ":");
7651 as_bad (_("`:' expected"));
7655 new_token
.code
= T_ID
;
7659 else if (strchr ("+-/*%|&^:[]()~", *intel_parser
.op_string
))
7661 new_token
.code
= *intel_parser
.op_string
;
7662 new_token
.str
[0] = *intel_parser
.op_string
;
7663 new_token
.str
[1] = '\0';
7666 else if (strchr ("<>", *intel_parser
.op_string
)
7667 && *intel_parser
.op_string
== *(intel_parser
.op_string
+ 1))
7669 new_token
.code
= *intel_parser
.op_string
== '<' ? T_SHL
: T_SHR
;
7670 new_token
.str
[0] = *intel_parser
.op_string
;
7671 new_token
.str
[1] = *intel_parser
.op_string
;
7672 new_token
.str
[2] = '\0';
7676 as_bad (_("Unrecognized token `%s'"), intel_parser
.op_string
);
7678 intel_parser
.op_string
+= strlen (new_token
.str
);
7679 cur_token
= new_token
;
7682 /* Put cur_token back into the token stream and make cur_token point to
7685 intel_putback_token ()
7687 if (cur_token
.code
!= T_NIL
)
7689 intel_parser
.op_string
-= strlen (cur_token
.str
);
7690 free (cur_token
.str
);
7692 cur_token
= prev_token
;
7694 /* Forget prev_token. */
7695 prev_token
.code
= T_NIL
;
7696 prev_token
.reg
= NULL
;
7697 prev_token
.str
= NULL
;
7701 tc_x86_regname_to_dw2regnum (char *regname
)
7703 unsigned int regnum
;
7704 unsigned int regnames_count
;
7705 static const char *const regnames_32
[] =
7707 "eax", "ecx", "edx", "ebx",
7708 "esp", "ebp", "esi", "edi",
7709 "eip", "eflags", NULL
,
7710 "st0", "st1", "st2", "st3",
7711 "st4", "st5", "st6", "st7",
7713 "xmm0", "xmm1", "xmm2", "xmm3",
7714 "xmm4", "xmm5", "xmm6", "xmm7",
7715 "mm0", "mm1", "mm2", "mm3",
7716 "mm4", "mm5", "mm6", "mm7",
7717 "fcw", "fsw", "mxcsr",
7718 "es", "cs", "ss", "ds", "fs", "gs", NULL
, NULL
,
7721 static const char *const regnames_64
[] =
7723 "rax", "rdx", "rcx", "rbx",
7724 "rsi", "rdi", "rbp", "rsp",
7725 "r8", "r9", "r10", "r11",
7726 "r12", "r13", "r14", "r15",
7728 "xmm0", "xmm1", "xmm2", "xmm3",
7729 "xmm4", "xmm5", "xmm6", "xmm7",
7730 "xmm8", "xmm9", "xmm10", "xmm11",
7731 "xmm12", "xmm13", "xmm14", "xmm15",
7732 "st0", "st1", "st2", "st3",
7733 "st4", "st5", "st6", "st7",
7734 "mm0", "mm1", "mm2", "mm3",
7735 "mm4", "mm5", "mm6", "mm7",
7737 "es", "cs", "ss", "ds", "fs", "gs", NULL
, NULL
,
7738 "fs.base", "gs.base", NULL
, NULL
,
7740 "mxcsr", "fcw", "fsw"
7742 const char *const *regnames
;
7744 if (flag_code
== CODE_64BIT
)
7746 regnames
= regnames_64
;
7747 regnames_count
= ARRAY_SIZE (regnames_64
);
7751 regnames
= regnames_32
;
7752 regnames_count
= ARRAY_SIZE (regnames_32
);
7755 for (regnum
= 0; regnum
< regnames_count
; regnum
++)
7756 if (regnames
[regnum
] != NULL
7757 && strcmp (regname
, regnames
[regnum
]) == 0)
7764 tc_x86_frame_initial_instructions (void)
7766 static unsigned int sp_regno
;
7769 sp_regno
= tc_x86_regname_to_dw2regnum (flag_code
== CODE_64BIT
7772 cfi_add_CFA_def_cfa (sp_regno
, -x86_cie_data_alignment
);
7773 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
7777 i386_elf_section_type (const char *str
, size_t len
)
7779 if (flag_code
== CODE_64BIT
7780 && len
== sizeof ("unwind") - 1
7781 && strncmp (str
, "unwind", 6) == 0)
7782 return SHT_X86_64_UNWIND
;
7789 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
7793 expr
.X_op
= O_secrel
;
7794 expr
.X_add_symbol
= symbol
;
7795 expr
.X_add_number
= 0;
7796 emit_expr (&expr
, size
);
7800 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7801 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
7804 x86_64_section_letter (int letter
, char **ptr_msg
)
7806 if (flag_code
== CODE_64BIT
)
7809 return SHF_X86_64_LARGE
;
7811 *ptr_msg
= _("Bad .section directive: want a,l,w,x,M,S,G,T in string");
7814 *ptr_msg
= _("Bad .section directive: want a,w,x,M,S,G,T in string");
7819 x86_64_section_word (char *str
, size_t len
)
7821 if (len
== 5 && flag_code
== CODE_64BIT
&& CONST_STRNEQ (str
, "large"))
7822 return SHF_X86_64_LARGE
;
7828 handle_large_common (int small ATTRIBUTE_UNUSED
)
7830 if (flag_code
!= CODE_64BIT
)
7832 s_comm_internal (0, elf_common_parse
);
7833 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
7837 static segT lbss_section
;
7838 asection
*saved_com_section_ptr
= elf_com_section_ptr
;
7839 asection
*saved_bss_section
= bss_section
;
7841 if (lbss_section
== NULL
)
7843 flagword applicable
;
7845 subsegT subseg
= now_subseg
;
7847 /* The .lbss section is for local .largecomm symbols. */
7848 lbss_section
= subseg_new (".lbss", 0);
7849 applicable
= bfd_applicable_section_flags (stdoutput
);
7850 bfd_set_section_flags (stdoutput
, lbss_section
,
7851 applicable
& SEC_ALLOC
);
7852 seg_info (lbss_section
)->bss
= 1;
7854 subseg_set (seg
, subseg
);
7857 elf_com_section_ptr
= &_bfd_elf_large_com_section
;
7858 bss_section
= lbss_section
;
7860 s_comm_internal (0, elf_common_parse
);
7862 elf_com_section_ptr
= saved_com_section_ptr
;
7863 bss_section
= saved_bss_section
;
7866 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */