1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright (C) 1989-2018 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 /* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
23 x86_64 support by Jan Hubicka (jh@suse.cz)
24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
29 #include "safe-ctype.h"
31 #include "dwarf2dbg.h"
32 #include "dw2gencfi.h"
33 #include "elf/x86-64.h"
34 #include "opcodes/i386-init.h"
36 #ifndef REGISTER_WARNINGS
37 #define REGISTER_WARNINGS 1
40 #ifndef INFER_ADDR_PREFIX
41 #define INFER_ADDR_PREFIX 1
45 #define DEFAULT_ARCH "i386"
50 #define INLINE __inline__
56 /* Prefixes will be emitted in the order defined below.
57 WAIT_PREFIX must be the first prefix since FWAIT is really is an
58 instruction, and so must come before any prefixes.
59 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
60 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
66 #define HLE_PREFIX REP_PREFIX
67 #define BND_PREFIX REP_PREFIX
69 #define REX_PREFIX 6 /* must come last. */
70 #define MAX_PREFIXES 7 /* max prefixes per opcode */
72 /* we define the syntax here (modulo base,index,scale syntax) */
73 #define REGISTER_PREFIX '%'
74 #define IMMEDIATE_PREFIX '$'
75 #define ABSOLUTE_PREFIX '*'
77 /* these are the instruction mnemonic suffixes in AT&T syntax or
78 memory operand size in Intel syntax. */
79 #define WORD_MNEM_SUFFIX 'w'
80 #define BYTE_MNEM_SUFFIX 'b'
81 #define SHORT_MNEM_SUFFIX 's'
82 #define LONG_MNEM_SUFFIX 'l'
83 #define QWORD_MNEM_SUFFIX 'q'
84 /* Intel Syntax. Use a non-ascii letter since since it never appears
86 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
88 #define END_OF_INSN '\0'
91 'templates' is for grouping together 'template' structures for opcodes
92 of the same name. This is only used for storing the insns in the grand
93 ole hash table of insns.
94 The templates themselves start at START and range up to (but not including)
99 const insn_template
*start
;
100 const insn_template
*end
;
104 /* 386 operand encoding bytes: see 386 book for details of this. */
107 unsigned int regmem
; /* codes register or memory operand */
108 unsigned int reg
; /* codes register operand (or extended opcode) */
109 unsigned int mode
; /* how to interpret regmem & reg */
113 /* x86-64 extension prefix. */
114 typedef int rex_byte
;
116 /* 386 opcode byte to code indirect addressing. */
125 /* x86 arch names, types and features */
128 const char *name
; /* arch name */
129 unsigned int len
; /* arch string length */
130 enum processor_type type
; /* arch type */
131 i386_cpu_flags flags
; /* cpu feature flags */
132 unsigned int skip
; /* show_arch should skip this. */
136 /* Used to turn off indicated flags. */
139 const char *name
; /* arch name */
140 unsigned int len
; /* arch string length */
141 i386_cpu_flags flags
; /* cpu feature flags */
145 static void update_code_flag (int, int);
146 static void set_code_flag (int);
147 static void set_16bit_gcc_code_flag (int);
148 static void set_intel_syntax (int);
149 static void set_intel_mnemonic (int);
150 static void set_allow_index_reg (int);
151 static void set_check (int);
152 static void set_cpu_arch (int);
154 static void pe_directive_secrel (int);
156 static void signed_cons (int);
157 static char *output_invalid (int c
);
158 static int i386_finalize_immediate (segT
, expressionS
*, i386_operand_type
,
160 static int i386_finalize_displacement (segT
, expressionS
*, i386_operand_type
,
162 static int i386_att_operand (char *);
163 static int i386_intel_operand (char *, int);
164 static int i386_intel_simplify (expressionS
*);
165 static int i386_intel_parse_name (const char *, expressionS
*);
166 static const reg_entry
*parse_register (char *, char **);
167 static char *parse_insn (char *, char *);
168 static char *parse_operands (char *, const char *);
169 static void swap_operands (void);
170 static void swap_2_operands (int, int);
171 static void optimize_imm (void);
172 static void optimize_disp (void);
173 static const insn_template
*match_template (char);
174 static int check_string (void);
175 static int process_suffix (void);
176 static int check_byte_reg (void);
177 static int check_long_reg (void);
178 static int check_qword_reg (void);
179 static int check_word_reg (void);
180 static int finalize_imm (void);
181 static int process_operands (void);
182 static const seg_entry
*build_modrm_byte (void);
183 static void output_insn (void);
184 static void output_imm (fragS
*, offsetT
);
185 static void output_disp (fragS
*, offsetT
);
187 static void s_bss (int);
189 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
190 static void handle_large_common (int small ATTRIBUTE_UNUSED
);
193 static const char *default_arch
= DEFAULT_ARCH
;
195 /* This struct describes rounding control and SAE in the instruction. */
209 static struct RC_Operation rc_op
;
211 /* The struct describes masking, applied to OPERAND in the instruction.
212 MASK is a pointer to the corresponding mask register. ZEROING tells
213 whether merging or zeroing mask is used. */
214 struct Mask_Operation
216 const reg_entry
*mask
;
217 unsigned int zeroing
;
218 /* The operand where this operation is associated. */
222 static struct Mask_Operation mask_op
;
224 /* The struct describes broadcasting, applied to OPERAND. FACTOR is
226 struct Broadcast_Operation
228 /* Type of broadcast: {1to2}, {1to4}, {1to8}, or {1to16}. */
231 /* Index of broadcasted operand. */
235 static struct Broadcast_Operation broadcast_op
;
240 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
241 unsigned char bytes
[4];
243 /* Destination or source register specifier. */
244 const reg_entry
*register_specifier
;
247 /* 'md_assemble ()' gathers together information and puts it into a
254 const reg_entry
*regs
;
259 operand_size_mismatch
,
260 operand_type_mismatch
,
261 register_type_mismatch
,
262 number_of_operands_mismatch
,
263 invalid_instruction_suffix
,
265 unsupported_with_intel_mnemonic
,
268 invalid_vsib_address
,
269 invalid_vector_register_set
,
270 unsupported_vector_index_register
,
271 unsupported_broadcast
,
272 broadcast_not_on_src_operand
,
275 mask_not_on_destination
,
278 rc_sae_operand_not_last_imm
,
279 invalid_register_operand
,
284 /* TM holds the template for the insn were currently assembling. */
287 /* SUFFIX holds the instruction size suffix for byte, word, dword
288 or qword, if given. */
291 /* OPERANDS gives the number of given operands. */
292 unsigned int operands
;
294 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
295 of given register, displacement, memory operands and immediate
297 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
299 /* TYPES [i] is the type (see above #defines) which tells us how to
300 use OP[i] for the corresponding operand. */
301 i386_operand_type types
[MAX_OPERANDS
];
303 /* Displacement expression, immediate expression, or register for each
305 union i386_op op
[MAX_OPERANDS
];
307 /* Flags for operands. */
308 unsigned int flags
[MAX_OPERANDS
];
309 #define Operand_PCrel 1
311 /* Relocation type for operand */
312 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
314 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
315 the base index byte below. */
316 const reg_entry
*base_reg
;
317 const reg_entry
*index_reg
;
318 unsigned int log2_scale_factor
;
320 /* SEG gives the seg_entries of this insn. They are zero unless
321 explicit segment overrides are given. */
322 const seg_entry
*seg
[2];
324 /* Copied first memory operand string, for re-checking. */
327 /* PREFIX holds all the given prefix opcodes (usually null).
328 PREFIXES is the number of prefix opcodes. */
329 unsigned int prefixes
;
330 unsigned char prefix
[MAX_PREFIXES
];
332 /* RM and SIB are the modrm byte and the sib byte where the
333 addressing modes of this insn are encoded. */
340 /* Masking attributes. */
341 struct Mask_Operation
*mask
;
343 /* Rounding control and SAE attributes. */
344 struct RC_Operation
*rounding
;
346 /* Broadcasting attributes. */
347 struct Broadcast_Operation
*broadcast
;
349 /* Compressed disp8*N attribute. */
350 unsigned int memshift
;
352 /* Prefer load or store in encoding. */
355 dir_encoding_default
= 0,
360 /* Prefer 8bit or 32bit displacement in encoding. */
363 disp_encoding_default
= 0,
368 /* Prefer the REX byte in encoding. */
369 bfd_boolean rex_encoding
;
371 /* Disable instruction size optimization. */
372 bfd_boolean no_optimize
;
374 /* How to encode vector instructions. */
377 vex_encoding_default
= 0,
384 const char *rep_prefix
;
387 const char *hle_prefix
;
389 /* Have BND prefix. */
390 const char *bnd_prefix
;
392 /* Have NOTRACK prefix. */
393 const char *notrack_prefix
;
396 enum i386_error error
;
399 typedef struct _i386_insn i386_insn
;
401 /* Link RC type with corresponding string, that'll be looked for in
410 static const struct RC_name RC_NamesTable
[] =
412 { rne
, STRING_COMMA_LEN ("rn-sae") },
413 { rd
, STRING_COMMA_LEN ("rd-sae") },
414 { ru
, STRING_COMMA_LEN ("ru-sae") },
415 { rz
, STRING_COMMA_LEN ("rz-sae") },
416 { saeonly
, STRING_COMMA_LEN ("sae") },
419 /* List of chars besides those in app.c:symbol_chars that can start an
420 operand. Used to prevent the scrubber eating vital white-space. */
421 const char extra_symbol_chars
[] = "*%-([{}"
430 #if (defined (TE_I386AIX) \
431 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
432 && !defined (TE_GNU) \
433 && !defined (TE_LINUX) \
434 && !defined (TE_NACL) \
435 && !defined (TE_FreeBSD) \
436 && !defined (TE_DragonFly) \
437 && !defined (TE_NetBSD)))
438 /* This array holds the chars that always start a comment. If the
439 pre-processor is disabled, these aren't very useful. The option
440 --divide will remove '/' from this list. */
441 const char *i386_comment_chars
= "#/";
442 #define SVR4_COMMENT_CHARS 1
443 #define PREFIX_SEPARATOR '\\'
446 const char *i386_comment_chars
= "#";
447 #define PREFIX_SEPARATOR '/'
450 /* This array holds the chars that only start a comment at the beginning of
451 a line. If the line seems to have the form '# 123 filename'
452 .line and .file directives will appear in the pre-processed output.
453 Note that input_file.c hand checks for '#' at the beginning of the
454 first line of the input file. This is because the compiler outputs
455 #NO_APP at the beginning of its output.
456 Also note that comments started like this one will always work if
457 '/' isn't otherwise defined. */
458 const char line_comment_chars
[] = "#/";
460 const char line_separator_chars
[] = ";";
462 /* Chars that can be used to separate mant from exp in floating point
464 const char EXP_CHARS
[] = "eE";
466 /* Chars that mean this number is a floating point constant
469 const char FLT_CHARS
[] = "fFdDxX";
471 /* Tables for lexical analysis. */
472 static char mnemonic_chars
[256];
473 static char register_chars
[256];
474 static char operand_chars
[256];
475 static char identifier_chars
[256];
476 static char digit_chars
[256];
478 /* Lexical macros. */
479 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
480 #define is_operand_char(x) (operand_chars[(unsigned char) x])
481 #define is_register_char(x) (register_chars[(unsigned char) x])
482 #define is_space_char(x) ((x) == ' ')
483 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
484 #define is_digit_char(x) (digit_chars[(unsigned char) x])
486 /* All non-digit non-letter characters that may occur in an operand. */
487 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
489 /* md_assemble() always leaves the strings it's passed unaltered. To
490 effect this we maintain a stack of saved characters that we've smashed
491 with '\0's (indicating end of strings for various sub-fields of the
492 assembler instruction). */
493 static char save_stack
[32];
494 static char *save_stack_p
;
495 #define END_STRING_AND_SAVE(s) \
496 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
497 #define RESTORE_END_STRING(s) \
498 do { *(s) = *--save_stack_p; } while (0)
500 /* The instruction we're assembling. */
503 /* Possible templates for current insn. */
504 static const templates
*current_templates
;
506 /* Per instruction expressionS buffers: max displacements & immediates. */
507 static expressionS disp_expressions
[MAX_MEMORY_OPERANDS
];
508 static expressionS im_expressions
[MAX_IMMEDIATE_OPERANDS
];
510 /* Current operand we are working on. */
511 static int this_operand
= -1;
513 /* We support four different modes. FLAG_CODE variable is used to distinguish
521 static enum flag_code flag_code
;
522 static unsigned int object_64bit
;
523 static unsigned int disallow_64bit_reloc
;
524 static int use_rela_relocations
= 0;
526 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
527 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
528 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
530 /* The ELF ABI to use. */
538 static enum x86_elf_abi x86_elf_abi
= I386_ABI
;
541 #if defined (TE_PE) || defined (TE_PEP)
542 /* Use big object file format. */
543 static int use_big_obj
= 0;
546 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
547 /* 1 if generating code for a shared library. */
548 static int shared
= 0;
551 /* 1 for intel syntax,
553 static int intel_syntax
= 0;
555 /* 1 for Intel64 ISA,
559 /* 1 for intel mnemonic,
560 0 if att mnemonic. */
561 static int intel_mnemonic
= !SYSV386_COMPAT
;
563 /* 1 if pseudo registers are permitted. */
564 static int allow_pseudo_reg
= 0;
566 /* 1 if register prefix % not required. */
567 static int allow_naked_reg
= 0;
569 /* 1 if the assembler should add BND prefix for all control-transferring
570 instructions supporting it, even if this prefix wasn't specified
572 static int add_bnd_prefix
= 0;
574 /* 1 if pseudo index register, eiz/riz, is allowed . */
575 static int allow_index_reg
= 0;
577 /* 1 if the assembler should ignore LOCK prefix, even if it was
578 specified explicitly. */
579 static int omit_lock_prefix
= 0;
581 /* 1 if the assembler should encode lfence, mfence, and sfence as
582 "lock addl $0, (%{re}sp)". */
583 static int avoid_fence
= 0;
585 /* 1 if the assembler should generate relax relocations. */
587 static int generate_relax_relocations
588 = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS
;
590 static enum check_kind
596 sse_check
, operand_check
= check_warning
;
599 1. Clear the REX_W bit with register operand if possible.
600 2. Above plus use 128bit vector instruction to clear the full vector
603 static int optimize
= 0;
606 1. Clear the REX_W bit with register operand if possible.
607 2. Above plus use 128bit vector instruction to clear the full vector
609 3. Above plus optimize "test{q,l,w} $imm8,%r{64,32,16}" to
612 static int optimize_for_space
= 0;
614 /* Register prefix used for error message. */
615 static const char *register_prefix
= "%";
617 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
618 leave, push, and pop instructions so that gcc has the same stack
619 frame as in 32 bit mode. */
620 static char stackop_size
= '\0';
622 /* Non-zero to optimize code alignment. */
623 int optimize_align_code
= 1;
625 /* Non-zero to quieten some warnings. */
626 static int quiet_warnings
= 0;
629 static const char *cpu_arch_name
= NULL
;
630 static char *cpu_sub_arch_name
= NULL
;
632 /* CPU feature flags. */
633 static i386_cpu_flags cpu_arch_flags
= CPU_UNKNOWN_FLAGS
;
635 /* If we have selected a cpu we are generating instructions for. */
636 static int cpu_arch_tune_set
= 0;
638 /* Cpu we are generating instructions for. */
639 enum processor_type cpu_arch_tune
= PROCESSOR_UNKNOWN
;
641 /* CPU feature flags of cpu we are generating instructions for. */
642 static i386_cpu_flags cpu_arch_tune_flags
;
644 /* CPU instruction set architecture used. */
645 enum processor_type cpu_arch_isa
= PROCESSOR_UNKNOWN
;
647 /* CPU feature flags of instruction set architecture used. */
648 i386_cpu_flags cpu_arch_isa_flags
;
650 /* If set, conditional jumps are not automatically promoted to handle
651 larger than a byte offset. */
652 static unsigned int no_cond_jump_promotion
= 0;
654 /* Encode SSE instructions with VEX prefix. */
655 static unsigned int sse2avx
;
657 /* Encode scalar AVX instructions with specific vector length. */
664 /* Encode scalar EVEX LIG instructions with specific vector length. */
672 /* Encode EVEX WIG instructions with specific evex.w. */
679 /* Value to encode in EVEX RC bits, for SAE-only instructions. */
680 static enum rc_type evexrcig
= rne
;
682 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
683 static symbolS
*GOT_symbol
;
685 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
686 unsigned int x86_dwarf2_return_column
;
688 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
689 int x86_cie_data_alignment
;
691 /* Interface to relax_segment.
692 There are 3 major relax states for 386 jump insns because the
693 different types of jumps add different sizes to frags when we're
694 figuring out what sort of jump to choose to reach a given label. */
697 #define UNCOND_JUMP 0
699 #define COND_JUMP86 2
704 #define SMALL16 (SMALL | CODE16)
706 #define BIG16 (BIG | CODE16)
710 #define INLINE __inline__
716 #define ENCODE_RELAX_STATE(type, size) \
717 ((relax_substateT) (((type) << 2) | (size)))
718 #define TYPE_FROM_RELAX_STATE(s) \
720 #define DISP_SIZE_FROM_RELAX_STATE(s) \
721 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
723 /* This table is used by relax_frag to promote short jumps to long
724 ones where necessary. SMALL (short) jumps may be promoted to BIG
725 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
726 don't allow a short jump in a 32 bit code segment to be promoted to
727 a 16 bit offset jump because it's slower (requires data size
728 prefix), and doesn't work, unless the destination is in the bottom
729 64k of the code segment (The top 16 bits of eip are zeroed). */
731 const relax_typeS md_relax_table
[] =
734 1) most positive reach of this state,
735 2) most negative reach of this state,
736 3) how many bytes this mode will have in the variable part of the frag
737 4) which index into the table to try if we can't fit into this one. */
739 /* UNCOND_JUMP states. */
740 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
741 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
742 /* dword jmp adds 4 bytes to frag:
743 0 extra opcode bytes, 4 displacement bytes. */
745 /* word jmp adds 2 byte2 to frag:
746 0 extra opcode bytes, 2 displacement bytes. */
749 /* COND_JUMP states. */
750 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
751 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
752 /* dword conditionals adds 5 bytes to frag:
753 1 extra opcode byte, 4 displacement bytes. */
755 /* word conditionals add 3 bytes to frag:
756 1 extra opcode byte, 2 displacement bytes. */
759 /* COND_JUMP86 states. */
760 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
761 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
762 /* dword conditionals adds 5 bytes to frag:
763 1 extra opcode byte, 4 displacement bytes. */
765 /* word conditionals add 4 bytes to frag:
766 1 displacement byte and a 3 byte long branch insn. */
770 static const arch_entry cpu_arch
[] =
772 /* Do not replace the first two entries - i386_target_format()
773 relies on them being there in this order. */
774 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32
,
775 CPU_GENERIC32_FLAGS
, 0 },
776 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64
,
777 CPU_GENERIC64_FLAGS
, 0 },
778 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN
,
780 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN
,
782 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN
,
784 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386
,
786 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486
,
788 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM
,
790 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO
,
792 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM
,
794 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO
,
795 CPU_PENTIUMPRO_FLAGS
, 0 },
796 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO
,
798 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO
,
800 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4
,
802 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA
,
804 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA
,
805 CPU_NOCONA_FLAGS
, 0 },
806 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE
,
808 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE
,
810 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2
,
811 CPU_CORE2_FLAGS
, 1 },
812 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2
,
813 CPU_CORE2_FLAGS
, 0 },
814 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7
,
815 CPU_COREI7_FLAGS
, 0 },
816 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM
,
818 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM
,
820 { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU
,
821 CPU_IAMCU_FLAGS
, 0 },
822 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6
,
824 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6
,
826 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON
,
827 CPU_ATHLON_FLAGS
, 0 },
828 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8
,
830 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8
,
832 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8
,
834 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10
,
835 CPU_AMDFAM10_FLAGS
, 0 },
836 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD
,
837 CPU_BDVER1_FLAGS
, 0 },
838 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD
,
839 CPU_BDVER2_FLAGS
, 0 },
840 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD
,
841 CPU_BDVER3_FLAGS
, 0 },
842 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD
,
843 CPU_BDVER4_FLAGS
, 0 },
844 { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER
,
845 CPU_ZNVER1_FLAGS
, 0 },
846 { STRING_COMMA_LEN ("znver2"), PROCESSOR_ZNVER
,
847 CPU_ZNVER2_FLAGS
, 0 },
848 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT
,
849 CPU_BTVER1_FLAGS
, 0 },
850 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT
,
851 CPU_BTVER2_FLAGS
, 0 },
852 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN
,
854 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN
,
856 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN
,
858 { STRING_COMMA_LEN (".687"), PROCESSOR_UNKNOWN
,
860 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN
,
862 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN
,
864 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN
,
866 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN
,
868 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN
,
869 CPU_SSSE3_FLAGS
, 0 },
870 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN
,
871 CPU_SSE4_1_FLAGS
, 0 },
872 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN
,
873 CPU_SSE4_2_FLAGS
, 0 },
874 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN
,
875 CPU_SSE4_2_FLAGS
, 0 },
876 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN
,
878 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN
,
880 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN
,
881 CPU_AVX512F_FLAGS
, 0 },
882 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN
,
883 CPU_AVX512CD_FLAGS
, 0 },
884 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN
,
885 CPU_AVX512ER_FLAGS
, 0 },
886 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN
,
887 CPU_AVX512PF_FLAGS
, 0 },
888 { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN
,
889 CPU_AVX512DQ_FLAGS
, 0 },
890 { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN
,
891 CPU_AVX512BW_FLAGS
, 0 },
892 { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN
,
893 CPU_AVX512VL_FLAGS
, 0 },
894 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN
,
896 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN
,
897 CPU_VMFUNC_FLAGS
, 0 },
898 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN
,
900 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN
,
901 CPU_XSAVE_FLAGS
, 0 },
902 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN
,
903 CPU_XSAVEOPT_FLAGS
, 0 },
904 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN
,
905 CPU_XSAVEC_FLAGS
, 0 },
906 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN
,
907 CPU_XSAVES_FLAGS
, 0 },
908 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN
,
910 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN
,
911 CPU_PCLMUL_FLAGS
, 0 },
912 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN
,
913 CPU_PCLMUL_FLAGS
, 1 },
914 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN
,
915 CPU_FSGSBASE_FLAGS
, 0 },
916 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN
,
917 CPU_RDRND_FLAGS
, 0 },
918 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN
,
920 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN
,
922 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN
,
924 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN
,
926 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN
,
928 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN
,
930 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN
,
931 CPU_MOVBE_FLAGS
, 0 },
932 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN
,
934 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN
,
936 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN
,
937 CPU_LZCNT_FLAGS
, 0 },
938 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN
,
940 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN
,
942 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN
,
943 CPU_INVPCID_FLAGS
, 0 },
944 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN
,
945 CPU_CLFLUSH_FLAGS
, 0 },
946 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN
,
948 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN
,
949 CPU_SYSCALL_FLAGS
, 0 },
950 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN
,
951 CPU_RDTSCP_FLAGS
, 0 },
952 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN
,
953 CPU_3DNOW_FLAGS
, 0 },
954 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN
,
955 CPU_3DNOWA_FLAGS
, 0 },
956 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN
,
957 CPU_PADLOCK_FLAGS
, 0 },
958 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN
,
960 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN
,
962 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN
,
963 CPU_SSE4A_FLAGS
, 0 },
964 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN
,
966 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN
,
968 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN
,
970 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN
,
972 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN
,
973 CPU_RDSEED_FLAGS
, 0 },
974 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN
,
975 CPU_PRFCHW_FLAGS
, 0 },
976 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN
,
978 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN
,
980 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN
,
982 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN
,
983 CPU_CLFLUSHOPT_FLAGS
, 0 },
984 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN
,
985 CPU_PREFETCHWT1_FLAGS
, 0 },
986 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN
,
988 { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN
,
990 { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN
,
991 CPU_AVX512IFMA_FLAGS
, 0 },
992 { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN
,
993 CPU_AVX512VBMI_FLAGS
, 0 },
994 { STRING_COMMA_LEN (".avx512_4fmaps"), PROCESSOR_UNKNOWN
,
995 CPU_AVX512_4FMAPS_FLAGS
, 0 },
996 { STRING_COMMA_LEN (".avx512_4vnniw"), PROCESSOR_UNKNOWN
,
997 CPU_AVX512_4VNNIW_FLAGS
, 0 },
998 { STRING_COMMA_LEN (".avx512_vpopcntdq"), PROCESSOR_UNKNOWN
,
999 CPU_AVX512_VPOPCNTDQ_FLAGS
, 0 },
1000 { STRING_COMMA_LEN (".avx512_vbmi2"), PROCESSOR_UNKNOWN
,
1001 CPU_AVX512_VBMI2_FLAGS
, 0 },
1002 { STRING_COMMA_LEN (".avx512_vnni"), PROCESSOR_UNKNOWN
,
1003 CPU_AVX512_VNNI_FLAGS
, 0 },
1004 { STRING_COMMA_LEN (".avx512_bitalg"), PROCESSOR_UNKNOWN
,
1005 CPU_AVX512_BITALG_FLAGS
, 0 },
1006 { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN
,
1007 CPU_CLZERO_FLAGS
, 0 },
1008 { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN
,
1009 CPU_MWAITX_FLAGS
, 0 },
1010 { STRING_COMMA_LEN (".ospke"), PROCESSOR_UNKNOWN
,
1011 CPU_OSPKE_FLAGS
, 0 },
1012 { STRING_COMMA_LEN (".rdpid"), PROCESSOR_UNKNOWN
,
1013 CPU_RDPID_FLAGS
, 0 },
1014 { STRING_COMMA_LEN (".ptwrite"), PROCESSOR_UNKNOWN
,
1015 CPU_PTWRITE_FLAGS
, 0 },
1016 { STRING_COMMA_LEN (".ibt"), PROCESSOR_UNKNOWN
,
1018 { STRING_COMMA_LEN (".shstk"), PROCESSOR_UNKNOWN
,
1019 CPU_SHSTK_FLAGS
, 0 },
1020 { STRING_COMMA_LEN (".gfni"), PROCESSOR_UNKNOWN
,
1021 CPU_GFNI_FLAGS
, 0 },
1022 { STRING_COMMA_LEN (".vaes"), PROCESSOR_UNKNOWN
,
1023 CPU_VAES_FLAGS
, 0 },
1024 { STRING_COMMA_LEN (".vpclmulqdq"), PROCESSOR_UNKNOWN
,
1025 CPU_VPCLMULQDQ_FLAGS
, 0 },
1026 { STRING_COMMA_LEN (".wbnoinvd"), PROCESSOR_UNKNOWN
,
1027 CPU_WBNOINVD_FLAGS
, 0 },
1028 { STRING_COMMA_LEN (".pconfig"), PROCESSOR_UNKNOWN
,
1029 CPU_PCONFIG_FLAGS
, 0 },
1030 { STRING_COMMA_LEN (".waitpkg"), PROCESSOR_UNKNOWN
,
1031 CPU_WAITPKG_FLAGS
, 0 },
1032 { STRING_COMMA_LEN (".cldemote"), PROCESSOR_UNKNOWN
,
1033 CPU_CLDEMOTE_FLAGS
, 0 },
1034 { STRING_COMMA_LEN (".movdiri"), PROCESSOR_UNKNOWN
,
1035 CPU_MOVDIRI_FLAGS
, 0 },
1036 { STRING_COMMA_LEN (".movdir64b"), PROCESSOR_UNKNOWN
,
1037 CPU_MOVDIR64B_FLAGS
, 0 },
1040 static const noarch_entry cpu_noarch
[] =
1042 { STRING_COMMA_LEN ("no87"), CPU_ANY_X87_FLAGS
},
1043 { STRING_COMMA_LEN ("no287"), CPU_ANY_287_FLAGS
},
1044 { STRING_COMMA_LEN ("no387"), CPU_ANY_387_FLAGS
},
1045 { STRING_COMMA_LEN ("no687"), CPU_ANY_687_FLAGS
},
1046 { STRING_COMMA_LEN ("nommx"), CPU_ANY_MMX_FLAGS
},
1047 { STRING_COMMA_LEN ("nosse"), CPU_ANY_SSE_FLAGS
},
1048 { STRING_COMMA_LEN ("nosse2"), CPU_ANY_SSE2_FLAGS
},
1049 { STRING_COMMA_LEN ("nosse3"), CPU_ANY_SSE3_FLAGS
},
1050 { STRING_COMMA_LEN ("nossse3"), CPU_ANY_SSSE3_FLAGS
},
1051 { STRING_COMMA_LEN ("nosse4.1"), CPU_ANY_SSE4_1_FLAGS
},
1052 { STRING_COMMA_LEN ("nosse4.2"), CPU_ANY_SSE4_2_FLAGS
},
1053 { STRING_COMMA_LEN ("nosse4"), CPU_ANY_SSE4_1_FLAGS
},
1054 { STRING_COMMA_LEN ("noavx"), CPU_ANY_AVX_FLAGS
},
1055 { STRING_COMMA_LEN ("noavx2"), CPU_ANY_AVX2_FLAGS
},
1056 { STRING_COMMA_LEN ("noavx512f"), CPU_ANY_AVX512F_FLAGS
},
1057 { STRING_COMMA_LEN ("noavx512cd"), CPU_ANY_AVX512CD_FLAGS
},
1058 { STRING_COMMA_LEN ("noavx512er"), CPU_ANY_AVX512ER_FLAGS
},
1059 { STRING_COMMA_LEN ("noavx512pf"), CPU_ANY_AVX512PF_FLAGS
},
1060 { STRING_COMMA_LEN ("noavx512dq"), CPU_ANY_AVX512DQ_FLAGS
},
1061 { STRING_COMMA_LEN ("noavx512bw"), CPU_ANY_AVX512BW_FLAGS
},
1062 { STRING_COMMA_LEN ("noavx512vl"), CPU_ANY_AVX512VL_FLAGS
},
1063 { STRING_COMMA_LEN ("noavx512ifma"), CPU_ANY_AVX512IFMA_FLAGS
},
1064 { STRING_COMMA_LEN ("noavx512vbmi"), CPU_ANY_AVX512VBMI_FLAGS
},
1065 { STRING_COMMA_LEN ("noavx512_4fmaps"), CPU_ANY_AVX512_4FMAPS_FLAGS
},
1066 { STRING_COMMA_LEN ("noavx512_4vnniw"), CPU_ANY_AVX512_4VNNIW_FLAGS
},
1067 { STRING_COMMA_LEN ("noavx512_vpopcntdq"), CPU_ANY_AVX512_VPOPCNTDQ_FLAGS
},
1068 { STRING_COMMA_LEN ("noavx512_vbmi2"), CPU_ANY_AVX512_VBMI2_FLAGS
},
1069 { STRING_COMMA_LEN ("noavx512_vnni"), CPU_ANY_AVX512_VNNI_FLAGS
},
1070 { STRING_COMMA_LEN ("noavx512_bitalg"), CPU_ANY_AVX512_BITALG_FLAGS
},
1071 { STRING_COMMA_LEN ("noibt"), CPU_ANY_IBT_FLAGS
},
1072 { STRING_COMMA_LEN ("noshstk"), CPU_ANY_SHSTK_FLAGS
},
1073 { STRING_COMMA_LEN ("nomovdiri"), CPU_ANY_MOVDIRI_FLAGS
},
1074 { STRING_COMMA_LEN ("nomovdir64b"), CPU_ANY_MOVDIR64B_FLAGS
},
1078 /* Like s_lcomm_internal in gas/read.c but the alignment string
1079 is allowed to be optional. */
1082 pe_lcomm_internal (int needs_align
, symbolS
*symbolP
, addressT size
)
1089 && *input_line_pointer
== ',')
1091 align
= parse_align (needs_align
- 1);
1093 if (align
== (addressT
) -1)
1108 bss_alloc (symbolP
, size
, align
);
1113 pe_lcomm (int needs_align
)
1115 s_comm_internal (needs_align
* 2, pe_lcomm_internal
);
1119 const pseudo_typeS md_pseudo_table
[] =
1121 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
1122 {"align", s_align_bytes
, 0},
1124 {"align", s_align_ptwo
, 0},
1126 {"arch", set_cpu_arch
, 0},
1130 {"lcomm", pe_lcomm
, 1},
1132 {"ffloat", float_cons
, 'f'},
1133 {"dfloat", float_cons
, 'd'},
1134 {"tfloat", float_cons
, 'x'},
1136 {"slong", signed_cons
, 4},
1137 {"noopt", s_ignore
, 0},
1138 {"optim", s_ignore
, 0},
1139 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
1140 {"code16", set_code_flag
, CODE_16BIT
},
1141 {"code32", set_code_flag
, CODE_32BIT
},
1143 {"code64", set_code_flag
, CODE_64BIT
},
1145 {"intel_syntax", set_intel_syntax
, 1},
1146 {"att_syntax", set_intel_syntax
, 0},
1147 {"intel_mnemonic", set_intel_mnemonic
, 1},
1148 {"att_mnemonic", set_intel_mnemonic
, 0},
1149 {"allow_index_reg", set_allow_index_reg
, 1},
1150 {"disallow_index_reg", set_allow_index_reg
, 0},
1151 {"sse_check", set_check
, 0},
1152 {"operand_check", set_check
, 1},
1153 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1154 {"largecomm", handle_large_common
, 0},
1156 {"file", dwarf2_directive_file
, 0},
1157 {"loc", dwarf2_directive_loc
, 0},
1158 {"loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0},
1161 {"secrel32", pe_directive_secrel
, 0},
1166 /* For interface with expression (). */
1167 extern char *input_line_pointer
;
1169 /* Hash table for instruction mnemonic lookup. */
1170 static struct hash_control
*op_hash
;
1172 /* Hash table for register lookup. */
1173 static struct hash_control
*reg_hash
;
1175 /* Various efficient no-op patterns for aligning code labels.
1176 Note: Don't try to assemble the instructions in the comments.
1177 0L and 0w are not legal. */
1178 static const unsigned char f32_1
[] =
1180 static const unsigned char f32_2
[] =
1181 {0x66,0x90}; /* xchg %ax,%ax */
1182 static const unsigned char f32_3
[] =
1183 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1184 static const unsigned char f32_4
[] =
1185 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1186 static const unsigned char f32_6
[] =
1187 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1188 static const unsigned char f32_7
[] =
1189 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1190 static const unsigned char f16_3
[] =
1191 {0x8d,0x74,0x00}; /* lea 0(%si),%si */
1192 static const unsigned char f16_4
[] =
1193 {0x8d,0xb4,0x00,0x00}; /* lea 0W(%si),%si */
1194 static const unsigned char jump_disp8
[] =
1195 {0xeb}; /* jmp disp8 */
1196 static const unsigned char jump32_disp32
[] =
1197 {0xe9}; /* jmp disp32 */
1198 static const unsigned char jump16_disp32
[] =
1199 {0x66,0xe9}; /* jmp disp32 */
1200 /* 32-bit NOPs patterns. */
1201 static const unsigned char *const f32_patt
[] = {
1202 f32_1
, f32_2
, f32_3
, f32_4
, NULL
, f32_6
, f32_7
1204 /* 16-bit NOPs patterns. */
1205 static const unsigned char *const f16_patt
[] = {
1206 f32_1
, f32_2
, f16_3
, f16_4
1208 /* nopl (%[re]ax) */
1209 static const unsigned char alt_3
[] =
1211 /* nopl 0(%[re]ax) */
1212 static const unsigned char alt_4
[] =
1213 {0x0f,0x1f,0x40,0x00};
1214 /* nopl 0(%[re]ax,%[re]ax,1) */
1215 static const unsigned char alt_5
[] =
1216 {0x0f,0x1f,0x44,0x00,0x00};
1217 /* nopw 0(%[re]ax,%[re]ax,1) */
1218 static const unsigned char alt_6
[] =
1219 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1220 /* nopl 0L(%[re]ax) */
1221 static const unsigned char alt_7
[] =
1222 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1223 /* nopl 0L(%[re]ax,%[re]ax,1) */
1224 static const unsigned char alt_8
[] =
1225 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1226 /* nopw 0L(%[re]ax,%[re]ax,1) */
1227 static const unsigned char alt_9
[] =
1228 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1229 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1230 static const unsigned char alt_10
[] =
1231 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1232 /* data16 nopw %cs:0L(%eax,%eax,1) */
1233 static const unsigned char alt_11
[] =
1234 {0x66,0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1235 /* 32-bit and 64-bit NOPs patterns. */
1236 static const unsigned char *const alt_patt
[] = {
1237 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
1238 alt_9
, alt_10
, alt_11
1241 /* Genenerate COUNT bytes of NOPs to WHERE from PATT with the maximum
1242 size of a single NOP instruction MAX_SINGLE_NOP_SIZE. */
1245 i386_output_nops (char *where
, const unsigned char *const *patt
,
1246 int count
, int max_single_nop_size
)
1249 /* Place the longer NOP first. */
1252 const unsigned char *nops
= patt
[max_single_nop_size
- 1];
1254 /* Use the smaller one if the requsted one isn't available. */
1257 max_single_nop_size
--;
1258 nops
= patt
[max_single_nop_size
- 1];
1261 last
= count
% max_single_nop_size
;
1264 for (offset
= 0; offset
< count
; offset
+= max_single_nop_size
)
1265 memcpy (where
+ offset
, nops
, max_single_nop_size
);
1269 nops
= patt
[last
- 1];
1272 /* Use the smaller one plus one-byte NOP if the needed one
1275 nops
= patt
[last
- 1];
1276 memcpy (where
+ offset
, nops
, last
);
1277 where
[offset
+ last
] = *patt
[0];
1280 memcpy (where
+ offset
, nops
, last
);
1285 fits_in_imm7 (offsetT num
)
1287 return (num
& 0x7f) == num
;
1291 fits_in_imm31 (offsetT num
)
1293 return (num
& 0x7fffffff) == num
;
1296 /* Genenerate COUNT bytes of NOPs to WHERE with the maximum size of a
1297 single NOP instruction LIMIT. */
1300 i386_generate_nops (fragS
*fragP
, char *where
, offsetT count
, int limit
)
1302 const unsigned char *const *patt
= NULL
;
1303 int max_single_nop_size
;
1304 /* Maximum number of NOPs before switching to jump over NOPs. */
1305 int max_number_of_nops
;
1307 switch (fragP
->fr_type
)
1316 /* We need to decide which NOP sequence to use for 32bit and
1317 64bit. When -mtune= is used:
1319 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1320 PROCESSOR_GENERIC32, f32_patt will be used.
1321 2. For the rest, alt_patt will be used.
1323 When -mtune= isn't used, alt_patt will be used if
1324 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
1327 When -march= or .arch is used, we can't use anything beyond
1328 cpu_arch_isa_flags. */
1330 if (flag_code
== CODE_16BIT
)
1333 max_single_nop_size
= sizeof (f16_patt
) / sizeof (f16_patt
[0]);
1334 /* Limit number of NOPs to 2 in 16-bit mode. */
1335 max_number_of_nops
= 2;
1339 if (fragP
->tc_frag_data
.isa
== PROCESSOR_UNKNOWN
)
1341 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1342 switch (cpu_arch_tune
)
1344 case PROCESSOR_UNKNOWN
:
1345 /* We use cpu_arch_isa_flags to check if we SHOULD
1346 optimize with nops. */
1347 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1352 case PROCESSOR_PENTIUM4
:
1353 case PROCESSOR_NOCONA
:
1354 case PROCESSOR_CORE
:
1355 case PROCESSOR_CORE2
:
1356 case PROCESSOR_COREI7
:
1357 case PROCESSOR_L1OM
:
1358 case PROCESSOR_K1OM
:
1359 case PROCESSOR_GENERIC64
:
1361 case PROCESSOR_ATHLON
:
1363 case PROCESSOR_AMDFAM10
:
1365 case PROCESSOR_ZNVER
:
1369 case PROCESSOR_I386
:
1370 case PROCESSOR_I486
:
1371 case PROCESSOR_PENTIUM
:
1372 case PROCESSOR_PENTIUMPRO
:
1373 case PROCESSOR_IAMCU
:
1374 case PROCESSOR_GENERIC32
:
1381 switch (fragP
->tc_frag_data
.tune
)
1383 case PROCESSOR_UNKNOWN
:
1384 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1385 PROCESSOR_UNKNOWN. */
1389 case PROCESSOR_I386
:
1390 case PROCESSOR_I486
:
1391 case PROCESSOR_PENTIUM
:
1392 case PROCESSOR_IAMCU
:
1394 case PROCESSOR_ATHLON
:
1396 case PROCESSOR_AMDFAM10
:
1398 case PROCESSOR_ZNVER
:
1400 case PROCESSOR_GENERIC32
:
1401 /* We use cpu_arch_isa_flags to check if we CAN optimize
1403 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1408 case PROCESSOR_PENTIUMPRO
:
1409 case PROCESSOR_PENTIUM4
:
1410 case PROCESSOR_NOCONA
:
1411 case PROCESSOR_CORE
:
1412 case PROCESSOR_CORE2
:
1413 case PROCESSOR_COREI7
:
1414 case PROCESSOR_L1OM
:
1415 case PROCESSOR_K1OM
:
1416 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1421 case PROCESSOR_GENERIC64
:
1427 if (patt
== f32_patt
)
1429 max_single_nop_size
= sizeof (f32_patt
) / sizeof (f32_patt
[0]);
1430 /* Limit number of NOPs to 2 for older processors. */
1431 max_number_of_nops
= 2;
1435 max_single_nop_size
= sizeof (alt_patt
) / sizeof (alt_patt
[0]);
1436 /* Limit number of NOPs to 7 for newer processors. */
1437 max_number_of_nops
= 7;
1442 limit
= max_single_nop_size
;
1444 if (fragP
->fr_type
== rs_fill_nop
)
1446 /* Output NOPs for .nop directive. */
1447 if (limit
> max_single_nop_size
)
1449 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
1450 _("invalid single nop size: %d "
1451 "(expect within [0, %d])"),
1452 limit
, max_single_nop_size
);
1457 fragP
->fr_var
= count
;
1459 if ((count
/ max_single_nop_size
) > max_number_of_nops
)
1461 /* Generate jump over NOPs. */
1462 offsetT disp
= count
- 2;
1463 if (fits_in_imm7 (disp
))
1465 /* Use "jmp disp8" if possible. */
1467 where
[0] = jump_disp8
[0];
1473 unsigned int size_of_jump
;
1475 if (flag_code
== CODE_16BIT
)
1477 where
[0] = jump16_disp32
[0];
1478 where
[1] = jump16_disp32
[1];
1483 where
[0] = jump32_disp32
[0];
1487 count
-= size_of_jump
+ 4;
1488 if (!fits_in_imm31 (count
))
1490 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
1491 _("jump over nop padding out of range"));
1495 md_number_to_chars (where
+ size_of_jump
, count
, 4);
1496 where
+= size_of_jump
+ 4;
1500 /* Generate multiple NOPs. */
1501 i386_output_nops (where
, patt
, count
, limit
);
1505 operand_type_all_zero (const union i386_operand_type
*x
)
1507 switch (ARRAY_SIZE(x
->array
))
1518 return !x
->array
[0];
1525 operand_type_set (union i386_operand_type
*x
, unsigned int v
)
1527 switch (ARRAY_SIZE(x
->array
))
1545 operand_type_equal (const union i386_operand_type
*x
,
1546 const union i386_operand_type
*y
)
1548 switch (ARRAY_SIZE(x
->array
))
1551 if (x
->array
[2] != y
->array
[2])
1555 if (x
->array
[1] != y
->array
[1])
1559 return x
->array
[0] == y
->array
[0];
1567 cpu_flags_all_zero (const union i386_cpu_flags
*x
)
1569 switch (ARRAY_SIZE(x
->array
))
1584 return !x
->array
[0];
1591 cpu_flags_equal (const union i386_cpu_flags
*x
,
1592 const union i386_cpu_flags
*y
)
1594 switch (ARRAY_SIZE(x
->array
))
1597 if (x
->array
[3] != y
->array
[3])
1601 if (x
->array
[2] != y
->array
[2])
1605 if (x
->array
[1] != y
->array
[1])
1609 return x
->array
[0] == y
->array
[0];
1617 cpu_flags_check_cpu64 (i386_cpu_flags f
)
1619 return !((flag_code
== CODE_64BIT
&& f
.bitfield
.cpuno64
)
1620 || (flag_code
!= CODE_64BIT
&& f
.bitfield
.cpu64
));
1623 static INLINE i386_cpu_flags
1624 cpu_flags_and (i386_cpu_flags x
, i386_cpu_flags y
)
1626 switch (ARRAY_SIZE (x
.array
))
1629 x
.array
[3] &= y
.array
[3];
1632 x
.array
[2] &= y
.array
[2];
1635 x
.array
[1] &= y
.array
[1];
1638 x
.array
[0] &= y
.array
[0];
1646 static INLINE i386_cpu_flags
1647 cpu_flags_or (i386_cpu_flags x
, i386_cpu_flags y
)
1649 switch (ARRAY_SIZE (x
.array
))
1652 x
.array
[3] |= y
.array
[3];
1655 x
.array
[2] |= y
.array
[2];
1658 x
.array
[1] |= y
.array
[1];
1661 x
.array
[0] |= y
.array
[0];
1669 static INLINE i386_cpu_flags
1670 cpu_flags_and_not (i386_cpu_flags x
, i386_cpu_flags y
)
1672 switch (ARRAY_SIZE (x
.array
))
1675 x
.array
[3] &= ~y
.array
[3];
1678 x
.array
[2] &= ~y
.array
[2];
1681 x
.array
[1] &= ~y
.array
[1];
1684 x
.array
[0] &= ~y
.array
[0];
1692 #define CPU_FLAGS_ARCH_MATCH 0x1
1693 #define CPU_FLAGS_64BIT_MATCH 0x2
1695 #define CPU_FLAGS_PERFECT_MATCH \
1696 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_64BIT_MATCH)
1698 /* Return CPU flags match bits. */
1701 cpu_flags_match (const insn_template
*t
)
1703 i386_cpu_flags x
= t
->cpu_flags
;
1704 int match
= cpu_flags_check_cpu64 (x
) ? CPU_FLAGS_64BIT_MATCH
: 0;
1706 x
.bitfield
.cpu64
= 0;
1707 x
.bitfield
.cpuno64
= 0;
1709 if (cpu_flags_all_zero (&x
))
1711 /* This instruction is available on all archs. */
1712 match
|= CPU_FLAGS_ARCH_MATCH
;
1716 /* This instruction is available only on some archs. */
1717 i386_cpu_flags cpu
= cpu_arch_flags
;
1719 /* AVX512VL is no standalone feature - match it and then strip it. */
1720 if (x
.bitfield
.cpuavx512vl
&& !cpu
.bitfield
.cpuavx512vl
)
1722 x
.bitfield
.cpuavx512vl
= 0;
1724 cpu
= cpu_flags_and (x
, cpu
);
1725 if (!cpu_flags_all_zero (&cpu
))
1727 if (x
.bitfield
.cpuavx
)
1729 /* We need to check a few extra flags with AVX. */
1730 if (cpu
.bitfield
.cpuavx
1731 && (!t
->opcode_modifier
.sse2avx
|| sse2avx
)
1732 && (!x
.bitfield
.cpuaes
|| cpu
.bitfield
.cpuaes
)
1733 && (!x
.bitfield
.cpugfni
|| cpu
.bitfield
.cpugfni
)
1734 && (!x
.bitfield
.cpupclmul
|| cpu
.bitfield
.cpupclmul
))
1735 match
|= CPU_FLAGS_ARCH_MATCH
;
1737 else if (x
.bitfield
.cpuavx512f
)
1739 /* We need to check a few extra flags with AVX512F. */
1740 if (cpu
.bitfield
.cpuavx512f
1741 && (!x
.bitfield
.cpugfni
|| cpu
.bitfield
.cpugfni
)
1742 && (!x
.bitfield
.cpuvaes
|| cpu
.bitfield
.cpuvaes
)
1743 && (!x
.bitfield
.cpuvpclmulqdq
|| cpu
.bitfield
.cpuvpclmulqdq
))
1744 match
|= CPU_FLAGS_ARCH_MATCH
;
1747 match
|= CPU_FLAGS_ARCH_MATCH
;
1753 static INLINE i386_operand_type
1754 operand_type_and (i386_operand_type x
, i386_operand_type y
)
1756 switch (ARRAY_SIZE (x
.array
))
1759 x
.array
[2] &= y
.array
[2];
1762 x
.array
[1] &= y
.array
[1];
1765 x
.array
[0] &= y
.array
[0];
1773 static INLINE i386_operand_type
1774 operand_type_and_not (i386_operand_type x
, i386_operand_type y
)
1776 switch (ARRAY_SIZE (x
.array
))
1779 x
.array
[2] &= ~y
.array
[2];
1782 x
.array
[1] &= ~y
.array
[1];
1785 x
.array
[0] &= ~y
.array
[0];
1793 static INLINE i386_operand_type
1794 operand_type_or (i386_operand_type x
, i386_operand_type y
)
1796 switch (ARRAY_SIZE (x
.array
))
1799 x
.array
[2] |= y
.array
[2];
1802 x
.array
[1] |= y
.array
[1];
1805 x
.array
[0] |= y
.array
[0];
1813 static INLINE i386_operand_type
1814 operand_type_xor (i386_operand_type x
, i386_operand_type y
)
1816 switch (ARRAY_SIZE (x
.array
))
1819 x
.array
[2] ^= y
.array
[2];
1822 x
.array
[1] ^= y
.array
[1];
1825 x
.array
[0] ^= y
.array
[0];
1833 static const i386_operand_type acc32
= OPERAND_TYPE_ACC32
;
1834 static const i386_operand_type acc64
= OPERAND_TYPE_ACC64
;
1835 static const i386_operand_type disp16
= OPERAND_TYPE_DISP16
;
1836 static const i386_operand_type disp32
= OPERAND_TYPE_DISP32
;
1837 static const i386_operand_type disp32s
= OPERAND_TYPE_DISP32S
;
1838 static const i386_operand_type disp16_32
= OPERAND_TYPE_DISP16_32
;
1839 static const i386_operand_type anydisp
1840 = OPERAND_TYPE_ANYDISP
;
1841 static const i386_operand_type regxmm
= OPERAND_TYPE_REGXMM
;
1842 static const i386_operand_type regmask
= OPERAND_TYPE_REGMASK
;
1843 static const i386_operand_type imm8
= OPERAND_TYPE_IMM8
;
1844 static const i386_operand_type imm8s
= OPERAND_TYPE_IMM8S
;
1845 static const i386_operand_type imm16
= OPERAND_TYPE_IMM16
;
1846 static const i386_operand_type imm32
= OPERAND_TYPE_IMM32
;
1847 static const i386_operand_type imm32s
= OPERAND_TYPE_IMM32S
;
1848 static const i386_operand_type imm64
= OPERAND_TYPE_IMM64
;
1849 static const i386_operand_type imm16_32
= OPERAND_TYPE_IMM16_32
;
1850 static const i386_operand_type imm16_32s
= OPERAND_TYPE_IMM16_32S
;
1851 static const i386_operand_type imm16_32_32s
= OPERAND_TYPE_IMM16_32_32S
;
1852 static const i386_operand_type vec_imm4
= OPERAND_TYPE_VEC_IMM4
;
1863 operand_type_check (i386_operand_type t
, enum operand_type c
)
1868 return t
.bitfield
.reg
;
1871 return (t
.bitfield
.imm8
1875 || t
.bitfield
.imm32s
1876 || t
.bitfield
.imm64
);
1879 return (t
.bitfield
.disp8
1880 || t
.bitfield
.disp16
1881 || t
.bitfield
.disp32
1882 || t
.bitfield
.disp32s
1883 || t
.bitfield
.disp64
);
1886 return (t
.bitfield
.disp8
1887 || t
.bitfield
.disp16
1888 || t
.bitfield
.disp32
1889 || t
.bitfield
.disp32s
1890 || t
.bitfield
.disp64
1891 || t
.bitfield
.baseindex
);
1900 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit/80bit on
1901 operand J for instruction template T. */
1904 match_reg_size (const insn_template
*t
, unsigned int wanted
, unsigned int given
)
1906 return !((i
.types
[given
].bitfield
.byte
1907 && !t
->operand_types
[wanted
].bitfield
.byte
)
1908 || (i
.types
[given
].bitfield
.word
1909 && !t
->operand_types
[wanted
].bitfield
.word
)
1910 || (i
.types
[given
].bitfield
.dword
1911 && !t
->operand_types
[wanted
].bitfield
.dword
)
1912 || (i
.types
[given
].bitfield
.qword
1913 && !t
->operand_types
[wanted
].bitfield
.qword
)
1914 || (i
.types
[given
].bitfield
.tbyte
1915 && !t
->operand_types
[wanted
].bitfield
.tbyte
));
1918 /* Return 1 if there is no conflict in SIMD register on
1919 operand J for instruction template T. */
1922 match_simd_size (const insn_template
*t
, unsigned int wanted
, unsigned int given
)
1924 return !((i
.types
[given
].bitfield
.xmmword
1925 && !t
->operand_types
[wanted
].bitfield
.xmmword
)
1926 || (i
.types
[given
].bitfield
.ymmword
1927 && !t
->operand_types
[wanted
].bitfield
.ymmword
)
1928 || (i
.types
[given
].bitfield
.zmmword
1929 && !t
->operand_types
[wanted
].bitfield
.zmmword
));
1932 /* Return 1 if there is no conflict in any size on operand J for
1933 instruction template T. */
1936 match_mem_size (const insn_template
*t
, unsigned int wanted
, unsigned int given
)
1938 return (match_reg_size (t
, wanted
, given
)
1939 && !((i
.types
[given
].bitfield
.unspecified
1941 && !t
->operand_types
[wanted
].bitfield
.unspecified
)
1942 || (i
.types
[given
].bitfield
.fword
1943 && !t
->operand_types
[wanted
].bitfield
.fword
)
1944 /* For scalar opcode templates to allow register and memory
1945 operands at the same time, some special casing is needed
1946 here. Also for v{,p}broadcast*, {,v}pmov{s,z}*, and
1947 down-conversion vpmov*. */
1948 || ((t
->operand_types
[wanted
].bitfield
.regsimd
1949 && !t
->opcode_modifier
.broadcast
1950 && (t
->operand_types
[wanted
].bitfield
.byte
1951 || t
->operand_types
[wanted
].bitfield
.word
1952 || t
->operand_types
[wanted
].bitfield
.dword
1953 || t
->operand_types
[wanted
].bitfield
.qword
))
1954 ? (i
.types
[given
].bitfield
.xmmword
1955 || i
.types
[given
].bitfield
.ymmword
1956 || i
.types
[given
].bitfield
.zmmword
)
1957 : !match_simd_size(t
, wanted
, given
))));
1960 /* Return value has MATCH_STRAIGHT set if there is no size conflict on any
1961 operands for instruction template T, and it has MATCH_REVERSE set if there
1962 is no size conflict on any operands for the template with operands reversed
1963 (and the template allows for reversing in the first place). */
1965 #define MATCH_STRAIGHT 1
1966 #define MATCH_REVERSE 2
1968 static INLINE
unsigned int
1969 operand_size_match (const insn_template
*t
)
1971 unsigned int j
, match
= MATCH_STRAIGHT
;
1973 /* Don't check jump instructions. */
1974 if (t
->opcode_modifier
.jump
1975 || t
->opcode_modifier
.jumpbyte
1976 || t
->opcode_modifier
.jumpdword
1977 || t
->opcode_modifier
.jumpintersegment
)
1980 /* Check memory and accumulator operand size. */
1981 for (j
= 0; j
< i
.operands
; j
++)
1983 if (!i
.types
[j
].bitfield
.reg
&& !i
.types
[j
].bitfield
.regsimd
1984 && t
->operand_types
[j
].bitfield
.anysize
)
1987 if (t
->operand_types
[j
].bitfield
.reg
1988 && !match_reg_size (t
, j
, j
))
1994 if (t
->operand_types
[j
].bitfield
.regsimd
1995 && !match_simd_size (t
, j
, j
))
2001 if (t
->operand_types
[j
].bitfield
.acc
2002 && (!match_reg_size (t
, j
, j
) || !match_simd_size (t
, j
, j
)))
2008 if (i
.types
[j
].bitfield
.mem
&& !match_mem_size (t
, j
, j
))
2015 if (!t
->opcode_modifier
.d
)
2019 i
.error
= operand_size_mismatch
;
2023 /* Check reverse. */
2024 gas_assert (i
.operands
== 2);
2026 for (j
= 0; j
< 2; j
++)
2028 if ((t
->operand_types
[j
].bitfield
.reg
2029 || t
->operand_types
[j
].bitfield
.acc
)
2030 && !match_reg_size (t
, j
, !j
))
2033 if (i
.types
[!j
].bitfield
.mem
2034 && !match_mem_size (t
, j
, !j
))
2038 return match
| MATCH_REVERSE
;
2042 operand_type_match (i386_operand_type overlap
,
2043 i386_operand_type given
)
2045 i386_operand_type temp
= overlap
;
2047 temp
.bitfield
.jumpabsolute
= 0;
2048 temp
.bitfield
.unspecified
= 0;
2049 temp
.bitfield
.byte
= 0;
2050 temp
.bitfield
.word
= 0;
2051 temp
.bitfield
.dword
= 0;
2052 temp
.bitfield
.fword
= 0;
2053 temp
.bitfield
.qword
= 0;
2054 temp
.bitfield
.tbyte
= 0;
2055 temp
.bitfield
.xmmword
= 0;
2056 temp
.bitfield
.ymmword
= 0;
2057 temp
.bitfield
.zmmword
= 0;
2058 if (operand_type_all_zero (&temp
))
2061 if (given
.bitfield
.baseindex
== overlap
.bitfield
.baseindex
2062 && given
.bitfield
.jumpabsolute
== overlap
.bitfield
.jumpabsolute
)
2066 i
.error
= operand_type_mismatch
;
2070 /* If given types g0 and g1 are registers they must be of the same type
2071 unless the expected operand type register overlap is null.
2072 Memory operand size of certain SIMD instructions is also being checked
2076 operand_type_register_match (i386_operand_type g0
,
2077 i386_operand_type t0
,
2078 i386_operand_type g1
,
2079 i386_operand_type t1
)
2081 if (!g0
.bitfield
.reg
2082 && !g0
.bitfield
.regsimd
2083 && (!operand_type_check (g0
, anymem
)
2084 || g0
.bitfield
.unspecified
2085 || !t0
.bitfield
.regsimd
))
2088 if (!g1
.bitfield
.reg
2089 && !g1
.bitfield
.regsimd
2090 && (!operand_type_check (g1
, anymem
)
2091 || g1
.bitfield
.unspecified
2092 || !t1
.bitfield
.regsimd
))
2095 if (g0
.bitfield
.byte
== g1
.bitfield
.byte
2096 && g0
.bitfield
.word
== g1
.bitfield
.word
2097 && g0
.bitfield
.dword
== g1
.bitfield
.dword
2098 && g0
.bitfield
.qword
== g1
.bitfield
.qword
2099 && g0
.bitfield
.xmmword
== g1
.bitfield
.xmmword
2100 && g0
.bitfield
.ymmword
== g1
.bitfield
.ymmword
2101 && g0
.bitfield
.zmmword
== g1
.bitfield
.zmmword
)
2104 if (!(t0
.bitfield
.byte
& t1
.bitfield
.byte
)
2105 && !(t0
.bitfield
.word
& t1
.bitfield
.word
)
2106 && !(t0
.bitfield
.dword
& t1
.bitfield
.dword
)
2107 && !(t0
.bitfield
.qword
& t1
.bitfield
.qword
)
2108 && !(t0
.bitfield
.xmmword
& t1
.bitfield
.xmmword
)
2109 && !(t0
.bitfield
.ymmword
& t1
.bitfield
.ymmword
)
2110 && !(t0
.bitfield
.zmmword
& t1
.bitfield
.zmmword
))
2113 i
.error
= register_type_mismatch
;
2118 static INLINE
unsigned int
2119 register_number (const reg_entry
*r
)
2121 unsigned int nr
= r
->reg_num
;
2123 if (r
->reg_flags
& RegRex
)
2126 if (r
->reg_flags
& RegVRex
)
2132 static INLINE
unsigned int
2133 mode_from_disp_size (i386_operand_type t
)
2135 if (t
.bitfield
.disp8
)
2137 else if (t
.bitfield
.disp16
2138 || t
.bitfield
.disp32
2139 || t
.bitfield
.disp32s
)
2146 fits_in_signed_byte (addressT num
)
2148 return num
+ 0x80 <= 0xff;
2152 fits_in_unsigned_byte (addressT num
)
2158 fits_in_unsigned_word (addressT num
)
2160 return num
<= 0xffff;
2164 fits_in_signed_word (addressT num
)
2166 return num
+ 0x8000 <= 0xffff;
2170 fits_in_signed_long (addressT num ATTRIBUTE_UNUSED
)
2175 return num
+ 0x80000000 <= 0xffffffff;
2177 } /* fits_in_signed_long() */
2180 fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED
)
2185 return num
<= 0xffffffff;
2187 } /* fits_in_unsigned_long() */
2190 fits_in_disp8 (offsetT num
)
2192 int shift
= i
.memshift
;
2198 mask
= (1 << shift
) - 1;
2200 /* Return 0 if NUM isn't properly aligned. */
2204 /* Check if NUM will fit in 8bit after shift. */
2205 return fits_in_signed_byte (num
>> shift
);
2209 fits_in_imm4 (offsetT num
)
2211 return (num
& 0xf) == num
;
2214 static i386_operand_type
2215 smallest_imm_type (offsetT num
)
2217 i386_operand_type t
;
2219 operand_type_set (&t
, 0);
2220 t
.bitfield
.imm64
= 1;
2222 if (cpu_arch_tune
!= PROCESSOR_I486
&& num
== 1)
2224 /* This code is disabled on the 486 because all the Imm1 forms
2225 in the opcode table are slower on the i486. They're the
2226 versions with the implicitly specified single-position
2227 displacement, which has another syntax if you really want to
2229 t
.bitfield
.imm1
= 1;
2230 t
.bitfield
.imm8
= 1;
2231 t
.bitfield
.imm8s
= 1;
2232 t
.bitfield
.imm16
= 1;
2233 t
.bitfield
.imm32
= 1;
2234 t
.bitfield
.imm32s
= 1;
2236 else if (fits_in_signed_byte (num
))
2238 t
.bitfield
.imm8
= 1;
2239 t
.bitfield
.imm8s
= 1;
2240 t
.bitfield
.imm16
= 1;
2241 t
.bitfield
.imm32
= 1;
2242 t
.bitfield
.imm32s
= 1;
2244 else if (fits_in_unsigned_byte (num
))
2246 t
.bitfield
.imm8
= 1;
2247 t
.bitfield
.imm16
= 1;
2248 t
.bitfield
.imm32
= 1;
2249 t
.bitfield
.imm32s
= 1;
2251 else if (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
2253 t
.bitfield
.imm16
= 1;
2254 t
.bitfield
.imm32
= 1;
2255 t
.bitfield
.imm32s
= 1;
2257 else if (fits_in_signed_long (num
))
2259 t
.bitfield
.imm32
= 1;
2260 t
.bitfield
.imm32s
= 1;
2262 else if (fits_in_unsigned_long (num
))
2263 t
.bitfield
.imm32
= 1;
2269 offset_in_range (offsetT val
, int size
)
2275 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
2276 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
2277 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
2279 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
2285 /* If BFD64, sign extend val for 32bit address mode. */
2286 if (flag_code
!= CODE_64BIT
2287 || i
.prefix
[ADDR_PREFIX
])
2288 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
2289 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
2292 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
2294 char buf1
[40], buf2
[40];
2296 sprint_value (buf1
, val
);
2297 sprint_value (buf2
, val
& mask
);
2298 as_warn (_("%s shortened to %s"), buf1
, buf2
);
2313 a. PREFIX_EXIST if attempting to add a prefix where one from the
2314 same class already exists.
2315 b. PREFIX_LOCK if lock prefix is added.
2316 c. PREFIX_REP if rep/repne prefix is added.
2317 d. PREFIX_DS if ds prefix is added.
2318 e. PREFIX_OTHER if other prefix is added.
2321 static enum PREFIX_GROUP
2322 add_prefix (unsigned int prefix
)
2324 enum PREFIX_GROUP ret
= PREFIX_OTHER
;
2327 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
2328 && flag_code
== CODE_64BIT
)
2330 if ((i
.prefix
[REX_PREFIX
] & prefix
& REX_W
)
2331 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_R
)
2332 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_X
)
2333 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_B
))
2344 case DS_PREFIX_OPCODE
:
2347 case CS_PREFIX_OPCODE
:
2348 case ES_PREFIX_OPCODE
:
2349 case FS_PREFIX_OPCODE
:
2350 case GS_PREFIX_OPCODE
:
2351 case SS_PREFIX_OPCODE
:
2355 case REPNE_PREFIX_OPCODE
:
2356 case REPE_PREFIX_OPCODE
:
2361 case LOCK_PREFIX_OPCODE
:
2370 case ADDR_PREFIX_OPCODE
:
2374 case DATA_PREFIX_OPCODE
:
2378 if (i
.prefix
[q
] != 0)
2386 i
.prefix
[q
] |= prefix
;
2389 as_bad (_("same type of prefix used twice"));
2395 update_code_flag (int value
, int check
)
2397 PRINTF_LIKE ((*as_error
));
2399 flag_code
= (enum flag_code
) value
;
2400 if (flag_code
== CODE_64BIT
)
2402 cpu_arch_flags
.bitfield
.cpu64
= 1;
2403 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2407 cpu_arch_flags
.bitfield
.cpu64
= 0;
2408 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2410 if (value
== CODE_64BIT
&& !cpu_arch_flags
.bitfield
.cpulm
)
2413 as_error
= as_fatal
;
2416 (*as_error
) (_("64bit mode not supported on `%s'."),
2417 cpu_arch_name
? cpu_arch_name
: default_arch
);
2419 if (value
== CODE_32BIT
&& !cpu_arch_flags
.bitfield
.cpui386
)
2422 as_error
= as_fatal
;
2425 (*as_error
) (_("32bit mode not supported on `%s'."),
2426 cpu_arch_name
? cpu_arch_name
: default_arch
);
2428 stackop_size
= '\0';
2432 set_code_flag (int value
)
2434 update_code_flag (value
, 0);
2438 set_16bit_gcc_code_flag (int new_code_flag
)
2440 flag_code
= (enum flag_code
) new_code_flag
;
2441 if (flag_code
!= CODE_16BIT
)
2443 cpu_arch_flags
.bitfield
.cpu64
= 0;
2444 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2445 stackop_size
= LONG_MNEM_SUFFIX
;
2449 set_intel_syntax (int syntax_flag
)
2451 /* Find out if register prefixing is specified. */
2452 int ask_naked_reg
= 0;
2455 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2458 int e
= get_symbol_name (&string
);
2460 if (strcmp (string
, "prefix") == 0)
2462 else if (strcmp (string
, "noprefix") == 0)
2465 as_bad (_("bad argument to syntax directive."));
2466 (void) restore_line_pointer (e
);
2468 demand_empty_rest_of_line ();
2470 intel_syntax
= syntax_flag
;
2472 if (ask_naked_reg
== 0)
2473 allow_naked_reg
= (intel_syntax
2474 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
2476 allow_naked_reg
= (ask_naked_reg
< 0);
2478 expr_set_rank (O_full_ptr
, syntax_flag
? 10 : 0);
2480 identifier_chars
['%'] = intel_syntax
&& allow_naked_reg
? '%' : 0;
2481 identifier_chars
['$'] = intel_syntax
? '$' : 0;
2482 register_prefix
= allow_naked_reg
? "" : "%";
2486 set_intel_mnemonic (int mnemonic_flag
)
2488 intel_mnemonic
= mnemonic_flag
;
2492 set_allow_index_reg (int flag
)
2494 allow_index_reg
= flag
;
2498 set_check (int what
)
2500 enum check_kind
*kind
;
2505 kind
= &operand_check
;
2516 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2519 int e
= get_symbol_name (&string
);
2521 if (strcmp (string
, "none") == 0)
2523 else if (strcmp (string
, "warning") == 0)
2524 *kind
= check_warning
;
2525 else if (strcmp (string
, "error") == 0)
2526 *kind
= check_error
;
2528 as_bad (_("bad argument to %s_check directive."), str
);
2529 (void) restore_line_pointer (e
);
2532 as_bad (_("missing argument for %s_check directive"), str
);
2534 demand_empty_rest_of_line ();
2538 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED
,
2539 i386_cpu_flags new_flag ATTRIBUTE_UNUSED
)
2541 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2542 static const char *arch
;
2544 /* Intel LIOM is only supported on ELF. */
2550 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2551 use default_arch. */
2552 arch
= cpu_arch_name
;
2554 arch
= default_arch
;
2557 /* If we are targeting Intel MCU, we must enable it. */
2558 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_IAMCU
2559 || new_flag
.bitfield
.cpuiamcu
)
2562 /* If we are targeting Intel L1OM, we must enable it. */
2563 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_L1OM
2564 || new_flag
.bitfield
.cpul1om
)
2567 /* If we are targeting Intel K1OM, we must enable it. */
2568 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_K1OM
2569 || new_flag
.bitfield
.cpuk1om
)
2572 as_bad (_("`%s' is not supported on `%s'"), name
, arch
);
2577 set_cpu_arch (int dummy ATTRIBUTE_UNUSED
)
2581 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2584 int e
= get_symbol_name (&string
);
2586 i386_cpu_flags flags
;
2588 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
2590 if (strcmp (string
, cpu_arch
[j
].name
) == 0)
2592 check_cpu_arch_compatible (string
, cpu_arch
[j
].flags
);
2596 cpu_arch_name
= cpu_arch
[j
].name
;
2597 cpu_sub_arch_name
= NULL
;
2598 cpu_arch_flags
= cpu_arch
[j
].flags
;
2599 if (flag_code
== CODE_64BIT
)
2601 cpu_arch_flags
.bitfield
.cpu64
= 1;
2602 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2606 cpu_arch_flags
.bitfield
.cpu64
= 0;
2607 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2609 cpu_arch_isa
= cpu_arch
[j
].type
;
2610 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
2611 if (!cpu_arch_tune_set
)
2613 cpu_arch_tune
= cpu_arch_isa
;
2614 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
2619 flags
= cpu_flags_or (cpu_arch_flags
,
2622 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2624 if (cpu_sub_arch_name
)
2626 char *name
= cpu_sub_arch_name
;
2627 cpu_sub_arch_name
= concat (name
,
2629 (const char *) NULL
);
2633 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
2634 cpu_arch_flags
= flags
;
2635 cpu_arch_isa_flags
= flags
;
2639 = cpu_flags_or (cpu_arch_isa_flags
,
2641 (void) restore_line_pointer (e
);
2642 demand_empty_rest_of_line ();
2647 if (*string
== '.' && j
>= ARRAY_SIZE (cpu_arch
))
2649 /* Disable an ISA extension. */
2650 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
2651 if (strcmp (string
+ 1, cpu_noarch
[j
].name
) == 0)
2653 flags
= cpu_flags_and_not (cpu_arch_flags
,
2654 cpu_noarch
[j
].flags
);
2655 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2657 if (cpu_sub_arch_name
)
2659 char *name
= cpu_sub_arch_name
;
2660 cpu_sub_arch_name
= concat (name
, string
,
2661 (const char *) NULL
);
2665 cpu_sub_arch_name
= xstrdup (string
);
2666 cpu_arch_flags
= flags
;
2667 cpu_arch_isa_flags
= flags
;
2669 (void) restore_line_pointer (e
);
2670 demand_empty_rest_of_line ();
2674 j
= ARRAY_SIZE (cpu_arch
);
2677 if (j
>= ARRAY_SIZE (cpu_arch
))
2678 as_bad (_("no such architecture: `%s'"), string
);
2680 *input_line_pointer
= e
;
2683 as_bad (_("missing cpu architecture"));
2685 no_cond_jump_promotion
= 0;
2686 if (*input_line_pointer
== ','
2687 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
2692 ++input_line_pointer
;
2693 e
= get_symbol_name (&string
);
2695 if (strcmp (string
, "nojumps") == 0)
2696 no_cond_jump_promotion
= 1;
2697 else if (strcmp (string
, "jumps") == 0)
2700 as_bad (_("no such architecture modifier: `%s'"), string
);
2702 (void) restore_line_pointer (e
);
2705 demand_empty_rest_of_line ();
2708 enum bfd_architecture
2711 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2713 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2714 || flag_code
!= CODE_64BIT
)
2715 as_fatal (_("Intel L1OM is 64bit ELF only"));
2716 return bfd_arch_l1om
;
2718 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2720 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2721 || flag_code
!= CODE_64BIT
)
2722 as_fatal (_("Intel K1OM is 64bit ELF only"));
2723 return bfd_arch_k1om
;
2725 else if (cpu_arch_isa
== PROCESSOR_IAMCU
)
2727 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2728 || flag_code
== CODE_64BIT
)
2729 as_fatal (_("Intel MCU is 32bit ELF only"));
2730 return bfd_arch_iamcu
;
2733 return bfd_arch_i386
;
2739 if (!strncmp (default_arch
, "x86_64", 6))
2741 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2743 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2744 || default_arch
[6] != '\0')
2745 as_fatal (_("Intel L1OM is 64bit ELF only"));
2746 return bfd_mach_l1om
;
2748 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2750 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2751 || default_arch
[6] != '\0')
2752 as_fatal (_("Intel K1OM is 64bit ELF only"));
2753 return bfd_mach_k1om
;
2755 else if (default_arch
[6] == '\0')
2756 return bfd_mach_x86_64
;
2758 return bfd_mach_x64_32
;
2760 else if (!strcmp (default_arch
, "i386")
2761 || !strcmp (default_arch
, "iamcu"))
2763 if (cpu_arch_isa
== PROCESSOR_IAMCU
)
2765 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
2766 as_fatal (_("Intel MCU is 32bit ELF only"));
2767 return bfd_mach_i386_iamcu
;
2770 return bfd_mach_i386_i386
;
2773 as_fatal (_("unknown architecture"));
2779 const char *hash_err
;
2781 /* Support pseudo prefixes like {disp32}. */
2782 lex_type
['{'] = LEX_BEGIN_NAME
;
2784 /* Initialize op_hash hash table. */
2785 op_hash
= hash_new ();
2788 const insn_template
*optab
;
2789 templates
*core_optab
;
2791 /* Setup for loop. */
2793 core_optab
= XNEW (templates
);
2794 core_optab
->start
= optab
;
2799 if (optab
->name
== NULL
2800 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
2802 /* different name --> ship out current template list;
2803 add to hash table; & begin anew. */
2804 core_optab
->end
= optab
;
2805 hash_err
= hash_insert (op_hash
,
2807 (void *) core_optab
);
2810 as_fatal (_("can't hash %s: %s"),
2814 if (optab
->name
== NULL
)
2816 core_optab
= XNEW (templates
);
2817 core_optab
->start
= optab
;
2822 /* Initialize reg_hash hash table. */
2823 reg_hash
= hash_new ();
2825 const reg_entry
*regtab
;
2826 unsigned int regtab_size
= i386_regtab_size
;
2828 for (regtab
= i386_regtab
; regtab_size
--; regtab
++)
2830 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (void *) regtab
);
2832 as_fatal (_("can't hash %s: %s"),
2838 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
2843 for (c
= 0; c
< 256; c
++)
2848 mnemonic_chars
[c
] = c
;
2849 register_chars
[c
] = c
;
2850 operand_chars
[c
] = c
;
2852 else if (ISLOWER (c
))
2854 mnemonic_chars
[c
] = c
;
2855 register_chars
[c
] = c
;
2856 operand_chars
[c
] = c
;
2858 else if (ISUPPER (c
))
2860 mnemonic_chars
[c
] = TOLOWER (c
);
2861 register_chars
[c
] = mnemonic_chars
[c
];
2862 operand_chars
[c
] = c
;
2864 else if (c
== '{' || c
== '}')
2866 mnemonic_chars
[c
] = c
;
2867 operand_chars
[c
] = c
;
2870 if (ISALPHA (c
) || ISDIGIT (c
))
2871 identifier_chars
[c
] = c
;
2874 identifier_chars
[c
] = c
;
2875 operand_chars
[c
] = c
;
2880 identifier_chars
['@'] = '@';
2883 identifier_chars
['?'] = '?';
2884 operand_chars
['?'] = '?';
2886 digit_chars
['-'] = '-';
2887 mnemonic_chars
['_'] = '_';
2888 mnemonic_chars
['-'] = '-';
2889 mnemonic_chars
['.'] = '.';
2890 identifier_chars
['_'] = '_';
2891 identifier_chars
['.'] = '.';
2893 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
2894 operand_chars
[(unsigned char) *p
] = *p
;
2897 if (flag_code
== CODE_64BIT
)
2899 #if defined (OBJ_COFF) && defined (TE_PE)
2900 x86_dwarf2_return_column
= (OUTPUT_FLAVOR
== bfd_target_coff_flavour
2903 x86_dwarf2_return_column
= 16;
2905 x86_cie_data_alignment
= -8;
2909 x86_dwarf2_return_column
= 8;
2910 x86_cie_data_alignment
= -4;
2915 i386_print_statistics (FILE *file
)
2917 hash_print_statistics (file
, "i386 opcode", op_hash
);
2918 hash_print_statistics (file
, "i386 register", reg_hash
);
2923 /* Debugging routines for md_assemble. */
2924 static void pte (insn_template
*);
2925 static void pt (i386_operand_type
);
2926 static void pe (expressionS
*);
2927 static void ps (symbolS
*);
2930 pi (char *line
, i386_insn
*x
)
2934 fprintf (stdout
, "%s: template ", line
);
2936 fprintf (stdout
, " address: base %s index %s scale %x\n",
2937 x
->base_reg
? x
->base_reg
->reg_name
: "none",
2938 x
->index_reg
? x
->index_reg
->reg_name
: "none",
2939 x
->log2_scale_factor
);
2940 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
2941 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
2942 fprintf (stdout
, " sib: base %x index %x scale %x\n",
2943 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
2944 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
2945 (x
->rex
& REX_W
) != 0,
2946 (x
->rex
& REX_R
) != 0,
2947 (x
->rex
& REX_X
) != 0,
2948 (x
->rex
& REX_B
) != 0);
2949 for (j
= 0; j
< x
->operands
; j
++)
2951 fprintf (stdout
, " #%d: ", j
+ 1);
2953 fprintf (stdout
, "\n");
2954 if (x
->types
[j
].bitfield
.reg
2955 || x
->types
[j
].bitfield
.regmmx
2956 || x
->types
[j
].bitfield
.regsimd
2957 || x
->types
[j
].bitfield
.sreg2
2958 || x
->types
[j
].bitfield
.sreg3
2959 || x
->types
[j
].bitfield
.control
2960 || x
->types
[j
].bitfield
.debug
2961 || x
->types
[j
].bitfield
.test
)
2962 fprintf (stdout
, "%s\n", x
->op
[j
].regs
->reg_name
);
2963 if (operand_type_check (x
->types
[j
], imm
))
2965 if (operand_type_check (x
->types
[j
], disp
))
2966 pe (x
->op
[j
].disps
);
2971 pte (insn_template
*t
)
2974 fprintf (stdout
, " %d operands ", t
->operands
);
2975 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
2976 if (t
->extension_opcode
!= None
)
2977 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
2978 if (t
->opcode_modifier
.d
)
2979 fprintf (stdout
, "D");
2980 if (t
->opcode_modifier
.w
)
2981 fprintf (stdout
, "W");
2982 fprintf (stdout
, "\n");
2983 for (j
= 0; j
< t
->operands
; j
++)
2985 fprintf (stdout
, " #%d type ", j
+ 1);
2986 pt (t
->operand_types
[j
]);
2987 fprintf (stdout
, "\n");
2994 fprintf (stdout
, " operation %d\n", e
->X_op
);
2995 fprintf (stdout
, " add_number %ld (%lx)\n",
2996 (long) e
->X_add_number
, (long) e
->X_add_number
);
2997 if (e
->X_add_symbol
)
2999 fprintf (stdout
, " add_symbol ");
3000 ps (e
->X_add_symbol
);
3001 fprintf (stdout
, "\n");
3005 fprintf (stdout
, " op_symbol ");
3006 ps (e
->X_op_symbol
);
3007 fprintf (stdout
, "\n");
3014 fprintf (stdout
, "%s type %s%s",
3016 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
3017 segment_name (S_GET_SEGMENT (s
)));
3020 static struct type_name
3022 i386_operand_type mask
;
3025 const type_names
[] =
3027 { OPERAND_TYPE_REG8
, "r8" },
3028 { OPERAND_TYPE_REG16
, "r16" },
3029 { OPERAND_TYPE_REG32
, "r32" },
3030 { OPERAND_TYPE_REG64
, "r64" },
3031 { OPERAND_TYPE_IMM8
, "i8" },
3032 { OPERAND_TYPE_IMM8
, "i8s" },
3033 { OPERAND_TYPE_IMM16
, "i16" },
3034 { OPERAND_TYPE_IMM32
, "i32" },
3035 { OPERAND_TYPE_IMM32S
, "i32s" },
3036 { OPERAND_TYPE_IMM64
, "i64" },
3037 { OPERAND_TYPE_IMM1
, "i1" },
3038 { OPERAND_TYPE_BASEINDEX
, "BaseIndex" },
3039 { OPERAND_TYPE_DISP8
, "d8" },
3040 { OPERAND_TYPE_DISP16
, "d16" },
3041 { OPERAND_TYPE_DISP32
, "d32" },
3042 { OPERAND_TYPE_DISP32S
, "d32s" },
3043 { OPERAND_TYPE_DISP64
, "d64" },
3044 { OPERAND_TYPE_INOUTPORTREG
, "InOutPortReg" },
3045 { OPERAND_TYPE_SHIFTCOUNT
, "ShiftCount" },
3046 { OPERAND_TYPE_CONTROL
, "control reg" },
3047 { OPERAND_TYPE_TEST
, "test reg" },
3048 { OPERAND_TYPE_DEBUG
, "debug reg" },
3049 { OPERAND_TYPE_FLOATREG
, "FReg" },
3050 { OPERAND_TYPE_FLOATACC
, "FAcc" },
3051 { OPERAND_TYPE_SREG2
, "SReg2" },
3052 { OPERAND_TYPE_SREG3
, "SReg3" },
3053 { OPERAND_TYPE_ACC
, "Acc" },
3054 { OPERAND_TYPE_JUMPABSOLUTE
, "Jump Absolute" },
3055 { OPERAND_TYPE_REGMMX
, "rMMX" },
3056 { OPERAND_TYPE_REGXMM
, "rXMM" },
3057 { OPERAND_TYPE_REGYMM
, "rYMM" },
3058 { OPERAND_TYPE_REGZMM
, "rZMM" },
3059 { OPERAND_TYPE_REGMASK
, "Mask reg" },
3060 { OPERAND_TYPE_ESSEG
, "es" },
3064 pt (i386_operand_type t
)
3067 i386_operand_type a
;
3069 for (j
= 0; j
< ARRAY_SIZE (type_names
); j
++)
3071 a
= operand_type_and (t
, type_names
[j
].mask
);
3072 if (!operand_type_all_zero (&a
))
3073 fprintf (stdout
, "%s, ", type_names
[j
].name
);
3078 #endif /* DEBUG386 */
3080 static bfd_reloc_code_real_type
3081 reloc (unsigned int size
,
3084 bfd_reloc_code_real_type other
)
3086 if (other
!= NO_RELOC
)
3088 reloc_howto_type
*rel
;
3093 case BFD_RELOC_X86_64_GOT32
:
3094 return BFD_RELOC_X86_64_GOT64
;
3096 case BFD_RELOC_X86_64_GOTPLT64
:
3097 return BFD_RELOC_X86_64_GOTPLT64
;
3099 case BFD_RELOC_X86_64_PLTOFF64
:
3100 return BFD_RELOC_X86_64_PLTOFF64
;
3102 case BFD_RELOC_X86_64_GOTPC32
:
3103 other
= BFD_RELOC_X86_64_GOTPC64
;
3105 case BFD_RELOC_X86_64_GOTPCREL
:
3106 other
= BFD_RELOC_X86_64_GOTPCREL64
;
3108 case BFD_RELOC_X86_64_TPOFF32
:
3109 other
= BFD_RELOC_X86_64_TPOFF64
;
3111 case BFD_RELOC_X86_64_DTPOFF32
:
3112 other
= BFD_RELOC_X86_64_DTPOFF64
;
3118 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3119 if (other
== BFD_RELOC_SIZE32
)
3122 other
= BFD_RELOC_SIZE64
;
3125 as_bad (_("there are no pc-relative size relocations"));
3131 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
3132 if (size
== 4 && (flag_code
!= CODE_64BIT
|| disallow_64bit_reloc
))
3135 rel
= bfd_reloc_type_lookup (stdoutput
, other
);
3137 as_bad (_("unknown relocation (%u)"), other
);
3138 else if (size
!= bfd_get_reloc_size (rel
))
3139 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
3140 bfd_get_reloc_size (rel
),
3142 else if (pcrel
&& !rel
->pc_relative
)
3143 as_bad (_("non-pc-relative relocation for pc-relative field"));
3144 else if ((rel
->complain_on_overflow
== complain_overflow_signed
3146 || (rel
->complain_on_overflow
== complain_overflow_unsigned
3148 as_bad (_("relocated field and relocation type differ in signedness"));
3157 as_bad (_("there are no unsigned pc-relative relocations"));
3160 case 1: return BFD_RELOC_8_PCREL
;
3161 case 2: return BFD_RELOC_16_PCREL
;
3162 case 4: return BFD_RELOC_32_PCREL
;
3163 case 8: return BFD_RELOC_64_PCREL
;
3165 as_bad (_("cannot do %u byte pc-relative relocation"), size
);
3172 case 4: return BFD_RELOC_X86_64_32S
;
3177 case 1: return BFD_RELOC_8
;
3178 case 2: return BFD_RELOC_16
;
3179 case 4: return BFD_RELOC_32
;
3180 case 8: return BFD_RELOC_64
;
3182 as_bad (_("cannot do %s %u byte relocation"),
3183 sign
> 0 ? "signed" : "unsigned", size
);
3189 /* Here we decide which fixups can be adjusted to make them relative to
3190 the beginning of the section instead of the symbol. Basically we need
3191 to make sure that the dynamic relocations are done correctly, so in
3192 some cases we force the original symbol to be used. */
3195 tc_i386_fix_adjustable (fixS
*fixP ATTRIBUTE_UNUSED
)
3197 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3201 /* Don't adjust pc-relative references to merge sections in 64-bit
3203 if (use_rela_relocations
3204 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
3208 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
3209 and changed later by validate_fix. */
3210 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
3211 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
3214 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
3215 for size relocations. */
3216 if (fixP
->fx_r_type
== BFD_RELOC_SIZE32
3217 || fixP
->fx_r_type
== BFD_RELOC_SIZE64
3218 || fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
3219 || fixP
->fx_r_type
== BFD_RELOC_386_PLT32
3220 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
3221 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32X
3222 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
3223 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
3224 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
3225 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
3226 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
3227 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
3228 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
3229 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
3230 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTDESC
3231 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_DESC_CALL
3232 || fixP
->fx_r_type
== BFD_RELOC_X86_64_PLT32
3233 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
3234 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
3235 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCRELX
3236 || fixP
->fx_r_type
== BFD_RELOC_X86_64_REX_GOTPCRELX
3237 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
3238 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
3239 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
3240 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
3241 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
3242 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
3243 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
3244 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
3245 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPC32_TLSDESC
3246 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSDESC_CALL
3247 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
3248 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
3255 intel_float_operand (const char *mnemonic
)
3257 /* Note that the value returned is meaningful only for opcodes with (memory)
3258 operands, hence the code here is free to improperly handle opcodes that
3259 have no operands (for better performance and smaller code). */
3261 if (mnemonic
[0] != 'f')
3262 return 0; /* non-math */
3264 switch (mnemonic
[1])
3266 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
3267 the fs segment override prefix not currently handled because no
3268 call path can make opcodes without operands get here */
3270 return 2 /* integer op */;
3272 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
3273 return 3; /* fldcw/fldenv */
3276 if (mnemonic
[2] != 'o' /* fnop */)
3277 return 3; /* non-waiting control op */
3280 if (mnemonic
[2] == 's')
3281 return 3; /* frstor/frstpm */
3284 if (mnemonic
[2] == 'a')
3285 return 3; /* fsave */
3286 if (mnemonic
[2] == 't')
3288 switch (mnemonic
[3])
3290 case 'c': /* fstcw */
3291 case 'd': /* fstdw */
3292 case 'e': /* fstenv */
3293 case 's': /* fsts[gw] */
3299 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
3300 return 0; /* fxsave/fxrstor are not really math ops */
3307 /* Build the VEX prefix. */
3310 build_vex_prefix (const insn_template
*t
)
3312 unsigned int register_specifier
;
3313 unsigned int implied_prefix
;
3314 unsigned int vector_length
;
3316 /* Check register specifier. */
3317 if (i
.vex
.register_specifier
)
3319 register_specifier
=
3320 ~register_number (i
.vex
.register_specifier
) & 0xf;
3321 gas_assert ((i
.vex
.register_specifier
->reg_flags
& RegVRex
) == 0);
3324 register_specifier
= 0xf;
3326 /* Use 2-byte VEX prefix by swapping destination and source
3328 if (i
.vec_encoding
!= vex_encoding_vex3
3329 && i
.dir_encoding
== dir_encoding_default
3330 && i
.operands
== i
.reg_operands
3331 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3332 && i
.tm
.opcode_modifier
.load
3335 unsigned int xchg
= i
.operands
- 1;
3336 union i386_op temp_op
;
3337 i386_operand_type temp_type
;
3339 temp_type
= i
.types
[xchg
];
3340 i
.types
[xchg
] = i
.types
[0];
3341 i
.types
[0] = temp_type
;
3342 temp_op
= i
.op
[xchg
];
3343 i
.op
[xchg
] = i
.op
[0];
3346 gas_assert (i
.rm
.mode
== 3);
3350 i
.rm
.regmem
= i
.rm
.reg
;
3353 /* Use the next insn. */
3357 if (i
.tm
.opcode_modifier
.vex
== VEXScalar
)
3358 vector_length
= avxscalar
;
3359 else if (i
.tm
.opcode_modifier
.vex
== VEX256
)
3366 for (op
= 0; op
< t
->operands
; ++op
)
3367 if (t
->operand_types
[op
].bitfield
.xmmword
3368 && t
->operand_types
[op
].bitfield
.ymmword
3369 && i
.types
[op
].bitfield
.ymmword
)
3376 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3381 case DATA_PREFIX_OPCODE
:
3384 case REPE_PREFIX_OPCODE
:
3387 case REPNE_PREFIX_OPCODE
:
3394 /* Use 2-byte VEX prefix if possible. */
3395 if (i
.vec_encoding
!= vex_encoding_vex3
3396 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3397 && i
.tm
.opcode_modifier
.vexw
!= VEXW1
3398 && (i
.rex
& (REX_W
| REX_X
| REX_B
)) == 0)
3400 /* 2-byte VEX prefix. */
3404 i
.vex
.bytes
[0] = 0xc5;
3406 /* Check the REX.R bit. */
3407 r
= (i
.rex
& REX_R
) ? 0 : 1;
3408 i
.vex
.bytes
[1] = (r
<< 7
3409 | register_specifier
<< 3
3410 | vector_length
<< 2
3415 /* 3-byte VEX prefix. */
3420 switch (i
.tm
.opcode_modifier
.vexopcode
)
3424 i
.vex
.bytes
[0] = 0xc4;
3428 i
.vex
.bytes
[0] = 0xc4;
3432 i
.vex
.bytes
[0] = 0xc4;
3436 i
.vex
.bytes
[0] = 0x8f;
3440 i
.vex
.bytes
[0] = 0x8f;
3444 i
.vex
.bytes
[0] = 0x8f;
3450 /* The high 3 bits of the second VEX byte are 1's compliment
3451 of RXB bits from REX. */
3452 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3454 /* Check the REX.W bit. */
3455 w
= (i
.rex
& REX_W
) ? 1 : 0;
3456 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
3459 i
.vex
.bytes
[2] = (w
<< 7
3460 | register_specifier
<< 3
3461 | vector_length
<< 2
3466 static INLINE bfd_boolean
3467 is_evex_encoding (const insn_template
*t
)
3469 return t
->opcode_modifier
.evex
|| t
->opcode_modifier
.disp8memshift
3470 || t
->opcode_modifier
.broadcast
|| t
->opcode_modifier
.masking
3471 || t
->opcode_modifier
.staticrounding
|| t
->opcode_modifier
.sae
;
3474 /* Build the EVEX prefix. */
3477 build_evex_prefix (void)
3479 unsigned int register_specifier
;
3480 unsigned int implied_prefix
;
3482 rex_byte vrex_used
= 0;
3484 /* Check register specifier. */
3485 if (i
.vex
.register_specifier
)
3487 gas_assert ((i
.vrex
& REX_X
) == 0);
3489 register_specifier
= i
.vex
.register_specifier
->reg_num
;
3490 if ((i
.vex
.register_specifier
->reg_flags
& RegRex
))
3491 register_specifier
+= 8;
3492 /* The upper 16 registers are encoded in the fourth byte of the
3494 if (!(i
.vex
.register_specifier
->reg_flags
& RegVRex
))
3495 i
.vex
.bytes
[3] = 0x8;
3496 register_specifier
= ~register_specifier
& 0xf;
3500 register_specifier
= 0xf;
3502 /* Encode upper 16 vector index register in the fourth byte of
3504 if (!(i
.vrex
& REX_X
))
3505 i
.vex
.bytes
[3] = 0x8;
3510 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3515 case DATA_PREFIX_OPCODE
:
3518 case REPE_PREFIX_OPCODE
:
3521 case REPNE_PREFIX_OPCODE
:
3528 /* 4 byte EVEX prefix. */
3530 i
.vex
.bytes
[0] = 0x62;
3533 switch (i
.tm
.opcode_modifier
.vexopcode
)
3549 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3551 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3553 /* The fifth bit of the second EVEX byte is 1's compliment of the
3554 REX_R bit in VREX. */
3555 if (!(i
.vrex
& REX_R
))
3556 i
.vex
.bytes
[1] |= 0x10;
3560 if ((i
.reg_operands
+ i
.imm_operands
) == i
.operands
)
3562 /* When all operands are registers, the REX_X bit in REX is not
3563 used. We reuse it to encode the upper 16 registers, which is
3564 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3565 as 1's compliment. */
3566 if ((i
.vrex
& REX_B
))
3569 i
.vex
.bytes
[1] &= ~0x40;
3573 /* EVEX instructions shouldn't need the REX prefix. */
3574 i
.vrex
&= ~vrex_used
;
3575 gas_assert (i
.vrex
== 0);
3577 /* Check the REX.W bit. */
3578 w
= (i
.rex
& REX_W
) ? 1 : 0;
3579 if (i
.tm
.opcode_modifier
.vexw
)
3581 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
3584 /* If w is not set it means we are dealing with WIG instruction. */
3587 if (evexwig
== evexw1
)
3591 /* Encode the U bit. */
3592 implied_prefix
|= 0x4;
3594 /* The third byte of the EVEX prefix. */
3595 i
.vex
.bytes
[2] = (w
<< 7 | register_specifier
<< 3 | implied_prefix
);
3597 /* The fourth byte of the EVEX prefix. */
3598 /* The zeroing-masking bit. */
3599 if (i
.mask
&& i
.mask
->zeroing
)
3600 i
.vex
.bytes
[3] |= 0x80;
3602 /* Don't always set the broadcast bit if there is no RC. */
3605 /* Encode the vector length. */
3606 unsigned int vec_length
;
3608 if (!i
.tm
.opcode_modifier
.evex
3609 || i
.tm
.opcode_modifier
.evex
== EVEXDYN
)
3614 for (op
= 0; op
< i
.tm
.operands
; ++op
)
3615 if (i
.tm
.operand_types
[op
].bitfield
.xmmword
3616 + i
.tm
.operand_types
[op
].bitfield
.ymmword
3617 + i
.tm
.operand_types
[op
].bitfield
.zmmword
> 1)
3619 if (i
.types
[op
].bitfield
.zmmword
)
3620 i
.tm
.opcode_modifier
.evex
= EVEX512
;
3621 else if (i
.types
[op
].bitfield
.ymmword
)
3622 i
.tm
.opcode_modifier
.evex
= EVEX256
;
3623 else if (i
.types
[op
].bitfield
.xmmword
)
3624 i
.tm
.opcode_modifier
.evex
= EVEX128
;
3631 switch (i
.tm
.opcode_modifier
.evex
)
3633 case EVEXLIG
: /* LL' is ignored */
3634 vec_length
= evexlig
<< 5;
3637 vec_length
= 0 << 5;
3640 vec_length
= 1 << 5;
3643 vec_length
= 2 << 5;
3649 i
.vex
.bytes
[3] |= vec_length
;
3650 /* Encode the broadcast bit. */
3652 i
.vex
.bytes
[3] |= 0x10;
3656 if (i
.rounding
->type
!= saeonly
)
3657 i
.vex
.bytes
[3] |= 0x10 | (i
.rounding
->type
<< 5);
3659 i
.vex
.bytes
[3] |= 0x10 | (evexrcig
<< 5);
3662 if (i
.mask
&& i
.mask
->mask
)
3663 i
.vex
.bytes
[3] |= i
.mask
->mask
->reg_num
;
3667 process_immext (void)
3671 if ((i
.tm
.cpu_flags
.bitfield
.cpusse3
|| i
.tm
.cpu_flags
.bitfield
.cpusvme
)
3674 /* MONITOR/MWAIT as well as SVME instructions have fixed operands
3675 with an opcode suffix which is coded in the same place as an
3676 8-bit immediate field would be.
3677 Here we check those operands and remove them afterwards. */
3680 for (x
= 0; x
< i
.operands
; x
++)
3681 if (register_number (i
.op
[x
].regs
) != x
)
3682 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3683 register_prefix
, i
.op
[x
].regs
->reg_name
, x
+ 1,
3689 if (i
.tm
.cpu_flags
.bitfield
.cpumwaitx
&& i
.operands
> 0)
3691 /* MONITORX/MWAITX instructions have fixed operands with an opcode
3692 suffix which is coded in the same place as an 8-bit immediate
3694 Here we check those operands and remove them afterwards. */
3697 if (i
.operands
!= 3)
3700 for (x
= 0; x
< 2; x
++)
3701 if (register_number (i
.op
[x
].regs
) != x
)
3702 goto bad_register_operand
;
3704 /* Check for third operand for mwaitx/monitorx insn. */
3705 if (register_number (i
.op
[x
].regs
)
3706 != (x
+ (i
.tm
.extension_opcode
== 0xfb)))
3708 bad_register_operand
:
3709 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3710 register_prefix
, i
.op
[x
].regs
->reg_name
, x
+1,
3717 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
3718 which is coded in the same place as an 8-bit immediate field
3719 would be. Here we fake an 8-bit immediate operand from the
3720 opcode suffix stored in tm.extension_opcode.
3722 AVX instructions also use this encoding, for some of
3723 3 argument instructions. */
3725 gas_assert (i
.imm_operands
<= 1
3727 || ((i
.tm
.opcode_modifier
.vex
3728 || i
.tm
.opcode_modifier
.vexopcode
3729 || is_evex_encoding (&i
.tm
))
3730 && i
.operands
<= 4)));
3732 exp
= &im_expressions
[i
.imm_operands
++];
3733 i
.op
[i
.operands
].imms
= exp
;
3734 i
.types
[i
.operands
] = imm8
;
3736 exp
->X_op
= O_constant
;
3737 exp
->X_add_number
= i
.tm
.extension_opcode
;
3738 i
.tm
.extension_opcode
= None
;
3745 switch (i
.tm
.opcode_modifier
.hleprefixok
)
3750 as_bad (_("invalid instruction `%s' after `%s'"),
3751 i
.tm
.name
, i
.hle_prefix
);
3754 if (i
.prefix
[LOCK_PREFIX
])
3756 as_bad (_("missing `lock' with `%s'"), i
.hle_prefix
);
3760 case HLEPrefixRelease
:
3761 if (i
.prefix
[HLE_PREFIX
] != XRELEASE_PREFIX_OPCODE
)
3763 as_bad (_("instruction `%s' after `xacquire' not allowed"),
3767 if (i
.mem_operands
== 0
3768 || !operand_type_check (i
.types
[i
.operands
- 1], anymem
))
3770 as_bad (_("memory destination needed for instruction `%s'"
3771 " after `xrelease'"), i
.tm
.name
);
3778 /* Try the shortest encoding by shortening operand size. */
3781 optimize_encoding (void)
3785 if (optimize_for_space
3786 && i
.reg_operands
== 1
3787 && i
.imm_operands
== 1
3788 && !i
.types
[1].bitfield
.byte
3789 && i
.op
[0].imms
->X_op
== O_constant
3790 && fits_in_imm7 (i
.op
[0].imms
->X_add_number
)
3791 && ((i
.tm
.base_opcode
== 0xa8
3792 && i
.tm
.extension_opcode
== None
)
3793 || (i
.tm
.base_opcode
== 0xf6
3794 && i
.tm
.extension_opcode
== 0x0)))
3797 test $imm7, %r64/%r32/%r16 -> test $imm7, %r8
3799 unsigned int base_regnum
= i
.op
[1].regs
->reg_num
;
3800 if (flag_code
== CODE_64BIT
|| base_regnum
< 4)
3802 i
.types
[1].bitfield
.byte
= 1;
3803 /* Ignore the suffix. */
3805 if (base_regnum
>= 4
3806 && !(i
.op
[1].regs
->reg_flags
& RegRex
))
3808 /* Handle SP, BP, SI and DI registers. */
3809 if (i
.types
[1].bitfield
.word
)
3811 else if (i
.types
[1].bitfield
.dword
)
3819 else if (flag_code
== CODE_64BIT
3820 && ((i
.types
[1].bitfield
.qword
3821 && i
.reg_operands
== 1
3822 && i
.imm_operands
== 1
3823 && i
.op
[0].imms
->X_op
== O_constant
3824 && ((i
.tm
.base_opcode
== 0xb0
3825 && i
.tm
.extension_opcode
== None
3826 && fits_in_unsigned_long (i
.op
[0].imms
->X_add_number
))
3827 || (fits_in_imm31 (i
.op
[0].imms
->X_add_number
)
3828 && (((i
.tm
.base_opcode
== 0x24
3829 || i
.tm
.base_opcode
== 0xa8)
3830 && i
.tm
.extension_opcode
== None
)
3831 || (i
.tm
.base_opcode
== 0x80
3832 && i
.tm
.extension_opcode
== 0x4)
3833 || ((i
.tm
.base_opcode
== 0xf6
3834 || i
.tm
.base_opcode
== 0xc6)
3835 && i
.tm
.extension_opcode
== 0x0)))))
3836 || (i
.types
[0].bitfield
.qword
3837 && ((i
.reg_operands
== 2
3838 && i
.op
[0].regs
== i
.op
[1].regs
3839 && ((i
.tm
.base_opcode
== 0x30
3840 || i
.tm
.base_opcode
== 0x28)
3841 && i
.tm
.extension_opcode
== None
))
3842 || (i
.reg_operands
== 1
3844 && i
.tm
.base_opcode
== 0x30
3845 && i
.tm
.extension_opcode
== None
)))))
3848 andq $imm31, %r64 -> andl $imm31, %r32
3849 testq $imm31, %r64 -> testl $imm31, %r32
3850 xorq %r64, %r64 -> xorl %r32, %r32
3851 subq %r64, %r64 -> subl %r32, %r32
3852 movq $imm31, %r64 -> movl $imm31, %r32
3853 movq $imm32, %r64 -> movl $imm32, %r32
3855 i
.tm
.opcode_modifier
.norex64
= 1;
3856 if (i
.tm
.base_opcode
== 0xb0 || i
.tm
.base_opcode
== 0xc6)
3859 movq $imm31, %r64 -> movl $imm31, %r32
3860 movq $imm32, %r64 -> movl $imm32, %r32
3862 i
.tm
.operand_types
[0].bitfield
.imm32
= 1;
3863 i
.tm
.operand_types
[0].bitfield
.imm32s
= 0;
3864 i
.tm
.operand_types
[0].bitfield
.imm64
= 0;
3865 i
.types
[0].bitfield
.imm32
= 1;
3866 i
.types
[0].bitfield
.imm32s
= 0;
3867 i
.types
[0].bitfield
.imm64
= 0;
3868 i
.types
[1].bitfield
.dword
= 1;
3869 i
.types
[1].bitfield
.qword
= 0;
3870 if (i
.tm
.base_opcode
== 0xc6)
3873 movq $imm31, %r64 -> movl $imm31, %r32
3875 i
.tm
.base_opcode
= 0xb0;
3876 i
.tm
.extension_opcode
= None
;
3877 i
.tm
.opcode_modifier
.shortform
= 1;
3878 i
.tm
.opcode_modifier
.modrm
= 0;
3882 else if (optimize
> 1
3883 && i
.reg_operands
== 3
3884 && i
.op
[0].regs
== i
.op
[1].regs
3885 && !i
.types
[2].bitfield
.xmmword
3886 && (i
.tm
.opcode_modifier
.vex
3887 || ((!i
.mask
|| i
.mask
->zeroing
)
3889 && is_evex_encoding (&i
.tm
)
3890 && (i
.vec_encoding
!= vex_encoding_evex
3891 || i
.tm
.cpu_flags
.bitfield
.cpuavx512vl
3892 || (i
.tm
.operand_types
[2].bitfield
.zmmword
3893 && i
.types
[2].bitfield
.ymmword
)
3894 || cpu_arch_isa_flags
.bitfield
.cpuavx512vl
)))
3895 && ((i
.tm
.base_opcode
== 0x55
3896 || i
.tm
.base_opcode
== 0x6655
3897 || i
.tm
.base_opcode
== 0x66df
3898 || i
.tm
.base_opcode
== 0x57
3899 || i
.tm
.base_opcode
== 0x6657
3900 || i
.tm
.base_opcode
== 0x66ef
3901 || i
.tm
.base_opcode
== 0x66f8
3902 || i
.tm
.base_opcode
== 0x66f9
3903 || i
.tm
.base_opcode
== 0x66fa
3904 || i
.tm
.base_opcode
== 0x66fb)
3905 && i
.tm
.extension_opcode
== None
))
3908 VOP, one of vandnps, vandnpd, vxorps, vxorpd, vpsubb, vpsubd,
3910 EVEX VOP %zmmM, %zmmM, %zmmN
3911 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
3912 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3913 EVEX VOP %ymmM, %ymmM, %ymmN
3914 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
3915 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3916 VEX VOP %ymmM, %ymmM, %ymmN
3917 -> VEX VOP %xmmM, %xmmM, %xmmN
3918 VOP, one of vpandn and vpxor:
3919 VEX VOP %ymmM, %ymmM, %ymmN
3920 -> VEX VOP %xmmM, %xmmM, %xmmN
3921 VOP, one of vpandnd and vpandnq:
3922 EVEX VOP %zmmM, %zmmM, %zmmN
3923 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
3924 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3925 EVEX VOP %ymmM, %ymmM, %ymmN
3926 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
3927 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3928 VOP, one of vpxord and vpxorq:
3929 EVEX VOP %zmmM, %zmmM, %zmmN
3930 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
3931 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3932 EVEX VOP %ymmM, %ymmM, %ymmN
3933 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
3934 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3936 if (is_evex_encoding (&i
.tm
))
3938 if (i
.vec_encoding
== vex_encoding_evex
)
3939 i
.tm
.opcode_modifier
.evex
= EVEX128
;
3942 i
.tm
.opcode_modifier
.vex
= VEX128
;
3943 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
3944 i
.tm
.opcode_modifier
.evex
= 0;
3948 i
.tm
.opcode_modifier
.vex
= VEX128
;
3950 if (i
.tm
.opcode_modifier
.vex
)
3951 for (j
= 0; j
< 3; j
++)
3953 i
.types
[j
].bitfield
.xmmword
= 1;
3954 i
.types
[j
].bitfield
.ymmword
= 0;
3959 /* This is the guts of the machine-dependent assembler. LINE points to a
3960 machine dependent instruction. This function is supposed to emit
3961 the frags/bytes it assembles to. */
3964 md_assemble (char *line
)
3967 char mnemonic
[MAX_MNEM_SIZE
], mnem_suffix
;
3968 const insn_template
*t
;
3970 /* Initialize globals. */
3971 memset (&i
, '\0', sizeof (i
));
3972 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3973 i
.reloc
[j
] = NO_RELOC
;
3974 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
3975 memset (im_expressions
, '\0', sizeof (im_expressions
));
3976 save_stack_p
= save_stack
;
3978 /* First parse an instruction mnemonic & call i386_operand for the operands.
3979 We assume that the scrubber has arranged it so that line[0] is the valid
3980 start of a (possibly prefixed) mnemonic. */
3982 line
= parse_insn (line
, mnemonic
);
3985 mnem_suffix
= i
.suffix
;
3987 line
= parse_operands (line
, mnemonic
);
3989 xfree (i
.memop1_string
);
3990 i
.memop1_string
= NULL
;
3994 /* Now we've parsed the mnemonic into a set of templates, and have the
3995 operands at hand. */
3997 /* All intel opcodes have reversed operands except for "bound" and
3998 "enter". We also don't reverse intersegment "jmp" and "call"
3999 instructions with 2 immediate operands so that the immediate segment
4000 precedes the offset, as it does when in AT&T mode. */
4003 && (strcmp (mnemonic
, "bound") != 0)
4004 && (strcmp (mnemonic
, "invlpga") != 0)
4005 && !(operand_type_check (i
.types
[0], imm
)
4006 && operand_type_check (i
.types
[1], imm
)))
4009 /* The order of the immediates should be reversed
4010 for 2 immediates extrq and insertq instructions */
4011 if (i
.imm_operands
== 2
4012 && (strcmp (mnemonic
, "extrq") == 0
4013 || strcmp (mnemonic
, "insertq") == 0))
4014 swap_2_operands (0, 1);
4019 /* Don't optimize displacement for movabs since it only takes 64bit
4022 && i
.disp_encoding
!= disp_encoding_32bit
4023 && (flag_code
!= CODE_64BIT
4024 || strcmp (mnemonic
, "movabs") != 0))
4027 /* Next, we find a template that matches the given insn,
4028 making sure the overlap of the given operands types is consistent
4029 with the template operand types. */
4031 if (!(t
= match_template (mnem_suffix
)))
4034 if (sse_check
!= check_none
4035 && !i
.tm
.opcode_modifier
.noavx
4036 && !i
.tm
.cpu_flags
.bitfield
.cpuavx
4037 && (i
.tm
.cpu_flags
.bitfield
.cpusse
4038 || i
.tm
.cpu_flags
.bitfield
.cpusse2
4039 || i
.tm
.cpu_flags
.bitfield
.cpusse3
4040 || i
.tm
.cpu_flags
.bitfield
.cpussse3
4041 || i
.tm
.cpu_flags
.bitfield
.cpusse4_1
4042 || i
.tm
.cpu_flags
.bitfield
.cpusse4_2
4043 || i
.tm
.cpu_flags
.bitfield
.cpupclmul
4044 || i
.tm
.cpu_flags
.bitfield
.cpuaes
4045 || i
.tm
.cpu_flags
.bitfield
.cpugfni
))
4047 (sse_check
== check_warning
4049 : as_bad
) (_("SSE instruction `%s' is used"), i
.tm
.name
);
4052 /* Zap movzx and movsx suffix. The suffix has been set from
4053 "word ptr" or "byte ptr" on the source operand in Intel syntax
4054 or extracted from mnemonic in AT&T syntax. But we'll use
4055 the destination register to choose the suffix for encoding. */
4056 if ((i
.tm
.base_opcode
& ~9) == 0x0fb6)
4058 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
4059 there is no suffix, the default will be byte extension. */
4060 if (i
.reg_operands
!= 2
4063 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
4068 if (i
.tm
.opcode_modifier
.fwait
)
4069 if (!add_prefix (FWAIT_OPCODE
))
4072 /* Check if REP prefix is OK. */
4073 if (i
.rep_prefix
&& !i
.tm
.opcode_modifier
.repprefixok
)
4075 as_bad (_("invalid instruction `%s' after `%s'"),
4076 i
.tm
.name
, i
.rep_prefix
);
4080 /* Check for lock without a lockable instruction. Destination operand
4081 must be memory unless it is xchg (0x86). */
4082 if (i
.prefix
[LOCK_PREFIX
]
4083 && (!i
.tm
.opcode_modifier
.islockable
4084 || i
.mem_operands
== 0
4085 || (i
.tm
.base_opcode
!= 0x86
4086 && !operand_type_check (i
.types
[i
.operands
- 1], anymem
))))
4088 as_bad (_("expecting lockable instruction after `lock'"));
4092 /* Check if HLE prefix is OK. */
4093 if (i
.hle_prefix
&& !check_hle ())
4096 /* Check BND prefix. */
4097 if (i
.bnd_prefix
&& !i
.tm
.opcode_modifier
.bndprefixok
)
4098 as_bad (_("expecting valid branch instruction after `bnd'"));
4100 /* Check NOTRACK prefix. */
4101 if (i
.notrack_prefix
&& !i
.tm
.opcode_modifier
.notrackprefixok
)
4102 as_bad (_("expecting indirect branch instruction after `notrack'"));
4104 if (i
.tm
.cpu_flags
.bitfield
.cpumpx
)
4106 if (flag_code
== CODE_64BIT
&& i
.prefix
[ADDR_PREFIX
])
4107 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
4108 else if (flag_code
!= CODE_16BIT
4109 ? i
.prefix
[ADDR_PREFIX
]
4110 : i
.mem_operands
&& !i
.prefix
[ADDR_PREFIX
])
4111 as_bad (_("16-bit address isn't allowed in MPX instructions"));
4114 /* Insert BND prefix. */
4115 if (add_bnd_prefix
&& i
.tm
.opcode_modifier
.bndprefixok
)
4117 if (!i
.prefix
[BND_PREFIX
])
4118 add_prefix (BND_PREFIX_OPCODE
);
4119 else if (i
.prefix
[BND_PREFIX
] != BND_PREFIX_OPCODE
)
4121 as_warn (_("replacing `rep'/`repe' prefix by `bnd'"));
4122 i
.prefix
[BND_PREFIX
] = BND_PREFIX_OPCODE
;
4126 /* Check string instruction segment overrides. */
4127 if (i
.tm
.opcode_modifier
.isstring
&& i
.mem_operands
!= 0)
4129 if (!check_string ())
4131 i
.disp_operands
= 0;
4134 if (optimize
&& !i
.no_optimize
&& i
.tm
.opcode_modifier
.optimize
)
4135 optimize_encoding ();
4137 if (!process_suffix ())
4140 /* Update operand types. */
4141 for (j
= 0; j
< i
.operands
; j
++)
4142 i
.types
[j
] = operand_type_and (i
.types
[j
], i
.tm
.operand_types
[j
]);
4144 /* Make still unresolved immediate matches conform to size of immediate
4145 given in i.suffix. */
4146 if (!finalize_imm ())
4149 if (i
.types
[0].bitfield
.imm1
)
4150 i
.imm_operands
= 0; /* kludge for shift insns. */
4152 /* We only need to check those implicit registers for instructions
4153 with 3 operands or less. */
4154 if (i
.operands
<= 3)
4155 for (j
= 0; j
< i
.operands
; j
++)
4156 if (i
.types
[j
].bitfield
.inoutportreg
4157 || i
.types
[j
].bitfield
.shiftcount
4158 || (i
.types
[j
].bitfield
.acc
&& !i
.types
[j
].bitfield
.xmmword
))
4161 /* ImmExt should be processed after SSE2AVX. */
4162 if (!i
.tm
.opcode_modifier
.sse2avx
4163 && i
.tm
.opcode_modifier
.immext
)
4166 /* For insns with operands there are more diddles to do to the opcode. */
4169 if (!process_operands ())
4172 else if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
4174 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
4175 as_warn (_("translating to `%sp'"), i
.tm
.name
);
4178 if (i
.tm
.opcode_modifier
.vex
|| i
.tm
.opcode_modifier
.vexopcode
4179 || is_evex_encoding (&i
.tm
))
4181 if (flag_code
== CODE_16BIT
)
4183 as_bad (_("instruction `%s' isn't supported in 16-bit mode."),
4188 if (i
.tm
.opcode_modifier
.vex
)
4189 build_vex_prefix (t
);
4191 build_evex_prefix ();
4194 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
4195 instructions may define INT_OPCODE as well, so avoid this corner
4196 case for those instructions that use MODRM. */
4197 if (i
.tm
.base_opcode
== INT_OPCODE
4198 && !i
.tm
.opcode_modifier
.modrm
4199 && i
.op
[0].imms
->X_add_number
== 3)
4201 i
.tm
.base_opcode
= INT3_OPCODE
;
4205 if ((i
.tm
.opcode_modifier
.jump
4206 || i
.tm
.opcode_modifier
.jumpbyte
4207 || i
.tm
.opcode_modifier
.jumpdword
)
4208 && i
.op
[0].disps
->X_op
== O_constant
)
4210 /* Convert "jmp constant" (and "call constant") to a jump (call) to
4211 the absolute address given by the constant. Since ix86 jumps and
4212 calls are pc relative, we need to generate a reloc. */
4213 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
4214 i
.op
[0].disps
->X_op
= O_symbol
;
4217 if (i
.tm
.opcode_modifier
.rex64
)
4220 /* For 8 bit registers we need an empty rex prefix. Also if the
4221 instruction already has a prefix, we need to convert old
4222 registers to new ones. */
4224 if ((i
.types
[0].bitfield
.reg
&& i
.types
[0].bitfield
.byte
4225 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
4226 || (i
.types
[1].bitfield
.reg
&& i
.types
[1].bitfield
.byte
4227 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
4228 || (((i
.types
[0].bitfield
.reg
&& i
.types
[0].bitfield
.byte
)
4229 || (i
.types
[1].bitfield
.reg
&& i
.types
[1].bitfield
.byte
))
4234 i
.rex
|= REX_OPCODE
;
4235 for (x
= 0; x
< 2; x
++)
4237 /* Look for 8 bit operand that uses old registers. */
4238 if (i
.types
[x
].bitfield
.reg
&& i
.types
[x
].bitfield
.byte
4239 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
4241 /* In case it is "hi" register, give up. */
4242 if (i
.op
[x
].regs
->reg_num
> 3)
4243 as_bad (_("can't encode register '%s%s' in an "
4244 "instruction requiring REX prefix."),
4245 register_prefix
, i
.op
[x
].regs
->reg_name
);
4247 /* Otherwise it is equivalent to the extended register.
4248 Since the encoding doesn't change this is merely
4249 cosmetic cleanup for debug output. */
4251 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
4256 if (i
.rex
== 0 && i
.rex_encoding
)
4258 /* Check if we can add a REX_OPCODE byte. Look for 8 bit operand
4259 that uses legacy register. If it is "hi" register, don't add
4260 the REX_OPCODE byte. */
4262 for (x
= 0; x
< 2; x
++)
4263 if (i
.types
[x
].bitfield
.reg
4264 && i
.types
[x
].bitfield
.byte
4265 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0
4266 && i
.op
[x
].regs
->reg_num
> 3)
4268 i
.rex_encoding
= FALSE
;
4277 add_prefix (REX_OPCODE
| i
.rex
);
4279 /* We are ready to output the insn. */
4284 parse_insn (char *line
, char *mnemonic
)
4287 char *token_start
= l
;
4290 const insn_template
*t
;
4296 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
4301 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
4303 as_bad (_("no such instruction: `%s'"), token_start
);
4308 if (!is_space_char (*l
)
4309 && *l
!= END_OF_INSN
4311 || (*l
!= PREFIX_SEPARATOR
4314 as_bad (_("invalid character %s in mnemonic"),
4315 output_invalid (*l
));
4318 if (token_start
== l
)
4320 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
4321 as_bad (_("expecting prefix; got nothing"));
4323 as_bad (_("expecting mnemonic; got nothing"));
4327 /* Look up instruction (or prefix) via hash table. */
4328 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
4330 if (*l
!= END_OF_INSN
4331 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
4332 && current_templates
4333 && current_templates
->start
->opcode_modifier
.isprefix
)
4335 if (!cpu_flags_check_cpu64 (current_templates
->start
->cpu_flags
))
4337 as_bad ((flag_code
!= CODE_64BIT
4338 ? _("`%s' is only supported in 64-bit mode")
4339 : _("`%s' is not supported in 64-bit mode")),
4340 current_templates
->start
->name
);
4343 /* If we are in 16-bit mode, do not allow addr16 or data16.
4344 Similarly, in 32-bit mode, do not allow addr32 or data32. */
4345 if ((current_templates
->start
->opcode_modifier
.size16
4346 || current_templates
->start
->opcode_modifier
.size32
)
4347 && flag_code
!= CODE_64BIT
4348 && (current_templates
->start
->opcode_modifier
.size32
4349 ^ (flag_code
== CODE_16BIT
)))
4351 as_bad (_("redundant %s prefix"),
4352 current_templates
->start
->name
);
4355 if (current_templates
->start
->opcode_length
== 0)
4357 /* Handle pseudo prefixes. */
4358 switch (current_templates
->start
->base_opcode
)
4362 i
.disp_encoding
= disp_encoding_8bit
;
4366 i
.disp_encoding
= disp_encoding_32bit
;
4370 i
.dir_encoding
= dir_encoding_load
;
4374 i
.dir_encoding
= dir_encoding_store
;
4378 i
.vec_encoding
= vex_encoding_vex2
;
4382 i
.vec_encoding
= vex_encoding_vex3
;
4386 i
.vec_encoding
= vex_encoding_evex
;
4390 i
.rex_encoding
= TRUE
;
4394 i
.no_optimize
= TRUE
;
4402 /* Add prefix, checking for repeated prefixes. */
4403 switch (add_prefix (current_templates
->start
->base_opcode
))
4408 if (current_templates
->start
->cpu_flags
.bitfield
.cpuibt
)
4409 i
.notrack_prefix
= current_templates
->start
->name
;
4412 if (current_templates
->start
->cpu_flags
.bitfield
.cpuhle
)
4413 i
.hle_prefix
= current_templates
->start
->name
;
4414 else if (current_templates
->start
->cpu_flags
.bitfield
.cpumpx
)
4415 i
.bnd_prefix
= current_templates
->start
->name
;
4417 i
.rep_prefix
= current_templates
->start
->name
;
4423 /* Skip past PREFIX_SEPARATOR and reset token_start. */
4430 if (!current_templates
)
4432 /* Check if we should swap operand or force 32bit displacement in
4434 if (mnem_p
- 2 == dot_p
&& dot_p
[1] == 's')
4435 i
.dir_encoding
= dir_encoding_store
;
4436 else if (mnem_p
- 3 == dot_p
4439 i
.disp_encoding
= disp_encoding_8bit
;
4440 else if (mnem_p
- 4 == dot_p
4444 i
.disp_encoding
= disp_encoding_32bit
;
4449 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
4452 if (!current_templates
)
4455 /* See if we can get a match by trimming off a suffix. */
4458 case WORD_MNEM_SUFFIX
:
4459 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
4460 i
.suffix
= SHORT_MNEM_SUFFIX
;
4463 case BYTE_MNEM_SUFFIX
:
4464 case QWORD_MNEM_SUFFIX
:
4465 i
.suffix
= mnem_p
[-1];
4467 current_templates
= (const templates
*) hash_find (op_hash
,
4470 case SHORT_MNEM_SUFFIX
:
4471 case LONG_MNEM_SUFFIX
:
4474 i
.suffix
= mnem_p
[-1];
4476 current_templates
= (const templates
*) hash_find (op_hash
,
4485 if (intel_float_operand (mnemonic
) == 1)
4486 i
.suffix
= SHORT_MNEM_SUFFIX
;
4488 i
.suffix
= LONG_MNEM_SUFFIX
;
4490 current_templates
= (const templates
*) hash_find (op_hash
,
4495 if (!current_templates
)
4497 as_bad (_("no such instruction: `%s'"), token_start
);
4502 if (current_templates
->start
->opcode_modifier
.jump
4503 || current_templates
->start
->opcode_modifier
.jumpbyte
)
4505 /* Check for a branch hint. We allow ",pt" and ",pn" for
4506 predict taken and predict not taken respectively.
4507 I'm not sure that branch hints actually do anything on loop
4508 and jcxz insns (JumpByte) for current Pentium4 chips. They
4509 may work in the future and it doesn't hurt to accept them
4511 if (l
[0] == ',' && l
[1] == 'p')
4515 if (!add_prefix (DS_PREFIX_OPCODE
))
4519 else if (l
[2] == 'n')
4521 if (!add_prefix (CS_PREFIX_OPCODE
))
4527 /* Any other comma loses. */
4530 as_bad (_("invalid character %s in mnemonic"),
4531 output_invalid (*l
));
4535 /* Check if instruction is supported on specified architecture. */
4537 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
4539 supported
|= cpu_flags_match (t
);
4540 if (supported
== CPU_FLAGS_PERFECT_MATCH
)
4542 if (!cpu_arch_flags
.bitfield
.cpui386
&& (flag_code
!= CODE_16BIT
))
4543 as_warn (_("use .code16 to ensure correct addressing mode"));
4549 if (!(supported
& CPU_FLAGS_64BIT_MATCH
))
4550 as_bad (flag_code
== CODE_64BIT
4551 ? _("`%s' is not supported in 64-bit mode")
4552 : _("`%s' is only supported in 64-bit mode"),
4553 current_templates
->start
->name
);
4555 as_bad (_("`%s' is not supported on `%s%s'"),
4556 current_templates
->start
->name
,
4557 cpu_arch_name
? cpu_arch_name
: default_arch
,
4558 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
4564 parse_operands (char *l
, const char *mnemonic
)
4568 /* 1 if operand is pending after ','. */
4569 unsigned int expecting_operand
= 0;
4571 /* Non-zero if operand parens not balanced. */
4572 unsigned int paren_not_balanced
;
4574 while (*l
!= END_OF_INSN
)
4576 /* Skip optional white space before operand. */
4577 if (is_space_char (*l
))
4579 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
&& *l
!= '"')
4581 as_bad (_("invalid character %s before operand %d"),
4582 output_invalid (*l
),
4586 token_start
= l
; /* After white space. */
4587 paren_not_balanced
= 0;
4588 while (paren_not_balanced
|| *l
!= ',')
4590 if (*l
== END_OF_INSN
)
4592 if (paren_not_balanced
)
4595 as_bad (_("unbalanced parenthesis in operand %d."),
4598 as_bad (_("unbalanced brackets in operand %d."),
4603 break; /* we are done */
4605 else if (!is_operand_char (*l
) && !is_space_char (*l
) && *l
!= '"')
4607 as_bad (_("invalid character %s in operand %d"),
4608 output_invalid (*l
),
4615 ++paren_not_balanced
;
4617 --paren_not_balanced
;
4622 ++paren_not_balanced
;
4624 --paren_not_balanced
;
4628 if (l
!= token_start
)
4629 { /* Yes, we've read in another operand. */
4630 unsigned int operand_ok
;
4631 this_operand
= i
.operands
++;
4632 if (i
.operands
> MAX_OPERANDS
)
4634 as_bad (_("spurious operands; (%d operands/instruction max)"),
4638 i
.types
[this_operand
].bitfield
.unspecified
= 1;
4639 /* Now parse operand adding info to 'i' as we go along. */
4640 END_STRING_AND_SAVE (l
);
4644 i386_intel_operand (token_start
,
4645 intel_float_operand (mnemonic
));
4647 operand_ok
= i386_att_operand (token_start
);
4649 RESTORE_END_STRING (l
);
4655 if (expecting_operand
)
4657 expecting_operand_after_comma
:
4658 as_bad (_("expecting operand after ','; got nothing"));
4663 as_bad (_("expecting operand before ','; got nothing"));
4668 /* Now *l must be either ',' or END_OF_INSN. */
4671 if (*++l
== END_OF_INSN
)
4673 /* Just skip it, if it's \n complain. */
4674 goto expecting_operand_after_comma
;
4676 expecting_operand
= 1;
4683 swap_2_operands (int xchg1
, int xchg2
)
4685 union i386_op temp_op
;
4686 i386_operand_type temp_type
;
4687 enum bfd_reloc_code_real temp_reloc
;
4689 temp_type
= i
.types
[xchg2
];
4690 i
.types
[xchg2
] = i
.types
[xchg1
];
4691 i
.types
[xchg1
] = temp_type
;
4692 temp_op
= i
.op
[xchg2
];
4693 i
.op
[xchg2
] = i
.op
[xchg1
];
4694 i
.op
[xchg1
] = temp_op
;
4695 temp_reloc
= i
.reloc
[xchg2
];
4696 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
4697 i
.reloc
[xchg1
] = temp_reloc
;
4701 if (i
.mask
->operand
== xchg1
)
4702 i
.mask
->operand
= xchg2
;
4703 else if (i
.mask
->operand
== xchg2
)
4704 i
.mask
->operand
= xchg1
;
4708 if (i
.broadcast
->operand
== xchg1
)
4709 i
.broadcast
->operand
= xchg2
;
4710 else if (i
.broadcast
->operand
== xchg2
)
4711 i
.broadcast
->operand
= xchg1
;
4715 if (i
.rounding
->operand
== xchg1
)
4716 i
.rounding
->operand
= xchg2
;
4717 else if (i
.rounding
->operand
== xchg2
)
4718 i
.rounding
->operand
= xchg1
;
4723 swap_operands (void)
4729 swap_2_operands (1, i
.operands
- 2);
4733 swap_2_operands (0, i
.operands
- 1);
4739 if (i
.mem_operands
== 2)
4741 const seg_entry
*temp_seg
;
4742 temp_seg
= i
.seg
[0];
4743 i
.seg
[0] = i
.seg
[1];
4744 i
.seg
[1] = temp_seg
;
4748 /* Try to ensure constant immediates are represented in the smallest
4753 char guess_suffix
= 0;
4757 guess_suffix
= i
.suffix
;
4758 else if (i
.reg_operands
)
4760 /* Figure out a suffix from the last register operand specified.
4761 We can't do this properly yet, ie. excluding InOutPortReg,
4762 but the following works for instructions with immediates.
4763 In any case, we can't set i.suffix yet. */
4764 for (op
= i
.operands
; --op
>= 0;)
4765 if (i
.types
[op
].bitfield
.reg
&& i
.types
[op
].bitfield
.byte
)
4767 guess_suffix
= BYTE_MNEM_SUFFIX
;
4770 else if (i
.types
[op
].bitfield
.reg
&& i
.types
[op
].bitfield
.word
)
4772 guess_suffix
= WORD_MNEM_SUFFIX
;
4775 else if (i
.types
[op
].bitfield
.reg
&& i
.types
[op
].bitfield
.dword
)
4777 guess_suffix
= LONG_MNEM_SUFFIX
;
4780 else if (i
.types
[op
].bitfield
.reg
&& i
.types
[op
].bitfield
.qword
)
4782 guess_suffix
= QWORD_MNEM_SUFFIX
;
4786 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
4787 guess_suffix
= WORD_MNEM_SUFFIX
;
4789 for (op
= i
.operands
; --op
>= 0;)
4790 if (operand_type_check (i
.types
[op
], imm
))
4792 switch (i
.op
[op
].imms
->X_op
)
4795 /* If a suffix is given, this operand may be shortened. */
4796 switch (guess_suffix
)
4798 case LONG_MNEM_SUFFIX
:
4799 i
.types
[op
].bitfield
.imm32
= 1;
4800 i
.types
[op
].bitfield
.imm64
= 1;
4802 case WORD_MNEM_SUFFIX
:
4803 i
.types
[op
].bitfield
.imm16
= 1;
4804 i
.types
[op
].bitfield
.imm32
= 1;
4805 i
.types
[op
].bitfield
.imm32s
= 1;
4806 i
.types
[op
].bitfield
.imm64
= 1;
4808 case BYTE_MNEM_SUFFIX
:
4809 i
.types
[op
].bitfield
.imm8
= 1;
4810 i
.types
[op
].bitfield
.imm8s
= 1;
4811 i
.types
[op
].bitfield
.imm16
= 1;
4812 i
.types
[op
].bitfield
.imm32
= 1;
4813 i
.types
[op
].bitfield
.imm32s
= 1;
4814 i
.types
[op
].bitfield
.imm64
= 1;
4818 /* If this operand is at most 16 bits, convert it
4819 to a signed 16 bit number before trying to see
4820 whether it will fit in an even smaller size.
4821 This allows a 16-bit operand such as $0xffe0 to
4822 be recognised as within Imm8S range. */
4823 if ((i
.types
[op
].bitfield
.imm16
)
4824 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
4826 i
.op
[op
].imms
->X_add_number
=
4827 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
4830 /* Store 32-bit immediate in 64-bit for 64-bit BFD. */
4831 if ((i
.types
[op
].bitfield
.imm32
)
4832 && ((i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1))
4835 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
4836 ^ ((offsetT
) 1 << 31))
4837 - ((offsetT
) 1 << 31));
4841 = operand_type_or (i
.types
[op
],
4842 smallest_imm_type (i
.op
[op
].imms
->X_add_number
));
4844 /* We must avoid matching of Imm32 templates when 64bit
4845 only immediate is available. */
4846 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
4847 i
.types
[op
].bitfield
.imm32
= 0;
4854 /* Symbols and expressions. */
4856 /* Convert symbolic operand to proper sizes for matching, but don't
4857 prevent matching a set of insns that only supports sizes other
4858 than those matching the insn suffix. */
4860 i386_operand_type mask
, allowed
;
4861 const insn_template
*t
;
4863 operand_type_set (&mask
, 0);
4864 operand_type_set (&allowed
, 0);
4866 for (t
= current_templates
->start
;
4867 t
< current_templates
->end
;
4869 allowed
= operand_type_or (allowed
,
4870 t
->operand_types
[op
]);
4871 switch (guess_suffix
)
4873 case QWORD_MNEM_SUFFIX
:
4874 mask
.bitfield
.imm64
= 1;
4875 mask
.bitfield
.imm32s
= 1;
4877 case LONG_MNEM_SUFFIX
:
4878 mask
.bitfield
.imm32
= 1;
4880 case WORD_MNEM_SUFFIX
:
4881 mask
.bitfield
.imm16
= 1;
4883 case BYTE_MNEM_SUFFIX
:
4884 mask
.bitfield
.imm8
= 1;
4889 allowed
= operand_type_and (mask
, allowed
);
4890 if (!operand_type_all_zero (&allowed
))
4891 i
.types
[op
] = operand_type_and (i
.types
[op
], mask
);
4898 /* Try to use the smallest displacement type too. */
4900 optimize_disp (void)
4904 for (op
= i
.operands
; --op
>= 0;)
4905 if (operand_type_check (i
.types
[op
], disp
))
4907 if (i
.op
[op
].disps
->X_op
== O_constant
)
4909 offsetT op_disp
= i
.op
[op
].disps
->X_add_number
;
4911 if (i
.types
[op
].bitfield
.disp16
4912 && (op_disp
& ~(offsetT
) 0xffff) == 0)
4914 /* If this operand is at most 16 bits, convert
4915 to a signed 16 bit number and don't use 64bit
4917 op_disp
= (((op_disp
& 0xffff) ^ 0x8000) - 0x8000);
4918 i
.types
[op
].bitfield
.disp64
= 0;
4921 /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */
4922 if (i
.types
[op
].bitfield
.disp32
4923 && (op_disp
& ~(((offsetT
) 2 << 31) - 1)) == 0)
4925 /* If this operand is at most 32 bits, convert
4926 to a signed 32 bit number and don't use 64bit
4928 op_disp
&= (((offsetT
) 2 << 31) - 1);
4929 op_disp
= (op_disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
4930 i
.types
[op
].bitfield
.disp64
= 0;
4933 if (!op_disp
&& i
.types
[op
].bitfield
.baseindex
)
4935 i
.types
[op
].bitfield
.disp8
= 0;
4936 i
.types
[op
].bitfield
.disp16
= 0;
4937 i
.types
[op
].bitfield
.disp32
= 0;
4938 i
.types
[op
].bitfield
.disp32s
= 0;
4939 i
.types
[op
].bitfield
.disp64
= 0;
4943 else if (flag_code
== CODE_64BIT
)
4945 if (fits_in_signed_long (op_disp
))
4947 i
.types
[op
].bitfield
.disp64
= 0;
4948 i
.types
[op
].bitfield
.disp32s
= 1;
4950 if (i
.prefix
[ADDR_PREFIX
]
4951 && fits_in_unsigned_long (op_disp
))
4952 i
.types
[op
].bitfield
.disp32
= 1;
4954 if ((i
.types
[op
].bitfield
.disp32
4955 || i
.types
[op
].bitfield
.disp32s
4956 || i
.types
[op
].bitfield
.disp16
)
4957 && fits_in_disp8 (op_disp
))
4958 i
.types
[op
].bitfield
.disp8
= 1;
4960 else if (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
4961 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
)
4963 fix_new_exp (frag_now
, frag_more (0) - frag_now
->fr_literal
, 0,
4964 i
.op
[op
].disps
, 0, i
.reloc
[op
]);
4965 i
.types
[op
].bitfield
.disp8
= 0;
4966 i
.types
[op
].bitfield
.disp16
= 0;
4967 i
.types
[op
].bitfield
.disp32
= 0;
4968 i
.types
[op
].bitfield
.disp32s
= 0;
4969 i
.types
[op
].bitfield
.disp64
= 0;
4972 /* We only support 64bit displacement on constants. */
4973 i
.types
[op
].bitfield
.disp64
= 0;
4977 /* Check if operands are valid for the instruction. */
4980 check_VecOperands (const insn_template
*t
)
4984 static const i386_cpu_flags avx512
= CPU_ANY_AVX512F_FLAGS
;
4986 /* Templates allowing for ZMMword as well as YMMword and/or XMMword for
4987 any one operand are implicity requiring AVX512VL support if the actual
4988 operand size is YMMword or XMMword. Since this function runs after
4989 template matching, there's no need to check for YMMword/XMMword in
4991 cpu
= cpu_flags_and (t
->cpu_flags
, avx512
);
4992 if (!cpu_flags_all_zero (&cpu
)
4993 && !t
->cpu_flags
.bitfield
.cpuavx512vl
4994 && !cpu_arch_flags
.bitfield
.cpuavx512vl
)
4996 for (op
= 0; op
< t
->operands
; ++op
)
4998 if (t
->operand_types
[op
].bitfield
.zmmword
4999 && (i
.types
[op
].bitfield
.ymmword
5000 || i
.types
[op
].bitfield
.xmmword
))
5002 i
.error
= unsupported
;
5008 /* Without VSIB byte, we can't have a vector register for index. */
5009 if (!t
->opcode_modifier
.vecsib
5011 && (i
.index_reg
->reg_type
.bitfield
.xmmword
5012 || i
.index_reg
->reg_type
.bitfield
.ymmword
5013 || i
.index_reg
->reg_type
.bitfield
.zmmword
))
5015 i
.error
= unsupported_vector_index_register
;
5019 /* Check if default mask is allowed. */
5020 if (t
->opcode_modifier
.nodefmask
5021 && (!i
.mask
|| i
.mask
->mask
->reg_num
== 0))
5023 i
.error
= no_default_mask
;
5027 /* For VSIB byte, we need a vector register for index, and all vector
5028 registers must be distinct. */
5029 if (t
->opcode_modifier
.vecsib
)
5032 || !((t
->opcode_modifier
.vecsib
== VecSIB128
5033 && i
.index_reg
->reg_type
.bitfield
.xmmword
)
5034 || (t
->opcode_modifier
.vecsib
== VecSIB256
5035 && i
.index_reg
->reg_type
.bitfield
.ymmword
)
5036 || (t
->opcode_modifier
.vecsib
== VecSIB512
5037 && i
.index_reg
->reg_type
.bitfield
.zmmword
)))
5039 i
.error
= invalid_vsib_address
;
5043 gas_assert (i
.reg_operands
== 2 || i
.mask
);
5044 if (i
.reg_operands
== 2 && !i
.mask
)
5046 gas_assert (i
.types
[0].bitfield
.regsimd
);
5047 gas_assert (i
.types
[0].bitfield
.xmmword
5048 || i
.types
[0].bitfield
.ymmword
);
5049 gas_assert (i
.types
[2].bitfield
.regsimd
);
5050 gas_assert (i
.types
[2].bitfield
.xmmword
5051 || i
.types
[2].bitfield
.ymmword
);
5052 if (operand_check
== check_none
)
5054 if (register_number (i
.op
[0].regs
)
5055 != register_number (i
.index_reg
)
5056 && register_number (i
.op
[2].regs
)
5057 != register_number (i
.index_reg
)
5058 && register_number (i
.op
[0].regs
)
5059 != register_number (i
.op
[2].regs
))
5061 if (operand_check
== check_error
)
5063 i
.error
= invalid_vector_register_set
;
5066 as_warn (_("mask, index, and destination registers should be distinct"));
5068 else if (i
.reg_operands
== 1 && i
.mask
)
5070 if (i
.types
[1].bitfield
.regsimd
5071 && (i
.types
[1].bitfield
.xmmword
5072 || i
.types
[1].bitfield
.ymmword
5073 || i
.types
[1].bitfield
.zmmword
)
5074 && (register_number (i
.op
[1].regs
)
5075 == register_number (i
.index_reg
)))
5077 if (operand_check
== check_error
)
5079 i
.error
= invalid_vector_register_set
;
5082 if (operand_check
!= check_none
)
5083 as_warn (_("index and destination registers should be distinct"));
5088 /* Check if broadcast is supported by the instruction and is applied
5089 to the memory operand. */
5092 i386_operand_type type
, overlap
;
5094 /* Check if specified broadcast is supported in this instruction,
5095 and it's applied to memory operand of DWORD or QWORD type. */
5096 op
= i
.broadcast
->operand
;
5097 if (!t
->opcode_modifier
.broadcast
5098 || !i
.types
[op
].bitfield
.mem
5099 || (!i
.types
[op
].bitfield
.unspecified
5100 && (t
->operand_types
[op
].bitfield
.dword
5101 ? !i
.types
[op
].bitfield
.dword
5102 : !i
.types
[op
].bitfield
.qword
)))
5105 i
.error
= unsupported_broadcast
;
5109 operand_type_set (&type
, 0);
5110 switch ((t
->operand_types
[op
].bitfield
.dword
? 4 : 8) * i
.broadcast
->type
)
5113 type
.bitfield
.qword
= 1;
5116 type
.bitfield
.xmmword
= 1;
5119 type
.bitfield
.ymmword
= 1;
5122 type
.bitfield
.zmmword
= 1;
5128 overlap
= operand_type_and (type
, t
->operand_types
[op
]);
5129 if (operand_type_all_zero (&overlap
))
5132 if (t
->opcode_modifier
.checkregsize
)
5136 type
.bitfield
.baseindex
= 1;
5137 for (j
= 0; j
< i
.operands
; ++j
)
5140 && !operand_type_register_match(i
.types
[j
],
5141 t
->operand_types
[j
],
5143 t
->operand_types
[op
]))
5148 /* If broadcast is supported in this instruction, we need to check if
5149 operand of one-element size isn't specified without broadcast. */
5150 else if (t
->opcode_modifier
.broadcast
&& i
.mem_operands
)
5152 /* Find memory operand. */
5153 for (op
= 0; op
< i
.operands
; op
++)
5154 if (operand_type_check (i
.types
[op
], anymem
))
5156 gas_assert (op
< i
.operands
);
5157 /* Check size of the memory operand. */
5158 if (t
->operand_types
[op
].bitfield
.dword
5159 ? i
.types
[op
].bitfield
.dword
5160 : i
.types
[op
].bitfield
.qword
)
5162 i
.error
= broadcast_needed
;
5167 op
= MAX_OPERANDS
- 1; /* Avoid uninitialized variable warning. */
5169 /* Check if requested masking is supported. */
5171 && (!t
->opcode_modifier
.masking
5173 && t
->opcode_modifier
.masking
== MERGING_MASKING
)))
5175 i
.error
= unsupported_masking
;
5179 /* Check if masking is applied to dest operand. */
5180 if (i
.mask
&& (i
.mask
->operand
!= (int) (i
.operands
- 1)))
5182 i
.error
= mask_not_on_destination
;
5189 if ((i
.rounding
->type
!= saeonly
5190 && !t
->opcode_modifier
.staticrounding
)
5191 || (i
.rounding
->type
== saeonly
5192 && (t
->opcode_modifier
.staticrounding
5193 || !t
->opcode_modifier
.sae
)))
5195 i
.error
= unsupported_rc_sae
;
5198 /* If the instruction has several immediate operands and one of
5199 them is rounding, the rounding operand should be the last
5200 immediate operand. */
5201 if (i
.imm_operands
> 1
5202 && i
.rounding
->operand
!= (int) (i
.imm_operands
- 1))
5204 i
.error
= rc_sae_operand_not_last_imm
;
5209 /* Check vector Disp8 operand. */
5210 if (t
->opcode_modifier
.disp8memshift
5211 && i
.disp_encoding
!= disp_encoding_32bit
)
5214 i
.memshift
= t
->operand_types
[op
].bitfield
.dword
? 2 : 3;
5215 else if (t
->opcode_modifier
.disp8memshift
!= DISP8_SHIFT_VL
)
5216 i
.memshift
= t
->opcode_modifier
.disp8memshift
;
5219 const i386_operand_type
*type
= NULL
;
5222 for (op
= 0; op
< i
.operands
; op
++)
5223 if (operand_type_check (i
.types
[op
], anymem
))
5225 if (t
->operand_types
[op
].bitfield
.xmmword
5226 + t
->operand_types
[op
].bitfield
.ymmword
5227 + t
->operand_types
[op
].bitfield
.zmmword
<= 1)
5228 type
= &t
->operand_types
[op
];
5229 else if (!i
.types
[op
].bitfield
.unspecified
)
5230 type
= &i
.types
[op
];
5232 else if (i
.types
[op
].bitfield
.regsimd
)
5234 if (i
.types
[op
].bitfield
.zmmword
)
5236 else if (i
.types
[op
].bitfield
.ymmword
&& i
.memshift
< 5)
5238 else if (i
.types
[op
].bitfield
.xmmword
&& i
.memshift
< 4)
5244 if (type
->bitfield
.zmmword
)
5246 else if (type
->bitfield
.ymmword
)
5248 else if (type
->bitfield
.xmmword
)
5252 /* For the check in fits_in_disp8(). */
5253 if (i
.memshift
== 0)
5257 for (op
= 0; op
< i
.operands
; op
++)
5258 if (operand_type_check (i
.types
[op
], disp
)
5259 && i
.op
[op
].disps
->X_op
== O_constant
)
5261 if (fits_in_disp8 (i
.op
[op
].disps
->X_add_number
))
5263 i
.types
[op
].bitfield
.disp8
= 1;
5266 i
.types
[op
].bitfield
.disp8
= 0;
5275 /* Check if operands are valid for the instruction. Update VEX
5279 VEX_check_operands (const insn_template
*t
)
5281 if (i
.vec_encoding
== vex_encoding_evex
)
5283 /* This instruction must be encoded with EVEX prefix. */
5284 if (!is_evex_encoding (t
))
5286 i
.error
= unsupported
;
5292 if (!t
->opcode_modifier
.vex
)
5294 /* This instruction template doesn't have VEX prefix. */
5295 if (i
.vec_encoding
!= vex_encoding_default
)
5297 i
.error
= unsupported
;
5303 /* Only check VEX_Imm4, which must be the first operand. */
5304 if (t
->operand_types
[0].bitfield
.vec_imm4
)
5306 if (i
.op
[0].imms
->X_op
!= O_constant
5307 || !fits_in_imm4 (i
.op
[0].imms
->X_add_number
))
5313 /* Turn off Imm8 so that update_imm won't complain. */
5314 i
.types
[0] = vec_imm4
;
5320 static const insn_template
*
5321 match_template (char mnem_suffix
)
5323 /* Points to template once we've found it. */
5324 const insn_template
*t
;
5325 i386_operand_type overlap0
, overlap1
, overlap2
, overlap3
;
5326 i386_operand_type overlap4
;
5327 unsigned int found_reverse_match
;
5328 i386_opcode_modifier suffix_check
, mnemsuf_check
;
5329 i386_operand_type operand_types
[MAX_OPERANDS
];
5330 int addr_prefix_disp
;
5332 unsigned int found_cpu_match
, size_match
;
5333 unsigned int check_register
;
5334 enum i386_error specific_error
= 0;
5336 #if MAX_OPERANDS != 5
5337 # error "MAX_OPERANDS must be 5."
5340 found_reverse_match
= 0;
5341 addr_prefix_disp
= -1;
5343 memset (&suffix_check
, 0, sizeof (suffix_check
));
5344 if (intel_syntax
&& i
.broadcast
)
5346 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
5347 suffix_check
.no_bsuf
= 1;
5348 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
5349 suffix_check
.no_wsuf
= 1;
5350 else if (i
.suffix
== SHORT_MNEM_SUFFIX
)
5351 suffix_check
.no_ssuf
= 1;
5352 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
5353 suffix_check
.no_lsuf
= 1;
5354 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
5355 suffix_check
.no_qsuf
= 1;
5356 else if (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
)
5357 suffix_check
.no_ldsuf
= 1;
5359 memset (&mnemsuf_check
, 0, sizeof (mnemsuf_check
));
5362 switch (mnem_suffix
)
5364 case BYTE_MNEM_SUFFIX
: mnemsuf_check
.no_bsuf
= 1; break;
5365 case WORD_MNEM_SUFFIX
: mnemsuf_check
.no_wsuf
= 1; break;
5366 case SHORT_MNEM_SUFFIX
: mnemsuf_check
.no_ssuf
= 1; break;
5367 case LONG_MNEM_SUFFIX
: mnemsuf_check
.no_lsuf
= 1; break;
5368 case QWORD_MNEM_SUFFIX
: mnemsuf_check
.no_qsuf
= 1; break;
5372 /* Must have right number of operands. */
5373 i
.error
= number_of_operands_mismatch
;
5375 for (t
= current_templates
->start
; t
< current_templates
->end
; t
++)
5377 addr_prefix_disp
= -1;
5379 if (i
.operands
!= t
->operands
)
5382 /* Check processor support. */
5383 i
.error
= unsupported
;
5384 found_cpu_match
= (cpu_flags_match (t
)
5385 == CPU_FLAGS_PERFECT_MATCH
);
5386 if (!found_cpu_match
)
5389 /* Check AT&T mnemonic. */
5390 i
.error
= unsupported_with_intel_mnemonic
;
5391 if (intel_mnemonic
&& t
->opcode_modifier
.attmnemonic
)
5394 /* Check AT&T/Intel syntax and Intel64/AMD64 ISA. */
5395 i
.error
= unsupported_syntax
;
5396 if ((intel_syntax
&& t
->opcode_modifier
.attsyntax
)
5397 || (!intel_syntax
&& t
->opcode_modifier
.intelsyntax
)
5398 || (intel64
&& t
->opcode_modifier
.amd64
)
5399 || (!intel64
&& t
->opcode_modifier
.intel64
))
5402 /* Check the suffix, except for some instructions in intel mode. */
5403 i
.error
= invalid_instruction_suffix
;
5404 if ((!intel_syntax
|| !t
->opcode_modifier
.ignoresize
)
5405 && ((t
->opcode_modifier
.no_bsuf
&& suffix_check
.no_bsuf
)
5406 || (t
->opcode_modifier
.no_wsuf
&& suffix_check
.no_wsuf
)
5407 || (t
->opcode_modifier
.no_lsuf
&& suffix_check
.no_lsuf
)
5408 || (t
->opcode_modifier
.no_ssuf
&& suffix_check
.no_ssuf
)
5409 || (t
->opcode_modifier
.no_qsuf
&& suffix_check
.no_qsuf
)
5410 || (t
->opcode_modifier
.no_ldsuf
&& suffix_check
.no_ldsuf
)))
5412 /* In Intel mode all mnemonic suffixes must be explicitly allowed. */
5413 if ((t
->opcode_modifier
.no_bsuf
&& mnemsuf_check
.no_bsuf
)
5414 || (t
->opcode_modifier
.no_wsuf
&& mnemsuf_check
.no_wsuf
)
5415 || (t
->opcode_modifier
.no_lsuf
&& mnemsuf_check
.no_lsuf
)
5416 || (t
->opcode_modifier
.no_ssuf
&& mnemsuf_check
.no_ssuf
)
5417 || (t
->opcode_modifier
.no_qsuf
&& mnemsuf_check
.no_qsuf
)
5418 || (t
->opcode_modifier
.no_ldsuf
&& mnemsuf_check
.no_ldsuf
))
5421 size_match
= operand_size_match (t
);
5425 for (j
= 0; j
< MAX_OPERANDS
; j
++)
5426 operand_types
[j
] = t
->operand_types
[j
];
5428 /* In general, don't allow 64-bit operands in 32-bit mode. */
5429 if (i
.suffix
== QWORD_MNEM_SUFFIX
5430 && flag_code
!= CODE_64BIT
5432 ? (!t
->opcode_modifier
.ignoresize
5433 && !intel_float_operand (t
->name
))
5434 : intel_float_operand (t
->name
) != 2)
5435 && ((!operand_types
[0].bitfield
.regmmx
5436 && !operand_types
[0].bitfield
.regsimd
)
5437 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
5438 && !operand_types
[t
->operands
> 1].bitfield
.regsimd
))
5439 && (t
->base_opcode
!= 0x0fc7
5440 || t
->extension_opcode
!= 1 /* cmpxchg8b */))
5443 /* In general, don't allow 32-bit operands on pre-386. */
5444 else if (i
.suffix
== LONG_MNEM_SUFFIX
5445 && !cpu_arch_flags
.bitfield
.cpui386
5447 ? (!t
->opcode_modifier
.ignoresize
5448 && !intel_float_operand (t
->name
))
5449 : intel_float_operand (t
->name
) != 2)
5450 && ((!operand_types
[0].bitfield
.regmmx
5451 && !operand_types
[0].bitfield
.regsimd
)
5452 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
5453 && !operand_types
[t
->operands
> 1].bitfield
.regsimd
)))
5456 /* Do not verify operands when there are none. */
5460 /* We've found a match; break out of loop. */
5464 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
5465 into Disp32/Disp16/Disp32 operand. */
5466 if (i
.prefix
[ADDR_PREFIX
] != 0)
5468 /* There should be only one Disp operand. */
5472 for (j
= 0; j
< MAX_OPERANDS
; j
++)
5474 if (operand_types
[j
].bitfield
.disp16
)
5476 addr_prefix_disp
= j
;
5477 operand_types
[j
].bitfield
.disp32
= 1;
5478 operand_types
[j
].bitfield
.disp16
= 0;
5484 for (j
= 0; j
< MAX_OPERANDS
; j
++)
5486 if (operand_types
[j
].bitfield
.disp32
)
5488 addr_prefix_disp
= j
;
5489 operand_types
[j
].bitfield
.disp32
= 0;
5490 operand_types
[j
].bitfield
.disp16
= 1;
5496 for (j
= 0; j
< MAX_OPERANDS
; j
++)
5498 if (operand_types
[j
].bitfield
.disp64
)
5500 addr_prefix_disp
= j
;
5501 operand_types
[j
].bitfield
.disp64
= 0;
5502 operand_types
[j
].bitfield
.disp32
= 1;
5510 /* Force 0x8b encoding for "mov foo@GOT, %eax". */
5511 if (i
.reloc
[0] == BFD_RELOC_386_GOT32
&& t
->base_opcode
== 0xa0)
5514 /* We check register size if needed. */
5515 if (t
->opcode_modifier
.checkregsize
)
5517 check_register
= (1 << t
->operands
) - 1;
5519 check_register
&= ~(1 << i
.broadcast
->operand
);
5524 overlap0
= operand_type_and (i
.types
[0], operand_types
[0]);
5525 switch (t
->operands
)
5528 if (!operand_type_match (overlap0
, i
.types
[0]))
5532 /* xchg %eax, %eax is a special case. It is an alias for nop
5533 only in 32bit mode and we can use opcode 0x90. In 64bit
5534 mode, we can't use 0x90 for xchg %eax, %eax since it should
5535 zero-extend %eax to %rax. */
5536 if (flag_code
== CODE_64BIT
5537 && t
->base_opcode
== 0x90
5538 && operand_type_equal (&i
.types
[0], &acc32
)
5539 && operand_type_equal (&i
.types
[1], &acc32
))
5541 /* xrelease mov %eax, <disp> is another special case. It must not
5542 match the accumulator-only encoding of mov. */
5543 if (flag_code
!= CODE_64BIT
5545 && t
->base_opcode
== 0xa0
5546 && i
.types
[0].bitfield
.acc
5547 && operand_type_check (i
.types
[1], anymem
))
5549 if (!(size_match
& MATCH_STRAIGHT
))
5551 /* If we want store form, we reverse direction of operands. */
5552 if (i
.dir_encoding
== dir_encoding_store
5553 && t
->opcode_modifier
.d
)
5558 /* If we want store form, we skip the current load. */
5559 if (i
.dir_encoding
== dir_encoding_store
5560 && i
.mem_operands
== 0
5561 && t
->opcode_modifier
.load
)
5566 overlap1
= operand_type_and (i
.types
[1], operand_types
[1]);
5567 if (!operand_type_match (overlap0
, i
.types
[0])
5568 || !operand_type_match (overlap1
, i
.types
[1])
5569 || ((check_register
& 3) == 3
5570 && !operand_type_register_match (i
.types
[0],
5575 /* Check if other direction is valid ... */
5576 if (!t
->opcode_modifier
.d
)
5580 if (!(size_match
& MATCH_REVERSE
))
5582 /* Try reversing direction of operands. */
5583 overlap0
= operand_type_and (i
.types
[0], operand_types
[1]);
5584 overlap1
= operand_type_and (i
.types
[1], operand_types
[0]);
5585 if (!operand_type_match (overlap0
, i
.types
[0])
5586 || !operand_type_match (overlap1
, i
.types
[1])
5588 && !operand_type_register_match (i
.types
[0],
5593 /* Does not match either direction. */
5596 /* found_reverse_match holds which of D or FloatR
5598 if (!t
->opcode_modifier
.d
)
5599 found_reverse_match
= 0;
5600 else if (operand_types
[0].bitfield
.tbyte
)
5601 found_reverse_match
= Opcode_FloatD
;
5603 found_reverse_match
= Opcode_D
;
5604 if (t
->opcode_modifier
.floatr
)
5605 found_reverse_match
|= Opcode_FloatR
;
5609 /* Found a forward 2 operand match here. */
5610 switch (t
->operands
)
5613 overlap4
= operand_type_and (i
.types
[4],
5617 overlap3
= operand_type_and (i
.types
[3],
5621 overlap2
= operand_type_and (i
.types
[2],
5626 switch (t
->operands
)
5629 if (!operand_type_match (overlap4
, i
.types
[4])
5630 || !operand_type_register_match (i
.types
[3],
5637 if (!operand_type_match (overlap3
, i
.types
[3])
5638 || ((check_register
& 0xa) == 0xa
5639 && !operand_type_register_match (i
.types
[1],
5643 || ((check_register
& 0xc) == 0xc
5644 && !operand_type_register_match (i
.types
[2],
5651 /* Here we make use of the fact that there are no
5652 reverse match 3 operand instructions. */
5653 if (!operand_type_match (overlap2
, i
.types
[2])
5654 || ((check_register
& 5) == 5
5655 && !operand_type_register_match (i
.types
[0],
5659 || ((check_register
& 6) == 6
5660 && !operand_type_register_match (i
.types
[1],
5668 /* Found either forward/reverse 2, 3 or 4 operand match here:
5669 slip through to break. */
5671 if (!found_cpu_match
)
5673 found_reverse_match
= 0;
5677 /* Check if vector and VEX operands are valid. */
5678 if (check_VecOperands (t
) || VEX_check_operands (t
))
5680 specific_error
= i
.error
;
5684 /* We've found a match; break out of loop. */
5688 if (t
== current_templates
->end
)
5690 /* We found no match. */
5691 const char *err_msg
;
5692 switch (specific_error
? specific_error
: i
.error
)
5696 case operand_size_mismatch
:
5697 err_msg
= _("operand size mismatch");
5699 case operand_type_mismatch
:
5700 err_msg
= _("operand type mismatch");
5702 case register_type_mismatch
:
5703 err_msg
= _("register type mismatch");
5705 case number_of_operands_mismatch
:
5706 err_msg
= _("number of operands mismatch");
5708 case invalid_instruction_suffix
:
5709 err_msg
= _("invalid instruction suffix");
5712 err_msg
= _("constant doesn't fit in 4 bits");
5714 case unsupported_with_intel_mnemonic
:
5715 err_msg
= _("unsupported with Intel mnemonic");
5717 case unsupported_syntax
:
5718 err_msg
= _("unsupported syntax");
5721 as_bad (_("unsupported instruction `%s'"),
5722 current_templates
->start
->name
);
5724 case invalid_vsib_address
:
5725 err_msg
= _("invalid VSIB address");
5727 case invalid_vector_register_set
:
5728 err_msg
= _("mask, index, and destination registers must be distinct");
5730 case unsupported_vector_index_register
:
5731 err_msg
= _("unsupported vector index register");
5733 case unsupported_broadcast
:
5734 err_msg
= _("unsupported broadcast");
5736 case broadcast_not_on_src_operand
:
5737 err_msg
= _("broadcast not on source memory operand");
5739 case broadcast_needed
:
5740 err_msg
= _("broadcast is needed for operand of such type");
5742 case unsupported_masking
:
5743 err_msg
= _("unsupported masking");
5745 case mask_not_on_destination
:
5746 err_msg
= _("mask not on destination operand");
5748 case no_default_mask
:
5749 err_msg
= _("default mask isn't allowed");
5751 case unsupported_rc_sae
:
5752 err_msg
= _("unsupported static rounding/sae");
5754 case rc_sae_operand_not_last_imm
:
5756 err_msg
= _("RC/SAE operand must precede immediate operands");
5758 err_msg
= _("RC/SAE operand must follow immediate operands");
5760 case invalid_register_operand
:
5761 err_msg
= _("invalid register operand");
5764 as_bad (_("%s for `%s'"), err_msg
,
5765 current_templates
->start
->name
);
5769 if (!quiet_warnings
)
5772 && (i
.types
[0].bitfield
.jumpabsolute
5773 != operand_types
[0].bitfield
.jumpabsolute
))
5775 as_warn (_("indirect %s without `*'"), t
->name
);
5778 if (t
->opcode_modifier
.isprefix
5779 && t
->opcode_modifier
.ignoresize
)
5781 /* Warn them that a data or address size prefix doesn't
5782 affect assembly of the next line of code. */
5783 as_warn (_("stand-alone `%s' prefix"), t
->name
);
5787 /* Copy the template we found. */
5790 if (addr_prefix_disp
!= -1)
5791 i
.tm
.operand_types
[addr_prefix_disp
]
5792 = operand_types
[addr_prefix_disp
];
5794 if (found_reverse_match
)
5796 /* If we found a reverse match we must alter the opcode
5797 direction bit. found_reverse_match holds bits to change
5798 (different for int & float insns). */
5800 i
.tm
.base_opcode
^= found_reverse_match
;
5802 i
.tm
.operand_types
[0] = operand_types
[1];
5803 i
.tm
.operand_types
[1] = operand_types
[0];
5812 int mem_op
= operand_type_check (i
.types
[0], anymem
) ? 0 : 1;
5813 if (i
.tm
.operand_types
[mem_op
].bitfield
.esseg
)
5815 if (i
.seg
[0] != NULL
&& i
.seg
[0] != &es
)
5817 as_bad (_("`%s' operand %d must use `%ses' segment"),
5823 /* There's only ever one segment override allowed per instruction.
5824 This instruction possibly has a legal segment override on the
5825 second operand, so copy the segment to where non-string
5826 instructions store it, allowing common code. */
5827 i
.seg
[0] = i
.seg
[1];
5829 else if (i
.tm
.operand_types
[mem_op
+ 1].bitfield
.esseg
)
5831 if (i
.seg
[1] != NULL
&& i
.seg
[1] != &es
)
5833 as_bad (_("`%s' operand %d must use `%ses' segment"),
5844 process_suffix (void)
5846 /* If matched instruction specifies an explicit instruction mnemonic
5848 if (i
.tm
.opcode_modifier
.size16
)
5849 i
.suffix
= WORD_MNEM_SUFFIX
;
5850 else if (i
.tm
.opcode_modifier
.size32
)
5851 i
.suffix
= LONG_MNEM_SUFFIX
;
5852 else if (i
.tm
.opcode_modifier
.size64
)
5853 i
.suffix
= QWORD_MNEM_SUFFIX
;
5854 else if (i
.reg_operands
)
5856 /* If there's no instruction mnemonic suffix we try to invent one
5857 based on register operands. */
5860 /* We take i.suffix from the last register operand specified,
5861 Destination register type is more significant than source
5862 register type. crc32 in SSE4.2 prefers source register
5864 if (i
.tm
.base_opcode
== 0xf20f38f1)
5866 if (i
.types
[0].bitfield
.reg
&& i
.types
[0].bitfield
.word
)
5867 i
.suffix
= WORD_MNEM_SUFFIX
;
5868 else if (i
.types
[0].bitfield
.reg
&& i
.types
[0].bitfield
.dword
)
5869 i
.suffix
= LONG_MNEM_SUFFIX
;
5870 else if (i
.types
[0].bitfield
.reg
&& i
.types
[0].bitfield
.qword
)
5871 i
.suffix
= QWORD_MNEM_SUFFIX
;
5873 else if (i
.tm
.base_opcode
== 0xf20f38f0)
5875 if (i
.types
[0].bitfield
.reg
&& i
.types
[0].bitfield
.byte
)
5876 i
.suffix
= BYTE_MNEM_SUFFIX
;
5883 if (i
.tm
.base_opcode
== 0xf20f38f1
5884 || i
.tm
.base_opcode
== 0xf20f38f0)
5886 /* We have to know the operand size for crc32. */
5887 as_bad (_("ambiguous memory operand size for `%s`"),
5892 for (op
= i
.operands
; --op
>= 0;)
5893 if (!i
.tm
.operand_types
[op
].bitfield
.inoutportreg
5894 && !i
.tm
.operand_types
[op
].bitfield
.shiftcount
)
5896 if (!i
.types
[op
].bitfield
.reg
)
5898 if (i
.types
[op
].bitfield
.byte
)
5899 i
.suffix
= BYTE_MNEM_SUFFIX
;
5900 else if (i
.types
[op
].bitfield
.word
)
5901 i
.suffix
= WORD_MNEM_SUFFIX
;
5902 else if (i
.types
[op
].bitfield
.dword
)
5903 i
.suffix
= LONG_MNEM_SUFFIX
;
5904 else if (i
.types
[op
].bitfield
.qword
)
5905 i
.suffix
= QWORD_MNEM_SUFFIX
;
5912 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
5915 && i
.tm
.opcode_modifier
.ignoresize
5916 && i
.tm
.opcode_modifier
.no_bsuf
)
5918 else if (!check_byte_reg ())
5921 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
5924 && i
.tm
.opcode_modifier
.ignoresize
5925 && i
.tm
.opcode_modifier
.no_lsuf
5926 && !i
.tm
.opcode_modifier
.todword
5927 && !i
.tm
.opcode_modifier
.toqword
)
5929 else if (!check_long_reg ())
5932 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
5935 && i
.tm
.opcode_modifier
.ignoresize
5936 && i
.tm
.opcode_modifier
.no_qsuf
5937 && !i
.tm
.opcode_modifier
.todword
5938 && !i
.tm
.opcode_modifier
.toqword
)
5940 else if (!check_qword_reg ())
5943 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
5946 && i
.tm
.opcode_modifier
.ignoresize
5947 && i
.tm
.opcode_modifier
.no_wsuf
)
5949 else if (!check_word_reg ())
5952 else if (intel_syntax
&& i
.tm
.opcode_modifier
.ignoresize
)
5953 /* Do nothing if the instruction is going to ignore the prefix. */
5958 else if (i
.tm
.opcode_modifier
.defaultsize
5960 /* exclude fldenv/frstor/fsave/fstenv */
5961 && i
.tm
.opcode_modifier
.no_ssuf
)
5963 i
.suffix
= stackop_size
;
5965 else if (intel_syntax
5967 && (i
.tm
.operand_types
[0].bitfield
.jumpabsolute
5968 || i
.tm
.opcode_modifier
.jumpbyte
5969 || i
.tm
.opcode_modifier
.jumpintersegment
5970 || (i
.tm
.base_opcode
== 0x0f01 /* [ls][gi]dt */
5971 && i
.tm
.extension_opcode
<= 3)))
5976 if (!i
.tm
.opcode_modifier
.no_qsuf
)
5978 i
.suffix
= QWORD_MNEM_SUFFIX
;
5983 if (!i
.tm
.opcode_modifier
.no_lsuf
)
5984 i
.suffix
= LONG_MNEM_SUFFIX
;
5987 if (!i
.tm
.opcode_modifier
.no_wsuf
)
5988 i
.suffix
= WORD_MNEM_SUFFIX
;
5997 if (i
.tm
.opcode_modifier
.w
)
5999 as_bad (_("no instruction mnemonic suffix given and "
6000 "no register operands; can't size instruction"));
6006 unsigned int suffixes
;
6008 suffixes
= !i
.tm
.opcode_modifier
.no_bsuf
;
6009 if (!i
.tm
.opcode_modifier
.no_wsuf
)
6011 if (!i
.tm
.opcode_modifier
.no_lsuf
)
6013 if (!i
.tm
.opcode_modifier
.no_ldsuf
)
6015 if (!i
.tm
.opcode_modifier
.no_ssuf
)
6017 if (flag_code
== CODE_64BIT
&& !i
.tm
.opcode_modifier
.no_qsuf
)
6020 /* There are more than suffix matches. */
6021 if (i
.tm
.opcode_modifier
.w
6022 || ((suffixes
& (suffixes
- 1))
6023 && !i
.tm
.opcode_modifier
.defaultsize
6024 && !i
.tm
.opcode_modifier
.ignoresize
))
6026 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
6032 /* Change the opcode based on the operand size given by i.suffix. */
6035 /* Size floating point instruction. */
6036 case LONG_MNEM_SUFFIX
:
6037 if (i
.tm
.opcode_modifier
.floatmf
)
6039 i
.tm
.base_opcode
^= 4;
6043 case WORD_MNEM_SUFFIX
:
6044 case QWORD_MNEM_SUFFIX
:
6045 /* It's not a byte, select word/dword operation. */
6046 if (i
.tm
.opcode_modifier
.w
)
6048 if (i
.tm
.opcode_modifier
.shortform
)
6049 i
.tm
.base_opcode
|= 8;
6051 i
.tm
.base_opcode
|= 1;
6054 case SHORT_MNEM_SUFFIX
:
6055 /* Now select between word & dword operations via the operand
6056 size prefix, except for instructions that will ignore this
6058 if (i
.reg_operands
> 0
6059 && i
.types
[0].bitfield
.reg
6060 && i
.tm
.opcode_modifier
.addrprefixopreg
6061 && (i
.tm
.opcode_modifier
.immext
6062 || i
.operands
== 1))
6064 /* The address size override prefix changes the size of the
6066 if ((flag_code
== CODE_32BIT
6067 && i
.op
[0].regs
->reg_type
.bitfield
.word
)
6068 || (flag_code
!= CODE_32BIT
6069 && i
.op
[0].regs
->reg_type
.bitfield
.dword
))
6070 if (!add_prefix (ADDR_PREFIX_OPCODE
))
6073 else if (i
.suffix
!= QWORD_MNEM_SUFFIX
6074 && !i
.tm
.opcode_modifier
.ignoresize
6075 && !i
.tm
.opcode_modifier
.floatmf
6076 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
6077 || (flag_code
== CODE_64BIT
6078 && i
.tm
.opcode_modifier
.jumpbyte
)))
6080 unsigned int prefix
= DATA_PREFIX_OPCODE
;
6082 if (i
.tm
.opcode_modifier
.jumpbyte
) /* jcxz, loop */
6083 prefix
= ADDR_PREFIX_OPCODE
;
6085 if (!add_prefix (prefix
))
6089 /* Set mode64 for an operand. */
6090 if (i
.suffix
== QWORD_MNEM_SUFFIX
6091 && flag_code
== CODE_64BIT
6092 && !i
.tm
.opcode_modifier
.norex64
6093 /* Special case for xchg %rax,%rax. It is NOP and doesn't
6095 && ! (i
.operands
== 2
6096 && i
.tm
.base_opcode
== 0x90
6097 && i
.tm
.extension_opcode
== None
6098 && operand_type_equal (&i
.types
[0], &acc64
)
6099 && operand_type_equal (&i
.types
[1], &acc64
)))
6105 if (i
.reg_operands
!= 0
6107 && i
.tm
.opcode_modifier
.addrprefixopreg
6108 && !i
.tm
.opcode_modifier
.immext
)
6110 /* Check invalid register operand when the address size override
6111 prefix changes the size of register operands. */
6113 enum { need_word
, need_dword
, need_qword
} need
;
6115 if (flag_code
== CODE_32BIT
)
6116 need
= i
.prefix
[ADDR_PREFIX
] ? need_word
: need_dword
;
6119 if (i
.prefix
[ADDR_PREFIX
])
6122 need
= flag_code
== CODE_64BIT
? need_qword
: need_word
;
6125 for (op
= 0; op
< i
.operands
; op
++)
6126 if (i
.types
[op
].bitfield
.reg
6127 && ((need
== need_word
6128 && !i
.op
[op
].regs
->reg_type
.bitfield
.word
)
6129 || (need
== need_dword
6130 && !i
.op
[op
].regs
->reg_type
.bitfield
.dword
)
6131 || (need
== need_qword
6132 && !i
.op
[op
].regs
->reg_type
.bitfield
.qword
)))
6134 as_bad (_("invalid register operand size for `%s'"),
6144 check_byte_reg (void)
6148 for (op
= i
.operands
; --op
>= 0;)
6150 /* Skip non-register operands. */
6151 if (!i
.types
[op
].bitfield
.reg
)
6154 /* If this is an eight bit register, it's OK. If it's the 16 or
6155 32 bit version of an eight bit register, we will just use the
6156 low portion, and that's OK too. */
6157 if (i
.types
[op
].bitfield
.byte
)
6160 /* I/O port address operands are OK too. */
6161 if (i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
6164 /* crc32 doesn't generate this warning. */
6165 if (i
.tm
.base_opcode
== 0xf20f38f0)
6168 if ((i
.types
[op
].bitfield
.word
6169 || i
.types
[op
].bitfield
.dword
6170 || i
.types
[op
].bitfield
.qword
)
6171 && i
.op
[op
].regs
->reg_num
< 4
6172 /* Prohibit these changes in 64bit mode, since the lowering
6173 would be more complicated. */
6174 && flag_code
!= CODE_64BIT
)
6176 #if REGISTER_WARNINGS
6177 if (!quiet_warnings
)
6178 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6180 (i
.op
[op
].regs
+ (i
.types
[op
].bitfield
.word
6181 ? REGNAM_AL
- REGNAM_AX
6182 : REGNAM_AL
- REGNAM_EAX
))->reg_name
,
6184 i
.op
[op
].regs
->reg_name
,
6189 /* Any other register is bad. */
6190 if (i
.types
[op
].bitfield
.reg
6191 || i
.types
[op
].bitfield
.regmmx
6192 || i
.types
[op
].bitfield
.regsimd
6193 || i
.types
[op
].bitfield
.sreg2
6194 || i
.types
[op
].bitfield
.sreg3
6195 || i
.types
[op
].bitfield
.control
6196 || i
.types
[op
].bitfield
.debug
6197 || i
.types
[op
].bitfield
.test
)
6199 as_bad (_("`%s%s' not allowed with `%s%c'"),
6201 i
.op
[op
].regs
->reg_name
,
6211 check_long_reg (void)
6215 for (op
= i
.operands
; --op
>= 0;)
6216 /* Skip non-register operands. */
6217 if (!i
.types
[op
].bitfield
.reg
)
6219 /* Reject eight bit registers, except where the template requires
6220 them. (eg. movzb) */
6221 else if (i
.types
[op
].bitfield
.byte
6222 && (i
.tm
.operand_types
[op
].bitfield
.reg
6223 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6224 && (i
.tm
.operand_types
[op
].bitfield
.word
6225 || i
.tm
.operand_types
[op
].bitfield
.dword
))
6227 as_bad (_("`%s%s' not allowed with `%s%c'"),
6229 i
.op
[op
].regs
->reg_name
,
6234 /* Warn if the e prefix on a general reg is missing. */
6235 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
6236 && i
.types
[op
].bitfield
.word
6237 && (i
.tm
.operand_types
[op
].bitfield
.reg
6238 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6239 && i
.tm
.operand_types
[op
].bitfield
.dword
)
6241 /* Prohibit these changes in the 64bit mode, since the
6242 lowering is more complicated. */
6243 if (flag_code
== CODE_64BIT
)
6245 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6246 register_prefix
, i
.op
[op
].regs
->reg_name
,
6250 #if REGISTER_WARNINGS
6251 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6253 (i
.op
[op
].regs
+ REGNAM_EAX
- REGNAM_AX
)->reg_name
,
6254 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
6257 /* Warn if the r prefix on a general reg is present. */
6258 else if (i
.types
[op
].bitfield
.qword
6259 && (i
.tm
.operand_types
[op
].bitfield
.reg
6260 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6261 && i
.tm
.operand_types
[op
].bitfield
.dword
)
6264 && i
.tm
.opcode_modifier
.toqword
6265 && !i
.types
[0].bitfield
.regsimd
)
6267 /* Convert to QWORD. We want REX byte. */
6268 i
.suffix
= QWORD_MNEM_SUFFIX
;
6272 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6273 register_prefix
, i
.op
[op
].regs
->reg_name
,
6282 check_qword_reg (void)
6286 for (op
= i
.operands
; --op
>= 0; )
6287 /* Skip non-register operands. */
6288 if (!i
.types
[op
].bitfield
.reg
)
6290 /* Reject eight bit registers, except where the template requires
6291 them. (eg. movzb) */
6292 else if (i
.types
[op
].bitfield
.byte
6293 && (i
.tm
.operand_types
[op
].bitfield
.reg
6294 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6295 && (i
.tm
.operand_types
[op
].bitfield
.word
6296 || i
.tm
.operand_types
[op
].bitfield
.dword
))
6298 as_bad (_("`%s%s' not allowed with `%s%c'"),
6300 i
.op
[op
].regs
->reg_name
,
6305 /* Warn if the r prefix on a general reg is missing. */
6306 else if ((i
.types
[op
].bitfield
.word
6307 || i
.types
[op
].bitfield
.dword
)
6308 && (i
.tm
.operand_types
[op
].bitfield
.reg
6309 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6310 && i
.tm
.operand_types
[op
].bitfield
.qword
)
6312 /* Prohibit these changes in the 64bit mode, since the
6313 lowering is more complicated. */
6315 && i
.tm
.opcode_modifier
.todword
6316 && !i
.types
[0].bitfield
.regsimd
)
6318 /* Convert to DWORD. We don't want REX byte. */
6319 i
.suffix
= LONG_MNEM_SUFFIX
;
6323 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6324 register_prefix
, i
.op
[op
].regs
->reg_name
,
6333 check_word_reg (void)
6336 for (op
= i
.operands
; --op
>= 0;)
6337 /* Skip non-register operands. */
6338 if (!i
.types
[op
].bitfield
.reg
)
6340 /* Reject eight bit registers, except where the template requires
6341 them. (eg. movzb) */
6342 else if (i
.types
[op
].bitfield
.byte
6343 && (i
.tm
.operand_types
[op
].bitfield
.reg
6344 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6345 && (i
.tm
.operand_types
[op
].bitfield
.word
6346 || i
.tm
.operand_types
[op
].bitfield
.dword
))
6348 as_bad (_("`%s%s' not allowed with `%s%c'"),
6350 i
.op
[op
].regs
->reg_name
,
6355 /* Warn if the e or r prefix on a general reg is present. */
6356 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
6357 && (i
.types
[op
].bitfield
.dword
6358 || i
.types
[op
].bitfield
.qword
)
6359 && (i
.tm
.operand_types
[op
].bitfield
.reg
6360 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6361 && i
.tm
.operand_types
[op
].bitfield
.word
)
6363 /* Prohibit these changes in the 64bit mode, since the
6364 lowering is more complicated. */
6365 if (flag_code
== CODE_64BIT
)
6367 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6368 register_prefix
, i
.op
[op
].regs
->reg_name
,
6372 #if REGISTER_WARNINGS
6373 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6375 (i
.op
[op
].regs
+ REGNAM_AX
- REGNAM_EAX
)->reg_name
,
6376 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
6383 update_imm (unsigned int j
)
6385 i386_operand_type overlap
= i
.types
[j
];
6386 if ((overlap
.bitfield
.imm8
6387 || overlap
.bitfield
.imm8s
6388 || overlap
.bitfield
.imm16
6389 || overlap
.bitfield
.imm32
6390 || overlap
.bitfield
.imm32s
6391 || overlap
.bitfield
.imm64
)
6392 && !operand_type_equal (&overlap
, &imm8
)
6393 && !operand_type_equal (&overlap
, &imm8s
)
6394 && !operand_type_equal (&overlap
, &imm16
)
6395 && !operand_type_equal (&overlap
, &imm32
)
6396 && !operand_type_equal (&overlap
, &imm32s
)
6397 && !operand_type_equal (&overlap
, &imm64
))
6401 i386_operand_type temp
;
6403 operand_type_set (&temp
, 0);
6404 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
6406 temp
.bitfield
.imm8
= overlap
.bitfield
.imm8
;
6407 temp
.bitfield
.imm8s
= overlap
.bitfield
.imm8s
;
6409 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
6410 temp
.bitfield
.imm16
= overlap
.bitfield
.imm16
;
6411 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
6413 temp
.bitfield
.imm64
= overlap
.bitfield
.imm64
;
6414 temp
.bitfield
.imm32s
= overlap
.bitfield
.imm32s
;
6417 temp
.bitfield
.imm32
= overlap
.bitfield
.imm32
;
6420 else if (operand_type_equal (&overlap
, &imm16_32_32s
)
6421 || operand_type_equal (&overlap
, &imm16_32
)
6422 || operand_type_equal (&overlap
, &imm16_32s
))
6424 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
6429 if (!operand_type_equal (&overlap
, &imm8
)
6430 && !operand_type_equal (&overlap
, &imm8s
)
6431 && !operand_type_equal (&overlap
, &imm16
)
6432 && !operand_type_equal (&overlap
, &imm32
)
6433 && !operand_type_equal (&overlap
, &imm32s
)
6434 && !operand_type_equal (&overlap
, &imm64
))
6436 as_bad (_("no instruction mnemonic suffix given; "
6437 "can't determine immediate size"));
6441 i
.types
[j
] = overlap
;
6451 /* Update the first 2 immediate operands. */
6452 n
= i
.operands
> 2 ? 2 : i
.operands
;
6455 for (j
= 0; j
< n
; j
++)
6456 if (update_imm (j
) == 0)
6459 /* The 3rd operand can't be immediate operand. */
6460 gas_assert (operand_type_check (i
.types
[2], imm
) == 0);
6467 process_operands (void)
6469 /* Default segment register this instruction will use for memory
6470 accesses. 0 means unknown. This is only for optimizing out
6471 unnecessary segment overrides. */
6472 const seg_entry
*default_seg
= 0;
6474 if (i
.tm
.opcode_modifier
.sse2avx
&& i
.tm
.opcode_modifier
.vexvvvv
)
6476 unsigned int dupl
= i
.operands
;
6477 unsigned int dest
= dupl
- 1;
6480 /* The destination must be an xmm register. */
6481 gas_assert (i
.reg_operands
6482 && MAX_OPERANDS
> dupl
6483 && operand_type_equal (&i
.types
[dest
], ®xmm
));
6485 if (i
.tm
.operand_types
[0].bitfield
.acc
6486 && i
.tm
.operand_types
[0].bitfield
.xmmword
)
6488 if (i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
)
6490 /* Keep xmm0 for instructions with VEX prefix and 3
6492 i
.tm
.operand_types
[0].bitfield
.acc
= 0;
6493 i
.tm
.operand_types
[0].bitfield
.regsimd
= 1;
6498 /* We remove the first xmm0 and keep the number of
6499 operands unchanged, which in fact duplicates the
6501 for (j
= 1; j
< i
.operands
; j
++)
6503 i
.op
[j
- 1] = i
.op
[j
];
6504 i
.types
[j
- 1] = i
.types
[j
];
6505 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
6509 else if (i
.tm
.opcode_modifier
.implicit1stxmm0
)
6511 gas_assert ((MAX_OPERANDS
- 1) > dupl
6512 && (i
.tm
.opcode_modifier
.vexsources
6515 /* Add the implicit xmm0 for instructions with VEX prefix
6517 for (j
= i
.operands
; j
> 0; j
--)
6519 i
.op
[j
] = i
.op
[j
- 1];
6520 i
.types
[j
] = i
.types
[j
- 1];
6521 i
.tm
.operand_types
[j
] = i
.tm
.operand_types
[j
- 1];
6524 = (const reg_entry
*) hash_find (reg_hash
, "xmm0");
6525 i
.types
[0] = regxmm
;
6526 i
.tm
.operand_types
[0] = regxmm
;
6529 i
.reg_operands
+= 2;
6534 i
.op
[dupl
] = i
.op
[dest
];
6535 i
.types
[dupl
] = i
.types
[dest
];
6536 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
6545 i
.op
[dupl
] = i
.op
[dest
];
6546 i
.types
[dupl
] = i
.types
[dest
];
6547 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
6550 if (i
.tm
.opcode_modifier
.immext
)
6553 else if (i
.tm
.operand_types
[0].bitfield
.acc
6554 && i
.tm
.operand_types
[0].bitfield
.xmmword
)
6558 for (j
= 1; j
< i
.operands
; j
++)
6560 i
.op
[j
- 1] = i
.op
[j
];
6561 i
.types
[j
- 1] = i
.types
[j
];
6563 /* We need to adjust fields in i.tm since they are used by
6564 build_modrm_byte. */
6565 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
6572 else if (i
.tm
.opcode_modifier
.implicitquadgroup
)
6574 unsigned int regnum
, first_reg_in_group
, last_reg_in_group
;
6576 /* The second operand must be {x,y,z}mmN, where N is a multiple of 4. */
6577 gas_assert (i
.operands
>= 2 && i
.types
[1].bitfield
.regsimd
);
6578 regnum
= register_number (i
.op
[1].regs
);
6579 first_reg_in_group
= regnum
& ~3;
6580 last_reg_in_group
= first_reg_in_group
+ 3;
6581 if (regnum
!= first_reg_in_group
)
6582 as_warn (_("source register `%s%s' implicitly denotes"
6583 " `%s%.3s%u' to `%s%.3s%u' source group in `%s'"),
6584 register_prefix
, i
.op
[1].regs
->reg_name
,
6585 register_prefix
, i
.op
[1].regs
->reg_name
, first_reg_in_group
,
6586 register_prefix
, i
.op
[1].regs
->reg_name
, last_reg_in_group
,
6589 else if (i
.tm
.opcode_modifier
.regkludge
)
6591 /* The imul $imm, %reg instruction is converted into
6592 imul $imm, %reg, %reg, and the clr %reg instruction
6593 is converted into xor %reg, %reg. */
6595 unsigned int first_reg_op
;
6597 if (operand_type_check (i
.types
[0], reg
))
6601 /* Pretend we saw the extra register operand. */
6602 gas_assert (i
.reg_operands
== 1
6603 && i
.op
[first_reg_op
+ 1].regs
== 0);
6604 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
6605 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
6610 if (i
.tm
.opcode_modifier
.shortform
)
6612 if (i
.types
[0].bitfield
.sreg2
6613 || i
.types
[0].bitfield
.sreg3
)
6615 if (i
.tm
.base_opcode
== POP_SEG_SHORT
6616 && i
.op
[0].regs
->reg_num
== 1)
6618 as_bad (_("you can't `pop %scs'"), register_prefix
);
6621 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
6622 if ((i
.op
[0].regs
->reg_flags
& RegRex
) != 0)
6627 /* The register or float register operand is in operand
6631 if ((i
.types
[0].bitfield
.reg
&& i
.types
[0].bitfield
.tbyte
)
6632 || operand_type_check (i
.types
[0], reg
))
6636 /* Register goes in low 3 bits of opcode. */
6637 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
6638 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
6640 if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
6642 /* Warn about some common errors, but press on regardless.
6643 The first case can be generated by gcc (<= 2.8.1). */
6644 if (i
.operands
== 2)
6646 /* Reversed arguments on faddp, fsubp, etc. */
6647 as_warn (_("translating to `%s %s%s,%s%s'"), i
.tm
.name
,
6648 register_prefix
, i
.op
[!intel_syntax
].regs
->reg_name
,
6649 register_prefix
, i
.op
[intel_syntax
].regs
->reg_name
);
6653 /* Extraneous `l' suffix on fp insn. */
6654 as_warn (_("translating to `%s %s%s'"), i
.tm
.name
,
6655 register_prefix
, i
.op
[0].regs
->reg_name
);
6660 else if (i
.tm
.opcode_modifier
.modrm
)
6662 /* The opcode is completed (modulo i.tm.extension_opcode which
6663 must be put into the modrm byte). Now, we make the modrm and
6664 index base bytes based on all the info we've collected. */
6666 default_seg
= build_modrm_byte ();
6668 else if ((i
.tm
.base_opcode
& ~0x3) == MOV_AX_DISP32
)
6672 else if (i
.tm
.opcode_modifier
.isstring
)
6674 /* For the string instructions that allow a segment override
6675 on one of their operands, the default segment is ds. */
6679 if (i
.tm
.base_opcode
== 0x8d /* lea */
6682 as_warn (_("segment override on `%s' is ineffectual"), i
.tm
.name
);
6684 /* If a segment was explicitly specified, and the specified segment
6685 is not the default, use an opcode prefix to select it. If we
6686 never figured out what the default segment is, then default_seg
6687 will be zero at this point, and the specified segment prefix will
6689 if ((i
.seg
[0]) && (i
.seg
[0] != default_seg
))
6691 if (!add_prefix (i
.seg
[0]->seg_prefix
))
6697 static const seg_entry
*
6698 build_modrm_byte (void)
6700 const seg_entry
*default_seg
= 0;
6701 unsigned int source
, dest
;
6704 vex_3_sources
= i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
;
6707 unsigned int nds
, reg_slot
;
6710 dest
= i
.operands
- 1;
6713 /* There are 2 kinds of instructions:
6714 1. 5 operands: 4 register operands or 3 register operands
6715 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
6716 VexW0 or VexW1. The destination must be either XMM, YMM or
6718 2. 4 operands: 4 register operands or 3 register operands
6719 plus 1 memory operand, with VexXDS. */
6720 gas_assert ((i
.reg_operands
== 4
6721 || (i
.reg_operands
== 3 && i
.mem_operands
== 1))
6722 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
6723 && i
.tm
.opcode_modifier
.vexw
6724 && i
.tm
.operand_types
[dest
].bitfield
.regsimd
);
6726 /* If VexW1 is set, the first non-immediate operand is the source and
6727 the second non-immediate one is encoded in the immediate operand. */
6728 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
6730 source
= i
.imm_operands
;
6731 reg_slot
= i
.imm_operands
+ 1;
6735 source
= i
.imm_operands
+ 1;
6736 reg_slot
= i
.imm_operands
;
6739 if (i
.imm_operands
== 0)
6741 /* When there is no immediate operand, generate an 8bit
6742 immediate operand to encode the first operand. */
6743 exp
= &im_expressions
[i
.imm_operands
++];
6744 i
.op
[i
.operands
].imms
= exp
;
6745 i
.types
[i
.operands
] = imm8
;
6748 gas_assert (i
.tm
.operand_types
[reg_slot
].bitfield
.regsimd
);
6749 exp
->X_op
= O_constant
;
6750 exp
->X_add_number
= register_number (i
.op
[reg_slot
].regs
) << 4;
6751 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
6755 unsigned int imm_slot
;
6757 gas_assert (i
.imm_operands
== 1 && i
.types
[0].bitfield
.vec_imm4
);
6759 if (i
.tm
.opcode_modifier
.immext
)
6761 /* When ImmExt is set, the immediate byte is the last
6763 imm_slot
= i
.operands
- 1;
6771 /* Turn on Imm8 so that output_imm will generate it. */
6772 i
.types
[imm_slot
].bitfield
.imm8
= 1;
6775 gas_assert (i
.tm
.operand_types
[reg_slot
].bitfield
.regsimd
);
6776 i
.op
[imm_slot
].imms
->X_add_number
6777 |= register_number (i
.op
[reg_slot
].regs
) << 4;
6778 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
6781 gas_assert (i
.tm
.operand_types
[nds
].bitfield
.regsimd
);
6782 i
.vex
.register_specifier
= i
.op
[nds
].regs
;
6787 /* i.reg_operands MUST be the number of real register operands;
6788 implicit registers do not count. If there are 3 register
6789 operands, it must be a instruction with VexNDS. For a
6790 instruction with VexNDD, the destination register is encoded
6791 in VEX prefix. If there are 4 register operands, it must be
6792 a instruction with VEX prefix and 3 sources. */
6793 if (i
.mem_operands
== 0
6794 && ((i
.reg_operands
== 2
6795 && i
.tm
.opcode_modifier
.vexvvvv
<= VEXXDS
)
6796 || (i
.reg_operands
== 3
6797 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
6798 || (i
.reg_operands
== 4 && vex_3_sources
)))
6806 /* When there are 3 operands, one of them may be immediate,
6807 which may be the first or the last operand. Otherwise,
6808 the first operand must be shift count register (cl) or it
6809 is an instruction with VexNDS. */
6810 gas_assert (i
.imm_operands
== 1
6811 || (i
.imm_operands
== 0
6812 && (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
6813 || i
.types
[0].bitfield
.shiftcount
)));
6814 if (operand_type_check (i
.types
[0], imm
)
6815 || i
.types
[0].bitfield
.shiftcount
)
6821 /* When there are 4 operands, the first two must be 8bit
6822 immediate operands. The source operand will be the 3rd
6825 For instructions with VexNDS, if the first operand
6826 an imm8, the source operand is the 2nd one. If the last
6827 operand is imm8, the source operand is the first one. */
6828 gas_assert ((i
.imm_operands
== 2
6829 && i
.types
[0].bitfield
.imm8
6830 && i
.types
[1].bitfield
.imm8
)
6831 || (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
6832 && i
.imm_operands
== 1
6833 && (i
.types
[0].bitfield
.imm8
6834 || i
.types
[i
.operands
- 1].bitfield
.imm8
6836 if (i
.imm_operands
== 2)
6840 if (i
.types
[0].bitfield
.imm8
)
6847 if (is_evex_encoding (&i
.tm
))
6849 /* For EVEX instructions, when there are 5 operands, the
6850 first one must be immediate operand. If the second one
6851 is immediate operand, the source operand is the 3th
6852 one. If the last one is immediate operand, the source
6853 operand is the 2nd one. */
6854 gas_assert (i
.imm_operands
== 2
6855 && i
.tm
.opcode_modifier
.sae
6856 && operand_type_check (i
.types
[0], imm
));
6857 if (operand_type_check (i
.types
[1], imm
))
6859 else if (operand_type_check (i
.types
[4], imm
))
6873 /* RC/SAE operand could be between DEST and SRC. That happens
6874 when one operand is GPR and the other one is XMM/YMM/ZMM
6876 if (i
.rounding
&& i
.rounding
->operand
== (int) dest
)
6879 if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
6881 /* For instructions with VexNDS, the register-only source
6882 operand must be a 32/64bit integer, XMM, YMM, ZMM, or mask
6883 register. It is encoded in VEX prefix. We need to
6884 clear RegMem bit before calling operand_type_equal. */
6886 i386_operand_type op
;
6889 /* Check register-only source operand when two source
6890 operands are swapped. */
6891 if (!i
.tm
.operand_types
[source
].bitfield
.baseindex
6892 && i
.tm
.operand_types
[dest
].bitfield
.baseindex
)
6900 op
= i
.tm
.operand_types
[vvvv
];
6901 op
.bitfield
.regmem
= 0;
6902 if ((dest
+ 1) >= i
.operands
6903 || ((!op
.bitfield
.reg
6904 || (!op
.bitfield
.dword
&& !op
.bitfield
.qword
))
6905 && !op
.bitfield
.regsimd
6906 && !operand_type_equal (&op
, ®mask
)))
6908 i
.vex
.register_specifier
= i
.op
[vvvv
].regs
;
6914 /* One of the register operands will be encoded in the i.tm.reg
6915 field, the other in the combined i.tm.mode and i.tm.regmem
6916 fields. If no form of this instruction supports a memory
6917 destination operand, then we assume the source operand may
6918 sometimes be a memory operand and so we need to store the
6919 destination in the i.rm.reg field. */
6920 if (!i
.tm
.operand_types
[dest
].bitfield
.regmem
6921 && operand_type_check (i
.tm
.operand_types
[dest
], anymem
) == 0)
6923 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
6924 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
6925 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
6927 if ((i
.op
[dest
].regs
->reg_flags
& RegVRex
) != 0)
6929 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
6931 if ((i
.op
[source
].regs
->reg_flags
& RegVRex
) != 0)
6936 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
6937 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
6938 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
6940 if ((i
.op
[dest
].regs
->reg_flags
& RegVRex
) != 0)
6942 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
6944 if ((i
.op
[source
].regs
->reg_flags
& RegVRex
) != 0)
6947 if (flag_code
!= CODE_64BIT
&& (i
.rex
& REX_R
))
6949 if (!i
.types
[i
.tm
.operand_types
[0].bitfield
.regmem
].bitfield
.control
)
6952 add_prefix (LOCK_PREFIX_OPCODE
);
6956 { /* If it's not 2 reg operands... */
6961 unsigned int fake_zero_displacement
= 0;
6964 for (op
= 0; op
< i
.operands
; op
++)
6965 if (operand_type_check (i
.types
[op
], anymem
))
6967 gas_assert (op
< i
.operands
);
6969 if (i
.tm
.opcode_modifier
.vecsib
)
6971 if (i
.index_reg
->reg_num
== RegEiz
6972 || i
.index_reg
->reg_num
== RegRiz
)
6975 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6978 i
.sib
.base
= NO_BASE_REGISTER
;
6979 i
.sib
.scale
= i
.log2_scale_factor
;
6980 i
.types
[op
].bitfield
.disp8
= 0;
6981 i
.types
[op
].bitfield
.disp16
= 0;
6982 i
.types
[op
].bitfield
.disp64
= 0;
6983 if (flag_code
!= CODE_64BIT
|| i
.prefix
[ADDR_PREFIX
])
6985 /* Must be 32 bit */
6986 i
.types
[op
].bitfield
.disp32
= 1;
6987 i
.types
[op
].bitfield
.disp32s
= 0;
6991 i
.types
[op
].bitfield
.disp32
= 0;
6992 i
.types
[op
].bitfield
.disp32s
= 1;
6995 i
.sib
.index
= i
.index_reg
->reg_num
;
6996 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
6998 if ((i
.index_reg
->reg_flags
& RegVRex
) != 0)
7004 if (i
.base_reg
== 0)
7007 if (!i
.disp_operands
)
7008 fake_zero_displacement
= 1;
7009 if (i
.index_reg
== 0)
7011 i386_operand_type newdisp
;
7013 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
7014 /* Operand is just <disp> */
7015 if (flag_code
== CODE_64BIT
)
7017 /* 64bit mode overwrites the 32bit absolute
7018 addressing by RIP relative addressing and
7019 absolute addressing is encoded by one of the
7020 redundant SIB forms. */
7021 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
7022 i
.sib
.base
= NO_BASE_REGISTER
;
7023 i
.sib
.index
= NO_INDEX_REGISTER
;
7024 newdisp
= (!i
.prefix
[ADDR_PREFIX
] ? disp32s
: disp32
);
7026 else if ((flag_code
== CODE_16BIT
)
7027 ^ (i
.prefix
[ADDR_PREFIX
] != 0))
7029 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
7034 i
.rm
.regmem
= NO_BASE_REGISTER
;
7037 i
.types
[op
] = operand_type_and_not (i
.types
[op
], anydisp
);
7038 i
.types
[op
] = operand_type_or (i
.types
[op
], newdisp
);
7040 else if (!i
.tm
.opcode_modifier
.vecsib
)
7042 /* !i.base_reg && i.index_reg */
7043 if (i
.index_reg
->reg_num
== RegEiz
7044 || i
.index_reg
->reg_num
== RegRiz
)
7045 i
.sib
.index
= NO_INDEX_REGISTER
;
7047 i
.sib
.index
= i
.index_reg
->reg_num
;
7048 i
.sib
.base
= NO_BASE_REGISTER
;
7049 i
.sib
.scale
= i
.log2_scale_factor
;
7050 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
7051 i
.types
[op
].bitfield
.disp8
= 0;
7052 i
.types
[op
].bitfield
.disp16
= 0;
7053 i
.types
[op
].bitfield
.disp64
= 0;
7054 if (flag_code
!= CODE_64BIT
|| i
.prefix
[ADDR_PREFIX
])
7056 /* Must be 32 bit */
7057 i
.types
[op
].bitfield
.disp32
= 1;
7058 i
.types
[op
].bitfield
.disp32s
= 0;
7062 i
.types
[op
].bitfield
.disp32
= 0;
7063 i
.types
[op
].bitfield
.disp32s
= 1;
7065 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
7069 /* RIP addressing for 64bit mode. */
7070 else if (i
.base_reg
->reg_num
== RegRip
||
7071 i
.base_reg
->reg_num
== RegEip
)
7073 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
7074 i
.rm
.regmem
= NO_BASE_REGISTER
;
7075 i
.types
[op
].bitfield
.disp8
= 0;
7076 i
.types
[op
].bitfield
.disp16
= 0;
7077 i
.types
[op
].bitfield
.disp32
= 0;
7078 i
.types
[op
].bitfield
.disp32s
= 1;
7079 i
.types
[op
].bitfield
.disp64
= 0;
7080 i
.flags
[op
] |= Operand_PCrel
;
7081 if (! i
.disp_operands
)
7082 fake_zero_displacement
= 1;
7084 else if (i
.base_reg
->reg_type
.bitfield
.word
)
7086 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
7087 switch (i
.base_reg
->reg_num
)
7090 if (i
.index_reg
== 0)
7092 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
7093 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
7097 if (i
.index_reg
== 0)
7100 if (operand_type_check (i
.types
[op
], disp
) == 0)
7102 /* fake (%bp) into 0(%bp) */
7103 i
.types
[op
].bitfield
.disp8
= 1;
7104 fake_zero_displacement
= 1;
7107 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
7108 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
7110 default: /* (%si) -> 4 or (%di) -> 5 */
7111 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
7113 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
7115 else /* i.base_reg and 32/64 bit mode */
7117 if (flag_code
== CODE_64BIT
7118 && operand_type_check (i
.types
[op
], disp
))
7120 i
.types
[op
].bitfield
.disp16
= 0;
7121 i
.types
[op
].bitfield
.disp64
= 0;
7122 if (i
.prefix
[ADDR_PREFIX
] == 0)
7124 i
.types
[op
].bitfield
.disp32
= 0;
7125 i
.types
[op
].bitfield
.disp32s
= 1;
7129 i
.types
[op
].bitfield
.disp32
= 1;
7130 i
.types
[op
].bitfield
.disp32s
= 0;
7134 if (!i
.tm
.opcode_modifier
.vecsib
)
7135 i
.rm
.regmem
= i
.base_reg
->reg_num
;
7136 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
7138 i
.sib
.base
= i
.base_reg
->reg_num
;
7139 /* x86-64 ignores REX prefix bit here to avoid decoder
7141 if (!(i
.base_reg
->reg_flags
& RegRex
)
7142 && (i
.base_reg
->reg_num
== EBP_REG_NUM
7143 || i
.base_reg
->reg_num
== ESP_REG_NUM
))
7145 if (i
.base_reg
->reg_num
== 5 && i
.disp_operands
== 0)
7147 fake_zero_displacement
= 1;
7148 i
.types
[op
].bitfield
.disp8
= 1;
7150 i
.sib
.scale
= i
.log2_scale_factor
;
7151 if (i
.index_reg
== 0)
7153 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
7154 /* <disp>(%esp) becomes two byte modrm with no index
7155 register. We've already stored the code for esp
7156 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
7157 Any base register besides %esp will not use the
7158 extra modrm byte. */
7159 i
.sib
.index
= NO_INDEX_REGISTER
;
7161 else if (!i
.tm
.opcode_modifier
.vecsib
)
7163 if (i
.index_reg
->reg_num
== RegEiz
7164 || i
.index_reg
->reg_num
== RegRiz
)
7165 i
.sib
.index
= NO_INDEX_REGISTER
;
7167 i
.sib
.index
= i
.index_reg
->reg_num
;
7168 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
7169 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
7174 && (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
7175 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
))
7179 if (!fake_zero_displacement
7183 fake_zero_displacement
= 1;
7184 if (i
.disp_encoding
== disp_encoding_8bit
)
7185 i
.types
[op
].bitfield
.disp8
= 1;
7187 i
.types
[op
].bitfield
.disp32
= 1;
7189 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
7193 if (fake_zero_displacement
)
7195 /* Fakes a zero displacement assuming that i.types[op]
7196 holds the correct displacement size. */
7199 gas_assert (i
.op
[op
].disps
== 0);
7200 exp
= &disp_expressions
[i
.disp_operands
++];
7201 i
.op
[op
].disps
= exp
;
7202 exp
->X_op
= O_constant
;
7203 exp
->X_add_number
= 0;
7204 exp
->X_add_symbol
= (symbolS
*) 0;
7205 exp
->X_op_symbol
= (symbolS
*) 0;
7213 if (i
.tm
.opcode_modifier
.vexsources
== XOP2SOURCES
)
7215 if (operand_type_check (i
.types
[0], imm
))
7216 i
.vex
.register_specifier
= NULL
;
7219 /* VEX.vvvv encodes one of the sources when the first
7220 operand is not an immediate. */
7221 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
7222 i
.vex
.register_specifier
= i
.op
[0].regs
;
7224 i
.vex
.register_specifier
= i
.op
[1].regs
;
7227 /* Destination is a XMM register encoded in the ModRM.reg
7229 i
.rm
.reg
= i
.op
[2].regs
->reg_num
;
7230 if ((i
.op
[2].regs
->reg_flags
& RegRex
) != 0)
7233 /* ModRM.rm and VEX.B encodes the other source. */
7234 if (!i
.mem_operands
)
7238 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
7239 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
7241 i
.rm
.regmem
= i
.op
[0].regs
->reg_num
;
7243 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
7247 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXLWP
)
7249 i
.vex
.register_specifier
= i
.op
[2].regs
;
7250 if (!i
.mem_operands
)
7253 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
7254 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
7258 /* Fill in i.rm.reg or i.rm.regmem field with register operand
7259 (if any) based on i.tm.extension_opcode. Again, we must be
7260 careful to make sure that segment/control/debug/test/MMX
7261 registers are coded into the i.rm.reg field. */
7262 else if (i
.reg_operands
)
7265 unsigned int vex_reg
= ~0;
7267 for (op
= 0; op
< i
.operands
; op
++)
7268 if (i
.types
[op
].bitfield
.reg
7269 || i
.types
[op
].bitfield
.regmmx
7270 || i
.types
[op
].bitfield
.regsimd
7271 || i
.types
[op
].bitfield
.regbnd
7272 || i
.types
[op
].bitfield
.regmask
7273 || i
.types
[op
].bitfield
.sreg2
7274 || i
.types
[op
].bitfield
.sreg3
7275 || i
.types
[op
].bitfield
.control
7276 || i
.types
[op
].bitfield
.debug
7277 || i
.types
[op
].bitfield
.test
)
7282 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
7284 /* For instructions with VexNDS, the register-only
7285 source operand is encoded in VEX prefix. */
7286 gas_assert (mem
!= (unsigned int) ~0);
7291 gas_assert (op
< i
.operands
);
7295 /* Check register-only source operand when two source
7296 operands are swapped. */
7297 if (!i
.tm
.operand_types
[op
].bitfield
.baseindex
7298 && i
.tm
.operand_types
[op
+ 1].bitfield
.baseindex
)
7302 gas_assert (mem
== (vex_reg
+ 1)
7303 && op
< i
.operands
);
7308 gas_assert (vex_reg
< i
.operands
);
7312 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXNDD
)
7314 /* For instructions with VexNDD, the register destination
7315 is encoded in VEX prefix. */
7316 if (i
.mem_operands
== 0)
7318 /* There is no memory operand. */
7319 gas_assert ((op
+ 2) == i
.operands
);
7324 /* There are only 2 non-immediate operands. */
7325 gas_assert (op
< i
.imm_operands
+ 2
7326 && i
.operands
== i
.imm_operands
+ 2);
7327 vex_reg
= i
.imm_operands
+ 1;
7331 gas_assert (op
< i
.operands
);
7333 if (vex_reg
!= (unsigned int) ~0)
7335 i386_operand_type
*type
= &i
.tm
.operand_types
[vex_reg
];
7337 if ((!type
->bitfield
.reg
7338 || (!type
->bitfield
.dword
&& !type
->bitfield
.qword
))
7339 && !type
->bitfield
.regsimd
7340 && !operand_type_equal (type
, ®mask
))
7343 i
.vex
.register_specifier
= i
.op
[vex_reg
].regs
;
7346 /* Don't set OP operand twice. */
7349 /* If there is an extension opcode to put here, the
7350 register number must be put into the regmem field. */
7351 if (i
.tm
.extension_opcode
!= None
)
7353 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
7354 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
7356 if ((i
.op
[op
].regs
->reg_flags
& RegVRex
) != 0)
7361 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
7362 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
7364 if ((i
.op
[op
].regs
->reg_flags
& RegVRex
) != 0)
7369 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
7370 must set it to 3 to indicate this is a register operand
7371 in the regmem field. */
7372 if (!i
.mem_operands
)
7376 /* Fill in i.rm.reg field with extension opcode (if any). */
7377 if (i
.tm
.extension_opcode
!= None
)
7378 i
.rm
.reg
= i
.tm
.extension_opcode
;
7384 output_branch (void)
7390 relax_substateT subtype
;
7394 code16
= flag_code
== CODE_16BIT
? CODE16
: 0;
7395 size
= i
.disp_encoding
== disp_encoding_32bit
? BIG
: SMALL
;
7398 if (i
.prefix
[DATA_PREFIX
] != 0)
7404 /* Pentium4 branch hints. */
7405 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
7406 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
7411 if (i
.prefix
[REX_PREFIX
] != 0)
7417 /* BND prefixed jump. */
7418 if (i
.prefix
[BND_PREFIX
] != 0)
7420 FRAG_APPEND_1_CHAR (i
.prefix
[BND_PREFIX
]);
7424 if (i
.prefixes
!= 0 && !intel_syntax
)
7425 as_warn (_("skipping prefixes on this instruction"));
7427 /* It's always a symbol; End frag & setup for relax.
7428 Make sure there is enough room in this frag for the largest
7429 instruction we may generate in md_convert_frag. This is 2
7430 bytes for the opcode and room for the prefix and largest
7432 frag_grow (prefix
+ 2 + 4);
7433 /* Prefix and 1 opcode byte go in fr_fix. */
7434 p
= frag_more (prefix
+ 1);
7435 if (i
.prefix
[DATA_PREFIX
] != 0)
7436 *p
++ = DATA_PREFIX_OPCODE
;
7437 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
7438 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
7439 *p
++ = i
.prefix
[SEG_PREFIX
];
7440 if (i
.prefix
[REX_PREFIX
] != 0)
7441 *p
++ = i
.prefix
[REX_PREFIX
];
7442 *p
= i
.tm
.base_opcode
;
7444 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
7445 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, size
);
7446 else if (cpu_arch_flags
.bitfield
.cpui386
)
7447 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, size
);
7449 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, size
);
7452 sym
= i
.op
[0].disps
->X_add_symbol
;
7453 off
= i
.op
[0].disps
->X_add_number
;
7455 if (i
.op
[0].disps
->X_op
!= O_constant
7456 && i
.op
[0].disps
->X_op
!= O_symbol
)
7458 /* Handle complex expressions. */
7459 sym
= make_expr_symbol (i
.op
[0].disps
);
7463 /* 1 possible extra opcode + 4 byte displacement go in var part.
7464 Pass reloc in fr_var. */
7465 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
7468 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7469 /* Return TRUE iff PLT32 relocation should be used for branching to
7473 need_plt32_p (symbolS
*s
)
7475 /* PLT32 relocation is ELF only. */
7479 /* Since there is no need to prepare for PLT branch on x86-64, we
7480 can generate R_X86_64_PLT32, instead of R_X86_64_PC32, which can
7481 be used as a marker for 32-bit PC-relative branches. */
7485 /* Weak or undefined symbol need PLT32 relocation. */
7486 if (S_IS_WEAK (s
) || !S_IS_DEFINED (s
))
7489 /* Non-global symbol doesn't need PLT32 relocation. */
7490 if (! S_IS_EXTERNAL (s
))
7493 /* Other global symbols need PLT32 relocation. NB: Symbol with
7494 non-default visibilities are treated as normal global symbol
7495 so that PLT32 relocation can be used as a marker for 32-bit
7496 PC-relative branches. It is useful for linker relaxation. */
7507 bfd_reloc_code_real_type jump_reloc
= i
.reloc
[0];
7509 if (i
.tm
.opcode_modifier
.jumpbyte
)
7511 /* This is a loop or jecxz type instruction. */
7513 if (i
.prefix
[ADDR_PREFIX
] != 0)
7515 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
7518 /* Pentium4 branch hints. */
7519 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
7520 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
7522 FRAG_APPEND_1_CHAR (i
.prefix
[SEG_PREFIX
]);
7531 if (flag_code
== CODE_16BIT
)
7534 if (i
.prefix
[DATA_PREFIX
] != 0)
7536 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
7546 if (i
.prefix
[REX_PREFIX
] != 0)
7548 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
7552 /* BND prefixed jump. */
7553 if (i
.prefix
[BND_PREFIX
] != 0)
7555 FRAG_APPEND_1_CHAR (i
.prefix
[BND_PREFIX
]);
7559 if (i
.prefixes
!= 0 && !intel_syntax
)
7560 as_warn (_("skipping prefixes on this instruction"));
7562 p
= frag_more (i
.tm
.opcode_length
+ size
);
7563 switch (i
.tm
.opcode_length
)
7566 *p
++ = i
.tm
.base_opcode
>> 8;
7569 *p
++ = i
.tm
.base_opcode
;
7575 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7577 && jump_reloc
== NO_RELOC
7578 && need_plt32_p (i
.op
[0].disps
->X_add_symbol
))
7579 jump_reloc
= BFD_RELOC_X86_64_PLT32
;
7582 jump_reloc
= reloc (size
, 1, 1, jump_reloc
);
7584 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
7585 i
.op
[0].disps
, 1, jump_reloc
);
7587 /* All jumps handled here are signed, but don't use a signed limit
7588 check for 32 and 16 bit jumps as we want to allow wrap around at
7589 4G and 64k respectively. */
7591 fixP
->fx_signed
= 1;
7595 output_interseg_jump (void)
7603 if (flag_code
== CODE_16BIT
)
7607 if (i
.prefix
[DATA_PREFIX
] != 0)
7613 if (i
.prefix
[REX_PREFIX
] != 0)
7623 if (i
.prefixes
!= 0 && !intel_syntax
)
7624 as_warn (_("skipping prefixes on this instruction"));
7626 /* 1 opcode; 2 segment; offset */
7627 p
= frag_more (prefix
+ 1 + 2 + size
);
7629 if (i
.prefix
[DATA_PREFIX
] != 0)
7630 *p
++ = DATA_PREFIX_OPCODE
;
7632 if (i
.prefix
[REX_PREFIX
] != 0)
7633 *p
++ = i
.prefix
[REX_PREFIX
];
7635 *p
++ = i
.tm
.base_opcode
;
7636 if (i
.op
[1].imms
->X_op
== O_constant
)
7638 offsetT n
= i
.op
[1].imms
->X_add_number
;
7641 && !fits_in_unsigned_word (n
)
7642 && !fits_in_signed_word (n
))
7644 as_bad (_("16-bit jump out of range"));
7647 md_number_to_chars (p
, n
, size
);
7650 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
7651 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
7652 if (i
.op
[0].imms
->X_op
!= O_constant
)
7653 as_bad (_("can't handle non absolute segment in `%s'"),
7655 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
7661 fragS
*insn_start_frag
;
7662 offsetT insn_start_off
;
7664 /* Tie dwarf2 debug info to the address at the start of the insn.
7665 We can't do this after the insn has been output as the current
7666 frag may have been closed off. eg. by frag_var. */
7667 dwarf2_emit_insn (0);
7669 insn_start_frag
= frag_now
;
7670 insn_start_off
= frag_now_fix ();
7673 if (i
.tm
.opcode_modifier
.jump
)
7675 else if (i
.tm
.opcode_modifier
.jumpbyte
7676 || i
.tm
.opcode_modifier
.jumpdword
)
7678 else if (i
.tm
.opcode_modifier
.jumpintersegment
)
7679 output_interseg_jump ();
7682 /* Output normal instructions here. */
7686 unsigned int prefix
;
7689 && i
.tm
.base_opcode
== 0xfae
7691 && i
.imm_operands
== 1
7692 && (i
.op
[0].imms
->X_add_number
== 0xe8
7693 || i
.op
[0].imms
->X_add_number
== 0xf0
7694 || i
.op
[0].imms
->X_add_number
== 0xf8))
7696 /* Encode lfence, mfence, and sfence as
7697 f0 83 04 24 00 lock addl $0x0, (%{re}sp). */
7698 offsetT val
= 0x240483f0ULL
;
7700 md_number_to_chars (p
, val
, 5);
7704 /* Some processors fail on LOCK prefix. This options makes
7705 assembler ignore LOCK prefix and serves as a workaround. */
7706 if (omit_lock_prefix
)
7708 if (i
.tm
.base_opcode
== LOCK_PREFIX_OPCODE
)
7710 i
.prefix
[LOCK_PREFIX
] = 0;
7713 /* Since the VEX/EVEX prefix contains the implicit prefix, we
7714 don't need the explicit prefix. */
7715 if (!i
.tm
.opcode_modifier
.vex
&& !i
.tm
.opcode_modifier
.evex
)
7717 switch (i
.tm
.opcode_length
)
7720 if (i
.tm
.base_opcode
& 0xff000000)
7722 prefix
= (i
.tm
.base_opcode
>> 24) & 0xff;
7723 add_prefix (prefix
);
7727 if ((i
.tm
.base_opcode
& 0xff0000) != 0)
7729 prefix
= (i
.tm
.base_opcode
>> 16) & 0xff;
7730 if (!i
.tm
.cpu_flags
.bitfield
.cpupadlock
7731 || prefix
!= REPE_PREFIX_OPCODE
7732 || (i
.prefix
[REP_PREFIX
] != REPE_PREFIX_OPCODE
))
7733 add_prefix (prefix
);
7739 /* Check for pseudo prefixes. */
7740 as_bad_where (insn_start_frag
->fr_file
,
7741 insn_start_frag
->fr_line
,
7742 _("pseudo prefix without instruction"));
7748 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
7749 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
7750 R_X86_64_GOTTPOFF relocation so that linker can safely
7751 perform IE->LE optimization. */
7752 if (x86_elf_abi
== X86_64_X32_ABI
7754 && i
.reloc
[0] == BFD_RELOC_X86_64_GOTTPOFF
7755 && i
.prefix
[REX_PREFIX
] == 0)
7756 add_prefix (REX_OPCODE
);
7759 /* The prefix bytes. */
7760 for (j
= ARRAY_SIZE (i
.prefix
), q
= i
.prefix
; j
> 0; j
--, q
++)
7762 FRAG_APPEND_1_CHAR (*q
);
7766 for (j
= 0, q
= i
.prefix
; j
< ARRAY_SIZE (i
.prefix
); j
++, q
++)
7771 /* REX byte is encoded in VEX prefix. */
7775 FRAG_APPEND_1_CHAR (*q
);
7778 /* There should be no other prefixes for instructions
7783 /* For EVEX instructions i.vrex should become 0 after
7784 build_evex_prefix. For VEX instructions upper 16 registers
7785 aren't available, so VREX should be 0. */
7788 /* Now the VEX prefix. */
7789 p
= frag_more (i
.vex
.length
);
7790 for (j
= 0; j
< i
.vex
.length
; j
++)
7791 p
[j
] = i
.vex
.bytes
[j
];
7794 /* Now the opcode; be careful about word order here! */
7795 if (i
.tm
.opcode_length
== 1)
7797 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
7801 switch (i
.tm
.opcode_length
)
7805 *p
++ = (i
.tm
.base_opcode
>> 24) & 0xff;
7806 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
7810 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
7820 /* Put out high byte first: can't use md_number_to_chars! */
7821 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
7822 *p
= i
.tm
.base_opcode
& 0xff;
7825 /* Now the modrm byte and sib byte (if present). */
7826 if (i
.tm
.opcode_modifier
.modrm
)
7828 FRAG_APPEND_1_CHAR ((i
.rm
.regmem
<< 0
7831 /* If i.rm.regmem == ESP (4)
7832 && i.rm.mode != (Register mode)
7834 ==> need second modrm byte. */
7835 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
7837 && !(i
.base_reg
&& i
.base_reg
->reg_type
.bitfield
.word
))
7838 FRAG_APPEND_1_CHAR ((i
.sib
.base
<< 0
7840 | i
.sib
.scale
<< 6));
7843 if (i
.disp_operands
)
7844 output_disp (insn_start_frag
, insn_start_off
);
7847 output_imm (insn_start_frag
, insn_start_off
);
7853 pi ("" /*line*/, &i
);
7855 #endif /* DEBUG386 */
7858 /* Return the size of the displacement operand N. */
7861 disp_size (unsigned int n
)
7865 if (i
.types
[n
].bitfield
.disp64
)
7867 else if (i
.types
[n
].bitfield
.disp8
)
7869 else if (i
.types
[n
].bitfield
.disp16
)
7874 /* Return the size of the immediate operand N. */
7877 imm_size (unsigned int n
)
7880 if (i
.types
[n
].bitfield
.imm64
)
7882 else if (i
.types
[n
].bitfield
.imm8
|| i
.types
[n
].bitfield
.imm8s
)
7884 else if (i
.types
[n
].bitfield
.imm16
)
7890 output_disp (fragS
*insn_start_frag
, offsetT insn_start_off
)
7895 for (n
= 0; n
< i
.operands
; n
++)
7897 if (operand_type_check (i
.types
[n
], disp
))
7899 if (i
.op
[n
].disps
->X_op
== O_constant
)
7901 int size
= disp_size (n
);
7902 offsetT val
= i
.op
[n
].disps
->X_add_number
;
7904 val
= offset_in_range (val
>> i
.memshift
, size
);
7905 p
= frag_more (size
);
7906 md_number_to_chars (p
, val
, size
);
7910 enum bfd_reloc_code_real reloc_type
;
7911 int size
= disp_size (n
);
7912 int sign
= i
.types
[n
].bitfield
.disp32s
;
7913 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
7916 /* We can't have 8 bit displacement here. */
7917 gas_assert (!i
.types
[n
].bitfield
.disp8
);
7919 /* The PC relative address is computed relative
7920 to the instruction boundary, so in case immediate
7921 fields follows, we need to adjust the value. */
7922 if (pcrel
&& i
.imm_operands
)
7927 for (n1
= 0; n1
< i
.operands
; n1
++)
7928 if (operand_type_check (i
.types
[n1
], imm
))
7930 /* Only one immediate is allowed for PC
7931 relative address. */
7932 gas_assert (sz
== 0);
7934 i
.op
[n
].disps
->X_add_number
-= sz
;
7936 /* We should find the immediate. */
7937 gas_assert (sz
!= 0);
7940 p
= frag_more (size
);
7941 reloc_type
= reloc (size
, pcrel
, sign
, i
.reloc
[n
]);
7943 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
7944 && (((reloc_type
== BFD_RELOC_32
7945 || reloc_type
== BFD_RELOC_X86_64_32S
7946 || (reloc_type
== BFD_RELOC_64
7948 && (i
.op
[n
].disps
->X_op
== O_symbol
7949 || (i
.op
[n
].disps
->X_op
== O_add
7950 && ((symbol_get_value_expression
7951 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
7953 || reloc_type
== BFD_RELOC_32_PCREL
))
7957 if (insn_start_frag
== frag_now
)
7958 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
7963 add
= insn_start_frag
->fr_fix
- insn_start_off
;
7964 for (fr
= insn_start_frag
->fr_next
;
7965 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
7967 add
+= p
- frag_now
->fr_literal
;
7972 reloc_type
= BFD_RELOC_386_GOTPC
;
7973 i
.op
[n
].imms
->X_add_number
+= add
;
7975 else if (reloc_type
== BFD_RELOC_64
)
7976 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
7978 /* Don't do the adjustment for x86-64, as there
7979 the pcrel addressing is relative to the _next_
7980 insn, and that is taken care of in other code. */
7981 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
7983 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
7984 size
, i
.op
[n
].disps
, pcrel
,
7986 /* Check for "call/jmp *mem", "mov mem, %reg",
7987 "test %reg, mem" and "binop mem, %reg" where binop
7988 is one of adc, add, and, cmp, or, sbb, sub, xor
7989 instructions. Always generate R_386_GOT32X for
7990 "sym*GOT" operand in 32-bit mode. */
7991 if ((generate_relax_relocations
7994 && i
.rm
.regmem
== 5))
7996 || (i
.rm
.mode
== 0 && i
.rm
.regmem
== 5))
7997 && ((i
.operands
== 1
7998 && i
.tm
.base_opcode
== 0xff
7999 && (i
.rm
.reg
== 2 || i
.rm
.reg
== 4))
8001 && (i
.tm
.base_opcode
== 0x8b
8002 || i
.tm
.base_opcode
== 0x85
8003 || (i
.tm
.base_opcode
& 0xc7) == 0x03))))
8007 fixP
->fx_tcbit
= i
.rex
!= 0;
8009 && (i
.base_reg
->reg_num
== RegRip
8010 || i
.base_reg
->reg_num
== RegEip
))
8011 fixP
->fx_tcbit2
= 1;
8014 fixP
->fx_tcbit2
= 1;
8022 output_imm (fragS
*insn_start_frag
, offsetT insn_start_off
)
8027 for (n
= 0; n
< i
.operands
; n
++)
8029 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
8030 if (i
.rounding
&& (int) n
== i
.rounding
->operand
)
8033 if (operand_type_check (i
.types
[n
], imm
))
8035 if (i
.op
[n
].imms
->X_op
== O_constant
)
8037 int size
= imm_size (n
);
8040 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
8042 p
= frag_more (size
);
8043 md_number_to_chars (p
, val
, size
);
8047 /* Not absolute_section.
8048 Need a 32-bit fixup (don't support 8bit
8049 non-absolute imms). Try to support other
8051 enum bfd_reloc_code_real reloc_type
;
8052 int size
= imm_size (n
);
8055 if (i
.types
[n
].bitfield
.imm32s
8056 && (i
.suffix
== QWORD_MNEM_SUFFIX
8057 || (!i
.suffix
&& i
.tm
.opcode_modifier
.no_lsuf
)))
8062 p
= frag_more (size
);
8063 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
8065 /* This is tough to explain. We end up with this one if we
8066 * have operands that look like
8067 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
8068 * obtain the absolute address of the GOT, and it is strongly
8069 * preferable from a performance point of view to avoid using
8070 * a runtime relocation for this. The actual sequence of
8071 * instructions often look something like:
8076 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
8078 * The call and pop essentially return the absolute address
8079 * of the label .L66 and store it in %ebx. The linker itself
8080 * will ultimately change the first operand of the addl so
8081 * that %ebx points to the GOT, but to keep things simple, the
8082 * .o file must have this operand set so that it generates not
8083 * the absolute address of .L66, but the absolute address of
8084 * itself. This allows the linker itself simply treat a GOTPC
8085 * relocation as asking for a pcrel offset to the GOT to be
8086 * added in, and the addend of the relocation is stored in the
8087 * operand field for the instruction itself.
8089 * Our job here is to fix the operand so that it would add
8090 * the correct offset so that %ebx would point to itself. The
8091 * thing that is tricky is that .-.L66 will point to the
8092 * beginning of the instruction, so we need to further modify
8093 * the operand so that it will point to itself. There are
8094 * other cases where you have something like:
8096 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
8098 * and here no correction would be required. Internally in
8099 * the assembler we treat operands of this form as not being
8100 * pcrel since the '.' is explicitly mentioned, and I wonder
8101 * whether it would simplify matters to do it this way. Who
8102 * knows. In earlier versions of the PIC patches, the
8103 * pcrel_adjust field was used to store the correction, but
8104 * since the expression is not pcrel, I felt it would be
8105 * confusing to do it this way. */
8107 if ((reloc_type
== BFD_RELOC_32
8108 || reloc_type
== BFD_RELOC_X86_64_32S
8109 || reloc_type
== BFD_RELOC_64
)
8111 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
8112 && (i
.op
[n
].imms
->X_op
== O_symbol
8113 || (i
.op
[n
].imms
->X_op
== O_add
8114 && ((symbol_get_value_expression
8115 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
8120 if (insn_start_frag
== frag_now
)
8121 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
8126 add
= insn_start_frag
->fr_fix
- insn_start_off
;
8127 for (fr
= insn_start_frag
->fr_next
;
8128 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
8130 add
+= p
- frag_now
->fr_literal
;
8134 reloc_type
= BFD_RELOC_386_GOTPC
;
8136 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
8138 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
8139 i
.op
[n
].imms
->X_add_number
+= add
;
8141 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
8142 i
.op
[n
].imms
, 0, reloc_type
);
8148 /* x86_cons_fix_new is called via the expression parsing code when a
8149 reloc is needed. We use this hook to get the correct .got reloc. */
8150 static int cons_sign
= -1;
8153 x86_cons_fix_new (fragS
*frag
, unsigned int off
, unsigned int len
,
8154 expressionS
*exp
, bfd_reloc_code_real_type r
)
8156 r
= reloc (len
, 0, cons_sign
, r
);
8159 if (exp
->X_op
== O_secrel
)
8161 exp
->X_op
= O_symbol
;
8162 r
= BFD_RELOC_32_SECREL
;
8166 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
8169 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
8170 purpose of the `.dc.a' internal pseudo-op. */
8173 x86_address_bytes (void)
8175 if ((stdoutput
->arch_info
->mach
& bfd_mach_x64_32
))
8177 return stdoutput
->arch_info
->bits_per_address
/ 8;
8180 #if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
8182 # define lex_got(reloc, adjust, types) NULL
8184 /* Parse operands of the form
8185 <symbol>@GOTOFF+<nnn>
8186 and similar .plt or .got references.
8188 If we find one, set up the correct relocation in RELOC and copy the
8189 input string, minus the `@GOTOFF' into a malloc'd buffer for
8190 parsing by the calling routine. Return this buffer, and if ADJUST
8191 is non-null set it to the length of the string we removed from the
8192 input line. Otherwise return NULL. */
8194 lex_got (enum bfd_reloc_code_real
*rel
,
8196 i386_operand_type
*types
)
8198 /* Some of the relocations depend on the size of what field is to
8199 be relocated. But in our callers i386_immediate and i386_displacement
8200 we don't yet know the operand size (this will be set by insn
8201 matching). Hence we record the word32 relocation here,
8202 and adjust the reloc according to the real size in reloc(). */
8203 static const struct {
8206 const enum bfd_reloc_code_real rel
[2];
8207 const i386_operand_type types64
;
8209 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8210 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32
,
8212 OPERAND_TYPE_IMM32_64
},
8214 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real
,
8215 BFD_RELOC_X86_64_PLTOFF64
},
8216 OPERAND_TYPE_IMM64
},
8217 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32
,
8218 BFD_RELOC_X86_64_PLT32
},
8219 OPERAND_TYPE_IMM32_32S_DISP32
},
8220 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real
,
8221 BFD_RELOC_X86_64_GOTPLT64
},
8222 OPERAND_TYPE_IMM64_DISP64
},
8223 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF
,
8224 BFD_RELOC_X86_64_GOTOFF64
},
8225 OPERAND_TYPE_IMM64_DISP64
},
8226 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real
,
8227 BFD_RELOC_X86_64_GOTPCREL
},
8228 OPERAND_TYPE_IMM32_32S_DISP32
},
8229 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD
,
8230 BFD_RELOC_X86_64_TLSGD
},
8231 OPERAND_TYPE_IMM32_32S_DISP32
},
8232 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM
,
8233 _dummy_first_bfd_reloc_code_real
},
8234 OPERAND_TYPE_NONE
},
8235 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real
,
8236 BFD_RELOC_X86_64_TLSLD
},
8237 OPERAND_TYPE_IMM32_32S_DISP32
},
8238 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32
,
8239 BFD_RELOC_X86_64_GOTTPOFF
},
8240 OPERAND_TYPE_IMM32_32S_DISP32
},
8241 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32
,
8242 BFD_RELOC_X86_64_TPOFF32
},
8243 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
8244 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE
,
8245 _dummy_first_bfd_reloc_code_real
},
8246 OPERAND_TYPE_NONE
},
8247 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32
,
8248 BFD_RELOC_X86_64_DTPOFF32
},
8249 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
8250 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE
,
8251 _dummy_first_bfd_reloc_code_real
},
8252 OPERAND_TYPE_NONE
},
8253 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE
,
8254 _dummy_first_bfd_reloc_code_real
},
8255 OPERAND_TYPE_NONE
},
8256 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32
,
8257 BFD_RELOC_X86_64_GOT32
},
8258 OPERAND_TYPE_IMM32_32S_64_DISP32
},
8259 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC
,
8260 BFD_RELOC_X86_64_GOTPC32_TLSDESC
},
8261 OPERAND_TYPE_IMM32_32S_DISP32
},
8262 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL
,
8263 BFD_RELOC_X86_64_TLSDESC_CALL
},
8264 OPERAND_TYPE_IMM32_32S_DISP32
},
8269 #if defined (OBJ_MAYBE_ELF)
8274 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
8275 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
8278 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
8280 int len
= gotrel
[j
].len
;
8281 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
8283 if (gotrel
[j
].rel
[object_64bit
] != 0)
8286 char *tmpbuf
, *past_reloc
;
8288 *rel
= gotrel
[j
].rel
[object_64bit
];
8292 if (flag_code
!= CODE_64BIT
)
8294 types
->bitfield
.imm32
= 1;
8295 types
->bitfield
.disp32
= 1;
8298 *types
= gotrel
[j
].types64
;
8301 if (j
!= 0 && GOT_symbol
== NULL
)
8302 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
8304 /* The length of the first part of our input line. */
8305 first
= cp
- input_line_pointer
;
8307 /* The second part goes from after the reloc token until
8308 (and including) an end_of_line char or comma. */
8309 past_reloc
= cp
+ 1 + len
;
8311 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
8313 second
= cp
+ 1 - past_reloc
;
8315 /* Allocate and copy string. The trailing NUL shouldn't
8316 be necessary, but be safe. */
8317 tmpbuf
= XNEWVEC (char, first
+ second
+ 2);
8318 memcpy (tmpbuf
, input_line_pointer
, first
);
8319 if (second
!= 0 && *past_reloc
!= ' ')
8320 /* Replace the relocation token with ' ', so that
8321 errors like foo@GOTOFF1 will be detected. */
8322 tmpbuf
[first
++] = ' ';
8324 /* Increment length by 1 if the relocation token is
8329 memcpy (tmpbuf
+ first
, past_reloc
, second
);
8330 tmpbuf
[first
+ second
] = '\0';
8334 as_bad (_("@%s reloc is not supported with %d-bit output format"),
8335 gotrel
[j
].str
, 1 << (5 + object_64bit
));
8340 /* Might be a symbol version string. Don't as_bad here. */
8349 /* Parse operands of the form
8350 <symbol>@SECREL32+<nnn>
8352 If we find one, set up the correct relocation in RELOC and copy the
8353 input string, minus the `@SECREL32' into a malloc'd buffer for
8354 parsing by the calling routine. Return this buffer, and if ADJUST
8355 is non-null set it to the length of the string we removed from the
8356 input line. Otherwise return NULL.
8358 This function is copied from the ELF version above adjusted for PE targets. */
8361 lex_got (enum bfd_reloc_code_real
*rel ATTRIBUTE_UNUSED
,
8362 int *adjust ATTRIBUTE_UNUSED
,
8363 i386_operand_type
*types
)
8369 const enum bfd_reloc_code_real rel
[2];
8370 const i386_operand_type types64
;
8374 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL
,
8375 BFD_RELOC_32_SECREL
},
8376 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
8382 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
8383 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
8386 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
8388 int len
= gotrel
[j
].len
;
8390 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
8392 if (gotrel
[j
].rel
[object_64bit
] != 0)
8395 char *tmpbuf
, *past_reloc
;
8397 *rel
= gotrel
[j
].rel
[object_64bit
];
8403 if (flag_code
!= CODE_64BIT
)
8405 types
->bitfield
.imm32
= 1;
8406 types
->bitfield
.disp32
= 1;
8409 *types
= gotrel
[j
].types64
;
8412 /* The length of the first part of our input line. */
8413 first
= cp
- input_line_pointer
;
8415 /* The second part goes from after the reloc token until
8416 (and including) an end_of_line char or comma. */
8417 past_reloc
= cp
+ 1 + len
;
8419 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
8421 second
= cp
+ 1 - past_reloc
;
8423 /* Allocate and copy string. The trailing NUL shouldn't
8424 be necessary, but be safe. */
8425 tmpbuf
= XNEWVEC (char, first
+ second
+ 2);
8426 memcpy (tmpbuf
, input_line_pointer
, first
);
8427 if (second
!= 0 && *past_reloc
!= ' ')
8428 /* Replace the relocation token with ' ', so that
8429 errors like foo@SECLREL321 will be detected. */
8430 tmpbuf
[first
++] = ' ';
8431 memcpy (tmpbuf
+ first
, past_reloc
, second
);
8432 tmpbuf
[first
+ second
] = '\0';
8436 as_bad (_("@%s reloc is not supported with %d-bit output format"),
8437 gotrel
[j
].str
, 1 << (5 + object_64bit
));
8442 /* Might be a symbol version string. Don't as_bad here. */
8448 bfd_reloc_code_real_type
8449 x86_cons (expressionS
*exp
, int size
)
8451 bfd_reloc_code_real_type got_reloc
= NO_RELOC
;
8453 intel_syntax
= -intel_syntax
;
8456 if (size
== 4 || (object_64bit
&& size
== 8))
8458 /* Handle @GOTOFF and the like in an expression. */
8460 char *gotfree_input_line
;
8463 save
= input_line_pointer
;
8464 gotfree_input_line
= lex_got (&got_reloc
, &adjust
, NULL
);
8465 if (gotfree_input_line
)
8466 input_line_pointer
= gotfree_input_line
;
8470 if (gotfree_input_line
)
8472 /* expression () has merrily parsed up to the end of line,
8473 or a comma - in the wrong buffer. Transfer how far
8474 input_line_pointer has moved to the right buffer. */
8475 input_line_pointer
= (save
8476 + (input_line_pointer
- gotfree_input_line
)
8478 free (gotfree_input_line
);
8479 if (exp
->X_op
== O_constant
8480 || exp
->X_op
== O_absent
8481 || exp
->X_op
== O_illegal
8482 || exp
->X_op
== O_register
8483 || exp
->X_op
== O_big
)
8485 char c
= *input_line_pointer
;
8486 *input_line_pointer
= 0;
8487 as_bad (_("missing or invalid expression `%s'"), save
);
8488 *input_line_pointer
= c
;
8495 intel_syntax
= -intel_syntax
;
8498 i386_intel_simplify (exp
);
8504 signed_cons (int size
)
8506 if (flag_code
== CODE_64BIT
)
8514 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
8521 if (exp
.X_op
== O_symbol
)
8522 exp
.X_op
= O_secrel
;
8524 emit_expr (&exp
, 4);
8526 while (*input_line_pointer
++ == ',');
8528 input_line_pointer
--;
8529 demand_empty_rest_of_line ();
8533 /* Handle Vector operations. */
8536 check_VecOperations (char *op_string
, char *op_end
)
8538 const reg_entry
*mask
;
8543 && (op_end
== NULL
|| op_string
< op_end
))
8546 if (*op_string
== '{')
8550 /* Check broadcasts. */
8551 if (strncmp (op_string
, "1to", 3) == 0)
8556 goto duplicated_vec_op
;
8559 if (*op_string
== '8')
8561 else if (*op_string
== '4')
8563 else if (*op_string
== '2')
8565 else if (*op_string
== '1'
8566 && *(op_string
+1) == '6')
8573 as_bad (_("Unsupported broadcast: `%s'"), saved
);
8578 broadcast_op
.type
= bcst_type
;
8579 broadcast_op
.operand
= this_operand
;
8580 i
.broadcast
= &broadcast_op
;
8582 /* Check masking operation. */
8583 else if ((mask
= parse_register (op_string
, &end_op
)) != NULL
)
8585 /* k0 can't be used for write mask. */
8586 if (!mask
->reg_type
.bitfield
.regmask
|| mask
->reg_num
== 0)
8588 as_bad (_("`%s%s' can't be used for write mask"),
8589 register_prefix
, mask
->reg_name
);
8595 mask_op
.mask
= mask
;
8596 mask_op
.zeroing
= 0;
8597 mask_op
.operand
= this_operand
;
8603 goto duplicated_vec_op
;
8605 i
.mask
->mask
= mask
;
8607 /* Only "{z}" is allowed here. No need to check
8608 zeroing mask explicitly. */
8609 if (i
.mask
->operand
!= this_operand
)
8611 as_bad (_("invalid write mask `%s'"), saved
);
8618 /* Check zeroing-flag for masking operation. */
8619 else if (*op_string
== 'z')
8623 mask_op
.mask
= NULL
;
8624 mask_op
.zeroing
= 1;
8625 mask_op
.operand
= this_operand
;
8630 if (i
.mask
->zeroing
)
8633 as_bad (_("duplicated `%s'"), saved
);
8637 i
.mask
->zeroing
= 1;
8639 /* Only "{%k}" is allowed here. No need to check mask
8640 register explicitly. */
8641 if (i
.mask
->operand
!= this_operand
)
8643 as_bad (_("invalid zeroing-masking `%s'"),
8652 goto unknown_vec_op
;
8654 if (*op_string
!= '}')
8656 as_bad (_("missing `}' in `%s'"), saved
);
8661 /* Strip whitespace since the addition of pseudo prefixes
8662 changed how the scrubber treats '{'. */
8663 if (is_space_char (*op_string
))
8669 /* We don't know this one. */
8670 as_bad (_("unknown vector operation: `%s'"), saved
);
8674 if (i
.mask
&& i
.mask
->zeroing
&& !i
.mask
->mask
)
8676 as_bad (_("zeroing-masking only allowed with write mask"));
8684 i386_immediate (char *imm_start
)
8686 char *save_input_line_pointer
;
8687 char *gotfree_input_line
;
8690 i386_operand_type types
;
8692 operand_type_set (&types
, ~0);
8694 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
8696 as_bad (_("at most %d immediate operands are allowed"),
8697 MAX_IMMEDIATE_OPERANDS
);
8701 exp
= &im_expressions
[i
.imm_operands
++];
8702 i
.op
[this_operand
].imms
= exp
;
8704 if (is_space_char (*imm_start
))
8707 save_input_line_pointer
= input_line_pointer
;
8708 input_line_pointer
= imm_start
;
8710 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
8711 if (gotfree_input_line
)
8712 input_line_pointer
= gotfree_input_line
;
8714 exp_seg
= expression (exp
);
8718 /* Handle vector operations. */
8719 if (*input_line_pointer
== '{')
8721 input_line_pointer
= check_VecOperations (input_line_pointer
,
8723 if (input_line_pointer
== NULL
)
8727 if (*input_line_pointer
)
8728 as_bad (_("junk `%s' after expression"), input_line_pointer
);
8730 input_line_pointer
= save_input_line_pointer
;
8731 if (gotfree_input_line
)
8733 free (gotfree_input_line
);
8735 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
8736 exp
->X_op
= O_illegal
;
8739 return i386_finalize_immediate (exp_seg
, exp
, types
, imm_start
);
8743 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
8744 i386_operand_type types
, const char *imm_start
)
8746 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_illegal
|| exp
->X_op
== O_big
)
8749 as_bad (_("missing or invalid immediate expression `%s'"),
8753 else if (exp
->X_op
== O_constant
)
8755 /* Size it properly later. */
8756 i
.types
[this_operand
].bitfield
.imm64
= 1;
8757 /* If not 64bit, sign extend val. */
8758 if (flag_code
!= CODE_64BIT
8759 && (exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
8761 = (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
8763 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8764 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
8765 && exp_seg
!= absolute_section
8766 && exp_seg
!= text_section
8767 && exp_seg
!= data_section
8768 && exp_seg
!= bss_section
8769 && exp_seg
!= undefined_section
8770 && !bfd_is_com_section (exp_seg
))
8772 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
8776 else if (!intel_syntax
&& exp_seg
== reg_section
)
8779 as_bad (_("illegal immediate register operand %s"), imm_start
);
8784 /* This is an address. The size of the address will be
8785 determined later, depending on destination register,
8786 suffix, or the default for the section. */
8787 i
.types
[this_operand
].bitfield
.imm8
= 1;
8788 i
.types
[this_operand
].bitfield
.imm16
= 1;
8789 i
.types
[this_operand
].bitfield
.imm32
= 1;
8790 i
.types
[this_operand
].bitfield
.imm32s
= 1;
8791 i
.types
[this_operand
].bitfield
.imm64
= 1;
8792 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
8800 i386_scale (char *scale
)
8803 char *save
= input_line_pointer
;
8805 input_line_pointer
= scale
;
8806 val
= get_absolute_expression ();
8811 i
.log2_scale_factor
= 0;
8814 i
.log2_scale_factor
= 1;
8817 i
.log2_scale_factor
= 2;
8820 i
.log2_scale_factor
= 3;
8824 char sep
= *input_line_pointer
;
8826 *input_line_pointer
= '\0';
8827 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
8829 *input_line_pointer
= sep
;
8830 input_line_pointer
= save
;
8834 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
8836 as_warn (_("scale factor of %d without an index register"),
8837 1 << i
.log2_scale_factor
);
8838 i
.log2_scale_factor
= 0;
8840 scale
= input_line_pointer
;
8841 input_line_pointer
= save
;
8846 i386_displacement (char *disp_start
, char *disp_end
)
8850 char *save_input_line_pointer
;
8851 char *gotfree_input_line
;
8853 i386_operand_type bigdisp
, types
= anydisp
;
8856 if (i
.disp_operands
== MAX_MEMORY_OPERANDS
)
8858 as_bad (_("at most %d displacement operands are allowed"),
8859 MAX_MEMORY_OPERANDS
);
8863 operand_type_set (&bigdisp
, 0);
8864 if ((i
.types
[this_operand
].bitfield
.jumpabsolute
)
8865 || (!current_templates
->start
->opcode_modifier
.jump
8866 && !current_templates
->start
->opcode_modifier
.jumpdword
))
8868 bigdisp
.bitfield
.disp32
= 1;
8869 override
= (i
.prefix
[ADDR_PREFIX
] != 0);
8870 if (flag_code
== CODE_64BIT
)
8874 bigdisp
.bitfield
.disp32s
= 1;
8875 bigdisp
.bitfield
.disp64
= 1;
8878 else if ((flag_code
== CODE_16BIT
) ^ override
)
8880 bigdisp
.bitfield
.disp32
= 0;
8881 bigdisp
.bitfield
.disp16
= 1;
8886 /* For PC-relative branches, the width of the displacement
8887 is dependent upon data size, not address size. */
8888 override
= (i
.prefix
[DATA_PREFIX
] != 0);
8889 if (flag_code
== CODE_64BIT
)
8891 if (override
|| i
.suffix
== WORD_MNEM_SUFFIX
)
8892 bigdisp
.bitfield
.disp16
= 1;
8895 bigdisp
.bitfield
.disp32
= 1;
8896 bigdisp
.bitfield
.disp32s
= 1;
8902 override
= (i
.suffix
== (flag_code
!= CODE_16BIT
8904 : LONG_MNEM_SUFFIX
));
8905 bigdisp
.bitfield
.disp32
= 1;
8906 if ((flag_code
== CODE_16BIT
) ^ override
)
8908 bigdisp
.bitfield
.disp32
= 0;
8909 bigdisp
.bitfield
.disp16
= 1;
8913 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
8916 exp
= &disp_expressions
[i
.disp_operands
];
8917 i
.op
[this_operand
].disps
= exp
;
8919 save_input_line_pointer
= input_line_pointer
;
8920 input_line_pointer
= disp_start
;
8921 END_STRING_AND_SAVE (disp_end
);
8923 #ifndef GCC_ASM_O_HACK
8924 #define GCC_ASM_O_HACK 0
8927 END_STRING_AND_SAVE (disp_end
+ 1);
8928 if (i
.types
[this_operand
].bitfield
.baseIndex
8929 && displacement_string_end
[-1] == '+')
8931 /* This hack is to avoid a warning when using the "o"
8932 constraint within gcc asm statements.
8935 #define _set_tssldt_desc(n,addr,limit,type) \
8936 __asm__ __volatile__ ( \
8938 "movw %w1,2+%0\n\t" \
8940 "movb %b1,4+%0\n\t" \
8941 "movb %4,5+%0\n\t" \
8942 "movb $0,6+%0\n\t" \
8943 "movb %h1,7+%0\n\t" \
8945 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
8947 This works great except that the output assembler ends
8948 up looking a bit weird if it turns out that there is
8949 no offset. You end up producing code that looks like:
8962 So here we provide the missing zero. */
8964 *displacement_string_end
= '0';
8967 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
8968 if (gotfree_input_line
)
8969 input_line_pointer
= gotfree_input_line
;
8971 exp_seg
= expression (exp
);
8974 if (*input_line_pointer
)
8975 as_bad (_("junk `%s' after expression"), input_line_pointer
);
8977 RESTORE_END_STRING (disp_end
+ 1);
8979 input_line_pointer
= save_input_line_pointer
;
8980 if (gotfree_input_line
)
8982 free (gotfree_input_line
);
8984 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
8985 exp
->X_op
= O_illegal
;
8988 ret
= i386_finalize_displacement (exp_seg
, exp
, types
, disp_start
);
8990 RESTORE_END_STRING (disp_end
);
8996 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
8997 i386_operand_type types
, const char *disp_start
)
8999 i386_operand_type bigdisp
;
9002 /* We do this to make sure that the section symbol is in
9003 the symbol table. We will ultimately change the relocation
9004 to be relative to the beginning of the section. */
9005 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
9006 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
9007 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
9009 if (exp
->X_op
!= O_symbol
)
9012 if (S_IS_LOCAL (exp
->X_add_symbol
)
9013 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
9014 && S_GET_SEGMENT (exp
->X_add_symbol
) != expr_section
)
9015 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
9016 exp
->X_op
= O_subtract
;
9017 exp
->X_op_symbol
= GOT_symbol
;
9018 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
9019 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
9020 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
9021 i
.reloc
[this_operand
] = BFD_RELOC_64
;
9023 i
.reloc
[this_operand
] = BFD_RELOC_32
;
9026 else if (exp
->X_op
== O_absent
9027 || exp
->X_op
== O_illegal
9028 || exp
->X_op
== O_big
)
9031 as_bad (_("missing or invalid displacement expression `%s'"),
9036 else if (flag_code
== CODE_64BIT
9037 && !i
.prefix
[ADDR_PREFIX
]
9038 && exp
->X_op
== O_constant
)
9040 /* Since displacement is signed extended to 64bit, don't allow
9041 disp32 and turn off disp32s if they are out of range. */
9042 i
.types
[this_operand
].bitfield
.disp32
= 0;
9043 if (!fits_in_signed_long (exp
->X_add_number
))
9045 i
.types
[this_operand
].bitfield
.disp32s
= 0;
9046 if (i
.types
[this_operand
].bitfield
.baseindex
)
9048 as_bad (_("0x%lx out range of signed 32bit displacement"),
9049 (long) exp
->X_add_number
);
9055 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
9056 else if (exp
->X_op
!= O_constant
9057 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
9058 && exp_seg
!= absolute_section
9059 && exp_seg
!= text_section
9060 && exp_seg
!= data_section
9061 && exp_seg
!= bss_section
9062 && exp_seg
!= undefined_section
9063 && !bfd_is_com_section (exp_seg
))
9065 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
9070 /* Check if this is a displacement only operand. */
9071 bigdisp
= i
.types
[this_operand
];
9072 bigdisp
.bitfield
.disp8
= 0;
9073 bigdisp
.bitfield
.disp16
= 0;
9074 bigdisp
.bitfield
.disp32
= 0;
9075 bigdisp
.bitfield
.disp32s
= 0;
9076 bigdisp
.bitfield
.disp64
= 0;
9077 if (operand_type_all_zero (&bigdisp
))
9078 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
9084 /* Return the active addressing mode, taking address override and
9085 registers forming the address into consideration. Update the
9086 address override prefix if necessary. */
9088 static enum flag_code
9089 i386_addressing_mode (void)
9091 enum flag_code addr_mode
;
9093 if (i
.prefix
[ADDR_PREFIX
])
9094 addr_mode
= flag_code
== CODE_32BIT
? CODE_16BIT
: CODE_32BIT
;
9097 addr_mode
= flag_code
;
9099 #if INFER_ADDR_PREFIX
9100 if (i
.mem_operands
== 0)
9102 /* Infer address prefix from the first memory operand. */
9103 const reg_entry
*addr_reg
= i
.base_reg
;
9105 if (addr_reg
== NULL
)
9106 addr_reg
= i
.index_reg
;
9110 if (addr_reg
->reg_num
== RegEip
9111 || addr_reg
->reg_num
== RegEiz
9112 || addr_reg
->reg_type
.bitfield
.dword
)
9113 addr_mode
= CODE_32BIT
;
9114 else if (flag_code
!= CODE_64BIT
9115 && addr_reg
->reg_type
.bitfield
.word
)
9116 addr_mode
= CODE_16BIT
;
9118 if (addr_mode
!= flag_code
)
9120 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
9122 /* Change the size of any displacement too. At most one
9123 of Disp16 or Disp32 is set.
9124 FIXME. There doesn't seem to be any real need for
9125 separate Disp16 and Disp32 flags. The same goes for
9126 Imm16 and Imm32. Removing them would probably clean
9127 up the code quite a lot. */
9128 if (flag_code
!= CODE_64BIT
9129 && (i
.types
[this_operand
].bitfield
.disp16
9130 || i
.types
[this_operand
].bitfield
.disp32
))
9131 i
.types
[this_operand
]
9132 = operand_type_xor (i
.types
[this_operand
], disp16_32
);
9142 /* Make sure the memory operand we've been dealt is valid.
9143 Return 1 on success, 0 on a failure. */
9146 i386_index_check (const char *operand_string
)
9148 const char *kind
= "base/index";
9149 enum flag_code addr_mode
= i386_addressing_mode ();
9151 if (current_templates
->start
->opcode_modifier
.isstring
9152 && !current_templates
->start
->opcode_modifier
.immext
9153 && (current_templates
->end
[-1].opcode_modifier
.isstring
9156 /* Memory operands of string insns are special in that they only allow
9157 a single register (rDI, rSI, or rBX) as their memory address. */
9158 const reg_entry
*expected_reg
;
9159 static const char *di_si
[][2] =
9165 static const char *bx
[] = { "ebx", "bx", "rbx" };
9167 kind
= "string address";
9169 if (current_templates
->start
->opcode_modifier
.repprefixok
)
9171 i386_operand_type type
= current_templates
->end
[-1].operand_types
[0];
9173 if (!type
.bitfield
.baseindex
9174 || ((!i
.mem_operands
!= !intel_syntax
)
9175 && current_templates
->end
[-1].operand_types
[1]
9176 .bitfield
.baseindex
))
9177 type
= current_templates
->end
[-1].operand_types
[1];
9178 expected_reg
= hash_find (reg_hash
,
9179 di_si
[addr_mode
][type
.bitfield
.esseg
]);
9183 expected_reg
= hash_find (reg_hash
, bx
[addr_mode
]);
9185 if (i
.base_reg
!= expected_reg
9187 || operand_type_check (i
.types
[this_operand
], disp
))
9189 /* The second memory operand must have the same size as
9193 && !((addr_mode
== CODE_64BIT
9194 && i
.base_reg
->reg_type
.bitfield
.qword
)
9195 || (addr_mode
== CODE_32BIT
9196 ? i
.base_reg
->reg_type
.bitfield
.dword
9197 : i
.base_reg
->reg_type
.bitfield
.word
)))
9200 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
9202 intel_syntax
? '[' : '(',
9204 expected_reg
->reg_name
,
9205 intel_syntax
? ']' : ')');
9212 as_bad (_("`%s' is not a valid %s expression"),
9213 operand_string
, kind
);
9218 if (addr_mode
!= CODE_16BIT
)
9220 /* 32-bit/64-bit checks. */
9222 && (addr_mode
== CODE_64BIT
9223 ? !i
.base_reg
->reg_type
.bitfield
.qword
9224 : !i
.base_reg
->reg_type
.bitfield
.dword
)
9226 || (i
.base_reg
->reg_num
9227 != (addr_mode
== CODE_64BIT
? RegRip
: RegEip
))))
9229 && !i
.index_reg
->reg_type
.bitfield
.xmmword
9230 && !i
.index_reg
->reg_type
.bitfield
.ymmword
9231 && !i
.index_reg
->reg_type
.bitfield
.zmmword
9232 && ((addr_mode
== CODE_64BIT
9233 ? !(i
.index_reg
->reg_type
.bitfield
.qword
9234 || i
.index_reg
->reg_num
== RegRiz
)
9235 : !(i
.index_reg
->reg_type
.bitfield
.dword
9236 || i
.index_reg
->reg_num
== RegEiz
))
9237 || !i
.index_reg
->reg_type
.bitfield
.baseindex
)))
9240 /* bndmk, bndldx, and bndstx have special restrictions. */
9241 if (current_templates
->start
->base_opcode
== 0xf30f1b
9242 || (current_templates
->start
->base_opcode
& ~1) == 0x0f1a)
9244 /* They cannot use RIP-relative addressing. */
9245 if (i
.base_reg
&& i
.base_reg
->reg_num
== RegRip
)
9247 as_bad (_("`%s' cannot be used here"), operand_string
);
9251 /* bndldx and bndstx ignore their scale factor. */
9252 if (current_templates
->start
->base_opcode
!= 0xf30f1b
9253 && i
.log2_scale_factor
)
9254 as_warn (_("register scaling is being ignored here"));
9259 /* 16-bit checks. */
9261 && (!i
.base_reg
->reg_type
.bitfield
.word
9262 || !i
.base_reg
->reg_type
.bitfield
.baseindex
))
9264 && (!i
.index_reg
->reg_type
.bitfield
.word
9265 || !i
.index_reg
->reg_type
.bitfield
.baseindex
9267 && i
.base_reg
->reg_num
< 6
9268 && i
.index_reg
->reg_num
>= 6
9269 && i
.log2_scale_factor
== 0))))
9276 /* Handle vector immediates. */
9279 RC_SAE_immediate (const char *imm_start
)
9281 unsigned int match_found
, j
;
9282 const char *pstr
= imm_start
;
9290 for (j
= 0; j
< ARRAY_SIZE (RC_NamesTable
); j
++)
9292 if (!strncmp (pstr
, RC_NamesTable
[j
].name
, RC_NamesTable
[j
].len
))
9296 rc_op
.type
= RC_NamesTable
[j
].type
;
9297 rc_op
.operand
= this_operand
;
9298 i
.rounding
= &rc_op
;
9302 as_bad (_("duplicated `%s'"), imm_start
);
9305 pstr
+= RC_NamesTable
[j
].len
;
9315 as_bad (_("Missing '}': '%s'"), imm_start
);
9318 /* RC/SAE immediate string should contain nothing more. */;
9321 as_bad (_("Junk after '}': '%s'"), imm_start
);
9325 exp
= &im_expressions
[i
.imm_operands
++];
9326 i
.op
[this_operand
].imms
= exp
;
9328 exp
->X_op
= O_constant
;
9329 exp
->X_add_number
= 0;
9330 exp
->X_add_symbol
= (symbolS
*) 0;
9331 exp
->X_op_symbol
= (symbolS
*) 0;
9333 i
.types
[this_operand
].bitfield
.imm8
= 1;
9337 /* Only string instructions can have a second memory operand, so
9338 reduce current_templates to just those if it contains any. */
9340 maybe_adjust_templates (void)
9342 const insn_template
*t
;
9344 gas_assert (i
.mem_operands
== 1);
9346 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
9347 if (t
->opcode_modifier
.isstring
)
9350 if (t
< current_templates
->end
)
9352 static templates aux_templates
;
9353 bfd_boolean recheck
;
9355 aux_templates
.start
= t
;
9356 for (; t
< current_templates
->end
; ++t
)
9357 if (!t
->opcode_modifier
.isstring
)
9359 aux_templates
.end
= t
;
9361 /* Determine whether to re-check the first memory operand. */
9362 recheck
= (aux_templates
.start
!= current_templates
->start
9363 || t
!= current_templates
->end
);
9365 current_templates
= &aux_templates
;
9370 if (i
.memop1_string
!= NULL
9371 && i386_index_check (i
.memop1_string
) == 0)
9380 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
9384 i386_att_operand (char *operand_string
)
9388 char *op_string
= operand_string
;
9390 if (is_space_char (*op_string
))
9393 /* We check for an absolute prefix (differentiating,
9394 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
9395 if (*op_string
== ABSOLUTE_PREFIX
)
9398 if (is_space_char (*op_string
))
9400 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
9403 /* Check if operand is a register. */
9404 if ((r
= parse_register (op_string
, &end_op
)) != NULL
)
9406 i386_operand_type temp
;
9408 /* Check for a segment override by searching for ':' after a
9409 segment register. */
9411 if (is_space_char (*op_string
))
9413 if (*op_string
== ':'
9414 && (r
->reg_type
.bitfield
.sreg2
9415 || r
->reg_type
.bitfield
.sreg3
))
9420 i
.seg
[i
.mem_operands
] = &es
;
9423 i
.seg
[i
.mem_operands
] = &cs
;
9426 i
.seg
[i
.mem_operands
] = &ss
;
9429 i
.seg
[i
.mem_operands
] = &ds
;
9432 i
.seg
[i
.mem_operands
] = &fs
;
9435 i
.seg
[i
.mem_operands
] = &gs
;
9439 /* Skip the ':' and whitespace. */
9441 if (is_space_char (*op_string
))
9444 if (!is_digit_char (*op_string
)
9445 && !is_identifier_char (*op_string
)
9446 && *op_string
!= '('
9447 && *op_string
!= ABSOLUTE_PREFIX
)
9449 as_bad (_("bad memory operand `%s'"), op_string
);
9452 /* Handle case of %es:*foo. */
9453 if (*op_string
== ABSOLUTE_PREFIX
)
9456 if (is_space_char (*op_string
))
9458 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
9460 goto do_memory_reference
;
9463 /* Handle vector operations. */
9464 if (*op_string
== '{')
9466 op_string
= check_VecOperations (op_string
, NULL
);
9467 if (op_string
== NULL
)
9473 as_bad (_("junk `%s' after register"), op_string
);
9477 temp
.bitfield
.baseindex
= 0;
9478 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
9480 i
.types
[this_operand
].bitfield
.unspecified
= 0;
9481 i
.op
[this_operand
].regs
= r
;
9484 else if (*op_string
== REGISTER_PREFIX
)
9486 as_bad (_("bad register name `%s'"), op_string
);
9489 else if (*op_string
== IMMEDIATE_PREFIX
)
9492 if (i
.types
[this_operand
].bitfield
.jumpabsolute
)
9494 as_bad (_("immediate operand illegal with absolute jump"));
9497 if (!i386_immediate (op_string
))
9500 else if (RC_SAE_immediate (operand_string
))
9502 /* If it is a RC or SAE immediate, do nothing. */
9505 else if (is_digit_char (*op_string
)
9506 || is_identifier_char (*op_string
)
9507 || *op_string
== '"'
9508 || *op_string
== '(')
9510 /* This is a memory reference of some sort. */
9513 /* Start and end of displacement string expression (if found). */
9514 char *displacement_string_start
;
9515 char *displacement_string_end
;
9518 do_memory_reference
:
9519 if (i
.mem_operands
== 1 && !maybe_adjust_templates ())
9521 if ((i
.mem_operands
== 1
9522 && !current_templates
->start
->opcode_modifier
.isstring
)
9523 || i
.mem_operands
== 2)
9525 as_bad (_("too many memory references for `%s'"),
9526 current_templates
->start
->name
);
9530 /* Check for base index form. We detect the base index form by
9531 looking for an ')' at the end of the operand, searching
9532 for the '(' matching it, and finding a REGISTER_PREFIX or ','
9534 base_string
= op_string
+ strlen (op_string
);
9536 /* Handle vector operations. */
9537 vop_start
= strchr (op_string
, '{');
9538 if (vop_start
&& vop_start
< base_string
)
9540 if (check_VecOperations (vop_start
, base_string
) == NULL
)
9542 base_string
= vop_start
;
9546 if (is_space_char (*base_string
))
9549 /* If we only have a displacement, set-up for it to be parsed later. */
9550 displacement_string_start
= op_string
;
9551 displacement_string_end
= base_string
+ 1;
9553 if (*base_string
== ')')
9556 unsigned int parens_balanced
= 1;
9557 /* We've already checked that the number of left & right ()'s are
9558 equal, so this loop will not be infinite. */
9562 if (*base_string
== ')')
9564 if (*base_string
== '(')
9567 while (parens_balanced
);
9569 temp_string
= base_string
;
9571 /* Skip past '(' and whitespace. */
9573 if (is_space_char (*base_string
))
9576 if (*base_string
== ','
9577 || ((i
.base_reg
= parse_register (base_string
, &end_op
))
9580 displacement_string_end
= temp_string
;
9582 i
.types
[this_operand
].bitfield
.baseindex
= 1;
9586 base_string
= end_op
;
9587 if (is_space_char (*base_string
))
9591 /* There may be an index reg or scale factor here. */
9592 if (*base_string
== ',')
9595 if (is_space_char (*base_string
))
9598 if ((i
.index_reg
= parse_register (base_string
, &end_op
))
9601 base_string
= end_op
;
9602 if (is_space_char (*base_string
))
9604 if (*base_string
== ',')
9607 if (is_space_char (*base_string
))
9610 else if (*base_string
!= ')')
9612 as_bad (_("expecting `,' or `)' "
9613 "after index register in `%s'"),
9618 else if (*base_string
== REGISTER_PREFIX
)
9620 end_op
= strchr (base_string
, ',');
9623 as_bad (_("bad register name `%s'"), base_string
);
9627 /* Check for scale factor. */
9628 if (*base_string
!= ')')
9630 char *end_scale
= i386_scale (base_string
);
9635 base_string
= end_scale
;
9636 if (is_space_char (*base_string
))
9638 if (*base_string
!= ')')
9640 as_bad (_("expecting `)' "
9641 "after scale factor in `%s'"),
9646 else if (!i
.index_reg
)
9648 as_bad (_("expecting index register or scale factor "
9649 "after `,'; got '%c'"),
9654 else if (*base_string
!= ')')
9656 as_bad (_("expecting `,' or `)' "
9657 "after base register in `%s'"),
9662 else if (*base_string
== REGISTER_PREFIX
)
9664 end_op
= strchr (base_string
, ',');
9667 as_bad (_("bad register name `%s'"), base_string
);
9672 /* If there's an expression beginning the operand, parse it,
9673 assuming displacement_string_start and
9674 displacement_string_end are meaningful. */
9675 if (displacement_string_start
!= displacement_string_end
)
9677 if (!i386_displacement (displacement_string_start
,
9678 displacement_string_end
))
9682 /* Special case for (%dx) while doing input/output op. */
9684 && i
.base_reg
->reg_type
.bitfield
.inoutportreg
9686 && i
.log2_scale_factor
== 0
9687 && i
.seg
[i
.mem_operands
] == 0
9688 && !operand_type_check (i
.types
[this_operand
], disp
))
9690 i
.types
[this_operand
] = i
.base_reg
->reg_type
;
9694 if (i386_index_check (operand_string
) == 0)
9696 i
.types
[this_operand
].bitfield
.mem
= 1;
9697 if (i
.mem_operands
== 0)
9698 i
.memop1_string
= xstrdup (operand_string
);
9703 /* It's not a memory operand; argh! */
9704 as_bad (_("invalid char %s beginning operand %d `%s'"),
9705 output_invalid (*op_string
),
9710 return 1; /* Normal return. */
9713 /* Calculate the maximum variable size (i.e., excluding fr_fix)
9714 that an rs_machine_dependent frag may reach. */
9717 i386_frag_max_var (fragS
*frag
)
9719 /* The only relaxable frags are for jumps.
9720 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
9721 gas_assert (frag
->fr_type
== rs_machine_dependent
);
9722 return TYPE_FROM_RELAX_STATE (frag
->fr_subtype
) == UNCOND_JUMP
? 4 : 5;
9725 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9727 elf_symbol_resolved_in_segment_p (symbolS
*fr_symbol
, offsetT fr_var
)
9729 /* STT_GNU_IFUNC symbol must go through PLT. */
9730 if ((symbol_get_bfdsym (fr_symbol
)->flags
9731 & BSF_GNU_INDIRECT_FUNCTION
) != 0)
9734 if (!S_IS_EXTERNAL (fr_symbol
))
9735 /* Symbol may be weak or local. */
9736 return !S_IS_WEAK (fr_symbol
);
9738 /* Global symbols with non-default visibility can't be preempted. */
9739 if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol
)) != STV_DEFAULT
)
9742 if (fr_var
!= NO_RELOC
)
9743 switch ((enum bfd_reloc_code_real
) fr_var
)
9745 case BFD_RELOC_386_PLT32
:
9746 case BFD_RELOC_X86_64_PLT32
:
9747 /* Symbol with PLT relocation may be preempted. */
9753 /* Global symbols with default visibility in a shared library may be
9754 preempted by another definition. */
9759 /* md_estimate_size_before_relax()
9761 Called just before relax() for rs_machine_dependent frags. The x86
9762 assembler uses these frags to handle variable size jump
9765 Any symbol that is now undefined will not become defined.
9766 Return the correct fr_subtype in the frag.
9767 Return the initial "guess for variable size of frag" to caller.
9768 The guess is actually the growth beyond the fixed part. Whatever
9769 we do to grow the fixed or variable part contributes to our
9773 md_estimate_size_before_relax (fragS
*fragP
, segT segment
)
9775 /* We've already got fragP->fr_subtype right; all we have to do is
9776 check for un-relaxable symbols. On an ELF system, we can't relax
9777 an externally visible symbol, because it may be overridden by a
9779 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
9780 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9782 && !elf_symbol_resolved_in_segment_p (fragP
->fr_symbol
,
9785 #if defined (OBJ_COFF) && defined (TE_PE)
9786 || (OUTPUT_FLAVOR
== bfd_target_coff_flavour
9787 && S_IS_WEAK (fragP
->fr_symbol
))
9791 /* Symbol is undefined in this segment, or we need to keep a
9792 reloc so that weak symbols can be overridden. */
9793 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
9794 enum bfd_reloc_code_real reloc_type
;
9795 unsigned char *opcode
;
9798 if (fragP
->fr_var
!= NO_RELOC
)
9799 reloc_type
= (enum bfd_reloc_code_real
) fragP
->fr_var
;
9801 reloc_type
= BFD_RELOC_16_PCREL
;
9802 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9803 else if (need_plt32_p (fragP
->fr_symbol
))
9804 reloc_type
= BFD_RELOC_X86_64_PLT32
;
9807 reloc_type
= BFD_RELOC_32_PCREL
;
9809 old_fr_fix
= fragP
->fr_fix
;
9810 opcode
= (unsigned char *) fragP
->fr_opcode
;
9812 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
9815 /* Make jmp (0xeb) a (d)word displacement jump. */
9817 fragP
->fr_fix
+= size
;
9818 fix_new (fragP
, old_fr_fix
, size
,
9820 fragP
->fr_offset
, 1,
9826 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
9828 /* Negate the condition, and branch past an
9829 unconditional jump. */
9832 /* Insert an unconditional jump. */
9834 /* We added two extra opcode bytes, and have a two byte
9836 fragP
->fr_fix
+= 2 + 2;
9837 fix_new (fragP
, old_fr_fix
+ 2, 2,
9839 fragP
->fr_offset
, 1,
9846 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
9851 fixP
= fix_new (fragP
, old_fr_fix
, 1,
9853 fragP
->fr_offset
, 1,
9855 fixP
->fx_signed
= 1;
9859 /* This changes the byte-displacement jump 0x7N
9860 to the (d)word-displacement jump 0x0f,0x8N. */
9861 opcode
[1] = opcode
[0] + 0x10;
9862 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
9863 /* We've added an opcode byte. */
9864 fragP
->fr_fix
+= 1 + size
;
9865 fix_new (fragP
, old_fr_fix
+ 1, size
,
9867 fragP
->fr_offset
, 1,
9872 BAD_CASE (fragP
->fr_subtype
);
9876 return fragP
->fr_fix
- old_fr_fix
;
9879 /* Guess size depending on current relax state. Initially the relax
9880 state will correspond to a short jump and we return 1, because
9881 the variable part of the frag (the branch offset) is one byte
9882 long. However, we can relax a section more than once and in that
9883 case we must either set fr_subtype back to the unrelaxed state,
9884 or return the value for the appropriate branch. */
9885 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
9888 /* Called after relax() is finished.
9890 In: Address of frag.
9891 fr_type == rs_machine_dependent.
9892 fr_subtype is what the address relaxed to.
9894 Out: Any fixSs and constants are set up.
9895 Caller will turn frag into a ".space 0". */
9898 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec ATTRIBUTE_UNUSED
,
9901 unsigned char *opcode
;
9902 unsigned char *where_to_put_displacement
= NULL
;
9903 offsetT target_address
;
9904 offsetT opcode_address
;
9905 unsigned int extension
= 0;
9906 offsetT displacement_from_opcode_start
;
9908 opcode
= (unsigned char *) fragP
->fr_opcode
;
9910 /* Address we want to reach in file space. */
9911 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
9913 /* Address opcode resides at in file space. */
9914 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
9916 /* Displacement from opcode start to fill into instruction. */
9917 displacement_from_opcode_start
= target_address
- opcode_address
;
9919 if ((fragP
->fr_subtype
& BIG
) == 0)
9921 /* Don't have to change opcode. */
9922 extension
= 1; /* 1 opcode + 1 displacement */
9923 where_to_put_displacement
= &opcode
[1];
9927 if (no_cond_jump_promotion
9928 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
9929 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
9930 _("long jump required"));
9932 switch (fragP
->fr_subtype
)
9934 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
9935 extension
= 4; /* 1 opcode + 4 displacement */
9937 where_to_put_displacement
= &opcode
[1];
9940 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
9941 extension
= 2; /* 1 opcode + 2 displacement */
9943 where_to_put_displacement
= &opcode
[1];
9946 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
9947 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
9948 extension
= 5; /* 2 opcode + 4 displacement */
9949 opcode
[1] = opcode
[0] + 0x10;
9950 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
9951 where_to_put_displacement
= &opcode
[2];
9954 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
9955 extension
= 3; /* 2 opcode + 2 displacement */
9956 opcode
[1] = opcode
[0] + 0x10;
9957 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
9958 where_to_put_displacement
= &opcode
[2];
9961 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
9966 where_to_put_displacement
= &opcode
[3];
9970 BAD_CASE (fragP
->fr_subtype
);
9975 /* If size if less then four we are sure that the operand fits,
9976 but if it's 4, then it could be that the displacement is larger
9978 if (DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
) == 4
9980 && ((addressT
) (displacement_from_opcode_start
- extension
9981 + ((addressT
) 1 << 31))
9982 > (((addressT
) 2 << 31) - 1)))
9984 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
9985 _("jump target out of range"));
9986 /* Make us emit 0. */
9987 displacement_from_opcode_start
= extension
;
9989 /* Now put displacement after opcode. */
9990 md_number_to_chars ((char *) where_to_put_displacement
,
9991 (valueT
) (displacement_from_opcode_start
- extension
),
9992 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
9993 fragP
->fr_fix
+= extension
;
9996 /* Apply a fixup (fixP) to segment data, once it has been determined
9997 by our caller that we have all the info we need to fix it up.
9999 Parameter valP is the pointer to the value of the bits.
10001 On the 386, immediates, displacements, and data pointers are all in
10002 the same (little-endian) format, so we don't need to care about which
10003 we are handling. */
10006 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
10008 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
10009 valueT value
= *valP
;
10011 #if !defined (TE_Mach)
10012 if (fixP
->fx_pcrel
)
10014 switch (fixP
->fx_r_type
)
10020 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
10023 case BFD_RELOC_X86_64_32S
:
10024 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
10027 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
10030 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
10035 if (fixP
->fx_addsy
!= NULL
10036 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
10037 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
10038 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
10039 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
10040 && !use_rela_relocations
)
10042 /* This is a hack. There should be a better way to handle this.
10043 This covers for the fact that bfd_install_relocation will
10044 subtract the current location (for partial_inplace, PC relative
10045 relocations); see more below. */
10049 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
10052 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
10054 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10057 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
10059 if ((sym_seg
== seg
10060 || (symbol_section_p (fixP
->fx_addsy
)
10061 && sym_seg
!= absolute_section
))
10062 && !generic_force_reloc (fixP
))
10064 /* Yes, we add the values in twice. This is because
10065 bfd_install_relocation subtracts them out again. I think
10066 bfd_install_relocation is broken, but I don't dare change
10068 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
10072 #if defined (OBJ_COFF) && defined (TE_PE)
10073 /* For some reason, the PE format does not store a
10074 section address offset for a PC relative symbol. */
10075 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
10076 || S_IS_WEAK (fixP
->fx_addsy
))
10077 value
+= md_pcrel_from (fixP
);
10080 #if defined (OBJ_COFF) && defined (TE_PE)
10081 if (fixP
->fx_addsy
!= NULL
10082 && S_IS_WEAK (fixP
->fx_addsy
)
10083 /* PR 16858: Do not modify weak function references. */
10084 && ! fixP
->fx_pcrel
)
10086 #if !defined (TE_PEP)
10087 /* For x86 PE weak function symbols are neither PC-relative
10088 nor do they set S_IS_FUNCTION. So the only reliable way
10089 to detect them is to check the flags of their containing
10091 if (S_GET_SEGMENT (fixP
->fx_addsy
) != NULL
10092 && S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_CODE
)
10096 value
-= S_GET_VALUE (fixP
->fx_addsy
);
10100 /* Fix a few things - the dynamic linker expects certain values here,
10101 and we must not disappoint it. */
10102 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10103 if (IS_ELF
&& fixP
->fx_addsy
)
10104 switch (fixP
->fx_r_type
)
10106 case BFD_RELOC_386_PLT32
:
10107 case BFD_RELOC_X86_64_PLT32
:
10108 /* Make the jump instruction point to the address of the operand. At
10109 runtime we merely add the offset to the actual PLT entry. */
10113 case BFD_RELOC_386_TLS_GD
:
10114 case BFD_RELOC_386_TLS_LDM
:
10115 case BFD_RELOC_386_TLS_IE_32
:
10116 case BFD_RELOC_386_TLS_IE
:
10117 case BFD_RELOC_386_TLS_GOTIE
:
10118 case BFD_RELOC_386_TLS_GOTDESC
:
10119 case BFD_RELOC_X86_64_TLSGD
:
10120 case BFD_RELOC_X86_64_TLSLD
:
10121 case BFD_RELOC_X86_64_GOTTPOFF
:
10122 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
10123 value
= 0; /* Fully resolved at runtime. No addend. */
10125 case BFD_RELOC_386_TLS_LE
:
10126 case BFD_RELOC_386_TLS_LDO_32
:
10127 case BFD_RELOC_386_TLS_LE_32
:
10128 case BFD_RELOC_X86_64_DTPOFF32
:
10129 case BFD_RELOC_X86_64_DTPOFF64
:
10130 case BFD_RELOC_X86_64_TPOFF32
:
10131 case BFD_RELOC_X86_64_TPOFF64
:
10132 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
10135 case BFD_RELOC_386_TLS_DESC_CALL
:
10136 case BFD_RELOC_X86_64_TLSDESC_CALL
:
10137 value
= 0; /* Fully resolved at runtime. No addend. */
10138 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
10142 case BFD_RELOC_VTABLE_INHERIT
:
10143 case BFD_RELOC_VTABLE_ENTRY
:
10150 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
10152 #endif /* !defined (TE_Mach) */
10154 /* Are we finished with this relocation now? */
10155 if (fixP
->fx_addsy
== NULL
)
10157 #if defined (OBJ_COFF) && defined (TE_PE)
10158 else if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
10161 /* Remember value for tc_gen_reloc. */
10162 fixP
->fx_addnumber
= value
;
10163 /* Clear out the frag for now. */
10167 else if (use_rela_relocations
)
10169 fixP
->fx_no_overflow
= 1;
10170 /* Remember value for tc_gen_reloc. */
10171 fixP
->fx_addnumber
= value
;
10175 md_number_to_chars (p
, value
, fixP
->fx_size
);
10179 md_atof (int type
, char *litP
, int *sizeP
)
10181 /* This outputs the LITTLENUMs in REVERSE order;
10182 in accord with the bigendian 386. */
10183 return ieee_md_atof (type
, litP
, sizeP
, FALSE
);
10186 static char output_invalid_buf
[sizeof (unsigned char) * 2 + 6];
10189 output_invalid (int c
)
10192 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
10195 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
10196 "(0x%x)", (unsigned char) c
);
10197 return output_invalid_buf
;
10200 /* REG_STRING starts *before* REGISTER_PREFIX. */
10202 static const reg_entry
*
10203 parse_real_register (char *reg_string
, char **end_op
)
10205 char *s
= reg_string
;
10207 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
10208 const reg_entry
*r
;
10210 /* Skip possible REGISTER_PREFIX and possible whitespace. */
10211 if (*s
== REGISTER_PREFIX
)
10214 if (is_space_char (*s
))
10217 p
= reg_name_given
;
10218 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
10220 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
10221 return (const reg_entry
*) NULL
;
10225 /* For naked regs, make sure that we are not dealing with an identifier.
10226 This prevents confusing an identifier like `eax_var' with register
10228 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
10229 return (const reg_entry
*) NULL
;
10233 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
10235 /* Handle floating point regs, allowing spaces in the (i) part. */
10236 if (r
== i386_regtab
/* %st is first entry of table */)
10238 if (!cpu_arch_flags
.bitfield
.cpu8087
10239 && !cpu_arch_flags
.bitfield
.cpu287
10240 && !cpu_arch_flags
.bitfield
.cpu387
)
10241 return (const reg_entry
*) NULL
;
10243 if (is_space_char (*s
))
10248 if (is_space_char (*s
))
10250 if (*s
>= '0' && *s
<= '7')
10252 int fpr
= *s
- '0';
10254 if (is_space_char (*s
))
10259 r
= (const reg_entry
*) hash_find (reg_hash
, "st(0)");
10264 /* We have "%st(" then garbage. */
10265 return (const reg_entry
*) NULL
;
10269 if (r
== NULL
|| allow_pseudo_reg
)
10272 if (operand_type_all_zero (&r
->reg_type
))
10273 return (const reg_entry
*) NULL
;
10275 if ((r
->reg_type
.bitfield
.dword
10276 || r
->reg_type
.bitfield
.sreg3
10277 || r
->reg_type
.bitfield
.control
10278 || r
->reg_type
.bitfield
.debug
10279 || r
->reg_type
.bitfield
.test
)
10280 && !cpu_arch_flags
.bitfield
.cpui386
)
10281 return (const reg_entry
*) NULL
;
10283 if (r
->reg_type
.bitfield
.regmmx
&& !cpu_arch_flags
.bitfield
.cpummx
)
10284 return (const reg_entry
*) NULL
;
10286 if (!cpu_arch_flags
.bitfield
.cpuavx512f
)
10288 if (r
->reg_type
.bitfield
.zmmword
|| r
->reg_type
.bitfield
.regmask
)
10289 return (const reg_entry
*) NULL
;
10291 if (!cpu_arch_flags
.bitfield
.cpuavx
)
10293 if (r
->reg_type
.bitfield
.ymmword
)
10294 return (const reg_entry
*) NULL
;
10296 if (!cpu_arch_flags
.bitfield
.cpusse
&& r
->reg_type
.bitfield
.xmmword
)
10297 return (const reg_entry
*) NULL
;
10301 if (r
->reg_type
.bitfield
.regbnd
&& !cpu_arch_flags
.bitfield
.cpumpx
)
10302 return (const reg_entry
*) NULL
;
10304 /* Don't allow fake index register unless allow_index_reg isn't 0. */
10305 if (!allow_index_reg
10306 && (r
->reg_num
== RegEiz
|| r
->reg_num
== RegRiz
))
10307 return (const reg_entry
*) NULL
;
10309 /* Upper 16 vector registers are only available with VREX in 64bit
10310 mode, and require EVEX encoding. */
10311 if (r
->reg_flags
& RegVRex
)
10313 if (!cpu_arch_flags
.bitfield
.cpuvrex
10314 || flag_code
!= CODE_64BIT
)
10315 return (const reg_entry
*) NULL
;
10317 i
.vec_encoding
= vex_encoding_evex
;
10320 if (((r
->reg_flags
& (RegRex64
| RegRex
)) || r
->reg_type
.bitfield
.qword
)
10321 && (!cpu_arch_flags
.bitfield
.cpulm
|| !r
->reg_type
.bitfield
.control
)
10322 && flag_code
!= CODE_64BIT
)
10323 return (const reg_entry
*) NULL
;
10325 if (r
->reg_type
.bitfield
.sreg3
&& r
->reg_num
== RegFlat
&& !intel_syntax
)
10326 return (const reg_entry
*) NULL
;
10331 /* REG_STRING starts *before* REGISTER_PREFIX. */
10333 static const reg_entry
*
10334 parse_register (char *reg_string
, char **end_op
)
10336 const reg_entry
*r
;
10338 if (*reg_string
== REGISTER_PREFIX
|| allow_naked_reg
)
10339 r
= parse_real_register (reg_string
, end_op
);
10344 char *save
= input_line_pointer
;
10348 input_line_pointer
= reg_string
;
10349 c
= get_symbol_name (®_string
);
10350 symbolP
= symbol_find (reg_string
);
10351 if (symbolP
&& S_GET_SEGMENT (symbolP
) == reg_section
)
10353 const expressionS
*e
= symbol_get_value_expression (symbolP
);
10355 know (e
->X_op
== O_register
);
10356 know (e
->X_add_number
>= 0
10357 && (valueT
) e
->X_add_number
< i386_regtab_size
);
10358 r
= i386_regtab
+ e
->X_add_number
;
10359 if ((r
->reg_flags
& RegVRex
))
10360 i
.vec_encoding
= vex_encoding_evex
;
10361 *end_op
= input_line_pointer
;
10363 *input_line_pointer
= c
;
10364 input_line_pointer
= save
;
10370 i386_parse_name (char *name
, expressionS
*e
, char *nextcharP
)
10372 const reg_entry
*r
;
10373 char *end
= input_line_pointer
;
10376 r
= parse_register (name
, &input_line_pointer
);
10377 if (r
&& end
<= input_line_pointer
)
10379 *nextcharP
= *input_line_pointer
;
10380 *input_line_pointer
= 0;
10381 e
->X_op
= O_register
;
10382 e
->X_add_number
= r
- i386_regtab
;
10385 input_line_pointer
= end
;
10387 return intel_syntax
? i386_intel_parse_name (name
, e
) : 0;
10391 md_operand (expressionS
*e
)
10394 const reg_entry
*r
;
10396 switch (*input_line_pointer
)
10398 case REGISTER_PREFIX
:
10399 r
= parse_real_register (input_line_pointer
, &end
);
10402 e
->X_op
= O_register
;
10403 e
->X_add_number
= r
- i386_regtab
;
10404 input_line_pointer
= end
;
10409 gas_assert (intel_syntax
);
10410 end
= input_line_pointer
++;
10412 if (*input_line_pointer
== ']')
10414 ++input_line_pointer
;
10415 e
->X_op_symbol
= make_expr_symbol (e
);
10416 e
->X_add_symbol
= NULL
;
10417 e
->X_add_number
= 0;
10422 e
->X_op
= O_absent
;
10423 input_line_pointer
= end
;
10430 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10431 const char *md_shortopts
= "kVQ:sqnO::";
10433 const char *md_shortopts
= "qnO::";
10436 #define OPTION_32 (OPTION_MD_BASE + 0)
10437 #define OPTION_64 (OPTION_MD_BASE + 1)
10438 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
10439 #define OPTION_MARCH (OPTION_MD_BASE + 3)
10440 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
10441 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
10442 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
10443 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
10444 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
10445 #define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 9)
10446 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
10447 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
10448 #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
10449 #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
10450 #define OPTION_X32 (OPTION_MD_BASE + 14)
10451 #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
10452 #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
10453 #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
10454 #define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
10455 #define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
10456 #define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
10457 #define OPTION_MSHARED (OPTION_MD_BASE + 21)
10458 #define OPTION_MAMD64 (OPTION_MD_BASE + 22)
10459 #define OPTION_MINTEL64 (OPTION_MD_BASE + 23)
10460 #define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24)
10462 struct option md_longopts
[] =
10464 {"32", no_argument
, NULL
, OPTION_32
},
10465 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10466 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
10467 {"64", no_argument
, NULL
, OPTION_64
},
10469 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10470 {"x32", no_argument
, NULL
, OPTION_X32
},
10471 {"mshared", no_argument
, NULL
, OPTION_MSHARED
},
10473 {"divide", no_argument
, NULL
, OPTION_DIVIDE
},
10474 {"march", required_argument
, NULL
, OPTION_MARCH
},
10475 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
10476 {"mmnemonic", required_argument
, NULL
, OPTION_MMNEMONIC
},
10477 {"msyntax", required_argument
, NULL
, OPTION_MSYNTAX
},
10478 {"mindex-reg", no_argument
, NULL
, OPTION_MINDEX_REG
},
10479 {"mnaked-reg", no_argument
, NULL
, OPTION_MNAKED_REG
},
10480 {"msse2avx", no_argument
, NULL
, OPTION_MSSE2AVX
},
10481 {"msse-check", required_argument
, NULL
, OPTION_MSSE_CHECK
},
10482 {"moperand-check", required_argument
, NULL
, OPTION_MOPERAND_CHECK
},
10483 {"mavxscalar", required_argument
, NULL
, OPTION_MAVXSCALAR
},
10484 {"madd-bnd-prefix", no_argument
, NULL
, OPTION_MADD_BND_PREFIX
},
10485 {"mevexlig", required_argument
, NULL
, OPTION_MEVEXLIG
},
10486 {"mevexwig", required_argument
, NULL
, OPTION_MEVEXWIG
},
10487 # if defined (TE_PE) || defined (TE_PEP)
10488 {"mbig-obj", no_argument
, NULL
, OPTION_MBIG_OBJ
},
10490 {"momit-lock-prefix", required_argument
, NULL
, OPTION_MOMIT_LOCK_PREFIX
},
10491 {"mfence-as-lock-add", required_argument
, NULL
, OPTION_MFENCE_AS_LOCK_ADD
},
10492 {"mrelax-relocations", required_argument
, NULL
, OPTION_MRELAX_RELOCATIONS
},
10493 {"mevexrcig", required_argument
, NULL
, OPTION_MEVEXRCIG
},
10494 {"mamd64", no_argument
, NULL
, OPTION_MAMD64
},
10495 {"mintel64", no_argument
, NULL
, OPTION_MINTEL64
},
10496 {NULL
, no_argument
, NULL
, 0}
10498 size_t md_longopts_size
= sizeof (md_longopts
);
10501 md_parse_option (int c
, const char *arg
)
10504 char *arch
, *next
, *saved
;
10509 optimize_align_code
= 0;
10513 quiet_warnings
= 1;
10516 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10517 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
10518 should be emitted or not. FIXME: Not implemented. */
10522 /* -V: SVR4 argument to print version ID. */
10524 print_version_id ();
10527 /* -k: Ignore for FreeBSD compatibility. */
10532 /* -s: On i386 Solaris, this tells the native assembler to use
10533 .stab instead of .stab.excl. We always use .stab anyhow. */
10536 case OPTION_MSHARED
:
10540 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10541 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
10544 const char **list
, **l
;
10546 list
= bfd_target_list ();
10547 for (l
= list
; *l
!= NULL
; l
++)
10548 if (CONST_STRNEQ (*l
, "elf64-x86-64")
10549 || strcmp (*l
, "coff-x86-64") == 0
10550 || strcmp (*l
, "pe-x86-64") == 0
10551 || strcmp (*l
, "pei-x86-64") == 0
10552 || strcmp (*l
, "mach-o-x86-64") == 0)
10554 default_arch
= "x86_64";
10558 as_fatal (_("no compiled in support for x86_64"));
10564 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10568 const char **list
, **l
;
10570 list
= bfd_target_list ();
10571 for (l
= list
; *l
!= NULL
; l
++)
10572 if (CONST_STRNEQ (*l
, "elf32-x86-64"))
10574 default_arch
= "x86_64:32";
10578 as_fatal (_("no compiled in support for 32bit x86_64"));
10582 as_fatal (_("32bit x86_64 is only supported for ELF"));
10587 default_arch
= "i386";
10590 case OPTION_DIVIDE
:
10591 #ifdef SVR4_COMMENT_CHARS
10596 n
= XNEWVEC (char, strlen (i386_comment_chars
) + 1);
10598 for (s
= i386_comment_chars
; *s
!= '\0'; s
++)
10602 i386_comment_chars
= n
;
10608 saved
= xstrdup (arg
);
10610 /* Allow -march=+nosse. */
10616 as_fatal (_("invalid -march= option: `%s'"), arg
);
10617 next
= strchr (arch
, '+');
10620 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
10622 if (strcmp (arch
, cpu_arch
[j
].name
) == 0)
10625 if (! cpu_arch
[j
].flags
.bitfield
.cpui386
)
10628 cpu_arch_name
= cpu_arch
[j
].name
;
10629 cpu_sub_arch_name
= NULL
;
10630 cpu_arch_flags
= cpu_arch
[j
].flags
;
10631 cpu_arch_isa
= cpu_arch
[j
].type
;
10632 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
10633 if (!cpu_arch_tune_set
)
10635 cpu_arch_tune
= cpu_arch_isa
;
10636 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
10640 else if (*cpu_arch
[j
].name
== '.'
10641 && strcmp (arch
, cpu_arch
[j
].name
+ 1) == 0)
10643 /* ISA extension. */
10644 i386_cpu_flags flags
;
10646 flags
= cpu_flags_or (cpu_arch_flags
,
10647 cpu_arch
[j
].flags
);
10649 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
10651 if (cpu_sub_arch_name
)
10653 char *name
= cpu_sub_arch_name
;
10654 cpu_sub_arch_name
= concat (name
,
10656 (const char *) NULL
);
10660 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
10661 cpu_arch_flags
= flags
;
10662 cpu_arch_isa_flags
= flags
;
10666 = cpu_flags_or (cpu_arch_isa_flags
,
10667 cpu_arch
[j
].flags
);
10672 if (j
>= ARRAY_SIZE (cpu_arch
))
10674 /* Disable an ISA extension. */
10675 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
10676 if (strcmp (arch
, cpu_noarch
[j
].name
) == 0)
10678 i386_cpu_flags flags
;
10680 flags
= cpu_flags_and_not (cpu_arch_flags
,
10681 cpu_noarch
[j
].flags
);
10682 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
10684 if (cpu_sub_arch_name
)
10686 char *name
= cpu_sub_arch_name
;
10687 cpu_sub_arch_name
= concat (arch
,
10688 (const char *) NULL
);
10692 cpu_sub_arch_name
= xstrdup (arch
);
10693 cpu_arch_flags
= flags
;
10694 cpu_arch_isa_flags
= flags
;
10699 if (j
>= ARRAY_SIZE (cpu_noarch
))
10700 j
= ARRAY_SIZE (cpu_arch
);
10703 if (j
>= ARRAY_SIZE (cpu_arch
))
10704 as_fatal (_("invalid -march= option: `%s'"), arg
);
10708 while (next
!= NULL
);
10714 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
10715 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
10717 if (strcmp (arg
, cpu_arch
[j
].name
) == 0)
10719 cpu_arch_tune_set
= 1;
10720 cpu_arch_tune
= cpu_arch
[j
].type
;
10721 cpu_arch_tune_flags
= cpu_arch
[j
].flags
;
10725 if (j
>= ARRAY_SIZE (cpu_arch
))
10726 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
10729 case OPTION_MMNEMONIC
:
10730 if (strcasecmp (arg
, "att") == 0)
10731 intel_mnemonic
= 0;
10732 else if (strcasecmp (arg
, "intel") == 0)
10733 intel_mnemonic
= 1;
10735 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg
);
10738 case OPTION_MSYNTAX
:
10739 if (strcasecmp (arg
, "att") == 0)
10741 else if (strcasecmp (arg
, "intel") == 0)
10744 as_fatal (_("invalid -msyntax= option: `%s'"), arg
);
10747 case OPTION_MINDEX_REG
:
10748 allow_index_reg
= 1;
10751 case OPTION_MNAKED_REG
:
10752 allow_naked_reg
= 1;
10755 case OPTION_MSSE2AVX
:
10759 case OPTION_MSSE_CHECK
:
10760 if (strcasecmp (arg
, "error") == 0)
10761 sse_check
= check_error
;
10762 else if (strcasecmp (arg
, "warning") == 0)
10763 sse_check
= check_warning
;
10764 else if (strcasecmp (arg
, "none") == 0)
10765 sse_check
= check_none
;
10767 as_fatal (_("invalid -msse-check= option: `%s'"), arg
);
10770 case OPTION_MOPERAND_CHECK
:
10771 if (strcasecmp (arg
, "error") == 0)
10772 operand_check
= check_error
;
10773 else if (strcasecmp (arg
, "warning") == 0)
10774 operand_check
= check_warning
;
10775 else if (strcasecmp (arg
, "none") == 0)
10776 operand_check
= check_none
;
10778 as_fatal (_("invalid -moperand-check= option: `%s'"), arg
);
10781 case OPTION_MAVXSCALAR
:
10782 if (strcasecmp (arg
, "128") == 0)
10783 avxscalar
= vex128
;
10784 else if (strcasecmp (arg
, "256") == 0)
10785 avxscalar
= vex256
;
10787 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg
);
10790 case OPTION_MADD_BND_PREFIX
:
10791 add_bnd_prefix
= 1;
10794 case OPTION_MEVEXLIG
:
10795 if (strcmp (arg
, "128") == 0)
10796 evexlig
= evexl128
;
10797 else if (strcmp (arg
, "256") == 0)
10798 evexlig
= evexl256
;
10799 else if (strcmp (arg
, "512") == 0)
10800 evexlig
= evexl512
;
10802 as_fatal (_("invalid -mevexlig= option: `%s'"), arg
);
10805 case OPTION_MEVEXRCIG
:
10806 if (strcmp (arg
, "rne") == 0)
10808 else if (strcmp (arg
, "rd") == 0)
10810 else if (strcmp (arg
, "ru") == 0)
10812 else if (strcmp (arg
, "rz") == 0)
10815 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg
);
10818 case OPTION_MEVEXWIG
:
10819 if (strcmp (arg
, "0") == 0)
10821 else if (strcmp (arg
, "1") == 0)
10824 as_fatal (_("invalid -mevexwig= option: `%s'"), arg
);
10827 # if defined (TE_PE) || defined (TE_PEP)
10828 case OPTION_MBIG_OBJ
:
10833 case OPTION_MOMIT_LOCK_PREFIX
:
10834 if (strcasecmp (arg
, "yes") == 0)
10835 omit_lock_prefix
= 1;
10836 else if (strcasecmp (arg
, "no") == 0)
10837 omit_lock_prefix
= 0;
10839 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg
);
10842 case OPTION_MFENCE_AS_LOCK_ADD
:
10843 if (strcasecmp (arg
, "yes") == 0)
10845 else if (strcasecmp (arg
, "no") == 0)
10848 as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg
);
10851 case OPTION_MRELAX_RELOCATIONS
:
10852 if (strcasecmp (arg
, "yes") == 0)
10853 generate_relax_relocations
= 1;
10854 else if (strcasecmp (arg
, "no") == 0)
10855 generate_relax_relocations
= 0;
10857 as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg
);
10860 case OPTION_MAMD64
:
10864 case OPTION_MINTEL64
:
10872 /* Turn off -Os. */
10873 optimize_for_space
= 0;
10875 else if (*arg
== 's')
10877 optimize_for_space
= 1;
10878 /* Turn on all encoding optimizations. */
10883 optimize
= atoi (arg
);
10884 /* Turn off -Os. */
10885 optimize_for_space
= 0;
10895 #define MESSAGE_TEMPLATE \
10899 output_message (FILE *stream
, char *p
, char *message
, char *start
,
10900 int *left_p
, const char *name
, int len
)
10902 int size
= sizeof (MESSAGE_TEMPLATE
);
10903 int left
= *left_p
;
10905 /* Reserve 2 spaces for ", " or ",\0" */
10908 /* Check if there is any room. */
10916 p
= mempcpy (p
, name
, len
);
10920 /* Output the current message now and start a new one. */
10923 fprintf (stream
, "%s\n", message
);
10925 left
= size
- (start
- message
) - len
- 2;
10927 gas_assert (left
>= 0);
10929 p
= mempcpy (p
, name
, len
);
10937 show_arch (FILE *stream
, int ext
, int check
)
10939 static char message
[] = MESSAGE_TEMPLATE
;
10940 char *start
= message
+ 27;
10942 int size
= sizeof (MESSAGE_TEMPLATE
);
10949 left
= size
- (start
- message
);
10950 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
10952 /* Should it be skipped? */
10953 if (cpu_arch
[j
].skip
)
10956 name
= cpu_arch
[j
].name
;
10957 len
= cpu_arch
[j
].len
;
10960 /* It is an extension. Skip if we aren't asked to show it. */
10971 /* It is an processor. Skip if we show only extension. */
10974 else if (check
&& ! cpu_arch
[j
].flags
.bitfield
.cpui386
)
10976 /* It is an impossible processor - skip. */
10980 p
= output_message (stream
, p
, message
, start
, &left
, name
, len
);
10983 /* Display disabled extensions. */
10985 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
10987 name
= cpu_noarch
[j
].name
;
10988 len
= cpu_noarch
[j
].len
;
10989 p
= output_message (stream
, p
, message
, start
, &left
, name
,
10994 fprintf (stream
, "%s\n", message
);
10998 md_show_usage (FILE *stream
)
11000 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11001 fprintf (stream
, _("\
11003 -V print assembler version number\n\
11006 fprintf (stream
, _("\
11007 -n Do not optimize code alignment\n\
11008 -q quieten some warnings\n"));
11009 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11010 fprintf (stream
, _("\
11013 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
11014 || defined (TE_PE) || defined (TE_PEP))
11015 fprintf (stream
, _("\
11016 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
11018 #ifdef SVR4_COMMENT_CHARS
11019 fprintf (stream
, _("\
11020 --divide do not treat `/' as a comment character\n"));
11022 fprintf (stream
, _("\
11023 --divide ignored\n"));
11025 fprintf (stream
, _("\
11026 -march=CPU[,+EXTENSION...]\n\
11027 generate code for CPU and EXTENSION, CPU is one of:\n"));
11028 show_arch (stream
, 0, 1);
11029 fprintf (stream
, _("\
11030 EXTENSION is combination of:\n"));
11031 show_arch (stream
, 1, 0);
11032 fprintf (stream
, _("\
11033 -mtune=CPU optimize for CPU, CPU is one of:\n"));
11034 show_arch (stream
, 0, 0);
11035 fprintf (stream
, _("\
11036 -msse2avx encode SSE instructions with VEX prefix\n"));
11037 fprintf (stream
, _("\
11038 -msse-check=[none|error|warning]\n\
11039 check SSE instructions\n"));
11040 fprintf (stream
, _("\
11041 -moperand-check=[none|error|warning]\n\
11042 check operand combinations for validity\n"));
11043 fprintf (stream
, _("\
11044 -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n\
11046 fprintf (stream
, _("\
11047 -mevexlig=[128|256|512] encode scalar EVEX instructions with specific vector\n\
11049 fprintf (stream
, _("\
11050 -mevexwig=[0|1] encode EVEX instructions with specific EVEX.W value\n\
11051 for EVEX.W bit ignored instructions\n"));
11052 fprintf (stream
, _("\
11053 -mevexrcig=[rne|rd|ru|rz]\n\
11054 encode EVEX instructions with specific EVEX.RC value\n\
11055 for SAE-only ignored instructions\n"));
11056 fprintf (stream
, _("\
11057 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
11058 fprintf (stream
, _("\
11059 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
11060 fprintf (stream
, _("\
11061 -mindex-reg support pseudo index registers\n"));
11062 fprintf (stream
, _("\
11063 -mnaked-reg don't require `%%' prefix for registers\n"));
11064 fprintf (stream
, _("\
11065 -madd-bnd-prefix add BND prefix for all valid branches\n"));
11066 fprintf (stream
, _("\
11067 -mshared disable branch optimization for shared code\n"));
11068 # if defined (TE_PE) || defined (TE_PEP)
11069 fprintf (stream
, _("\
11070 -mbig-obj generate big object files\n"));
11072 fprintf (stream
, _("\
11073 -momit-lock-prefix=[no|yes]\n\
11074 strip all lock prefixes\n"));
11075 fprintf (stream
, _("\
11076 -mfence-as-lock-add=[no|yes]\n\
11077 encode lfence, mfence and sfence as\n\
11078 lock addl $0x0, (%%{re}sp)\n"));
11079 fprintf (stream
, _("\
11080 -mrelax-relocations=[no|yes]\n\
11081 generate relax relocations\n"));
11082 fprintf (stream
, _("\
11083 -mamd64 accept only AMD64 ISA\n"));
11084 fprintf (stream
, _("\
11085 -mintel64 accept only Intel64 ISA\n"));
11088 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
11089 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
11090 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
11092 /* Pick the target format to use. */
11095 i386_target_format (void)
11097 if (!strncmp (default_arch
, "x86_64", 6))
11099 update_code_flag (CODE_64BIT
, 1);
11100 if (default_arch
[6] == '\0')
11101 x86_elf_abi
= X86_64_ABI
;
11103 x86_elf_abi
= X86_64_X32_ABI
;
11105 else if (!strcmp (default_arch
, "i386"))
11106 update_code_flag (CODE_32BIT
, 1);
11107 else if (!strcmp (default_arch
, "iamcu"))
11109 update_code_flag (CODE_32BIT
, 1);
11110 if (cpu_arch_isa
== PROCESSOR_UNKNOWN
)
11112 static const i386_cpu_flags iamcu_flags
= CPU_IAMCU_FLAGS
;
11113 cpu_arch_name
= "iamcu";
11114 cpu_sub_arch_name
= NULL
;
11115 cpu_arch_flags
= iamcu_flags
;
11116 cpu_arch_isa
= PROCESSOR_IAMCU
;
11117 cpu_arch_isa_flags
= iamcu_flags
;
11118 if (!cpu_arch_tune_set
)
11120 cpu_arch_tune
= cpu_arch_isa
;
11121 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
11124 else if (cpu_arch_isa
!= PROCESSOR_IAMCU
)
11125 as_fatal (_("Intel MCU doesn't support `%s' architecture"),
11129 as_fatal (_("unknown architecture"));
11131 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
11132 cpu_arch_isa_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
11133 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
11134 cpu_arch_tune_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
11136 switch (OUTPUT_FLAVOR
)
11138 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
11139 case bfd_target_aout_flavour
:
11140 return AOUT_TARGET_FORMAT
;
11142 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
11143 # if defined (TE_PE) || defined (TE_PEP)
11144 case bfd_target_coff_flavour
:
11145 if (flag_code
== CODE_64BIT
)
11146 return use_big_obj
? "pe-bigobj-x86-64" : "pe-x86-64";
11149 # elif defined (TE_GO32)
11150 case bfd_target_coff_flavour
:
11151 return "coff-go32";
11153 case bfd_target_coff_flavour
:
11154 return "coff-i386";
11157 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
11158 case bfd_target_elf_flavour
:
11160 const char *format
;
11162 switch (x86_elf_abi
)
11165 format
= ELF_TARGET_FORMAT
;
11168 use_rela_relocations
= 1;
11170 format
= ELF_TARGET_FORMAT64
;
11172 case X86_64_X32_ABI
:
11173 use_rela_relocations
= 1;
11175 disallow_64bit_reloc
= 1;
11176 format
= ELF_TARGET_FORMAT32
;
11179 if (cpu_arch_isa
== PROCESSOR_L1OM
)
11181 if (x86_elf_abi
!= X86_64_ABI
)
11182 as_fatal (_("Intel L1OM is 64bit only"));
11183 return ELF_TARGET_L1OM_FORMAT
;
11185 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
11187 if (x86_elf_abi
!= X86_64_ABI
)
11188 as_fatal (_("Intel K1OM is 64bit only"));
11189 return ELF_TARGET_K1OM_FORMAT
;
11191 else if (cpu_arch_isa
== PROCESSOR_IAMCU
)
11193 if (x86_elf_abi
!= I386_ABI
)
11194 as_fatal (_("Intel MCU is 32bit only"));
11195 return ELF_TARGET_IAMCU_FORMAT
;
11201 #if defined (OBJ_MACH_O)
11202 case bfd_target_mach_o_flavour
:
11203 if (flag_code
== CODE_64BIT
)
11205 use_rela_relocations
= 1;
11207 return "mach-o-x86-64";
11210 return "mach-o-i386";
11218 #endif /* OBJ_MAYBE_ more than one */
11221 md_undefined_symbol (char *name
)
11223 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
11224 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
11225 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
11226 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
11230 if (symbol_find (name
))
11231 as_bad (_("GOT already in symbol table"));
11232 GOT_symbol
= symbol_new (name
, undefined_section
,
11233 (valueT
) 0, &zero_address_frag
);
11240 /* Round up a section size to the appropriate boundary. */
11243 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
11245 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
11246 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
11248 /* For a.out, force the section size to be aligned. If we don't do
11249 this, BFD will align it for us, but it will not write out the
11250 final bytes of the section. This may be a bug in BFD, but it is
11251 easier to fix it here since that is how the other a.out targets
11255 align
= bfd_get_section_alignment (stdoutput
, segment
);
11256 size
= ((size
+ (1 << align
) - 1) & (-((valueT
) 1 << align
)));
11263 /* On the i386, PC-relative offsets are relative to the start of the
11264 next instruction. That is, the address of the offset, plus its
11265 size, since the offset is always the last part of the insn. */
11268 md_pcrel_from (fixS
*fixP
)
11270 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
11276 s_bss (int ignore ATTRIBUTE_UNUSED
)
11280 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11282 obj_elf_section_change_hook ();
11284 temp
= get_absolute_expression ();
11285 subseg_set (bss_section
, (subsegT
) temp
);
11286 demand_empty_rest_of_line ();
11292 i386_validate_fix (fixS
*fixp
)
11294 if (fixp
->fx_subsy
)
11296 if (fixp
->fx_subsy
== GOT_symbol
)
11298 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
11302 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11303 if (fixp
->fx_tcbit2
)
11304 fixp
->fx_r_type
= (fixp
->fx_tcbit
11305 ? BFD_RELOC_X86_64_REX_GOTPCRELX
11306 : BFD_RELOC_X86_64_GOTPCRELX
);
11309 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
11314 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
11316 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
11318 fixp
->fx_subsy
= 0;
11321 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11322 else if (!object_64bit
)
11324 if (fixp
->fx_r_type
== BFD_RELOC_386_GOT32
11325 && fixp
->fx_tcbit2
)
11326 fixp
->fx_r_type
= BFD_RELOC_386_GOT32X
;
11332 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
11335 bfd_reloc_code_real_type code
;
11337 switch (fixp
->fx_r_type
)
11339 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11340 case BFD_RELOC_SIZE32
:
11341 case BFD_RELOC_SIZE64
:
11342 if (S_IS_DEFINED (fixp
->fx_addsy
)
11343 && !S_IS_EXTERNAL (fixp
->fx_addsy
))
11345 /* Resolve size relocation against local symbol to size of
11346 the symbol plus addend. */
11347 valueT value
= S_GET_SIZE (fixp
->fx_addsy
) + fixp
->fx_offset
;
11348 if (fixp
->fx_r_type
== BFD_RELOC_SIZE32
11349 && !fits_in_unsigned_long (value
))
11350 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
11351 _("symbol size computation overflow"));
11352 fixp
->fx_addsy
= NULL
;
11353 fixp
->fx_subsy
= NULL
;
11354 md_apply_fix (fixp
, (valueT
*) &value
, NULL
);
11358 /* Fall through. */
11360 case BFD_RELOC_X86_64_PLT32
:
11361 case BFD_RELOC_X86_64_GOT32
:
11362 case BFD_RELOC_X86_64_GOTPCREL
:
11363 case BFD_RELOC_X86_64_GOTPCRELX
:
11364 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
11365 case BFD_RELOC_386_PLT32
:
11366 case BFD_RELOC_386_GOT32
:
11367 case BFD_RELOC_386_GOT32X
:
11368 case BFD_RELOC_386_GOTOFF
:
11369 case BFD_RELOC_386_GOTPC
:
11370 case BFD_RELOC_386_TLS_GD
:
11371 case BFD_RELOC_386_TLS_LDM
:
11372 case BFD_RELOC_386_TLS_LDO_32
:
11373 case BFD_RELOC_386_TLS_IE_32
:
11374 case BFD_RELOC_386_TLS_IE
:
11375 case BFD_RELOC_386_TLS_GOTIE
:
11376 case BFD_RELOC_386_TLS_LE_32
:
11377 case BFD_RELOC_386_TLS_LE
:
11378 case BFD_RELOC_386_TLS_GOTDESC
:
11379 case BFD_RELOC_386_TLS_DESC_CALL
:
11380 case BFD_RELOC_X86_64_TLSGD
:
11381 case BFD_RELOC_X86_64_TLSLD
:
11382 case BFD_RELOC_X86_64_DTPOFF32
:
11383 case BFD_RELOC_X86_64_DTPOFF64
:
11384 case BFD_RELOC_X86_64_GOTTPOFF
:
11385 case BFD_RELOC_X86_64_TPOFF32
:
11386 case BFD_RELOC_X86_64_TPOFF64
:
11387 case BFD_RELOC_X86_64_GOTOFF64
:
11388 case BFD_RELOC_X86_64_GOTPC32
:
11389 case BFD_RELOC_X86_64_GOT64
:
11390 case BFD_RELOC_X86_64_GOTPCREL64
:
11391 case BFD_RELOC_X86_64_GOTPC64
:
11392 case BFD_RELOC_X86_64_GOTPLT64
:
11393 case BFD_RELOC_X86_64_PLTOFF64
:
11394 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
11395 case BFD_RELOC_X86_64_TLSDESC_CALL
:
11396 case BFD_RELOC_RVA
:
11397 case BFD_RELOC_VTABLE_ENTRY
:
11398 case BFD_RELOC_VTABLE_INHERIT
:
11400 case BFD_RELOC_32_SECREL
:
11402 code
= fixp
->fx_r_type
;
11404 case BFD_RELOC_X86_64_32S
:
11405 if (!fixp
->fx_pcrel
)
11407 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
11408 code
= fixp
->fx_r_type
;
11411 /* Fall through. */
11413 if (fixp
->fx_pcrel
)
11415 switch (fixp
->fx_size
)
11418 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
11419 _("can not do %d byte pc-relative relocation"),
11421 code
= BFD_RELOC_32_PCREL
;
11423 case 1: code
= BFD_RELOC_8_PCREL
; break;
11424 case 2: code
= BFD_RELOC_16_PCREL
; break;
11425 case 4: code
= BFD_RELOC_32_PCREL
; break;
11427 case 8: code
= BFD_RELOC_64_PCREL
; break;
11433 switch (fixp
->fx_size
)
11436 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
11437 _("can not do %d byte relocation"),
11439 code
= BFD_RELOC_32
;
11441 case 1: code
= BFD_RELOC_8
; break;
11442 case 2: code
= BFD_RELOC_16
; break;
11443 case 4: code
= BFD_RELOC_32
; break;
11445 case 8: code
= BFD_RELOC_64
; break;
11452 if ((code
== BFD_RELOC_32
11453 || code
== BFD_RELOC_32_PCREL
11454 || code
== BFD_RELOC_X86_64_32S
)
11456 && fixp
->fx_addsy
== GOT_symbol
)
11459 code
= BFD_RELOC_386_GOTPC
;
11461 code
= BFD_RELOC_X86_64_GOTPC32
;
11463 if ((code
== BFD_RELOC_64
|| code
== BFD_RELOC_64_PCREL
)
11465 && fixp
->fx_addsy
== GOT_symbol
)
11467 code
= BFD_RELOC_X86_64_GOTPC64
;
11470 rel
= XNEW (arelent
);
11471 rel
->sym_ptr_ptr
= XNEW (asymbol
*);
11472 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
11474 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
11476 if (!use_rela_relocations
)
11478 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
11479 vtable entry to be used in the relocation's section offset. */
11480 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
11481 rel
->address
= fixp
->fx_offset
;
11482 #if defined (OBJ_COFF) && defined (TE_PE)
11483 else if (fixp
->fx_addsy
&& S_IS_WEAK (fixp
->fx_addsy
))
11484 rel
->addend
= fixp
->fx_addnumber
- (S_GET_VALUE (fixp
->fx_addsy
) * 2);
11489 /* Use the rela in 64bit mode. */
11492 if (disallow_64bit_reloc
)
11495 case BFD_RELOC_X86_64_DTPOFF64
:
11496 case BFD_RELOC_X86_64_TPOFF64
:
11497 case BFD_RELOC_64_PCREL
:
11498 case BFD_RELOC_X86_64_GOTOFF64
:
11499 case BFD_RELOC_X86_64_GOT64
:
11500 case BFD_RELOC_X86_64_GOTPCREL64
:
11501 case BFD_RELOC_X86_64_GOTPC64
:
11502 case BFD_RELOC_X86_64_GOTPLT64
:
11503 case BFD_RELOC_X86_64_PLTOFF64
:
11504 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
11505 _("cannot represent relocation type %s in x32 mode"),
11506 bfd_get_reloc_code_name (code
));
11512 if (!fixp
->fx_pcrel
)
11513 rel
->addend
= fixp
->fx_offset
;
11517 case BFD_RELOC_X86_64_PLT32
:
11518 case BFD_RELOC_X86_64_GOT32
:
11519 case BFD_RELOC_X86_64_GOTPCREL
:
11520 case BFD_RELOC_X86_64_GOTPCRELX
:
11521 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
11522 case BFD_RELOC_X86_64_TLSGD
:
11523 case BFD_RELOC_X86_64_TLSLD
:
11524 case BFD_RELOC_X86_64_GOTTPOFF
:
11525 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
11526 case BFD_RELOC_X86_64_TLSDESC_CALL
:
11527 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
11530 rel
->addend
= (section
->vma
11532 + fixp
->fx_addnumber
11533 + md_pcrel_from (fixp
));
11538 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
11539 if (rel
->howto
== NULL
)
11541 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
11542 _("cannot represent relocation type %s"),
11543 bfd_get_reloc_code_name (code
));
11544 /* Set howto to a garbage value so that we can keep going. */
11545 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
11546 gas_assert (rel
->howto
!= NULL
);
11552 #include "tc-i386-intel.c"
11555 tc_x86_parse_to_dw2regnum (expressionS
*exp
)
11557 int saved_naked_reg
;
11558 char saved_register_dot
;
11560 saved_naked_reg
= allow_naked_reg
;
11561 allow_naked_reg
= 1;
11562 saved_register_dot
= register_chars
['.'];
11563 register_chars
['.'] = '.';
11564 allow_pseudo_reg
= 1;
11565 expression_and_evaluate (exp
);
11566 allow_pseudo_reg
= 0;
11567 register_chars
['.'] = saved_register_dot
;
11568 allow_naked_reg
= saved_naked_reg
;
11570 if (exp
->X_op
== O_register
&& exp
->X_add_number
>= 0)
11572 if ((addressT
) exp
->X_add_number
< i386_regtab_size
)
11574 exp
->X_op
= O_constant
;
11575 exp
->X_add_number
= i386_regtab
[exp
->X_add_number
]
11576 .dw2_regnum
[flag_code
>> 1];
11579 exp
->X_op
= O_illegal
;
11584 tc_x86_frame_initial_instructions (void)
11586 static unsigned int sp_regno
[2];
11588 if (!sp_regno
[flag_code
>> 1])
11590 char *saved_input
= input_line_pointer
;
11591 char sp
[][4] = {"esp", "rsp"};
11594 input_line_pointer
= sp
[flag_code
>> 1];
11595 tc_x86_parse_to_dw2regnum (&exp
);
11596 gas_assert (exp
.X_op
== O_constant
);
11597 sp_regno
[flag_code
>> 1] = exp
.X_add_number
;
11598 input_line_pointer
= saved_input
;
11601 cfi_add_CFA_def_cfa (sp_regno
[flag_code
>> 1], -x86_cie_data_alignment
);
11602 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
11606 x86_dwarf2_addr_size (void)
11608 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
11609 if (x86_elf_abi
== X86_64_X32_ABI
)
11612 return bfd_arch_bits_per_address (stdoutput
) / 8;
11616 i386_elf_section_type (const char *str
, size_t len
)
11618 if (flag_code
== CODE_64BIT
11619 && len
== sizeof ("unwind") - 1
11620 && strncmp (str
, "unwind", 6) == 0)
11621 return SHT_X86_64_UNWIND
;
11628 i386_solaris_fix_up_eh_frame (segT sec
)
11630 if (flag_code
== CODE_64BIT
)
11631 elf_section_type (sec
) = SHT_X86_64_UNWIND
;
11637 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
11641 exp
.X_op
= O_secrel
;
11642 exp
.X_add_symbol
= symbol
;
11643 exp
.X_add_number
= 0;
11644 emit_expr (&exp
, size
);
11648 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11649 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
11652 x86_64_section_letter (int letter
, const char **ptr_msg
)
11654 if (flag_code
== CODE_64BIT
)
11657 return SHF_X86_64_LARGE
;
11659 *ptr_msg
= _("bad .section directive: want a,l,w,x,M,S,G,T in string");
11662 *ptr_msg
= _("bad .section directive: want a,w,x,M,S,G,T in string");
11667 x86_64_section_word (char *str
, size_t len
)
11669 if (len
== 5 && flag_code
== CODE_64BIT
&& CONST_STRNEQ (str
, "large"))
11670 return SHF_X86_64_LARGE
;
11676 handle_large_common (int small ATTRIBUTE_UNUSED
)
11678 if (flag_code
!= CODE_64BIT
)
11680 s_comm_internal (0, elf_common_parse
);
11681 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
11685 static segT lbss_section
;
11686 asection
*saved_com_section_ptr
= elf_com_section_ptr
;
11687 asection
*saved_bss_section
= bss_section
;
11689 if (lbss_section
== NULL
)
11691 flagword applicable
;
11692 segT seg
= now_seg
;
11693 subsegT subseg
= now_subseg
;
11695 /* The .lbss section is for local .largecomm symbols. */
11696 lbss_section
= subseg_new (".lbss", 0);
11697 applicable
= bfd_applicable_section_flags (stdoutput
);
11698 bfd_set_section_flags (stdoutput
, lbss_section
,
11699 applicable
& SEC_ALLOC
);
11700 seg_info (lbss_section
)->bss
= 1;
11702 subseg_set (seg
, subseg
);
11705 elf_com_section_ptr
= &_bfd_elf_large_com_section
;
11706 bss_section
= lbss_section
;
11708 s_comm_internal (0, elf_common_parse
);
11710 elf_com_section_ptr
= saved_com_section_ptr
;
11711 bss_section
= saved_bss_section
;
11714 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */