1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright (C) 1989-2019 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 /* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
23 x86_64 support by Jan Hubicka (jh@suse.cz)
24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
29 #include "safe-ctype.h"
31 #include "dwarf2dbg.h"
32 #include "dw2gencfi.h"
33 #include "elf/x86-64.h"
34 #include "opcodes/i386-init.h"
39 #ifdef HAVE_SYS_PARAM_H
40 #include <sys/param.h>
43 #define INT_MAX (int) (((unsigned) (-1)) >> 1)
47 #ifndef REGISTER_WARNINGS
48 #define REGISTER_WARNINGS 1
51 #ifndef INFER_ADDR_PREFIX
52 #define INFER_ADDR_PREFIX 1
56 #define DEFAULT_ARCH "i386"
61 #define INLINE __inline__
67 /* Prefixes will be emitted in the order defined below.
68 WAIT_PREFIX must be the first prefix since FWAIT is really is an
69 instruction, and so must come before any prefixes.
70 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
71 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
77 #define HLE_PREFIX REP_PREFIX
78 #define BND_PREFIX REP_PREFIX
80 #define REX_PREFIX 6 /* must come last. */
81 #define MAX_PREFIXES 7 /* max prefixes per opcode */
83 /* we define the syntax here (modulo base,index,scale syntax) */
84 #define REGISTER_PREFIX '%'
85 #define IMMEDIATE_PREFIX '$'
86 #define ABSOLUTE_PREFIX '*'
88 /* these are the instruction mnemonic suffixes in AT&T syntax or
89 memory operand size in Intel syntax. */
90 #define WORD_MNEM_SUFFIX 'w'
91 #define BYTE_MNEM_SUFFIX 'b'
92 #define SHORT_MNEM_SUFFIX 's'
93 #define LONG_MNEM_SUFFIX 'l'
94 #define QWORD_MNEM_SUFFIX 'q'
95 /* Intel Syntax. Use a non-ascii letter since since it never appears
97 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
99 #define END_OF_INSN '\0'
101 /* This matches the C -> StaticRounding alias in the opcode table. */
102 #define commutative staticrounding
105 'templates' is for grouping together 'template' structures for opcodes
106 of the same name. This is only used for storing the insns in the grand
107 ole hash table of insns.
108 The templates themselves start at START and range up to (but not including)
113 const insn_template
*start
;
114 const insn_template
*end
;
118 /* 386 operand encoding bytes: see 386 book for details of this. */
121 unsigned int regmem
; /* codes register or memory operand */
122 unsigned int reg
; /* codes register operand (or extended opcode) */
123 unsigned int mode
; /* how to interpret regmem & reg */
127 /* x86-64 extension prefix. */
128 typedef int rex_byte
;
130 /* 386 opcode byte to code indirect addressing. */
139 /* x86 arch names, types and features */
142 const char *name
; /* arch name */
143 unsigned int len
; /* arch string length */
144 enum processor_type type
; /* arch type */
145 i386_cpu_flags flags
; /* cpu feature flags */
146 unsigned int skip
; /* show_arch should skip this. */
150 /* Used to turn off indicated flags. */
153 const char *name
; /* arch name */
154 unsigned int len
; /* arch string length */
155 i386_cpu_flags flags
; /* cpu feature flags */
159 static void update_code_flag (int, int);
160 static void set_code_flag (int);
161 static void set_16bit_gcc_code_flag (int);
162 static void set_intel_syntax (int);
163 static void set_intel_mnemonic (int);
164 static void set_allow_index_reg (int);
165 static void set_check (int);
166 static void set_cpu_arch (int);
168 static void pe_directive_secrel (int);
170 static void signed_cons (int);
171 static char *output_invalid (int c
);
172 static int i386_finalize_immediate (segT
, expressionS
*, i386_operand_type
,
174 static int i386_finalize_displacement (segT
, expressionS
*, i386_operand_type
,
176 static int i386_att_operand (char *);
177 static int i386_intel_operand (char *, int);
178 static int i386_intel_simplify (expressionS
*);
179 static int i386_intel_parse_name (const char *, expressionS
*);
180 static const reg_entry
*parse_register (char *, char **);
181 static char *parse_insn (char *, char *);
182 static char *parse_operands (char *, const char *);
183 static void swap_operands (void);
184 static void swap_2_operands (int, int);
185 static void optimize_imm (void);
186 static void optimize_disp (void);
187 static const insn_template
*match_template (char);
188 static int check_string (void);
189 static int process_suffix (void);
190 static int check_byte_reg (void);
191 static int check_long_reg (void);
192 static int check_qword_reg (void);
193 static int check_word_reg (void);
194 static int finalize_imm (void);
195 static int process_operands (void);
196 static const seg_entry
*build_modrm_byte (void);
197 static void output_insn (void);
198 static void output_imm (fragS
*, offsetT
);
199 static void output_disp (fragS
*, offsetT
);
201 static void s_bss (int);
203 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
204 static void handle_large_common (int small ATTRIBUTE_UNUSED
);
206 /* GNU_PROPERTY_X86_ISA_1_USED. */
207 static unsigned int x86_isa_1_used
;
208 /* GNU_PROPERTY_X86_FEATURE_2_USED. */
209 static unsigned int x86_feature_2_used
;
210 /* Generate x86 used ISA and feature properties. */
211 static unsigned int x86_used_note
= DEFAULT_X86_USED_NOTE
;
214 static const char *default_arch
= DEFAULT_ARCH
;
216 /* This struct describes rounding control and SAE in the instruction. */
230 static struct RC_Operation rc_op
;
232 /* The struct describes masking, applied to OPERAND in the instruction.
233 MASK is a pointer to the corresponding mask register. ZEROING tells
234 whether merging or zeroing mask is used. */
235 struct Mask_Operation
237 const reg_entry
*mask
;
238 unsigned int zeroing
;
239 /* The operand where this operation is associated. */
243 static struct Mask_Operation mask_op
;
245 /* The struct describes broadcasting, applied to OPERAND. FACTOR is
247 struct Broadcast_Operation
249 /* Type of broadcast: {1to2}, {1to4}, {1to8}, or {1to16}. */
252 /* Index of broadcasted operand. */
255 /* Number of bytes to broadcast. */
259 static struct Broadcast_Operation broadcast_op
;
264 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
265 unsigned char bytes
[4];
267 /* Destination or source register specifier. */
268 const reg_entry
*register_specifier
;
271 /* 'md_assemble ()' gathers together information and puts it into a
278 const reg_entry
*regs
;
283 operand_size_mismatch
,
284 operand_type_mismatch
,
285 register_type_mismatch
,
286 number_of_operands_mismatch
,
287 invalid_instruction_suffix
,
289 unsupported_with_intel_mnemonic
,
292 invalid_vsib_address
,
293 invalid_vector_register_set
,
294 unsupported_vector_index_register
,
295 unsupported_broadcast
,
298 mask_not_on_destination
,
301 rc_sae_operand_not_last_imm
,
302 invalid_register_operand
,
307 /* TM holds the template for the insn were currently assembling. */
310 /* SUFFIX holds the instruction size suffix for byte, word, dword
311 or qword, if given. */
314 /* OPERANDS gives the number of given operands. */
315 unsigned int operands
;
317 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
318 of given register, displacement, memory operands and immediate
320 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
322 /* TYPES [i] is the type (see above #defines) which tells us how to
323 use OP[i] for the corresponding operand. */
324 i386_operand_type types
[MAX_OPERANDS
];
326 /* Displacement expression, immediate expression, or register for each
328 union i386_op op
[MAX_OPERANDS
];
330 /* Flags for operands. */
331 unsigned int flags
[MAX_OPERANDS
];
332 #define Operand_PCrel 1
333 #define Operand_Mem 2
335 /* Relocation type for operand */
336 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
338 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
339 the base index byte below. */
340 const reg_entry
*base_reg
;
341 const reg_entry
*index_reg
;
342 unsigned int log2_scale_factor
;
344 /* SEG gives the seg_entries of this insn. They are zero unless
345 explicit segment overrides are given. */
346 const seg_entry
*seg
[2];
348 /* Copied first memory operand string, for re-checking. */
351 /* PREFIX holds all the given prefix opcodes (usually null).
352 PREFIXES is the number of prefix opcodes. */
353 unsigned int prefixes
;
354 unsigned char prefix
[MAX_PREFIXES
];
356 /* Has MMX register operands. */
357 bfd_boolean has_regmmx
;
359 /* Has XMM register operands. */
360 bfd_boolean has_regxmm
;
362 /* Has YMM register operands. */
363 bfd_boolean has_regymm
;
365 /* Has ZMM register operands. */
366 bfd_boolean has_regzmm
;
368 /* RM and SIB are the modrm byte and the sib byte where the
369 addressing modes of this insn are encoded. */
376 /* Masking attributes. */
377 struct Mask_Operation
*mask
;
379 /* Rounding control and SAE attributes. */
380 struct RC_Operation
*rounding
;
382 /* Broadcasting attributes. */
383 struct Broadcast_Operation
*broadcast
;
385 /* Compressed disp8*N attribute. */
386 unsigned int memshift
;
388 /* Prefer load or store in encoding. */
391 dir_encoding_default
= 0,
397 /* Prefer 8bit or 32bit displacement in encoding. */
400 disp_encoding_default
= 0,
405 /* Prefer the REX byte in encoding. */
406 bfd_boolean rex_encoding
;
408 /* Disable instruction size optimization. */
409 bfd_boolean no_optimize
;
411 /* How to encode vector instructions. */
414 vex_encoding_default
= 0,
421 const char *rep_prefix
;
424 const char *hle_prefix
;
426 /* Have BND prefix. */
427 const char *bnd_prefix
;
429 /* Have NOTRACK prefix. */
430 const char *notrack_prefix
;
433 enum i386_error error
;
436 typedef struct _i386_insn i386_insn
;
438 /* Link RC type with corresponding string, that'll be looked for in
447 static const struct RC_name RC_NamesTable
[] =
449 { rne
, STRING_COMMA_LEN ("rn-sae") },
450 { rd
, STRING_COMMA_LEN ("rd-sae") },
451 { ru
, STRING_COMMA_LEN ("ru-sae") },
452 { rz
, STRING_COMMA_LEN ("rz-sae") },
453 { saeonly
, STRING_COMMA_LEN ("sae") },
456 /* List of chars besides those in app.c:symbol_chars that can start an
457 operand. Used to prevent the scrubber eating vital white-space. */
458 const char extra_symbol_chars
[] = "*%-([{}"
467 #if (defined (TE_I386AIX) \
468 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
469 && !defined (TE_GNU) \
470 && !defined (TE_LINUX) \
471 && !defined (TE_NACL) \
472 && !defined (TE_FreeBSD) \
473 && !defined (TE_DragonFly) \
474 && !defined (TE_NetBSD)))
475 /* This array holds the chars that always start a comment. If the
476 pre-processor is disabled, these aren't very useful. The option
477 --divide will remove '/' from this list. */
478 const char *i386_comment_chars
= "#/";
479 #define SVR4_COMMENT_CHARS 1
480 #define PREFIX_SEPARATOR '\\'
483 const char *i386_comment_chars
= "#";
484 #define PREFIX_SEPARATOR '/'
487 /* This array holds the chars that only start a comment at the beginning of
488 a line. If the line seems to have the form '# 123 filename'
489 .line and .file directives will appear in the pre-processed output.
490 Note that input_file.c hand checks for '#' at the beginning of the
491 first line of the input file. This is because the compiler outputs
492 #NO_APP at the beginning of its output.
493 Also note that comments started like this one will always work if
494 '/' isn't otherwise defined. */
495 const char line_comment_chars
[] = "#/";
497 const char line_separator_chars
[] = ";";
499 /* Chars that can be used to separate mant from exp in floating point
501 const char EXP_CHARS
[] = "eE";
503 /* Chars that mean this number is a floating point constant
506 const char FLT_CHARS
[] = "fFdDxX";
508 /* Tables for lexical analysis. */
509 static char mnemonic_chars
[256];
510 static char register_chars
[256];
511 static char operand_chars
[256];
512 static char identifier_chars
[256];
513 static char digit_chars
[256];
515 /* Lexical macros. */
516 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
517 #define is_operand_char(x) (operand_chars[(unsigned char) x])
518 #define is_register_char(x) (register_chars[(unsigned char) x])
519 #define is_space_char(x) ((x) == ' ')
520 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
521 #define is_digit_char(x) (digit_chars[(unsigned char) x])
523 /* All non-digit non-letter characters that may occur in an operand. */
524 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
526 /* md_assemble() always leaves the strings it's passed unaltered. To
527 effect this we maintain a stack of saved characters that we've smashed
528 with '\0's (indicating end of strings for various sub-fields of the
529 assembler instruction). */
530 static char save_stack
[32];
531 static char *save_stack_p
;
532 #define END_STRING_AND_SAVE(s) \
533 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
534 #define RESTORE_END_STRING(s) \
535 do { *(s) = *--save_stack_p; } while (0)
537 /* The instruction we're assembling. */
540 /* Possible templates for current insn. */
541 static const templates
*current_templates
;
543 /* Per instruction expressionS buffers: max displacements & immediates. */
544 static expressionS disp_expressions
[MAX_MEMORY_OPERANDS
];
545 static expressionS im_expressions
[MAX_IMMEDIATE_OPERANDS
];
547 /* Current operand we are working on. */
548 static int this_operand
= -1;
550 /* We support four different modes. FLAG_CODE variable is used to distinguish
558 static enum flag_code flag_code
;
559 static unsigned int object_64bit
;
560 static unsigned int disallow_64bit_reloc
;
561 static int use_rela_relocations
= 0;
563 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
564 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
565 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
567 /* The ELF ABI to use. */
575 static enum x86_elf_abi x86_elf_abi
= I386_ABI
;
578 #if defined (TE_PE) || defined (TE_PEP)
579 /* Use big object file format. */
580 static int use_big_obj
= 0;
583 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
584 /* 1 if generating code for a shared library. */
585 static int shared
= 0;
588 /* 1 for intel syntax,
590 static int intel_syntax
= 0;
592 /* 1 for Intel64 ISA,
596 /* 1 for intel mnemonic,
597 0 if att mnemonic. */
598 static int intel_mnemonic
= !SYSV386_COMPAT
;
600 /* 1 if pseudo registers are permitted. */
601 static int allow_pseudo_reg
= 0;
603 /* 1 if register prefix % not required. */
604 static int allow_naked_reg
= 0;
606 /* 1 if the assembler should add BND prefix for all control-transferring
607 instructions supporting it, even if this prefix wasn't specified
609 static int add_bnd_prefix
= 0;
611 /* 1 if pseudo index register, eiz/riz, is allowed . */
612 static int allow_index_reg
= 0;
614 /* 1 if the assembler should ignore LOCK prefix, even if it was
615 specified explicitly. */
616 static int omit_lock_prefix
= 0;
618 /* 1 if the assembler should encode lfence, mfence, and sfence as
619 "lock addl $0, (%{re}sp)". */
620 static int avoid_fence
= 0;
622 /* 1 if the assembler should generate relax relocations. */
624 static int generate_relax_relocations
625 = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS
;
627 static enum check_kind
633 sse_check
, operand_check
= check_warning
;
636 1. Clear the REX_W bit with register operand if possible.
637 2. Above plus use 128bit vector instruction to clear the full vector
640 static int optimize
= 0;
643 1. Clear the REX_W bit with register operand if possible.
644 2. Above plus use 128bit vector instruction to clear the full vector
646 3. Above plus optimize "test{q,l,w} $imm8,%r{64,32,16}" to
649 static int optimize_for_space
= 0;
651 /* Register prefix used for error message. */
652 static const char *register_prefix
= "%";
654 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
655 leave, push, and pop instructions so that gcc has the same stack
656 frame as in 32 bit mode. */
657 static char stackop_size
= '\0';
659 /* Non-zero to optimize code alignment. */
660 int optimize_align_code
= 1;
662 /* Non-zero to quieten some warnings. */
663 static int quiet_warnings
= 0;
666 static const char *cpu_arch_name
= NULL
;
667 static char *cpu_sub_arch_name
= NULL
;
669 /* CPU feature flags. */
670 static i386_cpu_flags cpu_arch_flags
= CPU_UNKNOWN_FLAGS
;
672 /* If we have selected a cpu we are generating instructions for. */
673 static int cpu_arch_tune_set
= 0;
675 /* Cpu we are generating instructions for. */
676 enum processor_type cpu_arch_tune
= PROCESSOR_UNKNOWN
;
678 /* CPU feature flags of cpu we are generating instructions for. */
679 static i386_cpu_flags cpu_arch_tune_flags
;
681 /* CPU instruction set architecture used. */
682 enum processor_type cpu_arch_isa
= PROCESSOR_UNKNOWN
;
684 /* CPU feature flags of instruction set architecture used. */
685 i386_cpu_flags cpu_arch_isa_flags
;
687 /* If set, conditional jumps are not automatically promoted to handle
688 larger than a byte offset. */
689 static unsigned int no_cond_jump_promotion
= 0;
691 /* Encode SSE instructions with VEX prefix. */
692 static unsigned int sse2avx
;
694 /* Encode scalar AVX instructions with specific vector length. */
701 /* Encode VEX WIG instructions with specific vex.w. */
708 /* Encode scalar EVEX LIG instructions with specific vector length. */
716 /* Encode EVEX WIG instructions with specific evex.w. */
723 /* Value to encode in EVEX RC bits, for SAE-only instructions. */
724 static enum rc_type evexrcig
= rne
;
726 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
727 static symbolS
*GOT_symbol
;
729 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
730 unsigned int x86_dwarf2_return_column
;
732 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
733 int x86_cie_data_alignment
;
735 /* Interface to relax_segment.
736 There are 3 major relax states for 386 jump insns because the
737 different types of jumps add different sizes to frags when we're
738 figuring out what sort of jump to choose to reach a given label. */
741 #define UNCOND_JUMP 0
743 #define COND_JUMP86 2
748 #define SMALL16 (SMALL | CODE16)
750 #define BIG16 (BIG | CODE16)
754 #define INLINE __inline__
760 #define ENCODE_RELAX_STATE(type, size) \
761 ((relax_substateT) (((type) << 2) | (size)))
762 #define TYPE_FROM_RELAX_STATE(s) \
764 #define DISP_SIZE_FROM_RELAX_STATE(s) \
765 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
767 /* This table is used by relax_frag to promote short jumps to long
768 ones where necessary. SMALL (short) jumps may be promoted to BIG
769 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
770 don't allow a short jump in a 32 bit code segment to be promoted to
771 a 16 bit offset jump because it's slower (requires data size
772 prefix), and doesn't work, unless the destination is in the bottom
773 64k of the code segment (The top 16 bits of eip are zeroed). */
775 const relax_typeS md_relax_table
[] =
778 1) most positive reach of this state,
779 2) most negative reach of this state,
780 3) how many bytes this mode will have in the variable part of the frag
781 4) which index into the table to try if we can't fit into this one. */
783 /* UNCOND_JUMP states. */
784 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
785 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
786 /* dword jmp adds 4 bytes to frag:
787 0 extra opcode bytes, 4 displacement bytes. */
789 /* word jmp adds 2 byte2 to frag:
790 0 extra opcode bytes, 2 displacement bytes. */
793 /* COND_JUMP states. */
794 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
795 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
796 /* dword conditionals adds 5 bytes to frag:
797 1 extra opcode byte, 4 displacement bytes. */
799 /* word conditionals add 3 bytes to frag:
800 1 extra opcode byte, 2 displacement bytes. */
803 /* COND_JUMP86 states. */
804 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
805 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
806 /* dword conditionals adds 5 bytes to frag:
807 1 extra opcode byte, 4 displacement bytes. */
809 /* word conditionals add 4 bytes to frag:
810 1 displacement byte and a 3 byte long branch insn. */
814 static const arch_entry cpu_arch
[] =
816 /* Do not replace the first two entries - i386_target_format()
817 relies on them being there in this order. */
818 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32
,
819 CPU_GENERIC32_FLAGS
, 0 },
820 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64
,
821 CPU_GENERIC64_FLAGS
, 0 },
822 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN
,
824 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN
,
826 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN
,
828 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386
,
830 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486
,
832 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM
,
834 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO
,
836 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM
,
838 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO
,
839 CPU_PENTIUMPRO_FLAGS
, 0 },
840 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO
,
842 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO
,
844 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4
,
846 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA
,
848 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA
,
849 CPU_NOCONA_FLAGS
, 0 },
850 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE
,
852 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE
,
854 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2
,
855 CPU_CORE2_FLAGS
, 1 },
856 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2
,
857 CPU_CORE2_FLAGS
, 0 },
858 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7
,
859 CPU_COREI7_FLAGS
, 0 },
860 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM
,
862 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM
,
864 { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU
,
865 CPU_IAMCU_FLAGS
, 0 },
866 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6
,
868 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6
,
870 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON
,
871 CPU_ATHLON_FLAGS
, 0 },
872 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8
,
874 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8
,
876 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8
,
878 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10
,
879 CPU_AMDFAM10_FLAGS
, 0 },
880 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD
,
881 CPU_BDVER1_FLAGS
, 0 },
882 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD
,
883 CPU_BDVER2_FLAGS
, 0 },
884 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD
,
885 CPU_BDVER3_FLAGS
, 0 },
886 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD
,
887 CPU_BDVER4_FLAGS
, 0 },
888 { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER
,
889 CPU_ZNVER1_FLAGS
, 0 },
890 { STRING_COMMA_LEN ("znver2"), PROCESSOR_ZNVER
,
891 CPU_ZNVER2_FLAGS
, 0 },
892 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT
,
893 CPU_BTVER1_FLAGS
, 0 },
894 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT
,
895 CPU_BTVER2_FLAGS
, 0 },
896 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN
,
898 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN
,
900 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN
,
902 { STRING_COMMA_LEN (".687"), PROCESSOR_UNKNOWN
,
904 { STRING_COMMA_LEN (".cmov"), PROCESSOR_UNKNOWN
,
906 { STRING_COMMA_LEN (".fxsr"), PROCESSOR_UNKNOWN
,
908 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN
,
910 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN
,
912 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN
,
914 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN
,
916 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN
,
917 CPU_SSSE3_FLAGS
, 0 },
918 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN
,
919 CPU_SSE4_1_FLAGS
, 0 },
920 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN
,
921 CPU_SSE4_2_FLAGS
, 0 },
922 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN
,
923 CPU_SSE4_2_FLAGS
, 0 },
924 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN
,
926 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN
,
928 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN
,
929 CPU_AVX512F_FLAGS
, 0 },
930 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN
,
931 CPU_AVX512CD_FLAGS
, 0 },
932 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN
,
933 CPU_AVX512ER_FLAGS
, 0 },
934 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN
,
935 CPU_AVX512PF_FLAGS
, 0 },
936 { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN
,
937 CPU_AVX512DQ_FLAGS
, 0 },
938 { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN
,
939 CPU_AVX512BW_FLAGS
, 0 },
940 { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN
,
941 CPU_AVX512VL_FLAGS
, 0 },
942 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN
,
944 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN
,
945 CPU_VMFUNC_FLAGS
, 0 },
946 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN
,
948 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN
,
949 CPU_XSAVE_FLAGS
, 0 },
950 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN
,
951 CPU_XSAVEOPT_FLAGS
, 0 },
952 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN
,
953 CPU_XSAVEC_FLAGS
, 0 },
954 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN
,
955 CPU_XSAVES_FLAGS
, 0 },
956 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN
,
958 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN
,
959 CPU_PCLMUL_FLAGS
, 0 },
960 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN
,
961 CPU_PCLMUL_FLAGS
, 1 },
962 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN
,
963 CPU_FSGSBASE_FLAGS
, 0 },
964 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN
,
965 CPU_RDRND_FLAGS
, 0 },
966 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN
,
968 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN
,
970 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN
,
972 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN
,
974 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN
,
976 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN
,
978 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN
,
979 CPU_MOVBE_FLAGS
, 0 },
980 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN
,
982 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN
,
984 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN
,
985 CPU_LZCNT_FLAGS
, 0 },
986 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN
,
988 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN
,
990 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN
,
991 CPU_INVPCID_FLAGS
, 0 },
992 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN
,
993 CPU_CLFLUSH_FLAGS
, 0 },
994 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN
,
996 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN
,
997 CPU_SYSCALL_FLAGS
, 0 },
998 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN
,
999 CPU_RDTSCP_FLAGS
, 0 },
1000 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN
,
1001 CPU_3DNOW_FLAGS
, 0 },
1002 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN
,
1003 CPU_3DNOWA_FLAGS
, 0 },
1004 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN
,
1005 CPU_PADLOCK_FLAGS
, 0 },
1006 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN
,
1007 CPU_SVME_FLAGS
, 1 },
1008 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN
,
1009 CPU_SVME_FLAGS
, 0 },
1010 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN
,
1011 CPU_SSE4A_FLAGS
, 0 },
1012 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN
,
1014 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN
,
1016 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN
,
1018 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN
,
1020 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN
,
1021 CPU_RDSEED_FLAGS
, 0 },
1022 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN
,
1023 CPU_PRFCHW_FLAGS
, 0 },
1024 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN
,
1025 CPU_SMAP_FLAGS
, 0 },
1026 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN
,
1028 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN
,
1030 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN
,
1031 CPU_CLFLUSHOPT_FLAGS
, 0 },
1032 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN
,
1033 CPU_PREFETCHWT1_FLAGS
, 0 },
1034 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN
,
1036 { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN
,
1037 CPU_CLWB_FLAGS
, 0 },
1038 { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN
,
1039 CPU_AVX512IFMA_FLAGS
, 0 },
1040 { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN
,
1041 CPU_AVX512VBMI_FLAGS
, 0 },
1042 { STRING_COMMA_LEN (".avx512_4fmaps"), PROCESSOR_UNKNOWN
,
1043 CPU_AVX512_4FMAPS_FLAGS
, 0 },
1044 { STRING_COMMA_LEN (".avx512_4vnniw"), PROCESSOR_UNKNOWN
,
1045 CPU_AVX512_4VNNIW_FLAGS
, 0 },
1046 { STRING_COMMA_LEN (".avx512_vpopcntdq"), PROCESSOR_UNKNOWN
,
1047 CPU_AVX512_VPOPCNTDQ_FLAGS
, 0 },
1048 { STRING_COMMA_LEN (".avx512_vbmi2"), PROCESSOR_UNKNOWN
,
1049 CPU_AVX512_VBMI2_FLAGS
, 0 },
1050 { STRING_COMMA_LEN (".avx512_vnni"), PROCESSOR_UNKNOWN
,
1051 CPU_AVX512_VNNI_FLAGS
, 0 },
1052 { STRING_COMMA_LEN (".avx512_bitalg"), PROCESSOR_UNKNOWN
,
1053 CPU_AVX512_BITALG_FLAGS
, 0 },
1054 { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN
,
1055 CPU_CLZERO_FLAGS
, 0 },
1056 { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN
,
1057 CPU_MWAITX_FLAGS
, 0 },
1058 { STRING_COMMA_LEN (".ospke"), PROCESSOR_UNKNOWN
,
1059 CPU_OSPKE_FLAGS
, 0 },
1060 { STRING_COMMA_LEN (".rdpid"), PROCESSOR_UNKNOWN
,
1061 CPU_RDPID_FLAGS
, 0 },
1062 { STRING_COMMA_LEN (".ptwrite"), PROCESSOR_UNKNOWN
,
1063 CPU_PTWRITE_FLAGS
, 0 },
1064 { STRING_COMMA_LEN (".ibt"), PROCESSOR_UNKNOWN
,
1066 { STRING_COMMA_LEN (".shstk"), PROCESSOR_UNKNOWN
,
1067 CPU_SHSTK_FLAGS
, 0 },
1068 { STRING_COMMA_LEN (".gfni"), PROCESSOR_UNKNOWN
,
1069 CPU_GFNI_FLAGS
, 0 },
1070 { STRING_COMMA_LEN (".vaes"), PROCESSOR_UNKNOWN
,
1071 CPU_VAES_FLAGS
, 0 },
1072 { STRING_COMMA_LEN (".vpclmulqdq"), PROCESSOR_UNKNOWN
,
1073 CPU_VPCLMULQDQ_FLAGS
, 0 },
1074 { STRING_COMMA_LEN (".wbnoinvd"), PROCESSOR_UNKNOWN
,
1075 CPU_WBNOINVD_FLAGS
, 0 },
1076 { STRING_COMMA_LEN (".pconfig"), PROCESSOR_UNKNOWN
,
1077 CPU_PCONFIG_FLAGS
, 0 },
1078 { STRING_COMMA_LEN (".waitpkg"), PROCESSOR_UNKNOWN
,
1079 CPU_WAITPKG_FLAGS
, 0 },
1080 { STRING_COMMA_LEN (".cldemote"), PROCESSOR_UNKNOWN
,
1081 CPU_CLDEMOTE_FLAGS
, 0 },
1082 { STRING_COMMA_LEN (".movdiri"), PROCESSOR_UNKNOWN
,
1083 CPU_MOVDIRI_FLAGS
, 0 },
1084 { STRING_COMMA_LEN (".movdir64b"), PROCESSOR_UNKNOWN
,
1085 CPU_MOVDIR64B_FLAGS
, 0 },
1086 { STRING_COMMA_LEN (".avx512_bf16"), PROCESSOR_UNKNOWN
,
1087 CPU_AVX512_BF16_FLAGS
, 0 },
1088 { STRING_COMMA_LEN (".avx512_vp2intersect"), PROCESSOR_UNKNOWN
,
1089 CPU_AVX512_VP2INTERSECT_FLAGS
, 0 },
1090 { STRING_COMMA_LEN (".enqcmd"), PROCESSOR_UNKNOWN
,
1091 CPU_ENQCMD_FLAGS
, 0 },
1094 static const noarch_entry cpu_noarch
[] =
1096 { STRING_COMMA_LEN ("no87"), CPU_ANY_X87_FLAGS
},
1097 { STRING_COMMA_LEN ("no287"), CPU_ANY_287_FLAGS
},
1098 { STRING_COMMA_LEN ("no387"), CPU_ANY_387_FLAGS
},
1099 { STRING_COMMA_LEN ("no687"), CPU_ANY_687_FLAGS
},
1100 { STRING_COMMA_LEN ("nocmov"), CPU_ANY_CMOV_FLAGS
},
1101 { STRING_COMMA_LEN ("nofxsr"), CPU_ANY_FXSR_FLAGS
},
1102 { STRING_COMMA_LEN ("nommx"), CPU_ANY_MMX_FLAGS
},
1103 { STRING_COMMA_LEN ("nosse"), CPU_ANY_SSE_FLAGS
},
1104 { STRING_COMMA_LEN ("nosse2"), CPU_ANY_SSE2_FLAGS
},
1105 { STRING_COMMA_LEN ("nosse3"), CPU_ANY_SSE3_FLAGS
},
1106 { STRING_COMMA_LEN ("nossse3"), CPU_ANY_SSSE3_FLAGS
},
1107 { STRING_COMMA_LEN ("nosse4.1"), CPU_ANY_SSE4_1_FLAGS
},
1108 { STRING_COMMA_LEN ("nosse4.2"), CPU_ANY_SSE4_2_FLAGS
},
1109 { STRING_COMMA_LEN ("nosse4"), CPU_ANY_SSE4_1_FLAGS
},
1110 { STRING_COMMA_LEN ("noavx"), CPU_ANY_AVX_FLAGS
},
1111 { STRING_COMMA_LEN ("noavx2"), CPU_ANY_AVX2_FLAGS
},
1112 { STRING_COMMA_LEN ("noavx512f"), CPU_ANY_AVX512F_FLAGS
},
1113 { STRING_COMMA_LEN ("noavx512cd"), CPU_ANY_AVX512CD_FLAGS
},
1114 { STRING_COMMA_LEN ("noavx512er"), CPU_ANY_AVX512ER_FLAGS
},
1115 { STRING_COMMA_LEN ("noavx512pf"), CPU_ANY_AVX512PF_FLAGS
},
1116 { STRING_COMMA_LEN ("noavx512dq"), CPU_ANY_AVX512DQ_FLAGS
},
1117 { STRING_COMMA_LEN ("noavx512bw"), CPU_ANY_AVX512BW_FLAGS
},
1118 { STRING_COMMA_LEN ("noavx512vl"), CPU_ANY_AVX512VL_FLAGS
},
1119 { STRING_COMMA_LEN ("noavx512ifma"), CPU_ANY_AVX512IFMA_FLAGS
},
1120 { STRING_COMMA_LEN ("noavx512vbmi"), CPU_ANY_AVX512VBMI_FLAGS
},
1121 { STRING_COMMA_LEN ("noavx512_4fmaps"), CPU_ANY_AVX512_4FMAPS_FLAGS
},
1122 { STRING_COMMA_LEN ("noavx512_4vnniw"), CPU_ANY_AVX512_4VNNIW_FLAGS
},
1123 { STRING_COMMA_LEN ("noavx512_vpopcntdq"), CPU_ANY_AVX512_VPOPCNTDQ_FLAGS
},
1124 { STRING_COMMA_LEN ("noavx512_vbmi2"), CPU_ANY_AVX512_VBMI2_FLAGS
},
1125 { STRING_COMMA_LEN ("noavx512_vnni"), CPU_ANY_AVX512_VNNI_FLAGS
},
1126 { STRING_COMMA_LEN ("noavx512_bitalg"), CPU_ANY_AVX512_BITALG_FLAGS
},
1127 { STRING_COMMA_LEN ("noibt"), CPU_ANY_IBT_FLAGS
},
1128 { STRING_COMMA_LEN ("noshstk"), CPU_ANY_SHSTK_FLAGS
},
1129 { STRING_COMMA_LEN ("nomovdiri"), CPU_ANY_MOVDIRI_FLAGS
},
1130 { STRING_COMMA_LEN ("nomovdir64b"), CPU_ANY_MOVDIR64B_FLAGS
},
1131 { STRING_COMMA_LEN ("noavx512_bf16"), CPU_ANY_AVX512_BF16_FLAGS
},
1132 { STRING_COMMA_LEN ("noavx512_vp2intersect"), CPU_ANY_SHSTK_FLAGS
},
1133 { STRING_COMMA_LEN ("noenqcmd"), CPU_ANY_ENQCMD_FLAGS
},
1137 /* Like s_lcomm_internal in gas/read.c but the alignment string
1138 is allowed to be optional. */
1141 pe_lcomm_internal (int needs_align
, symbolS
*symbolP
, addressT size
)
1148 && *input_line_pointer
== ',')
1150 align
= parse_align (needs_align
- 1);
1152 if (align
== (addressT
) -1)
1167 bss_alloc (symbolP
, size
, align
);
1172 pe_lcomm (int needs_align
)
1174 s_comm_internal (needs_align
* 2, pe_lcomm_internal
);
1178 const pseudo_typeS md_pseudo_table
[] =
1180 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
1181 {"align", s_align_bytes
, 0},
1183 {"align", s_align_ptwo
, 0},
1185 {"arch", set_cpu_arch
, 0},
1189 {"lcomm", pe_lcomm
, 1},
1191 {"ffloat", float_cons
, 'f'},
1192 {"dfloat", float_cons
, 'd'},
1193 {"tfloat", float_cons
, 'x'},
1195 {"slong", signed_cons
, 4},
1196 {"noopt", s_ignore
, 0},
1197 {"optim", s_ignore
, 0},
1198 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
1199 {"code16", set_code_flag
, CODE_16BIT
},
1200 {"code32", set_code_flag
, CODE_32BIT
},
1202 {"code64", set_code_flag
, CODE_64BIT
},
1204 {"intel_syntax", set_intel_syntax
, 1},
1205 {"att_syntax", set_intel_syntax
, 0},
1206 {"intel_mnemonic", set_intel_mnemonic
, 1},
1207 {"att_mnemonic", set_intel_mnemonic
, 0},
1208 {"allow_index_reg", set_allow_index_reg
, 1},
1209 {"disallow_index_reg", set_allow_index_reg
, 0},
1210 {"sse_check", set_check
, 0},
1211 {"operand_check", set_check
, 1},
1212 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1213 {"largecomm", handle_large_common
, 0},
1215 {"file", dwarf2_directive_file
, 0},
1216 {"loc", dwarf2_directive_loc
, 0},
1217 {"loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0},
1220 {"secrel32", pe_directive_secrel
, 0},
1225 /* For interface with expression (). */
1226 extern char *input_line_pointer
;
1228 /* Hash table for instruction mnemonic lookup. */
1229 static struct hash_control
*op_hash
;
1231 /* Hash table for register lookup. */
1232 static struct hash_control
*reg_hash
;
1234 /* Various efficient no-op patterns for aligning code labels.
1235 Note: Don't try to assemble the instructions in the comments.
1236 0L and 0w are not legal. */
1237 static const unsigned char f32_1
[] =
1239 static const unsigned char f32_2
[] =
1240 {0x66,0x90}; /* xchg %ax,%ax */
1241 static const unsigned char f32_3
[] =
1242 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1243 static const unsigned char f32_4
[] =
1244 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1245 static const unsigned char f32_6
[] =
1246 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1247 static const unsigned char f32_7
[] =
1248 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1249 static const unsigned char f16_3
[] =
1250 {0x8d,0x74,0x00}; /* lea 0(%si),%si */
1251 static const unsigned char f16_4
[] =
1252 {0x8d,0xb4,0x00,0x00}; /* lea 0W(%si),%si */
1253 static const unsigned char jump_disp8
[] =
1254 {0xeb}; /* jmp disp8 */
1255 static const unsigned char jump32_disp32
[] =
1256 {0xe9}; /* jmp disp32 */
1257 static const unsigned char jump16_disp32
[] =
1258 {0x66,0xe9}; /* jmp disp32 */
1259 /* 32-bit NOPs patterns. */
1260 static const unsigned char *const f32_patt
[] = {
1261 f32_1
, f32_2
, f32_3
, f32_4
, NULL
, f32_6
, f32_7
1263 /* 16-bit NOPs patterns. */
1264 static const unsigned char *const f16_patt
[] = {
1265 f32_1
, f32_2
, f16_3
, f16_4
1267 /* nopl (%[re]ax) */
1268 static const unsigned char alt_3
[] =
1270 /* nopl 0(%[re]ax) */
1271 static const unsigned char alt_4
[] =
1272 {0x0f,0x1f,0x40,0x00};
1273 /* nopl 0(%[re]ax,%[re]ax,1) */
1274 static const unsigned char alt_5
[] =
1275 {0x0f,0x1f,0x44,0x00,0x00};
1276 /* nopw 0(%[re]ax,%[re]ax,1) */
1277 static const unsigned char alt_6
[] =
1278 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1279 /* nopl 0L(%[re]ax) */
1280 static const unsigned char alt_7
[] =
1281 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1282 /* nopl 0L(%[re]ax,%[re]ax,1) */
1283 static const unsigned char alt_8
[] =
1284 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1285 /* nopw 0L(%[re]ax,%[re]ax,1) */
1286 static const unsigned char alt_9
[] =
1287 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1288 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1289 static const unsigned char alt_10
[] =
1290 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1291 /* data16 nopw %cs:0L(%eax,%eax,1) */
1292 static const unsigned char alt_11
[] =
1293 {0x66,0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1294 /* 32-bit and 64-bit NOPs patterns. */
1295 static const unsigned char *const alt_patt
[] = {
1296 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
1297 alt_9
, alt_10
, alt_11
1300 /* Genenerate COUNT bytes of NOPs to WHERE from PATT with the maximum
1301 size of a single NOP instruction MAX_SINGLE_NOP_SIZE. */
1304 i386_output_nops (char *where
, const unsigned char *const *patt
,
1305 int count
, int max_single_nop_size
)
1308 /* Place the longer NOP first. */
1311 const unsigned char *nops
;
1313 if (max_single_nop_size
< 1)
1315 as_fatal (_("i386_output_nops called to generate nops of at most %d bytes!"),
1316 max_single_nop_size
);
1320 nops
= patt
[max_single_nop_size
- 1];
1322 /* Use the smaller one if the requsted one isn't available. */
1325 max_single_nop_size
--;
1326 nops
= patt
[max_single_nop_size
- 1];
1329 last
= count
% max_single_nop_size
;
1332 for (offset
= 0; offset
< count
; offset
+= max_single_nop_size
)
1333 memcpy (where
+ offset
, nops
, max_single_nop_size
);
1337 nops
= patt
[last
- 1];
1340 /* Use the smaller one plus one-byte NOP if the needed one
1343 nops
= patt
[last
- 1];
1344 memcpy (where
+ offset
, nops
, last
);
1345 where
[offset
+ last
] = *patt
[0];
1348 memcpy (where
+ offset
, nops
, last
);
1353 fits_in_imm7 (offsetT num
)
1355 return (num
& 0x7f) == num
;
1359 fits_in_imm31 (offsetT num
)
1361 return (num
& 0x7fffffff) == num
;
1364 /* Genenerate COUNT bytes of NOPs to WHERE with the maximum size of a
1365 single NOP instruction LIMIT. */
1368 i386_generate_nops (fragS
*fragP
, char *where
, offsetT count
, int limit
)
1370 const unsigned char *const *patt
= NULL
;
1371 int max_single_nop_size
;
1372 /* Maximum number of NOPs before switching to jump over NOPs. */
1373 int max_number_of_nops
;
1375 switch (fragP
->fr_type
)
1384 /* We need to decide which NOP sequence to use for 32bit and
1385 64bit. When -mtune= is used:
1387 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1388 PROCESSOR_GENERIC32, f32_patt will be used.
1389 2. For the rest, alt_patt will be used.
1391 When -mtune= isn't used, alt_patt will be used if
1392 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
1395 When -march= or .arch is used, we can't use anything beyond
1396 cpu_arch_isa_flags. */
1398 if (flag_code
== CODE_16BIT
)
1401 max_single_nop_size
= sizeof (f16_patt
) / sizeof (f16_patt
[0]);
1402 /* Limit number of NOPs to 2 in 16-bit mode. */
1403 max_number_of_nops
= 2;
1407 if (fragP
->tc_frag_data
.isa
== PROCESSOR_UNKNOWN
)
1409 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1410 switch (cpu_arch_tune
)
1412 case PROCESSOR_UNKNOWN
:
1413 /* We use cpu_arch_isa_flags to check if we SHOULD
1414 optimize with nops. */
1415 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1420 case PROCESSOR_PENTIUM4
:
1421 case PROCESSOR_NOCONA
:
1422 case PROCESSOR_CORE
:
1423 case PROCESSOR_CORE2
:
1424 case PROCESSOR_COREI7
:
1425 case PROCESSOR_L1OM
:
1426 case PROCESSOR_K1OM
:
1427 case PROCESSOR_GENERIC64
:
1429 case PROCESSOR_ATHLON
:
1431 case PROCESSOR_AMDFAM10
:
1433 case PROCESSOR_ZNVER
:
1437 case PROCESSOR_I386
:
1438 case PROCESSOR_I486
:
1439 case PROCESSOR_PENTIUM
:
1440 case PROCESSOR_PENTIUMPRO
:
1441 case PROCESSOR_IAMCU
:
1442 case PROCESSOR_GENERIC32
:
1449 switch (fragP
->tc_frag_data
.tune
)
1451 case PROCESSOR_UNKNOWN
:
1452 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1453 PROCESSOR_UNKNOWN. */
1457 case PROCESSOR_I386
:
1458 case PROCESSOR_I486
:
1459 case PROCESSOR_PENTIUM
:
1460 case PROCESSOR_IAMCU
:
1462 case PROCESSOR_ATHLON
:
1464 case PROCESSOR_AMDFAM10
:
1466 case PROCESSOR_ZNVER
:
1468 case PROCESSOR_GENERIC32
:
1469 /* We use cpu_arch_isa_flags to check if we CAN optimize
1471 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1476 case PROCESSOR_PENTIUMPRO
:
1477 case PROCESSOR_PENTIUM4
:
1478 case PROCESSOR_NOCONA
:
1479 case PROCESSOR_CORE
:
1480 case PROCESSOR_CORE2
:
1481 case PROCESSOR_COREI7
:
1482 case PROCESSOR_L1OM
:
1483 case PROCESSOR_K1OM
:
1484 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1489 case PROCESSOR_GENERIC64
:
1495 if (patt
== f32_patt
)
1497 max_single_nop_size
= sizeof (f32_patt
) / sizeof (f32_patt
[0]);
1498 /* Limit number of NOPs to 2 for older processors. */
1499 max_number_of_nops
= 2;
1503 max_single_nop_size
= sizeof (alt_patt
) / sizeof (alt_patt
[0]);
1504 /* Limit number of NOPs to 7 for newer processors. */
1505 max_number_of_nops
= 7;
1510 limit
= max_single_nop_size
;
1512 if (fragP
->fr_type
== rs_fill_nop
)
1514 /* Output NOPs for .nop directive. */
1515 if (limit
> max_single_nop_size
)
1517 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
1518 _("invalid single nop size: %d "
1519 "(expect within [0, %d])"),
1520 limit
, max_single_nop_size
);
1525 fragP
->fr_var
= count
;
1527 if ((count
/ max_single_nop_size
) > max_number_of_nops
)
1529 /* Generate jump over NOPs. */
1530 offsetT disp
= count
- 2;
1531 if (fits_in_imm7 (disp
))
1533 /* Use "jmp disp8" if possible. */
1535 where
[0] = jump_disp8
[0];
1541 unsigned int size_of_jump
;
1543 if (flag_code
== CODE_16BIT
)
1545 where
[0] = jump16_disp32
[0];
1546 where
[1] = jump16_disp32
[1];
1551 where
[0] = jump32_disp32
[0];
1555 count
-= size_of_jump
+ 4;
1556 if (!fits_in_imm31 (count
))
1558 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
1559 _("jump over nop padding out of range"));
1563 md_number_to_chars (where
+ size_of_jump
, count
, 4);
1564 where
+= size_of_jump
+ 4;
1568 /* Generate multiple NOPs. */
1569 i386_output_nops (where
, patt
, count
, limit
);
1573 operand_type_all_zero (const union i386_operand_type
*x
)
1575 switch (ARRAY_SIZE(x
->array
))
1586 return !x
->array
[0];
1593 operand_type_set (union i386_operand_type
*x
, unsigned int v
)
1595 switch (ARRAY_SIZE(x
->array
))
1613 operand_type_equal (const union i386_operand_type
*x
,
1614 const union i386_operand_type
*y
)
1616 switch (ARRAY_SIZE(x
->array
))
1619 if (x
->array
[2] != y
->array
[2])
1623 if (x
->array
[1] != y
->array
[1])
1627 return x
->array
[0] == y
->array
[0];
1635 cpu_flags_all_zero (const union i386_cpu_flags
*x
)
1637 switch (ARRAY_SIZE(x
->array
))
1652 return !x
->array
[0];
1659 cpu_flags_equal (const union i386_cpu_flags
*x
,
1660 const union i386_cpu_flags
*y
)
1662 switch (ARRAY_SIZE(x
->array
))
1665 if (x
->array
[3] != y
->array
[3])
1669 if (x
->array
[2] != y
->array
[2])
1673 if (x
->array
[1] != y
->array
[1])
1677 return x
->array
[0] == y
->array
[0];
1685 cpu_flags_check_cpu64 (i386_cpu_flags f
)
1687 return !((flag_code
== CODE_64BIT
&& f
.bitfield
.cpuno64
)
1688 || (flag_code
!= CODE_64BIT
&& f
.bitfield
.cpu64
));
1691 static INLINE i386_cpu_flags
1692 cpu_flags_and (i386_cpu_flags x
, i386_cpu_flags y
)
1694 switch (ARRAY_SIZE (x
.array
))
1697 x
.array
[3] &= y
.array
[3];
1700 x
.array
[2] &= y
.array
[2];
1703 x
.array
[1] &= y
.array
[1];
1706 x
.array
[0] &= y
.array
[0];
1714 static INLINE i386_cpu_flags
1715 cpu_flags_or (i386_cpu_flags x
, i386_cpu_flags y
)
1717 switch (ARRAY_SIZE (x
.array
))
1720 x
.array
[3] |= y
.array
[3];
1723 x
.array
[2] |= y
.array
[2];
1726 x
.array
[1] |= y
.array
[1];
1729 x
.array
[0] |= y
.array
[0];
1737 static INLINE i386_cpu_flags
1738 cpu_flags_and_not (i386_cpu_flags x
, i386_cpu_flags y
)
1740 switch (ARRAY_SIZE (x
.array
))
1743 x
.array
[3] &= ~y
.array
[3];
1746 x
.array
[2] &= ~y
.array
[2];
1749 x
.array
[1] &= ~y
.array
[1];
1752 x
.array
[0] &= ~y
.array
[0];
1760 #define CPU_FLAGS_ARCH_MATCH 0x1
1761 #define CPU_FLAGS_64BIT_MATCH 0x2
1763 #define CPU_FLAGS_PERFECT_MATCH \
1764 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_64BIT_MATCH)
1766 /* Return CPU flags match bits. */
1769 cpu_flags_match (const insn_template
*t
)
1771 i386_cpu_flags x
= t
->cpu_flags
;
1772 int match
= cpu_flags_check_cpu64 (x
) ? CPU_FLAGS_64BIT_MATCH
: 0;
1774 x
.bitfield
.cpu64
= 0;
1775 x
.bitfield
.cpuno64
= 0;
1777 if (cpu_flags_all_zero (&x
))
1779 /* This instruction is available on all archs. */
1780 match
|= CPU_FLAGS_ARCH_MATCH
;
1784 /* This instruction is available only on some archs. */
1785 i386_cpu_flags cpu
= cpu_arch_flags
;
1787 /* AVX512VL is no standalone feature - match it and then strip it. */
1788 if (x
.bitfield
.cpuavx512vl
&& !cpu
.bitfield
.cpuavx512vl
)
1790 x
.bitfield
.cpuavx512vl
= 0;
1792 cpu
= cpu_flags_and (x
, cpu
);
1793 if (!cpu_flags_all_zero (&cpu
))
1795 if (x
.bitfield
.cpuavx
)
1797 /* We need to check a few extra flags with AVX. */
1798 if (cpu
.bitfield
.cpuavx
1799 && (!t
->opcode_modifier
.sse2avx
|| sse2avx
)
1800 && (!x
.bitfield
.cpuaes
|| cpu
.bitfield
.cpuaes
)
1801 && (!x
.bitfield
.cpugfni
|| cpu
.bitfield
.cpugfni
)
1802 && (!x
.bitfield
.cpupclmul
|| cpu
.bitfield
.cpupclmul
))
1803 match
|= CPU_FLAGS_ARCH_MATCH
;
1805 else if (x
.bitfield
.cpuavx512f
)
1807 /* We need to check a few extra flags with AVX512F. */
1808 if (cpu
.bitfield
.cpuavx512f
1809 && (!x
.bitfield
.cpugfni
|| cpu
.bitfield
.cpugfni
)
1810 && (!x
.bitfield
.cpuvaes
|| cpu
.bitfield
.cpuvaes
)
1811 && (!x
.bitfield
.cpuvpclmulqdq
|| cpu
.bitfield
.cpuvpclmulqdq
))
1812 match
|= CPU_FLAGS_ARCH_MATCH
;
1815 match
|= CPU_FLAGS_ARCH_MATCH
;
1821 static INLINE i386_operand_type
1822 operand_type_and (i386_operand_type x
, i386_operand_type y
)
1824 switch (ARRAY_SIZE (x
.array
))
1827 x
.array
[2] &= y
.array
[2];
1830 x
.array
[1] &= y
.array
[1];
1833 x
.array
[0] &= y
.array
[0];
1841 static INLINE i386_operand_type
1842 operand_type_and_not (i386_operand_type x
, i386_operand_type y
)
1844 switch (ARRAY_SIZE (x
.array
))
1847 x
.array
[2] &= ~y
.array
[2];
1850 x
.array
[1] &= ~y
.array
[1];
1853 x
.array
[0] &= ~y
.array
[0];
1861 static INLINE i386_operand_type
1862 operand_type_or (i386_operand_type x
, i386_operand_type y
)
1864 switch (ARRAY_SIZE (x
.array
))
1867 x
.array
[2] |= y
.array
[2];
1870 x
.array
[1] |= y
.array
[1];
1873 x
.array
[0] |= y
.array
[0];
1881 static INLINE i386_operand_type
1882 operand_type_xor (i386_operand_type x
, i386_operand_type y
)
1884 switch (ARRAY_SIZE (x
.array
))
1887 x
.array
[2] ^= y
.array
[2];
1890 x
.array
[1] ^= y
.array
[1];
1893 x
.array
[0] ^= y
.array
[0];
1901 static const i386_operand_type disp16
= OPERAND_TYPE_DISP16
;
1902 static const i386_operand_type disp32
= OPERAND_TYPE_DISP32
;
1903 static const i386_operand_type disp32s
= OPERAND_TYPE_DISP32S
;
1904 static const i386_operand_type disp16_32
= OPERAND_TYPE_DISP16_32
;
1905 static const i386_operand_type anydisp
1906 = OPERAND_TYPE_ANYDISP
;
1907 static const i386_operand_type regxmm
= OPERAND_TYPE_REGXMM
;
1908 static const i386_operand_type regmask
= OPERAND_TYPE_REGMASK
;
1909 static const i386_operand_type imm8
= OPERAND_TYPE_IMM8
;
1910 static const i386_operand_type imm8s
= OPERAND_TYPE_IMM8S
;
1911 static const i386_operand_type imm16
= OPERAND_TYPE_IMM16
;
1912 static const i386_operand_type imm32
= OPERAND_TYPE_IMM32
;
1913 static const i386_operand_type imm32s
= OPERAND_TYPE_IMM32S
;
1914 static const i386_operand_type imm64
= OPERAND_TYPE_IMM64
;
1915 static const i386_operand_type imm16_32
= OPERAND_TYPE_IMM16_32
;
1916 static const i386_operand_type imm16_32s
= OPERAND_TYPE_IMM16_32S
;
1917 static const i386_operand_type imm16_32_32s
= OPERAND_TYPE_IMM16_32_32S
;
1928 operand_type_check (i386_operand_type t
, enum operand_type c
)
1933 return t
.bitfield
.reg
;
1936 return (t
.bitfield
.imm8
1940 || t
.bitfield
.imm32s
1941 || t
.bitfield
.imm64
);
1944 return (t
.bitfield
.disp8
1945 || t
.bitfield
.disp16
1946 || t
.bitfield
.disp32
1947 || t
.bitfield
.disp32s
1948 || t
.bitfield
.disp64
);
1951 return (t
.bitfield
.disp8
1952 || t
.bitfield
.disp16
1953 || t
.bitfield
.disp32
1954 || t
.bitfield
.disp32s
1955 || t
.bitfield
.disp64
1956 || t
.bitfield
.baseindex
);
1965 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit/80bit size
1966 between operand GIVEN and opeand WANTED for instruction template T. */
1969 match_operand_size (const insn_template
*t
, unsigned int wanted
,
1972 return !((i
.types
[given
].bitfield
.byte
1973 && !t
->operand_types
[wanted
].bitfield
.byte
)
1974 || (i
.types
[given
].bitfield
.word
1975 && !t
->operand_types
[wanted
].bitfield
.word
)
1976 || (i
.types
[given
].bitfield
.dword
1977 && !t
->operand_types
[wanted
].bitfield
.dword
)
1978 || (i
.types
[given
].bitfield
.qword
1979 && !t
->operand_types
[wanted
].bitfield
.qword
)
1980 || (i
.types
[given
].bitfield
.tbyte
1981 && !t
->operand_types
[wanted
].bitfield
.tbyte
));
1984 /* Return 1 if there is no conflict in SIMD register between operand
1985 GIVEN and opeand WANTED for instruction template T. */
1988 match_simd_size (const insn_template
*t
, unsigned int wanted
,
1991 return !((i
.types
[given
].bitfield
.xmmword
1992 && !t
->operand_types
[wanted
].bitfield
.xmmword
)
1993 || (i
.types
[given
].bitfield
.ymmword
1994 && !t
->operand_types
[wanted
].bitfield
.ymmword
)
1995 || (i
.types
[given
].bitfield
.zmmword
1996 && !t
->operand_types
[wanted
].bitfield
.zmmword
));
1999 /* Return 1 if there is no conflict in any size between operand GIVEN
2000 and opeand WANTED for instruction template T. */
2003 match_mem_size (const insn_template
*t
, unsigned int wanted
,
2006 return (match_operand_size (t
, wanted
, given
)
2007 && !((i
.types
[given
].bitfield
.unspecified
2009 && !t
->operand_types
[wanted
].bitfield
.unspecified
)
2010 || (i
.types
[given
].bitfield
.fword
2011 && !t
->operand_types
[wanted
].bitfield
.fword
)
2012 /* For scalar opcode templates to allow register and memory
2013 operands at the same time, some special casing is needed
2014 here. Also for v{,p}broadcast*, {,v}pmov{s,z}*, and
2015 down-conversion vpmov*. */
2016 || ((t
->operand_types
[wanted
].bitfield
.regsimd
2017 && !t
->opcode_modifier
.broadcast
2018 && (t
->operand_types
[wanted
].bitfield
.byte
2019 || t
->operand_types
[wanted
].bitfield
.word
2020 || t
->operand_types
[wanted
].bitfield
.dword
2021 || t
->operand_types
[wanted
].bitfield
.qword
))
2022 ? (i
.types
[given
].bitfield
.xmmword
2023 || i
.types
[given
].bitfield
.ymmword
2024 || i
.types
[given
].bitfield
.zmmword
)
2025 : !match_simd_size(t
, wanted
, given
))));
2028 /* Return value has MATCH_STRAIGHT set if there is no size conflict on any
2029 operands for instruction template T, and it has MATCH_REVERSE set if there
2030 is no size conflict on any operands for the template with operands reversed
2031 (and the template allows for reversing in the first place). */
2033 #define MATCH_STRAIGHT 1
2034 #define MATCH_REVERSE 2
2036 static INLINE
unsigned int
2037 operand_size_match (const insn_template
*t
)
2039 unsigned int j
, match
= MATCH_STRAIGHT
;
2041 /* Don't check jump instructions. */
2042 if (t
->opcode_modifier
.jump
2043 || t
->opcode_modifier
.jumpbyte
2044 || t
->opcode_modifier
.jumpdword
2045 || t
->opcode_modifier
.jumpintersegment
)
2048 /* Check memory and accumulator operand size. */
2049 for (j
= 0; j
< i
.operands
; j
++)
2051 if (!i
.types
[j
].bitfield
.reg
&& !i
.types
[j
].bitfield
.regsimd
2052 && t
->operand_types
[j
].bitfield
.anysize
)
2055 if (t
->operand_types
[j
].bitfield
.reg
2056 && !match_operand_size (t
, j
, j
))
2062 if (t
->operand_types
[j
].bitfield
.regsimd
2063 && !match_simd_size (t
, j
, j
))
2069 if (t
->operand_types
[j
].bitfield
.acc
2070 && (!match_operand_size (t
, j
, j
) || !match_simd_size (t
, j
, j
)))
2076 if ((i
.flags
[j
] & Operand_Mem
) && !match_mem_size (t
, j
, j
))
2083 if (!t
->opcode_modifier
.d
)
2087 i
.error
= operand_size_mismatch
;
2091 /* Check reverse. */
2092 gas_assert (i
.operands
>= 2 && i
.operands
<= 3);
2094 for (j
= 0; j
< i
.operands
; j
++)
2096 unsigned int given
= i
.operands
- j
- 1;
2098 if (t
->operand_types
[j
].bitfield
.reg
2099 && !match_operand_size (t
, j
, given
))
2102 if (t
->operand_types
[j
].bitfield
.regsimd
2103 && !match_simd_size (t
, j
, given
))
2106 if (t
->operand_types
[j
].bitfield
.acc
2107 && (!match_operand_size (t
, j
, given
)
2108 || !match_simd_size (t
, j
, given
)))
2111 if ((i
.flags
[given
] & Operand_Mem
) && !match_mem_size (t
, j
, given
))
2115 return match
| MATCH_REVERSE
;
2119 operand_type_match (i386_operand_type overlap
,
2120 i386_operand_type given
)
2122 i386_operand_type temp
= overlap
;
2124 temp
.bitfield
.jumpabsolute
= 0;
2125 temp
.bitfield
.unspecified
= 0;
2126 temp
.bitfield
.byte
= 0;
2127 temp
.bitfield
.word
= 0;
2128 temp
.bitfield
.dword
= 0;
2129 temp
.bitfield
.fword
= 0;
2130 temp
.bitfield
.qword
= 0;
2131 temp
.bitfield
.tbyte
= 0;
2132 temp
.bitfield
.xmmword
= 0;
2133 temp
.bitfield
.ymmword
= 0;
2134 temp
.bitfield
.zmmword
= 0;
2135 if (operand_type_all_zero (&temp
))
2138 if (given
.bitfield
.baseindex
== overlap
.bitfield
.baseindex
2139 && given
.bitfield
.jumpabsolute
== overlap
.bitfield
.jumpabsolute
)
2143 i
.error
= operand_type_mismatch
;
2147 /* If given types g0 and g1 are registers they must be of the same type
2148 unless the expected operand type register overlap is null.
2149 Memory operand size of certain SIMD instructions is also being checked
2153 operand_type_register_match (i386_operand_type g0
,
2154 i386_operand_type t0
,
2155 i386_operand_type g1
,
2156 i386_operand_type t1
)
2158 if (!g0
.bitfield
.reg
2159 && !g0
.bitfield
.regsimd
2160 && (!operand_type_check (g0
, anymem
)
2161 || g0
.bitfield
.unspecified
2162 || !t0
.bitfield
.regsimd
))
2165 if (!g1
.bitfield
.reg
2166 && !g1
.bitfield
.regsimd
2167 && (!operand_type_check (g1
, anymem
)
2168 || g1
.bitfield
.unspecified
2169 || !t1
.bitfield
.regsimd
))
2172 if (g0
.bitfield
.byte
== g1
.bitfield
.byte
2173 && g0
.bitfield
.word
== g1
.bitfield
.word
2174 && g0
.bitfield
.dword
== g1
.bitfield
.dword
2175 && g0
.bitfield
.qword
== g1
.bitfield
.qword
2176 && g0
.bitfield
.xmmword
== g1
.bitfield
.xmmword
2177 && g0
.bitfield
.ymmword
== g1
.bitfield
.ymmword
2178 && g0
.bitfield
.zmmword
== g1
.bitfield
.zmmword
)
2181 if (!(t0
.bitfield
.byte
& t1
.bitfield
.byte
)
2182 && !(t0
.bitfield
.word
& t1
.bitfield
.word
)
2183 && !(t0
.bitfield
.dword
& t1
.bitfield
.dword
)
2184 && !(t0
.bitfield
.qword
& t1
.bitfield
.qword
)
2185 && !(t0
.bitfield
.xmmword
& t1
.bitfield
.xmmword
)
2186 && !(t0
.bitfield
.ymmword
& t1
.bitfield
.ymmword
)
2187 && !(t0
.bitfield
.zmmword
& t1
.bitfield
.zmmword
))
2190 i
.error
= register_type_mismatch
;
2195 static INLINE
unsigned int
2196 register_number (const reg_entry
*r
)
2198 unsigned int nr
= r
->reg_num
;
2200 if (r
->reg_flags
& RegRex
)
2203 if (r
->reg_flags
& RegVRex
)
2209 static INLINE
unsigned int
2210 mode_from_disp_size (i386_operand_type t
)
2212 if (t
.bitfield
.disp8
)
2214 else if (t
.bitfield
.disp16
2215 || t
.bitfield
.disp32
2216 || t
.bitfield
.disp32s
)
2223 fits_in_signed_byte (addressT num
)
2225 return num
+ 0x80 <= 0xff;
2229 fits_in_unsigned_byte (addressT num
)
2235 fits_in_unsigned_word (addressT num
)
2237 return num
<= 0xffff;
2241 fits_in_signed_word (addressT num
)
2243 return num
+ 0x8000 <= 0xffff;
2247 fits_in_signed_long (addressT num ATTRIBUTE_UNUSED
)
2252 return num
+ 0x80000000 <= 0xffffffff;
2254 } /* fits_in_signed_long() */
2257 fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED
)
2262 return num
<= 0xffffffff;
2264 } /* fits_in_unsigned_long() */
2267 fits_in_disp8 (offsetT num
)
2269 int shift
= i
.memshift
;
2275 mask
= (1 << shift
) - 1;
2277 /* Return 0 if NUM isn't properly aligned. */
2281 /* Check if NUM will fit in 8bit after shift. */
2282 return fits_in_signed_byte (num
>> shift
);
2286 fits_in_imm4 (offsetT num
)
2288 return (num
& 0xf) == num
;
2291 static i386_operand_type
2292 smallest_imm_type (offsetT num
)
2294 i386_operand_type t
;
2296 operand_type_set (&t
, 0);
2297 t
.bitfield
.imm64
= 1;
2299 if (cpu_arch_tune
!= PROCESSOR_I486
&& num
== 1)
2301 /* This code is disabled on the 486 because all the Imm1 forms
2302 in the opcode table are slower on the i486. They're the
2303 versions with the implicitly specified single-position
2304 displacement, which has another syntax if you really want to
2306 t
.bitfield
.imm1
= 1;
2307 t
.bitfield
.imm8
= 1;
2308 t
.bitfield
.imm8s
= 1;
2309 t
.bitfield
.imm16
= 1;
2310 t
.bitfield
.imm32
= 1;
2311 t
.bitfield
.imm32s
= 1;
2313 else if (fits_in_signed_byte (num
))
2315 t
.bitfield
.imm8
= 1;
2316 t
.bitfield
.imm8s
= 1;
2317 t
.bitfield
.imm16
= 1;
2318 t
.bitfield
.imm32
= 1;
2319 t
.bitfield
.imm32s
= 1;
2321 else if (fits_in_unsigned_byte (num
))
2323 t
.bitfield
.imm8
= 1;
2324 t
.bitfield
.imm16
= 1;
2325 t
.bitfield
.imm32
= 1;
2326 t
.bitfield
.imm32s
= 1;
2328 else if (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
2330 t
.bitfield
.imm16
= 1;
2331 t
.bitfield
.imm32
= 1;
2332 t
.bitfield
.imm32s
= 1;
2334 else if (fits_in_signed_long (num
))
2336 t
.bitfield
.imm32
= 1;
2337 t
.bitfield
.imm32s
= 1;
2339 else if (fits_in_unsigned_long (num
))
2340 t
.bitfield
.imm32
= 1;
2346 offset_in_range (offsetT val
, int size
)
2352 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
2353 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
2354 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
2356 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
2362 /* If BFD64, sign extend val for 32bit address mode. */
2363 if (flag_code
!= CODE_64BIT
2364 || i
.prefix
[ADDR_PREFIX
])
2365 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
2366 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
2369 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
2371 char buf1
[40], buf2
[40];
2373 sprint_value (buf1
, val
);
2374 sprint_value (buf2
, val
& mask
);
2375 as_warn (_("%s shortened to %s"), buf1
, buf2
);
2390 a. PREFIX_EXIST if attempting to add a prefix where one from the
2391 same class already exists.
2392 b. PREFIX_LOCK if lock prefix is added.
2393 c. PREFIX_REP if rep/repne prefix is added.
2394 d. PREFIX_DS if ds prefix is added.
2395 e. PREFIX_OTHER if other prefix is added.
2398 static enum PREFIX_GROUP
2399 add_prefix (unsigned int prefix
)
2401 enum PREFIX_GROUP ret
= PREFIX_OTHER
;
2404 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
2405 && flag_code
== CODE_64BIT
)
2407 if ((i
.prefix
[REX_PREFIX
] & prefix
& REX_W
)
2408 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_R
)
2409 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_X
)
2410 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_B
))
2421 case DS_PREFIX_OPCODE
:
2424 case CS_PREFIX_OPCODE
:
2425 case ES_PREFIX_OPCODE
:
2426 case FS_PREFIX_OPCODE
:
2427 case GS_PREFIX_OPCODE
:
2428 case SS_PREFIX_OPCODE
:
2432 case REPNE_PREFIX_OPCODE
:
2433 case REPE_PREFIX_OPCODE
:
2438 case LOCK_PREFIX_OPCODE
:
2447 case ADDR_PREFIX_OPCODE
:
2451 case DATA_PREFIX_OPCODE
:
2455 if (i
.prefix
[q
] != 0)
2463 i
.prefix
[q
] |= prefix
;
2466 as_bad (_("same type of prefix used twice"));
2472 update_code_flag (int value
, int check
)
2474 PRINTF_LIKE ((*as_error
));
2476 flag_code
= (enum flag_code
) value
;
2477 if (flag_code
== CODE_64BIT
)
2479 cpu_arch_flags
.bitfield
.cpu64
= 1;
2480 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2484 cpu_arch_flags
.bitfield
.cpu64
= 0;
2485 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2487 if (value
== CODE_64BIT
&& !cpu_arch_flags
.bitfield
.cpulm
)
2490 as_error
= as_fatal
;
2493 (*as_error
) (_("64bit mode not supported on `%s'."),
2494 cpu_arch_name
? cpu_arch_name
: default_arch
);
2496 if (value
== CODE_32BIT
&& !cpu_arch_flags
.bitfield
.cpui386
)
2499 as_error
= as_fatal
;
2502 (*as_error
) (_("32bit mode not supported on `%s'."),
2503 cpu_arch_name
? cpu_arch_name
: default_arch
);
2505 stackop_size
= '\0';
2509 set_code_flag (int value
)
2511 update_code_flag (value
, 0);
2515 set_16bit_gcc_code_flag (int new_code_flag
)
2517 flag_code
= (enum flag_code
) new_code_flag
;
2518 if (flag_code
!= CODE_16BIT
)
2520 cpu_arch_flags
.bitfield
.cpu64
= 0;
2521 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2522 stackop_size
= LONG_MNEM_SUFFIX
;
2526 set_intel_syntax (int syntax_flag
)
2528 /* Find out if register prefixing is specified. */
2529 int ask_naked_reg
= 0;
2532 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2535 int e
= get_symbol_name (&string
);
2537 if (strcmp (string
, "prefix") == 0)
2539 else if (strcmp (string
, "noprefix") == 0)
2542 as_bad (_("bad argument to syntax directive."));
2543 (void) restore_line_pointer (e
);
2545 demand_empty_rest_of_line ();
2547 intel_syntax
= syntax_flag
;
2549 if (ask_naked_reg
== 0)
2550 allow_naked_reg
= (intel_syntax
2551 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
2553 allow_naked_reg
= (ask_naked_reg
< 0);
2555 expr_set_rank (O_full_ptr
, syntax_flag
? 10 : 0);
2557 identifier_chars
['%'] = intel_syntax
&& allow_naked_reg
? '%' : 0;
2558 identifier_chars
['$'] = intel_syntax
? '$' : 0;
2559 register_prefix
= allow_naked_reg
? "" : "%";
2563 set_intel_mnemonic (int mnemonic_flag
)
2565 intel_mnemonic
= mnemonic_flag
;
2569 set_allow_index_reg (int flag
)
2571 allow_index_reg
= flag
;
2575 set_check (int what
)
2577 enum check_kind
*kind
;
2582 kind
= &operand_check
;
2593 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2596 int e
= get_symbol_name (&string
);
2598 if (strcmp (string
, "none") == 0)
2600 else if (strcmp (string
, "warning") == 0)
2601 *kind
= check_warning
;
2602 else if (strcmp (string
, "error") == 0)
2603 *kind
= check_error
;
2605 as_bad (_("bad argument to %s_check directive."), str
);
2606 (void) restore_line_pointer (e
);
2609 as_bad (_("missing argument for %s_check directive"), str
);
2611 demand_empty_rest_of_line ();
2615 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED
,
2616 i386_cpu_flags new_flag ATTRIBUTE_UNUSED
)
2618 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2619 static const char *arch
;
2621 /* Intel LIOM is only supported on ELF. */
2627 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2628 use default_arch. */
2629 arch
= cpu_arch_name
;
2631 arch
= default_arch
;
2634 /* If we are targeting Intel MCU, we must enable it. */
2635 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_IAMCU
2636 || new_flag
.bitfield
.cpuiamcu
)
2639 /* If we are targeting Intel L1OM, we must enable it. */
2640 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_L1OM
2641 || new_flag
.bitfield
.cpul1om
)
2644 /* If we are targeting Intel K1OM, we must enable it. */
2645 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_K1OM
2646 || new_flag
.bitfield
.cpuk1om
)
2649 as_bad (_("`%s' is not supported on `%s'"), name
, arch
);
2654 set_cpu_arch (int dummy ATTRIBUTE_UNUSED
)
2658 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2661 int e
= get_symbol_name (&string
);
2663 i386_cpu_flags flags
;
2665 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
2667 if (strcmp (string
, cpu_arch
[j
].name
) == 0)
2669 check_cpu_arch_compatible (string
, cpu_arch
[j
].flags
);
2673 cpu_arch_name
= cpu_arch
[j
].name
;
2674 cpu_sub_arch_name
= NULL
;
2675 cpu_arch_flags
= cpu_arch
[j
].flags
;
2676 if (flag_code
== CODE_64BIT
)
2678 cpu_arch_flags
.bitfield
.cpu64
= 1;
2679 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2683 cpu_arch_flags
.bitfield
.cpu64
= 0;
2684 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2686 cpu_arch_isa
= cpu_arch
[j
].type
;
2687 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
2688 if (!cpu_arch_tune_set
)
2690 cpu_arch_tune
= cpu_arch_isa
;
2691 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
2696 flags
= cpu_flags_or (cpu_arch_flags
,
2699 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2701 if (cpu_sub_arch_name
)
2703 char *name
= cpu_sub_arch_name
;
2704 cpu_sub_arch_name
= concat (name
,
2706 (const char *) NULL
);
2710 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
2711 cpu_arch_flags
= flags
;
2712 cpu_arch_isa_flags
= flags
;
2716 = cpu_flags_or (cpu_arch_isa_flags
,
2718 (void) restore_line_pointer (e
);
2719 demand_empty_rest_of_line ();
2724 if (*string
== '.' && j
>= ARRAY_SIZE (cpu_arch
))
2726 /* Disable an ISA extension. */
2727 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
2728 if (strcmp (string
+ 1, cpu_noarch
[j
].name
) == 0)
2730 flags
= cpu_flags_and_not (cpu_arch_flags
,
2731 cpu_noarch
[j
].flags
);
2732 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2734 if (cpu_sub_arch_name
)
2736 char *name
= cpu_sub_arch_name
;
2737 cpu_sub_arch_name
= concat (name
, string
,
2738 (const char *) NULL
);
2742 cpu_sub_arch_name
= xstrdup (string
);
2743 cpu_arch_flags
= flags
;
2744 cpu_arch_isa_flags
= flags
;
2746 (void) restore_line_pointer (e
);
2747 demand_empty_rest_of_line ();
2751 j
= ARRAY_SIZE (cpu_arch
);
2754 if (j
>= ARRAY_SIZE (cpu_arch
))
2755 as_bad (_("no such architecture: `%s'"), string
);
2757 *input_line_pointer
= e
;
2760 as_bad (_("missing cpu architecture"));
2762 no_cond_jump_promotion
= 0;
2763 if (*input_line_pointer
== ','
2764 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
2769 ++input_line_pointer
;
2770 e
= get_symbol_name (&string
);
2772 if (strcmp (string
, "nojumps") == 0)
2773 no_cond_jump_promotion
= 1;
2774 else if (strcmp (string
, "jumps") == 0)
2777 as_bad (_("no such architecture modifier: `%s'"), string
);
2779 (void) restore_line_pointer (e
);
2782 demand_empty_rest_of_line ();
2785 enum bfd_architecture
2788 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2790 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2791 || flag_code
!= CODE_64BIT
)
2792 as_fatal (_("Intel L1OM is 64bit ELF only"));
2793 return bfd_arch_l1om
;
2795 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2797 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2798 || flag_code
!= CODE_64BIT
)
2799 as_fatal (_("Intel K1OM is 64bit ELF only"));
2800 return bfd_arch_k1om
;
2802 else if (cpu_arch_isa
== PROCESSOR_IAMCU
)
2804 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2805 || flag_code
== CODE_64BIT
)
2806 as_fatal (_("Intel MCU is 32bit ELF only"));
2807 return bfd_arch_iamcu
;
2810 return bfd_arch_i386
;
2816 if (!strncmp (default_arch
, "x86_64", 6))
2818 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2820 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2821 || default_arch
[6] != '\0')
2822 as_fatal (_("Intel L1OM is 64bit ELF only"));
2823 return bfd_mach_l1om
;
2825 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2827 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2828 || default_arch
[6] != '\0')
2829 as_fatal (_("Intel K1OM is 64bit ELF only"));
2830 return bfd_mach_k1om
;
2832 else if (default_arch
[6] == '\0')
2833 return bfd_mach_x86_64
;
2835 return bfd_mach_x64_32
;
2837 else if (!strcmp (default_arch
, "i386")
2838 || !strcmp (default_arch
, "iamcu"))
2840 if (cpu_arch_isa
== PROCESSOR_IAMCU
)
2842 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
2843 as_fatal (_("Intel MCU is 32bit ELF only"));
2844 return bfd_mach_i386_iamcu
;
2847 return bfd_mach_i386_i386
;
2850 as_fatal (_("unknown architecture"));
2856 const char *hash_err
;
2858 /* Support pseudo prefixes like {disp32}. */
2859 lex_type
['{'] = LEX_BEGIN_NAME
;
2861 /* Initialize op_hash hash table. */
2862 op_hash
= hash_new ();
2865 const insn_template
*optab
;
2866 templates
*core_optab
;
2868 /* Setup for loop. */
2870 core_optab
= XNEW (templates
);
2871 core_optab
->start
= optab
;
2876 if (optab
->name
== NULL
2877 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
2879 /* different name --> ship out current template list;
2880 add to hash table; & begin anew. */
2881 core_optab
->end
= optab
;
2882 hash_err
= hash_insert (op_hash
,
2884 (void *) core_optab
);
2887 as_fatal (_("can't hash %s: %s"),
2891 if (optab
->name
== NULL
)
2893 core_optab
= XNEW (templates
);
2894 core_optab
->start
= optab
;
2899 /* Initialize reg_hash hash table. */
2900 reg_hash
= hash_new ();
2902 const reg_entry
*regtab
;
2903 unsigned int regtab_size
= i386_regtab_size
;
2905 for (regtab
= i386_regtab
; regtab_size
--; regtab
++)
2907 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (void *) regtab
);
2909 as_fatal (_("can't hash %s: %s"),
2915 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
2920 for (c
= 0; c
< 256; c
++)
2925 mnemonic_chars
[c
] = c
;
2926 register_chars
[c
] = c
;
2927 operand_chars
[c
] = c
;
2929 else if (ISLOWER (c
))
2931 mnemonic_chars
[c
] = c
;
2932 register_chars
[c
] = c
;
2933 operand_chars
[c
] = c
;
2935 else if (ISUPPER (c
))
2937 mnemonic_chars
[c
] = TOLOWER (c
);
2938 register_chars
[c
] = mnemonic_chars
[c
];
2939 operand_chars
[c
] = c
;
2941 else if (c
== '{' || c
== '}')
2943 mnemonic_chars
[c
] = c
;
2944 operand_chars
[c
] = c
;
2947 if (ISALPHA (c
) || ISDIGIT (c
))
2948 identifier_chars
[c
] = c
;
2951 identifier_chars
[c
] = c
;
2952 operand_chars
[c
] = c
;
2957 identifier_chars
['@'] = '@';
2960 identifier_chars
['?'] = '?';
2961 operand_chars
['?'] = '?';
2963 digit_chars
['-'] = '-';
2964 mnemonic_chars
['_'] = '_';
2965 mnemonic_chars
['-'] = '-';
2966 mnemonic_chars
['.'] = '.';
2967 identifier_chars
['_'] = '_';
2968 identifier_chars
['.'] = '.';
2970 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
2971 operand_chars
[(unsigned char) *p
] = *p
;
2974 if (flag_code
== CODE_64BIT
)
2976 #if defined (OBJ_COFF) && defined (TE_PE)
2977 x86_dwarf2_return_column
= (OUTPUT_FLAVOR
== bfd_target_coff_flavour
2980 x86_dwarf2_return_column
= 16;
2982 x86_cie_data_alignment
= -8;
2986 x86_dwarf2_return_column
= 8;
2987 x86_cie_data_alignment
= -4;
2992 i386_print_statistics (FILE *file
)
2994 hash_print_statistics (file
, "i386 opcode", op_hash
);
2995 hash_print_statistics (file
, "i386 register", reg_hash
);
3000 /* Debugging routines for md_assemble. */
3001 static void pte (insn_template
*);
3002 static void pt (i386_operand_type
);
3003 static void pe (expressionS
*);
3004 static void ps (symbolS
*);
3007 pi (const char *line
, i386_insn
*x
)
3011 fprintf (stdout
, "%s: template ", line
);
3013 fprintf (stdout
, " address: base %s index %s scale %x\n",
3014 x
->base_reg
? x
->base_reg
->reg_name
: "none",
3015 x
->index_reg
? x
->index_reg
->reg_name
: "none",
3016 x
->log2_scale_factor
);
3017 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
3018 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
3019 fprintf (stdout
, " sib: base %x index %x scale %x\n",
3020 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
3021 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
3022 (x
->rex
& REX_W
) != 0,
3023 (x
->rex
& REX_R
) != 0,
3024 (x
->rex
& REX_X
) != 0,
3025 (x
->rex
& REX_B
) != 0);
3026 for (j
= 0; j
< x
->operands
; j
++)
3028 fprintf (stdout
, " #%d: ", j
+ 1);
3030 fprintf (stdout
, "\n");
3031 if (x
->types
[j
].bitfield
.reg
3032 || x
->types
[j
].bitfield
.regmmx
3033 || x
->types
[j
].bitfield
.regsimd
3034 || x
->types
[j
].bitfield
.sreg
3035 || x
->types
[j
].bitfield
.control
3036 || x
->types
[j
].bitfield
.debug
3037 || x
->types
[j
].bitfield
.test
)
3038 fprintf (stdout
, "%s\n", x
->op
[j
].regs
->reg_name
);
3039 if (operand_type_check (x
->types
[j
], imm
))
3041 if (operand_type_check (x
->types
[j
], disp
))
3042 pe (x
->op
[j
].disps
);
3047 pte (insn_template
*t
)
3050 fprintf (stdout
, " %d operands ", t
->operands
);
3051 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
3052 if (t
->extension_opcode
!= None
)
3053 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
3054 if (t
->opcode_modifier
.d
)
3055 fprintf (stdout
, "D");
3056 if (t
->opcode_modifier
.w
)
3057 fprintf (stdout
, "W");
3058 fprintf (stdout
, "\n");
3059 for (j
= 0; j
< t
->operands
; j
++)
3061 fprintf (stdout
, " #%d type ", j
+ 1);
3062 pt (t
->operand_types
[j
]);
3063 fprintf (stdout
, "\n");
3070 fprintf (stdout
, " operation %d\n", e
->X_op
);
3071 fprintf (stdout
, " add_number %ld (%lx)\n",
3072 (long) e
->X_add_number
, (long) e
->X_add_number
);
3073 if (e
->X_add_symbol
)
3075 fprintf (stdout
, " add_symbol ");
3076 ps (e
->X_add_symbol
);
3077 fprintf (stdout
, "\n");
3081 fprintf (stdout
, " op_symbol ");
3082 ps (e
->X_op_symbol
);
3083 fprintf (stdout
, "\n");
3090 fprintf (stdout
, "%s type %s%s",
3092 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
3093 segment_name (S_GET_SEGMENT (s
)));
3096 static struct type_name
3098 i386_operand_type mask
;
3101 const type_names
[] =
3103 { OPERAND_TYPE_REG8
, "r8" },
3104 { OPERAND_TYPE_REG16
, "r16" },
3105 { OPERAND_TYPE_REG32
, "r32" },
3106 { OPERAND_TYPE_REG64
, "r64" },
3107 { OPERAND_TYPE_ACC8
, "acc8" },
3108 { OPERAND_TYPE_ACC16
, "acc16" },
3109 { OPERAND_TYPE_ACC32
, "acc32" },
3110 { OPERAND_TYPE_ACC64
, "acc64" },
3111 { OPERAND_TYPE_IMM8
, "i8" },
3112 { OPERAND_TYPE_IMM8
, "i8s" },
3113 { OPERAND_TYPE_IMM16
, "i16" },
3114 { OPERAND_TYPE_IMM32
, "i32" },
3115 { OPERAND_TYPE_IMM32S
, "i32s" },
3116 { OPERAND_TYPE_IMM64
, "i64" },
3117 { OPERAND_TYPE_IMM1
, "i1" },
3118 { OPERAND_TYPE_BASEINDEX
, "BaseIndex" },
3119 { OPERAND_TYPE_DISP8
, "d8" },
3120 { OPERAND_TYPE_DISP16
, "d16" },
3121 { OPERAND_TYPE_DISP32
, "d32" },
3122 { OPERAND_TYPE_DISP32S
, "d32s" },
3123 { OPERAND_TYPE_DISP64
, "d64" },
3124 { OPERAND_TYPE_INOUTPORTREG
, "InOutPortReg" },
3125 { OPERAND_TYPE_SHIFTCOUNT
, "ShiftCount" },
3126 { OPERAND_TYPE_CONTROL
, "control reg" },
3127 { OPERAND_TYPE_TEST
, "test reg" },
3128 { OPERAND_TYPE_DEBUG
, "debug reg" },
3129 { OPERAND_TYPE_FLOATREG
, "FReg" },
3130 { OPERAND_TYPE_FLOATACC
, "FAcc" },
3131 { OPERAND_TYPE_SREG
, "SReg" },
3132 { OPERAND_TYPE_JUMPABSOLUTE
, "Jump Absolute" },
3133 { OPERAND_TYPE_REGMMX
, "rMMX" },
3134 { OPERAND_TYPE_REGXMM
, "rXMM" },
3135 { OPERAND_TYPE_REGYMM
, "rYMM" },
3136 { OPERAND_TYPE_REGZMM
, "rZMM" },
3137 { OPERAND_TYPE_REGMASK
, "Mask reg" },
3138 { OPERAND_TYPE_ESSEG
, "es" },
3142 pt (i386_operand_type t
)
3145 i386_operand_type a
;
3147 for (j
= 0; j
< ARRAY_SIZE (type_names
); j
++)
3149 a
= operand_type_and (t
, type_names
[j
].mask
);
3150 if (operand_type_equal (&a
, &type_names
[j
].mask
))
3151 fprintf (stdout
, "%s, ", type_names
[j
].name
);
3156 #endif /* DEBUG386 */
3158 static bfd_reloc_code_real_type
3159 reloc (unsigned int size
,
3162 bfd_reloc_code_real_type other
)
3164 if (other
!= NO_RELOC
)
3166 reloc_howto_type
*rel
;
3171 case BFD_RELOC_X86_64_GOT32
:
3172 return BFD_RELOC_X86_64_GOT64
;
3174 case BFD_RELOC_X86_64_GOTPLT64
:
3175 return BFD_RELOC_X86_64_GOTPLT64
;
3177 case BFD_RELOC_X86_64_PLTOFF64
:
3178 return BFD_RELOC_X86_64_PLTOFF64
;
3180 case BFD_RELOC_X86_64_GOTPC32
:
3181 other
= BFD_RELOC_X86_64_GOTPC64
;
3183 case BFD_RELOC_X86_64_GOTPCREL
:
3184 other
= BFD_RELOC_X86_64_GOTPCREL64
;
3186 case BFD_RELOC_X86_64_TPOFF32
:
3187 other
= BFD_RELOC_X86_64_TPOFF64
;
3189 case BFD_RELOC_X86_64_DTPOFF32
:
3190 other
= BFD_RELOC_X86_64_DTPOFF64
;
3196 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3197 if (other
== BFD_RELOC_SIZE32
)
3200 other
= BFD_RELOC_SIZE64
;
3203 as_bad (_("there are no pc-relative size relocations"));
3209 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
3210 if (size
== 4 && (flag_code
!= CODE_64BIT
|| disallow_64bit_reloc
))
3213 rel
= bfd_reloc_type_lookup (stdoutput
, other
);
3215 as_bad (_("unknown relocation (%u)"), other
);
3216 else if (size
!= bfd_get_reloc_size (rel
))
3217 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
3218 bfd_get_reloc_size (rel
),
3220 else if (pcrel
&& !rel
->pc_relative
)
3221 as_bad (_("non-pc-relative relocation for pc-relative field"));
3222 else if ((rel
->complain_on_overflow
== complain_overflow_signed
3224 || (rel
->complain_on_overflow
== complain_overflow_unsigned
3226 as_bad (_("relocated field and relocation type differ in signedness"));
3235 as_bad (_("there are no unsigned pc-relative relocations"));
3238 case 1: return BFD_RELOC_8_PCREL
;
3239 case 2: return BFD_RELOC_16_PCREL
;
3240 case 4: return BFD_RELOC_32_PCREL
;
3241 case 8: return BFD_RELOC_64_PCREL
;
3243 as_bad (_("cannot do %u byte pc-relative relocation"), size
);
3250 case 4: return BFD_RELOC_X86_64_32S
;
3255 case 1: return BFD_RELOC_8
;
3256 case 2: return BFD_RELOC_16
;
3257 case 4: return BFD_RELOC_32
;
3258 case 8: return BFD_RELOC_64
;
3260 as_bad (_("cannot do %s %u byte relocation"),
3261 sign
> 0 ? "signed" : "unsigned", size
);
3267 /* Here we decide which fixups can be adjusted to make them relative to
3268 the beginning of the section instead of the symbol. Basically we need
3269 to make sure that the dynamic relocations are done correctly, so in
3270 some cases we force the original symbol to be used. */
3273 tc_i386_fix_adjustable (fixS
*fixP ATTRIBUTE_UNUSED
)
3275 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3279 /* Don't adjust pc-relative references to merge sections in 64-bit
3281 if (use_rela_relocations
3282 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
3286 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
3287 and changed later by validate_fix. */
3288 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
3289 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
3292 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
3293 for size relocations. */
3294 if (fixP
->fx_r_type
== BFD_RELOC_SIZE32
3295 || fixP
->fx_r_type
== BFD_RELOC_SIZE64
3296 || fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
3297 || fixP
->fx_r_type
== BFD_RELOC_386_PLT32
3298 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
3299 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32X
3300 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
3301 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
3302 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
3303 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
3304 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
3305 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
3306 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
3307 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
3308 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTDESC
3309 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_DESC_CALL
3310 || fixP
->fx_r_type
== BFD_RELOC_X86_64_PLT32
3311 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
3312 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
3313 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCRELX
3314 || fixP
->fx_r_type
== BFD_RELOC_X86_64_REX_GOTPCRELX
3315 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
3316 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
3317 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
3318 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
3319 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
3320 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
3321 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
3322 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
3323 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPC32_TLSDESC
3324 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSDESC_CALL
3325 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
3326 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
3333 intel_float_operand (const char *mnemonic
)
3335 /* Note that the value returned is meaningful only for opcodes with (memory)
3336 operands, hence the code here is free to improperly handle opcodes that
3337 have no operands (for better performance and smaller code). */
3339 if (mnemonic
[0] != 'f')
3340 return 0; /* non-math */
3342 switch (mnemonic
[1])
3344 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
3345 the fs segment override prefix not currently handled because no
3346 call path can make opcodes without operands get here */
3348 return 2 /* integer op */;
3350 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
3351 return 3; /* fldcw/fldenv */
3354 if (mnemonic
[2] != 'o' /* fnop */)
3355 return 3; /* non-waiting control op */
3358 if (mnemonic
[2] == 's')
3359 return 3; /* frstor/frstpm */
3362 if (mnemonic
[2] == 'a')
3363 return 3; /* fsave */
3364 if (mnemonic
[2] == 't')
3366 switch (mnemonic
[3])
3368 case 'c': /* fstcw */
3369 case 'd': /* fstdw */
3370 case 'e': /* fstenv */
3371 case 's': /* fsts[gw] */
3377 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
3378 return 0; /* fxsave/fxrstor are not really math ops */
3385 /* Build the VEX prefix. */
3388 build_vex_prefix (const insn_template
*t
)
3390 unsigned int register_specifier
;
3391 unsigned int implied_prefix
;
3392 unsigned int vector_length
;
3395 /* Check register specifier. */
3396 if (i
.vex
.register_specifier
)
3398 register_specifier
=
3399 ~register_number (i
.vex
.register_specifier
) & 0xf;
3400 gas_assert ((i
.vex
.register_specifier
->reg_flags
& RegVRex
) == 0);
3403 register_specifier
= 0xf;
3405 /* Use 2-byte VEX prefix by swapping destination and source operand
3406 if there are more than 1 register operand. */
3407 if (i
.reg_operands
> 1
3408 && i
.vec_encoding
!= vex_encoding_vex3
3409 && i
.dir_encoding
== dir_encoding_default
3410 && i
.operands
== i
.reg_operands
3411 && operand_type_equal (&i
.types
[0], &i
.types
[i
.operands
- 1])
3412 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3413 && (i
.tm
.opcode_modifier
.load
|| i
.tm
.opcode_modifier
.d
)
3416 unsigned int xchg
= i
.operands
- 1;
3417 union i386_op temp_op
;
3418 i386_operand_type temp_type
;
3420 temp_type
= i
.types
[xchg
];
3421 i
.types
[xchg
] = i
.types
[0];
3422 i
.types
[0] = temp_type
;
3423 temp_op
= i
.op
[xchg
];
3424 i
.op
[xchg
] = i
.op
[0];
3427 gas_assert (i
.rm
.mode
== 3);
3431 i
.rm
.regmem
= i
.rm
.reg
;
3434 if (i
.tm
.opcode_modifier
.d
)
3435 i
.tm
.base_opcode
^= (i
.tm
.base_opcode
& 0xee) != 0x6e
3436 ? Opcode_SIMD_FloatD
: Opcode_SIMD_IntD
;
3437 else /* Use the next insn. */
3441 /* Use 2-byte VEX prefix by swapping commutative source operands if there
3442 are no memory operands and at least 3 register ones. */
3443 if (i
.reg_operands
>= 3
3444 && i
.vec_encoding
!= vex_encoding_vex3
3445 && i
.reg_operands
== i
.operands
- i
.imm_operands
3446 && i
.tm
.opcode_modifier
.vex
3447 && i
.tm
.opcode_modifier
.commutative
3448 && (i
.tm
.opcode_modifier
.sse2avx
|| optimize
> 1)
3450 && i
.vex
.register_specifier
3451 && !(i
.vex
.register_specifier
->reg_flags
& RegRex
))
3453 unsigned int xchg
= i
.operands
- i
.reg_operands
;
3454 union i386_op temp_op
;
3455 i386_operand_type temp_type
;
3457 gas_assert (i
.tm
.opcode_modifier
.vexopcode
== VEX0F
);
3458 gas_assert (!i
.tm
.opcode_modifier
.sae
);
3459 gas_assert (operand_type_equal (&i
.types
[i
.operands
- 2],
3460 &i
.types
[i
.operands
- 3]));
3461 gas_assert (i
.rm
.mode
== 3);
3463 temp_type
= i
.types
[xchg
];
3464 i
.types
[xchg
] = i
.types
[xchg
+ 1];
3465 i
.types
[xchg
+ 1] = temp_type
;
3466 temp_op
= i
.op
[xchg
];
3467 i
.op
[xchg
] = i
.op
[xchg
+ 1];
3468 i
.op
[xchg
+ 1] = temp_op
;
3471 xchg
= i
.rm
.regmem
| 8;
3472 i
.rm
.regmem
= ~register_specifier
& 0xf;
3473 gas_assert (!(i
.rm
.regmem
& 8));
3474 i
.vex
.register_specifier
+= xchg
- i
.rm
.regmem
;
3475 register_specifier
= ~xchg
& 0xf;
3478 if (i
.tm
.opcode_modifier
.vex
== VEXScalar
)
3479 vector_length
= avxscalar
;
3480 else if (i
.tm
.opcode_modifier
.vex
== VEX256
)
3486 /* Determine vector length from the last multi-length vector
3489 for (op
= t
->operands
; op
--;)
3490 if (t
->operand_types
[op
].bitfield
.xmmword
3491 && t
->operand_types
[op
].bitfield
.ymmword
3492 && i
.types
[op
].bitfield
.ymmword
)
3499 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3504 case DATA_PREFIX_OPCODE
:
3507 case REPE_PREFIX_OPCODE
:
3510 case REPNE_PREFIX_OPCODE
:
3517 /* Check the REX.W bit and VEXW. */
3518 if (i
.tm
.opcode_modifier
.vexw
== VEXWIG
)
3519 w
= (vexwig
== vexw1
|| (i
.rex
& REX_W
)) ? 1 : 0;
3520 else if (i
.tm
.opcode_modifier
.vexw
)
3521 w
= i
.tm
.opcode_modifier
.vexw
== VEXW1
? 1 : 0;
3523 w
= (flag_code
== CODE_64BIT
? i
.rex
& REX_W
: vexwig
== vexw1
) ? 1 : 0;
3525 /* Use 2-byte VEX prefix if possible. */
3527 && i
.vec_encoding
!= vex_encoding_vex3
3528 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3529 && (i
.rex
& (REX_W
| REX_X
| REX_B
)) == 0)
3531 /* 2-byte VEX prefix. */
3535 i
.vex
.bytes
[0] = 0xc5;
3537 /* Check the REX.R bit. */
3538 r
= (i
.rex
& REX_R
) ? 0 : 1;
3539 i
.vex
.bytes
[1] = (r
<< 7
3540 | register_specifier
<< 3
3541 | vector_length
<< 2
3546 /* 3-byte VEX prefix. */
3551 switch (i
.tm
.opcode_modifier
.vexopcode
)
3555 i
.vex
.bytes
[0] = 0xc4;
3559 i
.vex
.bytes
[0] = 0xc4;
3563 i
.vex
.bytes
[0] = 0xc4;
3567 i
.vex
.bytes
[0] = 0x8f;
3571 i
.vex
.bytes
[0] = 0x8f;
3575 i
.vex
.bytes
[0] = 0x8f;
3581 /* The high 3 bits of the second VEX byte are 1's compliment
3582 of RXB bits from REX. */
3583 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3585 i
.vex
.bytes
[2] = (w
<< 7
3586 | register_specifier
<< 3
3587 | vector_length
<< 2
3592 static INLINE bfd_boolean
3593 is_evex_encoding (const insn_template
*t
)
3595 return t
->opcode_modifier
.evex
|| t
->opcode_modifier
.disp8memshift
3596 || t
->opcode_modifier
.broadcast
|| t
->opcode_modifier
.masking
3597 || t
->opcode_modifier
.sae
;
3600 static INLINE bfd_boolean
3601 is_any_vex_encoding (const insn_template
*t
)
3603 return t
->opcode_modifier
.vex
|| t
->opcode_modifier
.vexopcode
3604 || is_evex_encoding (t
);
3607 /* Build the EVEX prefix. */
3610 build_evex_prefix (void)
3612 unsigned int register_specifier
;
3613 unsigned int implied_prefix
;
3615 rex_byte vrex_used
= 0;
3617 /* Check register specifier. */
3618 if (i
.vex
.register_specifier
)
3620 gas_assert ((i
.vrex
& REX_X
) == 0);
3622 register_specifier
= i
.vex
.register_specifier
->reg_num
;
3623 if ((i
.vex
.register_specifier
->reg_flags
& RegRex
))
3624 register_specifier
+= 8;
3625 /* The upper 16 registers are encoded in the fourth byte of the
3627 if (!(i
.vex
.register_specifier
->reg_flags
& RegVRex
))
3628 i
.vex
.bytes
[3] = 0x8;
3629 register_specifier
= ~register_specifier
& 0xf;
3633 register_specifier
= 0xf;
3635 /* Encode upper 16 vector index register in the fourth byte of
3637 if (!(i
.vrex
& REX_X
))
3638 i
.vex
.bytes
[3] = 0x8;
3643 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3648 case DATA_PREFIX_OPCODE
:
3651 case REPE_PREFIX_OPCODE
:
3654 case REPNE_PREFIX_OPCODE
:
3661 /* 4 byte EVEX prefix. */
3663 i
.vex
.bytes
[0] = 0x62;
3666 switch (i
.tm
.opcode_modifier
.vexopcode
)
3682 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3684 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3686 /* The fifth bit of the second EVEX byte is 1's compliment of the
3687 REX_R bit in VREX. */
3688 if (!(i
.vrex
& REX_R
))
3689 i
.vex
.bytes
[1] |= 0x10;
3693 if ((i
.reg_operands
+ i
.imm_operands
) == i
.operands
)
3695 /* When all operands are registers, the REX_X bit in REX is not
3696 used. We reuse it to encode the upper 16 registers, which is
3697 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3698 as 1's compliment. */
3699 if ((i
.vrex
& REX_B
))
3702 i
.vex
.bytes
[1] &= ~0x40;
3706 /* EVEX instructions shouldn't need the REX prefix. */
3707 i
.vrex
&= ~vrex_used
;
3708 gas_assert (i
.vrex
== 0);
3710 /* Check the REX.W bit and VEXW. */
3711 if (i
.tm
.opcode_modifier
.vexw
== VEXWIG
)
3712 w
= (evexwig
== evexw1
|| (i
.rex
& REX_W
)) ? 1 : 0;
3713 else if (i
.tm
.opcode_modifier
.vexw
)
3714 w
= i
.tm
.opcode_modifier
.vexw
== VEXW1
? 1 : 0;
3716 w
= (flag_code
== CODE_64BIT
? i
.rex
& REX_W
: evexwig
== evexw1
) ? 1 : 0;
3718 /* Encode the U bit. */
3719 implied_prefix
|= 0x4;
3721 /* The third byte of the EVEX prefix. */
3722 i
.vex
.bytes
[2] = (w
<< 7 | register_specifier
<< 3 | implied_prefix
);
3724 /* The fourth byte of the EVEX prefix. */
3725 /* The zeroing-masking bit. */
3726 if (i
.mask
&& i
.mask
->zeroing
)
3727 i
.vex
.bytes
[3] |= 0x80;
3729 /* Don't always set the broadcast bit if there is no RC. */
3732 /* Encode the vector length. */
3733 unsigned int vec_length
;
3735 if (!i
.tm
.opcode_modifier
.evex
3736 || i
.tm
.opcode_modifier
.evex
== EVEXDYN
)
3740 /* Determine vector length from the last multi-length vector
3743 for (op
= i
.operands
; op
--;)
3744 if (i
.tm
.operand_types
[op
].bitfield
.xmmword
3745 + i
.tm
.operand_types
[op
].bitfield
.ymmword
3746 + i
.tm
.operand_types
[op
].bitfield
.zmmword
> 1)
3748 if (i
.types
[op
].bitfield
.zmmword
)
3750 i
.tm
.opcode_modifier
.evex
= EVEX512
;
3753 else if (i
.types
[op
].bitfield
.ymmword
)
3755 i
.tm
.opcode_modifier
.evex
= EVEX256
;
3758 else if (i
.types
[op
].bitfield
.xmmword
)
3760 i
.tm
.opcode_modifier
.evex
= EVEX128
;
3763 else if (i
.broadcast
&& (int) op
== i
.broadcast
->operand
)
3765 switch (i
.broadcast
->bytes
)
3768 i
.tm
.opcode_modifier
.evex
= EVEX512
;
3771 i
.tm
.opcode_modifier
.evex
= EVEX256
;
3774 i
.tm
.opcode_modifier
.evex
= EVEX128
;
3783 if (op
>= MAX_OPERANDS
)
3787 switch (i
.tm
.opcode_modifier
.evex
)
3789 case EVEXLIG
: /* LL' is ignored */
3790 vec_length
= evexlig
<< 5;
3793 vec_length
= 0 << 5;
3796 vec_length
= 1 << 5;
3799 vec_length
= 2 << 5;
3805 i
.vex
.bytes
[3] |= vec_length
;
3806 /* Encode the broadcast bit. */
3808 i
.vex
.bytes
[3] |= 0x10;
3812 if (i
.rounding
->type
!= saeonly
)
3813 i
.vex
.bytes
[3] |= 0x10 | (i
.rounding
->type
<< 5);
3815 i
.vex
.bytes
[3] |= 0x10 | (evexrcig
<< 5);
3818 if (i
.mask
&& i
.mask
->mask
)
3819 i
.vex
.bytes
[3] |= i
.mask
->mask
->reg_num
;
3823 process_immext (void)
3827 if ((i
.tm
.cpu_flags
.bitfield
.cpusse3
|| i
.tm
.cpu_flags
.bitfield
.cpusvme
)
3830 /* MONITOR/MWAIT as well as SVME instructions have fixed operands
3831 with an opcode suffix which is coded in the same place as an
3832 8-bit immediate field would be.
3833 Here we check those operands and remove them afterwards. */
3836 for (x
= 0; x
< i
.operands
; x
++)
3837 if (register_number (i
.op
[x
].regs
) != x
)
3838 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3839 register_prefix
, i
.op
[x
].regs
->reg_name
, x
+ 1,
3845 if (i
.tm
.cpu_flags
.bitfield
.cpumwaitx
&& i
.operands
> 0)
3847 /* MONITORX/MWAITX instructions have fixed operands with an opcode
3848 suffix which is coded in the same place as an 8-bit immediate
3850 Here we check those operands and remove them afterwards. */
3853 if (i
.operands
!= 3)
3856 for (x
= 0; x
< 2; x
++)
3857 if (register_number (i
.op
[x
].regs
) != x
)
3858 goto bad_register_operand
;
3860 /* Check for third operand for mwaitx/monitorx insn. */
3861 if (register_number (i
.op
[x
].regs
)
3862 != (x
+ (i
.tm
.extension_opcode
== 0xfb)))
3864 bad_register_operand
:
3865 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3866 register_prefix
, i
.op
[x
].regs
->reg_name
, x
+1,
3873 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
3874 which is coded in the same place as an 8-bit immediate field
3875 would be. Here we fake an 8-bit immediate operand from the
3876 opcode suffix stored in tm.extension_opcode.
3878 AVX instructions also use this encoding, for some of
3879 3 argument instructions. */
3881 gas_assert (i
.imm_operands
<= 1
3883 || (is_any_vex_encoding (&i
.tm
)
3884 && i
.operands
<= 4)));
3886 exp
= &im_expressions
[i
.imm_operands
++];
3887 i
.op
[i
.operands
].imms
= exp
;
3888 i
.types
[i
.operands
] = imm8
;
3890 exp
->X_op
= O_constant
;
3891 exp
->X_add_number
= i
.tm
.extension_opcode
;
3892 i
.tm
.extension_opcode
= None
;
3899 switch (i
.tm
.opcode_modifier
.hleprefixok
)
3904 as_bad (_("invalid instruction `%s' after `%s'"),
3905 i
.tm
.name
, i
.hle_prefix
);
3908 if (i
.prefix
[LOCK_PREFIX
])
3910 as_bad (_("missing `lock' with `%s'"), i
.hle_prefix
);
3914 case HLEPrefixRelease
:
3915 if (i
.prefix
[HLE_PREFIX
] != XRELEASE_PREFIX_OPCODE
)
3917 as_bad (_("instruction `%s' after `xacquire' not allowed"),
3921 if (i
.mem_operands
== 0 || !(i
.flags
[i
.operands
- 1] & Operand_Mem
))
3923 as_bad (_("memory destination needed for instruction `%s'"
3924 " after `xrelease'"), i
.tm
.name
);
3931 /* Try the shortest encoding by shortening operand size. */
3934 optimize_encoding (void)
3938 if (optimize_for_space
3939 && i
.reg_operands
== 1
3940 && i
.imm_operands
== 1
3941 && !i
.types
[1].bitfield
.byte
3942 && i
.op
[0].imms
->X_op
== O_constant
3943 && fits_in_imm7 (i
.op
[0].imms
->X_add_number
)
3944 && ((i
.tm
.base_opcode
== 0xa8
3945 && i
.tm
.extension_opcode
== None
)
3946 || (i
.tm
.base_opcode
== 0xf6
3947 && i
.tm
.extension_opcode
== 0x0)))
3950 test $imm7, %r64/%r32/%r16 -> test $imm7, %r8
3952 unsigned int base_regnum
= i
.op
[1].regs
->reg_num
;
3953 if (flag_code
== CODE_64BIT
|| base_regnum
< 4)
3955 i
.types
[1].bitfield
.byte
= 1;
3956 /* Ignore the suffix. */
3958 if (base_regnum
>= 4
3959 && !(i
.op
[1].regs
->reg_flags
& RegRex
))
3961 /* Handle SP, BP, SI and DI registers. */
3962 if (i
.types
[1].bitfield
.word
)
3964 else if (i
.types
[1].bitfield
.dword
)
3972 else if (flag_code
== CODE_64BIT
3973 && ((i
.types
[1].bitfield
.qword
3974 && i
.reg_operands
== 1
3975 && i
.imm_operands
== 1
3976 && i
.op
[0].imms
->X_op
== O_constant
3977 && ((i
.tm
.base_opcode
== 0xb8
3978 && i
.tm
.extension_opcode
== None
3979 && fits_in_unsigned_long (i
.op
[0].imms
->X_add_number
))
3980 || (fits_in_imm31 (i
.op
[0].imms
->X_add_number
)
3981 && (((i
.tm
.base_opcode
== 0x24
3982 || i
.tm
.base_opcode
== 0xa8)
3983 && i
.tm
.extension_opcode
== None
)
3984 || (i
.tm
.base_opcode
== 0x80
3985 && i
.tm
.extension_opcode
== 0x4)
3986 || ((i
.tm
.base_opcode
== 0xf6
3987 || (i
.tm
.base_opcode
| 1) == 0xc7)
3988 && i
.tm
.extension_opcode
== 0x0)))
3989 || (fits_in_imm7 (i
.op
[0].imms
->X_add_number
)
3990 && i
.tm
.base_opcode
== 0x83
3991 && i
.tm
.extension_opcode
== 0x4)))
3992 || (i
.types
[0].bitfield
.qword
3993 && ((i
.reg_operands
== 2
3994 && i
.op
[0].regs
== i
.op
[1].regs
3995 && ((i
.tm
.base_opcode
== 0x30
3996 || i
.tm
.base_opcode
== 0x28)
3997 && i
.tm
.extension_opcode
== None
))
3998 || (i
.reg_operands
== 1
4000 && i
.tm
.base_opcode
== 0x30
4001 && i
.tm
.extension_opcode
== None
)))))
4004 andq $imm31, %r64 -> andl $imm31, %r32
4005 andq $imm7, %r64 -> andl $imm7, %r32
4006 testq $imm31, %r64 -> testl $imm31, %r32
4007 xorq %r64, %r64 -> xorl %r32, %r32
4008 subq %r64, %r64 -> subl %r32, %r32
4009 movq $imm31, %r64 -> movl $imm31, %r32
4010 movq $imm32, %r64 -> movl $imm32, %r32
4012 i
.tm
.opcode_modifier
.norex64
= 1;
4013 if (i
.tm
.base_opcode
== 0xb8 || (i
.tm
.base_opcode
| 1) == 0xc7)
4016 movq $imm31, %r64 -> movl $imm31, %r32
4017 movq $imm32, %r64 -> movl $imm32, %r32
4019 i
.tm
.operand_types
[0].bitfield
.imm32
= 1;
4020 i
.tm
.operand_types
[0].bitfield
.imm32s
= 0;
4021 i
.tm
.operand_types
[0].bitfield
.imm64
= 0;
4022 i
.types
[0].bitfield
.imm32
= 1;
4023 i
.types
[0].bitfield
.imm32s
= 0;
4024 i
.types
[0].bitfield
.imm64
= 0;
4025 i
.types
[1].bitfield
.dword
= 1;
4026 i
.types
[1].bitfield
.qword
= 0;
4027 if ((i
.tm
.base_opcode
| 1) == 0xc7)
4030 movq $imm31, %r64 -> movl $imm31, %r32
4032 i
.tm
.base_opcode
= 0xb8;
4033 i
.tm
.extension_opcode
= None
;
4034 i
.tm
.opcode_modifier
.w
= 0;
4035 i
.tm
.opcode_modifier
.shortform
= 1;
4036 i
.tm
.opcode_modifier
.modrm
= 0;
4040 else if (optimize
> 1
4041 && !optimize_for_space
4042 && i
.reg_operands
== 2
4043 && i
.op
[0].regs
== i
.op
[1].regs
4044 && ((i
.tm
.base_opcode
& ~(Opcode_D
| 1)) == 0x8
4045 || (i
.tm
.base_opcode
& ~(Opcode_D
| 1)) == 0x20)
4046 && (flag_code
!= CODE_64BIT
|| !i
.types
[0].bitfield
.dword
))
4049 andb %rN, %rN -> testb %rN, %rN
4050 andw %rN, %rN -> testw %rN, %rN
4051 andq %rN, %rN -> testq %rN, %rN
4052 orb %rN, %rN -> testb %rN, %rN
4053 orw %rN, %rN -> testw %rN, %rN
4054 orq %rN, %rN -> testq %rN, %rN
4056 and outside of 64-bit mode
4058 andl %rN, %rN -> testl %rN, %rN
4059 orl %rN, %rN -> testl %rN, %rN
4061 i
.tm
.base_opcode
= 0x84 | (i
.tm
.base_opcode
& 1);
4063 else if (i
.reg_operands
== 3
4064 && i
.op
[0].regs
== i
.op
[1].regs
4065 && !i
.types
[2].bitfield
.xmmword
4066 && (i
.tm
.opcode_modifier
.vex
4067 || ((!i
.mask
|| i
.mask
->zeroing
)
4069 && is_evex_encoding (&i
.tm
)
4070 && (i
.vec_encoding
!= vex_encoding_evex
4071 || cpu_arch_isa_flags
.bitfield
.cpuavx512vl
4072 || i
.tm
.cpu_flags
.bitfield
.cpuavx512vl
4073 || (i
.tm
.operand_types
[2].bitfield
.zmmword
4074 && i
.types
[2].bitfield
.ymmword
))))
4075 && ((i
.tm
.base_opcode
== 0x55
4076 || i
.tm
.base_opcode
== 0x6655
4077 || i
.tm
.base_opcode
== 0x66df
4078 || i
.tm
.base_opcode
== 0x57
4079 || i
.tm
.base_opcode
== 0x6657
4080 || i
.tm
.base_opcode
== 0x66ef
4081 || i
.tm
.base_opcode
== 0x66f8
4082 || i
.tm
.base_opcode
== 0x66f9
4083 || i
.tm
.base_opcode
== 0x66fa
4084 || i
.tm
.base_opcode
== 0x66fb
4085 || i
.tm
.base_opcode
== 0x42
4086 || i
.tm
.base_opcode
== 0x6642
4087 || i
.tm
.base_opcode
== 0x47
4088 || i
.tm
.base_opcode
== 0x6647)
4089 && i
.tm
.extension_opcode
== None
))
4092 VOP, one of vandnps, vandnpd, vxorps, vxorpd, vpsubb, vpsubd,
4094 EVEX VOP %zmmM, %zmmM, %zmmN
4095 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
4096 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4097 EVEX VOP %ymmM, %ymmM, %ymmN
4098 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
4099 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4100 VEX VOP %ymmM, %ymmM, %ymmN
4101 -> VEX VOP %xmmM, %xmmM, %xmmN
4102 VOP, one of vpandn and vpxor:
4103 VEX VOP %ymmM, %ymmM, %ymmN
4104 -> VEX VOP %xmmM, %xmmM, %xmmN
4105 VOP, one of vpandnd and vpandnq:
4106 EVEX VOP %zmmM, %zmmM, %zmmN
4107 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
4108 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4109 EVEX VOP %ymmM, %ymmM, %ymmN
4110 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
4111 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4112 VOP, one of vpxord and vpxorq:
4113 EVEX VOP %zmmM, %zmmM, %zmmN
4114 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
4115 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4116 EVEX VOP %ymmM, %ymmM, %ymmN
4117 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
4118 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4119 VOP, one of kxord and kxorq:
4120 VEX VOP %kM, %kM, %kN
4121 -> VEX kxorw %kM, %kM, %kN
4122 VOP, one of kandnd and kandnq:
4123 VEX VOP %kM, %kM, %kN
4124 -> VEX kandnw %kM, %kM, %kN
4126 if (is_evex_encoding (&i
.tm
))
4128 if (i
.vec_encoding
!= vex_encoding_evex
)
4130 i
.tm
.opcode_modifier
.vex
= VEX128
;
4131 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4132 i
.tm
.opcode_modifier
.evex
= 0;
4134 else if (optimize
> 1)
4135 i
.tm
.opcode_modifier
.evex
= EVEX128
;
4139 else if (i
.tm
.operand_types
[0].bitfield
.regmask
)
4141 i
.tm
.base_opcode
&= 0xff;
4142 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4145 i
.tm
.opcode_modifier
.vex
= VEX128
;
4147 if (i
.tm
.opcode_modifier
.vex
)
4148 for (j
= 0; j
< 3; j
++)
4150 i
.types
[j
].bitfield
.xmmword
= 1;
4151 i
.types
[j
].bitfield
.ymmword
= 0;
4154 else if (i
.vec_encoding
!= vex_encoding_evex
4155 && !i
.types
[0].bitfield
.zmmword
4156 && !i
.types
[1].bitfield
.zmmword
4159 && is_evex_encoding (&i
.tm
)
4160 && ((i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0x666f
4161 || (i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0xf36f
4162 || (i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0xf26f
4163 || (i
.tm
.base_opcode
& ~4) == 0x66db
4164 || (i
.tm
.base_opcode
& ~4) == 0x66eb)
4165 && i
.tm
.extension_opcode
== None
)
4168 VOP, one of vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16,
4169 vmovdqu32 and vmovdqu64:
4170 EVEX VOP %xmmM, %xmmN
4171 -> VEX vmovdqa|vmovdqu %xmmM, %xmmN (M and N < 16)
4172 EVEX VOP %ymmM, %ymmN
4173 -> VEX vmovdqa|vmovdqu %ymmM, %ymmN (M and N < 16)
4175 -> VEX vmovdqa|vmovdqu %xmmM, mem (M < 16)
4177 -> VEX vmovdqa|vmovdqu %ymmM, mem (M < 16)
4179 -> VEX mvmovdqa|vmovdquem, %xmmN (N < 16)
4181 -> VEX vmovdqa|vmovdqu mem, %ymmN (N < 16)
4182 VOP, one of vpand, vpandn, vpor, vpxor:
4183 EVEX VOP{d,q} %xmmL, %xmmM, %xmmN
4184 -> VEX VOP %xmmL, %xmmM, %xmmN (L, M, and N < 16)
4185 EVEX VOP{d,q} %ymmL, %ymmM, %ymmN
4186 -> VEX VOP %ymmL, %ymmM, %ymmN (L, M, and N < 16)
4187 EVEX VOP{d,q} mem, %xmmM, %xmmN
4188 -> VEX VOP mem, %xmmM, %xmmN (M and N < 16)
4189 EVEX VOP{d,q} mem, %ymmM, %ymmN
4190 -> VEX VOP mem, %ymmM, %ymmN (M and N < 16)
4192 for (j
= 0; j
< i
.operands
; j
++)
4193 if (operand_type_check (i
.types
[j
], disp
)
4194 && i
.op
[j
].disps
->X_op
== O_constant
)
4196 /* Since the VEX prefix has 2 or 3 bytes, the EVEX prefix
4197 has 4 bytes, EVEX Disp8 has 1 byte and VEX Disp32 has 4
4198 bytes, we choose EVEX Disp8 over VEX Disp32. */
4199 int evex_disp8
, vex_disp8
;
4200 unsigned int memshift
= i
.memshift
;
4201 offsetT n
= i
.op
[j
].disps
->X_add_number
;
4203 evex_disp8
= fits_in_disp8 (n
);
4205 vex_disp8
= fits_in_disp8 (n
);
4206 if (evex_disp8
!= vex_disp8
)
4208 i
.memshift
= memshift
;
4212 i
.types
[j
].bitfield
.disp8
= vex_disp8
;
4215 if ((i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0xf26f)
4216 i
.tm
.base_opcode
^= 0xf36f ^ 0xf26f;
4217 i
.tm
.opcode_modifier
.vex
4218 = i
.types
[0].bitfield
.ymmword
? VEX256
: VEX128
;
4219 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4220 /* VPAND, VPOR, and VPXOR are commutative. */
4221 if (i
.reg_operands
== 3 && i
.tm
.base_opcode
!= 0x66df)
4222 i
.tm
.opcode_modifier
.commutative
= 1;
4223 i
.tm
.opcode_modifier
.evex
= 0;
4224 i
.tm
.opcode_modifier
.masking
= 0;
4225 i
.tm
.opcode_modifier
.broadcast
= 0;
4226 i
.tm
.opcode_modifier
.disp8memshift
= 0;
4229 i
.types
[j
].bitfield
.disp8
4230 = fits_in_disp8 (i
.op
[j
].disps
->X_add_number
);
4234 /* This is the guts of the machine-dependent assembler. LINE points to a
4235 machine dependent instruction. This function is supposed to emit
4236 the frags/bytes it assembles to. */
4239 md_assemble (char *line
)
4242 char mnemonic
[MAX_MNEM_SIZE
], mnem_suffix
;
4243 const insn_template
*t
;
4245 /* Initialize globals. */
4246 memset (&i
, '\0', sizeof (i
));
4247 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4248 i
.reloc
[j
] = NO_RELOC
;
4249 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
4250 memset (im_expressions
, '\0', sizeof (im_expressions
));
4251 save_stack_p
= save_stack
;
4253 /* First parse an instruction mnemonic & call i386_operand for the operands.
4254 We assume that the scrubber has arranged it so that line[0] is the valid
4255 start of a (possibly prefixed) mnemonic. */
4257 line
= parse_insn (line
, mnemonic
);
4260 mnem_suffix
= i
.suffix
;
4262 line
= parse_operands (line
, mnemonic
);
4264 xfree (i
.memop1_string
);
4265 i
.memop1_string
= NULL
;
4269 /* Now we've parsed the mnemonic into a set of templates, and have the
4270 operands at hand. */
4272 /* All intel opcodes have reversed operands except for "bound" and
4273 "enter". We also don't reverse intersegment "jmp" and "call"
4274 instructions with 2 immediate operands so that the immediate segment
4275 precedes the offset, as it does when in AT&T mode. */
4278 && (strcmp (mnemonic
, "bound") != 0)
4279 && (strcmp (mnemonic
, "invlpga") != 0)
4280 && !(operand_type_check (i
.types
[0], imm
)
4281 && operand_type_check (i
.types
[1], imm
)))
4284 /* The order of the immediates should be reversed
4285 for 2 immediates extrq and insertq instructions */
4286 if (i
.imm_operands
== 2
4287 && (strcmp (mnemonic
, "extrq") == 0
4288 || strcmp (mnemonic
, "insertq") == 0))
4289 swap_2_operands (0, 1);
4294 /* Don't optimize displacement for movabs since it only takes 64bit
4297 && i
.disp_encoding
!= disp_encoding_32bit
4298 && (flag_code
!= CODE_64BIT
4299 || strcmp (mnemonic
, "movabs") != 0))
4302 /* Next, we find a template that matches the given insn,
4303 making sure the overlap of the given operands types is consistent
4304 with the template operand types. */
4306 if (!(t
= match_template (mnem_suffix
)))
4309 if (sse_check
!= check_none
4310 && !i
.tm
.opcode_modifier
.noavx
4311 && !i
.tm
.cpu_flags
.bitfield
.cpuavx
4312 && (i
.tm
.cpu_flags
.bitfield
.cpusse
4313 || i
.tm
.cpu_flags
.bitfield
.cpusse2
4314 || i
.tm
.cpu_flags
.bitfield
.cpusse3
4315 || i
.tm
.cpu_flags
.bitfield
.cpussse3
4316 || i
.tm
.cpu_flags
.bitfield
.cpusse4_1
4317 || i
.tm
.cpu_flags
.bitfield
.cpusse4_2
4318 || i
.tm
.cpu_flags
.bitfield
.cpupclmul
4319 || i
.tm
.cpu_flags
.bitfield
.cpuaes
4320 || i
.tm
.cpu_flags
.bitfield
.cpugfni
))
4322 (sse_check
== check_warning
4324 : as_bad
) (_("SSE instruction `%s' is used"), i
.tm
.name
);
4327 /* Zap movzx and movsx suffix. The suffix has been set from
4328 "word ptr" or "byte ptr" on the source operand in Intel syntax
4329 or extracted from mnemonic in AT&T syntax. But we'll use
4330 the destination register to choose the suffix for encoding. */
4331 if ((i
.tm
.base_opcode
& ~9) == 0x0fb6)
4333 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
4334 there is no suffix, the default will be byte extension. */
4335 if (i
.reg_operands
!= 2
4338 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
4343 if (i
.tm
.opcode_modifier
.fwait
)
4344 if (!add_prefix (FWAIT_OPCODE
))
4347 /* Check if REP prefix is OK. */
4348 if (i
.rep_prefix
&& !i
.tm
.opcode_modifier
.repprefixok
)
4350 as_bad (_("invalid instruction `%s' after `%s'"),
4351 i
.tm
.name
, i
.rep_prefix
);
4355 /* Check for lock without a lockable instruction. Destination operand
4356 must be memory unless it is xchg (0x86). */
4357 if (i
.prefix
[LOCK_PREFIX
]
4358 && (!i
.tm
.opcode_modifier
.islockable
4359 || i
.mem_operands
== 0
4360 || (i
.tm
.base_opcode
!= 0x86
4361 && !(i
.flags
[i
.operands
- 1] & Operand_Mem
))))
4363 as_bad (_("expecting lockable instruction after `lock'"));
4367 /* Check for data size prefix on VEX/XOP/EVEX encoded insns. */
4368 if (i
.prefix
[DATA_PREFIX
] && is_any_vex_encoding (&i
.tm
))
4370 as_bad (_("data size prefix invalid with `%s'"), i
.tm
.name
);
4374 /* Check if HLE prefix is OK. */
4375 if (i
.hle_prefix
&& !check_hle ())
4378 /* Check BND prefix. */
4379 if (i
.bnd_prefix
&& !i
.tm
.opcode_modifier
.bndprefixok
)
4380 as_bad (_("expecting valid branch instruction after `bnd'"));
4382 /* Check NOTRACK prefix. */
4383 if (i
.notrack_prefix
&& !i
.tm
.opcode_modifier
.notrackprefixok
)
4384 as_bad (_("expecting indirect branch instruction after `notrack'"));
4386 if (i
.tm
.cpu_flags
.bitfield
.cpumpx
)
4388 if (flag_code
== CODE_64BIT
&& i
.prefix
[ADDR_PREFIX
])
4389 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
4390 else if (flag_code
!= CODE_16BIT
4391 ? i
.prefix
[ADDR_PREFIX
]
4392 : i
.mem_operands
&& !i
.prefix
[ADDR_PREFIX
])
4393 as_bad (_("16-bit address isn't allowed in MPX instructions"));
4396 /* Insert BND prefix. */
4397 if (add_bnd_prefix
&& i
.tm
.opcode_modifier
.bndprefixok
)
4399 if (!i
.prefix
[BND_PREFIX
])
4400 add_prefix (BND_PREFIX_OPCODE
);
4401 else if (i
.prefix
[BND_PREFIX
] != BND_PREFIX_OPCODE
)
4403 as_warn (_("replacing `rep'/`repe' prefix by `bnd'"));
4404 i
.prefix
[BND_PREFIX
] = BND_PREFIX_OPCODE
;
4408 /* Check string instruction segment overrides. */
4409 if (i
.tm
.opcode_modifier
.isstring
&& i
.mem_operands
!= 0)
4411 if (!check_string ())
4413 i
.disp_operands
= 0;
4416 if (optimize
&& !i
.no_optimize
&& i
.tm
.opcode_modifier
.optimize
)
4417 optimize_encoding ();
4419 if (!process_suffix ())
4422 /* Update operand types. */
4423 for (j
= 0; j
< i
.operands
; j
++)
4424 i
.types
[j
] = operand_type_and (i
.types
[j
], i
.tm
.operand_types
[j
]);
4426 /* Make still unresolved immediate matches conform to size of immediate
4427 given in i.suffix. */
4428 if (!finalize_imm ())
4431 if (i
.types
[0].bitfield
.imm1
)
4432 i
.imm_operands
= 0; /* kludge for shift insns. */
4434 /* We only need to check those implicit registers for instructions
4435 with 3 operands or less. */
4436 if (i
.operands
<= 3)
4437 for (j
= 0; j
< i
.operands
; j
++)
4438 if (i
.types
[j
].bitfield
.inoutportreg
4439 || i
.types
[j
].bitfield
.shiftcount
4440 || (i
.types
[j
].bitfield
.acc
&& !i
.types
[j
].bitfield
.xmmword
))
4443 /* ImmExt should be processed after SSE2AVX. */
4444 if (!i
.tm
.opcode_modifier
.sse2avx
4445 && i
.tm
.opcode_modifier
.immext
)
4448 /* For insns with operands there are more diddles to do to the opcode. */
4451 if (!process_operands ())
4454 else if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
4456 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
4457 as_warn (_("translating to `%sp'"), i
.tm
.name
);
4460 if (is_any_vex_encoding (&i
.tm
))
4462 if (!cpu_arch_flags
.bitfield
.cpui286
)
4464 as_bad (_("instruction `%s' isn't supported outside of protected mode."),
4469 if (i
.tm
.opcode_modifier
.vex
)
4470 build_vex_prefix (t
);
4472 build_evex_prefix ();
4475 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
4476 instructions may define INT_OPCODE as well, so avoid this corner
4477 case for those instructions that use MODRM. */
4478 if (i
.tm
.base_opcode
== INT_OPCODE
4479 && !i
.tm
.opcode_modifier
.modrm
4480 && i
.op
[0].imms
->X_add_number
== 3)
4482 i
.tm
.base_opcode
= INT3_OPCODE
;
4486 if ((i
.tm
.opcode_modifier
.jump
4487 || i
.tm
.opcode_modifier
.jumpbyte
4488 || i
.tm
.opcode_modifier
.jumpdword
)
4489 && i
.op
[0].disps
->X_op
== O_constant
)
4491 /* Convert "jmp constant" (and "call constant") to a jump (call) to
4492 the absolute address given by the constant. Since ix86 jumps and
4493 calls are pc relative, we need to generate a reloc. */
4494 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
4495 i
.op
[0].disps
->X_op
= O_symbol
;
4498 if (i
.tm
.opcode_modifier
.rex64
)
4501 /* For 8 bit registers we need an empty rex prefix. Also if the
4502 instruction already has a prefix, we need to convert old
4503 registers to new ones. */
4505 if ((i
.types
[0].bitfield
.reg
&& i
.types
[0].bitfield
.byte
4506 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
4507 || (i
.types
[1].bitfield
.reg
&& i
.types
[1].bitfield
.byte
4508 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
4509 || (((i
.types
[0].bitfield
.reg
&& i
.types
[0].bitfield
.byte
)
4510 || (i
.types
[1].bitfield
.reg
&& i
.types
[1].bitfield
.byte
))
4515 i
.rex
|= REX_OPCODE
;
4516 for (x
= 0; x
< 2; x
++)
4518 /* Look for 8 bit operand that uses old registers. */
4519 if (i
.types
[x
].bitfield
.reg
&& i
.types
[x
].bitfield
.byte
4520 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
4522 /* In case it is "hi" register, give up. */
4523 if (i
.op
[x
].regs
->reg_num
> 3)
4524 as_bad (_("can't encode register '%s%s' in an "
4525 "instruction requiring REX prefix."),
4526 register_prefix
, i
.op
[x
].regs
->reg_name
);
4528 /* Otherwise it is equivalent to the extended register.
4529 Since the encoding doesn't change this is merely
4530 cosmetic cleanup for debug output. */
4532 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
4537 if (i
.rex
== 0 && i
.rex_encoding
)
4539 /* Check if we can add a REX_OPCODE byte. Look for 8 bit operand
4540 that uses legacy register. If it is "hi" register, don't add
4541 the REX_OPCODE byte. */
4543 for (x
= 0; x
< 2; x
++)
4544 if (i
.types
[x
].bitfield
.reg
4545 && i
.types
[x
].bitfield
.byte
4546 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0
4547 && i
.op
[x
].regs
->reg_num
> 3)
4549 i
.rex_encoding
= FALSE
;
4558 add_prefix (REX_OPCODE
| i
.rex
);
4560 /* We are ready to output the insn. */
4565 parse_insn (char *line
, char *mnemonic
)
4568 char *token_start
= l
;
4571 const insn_template
*t
;
4577 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
4582 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
4584 as_bad (_("no such instruction: `%s'"), token_start
);
4589 if (!is_space_char (*l
)
4590 && *l
!= END_OF_INSN
4592 || (*l
!= PREFIX_SEPARATOR
4595 as_bad (_("invalid character %s in mnemonic"),
4596 output_invalid (*l
));
4599 if (token_start
== l
)
4601 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
4602 as_bad (_("expecting prefix; got nothing"));
4604 as_bad (_("expecting mnemonic; got nothing"));
4608 /* Look up instruction (or prefix) via hash table. */
4609 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
4611 if (*l
!= END_OF_INSN
4612 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
4613 && current_templates
4614 && current_templates
->start
->opcode_modifier
.isprefix
)
4616 if (!cpu_flags_check_cpu64 (current_templates
->start
->cpu_flags
))
4618 as_bad ((flag_code
!= CODE_64BIT
4619 ? _("`%s' is only supported in 64-bit mode")
4620 : _("`%s' is not supported in 64-bit mode")),
4621 current_templates
->start
->name
);
4624 /* If we are in 16-bit mode, do not allow addr16 or data16.
4625 Similarly, in 32-bit mode, do not allow addr32 or data32. */
4626 if ((current_templates
->start
->opcode_modifier
.size
== SIZE16
4627 || current_templates
->start
->opcode_modifier
.size
== SIZE32
)
4628 && flag_code
!= CODE_64BIT
4629 && ((current_templates
->start
->opcode_modifier
.size
== SIZE32
)
4630 ^ (flag_code
== CODE_16BIT
)))
4632 as_bad (_("redundant %s prefix"),
4633 current_templates
->start
->name
);
4636 if (current_templates
->start
->opcode_length
== 0)
4638 /* Handle pseudo prefixes. */
4639 switch (current_templates
->start
->base_opcode
)
4643 i
.disp_encoding
= disp_encoding_8bit
;
4647 i
.disp_encoding
= disp_encoding_32bit
;
4651 i
.dir_encoding
= dir_encoding_load
;
4655 i
.dir_encoding
= dir_encoding_store
;
4659 i
.vec_encoding
= vex_encoding_vex2
;
4663 i
.vec_encoding
= vex_encoding_vex3
;
4667 i
.vec_encoding
= vex_encoding_evex
;
4671 i
.rex_encoding
= TRUE
;
4675 i
.no_optimize
= TRUE
;
4683 /* Add prefix, checking for repeated prefixes. */
4684 switch (add_prefix (current_templates
->start
->base_opcode
))
4689 if (current_templates
->start
->cpu_flags
.bitfield
.cpuibt
)
4690 i
.notrack_prefix
= current_templates
->start
->name
;
4693 if (current_templates
->start
->cpu_flags
.bitfield
.cpuhle
)
4694 i
.hle_prefix
= current_templates
->start
->name
;
4695 else if (current_templates
->start
->cpu_flags
.bitfield
.cpumpx
)
4696 i
.bnd_prefix
= current_templates
->start
->name
;
4698 i
.rep_prefix
= current_templates
->start
->name
;
4704 /* Skip past PREFIX_SEPARATOR and reset token_start. */
4711 if (!current_templates
)
4713 /* Deprecated functionality (new code should use pseudo-prefixes instead):
4714 Check if we should swap operand or force 32bit displacement in
4716 if (mnem_p
- 2 == dot_p
&& dot_p
[1] == 's')
4717 i
.dir_encoding
= dir_encoding_swap
;
4718 else if (mnem_p
- 3 == dot_p
4721 i
.disp_encoding
= disp_encoding_8bit
;
4722 else if (mnem_p
- 4 == dot_p
4726 i
.disp_encoding
= disp_encoding_32bit
;
4731 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
4734 if (!current_templates
)
4737 if (mnem_p
> mnemonic
)
4739 /* See if we can get a match by trimming off a suffix. */
4742 case WORD_MNEM_SUFFIX
:
4743 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
4744 i
.suffix
= SHORT_MNEM_SUFFIX
;
4747 case BYTE_MNEM_SUFFIX
:
4748 case QWORD_MNEM_SUFFIX
:
4749 i
.suffix
= mnem_p
[-1];
4751 current_templates
= (const templates
*) hash_find (op_hash
,
4754 case SHORT_MNEM_SUFFIX
:
4755 case LONG_MNEM_SUFFIX
:
4758 i
.suffix
= mnem_p
[-1];
4760 current_templates
= (const templates
*) hash_find (op_hash
,
4769 if (intel_float_operand (mnemonic
) == 1)
4770 i
.suffix
= SHORT_MNEM_SUFFIX
;
4772 i
.suffix
= LONG_MNEM_SUFFIX
;
4774 current_templates
= (const templates
*) hash_find (op_hash
,
4781 if (!current_templates
)
4783 as_bad (_("no such instruction: `%s'"), token_start
);
4788 if (current_templates
->start
->opcode_modifier
.jump
4789 || current_templates
->start
->opcode_modifier
.jumpbyte
)
4791 /* Check for a branch hint. We allow ",pt" and ",pn" for
4792 predict taken and predict not taken respectively.
4793 I'm not sure that branch hints actually do anything on loop
4794 and jcxz insns (JumpByte) for current Pentium4 chips. They
4795 may work in the future and it doesn't hurt to accept them
4797 if (l
[0] == ',' && l
[1] == 'p')
4801 if (!add_prefix (DS_PREFIX_OPCODE
))
4805 else if (l
[2] == 'n')
4807 if (!add_prefix (CS_PREFIX_OPCODE
))
4813 /* Any other comma loses. */
4816 as_bad (_("invalid character %s in mnemonic"),
4817 output_invalid (*l
));
4821 /* Check if instruction is supported on specified architecture. */
4823 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
4825 supported
|= cpu_flags_match (t
);
4826 if (supported
== CPU_FLAGS_PERFECT_MATCH
)
4828 if (!cpu_arch_flags
.bitfield
.cpui386
&& (flag_code
!= CODE_16BIT
))
4829 as_warn (_("use .code16 to ensure correct addressing mode"));
4835 if (!(supported
& CPU_FLAGS_64BIT_MATCH
))
4836 as_bad (flag_code
== CODE_64BIT
4837 ? _("`%s' is not supported in 64-bit mode")
4838 : _("`%s' is only supported in 64-bit mode"),
4839 current_templates
->start
->name
);
4841 as_bad (_("`%s' is not supported on `%s%s'"),
4842 current_templates
->start
->name
,
4843 cpu_arch_name
? cpu_arch_name
: default_arch
,
4844 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
4850 parse_operands (char *l
, const char *mnemonic
)
4854 /* 1 if operand is pending after ','. */
4855 unsigned int expecting_operand
= 0;
4857 /* Non-zero if operand parens not balanced. */
4858 unsigned int paren_not_balanced
;
4860 while (*l
!= END_OF_INSN
)
4862 /* Skip optional white space before operand. */
4863 if (is_space_char (*l
))
4865 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
&& *l
!= '"')
4867 as_bad (_("invalid character %s before operand %d"),
4868 output_invalid (*l
),
4872 token_start
= l
; /* After white space. */
4873 paren_not_balanced
= 0;
4874 while (paren_not_balanced
|| *l
!= ',')
4876 if (*l
== END_OF_INSN
)
4878 if (paren_not_balanced
)
4881 as_bad (_("unbalanced parenthesis in operand %d."),
4884 as_bad (_("unbalanced brackets in operand %d."),
4889 break; /* we are done */
4891 else if (!is_operand_char (*l
) && !is_space_char (*l
) && *l
!= '"')
4893 as_bad (_("invalid character %s in operand %d"),
4894 output_invalid (*l
),
4901 ++paren_not_balanced
;
4903 --paren_not_balanced
;
4908 ++paren_not_balanced
;
4910 --paren_not_balanced
;
4914 if (l
!= token_start
)
4915 { /* Yes, we've read in another operand. */
4916 unsigned int operand_ok
;
4917 this_operand
= i
.operands
++;
4918 if (i
.operands
> MAX_OPERANDS
)
4920 as_bad (_("spurious operands; (%d operands/instruction max)"),
4924 i
.types
[this_operand
].bitfield
.unspecified
= 1;
4925 /* Now parse operand adding info to 'i' as we go along. */
4926 END_STRING_AND_SAVE (l
);
4928 if (i
.mem_operands
> 1)
4930 as_bad (_("too many memory references for `%s'"),
4937 i386_intel_operand (token_start
,
4938 intel_float_operand (mnemonic
));
4940 operand_ok
= i386_att_operand (token_start
);
4942 RESTORE_END_STRING (l
);
4948 if (expecting_operand
)
4950 expecting_operand_after_comma
:
4951 as_bad (_("expecting operand after ','; got nothing"));
4956 as_bad (_("expecting operand before ','; got nothing"));
4961 /* Now *l must be either ',' or END_OF_INSN. */
4964 if (*++l
== END_OF_INSN
)
4966 /* Just skip it, if it's \n complain. */
4967 goto expecting_operand_after_comma
;
4969 expecting_operand
= 1;
4976 swap_2_operands (int xchg1
, int xchg2
)
4978 union i386_op temp_op
;
4979 i386_operand_type temp_type
;
4980 unsigned int temp_flags
;
4981 enum bfd_reloc_code_real temp_reloc
;
4983 temp_type
= i
.types
[xchg2
];
4984 i
.types
[xchg2
] = i
.types
[xchg1
];
4985 i
.types
[xchg1
] = temp_type
;
4987 temp_flags
= i
.flags
[xchg2
];
4988 i
.flags
[xchg2
] = i
.flags
[xchg1
];
4989 i
.flags
[xchg1
] = temp_flags
;
4991 temp_op
= i
.op
[xchg2
];
4992 i
.op
[xchg2
] = i
.op
[xchg1
];
4993 i
.op
[xchg1
] = temp_op
;
4995 temp_reloc
= i
.reloc
[xchg2
];
4996 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
4997 i
.reloc
[xchg1
] = temp_reloc
;
5001 if (i
.mask
->operand
== xchg1
)
5002 i
.mask
->operand
= xchg2
;
5003 else if (i
.mask
->operand
== xchg2
)
5004 i
.mask
->operand
= xchg1
;
5008 if (i
.broadcast
->operand
== xchg1
)
5009 i
.broadcast
->operand
= xchg2
;
5010 else if (i
.broadcast
->operand
== xchg2
)
5011 i
.broadcast
->operand
= xchg1
;
5015 if (i
.rounding
->operand
== xchg1
)
5016 i
.rounding
->operand
= xchg2
;
5017 else if (i
.rounding
->operand
== xchg2
)
5018 i
.rounding
->operand
= xchg1
;
5023 swap_operands (void)
5029 swap_2_operands (1, i
.operands
- 2);
5033 swap_2_operands (0, i
.operands
- 1);
5039 if (i
.mem_operands
== 2)
5041 const seg_entry
*temp_seg
;
5042 temp_seg
= i
.seg
[0];
5043 i
.seg
[0] = i
.seg
[1];
5044 i
.seg
[1] = temp_seg
;
5048 /* Try to ensure constant immediates are represented in the smallest
5053 char guess_suffix
= 0;
5057 guess_suffix
= i
.suffix
;
5058 else if (i
.reg_operands
)
5060 /* Figure out a suffix from the last register operand specified.
5061 We can't do this properly yet, ie. excluding InOutPortReg,
5062 but the following works for instructions with immediates.
5063 In any case, we can't set i.suffix yet. */
5064 for (op
= i
.operands
; --op
>= 0;)
5065 if (i
.types
[op
].bitfield
.reg
&& i
.types
[op
].bitfield
.byte
)
5067 guess_suffix
= BYTE_MNEM_SUFFIX
;
5070 else if (i
.types
[op
].bitfield
.reg
&& i
.types
[op
].bitfield
.word
)
5072 guess_suffix
= WORD_MNEM_SUFFIX
;
5075 else if (i
.types
[op
].bitfield
.reg
&& i
.types
[op
].bitfield
.dword
)
5077 guess_suffix
= LONG_MNEM_SUFFIX
;
5080 else if (i
.types
[op
].bitfield
.reg
&& i
.types
[op
].bitfield
.qword
)
5082 guess_suffix
= QWORD_MNEM_SUFFIX
;
5086 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
5087 guess_suffix
= WORD_MNEM_SUFFIX
;
5089 for (op
= i
.operands
; --op
>= 0;)
5090 if (operand_type_check (i
.types
[op
], imm
))
5092 switch (i
.op
[op
].imms
->X_op
)
5095 /* If a suffix is given, this operand may be shortened. */
5096 switch (guess_suffix
)
5098 case LONG_MNEM_SUFFIX
:
5099 i
.types
[op
].bitfield
.imm32
= 1;
5100 i
.types
[op
].bitfield
.imm64
= 1;
5102 case WORD_MNEM_SUFFIX
:
5103 i
.types
[op
].bitfield
.imm16
= 1;
5104 i
.types
[op
].bitfield
.imm32
= 1;
5105 i
.types
[op
].bitfield
.imm32s
= 1;
5106 i
.types
[op
].bitfield
.imm64
= 1;
5108 case BYTE_MNEM_SUFFIX
:
5109 i
.types
[op
].bitfield
.imm8
= 1;
5110 i
.types
[op
].bitfield
.imm8s
= 1;
5111 i
.types
[op
].bitfield
.imm16
= 1;
5112 i
.types
[op
].bitfield
.imm32
= 1;
5113 i
.types
[op
].bitfield
.imm32s
= 1;
5114 i
.types
[op
].bitfield
.imm64
= 1;
5118 /* If this operand is at most 16 bits, convert it
5119 to a signed 16 bit number before trying to see
5120 whether it will fit in an even smaller size.
5121 This allows a 16-bit operand such as $0xffe0 to
5122 be recognised as within Imm8S range. */
5123 if ((i
.types
[op
].bitfield
.imm16
)
5124 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
5126 i
.op
[op
].imms
->X_add_number
=
5127 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
5130 /* Store 32-bit immediate in 64-bit for 64-bit BFD. */
5131 if ((i
.types
[op
].bitfield
.imm32
)
5132 && ((i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1))
5135 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
5136 ^ ((offsetT
) 1 << 31))
5137 - ((offsetT
) 1 << 31));
5141 = operand_type_or (i
.types
[op
],
5142 smallest_imm_type (i
.op
[op
].imms
->X_add_number
));
5144 /* We must avoid matching of Imm32 templates when 64bit
5145 only immediate is available. */
5146 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
5147 i
.types
[op
].bitfield
.imm32
= 0;
5154 /* Symbols and expressions. */
5156 /* Convert symbolic operand to proper sizes for matching, but don't
5157 prevent matching a set of insns that only supports sizes other
5158 than those matching the insn suffix. */
5160 i386_operand_type mask
, allowed
;
5161 const insn_template
*t
;
5163 operand_type_set (&mask
, 0);
5164 operand_type_set (&allowed
, 0);
5166 for (t
= current_templates
->start
;
5167 t
< current_templates
->end
;
5169 allowed
= operand_type_or (allowed
,
5170 t
->operand_types
[op
]);
5171 switch (guess_suffix
)
5173 case QWORD_MNEM_SUFFIX
:
5174 mask
.bitfield
.imm64
= 1;
5175 mask
.bitfield
.imm32s
= 1;
5177 case LONG_MNEM_SUFFIX
:
5178 mask
.bitfield
.imm32
= 1;
5180 case WORD_MNEM_SUFFIX
:
5181 mask
.bitfield
.imm16
= 1;
5183 case BYTE_MNEM_SUFFIX
:
5184 mask
.bitfield
.imm8
= 1;
5189 allowed
= operand_type_and (mask
, allowed
);
5190 if (!operand_type_all_zero (&allowed
))
5191 i
.types
[op
] = operand_type_and (i
.types
[op
], mask
);
5198 /* Try to use the smallest displacement type too. */
5200 optimize_disp (void)
5204 for (op
= i
.operands
; --op
>= 0;)
5205 if (operand_type_check (i
.types
[op
], disp
))
5207 if (i
.op
[op
].disps
->X_op
== O_constant
)
5209 offsetT op_disp
= i
.op
[op
].disps
->X_add_number
;
5211 if (i
.types
[op
].bitfield
.disp16
5212 && (op_disp
& ~(offsetT
) 0xffff) == 0)
5214 /* If this operand is at most 16 bits, convert
5215 to a signed 16 bit number and don't use 64bit
5217 op_disp
= (((op_disp
& 0xffff) ^ 0x8000) - 0x8000);
5218 i
.types
[op
].bitfield
.disp64
= 0;
5221 /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */
5222 if (i
.types
[op
].bitfield
.disp32
5223 && (op_disp
& ~(((offsetT
) 2 << 31) - 1)) == 0)
5225 /* If this operand is at most 32 bits, convert
5226 to a signed 32 bit number and don't use 64bit
5228 op_disp
&= (((offsetT
) 2 << 31) - 1);
5229 op_disp
= (op_disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
5230 i
.types
[op
].bitfield
.disp64
= 0;
5233 if (!op_disp
&& i
.types
[op
].bitfield
.baseindex
)
5235 i
.types
[op
].bitfield
.disp8
= 0;
5236 i
.types
[op
].bitfield
.disp16
= 0;
5237 i
.types
[op
].bitfield
.disp32
= 0;
5238 i
.types
[op
].bitfield
.disp32s
= 0;
5239 i
.types
[op
].bitfield
.disp64
= 0;
5243 else if (flag_code
== CODE_64BIT
)
5245 if (fits_in_signed_long (op_disp
))
5247 i
.types
[op
].bitfield
.disp64
= 0;
5248 i
.types
[op
].bitfield
.disp32s
= 1;
5250 if (i
.prefix
[ADDR_PREFIX
]
5251 && fits_in_unsigned_long (op_disp
))
5252 i
.types
[op
].bitfield
.disp32
= 1;
5254 if ((i
.types
[op
].bitfield
.disp32
5255 || i
.types
[op
].bitfield
.disp32s
5256 || i
.types
[op
].bitfield
.disp16
)
5257 && fits_in_disp8 (op_disp
))
5258 i
.types
[op
].bitfield
.disp8
= 1;
5260 else if (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
5261 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
)
5263 fix_new_exp (frag_now
, frag_more (0) - frag_now
->fr_literal
, 0,
5264 i
.op
[op
].disps
, 0, i
.reloc
[op
]);
5265 i
.types
[op
].bitfield
.disp8
= 0;
5266 i
.types
[op
].bitfield
.disp16
= 0;
5267 i
.types
[op
].bitfield
.disp32
= 0;
5268 i
.types
[op
].bitfield
.disp32s
= 0;
5269 i
.types
[op
].bitfield
.disp64
= 0;
5272 /* We only support 64bit displacement on constants. */
5273 i
.types
[op
].bitfield
.disp64
= 0;
5277 /* Return 1 if there is a match in broadcast bytes between operand
5278 GIVEN and instruction template T. */
5281 match_broadcast_size (const insn_template
*t
, unsigned int given
)
5283 return ((t
->opcode_modifier
.broadcast
== BYTE_BROADCAST
5284 && i
.types
[given
].bitfield
.byte
)
5285 || (t
->opcode_modifier
.broadcast
== WORD_BROADCAST
5286 && i
.types
[given
].bitfield
.word
)
5287 || (t
->opcode_modifier
.broadcast
== DWORD_BROADCAST
5288 && i
.types
[given
].bitfield
.dword
)
5289 || (t
->opcode_modifier
.broadcast
== QWORD_BROADCAST
5290 && i
.types
[given
].bitfield
.qword
));
5293 /* Check if operands are valid for the instruction. */
5296 check_VecOperands (const insn_template
*t
)
5300 static const i386_cpu_flags avx512
= CPU_ANY_AVX512F_FLAGS
;
5302 /* Templates allowing for ZMMword as well as YMMword and/or XMMword for
5303 any one operand are implicity requiring AVX512VL support if the actual
5304 operand size is YMMword or XMMword. Since this function runs after
5305 template matching, there's no need to check for YMMword/XMMword in
5307 cpu
= cpu_flags_and (t
->cpu_flags
, avx512
);
5308 if (!cpu_flags_all_zero (&cpu
)
5309 && !t
->cpu_flags
.bitfield
.cpuavx512vl
5310 && !cpu_arch_flags
.bitfield
.cpuavx512vl
)
5312 for (op
= 0; op
< t
->operands
; ++op
)
5314 if (t
->operand_types
[op
].bitfield
.zmmword
5315 && (i
.types
[op
].bitfield
.ymmword
5316 || i
.types
[op
].bitfield
.xmmword
))
5318 i
.error
= unsupported
;
5324 /* Without VSIB byte, we can't have a vector register for index. */
5325 if (!t
->opcode_modifier
.vecsib
5327 && (i
.index_reg
->reg_type
.bitfield
.xmmword
5328 || i
.index_reg
->reg_type
.bitfield
.ymmword
5329 || i
.index_reg
->reg_type
.bitfield
.zmmword
))
5331 i
.error
= unsupported_vector_index_register
;
5335 /* Check if default mask is allowed. */
5336 if (t
->opcode_modifier
.nodefmask
5337 && (!i
.mask
|| i
.mask
->mask
->reg_num
== 0))
5339 i
.error
= no_default_mask
;
5343 /* For VSIB byte, we need a vector register for index, and all vector
5344 registers must be distinct. */
5345 if (t
->opcode_modifier
.vecsib
)
5348 || !((t
->opcode_modifier
.vecsib
== VecSIB128
5349 && i
.index_reg
->reg_type
.bitfield
.xmmword
)
5350 || (t
->opcode_modifier
.vecsib
== VecSIB256
5351 && i
.index_reg
->reg_type
.bitfield
.ymmword
)
5352 || (t
->opcode_modifier
.vecsib
== VecSIB512
5353 && i
.index_reg
->reg_type
.bitfield
.zmmword
)))
5355 i
.error
= invalid_vsib_address
;
5359 gas_assert (i
.reg_operands
== 2 || i
.mask
);
5360 if (i
.reg_operands
== 2 && !i
.mask
)
5362 gas_assert (i
.types
[0].bitfield
.regsimd
);
5363 gas_assert (i
.types
[0].bitfield
.xmmword
5364 || i
.types
[0].bitfield
.ymmword
);
5365 gas_assert (i
.types
[2].bitfield
.regsimd
);
5366 gas_assert (i
.types
[2].bitfield
.xmmword
5367 || i
.types
[2].bitfield
.ymmword
);
5368 if (operand_check
== check_none
)
5370 if (register_number (i
.op
[0].regs
)
5371 != register_number (i
.index_reg
)
5372 && register_number (i
.op
[2].regs
)
5373 != register_number (i
.index_reg
)
5374 && register_number (i
.op
[0].regs
)
5375 != register_number (i
.op
[2].regs
))
5377 if (operand_check
== check_error
)
5379 i
.error
= invalid_vector_register_set
;
5382 as_warn (_("mask, index, and destination registers should be distinct"));
5384 else if (i
.reg_operands
== 1 && i
.mask
)
5386 if (i
.types
[1].bitfield
.regsimd
5387 && (i
.types
[1].bitfield
.xmmword
5388 || i
.types
[1].bitfield
.ymmword
5389 || i
.types
[1].bitfield
.zmmword
)
5390 && (register_number (i
.op
[1].regs
)
5391 == register_number (i
.index_reg
)))
5393 if (operand_check
== check_error
)
5395 i
.error
= invalid_vector_register_set
;
5398 if (operand_check
!= check_none
)
5399 as_warn (_("index and destination registers should be distinct"));
5404 /* Check if broadcast is supported by the instruction and is applied
5405 to the memory operand. */
5408 i386_operand_type type
, overlap
;
5410 /* Check if specified broadcast is supported in this instruction,
5411 and its broadcast bytes match the memory operand. */
5412 op
= i
.broadcast
->operand
;
5413 if (!t
->opcode_modifier
.broadcast
5414 || !(i
.flags
[op
] & Operand_Mem
)
5415 || (!i
.types
[op
].bitfield
.unspecified
5416 && !match_broadcast_size (t
, op
)))
5419 i
.error
= unsupported_broadcast
;
5423 i
.broadcast
->bytes
= ((1 << (t
->opcode_modifier
.broadcast
- 1))
5424 * i
.broadcast
->type
);
5425 operand_type_set (&type
, 0);
5426 switch (i
.broadcast
->bytes
)
5429 type
.bitfield
.word
= 1;
5432 type
.bitfield
.dword
= 1;
5435 type
.bitfield
.qword
= 1;
5438 type
.bitfield
.xmmword
= 1;
5441 type
.bitfield
.ymmword
= 1;
5444 type
.bitfield
.zmmword
= 1;
5450 overlap
= operand_type_and (type
, t
->operand_types
[op
]);
5451 if (operand_type_all_zero (&overlap
))
5454 if (t
->opcode_modifier
.checkregsize
)
5458 type
.bitfield
.baseindex
= 1;
5459 for (j
= 0; j
< i
.operands
; ++j
)
5462 && !operand_type_register_match(i
.types
[j
],
5463 t
->operand_types
[j
],
5465 t
->operand_types
[op
]))
5470 /* If broadcast is supported in this instruction, we need to check if
5471 operand of one-element size isn't specified without broadcast. */
5472 else if (t
->opcode_modifier
.broadcast
&& i
.mem_operands
)
5474 /* Find memory operand. */
5475 for (op
= 0; op
< i
.operands
; op
++)
5476 if (i
.flags
[op
] & Operand_Mem
)
5478 gas_assert (op
< i
.operands
);
5479 /* Check size of the memory operand. */
5480 if (match_broadcast_size (t
, op
))
5482 i
.error
= broadcast_needed
;
5487 op
= MAX_OPERANDS
- 1; /* Avoid uninitialized variable warning. */
5489 /* Check if requested masking is supported. */
5492 switch (t
->opcode_modifier
.masking
)
5496 case MERGING_MASKING
:
5497 if (i
.mask
->zeroing
)
5500 i
.error
= unsupported_masking
;
5504 case DYNAMIC_MASKING
:
5505 /* Memory destinations allow only merging masking. */
5506 if (i
.mask
->zeroing
&& i
.mem_operands
)
5508 /* Find memory operand. */
5509 for (op
= 0; op
< i
.operands
; op
++)
5510 if (i
.flags
[op
] & Operand_Mem
)
5512 gas_assert (op
< i
.operands
);
5513 if (op
== i
.operands
- 1)
5515 i
.error
= unsupported_masking
;
5525 /* Check if masking is applied to dest operand. */
5526 if (i
.mask
&& (i
.mask
->operand
!= (int) (i
.operands
- 1)))
5528 i
.error
= mask_not_on_destination
;
5535 if (!t
->opcode_modifier
.sae
5536 || (i
.rounding
->type
!= saeonly
&& !t
->opcode_modifier
.staticrounding
))
5538 i
.error
= unsupported_rc_sae
;
5541 /* If the instruction has several immediate operands and one of
5542 them is rounding, the rounding operand should be the last
5543 immediate operand. */
5544 if (i
.imm_operands
> 1
5545 && i
.rounding
->operand
!= (int) (i
.imm_operands
- 1))
5547 i
.error
= rc_sae_operand_not_last_imm
;
5552 /* Check vector Disp8 operand. */
5553 if (t
->opcode_modifier
.disp8memshift
5554 && i
.disp_encoding
!= disp_encoding_32bit
)
5557 i
.memshift
= t
->opcode_modifier
.broadcast
- 1;
5558 else if (t
->opcode_modifier
.disp8memshift
!= DISP8_SHIFT_VL
)
5559 i
.memshift
= t
->opcode_modifier
.disp8memshift
;
5562 const i386_operand_type
*type
= NULL
;
5565 for (op
= 0; op
< i
.operands
; op
++)
5566 if (i
.flags
[op
] & Operand_Mem
)
5568 if (t
->opcode_modifier
.evex
== EVEXLIG
)
5569 i
.memshift
= 2 + (i
.suffix
== QWORD_MNEM_SUFFIX
);
5570 else if (t
->operand_types
[op
].bitfield
.xmmword
5571 + t
->operand_types
[op
].bitfield
.ymmword
5572 + t
->operand_types
[op
].bitfield
.zmmword
<= 1)
5573 type
= &t
->operand_types
[op
];
5574 else if (!i
.types
[op
].bitfield
.unspecified
)
5575 type
= &i
.types
[op
];
5577 else if (i
.types
[op
].bitfield
.regsimd
5578 && t
->opcode_modifier
.evex
!= EVEXLIG
)
5580 if (i
.types
[op
].bitfield
.zmmword
)
5582 else if (i
.types
[op
].bitfield
.ymmword
&& i
.memshift
< 5)
5584 else if (i
.types
[op
].bitfield
.xmmword
&& i
.memshift
< 4)
5590 if (type
->bitfield
.zmmword
)
5592 else if (type
->bitfield
.ymmword
)
5594 else if (type
->bitfield
.xmmword
)
5598 /* For the check in fits_in_disp8(). */
5599 if (i
.memshift
== 0)
5603 for (op
= 0; op
< i
.operands
; op
++)
5604 if (operand_type_check (i
.types
[op
], disp
)
5605 && i
.op
[op
].disps
->X_op
== O_constant
)
5607 if (fits_in_disp8 (i
.op
[op
].disps
->X_add_number
))
5609 i
.types
[op
].bitfield
.disp8
= 1;
5612 i
.types
[op
].bitfield
.disp8
= 0;
5621 /* Check if operands are valid for the instruction. Update VEX
5625 VEX_check_operands (const insn_template
*t
)
5627 if (i
.vec_encoding
== vex_encoding_evex
)
5629 /* This instruction must be encoded with EVEX prefix. */
5630 if (!is_evex_encoding (t
))
5632 i
.error
= unsupported
;
5638 if (!t
->opcode_modifier
.vex
)
5640 /* This instruction template doesn't have VEX prefix. */
5641 if (i
.vec_encoding
!= vex_encoding_default
)
5643 i
.error
= unsupported
;
5649 /* Check the special Imm4 cases; must be the first operand. */
5650 if (t
->cpu_flags
.bitfield
.cpuxop
&& t
->operands
== 5)
5652 if (i
.op
[0].imms
->X_op
!= O_constant
5653 || !fits_in_imm4 (i
.op
[0].imms
->X_add_number
))
5659 /* Turn off Imm<N> so that update_imm won't complain. */
5660 operand_type_set (&i
.types
[0], 0);
5666 static const insn_template
*
5667 match_template (char mnem_suffix
)
5669 /* Points to template once we've found it. */
5670 const insn_template
*t
;
5671 i386_operand_type overlap0
, overlap1
, overlap2
, overlap3
;
5672 i386_operand_type overlap4
;
5673 unsigned int found_reverse_match
;
5674 i386_opcode_modifier suffix_check
, mnemsuf_check
;
5675 i386_operand_type operand_types
[MAX_OPERANDS
];
5676 int addr_prefix_disp
;
5678 unsigned int found_cpu_match
, size_match
;
5679 unsigned int check_register
;
5680 enum i386_error specific_error
= 0;
5682 #if MAX_OPERANDS != 5
5683 # error "MAX_OPERANDS must be 5."
5686 found_reverse_match
= 0;
5687 addr_prefix_disp
= -1;
5689 memset (&suffix_check
, 0, sizeof (suffix_check
));
5690 if (intel_syntax
&& i
.broadcast
)
5692 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
5693 suffix_check
.no_bsuf
= 1;
5694 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
5695 suffix_check
.no_wsuf
= 1;
5696 else if (i
.suffix
== SHORT_MNEM_SUFFIX
)
5697 suffix_check
.no_ssuf
= 1;
5698 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
5699 suffix_check
.no_lsuf
= 1;
5700 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
5701 suffix_check
.no_qsuf
= 1;
5702 else if (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
)
5703 suffix_check
.no_ldsuf
= 1;
5705 memset (&mnemsuf_check
, 0, sizeof (mnemsuf_check
));
5708 switch (mnem_suffix
)
5710 case BYTE_MNEM_SUFFIX
: mnemsuf_check
.no_bsuf
= 1; break;
5711 case WORD_MNEM_SUFFIX
: mnemsuf_check
.no_wsuf
= 1; break;
5712 case SHORT_MNEM_SUFFIX
: mnemsuf_check
.no_ssuf
= 1; break;
5713 case LONG_MNEM_SUFFIX
: mnemsuf_check
.no_lsuf
= 1; break;
5714 case QWORD_MNEM_SUFFIX
: mnemsuf_check
.no_qsuf
= 1; break;
5718 /* Must have right number of operands. */
5719 i
.error
= number_of_operands_mismatch
;
5721 for (t
= current_templates
->start
; t
< current_templates
->end
; t
++)
5723 addr_prefix_disp
= -1;
5724 found_reverse_match
= 0;
5726 if (i
.operands
!= t
->operands
)
5729 /* Check processor support. */
5730 i
.error
= unsupported
;
5731 found_cpu_match
= (cpu_flags_match (t
)
5732 == CPU_FLAGS_PERFECT_MATCH
);
5733 if (!found_cpu_match
)
5736 /* Check AT&T mnemonic. */
5737 i
.error
= unsupported_with_intel_mnemonic
;
5738 if (intel_mnemonic
&& t
->opcode_modifier
.attmnemonic
)
5741 /* Check AT&T/Intel syntax and Intel64/AMD64 ISA. */
5742 i
.error
= unsupported_syntax
;
5743 if ((intel_syntax
&& t
->opcode_modifier
.attsyntax
)
5744 || (!intel_syntax
&& t
->opcode_modifier
.intelsyntax
)
5745 || (intel64
&& t
->opcode_modifier
.amd64
)
5746 || (!intel64
&& t
->opcode_modifier
.intel64
))
5749 /* Check the suffix, except for some instructions in intel mode. */
5750 i
.error
= invalid_instruction_suffix
;
5751 if ((!intel_syntax
|| !t
->opcode_modifier
.ignoresize
)
5752 && ((t
->opcode_modifier
.no_bsuf
&& suffix_check
.no_bsuf
)
5753 || (t
->opcode_modifier
.no_wsuf
&& suffix_check
.no_wsuf
)
5754 || (t
->opcode_modifier
.no_lsuf
&& suffix_check
.no_lsuf
)
5755 || (t
->opcode_modifier
.no_ssuf
&& suffix_check
.no_ssuf
)
5756 || (t
->opcode_modifier
.no_qsuf
&& suffix_check
.no_qsuf
)
5757 || (t
->opcode_modifier
.no_ldsuf
&& suffix_check
.no_ldsuf
)))
5759 /* In Intel mode all mnemonic suffixes must be explicitly allowed. */
5760 if ((t
->opcode_modifier
.no_bsuf
&& mnemsuf_check
.no_bsuf
)
5761 || (t
->opcode_modifier
.no_wsuf
&& mnemsuf_check
.no_wsuf
)
5762 || (t
->opcode_modifier
.no_lsuf
&& mnemsuf_check
.no_lsuf
)
5763 || (t
->opcode_modifier
.no_ssuf
&& mnemsuf_check
.no_ssuf
)
5764 || (t
->opcode_modifier
.no_qsuf
&& mnemsuf_check
.no_qsuf
)
5765 || (t
->opcode_modifier
.no_ldsuf
&& mnemsuf_check
.no_ldsuf
))
5768 size_match
= operand_size_match (t
);
5772 for (j
= 0; j
< MAX_OPERANDS
; j
++)
5773 operand_types
[j
] = t
->operand_types
[j
];
5775 /* In general, don't allow 64-bit operands in 32-bit mode. */
5776 if (i
.suffix
== QWORD_MNEM_SUFFIX
5777 && flag_code
!= CODE_64BIT
5779 ? (!t
->opcode_modifier
.ignoresize
5780 && !t
->opcode_modifier
.broadcast
5781 && !intel_float_operand (t
->name
))
5782 : intel_float_operand (t
->name
) != 2)
5783 && ((!operand_types
[0].bitfield
.regmmx
5784 && !operand_types
[0].bitfield
.regsimd
)
5785 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
5786 && !operand_types
[t
->operands
> 1].bitfield
.regsimd
))
5787 && (t
->base_opcode
!= 0x0fc7
5788 || t
->extension_opcode
!= 1 /* cmpxchg8b */))
5791 /* In general, don't allow 32-bit operands on pre-386. */
5792 else if (i
.suffix
== LONG_MNEM_SUFFIX
5793 && !cpu_arch_flags
.bitfield
.cpui386
5795 ? (!t
->opcode_modifier
.ignoresize
5796 && !intel_float_operand (t
->name
))
5797 : intel_float_operand (t
->name
) != 2)
5798 && ((!operand_types
[0].bitfield
.regmmx
5799 && !operand_types
[0].bitfield
.regsimd
)
5800 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
5801 && !operand_types
[t
->operands
> 1].bitfield
.regsimd
)))
5804 /* Do not verify operands when there are none. */
5808 /* We've found a match; break out of loop. */
5812 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
5813 into Disp32/Disp16/Disp32 operand. */
5814 if (i
.prefix
[ADDR_PREFIX
] != 0)
5816 /* There should be only one Disp operand. */
5820 for (j
= 0; j
< MAX_OPERANDS
; j
++)
5822 if (operand_types
[j
].bitfield
.disp16
)
5824 addr_prefix_disp
= j
;
5825 operand_types
[j
].bitfield
.disp32
= 1;
5826 operand_types
[j
].bitfield
.disp16
= 0;
5832 for (j
= 0; j
< MAX_OPERANDS
; j
++)
5834 if (operand_types
[j
].bitfield
.disp32
)
5836 addr_prefix_disp
= j
;
5837 operand_types
[j
].bitfield
.disp32
= 0;
5838 operand_types
[j
].bitfield
.disp16
= 1;
5844 for (j
= 0; j
< MAX_OPERANDS
; j
++)
5846 if (operand_types
[j
].bitfield
.disp64
)
5848 addr_prefix_disp
= j
;
5849 operand_types
[j
].bitfield
.disp64
= 0;
5850 operand_types
[j
].bitfield
.disp32
= 1;
5858 /* Force 0x8b encoding for "mov foo@GOT, %eax". */
5859 if (i
.reloc
[0] == BFD_RELOC_386_GOT32
&& t
->base_opcode
== 0xa0)
5862 /* We check register size if needed. */
5863 if (t
->opcode_modifier
.checkregsize
)
5865 check_register
= (1 << t
->operands
) - 1;
5867 check_register
&= ~(1 << i
.broadcast
->operand
);
5872 overlap0
= operand_type_and (i
.types
[0], operand_types
[0]);
5873 switch (t
->operands
)
5876 if (!operand_type_match (overlap0
, i
.types
[0]))
5880 /* xchg %eax, %eax is a special case. It is an alias for nop
5881 only in 32bit mode and we can use opcode 0x90. In 64bit
5882 mode, we can't use 0x90 for xchg %eax, %eax since it should
5883 zero-extend %eax to %rax. */
5884 if (flag_code
== CODE_64BIT
5885 && t
->base_opcode
== 0x90
5886 && i
.types
[0].bitfield
.acc
&& i
.types
[0].bitfield
.dword
5887 && i
.types
[1].bitfield
.acc
&& i
.types
[1].bitfield
.dword
)
5889 /* xrelease mov %eax, <disp> is another special case. It must not
5890 match the accumulator-only encoding of mov. */
5891 if (flag_code
!= CODE_64BIT
5893 && t
->base_opcode
== 0xa0
5894 && i
.types
[0].bitfield
.acc
5895 && (i
.flags
[1] & Operand_Mem
))
5900 if (!(size_match
& MATCH_STRAIGHT
))
5902 /* Reverse direction of operands if swapping is possible in the first
5903 place (operands need to be symmetric) and
5904 - the load form is requested, and the template is a store form,
5905 - the store form is requested, and the template is a load form,
5906 - the non-default (swapped) form is requested. */
5907 overlap1
= operand_type_and (operand_types
[0], operand_types
[1]);
5908 if (t
->opcode_modifier
.d
&& i
.reg_operands
== i
.operands
5909 && !operand_type_all_zero (&overlap1
))
5910 switch (i
.dir_encoding
)
5912 case dir_encoding_load
:
5913 if (operand_type_check (operand_types
[i
.operands
- 1], anymem
)
5914 || t
->opcode_modifier
.regmem
)
5918 case dir_encoding_store
:
5919 if (!operand_type_check (operand_types
[i
.operands
- 1], anymem
)
5920 && !t
->opcode_modifier
.regmem
)
5924 case dir_encoding_swap
:
5927 case dir_encoding_default
:
5930 /* If we want store form, we skip the current load. */
5931 if ((i
.dir_encoding
== dir_encoding_store
5932 || i
.dir_encoding
== dir_encoding_swap
)
5933 && i
.mem_operands
== 0
5934 && t
->opcode_modifier
.load
)
5939 overlap1
= operand_type_and (i
.types
[1], operand_types
[1]);
5940 if (!operand_type_match (overlap0
, i
.types
[0])
5941 || !operand_type_match (overlap1
, i
.types
[1])
5942 || ((check_register
& 3) == 3
5943 && !operand_type_register_match (i
.types
[0],
5948 /* Check if other direction is valid ... */
5949 if (!t
->opcode_modifier
.d
)
5953 if (!(size_match
& MATCH_REVERSE
))
5955 /* Try reversing direction of operands. */
5956 overlap0
= operand_type_and (i
.types
[0], operand_types
[i
.operands
- 1]);
5957 overlap1
= operand_type_and (i
.types
[i
.operands
- 1], operand_types
[0]);
5958 if (!operand_type_match (overlap0
, i
.types
[0])
5959 || !operand_type_match (overlap1
, i
.types
[i
.operands
- 1])
5961 && !operand_type_register_match (i
.types
[0],
5962 operand_types
[i
.operands
- 1],
5963 i
.types
[i
.operands
- 1],
5966 /* Does not match either direction. */
5969 /* found_reverse_match holds which of D or FloatR
5971 if (!t
->opcode_modifier
.d
)
5972 found_reverse_match
= 0;
5973 else if (operand_types
[0].bitfield
.tbyte
)
5974 found_reverse_match
= Opcode_FloatD
;
5975 else if (operand_types
[0].bitfield
.xmmword
5976 || operand_types
[i
.operands
- 1].bitfield
.xmmword
5977 || operand_types
[0].bitfield
.regmmx
5978 || operand_types
[i
.operands
- 1].bitfield
.regmmx
5979 || is_any_vex_encoding(t
))
5980 found_reverse_match
= (t
->base_opcode
& 0xee) != 0x6e
5981 ? Opcode_SIMD_FloatD
: Opcode_SIMD_IntD
;
5983 found_reverse_match
= Opcode_D
;
5984 if (t
->opcode_modifier
.floatr
)
5985 found_reverse_match
|= Opcode_FloatR
;
5989 /* Found a forward 2 operand match here. */
5990 switch (t
->operands
)
5993 overlap4
= operand_type_and (i
.types
[4],
5997 overlap3
= operand_type_and (i
.types
[3],
6001 overlap2
= operand_type_and (i
.types
[2],
6006 switch (t
->operands
)
6009 if (!operand_type_match (overlap4
, i
.types
[4])
6010 || !operand_type_register_match (i
.types
[3],
6017 if (!operand_type_match (overlap3
, i
.types
[3])
6018 || ((check_register
& 0xa) == 0xa
6019 && !operand_type_register_match (i
.types
[1],
6023 || ((check_register
& 0xc) == 0xc
6024 && !operand_type_register_match (i
.types
[2],
6031 /* Here we make use of the fact that there are no
6032 reverse match 3 operand instructions. */
6033 if (!operand_type_match (overlap2
, i
.types
[2])
6034 || ((check_register
& 5) == 5
6035 && !operand_type_register_match (i
.types
[0],
6039 || ((check_register
& 6) == 6
6040 && !operand_type_register_match (i
.types
[1],
6048 /* Found either forward/reverse 2, 3 or 4 operand match here:
6049 slip through to break. */
6051 if (!found_cpu_match
)
6054 /* Check if vector and VEX operands are valid. */
6055 if (check_VecOperands (t
) || VEX_check_operands (t
))
6057 specific_error
= i
.error
;
6061 /* We've found a match; break out of loop. */
6065 if (t
== current_templates
->end
)
6067 /* We found no match. */
6068 const char *err_msg
;
6069 switch (specific_error
? specific_error
: i
.error
)
6073 case operand_size_mismatch
:
6074 err_msg
= _("operand size mismatch");
6076 case operand_type_mismatch
:
6077 err_msg
= _("operand type mismatch");
6079 case register_type_mismatch
:
6080 err_msg
= _("register type mismatch");
6082 case number_of_operands_mismatch
:
6083 err_msg
= _("number of operands mismatch");
6085 case invalid_instruction_suffix
:
6086 err_msg
= _("invalid instruction suffix");
6089 err_msg
= _("constant doesn't fit in 4 bits");
6091 case unsupported_with_intel_mnemonic
:
6092 err_msg
= _("unsupported with Intel mnemonic");
6094 case unsupported_syntax
:
6095 err_msg
= _("unsupported syntax");
6098 as_bad (_("unsupported instruction `%s'"),
6099 current_templates
->start
->name
);
6101 case invalid_vsib_address
:
6102 err_msg
= _("invalid VSIB address");
6104 case invalid_vector_register_set
:
6105 err_msg
= _("mask, index, and destination registers must be distinct");
6107 case unsupported_vector_index_register
:
6108 err_msg
= _("unsupported vector index register");
6110 case unsupported_broadcast
:
6111 err_msg
= _("unsupported broadcast");
6113 case broadcast_needed
:
6114 err_msg
= _("broadcast is needed for operand of such type");
6116 case unsupported_masking
:
6117 err_msg
= _("unsupported masking");
6119 case mask_not_on_destination
:
6120 err_msg
= _("mask not on destination operand");
6122 case no_default_mask
:
6123 err_msg
= _("default mask isn't allowed");
6125 case unsupported_rc_sae
:
6126 err_msg
= _("unsupported static rounding/sae");
6128 case rc_sae_operand_not_last_imm
:
6130 err_msg
= _("RC/SAE operand must precede immediate operands");
6132 err_msg
= _("RC/SAE operand must follow immediate operands");
6134 case invalid_register_operand
:
6135 err_msg
= _("invalid register operand");
6138 as_bad (_("%s for `%s'"), err_msg
,
6139 current_templates
->start
->name
);
6143 if (!quiet_warnings
)
6146 && (i
.types
[0].bitfield
.jumpabsolute
6147 != operand_types
[0].bitfield
.jumpabsolute
))
6149 as_warn (_("indirect %s without `*'"), t
->name
);
6152 if (t
->opcode_modifier
.isprefix
6153 && t
->opcode_modifier
.ignoresize
)
6155 /* Warn them that a data or address size prefix doesn't
6156 affect assembly of the next line of code. */
6157 as_warn (_("stand-alone `%s' prefix"), t
->name
);
6161 /* Copy the template we found. */
6164 if (addr_prefix_disp
!= -1)
6165 i
.tm
.operand_types
[addr_prefix_disp
]
6166 = operand_types
[addr_prefix_disp
];
6168 if (found_reverse_match
)
6170 /* If we found a reverse match we must alter the opcode direction
6171 bit and clear/flip the regmem modifier one. found_reverse_match
6172 holds bits to change (different for int & float insns). */
6174 i
.tm
.base_opcode
^= found_reverse_match
;
6176 i
.tm
.operand_types
[0] = operand_types
[i
.operands
- 1];
6177 i
.tm
.operand_types
[i
.operands
- 1] = operand_types
[0];
6179 /* Certain SIMD insns have their load forms specified in the opcode
6180 table, and hence we need to _set_ RegMem instead of clearing it.
6181 We need to avoid setting the bit though on insns like KMOVW. */
6182 i
.tm
.opcode_modifier
.regmem
6183 = i
.tm
.opcode_modifier
.modrm
&& i
.tm
.opcode_modifier
.d
6184 && i
.tm
.operands
> 2U - i
.tm
.opcode_modifier
.sse2avx
6185 && !i
.tm
.opcode_modifier
.regmem
;
6194 unsigned int mem_op
= i
.flags
[0] & Operand_Mem
? 0 : 1;
6196 if (i
.tm
.operand_types
[mem_op
].bitfield
.esseg
)
6198 if (i
.seg
[0] != NULL
&& i
.seg
[0] != &es
)
6200 as_bad (_("`%s' operand %d must use `%ses' segment"),
6202 intel_syntax
? i
.tm
.operands
- mem_op
: mem_op
+ 1,
6206 /* There's only ever one segment override allowed per instruction.
6207 This instruction possibly has a legal segment override on the
6208 second operand, so copy the segment to where non-string
6209 instructions store it, allowing common code. */
6210 i
.seg
[0] = i
.seg
[1];
6212 else if (i
.tm
.operand_types
[mem_op
+ 1].bitfield
.esseg
)
6214 if (i
.seg
[1] != NULL
&& i
.seg
[1] != &es
)
6216 as_bad (_("`%s' operand %d must use `%ses' segment"),
6218 intel_syntax
? i
.tm
.operands
- mem_op
- 1 : mem_op
+ 2,
6227 process_suffix (void)
6229 /* If matched instruction specifies an explicit instruction mnemonic
6231 if (i
.tm
.opcode_modifier
.size
== SIZE16
)
6232 i
.suffix
= WORD_MNEM_SUFFIX
;
6233 else if (i
.tm
.opcode_modifier
.size
== SIZE32
)
6234 i
.suffix
= LONG_MNEM_SUFFIX
;
6235 else if (i
.tm
.opcode_modifier
.size
== SIZE64
)
6236 i
.suffix
= QWORD_MNEM_SUFFIX
;
6237 else if (i
.reg_operands
)
6239 /* If there's no instruction mnemonic suffix we try to invent one
6240 based on register operands. */
6243 /* We take i.suffix from the last register operand specified,
6244 Destination register type is more significant than source
6245 register type. crc32 in SSE4.2 prefers source register
6247 if (i
.tm
.base_opcode
== 0xf20f38f0 && i
.types
[0].bitfield
.reg
)
6249 if (i
.types
[0].bitfield
.byte
)
6250 i
.suffix
= BYTE_MNEM_SUFFIX
;
6251 else if (i
.types
[0].bitfield
.word
)
6252 i
.suffix
= WORD_MNEM_SUFFIX
;
6253 else if (i
.types
[0].bitfield
.dword
)
6254 i
.suffix
= LONG_MNEM_SUFFIX
;
6255 else if (i
.types
[0].bitfield
.qword
)
6256 i
.suffix
= QWORD_MNEM_SUFFIX
;
6263 if (i
.tm
.base_opcode
== 0xf20f38f0)
6265 /* We have to know the operand size for crc32. */
6266 as_bad (_("ambiguous memory operand size for `%s`"),
6271 for (op
= i
.operands
; --op
>= 0;)
6272 if (!i
.tm
.operand_types
[op
].bitfield
.inoutportreg
6273 && !i
.tm
.operand_types
[op
].bitfield
.shiftcount
)
6275 if (!i
.types
[op
].bitfield
.reg
)
6277 if (i
.types
[op
].bitfield
.byte
)
6278 i
.suffix
= BYTE_MNEM_SUFFIX
;
6279 else if (i
.types
[op
].bitfield
.word
)
6280 i
.suffix
= WORD_MNEM_SUFFIX
;
6281 else if (i
.types
[op
].bitfield
.dword
)
6282 i
.suffix
= LONG_MNEM_SUFFIX
;
6283 else if (i
.types
[op
].bitfield
.qword
)
6284 i
.suffix
= QWORD_MNEM_SUFFIX
;
6291 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
6294 && i
.tm
.opcode_modifier
.ignoresize
6295 && i
.tm
.opcode_modifier
.no_bsuf
)
6297 else if (!check_byte_reg ())
6300 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
6303 && i
.tm
.opcode_modifier
.ignoresize
6304 && i
.tm
.opcode_modifier
.no_lsuf
6305 && !i
.tm
.opcode_modifier
.todword
6306 && !i
.tm
.opcode_modifier
.toqword
)
6308 else if (!check_long_reg ())
6311 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
6314 && i
.tm
.opcode_modifier
.ignoresize
6315 && i
.tm
.opcode_modifier
.no_qsuf
6316 && !i
.tm
.opcode_modifier
.todword
6317 && !i
.tm
.opcode_modifier
.toqword
)
6319 else if (!check_qword_reg ())
6322 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
6325 && i
.tm
.opcode_modifier
.ignoresize
6326 && i
.tm
.opcode_modifier
.no_wsuf
)
6328 else if (!check_word_reg ())
6331 else if (intel_syntax
&& i
.tm
.opcode_modifier
.ignoresize
)
6332 /* Do nothing if the instruction is going to ignore the prefix. */
6337 else if (i
.tm
.opcode_modifier
.defaultsize
6339 /* exclude fldenv/frstor/fsave/fstenv */
6340 && i
.tm
.opcode_modifier
.no_ssuf
)
6342 if (stackop_size
== LONG_MNEM_SUFFIX
6343 && i
.tm
.base_opcode
== 0xcf)
6345 /* stackop_size is set to LONG_MNEM_SUFFIX for the
6346 .code16gcc directive to support 16-bit mode with
6347 32-bit address. For IRET without a suffix, generate
6348 16-bit IRET (opcode 0xcf) to return from an interrupt
6350 i
.suffix
= WORD_MNEM_SUFFIX
;
6351 as_warn (_("generating 16-bit `iret' for .code16gcc directive"));
6354 i
.suffix
= stackop_size
;
6356 else if (intel_syntax
6358 && (i
.tm
.operand_types
[0].bitfield
.jumpabsolute
6359 || i
.tm
.opcode_modifier
.jumpbyte
6360 || i
.tm
.opcode_modifier
.jumpintersegment
6361 || (i
.tm
.base_opcode
== 0x0f01 /* [ls][gi]dt */
6362 && i
.tm
.extension_opcode
<= 3)))
6367 if (!i
.tm
.opcode_modifier
.no_qsuf
)
6369 i
.suffix
= QWORD_MNEM_SUFFIX
;
6374 if (!i
.tm
.opcode_modifier
.no_lsuf
)
6375 i
.suffix
= LONG_MNEM_SUFFIX
;
6378 if (!i
.tm
.opcode_modifier
.no_wsuf
)
6379 i
.suffix
= WORD_MNEM_SUFFIX
;
6388 if (i
.tm
.opcode_modifier
.w
)
6390 as_bad (_("no instruction mnemonic suffix given and "
6391 "no register operands; can't size instruction"));
6397 unsigned int suffixes
;
6399 suffixes
= !i
.tm
.opcode_modifier
.no_bsuf
;
6400 if (!i
.tm
.opcode_modifier
.no_wsuf
)
6402 if (!i
.tm
.opcode_modifier
.no_lsuf
)
6404 if (!i
.tm
.opcode_modifier
.no_ldsuf
)
6406 if (!i
.tm
.opcode_modifier
.no_ssuf
)
6408 if (flag_code
== CODE_64BIT
&& !i
.tm
.opcode_modifier
.no_qsuf
)
6411 /* There are more than suffix matches. */
6412 if (i
.tm
.opcode_modifier
.w
6413 || ((suffixes
& (suffixes
- 1))
6414 && !i
.tm
.opcode_modifier
.defaultsize
6415 && !i
.tm
.opcode_modifier
.ignoresize
))
6417 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
6423 /* Change the opcode based on the operand size given by i.suffix. */
6426 /* Size floating point instruction. */
6427 case LONG_MNEM_SUFFIX
:
6428 if (i
.tm
.opcode_modifier
.floatmf
)
6430 i
.tm
.base_opcode
^= 4;
6434 case WORD_MNEM_SUFFIX
:
6435 case QWORD_MNEM_SUFFIX
:
6436 /* It's not a byte, select word/dword operation. */
6437 if (i
.tm
.opcode_modifier
.w
)
6439 if (i
.tm
.opcode_modifier
.shortform
)
6440 i
.tm
.base_opcode
|= 8;
6442 i
.tm
.base_opcode
|= 1;
6445 case SHORT_MNEM_SUFFIX
:
6446 /* Now select between word & dword operations via the operand
6447 size prefix, except for instructions that will ignore this
6449 if (i
.reg_operands
> 0
6450 && i
.types
[0].bitfield
.reg
6451 && i
.tm
.opcode_modifier
.addrprefixopreg
6452 && (i
.tm
.opcode_modifier
.immext
6453 || i
.operands
== 1))
6455 /* The address size override prefix changes the size of the
6457 if ((flag_code
== CODE_32BIT
6458 && i
.op
[0].regs
->reg_type
.bitfield
.word
)
6459 || (flag_code
!= CODE_32BIT
6460 && i
.op
[0].regs
->reg_type
.bitfield
.dword
))
6461 if (!add_prefix (ADDR_PREFIX_OPCODE
))
6464 else if (i
.suffix
!= QWORD_MNEM_SUFFIX
6465 && !i
.tm
.opcode_modifier
.ignoresize
6466 && !i
.tm
.opcode_modifier
.floatmf
6467 && !is_any_vex_encoding (&i
.tm
)
6468 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
6469 || (flag_code
== CODE_64BIT
6470 && i
.tm
.opcode_modifier
.jumpbyte
)))
6472 unsigned int prefix
= DATA_PREFIX_OPCODE
;
6474 if (i
.tm
.opcode_modifier
.jumpbyte
) /* jcxz, loop */
6475 prefix
= ADDR_PREFIX_OPCODE
;
6477 if (!add_prefix (prefix
))
6481 /* Set mode64 for an operand. */
6482 if (i
.suffix
== QWORD_MNEM_SUFFIX
6483 && flag_code
== CODE_64BIT
6484 && !i
.tm
.opcode_modifier
.norex64
6485 /* Special case for xchg %rax,%rax. It is NOP and doesn't
6487 && ! (i
.operands
== 2
6488 && i
.tm
.base_opcode
== 0x90
6489 && i
.tm
.extension_opcode
== None
6490 && i
.types
[0].bitfield
.acc
&& i
.types
[0].bitfield
.qword
6491 && i
.types
[1].bitfield
.acc
&& i
.types
[1].bitfield
.qword
))
6497 if (i
.reg_operands
!= 0
6499 && i
.tm
.opcode_modifier
.addrprefixopreg
6500 && !i
.tm
.opcode_modifier
.immext
)
6502 /* Check invalid register operand when the address size override
6503 prefix changes the size of register operands. */
6505 enum { need_word
, need_dword
, need_qword
} need
;
6507 if (flag_code
== CODE_32BIT
)
6508 need
= i
.prefix
[ADDR_PREFIX
] ? need_word
: need_dword
;
6511 if (i
.prefix
[ADDR_PREFIX
])
6514 need
= flag_code
== CODE_64BIT
? need_qword
: need_word
;
6517 for (op
= 0; op
< i
.operands
; op
++)
6518 if (i
.types
[op
].bitfield
.reg
6519 && ((need
== need_word
6520 && !i
.op
[op
].regs
->reg_type
.bitfield
.word
)
6521 || (need
== need_dword
6522 && !i
.op
[op
].regs
->reg_type
.bitfield
.dword
)
6523 || (need
== need_qword
6524 && !i
.op
[op
].regs
->reg_type
.bitfield
.qword
)))
6526 as_bad (_("invalid register operand size for `%s'"),
6536 check_byte_reg (void)
6540 for (op
= i
.operands
; --op
>= 0;)
6542 /* Skip non-register operands. */
6543 if (!i
.types
[op
].bitfield
.reg
)
6546 /* If this is an eight bit register, it's OK. If it's the 16 or
6547 32 bit version of an eight bit register, we will just use the
6548 low portion, and that's OK too. */
6549 if (i
.types
[op
].bitfield
.byte
)
6552 /* I/O port address operands are OK too. */
6553 if (i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
6556 /* crc32 doesn't generate this warning. */
6557 if (i
.tm
.base_opcode
== 0xf20f38f0)
6560 if ((i
.types
[op
].bitfield
.word
6561 || i
.types
[op
].bitfield
.dword
6562 || i
.types
[op
].bitfield
.qword
)
6563 && i
.op
[op
].regs
->reg_num
< 4
6564 /* Prohibit these changes in 64bit mode, since the lowering
6565 would be more complicated. */
6566 && flag_code
!= CODE_64BIT
)
6568 #if REGISTER_WARNINGS
6569 if (!quiet_warnings
)
6570 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6572 (i
.op
[op
].regs
+ (i
.types
[op
].bitfield
.word
6573 ? REGNAM_AL
- REGNAM_AX
6574 : REGNAM_AL
- REGNAM_EAX
))->reg_name
,
6576 i
.op
[op
].regs
->reg_name
,
6581 /* Any other register is bad. */
6582 if (i
.types
[op
].bitfield
.reg
6583 || i
.types
[op
].bitfield
.regmmx
6584 || i
.types
[op
].bitfield
.regsimd
6585 || i
.types
[op
].bitfield
.sreg
6586 || i
.types
[op
].bitfield
.control
6587 || i
.types
[op
].bitfield
.debug
6588 || i
.types
[op
].bitfield
.test
)
6590 as_bad (_("`%s%s' not allowed with `%s%c'"),
6592 i
.op
[op
].regs
->reg_name
,
6602 check_long_reg (void)
6606 for (op
= i
.operands
; --op
>= 0;)
6607 /* Skip non-register operands. */
6608 if (!i
.types
[op
].bitfield
.reg
)
6610 /* Reject eight bit registers, except where the template requires
6611 them. (eg. movzb) */
6612 else if (i
.types
[op
].bitfield
.byte
6613 && (i
.tm
.operand_types
[op
].bitfield
.reg
6614 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6615 && (i
.tm
.operand_types
[op
].bitfield
.word
6616 || i
.tm
.operand_types
[op
].bitfield
.dword
))
6618 as_bad (_("`%s%s' not allowed with `%s%c'"),
6620 i
.op
[op
].regs
->reg_name
,
6625 /* Warn if the e prefix on a general reg is missing. */
6626 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
6627 && i
.types
[op
].bitfield
.word
6628 && (i
.tm
.operand_types
[op
].bitfield
.reg
6629 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6630 && i
.tm
.operand_types
[op
].bitfield
.dword
)
6632 /* Prohibit these changes in the 64bit mode, since the
6633 lowering is more complicated. */
6634 if (flag_code
== CODE_64BIT
)
6636 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6637 register_prefix
, i
.op
[op
].regs
->reg_name
,
6641 #if REGISTER_WARNINGS
6642 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6644 (i
.op
[op
].regs
+ REGNAM_EAX
- REGNAM_AX
)->reg_name
,
6645 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
6648 /* Warn if the r prefix on a general reg is present. */
6649 else if (i
.types
[op
].bitfield
.qword
6650 && (i
.tm
.operand_types
[op
].bitfield
.reg
6651 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6652 && i
.tm
.operand_types
[op
].bitfield
.dword
)
6655 && i
.tm
.opcode_modifier
.toqword
6656 && !i
.types
[0].bitfield
.regsimd
)
6658 /* Convert to QWORD. We want REX byte. */
6659 i
.suffix
= QWORD_MNEM_SUFFIX
;
6663 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6664 register_prefix
, i
.op
[op
].regs
->reg_name
,
6673 check_qword_reg (void)
6677 for (op
= i
.operands
; --op
>= 0; )
6678 /* Skip non-register operands. */
6679 if (!i
.types
[op
].bitfield
.reg
)
6681 /* Reject eight bit registers, except where the template requires
6682 them. (eg. movzb) */
6683 else if (i
.types
[op
].bitfield
.byte
6684 && (i
.tm
.operand_types
[op
].bitfield
.reg
6685 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6686 && (i
.tm
.operand_types
[op
].bitfield
.word
6687 || i
.tm
.operand_types
[op
].bitfield
.dword
))
6689 as_bad (_("`%s%s' not allowed with `%s%c'"),
6691 i
.op
[op
].regs
->reg_name
,
6696 /* Warn if the r prefix on a general reg is missing. */
6697 else if ((i
.types
[op
].bitfield
.word
6698 || i
.types
[op
].bitfield
.dword
)
6699 && (i
.tm
.operand_types
[op
].bitfield
.reg
6700 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6701 && i
.tm
.operand_types
[op
].bitfield
.qword
)
6703 /* Prohibit these changes in the 64bit mode, since the
6704 lowering is more complicated. */
6706 && i
.tm
.opcode_modifier
.todword
6707 && !i
.types
[0].bitfield
.regsimd
)
6709 /* Convert to DWORD. We don't want REX byte. */
6710 i
.suffix
= LONG_MNEM_SUFFIX
;
6714 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6715 register_prefix
, i
.op
[op
].regs
->reg_name
,
6724 check_word_reg (void)
6727 for (op
= i
.operands
; --op
>= 0;)
6728 /* Skip non-register operands. */
6729 if (!i
.types
[op
].bitfield
.reg
)
6731 /* Reject eight bit registers, except where the template requires
6732 them. (eg. movzb) */
6733 else if (i
.types
[op
].bitfield
.byte
6734 && (i
.tm
.operand_types
[op
].bitfield
.reg
6735 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6736 && (i
.tm
.operand_types
[op
].bitfield
.word
6737 || i
.tm
.operand_types
[op
].bitfield
.dword
))
6739 as_bad (_("`%s%s' not allowed with `%s%c'"),
6741 i
.op
[op
].regs
->reg_name
,
6746 /* Warn if the e or r prefix on a general reg is present. */
6747 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
6748 && (i
.types
[op
].bitfield
.dword
6749 || i
.types
[op
].bitfield
.qword
)
6750 && (i
.tm
.operand_types
[op
].bitfield
.reg
6751 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6752 && i
.tm
.operand_types
[op
].bitfield
.word
)
6754 /* Prohibit these changes in the 64bit mode, since the
6755 lowering is more complicated. */
6756 if (flag_code
== CODE_64BIT
)
6758 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6759 register_prefix
, i
.op
[op
].regs
->reg_name
,
6763 #if REGISTER_WARNINGS
6764 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6766 (i
.op
[op
].regs
+ REGNAM_AX
- REGNAM_EAX
)->reg_name
,
6767 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
6774 update_imm (unsigned int j
)
6776 i386_operand_type overlap
= i
.types
[j
];
6777 if ((overlap
.bitfield
.imm8
6778 || overlap
.bitfield
.imm8s
6779 || overlap
.bitfield
.imm16
6780 || overlap
.bitfield
.imm32
6781 || overlap
.bitfield
.imm32s
6782 || overlap
.bitfield
.imm64
)
6783 && !operand_type_equal (&overlap
, &imm8
)
6784 && !operand_type_equal (&overlap
, &imm8s
)
6785 && !operand_type_equal (&overlap
, &imm16
)
6786 && !operand_type_equal (&overlap
, &imm32
)
6787 && !operand_type_equal (&overlap
, &imm32s
)
6788 && !operand_type_equal (&overlap
, &imm64
))
6792 i386_operand_type temp
;
6794 operand_type_set (&temp
, 0);
6795 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
6797 temp
.bitfield
.imm8
= overlap
.bitfield
.imm8
;
6798 temp
.bitfield
.imm8s
= overlap
.bitfield
.imm8s
;
6800 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
6801 temp
.bitfield
.imm16
= overlap
.bitfield
.imm16
;
6802 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
6804 temp
.bitfield
.imm64
= overlap
.bitfield
.imm64
;
6805 temp
.bitfield
.imm32s
= overlap
.bitfield
.imm32s
;
6808 temp
.bitfield
.imm32
= overlap
.bitfield
.imm32
;
6811 else if (operand_type_equal (&overlap
, &imm16_32_32s
)
6812 || operand_type_equal (&overlap
, &imm16_32
)
6813 || operand_type_equal (&overlap
, &imm16_32s
))
6815 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
6820 if (!operand_type_equal (&overlap
, &imm8
)
6821 && !operand_type_equal (&overlap
, &imm8s
)
6822 && !operand_type_equal (&overlap
, &imm16
)
6823 && !operand_type_equal (&overlap
, &imm32
)
6824 && !operand_type_equal (&overlap
, &imm32s
)
6825 && !operand_type_equal (&overlap
, &imm64
))
6827 as_bad (_("no instruction mnemonic suffix given; "
6828 "can't determine immediate size"));
6832 i
.types
[j
] = overlap
;
6842 /* Update the first 2 immediate operands. */
6843 n
= i
.operands
> 2 ? 2 : i
.operands
;
6846 for (j
= 0; j
< n
; j
++)
6847 if (update_imm (j
) == 0)
6850 /* The 3rd operand can't be immediate operand. */
6851 gas_assert (operand_type_check (i
.types
[2], imm
) == 0);
6858 process_operands (void)
6860 /* Default segment register this instruction will use for memory
6861 accesses. 0 means unknown. This is only for optimizing out
6862 unnecessary segment overrides. */
6863 const seg_entry
*default_seg
= 0;
6865 if (i
.tm
.opcode_modifier
.sse2avx
&& i
.tm
.opcode_modifier
.vexvvvv
)
6867 unsigned int dupl
= i
.operands
;
6868 unsigned int dest
= dupl
- 1;
6871 /* The destination must be an xmm register. */
6872 gas_assert (i
.reg_operands
6873 && MAX_OPERANDS
> dupl
6874 && operand_type_equal (&i
.types
[dest
], ®xmm
));
6876 if (i
.tm
.operand_types
[0].bitfield
.acc
6877 && i
.tm
.operand_types
[0].bitfield
.xmmword
)
6879 if (i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
)
6881 /* Keep xmm0 for instructions with VEX prefix and 3
6883 i
.tm
.operand_types
[0].bitfield
.acc
= 0;
6884 i
.tm
.operand_types
[0].bitfield
.regsimd
= 1;
6889 /* We remove the first xmm0 and keep the number of
6890 operands unchanged, which in fact duplicates the
6892 for (j
= 1; j
< i
.operands
; j
++)
6894 i
.op
[j
- 1] = i
.op
[j
];
6895 i
.types
[j
- 1] = i
.types
[j
];
6896 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
6897 i
.flags
[j
- 1] = i
.flags
[j
];
6901 else if (i
.tm
.opcode_modifier
.implicit1stxmm0
)
6903 gas_assert ((MAX_OPERANDS
- 1) > dupl
6904 && (i
.tm
.opcode_modifier
.vexsources
6907 /* Add the implicit xmm0 for instructions with VEX prefix
6909 for (j
= i
.operands
; j
> 0; j
--)
6911 i
.op
[j
] = i
.op
[j
- 1];
6912 i
.types
[j
] = i
.types
[j
- 1];
6913 i
.tm
.operand_types
[j
] = i
.tm
.operand_types
[j
- 1];
6914 i
.flags
[j
] = i
.flags
[j
- 1];
6917 = (const reg_entry
*) hash_find (reg_hash
, "xmm0");
6918 i
.types
[0] = regxmm
;
6919 i
.tm
.operand_types
[0] = regxmm
;
6922 i
.reg_operands
+= 2;
6927 i
.op
[dupl
] = i
.op
[dest
];
6928 i
.types
[dupl
] = i
.types
[dest
];
6929 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
6930 i
.flags
[dupl
] = i
.flags
[dest
];
6939 i
.op
[dupl
] = i
.op
[dest
];
6940 i
.types
[dupl
] = i
.types
[dest
];
6941 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
6942 i
.flags
[dupl
] = i
.flags
[dest
];
6945 if (i
.tm
.opcode_modifier
.immext
)
6948 else if (i
.tm
.operand_types
[0].bitfield
.acc
6949 && i
.tm
.operand_types
[0].bitfield
.xmmword
)
6953 for (j
= 1; j
< i
.operands
; j
++)
6955 i
.op
[j
- 1] = i
.op
[j
];
6956 i
.types
[j
- 1] = i
.types
[j
];
6958 /* We need to adjust fields in i.tm since they are used by
6959 build_modrm_byte. */
6960 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
6962 i
.flags
[j
- 1] = i
.flags
[j
];
6969 else if (i
.tm
.opcode_modifier
.implicitquadgroup
)
6971 unsigned int regnum
, first_reg_in_group
, last_reg_in_group
;
6973 /* The second operand must be {x,y,z}mmN, where N is a multiple of 4. */
6974 gas_assert (i
.operands
>= 2 && i
.types
[1].bitfield
.regsimd
);
6975 regnum
= register_number (i
.op
[1].regs
);
6976 first_reg_in_group
= regnum
& ~3;
6977 last_reg_in_group
= first_reg_in_group
+ 3;
6978 if (regnum
!= first_reg_in_group
)
6979 as_warn (_("source register `%s%s' implicitly denotes"
6980 " `%s%.3s%u' to `%s%.3s%u' source group in `%s'"),
6981 register_prefix
, i
.op
[1].regs
->reg_name
,
6982 register_prefix
, i
.op
[1].regs
->reg_name
, first_reg_in_group
,
6983 register_prefix
, i
.op
[1].regs
->reg_name
, last_reg_in_group
,
6986 else if (i
.tm
.opcode_modifier
.regkludge
)
6988 /* The imul $imm, %reg instruction is converted into
6989 imul $imm, %reg, %reg, and the clr %reg instruction
6990 is converted into xor %reg, %reg. */
6992 unsigned int first_reg_op
;
6994 if (operand_type_check (i
.types
[0], reg
))
6998 /* Pretend we saw the extra register operand. */
6999 gas_assert (i
.reg_operands
== 1
7000 && i
.op
[first_reg_op
+ 1].regs
== 0);
7001 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
7002 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
7007 if (i
.tm
.opcode_modifier
.shortform
)
7009 if (i
.types
[0].bitfield
.sreg
)
7011 if (flag_code
!= CODE_64BIT
7012 ? i
.tm
.base_opcode
== POP_SEG_SHORT
7013 && i
.op
[0].regs
->reg_num
== 1
7014 : (i
.tm
.base_opcode
| 1) == POP_SEG386_SHORT
7015 && i
.op
[0].regs
->reg_num
< 4)
7017 as_bad (_("you can't `%s %s%s'"),
7018 i
.tm
.name
, register_prefix
, i
.op
[0].regs
->reg_name
);
7021 if ( i
.op
[0].regs
->reg_num
> 3 && i
.tm
.opcode_length
== 1 )
7023 i
.tm
.base_opcode
^= POP_SEG_SHORT
^ POP_SEG386_SHORT
;
7024 i
.tm
.opcode_length
= 2;
7026 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
7030 /* The register or float register operand is in operand
7034 if ((i
.types
[0].bitfield
.reg
&& i
.types
[0].bitfield
.tbyte
)
7035 || operand_type_check (i
.types
[0], reg
))
7039 /* Register goes in low 3 bits of opcode. */
7040 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
7041 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
7043 if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
7045 /* Warn about some common errors, but press on regardless.
7046 The first case can be generated by gcc (<= 2.8.1). */
7047 if (i
.operands
== 2)
7049 /* Reversed arguments on faddp, fsubp, etc. */
7050 as_warn (_("translating to `%s %s%s,%s%s'"), i
.tm
.name
,
7051 register_prefix
, i
.op
[!intel_syntax
].regs
->reg_name
,
7052 register_prefix
, i
.op
[intel_syntax
].regs
->reg_name
);
7056 /* Extraneous `l' suffix on fp insn. */
7057 as_warn (_("translating to `%s %s%s'"), i
.tm
.name
,
7058 register_prefix
, i
.op
[0].regs
->reg_name
);
7063 else if (i
.tm
.opcode_modifier
.modrm
)
7065 /* The opcode is completed (modulo i.tm.extension_opcode which
7066 must be put into the modrm byte). Now, we make the modrm and
7067 index base bytes based on all the info we've collected. */
7069 default_seg
= build_modrm_byte ();
7071 else if ((i
.tm
.base_opcode
& ~0x3) == MOV_AX_DISP32
)
7075 else if (i
.tm
.opcode_modifier
.isstring
)
7077 /* For the string instructions that allow a segment override
7078 on one of their operands, the default segment is ds. */
7082 if (i
.tm
.base_opcode
== 0x8d /* lea */
7085 as_warn (_("segment override on `%s' is ineffectual"), i
.tm
.name
);
7087 /* If a segment was explicitly specified, and the specified segment
7088 is not the default, use an opcode prefix to select it. If we
7089 never figured out what the default segment is, then default_seg
7090 will be zero at this point, and the specified segment prefix will
7092 if ((i
.seg
[0]) && (i
.seg
[0] != default_seg
))
7094 if (!add_prefix (i
.seg
[0]->seg_prefix
))
7100 static const seg_entry
*
7101 build_modrm_byte (void)
7103 const seg_entry
*default_seg
= 0;
7104 unsigned int source
, dest
;
7107 vex_3_sources
= i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
;
7110 unsigned int nds
, reg_slot
;
7113 dest
= i
.operands
- 1;
7116 /* There are 2 kinds of instructions:
7117 1. 5 operands: 4 register operands or 3 register operands
7118 plus 1 memory operand plus one Imm4 operand, VexXDS, and
7119 VexW0 or VexW1. The destination must be either XMM, YMM or
7121 2. 4 operands: 4 register operands or 3 register operands
7122 plus 1 memory operand, with VexXDS. */
7123 gas_assert ((i
.reg_operands
== 4
7124 || (i
.reg_operands
== 3 && i
.mem_operands
== 1))
7125 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
7126 && i
.tm
.opcode_modifier
.vexw
7127 && i
.tm
.operand_types
[dest
].bitfield
.regsimd
);
7129 /* If VexW1 is set, the first non-immediate operand is the source and
7130 the second non-immediate one is encoded in the immediate operand. */
7131 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
7133 source
= i
.imm_operands
;
7134 reg_slot
= i
.imm_operands
+ 1;
7138 source
= i
.imm_operands
+ 1;
7139 reg_slot
= i
.imm_operands
;
7142 if (i
.imm_operands
== 0)
7144 /* When there is no immediate operand, generate an 8bit
7145 immediate operand to encode the first operand. */
7146 exp
= &im_expressions
[i
.imm_operands
++];
7147 i
.op
[i
.operands
].imms
= exp
;
7148 i
.types
[i
.operands
] = imm8
;
7151 gas_assert (i
.tm
.operand_types
[reg_slot
].bitfield
.regsimd
);
7152 exp
->X_op
= O_constant
;
7153 exp
->X_add_number
= register_number (i
.op
[reg_slot
].regs
) << 4;
7154 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
7158 gas_assert (i
.imm_operands
== 1);
7159 gas_assert (fits_in_imm4 (i
.op
[0].imms
->X_add_number
));
7160 gas_assert (!i
.tm
.opcode_modifier
.immext
);
7162 /* Turn on Imm8 again so that output_imm will generate it. */
7163 i
.types
[0].bitfield
.imm8
= 1;
7165 gas_assert (i
.tm
.operand_types
[reg_slot
].bitfield
.regsimd
);
7166 i
.op
[0].imms
->X_add_number
7167 |= register_number (i
.op
[reg_slot
].regs
) << 4;
7168 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
7171 gas_assert (i
.tm
.operand_types
[nds
].bitfield
.regsimd
);
7172 i
.vex
.register_specifier
= i
.op
[nds
].regs
;
7177 /* i.reg_operands MUST be the number of real register operands;
7178 implicit registers do not count. If there are 3 register
7179 operands, it must be a instruction with VexNDS. For a
7180 instruction with VexNDD, the destination register is encoded
7181 in VEX prefix. If there are 4 register operands, it must be
7182 a instruction with VEX prefix and 3 sources. */
7183 if (i
.mem_operands
== 0
7184 && ((i
.reg_operands
== 2
7185 && i
.tm
.opcode_modifier
.vexvvvv
<= VEXXDS
)
7186 || (i
.reg_operands
== 3
7187 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
7188 || (i
.reg_operands
== 4 && vex_3_sources
)))
7196 /* When there are 3 operands, one of them may be immediate,
7197 which may be the first or the last operand. Otherwise,
7198 the first operand must be shift count register (cl) or it
7199 is an instruction with VexNDS. */
7200 gas_assert (i
.imm_operands
== 1
7201 || (i
.imm_operands
== 0
7202 && (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
7203 || i
.types
[0].bitfield
.shiftcount
)));
7204 if (operand_type_check (i
.types
[0], imm
)
7205 || i
.types
[0].bitfield
.shiftcount
)
7211 /* When there are 4 operands, the first two must be 8bit
7212 immediate operands. The source operand will be the 3rd
7215 For instructions with VexNDS, if the first operand
7216 an imm8, the source operand is the 2nd one. If the last
7217 operand is imm8, the source operand is the first one. */
7218 gas_assert ((i
.imm_operands
== 2
7219 && i
.types
[0].bitfield
.imm8
7220 && i
.types
[1].bitfield
.imm8
)
7221 || (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
7222 && i
.imm_operands
== 1
7223 && (i
.types
[0].bitfield
.imm8
7224 || i
.types
[i
.operands
- 1].bitfield
.imm8
7226 if (i
.imm_operands
== 2)
7230 if (i
.types
[0].bitfield
.imm8
)
7237 if (is_evex_encoding (&i
.tm
))
7239 /* For EVEX instructions, when there are 5 operands, the
7240 first one must be immediate operand. If the second one
7241 is immediate operand, the source operand is the 3th
7242 one. If the last one is immediate operand, the source
7243 operand is the 2nd one. */
7244 gas_assert (i
.imm_operands
== 2
7245 && i
.tm
.opcode_modifier
.sae
7246 && operand_type_check (i
.types
[0], imm
));
7247 if (operand_type_check (i
.types
[1], imm
))
7249 else if (operand_type_check (i
.types
[4], imm
))
7263 /* RC/SAE operand could be between DEST and SRC. That happens
7264 when one operand is GPR and the other one is XMM/YMM/ZMM
7266 if (i
.rounding
&& i
.rounding
->operand
== (int) dest
)
7269 if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
7271 /* For instructions with VexNDS, the register-only source
7272 operand must be a 32/64bit integer, XMM, YMM, ZMM, or mask
7273 register. It is encoded in VEX prefix. */
7275 i386_operand_type op
;
7278 /* Check register-only source operand when two source
7279 operands are swapped. */
7280 if (!i
.tm
.operand_types
[source
].bitfield
.baseindex
7281 && i
.tm
.operand_types
[dest
].bitfield
.baseindex
)
7289 op
= i
.tm
.operand_types
[vvvv
];
7290 if ((dest
+ 1) >= i
.operands
7291 || ((!op
.bitfield
.reg
7292 || (!op
.bitfield
.dword
&& !op
.bitfield
.qword
))
7293 && !op
.bitfield
.regsimd
7294 && !operand_type_equal (&op
, ®mask
)))
7296 i
.vex
.register_specifier
= i
.op
[vvvv
].regs
;
7302 /* One of the register operands will be encoded in the i.rm.reg
7303 field, the other in the combined i.rm.mode and i.rm.regmem
7304 fields. If no form of this instruction supports a memory
7305 destination operand, then we assume the source operand may
7306 sometimes be a memory operand and so we need to store the
7307 destination in the i.rm.reg field. */
7308 if (!i
.tm
.opcode_modifier
.regmem
7309 && operand_type_check (i
.tm
.operand_types
[dest
], anymem
) == 0)
7311 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
7312 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
7313 if (i
.op
[dest
].regs
->reg_type
.bitfield
.regmmx
7314 || i
.op
[source
].regs
->reg_type
.bitfield
.regmmx
)
7315 i
.has_regmmx
= TRUE
;
7316 else if (i
.op
[dest
].regs
->reg_type
.bitfield
.regsimd
7317 || i
.op
[source
].regs
->reg_type
.bitfield
.regsimd
)
7319 if (i
.types
[dest
].bitfield
.zmmword
7320 || i
.types
[source
].bitfield
.zmmword
)
7321 i
.has_regzmm
= TRUE
;
7322 else if (i
.types
[dest
].bitfield
.ymmword
7323 || i
.types
[source
].bitfield
.ymmword
)
7324 i
.has_regymm
= TRUE
;
7326 i
.has_regxmm
= TRUE
;
7328 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
7330 if ((i
.op
[dest
].regs
->reg_flags
& RegVRex
) != 0)
7332 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
7334 if ((i
.op
[source
].regs
->reg_flags
& RegVRex
) != 0)
7339 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
7340 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
7341 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
7343 if ((i
.op
[dest
].regs
->reg_flags
& RegVRex
) != 0)
7345 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
7347 if ((i
.op
[source
].regs
->reg_flags
& RegVRex
) != 0)
7350 if (flag_code
!= CODE_64BIT
&& (i
.rex
& REX_R
))
7352 if (!i
.types
[!i
.tm
.opcode_modifier
.regmem
].bitfield
.control
)
7355 add_prefix (LOCK_PREFIX_OPCODE
);
7359 { /* If it's not 2 reg operands... */
7364 unsigned int fake_zero_displacement
= 0;
7367 for (op
= 0; op
< i
.operands
; op
++)
7368 if (i
.flags
[op
] & Operand_Mem
)
7370 gas_assert (op
< i
.operands
);
7372 if (i
.tm
.opcode_modifier
.vecsib
)
7374 if (i
.index_reg
->reg_num
== RegIZ
)
7377 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
7380 i
.sib
.base
= NO_BASE_REGISTER
;
7381 i
.sib
.scale
= i
.log2_scale_factor
;
7382 i
.types
[op
].bitfield
.disp8
= 0;
7383 i
.types
[op
].bitfield
.disp16
= 0;
7384 i
.types
[op
].bitfield
.disp64
= 0;
7385 if (flag_code
!= CODE_64BIT
|| i
.prefix
[ADDR_PREFIX
])
7387 /* Must be 32 bit */
7388 i
.types
[op
].bitfield
.disp32
= 1;
7389 i
.types
[op
].bitfield
.disp32s
= 0;
7393 i
.types
[op
].bitfield
.disp32
= 0;
7394 i
.types
[op
].bitfield
.disp32s
= 1;
7397 i
.sib
.index
= i
.index_reg
->reg_num
;
7398 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
7400 if ((i
.index_reg
->reg_flags
& RegVRex
) != 0)
7406 if (i
.base_reg
== 0)
7409 if (!i
.disp_operands
)
7410 fake_zero_displacement
= 1;
7411 if (i
.index_reg
== 0)
7413 i386_operand_type newdisp
;
7415 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
7416 /* Operand is just <disp> */
7417 if (flag_code
== CODE_64BIT
)
7419 /* 64bit mode overwrites the 32bit absolute
7420 addressing by RIP relative addressing and
7421 absolute addressing is encoded by one of the
7422 redundant SIB forms. */
7423 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
7424 i
.sib
.base
= NO_BASE_REGISTER
;
7425 i
.sib
.index
= NO_INDEX_REGISTER
;
7426 newdisp
= (!i
.prefix
[ADDR_PREFIX
] ? disp32s
: disp32
);
7428 else if ((flag_code
== CODE_16BIT
)
7429 ^ (i
.prefix
[ADDR_PREFIX
] != 0))
7431 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
7436 i
.rm
.regmem
= NO_BASE_REGISTER
;
7439 i
.types
[op
] = operand_type_and_not (i
.types
[op
], anydisp
);
7440 i
.types
[op
] = operand_type_or (i
.types
[op
], newdisp
);
7442 else if (!i
.tm
.opcode_modifier
.vecsib
)
7444 /* !i.base_reg && i.index_reg */
7445 if (i
.index_reg
->reg_num
== RegIZ
)
7446 i
.sib
.index
= NO_INDEX_REGISTER
;
7448 i
.sib
.index
= i
.index_reg
->reg_num
;
7449 i
.sib
.base
= NO_BASE_REGISTER
;
7450 i
.sib
.scale
= i
.log2_scale_factor
;
7451 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
7452 i
.types
[op
].bitfield
.disp8
= 0;
7453 i
.types
[op
].bitfield
.disp16
= 0;
7454 i
.types
[op
].bitfield
.disp64
= 0;
7455 if (flag_code
!= CODE_64BIT
|| i
.prefix
[ADDR_PREFIX
])
7457 /* Must be 32 bit */
7458 i
.types
[op
].bitfield
.disp32
= 1;
7459 i
.types
[op
].bitfield
.disp32s
= 0;
7463 i
.types
[op
].bitfield
.disp32
= 0;
7464 i
.types
[op
].bitfield
.disp32s
= 1;
7466 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
7470 /* RIP addressing for 64bit mode. */
7471 else if (i
.base_reg
->reg_num
== RegIP
)
7473 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
7474 i
.rm
.regmem
= NO_BASE_REGISTER
;
7475 i
.types
[op
].bitfield
.disp8
= 0;
7476 i
.types
[op
].bitfield
.disp16
= 0;
7477 i
.types
[op
].bitfield
.disp32
= 0;
7478 i
.types
[op
].bitfield
.disp32s
= 1;
7479 i
.types
[op
].bitfield
.disp64
= 0;
7480 i
.flags
[op
] |= Operand_PCrel
;
7481 if (! i
.disp_operands
)
7482 fake_zero_displacement
= 1;
7484 else if (i
.base_reg
->reg_type
.bitfield
.word
)
7486 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
7487 switch (i
.base_reg
->reg_num
)
7490 if (i
.index_reg
== 0)
7492 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
7493 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
7497 if (i
.index_reg
== 0)
7500 if (operand_type_check (i
.types
[op
], disp
) == 0)
7502 /* fake (%bp) into 0(%bp) */
7503 i
.types
[op
].bitfield
.disp8
= 1;
7504 fake_zero_displacement
= 1;
7507 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
7508 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
7510 default: /* (%si) -> 4 or (%di) -> 5 */
7511 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
7513 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
7515 else /* i.base_reg and 32/64 bit mode */
7517 if (flag_code
== CODE_64BIT
7518 && operand_type_check (i
.types
[op
], disp
))
7520 i
.types
[op
].bitfield
.disp16
= 0;
7521 i
.types
[op
].bitfield
.disp64
= 0;
7522 if (i
.prefix
[ADDR_PREFIX
] == 0)
7524 i
.types
[op
].bitfield
.disp32
= 0;
7525 i
.types
[op
].bitfield
.disp32s
= 1;
7529 i
.types
[op
].bitfield
.disp32
= 1;
7530 i
.types
[op
].bitfield
.disp32s
= 0;
7534 if (!i
.tm
.opcode_modifier
.vecsib
)
7535 i
.rm
.regmem
= i
.base_reg
->reg_num
;
7536 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
7538 i
.sib
.base
= i
.base_reg
->reg_num
;
7539 /* x86-64 ignores REX prefix bit here to avoid decoder
7541 if (!(i
.base_reg
->reg_flags
& RegRex
)
7542 && (i
.base_reg
->reg_num
== EBP_REG_NUM
7543 || i
.base_reg
->reg_num
== ESP_REG_NUM
))
7545 if (i
.base_reg
->reg_num
== 5 && i
.disp_operands
== 0)
7547 fake_zero_displacement
= 1;
7548 i
.types
[op
].bitfield
.disp8
= 1;
7550 i
.sib
.scale
= i
.log2_scale_factor
;
7551 if (i
.index_reg
== 0)
7553 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
7554 /* <disp>(%esp) becomes two byte modrm with no index
7555 register. We've already stored the code for esp
7556 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
7557 Any base register besides %esp will not use the
7558 extra modrm byte. */
7559 i
.sib
.index
= NO_INDEX_REGISTER
;
7561 else if (!i
.tm
.opcode_modifier
.vecsib
)
7563 if (i
.index_reg
->reg_num
== RegIZ
)
7564 i
.sib
.index
= NO_INDEX_REGISTER
;
7566 i
.sib
.index
= i
.index_reg
->reg_num
;
7567 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
7568 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
7573 && (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
7574 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
))
7578 if (!fake_zero_displacement
7582 fake_zero_displacement
= 1;
7583 if (i
.disp_encoding
== disp_encoding_8bit
)
7584 i
.types
[op
].bitfield
.disp8
= 1;
7586 i
.types
[op
].bitfield
.disp32
= 1;
7588 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
7592 if (fake_zero_displacement
)
7594 /* Fakes a zero displacement assuming that i.types[op]
7595 holds the correct displacement size. */
7598 gas_assert (i
.op
[op
].disps
== 0);
7599 exp
= &disp_expressions
[i
.disp_operands
++];
7600 i
.op
[op
].disps
= exp
;
7601 exp
->X_op
= O_constant
;
7602 exp
->X_add_number
= 0;
7603 exp
->X_add_symbol
= (symbolS
*) 0;
7604 exp
->X_op_symbol
= (symbolS
*) 0;
7612 if (i
.tm
.opcode_modifier
.vexsources
== XOP2SOURCES
)
7614 if (operand_type_check (i
.types
[0], imm
))
7615 i
.vex
.register_specifier
= NULL
;
7618 /* VEX.vvvv encodes one of the sources when the first
7619 operand is not an immediate. */
7620 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
7621 i
.vex
.register_specifier
= i
.op
[0].regs
;
7623 i
.vex
.register_specifier
= i
.op
[1].regs
;
7626 /* Destination is a XMM register encoded in the ModRM.reg
7628 i
.rm
.reg
= i
.op
[2].regs
->reg_num
;
7629 if ((i
.op
[2].regs
->reg_flags
& RegRex
) != 0)
7632 /* ModRM.rm and VEX.B encodes the other source. */
7633 if (!i
.mem_operands
)
7637 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
7638 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
7640 i
.rm
.regmem
= i
.op
[0].regs
->reg_num
;
7642 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
7646 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXLWP
)
7648 i
.vex
.register_specifier
= i
.op
[2].regs
;
7649 if (!i
.mem_operands
)
7652 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
7653 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
7657 /* Fill in i.rm.reg or i.rm.regmem field with register operand
7658 (if any) based on i.tm.extension_opcode. Again, we must be
7659 careful to make sure that segment/control/debug/test/MMX
7660 registers are coded into the i.rm.reg field. */
7661 else if (i
.reg_operands
)
7664 unsigned int vex_reg
= ~0;
7666 for (op
= 0; op
< i
.operands
; op
++)
7668 if (i
.types
[op
].bitfield
.reg
7669 || i
.types
[op
].bitfield
.regbnd
7670 || i
.types
[op
].bitfield
.regmask
7671 || i
.types
[op
].bitfield
.sreg
7672 || i
.types
[op
].bitfield
.control
7673 || i
.types
[op
].bitfield
.debug
7674 || i
.types
[op
].bitfield
.test
)
7676 if (i
.types
[op
].bitfield
.regsimd
)
7678 if (i
.types
[op
].bitfield
.zmmword
)
7679 i
.has_regzmm
= TRUE
;
7680 else if (i
.types
[op
].bitfield
.ymmword
)
7681 i
.has_regymm
= TRUE
;
7683 i
.has_regxmm
= TRUE
;
7686 if (i
.types
[op
].bitfield
.regmmx
)
7688 i
.has_regmmx
= TRUE
;
7695 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
7697 /* For instructions with VexNDS, the register-only
7698 source operand is encoded in VEX prefix. */
7699 gas_assert (mem
!= (unsigned int) ~0);
7704 gas_assert (op
< i
.operands
);
7708 /* Check register-only source operand when two source
7709 operands are swapped. */
7710 if (!i
.tm
.operand_types
[op
].bitfield
.baseindex
7711 && i
.tm
.operand_types
[op
+ 1].bitfield
.baseindex
)
7715 gas_assert (mem
== (vex_reg
+ 1)
7716 && op
< i
.operands
);
7721 gas_assert (vex_reg
< i
.operands
);
7725 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXNDD
)
7727 /* For instructions with VexNDD, the register destination
7728 is encoded in VEX prefix. */
7729 if (i
.mem_operands
== 0)
7731 /* There is no memory operand. */
7732 gas_assert ((op
+ 2) == i
.operands
);
7737 /* There are only 2 non-immediate operands. */
7738 gas_assert (op
< i
.imm_operands
+ 2
7739 && i
.operands
== i
.imm_operands
+ 2);
7740 vex_reg
= i
.imm_operands
+ 1;
7744 gas_assert (op
< i
.operands
);
7746 if (vex_reg
!= (unsigned int) ~0)
7748 i386_operand_type
*type
= &i
.tm
.operand_types
[vex_reg
];
7750 if ((!type
->bitfield
.reg
7751 || (!type
->bitfield
.dword
&& !type
->bitfield
.qword
))
7752 && !type
->bitfield
.regsimd
7753 && !operand_type_equal (type
, ®mask
))
7756 i
.vex
.register_specifier
= i
.op
[vex_reg
].regs
;
7759 /* Don't set OP operand twice. */
7762 /* If there is an extension opcode to put here, the
7763 register number must be put into the regmem field. */
7764 if (i
.tm
.extension_opcode
!= None
)
7766 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
7767 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
7769 if ((i
.op
[op
].regs
->reg_flags
& RegVRex
) != 0)
7774 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
7775 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
7777 if ((i
.op
[op
].regs
->reg_flags
& RegVRex
) != 0)
7782 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
7783 must set it to 3 to indicate this is a register operand
7784 in the regmem field. */
7785 if (!i
.mem_operands
)
7789 /* Fill in i.rm.reg field with extension opcode (if any). */
7790 if (i
.tm
.extension_opcode
!= None
)
7791 i
.rm
.reg
= i
.tm
.extension_opcode
;
7797 output_branch (void)
7803 relax_substateT subtype
;
7807 code16
= flag_code
== CODE_16BIT
? CODE16
: 0;
7808 size
= i
.disp_encoding
== disp_encoding_32bit
? BIG
: SMALL
;
7811 if (i
.prefix
[DATA_PREFIX
] != 0)
7817 /* Pentium4 branch hints. */
7818 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
7819 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
7824 if (i
.prefix
[REX_PREFIX
] != 0)
7830 /* BND prefixed jump. */
7831 if (i
.prefix
[BND_PREFIX
] != 0)
7833 FRAG_APPEND_1_CHAR (i
.prefix
[BND_PREFIX
]);
7837 if (i
.prefixes
!= 0 && !intel_syntax
)
7838 as_warn (_("skipping prefixes on this instruction"));
7840 /* It's always a symbol; End frag & setup for relax.
7841 Make sure there is enough room in this frag for the largest
7842 instruction we may generate in md_convert_frag. This is 2
7843 bytes for the opcode and room for the prefix and largest
7845 frag_grow (prefix
+ 2 + 4);
7846 /* Prefix and 1 opcode byte go in fr_fix. */
7847 p
= frag_more (prefix
+ 1);
7848 if (i
.prefix
[DATA_PREFIX
] != 0)
7849 *p
++ = DATA_PREFIX_OPCODE
;
7850 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
7851 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
7852 *p
++ = i
.prefix
[SEG_PREFIX
];
7853 if (i
.prefix
[REX_PREFIX
] != 0)
7854 *p
++ = i
.prefix
[REX_PREFIX
];
7855 *p
= i
.tm
.base_opcode
;
7857 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
7858 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, size
);
7859 else if (cpu_arch_flags
.bitfield
.cpui386
)
7860 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, size
);
7862 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, size
);
7865 sym
= i
.op
[0].disps
->X_add_symbol
;
7866 off
= i
.op
[0].disps
->X_add_number
;
7868 if (i
.op
[0].disps
->X_op
!= O_constant
7869 && i
.op
[0].disps
->X_op
!= O_symbol
)
7871 /* Handle complex expressions. */
7872 sym
= make_expr_symbol (i
.op
[0].disps
);
7876 /* 1 possible extra opcode + 4 byte displacement go in var part.
7877 Pass reloc in fr_var. */
7878 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
7881 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7882 /* Return TRUE iff PLT32 relocation should be used for branching to
7886 need_plt32_p (symbolS
*s
)
7888 /* PLT32 relocation is ELF only. */
7893 /* Don't emit PLT32 relocation on Solaris: neither native linker nor
7894 krtld support it. */
7898 /* Since there is no need to prepare for PLT branch on x86-64, we
7899 can generate R_X86_64_PLT32, instead of R_X86_64_PC32, which can
7900 be used as a marker for 32-bit PC-relative branches. */
7904 /* Weak or undefined symbol need PLT32 relocation. */
7905 if (S_IS_WEAK (s
) || !S_IS_DEFINED (s
))
7908 /* Non-global symbol doesn't need PLT32 relocation. */
7909 if (! S_IS_EXTERNAL (s
))
7912 /* Other global symbols need PLT32 relocation. NB: Symbol with
7913 non-default visibilities are treated as normal global symbol
7914 so that PLT32 relocation can be used as a marker for 32-bit
7915 PC-relative branches. It is useful for linker relaxation. */
7926 bfd_reloc_code_real_type jump_reloc
= i
.reloc
[0];
7928 if (i
.tm
.opcode_modifier
.jumpbyte
)
7930 /* This is a loop or jecxz type instruction. */
7932 if (i
.prefix
[ADDR_PREFIX
] != 0)
7934 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
7937 /* Pentium4 branch hints. */
7938 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
7939 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
7941 FRAG_APPEND_1_CHAR (i
.prefix
[SEG_PREFIX
]);
7950 if (flag_code
== CODE_16BIT
)
7953 if (i
.prefix
[DATA_PREFIX
] != 0)
7955 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
7965 if (i
.prefix
[REX_PREFIX
] != 0)
7967 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
7971 /* BND prefixed jump. */
7972 if (i
.prefix
[BND_PREFIX
] != 0)
7974 FRAG_APPEND_1_CHAR (i
.prefix
[BND_PREFIX
]);
7978 if (i
.prefixes
!= 0 && !intel_syntax
)
7979 as_warn (_("skipping prefixes on this instruction"));
7981 p
= frag_more (i
.tm
.opcode_length
+ size
);
7982 switch (i
.tm
.opcode_length
)
7985 *p
++ = i
.tm
.base_opcode
>> 8;
7988 *p
++ = i
.tm
.base_opcode
;
7994 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7996 && jump_reloc
== NO_RELOC
7997 && need_plt32_p (i
.op
[0].disps
->X_add_symbol
))
7998 jump_reloc
= BFD_RELOC_X86_64_PLT32
;
8001 jump_reloc
= reloc (size
, 1, 1, jump_reloc
);
8003 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
8004 i
.op
[0].disps
, 1, jump_reloc
);
8006 /* All jumps handled here are signed, but don't use a signed limit
8007 check for 32 and 16 bit jumps as we want to allow wrap around at
8008 4G and 64k respectively. */
8010 fixP
->fx_signed
= 1;
8014 output_interseg_jump (void)
8022 if (flag_code
== CODE_16BIT
)
8026 if (i
.prefix
[DATA_PREFIX
] != 0)
8032 if (i
.prefix
[REX_PREFIX
] != 0)
8042 if (i
.prefixes
!= 0 && !intel_syntax
)
8043 as_warn (_("skipping prefixes on this instruction"));
8045 /* 1 opcode; 2 segment; offset */
8046 p
= frag_more (prefix
+ 1 + 2 + size
);
8048 if (i
.prefix
[DATA_PREFIX
] != 0)
8049 *p
++ = DATA_PREFIX_OPCODE
;
8051 if (i
.prefix
[REX_PREFIX
] != 0)
8052 *p
++ = i
.prefix
[REX_PREFIX
];
8054 *p
++ = i
.tm
.base_opcode
;
8055 if (i
.op
[1].imms
->X_op
== O_constant
)
8057 offsetT n
= i
.op
[1].imms
->X_add_number
;
8060 && !fits_in_unsigned_word (n
)
8061 && !fits_in_signed_word (n
))
8063 as_bad (_("16-bit jump out of range"));
8066 md_number_to_chars (p
, n
, size
);
8069 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
8070 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
8071 if (i
.op
[0].imms
->X_op
!= O_constant
)
8072 as_bad (_("can't handle non absolute segment in `%s'"),
8074 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
8077 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8082 asection
*seg
= now_seg
;
8083 subsegT subseg
= now_subseg
;
8085 unsigned int alignment
, align_size_1
;
8086 unsigned int isa_1_descsz
, feature_2_descsz
, descsz
;
8087 unsigned int isa_1_descsz_raw
, feature_2_descsz_raw
;
8088 unsigned int padding
;
8090 if (!IS_ELF
|| !x86_used_note
)
8093 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_X86
;
8095 /* The .note.gnu.property section layout:
8097 Field Length Contents
8100 n_descsz 4 The note descriptor size
8101 n_type 4 NT_GNU_PROPERTY_TYPE_0
8103 n_desc n_descsz The program property array
8107 /* Create the .note.gnu.property section. */
8108 sec
= subseg_new (NOTE_GNU_PROPERTY_SECTION_NAME
, 0);
8109 bfd_set_section_flags (sec
,
8116 if (get_elf_backend_data (stdoutput
)->s
->elfclass
== ELFCLASS64
)
8127 bfd_set_section_alignment (sec
, alignment
);
8128 elf_section_type (sec
) = SHT_NOTE
;
8130 /* GNU_PROPERTY_X86_ISA_1_USED: 4-byte type + 4-byte data size
8132 isa_1_descsz_raw
= 4 + 4 + 4;
8133 /* Align GNU_PROPERTY_X86_ISA_1_USED. */
8134 isa_1_descsz
= (isa_1_descsz_raw
+ align_size_1
) & ~align_size_1
;
8136 feature_2_descsz_raw
= isa_1_descsz
;
8137 /* GNU_PROPERTY_X86_FEATURE_2_USED: 4-byte type + 4-byte data size
8139 feature_2_descsz_raw
+= 4 + 4 + 4;
8140 /* Align GNU_PROPERTY_X86_FEATURE_2_USED. */
8141 feature_2_descsz
= ((feature_2_descsz_raw
+ align_size_1
)
8144 descsz
= feature_2_descsz
;
8145 /* Section size: n_namsz + n_descsz + n_type + n_name + n_descsz. */
8146 p
= frag_more (4 + 4 + 4 + 4 + descsz
);
8148 /* Write n_namsz. */
8149 md_number_to_chars (p
, (valueT
) 4, 4);
8151 /* Write n_descsz. */
8152 md_number_to_chars (p
+ 4, (valueT
) descsz
, 4);
8155 md_number_to_chars (p
+ 4 * 2, (valueT
) NT_GNU_PROPERTY_TYPE_0
, 4);
8158 memcpy (p
+ 4 * 3, "GNU", 4);
8160 /* Write 4-byte type. */
8161 md_number_to_chars (p
+ 4 * 4,
8162 (valueT
) GNU_PROPERTY_X86_ISA_1_USED
, 4);
8164 /* Write 4-byte data size. */
8165 md_number_to_chars (p
+ 4 * 5, (valueT
) 4, 4);
8167 /* Write 4-byte data. */
8168 md_number_to_chars (p
+ 4 * 6, (valueT
) x86_isa_1_used
, 4);
8170 /* Zero out paddings. */
8171 padding
= isa_1_descsz
- isa_1_descsz_raw
;
8173 memset (p
+ 4 * 7, 0, padding
);
8175 /* Write 4-byte type. */
8176 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 4,
8177 (valueT
) GNU_PROPERTY_X86_FEATURE_2_USED
, 4);
8179 /* Write 4-byte data size. */
8180 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 5, (valueT
) 4, 4);
8182 /* Write 4-byte data. */
8183 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 6,
8184 (valueT
) x86_feature_2_used
, 4);
8186 /* Zero out paddings. */
8187 padding
= feature_2_descsz
- feature_2_descsz_raw
;
8189 memset (p
+ isa_1_descsz
+ 4 * 7, 0, padding
);
8191 /* We probably can't restore the current segment, for there likely
8194 subseg_set (seg
, subseg
);
8199 encoding_length (const fragS
*start_frag
, offsetT start_off
,
8200 const char *frag_now_ptr
)
8202 unsigned int len
= 0;
8204 if (start_frag
!= frag_now
)
8206 const fragS
*fr
= start_frag
;
8211 } while (fr
&& fr
!= frag_now
);
8214 return len
- start_off
+ (frag_now_ptr
- frag_now
->fr_literal
);
8220 fragS
*insn_start_frag
;
8221 offsetT insn_start_off
;
8223 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8224 if (IS_ELF
&& x86_used_note
)
8226 if (i
.tm
.cpu_flags
.bitfield
.cpucmov
)
8227 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_CMOV
;
8228 if (i
.tm
.cpu_flags
.bitfield
.cpusse
)
8229 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE
;
8230 if (i
.tm
.cpu_flags
.bitfield
.cpusse2
)
8231 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE2
;
8232 if (i
.tm
.cpu_flags
.bitfield
.cpusse3
)
8233 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE3
;
8234 if (i
.tm
.cpu_flags
.bitfield
.cpussse3
)
8235 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSSE3
;
8236 if (i
.tm
.cpu_flags
.bitfield
.cpusse4_1
)
8237 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE4_1
;
8238 if (i
.tm
.cpu_flags
.bitfield
.cpusse4_2
)
8239 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE4_2
;
8240 if (i
.tm
.cpu_flags
.bitfield
.cpuavx
)
8241 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX
;
8242 if (i
.tm
.cpu_flags
.bitfield
.cpuavx2
)
8243 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX2
;
8244 if (i
.tm
.cpu_flags
.bitfield
.cpufma
)
8245 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_FMA
;
8246 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512f
)
8247 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512F
;
8248 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512cd
)
8249 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512CD
;
8250 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512er
)
8251 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512ER
;
8252 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512pf
)
8253 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512PF
;
8254 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512vl
)
8255 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512VL
;
8256 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512dq
)
8257 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512DQ
;
8258 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512bw
)
8259 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512BW
;
8260 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_4fmaps
)
8261 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_4FMAPS
;
8262 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_4vnniw
)
8263 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_4VNNIW
;
8264 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_bitalg
)
8265 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_BITALG
;
8266 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512ifma
)
8267 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_IFMA
;
8268 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512vbmi
)
8269 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_VBMI
;
8270 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_vbmi2
)
8271 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_VBMI2
;
8272 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_vnni
)
8273 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_VNNI
;
8274 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_bf16
)
8275 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_BF16
;
8277 if (i
.tm
.cpu_flags
.bitfield
.cpu8087
8278 || i
.tm
.cpu_flags
.bitfield
.cpu287
8279 || i
.tm
.cpu_flags
.bitfield
.cpu387
8280 || i
.tm
.cpu_flags
.bitfield
.cpu687
8281 || i
.tm
.cpu_flags
.bitfield
.cpufisttp
)
8282 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_X87
;
8283 /* Don't set GNU_PROPERTY_X86_FEATURE_2_MMX for prefetchtXXX nor
8284 Xfence instructions. */
8285 if (i
.tm
.base_opcode
!= 0xf18
8286 && i
.tm
.base_opcode
!= 0xf0d
8287 && i
.tm
.base_opcode
!= 0xfaef8
8289 || i
.tm
.cpu_flags
.bitfield
.cpummx
8290 || i
.tm
.cpu_flags
.bitfield
.cpua3dnow
8291 || i
.tm
.cpu_flags
.bitfield
.cpua3dnowa
))
8292 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_MMX
;
8294 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XMM
;
8296 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_YMM
;
8298 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_ZMM
;
8299 if (i
.tm
.cpu_flags
.bitfield
.cpufxsr
)
8300 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_FXSR
;
8301 if (i
.tm
.cpu_flags
.bitfield
.cpuxsave
)
8302 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVE
;
8303 if (i
.tm
.cpu_flags
.bitfield
.cpuxsaveopt
)
8304 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVEOPT
;
8305 if (i
.tm
.cpu_flags
.bitfield
.cpuxsavec
)
8306 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVEC
;
8310 /* Tie dwarf2 debug info to the address at the start of the insn.
8311 We can't do this after the insn has been output as the current
8312 frag may have been closed off. eg. by frag_var. */
8313 dwarf2_emit_insn (0);
8315 insn_start_frag
= frag_now
;
8316 insn_start_off
= frag_now_fix ();
8319 if (i
.tm
.opcode_modifier
.jump
)
8321 else if (i
.tm
.opcode_modifier
.jumpbyte
8322 || i
.tm
.opcode_modifier
.jumpdword
)
8324 else if (i
.tm
.opcode_modifier
.jumpintersegment
)
8325 output_interseg_jump ();
8328 /* Output normal instructions here. */
8332 unsigned int prefix
;
8335 && (i
.tm
.base_opcode
== 0xfaee8
8336 || i
.tm
.base_opcode
== 0xfaef0
8337 || i
.tm
.base_opcode
== 0xfaef8))
8339 /* Encode lfence, mfence, and sfence as
8340 f0 83 04 24 00 lock addl $0x0, (%{re}sp). */
8341 offsetT val
= 0x240483f0ULL
;
8343 md_number_to_chars (p
, val
, 5);
8347 /* Some processors fail on LOCK prefix. This options makes
8348 assembler ignore LOCK prefix and serves as a workaround. */
8349 if (omit_lock_prefix
)
8351 if (i
.tm
.base_opcode
== LOCK_PREFIX_OPCODE
)
8353 i
.prefix
[LOCK_PREFIX
] = 0;
8356 /* Since the VEX/EVEX prefix contains the implicit prefix, we
8357 don't need the explicit prefix. */
8358 if (!i
.tm
.opcode_modifier
.vex
&& !i
.tm
.opcode_modifier
.evex
)
8360 switch (i
.tm
.opcode_length
)
8363 if (i
.tm
.base_opcode
& 0xff000000)
8365 prefix
= (i
.tm
.base_opcode
>> 24) & 0xff;
8366 if (!i
.tm
.cpu_flags
.bitfield
.cpupadlock
8367 || prefix
!= REPE_PREFIX_OPCODE
8368 || (i
.prefix
[REP_PREFIX
] != REPE_PREFIX_OPCODE
))
8369 add_prefix (prefix
);
8373 if ((i
.tm
.base_opcode
& 0xff0000) != 0)
8375 prefix
= (i
.tm
.base_opcode
>> 16) & 0xff;
8376 add_prefix (prefix
);
8382 /* Check for pseudo prefixes. */
8383 as_bad_where (insn_start_frag
->fr_file
,
8384 insn_start_frag
->fr_line
,
8385 _("pseudo prefix without instruction"));
8391 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
8392 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
8393 R_X86_64_GOTTPOFF relocation so that linker can safely
8394 perform IE->LE optimization. */
8395 if (x86_elf_abi
== X86_64_X32_ABI
8397 && i
.reloc
[0] == BFD_RELOC_X86_64_GOTTPOFF
8398 && i
.prefix
[REX_PREFIX
] == 0)
8399 add_prefix (REX_OPCODE
);
8402 /* The prefix bytes. */
8403 for (j
= ARRAY_SIZE (i
.prefix
), q
= i
.prefix
; j
> 0; j
--, q
++)
8405 FRAG_APPEND_1_CHAR (*q
);
8409 for (j
= 0, q
= i
.prefix
; j
< ARRAY_SIZE (i
.prefix
); j
++, q
++)
8414 /* REX byte is encoded in VEX prefix. */
8418 FRAG_APPEND_1_CHAR (*q
);
8421 /* There should be no other prefixes for instructions
8426 /* For EVEX instructions i.vrex should become 0 after
8427 build_evex_prefix. For VEX instructions upper 16 registers
8428 aren't available, so VREX should be 0. */
8431 /* Now the VEX prefix. */
8432 p
= frag_more (i
.vex
.length
);
8433 for (j
= 0; j
< i
.vex
.length
; j
++)
8434 p
[j
] = i
.vex
.bytes
[j
];
8437 /* Now the opcode; be careful about word order here! */
8438 if (i
.tm
.opcode_length
== 1)
8440 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
8444 switch (i
.tm
.opcode_length
)
8448 *p
++ = (i
.tm
.base_opcode
>> 24) & 0xff;
8449 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
8453 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
8463 /* Put out high byte first: can't use md_number_to_chars! */
8464 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
8465 *p
= i
.tm
.base_opcode
& 0xff;
8468 /* Now the modrm byte and sib byte (if present). */
8469 if (i
.tm
.opcode_modifier
.modrm
)
8471 FRAG_APPEND_1_CHAR ((i
.rm
.regmem
<< 0
8474 /* If i.rm.regmem == ESP (4)
8475 && i.rm.mode != (Register mode)
8477 ==> need second modrm byte. */
8478 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
8480 && !(i
.base_reg
&& i
.base_reg
->reg_type
.bitfield
.word
))
8481 FRAG_APPEND_1_CHAR ((i
.sib
.base
<< 0
8483 | i
.sib
.scale
<< 6));
8486 if (i
.disp_operands
)
8487 output_disp (insn_start_frag
, insn_start_off
);
8490 output_imm (insn_start_frag
, insn_start_off
);
8493 * frag_now_fix () returning plain abs_section_offset when we're in the
8494 * absolute section, and abs_section_offset not getting updated as data
8495 * gets added to the frag breaks the logic below.
8497 if (now_seg
!= absolute_section
)
8499 j
= encoding_length (insn_start_frag
, insn_start_off
, frag_more (0));
8501 as_warn (_("instruction length of %u bytes exceeds the limit of 15"),
8509 pi ("" /*line*/, &i
);
8511 #endif /* DEBUG386 */
8514 /* Return the size of the displacement operand N. */
8517 disp_size (unsigned int n
)
8521 if (i
.types
[n
].bitfield
.disp64
)
8523 else if (i
.types
[n
].bitfield
.disp8
)
8525 else if (i
.types
[n
].bitfield
.disp16
)
8530 /* Return the size of the immediate operand N. */
8533 imm_size (unsigned int n
)
8536 if (i
.types
[n
].bitfield
.imm64
)
8538 else if (i
.types
[n
].bitfield
.imm8
|| i
.types
[n
].bitfield
.imm8s
)
8540 else if (i
.types
[n
].bitfield
.imm16
)
8546 output_disp (fragS
*insn_start_frag
, offsetT insn_start_off
)
8551 for (n
= 0; n
< i
.operands
; n
++)
8553 if (operand_type_check (i
.types
[n
], disp
))
8555 if (i
.op
[n
].disps
->X_op
== O_constant
)
8557 int size
= disp_size (n
);
8558 offsetT val
= i
.op
[n
].disps
->X_add_number
;
8560 val
= offset_in_range (val
>> (size
== 1 ? i
.memshift
: 0),
8562 p
= frag_more (size
);
8563 md_number_to_chars (p
, val
, size
);
8567 enum bfd_reloc_code_real reloc_type
;
8568 int size
= disp_size (n
);
8569 int sign
= i
.types
[n
].bitfield
.disp32s
;
8570 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
8573 /* We can't have 8 bit displacement here. */
8574 gas_assert (!i
.types
[n
].bitfield
.disp8
);
8576 /* The PC relative address is computed relative
8577 to the instruction boundary, so in case immediate
8578 fields follows, we need to adjust the value. */
8579 if (pcrel
&& i
.imm_operands
)
8584 for (n1
= 0; n1
< i
.operands
; n1
++)
8585 if (operand_type_check (i
.types
[n1
], imm
))
8587 /* Only one immediate is allowed for PC
8588 relative address. */
8589 gas_assert (sz
== 0);
8591 i
.op
[n
].disps
->X_add_number
-= sz
;
8593 /* We should find the immediate. */
8594 gas_assert (sz
!= 0);
8597 p
= frag_more (size
);
8598 reloc_type
= reloc (size
, pcrel
, sign
, i
.reloc
[n
]);
8600 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
8601 && (((reloc_type
== BFD_RELOC_32
8602 || reloc_type
== BFD_RELOC_X86_64_32S
8603 || (reloc_type
== BFD_RELOC_64
8605 && (i
.op
[n
].disps
->X_op
== O_symbol
8606 || (i
.op
[n
].disps
->X_op
== O_add
8607 && ((symbol_get_value_expression
8608 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
8610 || reloc_type
== BFD_RELOC_32_PCREL
))
8614 reloc_type
= BFD_RELOC_386_GOTPC
;
8615 i
.op
[n
].imms
->X_add_number
+=
8616 encoding_length (insn_start_frag
, insn_start_off
, p
);
8618 else if (reloc_type
== BFD_RELOC_64
)
8619 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
8621 /* Don't do the adjustment for x86-64, as there
8622 the pcrel addressing is relative to the _next_
8623 insn, and that is taken care of in other code. */
8624 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
8626 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
8627 size
, i
.op
[n
].disps
, pcrel
,
8629 /* Check for "call/jmp *mem", "mov mem, %reg",
8630 "test %reg, mem" and "binop mem, %reg" where binop
8631 is one of adc, add, and, cmp, or, sbb, sub, xor
8632 instructions without data prefix. Always generate
8633 R_386_GOT32X for "sym*GOT" operand in 32-bit mode. */
8634 if (i
.prefix
[DATA_PREFIX
] == 0
8635 && (generate_relax_relocations
8638 && i
.rm
.regmem
== 5))
8640 || (i
.rm
.mode
== 0 && i
.rm
.regmem
== 5))
8641 && ((i
.operands
== 1
8642 && i
.tm
.base_opcode
== 0xff
8643 && (i
.rm
.reg
== 2 || i
.rm
.reg
== 4))
8645 && (i
.tm
.base_opcode
== 0x8b
8646 || i
.tm
.base_opcode
== 0x85
8647 || (i
.tm
.base_opcode
& 0xc7) == 0x03))))
8651 fixP
->fx_tcbit
= i
.rex
!= 0;
8653 && (i
.base_reg
->reg_num
== RegIP
))
8654 fixP
->fx_tcbit2
= 1;
8657 fixP
->fx_tcbit2
= 1;
8665 output_imm (fragS
*insn_start_frag
, offsetT insn_start_off
)
8670 for (n
= 0; n
< i
.operands
; n
++)
8672 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
8673 if (i
.rounding
&& (int) n
== i
.rounding
->operand
)
8676 if (operand_type_check (i
.types
[n
], imm
))
8678 if (i
.op
[n
].imms
->X_op
== O_constant
)
8680 int size
= imm_size (n
);
8683 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
8685 p
= frag_more (size
);
8686 md_number_to_chars (p
, val
, size
);
8690 /* Not absolute_section.
8691 Need a 32-bit fixup (don't support 8bit
8692 non-absolute imms). Try to support other
8694 enum bfd_reloc_code_real reloc_type
;
8695 int size
= imm_size (n
);
8698 if (i
.types
[n
].bitfield
.imm32s
8699 && (i
.suffix
== QWORD_MNEM_SUFFIX
8700 || (!i
.suffix
&& i
.tm
.opcode_modifier
.no_lsuf
)))
8705 p
= frag_more (size
);
8706 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
8708 /* This is tough to explain. We end up with this one if we
8709 * have operands that look like
8710 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
8711 * obtain the absolute address of the GOT, and it is strongly
8712 * preferable from a performance point of view to avoid using
8713 * a runtime relocation for this. The actual sequence of
8714 * instructions often look something like:
8719 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
8721 * The call and pop essentially return the absolute address
8722 * of the label .L66 and store it in %ebx. The linker itself
8723 * will ultimately change the first operand of the addl so
8724 * that %ebx points to the GOT, but to keep things simple, the
8725 * .o file must have this operand set so that it generates not
8726 * the absolute address of .L66, but the absolute address of
8727 * itself. This allows the linker itself simply treat a GOTPC
8728 * relocation as asking for a pcrel offset to the GOT to be
8729 * added in, and the addend of the relocation is stored in the
8730 * operand field for the instruction itself.
8732 * Our job here is to fix the operand so that it would add
8733 * the correct offset so that %ebx would point to itself. The
8734 * thing that is tricky is that .-.L66 will point to the
8735 * beginning of the instruction, so we need to further modify
8736 * the operand so that it will point to itself. There are
8737 * other cases where you have something like:
8739 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
8741 * and here no correction would be required. Internally in
8742 * the assembler we treat operands of this form as not being
8743 * pcrel since the '.' is explicitly mentioned, and I wonder
8744 * whether it would simplify matters to do it this way. Who
8745 * knows. In earlier versions of the PIC patches, the
8746 * pcrel_adjust field was used to store the correction, but
8747 * since the expression is not pcrel, I felt it would be
8748 * confusing to do it this way. */
8750 if ((reloc_type
== BFD_RELOC_32
8751 || reloc_type
== BFD_RELOC_X86_64_32S
8752 || reloc_type
== BFD_RELOC_64
)
8754 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
8755 && (i
.op
[n
].imms
->X_op
== O_symbol
8756 || (i
.op
[n
].imms
->X_op
== O_add
8757 && ((symbol_get_value_expression
8758 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
8762 reloc_type
= BFD_RELOC_386_GOTPC
;
8764 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
8766 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
8767 i
.op
[n
].imms
->X_add_number
+=
8768 encoding_length (insn_start_frag
, insn_start_off
, p
);
8770 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
8771 i
.op
[n
].imms
, 0, reloc_type
);
8777 /* x86_cons_fix_new is called via the expression parsing code when a
8778 reloc is needed. We use this hook to get the correct .got reloc. */
8779 static int cons_sign
= -1;
8782 x86_cons_fix_new (fragS
*frag
, unsigned int off
, unsigned int len
,
8783 expressionS
*exp
, bfd_reloc_code_real_type r
)
8785 r
= reloc (len
, 0, cons_sign
, r
);
8788 if (exp
->X_op
== O_secrel
)
8790 exp
->X_op
= O_symbol
;
8791 r
= BFD_RELOC_32_SECREL
;
8795 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
8798 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
8799 purpose of the `.dc.a' internal pseudo-op. */
8802 x86_address_bytes (void)
8804 if ((stdoutput
->arch_info
->mach
& bfd_mach_x64_32
))
8806 return stdoutput
->arch_info
->bits_per_address
/ 8;
8809 #if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
8811 # define lex_got(reloc, adjust, types) NULL
8813 /* Parse operands of the form
8814 <symbol>@GOTOFF+<nnn>
8815 and similar .plt or .got references.
8817 If we find one, set up the correct relocation in RELOC and copy the
8818 input string, minus the `@GOTOFF' into a malloc'd buffer for
8819 parsing by the calling routine. Return this buffer, and if ADJUST
8820 is non-null set it to the length of the string we removed from the
8821 input line. Otherwise return NULL. */
8823 lex_got (enum bfd_reloc_code_real
*rel
,
8825 i386_operand_type
*types
)
8827 /* Some of the relocations depend on the size of what field is to
8828 be relocated. But in our callers i386_immediate and i386_displacement
8829 we don't yet know the operand size (this will be set by insn
8830 matching). Hence we record the word32 relocation here,
8831 and adjust the reloc according to the real size in reloc(). */
8832 static const struct {
8835 const enum bfd_reloc_code_real rel
[2];
8836 const i386_operand_type types64
;
8838 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8839 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32
,
8841 OPERAND_TYPE_IMM32_64
},
8843 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real
,
8844 BFD_RELOC_X86_64_PLTOFF64
},
8845 OPERAND_TYPE_IMM64
},
8846 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32
,
8847 BFD_RELOC_X86_64_PLT32
},
8848 OPERAND_TYPE_IMM32_32S_DISP32
},
8849 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real
,
8850 BFD_RELOC_X86_64_GOTPLT64
},
8851 OPERAND_TYPE_IMM64_DISP64
},
8852 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF
,
8853 BFD_RELOC_X86_64_GOTOFF64
},
8854 OPERAND_TYPE_IMM64_DISP64
},
8855 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real
,
8856 BFD_RELOC_X86_64_GOTPCREL
},
8857 OPERAND_TYPE_IMM32_32S_DISP32
},
8858 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD
,
8859 BFD_RELOC_X86_64_TLSGD
},
8860 OPERAND_TYPE_IMM32_32S_DISP32
},
8861 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM
,
8862 _dummy_first_bfd_reloc_code_real
},
8863 OPERAND_TYPE_NONE
},
8864 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real
,
8865 BFD_RELOC_X86_64_TLSLD
},
8866 OPERAND_TYPE_IMM32_32S_DISP32
},
8867 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32
,
8868 BFD_RELOC_X86_64_GOTTPOFF
},
8869 OPERAND_TYPE_IMM32_32S_DISP32
},
8870 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32
,
8871 BFD_RELOC_X86_64_TPOFF32
},
8872 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
8873 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE
,
8874 _dummy_first_bfd_reloc_code_real
},
8875 OPERAND_TYPE_NONE
},
8876 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32
,
8877 BFD_RELOC_X86_64_DTPOFF32
},
8878 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
8879 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE
,
8880 _dummy_first_bfd_reloc_code_real
},
8881 OPERAND_TYPE_NONE
},
8882 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE
,
8883 _dummy_first_bfd_reloc_code_real
},
8884 OPERAND_TYPE_NONE
},
8885 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32
,
8886 BFD_RELOC_X86_64_GOT32
},
8887 OPERAND_TYPE_IMM32_32S_64_DISP32
},
8888 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC
,
8889 BFD_RELOC_X86_64_GOTPC32_TLSDESC
},
8890 OPERAND_TYPE_IMM32_32S_DISP32
},
8891 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL
,
8892 BFD_RELOC_X86_64_TLSDESC_CALL
},
8893 OPERAND_TYPE_IMM32_32S_DISP32
},
8898 #if defined (OBJ_MAYBE_ELF)
8903 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
8904 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
8907 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
8909 int len
= gotrel
[j
].len
;
8910 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
8912 if (gotrel
[j
].rel
[object_64bit
] != 0)
8915 char *tmpbuf
, *past_reloc
;
8917 *rel
= gotrel
[j
].rel
[object_64bit
];
8921 if (flag_code
!= CODE_64BIT
)
8923 types
->bitfield
.imm32
= 1;
8924 types
->bitfield
.disp32
= 1;
8927 *types
= gotrel
[j
].types64
;
8930 if (j
!= 0 && GOT_symbol
== NULL
)
8931 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
8933 /* The length of the first part of our input line. */
8934 first
= cp
- input_line_pointer
;
8936 /* The second part goes from after the reloc token until
8937 (and including) an end_of_line char or comma. */
8938 past_reloc
= cp
+ 1 + len
;
8940 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
8942 second
= cp
+ 1 - past_reloc
;
8944 /* Allocate and copy string. The trailing NUL shouldn't
8945 be necessary, but be safe. */
8946 tmpbuf
= XNEWVEC (char, first
+ second
+ 2);
8947 memcpy (tmpbuf
, input_line_pointer
, first
);
8948 if (second
!= 0 && *past_reloc
!= ' ')
8949 /* Replace the relocation token with ' ', so that
8950 errors like foo@GOTOFF1 will be detected. */
8951 tmpbuf
[first
++] = ' ';
8953 /* Increment length by 1 if the relocation token is
8958 memcpy (tmpbuf
+ first
, past_reloc
, second
);
8959 tmpbuf
[first
+ second
] = '\0';
8963 as_bad (_("@%s reloc is not supported with %d-bit output format"),
8964 gotrel
[j
].str
, 1 << (5 + object_64bit
));
8969 /* Might be a symbol version string. Don't as_bad here. */
8978 /* Parse operands of the form
8979 <symbol>@SECREL32+<nnn>
8981 If we find one, set up the correct relocation in RELOC and copy the
8982 input string, minus the `@SECREL32' into a malloc'd buffer for
8983 parsing by the calling routine. Return this buffer, and if ADJUST
8984 is non-null set it to the length of the string we removed from the
8985 input line. Otherwise return NULL.
8987 This function is copied from the ELF version above adjusted for PE targets. */
8990 lex_got (enum bfd_reloc_code_real
*rel ATTRIBUTE_UNUSED
,
8991 int *adjust ATTRIBUTE_UNUSED
,
8992 i386_operand_type
*types
)
8998 const enum bfd_reloc_code_real rel
[2];
8999 const i386_operand_type types64
;
9003 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL
,
9004 BFD_RELOC_32_SECREL
},
9005 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
9011 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
9012 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
9015 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
9017 int len
= gotrel
[j
].len
;
9019 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
9021 if (gotrel
[j
].rel
[object_64bit
] != 0)
9024 char *tmpbuf
, *past_reloc
;
9026 *rel
= gotrel
[j
].rel
[object_64bit
];
9032 if (flag_code
!= CODE_64BIT
)
9034 types
->bitfield
.imm32
= 1;
9035 types
->bitfield
.disp32
= 1;
9038 *types
= gotrel
[j
].types64
;
9041 /* The length of the first part of our input line. */
9042 first
= cp
- input_line_pointer
;
9044 /* The second part goes from after the reloc token until
9045 (and including) an end_of_line char or comma. */
9046 past_reloc
= cp
+ 1 + len
;
9048 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
9050 second
= cp
+ 1 - past_reloc
;
9052 /* Allocate and copy string. The trailing NUL shouldn't
9053 be necessary, but be safe. */
9054 tmpbuf
= XNEWVEC (char, first
+ second
+ 2);
9055 memcpy (tmpbuf
, input_line_pointer
, first
);
9056 if (second
!= 0 && *past_reloc
!= ' ')
9057 /* Replace the relocation token with ' ', so that
9058 errors like foo@SECLREL321 will be detected. */
9059 tmpbuf
[first
++] = ' ';
9060 memcpy (tmpbuf
+ first
, past_reloc
, second
);
9061 tmpbuf
[first
+ second
] = '\0';
9065 as_bad (_("@%s reloc is not supported with %d-bit output format"),
9066 gotrel
[j
].str
, 1 << (5 + object_64bit
));
9071 /* Might be a symbol version string. Don't as_bad here. */
9077 bfd_reloc_code_real_type
9078 x86_cons (expressionS
*exp
, int size
)
9080 bfd_reloc_code_real_type got_reloc
= NO_RELOC
;
9082 intel_syntax
= -intel_syntax
;
9085 if (size
== 4 || (object_64bit
&& size
== 8))
9087 /* Handle @GOTOFF and the like in an expression. */
9089 char *gotfree_input_line
;
9092 save
= input_line_pointer
;
9093 gotfree_input_line
= lex_got (&got_reloc
, &adjust
, NULL
);
9094 if (gotfree_input_line
)
9095 input_line_pointer
= gotfree_input_line
;
9099 if (gotfree_input_line
)
9101 /* expression () has merrily parsed up to the end of line,
9102 or a comma - in the wrong buffer. Transfer how far
9103 input_line_pointer has moved to the right buffer. */
9104 input_line_pointer
= (save
9105 + (input_line_pointer
- gotfree_input_line
)
9107 free (gotfree_input_line
);
9108 if (exp
->X_op
== O_constant
9109 || exp
->X_op
== O_absent
9110 || exp
->X_op
== O_illegal
9111 || exp
->X_op
== O_register
9112 || exp
->X_op
== O_big
)
9114 char c
= *input_line_pointer
;
9115 *input_line_pointer
= 0;
9116 as_bad (_("missing or invalid expression `%s'"), save
);
9117 *input_line_pointer
= c
;
9119 else if ((got_reloc
== BFD_RELOC_386_PLT32
9120 || got_reloc
== BFD_RELOC_X86_64_PLT32
)
9121 && exp
->X_op
!= O_symbol
)
9123 char c
= *input_line_pointer
;
9124 *input_line_pointer
= 0;
9125 as_bad (_("invalid PLT expression `%s'"), save
);
9126 *input_line_pointer
= c
;
9133 intel_syntax
= -intel_syntax
;
9136 i386_intel_simplify (exp
);
9142 signed_cons (int size
)
9144 if (flag_code
== CODE_64BIT
)
9152 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
9159 if (exp
.X_op
== O_symbol
)
9160 exp
.X_op
= O_secrel
;
9162 emit_expr (&exp
, 4);
9164 while (*input_line_pointer
++ == ',');
9166 input_line_pointer
--;
9167 demand_empty_rest_of_line ();
9171 /* Handle Vector operations. */
9174 check_VecOperations (char *op_string
, char *op_end
)
9176 const reg_entry
*mask
;
9181 && (op_end
== NULL
|| op_string
< op_end
))
9184 if (*op_string
== '{')
9188 /* Check broadcasts. */
9189 if (strncmp (op_string
, "1to", 3) == 0)
9194 goto duplicated_vec_op
;
9197 if (*op_string
== '8')
9199 else if (*op_string
== '4')
9201 else if (*op_string
== '2')
9203 else if (*op_string
== '1'
9204 && *(op_string
+1) == '6')
9211 as_bad (_("Unsupported broadcast: `%s'"), saved
);
9216 broadcast_op
.type
= bcst_type
;
9217 broadcast_op
.operand
= this_operand
;
9218 broadcast_op
.bytes
= 0;
9219 i
.broadcast
= &broadcast_op
;
9221 /* Check masking operation. */
9222 else if ((mask
= parse_register (op_string
, &end_op
)) != NULL
)
9224 /* k0 can't be used for write mask. */
9225 if (!mask
->reg_type
.bitfield
.regmask
|| mask
->reg_num
== 0)
9227 as_bad (_("`%s%s' can't be used for write mask"),
9228 register_prefix
, mask
->reg_name
);
9234 mask_op
.mask
= mask
;
9235 mask_op
.zeroing
= 0;
9236 mask_op
.operand
= this_operand
;
9242 goto duplicated_vec_op
;
9244 i
.mask
->mask
= mask
;
9246 /* Only "{z}" is allowed here. No need to check
9247 zeroing mask explicitly. */
9248 if (i
.mask
->operand
!= this_operand
)
9250 as_bad (_("invalid write mask `%s'"), saved
);
9257 /* Check zeroing-flag for masking operation. */
9258 else if (*op_string
== 'z')
9262 mask_op
.mask
= NULL
;
9263 mask_op
.zeroing
= 1;
9264 mask_op
.operand
= this_operand
;
9269 if (i
.mask
->zeroing
)
9272 as_bad (_("duplicated `%s'"), saved
);
9276 i
.mask
->zeroing
= 1;
9278 /* Only "{%k}" is allowed here. No need to check mask
9279 register explicitly. */
9280 if (i
.mask
->operand
!= this_operand
)
9282 as_bad (_("invalid zeroing-masking `%s'"),
9291 goto unknown_vec_op
;
9293 if (*op_string
!= '}')
9295 as_bad (_("missing `}' in `%s'"), saved
);
9300 /* Strip whitespace since the addition of pseudo prefixes
9301 changed how the scrubber treats '{'. */
9302 if (is_space_char (*op_string
))
9308 /* We don't know this one. */
9309 as_bad (_("unknown vector operation: `%s'"), saved
);
9313 if (i
.mask
&& i
.mask
->zeroing
&& !i
.mask
->mask
)
9315 as_bad (_("zeroing-masking only allowed with write mask"));
9323 i386_immediate (char *imm_start
)
9325 char *save_input_line_pointer
;
9326 char *gotfree_input_line
;
9329 i386_operand_type types
;
9331 operand_type_set (&types
, ~0);
9333 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
9335 as_bad (_("at most %d immediate operands are allowed"),
9336 MAX_IMMEDIATE_OPERANDS
);
9340 exp
= &im_expressions
[i
.imm_operands
++];
9341 i
.op
[this_operand
].imms
= exp
;
9343 if (is_space_char (*imm_start
))
9346 save_input_line_pointer
= input_line_pointer
;
9347 input_line_pointer
= imm_start
;
9349 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
9350 if (gotfree_input_line
)
9351 input_line_pointer
= gotfree_input_line
;
9353 exp_seg
= expression (exp
);
9357 /* Handle vector operations. */
9358 if (*input_line_pointer
== '{')
9360 input_line_pointer
= check_VecOperations (input_line_pointer
,
9362 if (input_line_pointer
== NULL
)
9366 if (*input_line_pointer
)
9367 as_bad (_("junk `%s' after expression"), input_line_pointer
);
9369 input_line_pointer
= save_input_line_pointer
;
9370 if (gotfree_input_line
)
9372 free (gotfree_input_line
);
9374 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
9375 exp
->X_op
= O_illegal
;
9378 return i386_finalize_immediate (exp_seg
, exp
, types
, imm_start
);
9382 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
9383 i386_operand_type types
, const char *imm_start
)
9385 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_illegal
|| exp
->X_op
== O_big
)
9388 as_bad (_("missing or invalid immediate expression `%s'"),
9392 else if (exp
->X_op
== O_constant
)
9394 /* Size it properly later. */
9395 i
.types
[this_operand
].bitfield
.imm64
= 1;
9396 /* If not 64bit, sign extend val. */
9397 if (flag_code
!= CODE_64BIT
9398 && (exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
9400 = (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
9402 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
9403 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
9404 && exp_seg
!= absolute_section
9405 && exp_seg
!= text_section
9406 && exp_seg
!= data_section
9407 && exp_seg
!= bss_section
9408 && exp_seg
!= undefined_section
9409 && !bfd_is_com_section (exp_seg
))
9411 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
9415 else if (!intel_syntax
&& exp_seg
== reg_section
)
9418 as_bad (_("illegal immediate register operand %s"), imm_start
);
9423 /* This is an address. The size of the address will be
9424 determined later, depending on destination register,
9425 suffix, or the default for the section. */
9426 i
.types
[this_operand
].bitfield
.imm8
= 1;
9427 i
.types
[this_operand
].bitfield
.imm16
= 1;
9428 i
.types
[this_operand
].bitfield
.imm32
= 1;
9429 i
.types
[this_operand
].bitfield
.imm32s
= 1;
9430 i
.types
[this_operand
].bitfield
.imm64
= 1;
9431 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
9439 i386_scale (char *scale
)
9442 char *save
= input_line_pointer
;
9444 input_line_pointer
= scale
;
9445 val
= get_absolute_expression ();
9450 i
.log2_scale_factor
= 0;
9453 i
.log2_scale_factor
= 1;
9456 i
.log2_scale_factor
= 2;
9459 i
.log2_scale_factor
= 3;
9463 char sep
= *input_line_pointer
;
9465 *input_line_pointer
= '\0';
9466 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
9468 *input_line_pointer
= sep
;
9469 input_line_pointer
= save
;
9473 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
9475 as_warn (_("scale factor of %d without an index register"),
9476 1 << i
.log2_scale_factor
);
9477 i
.log2_scale_factor
= 0;
9479 scale
= input_line_pointer
;
9480 input_line_pointer
= save
;
9485 i386_displacement (char *disp_start
, char *disp_end
)
9489 char *save_input_line_pointer
;
9490 char *gotfree_input_line
;
9492 i386_operand_type bigdisp
, types
= anydisp
;
9495 if (i
.disp_operands
== MAX_MEMORY_OPERANDS
)
9497 as_bad (_("at most %d displacement operands are allowed"),
9498 MAX_MEMORY_OPERANDS
);
9502 operand_type_set (&bigdisp
, 0);
9503 if ((i
.types
[this_operand
].bitfield
.jumpabsolute
)
9504 || (!current_templates
->start
->opcode_modifier
.jump
9505 && !current_templates
->start
->opcode_modifier
.jumpdword
))
9507 bigdisp
.bitfield
.disp32
= 1;
9508 override
= (i
.prefix
[ADDR_PREFIX
] != 0);
9509 if (flag_code
== CODE_64BIT
)
9513 bigdisp
.bitfield
.disp32s
= 1;
9514 bigdisp
.bitfield
.disp64
= 1;
9517 else if ((flag_code
== CODE_16BIT
) ^ override
)
9519 bigdisp
.bitfield
.disp32
= 0;
9520 bigdisp
.bitfield
.disp16
= 1;
9525 /* For PC-relative branches, the width of the displacement
9526 is dependent upon data size, not address size. */
9527 override
= (i
.prefix
[DATA_PREFIX
] != 0);
9528 if (flag_code
== CODE_64BIT
)
9530 if (override
|| i
.suffix
== WORD_MNEM_SUFFIX
)
9531 bigdisp
.bitfield
.disp16
= 1;
9534 bigdisp
.bitfield
.disp32
= 1;
9535 bigdisp
.bitfield
.disp32s
= 1;
9541 override
= (i
.suffix
== (flag_code
!= CODE_16BIT
9543 : LONG_MNEM_SUFFIX
));
9544 bigdisp
.bitfield
.disp32
= 1;
9545 if ((flag_code
== CODE_16BIT
) ^ override
)
9547 bigdisp
.bitfield
.disp32
= 0;
9548 bigdisp
.bitfield
.disp16
= 1;
9552 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
9555 exp
= &disp_expressions
[i
.disp_operands
];
9556 i
.op
[this_operand
].disps
= exp
;
9558 save_input_line_pointer
= input_line_pointer
;
9559 input_line_pointer
= disp_start
;
9560 END_STRING_AND_SAVE (disp_end
);
9562 #ifndef GCC_ASM_O_HACK
9563 #define GCC_ASM_O_HACK 0
9566 END_STRING_AND_SAVE (disp_end
+ 1);
9567 if (i
.types
[this_operand
].bitfield
.baseIndex
9568 && displacement_string_end
[-1] == '+')
9570 /* This hack is to avoid a warning when using the "o"
9571 constraint within gcc asm statements.
9574 #define _set_tssldt_desc(n,addr,limit,type) \
9575 __asm__ __volatile__ ( \
9577 "movw %w1,2+%0\n\t" \
9579 "movb %b1,4+%0\n\t" \
9580 "movb %4,5+%0\n\t" \
9581 "movb $0,6+%0\n\t" \
9582 "movb %h1,7+%0\n\t" \
9584 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
9586 This works great except that the output assembler ends
9587 up looking a bit weird if it turns out that there is
9588 no offset. You end up producing code that looks like:
9601 So here we provide the missing zero. */
9603 *displacement_string_end
= '0';
9606 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
9607 if (gotfree_input_line
)
9608 input_line_pointer
= gotfree_input_line
;
9610 exp_seg
= expression (exp
);
9613 if (*input_line_pointer
)
9614 as_bad (_("junk `%s' after expression"), input_line_pointer
);
9616 RESTORE_END_STRING (disp_end
+ 1);
9618 input_line_pointer
= save_input_line_pointer
;
9619 if (gotfree_input_line
)
9621 free (gotfree_input_line
);
9623 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
9624 exp
->X_op
= O_illegal
;
9627 ret
= i386_finalize_displacement (exp_seg
, exp
, types
, disp_start
);
9629 RESTORE_END_STRING (disp_end
);
9635 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
9636 i386_operand_type types
, const char *disp_start
)
9638 i386_operand_type bigdisp
;
9641 /* We do this to make sure that the section symbol is in
9642 the symbol table. We will ultimately change the relocation
9643 to be relative to the beginning of the section. */
9644 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
9645 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
9646 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
9648 if (exp
->X_op
!= O_symbol
)
9651 if (S_IS_LOCAL (exp
->X_add_symbol
)
9652 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
9653 && S_GET_SEGMENT (exp
->X_add_symbol
) != expr_section
)
9654 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
9655 exp
->X_op
= O_subtract
;
9656 exp
->X_op_symbol
= GOT_symbol
;
9657 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
9658 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
9659 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
9660 i
.reloc
[this_operand
] = BFD_RELOC_64
;
9662 i
.reloc
[this_operand
] = BFD_RELOC_32
;
9665 else if (exp
->X_op
== O_absent
9666 || exp
->X_op
== O_illegal
9667 || exp
->X_op
== O_big
)
9670 as_bad (_("missing or invalid displacement expression `%s'"),
9675 else if (flag_code
== CODE_64BIT
9676 && !i
.prefix
[ADDR_PREFIX
]
9677 && exp
->X_op
== O_constant
)
9679 /* Since displacement is signed extended to 64bit, don't allow
9680 disp32 and turn off disp32s if they are out of range. */
9681 i
.types
[this_operand
].bitfield
.disp32
= 0;
9682 if (!fits_in_signed_long (exp
->X_add_number
))
9684 i
.types
[this_operand
].bitfield
.disp32s
= 0;
9685 if (i
.types
[this_operand
].bitfield
.baseindex
)
9687 as_bad (_("0x%lx out range of signed 32bit displacement"),
9688 (long) exp
->X_add_number
);
9694 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
9695 else if (exp
->X_op
!= O_constant
9696 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
9697 && exp_seg
!= absolute_section
9698 && exp_seg
!= text_section
9699 && exp_seg
!= data_section
9700 && exp_seg
!= bss_section
9701 && exp_seg
!= undefined_section
9702 && !bfd_is_com_section (exp_seg
))
9704 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
9709 /* Check if this is a displacement only operand. */
9710 bigdisp
= i
.types
[this_operand
];
9711 bigdisp
.bitfield
.disp8
= 0;
9712 bigdisp
.bitfield
.disp16
= 0;
9713 bigdisp
.bitfield
.disp32
= 0;
9714 bigdisp
.bitfield
.disp32s
= 0;
9715 bigdisp
.bitfield
.disp64
= 0;
9716 if (operand_type_all_zero (&bigdisp
))
9717 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
9723 /* Return the active addressing mode, taking address override and
9724 registers forming the address into consideration. Update the
9725 address override prefix if necessary. */
9727 static enum flag_code
9728 i386_addressing_mode (void)
9730 enum flag_code addr_mode
;
9732 if (i
.prefix
[ADDR_PREFIX
])
9733 addr_mode
= flag_code
== CODE_32BIT
? CODE_16BIT
: CODE_32BIT
;
9736 addr_mode
= flag_code
;
9738 #if INFER_ADDR_PREFIX
9739 if (i
.mem_operands
== 0)
9741 /* Infer address prefix from the first memory operand. */
9742 const reg_entry
*addr_reg
= i
.base_reg
;
9744 if (addr_reg
== NULL
)
9745 addr_reg
= i
.index_reg
;
9749 if (addr_reg
->reg_type
.bitfield
.dword
)
9750 addr_mode
= CODE_32BIT
;
9751 else if (flag_code
!= CODE_64BIT
9752 && addr_reg
->reg_type
.bitfield
.word
)
9753 addr_mode
= CODE_16BIT
;
9755 if (addr_mode
!= flag_code
)
9757 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
9759 /* Change the size of any displacement too. At most one
9760 of Disp16 or Disp32 is set.
9761 FIXME. There doesn't seem to be any real need for
9762 separate Disp16 and Disp32 flags. The same goes for
9763 Imm16 and Imm32. Removing them would probably clean
9764 up the code quite a lot. */
9765 if (flag_code
!= CODE_64BIT
9766 && (i
.types
[this_operand
].bitfield
.disp16
9767 || i
.types
[this_operand
].bitfield
.disp32
))
9768 i
.types
[this_operand
]
9769 = operand_type_xor (i
.types
[this_operand
], disp16_32
);
9779 /* Make sure the memory operand we've been dealt is valid.
9780 Return 1 on success, 0 on a failure. */
9783 i386_index_check (const char *operand_string
)
9785 const char *kind
= "base/index";
9786 enum flag_code addr_mode
= i386_addressing_mode ();
9788 if (current_templates
->start
->opcode_modifier
.isstring
9789 && !current_templates
->start
->cpu_flags
.bitfield
.cpupadlock
9790 && (current_templates
->end
[-1].opcode_modifier
.isstring
9793 /* Memory operands of string insns are special in that they only allow
9794 a single register (rDI, rSI, or rBX) as their memory address. */
9795 const reg_entry
*expected_reg
;
9796 static const char *di_si
[][2] =
9802 static const char *bx
[] = { "ebx", "bx", "rbx" };
9804 kind
= "string address";
9806 if (current_templates
->start
->opcode_modifier
.repprefixok
)
9808 i386_operand_type type
= current_templates
->end
[-1].operand_types
[0];
9810 if (!type
.bitfield
.baseindex
9811 || ((!i
.mem_operands
!= !intel_syntax
)
9812 && current_templates
->end
[-1].operand_types
[1]
9813 .bitfield
.baseindex
))
9814 type
= current_templates
->end
[-1].operand_types
[1];
9815 expected_reg
= hash_find (reg_hash
,
9816 di_si
[addr_mode
][type
.bitfield
.esseg
]);
9820 expected_reg
= hash_find (reg_hash
, bx
[addr_mode
]);
9822 if (i
.base_reg
!= expected_reg
9824 || operand_type_check (i
.types
[this_operand
], disp
))
9826 /* The second memory operand must have the same size as
9830 && !((addr_mode
== CODE_64BIT
9831 && i
.base_reg
->reg_type
.bitfield
.qword
)
9832 || (addr_mode
== CODE_32BIT
9833 ? i
.base_reg
->reg_type
.bitfield
.dword
9834 : i
.base_reg
->reg_type
.bitfield
.word
)))
9837 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
9839 intel_syntax
? '[' : '(',
9841 expected_reg
->reg_name
,
9842 intel_syntax
? ']' : ')');
9849 as_bad (_("`%s' is not a valid %s expression"),
9850 operand_string
, kind
);
9855 if (addr_mode
!= CODE_16BIT
)
9857 /* 32-bit/64-bit checks. */
9859 && ((addr_mode
== CODE_64BIT
9860 ? !i
.base_reg
->reg_type
.bitfield
.qword
9861 : !i
.base_reg
->reg_type
.bitfield
.dword
)
9862 || (i
.index_reg
&& i
.base_reg
->reg_num
== RegIP
)
9863 || i
.base_reg
->reg_num
== RegIZ
))
9865 && !i
.index_reg
->reg_type
.bitfield
.xmmword
9866 && !i
.index_reg
->reg_type
.bitfield
.ymmword
9867 && !i
.index_reg
->reg_type
.bitfield
.zmmword
9868 && ((addr_mode
== CODE_64BIT
9869 ? !i
.index_reg
->reg_type
.bitfield
.qword
9870 : !i
.index_reg
->reg_type
.bitfield
.dword
)
9871 || !i
.index_reg
->reg_type
.bitfield
.baseindex
)))
9874 /* bndmk, bndldx, and bndstx have special restrictions. */
9875 if (current_templates
->start
->base_opcode
== 0xf30f1b
9876 || (current_templates
->start
->base_opcode
& ~1) == 0x0f1a)
9878 /* They cannot use RIP-relative addressing. */
9879 if (i
.base_reg
&& i
.base_reg
->reg_num
== RegIP
)
9881 as_bad (_("`%s' cannot be used here"), operand_string
);
9885 /* bndldx and bndstx ignore their scale factor. */
9886 if (current_templates
->start
->base_opcode
!= 0xf30f1b
9887 && i
.log2_scale_factor
)
9888 as_warn (_("register scaling is being ignored here"));
9893 /* 16-bit checks. */
9895 && (!i
.base_reg
->reg_type
.bitfield
.word
9896 || !i
.base_reg
->reg_type
.bitfield
.baseindex
))
9898 && (!i
.index_reg
->reg_type
.bitfield
.word
9899 || !i
.index_reg
->reg_type
.bitfield
.baseindex
9901 && i
.base_reg
->reg_num
< 6
9902 && i
.index_reg
->reg_num
>= 6
9903 && i
.log2_scale_factor
== 0))))
9910 /* Handle vector immediates. */
9913 RC_SAE_immediate (const char *imm_start
)
9915 unsigned int match_found
, j
;
9916 const char *pstr
= imm_start
;
9924 for (j
= 0; j
< ARRAY_SIZE (RC_NamesTable
); j
++)
9926 if (!strncmp (pstr
, RC_NamesTable
[j
].name
, RC_NamesTable
[j
].len
))
9930 rc_op
.type
= RC_NamesTable
[j
].type
;
9931 rc_op
.operand
= this_operand
;
9932 i
.rounding
= &rc_op
;
9936 as_bad (_("duplicated `%s'"), imm_start
);
9939 pstr
+= RC_NamesTable
[j
].len
;
9949 as_bad (_("Missing '}': '%s'"), imm_start
);
9952 /* RC/SAE immediate string should contain nothing more. */;
9955 as_bad (_("Junk after '}': '%s'"), imm_start
);
9959 exp
= &im_expressions
[i
.imm_operands
++];
9960 i
.op
[this_operand
].imms
= exp
;
9962 exp
->X_op
= O_constant
;
9963 exp
->X_add_number
= 0;
9964 exp
->X_add_symbol
= (symbolS
*) 0;
9965 exp
->X_op_symbol
= (symbolS
*) 0;
9967 i
.types
[this_operand
].bitfield
.imm8
= 1;
9971 /* Only string instructions can have a second memory operand, so
9972 reduce current_templates to just those if it contains any. */
9974 maybe_adjust_templates (void)
9976 const insn_template
*t
;
9978 gas_assert (i
.mem_operands
== 1);
9980 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
9981 if (t
->opcode_modifier
.isstring
)
9984 if (t
< current_templates
->end
)
9986 static templates aux_templates
;
9987 bfd_boolean recheck
;
9989 aux_templates
.start
= t
;
9990 for (; t
< current_templates
->end
; ++t
)
9991 if (!t
->opcode_modifier
.isstring
)
9993 aux_templates
.end
= t
;
9995 /* Determine whether to re-check the first memory operand. */
9996 recheck
= (aux_templates
.start
!= current_templates
->start
9997 || t
!= current_templates
->end
);
9999 current_templates
= &aux_templates
;
10003 i
.mem_operands
= 0;
10004 if (i
.memop1_string
!= NULL
10005 && i386_index_check (i
.memop1_string
) == 0)
10007 i
.mem_operands
= 1;
10014 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
10018 i386_att_operand (char *operand_string
)
10020 const reg_entry
*r
;
10022 char *op_string
= operand_string
;
10024 if (is_space_char (*op_string
))
10027 /* We check for an absolute prefix (differentiating,
10028 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
10029 if (*op_string
== ABSOLUTE_PREFIX
)
10032 if (is_space_char (*op_string
))
10034 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
10037 /* Check if operand is a register. */
10038 if ((r
= parse_register (op_string
, &end_op
)) != NULL
)
10040 i386_operand_type temp
;
10042 /* Check for a segment override by searching for ':' after a
10043 segment register. */
10044 op_string
= end_op
;
10045 if (is_space_char (*op_string
))
10047 if (*op_string
== ':' && r
->reg_type
.bitfield
.sreg
)
10049 switch (r
->reg_num
)
10052 i
.seg
[i
.mem_operands
] = &es
;
10055 i
.seg
[i
.mem_operands
] = &cs
;
10058 i
.seg
[i
.mem_operands
] = &ss
;
10061 i
.seg
[i
.mem_operands
] = &ds
;
10064 i
.seg
[i
.mem_operands
] = &fs
;
10067 i
.seg
[i
.mem_operands
] = &gs
;
10071 /* Skip the ':' and whitespace. */
10073 if (is_space_char (*op_string
))
10076 if (!is_digit_char (*op_string
)
10077 && !is_identifier_char (*op_string
)
10078 && *op_string
!= '('
10079 && *op_string
!= ABSOLUTE_PREFIX
)
10081 as_bad (_("bad memory operand `%s'"), op_string
);
10084 /* Handle case of %es:*foo. */
10085 if (*op_string
== ABSOLUTE_PREFIX
)
10088 if (is_space_char (*op_string
))
10090 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
10092 goto do_memory_reference
;
10095 /* Handle vector operations. */
10096 if (*op_string
== '{')
10098 op_string
= check_VecOperations (op_string
, NULL
);
10099 if (op_string
== NULL
)
10105 as_bad (_("junk `%s' after register"), op_string
);
10108 temp
= r
->reg_type
;
10109 temp
.bitfield
.baseindex
= 0;
10110 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
10112 i
.types
[this_operand
].bitfield
.unspecified
= 0;
10113 i
.op
[this_operand
].regs
= r
;
10116 else if (*op_string
== REGISTER_PREFIX
)
10118 as_bad (_("bad register name `%s'"), op_string
);
10121 else if (*op_string
== IMMEDIATE_PREFIX
)
10124 if (i
.types
[this_operand
].bitfield
.jumpabsolute
)
10126 as_bad (_("immediate operand illegal with absolute jump"));
10129 if (!i386_immediate (op_string
))
10132 else if (RC_SAE_immediate (operand_string
))
10134 /* If it is a RC or SAE immediate, do nothing. */
10137 else if (is_digit_char (*op_string
)
10138 || is_identifier_char (*op_string
)
10139 || *op_string
== '"'
10140 || *op_string
== '(')
10142 /* This is a memory reference of some sort. */
10145 /* Start and end of displacement string expression (if found). */
10146 char *displacement_string_start
;
10147 char *displacement_string_end
;
10150 do_memory_reference
:
10151 if (i
.mem_operands
== 1 && !maybe_adjust_templates ())
10153 if ((i
.mem_operands
== 1
10154 && !current_templates
->start
->opcode_modifier
.isstring
)
10155 || i
.mem_operands
== 2)
10157 as_bad (_("too many memory references for `%s'"),
10158 current_templates
->start
->name
);
10162 /* Check for base index form. We detect the base index form by
10163 looking for an ')' at the end of the operand, searching
10164 for the '(' matching it, and finding a REGISTER_PREFIX or ','
10166 base_string
= op_string
+ strlen (op_string
);
10168 /* Handle vector operations. */
10169 vop_start
= strchr (op_string
, '{');
10170 if (vop_start
&& vop_start
< base_string
)
10172 if (check_VecOperations (vop_start
, base_string
) == NULL
)
10174 base_string
= vop_start
;
10178 if (is_space_char (*base_string
))
10181 /* If we only have a displacement, set-up for it to be parsed later. */
10182 displacement_string_start
= op_string
;
10183 displacement_string_end
= base_string
+ 1;
10185 if (*base_string
== ')')
10188 unsigned int parens_balanced
= 1;
10189 /* We've already checked that the number of left & right ()'s are
10190 equal, so this loop will not be infinite. */
10194 if (*base_string
== ')')
10196 if (*base_string
== '(')
10199 while (parens_balanced
);
10201 temp_string
= base_string
;
10203 /* Skip past '(' and whitespace. */
10205 if (is_space_char (*base_string
))
10208 if (*base_string
== ','
10209 || ((i
.base_reg
= parse_register (base_string
, &end_op
))
10212 displacement_string_end
= temp_string
;
10214 i
.types
[this_operand
].bitfield
.baseindex
= 1;
10218 base_string
= end_op
;
10219 if (is_space_char (*base_string
))
10223 /* There may be an index reg or scale factor here. */
10224 if (*base_string
== ',')
10227 if (is_space_char (*base_string
))
10230 if ((i
.index_reg
= parse_register (base_string
, &end_op
))
10233 base_string
= end_op
;
10234 if (is_space_char (*base_string
))
10236 if (*base_string
== ',')
10239 if (is_space_char (*base_string
))
10242 else if (*base_string
!= ')')
10244 as_bad (_("expecting `,' or `)' "
10245 "after index register in `%s'"),
10250 else if (*base_string
== REGISTER_PREFIX
)
10252 end_op
= strchr (base_string
, ',');
10255 as_bad (_("bad register name `%s'"), base_string
);
10259 /* Check for scale factor. */
10260 if (*base_string
!= ')')
10262 char *end_scale
= i386_scale (base_string
);
10267 base_string
= end_scale
;
10268 if (is_space_char (*base_string
))
10270 if (*base_string
!= ')')
10272 as_bad (_("expecting `)' "
10273 "after scale factor in `%s'"),
10278 else if (!i
.index_reg
)
10280 as_bad (_("expecting index register or scale factor "
10281 "after `,'; got '%c'"),
10286 else if (*base_string
!= ')')
10288 as_bad (_("expecting `,' or `)' "
10289 "after base register in `%s'"),
10294 else if (*base_string
== REGISTER_PREFIX
)
10296 end_op
= strchr (base_string
, ',');
10299 as_bad (_("bad register name `%s'"), base_string
);
10304 /* If there's an expression beginning the operand, parse it,
10305 assuming displacement_string_start and
10306 displacement_string_end are meaningful. */
10307 if (displacement_string_start
!= displacement_string_end
)
10309 if (!i386_displacement (displacement_string_start
,
10310 displacement_string_end
))
10314 /* Special case for (%dx) while doing input/output op. */
10316 && i
.base_reg
->reg_type
.bitfield
.inoutportreg
10317 && i
.index_reg
== 0
10318 && i
.log2_scale_factor
== 0
10319 && i
.seg
[i
.mem_operands
] == 0
10320 && !operand_type_check (i
.types
[this_operand
], disp
))
10322 i
.types
[this_operand
] = i
.base_reg
->reg_type
;
10326 if (i386_index_check (operand_string
) == 0)
10328 i
.flags
[this_operand
] |= Operand_Mem
;
10329 if (i
.mem_operands
== 0)
10330 i
.memop1_string
= xstrdup (operand_string
);
10335 /* It's not a memory operand; argh! */
10336 as_bad (_("invalid char %s beginning operand %d `%s'"),
10337 output_invalid (*op_string
),
10342 return 1; /* Normal return. */
10345 /* Calculate the maximum variable size (i.e., excluding fr_fix)
10346 that an rs_machine_dependent frag may reach. */
10349 i386_frag_max_var (fragS
*frag
)
10351 /* The only relaxable frags are for jumps.
10352 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
10353 gas_assert (frag
->fr_type
== rs_machine_dependent
);
10354 return TYPE_FROM_RELAX_STATE (frag
->fr_subtype
) == UNCOND_JUMP
? 4 : 5;
10357 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10359 elf_symbol_resolved_in_segment_p (symbolS
*fr_symbol
, offsetT fr_var
)
10361 /* STT_GNU_IFUNC symbol must go through PLT. */
10362 if ((symbol_get_bfdsym (fr_symbol
)->flags
10363 & BSF_GNU_INDIRECT_FUNCTION
) != 0)
10366 if (!S_IS_EXTERNAL (fr_symbol
))
10367 /* Symbol may be weak or local. */
10368 return !S_IS_WEAK (fr_symbol
);
10370 /* Global symbols with non-default visibility can't be preempted. */
10371 if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol
)) != STV_DEFAULT
)
10374 if (fr_var
!= NO_RELOC
)
10375 switch ((enum bfd_reloc_code_real
) fr_var
)
10377 case BFD_RELOC_386_PLT32
:
10378 case BFD_RELOC_X86_64_PLT32
:
10379 /* Symbol with PLT relocation may be preempted. */
10385 /* Global symbols with default visibility in a shared library may be
10386 preempted by another definition. */
10391 /* md_estimate_size_before_relax()
10393 Called just before relax() for rs_machine_dependent frags. The x86
10394 assembler uses these frags to handle variable size jump
10397 Any symbol that is now undefined will not become defined.
10398 Return the correct fr_subtype in the frag.
10399 Return the initial "guess for variable size of frag" to caller.
10400 The guess is actually the growth beyond the fixed part. Whatever
10401 we do to grow the fixed or variable part contributes to our
10405 md_estimate_size_before_relax (fragS
*fragP
, segT segment
)
10407 /* We've already got fragP->fr_subtype right; all we have to do is
10408 check for un-relaxable symbols. On an ELF system, we can't relax
10409 an externally visible symbol, because it may be overridden by a
10411 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
10412 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10414 && !elf_symbol_resolved_in_segment_p (fragP
->fr_symbol
,
10417 #if defined (OBJ_COFF) && defined (TE_PE)
10418 || (OUTPUT_FLAVOR
== bfd_target_coff_flavour
10419 && S_IS_WEAK (fragP
->fr_symbol
))
10423 /* Symbol is undefined in this segment, or we need to keep a
10424 reloc so that weak symbols can be overridden. */
10425 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
10426 enum bfd_reloc_code_real reloc_type
;
10427 unsigned char *opcode
;
10430 if (fragP
->fr_var
!= NO_RELOC
)
10431 reloc_type
= (enum bfd_reloc_code_real
) fragP
->fr_var
;
10432 else if (size
== 2)
10433 reloc_type
= BFD_RELOC_16_PCREL
;
10434 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10435 else if (need_plt32_p (fragP
->fr_symbol
))
10436 reloc_type
= BFD_RELOC_X86_64_PLT32
;
10439 reloc_type
= BFD_RELOC_32_PCREL
;
10441 old_fr_fix
= fragP
->fr_fix
;
10442 opcode
= (unsigned char *) fragP
->fr_opcode
;
10444 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
10447 /* Make jmp (0xeb) a (d)word displacement jump. */
10449 fragP
->fr_fix
+= size
;
10450 fix_new (fragP
, old_fr_fix
, size
,
10452 fragP
->fr_offset
, 1,
10458 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
10460 /* Negate the condition, and branch past an
10461 unconditional jump. */
10464 /* Insert an unconditional jump. */
10466 /* We added two extra opcode bytes, and have a two byte
10468 fragP
->fr_fix
+= 2 + 2;
10469 fix_new (fragP
, old_fr_fix
+ 2, 2,
10471 fragP
->fr_offset
, 1,
10475 /* Fall through. */
10478 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
10482 fragP
->fr_fix
+= 1;
10483 fixP
= fix_new (fragP
, old_fr_fix
, 1,
10485 fragP
->fr_offset
, 1,
10486 BFD_RELOC_8_PCREL
);
10487 fixP
->fx_signed
= 1;
10491 /* This changes the byte-displacement jump 0x7N
10492 to the (d)word-displacement jump 0x0f,0x8N. */
10493 opcode
[1] = opcode
[0] + 0x10;
10494 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
10495 /* We've added an opcode byte. */
10496 fragP
->fr_fix
+= 1 + size
;
10497 fix_new (fragP
, old_fr_fix
+ 1, size
,
10499 fragP
->fr_offset
, 1,
10504 BAD_CASE (fragP
->fr_subtype
);
10508 return fragP
->fr_fix
- old_fr_fix
;
10511 /* Guess size depending on current relax state. Initially the relax
10512 state will correspond to a short jump and we return 1, because
10513 the variable part of the frag (the branch offset) is one byte
10514 long. However, we can relax a section more than once and in that
10515 case we must either set fr_subtype back to the unrelaxed state,
10516 or return the value for the appropriate branch. */
10517 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
10520 /* Called after relax() is finished.
10522 In: Address of frag.
10523 fr_type == rs_machine_dependent.
10524 fr_subtype is what the address relaxed to.
10526 Out: Any fixSs and constants are set up.
10527 Caller will turn frag into a ".space 0". */
10530 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec ATTRIBUTE_UNUSED
,
10533 unsigned char *opcode
;
10534 unsigned char *where_to_put_displacement
= NULL
;
10535 offsetT target_address
;
10536 offsetT opcode_address
;
10537 unsigned int extension
= 0;
10538 offsetT displacement_from_opcode_start
;
10540 opcode
= (unsigned char *) fragP
->fr_opcode
;
10542 /* Address we want to reach in file space. */
10543 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
10545 /* Address opcode resides at in file space. */
10546 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
10548 /* Displacement from opcode start to fill into instruction. */
10549 displacement_from_opcode_start
= target_address
- opcode_address
;
10551 if ((fragP
->fr_subtype
& BIG
) == 0)
10553 /* Don't have to change opcode. */
10554 extension
= 1; /* 1 opcode + 1 displacement */
10555 where_to_put_displacement
= &opcode
[1];
10559 if (no_cond_jump_promotion
10560 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
10561 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
10562 _("long jump required"));
10564 switch (fragP
->fr_subtype
)
10566 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
10567 extension
= 4; /* 1 opcode + 4 displacement */
10569 where_to_put_displacement
= &opcode
[1];
10572 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
10573 extension
= 2; /* 1 opcode + 2 displacement */
10575 where_to_put_displacement
= &opcode
[1];
10578 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
10579 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
10580 extension
= 5; /* 2 opcode + 4 displacement */
10581 opcode
[1] = opcode
[0] + 0x10;
10582 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
10583 where_to_put_displacement
= &opcode
[2];
10586 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
10587 extension
= 3; /* 2 opcode + 2 displacement */
10588 opcode
[1] = opcode
[0] + 0x10;
10589 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
10590 where_to_put_displacement
= &opcode
[2];
10593 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
10598 where_to_put_displacement
= &opcode
[3];
10602 BAD_CASE (fragP
->fr_subtype
);
10607 /* If size if less then four we are sure that the operand fits,
10608 but if it's 4, then it could be that the displacement is larger
10610 if (DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
) == 4
10612 && ((addressT
) (displacement_from_opcode_start
- extension
10613 + ((addressT
) 1 << 31))
10614 > (((addressT
) 2 << 31) - 1)))
10616 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
10617 _("jump target out of range"));
10618 /* Make us emit 0. */
10619 displacement_from_opcode_start
= extension
;
10621 /* Now put displacement after opcode. */
10622 md_number_to_chars ((char *) where_to_put_displacement
,
10623 (valueT
) (displacement_from_opcode_start
- extension
),
10624 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
10625 fragP
->fr_fix
+= extension
;
10628 /* Apply a fixup (fixP) to segment data, once it has been determined
10629 by our caller that we have all the info we need to fix it up.
10631 Parameter valP is the pointer to the value of the bits.
10633 On the 386, immediates, displacements, and data pointers are all in
10634 the same (little-endian) format, so we don't need to care about which
10635 we are handling. */
10638 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
10640 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
10641 valueT value
= *valP
;
10643 #if !defined (TE_Mach)
10644 if (fixP
->fx_pcrel
)
10646 switch (fixP
->fx_r_type
)
10652 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
10655 case BFD_RELOC_X86_64_32S
:
10656 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
10659 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
10662 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
10667 if (fixP
->fx_addsy
!= NULL
10668 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
10669 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
10670 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
10671 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
10672 && !use_rela_relocations
)
10674 /* This is a hack. There should be a better way to handle this.
10675 This covers for the fact that bfd_install_relocation will
10676 subtract the current location (for partial_inplace, PC relative
10677 relocations); see more below. */
10681 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
10684 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
10686 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10689 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
10691 if ((sym_seg
== seg
10692 || (symbol_section_p (fixP
->fx_addsy
)
10693 && sym_seg
!= absolute_section
))
10694 && !generic_force_reloc (fixP
))
10696 /* Yes, we add the values in twice. This is because
10697 bfd_install_relocation subtracts them out again. I think
10698 bfd_install_relocation is broken, but I don't dare change
10700 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
10704 #if defined (OBJ_COFF) && defined (TE_PE)
10705 /* For some reason, the PE format does not store a
10706 section address offset for a PC relative symbol. */
10707 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
10708 || S_IS_WEAK (fixP
->fx_addsy
))
10709 value
+= md_pcrel_from (fixP
);
10712 #if defined (OBJ_COFF) && defined (TE_PE)
10713 if (fixP
->fx_addsy
!= NULL
10714 && S_IS_WEAK (fixP
->fx_addsy
)
10715 /* PR 16858: Do not modify weak function references. */
10716 && ! fixP
->fx_pcrel
)
10718 #if !defined (TE_PEP)
10719 /* For x86 PE weak function symbols are neither PC-relative
10720 nor do they set S_IS_FUNCTION. So the only reliable way
10721 to detect them is to check the flags of their containing
10723 if (S_GET_SEGMENT (fixP
->fx_addsy
) != NULL
10724 && S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_CODE
)
10728 value
-= S_GET_VALUE (fixP
->fx_addsy
);
10732 /* Fix a few things - the dynamic linker expects certain values here,
10733 and we must not disappoint it. */
10734 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10735 if (IS_ELF
&& fixP
->fx_addsy
)
10736 switch (fixP
->fx_r_type
)
10738 case BFD_RELOC_386_PLT32
:
10739 case BFD_RELOC_X86_64_PLT32
:
10740 /* Make the jump instruction point to the address of the operand.
10741 At runtime we merely add the offset to the actual PLT entry.
10742 NB: Subtract the offset size only for jump instructions. */
10743 if (fixP
->fx_pcrel
)
10747 case BFD_RELOC_386_TLS_GD
:
10748 case BFD_RELOC_386_TLS_LDM
:
10749 case BFD_RELOC_386_TLS_IE_32
:
10750 case BFD_RELOC_386_TLS_IE
:
10751 case BFD_RELOC_386_TLS_GOTIE
:
10752 case BFD_RELOC_386_TLS_GOTDESC
:
10753 case BFD_RELOC_X86_64_TLSGD
:
10754 case BFD_RELOC_X86_64_TLSLD
:
10755 case BFD_RELOC_X86_64_GOTTPOFF
:
10756 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
10757 value
= 0; /* Fully resolved at runtime. No addend. */
10759 case BFD_RELOC_386_TLS_LE
:
10760 case BFD_RELOC_386_TLS_LDO_32
:
10761 case BFD_RELOC_386_TLS_LE_32
:
10762 case BFD_RELOC_X86_64_DTPOFF32
:
10763 case BFD_RELOC_X86_64_DTPOFF64
:
10764 case BFD_RELOC_X86_64_TPOFF32
:
10765 case BFD_RELOC_X86_64_TPOFF64
:
10766 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
10769 case BFD_RELOC_386_TLS_DESC_CALL
:
10770 case BFD_RELOC_X86_64_TLSDESC_CALL
:
10771 value
= 0; /* Fully resolved at runtime. No addend. */
10772 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
10776 case BFD_RELOC_VTABLE_INHERIT
:
10777 case BFD_RELOC_VTABLE_ENTRY
:
10784 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
10786 #endif /* !defined (TE_Mach) */
10788 /* Are we finished with this relocation now? */
10789 if (fixP
->fx_addsy
== NULL
)
10791 #if defined (OBJ_COFF) && defined (TE_PE)
10792 else if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
10795 /* Remember value for tc_gen_reloc. */
10796 fixP
->fx_addnumber
= value
;
10797 /* Clear out the frag for now. */
10801 else if (use_rela_relocations
)
10803 fixP
->fx_no_overflow
= 1;
10804 /* Remember value for tc_gen_reloc. */
10805 fixP
->fx_addnumber
= value
;
10809 md_number_to_chars (p
, value
, fixP
->fx_size
);
10813 md_atof (int type
, char *litP
, int *sizeP
)
10815 /* This outputs the LITTLENUMs in REVERSE order;
10816 in accord with the bigendian 386. */
10817 return ieee_md_atof (type
, litP
, sizeP
, FALSE
);
10820 static char output_invalid_buf
[sizeof (unsigned char) * 2 + 6];
10823 output_invalid (int c
)
10826 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
10829 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
10830 "(0x%x)", (unsigned char) c
);
10831 return output_invalid_buf
;
10834 /* REG_STRING starts *before* REGISTER_PREFIX. */
10836 static const reg_entry
*
10837 parse_real_register (char *reg_string
, char **end_op
)
10839 char *s
= reg_string
;
10841 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
10842 const reg_entry
*r
;
10844 /* Skip possible REGISTER_PREFIX and possible whitespace. */
10845 if (*s
== REGISTER_PREFIX
)
10848 if (is_space_char (*s
))
10851 p
= reg_name_given
;
10852 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
10854 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
10855 return (const reg_entry
*) NULL
;
10859 /* For naked regs, make sure that we are not dealing with an identifier.
10860 This prevents confusing an identifier like `eax_var' with register
10862 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
10863 return (const reg_entry
*) NULL
;
10867 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
10869 /* Handle floating point regs, allowing spaces in the (i) part. */
10870 if (r
== i386_regtab
/* %st is first entry of table */)
10872 if (!cpu_arch_flags
.bitfield
.cpu8087
10873 && !cpu_arch_flags
.bitfield
.cpu287
10874 && !cpu_arch_flags
.bitfield
.cpu387
)
10875 return (const reg_entry
*) NULL
;
10877 if (is_space_char (*s
))
10882 if (is_space_char (*s
))
10884 if (*s
>= '0' && *s
<= '7')
10886 int fpr
= *s
- '0';
10888 if (is_space_char (*s
))
10893 r
= (const reg_entry
*) hash_find (reg_hash
, "st(0)");
10898 /* We have "%st(" then garbage. */
10899 return (const reg_entry
*) NULL
;
10903 if (r
== NULL
|| allow_pseudo_reg
)
10906 if (operand_type_all_zero (&r
->reg_type
))
10907 return (const reg_entry
*) NULL
;
10909 if ((r
->reg_type
.bitfield
.dword
10910 || (r
->reg_type
.bitfield
.sreg
&& r
->reg_num
> 3)
10911 || r
->reg_type
.bitfield
.control
10912 || r
->reg_type
.bitfield
.debug
10913 || r
->reg_type
.bitfield
.test
)
10914 && !cpu_arch_flags
.bitfield
.cpui386
)
10915 return (const reg_entry
*) NULL
;
10917 if (r
->reg_type
.bitfield
.regmmx
&& !cpu_arch_flags
.bitfield
.cpummx
)
10918 return (const reg_entry
*) NULL
;
10920 if (!cpu_arch_flags
.bitfield
.cpuavx512f
)
10922 if (r
->reg_type
.bitfield
.zmmword
|| r
->reg_type
.bitfield
.regmask
)
10923 return (const reg_entry
*) NULL
;
10925 if (!cpu_arch_flags
.bitfield
.cpuavx
)
10927 if (r
->reg_type
.bitfield
.ymmword
)
10928 return (const reg_entry
*) NULL
;
10930 if (!cpu_arch_flags
.bitfield
.cpusse
&& r
->reg_type
.bitfield
.xmmword
)
10931 return (const reg_entry
*) NULL
;
10935 if (r
->reg_type
.bitfield
.regbnd
&& !cpu_arch_flags
.bitfield
.cpumpx
)
10936 return (const reg_entry
*) NULL
;
10938 /* Don't allow fake index register unless allow_index_reg isn't 0. */
10939 if (!allow_index_reg
&& r
->reg_num
== RegIZ
)
10940 return (const reg_entry
*) NULL
;
10942 /* Upper 16 vector registers are only available with VREX in 64bit
10943 mode, and require EVEX encoding. */
10944 if (r
->reg_flags
& RegVRex
)
10946 if (!cpu_arch_flags
.bitfield
.cpuavx512f
10947 || flag_code
!= CODE_64BIT
)
10948 return (const reg_entry
*) NULL
;
10950 i
.vec_encoding
= vex_encoding_evex
;
10953 if (((r
->reg_flags
& (RegRex64
| RegRex
)) || r
->reg_type
.bitfield
.qword
)
10954 && (!cpu_arch_flags
.bitfield
.cpulm
|| !r
->reg_type
.bitfield
.control
)
10955 && flag_code
!= CODE_64BIT
)
10956 return (const reg_entry
*) NULL
;
10958 if (r
->reg_type
.bitfield
.sreg
&& r
->reg_num
== RegFlat
&& !intel_syntax
)
10959 return (const reg_entry
*) NULL
;
10964 /* REG_STRING starts *before* REGISTER_PREFIX. */
10966 static const reg_entry
*
10967 parse_register (char *reg_string
, char **end_op
)
10969 const reg_entry
*r
;
10971 if (*reg_string
== REGISTER_PREFIX
|| allow_naked_reg
)
10972 r
= parse_real_register (reg_string
, end_op
);
10977 char *save
= input_line_pointer
;
10981 input_line_pointer
= reg_string
;
10982 c
= get_symbol_name (®_string
);
10983 symbolP
= symbol_find (reg_string
);
10984 if (symbolP
&& S_GET_SEGMENT (symbolP
) == reg_section
)
10986 const expressionS
*e
= symbol_get_value_expression (symbolP
);
10988 know (e
->X_op
== O_register
);
10989 know (e
->X_add_number
>= 0
10990 && (valueT
) e
->X_add_number
< i386_regtab_size
);
10991 r
= i386_regtab
+ e
->X_add_number
;
10992 if ((r
->reg_flags
& RegVRex
))
10993 i
.vec_encoding
= vex_encoding_evex
;
10994 *end_op
= input_line_pointer
;
10996 *input_line_pointer
= c
;
10997 input_line_pointer
= save
;
11003 i386_parse_name (char *name
, expressionS
*e
, char *nextcharP
)
11005 const reg_entry
*r
;
11006 char *end
= input_line_pointer
;
11009 r
= parse_register (name
, &input_line_pointer
);
11010 if (r
&& end
<= input_line_pointer
)
11012 *nextcharP
= *input_line_pointer
;
11013 *input_line_pointer
= 0;
11014 e
->X_op
= O_register
;
11015 e
->X_add_number
= r
- i386_regtab
;
11018 input_line_pointer
= end
;
11020 return intel_syntax
? i386_intel_parse_name (name
, e
) : 0;
11024 md_operand (expressionS
*e
)
11027 const reg_entry
*r
;
11029 switch (*input_line_pointer
)
11031 case REGISTER_PREFIX
:
11032 r
= parse_real_register (input_line_pointer
, &end
);
11035 e
->X_op
= O_register
;
11036 e
->X_add_number
= r
- i386_regtab
;
11037 input_line_pointer
= end
;
11042 gas_assert (intel_syntax
);
11043 end
= input_line_pointer
++;
11045 if (*input_line_pointer
== ']')
11047 ++input_line_pointer
;
11048 e
->X_op_symbol
= make_expr_symbol (e
);
11049 e
->X_add_symbol
= NULL
;
11050 e
->X_add_number
= 0;
11055 e
->X_op
= O_absent
;
11056 input_line_pointer
= end
;
11063 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11064 const char *md_shortopts
= "kVQ:sqnO::";
11066 const char *md_shortopts
= "qnO::";
11069 #define OPTION_32 (OPTION_MD_BASE + 0)
11070 #define OPTION_64 (OPTION_MD_BASE + 1)
11071 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
11072 #define OPTION_MARCH (OPTION_MD_BASE + 3)
11073 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
11074 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
11075 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
11076 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
11077 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
11078 #define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 9)
11079 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
11080 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
11081 #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
11082 #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
11083 #define OPTION_X32 (OPTION_MD_BASE + 14)
11084 #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
11085 #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
11086 #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
11087 #define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
11088 #define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
11089 #define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
11090 #define OPTION_MSHARED (OPTION_MD_BASE + 21)
11091 #define OPTION_MAMD64 (OPTION_MD_BASE + 22)
11092 #define OPTION_MINTEL64 (OPTION_MD_BASE + 23)
11093 #define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24)
11094 #define OPTION_X86_USED_NOTE (OPTION_MD_BASE + 25)
11095 #define OPTION_MVEXWIG (OPTION_MD_BASE + 26)
11097 struct option md_longopts
[] =
11099 {"32", no_argument
, NULL
, OPTION_32
},
11100 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
11101 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
11102 {"64", no_argument
, NULL
, OPTION_64
},
11104 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11105 {"x32", no_argument
, NULL
, OPTION_X32
},
11106 {"mshared", no_argument
, NULL
, OPTION_MSHARED
},
11107 {"mx86-used-note", required_argument
, NULL
, OPTION_X86_USED_NOTE
},
11109 {"divide", no_argument
, NULL
, OPTION_DIVIDE
},
11110 {"march", required_argument
, NULL
, OPTION_MARCH
},
11111 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
11112 {"mmnemonic", required_argument
, NULL
, OPTION_MMNEMONIC
},
11113 {"msyntax", required_argument
, NULL
, OPTION_MSYNTAX
},
11114 {"mindex-reg", no_argument
, NULL
, OPTION_MINDEX_REG
},
11115 {"mnaked-reg", no_argument
, NULL
, OPTION_MNAKED_REG
},
11116 {"msse2avx", no_argument
, NULL
, OPTION_MSSE2AVX
},
11117 {"msse-check", required_argument
, NULL
, OPTION_MSSE_CHECK
},
11118 {"moperand-check", required_argument
, NULL
, OPTION_MOPERAND_CHECK
},
11119 {"mavxscalar", required_argument
, NULL
, OPTION_MAVXSCALAR
},
11120 {"mvexwig", required_argument
, NULL
, OPTION_MVEXWIG
},
11121 {"madd-bnd-prefix", no_argument
, NULL
, OPTION_MADD_BND_PREFIX
},
11122 {"mevexlig", required_argument
, NULL
, OPTION_MEVEXLIG
},
11123 {"mevexwig", required_argument
, NULL
, OPTION_MEVEXWIG
},
11124 # if defined (TE_PE) || defined (TE_PEP)
11125 {"mbig-obj", no_argument
, NULL
, OPTION_MBIG_OBJ
},
11127 {"momit-lock-prefix", required_argument
, NULL
, OPTION_MOMIT_LOCK_PREFIX
},
11128 {"mfence-as-lock-add", required_argument
, NULL
, OPTION_MFENCE_AS_LOCK_ADD
},
11129 {"mrelax-relocations", required_argument
, NULL
, OPTION_MRELAX_RELOCATIONS
},
11130 {"mevexrcig", required_argument
, NULL
, OPTION_MEVEXRCIG
},
11131 {"mamd64", no_argument
, NULL
, OPTION_MAMD64
},
11132 {"mintel64", no_argument
, NULL
, OPTION_MINTEL64
},
11133 {NULL
, no_argument
, NULL
, 0}
11135 size_t md_longopts_size
= sizeof (md_longopts
);
11138 md_parse_option (int c
, const char *arg
)
11141 char *arch
, *next
, *saved
;
11146 optimize_align_code
= 0;
11150 quiet_warnings
= 1;
11153 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11154 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
11155 should be emitted or not. FIXME: Not implemented. */
11157 if ((arg
[0] != 'y' && arg
[0] != 'n') || arg
[1])
11161 /* -V: SVR4 argument to print version ID. */
11163 print_version_id ();
11166 /* -k: Ignore for FreeBSD compatibility. */
11171 /* -s: On i386 Solaris, this tells the native assembler to use
11172 .stab instead of .stab.excl. We always use .stab anyhow. */
11175 case OPTION_MSHARED
:
11179 case OPTION_X86_USED_NOTE
:
11180 if (strcasecmp (arg
, "yes") == 0)
11182 else if (strcasecmp (arg
, "no") == 0)
11185 as_fatal (_("invalid -mx86-used-note= option: `%s'"), arg
);
11190 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
11191 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
11194 const char **list
, **l
;
11196 list
= bfd_target_list ();
11197 for (l
= list
; *l
!= NULL
; l
++)
11198 if (CONST_STRNEQ (*l
, "elf64-x86-64")
11199 || strcmp (*l
, "coff-x86-64") == 0
11200 || strcmp (*l
, "pe-x86-64") == 0
11201 || strcmp (*l
, "pei-x86-64") == 0
11202 || strcmp (*l
, "mach-o-x86-64") == 0)
11204 default_arch
= "x86_64";
11208 as_fatal (_("no compiled in support for x86_64"));
11214 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11218 const char **list
, **l
;
11220 list
= bfd_target_list ();
11221 for (l
= list
; *l
!= NULL
; l
++)
11222 if (CONST_STRNEQ (*l
, "elf32-x86-64"))
11224 default_arch
= "x86_64:32";
11228 as_fatal (_("no compiled in support for 32bit x86_64"));
11232 as_fatal (_("32bit x86_64 is only supported for ELF"));
11237 default_arch
= "i386";
11240 case OPTION_DIVIDE
:
11241 #ifdef SVR4_COMMENT_CHARS
11246 n
= XNEWVEC (char, strlen (i386_comment_chars
) + 1);
11248 for (s
= i386_comment_chars
; *s
!= '\0'; s
++)
11252 i386_comment_chars
= n
;
11258 saved
= xstrdup (arg
);
11260 /* Allow -march=+nosse. */
11266 as_fatal (_("invalid -march= option: `%s'"), arg
);
11267 next
= strchr (arch
, '+');
11270 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
11272 if (strcmp (arch
, cpu_arch
[j
].name
) == 0)
11275 if (! cpu_arch
[j
].flags
.bitfield
.cpui386
)
11278 cpu_arch_name
= cpu_arch
[j
].name
;
11279 cpu_sub_arch_name
= NULL
;
11280 cpu_arch_flags
= cpu_arch
[j
].flags
;
11281 cpu_arch_isa
= cpu_arch
[j
].type
;
11282 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
11283 if (!cpu_arch_tune_set
)
11285 cpu_arch_tune
= cpu_arch_isa
;
11286 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
11290 else if (*cpu_arch
[j
].name
== '.'
11291 && strcmp (arch
, cpu_arch
[j
].name
+ 1) == 0)
11293 /* ISA extension. */
11294 i386_cpu_flags flags
;
11296 flags
= cpu_flags_or (cpu_arch_flags
,
11297 cpu_arch
[j
].flags
);
11299 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
11301 if (cpu_sub_arch_name
)
11303 char *name
= cpu_sub_arch_name
;
11304 cpu_sub_arch_name
= concat (name
,
11306 (const char *) NULL
);
11310 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
11311 cpu_arch_flags
= flags
;
11312 cpu_arch_isa_flags
= flags
;
11316 = cpu_flags_or (cpu_arch_isa_flags
,
11317 cpu_arch
[j
].flags
);
11322 if (j
>= ARRAY_SIZE (cpu_arch
))
11324 /* Disable an ISA extension. */
11325 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
11326 if (strcmp (arch
, cpu_noarch
[j
].name
) == 0)
11328 i386_cpu_flags flags
;
11330 flags
= cpu_flags_and_not (cpu_arch_flags
,
11331 cpu_noarch
[j
].flags
);
11332 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
11334 if (cpu_sub_arch_name
)
11336 char *name
= cpu_sub_arch_name
;
11337 cpu_sub_arch_name
= concat (arch
,
11338 (const char *) NULL
);
11342 cpu_sub_arch_name
= xstrdup (arch
);
11343 cpu_arch_flags
= flags
;
11344 cpu_arch_isa_flags
= flags
;
11349 if (j
>= ARRAY_SIZE (cpu_noarch
))
11350 j
= ARRAY_SIZE (cpu_arch
);
11353 if (j
>= ARRAY_SIZE (cpu_arch
))
11354 as_fatal (_("invalid -march= option: `%s'"), arg
);
11358 while (next
!= NULL
);
11364 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
11365 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
11367 if (strcmp (arg
, cpu_arch
[j
].name
) == 0)
11369 cpu_arch_tune_set
= 1;
11370 cpu_arch_tune
= cpu_arch
[j
].type
;
11371 cpu_arch_tune_flags
= cpu_arch
[j
].flags
;
11375 if (j
>= ARRAY_SIZE (cpu_arch
))
11376 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
11379 case OPTION_MMNEMONIC
:
11380 if (strcasecmp (arg
, "att") == 0)
11381 intel_mnemonic
= 0;
11382 else if (strcasecmp (arg
, "intel") == 0)
11383 intel_mnemonic
= 1;
11385 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg
);
11388 case OPTION_MSYNTAX
:
11389 if (strcasecmp (arg
, "att") == 0)
11391 else if (strcasecmp (arg
, "intel") == 0)
11394 as_fatal (_("invalid -msyntax= option: `%s'"), arg
);
11397 case OPTION_MINDEX_REG
:
11398 allow_index_reg
= 1;
11401 case OPTION_MNAKED_REG
:
11402 allow_naked_reg
= 1;
11405 case OPTION_MSSE2AVX
:
11409 case OPTION_MSSE_CHECK
:
11410 if (strcasecmp (arg
, "error") == 0)
11411 sse_check
= check_error
;
11412 else if (strcasecmp (arg
, "warning") == 0)
11413 sse_check
= check_warning
;
11414 else if (strcasecmp (arg
, "none") == 0)
11415 sse_check
= check_none
;
11417 as_fatal (_("invalid -msse-check= option: `%s'"), arg
);
11420 case OPTION_MOPERAND_CHECK
:
11421 if (strcasecmp (arg
, "error") == 0)
11422 operand_check
= check_error
;
11423 else if (strcasecmp (arg
, "warning") == 0)
11424 operand_check
= check_warning
;
11425 else if (strcasecmp (arg
, "none") == 0)
11426 operand_check
= check_none
;
11428 as_fatal (_("invalid -moperand-check= option: `%s'"), arg
);
11431 case OPTION_MAVXSCALAR
:
11432 if (strcasecmp (arg
, "128") == 0)
11433 avxscalar
= vex128
;
11434 else if (strcasecmp (arg
, "256") == 0)
11435 avxscalar
= vex256
;
11437 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg
);
11440 case OPTION_MVEXWIG
:
11441 if (strcmp (arg
, "0") == 0)
11443 else if (strcmp (arg
, "1") == 0)
11446 as_fatal (_("invalid -mvexwig= option: `%s'"), arg
);
11449 case OPTION_MADD_BND_PREFIX
:
11450 add_bnd_prefix
= 1;
11453 case OPTION_MEVEXLIG
:
11454 if (strcmp (arg
, "128") == 0)
11455 evexlig
= evexl128
;
11456 else if (strcmp (arg
, "256") == 0)
11457 evexlig
= evexl256
;
11458 else if (strcmp (arg
, "512") == 0)
11459 evexlig
= evexl512
;
11461 as_fatal (_("invalid -mevexlig= option: `%s'"), arg
);
11464 case OPTION_MEVEXRCIG
:
11465 if (strcmp (arg
, "rne") == 0)
11467 else if (strcmp (arg
, "rd") == 0)
11469 else if (strcmp (arg
, "ru") == 0)
11471 else if (strcmp (arg
, "rz") == 0)
11474 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg
);
11477 case OPTION_MEVEXWIG
:
11478 if (strcmp (arg
, "0") == 0)
11480 else if (strcmp (arg
, "1") == 0)
11483 as_fatal (_("invalid -mevexwig= option: `%s'"), arg
);
11486 # if defined (TE_PE) || defined (TE_PEP)
11487 case OPTION_MBIG_OBJ
:
11492 case OPTION_MOMIT_LOCK_PREFIX
:
11493 if (strcasecmp (arg
, "yes") == 0)
11494 omit_lock_prefix
= 1;
11495 else if (strcasecmp (arg
, "no") == 0)
11496 omit_lock_prefix
= 0;
11498 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg
);
11501 case OPTION_MFENCE_AS_LOCK_ADD
:
11502 if (strcasecmp (arg
, "yes") == 0)
11504 else if (strcasecmp (arg
, "no") == 0)
11507 as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg
);
11510 case OPTION_MRELAX_RELOCATIONS
:
11511 if (strcasecmp (arg
, "yes") == 0)
11512 generate_relax_relocations
= 1;
11513 else if (strcasecmp (arg
, "no") == 0)
11514 generate_relax_relocations
= 0;
11516 as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg
);
11519 case OPTION_MAMD64
:
11523 case OPTION_MINTEL64
:
11531 /* Turn off -Os. */
11532 optimize_for_space
= 0;
11534 else if (*arg
== 's')
11536 optimize_for_space
= 1;
11537 /* Turn on all encoding optimizations. */
11538 optimize
= INT_MAX
;
11542 optimize
= atoi (arg
);
11543 /* Turn off -Os. */
11544 optimize_for_space
= 0;
11554 #define MESSAGE_TEMPLATE \
11558 output_message (FILE *stream
, char *p
, char *message
, char *start
,
11559 int *left_p
, const char *name
, int len
)
11561 int size
= sizeof (MESSAGE_TEMPLATE
);
11562 int left
= *left_p
;
11564 /* Reserve 2 spaces for ", " or ",\0" */
11567 /* Check if there is any room. */
11575 p
= mempcpy (p
, name
, len
);
11579 /* Output the current message now and start a new one. */
11582 fprintf (stream
, "%s\n", message
);
11584 left
= size
- (start
- message
) - len
- 2;
11586 gas_assert (left
>= 0);
11588 p
= mempcpy (p
, name
, len
);
11596 show_arch (FILE *stream
, int ext
, int check
)
11598 static char message
[] = MESSAGE_TEMPLATE
;
11599 char *start
= message
+ 27;
11601 int size
= sizeof (MESSAGE_TEMPLATE
);
11608 left
= size
- (start
- message
);
11609 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
11611 /* Should it be skipped? */
11612 if (cpu_arch
[j
].skip
)
11615 name
= cpu_arch
[j
].name
;
11616 len
= cpu_arch
[j
].len
;
11619 /* It is an extension. Skip if we aren't asked to show it. */
11630 /* It is an processor. Skip if we show only extension. */
11633 else if (check
&& ! cpu_arch
[j
].flags
.bitfield
.cpui386
)
11635 /* It is an impossible processor - skip. */
11639 p
= output_message (stream
, p
, message
, start
, &left
, name
, len
);
11642 /* Display disabled extensions. */
11644 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
11646 name
= cpu_noarch
[j
].name
;
11647 len
= cpu_noarch
[j
].len
;
11648 p
= output_message (stream
, p
, message
, start
, &left
, name
,
11653 fprintf (stream
, "%s\n", message
);
11657 md_show_usage (FILE *stream
)
11659 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11660 fprintf (stream
, _("\
11661 -Qy, -Qn ignored\n\
11662 -V print assembler version number\n\
11665 fprintf (stream
, _("\
11666 -n Do not optimize code alignment\n\
11667 -q quieten some warnings\n"));
11668 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11669 fprintf (stream
, _("\
11672 #if defined BFD64 && (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
11673 || defined (TE_PE) || defined (TE_PEP))
11674 fprintf (stream
, _("\
11675 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
11677 #ifdef SVR4_COMMENT_CHARS
11678 fprintf (stream
, _("\
11679 --divide do not treat `/' as a comment character\n"));
11681 fprintf (stream
, _("\
11682 --divide ignored\n"));
11684 fprintf (stream
, _("\
11685 -march=CPU[,+EXTENSION...]\n\
11686 generate code for CPU and EXTENSION, CPU is one of:\n"));
11687 show_arch (stream
, 0, 1);
11688 fprintf (stream
, _("\
11689 EXTENSION is combination of:\n"));
11690 show_arch (stream
, 1, 0);
11691 fprintf (stream
, _("\
11692 -mtune=CPU optimize for CPU, CPU is one of:\n"));
11693 show_arch (stream
, 0, 0);
11694 fprintf (stream
, _("\
11695 -msse2avx encode SSE instructions with VEX prefix\n"));
11696 fprintf (stream
, _("\
11697 -msse-check=[none|error|warning] (default: warning)\n\
11698 check SSE instructions\n"));
11699 fprintf (stream
, _("\
11700 -moperand-check=[none|error|warning] (default: warning)\n\
11701 check operand combinations for validity\n"));
11702 fprintf (stream
, _("\
11703 -mavxscalar=[128|256] (default: 128)\n\
11704 encode scalar AVX instructions with specific vector\n\
11706 fprintf (stream
, _("\
11707 -mvexwig=[0|1] (default: 0)\n\
11708 encode VEX instructions with specific VEX.W value\n\
11709 for VEX.W bit ignored instructions\n"));
11710 fprintf (stream
, _("\
11711 -mevexlig=[128|256|512] (default: 128)\n\
11712 encode scalar EVEX instructions with specific vector\n\
11714 fprintf (stream
, _("\
11715 -mevexwig=[0|1] (default: 0)\n\
11716 encode EVEX instructions with specific EVEX.W value\n\
11717 for EVEX.W bit ignored instructions\n"));
11718 fprintf (stream
, _("\
11719 -mevexrcig=[rne|rd|ru|rz] (default: rne)\n\
11720 encode EVEX instructions with specific EVEX.RC value\n\
11721 for SAE-only ignored instructions\n"));
11722 fprintf (stream
, _("\
11723 -mmnemonic=[att|intel] "));
11724 if (SYSV386_COMPAT
)
11725 fprintf (stream
, _("(default: att)\n"));
11727 fprintf (stream
, _("(default: intel)\n"));
11728 fprintf (stream
, _("\
11729 use AT&T/Intel mnemonic\n"));
11730 fprintf (stream
, _("\
11731 -msyntax=[att|intel] (default: att)\n\
11732 use AT&T/Intel syntax\n"));
11733 fprintf (stream
, _("\
11734 -mindex-reg support pseudo index registers\n"));
11735 fprintf (stream
, _("\
11736 -mnaked-reg don't require `%%' prefix for registers\n"));
11737 fprintf (stream
, _("\
11738 -madd-bnd-prefix add BND prefix for all valid branches\n"));
11739 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11740 fprintf (stream
, _("\
11741 -mshared disable branch optimization for shared code\n"));
11742 fprintf (stream
, _("\
11743 -mx86-used-note=[no|yes] "));
11744 if (DEFAULT_X86_USED_NOTE
)
11745 fprintf (stream
, _("(default: yes)\n"));
11747 fprintf (stream
, _("(default: no)\n"));
11748 fprintf (stream
, _("\
11749 generate x86 used ISA and feature properties\n"));
11751 #if defined (TE_PE) || defined (TE_PEP)
11752 fprintf (stream
, _("\
11753 -mbig-obj generate big object files\n"));
11755 fprintf (stream
, _("\
11756 -momit-lock-prefix=[no|yes] (default: no)\n\
11757 strip all lock prefixes\n"));
11758 fprintf (stream
, _("\
11759 -mfence-as-lock-add=[no|yes] (default: no)\n\
11760 encode lfence, mfence and sfence as\n\
11761 lock addl $0x0, (%%{re}sp)\n"));
11762 fprintf (stream
, _("\
11763 -mrelax-relocations=[no|yes] "));
11764 if (DEFAULT_GENERATE_X86_RELAX_RELOCATIONS
)
11765 fprintf (stream
, _("(default: yes)\n"));
11767 fprintf (stream
, _("(default: no)\n"));
11768 fprintf (stream
, _("\
11769 generate relax relocations\n"));
11770 fprintf (stream
, _("\
11771 -mamd64 accept only AMD64 ISA [default]\n"));
11772 fprintf (stream
, _("\
11773 -mintel64 accept only Intel64 ISA\n"));
11776 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
11777 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
11778 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
11780 /* Pick the target format to use. */
11783 i386_target_format (void)
11785 if (!strncmp (default_arch
, "x86_64", 6))
11787 update_code_flag (CODE_64BIT
, 1);
11788 if (default_arch
[6] == '\0')
11789 x86_elf_abi
= X86_64_ABI
;
11791 x86_elf_abi
= X86_64_X32_ABI
;
11793 else if (!strcmp (default_arch
, "i386"))
11794 update_code_flag (CODE_32BIT
, 1);
11795 else if (!strcmp (default_arch
, "iamcu"))
11797 update_code_flag (CODE_32BIT
, 1);
11798 if (cpu_arch_isa
== PROCESSOR_UNKNOWN
)
11800 static const i386_cpu_flags iamcu_flags
= CPU_IAMCU_FLAGS
;
11801 cpu_arch_name
= "iamcu";
11802 cpu_sub_arch_name
= NULL
;
11803 cpu_arch_flags
= iamcu_flags
;
11804 cpu_arch_isa
= PROCESSOR_IAMCU
;
11805 cpu_arch_isa_flags
= iamcu_flags
;
11806 if (!cpu_arch_tune_set
)
11808 cpu_arch_tune
= cpu_arch_isa
;
11809 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
11812 else if (cpu_arch_isa
!= PROCESSOR_IAMCU
)
11813 as_fatal (_("Intel MCU doesn't support `%s' architecture"),
11817 as_fatal (_("unknown architecture"));
11819 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
11820 cpu_arch_isa_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
11821 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
11822 cpu_arch_tune_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
11824 switch (OUTPUT_FLAVOR
)
11826 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
11827 case bfd_target_aout_flavour
:
11828 return AOUT_TARGET_FORMAT
;
11830 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
11831 # if defined (TE_PE) || defined (TE_PEP)
11832 case bfd_target_coff_flavour
:
11833 if (flag_code
== CODE_64BIT
)
11834 return use_big_obj
? "pe-bigobj-x86-64" : "pe-x86-64";
11837 # elif defined (TE_GO32)
11838 case bfd_target_coff_flavour
:
11839 return "coff-go32";
11841 case bfd_target_coff_flavour
:
11842 return "coff-i386";
11845 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
11846 case bfd_target_elf_flavour
:
11848 const char *format
;
11850 switch (x86_elf_abi
)
11853 format
= ELF_TARGET_FORMAT
;
11856 use_rela_relocations
= 1;
11858 format
= ELF_TARGET_FORMAT64
;
11860 case X86_64_X32_ABI
:
11861 use_rela_relocations
= 1;
11863 disallow_64bit_reloc
= 1;
11864 format
= ELF_TARGET_FORMAT32
;
11867 if (cpu_arch_isa
== PROCESSOR_L1OM
)
11869 if (x86_elf_abi
!= X86_64_ABI
)
11870 as_fatal (_("Intel L1OM is 64bit only"));
11871 return ELF_TARGET_L1OM_FORMAT
;
11873 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
11875 if (x86_elf_abi
!= X86_64_ABI
)
11876 as_fatal (_("Intel K1OM is 64bit only"));
11877 return ELF_TARGET_K1OM_FORMAT
;
11879 else if (cpu_arch_isa
== PROCESSOR_IAMCU
)
11881 if (x86_elf_abi
!= I386_ABI
)
11882 as_fatal (_("Intel MCU is 32bit only"));
11883 return ELF_TARGET_IAMCU_FORMAT
;
11889 #if defined (OBJ_MACH_O)
11890 case bfd_target_mach_o_flavour
:
11891 if (flag_code
== CODE_64BIT
)
11893 use_rela_relocations
= 1;
11895 return "mach-o-x86-64";
11898 return "mach-o-i386";
11906 #endif /* OBJ_MAYBE_ more than one */
11909 md_undefined_symbol (char *name
)
11911 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
11912 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
11913 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
11914 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
11918 if (symbol_find (name
))
11919 as_bad (_("GOT already in symbol table"));
11920 GOT_symbol
= symbol_new (name
, undefined_section
,
11921 (valueT
) 0, &zero_address_frag
);
11928 /* Round up a section size to the appropriate boundary. */
11931 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
11933 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
11934 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
11936 /* For a.out, force the section size to be aligned. If we don't do
11937 this, BFD will align it for us, but it will not write out the
11938 final bytes of the section. This may be a bug in BFD, but it is
11939 easier to fix it here since that is how the other a.out targets
11943 align
= bfd_section_alignment (segment
);
11944 size
= ((size
+ (1 << align
) - 1) & (-((valueT
) 1 << align
)));
11951 /* On the i386, PC-relative offsets are relative to the start of the
11952 next instruction. That is, the address of the offset, plus its
11953 size, since the offset is always the last part of the insn. */
11956 md_pcrel_from (fixS
*fixP
)
11958 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
11964 s_bss (int ignore ATTRIBUTE_UNUSED
)
11968 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11970 obj_elf_section_change_hook ();
11972 temp
= get_absolute_expression ();
11973 subseg_set (bss_section
, (subsegT
) temp
);
11974 demand_empty_rest_of_line ();
11980 i386_validate_fix (fixS
*fixp
)
11982 if (fixp
->fx_subsy
)
11984 if (fixp
->fx_subsy
== GOT_symbol
)
11986 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
11990 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11991 if (fixp
->fx_tcbit2
)
11992 fixp
->fx_r_type
= (fixp
->fx_tcbit
11993 ? BFD_RELOC_X86_64_REX_GOTPCRELX
11994 : BFD_RELOC_X86_64_GOTPCRELX
);
11997 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
12002 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
12004 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
12006 fixp
->fx_subsy
= 0;
12009 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12010 else if (!object_64bit
)
12012 if (fixp
->fx_r_type
== BFD_RELOC_386_GOT32
12013 && fixp
->fx_tcbit2
)
12014 fixp
->fx_r_type
= BFD_RELOC_386_GOT32X
;
12020 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
12023 bfd_reloc_code_real_type code
;
12025 switch (fixp
->fx_r_type
)
12027 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12028 case BFD_RELOC_SIZE32
:
12029 case BFD_RELOC_SIZE64
:
12030 if (S_IS_DEFINED (fixp
->fx_addsy
)
12031 && !S_IS_EXTERNAL (fixp
->fx_addsy
))
12033 /* Resolve size relocation against local symbol to size of
12034 the symbol plus addend. */
12035 valueT value
= S_GET_SIZE (fixp
->fx_addsy
) + fixp
->fx_offset
;
12036 if (fixp
->fx_r_type
== BFD_RELOC_SIZE32
12037 && !fits_in_unsigned_long (value
))
12038 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
12039 _("symbol size computation overflow"));
12040 fixp
->fx_addsy
= NULL
;
12041 fixp
->fx_subsy
= NULL
;
12042 md_apply_fix (fixp
, (valueT
*) &value
, NULL
);
12046 /* Fall through. */
12048 case BFD_RELOC_X86_64_PLT32
:
12049 case BFD_RELOC_X86_64_GOT32
:
12050 case BFD_RELOC_X86_64_GOTPCREL
:
12051 case BFD_RELOC_X86_64_GOTPCRELX
:
12052 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
12053 case BFD_RELOC_386_PLT32
:
12054 case BFD_RELOC_386_GOT32
:
12055 case BFD_RELOC_386_GOT32X
:
12056 case BFD_RELOC_386_GOTOFF
:
12057 case BFD_RELOC_386_GOTPC
:
12058 case BFD_RELOC_386_TLS_GD
:
12059 case BFD_RELOC_386_TLS_LDM
:
12060 case BFD_RELOC_386_TLS_LDO_32
:
12061 case BFD_RELOC_386_TLS_IE_32
:
12062 case BFD_RELOC_386_TLS_IE
:
12063 case BFD_RELOC_386_TLS_GOTIE
:
12064 case BFD_RELOC_386_TLS_LE_32
:
12065 case BFD_RELOC_386_TLS_LE
:
12066 case BFD_RELOC_386_TLS_GOTDESC
:
12067 case BFD_RELOC_386_TLS_DESC_CALL
:
12068 case BFD_RELOC_X86_64_TLSGD
:
12069 case BFD_RELOC_X86_64_TLSLD
:
12070 case BFD_RELOC_X86_64_DTPOFF32
:
12071 case BFD_RELOC_X86_64_DTPOFF64
:
12072 case BFD_RELOC_X86_64_GOTTPOFF
:
12073 case BFD_RELOC_X86_64_TPOFF32
:
12074 case BFD_RELOC_X86_64_TPOFF64
:
12075 case BFD_RELOC_X86_64_GOTOFF64
:
12076 case BFD_RELOC_X86_64_GOTPC32
:
12077 case BFD_RELOC_X86_64_GOT64
:
12078 case BFD_RELOC_X86_64_GOTPCREL64
:
12079 case BFD_RELOC_X86_64_GOTPC64
:
12080 case BFD_RELOC_X86_64_GOTPLT64
:
12081 case BFD_RELOC_X86_64_PLTOFF64
:
12082 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
12083 case BFD_RELOC_X86_64_TLSDESC_CALL
:
12084 case BFD_RELOC_RVA
:
12085 case BFD_RELOC_VTABLE_ENTRY
:
12086 case BFD_RELOC_VTABLE_INHERIT
:
12088 case BFD_RELOC_32_SECREL
:
12090 code
= fixp
->fx_r_type
;
12092 case BFD_RELOC_X86_64_32S
:
12093 if (!fixp
->fx_pcrel
)
12095 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
12096 code
= fixp
->fx_r_type
;
12099 /* Fall through. */
12101 if (fixp
->fx_pcrel
)
12103 switch (fixp
->fx_size
)
12106 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
12107 _("can not do %d byte pc-relative relocation"),
12109 code
= BFD_RELOC_32_PCREL
;
12111 case 1: code
= BFD_RELOC_8_PCREL
; break;
12112 case 2: code
= BFD_RELOC_16_PCREL
; break;
12113 case 4: code
= BFD_RELOC_32_PCREL
; break;
12115 case 8: code
= BFD_RELOC_64_PCREL
; break;
12121 switch (fixp
->fx_size
)
12124 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
12125 _("can not do %d byte relocation"),
12127 code
= BFD_RELOC_32
;
12129 case 1: code
= BFD_RELOC_8
; break;
12130 case 2: code
= BFD_RELOC_16
; break;
12131 case 4: code
= BFD_RELOC_32
; break;
12133 case 8: code
= BFD_RELOC_64
; break;
12140 if ((code
== BFD_RELOC_32
12141 || code
== BFD_RELOC_32_PCREL
12142 || code
== BFD_RELOC_X86_64_32S
)
12144 && fixp
->fx_addsy
== GOT_symbol
)
12147 code
= BFD_RELOC_386_GOTPC
;
12149 code
= BFD_RELOC_X86_64_GOTPC32
;
12151 if ((code
== BFD_RELOC_64
|| code
== BFD_RELOC_64_PCREL
)
12153 && fixp
->fx_addsy
== GOT_symbol
)
12155 code
= BFD_RELOC_X86_64_GOTPC64
;
12158 rel
= XNEW (arelent
);
12159 rel
->sym_ptr_ptr
= XNEW (asymbol
*);
12160 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
12162 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
12164 if (!use_rela_relocations
)
12166 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
12167 vtable entry to be used in the relocation's section offset. */
12168 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
12169 rel
->address
= fixp
->fx_offset
;
12170 #if defined (OBJ_COFF) && defined (TE_PE)
12171 else if (fixp
->fx_addsy
&& S_IS_WEAK (fixp
->fx_addsy
))
12172 rel
->addend
= fixp
->fx_addnumber
- (S_GET_VALUE (fixp
->fx_addsy
) * 2);
12177 /* Use the rela in 64bit mode. */
12180 if (disallow_64bit_reloc
)
12183 case BFD_RELOC_X86_64_DTPOFF64
:
12184 case BFD_RELOC_X86_64_TPOFF64
:
12185 case BFD_RELOC_64_PCREL
:
12186 case BFD_RELOC_X86_64_GOTOFF64
:
12187 case BFD_RELOC_X86_64_GOT64
:
12188 case BFD_RELOC_X86_64_GOTPCREL64
:
12189 case BFD_RELOC_X86_64_GOTPC64
:
12190 case BFD_RELOC_X86_64_GOTPLT64
:
12191 case BFD_RELOC_X86_64_PLTOFF64
:
12192 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
12193 _("cannot represent relocation type %s in x32 mode"),
12194 bfd_get_reloc_code_name (code
));
12200 if (!fixp
->fx_pcrel
)
12201 rel
->addend
= fixp
->fx_offset
;
12205 case BFD_RELOC_X86_64_PLT32
:
12206 case BFD_RELOC_X86_64_GOT32
:
12207 case BFD_RELOC_X86_64_GOTPCREL
:
12208 case BFD_RELOC_X86_64_GOTPCRELX
:
12209 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
12210 case BFD_RELOC_X86_64_TLSGD
:
12211 case BFD_RELOC_X86_64_TLSLD
:
12212 case BFD_RELOC_X86_64_GOTTPOFF
:
12213 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
12214 case BFD_RELOC_X86_64_TLSDESC_CALL
:
12215 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
12218 rel
->addend
= (section
->vma
12220 + fixp
->fx_addnumber
12221 + md_pcrel_from (fixp
));
12226 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
12227 if (rel
->howto
== NULL
)
12229 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
12230 _("cannot represent relocation type %s"),
12231 bfd_get_reloc_code_name (code
));
12232 /* Set howto to a garbage value so that we can keep going. */
12233 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
12234 gas_assert (rel
->howto
!= NULL
);
12240 #include "tc-i386-intel.c"
12243 tc_x86_parse_to_dw2regnum (expressionS
*exp
)
12245 int saved_naked_reg
;
12246 char saved_register_dot
;
12248 saved_naked_reg
= allow_naked_reg
;
12249 allow_naked_reg
= 1;
12250 saved_register_dot
= register_chars
['.'];
12251 register_chars
['.'] = '.';
12252 allow_pseudo_reg
= 1;
12253 expression_and_evaluate (exp
);
12254 allow_pseudo_reg
= 0;
12255 register_chars
['.'] = saved_register_dot
;
12256 allow_naked_reg
= saved_naked_reg
;
12258 if (exp
->X_op
== O_register
&& exp
->X_add_number
>= 0)
12260 if ((addressT
) exp
->X_add_number
< i386_regtab_size
)
12262 exp
->X_op
= O_constant
;
12263 exp
->X_add_number
= i386_regtab
[exp
->X_add_number
]
12264 .dw2_regnum
[flag_code
>> 1];
12267 exp
->X_op
= O_illegal
;
12272 tc_x86_frame_initial_instructions (void)
12274 static unsigned int sp_regno
[2];
12276 if (!sp_regno
[flag_code
>> 1])
12278 char *saved_input
= input_line_pointer
;
12279 char sp
[][4] = {"esp", "rsp"};
12282 input_line_pointer
= sp
[flag_code
>> 1];
12283 tc_x86_parse_to_dw2regnum (&exp
);
12284 gas_assert (exp
.X_op
== O_constant
);
12285 sp_regno
[flag_code
>> 1] = exp
.X_add_number
;
12286 input_line_pointer
= saved_input
;
12289 cfi_add_CFA_def_cfa (sp_regno
[flag_code
>> 1], -x86_cie_data_alignment
);
12290 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
12294 x86_dwarf2_addr_size (void)
12296 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
12297 if (x86_elf_abi
== X86_64_X32_ABI
)
12300 return bfd_arch_bits_per_address (stdoutput
) / 8;
12304 i386_elf_section_type (const char *str
, size_t len
)
12306 if (flag_code
== CODE_64BIT
12307 && len
== sizeof ("unwind") - 1
12308 && strncmp (str
, "unwind", 6) == 0)
12309 return SHT_X86_64_UNWIND
;
12316 i386_solaris_fix_up_eh_frame (segT sec
)
12318 if (flag_code
== CODE_64BIT
)
12319 elf_section_type (sec
) = SHT_X86_64_UNWIND
;
12325 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
12329 exp
.X_op
= O_secrel
;
12330 exp
.X_add_symbol
= symbol
;
12331 exp
.X_add_number
= 0;
12332 emit_expr (&exp
, size
);
12336 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12337 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
12340 x86_64_section_letter (int letter
, const char **ptr_msg
)
12342 if (flag_code
== CODE_64BIT
)
12345 return SHF_X86_64_LARGE
;
12347 *ptr_msg
= _("bad .section directive: want a,l,w,x,M,S,G,T in string");
12350 *ptr_msg
= _("bad .section directive: want a,w,x,M,S,G,T in string");
12355 x86_64_section_word (char *str
, size_t len
)
12357 if (len
== 5 && flag_code
== CODE_64BIT
&& CONST_STRNEQ (str
, "large"))
12358 return SHF_X86_64_LARGE
;
12364 handle_large_common (int small ATTRIBUTE_UNUSED
)
12366 if (flag_code
!= CODE_64BIT
)
12368 s_comm_internal (0, elf_common_parse
);
12369 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
12373 static segT lbss_section
;
12374 asection
*saved_com_section_ptr
= elf_com_section_ptr
;
12375 asection
*saved_bss_section
= bss_section
;
12377 if (lbss_section
== NULL
)
12379 flagword applicable
;
12380 segT seg
= now_seg
;
12381 subsegT subseg
= now_subseg
;
12383 /* The .lbss section is for local .largecomm symbols. */
12384 lbss_section
= subseg_new (".lbss", 0);
12385 applicable
= bfd_applicable_section_flags (stdoutput
);
12386 bfd_set_section_flags (lbss_section
, applicable
& SEC_ALLOC
);
12387 seg_info (lbss_section
)->bss
= 1;
12389 subseg_set (seg
, subseg
);
12392 elf_com_section_ptr
= &_bfd_elf_large_com_section
;
12393 bss_section
= lbss_section
;
12395 s_comm_internal (0, elf_common_parse
);
12397 elf_com_section_ptr
= saved_com_section_ptr
;
12398 bss_section
= saved_bss_section
;
12401 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */