1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright (C) 1989-2020 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 /* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
23 x86_64 support by Jan Hubicka (jh@suse.cz)
24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
29 #include "safe-ctype.h"
31 #include "dwarf2dbg.h"
32 #include "dw2gencfi.h"
33 #include "elf/x86-64.h"
34 #include "opcodes/i386-init.h"
39 #ifdef HAVE_SYS_PARAM_H
40 #include <sys/param.h>
43 #define INT_MAX (int) (((unsigned) (-1)) >> 1)
47 #ifndef INFER_ADDR_PREFIX
48 #define INFER_ADDR_PREFIX 1
52 #define DEFAULT_ARCH "i386"
57 #define INLINE __inline__
63 /* Prefixes will be emitted in the order defined below.
64 WAIT_PREFIX must be the first prefix since FWAIT is really is an
65 instruction, and so must come before any prefixes.
66 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
67 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
73 #define HLE_PREFIX REP_PREFIX
74 #define BND_PREFIX REP_PREFIX
76 #define REX_PREFIX 6 /* must come last. */
77 #define MAX_PREFIXES 7 /* max prefixes per opcode */
79 /* we define the syntax here (modulo base,index,scale syntax) */
80 #define REGISTER_PREFIX '%'
81 #define IMMEDIATE_PREFIX '$'
82 #define ABSOLUTE_PREFIX '*'
84 /* these are the instruction mnemonic suffixes in AT&T syntax or
85 memory operand size in Intel syntax. */
86 #define WORD_MNEM_SUFFIX 'w'
87 #define BYTE_MNEM_SUFFIX 'b'
88 #define SHORT_MNEM_SUFFIX 's'
89 #define LONG_MNEM_SUFFIX 'l'
90 #define QWORD_MNEM_SUFFIX 'q'
91 /* Intel Syntax. Use a non-ascii letter since since it never appears
93 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
95 #define END_OF_INSN '\0'
97 /* This matches the C -> StaticRounding alias in the opcode table. */
98 #define commutative staticrounding
101 'templates' is for grouping together 'template' structures for opcodes
102 of the same name. This is only used for storing the insns in the grand
103 ole hash table of insns.
104 The templates themselves start at START and range up to (but not including)
109 const insn_template
*start
;
110 const insn_template
*end
;
114 /* 386 operand encoding bytes: see 386 book for details of this. */
117 unsigned int regmem
; /* codes register or memory operand */
118 unsigned int reg
; /* codes register operand (or extended opcode) */
119 unsigned int mode
; /* how to interpret regmem & reg */
123 /* x86-64 extension prefix. */
124 typedef int rex_byte
;
126 /* 386 opcode byte to code indirect addressing. */
135 /* x86 arch names, types and features */
138 const char *name
; /* arch name */
139 unsigned int len
; /* arch string length */
140 enum processor_type type
; /* arch type */
141 i386_cpu_flags flags
; /* cpu feature flags */
142 unsigned int skip
; /* show_arch should skip this. */
146 /* Used to turn off indicated flags. */
149 const char *name
; /* arch name */
150 unsigned int len
; /* arch string length */
151 i386_cpu_flags flags
; /* cpu feature flags */
155 static void update_code_flag (int, int);
156 static void set_code_flag (int);
157 static void set_16bit_gcc_code_flag (int);
158 static void set_intel_syntax (int);
159 static void set_intel_mnemonic (int);
160 static void set_allow_index_reg (int);
161 static void set_check (int);
162 static void set_cpu_arch (int);
164 static void pe_directive_secrel (int);
166 static void signed_cons (int);
167 static char *output_invalid (int c
);
168 static int i386_finalize_immediate (segT
, expressionS
*, i386_operand_type
,
170 static int i386_finalize_displacement (segT
, expressionS
*, i386_operand_type
,
172 static int i386_att_operand (char *);
173 static int i386_intel_operand (char *, int);
174 static int i386_intel_simplify (expressionS
*);
175 static int i386_intel_parse_name (const char *, expressionS
*);
176 static const reg_entry
*parse_register (char *, char **);
177 static char *parse_insn (char *, char *);
178 static char *parse_operands (char *, const char *);
179 static void swap_operands (void);
180 static void swap_2_operands (int, int);
181 static enum flag_code
i386_addressing_mode (void);
182 static void optimize_imm (void);
183 static void optimize_disp (void);
184 static const insn_template
*match_template (char);
185 static int check_string (void);
186 static int process_suffix (void);
187 static int check_byte_reg (void);
188 static int check_long_reg (void);
189 static int check_qword_reg (void);
190 static int check_word_reg (void);
191 static int finalize_imm (void);
192 static int process_operands (void);
193 static const seg_entry
*build_modrm_byte (void);
194 static void output_insn (void);
195 static void output_imm (fragS
*, offsetT
);
196 static void output_disp (fragS
*, offsetT
);
198 static void s_bss (int);
200 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
201 static void handle_large_common (int small ATTRIBUTE_UNUSED
);
203 /* GNU_PROPERTY_X86_ISA_1_USED. */
204 static unsigned int x86_isa_1_used
;
205 /* GNU_PROPERTY_X86_FEATURE_2_USED. */
206 static unsigned int x86_feature_2_used
;
207 /* Generate x86 used ISA and feature properties. */
208 static unsigned int x86_used_note
= DEFAULT_X86_USED_NOTE
;
211 static const char *default_arch
= DEFAULT_ARCH
;
213 /* This struct describes rounding control and SAE in the instruction. */
227 static struct RC_Operation rc_op
;
229 /* The struct describes masking, applied to OPERAND in the instruction.
230 MASK is a pointer to the corresponding mask register. ZEROING tells
231 whether merging or zeroing mask is used. */
232 struct Mask_Operation
234 const reg_entry
*mask
;
235 unsigned int zeroing
;
236 /* The operand where this operation is associated. */
240 static struct Mask_Operation mask_op
;
242 /* The struct describes broadcasting, applied to OPERAND. FACTOR is
244 struct Broadcast_Operation
246 /* Type of broadcast: {1to2}, {1to4}, {1to8}, or {1to16}. */
249 /* Index of broadcasted operand. */
252 /* Number of bytes to broadcast. */
256 static struct Broadcast_Operation broadcast_op
;
261 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
262 unsigned char bytes
[4];
264 /* Destination or source register specifier. */
265 const reg_entry
*register_specifier
;
268 /* 'md_assemble ()' gathers together information and puts it into a
275 const reg_entry
*regs
;
280 operand_size_mismatch
,
281 operand_type_mismatch
,
282 register_type_mismatch
,
283 number_of_operands_mismatch
,
284 invalid_instruction_suffix
,
286 unsupported_with_intel_mnemonic
,
289 invalid_vsib_address
,
290 invalid_vector_register_set
,
291 unsupported_vector_index_register
,
292 unsupported_broadcast
,
295 mask_not_on_destination
,
298 rc_sae_operand_not_last_imm
,
299 invalid_register_operand
,
304 /* TM holds the template for the insn were currently assembling. */
307 /* SUFFIX holds the instruction size suffix for byte, word, dword
308 or qword, if given. */
311 /* OPERANDS gives the number of given operands. */
312 unsigned int operands
;
314 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
315 of given register, displacement, memory operands and immediate
317 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
319 /* TYPES [i] is the type (see above #defines) which tells us how to
320 use OP[i] for the corresponding operand. */
321 i386_operand_type types
[MAX_OPERANDS
];
323 /* Displacement expression, immediate expression, or register for each
325 union i386_op op
[MAX_OPERANDS
];
327 /* Flags for operands. */
328 unsigned int flags
[MAX_OPERANDS
];
329 #define Operand_PCrel 1
330 #define Operand_Mem 2
332 /* Relocation type for operand */
333 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
335 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
336 the base index byte below. */
337 const reg_entry
*base_reg
;
338 const reg_entry
*index_reg
;
339 unsigned int log2_scale_factor
;
341 /* SEG gives the seg_entries of this insn. They are zero unless
342 explicit segment overrides are given. */
343 const seg_entry
*seg
[2];
345 /* Copied first memory operand string, for re-checking. */
348 /* PREFIX holds all the given prefix opcodes (usually null).
349 PREFIXES is the number of prefix opcodes. */
350 unsigned int prefixes
;
351 unsigned char prefix
[MAX_PREFIXES
];
353 /* Register is in low 3 bits of opcode. */
354 bfd_boolean short_form
;
356 /* The operand to a branch insn indicates an absolute branch. */
357 bfd_boolean jumpabsolute
;
359 /* Has MMX register operands. */
360 bfd_boolean has_regmmx
;
362 /* Has XMM register operands. */
363 bfd_boolean has_regxmm
;
365 /* Has YMM register operands. */
366 bfd_boolean has_regymm
;
368 /* Has ZMM register operands. */
369 bfd_boolean has_regzmm
;
371 /* Has GOTPC or TLS relocation. */
372 bfd_boolean has_gotpc_tls_reloc
;
374 /* RM and SIB are the modrm byte and the sib byte where the
375 addressing modes of this insn are encoded. */
382 /* Masking attributes. */
383 struct Mask_Operation
*mask
;
385 /* Rounding control and SAE attributes. */
386 struct RC_Operation
*rounding
;
388 /* Broadcasting attributes. */
389 struct Broadcast_Operation
*broadcast
;
391 /* Compressed disp8*N attribute. */
392 unsigned int memshift
;
394 /* Prefer load or store in encoding. */
397 dir_encoding_default
= 0,
403 /* Prefer 8bit or 32bit displacement in encoding. */
406 disp_encoding_default
= 0,
411 /* Prefer the REX byte in encoding. */
412 bfd_boolean rex_encoding
;
414 /* Disable instruction size optimization. */
415 bfd_boolean no_optimize
;
417 /* How to encode vector instructions. */
420 vex_encoding_default
= 0,
427 const char *rep_prefix
;
430 const char *hle_prefix
;
432 /* Have BND prefix. */
433 const char *bnd_prefix
;
435 /* Have NOTRACK prefix. */
436 const char *notrack_prefix
;
439 enum i386_error error
;
442 typedef struct _i386_insn i386_insn
;
444 /* Link RC type with corresponding string, that'll be looked for in
453 static const struct RC_name RC_NamesTable
[] =
455 { rne
, STRING_COMMA_LEN ("rn-sae") },
456 { rd
, STRING_COMMA_LEN ("rd-sae") },
457 { ru
, STRING_COMMA_LEN ("ru-sae") },
458 { rz
, STRING_COMMA_LEN ("rz-sae") },
459 { saeonly
, STRING_COMMA_LEN ("sae") },
462 /* List of chars besides those in app.c:symbol_chars that can start an
463 operand. Used to prevent the scrubber eating vital white-space. */
464 const char extra_symbol_chars
[] = "*%-([{}"
473 #if (defined (TE_I386AIX) \
474 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
475 && !defined (TE_GNU) \
476 && !defined (TE_LINUX) \
477 && !defined (TE_NACL) \
478 && !defined (TE_FreeBSD) \
479 && !defined (TE_DragonFly) \
480 && !defined (TE_NetBSD)))
481 /* This array holds the chars that always start a comment. If the
482 pre-processor is disabled, these aren't very useful. The option
483 --divide will remove '/' from this list. */
484 const char *i386_comment_chars
= "#/";
485 #define SVR4_COMMENT_CHARS 1
486 #define PREFIX_SEPARATOR '\\'
489 const char *i386_comment_chars
= "#";
490 #define PREFIX_SEPARATOR '/'
493 /* This array holds the chars that only start a comment at the beginning of
494 a line. If the line seems to have the form '# 123 filename'
495 .line and .file directives will appear in the pre-processed output.
496 Note that input_file.c hand checks for '#' at the beginning of the
497 first line of the input file. This is because the compiler outputs
498 #NO_APP at the beginning of its output.
499 Also note that comments started like this one will always work if
500 '/' isn't otherwise defined. */
501 const char line_comment_chars
[] = "#/";
503 const char line_separator_chars
[] = ";";
505 /* Chars that can be used to separate mant from exp in floating point
507 const char EXP_CHARS
[] = "eE";
509 /* Chars that mean this number is a floating point constant
512 const char FLT_CHARS
[] = "fFdDxX";
514 /* Tables for lexical analysis. */
515 static char mnemonic_chars
[256];
516 static char register_chars
[256];
517 static char operand_chars
[256];
518 static char identifier_chars
[256];
519 static char digit_chars
[256];
521 /* Lexical macros. */
522 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
523 #define is_operand_char(x) (operand_chars[(unsigned char) x])
524 #define is_register_char(x) (register_chars[(unsigned char) x])
525 #define is_space_char(x) ((x) == ' ')
526 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
527 #define is_digit_char(x) (digit_chars[(unsigned char) x])
529 /* All non-digit non-letter characters that may occur in an operand. */
530 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
532 /* md_assemble() always leaves the strings it's passed unaltered. To
533 effect this we maintain a stack of saved characters that we've smashed
534 with '\0's (indicating end of strings for various sub-fields of the
535 assembler instruction). */
536 static char save_stack
[32];
537 static char *save_stack_p
;
538 #define END_STRING_AND_SAVE(s) \
539 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
540 #define RESTORE_END_STRING(s) \
541 do { *(s) = *--save_stack_p; } while (0)
543 /* The instruction we're assembling. */
546 /* Possible templates for current insn. */
547 static const templates
*current_templates
;
549 /* Per instruction expressionS buffers: max displacements & immediates. */
550 static expressionS disp_expressions
[MAX_MEMORY_OPERANDS
];
551 static expressionS im_expressions
[MAX_IMMEDIATE_OPERANDS
];
553 /* Current operand we are working on. */
554 static int this_operand
= -1;
556 /* We support four different modes. FLAG_CODE variable is used to distinguish
564 static enum flag_code flag_code
;
565 static unsigned int object_64bit
;
566 static unsigned int disallow_64bit_reloc
;
567 static int use_rela_relocations
= 0;
568 /* __tls_get_addr/___tls_get_addr symbol for TLS. */
569 static const char *tls_get_addr
;
571 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
572 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
573 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
575 /* The ELF ABI to use. */
583 static enum x86_elf_abi x86_elf_abi
= I386_ABI
;
586 #if defined (TE_PE) || defined (TE_PEP)
587 /* Use big object file format. */
588 static int use_big_obj
= 0;
591 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
592 /* 1 if generating code for a shared library. */
593 static int shared
= 0;
596 /* 1 for intel syntax,
598 static int intel_syntax
= 0;
600 static enum x86_64_isa
602 amd64
= 1, /* AMD64 ISA. */
603 intel64
/* Intel64 ISA. */
606 /* 1 for intel mnemonic,
607 0 if att mnemonic. */
608 static int intel_mnemonic
= !SYSV386_COMPAT
;
610 /* 1 if pseudo registers are permitted. */
611 static int allow_pseudo_reg
= 0;
613 /* 1 if register prefix % not required. */
614 static int allow_naked_reg
= 0;
616 /* 1 if the assembler should add BND prefix for all control-transferring
617 instructions supporting it, even if this prefix wasn't specified
619 static int add_bnd_prefix
= 0;
621 /* 1 if pseudo index register, eiz/riz, is allowed . */
622 static int allow_index_reg
= 0;
624 /* 1 if the assembler should ignore LOCK prefix, even if it was
625 specified explicitly. */
626 static int omit_lock_prefix
= 0;
628 /* 1 if the assembler should encode lfence, mfence, and sfence as
629 "lock addl $0, (%{re}sp)". */
630 static int avoid_fence
= 0;
632 /* Type of the previous instruction. */
647 /* 1 if the assembler should generate relax relocations. */
649 static int generate_relax_relocations
650 = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS
;
652 static enum check_kind
658 sse_check
, operand_check
= check_warning
;
660 /* Non-zero if branches should be aligned within power of 2 boundary. */
661 static int align_branch_power
= 0;
663 /* Types of branches to align. */
664 enum align_branch_kind
666 align_branch_none
= 0,
667 align_branch_jcc
= 1,
668 align_branch_fused
= 2,
669 align_branch_jmp
= 3,
670 align_branch_call
= 4,
671 align_branch_indirect
= 5,
675 /* Type bits of branches to align. */
676 enum align_branch_bit
678 align_branch_jcc_bit
= 1 << align_branch_jcc
,
679 align_branch_fused_bit
= 1 << align_branch_fused
,
680 align_branch_jmp_bit
= 1 << align_branch_jmp
,
681 align_branch_call_bit
= 1 << align_branch_call
,
682 align_branch_indirect_bit
= 1 << align_branch_indirect
,
683 align_branch_ret_bit
= 1 << align_branch_ret
686 static unsigned int align_branch
= (align_branch_jcc_bit
687 | align_branch_fused_bit
688 | align_branch_jmp_bit
);
690 /* The maximum padding size for fused jcc. CMP like instruction can
691 be 9 bytes and jcc can be 6 bytes. Leave room just in case for
693 #define MAX_FUSED_JCC_PADDING_SIZE 20
695 /* The maximum number of prefixes added for an instruction. */
696 static unsigned int align_branch_prefix_size
= 5;
699 1. Clear the REX_W bit with register operand if possible.
700 2. Above plus use 128bit vector instruction to clear the full vector
703 static int optimize
= 0;
706 1. Clear the REX_W bit with register operand if possible.
707 2. Above plus use 128bit vector instruction to clear the full vector
709 3. Above plus optimize "test{q,l,w} $imm8,%r{64,32,16}" to
712 static int optimize_for_space
= 0;
714 /* Register prefix used for error message. */
715 static const char *register_prefix
= "%";
717 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
718 leave, push, and pop instructions so that gcc has the same stack
719 frame as in 32 bit mode. */
720 static char stackop_size
= '\0';
722 /* Non-zero to optimize code alignment. */
723 int optimize_align_code
= 1;
725 /* Non-zero to quieten some warnings. */
726 static int quiet_warnings
= 0;
729 static const char *cpu_arch_name
= NULL
;
730 static char *cpu_sub_arch_name
= NULL
;
732 /* CPU feature flags. */
733 static i386_cpu_flags cpu_arch_flags
= CPU_UNKNOWN_FLAGS
;
735 /* If we have selected a cpu we are generating instructions for. */
736 static int cpu_arch_tune_set
= 0;
738 /* Cpu we are generating instructions for. */
739 enum processor_type cpu_arch_tune
= PROCESSOR_UNKNOWN
;
741 /* CPU feature flags of cpu we are generating instructions for. */
742 static i386_cpu_flags cpu_arch_tune_flags
;
744 /* CPU instruction set architecture used. */
745 enum processor_type cpu_arch_isa
= PROCESSOR_UNKNOWN
;
747 /* CPU feature flags of instruction set architecture used. */
748 i386_cpu_flags cpu_arch_isa_flags
;
750 /* If set, conditional jumps are not automatically promoted to handle
751 larger than a byte offset. */
752 static unsigned int no_cond_jump_promotion
= 0;
754 /* Encode SSE instructions with VEX prefix. */
755 static unsigned int sse2avx
;
757 /* Encode scalar AVX instructions with specific vector length. */
764 /* Encode VEX WIG instructions with specific vex.w. */
771 /* Encode scalar EVEX LIG instructions with specific vector length. */
779 /* Encode EVEX WIG instructions with specific evex.w. */
786 /* Value to encode in EVEX RC bits, for SAE-only instructions. */
787 static enum rc_type evexrcig
= rne
;
789 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
790 static symbolS
*GOT_symbol
;
792 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
793 unsigned int x86_dwarf2_return_column
;
795 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
796 int x86_cie_data_alignment
;
798 /* Interface to relax_segment.
799 There are 3 major relax states for 386 jump insns because the
800 different types of jumps add different sizes to frags when we're
801 figuring out what sort of jump to choose to reach a given label.
803 BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING are used to align
804 branches which are handled by md_estimate_size_before_relax() and
805 i386_generic_table_relax_frag(). */
808 #define UNCOND_JUMP 0
810 #define COND_JUMP86 2
811 #define BRANCH_PADDING 3
812 #define BRANCH_PREFIX 4
813 #define FUSED_JCC_PADDING 5
818 #define SMALL16 (SMALL | CODE16)
820 #define BIG16 (BIG | CODE16)
824 #define INLINE __inline__
830 #define ENCODE_RELAX_STATE(type, size) \
831 ((relax_substateT) (((type) << 2) | (size)))
832 #define TYPE_FROM_RELAX_STATE(s) \
834 #define DISP_SIZE_FROM_RELAX_STATE(s) \
835 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
837 /* This table is used by relax_frag to promote short jumps to long
838 ones where necessary. SMALL (short) jumps may be promoted to BIG
839 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
840 don't allow a short jump in a 32 bit code segment to be promoted to
841 a 16 bit offset jump because it's slower (requires data size
842 prefix), and doesn't work, unless the destination is in the bottom
843 64k of the code segment (The top 16 bits of eip are zeroed). */
845 const relax_typeS md_relax_table
[] =
848 1) most positive reach of this state,
849 2) most negative reach of this state,
850 3) how many bytes this mode will have in the variable part of the frag
851 4) which index into the table to try if we can't fit into this one. */
853 /* UNCOND_JUMP states. */
854 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
855 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
856 /* dword jmp adds 4 bytes to frag:
857 0 extra opcode bytes, 4 displacement bytes. */
859 /* word jmp adds 2 byte2 to frag:
860 0 extra opcode bytes, 2 displacement bytes. */
863 /* COND_JUMP states. */
864 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
865 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
866 /* dword conditionals adds 5 bytes to frag:
867 1 extra opcode byte, 4 displacement bytes. */
869 /* word conditionals add 3 bytes to frag:
870 1 extra opcode byte, 2 displacement bytes. */
873 /* COND_JUMP86 states. */
874 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
875 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
876 /* dword conditionals adds 5 bytes to frag:
877 1 extra opcode byte, 4 displacement bytes. */
879 /* word conditionals add 4 bytes to frag:
880 1 displacement byte and a 3 byte long branch insn. */
884 static const arch_entry cpu_arch
[] =
886 /* Do not replace the first two entries - i386_target_format()
887 relies on them being there in this order. */
888 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32
,
889 CPU_GENERIC32_FLAGS
, 0 },
890 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64
,
891 CPU_GENERIC64_FLAGS
, 0 },
892 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN
,
894 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN
,
896 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN
,
898 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386
,
900 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486
,
902 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM
,
904 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO
,
906 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM
,
908 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO
,
909 CPU_PENTIUMPRO_FLAGS
, 0 },
910 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO
,
912 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO
,
914 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4
,
916 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA
,
918 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA
,
919 CPU_NOCONA_FLAGS
, 0 },
920 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE
,
922 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE
,
924 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2
,
925 CPU_CORE2_FLAGS
, 1 },
926 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2
,
927 CPU_CORE2_FLAGS
, 0 },
928 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7
,
929 CPU_COREI7_FLAGS
, 0 },
930 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM
,
932 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM
,
934 { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU
,
935 CPU_IAMCU_FLAGS
, 0 },
936 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6
,
938 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6
,
940 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON
,
941 CPU_ATHLON_FLAGS
, 0 },
942 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8
,
944 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8
,
946 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8
,
948 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10
,
949 CPU_AMDFAM10_FLAGS
, 0 },
950 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD
,
951 CPU_BDVER1_FLAGS
, 0 },
952 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD
,
953 CPU_BDVER2_FLAGS
, 0 },
954 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD
,
955 CPU_BDVER3_FLAGS
, 0 },
956 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD
,
957 CPU_BDVER4_FLAGS
, 0 },
958 { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER
,
959 CPU_ZNVER1_FLAGS
, 0 },
960 { STRING_COMMA_LEN ("znver2"), PROCESSOR_ZNVER
,
961 CPU_ZNVER2_FLAGS
, 0 },
962 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT
,
963 CPU_BTVER1_FLAGS
, 0 },
964 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT
,
965 CPU_BTVER2_FLAGS
, 0 },
966 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN
,
968 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN
,
970 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN
,
972 { STRING_COMMA_LEN (".687"), PROCESSOR_UNKNOWN
,
974 { STRING_COMMA_LEN (".cmov"), PROCESSOR_UNKNOWN
,
976 { STRING_COMMA_LEN (".fxsr"), PROCESSOR_UNKNOWN
,
978 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN
,
980 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN
,
982 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN
,
984 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN
,
986 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN
,
987 CPU_SSE4A_FLAGS
, 0 },
988 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN
,
989 CPU_SSSE3_FLAGS
, 0 },
990 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN
,
991 CPU_SSE4_1_FLAGS
, 0 },
992 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN
,
993 CPU_SSE4_2_FLAGS
, 0 },
994 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN
,
995 CPU_SSE4_2_FLAGS
, 0 },
996 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN
,
998 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN
,
1000 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN
,
1001 CPU_AVX512F_FLAGS
, 0 },
1002 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN
,
1003 CPU_AVX512CD_FLAGS
, 0 },
1004 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN
,
1005 CPU_AVX512ER_FLAGS
, 0 },
1006 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN
,
1007 CPU_AVX512PF_FLAGS
, 0 },
1008 { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN
,
1009 CPU_AVX512DQ_FLAGS
, 0 },
1010 { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN
,
1011 CPU_AVX512BW_FLAGS
, 0 },
1012 { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN
,
1013 CPU_AVX512VL_FLAGS
, 0 },
1014 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN
,
1016 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN
,
1017 CPU_VMFUNC_FLAGS
, 0 },
1018 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN
,
1020 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN
,
1021 CPU_XSAVE_FLAGS
, 0 },
1022 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN
,
1023 CPU_XSAVEOPT_FLAGS
, 0 },
1024 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN
,
1025 CPU_XSAVEC_FLAGS
, 0 },
1026 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN
,
1027 CPU_XSAVES_FLAGS
, 0 },
1028 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN
,
1030 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN
,
1031 CPU_PCLMUL_FLAGS
, 0 },
1032 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN
,
1033 CPU_PCLMUL_FLAGS
, 1 },
1034 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN
,
1035 CPU_FSGSBASE_FLAGS
, 0 },
1036 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN
,
1037 CPU_RDRND_FLAGS
, 0 },
1038 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN
,
1039 CPU_F16C_FLAGS
, 0 },
1040 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN
,
1041 CPU_BMI2_FLAGS
, 0 },
1042 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN
,
1044 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN
,
1045 CPU_FMA4_FLAGS
, 0 },
1046 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN
,
1048 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN
,
1050 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN
,
1051 CPU_MOVBE_FLAGS
, 0 },
1052 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN
,
1053 CPU_CX16_FLAGS
, 0 },
1054 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN
,
1056 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN
,
1057 CPU_LZCNT_FLAGS
, 0 },
1058 { STRING_COMMA_LEN (".popcnt"), PROCESSOR_UNKNOWN
,
1059 CPU_POPCNT_FLAGS
, 0 },
1060 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN
,
1062 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN
,
1064 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN
,
1065 CPU_INVPCID_FLAGS
, 0 },
1066 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN
,
1067 CPU_CLFLUSH_FLAGS
, 0 },
1068 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN
,
1070 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN
,
1071 CPU_SYSCALL_FLAGS
, 0 },
1072 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN
,
1073 CPU_RDTSCP_FLAGS
, 0 },
1074 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN
,
1075 CPU_3DNOW_FLAGS
, 0 },
1076 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN
,
1077 CPU_3DNOWA_FLAGS
, 0 },
1078 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN
,
1079 CPU_PADLOCK_FLAGS
, 0 },
1080 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN
,
1081 CPU_SVME_FLAGS
, 1 },
1082 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN
,
1083 CPU_SVME_FLAGS
, 0 },
1084 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN
,
1085 CPU_SSE4A_FLAGS
, 0 },
1086 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN
,
1088 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN
,
1090 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN
,
1092 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN
,
1094 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN
,
1095 CPU_RDSEED_FLAGS
, 0 },
1096 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN
,
1097 CPU_PRFCHW_FLAGS
, 0 },
1098 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN
,
1099 CPU_SMAP_FLAGS
, 0 },
1100 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN
,
1102 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN
,
1104 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN
,
1105 CPU_CLFLUSHOPT_FLAGS
, 0 },
1106 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN
,
1107 CPU_PREFETCHWT1_FLAGS
, 0 },
1108 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN
,
1110 { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN
,
1111 CPU_CLWB_FLAGS
, 0 },
1112 { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN
,
1113 CPU_AVX512IFMA_FLAGS
, 0 },
1114 { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN
,
1115 CPU_AVX512VBMI_FLAGS
, 0 },
1116 { STRING_COMMA_LEN (".avx512_4fmaps"), PROCESSOR_UNKNOWN
,
1117 CPU_AVX512_4FMAPS_FLAGS
, 0 },
1118 { STRING_COMMA_LEN (".avx512_4vnniw"), PROCESSOR_UNKNOWN
,
1119 CPU_AVX512_4VNNIW_FLAGS
, 0 },
1120 { STRING_COMMA_LEN (".avx512_vpopcntdq"), PROCESSOR_UNKNOWN
,
1121 CPU_AVX512_VPOPCNTDQ_FLAGS
, 0 },
1122 { STRING_COMMA_LEN (".avx512_vbmi2"), PROCESSOR_UNKNOWN
,
1123 CPU_AVX512_VBMI2_FLAGS
, 0 },
1124 { STRING_COMMA_LEN (".avx512_vnni"), PROCESSOR_UNKNOWN
,
1125 CPU_AVX512_VNNI_FLAGS
, 0 },
1126 { STRING_COMMA_LEN (".avx512_bitalg"), PROCESSOR_UNKNOWN
,
1127 CPU_AVX512_BITALG_FLAGS
, 0 },
1128 { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN
,
1129 CPU_CLZERO_FLAGS
, 0 },
1130 { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN
,
1131 CPU_MWAITX_FLAGS
, 0 },
1132 { STRING_COMMA_LEN (".ospke"), PROCESSOR_UNKNOWN
,
1133 CPU_OSPKE_FLAGS
, 0 },
1134 { STRING_COMMA_LEN (".rdpid"), PROCESSOR_UNKNOWN
,
1135 CPU_RDPID_FLAGS
, 0 },
1136 { STRING_COMMA_LEN (".ptwrite"), PROCESSOR_UNKNOWN
,
1137 CPU_PTWRITE_FLAGS
, 0 },
1138 { STRING_COMMA_LEN (".ibt"), PROCESSOR_UNKNOWN
,
1140 { STRING_COMMA_LEN (".shstk"), PROCESSOR_UNKNOWN
,
1141 CPU_SHSTK_FLAGS
, 0 },
1142 { STRING_COMMA_LEN (".gfni"), PROCESSOR_UNKNOWN
,
1143 CPU_GFNI_FLAGS
, 0 },
1144 { STRING_COMMA_LEN (".vaes"), PROCESSOR_UNKNOWN
,
1145 CPU_VAES_FLAGS
, 0 },
1146 { STRING_COMMA_LEN (".vpclmulqdq"), PROCESSOR_UNKNOWN
,
1147 CPU_VPCLMULQDQ_FLAGS
, 0 },
1148 { STRING_COMMA_LEN (".wbnoinvd"), PROCESSOR_UNKNOWN
,
1149 CPU_WBNOINVD_FLAGS
, 0 },
1150 { STRING_COMMA_LEN (".pconfig"), PROCESSOR_UNKNOWN
,
1151 CPU_PCONFIG_FLAGS
, 0 },
1152 { STRING_COMMA_LEN (".waitpkg"), PROCESSOR_UNKNOWN
,
1153 CPU_WAITPKG_FLAGS
, 0 },
1154 { STRING_COMMA_LEN (".cldemote"), PROCESSOR_UNKNOWN
,
1155 CPU_CLDEMOTE_FLAGS
, 0 },
1156 { STRING_COMMA_LEN (".movdiri"), PROCESSOR_UNKNOWN
,
1157 CPU_MOVDIRI_FLAGS
, 0 },
1158 { STRING_COMMA_LEN (".movdir64b"), PROCESSOR_UNKNOWN
,
1159 CPU_MOVDIR64B_FLAGS
, 0 },
1160 { STRING_COMMA_LEN (".avx512_bf16"), PROCESSOR_UNKNOWN
,
1161 CPU_AVX512_BF16_FLAGS
, 0 },
1162 { STRING_COMMA_LEN (".avx512_vp2intersect"), PROCESSOR_UNKNOWN
,
1163 CPU_AVX512_VP2INTERSECT_FLAGS
, 0 },
1164 { STRING_COMMA_LEN (".enqcmd"), PROCESSOR_UNKNOWN
,
1165 CPU_ENQCMD_FLAGS
, 0 },
1166 { STRING_COMMA_LEN (".rdpru"), PROCESSOR_UNKNOWN
,
1167 CPU_RDPRU_FLAGS
, 0 },
1168 { STRING_COMMA_LEN (".mcommit"), PROCESSOR_UNKNOWN
,
1169 CPU_MCOMMIT_FLAGS
, 0 },
1172 static const noarch_entry cpu_noarch
[] =
1174 { STRING_COMMA_LEN ("no87"), CPU_ANY_X87_FLAGS
},
1175 { STRING_COMMA_LEN ("no287"), CPU_ANY_287_FLAGS
},
1176 { STRING_COMMA_LEN ("no387"), CPU_ANY_387_FLAGS
},
1177 { STRING_COMMA_LEN ("no687"), CPU_ANY_687_FLAGS
},
1178 { STRING_COMMA_LEN ("nocmov"), CPU_ANY_CMOV_FLAGS
},
1179 { STRING_COMMA_LEN ("nofxsr"), CPU_ANY_FXSR_FLAGS
},
1180 { STRING_COMMA_LEN ("nommx"), CPU_ANY_MMX_FLAGS
},
1181 { STRING_COMMA_LEN ("nosse"), CPU_ANY_SSE_FLAGS
},
1182 { STRING_COMMA_LEN ("nosse2"), CPU_ANY_SSE2_FLAGS
},
1183 { STRING_COMMA_LEN ("nosse3"), CPU_ANY_SSE3_FLAGS
},
1184 { STRING_COMMA_LEN ("nosse4a"), CPU_ANY_SSE4A_FLAGS
},
1185 { STRING_COMMA_LEN ("nossse3"), CPU_ANY_SSSE3_FLAGS
},
1186 { STRING_COMMA_LEN ("nosse4.1"), CPU_ANY_SSE4_1_FLAGS
},
1187 { STRING_COMMA_LEN ("nosse4.2"), CPU_ANY_SSE4_2_FLAGS
},
1188 { STRING_COMMA_LEN ("nosse4"), CPU_ANY_SSE4_1_FLAGS
},
1189 { STRING_COMMA_LEN ("noavx"), CPU_ANY_AVX_FLAGS
},
1190 { STRING_COMMA_LEN ("noavx2"), CPU_ANY_AVX2_FLAGS
},
1191 { STRING_COMMA_LEN ("noavx512f"), CPU_ANY_AVX512F_FLAGS
},
1192 { STRING_COMMA_LEN ("noavx512cd"), CPU_ANY_AVX512CD_FLAGS
},
1193 { STRING_COMMA_LEN ("noavx512er"), CPU_ANY_AVX512ER_FLAGS
},
1194 { STRING_COMMA_LEN ("noavx512pf"), CPU_ANY_AVX512PF_FLAGS
},
1195 { STRING_COMMA_LEN ("noavx512dq"), CPU_ANY_AVX512DQ_FLAGS
},
1196 { STRING_COMMA_LEN ("noavx512bw"), CPU_ANY_AVX512BW_FLAGS
},
1197 { STRING_COMMA_LEN ("noavx512vl"), CPU_ANY_AVX512VL_FLAGS
},
1198 { STRING_COMMA_LEN ("noavx512ifma"), CPU_ANY_AVX512IFMA_FLAGS
},
1199 { STRING_COMMA_LEN ("noavx512vbmi"), CPU_ANY_AVX512VBMI_FLAGS
},
1200 { STRING_COMMA_LEN ("noavx512_4fmaps"), CPU_ANY_AVX512_4FMAPS_FLAGS
},
1201 { STRING_COMMA_LEN ("noavx512_4vnniw"), CPU_ANY_AVX512_4VNNIW_FLAGS
},
1202 { STRING_COMMA_LEN ("noavx512_vpopcntdq"), CPU_ANY_AVX512_VPOPCNTDQ_FLAGS
},
1203 { STRING_COMMA_LEN ("noavx512_vbmi2"), CPU_ANY_AVX512_VBMI2_FLAGS
},
1204 { STRING_COMMA_LEN ("noavx512_vnni"), CPU_ANY_AVX512_VNNI_FLAGS
},
1205 { STRING_COMMA_LEN ("noavx512_bitalg"), CPU_ANY_AVX512_BITALG_FLAGS
},
1206 { STRING_COMMA_LEN ("noibt"), CPU_ANY_IBT_FLAGS
},
1207 { STRING_COMMA_LEN ("noshstk"), CPU_ANY_SHSTK_FLAGS
},
1208 { STRING_COMMA_LEN ("nomovdiri"), CPU_ANY_MOVDIRI_FLAGS
},
1209 { STRING_COMMA_LEN ("nomovdir64b"), CPU_ANY_MOVDIR64B_FLAGS
},
1210 { STRING_COMMA_LEN ("noavx512_bf16"), CPU_ANY_AVX512_BF16_FLAGS
},
1211 { STRING_COMMA_LEN ("noavx512_vp2intersect"), CPU_ANY_SHSTK_FLAGS
},
1212 { STRING_COMMA_LEN ("noenqcmd"), CPU_ANY_ENQCMD_FLAGS
},
1216 /* Like s_lcomm_internal in gas/read.c but the alignment string
1217 is allowed to be optional. */
1220 pe_lcomm_internal (int needs_align
, symbolS
*symbolP
, addressT size
)
1227 && *input_line_pointer
== ',')
1229 align
= parse_align (needs_align
- 1);
1231 if (align
== (addressT
) -1)
1246 bss_alloc (symbolP
, size
, align
);
1251 pe_lcomm (int needs_align
)
1253 s_comm_internal (needs_align
* 2, pe_lcomm_internal
);
1257 const pseudo_typeS md_pseudo_table
[] =
1259 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
1260 {"align", s_align_bytes
, 0},
1262 {"align", s_align_ptwo
, 0},
1264 {"arch", set_cpu_arch
, 0},
1268 {"lcomm", pe_lcomm
, 1},
1270 {"ffloat", float_cons
, 'f'},
1271 {"dfloat", float_cons
, 'd'},
1272 {"tfloat", float_cons
, 'x'},
1274 {"slong", signed_cons
, 4},
1275 {"noopt", s_ignore
, 0},
1276 {"optim", s_ignore
, 0},
1277 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
1278 {"code16", set_code_flag
, CODE_16BIT
},
1279 {"code32", set_code_flag
, CODE_32BIT
},
1281 {"code64", set_code_flag
, CODE_64BIT
},
1283 {"intel_syntax", set_intel_syntax
, 1},
1284 {"att_syntax", set_intel_syntax
, 0},
1285 {"intel_mnemonic", set_intel_mnemonic
, 1},
1286 {"att_mnemonic", set_intel_mnemonic
, 0},
1287 {"allow_index_reg", set_allow_index_reg
, 1},
1288 {"disallow_index_reg", set_allow_index_reg
, 0},
1289 {"sse_check", set_check
, 0},
1290 {"operand_check", set_check
, 1},
1291 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1292 {"largecomm", handle_large_common
, 0},
1294 {"file", dwarf2_directive_file
, 0},
1295 {"loc", dwarf2_directive_loc
, 0},
1296 {"loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0},
1299 {"secrel32", pe_directive_secrel
, 0},
1304 /* For interface with expression (). */
1305 extern char *input_line_pointer
;
1307 /* Hash table for instruction mnemonic lookup. */
1308 static struct hash_control
*op_hash
;
1310 /* Hash table for register lookup. */
1311 static struct hash_control
*reg_hash
;
1313 /* Various efficient no-op patterns for aligning code labels.
1314 Note: Don't try to assemble the instructions in the comments.
1315 0L and 0w are not legal. */
1316 static const unsigned char f32_1
[] =
1318 static const unsigned char f32_2
[] =
1319 {0x66,0x90}; /* xchg %ax,%ax */
1320 static const unsigned char f32_3
[] =
1321 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1322 static const unsigned char f32_4
[] =
1323 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1324 static const unsigned char f32_6
[] =
1325 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1326 static const unsigned char f32_7
[] =
1327 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1328 static const unsigned char f16_3
[] =
1329 {0x8d,0x74,0x00}; /* lea 0(%si),%si */
1330 static const unsigned char f16_4
[] =
1331 {0x8d,0xb4,0x00,0x00}; /* lea 0W(%si),%si */
1332 static const unsigned char jump_disp8
[] =
1333 {0xeb}; /* jmp disp8 */
1334 static const unsigned char jump32_disp32
[] =
1335 {0xe9}; /* jmp disp32 */
1336 static const unsigned char jump16_disp32
[] =
1337 {0x66,0xe9}; /* jmp disp32 */
1338 /* 32-bit NOPs patterns. */
1339 static const unsigned char *const f32_patt
[] = {
1340 f32_1
, f32_2
, f32_3
, f32_4
, NULL
, f32_6
, f32_7
1342 /* 16-bit NOPs patterns. */
1343 static const unsigned char *const f16_patt
[] = {
1344 f32_1
, f32_2
, f16_3
, f16_4
1346 /* nopl (%[re]ax) */
1347 static const unsigned char alt_3
[] =
1349 /* nopl 0(%[re]ax) */
1350 static const unsigned char alt_4
[] =
1351 {0x0f,0x1f,0x40,0x00};
1352 /* nopl 0(%[re]ax,%[re]ax,1) */
1353 static const unsigned char alt_5
[] =
1354 {0x0f,0x1f,0x44,0x00,0x00};
1355 /* nopw 0(%[re]ax,%[re]ax,1) */
1356 static const unsigned char alt_6
[] =
1357 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1358 /* nopl 0L(%[re]ax) */
1359 static const unsigned char alt_7
[] =
1360 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1361 /* nopl 0L(%[re]ax,%[re]ax,1) */
1362 static const unsigned char alt_8
[] =
1363 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1364 /* nopw 0L(%[re]ax,%[re]ax,1) */
1365 static const unsigned char alt_9
[] =
1366 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1367 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1368 static const unsigned char alt_10
[] =
1369 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1370 /* data16 nopw %cs:0L(%eax,%eax,1) */
1371 static const unsigned char alt_11
[] =
1372 {0x66,0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1373 /* 32-bit and 64-bit NOPs patterns. */
1374 static const unsigned char *const alt_patt
[] = {
1375 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
1376 alt_9
, alt_10
, alt_11
1379 /* Genenerate COUNT bytes of NOPs to WHERE from PATT with the maximum
1380 size of a single NOP instruction MAX_SINGLE_NOP_SIZE. */
1383 i386_output_nops (char *where
, const unsigned char *const *patt
,
1384 int count
, int max_single_nop_size
)
1387 /* Place the longer NOP first. */
1390 const unsigned char *nops
;
1392 if (max_single_nop_size
< 1)
1394 as_fatal (_("i386_output_nops called to generate nops of at most %d bytes!"),
1395 max_single_nop_size
);
1399 nops
= patt
[max_single_nop_size
- 1];
1401 /* Use the smaller one if the requsted one isn't available. */
1404 max_single_nop_size
--;
1405 nops
= patt
[max_single_nop_size
- 1];
1408 last
= count
% max_single_nop_size
;
1411 for (offset
= 0; offset
< count
; offset
+= max_single_nop_size
)
1412 memcpy (where
+ offset
, nops
, max_single_nop_size
);
1416 nops
= patt
[last
- 1];
1419 /* Use the smaller one plus one-byte NOP if the needed one
1422 nops
= patt
[last
- 1];
1423 memcpy (where
+ offset
, nops
, last
);
1424 where
[offset
+ last
] = *patt
[0];
1427 memcpy (where
+ offset
, nops
, last
);
1432 fits_in_imm7 (offsetT num
)
1434 return (num
& 0x7f) == num
;
1438 fits_in_imm31 (offsetT num
)
1440 return (num
& 0x7fffffff) == num
;
1443 /* Genenerate COUNT bytes of NOPs to WHERE with the maximum size of a
1444 single NOP instruction LIMIT. */
1447 i386_generate_nops (fragS
*fragP
, char *where
, offsetT count
, int limit
)
1449 const unsigned char *const *patt
= NULL
;
1450 int max_single_nop_size
;
1451 /* Maximum number of NOPs before switching to jump over NOPs. */
1452 int max_number_of_nops
;
1454 switch (fragP
->fr_type
)
1459 case rs_machine_dependent
:
1460 /* Allow NOP padding for jumps and calls. */
1461 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
1462 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
)
1469 /* We need to decide which NOP sequence to use for 32bit and
1470 64bit. When -mtune= is used:
1472 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1473 PROCESSOR_GENERIC32, f32_patt will be used.
1474 2. For the rest, alt_patt will be used.
1476 When -mtune= isn't used, alt_patt will be used if
1477 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
1480 When -march= or .arch is used, we can't use anything beyond
1481 cpu_arch_isa_flags. */
1483 if (flag_code
== CODE_16BIT
)
1486 max_single_nop_size
= sizeof (f16_patt
) / sizeof (f16_patt
[0]);
1487 /* Limit number of NOPs to 2 in 16-bit mode. */
1488 max_number_of_nops
= 2;
1492 if (fragP
->tc_frag_data
.isa
== PROCESSOR_UNKNOWN
)
1494 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1495 switch (cpu_arch_tune
)
1497 case PROCESSOR_UNKNOWN
:
1498 /* We use cpu_arch_isa_flags to check if we SHOULD
1499 optimize with nops. */
1500 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1505 case PROCESSOR_PENTIUM4
:
1506 case PROCESSOR_NOCONA
:
1507 case PROCESSOR_CORE
:
1508 case PROCESSOR_CORE2
:
1509 case PROCESSOR_COREI7
:
1510 case PROCESSOR_L1OM
:
1511 case PROCESSOR_K1OM
:
1512 case PROCESSOR_GENERIC64
:
1514 case PROCESSOR_ATHLON
:
1516 case PROCESSOR_AMDFAM10
:
1518 case PROCESSOR_ZNVER
:
1522 case PROCESSOR_I386
:
1523 case PROCESSOR_I486
:
1524 case PROCESSOR_PENTIUM
:
1525 case PROCESSOR_PENTIUMPRO
:
1526 case PROCESSOR_IAMCU
:
1527 case PROCESSOR_GENERIC32
:
1534 switch (fragP
->tc_frag_data
.tune
)
1536 case PROCESSOR_UNKNOWN
:
1537 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1538 PROCESSOR_UNKNOWN. */
1542 case PROCESSOR_I386
:
1543 case PROCESSOR_I486
:
1544 case PROCESSOR_PENTIUM
:
1545 case PROCESSOR_IAMCU
:
1547 case PROCESSOR_ATHLON
:
1549 case PROCESSOR_AMDFAM10
:
1551 case PROCESSOR_ZNVER
:
1553 case PROCESSOR_GENERIC32
:
1554 /* We use cpu_arch_isa_flags to check if we CAN optimize
1556 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1561 case PROCESSOR_PENTIUMPRO
:
1562 case PROCESSOR_PENTIUM4
:
1563 case PROCESSOR_NOCONA
:
1564 case PROCESSOR_CORE
:
1565 case PROCESSOR_CORE2
:
1566 case PROCESSOR_COREI7
:
1567 case PROCESSOR_L1OM
:
1568 case PROCESSOR_K1OM
:
1569 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1574 case PROCESSOR_GENERIC64
:
1580 if (patt
== f32_patt
)
1582 max_single_nop_size
= sizeof (f32_patt
) / sizeof (f32_patt
[0]);
1583 /* Limit number of NOPs to 2 for older processors. */
1584 max_number_of_nops
= 2;
1588 max_single_nop_size
= sizeof (alt_patt
) / sizeof (alt_patt
[0]);
1589 /* Limit number of NOPs to 7 for newer processors. */
1590 max_number_of_nops
= 7;
1595 limit
= max_single_nop_size
;
1597 if (fragP
->fr_type
== rs_fill_nop
)
1599 /* Output NOPs for .nop directive. */
1600 if (limit
> max_single_nop_size
)
1602 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
1603 _("invalid single nop size: %d "
1604 "(expect within [0, %d])"),
1605 limit
, max_single_nop_size
);
1609 else if (fragP
->fr_type
!= rs_machine_dependent
)
1610 fragP
->fr_var
= count
;
1612 if ((count
/ max_single_nop_size
) > max_number_of_nops
)
1614 /* Generate jump over NOPs. */
1615 offsetT disp
= count
- 2;
1616 if (fits_in_imm7 (disp
))
1618 /* Use "jmp disp8" if possible. */
1620 where
[0] = jump_disp8
[0];
1626 unsigned int size_of_jump
;
1628 if (flag_code
== CODE_16BIT
)
1630 where
[0] = jump16_disp32
[0];
1631 where
[1] = jump16_disp32
[1];
1636 where
[0] = jump32_disp32
[0];
1640 count
-= size_of_jump
+ 4;
1641 if (!fits_in_imm31 (count
))
1643 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
1644 _("jump over nop padding out of range"));
1648 md_number_to_chars (where
+ size_of_jump
, count
, 4);
1649 where
+= size_of_jump
+ 4;
1653 /* Generate multiple NOPs. */
1654 i386_output_nops (where
, patt
, count
, limit
);
1658 operand_type_all_zero (const union i386_operand_type
*x
)
1660 switch (ARRAY_SIZE(x
->array
))
1671 return !x
->array
[0];
1678 operand_type_set (union i386_operand_type
*x
, unsigned int v
)
1680 switch (ARRAY_SIZE(x
->array
))
1696 x
->bitfield
.class = ClassNone
;
1697 x
->bitfield
.instance
= InstanceNone
;
1701 operand_type_equal (const union i386_operand_type
*x
,
1702 const union i386_operand_type
*y
)
1704 switch (ARRAY_SIZE(x
->array
))
1707 if (x
->array
[2] != y
->array
[2])
1711 if (x
->array
[1] != y
->array
[1])
1715 return x
->array
[0] == y
->array
[0];
1723 cpu_flags_all_zero (const union i386_cpu_flags
*x
)
1725 switch (ARRAY_SIZE(x
->array
))
1740 return !x
->array
[0];
1747 cpu_flags_equal (const union i386_cpu_flags
*x
,
1748 const union i386_cpu_flags
*y
)
1750 switch (ARRAY_SIZE(x
->array
))
1753 if (x
->array
[3] != y
->array
[3])
1757 if (x
->array
[2] != y
->array
[2])
1761 if (x
->array
[1] != y
->array
[1])
1765 return x
->array
[0] == y
->array
[0];
1773 cpu_flags_check_cpu64 (i386_cpu_flags f
)
1775 return !((flag_code
== CODE_64BIT
&& f
.bitfield
.cpuno64
)
1776 || (flag_code
!= CODE_64BIT
&& f
.bitfield
.cpu64
));
1779 static INLINE i386_cpu_flags
1780 cpu_flags_and (i386_cpu_flags x
, i386_cpu_flags y
)
1782 switch (ARRAY_SIZE (x
.array
))
1785 x
.array
[3] &= y
.array
[3];
1788 x
.array
[2] &= y
.array
[2];
1791 x
.array
[1] &= y
.array
[1];
1794 x
.array
[0] &= y
.array
[0];
1802 static INLINE i386_cpu_flags
1803 cpu_flags_or (i386_cpu_flags x
, i386_cpu_flags y
)
1805 switch (ARRAY_SIZE (x
.array
))
1808 x
.array
[3] |= y
.array
[3];
1811 x
.array
[2] |= y
.array
[2];
1814 x
.array
[1] |= y
.array
[1];
1817 x
.array
[0] |= y
.array
[0];
1825 static INLINE i386_cpu_flags
1826 cpu_flags_and_not (i386_cpu_flags x
, i386_cpu_flags y
)
1828 switch (ARRAY_SIZE (x
.array
))
1831 x
.array
[3] &= ~y
.array
[3];
1834 x
.array
[2] &= ~y
.array
[2];
1837 x
.array
[1] &= ~y
.array
[1];
1840 x
.array
[0] &= ~y
.array
[0];
1848 static const i386_cpu_flags avx512
= CPU_ANY_AVX512F_FLAGS
;
1850 #define CPU_FLAGS_ARCH_MATCH 0x1
1851 #define CPU_FLAGS_64BIT_MATCH 0x2
1853 #define CPU_FLAGS_PERFECT_MATCH \
1854 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_64BIT_MATCH)
1856 /* Return CPU flags match bits. */
1859 cpu_flags_match (const insn_template
*t
)
1861 i386_cpu_flags x
= t
->cpu_flags
;
1862 int match
= cpu_flags_check_cpu64 (x
) ? CPU_FLAGS_64BIT_MATCH
: 0;
1864 x
.bitfield
.cpu64
= 0;
1865 x
.bitfield
.cpuno64
= 0;
1867 if (cpu_flags_all_zero (&x
))
1869 /* This instruction is available on all archs. */
1870 match
|= CPU_FLAGS_ARCH_MATCH
;
1874 /* This instruction is available only on some archs. */
1875 i386_cpu_flags cpu
= cpu_arch_flags
;
1877 /* AVX512VL is no standalone feature - match it and then strip it. */
1878 if (x
.bitfield
.cpuavx512vl
&& !cpu
.bitfield
.cpuavx512vl
)
1880 x
.bitfield
.cpuavx512vl
= 0;
1882 cpu
= cpu_flags_and (x
, cpu
);
1883 if (!cpu_flags_all_zero (&cpu
))
1885 if (x
.bitfield
.cpuavx
)
1887 /* We need to check a few extra flags with AVX. */
1888 if (cpu
.bitfield
.cpuavx
1889 && (!t
->opcode_modifier
.sse2avx
|| sse2avx
)
1890 && (!x
.bitfield
.cpuaes
|| cpu
.bitfield
.cpuaes
)
1891 && (!x
.bitfield
.cpugfni
|| cpu
.bitfield
.cpugfni
)
1892 && (!x
.bitfield
.cpupclmul
|| cpu
.bitfield
.cpupclmul
))
1893 match
|= CPU_FLAGS_ARCH_MATCH
;
1895 else if (x
.bitfield
.cpuavx512f
)
1897 /* We need to check a few extra flags with AVX512F. */
1898 if (cpu
.bitfield
.cpuavx512f
1899 && (!x
.bitfield
.cpugfni
|| cpu
.bitfield
.cpugfni
)
1900 && (!x
.bitfield
.cpuvaes
|| cpu
.bitfield
.cpuvaes
)
1901 && (!x
.bitfield
.cpuvpclmulqdq
|| cpu
.bitfield
.cpuvpclmulqdq
))
1902 match
|= CPU_FLAGS_ARCH_MATCH
;
1905 match
|= CPU_FLAGS_ARCH_MATCH
;
1911 static INLINE i386_operand_type
1912 operand_type_and (i386_operand_type x
, i386_operand_type y
)
1914 if (x
.bitfield
.class != y
.bitfield
.class)
1915 x
.bitfield
.class = ClassNone
;
1916 if (x
.bitfield
.instance
!= y
.bitfield
.instance
)
1917 x
.bitfield
.instance
= InstanceNone
;
1919 switch (ARRAY_SIZE (x
.array
))
1922 x
.array
[2] &= y
.array
[2];
1925 x
.array
[1] &= y
.array
[1];
1928 x
.array
[0] &= y
.array
[0];
1936 static INLINE i386_operand_type
1937 operand_type_and_not (i386_operand_type x
, i386_operand_type y
)
1939 gas_assert (y
.bitfield
.class == ClassNone
);
1940 gas_assert (y
.bitfield
.instance
== InstanceNone
);
1942 switch (ARRAY_SIZE (x
.array
))
1945 x
.array
[2] &= ~y
.array
[2];
1948 x
.array
[1] &= ~y
.array
[1];
1951 x
.array
[0] &= ~y
.array
[0];
1959 static INLINE i386_operand_type
1960 operand_type_or (i386_operand_type x
, i386_operand_type y
)
1962 gas_assert (x
.bitfield
.class == ClassNone
||
1963 y
.bitfield
.class == ClassNone
||
1964 x
.bitfield
.class == y
.bitfield
.class);
1965 gas_assert (x
.bitfield
.instance
== InstanceNone
||
1966 y
.bitfield
.instance
== InstanceNone
||
1967 x
.bitfield
.instance
== y
.bitfield
.instance
);
1969 switch (ARRAY_SIZE (x
.array
))
1972 x
.array
[2] |= y
.array
[2];
1975 x
.array
[1] |= y
.array
[1];
1978 x
.array
[0] |= y
.array
[0];
1986 static INLINE i386_operand_type
1987 operand_type_xor (i386_operand_type x
, i386_operand_type y
)
1989 gas_assert (y
.bitfield
.class == ClassNone
);
1990 gas_assert (y
.bitfield
.instance
== InstanceNone
);
1992 switch (ARRAY_SIZE (x
.array
))
1995 x
.array
[2] ^= y
.array
[2];
1998 x
.array
[1] ^= y
.array
[1];
2001 x
.array
[0] ^= y
.array
[0];
2009 static const i386_operand_type disp16
= OPERAND_TYPE_DISP16
;
2010 static const i386_operand_type disp32
= OPERAND_TYPE_DISP32
;
2011 static const i386_operand_type disp32s
= OPERAND_TYPE_DISP32S
;
2012 static const i386_operand_type disp16_32
= OPERAND_TYPE_DISP16_32
;
2013 static const i386_operand_type anydisp
= OPERAND_TYPE_ANYDISP
;
2014 static const i386_operand_type anyimm
= OPERAND_TYPE_ANYIMM
;
2015 static const i386_operand_type regxmm
= OPERAND_TYPE_REGXMM
;
2016 static const i386_operand_type regmask
= OPERAND_TYPE_REGMASK
;
2017 static const i386_operand_type imm8
= OPERAND_TYPE_IMM8
;
2018 static const i386_operand_type imm8s
= OPERAND_TYPE_IMM8S
;
2019 static const i386_operand_type imm16
= OPERAND_TYPE_IMM16
;
2020 static const i386_operand_type imm32
= OPERAND_TYPE_IMM32
;
2021 static const i386_operand_type imm32s
= OPERAND_TYPE_IMM32S
;
2022 static const i386_operand_type imm64
= OPERAND_TYPE_IMM64
;
2023 static const i386_operand_type imm16_32
= OPERAND_TYPE_IMM16_32
;
2024 static const i386_operand_type imm16_32s
= OPERAND_TYPE_IMM16_32S
;
2025 static const i386_operand_type imm16_32_32s
= OPERAND_TYPE_IMM16_32_32S
;
2036 operand_type_check (i386_operand_type t
, enum operand_type c
)
2041 return t
.bitfield
.class == Reg
;
2044 return (t
.bitfield
.imm8
2048 || t
.bitfield
.imm32s
2049 || t
.bitfield
.imm64
);
2052 return (t
.bitfield
.disp8
2053 || t
.bitfield
.disp16
2054 || t
.bitfield
.disp32
2055 || t
.bitfield
.disp32s
2056 || t
.bitfield
.disp64
);
2059 return (t
.bitfield
.disp8
2060 || t
.bitfield
.disp16
2061 || t
.bitfield
.disp32
2062 || t
.bitfield
.disp32s
2063 || t
.bitfield
.disp64
2064 || t
.bitfield
.baseindex
);
2073 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit/80bit size
2074 between operand GIVEN and opeand WANTED for instruction template T. */
2077 match_operand_size (const insn_template
*t
, unsigned int wanted
,
2080 return !((i
.types
[given
].bitfield
.byte
2081 && !t
->operand_types
[wanted
].bitfield
.byte
)
2082 || (i
.types
[given
].bitfield
.word
2083 && !t
->operand_types
[wanted
].bitfield
.word
)
2084 || (i
.types
[given
].bitfield
.dword
2085 && !t
->operand_types
[wanted
].bitfield
.dword
)
2086 || (i
.types
[given
].bitfield
.qword
2087 && !t
->operand_types
[wanted
].bitfield
.qword
)
2088 || (i
.types
[given
].bitfield
.tbyte
2089 && !t
->operand_types
[wanted
].bitfield
.tbyte
));
2092 /* Return 1 if there is no conflict in SIMD register between operand
2093 GIVEN and opeand WANTED for instruction template T. */
2096 match_simd_size (const insn_template
*t
, unsigned int wanted
,
2099 return !((i
.types
[given
].bitfield
.xmmword
2100 && !t
->operand_types
[wanted
].bitfield
.xmmword
)
2101 || (i
.types
[given
].bitfield
.ymmword
2102 && !t
->operand_types
[wanted
].bitfield
.ymmword
)
2103 || (i
.types
[given
].bitfield
.zmmword
2104 && !t
->operand_types
[wanted
].bitfield
.zmmword
));
2107 /* Return 1 if there is no conflict in any size between operand GIVEN
2108 and opeand WANTED for instruction template T. */
2111 match_mem_size (const insn_template
*t
, unsigned int wanted
,
2114 return (match_operand_size (t
, wanted
, given
)
2115 && !((i
.types
[given
].bitfield
.unspecified
2117 && !t
->operand_types
[wanted
].bitfield
.unspecified
)
2118 || (i
.types
[given
].bitfield
.fword
2119 && !t
->operand_types
[wanted
].bitfield
.fword
)
2120 /* For scalar opcode templates to allow register and memory
2121 operands at the same time, some special casing is needed
2122 here. Also for v{,p}broadcast*, {,v}pmov{s,z}*, and
2123 down-conversion vpmov*. */
2124 || ((t
->operand_types
[wanted
].bitfield
.class == RegSIMD
2125 && !t
->opcode_modifier
.broadcast
2126 && (t
->operand_types
[wanted
].bitfield
.byte
2127 || t
->operand_types
[wanted
].bitfield
.word
2128 || t
->operand_types
[wanted
].bitfield
.dword
2129 || t
->operand_types
[wanted
].bitfield
.qword
))
2130 ? (i
.types
[given
].bitfield
.xmmword
2131 || i
.types
[given
].bitfield
.ymmword
2132 || i
.types
[given
].bitfield
.zmmword
)
2133 : !match_simd_size(t
, wanted
, given
))));
2136 /* Return value has MATCH_STRAIGHT set if there is no size conflict on any
2137 operands for instruction template T, and it has MATCH_REVERSE set if there
2138 is no size conflict on any operands for the template with operands reversed
2139 (and the template allows for reversing in the first place). */
2141 #define MATCH_STRAIGHT 1
2142 #define MATCH_REVERSE 2
2144 static INLINE
unsigned int
2145 operand_size_match (const insn_template
*t
)
2147 unsigned int j
, match
= MATCH_STRAIGHT
;
2149 /* Don't check non-absolute jump instructions. */
2150 if (t
->opcode_modifier
.jump
2151 && t
->opcode_modifier
.jump
!= JUMP_ABSOLUTE
)
2154 /* Check memory and accumulator operand size. */
2155 for (j
= 0; j
< i
.operands
; j
++)
2157 if (i
.types
[j
].bitfield
.class != Reg
2158 && i
.types
[j
].bitfield
.class != RegSIMD
2159 && t
->opcode_modifier
.anysize
)
2162 if (t
->operand_types
[j
].bitfield
.class == Reg
2163 && !match_operand_size (t
, j
, j
))
2169 if (t
->operand_types
[j
].bitfield
.class == RegSIMD
2170 && !match_simd_size (t
, j
, j
))
2176 if (t
->operand_types
[j
].bitfield
.instance
== Accum
2177 && (!match_operand_size (t
, j
, j
) || !match_simd_size (t
, j
, j
)))
2183 if ((i
.flags
[j
] & Operand_Mem
) && !match_mem_size (t
, j
, j
))
2190 if (!t
->opcode_modifier
.d
)
2194 i
.error
= operand_size_mismatch
;
2198 /* Check reverse. */
2199 gas_assert (i
.operands
>= 2 && i
.operands
<= 3);
2201 for (j
= 0; j
< i
.operands
; j
++)
2203 unsigned int given
= i
.operands
- j
- 1;
2205 if (t
->operand_types
[j
].bitfield
.class == Reg
2206 && !match_operand_size (t
, j
, given
))
2209 if (t
->operand_types
[j
].bitfield
.class == RegSIMD
2210 && !match_simd_size (t
, j
, given
))
2213 if (t
->operand_types
[j
].bitfield
.instance
== Accum
2214 && (!match_operand_size (t
, j
, given
)
2215 || !match_simd_size (t
, j
, given
)))
2218 if ((i
.flags
[given
] & Operand_Mem
) && !match_mem_size (t
, j
, given
))
2222 return match
| MATCH_REVERSE
;
2226 operand_type_match (i386_operand_type overlap
,
2227 i386_operand_type given
)
2229 i386_operand_type temp
= overlap
;
2231 temp
.bitfield
.unspecified
= 0;
2232 temp
.bitfield
.byte
= 0;
2233 temp
.bitfield
.word
= 0;
2234 temp
.bitfield
.dword
= 0;
2235 temp
.bitfield
.fword
= 0;
2236 temp
.bitfield
.qword
= 0;
2237 temp
.bitfield
.tbyte
= 0;
2238 temp
.bitfield
.xmmword
= 0;
2239 temp
.bitfield
.ymmword
= 0;
2240 temp
.bitfield
.zmmword
= 0;
2241 if (operand_type_all_zero (&temp
))
2244 if (given
.bitfield
.baseindex
== overlap
.bitfield
.baseindex
)
2248 i
.error
= operand_type_mismatch
;
2252 /* If given types g0 and g1 are registers they must be of the same type
2253 unless the expected operand type register overlap is null.
2254 Some Intel syntax memory operand size checking also happens here. */
2257 operand_type_register_match (i386_operand_type g0
,
2258 i386_operand_type t0
,
2259 i386_operand_type g1
,
2260 i386_operand_type t1
)
2262 if (g0
.bitfield
.class != Reg
2263 && g0
.bitfield
.class != RegSIMD
2264 && (!operand_type_check (g0
, anymem
)
2265 || g0
.bitfield
.unspecified
2266 || (t0
.bitfield
.class != Reg
2267 && t0
.bitfield
.class != RegSIMD
)))
2270 if (g1
.bitfield
.class != Reg
2271 && g1
.bitfield
.class != RegSIMD
2272 && (!operand_type_check (g1
, anymem
)
2273 || g1
.bitfield
.unspecified
2274 || (t1
.bitfield
.class != Reg
2275 && t1
.bitfield
.class != RegSIMD
)))
2278 if (g0
.bitfield
.byte
== g1
.bitfield
.byte
2279 && g0
.bitfield
.word
== g1
.bitfield
.word
2280 && g0
.bitfield
.dword
== g1
.bitfield
.dword
2281 && g0
.bitfield
.qword
== g1
.bitfield
.qword
2282 && g0
.bitfield
.xmmword
== g1
.bitfield
.xmmword
2283 && g0
.bitfield
.ymmword
== g1
.bitfield
.ymmword
2284 && g0
.bitfield
.zmmword
== g1
.bitfield
.zmmword
)
2287 if (!(t0
.bitfield
.byte
& t1
.bitfield
.byte
)
2288 && !(t0
.bitfield
.word
& t1
.bitfield
.word
)
2289 && !(t0
.bitfield
.dword
& t1
.bitfield
.dword
)
2290 && !(t0
.bitfield
.qword
& t1
.bitfield
.qword
)
2291 && !(t0
.bitfield
.xmmword
& t1
.bitfield
.xmmword
)
2292 && !(t0
.bitfield
.ymmword
& t1
.bitfield
.ymmword
)
2293 && !(t0
.bitfield
.zmmword
& t1
.bitfield
.zmmword
))
2296 i
.error
= register_type_mismatch
;
2301 static INLINE
unsigned int
2302 register_number (const reg_entry
*r
)
2304 unsigned int nr
= r
->reg_num
;
2306 if (r
->reg_flags
& RegRex
)
2309 if (r
->reg_flags
& RegVRex
)
2315 static INLINE
unsigned int
2316 mode_from_disp_size (i386_operand_type t
)
2318 if (t
.bitfield
.disp8
)
2320 else if (t
.bitfield
.disp16
2321 || t
.bitfield
.disp32
2322 || t
.bitfield
.disp32s
)
2329 fits_in_signed_byte (addressT num
)
2331 return num
+ 0x80 <= 0xff;
2335 fits_in_unsigned_byte (addressT num
)
2341 fits_in_unsigned_word (addressT num
)
2343 return num
<= 0xffff;
2347 fits_in_signed_word (addressT num
)
2349 return num
+ 0x8000 <= 0xffff;
2353 fits_in_signed_long (addressT num ATTRIBUTE_UNUSED
)
2358 return num
+ 0x80000000 <= 0xffffffff;
2360 } /* fits_in_signed_long() */
2363 fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED
)
2368 return num
<= 0xffffffff;
2370 } /* fits_in_unsigned_long() */
2373 fits_in_disp8 (offsetT num
)
2375 int shift
= i
.memshift
;
2381 mask
= (1 << shift
) - 1;
2383 /* Return 0 if NUM isn't properly aligned. */
2387 /* Check if NUM will fit in 8bit after shift. */
2388 return fits_in_signed_byte (num
>> shift
);
2392 fits_in_imm4 (offsetT num
)
2394 return (num
& 0xf) == num
;
2397 static i386_operand_type
2398 smallest_imm_type (offsetT num
)
2400 i386_operand_type t
;
2402 operand_type_set (&t
, 0);
2403 t
.bitfield
.imm64
= 1;
2405 if (cpu_arch_tune
!= PROCESSOR_I486
&& num
== 1)
2407 /* This code is disabled on the 486 because all the Imm1 forms
2408 in the opcode table are slower on the i486. They're the
2409 versions with the implicitly specified single-position
2410 displacement, which has another syntax if you really want to
2412 t
.bitfield
.imm1
= 1;
2413 t
.bitfield
.imm8
= 1;
2414 t
.bitfield
.imm8s
= 1;
2415 t
.bitfield
.imm16
= 1;
2416 t
.bitfield
.imm32
= 1;
2417 t
.bitfield
.imm32s
= 1;
2419 else if (fits_in_signed_byte (num
))
2421 t
.bitfield
.imm8
= 1;
2422 t
.bitfield
.imm8s
= 1;
2423 t
.bitfield
.imm16
= 1;
2424 t
.bitfield
.imm32
= 1;
2425 t
.bitfield
.imm32s
= 1;
2427 else if (fits_in_unsigned_byte (num
))
2429 t
.bitfield
.imm8
= 1;
2430 t
.bitfield
.imm16
= 1;
2431 t
.bitfield
.imm32
= 1;
2432 t
.bitfield
.imm32s
= 1;
2434 else if (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
2436 t
.bitfield
.imm16
= 1;
2437 t
.bitfield
.imm32
= 1;
2438 t
.bitfield
.imm32s
= 1;
2440 else if (fits_in_signed_long (num
))
2442 t
.bitfield
.imm32
= 1;
2443 t
.bitfield
.imm32s
= 1;
2445 else if (fits_in_unsigned_long (num
))
2446 t
.bitfield
.imm32
= 1;
2452 offset_in_range (offsetT val
, int size
)
2458 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
2459 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
2460 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
2462 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
2468 /* If BFD64, sign extend val for 32bit address mode. */
2469 if (flag_code
!= CODE_64BIT
2470 || i
.prefix
[ADDR_PREFIX
])
2471 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
2472 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
2475 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
2477 char buf1
[40], buf2
[40];
2479 sprint_value (buf1
, val
);
2480 sprint_value (buf2
, val
& mask
);
2481 as_warn (_("%s shortened to %s"), buf1
, buf2
);
2496 a. PREFIX_EXIST if attempting to add a prefix where one from the
2497 same class already exists.
2498 b. PREFIX_LOCK if lock prefix is added.
2499 c. PREFIX_REP if rep/repne prefix is added.
2500 d. PREFIX_DS if ds prefix is added.
2501 e. PREFIX_OTHER if other prefix is added.
2504 static enum PREFIX_GROUP
2505 add_prefix (unsigned int prefix
)
2507 enum PREFIX_GROUP ret
= PREFIX_OTHER
;
2510 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
2511 && flag_code
== CODE_64BIT
)
2513 if ((i
.prefix
[REX_PREFIX
] & prefix
& REX_W
)
2514 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_R
)
2515 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_X
)
2516 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_B
))
2527 case DS_PREFIX_OPCODE
:
2530 case CS_PREFIX_OPCODE
:
2531 case ES_PREFIX_OPCODE
:
2532 case FS_PREFIX_OPCODE
:
2533 case GS_PREFIX_OPCODE
:
2534 case SS_PREFIX_OPCODE
:
2538 case REPNE_PREFIX_OPCODE
:
2539 case REPE_PREFIX_OPCODE
:
2544 case LOCK_PREFIX_OPCODE
:
2553 case ADDR_PREFIX_OPCODE
:
2557 case DATA_PREFIX_OPCODE
:
2561 if (i
.prefix
[q
] != 0)
2569 i
.prefix
[q
] |= prefix
;
2572 as_bad (_("same type of prefix used twice"));
2578 update_code_flag (int value
, int check
)
2580 PRINTF_LIKE ((*as_error
));
2582 flag_code
= (enum flag_code
) value
;
2583 if (flag_code
== CODE_64BIT
)
2585 cpu_arch_flags
.bitfield
.cpu64
= 1;
2586 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2590 cpu_arch_flags
.bitfield
.cpu64
= 0;
2591 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2593 if (value
== CODE_64BIT
&& !cpu_arch_flags
.bitfield
.cpulm
)
2596 as_error
= as_fatal
;
2599 (*as_error
) (_("64bit mode not supported on `%s'."),
2600 cpu_arch_name
? cpu_arch_name
: default_arch
);
2602 if (value
== CODE_32BIT
&& !cpu_arch_flags
.bitfield
.cpui386
)
2605 as_error
= as_fatal
;
2608 (*as_error
) (_("32bit mode not supported on `%s'."),
2609 cpu_arch_name
? cpu_arch_name
: default_arch
);
2611 stackop_size
= '\0';
2615 set_code_flag (int value
)
2617 update_code_flag (value
, 0);
2621 set_16bit_gcc_code_flag (int new_code_flag
)
2623 flag_code
= (enum flag_code
) new_code_flag
;
2624 if (flag_code
!= CODE_16BIT
)
2626 cpu_arch_flags
.bitfield
.cpu64
= 0;
2627 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2628 stackop_size
= LONG_MNEM_SUFFIX
;
2632 set_intel_syntax (int syntax_flag
)
2634 /* Find out if register prefixing is specified. */
2635 int ask_naked_reg
= 0;
2638 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2641 int e
= get_symbol_name (&string
);
2643 if (strcmp (string
, "prefix") == 0)
2645 else if (strcmp (string
, "noprefix") == 0)
2648 as_bad (_("bad argument to syntax directive."));
2649 (void) restore_line_pointer (e
);
2651 demand_empty_rest_of_line ();
2653 intel_syntax
= syntax_flag
;
2655 if (ask_naked_reg
== 0)
2656 allow_naked_reg
= (intel_syntax
2657 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
2659 allow_naked_reg
= (ask_naked_reg
< 0);
2661 expr_set_rank (O_full_ptr
, syntax_flag
? 10 : 0);
2663 identifier_chars
['%'] = intel_syntax
&& allow_naked_reg
? '%' : 0;
2664 identifier_chars
['$'] = intel_syntax
? '$' : 0;
2665 register_prefix
= allow_naked_reg
? "" : "%";
2669 set_intel_mnemonic (int mnemonic_flag
)
2671 intel_mnemonic
= mnemonic_flag
;
2675 set_allow_index_reg (int flag
)
2677 allow_index_reg
= flag
;
2681 set_check (int what
)
2683 enum check_kind
*kind
;
2688 kind
= &operand_check
;
2699 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2702 int e
= get_symbol_name (&string
);
2704 if (strcmp (string
, "none") == 0)
2706 else if (strcmp (string
, "warning") == 0)
2707 *kind
= check_warning
;
2708 else if (strcmp (string
, "error") == 0)
2709 *kind
= check_error
;
2711 as_bad (_("bad argument to %s_check directive."), str
);
2712 (void) restore_line_pointer (e
);
2715 as_bad (_("missing argument for %s_check directive"), str
);
2717 demand_empty_rest_of_line ();
2721 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED
,
2722 i386_cpu_flags new_flag ATTRIBUTE_UNUSED
)
2724 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2725 static const char *arch
;
2727 /* Intel LIOM is only supported on ELF. */
2733 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2734 use default_arch. */
2735 arch
= cpu_arch_name
;
2737 arch
= default_arch
;
2740 /* If we are targeting Intel MCU, we must enable it. */
2741 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_IAMCU
2742 || new_flag
.bitfield
.cpuiamcu
)
2745 /* If we are targeting Intel L1OM, we must enable it. */
2746 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_L1OM
2747 || new_flag
.bitfield
.cpul1om
)
2750 /* If we are targeting Intel K1OM, we must enable it. */
2751 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_K1OM
2752 || new_flag
.bitfield
.cpuk1om
)
2755 as_bad (_("`%s' is not supported on `%s'"), name
, arch
);
2760 set_cpu_arch (int dummy ATTRIBUTE_UNUSED
)
2764 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2767 int e
= get_symbol_name (&string
);
2769 i386_cpu_flags flags
;
2771 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
2773 if (strcmp (string
, cpu_arch
[j
].name
) == 0)
2775 check_cpu_arch_compatible (string
, cpu_arch
[j
].flags
);
2779 cpu_arch_name
= cpu_arch
[j
].name
;
2780 cpu_sub_arch_name
= NULL
;
2781 cpu_arch_flags
= cpu_arch
[j
].flags
;
2782 if (flag_code
== CODE_64BIT
)
2784 cpu_arch_flags
.bitfield
.cpu64
= 1;
2785 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2789 cpu_arch_flags
.bitfield
.cpu64
= 0;
2790 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2792 cpu_arch_isa
= cpu_arch
[j
].type
;
2793 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
2794 if (!cpu_arch_tune_set
)
2796 cpu_arch_tune
= cpu_arch_isa
;
2797 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
2802 flags
= cpu_flags_or (cpu_arch_flags
,
2805 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2807 if (cpu_sub_arch_name
)
2809 char *name
= cpu_sub_arch_name
;
2810 cpu_sub_arch_name
= concat (name
,
2812 (const char *) NULL
);
2816 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
2817 cpu_arch_flags
= flags
;
2818 cpu_arch_isa_flags
= flags
;
2822 = cpu_flags_or (cpu_arch_isa_flags
,
2824 (void) restore_line_pointer (e
);
2825 demand_empty_rest_of_line ();
2830 if (*string
== '.' && j
>= ARRAY_SIZE (cpu_arch
))
2832 /* Disable an ISA extension. */
2833 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
2834 if (strcmp (string
+ 1, cpu_noarch
[j
].name
) == 0)
2836 flags
= cpu_flags_and_not (cpu_arch_flags
,
2837 cpu_noarch
[j
].flags
);
2838 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2840 if (cpu_sub_arch_name
)
2842 char *name
= cpu_sub_arch_name
;
2843 cpu_sub_arch_name
= concat (name
, string
,
2844 (const char *) NULL
);
2848 cpu_sub_arch_name
= xstrdup (string
);
2849 cpu_arch_flags
= flags
;
2850 cpu_arch_isa_flags
= flags
;
2852 (void) restore_line_pointer (e
);
2853 demand_empty_rest_of_line ();
2857 j
= ARRAY_SIZE (cpu_arch
);
2860 if (j
>= ARRAY_SIZE (cpu_arch
))
2861 as_bad (_("no such architecture: `%s'"), string
);
2863 *input_line_pointer
= e
;
2866 as_bad (_("missing cpu architecture"));
2868 no_cond_jump_promotion
= 0;
2869 if (*input_line_pointer
== ','
2870 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
2875 ++input_line_pointer
;
2876 e
= get_symbol_name (&string
);
2878 if (strcmp (string
, "nojumps") == 0)
2879 no_cond_jump_promotion
= 1;
2880 else if (strcmp (string
, "jumps") == 0)
2883 as_bad (_("no such architecture modifier: `%s'"), string
);
2885 (void) restore_line_pointer (e
);
2888 demand_empty_rest_of_line ();
2891 enum bfd_architecture
2894 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2896 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2897 || flag_code
!= CODE_64BIT
)
2898 as_fatal (_("Intel L1OM is 64bit ELF only"));
2899 return bfd_arch_l1om
;
2901 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2903 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2904 || flag_code
!= CODE_64BIT
)
2905 as_fatal (_("Intel K1OM is 64bit ELF only"));
2906 return bfd_arch_k1om
;
2908 else if (cpu_arch_isa
== PROCESSOR_IAMCU
)
2910 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2911 || flag_code
== CODE_64BIT
)
2912 as_fatal (_("Intel MCU is 32bit ELF only"));
2913 return bfd_arch_iamcu
;
2916 return bfd_arch_i386
;
2922 if (!strncmp (default_arch
, "x86_64", 6))
2924 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2926 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2927 || default_arch
[6] != '\0')
2928 as_fatal (_("Intel L1OM is 64bit ELF only"));
2929 return bfd_mach_l1om
;
2931 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2933 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2934 || default_arch
[6] != '\0')
2935 as_fatal (_("Intel K1OM is 64bit ELF only"));
2936 return bfd_mach_k1om
;
2938 else if (default_arch
[6] == '\0')
2939 return bfd_mach_x86_64
;
2941 return bfd_mach_x64_32
;
2943 else if (!strcmp (default_arch
, "i386")
2944 || !strcmp (default_arch
, "iamcu"))
2946 if (cpu_arch_isa
== PROCESSOR_IAMCU
)
2948 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
2949 as_fatal (_("Intel MCU is 32bit ELF only"));
2950 return bfd_mach_i386_iamcu
;
2953 return bfd_mach_i386_i386
;
2956 as_fatal (_("unknown architecture"));
2962 const char *hash_err
;
2964 /* Support pseudo prefixes like {disp32}. */
2965 lex_type
['{'] = LEX_BEGIN_NAME
;
2967 /* Initialize op_hash hash table. */
2968 op_hash
= hash_new ();
2971 const insn_template
*optab
;
2972 templates
*core_optab
;
2974 /* Setup for loop. */
2976 core_optab
= XNEW (templates
);
2977 core_optab
->start
= optab
;
2982 if (optab
->name
== NULL
2983 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
2985 /* different name --> ship out current template list;
2986 add to hash table; & begin anew. */
2987 core_optab
->end
= optab
;
2988 hash_err
= hash_insert (op_hash
,
2990 (void *) core_optab
);
2993 as_fatal (_("can't hash %s: %s"),
2997 if (optab
->name
== NULL
)
2999 core_optab
= XNEW (templates
);
3000 core_optab
->start
= optab
;
3005 /* Initialize reg_hash hash table. */
3006 reg_hash
= hash_new ();
3008 const reg_entry
*regtab
;
3009 unsigned int regtab_size
= i386_regtab_size
;
3011 for (regtab
= i386_regtab
; regtab_size
--; regtab
++)
3013 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (void *) regtab
);
3015 as_fatal (_("can't hash %s: %s"),
3021 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
3026 for (c
= 0; c
< 256; c
++)
3031 mnemonic_chars
[c
] = c
;
3032 register_chars
[c
] = c
;
3033 operand_chars
[c
] = c
;
3035 else if (ISLOWER (c
))
3037 mnemonic_chars
[c
] = c
;
3038 register_chars
[c
] = c
;
3039 operand_chars
[c
] = c
;
3041 else if (ISUPPER (c
))
3043 mnemonic_chars
[c
] = TOLOWER (c
);
3044 register_chars
[c
] = mnemonic_chars
[c
];
3045 operand_chars
[c
] = c
;
3047 else if (c
== '{' || c
== '}')
3049 mnemonic_chars
[c
] = c
;
3050 operand_chars
[c
] = c
;
3053 if (ISALPHA (c
) || ISDIGIT (c
))
3054 identifier_chars
[c
] = c
;
3057 identifier_chars
[c
] = c
;
3058 operand_chars
[c
] = c
;
3063 identifier_chars
['@'] = '@';
3066 identifier_chars
['?'] = '?';
3067 operand_chars
['?'] = '?';
3069 digit_chars
['-'] = '-';
3070 mnemonic_chars
['_'] = '_';
3071 mnemonic_chars
['-'] = '-';
3072 mnemonic_chars
['.'] = '.';
3073 identifier_chars
['_'] = '_';
3074 identifier_chars
['.'] = '.';
3076 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
3077 operand_chars
[(unsigned char) *p
] = *p
;
3080 if (flag_code
== CODE_64BIT
)
3082 #if defined (OBJ_COFF) && defined (TE_PE)
3083 x86_dwarf2_return_column
= (OUTPUT_FLAVOR
== bfd_target_coff_flavour
3086 x86_dwarf2_return_column
= 16;
3088 x86_cie_data_alignment
= -8;
3092 x86_dwarf2_return_column
= 8;
3093 x86_cie_data_alignment
= -4;
3096 /* NB: FUSED_JCC_PADDING frag must have sufficient room so that it
3097 can be turned into BRANCH_PREFIX frag. */
3098 if (align_branch_prefix_size
> MAX_FUSED_JCC_PADDING_SIZE
)
3103 i386_print_statistics (FILE *file
)
3105 hash_print_statistics (file
, "i386 opcode", op_hash
);
3106 hash_print_statistics (file
, "i386 register", reg_hash
);
3111 /* Debugging routines for md_assemble. */
3112 static void pte (insn_template
*);
3113 static void pt (i386_operand_type
);
3114 static void pe (expressionS
*);
3115 static void ps (symbolS
*);
3118 pi (const char *line
, i386_insn
*x
)
3122 fprintf (stdout
, "%s: template ", line
);
3124 fprintf (stdout
, " address: base %s index %s scale %x\n",
3125 x
->base_reg
? x
->base_reg
->reg_name
: "none",
3126 x
->index_reg
? x
->index_reg
->reg_name
: "none",
3127 x
->log2_scale_factor
);
3128 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
3129 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
3130 fprintf (stdout
, " sib: base %x index %x scale %x\n",
3131 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
3132 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
3133 (x
->rex
& REX_W
) != 0,
3134 (x
->rex
& REX_R
) != 0,
3135 (x
->rex
& REX_X
) != 0,
3136 (x
->rex
& REX_B
) != 0);
3137 for (j
= 0; j
< x
->operands
; j
++)
3139 fprintf (stdout
, " #%d: ", j
+ 1);
3141 fprintf (stdout
, "\n");
3142 if (x
->types
[j
].bitfield
.class == Reg
3143 || x
->types
[j
].bitfield
.class == RegMMX
3144 || x
->types
[j
].bitfield
.class == RegSIMD
3145 || x
->types
[j
].bitfield
.class == SReg
3146 || x
->types
[j
].bitfield
.class == RegCR
3147 || x
->types
[j
].bitfield
.class == RegDR
3148 || x
->types
[j
].bitfield
.class == RegTR
)
3149 fprintf (stdout
, "%s\n", x
->op
[j
].regs
->reg_name
);
3150 if (operand_type_check (x
->types
[j
], imm
))
3152 if (operand_type_check (x
->types
[j
], disp
))
3153 pe (x
->op
[j
].disps
);
3158 pte (insn_template
*t
)
3161 fprintf (stdout
, " %d operands ", t
->operands
);
3162 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
3163 if (t
->extension_opcode
!= None
)
3164 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
3165 if (t
->opcode_modifier
.d
)
3166 fprintf (stdout
, "D");
3167 if (t
->opcode_modifier
.w
)
3168 fprintf (stdout
, "W");
3169 fprintf (stdout
, "\n");
3170 for (j
= 0; j
< t
->operands
; j
++)
3172 fprintf (stdout
, " #%d type ", j
+ 1);
3173 pt (t
->operand_types
[j
]);
3174 fprintf (stdout
, "\n");
3181 fprintf (stdout
, " operation %d\n", e
->X_op
);
3182 fprintf (stdout
, " add_number %ld (%lx)\n",
3183 (long) e
->X_add_number
, (long) e
->X_add_number
);
3184 if (e
->X_add_symbol
)
3186 fprintf (stdout
, " add_symbol ");
3187 ps (e
->X_add_symbol
);
3188 fprintf (stdout
, "\n");
3192 fprintf (stdout
, " op_symbol ");
3193 ps (e
->X_op_symbol
);
3194 fprintf (stdout
, "\n");
3201 fprintf (stdout
, "%s type %s%s",
3203 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
3204 segment_name (S_GET_SEGMENT (s
)));
3207 static struct type_name
3209 i386_operand_type mask
;
3212 const type_names
[] =
3214 { OPERAND_TYPE_REG8
, "r8" },
3215 { OPERAND_TYPE_REG16
, "r16" },
3216 { OPERAND_TYPE_REG32
, "r32" },
3217 { OPERAND_TYPE_REG64
, "r64" },
3218 { OPERAND_TYPE_ACC8
, "acc8" },
3219 { OPERAND_TYPE_ACC16
, "acc16" },
3220 { OPERAND_TYPE_ACC32
, "acc32" },
3221 { OPERAND_TYPE_ACC64
, "acc64" },
3222 { OPERAND_TYPE_IMM8
, "i8" },
3223 { OPERAND_TYPE_IMM8
, "i8s" },
3224 { OPERAND_TYPE_IMM16
, "i16" },
3225 { OPERAND_TYPE_IMM32
, "i32" },
3226 { OPERAND_TYPE_IMM32S
, "i32s" },
3227 { OPERAND_TYPE_IMM64
, "i64" },
3228 { OPERAND_TYPE_IMM1
, "i1" },
3229 { OPERAND_TYPE_BASEINDEX
, "BaseIndex" },
3230 { OPERAND_TYPE_DISP8
, "d8" },
3231 { OPERAND_TYPE_DISP16
, "d16" },
3232 { OPERAND_TYPE_DISP32
, "d32" },
3233 { OPERAND_TYPE_DISP32S
, "d32s" },
3234 { OPERAND_TYPE_DISP64
, "d64" },
3235 { OPERAND_TYPE_INOUTPORTREG
, "InOutPortReg" },
3236 { OPERAND_TYPE_SHIFTCOUNT
, "ShiftCount" },
3237 { OPERAND_TYPE_CONTROL
, "control reg" },
3238 { OPERAND_TYPE_TEST
, "test reg" },
3239 { OPERAND_TYPE_DEBUG
, "debug reg" },
3240 { OPERAND_TYPE_FLOATREG
, "FReg" },
3241 { OPERAND_TYPE_FLOATACC
, "FAcc" },
3242 { OPERAND_TYPE_SREG
, "SReg" },
3243 { OPERAND_TYPE_REGMMX
, "rMMX" },
3244 { OPERAND_TYPE_REGXMM
, "rXMM" },
3245 { OPERAND_TYPE_REGYMM
, "rYMM" },
3246 { OPERAND_TYPE_REGZMM
, "rZMM" },
3247 { OPERAND_TYPE_REGMASK
, "Mask reg" },
3251 pt (i386_operand_type t
)
3254 i386_operand_type a
;
3256 for (j
= 0; j
< ARRAY_SIZE (type_names
); j
++)
3258 a
= operand_type_and (t
, type_names
[j
].mask
);
3259 if (operand_type_equal (&a
, &type_names
[j
].mask
))
3260 fprintf (stdout
, "%s, ", type_names
[j
].name
);
3265 #endif /* DEBUG386 */
3267 static bfd_reloc_code_real_type
3268 reloc (unsigned int size
,
3271 bfd_reloc_code_real_type other
)
3273 if (other
!= NO_RELOC
)
3275 reloc_howto_type
*rel
;
3280 case BFD_RELOC_X86_64_GOT32
:
3281 return BFD_RELOC_X86_64_GOT64
;
3283 case BFD_RELOC_X86_64_GOTPLT64
:
3284 return BFD_RELOC_X86_64_GOTPLT64
;
3286 case BFD_RELOC_X86_64_PLTOFF64
:
3287 return BFD_RELOC_X86_64_PLTOFF64
;
3289 case BFD_RELOC_X86_64_GOTPC32
:
3290 other
= BFD_RELOC_X86_64_GOTPC64
;
3292 case BFD_RELOC_X86_64_GOTPCREL
:
3293 other
= BFD_RELOC_X86_64_GOTPCREL64
;
3295 case BFD_RELOC_X86_64_TPOFF32
:
3296 other
= BFD_RELOC_X86_64_TPOFF64
;
3298 case BFD_RELOC_X86_64_DTPOFF32
:
3299 other
= BFD_RELOC_X86_64_DTPOFF64
;
3305 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3306 if (other
== BFD_RELOC_SIZE32
)
3309 other
= BFD_RELOC_SIZE64
;
3312 as_bad (_("there are no pc-relative size relocations"));
3318 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
3319 if (size
== 4 && (flag_code
!= CODE_64BIT
|| disallow_64bit_reloc
))
3322 rel
= bfd_reloc_type_lookup (stdoutput
, other
);
3324 as_bad (_("unknown relocation (%u)"), other
);
3325 else if (size
!= bfd_get_reloc_size (rel
))
3326 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
3327 bfd_get_reloc_size (rel
),
3329 else if (pcrel
&& !rel
->pc_relative
)
3330 as_bad (_("non-pc-relative relocation for pc-relative field"));
3331 else if ((rel
->complain_on_overflow
== complain_overflow_signed
3333 || (rel
->complain_on_overflow
== complain_overflow_unsigned
3335 as_bad (_("relocated field and relocation type differ in signedness"));
3344 as_bad (_("there are no unsigned pc-relative relocations"));
3347 case 1: return BFD_RELOC_8_PCREL
;
3348 case 2: return BFD_RELOC_16_PCREL
;
3349 case 4: return BFD_RELOC_32_PCREL
;
3350 case 8: return BFD_RELOC_64_PCREL
;
3352 as_bad (_("cannot do %u byte pc-relative relocation"), size
);
3359 case 4: return BFD_RELOC_X86_64_32S
;
3364 case 1: return BFD_RELOC_8
;
3365 case 2: return BFD_RELOC_16
;
3366 case 4: return BFD_RELOC_32
;
3367 case 8: return BFD_RELOC_64
;
3369 as_bad (_("cannot do %s %u byte relocation"),
3370 sign
> 0 ? "signed" : "unsigned", size
);
3376 /* Here we decide which fixups can be adjusted to make them relative to
3377 the beginning of the section instead of the symbol. Basically we need
3378 to make sure that the dynamic relocations are done correctly, so in
3379 some cases we force the original symbol to be used. */
3382 tc_i386_fix_adjustable (fixS
*fixP ATTRIBUTE_UNUSED
)
3384 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3388 /* Don't adjust pc-relative references to merge sections in 64-bit
3390 if (use_rela_relocations
3391 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
3395 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
3396 and changed later by validate_fix. */
3397 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
3398 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
3401 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
3402 for size relocations. */
3403 if (fixP
->fx_r_type
== BFD_RELOC_SIZE32
3404 || fixP
->fx_r_type
== BFD_RELOC_SIZE64
3405 || fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
3406 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
3407 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32X
3408 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
3409 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
3410 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
3411 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
3412 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
3413 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
3414 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
3415 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
3416 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTDESC
3417 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_DESC_CALL
3418 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
3419 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
3420 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCRELX
3421 || fixP
->fx_r_type
== BFD_RELOC_X86_64_REX_GOTPCRELX
3422 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
3423 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
3424 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
3425 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
3426 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
3427 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
3428 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
3429 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
3430 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPC32_TLSDESC
3431 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSDESC_CALL
3432 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
3433 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
3440 intel_float_operand (const char *mnemonic
)
3442 /* Note that the value returned is meaningful only for opcodes with (memory)
3443 operands, hence the code here is free to improperly handle opcodes that
3444 have no operands (for better performance and smaller code). */
3446 if (mnemonic
[0] != 'f')
3447 return 0; /* non-math */
3449 switch (mnemonic
[1])
3451 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
3452 the fs segment override prefix not currently handled because no
3453 call path can make opcodes without operands get here */
3455 return 2 /* integer op */;
3457 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
3458 return 3; /* fldcw/fldenv */
3461 if (mnemonic
[2] != 'o' /* fnop */)
3462 return 3; /* non-waiting control op */
3465 if (mnemonic
[2] == 's')
3466 return 3; /* frstor/frstpm */
3469 if (mnemonic
[2] == 'a')
3470 return 3; /* fsave */
3471 if (mnemonic
[2] == 't')
3473 switch (mnemonic
[3])
3475 case 'c': /* fstcw */
3476 case 'd': /* fstdw */
3477 case 'e': /* fstenv */
3478 case 's': /* fsts[gw] */
3484 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
3485 return 0; /* fxsave/fxrstor are not really math ops */
3492 /* Build the VEX prefix. */
3495 build_vex_prefix (const insn_template
*t
)
3497 unsigned int register_specifier
;
3498 unsigned int implied_prefix
;
3499 unsigned int vector_length
;
3502 /* Check register specifier. */
3503 if (i
.vex
.register_specifier
)
3505 register_specifier
=
3506 ~register_number (i
.vex
.register_specifier
) & 0xf;
3507 gas_assert ((i
.vex
.register_specifier
->reg_flags
& RegVRex
) == 0);
3510 register_specifier
= 0xf;
3512 /* Use 2-byte VEX prefix by swapping destination and source operand
3513 if there are more than 1 register operand. */
3514 if (i
.reg_operands
> 1
3515 && i
.vec_encoding
!= vex_encoding_vex3
3516 && i
.dir_encoding
== dir_encoding_default
3517 && i
.operands
== i
.reg_operands
3518 && operand_type_equal (&i
.types
[0], &i
.types
[i
.operands
- 1])
3519 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3520 && (i
.tm
.opcode_modifier
.load
|| i
.tm
.opcode_modifier
.d
)
3523 unsigned int xchg
= i
.operands
- 1;
3524 union i386_op temp_op
;
3525 i386_operand_type temp_type
;
3527 temp_type
= i
.types
[xchg
];
3528 i
.types
[xchg
] = i
.types
[0];
3529 i
.types
[0] = temp_type
;
3530 temp_op
= i
.op
[xchg
];
3531 i
.op
[xchg
] = i
.op
[0];
3534 gas_assert (i
.rm
.mode
== 3);
3538 i
.rm
.regmem
= i
.rm
.reg
;
3541 if (i
.tm
.opcode_modifier
.d
)
3542 i
.tm
.base_opcode
^= (i
.tm
.base_opcode
& 0xee) != 0x6e
3543 ? Opcode_SIMD_FloatD
: Opcode_SIMD_IntD
;
3544 else /* Use the next insn. */
3548 /* Use 2-byte VEX prefix by swapping commutative source operands if there
3549 are no memory operands and at least 3 register ones. */
3550 if (i
.reg_operands
>= 3
3551 && i
.vec_encoding
!= vex_encoding_vex3
3552 && i
.reg_operands
== i
.operands
- i
.imm_operands
3553 && i
.tm
.opcode_modifier
.vex
3554 && i
.tm
.opcode_modifier
.commutative
3555 && (i
.tm
.opcode_modifier
.sse2avx
|| optimize
> 1)
3557 && i
.vex
.register_specifier
3558 && !(i
.vex
.register_specifier
->reg_flags
& RegRex
))
3560 unsigned int xchg
= i
.operands
- i
.reg_operands
;
3561 union i386_op temp_op
;
3562 i386_operand_type temp_type
;
3564 gas_assert (i
.tm
.opcode_modifier
.vexopcode
== VEX0F
);
3565 gas_assert (!i
.tm
.opcode_modifier
.sae
);
3566 gas_assert (operand_type_equal (&i
.types
[i
.operands
- 2],
3567 &i
.types
[i
.operands
- 3]));
3568 gas_assert (i
.rm
.mode
== 3);
3570 temp_type
= i
.types
[xchg
];
3571 i
.types
[xchg
] = i
.types
[xchg
+ 1];
3572 i
.types
[xchg
+ 1] = temp_type
;
3573 temp_op
= i
.op
[xchg
];
3574 i
.op
[xchg
] = i
.op
[xchg
+ 1];
3575 i
.op
[xchg
+ 1] = temp_op
;
3578 xchg
= i
.rm
.regmem
| 8;
3579 i
.rm
.regmem
= ~register_specifier
& 0xf;
3580 gas_assert (!(i
.rm
.regmem
& 8));
3581 i
.vex
.register_specifier
+= xchg
- i
.rm
.regmem
;
3582 register_specifier
= ~xchg
& 0xf;
3585 if (i
.tm
.opcode_modifier
.vex
== VEXScalar
)
3586 vector_length
= avxscalar
;
3587 else if (i
.tm
.opcode_modifier
.vex
== VEX256
)
3593 /* Determine vector length from the last multi-length vector
3596 for (op
= t
->operands
; op
--;)
3597 if (t
->operand_types
[op
].bitfield
.xmmword
3598 && t
->operand_types
[op
].bitfield
.ymmword
3599 && i
.types
[op
].bitfield
.ymmword
)
3606 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3611 case DATA_PREFIX_OPCODE
:
3614 case REPE_PREFIX_OPCODE
:
3617 case REPNE_PREFIX_OPCODE
:
3624 /* Check the REX.W bit and VEXW. */
3625 if (i
.tm
.opcode_modifier
.vexw
== VEXWIG
)
3626 w
= (vexwig
== vexw1
|| (i
.rex
& REX_W
)) ? 1 : 0;
3627 else if (i
.tm
.opcode_modifier
.vexw
)
3628 w
= i
.tm
.opcode_modifier
.vexw
== VEXW1
? 1 : 0;
3630 w
= (flag_code
== CODE_64BIT
? i
.rex
& REX_W
: vexwig
== vexw1
) ? 1 : 0;
3632 /* Use 2-byte VEX prefix if possible. */
3634 && i
.vec_encoding
!= vex_encoding_vex3
3635 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3636 && (i
.rex
& (REX_W
| REX_X
| REX_B
)) == 0)
3638 /* 2-byte VEX prefix. */
3642 i
.vex
.bytes
[0] = 0xc5;
3644 /* Check the REX.R bit. */
3645 r
= (i
.rex
& REX_R
) ? 0 : 1;
3646 i
.vex
.bytes
[1] = (r
<< 7
3647 | register_specifier
<< 3
3648 | vector_length
<< 2
3653 /* 3-byte VEX prefix. */
3658 switch (i
.tm
.opcode_modifier
.vexopcode
)
3662 i
.vex
.bytes
[0] = 0xc4;
3666 i
.vex
.bytes
[0] = 0xc4;
3670 i
.vex
.bytes
[0] = 0xc4;
3674 i
.vex
.bytes
[0] = 0x8f;
3678 i
.vex
.bytes
[0] = 0x8f;
3682 i
.vex
.bytes
[0] = 0x8f;
3688 /* The high 3 bits of the second VEX byte are 1's compliment
3689 of RXB bits from REX. */
3690 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3692 i
.vex
.bytes
[2] = (w
<< 7
3693 | register_specifier
<< 3
3694 | vector_length
<< 2
3699 static INLINE bfd_boolean
3700 is_evex_encoding (const insn_template
*t
)
3702 return t
->opcode_modifier
.evex
|| t
->opcode_modifier
.disp8memshift
3703 || t
->opcode_modifier
.broadcast
|| t
->opcode_modifier
.masking
3704 || t
->opcode_modifier
.sae
;
3707 static INLINE bfd_boolean
3708 is_any_vex_encoding (const insn_template
*t
)
3710 return t
->opcode_modifier
.vex
|| t
->opcode_modifier
.vexopcode
3711 || is_evex_encoding (t
);
3714 /* Build the EVEX prefix. */
3717 build_evex_prefix (void)
3719 unsigned int register_specifier
;
3720 unsigned int implied_prefix
;
3722 rex_byte vrex_used
= 0;
3724 /* Check register specifier. */
3725 if (i
.vex
.register_specifier
)
3727 gas_assert ((i
.vrex
& REX_X
) == 0);
3729 register_specifier
= i
.vex
.register_specifier
->reg_num
;
3730 if ((i
.vex
.register_specifier
->reg_flags
& RegRex
))
3731 register_specifier
+= 8;
3732 /* The upper 16 registers are encoded in the fourth byte of the
3734 if (!(i
.vex
.register_specifier
->reg_flags
& RegVRex
))
3735 i
.vex
.bytes
[3] = 0x8;
3736 register_specifier
= ~register_specifier
& 0xf;
3740 register_specifier
= 0xf;
3742 /* Encode upper 16 vector index register in the fourth byte of
3744 if (!(i
.vrex
& REX_X
))
3745 i
.vex
.bytes
[3] = 0x8;
3750 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3755 case DATA_PREFIX_OPCODE
:
3758 case REPE_PREFIX_OPCODE
:
3761 case REPNE_PREFIX_OPCODE
:
3768 /* 4 byte EVEX prefix. */
3770 i
.vex
.bytes
[0] = 0x62;
3773 switch (i
.tm
.opcode_modifier
.vexopcode
)
3789 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3791 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3793 /* The fifth bit of the second EVEX byte is 1's compliment of the
3794 REX_R bit in VREX. */
3795 if (!(i
.vrex
& REX_R
))
3796 i
.vex
.bytes
[1] |= 0x10;
3800 if ((i
.reg_operands
+ i
.imm_operands
) == i
.operands
)
3802 /* When all operands are registers, the REX_X bit in REX is not
3803 used. We reuse it to encode the upper 16 registers, which is
3804 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3805 as 1's compliment. */
3806 if ((i
.vrex
& REX_B
))
3809 i
.vex
.bytes
[1] &= ~0x40;
3813 /* EVEX instructions shouldn't need the REX prefix. */
3814 i
.vrex
&= ~vrex_used
;
3815 gas_assert (i
.vrex
== 0);
3817 /* Check the REX.W bit and VEXW. */
3818 if (i
.tm
.opcode_modifier
.vexw
== VEXWIG
)
3819 w
= (evexwig
== evexw1
|| (i
.rex
& REX_W
)) ? 1 : 0;
3820 else if (i
.tm
.opcode_modifier
.vexw
)
3821 w
= i
.tm
.opcode_modifier
.vexw
== VEXW1
? 1 : 0;
3823 w
= (flag_code
== CODE_64BIT
? i
.rex
& REX_W
: evexwig
== evexw1
) ? 1 : 0;
3825 /* Encode the U bit. */
3826 implied_prefix
|= 0x4;
3828 /* The third byte of the EVEX prefix. */
3829 i
.vex
.bytes
[2] = (w
<< 7 | register_specifier
<< 3 | implied_prefix
);
3831 /* The fourth byte of the EVEX prefix. */
3832 /* The zeroing-masking bit. */
3833 if (i
.mask
&& i
.mask
->zeroing
)
3834 i
.vex
.bytes
[3] |= 0x80;
3836 /* Don't always set the broadcast bit if there is no RC. */
3839 /* Encode the vector length. */
3840 unsigned int vec_length
;
3842 if (!i
.tm
.opcode_modifier
.evex
3843 || i
.tm
.opcode_modifier
.evex
== EVEXDYN
)
3847 /* Determine vector length from the last multi-length vector
3850 for (op
= i
.operands
; op
--;)
3851 if (i
.tm
.operand_types
[op
].bitfield
.xmmword
3852 + i
.tm
.operand_types
[op
].bitfield
.ymmword
3853 + i
.tm
.operand_types
[op
].bitfield
.zmmword
> 1)
3855 if (i
.types
[op
].bitfield
.zmmword
)
3857 i
.tm
.opcode_modifier
.evex
= EVEX512
;
3860 else if (i
.types
[op
].bitfield
.ymmword
)
3862 i
.tm
.opcode_modifier
.evex
= EVEX256
;
3865 else if (i
.types
[op
].bitfield
.xmmword
)
3867 i
.tm
.opcode_modifier
.evex
= EVEX128
;
3870 else if (i
.broadcast
&& (int) op
== i
.broadcast
->operand
)
3872 switch (i
.broadcast
->bytes
)
3875 i
.tm
.opcode_modifier
.evex
= EVEX512
;
3878 i
.tm
.opcode_modifier
.evex
= EVEX256
;
3881 i
.tm
.opcode_modifier
.evex
= EVEX128
;
3890 if (op
>= MAX_OPERANDS
)
3894 switch (i
.tm
.opcode_modifier
.evex
)
3896 case EVEXLIG
: /* LL' is ignored */
3897 vec_length
= evexlig
<< 5;
3900 vec_length
= 0 << 5;
3903 vec_length
= 1 << 5;
3906 vec_length
= 2 << 5;
3912 i
.vex
.bytes
[3] |= vec_length
;
3913 /* Encode the broadcast bit. */
3915 i
.vex
.bytes
[3] |= 0x10;
3919 if (i
.rounding
->type
!= saeonly
)
3920 i
.vex
.bytes
[3] |= 0x10 | (i
.rounding
->type
<< 5);
3922 i
.vex
.bytes
[3] |= 0x10 | (evexrcig
<< 5);
3925 if (i
.mask
&& i
.mask
->mask
)
3926 i
.vex
.bytes
[3] |= i
.mask
->mask
->reg_num
;
3930 process_immext (void)
3934 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
3935 which is coded in the same place as an 8-bit immediate field
3936 would be. Here we fake an 8-bit immediate operand from the
3937 opcode suffix stored in tm.extension_opcode.
3939 AVX instructions also use this encoding, for some of
3940 3 argument instructions. */
3942 gas_assert (i
.imm_operands
<= 1
3944 || (is_any_vex_encoding (&i
.tm
)
3945 && i
.operands
<= 4)));
3947 exp
= &im_expressions
[i
.imm_operands
++];
3948 i
.op
[i
.operands
].imms
= exp
;
3949 i
.types
[i
.operands
] = imm8
;
3951 exp
->X_op
= O_constant
;
3952 exp
->X_add_number
= i
.tm
.extension_opcode
;
3953 i
.tm
.extension_opcode
= None
;
3960 switch (i
.tm
.opcode_modifier
.hleprefixok
)
3965 as_bad (_("invalid instruction `%s' after `%s'"),
3966 i
.tm
.name
, i
.hle_prefix
);
3969 if (i
.prefix
[LOCK_PREFIX
])
3971 as_bad (_("missing `lock' with `%s'"), i
.hle_prefix
);
3975 case HLEPrefixRelease
:
3976 if (i
.prefix
[HLE_PREFIX
] != XRELEASE_PREFIX_OPCODE
)
3978 as_bad (_("instruction `%s' after `xacquire' not allowed"),
3982 if (i
.mem_operands
== 0 || !(i
.flags
[i
.operands
- 1] & Operand_Mem
))
3984 as_bad (_("memory destination needed for instruction `%s'"
3985 " after `xrelease'"), i
.tm
.name
);
3992 /* Try the shortest encoding by shortening operand size. */
3995 optimize_encoding (void)
3999 if (optimize_for_space
4000 && !is_any_vex_encoding (&i
.tm
)
4001 && i
.reg_operands
== 1
4002 && i
.imm_operands
== 1
4003 && !i
.types
[1].bitfield
.byte
4004 && i
.op
[0].imms
->X_op
== O_constant
4005 && fits_in_imm7 (i
.op
[0].imms
->X_add_number
)
4006 && (i
.tm
.base_opcode
== 0xa8
4007 || (i
.tm
.base_opcode
== 0xf6
4008 && i
.tm
.extension_opcode
== 0x0)))
4011 test $imm7, %r64/%r32/%r16 -> test $imm7, %r8
4013 unsigned int base_regnum
= i
.op
[1].regs
->reg_num
;
4014 if (flag_code
== CODE_64BIT
|| base_regnum
< 4)
4016 i
.types
[1].bitfield
.byte
= 1;
4017 /* Ignore the suffix. */
4019 /* Convert to byte registers. */
4020 if (i
.types
[1].bitfield
.word
)
4022 else if (i
.types
[1].bitfield
.dword
)
4026 if (!(i
.op
[1].regs
->reg_flags
& RegRex
) && base_regnum
< 4)
4031 else if (flag_code
== CODE_64BIT
4032 && !is_any_vex_encoding (&i
.tm
)
4033 && ((i
.types
[1].bitfield
.qword
4034 && i
.reg_operands
== 1
4035 && i
.imm_operands
== 1
4036 && i
.op
[0].imms
->X_op
== O_constant
4037 && ((i
.tm
.base_opcode
== 0xb8
4038 && i
.tm
.extension_opcode
== None
4039 && fits_in_unsigned_long (i
.op
[0].imms
->X_add_number
))
4040 || (fits_in_imm31 (i
.op
[0].imms
->X_add_number
)
4041 && ((i
.tm
.base_opcode
== 0x24
4042 || i
.tm
.base_opcode
== 0xa8)
4043 || (i
.tm
.base_opcode
== 0x80
4044 && i
.tm
.extension_opcode
== 0x4)
4045 || ((i
.tm
.base_opcode
== 0xf6
4046 || (i
.tm
.base_opcode
| 1) == 0xc7)
4047 && i
.tm
.extension_opcode
== 0x0)))
4048 || (fits_in_imm7 (i
.op
[0].imms
->X_add_number
)
4049 && i
.tm
.base_opcode
== 0x83
4050 && i
.tm
.extension_opcode
== 0x4)))
4051 || (i
.types
[0].bitfield
.qword
4052 && ((i
.reg_operands
== 2
4053 && i
.op
[0].regs
== i
.op
[1].regs
4054 && (i
.tm
.base_opcode
== 0x30
4055 || i
.tm
.base_opcode
== 0x28))
4056 || (i
.reg_operands
== 1
4058 && i
.tm
.base_opcode
== 0x30)))))
4061 andq $imm31, %r64 -> andl $imm31, %r32
4062 andq $imm7, %r64 -> andl $imm7, %r32
4063 testq $imm31, %r64 -> testl $imm31, %r32
4064 xorq %r64, %r64 -> xorl %r32, %r32
4065 subq %r64, %r64 -> subl %r32, %r32
4066 movq $imm31, %r64 -> movl $imm31, %r32
4067 movq $imm32, %r64 -> movl $imm32, %r32
4069 i
.tm
.opcode_modifier
.norex64
= 1;
4070 if (i
.tm
.base_opcode
== 0xb8 || (i
.tm
.base_opcode
| 1) == 0xc7)
4073 movq $imm31, %r64 -> movl $imm31, %r32
4074 movq $imm32, %r64 -> movl $imm32, %r32
4076 i
.tm
.operand_types
[0].bitfield
.imm32
= 1;
4077 i
.tm
.operand_types
[0].bitfield
.imm32s
= 0;
4078 i
.tm
.operand_types
[0].bitfield
.imm64
= 0;
4079 i
.types
[0].bitfield
.imm32
= 1;
4080 i
.types
[0].bitfield
.imm32s
= 0;
4081 i
.types
[0].bitfield
.imm64
= 0;
4082 i
.types
[1].bitfield
.dword
= 1;
4083 i
.types
[1].bitfield
.qword
= 0;
4084 if ((i
.tm
.base_opcode
| 1) == 0xc7)
4087 movq $imm31, %r64 -> movl $imm31, %r32
4089 i
.tm
.base_opcode
= 0xb8;
4090 i
.tm
.extension_opcode
= None
;
4091 i
.tm
.opcode_modifier
.w
= 0;
4092 i
.tm
.opcode_modifier
.modrm
= 0;
4096 else if (optimize
> 1
4097 && !optimize_for_space
4098 && !is_any_vex_encoding (&i
.tm
)
4099 && i
.reg_operands
== 2
4100 && i
.op
[0].regs
== i
.op
[1].regs
4101 && ((i
.tm
.base_opcode
& ~(Opcode_D
| 1)) == 0x8
4102 || (i
.tm
.base_opcode
& ~(Opcode_D
| 1)) == 0x20)
4103 && (flag_code
!= CODE_64BIT
|| !i
.types
[0].bitfield
.dword
))
4106 andb %rN, %rN -> testb %rN, %rN
4107 andw %rN, %rN -> testw %rN, %rN
4108 andq %rN, %rN -> testq %rN, %rN
4109 orb %rN, %rN -> testb %rN, %rN
4110 orw %rN, %rN -> testw %rN, %rN
4111 orq %rN, %rN -> testq %rN, %rN
4113 and outside of 64-bit mode
4115 andl %rN, %rN -> testl %rN, %rN
4116 orl %rN, %rN -> testl %rN, %rN
4118 i
.tm
.base_opcode
= 0x84 | (i
.tm
.base_opcode
& 1);
4120 else if (i
.reg_operands
== 3
4121 && i
.op
[0].regs
== i
.op
[1].regs
4122 && !i
.types
[2].bitfield
.xmmword
4123 && (i
.tm
.opcode_modifier
.vex
4124 || ((!i
.mask
|| i
.mask
->zeroing
)
4126 && is_evex_encoding (&i
.tm
)
4127 && (i
.vec_encoding
!= vex_encoding_evex
4128 || cpu_arch_isa_flags
.bitfield
.cpuavx512vl
4129 || i
.tm
.cpu_flags
.bitfield
.cpuavx512vl
4130 || (i
.tm
.operand_types
[2].bitfield
.zmmword
4131 && i
.types
[2].bitfield
.ymmword
))))
4132 && ((i
.tm
.base_opcode
== 0x55
4133 || i
.tm
.base_opcode
== 0x6655
4134 || i
.tm
.base_opcode
== 0x66df
4135 || i
.tm
.base_opcode
== 0x57
4136 || i
.tm
.base_opcode
== 0x6657
4137 || i
.tm
.base_opcode
== 0x66ef
4138 || i
.tm
.base_opcode
== 0x66f8
4139 || i
.tm
.base_opcode
== 0x66f9
4140 || i
.tm
.base_opcode
== 0x66fa
4141 || i
.tm
.base_opcode
== 0x66fb
4142 || i
.tm
.base_opcode
== 0x42
4143 || i
.tm
.base_opcode
== 0x6642
4144 || i
.tm
.base_opcode
== 0x47
4145 || i
.tm
.base_opcode
== 0x6647)
4146 && i
.tm
.extension_opcode
== None
))
4149 VOP, one of vandnps, vandnpd, vxorps, vxorpd, vpsubb, vpsubd,
4151 EVEX VOP %zmmM, %zmmM, %zmmN
4152 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
4153 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4154 EVEX VOP %ymmM, %ymmM, %ymmN
4155 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
4156 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4157 VEX VOP %ymmM, %ymmM, %ymmN
4158 -> VEX VOP %xmmM, %xmmM, %xmmN
4159 VOP, one of vpandn and vpxor:
4160 VEX VOP %ymmM, %ymmM, %ymmN
4161 -> VEX VOP %xmmM, %xmmM, %xmmN
4162 VOP, one of vpandnd and vpandnq:
4163 EVEX VOP %zmmM, %zmmM, %zmmN
4164 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
4165 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4166 EVEX VOP %ymmM, %ymmM, %ymmN
4167 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
4168 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4169 VOP, one of vpxord and vpxorq:
4170 EVEX VOP %zmmM, %zmmM, %zmmN
4171 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
4172 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4173 EVEX VOP %ymmM, %ymmM, %ymmN
4174 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
4175 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4176 VOP, one of kxord and kxorq:
4177 VEX VOP %kM, %kM, %kN
4178 -> VEX kxorw %kM, %kM, %kN
4179 VOP, one of kandnd and kandnq:
4180 VEX VOP %kM, %kM, %kN
4181 -> VEX kandnw %kM, %kM, %kN
4183 if (is_evex_encoding (&i
.tm
))
4185 if (i
.vec_encoding
!= vex_encoding_evex
)
4187 i
.tm
.opcode_modifier
.vex
= VEX128
;
4188 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4189 i
.tm
.opcode_modifier
.evex
= 0;
4191 else if (optimize
> 1)
4192 i
.tm
.opcode_modifier
.evex
= EVEX128
;
4196 else if (i
.tm
.operand_types
[0].bitfield
.class == RegMask
)
4198 i
.tm
.base_opcode
&= 0xff;
4199 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4202 i
.tm
.opcode_modifier
.vex
= VEX128
;
4204 if (i
.tm
.opcode_modifier
.vex
)
4205 for (j
= 0; j
< 3; j
++)
4207 i
.types
[j
].bitfield
.xmmword
= 1;
4208 i
.types
[j
].bitfield
.ymmword
= 0;
4211 else if (i
.vec_encoding
!= vex_encoding_evex
4212 && !i
.types
[0].bitfield
.zmmword
4213 && !i
.types
[1].bitfield
.zmmword
4216 && is_evex_encoding (&i
.tm
)
4217 && ((i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0x666f
4218 || (i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0xf36f
4219 || (i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0xf26f
4220 || (i
.tm
.base_opcode
& ~4) == 0x66db
4221 || (i
.tm
.base_opcode
& ~4) == 0x66eb)
4222 && i
.tm
.extension_opcode
== None
)
4225 VOP, one of vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16,
4226 vmovdqu32 and vmovdqu64:
4227 EVEX VOP %xmmM, %xmmN
4228 -> VEX vmovdqa|vmovdqu %xmmM, %xmmN (M and N < 16)
4229 EVEX VOP %ymmM, %ymmN
4230 -> VEX vmovdqa|vmovdqu %ymmM, %ymmN (M and N < 16)
4232 -> VEX vmovdqa|vmovdqu %xmmM, mem (M < 16)
4234 -> VEX vmovdqa|vmovdqu %ymmM, mem (M < 16)
4236 -> VEX mvmovdqa|vmovdquem, %xmmN (N < 16)
4238 -> VEX vmovdqa|vmovdqu mem, %ymmN (N < 16)
4239 VOP, one of vpand, vpandn, vpor, vpxor:
4240 EVEX VOP{d,q} %xmmL, %xmmM, %xmmN
4241 -> VEX VOP %xmmL, %xmmM, %xmmN (L, M, and N < 16)
4242 EVEX VOP{d,q} %ymmL, %ymmM, %ymmN
4243 -> VEX VOP %ymmL, %ymmM, %ymmN (L, M, and N < 16)
4244 EVEX VOP{d,q} mem, %xmmM, %xmmN
4245 -> VEX VOP mem, %xmmM, %xmmN (M and N < 16)
4246 EVEX VOP{d,q} mem, %ymmM, %ymmN
4247 -> VEX VOP mem, %ymmM, %ymmN (M and N < 16)
4249 for (j
= 0; j
< i
.operands
; j
++)
4250 if (operand_type_check (i
.types
[j
], disp
)
4251 && i
.op
[j
].disps
->X_op
== O_constant
)
4253 /* Since the VEX prefix has 2 or 3 bytes, the EVEX prefix
4254 has 4 bytes, EVEX Disp8 has 1 byte and VEX Disp32 has 4
4255 bytes, we choose EVEX Disp8 over VEX Disp32. */
4256 int evex_disp8
, vex_disp8
;
4257 unsigned int memshift
= i
.memshift
;
4258 offsetT n
= i
.op
[j
].disps
->X_add_number
;
4260 evex_disp8
= fits_in_disp8 (n
);
4262 vex_disp8
= fits_in_disp8 (n
);
4263 if (evex_disp8
!= vex_disp8
)
4265 i
.memshift
= memshift
;
4269 i
.types
[j
].bitfield
.disp8
= vex_disp8
;
4272 if ((i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0xf26f)
4273 i
.tm
.base_opcode
^= 0xf36f ^ 0xf26f;
4274 i
.tm
.opcode_modifier
.vex
4275 = i
.types
[0].bitfield
.ymmword
? VEX256
: VEX128
;
4276 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4277 /* VPAND, VPOR, and VPXOR are commutative. */
4278 if (i
.reg_operands
== 3 && i
.tm
.base_opcode
!= 0x66df)
4279 i
.tm
.opcode_modifier
.commutative
= 1;
4280 i
.tm
.opcode_modifier
.evex
= 0;
4281 i
.tm
.opcode_modifier
.masking
= 0;
4282 i
.tm
.opcode_modifier
.broadcast
= 0;
4283 i
.tm
.opcode_modifier
.disp8memshift
= 0;
4286 i
.types
[j
].bitfield
.disp8
4287 = fits_in_disp8 (i
.op
[j
].disps
->X_add_number
);
4291 /* This is the guts of the machine-dependent assembler. LINE points to a
4292 machine dependent instruction. This function is supposed to emit
4293 the frags/bytes it assembles to. */
4296 md_assemble (char *line
)
4299 char mnemonic
[MAX_MNEM_SIZE
], mnem_suffix
;
4300 const insn_template
*t
;
4302 /* Initialize globals. */
4303 memset (&i
, '\0', sizeof (i
));
4304 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4305 i
.reloc
[j
] = NO_RELOC
;
4306 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
4307 memset (im_expressions
, '\0', sizeof (im_expressions
));
4308 save_stack_p
= save_stack
;
4310 /* First parse an instruction mnemonic & call i386_operand for the operands.
4311 We assume that the scrubber has arranged it so that line[0] is the valid
4312 start of a (possibly prefixed) mnemonic. */
4314 line
= parse_insn (line
, mnemonic
);
4317 mnem_suffix
= i
.suffix
;
4319 line
= parse_operands (line
, mnemonic
);
4321 xfree (i
.memop1_string
);
4322 i
.memop1_string
= NULL
;
4326 /* Now we've parsed the mnemonic into a set of templates, and have the
4327 operands at hand. */
4329 /* All Intel opcodes have reversed operands except for "bound", "enter"
4330 "monitor*", and "mwait*". We also don't reverse intersegment "jmp"
4331 and "call" instructions with 2 immediate operands so that the immediate
4332 segment precedes the offset, as it does when in AT&T mode. */
4335 && (strcmp (mnemonic
, "bound") != 0)
4336 && (strcmp (mnemonic
, "invlpga") != 0)
4337 && (strncmp (mnemonic
, "monitor", 7) != 0)
4338 && (strncmp (mnemonic
, "mwait", 5) != 0)
4339 && !(operand_type_check (i
.types
[0], imm
)
4340 && operand_type_check (i
.types
[1], imm
)))
4343 /* The order of the immediates should be reversed
4344 for 2 immediates extrq and insertq instructions */
4345 if (i
.imm_operands
== 2
4346 && (strcmp (mnemonic
, "extrq") == 0
4347 || strcmp (mnemonic
, "insertq") == 0))
4348 swap_2_operands (0, 1);
4353 /* Don't optimize displacement for movabs since it only takes 64bit
4356 && i
.disp_encoding
!= disp_encoding_32bit
4357 && (flag_code
!= CODE_64BIT
4358 || strcmp (mnemonic
, "movabs") != 0))
4361 /* Next, we find a template that matches the given insn,
4362 making sure the overlap of the given operands types is consistent
4363 with the template operand types. */
4365 if (!(t
= match_template (mnem_suffix
)))
4368 if (sse_check
!= check_none
4369 && !i
.tm
.opcode_modifier
.noavx
4370 && !i
.tm
.cpu_flags
.bitfield
.cpuavx
4371 && !i
.tm
.cpu_flags
.bitfield
.cpuavx512f
4372 && (i
.tm
.cpu_flags
.bitfield
.cpusse
4373 || i
.tm
.cpu_flags
.bitfield
.cpusse2
4374 || i
.tm
.cpu_flags
.bitfield
.cpusse3
4375 || i
.tm
.cpu_flags
.bitfield
.cpussse3
4376 || i
.tm
.cpu_flags
.bitfield
.cpusse4_1
4377 || i
.tm
.cpu_flags
.bitfield
.cpusse4_2
4378 || i
.tm
.cpu_flags
.bitfield
.cpusse4a
4379 || i
.tm
.cpu_flags
.bitfield
.cpupclmul
4380 || i
.tm
.cpu_flags
.bitfield
.cpuaes
4381 || i
.tm
.cpu_flags
.bitfield
.cpusha
4382 || i
.tm
.cpu_flags
.bitfield
.cpugfni
))
4384 (sse_check
== check_warning
4386 : as_bad
) (_("SSE instruction `%s' is used"), i
.tm
.name
);
4389 if (i
.tm
.opcode_modifier
.fwait
)
4390 if (!add_prefix (FWAIT_OPCODE
))
4393 /* Check if REP prefix is OK. */
4394 if (i
.rep_prefix
&& !i
.tm
.opcode_modifier
.repprefixok
)
4396 as_bad (_("invalid instruction `%s' after `%s'"),
4397 i
.tm
.name
, i
.rep_prefix
);
4401 /* Check for lock without a lockable instruction. Destination operand
4402 must be memory unless it is xchg (0x86). */
4403 if (i
.prefix
[LOCK_PREFIX
]
4404 && (!i
.tm
.opcode_modifier
.islockable
4405 || i
.mem_operands
== 0
4406 || (i
.tm
.base_opcode
!= 0x86
4407 && !(i
.flags
[i
.operands
- 1] & Operand_Mem
))))
4409 as_bad (_("expecting lockable instruction after `lock'"));
4413 /* Check for data size prefix on VEX/XOP/EVEX encoded insns. */
4414 if (i
.prefix
[DATA_PREFIX
] && is_any_vex_encoding (&i
.tm
))
4416 as_bad (_("data size prefix invalid with `%s'"), i
.tm
.name
);
4420 /* Check if HLE prefix is OK. */
4421 if (i
.hle_prefix
&& !check_hle ())
4424 /* Check BND prefix. */
4425 if (i
.bnd_prefix
&& !i
.tm
.opcode_modifier
.bndprefixok
)
4426 as_bad (_("expecting valid branch instruction after `bnd'"));
4428 /* Check NOTRACK prefix. */
4429 if (i
.notrack_prefix
&& !i
.tm
.opcode_modifier
.notrackprefixok
)
4430 as_bad (_("expecting indirect branch instruction after `notrack'"));
4432 if (i
.tm
.cpu_flags
.bitfield
.cpumpx
)
4434 if (flag_code
== CODE_64BIT
&& i
.prefix
[ADDR_PREFIX
])
4435 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
4436 else if (flag_code
!= CODE_16BIT
4437 ? i
.prefix
[ADDR_PREFIX
]
4438 : i
.mem_operands
&& !i
.prefix
[ADDR_PREFIX
])
4439 as_bad (_("16-bit address isn't allowed in MPX instructions"));
4442 /* Insert BND prefix. */
4443 if (add_bnd_prefix
&& i
.tm
.opcode_modifier
.bndprefixok
)
4445 if (!i
.prefix
[BND_PREFIX
])
4446 add_prefix (BND_PREFIX_OPCODE
);
4447 else if (i
.prefix
[BND_PREFIX
] != BND_PREFIX_OPCODE
)
4449 as_warn (_("replacing `rep'/`repe' prefix by `bnd'"));
4450 i
.prefix
[BND_PREFIX
] = BND_PREFIX_OPCODE
;
4454 /* Check string instruction segment overrides. */
4455 if (i
.tm
.opcode_modifier
.isstring
>= IS_STRING_ES_OP0
)
4457 gas_assert (i
.mem_operands
);
4458 if (!check_string ())
4460 i
.disp_operands
= 0;
4463 if (optimize
&& !i
.no_optimize
&& i
.tm
.opcode_modifier
.optimize
)
4464 optimize_encoding ();
4466 if (!process_suffix ())
4469 /* Update operand types. */
4470 for (j
= 0; j
< i
.operands
; j
++)
4471 i
.types
[j
] = operand_type_and (i
.types
[j
], i
.tm
.operand_types
[j
]);
4473 /* Make still unresolved immediate matches conform to size of immediate
4474 given in i.suffix. */
4475 if (!finalize_imm ())
4478 if (i
.types
[0].bitfield
.imm1
)
4479 i
.imm_operands
= 0; /* kludge for shift insns. */
4481 /* We only need to check those implicit registers for instructions
4482 with 3 operands or less. */
4483 if (i
.operands
<= 3)
4484 for (j
= 0; j
< i
.operands
; j
++)
4485 if (i
.types
[j
].bitfield
.instance
!= InstanceNone
4486 && !i
.types
[j
].bitfield
.xmmword
)
4489 /* ImmExt should be processed after SSE2AVX. */
4490 if (!i
.tm
.opcode_modifier
.sse2avx
4491 && i
.tm
.opcode_modifier
.immext
)
4494 /* For insns with operands there are more diddles to do to the opcode. */
4497 if (!process_operands ())
4500 else if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
4502 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
4503 as_warn (_("translating to `%sp'"), i
.tm
.name
);
4506 if (is_any_vex_encoding (&i
.tm
))
4508 if (!cpu_arch_flags
.bitfield
.cpui286
)
4510 as_bad (_("instruction `%s' isn't supported outside of protected mode."),
4515 if (i
.tm
.opcode_modifier
.vex
)
4516 build_vex_prefix (t
);
4518 build_evex_prefix ();
4521 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
4522 instructions may define INT_OPCODE as well, so avoid this corner
4523 case for those instructions that use MODRM. */
4524 if (i
.tm
.base_opcode
== INT_OPCODE
4525 && !i
.tm
.opcode_modifier
.modrm
4526 && i
.op
[0].imms
->X_add_number
== 3)
4528 i
.tm
.base_opcode
= INT3_OPCODE
;
4532 if ((i
.tm
.opcode_modifier
.jump
== JUMP
4533 || i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
4534 || i
.tm
.opcode_modifier
.jump
== JUMP_DWORD
)
4535 && i
.op
[0].disps
->X_op
== O_constant
)
4537 /* Convert "jmp constant" (and "call constant") to a jump (call) to
4538 the absolute address given by the constant. Since ix86 jumps and
4539 calls are pc relative, we need to generate a reloc. */
4540 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
4541 i
.op
[0].disps
->X_op
= O_symbol
;
4544 if (i
.tm
.opcode_modifier
.rex64
)
4547 /* For 8 bit registers we need an empty rex prefix. Also if the
4548 instruction already has a prefix, we need to convert old
4549 registers to new ones. */
4551 if ((i
.types
[0].bitfield
.class == Reg
&& i
.types
[0].bitfield
.byte
4552 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
4553 || (i
.types
[1].bitfield
.class == Reg
&& i
.types
[1].bitfield
.byte
4554 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
4555 || (((i
.types
[0].bitfield
.class == Reg
&& i
.types
[0].bitfield
.byte
)
4556 || (i
.types
[1].bitfield
.class == Reg
&& i
.types
[1].bitfield
.byte
))
4561 i
.rex
|= REX_OPCODE
;
4562 for (x
= 0; x
< 2; x
++)
4564 /* Look for 8 bit operand that uses old registers. */
4565 if (i
.types
[x
].bitfield
.class == Reg
&& i
.types
[x
].bitfield
.byte
4566 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
4568 gas_assert (!(i
.op
[x
].regs
->reg_flags
& RegRex
));
4569 /* In case it is "hi" register, give up. */
4570 if (i
.op
[x
].regs
->reg_num
> 3)
4571 as_bad (_("can't encode register '%s%s' in an "
4572 "instruction requiring REX prefix."),
4573 register_prefix
, i
.op
[x
].regs
->reg_name
);
4575 /* Otherwise it is equivalent to the extended register.
4576 Since the encoding doesn't change this is merely
4577 cosmetic cleanup for debug output. */
4579 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
4584 if (i
.rex
== 0 && i
.rex_encoding
)
4586 /* Check if we can add a REX_OPCODE byte. Look for 8 bit operand
4587 that uses legacy register. If it is "hi" register, don't add
4588 the REX_OPCODE byte. */
4590 for (x
= 0; x
< 2; x
++)
4591 if (i
.types
[x
].bitfield
.class == Reg
4592 && i
.types
[x
].bitfield
.byte
4593 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0
4594 && i
.op
[x
].regs
->reg_num
> 3)
4596 gas_assert (!(i
.op
[x
].regs
->reg_flags
& RegRex
));
4597 i
.rex_encoding
= FALSE
;
4606 add_prefix (REX_OPCODE
| i
.rex
);
4608 /* We are ready to output the insn. */
4611 last_insn
.seg
= now_seg
;
4613 if (i
.tm
.opcode_modifier
.isprefix
)
4615 last_insn
.kind
= last_insn_prefix
;
4616 last_insn
.name
= i
.tm
.name
;
4617 last_insn
.file
= as_where (&last_insn
.line
);
4620 last_insn
.kind
= last_insn_other
;
4624 parse_insn (char *line
, char *mnemonic
)
4627 char *token_start
= l
;
4630 const insn_template
*t
;
4636 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
4641 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
4643 as_bad (_("no such instruction: `%s'"), token_start
);
4648 if (!is_space_char (*l
)
4649 && *l
!= END_OF_INSN
4651 || (*l
!= PREFIX_SEPARATOR
4654 as_bad (_("invalid character %s in mnemonic"),
4655 output_invalid (*l
));
4658 if (token_start
== l
)
4660 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
4661 as_bad (_("expecting prefix; got nothing"));
4663 as_bad (_("expecting mnemonic; got nothing"));
4667 /* Look up instruction (or prefix) via hash table. */
4668 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
4670 if (*l
!= END_OF_INSN
4671 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
4672 && current_templates
4673 && current_templates
->start
->opcode_modifier
.isprefix
)
4675 if (!cpu_flags_check_cpu64 (current_templates
->start
->cpu_flags
))
4677 as_bad ((flag_code
!= CODE_64BIT
4678 ? _("`%s' is only supported in 64-bit mode")
4679 : _("`%s' is not supported in 64-bit mode")),
4680 current_templates
->start
->name
);
4683 /* If we are in 16-bit mode, do not allow addr16 or data16.
4684 Similarly, in 32-bit mode, do not allow addr32 or data32. */
4685 if ((current_templates
->start
->opcode_modifier
.size
== SIZE16
4686 || current_templates
->start
->opcode_modifier
.size
== SIZE32
)
4687 && flag_code
!= CODE_64BIT
4688 && ((current_templates
->start
->opcode_modifier
.size
== SIZE32
)
4689 ^ (flag_code
== CODE_16BIT
)))
4691 as_bad (_("redundant %s prefix"),
4692 current_templates
->start
->name
);
4695 if (current_templates
->start
->opcode_length
== 0)
4697 /* Handle pseudo prefixes. */
4698 switch (current_templates
->start
->base_opcode
)
4702 i
.disp_encoding
= disp_encoding_8bit
;
4706 i
.disp_encoding
= disp_encoding_32bit
;
4710 i
.dir_encoding
= dir_encoding_load
;
4714 i
.dir_encoding
= dir_encoding_store
;
4718 i
.vec_encoding
= vex_encoding_vex
;
4722 i
.vec_encoding
= vex_encoding_vex3
;
4726 i
.vec_encoding
= vex_encoding_evex
;
4730 i
.rex_encoding
= TRUE
;
4734 i
.no_optimize
= TRUE
;
4742 /* Add prefix, checking for repeated prefixes. */
4743 switch (add_prefix (current_templates
->start
->base_opcode
))
4748 if (current_templates
->start
->cpu_flags
.bitfield
.cpuibt
)
4749 i
.notrack_prefix
= current_templates
->start
->name
;
4752 if (current_templates
->start
->cpu_flags
.bitfield
.cpuhle
)
4753 i
.hle_prefix
= current_templates
->start
->name
;
4754 else if (current_templates
->start
->cpu_flags
.bitfield
.cpumpx
)
4755 i
.bnd_prefix
= current_templates
->start
->name
;
4757 i
.rep_prefix
= current_templates
->start
->name
;
4763 /* Skip past PREFIX_SEPARATOR and reset token_start. */
4770 if (!current_templates
)
4772 /* Deprecated functionality (new code should use pseudo-prefixes instead):
4773 Check if we should swap operand or force 32bit displacement in
4775 if (mnem_p
- 2 == dot_p
&& dot_p
[1] == 's')
4776 i
.dir_encoding
= dir_encoding_swap
;
4777 else if (mnem_p
- 3 == dot_p
4780 i
.disp_encoding
= disp_encoding_8bit
;
4781 else if (mnem_p
- 4 == dot_p
4785 i
.disp_encoding
= disp_encoding_32bit
;
4790 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
4793 if (!current_templates
)
4796 if (mnem_p
> mnemonic
)
4798 /* See if we can get a match by trimming off a suffix. */
4801 case WORD_MNEM_SUFFIX
:
4802 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
4803 i
.suffix
= SHORT_MNEM_SUFFIX
;
4806 case BYTE_MNEM_SUFFIX
:
4807 case QWORD_MNEM_SUFFIX
:
4808 i
.suffix
= mnem_p
[-1];
4810 current_templates
= (const templates
*) hash_find (op_hash
,
4813 case SHORT_MNEM_SUFFIX
:
4814 case LONG_MNEM_SUFFIX
:
4817 i
.suffix
= mnem_p
[-1];
4819 current_templates
= (const templates
*) hash_find (op_hash
,
4828 if (intel_float_operand (mnemonic
) == 1)
4829 i
.suffix
= SHORT_MNEM_SUFFIX
;
4831 i
.suffix
= LONG_MNEM_SUFFIX
;
4833 current_templates
= (const templates
*) hash_find (op_hash
,
4840 if (!current_templates
)
4842 as_bad (_("no such instruction: `%s'"), token_start
);
4847 if (current_templates
->start
->opcode_modifier
.jump
== JUMP
4848 || current_templates
->start
->opcode_modifier
.jump
== JUMP_BYTE
)
4850 /* Check for a branch hint. We allow ",pt" and ",pn" for
4851 predict taken and predict not taken respectively.
4852 I'm not sure that branch hints actually do anything on loop
4853 and jcxz insns (JumpByte) for current Pentium4 chips. They
4854 may work in the future and it doesn't hurt to accept them
4856 if (l
[0] == ',' && l
[1] == 'p')
4860 if (!add_prefix (DS_PREFIX_OPCODE
))
4864 else if (l
[2] == 'n')
4866 if (!add_prefix (CS_PREFIX_OPCODE
))
4872 /* Any other comma loses. */
4875 as_bad (_("invalid character %s in mnemonic"),
4876 output_invalid (*l
));
4880 /* Check if instruction is supported on specified architecture. */
4882 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
4884 supported
|= cpu_flags_match (t
);
4885 if (supported
== CPU_FLAGS_PERFECT_MATCH
)
4887 if (!cpu_arch_flags
.bitfield
.cpui386
&& (flag_code
!= CODE_16BIT
))
4888 as_warn (_("use .code16 to ensure correct addressing mode"));
4894 if (!(supported
& CPU_FLAGS_64BIT_MATCH
))
4895 as_bad (flag_code
== CODE_64BIT
4896 ? _("`%s' is not supported in 64-bit mode")
4897 : _("`%s' is only supported in 64-bit mode"),
4898 current_templates
->start
->name
);
4900 as_bad (_("`%s' is not supported on `%s%s'"),
4901 current_templates
->start
->name
,
4902 cpu_arch_name
? cpu_arch_name
: default_arch
,
4903 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
4909 parse_operands (char *l
, const char *mnemonic
)
4913 /* 1 if operand is pending after ','. */
4914 unsigned int expecting_operand
= 0;
4916 /* Non-zero if operand parens not balanced. */
4917 unsigned int paren_not_balanced
;
4919 while (*l
!= END_OF_INSN
)
4921 /* Skip optional white space before operand. */
4922 if (is_space_char (*l
))
4924 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
&& *l
!= '"')
4926 as_bad (_("invalid character %s before operand %d"),
4927 output_invalid (*l
),
4931 token_start
= l
; /* After white space. */
4932 paren_not_balanced
= 0;
4933 while (paren_not_balanced
|| *l
!= ',')
4935 if (*l
== END_OF_INSN
)
4937 if (paren_not_balanced
)
4940 as_bad (_("unbalanced parenthesis in operand %d."),
4943 as_bad (_("unbalanced brackets in operand %d."),
4948 break; /* we are done */
4950 else if (!is_operand_char (*l
) && !is_space_char (*l
) && *l
!= '"')
4952 as_bad (_("invalid character %s in operand %d"),
4953 output_invalid (*l
),
4960 ++paren_not_balanced
;
4962 --paren_not_balanced
;
4967 ++paren_not_balanced
;
4969 --paren_not_balanced
;
4973 if (l
!= token_start
)
4974 { /* Yes, we've read in another operand. */
4975 unsigned int operand_ok
;
4976 this_operand
= i
.operands
++;
4977 if (i
.operands
> MAX_OPERANDS
)
4979 as_bad (_("spurious operands; (%d operands/instruction max)"),
4983 i
.types
[this_operand
].bitfield
.unspecified
= 1;
4984 /* Now parse operand adding info to 'i' as we go along. */
4985 END_STRING_AND_SAVE (l
);
4987 if (i
.mem_operands
> 1)
4989 as_bad (_("too many memory references for `%s'"),
4996 i386_intel_operand (token_start
,
4997 intel_float_operand (mnemonic
));
4999 operand_ok
= i386_att_operand (token_start
);
5001 RESTORE_END_STRING (l
);
5007 if (expecting_operand
)
5009 expecting_operand_after_comma
:
5010 as_bad (_("expecting operand after ','; got nothing"));
5015 as_bad (_("expecting operand before ','; got nothing"));
5020 /* Now *l must be either ',' or END_OF_INSN. */
5023 if (*++l
== END_OF_INSN
)
5025 /* Just skip it, if it's \n complain. */
5026 goto expecting_operand_after_comma
;
5028 expecting_operand
= 1;
5035 swap_2_operands (int xchg1
, int xchg2
)
5037 union i386_op temp_op
;
5038 i386_operand_type temp_type
;
5039 unsigned int temp_flags
;
5040 enum bfd_reloc_code_real temp_reloc
;
5042 temp_type
= i
.types
[xchg2
];
5043 i
.types
[xchg2
] = i
.types
[xchg1
];
5044 i
.types
[xchg1
] = temp_type
;
5046 temp_flags
= i
.flags
[xchg2
];
5047 i
.flags
[xchg2
] = i
.flags
[xchg1
];
5048 i
.flags
[xchg1
] = temp_flags
;
5050 temp_op
= i
.op
[xchg2
];
5051 i
.op
[xchg2
] = i
.op
[xchg1
];
5052 i
.op
[xchg1
] = temp_op
;
5054 temp_reloc
= i
.reloc
[xchg2
];
5055 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
5056 i
.reloc
[xchg1
] = temp_reloc
;
5060 if (i
.mask
->operand
== xchg1
)
5061 i
.mask
->operand
= xchg2
;
5062 else if (i
.mask
->operand
== xchg2
)
5063 i
.mask
->operand
= xchg1
;
5067 if (i
.broadcast
->operand
== xchg1
)
5068 i
.broadcast
->operand
= xchg2
;
5069 else if (i
.broadcast
->operand
== xchg2
)
5070 i
.broadcast
->operand
= xchg1
;
5074 if (i
.rounding
->operand
== xchg1
)
5075 i
.rounding
->operand
= xchg2
;
5076 else if (i
.rounding
->operand
== xchg2
)
5077 i
.rounding
->operand
= xchg1
;
5082 swap_operands (void)
5088 swap_2_operands (1, i
.operands
- 2);
5092 swap_2_operands (0, i
.operands
- 1);
5098 if (i
.mem_operands
== 2)
5100 const seg_entry
*temp_seg
;
5101 temp_seg
= i
.seg
[0];
5102 i
.seg
[0] = i
.seg
[1];
5103 i
.seg
[1] = temp_seg
;
5107 /* Try to ensure constant immediates are represented in the smallest
5112 char guess_suffix
= 0;
5116 guess_suffix
= i
.suffix
;
5117 else if (i
.reg_operands
)
5119 /* Figure out a suffix from the last register operand specified.
5120 We can't do this properly yet, i.e. excluding special register
5121 instances, but the following works for instructions with
5122 immediates. In any case, we can't set i.suffix yet. */
5123 for (op
= i
.operands
; --op
>= 0;)
5124 if (i
.types
[op
].bitfield
.class != Reg
)
5126 else if (i
.types
[op
].bitfield
.byte
)
5128 guess_suffix
= BYTE_MNEM_SUFFIX
;
5131 else if (i
.types
[op
].bitfield
.word
)
5133 guess_suffix
= WORD_MNEM_SUFFIX
;
5136 else if (i
.types
[op
].bitfield
.dword
)
5138 guess_suffix
= LONG_MNEM_SUFFIX
;
5141 else if (i
.types
[op
].bitfield
.qword
)
5143 guess_suffix
= QWORD_MNEM_SUFFIX
;
5147 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
5148 guess_suffix
= WORD_MNEM_SUFFIX
;
5150 for (op
= i
.operands
; --op
>= 0;)
5151 if (operand_type_check (i
.types
[op
], imm
))
5153 switch (i
.op
[op
].imms
->X_op
)
5156 /* If a suffix is given, this operand may be shortened. */
5157 switch (guess_suffix
)
5159 case LONG_MNEM_SUFFIX
:
5160 i
.types
[op
].bitfield
.imm32
= 1;
5161 i
.types
[op
].bitfield
.imm64
= 1;
5163 case WORD_MNEM_SUFFIX
:
5164 i
.types
[op
].bitfield
.imm16
= 1;
5165 i
.types
[op
].bitfield
.imm32
= 1;
5166 i
.types
[op
].bitfield
.imm32s
= 1;
5167 i
.types
[op
].bitfield
.imm64
= 1;
5169 case BYTE_MNEM_SUFFIX
:
5170 i
.types
[op
].bitfield
.imm8
= 1;
5171 i
.types
[op
].bitfield
.imm8s
= 1;
5172 i
.types
[op
].bitfield
.imm16
= 1;
5173 i
.types
[op
].bitfield
.imm32
= 1;
5174 i
.types
[op
].bitfield
.imm32s
= 1;
5175 i
.types
[op
].bitfield
.imm64
= 1;
5179 /* If this operand is at most 16 bits, convert it
5180 to a signed 16 bit number before trying to see
5181 whether it will fit in an even smaller size.
5182 This allows a 16-bit operand such as $0xffe0 to
5183 be recognised as within Imm8S range. */
5184 if ((i
.types
[op
].bitfield
.imm16
)
5185 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
5187 i
.op
[op
].imms
->X_add_number
=
5188 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
5191 /* Store 32-bit immediate in 64-bit for 64-bit BFD. */
5192 if ((i
.types
[op
].bitfield
.imm32
)
5193 && ((i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1))
5196 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
5197 ^ ((offsetT
) 1 << 31))
5198 - ((offsetT
) 1 << 31));
5202 = operand_type_or (i
.types
[op
],
5203 smallest_imm_type (i
.op
[op
].imms
->X_add_number
));
5205 /* We must avoid matching of Imm32 templates when 64bit
5206 only immediate is available. */
5207 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
5208 i
.types
[op
].bitfield
.imm32
= 0;
5215 /* Symbols and expressions. */
5217 /* Convert symbolic operand to proper sizes for matching, but don't
5218 prevent matching a set of insns that only supports sizes other
5219 than those matching the insn suffix. */
5221 i386_operand_type mask
, allowed
;
5222 const insn_template
*t
;
5224 operand_type_set (&mask
, 0);
5225 operand_type_set (&allowed
, 0);
5227 for (t
= current_templates
->start
;
5228 t
< current_templates
->end
;
5231 allowed
= operand_type_or (allowed
, t
->operand_types
[op
]);
5232 allowed
= operand_type_and (allowed
, anyimm
);
5234 switch (guess_suffix
)
5236 case QWORD_MNEM_SUFFIX
:
5237 mask
.bitfield
.imm64
= 1;
5238 mask
.bitfield
.imm32s
= 1;
5240 case LONG_MNEM_SUFFIX
:
5241 mask
.bitfield
.imm32
= 1;
5243 case WORD_MNEM_SUFFIX
:
5244 mask
.bitfield
.imm16
= 1;
5246 case BYTE_MNEM_SUFFIX
:
5247 mask
.bitfield
.imm8
= 1;
5252 allowed
= operand_type_and (mask
, allowed
);
5253 if (!operand_type_all_zero (&allowed
))
5254 i
.types
[op
] = operand_type_and (i
.types
[op
], mask
);
5261 /* Try to use the smallest displacement type too. */
5263 optimize_disp (void)
5267 for (op
= i
.operands
; --op
>= 0;)
5268 if (operand_type_check (i
.types
[op
], disp
))
5270 if (i
.op
[op
].disps
->X_op
== O_constant
)
5272 offsetT op_disp
= i
.op
[op
].disps
->X_add_number
;
5274 if (i
.types
[op
].bitfield
.disp16
5275 && (op_disp
& ~(offsetT
) 0xffff) == 0)
5277 /* If this operand is at most 16 bits, convert
5278 to a signed 16 bit number and don't use 64bit
5280 op_disp
= (((op_disp
& 0xffff) ^ 0x8000) - 0x8000);
5281 i
.types
[op
].bitfield
.disp64
= 0;
5284 /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */
5285 if (i
.types
[op
].bitfield
.disp32
5286 && (op_disp
& ~(((offsetT
) 2 << 31) - 1)) == 0)
5288 /* If this operand is at most 32 bits, convert
5289 to a signed 32 bit number and don't use 64bit
5291 op_disp
&= (((offsetT
) 2 << 31) - 1);
5292 op_disp
= (op_disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
5293 i
.types
[op
].bitfield
.disp64
= 0;
5296 if (!op_disp
&& i
.types
[op
].bitfield
.baseindex
)
5298 i
.types
[op
].bitfield
.disp8
= 0;
5299 i
.types
[op
].bitfield
.disp16
= 0;
5300 i
.types
[op
].bitfield
.disp32
= 0;
5301 i
.types
[op
].bitfield
.disp32s
= 0;
5302 i
.types
[op
].bitfield
.disp64
= 0;
5306 else if (flag_code
== CODE_64BIT
)
5308 if (fits_in_signed_long (op_disp
))
5310 i
.types
[op
].bitfield
.disp64
= 0;
5311 i
.types
[op
].bitfield
.disp32s
= 1;
5313 if (i
.prefix
[ADDR_PREFIX
]
5314 && fits_in_unsigned_long (op_disp
))
5315 i
.types
[op
].bitfield
.disp32
= 1;
5317 if ((i
.types
[op
].bitfield
.disp32
5318 || i
.types
[op
].bitfield
.disp32s
5319 || i
.types
[op
].bitfield
.disp16
)
5320 && fits_in_disp8 (op_disp
))
5321 i
.types
[op
].bitfield
.disp8
= 1;
5323 else if (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
5324 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
)
5326 fix_new_exp (frag_now
, frag_more (0) - frag_now
->fr_literal
, 0,
5327 i
.op
[op
].disps
, 0, i
.reloc
[op
]);
5328 i
.types
[op
].bitfield
.disp8
= 0;
5329 i
.types
[op
].bitfield
.disp16
= 0;
5330 i
.types
[op
].bitfield
.disp32
= 0;
5331 i
.types
[op
].bitfield
.disp32s
= 0;
5332 i
.types
[op
].bitfield
.disp64
= 0;
5335 /* We only support 64bit displacement on constants. */
5336 i
.types
[op
].bitfield
.disp64
= 0;
5340 /* Return 1 if there is a match in broadcast bytes between operand
5341 GIVEN and instruction template T. */
5344 match_broadcast_size (const insn_template
*t
, unsigned int given
)
5346 return ((t
->opcode_modifier
.broadcast
== BYTE_BROADCAST
5347 && i
.types
[given
].bitfield
.byte
)
5348 || (t
->opcode_modifier
.broadcast
== WORD_BROADCAST
5349 && i
.types
[given
].bitfield
.word
)
5350 || (t
->opcode_modifier
.broadcast
== DWORD_BROADCAST
5351 && i
.types
[given
].bitfield
.dword
)
5352 || (t
->opcode_modifier
.broadcast
== QWORD_BROADCAST
5353 && i
.types
[given
].bitfield
.qword
));
5356 /* Check if operands are valid for the instruction. */
5359 check_VecOperands (const insn_template
*t
)
5364 /* Templates allowing for ZMMword as well as YMMword and/or XMMword for
5365 any one operand are implicity requiring AVX512VL support if the actual
5366 operand size is YMMword or XMMword. Since this function runs after
5367 template matching, there's no need to check for YMMword/XMMword in
5369 cpu
= cpu_flags_and (t
->cpu_flags
, avx512
);
5370 if (!cpu_flags_all_zero (&cpu
)
5371 && !t
->cpu_flags
.bitfield
.cpuavx512vl
5372 && !cpu_arch_flags
.bitfield
.cpuavx512vl
)
5374 for (op
= 0; op
< t
->operands
; ++op
)
5376 if (t
->operand_types
[op
].bitfield
.zmmword
5377 && (i
.types
[op
].bitfield
.ymmword
5378 || i
.types
[op
].bitfield
.xmmword
))
5380 i
.error
= unsupported
;
5386 /* Without VSIB byte, we can't have a vector register for index. */
5387 if (!t
->opcode_modifier
.vecsib
5389 && (i
.index_reg
->reg_type
.bitfield
.xmmword
5390 || i
.index_reg
->reg_type
.bitfield
.ymmword
5391 || i
.index_reg
->reg_type
.bitfield
.zmmword
))
5393 i
.error
= unsupported_vector_index_register
;
5397 /* Check if default mask is allowed. */
5398 if (t
->opcode_modifier
.nodefmask
5399 && (!i
.mask
|| i
.mask
->mask
->reg_num
== 0))
5401 i
.error
= no_default_mask
;
5405 /* For VSIB byte, we need a vector register for index, and all vector
5406 registers must be distinct. */
5407 if (t
->opcode_modifier
.vecsib
)
5410 || !((t
->opcode_modifier
.vecsib
== VecSIB128
5411 && i
.index_reg
->reg_type
.bitfield
.xmmword
)
5412 || (t
->opcode_modifier
.vecsib
== VecSIB256
5413 && i
.index_reg
->reg_type
.bitfield
.ymmword
)
5414 || (t
->opcode_modifier
.vecsib
== VecSIB512
5415 && i
.index_reg
->reg_type
.bitfield
.zmmword
)))
5417 i
.error
= invalid_vsib_address
;
5421 gas_assert (i
.reg_operands
== 2 || i
.mask
);
5422 if (i
.reg_operands
== 2 && !i
.mask
)
5424 gas_assert (i
.types
[0].bitfield
.class == RegSIMD
);
5425 gas_assert (i
.types
[0].bitfield
.xmmword
5426 || i
.types
[0].bitfield
.ymmword
);
5427 gas_assert (i
.types
[2].bitfield
.class == RegSIMD
);
5428 gas_assert (i
.types
[2].bitfield
.xmmword
5429 || i
.types
[2].bitfield
.ymmword
);
5430 if (operand_check
== check_none
)
5432 if (register_number (i
.op
[0].regs
)
5433 != register_number (i
.index_reg
)
5434 && register_number (i
.op
[2].regs
)
5435 != register_number (i
.index_reg
)
5436 && register_number (i
.op
[0].regs
)
5437 != register_number (i
.op
[2].regs
))
5439 if (operand_check
== check_error
)
5441 i
.error
= invalid_vector_register_set
;
5444 as_warn (_("mask, index, and destination registers should be distinct"));
5446 else if (i
.reg_operands
== 1 && i
.mask
)
5448 if (i
.types
[1].bitfield
.class == RegSIMD
5449 && (i
.types
[1].bitfield
.xmmword
5450 || i
.types
[1].bitfield
.ymmword
5451 || i
.types
[1].bitfield
.zmmword
)
5452 && (register_number (i
.op
[1].regs
)
5453 == register_number (i
.index_reg
)))
5455 if (operand_check
== check_error
)
5457 i
.error
= invalid_vector_register_set
;
5460 if (operand_check
!= check_none
)
5461 as_warn (_("index and destination registers should be distinct"));
5466 /* Check if broadcast is supported by the instruction and is applied
5467 to the memory operand. */
5470 i386_operand_type type
, overlap
;
5472 /* Check if specified broadcast is supported in this instruction,
5473 and its broadcast bytes match the memory operand. */
5474 op
= i
.broadcast
->operand
;
5475 if (!t
->opcode_modifier
.broadcast
5476 || !(i
.flags
[op
] & Operand_Mem
)
5477 || (!i
.types
[op
].bitfield
.unspecified
5478 && !match_broadcast_size (t
, op
)))
5481 i
.error
= unsupported_broadcast
;
5485 i
.broadcast
->bytes
= ((1 << (t
->opcode_modifier
.broadcast
- 1))
5486 * i
.broadcast
->type
);
5487 operand_type_set (&type
, 0);
5488 switch (i
.broadcast
->bytes
)
5491 type
.bitfield
.word
= 1;
5494 type
.bitfield
.dword
= 1;
5497 type
.bitfield
.qword
= 1;
5500 type
.bitfield
.xmmword
= 1;
5503 type
.bitfield
.ymmword
= 1;
5506 type
.bitfield
.zmmword
= 1;
5512 overlap
= operand_type_and (type
, t
->operand_types
[op
]);
5513 if (operand_type_all_zero (&overlap
))
5516 if (t
->opcode_modifier
.checkregsize
)
5520 type
.bitfield
.baseindex
= 1;
5521 for (j
= 0; j
< i
.operands
; ++j
)
5524 && !operand_type_register_match(i
.types
[j
],
5525 t
->operand_types
[j
],
5527 t
->operand_types
[op
]))
5532 /* If broadcast is supported in this instruction, we need to check if
5533 operand of one-element size isn't specified without broadcast. */
5534 else if (t
->opcode_modifier
.broadcast
&& i
.mem_operands
)
5536 /* Find memory operand. */
5537 for (op
= 0; op
< i
.operands
; op
++)
5538 if (i
.flags
[op
] & Operand_Mem
)
5540 gas_assert (op
< i
.operands
);
5541 /* Check size of the memory operand. */
5542 if (match_broadcast_size (t
, op
))
5544 i
.error
= broadcast_needed
;
5549 op
= MAX_OPERANDS
- 1; /* Avoid uninitialized variable warning. */
5551 /* Check if requested masking is supported. */
5554 switch (t
->opcode_modifier
.masking
)
5558 case MERGING_MASKING
:
5559 if (i
.mask
->zeroing
)
5562 i
.error
= unsupported_masking
;
5566 case DYNAMIC_MASKING
:
5567 /* Memory destinations allow only merging masking. */
5568 if (i
.mask
->zeroing
&& i
.mem_operands
)
5570 /* Find memory operand. */
5571 for (op
= 0; op
< i
.operands
; op
++)
5572 if (i
.flags
[op
] & Operand_Mem
)
5574 gas_assert (op
< i
.operands
);
5575 if (op
== i
.operands
- 1)
5577 i
.error
= unsupported_masking
;
5587 /* Check if masking is applied to dest operand. */
5588 if (i
.mask
&& (i
.mask
->operand
!= (int) (i
.operands
- 1)))
5590 i
.error
= mask_not_on_destination
;
5597 if (!t
->opcode_modifier
.sae
5598 || (i
.rounding
->type
!= saeonly
&& !t
->opcode_modifier
.staticrounding
))
5600 i
.error
= unsupported_rc_sae
;
5603 /* If the instruction has several immediate operands and one of
5604 them is rounding, the rounding operand should be the last
5605 immediate operand. */
5606 if (i
.imm_operands
> 1
5607 && i
.rounding
->operand
!= (int) (i
.imm_operands
- 1))
5609 i
.error
= rc_sae_operand_not_last_imm
;
5614 /* Check vector Disp8 operand. */
5615 if (t
->opcode_modifier
.disp8memshift
5616 && i
.disp_encoding
!= disp_encoding_32bit
)
5619 i
.memshift
= t
->opcode_modifier
.broadcast
- 1;
5620 else if (t
->opcode_modifier
.disp8memshift
!= DISP8_SHIFT_VL
)
5621 i
.memshift
= t
->opcode_modifier
.disp8memshift
;
5624 const i386_operand_type
*type
= NULL
;
5627 for (op
= 0; op
< i
.operands
; op
++)
5628 if (i
.flags
[op
] & Operand_Mem
)
5630 if (t
->opcode_modifier
.evex
== EVEXLIG
)
5631 i
.memshift
= 2 + (i
.suffix
== QWORD_MNEM_SUFFIX
);
5632 else if (t
->operand_types
[op
].bitfield
.xmmword
5633 + t
->operand_types
[op
].bitfield
.ymmword
5634 + t
->operand_types
[op
].bitfield
.zmmword
<= 1)
5635 type
= &t
->operand_types
[op
];
5636 else if (!i
.types
[op
].bitfield
.unspecified
)
5637 type
= &i
.types
[op
];
5639 else if (i
.types
[op
].bitfield
.class == RegSIMD
5640 && t
->opcode_modifier
.evex
!= EVEXLIG
)
5642 if (i
.types
[op
].bitfield
.zmmword
)
5644 else if (i
.types
[op
].bitfield
.ymmword
&& i
.memshift
< 5)
5646 else if (i
.types
[op
].bitfield
.xmmword
&& i
.memshift
< 4)
5652 if (type
->bitfield
.zmmword
)
5654 else if (type
->bitfield
.ymmword
)
5656 else if (type
->bitfield
.xmmword
)
5660 /* For the check in fits_in_disp8(). */
5661 if (i
.memshift
== 0)
5665 for (op
= 0; op
< i
.operands
; op
++)
5666 if (operand_type_check (i
.types
[op
], disp
)
5667 && i
.op
[op
].disps
->X_op
== O_constant
)
5669 if (fits_in_disp8 (i
.op
[op
].disps
->X_add_number
))
5671 i
.types
[op
].bitfield
.disp8
= 1;
5674 i
.types
[op
].bitfield
.disp8
= 0;
5683 /* Check if operands are valid for the instruction. Update VEX
5687 VEX_check_operands (const insn_template
*t
)
5689 if (i
.vec_encoding
== vex_encoding_evex
)
5691 /* This instruction must be encoded with EVEX prefix. */
5692 if (!is_evex_encoding (t
))
5694 i
.error
= unsupported
;
5700 if (!t
->opcode_modifier
.vex
)
5702 /* This instruction template doesn't have VEX prefix. */
5703 if (i
.vec_encoding
!= vex_encoding_default
)
5705 i
.error
= unsupported
;
5711 /* Check the special Imm4 cases; must be the first operand. */
5712 if (t
->cpu_flags
.bitfield
.cpuxop
&& t
->operands
== 5)
5714 if (i
.op
[0].imms
->X_op
!= O_constant
5715 || !fits_in_imm4 (i
.op
[0].imms
->X_add_number
))
5721 /* Turn off Imm<N> so that update_imm won't complain. */
5722 operand_type_set (&i
.types
[0], 0);
5728 static const insn_template
*
5729 match_template (char mnem_suffix
)
5731 /* Points to template once we've found it. */
5732 const insn_template
*t
;
5733 i386_operand_type overlap0
, overlap1
, overlap2
, overlap3
;
5734 i386_operand_type overlap4
;
5735 unsigned int found_reverse_match
;
5736 i386_opcode_modifier suffix_check
;
5737 i386_operand_type operand_types
[MAX_OPERANDS
];
5738 int addr_prefix_disp
;
5739 unsigned int j
, size_match
, check_register
;
5740 enum i386_error specific_error
= 0;
5742 #if MAX_OPERANDS != 5
5743 # error "MAX_OPERANDS must be 5."
5746 found_reverse_match
= 0;
5747 addr_prefix_disp
= -1;
5749 /* Prepare for mnemonic suffix check. */
5750 memset (&suffix_check
, 0, sizeof (suffix_check
));
5751 switch (mnem_suffix
)
5753 case BYTE_MNEM_SUFFIX
:
5754 suffix_check
.no_bsuf
= 1;
5756 case WORD_MNEM_SUFFIX
:
5757 suffix_check
.no_wsuf
= 1;
5759 case SHORT_MNEM_SUFFIX
:
5760 suffix_check
.no_ssuf
= 1;
5762 case LONG_MNEM_SUFFIX
:
5763 suffix_check
.no_lsuf
= 1;
5765 case QWORD_MNEM_SUFFIX
:
5766 suffix_check
.no_qsuf
= 1;
5769 /* NB: In Intel syntax, normally we can check for memory operand
5770 size when there is no mnemonic suffix. But jmp and call have
5771 2 different encodings with Dword memory operand size, one with
5772 No_ldSuf and the other without. i.suffix is set to
5773 LONG_DOUBLE_MNEM_SUFFIX to skip the one with No_ldSuf. */
5774 if (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
)
5775 suffix_check
.no_ldsuf
= 1;
5778 /* Must have right number of operands. */
5779 i
.error
= number_of_operands_mismatch
;
5781 for (t
= current_templates
->start
; t
< current_templates
->end
; t
++)
5783 addr_prefix_disp
= -1;
5784 found_reverse_match
= 0;
5786 if (i
.operands
!= t
->operands
)
5789 /* Check processor support. */
5790 i
.error
= unsupported
;
5791 if (cpu_flags_match (t
) != CPU_FLAGS_PERFECT_MATCH
)
5794 /* Check AT&T mnemonic. */
5795 i
.error
= unsupported_with_intel_mnemonic
;
5796 if (intel_mnemonic
&& t
->opcode_modifier
.attmnemonic
)
5799 /* Check AT&T/Intel syntax. */
5800 i
.error
= unsupported_syntax
;
5801 if ((intel_syntax
&& t
->opcode_modifier
.attsyntax
)
5802 || (!intel_syntax
&& t
->opcode_modifier
.intelsyntax
))
5805 /* Check Intel64/AMD64 ISA. */
5809 /* Default: Don't accept Intel64. */
5810 if (t
->opcode_modifier
.isa64
== INTEL64
)
5814 /* -mamd64: Don't accept Intel64 and Intel64 only. */
5815 if (t
->opcode_modifier
.isa64
>= INTEL64
)
5819 /* -mintel64: Don't accept AMD64. */
5820 if (t
->opcode_modifier
.isa64
== AMD64
&& flag_code
== CODE_64BIT
)
5825 /* Check the suffix. */
5826 i
.error
= invalid_instruction_suffix
;
5827 if ((t
->opcode_modifier
.no_bsuf
&& suffix_check
.no_bsuf
)
5828 || (t
->opcode_modifier
.no_wsuf
&& suffix_check
.no_wsuf
)
5829 || (t
->opcode_modifier
.no_lsuf
&& suffix_check
.no_lsuf
)
5830 || (t
->opcode_modifier
.no_ssuf
&& suffix_check
.no_ssuf
)
5831 || (t
->opcode_modifier
.no_qsuf
&& suffix_check
.no_qsuf
)
5832 || (t
->opcode_modifier
.no_ldsuf
&& suffix_check
.no_ldsuf
))
5835 size_match
= operand_size_match (t
);
5839 /* This is intentionally not
5841 if (i.jumpabsolute != (t->opcode_modifier.jump == JUMP_ABSOLUTE))
5843 as the case of a missing * on the operand is accepted (perhaps with
5844 a warning, issued further down). */
5845 if (i
.jumpabsolute
&& t
->opcode_modifier
.jump
!= JUMP_ABSOLUTE
)
5847 i
.error
= operand_type_mismatch
;
5851 for (j
= 0; j
< MAX_OPERANDS
; j
++)
5852 operand_types
[j
] = t
->operand_types
[j
];
5854 /* In general, don't allow 64-bit operands in 32-bit mode. */
5855 if (i
.suffix
== QWORD_MNEM_SUFFIX
5856 && flag_code
!= CODE_64BIT
5858 ? (!t
->opcode_modifier
.ignoresize
5859 && !t
->opcode_modifier
.broadcast
5860 && !intel_float_operand (t
->name
))
5861 : intel_float_operand (t
->name
) != 2)
5862 && ((operand_types
[0].bitfield
.class != RegMMX
5863 && operand_types
[0].bitfield
.class != RegSIMD
)
5864 || (operand_types
[t
->operands
> 1].bitfield
.class != RegMMX
5865 && operand_types
[t
->operands
> 1].bitfield
.class != RegSIMD
))
5866 && (t
->base_opcode
!= 0x0fc7
5867 || t
->extension_opcode
!= 1 /* cmpxchg8b */))
5870 /* In general, don't allow 32-bit operands on pre-386. */
5871 else if (i
.suffix
== LONG_MNEM_SUFFIX
5872 && !cpu_arch_flags
.bitfield
.cpui386
5874 ? (!t
->opcode_modifier
.ignoresize
5875 && !intel_float_operand (t
->name
))
5876 : intel_float_operand (t
->name
) != 2)
5877 && ((operand_types
[0].bitfield
.class != RegMMX
5878 && operand_types
[0].bitfield
.class != RegSIMD
)
5879 || (operand_types
[t
->operands
> 1].bitfield
.class != RegMMX
5880 && operand_types
[t
->operands
> 1].bitfield
.class
5884 /* Do not verify operands when there are none. */
5888 /* We've found a match; break out of loop. */
5892 if (!t
->opcode_modifier
.jump
5893 || t
->opcode_modifier
.jump
== JUMP_ABSOLUTE
)
5895 /* There should be only one Disp operand. */
5896 for (j
= 0; j
< MAX_OPERANDS
; j
++)
5897 if (operand_type_check (operand_types
[j
], disp
))
5899 if (j
< MAX_OPERANDS
)
5901 bfd_boolean override
= (i
.prefix
[ADDR_PREFIX
] != 0);
5903 addr_prefix_disp
= j
;
5905 /* Address size prefix will turn Disp64/Disp32S/Disp32/Disp16
5906 operand into Disp32/Disp32/Disp16/Disp32 operand. */
5910 override
= !override
;
5913 if (operand_types
[j
].bitfield
.disp32
5914 && operand_types
[j
].bitfield
.disp16
)
5916 operand_types
[j
].bitfield
.disp16
= override
;
5917 operand_types
[j
].bitfield
.disp32
= !override
;
5919 operand_types
[j
].bitfield
.disp32s
= 0;
5920 operand_types
[j
].bitfield
.disp64
= 0;
5924 if (operand_types
[j
].bitfield
.disp32s
5925 || operand_types
[j
].bitfield
.disp64
)
5927 operand_types
[j
].bitfield
.disp64
&= !override
;
5928 operand_types
[j
].bitfield
.disp32s
&= !override
;
5929 operand_types
[j
].bitfield
.disp32
= override
;
5931 operand_types
[j
].bitfield
.disp16
= 0;
5937 /* Force 0x8b encoding for "mov foo@GOT, %eax". */
5938 if (i
.reloc
[0] == BFD_RELOC_386_GOT32
&& t
->base_opcode
== 0xa0)
5941 /* We check register size if needed. */
5942 if (t
->opcode_modifier
.checkregsize
)
5944 check_register
= (1 << t
->operands
) - 1;
5946 check_register
&= ~(1 << i
.broadcast
->operand
);
5951 overlap0
= operand_type_and (i
.types
[0], operand_types
[0]);
5952 switch (t
->operands
)
5955 if (!operand_type_match (overlap0
, i
.types
[0]))
5959 /* xchg %eax, %eax is a special case. It is an alias for nop
5960 only in 32bit mode and we can use opcode 0x90. In 64bit
5961 mode, we can't use 0x90 for xchg %eax, %eax since it should
5962 zero-extend %eax to %rax. */
5963 if (flag_code
== CODE_64BIT
5964 && t
->base_opcode
== 0x90
5965 && i
.types
[0].bitfield
.instance
== Accum
5966 && i
.types
[0].bitfield
.dword
5967 && i
.types
[1].bitfield
.instance
== Accum
5968 && i
.types
[1].bitfield
.dword
)
5970 /* xrelease mov %eax, <disp> is another special case. It must not
5971 match the accumulator-only encoding of mov. */
5972 if (flag_code
!= CODE_64BIT
5974 && t
->base_opcode
== 0xa0
5975 && i
.types
[0].bitfield
.instance
== Accum
5976 && (i
.flags
[1] & Operand_Mem
))
5981 if (!(size_match
& MATCH_STRAIGHT
))
5983 /* Reverse direction of operands if swapping is possible in the first
5984 place (operands need to be symmetric) and
5985 - the load form is requested, and the template is a store form,
5986 - the store form is requested, and the template is a load form,
5987 - the non-default (swapped) form is requested. */
5988 overlap1
= operand_type_and (operand_types
[0], operand_types
[1]);
5989 if (t
->opcode_modifier
.d
&& i
.reg_operands
== i
.operands
5990 && !operand_type_all_zero (&overlap1
))
5991 switch (i
.dir_encoding
)
5993 case dir_encoding_load
:
5994 if (operand_type_check (operand_types
[i
.operands
- 1], anymem
)
5995 || t
->opcode_modifier
.regmem
)
5999 case dir_encoding_store
:
6000 if (!operand_type_check (operand_types
[i
.operands
- 1], anymem
)
6001 && !t
->opcode_modifier
.regmem
)
6005 case dir_encoding_swap
:
6008 case dir_encoding_default
:
6011 /* If we want store form, we skip the current load. */
6012 if ((i
.dir_encoding
== dir_encoding_store
6013 || i
.dir_encoding
== dir_encoding_swap
)
6014 && i
.mem_operands
== 0
6015 && t
->opcode_modifier
.load
)
6020 overlap1
= operand_type_and (i
.types
[1], operand_types
[1]);
6021 if (!operand_type_match (overlap0
, i
.types
[0])
6022 || !operand_type_match (overlap1
, i
.types
[1])
6023 || ((check_register
& 3) == 3
6024 && !operand_type_register_match (i
.types
[0],
6029 /* Check if other direction is valid ... */
6030 if (!t
->opcode_modifier
.d
)
6034 if (!(size_match
& MATCH_REVERSE
))
6036 /* Try reversing direction of operands. */
6037 overlap0
= operand_type_and (i
.types
[0], operand_types
[i
.operands
- 1]);
6038 overlap1
= operand_type_and (i
.types
[i
.operands
- 1], operand_types
[0]);
6039 if (!operand_type_match (overlap0
, i
.types
[0])
6040 || !operand_type_match (overlap1
, i
.types
[i
.operands
- 1])
6042 && !operand_type_register_match (i
.types
[0],
6043 operand_types
[i
.operands
- 1],
6044 i
.types
[i
.operands
- 1],
6047 /* Does not match either direction. */
6050 /* found_reverse_match holds which of D or FloatR
6052 if (!t
->opcode_modifier
.d
)
6053 found_reverse_match
= 0;
6054 else if (operand_types
[0].bitfield
.tbyte
)
6055 found_reverse_match
= Opcode_FloatD
;
6056 else if (operand_types
[0].bitfield
.xmmword
6057 || operand_types
[i
.operands
- 1].bitfield
.xmmword
6058 || operand_types
[0].bitfield
.class == RegMMX
6059 || operand_types
[i
.operands
- 1].bitfield
.class == RegMMX
6060 || is_any_vex_encoding(t
))
6061 found_reverse_match
= (t
->base_opcode
& 0xee) != 0x6e
6062 ? Opcode_SIMD_FloatD
: Opcode_SIMD_IntD
;
6064 found_reverse_match
= Opcode_D
;
6065 if (t
->opcode_modifier
.floatr
)
6066 found_reverse_match
|= Opcode_FloatR
;
6070 /* Found a forward 2 operand match here. */
6071 switch (t
->operands
)
6074 overlap4
= operand_type_and (i
.types
[4],
6078 overlap3
= operand_type_and (i
.types
[3],
6082 overlap2
= operand_type_and (i
.types
[2],
6087 switch (t
->operands
)
6090 if (!operand_type_match (overlap4
, i
.types
[4])
6091 || !operand_type_register_match (i
.types
[3],
6098 if (!operand_type_match (overlap3
, i
.types
[3])
6099 || ((check_register
& 0xa) == 0xa
6100 && !operand_type_register_match (i
.types
[1],
6104 || ((check_register
& 0xc) == 0xc
6105 && !operand_type_register_match (i
.types
[2],
6112 /* Here we make use of the fact that there are no
6113 reverse match 3 operand instructions. */
6114 if (!operand_type_match (overlap2
, i
.types
[2])
6115 || ((check_register
& 5) == 5
6116 && !operand_type_register_match (i
.types
[0],
6120 || ((check_register
& 6) == 6
6121 && !operand_type_register_match (i
.types
[1],
6129 /* Found either forward/reverse 2, 3 or 4 operand match here:
6130 slip through to break. */
6133 /* Check if vector and VEX operands are valid. */
6134 if (check_VecOperands (t
) || VEX_check_operands (t
))
6136 specific_error
= i
.error
;
6140 /* We've found a match; break out of loop. */
6144 if (t
== current_templates
->end
)
6146 /* We found no match. */
6147 const char *err_msg
;
6148 switch (specific_error
? specific_error
: i
.error
)
6152 case operand_size_mismatch
:
6153 err_msg
= _("operand size mismatch");
6155 case operand_type_mismatch
:
6156 err_msg
= _("operand type mismatch");
6158 case register_type_mismatch
:
6159 err_msg
= _("register type mismatch");
6161 case number_of_operands_mismatch
:
6162 err_msg
= _("number of operands mismatch");
6164 case invalid_instruction_suffix
:
6165 err_msg
= _("invalid instruction suffix");
6168 err_msg
= _("constant doesn't fit in 4 bits");
6170 case unsupported_with_intel_mnemonic
:
6171 err_msg
= _("unsupported with Intel mnemonic");
6173 case unsupported_syntax
:
6174 err_msg
= _("unsupported syntax");
6177 as_bad (_("unsupported instruction `%s'"),
6178 current_templates
->start
->name
);
6180 case invalid_vsib_address
:
6181 err_msg
= _("invalid VSIB address");
6183 case invalid_vector_register_set
:
6184 err_msg
= _("mask, index, and destination registers must be distinct");
6186 case unsupported_vector_index_register
:
6187 err_msg
= _("unsupported vector index register");
6189 case unsupported_broadcast
:
6190 err_msg
= _("unsupported broadcast");
6192 case broadcast_needed
:
6193 err_msg
= _("broadcast is needed for operand of such type");
6195 case unsupported_masking
:
6196 err_msg
= _("unsupported masking");
6198 case mask_not_on_destination
:
6199 err_msg
= _("mask not on destination operand");
6201 case no_default_mask
:
6202 err_msg
= _("default mask isn't allowed");
6204 case unsupported_rc_sae
:
6205 err_msg
= _("unsupported static rounding/sae");
6207 case rc_sae_operand_not_last_imm
:
6209 err_msg
= _("RC/SAE operand must precede immediate operands");
6211 err_msg
= _("RC/SAE operand must follow immediate operands");
6213 case invalid_register_operand
:
6214 err_msg
= _("invalid register operand");
6217 as_bad (_("%s for `%s'"), err_msg
,
6218 current_templates
->start
->name
);
6222 if (!quiet_warnings
)
6225 && (i
.jumpabsolute
!= (t
->opcode_modifier
.jump
== JUMP_ABSOLUTE
)))
6226 as_warn (_("indirect %s without `*'"), t
->name
);
6228 if (t
->opcode_modifier
.isprefix
6229 && t
->opcode_modifier
.ignoresize
)
6231 /* Warn them that a data or address size prefix doesn't
6232 affect assembly of the next line of code. */
6233 as_warn (_("stand-alone `%s' prefix"), t
->name
);
6237 /* Copy the template we found. */
6240 if (addr_prefix_disp
!= -1)
6241 i
.tm
.operand_types
[addr_prefix_disp
]
6242 = operand_types
[addr_prefix_disp
];
6244 if (found_reverse_match
)
6246 /* If we found a reverse match we must alter the opcode direction
6247 bit and clear/flip the regmem modifier one. found_reverse_match
6248 holds bits to change (different for int & float insns). */
6250 i
.tm
.base_opcode
^= found_reverse_match
;
6252 i
.tm
.operand_types
[0] = operand_types
[i
.operands
- 1];
6253 i
.tm
.operand_types
[i
.operands
- 1] = operand_types
[0];
6255 /* Certain SIMD insns have their load forms specified in the opcode
6256 table, and hence we need to _set_ RegMem instead of clearing it.
6257 We need to avoid setting the bit though on insns like KMOVW. */
6258 i
.tm
.opcode_modifier
.regmem
6259 = i
.tm
.opcode_modifier
.modrm
&& i
.tm
.opcode_modifier
.d
6260 && i
.tm
.operands
> 2U - i
.tm
.opcode_modifier
.sse2avx
6261 && !i
.tm
.opcode_modifier
.regmem
;
6270 unsigned int es_op
= i
.tm
.opcode_modifier
.isstring
- IS_STRING_ES_OP0
;
6271 unsigned int op
= i
.tm
.operand_types
[0].bitfield
.baseindex
? es_op
: 0;
6273 if (i
.seg
[op
] != NULL
&& i
.seg
[op
] != &es
)
6275 as_bad (_("`%s' operand %u must use `%ses' segment"),
6277 intel_syntax
? i
.tm
.operands
- es_op
: es_op
+ 1,
6282 /* There's only ever one segment override allowed per instruction.
6283 This instruction possibly has a legal segment override on the
6284 second operand, so copy the segment to where non-string
6285 instructions store it, allowing common code. */
6286 i
.seg
[op
] = i
.seg
[1];
6292 process_suffix (void)
6294 /* If matched instruction specifies an explicit instruction mnemonic
6296 if (i
.tm
.opcode_modifier
.size
== SIZE16
)
6297 i
.suffix
= WORD_MNEM_SUFFIX
;
6298 else if (i
.tm
.opcode_modifier
.size
== SIZE32
)
6299 i
.suffix
= LONG_MNEM_SUFFIX
;
6300 else if (i
.tm
.opcode_modifier
.size
== SIZE64
)
6301 i
.suffix
= QWORD_MNEM_SUFFIX
;
6302 else if (i
.reg_operands
6303 && (i
.operands
> 1 || i
.types
[0].bitfield
.class == Reg
)
6304 && !i
.tm
.opcode_modifier
.addrprefixopreg
)
6306 unsigned int numop
= i
.operands
;
6308 /* movsx/movzx want only their source operand considered here, for the
6309 ambiguity checking below. The suffix will be replaced afterwards
6310 to represent the destination (register). */
6311 if (((i
.tm
.base_opcode
| 8) == 0xfbe && i
.tm
.opcode_modifier
.w
)
6312 || (i
.tm
.base_opcode
== 0x63 && i
.tm
.cpu_flags
.bitfield
.cpu64
))
6315 /* If there's no instruction mnemonic suffix we try to invent one
6316 based on GPR operands. */
6319 /* We take i.suffix from the last register operand specified,
6320 Destination register type is more significant than source
6321 register type. crc32 in SSE4.2 prefers source register
6323 unsigned int op
= i
.tm
.base_opcode
!= 0xf20f38f0 ? i
.operands
: 1;
6326 if (i
.tm
.operand_types
[op
].bitfield
.instance
== InstanceNone
6327 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
6329 if (i
.types
[op
].bitfield
.class != Reg
)
6331 if (i
.types
[op
].bitfield
.byte
)
6332 i
.suffix
= BYTE_MNEM_SUFFIX
;
6333 else if (i
.types
[op
].bitfield
.word
)
6334 i
.suffix
= WORD_MNEM_SUFFIX
;
6335 else if (i
.types
[op
].bitfield
.dword
)
6336 i
.suffix
= LONG_MNEM_SUFFIX
;
6337 else if (i
.types
[op
].bitfield
.qword
)
6338 i
.suffix
= QWORD_MNEM_SUFFIX
;
6344 /* As an exception, movsx/movzx silently default to a byte source
6346 if ((i
.tm
.base_opcode
| 8) == 0xfbe && i
.tm
.opcode_modifier
.w
6347 && !i
.suffix
&& !intel_syntax
)
6348 i
.suffix
= BYTE_MNEM_SUFFIX
;
6350 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
6353 && i
.tm
.opcode_modifier
.ignoresize
6354 && i
.tm
.opcode_modifier
.no_bsuf
)
6356 else if (!check_byte_reg ())
6359 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
6362 && i
.tm
.opcode_modifier
.ignoresize
6363 && i
.tm
.opcode_modifier
.no_lsuf
6364 && !i
.tm
.opcode_modifier
.todword
6365 && !i
.tm
.opcode_modifier
.toqword
)
6367 else if (!check_long_reg ())
6370 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
6373 && i
.tm
.opcode_modifier
.ignoresize
6374 && i
.tm
.opcode_modifier
.no_qsuf
6375 && !i
.tm
.opcode_modifier
.todword
6376 && !i
.tm
.opcode_modifier
.toqword
)
6378 else if (!check_qword_reg ())
6381 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
6384 && i
.tm
.opcode_modifier
.ignoresize
6385 && i
.tm
.opcode_modifier
.no_wsuf
)
6387 else if (!check_word_reg ())
6390 else if (intel_syntax
&& i
.tm
.opcode_modifier
.ignoresize
)
6391 /* Do nothing if the instruction is going to ignore the prefix. */
6396 /* Undo the movsx/movzx change done above. */
6399 else if (i
.tm
.opcode_modifier
.defaultsize
&& !i
.suffix
)
6401 i
.suffix
= stackop_size
;
6402 if (stackop_size
== LONG_MNEM_SUFFIX
)
6404 /* stackop_size is set to LONG_MNEM_SUFFIX for the
6405 .code16gcc directive to support 16-bit mode with
6406 32-bit address. For IRET without a suffix, generate
6407 16-bit IRET (opcode 0xcf) to return from an interrupt
6409 if (i
.tm
.base_opcode
== 0xcf)
6411 i
.suffix
= WORD_MNEM_SUFFIX
;
6412 as_warn (_("generating 16-bit `iret' for .code16gcc directive"));
6414 /* Warn about changed behavior for segment register push/pop. */
6415 else if ((i
.tm
.base_opcode
| 1) == 0x07)
6416 as_warn (_("generating 32-bit `%s', unlike earlier gas versions"),
6421 && (i
.tm
.opcode_modifier
.jump
== JUMP_ABSOLUTE
6422 || i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
6423 || i
.tm
.opcode_modifier
.jump
== JUMP_INTERSEGMENT
6424 || (i
.tm
.base_opcode
== 0x0f01 /* [ls][gi]dt */
6425 && i
.tm
.extension_opcode
<= 3)))
6430 if (!i
.tm
.opcode_modifier
.no_qsuf
)
6432 i
.suffix
= QWORD_MNEM_SUFFIX
;
6437 if (!i
.tm
.opcode_modifier
.no_lsuf
)
6438 i
.suffix
= LONG_MNEM_SUFFIX
;
6441 if (!i
.tm
.opcode_modifier
.no_wsuf
)
6442 i
.suffix
= WORD_MNEM_SUFFIX
;
6448 && (!i
.tm
.opcode_modifier
.defaultsize
6449 /* Also cover lret/retf/iret in 64-bit mode. */
6450 || (flag_code
== CODE_64BIT
6451 && !i
.tm
.opcode_modifier
.no_lsuf
6452 && !i
.tm
.opcode_modifier
.no_qsuf
))
6453 && !i
.tm
.opcode_modifier
.ignoresize
6454 /* Accept FLDENV et al without suffix. */
6455 && (i
.tm
.opcode_modifier
.no_ssuf
|| i
.tm
.opcode_modifier
.floatmf
))
6457 unsigned int suffixes
, evex
= 0;
6459 suffixes
= !i
.tm
.opcode_modifier
.no_bsuf
;
6460 if (!i
.tm
.opcode_modifier
.no_wsuf
)
6462 if (!i
.tm
.opcode_modifier
.no_lsuf
)
6464 if (!i
.tm
.opcode_modifier
.no_ldsuf
)
6466 if (!i
.tm
.opcode_modifier
.no_ssuf
)
6468 if (flag_code
== CODE_64BIT
&& !i
.tm
.opcode_modifier
.no_qsuf
)
6471 /* For [XYZ]MMWORD operands inspect operand sizes. While generally
6472 also suitable for AT&T syntax mode, it was requested that this be
6473 restricted to just Intel syntax. */
6474 if (intel_syntax
&& is_any_vex_encoding (&i
.tm
) && !i
.broadcast
)
6478 for (op
= 0; op
< i
.tm
.operands
; ++op
)
6480 if (is_evex_encoding (&i
.tm
)
6481 && !cpu_arch_flags
.bitfield
.cpuavx512vl
)
6483 if (i
.tm
.operand_types
[op
].bitfield
.ymmword
)
6484 i
.tm
.operand_types
[op
].bitfield
.xmmword
= 0;
6485 if (i
.tm
.operand_types
[op
].bitfield
.zmmword
)
6486 i
.tm
.operand_types
[op
].bitfield
.ymmword
= 0;
6487 if (!i
.tm
.opcode_modifier
.evex
6488 || i
.tm
.opcode_modifier
.evex
== EVEXDYN
)
6489 i
.tm
.opcode_modifier
.evex
= EVEX512
;
6492 if (i
.tm
.operand_types
[op
].bitfield
.xmmword
6493 + i
.tm
.operand_types
[op
].bitfield
.ymmword
6494 + i
.tm
.operand_types
[op
].bitfield
.zmmword
< 2)
6497 /* Any properly sized operand disambiguates the insn. */
6498 if (i
.types
[op
].bitfield
.xmmword
6499 || i
.types
[op
].bitfield
.ymmword
6500 || i
.types
[op
].bitfield
.zmmword
)
6502 suffixes
&= ~(7 << 6);
6507 if ((i
.flags
[op
] & Operand_Mem
)
6508 && i
.tm
.operand_types
[op
].bitfield
.unspecified
)
6510 if (i
.tm
.operand_types
[op
].bitfield
.xmmword
)
6512 if (i
.tm
.operand_types
[op
].bitfield
.ymmword
)
6514 if (i
.tm
.operand_types
[op
].bitfield
.zmmword
)
6516 if (is_evex_encoding (&i
.tm
))
6522 /* Are multiple suffixes / operand sizes allowed? */
6523 if (suffixes
& (suffixes
- 1))
6526 && (!i
.tm
.opcode_modifier
.defaultsize
6527 || operand_check
== check_error
))
6529 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
6532 if (operand_check
== check_error
)
6534 as_bad (_("no instruction mnemonic suffix given and "
6535 "no register operands; can't size `%s'"), i
.tm
.name
);
6538 if (operand_check
== check_warning
)
6539 as_warn (_("%s; using default for `%s'"),
6541 ? _("ambiguous operand size")
6542 : _("no instruction mnemonic suffix given and "
6543 "no register operands"),
6546 if (i
.tm
.opcode_modifier
.floatmf
)
6547 i
.suffix
= SHORT_MNEM_SUFFIX
;
6548 else if ((i
.tm
.base_opcode
| 8) == 0xfbe
6549 || (i
.tm
.base_opcode
== 0x63
6550 && i
.tm
.cpu_flags
.bitfield
.cpu64
))
6551 /* handled below */;
6553 i
.tm
.opcode_modifier
.evex
= evex
;
6554 else if (flag_code
== CODE_16BIT
)
6555 i
.suffix
= WORD_MNEM_SUFFIX
;
6556 else if (!i
.tm
.opcode_modifier
.no_lsuf
)
6557 i
.suffix
= LONG_MNEM_SUFFIX
;
6559 i
.suffix
= QWORD_MNEM_SUFFIX
;
6563 if ((i
.tm
.base_opcode
| 8) == 0xfbe
6564 || (i
.tm
.base_opcode
== 0x63 && i
.tm
.cpu_flags
.bitfield
.cpu64
))
6566 /* In Intel syntax, movsx/movzx must have a "suffix" (checked above).
6567 In AT&T syntax, if there is no suffix (warned about above), the default
6568 will be byte extension. */
6569 if (i
.tm
.opcode_modifier
.w
&& i
.suffix
&& i
.suffix
!= BYTE_MNEM_SUFFIX
)
6570 i
.tm
.base_opcode
|= 1;
6572 /* For further processing, the suffix should represent the destination
6573 (register). This is already the case when one was used with
6574 mov[sz][bw]*, but we need to replace it for mov[sz]x, or if there was
6575 no suffix to begin with. */
6576 if (i
.tm
.opcode_modifier
.w
|| i
.tm
.base_opcode
== 0x63 || !i
.suffix
)
6578 if (i
.types
[1].bitfield
.word
)
6579 i
.suffix
= WORD_MNEM_SUFFIX
;
6580 else if (i
.types
[1].bitfield
.qword
)
6581 i
.suffix
= QWORD_MNEM_SUFFIX
;
6583 i
.suffix
= LONG_MNEM_SUFFIX
;
6585 i
.tm
.opcode_modifier
.w
= 0;
6589 if (!i
.tm
.opcode_modifier
.modrm
&& i
.reg_operands
&& i
.tm
.operands
< 3)
6590 i
.short_form
= (i
.tm
.operand_types
[0].bitfield
.class == Reg
)
6591 != (i
.tm
.operand_types
[1].bitfield
.class == Reg
);
6593 /* Change the opcode based on the operand size given by i.suffix. */
6596 /* Size floating point instruction. */
6597 case LONG_MNEM_SUFFIX
:
6598 if (i
.tm
.opcode_modifier
.floatmf
)
6600 i
.tm
.base_opcode
^= 4;
6604 case WORD_MNEM_SUFFIX
:
6605 case QWORD_MNEM_SUFFIX
:
6606 /* It's not a byte, select word/dword operation. */
6607 if (i
.tm
.opcode_modifier
.w
)
6610 i
.tm
.base_opcode
|= 8;
6612 i
.tm
.base_opcode
|= 1;
6615 case SHORT_MNEM_SUFFIX
:
6616 /* Now select between word & dword operations via the operand
6617 size prefix, except for instructions that will ignore this
6619 if (i
.suffix
!= QWORD_MNEM_SUFFIX
6620 && !i
.tm
.opcode_modifier
.ignoresize
6621 && !i
.tm
.opcode_modifier
.floatmf
6622 && !is_any_vex_encoding (&i
.tm
)
6623 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
6624 || (flag_code
== CODE_64BIT
6625 && i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
)))
6627 unsigned int prefix
= DATA_PREFIX_OPCODE
;
6629 if (i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
) /* jcxz, loop */
6630 prefix
= ADDR_PREFIX_OPCODE
;
6632 if (!add_prefix (prefix
))
6636 /* Set mode64 for an operand. */
6637 if (i
.suffix
== QWORD_MNEM_SUFFIX
6638 && flag_code
== CODE_64BIT
6639 && !i
.tm
.opcode_modifier
.norex64
6640 /* Special case for xchg %rax,%rax. It is NOP and doesn't
6642 && ! (i
.operands
== 2
6643 && i
.tm
.base_opcode
== 0x90
6644 && i
.tm
.extension_opcode
== None
6645 && i
.types
[0].bitfield
.instance
== Accum
6646 && i
.types
[0].bitfield
.qword
6647 && i
.types
[1].bitfield
.instance
== Accum
6648 && i
.types
[1].bitfield
.qword
))
6654 if (i
.tm
.opcode_modifier
.addrprefixopreg
)
6656 gas_assert (!i
.suffix
);
6657 gas_assert (i
.reg_operands
);
6659 if (i
.tm
.operand_types
[0].bitfield
.instance
== Accum
6662 /* The address size override prefix changes the size of the
6664 if (flag_code
== CODE_64BIT
6665 && i
.op
[0].regs
->reg_type
.bitfield
.word
)
6667 as_bad (_("16-bit addressing unavailable for `%s'"),
6672 if ((flag_code
== CODE_32BIT
6673 ? i
.op
[0].regs
->reg_type
.bitfield
.word
6674 : i
.op
[0].regs
->reg_type
.bitfield
.dword
)
6675 && !add_prefix (ADDR_PREFIX_OPCODE
))
6680 /* Check invalid register operand when the address size override
6681 prefix changes the size of register operands. */
6683 enum { need_word
, need_dword
, need_qword
} need
;
6685 if (flag_code
== CODE_32BIT
)
6686 need
= i
.prefix
[ADDR_PREFIX
] ? need_word
: need_dword
;
6687 else if (i
.prefix
[ADDR_PREFIX
])
6690 need
= flag_code
== CODE_64BIT
? need_qword
: need_word
;
6692 for (op
= 0; op
< i
.operands
; op
++)
6694 if (i
.types
[op
].bitfield
.class != Reg
)
6700 if (i
.op
[op
].regs
->reg_type
.bitfield
.word
)
6704 if (i
.op
[op
].regs
->reg_type
.bitfield
.dword
)
6708 if (i
.op
[op
].regs
->reg_type
.bitfield
.qword
)
6713 as_bad (_("invalid register operand size for `%s'"),
6724 check_byte_reg (void)
6728 for (op
= i
.operands
; --op
>= 0;)
6730 /* Skip non-register operands. */
6731 if (i
.types
[op
].bitfield
.class != Reg
)
6734 /* If this is an eight bit register, it's OK. If it's the 16 or
6735 32 bit version of an eight bit register, we will just use the
6736 low portion, and that's OK too. */
6737 if (i
.types
[op
].bitfield
.byte
)
6740 /* I/O port address operands are OK too. */
6741 if (i
.tm
.operand_types
[op
].bitfield
.instance
== RegD
6742 && i
.tm
.operand_types
[op
].bitfield
.word
)
6745 /* crc32 only wants its source operand checked here. */
6746 if (i
.tm
.base_opcode
== 0xf20f38f0 && op
)
6749 /* Any other register is bad. */
6750 if (i
.types
[op
].bitfield
.class == Reg
6751 || i
.types
[op
].bitfield
.class == RegMMX
6752 || i
.types
[op
].bitfield
.class == RegSIMD
6753 || i
.types
[op
].bitfield
.class == SReg
6754 || i
.types
[op
].bitfield
.class == RegCR
6755 || i
.types
[op
].bitfield
.class == RegDR
6756 || i
.types
[op
].bitfield
.class == RegTR
)
6758 as_bad (_("`%s%s' not allowed with `%s%c'"),
6760 i
.op
[op
].regs
->reg_name
,
6770 check_long_reg (void)
6774 for (op
= i
.operands
; --op
>= 0;)
6775 /* Skip non-register operands. */
6776 if (i
.types
[op
].bitfield
.class != Reg
)
6778 /* Reject eight bit registers, except where the template requires
6779 them. (eg. movzb) */
6780 else if (i
.types
[op
].bitfield
.byte
6781 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
6782 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
6783 && (i
.tm
.operand_types
[op
].bitfield
.word
6784 || i
.tm
.operand_types
[op
].bitfield
.dword
))
6786 as_bad (_("`%s%s' not allowed with `%s%c'"),
6788 i
.op
[op
].regs
->reg_name
,
6793 /* Error if the e prefix on a general reg is missing. */
6794 else if (i
.types
[op
].bitfield
.word
6795 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
6796 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
6797 && i
.tm
.operand_types
[op
].bitfield
.dword
)
6799 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6800 register_prefix
, i
.op
[op
].regs
->reg_name
,
6804 /* Warn if the r prefix on a general reg is present. */
6805 else if (i
.types
[op
].bitfield
.qword
6806 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
6807 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
6808 && i
.tm
.operand_types
[op
].bitfield
.dword
)
6811 && i
.tm
.opcode_modifier
.toqword
6812 && i
.types
[0].bitfield
.class != RegSIMD
)
6814 /* Convert to QWORD. We want REX byte. */
6815 i
.suffix
= QWORD_MNEM_SUFFIX
;
6819 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6820 register_prefix
, i
.op
[op
].regs
->reg_name
,
6829 check_qword_reg (void)
6833 for (op
= i
.operands
; --op
>= 0; )
6834 /* Skip non-register operands. */
6835 if (i
.types
[op
].bitfield
.class != Reg
)
6837 /* Reject eight bit registers, except where the template requires
6838 them. (eg. movzb) */
6839 else if (i
.types
[op
].bitfield
.byte
6840 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
6841 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
6842 && (i
.tm
.operand_types
[op
].bitfield
.word
6843 || i
.tm
.operand_types
[op
].bitfield
.dword
))
6845 as_bad (_("`%s%s' not allowed with `%s%c'"),
6847 i
.op
[op
].regs
->reg_name
,
6852 /* Warn if the r prefix on a general reg is missing. */
6853 else if ((i
.types
[op
].bitfield
.word
6854 || i
.types
[op
].bitfield
.dword
)
6855 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
6856 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
6857 && i
.tm
.operand_types
[op
].bitfield
.qword
)
6859 /* Prohibit these changes in the 64bit mode, since the
6860 lowering is more complicated. */
6862 && i
.tm
.opcode_modifier
.todword
6863 && i
.types
[0].bitfield
.class != RegSIMD
)
6865 /* Convert to DWORD. We don't want REX byte. */
6866 i
.suffix
= LONG_MNEM_SUFFIX
;
6870 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6871 register_prefix
, i
.op
[op
].regs
->reg_name
,
6880 check_word_reg (void)
6883 for (op
= i
.operands
; --op
>= 0;)
6884 /* Skip non-register operands. */
6885 if (i
.types
[op
].bitfield
.class != Reg
)
6887 /* Reject eight bit registers, except where the template requires
6888 them. (eg. movzb) */
6889 else if (i
.types
[op
].bitfield
.byte
6890 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
6891 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
6892 && (i
.tm
.operand_types
[op
].bitfield
.word
6893 || i
.tm
.operand_types
[op
].bitfield
.dword
))
6895 as_bad (_("`%s%s' not allowed with `%s%c'"),
6897 i
.op
[op
].regs
->reg_name
,
6902 /* Error if the e or r prefix on a general reg is present. */
6903 else if ((i
.types
[op
].bitfield
.dword
6904 || i
.types
[op
].bitfield
.qword
)
6905 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
6906 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
6907 && i
.tm
.operand_types
[op
].bitfield
.word
)
6909 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6910 register_prefix
, i
.op
[op
].regs
->reg_name
,
6918 update_imm (unsigned int j
)
6920 i386_operand_type overlap
= i
.types
[j
];
6921 if ((overlap
.bitfield
.imm8
6922 || overlap
.bitfield
.imm8s
6923 || overlap
.bitfield
.imm16
6924 || overlap
.bitfield
.imm32
6925 || overlap
.bitfield
.imm32s
6926 || overlap
.bitfield
.imm64
)
6927 && !operand_type_equal (&overlap
, &imm8
)
6928 && !operand_type_equal (&overlap
, &imm8s
)
6929 && !operand_type_equal (&overlap
, &imm16
)
6930 && !operand_type_equal (&overlap
, &imm32
)
6931 && !operand_type_equal (&overlap
, &imm32s
)
6932 && !operand_type_equal (&overlap
, &imm64
))
6936 i386_operand_type temp
;
6938 operand_type_set (&temp
, 0);
6939 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
6941 temp
.bitfield
.imm8
= overlap
.bitfield
.imm8
;
6942 temp
.bitfield
.imm8s
= overlap
.bitfield
.imm8s
;
6944 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
6945 temp
.bitfield
.imm16
= overlap
.bitfield
.imm16
;
6946 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
6948 temp
.bitfield
.imm64
= overlap
.bitfield
.imm64
;
6949 temp
.bitfield
.imm32s
= overlap
.bitfield
.imm32s
;
6952 temp
.bitfield
.imm32
= overlap
.bitfield
.imm32
;
6955 else if (operand_type_equal (&overlap
, &imm16_32_32s
)
6956 || operand_type_equal (&overlap
, &imm16_32
)
6957 || operand_type_equal (&overlap
, &imm16_32s
))
6959 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
6964 if (!operand_type_equal (&overlap
, &imm8
)
6965 && !operand_type_equal (&overlap
, &imm8s
)
6966 && !operand_type_equal (&overlap
, &imm16
)
6967 && !operand_type_equal (&overlap
, &imm32
)
6968 && !operand_type_equal (&overlap
, &imm32s
)
6969 && !operand_type_equal (&overlap
, &imm64
))
6971 as_bad (_("no instruction mnemonic suffix given; "
6972 "can't determine immediate size"));
6976 i
.types
[j
] = overlap
;
6986 /* Update the first 2 immediate operands. */
6987 n
= i
.operands
> 2 ? 2 : i
.operands
;
6990 for (j
= 0; j
< n
; j
++)
6991 if (update_imm (j
) == 0)
6994 /* The 3rd operand can't be immediate operand. */
6995 gas_assert (operand_type_check (i
.types
[2], imm
) == 0);
7002 process_operands (void)
7004 /* Default segment register this instruction will use for memory
7005 accesses. 0 means unknown. This is only for optimizing out
7006 unnecessary segment overrides. */
7007 const seg_entry
*default_seg
= 0;
7009 if (i
.tm
.opcode_modifier
.sse2avx
&& i
.tm
.opcode_modifier
.vexvvvv
)
7011 unsigned int dupl
= i
.operands
;
7012 unsigned int dest
= dupl
- 1;
7015 /* The destination must be an xmm register. */
7016 gas_assert (i
.reg_operands
7017 && MAX_OPERANDS
> dupl
7018 && operand_type_equal (&i
.types
[dest
], ®xmm
));
7020 if (i
.tm
.operand_types
[0].bitfield
.instance
== Accum
7021 && i
.tm
.operand_types
[0].bitfield
.xmmword
)
7023 if (i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
)
7025 /* Keep xmm0 for instructions with VEX prefix and 3
7027 i
.tm
.operand_types
[0].bitfield
.instance
= InstanceNone
;
7028 i
.tm
.operand_types
[0].bitfield
.class = RegSIMD
;
7033 /* We remove the first xmm0 and keep the number of
7034 operands unchanged, which in fact duplicates the
7036 for (j
= 1; j
< i
.operands
; j
++)
7038 i
.op
[j
- 1] = i
.op
[j
];
7039 i
.types
[j
- 1] = i
.types
[j
];
7040 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
7041 i
.flags
[j
- 1] = i
.flags
[j
];
7045 else if (i
.tm
.opcode_modifier
.implicit1stxmm0
)
7047 gas_assert ((MAX_OPERANDS
- 1) > dupl
7048 && (i
.tm
.opcode_modifier
.vexsources
7051 /* Add the implicit xmm0 for instructions with VEX prefix
7053 for (j
= i
.operands
; j
> 0; j
--)
7055 i
.op
[j
] = i
.op
[j
- 1];
7056 i
.types
[j
] = i
.types
[j
- 1];
7057 i
.tm
.operand_types
[j
] = i
.tm
.operand_types
[j
- 1];
7058 i
.flags
[j
] = i
.flags
[j
- 1];
7061 = (const reg_entry
*) hash_find (reg_hash
, "xmm0");
7062 i
.types
[0] = regxmm
;
7063 i
.tm
.operand_types
[0] = regxmm
;
7066 i
.reg_operands
+= 2;
7071 i
.op
[dupl
] = i
.op
[dest
];
7072 i
.types
[dupl
] = i
.types
[dest
];
7073 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
7074 i
.flags
[dupl
] = i
.flags
[dest
];
7083 i
.op
[dupl
] = i
.op
[dest
];
7084 i
.types
[dupl
] = i
.types
[dest
];
7085 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
7086 i
.flags
[dupl
] = i
.flags
[dest
];
7089 if (i
.tm
.opcode_modifier
.immext
)
7092 else if (i
.tm
.operand_types
[0].bitfield
.instance
== Accum
7093 && i
.tm
.operand_types
[0].bitfield
.xmmword
)
7097 for (j
= 1; j
< i
.operands
; j
++)
7099 i
.op
[j
- 1] = i
.op
[j
];
7100 i
.types
[j
- 1] = i
.types
[j
];
7102 /* We need to adjust fields in i.tm since they are used by
7103 build_modrm_byte. */
7104 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
7106 i
.flags
[j
- 1] = i
.flags
[j
];
7113 else if (i
.tm
.opcode_modifier
.implicitquadgroup
)
7115 unsigned int regnum
, first_reg_in_group
, last_reg_in_group
;
7117 /* The second operand must be {x,y,z}mmN, where N is a multiple of 4. */
7118 gas_assert (i
.operands
>= 2 && i
.types
[1].bitfield
.class == RegSIMD
);
7119 regnum
= register_number (i
.op
[1].regs
);
7120 first_reg_in_group
= regnum
& ~3;
7121 last_reg_in_group
= first_reg_in_group
+ 3;
7122 if (regnum
!= first_reg_in_group
)
7123 as_warn (_("source register `%s%s' implicitly denotes"
7124 " `%s%.3s%u' to `%s%.3s%u' source group in `%s'"),
7125 register_prefix
, i
.op
[1].regs
->reg_name
,
7126 register_prefix
, i
.op
[1].regs
->reg_name
, first_reg_in_group
,
7127 register_prefix
, i
.op
[1].regs
->reg_name
, last_reg_in_group
,
7130 else if (i
.tm
.opcode_modifier
.regkludge
)
7132 /* The imul $imm, %reg instruction is converted into
7133 imul $imm, %reg, %reg, and the clr %reg instruction
7134 is converted into xor %reg, %reg. */
7136 unsigned int first_reg_op
;
7138 if (operand_type_check (i
.types
[0], reg
))
7142 /* Pretend we saw the extra register operand. */
7143 gas_assert (i
.reg_operands
== 1
7144 && i
.op
[first_reg_op
+ 1].regs
== 0);
7145 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
7146 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
7151 if (i
.tm
.opcode_modifier
.modrm
)
7153 /* The opcode is completed (modulo i.tm.extension_opcode which
7154 must be put into the modrm byte). Now, we make the modrm and
7155 index base bytes based on all the info we've collected. */
7157 default_seg
= build_modrm_byte ();
7159 else if (i
.types
[0].bitfield
.class == SReg
)
7161 if (flag_code
!= CODE_64BIT
7162 ? i
.tm
.base_opcode
== POP_SEG_SHORT
7163 && i
.op
[0].regs
->reg_num
== 1
7164 : (i
.tm
.base_opcode
| 1) == POP_SEG386_SHORT
7165 && i
.op
[0].regs
->reg_num
< 4)
7167 as_bad (_("you can't `%s %s%s'"),
7168 i
.tm
.name
, register_prefix
, i
.op
[0].regs
->reg_name
);
7171 if ( i
.op
[0].regs
->reg_num
> 3 && i
.tm
.opcode_length
== 1 )
7173 i
.tm
.base_opcode
^= POP_SEG_SHORT
^ POP_SEG386_SHORT
;
7174 i
.tm
.opcode_length
= 2;
7176 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
7178 else if ((i
.tm
.base_opcode
& ~0x3) == MOV_AX_DISP32
)
7182 else if (i
.tm
.opcode_modifier
.isstring
)
7184 /* For the string instructions that allow a segment override
7185 on one of their operands, the default segment is ds. */
7188 else if (i
.short_form
)
7190 /* The register or float register operand is in operand
7192 unsigned int op
= i
.tm
.operand_types
[0].bitfield
.class != Reg
;
7194 /* Register goes in low 3 bits of opcode. */
7195 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
7196 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
7198 if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
7200 /* Warn about some common errors, but press on regardless.
7201 The first case can be generated by gcc (<= 2.8.1). */
7202 if (i
.operands
== 2)
7204 /* Reversed arguments on faddp, fsubp, etc. */
7205 as_warn (_("translating to `%s %s%s,%s%s'"), i
.tm
.name
,
7206 register_prefix
, i
.op
[!intel_syntax
].regs
->reg_name
,
7207 register_prefix
, i
.op
[intel_syntax
].regs
->reg_name
);
7211 /* Extraneous `l' suffix on fp insn. */
7212 as_warn (_("translating to `%s %s%s'"), i
.tm
.name
,
7213 register_prefix
, i
.op
[0].regs
->reg_name
);
7218 if ((i
.seg
[0] || i
.prefix
[SEG_PREFIX
])
7219 && i
.tm
.base_opcode
== 0x8d /* lea */
7220 && !is_any_vex_encoding(&i
.tm
))
7222 if (!quiet_warnings
)
7223 as_warn (_("segment override on `%s' is ineffectual"), i
.tm
.name
);
7227 i
.prefix
[SEG_PREFIX
] = 0;
7231 /* If a segment was explicitly specified, and the specified segment
7232 is neither the default nor the one already recorded from a prefix,
7233 use an opcode prefix to select it. If we never figured out what
7234 the default segment is, then default_seg will be zero at this
7235 point, and the specified segment prefix will always be used. */
7237 && i
.seg
[0] != default_seg
7238 && i
.seg
[0]->seg_prefix
!= i
.prefix
[SEG_PREFIX
])
7240 if (!add_prefix (i
.seg
[0]->seg_prefix
))
7246 static const seg_entry
*
7247 build_modrm_byte (void)
7249 const seg_entry
*default_seg
= 0;
7250 unsigned int source
, dest
;
7253 vex_3_sources
= i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
;
7256 unsigned int nds
, reg_slot
;
7259 dest
= i
.operands
- 1;
7262 /* There are 2 kinds of instructions:
7263 1. 5 operands: 4 register operands or 3 register operands
7264 plus 1 memory operand plus one Imm4 operand, VexXDS, and
7265 VexW0 or VexW1. The destination must be either XMM, YMM or
7267 2. 4 operands: 4 register operands or 3 register operands
7268 plus 1 memory operand, with VexXDS. */
7269 gas_assert ((i
.reg_operands
== 4
7270 || (i
.reg_operands
== 3 && i
.mem_operands
== 1))
7271 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
7272 && i
.tm
.opcode_modifier
.vexw
7273 && i
.tm
.operand_types
[dest
].bitfield
.class == RegSIMD
);
7275 /* If VexW1 is set, the first non-immediate operand is the source and
7276 the second non-immediate one is encoded in the immediate operand. */
7277 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
7279 source
= i
.imm_operands
;
7280 reg_slot
= i
.imm_operands
+ 1;
7284 source
= i
.imm_operands
+ 1;
7285 reg_slot
= i
.imm_operands
;
7288 if (i
.imm_operands
== 0)
7290 /* When there is no immediate operand, generate an 8bit
7291 immediate operand to encode the first operand. */
7292 exp
= &im_expressions
[i
.imm_operands
++];
7293 i
.op
[i
.operands
].imms
= exp
;
7294 i
.types
[i
.operands
] = imm8
;
7297 gas_assert (i
.tm
.operand_types
[reg_slot
].bitfield
.class == RegSIMD
);
7298 exp
->X_op
= O_constant
;
7299 exp
->X_add_number
= register_number (i
.op
[reg_slot
].regs
) << 4;
7300 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
7304 gas_assert (i
.imm_operands
== 1);
7305 gas_assert (fits_in_imm4 (i
.op
[0].imms
->X_add_number
));
7306 gas_assert (!i
.tm
.opcode_modifier
.immext
);
7308 /* Turn on Imm8 again so that output_imm will generate it. */
7309 i
.types
[0].bitfield
.imm8
= 1;
7311 gas_assert (i
.tm
.operand_types
[reg_slot
].bitfield
.class == RegSIMD
);
7312 i
.op
[0].imms
->X_add_number
7313 |= register_number (i
.op
[reg_slot
].regs
) << 4;
7314 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
7317 gas_assert (i
.tm
.operand_types
[nds
].bitfield
.class == RegSIMD
);
7318 i
.vex
.register_specifier
= i
.op
[nds
].regs
;
7323 /* i.reg_operands MUST be the number of real register operands;
7324 implicit registers do not count. If there are 3 register
7325 operands, it must be a instruction with VexNDS. For a
7326 instruction with VexNDD, the destination register is encoded
7327 in VEX prefix. If there are 4 register operands, it must be
7328 a instruction with VEX prefix and 3 sources. */
7329 if (i
.mem_operands
== 0
7330 && ((i
.reg_operands
== 2
7331 && i
.tm
.opcode_modifier
.vexvvvv
<= VEXXDS
)
7332 || (i
.reg_operands
== 3
7333 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
7334 || (i
.reg_operands
== 4 && vex_3_sources
)))
7342 /* When there are 3 operands, one of them may be immediate,
7343 which may be the first or the last operand. Otherwise,
7344 the first operand must be shift count register (cl) or it
7345 is an instruction with VexNDS. */
7346 gas_assert (i
.imm_operands
== 1
7347 || (i
.imm_operands
== 0
7348 && (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
7349 || (i
.types
[0].bitfield
.instance
== RegC
7350 && i
.types
[0].bitfield
.byte
))));
7351 if (operand_type_check (i
.types
[0], imm
)
7352 || (i
.types
[0].bitfield
.instance
== RegC
7353 && i
.types
[0].bitfield
.byte
))
7359 /* When there are 4 operands, the first two must be 8bit
7360 immediate operands. The source operand will be the 3rd
7363 For instructions with VexNDS, if the first operand
7364 an imm8, the source operand is the 2nd one. If the last
7365 operand is imm8, the source operand is the first one. */
7366 gas_assert ((i
.imm_operands
== 2
7367 && i
.types
[0].bitfield
.imm8
7368 && i
.types
[1].bitfield
.imm8
)
7369 || (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
7370 && i
.imm_operands
== 1
7371 && (i
.types
[0].bitfield
.imm8
7372 || i
.types
[i
.operands
- 1].bitfield
.imm8
7374 if (i
.imm_operands
== 2)
7378 if (i
.types
[0].bitfield
.imm8
)
7385 if (is_evex_encoding (&i
.tm
))
7387 /* For EVEX instructions, when there are 5 operands, the
7388 first one must be immediate operand. If the second one
7389 is immediate operand, the source operand is the 3th
7390 one. If the last one is immediate operand, the source
7391 operand is the 2nd one. */
7392 gas_assert (i
.imm_operands
== 2
7393 && i
.tm
.opcode_modifier
.sae
7394 && operand_type_check (i
.types
[0], imm
));
7395 if (operand_type_check (i
.types
[1], imm
))
7397 else if (operand_type_check (i
.types
[4], imm
))
7411 /* RC/SAE operand could be between DEST and SRC. That happens
7412 when one operand is GPR and the other one is XMM/YMM/ZMM
7414 if (i
.rounding
&& i
.rounding
->operand
== (int) dest
)
7417 if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
7419 /* For instructions with VexNDS, the register-only source
7420 operand must be a 32/64bit integer, XMM, YMM, ZMM, or mask
7421 register. It is encoded in VEX prefix. */
7423 i386_operand_type op
;
7426 /* Check register-only source operand when two source
7427 operands are swapped. */
7428 if (!i
.tm
.operand_types
[source
].bitfield
.baseindex
7429 && i
.tm
.operand_types
[dest
].bitfield
.baseindex
)
7437 op
= i
.tm
.operand_types
[vvvv
];
7438 if ((dest
+ 1) >= i
.operands
7439 || ((op
.bitfield
.class != Reg
7440 || (!op
.bitfield
.dword
&& !op
.bitfield
.qword
))
7441 && op
.bitfield
.class != RegSIMD
7442 && !operand_type_equal (&op
, ®mask
)))
7444 i
.vex
.register_specifier
= i
.op
[vvvv
].regs
;
7450 /* One of the register operands will be encoded in the i.rm.reg
7451 field, the other in the combined i.rm.mode and i.rm.regmem
7452 fields. If no form of this instruction supports a memory
7453 destination operand, then we assume the source operand may
7454 sometimes be a memory operand and so we need to store the
7455 destination in the i.rm.reg field. */
7456 if (!i
.tm
.opcode_modifier
.regmem
7457 && operand_type_check (i
.tm
.operand_types
[dest
], anymem
) == 0)
7459 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
7460 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
7461 if (i
.op
[dest
].regs
->reg_type
.bitfield
.class == RegMMX
7462 || i
.op
[source
].regs
->reg_type
.bitfield
.class == RegMMX
)
7463 i
.has_regmmx
= TRUE
;
7464 else if (i
.op
[dest
].regs
->reg_type
.bitfield
.class == RegSIMD
7465 || i
.op
[source
].regs
->reg_type
.bitfield
.class == RegSIMD
)
7467 if (i
.types
[dest
].bitfield
.zmmword
7468 || i
.types
[source
].bitfield
.zmmword
)
7469 i
.has_regzmm
= TRUE
;
7470 else if (i
.types
[dest
].bitfield
.ymmword
7471 || i
.types
[source
].bitfield
.ymmword
)
7472 i
.has_regymm
= TRUE
;
7474 i
.has_regxmm
= TRUE
;
7476 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
7478 if ((i
.op
[dest
].regs
->reg_flags
& RegVRex
) != 0)
7480 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
7482 if ((i
.op
[source
].regs
->reg_flags
& RegVRex
) != 0)
7487 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
7488 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
7489 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
7491 if ((i
.op
[dest
].regs
->reg_flags
& RegVRex
) != 0)
7493 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
7495 if ((i
.op
[source
].regs
->reg_flags
& RegVRex
) != 0)
7498 if (flag_code
!= CODE_64BIT
&& (i
.rex
& REX_R
))
7500 if (i
.types
[!i
.tm
.opcode_modifier
.regmem
].bitfield
.class != RegCR
)
7503 add_prefix (LOCK_PREFIX_OPCODE
);
7507 { /* If it's not 2 reg operands... */
7512 unsigned int fake_zero_displacement
= 0;
7515 for (op
= 0; op
< i
.operands
; op
++)
7516 if (i
.flags
[op
] & Operand_Mem
)
7518 gas_assert (op
< i
.operands
);
7520 if (i
.tm
.opcode_modifier
.vecsib
)
7522 if (i
.index_reg
->reg_num
== RegIZ
)
7525 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
7528 i
.sib
.base
= NO_BASE_REGISTER
;
7529 i
.sib
.scale
= i
.log2_scale_factor
;
7530 i
.types
[op
].bitfield
.disp8
= 0;
7531 i
.types
[op
].bitfield
.disp16
= 0;
7532 i
.types
[op
].bitfield
.disp64
= 0;
7533 if (flag_code
!= CODE_64BIT
|| i
.prefix
[ADDR_PREFIX
])
7535 /* Must be 32 bit */
7536 i
.types
[op
].bitfield
.disp32
= 1;
7537 i
.types
[op
].bitfield
.disp32s
= 0;
7541 i
.types
[op
].bitfield
.disp32
= 0;
7542 i
.types
[op
].bitfield
.disp32s
= 1;
7545 i
.sib
.index
= i
.index_reg
->reg_num
;
7546 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
7548 if ((i
.index_reg
->reg_flags
& RegVRex
) != 0)
7554 if (i
.base_reg
== 0)
7557 if (!i
.disp_operands
)
7558 fake_zero_displacement
= 1;
7559 if (i
.index_reg
== 0)
7561 i386_operand_type newdisp
;
7563 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
7564 /* Operand is just <disp> */
7565 if (flag_code
== CODE_64BIT
)
7567 /* 64bit mode overwrites the 32bit absolute
7568 addressing by RIP relative addressing and
7569 absolute addressing is encoded by one of the
7570 redundant SIB forms. */
7571 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
7572 i
.sib
.base
= NO_BASE_REGISTER
;
7573 i
.sib
.index
= NO_INDEX_REGISTER
;
7574 newdisp
= (!i
.prefix
[ADDR_PREFIX
] ? disp32s
: disp32
);
7576 else if ((flag_code
== CODE_16BIT
)
7577 ^ (i
.prefix
[ADDR_PREFIX
] != 0))
7579 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
7584 i
.rm
.regmem
= NO_BASE_REGISTER
;
7587 i
.types
[op
] = operand_type_and_not (i
.types
[op
], anydisp
);
7588 i
.types
[op
] = operand_type_or (i
.types
[op
], newdisp
);
7590 else if (!i
.tm
.opcode_modifier
.vecsib
)
7592 /* !i.base_reg && i.index_reg */
7593 if (i
.index_reg
->reg_num
== RegIZ
)
7594 i
.sib
.index
= NO_INDEX_REGISTER
;
7596 i
.sib
.index
= i
.index_reg
->reg_num
;
7597 i
.sib
.base
= NO_BASE_REGISTER
;
7598 i
.sib
.scale
= i
.log2_scale_factor
;
7599 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
7600 i
.types
[op
].bitfield
.disp8
= 0;
7601 i
.types
[op
].bitfield
.disp16
= 0;
7602 i
.types
[op
].bitfield
.disp64
= 0;
7603 if (flag_code
!= CODE_64BIT
|| i
.prefix
[ADDR_PREFIX
])
7605 /* Must be 32 bit */
7606 i
.types
[op
].bitfield
.disp32
= 1;
7607 i
.types
[op
].bitfield
.disp32s
= 0;
7611 i
.types
[op
].bitfield
.disp32
= 0;
7612 i
.types
[op
].bitfield
.disp32s
= 1;
7614 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
7618 /* RIP addressing for 64bit mode. */
7619 else if (i
.base_reg
->reg_num
== RegIP
)
7621 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
7622 i
.rm
.regmem
= NO_BASE_REGISTER
;
7623 i
.types
[op
].bitfield
.disp8
= 0;
7624 i
.types
[op
].bitfield
.disp16
= 0;
7625 i
.types
[op
].bitfield
.disp32
= 0;
7626 i
.types
[op
].bitfield
.disp32s
= 1;
7627 i
.types
[op
].bitfield
.disp64
= 0;
7628 i
.flags
[op
] |= Operand_PCrel
;
7629 if (! i
.disp_operands
)
7630 fake_zero_displacement
= 1;
7632 else if (i
.base_reg
->reg_type
.bitfield
.word
)
7634 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
7635 switch (i
.base_reg
->reg_num
)
7638 if (i
.index_reg
== 0)
7640 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
7641 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
7645 if (i
.index_reg
== 0)
7648 if (operand_type_check (i
.types
[op
], disp
) == 0)
7650 /* fake (%bp) into 0(%bp) */
7651 i
.types
[op
].bitfield
.disp8
= 1;
7652 fake_zero_displacement
= 1;
7655 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
7656 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
7658 default: /* (%si) -> 4 or (%di) -> 5 */
7659 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
7661 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
7663 else /* i.base_reg and 32/64 bit mode */
7665 if (flag_code
== CODE_64BIT
7666 && operand_type_check (i
.types
[op
], disp
))
7668 i
.types
[op
].bitfield
.disp16
= 0;
7669 i
.types
[op
].bitfield
.disp64
= 0;
7670 if (i
.prefix
[ADDR_PREFIX
] == 0)
7672 i
.types
[op
].bitfield
.disp32
= 0;
7673 i
.types
[op
].bitfield
.disp32s
= 1;
7677 i
.types
[op
].bitfield
.disp32
= 1;
7678 i
.types
[op
].bitfield
.disp32s
= 0;
7682 if (!i
.tm
.opcode_modifier
.vecsib
)
7683 i
.rm
.regmem
= i
.base_reg
->reg_num
;
7684 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
7686 i
.sib
.base
= i
.base_reg
->reg_num
;
7687 /* x86-64 ignores REX prefix bit here to avoid decoder
7689 if (!(i
.base_reg
->reg_flags
& RegRex
)
7690 && (i
.base_reg
->reg_num
== EBP_REG_NUM
7691 || i
.base_reg
->reg_num
== ESP_REG_NUM
))
7693 if (i
.base_reg
->reg_num
== 5 && i
.disp_operands
== 0)
7695 fake_zero_displacement
= 1;
7696 i
.types
[op
].bitfield
.disp8
= 1;
7698 i
.sib
.scale
= i
.log2_scale_factor
;
7699 if (i
.index_reg
== 0)
7701 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
7702 /* <disp>(%esp) becomes two byte modrm with no index
7703 register. We've already stored the code for esp
7704 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
7705 Any base register besides %esp will not use the
7706 extra modrm byte. */
7707 i
.sib
.index
= NO_INDEX_REGISTER
;
7709 else if (!i
.tm
.opcode_modifier
.vecsib
)
7711 if (i
.index_reg
->reg_num
== RegIZ
)
7712 i
.sib
.index
= NO_INDEX_REGISTER
;
7714 i
.sib
.index
= i
.index_reg
->reg_num
;
7715 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
7716 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
7721 && (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
7722 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
))
7726 if (!fake_zero_displacement
7730 fake_zero_displacement
= 1;
7731 if (i
.disp_encoding
== disp_encoding_8bit
)
7732 i
.types
[op
].bitfield
.disp8
= 1;
7734 i
.types
[op
].bitfield
.disp32
= 1;
7736 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
7740 if (fake_zero_displacement
)
7742 /* Fakes a zero displacement assuming that i.types[op]
7743 holds the correct displacement size. */
7746 gas_assert (i
.op
[op
].disps
== 0);
7747 exp
= &disp_expressions
[i
.disp_operands
++];
7748 i
.op
[op
].disps
= exp
;
7749 exp
->X_op
= O_constant
;
7750 exp
->X_add_number
= 0;
7751 exp
->X_add_symbol
= (symbolS
*) 0;
7752 exp
->X_op_symbol
= (symbolS
*) 0;
7760 if (i
.tm
.opcode_modifier
.vexsources
== XOP2SOURCES
)
7762 if (operand_type_check (i
.types
[0], imm
))
7763 i
.vex
.register_specifier
= NULL
;
7766 /* VEX.vvvv encodes one of the sources when the first
7767 operand is not an immediate. */
7768 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
7769 i
.vex
.register_specifier
= i
.op
[0].regs
;
7771 i
.vex
.register_specifier
= i
.op
[1].regs
;
7774 /* Destination is a XMM register encoded in the ModRM.reg
7776 i
.rm
.reg
= i
.op
[2].regs
->reg_num
;
7777 if ((i
.op
[2].regs
->reg_flags
& RegRex
) != 0)
7780 /* ModRM.rm and VEX.B encodes the other source. */
7781 if (!i
.mem_operands
)
7785 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
7786 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
7788 i
.rm
.regmem
= i
.op
[0].regs
->reg_num
;
7790 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
7794 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXLWP
)
7796 i
.vex
.register_specifier
= i
.op
[2].regs
;
7797 if (!i
.mem_operands
)
7800 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
7801 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
7805 /* Fill in i.rm.reg or i.rm.regmem field with register operand
7806 (if any) based on i.tm.extension_opcode. Again, we must be
7807 careful to make sure that segment/control/debug/test/MMX
7808 registers are coded into the i.rm.reg field. */
7809 else if (i
.reg_operands
)
7812 unsigned int vex_reg
= ~0;
7814 for (op
= 0; op
< i
.operands
; op
++)
7816 if (i
.types
[op
].bitfield
.class == Reg
7817 || i
.types
[op
].bitfield
.class == RegBND
7818 || i
.types
[op
].bitfield
.class == RegMask
7819 || i
.types
[op
].bitfield
.class == SReg
7820 || i
.types
[op
].bitfield
.class == RegCR
7821 || i
.types
[op
].bitfield
.class == RegDR
7822 || i
.types
[op
].bitfield
.class == RegTR
)
7824 if (i
.types
[op
].bitfield
.class == RegSIMD
)
7826 if (i
.types
[op
].bitfield
.zmmword
)
7827 i
.has_regzmm
= TRUE
;
7828 else if (i
.types
[op
].bitfield
.ymmword
)
7829 i
.has_regymm
= TRUE
;
7831 i
.has_regxmm
= TRUE
;
7834 if (i
.types
[op
].bitfield
.class == RegMMX
)
7836 i
.has_regmmx
= TRUE
;
7843 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
7845 /* For instructions with VexNDS, the register-only
7846 source operand is encoded in VEX prefix. */
7847 gas_assert (mem
!= (unsigned int) ~0);
7852 gas_assert (op
< i
.operands
);
7856 /* Check register-only source operand when two source
7857 operands are swapped. */
7858 if (!i
.tm
.operand_types
[op
].bitfield
.baseindex
7859 && i
.tm
.operand_types
[op
+ 1].bitfield
.baseindex
)
7863 gas_assert (mem
== (vex_reg
+ 1)
7864 && op
< i
.operands
);
7869 gas_assert (vex_reg
< i
.operands
);
7873 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXNDD
)
7875 /* For instructions with VexNDD, the register destination
7876 is encoded in VEX prefix. */
7877 if (i
.mem_operands
== 0)
7879 /* There is no memory operand. */
7880 gas_assert ((op
+ 2) == i
.operands
);
7885 /* There are only 2 non-immediate operands. */
7886 gas_assert (op
< i
.imm_operands
+ 2
7887 && i
.operands
== i
.imm_operands
+ 2);
7888 vex_reg
= i
.imm_operands
+ 1;
7892 gas_assert (op
< i
.operands
);
7894 if (vex_reg
!= (unsigned int) ~0)
7896 i386_operand_type
*type
= &i
.tm
.operand_types
[vex_reg
];
7898 if ((type
->bitfield
.class != Reg
7899 || (!type
->bitfield
.dword
&& !type
->bitfield
.qword
))
7900 && type
->bitfield
.class != RegSIMD
7901 && !operand_type_equal (type
, ®mask
))
7904 i
.vex
.register_specifier
= i
.op
[vex_reg
].regs
;
7907 /* Don't set OP operand twice. */
7910 /* If there is an extension opcode to put here, the
7911 register number must be put into the regmem field. */
7912 if (i
.tm
.extension_opcode
!= None
)
7914 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
7915 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
7917 if ((i
.op
[op
].regs
->reg_flags
& RegVRex
) != 0)
7922 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
7923 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
7925 if ((i
.op
[op
].regs
->reg_flags
& RegVRex
) != 0)
7930 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
7931 must set it to 3 to indicate this is a register operand
7932 in the regmem field. */
7933 if (!i
.mem_operands
)
7937 /* Fill in i.rm.reg field with extension opcode (if any). */
7938 if (i
.tm
.extension_opcode
!= None
)
7939 i
.rm
.reg
= i
.tm
.extension_opcode
;
7945 flip_code16 (unsigned int code16
)
7947 gas_assert (i
.tm
.operands
== 1);
7949 return !(i
.prefix
[REX_PREFIX
] & REX_W
)
7950 && (code16
? i
.tm
.operand_types
[0].bitfield
.disp32
7951 || i
.tm
.operand_types
[0].bitfield
.disp32s
7952 : i
.tm
.operand_types
[0].bitfield
.disp16
)
7957 output_branch (void)
7963 relax_substateT subtype
;
7967 code16
= flag_code
== CODE_16BIT
? CODE16
: 0;
7968 size
= i
.disp_encoding
== disp_encoding_32bit
? BIG
: SMALL
;
7971 if (i
.prefix
[DATA_PREFIX
] != 0)
7975 code16
^= flip_code16(code16
);
7977 /* Pentium4 branch hints. */
7978 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
7979 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
7984 if (i
.prefix
[REX_PREFIX
] != 0)
7990 /* BND prefixed jump. */
7991 if (i
.prefix
[BND_PREFIX
] != 0)
7997 if (i
.prefixes
!= 0)
7998 as_warn (_("skipping prefixes on `%s'"), i
.tm
.name
);
8000 /* It's always a symbol; End frag & setup for relax.
8001 Make sure there is enough room in this frag for the largest
8002 instruction we may generate in md_convert_frag. This is 2
8003 bytes for the opcode and room for the prefix and largest
8005 frag_grow (prefix
+ 2 + 4);
8006 /* Prefix and 1 opcode byte go in fr_fix. */
8007 p
= frag_more (prefix
+ 1);
8008 if (i
.prefix
[DATA_PREFIX
] != 0)
8009 *p
++ = DATA_PREFIX_OPCODE
;
8010 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
8011 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
8012 *p
++ = i
.prefix
[SEG_PREFIX
];
8013 if (i
.prefix
[BND_PREFIX
] != 0)
8014 *p
++ = BND_PREFIX_OPCODE
;
8015 if (i
.prefix
[REX_PREFIX
] != 0)
8016 *p
++ = i
.prefix
[REX_PREFIX
];
8017 *p
= i
.tm
.base_opcode
;
8019 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
8020 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, size
);
8021 else if (cpu_arch_flags
.bitfield
.cpui386
)
8022 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, size
);
8024 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, size
);
8027 sym
= i
.op
[0].disps
->X_add_symbol
;
8028 off
= i
.op
[0].disps
->X_add_number
;
8030 if (i
.op
[0].disps
->X_op
!= O_constant
8031 && i
.op
[0].disps
->X_op
!= O_symbol
)
8033 /* Handle complex expressions. */
8034 sym
= make_expr_symbol (i
.op
[0].disps
);
8038 /* 1 possible extra opcode + 4 byte displacement go in var part.
8039 Pass reloc in fr_var. */
8040 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
8043 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8044 /* Return TRUE iff PLT32 relocation should be used for branching to
8048 need_plt32_p (symbolS
*s
)
8050 /* PLT32 relocation is ELF only. */
8055 /* Don't emit PLT32 relocation on Solaris: neither native linker nor
8056 krtld support it. */
8060 /* Since there is no need to prepare for PLT branch on x86-64, we
8061 can generate R_X86_64_PLT32, instead of R_X86_64_PC32, which can
8062 be used as a marker for 32-bit PC-relative branches. */
8066 /* Weak or undefined symbol need PLT32 relocation. */
8067 if (S_IS_WEAK (s
) || !S_IS_DEFINED (s
))
8070 /* Non-global symbol doesn't need PLT32 relocation. */
8071 if (! S_IS_EXTERNAL (s
))
8074 /* Other global symbols need PLT32 relocation. NB: Symbol with
8075 non-default visibilities are treated as normal global symbol
8076 so that PLT32 relocation can be used as a marker for 32-bit
8077 PC-relative branches. It is useful for linker relaxation. */
8088 bfd_reloc_code_real_type jump_reloc
= i
.reloc
[0];
8090 if (i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
)
8092 /* This is a loop or jecxz type instruction. */
8094 if (i
.prefix
[ADDR_PREFIX
] != 0)
8096 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
8099 /* Pentium4 branch hints. */
8100 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
8101 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
8103 FRAG_APPEND_1_CHAR (i
.prefix
[SEG_PREFIX
]);
8112 if (flag_code
== CODE_16BIT
)
8115 if (i
.prefix
[DATA_PREFIX
] != 0)
8117 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
8119 code16
^= flip_code16(code16
);
8127 /* BND prefixed jump. */
8128 if (i
.prefix
[BND_PREFIX
] != 0)
8130 FRAG_APPEND_1_CHAR (i
.prefix
[BND_PREFIX
]);
8134 if (i
.prefix
[REX_PREFIX
] != 0)
8136 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
8140 if (i
.prefixes
!= 0)
8141 as_warn (_("skipping prefixes on `%s'"), i
.tm
.name
);
8143 p
= frag_more (i
.tm
.opcode_length
+ size
);
8144 switch (i
.tm
.opcode_length
)
8147 *p
++ = i
.tm
.base_opcode
>> 8;
8150 *p
++ = i
.tm
.base_opcode
;
8156 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8158 && jump_reloc
== NO_RELOC
8159 && need_plt32_p (i
.op
[0].disps
->X_add_symbol
))
8160 jump_reloc
= BFD_RELOC_X86_64_PLT32
;
8163 jump_reloc
= reloc (size
, 1, 1, jump_reloc
);
8165 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
8166 i
.op
[0].disps
, 1, jump_reloc
);
8168 /* All jumps handled here are signed, but don't use a signed limit
8169 check for 32 and 16 bit jumps as we want to allow wrap around at
8170 4G and 64k respectively. */
8172 fixP
->fx_signed
= 1;
8176 output_interseg_jump (void)
8184 if (flag_code
== CODE_16BIT
)
8188 if (i
.prefix
[DATA_PREFIX
] != 0)
8195 gas_assert (!i
.prefix
[REX_PREFIX
]);
8201 if (i
.prefixes
!= 0)
8202 as_warn (_("skipping prefixes on `%s'"), i
.tm
.name
);
8204 /* 1 opcode; 2 segment; offset */
8205 p
= frag_more (prefix
+ 1 + 2 + size
);
8207 if (i
.prefix
[DATA_PREFIX
] != 0)
8208 *p
++ = DATA_PREFIX_OPCODE
;
8210 if (i
.prefix
[REX_PREFIX
] != 0)
8211 *p
++ = i
.prefix
[REX_PREFIX
];
8213 *p
++ = i
.tm
.base_opcode
;
8214 if (i
.op
[1].imms
->X_op
== O_constant
)
8216 offsetT n
= i
.op
[1].imms
->X_add_number
;
8219 && !fits_in_unsigned_word (n
)
8220 && !fits_in_signed_word (n
))
8222 as_bad (_("16-bit jump out of range"));
8225 md_number_to_chars (p
, n
, size
);
8228 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
8229 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
8230 if (i
.op
[0].imms
->X_op
!= O_constant
)
8231 as_bad (_("can't handle non absolute segment in `%s'"),
8233 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
8236 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8241 asection
*seg
= now_seg
;
8242 subsegT subseg
= now_subseg
;
8244 unsigned int alignment
, align_size_1
;
8245 unsigned int isa_1_descsz
, feature_2_descsz
, descsz
;
8246 unsigned int isa_1_descsz_raw
, feature_2_descsz_raw
;
8247 unsigned int padding
;
8249 if (!IS_ELF
|| !x86_used_note
)
8252 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_X86
;
8254 /* The .note.gnu.property section layout:
8256 Field Length Contents
8259 n_descsz 4 The note descriptor size
8260 n_type 4 NT_GNU_PROPERTY_TYPE_0
8262 n_desc n_descsz The program property array
8266 /* Create the .note.gnu.property section. */
8267 sec
= subseg_new (NOTE_GNU_PROPERTY_SECTION_NAME
, 0);
8268 bfd_set_section_flags (sec
,
8275 if (get_elf_backend_data (stdoutput
)->s
->elfclass
== ELFCLASS64
)
8286 bfd_set_section_alignment (sec
, alignment
);
8287 elf_section_type (sec
) = SHT_NOTE
;
8289 /* GNU_PROPERTY_X86_ISA_1_USED: 4-byte type + 4-byte data size
8291 isa_1_descsz_raw
= 4 + 4 + 4;
8292 /* Align GNU_PROPERTY_X86_ISA_1_USED. */
8293 isa_1_descsz
= (isa_1_descsz_raw
+ align_size_1
) & ~align_size_1
;
8295 feature_2_descsz_raw
= isa_1_descsz
;
8296 /* GNU_PROPERTY_X86_FEATURE_2_USED: 4-byte type + 4-byte data size
8298 feature_2_descsz_raw
+= 4 + 4 + 4;
8299 /* Align GNU_PROPERTY_X86_FEATURE_2_USED. */
8300 feature_2_descsz
= ((feature_2_descsz_raw
+ align_size_1
)
8303 descsz
= feature_2_descsz
;
8304 /* Section size: n_namsz + n_descsz + n_type + n_name + n_descsz. */
8305 p
= frag_more (4 + 4 + 4 + 4 + descsz
);
8307 /* Write n_namsz. */
8308 md_number_to_chars (p
, (valueT
) 4, 4);
8310 /* Write n_descsz. */
8311 md_number_to_chars (p
+ 4, (valueT
) descsz
, 4);
8314 md_number_to_chars (p
+ 4 * 2, (valueT
) NT_GNU_PROPERTY_TYPE_0
, 4);
8317 memcpy (p
+ 4 * 3, "GNU", 4);
8319 /* Write 4-byte type. */
8320 md_number_to_chars (p
+ 4 * 4,
8321 (valueT
) GNU_PROPERTY_X86_ISA_1_USED
, 4);
8323 /* Write 4-byte data size. */
8324 md_number_to_chars (p
+ 4 * 5, (valueT
) 4, 4);
8326 /* Write 4-byte data. */
8327 md_number_to_chars (p
+ 4 * 6, (valueT
) x86_isa_1_used
, 4);
8329 /* Zero out paddings. */
8330 padding
= isa_1_descsz
- isa_1_descsz_raw
;
8332 memset (p
+ 4 * 7, 0, padding
);
8334 /* Write 4-byte type. */
8335 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 4,
8336 (valueT
) GNU_PROPERTY_X86_FEATURE_2_USED
, 4);
8338 /* Write 4-byte data size. */
8339 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 5, (valueT
) 4, 4);
8341 /* Write 4-byte data. */
8342 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 6,
8343 (valueT
) x86_feature_2_used
, 4);
8345 /* Zero out paddings. */
8346 padding
= feature_2_descsz
- feature_2_descsz_raw
;
8348 memset (p
+ isa_1_descsz
+ 4 * 7, 0, padding
);
8350 /* We probably can't restore the current segment, for there likely
8353 subseg_set (seg
, subseg
);
8358 encoding_length (const fragS
*start_frag
, offsetT start_off
,
8359 const char *frag_now_ptr
)
8361 unsigned int len
= 0;
8363 if (start_frag
!= frag_now
)
8365 const fragS
*fr
= start_frag
;
8370 } while (fr
&& fr
!= frag_now
);
8373 return len
- start_off
+ (frag_now_ptr
- frag_now
->fr_literal
);
8376 /* Return 1 for test, and, cmp, add, sub, inc and dec which may
8377 be macro-fused with conditional jumps. */
8380 maybe_fused_with_jcc_p (void)
8382 /* No RIP address. */
8383 if (i
.base_reg
&& i
.base_reg
->reg_num
== RegIP
)
8386 /* No VEX/EVEX encoding. */
8387 if (is_any_vex_encoding (&i
.tm
))
8390 /* and, add, sub with destination register. */
8391 if ((i
.tm
.base_opcode
>= 0x20 && i
.tm
.base_opcode
<= 0x25)
8392 || i
.tm
.base_opcode
<= 5
8393 || (i
.tm
.base_opcode
>= 0x28 && i
.tm
.base_opcode
<= 0x2d)
8394 || ((i
.tm
.base_opcode
| 3) == 0x83
8395 && ((i
.tm
.extension_opcode
| 1) == 0x5
8396 || i
.tm
.extension_opcode
== 0x0)))
8397 return (i
.types
[1].bitfield
.class == Reg
8398 || i
.types
[1].bitfield
.instance
== Accum
);
8400 /* test, cmp with any register. */
8401 if ((i
.tm
.base_opcode
| 1) == 0x85
8402 || (i
.tm
.base_opcode
| 1) == 0xa9
8403 || ((i
.tm
.base_opcode
| 1) == 0xf7
8404 && i
.tm
.extension_opcode
== 0)
8405 || (i
.tm
.base_opcode
>= 0x38 && i
.tm
.base_opcode
<= 0x3d)
8406 || ((i
.tm
.base_opcode
| 3) == 0x83
8407 && (i
.tm
.extension_opcode
== 0x7)))
8408 return (i
.types
[0].bitfield
.class == Reg
8409 || i
.types
[0].bitfield
.instance
== Accum
8410 || i
.types
[1].bitfield
.class == Reg
8411 || i
.types
[1].bitfield
.instance
== Accum
);
8413 /* inc, dec with any register. */
8414 if ((i
.tm
.cpu_flags
.bitfield
.cpuno64
8415 && (i
.tm
.base_opcode
| 0xf) == 0x4f)
8416 || ((i
.tm
.base_opcode
| 1) == 0xff
8417 && i
.tm
.extension_opcode
<= 0x1))
8418 return (i
.types
[0].bitfield
.class == Reg
8419 || i
.types
[0].bitfield
.instance
== Accum
);
8424 /* Return 1 if a FUSED_JCC_PADDING frag should be generated. */
8427 add_fused_jcc_padding_frag_p (void)
8429 /* NB: Don't work with COND_JUMP86 without i386. */
8430 if (!align_branch_power
8431 || now_seg
== absolute_section
8432 || !cpu_arch_flags
.bitfield
.cpui386
8433 || !(align_branch
& align_branch_fused_bit
))
8436 if (maybe_fused_with_jcc_p ())
8438 if (last_insn
.kind
== last_insn_other
8439 || last_insn
.seg
!= now_seg
)
8442 as_warn_where (last_insn
.file
, last_insn
.line
,
8443 _("`%s` skips -malign-branch-boundary on `%s`"),
8444 last_insn
.name
, i
.tm
.name
);
8450 /* Return 1 if a BRANCH_PREFIX frag should be generated. */
8453 add_branch_prefix_frag_p (void)
8455 /* NB: Don't work with COND_JUMP86 without i386. Don't add prefix
8456 to PadLock instructions since they include prefixes in opcode. */
8457 if (!align_branch_power
8458 || !align_branch_prefix_size
8459 || now_seg
== absolute_section
8460 || i
.tm
.cpu_flags
.bitfield
.cpupadlock
8461 || !cpu_arch_flags
.bitfield
.cpui386
)
8464 /* Don't add prefix if it is a prefix or there is no operand in case
8465 that segment prefix is special. */
8466 if (!i
.operands
|| i
.tm
.opcode_modifier
.isprefix
)
8469 if (last_insn
.kind
== last_insn_other
8470 || last_insn
.seg
!= now_seg
)
8474 as_warn_where (last_insn
.file
, last_insn
.line
,
8475 _("`%s` skips -malign-branch-boundary on `%s`"),
8476 last_insn
.name
, i
.tm
.name
);
8481 /* Return 1 if a BRANCH_PADDING frag should be generated. */
8484 add_branch_padding_frag_p (enum align_branch_kind
*branch_p
)
8488 /* NB: Don't work with COND_JUMP86 without i386. */
8489 if (!align_branch_power
8490 || now_seg
== absolute_section
8491 || !cpu_arch_flags
.bitfield
.cpui386
)
8496 /* Check for jcc and direct jmp. */
8497 if (i
.tm
.opcode_modifier
.jump
== JUMP
)
8499 if (i
.tm
.base_opcode
== JUMP_PC_RELATIVE
)
8501 *branch_p
= align_branch_jmp
;
8502 add_padding
= align_branch
& align_branch_jmp_bit
;
8506 *branch_p
= align_branch_jcc
;
8507 if ((align_branch
& align_branch_jcc_bit
))
8511 else if (is_any_vex_encoding (&i
.tm
))
8513 else if ((i
.tm
.base_opcode
| 1) == 0xc3)
8516 *branch_p
= align_branch_ret
;
8517 if ((align_branch
& align_branch_ret_bit
))
8522 /* Check for indirect jmp, direct and indirect calls. */
8523 if (i
.tm
.base_opcode
== 0xe8)
8526 *branch_p
= align_branch_call
;
8527 if ((align_branch
& align_branch_call_bit
))
8530 else if (i
.tm
.base_opcode
== 0xff
8531 && (i
.tm
.extension_opcode
== 2
8532 || i
.tm
.extension_opcode
== 4))
8534 /* Indirect call and jmp. */
8535 *branch_p
= align_branch_indirect
;
8536 if ((align_branch
& align_branch_indirect_bit
))
8543 && (i
.op
[0].disps
->X_op
== O_symbol
8544 || (i
.op
[0].disps
->X_op
== O_subtract
8545 && i
.op
[0].disps
->X_op_symbol
== GOT_symbol
)))
8547 symbolS
*s
= i
.op
[0].disps
->X_add_symbol
;
8548 /* No padding to call to global or undefined tls_get_addr. */
8549 if ((S_IS_EXTERNAL (s
) || !S_IS_DEFINED (s
))
8550 && strcmp (S_GET_NAME (s
), tls_get_addr
) == 0)
8556 && last_insn
.kind
!= last_insn_other
8557 && last_insn
.seg
== now_seg
)
8560 as_warn_where (last_insn
.file
, last_insn
.line
,
8561 _("`%s` skips -malign-branch-boundary on `%s`"),
8562 last_insn
.name
, i
.tm
.name
);
8572 fragS
*insn_start_frag
;
8573 offsetT insn_start_off
;
8574 fragS
*fragP
= NULL
;
8575 enum align_branch_kind branch
= align_branch_none
;
8577 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8578 if (IS_ELF
&& x86_used_note
)
8580 if (i
.tm
.cpu_flags
.bitfield
.cpucmov
)
8581 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_CMOV
;
8582 if (i
.tm
.cpu_flags
.bitfield
.cpusse
)
8583 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE
;
8584 if (i
.tm
.cpu_flags
.bitfield
.cpusse2
)
8585 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE2
;
8586 if (i
.tm
.cpu_flags
.bitfield
.cpusse3
)
8587 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE3
;
8588 if (i
.tm
.cpu_flags
.bitfield
.cpussse3
)
8589 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSSE3
;
8590 if (i
.tm
.cpu_flags
.bitfield
.cpusse4_1
)
8591 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE4_1
;
8592 if (i
.tm
.cpu_flags
.bitfield
.cpusse4_2
)
8593 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE4_2
;
8594 if (i
.tm
.cpu_flags
.bitfield
.cpuavx
)
8595 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX
;
8596 if (i
.tm
.cpu_flags
.bitfield
.cpuavx2
)
8597 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX2
;
8598 if (i
.tm
.cpu_flags
.bitfield
.cpufma
)
8599 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_FMA
;
8600 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512f
)
8601 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512F
;
8602 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512cd
)
8603 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512CD
;
8604 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512er
)
8605 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512ER
;
8606 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512pf
)
8607 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512PF
;
8608 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512vl
)
8609 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512VL
;
8610 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512dq
)
8611 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512DQ
;
8612 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512bw
)
8613 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512BW
;
8614 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_4fmaps
)
8615 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_4FMAPS
;
8616 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_4vnniw
)
8617 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_4VNNIW
;
8618 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_bitalg
)
8619 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_BITALG
;
8620 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512ifma
)
8621 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_IFMA
;
8622 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512vbmi
)
8623 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_VBMI
;
8624 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_vbmi2
)
8625 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_VBMI2
;
8626 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_vnni
)
8627 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_VNNI
;
8628 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_bf16
)
8629 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_BF16
;
8631 if (i
.tm
.cpu_flags
.bitfield
.cpu8087
8632 || i
.tm
.cpu_flags
.bitfield
.cpu287
8633 || i
.tm
.cpu_flags
.bitfield
.cpu387
8634 || i
.tm
.cpu_flags
.bitfield
.cpu687
8635 || i
.tm
.cpu_flags
.bitfield
.cpufisttp
)
8636 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_X87
;
8638 || i
.tm
.base_opcode
== 0xf77 /* emms */
8639 || i
.tm
.base_opcode
== 0xf0e /* femms */)
8640 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_MMX
;
8642 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XMM
;
8644 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_YMM
;
8646 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_ZMM
;
8647 if (i
.tm
.cpu_flags
.bitfield
.cpufxsr
)
8648 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_FXSR
;
8649 if (i
.tm
.cpu_flags
.bitfield
.cpuxsave
)
8650 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVE
;
8651 if (i
.tm
.cpu_flags
.bitfield
.cpuxsaveopt
)
8652 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVEOPT
;
8653 if (i
.tm
.cpu_flags
.bitfield
.cpuxsavec
)
8654 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVEC
;
8658 /* Tie dwarf2 debug info to the address at the start of the insn.
8659 We can't do this after the insn has been output as the current
8660 frag may have been closed off. eg. by frag_var. */
8661 dwarf2_emit_insn (0);
8663 insn_start_frag
= frag_now
;
8664 insn_start_off
= frag_now_fix ();
8666 if (add_branch_padding_frag_p (&branch
))
8669 /* Branch can be 8 bytes. Leave some room for prefixes. */
8670 unsigned int max_branch_padding_size
= 14;
8672 /* Align section to boundary. */
8673 record_alignment (now_seg
, align_branch_power
);
8675 /* Make room for padding. */
8676 frag_grow (max_branch_padding_size
);
8678 /* Start of the padding. */
8683 frag_var (rs_machine_dependent
, max_branch_padding_size
, 0,
8684 ENCODE_RELAX_STATE (BRANCH_PADDING
, 0),
8687 fragP
->tc_frag_data
.branch_type
= branch
;
8688 fragP
->tc_frag_data
.max_bytes
= max_branch_padding_size
;
8692 if (i
.tm
.opcode_modifier
.jump
== JUMP
)
8694 else if (i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
8695 || i
.tm
.opcode_modifier
.jump
== JUMP_DWORD
)
8697 else if (i
.tm
.opcode_modifier
.jump
== JUMP_INTERSEGMENT
)
8698 output_interseg_jump ();
8701 /* Output normal instructions here. */
8705 unsigned int prefix
;
8708 && (i
.tm
.base_opcode
== 0xfaee8
8709 || i
.tm
.base_opcode
== 0xfaef0
8710 || i
.tm
.base_opcode
== 0xfaef8))
8712 /* Encode lfence, mfence, and sfence as
8713 f0 83 04 24 00 lock addl $0x0, (%{re}sp). */
8714 offsetT val
= 0x240483f0ULL
;
8716 md_number_to_chars (p
, val
, 5);
8720 /* Some processors fail on LOCK prefix. This options makes
8721 assembler ignore LOCK prefix and serves as a workaround. */
8722 if (omit_lock_prefix
)
8724 if (i
.tm
.base_opcode
== LOCK_PREFIX_OPCODE
)
8726 i
.prefix
[LOCK_PREFIX
] = 0;
8730 /* Skip if this is a branch. */
8732 else if (add_fused_jcc_padding_frag_p ())
8734 /* Make room for padding. */
8735 frag_grow (MAX_FUSED_JCC_PADDING_SIZE
);
8740 frag_var (rs_machine_dependent
, MAX_FUSED_JCC_PADDING_SIZE
, 0,
8741 ENCODE_RELAX_STATE (FUSED_JCC_PADDING
, 0),
8744 fragP
->tc_frag_data
.branch_type
= align_branch_fused
;
8745 fragP
->tc_frag_data
.max_bytes
= MAX_FUSED_JCC_PADDING_SIZE
;
8747 else if (add_branch_prefix_frag_p ())
8749 unsigned int max_prefix_size
= align_branch_prefix_size
;
8751 /* Make room for padding. */
8752 frag_grow (max_prefix_size
);
8757 frag_var (rs_machine_dependent
, max_prefix_size
, 0,
8758 ENCODE_RELAX_STATE (BRANCH_PREFIX
, 0),
8761 fragP
->tc_frag_data
.max_bytes
= max_prefix_size
;
8764 /* Since the VEX/EVEX prefix contains the implicit prefix, we
8765 don't need the explicit prefix. */
8766 if (!i
.tm
.opcode_modifier
.vex
&& !i
.tm
.opcode_modifier
.evex
)
8768 switch (i
.tm
.opcode_length
)
8771 if (i
.tm
.base_opcode
& 0xff000000)
8773 prefix
= (i
.tm
.base_opcode
>> 24) & 0xff;
8774 if (!i
.tm
.cpu_flags
.bitfield
.cpupadlock
8775 || prefix
!= REPE_PREFIX_OPCODE
8776 || (i
.prefix
[REP_PREFIX
] != REPE_PREFIX_OPCODE
))
8777 add_prefix (prefix
);
8781 if ((i
.tm
.base_opcode
& 0xff0000) != 0)
8783 prefix
= (i
.tm
.base_opcode
>> 16) & 0xff;
8784 add_prefix (prefix
);
8790 /* Check for pseudo prefixes. */
8791 as_bad_where (insn_start_frag
->fr_file
,
8792 insn_start_frag
->fr_line
,
8793 _("pseudo prefix without instruction"));
8799 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
8800 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
8801 R_X86_64_GOTTPOFF relocation so that linker can safely
8802 perform IE->LE optimization. A dummy REX_OPCODE prefix
8803 is also needed for lea with R_X86_64_GOTPC32_TLSDESC
8804 relocation for GDesc -> IE/LE optimization. */
8805 if (x86_elf_abi
== X86_64_X32_ABI
8807 && (i
.reloc
[0] == BFD_RELOC_X86_64_GOTTPOFF
8808 || i
.reloc
[0] == BFD_RELOC_X86_64_GOTPC32_TLSDESC
)
8809 && i
.prefix
[REX_PREFIX
] == 0)
8810 add_prefix (REX_OPCODE
);
8813 /* The prefix bytes. */
8814 for (j
= ARRAY_SIZE (i
.prefix
), q
= i
.prefix
; j
> 0; j
--, q
++)
8816 FRAG_APPEND_1_CHAR (*q
);
8820 for (j
= 0, q
= i
.prefix
; j
< ARRAY_SIZE (i
.prefix
); j
++, q
++)
8825 /* REX byte is encoded in VEX prefix. */
8829 FRAG_APPEND_1_CHAR (*q
);
8832 /* There should be no other prefixes for instructions
8837 /* For EVEX instructions i.vrex should become 0 after
8838 build_evex_prefix. For VEX instructions upper 16 registers
8839 aren't available, so VREX should be 0. */
8842 /* Now the VEX prefix. */
8843 p
= frag_more (i
.vex
.length
);
8844 for (j
= 0; j
< i
.vex
.length
; j
++)
8845 p
[j
] = i
.vex
.bytes
[j
];
8848 /* Now the opcode; be careful about word order here! */
8849 if (i
.tm
.opcode_length
== 1)
8851 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
8855 switch (i
.tm
.opcode_length
)
8859 *p
++ = (i
.tm
.base_opcode
>> 24) & 0xff;
8860 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
8864 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
8874 /* Put out high byte first: can't use md_number_to_chars! */
8875 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
8876 *p
= i
.tm
.base_opcode
& 0xff;
8879 /* Now the modrm byte and sib byte (if present). */
8880 if (i
.tm
.opcode_modifier
.modrm
)
8882 FRAG_APPEND_1_CHAR ((i
.rm
.regmem
<< 0
8885 /* If i.rm.regmem == ESP (4)
8886 && i.rm.mode != (Register mode)
8888 ==> need second modrm byte. */
8889 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
8891 && !(i
.base_reg
&& i
.base_reg
->reg_type
.bitfield
.word
))
8892 FRAG_APPEND_1_CHAR ((i
.sib
.base
<< 0
8894 | i
.sib
.scale
<< 6));
8897 if (i
.disp_operands
)
8898 output_disp (insn_start_frag
, insn_start_off
);
8901 output_imm (insn_start_frag
, insn_start_off
);
8904 * frag_now_fix () returning plain abs_section_offset when we're in the
8905 * absolute section, and abs_section_offset not getting updated as data
8906 * gets added to the frag breaks the logic below.
8908 if (now_seg
!= absolute_section
)
8910 j
= encoding_length (insn_start_frag
, insn_start_off
, frag_more (0));
8912 as_warn (_("instruction length of %u bytes exceeds the limit of 15"),
8916 /* NB: Don't add prefix with GOTPC relocation since
8917 output_disp() above depends on the fixed encoding
8918 length. Can't add prefix with TLS relocation since
8919 it breaks TLS linker optimization. */
8920 unsigned int max
= i
.has_gotpc_tls_reloc
? 0 : 15 - j
;
8921 /* Prefix count on the current instruction. */
8922 unsigned int count
= i
.vex
.length
;
8924 for (k
= 0; k
< ARRAY_SIZE (i
.prefix
); k
++)
8925 /* REX byte is encoded in VEX/EVEX prefix. */
8926 if (i
.prefix
[k
] && (k
!= REX_PREFIX
|| !i
.vex
.length
))
8929 /* Count prefixes for extended opcode maps. */
8931 switch (i
.tm
.opcode_length
)
8934 if (((i
.tm
.base_opcode
>> 16) & 0xff) == 0xf)
8937 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
8949 if (((i
.tm
.base_opcode
>> 8) & 0xff) == 0xf)
8958 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
)
8961 /* Set the maximum prefix size in BRANCH_PREFIX
8963 if (fragP
->tc_frag_data
.max_bytes
> max
)
8964 fragP
->tc_frag_data
.max_bytes
= max
;
8965 if (fragP
->tc_frag_data
.max_bytes
> count
)
8966 fragP
->tc_frag_data
.max_bytes
-= count
;
8968 fragP
->tc_frag_data
.max_bytes
= 0;
8972 /* Remember the maximum prefix size in FUSED_JCC_PADDING
8974 unsigned int max_prefix_size
;
8975 if (align_branch_prefix_size
> max
)
8976 max_prefix_size
= max
;
8978 max_prefix_size
= align_branch_prefix_size
;
8979 if (max_prefix_size
> count
)
8980 fragP
->tc_frag_data
.max_prefix_length
8981 = max_prefix_size
- count
;
8984 /* Use existing segment prefix if possible. Use CS
8985 segment prefix in 64-bit mode. In 32-bit mode, use SS
8986 segment prefix with ESP/EBP base register and use DS
8987 segment prefix without ESP/EBP base register. */
8988 if (i
.prefix
[SEG_PREFIX
])
8989 fragP
->tc_frag_data
.default_prefix
= i
.prefix
[SEG_PREFIX
];
8990 else if (flag_code
== CODE_64BIT
)
8991 fragP
->tc_frag_data
.default_prefix
= CS_PREFIX_OPCODE
;
8993 && (i
.base_reg
->reg_num
== 4
8994 || i
.base_reg
->reg_num
== 5))
8995 fragP
->tc_frag_data
.default_prefix
= SS_PREFIX_OPCODE
;
8997 fragP
->tc_frag_data
.default_prefix
= DS_PREFIX_OPCODE
;
9002 /* NB: Don't work with COND_JUMP86 without i386. */
9003 if (align_branch_power
9004 && now_seg
!= absolute_section
9005 && cpu_arch_flags
.bitfield
.cpui386
)
9007 /* Terminate each frag so that we can add prefix and check for
9009 frag_wane (frag_now
);
9016 pi ("" /*line*/, &i
);
9018 #endif /* DEBUG386 */
9021 /* Return the size of the displacement operand N. */
9024 disp_size (unsigned int n
)
9028 if (i
.types
[n
].bitfield
.disp64
)
9030 else if (i
.types
[n
].bitfield
.disp8
)
9032 else if (i
.types
[n
].bitfield
.disp16
)
9037 /* Return the size of the immediate operand N. */
9040 imm_size (unsigned int n
)
9043 if (i
.types
[n
].bitfield
.imm64
)
9045 else if (i
.types
[n
].bitfield
.imm8
|| i
.types
[n
].bitfield
.imm8s
)
9047 else if (i
.types
[n
].bitfield
.imm16
)
9053 output_disp (fragS
*insn_start_frag
, offsetT insn_start_off
)
9058 for (n
= 0; n
< i
.operands
; n
++)
9060 if (operand_type_check (i
.types
[n
], disp
))
9062 if (i
.op
[n
].disps
->X_op
== O_constant
)
9064 int size
= disp_size (n
);
9065 offsetT val
= i
.op
[n
].disps
->X_add_number
;
9067 val
= offset_in_range (val
>> (size
== 1 ? i
.memshift
: 0),
9069 p
= frag_more (size
);
9070 md_number_to_chars (p
, val
, size
);
9074 enum bfd_reloc_code_real reloc_type
;
9075 int size
= disp_size (n
);
9076 int sign
= i
.types
[n
].bitfield
.disp32s
;
9077 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
9080 /* We can't have 8 bit displacement here. */
9081 gas_assert (!i
.types
[n
].bitfield
.disp8
);
9083 /* The PC relative address is computed relative
9084 to the instruction boundary, so in case immediate
9085 fields follows, we need to adjust the value. */
9086 if (pcrel
&& i
.imm_operands
)
9091 for (n1
= 0; n1
< i
.operands
; n1
++)
9092 if (operand_type_check (i
.types
[n1
], imm
))
9094 /* Only one immediate is allowed for PC
9095 relative address. */
9096 gas_assert (sz
== 0);
9098 i
.op
[n
].disps
->X_add_number
-= sz
;
9100 /* We should find the immediate. */
9101 gas_assert (sz
!= 0);
9104 p
= frag_more (size
);
9105 reloc_type
= reloc (size
, pcrel
, sign
, i
.reloc
[n
]);
9107 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
9108 && (((reloc_type
== BFD_RELOC_32
9109 || reloc_type
== BFD_RELOC_X86_64_32S
9110 || (reloc_type
== BFD_RELOC_64
9112 && (i
.op
[n
].disps
->X_op
== O_symbol
9113 || (i
.op
[n
].disps
->X_op
== O_add
9114 && ((symbol_get_value_expression
9115 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
9117 || reloc_type
== BFD_RELOC_32_PCREL
))
9121 reloc_type
= BFD_RELOC_386_GOTPC
;
9122 i
.has_gotpc_tls_reloc
= TRUE
;
9123 i
.op
[n
].imms
->X_add_number
+=
9124 encoding_length (insn_start_frag
, insn_start_off
, p
);
9126 else if (reloc_type
== BFD_RELOC_64
)
9127 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
9129 /* Don't do the adjustment for x86-64, as there
9130 the pcrel addressing is relative to the _next_
9131 insn, and that is taken care of in other code. */
9132 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
9134 else if (align_branch_power
)
9138 case BFD_RELOC_386_TLS_GD
:
9139 case BFD_RELOC_386_TLS_LDM
:
9140 case BFD_RELOC_386_TLS_IE
:
9141 case BFD_RELOC_386_TLS_IE_32
:
9142 case BFD_RELOC_386_TLS_GOTIE
:
9143 case BFD_RELOC_386_TLS_GOTDESC
:
9144 case BFD_RELOC_386_TLS_DESC_CALL
:
9145 case BFD_RELOC_X86_64_TLSGD
:
9146 case BFD_RELOC_X86_64_TLSLD
:
9147 case BFD_RELOC_X86_64_GOTTPOFF
:
9148 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
9149 case BFD_RELOC_X86_64_TLSDESC_CALL
:
9150 i
.has_gotpc_tls_reloc
= TRUE
;
9155 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
9156 size
, i
.op
[n
].disps
, pcrel
,
9158 /* Check for "call/jmp *mem", "mov mem, %reg",
9159 "test %reg, mem" and "binop mem, %reg" where binop
9160 is one of adc, add, and, cmp, or, sbb, sub, xor
9161 instructions without data prefix. Always generate
9162 R_386_GOT32X for "sym*GOT" operand in 32-bit mode. */
9163 if (i
.prefix
[DATA_PREFIX
] == 0
9164 && (generate_relax_relocations
9167 && i
.rm
.regmem
== 5))
9169 || (i
.rm
.mode
== 0 && i
.rm
.regmem
== 5))
9170 && !is_any_vex_encoding(&i
.tm
)
9171 && ((i
.operands
== 1
9172 && i
.tm
.base_opcode
== 0xff
9173 && (i
.rm
.reg
== 2 || i
.rm
.reg
== 4))
9175 && (i
.tm
.base_opcode
== 0x8b
9176 || i
.tm
.base_opcode
== 0x85
9177 || (i
.tm
.base_opcode
& ~0x38) == 0x03))))
9181 fixP
->fx_tcbit
= i
.rex
!= 0;
9183 && (i
.base_reg
->reg_num
== RegIP
))
9184 fixP
->fx_tcbit2
= 1;
9187 fixP
->fx_tcbit2
= 1;
9195 output_imm (fragS
*insn_start_frag
, offsetT insn_start_off
)
9200 for (n
= 0; n
< i
.operands
; n
++)
9202 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
9203 if (i
.rounding
&& (int) n
== i
.rounding
->operand
)
9206 if (operand_type_check (i
.types
[n
], imm
))
9208 if (i
.op
[n
].imms
->X_op
== O_constant
)
9210 int size
= imm_size (n
);
9213 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
9215 p
= frag_more (size
);
9216 md_number_to_chars (p
, val
, size
);
9220 /* Not absolute_section.
9221 Need a 32-bit fixup (don't support 8bit
9222 non-absolute imms). Try to support other
9224 enum bfd_reloc_code_real reloc_type
;
9225 int size
= imm_size (n
);
9228 if (i
.types
[n
].bitfield
.imm32s
9229 && (i
.suffix
== QWORD_MNEM_SUFFIX
9230 || (!i
.suffix
&& i
.tm
.opcode_modifier
.no_lsuf
)))
9235 p
= frag_more (size
);
9236 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
9238 /* This is tough to explain. We end up with this one if we
9239 * have operands that look like
9240 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
9241 * obtain the absolute address of the GOT, and it is strongly
9242 * preferable from a performance point of view to avoid using
9243 * a runtime relocation for this. The actual sequence of
9244 * instructions often look something like:
9249 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
9251 * The call and pop essentially return the absolute address
9252 * of the label .L66 and store it in %ebx. The linker itself
9253 * will ultimately change the first operand of the addl so
9254 * that %ebx points to the GOT, but to keep things simple, the
9255 * .o file must have this operand set so that it generates not
9256 * the absolute address of .L66, but the absolute address of
9257 * itself. This allows the linker itself simply treat a GOTPC
9258 * relocation as asking for a pcrel offset to the GOT to be
9259 * added in, and the addend of the relocation is stored in the
9260 * operand field for the instruction itself.
9262 * Our job here is to fix the operand so that it would add
9263 * the correct offset so that %ebx would point to itself. The
9264 * thing that is tricky is that .-.L66 will point to the
9265 * beginning of the instruction, so we need to further modify
9266 * the operand so that it will point to itself. There are
9267 * other cases where you have something like:
9269 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
9271 * and here no correction would be required. Internally in
9272 * the assembler we treat operands of this form as not being
9273 * pcrel since the '.' is explicitly mentioned, and I wonder
9274 * whether it would simplify matters to do it this way. Who
9275 * knows. In earlier versions of the PIC patches, the
9276 * pcrel_adjust field was used to store the correction, but
9277 * since the expression is not pcrel, I felt it would be
9278 * confusing to do it this way. */
9280 if ((reloc_type
== BFD_RELOC_32
9281 || reloc_type
== BFD_RELOC_X86_64_32S
9282 || reloc_type
== BFD_RELOC_64
)
9284 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
9285 && (i
.op
[n
].imms
->X_op
== O_symbol
9286 || (i
.op
[n
].imms
->X_op
== O_add
9287 && ((symbol_get_value_expression
9288 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
9292 reloc_type
= BFD_RELOC_386_GOTPC
;
9294 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
9296 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
9297 i
.has_gotpc_tls_reloc
= TRUE
;
9298 i
.op
[n
].imms
->X_add_number
+=
9299 encoding_length (insn_start_frag
, insn_start_off
, p
);
9301 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
9302 i
.op
[n
].imms
, 0, reloc_type
);
9308 /* x86_cons_fix_new is called via the expression parsing code when a
9309 reloc is needed. We use this hook to get the correct .got reloc. */
9310 static int cons_sign
= -1;
9313 x86_cons_fix_new (fragS
*frag
, unsigned int off
, unsigned int len
,
9314 expressionS
*exp
, bfd_reloc_code_real_type r
)
9316 r
= reloc (len
, 0, cons_sign
, r
);
9319 if (exp
->X_op
== O_secrel
)
9321 exp
->X_op
= O_symbol
;
9322 r
= BFD_RELOC_32_SECREL
;
9326 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
9329 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
9330 purpose of the `.dc.a' internal pseudo-op. */
9333 x86_address_bytes (void)
9335 if ((stdoutput
->arch_info
->mach
& bfd_mach_x64_32
))
9337 return stdoutput
->arch_info
->bits_per_address
/ 8;
9340 #if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
9342 # define lex_got(reloc, adjust, types) NULL
9344 /* Parse operands of the form
9345 <symbol>@GOTOFF+<nnn>
9346 and similar .plt or .got references.
9348 If we find one, set up the correct relocation in RELOC and copy the
9349 input string, minus the `@GOTOFF' into a malloc'd buffer for
9350 parsing by the calling routine. Return this buffer, and if ADJUST
9351 is non-null set it to the length of the string we removed from the
9352 input line. Otherwise return NULL. */
9354 lex_got (enum bfd_reloc_code_real
*rel
,
9356 i386_operand_type
*types
)
9358 /* Some of the relocations depend on the size of what field is to
9359 be relocated. But in our callers i386_immediate and i386_displacement
9360 we don't yet know the operand size (this will be set by insn
9361 matching). Hence we record the word32 relocation here,
9362 and adjust the reloc according to the real size in reloc(). */
9363 static const struct {
9366 const enum bfd_reloc_code_real rel
[2];
9367 const i386_operand_type types64
;
9369 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9370 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32
,
9372 OPERAND_TYPE_IMM32_64
},
9374 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real
,
9375 BFD_RELOC_X86_64_PLTOFF64
},
9376 OPERAND_TYPE_IMM64
},
9377 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32
,
9378 BFD_RELOC_X86_64_PLT32
},
9379 OPERAND_TYPE_IMM32_32S_DISP32
},
9380 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real
,
9381 BFD_RELOC_X86_64_GOTPLT64
},
9382 OPERAND_TYPE_IMM64_DISP64
},
9383 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF
,
9384 BFD_RELOC_X86_64_GOTOFF64
},
9385 OPERAND_TYPE_IMM64_DISP64
},
9386 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real
,
9387 BFD_RELOC_X86_64_GOTPCREL
},
9388 OPERAND_TYPE_IMM32_32S_DISP32
},
9389 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD
,
9390 BFD_RELOC_X86_64_TLSGD
},
9391 OPERAND_TYPE_IMM32_32S_DISP32
},
9392 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM
,
9393 _dummy_first_bfd_reloc_code_real
},
9394 OPERAND_TYPE_NONE
},
9395 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real
,
9396 BFD_RELOC_X86_64_TLSLD
},
9397 OPERAND_TYPE_IMM32_32S_DISP32
},
9398 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32
,
9399 BFD_RELOC_X86_64_GOTTPOFF
},
9400 OPERAND_TYPE_IMM32_32S_DISP32
},
9401 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32
,
9402 BFD_RELOC_X86_64_TPOFF32
},
9403 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
9404 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE
,
9405 _dummy_first_bfd_reloc_code_real
},
9406 OPERAND_TYPE_NONE
},
9407 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32
,
9408 BFD_RELOC_X86_64_DTPOFF32
},
9409 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
9410 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE
,
9411 _dummy_first_bfd_reloc_code_real
},
9412 OPERAND_TYPE_NONE
},
9413 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE
,
9414 _dummy_first_bfd_reloc_code_real
},
9415 OPERAND_TYPE_NONE
},
9416 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32
,
9417 BFD_RELOC_X86_64_GOT32
},
9418 OPERAND_TYPE_IMM32_32S_64_DISP32
},
9419 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC
,
9420 BFD_RELOC_X86_64_GOTPC32_TLSDESC
},
9421 OPERAND_TYPE_IMM32_32S_DISP32
},
9422 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL
,
9423 BFD_RELOC_X86_64_TLSDESC_CALL
},
9424 OPERAND_TYPE_IMM32_32S_DISP32
},
9429 #if defined (OBJ_MAYBE_ELF)
9434 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
9435 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
9438 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
9440 int len
= gotrel
[j
].len
;
9441 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
9443 if (gotrel
[j
].rel
[object_64bit
] != 0)
9446 char *tmpbuf
, *past_reloc
;
9448 *rel
= gotrel
[j
].rel
[object_64bit
];
9452 if (flag_code
!= CODE_64BIT
)
9454 types
->bitfield
.imm32
= 1;
9455 types
->bitfield
.disp32
= 1;
9458 *types
= gotrel
[j
].types64
;
9461 if (j
!= 0 && GOT_symbol
== NULL
)
9462 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
9464 /* The length of the first part of our input line. */
9465 first
= cp
- input_line_pointer
;
9467 /* The second part goes from after the reloc token until
9468 (and including) an end_of_line char or comma. */
9469 past_reloc
= cp
+ 1 + len
;
9471 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
9473 second
= cp
+ 1 - past_reloc
;
9475 /* Allocate and copy string. The trailing NUL shouldn't
9476 be necessary, but be safe. */
9477 tmpbuf
= XNEWVEC (char, first
+ second
+ 2);
9478 memcpy (tmpbuf
, input_line_pointer
, first
);
9479 if (second
!= 0 && *past_reloc
!= ' ')
9480 /* Replace the relocation token with ' ', so that
9481 errors like foo@GOTOFF1 will be detected. */
9482 tmpbuf
[first
++] = ' ';
9484 /* Increment length by 1 if the relocation token is
9489 memcpy (tmpbuf
+ first
, past_reloc
, second
);
9490 tmpbuf
[first
+ second
] = '\0';
9494 as_bad (_("@%s reloc is not supported with %d-bit output format"),
9495 gotrel
[j
].str
, 1 << (5 + object_64bit
));
9500 /* Might be a symbol version string. Don't as_bad here. */
9509 /* Parse operands of the form
9510 <symbol>@SECREL32+<nnn>
9512 If we find one, set up the correct relocation in RELOC and copy the
9513 input string, minus the `@SECREL32' into a malloc'd buffer for
9514 parsing by the calling routine. Return this buffer, and if ADJUST
9515 is non-null set it to the length of the string we removed from the
9516 input line. Otherwise return NULL.
9518 This function is copied from the ELF version above adjusted for PE targets. */
9521 lex_got (enum bfd_reloc_code_real
*rel ATTRIBUTE_UNUSED
,
9522 int *adjust ATTRIBUTE_UNUSED
,
9523 i386_operand_type
*types
)
9529 const enum bfd_reloc_code_real rel
[2];
9530 const i386_operand_type types64
;
9534 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL
,
9535 BFD_RELOC_32_SECREL
},
9536 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
9542 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
9543 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
9546 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
9548 int len
= gotrel
[j
].len
;
9550 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
9552 if (gotrel
[j
].rel
[object_64bit
] != 0)
9555 char *tmpbuf
, *past_reloc
;
9557 *rel
= gotrel
[j
].rel
[object_64bit
];
9563 if (flag_code
!= CODE_64BIT
)
9565 types
->bitfield
.imm32
= 1;
9566 types
->bitfield
.disp32
= 1;
9569 *types
= gotrel
[j
].types64
;
9572 /* The length of the first part of our input line. */
9573 first
= cp
- input_line_pointer
;
9575 /* The second part goes from after the reloc token until
9576 (and including) an end_of_line char or comma. */
9577 past_reloc
= cp
+ 1 + len
;
9579 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
9581 second
= cp
+ 1 - past_reloc
;
9583 /* Allocate and copy string. The trailing NUL shouldn't
9584 be necessary, but be safe. */
9585 tmpbuf
= XNEWVEC (char, first
+ second
+ 2);
9586 memcpy (tmpbuf
, input_line_pointer
, first
);
9587 if (second
!= 0 && *past_reloc
!= ' ')
9588 /* Replace the relocation token with ' ', so that
9589 errors like foo@SECLREL321 will be detected. */
9590 tmpbuf
[first
++] = ' ';
9591 memcpy (tmpbuf
+ first
, past_reloc
, second
);
9592 tmpbuf
[first
+ second
] = '\0';
9596 as_bad (_("@%s reloc is not supported with %d-bit output format"),
9597 gotrel
[j
].str
, 1 << (5 + object_64bit
));
9602 /* Might be a symbol version string. Don't as_bad here. */
9608 bfd_reloc_code_real_type
9609 x86_cons (expressionS
*exp
, int size
)
9611 bfd_reloc_code_real_type got_reloc
= NO_RELOC
;
9613 intel_syntax
= -intel_syntax
;
9616 if (size
== 4 || (object_64bit
&& size
== 8))
9618 /* Handle @GOTOFF and the like in an expression. */
9620 char *gotfree_input_line
;
9623 save
= input_line_pointer
;
9624 gotfree_input_line
= lex_got (&got_reloc
, &adjust
, NULL
);
9625 if (gotfree_input_line
)
9626 input_line_pointer
= gotfree_input_line
;
9630 if (gotfree_input_line
)
9632 /* expression () has merrily parsed up to the end of line,
9633 or a comma - in the wrong buffer. Transfer how far
9634 input_line_pointer has moved to the right buffer. */
9635 input_line_pointer
= (save
9636 + (input_line_pointer
- gotfree_input_line
)
9638 free (gotfree_input_line
);
9639 if (exp
->X_op
== O_constant
9640 || exp
->X_op
== O_absent
9641 || exp
->X_op
== O_illegal
9642 || exp
->X_op
== O_register
9643 || exp
->X_op
== O_big
)
9645 char c
= *input_line_pointer
;
9646 *input_line_pointer
= 0;
9647 as_bad (_("missing or invalid expression `%s'"), save
);
9648 *input_line_pointer
= c
;
9650 else if ((got_reloc
== BFD_RELOC_386_PLT32
9651 || got_reloc
== BFD_RELOC_X86_64_PLT32
)
9652 && exp
->X_op
!= O_symbol
)
9654 char c
= *input_line_pointer
;
9655 *input_line_pointer
= 0;
9656 as_bad (_("invalid PLT expression `%s'"), save
);
9657 *input_line_pointer
= c
;
9664 intel_syntax
= -intel_syntax
;
9667 i386_intel_simplify (exp
);
9673 signed_cons (int size
)
9675 if (flag_code
== CODE_64BIT
)
9683 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
9690 if (exp
.X_op
== O_symbol
)
9691 exp
.X_op
= O_secrel
;
9693 emit_expr (&exp
, 4);
9695 while (*input_line_pointer
++ == ',');
9697 input_line_pointer
--;
9698 demand_empty_rest_of_line ();
9702 /* Handle Vector operations. */
9705 check_VecOperations (char *op_string
, char *op_end
)
9707 const reg_entry
*mask
;
9712 && (op_end
== NULL
|| op_string
< op_end
))
9715 if (*op_string
== '{')
9719 /* Check broadcasts. */
9720 if (strncmp (op_string
, "1to", 3) == 0)
9725 goto duplicated_vec_op
;
9728 if (*op_string
== '8')
9730 else if (*op_string
== '4')
9732 else if (*op_string
== '2')
9734 else if (*op_string
== '1'
9735 && *(op_string
+1) == '6')
9742 as_bad (_("Unsupported broadcast: `%s'"), saved
);
9747 broadcast_op
.type
= bcst_type
;
9748 broadcast_op
.operand
= this_operand
;
9749 broadcast_op
.bytes
= 0;
9750 i
.broadcast
= &broadcast_op
;
9752 /* Check masking operation. */
9753 else if ((mask
= parse_register (op_string
, &end_op
)) != NULL
)
9755 /* k0 can't be used for write mask. */
9756 if (mask
->reg_type
.bitfield
.class != RegMask
|| !mask
->reg_num
)
9758 as_bad (_("`%s%s' can't be used for write mask"),
9759 register_prefix
, mask
->reg_name
);
9765 mask_op
.mask
= mask
;
9766 mask_op
.zeroing
= 0;
9767 mask_op
.operand
= this_operand
;
9773 goto duplicated_vec_op
;
9775 i
.mask
->mask
= mask
;
9777 /* Only "{z}" is allowed here. No need to check
9778 zeroing mask explicitly. */
9779 if (i
.mask
->operand
!= this_operand
)
9781 as_bad (_("invalid write mask `%s'"), saved
);
9788 /* Check zeroing-flag for masking operation. */
9789 else if (*op_string
== 'z')
9793 mask_op
.mask
= NULL
;
9794 mask_op
.zeroing
= 1;
9795 mask_op
.operand
= this_operand
;
9800 if (i
.mask
->zeroing
)
9803 as_bad (_("duplicated `%s'"), saved
);
9807 i
.mask
->zeroing
= 1;
9809 /* Only "{%k}" is allowed here. No need to check mask
9810 register explicitly. */
9811 if (i
.mask
->operand
!= this_operand
)
9813 as_bad (_("invalid zeroing-masking `%s'"),
9822 goto unknown_vec_op
;
9824 if (*op_string
!= '}')
9826 as_bad (_("missing `}' in `%s'"), saved
);
9831 /* Strip whitespace since the addition of pseudo prefixes
9832 changed how the scrubber treats '{'. */
9833 if (is_space_char (*op_string
))
9839 /* We don't know this one. */
9840 as_bad (_("unknown vector operation: `%s'"), saved
);
9844 if (i
.mask
&& i
.mask
->zeroing
&& !i
.mask
->mask
)
9846 as_bad (_("zeroing-masking only allowed with write mask"));
9854 i386_immediate (char *imm_start
)
9856 char *save_input_line_pointer
;
9857 char *gotfree_input_line
;
9860 i386_operand_type types
;
9862 operand_type_set (&types
, ~0);
9864 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
9866 as_bad (_("at most %d immediate operands are allowed"),
9867 MAX_IMMEDIATE_OPERANDS
);
9871 exp
= &im_expressions
[i
.imm_operands
++];
9872 i
.op
[this_operand
].imms
= exp
;
9874 if (is_space_char (*imm_start
))
9877 save_input_line_pointer
= input_line_pointer
;
9878 input_line_pointer
= imm_start
;
9880 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
9881 if (gotfree_input_line
)
9882 input_line_pointer
= gotfree_input_line
;
9884 exp_seg
= expression (exp
);
9888 /* Handle vector operations. */
9889 if (*input_line_pointer
== '{')
9891 input_line_pointer
= check_VecOperations (input_line_pointer
,
9893 if (input_line_pointer
== NULL
)
9897 if (*input_line_pointer
)
9898 as_bad (_("junk `%s' after expression"), input_line_pointer
);
9900 input_line_pointer
= save_input_line_pointer
;
9901 if (gotfree_input_line
)
9903 free (gotfree_input_line
);
9905 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
9906 exp
->X_op
= O_illegal
;
9909 return i386_finalize_immediate (exp_seg
, exp
, types
, imm_start
);
9913 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
9914 i386_operand_type types
, const char *imm_start
)
9916 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_illegal
|| exp
->X_op
== O_big
)
9919 as_bad (_("missing or invalid immediate expression `%s'"),
9923 else if (exp
->X_op
== O_constant
)
9925 /* Size it properly later. */
9926 i
.types
[this_operand
].bitfield
.imm64
= 1;
9927 /* If not 64bit, sign extend val. */
9928 if (flag_code
!= CODE_64BIT
9929 && (exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
9931 = (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
9933 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
9934 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
9935 && exp_seg
!= absolute_section
9936 && exp_seg
!= text_section
9937 && exp_seg
!= data_section
9938 && exp_seg
!= bss_section
9939 && exp_seg
!= undefined_section
9940 && !bfd_is_com_section (exp_seg
))
9942 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
9946 else if (!intel_syntax
&& exp_seg
== reg_section
)
9949 as_bad (_("illegal immediate register operand %s"), imm_start
);
9954 /* This is an address. The size of the address will be
9955 determined later, depending on destination register,
9956 suffix, or the default for the section. */
9957 i
.types
[this_operand
].bitfield
.imm8
= 1;
9958 i
.types
[this_operand
].bitfield
.imm16
= 1;
9959 i
.types
[this_operand
].bitfield
.imm32
= 1;
9960 i
.types
[this_operand
].bitfield
.imm32s
= 1;
9961 i
.types
[this_operand
].bitfield
.imm64
= 1;
9962 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
9970 i386_scale (char *scale
)
9973 char *save
= input_line_pointer
;
9975 input_line_pointer
= scale
;
9976 val
= get_absolute_expression ();
9981 i
.log2_scale_factor
= 0;
9984 i
.log2_scale_factor
= 1;
9987 i
.log2_scale_factor
= 2;
9990 i
.log2_scale_factor
= 3;
9994 char sep
= *input_line_pointer
;
9996 *input_line_pointer
= '\0';
9997 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
9999 *input_line_pointer
= sep
;
10000 input_line_pointer
= save
;
10004 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
10006 as_warn (_("scale factor of %d without an index register"),
10007 1 << i
.log2_scale_factor
);
10008 i
.log2_scale_factor
= 0;
10010 scale
= input_line_pointer
;
10011 input_line_pointer
= save
;
10016 i386_displacement (char *disp_start
, char *disp_end
)
10020 char *save_input_line_pointer
;
10021 char *gotfree_input_line
;
10023 i386_operand_type bigdisp
, types
= anydisp
;
10026 if (i
.disp_operands
== MAX_MEMORY_OPERANDS
)
10028 as_bad (_("at most %d displacement operands are allowed"),
10029 MAX_MEMORY_OPERANDS
);
10033 operand_type_set (&bigdisp
, 0);
10035 || i
.types
[this_operand
].bitfield
.baseindex
10036 || (current_templates
->start
->opcode_modifier
.jump
!= JUMP
10037 && current_templates
->start
->opcode_modifier
.jump
!= JUMP_DWORD
))
10039 i386_addressing_mode ();
10040 override
= (i
.prefix
[ADDR_PREFIX
] != 0);
10041 if (flag_code
== CODE_64BIT
)
10045 bigdisp
.bitfield
.disp32s
= 1;
10046 bigdisp
.bitfield
.disp64
= 1;
10049 bigdisp
.bitfield
.disp32
= 1;
10051 else if ((flag_code
== CODE_16BIT
) ^ override
)
10052 bigdisp
.bitfield
.disp16
= 1;
10054 bigdisp
.bitfield
.disp32
= 1;
10058 /* For PC-relative branches, the width of the displacement may be
10059 dependent upon data size, but is never dependent upon address size.
10060 Also make sure to not unintentionally match against a non-PC-relative
10061 branch template. */
10062 static templates aux_templates
;
10063 const insn_template
*t
= current_templates
->start
;
10064 bfd_boolean has_intel64
= FALSE
;
10066 aux_templates
.start
= t
;
10067 while (++t
< current_templates
->end
)
10069 if (t
->opcode_modifier
.jump
10070 != current_templates
->start
->opcode_modifier
.jump
)
10072 if ((t
->opcode_modifier
.isa64
>= INTEL64
))
10073 has_intel64
= TRUE
;
10075 if (t
< current_templates
->end
)
10077 aux_templates
.end
= t
;
10078 current_templates
= &aux_templates
;
10081 override
= (i
.prefix
[DATA_PREFIX
] != 0);
10082 if (flag_code
== CODE_64BIT
)
10084 if ((override
|| i
.suffix
== WORD_MNEM_SUFFIX
)
10085 && (!intel64
|| !has_intel64
))
10086 bigdisp
.bitfield
.disp16
= 1;
10088 bigdisp
.bitfield
.disp32s
= 1;
10093 override
= (i
.suffix
== (flag_code
!= CODE_16BIT
10095 : LONG_MNEM_SUFFIX
));
10096 bigdisp
.bitfield
.disp32
= 1;
10097 if ((flag_code
== CODE_16BIT
) ^ override
)
10099 bigdisp
.bitfield
.disp32
= 0;
10100 bigdisp
.bitfield
.disp16
= 1;
10104 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
10107 exp
= &disp_expressions
[i
.disp_operands
];
10108 i
.op
[this_operand
].disps
= exp
;
10110 save_input_line_pointer
= input_line_pointer
;
10111 input_line_pointer
= disp_start
;
10112 END_STRING_AND_SAVE (disp_end
);
10114 #ifndef GCC_ASM_O_HACK
10115 #define GCC_ASM_O_HACK 0
10118 END_STRING_AND_SAVE (disp_end
+ 1);
10119 if (i
.types
[this_operand
].bitfield
.baseIndex
10120 && displacement_string_end
[-1] == '+')
10122 /* This hack is to avoid a warning when using the "o"
10123 constraint within gcc asm statements.
10126 #define _set_tssldt_desc(n,addr,limit,type) \
10127 __asm__ __volatile__ ( \
10128 "movw %w2,%0\n\t" \
10129 "movw %w1,2+%0\n\t" \
10130 "rorl $16,%1\n\t" \
10131 "movb %b1,4+%0\n\t" \
10132 "movb %4,5+%0\n\t" \
10133 "movb $0,6+%0\n\t" \
10134 "movb %h1,7+%0\n\t" \
10136 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
10138 This works great except that the output assembler ends
10139 up looking a bit weird if it turns out that there is
10140 no offset. You end up producing code that looks like:
10153 So here we provide the missing zero. */
10155 *displacement_string_end
= '0';
10158 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
10159 if (gotfree_input_line
)
10160 input_line_pointer
= gotfree_input_line
;
10162 exp_seg
= expression (exp
);
10164 SKIP_WHITESPACE ();
10165 if (*input_line_pointer
)
10166 as_bad (_("junk `%s' after expression"), input_line_pointer
);
10168 RESTORE_END_STRING (disp_end
+ 1);
10170 input_line_pointer
= save_input_line_pointer
;
10171 if (gotfree_input_line
)
10173 free (gotfree_input_line
);
10175 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
10176 exp
->X_op
= O_illegal
;
10179 ret
= i386_finalize_displacement (exp_seg
, exp
, types
, disp_start
);
10181 RESTORE_END_STRING (disp_end
);
10187 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
10188 i386_operand_type types
, const char *disp_start
)
10190 i386_operand_type bigdisp
;
10193 /* We do this to make sure that the section symbol is in
10194 the symbol table. We will ultimately change the relocation
10195 to be relative to the beginning of the section. */
10196 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
10197 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
10198 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
10200 if (exp
->X_op
!= O_symbol
)
10203 if (S_IS_LOCAL (exp
->X_add_symbol
)
10204 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
10205 && S_GET_SEGMENT (exp
->X_add_symbol
) != expr_section
)
10206 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
10207 exp
->X_op
= O_subtract
;
10208 exp
->X_op_symbol
= GOT_symbol
;
10209 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
10210 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
10211 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
10212 i
.reloc
[this_operand
] = BFD_RELOC_64
;
10214 i
.reloc
[this_operand
] = BFD_RELOC_32
;
10217 else if (exp
->X_op
== O_absent
10218 || exp
->X_op
== O_illegal
10219 || exp
->X_op
== O_big
)
10222 as_bad (_("missing or invalid displacement expression `%s'"),
10227 else if (flag_code
== CODE_64BIT
10228 && !i
.prefix
[ADDR_PREFIX
]
10229 && exp
->X_op
== O_constant
)
10231 /* Since displacement is signed extended to 64bit, don't allow
10232 disp32 and turn off disp32s if they are out of range. */
10233 i
.types
[this_operand
].bitfield
.disp32
= 0;
10234 if (!fits_in_signed_long (exp
->X_add_number
))
10236 i
.types
[this_operand
].bitfield
.disp32s
= 0;
10237 if (i
.types
[this_operand
].bitfield
.baseindex
)
10239 as_bad (_("0x%lx out range of signed 32bit displacement"),
10240 (long) exp
->X_add_number
);
10246 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
10247 else if (exp
->X_op
!= O_constant
10248 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
10249 && exp_seg
!= absolute_section
10250 && exp_seg
!= text_section
10251 && exp_seg
!= data_section
10252 && exp_seg
!= bss_section
10253 && exp_seg
!= undefined_section
10254 && !bfd_is_com_section (exp_seg
))
10256 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
10261 if (current_templates
->start
->opcode_modifier
.jump
== JUMP_BYTE
10262 /* Constants get taken care of by optimize_disp(). */
10263 && exp
->X_op
!= O_constant
)
10264 i
.types
[this_operand
].bitfield
.disp8
= 1;
10266 /* Check if this is a displacement only operand. */
10267 bigdisp
= i
.types
[this_operand
];
10268 bigdisp
.bitfield
.disp8
= 0;
10269 bigdisp
.bitfield
.disp16
= 0;
10270 bigdisp
.bitfield
.disp32
= 0;
10271 bigdisp
.bitfield
.disp32s
= 0;
10272 bigdisp
.bitfield
.disp64
= 0;
10273 if (operand_type_all_zero (&bigdisp
))
10274 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
10280 /* Return the active addressing mode, taking address override and
10281 registers forming the address into consideration. Update the
10282 address override prefix if necessary. */
10284 static enum flag_code
10285 i386_addressing_mode (void)
10287 enum flag_code addr_mode
;
10289 if (i
.prefix
[ADDR_PREFIX
])
10290 addr_mode
= flag_code
== CODE_32BIT
? CODE_16BIT
: CODE_32BIT
;
10293 addr_mode
= flag_code
;
10295 #if INFER_ADDR_PREFIX
10296 if (i
.mem_operands
== 0)
10298 /* Infer address prefix from the first memory operand. */
10299 const reg_entry
*addr_reg
= i
.base_reg
;
10301 if (addr_reg
== NULL
)
10302 addr_reg
= i
.index_reg
;
10306 if (addr_reg
->reg_type
.bitfield
.dword
)
10307 addr_mode
= CODE_32BIT
;
10308 else if (flag_code
!= CODE_64BIT
10309 && addr_reg
->reg_type
.bitfield
.word
)
10310 addr_mode
= CODE_16BIT
;
10312 if (addr_mode
!= flag_code
)
10314 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
10316 /* Change the size of any displacement too. At most one
10317 of Disp16 or Disp32 is set.
10318 FIXME. There doesn't seem to be any real need for
10319 separate Disp16 and Disp32 flags. The same goes for
10320 Imm16 and Imm32. Removing them would probably clean
10321 up the code quite a lot. */
10322 if (flag_code
!= CODE_64BIT
10323 && (i
.types
[this_operand
].bitfield
.disp16
10324 || i
.types
[this_operand
].bitfield
.disp32
))
10325 i
.types
[this_operand
]
10326 = operand_type_xor (i
.types
[this_operand
], disp16_32
);
10336 /* Make sure the memory operand we've been dealt is valid.
10337 Return 1 on success, 0 on a failure. */
10340 i386_index_check (const char *operand_string
)
10342 const char *kind
= "base/index";
10343 enum flag_code addr_mode
= i386_addressing_mode ();
10345 if (current_templates
->start
->opcode_modifier
.isstring
10346 && !current_templates
->start
->cpu_flags
.bitfield
.cpupadlock
10347 && (current_templates
->end
[-1].opcode_modifier
.isstring
10348 || i
.mem_operands
))
10350 /* Memory operands of string insns are special in that they only allow
10351 a single register (rDI, rSI, or rBX) as their memory address. */
10352 const reg_entry
*expected_reg
;
10353 static const char *di_si
[][2] =
10359 static const char *bx
[] = { "ebx", "bx", "rbx" };
10361 kind
= "string address";
10363 if (current_templates
->start
->opcode_modifier
.repprefixok
)
10365 int es_op
= current_templates
->end
[-1].opcode_modifier
.isstring
10366 - IS_STRING_ES_OP0
;
10369 if (!current_templates
->end
[-1].operand_types
[0].bitfield
.baseindex
10370 || ((!i
.mem_operands
!= !intel_syntax
)
10371 && current_templates
->end
[-1].operand_types
[1]
10372 .bitfield
.baseindex
))
10374 expected_reg
= hash_find (reg_hash
, di_si
[addr_mode
][op
== es_op
]);
10377 expected_reg
= hash_find (reg_hash
, bx
[addr_mode
]);
10379 if (i
.base_reg
!= expected_reg
10381 || operand_type_check (i
.types
[this_operand
], disp
))
10383 /* The second memory operand must have the same size as
10387 && !((addr_mode
== CODE_64BIT
10388 && i
.base_reg
->reg_type
.bitfield
.qword
)
10389 || (addr_mode
== CODE_32BIT
10390 ? i
.base_reg
->reg_type
.bitfield
.dword
10391 : i
.base_reg
->reg_type
.bitfield
.word
)))
10394 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
10396 intel_syntax
? '[' : '(',
10398 expected_reg
->reg_name
,
10399 intel_syntax
? ']' : ')');
10406 as_bad (_("`%s' is not a valid %s expression"),
10407 operand_string
, kind
);
10412 if (addr_mode
!= CODE_16BIT
)
10414 /* 32-bit/64-bit checks. */
10416 && ((addr_mode
== CODE_64BIT
10417 ? !i
.base_reg
->reg_type
.bitfield
.qword
10418 : !i
.base_reg
->reg_type
.bitfield
.dword
)
10419 || (i
.index_reg
&& i
.base_reg
->reg_num
== RegIP
)
10420 || i
.base_reg
->reg_num
== RegIZ
))
10422 && !i
.index_reg
->reg_type
.bitfield
.xmmword
10423 && !i
.index_reg
->reg_type
.bitfield
.ymmword
10424 && !i
.index_reg
->reg_type
.bitfield
.zmmword
10425 && ((addr_mode
== CODE_64BIT
10426 ? !i
.index_reg
->reg_type
.bitfield
.qword
10427 : !i
.index_reg
->reg_type
.bitfield
.dword
)
10428 || !i
.index_reg
->reg_type
.bitfield
.baseindex
)))
10431 /* bndmk, bndldx, and bndstx have special restrictions. */
10432 if (current_templates
->start
->base_opcode
== 0xf30f1b
10433 || (current_templates
->start
->base_opcode
& ~1) == 0x0f1a)
10435 /* They cannot use RIP-relative addressing. */
10436 if (i
.base_reg
&& i
.base_reg
->reg_num
== RegIP
)
10438 as_bad (_("`%s' cannot be used here"), operand_string
);
10442 /* bndldx and bndstx ignore their scale factor. */
10443 if (current_templates
->start
->base_opcode
!= 0xf30f1b
10444 && i
.log2_scale_factor
)
10445 as_warn (_("register scaling is being ignored here"));
10450 /* 16-bit checks. */
10452 && (!i
.base_reg
->reg_type
.bitfield
.word
10453 || !i
.base_reg
->reg_type
.bitfield
.baseindex
))
10455 && (!i
.index_reg
->reg_type
.bitfield
.word
10456 || !i
.index_reg
->reg_type
.bitfield
.baseindex
10458 && i
.base_reg
->reg_num
< 6
10459 && i
.index_reg
->reg_num
>= 6
10460 && i
.log2_scale_factor
== 0))))
10467 /* Handle vector immediates. */
10470 RC_SAE_immediate (const char *imm_start
)
10472 unsigned int match_found
, j
;
10473 const char *pstr
= imm_start
;
10481 for (j
= 0; j
< ARRAY_SIZE (RC_NamesTable
); j
++)
10483 if (!strncmp (pstr
, RC_NamesTable
[j
].name
, RC_NamesTable
[j
].len
))
10487 rc_op
.type
= RC_NamesTable
[j
].type
;
10488 rc_op
.operand
= this_operand
;
10489 i
.rounding
= &rc_op
;
10493 as_bad (_("duplicated `%s'"), imm_start
);
10496 pstr
+= RC_NamesTable
[j
].len
;
10504 if (*pstr
++ != '}')
10506 as_bad (_("Missing '}': '%s'"), imm_start
);
10509 /* RC/SAE immediate string should contain nothing more. */;
10512 as_bad (_("Junk after '}': '%s'"), imm_start
);
10516 exp
= &im_expressions
[i
.imm_operands
++];
10517 i
.op
[this_operand
].imms
= exp
;
10519 exp
->X_op
= O_constant
;
10520 exp
->X_add_number
= 0;
10521 exp
->X_add_symbol
= (symbolS
*) 0;
10522 exp
->X_op_symbol
= (symbolS
*) 0;
10524 i
.types
[this_operand
].bitfield
.imm8
= 1;
10528 /* Only string instructions can have a second memory operand, so
10529 reduce current_templates to just those if it contains any. */
10531 maybe_adjust_templates (void)
10533 const insn_template
*t
;
10535 gas_assert (i
.mem_operands
== 1);
10537 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
10538 if (t
->opcode_modifier
.isstring
)
10541 if (t
< current_templates
->end
)
10543 static templates aux_templates
;
10544 bfd_boolean recheck
;
10546 aux_templates
.start
= t
;
10547 for (; t
< current_templates
->end
; ++t
)
10548 if (!t
->opcode_modifier
.isstring
)
10550 aux_templates
.end
= t
;
10552 /* Determine whether to re-check the first memory operand. */
10553 recheck
= (aux_templates
.start
!= current_templates
->start
10554 || t
!= current_templates
->end
);
10556 current_templates
= &aux_templates
;
10560 i
.mem_operands
= 0;
10561 if (i
.memop1_string
!= NULL
10562 && i386_index_check (i
.memop1_string
) == 0)
10564 i
.mem_operands
= 1;
10571 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
10575 i386_att_operand (char *operand_string
)
10577 const reg_entry
*r
;
10579 char *op_string
= operand_string
;
10581 if (is_space_char (*op_string
))
10584 /* We check for an absolute prefix (differentiating,
10585 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
10586 if (*op_string
== ABSOLUTE_PREFIX
)
10589 if (is_space_char (*op_string
))
10591 i
.jumpabsolute
= TRUE
;
10594 /* Check if operand is a register. */
10595 if ((r
= parse_register (op_string
, &end_op
)) != NULL
)
10597 i386_operand_type temp
;
10599 /* Check for a segment override by searching for ':' after a
10600 segment register. */
10601 op_string
= end_op
;
10602 if (is_space_char (*op_string
))
10604 if (*op_string
== ':' && r
->reg_type
.bitfield
.class == SReg
)
10606 switch (r
->reg_num
)
10609 i
.seg
[i
.mem_operands
] = &es
;
10612 i
.seg
[i
.mem_operands
] = &cs
;
10615 i
.seg
[i
.mem_operands
] = &ss
;
10618 i
.seg
[i
.mem_operands
] = &ds
;
10621 i
.seg
[i
.mem_operands
] = &fs
;
10624 i
.seg
[i
.mem_operands
] = &gs
;
10628 /* Skip the ':' and whitespace. */
10630 if (is_space_char (*op_string
))
10633 if (!is_digit_char (*op_string
)
10634 && !is_identifier_char (*op_string
)
10635 && *op_string
!= '('
10636 && *op_string
!= ABSOLUTE_PREFIX
)
10638 as_bad (_("bad memory operand `%s'"), op_string
);
10641 /* Handle case of %es:*foo. */
10642 if (*op_string
== ABSOLUTE_PREFIX
)
10645 if (is_space_char (*op_string
))
10647 i
.jumpabsolute
= TRUE
;
10649 goto do_memory_reference
;
10652 /* Handle vector operations. */
10653 if (*op_string
== '{')
10655 op_string
= check_VecOperations (op_string
, NULL
);
10656 if (op_string
== NULL
)
10662 as_bad (_("junk `%s' after register"), op_string
);
10665 temp
= r
->reg_type
;
10666 temp
.bitfield
.baseindex
= 0;
10667 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
10669 i
.types
[this_operand
].bitfield
.unspecified
= 0;
10670 i
.op
[this_operand
].regs
= r
;
10673 else if (*op_string
== REGISTER_PREFIX
)
10675 as_bad (_("bad register name `%s'"), op_string
);
10678 else if (*op_string
== IMMEDIATE_PREFIX
)
10681 if (i
.jumpabsolute
)
10683 as_bad (_("immediate operand illegal with absolute jump"));
10686 if (!i386_immediate (op_string
))
10689 else if (RC_SAE_immediate (operand_string
))
10691 /* If it is a RC or SAE immediate, do nothing. */
10694 else if (is_digit_char (*op_string
)
10695 || is_identifier_char (*op_string
)
10696 || *op_string
== '"'
10697 || *op_string
== '(')
10699 /* This is a memory reference of some sort. */
10702 /* Start and end of displacement string expression (if found). */
10703 char *displacement_string_start
;
10704 char *displacement_string_end
;
10707 do_memory_reference
:
10708 if (i
.mem_operands
== 1 && !maybe_adjust_templates ())
10710 if ((i
.mem_operands
== 1
10711 && !current_templates
->start
->opcode_modifier
.isstring
)
10712 || i
.mem_operands
== 2)
10714 as_bad (_("too many memory references for `%s'"),
10715 current_templates
->start
->name
);
10719 /* Check for base index form. We detect the base index form by
10720 looking for an ')' at the end of the operand, searching
10721 for the '(' matching it, and finding a REGISTER_PREFIX or ','
10723 base_string
= op_string
+ strlen (op_string
);
10725 /* Handle vector operations. */
10726 vop_start
= strchr (op_string
, '{');
10727 if (vop_start
&& vop_start
< base_string
)
10729 if (check_VecOperations (vop_start
, base_string
) == NULL
)
10731 base_string
= vop_start
;
10735 if (is_space_char (*base_string
))
10738 /* If we only have a displacement, set-up for it to be parsed later. */
10739 displacement_string_start
= op_string
;
10740 displacement_string_end
= base_string
+ 1;
10742 if (*base_string
== ')')
10745 unsigned int parens_balanced
= 1;
10746 /* We've already checked that the number of left & right ()'s are
10747 equal, so this loop will not be infinite. */
10751 if (*base_string
== ')')
10753 if (*base_string
== '(')
10756 while (parens_balanced
);
10758 temp_string
= base_string
;
10760 /* Skip past '(' and whitespace. */
10762 if (is_space_char (*base_string
))
10765 if (*base_string
== ','
10766 || ((i
.base_reg
= parse_register (base_string
, &end_op
))
10769 displacement_string_end
= temp_string
;
10771 i
.types
[this_operand
].bitfield
.baseindex
= 1;
10775 base_string
= end_op
;
10776 if (is_space_char (*base_string
))
10780 /* There may be an index reg or scale factor here. */
10781 if (*base_string
== ',')
10784 if (is_space_char (*base_string
))
10787 if ((i
.index_reg
= parse_register (base_string
, &end_op
))
10790 base_string
= end_op
;
10791 if (is_space_char (*base_string
))
10793 if (*base_string
== ',')
10796 if (is_space_char (*base_string
))
10799 else if (*base_string
!= ')')
10801 as_bad (_("expecting `,' or `)' "
10802 "after index register in `%s'"),
10807 else if (*base_string
== REGISTER_PREFIX
)
10809 end_op
= strchr (base_string
, ',');
10812 as_bad (_("bad register name `%s'"), base_string
);
10816 /* Check for scale factor. */
10817 if (*base_string
!= ')')
10819 char *end_scale
= i386_scale (base_string
);
10824 base_string
= end_scale
;
10825 if (is_space_char (*base_string
))
10827 if (*base_string
!= ')')
10829 as_bad (_("expecting `)' "
10830 "after scale factor in `%s'"),
10835 else if (!i
.index_reg
)
10837 as_bad (_("expecting index register or scale factor "
10838 "after `,'; got '%c'"),
10843 else if (*base_string
!= ')')
10845 as_bad (_("expecting `,' or `)' "
10846 "after base register in `%s'"),
10851 else if (*base_string
== REGISTER_PREFIX
)
10853 end_op
= strchr (base_string
, ',');
10856 as_bad (_("bad register name `%s'"), base_string
);
10861 /* If there's an expression beginning the operand, parse it,
10862 assuming displacement_string_start and
10863 displacement_string_end are meaningful. */
10864 if (displacement_string_start
!= displacement_string_end
)
10866 if (!i386_displacement (displacement_string_start
,
10867 displacement_string_end
))
10871 /* Special case for (%dx) while doing input/output op. */
10873 && i
.base_reg
->reg_type
.bitfield
.instance
== RegD
10874 && i
.base_reg
->reg_type
.bitfield
.word
10875 && i
.index_reg
== 0
10876 && i
.log2_scale_factor
== 0
10877 && i
.seg
[i
.mem_operands
] == 0
10878 && !operand_type_check (i
.types
[this_operand
], disp
))
10880 i
.types
[this_operand
] = i
.base_reg
->reg_type
;
10884 if (i386_index_check (operand_string
) == 0)
10886 i
.flags
[this_operand
] |= Operand_Mem
;
10887 if (i
.mem_operands
== 0)
10888 i
.memop1_string
= xstrdup (operand_string
);
10893 /* It's not a memory operand; argh! */
10894 as_bad (_("invalid char %s beginning operand %d `%s'"),
10895 output_invalid (*op_string
),
10900 return 1; /* Normal return. */
10903 /* Calculate the maximum variable size (i.e., excluding fr_fix)
10904 that an rs_machine_dependent frag may reach. */
10907 i386_frag_max_var (fragS
*frag
)
10909 /* The only relaxable frags are for jumps.
10910 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
10911 gas_assert (frag
->fr_type
== rs_machine_dependent
);
10912 return TYPE_FROM_RELAX_STATE (frag
->fr_subtype
) == UNCOND_JUMP
? 4 : 5;
10915 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10917 elf_symbol_resolved_in_segment_p (symbolS
*fr_symbol
, offsetT fr_var
)
10919 /* STT_GNU_IFUNC symbol must go through PLT. */
10920 if ((symbol_get_bfdsym (fr_symbol
)->flags
10921 & BSF_GNU_INDIRECT_FUNCTION
) != 0)
10924 if (!S_IS_EXTERNAL (fr_symbol
))
10925 /* Symbol may be weak or local. */
10926 return !S_IS_WEAK (fr_symbol
);
10928 /* Global symbols with non-default visibility can't be preempted. */
10929 if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol
)) != STV_DEFAULT
)
10932 if (fr_var
!= NO_RELOC
)
10933 switch ((enum bfd_reloc_code_real
) fr_var
)
10935 case BFD_RELOC_386_PLT32
:
10936 case BFD_RELOC_X86_64_PLT32
:
10937 /* Symbol with PLT relocation may be preempted. */
10943 /* Global symbols with default visibility in a shared library may be
10944 preempted by another definition. */
10949 /* Return the next non-empty frag. */
10952 i386_next_non_empty_frag (fragS
*fragP
)
10954 /* There may be a frag with a ".fill 0" when there is no room in
10955 the current frag for frag_grow in output_insn. */
10956 for (fragP
= fragP
->fr_next
;
10958 && fragP
->fr_type
== rs_fill
10959 && fragP
->fr_fix
== 0);
10960 fragP
= fragP
->fr_next
)
10965 /* Return the next jcc frag after BRANCH_PADDING. */
10968 i386_next_jcc_frag (fragS
*fragP
)
10973 if (fragP
->fr_type
== rs_machine_dependent
10974 && (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
)
10975 == BRANCH_PADDING
))
10977 fragP
= i386_next_non_empty_frag (fragP
);
10978 if (fragP
->fr_type
!= rs_machine_dependent
)
10980 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == COND_JUMP
)
10987 /* Classify BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING frags. */
10990 i386_classify_machine_dependent_frag (fragS
*fragP
)
10994 fragS
*branch_fragP
;
10996 unsigned int max_prefix_length
;
10998 if (fragP
->tc_frag_data
.classified
)
11001 /* First scan for BRANCH_PADDING and FUSED_JCC_PADDING. Convert
11002 FUSED_JCC_PADDING and merge BRANCH_PADDING. */
11003 for (next_fragP
= fragP
;
11004 next_fragP
!= NULL
;
11005 next_fragP
= next_fragP
->fr_next
)
11007 next_fragP
->tc_frag_data
.classified
= 1;
11008 if (next_fragP
->fr_type
== rs_machine_dependent
)
11009 switch (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
))
11011 case BRANCH_PADDING
:
11012 /* The BRANCH_PADDING frag must be followed by a branch
11014 branch_fragP
= i386_next_non_empty_frag (next_fragP
);
11015 next_fragP
->tc_frag_data
.u
.branch_fragP
= branch_fragP
;
11017 case FUSED_JCC_PADDING
:
11018 /* Check if this is a fused jcc:
11020 CMP like instruction
11024 cmp_fragP
= i386_next_non_empty_frag (next_fragP
);
11025 pad_fragP
= i386_next_non_empty_frag (cmp_fragP
);
11026 branch_fragP
= i386_next_jcc_frag (pad_fragP
);
11029 /* The BRANCH_PADDING frag is merged with the
11030 FUSED_JCC_PADDING frag. */
11031 next_fragP
->tc_frag_data
.u
.branch_fragP
= branch_fragP
;
11032 /* CMP like instruction size. */
11033 next_fragP
->tc_frag_data
.cmp_size
= cmp_fragP
->fr_fix
;
11034 frag_wane (pad_fragP
);
11035 /* Skip to branch_fragP. */
11036 next_fragP
= branch_fragP
;
11038 else if (next_fragP
->tc_frag_data
.max_prefix_length
)
11040 /* Turn FUSED_JCC_PADDING into BRANCH_PREFIX if it isn't
11042 next_fragP
->fr_subtype
11043 = ENCODE_RELAX_STATE (BRANCH_PREFIX
, 0);
11044 next_fragP
->tc_frag_data
.max_bytes
11045 = next_fragP
->tc_frag_data
.max_prefix_length
;
11046 /* This will be updated in the BRANCH_PREFIX scan. */
11047 next_fragP
->tc_frag_data
.max_prefix_length
= 0;
11050 frag_wane (next_fragP
);
11055 /* Stop if there is no BRANCH_PREFIX. */
11056 if (!align_branch_prefix_size
)
11059 /* Scan for BRANCH_PREFIX. */
11060 for (; fragP
!= NULL
; fragP
= fragP
->fr_next
)
11062 if (fragP
->fr_type
!= rs_machine_dependent
11063 || (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
)
11067 /* Count all BRANCH_PREFIX frags before BRANCH_PADDING and
11068 COND_JUMP_PREFIX. */
11069 max_prefix_length
= 0;
11070 for (next_fragP
= fragP
;
11071 next_fragP
!= NULL
;
11072 next_fragP
= next_fragP
->fr_next
)
11074 if (next_fragP
->fr_type
== rs_fill
)
11075 /* Skip rs_fill frags. */
11077 else if (next_fragP
->fr_type
!= rs_machine_dependent
)
11078 /* Stop for all other frags. */
11081 /* rs_machine_dependent frags. */
11082 if (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
11085 /* Count BRANCH_PREFIX frags. */
11086 if (max_prefix_length
>= MAX_FUSED_JCC_PADDING_SIZE
)
11088 max_prefix_length
= MAX_FUSED_JCC_PADDING_SIZE
;
11089 frag_wane (next_fragP
);
11093 += next_fragP
->tc_frag_data
.max_bytes
;
11095 else if ((TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
11097 || (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
11098 == FUSED_JCC_PADDING
))
11100 /* Stop at BRANCH_PADDING and FUSED_JCC_PADDING. */
11101 fragP
->tc_frag_data
.u
.padding_fragP
= next_fragP
;
11105 /* Stop for other rs_machine_dependent frags. */
11109 fragP
->tc_frag_data
.max_prefix_length
= max_prefix_length
;
11111 /* Skip to the next frag. */
11112 fragP
= next_fragP
;
11116 /* Compute padding size for
11119 CMP like instruction
11121 COND_JUMP/UNCOND_JUMP
11126 COND_JUMP/UNCOND_JUMP
11130 i386_branch_padding_size (fragS
*fragP
, offsetT address
)
11132 unsigned int offset
, size
, padding_size
;
11133 fragS
*branch_fragP
= fragP
->tc_frag_data
.u
.branch_fragP
;
11135 /* The start address of the BRANCH_PADDING or FUSED_JCC_PADDING frag. */
11137 address
= fragP
->fr_address
;
11138 address
+= fragP
->fr_fix
;
11140 /* CMP like instrunction size. */
11141 size
= fragP
->tc_frag_data
.cmp_size
;
11143 /* The base size of the branch frag. */
11144 size
+= branch_fragP
->fr_fix
;
11146 /* Add opcode and displacement bytes for the rs_machine_dependent
11148 if (branch_fragP
->fr_type
== rs_machine_dependent
)
11149 size
+= md_relax_table
[branch_fragP
->fr_subtype
].rlx_length
;
11151 /* Check if branch is within boundary and doesn't end at the last
11153 offset
= address
& ((1U << align_branch_power
) - 1);
11154 if ((offset
+ size
) >= (1U << align_branch_power
))
11155 /* Padding needed to avoid crossing boundary. */
11156 padding_size
= (1U << align_branch_power
) - offset
;
11158 /* No padding needed. */
11161 /* The return value may be saved in tc_frag_data.length which is
11163 if (!fits_in_unsigned_byte (padding_size
))
11166 return padding_size
;
11169 /* i386_generic_table_relax_frag()
11171 Handle BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING frags to
11172 grow/shrink padding to align branch frags. Hand others to
11176 i386_generic_table_relax_frag (segT segment
, fragS
*fragP
, long stretch
)
11178 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
11179 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
)
11181 long padding_size
= i386_branch_padding_size (fragP
, 0);
11182 long grow
= padding_size
- fragP
->tc_frag_data
.length
;
11184 /* When the BRANCH_PREFIX frag is used, the computed address
11185 must match the actual address and there should be no padding. */
11186 if (fragP
->tc_frag_data
.padding_address
11187 && (fragP
->tc_frag_data
.padding_address
!= fragP
->fr_address
11191 /* Update the padding size. */
11193 fragP
->tc_frag_data
.length
= padding_size
;
11197 else if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
)
11199 fragS
*padding_fragP
, *next_fragP
;
11200 long padding_size
, left_size
, last_size
;
11202 padding_fragP
= fragP
->tc_frag_data
.u
.padding_fragP
;
11203 if (!padding_fragP
)
11204 /* Use the padding set by the leading BRANCH_PREFIX frag. */
11205 return (fragP
->tc_frag_data
.length
11206 - fragP
->tc_frag_data
.last_length
);
11208 /* Compute the relative address of the padding frag in the very
11209 first time where the BRANCH_PREFIX frag sizes are zero. */
11210 if (!fragP
->tc_frag_data
.padding_address
)
11211 fragP
->tc_frag_data
.padding_address
11212 = padding_fragP
->fr_address
- (fragP
->fr_address
- stretch
);
11214 /* First update the last length from the previous interation. */
11215 left_size
= fragP
->tc_frag_data
.prefix_length
;
11216 for (next_fragP
= fragP
;
11217 next_fragP
!= padding_fragP
;
11218 next_fragP
= next_fragP
->fr_next
)
11219 if (next_fragP
->fr_type
== rs_machine_dependent
11220 && (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
11225 int max
= next_fragP
->tc_frag_data
.max_bytes
;
11229 if (max
> left_size
)
11234 next_fragP
->tc_frag_data
.last_length
= size
;
11238 next_fragP
->tc_frag_data
.last_length
= 0;
11241 /* Check the padding size for the padding frag. */
11242 padding_size
= i386_branch_padding_size
11243 (padding_fragP
, (fragP
->fr_address
11244 + fragP
->tc_frag_data
.padding_address
));
11246 last_size
= fragP
->tc_frag_data
.prefix_length
;
11247 /* Check if there is change from the last interation. */
11248 if (padding_size
== last_size
)
11250 /* Update the expected address of the padding frag. */
11251 padding_fragP
->tc_frag_data
.padding_address
11252 = (fragP
->fr_address
+ padding_size
11253 + fragP
->tc_frag_data
.padding_address
);
11257 if (padding_size
> fragP
->tc_frag_data
.max_prefix_length
)
11259 /* No padding if there is no sufficient room. Clear the
11260 expected address of the padding frag. */
11261 padding_fragP
->tc_frag_data
.padding_address
= 0;
11265 /* Store the expected address of the padding frag. */
11266 padding_fragP
->tc_frag_data
.padding_address
11267 = (fragP
->fr_address
+ padding_size
11268 + fragP
->tc_frag_data
.padding_address
);
11270 fragP
->tc_frag_data
.prefix_length
= padding_size
;
11272 /* Update the length for the current interation. */
11273 left_size
= padding_size
;
11274 for (next_fragP
= fragP
;
11275 next_fragP
!= padding_fragP
;
11276 next_fragP
= next_fragP
->fr_next
)
11277 if (next_fragP
->fr_type
== rs_machine_dependent
11278 && (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
11283 int max
= next_fragP
->tc_frag_data
.max_bytes
;
11287 if (max
> left_size
)
11292 next_fragP
->tc_frag_data
.length
= size
;
11296 next_fragP
->tc_frag_data
.length
= 0;
11299 return (fragP
->tc_frag_data
.length
11300 - fragP
->tc_frag_data
.last_length
);
11302 return relax_frag (segment
, fragP
, stretch
);
11305 /* md_estimate_size_before_relax()
11307 Called just before relax() for rs_machine_dependent frags. The x86
11308 assembler uses these frags to handle variable size jump
11311 Any symbol that is now undefined will not become defined.
11312 Return the correct fr_subtype in the frag.
11313 Return the initial "guess for variable size of frag" to caller.
11314 The guess is actually the growth beyond the fixed part. Whatever
11315 we do to grow the fixed or variable part contributes to our
11319 md_estimate_size_before_relax (fragS
*fragP
, segT segment
)
11321 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
11322 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
11323 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
)
11325 i386_classify_machine_dependent_frag (fragP
);
11326 return fragP
->tc_frag_data
.length
;
11329 /* We've already got fragP->fr_subtype right; all we have to do is
11330 check for un-relaxable symbols. On an ELF system, we can't relax
11331 an externally visible symbol, because it may be overridden by a
11333 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
11334 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11336 && !elf_symbol_resolved_in_segment_p (fragP
->fr_symbol
,
11339 #if defined (OBJ_COFF) && defined (TE_PE)
11340 || (OUTPUT_FLAVOR
== bfd_target_coff_flavour
11341 && S_IS_WEAK (fragP
->fr_symbol
))
11345 /* Symbol is undefined in this segment, or we need to keep a
11346 reloc so that weak symbols can be overridden. */
11347 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
11348 enum bfd_reloc_code_real reloc_type
;
11349 unsigned char *opcode
;
11352 if (fragP
->fr_var
!= NO_RELOC
)
11353 reloc_type
= (enum bfd_reloc_code_real
) fragP
->fr_var
;
11354 else if (size
== 2)
11355 reloc_type
= BFD_RELOC_16_PCREL
;
11356 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11357 else if (need_plt32_p (fragP
->fr_symbol
))
11358 reloc_type
= BFD_RELOC_X86_64_PLT32
;
11361 reloc_type
= BFD_RELOC_32_PCREL
;
11363 old_fr_fix
= fragP
->fr_fix
;
11364 opcode
= (unsigned char *) fragP
->fr_opcode
;
11366 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
11369 /* Make jmp (0xeb) a (d)word displacement jump. */
11371 fragP
->fr_fix
+= size
;
11372 fix_new (fragP
, old_fr_fix
, size
,
11374 fragP
->fr_offset
, 1,
11380 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
11382 /* Negate the condition, and branch past an
11383 unconditional jump. */
11386 /* Insert an unconditional jump. */
11388 /* We added two extra opcode bytes, and have a two byte
11390 fragP
->fr_fix
+= 2 + 2;
11391 fix_new (fragP
, old_fr_fix
+ 2, 2,
11393 fragP
->fr_offset
, 1,
11397 /* Fall through. */
11400 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
11404 fragP
->fr_fix
+= 1;
11405 fixP
= fix_new (fragP
, old_fr_fix
, 1,
11407 fragP
->fr_offset
, 1,
11408 BFD_RELOC_8_PCREL
);
11409 fixP
->fx_signed
= 1;
11413 /* This changes the byte-displacement jump 0x7N
11414 to the (d)word-displacement jump 0x0f,0x8N. */
11415 opcode
[1] = opcode
[0] + 0x10;
11416 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
11417 /* We've added an opcode byte. */
11418 fragP
->fr_fix
+= 1 + size
;
11419 fix_new (fragP
, old_fr_fix
+ 1, size
,
11421 fragP
->fr_offset
, 1,
11426 BAD_CASE (fragP
->fr_subtype
);
11430 return fragP
->fr_fix
- old_fr_fix
;
11433 /* Guess size depending on current relax state. Initially the relax
11434 state will correspond to a short jump and we return 1, because
11435 the variable part of the frag (the branch offset) is one byte
11436 long. However, we can relax a section more than once and in that
11437 case we must either set fr_subtype back to the unrelaxed state,
11438 or return the value for the appropriate branch. */
11439 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
11442 /* Called after relax() is finished.
11444 In: Address of frag.
11445 fr_type == rs_machine_dependent.
11446 fr_subtype is what the address relaxed to.
11448 Out: Any fixSs and constants are set up.
11449 Caller will turn frag into a ".space 0". */
11452 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec ATTRIBUTE_UNUSED
,
11455 unsigned char *opcode
;
11456 unsigned char *where_to_put_displacement
= NULL
;
11457 offsetT target_address
;
11458 offsetT opcode_address
;
11459 unsigned int extension
= 0;
11460 offsetT displacement_from_opcode_start
;
11462 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
11463 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
11464 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
)
11466 /* Generate nop padding. */
11467 unsigned int size
= fragP
->tc_frag_data
.length
;
11470 if (size
> fragP
->tc_frag_data
.max_bytes
)
11476 const char *branch
= "branch";
11477 const char *prefix
= "";
11478 fragS
*padding_fragP
;
11479 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
)
11482 padding_fragP
= fragP
->tc_frag_data
.u
.padding_fragP
;
11483 switch (fragP
->tc_frag_data
.default_prefix
)
11488 case CS_PREFIX_OPCODE
:
11491 case DS_PREFIX_OPCODE
:
11494 case ES_PREFIX_OPCODE
:
11497 case FS_PREFIX_OPCODE
:
11500 case GS_PREFIX_OPCODE
:
11503 case SS_PREFIX_OPCODE
:
11508 msg
= _("%s:%u: add %d%s at 0x%llx to align "
11509 "%s within %d-byte boundary\n");
11511 msg
= _("%s:%u: add additional %d%s at 0x%llx to "
11512 "align %s within %d-byte boundary\n");
11516 padding_fragP
= fragP
;
11517 msg
= _("%s:%u: add %d%s-byte nop at 0x%llx to align "
11518 "%s within %d-byte boundary\n");
11522 switch (padding_fragP
->tc_frag_data
.branch_type
)
11524 case align_branch_jcc
:
11527 case align_branch_fused
:
11528 branch
= "fused jcc";
11530 case align_branch_jmp
:
11533 case align_branch_call
:
11536 case align_branch_indirect
:
11537 branch
= "indiret branch";
11539 case align_branch_ret
:
11546 fprintf (stdout
, msg
,
11547 fragP
->fr_file
, fragP
->fr_line
, size
, prefix
,
11548 (long long) fragP
->fr_address
, branch
,
11549 1 << align_branch_power
);
11551 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
)
11552 memset (fragP
->fr_opcode
,
11553 fragP
->tc_frag_data
.default_prefix
, size
);
11555 i386_generate_nops (fragP
, (char *) fragP
->fr_opcode
,
11557 fragP
->fr_fix
+= size
;
11562 opcode
= (unsigned char *) fragP
->fr_opcode
;
11564 /* Address we want to reach in file space. */
11565 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
11567 /* Address opcode resides at in file space. */
11568 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
11570 /* Displacement from opcode start to fill into instruction. */
11571 displacement_from_opcode_start
= target_address
- opcode_address
;
11573 if ((fragP
->fr_subtype
& BIG
) == 0)
11575 /* Don't have to change opcode. */
11576 extension
= 1; /* 1 opcode + 1 displacement */
11577 where_to_put_displacement
= &opcode
[1];
11581 if (no_cond_jump_promotion
11582 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
11583 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
11584 _("long jump required"));
11586 switch (fragP
->fr_subtype
)
11588 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
11589 extension
= 4; /* 1 opcode + 4 displacement */
11591 where_to_put_displacement
= &opcode
[1];
11594 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
11595 extension
= 2; /* 1 opcode + 2 displacement */
11597 where_to_put_displacement
= &opcode
[1];
11600 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
11601 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
11602 extension
= 5; /* 2 opcode + 4 displacement */
11603 opcode
[1] = opcode
[0] + 0x10;
11604 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
11605 where_to_put_displacement
= &opcode
[2];
11608 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
11609 extension
= 3; /* 2 opcode + 2 displacement */
11610 opcode
[1] = opcode
[0] + 0x10;
11611 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
11612 where_to_put_displacement
= &opcode
[2];
11615 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
11620 where_to_put_displacement
= &opcode
[3];
11624 BAD_CASE (fragP
->fr_subtype
);
11629 /* If size if less then four we are sure that the operand fits,
11630 but if it's 4, then it could be that the displacement is larger
11632 if (DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
) == 4
11634 && ((addressT
) (displacement_from_opcode_start
- extension
11635 + ((addressT
) 1 << 31))
11636 > (((addressT
) 2 << 31) - 1)))
11638 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
11639 _("jump target out of range"));
11640 /* Make us emit 0. */
11641 displacement_from_opcode_start
= extension
;
11643 /* Now put displacement after opcode. */
11644 md_number_to_chars ((char *) where_to_put_displacement
,
11645 (valueT
) (displacement_from_opcode_start
- extension
),
11646 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
11647 fragP
->fr_fix
+= extension
;
11650 /* Apply a fixup (fixP) to segment data, once it has been determined
11651 by our caller that we have all the info we need to fix it up.
11653 Parameter valP is the pointer to the value of the bits.
11655 On the 386, immediates, displacements, and data pointers are all in
11656 the same (little-endian) format, so we don't need to care about which
11657 we are handling. */
11660 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
11662 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
11663 valueT value
= *valP
;
11665 #if !defined (TE_Mach)
11666 if (fixP
->fx_pcrel
)
11668 switch (fixP
->fx_r_type
)
11674 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
11677 case BFD_RELOC_X86_64_32S
:
11678 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
11681 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
11684 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
11689 if (fixP
->fx_addsy
!= NULL
11690 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
11691 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
11692 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
11693 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
11694 && !use_rela_relocations
)
11696 /* This is a hack. There should be a better way to handle this.
11697 This covers for the fact that bfd_install_relocation will
11698 subtract the current location (for partial_inplace, PC relative
11699 relocations); see more below. */
11703 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
11706 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
11708 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11711 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
11713 if ((sym_seg
== seg
11714 || (symbol_section_p (fixP
->fx_addsy
)
11715 && sym_seg
!= absolute_section
))
11716 && !generic_force_reloc (fixP
))
11718 /* Yes, we add the values in twice. This is because
11719 bfd_install_relocation subtracts them out again. I think
11720 bfd_install_relocation is broken, but I don't dare change
11722 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
11726 #if defined (OBJ_COFF) && defined (TE_PE)
11727 /* For some reason, the PE format does not store a
11728 section address offset for a PC relative symbol. */
11729 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
11730 || S_IS_WEAK (fixP
->fx_addsy
))
11731 value
+= md_pcrel_from (fixP
);
11734 #if defined (OBJ_COFF) && defined (TE_PE)
11735 if (fixP
->fx_addsy
!= NULL
11736 && S_IS_WEAK (fixP
->fx_addsy
)
11737 /* PR 16858: Do not modify weak function references. */
11738 && ! fixP
->fx_pcrel
)
11740 #if !defined (TE_PEP)
11741 /* For x86 PE weak function symbols are neither PC-relative
11742 nor do they set S_IS_FUNCTION. So the only reliable way
11743 to detect them is to check the flags of their containing
11745 if (S_GET_SEGMENT (fixP
->fx_addsy
) != NULL
11746 && S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_CODE
)
11750 value
-= S_GET_VALUE (fixP
->fx_addsy
);
11754 /* Fix a few things - the dynamic linker expects certain values here,
11755 and we must not disappoint it. */
11756 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11757 if (IS_ELF
&& fixP
->fx_addsy
)
11758 switch (fixP
->fx_r_type
)
11760 case BFD_RELOC_386_PLT32
:
11761 case BFD_RELOC_X86_64_PLT32
:
11762 /* Make the jump instruction point to the address of the operand.
11763 At runtime we merely add the offset to the actual PLT entry.
11764 NB: Subtract the offset size only for jump instructions. */
11765 if (fixP
->fx_pcrel
)
11769 case BFD_RELOC_386_TLS_GD
:
11770 case BFD_RELOC_386_TLS_LDM
:
11771 case BFD_RELOC_386_TLS_IE_32
:
11772 case BFD_RELOC_386_TLS_IE
:
11773 case BFD_RELOC_386_TLS_GOTIE
:
11774 case BFD_RELOC_386_TLS_GOTDESC
:
11775 case BFD_RELOC_X86_64_TLSGD
:
11776 case BFD_RELOC_X86_64_TLSLD
:
11777 case BFD_RELOC_X86_64_GOTTPOFF
:
11778 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
11779 value
= 0; /* Fully resolved at runtime. No addend. */
11781 case BFD_RELOC_386_TLS_LE
:
11782 case BFD_RELOC_386_TLS_LDO_32
:
11783 case BFD_RELOC_386_TLS_LE_32
:
11784 case BFD_RELOC_X86_64_DTPOFF32
:
11785 case BFD_RELOC_X86_64_DTPOFF64
:
11786 case BFD_RELOC_X86_64_TPOFF32
:
11787 case BFD_RELOC_X86_64_TPOFF64
:
11788 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
11791 case BFD_RELOC_386_TLS_DESC_CALL
:
11792 case BFD_RELOC_X86_64_TLSDESC_CALL
:
11793 value
= 0; /* Fully resolved at runtime. No addend. */
11794 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
11798 case BFD_RELOC_VTABLE_INHERIT
:
11799 case BFD_RELOC_VTABLE_ENTRY
:
11806 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
11808 #endif /* !defined (TE_Mach) */
11810 /* Are we finished with this relocation now? */
11811 if (fixP
->fx_addsy
== NULL
)
11813 #if defined (OBJ_COFF) && defined (TE_PE)
11814 else if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
11817 /* Remember value for tc_gen_reloc. */
11818 fixP
->fx_addnumber
= value
;
11819 /* Clear out the frag for now. */
11823 else if (use_rela_relocations
)
11825 fixP
->fx_no_overflow
= 1;
11826 /* Remember value for tc_gen_reloc. */
11827 fixP
->fx_addnumber
= value
;
11831 md_number_to_chars (p
, value
, fixP
->fx_size
);
11835 md_atof (int type
, char *litP
, int *sizeP
)
11837 /* This outputs the LITTLENUMs in REVERSE order;
11838 in accord with the bigendian 386. */
11839 return ieee_md_atof (type
, litP
, sizeP
, FALSE
);
11842 static char output_invalid_buf
[sizeof (unsigned char) * 2 + 6];
11845 output_invalid (int c
)
11848 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
11851 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
11852 "(0x%x)", (unsigned char) c
);
11853 return output_invalid_buf
;
11856 /* REG_STRING starts *before* REGISTER_PREFIX. */
11858 static const reg_entry
*
11859 parse_real_register (char *reg_string
, char **end_op
)
11861 char *s
= reg_string
;
11863 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
11864 const reg_entry
*r
;
11866 /* Skip possible REGISTER_PREFIX and possible whitespace. */
11867 if (*s
== REGISTER_PREFIX
)
11870 if (is_space_char (*s
))
11873 p
= reg_name_given
;
11874 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
11876 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
11877 return (const reg_entry
*) NULL
;
11881 /* For naked regs, make sure that we are not dealing with an identifier.
11882 This prevents confusing an identifier like `eax_var' with register
11884 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
11885 return (const reg_entry
*) NULL
;
11889 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
11891 /* Handle floating point regs, allowing spaces in the (i) part. */
11892 if (r
== i386_regtab
/* %st is first entry of table */)
11894 if (!cpu_arch_flags
.bitfield
.cpu8087
11895 && !cpu_arch_flags
.bitfield
.cpu287
11896 && !cpu_arch_flags
.bitfield
.cpu387
)
11897 return (const reg_entry
*) NULL
;
11899 if (is_space_char (*s
))
11904 if (is_space_char (*s
))
11906 if (*s
>= '0' && *s
<= '7')
11908 int fpr
= *s
- '0';
11910 if (is_space_char (*s
))
11915 r
= (const reg_entry
*) hash_find (reg_hash
, "st(0)");
11920 /* We have "%st(" then garbage. */
11921 return (const reg_entry
*) NULL
;
11925 if (r
== NULL
|| allow_pseudo_reg
)
11928 if (operand_type_all_zero (&r
->reg_type
))
11929 return (const reg_entry
*) NULL
;
11931 if ((r
->reg_type
.bitfield
.dword
11932 || (r
->reg_type
.bitfield
.class == SReg
&& r
->reg_num
> 3)
11933 || r
->reg_type
.bitfield
.class == RegCR
11934 || r
->reg_type
.bitfield
.class == RegDR
11935 || r
->reg_type
.bitfield
.class == RegTR
)
11936 && !cpu_arch_flags
.bitfield
.cpui386
)
11937 return (const reg_entry
*) NULL
;
11939 if (r
->reg_type
.bitfield
.class == RegMMX
&& !cpu_arch_flags
.bitfield
.cpummx
)
11940 return (const reg_entry
*) NULL
;
11942 if (!cpu_arch_flags
.bitfield
.cpuavx512f
)
11944 if (r
->reg_type
.bitfield
.zmmword
11945 || r
->reg_type
.bitfield
.class == RegMask
)
11946 return (const reg_entry
*) NULL
;
11948 if (!cpu_arch_flags
.bitfield
.cpuavx
)
11950 if (r
->reg_type
.bitfield
.ymmword
)
11951 return (const reg_entry
*) NULL
;
11953 if (!cpu_arch_flags
.bitfield
.cpusse
&& r
->reg_type
.bitfield
.xmmword
)
11954 return (const reg_entry
*) NULL
;
11958 if (r
->reg_type
.bitfield
.class == RegBND
&& !cpu_arch_flags
.bitfield
.cpumpx
)
11959 return (const reg_entry
*) NULL
;
11961 /* Don't allow fake index register unless allow_index_reg isn't 0. */
11962 if (!allow_index_reg
&& r
->reg_num
== RegIZ
)
11963 return (const reg_entry
*) NULL
;
11965 /* Upper 16 vector registers are only available with VREX in 64bit
11966 mode, and require EVEX encoding. */
11967 if (r
->reg_flags
& RegVRex
)
11969 if (!cpu_arch_flags
.bitfield
.cpuavx512f
11970 || flag_code
!= CODE_64BIT
)
11971 return (const reg_entry
*) NULL
;
11973 i
.vec_encoding
= vex_encoding_evex
;
11976 if (((r
->reg_flags
& (RegRex64
| RegRex
)) || r
->reg_type
.bitfield
.qword
)
11977 && (!cpu_arch_flags
.bitfield
.cpulm
|| r
->reg_type
.bitfield
.class != RegCR
)
11978 && flag_code
!= CODE_64BIT
)
11979 return (const reg_entry
*) NULL
;
11981 if (r
->reg_type
.bitfield
.class == SReg
&& r
->reg_num
== RegFlat
11983 return (const reg_entry
*) NULL
;
11988 /* REG_STRING starts *before* REGISTER_PREFIX. */
11990 static const reg_entry
*
11991 parse_register (char *reg_string
, char **end_op
)
11993 const reg_entry
*r
;
11995 if (*reg_string
== REGISTER_PREFIX
|| allow_naked_reg
)
11996 r
= parse_real_register (reg_string
, end_op
);
12001 char *save
= input_line_pointer
;
12005 input_line_pointer
= reg_string
;
12006 c
= get_symbol_name (®_string
);
12007 symbolP
= symbol_find (reg_string
);
12008 if (symbolP
&& S_GET_SEGMENT (symbolP
) == reg_section
)
12010 const expressionS
*e
= symbol_get_value_expression (symbolP
);
12012 know (e
->X_op
== O_register
);
12013 know (e
->X_add_number
>= 0
12014 && (valueT
) e
->X_add_number
< i386_regtab_size
);
12015 r
= i386_regtab
+ e
->X_add_number
;
12016 if ((r
->reg_flags
& RegVRex
))
12017 i
.vec_encoding
= vex_encoding_evex
;
12018 *end_op
= input_line_pointer
;
12020 *input_line_pointer
= c
;
12021 input_line_pointer
= save
;
12027 i386_parse_name (char *name
, expressionS
*e
, char *nextcharP
)
12029 const reg_entry
*r
;
12030 char *end
= input_line_pointer
;
12033 r
= parse_register (name
, &input_line_pointer
);
12034 if (r
&& end
<= input_line_pointer
)
12036 *nextcharP
= *input_line_pointer
;
12037 *input_line_pointer
= 0;
12038 e
->X_op
= O_register
;
12039 e
->X_add_number
= r
- i386_regtab
;
12042 input_line_pointer
= end
;
12044 return intel_syntax
? i386_intel_parse_name (name
, e
) : 0;
12048 md_operand (expressionS
*e
)
12051 const reg_entry
*r
;
12053 switch (*input_line_pointer
)
12055 case REGISTER_PREFIX
:
12056 r
= parse_real_register (input_line_pointer
, &end
);
12059 e
->X_op
= O_register
;
12060 e
->X_add_number
= r
- i386_regtab
;
12061 input_line_pointer
= end
;
12066 gas_assert (intel_syntax
);
12067 end
= input_line_pointer
++;
12069 if (*input_line_pointer
== ']')
12071 ++input_line_pointer
;
12072 e
->X_op_symbol
= make_expr_symbol (e
);
12073 e
->X_add_symbol
= NULL
;
12074 e
->X_add_number
= 0;
12079 e
->X_op
= O_absent
;
12080 input_line_pointer
= end
;
12087 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12088 const char *md_shortopts
= "kVQ:sqnO::";
12090 const char *md_shortopts
= "qnO::";
12093 #define OPTION_32 (OPTION_MD_BASE + 0)
12094 #define OPTION_64 (OPTION_MD_BASE + 1)
12095 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
12096 #define OPTION_MARCH (OPTION_MD_BASE + 3)
12097 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
12098 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
12099 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
12100 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
12101 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
12102 #define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 9)
12103 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
12104 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
12105 #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
12106 #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
12107 #define OPTION_X32 (OPTION_MD_BASE + 14)
12108 #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
12109 #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
12110 #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
12111 #define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
12112 #define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
12113 #define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
12114 #define OPTION_MSHARED (OPTION_MD_BASE + 21)
12115 #define OPTION_MAMD64 (OPTION_MD_BASE + 22)
12116 #define OPTION_MINTEL64 (OPTION_MD_BASE + 23)
12117 #define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24)
12118 #define OPTION_X86_USED_NOTE (OPTION_MD_BASE + 25)
12119 #define OPTION_MVEXWIG (OPTION_MD_BASE + 26)
12120 #define OPTION_MALIGN_BRANCH_BOUNDARY (OPTION_MD_BASE + 27)
12121 #define OPTION_MALIGN_BRANCH_PREFIX_SIZE (OPTION_MD_BASE + 28)
12122 #define OPTION_MALIGN_BRANCH (OPTION_MD_BASE + 29)
12123 #define OPTION_MBRANCHES_WITH_32B_BOUNDARIES (OPTION_MD_BASE + 30)
12125 struct option md_longopts
[] =
12127 {"32", no_argument
, NULL
, OPTION_32
},
12128 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
12129 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
12130 {"64", no_argument
, NULL
, OPTION_64
},
12132 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12133 {"x32", no_argument
, NULL
, OPTION_X32
},
12134 {"mshared", no_argument
, NULL
, OPTION_MSHARED
},
12135 {"mx86-used-note", required_argument
, NULL
, OPTION_X86_USED_NOTE
},
12137 {"divide", no_argument
, NULL
, OPTION_DIVIDE
},
12138 {"march", required_argument
, NULL
, OPTION_MARCH
},
12139 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
12140 {"mmnemonic", required_argument
, NULL
, OPTION_MMNEMONIC
},
12141 {"msyntax", required_argument
, NULL
, OPTION_MSYNTAX
},
12142 {"mindex-reg", no_argument
, NULL
, OPTION_MINDEX_REG
},
12143 {"mnaked-reg", no_argument
, NULL
, OPTION_MNAKED_REG
},
12144 {"msse2avx", no_argument
, NULL
, OPTION_MSSE2AVX
},
12145 {"msse-check", required_argument
, NULL
, OPTION_MSSE_CHECK
},
12146 {"moperand-check", required_argument
, NULL
, OPTION_MOPERAND_CHECK
},
12147 {"mavxscalar", required_argument
, NULL
, OPTION_MAVXSCALAR
},
12148 {"mvexwig", required_argument
, NULL
, OPTION_MVEXWIG
},
12149 {"madd-bnd-prefix", no_argument
, NULL
, OPTION_MADD_BND_PREFIX
},
12150 {"mevexlig", required_argument
, NULL
, OPTION_MEVEXLIG
},
12151 {"mevexwig", required_argument
, NULL
, OPTION_MEVEXWIG
},
12152 # if defined (TE_PE) || defined (TE_PEP)
12153 {"mbig-obj", no_argument
, NULL
, OPTION_MBIG_OBJ
},
12155 {"momit-lock-prefix", required_argument
, NULL
, OPTION_MOMIT_LOCK_PREFIX
},
12156 {"mfence-as-lock-add", required_argument
, NULL
, OPTION_MFENCE_AS_LOCK_ADD
},
12157 {"mrelax-relocations", required_argument
, NULL
, OPTION_MRELAX_RELOCATIONS
},
12158 {"mevexrcig", required_argument
, NULL
, OPTION_MEVEXRCIG
},
12159 {"malign-branch-boundary", required_argument
, NULL
, OPTION_MALIGN_BRANCH_BOUNDARY
},
12160 {"malign-branch-prefix-size", required_argument
, NULL
, OPTION_MALIGN_BRANCH_PREFIX_SIZE
},
12161 {"malign-branch", required_argument
, NULL
, OPTION_MALIGN_BRANCH
},
12162 {"mbranches-within-32B-boundaries", no_argument
, NULL
, OPTION_MBRANCHES_WITH_32B_BOUNDARIES
},
12163 {"mamd64", no_argument
, NULL
, OPTION_MAMD64
},
12164 {"mintel64", no_argument
, NULL
, OPTION_MINTEL64
},
12165 {NULL
, no_argument
, NULL
, 0}
12167 size_t md_longopts_size
= sizeof (md_longopts
);
12170 md_parse_option (int c
, const char *arg
)
12173 char *arch
, *next
, *saved
, *type
;
12178 optimize_align_code
= 0;
12182 quiet_warnings
= 1;
12185 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12186 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
12187 should be emitted or not. FIXME: Not implemented. */
12189 if ((arg
[0] != 'y' && arg
[0] != 'n') || arg
[1])
12193 /* -V: SVR4 argument to print version ID. */
12195 print_version_id ();
12198 /* -k: Ignore for FreeBSD compatibility. */
12203 /* -s: On i386 Solaris, this tells the native assembler to use
12204 .stab instead of .stab.excl. We always use .stab anyhow. */
12207 case OPTION_MSHARED
:
12211 case OPTION_X86_USED_NOTE
:
12212 if (strcasecmp (arg
, "yes") == 0)
12214 else if (strcasecmp (arg
, "no") == 0)
12217 as_fatal (_("invalid -mx86-used-note= option: `%s'"), arg
);
12222 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
12223 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
12226 const char **list
, **l
;
12228 list
= bfd_target_list ();
12229 for (l
= list
; *l
!= NULL
; l
++)
12230 if (CONST_STRNEQ (*l
, "elf64-x86-64")
12231 || strcmp (*l
, "coff-x86-64") == 0
12232 || strcmp (*l
, "pe-x86-64") == 0
12233 || strcmp (*l
, "pei-x86-64") == 0
12234 || strcmp (*l
, "mach-o-x86-64") == 0)
12236 default_arch
= "x86_64";
12240 as_fatal (_("no compiled in support for x86_64"));
12246 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12250 const char **list
, **l
;
12252 list
= bfd_target_list ();
12253 for (l
= list
; *l
!= NULL
; l
++)
12254 if (CONST_STRNEQ (*l
, "elf32-x86-64"))
12256 default_arch
= "x86_64:32";
12260 as_fatal (_("no compiled in support for 32bit x86_64"));
12264 as_fatal (_("32bit x86_64 is only supported for ELF"));
12269 default_arch
= "i386";
12272 case OPTION_DIVIDE
:
12273 #ifdef SVR4_COMMENT_CHARS
12278 n
= XNEWVEC (char, strlen (i386_comment_chars
) + 1);
12280 for (s
= i386_comment_chars
; *s
!= '\0'; s
++)
12284 i386_comment_chars
= n
;
12290 saved
= xstrdup (arg
);
12292 /* Allow -march=+nosse. */
12298 as_fatal (_("invalid -march= option: `%s'"), arg
);
12299 next
= strchr (arch
, '+');
12302 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
12304 if (strcmp (arch
, cpu_arch
[j
].name
) == 0)
12307 if (! cpu_arch
[j
].flags
.bitfield
.cpui386
)
12310 cpu_arch_name
= cpu_arch
[j
].name
;
12311 cpu_sub_arch_name
= NULL
;
12312 cpu_arch_flags
= cpu_arch
[j
].flags
;
12313 cpu_arch_isa
= cpu_arch
[j
].type
;
12314 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
12315 if (!cpu_arch_tune_set
)
12317 cpu_arch_tune
= cpu_arch_isa
;
12318 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
12322 else if (*cpu_arch
[j
].name
== '.'
12323 && strcmp (arch
, cpu_arch
[j
].name
+ 1) == 0)
12325 /* ISA extension. */
12326 i386_cpu_flags flags
;
12328 flags
= cpu_flags_or (cpu_arch_flags
,
12329 cpu_arch
[j
].flags
);
12331 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
12333 if (cpu_sub_arch_name
)
12335 char *name
= cpu_sub_arch_name
;
12336 cpu_sub_arch_name
= concat (name
,
12338 (const char *) NULL
);
12342 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
12343 cpu_arch_flags
= flags
;
12344 cpu_arch_isa_flags
= flags
;
12348 = cpu_flags_or (cpu_arch_isa_flags
,
12349 cpu_arch
[j
].flags
);
12354 if (j
>= ARRAY_SIZE (cpu_arch
))
12356 /* Disable an ISA extension. */
12357 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
12358 if (strcmp (arch
, cpu_noarch
[j
].name
) == 0)
12360 i386_cpu_flags flags
;
12362 flags
= cpu_flags_and_not (cpu_arch_flags
,
12363 cpu_noarch
[j
].flags
);
12364 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
12366 if (cpu_sub_arch_name
)
12368 char *name
= cpu_sub_arch_name
;
12369 cpu_sub_arch_name
= concat (arch
,
12370 (const char *) NULL
);
12374 cpu_sub_arch_name
= xstrdup (arch
);
12375 cpu_arch_flags
= flags
;
12376 cpu_arch_isa_flags
= flags
;
12381 if (j
>= ARRAY_SIZE (cpu_noarch
))
12382 j
= ARRAY_SIZE (cpu_arch
);
12385 if (j
>= ARRAY_SIZE (cpu_arch
))
12386 as_fatal (_("invalid -march= option: `%s'"), arg
);
12390 while (next
!= NULL
);
12396 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
12397 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
12399 if (strcmp (arg
, cpu_arch
[j
].name
) == 0)
12401 cpu_arch_tune_set
= 1;
12402 cpu_arch_tune
= cpu_arch
[j
].type
;
12403 cpu_arch_tune_flags
= cpu_arch
[j
].flags
;
12407 if (j
>= ARRAY_SIZE (cpu_arch
))
12408 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
12411 case OPTION_MMNEMONIC
:
12412 if (strcasecmp (arg
, "att") == 0)
12413 intel_mnemonic
= 0;
12414 else if (strcasecmp (arg
, "intel") == 0)
12415 intel_mnemonic
= 1;
12417 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg
);
12420 case OPTION_MSYNTAX
:
12421 if (strcasecmp (arg
, "att") == 0)
12423 else if (strcasecmp (arg
, "intel") == 0)
12426 as_fatal (_("invalid -msyntax= option: `%s'"), arg
);
12429 case OPTION_MINDEX_REG
:
12430 allow_index_reg
= 1;
12433 case OPTION_MNAKED_REG
:
12434 allow_naked_reg
= 1;
12437 case OPTION_MSSE2AVX
:
12441 case OPTION_MSSE_CHECK
:
12442 if (strcasecmp (arg
, "error") == 0)
12443 sse_check
= check_error
;
12444 else if (strcasecmp (arg
, "warning") == 0)
12445 sse_check
= check_warning
;
12446 else if (strcasecmp (arg
, "none") == 0)
12447 sse_check
= check_none
;
12449 as_fatal (_("invalid -msse-check= option: `%s'"), arg
);
12452 case OPTION_MOPERAND_CHECK
:
12453 if (strcasecmp (arg
, "error") == 0)
12454 operand_check
= check_error
;
12455 else if (strcasecmp (arg
, "warning") == 0)
12456 operand_check
= check_warning
;
12457 else if (strcasecmp (arg
, "none") == 0)
12458 operand_check
= check_none
;
12460 as_fatal (_("invalid -moperand-check= option: `%s'"), arg
);
12463 case OPTION_MAVXSCALAR
:
12464 if (strcasecmp (arg
, "128") == 0)
12465 avxscalar
= vex128
;
12466 else if (strcasecmp (arg
, "256") == 0)
12467 avxscalar
= vex256
;
12469 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg
);
12472 case OPTION_MVEXWIG
:
12473 if (strcmp (arg
, "0") == 0)
12475 else if (strcmp (arg
, "1") == 0)
12478 as_fatal (_("invalid -mvexwig= option: `%s'"), arg
);
12481 case OPTION_MADD_BND_PREFIX
:
12482 add_bnd_prefix
= 1;
12485 case OPTION_MEVEXLIG
:
12486 if (strcmp (arg
, "128") == 0)
12487 evexlig
= evexl128
;
12488 else if (strcmp (arg
, "256") == 0)
12489 evexlig
= evexl256
;
12490 else if (strcmp (arg
, "512") == 0)
12491 evexlig
= evexl512
;
12493 as_fatal (_("invalid -mevexlig= option: `%s'"), arg
);
12496 case OPTION_MEVEXRCIG
:
12497 if (strcmp (arg
, "rne") == 0)
12499 else if (strcmp (arg
, "rd") == 0)
12501 else if (strcmp (arg
, "ru") == 0)
12503 else if (strcmp (arg
, "rz") == 0)
12506 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg
);
12509 case OPTION_MEVEXWIG
:
12510 if (strcmp (arg
, "0") == 0)
12512 else if (strcmp (arg
, "1") == 0)
12515 as_fatal (_("invalid -mevexwig= option: `%s'"), arg
);
12518 # if defined (TE_PE) || defined (TE_PEP)
12519 case OPTION_MBIG_OBJ
:
12524 case OPTION_MOMIT_LOCK_PREFIX
:
12525 if (strcasecmp (arg
, "yes") == 0)
12526 omit_lock_prefix
= 1;
12527 else if (strcasecmp (arg
, "no") == 0)
12528 omit_lock_prefix
= 0;
12530 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg
);
12533 case OPTION_MFENCE_AS_LOCK_ADD
:
12534 if (strcasecmp (arg
, "yes") == 0)
12536 else if (strcasecmp (arg
, "no") == 0)
12539 as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg
);
12542 case OPTION_MRELAX_RELOCATIONS
:
12543 if (strcasecmp (arg
, "yes") == 0)
12544 generate_relax_relocations
= 1;
12545 else if (strcasecmp (arg
, "no") == 0)
12546 generate_relax_relocations
= 0;
12548 as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg
);
12551 case OPTION_MALIGN_BRANCH_BOUNDARY
:
12554 long int align
= strtoul (arg
, &end
, 0);
12559 align_branch_power
= 0;
12562 else if (align
>= 16)
12565 for (align_power
= 0;
12567 align
>>= 1, align_power
++)
12569 /* Limit alignment power to 31. */
12570 if (align
== 1 && align_power
< 32)
12572 align_branch_power
= align_power
;
12577 as_fatal (_("invalid -malign-branch-boundary= value: %s"), arg
);
12581 case OPTION_MALIGN_BRANCH_PREFIX_SIZE
:
12584 int align
= strtoul (arg
, &end
, 0);
12585 /* Some processors only support 5 prefixes. */
12586 if (*end
== '\0' && align
>= 0 && align
< 6)
12588 align_branch_prefix_size
= align
;
12591 as_fatal (_("invalid -malign-branch-prefix-size= value: %s"),
12596 case OPTION_MALIGN_BRANCH
:
12598 saved
= xstrdup (arg
);
12602 next
= strchr (type
, '+');
12605 if (strcasecmp (type
, "jcc") == 0)
12606 align_branch
|= align_branch_jcc_bit
;
12607 else if (strcasecmp (type
, "fused") == 0)
12608 align_branch
|= align_branch_fused_bit
;
12609 else if (strcasecmp (type
, "jmp") == 0)
12610 align_branch
|= align_branch_jmp_bit
;
12611 else if (strcasecmp (type
, "call") == 0)
12612 align_branch
|= align_branch_call_bit
;
12613 else if (strcasecmp (type
, "ret") == 0)
12614 align_branch
|= align_branch_ret_bit
;
12615 else if (strcasecmp (type
, "indirect") == 0)
12616 align_branch
|= align_branch_indirect_bit
;
12618 as_fatal (_("invalid -malign-branch= option: `%s'"), arg
);
12621 while (next
!= NULL
);
12625 case OPTION_MBRANCHES_WITH_32B_BOUNDARIES
:
12626 align_branch_power
= 5;
12627 align_branch_prefix_size
= 5;
12628 align_branch
= (align_branch_jcc_bit
12629 | align_branch_fused_bit
12630 | align_branch_jmp_bit
);
12633 case OPTION_MAMD64
:
12637 case OPTION_MINTEL64
:
12645 /* Turn off -Os. */
12646 optimize_for_space
= 0;
12648 else if (*arg
== 's')
12650 optimize_for_space
= 1;
12651 /* Turn on all encoding optimizations. */
12652 optimize
= INT_MAX
;
12656 optimize
= atoi (arg
);
12657 /* Turn off -Os. */
12658 optimize_for_space
= 0;
12668 #define MESSAGE_TEMPLATE \
12672 output_message (FILE *stream
, char *p
, char *message
, char *start
,
12673 int *left_p
, const char *name
, int len
)
12675 int size
= sizeof (MESSAGE_TEMPLATE
);
12676 int left
= *left_p
;
12678 /* Reserve 2 spaces for ", " or ",\0" */
12681 /* Check if there is any room. */
12689 p
= mempcpy (p
, name
, len
);
12693 /* Output the current message now and start a new one. */
12696 fprintf (stream
, "%s\n", message
);
12698 left
= size
- (start
- message
) - len
- 2;
12700 gas_assert (left
>= 0);
12702 p
= mempcpy (p
, name
, len
);
12710 show_arch (FILE *stream
, int ext
, int check
)
12712 static char message
[] = MESSAGE_TEMPLATE
;
12713 char *start
= message
+ 27;
12715 int size
= sizeof (MESSAGE_TEMPLATE
);
12722 left
= size
- (start
- message
);
12723 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
12725 /* Should it be skipped? */
12726 if (cpu_arch
[j
].skip
)
12729 name
= cpu_arch
[j
].name
;
12730 len
= cpu_arch
[j
].len
;
12733 /* It is an extension. Skip if we aren't asked to show it. */
12744 /* It is an processor. Skip if we show only extension. */
12747 else if (check
&& ! cpu_arch
[j
].flags
.bitfield
.cpui386
)
12749 /* It is an impossible processor - skip. */
12753 p
= output_message (stream
, p
, message
, start
, &left
, name
, len
);
12756 /* Display disabled extensions. */
12758 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
12760 name
= cpu_noarch
[j
].name
;
12761 len
= cpu_noarch
[j
].len
;
12762 p
= output_message (stream
, p
, message
, start
, &left
, name
,
12767 fprintf (stream
, "%s\n", message
);
12771 md_show_usage (FILE *stream
)
12773 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12774 fprintf (stream
, _("\
12775 -Qy, -Qn ignored\n\
12776 -V print assembler version number\n\
12779 fprintf (stream
, _("\
12780 -n Do not optimize code alignment\n\
12781 -q quieten some warnings\n"));
12782 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12783 fprintf (stream
, _("\
12786 #if defined BFD64 && (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
12787 || defined (TE_PE) || defined (TE_PEP))
12788 fprintf (stream
, _("\
12789 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
12791 #ifdef SVR4_COMMENT_CHARS
12792 fprintf (stream
, _("\
12793 --divide do not treat `/' as a comment character\n"));
12795 fprintf (stream
, _("\
12796 --divide ignored\n"));
12798 fprintf (stream
, _("\
12799 -march=CPU[,+EXTENSION...]\n\
12800 generate code for CPU and EXTENSION, CPU is one of:\n"));
12801 show_arch (stream
, 0, 1);
12802 fprintf (stream
, _("\
12803 EXTENSION is combination of:\n"));
12804 show_arch (stream
, 1, 0);
12805 fprintf (stream
, _("\
12806 -mtune=CPU optimize for CPU, CPU is one of:\n"));
12807 show_arch (stream
, 0, 0);
12808 fprintf (stream
, _("\
12809 -msse2avx encode SSE instructions with VEX prefix\n"));
12810 fprintf (stream
, _("\
12811 -msse-check=[none|error|warning] (default: warning)\n\
12812 check SSE instructions\n"));
12813 fprintf (stream
, _("\
12814 -moperand-check=[none|error|warning] (default: warning)\n\
12815 check operand combinations for validity\n"));
12816 fprintf (stream
, _("\
12817 -mavxscalar=[128|256] (default: 128)\n\
12818 encode scalar AVX instructions with specific vector\n\
12820 fprintf (stream
, _("\
12821 -mvexwig=[0|1] (default: 0)\n\
12822 encode VEX instructions with specific VEX.W value\n\
12823 for VEX.W bit ignored instructions\n"));
12824 fprintf (stream
, _("\
12825 -mevexlig=[128|256|512] (default: 128)\n\
12826 encode scalar EVEX instructions with specific vector\n\
12828 fprintf (stream
, _("\
12829 -mevexwig=[0|1] (default: 0)\n\
12830 encode EVEX instructions with specific EVEX.W value\n\
12831 for EVEX.W bit ignored instructions\n"));
12832 fprintf (stream
, _("\
12833 -mevexrcig=[rne|rd|ru|rz] (default: rne)\n\
12834 encode EVEX instructions with specific EVEX.RC value\n\
12835 for SAE-only ignored instructions\n"));
12836 fprintf (stream
, _("\
12837 -mmnemonic=[att|intel] "));
12838 if (SYSV386_COMPAT
)
12839 fprintf (stream
, _("(default: att)\n"));
12841 fprintf (stream
, _("(default: intel)\n"));
12842 fprintf (stream
, _("\
12843 use AT&T/Intel mnemonic\n"));
12844 fprintf (stream
, _("\
12845 -msyntax=[att|intel] (default: att)\n\
12846 use AT&T/Intel syntax\n"));
12847 fprintf (stream
, _("\
12848 -mindex-reg support pseudo index registers\n"));
12849 fprintf (stream
, _("\
12850 -mnaked-reg don't require `%%' prefix for registers\n"));
12851 fprintf (stream
, _("\
12852 -madd-bnd-prefix add BND prefix for all valid branches\n"));
12853 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12854 fprintf (stream
, _("\
12855 -mshared disable branch optimization for shared code\n"));
12856 fprintf (stream
, _("\
12857 -mx86-used-note=[no|yes] "));
12858 if (DEFAULT_X86_USED_NOTE
)
12859 fprintf (stream
, _("(default: yes)\n"));
12861 fprintf (stream
, _("(default: no)\n"));
12862 fprintf (stream
, _("\
12863 generate x86 used ISA and feature properties\n"));
12865 #if defined (TE_PE) || defined (TE_PEP)
12866 fprintf (stream
, _("\
12867 -mbig-obj generate big object files\n"));
12869 fprintf (stream
, _("\
12870 -momit-lock-prefix=[no|yes] (default: no)\n\
12871 strip all lock prefixes\n"));
12872 fprintf (stream
, _("\
12873 -mfence-as-lock-add=[no|yes] (default: no)\n\
12874 encode lfence, mfence and sfence as\n\
12875 lock addl $0x0, (%%{re}sp)\n"));
12876 fprintf (stream
, _("\
12877 -mrelax-relocations=[no|yes] "));
12878 if (DEFAULT_GENERATE_X86_RELAX_RELOCATIONS
)
12879 fprintf (stream
, _("(default: yes)\n"));
12881 fprintf (stream
, _("(default: no)\n"));
12882 fprintf (stream
, _("\
12883 generate relax relocations\n"));
12884 fprintf (stream
, _("\
12885 -malign-branch-boundary=NUM (default: 0)\n\
12886 align branches within NUM byte boundary\n"));
12887 fprintf (stream
, _("\
12888 -malign-branch=TYPE[+TYPE...] (default: jcc+fused+jmp)\n\
12889 TYPE is combination of jcc, fused, jmp, call, ret,\n\
12891 specify types of branches to align\n"));
12892 fprintf (stream
, _("\
12893 -malign-branch-prefix-size=NUM (default: 5)\n\
12894 align branches with NUM prefixes per instruction\n"));
12895 fprintf (stream
, _("\
12896 -mbranches-within-32B-boundaries\n\
12897 align branches within 32 byte boundary\n"));
12898 fprintf (stream
, _("\
12899 -mamd64 accept only AMD64 ISA [default]\n"));
12900 fprintf (stream
, _("\
12901 -mintel64 accept only Intel64 ISA\n"));
12904 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
12905 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
12906 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
12908 /* Pick the target format to use. */
12911 i386_target_format (void)
12913 if (!strncmp (default_arch
, "x86_64", 6))
12915 update_code_flag (CODE_64BIT
, 1);
12916 if (default_arch
[6] == '\0')
12917 x86_elf_abi
= X86_64_ABI
;
12919 x86_elf_abi
= X86_64_X32_ABI
;
12921 else if (!strcmp (default_arch
, "i386"))
12922 update_code_flag (CODE_32BIT
, 1);
12923 else if (!strcmp (default_arch
, "iamcu"))
12925 update_code_flag (CODE_32BIT
, 1);
12926 if (cpu_arch_isa
== PROCESSOR_UNKNOWN
)
12928 static const i386_cpu_flags iamcu_flags
= CPU_IAMCU_FLAGS
;
12929 cpu_arch_name
= "iamcu";
12930 cpu_sub_arch_name
= NULL
;
12931 cpu_arch_flags
= iamcu_flags
;
12932 cpu_arch_isa
= PROCESSOR_IAMCU
;
12933 cpu_arch_isa_flags
= iamcu_flags
;
12934 if (!cpu_arch_tune_set
)
12936 cpu_arch_tune
= cpu_arch_isa
;
12937 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
12940 else if (cpu_arch_isa
!= PROCESSOR_IAMCU
)
12941 as_fatal (_("Intel MCU doesn't support `%s' architecture"),
12945 as_fatal (_("unknown architecture"));
12947 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
12948 cpu_arch_isa_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
12949 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
12950 cpu_arch_tune_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
12952 switch (OUTPUT_FLAVOR
)
12954 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
12955 case bfd_target_aout_flavour
:
12956 return AOUT_TARGET_FORMAT
;
12958 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
12959 # if defined (TE_PE) || defined (TE_PEP)
12960 case bfd_target_coff_flavour
:
12961 if (flag_code
== CODE_64BIT
)
12962 return use_big_obj
? "pe-bigobj-x86-64" : "pe-x86-64";
12965 # elif defined (TE_GO32)
12966 case bfd_target_coff_flavour
:
12967 return "coff-go32";
12969 case bfd_target_coff_flavour
:
12970 return "coff-i386";
12973 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
12974 case bfd_target_elf_flavour
:
12976 const char *format
;
12978 switch (x86_elf_abi
)
12981 format
= ELF_TARGET_FORMAT
;
12983 tls_get_addr
= "___tls_get_addr";
12987 use_rela_relocations
= 1;
12990 tls_get_addr
= "__tls_get_addr";
12992 format
= ELF_TARGET_FORMAT64
;
12994 case X86_64_X32_ABI
:
12995 use_rela_relocations
= 1;
12998 tls_get_addr
= "__tls_get_addr";
13000 disallow_64bit_reloc
= 1;
13001 format
= ELF_TARGET_FORMAT32
;
13004 if (cpu_arch_isa
== PROCESSOR_L1OM
)
13006 if (x86_elf_abi
!= X86_64_ABI
)
13007 as_fatal (_("Intel L1OM is 64bit only"));
13008 return ELF_TARGET_L1OM_FORMAT
;
13010 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
13012 if (x86_elf_abi
!= X86_64_ABI
)
13013 as_fatal (_("Intel K1OM is 64bit only"));
13014 return ELF_TARGET_K1OM_FORMAT
;
13016 else if (cpu_arch_isa
== PROCESSOR_IAMCU
)
13018 if (x86_elf_abi
!= I386_ABI
)
13019 as_fatal (_("Intel MCU is 32bit only"));
13020 return ELF_TARGET_IAMCU_FORMAT
;
13026 #if defined (OBJ_MACH_O)
13027 case bfd_target_mach_o_flavour
:
13028 if (flag_code
== CODE_64BIT
)
13030 use_rela_relocations
= 1;
13032 return "mach-o-x86-64";
13035 return "mach-o-i386";
13043 #endif /* OBJ_MAYBE_ more than one */
13046 md_undefined_symbol (char *name
)
13048 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
13049 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
13050 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
13051 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
13055 if (symbol_find (name
))
13056 as_bad (_("GOT already in symbol table"));
13057 GOT_symbol
= symbol_new (name
, undefined_section
,
13058 (valueT
) 0, &zero_address_frag
);
13065 /* Round up a section size to the appropriate boundary. */
13068 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
13070 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
13071 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
13073 /* For a.out, force the section size to be aligned. If we don't do
13074 this, BFD will align it for us, but it will not write out the
13075 final bytes of the section. This may be a bug in BFD, but it is
13076 easier to fix it here since that is how the other a.out targets
13080 align
= bfd_section_alignment (segment
);
13081 size
= ((size
+ (1 << align
) - 1) & (-((valueT
) 1 << align
)));
13088 /* On the i386, PC-relative offsets are relative to the start of the
13089 next instruction. That is, the address of the offset, plus its
13090 size, since the offset is always the last part of the insn. */
13093 md_pcrel_from (fixS
*fixP
)
13095 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
13101 s_bss (int ignore ATTRIBUTE_UNUSED
)
13105 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13107 obj_elf_section_change_hook ();
13109 temp
= get_absolute_expression ();
13110 subseg_set (bss_section
, (subsegT
) temp
);
13111 demand_empty_rest_of_line ();
13116 /* Remember constant directive. */
13119 i386_cons_align (int ignore ATTRIBUTE_UNUSED
)
13121 if (last_insn
.kind
!= last_insn_directive
13122 && (bfd_section_flags (now_seg
) & SEC_CODE
))
13124 last_insn
.seg
= now_seg
;
13125 last_insn
.kind
= last_insn_directive
;
13126 last_insn
.name
= "constant directive";
13127 last_insn
.file
= as_where (&last_insn
.line
);
13132 i386_validate_fix (fixS
*fixp
)
13134 if (fixp
->fx_subsy
)
13136 if (fixp
->fx_subsy
== GOT_symbol
)
13138 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
13142 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13143 if (fixp
->fx_tcbit2
)
13144 fixp
->fx_r_type
= (fixp
->fx_tcbit
13145 ? BFD_RELOC_X86_64_REX_GOTPCRELX
13146 : BFD_RELOC_X86_64_GOTPCRELX
);
13149 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
13154 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
13156 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
13158 fixp
->fx_subsy
= 0;
13161 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13162 else if (!object_64bit
)
13164 if (fixp
->fx_r_type
== BFD_RELOC_386_GOT32
13165 && fixp
->fx_tcbit2
)
13166 fixp
->fx_r_type
= BFD_RELOC_386_GOT32X
;
13172 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
13175 bfd_reloc_code_real_type code
;
13177 switch (fixp
->fx_r_type
)
13179 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13180 case BFD_RELOC_SIZE32
:
13181 case BFD_RELOC_SIZE64
:
13182 if (S_IS_DEFINED (fixp
->fx_addsy
)
13183 && !S_IS_EXTERNAL (fixp
->fx_addsy
))
13185 /* Resolve size relocation against local symbol to size of
13186 the symbol plus addend. */
13187 valueT value
= S_GET_SIZE (fixp
->fx_addsy
) + fixp
->fx_offset
;
13188 if (fixp
->fx_r_type
== BFD_RELOC_SIZE32
13189 && !fits_in_unsigned_long (value
))
13190 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
13191 _("symbol size computation overflow"));
13192 fixp
->fx_addsy
= NULL
;
13193 fixp
->fx_subsy
= NULL
;
13194 md_apply_fix (fixp
, (valueT
*) &value
, NULL
);
13198 /* Fall through. */
13200 case BFD_RELOC_X86_64_PLT32
:
13201 case BFD_RELOC_X86_64_GOT32
:
13202 case BFD_RELOC_X86_64_GOTPCREL
:
13203 case BFD_RELOC_X86_64_GOTPCRELX
:
13204 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
13205 case BFD_RELOC_386_PLT32
:
13206 case BFD_RELOC_386_GOT32
:
13207 case BFD_RELOC_386_GOT32X
:
13208 case BFD_RELOC_386_GOTOFF
:
13209 case BFD_RELOC_386_GOTPC
:
13210 case BFD_RELOC_386_TLS_GD
:
13211 case BFD_RELOC_386_TLS_LDM
:
13212 case BFD_RELOC_386_TLS_LDO_32
:
13213 case BFD_RELOC_386_TLS_IE_32
:
13214 case BFD_RELOC_386_TLS_IE
:
13215 case BFD_RELOC_386_TLS_GOTIE
:
13216 case BFD_RELOC_386_TLS_LE_32
:
13217 case BFD_RELOC_386_TLS_LE
:
13218 case BFD_RELOC_386_TLS_GOTDESC
:
13219 case BFD_RELOC_386_TLS_DESC_CALL
:
13220 case BFD_RELOC_X86_64_TLSGD
:
13221 case BFD_RELOC_X86_64_TLSLD
:
13222 case BFD_RELOC_X86_64_DTPOFF32
:
13223 case BFD_RELOC_X86_64_DTPOFF64
:
13224 case BFD_RELOC_X86_64_GOTTPOFF
:
13225 case BFD_RELOC_X86_64_TPOFF32
:
13226 case BFD_RELOC_X86_64_TPOFF64
:
13227 case BFD_RELOC_X86_64_GOTOFF64
:
13228 case BFD_RELOC_X86_64_GOTPC32
:
13229 case BFD_RELOC_X86_64_GOT64
:
13230 case BFD_RELOC_X86_64_GOTPCREL64
:
13231 case BFD_RELOC_X86_64_GOTPC64
:
13232 case BFD_RELOC_X86_64_GOTPLT64
:
13233 case BFD_RELOC_X86_64_PLTOFF64
:
13234 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
13235 case BFD_RELOC_X86_64_TLSDESC_CALL
:
13236 case BFD_RELOC_RVA
:
13237 case BFD_RELOC_VTABLE_ENTRY
:
13238 case BFD_RELOC_VTABLE_INHERIT
:
13240 case BFD_RELOC_32_SECREL
:
13242 code
= fixp
->fx_r_type
;
13244 case BFD_RELOC_X86_64_32S
:
13245 if (!fixp
->fx_pcrel
)
13247 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
13248 code
= fixp
->fx_r_type
;
13251 /* Fall through. */
13253 if (fixp
->fx_pcrel
)
13255 switch (fixp
->fx_size
)
13258 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
13259 _("can not do %d byte pc-relative relocation"),
13261 code
= BFD_RELOC_32_PCREL
;
13263 case 1: code
= BFD_RELOC_8_PCREL
; break;
13264 case 2: code
= BFD_RELOC_16_PCREL
; break;
13265 case 4: code
= BFD_RELOC_32_PCREL
; break;
13267 case 8: code
= BFD_RELOC_64_PCREL
; break;
13273 switch (fixp
->fx_size
)
13276 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
13277 _("can not do %d byte relocation"),
13279 code
= BFD_RELOC_32
;
13281 case 1: code
= BFD_RELOC_8
; break;
13282 case 2: code
= BFD_RELOC_16
; break;
13283 case 4: code
= BFD_RELOC_32
; break;
13285 case 8: code
= BFD_RELOC_64
; break;
13292 if ((code
== BFD_RELOC_32
13293 || code
== BFD_RELOC_32_PCREL
13294 || code
== BFD_RELOC_X86_64_32S
)
13296 && fixp
->fx_addsy
== GOT_symbol
)
13299 code
= BFD_RELOC_386_GOTPC
;
13301 code
= BFD_RELOC_X86_64_GOTPC32
;
13303 if ((code
== BFD_RELOC_64
|| code
== BFD_RELOC_64_PCREL
)
13305 && fixp
->fx_addsy
== GOT_symbol
)
13307 code
= BFD_RELOC_X86_64_GOTPC64
;
13310 rel
= XNEW (arelent
);
13311 rel
->sym_ptr_ptr
= XNEW (asymbol
*);
13312 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
13314 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
13316 if (!use_rela_relocations
)
13318 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
13319 vtable entry to be used in the relocation's section offset. */
13320 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
13321 rel
->address
= fixp
->fx_offset
;
13322 #if defined (OBJ_COFF) && defined (TE_PE)
13323 else if (fixp
->fx_addsy
&& S_IS_WEAK (fixp
->fx_addsy
))
13324 rel
->addend
= fixp
->fx_addnumber
- (S_GET_VALUE (fixp
->fx_addsy
) * 2);
13329 /* Use the rela in 64bit mode. */
13332 if (disallow_64bit_reloc
)
13335 case BFD_RELOC_X86_64_DTPOFF64
:
13336 case BFD_RELOC_X86_64_TPOFF64
:
13337 case BFD_RELOC_64_PCREL
:
13338 case BFD_RELOC_X86_64_GOTOFF64
:
13339 case BFD_RELOC_X86_64_GOT64
:
13340 case BFD_RELOC_X86_64_GOTPCREL64
:
13341 case BFD_RELOC_X86_64_GOTPC64
:
13342 case BFD_RELOC_X86_64_GOTPLT64
:
13343 case BFD_RELOC_X86_64_PLTOFF64
:
13344 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
13345 _("cannot represent relocation type %s in x32 mode"),
13346 bfd_get_reloc_code_name (code
));
13352 if (!fixp
->fx_pcrel
)
13353 rel
->addend
= fixp
->fx_offset
;
13357 case BFD_RELOC_X86_64_PLT32
:
13358 case BFD_RELOC_X86_64_GOT32
:
13359 case BFD_RELOC_X86_64_GOTPCREL
:
13360 case BFD_RELOC_X86_64_GOTPCRELX
:
13361 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
13362 case BFD_RELOC_X86_64_TLSGD
:
13363 case BFD_RELOC_X86_64_TLSLD
:
13364 case BFD_RELOC_X86_64_GOTTPOFF
:
13365 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
13366 case BFD_RELOC_X86_64_TLSDESC_CALL
:
13367 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
13370 rel
->addend
= (section
->vma
13372 + fixp
->fx_addnumber
13373 + md_pcrel_from (fixp
));
13378 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
13379 if (rel
->howto
== NULL
)
13381 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
13382 _("cannot represent relocation type %s"),
13383 bfd_get_reloc_code_name (code
));
13384 /* Set howto to a garbage value so that we can keep going. */
13385 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
13386 gas_assert (rel
->howto
!= NULL
);
13392 #include "tc-i386-intel.c"
13395 tc_x86_parse_to_dw2regnum (expressionS
*exp
)
13397 int saved_naked_reg
;
13398 char saved_register_dot
;
13400 saved_naked_reg
= allow_naked_reg
;
13401 allow_naked_reg
= 1;
13402 saved_register_dot
= register_chars
['.'];
13403 register_chars
['.'] = '.';
13404 allow_pseudo_reg
= 1;
13405 expression_and_evaluate (exp
);
13406 allow_pseudo_reg
= 0;
13407 register_chars
['.'] = saved_register_dot
;
13408 allow_naked_reg
= saved_naked_reg
;
13410 if (exp
->X_op
== O_register
&& exp
->X_add_number
>= 0)
13412 if ((addressT
) exp
->X_add_number
< i386_regtab_size
)
13414 exp
->X_op
= O_constant
;
13415 exp
->X_add_number
= i386_regtab
[exp
->X_add_number
]
13416 .dw2_regnum
[flag_code
>> 1];
13419 exp
->X_op
= O_illegal
;
13424 tc_x86_frame_initial_instructions (void)
13426 static unsigned int sp_regno
[2];
13428 if (!sp_regno
[flag_code
>> 1])
13430 char *saved_input
= input_line_pointer
;
13431 char sp
[][4] = {"esp", "rsp"};
13434 input_line_pointer
= sp
[flag_code
>> 1];
13435 tc_x86_parse_to_dw2regnum (&exp
);
13436 gas_assert (exp
.X_op
== O_constant
);
13437 sp_regno
[flag_code
>> 1] = exp
.X_add_number
;
13438 input_line_pointer
= saved_input
;
13441 cfi_add_CFA_def_cfa (sp_regno
[flag_code
>> 1], -x86_cie_data_alignment
);
13442 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
13446 x86_dwarf2_addr_size (void)
13448 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
13449 if (x86_elf_abi
== X86_64_X32_ABI
)
13452 return bfd_arch_bits_per_address (stdoutput
) / 8;
13456 i386_elf_section_type (const char *str
, size_t len
)
13458 if (flag_code
== CODE_64BIT
13459 && len
== sizeof ("unwind") - 1
13460 && strncmp (str
, "unwind", 6) == 0)
13461 return SHT_X86_64_UNWIND
;
13468 i386_solaris_fix_up_eh_frame (segT sec
)
13470 if (flag_code
== CODE_64BIT
)
13471 elf_section_type (sec
) = SHT_X86_64_UNWIND
;
13477 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
13481 exp
.X_op
= O_secrel
;
13482 exp
.X_add_symbol
= symbol
;
13483 exp
.X_add_number
= 0;
13484 emit_expr (&exp
, size
);
13488 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13489 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
13492 x86_64_section_letter (int letter
, const char **ptr_msg
)
13494 if (flag_code
== CODE_64BIT
)
13497 return SHF_X86_64_LARGE
;
13499 *ptr_msg
= _("bad .section directive: want a,l,w,x,M,S,G,T in string");
13502 *ptr_msg
= _("bad .section directive: want a,w,x,M,S,G,T in string");
13507 x86_64_section_word (char *str
, size_t len
)
13509 if (len
== 5 && flag_code
== CODE_64BIT
&& CONST_STRNEQ (str
, "large"))
13510 return SHF_X86_64_LARGE
;
13516 handle_large_common (int small ATTRIBUTE_UNUSED
)
13518 if (flag_code
!= CODE_64BIT
)
13520 s_comm_internal (0, elf_common_parse
);
13521 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
13525 static segT lbss_section
;
13526 asection
*saved_com_section_ptr
= elf_com_section_ptr
;
13527 asection
*saved_bss_section
= bss_section
;
13529 if (lbss_section
== NULL
)
13531 flagword applicable
;
13532 segT seg
= now_seg
;
13533 subsegT subseg
= now_subseg
;
13535 /* The .lbss section is for local .largecomm symbols. */
13536 lbss_section
= subseg_new (".lbss", 0);
13537 applicable
= bfd_applicable_section_flags (stdoutput
);
13538 bfd_set_section_flags (lbss_section
, applicable
& SEC_ALLOC
);
13539 seg_info (lbss_section
)->bss
= 1;
13541 subseg_set (seg
, subseg
);
13544 elf_com_section_ptr
= &_bfd_elf_large_com_section
;
13545 bss_section
= lbss_section
;
13547 s_comm_internal (0, elf_common_parse
);
13549 elf_com_section_ptr
= saved_com_section_ptr
;
13550 bss_section
= saved_bss_section
;
13553 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */