1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright (C) 1989-2019 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 /* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
23 x86_64 support by Jan Hubicka (jh@suse.cz)
24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
29 #include "safe-ctype.h"
31 #include "dwarf2dbg.h"
32 #include "dw2gencfi.h"
33 #include "elf/x86-64.h"
34 #include "opcodes/i386-init.h"
39 #ifdef HAVE_SYS_PARAM_H
40 #include <sys/param.h>
43 #define INT_MAX (int) (((unsigned) (-1)) >> 1)
47 #ifndef REGISTER_WARNINGS
48 #define REGISTER_WARNINGS 1
51 #ifndef INFER_ADDR_PREFIX
52 #define INFER_ADDR_PREFIX 1
56 #define DEFAULT_ARCH "i386"
61 #define INLINE __inline__
67 /* Prefixes will be emitted in the order defined below.
68 WAIT_PREFIX must be the first prefix since FWAIT is really is an
69 instruction, and so must come before any prefixes.
70 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
71 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
77 #define HLE_PREFIX REP_PREFIX
78 #define BND_PREFIX REP_PREFIX
80 #define REX_PREFIX 6 /* must come last. */
81 #define MAX_PREFIXES 7 /* max prefixes per opcode */
83 /* we define the syntax here (modulo base,index,scale syntax) */
84 #define REGISTER_PREFIX '%'
85 #define IMMEDIATE_PREFIX '$'
86 #define ABSOLUTE_PREFIX '*'
88 /* these are the instruction mnemonic suffixes in AT&T syntax or
89 memory operand size in Intel syntax. */
90 #define WORD_MNEM_SUFFIX 'w'
91 #define BYTE_MNEM_SUFFIX 'b'
92 #define SHORT_MNEM_SUFFIX 's'
93 #define LONG_MNEM_SUFFIX 'l'
94 #define QWORD_MNEM_SUFFIX 'q'
95 /* Intel Syntax. Use a non-ascii letter since since it never appears
97 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
99 #define END_OF_INSN '\0'
102 'templates' is for grouping together 'template' structures for opcodes
103 of the same name. This is only used for storing the insns in the grand
104 ole hash table of insns.
105 The templates themselves start at START and range up to (but not including)
110 const insn_template
*start
;
111 const insn_template
*end
;
115 /* 386 operand encoding bytes: see 386 book for details of this. */
118 unsigned int regmem
; /* codes register or memory operand */
119 unsigned int reg
; /* codes register operand (or extended opcode) */
120 unsigned int mode
; /* how to interpret regmem & reg */
124 /* x86-64 extension prefix. */
125 typedef int rex_byte
;
127 /* 386 opcode byte to code indirect addressing. */
136 /* x86 arch names, types and features */
139 const char *name
; /* arch name */
140 unsigned int len
; /* arch string length */
141 enum processor_type type
; /* arch type */
142 i386_cpu_flags flags
; /* cpu feature flags */
143 unsigned int skip
; /* show_arch should skip this. */
147 /* Used to turn off indicated flags. */
150 const char *name
; /* arch name */
151 unsigned int len
; /* arch string length */
152 i386_cpu_flags flags
; /* cpu feature flags */
156 static void update_code_flag (int, int);
157 static void set_code_flag (int);
158 static void set_16bit_gcc_code_flag (int);
159 static void set_intel_syntax (int);
160 static void set_intel_mnemonic (int);
161 static void set_allow_index_reg (int);
162 static void set_check (int);
163 static void set_cpu_arch (int);
165 static void pe_directive_secrel (int);
167 static void signed_cons (int);
168 static char *output_invalid (int c
);
169 static int i386_finalize_immediate (segT
, expressionS
*, i386_operand_type
,
171 static int i386_finalize_displacement (segT
, expressionS
*, i386_operand_type
,
173 static int i386_att_operand (char *);
174 static int i386_intel_operand (char *, int);
175 static int i386_intel_simplify (expressionS
*);
176 static int i386_intel_parse_name (const char *, expressionS
*);
177 static const reg_entry
*parse_register (char *, char **);
178 static char *parse_insn (char *, char *);
179 static char *parse_operands (char *, const char *);
180 static void swap_operands (void);
181 static void swap_2_operands (int, int);
182 static void optimize_imm (void);
183 static void optimize_disp (void);
184 static const insn_template
*match_template (char);
185 static int check_string (void);
186 static int process_suffix (void);
187 static int check_byte_reg (void);
188 static int check_long_reg (void);
189 static int check_qword_reg (void);
190 static int check_word_reg (void);
191 static int finalize_imm (void);
192 static int process_operands (void);
193 static const seg_entry
*build_modrm_byte (void);
194 static void output_insn (void);
195 static void output_imm (fragS
*, offsetT
);
196 static void output_disp (fragS
*, offsetT
);
198 static void s_bss (int);
200 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
201 static void handle_large_common (int small ATTRIBUTE_UNUSED
);
203 /* GNU_PROPERTY_X86_ISA_1_USED. */
204 static unsigned int x86_isa_1_used
;
205 /* GNU_PROPERTY_X86_FEATURE_2_USED. */
206 static unsigned int x86_feature_2_used
;
207 /* Generate x86 used ISA and feature properties. */
208 static unsigned int x86_used_note
= DEFAULT_X86_USED_NOTE
;
211 static const char *default_arch
= DEFAULT_ARCH
;
213 /* This struct describes rounding control and SAE in the instruction. */
227 static struct RC_Operation rc_op
;
229 /* The struct describes masking, applied to OPERAND in the instruction.
230 MASK is a pointer to the corresponding mask register. ZEROING tells
231 whether merging or zeroing mask is used. */
232 struct Mask_Operation
234 const reg_entry
*mask
;
235 unsigned int zeroing
;
236 /* The operand where this operation is associated. */
240 static struct Mask_Operation mask_op
;
242 /* The struct describes broadcasting, applied to OPERAND. FACTOR is
244 struct Broadcast_Operation
246 /* Type of broadcast: {1to2}, {1to4}, {1to8}, or {1to16}. */
249 /* Index of broadcasted operand. */
252 /* Number of bytes to broadcast. */
256 static struct Broadcast_Operation broadcast_op
;
261 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
262 unsigned char bytes
[4];
264 /* Destination or source register specifier. */
265 const reg_entry
*register_specifier
;
268 /* 'md_assemble ()' gathers together information and puts it into a
275 const reg_entry
*regs
;
280 operand_size_mismatch
,
281 operand_type_mismatch
,
282 register_type_mismatch
,
283 number_of_operands_mismatch
,
284 invalid_instruction_suffix
,
286 unsupported_with_intel_mnemonic
,
289 invalid_vsib_address
,
290 invalid_vector_register_set
,
291 unsupported_vector_index_register
,
292 unsupported_broadcast
,
295 mask_not_on_destination
,
298 rc_sae_operand_not_last_imm
,
299 invalid_register_operand
,
304 /* TM holds the template for the insn were currently assembling. */
307 /* SUFFIX holds the instruction size suffix for byte, word, dword
308 or qword, if given. */
311 /* OPERANDS gives the number of given operands. */
312 unsigned int operands
;
314 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
315 of given register, displacement, memory operands and immediate
317 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
319 /* TYPES [i] is the type (see above #defines) which tells us how to
320 use OP[i] for the corresponding operand. */
321 i386_operand_type types
[MAX_OPERANDS
];
323 /* Displacement expression, immediate expression, or register for each
325 union i386_op op
[MAX_OPERANDS
];
327 /* Flags for operands. */
328 unsigned int flags
[MAX_OPERANDS
];
329 #define Operand_PCrel 1
330 #define Operand_Mem 2
332 /* Relocation type for operand */
333 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
335 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
336 the base index byte below. */
337 const reg_entry
*base_reg
;
338 const reg_entry
*index_reg
;
339 unsigned int log2_scale_factor
;
341 /* SEG gives the seg_entries of this insn. They are zero unless
342 explicit segment overrides are given. */
343 const seg_entry
*seg
[2];
345 /* Copied first memory operand string, for re-checking. */
348 /* PREFIX holds all the given prefix opcodes (usually null).
349 PREFIXES is the number of prefix opcodes. */
350 unsigned int prefixes
;
351 unsigned char prefix
[MAX_PREFIXES
];
353 /* Has MMX register operands. */
354 bfd_boolean has_regmmx
;
356 /* Has XMM register operands. */
357 bfd_boolean has_regxmm
;
359 /* Has YMM register operands. */
360 bfd_boolean has_regymm
;
362 /* Has ZMM register operands. */
363 bfd_boolean has_regzmm
;
365 /* RM and SIB are the modrm byte and the sib byte where the
366 addressing modes of this insn are encoded. */
373 /* Masking attributes. */
374 struct Mask_Operation
*mask
;
376 /* Rounding control and SAE attributes. */
377 struct RC_Operation
*rounding
;
379 /* Broadcasting attributes. */
380 struct Broadcast_Operation
*broadcast
;
382 /* Compressed disp8*N attribute. */
383 unsigned int memshift
;
385 /* Prefer load or store in encoding. */
388 dir_encoding_default
= 0,
394 /* Prefer 8bit or 32bit displacement in encoding. */
397 disp_encoding_default
= 0,
402 /* Prefer the REX byte in encoding. */
403 bfd_boolean rex_encoding
;
405 /* Disable instruction size optimization. */
406 bfd_boolean no_optimize
;
408 /* How to encode vector instructions. */
411 vex_encoding_default
= 0,
418 const char *rep_prefix
;
421 const char *hle_prefix
;
423 /* Have BND prefix. */
424 const char *bnd_prefix
;
426 /* Have NOTRACK prefix. */
427 const char *notrack_prefix
;
430 enum i386_error error
;
433 typedef struct _i386_insn i386_insn
;
435 /* Link RC type with corresponding string, that'll be looked for in
444 static const struct RC_name RC_NamesTable
[] =
446 { rne
, STRING_COMMA_LEN ("rn-sae") },
447 { rd
, STRING_COMMA_LEN ("rd-sae") },
448 { ru
, STRING_COMMA_LEN ("ru-sae") },
449 { rz
, STRING_COMMA_LEN ("rz-sae") },
450 { saeonly
, STRING_COMMA_LEN ("sae") },
453 /* List of chars besides those in app.c:symbol_chars that can start an
454 operand. Used to prevent the scrubber eating vital white-space. */
455 const char extra_symbol_chars
[] = "*%-([{}"
464 #if (defined (TE_I386AIX) \
465 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
466 && !defined (TE_GNU) \
467 && !defined (TE_LINUX) \
468 && !defined (TE_NACL) \
469 && !defined (TE_FreeBSD) \
470 && !defined (TE_DragonFly) \
471 && !defined (TE_NetBSD)))
472 /* This array holds the chars that always start a comment. If the
473 pre-processor is disabled, these aren't very useful. The option
474 --divide will remove '/' from this list. */
475 const char *i386_comment_chars
= "#/";
476 #define SVR4_COMMENT_CHARS 1
477 #define PREFIX_SEPARATOR '\\'
480 const char *i386_comment_chars
= "#";
481 #define PREFIX_SEPARATOR '/'
484 /* This array holds the chars that only start a comment at the beginning of
485 a line. If the line seems to have the form '# 123 filename'
486 .line and .file directives will appear in the pre-processed output.
487 Note that input_file.c hand checks for '#' at the beginning of the
488 first line of the input file. This is because the compiler outputs
489 #NO_APP at the beginning of its output.
490 Also note that comments started like this one will always work if
491 '/' isn't otherwise defined. */
492 const char line_comment_chars
[] = "#/";
494 const char line_separator_chars
[] = ";";
496 /* Chars that can be used to separate mant from exp in floating point
498 const char EXP_CHARS
[] = "eE";
500 /* Chars that mean this number is a floating point constant
503 const char FLT_CHARS
[] = "fFdDxX";
505 /* Tables for lexical analysis. */
506 static char mnemonic_chars
[256];
507 static char register_chars
[256];
508 static char operand_chars
[256];
509 static char identifier_chars
[256];
510 static char digit_chars
[256];
512 /* Lexical macros. */
513 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
514 #define is_operand_char(x) (operand_chars[(unsigned char) x])
515 #define is_register_char(x) (register_chars[(unsigned char) x])
516 #define is_space_char(x) ((x) == ' ')
517 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
518 #define is_digit_char(x) (digit_chars[(unsigned char) x])
520 /* All non-digit non-letter characters that may occur in an operand. */
521 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
523 /* md_assemble() always leaves the strings it's passed unaltered. To
524 effect this we maintain a stack of saved characters that we've smashed
525 with '\0's (indicating end of strings for various sub-fields of the
526 assembler instruction). */
527 static char save_stack
[32];
528 static char *save_stack_p
;
529 #define END_STRING_AND_SAVE(s) \
530 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
531 #define RESTORE_END_STRING(s) \
532 do { *(s) = *--save_stack_p; } while (0)
534 /* The instruction we're assembling. */
537 /* Possible templates for current insn. */
538 static const templates
*current_templates
;
540 /* Per instruction expressionS buffers: max displacements & immediates. */
541 static expressionS disp_expressions
[MAX_MEMORY_OPERANDS
];
542 static expressionS im_expressions
[MAX_IMMEDIATE_OPERANDS
];
544 /* Current operand we are working on. */
545 static int this_operand
= -1;
547 /* We support four different modes. FLAG_CODE variable is used to distinguish
555 static enum flag_code flag_code
;
556 static unsigned int object_64bit
;
557 static unsigned int disallow_64bit_reloc
;
558 static int use_rela_relocations
= 0;
560 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
561 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
562 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
564 /* The ELF ABI to use. */
572 static enum x86_elf_abi x86_elf_abi
= I386_ABI
;
575 #if defined (TE_PE) || defined (TE_PEP)
576 /* Use big object file format. */
577 static int use_big_obj
= 0;
580 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
581 /* 1 if generating code for a shared library. */
582 static int shared
= 0;
585 /* 1 for intel syntax,
587 static int intel_syntax
= 0;
589 /* 1 for Intel64 ISA,
593 /* 1 for intel mnemonic,
594 0 if att mnemonic. */
595 static int intel_mnemonic
= !SYSV386_COMPAT
;
597 /* 1 if pseudo registers are permitted. */
598 static int allow_pseudo_reg
= 0;
600 /* 1 if register prefix % not required. */
601 static int allow_naked_reg
= 0;
603 /* 1 if the assembler should add BND prefix for all control-transferring
604 instructions supporting it, even if this prefix wasn't specified
606 static int add_bnd_prefix
= 0;
608 /* 1 if pseudo index register, eiz/riz, is allowed . */
609 static int allow_index_reg
= 0;
611 /* 1 if the assembler should ignore LOCK prefix, even if it was
612 specified explicitly. */
613 static int omit_lock_prefix
= 0;
615 /* 1 if the assembler should encode lfence, mfence, and sfence as
616 "lock addl $0, (%{re}sp)". */
617 static int avoid_fence
= 0;
619 /* 1 if the assembler should generate relax relocations. */
621 static int generate_relax_relocations
622 = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS
;
624 static enum check_kind
630 sse_check
, operand_check
= check_warning
;
633 1. Clear the REX_W bit with register operand if possible.
634 2. Above plus use 128bit vector instruction to clear the full vector
637 static int optimize
= 0;
640 1. Clear the REX_W bit with register operand if possible.
641 2. Above plus use 128bit vector instruction to clear the full vector
643 3. Above plus optimize "test{q,l,w} $imm8,%r{64,32,16}" to
646 static int optimize_for_space
= 0;
648 /* Register prefix used for error message. */
649 static const char *register_prefix
= "%";
651 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
652 leave, push, and pop instructions so that gcc has the same stack
653 frame as in 32 bit mode. */
654 static char stackop_size
= '\0';
656 /* Non-zero to optimize code alignment. */
657 int optimize_align_code
= 1;
659 /* Non-zero to quieten some warnings. */
660 static int quiet_warnings
= 0;
663 static const char *cpu_arch_name
= NULL
;
664 static char *cpu_sub_arch_name
= NULL
;
666 /* CPU feature flags. */
667 static i386_cpu_flags cpu_arch_flags
= CPU_UNKNOWN_FLAGS
;
669 /* If we have selected a cpu we are generating instructions for. */
670 static int cpu_arch_tune_set
= 0;
672 /* Cpu we are generating instructions for. */
673 enum processor_type cpu_arch_tune
= PROCESSOR_UNKNOWN
;
675 /* CPU feature flags of cpu we are generating instructions for. */
676 static i386_cpu_flags cpu_arch_tune_flags
;
678 /* CPU instruction set architecture used. */
679 enum processor_type cpu_arch_isa
= PROCESSOR_UNKNOWN
;
681 /* CPU feature flags of instruction set architecture used. */
682 i386_cpu_flags cpu_arch_isa_flags
;
684 /* If set, conditional jumps are not automatically promoted to handle
685 larger than a byte offset. */
686 static unsigned int no_cond_jump_promotion
= 0;
688 /* Encode SSE instructions with VEX prefix. */
689 static unsigned int sse2avx
;
691 /* Encode scalar AVX instructions with specific vector length. */
698 /* Encode VEX WIG instructions with specific vex.w. */
705 /* Encode scalar EVEX LIG instructions with specific vector length. */
713 /* Encode EVEX WIG instructions with specific evex.w. */
720 /* Value to encode in EVEX RC bits, for SAE-only instructions. */
721 static enum rc_type evexrcig
= rne
;
723 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
724 static symbolS
*GOT_symbol
;
726 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
727 unsigned int x86_dwarf2_return_column
;
729 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
730 int x86_cie_data_alignment
;
732 /* Interface to relax_segment.
733 There are 3 major relax states for 386 jump insns because the
734 different types of jumps add different sizes to frags when we're
735 figuring out what sort of jump to choose to reach a given label. */
738 #define UNCOND_JUMP 0
740 #define COND_JUMP86 2
745 #define SMALL16 (SMALL | CODE16)
747 #define BIG16 (BIG | CODE16)
751 #define INLINE __inline__
757 #define ENCODE_RELAX_STATE(type, size) \
758 ((relax_substateT) (((type) << 2) | (size)))
759 #define TYPE_FROM_RELAX_STATE(s) \
761 #define DISP_SIZE_FROM_RELAX_STATE(s) \
762 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
764 /* This table is used by relax_frag to promote short jumps to long
765 ones where necessary. SMALL (short) jumps may be promoted to BIG
766 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
767 don't allow a short jump in a 32 bit code segment to be promoted to
768 a 16 bit offset jump because it's slower (requires data size
769 prefix), and doesn't work, unless the destination is in the bottom
770 64k of the code segment (The top 16 bits of eip are zeroed). */
772 const relax_typeS md_relax_table
[] =
775 1) most positive reach of this state,
776 2) most negative reach of this state,
777 3) how many bytes this mode will have in the variable part of the frag
778 4) which index into the table to try if we can't fit into this one. */
780 /* UNCOND_JUMP states. */
781 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
782 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
783 /* dword jmp adds 4 bytes to frag:
784 0 extra opcode bytes, 4 displacement bytes. */
786 /* word jmp adds 2 byte2 to frag:
787 0 extra opcode bytes, 2 displacement bytes. */
790 /* COND_JUMP states. */
791 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
792 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
793 /* dword conditionals adds 5 bytes to frag:
794 1 extra opcode byte, 4 displacement bytes. */
796 /* word conditionals add 3 bytes to frag:
797 1 extra opcode byte, 2 displacement bytes. */
800 /* COND_JUMP86 states. */
801 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
802 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
803 /* dword conditionals adds 5 bytes to frag:
804 1 extra opcode byte, 4 displacement bytes. */
806 /* word conditionals add 4 bytes to frag:
807 1 displacement byte and a 3 byte long branch insn. */
811 static const arch_entry cpu_arch
[] =
813 /* Do not replace the first two entries - i386_target_format()
814 relies on them being there in this order. */
815 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32
,
816 CPU_GENERIC32_FLAGS
, 0 },
817 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64
,
818 CPU_GENERIC64_FLAGS
, 0 },
819 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN
,
821 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN
,
823 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN
,
825 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386
,
827 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486
,
829 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM
,
831 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO
,
833 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM
,
835 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO
,
836 CPU_PENTIUMPRO_FLAGS
, 0 },
837 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO
,
839 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO
,
841 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4
,
843 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA
,
845 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA
,
846 CPU_NOCONA_FLAGS
, 0 },
847 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE
,
849 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE
,
851 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2
,
852 CPU_CORE2_FLAGS
, 1 },
853 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2
,
854 CPU_CORE2_FLAGS
, 0 },
855 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7
,
856 CPU_COREI7_FLAGS
, 0 },
857 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM
,
859 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM
,
861 { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU
,
862 CPU_IAMCU_FLAGS
, 0 },
863 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6
,
865 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6
,
867 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON
,
868 CPU_ATHLON_FLAGS
, 0 },
869 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8
,
871 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8
,
873 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8
,
875 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10
,
876 CPU_AMDFAM10_FLAGS
, 0 },
877 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD
,
878 CPU_BDVER1_FLAGS
, 0 },
879 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD
,
880 CPU_BDVER2_FLAGS
, 0 },
881 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD
,
882 CPU_BDVER3_FLAGS
, 0 },
883 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD
,
884 CPU_BDVER4_FLAGS
, 0 },
885 { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER
,
886 CPU_ZNVER1_FLAGS
, 0 },
887 { STRING_COMMA_LEN ("znver2"), PROCESSOR_ZNVER
,
888 CPU_ZNVER2_FLAGS
, 0 },
889 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT
,
890 CPU_BTVER1_FLAGS
, 0 },
891 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT
,
892 CPU_BTVER2_FLAGS
, 0 },
893 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN
,
895 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN
,
897 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN
,
899 { STRING_COMMA_LEN (".687"), PROCESSOR_UNKNOWN
,
901 { STRING_COMMA_LEN (".cmov"), PROCESSOR_UNKNOWN
,
903 { STRING_COMMA_LEN (".fxsr"), PROCESSOR_UNKNOWN
,
905 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN
,
907 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN
,
909 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN
,
911 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN
,
913 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN
,
914 CPU_SSSE3_FLAGS
, 0 },
915 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN
,
916 CPU_SSE4_1_FLAGS
, 0 },
917 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN
,
918 CPU_SSE4_2_FLAGS
, 0 },
919 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN
,
920 CPU_SSE4_2_FLAGS
, 0 },
921 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN
,
923 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN
,
925 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN
,
926 CPU_AVX512F_FLAGS
, 0 },
927 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN
,
928 CPU_AVX512CD_FLAGS
, 0 },
929 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN
,
930 CPU_AVX512ER_FLAGS
, 0 },
931 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN
,
932 CPU_AVX512PF_FLAGS
, 0 },
933 { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN
,
934 CPU_AVX512DQ_FLAGS
, 0 },
935 { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN
,
936 CPU_AVX512BW_FLAGS
, 0 },
937 { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN
,
938 CPU_AVX512VL_FLAGS
, 0 },
939 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN
,
941 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN
,
942 CPU_VMFUNC_FLAGS
, 0 },
943 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN
,
945 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN
,
946 CPU_XSAVE_FLAGS
, 0 },
947 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN
,
948 CPU_XSAVEOPT_FLAGS
, 0 },
949 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN
,
950 CPU_XSAVEC_FLAGS
, 0 },
951 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN
,
952 CPU_XSAVES_FLAGS
, 0 },
953 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN
,
955 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN
,
956 CPU_PCLMUL_FLAGS
, 0 },
957 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN
,
958 CPU_PCLMUL_FLAGS
, 1 },
959 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN
,
960 CPU_FSGSBASE_FLAGS
, 0 },
961 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN
,
962 CPU_RDRND_FLAGS
, 0 },
963 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN
,
965 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN
,
967 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN
,
969 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN
,
971 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN
,
973 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN
,
975 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN
,
976 CPU_MOVBE_FLAGS
, 0 },
977 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN
,
979 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN
,
981 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN
,
982 CPU_LZCNT_FLAGS
, 0 },
983 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN
,
985 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN
,
987 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN
,
988 CPU_INVPCID_FLAGS
, 0 },
989 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN
,
990 CPU_CLFLUSH_FLAGS
, 0 },
991 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN
,
993 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN
,
994 CPU_SYSCALL_FLAGS
, 0 },
995 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN
,
996 CPU_RDTSCP_FLAGS
, 0 },
997 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN
,
998 CPU_3DNOW_FLAGS
, 0 },
999 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN
,
1000 CPU_3DNOWA_FLAGS
, 0 },
1001 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN
,
1002 CPU_PADLOCK_FLAGS
, 0 },
1003 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN
,
1004 CPU_SVME_FLAGS
, 1 },
1005 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN
,
1006 CPU_SVME_FLAGS
, 0 },
1007 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN
,
1008 CPU_SSE4A_FLAGS
, 0 },
1009 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN
,
1011 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN
,
1013 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN
,
1015 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN
,
1017 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN
,
1018 CPU_RDSEED_FLAGS
, 0 },
1019 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN
,
1020 CPU_PRFCHW_FLAGS
, 0 },
1021 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN
,
1022 CPU_SMAP_FLAGS
, 0 },
1023 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN
,
1025 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN
,
1027 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN
,
1028 CPU_CLFLUSHOPT_FLAGS
, 0 },
1029 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN
,
1030 CPU_PREFETCHWT1_FLAGS
, 0 },
1031 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN
,
1033 { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN
,
1034 CPU_CLWB_FLAGS
, 0 },
1035 { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN
,
1036 CPU_AVX512IFMA_FLAGS
, 0 },
1037 { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN
,
1038 CPU_AVX512VBMI_FLAGS
, 0 },
1039 { STRING_COMMA_LEN (".avx512_4fmaps"), PROCESSOR_UNKNOWN
,
1040 CPU_AVX512_4FMAPS_FLAGS
, 0 },
1041 { STRING_COMMA_LEN (".avx512_4vnniw"), PROCESSOR_UNKNOWN
,
1042 CPU_AVX512_4VNNIW_FLAGS
, 0 },
1043 { STRING_COMMA_LEN (".avx512_vpopcntdq"), PROCESSOR_UNKNOWN
,
1044 CPU_AVX512_VPOPCNTDQ_FLAGS
, 0 },
1045 { STRING_COMMA_LEN (".avx512_vbmi2"), PROCESSOR_UNKNOWN
,
1046 CPU_AVX512_VBMI2_FLAGS
, 0 },
1047 { STRING_COMMA_LEN (".avx512_vnni"), PROCESSOR_UNKNOWN
,
1048 CPU_AVX512_VNNI_FLAGS
, 0 },
1049 { STRING_COMMA_LEN (".avx512_bitalg"), PROCESSOR_UNKNOWN
,
1050 CPU_AVX512_BITALG_FLAGS
, 0 },
1051 { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN
,
1052 CPU_CLZERO_FLAGS
, 0 },
1053 { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN
,
1054 CPU_MWAITX_FLAGS
, 0 },
1055 { STRING_COMMA_LEN (".ospke"), PROCESSOR_UNKNOWN
,
1056 CPU_OSPKE_FLAGS
, 0 },
1057 { STRING_COMMA_LEN (".rdpid"), PROCESSOR_UNKNOWN
,
1058 CPU_RDPID_FLAGS
, 0 },
1059 { STRING_COMMA_LEN (".ptwrite"), PROCESSOR_UNKNOWN
,
1060 CPU_PTWRITE_FLAGS
, 0 },
1061 { STRING_COMMA_LEN (".ibt"), PROCESSOR_UNKNOWN
,
1063 { STRING_COMMA_LEN (".shstk"), PROCESSOR_UNKNOWN
,
1064 CPU_SHSTK_FLAGS
, 0 },
1065 { STRING_COMMA_LEN (".gfni"), PROCESSOR_UNKNOWN
,
1066 CPU_GFNI_FLAGS
, 0 },
1067 { STRING_COMMA_LEN (".vaes"), PROCESSOR_UNKNOWN
,
1068 CPU_VAES_FLAGS
, 0 },
1069 { STRING_COMMA_LEN (".vpclmulqdq"), PROCESSOR_UNKNOWN
,
1070 CPU_VPCLMULQDQ_FLAGS
, 0 },
1071 { STRING_COMMA_LEN (".wbnoinvd"), PROCESSOR_UNKNOWN
,
1072 CPU_WBNOINVD_FLAGS
, 0 },
1073 { STRING_COMMA_LEN (".pconfig"), PROCESSOR_UNKNOWN
,
1074 CPU_PCONFIG_FLAGS
, 0 },
1075 { STRING_COMMA_LEN (".waitpkg"), PROCESSOR_UNKNOWN
,
1076 CPU_WAITPKG_FLAGS
, 0 },
1077 { STRING_COMMA_LEN (".cldemote"), PROCESSOR_UNKNOWN
,
1078 CPU_CLDEMOTE_FLAGS
, 0 },
1079 { STRING_COMMA_LEN (".movdiri"), PROCESSOR_UNKNOWN
,
1080 CPU_MOVDIRI_FLAGS
, 0 },
1081 { STRING_COMMA_LEN (".movdir64b"), PROCESSOR_UNKNOWN
,
1082 CPU_MOVDIR64B_FLAGS
, 0 },
1085 static const noarch_entry cpu_noarch
[] =
1087 { STRING_COMMA_LEN ("no87"), CPU_ANY_X87_FLAGS
},
1088 { STRING_COMMA_LEN ("no287"), CPU_ANY_287_FLAGS
},
1089 { STRING_COMMA_LEN ("no387"), CPU_ANY_387_FLAGS
},
1090 { STRING_COMMA_LEN ("no687"), CPU_ANY_687_FLAGS
},
1091 { STRING_COMMA_LEN ("nocmov"), CPU_ANY_CMOV_FLAGS
},
1092 { STRING_COMMA_LEN ("nofxsr"), CPU_ANY_FXSR_FLAGS
},
1093 { STRING_COMMA_LEN ("nommx"), CPU_ANY_MMX_FLAGS
},
1094 { STRING_COMMA_LEN ("nosse"), CPU_ANY_SSE_FLAGS
},
1095 { STRING_COMMA_LEN ("nosse2"), CPU_ANY_SSE2_FLAGS
},
1096 { STRING_COMMA_LEN ("nosse3"), CPU_ANY_SSE3_FLAGS
},
1097 { STRING_COMMA_LEN ("nossse3"), CPU_ANY_SSSE3_FLAGS
},
1098 { STRING_COMMA_LEN ("nosse4.1"), CPU_ANY_SSE4_1_FLAGS
},
1099 { STRING_COMMA_LEN ("nosse4.2"), CPU_ANY_SSE4_2_FLAGS
},
1100 { STRING_COMMA_LEN ("nosse4"), CPU_ANY_SSE4_1_FLAGS
},
1101 { STRING_COMMA_LEN ("noavx"), CPU_ANY_AVX_FLAGS
},
1102 { STRING_COMMA_LEN ("noavx2"), CPU_ANY_AVX2_FLAGS
},
1103 { STRING_COMMA_LEN ("noavx512f"), CPU_ANY_AVX512F_FLAGS
},
1104 { STRING_COMMA_LEN ("noavx512cd"), CPU_ANY_AVX512CD_FLAGS
},
1105 { STRING_COMMA_LEN ("noavx512er"), CPU_ANY_AVX512ER_FLAGS
},
1106 { STRING_COMMA_LEN ("noavx512pf"), CPU_ANY_AVX512PF_FLAGS
},
1107 { STRING_COMMA_LEN ("noavx512dq"), CPU_ANY_AVX512DQ_FLAGS
},
1108 { STRING_COMMA_LEN ("noavx512bw"), CPU_ANY_AVX512BW_FLAGS
},
1109 { STRING_COMMA_LEN ("noavx512vl"), CPU_ANY_AVX512VL_FLAGS
},
1110 { STRING_COMMA_LEN ("noavx512ifma"), CPU_ANY_AVX512IFMA_FLAGS
},
1111 { STRING_COMMA_LEN ("noavx512vbmi"), CPU_ANY_AVX512VBMI_FLAGS
},
1112 { STRING_COMMA_LEN ("noavx512_4fmaps"), CPU_ANY_AVX512_4FMAPS_FLAGS
},
1113 { STRING_COMMA_LEN ("noavx512_4vnniw"), CPU_ANY_AVX512_4VNNIW_FLAGS
},
1114 { STRING_COMMA_LEN ("noavx512_vpopcntdq"), CPU_ANY_AVX512_VPOPCNTDQ_FLAGS
},
1115 { STRING_COMMA_LEN ("noavx512_vbmi2"), CPU_ANY_AVX512_VBMI2_FLAGS
},
1116 { STRING_COMMA_LEN ("noavx512_vnni"), CPU_ANY_AVX512_VNNI_FLAGS
},
1117 { STRING_COMMA_LEN ("noavx512_bitalg"), CPU_ANY_AVX512_BITALG_FLAGS
},
1118 { STRING_COMMA_LEN ("noibt"), CPU_ANY_IBT_FLAGS
},
1119 { STRING_COMMA_LEN ("noshstk"), CPU_ANY_SHSTK_FLAGS
},
1120 { STRING_COMMA_LEN ("nomovdiri"), CPU_ANY_MOVDIRI_FLAGS
},
1121 { STRING_COMMA_LEN ("nomovdir64b"), CPU_ANY_MOVDIR64B_FLAGS
},
1125 /* Like s_lcomm_internal in gas/read.c but the alignment string
1126 is allowed to be optional. */
1129 pe_lcomm_internal (int needs_align
, symbolS
*symbolP
, addressT size
)
1136 && *input_line_pointer
== ',')
1138 align
= parse_align (needs_align
- 1);
1140 if (align
== (addressT
) -1)
1155 bss_alloc (symbolP
, size
, align
);
1160 pe_lcomm (int needs_align
)
1162 s_comm_internal (needs_align
* 2, pe_lcomm_internal
);
1166 const pseudo_typeS md_pseudo_table
[] =
1168 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
1169 {"align", s_align_bytes
, 0},
1171 {"align", s_align_ptwo
, 0},
1173 {"arch", set_cpu_arch
, 0},
1177 {"lcomm", pe_lcomm
, 1},
1179 {"ffloat", float_cons
, 'f'},
1180 {"dfloat", float_cons
, 'd'},
1181 {"tfloat", float_cons
, 'x'},
1183 {"slong", signed_cons
, 4},
1184 {"noopt", s_ignore
, 0},
1185 {"optim", s_ignore
, 0},
1186 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
1187 {"code16", set_code_flag
, CODE_16BIT
},
1188 {"code32", set_code_flag
, CODE_32BIT
},
1190 {"code64", set_code_flag
, CODE_64BIT
},
1192 {"intel_syntax", set_intel_syntax
, 1},
1193 {"att_syntax", set_intel_syntax
, 0},
1194 {"intel_mnemonic", set_intel_mnemonic
, 1},
1195 {"att_mnemonic", set_intel_mnemonic
, 0},
1196 {"allow_index_reg", set_allow_index_reg
, 1},
1197 {"disallow_index_reg", set_allow_index_reg
, 0},
1198 {"sse_check", set_check
, 0},
1199 {"operand_check", set_check
, 1},
1200 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1201 {"largecomm", handle_large_common
, 0},
1203 {"file", dwarf2_directive_file
, 0},
1204 {"loc", dwarf2_directive_loc
, 0},
1205 {"loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0},
1208 {"secrel32", pe_directive_secrel
, 0},
1213 /* For interface with expression (). */
1214 extern char *input_line_pointer
;
1216 /* Hash table for instruction mnemonic lookup. */
1217 static struct hash_control
*op_hash
;
1219 /* Hash table for register lookup. */
1220 static struct hash_control
*reg_hash
;
1222 /* Various efficient no-op patterns for aligning code labels.
1223 Note: Don't try to assemble the instructions in the comments.
1224 0L and 0w are not legal. */
1225 static const unsigned char f32_1
[] =
1227 static const unsigned char f32_2
[] =
1228 {0x66,0x90}; /* xchg %ax,%ax */
1229 static const unsigned char f32_3
[] =
1230 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1231 static const unsigned char f32_4
[] =
1232 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1233 static const unsigned char f32_6
[] =
1234 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1235 static const unsigned char f32_7
[] =
1236 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1237 static const unsigned char f16_3
[] =
1238 {0x8d,0x74,0x00}; /* lea 0(%si),%si */
1239 static const unsigned char f16_4
[] =
1240 {0x8d,0xb4,0x00,0x00}; /* lea 0W(%si),%si */
1241 static const unsigned char jump_disp8
[] =
1242 {0xeb}; /* jmp disp8 */
1243 static const unsigned char jump32_disp32
[] =
1244 {0xe9}; /* jmp disp32 */
1245 static const unsigned char jump16_disp32
[] =
1246 {0x66,0xe9}; /* jmp disp32 */
1247 /* 32-bit NOPs patterns. */
1248 static const unsigned char *const f32_patt
[] = {
1249 f32_1
, f32_2
, f32_3
, f32_4
, NULL
, f32_6
, f32_7
1251 /* 16-bit NOPs patterns. */
1252 static const unsigned char *const f16_patt
[] = {
1253 f32_1
, f32_2
, f16_3
, f16_4
1255 /* nopl (%[re]ax) */
1256 static const unsigned char alt_3
[] =
1258 /* nopl 0(%[re]ax) */
1259 static const unsigned char alt_4
[] =
1260 {0x0f,0x1f,0x40,0x00};
1261 /* nopl 0(%[re]ax,%[re]ax,1) */
1262 static const unsigned char alt_5
[] =
1263 {0x0f,0x1f,0x44,0x00,0x00};
1264 /* nopw 0(%[re]ax,%[re]ax,1) */
1265 static const unsigned char alt_6
[] =
1266 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1267 /* nopl 0L(%[re]ax) */
1268 static const unsigned char alt_7
[] =
1269 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1270 /* nopl 0L(%[re]ax,%[re]ax,1) */
1271 static const unsigned char alt_8
[] =
1272 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1273 /* nopw 0L(%[re]ax,%[re]ax,1) */
1274 static const unsigned char alt_9
[] =
1275 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1276 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1277 static const unsigned char alt_10
[] =
1278 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1279 /* data16 nopw %cs:0L(%eax,%eax,1) */
1280 static const unsigned char alt_11
[] =
1281 {0x66,0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1282 /* 32-bit and 64-bit NOPs patterns. */
1283 static const unsigned char *const alt_patt
[] = {
1284 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
1285 alt_9
, alt_10
, alt_11
1288 /* Genenerate COUNT bytes of NOPs to WHERE from PATT with the maximum
1289 size of a single NOP instruction MAX_SINGLE_NOP_SIZE. */
1292 i386_output_nops (char *where
, const unsigned char *const *patt
,
1293 int count
, int max_single_nop_size
)
1296 /* Place the longer NOP first. */
1299 const unsigned char *nops
= patt
[max_single_nop_size
- 1];
1301 /* Use the smaller one if the requsted one isn't available. */
1304 max_single_nop_size
--;
1305 nops
= patt
[max_single_nop_size
- 1];
1308 last
= count
% max_single_nop_size
;
1311 for (offset
= 0; offset
< count
; offset
+= max_single_nop_size
)
1312 memcpy (where
+ offset
, nops
, max_single_nop_size
);
1316 nops
= patt
[last
- 1];
1319 /* Use the smaller one plus one-byte NOP if the needed one
1322 nops
= patt
[last
- 1];
1323 memcpy (where
+ offset
, nops
, last
);
1324 where
[offset
+ last
] = *patt
[0];
1327 memcpy (where
+ offset
, nops
, last
);
1332 fits_in_imm7 (offsetT num
)
1334 return (num
& 0x7f) == num
;
1338 fits_in_imm31 (offsetT num
)
1340 return (num
& 0x7fffffff) == num
;
1343 /* Genenerate COUNT bytes of NOPs to WHERE with the maximum size of a
1344 single NOP instruction LIMIT. */
1347 i386_generate_nops (fragS
*fragP
, char *where
, offsetT count
, int limit
)
1349 const unsigned char *const *patt
= NULL
;
1350 int max_single_nop_size
;
1351 /* Maximum number of NOPs before switching to jump over NOPs. */
1352 int max_number_of_nops
;
1354 switch (fragP
->fr_type
)
1363 /* We need to decide which NOP sequence to use for 32bit and
1364 64bit. When -mtune= is used:
1366 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1367 PROCESSOR_GENERIC32, f32_patt will be used.
1368 2. For the rest, alt_patt will be used.
1370 When -mtune= isn't used, alt_patt will be used if
1371 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
1374 When -march= or .arch is used, we can't use anything beyond
1375 cpu_arch_isa_flags. */
1377 if (flag_code
== CODE_16BIT
)
1380 max_single_nop_size
= sizeof (f16_patt
) / sizeof (f16_patt
[0]);
1381 /* Limit number of NOPs to 2 in 16-bit mode. */
1382 max_number_of_nops
= 2;
1386 if (fragP
->tc_frag_data
.isa
== PROCESSOR_UNKNOWN
)
1388 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1389 switch (cpu_arch_tune
)
1391 case PROCESSOR_UNKNOWN
:
1392 /* We use cpu_arch_isa_flags to check if we SHOULD
1393 optimize with nops. */
1394 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1399 case PROCESSOR_PENTIUM4
:
1400 case PROCESSOR_NOCONA
:
1401 case PROCESSOR_CORE
:
1402 case PROCESSOR_CORE2
:
1403 case PROCESSOR_COREI7
:
1404 case PROCESSOR_L1OM
:
1405 case PROCESSOR_K1OM
:
1406 case PROCESSOR_GENERIC64
:
1408 case PROCESSOR_ATHLON
:
1410 case PROCESSOR_AMDFAM10
:
1412 case PROCESSOR_ZNVER
:
1416 case PROCESSOR_I386
:
1417 case PROCESSOR_I486
:
1418 case PROCESSOR_PENTIUM
:
1419 case PROCESSOR_PENTIUMPRO
:
1420 case PROCESSOR_IAMCU
:
1421 case PROCESSOR_GENERIC32
:
1428 switch (fragP
->tc_frag_data
.tune
)
1430 case PROCESSOR_UNKNOWN
:
1431 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1432 PROCESSOR_UNKNOWN. */
1436 case PROCESSOR_I386
:
1437 case PROCESSOR_I486
:
1438 case PROCESSOR_PENTIUM
:
1439 case PROCESSOR_IAMCU
:
1441 case PROCESSOR_ATHLON
:
1443 case PROCESSOR_AMDFAM10
:
1445 case PROCESSOR_ZNVER
:
1447 case PROCESSOR_GENERIC32
:
1448 /* We use cpu_arch_isa_flags to check if we CAN optimize
1450 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1455 case PROCESSOR_PENTIUMPRO
:
1456 case PROCESSOR_PENTIUM4
:
1457 case PROCESSOR_NOCONA
:
1458 case PROCESSOR_CORE
:
1459 case PROCESSOR_CORE2
:
1460 case PROCESSOR_COREI7
:
1461 case PROCESSOR_L1OM
:
1462 case PROCESSOR_K1OM
:
1463 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1468 case PROCESSOR_GENERIC64
:
1474 if (patt
== f32_patt
)
1476 max_single_nop_size
= sizeof (f32_patt
) / sizeof (f32_patt
[0]);
1477 /* Limit number of NOPs to 2 for older processors. */
1478 max_number_of_nops
= 2;
1482 max_single_nop_size
= sizeof (alt_patt
) / sizeof (alt_patt
[0]);
1483 /* Limit number of NOPs to 7 for newer processors. */
1484 max_number_of_nops
= 7;
1489 limit
= max_single_nop_size
;
1491 if (fragP
->fr_type
== rs_fill_nop
)
1493 /* Output NOPs for .nop directive. */
1494 if (limit
> max_single_nop_size
)
1496 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
1497 _("invalid single nop size: %d "
1498 "(expect within [0, %d])"),
1499 limit
, max_single_nop_size
);
1504 fragP
->fr_var
= count
;
1506 if ((count
/ max_single_nop_size
) > max_number_of_nops
)
1508 /* Generate jump over NOPs. */
1509 offsetT disp
= count
- 2;
1510 if (fits_in_imm7 (disp
))
1512 /* Use "jmp disp8" if possible. */
1514 where
[0] = jump_disp8
[0];
1520 unsigned int size_of_jump
;
1522 if (flag_code
== CODE_16BIT
)
1524 where
[0] = jump16_disp32
[0];
1525 where
[1] = jump16_disp32
[1];
1530 where
[0] = jump32_disp32
[0];
1534 count
-= size_of_jump
+ 4;
1535 if (!fits_in_imm31 (count
))
1537 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
1538 _("jump over nop padding out of range"));
1542 md_number_to_chars (where
+ size_of_jump
, count
, 4);
1543 where
+= size_of_jump
+ 4;
1547 /* Generate multiple NOPs. */
1548 i386_output_nops (where
, patt
, count
, limit
);
1552 operand_type_all_zero (const union i386_operand_type
*x
)
1554 switch (ARRAY_SIZE(x
->array
))
1565 return !x
->array
[0];
1572 operand_type_set (union i386_operand_type
*x
, unsigned int v
)
1574 switch (ARRAY_SIZE(x
->array
))
1592 operand_type_equal (const union i386_operand_type
*x
,
1593 const union i386_operand_type
*y
)
1595 switch (ARRAY_SIZE(x
->array
))
1598 if (x
->array
[2] != y
->array
[2])
1602 if (x
->array
[1] != y
->array
[1])
1606 return x
->array
[0] == y
->array
[0];
1614 cpu_flags_all_zero (const union i386_cpu_flags
*x
)
1616 switch (ARRAY_SIZE(x
->array
))
1631 return !x
->array
[0];
1638 cpu_flags_equal (const union i386_cpu_flags
*x
,
1639 const union i386_cpu_flags
*y
)
1641 switch (ARRAY_SIZE(x
->array
))
1644 if (x
->array
[3] != y
->array
[3])
1648 if (x
->array
[2] != y
->array
[2])
1652 if (x
->array
[1] != y
->array
[1])
1656 return x
->array
[0] == y
->array
[0];
1664 cpu_flags_check_cpu64 (i386_cpu_flags f
)
1666 return !((flag_code
== CODE_64BIT
&& f
.bitfield
.cpuno64
)
1667 || (flag_code
!= CODE_64BIT
&& f
.bitfield
.cpu64
));
1670 static INLINE i386_cpu_flags
1671 cpu_flags_and (i386_cpu_flags x
, i386_cpu_flags y
)
1673 switch (ARRAY_SIZE (x
.array
))
1676 x
.array
[3] &= y
.array
[3];
1679 x
.array
[2] &= y
.array
[2];
1682 x
.array
[1] &= y
.array
[1];
1685 x
.array
[0] &= y
.array
[0];
1693 static INLINE i386_cpu_flags
1694 cpu_flags_or (i386_cpu_flags x
, i386_cpu_flags y
)
1696 switch (ARRAY_SIZE (x
.array
))
1699 x
.array
[3] |= y
.array
[3];
1702 x
.array
[2] |= y
.array
[2];
1705 x
.array
[1] |= y
.array
[1];
1708 x
.array
[0] |= y
.array
[0];
1716 static INLINE i386_cpu_flags
1717 cpu_flags_and_not (i386_cpu_flags x
, i386_cpu_flags y
)
1719 switch (ARRAY_SIZE (x
.array
))
1722 x
.array
[3] &= ~y
.array
[3];
1725 x
.array
[2] &= ~y
.array
[2];
1728 x
.array
[1] &= ~y
.array
[1];
1731 x
.array
[0] &= ~y
.array
[0];
1739 #define CPU_FLAGS_ARCH_MATCH 0x1
1740 #define CPU_FLAGS_64BIT_MATCH 0x2
1742 #define CPU_FLAGS_PERFECT_MATCH \
1743 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_64BIT_MATCH)
1745 /* Return CPU flags match bits. */
1748 cpu_flags_match (const insn_template
*t
)
1750 i386_cpu_flags x
= t
->cpu_flags
;
1751 int match
= cpu_flags_check_cpu64 (x
) ? CPU_FLAGS_64BIT_MATCH
: 0;
1753 x
.bitfield
.cpu64
= 0;
1754 x
.bitfield
.cpuno64
= 0;
1756 if (cpu_flags_all_zero (&x
))
1758 /* This instruction is available on all archs. */
1759 match
|= CPU_FLAGS_ARCH_MATCH
;
1763 /* This instruction is available only on some archs. */
1764 i386_cpu_flags cpu
= cpu_arch_flags
;
1766 /* AVX512VL is no standalone feature - match it and then strip it. */
1767 if (x
.bitfield
.cpuavx512vl
&& !cpu
.bitfield
.cpuavx512vl
)
1769 x
.bitfield
.cpuavx512vl
= 0;
1771 cpu
= cpu_flags_and (x
, cpu
);
1772 if (!cpu_flags_all_zero (&cpu
))
1774 if (x
.bitfield
.cpuavx
)
1776 /* We need to check a few extra flags with AVX. */
1777 if (cpu
.bitfield
.cpuavx
1778 && (!t
->opcode_modifier
.sse2avx
|| sse2avx
)
1779 && (!x
.bitfield
.cpuaes
|| cpu
.bitfield
.cpuaes
)
1780 && (!x
.bitfield
.cpugfni
|| cpu
.bitfield
.cpugfni
)
1781 && (!x
.bitfield
.cpupclmul
|| cpu
.bitfield
.cpupclmul
))
1782 match
|= CPU_FLAGS_ARCH_MATCH
;
1784 else if (x
.bitfield
.cpuavx512f
)
1786 /* We need to check a few extra flags with AVX512F. */
1787 if (cpu
.bitfield
.cpuavx512f
1788 && (!x
.bitfield
.cpugfni
|| cpu
.bitfield
.cpugfni
)
1789 && (!x
.bitfield
.cpuvaes
|| cpu
.bitfield
.cpuvaes
)
1790 && (!x
.bitfield
.cpuvpclmulqdq
|| cpu
.bitfield
.cpuvpclmulqdq
))
1791 match
|= CPU_FLAGS_ARCH_MATCH
;
1794 match
|= CPU_FLAGS_ARCH_MATCH
;
1800 static INLINE i386_operand_type
1801 operand_type_and (i386_operand_type x
, i386_operand_type y
)
1803 switch (ARRAY_SIZE (x
.array
))
1806 x
.array
[2] &= y
.array
[2];
1809 x
.array
[1] &= y
.array
[1];
1812 x
.array
[0] &= y
.array
[0];
1820 static INLINE i386_operand_type
1821 operand_type_and_not (i386_operand_type x
, i386_operand_type y
)
1823 switch (ARRAY_SIZE (x
.array
))
1826 x
.array
[2] &= ~y
.array
[2];
1829 x
.array
[1] &= ~y
.array
[1];
1832 x
.array
[0] &= ~y
.array
[0];
1840 static INLINE i386_operand_type
1841 operand_type_or (i386_operand_type x
, i386_operand_type y
)
1843 switch (ARRAY_SIZE (x
.array
))
1846 x
.array
[2] |= y
.array
[2];
1849 x
.array
[1] |= y
.array
[1];
1852 x
.array
[0] |= y
.array
[0];
1860 static INLINE i386_operand_type
1861 operand_type_xor (i386_operand_type x
, i386_operand_type y
)
1863 switch (ARRAY_SIZE (x
.array
))
1866 x
.array
[2] ^= y
.array
[2];
1869 x
.array
[1] ^= y
.array
[1];
1872 x
.array
[0] ^= y
.array
[0];
1880 static const i386_operand_type acc32
= OPERAND_TYPE_ACC32
;
1881 static const i386_operand_type acc64
= OPERAND_TYPE_ACC64
;
1882 static const i386_operand_type disp16
= OPERAND_TYPE_DISP16
;
1883 static const i386_operand_type disp32
= OPERAND_TYPE_DISP32
;
1884 static const i386_operand_type disp32s
= OPERAND_TYPE_DISP32S
;
1885 static const i386_operand_type disp16_32
= OPERAND_TYPE_DISP16_32
;
1886 static const i386_operand_type anydisp
1887 = OPERAND_TYPE_ANYDISP
;
1888 static const i386_operand_type regxmm
= OPERAND_TYPE_REGXMM
;
1889 static const i386_operand_type regmask
= OPERAND_TYPE_REGMASK
;
1890 static const i386_operand_type imm8
= OPERAND_TYPE_IMM8
;
1891 static const i386_operand_type imm8s
= OPERAND_TYPE_IMM8S
;
1892 static const i386_operand_type imm16
= OPERAND_TYPE_IMM16
;
1893 static const i386_operand_type imm32
= OPERAND_TYPE_IMM32
;
1894 static const i386_operand_type imm32s
= OPERAND_TYPE_IMM32S
;
1895 static const i386_operand_type imm64
= OPERAND_TYPE_IMM64
;
1896 static const i386_operand_type imm16_32
= OPERAND_TYPE_IMM16_32
;
1897 static const i386_operand_type imm16_32s
= OPERAND_TYPE_IMM16_32S
;
1898 static const i386_operand_type imm16_32_32s
= OPERAND_TYPE_IMM16_32_32S
;
1899 static const i386_operand_type vec_imm4
= OPERAND_TYPE_VEC_IMM4
;
1910 operand_type_check (i386_operand_type t
, enum operand_type c
)
1915 return t
.bitfield
.reg
;
1918 return (t
.bitfield
.imm8
1922 || t
.bitfield
.imm32s
1923 || t
.bitfield
.imm64
);
1926 return (t
.bitfield
.disp8
1927 || t
.bitfield
.disp16
1928 || t
.bitfield
.disp32
1929 || t
.bitfield
.disp32s
1930 || t
.bitfield
.disp64
);
1933 return (t
.bitfield
.disp8
1934 || t
.bitfield
.disp16
1935 || t
.bitfield
.disp32
1936 || t
.bitfield
.disp32s
1937 || t
.bitfield
.disp64
1938 || t
.bitfield
.baseindex
);
1947 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit/80bit size
1948 between operand GIVEN and opeand WANTED for instruction template T. */
1951 match_operand_size (const insn_template
*t
, unsigned int wanted
,
1954 return !((i
.types
[given
].bitfield
.byte
1955 && !t
->operand_types
[wanted
].bitfield
.byte
)
1956 || (i
.types
[given
].bitfield
.word
1957 && !t
->operand_types
[wanted
].bitfield
.word
)
1958 || (i
.types
[given
].bitfield
.dword
1959 && !t
->operand_types
[wanted
].bitfield
.dword
)
1960 || (i
.types
[given
].bitfield
.qword
1961 && !t
->operand_types
[wanted
].bitfield
.qword
)
1962 || (i
.types
[given
].bitfield
.tbyte
1963 && !t
->operand_types
[wanted
].bitfield
.tbyte
));
1966 /* Return 1 if there is no conflict in SIMD register between operand
1967 GIVEN and opeand WANTED for instruction template T. */
1970 match_simd_size (const insn_template
*t
, unsigned int wanted
,
1973 return !((i
.types
[given
].bitfield
.xmmword
1974 && !t
->operand_types
[wanted
].bitfield
.xmmword
)
1975 || (i
.types
[given
].bitfield
.ymmword
1976 && !t
->operand_types
[wanted
].bitfield
.ymmword
)
1977 || (i
.types
[given
].bitfield
.zmmword
1978 && !t
->operand_types
[wanted
].bitfield
.zmmword
));
1981 /* Return 1 if there is no conflict in any size between operand GIVEN
1982 and opeand WANTED for instruction template T. */
1985 match_mem_size (const insn_template
*t
, unsigned int wanted
,
1988 return (match_operand_size (t
, wanted
, given
)
1989 && !((i
.types
[given
].bitfield
.unspecified
1991 && !t
->operand_types
[wanted
].bitfield
.unspecified
)
1992 || (i
.types
[given
].bitfield
.fword
1993 && !t
->operand_types
[wanted
].bitfield
.fword
)
1994 /* For scalar opcode templates to allow register and memory
1995 operands at the same time, some special casing is needed
1996 here. Also for v{,p}broadcast*, {,v}pmov{s,z}*, and
1997 down-conversion vpmov*. */
1998 || ((t
->operand_types
[wanted
].bitfield
.regsimd
1999 && !t
->opcode_modifier
.broadcast
2000 && (t
->operand_types
[wanted
].bitfield
.byte
2001 || t
->operand_types
[wanted
].bitfield
.word
2002 || t
->operand_types
[wanted
].bitfield
.dword
2003 || t
->operand_types
[wanted
].bitfield
.qword
))
2004 ? (i
.types
[given
].bitfield
.xmmword
2005 || i
.types
[given
].bitfield
.ymmword
2006 || i
.types
[given
].bitfield
.zmmword
)
2007 : !match_simd_size(t
, wanted
, given
))));
2010 /* Return value has MATCH_STRAIGHT set if there is no size conflict on any
2011 operands for instruction template T, and it has MATCH_REVERSE set if there
2012 is no size conflict on any operands for the template with operands reversed
2013 (and the template allows for reversing in the first place). */
2015 #define MATCH_STRAIGHT 1
2016 #define MATCH_REVERSE 2
2018 static INLINE
unsigned int
2019 operand_size_match (const insn_template
*t
)
2021 unsigned int j
, match
= MATCH_STRAIGHT
;
2023 /* Don't check jump instructions. */
2024 if (t
->opcode_modifier
.jump
2025 || t
->opcode_modifier
.jumpbyte
2026 || t
->opcode_modifier
.jumpdword
2027 || t
->opcode_modifier
.jumpintersegment
)
2030 /* Check memory and accumulator operand size. */
2031 for (j
= 0; j
< i
.operands
; j
++)
2033 if (!i
.types
[j
].bitfield
.reg
&& !i
.types
[j
].bitfield
.regsimd
2034 && t
->operand_types
[j
].bitfield
.anysize
)
2037 if (t
->operand_types
[j
].bitfield
.reg
2038 && !match_operand_size (t
, j
, j
))
2044 if (t
->operand_types
[j
].bitfield
.regsimd
2045 && !match_simd_size (t
, j
, j
))
2051 if (t
->operand_types
[j
].bitfield
.acc
2052 && (!match_operand_size (t
, j
, j
) || !match_simd_size (t
, j
, j
)))
2058 if ((i
.flags
[j
] & Operand_Mem
) && !match_mem_size (t
, j
, j
))
2065 if (!t
->opcode_modifier
.d
)
2069 i
.error
= operand_size_mismatch
;
2073 /* Check reverse. */
2074 gas_assert (i
.operands
>= 2 && i
.operands
<= 3);
2076 for (j
= 0; j
< i
.operands
; j
++)
2078 unsigned int given
= i
.operands
- j
- 1;
2080 if (t
->operand_types
[j
].bitfield
.reg
2081 && !match_operand_size (t
, j
, given
))
2084 if (t
->operand_types
[j
].bitfield
.regsimd
2085 && !match_simd_size (t
, j
, given
))
2088 if (t
->operand_types
[j
].bitfield
.acc
2089 && (!match_operand_size (t
, j
, given
)
2090 || !match_simd_size (t
, j
, given
)))
2093 if ((i
.flags
[given
] & Operand_Mem
) && !match_mem_size (t
, j
, given
))
2097 return match
| MATCH_REVERSE
;
2101 operand_type_match (i386_operand_type overlap
,
2102 i386_operand_type given
)
2104 i386_operand_type temp
= overlap
;
2106 temp
.bitfield
.jumpabsolute
= 0;
2107 temp
.bitfield
.unspecified
= 0;
2108 temp
.bitfield
.byte
= 0;
2109 temp
.bitfield
.word
= 0;
2110 temp
.bitfield
.dword
= 0;
2111 temp
.bitfield
.fword
= 0;
2112 temp
.bitfield
.qword
= 0;
2113 temp
.bitfield
.tbyte
= 0;
2114 temp
.bitfield
.xmmword
= 0;
2115 temp
.bitfield
.ymmword
= 0;
2116 temp
.bitfield
.zmmword
= 0;
2117 if (operand_type_all_zero (&temp
))
2120 if (given
.bitfield
.baseindex
== overlap
.bitfield
.baseindex
2121 && given
.bitfield
.jumpabsolute
== overlap
.bitfield
.jumpabsolute
)
2125 i
.error
= operand_type_mismatch
;
2129 /* If given types g0 and g1 are registers they must be of the same type
2130 unless the expected operand type register overlap is null.
2131 Memory operand size of certain SIMD instructions is also being checked
2135 operand_type_register_match (i386_operand_type g0
,
2136 i386_operand_type t0
,
2137 i386_operand_type g1
,
2138 i386_operand_type t1
)
2140 if (!g0
.bitfield
.reg
2141 && !g0
.bitfield
.regsimd
2142 && (!operand_type_check (g0
, anymem
)
2143 || g0
.bitfield
.unspecified
2144 || !t0
.bitfield
.regsimd
))
2147 if (!g1
.bitfield
.reg
2148 && !g1
.bitfield
.regsimd
2149 && (!operand_type_check (g1
, anymem
)
2150 || g1
.bitfield
.unspecified
2151 || !t1
.bitfield
.regsimd
))
2154 if (g0
.bitfield
.byte
== g1
.bitfield
.byte
2155 && g0
.bitfield
.word
== g1
.bitfield
.word
2156 && g0
.bitfield
.dword
== g1
.bitfield
.dword
2157 && g0
.bitfield
.qword
== g1
.bitfield
.qword
2158 && g0
.bitfield
.xmmword
== g1
.bitfield
.xmmword
2159 && g0
.bitfield
.ymmword
== g1
.bitfield
.ymmword
2160 && g0
.bitfield
.zmmword
== g1
.bitfield
.zmmword
)
2163 if (!(t0
.bitfield
.byte
& t1
.bitfield
.byte
)
2164 && !(t0
.bitfield
.word
& t1
.bitfield
.word
)
2165 && !(t0
.bitfield
.dword
& t1
.bitfield
.dword
)
2166 && !(t0
.bitfield
.qword
& t1
.bitfield
.qword
)
2167 && !(t0
.bitfield
.xmmword
& t1
.bitfield
.xmmword
)
2168 && !(t0
.bitfield
.ymmword
& t1
.bitfield
.ymmword
)
2169 && !(t0
.bitfield
.zmmword
& t1
.bitfield
.zmmword
))
2172 i
.error
= register_type_mismatch
;
2177 static INLINE
unsigned int
2178 register_number (const reg_entry
*r
)
2180 unsigned int nr
= r
->reg_num
;
2182 if (r
->reg_flags
& RegRex
)
2185 if (r
->reg_flags
& RegVRex
)
2191 static INLINE
unsigned int
2192 mode_from_disp_size (i386_operand_type t
)
2194 if (t
.bitfield
.disp8
)
2196 else if (t
.bitfield
.disp16
2197 || t
.bitfield
.disp32
2198 || t
.bitfield
.disp32s
)
2205 fits_in_signed_byte (addressT num
)
2207 return num
+ 0x80 <= 0xff;
2211 fits_in_unsigned_byte (addressT num
)
2217 fits_in_unsigned_word (addressT num
)
2219 return num
<= 0xffff;
2223 fits_in_signed_word (addressT num
)
2225 return num
+ 0x8000 <= 0xffff;
2229 fits_in_signed_long (addressT num ATTRIBUTE_UNUSED
)
2234 return num
+ 0x80000000 <= 0xffffffff;
2236 } /* fits_in_signed_long() */
2239 fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED
)
2244 return num
<= 0xffffffff;
2246 } /* fits_in_unsigned_long() */
2249 fits_in_disp8 (offsetT num
)
2251 int shift
= i
.memshift
;
2257 mask
= (1 << shift
) - 1;
2259 /* Return 0 if NUM isn't properly aligned. */
2263 /* Check if NUM will fit in 8bit after shift. */
2264 return fits_in_signed_byte (num
>> shift
);
2268 fits_in_imm4 (offsetT num
)
2270 return (num
& 0xf) == num
;
2273 static i386_operand_type
2274 smallest_imm_type (offsetT num
)
2276 i386_operand_type t
;
2278 operand_type_set (&t
, 0);
2279 t
.bitfield
.imm64
= 1;
2281 if (cpu_arch_tune
!= PROCESSOR_I486
&& num
== 1)
2283 /* This code is disabled on the 486 because all the Imm1 forms
2284 in the opcode table are slower on the i486. They're the
2285 versions with the implicitly specified single-position
2286 displacement, which has another syntax if you really want to
2288 t
.bitfield
.imm1
= 1;
2289 t
.bitfield
.imm8
= 1;
2290 t
.bitfield
.imm8s
= 1;
2291 t
.bitfield
.imm16
= 1;
2292 t
.bitfield
.imm32
= 1;
2293 t
.bitfield
.imm32s
= 1;
2295 else if (fits_in_signed_byte (num
))
2297 t
.bitfield
.imm8
= 1;
2298 t
.bitfield
.imm8s
= 1;
2299 t
.bitfield
.imm16
= 1;
2300 t
.bitfield
.imm32
= 1;
2301 t
.bitfield
.imm32s
= 1;
2303 else if (fits_in_unsigned_byte (num
))
2305 t
.bitfield
.imm8
= 1;
2306 t
.bitfield
.imm16
= 1;
2307 t
.bitfield
.imm32
= 1;
2308 t
.bitfield
.imm32s
= 1;
2310 else if (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
2312 t
.bitfield
.imm16
= 1;
2313 t
.bitfield
.imm32
= 1;
2314 t
.bitfield
.imm32s
= 1;
2316 else if (fits_in_signed_long (num
))
2318 t
.bitfield
.imm32
= 1;
2319 t
.bitfield
.imm32s
= 1;
2321 else if (fits_in_unsigned_long (num
))
2322 t
.bitfield
.imm32
= 1;
2328 offset_in_range (offsetT val
, int size
)
2334 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
2335 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
2336 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
2338 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
2344 /* If BFD64, sign extend val for 32bit address mode. */
2345 if (flag_code
!= CODE_64BIT
2346 || i
.prefix
[ADDR_PREFIX
])
2347 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
2348 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
2351 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
2353 char buf1
[40], buf2
[40];
2355 sprint_value (buf1
, val
);
2356 sprint_value (buf2
, val
& mask
);
2357 as_warn (_("%s shortened to %s"), buf1
, buf2
);
2372 a. PREFIX_EXIST if attempting to add a prefix where one from the
2373 same class already exists.
2374 b. PREFIX_LOCK if lock prefix is added.
2375 c. PREFIX_REP if rep/repne prefix is added.
2376 d. PREFIX_DS if ds prefix is added.
2377 e. PREFIX_OTHER if other prefix is added.
2380 static enum PREFIX_GROUP
2381 add_prefix (unsigned int prefix
)
2383 enum PREFIX_GROUP ret
= PREFIX_OTHER
;
2386 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
2387 && flag_code
== CODE_64BIT
)
2389 if ((i
.prefix
[REX_PREFIX
] & prefix
& REX_W
)
2390 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_R
)
2391 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_X
)
2392 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_B
))
2403 case DS_PREFIX_OPCODE
:
2406 case CS_PREFIX_OPCODE
:
2407 case ES_PREFIX_OPCODE
:
2408 case FS_PREFIX_OPCODE
:
2409 case GS_PREFIX_OPCODE
:
2410 case SS_PREFIX_OPCODE
:
2414 case REPNE_PREFIX_OPCODE
:
2415 case REPE_PREFIX_OPCODE
:
2420 case LOCK_PREFIX_OPCODE
:
2429 case ADDR_PREFIX_OPCODE
:
2433 case DATA_PREFIX_OPCODE
:
2437 if (i
.prefix
[q
] != 0)
2445 i
.prefix
[q
] |= prefix
;
2448 as_bad (_("same type of prefix used twice"));
2454 update_code_flag (int value
, int check
)
2456 PRINTF_LIKE ((*as_error
));
2458 flag_code
= (enum flag_code
) value
;
2459 if (flag_code
== CODE_64BIT
)
2461 cpu_arch_flags
.bitfield
.cpu64
= 1;
2462 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2466 cpu_arch_flags
.bitfield
.cpu64
= 0;
2467 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2469 if (value
== CODE_64BIT
&& !cpu_arch_flags
.bitfield
.cpulm
)
2472 as_error
= as_fatal
;
2475 (*as_error
) (_("64bit mode not supported on `%s'."),
2476 cpu_arch_name
? cpu_arch_name
: default_arch
);
2478 if (value
== CODE_32BIT
&& !cpu_arch_flags
.bitfield
.cpui386
)
2481 as_error
= as_fatal
;
2484 (*as_error
) (_("32bit mode not supported on `%s'."),
2485 cpu_arch_name
? cpu_arch_name
: default_arch
);
2487 stackop_size
= '\0';
2491 set_code_flag (int value
)
2493 update_code_flag (value
, 0);
2497 set_16bit_gcc_code_flag (int new_code_flag
)
2499 flag_code
= (enum flag_code
) new_code_flag
;
2500 if (flag_code
!= CODE_16BIT
)
2502 cpu_arch_flags
.bitfield
.cpu64
= 0;
2503 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2504 stackop_size
= LONG_MNEM_SUFFIX
;
2508 set_intel_syntax (int syntax_flag
)
2510 /* Find out if register prefixing is specified. */
2511 int ask_naked_reg
= 0;
2514 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2517 int e
= get_symbol_name (&string
);
2519 if (strcmp (string
, "prefix") == 0)
2521 else if (strcmp (string
, "noprefix") == 0)
2524 as_bad (_("bad argument to syntax directive."));
2525 (void) restore_line_pointer (e
);
2527 demand_empty_rest_of_line ();
2529 intel_syntax
= syntax_flag
;
2531 if (ask_naked_reg
== 0)
2532 allow_naked_reg
= (intel_syntax
2533 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
2535 allow_naked_reg
= (ask_naked_reg
< 0);
2537 expr_set_rank (O_full_ptr
, syntax_flag
? 10 : 0);
2539 identifier_chars
['%'] = intel_syntax
&& allow_naked_reg
? '%' : 0;
2540 identifier_chars
['$'] = intel_syntax
? '$' : 0;
2541 register_prefix
= allow_naked_reg
? "" : "%";
2545 set_intel_mnemonic (int mnemonic_flag
)
2547 intel_mnemonic
= mnemonic_flag
;
2551 set_allow_index_reg (int flag
)
2553 allow_index_reg
= flag
;
2557 set_check (int what
)
2559 enum check_kind
*kind
;
2564 kind
= &operand_check
;
2575 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2578 int e
= get_symbol_name (&string
);
2580 if (strcmp (string
, "none") == 0)
2582 else if (strcmp (string
, "warning") == 0)
2583 *kind
= check_warning
;
2584 else if (strcmp (string
, "error") == 0)
2585 *kind
= check_error
;
2587 as_bad (_("bad argument to %s_check directive."), str
);
2588 (void) restore_line_pointer (e
);
2591 as_bad (_("missing argument for %s_check directive"), str
);
2593 demand_empty_rest_of_line ();
2597 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED
,
2598 i386_cpu_flags new_flag ATTRIBUTE_UNUSED
)
2600 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2601 static const char *arch
;
2603 /* Intel LIOM is only supported on ELF. */
2609 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2610 use default_arch. */
2611 arch
= cpu_arch_name
;
2613 arch
= default_arch
;
2616 /* If we are targeting Intel MCU, we must enable it. */
2617 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_IAMCU
2618 || new_flag
.bitfield
.cpuiamcu
)
2621 /* If we are targeting Intel L1OM, we must enable it. */
2622 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_L1OM
2623 || new_flag
.bitfield
.cpul1om
)
2626 /* If we are targeting Intel K1OM, we must enable it. */
2627 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_K1OM
2628 || new_flag
.bitfield
.cpuk1om
)
2631 as_bad (_("`%s' is not supported on `%s'"), name
, arch
);
2636 set_cpu_arch (int dummy ATTRIBUTE_UNUSED
)
2640 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2643 int e
= get_symbol_name (&string
);
2645 i386_cpu_flags flags
;
2647 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
2649 if (strcmp (string
, cpu_arch
[j
].name
) == 0)
2651 check_cpu_arch_compatible (string
, cpu_arch
[j
].flags
);
2655 cpu_arch_name
= cpu_arch
[j
].name
;
2656 cpu_sub_arch_name
= NULL
;
2657 cpu_arch_flags
= cpu_arch
[j
].flags
;
2658 if (flag_code
== CODE_64BIT
)
2660 cpu_arch_flags
.bitfield
.cpu64
= 1;
2661 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2665 cpu_arch_flags
.bitfield
.cpu64
= 0;
2666 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2668 cpu_arch_isa
= cpu_arch
[j
].type
;
2669 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
2670 if (!cpu_arch_tune_set
)
2672 cpu_arch_tune
= cpu_arch_isa
;
2673 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
2678 flags
= cpu_flags_or (cpu_arch_flags
,
2681 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2683 if (cpu_sub_arch_name
)
2685 char *name
= cpu_sub_arch_name
;
2686 cpu_sub_arch_name
= concat (name
,
2688 (const char *) NULL
);
2692 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
2693 cpu_arch_flags
= flags
;
2694 cpu_arch_isa_flags
= flags
;
2698 = cpu_flags_or (cpu_arch_isa_flags
,
2700 (void) restore_line_pointer (e
);
2701 demand_empty_rest_of_line ();
2706 if (*string
== '.' && j
>= ARRAY_SIZE (cpu_arch
))
2708 /* Disable an ISA extension. */
2709 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
2710 if (strcmp (string
+ 1, cpu_noarch
[j
].name
) == 0)
2712 flags
= cpu_flags_and_not (cpu_arch_flags
,
2713 cpu_noarch
[j
].flags
);
2714 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2716 if (cpu_sub_arch_name
)
2718 char *name
= cpu_sub_arch_name
;
2719 cpu_sub_arch_name
= concat (name
, string
,
2720 (const char *) NULL
);
2724 cpu_sub_arch_name
= xstrdup (string
);
2725 cpu_arch_flags
= flags
;
2726 cpu_arch_isa_flags
= flags
;
2728 (void) restore_line_pointer (e
);
2729 demand_empty_rest_of_line ();
2733 j
= ARRAY_SIZE (cpu_arch
);
2736 if (j
>= ARRAY_SIZE (cpu_arch
))
2737 as_bad (_("no such architecture: `%s'"), string
);
2739 *input_line_pointer
= e
;
2742 as_bad (_("missing cpu architecture"));
2744 no_cond_jump_promotion
= 0;
2745 if (*input_line_pointer
== ','
2746 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
2751 ++input_line_pointer
;
2752 e
= get_symbol_name (&string
);
2754 if (strcmp (string
, "nojumps") == 0)
2755 no_cond_jump_promotion
= 1;
2756 else if (strcmp (string
, "jumps") == 0)
2759 as_bad (_("no such architecture modifier: `%s'"), string
);
2761 (void) restore_line_pointer (e
);
2764 demand_empty_rest_of_line ();
2767 enum bfd_architecture
2770 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2772 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2773 || flag_code
!= CODE_64BIT
)
2774 as_fatal (_("Intel L1OM is 64bit ELF only"));
2775 return bfd_arch_l1om
;
2777 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2779 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2780 || flag_code
!= CODE_64BIT
)
2781 as_fatal (_("Intel K1OM is 64bit ELF only"));
2782 return bfd_arch_k1om
;
2784 else if (cpu_arch_isa
== PROCESSOR_IAMCU
)
2786 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2787 || flag_code
== CODE_64BIT
)
2788 as_fatal (_("Intel MCU is 32bit ELF only"));
2789 return bfd_arch_iamcu
;
2792 return bfd_arch_i386
;
2798 if (!strncmp (default_arch
, "x86_64", 6))
2800 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2802 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2803 || default_arch
[6] != '\0')
2804 as_fatal (_("Intel L1OM is 64bit ELF only"));
2805 return bfd_mach_l1om
;
2807 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2809 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2810 || default_arch
[6] != '\0')
2811 as_fatal (_("Intel K1OM is 64bit ELF only"));
2812 return bfd_mach_k1om
;
2814 else if (default_arch
[6] == '\0')
2815 return bfd_mach_x86_64
;
2817 return bfd_mach_x64_32
;
2819 else if (!strcmp (default_arch
, "i386")
2820 || !strcmp (default_arch
, "iamcu"))
2822 if (cpu_arch_isa
== PROCESSOR_IAMCU
)
2824 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
2825 as_fatal (_("Intel MCU is 32bit ELF only"));
2826 return bfd_mach_i386_iamcu
;
2829 return bfd_mach_i386_i386
;
2832 as_fatal (_("unknown architecture"));
2838 const char *hash_err
;
2840 /* Support pseudo prefixes like {disp32}. */
2841 lex_type
['{'] = LEX_BEGIN_NAME
;
2843 /* Initialize op_hash hash table. */
2844 op_hash
= hash_new ();
2847 const insn_template
*optab
;
2848 templates
*core_optab
;
2850 /* Setup for loop. */
2852 core_optab
= XNEW (templates
);
2853 core_optab
->start
= optab
;
2858 if (optab
->name
== NULL
2859 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
2861 /* different name --> ship out current template list;
2862 add to hash table; & begin anew. */
2863 core_optab
->end
= optab
;
2864 hash_err
= hash_insert (op_hash
,
2866 (void *) core_optab
);
2869 as_fatal (_("can't hash %s: %s"),
2873 if (optab
->name
== NULL
)
2875 core_optab
= XNEW (templates
);
2876 core_optab
->start
= optab
;
2881 /* Initialize reg_hash hash table. */
2882 reg_hash
= hash_new ();
2884 const reg_entry
*regtab
;
2885 unsigned int regtab_size
= i386_regtab_size
;
2887 for (regtab
= i386_regtab
; regtab_size
--; regtab
++)
2889 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (void *) regtab
);
2891 as_fatal (_("can't hash %s: %s"),
2897 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
2902 for (c
= 0; c
< 256; c
++)
2907 mnemonic_chars
[c
] = c
;
2908 register_chars
[c
] = c
;
2909 operand_chars
[c
] = c
;
2911 else if (ISLOWER (c
))
2913 mnemonic_chars
[c
] = c
;
2914 register_chars
[c
] = c
;
2915 operand_chars
[c
] = c
;
2917 else if (ISUPPER (c
))
2919 mnemonic_chars
[c
] = TOLOWER (c
);
2920 register_chars
[c
] = mnemonic_chars
[c
];
2921 operand_chars
[c
] = c
;
2923 else if (c
== '{' || c
== '}')
2925 mnemonic_chars
[c
] = c
;
2926 operand_chars
[c
] = c
;
2929 if (ISALPHA (c
) || ISDIGIT (c
))
2930 identifier_chars
[c
] = c
;
2933 identifier_chars
[c
] = c
;
2934 operand_chars
[c
] = c
;
2939 identifier_chars
['@'] = '@';
2942 identifier_chars
['?'] = '?';
2943 operand_chars
['?'] = '?';
2945 digit_chars
['-'] = '-';
2946 mnemonic_chars
['_'] = '_';
2947 mnemonic_chars
['-'] = '-';
2948 mnemonic_chars
['.'] = '.';
2949 identifier_chars
['_'] = '_';
2950 identifier_chars
['.'] = '.';
2952 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
2953 operand_chars
[(unsigned char) *p
] = *p
;
2956 if (flag_code
== CODE_64BIT
)
2958 #if defined (OBJ_COFF) && defined (TE_PE)
2959 x86_dwarf2_return_column
= (OUTPUT_FLAVOR
== bfd_target_coff_flavour
2962 x86_dwarf2_return_column
= 16;
2964 x86_cie_data_alignment
= -8;
2968 x86_dwarf2_return_column
= 8;
2969 x86_cie_data_alignment
= -4;
2974 i386_print_statistics (FILE *file
)
2976 hash_print_statistics (file
, "i386 opcode", op_hash
);
2977 hash_print_statistics (file
, "i386 register", reg_hash
);
2982 /* Debugging routines for md_assemble. */
2983 static void pte (insn_template
*);
2984 static void pt (i386_operand_type
);
2985 static void pe (expressionS
*);
2986 static void ps (symbolS
*);
2989 pi (char *line
, i386_insn
*x
)
2993 fprintf (stdout
, "%s: template ", line
);
2995 fprintf (stdout
, " address: base %s index %s scale %x\n",
2996 x
->base_reg
? x
->base_reg
->reg_name
: "none",
2997 x
->index_reg
? x
->index_reg
->reg_name
: "none",
2998 x
->log2_scale_factor
);
2999 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
3000 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
3001 fprintf (stdout
, " sib: base %x index %x scale %x\n",
3002 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
3003 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
3004 (x
->rex
& REX_W
) != 0,
3005 (x
->rex
& REX_R
) != 0,
3006 (x
->rex
& REX_X
) != 0,
3007 (x
->rex
& REX_B
) != 0);
3008 for (j
= 0; j
< x
->operands
; j
++)
3010 fprintf (stdout
, " #%d: ", j
+ 1);
3012 fprintf (stdout
, "\n");
3013 if (x
->types
[j
].bitfield
.reg
3014 || x
->types
[j
].bitfield
.regmmx
3015 || x
->types
[j
].bitfield
.regsimd
3016 || x
->types
[j
].bitfield
.sreg2
3017 || x
->types
[j
].bitfield
.sreg3
3018 || x
->types
[j
].bitfield
.control
3019 || x
->types
[j
].bitfield
.debug
3020 || x
->types
[j
].bitfield
.test
)
3021 fprintf (stdout
, "%s\n", x
->op
[j
].regs
->reg_name
);
3022 if (operand_type_check (x
->types
[j
], imm
))
3024 if (operand_type_check (x
->types
[j
], disp
))
3025 pe (x
->op
[j
].disps
);
3030 pte (insn_template
*t
)
3033 fprintf (stdout
, " %d operands ", t
->operands
);
3034 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
3035 if (t
->extension_opcode
!= None
)
3036 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
3037 if (t
->opcode_modifier
.d
)
3038 fprintf (stdout
, "D");
3039 if (t
->opcode_modifier
.w
)
3040 fprintf (stdout
, "W");
3041 fprintf (stdout
, "\n");
3042 for (j
= 0; j
< t
->operands
; j
++)
3044 fprintf (stdout
, " #%d type ", j
+ 1);
3045 pt (t
->operand_types
[j
]);
3046 fprintf (stdout
, "\n");
3053 fprintf (stdout
, " operation %d\n", e
->X_op
);
3054 fprintf (stdout
, " add_number %ld (%lx)\n",
3055 (long) e
->X_add_number
, (long) e
->X_add_number
);
3056 if (e
->X_add_symbol
)
3058 fprintf (stdout
, " add_symbol ");
3059 ps (e
->X_add_symbol
);
3060 fprintf (stdout
, "\n");
3064 fprintf (stdout
, " op_symbol ");
3065 ps (e
->X_op_symbol
);
3066 fprintf (stdout
, "\n");
3073 fprintf (stdout
, "%s type %s%s",
3075 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
3076 segment_name (S_GET_SEGMENT (s
)));
3079 static struct type_name
3081 i386_operand_type mask
;
3084 const type_names
[] =
3086 { OPERAND_TYPE_REG8
, "r8" },
3087 { OPERAND_TYPE_REG16
, "r16" },
3088 { OPERAND_TYPE_REG32
, "r32" },
3089 { OPERAND_TYPE_REG64
, "r64" },
3090 { OPERAND_TYPE_IMM8
, "i8" },
3091 { OPERAND_TYPE_IMM8
, "i8s" },
3092 { OPERAND_TYPE_IMM16
, "i16" },
3093 { OPERAND_TYPE_IMM32
, "i32" },
3094 { OPERAND_TYPE_IMM32S
, "i32s" },
3095 { OPERAND_TYPE_IMM64
, "i64" },
3096 { OPERAND_TYPE_IMM1
, "i1" },
3097 { OPERAND_TYPE_BASEINDEX
, "BaseIndex" },
3098 { OPERAND_TYPE_DISP8
, "d8" },
3099 { OPERAND_TYPE_DISP16
, "d16" },
3100 { OPERAND_TYPE_DISP32
, "d32" },
3101 { OPERAND_TYPE_DISP32S
, "d32s" },
3102 { OPERAND_TYPE_DISP64
, "d64" },
3103 { OPERAND_TYPE_INOUTPORTREG
, "InOutPortReg" },
3104 { OPERAND_TYPE_SHIFTCOUNT
, "ShiftCount" },
3105 { OPERAND_TYPE_CONTROL
, "control reg" },
3106 { OPERAND_TYPE_TEST
, "test reg" },
3107 { OPERAND_TYPE_DEBUG
, "debug reg" },
3108 { OPERAND_TYPE_FLOATREG
, "FReg" },
3109 { OPERAND_TYPE_FLOATACC
, "FAcc" },
3110 { OPERAND_TYPE_SREG2
, "SReg2" },
3111 { OPERAND_TYPE_SREG3
, "SReg3" },
3112 { OPERAND_TYPE_ACC
, "Acc" },
3113 { OPERAND_TYPE_JUMPABSOLUTE
, "Jump Absolute" },
3114 { OPERAND_TYPE_REGMMX
, "rMMX" },
3115 { OPERAND_TYPE_REGXMM
, "rXMM" },
3116 { OPERAND_TYPE_REGYMM
, "rYMM" },
3117 { OPERAND_TYPE_REGZMM
, "rZMM" },
3118 { OPERAND_TYPE_REGMASK
, "Mask reg" },
3119 { OPERAND_TYPE_ESSEG
, "es" },
3123 pt (i386_operand_type t
)
3126 i386_operand_type a
;
3128 for (j
= 0; j
< ARRAY_SIZE (type_names
); j
++)
3130 a
= operand_type_and (t
, type_names
[j
].mask
);
3131 if (!operand_type_all_zero (&a
))
3132 fprintf (stdout
, "%s, ", type_names
[j
].name
);
3137 #endif /* DEBUG386 */
3139 static bfd_reloc_code_real_type
3140 reloc (unsigned int size
,
3143 bfd_reloc_code_real_type other
)
3145 if (other
!= NO_RELOC
)
3147 reloc_howto_type
*rel
;
3152 case BFD_RELOC_X86_64_GOT32
:
3153 return BFD_RELOC_X86_64_GOT64
;
3155 case BFD_RELOC_X86_64_GOTPLT64
:
3156 return BFD_RELOC_X86_64_GOTPLT64
;
3158 case BFD_RELOC_X86_64_PLTOFF64
:
3159 return BFD_RELOC_X86_64_PLTOFF64
;
3161 case BFD_RELOC_X86_64_GOTPC32
:
3162 other
= BFD_RELOC_X86_64_GOTPC64
;
3164 case BFD_RELOC_X86_64_GOTPCREL
:
3165 other
= BFD_RELOC_X86_64_GOTPCREL64
;
3167 case BFD_RELOC_X86_64_TPOFF32
:
3168 other
= BFD_RELOC_X86_64_TPOFF64
;
3170 case BFD_RELOC_X86_64_DTPOFF32
:
3171 other
= BFD_RELOC_X86_64_DTPOFF64
;
3177 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3178 if (other
== BFD_RELOC_SIZE32
)
3181 other
= BFD_RELOC_SIZE64
;
3184 as_bad (_("there are no pc-relative size relocations"));
3190 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
3191 if (size
== 4 && (flag_code
!= CODE_64BIT
|| disallow_64bit_reloc
))
3194 rel
= bfd_reloc_type_lookup (stdoutput
, other
);
3196 as_bad (_("unknown relocation (%u)"), other
);
3197 else if (size
!= bfd_get_reloc_size (rel
))
3198 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
3199 bfd_get_reloc_size (rel
),
3201 else if (pcrel
&& !rel
->pc_relative
)
3202 as_bad (_("non-pc-relative relocation for pc-relative field"));
3203 else if ((rel
->complain_on_overflow
== complain_overflow_signed
3205 || (rel
->complain_on_overflow
== complain_overflow_unsigned
3207 as_bad (_("relocated field and relocation type differ in signedness"));
3216 as_bad (_("there are no unsigned pc-relative relocations"));
3219 case 1: return BFD_RELOC_8_PCREL
;
3220 case 2: return BFD_RELOC_16_PCREL
;
3221 case 4: return BFD_RELOC_32_PCREL
;
3222 case 8: return BFD_RELOC_64_PCREL
;
3224 as_bad (_("cannot do %u byte pc-relative relocation"), size
);
3231 case 4: return BFD_RELOC_X86_64_32S
;
3236 case 1: return BFD_RELOC_8
;
3237 case 2: return BFD_RELOC_16
;
3238 case 4: return BFD_RELOC_32
;
3239 case 8: return BFD_RELOC_64
;
3241 as_bad (_("cannot do %s %u byte relocation"),
3242 sign
> 0 ? "signed" : "unsigned", size
);
3248 /* Here we decide which fixups can be adjusted to make them relative to
3249 the beginning of the section instead of the symbol. Basically we need
3250 to make sure that the dynamic relocations are done correctly, so in
3251 some cases we force the original symbol to be used. */
3254 tc_i386_fix_adjustable (fixS
*fixP ATTRIBUTE_UNUSED
)
3256 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3260 /* Don't adjust pc-relative references to merge sections in 64-bit
3262 if (use_rela_relocations
3263 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
3267 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
3268 and changed later by validate_fix. */
3269 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
3270 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
3273 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
3274 for size relocations. */
3275 if (fixP
->fx_r_type
== BFD_RELOC_SIZE32
3276 || fixP
->fx_r_type
== BFD_RELOC_SIZE64
3277 || fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
3278 || fixP
->fx_r_type
== BFD_RELOC_386_PLT32
3279 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
3280 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32X
3281 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
3282 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
3283 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
3284 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
3285 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
3286 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
3287 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
3288 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
3289 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTDESC
3290 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_DESC_CALL
3291 || fixP
->fx_r_type
== BFD_RELOC_X86_64_PLT32
3292 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
3293 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
3294 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCRELX
3295 || fixP
->fx_r_type
== BFD_RELOC_X86_64_REX_GOTPCRELX
3296 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
3297 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
3298 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
3299 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
3300 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
3301 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
3302 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
3303 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
3304 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPC32_TLSDESC
3305 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSDESC_CALL
3306 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
3307 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
3314 intel_float_operand (const char *mnemonic
)
3316 /* Note that the value returned is meaningful only for opcodes with (memory)
3317 operands, hence the code here is free to improperly handle opcodes that
3318 have no operands (for better performance and smaller code). */
3320 if (mnemonic
[0] != 'f')
3321 return 0; /* non-math */
3323 switch (mnemonic
[1])
3325 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
3326 the fs segment override prefix not currently handled because no
3327 call path can make opcodes without operands get here */
3329 return 2 /* integer op */;
3331 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
3332 return 3; /* fldcw/fldenv */
3335 if (mnemonic
[2] != 'o' /* fnop */)
3336 return 3; /* non-waiting control op */
3339 if (mnemonic
[2] == 's')
3340 return 3; /* frstor/frstpm */
3343 if (mnemonic
[2] == 'a')
3344 return 3; /* fsave */
3345 if (mnemonic
[2] == 't')
3347 switch (mnemonic
[3])
3349 case 'c': /* fstcw */
3350 case 'd': /* fstdw */
3351 case 'e': /* fstenv */
3352 case 's': /* fsts[gw] */
3358 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
3359 return 0; /* fxsave/fxrstor are not really math ops */
3366 /* Build the VEX prefix. */
3369 build_vex_prefix (const insn_template
*t
)
3371 unsigned int register_specifier
;
3372 unsigned int implied_prefix
;
3373 unsigned int vector_length
;
3376 /* Check register specifier. */
3377 if (i
.vex
.register_specifier
)
3379 register_specifier
=
3380 ~register_number (i
.vex
.register_specifier
) & 0xf;
3381 gas_assert ((i
.vex
.register_specifier
->reg_flags
& RegVRex
) == 0);
3384 register_specifier
= 0xf;
3386 /* Use 2-byte VEX prefix by swapping destination and source operand
3387 if there are more than 1 register operand. */
3388 if (i
.reg_operands
> 1
3389 && i
.vec_encoding
!= vex_encoding_vex3
3390 && i
.dir_encoding
== dir_encoding_default
3391 && i
.operands
== i
.reg_operands
3392 && operand_type_equal (&i
.types
[0], &i
.types
[i
.operands
- 1])
3393 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3394 && (i
.tm
.opcode_modifier
.load
|| i
.tm
.opcode_modifier
.d
)
3397 unsigned int xchg
= i
.operands
- 1;
3398 union i386_op temp_op
;
3399 i386_operand_type temp_type
;
3401 temp_type
= i
.types
[xchg
];
3402 i
.types
[xchg
] = i
.types
[0];
3403 i
.types
[0] = temp_type
;
3404 temp_op
= i
.op
[xchg
];
3405 i
.op
[xchg
] = i
.op
[0];
3408 gas_assert (i
.rm
.mode
== 3);
3412 i
.rm
.regmem
= i
.rm
.reg
;
3415 if (i
.tm
.opcode_modifier
.d
)
3416 i
.tm
.base_opcode
^= (i
.tm
.base_opcode
& 0xee) != 0x6e
3417 ? Opcode_SIMD_FloatD
: Opcode_SIMD_IntD
;
3418 else /* Use the next insn. */
3422 if (i
.tm
.opcode_modifier
.vex
== VEXScalar
)
3423 vector_length
= avxscalar
;
3424 else if (i
.tm
.opcode_modifier
.vex
== VEX256
)
3430 /* Determine vector length from the last multi-length vector
3433 for (op
= t
->operands
; op
--;)
3434 if (t
->operand_types
[op
].bitfield
.xmmword
3435 && t
->operand_types
[op
].bitfield
.ymmword
3436 && i
.types
[op
].bitfield
.ymmword
)
3443 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3448 case DATA_PREFIX_OPCODE
:
3451 case REPE_PREFIX_OPCODE
:
3454 case REPNE_PREFIX_OPCODE
:
3461 /* Check the REX.W bit and VEXW. */
3462 if (i
.tm
.opcode_modifier
.vexw
== VEXWIG
)
3463 w
= (vexwig
== vexw1
|| (i
.rex
& REX_W
)) ? 1 : 0;
3464 else if (i
.tm
.opcode_modifier
.vexw
)
3465 w
= i
.tm
.opcode_modifier
.vexw
== VEXW1
? 1 : 0;
3467 w
= (flag_code
== CODE_64BIT
? i
.rex
& REX_W
: vexwig
== vexw1
) ? 1 : 0;
3469 /* Use 2-byte VEX prefix if possible. */
3471 && i
.vec_encoding
!= vex_encoding_vex3
3472 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3473 && (i
.rex
& (REX_W
| REX_X
| REX_B
)) == 0)
3475 /* 2-byte VEX prefix. */
3479 i
.vex
.bytes
[0] = 0xc5;
3481 /* Check the REX.R bit. */
3482 r
= (i
.rex
& REX_R
) ? 0 : 1;
3483 i
.vex
.bytes
[1] = (r
<< 7
3484 | register_specifier
<< 3
3485 | vector_length
<< 2
3490 /* 3-byte VEX prefix. */
3495 switch (i
.tm
.opcode_modifier
.vexopcode
)
3499 i
.vex
.bytes
[0] = 0xc4;
3503 i
.vex
.bytes
[0] = 0xc4;
3507 i
.vex
.bytes
[0] = 0xc4;
3511 i
.vex
.bytes
[0] = 0x8f;
3515 i
.vex
.bytes
[0] = 0x8f;
3519 i
.vex
.bytes
[0] = 0x8f;
3525 /* The high 3 bits of the second VEX byte are 1's compliment
3526 of RXB bits from REX. */
3527 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3529 i
.vex
.bytes
[2] = (w
<< 7
3530 | register_specifier
<< 3
3531 | vector_length
<< 2
3536 static INLINE bfd_boolean
3537 is_evex_encoding (const insn_template
*t
)
3539 return t
->opcode_modifier
.evex
|| t
->opcode_modifier
.disp8memshift
3540 || t
->opcode_modifier
.broadcast
|| t
->opcode_modifier
.masking
3541 || t
->opcode_modifier
.staticrounding
|| t
->opcode_modifier
.sae
;
3544 static INLINE bfd_boolean
3545 is_any_vex_encoding (const insn_template
*t
)
3547 return t
->opcode_modifier
.vex
|| t
->opcode_modifier
.vexopcode
3548 || is_evex_encoding (t
);
3551 /* Build the EVEX prefix. */
3554 build_evex_prefix (void)
3556 unsigned int register_specifier
;
3557 unsigned int implied_prefix
;
3559 rex_byte vrex_used
= 0;
3561 /* Check register specifier. */
3562 if (i
.vex
.register_specifier
)
3564 gas_assert ((i
.vrex
& REX_X
) == 0);
3566 register_specifier
= i
.vex
.register_specifier
->reg_num
;
3567 if ((i
.vex
.register_specifier
->reg_flags
& RegRex
))
3568 register_specifier
+= 8;
3569 /* The upper 16 registers are encoded in the fourth byte of the
3571 if (!(i
.vex
.register_specifier
->reg_flags
& RegVRex
))
3572 i
.vex
.bytes
[3] = 0x8;
3573 register_specifier
= ~register_specifier
& 0xf;
3577 register_specifier
= 0xf;
3579 /* Encode upper 16 vector index register in the fourth byte of
3581 if (!(i
.vrex
& REX_X
))
3582 i
.vex
.bytes
[3] = 0x8;
3587 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3592 case DATA_PREFIX_OPCODE
:
3595 case REPE_PREFIX_OPCODE
:
3598 case REPNE_PREFIX_OPCODE
:
3605 /* 4 byte EVEX prefix. */
3607 i
.vex
.bytes
[0] = 0x62;
3610 switch (i
.tm
.opcode_modifier
.vexopcode
)
3626 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3628 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3630 /* The fifth bit of the second EVEX byte is 1's compliment of the
3631 REX_R bit in VREX. */
3632 if (!(i
.vrex
& REX_R
))
3633 i
.vex
.bytes
[1] |= 0x10;
3637 if ((i
.reg_operands
+ i
.imm_operands
) == i
.operands
)
3639 /* When all operands are registers, the REX_X bit in REX is not
3640 used. We reuse it to encode the upper 16 registers, which is
3641 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3642 as 1's compliment. */
3643 if ((i
.vrex
& REX_B
))
3646 i
.vex
.bytes
[1] &= ~0x40;
3650 /* EVEX instructions shouldn't need the REX prefix. */
3651 i
.vrex
&= ~vrex_used
;
3652 gas_assert (i
.vrex
== 0);
3654 /* Check the REX.W bit and VEXW. */
3655 if (i
.tm
.opcode_modifier
.vexw
== VEXWIG
)
3656 w
= (evexwig
== evexw1
|| (i
.rex
& REX_W
)) ? 1 : 0;
3657 else if (i
.tm
.opcode_modifier
.vexw
)
3658 w
= i
.tm
.opcode_modifier
.vexw
== VEXW1
? 1 : 0;
3660 w
= (flag_code
== CODE_64BIT
? i
.rex
& REX_W
: evexwig
== evexw1
) ? 1 : 0;
3662 /* Encode the U bit. */
3663 implied_prefix
|= 0x4;
3665 /* The third byte of the EVEX prefix. */
3666 i
.vex
.bytes
[2] = (w
<< 7 | register_specifier
<< 3 | implied_prefix
);
3668 /* The fourth byte of the EVEX prefix. */
3669 /* The zeroing-masking bit. */
3670 if (i
.mask
&& i
.mask
->zeroing
)
3671 i
.vex
.bytes
[3] |= 0x80;
3673 /* Don't always set the broadcast bit if there is no RC. */
3676 /* Encode the vector length. */
3677 unsigned int vec_length
;
3679 if (!i
.tm
.opcode_modifier
.evex
3680 || i
.tm
.opcode_modifier
.evex
== EVEXDYN
)
3684 /* Determine vector length from the last multi-length vector
3687 for (op
= i
.operands
; op
--;)
3688 if (i
.tm
.operand_types
[op
].bitfield
.xmmword
3689 + i
.tm
.operand_types
[op
].bitfield
.ymmword
3690 + i
.tm
.operand_types
[op
].bitfield
.zmmword
> 1)
3692 if (i
.types
[op
].bitfield
.zmmword
)
3694 i
.tm
.opcode_modifier
.evex
= EVEX512
;
3697 else if (i
.types
[op
].bitfield
.ymmword
)
3699 i
.tm
.opcode_modifier
.evex
= EVEX256
;
3702 else if (i
.types
[op
].bitfield
.xmmword
)
3704 i
.tm
.opcode_modifier
.evex
= EVEX128
;
3707 else if (i
.broadcast
&& (int) op
== i
.broadcast
->operand
)
3709 switch (i
.broadcast
->bytes
)
3712 i
.tm
.opcode_modifier
.evex
= EVEX512
;
3715 i
.tm
.opcode_modifier
.evex
= EVEX256
;
3718 i
.tm
.opcode_modifier
.evex
= EVEX128
;
3727 if (op
>= MAX_OPERANDS
)
3731 switch (i
.tm
.opcode_modifier
.evex
)
3733 case EVEXLIG
: /* LL' is ignored */
3734 vec_length
= evexlig
<< 5;
3737 vec_length
= 0 << 5;
3740 vec_length
= 1 << 5;
3743 vec_length
= 2 << 5;
3749 i
.vex
.bytes
[3] |= vec_length
;
3750 /* Encode the broadcast bit. */
3752 i
.vex
.bytes
[3] |= 0x10;
3756 if (i
.rounding
->type
!= saeonly
)
3757 i
.vex
.bytes
[3] |= 0x10 | (i
.rounding
->type
<< 5);
3759 i
.vex
.bytes
[3] |= 0x10 | (evexrcig
<< 5);
3762 if (i
.mask
&& i
.mask
->mask
)
3763 i
.vex
.bytes
[3] |= i
.mask
->mask
->reg_num
;
3767 process_immext (void)
3771 if ((i
.tm
.cpu_flags
.bitfield
.cpusse3
|| i
.tm
.cpu_flags
.bitfield
.cpusvme
)
3774 /* MONITOR/MWAIT as well as SVME instructions have fixed operands
3775 with an opcode suffix which is coded in the same place as an
3776 8-bit immediate field would be.
3777 Here we check those operands and remove them afterwards. */
3780 for (x
= 0; x
< i
.operands
; x
++)
3781 if (register_number (i
.op
[x
].regs
) != x
)
3782 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3783 register_prefix
, i
.op
[x
].regs
->reg_name
, x
+ 1,
3789 if (i
.tm
.cpu_flags
.bitfield
.cpumwaitx
&& i
.operands
> 0)
3791 /* MONITORX/MWAITX instructions have fixed operands with an opcode
3792 suffix which is coded in the same place as an 8-bit immediate
3794 Here we check those operands and remove them afterwards. */
3797 if (i
.operands
!= 3)
3800 for (x
= 0; x
< 2; x
++)
3801 if (register_number (i
.op
[x
].regs
) != x
)
3802 goto bad_register_operand
;
3804 /* Check for third operand for mwaitx/monitorx insn. */
3805 if (register_number (i
.op
[x
].regs
)
3806 != (x
+ (i
.tm
.extension_opcode
== 0xfb)))
3808 bad_register_operand
:
3809 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3810 register_prefix
, i
.op
[x
].regs
->reg_name
, x
+1,
3817 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
3818 which is coded in the same place as an 8-bit immediate field
3819 would be. Here we fake an 8-bit immediate operand from the
3820 opcode suffix stored in tm.extension_opcode.
3822 AVX instructions also use this encoding, for some of
3823 3 argument instructions. */
3825 gas_assert (i
.imm_operands
<= 1
3827 || (is_any_vex_encoding (&i
.tm
)
3828 && i
.operands
<= 4)));
3830 exp
= &im_expressions
[i
.imm_operands
++];
3831 i
.op
[i
.operands
].imms
= exp
;
3832 i
.types
[i
.operands
] = imm8
;
3834 exp
->X_op
= O_constant
;
3835 exp
->X_add_number
= i
.tm
.extension_opcode
;
3836 i
.tm
.extension_opcode
= None
;
3843 switch (i
.tm
.opcode_modifier
.hleprefixok
)
3848 as_bad (_("invalid instruction `%s' after `%s'"),
3849 i
.tm
.name
, i
.hle_prefix
);
3852 if (i
.prefix
[LOCK_PREFIX
])
3854 as_bad (_("missing `lock' with `%s'"), i
.hle_prefix
);
3858 case HLEPrefixRelease
:
3859 if (i
.prefix
[HLE_PREFIX
] != XRELEASE_PREFIX_OPCODE
)
3861 as_bad (_("instruction `%s' after `xacquire' not allowed"),
3865 if (i
.mem_operands
== 0
3866 || !operand_type_check (i
.types
[i
.operands
- 1], anymem
))
3868 as_bad (_("memory destination needed for instruction `%s'"
3869 " after `xrelease'"), i
.tm
.name
);
3876 /* Try the shortest encoding by shortening operand size. */
3879 optimize_encoding (void)
3883 if (optimize_for_space
3884 && i
.reg_operands
== 1
3885 && i
.imm_operands
== 1
3886 && !i
.types
[1].bitfield
.byte
3887 && i
.op
[0].imms
->X_op
== O_constant
3888 && fits_in_imm7 (i
.op
[0].imms
->X_add_number
)
3889 && ((i
.tm
.base_opcode
== 0xa8
3890 && i
.tm
.extension_opcode
== None
)
3891 || (i
.tm
.base_opcode
== 0xf6
3892 && i
.tm
.extension_opcode
== 0x0)))
3895 test $imm7, %r64/%r32/%r16 -> test $imm7, %r8
3897 unsigned int base_regnum
= i
.op
[1].regs
->reg_num
;
3898 if (flag_code
== CODE_64BIT
|| base_regnum
< 4)
3900 i
.types
[1].bitfield
.byte
= 1;
3901 /* Ignore the suffix. */
3903 if (base_regnum
>= 4
3904 && !(i
.op
[1].regs
->reg_flags
& RegRex
))
3906 /* Handle SP, BP, SI and DI registers. */
3907 if (i
.types
[1].bitfield
.word
)
3909 else if (i
.types
[1].bitfield
.dword
)
3917 else if (flag_code
== CODE_64BIT
3918 && ((i
.types
[1].bitfield
.qword
3919 && i
.reg_operands
== 1
3920 && i
.imm_operands
== 1
3921 && i
.op
[0].imms
->X_op
== O_constant
3922 && ((i
.tm
.base_opcode
== 0xb0
3923 && i
.tm
.extension_opcode
== None
3924 && fits_in_unsigned_long (i
.op
[0].imms
->X_add_number
))
3925 || (fits_in_imm31 (i
.op
[0].imms
->X_add_number
)
3926 && (((i
.tm
.base_opcode
== 0x24
3927 || i
.tm
.base_opcode
== 0xa8)
3928 && i
.tm
.extension_opcode
== None
)
3929 || (i
.tm
.base_opcode
== 0x80
3930 && i
.tm
.extension_opcode
== 0x4)
3931 || ((i
.tm
.base_opcode
== 0xf6
3932 || i
.tm
.base_opcode
== 0xc6)
3933 && i
.tm
.extension_opcode
== 0x0)))))
3934 || (i
.types
[0].bitfield
.qword
3935 && ((i
.reg_operands
== 2
3936 && i
.op
[0].regs
== i
.op
[1].regs
3937 && ((i
.tm
.base_opcode
== 0x30
3938 || i
.tm
.base_opcode
== 0x28)
3939 && i
.tm
.extension_opcode
== None
))
3940 || (i
.reg_operands
== 1
3942 && i
.tm
.base_opcode
== 0x30
3943 && i
.tm
.extension_opcode
== None
)))))
3946 andq $imm31, %r64 -> andl $imm31, %r32
3947 testq $imm31, %r64 -> testl $imm31, %r32
3948 xorq %r64, %r64 -> xorl %r32, %r32
3949 subq %r64, %r64 -> subl %r32, %r32
3950 movq $imm31, %r64 -> movl $imm31, %r32
3951 movq $imm32, %r64 -> movl $imm32, %r32
3953 i
.tm
.opcode_modifier
.norex64
= 1;
3954 if (i
.tm
.base_opcode
== 0xb0 || i
.tm
.base_opcode
== 0xc6)
3957 movq $imm31, %r64 -> movl $imm31, %r32
3958 movq $imm32, %r64 -> movl $imm32, %r32
3960 i
.tm
.operand_types
[0].bitfield
.imm32
= 1;
3961 i
.tm
.operand_types
[0].bitfield
.imm32s
= 0;
3962 i
.tm
.operand_types
[0].bitfield
.imm64
= 0;
3963 i
.types
[0].bitfield
.imm32
= 1;
3964 i
.types
[0].bitfield
.imm32s
= 0;
3965 i
.types
[0].bitfield
.imm64
= 0;
3966 i
.types
[1].bitfield
.dword
= 1;
3967 i
.types
[1].bitfield
.qword
= 0;
3968 if (i
.tm
.base_opcode
== 0xc6)
3971 movq $imm31, %r64 -> movl $imm31, %r32
3973 i
.tm
.base_opcode
= 0xb0;
3974 i
.tm
.extension_opcode
= None
;
3975 i
.tm
.opcode_modifier
.shortform
= 1;
3976 i
.tm
.opcode_modifier
.modrm
= 0;
3980 else if (i
.reg_operands
== 3
3981 && i
.op
[0].regs
== i
.op
[1].regs
3982 && !i
.types
[2].bitfield
.xmmword
3983 && (i
.tm
.opcode_modifier
.vex
3984 || ((!i
.mask
|| i
.mask
->zeroing
)
3986 && is_evex_encoding (&i
.tm
)
3987 && (i
.vec_encoding
!= vex_encoding_evex
3988 || cpu_arch_flags
.bitfield
.cpuavx
3989 || cpu_arch_isa_flags
.bitfield
.cpuavx
3990 || cpu_arch_flags
.bitfield
.cpuavx512vl
3991 || cpu_arch_isa_flags
.bitfield
.cpuavx512vl
3992 || i
.tm
.cpu_flags
.bitfield
.cpuavx512vl
3993 || (i
.tm
.operand_types
[2].bitfield
.zmmword
3994 && i
.types
[2].bitfield
.ymmword
))))
3995 && ((i
.tm
.base_opcode
== 0x55
3996 || i
.tm
.base_opcode
== 0x6655
3997 || i
.tm
.base_opcode
== 0x66df
3998 || i
.tm
.base_opcode
== 0x57
3999 || i
.tm
.base_opcode
== 0x6657
4000 || i
.tm
.base_opcode
== 0x66ef
4001 || i
.tm
.base_opcode
== 0x66f8
4002 || i
.tm
.base_opcode
== 0x66f9
4003 || i
.tm
.base_opcode
== 0x66fa
4004 || i
.tm
.base_opcode
== 0x66fb
4005 || i
.tm
.base_opcode
== 0x42
4006 || i
.tm
.base_opcode
== 0x6642
4007 || i
.tm
.base_opcode
== 0x47
4008 || i
.tm
.base_opcode
== 0x6647)
4009 && i
.tm
.extension_opcode
== None
))
4012 VOP, one of vandnps, vandnpd, vxorps, vxorpd, vpsubb, vpsubd,
4014 EVEX VOP %zmmM, %zmmM, %zmmN
4015 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
4016 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4017 EVEX VOP %ymmM, %ymmM, %ymmN
4018 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
4019 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4020 VEX VOP %ymmM, %ymmM, %ymmN
4021 -> VEX VOP %xmmM, %xmmM, %xmmN
4022 VOP, one of vpandn and vpxor:
4023 VEX VOP %ymmM, %ymmM, %ymmN
4024 -> VEX VOP %xmmM, %xmmM, %xmmN
4025 VOP, one of vpandnd and vpandnq:
4026 EVEX VOP %zmmM, %zmmM, %zmmN
4027 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
4028 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4029 EVEX VOP %ymmM, %ymmM, %ymmN
4030 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
4031 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4032 VOP, one of vpxord and vpxorq:
4033 EVEX VOP %zmmM, %zmmM, %zmmN
4034 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
4035 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4036 EVEX VOP %ymmM, %ymmM, %ymmN
4037 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
4038 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4039 VOP, one of kxord and kxorq:
4040 VEX VOP %kM, %kM, %kN
4041 -> VEX kxorw %kM, %kM, %kN
4042 VOP, one of kandnd and kandnq:
4043 VEX VOP %kM, %kM, %kN
4044 -> VEX kandnw %kM, %kM, %kN
4046 if (is_evex_encoding (&i
.tm
))
4048 if (i
.vec_encoding
!= vex_encoding_evex
4049 && (cpu_arch_flags
.bitfield
.cpuavx
4050 || cpu_arch_isa_flags
.bitfield
.cpuavx
))
4052 i
.tm
.opcode_modifier
.vex
= VEX128
;
4053 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4054 i
.tm
.opcode_modifier
.evex
= 0;
4056 else if (optimize
> 1
4057 && (cpu_arch_flags
.bitfield
.cpuavx512vl
4058 || cpu_arch_isa_flags
.bitfield
.cpuavx512vl
))
4059 i
.tm
.opcode_modifier
.evex
= EVEX128
;
4063 else if (i
.tm
.operand_types
[0].bitfield
.regmask
)
4065 i
.tm
.base_opcode
&= 0xff;
4066 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4069 i
.tm
.opcode_modifier
.vex
= VEX128
;
4071 if (i
.tm
.opcode_modifier
.vex
)
4072 for (j
= 0; j
< 3; j
++)
4074 i
.types
[j
].bitfield
.xmmword
= 1;
4075 i
.types
[j
].bitfield
.ymmword
= 0;
4078 else if ((cpu_arch_flags
.bitfield
.cpuavx
4079 || cpu_arch_isa_flags
.bitfield
.cpuavx
)
4080 && i
.vec_encoding
!= vex_encoding_evex
4081 && !i
.types
[0].bitfield
.zmmword
4083 && is_evex_encoding (&i
.tm
)
4084 && (i
.tm
.base_opcode
== 0x666f
4085 || (i
.tm
.base_opcode
^ Opcode_SIMD_IntD
) == 0x666f
4086 || i
.tm
.base_opcode
== 0xf36f
4087 || (i
.tm
.base_opcode
^ Opcode_SIMD_IntD
) == 0xf36f
4088 || i
.tm
.base_opcode
== 0xf26f
4089 || (i
.tm
.base_opcode
^ Opcode_SIMD_IntD
) == 0xf26f)
4090 && i
.tm
.extension_opcode
== None
)
4093 VOP, one of vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16,
4094 vmovdqu32 and vmovdqu64:
4095 EVEX VOP %xmmM, %xmmN
4096 -> VEX vmovdqa|vmovdqu %xmmM, %xmmN (M and N < 16)
4097 EVEX VOP %ymmM, %ymmN
4098 -> VEX vmovdqa|vmovdqu %ymmM, %ymmN (M and N < 16)
4100 -> VEX vmovdqa|vmovdqu %xmmM, mem (M < 16)
4102 -> VEX vmovdqa|vmovdqu %ymmM, mem (M < 16)
4104 -> VEX mvmovdqa|vmovdquem, %xmmN (N < 16)
4106 -> VEX vmovdqa|vmovdqu mem, %ymmN (N < 16)
4108 if (i
.tm
.base_opcode
== 0xf26f)
4109 i
.tm
.base_opcode
= 0xf36f;
4110 else if ((i
.tm
.base_opcode
^ Opcode_SIMD_IntD
) == 0xf26f)
4111 i
.tm
.base_opcode
= 0xf36f ^ Opcode_SIMD_IntD
;
4112 i
.tm
.opcode_modifier
.vex
4113 = i
.types
[0].bitfield
.ymmword
? VEX256
: VEX128
;
4114 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4115 i
.tm
.opcode_modifier
.evex
= 0;
4116 i
.tm
.opcode_modifier
.masking
= 0;
4117 i
.tm
.opcode_modifier
.disp8memshift
= 0;
4119 for (j
= 0; j
< 2; j
++)
4120 if (operand_type_check (i
.types
[j
], disp
)
4121 && i
.op
[j
].disps
->X_op
== O_constant
)
4123 i
.types
[j
].bitfield
.disp8
4124 = fits_in_disp8 (i
.op
[j
].disps
->X_add_number
);
4130 /* This is the guts of the machine-dependent assembler. LINE points to a
4131 machine dependent instruction. This function is supposed to emit
4132 the frags/bytes it assembles to. */
4135 md_assemble (char *line
)
4138 char mnemonic
[MAX_MNEM_SIZE
], mnem_suffix
;
4139 const insn_template
*t
;
4141 /* Initialize globals. */
4142 memset (&i
, '\0', sizeof (i
));
4143 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4144 i
.reloc
[j
] = NO_RELOC
;
4145 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
4146 memset (im_expressions
, '\0', sizeof (im_expressions
));
4147 save_stack_p
= save_stack
;
4149 /* First parse an instruction mnemonic & call i386_operand for the operands.
4150 We assume that the scrubber has arranged it so that line[0] is the valid
4151 start of a (possibly prefixed) mnemonic. */
4153 line
= parse_insn (line
, mnemonic
);
4156 mnem_suffix
= i
.suffix
;
4158 line
= parse_operands (line
, mnemonic
);
4160 xfree (i
.memop1_string
);
4161 i
.memop1_string
= NULL
;
4165 /* Now we've parsed the mnemonic into a set of templates, and have the
4166 operands at hand. */
4168 /* All intel opcodes have reversed operands except for "bound" and
4169 "enter". We also don't reverse intersegment "jmp" and "call"
4170 instructions with 2 immediate operands so that the immediate segment
4171 precedes the offset, as it does when in AT&T mode. */
4174 && (strcmp (mnemonic
, "bound") != 0)
4175 && (strcmp (mnemonic
, "invlpga") != 0)
4176 && !(operand_type_check (i
.types
[0], imm
)
4177 && operand_type_check (i
.types
[1], imm
)))
4180 /* The order of the immediates should be reversed
4181 for 2 immediates extrq and insertq instructions */
4182 if (i
.imm_operands
== 2
4183 && (strcmp (mnemonic
, "extrq") == 0
4184 || strcmp (mnemonic
, "insertq") == 0))
4185 swap_2_operands (0, 1);
4190 /* Don't optimize displacement for movabs since it only takes 64bit
4193 && i
.disp_encoding
!= disp_encoding_32bit
4194 && (flag_code
!= CODE_64BIT
4195 || strcmp (mnemonic
, "movabs") != 0))
4198 /* Next, we find a template that matches the given insn,
4199 making sure the overlap of the given operands types is consistent
4200 with the template operand types. */
4202 if (!(t
= match_template (mnem_suffix
)))
4205 if (sse_check
!= check_none
4206 && !i
.tm
.opcode_modifier
.noavx
4207 && !i
.tm
.cpu_flags
.bitfield
.cpuavx
4208 && (i
.tm
.cpu_flags
.bitfield
.cpusse
4209 || i
.tm
.cpu_flags
.bitfield
.cpusse2
4210 || i
.tm
.cpu_flags
.bitfield
.cpusse3
4211 || i
.tm
.cpu_flags
.bitfield
.cpussse3
4212 || i
.tm
.cpu_flags
.bitfield
.cpusse4_1
4213 || i
.tm
.cpu_flags
.bitfield
.cpusse4_2
4214 || i
.tm
.cpu_flags
.bitfield
.cpupclmul
4215 || i
.tm
.cpu_flags
.bitfield
.cpuaes
4216 || i
.tm
.cpu_flags
.bitfield
.cpugfni
))
4218 (sse_check
== check_warning
4220 : as_bad
) (_("SSE instruction `%s' is used"), i
.tm
.name
);
4223 /* Zap movzx and movsx suffix. The suffix has been set from
4224 "word ptr" or "byte ptr" on the source operand in Intel syntax
4225 or extracted from mnemonic in AT&T syntax. But we'll use
4226 the destination register to choose the suffix for encoding. */
4227 if ((i
.tm
.base_opcode
& ~9) == 0x0fb6)
4229 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
4230 there is no suffix, the default will be byte extension. */
4231 if (i
.reg_operands
!= 2
4234 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
4239 if (i
.tm
.opcode_modifier
.fwait
)
4240 if (!add_prefix (FWAIT_OPCODE
))
4243 /* Check if REP prefix is OK. */
4244 if (i
.rep_prefix
&& !i
.tm
.opcode_modifier
.repprefixok
)
4246 as_bad (_("invalid instruction `%s' after `%s'"),
4247 i
.tm
.name
, i
.rep_prefix
);
4251 /* Check for lock without a lockable instruction. Destination operand
4252 must be memory unless it is xchg (0x86). */
4253 if (i
.prefix
[LOCK_PREFIX
]
4254 && (!i
.tm
.opcode_modifier
.islockable
4255 || i
.mem_operands
== 0
4256 || (i
.tm
.base_opcode
!= 0x86
4257 && !operand_type_check (i
.types
[i
.operands
- 1], anymem
))))
4259 as_bad (_("expecting lockable instruction after `lock'"));
4263 /* Check for data size prefix on VEX/XOP/EVEX encoded insns. */
4264 if (i
.prefix
[DATA_PREFIX
] && is_any_vex_encoding (&i
.tm
))
4266 as_bad (_("data size prefix invalid with `%s'"), i
.tm
.name
);
4270 /* Check if HLE prefix is OK. */
4271 if (i
.hle_prefix
&& !check_hle ())
4274 /* Check BND prefix. */
4275 if (i
.bnd_prefix
&& !i
.tm
.opcode_modifier
.bndprefixok
)
4276 as_bad (_("expecting valid branch instruction after `bnd'"));
4278 /* Check NOTRACK prefix. */
4279 if (i
.notrack_prefix
&& !i
.tm
.opcode_modifier
.notrackprefixok
)
4280 as_bad (_("expecting indirect branch instruction after `notrack'"));
4282 if (i
.tm
.cpu_flags
.bitfield
.cpumpx
)
4284 if (flag_code
== CODE_64BIT
&& i
.prefix
[ADDR_PREFIX
])
4285 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
4286 else if (flag_code
!= CODE_16BIT
4287 ? i
.prefix
[ADDR_PREFIX
]
4288 : i
.mem_operands
&& !i
.prefix
[ADDR_PREFIX
])
4289 as_bad (_("16-bit address isn't allowed in MPX instructions"));
4292 /* Insert BND prefix. */
4293 if (add_bnd_prefix
&& i
.tm
.opcode_modifier
.bndprefixok
)
4295 if (!i
.prefix
[BND_PREFIX
])
4296 add_prefix (BND_PREFIX_OPCODE
);
4297 else if (i
.prefix
[BND_PREFIX
] != BND_PREFIX_OPCODE
)
4299 as_warn (_("replacing `rep'/`repe' prefix by `bnd'"));
4300 i
.prefix
[BND_PREFIX
] = BND_PREFIX_OPCODE
;
4304 /* Check string instruction segment overrides. */
4305 if (i
.tm
.opcode_modifier
.isstring
&& i
.mem_operands
!= 0)
4307 if (!check_string ())
4309 i
.disp_operands
= 0;
4312 if (optimize
&& !i
.no_optimize
&& i
.tm
.opcode_modifier
.optimize
)
4313 optimize_encoding ();
4315 if (!process_suffix ())
4318 /* Update operand types. */
4319 for (j
= 0; j
< i
.operands
; j
++)
4320 i
.types
[j
] = operand_type_and (i
.types
[j
], i
.tm
.operand_types
[j
]);
4322 /* Make still unresolved immediate matches conform to size of immediate
4323 given in i.suffix. */
4324 if (!finalize_imm ())
4327 if (i
.types
[0].bitfield
.imm1
)
4328 i
.imm_operands
= 0; /* kludge for shift insns. */
4330 /* We only need to check those implicit registers for instructions
4331 with 3 operands or less. */
4332 if (i
.operands
<= 3)
4333 for (j
= 0; j
< i
.operands
; j
++)
4334 if (i
.types
[j
].bitfield
.inoutportreg
4335 || i
.types
[j
].bitfield
.shiftcount
4336 || (i
.types
[j
].bitfield
.acc
&& !i
.types
[j
].bitfield
.xmmword
))
4339 /* ImmExt should be processed after SSE2AVX. */
4340 if (!i
.tm
.opcode_modifier
.sse2avx
4341 && i
.tm
.opcode_modifier
.immext
)
4344 /* For insns with operands there are more diddles to do to the opcode. */
4347 if (!process_operands ())
4350 else if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
4352 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
4353 as_warn (_("translating to `%sp'"), i
.tm
.name
);
4356 if (is_any_vex_encoding (&i
.tm
))
4358 if (flag_code
== CODE_16BIT
)
4360 as_bad (_("instruction `%s' isn't supported in 16-bit mode."),
4365 if (i
.tm
.opcode_modifier
.vex
)
4366 build_vex_prefix (t
);
4368 build_evex_prefix ();
4371 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
4372 instructions may define INT_OPCODE as well, so avoid this corner
4373 case for those instructions that use MODRM. */
4374 if (i
.tm
.base_opcode
== INT_OPCODE
4375 && !i
.tm
.opcode_modifier
.modrm
4376 && i
.op
[0].imms
->X_add_number
== 3)
4378 i
.tm
.base_opcode
= INT3_OPCODE
;
4382 if ((i
.tm
.opcode_modifier
.jump
4383 || i
.tm
.opcode_modifier
.jumpbyte
4384 || i
.tm
.opcode_modifier
.jumpdword
)
4385 && i
.op
[0].disps
->X_op
== O_constant
)
4387 /* Convert "jmp constant" (and "call constant") to a jump (call) to
4388 the absolute address given by the constant. Since ix86 jumps and
4389 calls are pc relative, we need to generate a reloc. */
4390 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
4391 i
.op
[0].disps
->X_op
= O_symbol
;
4394 if (i
.tm
.opcode_modifier
.rex64
)
4397 /* For 8 bit registers we need an empty rex prefix. Also if the
4398 instruction already has a prefix, we need to convert old
4399 registers to new ones. */
4401 if ((i
.types
[0].bitfield
.reg
&& i
.types
[0].bitfield
.byte
4402 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
4403 || (i
.types
[1].bitfield
.reg
&& i
.types
[1].bitfield
.byte
4404 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
4405 || (((i
.types
[0].bitfield
.reg
&& i
.types
[0].bitfield
.byte
)
4406 || (i
.types
[1].bitfield
.reg
&& i
.types
[1].bitfield
.byte
))
4411 i
.rex
|= REX_OPCODE
;
4412 for (x
= 0; x
< 2; x
++)
4414 /* Look for 8 bit operand that uses old registers. */
4415 if (i
.types
[x
].bitfield
.reg
&& i
.types
[x
].bitfield
.byte
4416 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
4418 /* In case it is "hi" register, give up. */
4419 if (i
.op
[x
].regs
->reg_num
> 3)
4420 as_bad (_("can't encode register '%s%s' in an "
4421 "instruction requiring REX prefix."),
4422 register_prefix
, i
.op
[x
].regs
->reg_name
);
4424 /* Otherwise it is equivalent to the extended register.
4425 Since the encoding doesn't change this is merely
4426 cosmetic cleanup for debug output. */
4428 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
4433 if (i
.rex
== 0 && i
.rex_encoding
)
4435 /* Check if we can add a REX_OPCODE byte. Look for 8 bit operand
4436 that uses legacy register. If it is "hi" register, don't add
4437 the REX_OPCODE byte. */
4439 for (x
= 0; x
< 2; x
++)
4440 if (i
.types
[x
].bitfield
.reg
4441 && i
.types
[x
].bitfield
.byte
4442 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0
4443 && i
.op
[x
].regs
->reg_num
> 3)
4445 i
.rex_encoding
= FALSE
;
4454 add_prefix (REX_OPCODE
| i
.rex
);
4456 /* We are ready to output the insn. */
4461 parse_insn (char *line
, char *mnemonic
)
4464 char *token_start
= l
;
4467 const insn_template
*t
;
4473 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
4478 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
4480 as_bad (_("no such instruction: `%s'"), token_start
);
4485 if (!is_space_char (*l
)
4486 && *l
!= END_OF_INSN
4488 || (*l
!= PREFIX_SEPARATOR
4491 as_bad (_("invalid character %s in mnemonic"),
4492 output_invalid (*l
));
4495 if (token_start
== l
)
4497 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
4498 as_bad (_("expecting prefix; got nothing"));
4500 as_bad (_("expecting mnemonic; got nothing"));
4504 /* Look up instruction (or prefix) via hash table. */
4505 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
4507 if (*l
!= END_OF_INSN
4508 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
4509 && current_templates
4510 && current_templates
->start
->opcode_modifier
.isprefix
)
4512 if (!cpu_flags_check_cpu64 (current_templates
->start
->cpu_flags
))
4514 as_bad ((flag_code
!= CODE_64BIT
4515 ? _("`%s' is only supported in 64-bit mode")
4516 : _("`%s' is not supported in 64-bit mode")),
4517 current_templates
->start
->name
);
4520 /* If we are in 16-bit mode, do not allow addr16 or data16.
4521 Similarly, in 32-bit mode, do not allow addr32 or data32. */
4522 if ((current_templates
->start
->opcode_modifier
.size
== SIZE16
4523 || current_templates
->start
->opcode_modifier
.size
== SIZE32
)
4524 && flag_code
!= CODE_64BIT
4525 && ((current_templates
->start
->opcode_modifier
.size
== SIZE32
)
4526 ^ (flag_code
== CODE_16BIT
)))
4528 as_bad (_("redundant %s prefix"),
4529 current_templates
->start
->name
);
4532 if (current_templates
->start
->opcode_length
== 0)
4534 /* Handle pseudo prefixes. */
4535 switch (current_templates
->start
->base_opcode
)
4539 i
.disp_encoding
= disp_encoding_8bit
;
4543 i
.disp_encoding
= disp_encoding_32bit
;
4547 i
.dir_encoding
= dir_encoding_load
;
4551 i
.dir_encoding
= dir_encoding_store
;
4555 i
.vec_encoding
= vex_encoding_vex2
;
4559 i
.vec_encoding
= vex_encoding_vex3
;
4563 i
.vec_encoding
= vex_encoding_evex
;
4567 i
.rex_encoding
= TRUE
;
4571 i
.no_optimize
= TRUE
;
4579 /* Add prefix, checking for repeated prefixes. */
4580 switch (add_prefix (current_templates
->start
->base_opcode
))
4585 if (current_templates
->start
->cpu_flags
.bitfield
.cpuibt
)
4586 i
.notrack_prefix
= current_templates
->start
->name
;
4589 if (current_templates
->start
->cpu_flags
.bitfield
.cpuhle
)
4590 i
.hle_prefix
= current_templates
->start
->name
;
4591 else if (current_templates
->start
->cpu_flags
.bitfield
.cpumpx
)
4592 i
.bnd_prefix
= current_templates
->start
->name
;
4594 i
.rep_prefix
= current_templates
->start
->name
;
4600 /* Skip past PREFIX_SEPARATOR and reset token_start. */
4607 if (!current_templates
)
4609 /* Deprecated functionality (new code should use pseudo-prefixes instead):
4610 Check if we should swap operand or force 32bit displacement in
4612 if (mnem_p
- 2 == dot_p
&& dot_p
[1] == 's')
4613 i
.dir_encoding
= dir_encoding_swap
;
4614 else if (mnem_p
- 3 == dot_p
4617 i
.disp_encoding
= disp_encoding_8bit
;
4618 else if (mnem_p
- 4 == dot_p
4622 i
.disp_encoding
= disp_encoding_32bit
;
4627 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
4630 if (!current_templates
)
4633 if (mnem_p
> mnemonic
)
4635 /* See if we can get a match by trimming off a suffix. */
4638 case WORD_MNEM_SUFFIX
:
4639 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
4640 i
.suffix
= SHORT_MNEM_SUFFIX
;
4643 case BYTE_MNEM_SUFFIX
:
4644 case QWORD_MNEM_SUFFIX
:
4645 i
.suffix
= mnem_p
[-1];
4647 current_templates
= (const templates
*) hash_find (op_hash
,
4650 case SHORT_MNEM_SUFFIX
:
4651 case LONG_MNEM_SUFFIX
:
4654 i
.suffix
= mnem_p
[-1];
4656 current_templates
= (const templates
*) hash_find (op_hash
,
4665 if (intel_float_operand (mnemonic
) == 1)
4666 i
.suffix
= SHORT_MNEM_SUFFIX
;
4668 i
.suffix
= LONG_MNEM_SUFFIX
;
4670 current_templates
= (const templates
*) hash_find (op_hash
,
4677 if (!current_templates
)
4679 as_bad (_("no such instruction: `%s'"), token_start
);
4684 if (current_templates
->start
->opcode_modifier
.jump
4685 || current_templates
->start
->opcode_modifier
.jumpbyte
)
4687 /* Check for a branch hint. We allow ",pt" and ",pn" for
4688 predict taken and predict not taken respectively.
4689 I'm not sure that branch hints actually do anything on loop
4690 and jcxz insns (JumpByte) for current Pentium4 chips. They
4691 may work in the future and it doesn't hurt to accept them
4693 if (l
[0] == ',' && l
[1] == 'p')
4697 if (!add_prefix (DS_PREFIX_OPCODE
))
4701 else if (l
[2] == 'n')
4703 if (!add_prefix (CS_PREFIX_OPCODE
))
4709 /* Any other comma loses. */
4712 as_bad (_("invalid character %s in mnemonic"),
4713 output_invalid (*l
));
4717 /* Check if instruction is supported on specified architecture. */
4719 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
4721 supported
|= cpu_flags_match (t
);
4722 if (supported
== CPU_FLAGS_PERFECT_MATCH
)
4724 if (!cpu_arch_flags
.bitfield
.cpui386
&& (flag_code
!= CODE_16BIT
))
4725 as_warn (_("use .code16 to ensure correct addressing mode"));
4731 if (!(supported
& CPU_FLAGS_64BIT_MATCH
))
4732 as_bad (flag_code
== CODE_64BIT
4733 ? _("`%s' is not supported in 64-bit mode")
4734 : _("`%s' is only supported in 64-bit mode"),
4735 current_templates
->start
->name
);
4737 as_bad (_("`%s' is not supported on `%s%s'"),
4738 current_templates
->start
->name
,
4739 cpu_arch_name
? cpu_arch_name
: default_arch
,
4740 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
4746 parse_operands (char *l
, const char *mnemonic
)
4750 /* 1 if operand is pending after ','. */
4751 unsigned int expecting_operand
= 0;
4753 /* Non-zero if operand parens not balanced. */
4754 unsigned int paren_not_balanced
;
4756 while (*l
!= END_OF_INSN
)
4758 /* Skip optional white space before operand. */
4759 if (is_space_char (*l
))
4761 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
&& *l
!= '"')
4763 as_bad (_("invalid character %s before operand %d"),
4764 output_invalid (*l
),
4768 token_start
= l
; /* After white space. */
4769 paren_not_balanced
= 0;
4770 while (paren_not_balanced
|| *l
!= ',')
4772 if (*l
== END_OF_INSN
)
4774 if (paren_not_balanced
)
4777 as_bad (_("unbalanced parenthesis in operand %d."),
4780 as_bad (_("unbalanced brackets in operand %d."),
4785 break; /* we are done */
4787 else if (!is_operand_char (*l
) && !is_space_char (*l
) && *l
!= '"')
4789 as_bad (_("invalid character %s in operand %d"),
4790 output_invalid (*l
),
4797 ++paren_not_balanced
;
4799 --paren_not_balanced
;
4804 ++paren_not_balanced
;
4806 --paren_not_balanced
;
4810 if (l
!= token_start
)
4811 { /* Yes, we've read in another operand. */
4812 unsigned int operand_ok
;
4813 this_operand
= i
.operands
++;
4814 if (i
.operands
> MAX_OPERANDS
)
4816 as_bad (_("spurious operands; (%d operands/instruction max)"),
4820 i
.types
[this_operand
].bitfield
.unspecified
= 1;
4821 /* Now parse operand adding info to 'i' as we go along. */
4822 END_STRING_AND_SAVE (l
);
4824 if (i
.mem_operands
> 1)
4826 as_bad (_("too many memory references for `%s'"),
4833 i386_intel_operand (token_start
,
4834 intel_float_operand (mnemonic
));
4836 operand_ok
= i386_att_operand (token_start
);
4838 RESTORE_END_STRING (l
);
4844 if (expecting_operand
)
4846 expecting_operand_after_comma
:
4847 as_bad (_("expecting operand after ','; got nothing"));
4852 as_bad (_("expecting operand before ','; got nothing"));
4857 /* Now *l must be either ',' or END_OF_INSN. */
4860 if (*++l
== END_OF_INSN
)
4862 /* Just skip it, if it's \n complain. */
4863 goto expecting_operand_after_comma
;
4865 expecting_operand
= 1;
4872 swap_2_operands (int xchg1
, int xchg2
)
4874 union i386_op temp_op
;
4875 i386_operand_type temp_type
;
4876 unsigned int temp_flags
;
4877 enum bfd_reloc_code_real temp_reloc
;
4879 temp_type
= i
.types
[xchg2
];
4880 i
.types
[xchg2
] = i
.types
[xchg1
];
4881 i
.types
[xchg1
] = temp_type
;
4883 temp_flags
= i
.flags
[xchg2
];
4884 i
.flags
[xchg2
] = i
.flags
[xchg1
];
4885 i
.flags
[xchg1
] = temp_flags
;
4887 temp_op
= i
.op
[xchg2
];
4888 i
.op
[xchg2
] = i
.op
[xchg1
];
4889 i
.op
[xchg1
] = temp_op
;
4891 temp_reloc
= i
.reloc
[xchg2
];
4892 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
4893 i
.reloc
[xchg1
] = temp_reloc
;
4897 if (i
.mask
->operand
== xchg1
)
4898 i
.mask
->operand
= xchg2
;
4899 else if (i
.mask
->operand
== xchg2
)
4900 i
.mask
->operand
= xchg1
;
4904 if (i
.broadcast
->operand
== xchg1
)
4905 i
.broadcast
->operand
= xchg2
;
4906 else if (i
.broadcast
->operand
== xchg2
)
4907 i
.broadcast
->operand
= xchg1
;
4911 if (i
.rounding
->operand
== xchg1
)
4912 i
.rounding
->operand
= xchg2
;
4913 else if (i
.rounding
->operand
== xchg2
)
4914 i
.rounding
->operand
= xchg1
;
4919 swap_operands (void)
4925 swap_2_operands (1, i
.operands
- 2);
4929 swap_2_operands (0, i
.operands
- 1);
4935 if (i
.mem_operands
== 2)
4937 const seg_entry
*temp_seg
;
4938 temp_seg
= i
.seg
[0];
4939 i
.seg
[0] = i
.seg
[1];
4940 i
.seg
[1] = temp_seg
;
4944 /* Try to ensure constant immediates are represented in the smallest
4949 char guess_suffix
= 0;
4953 guess_suffix
= i
.suffix
;
4954 else if (i
.reg_operands
)
4956 /* Figure out a suffix from the last register operand specified.
4957 We can't do this properly yet, ie. excluding InOutPortReg,
4958 but the following works for instructions with immediates.
4959 In any case, we can't set i.suffix yet. */
4960 for (op
= i
.operands
; --op
>= 0;)
4961 if (i
.types
[op
].bitfield
.reg
&& i
.types
[op
].bitfield
.byte
)
4963 guess_suffix
= BYTE_MNEM_SUFFIX
;
4966 else if (i
.types
[op
].bitfield
.reg
&& i
.types
[op
].bitfield
.word
)
4968 guess_suffix
= WORD_MNEM_SUFFIX
;
4971 else if (i
.types
[op
].bitfield
.reg
&& i
.types
[op
].bitfield
.dword
)
4973 guess_suffix
= LONG_MNEM_SUFFIX
;
4976 else if (i
.types
[op
].bitfield
.reg
&& i
.types
[op
].bitfield
.qword
)
4978 guess_suffix
= QWORD_MNEM_SUFFIX
;
4982 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
4983 guess_suffix
= WORD_MNEM_SUFFIX
;
4985 for (op
= i
.operands
; --op
>= 0;)
4986 if (operand_type_check (i
.types
[op
], imm
))
4988 switch (i
.op
[op
].imms
->X_op
)
4991 /* If a suffix is given, this operand may be shortened. */
4992 switch (guess_suffix
)
4994 case LONG_MNEM_SUFFIX
:
4995 i
.types
[op
].bitfield
.imm32
= 1;
4996 i
.types
[op
].bitfield
.imm64
= 1;
4998 case WORD_MNEM_SUFFIX
:
4999 i
.types
[op
].bitfield
.imm16
= 1;
5000 i
.types
[op
].bitfield
.imm32
= 1;
5001 i
.types
[op
].bitfield
.imm32s
= 1;
5002 i
.types
[op
].bitfield
.imm64
= 1;
5004 case BYTE_MNEM_SUFFIX
:
5005 i
.types
[op
].bitfield
.imm8
= 1;
5006 i
.types
[op
].bitfield
.imm8s
= 1;
5007 i
.types
[op
].bitfield
.imm16
= 1;
5008 i
.types
[op
].bitfield
.imm32
= 1;
5009 i
.types
[op
].bitfield
.imm32s
= 1;
5010 i
.types
[op
].bitfield
.imm64
= 1;
5014 /* If this operand is at most 16 bits, convert it
5015 to a signed 16 bit number before trying to see
5016 whether it will fit in an even smaller size.
5017 This allows a 16-bit operand such as $0xffe0 to
5018 be recognised as within Imm8S range. */
5019 if ((i
.types
[op
].bitfield
.imm16
)
5020 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
5022 i
.op
[op
].imms
->X_add_number
=
5023 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
5026 /* Store 32-bit immediate in 64-bit for 64-bit BFD. */
5027 if ((i
.types
[op
].bitfield
.imm32
)
5028 && ((i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1))
5031 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
5032 ^ ((offsetT
) 1 << 31))
5033 - ((offsetT
) 1 << 31));
5037 = operand_type_or (i
.types
[op
],
5038 smallest_imm_type (i
.op
[op
].imms
->X_add_number
));
5040 /* We must avoid matching of Imm32 templates when 64bit
5041 only immediate is available. */
5042 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
5043 i
.types
[op
].bitfield
.imm32
= 0;
5050 /* Symbols and expressions. */
5052 /* Convert symbolic operand to proper sizes for matching, but don't
5053 prevent matching a set of insns that only supports sizes other
5054 than those matching the insn suffix. */
5056 i386_operand_type mask
, allowed
;
5057 const insn_template
*t
;
5059 operand_type_set (&mask
, 0);
5060 operand_type_set (&allowed
, 0);
5062 for (t
= current_templates
->start
;
5063 t
< current_templates
->end
;
5065 allowed
= operand_type_or (allowed
,
5066 t
->operand_types
[op
]);
5067 switch (guess_suffix
)
5069 case QWORD_MNEM_SUFFIX
:
5070 mask
.bitfield
.imm64
= 1;
5071 mask
.bitfield
.imm32s
= 1;
5073 case LONG_MNEM_SUFFIX
:
5074 mask
.bitfield
.imm32
= 1;
5076 case WORD_MNEM_SUFFIX
:
5077 mask
.bitfield
.imm16
= 1;
5079 case BYTE_MNEM_SUFFIX
:
5080 mask
.bitfield
.imm8
= 1;
5085 allowed
= operand_type_and (mask
, allowed
);
5086 if (!operand_type_all_zero (&allowed
))
5087 i
.types
[op
] = operand_type_and (i
.types
[op
], mask
);
5094 /* Try to use the smallest displacement type too. */
5096 optimize_disp (void)
5100 for (op
= i
.operands
; --op
>= 0;)
5101 if (operand_type_check (i
.types
[op
], disp
))
5103 if (i
.op
[op
].disps
->X_op
== O_constant
)
5105 offsetT op_disp
= i
.op
[op
].disps
->X_add_number
;
5107 if (i
.types
[op
].bitfield
.disp16
5108 && (op_disp
& ~(offsetT
) 0xffff) == 0)
5110 /* If this operand is at most 16 bits, convert
5111 to a signed 16 bit number and don't use 64bit
5113 op_disp
= (((op_disp
& 0xffff) ^ 0x8000) - 0x8000);
5114 i
.types
[op
].bitfield
.disp64
= 0;
5117 /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */
5118 if (i
.types
[op
].bitfield
.disp32
5119 && (op_disp
& ~(((offsetT
) 2 << 31) - 1)) == 0)
5121 /* If this operand is at most 32 bits, convert
5122 to a signed 32 bit number and don't use 64bit
5124 op_disp
&= (((offsetT
) 2 << 31) - 1);
5125 op_disp
= (op_disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
5126 i
.types
[op
].bitfield
.disp64
= 0;
5129 if (!op_disp
&& i
.types
[op
].bitfield
.baseindex
)
5131 i
.types
[op
].bitfield
.disp8
= 0;
5132 i
.types
[op
].bitfield
.disp16
= 0;
5133 i
.types
[op
].bitfield
.disp32
= 0;
5134 i
.types
[op
].bitfield
.disp32s
= 0;
5135 i
.types
[op
].bitfield
.disp64
= 0;
5139 else if (flag_code
== CODE_64BIT
)
5141 if (fits_in_signed_long (op_disp
))
5143 i
.types
[op
].bitfield
.disp64
= 0;
5144 i
.types
[op
].bitfield
.disp32s
= 1;
5146 if (i
.prefix
[ADDR_PREFIX
]
5147 && fits_in_unsigned_long (op_disp
))
5148 i
.types
[op
].bitfield
.disp32
= 1;
5150 if ((i
.types
[op
].bitfield
.disp32
5151 || i
.types
[op
].bitfield
.disp32s
5152 || i
.types
[op
].bitfield
.disp16
)
5153 && fits_in_disp8 (op_disp
))
5154 i
.types
[op
].bitfield
.disp8
= 1;
5156 else if (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
5157 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
)
5159 fix_new_exp (frag_now
, frag_more (0) - frag_now
->fr_literal
, 0,
5160 i
.op
[op
].disps
, 0, i
.reloc
[op
]);
5161 i
.types
[op
].bitfield
.disp8
= 0;
5162 i
.types
[op
].bitfield
.disp16
= 0;
5163 i
.types
[op
].bitfield
.disp32
= 0;
5164 i
.types
[op
].bitfield
.disp32s
= 0;
5165 i
.types
[op
].bitfield
.disp64
= 0;
5168 /* We only support 64bit displacement on constants. */
5169 i
.types
[op
].bitfield
.disp64
= 0;
5173 /* Return 1 if there is a match in broadcast bytes between operand
5174 GIVEN and instruction template T. */
5177 match_broadcast_size (const insn_template
*t
, unsigned int given
)
5179 return ((t
->opcode_modifier
.broadcast
== BYTE_BROADCAST
5180 && i
.types
[given
].bitfield
.byte
)
5181 || (t
->opcode_modifier
.broadcast
== WORD_BROADCAST
5182 && i
.types
[given
].bitfield
.word
)
5183 || (t
->opcode_modifier
.broadcast
== DWORD_BROADCAST
5184 && i
.types
[given
].bitfield
.dword
)
5185 || (t
->opcode_modifier
.broadcast
== QWORD_BROADCAST
5186 && i
.types
[given
].bitfield
.qword
));
5189 /* Check if operands are valid for the instruction. */
5192 check_VecOperands (const insn_template
*t
)
5196 static const i386_cpu_flags avx512
= CPU_ANY_AVX512F_FLAGS
;
5198 /* Templates allowing for ZMMword as well as YMMword and/or XMMword for
5199 any one operand are implicity requiring AVX512VL support if the actual
5200 operand size is YMMword or XMMword. Since this function runs after
5201 template matching, there's no need to check for YMMword/XMMword in
5203 cpu
= cpu_flags_and (t
->cpu_flags
, avx512
);
5204 if (!cpu_flags_all_zero (&cpu
)
5205 && !t
->cpu_flags
.bitfield
.cpuavx512vl
5206 && !cpu_arch_flags
.bitfield
.cpuavx512vl
)
5208 for (op
= 0; op
< t
->operands
; ++op
)
5210 if (t
->operand_types
[op
].bitfield
.zmmword
5211 && (i
.types
[op
].bitfield
.ymmword
5212 || i
.types
[op
].bitfield
.xmmword
))
5214 i
.error
= unsupported
;
5220 /* Without VSIB byte, we can't have a vector register for index. */
5221 if (!t
->opcode_modifier
.vecsib
5223 && (i
.index_reg
->reg_type
.bitfield
.xmmword
5224 || i
.index_reg
->reg_type
.bitfield
.ymmword
5225 || i
.index_reg
->reg_type
.bitfield
.zmmword
))
5227 i
.error
= unsupported_vector_index_register
;
5231 /* Check if default mask is allowed. */
5232 if (t
->opcode_modifier
.nodefmask
5233 && (!i
.mask
|| i
.mask
->mask
->reg_num
== 0))
5235 i
.error
= no_default_mask
;
5239 /* For VSIB byte, we need a vector register for index, and all vector
5240 registers must be distinct. */
5241 if (t
->opcode_modifier
.vecsib
)
5244 || !((t
->opcode_modifier
.vecsib
== VecSIB128
5245 && i
.index_reg
->reg_type
.bitfield
.xmmword
)
5246 || (t
->opcode_modifier
.vecsib
== VecSIB256
5247 && i
.index_reg
->reg_type
.bitfield
.ymmword
)
5248 || (t
->opcode_modifier
.vecsib
== VecSIB512
5249 && i
.index_reg
->reg_type
.bitfield
.zmmword
)))
5251 i
.error
= invalid_vsib_address
;
5255 gas_assert (i
.reg_operands
== 2 || i
.mask
);
5256 if (i
.reg_operands
== 2 && !i
.mask
)
5258 gas_assert (i
.types
[0].bitfield
.regsimd
);
5259 gas_assert (i
.types
[0].bitfield
.xmmword
5260 || i
.types
[0].bitfield
.ymmword
);
5261 gas_assert (i
.types
[2].bitfield
.regsimd
);
5262 gas_assert (i
.types
[2].bitfield
.xmmword
5263 || i
.types
[2].bitfield
.ymmword
);
5264 if (operand_check
== check_none
)
5266 if (register_number (i
.op
[0].regs
)
5267 != register_number (i
.index_reg
)
5268 && register_number (i
.op
[2].regs
)
5269 != register_number (i
.index_reg
)
5270 && register_number (i
.op
[0].regs
)
5271 != register_number (i
.op
[2].regs
))
5273 if (operand_check
== check_error
)
5275 i
.error
= invalid_vector_register_set
;
5278 as_warn (_("mask, index, and destination registers should be distinct"));
5280 else if (i
.reg_operands
== 1 && i
.mask
)
5282 if (i
.types
[1].bitfield
.regsimd
5283 && (i
.types
[1].bitfield
.xmmword
5284 || i
.types
[1].bitfield
.ymmword
5285 || i
.types
[1].bitfield
.zmmword
)
5286 && (register_number (i
.op
[1].regs
)
5287 == register_number (i
.index_reg
)))
5289 if (operand_check
== check_error
)
5291 i
.error
= invalid_vector_register_set
;
5294 if (operand_check
!= check_none
)
5295 as_warn (_("index and destination registers should be distinct"));
5300 /* Check if broadcast is supported by the instruction and is applied
5301 to the memory operand. */
5304 i386_operand_type type
, overlap
;
5306 /* Check if specified broadcast is supported in this instruction,
5307 and its broadcast bytes match the memory operand. */
5308 op
= i
.broadcast
->operand
;
5309 if (!t
->opcode_modifier
.broadcast
5310 || !(i
.flags
[op
] & Operand_Mem
)
5311 || (!i
.types
[op
].bitfield
.unspecified
5312 && !match_broadcast_size (t
, op
)))
5315 i
.error
= unsupported_broadcast
;
5319 i
.broadcast
->bytes
= ((1 << (t
->opcode_modifier
.broadcast
- 1))
5320 * i
.broadcast
->type
);
5321 operand_type_set (&type
, 0);
5322 switch (i
.broadcast
->bytes
)
5325 type
.bitfield
.word
= 1;
5328 type
.bitfield
.dword
= 1;
5331 type
.bitfield
.qword
= 1;
5334 type
.bitfield
.xmmword
= 1;
5337 type
.bitfield
.ymmword
= 1;
5340 type
.bitfield
.zmmword
= 1;
5346 overlap
= operand_type_and (type
, t
->operand_types
[op
]);
5347 if (operand_type_all_zero (&overlap
))
5350 if (t
->opcode_modifier
.checkregsize
)
5354 type
.bitfield
.baseindex
= 1;
5355 for (j
= 0; j
< i
.operands
; ++j
)
5358 && !operand_type_register_match(i
.types
[j
],
5359 t
->operand_types
[j
],
5361 t
->operand_types
[op
]))
5366 /* If broadcast is supported in this instruction, we need to check if
5367 operand of one-element size isn't specified without broadcast. */
5368 else if (t
->opcode_modifier
.broadcast
&& i
.mem_operands
)
5370 /* Find memory operand. */
5371 for (op
= 0; op
< i
.operands
; op
++)
5372 if (operand_type_check (i
.types
[op
], anymem
))
5374 gas_assert (op
< i
.operands
);
5375 /* Check size of the memory operand. */
5376 if (match_broadcast_size (t
, op
))
5378 i
.error
= broadcast_needed
;
5383 op
= MAX_OPERANDS
- 1; /* Avoid uninitialized variable warning. */
5385 /* Check if requested masking is supported. */
5388 switch (t
->opcode_modifier
.masking
)
5392 case MERGING_MASKING
:
5393 if (i
.mask
->zeroing
)
5396 i
.error
= unsupported_masking
;
5400 case DYNAMIC_MASKING
:
5401 /* Memory destinations allow only merging masking. */
5402 if (i
.mask
->zeroing
&& i
.mem_operands
)
5404 /* Find memory operand. */
5405 for (op
= 0; op
< i
.operands
; op
++)
5406 if (i
.flags
[op
] & Operand_Mem
)
5408 gas_assert (op
< i
.operands
);
5409 if (op
== i
.operands
- 1)
5411 i
.error
= unsupported_masking
;
5421 /* Check if masking is applied to dest operand. */
5422 if (i
.mask
&& (i
.mask
->operand
!= (int) (i
.operands
- 1)))
5424 i
.error
= mask_not_on_destination
;
5431 if ((i
.rounding
->type
!= saeonly
5432 && !t
->opcode_modifier
.staticrounding
)
5433 || (i
.rounding
->type
== saeonly
5434 && (t
->opcode_modifier
.staticrounding
5435 || !t
->opcode_modifier
.sae
)))
5437 i
.error
= unsupported_rc_sae
;
5440 /* If the instruction has several immediate operands and one of
5441 them is rounding, the rounding operand should be the last
5442 immediate operand. */
5443 if (i
.imm_operands
> 1
5444 && i
.rounding
->operand
!= (int) (i
.imm_operands
- 1))
5446 i
.error
= rc_sae_operand_not_last_imm
;
5451 /* Check vector Disp8 operand. */
5452 if (t
->opcode_modifier
.disp8memshift
5453 && i
.disp_encoding
!= disp_encoding_32bit
)
5456 i
.memshift
= t
->opcode_modifier
.broadcast
- 1;
5457 else if (t
->opcode_modifier
.disp8memshift
!= DISP8_SHIFT_VL
)
5458 i
.memshift
= t
->opcode_modifier
.disp8memshift
;
5461 const i386_operand_type
*type
= NULL
;
5464 for (op
= 0; op
< i
.operands
; op
++)
5465 if (operand_type_check (i
.types
[op
], anymem
))
5467 if (t
->opcode_modifier
.evex
== EVEXLIG
)
5468 i
.memshift
= 2 + (i
.suffix
== QWORD_MNEM_SUFFIX
);
5469 else if (t
->operand_types
[op
].bitfield
.xmmword
5470 + t
->operand_types
[op
].bitfield
.ymmword
5471 + t
->operand_types
[op
].bitfield
.zmmword
<= 1)
5472 type
= &t
->operand_types
[op
];
5473 else if (!i
.types
[op
].bitfield
.unspecified
)
5474 type
= &i
.types
[op
];
5476 else if (i
.types
[op
].bitfield
.regsimd
5477 && t
->opcode_modifier
.evex
!= EVEXLIG
)
5479 if (i
.types
[op
].bitfield
.zmmword
)
5481 else if (i
.types
[op
].bitfield
.ymmword
&& i
.memshift
< 5)
5483 else if (i
.types
[op
].bitfield
.xmmword
&& i
.memshift
< 4)
5489 if (type
->bitfield
.zmmword
)
5491 else if (type
->bitfield
.ymmword
)
5493 else if (type
->bitfield
.xmmword
)
5497 /* For the check in fits_in_disp8(). */
5498 if (i
.memshift
== 0)
5502 for (op
= 0; op
< i
.operands
; op
++)
5503 if (operand_type_check (i
.types
[op
], disp
)
5504 && i
.op
[op
].disps
->X_op
== O_constant
)
5506 if (fits_in_disp8 (i
.op
[op
].disps
->X_add_number
))
5508 i
.types
[op
].bitfield
.disp8
= 1;
5511 i
.types
[op
].bitfield
.disp8
= 0;
5520 /* Check if operands are valid for the instruction. Update VEX
5524 VEX_check_operands (const insn_template
*t
)
5526 if (i
.vec_encoding
== vex_encoding_evex
)
5528 /* This instruction must be encoded with EVEX prefix. */
5529 if (!is_evex_encoding (t
))
5531 i
.error
= unsupported
;
5537 if (!t
->opcode_modifier
.vex
)
5539 /* This instruction template doesn't have VEX prefix. */
5540 if (i
.vec_encoding
!= vex_encoding_default
)
5542 i
.error
= unsupported
;
5548 /* Only check VEX_Imm4, which must be the first operand. */
5549 if (t
->operand_types
[0].bitfield
.vec_imm4
)
5551 if (i
.op
[0].imms
->X_op
!= O_constant
5552 || !fits_in_imm4 (i
.op
[0].imms
->X_add_number
))
5558 /* Turn off Imm8 so that update_imm won't complain. */
5559 i
.types
[0] = vec_imm4
;
5565 static const insn_template
*
5566 match_template (char mnem_suffix
)
5568 /* Points to template once we've found it. */
5569 const insn_template
*t
;
5570 i386_operand_type overlap0
, overlap1
, overlap2
, overlap3
;
5571 i386_operand_type overlap4
;
5572 unsigned int found_reverse_match
;
5573 i386_opcode_modifier suffix_check
, mnemsuf_check
;
5574 i386_operand_type operand_types
[MAX_OPERANDS
];
5575 int addr_prefix_disp
;
5577 unsigned int found_cpu_match
, size_match
;
5578 unsigned int check_register
;
5579 enum i386_error specific_error
= 0;
5581 #if MAX_OPERANDS != 5
5582 # error "MAX_OPERANDS must be 5."
5585 found_reverse_match
= 0;
5586 addr_prefix_disp
= -1;
5588 memset (&suffix_check
, 0, sizeof (suffix_check
));
5589 if (intel_syntax
&& i
.broadcast
)
5591 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
5592 suffix_check
.no_bsuf
= 1;
5593 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
5594 suffix_check
.no_wsuf
= 1;
5595 else if (i
.suffix
== SHORT_MNEM_SUFFIX
)
5596 suffix_check
.no_ssuf
= 1;
5597 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
5598 suffix_check
.no_lsuf
= 1;
5599 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
5600 suffix_check
.no_qsuf
= 1;
5601 else if (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
)
5602 suffix_check
.no_ldsuf
= 1;
5604 memset (&mnemsuf_check
, 0, sizeof (mnemsuf_check
));
5607 switch (mnem_suffix
)
5609 case BYTE_MNEM_SUFFIX
: mnemsuf_check
.no_bsuf
= 1; break;
5610 case WORD_MNEM_SUFFIX
: mnemsuf_check
.no_wsuf
= 1; break;
5611 case SHORT_MNEM_SUFFIX
: mnemsuf_check
.no_ssuf
= 1; break;
5612 case LONG_MNEM_SUFFIX
: mnemsuf_check
.no_lsuf
= 1; break;
5613 case QWORD_MNEM_SUFFIX
: mnemsuf_check
.no_qsuf
= 1; break;
5617 /* Must have right number of operands. */
5618 i
.error
= number_of_operands_mismatch
;
5620 for (t
= current_templates
->start
; t
< current_templates
->end
; t
++)
5622 addr_prefix_disp
= -1;
5623 found_reverse_match
= 0;
5625 if (i
.operands
!= t
->operands
)
5628 /* Check processor support. */
5629 i
.error
= unsupported
;
5630 found_cpu_match
= (cpu_flags_match (t
)
5631 == CPU_FLAGS_PERFECT_MATCH
);
5632 if (!found_cpu_match
)
5635 /* Check AT&T mnemonic. */
5636 i
.error
= unsupported_with_intel_mnemonic
;
5637 if (intel_mnemonic
&& t
->opcode_modifier
.attmnemonic
)
5640 /* Check AT&T/Intel syntax and Intel64/AMD64 ISA. */
5641 i
.error
= unsupported_syntax
;
5642 if ((intel_syntax
&& t
->opcode_modifier
.attsyntax
)
5643 || (!intel_syntax
&& t
->opcode_modifier
.intelsyntax
)
5644 || (intel64
&& t
->opcode_modifier
.amd64
)
5645 || (!intel64
&& t
->opcode_modifier
.intel64
))
5648 /* Check the suffix, except for some instructions in intel mode. */
5649 i
.error
= invalid_instruction_suffix
;
5650 if ((!intel_syntax
|| !t
->opcode_modifier
.ignoresize
)
5651 && ((t
->opcode_modifier
.no_bsuf
&& suffix_check
.no_bsuf
)
5652 || (t
->opcode_modifier
.no_wsuf
&& suffix_check
.no_wsuf
)
5653 || (t
->opcode_modifier
.no_lsuf
&& suffix_check
.no_lsuf
)
5654 || (t
->opcode_modifier
.no_ssuf
&& suffix_check
.no_ssuf
)
5655 || (t
->opcode_modifier
.no_qsuf
&& suffix_check
.no_qsuf
)
5656 || (t
->opcode_modifier
.no_ldsuf
&& suffix_check
.no_ldsuf
)))
5658 /* In Intel mode all mnemonic suffixes must be explicitly allowed. */
5659 if ((t
->opcode_modifier
.no_bsuf
&& mnemsuf_check
.no_bsuf
)
5660 || (t
->opcode_modifier
.no_wsuf
&& mnemsuf_check
.no_wsuf
)
5661 || (t
->opcode_modifier
.no_lsuf
&& mnemsuf_check
.no_lsuf
)
5662 || (t
->opcode_modifier
.no_ssuf
&& mnemsuf_check
.no_ssuf
)
5663 || (t
->opcode_modifier
.no_qsuf
&& mnemsuf_check
.no_qsuf
)
5664 || (t
->opcode_modifier
.no_ldsuf
&& mnemsuf_check
.no_ldsuf
))
5667 size_match
= operand_size_match (t
);
5671 for (j
= 0; j
< MAX_OPERANDS
; j
++)
5672 operand_types
[j
] = t
->operand_types
[j
];
5674 /* In general, don't allow 64-bit operands in 32-bit mode. */
5675 if (i
.suffix
== QWORD_MNEM_SUFFIX
5676 && flag_code
!= CODE_64BIT
5678 ? (!t
->opcode_modifier
.ignoresize
5679 && !t
->opcode_modifier
.broadcast
5680 && !intel_float_operand (t
->name
))
5681 : intel_float_operand (t
->name
) != 2)
5682 && ((!operand_types
[0].bitfield
.regmmx
5683 && !operand_types
[0].bitfield
.regsimd
)
5684 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
5685 && !operand_types
[t
->operands
> 1].bitfield
.regsimd
))
5686 && (t
->base_opcode
!= 0x0fc7
5687 || t
->extension_opcode
!= 1 /* cmpxchg8b */))
5690 /* In general, don't allow 32-bit operands on pre-386. */
5691 else if (i
.suffix
== LONG_MNEM_SUFFIX
5692 && !cpu_arch_flags
.bitfield
.cpui386
5694 ? (!t
->opcode_modifier
.ignoresize
5695 && !intel_float_operand (t
->name
))
5696 : intel_float_operand (t
->name
) != 2)
5697 && ((!operand_types
[0].bitfield
.regmmx
5698 && !operand_types
[0].bitfield
.regsimd
)
5699 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
5700 && !operand_types
[t
->operands
> 1].bitfield
.regsimd
)))
5703 /* Do not verify operands when there are none. */
5707 /* We've found a match; break out of loop. */
5711 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
5712 into Disp32/Disp16/Disp32 operand. */
5713 if (i
.prefix
[ADDR_PREFIX
] != 0)
5715 /* There should be only one Disp operand. */
5719 for (j
= 0; j
< MAX_OPERANDS
; j
++)
5721 if (operand_types
[j
].bitfield
.disp16
)
5723 addr_prefix_disp
= j
;
5724 operand_types
[j
].bitfield
.disp32
= 1;
5725 operand_types
[j
].bitfield
.disp16
= 0;
5731 for (j
= 0; j
< MAX_OPERANDS
; j
++)
5733 if (operand_types
[j
].bitfield
.disp32
)
5735 addr_prefix_disp
= j
;
5736 operand_types
[j
].bitfield
.disp32
= 0;
5737 operand_types
[j
].bitfield
.disp16
= 1;
5743 for (j
= 0; j
< MAX_OPERANDS
; j
++)
5745 if (operand_types
[j
].bitfield
.disp64
)
5747 addr_prefix_disp
= j
;
5748 operand_types
[j
].bitfield
.disp64
= 0;
5749 operand_types
[j
].bitfield
.disp32
= 1;
5757 /* Force 0x8b encoding for "mov foo@GOT, %eax". */
5758 if (i
.reloc
[0] == BFD_RELOC_386_GOT32
&& t
->base_opcode
== 0xa0)
5761 /* We check register size if needed. */
5762 if (t
->opcode_modifier
.checkregsize
)
5764 check_register
= (1 << t
->operands
) - 1;
5766 check_register
&= ~(1 << i
.broadcast
->operand
);
5771 overlap0
= operand_type_and (i
.types
[0], operand_types
[0]);
5772 switch (t
->operands
)
5775 if (!operand_type_match (overlap0
, i
.types
[0]))
5779 /* xchg %eax, %eax is a special case. It is an alias for nop
5780 only in 32bit mode and we can use opcode 0x90. In 64bit
5781 mode, we can't use 0x90 for xchg %eax, %eax since it should
5782 zero-extend %eax to %rax. */
5783 if (flag_code
== CODE_64BIT
5784 && t
->base_opcode
== 0x90
5785 && operand_type_equal (&i
.types
[0], &acc32
)
5786 && operand_type_equal (&i
.types
[1], &acc32
))
5788 /* xrelease mov %eax, <disp> is another special case. It must not
5789 match the accumulator-only encoding of mov. */
5790 if (flag_code
!= CODE_64BIT
5792 && t
->base_opcode
== 0xa0
5793 && i
.types
[0].bitfield
.acc
5794 && operand_type_check (i
.types
[1], anymem
))
5799 if (!(size_match
& MATCH_STRAIGHT
))
5801 /* Reverse direction of operands if swapping is possible in the first
5802 place (operands need to be symmetric) and
5803 - the load form is requested, and the template is a store form,
5804 - the store form is requested, and the template is a load form,
5805 - the non-default (swapped) form is requested. */
5806 overlap1
= operand_type_and (operand_types
[0], operand_types
[1]);
5807 if (t
->opcode_modifier
.d
&& i
.reg_operands
== i
.operands
5808 && !operand_type_all_zero (&overlap1
))
5809 switch (i
.dir_encoding
)
5811 case dir_encoding_load
:
5812 if (operand_type_check (operand_types
[i
.operands
- 1], anymem
)
5813 || operand_types
[i
.operands
- 1].bitfield
.regmem
)
5817 case dir_encoding_store
:
5818 if (!operand_type_check (operand_types
[i
.operands
- 1], anymem
)
5819 && !operand_types
[i
.operands
- 1].bitfield
.regmem
)
5823 case dir_encoding_swap
:
5826 case dir_encoding_default
:
5829 /* If we want store form, we skip the current load. */
5830 if ((i
.dir_encoding
== dir_encoding_store
5831 || i
.dir_encoding
== dir_encoding_swap
)
5832 && i
.mem_operands
== 0
5833 && t
->opcode_modifier
.load
)
5838 overlap1
= operand_type_and (i
.types
[1], operand_types
[1]);
5839 if (!operand_type_match (overlap0
, i
.types
[0])
5840 || !operand_type_match (overlap1
, i
.types
[1])
5841 || ((check_register
& 3) == 3
5842 && !operand_type_register_match (i
.types
[0],
5847 /* Check if other direction is valid ... */
5848 if (!t
->opcode_modifier
.d
)
5852 if (!(size_match
& MATCH_REVERSE
))
5854 /* Try reversing direction of operands. */
5855 overlap0
= operand_type_and (i
.types
[0], operand_types
[i
.operands
- 1]);
5856 overlap1
= operand_type_and (i
.types
[i
.operands
- 1], operand_types
[0]);
5857 if (!operand_type_match (overlap0
, i
.types
[0])
5858 || !operand_type_match (overlap1
, i
.types
[i
.operands
- 1])
5860 && !operand_type_register_match (i
.types
[0],
5861 operand_types
[i
.operands
- 1],
5862 i
.types
[i
.operands
- 1],
5865 /* Does not match either direction. */
5868 /* found_reverse_match holds which of D or FloatR
5870 if (!t
->opcode_modifier
.d
)
5871 found_reverse_match
= 0;
5872 else if (operand_types
[0].bitfield
.tbyte
)
5873 found_reverse_match
= Opcode_FloatD
;
5874 else if (operand_types
[0].bitfield
.xmmword
5875 || operand_types
[i
.operands
- 1].bitfield
.xmmword
5876 || operand_types
[0].bitfield
.regmmx
5877 || operand_types
[i
.operands
- 1].bitfield
.regmmx
5878 || is_any_vex_encoding(t
))
5879 found_reverse_match
= (t
->base_opcode
& 0xee) != 0x6e
5880 ? Opcode_SIMD_FloatD
: Opcode_SIMD_IntD
;
5882 found_reverse_match
= Opcode_D
;
5883 if (t
->opcode_modifier
.floatr
)
5884 found_reverse_match
|= Opcode_FloatR
;
5888 /* Found a forward 2 operand match here. */
5889 switch (t
->operands
)
5892 overlap4
= operand_type_and (i
.types
[4],
5896 overlap3
= operand_type_and (i
.types
[3],
5900 overlap2
= operand_type_and (i
.types
[2],
5905 switch (t
->operands
)
5908 if (!operand_type_match (overlap4
, i
.types
[4])
5909 || !operand_type_register_match (i
.types
[3],
5916 if (!operand_type_match (overlap3
, i
.types
[3])
5917 || ((check_register
& 0xa) == 0xa
5918 && !operand_type_register_match (i
.types
[1],
5922 || ((check_register
& 0xc) == 0xc
5923 && !operand_type_register_match (i
.types
[2],
5930 /* Here we make use of the fact that there are no
5931 reverse match 3 operand instructions. */
5932 if (!operand_type_match (overlap2
, i
.types
[2])
5933 || ((check_register
& 5) == 5
5934 && !operand_type_register_match (i
.types
[0],
5938 || ((check_register
& 6) == 6
5939 && !operand_type_register_match (i
.types
[1],
5947 /* Found either forward/reverse 2, 3 or 4 operand match here:
5948 slip through to break. */
5950 if (!found_cpu_match
)
5953 /* Check if vector and VEX operands are valid. */
5954 if (check_VecOperands (t
) || VEX_check_operands (t
))
5956 specific_error
= i
.error
;
5960 /* We've found a match; break out of loop. */
5964 if (t
== current_templates
->end
)
5966 /* We found no match. */
5967 const char *err_msg
;
5968 switch (specific_error
? specific_error
: i
.error
)
5972 case operand_size_mismatch
:
5973 err_msg
= _("operand size mismatch");
5975 case operand_type_mismatch
:
5976 err_msg
= _("operand type mismatch");
5978 case register_type_mismatch
:
5979 err_msg
= _("register type mismatch");
5981 case number_of_operands_mismatch
:
5982 err_msg
= _("number of operands mismatch");
5984 case invalid_instruction_suffix
:
5985 err_msg
= _("invalid instruction suffix");
5988 err_msg
= _("constant doesn't fit in 4 bits");
5990 case unsupported_with_intel_mnemonic
:
5991 err_msg
= _("unsupported with Intel mnemonic");
5993 case unsupported_syntax
:
5994 err_msg
= _("unsupported syntax");
5997 as_bad (_("unsupported instruction `%s'"),
5998 current_templates
->start
->name
);
6000 case invalid_vsib_address
:
6001 err_msg
= _("invalid VSIB address");
6003 case invalid_vector_register_set
:
6004 err_msg
= _("mask, index, and destination registers must be distinct");
6006 case unsupported_vector_index_register
:
6007 err_msg
= _("unsupported vector index register");
6009 case unsupported_broadcast
:
6010 err_msg
= _("unsupported broadcast");
6012 case broadcast_needed
:
6013 err_msg
= _("broadcast is needed for operand of such type");
6015 case unsupported_masking
:
6016 err_msg
= _("unsupported masking");
6018 case mask_not_on_destination
:
6019 err_msg
= _("mask not on destination operand");
6021 case no_default_mask
:
6022 err_msg
= _("default mask isn't allowed");
6024 case unsupported_rc_sae
:
6025 err_msg
= _("unsupported static rounding/sae");
6027 case rc_sae_operand_not_last_imm
:
6029 err_msg
= _("RC/SAE operand must precede immediate operands");
6031 err_msg
= _("RC/SAE operand must follow immediate operands");
6033 case invalid_register_operand
:
6034 err_msg
= _("invalid register operand");
6037 as_bad (_("%s for `%s'"), err_msg
,
6038 current_templates
->start
->name
);
6042 if (!quiet_warnings
)
6045 && (i
.types
[0].bitfield
.jumpabsolute
6046 != operand_types
[0].bitfield
.jumpabsolute
))
6048 as_warn (_("indirect %s without `*'"), t
->name
);
6051 if (t
->opcode_modifier
.isprefix
6052 && t
->opcode_modifier
.ignoresize
)
6054 /* Warn them that a data or address size prefix doesn't
6055 affect assembly of the next line of code. */
6056 as_warn (_("stand-alone `%s' prefix"), t
->name
);
6060 /* Copy the template we found. */
6063 if (addr_prefix_disp
!= -1)
6064 i
.tm
.operand_types
[addr_prefix_disp
]
6065 = operand_types
[addr_prefix_disp
];
6067 if (found_reverse_match
)
6069 /* If we found a reverse match we must alter the opcode
6070 direction bit. found_reverse_match holds bits to change
6071 (different for int & float insns). */
6073 i
.tm
.base_opcode
^= found_reverse_match
;
6075 i
.tm
.operand_types
[0] = operand_types
[i
.operands
- 1];
6076 i
.tm
.operand_types
[i
.operands
- 1] = operand_types
[0];
6085 int mem_op
= operand_type_check (i
.types
[0], anymem
) ? 0 : 1;
6086 if (i
.tm
.operand_types
[mem_op
].bitfield
.esseg
)
6088 if (i
.seg
[0] != NULL
&& i
.seg
[0] != &es
)
6090 as_bad (_("`%s' operand %d must use `%ses' segment"),
6096 /* There's only ever one segment override allowed per instruction.
6097 This instruction possibly has a legal segment override on the
6098 second operand, so copy the segment to where non-string
6099 instructions store it, allowing common code. */
6100 i
.seg
[0] = i
.seg
[1];
6102 else if (i
.tm
.operand_types
[mem_op
+ 1].bitfield
.esseg
)
6104 if (i
.seg
[1] != NULL
&& i
.seg
[1] != &es
)
6106 as_bad (_("`%s' operand %d must use `%ses' segment"),
6117 process_suffix (void)
6119 /* If matched instruction specifies an explicit instruction mnemonic
6121 if (i
.tm
.opcode_modifier
.size
== SIZE16
)
6122 i
.suffix
= WORD_MNEM_SUFFIX
;
6123 else if (i
.tm
.opcode_modifier
.size
== SIZE32
)
6124 i
.suffix
= LONG_MNEM_SUFFIX
;
6125 else if (i
.tm
.opcode_modifier
.size
== SIZE64
)
6126 i
.suffix
= QWORD_MNEM_SUFFIX
;
6127 else if (i
.reg_operands
)
6129 /* If there's no instruction mnemonic suffix we try to invent one
6130 based on register operands. */
6133 /* We take i.suffix from the last register operand specified,
6134 Destination register type is more significant than source
6135 register type. crc32 in SSE4.2 prefers source register
6137 if (i
.tm
.base_opcode
== 0xf20f38f0 && i
.types
[0].bitfield
.reg
)
6139 if (i
.types
[0].bitfield
.byte
)
6140 i
.suffix
= BYTE_MNEM_SUFFIX
;
6141 else if (i
.types
[0].bitfield
.word
)
6142 i
.suffix
= WORD_MNEM_SUFFIX
;
6143 else if (i
.types
[0].bitfield
.dword
)
6144 i
.suffix
= LONG_MNEM_SUFFIX
;
6145 else if (i
.types
[0].bitfield
.qword
)
6146 i
.suffix
= QWORD_MNEM_SUFFIX
;
6153 if (i
.tm
.base_opcode
== 0xf20f38f0)
6155 /* We have to know the operand size for crc32. */
6156 as_bad (_("ambiguous memory operand size for `%s`"),
6161 for (op
= i
.operands
; --op
>= 0;)
6162 if (!i
.tm
.operand_types
[op
].bitfield
.inoutportreg
6163 && !i
.tm
.operand_types
[op
].bitfield
.shiftcount
)
6165 if (!i
.types
[op
].bitfield
.reg
)
6167 if (i
.types
[op
].bitfield
.byte
)
6168 i
.suffix
= BYTE_MNEM_SUFFIX
;
6169 else if (i
.types
[op
].bitfield
.word
)
6170 i
.suffix
= WORD_MNEM_SUFFIX
;
6171 else if (i
.types
[op
].bitfield
.dword
)
6172 i
.suffix
= LONG_MNEM_SUFFIX
;
6173 else if (i
.types
[op
].bitfield
.qword
)
6174 i
.suffix
= QWORD_MNEM_SUFFIX
;
6181 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
6184 && i
.tm
.opcode_modifier
.ignoresize
6185 && i
.tm
.opcode_modifier
.no_bsuf
)
6187 else if (!check_byte_reg ())
6190 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
6193 && i
.tm
.opcode_modifier
.ignoresize
6194 && i
.tm
.opcode_modifier
.no_lsuf
6195 && !i
.tm
.opcode_modifier
.todword
6196 && !i
.tm
.opcode_modifier
.toqword
)
6198 else if (!check_long_reg ())
6201 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
6204 && i
.tm
.opcode_modifier
.ignoresize
6205 && i
.tm
.opcode_modifier
.no_qsuf
6206 && !i
.tm
.opcode_modifier
.todword
6207 && !i
.tm
.opcode_modifier
.toqword
)
6209 else if (!check_qword_reg ())
6212 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
6215 && i
.tm
.opcode_modifier
.ignoresize
6216 && i
.tm
.opcode_modifier
.no_wsuf
)
6218 else if (!check_word_reg ())
6221 else if (intel_syntax
&& i
.tm
.opcode_modifier
.ignoresize
)
6222 /* Do nothing if the instruction is going to ignore the prefix. */
6227 else if (i
.tm
.opcode_modifier
.defaultsize
6229 /* exclude fldenv/frstor/fsave/fstenv */
6230 && i
.tm
.opcode_modifier
.no_ssuf
)
6232 i
.suffix
= stackop_size
;
6234 else if (intel_syntax
6236 && (i
.tm
.operand_types
[0].bitfield
.jumpabsolute
6237 || i
.tm
.opcode_modifier
.jumpbyte
6238 || i
.tm
.opcode_modifier
.jumpintersegment
6239 || (i
.tm
.base_opcode
== 0x0f01 /* [ls][gi]dt */
6240 && i
.tm
.extension_opcode
<= 3)))
6245 if (!i
.tm
.opcode_modifier
.no_qsuf
)
6247 i
.suffix
= QWORD_MNEM_SUFFIX
;
6252 if (!i
.tm
.opcode_modifier
.no_lsuf
)
6253 i
.suffix
= LONG_MNEM_SUFFIX
;
6256 if (!i
.tm
.opcode_modifier
.no_wsuf
)
6257 i
.suffix
= WORD_MNEM_SUFFIX
;
6266 if (i
.tm
.opcode_modifier
.w
)
6268 as_bad (_("no instruction mnemonic suffix given and "
6269 "no register operands; can't size instruction"));
6275 unsigned int suffixes
;
6277 suffixes
= !i
.tm
.opcode_modifier
.no_bsuf
;
6278 if (!i
.tm
.opcode_modifier
.no_wsuf
)
6280 if (!i
.tm
.opcode_modifier
.no_lsuf
)
6282 if (!i
.tm
.opcode_modifier
.no_ldsuf
)
6284 if (!i
.tm
.opcode_modifier
.no_ssuf
)
6286 if (flag_code
== CODE_64BIT
&& !i
.tm
.opcode_modifier
.no_qsuf
)
6289 /* There are more than suffix matches. */
6290 if (i
.tm
.opcode_modifier
.w
6291 || ((suffixes
& (suffixes
- 1))
6292 && !i
.tm
.opcode_modifier
.defaultsize
6293 && !i
.tm
.opcode_modifier
.ignoresize
))
6295 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
6301 /* Change the opcode based on the operand size given by i.suffix. */
6304 /* Size floating point instruction. */
6305 case LONG_MNEM_SUFFIX
:
6306 if (i
.tm
.opcode_modifier
.floatmf
)
6308 i
.tm
.base_opcode
^= 4;
6312 case WORD_MNEM_SUFFIX
:
6313 case QWORD_MNEM_SUFFIX
:
6314 /* It's not a byte, select word/dword operation. */
6315 if (i
.tm
.opcode_modifier
.w
)
6317 if (i
.tm
.opcode_modifier
.shortform
)
6318 i
.tm
.base_opcode
|= 8;
6320 i
.tm
.base_opcode
|= 1;
6323 case SHORT_MNEM_SUFFIX
:
6324 /* Now select between word & dword operations via the operand
6325 size prefix, except for instructions that will ignore this
6327 if (i
.reg_operands
> 0
6328 && i
.types
[0].bitfield
.reg
6329 && i
.tm
.opcode_modifier
.addrprefixopreg
6330 && (i
.tm
.opcode_modifier
.immext
6331 || i
.operands
== 1))
6333 /* The address size override prefix changes the size of the
6335 if ((flag_code
== CODE_32BIT
6336 && i
.op
[0].regs
->reg_type
.bitfield
.word
)
6337 || (flag_code
!= CODE_32BIT
6338 && i
.op
[0].regs
->reg_type
.bitfield
.dword
))
6339 if (!add_prefix (ADDR_PREFIX_OPCODE
))
6342 else if (i
.suffix
!= QWORD_MNEM_SUFFIX
6343 && !i
.tm
.opcode_modifier
.ignoresize
6344 && !i
.tm
.opcode_modifier
.floatmf
6345 && !i
.tm
.opcode_modifier
.vex
6346 && !i
.tm
.opcode_modifier
.vexopcode
6347 && !is_evex_encoding (&i
.tm
)
6348 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
6349 || (flag_code
== CODE_64BIT
6350 && i
.tm
.opcode_modifier
.jumpbyte
)))
6352 unsigned int prefix
= DATA_PREFIX_OPCODE
;
6354 if (i
.tm
.opcode_modifier
.jumpbyte
) /* jcxz, loop */
6355 prefix
= ADDR_PREFIX_OPCODE
;
6357 if (!add_prefix (prefix
))
6361 /* Set mode64 for an operand. */
6362 if (i
.suffix
== QWORD_MNEM_SUFFIX
6363 && flag_code
== CODE_64BIT
6364 && !i
.tm
.opcode_modifier
.norex64
6365 /* Special case for xchg %rax,%rax. It is NOP and doesn't
6367 && ! (i
.operands
== 2
6368 && i
.tm
.base_opcode
== 0x90
6369 && i
.tm
.extension_opcode
== None
6370 && operand_type_equal (&i
.types
[0], &acc64
)
6371 && operand_type_equal (&i
.types
[1], &acc64
)))
6377 if (i
.reg_operands
!= 0
6379 && i
.tm
.opcode_modifier
.addrprefixopreg
6380 && !i
.tm
.opcode_modifier
.immext
)
6382 /* Check invalid register operand when the address size override
6383 prefix changes the size of register operands. */
6385 enum { need_word
, need_dword
, need_qword
} need
;
6387 if (flag_code
== CODE_32BIT
)
6388 need
= i
.prefix
[ADDR_PREFIX
] ? need_word
: need_dword
;
6391 if (i
.prefix
[ADDR_PREFIX
])
6394 need
= flag_code
== CODE_64BIT
? need_qword
: need_word
;
6397 for (op
= 0; op
< i
.operands
; op
++)
6398 if (i
.types
[op
].bitfield
.reg
6399 && ((need
== need_word
6400 && !i
.op
[op
].regs
->reg_type
.bitfield
.word
)
6401 || (need
== need_dword
6402 && !i
.op
[op
].regs
->reg_type
.bitfield
.dword
)
6403 || (need
== need_qword
6404 && !i
.op
[op
].regs
->reg_type
.bitfield
.qword
)))
6406 as_bad (_("invalid register operand size for `%s'"),
6416 check_byte_reg (void)
6420 for (op
= i
.operands
; --op
>= 0;)
6422 /* Skip non-register operands. */
6423 if (!i
.types
[op
].bitfield
.reg
)
6426 /* If this is an eight bit register, it's OK. If it's the 16 or
6427 32 bit version of an eight bit register, we will just use the
6428 low portion, and that's OK too. */
6429 if (i
.types
[op
].bitfield
.byte
)
6432 /* I/O port address operands are OK too. */
6433 if (i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
6436 /* crc32 doesn't generate this warning. */
6437 if (i
.tm
.base_opcode
== 0xf20f38f0)
6440 if ((i
.types
[op
].bitfield
.word
6441 || i
.types
[op
].bitfield
.dword
6442 || i
.types
[op
].bitfield
.qword
)
6443 && i
.op
[op
].regs
->reg_num
< 4
6444 /* Prohibit these changes in 64bit mode, since the lowering
6445 would be more complicated. */
6446 && flag_code
!= CODE_64BIT
)
6448 #if REGISTER_WARNINGS
6449 if (!quiet_warnings
)
6450 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6452 (i
.op
[op
].regs
+ (i
.types
[op
].bitfield
.word
6453 ? REGNAM_AL
- REGNAM_AX
6454 : REGNAM_AL
- REGNAM_EAX
))->reg_name
,
6456 i
.op
[op
].regs
->reg_name
,
6461 /* Any other register is bad. */
6462 if (i
.types
[op
].bitfield
.reg
6463 || i
.types
[op
].bitfield
.regmmx
6464 || i
.types
[op
].bitfield
.regsimd
6465 || i
.types
[op
].bitfield
.sreg2
6466 || i
.types
[op
].bitfield
.sreg3
6467 || i
.types
[op
].bitfield
.control
6468 || i
.types
[op
].bitfield
.debug
6469 || i
.types
[op
].bitfield
.test
)
6471 as_bad (_("`%s%s' not allowed with `%s%c'"),
6473 i
.op
[op
].regs
->reg_name
,
6483 check_long_reg (void)
6487 for (op
= i
.operands
; --op
>= 0;)
6488 /* Skip non-register operands. */
6489 if (!i
.types
[op
].bitfield
.reg
)
6491 /* Reject eight bit registers, except where the template requires
6492 them. (eg. movzb) */
6493 else if (i
.types
[op
].bitfield
.byte
6494 && (i
.tm
.operand_types
[op
].bitfield
.reg
6495 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6496 && (i
.tm
.operand_types
[op
].bitfield
.word
6497 || i
.tm
.operand_types
[op
].bitfield
.dword
))
6499 as_bad (_("`%s%s' not allowed with `%s%c'"),
6501 i
.op
[op
].regs
->reg_name
,
6506 /* Warn if the e prefix on a general reg is missing. */
6507 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
6508 && i
.types
[op
].bitfield
.word
6509 && (i
.tm
.operand_types
[op
].bitfield
.reg
6510 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6511 && i
.tm
.operand_types
[op
].bitfield
.dword
)
6513 /* Prohibit these changes in the 64bit mode, since the
6514 lowering is more complicated. */
6515 if (flag_code
== CODE_64BIT
)
6517 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6518 register_prefix
, i
.op
[op
].regs
->reg_name
,
6522 #if REGISTER_WARNINGS
6523 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6525 (i
.op
[op
].regs
+ REGNAM_EAX
- REGNAM_AX
)->reg_name
,
6526 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
6529 /* Warn if the r prefix on a general reg is present. */
6530 else if (i
.types
[op
].bitfield
.qword
6531 && (i
.tm
.operand_types
[op
].bitfield
.reg
6532 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6533 && i
.tm
.operand_types
[op
].bitfield
.dword
)
6536 && i
.tm
.opcode_modifier
.toqword
6537 && !i
.types
[0].bitfield
.regsimd
)
6539 /* Convert to QWORD. We want REX byte. */
6540 i
.suffix
= QWORD_MNEM_SUFFIX
;
6544 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6545 register_prefix
, i
.op
[op
].regs
->reg_name
,
6554 check_qword_reg (void)
6558 for (op
= i
.operands
; --op
>= 0; )
6559 /* Skip non-register operands. */
6560 if (!i
.types
[op
].bitfield
.reg
)
6562 /* Reject eight bit registers, except where the template requires
6563 them. (eg. movzb) */
6564 else if (i
.types
[op
].bitfield
.byte
6565 && (i
.tm
.operand_types
[op
].bitfield
.reg
6566 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6567 && (i
.tm
.operand_types
[op
].bitfield
.word
6568 || i
.tm
.operand_types
[op
].bitfield
.dword
))
6570 as_bad (_("`%s%s' not allowed with `%s%c'"),
6572 i
.op
[op
].regs
->reg_name
,
6577 /* Warn if the r prefix on a general reg is missing. */
6578 else if ((i
.types
[op
].bitfield
.word
6579 || i
.types
[op
].bitfield
.dword
)
6580 && (i
.tm
.operand_types
[op
].bitfield
.reg
6581 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6582 && i
.tm
.operand_types
[op
].bitfield
.qword
)
6584 /* Prohibit these changes in the 64bit mode, since the
6585 lowering is more complicated. */
6587 && i
.tm
.opcode_modifier
.todword
6588 && !i
.types
[0].bitfield
.regsimd
)
6590 /* Convert to DWORD. We don't want REX byte. */
6591 i
.suffix
= LONG_MNEM_SUFFIX
;
6595 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6596 register_prefix
, i
.op
[op
].regs
->reg_name
,
6605 check_word_reg (void)
6608 for (op
= i
.operands
; --op
>= 0;)
6609 /* Skip non-register operands. */
6610 if (!i
.types
[op
].bitfield
.reg
)
6612 /* Reject eight bit registers, except where the template requires
6613 them. (eg. movzb) */
6614 else if (i
.types
[op
].bitfield
.byte
6615 && (i
.tm
.operand_types
[op
].bitfield
.reg
6616 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6617 && (i
.tm
.operand_types
[op
].bitfield
.word
6618 || i
.tm
.operand_types
[op
].bitfield
.dword
))
6620 as_bad (_("`%s%s' not allowed with `%s%c'"),
6622 i
.op
[op
].regs
->reg_name
,
6627 /* Warn if the e or r prefix on a general reg is present. */
6628 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
6629 && (i
.types
[op
].bitfield
.dword
6630 || i
.types
[op
].bitfield
.qword
)
6631 && (i
.tm
.operand_types
[op
].bitfield
.reg
6632 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6633 && i
.tm
.operand_types
[op
].bitfield
.word
)
6635 /* Prohibit these changes in the 64bit mode, since the
6636 lowering is more complicated. */
6637 if (flag_code
== CODE_64BIT
)
6639 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6640 register_prefix
, i
.op
[op
].regs
->reg_name
,
6644 #if REGISTER_WARNINGS
6645 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6647 (i
.op
[op
].regs
+ REGNAM_AX
- REGNAM_EAX
)->reg_name
,
6648 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
6655 update_imm (unsigned int j
)
6657 i386_operand_type overlap
= i
.types
[j
];
6658 if ((overlap
.bitfield
.imm8
6659 || overlap
.bitfield
.imm8s
6660 || overlap
.bitfield
.imm16
6661 || overlap
.bitfield
.imm32
6662 || overlap
.bitfield
.imm32s
6663 || overlap
.bitfield
.imm64
)
6664 && !operand_type_equal (&overlap
, &imm8
)
6665 && !operand_type_equal (&overlap
, &imm8s
)
6666 && !operand_type_equal (&overlap
, &imm16
)
6667 && !operand_type_equal (&overlap
, &imm32
)
6668 && !operand_type_equal (&overlap
, &imm32s
)
6669 && !operand_type_equal (&overlap
, &imm64
))
6673 i386_operand_type temp
;
6675 operand_type_set (&temp
, 0);
6676 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
6678 temp
.bitfield
.imm8
= overlap
.bitfield
.imm8
;
6679 temp
.bitfield
.imm8s
= overlap
.bitfield
.imm8s
;
6681 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
6682 temp
.bitfield
.imm16
= overlap
.bitfield
.imm16
;
6683 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
6685 temp
.bitfield
.imm64
= overlap
.bitfield
.imm64
;
6686 temp
.bitfield
.imm32s
= overlap
.bitfield
.imm32s
;
6689 temp
.bitfield
.imm32
= overlap
.bitfield
.imm32
;
6692 else if (operand_type_equal (&overlap
, &imm16_32_32s
)
6693 || operand_type_equal (&overlap
, &imm16_32
)
6694 || operand_type_equal (&overlap
, &imm16_32s
))
6696 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
6701 if (!operand_type_equal (&overlap
, &imm8
)
6702 && !operand_type_equal (&overlap
, &imm8s
)
6703 && !operand_type_equal (&overlap
, &imm16
)
6704 && !operand_type_equal (&overlap
, &imm32
)
6705 && !operand_type_equal (&overlap
, &imm32s
)
6706 && !operand_type_equal (&overlap
, &imm64
))
6708 as_bad (_("no instruction mnemonic suffix given; "
6709 "can't determine immediate size"));
6713 i
.types
[j
] = overlap
;
6723 /* Update the first 2 immediate operands. */
6724 n
= i
.operands
> 2 ? 2 : i
.operands
;
6727 for (j
= 0; j
< n
; j
++)
6728 if (update_imm (j
) == 0)
6731 /* The 3rd operand can't be immediate operand. */
6732 gas_assert (operand_type_check (i
.types
[2], imm
) == 0);
6739 process_operands (void)
6741 /* Default segment register this instruction will use for memory
6742 accesses. 0 means unknown. This is only for optimizing out
6743 unnecessary segment overrides. */
6744 const seg_entry
*default_seg
= 0;
6746 if (i
.tm
.opcode_modifier
.sse2avx
&& i
.tm
.opcode_modifier
.vexvvvv
)
6748 unsigned int dupl
= i
.operands
;
6749 unsigned int dest
= dupl
- 1;
6752 /* The destination must be an xmm register. */
6753 gas_assert (i
.reg_operands
6754 && MAX_OPERANDS
> dupl
6755 && operand_type_equal (&i
.types
[dest
], ®xmm
));
6757 if (i
.tm
.operand_types
[0].bitfield
.acc
6758 && i
.tm
.operand_types
[0].bitfield
.xmmword
)
6760 if (i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
)
6762 /* Keep xmm0 for instructions with VEX prefix and 3
6764 i
.tm
.operand_types
[0].bitfield
.acc
= 0;
6765 i
.tm
.operand_types
[0].bitfield
.regsimd
= 1;
6770 /* We remove the first xmm0 and keep the number of
6771 operands unchanged, which in fact duplicates the
6773 for (j
= 1; j
< i
.operands
; j
++)
6775 i
.op
[j
- 1] = i
.op
[j
];
6776 i
.types
[j
- 1] = i
.types
[j
];
6777 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
6781 else if (i
.tm
.opcode_modifier
.implicit1stxmm0
)
6783 gas_assert ((MAX_OPERANDS
- 1) > dupl
6784 && (i
.tm
.opcode_modifier
.vexsources
6787 /* Add the implicit xmm0 for instructions with VEX prefix
6789 for (j
= i
.operands
; j
> 0; j
--)
6791 i
.op
[j
] = i
.op
[j
- 1];
6792 i
.types
[j
] = i
.types
[j
- 1];
6793 i
.tm
.operand_types
[j
] = i
.tm
.operand_types
[j
- 1];
6796 = (const reg_entry
*) hash_find (reg_hash
, "xmm0");
6797 i
.types
[0] = regxmm
;
6798 i
.tm
.operand_types
[0] = regxmm
;
6801 i
.reg_operands
+= 2;
6806 i
.op
[dupl
] = i
.op
[dest
];
6807 i
.types
[dupl
] = i
.types
[dest
];
6808 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
6817 i
.op
[dupl
] = i
.op
[dest
];
6818 i
.types
[dupl
] = i
.types
[dest
];
6819 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
6822 if (i
.tm
.opcode_modifier
.immext
)
6825 else if (i
.tm
.operand_types
[0].bitfield
.acc
6826 && i
.tm
.operand_types
[0].bitfield
.xmmword
)
6830 for (j
= 1; j
< i
.operands
; j
++)
6832 i
.op
[j
- 1] = i
.op
[j
];
6833 i
.types
[j
- 1] = i
.types
[j
];
6835 /* We need to adjust fields in i.tm since they are used by
6836 build_modrm_byte. */
6837 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
6844 else if (i
.tm
.opcode_modifier
.implicitquadgroup
)
6846 unsigned int regnum
, first_reg_in_group
, last_reg_in_group
;
6848 /* The second operand must be {x,y,z}mmN, where N is a multiple of 4. */
6849 gas_assert (i
.operands
>= 2 && i
.types
[1].bitfield
.regsimd
);
6850 regnum
= register_number (i
.op
[1].regs
);
6851 first_reg_in_group
= regnum
& ~3;
6852 last_reg_in_group
= first_reg_in_group
+ 3;
6853 if (regnum
!= first_reg_in_group
)
6854 as_warn (_("source register `%s%s' implicitly denotes"
6855 " `%s%.3s%u' to `%s%.3s%u' source group in `%s'"),
6856 register_prefix
, i
.op
[1].regs
->reg_name
,
6857 register_prefix
, i
.op
[1].regs
->reg_name
, first_reg_in_group
,
6858 register_prefix
, i
.op
[1].regs
->reg_name
, last_reg_in_group
,
6861 else if (i
.tm
.opcode_modifier
.regkludge
)
6863 /* The imul $imm, %reg instruction is converted into
6864 imul $imm, %reg, %reg, and the clr %reg instruction
6865 is converted into xor %reg, %reg. */
6867 unsigned int first_reg_op
;
6869 if (operand_type_check (i
.types
[0], reg
))
6873 /* Pretend we saw the extra register operand. */
6874 gas_assert (i
.reg_operands
== 1
6875 && i
.op
[first_reg_op
+ 1].regs
== 0);
6876 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
6877 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
6882 if (i
.tm
.opcode_modifier
.shortform
)
6884 if (i
.types
[0].bitfield
.sreg2
6885 || i
.types
[0].bitfield
.sreg3
)
6887 if (i
.tm
.base_opcode
== POP_SEG_SHORT
6888 && i
.op
[0].regs
->reg_num
== 1)
6890 as_bad (_("you can't `pop %scs'"), register_prefix
);
6893 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
6894 if ((i
.op
[0].regs
->reg_flags
& RegRex
) != 0)
6899 /* The register or float register operand is in operand
6903 if ((i
.types
[0].bitfield
.reg
&& i
.types
[0].bitfield
.tbyte
)
6904 || operand_type_check (i
.types
[0], reg
))
6908 /* Register goes in low 3 bits of opcode. */
6909 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
6910 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
6912 if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
6914 /* Warn about some common errors, but press on regardless.
6915 The first case can be generated by gcc (<= 2.8.1). */
6916 if (i
.operands
== 2)
6918 /* Reversed arguments on faddp, fsubp, etc. */
6919 as_warn (_("translating to `%s %s%s,%s%s'"), i
.tm
.name
,
6920 register_prefix
, i
.op
[!intel_syntax
].regs
->reg_name
,
6921 register_prefix
, i
.op
[intel_syntax
].regs
->reg_name
);
6925 /* Extraneous `l' suffix on fp insn. */
6926 as_warn (_("translating to `%s %s%s'"), i
.tm
.name
,
6927 register_prefix
, i
.op
[0].regs
->reg_name
);
6932 else if (i
.tm
.opcode_modifier
.modrm
)
6934 /* The opcode is completed (modulo i.tm.extension_opcode which
6935 must be put into the modrm byte). Now, we make the modrm and
6936 index base bytes based on all the info we've collected. */
6938 default_seg
= build_modrm_byte ();
6940 else if ((i
.tm
.base_opcode
& ~0x3) == MOV_AX_DISP32
)
6944 else if (i
.tm
.opcode_modifier
.isstring
)
6946 /* For the string instructions that allow a segment override
6947 on one of their operands, the default segment is ds. */
6951 if (i
.tm
.base_opcode
== 0x8d /* lea */
6954 as_warn (_("segment override on `%s' is ineffectual"), i
.tm
.name
);
6956 /* If a segment was explicitly specified, and the specified segment
6957 is not the default, use an opcode prefix to select it. If we
6958 never figured out what the default segment is, then default_seg
6959 will be zero at this point, and the specified segment prefix will
6961 if ((i
.seg
[0]) && (i
.seg
[0] != default_seg
))
6963 if (!add_prefix (i
.seg
[0]->seg_prefix
))
6969 static const seg_entry
*
6970 build_modrm_byte (void)
6972 const seg_entry
*default_seg
= 0;
6973 unsigned int source
, dest
;
6976 vex_3_sources
= i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
;
6979 unsigned int nds
, reg_slot
;
6982 dest
= i
.operands
- 1;
6985 /* There are 2 kinds of instructions:
6986 1. 5 operands: 4 register operands or 3 register operands
6987 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
6988 VexW0 or VexW1. The destination must be either XMM, YMM or
6990 2. 4 operands: 4 register operands or 3 register operands
6991 plus 1 memory operand, with VexXDS. */
6992 gas_assert ((i
.reg_operands
== 4
6993 || (i
.reg_operands
== 3 && i
.mem_operands
== 1))
6994 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
6995 && i
.tm
.opcode_modifier
.vexw
6996 && i
.tm
.operand_types
[dest
].bitfield
.regsimd
);
6998 /* If VexW1 is set, the first non-immediate operand is the source and
6999 the second non-immediate one is encoded in the immediate operand. */
7000 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
7002 source
= i
.imm_operands
;
7003 reg_slot
= i
.imm_operands
+ 1;
7007 source
= i
.imm_operands
+ 1;
7008 reg_slot
= i
.imm_operands
;
7011 if (i
.imm_operands
== 0)
7013 /* When there is no immediate operand, generate an 8bit
7014 immediate operand to encode the first operand. */
7015 exp
= &im_expressions
[i
.imm_operands
++];
7016 i
.op
[i
.operands
].imms
= exp
;
7017 i
.types
[i
.operands
] = imm8
;
7020 gas_assert (i
.tm
.operand_types
[reg_slot
].bitfield
.regsimd
);
7021 exp
->X_op
= O_constant
;
7022 exp
->X_add_number
= register_number (i
.op
[reg_slot
].regs
) << 4;
7023 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
7027 unsigned int imm_slot
;
7029 gas_assert (i
.imm_operands
== 1 && i
.types
[0].bitfield
.vec_imm4
);
7031 if (i
.tm
.opcode_modifier
.immext
)
7033 /* When ImmExt is set, the immediate byte is the last
7035 imm_slot
= i
.operands
- 1;
7043 /* Turn on Imm8 so that output_imm will generate it. */
7044 i
.types
[imm_slot
].bitfield
.imm8
= 1;
7047 gas_assert (i
.tm
.operand_types
[reg_slot
].bitfield
.regsimd
);
7048 i
.op
[imm_slot
].imms
->X_add_number
7049 |= register_number (i
.op
[reg_slot
].regs
) << 4;
7050 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
7053 gas_assert (i
.tm
.operand_types
[nds
].bitfield
.regsimd
);
7054 i
.vex
.register_specifier
= i
.op
[nds
].regs
;
7059 /* i.reg_operands MUST be the number of real register operands;
7060 implicit registers do not count. If there are 3 register
7061 operands, it must be a instruction with VexNDS. For a
7062 instruction with VexNDD, the destination register is encoded
7063 in VEX prefix. If there are 4 register operands, it must be
7064 a instruction with VEX prefix and 3 sources. */
7065 if (i
.mem_operands
== 0
7066 && ((i
.reg_operands
== 2
7067 && i
.tm
.opcode_modifier
.vexvvvv
<= VEXXDS
)
7068 || (i
.reg_operands
== 3
7069 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
7070 || (i
.reg_operands
== 4 && vex_3_sources
)))
7078 /* When there are 3 operands, one of them may be immediate,
7079 which may be the first or the last operand. Otherwise,
7080 the first operand must be shift count register (cl) or it
7081 is an instruction with VexNDS. */
7082 gas_assert (i
.imm_operands
== 1
7083 || (i
.imm_operands
== 0
7084 && (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
7085 || i
.types
[0].bitfield
.shiftcount
)));
7086 if (operand_type_check (i
.types
[0], imm
)
7087 || i
.types
[0].bitfield
.shiftcount
)
7093 /* When there are 4 operands, the first two must be 8bit
7094 immediate operands. The source operand will be the 3rd
7097 For instructions with VexNDS, if the first operand
7098 an imm8, the source operand is the 2nd one. If the last
7099 operand is imm8, the source operand is the first one. */
7100 gas_assert ((i
.imm_operands
== 2
7101 && i
.types
[0].bitfield
.imm8
7102 && i
.types
[1].bitfield
.imm8
)
7103 || (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
7104 && i
.imm_operands
== 1
7105 && (i
.types
[0].bitfield
.imm8
7106 || i
.types
[i
.operands
- 1].bitfield
.imm8
7108 if (i
.imm_operands
== 2)
7112 if (i
.types
[0].bitfield
.imm8
)
7119 if (is_evex_encoding (&i
.tm
))
7121 /* For EVEX instructions, when there are 5 operands, the
7122 first one must be immediate operand. If the second one
7123 is immediate operand, the source operand is the 3th
7124 one. If the last one is immediate operand, the source
7125 operand is the 2nd one. */
7126 gas_assert (i
.imm_operands
== 2
7127 && i
.tm
.opcode_modifier
.sae
7128 && operand_type_check (i
.types
[0], imm
));
7129 if (operand_type_check (i
.types
[1], imm
))
7131 else if (operand_type_check (i
.types
[4], imm
))
7145 /* RC/SAE operand could be between DEST and SRC. That happens
7146 when one operand is GPR and the other one is XMM/YMM/ZMM
7148 if (i
.rounding
&& i
.rounding
->operand
== (int) dest
)
7151 if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
7153 /* For instructions with VexNDS, the register-only source
7154 operand must be a 32/64bit integer, XMM, YMM, ZMM, or mask
7155 register. It is encoded in VEX prefix. We need to
7156 clear RegMem bit before calling operand_type_equal. */
7158 i386_operand_type op
;
7161 /* Check register-only source operand when two source
7162 operands are swapped. */
7163 if (!i
.tm
.operand_types
[source
].bitfield
.baseindex
7164 && i
.tm
.operand_types
[dest
].bitfield
.baseindex
)
7172 op
= i
.tm
.operand_types
[vvvv
];
7173 op
.bitfield
.regmem
= 0;
7174 if ((dest
+ 1) >= i
.operands
7175 || ((!op
.bitfield
.reg
7176 || (!op
.bitfield
.dword
&& !op
.bitfield
.qword
))
7177 && !op
.bitfield
.regsimd
7178 && !operand_type_equal (&op
, ®mask
)))
7180 i
.vex
.register_specifier
= i
.op
[vvvv
].regs
;
7186 /* One of the register operands will be encoded in the i.tm.reg
7187 field, the other in the combined i.tm.mode and i.tm.regmem
7188 fields. If no form of this instruction supports a memory
7189 destination operand, then we assume the source operand may
7190 sometimes be a memory operand and so we need to store the
7191 destination in the i.rm.reg field. */
7192 if (!i
.tm
.operand_types
[dest
].bitfield
.regmem
7193 && operand_type_check (i
.tm
.operand_types
[dest
], anymem
) == 0)
7195 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
7196 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
7197 if (i
.op
[dest
].regs
->reg_type
.bitfield
.regmmx
7198 || i
.op
[source
].regs
->reg_type
.bitfield
.regmmx
)
7199 i
.has_regmmx
= TRUE
;
7200 else if (i
.op
[dest
].regs
->reg_type
.bitfield
.regsimd
7201 || i
.op
[source
].regs
->reg_type
.bitfield
.regsimd
)
7203 if (i
.types
[dest
].bitfield
.zmmword
7204 || i
.types
[source
].bitfield
.zmmword
)
7205 i
.has_regzmm
= TRUE
;
7206 else if (i
.types
[dest
].bitfield
.ymmword
7207 || i
.types
[source
].bitfield
.ymmword
)
7208 i
.has_regymm
= TRUE
;
7210 i
.has_regxmm
= TRUE
;
7212 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
7214 if ((i
.op
[dest
].regs
->reg_flags
& RegVRex
) != 0)
7216 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
7218 if ((i
.op
[source
].regs
->reg_flags
& RegVRex
) != 0)
7223 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
7224 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
7225 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
7227 if ((i
.op
[dest
].regs
->reg_flags
& RegVRex
) != 0)
7229 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
7231 if ((i
.op
[source
].regs
->reg_flags
& RegVRex
) != 0)
7234 if (flag_code
!= CODE_64BIT
&& (i
.rex
& REX_R
))
7236 if (!i
.types
[i
.tm
.operand_types
[0].bitfield
.regmem
].bitfield
.control
)
7239 add_prefix (LOCK_PREFIX_OPCODE
);
7243 { /* If it's not 2 reg operands... */
7248 unsigned int fake_zero_displacement
= 0;
7251 for (op
= 0; op
< i
.operands
; op
++)
7252 if (operand_type_check (i
.types
[op
], anymem
))
7254 gas_assert (op
< i
.operands
);
7256 if (i
.tm
.opcode_modifier
.vecsib
)
7258 if (i
.index_reg
->reg_num
== RegIZ
)
7261 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
7264 i
.sib
.base
= NO_BASE_REGISTER
;
7265 i
.sib
.scale
= i
.log2_scale_factor
;
7266 i
.types
[op
].bitfield
.disp8
= 0;
7267 i
.types
[op
].bitfield
.disp16
= 0;
7268 i
.types
[op
].bitfield
.disp64
= 0;
7269 if (flag_code
!= CODE_64BIT
|| i
.prefix
[ADDR_PREFIX
])
7271 /* Must be 32 bit */
7272 i
.types
[op
].bitfield
.disp32
= 1;
7273 i
.types
[op
].bitfield
.disp32s
= 0;
7277 i
.types
[op
].bitfield
.disp32
= 0;
7278 i
.types
[op
].bitfield
.disp32s
= 1;
7281 i
.sib
.index
= i
.index_reg
->reg_num
;
7282 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
7284 if ((i
.index_reg
->reg_flags
& RegVRex
) != 0)
7290 if (i
.base_reg
== 0)
7293 if (!i
.disp_operands
)
7294 fake_zero_displacement
= 1;
7295 if (i
.index_reg
== 0)
7297 i386_operand_type newdisp
;
7299 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
7300 /* Operand is just <disp> */
7301 if (flag_code
== CODE_64BIT
)
7303 /* 64bit mode overwrites the 32bit absolute
7304 addressing by RIP relative addressing and
7305 absolute addressing is encoded by one of the
7306 redundant SIB forms. */
7307 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
7308 i
.sib
.base
= NO_BASE_REGISTER
;
7309 i
.sib
.index
= NO_INDEX_REGISTER
;
7310 newdisp
= (!i
.prefix
[ADDR_PREFIX
] ? disp32s
: disp32
);
7312 else if ((flag_code
== CODE_16BIT
)
7313 ^ (i
.prefix
[ADDR_PREFIX
] != 0))
7315 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
7320 i
.rm
.regmem
= NO_BASE_REGISTER
;
7323 i
.types
[op
] = operand_type_and_not (i
.types
[op
], anydisp
);
7324 i
.types
[op
] = operand_type_or (i
.types
[op
], newdisp
);
7326 else if (!i
.tm
.opcode_modifier
.vecsib
)
7328 /* !i.base_reg && i.index_reg */
7329 if (i
.index_reg
->reg_num
== RegIZ
)
7330 i
.sib
.index
= NO_INDEX_REGISTER
;
7332 i
.sib
.index
= i
.index_reg
->reg_num
;
7333 i
.sib
.base
= NO_BASE_REGISTER
;
7334 i
.sib
.scale
= i
.log2_scale_factor
;
7335 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
7336 i
.types
[op
].bitfield
.disp8
= 0;
7337 i
.types
[op
].bitfield
.disp16
= 0;
7338 i
.types
[op
].bitfield
.disp64
= 0;
7339 if (flag_code
!= CODE_64BIT
|| i
.prefix
[ADDR_PREFIX
])
7341 /* Must be 32 bit */
7342 i
.types
[op
].bitfield
.disp32
= 1;
7343 i
.types
[op
].bitfield
.disp32s
= 0;
7347 i
.types
[op
].bitfield
.disp32
= 0;
7348 i
.types
[op
].bitfield
.disp32s
= 1;
7350 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
7354 /* RIP addressing for 64bit mode. */
7355 else if (i
.base_reg
->reg_num
== RegIP
)
7357 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
7358 i
.rm
.regmem
= NO_BASE_REGISTER
;
7359 i
.types
[op
].bitfield
.disp8
= 0;
7360 i
.types
[op
].bitfield
.disp16
= 0;
7361 i
.types
[op
].bitfield
.disp32
= 0;
7362 i
.types
[op
].bitfield
.disp32s
= 1;
7363 i
.types
[op
].bitfield
.disp64
= 0;
7364 i
.flags
[op
] |= Operand_PCrel
;
7365 if (! i
.disp_operands
)
7366 fake_zero_displacement
= 1;
7368 else if (i
.base_reg
->reg_type
.bitfield
.word
)
7370 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
7371 switch (i
.base_reg
->reg_num
)
7374 if (i
.index_reg
== 0)
7376 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
7377 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
7381 if (i
.index_reg
== 0)
7384 if (operand_type_check (i
.types
[op
], disp
) == 0)
7386 /* fake (%bp) into 0(%bp) */
7387 i
.types
[op
].bitfield
.disp8
= 1;
7388 fake_zero_displacement
= 1;
7391 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
7392 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
7394 default: /* (%si) -> 4 or (%di) -> 5 */
7395 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
7397 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
7399 else /* i.base_reg and 32/64 bit mode */
7401 if (flag_code
== CODE_64BIT
7402 && operand_type_check (i
.types
[op
], disp
))
7404 i
.types
[op
].bitfield
.disp16
= 0;
7405 i
.types
[op
].bitfield
.disp64
= 0;
7406 if (i
.prefix
[ADDR_PREFIX
] == 0)
7408 i
.types
[op
].bitfield
.disp32
= 0;
7409 i
.types
[op
].bitfield
.disp32s
= 1;
7413 i
.types
[op
].bitfield
.disp32
= 1;
7414 i
.types
[op
].bitfield
.disp32s
= 0;
7418 if (!i
.tm
.opcode_modifier
.vecsib
)
7419 i
.rm
.regmem
= i
.base_reg
->reg_num
;
7420 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
7422 i
.sib
.base
= i
.base_reg
->reg_num
;
7423 /* x86-64 ignores REX prefix bit here to avoid decoder
7425 if (!(i
.base_reg
->reg_flags
& RegRex
)
7426 && (i
.base_reg
->reg_num
== EBP_REG_NUM
7427 || i
.base_reg
->reg_num
== ESP_REG_NUM
))
7429 if (i
.base_reg
->reg_num
== 5 && i
.disp_operands
== 0)
7431 fake_zero_displacement
= 1;
7432 i
.types
[op
].bitfield
.disp8
= 1;
7434 i
.sib
.scale
= i
.log2_scale_factor
;
7435 if (i
.index_reg
== 0)
7437 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
7438 /* <disp>(%esp) becomes two byte modrm with no index
7439 register. We've already stored the code for esp
7440 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
7441 Any base register besides %esp will not use the
7442 extra modrm byte. */
7443 i
.sib
.index
= NO_INDEX_REGISTER
;
7445 else if (!i
.tm
.opcode_modifier
.vecsib
)
7447 if (i
.index_reg
->reg_num
== RegIZ
)
7448 i
.sib
.index
= NO_INDEX_REGISTER
;
7450 i
.sib
.index
= i
.index_reg
->reg_num
;
7451 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
7452 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
7457 && (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
7458 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
))
7462 if (!fake_zero_displacement
7466 fake_zero_displacement
= 1;
7467 if (i
.disp_encoding
== disp_encoding_8bit
)
7468 i
.types
[op
].bitfield
.disp8
= 1;
7470 i
.types
[op
].bitfield
.disp32
= 1;
7472 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
7476 if (fake_zero_displacement
)
7478 /* Fakes a zero displacement assuming that i.types[op]
7479 holds the correct displacement size. */
7482 gas_assert (i
.op
[op
].disps
== 0);
7483 exp
= &disp_expressions
[i
.disp_operands
++];
7484 i
.op
[op
].disps
= exp
;
7485 exp
->X_op
= O_constant
;
7486 exp
->X_add_number
= 0;
7487 exp
->X_add_symbol
= (symbolS
*) 0;
7488 exp
->X_op_symbol
= (symbolS
*) 0;
7496 if (i
.tm
.opcode_modifier
.vexsources
== XOP2SOURCES
)
7498 if (operand_type_check (i
.types
[0], imm
))
7499 i
.vex
.register_specifier
= NULL
;
7502 /* VEX.vvvv encodes one of the sources when the first
7503 operand is not an immediate. */
7504 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
7505 i
.vex
.register_specifier
= i
.op
[0].regs
;
7507 i
.vex
.register_specifier
= i
.op
[1].regs
;
7510 /* Destination is a XMM register encoded in the ModRM.reg
7512 i
.rm
.reg
= i
.op
[2].regs
->reg_num
;
7513 if ((i
.op
[2].regs
->reg_flags
& RegRex
) != 0)
7516 /* ModRM.rm and VEX.B encodes the other source. */
7517 if (!i
.mem_operands
)
7521 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
7522 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
7524 i
.rm
.regmem
= i
.op
[0].regs
->reg_num
;
7526 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
7530 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXLWP
)
7532 i
.vex
.register_specifier
= i
.op
[2].regs
;
7533 if (!i
.mem_operands
)
7536 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
7537 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
7541 /* Fill in i.rm.reg or i.rm.regmem field with register operand
7542 (if any) based on i.tm.extension_opcode. Again, we must be
7543 careful to make sure that segment/control/debug/test/MMX
7544 registers are coded into the i.rm.reg field. */
7545 else if (i
.reg_operands
)
7548 unsigned int vex_reg
= ~0;
7550 for (op
= 0; op
< i
.operands
; op
++)
7552 if (i
.types
[op
].bitfield
.reg
7553 || i
.types
[op
].bitfield
.regbnd
7554 || i
.types
[op
].bitfield
.regmask
7555 || i
.types
[op
].bitfield
.sreg2
7556 || i
.types
[op
].bitfield
.sreg3
7557 || i
.types
[op
].bitfield
.control
7558 || i
.types
[op
].bitfield
.debug
7559 || i
.types
[op
].bitfield
.test
)
7561 if (i
.types
[op
].bitfield
.regsimd
)
7563 if (i
.types
[op
].bitfield
.zmmword
)
7564 i
.has_regzmm
= TRUE
;
7565 else if (i
.types
[op
].bitfield
.ymmword
)
7566 i
.has_regymm
= TRUE
;
7568 i
.has_regxmm
= TRUE
;
7571 if (i
.types
[op
].bitfield
.regmmx
)
7573 i
.has_regmmx
= TRUE
;
7580 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
7582 /* For instructions with VexNDS, the register-only
7583 source operand is encoded in VEX prefix. */
7584 gas_assert (mem
!= (unsigned int) ~0);
7589 gas_assert (op
< i
.operands
);
7593 /* Check register-only source operand when two source
7594 operands are swapped. */
7595 if (!i
.tm
.operand_types
[op
].bitfield
.baseindex
7596 && i
.tm
.operand_types
[op
+ 1].bitfield
.baseindex
)
7600 gas_assert (mem
== (vex_reg
+ 1)
7601 && op
< i
.operands
);
7606 gas_assert (vex_reg
< i
.operands
);
7610 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXNDD
)
7612 /* For instructions with VexNDD, the register destination
7613 is encoded in VEX prefix. */
7614 if (i
.mem_operands
== 0)
7616 /* There is no memory operand. */
7617 gas_assert ((op
+ 2) == i
.operands
);
7622 /* There are only 2 non-immediate operands. */
7623 gas_assert (op
< i
.imm_operands
+ 2
7624 && i
.operands
== i
.imm_operands
+ 2);
7625 vex_reg
= i
.imm_operands
+ 1;
7629 gas_assert (op
< i
.operands
);
7631 if (vex_reg
!= (unsigned int) ~0)
7633 i386_operand_type
*type
= &i
.tm
.operand_types
[vex_reg
];
7635 if ((!type
->bitfield
.reg
7636 || (!type
->bitfield
.dword
&& !type
->bitfield
.qword
))
7637 && !type
->bitfield
.regsimd
7638 && !operand_type_equal (type
, ®mask
))
7641 i
.vex
.register_specifier
= i
.op
[vex_reg
].regs
;
7644 /* Don't set OP operand twice. */
7647 /* If there is an extension opcode to put here, the
7648 register number must be put into the regmem field. */
7649 if (i
.tm
.extension_opcode
!= None
)
7651 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
7652 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
7654 if ((i
.op
[op
].regs
->reg_flags
& RegVRex
) != 0)
7659 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
7660 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
7662 if ((i
.op
[op
].regs
->reg_flags
& RegVRex
) != 0)
7667 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
7668 must set it to 3 to indicate this is a register operand
7669 in the regmem field. */
7670 if (!i
.mem_operands
)
7674 /* Fill in i.rm.reg field with extension opcode (if any). */
7675 if (i
.tm
.extension_opcode
!= None
)
7676 i
.rm
.reg
= i
.tm
.extension_opcode
;
7682 output_branch (void)
7688 relax_substateT subtype
;
7692 code16
= flag_code
== CODE_16BIT
? CODE16
: 0;
7693 size
= i
.disp_encoding
== disp_encoding_32bit
? BIG
: SMALL
;
7696 if (i
.prefix
[DATA_PREFIX
] != 0)
7702 /* Pentium4 branch hints. */
7703 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
7704 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
7709 if (i
.prefix
[REX_PREFIX
] != 0)
7715 /* BND prefixed jump. */
7716 if (i
.prefix
[BND_PREFIX
] != 0)
7718 FRAG_APPEND_1_CHAR (i
.prefix
[BND_PREFIX
]);
7722 if (i
.prefixes
!= 0 && !intel_syntax
)
7723 as_warn (_("skipping prefixes on this instruction"));
7725 /* It's always a symbol; End frag & setup for relax.
7726 Make sure there is enough room in this frag for the largest
7727 instruction we may generate in md_convert_frag. This is 2
7728 bytes for the opcode and room for the prefix and largest
7730 frag_grow (prefix
+ 2 + 4);
7731 /* Prefix and 1 opcode byte go in fr_fix. */
7732 p
= frag_more (prefix
+ 1);
7733 if (i
.prefix
[DATA_PREFIX
] != 0)
7734 *p
++ = DATA_PREFIX_OPCODE
;
7735 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
7736 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
7737 *p
++ = i
.prefix
[SEG_PREFIX
];
7738 if (i
.prefix
[REX_PREFIX
] != 0)
7739 *p
++ = i
.prefix
[REX_PREFIX
];
7740 *p
= i
.tm
.base_opcode
;
7742 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
7743 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, size
);
7744 else if (cpu_arch_flags
.bitfield
.cpui386
)
7745 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, size
);
7747 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, size
);
7750 sym
= i
.op
[0].disps
->X_add_symbol
;
7751 off
= i
.op
[0].disps
->X_add_number
;
7753 if (i
.op
[0].disps
->X_op
!= O_constant
7754 && i
.op
[0].disps
->X_op
!= O_symbol
)
7756 /* Handle complex expressions. */
7757 sym
= make_expr_symbol (i
.op
[0].disps
);
7761 /* 1 possible extra opcode + 4 byte displacement go in var part.
7762 Pass reloc in fr_var. */
7763 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
7766 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7767 /* Return TRUE iff PLT32 relocation should be used for branching to
7771 need_plt32_p (symbolS
*s
)
7773 /* PLT32 relocation is ELF only. */
7777 /* Since there is no need to prepare for PLT branch on x86-64, we
7778 can generate R_X86_64_PLT32, instead of R_X86_64_PC32, which can
7779 be used as a marker for 32-bit PC-relative branches. */
7783 /* Weak or undefined symbol need PLT32 relocation. */
7784 if (S_IS_WEAK (s
) || !S_IS_DEFINED (s
))
7787 /* Non-global symbol doesn't need PLT32 relocation. */
7788 if (! S_IS_EXTERNAL (s
))
7791 /* Other global symbols need PLT32 relocation. NB: Symbol with
7792 non-default visibilities are treated as normal global symbol
7793 so that PLT32 relocation can be used as a marker for 32-bit
7794 PC-relative branches. It is useful for linker relaxation. */
7805 bfd_reloc_code_real_type jump_reloc
= i
.reloc
[0];
7807 if (i
.tm
.opcode_modifier
.jumpbyte
)
7809 /* This is a loop or jecxz type instruction. */
7811 if (i
.prefix
[ADDR_PREFIX
] != 0)
7813 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
7816 /* Pentium4 branch hints. */
7817 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
7818 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
7820 FRAG_APPEND_1_CHAR (i
.prefix
[SEG_PREFIX
]);
7829 if (flag_code
== CODE_16BIT
)
7832 if (i
.prefix
[DATA_PREFIX
] != 0)
7834 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
7844 if (i
.prefix
[REX_PREFIX
] != 0)
7846 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
7850 /* BND prefixed jump. */
7851 if (i
.prefix
[BND_PREFIX
] != 0)
7853 FRAG_APPEND_1_CHAR (i
.prefix
[BND_PREFIX
]);
7857 if (i
.prefixes
!= 0 && !intel_syntax
)
7858 as_warn (_("skipping prefixes on this instruction"));
7860 p
= frag_more (i
.tm
.opcode_length
+ size
);
7861 switch (i
.tm
.opcode_length
)
7864 *p
++ = i
.tm
.base_opcode
>> 8;
7867 *p
++ = i
.tm
.base_opcode
;
7873 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7875 && jump_reloc
== NO_RELOC
7876 && need_plt32_p (i
.op
[0].disps
->X_add_symbol
))
7877 jump_reloc
= BFD_RELOC_X86_64_PLT32
;
7880 jump_reloc
= reloc (size
, 1, 1, jump_reloc
);
7882 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
7883 i
.op
[0].disps
, 1, jump_reloc
);
7885 /* All jumps handled here are signed, but don't use a signed limit
7886 check for 32 and 16 bit jumps as we want to allow wrap around at
7887 4G and 64k respectively. */
7889 fixP
->fx_signed
= 1;
7893 output_interseg_jump (void)
7901 if (flag_code
== CODE_16BIT
)
7905 if (i
.prefix
[DATA_PREFIX
] != 0)
7911 if (i
.prefix
[REX_PREFIX
] != 0)
7921 if (i
.prefixes
!= 0 && !intel_syntax
)
7922 as_warn (_("skipping prefixes on this instruction"));
7924 /* 1 opcode; 2 segment; offset */
7925 p
= frag_more (prefix
+ 1 + 2 + size
);
7927 if (i
.prefix
[DATA_PREFIX
] != 0)
7928 *p
++ = DATA_PREFIX_OPCODE
;
7930 if (i
.prefix
[REX_PREFIX
] != 0)
7931 *p
++ = i
.prefix
[REX_PREFIX
];
7933 *p
++ = i
.tm
.base_opcode
;
7934 if (i
.op
[1].imms
->X_op
== O_constant
)
7936 offsetT n
= i
.op
[1].imms
->X_add_number
;
7939 && !fits_in_unsigned_word (n
)
7940 && !fits_in_signed_word (n
))
7942 as_bad (_("16-bit jump out of range"));
7945 md_number_to_chars (p
, n
, size
);
7948 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
7949 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
7950 if (i
.op
[0].imms
->X_op
!= O_constant
)
7951 as_bad (_("can't handle non absolute segment in `%s'"),
7953 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
7956 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7961 asection
*seg
= now_seg
;
7962 subsegT subseg
= now_subseg
;
7964 unsigned int alignment
, align_size_1
;
7965 unsigned int isa_1_descsz
, feature_2_descsz
, descsz
;
7966 unsigned int isa_1_descsz_raw
, feature_2_descsz_raw
;
7967 unsigned int padding
;
7969 if (!IS_ELF
|| !x86_used_note
)
7972 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_X86
;
7974 /* The .note.gnu.property section layout:
7976 Field Length Contents
7979 n_descsz 4 The note descriptor size
7980 n_type 4 NT_GNU_PROPERTY_TYPE_0
7982 n_desc n_descsz The program property array
7986 /* Create the .note.gnu.property section. */
7987 sec
= subseg_new (NOTE_GNU_PROPERTY_SECTION_NAME
, 0);
7988 bfd_set_section_flags (stdoutput
, sec
,
7995 if (get_elf_backend_data (stdoutput
)->s
->elfclass
== ELFCLASS64
)
8006 bfd_set_section_alignment (stdoutput
, sec
, alignment
);
8007 elf_section_type (sec
) = SHT_NOTE
;
8009 /* GNU_PROPERTY_X86_ISA_1_USED: 4-byte type + 4-byte data size
8011 isa_1_descsz_raw
= 4 + 4 + 4;
8012 /* Align GNU_PROPERTY_X86_ISA_1_USED. */
8013 isa_1_descsz
= (isa_1_descsz_raw
+ align_size_1
) & ~align_size_1
;
8015 feature_2_descsz_raw
= isa_1_descsz
;
8016 /* GNU_PROPERTY_X86_FEATURE_2_USED: 4-byte type + 4-byte data size
8018 feature_2_descsz_raw
+= 4 + 4 + 4;
8019 /* Align GNU_PROPERTY_X86_FEATURE_2_USED. */
8020 feature_2_descsz
= ((feature_2_descsz_raw
+ align_size_1
)
8023 descsz
= feature_2_descsz
;
8024 /* Section size: n_namsz + n_descsz + n_type + n_name + n_descsz. */
8025 p
= frag_more (4 + 4 + 4 + 4 + descsz
);
8027 /* Write n_namsz. */
8028 md_number_to_chars (p
, (valueT
) 4, 4);
8030 /* Write n_descsz. */
8031 md_number_to_chars (p
+ 4, (valueT
) descsz
, 4);
8034 md_number_to_chars (p
+ 4 * 2, (valueT
) NT_GNU_PROPERTY_TYPE_0
, 4);
8037 memcpy (p
+ 4 * 3, "GNU", 4);
8039 /* Write 4-byte type. */
8040 md_number_to_chars (p
+ 4 * 4,
8041 (valueT
) GNU_PROPERTY_X86_ISA_1_USED
, 4);
8043 /* Write 4-byte data size. */
8044 md_number_to_chars (p
+ 4 * 5, (valueT
) 4, 4);
8046 /* Write 4-byte data. */
8047 md_number_to_chars (p
+ 4 * 6, (valueT
) x86_isa_1_used
, 4);
8049 /* Zero out paddings. */
8050 padding
= isa_1_descsz
- isa_1_descsz_raw
;
8052 memset (p
+ 4 * 7, 0, padding
);
8054 /* Write 4-byte type. */
8055 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 4,
8056 (valueT
) GNU_PROPERTY_X86_FEATURE_2_USED
, 4);
8058 /* Write 4-byte data size. */
8059 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 5, (valueT
) 4, 4);
8061 /* Write 4-byte data. */
8062 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 6,
8063 (valueT
) x86_feature_2_used
, 4);
8065 /* Zero out paddings. */
8066 padding
= feature_2_descsz
- feature_2_descsz_raw
;
8068 memset (p
+ isa_1_descsz
+ 4 * 7, 0, padding
);
8070 /* We probably can't restore the current segment, for there likely
8073 subseg_set (seg
, subseg
);
8080 fragS
*insn_start_frag
;
8081 offsetT insn_start_off
;
8083 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8084 if (IS_ELF
&& x86_used_note
)
8086 if (i
.tm
.cpu_flags
.bitfield
.cpucmov
)
8087 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_CMOV
;
8088 if (i
.tm
.cpu_flags
.bitfield
.cpusse
)
8089 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE
;
8090 if (i
.tm
.cpu_flags
.bitfield
.cpusse2
)
8091 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE2
;
8092 if (i
.tm
.cpu_flags
.bitfield
.cpusse3
)
8093 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE3
;
8094 if (i
.tm
.cpu_flags
.bitfield
.cpussse3
)
8095 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSSE3
;
8096 if (i
.tm
.cpu_flags
.bitfield
.cpusse4_1
)
8097 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE4_1
;
8098 if (i
.tm
.cpu_flags
.bitfield
.cpusse4_2
)
8099 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE4_2
;
8100 if (i
.tm
.cpu_flags
.bitfield
.cpuavx
)
8101 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX
;
8102 if (i
.tm
.cpu_flags
.bitfield
.cpuavx2
)
8103 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX2
;
8104 if (i
.tm
.cpu_flags
.bitfield
.cpufma
)
8105 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_FMA
;
8106 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512f
)
8107 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512F
;
8108 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512cd
)
8109 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512CD
;
8110 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512er
)
8111 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512ER
;
8112 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512pf
)
8113 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512PF
;
8114 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512vl
)
8115 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512VL
;
8116 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512dq
)
8117 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512DQ
;
8118 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512bw
)
8119 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512BW
;
8120 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_4fmaps
)
8121 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_4FMAPS
;
8122 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_4vnniw
)
8123 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_4VNNIW
;
8124 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_bitalg
)
8125 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_BITALG
;
8126 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512ifma
)
8127 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_IFMA
;
8128 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512vbmi
)
8129 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_VBMI
;
8130 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_vbmi2
)
8131 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_VBMI2
;
8132 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_vnni
)
8133 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_VNNI
;
8135 if (i
.tm
.cpu_flags
.bitfield
.cpu8087
8136 || i
.tm
.cpu_flags
.bitfield
.cpu287
8137 || i
.tm
.cpu_flags
.bitfield
.cpu387
8138 || i
.tm
.cpu_flags
.bitfield
.cpu687
8139 || i
.tm
.cpu_flags
.bitfield
.cpufisttp
)
8140 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_X87
;
8141 /* Don't set GNU_PROPERTY_X86_FEATURE_2_MMX for prefetchtXXX nor
8142 Xfence instructions. */
8143 if (i
.tm
.base_opcode
!= 0xf18
8144 && i
.tm
.base_opcode
!= 0xf0d
8145 && i
.tm
.base_opcode
!= 0xfae
8147 || i
.tm
.cpu_flags
.bitfield
.cpummx
8148 || i
.tm
.cpu_flags
.bitfield
.cpua3dnow
8149 || i
.tm
.cpu_flags
.bitfield
.cpua3dnowa
))
8150 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_MMX
;
8152 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XMM
;
8154 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_YMM
;
8156 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_ZMM
;
8157 if (i
.tm
.cpu_flags
.bitfield
.cpufxsr
)
8158 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_FXSR
;
8159 if (i
.tm
.cpu_flags
.bitfield
.cpuxsave
)
8160 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVE
;
8161 if (i
.tm
.cpu_flags
.bitfield
.cpuxsaveopt
)
8162 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVEOPT
;
8163 if (i
.tm
.cpu_flags
.bitfield
.cpuxsavec
)
8164 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVEC
;
8168 /* Tie dwarf2 debug info to the address at the start of the insn.
8169 We can't do this after the insn has been output as the current
8170 frag may have been closed off. eg. by frag_var. */
8171 dwarf2_emit_insn (0);
8173 insn_start_frag
= frag_now
;
8174 insn_start_off
= frag_now_fix ();
8177 if (i
.tm
.opcode_modifier
.jump
)
8179 else if (i
.tm
.opcode_modifier
.jumpbyte
8180 || i
.tm
.opcode_modifier
.jumpdword
)
8182 else if (i
.tm
.opcode_modifier
.jumpintersegment
)
8183 output_interseg_jump ();
8186 /* Output normal instructions here. */
8190 unsigned int prefix
;
8193 && i
.tm
.base_opcode
== 0xfae
8195 && i
.imm_operands
== 1
8196 && (i
.op
[0].imms
->X_add_number
== 0xe8
8197 || i
.op
[0].imms
->X_add_number
== 0xf0
8198 || i
.op
[0].imms
->X_add_number
== 0xf8))
8200 /* Encode lfence, mfence, and sfence as
8201 f0 83 04 24 00 lock addl $0x0, (%{re}sp). */
8202 offsetT val
= 0x240483f0ULL
;
8204 md_number_to_chars (p
, val
, 5);
8208 /* Some processors fail on LOCK prefix. This options makes
8209 assembler ignore LOCK prefix and serves as a workaround. */
8210 if (omit_lock_prefix
)
8212 if (i
.tm
.base_opcode
== LOCK_PREFIX_OPCODE
)
8214 i
.prefix
[LOCK_PREFIX
] = 0;
8217 /* Since the VEX/EVEX prefix contains the implicit prefix, we
8218 don't need the explicit prefix. */
8219 if (!i
.tm
.opcode_modifier
.vex
&& !i
.tm
.opcode_modifier
.evex
)
8221 switch (i
.tm
.opcode_length
)
8224 if (i
.tm
.base_opcode
& 0xff000000)
8226 prefix
= (i
.tm
.base_opcode
>> 24) & 0xff;
8227 add_prefix (prefix
);
8231 if ((i
.tm
.base_opcode
& 0xff0000) != 0)
8233 prefix
= (i
.tm
.base_opcode
>> 16) & 0xff;
8234 if (!i
.tm
.cpu_flags
.bitfield
.cpupadlock
8235 || prefix
!= REPE_PREFIX_OPCODE
8236 || (i
.prefix
[REP_PREFIX
] != REPE_PREFIX_OPCODE
))
8237 add_prefix (prefix
);
8243 /* Check for pseudo prefixes. */
8244 as_bad_where (insn_start_frag
->fr_file
,
8245 insn_start_frag
->fr_line
,
8246 _("pseudo prefix without instruction"));
8252 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
8253 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
8254 R_X86_64_GOTTPOFF relocation so that linker can safely
8255 perform IE->LE optimization. */
8256 if (x86_elf_abi
== X86_64_X32_ABI
8258 && i
.reloc
[0] == BFD_RELOC_X86_64_GOTTPOFF
8259 && i
.prefix
[REX_PREFIX
] == 0)
8260 add_prefix (REX_OPCODE
);
8263 /* The prefix bytes. */
8264 for (j
= ARRAY_SIZE (i
.prefix
), q
= i
.prefix
; j
> 0; j
--, q
++)
8266 FRAG_APPEND_1_CHAR (*q
);
8270 for (j
= 0, q
= i
.prefix
; j
< ARRAY_SIZE (i
.prefix
); j
++, q
++)
8275 /* REX byte is encoded in VEX prefix. */
8279 FRAG_APPEND_1_CHAR (*q
);
8282 /* There should be no other prefixes for instructions
8287 /* For EVEX instructions i.vrex should become 0 after
8288 build_evex_prefix. For VEX instructions upper 16 registers
8289 aren't available, so VREX should be 0. */
8292 /* Now the VEX prefix. */
8293 p
= frag_more (i
.vex
.length
);
8294 for (j
= 0; j
< i
.vex
.length
; j
++)
8295 p
[j
] = i
.vex
.bytes
[j
];
8298 /* Now the opcode; be careful about word order here! */
8299 if (i
.tm
.opcode_length
== 1)
8301 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
8305 switch (i
.tm
.opcode_length
)
8309 *p
++ = (i
.tm
.base_opcode
>> 24) & 0xff;
8310 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
8314 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
8324 /* Put out high byte first: can't use md_number_to_chars! */
8325 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
8326 *p
= i
.tm
.base_opcode
& 0xff;
8329 /* Now the modrm byte and sib byte (if present). */
8330 if (i
.tm
.opcode_modifier
.modrm
)
8332 FRAG_APPEND_1_CHAR ((i
.rm
.regmem
<< 0
8335 /* If i.rm.regmem == ESP (4)
8336 && i.rm.mode != (Register mode)
8338 ==> need second modrm byte. */
8339 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
8341 && !(i
.base_reg
&& i
.base_reg
->reg_type
.bitfield
.word
))
8342 FRAG_APPEND_1_CHAR ((i
.sib
.base
<< 0
8344 | i
.sib
.scale
<< 6));
8347 if (i
.disp_operands
)
8348 output_disp (insn_start_frag
, insn_start_off
);
8351 output_imm (insn_start_frag
, insn_start_off
);
8357 pi ("" /*line*/, &i
);
8359 #endif /* DEBUG386 */
8362 /* Return the size of the displacement operand N. */
8365 disp_size (unsigned int n
)
8369 if (i
.types
[n
].bitfield
.disp64
)
8371 else if (i
.types
[n
].bitfield
.disp8
)
8373 else if (i
.types
[n
].bitfield
.disp16
)
8378 /* Return the size of the immediate operand N. */
8381 imm_size (unsigned int n
)
8384 if (i
.types
[n
].bitfield
.imm64
)
8386 else if (i
.types
[n
].bitfield
.imm8
|| i
.types
[n
].bitfield
.imm8s
)
8388 else if (i
.types
[n
].bitfield
.imm16
)
8394 output_disp (fragS
*insn_start_frag
, offsetT insn_start_off
)
8399 for (n
= 0; n
< i
.operands
; n
++)
8401 if (operand_type_check (i
.types
[n
], disp
))
8403 if (i
.op
[n
].disps
->X_op
== O_constant
)
8405 int size
= disp_size (n
);
8406 offsetT val
= i
.op
[n
].disps
->X_add_number
;
8408 val
= offset_in_range (val
>> (size
== 1 ? i
.memshift
: 0),
8410 p
= frag_more (size
);
8411 md_number_to_chars (p
, val
, size
);
8415 enum bfd_reloc_code_real reloc_type
;
8416 int size
= disp_size (n
);
8417 int sign
= i
.types
[n
].bitfield
.disp32s
;
8418 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
8421 /* We can't have 8 bit displacement here. */
8422 gas_assert (!i
.types
[n
].bitfield
.disp8
);
8424 /* The PC relative address is computed relative
8425 to the instruction boundary, so in case immediate
8426 fields follows, we need to adjust the value. */
8427 if (pcrel
&& i
.imm_operands
)
8432 for (n1
= 0; n1
< i
.operands
; n1
++)
8433 if (operand_type_check (i
.types
[n1
], imm
))
8435 /* Only one immediate is allowed for PC
8436 relative address. */
8437 gas_assert (sz
== 0);
8439 i
.op
[n
].disps
->X_add_number
-= sz
;
8441 /* We should find the immediate. */
8442 gas_assert (sz
!= 0);
8445 p
= frag_more (size
);
8446 reloc_type
= reloc (size
, pcrel
, sign
, i
.reloc
[n
]);
8448 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
8449 && (((reloc_type
== BFD_RELOC_32
8450 || reloc_type
== BFD_RELOC_X86_64_32S
8451 || (reloc_type
== BFD_RELOC_64
8453 && (i
.op
[n
].disps
->X_op
== O_symbol
8454 || (i
.op
[n
].disps
->X_op
== O_add
8455 && ((symbol_get_value_expression
8456 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
8458 || reloc_type
== BFD_RELOC_32_PCREL
))
8462 if (insn_start_frag
== frag_now
)
8463 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
8468 add
= insn_start_frag
->fr_fix
- insn_start_off
;
8469 for (fr
= insn_start_frag
->fr_next
;
8470 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
8472 add
+= p
- frag_now
->fr_literal
;
8477 reloc_type
= BFD_RELOC_386_GOTPC
;
8478 i
.op
[n
].imms
->X_add_number
+= add
;
8480 else if (reloc_type
== BFD_RELOC_64
)
8481 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
8483 /* Don't do the adjustment for x86-64, as there
8484 the pcrel addressing is relative to the _next_
8485 insn, and that is taken care of in other code. */
8486 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
8488 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
8489 size
, i
.op
[n
].disps
, pcrel
,
8491 /* Check for "call/jmp *mem", "mov mem, %reg",
8492 "test %reg, mem" and "binop mem, %reg" where binop
8493 is one of adc, add, and, cmp, or, sbb, sub, xor
8494 instructions without data prefix. Always generate
8495 R_386_GOT32X for "sym*GOT" operand in 32-bit mode. */
8496 if (i
.prefix
[DATA_PREFIX
] == 0
8497 && (generate_relax_relocations
8500 && i
.rm
.regmem
== 5))
8502 || (i
.rm
.mode
== 0 && i
.rm
.regmem
== 5))
8503 && ((i
.operands
== 1
8504 && i
.tm
.base_opcode
== 0xff
8505 && (i
.rm
.reg
== 2 || i
.rm
.reg
== 4))
8507 && (i
.tm
.base_opcode
== 0x8b
8508 || i
.tm
.base_opcode
== 0x85
8509 || (i
.tm
.base_opcode
& 0xc7) == 0x03))))
8513 fixP
->fx_tcbit
= i
.rex
!= 0;
8515 && (i
.base_reg
->reg_num
== RegIP
))
8516 fixP
->fx_tcbit2
= 1;
8519 fixP
->fx_tcbit2
= 1;
8527 output_imm (fragS
*insn_start_frag
, offsetT insn_start_off
)
8532 for (n
= 0; n
< i
.operands
; n
++)
8534 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
8535 if (i
.rounding
&& (int) n
== i
.rounding
->operand
)
8538 if (operand_type_check (i
.types
[n
], imm
))
8540 if (i
.op
[n
].imms
->X_op
== O_constant
)
8542 int size
= imm_size (n
);
8545 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
8547 p
= frag_more (size
);
8548 md_number_to_chars (p
, val
, size
);
8552 /* Not absolute_section.
8553 Need a 32-bit fixup (don't support 8bit
8554 non-absolute imms). Try to support other
8556 enum bfd_reloc_code_real reloc_type
;
8557 int size
= imm_size (n
);
8560 if (i
.types
[n
].bitfield
.imm32s
8561 && (i
.suffix
== QWORD_MNEM_SUFFIX
8562 || (!i
.suffix
&& i
.tm
.opcode_modifier
.no_lsuf
)))
8567 p
= frag_more (size
);
8568 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
8570 /* This is tough to explain. We end up with this one if we
8571 * have operands that look like
8572 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
8573 * obtain the absolute address of the GOT, and it is strongly
8574 * preferable from a performance point of view to avoid using
8575 * a runtime relocation for this. The actual sequence of
8576 * instructions often look something like:
8581 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
8583 * The call and pop essentially return the absolute address
8584 * of the label .L66 and store it in %ebx. The linker itself
8585 * will ultimately change the first operand of the addl so
8586 * that %ebx points to the GOT, but to keep things simple, the
8587 * .o file must have this operand set so that it generates not
8588 * the absolute address of .L66, but the absolute address of
8589 * itself. This allows the linker itself simply treat a GOTPC
8590 * relocation as asking for a pcrel offset to the GOT to be
8591 * added in, and the addend of the relocation is stored in the
8592 * operand field for the instruction itself.
8594 * Our job here is to fix the operand so that it would add
8595 * the correct offset so that %ebx would point to itself. The
8596 * thing that is tricky is that .-.L66 will point to the
8597 * beginning of the instruction, so we need to further modify
8598 * the operand so that it will point to itself. There are
8599 * other cases where you have something like:
8601 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
8603 * and here no correction would be required. Internally in
8604 * the assembler we treat operands of this form as not being
8605 * pcrel since the '.' is explicitly mentioned, and I wonder
8606 * whether it would simplify matters to do it this way. Who
8607 * knows. In earlier versions of the PIC patches, the
8608 * pcrel_adjust field was used to store the correction, but
8609 * since the expression is not pcrel, I felt it would be
8610 * confusing to do it this way. */
8612 if ((reloc_type
== BFD_RELOC_32
8613 || reloc_type
== BFD_RELOC_X86_64_32S
8614 || reloc_type
== BFD_RELOC_64
)
8616 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
8617 && (i
.op
[n
].imms
->X_op
== O_symbol
8618 || (i
.op
[n
].imms
->X_op
== O_add
8619 && ((symbol_get_value_expression
8620 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
8625 if (insn_start_frag
== frag_now
)
8626 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
8631 add
= insn_start_frag
->fr_fix
- insn_start_off
;
8632 for (fr
= insn_start_frag
->fr_next
;
8633 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
8635 add
+= p
- frag_now
->fr_literal
;
8639 reloc_type
= BFD_RELOC_386_GOTPC
;
8641 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
8643 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
8644 i
.op
[n
].imms
->X_add_number
+= add
;
8646 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
8647 i
.op
[n
].imms
, 0, reloc_type
);
8653 /* x86_cons_fix_new is called via the expression parsing code when a
8654 reloc is needed. We use this hook to get the correct .got reloc. */
8655 static int cons_sign
= -1;
8658 x86_cons_fix_new (fragS
*frag
, unsigned int off
, unsigned int len
,
8659 expressionS
*exp
, bfd_reloc_code_real_type r
)
8661 r
= reloc (len
, 0, cons_sign
, r
);
8664 if (exp
->X_op
== O_secrel
)
8666 exp
->X_op
= O_symbol
;
8667 r
= BFD_RELOC_32_SECREL
;
8671 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
8674 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
8675 purpose of the `.dc.a' internal pseudo-op. */
8678 x86_address_bytes (void)
8680 if ((stdoutput
->arch_info
->mach
& bfd_mach_x64_32
))
8682 return stdoutput
->arch_info
->bits_per_address
/ 8;
8685 #if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
8687 # define lex_got(reloc, adjust, types) NULL
8689 /* Parse operands of the form
8690 <symbol>@GOTOFF+<nnn>
8691 and similar .plt or .got references.
8693 If we find one, set up the correct relocation in RELOC and copy the
8694 input string, minus the `@GOTOFF' into a malloc'd buffer for
8695 parsing by the calling routine. Return this buffer, and if ADJUST
8696 is non-null set it to the length of the string we removed from the
8697 input line. Otherwise return NULL. */
8699 lex_got (enum bfd_reloc_code_real
*rel
,
8701 i386_operand_type
*types
)
8703 /* Some of the relocations depend on the size of what field is to
8704 be relocated. But in our callers i386_immediate and i386_displacement
8705 we don't yet know the operand size (this will be set by insn
8706 matching). Hence we record the word32 relocation here,
8707 and adjust the reloc according to the real size in reloc(). */
8708 static const struct {
8711 const enum bfd_reloc_code_real rel
[2];
8712 const i386_operand_type types64
;
8714 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8715 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32
,
8717 OPERAND_TYPE_IMM32_64
},
8719 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real
,
8720 BFD_RELOC_X86_64_PLTOFF64
},
8721 OPERAND_TYPE_IMM64
},
8722 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32
,
8723 BFD_RELOC_X86_64_PLT32
},
8724 OPERAND_TYPE_IMM32_32S_DISP32
},
8725 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real
,
8726 BFD_RELOC_X86_64_GOTPLT64
},
8727 OPERAND_TYPE_IMM64_DISP64
},
8728 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF
,
8729 BFD_RELOC_X86_64_GOTOFF64
},
8730 OPERAND_TYPE_IMM64_DISP64
},
8731 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real
,
8732 BFD_RELOC_X86_64_GOTPCREL
},
8733 OPERAND_TYPE_IMM32_32S_DISP32
},
8734 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD
,
8735 BFD_RELOC_X86_64_TLSGD
},
8736 OPERAND_TYPE_IMM32_32S_DISP32
},
8737 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM
,
8738 _dummy_first_bfd_reloc_code_real
},
8739 OPERAND_TYPE_NONE
},
8740 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real
,
8741 BFD_RELOC_X86_64_TLSLD
},
8742 OPERAND_TYPE_IMM32_32S_DISP32
},
8743 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32
,
8744 BFD_RELOC_X86_64_GOTTPOFF
},
8745 OPERAND_TYPE_IMM32_32S_DISP32
},
8746 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32
,
8747 BFD_RELOC_X86_64_TPOFF32
},
8748 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
8749 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE
,
8750 _dummy_first_bfd_reloc_code_real
},
8751 OPERAND_TYPE_NONE
},
8752 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32
,
8753 BFD_RELOC_X86_64_DTPOFF32
},
8754 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
8755 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE
,
8756 _dummy_first_bfd_reloc_code_real
},
8757 OPERAND_TYPE_NONE
},
8758 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE
,
8759 _dummy_first_bfd_reloc_code_real
},
8760 OPERAND_TYPE_NONE
},
8761 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32
,
8762 BFD_RELOC_X86_64_GOT32
},
8763 OPERAND_TYPE_IMM32_32S_64_DISP32
},
8764 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC
,
8765 BFD_RELOC_X86_64_GOTPC32_TLSDESC
},
8766 OPERAND_TYPE_IMM32_32S_DISP32
},
8767 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL
,
8768 BFD_RELOC_X86_64_TLSDESC_CALL
},
8769 OPERAND_TYPE_IMM32_32S_DISP32
},
8774 #if defined (OBJ_MAYBE_ELF)
8779 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
8780 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
8783 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
8785 int len
= gotrel
[j
].len
;
8786 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
8788 if (gotrel
[j
].rel
[object_64bit
] != 0)
8791 char *tmpbuf
, *past_reloc
;
8793 *rel
= gotrel
[j
].rel
[object_64bit
];
8797 if (flag_code
!= CODE_64BIT
)
8799 types
->bitfield
.imm32
= 1;
8800 types
->bitfield
.disp32
= 1;
8803 *types
= gotrel
[j
].types64
;
8806 if (j
!= 0 && GOT_symbol
== NULL
)
8807 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
8809 /* The length of the first part of our input line. */
8810 first
= cp
- input_line_pointer
;
8812 /* The second part goes from after the reloc token until
8813 (and including) an end_of_line char or comma. */
8814 past_reloc
= cp
+ 1 + len
;
8816 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
8818 second
= cp
+ 1 - past_reloc
;
8820 /* Allocate and copy string. The trailing NUL shouldn't
8821 be necessary, but be safe. */
8822 tmpbuf
= XNEWVEC (char, first
+ second
+ 2);
8823 memcpy (tmpbuf
, input_line_pointer
, first
);
8824 if (second
!= 0 && *past_reloc
!= ' ')
8825 /* Replace the relocation token with ' ', so that
8826 errors like foo@GOTOFF1 will be detected. */
8827 tmpbuf
[first
++] = ' ';
8829 /* Increment length by 1 if the relocation token is
8834 memcpy (tmpbuf
+ first
, past_reloc
, second
);
8835 tmpbuf
[first
+ second
] = '\0';
8839 as_bad (_("@%s reloc is not supported with %d-bit output format"),
8840 gotrel
[j
].str
, 1 << (5 + object_64bit
));
8845 /* Might be a symbol version string. Don't as_bad here. */
8854 /* Parse operands of the form
8855 <symbol>@SECREL32+<nnn>
8857 If we find one, set up the correct relocation in RELOC and copy the
8858 input string, minus the `@SECREL32' into a malloc'd buffer for
8859 parsing by the calling routine. Return this buffer, and if ADJUST
8860 is non-null set it to the length of the string we removed from the
8861 input line. Otherwise return NULL.
8863 This function is copied from the ELF version above adjusted for PE targets. */
8866 lex_got (enum bfd_reloc_code_real
*rel ATTRIBUTE_UNUSED
,
8867 int *adjust ATTRIBUTE_UNUSED
,
8868 i386_operand_type
*types
)
8874 const enum bfd_reloc_code_real rel
[2];
8875 const i386_operand_type types64
;
8879 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL
,
8880 BFD_RELOC_32_SECREL
},
8881 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
8887 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
8888 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
8891 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
8893 int len
= gotrel
[j
].len
;
8895 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
8897 if (gotrel
[j
].rel
[object_64bit
] != 0)
8900 char *tmpbuf
, *past_reloc
;
8902 *rel
= gotrel
[j
].rel
[object_64bit
];
8908 if (flag_code
!= CODE_64BIT
)
8910 types
->bitfield
.imm32
= 1;
8911 types
->bitfield
.disp32
= 1;
8914 *types
= gotrel
[j
].types64
;
8917 /* The length of the first part of our input line. */
8918 first
= cp
- input_line_pointer
;
8920 /* The second part goes from after the reloc token until
8921 (and including) an end_of_line char or comma. */
8922 past_reloc
= cp
+ 1 + len
;
8924 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
8926 second
= cp
+ 1 - past_reloc
;
8928 /* Allocate and copy string. The trailing NUL shouldn't
8929 be necessary, but be safe. */
8930 tmpbuf
= XNEWVEC (char, first
+ second
+ 2);
8931 memcpy (tmpbuf
, input_line_pointer
, first
);
8932 if (second
!= 0 && *past_reloc
!= ' ')
8933 /* Replace the relocation token with ' ', so that
8934 errors like foo@SECLREL321 will be detected. */
8935 tmpbuf
[first
++] = ' ';
8936 memcpy (tmpbuf
+ first
, past_reloc
, second
);
8937 tmpbuf
[first
+ second
] = '\0';
8941 as_bad (_("@%s reloc is not supported with %d-bit output format"),
8942 gotrel
[j
].str
, 1 << (5 + object_64bit
));
8947 /* Might be a symbol version string. Don't as_bad here. */
8953 bfd_reloc_code_real_type
8954 x86_cons (expressionS
*exp
, int size
)
8956 bfd_reloc_code_real_type got_reloc
= NO_RELOC
;
8958 intel_syntax
= -intel_syntax
;
8961 if (size
== 4 || (object_64bit
&& size
== 8))
8963 /* Handle @GOTOFF and the like in an expression. */
8965 char *gotfree_input_line
;
8968 save
= input_line_pointer
;
8969 gotfree_input_line
= lex_got (&got_reloc
, &adjust
, NULL
);
8970 if (gotfree_input_line
)
8971 input_line_pointer
= gotfree_input_line
;
8975 if (gotfree_input_line
)
8977 /* expression () has merrily parsed up to the end of line,
8978 or a comma - in the wrong buffer. Transfer how far
8979 input_line_pointer has moved to the right buffer. */
8980 input_line_pointer
= (save
8981 + (input_line_pointer
- gotfree_input_line
)
8983 free (gotfree_input_line
);
8984 if (exp
->X_op
== O_constant
8985 || exp
->X_op
== O_absent
8986 || exp
->X_op
== O_illegal
8987 || exp
->X_op
== O_register
8988 || exp
->X_op
== O_big
)
8990 char c
= *input_line_pointer
;
8991 *input_line_pointer
= 0;
8992 as_bad (_("missing or invalid expression `%s'"), save
);
8993 *input_line_pointer
= c
;
8995 else if ((got_reloc
== BFD_RELOC_386_PLT32
8996 || got_reloc
== BFD_RELOC_X86_64_PLT32
)
8997 && exp
->X_op
!= O_symbol
)
8999 char c
= *input_line_pointer
;
9000 *input_line_pointer
= 0;
9001 as_bad (_("invalid PLT expression `%s'"), save
);
9002 *input_line_pointer
= c
;
9009 intel_syntax
= -intel_syntax
;
9012 i386_intel_simplify (exp
);
9018 signed_cons (int size
)
9020 if (flag_code
== CODE_64BIT
)
9028 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
9035 if (exp
.X_op
== O_symbol
)
9036 exp
.X_op
= O_secrel
;
9038 emit_expr (&exp
, 4);
9040 while (*input_line_pointer
++ == ',');
9042 input_line_pointer
--;
9043 demand_empty_rest_of_line ();
9047 /* Handle Vector operations. */
9050 check_VecOperations (char *op_string
, char *op_end
)
9052 const reg_entry
*mask
;
9057 && (op_end
== NULL
|| op_string
< op_end
))
9060 if (*op_string
== '{')
9064 /* Check broadcasts. */
9065 if (strncmp (op_string
, "1to", 3) == 0)
9070 goto duplicated_vec_op
;
9073 if (*op_string
== '8')
9075 else if (*op_string
== '4')
9077 else if (*op_string
== '2')
9079 else if (*op_string
== '1'
9080 && *(op_string
+1) == '6')
9087 as_bad (_("Unsupported broadcast: `%s'"), saved
);
9092 broadcast_op
.type
= bcst_type
;
9093 broadcast_op
.operand
= this_operand
;
9094 broadcast_op
.bytes
= 0;
9095 i
.broadcast
= &broadcast_op
;
9097 /* Check masking operation. */
9098 else if ((mask
= parse_register (op_string
, &end_op
)) != NULL
)
9100 /* k0 can't be used for write mask. */
9101 if (!mask
->reg_type
.bitfield
.regmask
|| mask
->reg_num
== 0)
9103 as_bad (_("`%s%s' can't be used for write mask"),
9104 register_prefix
, mask
->reg_name
);
9110 mask_op
.mask
= mask
;
9111 mask_op
.zeroing
= 0;
9112 mask_op
.operand
= this_operand
;
9118 goto duplicated_vec_op
;
9120 i
.mask
->mask
= mask
;
9122 /* Only "{z}" is allowed here. No need to check
9123 zeroing mask explicitly. */
9124 if (i
.mask
->operand
!= this_operand
)
9126 as_bad (_("invalid write mask `%s'"), saved
);
9133 /* Check zeroing-flag for masking operation. */
9134 else if (*op_string
== 'z')
9138 mask_op
.mask
= NULL
;
9139 mask_op
.zeroing
= 1;
9140 mask_op
.operand
= this_operand
;
9145 if (i
.mask
->zeroing
)
9148 as_bad (_("duplicated `%s'"), saved
);
9152 i
.mask
->zeroing
= 1;
9154 /* Only "{%k}" is allowed here. No need to check mask
9155 register explicitly. */
9156 if (i
.mask
->operand
!= this_operand
)
9158 as_bad (_("invalid zeroing-masking `%s'"),
9167 goto unknown_vec_op
;
9169 if (*op_string
!= '}')
9171 as_bad (_("missing `}' in `%s'"), saved
);
9176 /* Strip whitespace since the addition of pseudo prefixes
9177 changed how the scrubber treats '{'. */
9178 if (is_space_char (*op_string
))
9184 /* We don't know this one. */
9185 as_bad (_("unknown vector operation: `%s'"), saved
);
9189 if (i
.mask
&& i
.mask
->zeroing
&& !i
.mask
->mask
)
9191 as_bad (_("zeroing-masking only allowed with write mask"));
9199 i386_immediate (char *imm_start
)
9201 char *save_input_line_pointer
;
9202 char *gotfree_input_line
;
9205 i386_operand_type types
;
9207 operand_type_set (&types
, ~0);
9209 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
9211 as_bad (_("at most %d immediate operands are allowed"),
9212 MAX_IMMEDIATE_OPERANDS
);
9216 exp
= &im_expressions
[i
.imm_operands
++];
9217 i
.op
[this_operand
].imms
= exp
;
9219 if (is_space_char (*imm_start
))
9222 save_input_line_pointer
= input_line_pointer
;
9223 input_line_pointer
= imm_start
;
9225 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
9226 if (gotfree_input_line
)
9227 input_line_pointer
= gotfree_input_line
;
9229 exp_seg
= expression (exp
);
9233 /* Handle vector operations. */
9234 if (*input_line_pointer
== '{')
9236 input_line_pointer
= check_VecOperations (input_line_pointer
,
9238 if (input_line_pointer
== NULL
)
9242 if (*input_line_pointer
)
9243 as_bad (_("junk `%s' after expression"), input_line_pointer
);
9245 input_line_pointer
= save_input_line_pointer
;
9246 if (gotfree_input_line
)
9248 free (gotfree_input_line
);
9250 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
9251 exp
->X_op
= O_illegal
;
9254 return i386_finalize_immediate (exp_seg
, exp
, types
, imm_start
);
9258 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
9259 i386_operand_type types
, const char *imm_start
)
9261 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_illegal
|| exp
->X_op
== O_big
)
9264 as_bad (_("missing or invalid immediate expression `%s'"),
9268 else if (exp
->X_op
== O_constant
)
9270 /* Size it properly later. */
9271 i
.types
[this_operand
].bitfield
.imm64
= 1;
9272 /* If not 64bit, sign extend val. */
9273 if (flag_code
!= CODE_64BIT
9274 && (exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
9276 = (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
9278 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
9279 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
9280 && exp_seg
!= absolute_section
9281 && exp_seg
!= text_section
9282 && exp_seg
!= data_section
9283 && exp_seg
!= bss_section
9284 && exp_seg
!= undefined_section
9285 && !bfd_is_com_section (exp_seg
))
9287 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
9291 else if (!intel_syntax
&& exp_seg
== reg_section
)
9294 as_bad (_("illegal immediate register operand %s"), imm_start
);
9299 /* This is an address. The size of the address will be
9300 determined later, depending on destination register,
9301 suffix, or the default for the section. */
9302 i
.types
[this_operand
].bitfield
.imm8
= 1;
9303 i
.types
[this_operand
].bitfield
.imm16
= 1;
9304 i
.types
[this_operand
].bitfield
.imm32
= 1;
9305 i
.types
[this_operand
].bitfield
.imm32s
= 1;
9306 i
.types
[this_operand
].bitfield
.imm64
= 1;
9307 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
9315 i386_scale (char *scale
)
9318 char *save
= input_line_pointer
;
9320 input_line_pointer
= scale
;
9321 val
= get_absolute_expression ();
9326 i
.log2_scale_factor
= 0;
9329 i
.log2_scale_factor
= 1;
9332 i
.log2_scale_factor
= 2;
9335 i
.log2_scale_factor
= 3;
9339 char sep
= *input_line_pointer
;
9341 *input_line_pointer
= '\0';
9342 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
9344 *input_line_pointer
= sep
;
9345 input_line_pointer
= save
;
9349 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
9351 as_warn (_("scale factor of %d without an index register"),
9352 1 << i
.log2_scale_factor
);
9353 i
.log2_scale_factor
= 0;
9355 scale
= input_line_pointer
;
9356 input_line_pointer
= save
;
9361 i386_displacement (char *disp_start
, char *disp_end
)
9365 char *save_input_line_pointer
;
9366 char *gotfree_input_line
;
9368 i386_operand_type bigdisp
, types
= anydisp
;
9371 if (i
.disp_operands
== MAX_MEMORY_OPERANDS
)
9373 as_bad (_("at most %d displacement operands are allowed"),
9374 MAX_MEMORY_OPERANDS
);
9378 operand_type_set (&bigdisp
, 0);
9379 if ((i
.types
[this_operand
].bitfield
.jumpabsolute
)
9380 || (!current_templates
->start
->opcode_modifier
.jump
9381 && !current_templates
->start
->opcode_modifier
.jumpdword
))
9383 bigdisp
.bitfield
.disp32
= 1;
9384 override
= (i
.prefix
[ADDR_PREFIX
] != 0);
9385 if (flag_code
== CODE_64BIT
)
9389 bigdisp
.bitfield
.disp32s
= 1;
9390 bigdisp
.bitfield
.disp64
= 1;
9393 else if ((flag_code
== CODE_16BIT
) ^ override
)
9395 bigdisp
.bitfield
.disp32
= 0;
9396 bigdisp
.bitfield
.disp16
= 1;
9401 /* For PC-relative branches, the width of the displacement
9402 is dependent upon data size, not address size. */
9403 override
= (i
.prefix
[DATA_PREFIX
] != 0);
9404 if (flag_code
== CODE_64BIT
)
9406 if (override
|| i
.suffix
== WORD_MNEM_SUFFIX
)
9407 bigdisp
.bitfield
.disp16
= 1;
9410 bigdisp
.bitfield
.disp32
= 1;
9411 bigdisp
.bitfield
.disp32s
= 1;
9417 override
= (i
.suffix
== (flag_code
!= CODE_16BIT
9419 : LONG_MNEM_SUFFIX
));
9420 bigdisp
.bitfield
.disp32
= 1;
9421 if ((flag_code
== CODE_16BIT
) ^ override
)
9423 bigdisp
.bitfield
.disp32
= 0;
9424 bigdisp
.bitfield
.disp16
= 1;
9428 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
9431 exp
= &disp_expressions
[i
.disp_operands
];
9432 i
.op
[this_operand
].disps
= exp
;
9434 save_input_line_pointer
= input_line_pointer
;
9435 input_line_pointer
= disp_start
;
9436 END_STRING_AND_SAVE (disp_end
);
9438 #ifndef GCC_ASM_O_HACK
9439 #define GCC_ASM_O_HACK 0
9442 END_STRING_AND_SAVE (disp_end
+ 1);
9443 if (i
.types
[this_operand
].bitfield
.baseIndex
9444 && displacement_string_end
[-1] == '+')
9446 /* This hack is to avoid a warning when using the "o"
9447 constraint within gcc asm statements.
9450 #define _set_tssldt_desc(n,addr,limit,type) \
9451 __asm__ __volatile__ ( \
9453 "movw %w1,2+%0\n\t" \
9455 "movb %b1,4+%0\n\t" \
9456 "movb %4,5+%0\n\t" \
9457 "movb $0,6+%0\n\t" \
9458 "movb %h1,7+%0\n\t" \
9460 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
9462 This works great except that the output assembler ends
9463 up looking a bit weird if it turns out that there is
9464 no offset. You end up producing code that looks like:
9477 So here we provide the missing zero. */
9479 *displacement_string_end
= '0';
9482 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
9483 if (gotfree_input_line
)
9484 input_line_pointer
= gotfree_input_line
;
9486 exp_seg
= expression (exp
);
9489 if (*input_line_pointer
)
9490 as_bad (_("junk `%s' after expression"), input_line_pointer
);
9492 RESTORE_END_STRING (disp_end
+ 1);
9494 input_line_pointer
= save_input_line_pointer
;
9495 if (gotfree_input_line
)
9497 free (gotfree_input_line
);
9499 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
9500 exp
->X_op
= O_illegal
;
9503 ret
= i386_finalize_displacement (exp_seg
, exp
, types
, disp_start
);
9505 RESTORE_END_STRING (disp_end
);
9511 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
9512 i386_operand_type types
, const char *disp_start
)
9514 i386_operand_type bigdisp
;
9517 /* We do this to make sure that the section symbol is in
9518 the symbol table. We will ultimately change the relocation
9519 to be relative to the beginning of the section. */
9520 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
9521 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
9522 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
9524 if (exp
->X_op
!= O_symbol
)
9527 if (S_IS_LOCAL (exp
->X_add_symbol
)
9528 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
9529 && S_GET_SEGMENT (exp
->X_add_symbol
) != expr_section
)
9530 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
9531 exp
->X_op
= O_subtract
;
9532 exp
->X_op_symbol
= GOT_symbol
;
9533 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
9534 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
9535 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
9536 i
.reloc
[this_operand
] = BFD_RELOC_64
;
9538 i
.reloc
[this_operand
] = BFD_RELOC_32
;
9541 else if (exp
->X_op
== O_absent
9542 || exp
->X_op
== O_illegal
9543 || exp
->X_op
== O_big
)
9546 as_bad (_("missing or invalid displacement expression `%s'"),
9551 else if (flag_code
== CODE_64BIT
9552 && !i
.prefix
[ADDR_PREFIX
]
9553 && exp
->X_op
== O_constant
)
9555 /* Since displacement is signed extended to 64bit, don't allow
9556 disp32 and turn off disp32s if they are out of range. */
9557 i
.types
[this_operand
].bitfield
.disp32
= 0;
9558 if (!fits_in_signed_long (exp
->X_add_number
))
9560 i
.types
[this_operand
].bitfield
.disp32s
= 0;
9561 if (i
.types
[this_operand
].bitfield
.baseindex
)
9563 as_bad (_("0x%lx out range of signed 32bit displacement"),
9564 (long) exp
->X_add_number
);
9570 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
9571 else if (exp
->X_op
!= O_constant
9572 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
9573 && exp_seg
!= absolute_section
9574 && exp_seg
!= text_section
9575 && exp_seg
!= data_section
9576 && exp_seg
!= bss_section
9577 && exp_seg
!= undefined_section
9578 && !bfd_is_com_section (exp_seg
))
9580 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
9585 /* Check if this is a displacement only operand. */
9586 bigdisp
= i
.types
[this_operand
];
9587 bigdisp
.bitfield
.disp8
= 0;
9588 bigdisp
.bitfield
.disp16
= 0;
9589 bigdisp
.bitfield
.disp32
= 0;
9590 bigdisp
.bitfield
.disp32s
= 0;
9591 bigdisp
.bitfield
.disp64
= 0;
9592 if (operand_type_all_zero (&bigdisp
))
9593 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
9599 /* Return the active addressing mode, taking address override and
9600 registers forming the address into consideration. Update the
9601 address override prefix if necessary. */
9603 static enum flag_code
9604 i386_addressing_mode (void)
9606 enum flag_code addr_mode
;
9608 if (i
.prefix
[ADDR_PREFIX
])
9609 addr_mode
= flag_code
== CODE_32BIT
? CODE_16BIT
: CODE_32BIT
;
9612 addr_mode
= flag_code
;
9614 #if INFER_ADDR_PREFIX
9615 if (i
.mem_operands
== 0)
9617 /* Infer address prefix from the first memory operand. */
9618 const reg_entry
*addr_reg
= i
.base_reg
;
9620 if (addr_reg
== NULL
)
9621 addr_reg
= i
.index_reg
;
9625 if (addr_reg
->reg_type
.bitfield
.dword
)
9626 addr_mode
= CODE_32BIT
;
9627 else if (flag_code
!= CODE_64BIT
9628 && addr_reg
->reg_type
.bitfield
.word
)
9629 addr_mode
= CODE_16BIT
;
9631 if (addr_mode
!= flag_code
)
9633 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
9635 /* Change the size of any displacement too. At most one
9636 of Disp16 or Disp32 is set.
9637 FIXME. There doesn't seem to be any real need for
9638 separate Disp16 and Disp32 flags. The same goes for
9639 Imm16 and Imm32. Removing them would probably clean
9640 up the code quite a lot. */
9641 if (flag_code
!= CODE_64BIT
9642 && (i
.types
[this_operand
].bitfield
.disp16
9643 || i
.types
[this_operand
].bitfield
.disp32
))
9644 i
.types
[this_operand
]
9645 = operand_type_xor (i
.types
[this_operand
], disp16_32
);
9655 /* Make sure the memory operand we've been dealt is valid.
9656 Return 1 on success, 0 on a failure. */
9659 i386_index_check (const char *operand_string
)
9661 const char *kind
= "base/index";
9662 enum flag_code addr_mode
= i386_addressing_mode ();
9664 if (current_templates
->start
->opcode_modifier
.isstring
9665 && !current_templates
->start
->opcode_modifier
.immext
9666 && (current_templates
->end
[-1].opcode_modifier
.isstring
9669 /* Memory operands of string insns are special in that they only allow
9670 a single register (rDI, rSI, or rBX) as their memory address. */
9671 const reg_entry
*expected_reg
;
9672 static const char *di_si
[][2] =
9678 static const char *bx
[] = { "ebx", "bx", "rbx" };
9680 kind
= "string address";
9682 if (current_templates
->start
->opcode_modifier
.repprefixok
)
9684 i386_operand_type type
= current_templates
->end
[-1].operand_types
[0];
9686 if (!type
.bitfield
.baseindex
9687 || ((!i
.mem_operands
!= !intel_syntax
)
9688 && current_templates
->end
[-1].operand_types
[1]
9689 .bitfield
.baseindex
))
9690 type
= current_templates
->end
[-1].operand_types
[1];
9691 expected_reg
= hash_find (reg_hash
,
9692 di_si
[addr_mode
][type
.bitfield
.esseg
]);
9696 expected_reg
= hash_find (reg_hash
, bx
[addr_mode
]);
9698 if (i
.base_reg
!= expected_reg
9700 || operand_type_check (i
.types
[this_operand
], disp
))
9702 /* The second memory operand must have the same size as
9706 && !((addr_mode
== CODE_64BIT
9707 && i
.base_reg
->reg_type
.bitfield
.qword
)
9708 || (addr_mode
== CODE_32BIT
9709 ? i
.base_reg
->reg_type
.bitfield
.dword
9710 : i
.base_reg
->reg_type
.bitfield
.word
)))
9713 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
9715 intel_syntax
? '[' : '(',
9717 expected_reg
->reg_name
,
9718 intel_syntax
? ']' : ')');
9725 as_bad (_("`%s' is not a valid %s expression"),
9726 operand_string
, kind
);
9731 if (addr_mode
!= CODE_16BIT
)
9733 /* 32-bit/64-bit checks. */
9735 && ((addr_mode
== CODE_64BIT
9736 ? !i
.base_reg
->reg_type
.bitfield
.qword
9737 : !i
.base_reg
->reg_type
.bitfield
.dword
)
9738 || (i
.index_reg
&& i
.base_reg
->reg_num
== RegIP
)
9739 || i
.base_reg
->reg_num
== RegIZ
))
9741 && !i
.index_reg
->reg_type
.bitfield
.xmmword
9742 && !i
.index_reg
->reg_type
.bitfield
.ymmword
9743 && !i
.index_reg
->reg_type
.bitfield
.zmmword
9744 && ((addr_mode
== CODE_64BIT
9745 ? !i
.index_reg
->reg_type
.bitfield
.qword
9746 : !i
.index_reg
->reg_type
.bitfield
.dword
)
9747 || !i
.index_reg
->reg_type
.bitfield
.baseindex
)))
9750 /* bndmk, bndldx, and bndstx have special restrictions. */
9751 if (current_templates
->start
->base_opcode
== 0xf30f1b
9752 || (current_templates
->start
->base_opcode
& ~1) == 0x0f1a)
9754 /* They cannot use RIP-relative addressing. */
9755 if (i
.base_reg
&& i
.base_reg
->reg_num
== RegIP
)
9757 as_bad (_("`%s' cannot be used here"), operand_string
);
9761 /* bndldx and bndstx ignore their scale factor. */
9762 if (current_templates
->start
->base_opcode
!= 0xf30f1b
9763 && i
.log2_scale_factor
)
9764 as_warn (_("register scaling is being ignored here"));
9769 /* 16-bit checks. */
9771 && (!i
.base_reg
->reg_type
.bitfield
.word
9772 || !i
.base_reg
->reg_type
.bitfield
.baseindex
))
9774 && (!i
.index_reg
->reg_type
.bitfield
.word
9775 || !i
.index_reg
->reg_type
.bitfield
.baseindex
9777 && i
.base_reg
->reg_num
< 6
9778 && i
.index_reg
->reg_num
>= 6
9779 && i
.log2_scale_factor
== 0))))
9786 /* Handle vector immediates. */
9789 RC_SAE_immediate (const char *imm_start
)
9791 unsigned int match_found
, j
;
9792 const char *pstr
= imm_start
;
9800 for (j
= 0; j
< ARRAY_SIZE (RC_NamesTable
); j
++)
9802 if (!strncmp (pstr
, RC_NamesTable
[j
].name
, RC_NamesTable
[j
].len
))
9806 rc_op
.type
= RC_NamesTable
[j
].type
;
9807 rc_op
.operand
= this_operand
;
9808 i
.rounding
= &rc_op
;
9812 as_bad (_("duplicated `%s'"), imm_start
);
9815 pstr
+= RC_NamesTable
[j
].len
;
9825 as_bad (_("Missing '}': '%s'"), imm_start
);
9828 /* RC/SAE immediate string should contain nothing more. */;
9831 as_bad (_("Junk after '}': '%s'"), imm_start
);
9835 exp
= &im_expressions
[i
.imm_operands
++];
9836 i
.op
[this_operand
].imms
= exp
;
9838 exp
->X_op
= O_constant
;
9839 exp
->X_add_number
= 0;
9840 exp
->X_add_symbol
= (symbolS
*) 0;
9841 exp
->X_op_symbol
= (symbolS
*) 0;
9843 i
.types
[this_operand
].bitfield
.imm8
= 1;
9847 /* Only string instructions can have a second memory operand, so
9848 reduce current_templates to just those if it contains any. */
9850 maybe_adjust_templates (void)
9852 const insn_template
*t
;
9854 gas_assert (i
.mem_operands
== 1);
9856 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
9857 if (t
->opcode_modifier
.isstring
)
9860 if (t
< current_templates
->end
)
9862 static templates aux_templates
;
9863 bfd_boolean recheck
;
9865 aux_templates
.start
= t
;
9866 for (; t
< current_templates
->end
; ++t
)
9867 if (!t
->opcode_modifier
.isstring
)
9869 aux_templates
.end
= t
;
9871 /* Determine whether to re-check the first memory operand. */
9872 recheck
= (aux_templates
.start
!= current_templates
->start
9873 || t
!= current_templates
->end
);
9875 current_templates
= &aux_templates
;
9880 if (i
.memop1_string
!= NULL
9881 && i386_index_check (i
.memop1_string
) == 0)
9890 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
9894 i386_att_operand (char *operand_string
)
9898 char *op_string
= operand_string
;
9900 if (is_space_char (*op_string
))
9903 /* We check for an absolute prefix (differentiating,
9904 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
9905 if (*op_string
== ABSOLUTE_PREFIX
)
9908 if (is_space_char (*op_string
))
9910 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
9913 /* Check if operand is a register. */
9914 if ((r
= parse_register (op_string
, &end_op
)) != NULL
)
9916 i386_operand_type temp
;
9918 /* Check for a segment override by searching for ':' after a
9919 segment register. */
9921 if (is_space_char (*op_string
))
9923 if (*op_string
== ':'
9924 && (r
->reg_type
.bitfield
.sreg2
9925 || r
->reg_type
.bitfield
.sreg3
))
9930 i
.seg
[i
.mem_operands
] = &es
;
9933 i
.seg
[i
.mem_operands
] = &cs
;
9936 i
.seg
[i
.mem_operands
] = &ss
;
9939 i
.seg
[i
.mem_operands
] = &ds
;
9942 i
.seg
[i
.mem_operands
] = &fs
;
9945 i
.seg
[i
.mem_operands
] = &gs
;
9949 /* Skip the ':' and whitespace. */
9951 if (is_space_char (*op_string
))
9954 if (!is_digit_char (*op_string
)
9955 && !is_identifier_char (*op_string
)
9956 && *op_string
!= '('
9957 && *op_string
!= ABSOLUTE_PREFIX
)
9959 as_bad (_("bad memory operand `%s'"), op_string
);
9962 /* Handle case of %es:*foo. */
9963 if (*op_string
== ABSOLUTE_PREFIX
)
9966 if (is_space_char (*op_string
))
9968 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
9970 goto do_memory_reference
;
9973 /* Handle vector operations. */
9974 if (*op_string
== '{')
9976 op_string
= check_VecOperations (op_string
, NULL
);
9977 if (op_string
== NULL
)
9983 as_bad (_("junk `%s' after register"), op_string
);
9987 temp
.bitfield
.baseindex
= 0;
9988 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
9990 i
.types
[this_operand
].bitfield
.unspecified
= 0;
9991 i
.op
[this_operand
].regs
= r
;
9994 else if (*op_string
== REGISTER_PREFIX
)
9996 as_bad (_("bad register name `%s'"), op_string
);
9999 else if (*op_string
== IMMEDIATE_PREFIX
)
10002 if (i
.types
[this_operand
].bitfield
.jumpabsolute
)
10004 as_bad (_("immediate operand illegal with absolute jump"));
10007 if (!i386_immediate (op_string
))
10010 else if (RC_SAE_immediate (operand_string
))
10012 /* If it is a RC or SAE immediate, do nothing. */
10015 else if (is_digit_char (*op_string
)
10016 || is_identifier_char (*op_string
)
10017 || *op_string
== '"'
10018 || *op_string
== '(')
10020 /* This is a memory reference of some sort. */
10023 /* Start and end of displacement string expression (if found). */
10024 char *displacement_string_start
;
10025 char *displacement_string_end
;
10028 do_memory_reference
:
10029 if (i
.mem_operands
== 1 && !maybe_adjust_templates ())
10031 if ((i
.mem_operands
== 1
10032 && !current_templates
->start
->opcode_modifier
.isstring
)
10033 || i
.mem_operands
== 2)
10035 as_bad (_("too many memory references for `%s'"),
10036 current_templates
->start
->name
);
10040 /* Check for base index form. We detect the base index form by
10041 looking for an ')' at the end of the operand, searching
10042 for the '(' matching it, and finding a REGISTER_PREFIX or ','
10044 base_string
= op_string
+ strlen (op_string
);
10046 /* Handle vector operations. */
10047 vop_start
= strchr (op_string
, '{');
10048 if (vop_start
&& vop_start
< base_string
)
10050 if (check_VecOperations (vop_start
, base_string
) == NULL
)
10052 base_string
= vop_start
;
10056 if (is_space_char (*base_string
))
10059 /* If we only have a displacement, set-up for it to be parsed later. */
10060 displacement_string_start
= op_string
;
10061 displacement_string_end
= base_string
+ 1;
10063 if (*base_string
== ')')
10066 unsigned int parens_balanced
= 1;
10067 /* We've already checked that the number of left & right ()'s are
10068 equal, so this loop will not be infinite. */
10072 if (*base_string
== ')')
10074 if (*base_string
== '(')
10077 while (parens_balanced
);
10079 temp_string
= base_string
;
10081 /* Skip past '(' and whitespace. */
10083 if (is_space_char (*base_string
))
10086 if (*base_string
== ','
10087 || ((i
.base_reg
= parse_register (base_string
, &end_op
))
10090 displacement_string_end
= temp_string
;
10092 i
.types
[this_operand
].bitfield
.baseindex
= 1;
10096 base_string
= end_op
;
10097 if (is_space_char (*base_string
))
10101 /* There may be an index reg or scale factor here. */
10102 if (*base_string
== ',')
10105 if (is_space_char (*base_string
))
10108 if ((i
.index_reg
= parse_register (base_string
, &end_op
))
10111 base_string
= end_op
;
10112 if (is_space_char (*base_string
))
10114 if (*base_string
== ',')
10117 if (is_space_char (*base_string
))
10120 else if (*base_string
!= ')')
10122 as_bad (_("expecting `,' or `)' "
10123 "after index register in `%s'"),
10128 else if (*base_string
== REGISTER_PREFIX
)
10130 end_op
= strchr (base_string
, ',');
10133 as_bad (_("bad register name `%s'"), base_string
);
10137 /* Check for scale factor. */
10138 if (*base_string
!= ')')
10140 char *end_scale
= i386_scale (base_string
);
10145 base_string
= end_scale
;
10146 if (is_space_char (*base_string
))
10148 if (*base_string
!= ')')
10150 as_bad (_("expecting `)' "
10151 "after scale factor in `%s'"),
10156 else if (!i
.index_reg
)
10158 as_bad (_("expecting index register or scale factor "
10159 "after `,'; got '%c'"),
10164 else if (*base_string
!= ')')
10166 as_bad (_("expecting `,' or `)' "
10167 "after base register in `%s'"),
10172 else if (*base_string
== REGISTER_PREFIX
)
10174 end_op
= strchr (base_string
, ',');
10177 as_bad (_("bad register name `%s'"), base_string
);
10182 /* If there's an expression beginning the operand, parse it,
10183 assuming displacement_string_start and
10184 displacement_string_end are meaningful. */
10185 if (displacement_string_start
!= displacement_string_end
)
10187 if (!i386_displacement (displacement_string_start
,
10188 displacement_string_end
))
10192 /* Special case for (%dx) while doing input/output op. */
10194 && i
.base_reg
->reg_type
.bitfield
.inoutportreg
10195 && i
.index_reg
== 0
10196 && i
.log2_scale_factor
== 0
10197 && i
.seg
[i
.mem_operands
] == 0
10198 && !operand_type_check (i
.types
[this_operand
], disp
))
10200 i
.types
[this_operand
] = i
.base_reg
->reg_type
;
10204 if (i386_index_check (operand_string
) == 0)
10206 i
.flags
[this_operand
] |= Operand_Mem
;
10207 if (i
.mem_operands
== 0)
10208 i
.memop1_string
= xstrdup (operand_string
);
10213 /* It's not a memory operand; argh! */
10214 as_bad (_("invalid char %s beginning operand %d `%s'"),
10215 output_invalid (*op_string
),
10220 return 1; /* Normal return. */
10223 /* Calculate the maximum variable size (i.e., excluding fr_fix)
10224 that an rs_machine_dependent frag may reach. */
10227 i386_frag_max_var (fragS
*frag
)
10229 /* The only relaxable frags are for jumps.
10230 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
10231 gas_assert (frag
->fr_type
== rs_machine_dependent
);
10232 return TYPE_FROM_RELAX_STATE (frag
->fr_subtype
) == UNCOND_JUMP
? 4 : 5;
10235 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10237 elf_symbol_resolved_in_segment_p (symbolS
*fr_symbol
, offsetT fr_var
)
10239 /* STT_GNU_IFUNC symbol must go through PLT. */
10240 if ((symbol_get_bfdsym (fr_symbol
)->flags
10241 & BSF_GNU_INDIRECT_FUNCTION
) != 0)
10244 if (!S_IS_EXTERNAL (fr_symbol
))
10245 /* Symbol may be weak or local. */
10246 return !S_IS_WEAK (fr_symbol
);
10248 /* Global symbols with non-default visibility can't be preempted. */
10249 if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol
)) != STV_DEFAULT
)
10252 if (fr_var
!= NO_RELOC
)
10253 switch ((enum bfd_reloc_code_real
) fr_var
)
10255 case BFD_RELOC_386_PLT32
:
10256 case BFD_RELOC_X86_64_PLT32
:
10257 /* Symbol with PLT relocation may be preempted. */
10263 /* Global symbols with default visibility in a shared library may be
10264 preempted by another definition. */
10269 /* md_estimate_size_before_relax()
10271 Called just before relax() for rs_machine_dependent frags. The x86
10272 assembler uses these frags to handle variable size jump
10275 Any symbol that is now undefined will not become defined.
10276 Return the correct fr_subtype in the frag.
10277 Return the initial "guess for variable size of frag" to caller.
10278 The guess is actually the growth beyond the fixed part. Whatever
10279 we do to grow the fixed or variable part contributes to our
10283 md_estimate_size_before_relax (fragS
*fragP
, segT segment
)
10285 /* We've already got fragP->fr_subtype right; all we have to do is
10286 check for un-relaxable symbols. On an ELF system, we can't relax
10287 an externally visible symbol, because it may be overridden by a
10289 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
10290 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10292 && !elf_symbol_resolved_in_segment_p (fragP
->fr_symbol
,
10295 #if defined (OBJ_COFF) && defined (TE_PE)
10296 || (OUTPUT_FLAVOR
== bfd_target_coff_flavour
10297 && S_IS_WEAK (fragP
->fr_symbol
))
10301 /* Symbol is undefined in this segment, or we need to keep a
10302 reloc so that weak symbols can be overridden. */
10303 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
10304 enum bfd_reloc_code_real reloc_type
;
10305 unsigned char *opcode
;
10308 if (fragP
->fr_var
!= NO_RELOC
)
10309 reloc_type
= (enum bfd_reloc_code_real
) fragP
->fr_var
;
10310 else if (size
== 2)
10311 reloc_type
= BFD_RELOC_16_PCREL
;
10312 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10313 else if (need_plt32_p (fragP
->fr_symbol
))
10314 reloc_type
= BFD_RELOC_X86_64_PLT32
;
10317 reloc_type
= BFD_RELOC_32_PCREL
;
10319 old_fr_fix
= fragP
->fr_fix
;
10320 opcode
= (unsigned char *) fragP
->fr_opcode
;
10322 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
10325 /* Make jmp (0xeb) a (d)word displacement jump. */
10327 fragP
->fr_fix
+= size
;
10328 fix_new (fragP
, old_fr_fix
, size
,
10330 fragP
->fr_offset
, 1,
10336 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
10338 /* Negate the condition, and branch past an
10339 unconditional jump. */
10342 /* Insert an unconditional jump. */
10344 /* We added two extra opcode bytes, and have a two byte
10346 fragP
->fr_fix
+= 2 + 2;
10347 fix_new (fragP
, old_fr_fix
+ 2, 2,
10349 fragP
->fr_offset
, 1,
10353 /* Fall through. */
10356 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
10360 fragP
->fr_fix
+= 1;
10361 fixP
= fix_new (fragP
, old_fr_fix
, 1,
10363 fragP
->fr_offset
, 1,
10364 BFD_RELOC_8_PCREL
);
10365 fixP
->fx_signed
= 1;
10369 /* This changes the byte-displacement jump 0x7N
10370 to the (d)word-displacement jump 0x0f,0x8N. */
10371 opcode
[1] = opcode
[0] + 0x10;
10372 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
10373 /* We've added an opcode byte. */
10374 fragP
->fr_fix
+= 1 + size
;
10375 fix_new (fragP
, old_fr_fix
+ 1, size
,
10377 fragP
->fr_offset
, 1,
10382 BAD_CASE (fragP
->fr_subtype
);
10386 return fragP
->fr_fix
- old_fr_fix
;
10389 /* Guess size depending on current relax state. Initially the relax
10390 state will correspond to a short jump and we return 1, because
10391 the variable part of the frag (the branch offset) is one byte
10392 long. However, we can relax a section more than once and in that
10393 case we must either set fr_subtype back to the unrelaxed state,
10394 or return the value for the appropriate branch. */
10395 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
10398 /* Called after relax() is finished.
10400 In: Address of frag.
10401 fr_type == rs_machine_dependent.
10402 fr_subtype is what the address relaxed to.
10404 Out: Any fixSs and constants are set up.
10405 Caller will turn frag into a ".space 0". */
10408 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec ATTRIBUTE_UNUSED
,
10411 unsigned char *opcode
;
10412 unsigned char *where_to_put_displacement
= NULL
;
10413 offsetT target_address
;
10414 offsetT opcode_address
;
10415 unsigned int extension
= 0;
10416 offsetT displacement_from_opcode_start
;
10418 opcode
= (unsigned char *) fragP
->fr_opcode
;
10420 /* Address we want to reach in file space. */
10421 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
10423 /* Address opcode resides at in file space. */
10424 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
10426 /* Displacement from opcode start to fill into instruction. */
10427 displacement_from_opcode_start
= target_address
- opcode_address
;
10429 if ((fragP
->fr_subtype
& BIG
) == 0)
10431 /* Don't have to change opcode. */
10432 extension
= 1; /* 1 opcode + 1 displacement */
10433 where_to_put_displacement
= &opcode
[1];
10437 if (no_cond_jump_promotion
10438 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
10439 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
10440 _("long jump required"));
10442 switch (fragP
->fr_subtype
)
10444 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
10445 extension
= 4; /* 1 opcode + 4 displacement */
10447 where_to_put_displacement
= &opcode
[1];
10450 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
10451 extension
= 2; /* 1 opcode + 2 displacement */
10453 where_to_put_displacement
= &opcode
[1];
10456 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
10457 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
10458 extension
= 5; /* 2 opcode + 4 displacement */
10459 opcode
[1] = opcode
[0] + 0x10;
10460 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
10461 where_to_put_displacement
= &opcode
[2];
10464 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
10465 extension
= 3; /* 2 opcode + 2 displacement */
10466 opcode
[1] = opcode
[0] + 0x10;
10467 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
10468 where_to_put_displacement
= &opcode
[2];
10471 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
10476 where_to_put_displacement
= &opcode
[3];
10480 BAD_CASE (fragP
->fr_subtype
);
10485 /* If size if less then four we are sure that the operand fits,
10486 but if it's 4, then it could be that the displacement is larger
10488 if (DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
) == 4
10490 && ((addressT
) (displacement_from_opcode_start
- extension
10491 + ((addressT
) 1 << 31))
10492 > (((addressT
) 2 << 31) - 1)))
10494 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
10495 _("jump target out of range"));
10496 /* Make us emit 0. */
10497 displacement_from_opcode_start
= extension
;
10499 /* Now put displacement after opcode. */
10500 md_number_to_chars ((char *) where_to_put_displacement
,
10501 (valueT
) (displacement_from_opcode_start
- extension
),
10502 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
10503 fragP
->fr_fix
+= extension
;
10506 /* Apply a fixup (fixP) to segment data, once it has been determined
10507 by our caller that we have all the info we need to fix it up.
10509 Parameter valP is the pointer to the value of the bits.
10511 On the 386, immediates, displacements, and data pointers are all in
10512 the same (little-endian) format, so we don't need to care about which
10513 we are handling. */
10516 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
10518 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
10519 valueT value
= *valP
;
10521 #if !defined (TE_Mach)
10522 if (fixP
->fx_pcrel
)
10524 switch (fixP
->fx_r_type
)
10530 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
10533 case BFD_RELOC_X86_64_32S
:
10534 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
10537 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
10540 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
10545 if (fixP
->fx_addsy
!= NULL
10546 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
10547 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
10548 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
10549 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
10550 && !use_rela_relocations
)
10552 /* This is a hack. There should be a better way to handle this.
10553 This covers for the fact that bfd_install_relocation will
10554 subtract the current location (for partial_inplace, PC relative
10555 relocations); see more below. */
10559 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
10562 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
10564 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10567 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
10569 if ((sym_seg
== seg
10570 || (symbol_section_p (fixP
->fx_addsy
)
10571 && sym_seg
!= absolute_section
))
10572 && !generic_force_reloc (fixP
))
10574 /* Yes, we add the values in twice. This is because
10575 bfd_install_relocation subtracts them out again. I think
10576 bfd_install_relocation is broken, but I don't dare change
10578 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
10582 #if defined (OBJ_COFF) && defined (TE_PE)
10583 /* For some reason, the PE format does not store a
10584 section address offset for a PC relative symbol. */
10585 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
10586 || S_IS_WEAK (fixP
->fx_addsy
))
10587 value
+= md_pcrel_from (fixP
);
10590 #if defined (OBJ_COFF) && defined (TE_PE)
10591 if (fixP
->fx_addsy
!= NULL
10592 && S_IS_WEAK (fixP
->fx_addsy
)
10593 /* PR 16858: Do not modify weak function references. */
10594 && ! fixP
->fx_pcrel
)
10596 #if !defined (TE_PEP)
10597 /* For x86 PE weak function symbols are neither PC-relative
10598 nor do they set S_IS_FUNCTION. So the only reliable way
10599 to detect them is to check the flags of their containing
10601 if (S_GET_SEGMENT (fixP
->fx_addsy
) != NULL
10602 && S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_CODE
)
10606 value
-= S_GET_VALUE (fixP
->fx_addsy
);
10610 /* Fix a few things - the dynamic linker expects certain values here,
10611 and we must not disappoint it. */
10612 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10613 if (IS_ELF
&& fixP
->fx_addsy
)
10614 switch (fixP
->fx_r_type
)
10616 case BFD_RELOC_386_PLT32
:
10617 case BFD_RELOC_X86_64_PLT32
:
10618 /* Make the jump instruction point to the address of the operand.
10619 At runtime we merely add the offset to the actual PLT entry.
10620 NB: Subtract the offset size only for jump instructions. */
10621 if (fixP
->fx_pcrel
)
10625 case BFD_RELOC_386_TLS_GD
:
10626 case BFD_RELOC_386_TLS_LDM
:
10627 case BFD_RELOC_386_TLS_IE_32
:
10628 case BFD_RELOC_386_TLS_IE
:
10629 case BFD_RELOC_386_TLS_GOTIE
:
10630 case BFD_RELOC_386_TLS_GOTDESC
:
10631 case BFD_RELOC_X86_64_TLSGD
:
10632 case BFD_RELOC_X86_64_TLSLD
:
10633 case BFD_RELOC_X86_64_GOTTPOFF
:
10634 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
10635 value
= 0; /* Fully resolved at runtime. No addend. */
10637 case BFD_RELOC_386_TLS_LE
:
10638 case BFD_RELOC_386_TLS_LDO_32
:
10639 case BFD_RELOC_386_TLS_LE_32
:
10640 case BFD_RELOC_X86_64_DTPOFF32
:
10641 case BFD_RELOC_X86_64_DTPOFF64
:
10642 case BFD_RELOC_X86_64_TPOFF32
:
10643 case BFD_RELOC_X86_64_TPOFF64
:
10644 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
10647 case BFD_RELOC_386_TLS_DESC_CALL
:
10648 case BFD_RELOC_X86_64_TLSDESC_CALL
:
10649 value
= 0; /* Fully resolved at runtime. No addend. */
10650 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
10654 case BFD_RELOC_VTABLE_INHERIT
:
10655 case BFD_RELOC_VTABLE_ENTRY
:
10662 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
10664 #endif /* !defined (TE_Mach) */
10666 /* Are we finished with this relocation now? */
10667 if (fixP
->fx_addsy
== NULL
)
10669 #if defined (OBJ_COFF) && defined (TE_PE)
10670 else if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
10673 /* Remember value for tc_gen_reloc. */
10674 fixP
->fx_addnumber
= value
;
10675 /* Clear out the frag for now. */
10679 else if (use_rela_relocations
)
10681 fixP
->fx_no_overflow
= 1;
10682 /* Remember value for tc_gen_reloc. */
10683 fixP
->fx_addnumber
= value
;
10687 md_number_to_chars (p
, value
, fixP
->fx_size
);
10691 md_atof (int type
, char *litP
, int *sizeP
)
10693 /* This outputs the LITTLENUMs in REVERSE order;
10694 in accord with the bigendian 386. */
10695 return ieee_md_atof (type
, litP
, sizeP
, FALSE
);
10698 static char output_invalid_buf
[sizeof (unsigned char) * 2 + 6];
10701 output_invalid (int c
)
10704 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
10707 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
10708 "(0x%x)", (unsigned char) c
);
10709 return output_invalid_buf
;
10712 /* REG_STRING starts *before* REGISTER_PREFIX. */
10714 static const reg_entry
*
10715 parse_real_register (char *reg_string
, char **end_op
)
10717 char *s
= reg_string
;
10719 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
10720 const reg_entry
*r
;
10722 /* Skip possible REGISTER_PREFIX and possible whitespace. */
10723 if (*s
== REGISTER_PREFIX
)
10726 if (is_space_char (*s
))
10729 p
= reg_name_given
;
10730 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
10732 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
10733 return (const reg_entry
*) NULL
;
10737 /* For naked regs, make sure that we are not dealing with an identifier.
10738 This prevents confusing an identifier like `eax_var' with register
10740 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
10741 return (const reg_entry
*) NULL
;
10745 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
10747 /* Handle floating point regs, allowing spaces in the (i) part. */
10748 if (r
== i386_regtab
/* %st is first entry of table */)
10750 if (!cpu_arch_flags
.bitfield
.cpu8087
10751 && !cpu_arch_flags
.bitfield
.cpu287
10752 && !cpu_arch_flags
.bitfield
.cpu387
)
10753 return (const reg_entry
*) NULL
;
10755 if (is_space_char (*s
))
10760 if (is_space_char (*s
))
10762 if (*s
>= '0' && *s
<= '7')
10764 int fpr
= *s
- '0';
10766 if (is_space_char (*s
))
10771 r
= (const reg_entry
*) hash_find (reg_hash
, "st(0)");
10776 /* We have "%st(" then garbage. */
10777 return (const reg_entry
*) NULL
;
10781 if (r
== NULL
|| allow_pseudo_reg
)
10784 if (operand_type_all_zero (&r
->reg_type
))
10785 return (const reg_entry
*) NULL
;
10787 if ((r
->reg_type
.bitfield
.dword
10788 || r
->reg_type
.bitfield
.sreg3
10789 || r
->reg_type
.bitfield
.control
10790 || r
->reg_type
.bitfield
.debug
10791 || r
->reg_type
.bitfield
.test
)
10792 && !cpu_arch_flags
.bitfield
.cpui386
)
10793 return (const reg_entry
*) NULL
;
10795 if (r
->reg_type
.bitfield
.regmmx
&& !cpu_arch_flags
.bitfield
.cpummx
)
10796 return (const reg_entry
*) NULL
;
10798 if (!cpu_arch_flags
.bitfield
.cpuavx512f
)
10800 if (r
->reg_type
.bitfield
.zmmword
|| r
->reg_type
.bitfield
.regmask
)
10801 return (const reg_entry
*) NULL
;
10803 if (!cpu_arch_flags
.bitfield
.cpuavx
)
10805 if (r
->reg_type
.bitfield
.ymmword
)
10806 return (const reg_entry
*) NULL
;
10808 if (!cpu_arch_flags
.bitfield
.cpusse
&& r
->reg_type
.bitfield
.xmmword
)
10809 return (const reg_entry
*) NULL
;
10813 if (r
->reg_type
.bitfield
.regbnd
&& !cpu_arch_flags
.bitfield
.cpumpx
)
10814 return (const reg_entry
*) NULL
;
10816 /* Don't allow fake index register unless allow_index_reg isn't 0. */
10817 if (!allow_index_reg
&& r
->reg_num
== RegIZ
)
10818 return (const reg_entry
*) NULL
;
10820 /* Upper 16 vector registers are only available with VREX in 64bit
10821 mode, and require EVEX encoding. */
10822 if (r
->reg_flags
& RegVRex
)
10824 if (!cpu_arch_flags
.bitfield
.cpuavx512f
10825 || flag_code
!= CODE_64BIT
)
10826 return (const reg_entry
*) NULL
;
10828 i
.vec_encoding
= vex_encoding_evex
;
10831 if (((r
->reg_flags
& (RegRex64
| RegRex
)) || r
->reg_type
.bitfield
.qword
)
10832 && (!cpu_arch_flags
.bitfield
.cpulm
|| !r
->reg_type
.bitfield
.control
)
10833 && flag_code
!= CODE_64BIT
)
10834 return (const reg_entry
*) NULL
;
10836 if (r
->reg_type
.bitfield
.sreg3
&& r
->reg_num
== RegFlat
&& !intel_syntax
)
10837 return (const reg_entry
*) NULL
;
10842 /* REG_STRING starts *before* REGISTER_PREFIX. */
10844 static const reg_entry
*
10845 parse_register (char *reg_string
, char **end_op
)
10847 const reg_entry
*r
;
10849 if (*reg_string
== REGISTER_PREFIX
|| allow_naked_reg
)
10850 r
= parse_real_register (reg_string
, end_op
);
10855 char *save
= input_line_pointer
;
10859 input_line_pointer
= reg_string
;
10860 c
= get_symbol_name (®_string
);
10861 symbolP
= symbol_find (reg_string
);
10862 if (symbolP
&& S_GET_SEGMENT (symbolP
) == reg_section
)
10864 const expressionS
*e
= symbol_get_value_expression (symbolP
);
10866 know (e
->X_op
== O_register
);
10867 know (e
->X_add_number
>= 0
10868 && (valueT
) e
->X_add_number
< i386_regtab_size
);
10869 r
= i386_regtab
+ e
->X_add_number
;
10870 if ((r
->reg_flags
& RegVRex
))
10871 i
.vec_encoding
= vex_encoding_evex
;
10872 *end_op
= input_line_pointer
;
10874 *input_line_pointer
= c
;
10875 input_line_pointer
= save
;
10881 i386_parse_name (char *name
, expressionS
*e
, char *nextcharP
)
10883 const reg_entry
*r
;
10884 char *end
= input_line_pointer
;
10887 r
= parse_register (name
, &input_line_pointer
);
10888 if (r
&& end
<= input_line_pointer
)
10890 *nextcharP
= *input_line_pointer
;
10891 *input_line_pointer
= 0;
10892 e
->X_op
= O_register
;
10893 e
->X_add_number
= r
- i386_regtab
;
10896 input_line_pointer
= end
;
10898 return intel_syntax
? i386_intel_parse_name (name
, e
) : 0;
10902 md_operand (expressionS
*e
)
10905 const reg_entry
*r
;
10907 switch (*input_line_pointer
)
10909 case REGISTER_PREFIX
:
10910 r
= parse_real_register (input_line_pointer
, &end
);
10913 e
->X_op
= O_register
;
10914 e
->X_add_number
= r
- i386_regtab
;
10915 input_line_pointer
= end
;
10920 gas_assert (intel_syntax
);
10921 end
= input_line_pointer
++;
10923 if (*input_line_pointer
== ']')
10925 ++input_line_pointer
;
10926 e
->X_op_symbol
= make_expr_symbol (e
);
10927 e
->X_add_symbol
= NULL
;
10928 e
->X_add_number
= 0;
10933 e
->X_op
= O_absent
;
10934 input_line_pointer
= end
;
10941 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10942 const char *md_shortopts
= "kVQ:sqnO::";
10944 const char *md_shortopts
= "qnO::";
10947 #define OPTION_32 (OPTION_MD_BASE + 0)
10948 #define OPTION_64 (OPTION_MD_BASE + 1)
10949 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
10950 #define OPTION_MARCH (OPTION_MD_BASE + 3)
10951 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
10952 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
10953 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
10954 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
10955 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
10956 #define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 9)
10957 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
10958 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
10959 #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
10960 #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
10961 #define OPTION_X32 (OPTION_MD_BASE + 14)
10962 #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
10963 #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
10964 #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
10965 #define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
10966 #define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
10967 #define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
10968 #define OPTION_MSHARED (OPTION_MD_BASE + 21)
10969 #define OPTION_MAMD64 (OPTION_MD_BASE + 22)
10970 #define OPTION_MINTEL64 (OPTION_MD_BASE + 23)
10971 #define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24)
10972 #define OPTION_X86_USED_NOTE (OPTION_MD_BASE + 25)
10973 #define OPTION_MVEXWIG (OPTION_MD_BASE + 26)
10975 struct option md_longopts
[] =
10977 {"32", no_argument
, NULL
, OPTION_32
},
10978 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10979 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
10980 {"64", no_argument
, NULL
, OPTION_64
},
10982 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10983 {"x32", no_argument
, NULL
, OPTION_X32
},
10984 {"mshared", no_argument
, NULL
, OPTION_MSHARED
},
10985 {"mx86-used-note", required_argument
, NULL
, OPTION_X86_USED_NOTE
},
10987 {"divide", no_argument
, NULL
, OPTION_DIVIDE
},
10988 {"march", required_argument
, NULL
, OPTION_MARCH
},
10989 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
10990 {"mmnemonic", required_argument
, NULL
, OPTION_MMNEMONIC
},
10991 {"msyntax", required_argument
, NULL
, OPTION_MSYNTAX
},
10992 {"mindex-reg", no_argument
, NULL
, OPTION_MINDEX_REG
},
10993 {"mnaked-reg", no_argument
, NULL
, OPTION_MNAKED_REG
},
10994 {"msse2avx", no_argument
, NULL
, OPTION_MSSE2AVX
},
10995 {"msse-check", required_argument
, NULL
, OPTION_MSSE_CHECK
},
10996 {"moperand-check", required_argument
, NULL
, OPTION_MOPERAND_CHECK
},
10997 {"mavxscalar", required_argument
, NULL
, OPTION_MAVXSCALAR
},
10998 {"mvexwig", required_argument
, NULL
, OPTION_MVEXWIG
},
10999 {"madd-bnd-prefix", no_argument
, NULL
, OPTION_MADD_BND_PREFIX
},
11000 {"mevexlig", required_argument
, NULL
, OPTION_MEVEXLIG
},
11001 {"mevexwig", required_argument
, NULL
, OPTION_MEVEXWIG
},
11002 # if defined (TE_PE) || defined (TE_PEP)
11003 {"mbig-obj", no_argument
, NULL
, OPTION_MBIG_OBJ
},
11005 {"momit-lock-prefix", required_argument
, NULL
, OPTION_MOMIT_LOCK_PREFIX
},
11006 {"mfence-as-lock-add", required_argument
, NULL
, OPTION_MFENCE_AS_LOCK_ADD
},
11007 {"mrelax-relocations", required_argument
, NULL
, OPTION_MRELAX_RELOCATIONS
},
11008 {"mevexrcig", required_argument
, NULL
, OPTION_MEVEXRCIG
},
11009 {"mamd64", no_argument
, NULL
, OPTION_MAMD64
},
11010 {"mintel64", no_argument
, NULL
, OPTION_MINTEL64
},
11011 {NULL
, no_argument
, NULL
, 0}
11013 size_t md_longopts_size
= sizeof (md_longopts
);
11016 md_parse_option (int c
, const char *arg
)
11019 char *arch
, *next
, *saved
;
11024 optimize_align_code
= 0;
11028 quiet_warnings
= 1;
11031 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11032 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
11033 should be emitted or not. FIXME: Not implemented. */
11037 /* -V: SVR4 argument to print version ID. */
11039 print_version_id ();
11042 /* -k: Ignore for FreeBSD compatibility. */
11047 /* -s: On i386 Solaris, this tells the native assembler to use
11048 .stab instead of .stab.excl. We always use .stab anyhow. */
11051 case OPTION_MSHARED
:
11055 case OPTION_X86_USED_NOTE
:
11056 if (strcasecmp (arg
, "yes") == 0)
11058 else if (strcasecmp (arg
, "no") == 0)
11061 as_fatal (_("invalid -mx86-used-note= option: `%s'"), arg
);
11066 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
11067 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
11070 const char **list
, **l
;
11072 list
= bfd_target_list ();
11073 for (l
= list
; *l
!= NULL
; l
++)
11074 if (CONST_STRNEQ (*l
, "elf64-x86-64")
11075 || strcmp (*l
, "coff-x86-64") == 0
11076 || strcmp (*l
, "pe-x86-64") == 0
11077 || strcmp (*l
, "pei-x86-64") == 0
11078 || strcmp (*l
, "mach-o-x86-64") == 0)
11080 default_arch
= "x86_64";
11084 as_fatal (_("no compiled in support for x86_64"));
11090 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11094 const char **list
, **l
;
11096 list
= bfd_target_list ();
11097 for (l
= list
; *l
!= NULL
; l
++)
11098 if (CONST_STRNEQ (*l
, "elf32-x86-64"))
11100 default_arch
= "x86_64:32";
11104 as_fatal (_("no compiled in support for 32bit x86_64"));
11108 as_fatal (_("32bit x86_64 is only supported for ELF"));
11113 default_arch
= "i386";
11116 case OPTION_DIVIDE
:
11117 #ifdef SVR4_COMMENT_CHARS
11122 n
= XNEWVEC (char, strlen (i386_comment_chars
) + 1);
11124 for (s
= i386_comment_chars
; *s
!= '\0'; s
++)
11128 i386_comment_chars
= n
;
11134 saved
= xstrdup (arg
);
11136 /* Allow -march=+nosse. */
11142 as_fatal (_("invalid -march= option: `%s'"), arg
);
11143 next
= strchr (arch
, '+');
11146 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
11148 if (strcmp (arch
, cpu_arch
[j
].name
) == 0)
11151 if (! cpu_arch
[j
].flags
.bitfield
.cpui386
)
11154 cpu_arch_name
= cpu_arch
[j
].name
;
11155 cpu_sub_arch_name
= NULL
;
11156 cpu_arch_flags
= cpu_arch
[j
].flags
;
11157 cpu_arch_isa
= cpu_arch
[j
].type
;
11158 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
11159 if (!cpu_arch_tune_set
)
11161 cpu_arch_tune
= cpu_arch_isa
;
11162 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
11166 else if (*cpu_arch
[j
].name
== '.'
11167 && strcmp (arch
, cpu_arch
[j
].name
+ 1) == 0)
11169 /* ISA extension. */
11170 i386_cpu_flags flags
;
11172 flags
= cpu_flags_or (cpu_arch_flags
,
11173 cpu_arch
[j
].flags
);
11175 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
11177 if (cpu_sub_arch_name
)
11179 char *name
= cpu_sub_arch_name
;
11180 cpu_sub_arch_name
= concat (name
,
11182 (const char *) NULL
);
11186 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
11187 cpu_arch_flags
= flags
;
11188 cpu_arch_isa_flags
= flags
;
11192 = cpu_flags_or (cpu_arch_isa_flags
,
11193 cpu_arch
[j
].flags
);
11198 if (j
>= ARRAY_SIZE (cpu_arch
))
11200 /* Disable an ISA extension. */
11201 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
11202 if (strcmp (arch
, cpu_noarch
[j
].name
) == 0)
11204 i386_cpu_flags flags
;
11206 flags
= cpu_flags_and_not (cpu_arch_flags
,
11207 cpu_noarch
[j
].flags
);
11208 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
11210 if (cpu_sub_arch_name
)
11212 char *name
= cpu_sub_arch_name
;
11213 cpu_sub_arch_name
= concat (arch
,
11214 (const char *) NULL
);
11218 cpu_sub_arch_name
= xstrdup (arch
);
11219 cpu_arch_flags
= flags
;
11220 cpu_arch_isa_flags
= flags
;
11225 if (j
>= ARRAY_SIZE (cpu_noarch
))
11226 j
= ARRAY_SIZE (cpu_arch
);
11229 if (j
>= ARRAY_SIZE (cpu_arch
))
11230 as_fatal (_("invalid -march= option: `%s'"), arg
);
11234 while (next
!= NULL
);
11240 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
11241 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
11243 if (strcmp (arg
, cpu_arch
[j
].name
) == 0)
11245 cpu_arch_tune_set
= 1;
11246 cpu_arch_tune
= cpu_arch
[j
].type
;
11247 cpu_arch_tune_flags
= cpu_arch
[j
].flags
;
11251 if (j
>= ARRAY_SIZE (cpu_arch
))
11252 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
11255 case OPTION_MMNEMONIC
:
11256 if (strcasecmp (arg
, "att") == 0)
11257 intel_mnemonic
= 0;
11258 else if (strcasecmp (arg
, "intel") == 0)
11259 intel_mnemonic
= 1;
11261 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg
);
11264 case OPTION_MSYNTAX
:
11265 if (strcasecmp (arg
, "att") == 0)
11267 else if (strcasecmp (arg
, "intel") == 0)
11270 as_fatal (_("invalid -msyntax= option: `%s'"), arg
);
11273 case OPTION_MINDEX_REG
:
11274 allow_index_reg
= 1;
11277 case OPTION_MNAKED_REG
:
11278 allow_naked_reg
= 1;
11281 case OPTION_MSSE2AVX
:
11285 case OPTION_MSSE_CHECK
:
11286 if (strcasecmp (arg
, "error") == 0)
11287 sse_check
= check_error
;
11288 else if (strcasecmp (arg
, "warning") == 0)
11289 sse_check
= check_warning
;
11290 else if (strcasecmp (arg
, "none") == 0)
11291 sse_check
= check_none
;
11293 as_fatal (_("invalid -msse-check= option: `%s'"), arg
);
11296 case OPTION_MOPERAND_CHECK
:
11297 if (strcasecmp (arg
, "error") == 0)
11298 operand_check
= check_error
;
11299 else if (strcasecmp (arg
, "warning") == 0)
11300 operand_check
= check_warning
;
11301 else if (strcasecmp (arg
, "none") == 0)
11302 operand_check
= check_none
;
11304 as_fatal (_("invalid -moperand-check= option: `%s'"), arg
);
11307 case OPTION_MAVXSCALAR
:
11308 if (strcasecmp (arg
, "128") == 0)
11309 avxscalar
= vex128
;
11310 else if (strcasecmp (arg
, "256") == 0)
11311 avxscalar
= vex256
;
11313 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg
);
11316 case OPTION_MVEXWIG
:
11317 if (strcmp (arg
, "0") == 0)
11319 else if (strcmp (arg
, "1") == 0)
11322 as_fatal (_("invalid -mvexwig= option: `%s'"), arg
);
11325 case OPTION_MADD_BND_PREFIX
:
11326 add_bnd_prefix
= 1;
11329 case OPTION_MEVEXLIG
:
11330 if (strcmp (arg
, "128") == 0)
11331 evexlig
= evexl128
;
11332 else if (strcmp (arg
, "256") == 0)
11333 evexlig
= evexl256
;
11334 else if (strcmp (arg
, "512") == 0)
11335 evexlig
= evexl512
;
11337 as_fatal (_("invalid -mevexlig= option: `%s'"), arg
);
11340 case OPTION_MEVEXRCIG
:
11341 if (strcmp (arg
, "rne") == 0)
11343 else if (strcmp (arg
, "rd") == 0)
11345 else if (strcmp (arg
, "ru") == 0)
11347 else if (strcmp (arg
, "rz") == 0)
11350 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg
);
11353 case OPTION_MEVEXWIG
:
11354 if (strcmp (arg
, "0") == 0)
11356 else if (strcmp (arg
, "1") == 0)
11359 as_fatal (_("invalid -mevexwig= option: `%s'"), arg
);
11362 # if defined (TE_PE) || defined (TE_PEP)
11363 case OPTION_MBIG_OBJ
:
11368 case OPTION_MOMIT_LOCK_PREFIX
:
11369 if (strcasecmp (arg
, "yes") == 0)
11370 omit_lock_prefix
= 1;
11371 else if (strcasecmp (arg
, "no") == 0)
11372 omit_lock_prefix
= 0;
11374 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg
);
11377 case OPTION_MFENCE_AS_LOCK_ADD
:
11378 if (strcasecmp (arg
, "yes") == 0)
11380 else if (strcasecmp (arg
, "no") == 0)
11383 as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg
);
11386 case OPTION_MRELAX_RELOCATIONS
:
11387 if (strcasecmp (arg
, "yes") == 0)
11388 generate_relax_relocations
= 1;
11389 else if (strcasecmp (arg
, "no") == 0)
11390 generate_relax_relocations
= 0;
11392 as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg
);
11395 case OPTION_MAMD64
:
11399 case OPTION_MINTEL64
:
11407 /* Turn off -Os. */
11408 optimize_for_space
= 0;
11410 else if (*arg
== 's')
11412 optimize_for_space
= 1;
11413 /* Turn on all encoding optimizations. */
11414 optimize
= INT_MAX
;
11418 optimize
= atoi (arg
);
11419 /* Turn off -Os. */
11420 optimize_for_space
= 0;
11430 #define MESSAGE_TEMPLATE \
11434 output_message (FILE *stream
, char *p
, char *message
, char *start
,
11435 int *left_p
, const char *name
, int len
)
11437 int size
= sizeof (MESSAGE_TEMPLATE
);
11438 int left
= *left_p
;
11440 /* Reserve 2 spaces for ", " or ",\0" */
11443 /* Check if there is any room. */
11451 p
= mempcpy (p
, name
, len
);
11455 /* Output the current message now and start a new one. */
11458 fprintf (stream
, "%s\n", message
);
11460 left
= size
- (start
- message
) - len
- 2;
11462 gas_assert (left
>= 0);
11464 p
= mempcpy (p
, name
, len
);
11472 show_arch (FILE *stream
, int ext
, int check
)
11474 static char message
[] = MESSAGE_TEMPLATE
;
11475 char *start
= message
+ 27;
11477 int size
= sizeof (MESSAGE_TEMPLATE
);
11484 left
= size
- (start
- message
);
11485 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
11487 /* Should it be skipped? */
11488 if (cpu_arch
[j
].skip
)
11491 name
= cpu_arch
[j
].name
;
11492 len
= cpu_arch
[j
].len
;
11495 /* It is an extension. Skip if we aren't asked to show it. */
11506 /* It is an processor. Skip if we show only extension. */
11509 else if (check
&& ! cpu_arch
[j
].flags
.bitfield
.cpui386
)
11511 /* It is an impossible processor - skip. */
11515 p
= output_message (stream
, p
, message
, start
, &left
, name
, len
);
11518 /* Display disabled extensions. */
11520 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
11522 name
= cpu_noarch
[j
].name
;
11523 len
= cpu_noarch
[j
].len
;
11524 p
= output_message (stream
, p
, message
, start
, &left
, name
,
11529 fprintf (stream
, "%s\n", message
);
11533 md_show_usage (FILE *stream
)
11535 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11536 fprintf (stream
, _("\
11538 -V print assembler version number\n\
11541 fprintf (stream
, _("\
11542 -n Do not optimize code alignment\n\
11543 -q quieten some warnings\n"));
11544 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11545 fprintf (stream
, _("\
11548 #if defined BFD64 && (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
11549 || defined (TE_PE) || defined (TE_PEP))
11550 fprintf (stream
, _("\
11551 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
11553 #ifdef SVR4_COMMENT_CHARS
11554 fprintf (stream
, _("\
11555 --divide do not treat `/' as a comment character\n"));
11557 fprintf (stream
, _("\
11558 --divide ignored\n"));
11560 fprintf (stream
, _("\
11561 -march=CPU[,+EXTENSION...]\n\
11562 generate code for CPU and EXTENSION, CPU is one of:\n"));
11563 show_arch (stream
, 0, 1);
11564 fprintf (stream
, _("\
11565 EXTENSION is combination of:\n"));
11566 show_arch (stream
, 1, 0);
11567 fprintf (stream
, _("\
11568 -mtune=CPU optimize for CPU, CPU is one of:\n"));
11569 show_arch (stream
, 0, 0);
11570 fprintf (stream
, _("\
11571 -msse2avx encode SSE instructions with VEX prefix\n"));
11572 fprintf (stream
, _("\
11573 -msse-check=[none|error|warning] (default: warning)\n\
11574 check SSE instructions\n"));
11575 fprintf (stream
, _("\
11576 -moperand-check=[none|error|warning] (default: warning)\n\
11577 check operand combinations for validity\n"));
11578 fprintf (stream
, _("\
11579 -mavxscalar=[128|256] (default: 128)\n\
11580 encode scalar AVX instructions with specific vector\n\
11582 fprintf (stream
, _("\
11583 -mvexwig=[0|1] (default: 0)\n\
11584 encode VEX instructions with specific VEX.W value\n\
11585 for VEX.W bit ignored instructions\n"));
11586 fprintf (stream
, _("\
11587 -mevexlig=[128|256|512] (default: 128)\n\
11588 encode scalar EVEX instructions with specific vector\n\
11590 fprintf (stream
, _("\
11591 -mevexwig=[0|1] (default: 0)\n\
11592 encode EVEX instructions with specific EVEX.W value\n\
11593 for EVEX.W bit ignored instructions\n"));
11594 fprintf (stream
, _("\
11595 -mevexrcig=[rne|rd|ru|rz] (default: rne)\n\
11596 encode EVEX instructions with specific EVEX.RC value\n\
11597 for SAE-only ignored instructions\n"));
11598 fprintf (stream
, _("\
11599 -mmnemonic=[att|intel] "));
11600 if (SYSV386_COMPAT
)
11601 fprintf (stream
, _("(default: att)\n"));
11603 fprintf (stream
, _("(default: intel)\n"));
11604 fprintf (stream
, _("\
11605 use AT&T/Intel mnemonic\n"));
11606 fprintf (stream
, _("\
11607 -msyntax=[att|intel] (default: att)\n\
11608 use AT&T/Intel syntax\n"));
11609 fprintf (stream
, _("\
11610 -mindex-reg support pseudo index registers\n"));
11611 fprintf (stream
, _("\
11612 -mnaked-reg don't require `%%' prefix for registers\n"));
11613 fprintf (stream
, _("\
11614 -madd-bnd-prefix add BND prefix for all valid branches\n"));
11615 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11616 fprintf (stream
, _("\
11617 -mshared disable branch optimization for shared code\n"));
11618 fprintf (stream
, _("\
11619 -mx86-used-note=[no|yes] "));
11620 if (DEFAULT_X86_USED_NOTE
)
11621 fprintf (stream
, _("(default: yes)\n"));
11623 fprintf (stream
, _("(default: no)\n"));
11624 fprintf (stream
, _("\
11625 generate x86 used ISA and feature properties\n"));
11627 #if defined (TE_PE) || defined (TE_PEP)
11628 fprintf (stream
, _("\
11629 -mbig-obj generate big object files\n"));
11631 fprintf (stream
, _("\
11632 -momit-lock-prefix=[no|yes] (default: no)\n\
11633 strip all lock prefixes\n"));
11634 fprintf (stream
, _("\
11635 -mfence-as-lock-add=[no|yes] (default: no)\n\
11636 encode lfence, mfence and sfence as\n\
11637 lock addl $0x0, (%%{re}sp)\n"));
11638 fprintf (stream
, _("\
11639 -mrelax-relocations=[no|yes] "));
11640 if (DEFAULT_GENERATE_X86_RELAX_RELOCATIONS
)
11641 fprintf (stream
, _("(default: yes)\n"));
11643 fprintf (stream
, _("(default: no)\n"));
11644 fprintf (stream
, _("\
11645 generate relax relocations\n"));
11646 fprintf (stream
, _("\
11647 -mamd64 accept only AMD64 ISA [default]\n"));
11648 fprintf (stream
, _("\
11649 -mintel64 accept only Intel64 ISA\n"));
11652 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
11653 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
11654 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
11656 /* Pick the target format to use. */
11659 i386_target_format (void)
11661 if (!strncmp (default_arch
, "x86_64", 6))
11663 update_code_flag (CODE_64BIT
, 1);
11664 if (default_arch
[6] == '\0')
11665 x86_elf_abi
= X86_64_ABI
;
11667 x86_elf_abi
= X86_64_X32_ABI
;
11669 else if (!strcmp (default_arch
, "i386"))
11670 update_code_flag (CODE_32BIT
, 1);
11671 else if (!strcmp (default_arch
, "iamcu"))
11673 update_code_flag (CODE_32BIT
, 1);
11674 if (cpu_arch_isa
== PROCESSOR_UNKNOWN
)
11676 static const i386_cpu_flags iamcu_flags
= CPU_IAMCU_FLAGS
;
11677 cpu_arch_name
= "iamcu";
11678 cpu_sub_arch_name
= NULL
;
11679 cpu_arch_flags
= iamcu_flags
;
11680 cpu_arch_isa
= PROCESSOR_IAMCU
;
11681 cpu_arch_isa_flags
= iamcu_flags
;
11682 if (!cpu_arch_tune_set
)
11684 cpu_arch_tune
= cpu_arch_isa
;
11685 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
11688 else if (cpu_arch_isa
!= PROCESSOR_IAMCU
)
11689 as_fatal (_("Intel MCU doesn't support `%s' architecture"),
11693 as_fatal (_("unknown architecture"));
11695 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
11696 cpu_arch_isa_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
11697 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
11698 cpu_arch_tune_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
11700 switch (OUTPUT_FLAVOR
)
11702 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
11703 case bfd_target_aout_flavour
:
11704 return AOUT_TARGET_FORMAT
;
11706 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
11707 # if defined (TE_PE) || defined (TE_PEP)
11708 case bfd_target_coff_flavour
:
11709 if (flag_code
== CODE_64BIT
)
11710 return use_big_obj
? "pe-bigobj-x86-64" : "pe-x86-64";
11713 # elif defined (TE_GO32)
11714 case bfd_target_coff_flavour
:
11715 return "coff-go32";
11717 case bfd_target_coff_flavour
:
11718 return "coff-i386";
11721 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
11722 case bfd_target_elf_flavour
:
11724 const char *format
;
11726 switch (x86_elf_abi
)
11729 format
= ELF_TARGET_FORMAT
;
11732 use_rela_relocations
= 1;
11734 format
= ELF_TARGET_FORMAT64
;
11736 case X86_64_X32_ABI
:
11737 use_rela_relocations
= 1;
11739 disallow_64bit_reloc
= 1;
11740 format
= ELF_TARGET_FORMAT32
;
11743 if (cpu_arch_isa
== PROCESSOR_L1OM
)
11745 if (x86_elf_abi
!= X86_64_ABI
)
11746 as_fatal (_("Intel L1OM is 64bit only"));
11747 return ELF_TARGET_L1OM_FORMAT
;
11749 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
11751 if (x86_elf_abi
!= X86_64_ABI
)
11752 as_fatal (_("Intel K1OM is 64bit only"));
11753 return ELF_TARGET_K1OM_FORMAT
;
11755 else if (cpu_arch_isa
== PROCESSOR_IAMCU
)
11757 if (x86_elf_abi
!= I386_ABI
)
11758 as_fatal (_("Intel MCU is 32bit only"));
11759 return ELF_TARGET_IAMCU_FORMAT
;
11765 #if defined (OBJ_MACH_O)
11766 case bfd_target_mach_o_flavour
:
11767 if (flag_code
== CODE_64BIT
)
11769 use_rela_relocations
= 1;
11771 return "mach-o-x86-64";
11774 return "mach-o-i386";
11782 #endif /* OBJ_MAYBE_ more than one */
11785 md_undefined_symbol (char *name
)
11787 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
11788 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
11789 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
11790 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
11794 if (symbol_find (name
))
11795 as_bad (_("GOT already in symbol table"));
11796 GOT_symbol
= symbol_new (name
, undefined_section
,
11797 (valueT
) 0, &zero_address_frag
);
11804 /* Round up a section size to the appropriate boundary. */
11807 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
11809 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
11810 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
11812 /* For a.out, force the section size to be aligned. If we don't do
11813 this, BFD will align it for us, but it will not write out the
11814 final bytes of the section. This may be a bug in BFD, but it is
11815 easier to fix it here since that is how the other a.out targets
11819 align
= bfd_get_section_alignment (stdoutput
, segment
);
11820 size
= ((size
+ (1 << align
) - 1) & (-((valueT
) 1 << align
)));
11827 /* On the i386, PC-relative offsets are relative to the start of the
11828 next instruction. That is, the address of the offset, plus its
11829 size, since the offset is always the last part of the insn. */
11832 md_pcrel_from (fixS
*fixP
)
11834 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
11840 s_bss (int ignore ATTRIBUTE_UNUSED
)
11844 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11846 obj_elf_section_change_hook ();
11848 temp
= get_absolute_expression ();
11849 subseg_set (bss_section
, (subsegT
) temp
);
11850 demand_empty_rest_of_line ();
11856 i386_validate_fix (fixS
*fixp
)
11858 if (fixp
->fx_subsy
)
11860 if (fixp
->fx_subsy
== GOT_symbol
)
11862 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
11866 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11867 if (fixp
->fx_tcbit2
)
11868 fixp
->fx_r_type
= (fixp
->fx_tcbit
11869 ? BFD_RELOC_X86_64_REX_GOTPCRELX
11870 : BFD_RELOC_X86_64_GOTPCRELX
);
11873 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
11878 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
11880 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
11882 fixp
->fx_subsy
= 0;
11885 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11886 else if (!object_64bit
)
11888 if (fixp
->fx_r_type
== BFD_RELOC_386_GOT32
11889 && fixp
->fx_tcbit2
)
11890 fixp
->fx_r_type
= BFD_RELOC_386_GOT32X
;
11896 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
11899 bfd_reloc_code_real_type code
;
11901 switch (fixp
->fx_r_type
)
11903 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11904 case BFD_RELOC_SIZE32
:
11905 case BFD_RELOC_SIZE64
:
11906 if (S_IS_DEFINED (fixp
->fx_addsy
)
11907 && !S_IS_EXTERNAL (fixp
->fx_addsy
))
11909 /* Resolve size relocation against local symbol to size of
11910 the symbol plus addend. */
11911 valueT value
= S_GET_SIZE (fixp
->fx_addsy
) + fixp
->fx_offset
;
11912 if (fixp
->fx_r_type
== BFD_RELOC_SIZE32
11913 && !fits_in_unsigned_long (value
))
11914 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
11915 _("symbol size computation overflow"));
11916 fixp
->fx_addsy
= NULL
;
11917 fixp
->fx_subsy
= NULL
;
11918 md_apply_fix (fixp
, (valueT
*) &value
, NULL
);
11922 /* Fall through. */
11924 case BFD_RELOC_X86_64_PLT32
:
11925 case BFD_RELOC_X86_64_GOT32
:
11926 case BFD_RELOC_X86_64_GOTPCREL
:
11927 case BFD_RELOC_X86_64_GOTPCRELX
:
11928 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
11929 case BFD_RELOC_386_PLT32
:
11930 case BFD_RELOC_386_GOT32
:
11931 case BFD_RELOC_386_GOT32X
:
11932 case BFD_RELOC_386_GOTOFF
:
11933 case BFD_RELOC_386_GOTPC
:
11934 case BFD_RELOC_386_TLS_GD
:
11935 case BFD_RELOC_386_TLS_LDM
:
11936 case BFD_RELOC_386_TLS_LDO_32
:
11937 case BFD_RELOC_386_TLS_IE_32
:
11938 case BFD_RELOC_386_TLS_IE
:
11939 case BFD_RELOC_386_TLS_GOTIE
:
11940 case BFD_RELOC_386_TLS_LE_32
:
11941 case BFD_RELOC_386_TLS_LE
:
11942 case BFD_RELOC_386_TLS_GOTDESC
:
11943 case BFD_RELOC_386_TLS_DESC_CALL
:
11944 case BFD_RELOC_X86_64_TLSGD
:
11945 case BFD_RELOC_X86_64_TLSLD
:
11946 case BFD_RELOC_X86_64_DTPOFF32
:
11947 case BFD_RELOC_X86_64_DTPOFF64
:
11948 case BFD_RELOC_X86_64_GOTTPOFF
:
11949 case BFD_RELOC_X86_64_TPOFF32
:
11950 case BFD_RELOC_X86_64_TPOFF64
:
11951 case BFD_RELOC_X86_64_GOTOFF64
:
11952 case BFD_RELOC_X86_64_GOTPC32
:
11953 case BFD_RELOC_X86_64_GOT64
:
11954 case BFD_RELOC_X86_64_GOTPCREL64
:
11955 case BFD_RELOC_X86_64_GOTPC64
:
11956 case BFD_RELOC_X86_64_GOTPLT64
:
11957 case BFD_RELOC_X86_64_PLTOFF64
:
11958 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
11959 case BFD_RELOC_X86_64_TLSDESC_CALL
:
11960 case BFD_RELOC_RVA
:
11961 case BFD_RELOC_VTABLE_ENTRY
:
11962 case BFD_RELOC_VTABLE_INHERIT
:
11964 case BFD_RELOC_32_SECREL
:
11966 code
= fixp
->fx_r_type
;
11968 case BFD_RELOC_X86_64_32S
:
11969 if (!fixp
->fx_pcrel
)
11971 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
11972 code
= fixp
->fx_r_type
;
11975 /* Fall through. */
11977 if (fixp
->fx_pcrel
)
11979 switch (fixp
->fx_size
)
11982 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
11983 _("can not do %d byte pc-relative relocation"),
11985 code
= BFD_RELOC_32_PCREL
;
11987 case 1: code
= BFD_RELOC_8_PCREL
; break;
11988 case 2: code
= BFD_RELOC_16_PCREL
; break;
11989 case 4: code
= BFD_RELOC_32_PCREL
; break;
11991 case 8: code
= BFD_RELOC_64_PCREL
; break;
11997 switch (fixp
->fx_size
)
12000 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
12001 _("can not do %d byte relocation"),
12003 code
= BFD_RELOC_32
;
12005 case 1: code
= BFD_RELOC_8
; break;
12006 case 2: code
= BFD_RELOC_16
; break;
12007 case 4: code
= BFD_RELOC_32
; break;
12009 case 8: code
= BFD_RELOC_64
; break;
12016 if ((code
== BFD_RELOC_32
12017 || code
== BFD_RELOC_32_PCREL
12018 || code
== BFD_RELOC_X86_64_32S
)
12020 && fixp
->fx_addsy
== GOT_symbol
)
12023 code
= BFD_RELOC_386_GOTPC
;
12025 code
= BFD_RELOC_X86_64_GOTPC32
;
12027 if ((code
== BFD_RELOC_64
|| code
== BFD_RELOC_64_PCREL
)
12029 && fixp
->fx_addsy
== GOT_symbol
)
12031 code
= BFD_RELOC_X86_64_GOTPC64
;
12034 rel
= XNEW (arelent
);
12035 rel
->sym_ptr_ptr
= XNEW (asymbol
*);
12036 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
12038 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
12040 if (!use_rela_relocations
)
12042 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
12043 vtable entry to be used in the relocation's section offset. */
12044 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
12045 rel
->address
= fixp
->fx_offset
;
12046 #if defined (OBJ_COFF) && defined (TE_PE)
12047 else if (fixp
->fx_addsy
&& S_IS_WEAK (fixp
->fx_addsy
))
12048 rel
->addend
= fixp
->fx_addnumber
- (S_GET_VALUE (fixp
->fx_addsy
) * 2);
12053 /* Use the rela in 64bit mode. */
12056 if (disallow_64bit_reloc
)
12059 case BFD_RELOC_X86_64_DTPOFF64
:
12060 case BFD_RELOC_X86_64_TPOFF64
:
12061 case BFD_RELOC_64_PCREL
:
12062 case BFD_RELOC_X86_64_GOTOFF64
:
12063 case BFD_RELOC_X86_64_GOT64
:
12064 case BFD_RELOC_X86_64_GOTPCREL64
:
12065 case BFD_RELOC_X86_64_GOTPC64
:
12066 case BFD_RELOC_X86_64_GOTPLT64
:
12067 case BFD_RELOC_X86_64_PLTOFF64
:
12068 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
12069 _("cannot represent relocation type %s in x32 mode"),
12070 bfd_get_reloc_code_name (code
));
12076 if (!fixp
->fx_pcrel
)
12077 rel
->addend
= fixp
->fx_offset
;
12081 case BFD_RELOC_X86_64_PLT32
:
12082 case BFD_RELOC_X86_64_GOT32
:
12083 case BFD_RELOC_X86_64_GOTPCREL
:
12084 case BFD_RELOC_X86_64_GOTPCRELX
:
12085 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
12086 case BFD_RELOC_X86_64_TLSGD
:
12087 case BFD_RELOC_X86_64_TLSLD
:
12088 case BFD_RELOC_X86_64_GOTTPOFF
:
12089 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
12090 case BFD_RELOC_X86_64_TLSDESC_CALL
:
12091 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
12094 rel
->addend
= (section
->vma
12096 + fixp
->fx_addnumber
12097 + md_pcrel_from (fixp
));
12102 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
12103 if (rel
->howto
== NULL
)
12105 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
12106 _("cannot represent relocation type %s"),
12107 bfd_get_reloc_code_name (code
));
12108 /* Set howto to a garbage value so that we can keep going. */
12109 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
12110 gas_assert (rel
->howto
!= NULL
);
12116 #include "tc-i386-intel.c"
12119 tc_x86_parse_to_dw2regnum (expressionS
*exp
)
12121 int saved_naked_reg
;
12122 char saved_register_dot
;
12124 saved_naked_reg
= allow_naked_reg
;
12125 allow_naked_reg
= 1;
12126 saved_register_dot
= register_chars
['.'];
12127 register_chars
['.'] = '.';
12128 allow_pseudo_reg
= 1;
12129 expression_and_evaluate (exp
);
12130 allow_pseudo_reg
= 0;
12131 register_chars
['.'] = saved_register_dot
;
12132 allow_naked_reg
= saved_naked_reg
;
12134 if (exp
->X_op
== O_register
&& exp
->X_add_number
>= 0)
12136 if ((addressT
) exp
->X_add_number
< i386_regtab_size
)
12138 exp
->X_op
= O_constant
;
12139 exp
->X_add_number
= i386_regtab
[exp
->X_add_number
]
12140 .dw2_regnum
[flag_code
>> 1];
12143 exp
->X_op
= O_illegal
;
12148 tc_x86_frame_initial_instructions (void)
12150 static unsigned int sp_regno
[2];
12152 if (!sp_regno
[flag_code
>> 1])
12154 char *saved_input
= input_line_pointer
;
12155 char sp
[][4] = {"esp", "rsp"};
12158 input_line_pointer
= sp
[flag_code
>> 1];
12159 tc_x86_parse_to_dw2regnum (&exp
);
12160 gas_assert (exp
.X_op
== O_constant
);
12161 sp_regno
[flag_code
>> 1] = exp
.X_add_number
;
12162 input_line_pointer
= saved_input
;
12165 cfi_add_CFA_def_cfa (sp_regno
[flag_code
>> 1], -x86_cie_data_alignment
);
12166 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
12170 x86_dwarf2_addr_size (void)
12172 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
12173 if (x86_elf_abi
== X86_64_X32_ABI
)
12176 return bfd_arch_bits_per_address (stdoutput
) / 8;
12180 i386_elf_section_type (const char *str
, size_t len
)
12182 if (flag_code
== CODE_64BIT
12183 && len
== sizeof ("unwind") - 1
12184 && strncmp (str
, "unwind", 6) == 0)
12185 return SHT_X86_64_UNWIND
;
12192 i386_solaris_fix_up_eh_frame (segT sec
)
12194 if (flag_code
== CODE_64BIT
)
12195 elf_section_type (sec
) = SHT_X86_64_UNWIND
;
12201 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
12205 exp
.X_op
= O_secrel
;
12206 exp
.X_add_symbol
= symbol
;
12207 exp
.X_add_number
= 0;
12208 emit_expr (&exp
, size
);
12212 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12213 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
12216 x86_64_section_letter (int letter
, const char **ptr_msg
)
12218 if (flag_code
== CODE_64BIT
)
12221 return SHF_X86_64_LARGE
;
12223 *ptr_msg
= _("bad .section directive: want a,l,w,x,M,S,G,T in string");
12226 *ptr_msg
= _("bad .section directive: want a,w,x,M,S,G,T in string");
12231 x86_64_section_word (char *str
, size_t len
)
12233 if (len
== 5 && flag_code
== CODE_64BIT
&& CONST_STRNEQ (str
, "large"))
12234 return SHF_X86_64_LARGE
;
12240 handle_large_common (int small ATTRIBUTE_UNUSED
)
12242 if (flag_code
!= CODE_64BIT
)
12244 s_comm_internal (0, elf_common_parse
);
12245 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
12249 static segT lbss_section
;
12250 asection
*saved_com_section_ptr
= elf_com_section_ptr
;
12251 asection
*saved_bss_section
= bss_section
;
12253 if (lbss_section
== NULL
)
12255 flagword applicable
;
12256 segT seg
= now_seg
;
12257 subsegT subseg
= now_subseg
;
12259 /* The .lbss section is for local .largecomm symbols. */
12260 lbss_section
= subseg_new (".lbss", 0);
12261 applicable
= bfd_applicable_section_flags (stdoutput
);
12262 bfd_set_section_flags (stdoutput
, lbss_section
,
12263 applicable
& SEC_ALLOC
);
12264 seg_info (lbss_section
)->bss
= 1;
12266 subseg_set (seg
, subseg
);
12269 elf_com_section_ptr
= &_bfd_elf_large_com_section
;
12270 bss_section
= lbss_section
;
12272 s_comm_internal (0, elf_common_parse
);
12274 elf_com_section_ptr
= saved_com_section_ptr
;
12275 bss_section
= saved_bss_section
;
12278 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */