1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright (C) 1989-2014 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 /* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
23 x86_64 support by Jan Hubicka (jh@suse.cz)
24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
29 #include "safe-ctype.h"
31 #include "dwarf2dbg.h"
32 #include "dw2gencfi.h"
33 #include "elf/x86-64.h"
34 #include "opcodes/i386-init.h"
36 #ifndef REGISTER_WARNINGS
37 #define REGISTER_WARNINGS 1
40 #ifndef INFER_ADDR_PREFIX
41 #define INFER_ADDR_PREFIX 1
45 #define DEFAULT_ARCH "i386"
50 #define INLINE __inline__
56 /* Prefixes will be emitted in the order defined below.
57 WAIT_PREFIX must be the first prefix since FWAIT is really is an
58 instruction, and so must come before any prefixes.
59 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
60 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
66 #define HLE_PREFIX REP_PREFIX
67 #define BND_PREFIX REP_PREFIX
69 #define REX_PREFIX 6 /* must come last. */
70 #define MAX_PREFIXES 7 /* max prefixes per opcode */
72 /* we define the syntax here (modulo base,index,scale syntax) */
73 #define REGISTER_PREFIX '%'
74 #define IMMEDIATE_PREFIX '$'
75 #define ABSOLUTE_PREFIX '*'
77 /* these are the instruction mnemonic suffixes in AT&T syntax or
78 memory operand size in Intel syntax. */
79 #define WORD_MNEM_SUFFIX 'w'
80 #define BYTE_MNEM_SUFFIX 'b'
81 #define SHORT_MNEM_SUFFIX 's'
82 #define LONG_MNEM_SUFFIX 'l'
83 #define QWORD_MNEM_SUFFIX 'q'
84 #define XMMWORD_MNEM_SUFFIX 'x'
85 #define YMMWORD_MNEM_SUFFIX 'y'
86 #define ZMMWORD_MNEM_SUFFIX 'z'
87 /* Intel Syntax. Use a non-ascii letter since since it never appears
89 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
91 #define END_OF_INSN '\0'
94 'templates' is for grouping together 'template' structures for opcodes
95 of the same name. This is only used for storing the insns in the grand
96 ole hash table of insns.
97 The templates themselves start at START and range up to (but not including)
102 const insn_template
*start
;
103 const insn_template
*end
;
107 /* 386 operand encoding bytes: see 386 book for details of this. */
110 unsigned int regmem
; /* codes register or memory operand */
111 unsigned int reg
; /* codes register operand (or extended opcode) */
112 unsigned int mode
; /* how to interpret regmem & reg */
116 /* x86-64 extension prefix. */
117 typedef int rex_byte
;
119 /* 386 opcode byte to code indirect addressing. */
128 /* x86 arch names, types and features */
131 const char *name
; /* arch name */
132 unsigned int len
; /* arch string length */
133 enum processor_type type
; /* arch type */
134 i386_cpu_flags flags
; /* cpu feature flags */
135 unsigned int skip
; /* show_arch should skip this. */
136 unsigned int negated
; /* turn off indicated flags. */
140 static void update_code_flag (int, int);
141 static void set_code_flag (int);
142 static void set_16bit_gcc_code_flag (int);
143 static void set_intel_syntax (int);
144 static void set_intel_mnemonic (int);
145 static void set_allow_index_reg (int);
146 static void set_check (int);
147 static void set_cpu_arch (int);
149 static void pe_directive_secrel (int);
151 static void signed_cons (int);
152 static char *output_invalid (int c
);
153 static int i386_finalize_immediate (segT
, expressionS
*, i386_operand_type
,
155 static int i386_finalize_displacement (segT
, expressionS
*, i386_operand_type
,
157 static int i386_att_operand (char *);
158 static int i386_intel_operand (char *, int);
159 static int i386_intel_simplify (expressionS
*);
160 static int i386_intel_parse_name (const char *, expressionS
*);
161 static const reg_entry
*parse_register (char *, char **);
162 static char *parse_insn (char *, char *);
163 static char *parse_operands (char *, const char *);
164 static void swap_operands (void);
165 static void swap_2_operands (int, int);
166 static void optimize_imm (void);
167 static void optimize_disp (void);
168 static const insn_template
*match_template (void);
169 static int check_string (void);
170 static int process_suffix (void);
171 static int check_byte_reg (void);
172 static int check_long_reg (void);
173 static int check_qword_reg (void);
174 static int check_word_reg (void);
175 static int finalize_imm (void);
176 static int process_operands (void);
177 static const seg_entry
*build_modrm_byte (void);
178 static void output_insn (void);
179 static void output_imm (fragS
*, offsetT
);
180 static void output_disp (fragS
*, offsetT
);
182 static void s_bss (int);
184 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
185 static void handle_large_common (int small ATTRIBUTE_UNUSED
);
188 static const char *default_arch
= DEFAULT_ARCH
;
190 /* This struct describes rounding control and SAE in the instruction. */
204 static struct RC_Operation rc_op
;
206 /* The struct describes masking, applied to OPERAND in the instruction.
207 MASK is a pointer to the corresponding mask register. ZEROING tells
208 whether merging or zeroing mask is used. */
209 struct Mask_Operation
211 const reg_entry
*mask
;
212 unsigned int zeroing
;
213 /* The operand where this operation is associated. */
217 static struct Mask_Operation mask_op
;
219 /* The struct describes broadcasting, applied to OPERAND. FACTOR is
221 struct Broadcast_Operation
223 /* Type of broadcast: no broadcast, {1to8}, or {1to16}. */
226 /* Index of broadcasted operand. */
230 static struct Broadcast_Operation broadcast_op
;
235 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
236 unsigned char bytes
[4];
238 /* Destination or source register specifier. */
239 const reg_entry
*register_specifier
;
242 /* 'md_assemble ()' gathers together information and puts it into a
249 const reg_entry
*regs
;
254 operand_size_mismatch
,
255 operand_type_mismatch
,
256 register_type_mismatch
,
257 number_of_operands_mismatch
,
258 invalid_instruction_suffix
,
261 unsupported_with_intel_mnemonic
,
264 invalid_vsib_address
,
265 invalid_vector_register_set
,
266 unsupported_vector_index_register
,
267 unsupported_broadcast
,
268 broadcast_not_on_src_operand
,
271 mask_not_on_destination
,
274 rc_sae_operand_not_last_imm
,
275 invalid_register_operand
,
281 /* TM holds the template for the insn were currently assembling. */
284 /* SUFFIX holds the instruction size suffix for byte, word, dword
285 or qword, if given. */
288 /* OPERANDS gives the number of given operands. */
289 unsigned int operands
;
291 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
292 of given register, displacement, memory operands and immediate
294 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
296 /* TYPES [i] is the type (see above #defines) which tells us how to
297 use OP[i] for the corresponding operand. */
298 i386_operand_type types
[MAX_OPERANDS
];
300 /* Displacement expression, immediate expression, or register for each
302 union i386_op op
[MAX_OPERANDS
];
304 /* Flags for operands. */
305 unsigned int flags
[MAX_OPERANDS
];
306 #define Operand_PCrel 1
308 /* Relocation type for operand */
309 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
311 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
312 the base index byte below. */
313 const reg_entry
*base_reg
;
314 const reg_entry
*index_reg
;
315 unsigned int log2_scale_factor
;
317 /* SEG gives the seg_entries of this insn. They are zero unless
318 explicit segment overrides are given. */
319 const seg_entry
*seg
[2];
321 /* PREFIX holds all the given prefix opcodes (usually null).
322 PREFIXES is the number of prefix opcodes. */
323 unsigned int prefixes
;
324 unsigned char prefix
[MAX_PREFIXES
];
326 /* RM and SIB are the modrm byte and the sib byte where the
327 addressing modes of this insn are encoded. */
334 /* Masking attributes. */
335 struct Mask_Operation
*mask
;
337 /* Rounding control and SAE attributes. */
338 struct RC_Operation
*rounding
;
340 /* Broadcasting attributes. */
341 struct Broadcast_Operation
*broadcast
;
343 /* Compressed disp8*N attribute. */
344 unsigned int memshift
;
346 /* Swap operand in encoding. */
347 unsigned int swap_operand
;
349 /* Prefer 8bit or 32bit displacement in encoding. */
352 disp_encoding_default
= 0,
358 const char *rep_prefix
;
361 const char *hle_prefix
;
363 /* Have BND prefix. */
364 const char *bnd_prefix
;
366 /* Need VREX to support upper 16 registers. */
370 enum i386_error error
;
373 typedef struct _i386_insn i386_insn
;
375 /* Link RC type with corresponding string, that'll be looked for in
384 static const struct RC_name RC_NamesTable
[] =
386 { rne
, STRING_COMMA_LEN ("rn-sae") },
387 { rd
, STRING_COMMA_LEN ("rd-sae") },
388 { ru
, STRING_COMMA_LEN ("ru-sae") },
389 { rz
, STRING_COMMA_LEN ("rz-sae") },
390 { saeonly
, STRING_COMMA_LEN ("sae") },
393 /* List of chars besides those in app.c:symbol_chars that can start an
394 operand. Used to prevent the scrubber eating vital white-space. */
395 const char extra_symbol_chars
[] = "*%-([{"
404 #if (defined (TE_I386AIX) \
405 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
406 && !defined (TE_GNU) \
407 && !defined (TE_LINUX) \
408 && !defined (TE_NACL) \
409 && !defined (TE_NETWARE) \
410 && !defined (TE_FreeBSD) \
411 && !defined (TE_DragonFly) \
412 && !defined (TE_NetBSD)))
413 /* This array holds the chars that always start a comment. If the
414 pre-processor is disabled, these aren't very useful. The option
415 --divide will remove '/' from this list. */
416 const char *i386_comment_chars
= "#/";
417 #define SVR4_COMMENT_CHARS 1
418 #define PREFIX_SEPARATOR '\\'
421 const char *i386_comment_chars
= "#";
422 #define PREFIX_SEPARATOR '/'
425 /* This array holds the chars that only start a comment at the beginning of
426 a line. If the line seems to have the form '# 123 filename'
427 .line and .file directives will appear in the pre-processed output.
428 Note that input_file.c hand checks for '#' at the beginning of the
429 first line of the input file. This is because the compiler outputs
430 #NO_APP at the beginning of its output.
431 Also note that comments started like this one will always work if
432 '/' isn't otherwise defined. */
433 const char line_comment_chars
[] = "#/";
435 const char line_separator_chars
[] = ";";
437 /* Chars that can be used to separate mant from exp in floating point
439 const char EXP_CHARS
[] = "eE";
441 /* Chars that mean this number is a floating point constant
444 const char FLT_CHARS
[] = "fFdDxX";
446 /* Tables for lexical analysis. */
447 static char mnemonic_chars
[256];
448 static char register_chars
[256];
449 static char operand_chars
[256];
450 static char identifier_chars
[256];
451 static char digit_chars
[256];
453 /* Lexical macros. */
454 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
455 #define is_operand_char(x) (operand_chars[(unsigned char) x])
456 #define is_register_char(x) (register_chars[(unsigned char) x])
457 #define is_space_char(x) ((x) == ' ')
458 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
459 #define is_digit_char(x) (digit_chars[(unsigned char) x])
461 /* All non-digit non-letter characters that may occur in an operand. */
462 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
464 /* md_assemble() always leaves the strings it's passed unaltered. To
465 effect this we maintain a stack of saved characters that we've smashed
466 with '\0's (indicating end of strings for various sub-fields of the
467 assembler instruction). */
468 static char save_stack
[32];
469 static char *save_stack_p
;
470 #define END_STRING_AND_SAVE(s) \
471 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
472 #define RESTORE_END_STRING(s) \
473 do { *(s) = *--save_stack_p; } while (0)
475 /* The instruction we're assembling. */
478 /* Possible templates for current insn. */
479 static const templates
*current_templates
;
481 /* Per instruction expressionS buffers: max displacements & immediates. */
482 static expressionS disp_expressions
[MAX_MEMORY_OPERANDS
];
483 static expressionS im_expressions
[MAX_IMMEDIATE_OPERANDS
];
485 /* Current operand we are working on. */
486 static int this_operand
= -1;
488 /* We support four different modes. FLAG_CODE variable is used to distinguish
496 static enum flag_code flag_code
;
497 static unsigned int object_64bit
;
498 static unsigned int disallow_64bit_reloc
;
499 static int use_rela_relocations
= 0;
501 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
502 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
503 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
505 /* The ELF ABI to use. */
513 static enum x86_elf_abi x86_elf_abi
= I386_ABI
;
516 #if defined (TE_PE) || defined (TE_PEP)
517 /* Use big object file format. */
518 static int use_big_obj
= 0;
521 /* 1 for intel syntax,
523 static int intel_syntax
= 0;
525 /* 1 for intel mnemonic,
526 0 if att mnemonic. */
527 static int intel_mnemonic
= !SYSV386_COMPAT
;
529 /* 1 if support old (<= 2.8.1) versions of gcc. */
530 static int old_gcc
= OLDGCC_COMPAT
;
532 /* 1 if pseudo registers are permitted. */
533 static int allow_pseudo_reg
= 0;
535 /* 1 if register prefix % not required. */
536 static int allow_naked_reg
= 0;
538 /* 1 if the assembler should add BND prefix for all control-tranferring
539 instructions supporting it, even if this prefix wasn't specified
541 static int add_bnd_prefix
= 0;
543 /* 1 if pseudo index register, eiz/riz, is allowed . */
544 static int allow_index_reg
= 0;
546 /* 1 if the assembler should ignore LOCK prefix, even if it was
547 specified explicitly. */
548 static int omit_lock_prefix
= 0;
550 static enum check_kind
556 sse_check
, operand_check
= check_warning
;
558 /* Register prefix used for error message. */
559 static const char *register_prefix
= "%";
561 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
562 leave, push, and pop instructions so that gcc has the same stack
563 frame as in 32 bit mode. */
564 static char stackop_size
= '\0';
566 /* Non-zero to optimize code alignment. */
567 int optimize_align_code
= 1;
569 /* Non-zero to quieten some warnings. */
570 static int quiet_warnings
= 0;
573 static const char *cpu_arch_name
= NULL
;
574 static char *cpu_sub_arch_name
= NULL
;
576 /* CPU feature flags. */
577 static i386_cpu_flags cpu_arch_flags
= CPU_UNKNOWN_FLAGS
;
579 /* If we have selected a cpu we are generating instructions for. */
580 static int cpu_arch_tune_set
= 0;
582 /* Cpu we are generating instructions for. */
583 enum processor_type cpu_arch_tune
= PROCESSOR_UNKNOWN
;
585 /* CPU feature flags of cpu we are generating instructions for. */
586 static i386_cpu_flags cpu_arch_tune_flags
;
588 /* CPU instruction set architecture used. */
589 enum processor_type cpu_arch_isa
= PROCESSOR_UNKNOWN
;
591 /* CPU feature flags of instruction set architecture used. */
592 i386_cpu_flags cpu_arch_isa_flags
;
594 /* If set, conditional jumps are not automatically promoted to handle
595 larger than a byte offset. */
596 static unsigned int no_cond_jump_promotion
= 0;
598 /* Encode SSE instructions with VEX prefix. */
599 static unsigned int sse2avx
;
601 /* Encode scalar AVX instructions with specific vector length. */
608 /* Encode scalar EVEX LIG instructions with specific vector length. */
616 /* Encode EVEX WIG instructions with specific evex.w. */
623 /* Value to encode in EVEX RC bits, for SAE-only instructions. */
624 static enum rc_type evexrcig
= rne
;
626 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
627 static symbolS
*GOT_symbol
;
629 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
630 unsigned int x86_dwarf2_return_column
;
632 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
633 int x86_cie_data_alignment
;
635 /* Interface to relax_segment.
636 There are 3 major relax states for 386 jump insns because the
637 different types of jumps add different sizes to frags when we're
638 figuring out what sort of jump to choose to reach a given label. */
641 #define UNCOND_JUMP 0
643 #define COND_JUMP86 2
648 #define SMALL16 (SMALL | CODE16)
650 #define BIG16 (BIG | CODE16)
654 #define INLINE __inline__
660 #define ENCODE_RELAX_STATE(type, size) \
661 ((relax_substateT) (((type) << 2) | (size)))
662 #define TYPE_FROM_RELAX_STATE(s) \
664 #define DISP_SIZE_FROM_RELAX_STATE(s) \
665 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
667 /* This table is used by relax_frag to promote short jumps to long
668 ones where necessary. SMALL (short) jumps may be promoted to BIG
669 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
670 don't allow a short jump in a 32 bit code segment to be promoted to
671 a 16 bit offset jump because it's slower (requires data size
672 prefix), and doesn't work, unless the destination is in the bottom
673 64k of the code segment (The top 16 bits of eip are zeroed). */
675 const relax_typeS md_relax_table
[] =
678 1) most positive reach of this state,
679 2) most negative reach of this state,
680 3) how many bytes this mode will have in the variable part of the frag
681 4) which index into the table to try if we can't fit into this one. */
683 /* UNCOND_JUMP states. */
684 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
685 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
686 /* dword jmp adds 4 bytes to frag:
687 0 extra opcode bytes, 4 displacement bytes. */
689 /* word jmp adds 2 byte2 to frag:
690 0 extra opcode bytes, 2 displacement bytes. */
693 /* COND_JUMP states. */
694 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
695 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
696 /* dword conditionals adds 5 bytes to frag:
697 1 extra opcode byte, 4 displacement bytes. */
699 /* word conditionals add 3 bytes to frag:
700 1 extra opcode byte, 2 displacement bytes. */
703 /* COND_JUMP86 states. */
704 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
705 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
706 /* dword conditionals adds 5 bytes to frag:
707 1 extra opcode byte, 4 displacement bytes. */
709 /* word conditionals add 4 bytes to frag:
710 1 displacement byte and a 3 byte long branch insn. */
714 static const arch_entry cpu_arch
[] =
716 /* Do not replace the first two entries - i386_target_format()
717 relies on them being there in this order. */
718 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32
,
719 CPU_GENERIC32_FLAGS
, 0, 0 },
720 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64
,
721 CPU_GENERIC64_FLAGS
, 0, 0 },
722 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN
,
723 CPU_NONE_FLAGS
, 0, 0 },
724 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN
,
725 CPU_I186_FLAGS
, 0, 0 },
726 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN
,
727 CPU_I286_FLAGS
, 0, 0 },
728 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386
,
729 CPU_I386_FLAGS
, 0, 0 },
730 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486
,
731 CPU_I486_FLAGS
, 0, 0 },
732 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM
,
733 CPU_I586_FLAGS
, 0, 0 },
734 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO
,
735 CPU_I686_FLAGS
, 0, 0 },
736 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM
,
737 CPU_I586_FLAGS
, 0, 0 },
738 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO
,
739 CPU_PENTIUMPRO_FLAGS
, 0, 0 },
740 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO
,
741 CPU_P2_FLAGS
, 0, 0 },
742 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO
,
743 CPU_P3_FLAGS
, 0, 0 },
744 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4
,
745 CPU_P4_FLAGS
, 0, 0 },
746 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA
,
747 CPU_CORE_FLAGS
, 0, 0 },
748 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA
,
749 CPU_NOCONA_FLAGS
, 0, 0 },
750 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE
,
751 CPU_CORE_FLAGS
, 1, 0 },
752 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE
,
753 CPU_CORE_FLAGS
, 0, 0 },
754 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2
,
755 CPU_CORE2_FLAGS
, 1, 0 },
756 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2
,
757 CPU_CORE2_FLAGS
, 0, 0 },
758 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7
,
759 CPU_COREI7_FLAGS
, 0, 0 },
760 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM
,
761 CPU_L1OM_FLAGS
, 0, 0 },
762 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM
,
763 CPU_K1OM_FLAGS
, 0, 0 },
764 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6
,
765 CPU_K6_FLAGS
, 0, 0 },
766 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6
,
767 CPU_K6_2_FLAGS
, 0, 0 },
768 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON
,
769 CPU_ATHLON_FLAGS
, 0, 0 },
770 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8
,
771 CPU_K8_FLAGS
, 1, 0 },
772 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8
,
773 CPU_K8_FLAGS
, 0, 0 },
774 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8
,
775 CPU_K8_FLAGS
, 0, 0 },
776 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10
,
777 CPU_AMDFAM10_FLAGS
, 0, 0 },
778 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD
,
779 CPU_BDVER1_FLAGS
, 0, 0 },
780 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD
,
781 CPU_BDVER2_FLAGS
, 0, 0 },
782 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD
,
783 CPU_BDVER3_FLAGS
, 0, 0 },
784 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD
,
785 CPU_BDVER4_FLAGS
, 0, 0 },
786 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT
,
787 CPU_BTVER1_FLAGS
, 0, 0 },
788 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT
,
789 CPU_BTVER2_FLAGS
, 0, 0 },
790 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN
,
791 CPU_8087_FLAGS
, 0, 0 },
792 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN
,
793 CPU_287_FLAGS
, 0, 0 },
794 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN
,
795 CPU_387_FLAGS
, 0, 0 },
796 { STRING_COMMA_LEN (".no87"), PROCESSOR_UNKNOWN
,
797 CPU_ANY87_FLAGS
, 0, 1 },
798 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN
,
799 CPU_MMX_FLAGS
, 0, 0 },
800 { STRING_COMMA_LEN (".nommx"), PROCESSOR_UNKNOWN
,
801 CPU_3DNOWA_FLAGS
, 0, 1 },
802 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN
,
803 CPU_SSE_FLAGS
, 0, 0 },
804 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN
,
805 CPU_SSE2_FLAGS
, 0, 0 },
806 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN
,
807 CPU_SSE3_FLAGS
, 0, 0 },
808 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN
,
809 CPU_SSSE3_FLAGS
, 0, 0 },
810 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN
,
811 CPU_SSE4_1_FLAGS
, 0, 0 },
812 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN
,
813 CPU_SSE4_2_FLAGS
, 0, 0 },
814 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN
,
815 CPU_SSE4_2_FLAGS
, 0, 0 },
816 { STRING_COMMA_LEN (".nosse"), PROCESSOR_UNKNOWN
,
817 CPU_ANY_SSE_FLAGS
, 0, 1 },
818 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN
,
819 CPU_AVX_FLAGS
, 0, 0 },
820 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN
,
821 CPU_AVX2_FLAGS
, 0, 0 },
822 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN
,
823 CPU_AVX512F_FLAGS
, 0, 0 },
824 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN
,
825 CPU_AVX512CD_FLAGS
, 0, 0 },
826 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN
,
827 CPU_AVX512ER_FLAGS
, 0, 0 },
828 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN
,
829 CPU_AVX512PF_FLAGS
, 0, 0 },
830 { STRING_COMMA_LEN (".noavx"), PROCESSOR_UNKNOWN
,
831 CPU_ANY_AVX_FLAGS
, 0, 1 },
832 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN
,
833 CPU_VMX_FLAGS
, 0, 0 },
834 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN
,
835 CPU_VMFUNC_FLAGS
, 0, 0 },
836 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN
,
837 CPU_SMX_FLAGS
, 0, 0 },
838 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN
,
839 CPU_XSAVE_FLAGS
, 0, 0 },
840 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN
,
841 CPU_XSAVEOPT_FLAGS
, 0, 0 },
842 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN
,
843 CPU_AES_FLAGS
, 0, 0 },
844 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN
,
845 CPU_PCLMUL_FLAGS
, 0, 0 },
846 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN
,
847 CPU_PCLMUL_FLAGS
, 1, 0 },
848 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN
,
849 CPU_FSGSBASE_FLAGS
, 0, 0 },
850 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN
,
851 CPU_RDRND_FLAGS
, 0, 0 },
852 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN
,
853 CPU_F16C_FLAGS
, 0, 0 },
854 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN
,
855 CPU_BMI2_FLAGS
, 0, 0 },
856 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN
,
857 CPU_FMA_FLAGS
, 0, 0 },
858 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN
,
859 CPU_FMA4_FLAGS
, 0, 0 },
860 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN
,
861 CPU_XOP_FLAGS
, 0, 0 },
862 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN
,
863 CPU_LWP_FLAGS
, 0, 0 },
864 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN
,
865 CPU_MOVBE_FLAGS
, 0, 0 },
866 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN
,
867 CPU_CX16_FLAGS
, 0, 0 },
868 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN
,
869 CPU_EPT_FLAGS
, 0, 0 },
870 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN
,
871 CPU_LZCNT_FLAGS
, 0, 0 },
872 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN
,
873 CPU_HLE_FLAGS
, 0, 0 },
874 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN
,
875 CPU_RTM_FLAGS
, 0, 0 },
876 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN
,
877 CPU_INVPCID_FLAGS
, 0, 0 },
878 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN
,
879 CPU_CLFLUSH_FLAGS
, 0, 0 },
880 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN
,
881 CPU_NOP_FLAGS
, 0, 0 },
882 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN
,
883 CPU_SYSCALL_FLAGS
, 0, 0 },
884 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN
,
885 CPU_RDTSCP_FLAGS
, 0, 0 },
886 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN
,
887 CPU_3DNOW_FLAGS
, 0, 0 },
888 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN
,
889 CPU_3DNOWA_FLAGS
, 0, 0 },
890 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN
,
891 CPU_PADLOCK_FLAGS
, 0, 0 },
892 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN
,
893 CPU_SVME_FLAGS
, 1, 0 },
894 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN
,
895 CPU_SVME_FLAGS
, 0, 0 },
896 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN
,
897 CPU_SSE4A_FLAGS
, 0, 0 },
898 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN
,
899 CPU_ABM_FLAGS
, 0, 0 },
900 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN
,
901 CPU_BMI_FLAGS
, 0, 0 },
902 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN
,
903 CPU_TBM_FLAGS
, 0, 0 },
904 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN
,
905 CPU_ADX_FLAGS
, 0, 0 },
906 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN
,
907 CPU_RDSEED_FLAGS
, 0, 0 },
908 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN
,
909 CPU_PRFCHW_FLAGS
, 0, 0 },
910 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN
,
911 CPU_SMAP_FLAGS
, 0, 0 },
912 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN
,
913 CPU_MPX_FLAGS
, 0, 0 },
914 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN
,
915 CPU_SHA_FLAGS
, 0, 0 },
916 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN
,
917 CPU_CLFLUSHOPT_FLAGS
, 0, 0 },
918 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN
,
919 CPU_XSAVEC_FLAGS
, 0, 0 },
920 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN
,
921 CPU_XSAVES_FLAGS
, 0, 0 },
922 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN
,
923 CPU_PREFETCHWT1_FLAGS
, 0, 0 },
924 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN
,
925 CPU_SE1_FLAGS
, 0, 0 },
926 { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN
,
927 CPU_AVX512DQ_FLAGS
, 0, 0 },
928 { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN
,
929 CPU_AVX512BW_FLAGS
, 0, 0 },
930 { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN
,
931 CPU_AVX512VL_FLAGS
, 0, 0 },
935 /* Like s_lcomm_internal in gas/read.c but the alignment string
936 is allowed to be optional. */
939 pe_lcomm_internal (int needs_align
, symbolS
*symbolP
, addressT size
)
946 && *input_line_pointer
== ',')
948 align
= parse_align (needs_align
- 1);
950 if (align
== (addressT
) -1)
965 bss_alloc (symbolP
, size
, align
);
970 pe_lcomm (int needs_align
)
972 s_comm_internal (needs_align
* 2, pe_lcomm_internal
);
976 const pseudo_typeS md_pseudo_table
[] =
978 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
979 {"align", s_align_bytes
, 0},
981 {"align", s_align_ptwo
, 0},
983 {"arch", set_cpu_arch
, 0},
987 {"lcomm", pe_lcomm
, 1},
989 {"ffloat", float_cons
, 'f'},
990 {"dfloat", float_cons
, 'd'},
991 {"tfloat", float_cons
, 'x'},
993 {"slong", signed_cons
, 4},
994 {"noopt", s_ignore
, 0},
995 {"optim", s_ignore
, 0},
996 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
997 {"code16", set_code_flag
, CODE_16BIT
},
998 {"code32", set_code_flag
, CODE_32BIT
},
999 {"code64", set_code_flag
, CODE_64BIT
},
1000 {"intel_syntax", set_intel_syntax
, 1},
1001 {"att_syntax", set_intel_syntax
, 0},
1002 {"intel_mnemonic", set_intel_mnemonic
, 1},
1003 {"att_mnemonic", set_intel_mnemonic
, 0},
1004 {"allow_index_reg", set_allow_index_reg
, 1},
1005 {"disallow_index_reg", set_allow_index_reg
, 0},
1006 {"sse_check", set_check
, 0},
1007 {"operand_check", set_check
, 1},
1008 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1009 {"largecomm", handle_large_common
, 0},
1011 {"file", (void (*) (int)) dwarf2_directive_file
, 0},
1012 {"loc", dwarf2_directive_loc
, 0},
1013 {"loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0},
1016 {"secrel32", pe_directive_secrel
, 0},
1021 /* For interface with expression (). */
1022 extern char *input_line_pointer
;
1024 /* Hash table for instruction mnemonic lookup. */
1025 static struct hash_control
*op_hash
;
1027 /* Hash table for register lookup. */
1028 static struct hash_control
*reg_hash
;
1031 i386_align_code (fragS
*fragP
, int count
)
1033 /* Various efficient no-op patterns for aligning code labels.
1034 Note: Don't try to assemble the instructions in the comments.
1035 0L and 0w are not legal. */
1036 static const char f32_1
[] =
1038 static const char f32_2
[] =
1039 {0x66,0x90}; /* xchg %ax,%ax */
1040 static const char f32_3
[] =
1041 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1042 static const char f32_4
[] =
1043 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1044 static const char f32_5
[] =
1046 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1047 static const char f32_6
[] =
1048 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1049 static const char f32_7
[] =
1050 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1051 static const char f32_8
[] =
1053 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1054 static const char f32_9
[] =
1055 {0x89,0xf6, /* movl %esi,%esi */
1056 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1057 static const char f32_10
[] =
1058 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
1059 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1060 static const char f32_11
[] =
1061 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
1062 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1063 static const char f32_12
[] =
1064 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1065 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
1066 static const char f32_13
[] =
1067 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1068 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1069 static const char f32_14
[] =
1070 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
1071 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1072 static const char f16_3
[] =
1073 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
1074 static const char f16_4
[] =
1075 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
1076 static const char f16_5
[] =
1078 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
1079 static const char f16_6
[] =
1080 {0x89,0xf6, /* mov %si,%si */
1081 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1082 static const char f16_7
[] =
1083 {0x8d,0x74,0x00, /* lea 0(%si),%si */
1084 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1085 static const char f16_8
[] =
1086 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
1087 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1088 static const char jump_31
[] =
1089 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
1090 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1091 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1092 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
1093 static const char *const f32_patt
[] = {
1094 f32_1
, f32_2
, f32_3
, f32_4
, f32_5
, f32_6
, f32_7
, f32_8
,
1095 f32_9
, f32_10
, f32_11
, f32_12
, f32_13
, f32_14
1097 static const char *const f16_patt
[] = {
1098 f32_1
, f32_2
, f16_3
, f16_4
, f16_5
, f16_6
, f16_7
, f16_8
1100 /* nopl (%[re]ax) */
1101 static const char alt_3
[] =
1103 /* nopl 0(%[re]ax) */
1104 static const char alt_4
[] =
1105 {0x0f,0x1f,0x40,0x00};
1106 /* nopl 0(%[re]ax,%[re]ax,1) */
1107 static const char alt_5
[] =
1108 {0x0f,0x1f,0x44,0x00,0x00};
1109 /* nopw 0(%[re]ax,%[re]ax,1) */
1110 static const char alt_6
[] =
1111 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1112 /* nopl 0L(%[re]ax) */
1113 static const char alt_7
[] =
1114 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1115 /* nopl 0L(%[re]ax,%[re]ax,1) */
1116 static const char alt_8
[] =
1117 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1118 /* nopw 0L(%[re]ax,%[re]ax,1) */
1119 static const char alt_9
[] =
1120 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1121 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1122 static const char alt_10
[] =
1123 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1125 nopw %cs:0L(%[re]ax,%[re]ax,1) */
1126 static const char alt_long_11
[] =
1128 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1131 nopw %cs:0L(%[re]ax,%[re]ax,1) */
1132 static const char alt_long_12
[] =
1135 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1139 nopw %cs:0L(%[re]ax,%[re]ax,1) */
1140 static const char alt_long_13
[] =
1144 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1149 nopw %cs:0L(%[re]ax,%[re]ax,1) */
1150 static const char alt_long_14
[] =
1155 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1161 nopw %cs:0L(%[re]ax,%[re]ax,1) */
1162 static const char alt_long_15
[] =
1168 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1169 /* nopl 0(%[re]ax,%[re]ax,1)
1170 nopw 0(%[re]ax,%[re]ax,1) */
1171 static const char alt_short_11
[] =
1172 {0x0f,0x1f,0x44,0x00,0x00,
1173 0x66,0x0f,0x1f,0x44,0x00,0x00};
1174 /* nopw 0(%[re]ax,%[re]ax,1)
1175 nopw 0(%[re]ax,%[re]ax,1) */
1176 static const char alt_short_12
[] =
1177 {0x66,0x0f,0x1f,0x44,0x00,0x00,
1178 0x66,0x0f,0x1f,0x44,0x00,0x00};
1179 /* nopw 0(%[re]ax,%[re]ax,1)
1181 static const char alt_short_13
[] =
1182 {0x66,0x0f,0x1f,0x44,0x00,0x00,
1183 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1186 static const char alt_short_14
[] =
1187 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
1188 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1190 nopl 0L(%[re]ax,%[re]ax,1) */
1191 static const char alt_short_15
[] =
1192 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
1193 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1194 static const char *const alt_short_patt
[] = {
1195 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
1196 alt_9
, alt_10
, alt_short_11
, alt_short_12
, alt_short_13
,
1197 alt_short_14
, alt_short_15
1199 static const char *const alt_long_patt
[] = {
1200 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
1201 alt_9
, alt_10
, alt_long_11
, alt_long_12
, alt_long_13
,
1202 alt_long_14
, alt_long_15
1205 /* Only align for at least a positive non-zero boundary. */
1206 if (count
<= 0 || count
> MAX_MEM_FOR_RS_ALIGN_CODE
)
1209 /* We need to decide which NOP sequence to use for 32bit and
1210 64bit. When -mtune= is used:
1212 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1213 PROCESSOR_GENERIC32, f32_patt will be used.
1214 2. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
1215 PROCESSOR_CORE, PROCESSOR_CORE2, PROCESSOR_COREI7, and
1216 PROCESSOR_GENERIC64, alt_long_patt will be used.
1217 3. For PROCESSOR_ATHLON, PROCESSOR_K6, PROCESSOR_K8 and
1218 PROCESSOR_AMDFAM10, PROCESSOR_BD and PROCESSOR_BT, alt_short_patt
1221 When -mtune= isn't used, alt_long_patt will be used if
1222 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
1225 When -march= or .arch is used, we can't use anything beyond
1226 cpu_arch_isa_flags. */
1228 if (flag_code
== CODE_16BIT
)
1232 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1234 /* Adjust jump offset. */
1235 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
1238 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1239 f16_patt
[count
- 1], count
);
1243 const char *const *patt
= NULL
;
1245 if (fragP
->tc_frag_data
.isa
== PROCESSOR_UNKNOWN
)
1247 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1248 switch (cpu_arch_tune
)
1250 case PROCESSOR_UNKNOWN
:
1251 /* We use cpu_arch_isa_flags to check if we SHOULD
1252 optimize with nops. */
1253 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1254 patt
= alt_long_patt
;
1258 case PROCESSOR_PENTIUM4
:
1259 case PROCESSOR_NOCONA
:
1260 case PROCESSOR_CORE
:
1261 case PROCESSOR_CORE2
:
1262 case PROCESSOR_COREI7
:
1263 case PROCESSOR_L1OM
:
1264 case PROCESSOR_K1OM
:
1265 case PROCESSOR_GENERIC64
:
1266 patt
= alt_long_patt
;
1269 case PROCESSOR_ATHLON
:
1271 case PROCESSOR_AMDFAM10
:
1274 patt
= alt_short_patt
;
1276 case PROCESSOR_I386
:
1277 case PROCESSOR_I486
:
1278 case PROCESSOR_PENTIUM
:
1279 case PROCESSOR_PENTIUMPRO
:
1280 case PROCESSOR_GENERIC32
:
1287 switch (fragP
->tc_frag_data
.tune
)
1289 case PROCESSOR_UNKNOWN
:
1290 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1291 PROCESSOR_UNKNOWN. */
1295 case PROCESSOR_I386
:
1296 case PROCESSOR_I486
:
1297 case PROCESSOR_PENTIUM
:
1299 case PROCESSOR_ATHLON
:
1301 case PROCESSOR_AMDFAM10
:
1304 case PROCESSOR_GENERIC32
:
1305 /* We use cpu_arch_isa_flags to check if we CAN optimize
1307 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1308 patt
= alt_short_patt
;
1312 case PROCESSOR_PENTIUMPRO
:
1313 case PROCESSOR_PENTIUM4
:
1314 case PROCESSOR_NOCONA
:
1315 case PROCESSOR_CORE
:
1316 case PROCESSOR_CORE2
:
1317 case PROCESSOR_COREI7
:
1318 case PROCESSOR_L1OM
:
1319 case PROCESSOR_K1OM
:
1320 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1321 patt
= alt_long_patt
;
1325 case PROCESSOR_GENERIC64
:
1326 patt
= alt_long_patt
;
1331 if (patt
== f32_patt
)
1333 /* If the padding is less than 15 bytes, we use the normal
1334 ones. Otherwise, we use a jump instruction and adjust
1338 /* For 64bit, the limit is 3 bytes. */
1339 if (flag_code
== CODE_64BIT
1340 && fragP
->tc_frag_data
.isa_flags
.bitfield
.cpulm
)
1345 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1346 patt
[count
- 1], count
);
1349 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1351 /* Adjust jump offset. */
1352 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
1357 /* Maximum length of an instruction is 15 byte. If the
1358 padding is greater than 15 bytes and we don't use jump,
1359 we have to break it into smaller pieces. */
1360 int padding
= count
;
1361 while (padding
> 15)
1364 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
+ padding
,
1369 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1370 patt
[padding
- 1], padding
);
1373 fragP
->fr_var
= count
;
1377 operand_type_all_zero (const union i386_operand_type
*x
)
1379 switch (ARRAY_SIZE(x
->array
))
1388 return !x
->array
[0];
1395 operand_type_set (union i386_operand_type
*x
, unsigned int v
)
1397 switch (ARRAY_SIZE(x
->array
))
1412 operand_type_equal (const union i386_operand_type
*x
,
1413 const union i386_operand_type
*y
)
1415 switch (ARRAY_SIZE(x
->array
))
1418 if (x
->array
[2] != y
->array
[2])
1421 if (x
->array
[1] != y
->array
[1])
1424 return x
->array
[0] == y
->array
[0];
1432 cpu_flags_all_zero (const union i386_cpu_flags
*x
)
1434 switch (ARRAY_SIZE(x
->array
))
1443 return !x
->array
[0];
1450 cpu_flags_set (union i386_cpu_flags
*x
, unsigned int v
)
1452 switch (ARRAY_SIZE(x
->array
))
1467 cpu_flags_equal (const union i386_cpu_flags
*x
,
1468 const union i386_cpu_flags
*y
)
1470 switch (ARRAY_SIZE(x
->array
))
1473 if (x
->array
[2] != y
->array
[2])
1476 if (x
->array
[1] != y
->array
[1])
1479 return x
->array
[0] == y
->array
[0];
1487 cpu_flags_check_cpu64 (i386_cpu_flags f
)
1489 return !((flag_code
== CODE_64BIT
&& f
.bitfield
.cpuno64
)
1490 || (flag_code
!= CODE_64BIT
&& f
.bitfield
.cpu64
));
1493 static INLINE i386_cpu_flags
1494 cpu_flags_and (i386_cpu_flags x
, i386_cpu_flags y
)
1496 switch (ARRAY_SIZE (x
.array
))
1499 x
.array
[2] &= y
.array
[2];
1501 x
.array
[1] &= y
.array
[1];
1503 x
.array
[0] &= y
.array
[0];
1511 static INLINE i386_cpu_flags
1512 cpu_flags_or (i386_cpu_flags x
, i386_cpu_flags y
)
1514 switch (ARRAY_SIZE (x
.array
))
1517 x
.array
[2] |= y
.array
[2];
1519 x
.array
[1] |= y
.array
[1];
1521 x
.array
[0] |= y
.array
[0];
1529 static INLINE i386_cpu_flags
1530 cpu_flags_and_not (i386_cpu_flags x
, i386_cpu_flags y
)
1532 switch (ARRAY_SIZE (x
.array
))
1535 x
.array
[2] &= ~y
.array
[2];
1537 x
.array
[1] &= ~y
.array
[1];
1539 x
.array
[0] &= ~y
.array
[0];
1547 #define CPU_FLAGS_ARCH_MATCH 0x1
1548 #define CPU_FLAGS_64BIT_MATCH 0x2
1549 #define CPU_FLAGS_AES_MATCH 0x4
1550 #define CPU_FLAGS_PCLMUL_MATCH 0x8
1551 #define CPU_FLAGS_AVX_MATCH 0x10
1553 #define CPU_FLAGS_32BIT_MATCH \
1554 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH \
1555 | CPU_FLAGS_PCLMUL_MATCH | CPU_FLAGS_AVX_MATCH)
1556 #define CPU_FLAGS_PERFECT_MATCH \
1557 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)
1559 /* Return CPU flags match bits. */
1562 cpu_flags_match (const insn_template
*t
)
1564 i386_cpu_flags x
= t
->cpu_flags
;
1565 int match
= cpu_flags_check_cpu64 (x
) ? CPU_FLAGS_64BIT_MATCH
: 0;
1567 x
.bitfield
.cpu64
= 0;
1568 x
.bitfield
.cpuno64
= 0;
1570 if (cpu_flags_all_zero (&x
))
1572 /* This instruction is available on all archs. */
1573 match
|= CPU_FLAGS_32BIT_MATCH
;
1577 /* This instruction is available only on some archs. */
1578 i386_cpu_flags cpu
= cpu_arch_flags
;
1580 cpu
.bitfield
.cpu64
= 0;
1581 cpu
.bitfield
.cpuno64
= 0;
1582 cpu
= cpu_flags_and (x
, cpu
);
1583 if (!cpu_flags_all_zero (&cpu
))
1585 if (x
.bitfield
.cpuavx
)
1587 /* We only need to check AES/PCLMUL/SSE2AVX with AVX. */
1588 if (cpu
.bitfield
.cpuavx
)
1590 /* Check SSE2AVX. */
1591 if (!t
->opcode_modifier
.sse2avx
|| sse2avx
)
1593 match
|= (CPU_FLAGS_ARCH_MATCH
1594 | CPU_FLAGS_AVX_MATCH
);
1596 if (!x
.bitfield
.cpuaes
|| cpu
.bitfield
.cpuaes
)
1597 match
|= CPU_FLAGS_AES_MATCH
;
1599 if (!x
.bitfield
.cpupclmul
1600 || cpu
.bitfield
.cpupclmul
)
1601 match
|= CPU_FLAGS_PCLMUL_MATCH
;
1605 match
|= CPU_FLAGS_ARCH_MATCH
;
1608 match
|= CPU_FLAGS_32BIT_MATCH
;
1614 static INLINE i386_operand_type
1615 operand_type_and (i386_operand_type x
, i386_operand_type y
)
1617 switch (ARRAY_SIZE (x
.array
))
1620 x
.array
[2] &= y
.array
[2];
1622 x
.array
[1] &= y
.array
[1];
1624 x
.array
[0] &= y
.array
[0];
1632 static INLINE i386_operand_type
1633 operand_type_or (i386_operand_type x
, i386_operand_type y
)
1635 switch (ARRAY_SIZE (x
.array
))
1638 x
.array
[2] |= y
.array
[2];
1640 x
.array
[1] |= y
.array
[1];
1642 x
.array
[0] |= y
.array
[0];
1650 static INLINE i386_operand_type
1651 operand_type_xor (i386_operand_type x
, i386_operand_type y
)
1653 switch (ARRAY_SIZE (x
.array
))
1656 x
.array
[2] ^= y
.array
[2];
1658 x
.array
[1] ^= y
.array
[1];
1660 x
.array
[0] ^= y
.array
[0];
1668 static const i386_operand_type acc32
= OPERAND_TYPE_ACC32
;
1669 static const i386_operand_type acc64
= OPERAND_TYPE_ACC64
;
1670 static const i386_operand_type control
= OPERAND_TYPE_CONTROL
;
1671 static const i386_operand_type inoutportreg
1672 = OPERAND_TYPE_INOUTPORTREG
;
1673 static const i386_operand_type reg16_inoutportreg
1674 = OPERAND_TYPE_REG16_INOUTPORTREG
;
1675 static const i386_operand_type disp16
= OPERAND_TYPE_DISP16
;
1676 static const i386_operand_type disp32
= OPERAND_TYPE_DISP32
;
1677 static const i386_operand_type disp32s
= OPERAND_TYPE_DISP32S
;
1678 static const i386_operand_type disp16_32
= OPERAND_TYPE_DISP16_32
;
1679 static const i386_operand_type anydisp
1680 = OPERAND_TYPE_ANYDISP
;
1681 static const i386_operand_type regxmm
= OPERAND_TYPE_REGXMM
;
1682 static const i386_operand_type regymm
= OPERAND_TYPE_REGYMM
;
1683 static const i386_operand_type regzmm
= OPERAND_TYPE_REGZMM
;
1684 static const i386_operand_type regmask
= OPERAND_TYPE_REGMASK
;
1685 static const i386_operand_type imm8
= OPERAND_TYPE_IMM8
;
1686 static const i386_operand_type imm8s
= OPERAND_TYPE_IMM8S
;
1687 static const i386_operand_type imm16
= OPERAND_TYPE_IMM16
;
1688 static const i386_operand_type imm32
= OPERAND_TYPE_IMM32
;
1689 static const i386_operand_type imm32s
= OPERAND_TYPE_IMM32S
;
1690 static const i386_operand_type imm64
= OPERAND_TYPE_IMM64
;
1691 static const i386_operand_type imm16_32
= OPERAND_TYPE_IMM16_32
;
1692 static const i386_operand_type imm16_32s
= OPERAND_TYPE_IMM16_32S
;
1693 static const i386_operand_type imm16_32_32s
= OPERAND_TYPE_IMM16_32_32S
;
1694 static const i386_operand_type vec_imm4
= OPERAND_TYPE_VEC_IMM4
;
1705 operand_type_check (i386_operand_type t
, enum operand_type c
)
1710 return (t
.bitfield
.reg8
1713 || t
.bitfield
.reg64
);
1716 return (t
.bitfield
.imm8
1720 || t
.bitfield
.imm32s
1721 || t
.bitfield
.imm64
);
1724 return (t
.bitfield
.disp8
1725 || t
.bitfield
.disp16
1726 || t
.bitfield
.disp32
1727 || t
.bitfield
.disp32s
1728 || t
.bitfield
.disp64
);
1731 return (t
.bitfield
.disp8
1732 || t
.bitfield
.disp16
1733 || t
.bitfield
.disp32
1734 || t
.bitfield
.disp32s
1735 || t
.bitfield
.disp64
1736 || t
.bitfield
.baseindex
);
1745 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1746 operand J for instruction template T. */
1749 match_reg_size (const insn_template
*t
, unsigned int j
)
1751 return !((i
.types
[j
].bitfield
.byte
1752 && !t
->operand_types
[j
].bitfield
.byte
)
1753 || (i
.types
[j
].bitfield
.word
1754 && !t
->operand_types
[j
].bitfield
.word
)
1755 || (i
.types
[j
].bitfield
.dword
1756 && !t
->operand_types
[j
].bitfield
.dword
)
1757 || (i
.types
[j
].bitfield
.qword
1758 && !t
->operand_types
[j
].bitfield
.qword
));
1761 /* Return 1 if there is no conflict in any size on operand J for
1762 instruction template T. */
1765 match_mem_size (const insn_template
*t
, unsigned int j
)
1767 return (match_reg_size (t
, j
)
1768 && !((i
.types
[j
].bitfield
.unspecified
1769 && !t
->operand_types
[j
].bitfield
.unspecified
)
1770 || (i
.types
[j
].bitfield
.fword
1771 && !t
->operand_types
[j
].bitfield
.fword
)
1772 || (i
.types
[j
].bitfield
.tbyte
1773 && !t
->operand_types
[j
].bitfield
.tbyte
)
1774 || (i
.types
[j
].bitfield
.xmmword
1775 && !t
->operand_types
[j
].bitfield
.xmmword
)
1776 || (i
.types
[j
].bitfield
.ymmword
1777 && !t
->operand_types
[j
].bitfield
.ymmword
)
1778 || (i
.types
[j
].bitfield
.zmmword
1779 && !t
->operand_types
[j
].bitfield
.zmmword
)));
1782 /* Return 1 if there is no size conflict on any operands for
1783 instruction template T. */
1786 operand_size_match (const insn_template
*t
)
1791 /* Don't check jump instructions. */
1792 if (t
->opcode_modifier
.jump
1793 || t
->opcode_modifier
.jumpbyte
1794 || t
->opcode_modifier
.jumpdword
1795 || t
->opcode_modifier
.jumpintersegment
)
1798 /* Check memory and accumulator operand size. */
1799 for (j
= 0; j
< i
.operands
; j
++)
1801 if (t
->operand_types
[j
].bitfield
.anysize
)
1804 if (t
->operand_types
[j
].bitfield
.acc
&& !match_reg_size (t
, j
))
1810 if (i
.types
[j
].bitfield
.mem
&& !match_mem_size (t
, j
))
1819 else if (!t
->opcode_modifier
.d
&& !t
->opcode_modifier
.floatd
)
1822 i
.error
= operand_size_mismatch
;
1826 /* Check reverse. */
1827 gas_assert (i
.operands
== 2);
1830 for (j
= 0; j
< 2; j
++)
1832 if (t
->operand_types
[j
].bitfield
.acc
1833 && !match_reg_size (t
, j
? 0 : 1))
1836 if (i
.types
[j
].bitfield
.mem
1837 && !match_mem_size (t
, j
? 0 : 1))
1845 operand_type_match (i386_operand_type overlap
,
1846 i386_operand_type given
)
1848 i386_operand_type temp
= overlap
;
1850 temp
.bitfield
.jumpabsolute
= 0;
1851 temp
.bitfield
.unspecified
= 0;
1852 temp
.bitfield
.byte
= 0;
1853 temp
.bitfield
.word
= 0;
1854 temp
.bitfield
.dword
= 0;
1855 temp
.bitfield
.fword
= 0;
1856 temp
.bitfield
.qword
= 0;
1857 temp
.bitfield
.tbyte
= 0;
1858 temp
.bitfield
.xmmword
= 0;
1859 temp
.bitfield
.ymmword
= 0;
1860 temp
.bitfield
.zmmword
= 0;
1861 if (operand_type_all_zero (&temp
))
1864 if (given
.bitfield
.baseindex
== overlap
.bitfield
.baseindex
1865 && given
.bitfield
.jumpabsolute
== overlap
.bitfield
.jumpabsolute
)
1869 i
.error
= operand_type_mismatch
;
1873 /* If given types g0 and g1 are registers they must be of the same type
1874 unless the expected operand type register overlap is null.
1875 Note that Acc in a template matches every size of reg. */
1878 operand_type_register_match (i386_operand_type m0
,
1879 i386_operand_type g0
,
1880 i386_operand_type t0
,
1881 i386_operand_type m1
,
1882 i386_operand_type g1
,
1883 i386_operand_type t1
)
1885 if (!operand_type_check (g0
, reg
))
1888 if (!operand_type_check (g1
, reg
))
1891 if (g0
.bitfield
.reg8
== g1
.bitfield
.reg8
1892 && g0
.bitfield
.reg16
== g1
.bitfield
.reg16
1893 && g0
.bitfield
.reg32
== g1
.bitfield
.reg32
1894 && g0
.bitfield
.reg64
== g1
.bitfield
.reg64
)
1897 if (m0
.bitfield
.acc
)
1899 t0
.bitfield
.reg8
= 1;
1900 t0
.bitfield
.reg16
= 1;
1901 t0
.bitfield
.reg32
= 1;
1902 t0
.bitfield
.reg64
= 1;
1905 if (m1
.bitfield
.acc
)
1907 t1
.bitfield
.reg8
= 1;
1908 t1
.bitfield
.reg16
= 1;
1909 t1
.bitfield
.reg32
= 1;
1910 t1
.bitfield
.reg64
= 1;
1913 if (!(t0
.bitfield
.reg8
& t1
.bitfield
.reg8
)
1914 && !(t0
.bitfield
.reg16
& t1
.bitfield
.reg16
)
1915 && !(t0
.bitfield
.reg32
& t1
.bitfield
.reg32
)
1916 && !(t0
.bitfield
.reg64
& t1
.bitfield
.reg64
))
1919 i
.error
= register_type_mismatch
;
1924 static INLINE
unsigned int
1925 register_number (const reg_entry
*r
)
1927 unsigned int nr
= r
->reg_num
;
1929 if (r
->reg_flags
& RegRex
)
1935 static INLINE
unsigned int
1936 mode_from_disp_size (i386_operand_type t
)
1938 if (t
.bitfield
.disp8
|| t
.bitfield
.vec_disp8
)
1940 else if (t
.bitfield
.disp16
1941 || t
.bitfield
.disp32
1942 || t
.bitfield
.disp32s
)
1949 fits_in_signed_byte (offsetT num
)
1951 return (num
>= -128) && (num
<= 127);
1955 fits_in_unsigned_byte (offsetT num
)
1957 return (num
& 0xff) == num
;
1961 fits_in_unsigned_word (offsetT num
)
1963 return (num
& 0xffff) == num
;
1967 fits_in_signed_word (offsetT num
)
1969 return (-32768 <= num
) && (num
<= 32767);
1973 fits_in_signed_long (offsetT num ATTRIBUTE_UNUSED
)
1978 return (!(((offsetT
) -1 << 31) & num
)
1979 || (((offsetT
) -1 << 31) & num
) == ((offsetT
) -1 << 31));
1981 } /* fits_in_signed_long() */
1984 fits_in_unsigned_long (offsetT num ATTRIBUTE_UNUSED
)
1989 return (num
& (((offsetT
) 2 << 31) - 1)) == num
;
1991 } /* fits_in_unsigned_long() */
1994 fits_in_vec_disp8 (offsetT num
)
1996 int shift
= i
.memshift
;
2002 mask
= (1 << shift
) - 1;
2004 /* Return 0 if NUM isn't properly aligned. */
2008 /* Check if NUM will fit in 8bit after shift. */
2009 return fits_in_signed_byte (num
>> shift
);
2013 fits_in_imm4 (offsetT num
)
2015 return (num
& 0xf) == num
;
2018 static i386_operand_type
2019 smallest_imm_type (offsetT num
)
2021 i386_operand_type t
;
2023 operand_type_set (&t
, 0);
2024 t
.bitfield
.imm64
= 1;
2026 if (cpu_arch_tune
!= PROCESSOR_I486
&& num
== 1)
2028 /* This code is disabled on the 486 because all the Imm1 forms
2029 in the opcode table are slower on the i486. They're the
2030 versions with the implicitly specified single-position
2031 displacement, which has another syntax if you really want to
2033 t
.bitfield
.imm1
= 1;
2034 t
.bitfield
.imm8
= 1;
2035 t
.bitfield
.imm8s
= 1;
2036 t
.bitfield
.imm16
= 1;
2037 t
.bitfield
.imm32
= 1;
2038 t
.bitfield
.imm32s
= 1;
2040 else if (fits_in_signed_byte (num
))
2042 t
.bitfield
.imm8
= 1;
2043 t
.bitfield
.imm8s
= 1;
2044 t
.bitfield
.imm16
= 1;
2045 t
.bitfield
.imm32
= 1;
2046 t
.bitfield
.imm32s
= 1;
2048 else if (fits_in_unsigned_byte (num
))
2050 t
.bitfield
.imm8
= 1;
2051 t
.bitfield
.imm16
= 1;
2052 t
.bitfield
.imm32
= 1;
2053 t
.bitfield
.imm32s
= 1;
2055 else if (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
2057 t
.bitfield
.imm16
= 1;
2058 t
.bitfield
.imm32
= 1;
2059 t
.bitfield
.imm32s
= 1;
2061 else if (fits_in_signed_long (num
))
2063 t
.bitfield
.imm32
= 1;
2064 t
.bitfield
.imm32s
= 1;
2066 else if (fits_in_unsigned_long (num
))
2067 t
.bitfield
.imm32
= 1;
2073 offset_in_range (offsetT val
, int size
)
2079 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
2080 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
2081 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
2083 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
2089 /* If BFD64, sign extend val for 32bit address mode. */
2090 if (flag_code
!= CODE_64BIT
2091 || i
.prefix
[ADDR_PREFIX
])
2092 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
2093 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
2096 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
2098 char buf1
[40], buf2
[40];
2100 sprint_value (buf1
, val
);
2101 sprint_value (buf2
, val
& mask
);
2102 as_warn (_("%s shortened to %s"), buf1
, buf2
);
2116 a. PREFIX_EXIST if attempting to add a prefix where one from the
2117 same class already exists.
2118 b. PREFIX_LOCK if lock prefix is added.
2119 c. PREFIX_REP if rep/repne prefix is added.
2120 d. PREFIX_OTHER if other prefix is added.
2123 static enum PREFIX_GROUP
2124 add_prefix (unsigned int prefix
)
2126 enum PREFIX_GROUP ret
= PREFIX_OTHER
;
2129 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
2130 && flag_code
== CODE_64BIT
)
2132 if ((i
.prefix
[REX_PREFIX
] & prefix
& REX_W
)
2133 || ((i
.prefix
[REX_PREFIX
] & (REX_R
| REX_X
| REX_B
))
2134 && (prefix
& (REX_R
| REX_X
| REX_B
))))
2145 case CS_PREFIX_OPCODE
:
2146 case DS_PREFIX_OPCODE
:
2147 case ES_PREFIX_OPCODE
:
2148 case FS_PREFIX_OPCODE
:
2149 case GS_PREFIX_OPCODE
:
2150 case SS_PREFIX_OPCODE
:
2154 case REPNE_PREFIX_OPCODE
:
2155 case REPE_PREFIX_OPCODE
:
2160 case LOCK_PREFIX_OPCODE
:
2169 case ADDR_PREFIX_OPCODE
:
2173 case DATA_PREFIX_OPCODE
:
2177 if (i
.prefix
[q
] != 0)
2185 i
.prefix
[q
] |= prefix
;
2188 as_bad (_("same type of prefix used twice"));
2194 update_code_flag (int value
, int check
)
2196 PRINTF_LIKE ((*as_error
));
2198 flag_code
= (enum flag_code
) value
;
2199 if (flag_code
== CODE_64BIT
)
2201 cpu_arch_flags
.bitfield
.cpu64
= 1;
2202 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2206 cpu_arch_flags
.bitfield
.cpu64
= 0;
2207 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2209 if (value
== CODE_64BIT
&& !cpu_arch_flags
.bitfield
.cpulm
)
2212 as_error
= as_fatal
;
2215 (*as_error
) (_("64bit mode not supported on `%s'."),
2216 cpu_arch_name
? cpu_arch_name
: default_arch
);
2218 if (value
== CODE_32BIT
&& !cpu_arch_flags
.bitfield
.cpui386
)
2221 as_error
= as_fatal
;
2224 (*as_error
) (_("32bit mode not supported on `%s'."),
2225 cpu_arch_name
? cpu_arch_name
: default_arch
);
2227 stackop_size
= '\0';
2231 set_code_flag (int value
)
2233 update_code_flag (value
, 0);
2237 set_16bit_gcc_code_flag (int new_code_flag
)
2239 flag_code
= (enum flag_code
) new_code_flag
;
2240 if (flag_code
!= CODE_16BIT
)
2242 cpu_arch_flags
.bitfield
.cpu64
= 0;
2243 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2244 stackop_size
= LONG_MNEM_SUFFIX
;
2248 set_intel_syntax (int syntax_flag
)
2250 /* Find out if register prefixing is specified. */
2251 int ask_naked_reg
= 0;
2254 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2256 char *string
= input_line_pointer
;
2257 int e
= get_symbol_end ();
2259 if (strcmp (string
, "prefix") == 0)
2261 else if (strcmp (string
, "noprefix") == 0)
2264 as_bad (_("bad argument to syntax directive."));
2265 *input_line_pointer
= e
;
2267 demand_empty_rest_of_line ();
2269 intel_syntax
= syntax_flag
;
2271 if (ask_naked_reg
== 0)
2272 allow_naked_reg
= (intel_syntax
2273 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
2275 allow_naked_reg
= (ask_naked_reg
< 0);
2277 expr_set_rank (O_full_ptr
, syntax_flag
? 10 : 0);
2279 identifier_chars
['%'] = intel_syntax
&& allow_naked_reg
? '%' : 0;
2280 identifier_chars
['$'] = intel_syntax
? '$' : 0;
2281 register_prefix
= allow_naked_reg
? "" : "%";
2285 set_intel_mnemonic (int mnemonic_flag
)
2287 intel_mnemonic
= mnemonic_flag
;
2291 set_allow_index_reg (int flag
)
2293 allow_index_reg
= flag
;
2297 set_check (int what
)
2299 enum check_kind
*kind
;
2304 kind
= &operand_check
;
2315 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2317 char *string
= input_line_pointer
;
2318 int e
= get_symbol_end ();
2320 if (strcmp (string
, "none") == 0)
2322 else if (strcmp (string
, "warning") == 0)
2323 *kind
= check_warning
;
2324 else if (strcmp (string
, "error") == 0)
2325 *kind
= check_error
;
2327 as_bad (_("bad argument to %s_check directive."), str
);
2328 *input_line_pointer
= e
;
2331 as_bad (_("missing argument for %s_check directive"), str
);
2333 demand_empty_rest_of_line ();
2337 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED
,
2338 i386_cpu_flags new_flag ATTRIBUTE_UNUSED
)
2340 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2341 static const char *arch
;
2343 /* Intel LIOM is only supported on ELF. */
2349 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2350 use default_arch. */
2351 arch
= cpu_arch_name
;
2353 arch
= default_arch
;
2356 /* If we are targeting Intel L1OM, we must enable it. */
2357 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_L1OM
2358 || new_flag
.bitfield
.cpul1om
)
2361 /* If we are targeting Intel K1OM, we must enable it. */
2362 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_K1OM
2363 || new_flag
.bitfield
.cpuk1om
)
2366 as_bad (_("`%s' is not supported on `%s'"), name
, arch
);
2371 set_cpu_arch (int dummy ATTRIBUTE_UNUSED
)
2375 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2377 char *string
= input_line_pointer
;
2378 int e
= get_symbol_end ();
2380 i386_cpu_flags flags
;
2382 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
2384 if (strcmp (string
, cpu_arch
[j
].name
) == 0)
2386 check_cpu_arch_compatible (string
, cpu_arch
[j
].flags
);
2390 cpu_arch_name
= cpu_arch
[j
].name
;
2391 cpu_sub_arch_name
= NULL
;
2392 cpu_arch_flags
= cpu_arch
[j
].flags
;
2393 if (flag_code
== CODE_64BIT
)
2395 cpu_arch_flags
.bitfield
.cpu64
= 1;
2396 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2400 cpu_arch_flags
.bitfield
.cpu64
= 0;
2401 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2403 cpu_arch_isa
= cpu_arch
[j
].type
;
2404 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
2405 if (!cpu_arch_tune_set
)
2407 cpu_arch_tune
= cpu_arch_isa
;
2408 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
2413 if (!cpu_arch
[j
].negated
)
2414 flags
= cpu_flags_or (cpu_arch_flags
,
2417 flags
= cpu_flags_and_not (cpu_arch_flags
,
2419 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2421 if (cpu_sub_arch_name
)
2423 char *name
= cpu_sub_arch_name
;
2424 cpu_sub_arch_name
= concat (name
,
2426 (const char *) NULL
);
2430 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
2431 cpu_arch_flags
= flags
;
2432 cpu_arch_isa_flags
= flags
;
2434 *input_line_pointer
= e
;
2435 demand_empty_rest_of_line ();
2439 if (j
>= ARRAY_SIZE (cpu_arch
))
2440 as_bad (_("no such architecture: `%s'"), string
);
2442 *input_line_pointer
= e
;
2445 as_bad (_("missing cpu architecture"));
2447 no_cond_jump_promotion
= 0;
2448 if (*input_line_pointer
== ','
2449 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
2451 char *string
= ++input_line_pointer
;
2452 int e
= get_symbol_end ();
2454 if (strcmp (string
, "nojumps") == 0)
2455 no_cond_jump_promotion
= 1;
2456 else if (strcmp (string
, "jumps") == 0)
2459 as_bad (_("no such architecture modifier: `%s'"), string
);
2461 *input_line_pointer
= e
;
2464 demand_empty_rest_of_line ();
2467 enum bfd_architecture
2470 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2472 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2473 || flag_code
!= CODE_64BIT
)
2474 as_fatal (_("Intel L1OM is 64bit ELF only"));
2475 return bfd_arch_l1om
;
2477 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2479 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2480 || flag_code
!= CODE_64BIT
)
2481 as_fatal (_("Intel K1OM is 64bit ELF only"));
2482 return bfd_arch_k1om
;
2485 return bfd_arch_i386
;
2491 if (!strncmp (default_arch
, "x86_64", 6))
2493 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2495 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2496 || default_arch
[6] != '\0')
2497 as_fatal (_("Intel L1OM is 64bit ELF only"));
2498 return bfd_mach_l1om
;
2500 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2502 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2503 || default_arch
[6] != '\0')
2504 as_fatal (_("Intel K1OM is 64bit ELF only"));
2505 return bfd_mach_k1om
;
2507 else if (default_arch
[6] == '\0')
2508 return bfd_mach_x86_64
;
2510 return bfd_mach_x64_32
;
2512 else if (!strcmp (default_arch
, "i386"))
2513 return bfd_mach_i386_i386
;
2515 as_fatal (_("unknown architecture"));
2521 const char *hash_err
;
2523 /* Initialize op_hash hash table. */
2524 op_hash
= hash_new ();
2527 const insn_template
*optab
;
2528 templates
*core_optab
;
2530 /* Setup for loop. */
2532 core_optab
= (templates
*) xmalloc (sizeof (templates
));
2533 core_optab
->start
= optab
;
2538 if (optab
->name
== NULL
2539 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
2541 /* different name --> ship out current template list;
2542 add to hash table; & begin anew. */
2543 core_optab
->end
= optab
;
2544 hash_err
= hash_insert (op_hash
,
2546 (void *) core_optab
);
2549 as_fatal (_("can't hash %s: %s"),
2553 if (optab
->name
== NULL
)
2555 core_optab
= (templates
*) xmalloc (sizeof (templates
));
2556 core_optab
->start
= optab
;
2561 /* Initialize reg_hash hash table. */
2562 reg_hash
= hash_new ();
2564 const reg_entry
*regtab
;
2565 unsigned int regtab_size
= i386_regtab_size
;
2567 for (regtab
= i386_regtab
; regtab_size
--; regtab
++)
2569 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (void *) regtab
);
2571 as_fatal (_("can't hash %s: %s"),
2577 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
2582 for (c
= 0; c
< 256; c
++)
2587 mnemonic_chars
[c
] = c
;
2588 register_chars
[c
] = c
;
2589 operand_chars
[c
] = c
;
2591 else if (ISLOWER (c
))
2593 mnemonic_chars
[c
] = c
;
2594 register_chars
[c
] = c
;
2595 operand_chars
[c
] = c
;
2597 else if (ISUPPER (c
))
2599 mnemonic_chars
[c
] = TOLOWER (c
);
2600 register_chars
[c
] = mnemonic_chars
[c
];
2601 operand_chars
[c
] = c
;
2603 else if (c
== '{' || c
== '}')
2604 operand_chars
[c
] = c
;
2606 if (ISALPHA (c
) || ISDIGIT (c
))
2607 identifier_chars
[c
] = c
;
2610 identifier_chars
[c
] = c
;
2611 operand_chars
[c
] = c
;
2616 identifier_chars
['@'] = '@';
2619 identifier_chars
['?'] = '?';
2620 operand_chars
['?'] = '?';
2622 digit_chars
['-'] = '-';
2623 mnemonic_chars
['_'] = '_';
2624 mnemonic_chars
['-'] = '-';
2625 mnemonic_chars
['.'] = '.';
2626 identifier_chars
['_'] = '_';
2627 identifier_chars
['.'] = '.';
2629 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
2630 operand_chars
[(unsigned char) *p
] = *p
;
2633 if (flag_code
== CODE_64BIT
)
2635 #if defined (OBJ_COFF) && defined (TE_PE)
2636 x86_dwarf2_return_column
= (OUTPUT_FLAVOR
== bfd_target_coff_flavour
2639 x86_dwarf2_return_column
= 16;
2641 x86_cie_data_alignment
= -8;
2645 x86_dwarf2_return_column
= 8;
2646 x86_cie_data_alignment
= -4;
2651 i386_print_statistics (FILE *file
)
2653 hash_print_statistics (file
, "i386 opcode", op_hash
);
2654 hash_print_statistics (file
, "i386 register", reg_hash
);
2659 /* Debugging routines for md_assemble. */
2660 static void pte (insn_template
*);
2661 static void pt (i386_operand_type
);
2662 static void pe (expressionS
*);
2663 static void ps (symbolS
*);
2666 pi (char *line
, i386_insn
*x
)
2670 fprintf (stdout
, "%s: template ", line
);
2672 fprintf (stdout
, " address: base %s index %s scale %x\n",
2673 x
->base_reg
? x
->base_reg
->reg_name
: "none",
2674 x
->index_reg
? x
->index_reg
->reg_name
: "none",
2675 x
->log2_scale_factor
);
2676 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
2677 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
2678 fprintf (stdout
, " sib: base %x index %x scale %x\n",
2679 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
2680 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
2681 (x
->rex
& REX_W
) != 0,
2682 (x
->rex
& REX_R
) != 0,
2683 (x
->rex
& REX_X
) != 0,
2684 (x
->rex
& REX_B
) != 0);
2685 for (j
= 0; j
< x
->operands
; j
++)
2687 fprintf (stdout
, " #%d: ", j
+ 1);
2689 fprintf (stdout
, "\n");
2690 if (x
->types
[j
].bitfield
.reg8
2691 || x
->types
[j
].bitfield
.reg16
2692 || x
->types
[j
].bitfield
.reg32
2693 || x
->types
[j
].bitfield
.reg64
2694 || x
->types
[j
].bitfield
.regmmx
2695 || x
->types
[j
].bitfield
.regxmm
2696 || x
->types
[j
].bitfield
.regymm
2697 || x
->types
[j
].bitfield
.regzmm
2698 || x
->types
[j
].bitfield
.sreg2
2699 || x
->types
[j
].bitfield
.sreg3
2700 || x
->types
[j
].bitfield
.control
2701 || x
->types
[j
].bitfield
.debug
2702 || x
->types
[j
].bitfield
.test
)
2703 fprintf (stdout
, "%s\n", x
->op
[j
].regs
->reg_name
);
2704 if (operand_type_check (x
->types
[j
], imm
))
2706 if (operand_type_check (x
->types
[j
], disp
))
2707 pe (x
->op
[j
].disps
);
2712 pte (insn_template
*t
)
2715 fprintf (stdout
, " %d operands ", t
->operands
);
2716 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
2717 if (t
->extension_opcode
!= None
)
2718 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
2719 if (t
->opcode_modifier
.d
)
2720 fprintf (stdout
, "D");
2721 if (t
->opcode_modifier
.w
)
2722 fprintf (stdout
, "W");
2723 fprintf (stdout
, "\n");
2724 for (j
= 0; j
< t
->operands
; j
++)
2726 fprintf (stdout
, " #%d type ", j
+ 1);
2727 pt (t
->operand_types
[j
]);
2728 fprintf (stdout
, "\n");
2735 fprintf (stdout
, " operation %d\n", e
->X_op
);
2736 fprintf (stdout
, " add_number %ld (%lx)\n",
2737 (long) e
->X_add_number
, (long) e
->X_add_number
);
2738 if (e
->X_add_symbol
)
2740 fprintf (stdout
, " add_symbol ");
2741 ps (e
->X_add_symbol
);
2742 fprintf (stdout
, "\n");
2746 fprintf (stdout
, " op_symbol ");
2747 ps (e
->X_op_symbol
);
2748 fprintf (stdout
, "\n");
2755 fprintf (stdout
, "%s type %s%s",
2757 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
2758 segment_name (S_GET_SEGMENT (s
)));
2761 static struct type_name
2763 i386_operand_type mask
;
2766 const type_names
[] =
2768 { OPERAND_TYPE_REG8
, "r8" },
2769 { OPERAND_TYPE_REG16
, "r16" },
2770 { OPERAND_TYPE_REG32
, "r32" },
2771 { OPERAND_TYPE_REG64
, "r64" },
2772 { OPERAND_TYPE_IMM8
, "i8" },
2773 { OPERAND_TYPE_IMM8
, "i8s" },
2774 { OPERAND_TYPE_IMM16
, "i16" },
2775 { OPERAND_TYPE_IMM32
, "i32" },
2776 { OPERAND_TYPE_IMM32S
, "i32s" },
2777 { OPERAND_TYPE_IMM64
, "i64" },
2778 { OPERAND_TYPE_IMM1
, "i1" },
2779 { OPERAND_TYPE_BASEINDEX
, "BaseIndex" },
2780 { OPERAND_TYPE_DISP8
, "d8" },
2781 { OPERAND_TYPE_DISP16
, "d16" },
2782 { OPERAND_TYPE_DISP32
, "d32" },
2783 { OPERAND_TYPE_DISP32S
, "d32s" },
2784 { OPERAND_TYPE_DISP64
, "d64" },
2785 { OPERAND_TYPE_VEC_DISP8
, "Vector d8" },
2786 { OPERAND_TYPE_INOUTPORTREG
, "InOutPortReg" },
2787 { OPERAND_TYPE_SHIFTCOUNT
, "ShiftCount" },
2788 { OPERAND_TYPE_CONTROL
, "control reg" },
2789 { OPERAND_TYPE_TEST
, "test reg" },
2790 { OPERAND_TYPE_DEBUG
, "debug reg" },
2791 { OPERAND_TYPE_FLOATREG
, "FReg" },
2792 { OPERAND_TYPE_FLOATACC
, "FAcc" },
2793 { OPERAND_TYPE_SREG2
, "SReg2" },
2794 { OPERAND_TYPE_SREG3
, "SReg3" },
2795 { OPERAND_TYPE_ACC
, "Acc" },
2796 { OPERAND_TYPE_JUMPABSOLUTE
, "Jump Absolute" },
2797 { OPERAND_TYPE_REGMMX
, "rMMX" },
2798 { OPERAND_TYPE_REGXMM
, "rXMM" },
2799 { OPERAND_TYPE_REGYMM
, "rYMM" },
2800 { OPERAND_TYPE_REGZMM
, "rZMM" },
2801 { OPERAND_TYPE_REGMASK
, "Mask reg" },
2802 { OPERAND_TYPE_ESSEG
, "es" },
2806 pt (i386_operand_type t
)
2809 i386_operand_type a
;
2811 for (j
= 0; j
< ARRAY_SIZE (type_names
); j
++)
2813 a
= operand_type_and (t
, type_names
[j
].mask
);
2814 if (!operand_type_all_zero (&a
))
2815 fprintf (stdout
, "%s, ", type_names
[j
].name
);
2820 #endif /* DEBUG386 */
2822 static bfd_reloc_code_real_type
2823 reloc (unsigned int size
,
2827 bfd_reloc_code_real_type other
)
2829 if (other
!= NO_RELOC
)
2831 reloc_howto_type
*rel
;
2836 case BFD_RELOC_X86_64_GOT32
:
2837 return BFD_RELOC_X86_64_GOT64
;
2839 case BFD_RELOC_X86_64_PLTOFF64
:
2840 return BFD_RELOC_X86_64_PLTOFF64
;
2842 case BFD_RELOC_X86_64_GOTPC32
:
2843 other
= BFD_RELOC_X86_64_GOTPC64
;
2845 case BFD_RELOC_X86_64_GOTPCREL
:
2846 other
= BFD_RELOC_X86_64_GOTPCREL64
;
2848 case BFD_RELOC_X86_64_TPOFF32
:
2849 other
= BFD_RELOC_X86_64_TPOFF64
;
2851 case BFD_RELOC_X86_64_DTPOFF32
:
2852 other
= BFD_RELOC_X86_64_DTPOFF64
;
2858 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2859 if (other
== BFD_RELOC_SIZE32
)
2862 other
= BFD_RELOC_SIZE64
;
2865 as_bad (_("there are no pc-relative size relocations"));
2871 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
2872 if (size
== 4 && (flag_code
!= CODE_64BIT
|| disallow_64bit_reloc
))
2875 rel
= bfd_reloc_type_lookup (stdoutput
, other
);
2877 as_bad (_("unknown relocation (%u)"), other
);
2878 else if (size
!= bfd_get_reloc_size (rel
))
2879 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
2880 bfd_get_reloc_size (rel
),
2882 else if (pcrel
&& !rel
->pc_relative
)
2883 as_bad (_("non-pc-relative relocation for pc-relative field"));
2884 else if ((rel
->complain_on_overflow
== complain_overflow_signed
2886 || (rel
->complain_on_overflow
== complain_overflow_unsigned
2888 as_bad (_("relocated field and relocation type differ in signedness"));
2897 as_bad (_("there are no unsigned pc-relative relocations"));
2900 case 1: return BFD_RELOC_8_PCREL
;
2901 case 2: return BFD_RELOC_16_PCREL
;
2902 case 4: return (bnd_prefix
&& object_64bit
2903 ? BFD_RELOC_X86_64_PC32_BND
2904 : BFD_RELOC_32_PCREL
);
2905 case 8: return BFD_RELOC_64_PCREL
;
2907 as_bad (_("cannot do %u byte pc-relative relocation"), size
);
2914 case 4: return BFD_RELOC_X86_64_32S
;
2919 case 1: return BFD_RELOC_8
;
2920 case 2: return BFD_RELOC_16
;
2921 case 4: return BFD_RELOC_32
;
2922 case 8: return BFD_RELOC_64
;
2924 as_bad (_("cannot do %s %u byte relocation"),
2925 sign
> 0 ? "signed" : "unsigned", size
);
2931 /* Here we decide which fixups can be adjusted to make them relative to
2932 the beginning of the section instead of the symbol. Basically we need
2933 to make sure that the dynamic relocations are done correctly, so in
2934 some cases we force the original symbol to be used. */
2937 tc_i386_fix_adjustable (fixS
*fixP ATTRIBUTE_UNUSED
)
2939 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2943 /* Don't adjust pc-relative references to merge sections in 64-bit
2945 if (use_rela_relocations
2946 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
2950 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
2951 and changed later by validate_fix. */
2952 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
2953 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
2956 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
2957 for size relocations. */
2958 if (fixP
->fx_r_type
== BFD_RELOC_SIZE32
2959 || fixP
->fx_r_type
== BFD_RELOC_SIZE64
2960 || fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
2961 || fixP
->fx_r_type
== BFD_RELOC_386_PLT32
2962 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
2963 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
2964 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
2965 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
2966 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
2967 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
2968 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
2969 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
2970 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
2971 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTDESC
2972 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_DESC_CALL
2973 || fixP
->fx_r_type
== BFD_RELOC_X86_64_PLT32
2974 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
2975 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
2976 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
2977 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
2978 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
2979 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
2980 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
2981 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
2982 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
2983 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
2984 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPC32_TLSDESC
2985 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSDESC_CALL
2986 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
2987 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
2994 intel_float_operand (const char *mnemonic
)
2996 /* Note that the value returned is meaningful only for opcodes with (memory)
2997 operands, hence the code here is free to improperly handle opcodes that
2998 have no operands (for better performance and smaller code). */
3000 if (mnemonic
[0] != 'f')
3001 return 0; /* non-math */
3003 switch (mnemonic
[1])
3005 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
3006 the fs segment override prefix not currently handled because no
3007 call path can make opcodes without operands get here */
3009 return 2 /* integer op */;
3011 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
3012 return 3; /* fldcw/fldenv */
3015 if (mnemonic
[2] != 'o' /* fnop */)
3016 return 3; /* non-waiting control op */
3019 if (mnemonic
[2] == 's')
3020 return 3; /* frstor/frstpm */
3023 if (mnemonic
[2] == 'a')
3024 return 3; /* fsave */
3025 if (mnemonic
[2] == 't')
3027 switch (mnemonic
[3])
3029 case 'c': /* fstcw */
3030 case 'd': /* fstdw */
3031 case 'e': /* fstenv */
3032 case 's': /* fsts[gw] */
3038 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
3039 return 0; /* fxsave/fxrstor are not really math ops */
3046 /* Build the VEX prefix. */
3049 build_vex_prefix (const insn_template
*t
)
3051 unsigned int register_specifier
;
3052 unsigned int implied_prefix
;
3053 unsigned int vector_length
;
3055 /* Check register specifier. */
3056 if (i
.vex
.register_specifier
)
3058 register_specifier
=
3059 ~register_number (i
.vex
.register_specifier
) & 0xf;
3060 gas_assert ((i
.vex
.register_specifier
->reg_flags
& RegVRex
) == 0);
3063 register_specifier
= 0xf;
3065 /* Use 2-byte VEX prefix by swappping destination and source
3068 && i
.operands
== i
.reg_operands
3069 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3070 && i
.tm
.opcode_modifier
.s
3073 unsigned int xchg
= i
.operands
- 1;
3074 union i386_op temp_op
;
3075 i386_operand_type temp_type
;
3077 temp_type
= i
.types
[xchg
];
3078 i
.types
[xchg
] = i
.types
[0];
3079 i
.types
[0] = temp_type
;
3080 temp_op
= i
.op
[xchg
];
3081 i
.op
[xchg
] = i
.op
[0];
3084 gas_assert (i
.rm
.mode
== 3);
3088 i
.rm
.regmem
= i
.rm
.reg
;
3091 /* Use the next insn. */
3095 if (i
.tm
.opcode_modifier
.vex
== VEXScalar
)
3096 vector_length
= avxscalar
;
3098 vector_length
= i
.tm
.opcode_modifier
.vex
== VEX256
? 1 : 0;
3100 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3105 case DATA_PREFIX_OPCODE
:
3108 case REPE_PREFIX_OPCODE
:
3111 case REPNE_PREFIX_OPCODE
:
3118 /* Use 2-byte VEX prefix if possible. */
3119 if (i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3120 && i
.tm
.opcode_modifier
.vexw
!= VEXW1
3121 && (i
.rex
& (REX_W
| REX_X
| REX_B
)) == 0)
3123 /* 2-byte VEX prefix. */
3127 i
.vex
.bytes
[0] = 0xc5;
3129 /* Check the REX.R bit. */
3130 r
= (i
.rex
& REX_R
) ? 0 : 1;
3131 i
.vex
.bytes
[1] = (r
<< 7
3132 | register_specifier
<< 3
3133 | vector_length
<< 2
3138 /* 3-byte VEX prefix. */
3143 switch (i
.tm
.opcode_modifier
.vexopcode
)
3147 i
.vex
.bytes
[0] = 0xc4;
3151 i
.vex
.bytes
[0] = 0xc4;
3155 i
.vex
.bytes
[0] = 0xc4;
3159 i
.vex
.bytes
[0] = 0x8f;
3163 i
.vex
.bytes
[0] = 0x8f;
3167 i
.vex
.bytes
[0] = 0x8f;
3173 /* The high 3 bits of the second VEX byte are 1's compliment
3174 of RXB bits from REX. */
3175 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3177 /* Check the REX.W bit. */
3178 w
= (i
.rex
& REX_W
) ? 1 : 0;
3179 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
3182 i
.vex
.bytes
[2] = (w
<< 7
3183 | register_specifier
<< 3
3184 | vector_length
<< 2
3189 /* Build the EVEX prefix. */
3192 build_evex_prefix (void)
3194 unsigned int register_specifier
;
3195 unsigned int implied_prefix
;
3197 rex_byte vrex_used
= 0;
3199 /* Check register specifier. */
3200 if (i
.vex
.register_specifier
)
3202 gas_assert ((i
.vrex
& REX_X
) == 0);
3204 register_specifier
= i
.vex
.register_specifier
->reg_num
;
3205 if ((i
.vex
.register_specifier
->reg_flags
& RegRex
))
3206 register_specifier
+= 8;
3207 /* The upper 16 registers are encoded in the fourth byte of the
3209 if (!(i
.vex
.register_specifier
->reg_flags
& RegVRex
))
3210 i
.vex
.bytes
[3] = 0x8;
3211 register_specifier
= ~register_specifier
& 0xf;
3215 register_specifier
= 0xf;
3217 /* Encode upper 16 vector index register in the fourth byte of
3219 if (!(i
.vrex
& REX_X
))
3220 i
.vex
.bytes
[3] = 0x8;
3225 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3230 case DATA_PREFIX_OPCODE
:
3233 case REPE_PREFIX_OPCODE
:
3236 case REPNE_PREFIX_OPCODE
:
3243 /* 4 byte EVEX prefix. */
3245 i
.vex
.bytes
[0] = 0x62;
3248 switch (i
.tm
.opcode_modifier
.vexopcode
)
3264 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3266 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3268 /* The fifth bit of the second EVEX byte is 1's compliment of the
3269 REX_R bit in VREX. */
3270 if (!(i
.vrex
& REX_R
))
3271 i
.vex
.bytes
[1] |= 0x10;
3275 if ((i
.reg_operands
+ i
.imm_operands
) == i
.operands
)
3277 /* When all operands are registers, the REX_X bit in REX is not
3278 used. We reuse it to encode the upper 16 registers, which is
3279 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3280 as 1's compliment. */
3281 if ((i
.vrex
& REX_B
))
3284 i
.vex
.bytes
[1] &= ~0x40;
3288 /* EVEX instructions shouldn't need the REX prefix. */
3289 i
.vrex
&= ~vrex_used
;
3290 gas_assert (i
.vrex
== 0);
3292 /* Check the REX.W bit. */
3293 w
= (i
.rex
& REX_W
) ? 1 : 0;
3294 if (i
.tm
.opcode_modifier
.vexw
)
3296 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
3299 /* If w is not set it means we are dealing with WIG instruction. */
3302 if (evexwig
== evexw1
)
3306 /* Encode the U bit. */
3307 implied_prefix
|= 0x4;
3309 /* The third byte of the EVEX prefix. */
3310 i
.vex
.bytes
[2] = (w
<< 7 | register_specifier
<< 3 | implied_prefix
);
3312 /* The fourth byte of the EVEX prefix. */
3313 /* The zeroing-masking bit. */
3314 if (i
.mask
&& i
.mask
->zeroing
)
3315 i
.vex
.bytes
[3] |= 0x80;
3317 /* Don't always set the broadcast bit if there is no RC. */
3320 /* Encode the vector length. */
3321 unsigned int vec_length
;
3323 switch (i
.tm
.opcode_modifier
.evex
)
3325 case EVEXLIG
: /* LL' is ignored */
3326 vec_length
= evexlig
<< 5;
3329 vec_length
= 0 << 5;
3332 vec_length
= 1 << 5;
3335 vec_length
= 2 << 5;
3341 i
.vex
.bytes
[3] |= vec_length
;
3342 /* Encode the broadcast bit. */
3344 i
.vex
.bytes
[3] |= 0x10;
3348 if (i
.rounding
->type
!= saeonly
)
3349 i
.vex
.bytes
[3] |= 0x10 | (i
.rounding
->type
<< 5);
3351 i
.vex
.bytes
[3] |= 0x10 | (evexrcig
<< 5);
3354 if (i
.mask
&& i
.mask
->mask
)
3355 i
.vex
.bytes
[3] |= i
.mask
->mask
->reg_num
;
3359 process_immext (void)
3363 if ((i
.tm
.cpu_flags
.bitfield
.cpusse3
|| i
.tm
.cpu_flags
.bitfield
.cpusvme
)
3366 /* MONITOR/MWAIT as well as SVME instructions have fixed operands
3367 with an opcode suffix which is coded in the same place as an
3368 8-bit immediate field would be.
3369 Here we check those operands and remove them afterwards. */
3372 for (x
= 0; x
< i
.operands
; x
++)
3373 if (register_number (i
.op
[x
].regs
) != x
)
3374 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3375 register_prefix
, i
.op
[x
].regs
->reg_name
, x
+ 1,
3381 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
3382 which is coded in the same place as an 8-bit immediate field
3383 would be. Here we fake an 8-bit immediate operand from the
3384 opcode suffix stored in tm.extension_opcode.
3386 AVX instructions also use this encoding, for some of
3387 3 argument instructions. */
3389 gas_assert (i
.imm_operands
<= 1
3391 || ((i
.tm
.opcode_modifier
.vex
3392 || i
.tm
.opcode_modifier
.evex
)
3393 && i
.operands
<= 4)));
3395 exp
= &im_expressions
[i
.imm_operands
++];
3396 i
.op
[i
.operands
].imms
= exp
;
3397 i
.types
[i
.operands
] = imm8
;
3399 exp
->X_op
= O_constant
;
3400 exp
->X_add_number
= i
.tm
.extension_opcode
;
3401 i
.tm
.extension_opcode
= None
;
3408 switch (i
.tm
.opcode_modifier
.hleprefixok
)
3413 as_bad (_("invalid instruction `%s' after `%s'"),
3414 i
.tm
.name
, i
.hle_prefix
);
3417 if (i
.prefix
[LOCK_PREFIX
])
3419 as_bad (_("missing `lock' with `%s'"), i
.hle_prefix
);
3423 case HLEPrefixRelease
:
3424 if (i
.prefix
[HLE_PREFIX
] != XRELEASE_PREFIX_OPCODE
)
3426 as_bad (_("instruction `%s' after `xacquire' not allowed"),
3430 if (i
.mem_operands
== 0
3431 || !operand_type_check (i
.types
[i
.operands
- 1], anymem
))
3433 as_bad (_("memory destination needed for instruction `%s'"
3434 " after `xrelease'"), i
.tm
.name
);
3441 /* This is the guts of the machine-dependent assembler. LINE points to a
3442 machine dependent instruction. This function is supposed to emit
3443 the frags/bytes it assembles to. */
3446 md_assemble (char *line
)
3449 char mnemonic
[MAX_MNEM_SIZE
];
3450 const insn_template
*t
;
3452 /* Initialize globals. */
3453 memset (&i
, '\0', sizeof (i
));
3454 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3455 i
.reloc
[j
] = NO_RELOC
;
3456 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
3457 memset (im_expressions
, '\0', sizeof (im_expressions
));
3458 save_stack_p
= save_stack
;
3460 /* First parse an instruction mnemonic & call i386_operand for the operands.
3461 We assume that the scrubber has arranged it so that line[0] is the valid
3462 start of a (possibly prefixed) mnemonic. */
3464 line
= parse_insn (line
, mnemonic
);
3468 line
= parse_operands (line
, mnemonic
);
3473 /* Now we've parsed the mnemonic into a set of templates, and have the
3474 operands at hand. */
3476 /* All intel opcodes have reversed operands except for "bound" and
3477 "enter". We also don't reverse intersegment "jmp" and "call"
3478 instructions with 2 immediate operands so that the immediate segment
3479 precedes the offset, as it does when in AT&T mode. */
3482 && (strcmp (mnemonic
, "bound") != 0)
3483 && (strcmp (mnemonic
, "invlpga") != 0)
3484 && !(operand_type_check (i
.types
[0], imm
)
3485 && operand_type_check (i
.types
[1], imm
)))
3488 /* The order of the immediates should be reversed
3489 for 2 immediates extrq and insertq instructions */
3490 if (i
.imm_operands
== 2
3491 && (strcmp (mnemonic
, "extrq") == 0
3492 || strcmp (mnemonic
, "insertq") == 0))
3493 swap_2_operands (0, 1);
3498 /* Don't optimize displacement for movabs since it only takes 64bit
3501 && i
.disp_encoding
!= disp_encoding_32bit
3502 && (flag_code
!= CODE_64BIT
3503 || strcmp (mnemonic
, "movabs") != 0))
3506 /* Next, we find a template that matches the given insn,
3507 making sure the overlap of the given operands types is consistent
3508 with the template operand types. */
3510 if (!(t
= match_template ()))
3513 if (sse_check
!= check_none
3514 && !i
.tm
.opcode_modifier
.noavx
3515 && (i
.tm
.cpu_flags
.bitfield
.cpusse
3516 || i
.tm
.cpu_flags
.bitfield
.cpusse2
3517 || i
.tm
.cpu_flags
.bitfield
.cpusse3
3518 || i
.tm
.cpu_flags
.bitfield
.cpussse3
3519 || i
.tm
.cpu_flags
.bitfield
.cpusse4_1
3520 || i
.tm
.cpu_flags
.bitfield
.cpusse4_2
))
3522 (sse_check
== check_warning
3524 : as_bad
) (_("SSE instruction `%s' is used"), i
.tm
.name
);
3527 /* Zap movzx and movsx suffix. The suffix has been set from
3528 "word ptr" or "byte ptr" on the source operand in Intel syntax
3529 or extracted from mnemonic in AT&T syntax. But we'll use
3530 the destination register to choose the suffix for encoding. */
3531 if ((i
.tm
.base_opcode
& ~9) == 0x0fb6)
3533 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
3534 there is no suffix, the default will be byte extension. */
3535 if (i
.reg_operands
!= 2
3538 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
3543 if (i
.tm
.opcode_modifier
.fwait
)
3544 if (!add_prefix (FWAIT_OPCODE
))
3547 /* Check if REP prefix is OK. */
3548 if (i
.rep_prefix
&& !i
.tm
.opcode_modifier
.repprefixok
)
3550 as_bad (_("invalid instruction `%s' after `%s'"),
3551 i
.tm
.name
, i
.rep_prefix
);
3555 /* Check for lock without a lockable instruction. Destination operand
3556 must be memory unless it is xchg (0x86). */
3557 if (i
.prefix
[LOCK_PREFIX
]
3558 && (!i
.tm
.opcode_modifier
.islockable
3559 || i
.mem_operands
== 0
3560 || (i
.tm
.base_opcode
!= 0x86
3561 && !operand_type_check (i
.types
[i
.operands
- 1], anymem
))))
3563 as_bad (_("expecting lockable instruction after `lock'"));
3567 /* Check if HLE prefix is OK. */
3568 if (i
.hle_prefix
&& !check_hle ())
3571 /* Check BND prefix. */
3572 if (i
.bnd_prefix
&& !i
.tm
.opcode_modifier
.bndprefixok
)
3573 as_bad (_("expecting valid branch instruction after `bnd'"));
3575 if (i
.tm
.cpu_flags
.bitfield
.cpumpx
3576 && flag_code
== CODE_64BIT
3577 && i
.prefix
[ADDR_PREFIX
])
3578 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
3580 /* Insert BND prefix. */
3582 && i
.tm
.opcode_modifier
.bndprefixok
3583 && !i
.prefix
[BND_PREFIX
])
3584 add_prefix (BND_PREFIX_OPCODE
);
3586 /* Check string instruction segment overrides. */
3587 if (i
.tm
.opcode_modifier
.isstring
&& i
.mem_operands
!= 0)
3589 if (!check_string ())
3591 i
.disp_operands
= 0;
3594 if (!process_suffix ())
3597 /* Update operand types. */
3598 for (j
= 0; j
< i
.operands
; j
++)
3599 i
.types
[j
] = operand_type_and (i
.types
[j
], i
.tm
.operand_types
[j
]);
3601 /* Make still unresolved immediate matches conform to size of immediate
3602 given in i.suffix. */
3603 if (!finalize_imm ())
3606 if (i
.types
[0].bitfield
.imm1
)
3607 i
.imm_operands
= 0; /* kludge for shift insns. */
3609 /* We only need to check those implicit registers for instructions
3610 with 3 operands or less. */
3611 if (i
.operands
<= 3)
3612 for (j
= 0; j
< i
.operands
; j
++)
3613 if (i
.types
[j
].bitfield
.inoutportreg
3614 || i
.types
[j
].bitfield
.shiftcount
3615 || i
.types
[j
].bitfield
.acc
3616 || i
.types
[j
].bitfield
.floatacc
)
3619 /* ImmExt should be processed after SSE2AVX. */
3620 if (!i
.tm
.opcode_modifier
.sse2avx
3621 && i
.tm
.opcode_modifier
.immext
)
3624 /* For insns with operands there are more diddles to do to the opcode. */
3627 if (!process_operands ())
3630 else if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
3632 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
3633 as_warn (_("translating to `%sp'"), i
.tm
.name
);
3636 if (i
.tm
.opcode_modifier
.vex
)
3637 build_vex_prefix (t
);
3639 if (i
.tm
.opcode_modifier
.evex
)
3640 build_evex_prefix ();
3642 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
3643 instructions may define INT_OPCODE as well, so avoid this corner
3644 case for those instructions that use MODRM. */
3645 if (i
.tm
.base_opcode
== INT_OPCODE
3646 && !i
.tm
.opcode_modifier
.modrm
3647 && i
.op
[0].imms
->X_add_number
== 3)
3649 i
.tm
.base_opcode
= INT3_OPCODE
;
3653 if ((i
.tm
.opcode_modifier
.jump
3654 || i
.tm
.opcode_modifier
.jumpbyte
3655 || i
.tm
.opcode_modifier
.jumpdword
)
3656 && i
.op
[0].disps
->X_op
== O_constant
)
3658 /* Convert "jmp constant" (and "call constant") to a jump (call) to
3659 the absolute address given by the constant. Since ix86 jumps and
3660 calls are pc relative, we need to generate a reloc. */
3661 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
3662 i
.op
[0].disps
->X_op
= O_symbol
;
3665 if (i
.tm
.opcode_modifier
.rex64
)
3668 /* For 8 bit registers we need an empty rex prefix. Also if the
3669 instruction already has a prefix, we need to convert old
3670 registers to new ones. */
3672 if ((i
.types
[0].bitfield
.reg8
3673 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
3674 || (i
.types
[1].bitfield
.reg8
3675 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
3676 || ((i
.types
[0].bitfield
.reg8
3677 || i
.types
[1].bitfield
.reg8
)
3682 i
.rex
|= REX_OPCODE
;
3683 for (x
= 0; x
< 2; x
++)
3685 /* Look for 8 bit operand that uses old registers. */
3686 if (i
.types
[x
].bitfield
.reg8
3687 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
3689 /* In case it is "hi" register, give up. */
3690 if (i
.op
[x
].regs
->reg_num
> 3)
3691 as_bad (_("can't encode register '%s%s' in an "
3692 "instruction requiring REX prefix."),
3693 register_prefix
, i
.op
[x
].regs
->reg_name
);
3695 /* Otherwise it is equivalent to the extended register.
3696 Since the encoding doesn't change this is merely
3697 cosmetic cleanup for debug output. */
3699 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
3705 add_prefix (REX_OPCODE
| i
.rex
);
3707 /* We are ready to output the insn. */
3712 parse_insn (char *line
, char *mnemonic
)
3715 char *token_start
= l
;
3718 const insn_template
*t
;
3724 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
3729 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
3731 as_bad (_("no such instruction: `%s'"), token_start
);
3736 if (!is_space_char (*l
)
3737 && *l
!= END_OF_INSN
3739 || (*l
!= PREFIX_SEPARATOR
3742 as_bad (_("invalid character %s in mnemonic"),
3743 output_invalid (*l
));
3746 if (token_start
== l
)
3748 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
3749 as_bad (_("expecting prefix; got nothing"));
3751 as_bad (_("expecting mnemonic; got nothing"));
3755 /* Look up instruction (or prefix) via hash table. */
3756 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
3758 if (*l
!= END_OF_INSN
3759 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
3760 && current_templates
3761 && current_templates
->start
->opcode_modifier
.isprefix
)
3763 if (!cpu_flags_check_cpu64 (current_templates
->start
->cpu_flags
))
3765 as_bad ((flag_code
!= CODE_64BIT
3766 ? _("`%s' is only supported in 64-bit mode")
3767 : _("`%s' is not supported in 64-bit mode")),
3768 current_templates
->start
->name
);
3771 /* If we are in 16-bit mode, do not allow addr16 or data16.
3772 Similarly, in 32-bit mode, do not allow addr32 or data32. */
3773 if ((current_templates
->start
->opcode_modifier
.size16
3774 || current_templates
->start
->opcode_modifier
.size32
)
3775 && flag_code
!= CODE_64BIT
3776 && (current_templates
->start
->opcode_modifier
.size32
3777 ^ (flag_code
== CODE_16BIT
)))
3779 as_bad (_("redundant %s prefix"),
3780 current_templates
->start
->name
);
3783 /* Add prefix, checking for repeated prefixes. */
3784 switch (add_prefix (current_templates
->start
->base_opcode
))
3789 if (current_templates
->start
->cpu_flags
.bitfield
.cpuhle
)
3790 i
.hle_prefix
= current_templates
->start
->name
;
3791 else if (current_templates
->start
->cpu_flags
.bitfield
.cpumpx
)
3792 i
.bnd_prefix
= current_templates
->start
->name
;
3794 i
.rep_prefix
= current_templates
->start
->name
;
3799 /* Skip past PREFIX_SEPARATOR and reset token_start. */
3806 if (!current_templates
)
3808 /* Check if we should swap operand or force 32bit displacement in
3810 if (mnem_p
- 2 == dot_p
&& dot_p
[1] == 's')
3812 else if (mnem_p
- 3 == dot_p
3815 i
.disp_encoding
= disp_encoding_8bit
;
3816 else if (mnem_p
- 4 == dot_p
3820 i
.disp_encoding
= disp_encoding_32bit
;
3825 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
3828 if (!current_templates
)
3831 /* See if we can get a match by trimming off a suffix. */
3834 case WORD_MNEM_SUFFIX
:
3835 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
3836 i
.suffix
= SHORT_MNEM_SUFFIX
;
3838 case BYTE_MNEM_SUFFIX
:
3839 case QWORD_MNEM_SUFFIX
:
3840 i
.suffix
= mnem_p
[-1];
3842 current_templates
= (const templates
*) hash_find (op_hash
,
3845 case SHORT_MNEM_SUFFIX
:
3846 case LONG_MNEM_SUFFIX
:
3849 i
.suffix
= mnem_p
[-1];
3851 current_templates
= (const templates
*) hash_find (op_hash
,
3860 if (intel_float_operand (mnemonic
) == 1)
3861 i
.suffix
= SHORT_MNEM_SUFFIX
;
3863 i
.suffix
= LONG_MNEM_SUFFIX
;
3865 current_templates
= (const templates
*) hash_find (op_hash
,
3870 if (!current_templates
)
3872 as_bad (_("no such instruction: `%s'"), token_start
);
3877 if (current_templates
->start
->opcode_modifier
.jump
3878 || current_templates
->start
->opcode_modifier
.jumpbyte
)
3880 /* Check for a branch hint. We allow ",pt" and ",pn" for
3881 predict taken and predict not taken respectively.
3882 I'm not sure that branch hints actually do anything on loop
3883 and jcxz insns (JumpByte) for current Pentium4 chips. They
3884 may work in the future and it doesn't hurt to accept them
3886 if (l
[0] == ',' && l
[1] == 'p')
3890 if (!add_prefix (DS_PREFIX_OPCODE
))
3894 else if (l
[2] == 'n')
3896 if (!add_prefix (CS_PREFIX_OPCODE
))
3902 /* Any other comma loses. */
3905 as_bad (_("invalid character %s in mnemonic"),
3906 output_invalid (*l
));
3910 /* Check if instruction is supported on specified architecture. */
3912 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
3914 supported
|= cpu_flags_match (t
);
3915 if (supported
== CPU_FLAGS_PERFECT_MATCH
)
3919 if (!(supported
& CPU_FLAGS_64BIT_MATCH
))
3921 as_bad (flag_code
== CODE_64BIT
3922 ? _("`%s' is not supported in 64-bit mode")
3923 : _("`%s' is only supported in 64-bit mode"),
3924 current_templates
->start
->name
);
3927 if (supported
!= CPU_FLAGS_PERFECT_MATCH
)
3929 as_bad (_("`%s' is not supported on `%s%s'"),
3930 current_templates
->start
->name
,
3931 cpu_arch_name
? cpu_arch_name
: default_arch
,
3932 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
3937 if (!cpu_arch_flags
.bitfield
.cpui386
3938 && (flag_code
!= CODE_16BIT
))
3940 as_warn (_("use .code16 to ensure correct addressing mode"));
3947 parse_operands (char *l
, const char *mnemonic
)
3951 /* 1 if operand is pending after ','. */
3952 unsigned int expecting_operand
= 0;
3954 /* Non-zero if operand parens not balanced. */
3955 unsigned int paren_not_balanced
;
3957 while (*l
!= END_OF_INSN
)
3959 /* Skip optional white space before operand. */
3960 if (is_space_char (*l
))
3962 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
)
3964 as_bad (_("invalid character %s before operand %d"),
3965 output_invalid (*l
),
3969 token_start
= l
; /* after white space */
3970 paren_not_balanced
= 0;
3971 while (paren_not_balanced
|| *l
!= ',')
3973 if (*l
== END_OF_INSN
)
3975 if (paren_not_balanced
)
3978 as_bad (_("unbalanced parenthesis in operand %d."),
3981 as_bad (_("unbalanced brackets in operand %d."),
3986 break; /* we are done */
3988 else if (!is_operand_char (*l
) && !is_space_char (*l
))
3990 as_bad (_("invalid character %s in operand %d"),
3991 output_invalid (*l
),
3998 ++paren_not_balanced
;
4000 --paren_not_balanced
;
4005 ++paren_not_balanced
;
4007 --paren_not_balanced
;
4011 if (l
!= token_start
)
4012 { /* Yes, we've read in another operand. */
4013 unsigned int operand_ok
;
4014 this_operand
= i
.operands
++;
4015 i
.types
[this_operand
].bitfield
.unspecified
= 1;
4016 if (i
.operands
> MAX_OPERANDS
)
4018 as_bad (_("spurious operands; (%d operands/instruction max)"),
4022 /* Now parse operand adding info to 'i' as we go along. */
4023 END_STRING_AND_SAVE (l
);
4027 i386_intel_operand (token_start
,
4028 intel_float_operand (mnemonic
));
4030 operand_ok
= i386_att_operand (token_start
);
4032 RESTORE_END_STRING (l
);
4038 if (expecting_operand
)
4040 expecting_operand_after_comma
:
4041 as_bad (_("expecting operand after ','; got nothing"));
4046 as_bad (_("expecting operand before ','; got nothing"));
4051 /* Now *l must be either ',' or END_OF_INSN. */
4054 if (*++l
== END_OF_INSN
)
4056 /* Just skip it, if it's \n complain. */
4057 goto expecting_operand_after_comma
;
4059 expecting_operand
= 1;
4066 swap_2_operands (int xchg1
, int xchg2
)
4068 union i386_op temp_op
;
4069 i386_operand_type temp_type
;
4070 enum bfd_reloc_code_real temp_reloc
;
4072 temp_type
= i
.types
[xchg2
];
4073 i
.types
[xchg2
] = i
.types
[xchg1
];
4074 i
.types
[xchg1
] = temp_type
;
4075 temp_op
= i
.op
[xchg2
];
4076 i
.op
[xchg2
] = i
.op
[xchg1
];
4077 i
.op
[xchg1
] = temp_op
;
4078 temp_reloc
= i
.reloc
[xchg2
];
4079 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
4080 i
.reloc
[xchg1
] = temp_reloc
;
4084 if (i
.mask
->operand
== xchg1
)
4085 i
.mask
->operand
= xchg2
;
4086 else if (i
.mask
->operand
== xchg2
)
4087 i
.mask
->operand
= xchg1
;
4091 if (i
.broadcast
->operand
== xchg1
)
4092 i
.broadcast
->operand
= xchg2
;
4093 else if (i
.broadcast
->operand
== xchg2
)
4094 i
.broadcast
->operand
= xchg1
;
4098 if (i
.rounding
->operand
== xchg1
)
4099 i
.rounding
->operand
= xchg2
;
4100 else if (i
.rounding
->operand
== xchg2
)
4101 i
.rounding
->operand
= xchg1
;
4106 swap_operands (void)
4112 swap_2_operands (1, i
.operands
- 2);
4115 swap_2_operands (0, i
.operands
- 1);
4121 if (i
.mem_operands
== 2)
4123 const seg_entry
*temp_seg
;
4124 temp_seg
= i
.seg
[0];
4125 i
.seg
[0] = i
.seg
[1];
4126 i
.seg
[1] = temp_seg
;
4130 /* Try to ensure constant immediates are represented in the smallest
4135 char guess_suffix
= 0;
4139 guess_suffix
= i
.suffix
;
4140 else if (i
.reg_operands
)
4142 /* Figure out a suffix from the last register operand specified.
4143 We can't do this properly yet, ie. excluding InOutPortReg,
4144 but the following works for instructions with immediates.
4145 In any case, we can't set i.suffix yet. */
4146 for (op
= i
.operands
; --op
>= 0;)
4147 if (i
.types
[op
].bitfield
.reg8
)
4149 guess_suffix
= BYTE_MNEM_SUFFIX
;
4152 else if (i
.types
[op
].bitfield
.reg16
)
4154 guess_suffix
= WORD_MNEM_SUFFIX
;
4157 else if (i
.types
[op
].bitfield
.reg32
)
4159 guess_suffix
= LONG_MNEM_SUFFIX
;
4162 else if (i
.types
[op
].bitfield
.reg64
)
4164 guess_suffix
= QWORD_MNEM_SUFFIX
;
4168 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
4169 guess_suffix
= WORD_MNEM_SUFFIX
;
4171 for (op
= i
.operands
; --op
>= 0;)
4172 if (operand_type_check (i
.types
[op
], imm
))
4174 switch (i
.op
[op
].imms
->X_op
)
4177 /* If a suffix is given, this operand may be shortened. */
4178 switch (guess_suffix
)
4180 case LONG_MNEM_SUFFIX
:
4181 i
.types
[op
].bitfield
.imm32
= 1;
4182 i
.types
[op
].bitfield
.imm64
= 1;
4184 case WORD_MNEM_SUFFIX
:
4185 i
.types
[op
].bitfield
.imm16
= 1;
4186 i
.types
[op
].bitfield
.imm32
= 1;
4187 i
.types
[op
].bitfield
.imm32s
= 1;
4188 i
.types
[op
].bitfield
.imm64
= 1;
4190 case BYTE_MNEM_SUFFIX
:
4191 i
.types
[op
].bitfield
.imm8
= 1;
4192 i
.types
[op
].bitfield
.imm8s
= 1;
4193 i
.types
[op
].bitfield
.imm16
= 1;
4194 i
.types
[op
].bitfield
.imm32
= 1;
4195 i
.types
[op
].bitfield
.imm32s
= 1;
4196 i
.types
[op
].bitfield
.imm64
= 1;
4200 /* If this operand is at most 16 bits, convert it
4201 to a signed 16 bit number before trying to see
4202 whether it will fit in an even smaller size.
4203 This allows a 16-bit operand such as $0xffe0 to
4204 be recognised as within Imm8S range. */
4205 if ((i
.types
[op
].bitfield
.imm16
)
4206 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
4208 i
.op
[op
].imms
->X_add_number
=
4209 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
4211 if ((i
.types
[op
].bitfield
.imm32
)
4212 && ((i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1))
4215 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
4216 ^ ((offsetT
) 1 << 31))
4217 - ((offsetT
) 1 << 31));
4220 = operand_type_or (i
.types
[op
],
4221 smallest_imm_type (i
.op
[op
].imms
->X_add_number
));
4223 /* We must avoid matching of Imm32 templates when 64bit
4224 only immediate is available. */
4225 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
4226 i
.types
[op
].bitfield
.imm32
= 0;
4233 /* Symbols and expressions. */
4235 /* Convert symbolic operand to proper sizes for matching, but don't
4236 prevent matching a set of insns that only supports sizes other
4237 than those matching the insn suffix. */
4239 i386_operand_type mask
, allowed
;
4240 const insn_template
*t
;
4242 operand_type_set (&mask
, 0);
4243 operand_type_set (&allowed
, 0);
4245 for (t
= current_templates
->start
;
4246 t
< current_templates
->end
;
4248 allowed
= operand_type_or (allowed
,
4249 t
->operand_types
[op
]);
4250 switch (guess_suffix
)
4252 case QWORD_MNEM_SUFFIX
:
4253 mask
.bitfield
.imm64
= 1;
4254 mask
.bitfield
.imm32s
= 1;
4256 case LONG_MNEM_SUFFIX
:
4257 mask
.bitfield
.imm32
= 1;
4259 case WORD_MNEM_SUFFIX
:
4260 mask
.bitfield
.imm16
= 1;
4262 case BYTE_MNEM_SUFFIX
:
4263 mask
.bitfield
.imm8
= 1;
4268 allowed
= operand_type_and (mask
, allowed
);
4269 if (!operand_type_all_zero (&allowed
))
4270 i
.types
[op
] = operand_type_and (i
.types
[op
], mask
);
4277 /* Try to use the smallest displacement type too. */
4279 optimize_disp (void)
4283 for (op
= i
.operands
; --op
>= 0;)
4284 if (operand_type_check (i
.types
[op
], disp
))
4286 if (i
.op
[op
].disps
->X_op
== O_constant
)
4288 offsetT op_disp
= i
.op
[op
].disps
->X_add_number
;
4290 if (i
.types
[op
].bitfield
.disp16
4291 && (op_disp
& ~(offsetT
) 0xffff) == 0)
4293 /* If this operand is at most 16 bits, convert
4294 to a signed 16 bit number and don't use 64bit
4296 op_disp
= (((op_disp
& 0xffff) ^ 0x8000) - 0x8000);
4297 i
.types
[op
].bitfield
.disp64
= 0;
4299 if (i
.types
[op
].bitfield
.disp32
4300 && (op_disp
& ~(((offsetT
) 2 << 31) - 1)) == 0)
4302 /* If this operand is at most 32 bits, convert
4303 to a signed 32 bit number and don't use 64bit
4305 op_disp
&= (((offsetT
) 2 << 31) - 1);
4306 op_disp
= (op_disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
4307 i
.types
[op
].bitfield
.disp64
= 0;
4309 if (!op_disp
&& i
.types
[op
].bitfield
.baseindex
)
4311 i
.types
[op
].bitfield
.disp8
= 0;
4312 i
.types
[op
].bitfield
.disp16
= 0;
4313 i
.types
[op
].bitfield
.disp32
= 0;
4314 i
.types
[op
].bitfield
.disp32s
= 0;
4315 i
.types
[op
].bitfield
.disp64
= 0;
4319 else if (flag_code
== CODE_64BIT
)
4321 if (fits_in_signed_long (op_disp
))
4323 i
.types
[op
].bitfield
.disp64
= 0;
4324 i
.types
[op
].bitfield
.disp32s
= 1;
4326 if (i
.prefix
[ADDR_PREFIX
]
4327 && fits_in_unsigned_long (op_disp
))
4328 i
.types
[op
].bitfield
.disp32
= 1;
4330 if ((i
.types
[op
].bitfield
.disp32
4331 || i
.types
[op
].bitfield
.disp32s
4332 || i
.types
[op
].bitfield
.disp16
)
4333 && fits_in_signed_byte (op_disp
))
4334 i
.types
[op
].bitfield
.disp8
= 1;
4336 else if (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
4337 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
)
4339 fix_new_exp (frag_now
, frag_more (0) - frag_now
->fr_literal
, 0,
4340 i
.op
[op
].disps
, 0, i
.reloc
[op
]);
4341 i
.types
[op
].bitfield
.disp8
= 0;
4342 i
.types
[op
].bitfield
.disp16
= 0;
4343 i
.types
[op
].bitfield
.disp32
= 0;
4344 i
.types
[op
].bitfield
.disp32s
= 0;
4345 i
.types
[op
].bitfield
.disp64
= 0;
4348 /* We only support 64bit displacement on constants. */
4349 i
.types
[op
].bitfield
.disp64
= 0;
4353 /* Check if operands are valid for the instruction. */
4356 check_VecOperands (const insn_template
*t
)
4360 /* Without VSIB byte, we can't have a vector register for index. */
4361 if (!t
->opcode_modifier
.vecsib
4363 && (i
.index_reg
->reg_type
.bitfield
.regxmm
4364 || i
.index_reg
->reg_type
.bitfield
.regymm
4365 || i
.index_reg
->reg_type
.bitfield
.regzmm
))
4367 i
.error
= unsupported_vector_index_register
;
4371 /* Check if default mask is allowed. */
4372 if (t
->opcode_modifier
.nodefmask
4373 && (!i
.mask
|| i
.mask
->mask
->reg_num
== 0))
4375 i
.error
= no_default_mask
;
4379 /* For VSIB byte, we need a vector register for index, and all vector
4380 registers must be distinct. */
4381 if (t
->opcode_modifier
.vecsib
)
4384 || !((t
->opcode_modifier
.vecsib
== VecSIB128
4385 && i
.index_reg
->reg_type
.bitfield
.regxmm
)
4386 || (t
->opcode_modifier
.vecsib
== VecSIB256
4387 && i
.index_reg
->reg_type
.bitfield
.regymm
)
4388 || (t
->opcode_modifier
.vecsib
== VecSIB512
4389 && i
.index_reg
->reg_type
.bitfield
.regzmm
)))
4391 i
.error
= invalid_vsib_address
;
4395 gas_assert (i
.reg_operands
== 2 || i
.mask
);
4396 if (i
.reg_operands
== 2 && !i
.mask
)
4398 gas_assert (i
.types
[0].bitfield
.regxmm
4399 || i
.types
[0].bitfield
.regymm
);
4400 gas_assert (i
.types
[2].bitfield
.regxmm
4401 || i
.types
[2].bitfield
.regymm
);
4402 if (operand_check
== check_none
)
4404 if (register_number (i
.op
[0].regs
)
4405 != register_number (i
.index_reg
)
4406 && register_number (i
.op
[2].regs
)
4407 != register_number (i
.index_reg
)
4408 && register_number (i
.op
[0].regs
)
4409 != register_number (i
.op
[2].regs
))
4411 if (operand_check
== check_error
)
4413 i
.error
= invalid_vector_register_set
;
4416 as_warn (_("mask, index, and destination registers should be distinct"));
4418 else if (i
.reg_operands
== 1 && i
.mask
)
4420 if ((i
.types
[1].bitfield
.regymm
4421 || i
.types
[1].bitfield
.regzmm
)
4422 && (register_number (i
.op
[1].regs
)
4423 == register_number (i
.index_reg
)))
4425 if (operand_check
== check_error
)
4427 i
.error
= invalid_vector_register_set
;
4430 if (operand_check
!= check_none
)
4431 as_warn (_("index and destination registers should be distinct"));
4436 /* Check if broadcast is supported by the instruction and is applied
4437 to the memory operand. */
4440 int broadcasted_opnd_size
;
4442 /* Check if specified broadcast is supported in this instruction,
4443 and it's applied to memory operand of DWORD or QWORD type,
4444 depending on VecESize. */
4445 if (i
.broadcast
->type
!= t
->opcode_modifier
.broadcast
4446 || !i
.types
[i
.broadcast
->operand
].bitfield
.mem
4447 || (t
->opcode_modifier
.vecesize
== 0
4448 && !i
.types
[i
.broadcast
->operand
].bitfield
.dword
4449 && !i
.types
[i
.broadcast
->operand
].bitfield
.unspecified
)
4450 || (t
->opcode_modifier
.vecesize
== 1
4451 && !i
.types
[i
.broadcast
->operand
].bitfield
.qword
4452 && !i
.types
[i
.broadcast
->operand
].bitfield
.unspecified
))
4455 broadcasted_opnd_size
= t
->opcode_modifier
.vecesize
? 64 : 32;
4456 if (i
.broadcast
->type
== BROADCAST_1TO16
)
4457 broadcasted_opnd_size
<<= 4; /* Broadcast 1to16. */
4458 else if (i
.broadcast
->type
== BROADCAST_1TO8
)
4459 broadcasted_opnd_size
<<= 3; /* Broadcast 1to8. */
4460 else if (i
.broadcast
->type
== BROADCAST_1TO4
)
4461 broadcasted_opnd_size
<<= 2; /* Broadcast 1to4. */
4462 else if (i
.broadcast
->type
== BROADCAST_1TO2
)
4463 broadcasted_opnd_size
<<= 1; /* Broadcast 1to2. */
4467 if ((broadcasted_opnd_size
== 256
4468 && !t
->operand_types
[i
.broadcast
->operand
].bitfield
.ymmword
)
4469 || (broadcasted_opnd_size
== 512
4470 && !t
->operand_types
[i
.broadcast
->operand
].bitfield
.zmmword
))
4473 i
.error
= unsupported_broadcast
;
4477 /* If broadcast is supported in this instruction, we need to check if
4478 operand of one-element size isn't specified without broadcast. */
4479 else if (t
->opcode_modifier
.broadcast
&& i
.mem_operands
)
4481 /* Find memory operand. */
4482 for (op
= 0; op
< i
.operands
; op
++)
4483 if (operand_type_check (i
.types
[op
], anymem
))
4485 gas_assert (op
< i
.operands
);
4486 /* Check size of the memory operand. */
4487 if ((t
->opcode_modifier
.vecesize
== 0
4488 && i
.types
[op
].bitfield
.dword
)
4489 || (t
->opcode_modifier
.vecesize
== 1
4490 && i
.types
[op
].bitfield
.qword
))
4492 i
.error
= broadcast_needed
;
4497 /* Check if requested masking is supported. */
4499 && (!t
->opcode_modifier
.masking
4501 && t
->opcode_modifier
.masking
== MERGING_MASKING
)))
4503 i
.error
= unsupported_masking
;
4507 /* Check if masking is applied to dest operand. */
4508 if (i
.mask
&& (i
.mask
->operand
!= (int) (i
.operands
- 1)))
4510 i
.error
= mask_not_on_destination
;
4517 if ((i
.rounding
->type
!= saeonly
4518 && !t
->opcode_modifier
.staticrounding
)
4519 || (i
.rounding
->type
== saeonly
4520 && (t
->opcode_modifier
.staticrounding
4521 || !t
->opcode_modifier
.sae
)))
4523 i
.error
= unsupported_rc_sae
;
4526 /* If the instruction has several immediate operands and one of
4527 them is rounding, the rounding operand should be the last
4528 immediate operand. */
4529 if (i
.imm_operands
> 1
4530 && i
.rounding
->operand
!= (int) (i
.imm_operands
- 1))
4532 i
.error
= rc_sae_operand_not_last_imm
;
4537 /* Check vector Disp8 operand. */
4538 if (t
->opcode_modifier
.disp8memshift
)
4541 i
.memshift
= t
->opcode_modifier
.vecesize
? 3 : 2;
4543 i
.memshift
= t
->opcode_modifier
.disp8memshift
;
4545 for (op
= 0; op
< i
.operands
; op
++)
4546 if (operand_type_check (i
.types
[op
], disp
)
4547 && i
.op
[op
].disps
->X_op
== O_constant
)
4549 offsetT value
= i
.op
[op
].disps
->X_add_number
;
4550 int vec_disp8_ok
= fits_in_vec_disp8 (value
);
4551 if (t
->operand_types
[op
].bitfield
.vec_disp8
)
4554 i
.types
[op
].bitfield
.vec_disp8
= 1;
4557 /* Vector insn can only have Vec_Disp8/Disp32 in
4558 32/64bit modes, and Vec_Disp8/Disp16 in 16bit
4560 i
.types
[op
].bitfield
.disp8
= 0;
4561 if (flag_code
!= CODE_16BIT
)
4562 i
.types
[op
].bitfield
.disp16
= 0;
4565 else if (flag_code
!= CODE_16BIT
)
4567 /* One form of this instruction supports vector Disp8.
4568 Try vector Disp8 if we need to use Disp32. */
4569 if (vec_disp8_ok
&& !fits_in_signed_byte (value
))
4571 i
.error
= try_vector_disp8
;
4583 /* Check if operands are valid for the instruction. Update VEX
4587 VEX_check_operands (const insn_template
*t
)
4589 /* VREX is only valid with EVEX prefix. */
4590 if (i
.need_vrex
&& !t
->opcode_modifier
.evex
)
4592 i
.error
= invalid_register_operand
;
4596 if (!t
->opcode_modifier
.vex
)
4599 /* Only check VEX_Imm4, which must be the first operand. */
4600 if (t
->operand_types
[0].bitfield
.vec_imm4
)
4602 if (i
.op
[0].imms
->X_op
!= O_constant
4603 || !fits_in_imm4 (i
.op
[0].imms
->X_add_number
))
4609 /* Turn off Imm8 so that update_imm won't complain. */
4610 i
.types
[0] = vec_imm4
;
4616 static const insn_template
*
4617 match_template (void)
4619 /* Points to template once we've found it. */
4620 const insn_template
*t
;
4621 i386_operand_type overlap0
, overlap1
, overlap2
, overlap3
;
4622 i386_operand_type overlap4
;
4623 unsigned int found_reverse_match
;
4624 i386_opcode_modifier suffix_check
;
4625 i386_operand_type operand_types
[MAX_OPERANDS
];
4626 int addr_prefix_disp
;
4628 unsigned int found_cpu_match
;
4629 unsigned int check_register
;
4630 enum i386_error specific_error
= 0;
4632 #if MAX_OPERANDS != 5
4633 # error "MAX_OPERANDS must be 5."
4636 found_reverse_match
= 0;
4637 addr_prefix_disp
= -1;
4639 memset (&suffix_check
, 0, sizeof (suffix_check
));
4640 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
4641 suffix_check
.no_bsuf
= 1;
4642 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
4643 suffix_check
.no_wsuf
= 1;
4644 else if (i
.suffix
== SHORT_MNEM_SUFFIX
)
4645 suffix_check
.no_ssuf
= 1;
4646 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
4647 suffix_check
.no_lsuf
= 1;
4648 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
4649 suffix_check
.no_qsuf
= 1;
4650 else if (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
)
4651 suffix_check
.no_ldsuf
= 1;
4653 /* Must have right number of operands. */
4654 i
.error
= number_of_operands_mismatch
;
4656 for (t
= current_templates
->start
; t
< current_templates
->end
; t
++)
4658 addr_prefix_disp
= -1;
4660 if (i
.operands
!= t
->operands
)
4663 /* Check processor support. */
4664 i
.error
= unsupported
;
4665 found_cpu_match
= (cpu_flags_match (t
)
4666 == CPU_FLAGS_PERFECT_MATCH
);
4667 if (!found_cpu_match
)
4670 /* Check old gcc support. */
4671 i
.error
= old_gcc_only
;
4672 if (!old_gcc
&& t
->opcode_modifier
.oldgcc
)
4675 /* Check AT&T mnemonic. */
4676 i
.error
= unsupported_with_intel_mnemonic
;
4677 if (intel_mnemonic
&& t
->opcode_modifier
.attmnemonic
)
4680 /* Check AT&T/Intel syntax. */
4681 i
.error
= unsupported_syntax
;
4682 if ((intel_syntax
&& t
->opcode_modifier
.attsyntax
)
4683 || (!intel_syntax
&& t
->opcode_modifier
.intelsyntax
))
4686 /* Check the suffix, except for some instructions in intel mode. */
4687 i
.error
= invalid_instruction_suffix
;
4688 if ((!intel_syntax
|| !t
->opcode_modifier
.ignoresize
)
4689 && ((t
->opcode_modifier
.no_bsuf
&& suffix_check
.no_bsuf
)
4690 || (t
->opcode_modifier
.no_wsuf
&& suffix_check
.no_wsuf
)
4691 || (t
->opcode_modifier
.no_lsuf
&& suffix_check
.no_lsuf
)
4692 || (t
->opcode_modifier
.no_ssuf
&& suffix_check
.no_ssuf
)
4693 || (t
->opcode_modifier
.no_qsuf
&& suffix_check
.no_qsuf
)
4694 || (t
->opcode_modifier
.no_ldsuf
&& suffix_check
.no_ldsuf
)))
4697 if (!operand_size_match (t
))
4700 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4701 operand_types
[j
] = t
->operand_types
[j
];
4703 /* In general, don't allow 64-bit operands in 32-bit mode. */
4704 if (i
.suffix
== QWORD_MNEM_SUFFIX
4705 && flag_code
!= CODE_64BIT
4707 ? (!t
->opcode_modifier
.ignoresize
4708 && !intel_float_operand (t
->name
))
4709 : intel_float_operand (t
->name
) != 2)
4710 && ((!operand_types
[0].bitfield
.regmmx
4711 && !operand_types
[0].bitfield
.regxmm
4712 && !operand_types
[0].bitfield
.regymm
4713 && !operand_types
[0].bitfield
.regzmm
)
4714 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
4715 && operand_types
[t
->operands
> 1].bitfield
.regxmm
4716 && operand_types
[t
->operands
> 1].bitfield
.regymm
4717 && operand_types
[t
->operands
> 1].bitfield
.regzmm
))
4718 && (t
->base_opcode
!= 0x0fc7
4719 || t
->extension_opcode
!= 1 /* cmpxchg8b */))
4722 /* In general, don't allow 32-bit operands on pre-386. */
4723 else if (i
.suffix
== LONG_MNEM_SUFFIX
4724 && !cpu_arch_flags
.bitfield
.cpui386
4726 ? (!t
->opcode_modifier
.ignoresize
4727 && !intel_float_operand (t
->name
))
4728 : intel_float_operand (t
->name
) != 2)
4729 && ((!operand_types
[0].bitfield
.regmmx
4730 && !operand_types
[0].bitfield
.regxmm
)
4731 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
4732 && operand_types
[t
->operands
> 1].bitfield
.regxmm
)))
4735 /* Do not verify operands when there are none. */
4739 /* We've found a match; break out of loop. */
4743 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
4744 into Disp32/Disp16/Disp32 operand. */
4745 if (i
.prefix
[ADDR_PREFIX
] != 0)
4747 /* There should be only one Disp operand. */
4751 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4753 if (operand_types
[j
].bitfield
.disp16
)
4755 addr_prefix_disp
= j
;
4756 operand_types
[j
].bitfield
.disp32
= 1;
4757 operand_types
[j
].bitfield
.disp16
= 0;
4763 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4765 if (operand_types
[j
].bitfield
.disp32
)
4767 addr_prefix_disp
= j
;
4768 operand_types
[j
].bitfield
.disp32
= 0;
4769 operand_types
[j
].bitfield
.disp16
= 1;
4775 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4777 if (operand_types
[j
].bitfield
.disp64
)
4779 addr_prefix_disp
= j
;
4780 operand_types
[j
].bitfield
.disp64
= 0;
4781 operand_types
[j
].bitfield
.disp32
= 1;
4789 /* We check register size if needed. */
4790 check_register
= t
->opcode_modifier
.checkregsize
;
4791 overlap0
= operand_type_and (i
.types
[0], operand_types
[0]);
4792 switch (t
->operands
)
4795 if (!operand_type_match (overlap0
, i
.types
[0]))
4799 /* xchg %eax, %eax is a special case. It is an aliase for nop
4800 only in 32bit mode and we can use opcode 0x90. In 64bit
4801 mode, we can't use 0x90 for xchg %eax, %eax since it should
4802 zero-extend %eax to %rax. */
4803 if (flag_code
== CODE_64BIT
4804 && t
->base_opcode
== 0x90
4805 && operand_type_equal (&i
.types
[0], &acc32
)
4806 && operand_type_equal (&i
.types
[1], &acc32
))
4810 /* If we swap operand in encoding, we either match
4811 the next one or reverse direction of operands. */
4812 if (t
->opcode_modifier
.s
)
4814 else if (t
->opcode_modifier
.d
)
4819 /* If we swap operand in encoding, we match the next one. */
4820 if (i
.swap_operand
&& t
->opcode_modifier
.s
)
4824 overlap1
= operand_type_and (i
.types
[1], operand_types
[1]);
4825 if (!operand_type_match (overlap0
, i
.types
[0])
4826 || !operand_type_match (overlap1
, i
.types
[1])
4828 && !operand_type_register_match (overlap0
, i
.types
[0],
4830 overlap1
, i
.types
[1],
4833 /* Check if other direction is valid ... */
4834 if (!t
->opcode_modifier
.d
&& !t
->opcode_modifier
.floatd
)
4838 /* Try reversing direction of operands. */
4839 overlap0
= operand_type_and (i
.types
[0], operand_types
[1]);
4840 overlap1
= operand_type_and (i
.types
[1], operand_types
[0]);
4841 if (!operand_type_match (overlap0
, i
.types
[0])
4842 || !operand_type_match (overlap1
, i
.types
[1])
4844 && !operand_type_register_match (overlap0
,
4851 /* Does not match either direction. */
4854 /* found_reverse_match holds which of D or FloatDR
4856 if (t
->opcode_modifier
.d
)
4857 found_reverse_match
= Opcode_D
;
4858 else if (t
->opcode_modifier
.floatd
)
4859 found_reverse_match
= Opcode_FloatD
;
4861 found_reverse_match
= 0;
4862 if (t
->opcode_modifier
.floatr
)
4863 found_reverse_match
|= Opcode_FloatR
;
4867 /* Found a forward 2 operand match here. */
4868 switch (t
->operands
)
4871 overlap4
= operand_type_and (i
.types
[4],
4874 overlap3
= operand_type_and (i
.types
[3],
4877 overlap2
= operand_type_and (i
.types
[2],
4882 switch (t
->operands
)
4885 if (!operand_type_match (overlap4
, i
.types
[4])
4886 || !operand_type_register_match (overlap3
,
4894 if (!operand_type_match (overlap3
, i
.types
[3])
4896 && !operand_type_register_match (overlap2
,
4904 /* Here we make use of the fact that there are no
4905 reverse match 3 operand instructions, and all 3
4906 operand instructions only need to be checked for
4907 register consistency between operands 2 and 3. */
4908 if (!operand_type_match (overlap2
, i
.types
[2])
4910 && !operand_type_register_match (overlap1
,
4920 /* Found either forward/reverse 2, 3 or 4 operand match here:
4921 slip through to break. */
4923 if (!found_cpu_match
)
4925 found_reverse_match
= 0;
4929 /* Check if vector and VEX operands are valid. */
4930 if (check_VecOperands (t
) || VEX_check_operands (t
))
4932 specific_error
= i
.error
;
4936 /* We've found a match; break out of loop. */
4940 if (t
== current_templates
->end
)
4942 /* We found no match. */
4943 const char *err_msg
;
4944 switch (specific_error
? specific_error
: i
.error
)
4948 case operand_size_mismatch
:
4949 err_msg
= _("operand size mismatch");
4951 case operand_type_mismatch
:
4952 err_msg
= _("operand type mismatch");
4954 case register_type_mismatch
:
4955 err_msg
= _("register type mismatch");
4957 case number_of_operands_mismatch
:
4958 err_msg
= _("number of operands mismatch");
4960 case invalid_instruction_suffix
:
4961 err_msg
= _("invalid instruction suffix");
4964 err_msg
= _("constant doesn't fit in 4 bits");
4967 err_msg
= _("only supported with old gcc");
4969 case unsupported_with_intel_mnemonic
:
4970 err_msg
= _("unsupported with Intel mnemonic");
4972 case unsupported_syntax
:
4973 err_msg
= _("unsupported syntax");
4976 as_bad (_("unsupported instruction `%s'"),
4977 current_templates
->start
->name
);
4979 case invalid_vsib_address
:
4980 err_msg
= _("invalid VSIB address");
4982 case invalid_vector_register_set
:
4983 err_msg
= _("mask, index, and destination registers must be distinct");
4985 case unsupported_vector_index_register
:
4986 err_msg
= _("unsupported vector index register");
4988 case unsupported_broadcast
:
4989 err_msg
= _("unsupported broadcast");
4991 case broadcast_not_on_src_operand
:
4992 err_msg
= _("broadcast not on source memory operand");
4994 case broadcast_needed
:
4995 err_msg
= _("broadcast is needed for operand of such type");
4997 case unsupported_masking
:
4998 err_msg
= _("unsupported masking");
5000 case mask_not_on_destination
:
5001 err_msg
= _("mask not on destination operand");
5003 case no_default_mask
:
5004 err_msg
= _("default mask isn't allowed");
5006 case unsupported_rc_sae
:
5007 err_msg
= _("unsupported static rounding/sae");
5009 case rc_sae_operand_not_last_imm
:
5011 err_msg
= _("RC/SAE operand must precede immediate operands");
5013 err_msg
= _("RC/SAE operand must follow immediate operands");
5015 case invalid_register_operand
:
5016 err_msg
= _("invalid register operand");
5019 as_bad (_("%s for `%s'"), err_msg
,
5020 current_templates
->start
->name
);
5024 if (!quiet_warnings
)
5027 && (i
.types
[0].bitfield
.jumpabsolute
5028 != operand_types
[0].bitfield
.jumpabsolute
))
5030 as_warn (_("indirect %s without `*'"), t
->name
);
5033 if (t
->opcode_modifier
.isprefix
5034 && t
->opcode_modifier
.ignoresize
)
5036 /* Warn them that a data or address size prefix doesn't
5037 affect assembly of the next line of code. */
5038 as_warn (_("stand-alone `%s' prefix"), t
->name
);
5042 /* Copy the template we found. */
5045 if (addr_prefix_disp
!= -1)
5046 i
.tm
.operand_types
[addr_prefix_disp
]
5047 = operand_types
[addr_prefix_disp
];
5049 if (found_reverse_match
)
5051 /* If we found a reverse match we must alter the opcode
5052 direction bit. found_reverse_match holds bits to change
5053 (different for int & float insns). */
5055 i
.tm
.base_opcode
^= found_reverse_match
;
5057 i
.tm
.operand_types
[0] = operand_types
[1];
5058 i
.tm
.operand_types
[1] = operand_types
[0];
5067 int mem_op
= operand_type_check (i
.types
[0], anymem
) ? 0 : 1;
5068 if (i
.tm
.operand_types
[mem_op
].bitfield
.esseg
)
5070 if (i
.seg
[0] != NULL
&& i
.seg
[0] != &es
)
5072 as_bad (_("`%s' operand %d must use `%ses' segment"),
5078 /* There's only ever one segment override allowed per instruction.
5079 This instruction possibly has a legal segment override on the
5080 second operand, so copy the segment to where non-string
5081 instructions store it, allowing common code. */
5082 i
.seg
[0] = i
.seg
[1];
5084 else if (i
.tm
.operand_types
[mem_op
+ 1].bitfield
.esseg
)
5086 if (i
.seg
[1] != NULL
&& i
.seg
[1] != &es
)
5088 as_bad (_("`%s' operand %d must use `%ses' segment"),
5099 process_suffix (void)
5101 /* If matched instruction specifies an explicit instruction mnemonic
5103 if (i
.tm
.opcode_modifier
.size16
)
5104 i
.suffix
= WORD_MNEM_SUFFIX
;
5105 else if (i
.tm
.opcode_modifier
.size32
)
5106 i
.suffix
= LONG_MNEM_SUFFIX
;
5107 else if (i
.tm
.opcode_modifier
.size64
)
5108 i
.suffix
= QWORD_MNEM_SUFFIX
;
5109 else if (i
.reg_operands
)
5111 /* If there's no instruction mnemonic suffix we try to invent one
5112 based on register operands. */
5115 /* We take i.suffix from the last register operand specified,
5116 Destination register type is more significant than source
5117 register type. crc32 in SSE4.2 prefers source register
5119 if (i
.tm
.base_opcode
== 0xf20f38f1)
5121 if (i
.types
[0].bitfield
.reg16
)
5122 i
.suffix
= WORD_MNEM_SUFFIX
;
5123 else if (i
.types
[0].bitfield
.reg32
)
5124 i
.suffix
= LONG_MNEM_SUFFIX
;
5125 else if (i
.types
[0].bitfield
.reg64
)
5126 i
.suffix
= QWORD_MNEM_SUFFIX
;
5128 else if (i
.tm
.base_opcode
== 0xf20f38f0)
5130 if (i
.types
[0].bitfield
.reg8
)
5131 i
.suffix
= BYTE_MNEM_SUFFIX
;
5138 if (i
.tm
.base_opcode
== 0xf20f38f1
5139 || i
.tm
.base_opcode
== 0xf20f38f0)
5141 /* We have to know the operand size for crc32. */
5142 as_bad (_("ambiguous memory operand size for `%s`"),
5147 for (op
= i
.operands
; --op
>= 0;)
5148 if (!i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
5150 if (i
.types
[op
].bitfield
.reg8
)
5152 i
.suffix
= BYTE_MNEM_SUFFIX
;
5155 else if (i
.types
[op
].bitfield
.reg16
)
5157 i
.suffix
= WORD_MNEM_SUFFIX
;
5160 else if (i
.types
[op
].bitfield
.reg32
)
5162 i
.suffix
= LONG_MNEM_SUFFIX
;
5165 else if (i
.types
[op
].bitfield
.reg64
)
5167 i
.suffix
= QWORD_MNEM_SUFFIX
;
5173 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
5176 && i
.tm
.opcode_modifier
.ignoresize
5177 && i
.tm
.opcode_modifier
.no_bsuf
)
5179 else if (!check_byte_reg ())
5182 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
5185 && i
.tm
.opcode_modifier
.ignoresize
5186 && i
.tm
.opcode_modifier
.no_lsuf
)
5188 else if (!check_long_reg ())
5191 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
5194 && i
.tm
.opcode_modifier
.ignoresize
5195 && i
.tm
.opcode_modifier
.no_qsuf
)
5197 else if (!check_qword_reg ())
5200 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
5203 && i
.tm
.opcode_modifier
.ignoresize
5204 && i
.tm
.opcode_modifier
.no_wsuf
)
5206 else if (!check_word_reg ())
5209 else if (i
.suffix
== XMMWORD_MNEM_SUFFIX
5210 || i
.suffix
== YMMWORD_MNEM_SUFFIX
5211 || i
.suffix
== ZMMWORD_MNEM_SUFFIX
)
5213 /* Skip if the instruction has x/y/z suffix. match_template
5214 should check if it is a valid suffix. */
5216 else if (intel_syntax
&& i
.tm
.opcode_modifier
.ignoresize
)
5217 /* Do nothing if the instruction is going to ignore the prefix. */
5222 else if (i
.tm
.opcode_modifier
.defaultsize
5224 /* exclude fldenv/frstor/fsave/fstenv */
5225 && i
.tm
.opcode_modifier
.no_ssuf
)
5227 i
.suffix
= stackop_size
;
5229 else if (intel_syntax
5231 && (i
.tm
.operand_types
[0].bitfield
.jumpabsolute
5232 || i
.tm
.opcode_modifier
.jumpbyte
5233 || i
.tm
.opcode_modifier
.jumpintersegment
5234 || (i
.tm
.base_opcode
== 0x0f01 /* [ls][gi]dt */
5235 && i
.tm
.extension_opcode
<= 3)))
5240 if (!i
.tm
.opcode_modifier
.no_qsuf
)
5242 i
.suffix
= QWORD_MNEM_SUFFIX
;
5246 if (!i
.tm
.opcode_modifier
.no_lsuf
)
5247 i
.suffix
= LONG_MNEM_SUFFIX
;
5250 if (!i
.tm
.opcode_modifier
.no_wsuf
)
5251 i
.suffix
= WORD_MNEM_SUFFIX
;
5260 if (i
.tm
.opcode_modifier
.w
)
5262 as_bad (_("no instruction mnemonic suffix given and "
5263 "no register operands; can't size instruction"));
5269 unsigned int suffixes
;
5271 suffixes
= !i
.tm
.opcode_modifier
.no_bsuf
;
5272 if (!i
.tm
.opcode_modifier
.no_wsuf
)
5274 if (!i
.tm
.opcode_modifier
.no_lsuf
)
5276 if (!i
.tm
.opcode_modifier
.no_ldsuf
)
5278 if (!i
.tm
.opcode_modifier
.no_ssuf
)
5280 if (!i
.tm
.opcode_modifier
.no_qsuf
)
5283 /* There are more than suffix matches. */
5284 if (i
.tm
.opcode_modifier
.w
5285 || ((suffixes
& (suffixes
- 1))
5286 && !i
.tm
.opcode_modifier
.defaultsize
5287 && !i
.tm
.opcode_modifier
.ignoresize
))
5289 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
5295 /* Change the opcode based on the operand size given by i.suffix;
5296 We don't need to change things for byte insns. */
5299 && i
.suffix
!= BYTE_MNEM_SUFFIX
5300 && i
.suffix
!= XMMWORD_MNEM_SUFFIX
5301 && i
.suffix
!= YMMWORD_MNEM_SUFFIX
5302 && i
.suffix
!= ZMMWORD_MNEM_SUFFIX
)
5304 /* It's not a byte, select word/dword operation. */
5305 if (i
.tm
.opcode_modifier
.w
)
5307 if (i
.tm
.opcode_modifier
.shortform
)
5308 i
.tm
.base_opcode
|= 8;
5310 i
.tm
.base_opcode
|= 1;
5313 /* Now select between word & dword operations via the operand
5314 size prefix, except for instructions that will ignore this
5316 if (i
.tm
.opcode_modifier
.addrprefixop0
)
5318 /* The address size override prefix changes the size of the
5320 if ((flag_code
== CODE_32BIT
5321 && i
.op
->regs
[0].reg_type
.bitfield
.reg16
)
5322 || (flag_code
!= CODE_32BIT
5323 && i
.op
->regs
[0].reg_type
.bitfield
.reg32
))
5324 if (!add_prefix (ADDR_PREFIX_OPCODE
))
5327 else if (i
.suffix
!= QWORD_MNEM_SUFFIX
5328 && i
.suffix
!= LONG_DOUBLE_MNEM_SUFFIX
5329 && !i
.tm
.opcode_modifier
.ignoresize
5330 && !i
.tm
.opcode_modifier
.floatmf
5331 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
5332 || (flag_code
== CODE_64BIT
5333 && i
.tm
.opcode_modifier
.jumpbyte
)))
5335 unsigned int prefix
= DATA_PREFIX_OPCODE
;
5337 if (i
.tm
.opcode_modifier
.jumpbyte
) /* jcxz, loop */
5338 prefix
= ADDR_PREFIX_OPCODE
;
5340 if (!add_prefix (prefix
))
5344 /* Set mode64 for an operand. */
5345 if (i
.suffix
== QWORD_MNEM_SUFFIX
5346 && flag_code
== CODE_64BIT
5347 && !i
.tm
.opcode_modifier
.norex64
)
5349 /* Special case for xchg %rax,%rax. It is NOP and doesn't
5350 need rex64. cmpxchg8b is also a special case. */
5351 if (! (i
.operands
== 2
5352 && i
.tm
.base_opcode
== 0x90
5353 && i
.tm
.extension_opcode
== None
5354 && operand_type_equal (&i
.types
[0], &acc64
)
5355 && operand_type_equal (&i
.types
[1], &acc64
))
5356 && ! (i
.operands
== 1
5357 && i
.tm
.base_opcode
== 0xfc7
5358 && i
.tm
.extension_opcode
== 1
5359 && !operand_type_check (i
.types
[0], reg
)
5360 && operand_type_check (i
.types
[0], anymem
)))
5364 /* Size floating point instruction. */
5365 if (i
.suffix
== LONG_MNEM_SUFFIX
)
5366 if (i
.tm
.opcode_modifier
.floatmf
)
5367 i
.tm
.base_opcode
^= 4;
5374 check_byte_reg (void)
5378 for (op
= i
.operands
; --op
>= 0;)
5380 /* If this is an eight bit register, it's OK. If it's the 16 or
5381 32 bit version of an eight bit register, we will just use the
5382 low portion, and that's OK too. */
5383 if (i
.types
[op
].bitfield
.reg8
)
5386 /* I/O port address operands are OK too. */
5387 if (i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
5390 /* crc32 doesn't generate this warning. */
5391 if (i
.tm
.base_opcode
== 0xf20f38f0)
5394 if ((i
.types
[op
].bitfield
.reg16
5395 || i
.types
[op
].bitfield
.reg32
5396 || i
.types
[op
].bitfield
.reg64
)
5397 && i
.op
[op
].regs
->reg_num
< 4
5398 /* Prohibit these changes in 64bit mode, since the lowering
5399 would be more complicated. */
5400 && flag_code
!= CODE_64BIT
)
5402 #if REGISTER_WARNINGS
5403 if (!quiet_warnings
)
5404 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5406 (i
.op
[op
].regs
+ (i
.types
[op
].bitfield
.reg16
5407 ? REGNAM_AL
- REGNAM_AX
5408 : REGNAM_AL
- REGNAM_EAX
))->reg_name
,
5410 i
.op
[op
].regs
->reg_name
,
5415 /* Any other register is bad. */
5416 if (i
.types
[op
].bitfield
.reg16
5417 || i
.types
[op
].bitfield
.reg32
5418 || i
.types
[op
].bitfield
.reg64
5419 || i
.types
[op
].bitfield
.regmmx
5420 || i
.types
[op
].bitfield
.regxmm
5421 || i
.types
[op
].bitfield
.regymm
5422 || i
.types
[op
].bitfield
.regzmm
5423 || i
.types
[op
].bitfield
.sreg2
5424 || i
.types
[op
].bitfield
.sreg3
5425 || i
.types
[op
].bitfield
.control
5426 || i
.types
[op
].bitfield
.debug
5427 || i
.types
[op
].bitfield
.test
5428 || i
.types
[op
].bitfield
.floatreg
5429 || i
.types
[op
].bitfield
.floatacc
)
5431 as_bad (_("`%s%s' not allowed with `%s%c'"),
5433 i
.op
[op
].regs
->reg_name
,
5443 check_long_reg (void)
5447 for (op
= i
.operands
; --op
>= 0;)
5448 /* Reject eight bit registers, except where the template requires
5449 them. (eg. movzb) */
5450 if (i
.types
[op
].bitfield
.reg8
5451 && (i
.tm
.operand_types
[op
].bitfield
.reg16
5452 || i
.tm
.operand_types
[op
].bitfield
.reg32
5453 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5455 as_bad (_("`%s%s' not allowed with `%s%c'"),
5457 i
.op
[op
].regs
->reg_name
,
5462 /* Warn if the e prefix on a general reg is missing. */
5463 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
5464 && i
.types
[op
].bitfield
.reg16
5465 && (i
.tm
.operand_types
[op
].bitfield
.reg32
5466 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5468 /* Prohibit these changes in the 64bit mode, since the
5469 lowering is more complicated. */
5470 if (flag_code
== CODE_64BIT
)
5472 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5473 register_prefix
, i
.op
[op
].regs
->reg_name
,
5477 #if REGISTER_WARNINGS
5478 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5480 (i
.op
[op
].regs
+ REGNAM_EAX
- REGNAM_AX
)->reg_name
,
5481 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
5484 /* Warn if the r prefix on a general reg is present. */
5485 else if (i
.types
[op
].bitfield
.reg64
5486 && (i
.tm
.operand_types
[op
].bitfield
.reg32
5487 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5490 && i
.tm
.opcode_modifier
.toqword
5491 && !i
.types
[0].bitfield
.regxmm
)
5493 /* Convert to QWORD. We want REX byte. */
5494 i
.suffix
= QWORD_MNEM_SUFFIX
;
5498 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5499 register_prefix
, i
.op
[op
].regs
->reg_name
,
5508 check_qword_reg (void)
5512 for (op
= i
.operands
; --op
>= 0; )
5513 /* Reject eight bit registers, except where the template requires
5514 them. (eg. movzb) */
5515 if (i
.types
[op
].bitfield
.reg8
5516 && (i
.tm
.operand_types
[op
].bitfield
.reg16
5517 || i
.tm
.operand_types
[op
].bitfield
.reg32
5518 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5520 as_bad (_("`%s%s' not allowed with `%s%c'"),
5522 i
.op
[op
].regs
->reg_name
,
5527 /* Warn if the r prefix on a general reg is missing. */
5528 else if ((i
.types
[op
].bitfield
.reg16
5529 || i
.types
[op
].bitfield
.reg32
)
5530 && (i
.tm
.operand_types
[op
].bitfield
.reg32
5531 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5533 /* Prohibit these changes in the 64bit mode, since the
5534 lowering is more complicated. */
5536 && i
.tm
.opcode_modifier
.todword
5537 && !i
.types
[0].bitfield
.regxmm
)
5539 /* Convert to DWORD. We don't want REX byte. */
5540 i
.suffix
= LONG_MNEM_SUFFIX
;
5544 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5545 register_prefix
, i
.op
[op
].regs
->reg_name
,
5554 check_word_reg (void)
5557 for (op
= i
.operands
; --op
>= 0;)
5558 /* Reject eight bit registers, except where the template requires
5559 them. (eg. movzb) */
5560 if (i
.types
[op
].bitfield
.reg8
5561 && (i
.tm
.operand_types
[op
].bitfield
.reg16
5562 || i
.tm
.operand_types
[op
].bitfield
.reg32
5563 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5565 as_bad (_("`%s%s' not allowed with `%s%c'"),
5567 i
.op
[op
].regs
->reg_name
,
5572 /* Warn if the e or r prefix on a general reg is present. */
5573 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
5574 && (i
.types
[op
].bitfield
.reg32
5575 || i
.types
[op
].bitfield
.reg64
)
5576 && (i
.tm
.operand_types
[op
].bitfield
.reg16
5577 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5579 /* Prohibit these changes in the 64bit mode, since the
5580 lowering is more complicated. */
5581 if (flag_code
== CODE_64BIT
)
5583 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5584 register_prefix
, i
.op
[op
].regs
->reg_name
,
5588 #if REGISTER_WARNINGS
5589 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5591 (i
.op
[op
].regs
+ REGNAM_AX
- REGNAM_EAX
)->reg_name
,
5592 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
5599 update_imm (unsigned int j
)
5601 i386_operand_type overlap
= i
.types
[j
];
5602 if ((overlap
.bitfield
.imm8
5603 || overlap
.bitfield
.imm8s
5604 || overlap
.bitfield
.imm16
5605 || overlap
.bitfield
.imm32
5606 || overlap
.bitfield
.imm32s
5607 || overlap
.bitfield
.imm64
)
5608 && !operand_type_equal (&overlap
, &imm8
)
5609 && !operand_type_equal (&overlap
, &imm8s
)
5610 && !operand_type_equal (&overlap
, &imm16
)
5611 && !operand_type_equal (&overlap
, &imm32
)
5612 && !operand_type_equal (&overlap
, &imm32s
)
5613 && !operand_type_equal (&overlap
, &imm64
))
5617 i386_operand_type temp
;
5619 operand_type_set (&temp
, 0);
5620 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
5622 temp
.bitfield
.imm8
= overlap
.bitfield
.imm8
;
5623 temp
.bitfield
.imm8s
= overlap
.bitfield
.imm8s
;
5625 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
5626 temp
.bitfield
.imm16
= overlap
.bitfield
.imm16
;
5627 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
5629 temp
.bitfield
.imm64
= overlap
.bitfield
.imm64
;
5630 temp
.bitfield
.imm32s
= overlap
.bitfield
.imm32s
;
5633 temp
.bitfield
.imm32
= overlap
.bitfield
.imm32
;
5636 else if (operand_type_equal (&overlap
, &imm16_32_32s
)
5637 || operand_type_equal (&overlap
, &imm16_32
)
5638 || operand_type_equal (&overlap
, &imm16_32s
))
5640 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
5645 if (!operand_type_equal (&overlap
, &imm8
)
5646 && !operand_type_equal (&overlap
, &imm8s
)
5647 && !operand_type_equal (&overlap
, &imm16
)
5648 && !operand_type_equal (&overlap
, &imm32
)
5649 && !operand_type_equal (&overlap
, &imm32s
)
5650 && !operand_type_equal (&overlap
, &imm64
))
5652 as_bad (_("no instruction mnemonic suffix given; "
5653 "can't determine immediate size"));
5657 i
.types
[j
] = overlap
;
5667 /* Update the first 2 immediate operands. */
5668 n
= i
.operands
> 2 ? 2 : i
.operands
;
5671 for (j
= 0; j
< n
; j
++)
5672 if (update_imm (j
) == 0)
5675 /* The 3rd operand can't be immediate operand. */
5676 gas_assert (operand_type_check (i
.types
[2], imm
) == 0);
5683 bad_implicit_operand (int xmm
)
5685 const char *ireg
= xmm
? "xmm0" : "ymm0";
5688 as_bad (_("the last operand of `%s' must be `%s%s'"),
5689 i
.tm
.name
, register_prefix
, ireg
);
5691 as_bad (_("the first operand of `%s' must be `%s%s'"),
5692 i
.tm
.name
, register_prefix
, ireg
);
5697 process_operands (void)
5699 /* Default segment register this instruction will use for memory
5700 accesses. 0 means unknown. This is only for optimizing out
5701 unnecessary segment overrides. */
5702 const seg_entry
*default_seg
= 0;
5704 if (i
.tm
.opcode_modifier
.sse2avx
&& i
.tm
.opcode_modifier
.vexvvvv
)
5706 unsigned int dupl
= i
.operands
;
5707 unsigned int dest
= dupl
- 1;
5710 /* The destination must be an xmm register. */
5711 gas_assert (i
.reg_operands
5712 && MAX_OPERANDS
> dupl
5713 && operand_type_equal (&i
.types
[dest
], ®xmm
));
5715 if (i
.tm
.opcode_modifier
.firstxmm0
)
5717 /* The first operand is implicit and must be xmm0. */
5718 gas_assert (operand_type_equal (&i
.types
[0], ®xmm
));
5719 if (register_number (i
.op
[0].regs
) != 0)
5720 return bad_implicit_operand (1);
5722 if (i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
)
5724 /* Keep xmm0 for instructions with VEX prefix and 3
5730 /* We remove the first xmm0 and keep the number of
5731 operands unchanged, which in fact duplicates the
5733 for (j
= 1; j
< i
.operands
; j
++)
5735 i
.op
[j
- 1] = i
.op
[j
];
5736 i
.types
[j
- 1] = i
.types
[j
];
5737 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
5741 else if (i
.tm
.opcode_modifier
.implicit1stxmm0
)
5743 gas_assert ((MAX_OPERANDS
- 1) > dupl
5744 && (i
.tm
.opcode_modifier
.vexsources
5747 /* Add the implicit xmm0 for instructions with VEX prefix
5749 for (j
= i
.operands
; j
> 0; j
--)
5751 i
.op
[j
] = i
.op
[j
- 1];
5752 i
.types
[j
] = i
.types
[j
- 1];
5753 i
.tm
.operand_types
[j
] = i
.tm
.operand_types
[j
- 1];
5756 = (const reg_entry
*) hash_find (reg_hash
, "xmm0");
5757 i
.types
[0] = regxmm
;
5758 i
.tm
.operand_types
[0] = regxmm
;
5761 i
.reg_operands
+= 2;
5766 i
.op
[dupl
] = i
.op
[dest
];
5767 i
.types
[dupl
] = i
.types
[dest
];
5768 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
5777 i
.op
[dupl
] = i
.op
[dest
];
5778 i
.types
[dupl
] = i
.types
[dest
];
5779 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
5782 if (i
.tm
.opcode_modifier
.immext
)
5785 else if (i
.tm
.opcode_modifier
.firstxmm0
)
5789 /* The first operand is implicit and must be xmm0/ymm0/zmm0. */
5790 gas_assert (i
.reg_operands
5791 && (operand_type_equal (&i
.types
[0], ®xmm
)
5792 || operand_type_equal (&i
.types
[0], ®ymm
)
5793 || operand_type_equal (&i
.types
[0], ®zmm
)));
5794 if (register_number (i
.op
[0].regs
) != 0)
5795 return bad_implicit_operand (i
.types
[0].bitfield
.regxmm
);
5797 for (j
= 1; j
< i
.operands
; j
++)
5799 i
.op
[j
- 1] = i
.op
[j
];
5800 i
.types
[j
- 1] = i
.types
[j
];
5802 /* We need to adjust fields in i.tm since they are used by
5803 build_modrm_byte. */
5804 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
5811 else if (i
.tm
.opcode_modifier
.regkludge
)
5813 /* The imul $imm, %reg instruction is converted into
5814 imul $imm, %reg, %reg, and the clr %reg instruction
5815 is converted into xor %reg, %reg. */
5817 unsigned int first_reg_op
;
5819 if (operand_type_check (i
.types
[0], reg
))
5823 /* Pretend we saw the extra register operand. */
5824 gas_assert (i
.reg_operands
== 1
5825 && i
.op
[first_reg_op
+ 1].regs
== 0);
5826 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
5827 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
5832 if (i
.tm
.opcode_modifier
.shortform
)
5834 if (i
.types
[0].bitfield
.sreg2
5835 || i
.types
[0].bitfield
.sreg3
)
5837 if (i
.tm
.base_opcode
== POP_SEG_SHORT
5838 && i
.op
[0].regs
->reg_num
== 1)
5840 as_bad (_("you can't `pop %scs'"), register_prefix
);
5843 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
5844 if ((i
.op
[0].regs
->reg_flags
& RegRex
) != 0)
5849 /* The register or float register operand is in operand
5853 if (i
.types
[0].bitfield
.floatreg
5854 || operand_type_check (i
.types
[0], reg
))
5858 /* Register goes in low 3 bits of opcode. */
5859 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
5860 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
5862 if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
5864 /* Warn about some common errors, but press on regardless.
5865 The first case can be generated by gcc (<= 2.8.1). */
5866 if (i
.operands
== 2)
5868 /* Reversed arguments on faddp, fsubp, etc. */
5869 as_warn (_("translating to `%s %s%s,%s%s'"), i
.tm
.name
,
5870 register_prefix
, i
.op
[!intel_syntax
].regs
->reg_name
,
5871 register_prefix
, i
.op
[intel_syntax
].regs
->reg_name
);
5875 /* Extraneous `l' suffix on fp insn. */
5876 as_warn (_("translating to `%s %s%s'"), i
.tm
.name
,
5877 register_prefix
, i
.op
[0].regs
->reg_name
);
5882 else if (i
.tm
.opcode_modifier
.modrm
)
5884 /* The opcode is completed (modulo i.tm.extension_opcode which
5885 must be put into the modrm byte). Now, we make the modrm and
5886 index base bytes based on all the info we've collected. */
5888 default_seg
= build_modrm_byte ();
5890 else if ((i
.tm
.base_opcode
& ~0x3) == MOV_AX_DISP32
)
5894 else if (i
.tm
.opcode_modifier
.isstring
)
5896 /* For the string instructions that allow a segment override
5897 on one of their operands, the default segment is ds. */
5901 if (i
.tm
.base_opcode
== 0x8d /* lea */
5904 as_warn (_("segment override on `%s' is ineffectual"), i
.tm
.name
);
5906 /* If a segment was explicitly specified, and the specified segment
5907 is not the default, use an opcode prefix to select it. If we
5908 never figured out what the default segment is, then default_seg
5909 will be zero at this point, and the specified segment prefix will
5911 if ((i
.seg
[0]) && (i
.seg
[0] != default_seg
))
5913 if (!add_prefix (i
.seg
[0]->seg_prefix
))
5919 static const seg_entry
*
5920 build_modrm_byte (void)
5922 const seg_entry
*default_seg
= 0;
5923 unsigned int source
, dest
;
5926 /* The first operand of instructions with VEX prefix and 3 sources
5927 must be VEX_Imm4. */
5928 vex_3_sources
= i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
;
5931 unsigned int nds
, reg_slot
;
5934 if (i
.tm
.opcode_modifier
.veximmext
5935 && i
.tm
.opcode_modifier
.immext
)
5937 dest
= i
.operands
- 2;
5938 gas_assert (dest
== 3);
5941 dest
= i
.operands
- 1;
5944 /* There are 2 kinds of instructions:
5945 1. 5 operands: 4 register operands or 3 register operands
5946 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
5947 VexW0 or VexW1. The destination must be either XMM, YMM or
5949 2. 4 operands: 4 register operands or 3 register operands
5950 plus 1 memory operand, VexXDS, and VexImmExt */
5951 gas_assert ((i
.reg_operands
== 4
5952 || (i
.reg_operands
== 3 && i
.mem_operands
== 1))
5953 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
5954 && (i
.tm
.opcode_modifier
.veximmext
5955 || (i
.imm_operands
== 1
5956 && i
.types
[0].bitfield
.vec_imm4
5957 && (i
.tm
.opcode_modifier
.vexw
== VEXW0
5958 || i
.tm
.opcode_modifier
.vexw
== VEXW1
)
5959 && (operand_type_equal (&i
.tm
.operand_types
[dest
], ®xmm
)
5960 || operand_type_equal (&i
.tm
.operand_types
[dest
], ®ymm
)
5961 || operand_type_equal (&i
.tm
.operand_types
[dest
], ®zmm
)))));
5963 if (i
.imm_operands
== 0)
5965 /* When there is no immediate operand, generate an 8bit
5966 immediate operand to encode the first operand. */
5967 exp
= &im_expressions
[i
.imm_operands
++];
5968 i
.op
[i
.operands
].imms
= exp
;
5969 i
.types
[i
.operands
] = imm8
;
5971 /* If VexW1 is set, the first operand is the source and
5972 the second operand is encoded in the immediate operand. */
5973 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
5984 /* FMA swaps REG and NDS. */
5985 if (i
.tm
.cpu_flags
.bitfield
.cpufma
)
5993 gas_assert (operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
5995 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
5997 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
5999 exp
->X_op
= O_constant
;
6000 exp
->X_add_number
= register_number (i
.op
[reg_slot
].regs
) << 4;
6001 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
6005 unsigned int imm_slot
;
6007 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
6009 /* If VexW0 is set, the third operand is the source and
6010 the second operand is encoded in the immediate
6017 /* VexW1 is set, the second operand is the source and
6018 the third operand is encoded in the immediate
6024 if (i
.tm
.opcode_modifier
.immext
)
6026 /* When ImmExt is set, the immdiate byte is the last
6028 imm_slot
= i
.operands
- 1;
6036 /* Turn on Imm8 so that output_imm will generate it. */
6037 i
.types
[imm_slot
].bitfield
.imm8
= 1;
6040 gas_assert (operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6042 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6044 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6046 i
.op
[imm_slot
].imms
->X_add_number
6047 |= register_number (i
.op
[reg_slot
].regs
) << 4;
6048 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
6051 gas_assert (operand_type_equal (&i
.tm
.operand_types
[nds
], ®xmm
)
6052 || operand_type_equal (&i
.tm
.operand_types
[nds
],
6054 || operand_type_equal (&i
.tm
.operand_types
[nds
],
6056 i
.vex
.register_specifier
= i
.op
[nds
].regs
;
6061 /* i.reg_operands MUST be the number of real register operands;
6062 implicit registers do not count. If there are 3 register
6063 operands, it must be a instruction with VexNDS. For a
6064 instruction with VexNDD, the destination register is encoded
6065 in VEX prefix. If there are 4 register operands, it must be
6066 a instruction with VEX prefix and 3 sources. */
6067 if (i
.mem_operands
== 0
6068 && ((i
.reg_operands
== 2
6069 && i
.tm
.opcode_modifier
.vexvvvv
<= VEXXDS
)
6070 || (i
.reg_operands
== 3
6071 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
6072 || (i
.reg_operands
== 4 && vex_3_sources
)))
6080 /* When there are 3 operands, one of them may be immediate,
6081 which may be the first or the last operand. Otherwise,
6082 the first operand must be shift count register (cl) or it
6083 is an instruction with VexNDS. */
6084 gas_assert (i
.imm_operands
== 1
6085 || (i
.imm_operands
== 0
6086 && (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
6087 || i
.types
[0].bitfield
.shiftcount
)));
6088 if (operand_type_check (i
.types
[0], imm
)
6089 || i
.types
[0].bitfield
.shiftcount
)
6095 /* When there are 4 operands, the first two must be 8bit
6096 immediate operands. The source operand will be the 3rd
6099 For instructions with VexNDS, if the first operand
6100 an imm8, the source operand is the 2nd one. If the last
6101 operand is imm8, the source operand is the first one. */
6102 gas_assert ((i
.imm_operands
== 2
6103 && i
.types
[0].bitfield
.imm8
6104 && i
.types
[1].bitfield
.imm8
)
6105 || (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
6106 && i
.imm_operands
== 1
6107 && (i
.types
[0].bitfield
.imm8
6108 || i
.types
[i
.operands
- 1].bitfield
.imm8
6110 if (i
.imm_operands
== 2)
6114 if (i
.types
[0].bitfield
.imm8
)
6121 if (i
.tm
.opcode_modifier
.evex
)
6123 /* For EVEX instructions, when there are 5 operands, the
6124 first one must be immediate operand. If the second one
6125 is immediate operand, the source operand is the 3th
6126 one. If the last one is immediate operand, the source
6127 operand is the 2nd one. */
6128 gas_assert (i
.imm_operands
== 2
6129 && i
.tm
.opcode_modifier
.sae
6130 && operand_type_check (i
.types
[0], imm
));
6131 if (operand_type_check (i
.types
[1], imm
))
6133 else if (operand_type_check (i
.types
[4], imm
))
6147 /* RC/SAE operand could be between DEST and SRC. That happens
6148 when one operand is GPR and the other one is XMM/YMM/ZMM
6150 if (i
.rounding
&& i
.rounding
->operand
== (int) dest
)
6153 if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
6155 /* For instructions with VexNDS, the register-only source
6156 operand must be 32/64bit integer, XMM, YMM or ZMM
6157 register. It is encoded in VEX prefix. We need to
6158 clear RegMem bit before calling operand_type_equal. */
6160 i386_operand_type op
;
6163 /* Check register-only source operand when two source
6164 operands are swapped. */
6165 if (!i
.tm
.operand_types
[source
].bitfield
.baseindex
6166 && i
.tm
.operand_types
[dest
].bitfield
.baseindex
)
6174 op
= i
.tm
.operand_types
[vvvv
];
6175 op
.bitfield
.regmem
= 0;
6176 if ((dest
+ 1) >= i
.operands
6177 || (!op
.bitfield
.reg32
6178 && op
.bitfield
.reg64
6179 && !operand_type_equal (&op
, ®xmm
)
6180 && !operand_type_equal (&op
, ®ymm
)
6181 && !operand_type_equal (&op
, ®zmm
)
6182 && !operand_type_equal (&op
, ®mask
)))
6184 i
.vex
.register_specifier
= i
.op
[vvvv
].regs
;
6190 /* One of the register operands will be encoded in the i.tm.reg
6191 field, the other in the combined i.tm.mode and i.tm.regmem
6192 fields. If no form of this instruction supports a memory
6193 destination operand, then we assume the source operand may
6194 sometimes be a memory operand and so we need to store the
6195 destination in the i.rm.reg field. */
6196 if (!i
.tm
.operand_types
[dest
].bitfield
.regmem
6197 && operand_type_check (i
.tm
.operand_types
[dest
], anymem
) == 0)
6199 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
6200 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
6201 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
6203 if ((i
.op
[dest
].regs
->reg_flags
& RegVRex
) != 0)
6205 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
6207 if ((i
.op
[source
].regs
->reg_flags
& RegVRex
) != 0)
6212 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
6213 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
6214 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
6216 if ((i
.op
[dest
].regs
->reg_flags
& RegVRex
) != 0)
6218 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
6220 if ((i
.op
[source
].regs
->reg_flags
& RegVRex
) != 0)
6223 if (flag_code
!= CODE_64BIT
&& (i
.rex
& (REX_R
| REX_B
)))
6225 if (!i
.types
[0].bitfield
.control
6226 && !i
.types
[1].bitfield
.control
)
6228 i
.rex
&= ~(REX_R
| REX_B
);
6229 add_prefix (LOCK_PREFIX_OPCODE
);
6233 { /* If it's not 2 reg operands... */
6238 unsigned int fake_zero_displacement
= 0;
6241 for (op
= 0; op
< i
.operands
; op
++)
6242 if (operand_type_check (i
.types
[op
], anymem
))
6244 gas_assert (op
< i
.operands
);
6246 if (i
.tm
.opcode_modifier
.vecsib
)
6248 if (i
.index_reg
->reg_num
== RegEiz
6249 || i
.index_reg
->reg_num
== RegRiz
)
6252 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6255 i
.sib
.base
= NO_BASE_REGISTER
;
6256 i
.sib
.scale
= i
.log2_scale_factor
;
6257 /* No Vec_Disp8 if there is no base. */
6258 i
.types
[op
].bitfield
.vec_disp8
= 0;
6259 i
.types
[op
].bitfield
.disp8
= 0;
6260 i
.types
[op
].bitfield
.disp16
= 0;
6261 i
.types
[op
].bitfield
.disp64
= 0;
6262 if (flag_code
!= CODE_64BIT
)
6264 /* Must be 32 bit */
6265 i
.types
[op
].bitfield
.disp32
= 1;
6266 i
.types
[op
].bitfield
.disp32s
= 0;
6270 i
.types
[op
].bitfield
.disp32
= 0;
6271 i
.types
[op
].bitfield
.disp32s
= 1;
6274 i
.sib
.index
= i
.index_reg
->reg_num
;
6275 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
6277 if ((i
.index_reg
->reg_flags
& RegVRex
) != 0)
6283 if (i
.base_reg
== 0)
6286 if (!i
.disp_operands
)
6288 fake_zero_displacement
= 1;
6289 /* Instructions with VSIB byte need 32bit displacement
6290 if there is no base register. */
6291 if (i
.tm
.opcode_modifier
.vecsib
)
6292 i
.types
[op
].bitfield
.disp32
= 1;
6294 if (i
.index_reg
== 0)
6296 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6297 /* Operand is just <disp> */
6298 if (flag_code
== CODE_64BIT
)
6300 /* 64bit mode overwrites the 32bit absolute
6301 addressing by RIP relative addressing and
6302 absolute addressing is encoded by one of the
6303 redundant SIB forms. */
6304 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6305 i
.sib
.base
= NO_BASE_REGISTER
;
6306 i
.sib
.index
= NO_INDEX_REGISTER
;
6307 i
.types
[op
] = ((i
.prefix
[ADDR_PREFIX
] == 0)
6308 ? disp32s
: disp32
);
6310 else if ((flag_code
== CODE_16BIT
)
6311 ^ (i
.prefix
[ADDR_PREFIX
] != 0))
6313 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
6314 i
.types
[op
] = disp16
;
6318 i
.rm
.regmem
= NO_BASE_REGISTER
;
6319 i
.types
[op
] = disp32
;
6322 else if (!i
.tm
.opcode_modifier
.vecsib
)
6324 /* !i.base_reg && i.index_reg */
6325 if (i
.index_reg
->reg_num
== RegEiz
6326 || i
.index_reg
->reg_num
== RegRiz
)
6327 i
.sib
.index
= NO_INDEX_REGISTER
;
6329 i
.sib
.index
= i
.index_reg
->reg_num
;
6330 i
.sib
.base
= NO_BASE_REGISTER
;
6331 i
.sib
.scale
= i
.log2_scale_factor
;
6332 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6333 /* No Vec_Disp8 if there is no base. */
6334 i
.types
[op
].bitfield
.vec_disp8
= 0;
6335 i
.types
[op
].bitfield
.disp8
= 0;
6336 i
.types
[op
].bitfield
.disp16
= 0;
6337 i
.types
[op
].bitfield
.disp64
= 0;
6338 if (flag_code
!= CODE_64BIT
)
6340 /* Must be 32 bit */
6341 i
.types
[op
].bitfield
.disp32
= 1;
6342 i
.types
[op
].bitfield
.disp32s
= 0;
6346 i
.types
[op
].bitfield
.disp32
= 0;
6347 i
.types
[op
].bitfield
.disp32s
= 1;
6349 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
6353 /* RIP addressing for 64bit mode. */
6354 else if (i
.base_reg
->reg_num
== RegRip
||
6355 i
.base_reg
->reg_num
== RegEip
)
6357 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6358 i
.rm
.regmem
= NO_BASE_REGISTER
;
6359 i
.types
[op
].bitfield
.disp8
= 0;
6360 i
.types
[op
].bitfield
.disp16
= 0;
6361 i
.types
[op
].bitfield
.disp32
= 0;
6362 i
.types
[op
].bitfield
.disp32s
= 1;
6363 i
.types
[op
].bitfield
.disp64
= 0;
6364 i
.types
[op
].bitfield
.vec_disp8
= 0;
6365 i
.flags
[op
] |= Operand_PCrel
;
6366 if (! i
.disp_operands
)
6367 fake_zero_displacement
= 1;
6369 else if (i
.base_reg
->reg_type
.bitfield
.reg16
)
6371 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6372 switch (i
.base_reg
->reg_num
)
6375 if (i
.index_reg
== 0)
6377 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
6378 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
6382 if (i
.index_reg
== 0)
6385 if (operand_type_check (i
.types
[op
], disp
) == 0)
6387 /* fake (%bp) into 0(%bp) */
6388 if (i
.tm
.operand_types
[op
].bitfield
.vec_disp8
)
6389 i
.types
[op
].bitfield
.vec_disp8
= 1;
6391 i
.types
[op
].bitfield
.disp8
= 1;
6392 fake_zero_displacement
= 1;
6395 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
6396 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
6398 default: /* (%si) -> 4 or (%di) -> 5 */
6399 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
6401 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
6403 else /* i.base_reg and 32/64 bit mode */
6405 if (flag_code
== CODE_64BIT
6406 && operand_type_check (i
.types
[op
], disp
))
6408 i386_operand_type temp
;
6409 operand_type_set (&temp
, 0);
6410 temp
.bitfield
.disp8
= i
.types
[op
].bitfield
.disp8
;
6411 temp
.bitfield
.vec_disp8
6412 = i
.types
[op
].bitfield
.vec_disp8
;
6414 if (i
.prefix
[ADDR_PREFIX
] == 0)
6415 i
.types
[op
].bitfield
.disp32s
= 1;
6417 i
.types
[op
].bitfield
.disp32
= 1;
6420 if (!i
.tm
.opcode_modifier
.vecsib
)
6421 i
.rm
.regmem
= i
.base_reg
->reg_num
;
6422 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
6424 i
.sib
.base
= i
.base_reg
->reg_num
;
6425 /* x86-64 ignores REX prefix bit here to avoid decoder
6427 if (!(i
.base_reg
->reg_flags
& RegRex
)
6428 && (i
.base_reg
->reg_num
== EBP_REG_NUM
6429 || i
.base_reg
->reg_num
== ESP_REG_NUM
))
6431 if (i
.base_reg
->reg_num
== 5 && i
.disp_operands
== 0)
6433 fake_zero_displacement
= 1;
6434 if (i
.tm
.operand_types
[op
].bitfield
.vec_disp8
)
6435 i
.types
[op
].bitfield
.vec_disp8
= 1;
6437 i
.types
[op
].bitfield
.disp8
= 1;
6439 i
.sib
.scale
= i
.log2_scale_factor
;
6440 if (i
.index_reg
== 0)
6442 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6443 /* <disp>(%esp) becomes two byte modrm with no index
6444 register. We've already stored the code for esp
6445 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
6446 Any base register besides %esp will not use the
6447 extra modrm byte. */
6448 i
.sib
.index
= NO_INDEX_REGISTER
;
6450 else if (!i
.tm
.opcode_modifier
.vecsib
)
6452 if (i
.index_reg
->reg_num
== RegEiz
6453 || i
.index_reg
->reg_num
== RegRiz
)
6454 i
.sib
.index
= NO_INDEX_REGISTER
;
6456 i
.sib
.index
= i
.index_reg
->reg_num
;
6457 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6458 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
6463 && (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
6464 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
))
6468 if (!fake_zero_displacement
6472 fake_zero_displacement
= 1;
6473 if (i
.disp_encoding
== disp_encoding_8bit
)
6474 i
.types
[op
].bitfield
.disp8
= 1;
6476 i
.types
[op
].bitfield
.disp32
= 1;
6478 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
6482 if (fake_zero_displacement
)
6484 /* Fakes a zero displacement assuming that i.types[op]
6485 holds the correct displacement size. */
6488 gas_assert (i
.op
[op
].disps
== 0);
6489 exp
= &disp_expressions
[i
.disp_operands
++];
6490 i
.op
[op
].disps
= exp
;
6491 exp
->X_op
= O_constant
;
6492 exp
->X_add_number
= 0;
6493 exp
->X_add_symbol
= (symbolS
*) 0;
6494 exp
->X_op_symbol
= (symbolS
*) 0;
6502 if (i
.tm
.opcode_modifier
.vexsources
== XOP2SOURCES
)
6504 if (operand_type_check (i
.types
[0], imm
))
6505 i
.vex
.register_specifier
= NULL
;
6508 /* VEX.vvvv encodes one of the sources when the first
6509 operand is not an immediate. */
6510 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
6511 i
.vex
.register_specifier
= i
.op
[0].regs
;
6513 i
.vex
.register_specifier
= i
.op
[1].regs
;
6516 /* Destination is a XMM register encoded in the ModRM.reg
6518 i
.rm
.reg
= i
.op
[2].regs
->reg_num
;
6519 if ((i
.op
[2].regs
->reg_flags
& RegRex
) != 0)
6522 /* ModRM.rm and VEX.B encodes the other source. */
6523 if (!i
.mem_operands
)
6527 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
6528 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
6530 i
.rm
.regmem
= i
.op
[0].regs
->reg_num
;
6532 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
6536 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXLWP
)
6538 i
.vex
.register_specifier
= i
.op
[2].regs
;
6539 if (!i
.mem_operands
)
6542 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
6543 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
6547 /* Fill in i.rm.reg or i.rm.regmem field with register operand
6548 (if any) based on i.tm.extension_opcode. Again, we must be
6549 careful to make sure that segment/control/debug/test/MMX
6550 registers are coded into the i.rm.reg field. */
6551 else if (i
.reg_operands
)
6554 unsigned int vex_reg
= ~0;
6556 for (op
= 0; op
< i
.operands
; op
++)
6557 if (i
.types
[op
].bitfield
.reg8
6558 || i
.types
[op
].bitfield
.reg16
6559 || i
.types
[op
].bitfield
.reg32
6560 || i
.types
[op
].bitfield
.reg64
6561 || i
.types
[op
].bitfield
.regmmx
6562 || i
.types
[op
].bitfield
.regxmm
6563 || i
.types
[op
].bitfield
.regymm
6564 || i
.types
[op
].bitfield
.regbnd
6565 || i
.types
[op
].bitfield
.regzmm
6566 || i
.types
[op
].bitfield
.regmask
6567 || i
.types
[op
].bitfield
.sreg2
6568 || i
.types
[op
].bitfield
.sreg3
6569 || i
.types
[op
].bitfield
.control
6570 || i
.types
[op
].bitfield
.debug
6571 || i
.types
[op
].bitfield
.test
)
6576 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
6578 /* For instructions with VexNDS, the register-only
6579 source operand is encoded in VEX prefix. */
6580 gas_assert (mem
!= (unsigned int) ~0);
6585 gas_assert (op
< i
.operands
);
6589 /* Check register-only source operand when two source
6590 operands are swapped. */
6591 if (!i
.tm
.operand_types
[op
].bitfield
.baseindex
6592 && i
.tm
.operand_types
[op
+ 1].bitfield
.baseindex
)
6596 gas_assert (mem
== (vex_reg
+ 1)
6597 && op
< i
.operands
);
6602 gas_assert (vex_reg
< i
.operands
);
6606 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXNDD
)
6608 /* For instructions with VexNDD, the register destination
6609 is encoded in VEX prefix. */
6610 if (i
.mem_operands
== 0)
6612 /* There is no memory operand. */
6613 gas_assert ((op
+ 2) == i
.operands
);
6618 /* There are only 2 operands. */
6619 gas_assert (op
< 2 && i
.operands
== 2);
6624 gas_assert (op
< i
.operands
);
6626 if (vex_reg
!= (unsigned int) ~0)
6628 i386_operand_type
*type
= &i
.tm
.operand_types
[vex_reg
];
6630 if (type
->bitfield
.reg32
!= 1
6631 && type
->bitfield
.reg64
!= 1
6632 && !operand_type_equal (type
, ®xmm
)
6633 && !operand_type_equal (type
, ®ymm
)
6634 && !operand_type_equal (type
, ®zmm
)
6635 && !operand_type_equal (type
, ®mask
))
6638 i
.vex
.register_specifier
= i
.op
[vex_reg
].regs
;
6641 /* Don't set OP operand twice. */
6644 /* If there is an extension opcode to put here, the
6645 register number must be put into the regmem field. */
6646 if (i
.tm
.extension_opcode
!= None
)
6648 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
6649 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
6651 if ((i
.op
[op
].regs
->reg_flags
& RegVRex
) != 0)
6656 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
6657 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
6659 if ((i
.op
[op
].regs
->reg_flags
& RegVRex
) != 0)
6664 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
6665 must set it to 3 to indicate this is a register operand
6666 in the regmem field. */
6667 if (!i
.mem_operands
)
6671 /* Fill in i.rm.reg field with extension opcode (if any). */
6672 if (i
.tm
.extension_opcode
!= None
)
6673 i
.rm
.reg
= i
.tm
.extension_opcode
;
6679 output_branch (void)
6685 relax_substateT subtype
;
6689 code16
= flag_code
== CODE_16BIT
? CODE16
: 0;
6690 size
= i
.disp_encoding
== disp_encoding_32bit
? BIG
: SMALL
;
6693 if (i
.prefix
[DATA_PREFIX
] != 0)
6699 /* Pentium4 branch hints. */
6700 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
6701 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
6706 if (i
.prefix
[REX_PREFIX
] != 0)
6712 /* BND prefixed jump. */
6713 if (i
.prefix
[BND_PREFIX
] != 0)
6715 FRAG_APPEND_1_CHAR (i
.prefix
[BND_PREFIX
]);
6719 if (i
.prefixes
!= 0 && !intel_syntax
)
6720 as_warn (_("skipping prefixes on this instruction"));
6722 /* It's always a symbol; End frag & setup for relax.
6723 Make sure there is enough room in this frag for the largest
6724 instruction we may generate in md_convert_frag. This is 2
6725 bytes for the opcode and room for the prefix and largest
6727 frag_grow (prefix
+ 2 + 4);
6728 /* Prefix and 1 opcode byte go in fr_fix. */
6729 p
= frag_more (prefix
+ 1);
6730 if (i
.prefix
[DATA_PREFIX
] != 0)
6731 *p
++ = DATA_PREFIX_OPCODE
;
6732 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
6733 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
6734 *p
++ = i
.prefix
[SEG_PREFIX
];
6735 if (i
.prefix
[REX_PREFIX
] != 0)
6736 *p
++ = i
.prefix
[REX_PREFIX
];
6737 *p
= i
.tm
.base_opcode
;
6739 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
6740 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, size
);
6741 else if (cpu_arch_flags
.bitfield
.cpui386
)
6742 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, size
);
6744 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, size
);
6747 sym
= i
.op
[0].disps
->X_add_symbol
;
6748 off
= i
.op
[0].disps
->X_add_number
;
6750 if (i
.op
[0].disps
->X_op
!= O_constant
6751 && i
.op
[0].disps
->X_op
!= O_symbol
)
6753 /* Handle complex expressions. */
6754 sym
= make_expr_symbol (i
.op
[0].disps
);
6758 /* 1 possible extra opcode + 4 byte displacement go in var part.
6759 Pass reloc in fr_var. */
6760 frag_var (rs_machine_dependent
, 5,
6762 || i
.reloc
[0] != NO_RELOC
6763 || (i
.bnd_prefix
== NULL
&& !add_bnd_prefix
))
6765 : BFD_RELOC_X86_64_PC32_BND
),
6766 subtype
, sym
, off
, p
);
6776 if (i
.tm
.opcode_modifier
.jumpbyte
)
6778 /* This is a loop or jecxz type instruction. */
6780 if (i
.prefix
[ADDR_PREFIX
] != 0)
6782 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
6785 /* Pentium4 branch hints. */
6786 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
6787 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
6789 FRAG_APPEND_1_CHAR (i
.prefix
[SEG_PREFIX
]);
6798 if (flag_code
== CODE_16BIT
)
6801 if (i
.prefix
[DATA_PREFIX
] != 0)
6803 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
6813 if (i
.prefix
[REX_PREFIX
] != 0)
6815 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
6819 /* BND prefixed jump. */
6820 if (i
.prefix
[BND_PREFIX
] != 0)
6822 FRAG_APPEND_1_CHAR (i
.prefix
[BND_PREFIX
]);
6826 if (i
.prefixes
!= 0 && !intel_syntax
)
6827 as_warn (_("skipping prefixes on this instruction"));
6829 p
= frag_more (i
.tm
.opcode_length
+ size
);
6830 switch (i
.tm
.opcode_length
)
6833 *p
++ = i
.tm
.base_opcode
>> 8;
6835 *p
++ = i
.tm
.base_opcode
;
6841 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
6842 i
.op
[0].disps
, 1, reloc (size
, 1, 1,
6843 (i
.bnd_prefix
!= NULL
6847 /* All jumps handled here are signed, but don't use a signed limit
6848 check for 32 and 16 bit jumps as we want to allow wrap around at
6849 4G and 64k respectively. */
6851 fixP
->fx_signed
= 1;
6855 output_interseg_jump (void)
6863 if (flag_code
== CODE_16BIT
)
6867 if (i
.prefix
[DATA_PREFIX
] != 0)
6873 if (i
.prefix
[REX_PREFIX
] != 0)
6883 if (i
.prefixes
!= 0 && !intel_syntax
)
6884 as_warn (_("skipping prefixes on this instruction"));
6886 /* 1 opcode; 2 segment; offset */
6887 p
= frag_more (prefix
+ 1 + 2 + size
);
6889 if (i
.prefix
[DATA_PREFIX
] != 0)
6890 *p
++ = DATA_PREFIX_OPCODE
;
6892 if (i
.prefix
[REX_PREFIX
] != 0)
6893 *p
++ = i
.prefix
[REX_PREFIX
];
6895 *p
++ = i
.tm
.base_opcode
;
6896 if (i
.op
[1].imms
->X_op
== O_constant
)
6898 offsetT n
= i
.op
[1].imms
->X_add_number
;
6901 && !fits_in_unsigned_word (n
)
6902 && !fits_in_signed_word (n
))
6904 as_bad (_("16-bit jump out of range"));
6907 md_number_to_chars (p
, n
, size
);
6910 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
6911 i
.op
[1].imms
, 0, reloc (size
, 0, 0, 0, i
.reloc
[1]));
6912 if (i
.op
[0].imms
->X_op
!= O_constant
)
6913 as_bad (_("can't handle non absolute segment in `%s'"),
6915 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
6921 fragS
*insn_start_frag
;
6922 offsetT insn_start_off
;
6924 /* Tie dwarf2 debug info to the address at the start of the insn.
6925 We can't do this after the insn has been output as the current
6926 frag may have been closed off. eg. by frag_var. */
6927 dwarf2_emit_insn (0);
6929 insn_start_frag
= frag_now
;
6930 insn_start_off
= frag_now_fix ();
6933 if (i
.tm
.opcode_modifier
.jump
)
6935 else if (i
.tm
.opcode_modifier
.jumpbyte
6936 || i
.tm
.opcode_modifier
.jumpdword
)
6938 else if (i
.tm
.opcode_modifier
.jumpintersegment
)
6939 output_interseg_jump ();
6942 /* Output normal instructions here. */
6946 unsigned int prefix
;
6948 /* Some processors fail on LOCK prefix. This options makes
6949 assembler ignore LOCK prefix and serves as a workaround. */
6950 if (omit_lock_prefix
)
6952 if (i
.tm
.base_opcode
== LOCK_PREFIX_OPCODE
)
6954 i
.prefix
[LOCK_PREFIX
] = 0;
6957 /* Since the VEX/EVEX prefix contains the implicit prefix, we
6958 don't need the explicit prefix. */
6959 if (!i
.tm
.opcode_modifier
.vex
&& !i
.tm
.opcode_modifier
.evex
)
6961 switch (i
.tm
.opcode_length
)
6964 if (i
.tm
.base_opcode
& 0xff000000)
6966 prefix
= (i
.tm
.base_opcode
>> 24) & 0xff;
6971 if ((i
.tm
.base_opcode
& 0xff0000) != 0)
6973 prefix
= (i
.tm
.base_opcode
>> 16) & 0xff;
6974 if (i
.tm
.cpu_flags
.bitfield
.cpupadlock
)
6977 if (prefix
!= REPE_PREFIX_OPCODE
6978 || (i
.prefix
[REP_PREFIX
]
6979 != REPE_PREFIX_OPCODE
))
6980 add_prefix (prefix
);
6983 add_prefix (prefix
);
6992 /* The prefix bytes. */
6993 for (j
= ARRAY_SIZE (i
.prefix
), q
= i
.prefix
; j
> 0; j
--, q
++)
6995 FRAG_APPEND_1_CHAR (*q
);
6999 for (j
= 0, q
= i
.prefix
; j
< ARRAY_SIZE (i
.prefix
); j
++, q
++)
7004 /* REX byte is encoded in VEX prefix. */
7008 FRAG_APPEND_1_CHAR (*q
);
7011 /* There should be no other prefixes for instructions
7016 /* For EVEX instructions i.vrex should become 0 after
7017 build_evex_prefix. For VEX instructions upper 16 registers
7018 aren't available, so VREX should be 0. */
7021 /* Now the VEX prefix. */
7022 p
= frag_more (i
.vex
.length
);
7023 for (j
= 0; j
< i
.vex
.length
; j
++)
7024 p
[j
] = i
.vex
.bytes
[j
];
7027 /* Now the opcode; be careful about word order here! */
7028 if (i
.tm
.opcode_length
== 1)
7030 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
7034 switch (i
.tm
.opcode_length
)
7038 *p
++ = (i
.tm
.base_opcode
>> 24) & 0xff;
7039 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
7043 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
7053 /* Put out high byte first: can't use md_number_to_chars! */
7054 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
7055 *p
= i
.tm
.base_opcode
& 0xff;
7058 /* Now the modrm byte and sib byte (if present). */
7059 if (i
.tm
.opcode_modifier
.modrm
)
7061 FRAG_APPEND_1_CHAR ((i
.rm
.regmem
<< 0
7064 /* If i.rm.regmem == ESP (4)
7065 && i.rm.mode != (Register mode)
7067 ==> need second modrm byte. */
7068 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
7070 && !(i
.base_reg
&& i
.base_reg
->reg_type
.bitfield
.reg16
))
7071 FRAG_APPEND_1_CHAR ((i
.sib
.base
<< 0
7073 | i
.sib
.scale
<< 6));
7076 if (i
.disp_operands
)
7077 output_disp (insn_start_frag
, insn_start_off
);
7080 output_imm (insn_start_frag
, insn_start_off
);
7086 pi ("" /*line*/, &i
);
7088 #endif /* DEBUG386 */
7091 /* Return the size of the displacement operand N. */
7094 disp_size (unsigned int n
)
7098 /* Vec_Disp8 has to be 8bit. */
7099 if (i
.types
[n
].bitfield
.vec_disp8
)
7101 else if (i
.types
[n
].bitfield
.disp64
)
7103 else if (i
.types
[n
].bitfield
.disp8
)
7105 else if (i
.types
[n
].bitfield
.disp16
)
7110 /* Return the size of the immediate operand N. */
7113 imm_size (unsigned int n
)
7116 if (i
.types
[n
].bitfield
.imm64
)
7118 else if (i
.types
[n
].bitfield
.imm8
|| i
.types
[n
].bitfield
.imm8s
)
7120 else if (i
.types
[n
].bitfield
.imm16
)
7126 output_disp (fragS
*insn_start_frag
, offsetT insn_start_off
)
7131 for (n
= 0; n
< i
.operands
; n
++)
7133 if (i
.types
[n
].bitfield
.vec_disp8
7134 || operand_type_check (i
.types
[n
], disp
))
7136 if (i
.op
[n
].disps
->X_op
== O_constant
)
7138 int size
= disp_size (n
);
7139 offsetT val
= i
.op
[n
].disps
->X_add_number
;
7141 if (i
.types
[n
].bitfield
.vec_disp8
)
7143 val
= offset_in_range (val
, size
);
7144 p
= frag_more (size
);
7145 md_number_to_chars (p
, val
, size
);
7149 enum bfd_reloc_code_real reloc_type
;
7150 int size
= disp_size (n
);
7151 int sign
= i
.types
[n
].bitfield
.disp32s
;
7152 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
7154 /* We can't have 8 bit displacement here. */
7155 gas_assert (!i
.types
[n
].bitfield
.disp8
);
7157 /* The PC relative address is computed relative
7158 to the instruction boundary, so in case immediate
7159 fields follows, we need to adjust the value. */
7160 if (pcrel
&& i
.imm_operands
)
7165 for (n1
= 0; n1
< i
.operands
; n1
++)
7166 if (operand_type_check (i
.types
[n1
], imm
))
7168 /* Only one immediate is allowed for PC
7169 relative address. */
7170 gas_assert (sz
== 0);
7172 i
.op
[n
].disps
->X_add_number
-= sz
;
7174 /* We should find the immediate. */
7175 gas_assert (sz
!= 0);
7178 p
= frag_more (size
);
7179 reloc_type
= reloc (size
, pcrel
, sign
,
7180 (i
.bnd_prefix
!= NULL
7184 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
7185 && (((reloc_type
== BFD_RELOC_32
7186 || reloc_type
== BFD_RELOC_X86_64_32S
7187 || (reloc_type
== BFD_RELOC_64
7189 && (i
.op
[n
].disps
->X_op
== O_symbol
7190 || (i
.op
[n
].disps
->X_op
== O_add
7191 && ((symbol_get_value_expression
7192 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
7194 || reloc_type
== BFD_RELOC_32_PCREL
))
7198 if (insn_start_frag
== frag_now
)
7199 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
7204 add
= insn_start_frag
->fr_fix
- insn_start_off
;
7205 for (fr
= insn_start_frag
->fr_next
;
7206 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
7208 add
+= p
- frag_now
->fr_literal
;
7213 reloc_type
= BFD_RELOC_386_GOTPC
;
7214 i
.op
[n
].imms
->X_add_number
+= add
;
7216 else if (reloc_type
== BFD_RELOC_64
)
7217 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
7219 /* Don't do the adjustment for x86-64, as there
7220 the pcrel addressing is relative to the _next_
7221 insn, and that is taken care of in other code. */
7222 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
7224 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
7225 i
.op
[n
].disps
, pcrel
, reloc_type
);
7232 output_imm (fragS
*insn_start_frag
, offsetT insn_start_off
)
7237 for (n
= 0; n
< i
.operands
; n
++)
7239 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
7240 if (i
.rounding
&& (int) n
== i
.rounding
->operand
)
7243 if (operand_type_check (i
.types
[n
], imm
))
7245 if (i
.op
[n
].imms
->X_op
== O_constant
)
7247 int size
= imm_size (n
);
7250 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
7252 p
= frag_more (size
);
7253 md_number_to_chars (p
, val
, size
);
7257 /* Not absolute_section.
7258 Need a 32-bit fixup (don't support 8bit
7259 non-absolute imms). Try to support other
7261 enum bfd_reloc_code_real reloc_type
;
7262 int size
= imm_size (n
);
7265 if (i
.types
[n
].bitfield
.imm32s
7266 && (i
.suffix
== QWORD_MNEM_SUFFIX
7267 || (!i
.suffix
&& i
.tm
.opcode_modifier
.no_lsuf
)))
7272 p
= frag_more (size
);
7273 reloc_type
= reloc (size
, 0, sign
, 0, i
.reloc
[n
]);
7275 /* This is tough to explain. We end up with this one if we
7276 * have operands that look like
7277 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
7278 * obtain the absolute address of the GOT, and it is strongly
7279 * preferable from a performance point of view to avoid using
7280 * a runtime relocation for this. The actual sequence of
7281 * instructions often look something like:
7286 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
7288 * The call and pop essentially return the absolute address
7289 * of the label .L66 and store it in %ebx. The linker itself
7290 * will ultimately change the first operand of the addl so
7291 * that %ebx points to the GOT, but to keep things simple, the
7292 * .o file must have this operand set so that it generates not
7293 * the absolute address of .L66, but the absolute address of
7294 * itself. This allows the linker itself simply treat a GOTPC
7295 * relocation as asking for a pcrel offset to the GOT to be
7296 * added in, and the addend of the relocation is stored in the
7297 * operand field for the instruction itself.
7299 * Our job here is to fix the operand so that it would add
7300 * the correct offset so that %ebx would point to itself. The
7301 * thing that is tricky is that .-.L66 will point to the
7302 * beginning of the instruction, so we need to further modify
7303 * the operand so that it will point to itself. There are
7304 * other cases where you have something like:
7306 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
7308 * and here no correction would be required. Internally in
7309 * the assembler we treat operands of this form as not being
7310 * pcrel since the '.' is explicitly mentioned, and I wonder
7311 * whether it would simplify matters to do it this way. Who
7312 * knows. In earlier versions of the PIC patches, the
7313 * pcrel_adjust field was used to store the correction, but
7314 * since the expression is not pcrel, I felt it would be
7315 * confusing to do it this way. */
7317 if ((reloc_type
== BFD_RELOC_32
7318 || reloc_type
== BFD_RELOC_X86_64_32S
7319 || reloc_type
== BFD_RELOC_64
)
7321 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
7322 && (i
.op
[n
].imms
->X_op
== O_symbol
7323 || (i
.op
[n
].imms
->X_op
== O_add
7324 && ((symbol_get_value_expression
7325 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
7330 if (insn_start_frag
== frag_now
)
7331 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
7336 add
= insn_start_frag
->fr_fix
- insn_start_off
;
7337 for (fr
= insn_start_frag
->fr_next
;
7338 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
7340 add
+= p
- frag_now
->fr_literal
;
7344 reloc_type
= BFD_RELOC_386_GOTPC
;
7346 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
7348 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
7349 i
.op
[n
].imms
->X_add_number
+= add
;
7351 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
7352 i
.op
[n
].imms
, 0, reloc_type
);
7358 /* x86_cons_fix_new is called via the expression parsing code when a
7359 reloc is needed. We use this hook to get the correct .got reloc. */
7360 static int cons_sign
= -1;
7363 x86_cons_fix_new (fragS
*frag
, unsigned int off
, unsigned int len
,
7364 expressionS
*exp
, bfd_reloc_code_real_type r
)
7366 r
= reloc (len
, 0, cons_sign
, 0, r
);
7369 if (exp
->X_op
== O_secrel
)
7371 exp
->X_op
= O_symbol
;
7372 r
= BFD_RELOC_32_SECREL
;
7376 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
7379 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
7380 purpose of the `.dc.a' internal pseudo-op. */
7383 x86_address_bytes (void)
7385 if ((stdoutput
->arch_info
->mach
& bfd_mach_x64_32
))
7387 return stdoutput
->arch_info
->bits_per_address
/ 8;
7390 #if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
7392 # define lex_got(reloc, adjust, types, bnd_prefix) NULL
7394 /* Parse operands of the form
7395 <symbol>@GOTOFF+<nnn>
7396 and similar .plt or .got references.
7398 If we find one, set up the correct relocation in RELOC and copy the
7399 input string, minus the `@GOTOFF' into a malloc'd buffer for
7400 parsing by the calling routine. Return this buffer, and if ADJUST
7401 is non-null set it to the length of the string we removed from the
7402 input line. Otherwise return NULL. */
7404 lex_got (enum bfd_reloc_code_real
*rel
,
7406 i386_operand_type
*types
,
7409 /* Some of the relocations depend on the size of what field is to
7410 be relocated. But in our callers i386_immediate and i386_displacement
7411 we don't yet know the operand size (this will be set by insn
7412 matching). Hence we record the word32 relocation here,
7413 and adjust the reloc according to the real size in reloc(). */
7414 static const struct {
7417 const enum bfd_reloc_code_real rel
[2];
7418 const i386_operand_type types64
;
7420 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7421 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32
,
7423 OPERAND_TYPE_IMM32_64
},
7425 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real
,
7426 BFD_RELOC_X86_64_PLTOFF64
},
7427 OPERAND_TYPE_IMM64
},
7428 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32
,
7429 BFD_RELOC_X86_64_PLT32
},
7430 OPERAND_TYPE_IMM32_32S_DISP32
},
7431 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real
,
7432 BFD_RELOC_X86_64_GOTPLT64
},
7433 OPERAND_TYPE_IMM64_DISP64
},
7434 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF
,
7435 BFD_RELOC_X86_64_GOTOFF64
},
7436 OPERAND_TYPE_IMM64_DISP64
},
7437 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real
,
7438 BFD_RELOC_X86_64_GOTPCREL
},
7439 OPERAND_TYPE_IMM32_32S_DISP32
},
7440 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD
,
7441 BFD_RELOC_X86_64_TLSGD
},
7442 OPERAND_TYPE_IMM32_32S_DISP32
},
7443 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM
,
7444 _dummy_first_bfd_reloc_code_real
},
7445 OPERAND_TYPE_NONE
},
7446 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real
,
7447 BFD_RELOC_X86_64_TLSLD
},
7448 OPERAND_TYPE_IMM32_32S_DISP32
},
7449 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32
,
7450 BFD_RELOC_X86_64_GOTTPOFF
},
7451 OPERAND_TYPE_IMM32_32S_DISP32
},
7452 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32
,
7453 BFD_RELOC_X86_64_TPOFF32
},
7454 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
7455 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE
,
7456 _dummy_first_bfd_reloc_code_real
},
7457 OPERAND_TYPE_NONE
},
7458 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32
,
7459 BFD_RELOC_X86_64_DTPOFF32
},
7460 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
7461 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE
,
7462 _dummy_first_bfd_reloc_code_real
},
7463 OPERAND_TYPE_NONE
},
7464 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE
,
7465 _dummy_first_bfd_reloc_code_real
},
7466 OPERAND_TYPE_NONE
},
7467 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32
,
7468 BFD_RELOC_X86_64_GOT32
},
7469 OPERAND_TYPE_IMM32_32S_64_DISP32
},
7470 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC
,
7471 BFD_RELOC_X86_64_GOTPC32_TLSDESC
},
7472 OPERAND_TYPE_IMM32_32S_DISP32
},
7473 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL
,
7474 BFD_RELOC_X86_64_TLSDESC_CALL
},
7475 OPERAND_TYPE_IMM32_32S_DISP32
},
7480 #if defined (OBJ_MAYBE_ELF)
7485 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
7486 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
7489 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
7491 int len
= gotrel
[j
].len
;
7492 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
7494 if (gotrel
[j
].rel
[object_64bit
] != 0)
7497 char *tmpbuf
, *past_reloc
;
7499 *rel
= gotrel
[j
].rel
[object_64bit
];
7503 if (flag_code
!= CODE_64BIT
)
7505 types
->bitfield
.imm32
= 1;
7506 types
->bitfield
.disp32
= 1;
7509 *types
= gotrel
[j
].types64
;
7512 if (j
!= 0 && GOT_symbol
== NULL
)
7513 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
7515 /* The length of the first part of our input line. */
7516 first
= cp
- input_line_pointer
;
7518 /* The second part goes from after the reloc token until
7519 (and including) an end_of_line char or comma. */
7520 past_reloc
= cp
+ 1 + len
;
7522 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
7524 second
= cp
+ 1 - past_reloc
;
7526 /* Allocate and copy string. The trailing NUL shouldn't
7527 be necessary, but be safe. */
7528 tmpbuf
= (char *) xmalloc (first
+ second
+ 2);
7529 memcpy (tmpbuf
, input_line_pointer
, first
);
7530 if (second
!= 0 && *past_reloc
!= ' ')
7531 /* Replace the relocation token with ' ', so that
7532 errors like foo@GOTOFF1 will be detected. */
7533 tmpbuf
[first
++] = ' ';
7535 /* Increment length by 1 if the relocation token is
7540 memcpy (tmpbuf
+ first
, past_reloc
, second
);
7541 tmpbuf
[first
+ second
] = '\0';
7542 if (bnd_prefix
&& *rel
== BFD_RELOC_X86_64_PLT32
)
7543 *rel
= BFD_RELOC_X86_64_PLT32_BND
;
7547 as_bad (_("@%s reloc is not supported with %d-bit output format"),
7548 gotrel
[j
].str
, 1 << (5 + object_64bit
));
7553 /* Might be a symbol version string. Don't as_bad here. */
7562 /* Parse operands of the form
7563 <symbol>@SECREL32+<nnn>
7565 If we find one, set up the correct relocation in RELOC and copy the
7566 input string, minus the `@SECREL32' into a malloc'd buffer for
7567 parsing by the calling routine. Return this buffer, and if ADJUST
7568 is non-null set it to the length of the string we removed from the
7569 input line. Otherwise return NULL.
7571 This function is copied from the ELF version above adjusted for PE targets. */
7574 lex_got (enum bfd_reloc_code_real
*rel ATTRIBUTE_UNUSED
,
7575 int *adjust ATTRIBUTE_UNUSED
,
7576 i386_operand_type
*types
,
7577 int bnd_prefix ATTRIBUTE_UNUSED
)
7583 const enum bfd_reloc_code_real rel
[2];
7584 const i386_operand_type types64
;
7588 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL
,
7589 BFD_RELOC_32_SECREL
},
7590 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
7596 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
7597 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
7600 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
7602 int len
= gotrel
[j
].len
;
7604 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
7606 if (gotrel
[j
].rel
[object_64bit
] != 0)
7609 char *tmpbuf
, *past_reloc
;
7611 *rel
= gotrel
[j
].rel
[object_64bit
];
7617 if (flag_code
!= CODE_64BIT
)
7619 types
->bitfield
.imm32
= 1;
7620 types
->bitfield
.disp32
= 1;
7623 *types
= gotrel
[j
].types64
;
7626 /* The length of the first part of our input line. */
7627 first
= cp
- input_line_pointer
;
7629 /* The second part goes from after the reloc token until
7630 (and including) an end_of_line char or comma. */
7631 past_reloc
= cp
+ 1 + len
;
7633 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
7635 second
= cp
+ 1 - past_reloc
;
7637 /* Allocate and copy string. The trailing NUL shouldn't
7638 be necessary, but be safe. */
7639 tmpbuf
= (char *) xmalloc (first
+ second
+ 2);
7640 memcpy (tmpbuf
, input_line_pointer
, first
);
7641 if (second
!= 0 && *past_reloc
!= ' ')
7642 /* Replace the relocation token with ' ', so that
7643 errors like foo@SECLREL321 will be detected. */
7644 tmpbuf
[first
++] = ' ';
7645 memcpy (tmpbuf
+ first
, past_reloc
, second
);
7646 tmpbuf
[first
+ second
] = '\0';
7650 as_bad (_("@%s reloc is not supported with %d-bit output format"),
7651 gotrel
[j
].str
, 1 << (5 + object_64bit
));
7656 /* Might be a symbol version string. Don't as_bad here. */
7662 bfd_reloc_code_real_type
7663 x86_cons (expressionS
*exp
, int size
)
7665 bfd_reloc_code_real_type got_reloc
= NO_RELOC
;
7667 intel_syntax
= -intel_syntax
;
7670 if (size
== 4 || (object_64bit
&& size
== 8))
7672 /* Handle @GOTOFF and the like in an expression. */
7674 char *gotfree_input_line
;
7677 save
= input_line_pointer
;
7678 gotfree_input_line
= lex_got (&got_reloc
, &adjust
, NULL
, 0);
7679 if (gotfree_input_line
)
7680 input_line_pointer
= gotfree_input_line
;
7684 if (gotfree_input_line
)
7686 /* expression () has merrily parsed up to the end of line,
7687 or a comma - in the wrong buffer. Transfer how far
7688 input_line_pointer has moved to the right buffer. */
7689 input_line_pointer
= (save
7690 + (input_line_pointer
- gotfree_input_line
)
7692 free (gotfree_input_line
);
7693 if (exp
->X_op
== O_constant
7694 || exp
->X_op
== O_absent
7695 || exp
->X_op
== O_illegal
7696 || exp
->X_op
== O_register
7697 || exp
->X_op
== O_big
)
7699 char c
= *input_line_pointer
;
7700 *input_line_pointer
= 0;
7701 as_bad (_("missing or invalid expression `%s'"), save
);
7702 *input_line_pointer
= c
;
7709 intel_syntax
= -intel_syntax
;
7712 i386_intel_simplify (exp
);
7718 signed_cons (int size
)
7720 if (flag_code
== CODE_64BIT
)
7728 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
7735 if (exp
.X_op
== O_symbol
)
7736 exp
.X_op
= O_secrel
;
7738 emit_expr (&exp
, 4);
7740 while (*input_line_pointer
++ == ',');
7742 input_line_pointer
--;
7743 demand_empty_rest_of_line ();
7747 /* Handle Vector operations. */
7750 check_VecOperations (char *op_string
, char *op_end
)
7752 const reg_entry
*mask
;
7757 && (op_end
== NULL
|| op_string
< op_end
))
7760 if (*op_string
== '{')
7764 /* Check broadcasts. */
7765 if (strncmp (op_string
, "1to", 3) == 0)
7770 goto duplicated_vec_op
;
7773 if (*op_string
== '8')
7774 bcst_type
= BROADCAST_1TO8
;
7775 else if (*op_string
== '4')
7776 bcst_type
= BROADCAST_1TO4
;
7777 else if (*op_string
== '2')
7778 bcst_type
= BROADCAST_1TO2
;
7779 else if (*op_string
== '1'
7780 && *(op_string
+1) == '6')
7782 bcst_type
= BROADCAST_1TO16
;
7787 as_bad (_("Unsupported broadcast: `%s'"), saved
);
7792 broadcast_op
.type
= bcst_type
;
7793 broadcast_op
.operand
= this_operand
;
7794 i
.broadcast
= &broadcast_op
;
7796 /* Check masking operation. */
7797 else if ((mask
= parse_register (op_string
, &end_op
)) != NULL
)
7799 /* k0 can't be used for write mask. */
7800 if (mask
->reg_num
== 0)
7802 as_bad (_("`%s' can't be used for write mask"),
7809 mask_op
.mask
= mask
;
7810 mask_op
.zeroing
= 0;
7811 mask_op
.operand
= this_operand
;
7817 goto duplicated_vec_op
;
7819 i
.mask
->mask
= mask
;
7821 /* Only "{z}" is allowed here. No need to check
7822 zeroing mask explicitly. */
7823 if (i
.mask
->operand
!= this_operand
)
7825 as_bad (_("invalid write mask `%s'"), saved
);
7832 /* Check zeroing-flag for masking operation. */
7833 else if (*op_string
== 'z')
7837 mask_op
.mask
= NULL
;
7838 mask_op
.zeroing
= 1;
7839 mask_op
.operand
= this_operand
;
7844 if (i
.mask
->zeroing
)
7847 as_bad (_("duplicated `%s'"), saved
);
7851 i
.mask
->zeroing
= 1;
7853 /* Only "{%k}" is allowed here. No need to check mask
7854 register explicitly. */
7855 if (i
.mask
->operand
!= this_operand
)
7857 as_bad (_("invalid zeroing-masking `%s'"),
7866 goto unknown_vec_op
;
7868 if (*op_string
!= '}')
7870 as_bad (_("missing `}' in `%s'"), saved
);
7877 /* We don't know this one. */
7878 as_bad (_("unknown vector operation: `%s'"), saved
);
7886 i386_immediate (char *imm_start
)
7888 char *save_input_line_pointer
;
7889 char *gotfree_input_line
;
7892 i386_operand_type types
;
7894 operand_type_set (&types
, ~0);
7896 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
7898 as_bad (_("at most %d immediate operands are allowed"),
7899 MAX_IMMEDIATE_OPERANDS
);
7903 exp
= &im_expressions
[i
.imm_operands
++];
7904 i
.op
[this_operand
].imms
= exp
;
7906 if (is_space_char (*imm_start
))
7909 save_input_line_pointer
= input_line_pointer
;
7910 input_line_pointer
= imm_start
;
7912 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
,
7913 (i
.bnd_prefix
!= NULL
7914 || add_bnd_prefix
));
7915 if (gotfree_input_line
)
7916 input_line_pointer
= gotfree_input_line
;
7918 exp_seg
= expression (exp
);
7922 /* Handle vector operations. */
7923 if (*input_line_pointer
== '{')
7925 input_line_pointer
= check_VecOperations (input_line_pointer
,
7927 if (input_line_pointer
== NULL
)
7931 if (*input_line_pointer
)
7932 as_bad (_("junk `%s' after expression"), input_line_pointer
);
7934 input_line_pointer
= save_input_line_pointer
;
7935 if (gotfree_input_line
)
7937 free (gotfree_input_line
);
7939 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
7940 exp
->X_op
= O_illegal
;
7943 return i386_finalize_immediate (exp_seg
, exp
, types
, imm_start
);
7947 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
7948 i386_operand_type types
, const char *imm_start
)
7950 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_illegal
|| exp
->X_op
== O_big
)
7953 as_bad (_("missing or invalid immediate expression `%s'"),
7957 else if (exp
->X_op
== O_constant
)
7959 /* Size it properly later. */
7960 i
.types
[this_operand
].bitfield
.imm64
= 1;
7961 /* If not 64bit, sign extend val. */
7962 if (flag_code
!= CODE_64BIT
7963 && (exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
7965 = (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
7967 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
7968 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
7969 && exp_seg
!= absolute_section
7970 && exp_seg
!= text_section
7971 && exp_seg
!= data_section
7972 && exp_seg
!= bss_section
7973 && exp_seg
!= undefined_section
7974 && !bfd_is_com_section (exp_seg
))
7976 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
7980 else if (!intel_syntax
&& exp
->X_op
== O_register
)
7983 as_bad (_("illegal immediate register operand %s"), imm_start
);
7988 /* This is an address. The size of the address will be
7989 determined later, depending on destination register,
7990 suffix, or the default for the section. */
7991 i
.types
[this_operand
].bitfield
.imm8
= 1;
7992 i
.types
[this_operand
].bitfield
.imm16
= 1;
7993 i
.types
[this_operand
].bitfield
.imm32
= 1;
7994 i
.types
[this_operand
].bitfield
.imm32s
= 1;
7995 i
.types
[this_operand
].bitfield
.imm64
= 1;
7996 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
8004 i386_scale (char *scale
)
8007 char *save
= input_line_pointer
;
8009 input_line_pointer
= scale
;
8010 val
= get_absolute_expression ();
8015 i
.log2_scale_factor
= 0;
8018 i
.log2_scale_factor
= 1;
8021 i
.log2_scale_factor
= 2;
8024 i
.log2_scale_factor
= 3;
8028 char sep
= *input_line_pointer
;
8030 *input_line_pointer
= '\0';
8031 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
8033 *input_line_pointer
= sep
;
8034 input_line_pointer
= save
;
8038 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
8040 as_warn (_("scale factor of %d without an index register"),
8041 1 << i
.log2_scale_factor
);
8042 i
.log2_scale_factor
= 0;
8044 scale
= input_line_pointer
;
8045 input_line_pointer
= save
;
8050 i386_displacement (char *disp_start
, char *disp_end
)
8054 char *save_input_line_pointer
;
8055 char *gotfree_input_line
;
8057 i386_operand_type bigdisp
, types
= anydisp
;
8060 if (i
.disp_operands
== MAX_MEMORY_OPERANDS
)
8062 as_bad (_("at most %d displacement operands are allowed"),
8063 MAX_MEMORY_OPERANDS
);
8067 operand_type_set (&bigdisp
, 0);
8068 if ((i
.types
[this_operand
].bitfield
.jumpabsolute
)
8069 || (!current_templates
->start
->opcode_modifier
.jump
8070 && !current_templates
->start
->opcode_modifier
.jumpdword
))
8072 bigdisp
.bitfield
.disp32
= 1;
8073 override
= (i
.prefix
[ADDR_PREFIX
] != 0);
8074 if (flag_code
== CODE_64BIT
)
8078 bigdisp
.bitfield
.disp32s
= 1;
8079 bigdisp
.bitfield
.disp64
= 1;
8082 else if ((flag_code
== CODE_16BIT
) ^ override
)
8084 bigdisp
.bitfield
.disp32
= 0;
8085 bigdisp
.bitfield
.disp16
= 1;
8090 /* For PC-relative branches, the width of the displacement
8091 is dependent upon data size, not address size. */
8092 override
= (i
.prefix
[DATA_PREFIX
] != 0);
8093 if (flag_code
== CODE_64BIT
)
8095 if (override
|| i
.suffix
== WORD_MNEM_SUFFIX
)
8096 bigdisp
.bitfield
.disp16
= 1;
8099 bigdisp
.bitfield
.disp32
= 1;
8100 bigdisp
.bitfield
.disp32s
= 1;
8106 override
= (i
.suffix
== (flag_code
!= CODE_16BIT
8108 : LONG_MNEM_SUFFIX
));
8109 bigdisp
.bitfield
.disp32
= 1;
8110 if ((flag_code
== CODE_16BIT
) ^ override
)
8112 bigdisp
.bitfield
.disp32
= 0;
8113 bigdisp
.bitfield
.disp16
= 1;
8117 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
8120 exp
= &disp_expressions
[i
.disp_operands
];
8121 i
.op
[this_operand
].disps
= exp
;
8123 save_input_line_pointer
= input_line_pointer
;
8124 input_line_pointer
= disp_start
;
8125 END_STRING_AND_SAVE (disp_end
);
8127 #ifndef GCC_ASM_O_HACK
8128 #define GCC_ASM_O_HACK 0
8131 END_STRING_AND_SAVE (disp_end
+ 1);
8132 if (i
.types
[this_operand
].bitfield
.baseIndex
8133 && displacement_string_end
[-1] == '+')
8135 /* This hack is to avoid a warning when using the "o"
8136 constraint within gcc asm statements.
8139 #define _set_tssldt_desc(n,addr,limit,type) \
8140 __asm__ __volatile__ ( \
8142 "movw %w1,2+%0\n\t" \
8144 "movb %b1,4+%0\n\t" \
8145 "movb %4,5+%0\n\t" \
8146 "movb $0,6+%0\n\t" \
8147 "movb %h1,7+%0\n\t" \
8149 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
8151 This works great except that the output assembler ends
8152 up looking a bit weird if it turns out that there is
8153 no offset. You end up producing code that looks like:
8166 So here we provide the missing zero. */
8168 *displacement_string_end
= '0';
8171 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
,
8172 (i
.bnd_prefix
!= NULL
8173 || add_bnd_prefix
));
8174 if (gotfree_input_line
)
8175 input_line_pointer
= gotfree_input_line
;
8177 exp_seg
= expression (exp
);
8180 if (*input_line_pointer
)
8181 as_bad (_("junk `%s' after expression"), input_line_pointer
);
8183 RESTORE_END_STRING (disp_end
+ 1);
8185 input_line_pointer
= save_input_line_pointer
;
8186 if (gotfree_input_line
)
8188 free (gotfree_input_line
);
8190 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
8191 exp
->X_op
= O_illegal
;
8194 ret
= i386_finalize_displacement (exp_seg
, exp
, types
, disp_start
);
8196 RESTORE_END_STRING (disp_end
);
8202 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
8203 i386_operand_type types
, const char *disp_start
)
8205 i386_operand_type bigdisp
;
8208 /* We do this to make sure that the section symbol is in
8209 the symbol table. We will ultimately change the relocation
8210 to be relative to the beginning of the section. */
8211 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
8212 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
8213 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
8215 if (exp
->X_op
!= O_symbol
)
8218 if (S_IS_LOCAL (exp
->X_add_symbol
)
8219 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
8220 && S_GET_SEGMENT (exp
->X_add_symbol
) != expr_section
)
8221 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
8222 exp
->X_op
= O_subtract
;
8223 exp
->X_op_symbol
= GOT_symbol
;
8224 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
8225 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
8226 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
8227 i
.reloc
[this_operand
] = BFD_RELOC_64
;
8229 i
.reloc
[this_operand
] = BFD_RELOC_32
;
8232 else if (exp
->X_op
== O_absent
8233 || exp
->X_op
== O_illegal
8234 || exp
->X_op
== O_big
)
8237 as_bad (_("missing or invalid displacement expression `%s'"),
8242 else if (flag_code
== CODE_64BIT
8243 && !i
.prefix
[ADDR_PREFIX
]
8244 && exp
->X_op
== O_constant
)
8246 /* Since displacement is signed extended to 64bit, don't allow
8247 disp32 and turn off disp32s if they are out of range. */
8248 i
.types
[this_operand
].bitfield
.disp32
= 0;
8249 if (!fits_in_signed_long (exp
->X_add_number
))
8251 i
.types
[this_operand
].bitfield
.disp32s
= 0;
8252 if (i
.types
[this_operand
].bitfield
.baseindex
)
8254 as_bad (_("0x%lx out range of signed 32bit displacement"),
8255 (long) exp
->X_add_number
);
8261 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8262 else if (exp
->X_op
!= O_constant
8263 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
8264 && exp_seg
!= absolute_section
8265 && exp_seg
!= text_section
8266 && exp_seg
!= data_section
8267 && exp_seg
!= bss_section
8268 && exp_seg
!= undefined_section
8269 && !bfd_is_com_section (exp_seg
))
8271 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
8276 /* Check if this is a displacement only operand. */
8277 bigdisp
= i
.types
[this_operand
];
8278 bigdisp
.bitfield
.disp8
= 0;
8279 bigdisp
.bitfield
.disp16
= 0;
8280 bigdisp
.bitfield
.disp32
= 0;
8281 bigdisp
.bitfield
.disp32s
= 0;
8282 bigdisp
.bitfield
.disp64
= 0;
8283 if (operand_type_all_zero (&bigdisp
))
8284 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
8290 /* Make sure the memory operand we've been dealt is valid.
8291 Return 1 on success, 0 on a failure. */
8294 i386_index_check (const char *operand_string
)
8296 const char *kind
= "base/index";
8297 enum flag_code addr_mode
;
8299 if (i
.prefix
[ADDR_PREFIX
])
8300 addr_mode
= flag_code
== CODE_32BIT
? CODE_16BIT
: CODE_32BIT
;
8303 addr_mode
= flag_code
;
8305 #if INFER_ADDR_PREFIX
8306 if (i
.mem_operands
== 0)
8308 /* Infer address prefix from the first memory operand. */
8309 const reg_entry
*addr_reg
= i
.base_reg
;
8311 if (addr_reg
== NULL
)
8312 addr_reg
= i
.index_reg
;
8316 if (addr_reg
->reg_num
== RegEip
8317 || addr_reg
->reg_num
== RegEiz
8318 || addr_reg
->reg_type
.bitfield
.reg32
)
8319 addr_mode
= CODE_32BIT
;
8320 else if (flag_code
!= CODE_64BIT
8321 && addr_reg
->reg_type
.bitfield
.reg16
)
8322 addr_mode
= CODE_16BIT
;
8324 if (addr_mode
!= flag_code
)
8326 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
8328 /* Change the size of any displacement too. At most one
8329 of Disp16 or Disp32 is set.
8330 FIXME. There doesn't seem to be any real need for
8331 separate Disp16 and Disp32 flags. The same goes for
8332 Imm16 and Imm32. Removing them would probably clean
8333 up the code quite a lot. */
8334 if (flag_code
!= CODE_64BIT
8335 && (i
.types
[this_operand
].bitfield
.disp16
8336 || i
.types
[this_operand
].bitfield
.disp32
))
8337 i
.types
[this_operand
]
8338 = operand_type_xor (i
.types
[this_operand
], disp16_32
);
8345 if (current_templates
->start
->opcode_modifier
.isstring
8346 && !current_templates
->start
->opcode_modifier
.immext
8347 && (current_templates
->end
[-1].opcode_modifier
.isstring
8350 /* Memory operands of string insns are special in that they only allow
8351 a single register (rDI, rSI, or rBX) as their memory address. */
8352 const reg_entry
*expected_reg
;
8353 static const char *di_si
[][2] =
8359 static const char *bx
[] = { "ebx", "bx", "rbx" };
8361 kind
= "string address";
8363 if (current_templates
->start
->opcode_modifier
.w
)
8365 i386_operand_type type
= current_templates
->end
[-1].operand_types
[0];
8367 if (!type
.bitfield
.baseindex
8368 || ((!i
.mem_operands
!= !intel_syntax
)
8369 && current_templates
->end
[-1].operand_types
[1]
8370 .bitfield
.baseindex
))
8371 type
= current_templates
->end
[-1].operand_types
[1];
8372 expected_reg
= hash_find (reg_hash
,
8373 di_si
[addr_mode
][type
.bitfield
.esseg
]);
8377 expected_reg
= hash_find (reg_hash
, bx
[addr_mode
]);
8379 if (i
.base_reg
!= expected_reg
8381 || operand_type_check (i
.types
[this_operand
], disp
))
8383 /* The second memory operand must have the same size as
8387 && !((addr_mode
== CODE_64BIT
8388 && i
.base_reg
->reg_type
.bitfield
.reg64
)
8389 || (addr_mode
== CODE_32BIT
8390 ? i
.base_reg
->reg_type
.bitfield
.reg32
8391 : i
.base_reg
->reg_type
.bitfield
.reg16
)))
8394 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
8396 intel_syntax
? '[' : '(',
8398 expected_reg
->reg_name
,
8399 intel_syntax
? ']' : ')');
8406 as_bad (_("`%s' is not a valid %s expression"),
8407 operand_string
, kind
);
8412 if (addr_mode
!= CODE_16BIT
)
8414 /* 32-bit/64-bit checks. */
8416 && (addr_mode
== CODE_64BIT
8417 ? !i
.base_reg
->reg_type
.bitfield
.reg64
8418 : !i
.base_reg
->reg_type
.bitfield
.reg32
)
8420 || (i
.base_reg
->reg_num
8421 != (addr_mode
== CODE_64BIT
? RegRip
: RegEip
))))
8423 && !i
.index_reg
->reg_type
.bitfield
.regxmm
8424 && !i
.index_reg
->reg_type
.bitfield
.regymm
8425 && !i
.index_reg
->reg_type
.bitfield
.regzmm
8426 && ((addr_mode
== CODE_64BIT
8427 ? !(i
.index_reg
->reg_type
.bitfield
.reg64
8428 || i
.index_reg
->reg_num
== RegRiz
)
8429 : !(i
.index_reg
->reg_type
.bitfield
.reg32
8430 || i
.index_reg
->reg_num
== RegEiz
))
8431 || !i
.index_reg
->reg_type
.bitfield
.baseindex
)))
8436 /* 16-bit checks. */
8438 && (!i
.base_reg
->reg_type
.bitfield
.reg16
8439 || !i
.base_reg
->reg_type
.bitfield
.baseindex
))
8441 && (!i
.index_reg
->reg_type
.bitfield
.reg16
8442 || !i
.index_reg
->reg_type
.bitfield
.baseindex
8444 && i
.base_reg
->reg_num
< 6
8445 && i
.index_reg
->reg_num
>= 6
8446 && i
.log2_scale_factor
== 0))))
8453 /* Handle vector immediates. */
8456 RC_SAE_immediate (const char *imm_start
)
8458 unsigned int match_found
, j
;
8459 const char *pstr
= imm_start
;
8467 for (j
= 0; j
< ARRAY_SIZE (RC_NamesTable
); j
++)
8469 if (!strncmp (pstr
, RC_NamesTable
[j
].name
, RC_NamesTable
[j
].len
))
8473 rc_op
.type
= RC_NamesTable
[j
].type
;
8474 rc_op
.operand
= this_operand
;
8475 i
.rounding
= &rc_op
;
8479 as_bad (_("duplicated `%s'"), imm_start
);
8482 pstr
+= RC_NamesTable
[j
].len
;
8492 as_bad (_("Missing '}': '%s'"), imm_start
);
8495 /* RC/SAE immediate string should contain nothing more. */;
8498 as_bad (_("Junk after '}': '%s'"), imm_start
);
8502 exp
= &im_expressions
[i
.imm_operands
++];
8503 i
.op
[this_operand
].imms
= exp
;
8505 exp
->X_op
= O_constant
;
8506 exp
->X_add_number
= 0;
8507 exp
->X_add_symbol
= (symbolS
*) 0;
8508 exp
->X_op_symbol
= (symbolS
*) 0;
8510 i
.types
[this_operand
].bitfield
.imm8
= 1;
8514 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
8518 i386_att_operand (char *operand_string
)
8522 char *op_string
= operand_string
;
8524 if (is_space_char (*op_string
))
8527 /* We check for an absolute prefix (differentiating,
8528 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
8529 if (*op_string
== ABSOLUTE_PREFIX
)
8532 if (is_space_char (*op_string
))
8534 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
8537 /* Check if operand is a register. */
8538 if ((r
= parse_register (op_string
, &end_op
)) != NULL
)
8540 i386_operand_type temp
;
8542 /* Check for a segment override by searching for ':' after a
8543 segment register. */
8545 if (is_space_char (*op_string
))
8547 if (*op_string
== ':'
8548 && (r
->reg_type
.bitfield
.sreg2
8549 || r
->reg_type
.bitfield
.sreg3
))
8554 i
.seg
[i
.mem_operands
] = &es
;
8557 i
.seg
[i
.mem_operands
] = &cs
;
8560 i
.seg
[i
.mem_operands
] = &ss
;
8563 i
.seg
[i
.mem_operands
] = &ds
;
8566 i
.seg
[i
.mem_operands
] = &fs
;
8569 i
.seg
[i
.mem_operands
] = &gs
;
8573 /* Skip the ':' and whitespace. */
8575 if (is_space_char (*op_string
))
8578 if (!is_digit_char (*op_string
)
8579 && !is_identifier_char (*op_string
)
8580 && *op_string
!= '('
8581 && *op_string
!= ABSOLUTE_PREFIX
)
8583 as_bad (_("bad memory operand `%s'"), op_string
);
8586 /* Handle case of %es:*foo. */
8587 if (*op_string
== ABSOLUTE_PREFIX
)
8590 if (is_space_char (*op_string
))
8592 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
8594 goto do_memory_reference
;
8597 /* Handle vector operations. */
8598 if (*op_string
== '{')
8600 op_string
= check_VecOperations (op_string
, NULL
);
8601 if (op_string
== NULL
)
8607 as_bad (_("junk `%s' after register"), op_string
);
8611 temp
.bitfield
.baseindex
= 0;
8612 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
8614 i
.types
[this_operand
].bitfield
.unspecified
= 0;
8615 i
.op
[this_operand
].regs
= r
;
8618 else if (*op_string
== REGISTER_PREFIX
)
8620 as_bad (_("bad register name `%s'"), op_string
);
8623 else if (*op_string
== IMMEDIATE_PREFIX
)
8626 if (i
.types
[this_operand
].bitfield
.jumpabsolute
)
8628 as_bad (_("immediate operand illegal with absolute jump"));
8631 if (!i386_immediate (op_string
))
8634 else if (RC_SAE_immediate (operand_string
))
8636 /* If it is a RC or SAE immediate, do nothing. */
8639 else if (is_digit_char (*op_string
)
8640 || is_identifier_char (*op_string
)
8641 || *op_string
== '(')
8643 /* This is a memory reference of some sort. */
8646 /* Start and end of displacement string expression (if found). */
8647 char *displacement_string_start
;
8648 char *displacement_string_end
;
8651 do_memory_reference
:
8652 if ((i
.mem_operands
== 1
8653 && !current_templates
->start
->opcode_modifier
.isstring
)
8654 || i
.mem_operands
== 2)
8656 as_bad (_("too many memory references for `%s'"),
8657 current_templates
->start
->name
);
8661 /* Check for base index form. We detect the base index form by
8662 looking for an ')' at the end of the operand, searching
8663 for the '(' matching it, and finding a REGISTER_PREFIX or ','
8665 base_string
= op_string
+ strlen (op_string
);
8667 /* Handle vector operations. */
8668 vop_start
= strchr (op_string
, '{');
8669 if (vop_start
&& vop_start
< base_string
)
8671 if (check_VecOperations (vop_start
, base_string
) == NULL
)
8673 base_string
= vop_start
;
8677 if (is_space_char (*base_string
))
8680 /* If we only have a displacement, set-up for it to be parsed later. */
8681 displacement_string_start
= op_string
;
8682 displacement_string_end
= base_string
+ 1;
8684 if (*base_string
== ')')
8687 unsigned int parens_balanced
= 1;
8688 /* We've already checked that the number of left & right ()'s are
8689 equal, so this loop will not be infinite. */
8693 if (*base_string
== ')')
8695 if (*base_string
== '(')
8698 while (parens_balanced
);
8700 temp_string
= base_string
;
8702 /* Skip past '(' and whitespace. */
8704 if (is_space_char (*base_string
))
8707 if (*base_string
== ','
8708 || ((i
.base_reg
= parse_register (base_string
, &end_op
))
8711 displacement_string_end
= temp_string
;
8713 i
.types
[this_operand
].bitfield
.baseindex
= 1;
8717 base_string
= end_op
;
8718 if (is_space_char (*base_string
))
8722 /* There may be an index reg or scale factor here. */
8723 if (*base_string
== ',')
8726 if (is_space_char (*base_string
))
8729 if ((i
.index_reg
= parse_register (base_string
, &end_op
))
8732 base_string
= end_op
;
8733 if (is_space_char (*base_string
))
8735 if (*base_string
== ',')
8738 if (is_space_char (*base_string
))
8741 else if (*base_string
!= ')')
8743 as_bad (_("expecting `,' or `)' "
8744 "after index register in `%s'"),
8749 else if (*base_string
== REGISTER_PREFIX
)
8751 end_op
= strchr (base_string
, ',');
8754 as_bad (_("bad register name `%s'"), base_string
);
8758 /* Check for scale factor. */
8759 if (*base_string
!= ')')
8761 char *end_scale
= i386_scale (base_string
);
8766 base_string
= end_scale
;
8767 if (is_space_char (*base_string
))
8769 if (*base_string
!= ')')
8771 as_bad (_("expecting `)' "
8772 "after scale factor in `%s'"),
8777 else if (!i
.index_reg
)
8779 as_bad (_("expecting index register or scale factor "
8780 "after `,'; got '%c'"),
8785 else if (*base_string
!= ')')
8787 as_bad (_("expecting `,' or `)' "
8788 "after base register in `%s'"),
8793 else if (*base_string
== REGISTER_PREFIX
)
8795 end_op
= strchr (base_string
, ',');
8798 as_bad (_("bad register name `%s'"), base_string
);
8803 /* If there's an expression beginning the operand, parse it,
8804 assuming displacement_string_start and
8805 displacement_string_end are meaningful. */
8806 if (displacement_string_start
!= displacement_string_end
)
8808 if (!i386_displacement (displacement_string_start
,
8809 displacement_string_end
))
8813 /* Special case for (%dx) while doing input/output op. */
8815 && operand_type_equal (&i
.base_reg
->reg_type
,
8816 ®16_inoutportreg
)
8818 && i
.log2_scale_factor
== 0
8819 && i
.seg
[i
.mem_operands
] == 0
8820 && !operand_type_check (i
.types
[this_operand
], disp
))
8822 i
.types
[this_operand
] = inoutportreg
;
8826 if (i386_index_check (operand_string
) == 0)
8828 i
.types
[this_operand
].bitfield
.mem
= 1;
8833 /* It's not a memory operand; argh! */
8834 as_bad (_("invalid char %s beginning operand %d `%s'"),
8835 output_invalid (*op_string
),
8840 return 1; /* Normal return. */
8843 /* Calculate the maximum variable size (i.e., excluding fr_fix)
8844 that an rs_machine_dependent frag may reach. */
8847 i386_frag_max_var (fragS
*frag
)
8849 /* The only relaxable frags are for jumps.
8850 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
8851 gas_assert (frag
->fr_type
== rs_machine_dependent
);
8852 return TYPE_FROM_RELAX_STATE (frag
->fr_subtype
) == UNCOND_JUMP
? 4 : 5;
8855 /* md_estimate_size_before_relax()
8857 Called just before relax() for rs_machine_dependent frags. The x86
8858 assembler uses these frags to handle variable size jump
8861 Any symbol that is now undefined will not become defined.
8862 Return the correct fr_subtype in the frag.
8863 Return the initial "guess for variable size of frag" to caller.
8864 The guess is actually the growth beyond the fixed part. Whatever
8865 we do to grow the fixed or variable part contributes to our
8869 md_estimate_size_before_relax (fragS
*fragP
, segT segment
)
8871 /* We've already got fragP->fr_subtype right; all we have to do is
8872 check for un-relaxable symbols. On an ELF system, we can't relax
8873 an externally visible symbol, because it may be overridden by a
8875 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
8876 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8878 && (S_IS_EXTERNAL (fragP
->fr_symbol
)
8879 || S_IS_WEAK (fragP
->fr_symbol
)
8880 || ((symbol_get_bfdsym (fragP
->fr_symbol
)->flags
8881 & BSF_GNU_INDIRECT_FUNCTION
))))
8883 #if defined (OBJ_COFF) && defined (TE_PE)
8884 || (OUTPUT_FLAVOR
== bfd_target_coff_flavour
8885 && S_IS_WEAK (fragP
->fr_symbol
))
8889 /* Symbol is undefined in this segment, or we need to keep a
8890 reloc so that weak symbols can be overridden. */
8891 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
8892 enum bfd_reloc_code_real reloc_type
;
8893 unsigned char *opcode
;
8896 if (fragP
->fr_var
!= NO_RELOC
)
8897 reloc_type
= (enum bfd_reloc_code_real
) fragP
->fr_var
;
8899 reloc_type
= BFD_RELOC_16_PCREL
;
8901 reloc_type
= BFD_RELOC_32_PCREL
;
8903 old_fr_fix
= fragP
->fr_fix
;
8904 opcode
= (unsigned char *) fragP
->fr_opcode
;
8906 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
8909 /* Make jmp (0xeb) a (d)word displacement jump. */
8911 fragP
->fr_fix
+= size
;
8912 fix_new (fragP
, old_fr_fix
, size
,
8914 fragP
->fr_offset
, 1,
8920 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
8922 /* Negate the condition, and branch past an
8923 unconditional jump. */
8926 /* Insert an unconditional jump. */
8928 /* We added two extra opcode bytes, and have a two byte
8930 fragP
->fr_fix
+= 2 + 2;
8931 fix_new (fragP
, old_fr_fix
+ 2, 2,
8933 fragP
->fr_offset
, 1,
8940 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
8945 fixP
= fix_new (fragP
, old_fr_fix
, 1,
8947 fragP
->fr_offset
, 1,
8949 fixP
->fx_signed
= 1;
8953 /* This changes the byte-displacement jump 0x7N
8954 to the (d)word-displacement jump 0x0f,0x8N. */
8955 opcode
[1] = opcode
[0] + 0x10;
8956 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
8957 /* We've added an opcode byte. */
8958 fragP
->fr_fix
+= 1 + size
;
8959 fix_new (fragP
, old_fr_fix
+ 1, size
,
8961 fragP
->fr_offset
, 1,
8966 BAD_CASE (fragP
->fr_subtype
);
8970 return fragP
->fr_fix
- old_fr_fix
;
8973 /* Guess size depending on current relax state. Initially the relax
8974 state will correspond to a short jump and we return 1, because
8975 the variable part of the frag (the branch offset) is one byte
8976 long. However, we can relax a section more than once and in that
8977 case we must either set fr_subtype back to the unrelaxed state,
8978 or return the value for the appropriate branch. */
8979 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
8982 /* Called after relax() is finished.
8984 In: Address of frag.
8985 fr_type == rs_machine_dependent.
8986 fr_subtype is what the address relaxed to.
8988 Out: Any fixSs and constants are set up.
8989 Caller will turn frag into a ".space 0". */
8992 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec ATTRIBUTE_UNUSED
,
8995 unsigned char *opcode
;
8996 unsigned char *where_to_put_displacement
= NULL
;
8997 offsetT target_address
;
8998 offsetT opcode_address
;
8999 unsigned int extension
= 0;
9000 offsetT displacement_from_opcode_start
;
9002 opcode
= (unsigned char *) fragP
->fr_opcode
;
9004 /* Address we want to reach in file space. */
9005 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
9007 /* Address opcode resides at in file space. */
9008 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
9010 /* Displacement from opcode start to fill into instruction. */
9011 displacement_from_opcode_start
= target_address
- opcode_address
;
9013 if ((fragP
->fr_subtype
& BIG
) == 0)
9015 /* Don't have to change opcode. */
9016 extension
= 1; /* 1 opcode + 1 displacement */
9017 where_to_put_displacement
= &opcode
[1];
9021 if (no_cond_jump_promotion
9022 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
9023 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
9024 _("long jump required"));
9026 switch (fragP
->fr_subtype
)
9028 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
9029 extension
= 4; /* 1 opcode + 4 displacement */
9031 where_to_put_displacement
= &opcode
[1];
9034 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
9035 extension
= 2; /* 1 opcode + 2 displacement */
9037 where_to_put_displacement
= &opcode
[1];
9040 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
9041 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
9042 extension
= 5; /* 2 opcode + 4 displacement */
9043 opcode
[1] = opcode
[0] + 0x10;
9044 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
9045 where_to_put_displacement
= &opcode
[2];
9048 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
9049 extension
= 3; /* 2 opcode + 2 displacement */
9050 opcode
[1] = opcode
[0] + 0x10;
9051 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
9052 where_to_put_displacement
= &opcode
[2];
9055 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
9060 where_to_put_displacement
= &opcode
[3];
9064 BAD_CASE (fragP
->fr_subtype
);
9069 /* If size if less then four we are sure that the operand fits,
9070 but if it's 4, then it could be that the displacement is larger
9072 if (DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
) == 4
9074 && ((addressT
) (displacement_from_opcode_start
- extension
9075 + ((addressT
) 1 << 31))
9076 > (((addressT
) 2 << 31) - 1)))
9078 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
9079 _("jump target out of range"));
9080 /* Make us emit 0. */
9081 displacement_from_opcode_start
= extension
;
9083 /* Now put displacement after opcode. */
9084 md_number_to_chars ((char *) where_to_put_displacement
,
9085 (valueT
) (displacement_from_opcode_start
- extension
),
9086 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
9087 fragP
->fr_fix
+= extension
;
9090 /* Apply a fixup (fixP) to segment data, once it has been determined
9091 by our caller that we have all the info we need to fix it up.
9093 Parameter valP is the pointer to the value of the bits.
9095 On the 386, immediates, displacements, and data pointers are all in
9096 the same (little-endian) format, so we don't need to care about which
9100 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
9102 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
9103 valueT value
= *valP
;
9105 #if !defined (TE_Mach)
9108 switch (fixP
->fx_r_type
)
9114 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
9117 case BFD_RELOC_X86_64_32S
:
9118 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
9121 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
9124 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
9129 if (fixP
->fx_addsy
!= NULL
9130 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
9131 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
9132 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
9133 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
9134 || fixP
->fx_r_type
== BFD_RELOC_X86_64_PC32_BND
)
9135 && !use_rela_relocations
)
9137 /* This is a hack. There should be a better way to handle this.
9138 This covers for the fact that bfd_install_relocation will
9139 subtract the current location (for partial_inplace, PC relative
9140 relocations); see more below. */
9144 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
9147 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
9149 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9152 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
9155 || (symbol_section_p (fixP
->fx_addsy
)
9156 && sym_seg
!= absolute_section
))
9157 && !generic_force_reloc (fixP
))
9159 /* Yes, we add the values in twice. This is because
9160 bfd_install_relocation subtracts them out again. I think
9161 bfd_install_relocation is broken, but I don't dare change
9163 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
9167 #if defined (OBJ_COFF) && defined (TE_PE)
9168 /* For some reason, the PE format does not store a
9169 section address offset for a PC relative symbol. */
9170 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
9171 || S_IS_WEAK (fixP
->fx_addsy
))
9172 value
+= md_pcrel_from (fixP
);
9175 #if defined (OBJ_COFF) && defined (TE_PE)
9176 if (fixP
->fx_addsy
!= NULL
9177 && S_IS_WEAK (fixP
->fx_addsy
)
9178 /* PR 16858: Do not modify weak function references. */
9179 && ! fixP
->fx_pcrel
)
9181 #if !defined (TE_PEP)
9182 /* For x86 PE weak function symbols are neither PC-relative
9183 nor do they set S_IS_FUNCTION. So the only reliable way
9184 to detect them is to check the flags of their containing
9186 if (S_GET_SEGMENT (fixP
->fx_addsy
) != NULL
9187 && S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_CODE
)
9191 value
-= S_GET_VALUE (fixP
->fx_addsy
);
9195 /* Fix a few things - the dynamic linker expects certain values here,
9196 and we must not disappoint it. */
9197 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9198 if (IS_ELF
&& fixP
->fx_addsy
)
9199 switch (fixP
->fx_r_type
)
9201 case BFD_RELOC_386_PLT32
:
9202 case BFD_RELOC_X86_64_PLT32
:
9203 case BFD_RELOC_X86_64_PLT32_BND
:
9204 /* Make the jump instruction point to the address of the operand. At
9205 runtime we merely add the offset to the actual PLT entry. */
9209 case BFD_RELOC_386_TLS_GD
:
9210 case BFD_RELOC_386_TLS_LDM
:
9211 case BFD_RELOC_386_TLS_IE_32
:
9212 case BFD_RELOC_386_TLS_IE
:
9213 case BFD_RELOC_386_TLS_GOTIE
:
9214 case BFD_RELOC_386_TLS_GOTDESC
:
9215 case BFD_RELOC_X86_64_TLSGD
:
9216 case BFD_RELOC_X86_64_TLSLD
:
9217 case BFD_RELOC_X86_64_GOTTPOFF
:
9218 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
9219 value
= 0; /* Fully resolved at runtime. No addend. */
9221 case BFD_RELOC_386_TLS_LE
:
9222 case BFD_RELOC_386_TLS_LDO_32
:
9223 case BFD_RELOC_386_TLS_LE_32
:
9224 case BFD_RELOC_X86_64_DTPOFF32
:
9225 case BFD_RELOC_X86_64_DTPOFF64
:
9226 case BFD_RELOC_X86_64_TPOFF32
:
9227 case BFD_RELOC_X86_64_TPOFF64
:
9228 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
9231 case BFD_RELOC_386_TLS_DESC_CALL
:
9232 case BFD_RELOC_X86_64_TLSDESC_CALL
:
9233 value
= 0; /* Fully resolved at runtime. No addend. */
9234 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
9238 case BFD_RELOC_386_GOT32
:
9239 case BFD_RELOC_X86_64_GOT32
:
9240 value
= 0; /* Fully resolved at runtime. No addend. */
9243 case BFD_RELOC_VTABLE_INHERIT
:
9244 case BFD_RELOC_VTABLE_ENTRY
:
9251 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
9253 #endif /* !defined (TE_Mach) */
9255 /* Are we finished with this relocation now? */
9256 if (fixP
->fx_addsy
== NULL
)
9258 #if defined (OBJ_COFF) && defined (TE_PE)
9259 else if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
9262 /* Remember value for tc_gen_reloc. */
9263 fixP
->fx_addnumber
= value
;
9264 /* Clear out the frag for now. */
9268 else if (use_rela_relocations
)
9270 fixP
->fx_no_overflow
= 1;
9271 /* Remember value for tc_gen_reloc. */
9272 fixP
->fx_addnumber
= value
;
9276 md_number_to_chars (p
, value
, fixP
->fx_size
);
9280 md_atof (int type
, char *litP
, int *sizeP
)
9282 /* This outputs the LITTLENUMs in REVERSE order;
9283 in accord with the bigendian 386. */
9284 return ieee_md_atof (type
, litP
, sizeP
, FALSE
);
9287 static char output_invalid_buf
[sizeof (unsigned char) * 2 + 6];
9290 output_invalid (int c
)
9293 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
9296 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
9297 "(0x%x)", (unsigned char) c
);
9298 return output_invalid_buf
;
9301 /* REG_STRING starts *before* REGISTER_PREFIX. */
9303 static const reg_entry
*
9304 parse_real_register (char *reg_string
, char **end_op
)
9306 char *s
= reg_string
;
9308 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
9311 /* Skip possible REGISTER_PREFIX and possible whitespace. */
9312 if (*s
== REGISTER_PREFIX
)
9315 if (is_space_char (*s
))
9319 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
9321 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
9322 return (const reg_entry
*) NULL
;
9326 /* For naked regs, make sure that we are not dealing with an identifier.
9327 This prevents confusing an identifier like `eax_var' with register
9329 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
9330 return (const reg_entry
*) NULL
;
9334 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
9336 /* Handle floating point regs, allowing spaces in the (i) part. */
9337 if (r
== i386_regtab
/* %st is first entry of table */)
9339 if (is_space_char (*s
))
9344 if (is_space_char (*s
))
9346 if (*s
>= '0' && *s
<= '7')
9350 if (is_space_char (*s
))
9355 r
= (const reg_entry
*) hash_find (reg_hash
, "st(0)");
9360 /* We have "%st(" then garbage. */
9361 return (const reg_entry
*) NULL
;
9365 if (r
== NULL
|| allow_pseudo_reg
)
9368 if (operand_type_all_zero (&r
->reg_type
))
9369 return (const reg_entry
*) NULL
;
9371 if ((r
->reg_type
.bitfield
.reg32
9372 || r
->reg_type
.bitfield
.sreg3
9373 || r
->reg_type
.bitfield
.control
9374 || r
->reg_type
.bitfield
.debug
9375 || r
->reg_type
.bitfield
.test
)
9376 && !cpu_arch_flags
.bitfield
.cpui386
)
9377 return (const reg_entry
*) NULL
;
9379 if (r
->reg_type
.bitfield
.floatreg
9380 && !cpu_arch_flags
.bitfield
.cpu8087
9381 && !cpu_arch_flags
.bitfield
.cpu287
9382 && !cpu_arch_flags
.bitfield
.cpu387
)
9383 return (const reg_entry
*) NULL
;
9385 if (r
->reg_type
.bitfield
.regmmx
&& !cpu_arch_flags
.bitfield
.cpummx
)
9386 return (const reg_entry
*) NULL
;
9388 if (r
->reg_type
.bitfield
.regxmm
&& !cpu_arch_flags
.bitfield
.cpusse
)
9389 return (const reg_entry
*) NULL
;
9391 if (r
->reg_type
.bitfield
.regymm
&& !cpu_arch_flags
.bitfield
.cpuavx
)
9392 return (const reg_entry
*) NULL
;
9394 if ((r
->reg_type
.bitfield
.regzmm
|| r
->reg_type
.bitfield
.regmask
)
9395 && !cpu_arch_flags
.bitfield
.cpuavx512f
)
9396 return (const reg_entry
*) NULL
;
9398 /* Don't allow fake index register unless allow_index_reg isn't 0. */
9399 if (!allow_index_reg
9400 && (r
->reg_num
== RegEiz
|| r
->reg_num
== RegRiz
))
9401 return (const reg_entry
*) NULL
;
9403 /* Upper 16 vector register is only available with VREX in 64bit
9405 if ((r
->reg_flags
& RegVRex
))
9407 if (!cpu_arch_flags
.bitfield
.cpuvrex
9408 || flag_code
!= CODE_64BIT
)
9409 return (const reg_entry
*) NULL
;
9414 if (((r
->reg_flags
& (RegRex64
| RegRex
))
9415 || r
->reg_type
.bitfield
.reg64
)
9416 && (!cpu_arch_flags
.bitfield
.cpulm
9417 || !operand_type_equal (&r
->reg_type
, &control
))
9418 && flag_code
!= CODE_64BIT
)
9419 return (const reg_entry
*) NULL
;
9421 if (r
->reg_type
.bitfield
.sreg3
&& r
->reg_num
== RegFlat
&& !intel_syntax
)
9422 return (const reg_entry
*) NULL
;
9427 /* REG_STRING starts *before* REGISTER_PREFIX. */
9429 static const reg_entry
*
9430 parse_register (char *reg_string
, char **end_op
)
9434 if (*reg_string
== REGISTER_PREFIX
|| allow_naked_reg
)
9435 r
= parse_real_register (reg_string
, end_op
);
9440 char *save
= input_line_pointer
;
9444 input_line_pointer
= reg_string
;
9445 c
= get_symbol_end ();
9446 symbolP
= symbol_find (reg_string
);
9447 if (symbolP
&& S_GET_SEGMENT (symbolP
) == reg_section
)
9449 const expressionS
*e
= symbol_get_value_expression (symbolP
);
9451 know (e
->X_op
== O_register
);
9452 know (e
->X_add_number
>= 0
9453 && (valueT
) e
->X_add_number
< i386_regtab_size
);
9454 r
= i386_regtab
+ e
->X_add_number
;
9455 if ((r
->reg_flags
& RegVRex
))
9457 *end_op
= input_line_pointer
;
9459 *input_line_pointer
= c
;
9460 input_line_pointer
= save
;
9466 i386_parse_name (char *name
, expressionS
*e
, char *nextcharP
)
9469 char *end
= input_line_pointer
;
9472 r
= parse_register (name
, &input_line_pointer
);
9473 if (r
&& end
<= input_line_pointer
)
9475 *nextcharP
= *input_line_pointer
;
9476 *input_line_pointer
= 0;
9477 e
->X_op
= O_register
;
9478 e
->X_add_number
= r
- i386_regtab
;
9481 input_line_pointer
= end
;
9483 return intel_syntax
? i386_intel_parse_name (name
, e
) : 0;
9487 md_operand (expressionS
*e
)
9492 switch (*input_line_pointer
)
9494 case REGISTER_PREFIX
:
9495 r
= parse_real_register (input_line_pointer
, &end
);
9498 e
->X_op
= O_register
;
9499 e
->X_add_number
= r
- i386_regtab
;
9500 input_line_pointer
= end
;
9505 gas_assert (intel_syntax
);
9506 end
= input_line_pointer
++;
9508 if (*input_line_pointer
== ']')
9510 ++input_line_pointer
;
9511 e
->X_op_symbol
= make_expr_symbol (e
);
9512 e
->X_add_symbol
= NULL
;
9513 e
->X_add_number
= 0;
9519 input_line_pointer
= end
;
9526 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9527 const char *md_shortopts
= "kVQ:sqn";
9529 const char *md_shortopts
= "qn";
9532 #define OPTION_32 (OPTION_MD_BASE + 0)
9533 #define OPTION_64 (OPTION_MD_BASE + 1)
9534 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
9535 #define OPTION_MARCH (OPTION_MD_BASE + 3)
9536 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
9537 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
9538 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
9539 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
9540 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
9541 #define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
9542 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
9543 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
9544 #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
9545 #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
9546 #define OPTION_X32 (OPTION_MD_BASE + 14)
9547 #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
9548 #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
9549 #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
9550 #define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
9551 #define OPTION_OMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
9552 #define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
9554 struct option md_longopts
[] =
9556 {"32", no_argument
, NULL
, OPTION_32
},
9557 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
9558 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
9559 {"64", no_argument
, NULL
, OPTION_64
},
9561 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9562 {"x32", no_argument
, NULL
, OPTION_X32
},
9564 {"divide", no_argument
, NULL
, OPTION_DIVIDE
},
9565 {"march", required_argument
, NULL
, OPTION_MARCH
},
9566 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
9567 {"mmnemonic", required_argument
, NULL
, OPTION_MMNEMONIC
},
9568 {"msyntax", required_argument
, NULL
, OPTION_MSYNTAX
},
9569 {"mindex-reg", no_argument
, NULL
, OPTION_MINDEX_REG
},
9570 {"mnaked-reg", no_argument
, NULL
, OPTION_MNAKED_REG
},
9571 {"mold-gcc", no_argument
, NULL
, OPTION_MOLD_GCC
},
9572 {"msse2avx", no_argument
, NULL
, OPTION_MSSE2AVX
},
9573 {"msse-check", required_argument
, NULL
, OPTION_MSSE_CHECK
},
9574 {"moperand-check", required_argument
, NULL
, OPTION_MOPERAND_CHECK
},
9575 {"mavxscalar", required_argument
, NULL
, OPTION_MAVXSCALAR
},
9576 {"madd-bnd-prefix", no_argument
, NULL
, OPTION_MADD_BND_PREFIX
},
9577 {"mevexlig", required_argument
, NULL
, OPTION_MEVEXLIG
},
9578 {"mevexwig", required_argument
, NULL
, OPTION_MEVEXWIG
},
9579 # if defined (TE_PE) || defined (TE_PEP)
9580 {"mbig-obj", no_argument
, NULL
, OPTION_MBIG_OBJ
},
9582 {"momit-lock-prefix", required_argument
, NULL
, OPTION_OMIT_LOCK_PREFIX
},
9583 {"mevexrcig", required_argument
, NULL
, OPTION_MEVEXRCIG
},
9584 {NULL
, no_argument
, NULL
, 0}
9586 size_t md_longopts_size
= sizeof (md_longopts
);
9589 md_parse_option (int c
, char *arg
)
9597 optimize_align_code
= 0;
9604 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9605 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
9606 should be emitted or not. FIXME: Not implemented. */
9610 /* -V: SVR4 argument to print version ID. */
9612 print_version_id ();
9615 /* -k: Ignore for FreeBSD compatibility. */
9620 /* -s: On i386 Solaris, this tells the native assembler to use
9621 .stab instead of .stab.excl. We always use .stab anyhow. */
9624 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
9625 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
9628 const char **list
, **l
;
9630 list
= bfd_target_list ();
9631 for (l
= list
; *l
!= NULL
; l
++)
9632 if (CONST_STRNEQ (*l
, "elf64-x86-64")
9633 || strcmp (*l
, "coff-x86-64") == 0
9634 || strcmp (*l
, "pe-x86-64") == 0
9635 || strcmp (*l
, "pei-x86-64") == 0
9636 || strcmp (*l
, "mach-o-x86-64") == 0)
9638 default_arch
= "x86_64";
9642 as_fatal (_("no compiled in support for x86_64"));
9648 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9652 const char **list
, **l
;
9654 list
= bfd_target_list ();
9655 for (l
= list
; *l
!= NULL
; l
++)
9656 if (CONST_STRNEQ (*l
, "elf32-x86-64"))
9658 default_arch
= "x86_64:32";
9662 as_fatal (_("no compiled in support for 32bit x86_64"));
9666 as_fatal (_("32bit x86_64 is only supported for ELF"));
9671 default_arch
= "i386";
9675 #ifdef SVR4_COMMENT_CHARS
9680 n
= (char *) xmalloc (strlen (i386_comment_chars
) + 1);
9682 for (s
= i386_comment_chars
; *s
!= '\0'; s
++)
9686 i386_comment_chars
= n
;
9692 arch
= xstrdup (arg
);
9696 as_fatal (_("invalid -march= option: `%s'"), arg
);
9697 next
= strchr (arch
, '+');
9700 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
9702 if (strcmp (arch
, cpu_arch
[j
].name
) == 0)
9705 if (! cpu_arch
[j
].flags
.bitfield
.cpui386
)
9708 cpu_arch_name
= cpu_arch
[j
].name
;
9709 cpu_sub_arch_name
= NULL
;
9710 cpu_arch_flags
= cpu_arch
[j
].flags
;
9711 cpu_arch_isa
= cpu_arch
[j
].type
;
9712 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
9713 if (!cpu_arch_tune_set
)
9715 cpu_arch_tune
= cpu_arch_isa
;
9716 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
9720 else if (*cpu_arch
[j
].name
== '.'
9721 && strcmp (arch
, cpu_arch
[j
].name
+ 1) == 0)
9723 /* ISA entension. */
9724 i386_cpu_flags flags
;
9726 if (!cpu_arch
[j
].negated
)
9727 flags
= cpu_flags_or (cpu_arch_flags
,
9730 flags
= cpu_flags_and_not (cpu_arch_flags
,
9732 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
9734 if (cpu_sub_arch_name
)
9736 char *name
= cpu_sub_arch_name
;
9737 cpu_sub_arch_name
= concat (name
,
9739 (const char *) NULL
);
9743 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
9744 cpu_arch_flags
= flags
;
9745 cpu_arch_isa_flags
= flags
;
9751 if (j
>= ARRAY_SIZE (cpu_arch
))
9752 as_fatal (_("invalid -march= option: `%s'"), arg
);
9756 while (next
!= NULL
);
9761 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
9762 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
9764 if (strcmp (arg
, cpu_arch
[j
].name
) == 0)
9766 cpu_arch_tune_set
= 1;
9767 cpu_arch_tune
= cpu_arch
[j
].type
;
9768 cpu_arch_tune_flags
= cpu_arch
[j
].flags
;
9772 if (j
>= ARRAY_SIZE (cpu_arch
))
9773 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
9776 case OPTION_MMNEMONIC
:
9777 if (strcasecmp (arg
, "att") == 0)
9779 else if (strcasecmp (arg
, "intel") == 0)
9782 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg
);
9785 case OPTION_MSYNTAX
:
9786 if (strcasecmp (arg
, "att") == 0)
9788 else if (strcasecmp (arg
, "intel") == 0)
9791 as_fatal (_("invalid -msyntax= option: `%s'"), arg
);
9794 case OPTION_MINDEX_REG
:
9795 allow_index_reg
= 1;
9798 case OPTION_MNAKED_REG
:
9799 allow_naked_reg
= 1;
9802 case OPTION_MOLD_GCC
:
9806 case OPTION_MSSE2AVX
:
9810 case OPTION_MSSE_CHECK
:
9811 if (strcasecmp (arg
, "error") == 0)
9812 sse_check
= check_error
;
9813 else if (strcasecmp (arg
, "warning") == 0)
9814 sse_check
= check_warning
;
9815 else if (strcasecmp (arg
, "none") == 0)
9816 sse_check
= check_none
;
9818 as_fatal (_("invalid -msse-check= option: `%s'"), arg
);
9821 case OPTION_MOPERAND_CHECK
:
9822 if (strcasecmp (arg
, "error") == 0)
9823 operand_check
= check_error
;
9824 else if (strcasecmp (arg
, "warning") == 0)
9825 operand_check
= check_warning
;
9826 else if (strcasecmp (arg
, "none") == 0)
9827 operand_check
= check_none
;
9829 as_fatal (_("invalid -moperand-check= option: `%s'"), arg
);
9832 case OPTION_MAVXSCALAR
:
9833 if (strcasecmp (arg
, "128") == 0)
9835 else if (strcasecmp (arg
, "256") == 0)
9838 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg
);
9841 case OPTION_MADD_BND_PREFIX
:
9845 case OPTION_MEVEXLIG
:
9846 if (strcmp (arg
, "128") == 0)
9848 else if (strcmp (arg
, "256") == 0)
9850 else if (strcmp (arg
, "512") == 0)
9853 as_fatal (_("invalid -mevexlig= option: `%s'"), arg
);
9856 case OPTION_MEVEXRCIG
:
9857 if (strcmp (arg
, "rne") == 0)
9859 else if (strcmp (arg
, "rd") == 0)
9861 else if (strcmp (arg
, "ru") == 0)
9863 else if (strcmp (arg
, "rz") == 0)
9866 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg
);
9869 case OPTION_MEVEXWIG
:
9870 if (strcmp (arg
, "0") == 0)
9872 else if (strcmp (arg
, "1") == 0)
9875 as_fatal (_("invalid -mevexwig= option: `%s'"), arg
);
9878 # if defined (TE_PE) || defined (TE_PEP)
9879 case OPTION_MBIG_OBJ
:
9884 case OPTION_OMIT_LOCK_PREFIX
:
9885 if (strcasecmp (arg
, "yes") == 0)
9886 omit_lock_prefix
= 1;
9887 else if (strcasecmp (arg
, "no") == 0)
9888 omit_lock_prefix
= 0;
9890 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg
);
9899 #define MESSAGE_TEMPLATE \
9903 show_arch (FILE *stream
, int ext
, int check
)
9905 static char message
[] = MESSAGE_TEMPLATE
;
9906 char *start
= message
+ 27;
9908 int size
= sizeof (MESSAGE_TEMPLATE
);
9915 left
= size
- (start
- message
);
9916 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
9918 /* Should it be skipped? */
9919 if (cpu_arch
[j
].skip
)
9922 name
= cpu_arch
[j
].name
;
9923 len
= cpu_arch
[j
].len
;
9926 /* It is an extension. Skip if we aren't asked to show it. */
9937 /* It is an processor. Skip if we show only extension. */
9940 else if (check
&& ! cpu_arch
[j
].flags
.bitfield
.cpui386
)
9942 /* It is an impossible processor - skip. */
9946 /* Reserve 2 spaces for ", " or ",\0" */
9949 /* Check if there is any room. */
9957 p
= mempcpy (p
, name
, len
);
9961 /* Output the current message now and start a new one. */
9964 fprintf (stream
, "%s\n", message
);
9966 left
= size
- (start
- message
) - len
- 2;
9968 gas_assert (left
>= 0);
9970 p
= mempcpy (p
, name
, len
);
9975 fprintf (stream
, "%s\n", message
);
9979 md_show_usage (FILE *stream
)
9981 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9982 fprintf (stream
, _("\
9984 -V print assembler version number\n\
9987 fprintf (stream
, _("\
9988 -n Do not optimize code alignment\n\
9989 -q quieten some warnings\n"));
9990 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9991 fprintf (stream
, _("\
9994 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
9995 || defined (TE_PE) || defined (TE_PEP))
9996 fprintf (stream
, _("\
9997 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
9999 #ifdef SVR4_COMMENT_CHARS
10000 fprintf (stream
, _("\
10001 --divide do not treat `/' as a comment character\n"));
10003 fprintf (stream
, _("\
10004 --divide ignored\n"));
10006 fprintf (stream
, _("\
10007 -march=CPU[,+EXTENSION...]\n\
10008 generate code for CPU and EXTENSION, CPU is one of:\n"));
10009 show_arch (stream
, 0, 1);
10010 fprintf (stream
, _("\
10011 EXTENSION is combination of:\n"));
10012 show_arch (stream
, 1, 0);
10013 fprintf (stream
, _("\
10014 -mtune=CPU optimize for CPU, CPU is one of:\n"));
10015 show_arch (stream
, 0, 0);
10016 fprintf (stream
, _("\
10017 -msse2avx encode SSE instructions with VEX prefix\n"));
10018 fprintf (stream
, _("\
10019 -msse-check=[none|error|warning]\n\
10020 check SSE instructions\n"));
10021 fprintf (stream
, _("\
10022 -moperand-check=[none|error|warning]\n\
10023 check operand combinations for validity\n"));
10024 fprintf (stream
, _("\
10025 -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n\
10027 fprintf (stream
, _("\
10028 -mevexlig=[128|256|512] encode scalar EVEX instructions with specific vector\n\
10030 fprintf (stream
, _("\
10031 -mevexwig=[0|1] encode EVEX instructions with specific EVEX.W value\n\
10032 for EVEX.W bit ignored instructions\n"));
10033 fprintf (stream
, _("\
10034 -mevexrcig=[rne|rd|ru|rz]\n\
10035 encode EVEX instructions with specific EVEX.RC value\n\
10036 for SAE-only ignored instructions\n"));
10037 fprintf (stream
, _("\
10038 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
10039 fprintf (stream
, _("\
10040 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
10041 fprintf (stream
, _("\
10042 -mindex-reg support pseudo index registers\n"));
10043 fprintf (stream
, _("\
10044 -mnaked-reg don't require `%%' prefix for registers\n"));
10045 fprintf (stream
, _("\
10046 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
10047 fprintf (stream
, _("\
10048 -madd-bnd-prefix add BND prefix for all valid branches\n"));
10049 # if defined (TE_PE) || defined (TE_PEP)
10050 fprintf (stream
, _("\
10051 -mbig-obj generate big object files\n"));
10053 fprintf (stream
, _("\
10054 -momit-lock-prefix=[no|yes]\n\
10055 strip all lock prefixes\n"));
10058 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
10059 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10060 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
10062 /* Pick the target format to use. */
10065 i386_target_format (void)
10067 if (!strncmp (default_arch
, "x86_64", 6))
10069 update_code_flag (CODE_64BIT
, 1);
10070 if (default_arch
[6] == '\0')
10071 x86_elf_abi
= X86_64_ABI
;
10073 x86_elf_abi
= X86_64_X32_ABI
;
10075 else if (!strcmp (default_arch
, "i386"))
10076 update_code_flag (CODE_32BIT
, 1);
10078 as_fatal (_("unknown architecture"));
10080 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
10081 cpu_arch_isa_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
10082 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
10083 cpu_arch_tune_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
10085 switch (OUTPUT_FLAVOR
)
10087 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
10088 case bfd_target_aout_flavour
:
10089 return AOUT_TARGET_FORMAT
;
10091 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
10092 # if defined (TE_PE) || defined (TE_PEP)
10093 case bfd_target_coff_flavour
:
10094 if (flag_code
== CODE_64BIT
)
10095 return use_big_obj
? "pe-bigobj-x86-64" : "pe-x86-64";
10098 # elif defined (TE_GO32)
10099 case bfd_target_coff_flavour
:
10100 return "coff-go32";
10102 case bfd_target_coff_flavour
:
10103 return "coff-i386";
10106 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
10107 case bfd_target_elf_flavour
:
10109 const char *format
;
10111 switch (x86_elf_abi
)
10114 format
= ELF_TARGET_FORMAT
;
10117 use_rela_relocations
= 1;
10119 format
= ELF_TARGET_FORMAT64
;
10121 case X86_64_X32_ABI
:
10122 use_rela_relocations
= 1;
10124 disallow_64bit_reloc
= 1;
10125 format
= ELF_TARGET_FORMAT32
;
10128 if (cpu_arch_isa
== PROCESSOR_L1OM
)
10130 if (x86_elf_abi
!= X86_64_ABI
)
10131 as_fatal (_("Intel L1OM is 64bit only"));
10132 return ELF_TARGET_L1OM_FORMAT
;
10134 if (cpu_arch_isa
== PROCESSOR_K1OM
)
10136 if (x86_elf_abi
!= X86_64_ABI
)
10137 as_fatal (_("Intel K1OM is 64bit only"));
10138 return ELF_TARGET_K1OM_FORMAT
;
10144 #if defined (OBJ_MACH_O)
10145 case bfd_target_mach_o_flavour
:
10146 if (flag_code
== CODE_64BIT
)
10148 use_rela_relocations
= 1;
10150 return "mach-o-x86-64";
10153 return "mach-o-i386";
10161 #endif /* OBJ_MAYBE_ more than one */
10163 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
10165 i386_elf_emit_arch_note (void)
10167 if (IS_ELF
&& cpu_arch_name
!= NULL
)
10170 asection
*seg
= now_seg
;
10171 subsegT subseg
= now_subseg
;
10172 Elf_Internal_Note i_note
;
10173 Elf_External_Note e_note
;
10174 asection
*note_secp
;
10177 /* Create the .note section. */
10178 note_secp
= subseg_new (".note", 0);
10179 bfd_set_section_flags (stdoutput
,
10181 SEC_HAS_CONTENTS
| SEC_READONLY
);
10183 /* Process the arch string. */
10184 len
= strlen (cpu_arch_name
);
10186 i_note
.namesz
= len
+ 1;
10188 i_note
.type
= NT_ARCH
;
10189 p
= frag_more (sizeof (e_note
.namesz
));
10190 md_number_to_chars (p
, (valueT
) i_note
.namesz
, sizeof (e_note
.namesz
));
10191 p
= frag_more (sizeof (e_note
.descsz
));
10192 md_number_to_chars (p
, (valueT
) i_note
.descsz
, sizeof (e_note
.descsz
));
10193 p
= frag_more (sizeof (e_note
.type
));
10194 md_number_to_chars (p
, (valueT
) i_note
.type
, sizeof (e_note
.type
));
10195 p
= frag_more (len
+ 1);
10196 strcpy (p
, cpu_arch_name
);
10198 frag_align (2, 0, 0);
10200 subseg_set (seg
, subseg
);
10206 md_undefined_symbol (char *name
)
10208 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
10209 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
10210 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
10211 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
10215 if (symbol_find (name
))
10216 as_bad (_("GOT already in symbol table"));
10217 GOT_symbol
= symbol_new (name
, undefined_section
,
10218 (valueT
) 0, &zero_address_frag
);
10225 /* Round up a section size to the appropriate boundary. */
10228 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
10230 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
10231 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
10233 /* For a.out, force the section size to be aligned. If we don't do
10234 this, BFD will align it for us, but it will not write out the
10235 final bytes of the section. This may be a bug in BFD, but it is
10236 easier to fix it here since that is how the other a.out targets
10240 align
= bfd_get_section_alignment (stdoutput
, segment
);
10241 size
= ((size
+ (1 << align
) - 1) & ((valueT
) -1 << align
));
10248 /* On the i386, PC-relative offsets are relative to the start of the
10249 next instruction. That is, the address of the offset, plus its
10250 size, since the offset is always the last part of the insn. */
10253 md_pcrel_from (fixS
*fixP
)
10255 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
10261 s_bss (int ignore ATTRIBUTE_UNUSED
)
10265 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10267 obj_elf_section_change_hook ();
10269 temp
= get_absolute_expression ();
10270 subseg_set (bss_section
, (subsegT
) temp
);
10271 demand_empty_rest_of_line ();
10277 i386_validate_fix (fixS
*fixp
)
10279 if (fixp
->fx_subsy
&& fixp
->fx_subsy
== GOT_symbol
)
10281 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
10285 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
10290 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
10292 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
10294 fixp
->fx_subsy
= 0;
10299 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
10302 bfd_reloc_code_real_type code
;
10304 switch (fixp
->fx_r_type
)
10306 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10307 case BFD_RELOC_SIZE32
:
10308 case BFD_RELOC_SIZE64
:
10309 if (S_IS_DEFINED (fixp
->fx_addsy
)
10310 && !S_IS_EXTERNAL (fixp
->fx_addsy
))
10312 /* Resolve size relocation against local symbol to size of
10313 the symbol plus addend. */
10314 valueT value
= S_GET_SIZE (fixp
->fx_addsy
) + fixp
->fx_offset
;
10315 if (fixp
->fx_r_type
== BFD_RELOC_SIZE32
10316 && !fits_in_unsigned_long (value
))
10317 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10318 _("symbol size computation overflow"));
10319 fixp
->fx_addsy
= NULL
;
10320 fixp
->fx_subsy
= NULL
;
10321 md_apply_fix (fixp
, (valueT
*) &value
, NULL
);
10326 case BFD_RELOC_X86_64_PLT32
:
10327 case BFD_RELOC_X86_64_PLT32_BND
:
10328 case BFD_RELOC_X86_64_GOT32
:
10329 case BFD_RELOC_X86_64_GOTPCREL
:
10330 case BFD_RELOC_386_PLT32
:
10331 case BFD_RELOC_386_GOT32
:
10332 case BFD_RELOC_386_GOTOFF
:
10333 case BFD_RELOC_386_GOTPC
:
10334 case BFD_RELOC_386_TLS_GD
:
10335 case BFD_RELOC_386_TLS_LDM
:
10336 case BFD_RELOC_386_TLS_LDO_32
:
10337 case BFD_RELOC_386_TLS_IE_32
:
10338 case BFD_RELOC_386_TLS_IE
:
10339 case BFD_RELOC_386_TLS_GOTIE
:
10340 case BFD_RELOC_386_TLS_LE_32
:
10341 case BFD_RELOC_386_TLS_LE
:
10342 case BFD_RELOC_386_TLS_GOTDESC
:
10343 case BFD_RELOC_386_TLS_DESC_CALL
:
10344 case BFD_RELOC_X86_64_TLSGD
:
10345 case BFD_RELOC_X86_64_TLSLD
:
10346 case BFD_RELOC_X86_64_DTPOFF32
:
10347 case BFD_RELOC_X86_64_DTPOFF64
:
10348 case BFD_RELOC_X86_64_GOTTPOFF
:
10349 case BFD_RELOC_X86_64_TPOFF32
:
10350 case BFD_RELOC_X86_64_TPOFF64
:
10351 case BFD_RELOC_X86_64_GOTOFF64
:
10352 case BFD_RELOC_X86_64_GOTPC32
:
10353 case BFD_RELOC_X86_64_GOT64
:
10354 case BFD_RELOC_X86_64_GOTPCREL64
:
10355 case BFD_RELOC_X86_64_GOTPC64
:
10356 case BFD_RELOC_X86_64_GOTPLT64
:
10357 case BFD_RELOC_X86_64_PLTOFF64
:
10358 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
10359 case BFD_RELOC_X86_64_TLSDESC_CALL
:
10360 case BFD_RELOC_RVA
:
10361 case BFD_RELOC_VTABLE_ENTRY
:
10362 case BFD_RELOC_VTABLE_INHERIT
:
10364 case BFD_RELOC_32_SECREL
:
10366 code
= fixp
->fx_r_type
;
10368 case BFD_RELOC_X86_64_32S
:
10369 if (!fixp
->fx_pcrel
)
10371 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
10372 code
= fixp
->fx_r_type
;
10376 if (fixp
->fx_pcrel
)
10378 switch (fixp
->fx_size
)
10381 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10382 _("can not do %d byte pc-relative relocation"),
10384 code
= BFD_RELOC_32_PCREL
;
10386 case 1: code
= BFD_RELOC_8_PCREL
; break;
10387 case 2: code
= BFD_RELOC_16_PCREL
; break;
10389 code
= (fixp
->fx_r_type
== BFD_RELOC_X86_64_PC32_BND
10390 ? fixp
-> fx_r_type
: BFD_RELOC_32_PCREL
);
10393 case 8: code
= BFD_RELOC_64_PCREL
; break;
10399 switch (fixp
->fx_size
)
10402 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10403 _("can not do %d byte relocation"),
10405 code
= BFD_RELOC_32
;
10407 case 1: code
= BFD_RELOC_8
; break;
10408 case 2: code
= BFD_RELOC_16
; break;
10409 case 4: code
= BFD_RELOC_32
; break;
10411 case 8: code
= BFD_RELOC_64
; break;
10418 if ((code
== BFD_RELOC_32
10419 || code
== BFD_RELOC_32_PCREL
10420 || code
== BFD_RELOC_X86_64_32S
)
10422 && fixp
->fx_addsy
== GOT_symbol
)
10425 code
= BFD_RELOC_386_GOTPC
;
10427 code
= BFD_RELOC_X86_64_GOTPC32
;
10429 if ((code
== BFD_RELOC_64
|| code
== BFD_RELOC_64_PCREL
)
10431 && fixp
->fx_addsy
== GOT_symbol
)
10433 code
= BFD_RELOC_X86_64_GOTPC64
;
10436 rel
= (arelent
*) xmalloc (sizeof (arelent
));
10437 rel
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
10438 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
10440 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
10442 if (!use_rela_relocations
)
10444 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
10445 vtable entry to be used in the relocation's section offset. */
10446 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
10447 rel
->address
= fixp
->fx_offset
;
10448 #if defined (OBJ_COFF) && defined (TE_PE)
10449 else if (fixp
->fx_addsy
&& S_IS_WEAK (fixp
->fx_addsy
))
10450 rel
->addend
= fixp
->fx_addnumber
- (S_GET_VALUE (fixp
->fx_addsy
) * 2);
10455 /* Use the rela in 64bit mode. */
10458 if (disallow_64bit_reloc
)
10461 case BFD_RELOC_X86_64_DTPOFF64
:
10462 case BFD_RELOC_X86_64_TPOFF64
:
10463 case BFD_RELOC_64_PCREL
:
10464 case BFD_RELOC_X86_64_GOTOFF64
:
10465 case BFD_RELOC_X86_64_GOT64
:
10466 case BFD_RELOC_X86_64_GOTPCREL64
:
10467 case BFD_RELOC_X86_64_GOTPC64
:
10468 case BFD_RELOC_X86_64_GOTPLT64
:
10469 case BFD_RELOC_X86_64_PLTOFF64
:
10470 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10471 _("cannot represent relocation type %s in x32 mode"),
10472 bfd_get_reloc_code_name (code
));
10478 if (!fixp
->fx_pcrel
)
10479 rel
->addend
= fixp
->fx_offset
;
10483 case BFD_RELOC_X86_64_PLT32
:
10484 case BFD_RELOC_X86_64_PLT32_BND
:
10485 case BFD_RELOC_X86_64_GOT32
:
10486 case BFD_RELOC_X86_64_GOTPCREL
:
10487 case BFD_RELOC_X86_64_TLSGD
:
10488 case BFD_RELOC_X86_64_TLSLD
:
10489 case BFD_RELOC_X86_64_GOTTPOFF
:
10490 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
10491 case BFD_RELOC_X86_64_TLSDESC_CALL
:
10492 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
10495 rel
->addend
= (section
->vma
10497 + fixp
->fx_addnumber
10498 + md_pcrel_from (fixp
));
10503 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
10504 if (rel
->howto
== NULL
)
10506 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10507 _("cannot represent relocation type %s"),
10508 bfd_get_reloc_code_name (code
));
10509 /* Set howto to a garbage value so that we can keep going. */
10510 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
10511 gas_assert (rel
->howto
!= NULL
);
10517 #include "tc-i386-intel.c"
10520 tc_x86_parse_to_dw2regnum (expressionS
*exp
)
10522 int saved_naked_reg
;
10523 char saved_register_dot
;
10525 saved_naked_reg
= allow_naked_reg
;
10526 allow_naked_reg
= 1;
10527 saved_register_dot
= register_chars
['.'];
10528 register_chars
['.'] = '.';
10529 allow_pseudo_reg
= 1;
10530 expression_and_evaluate (exp
);
10531 allow_pseudo_reg
= 0;
10532 register_chars
['.'] = saved_register_dot
;
10533 allow_naked_reg
= saved_naked_reg
;
10535 if (exp
->X_op
== O_register
&& exp
->X_add_number
>= 0)
10537 if ((addressT
) exp
->X_add_number
< i386_regtab_size
)
10539 exp
->X_op
= O_constant
;
10540 exp
->X_add_number
= i386_regtab
[exp
->X_add_number
]
10541 .dw2_regnum
[flag_code
>> 1];
10544 exp
->X_op
= O_illegal
;
10549 tc_x86_frame_initial_instructions (void)
10551 static unsigned int sp_regno
[2];
10553 if (!sp_regno
[flag_code
>> 1])
10555 char *saved_input
= input_line_pointer
;
10556 char sp
[][4] = {"esp", "rsp"};
10559 input_line_pointer
= sp
[flag_code
>> 1];
10560 tc_x86_parse_to_dw2regnum (&exp
);
10561 gas_assert (exp
.X_op
== O_constant
);
10562 sp_regno
[flag_code
>> 1] = exp
.X_add_number
;
10563 input_line_pointer
= saved_input
;
10566 cfi_add_CFA_def_cfa (sp_regno
[flag_code
>> 1], -x86_cie_data_alignment
);
10567 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
10571 x86_dwarf2_addr_size (void)
10573 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
10574 if (x86_elf_abi
== X86_64_X32_ABI
)
10577 return bfd_arch_bits_per_address (stdoutput
) / 8;
10581 i386_elf_section_type (const char *str
, size_t len
)
10583 if (flag_code
== CODE_64BIT
10584 && len
== sizeof ("unwind") - 1
10585 && strncmp (str
, "unwind", 6) == 0)
10586 return SHT_X86_64_UNWIND
;
10593 i386_solaris_fix_up_eh_frame (segT sec
)
10595 if (flag_code
== CODE_64BIT
)
10596 elf_section_type (sec
) = SHT_X86_64_UNWIND
;
10602 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
10606 exp
.X_op
= O_secrel
;
10607 exp
.X_add_symbol
= symbol
;
10608 exp
.X_add_number
= 0;
10609 emit_expr (&exp
, size
);
10613 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10614 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
10617 x86_64_section_letter (int letter
, char **ptr_msg
)
10619 if (flag_code
== CODE_64BIT
)
10622 return SHF_X86_64_LARGE
;
10624 *ptr_msg
= _("bad .section directive: want a,l,w,x,M,S,G,T in string");
10627 *ptr_msg
= _("bad .section directive: want a,w,x,M,S,G,T in string");
10632 x86_64_section_word (char *str
, size_t len
)
10634 if (len
== 5 && flag_code
== CODE_64BIT
&& CONST_STRNEQ (str
, "large"))
10635 return SHF_X86_64_LARGE
;
10641 handle_large_common (int small ATTRIBUTE_UNUSED
)
10643 if (flag_code
!= CODE_64BIT
)
10645 s_comm_internal (0, elf_common_parse
);
10646 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
10650 static segT lbss_section
;
10651 asection
*saved_com_section_ptr
= elf_com_section_ptr
;
10652 asection
*saved_bss_section
= bss_section
;
10654 if (lbss_section
== NULL
)
10656 flagword applicable
;
10657 segT seg
= now_seg
;
10658 subsegT subseg
= now_subseg
;
10660 /* The .lbss section is for local .largecomm symbols. */
10661 lbss_section
= subseg_new (".lbss", 0);
10662 applicable
= bfd_applicable_section_flags (stdoutput
);
10663 bfd_set_section_flags (stdoutput
, lbss_section
,
10664 applicable
& SEC_ALLOC
);
10665 seg_info (lbss_section
)->bss
= 1;
10667 subseg_set (seg
, subseg
);
10670 elf_com_section_ptr
= &_bfd_elf_large_com_section
;
10671 bss_section
= lbss_section
;
10673 s_comm_internal (0, elf_common_parse
);
10675 elf_com_section_ptr
= saved_com_section_ptr
;
10676 bss_section
= saved_bss_section
;
10679 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */