1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright (C) 1989-2019 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 /* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
23 x86_64 support by Jan Hubicka (jh@suse.cz)
24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
29 #include "safe-ctype.h"
31 #include "dwarf2dbg.h"
32 #include "dw2gencfi.h"
33 #include "elf/x86-64.h"
34 #include "opcodes/i386-init.h"
39 #ifdef HAVE_SYS_PARAM_H
40 #include <sys/param.h>
43 #define INT_MAX (int) (((unsigned) (-1)) >> 1)
47 #ifndef REGISTER_WARNINGS
48 #define REGISTER_WARNINGS 1
51 #ifndef INFER_ADDR_PREFIX
52 #define INFER_ADDR_PREFIX 1
56 #define DEFAULT_ARCH "i386"
61 #define INLINE __inline__
67 /* Prefixes will be emitted in the order defined below.
68 WAIT_PREFIX must be the first prefix since FWAIT is really is an
69 instruction, and so must come before any prefixes.
70 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
71 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
77 #define HLE_PREFIX REP_PREFIX
78 #define BND_PREFIX REP_PREFIX
80 #define REX_PREFIX 6 /* must come last. */
81 #define MAX_PREFIXES 7 /* max prefixes per opcode */
83 /* we define the syntax here (modulo base,index,scale syntax) */
84 #define REGISTER_PREFIX '%'
85 #define IMMEDIATE_PREFIX '$'
86 #define ABSOLUTE_PREFIX '*'
88 /* these are the instruction mnemonic suffixes in AT&T syntax or
89 memory operand size in Intel syntax. */
90 #define WORD_MNEM_SUFFIX 'w'
91 #define BYTE_MNEM_SUFFIX 'b'
92 #define SHORT_MNEM_SUFFIX 's'
93 #define LONG_MNEM_SUFFIX 'l'
94 #define QWORD_MNEM_SUFFIX 'q'
95 /* Intel Syntax. Use a non-ascii letter since since it never appears
97 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
99 #define END_OF_INSN '\0'
101 /* This matches the C -> StaticRounding alias in the opcode table. */
102 #define commutative staticrounding
105 'templates' is for grouping together 'template' structures for opcodes
106 of the same name. This is only used for storing the insns in the grand
107 ole hash table of insns.
108 The templates themselves start at START and range up to (but not including)
113 const insn_template
*start
;
114 const insn_template
*end
;
118 /* 386 operand encoding bytes: see 386 book for details of this. */
121 unsigned int regmem
; /* codes register or memory operand */
122 unsigned int reg
; /* codes register operand (or extended opcode) */
123 unsigned int mode
; /* how to interpret regmem & reg */
127 /* x86-64 extension prefix. */
128 typedef int rex_byte
;
130 /* 386 opcode byte to code indirect addressing. */
139 /* x86 arch names, types and features */
142 const char *name
; /* arch name */
143 unsigned int len
; /* arch string length */
144 enum processor_type type
; /* arch type */
145 i386_cpu_flags flags
; /* cpu feature flags */
146 unsigned int skip
; /* show_arch should skip this. */
150 /* Used to turn off indicated flags. */
153 const char *name
; /* arch name */
154 unsigned int len
; /* arch string length */
155 i386_cpu_flags flags
; /* cpu feature flags */
159 static void update_code_flag (int, int);
160 static void set_code_flag (int);
161 static void set_16bit_gcc_code_flag (int);
162 static void set_intel_syntax (int);
163 static void set_intel_mnemonic (int);
164 static void set_allow_index_reg (int);
165 static void set_check (int);
166 static void set_cpu_arch (int);
168 static void pe_directive_secrel (int);
170 static void signed_cons (int);
171 static char *output_invalid (int c
);
172 static int i386_finalize_immediate (segT
, expressionS
*, i386_operand_type
,
174 static int i386_finalize_displacement (segT
, expressionS
*, i386_operand_type
,
176 static int i386_att_operand (char *);
177 static int i386_intel_operand (char *, int);
178 static int i386_intel_simplify (expressionS
*);
179 static int i386_intel_parse_name (const char *, expressionS
*);
180 static const reg_entry
*parse_register (char *, char **);
181 static char *parse_insn (char *, char *);
182 static char *parse_operands (char *, const char *);
183 static void swap_operands (void);
184 static void swap_2_operands (int, int);
185 static void optimize_imm (void);
186 static void optimize_disp (void);
187 static const insn_template
*match_template (char);
188 static int check_string (void);
189 static int process_suffix (void);
190 static int check_byte_reg (void);
191 static int check_long_reg (void);
192 static int check_qword_reg (void);
193 static int check_word_reg (void);
194 static int finalize_imm (void);
195 static int process_operands (void);
196 static const seg_entry
*build_modrm_byte (void);
197 static void output_insn (void);
198 static void output_imm (fragS
*, offsetT
);
199 static void output_disp (fragS
*, offsetT
);
201 static void s_bss (int);
203 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
204 static void handle_large_common (int small ATTRIBUTE_UNUSED
);
206 /* GNU_PROPERTY_X86_ISA_1_USED. */
207 static unsigned int x86_isa_1_used
;
208 /* GNU_PROPERTY_X86_FEATURE_2_USED. */
209 static unsigned int x86_feature_2_used
;
210 /* Generate x86 used ISA and feature properties. */
211 static unsigned int x86_used_note
= DEFAULT_X86_USED_NOTE
;
214 static const char *default_arch
= DEFAULT_ARCH
;
216 /* This struct describes rounding control and SAE in the instruction. */
230 static struct RC_Operation rc_op
;
232 /* The struct describes masking, applied to OPERAND in the instruction.
233 MASK is a pointer to the corresponding mask register. ZEROING tells
234 whether merging or zeroing mask is used. */
235 struct Mask_Operation
237 const reg_entry
*mask
;
238 unsigned int zeroing
;
239 /* The operand where this operation is associated. */
243 static struct Mask_Operation mask_op
;
245 /* The struct describes broadcasting, applied to OPERAND. FACTOR is
247 struct Broadcast_Operation
249 /* Type of broadcast: {1to2}, {1to4}, {1to8}, or {1to16}. */
252 /* Index of broadcasted operand. */
255 /* Number of bytes to broadcast. */
259 static struct Broadcast_Operation broadcast_op
;
264 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
265 unsigned char bytes
[4];
267 /* Destination or source register specifier. */
268 const reg_entry
*register_specifier
;
271 /* 'md_assemble ()' gathers together information and puts it into a
278 const reg_entry
*regs
;
283 operand_size_mismatch
,
284 operand_type_mismatch
,
285 register_type_mismatch
,
286 number_of_operands_mismatch
,
287 invalid_instruction_suffix
,
289 unsupported_with_intel_mnemonic
,
292 invalid_vsib_address
,
293 invalid_vector_register_set
,
294 unsupported_vector_index_register
,
295 unsupported_broadcast
,
298 mask_not_on_destination
,
301 rc_sae_operand_not_last_imm
,
302 invalid_register_operand
,
307 /* TM holds the template for the insn were currently assembling. */
310 /* SUFFIX holds the instruction size suffix for byte, word, dword
311 or qword, if given. */
314 /* OPERANDS gives the number of given operands. */
315 unsigned int operands
;
317 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
318 of given register, displacement, memory operands and immediate
320 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
322 /* TYPES [i] is the type (see above #defines) which tells us how to
323 use OP[i] for the corresponding operand. */
324 i386_operand_type types
[MAX_OPERANDS
];
326 /* Displacement expression, immediate expression, or register for each
328 union i386_op op
[MAX_OPERANDS
];
330 /* Flags for operands. */
331 unsigned int flags
[MAX_OPERANDS
];
332 #define Operand_PCrel 1
333 #define Operand_Mem 2
335 /* Relocation type for operand */
336 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
338 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
339 the base index byte below. */
340 const reg_entry
*base_reg
;
341 const reg_entry
*index_reg
;
342 unsigned int log2_scale_factor
;
344 /* SEG gives the seg_entries of this insn. They are zero unless
345 explicit segment overrides are given. */
346 const seg_entry
*seg
[2];
348 /* Copied first memory operand string, for re-checking. */
351 /* PREFIX holds all the given prefix opcodes (usually null).
352 PREFIXES is the number of prefix opcodes. */
353 unsigned int prefixes
;
354 unsigned char prefix
[MAX_PREFIXES
];
356 /* The operand to a branch insn indicates an absolute branch. */
357 bfd_boolean jumpabsolute
;
359 /* Has MMX register operands. */
360 bfd_boolean has_regmmx
;
362 /* Has XMM register operands. */
363 bfd_boolean has_regxmm
;
365 /* Has YMM register operands. */
366 bfd_boolean has_regymm
;
368 /* Has ZMM register operands. */
369 bfd_boolean has_regzmm
;
371 /* RM and SIB are the modrm byte and the sib byte where the
372 addressing modes of this insn are encoded. */
379 /* Masking attributes. */
380 struct Mask_Operation
*mask
;
382 /* Rounding control and SAE attributes. */
383 struct RC_Operation
*rounding
;
385 /* Broadcasting attributes. */
386 struct Broadcast_Operation
*broadcast
;
388 /* Compressed disp8*N attribute. */
389 unsigned int memshift
;
391 /* Prefer load or store in encoding. */
394 dir_encoding_default
= 0,
400 /* Prefer 8bit or 32bit displacement in encoding. */
403 disp_encoding_default
= 0,
408 /* Prefer the REX byte in encoding. */
409 bfd_boolean rex_encoding
;
411 /* Disable instruction size optimization. */
412 bfd_boolean no_optimize
;
414 /* How to encode vector instructions. */
417 vex_encoding_default
= 0,
424 const char *rep_prefix
;
427 const char *hle_prefix
;
429 /* Have BND prefix. */
430 const char *bnd_prefix
;
432 /* Have NOTRACK prefix. */
433 const char *notrack_prefix
;
436 enum i386_error error
;
439 typedef struct _i386_insn i386_insn
;
441 /* Link RC type with corresponding string, that'll be looked for in
450 static const struct RC_name RC_NamesTable
[] =
452 { rne
, STRING_COMMA_LEN ("rn-sae") },
453 { rd
, STRING_COMMA_LEN ("rd-sae") },
454 { ru
, STRING_COMMA_LEN ("ru-sae") },
455 { rz
, STRING_COMMA_LEN ("rz-sae") },
456 { saeonly
, STRING_COMMA_LEN ("sae") },
459 /* List of chars besides those in app.c:symbol_chars that can start an
460 operand. Used to prevent the scrubber eating vital white-space. */
461 const char extra_symbol_chars
[] = "*%-([{}"
470 #if (defined (TE_I386AIX) \
471 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
472 && !defined (TE_GNU) \
473 && !defined (TE_LINUX) \
474 && !defined (TE_NACL) \
475 && !defined (TE_FreeBSD) \
476 && !defined (TE_DragonFly) \
477 && !defined (TE_NetBSD)))
478 /* This array holds the chars that always start a comment. If the
479 pre-processor is disabled, these aren't very useful. The option
480 --divide will remove '/' from this list. */
481 const char *i386_comment_chars
= "#/";
482 #define SVR4_COMMENT_CHARS 1
483 #define PREFIX_SEPARATOR '\\'
486 const char *i386_comment_chars
= "#";
487 #define PREFIX_SEPARATOR '/'
490 /* This array holds the chars that only start a comment at the beginning of
491 a line. If the line seems to have the form '# 123 filename'
492 .line and .file directives will appear in the pre-processed output.
493 Note that input_file.c hand checks for '#' at the beginning of the
494 first line of the input file. This is because the compiler outputs
495 #NO_APP at the beginning of its output.
496 Also note that comments started like this one will always work if
497 '/' isn't otherwise defined. */
498 const char line_comment_chars
[] = "#/";
500 const char line_separator_chars
[] = ";";
502 /* Chars that can be used to separate mant from exp in floating point
504 const char EXP_CHARS
[] = "eE";
506 /* Chars that mean this number is a floating point constant
509 const char FLT_CHARS
[] = "fFdDxX";
511 /* Tables for lexical analysis. */
512 static char mnemonic_chars
[256];
513 static char register_chars
[256];
514 static char operand_chars
[256];
515 static char identifier_chars
[256];
516 static char digit_chars
[256];
518 /* Lexical macros. */
519 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
520 #define is_operand_char(x) (operand_chars[(unsigned char) x])
521 #define is_register_char(x) (register_chars[(unsigned char) x])
522 #define is_space_char(x) ((x) == ' ')
523 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
524 #define is_digit_char(x) (digit_chars[(unsigned char) x])
526 /* All non-digit non-letter characters that may occur in an operand. */
527 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
529 /* md_assemble() always leaves the strings it's passed unaltered. To
530 effect this we maintain a stack of saved characters that we've smashed
531 with '\0's (indicating end of strings for various sub-fields of the
532 assembler instruction). */
533 static char save_stack
[32];
534 static char *save_stack_p
;
535 #define END_STRING_AND_SAVE(s) \
536 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
537 #define RESTORE_END_STRING(s) \
538 do { *(s) = *--save_stack_p; } while (0)
540 /* The instruction we're assembling. */
543 /* Possible templates for current insn. */
544 static const templates
*current_templates
;
546 /* Per instruction expressionS buffers: max displacements & immediates. */
547 static expressionS disp_expressions
[MAX_MEMORY_OPERANDS
];
548 static expressionS im_expressions
[MAX_IMMEDIATE_OPERANDS
];
550 /* Current operand we are working on. */
551 static int this_operand
= -1;
553 /* We support four different modes. FLAG_CODE variable is used to distinguish
561 static enum flag_code flag_code
;
562 static unsigned int object_64bit
;
563 static unsigned int disallow_64bit_reloc
;
564 static int use_rela_relocations
= 0;
566 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
567 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
568 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
570 /* The ELF ABI to use. */
578 static enum x86_elf_abi x86_elf_abi
= I386_ABI
;
581 #if defined (TE_PE) || defined (TE_PEP)
582 /* Use big object file format. */
583 static int use_big_obj
= 0;
586 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
587 /* 1 if generating code for a shared library. */
588 static int shared
= 0;
591 /* 1 for intel syntax,
593 static int intel_syntax
= 0;
595 /* 1 for Intel64 ISA,
599 /* 1 for intel mnemonic,
600 0 if att mnemonic. */
601 static int intel_mnemonic
= !SYSV386_COMPAT
;
603 /* 1 if pseudo registers are permitted. */
604 static int allow_pseudo_reg
= 0;
606 /* 1 if register prefix % not required. */
607 static int allow_naked_reg
= 0;
609 /* 1 if the assembler should add BND prefix for all control-transferring
610 instructions supporting it, even if this prefix wasn't specified
612 static int add_bnd_prefix
= 0;
614 /* 1 if pseudo index register, eiz/riz, is allowed . */
615 static int allow_index_reg
= 0;
617 /* 1 if the assembler should ignore LOCK prefix, even if it was
618 specified explicitly. */
619 static int omit_lock_prefix
= 0;
621 /* 1 if the assembler should encode lfence, mfence, and sfence as
622 "lock addl $0, (%{re}sp)". */
623 static int avoid_fence
= 0;
625 /* 1 if the assembler should generate relax relocations. */
627 static int generate_relax_relocations
628 = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS
;
630 static enum check_kind
636 sse_check
, operand_check
= check_warning
;
639 1. Clear the REX_W bit with register operand if possible.
640 2. Above plus use 128bit vector instruction to clear the full vector
643 static int optimize
= 0;
646 1. Clear the REX_W bit with register operand if possible.
647 2. Above plus use 128bit vector instruction to clear the full vector
649 3. Above plus optimize "test{q,l,w} $imm8,%r{64,32,16}" to
652 static int optimize_for_space
= 0;
654 /* Register prefix used for error message. */
655 static const char *register_prefix
= "%";
657 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
658 leave, push, and pop instructions so that gcc has the same stack
659 frame as in 32 bit mode. */
660 static char stackop_size
= '\0';
662 /* Non-zero to optimize code alignment. */
663 int optimize_align_code
= 1;
665 /* Non-zero to quieten some warnings. */
666 static int quiet_warnings
= 0;
669 static const char *cpu_arch_name
= NULL
;
670 static char *cpu_sub_arch_name
= NULL
;
672 /* CPU feature flags. */
673 static i386_cpu_flags cpu_arch_flags
= CPU_UNKNOWN_FLAGS
;
675 /* If we have selected a cpu we are generating instructions for. */
676 static int cpu_arch_tune_set
= 0;
678 /* Cpu we are generating instructions for. */
679 enum processor_type cpu_arch_tune
= PROCESSOR_UNKNOWN
;
681 /* CPU feature flags of cpu we are generating instructions for. */
682 static i386_cpu_flags cpu_arch_tune_flags
;
684 /* CPU instruction set architecture used. */
685 enum processor_type cpu_arch_isa
= PROCESSOR_UNKNOWN
;
687 /* CPU feature flags of instruction set architecture used. */
688 i386_cpu_flags cpu_arch_isa_flags
;
690 /* If set, conditional jumps are not automatically promoted to handle
691 larger than a byte offset. */
692 static unsigned int no_cond_jump_promotion
= 0;
694 /* Encode SSE instructions with VEX prefix. */
695 static unsigned int sse2avx
;
697 /* Encode scalar AVX instructions with specific vector length. */
704 /* Encode VEX WIG instructions with specific vex.w. */
711 /* Encode scalar EVEX LIG instructions with specific vector length. */
719 /* Encode EVEX WIG instructions with specific evex.w. */
726 /* Value to encode in EVEX RC bits, for SAE-only instructions. */
727 static enum rc_type evexrcig
= rne
;
729 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
730 static symbolS
*GOT_symbol
;
732 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
733 unsigned int x86_dwarf2_return_column
;
735 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
736 int x86_cie_data_alignment
;
738 /* Interface to relax_segment.
739 There are 3 major relax states for 386 jump insns because the
740 different types of jumps add different sizes to frags when we're
741 figuring out what sort of jump to choose to reach a given label. */
744 #define UNCOND_JUMP 0
746 #define COND_JUMP86 2
751 #define SMALL16 (SMALL | CODE16)
753 #define BIG16 (BIG | CODE16)
757 #define INLINE __inline__
763 #define ENCODE_RELAX_STATE(type, size) \
764 ((relax_substateT) (((type) << 2) | (size)))
765 #define TYPE_FROM_RELAX_STATE(s) \
767 #define DISP_SIZE_FROM_RELAX_STATE(s) \
768 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
770 /* This table is used by relax_frag to promote short jumps to long
771 ones where necessary. SMALL (short) jumps may be promoted to BIG
772 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
773 don't allow a short jump in a 32 bit code segment to be promoted to
774 a 16 bit offset jump because it's slower (requires data size
775 prefix), and doesn't work, unless the destination is in the bottom
776 64k of the code segment (The top 16 bits of eip are zeroed). */
778 const relax_typeS md_relax_table
[] =
781 1) most positive reach of this state,
782 2) most negative reach of this state,
783 3) how many bytes this mode will have in the variable part of the frag
784 4) which index into the table to try if we can't fit into this one. */
786 /* UNCOND_JUMP states. */
787 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
788 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
789 /* dword jmp adds 4 bytes to frag:
790 0 extra opcode bytes, 4 displacement bytes. */
792 /* word jmp adds 2 byte2 to frag:
793 0 extra opcode bytes, 2 displacement bytes. */
796 /* COND_JUMP states. */
797 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
798 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
799 /* dword conditionals adds 5 bytes to frag:
800 1 extra opcode byte, 4 displacement bytes. */
802 /* word conditionals add 3 bytes to frag:
803 1 extra opcode byte, 2 displacement bytes. */
806 /* COND_JUMP86 states. */
807 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
808 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
809 /* dword conditionals adds 5 bytes to frag:
810 1 extra opcode byte, 4 displacement bytes. */
812 /* word conditionals add 4 bytes to frag:
813 1 displacement byte and a 3 byte long branch insn. */
817 static const arch_entry cpu_arch
[] =
819 /* Do not replace the first two entries - i386_target_format()
820 relies on them being there in this order. */
821 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32
,
822 CPU_GENERIC32_FLAGS
, 0 },
823 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64
,
824 CPU_GENERIC64_FLAGS
, 0 },
825 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN
,
827 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN
,
829 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN
,
831 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386
,
833 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486
,
835 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM
,
837 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO
,
839 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM
,
841 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO
,
842 CPU_PENTIUMPRO_FLAGS
, 0 },
843 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO
,
845 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO
,
847 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4
,
849 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA
,
851 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA
,
852 CPU_NOCONA_FLAGS
, 0 },
853 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE
,
855 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE
,
857 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2
,
858 CPU_CORE2_FLAGS
, 1 },
859 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2
,
860 CPU_CORE2_FLAGS
, 0 },
861 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7
,
862 CPU_COREI7_FLAGS
, 0 },
863 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM
,
865 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM
,
867 { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU
,
868 CPU_IAMCU_FLAGS
, 0 },
869 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6
,
871 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6
,
873 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON
,
874 CPU_ATHLON_FLAGS
, 0 },
875 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8
,
877 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8
,
879 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8
,
881 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10
,
882 CPU_AMDFAM10_FLAGS
, 0 },
883 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD
,
884 CPU_BDVER1_FLAGS
, 0 },
885 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD
,
886 CPU_BDVER2_FLAGS
, 0 },
887 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD
,
888 CPU_BDVER3_FLAGS
, 0 },
889 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD
,
890 CPU_BDVER4_FLAGS
, 0 },
891 { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER
,
892 CPU_ZNVER1_FLAGS
, 0 },
893 { STRING_COMMA_LEN ("znver2"), PROCESSOR_ZNVER
,
894 CPU_ZNVER2_FLAGS
, 0 },
895 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT
,
896 CPU_BTVER1_FLAGS
, 0 },
897 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT
,
898 CPU_BTVER2_FLAGS
, 0 },
899 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN
,
901 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN
,
903 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN
,
905 { STRING_COMMA_LEN (".687"), PROCESSOR_UNKNOWN
,
907 { STRING_COMMA_LEN (".cmov"), PROCESSOR_UNKNOWN
,
909 { STRING_COMMA_LEN (".fxsr"), PROCESSOR_UNKNOWN
,
911 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN
,
913 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN
,
915 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN
,
917 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN
,
919 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN
,
920 CPU_SSSE3_FLAGS
, 0 },
921 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN
,
922 CPU_SSE4_1_FLAGS
, 0 },
923 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN
,
924 CPU_SSE4_2_FLAGS
, 0 },
925 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN
,
926 CPU_SSE4_2_FLAGS
, 0 },
927 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN
,
929 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN
,
931 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN
,
932 CPU_AVX512F_FLAGS
, 0 },
933 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN
,
934 CPU_AVX512CD_FLAGS
, 0 },
935 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN
,
936 CPU_AVX512ER_FLAGS
, 0 },
937 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN
,
938 CPU_AVX512PF_FLAGS
, 0 },
939 { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN
,
940 CPU_AVX512DQ_FLAGS
, 0 },
941 { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN
,
942 CPU_AVX512BW_FLAGS
, 0 },
943 { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN
,
944 CPU_AVX512VL_FLAGS
, 0 },
945 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN
,
947 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN
,
948 CPU_VMFUNC_FLAGS
, 0 },
949 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN
,
951 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN
,
952 CPU_XSAVE_FLAGS
, 0 },
953 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN
,
954 CPU_XSAVEOPT_FLAGS
, 0 },
955 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN
,
956 CPU_XSAVEC_FLAGS
, 0 },
957 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN
,
958 CPU_XSAVES_FLAGS
, 0 },
959 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN
,
961 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN
,
962 CPU_PCLMUL_FLAGS
, 0 },
963 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN
,
964 CPU_PCLMUL_FLAGS
, 1 },
965 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN
,
966 CPU_FSGSBASE_FLAGS
, 0 },
967 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN
,
968 CPU_RDRND_FLAGS
, 0 },
969 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN
,
971 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN
,
973 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN
,
975 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN
,
977 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN
,
979 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN
,
981 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN
,
982 CPU_MOVBE_FLAGS
, 0 },
983 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN
,
985 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN
,
987 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN
,
988 CPU_LZCNT_FLAGS
, 0 },
989 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN
,
991 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN
,
993 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN
,
994 CPU_INVPCID_FLAGS
, 0 },
995 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN
,
996 CPU_CLFLUSH_FLAGS
, 0 },
997 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN
,
999 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN
,
1000 CPU_SYSCALL_FLAGS
, 0 },
1001 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN
,
1002 CPU_RDTSCP_FLAGS
, 0 },
1003 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN
,
1004 CPU_3DNOW_FLAGS
, 0 },
1005 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN
,
1006 CPU_3DNOWA_FLAGS
, 0 },
1007 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN
,
1008 CPU_PADLOCK_FLAGS
, 0 },
1009 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN
,
1010 CPU_SVME_FLAGS
, 1 },
1011 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN
,
1012 CPU_SVME_FLAGS
, 0 },
1013 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN
,
1014 CPU_SSE4A_FLAGS
, 0 },
1015 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN
,
1017 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN
,
1019 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN
,
1021 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN
,
1023 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN
,
1024 CPU_RDSEED_FLAGS
, 0 },
1025 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN
,
1026 CPU_PRFCHW_FLAGS
, 0 },
1027 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN
,
1028 CPU_SMAP_FLAGS
, 0 },
1029 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN
,
1031 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN
,
1033 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN
,
1034 CPU_CLFLUSHOPT_FLAGS
, 0 },
1035 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN
,
1036 CPU_PREFETCHWT1_FLAGS
, 0 },
1037 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN
,
1039 { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN
,
1040 CPU_CLWB_FLAGS
, 0 },
1041 { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN
,
1042 CPU_AVX512IFMA_FLAGS
, 0 },
1043 { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN
,
1044 CPU_AVX512VBMI_FLAGS
, 0 },
1045 { STRING_COMMA_LEN (".avx512_4fmaps"), PROCESSOR_UNKNOWN
,
1046 CPU_AVX512_4FMAPS_FLAGS
, 0 },
1047 { STRING_COMMA_LEN (".avx512_4vnniw"), PROCESSOR_UNKNOWN
,
1048 CPU_AVX512_4VNNIW_FLAGS
, 0 },
1049 { STRING_COMMA_LEN (".avx512_vpopcntdq"), PROCESSOR_UNKNOWN
,
1050 CPU_AVX512_VPOPCNTDQ_FLAGS
, 0 },
1051 { STRING_COMMA_LEN (".avx512_vbmi2"), PROCESSOR_UNKNOWN
,
1052 CPU_AVX512_VBMI2_FLAGS
, 0 },
1053 { STRING_COMMA_LEN (".avx512_vnni"), PROCESSOR_UNKNOWN
,
1054 CPU_AVX512_VNNI_FLAGS
, 0 },
1055 { STRING_COMMA_LEN (".avx512_bitalg"), PROCESSOR_UNKNOWN
,
1056 CPU_AVX512_BITALG_FLAGS
, 0 },
1057 { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN
,
1058 CPU_CLZERO_FLAGS
, 0 },
1059 { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN
,
1060 CPU_MWAITX_FLAGS
, 0 },
1061 { STRING_COMMA_LEN (".ospke"), PROCESSOR_UNKNOWN
,
1062 CPU_OSPKE_FLAGS
, 0 },
1063 { STRING_COMMA_LEN (".rdpid"), PROCESSOR_UNKNOWN
,
1064 CPU_RDPID_FLAGS
, 0 },
1065 { STRING_COMMA_LEN (".ptwrite"), PROCESSOR_UNKNOWN
,
1066 CPU_PTWRITE_FLAGS
, 0 },
1067 { STRING_COMMA_LEN (".ibt"), PROCESSOR_UNKNOWN
,
1069 { STRING_COMMA_LEN (".shstk"), PROCESSOR_UNKNOWN
,
1070 CPU_SHSTK_FLAGS
, 0 },
1071 { STRING_COMMA_LEN (".gfni"), PROCESSOR_UNKNOWN
,
1072 CPU_GFNI_FLAGS
, 0 },
1073 { STRING_COMMA_LEN (".vaes"), PROCESSOR_UNKNOWN
,
1074 CPU_VAES_FLAGS
, 0 },
1075 { STRING_COMMA_LEN (".vpclmulqdq"), PROCESSOR_UNKNOWN
,
1076 CPU_VPCLMULQDQ_FLAGS
, 0 },
1077 { STRING_COMMA_LEN (".wbnoinvd"), PROCESSOR_UNKNOWN
,
1078 CPU_WBNOINVD_FLAGS
, 0 },
1079 { STRING_COMMA_LEN (".pconfig"), PROCESSOR_UNKNOWN
,
1080 CPU_PCONFIG_FLAGS
, 0 },
1081 { STRING_COMMA_LEN (".waitpkg"), PROCESSOR_UNKNOWN
,
1082 CPU_WAITPKG_FLAGS
, 0 },
1083 { STRING_COMMA_LEN (".cldemote"), PROCESSOR_UNKNOWN
,
1084 CPU_CLDEMOTE_FLAGS
, 0 },
1085 { STRING_COMMA_LEN (".movdiri"), PROCESSOR_UNKNOWN
,
1086 CPU_MOVDIRI_FLAGS
, 0 },
1087 { STRING_COMMA_LEN (".movdir64b"), PROCESSOR_UNKNOWN
,
1088 CPU_MOVDIR64B_FLAGS
, 0 },
1089 { STRING_COMMA_LEN (".avx512_bf16"), PROCESSOR_UNKNOWN
,
1090 CPU_AVX512_BF16_FLAGS
, 0 },
1091 { STRING_COMMA_LEN (".avx512_vp2intersect"), PROCESSOR_UNKNOWN
,
1092 CPU_AVX512_VP2INTERSECT_FLAGS
, 0 },
1093 { STRING_COMMA_LEN (".enqcmd"), PROCESSOR_UNKNOWN
,
1094 CPU_ENQCMD_FLAGS
, 0 },
1095 { STRING_COMMA_LEN (".rdpru"), PROCESSOR_UNKNOWN
,
1096 CPU_RDPRU_FLAGS
, 0 },
1097 { STRING_COMMA_LEN (".mcommit"), PROCESSOR_UNKNOWN
,
1098 CPU_MCOMMIT_FLAGS
, 0 },
1101 static const noarch_entry cpu_noarch
[] =
1103 { STRING_COMMA_LEN ("no87"), CPU_ANY_X87_FLAGS
},
1104 { STRING_COMMA_LEN ("no287"), CPU_ANY_287_FLAGS
},
1105 { STRING_COMMA_LEN ("no387"), CPU_ANY_387_FLAGS
},
1106 { STRING_COMMA_LEN ("no687"), CPU_ANY_687_FLAGS
},
1107 { STRING_COMMA_LEN ("nocmov"), CPU_ANY_CMOV_FLAGS
},
1108 { STRING_COMMA_LEN ("nofxsr"), CPU_ANY_FXSR_FLAGS
},
1109 { STRING_COMMA_LEN ("nommx"), CPU_ANY_MMX_FLAGS
},
1110 { STRING_COMMA_LEN ("nosse"), CPU_ANY_SSE_FLAGS
},
1111 { STRING_COMMA_LEN ("nosse2"), CPU_ANY_SSE2_FLAGS
},
1112 { STRING_COMMA_LEN ("nosse3"), CPU_ANY_SSE3_FLAGS
},
1113 { STRING_COMMA_LEN ("nossse3"), CPU_ANY_SSSE3_FLAGS
},
1114 { STRING_COMMA_LEN ("nosse4.1"), CPU_ANY_SSE4_1_FLAGS
},
1115 { STRING_COMMA_LEN ("nosse4.2"), CPU_ANY_SSE4_2_FLAGS
},
1116 { STRING_COMMA_LEN ("nosse4"), CPU_ANY_SSE4_1_FLAGS
},
1117 { STRING_COMMA_LEN ("noavx"), CPU_ANY_AVX_FLAGS
},
1118 { STRING_COMMA_LEN ("noavx2"), CPU_ANY_AVX2_FLAGS
},
1119 { STRING_COMMA_LEN ("noavx512f"), CPU_ANY_AVX512F_FLAGS
},
1120 { STRING_COMMA_LEN ("noavx512cd"), CPU_ANY_AVX512CD_FLAGS
},
1121 { STRING_COMMA_LEN ("noavx512er"), CPU_ANY_AVX512ER_FLAGS
},
1122 { STRING_COMMA_LEN ("noavx512pf"), CPU_ANY_AVX512PF_FLAGS
},
1123 { STRING_COMMA_LEN ("noavx512dq"), CPU_ANY_AVX512DQ_FLAGS
},
1124 { STRING_COMMA_LEN ("noavx512bw"), CPU_ANY_AVX512BW_FLAGS
},
1125 { STRING_COMMA_LEN ("noavx512vl"), CPU_ANY_AVX512VL_FLAGS
},
1126 { STRING_COMMA_LEN ("noavx512ifma"), CPU_ANY_AVX512IFMA_FLAGS
},
1127 { STRING_COMMA_LEN ("noavx512vbmi"), CPU_ANY_AVX512VBMI_FLAGS
},
1128 { STRING_COMMA_LEN ("noavx512_4fmaps"), CPU_ANY_AVX512_4FMAPS_FLAGS
},
1129 { STRING_COMMA_LEN ("noavx512_4vnniw"), CPU_ANY_AVX512_4VNNIW_FLAGS
},
1130 { STRING_COMMA_LEN ("noavx512_vpopcntdq"), CPU_ANY_AVX512_VPOPCNTDQ_FLAGS
},
1131 { STRING_COMMA_LEN ("noavx512_vbmi2"), CPU_ANY_AVX512_VBMI2_FLAGS
},
1132 { STRING_COMMA_LEN ("noavx512_vnni"), CPU_ANY_AVX512_VNNI_FLAGS
},
1133 { STRING_COMMA_LEN ("noavx512_bitalg"), CPU_ANY_AVX512_BITALG_FLAGS
},
1134 { STRING_COMMA_LEN ("noibt"), CPU_ANY_IBT_FLAGS
},
1135 { STRING_COMMA_LEN ("noshstk"), CPU_ANY_SHSTK_FLAGS
},
1136 { STRING_COMMA_LEN ("nomovdiri"), CPU_ANY_MOVDIRI_FLAGS
},
1137 { STRING_COMMA_LEN ("nomovdir64b"), CPU_ANY_MOVDIR64B_FLAGS
},
1138 { STRING_COMMA_LEN ("noavx512_bf16"), CPU_ANY_AVX512_BF16_FLAGS
},
1139 { STRING_COMMA_LEN ("noavx512_vp2intersect"), CPU_ANY_SHSTK_FLAGS
},
1140 { STRING_COMMA_LEN ("noenqcmd"), CPU_ANY_ENQCMD_FLAGS
},
1144 /* Like s_lcomm_internal in gas/read.c but the alignment string
1145 is allowed to be optional. */
1148 pe_lcomm_internal (int needs_align
, symbolS
*symbolP
, addressT size
)
1155 && *input_line_pointer
== ',')
1157 align
= parse_align (needs_align
- 1);
1159 if (align
== (addressT
) -1)
1174 bss_alloc (symbolP
, size
, align
);
1179 pe_lcomm (int needs_align
)
1181 s_comm_internal (needs_align
* 2, pe_lcomm_internal
);
1185 const pseudo_typeS md_pseudo_table
[] =
1187 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
1188 {"align", s_align_bytes
, 0},
1190 {"align", s_align_ptwo
, 0},
1192 {"arch", set_cpu_arch
, 0},
1196 {"lcomm", pe_lcomm
, 1},
1198 {"ffloat", float_cons
, 'f'},
1199 {"dfloat", float_cons
, 'd'},
1200 {"tfloat", float_cons
, 'x'},
1202 {"slong", signed_cons
, 4},
1203 {"noopt", s_ignore
, 0},
1204 {"optim", s_ignore
, 0},
1205 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
1206 {"code16", set_code_flag
, CODE_16BIT
},
1207 {"code32", set_code_flag
, CODE_32BIT
},
1209 {"code64", set_code_flag
, CODE_64BIT
},
1211 {"intel_syntax", set_intel_syntax
, 1},
1212 {"att_syntax", set_intel_syntax
, 0},
1213 {"intel_mnemonic", set_intel_mnemonic
, 1},
1214 {"att_mnemonic", set_intel_mnemonic
, 0},
1215 {"allow_index_reg", set_allow_index_reg
, 1},
1216 {"disallow_index_reg", set_allow_index_reg
, 0},
1217 {"sse_check", set_check
, 0},
1218 {"operand_check", set_check
, 1},
1219 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1220 {"largecomm", handle_large_common
, 0},
1222 {"file", dwarf2_directive_file
, 0},
1223 {"loc", dwarf2_directive_loc
, 0},
1224 {"loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0},
1227 {"secrel32", pe_directive_secrel
, 0},
1232 /* For interface with expression (). */
1233 extern char *input_line_pointer
;
1235 /* Hash table for instruction mnemonic lookup. */
1236 static struct hash_control
*op_hash
;
1238 /* Hash table for register lookup. */
1239 static struct hash_control
*reg_hash
;
1241 /* Various efficient no-op patterns for aligning code labels.
1242 Note: Don't try to assemble the instructions in the comments.
1243 0L and 0w are not legal. */
1244 static const unsigned char f32_1
[] =
1246 static const unsigned char f32_2
[] =
1247 {0x66,0x90}; /* xchg %ax,%ax */
1248 static const unsigned char f32_3
[] =
1249 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1250 static const unsigned char f32_4
[] =
1251 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1252 static const unsigned char f32_6
[] =
1253 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1254 static const unsigned char f32_7
[] =
1255 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1256 static const unsigned char f16_3
[] =
1257 {0x8d,0x74,0x00}; /* lea 0(%si),%si */
1258 static const unsigned char f16_4
[] =
1259 {0x8d,0xb4,0x00,0x00}; /* lea 0W(%si),%si */
1260 static const unsigned char jump_disp8
[] =
1261 {0xeb}; /* jmp disp8 */
1262 static const unsigned char jump32_disp32
[] =
1263 {0xe9}; /* jmp disp32 */
1264 static const unsigned char jump16_disp32
[] =
1265 {0x66,0xe9}; /* jmp disp32 */
1266 /* 32-bit NOPs patterns. */
1267 static const unsigned char *const f32_patt
[] = {
1268 f32_1
, f32_2
, f32_3
, f32_4
, NULL
, f32_6
, f32_7
1270 /* 16-bit NOPs patterns. */
1271 static const unsigned char *const f16_patt
[] = {
1272 f32_1
, f32_2
, f16_3
, f16_4
1274 /* nopl (%[re]ax) */
1275 static const unsigned char alt_3
[] =
1277 /* nopl 0(%[re]ax) */
1278 static const unsigned char alt_4
[] =
1279 {0x0f,0x1f,0x40,0x00};
1280 /* nopl 0(%[re]ax,%[re]ax,1) */
1281 static const unsigned char alt_5
[] =
1282 {0x0f,0x1f,0x44,0x00,0x00};
1283 /* nopw 0(%[re]ax,%[re]ax,1) */
1284 static const unsigned char alt_6
[] =
1285 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1286 /* nopl 0L(%[re]ax) */
1287 static const unsigned char alt_7
[] =
1288 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1289 /* nopl 0L(%[re]ax,%[re]ax,1) */
1290 static const unsigned char alt_8
[] =
1291 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1292 /* nopw 0L(%[re]ax,%[re]ax,1) */
1293 static const unsigned char alt_9
[] =
1294 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1295 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1296 static const unsigned char alt_10
[] =
1297 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1298 /* data16 nopw %cs:0L(%eax,%eax,1) */
1299 static const unsigned char alt_11
[] =
1300 {0x66,0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1301 /* 32-bit and 64-bit NOPs patterns. */
1302 static const unsigned char *const alt_patt
[] = {
1303 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
1304 alt_9
, alt_10
, alt_11
1307 /* Genenerate COUNT bytes of NOPs to WHERE from PATT with the maximum
1308 size of a single NOP instruction MAX_SINGLE_NOP_SIZE. */
1311 i386_output_nops (char *where
, const unsigned char *const *patt
,
1312 int count
, int max_single_nop_size
)
1315 /* Place the longer NOP first. */
1318 const unsigned char *nops
;
1320 if (max_single_nop_size
< 1)
1322 as_fatal (_("i386_output_nops called to generate nops of at most %d bytes!"),
1323 max_single_nop_size
);
1327 nops
= patt
[max_single_nop_size
- 1];
1329 /* Use the smaller one if the requsted one isn't available. */
1332 max_single_nop_size
--;
1333 nops
= patt
[max_single_nop_size
- 1];
1336 last
= count
% max_single_nop_size
;
1339 for (offset
= 0; offset
< count
; offset
+= max_single_nop_size
)
1340 memcpy (where
+ offset
, nops
, max_single_nop_size
);
1344 nops
= patt
[last
- 1];
1347 /* Use the smaller one plus one-byte NOP if the needed one
1350 nops
= patt
[last
- 1];
1351 memcpy (where
+ offset
, nops
, last
);
1352 where
[offset
+ last
] = *patt
[0];
1355 memcpy (where
+ offset
, nops
, last
);
1360 fits_in_imm7 (offsetT num
)
1362 return (num
& 0x7f) == num
;
1366 fits_in_imm31 (offsetT num
)
1368 return (num
& 0x7fffffff) == num
;
1371 /* Genenerate COUNT bytes of NOPs to WHERE with the maximum size of a
1372 single NOP instruction LIMIT. */
1375 i386_generate_nops (fragS
*fragP
, char *where
, offsetT count
, int limit
)
1377 const unsigned char *const *patt
= NULL
;
1378 int max_single_nop_size
;
1379 /* Maximum number of NOPs before switching to jump over NOPs. */
1380 int max_number_of_nops
;
1382 switch (fragP
->fr_type
)
1391 /* We need to decide which NOP sequence to use for 32bit and
1392 64bit. When -mtune= is used:
1394 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1395 PROCESSOR_GENERIC32, f32_patt will be used.
1396 2. For the rest, alt_patt will be used.
1398 When -mtune= isn't used, alt_patt will be used if
1399 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
1402 When -march= or .arch is used, we can't use anything beyond
1403 cpu_arch_isa_flags. */
1405 if (flag_code
== CODE_16BIT
)
1408 max_single_nop_size
= sizeof (f16_patt
) / sizeof (f16_patt
[0]);
1409 /* Limit number of NOPs to 2 in 16-bit mode. */
1410 max_number_of_nops
= 2;
1414 if (fragP
->tc_frag_data
.isa
== PROCESSOR_UNKNOWN
)
1416 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1417 switch (cpu_arch_tune
)
1419 case PROCESSOR_UNKNOWN
:
1420 /* We use cpu_arch_isa_flags to check if we SHOULD
1421 optimize with nops. */
1422 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1427 case PROCESSOR_PENTIUM4
:
1428 case PROCESSOR_NOCONA
:
1429 case PROCESSOR_CORE
:
1430 case PROCESSOR_CORE2
:
1431 case PROCESSOR_COREI7
:
1432 case PROCESSOR_L1OM
:
1433 case PROCESSOR_K1OM
:
1434 case PROCESSOR_GENERIC64
:
1436 case PROCESSOR_ATHLON
:
1438 case PROCESSOR_AMDFAM10
:
1440 case PROCESSOR_ZNVER
:
1444 case PROCESSOR_I386
:
1445 case PROCESSOR_I486
:
1446 case PROCESSOR_PENTIUM
:
1447 case PROCESSOR_PENTIUMPRO
:
1448 case PROCESSOR_IAMCU
:
1449 case PROCESSOR_GENERIC32
:
1456 switch (fragP
->tc_frag_data
.tune
)
1458 case PROCESSOR_UNKNOWN
:
1459 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1460 PROCESSOR_UNKNOWN. */
1464 case PROCESSOR_I386
:
1465 case PROCESSOR_I486
:
1466 case PROCESSOR_PENTIUM
:
1467 case PROCESSOR_IAMCU
:
1469 case PROCESSOR_ATHLON
:
1471 case PROCESSOR_AMDFAM10
:
1473 case PROCESSOR_ZNVER
:
1475 case PROCESSOR_GENERIC32
:
1476 /* We use cpu_arch_isa_flags to check if we CAN optimize
1478 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1483 case PROCESSOR_PENTIUMPRO
:
1484 case PROCESSOR_PENTIUM4
:
1485 case PROCESSOR_NOCONA
:
1486 case PROCESSOR_CORE
:
1487 case PROCESSOR_CORE2
:
1488 case PROCESSOR_COREI7
:
1489 case PROCESSOR_L1OM
:
1490 case PROCESSOR_K1OM
:
1491 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1496 case PROCESSOR_GENERIC64
:
1502 if (patt
== f32_patt
)
1504 max_single_nop_size
= sizeof (f32_patt
) / sizeof (f32_patt
[0]);
1505 /* Limit number of NOPs to 2 for older processors. */
1506 max_number_of_nops
= 2;
1510 max_single_nop_size
= sizeof (alt_patt
) / sizeof (alt_patt
[0]);
1511 /* Limit number of NOPs to 7 for newer processors. */
1512 max_number_of_nops
= 7;
1517 limit
= max_single_nop_size
;
1519 if (fragP
->fr_type
== rs_fill_nop
)
1521 /* Output NOPs for .nop directive. */
1522 if (limit
> max_single_nop_size
)
1524 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
1525 _("invalid single nop size: %d "
1526 "(expect within [0, %d])"),
1527 limit
, max_single_nop_size
);
1532 fragP
->fr_var
= count
;
1534 if ((count
/ max_single_nop_size
) > max_number_of_nops
)
1536 /* Generate jump over NOPs. */
1537 offsetT disp
= count
- 2;
1538 if (fits_in_imm7 (disp
))
1540 /* Use "jmp disp8" if possible. */
1542 where
[0] = jump_disp8
[0];
1548 unsigned int size_of_jump
;
1550 if (flag_code
== CODE_16BIT
)
1552 where
[0] = jump16_disp32
[0];
1553 where
[1] = jump16_disp32
[1];
1558 where
[0] = jump32_disp32
[0];
1562 count
-= size_of_jump
+ 4;
1563 if (!fits_in_imm31 (count
))
1565 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
1566 _("jump over nop padding out of range"));
1570 md_number_to_chars (where
+ size_of_jump
, count
, 4);
1571 where
+= size_of_jump
+ 4;
1575 /* Generate multiple NOPs. */
1576 i386_output_nops (where
, patt
, count
, limit
);
1580 operand_type_all_zero (const union i386_operand_type
*x
)
1582 switch (ARRAY_SIZE(x
->array
))
1593 return !x
->array
[0];
1600 operand_type_set (union i386_operand_type
*x
, unsigned int v
)
1602 switch (ARRAY_SIZE(x
->array
))
1618 x
->bitfield
.class = ClassNone
;
1619 x
->bitfield
.instance
= InstanceNone
;
1623 operand_type_equal (const union i386_operand_type
*x
,
1624 const union i386_operand_type
*y
)
1626 switch (ARRAY_SIZE(x
->array
))
1629 if (x
->array
[2] != y
->array
[2])
1633 if (x
->array
[1] != y
->array
[1])
1637 return x
->array
[0] == y
->array
[0];
1645 cpu_flags_all_zero (const union i386_cpu_flags
*x
)
1647 switch (ARRAY_SIZE(x
->array
))
1662 return !x
->array
[0];
1669 cpu_flags_equal (const union i386_cpu_flags
*x
,
1670 const union i386_cpu_flags
*y
)
1672 switch (ARRAY_SIZE(x
->array
))
1675 if (x
->array
[3] != y
->array
[3])
1679 if (x
->array
[2] != y
->array
[2])
1683 if (x
->array
[1] != y
->array
[1])
1687 return x
->array
[0] == y
->array
[0];
1695 cpu_flags_check_cpu64 (i386_cpu_flags f
)
1697 return !((flag_code
== CODE_64BIT
&& f
.bitfield
.cpuno64
)
1698 || (flag_code
!= CODE_64BIT
&& f
.bitfield
.cpu64
));
1701 static INLINE i386_cpu_flags
1702 cpu_flags_and (i386_cpu_flags x
, i386_cpu_flags y
)
1704 switch (ARRAY_SIZE (x
.array
))
1707 x
.array
[3] &= y
.array
[3];
1710 x
.array
[2] &= y
.array
[2];
1713 x
.array
[1] &= y
.array
[1];
1716 x
.array
[0] &= y
.array
[0];
1724 static INLINE i386_cpu_flags
1725 cpu_flags_or (i386_cpu_flags x
, i386_cpu_flags y
)
1727 switch (ARRAY_SIZE (x
.array
))
1730 x
.array
[3] |= y
.array
[3];
1733 x
.array
[2] |= y
.array
[2];
1736 x
.array
[1] |= y
.array
[1];
1739 x
.array
[0] |= y
.array
[0];
1747 static INLINE i386_cpu_flags
1748 cpu_flags_and_not (i386_cpu_flags x
, i386_cpu_flags y
)
1750 switch (ARRAY_SIZE (x
.array
))
1753 x
.array
[3] &= ~y
.array
[3];
1756 x
.array
[2] &= ~y
.array
[2];
1759 x
.array
[1] &= ~y
.array
[1];
1762 x
.array
[0] &= ~y
.array
[0];
1770 #define CPU_FLAGS_ARCH_MATCH 0x1
1771 #define CPU_FLAGS_64BIT_MATCH 0x2
1773 #define CPU_FLAGS_PERFECT_MATCH \
1774 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_64BIT_MATCH)
1776 /* Return CPU flags match bits. */
1779 cpu_flags_match (const insn_template
*t
)
1781 i386_cpu_flags x
= t
->cpu_flags
;
1782 int match
= cpu_flags_check_cpu64 (x
) ? CPU_FLAGS_64BIT_MATCH
: 0;
1784 x
.bitfield
.cpu64
= 0;
1785 x
.bitfield
.cpuno64
= 0;
1787 if (cpu_flags_all_zero (&x
))
1789 /* This instruction is available on all archs. */
1790 match
|= CPU_FLAGS_ARCH_MATCH
;
1794 /* This instruction is available only on some archs. */
1795 i386_cpu_flags cpu
= cpu_arch_flags
;
1797 /* AVX512VL is no standalone feature - match it and then strip it. */
1798 if (x
.bitfield
.cpuavx512vl
&& !cpu
.bitfield
.cpuavx512vl
)
1800 x
.bitfield
.cpuavx512vl
= 0;
1802 cpu
= cpu_flags_and (x
, cpu
);
1803 if (!cpu_flags_all_zero (&cpu
))
1805 if (x
.bitfield
.cpuavx
)
1807 /* We need to check a few extra flags with AVX. */
1808 if (cpu
.bitfield
.cpuavx
1809 && (!t
->opcode_modifier
.sse2avx
|| sse2avx
)
1810 && (!x
.bitfield
.cpuaes
|| cpu
.bitfield
.cpuaes
)
1811 && (!x
.bitfield
.cpugfni
|| cpu
.bitfield
.cpugfni
)
1812 && (!x
.bitfield
.cpupclmul
|| cpu
.bitfield
.cpupclmul
))
1813 match
|= CPU_FLAGS_ARCH_MATCH
;
1815 else if (x
.bitfield
.cpuavx512f
)
1817 /* We need to check a few extra flags with AVX512F. */
1818 if (cpu
.bitfield
.cpuavx512f
1819 && (!x
.bitfield
.cpugfni
|| cpu
.bitfield
.cpugfni
)
1820 && (!x
.bitfield
.cpuvaes
|| cpu
.bitfield
.cpuvaes
)
1821 && (!x
.bitfield
.cpuvpclmulqdq
|| cpu
.bitfield
.cpuvpclmulqdq
))
1822 match
|= CPU_FLAGS_ARCH_MATCH
;
1825 match
|= CPU_FLAGS_ARCH_MATCH
;
1831 static INLINE i386_operand_type
1832 operand_type_and (i386_operand_type x
, i386_operand_type y
)
1834 if (x
.bitfield
.class != y
.bitfield
.class)
1835 x
.bitfield
.class = ClassNone
;
1836 if (x
.bitfield
.instance
!= y
.bitfield
.instance
)
1837 x
.bitfield
.instance
= InstanceNone
;
1839 switch (ARRAY_SIZE (x
.array
))
1842 x
.array
[2] &= y
.array
[2];
1845 x
.array
[1] &= y
.array
[1];
1848 x
.array
[0] &= y
.array
[0];
1856 static INLINE i386_operand_type
1857 operand_type_and_not (i386_operand_type x
, i386_operand_type y
)
1859 gas_assert (y
.bitfield
.class == ClassNone
);
1860 gas_assert (y
.bitfield
.instance
== InstanceNone
);
1862 switch (ARRAY_SIZE (x
.array
))
1865 x
.array
[2] &= ~y
.array
[2];
1868 x
.array
[1] &= ~y
.array
[1];
1871 x
.array
[0] &= ~y
.array
[0];
1879 static INLINE i386_operand_type
1880 operand_type_or (i386_operand_type x
, i386_operand_type y
)
1882 gas_assert (x
.bitfield
.class == ClassNone
||
1883 y
.bitfield
.class == ClassNone
||
1884 x
.bitfield
.class == y
.bitfield
.class);
1885 gas_assert (x
.bitfield
.instance
== InstanceNone
||
1886 y
.bitfield
.instance
== InstanceNone
||
1887 x
.bitfield
.instance
== y
.bitfield
.instance
);
1889 switch (ARRAY_SIZE (x
.array
))
1892 x
.array
[2] |= y
.array
[2];
1895 x
.array
[1] |= y
.array
[1];
1898 x
.array
[0] |= y
.array
[0];
1906 static INLINE i386_operand_type
1907 operand_type_xor (i386_operand_type x
, i386_operand_type y
)
1909 gas_assert (y
.bitfield
.class == ClassNone
);
1910 gas_assert (y
.bitfield
.instance
== InstanceNone
);
1912 switch (ARRAY_SIZE (x
.array
))
1915 x
.array
[2] ^= y
.array
[2];
1918 x
.array
[1] ^= y
.array
[1];
1921 x
.array
[0] ^= y
.array
[0];
1929 static const i386_operand_type disp16
= OPERAND_TYPE_DISP16
;
1930 static const i386_operand_type disp32
= OPERAND_TYPE_DISP32
;
1931 static const i386_operand_type disp32s
= OPERAND_TYPE_DISP32S
;
1932 static const i386_operand_type disp16_32
= OPERAND_TYPE_DISP16_32
;
1933 static const i386_operand_type anydisp
= OPERAND_TYPE_ANYDISP
;
1934 static const i386_operand_type anyimm
= OPERAND_TYPE_ANYIMM
;
1935 static const i386_operand_type regxmm
= OPERAND_TYPE_REGXMM
;
1936 static const i386_operand_type regmask
= OPERAND_TYPE_REGMASK
;
1937 static const i386_operand_type imm8
= OPERAND_TYPE_IMM8
;
1938 static const i386_operand_type imm8s
= OPERAND_TYPE_IMM8S
;
1939 static const i386_operand_type imm16
= OPERAND_TYPE_IMM16
;
1940 static const i386_operand_type imm32
= OPERAND_TYPE_IMM32
;
1941 static const i386_operand_type imm32s
= OPERAND_TYPE_IMM32S
;
1942 static const i386_operand_type imm64
= OPERAND_TYPE_IMM64
;
1943 static const i386_operand_type imm16_32
= OPERAND_TYPE_IMM16_32
;
1944 static const i386_operand_type imm16_32s
= OPERAND_TYPE_IMM16_32S
;
1945 static const i386_operand_type imm16_32_32s
= OPERAND_TYPE_IMM16_32_32S
;
1956 operand_type_check (i386_operand_type t
, enum operand_type c
)
1961 return t
.bitfield
.class == Reg
;
1964 return (t
.bitfield
.imm8
1968 || t
.bitfield
.imm32s
1969 || t
.bitfield
.imm64
);
1972 return (t
.bitfield
.disp8
1973 || t
.bitfield
.disp16
1974 || t
.bitfield
.disp32
1975 || t
.bitfield
.disp32s
1976 || t
.bitfield
.disp64
);
1979 return (t
.bitfield
.disp8
1980 || t
.bitfield
.disp16
1981 || t
.bitfield
.disp32
1982 || t
.bitfield
.disp32s
1983 || t
.bitfield
.disp64
1984 || t
.bitfield
.baseindex
);
1993 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit/80bit size
1994 between operand GIVEN and opeand WANTED for instruction template T. */
1997 match_operand_size (const insn_template
*t
, unsigned int wanted
,
2000 return !((i
.types
[given
].bitfield
.byte
2001 && !t
->operand_types
[wanted
].bitfield
.byte
)
2002 || (i
.types
[given
].bitfield
.word
2003 && !t
->operand_types
[wanted
].bitfield
.word
)
2004 || (i
.types
[given
].bitfield
.dword
2005 && !t
->operand_types
[wanted
].bitfield
.dword
)
2006 || (i
.types
[given
].bitfield
.qword
2007 && !t
->operand_types
[wanted
].bitfield
.qword
)
2008 || (i
.types
[given
].bitfield
.tbyte
2009 && !t
->operand_types
[wanted
].bitfield
.tbyte
));
2012 /* Return 1 if there is no conflict in SIMD register between operand
2013 GIVEN and opeand WANTED for instruction template T. */
2016 match_simd_size (const insn_template
*t
, unsigned int wanted
,
2019 return !((i
.types
[given
].bitfield
.xmmword
2020 && !t
->operand_types
[wanted
].bitfield
.xmmword
)
2021 || (i
.types
[given
].bitfield
.ymmword
2022 && !t
->operand_types
[wanted
].bitfield
.ymmword
)
2023 || (i
.types
[given
].bitfield
.zmmword
2024 && !t
->operand_types
[wanted
].bitfield
.zmmword
));
2027 /* Return 1 if there is no conflict in any size between operand GIVEN
2028 and opeand WANTED for instruction template T. */
2031 match_mem_size (const insn_template
*t
, unsigned int wanted
,
2034 return (match_operand_size (t
, wanted
, given
)
2035 && !((i
.types
[given
].bitfield
.unspecified
2037 && !t
->operand_types
[wanted
].bitfield
.unspecified
)
2038 || (i
.types
[given
].bitfield
.fword
2039 && !t
->operand_types
[wanted
].bitfield
.fword
)
2040 /* For scalar opcode templates to allow register and memory
2041 operands at the same time, some special casing is needed
2042 here. Also for v{,p}broadcast*, {,v}pmov{s,z}*, and
2043 down-conversion vpmov*. */
2044 || ((t
->operand_types
[wanted
].bitfield
.class == RegSIMD
2045 && !t
->opcode_modifier
.broadcast
2046 && (t
->operand_types
[wanted
].bitfield
.byte
2047 || t
->operand_types
[wanted
].bitfield
.word
2048 || t
->operand_types
[wanted
].bitfield
.dword
2049 || t
->operand_types
[wanted
].bitfield
.qword
))
2050 ? (i
.types
[given
].bitfield
.xmmword
2051 || i
.types
[given
].bitfield
.ymmword
2052 || i
.types
[given
].bitfield
.zmmword
)
2053 : !match_simd_size(t
, wanted
, given
))));
2056 /* Return value has MATCH_STRAIGHT set if there is no size conflict on any
2057 operands for instruction template T, and it has MATCH_REVERSE set if there
2058 is no size conflict on any operands for the template with operands reversed
2059 (and the template allows for reversing in the first place). */
2061 #define MATCH_STRAIGHT 1
2062 #define MATCH_REVERSE 2
2064 static INLINE
unsigned int
2065 operand_size_match (const insn_template
*t
)
2067 unsigned int j
, match
= MATCH_STRAIGHT
;
2069 /* Don't check jump instructions. */
2070 if (t
->opcode_modifier
.jump
2071 || t
->opcode_modifier
.jumpbyte
2072 || t
->opcode_modifier
.jumpdword
2073 || t
->opcode_modifier
.jumpintersegment
)
2076 /* Check memory and accumulator operand size. */
2077 for (j
= 0; j
< i
.operands
; j
++)
2079 if (i
.types
[j
].bitfield
.class != Reg
2080 && i
.types
[j
].bitfield
.class != RegSIMD
2081 && t
->opcode_modifier
.anysize
)
2084 if (t
->operand_types
[j
].bitfield
.class == Reg
2085 && !match_operand_size (t
, j
, j
))
2091 if (t
->operand_types
[j
].bitfield
.class == RegSIMD
2092 && !match_simd_size (t
, j
, j
))
2098 if (t
->operand_types
[j
].bitfield
.instance
== Accum
2099 && (!match_operand_size (t
, j
, j
) || !match_simd_size (t
, j
, j
)))
2105 if ((i
.flags
[j
] & Operand_Mem
) && !match_mem_size (t
, j
, j
))
2112 if (!t
->opcode_modifier
.d
)
2116 i
.error
= operand_size_mismatch
;
2120 /* Check reverse. */
2121 gas_assert (i
.operands
>= 2 && i
.operands
<= 3);
2123 for (j
= 0; j
< i
.operands
; j
++)
2125 unsigned int given
= i
.operands
- j
- 1;
2127 if (t
->operand_types
[j
].bitfield
.class == Reg
2128 && !match_operand_size (t
, j
, given
))
2131 if (t
->operand_types
[j
].bitfield
.class == RegSIMD
2132 && !match_simd_size (t
, j
, given
))
2135 if (t
->operand_types
[j
].bitfield
.instance
== Accum
2136 && (!match_operand_size (t
, j
, given
)
2137 || !match_simd_size (t
, j
, given
)))
2140 if ((i
.flags
[given
] & Operand_Mem
) && !match_mem_size (t
, j
, given
))
2144 return match
| MATCH_REVERSE
;
2148 operand_type_match (i386_operand_type overlap
,
2149 i386_operand_type given
)
2151 i386_operand_type temp
= overlap
;
2153 temp
.bitfield
.unspecified
= 0;
2154 temp
.bitfield
.byte
= 0;
2155 temp
.bitfield
.word
= 0;
2156 temp
.bitfield
.dword
= 0;
2157 temp
.bitfield
.fword
= 0;
2158 temp
.bitfield
.qword
= 0;
2159 temp
.bitfield
.tbyte
= 0;
2160 temp
.bitfield
.xmmword
= 0;
2161 temp
.bitfield
.ymmword
= 0;
2162 temp
.bitfield
.zmmword
= 0;
2163 if (operand_type_all_zero (&temp
))
2166 if (given
.bitfield
.baseindex
== overlap
.bitfield
.baseindex
)
2170 i
.error
= operand_type_mismatch
;
2174 /* If given types g0 and g1 are registers they must be of the same type
2175 unless the expected operand type register overlap is null.
2176 Memory operand size of certain SIMD instructions is also being checked
2180 operand_type_register_match (i386_operand_type g0
,
2181 i386_operand_type t0
,
2182 i386_operand_type g1
,
2183 i386_operand_type t1
)
2185 if (g0
.bitfield
.class != Reg
2186 && g0
.bitfield
.class != RegSIMD
2187 && (!operand_type_check (g0
, anymem
)
2188 || g0
.bitfield
.unspecified
2189 || t0
.bitfield
.class != RegSIMD
))
2192 if (g1
.bitfield
.class != Reg
2193 && g1
.bitfield
.class != RegSIMD
2194 && (!operand_type_check (g1
, anymem
)
2195 || g1
.bitfield
.unspecified
2196 || t1
.bitfield
.class != RegSIMD
))
2199 if (g0
.bitfield
.byte
== g1
.bitfield
.byte
2200 && g0
.bitfield
.word
== g1
.bitfield
.word
2201 && g0
.bitfield
.dword
== g1
.bitfield
.dword
2202 && g0
.bitfield
.qword
== g1
.bitfield
.qword
2203 && g0
.bitfield
.xmmword
== g1
.bitfield
.xmmword
2204 && g0
.bitfield
.ymmword
== g1
.bitfield
.ymmword
2205 && g0
.bitfield
.zmmword
== g1
.bitfield
.zmmword
)
2208 if (!(t0
.bitfield
.byte
& t1
.bitfield
.byte
)
2209 && !(t0
.bitfield
.word
& t1
.bitfield
.word
)
2210 && !(t0
.bitfield
.dword
& t1
.bitfield
.dword
)
2211 && !(t0
.bitfield
.qword
& t1
.bitfield
.qword
)
2212 && !(t0
.bitfield
.xmmword
& t1
.bitfield
.xmmword
)
2213 && !(t0
.bitfield
.ymmword
& t1
.bitfield
.ymmword
)
2214 && !(t0
.bitfield
.zmmword
& t1
.bitfield
.zmmword
))
2217 i
.error
= register_type_mismatch
;
2222 static INLINE
unsigned int
2223 register_number (const reg_entry
*r
)
2225 unsigned int nr
= r
->reg_num
;
2227 if (r
->reg_flags
& RegRex
)
2230 if (r
->reg_flags
& RegVRex
)
2236 static INLINE
unsigned int
2237 mode_from_disp_size (i386_operand_type t
)
2239 if (t
.bitfield
.disp8
)
2241 else if (t
.bitfield
.disp16
2242 || t
.bitfield
.disp32
2243 || t
.bitfield
.disp32s
)
2250 fits_in_signed_byte (addressT num
)
2252 return num
+ 0x80 <= 0xff;
2256 fits_in_unsigned_byte (addressT num
)
2262 fits_in_unsigned_word (addressT num
)
2264 return num
<= 0xffff;
2268 fits_in_signed_word (addressT num
)
2270 return num
+ 0x8000 <= 0xffff;
2274 fits_in_signed_long (addressT num ATTRIBUTE_UNUSED
)
2279 return num
+ 0x80000000 <= 0xffffffff;
2281 } /* fits_in_signed_long() */
2284 fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED
)
2289 return num
<= 0xffffffff;
2291 } /* fits_in_unsigned_long() */
2294 fits_in_disp8 (offsetT num
)
2296 int shift
= i
.memshift
;
2302 mask
= (1 << shift
) - 1;
2304 /* Return 0 if NUM isn't properly aligned. */
2308 /* Check if NUM will fit in 8bit after shift. */
2309 return fits_in_signed_byte (num
>> shift
);
2313 fits_in_imm4 (offsetT num
)
2315 return (num
& 0xf) == num
;
2318 static i386_operand_type
2319 smallest_imm_type (offsetT num
)
2321 i386_operand_type t
;
2323 operand_type_set (&t
, 0);
2324 t
.bitfield
.imm64
= 1;
2326 if (cpu_arch_tune
!= PROCESSOR_I486
&& num
== 1)
2328 /* This code is disabled on the 486 because all the Imm1 forms
2329 in the opcode table are slower on the i486. They're the
2330 versions with the implicitly specified single-position
2331 displacement, which has another syntax if you really want to
2333 t
.bitfield
.imm1
= 1;
2334 t
.bitfield
.imm8
= 1;
2335 t
.bitfield
.imm8s
= 1;
2336 t
.bitfield
.imm16
= 1;
2337 t
.bitfield
.imm32
= 1;
2338 t
.bitfield
.imm32s
= 1;
2340 else if (fits_in_signed_byte (num
))
2342 t
.bitfield
.imm8
= 1;
2343 t
.bitfield
.imm8s
= 1;
2344 t
.bitfield
.imm16
= 1;
2345 t
.bitfield
.imm32
= 1;
2346 t
.bitfield
.imm32s
= 1;
2348 else if (fits_in_unsigned_byte (num
))
2350 t
.bitfield
.imm8
= 1;
2351 t
.bitfield
.imm16
= 1;
2352 t
.bitfield
.imm32
= 1;
2353 t
.bitfield
.imm32s
= 1;
2355 else if (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
2357 t
.bitfield
.imm16
= 1;
2358 t
.bitfield
.imm32
= 1;
2359 t
.bitfield
.imm32s
= 1;
2361 else if (fits_in_signed_long (num
))
2363 t
.bitfield
.imm32
= 1;
2364 t
.bitfield
.imm32s
= 1;
2366 else if (fits_in_unsigned_long (num
))
2367 t
.bitfield
.imm32
= 1;
2373 offset_in_range (offsetT val
, int size
)
2379 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
2380 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
2381 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
2383 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
2389 /* If BFD64, sign extend val for 32bit address mode. */
2390 if (flag_code
!= CODE_64BIT
2391 || i
.prefix
[ADDR_PREFIX
])
2392 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
2393 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
2396 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
2398 char buf1
[40], buf2
[40];
2400 sprint_value (buf1
, val
);
2401 sprint_value (buf2
, val
& mask
);
2402 as_warn (_("%s shortened to %s"), buf1
, buf2
);
2417 a. PREFIX_EXIST if attempting to add a prefix where one from the
2418 same class already exists.
2419 b. PREFIX_LOCK if lock prefix is added.
2420 c. PREFIX_REP if rep/repne prefix is added.
2421 d. PREFIX_DS if ds prefix is added.
2422 e. PREFIX_OTHER if other prefix is added.
2425 static enum PREFIX_GROUP
2426 add_prefix (unsigned int prefix
)
2428 enum PREFIX_GROUP ret
= PREFIX_OTHER
;
2431 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
2432 && flag_code
== CODE_64BIT
)
2434 if ((i
.prefix
[REX_PREFIX
] & prefix
& REX_W
)
2435 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_R
)
2436 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_X
)
2437 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_B
))
2448 case DS_PREFIX_OPCODE
:
2451 case CS_PREFIX_OPCODE
:
2452 case ES_PREFIX_OPCODE
:
2453 case FS_PREFIX_OPCODE
:
2454 case GS_PREFIX_OPCODE
:
2455 case SS_PREFIX_OPCODE
:
2459 case REPNE_PREFIX_OPCODE
:
2460 case REPE_PREFIX_OPCODE
:
2465 case LOCK_PREFIX_OPCODE
:
2474 case ADDR_PREFIX_OPCODE
:
2478 case DATA_PREFIX_OPCODE
:
2482 if (i
.prefix
[q
] != 0)
2490 i
.prefix
[q
] |= prefix
;
2493 as_bad (_("same type of prefix used twice"));
2499 update_code_flag (int value
, int check
)
2501 PRINTF_LIKE ((*as_error
));
2503 flag_code
= (enum flag_code
) value
;
2504 if (flag_code
== CODE_64BIT
)
2506 cpu_arch_flags
.bitfield
.cpu64
= 1;
2507 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2511 cpu_arch_flags
.bitfield
.cpu64
= 0;
2512 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2514 if (value
== CODE_64BIT
&& !cpu_arch_flags
.bitfield
.cpulm
)
2517 as_error
= as_fatal
;
2520 (*as_error
) (_("64bit mode not supported on `%s'."),
2521 cpu_arch_name
? cpu_arch_name
: default_arch
);
2523 if (value
== CODE_32BIT
&& !cpu_arch_flags
.bitfield
.cpui386
)
2526 as_error
= as_fatal
;
2529 (*as_error
) (_("32bit mode not supported on `%s'."),
2530 cpu_arch_name
? cpu_arch_name
: default_arch
);
2532 stackop_size
= '\0';
2536 set_code_flag (int value
)
2538 update_code_flag (value
, 0);
2542 set_16bit_gcc_code_flag (int new_code_flag
)
2544 flag_code
= (enum flag_code
) new_code_flag
;
2545 if (flag_code
!= CODE_16BIT
)
2547 cpu_arch_flags
.bitfield
.cpu64
= 0;
2548 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2549 stackop_size
= LONG_MNEM_SUFFIX
;
2553 set_intel_syntax (int syntax_flag
)
2555 /* Find out if register prefixing is specified. */
2556 int ask_naked_reg
= 0;
2559 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2562 int e
= get_symbol_name (&string
);
2564 if (strcmp (string
, "prefix") == 0)
2566 else if (strcmp (string
, "noprefix") == 0)
2569 as_bad (_("bad argument to syntax directive."));
2570 (void) restore_line_pointer (e
);
2572 demand_empty_rest_of_line ();
2574 intel_syntax
= syntax_flag
;
2576 if (ask_naked_reg
== 0)
2577 allow_naked_reg
= (intel_syntax
2578 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
2580 allow_naked_reg
= (ask_naked_reg
< 0);
2582 expr_set_rank (O_full_ptr
, syntax_flag
? 10 : 0);
2584 identifier_chars
['%'] = intel_syntax
&& allow_naked_reg
? '%' : 0;
2585 identifier_chars
['$'] = intel_syntax
? '$' : 0;
2586 register_prefix
= allow_naked_reg
? "" : "%";
2590 set_intel_mnemonic (int mnemonic_flag
)
2592 intel_mnemonic
= mnemonic_flag
;
2596 set_allow_index_reg (int flag
)
2598 allow_index_reg
= flag
;
2602 set_check (int what
)
2604 enum check_kind
*kind
;
2609 kind
= &operand_check
;
2620 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2623 int e
= get_symbol_name (&string
);
2625 if (strcmp (string
, "none") == 0)
2627 else if (strcmp (string
, "warning") == 0)
2628 *kind
= check_warning
;
2629 else if (strcmp (string
, "error") == 0)
2630 *kind
= check_error
;
2632 as_bad (_("bad argument to %s_check directive."), str
);
2633 (void) restore_line_pointer (e
);
2636 as_bad (_("missing argument for %s_check directive"), str
);
2638 demand_empty_rest_of_line ();
2642 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED
,
2643 i386_cpu_flags new_flag ATTRIBUTE_UNUSED
)
2645 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2646 static const char *arch
;
2648 /* Intel LIOM is only supported on ELF. */
2654 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2655 use default_arch. */
2656 arch
= cpu_arch_name
;
2658 arch
= default_arch
;
2661 /* If we are targeting Intel MCU, we must enable it. */
2662 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_IAMCU
2663 || new_flag
.bitfield
.cpuiamcu
)
2666 /* If we are targeting Intel L1OM, we must enable it. */
2667 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_L1OM
2668 || new_flag
.bitfield
.cpul1om
)
2671 /* If we are targeting Intel K1OM, we must enable it. */
2672 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_K1OM
2673 || new_flag
.bitfield
.cpuk1om
)
2676 as_bad (_("`%s' is not supported on `%s'"), name
, arch
);
2681 set_cpu_arch (int dummy ATTRIBUTE_UNUSED
)
2685 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2688 int e
= get_symbol_name (&string
);
2690 i386_cpu_flags flags
;
2692 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
2694 if (strcmp (string
, cpu_arch
[j
].name
) == 0)
2696 check_cpu_arch_compatible (string
, cpu_arch
[j
].flags
);
2700 cpu_arch_name
= cpu_arch
[j
].name
;
2701 cpu_sub_arch_name
= NULL
;
2702 cpu_arch_flags
= cpu_arch
[j
].flags
;
2703 if (flag_code
== CODE_64BIT
)
2705 cpu_arch_flags
.bitfield
.cpu64
= 1;
2706 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2710 cpu_arch_flags
.bitfield
.cpu64
= 0;
2711 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2713 cpu_arch_isa
= cpu_arch
[j
].type
;
2714 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
2715 if (!cpu_arch_tune_set
)
2717 cpu_arch_tune
= cpu_arch_isa
;
2718 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
2723 flags
= cpu_flags_or (cpu_arch_flags
,
2726 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2728 if (cpu_sub_arch_name
)
2730 char *name
= cpu_sub_arch_name
;
2731 cpu_sub_arch_name
= concat (name
,
2733 (const char *) NULL
);
2737 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
2738 cpu_arch_flags
= flags
;
2739 cpu_arch_isa_flags
= flags
;
2743 = cpu_flags_or (cpu_arch_isa_flags
,
2745 (void) restore_line_pointer (e
);
2746 demand_empty_rest_of_line ();
2751 if (*string
== '.' && j
>= ARRAY_SIZE (cpu_arch
))
2753 /* Disable an ISA extension. */
2754 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
2755 if (strcmp (string
+ 1, cpu_noarch
[j
].name
) == 0)
2757 flags
= cpu_flags_and_not (cpu_arch_flags
,
2758 cpu_noarch
[j
].flags
);
2759 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2761 if (cpu_sub_arch_name
)
2763 char *name
= cpu_sub_arch_name
;
2764 cpu_sub_arch_name
= concat (name
, string
,
2765 (const char *) NULL
);
2769 cpu_sub_arch_name
= xstrdup (string
);
2770 cpu_arch_flags
= flags
;
2771 cpu_arch_isa_flags
= flags
;
2773 (void) restore_line_pointer (e
);
2774 demand_empty_rest_of_line ();
2778 j
= ARRAY_SIZE (cpu_arch
);
2781 if (j
>= ARRAY_SIZE (cpu_arch
))
2782 as_bad (_("no such architecture: `%s'"), string
);
2784 *input_line_pointer
= e
;
2787 as_bad (_("missing cpu architecture"));
2789 no_cond_jump_promotion
= 0;
2790 if (*input_line_pointer
== ','
2791 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
2796 ++input_line_pointer
;
2797 e
= get_symbol_name (&string
);
2799 if (strcmp (string
, "nojumps") == 0)
2800 no_cond_jump_promotion
= 1;
2801 else if (strcmp (string
, "jumps") == 0)
2804 as_bad (_("no such architecture modifier: `%s'"), string
);
2806 (void) restore_line_pointer (e
);
2809 demand_empty_rest_of_line ();
2812 enum bfd_architecture
2815 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2817 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2818 || flag_code
!= CODE_64BIT
)
2819 as_fatal (_("Intel L1OM is 64bit ELF only"));
2820 return bfd_arch_l1om
;
2822 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2824 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2825 || flag_code
!= CODE_64BIT
)
2826 as_fatal (_("Intel K1OM is 64bit ELF only"));
2827 return bfd_arch_k1om
;
2829 else if (cpu_arch_isa
== PROCESSOR_IAMCU
)
2831 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2832 || flag_code
== CODE_64BIT
)
2833 as_fatal (_("Intel MCU is 32bit ELF only"));
2834 return bfd_arch_iamcu
;
2837 return bfd_arch_i386
;
2843 if (!strncmp (default_arch
, "x86_64", 6))
2845 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2847 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2848 || default_arch
[6] != '\0')
2849 as_fatal (_("Intel L1OM is 64bit ELF only"));
2850 return bfd_mach_l1om
;
2852 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2854 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2855 || default_arch
[6] != '\0')
2856 as_fatal (_("Intel K1OM is 64bit ELF only"));
2857 return bfd_mach_k1om
;
2859 else if (default_arch
[6] == '\0')
2860 return bfd_mach_x86_64
;
2862 return bfd_mach_x64_32
;
2864 else if (!strcmp (default_arch
, "i386")
2865 || !strcmp (default_arch
, "iamcu"))
2867 if (cpu_arch_isa
== PROCESSOR_IAMCU
)
2869 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
2870 as_fatal (_("Intel MCU is 32bit ELF only"));
2871 return bfd_mach_i386_iamcu
;
2874 return bfd_mach_i386_i386
;
2877 as_fatal (_("unknown architecture"));
2883 const char *hash_err
;
2885 /* Support pseudo prefixes like {disp32}. */
2886 lex_type
['{'] = LEX_BEGIN_NAME
;
2888 /* Initialize op_hash hash table. */
2889 op_hash
= hash_new ();
2892 const insn_template
*optab
;
2893 templates
*core_optab
;
2895 /* Setup for loop. */
2897 core_optab
= XNEW (templates
);
2898 core_optab
->start
= optab
;
2903 if (optab
->name
== NULL
2904 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
2906 /* different name --> ship out current template list;
2907 add to hash table; & begin anew. */
2908 core_optab
->end
= optab
;
2909 hash_err
= hash_insert (op_hash
,
2911 (void *) core_optab
);
2914 as_fatal (_("can't hash %s: %s"),
2918 if (optab
->name
== NULL
)
2920 core_optab
= XNEW (templates
);
2921 core_optab
->start
= optab
;
2926 /* Initialize reg_hash hash table. */
2927 reg_hash
= hash_new ();
2929 const reg_entry
*regtab
;
2930 unsigned int regtab_size
= i386_regtab_size
;
2932 for (regtab
= i386_regtab
; regtab_size
--; regtab
++)
2934 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (void *) regtab
);
2936 as_fatal (_("can't hash %s: %s"),
2942 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
2947 for (c
= 0; c
< 256; c
++)
2952 mnemonic_chars
[c
] = c
;
2953 register_chars
[c
] = c
;
2954 operand_chars
[c
] = c
;
2956 else if (ISLOWER (c
))
2958 mnemonic_chars
[c
] = c
;
2959 register_chars
[c
] = c
;
2960 operand_chars
[c
] = c
;
2962 else if (ISUPPER (c
))
2964 mnemonic_chars
[c
] = TOLOWER (c
);
2965 register_chars
[c
] = mnemonic_chars
[c
];
2966 operand_chars
[c
] = c
;
2968 else if (c
== '{' || c
== '}')
2970 mnemonic_chars
[c
] = c
;
2971 operand_chars
[c
] = c
;
2974 if (ISALPHA (c
) || ISDIGIT (c
))
2975 identifier_chars
[c
] = c
;
2978 identifier_chars
[c
] = c
;
2979 operand_chars
[c
] = c
;
2984 identifier_chars
['@'] = '@';
2987 identifier_chars
['?'] = '?';
2988 operand_chars
['?'] = '?';
2990 digit_chars
['-'] = '-';
2991 mnemonic_chars
['_'] = '_';
2992 mnemonic_chars
['-'] = '-';
2993 mnemonic_chars
['.'] = '.';
2994 identifier_chars
['_'] = '_';
2995 identifier_chars
['.'] = '.';
2997 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
2998 operand_chars
[(unsigned char) *p
] = *p
;
3001 if (flag_code
== CODE_64BIT
)
3003 #if defined (OBJ_COFF) && defined (TE_PE)
3004 x86_dwarf2_return_column
= (OUTPUT_FLAVOR
== bfd_target_coff_flavour
3007 x86_dwarf2_return_column
= 16;
3009 x86_cie_data_alignment
= -8;
3013 x86_dwarf2_return_column
= 8;
3014 x86_cie_data_alignment
= -4;
3019 i386_print_statistics (FILE *file
)
3021 hash_print_statistics (file
, "i386 opcode", op_hash
);
3022 hash_print_statistics (file
, "i386 register", reg_hash
);
3027 /* Debugging routines for md_assemble. */
3028 static void pte (insn_template
*);
3029 static void pt (i386_operand_type
);
3030 static void pe (expressionS
*);
3031 static void ps (symbolS
*);
3034 pi (const char *line
, i386_insn
*x
)
3038 fprintf (stdout
, "%s: template ", line
);
3040 fprintf (stdout
, " address: base %s index %s scale %x\n",
3041 x
->base_reg
? x
->base_reg
->reg_name
: "none",
3042 x
->index_reg
? x
->index_reg
->reg_name
: "none",
3043 x
->log2_scale_factor
);
3044 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
3045 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
3046 fprintf (stdout
, " sib: base %x index %x scale %x\n",
3047 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
3048 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
3049 (x
->rex
& REX_W
) != 0,
3050 (x
->rex
& REX_R
) != 0,
3051 (x
->rex
& REX_X
) != 0,
3052 (x
->rex
& REX_B
) != 0);
3053 for (j
= 0; j
< x
->operands
; j
++)
3055 fprintf (stdout
, " #%d: ", j
+ 1);
3057 fprintf (stdout
, "\n");
3058 if (x
->types
[j
].bitfield
.class == Reg
3059 || x
->types
[j
].bitfield
.class == RegMMX
3060 || x
->types
[j
].bitfield
.class == RegSIMD
3061 || x
->types
[j
].bitfield
.class == SReg
3062 || x
->types
[j
].bitfield
.class == RegCR
3063 || x
->types
[j
].bitfield
.class == RegDR
3064 || x
->types
[j
].bitfield
.class == RegTR
)
3065 fprintf (stdout
, "%s\n", x
->op
[j
].regs
->reg_name
);
3066 if (operand_type_check (x
->types
[j
], imm
))
3068 if (operand_type_check (x
->types
[j
], disp
))
3069 pe (x
->op
[j
].disps
);
3074 pte (insn_template
*t
)
3077 fprintf (stdout
, " %d operands ", t
->operands
);
3078 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
3079 if (t
->extension_opcode
!= None
)
3080 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
3081 if (t
->opcode_modifier
.d
)
3082 fprintf (stdout
, "D");
3083 if (t
->opcode_modifier
.w
)
3084 fprintf (stdout
, "W");
3085 fprintf (stdout
, "\n");
3086 for (j
= 0; j
< t
->operands
; j
++)
3088 fprintf (stdout
, " #%d type ", j
+ 1);
3089 pt (t
->operand_types
[j
]);
3090 fprintf (stdout
, "\n");
3097 fprintf (stdout
, " operation %d\n", e
->X_op
);
3098 fprintf (stdout
, " add_number %ld (%lx)\n",
3099 (long) e
->X_add_number
, (long) e
->X_add_number
);
3100 if (e
->X_add_symbol
)
3102 fprintf (stdout
, " add_symbol ");
3103 ps (e
->X_add_symbol
);
3104 fprintf (stdout
, "\n");
3108 fprintf (stdout
, " op_symbol ");
3109 ps (e
->X_op_symbol
);
3110 fprintf (stdout
, "\n");
3117 fprintf (stdout
, "%s type %s%s",
3119 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
3120 segment_name (S_GET_SEGMENT (s
)));
3123 static struct type_name
3125 i386_operand_type mask
;
3128 const type_names
[] =
3130 { OPERAND_TYPE_REG8
, "r8" },
3131 { OPERAND_TYPE_REG16
, "r16" },
3132 { OPERAND_TYPE_REG32
, "r32" },
3133 { OPERAND_TYPE_REG64
, "r64" },
3134 { OPERAND_TYPE_ACC8
, "acc8" },
3135 { OPERAND_TYPE_ACC16
, "acc16" },
3136 { OPERAND_TYPE_ACC32
, "acc32" },
3137 { OPERAND_TYPE_ACC64
, "acc64" },
3138 { OPERAND_TYPE_IMM8
, "i8" },
3139 { OPERAND_TYPE_IMM8
, "i8s" },
3140 { OPERAND_TYPE_IMM16
, "i16" },
3141 { OPERAND_TYPE_IMM32
, "i32" },
3142 { OPERAND_TYPE_IMM32S
, "i32s" },
3143 { OPERAND_TYPE_IMM64
, "i64" },
3144 { OPERAND_TYPE_IMM1
, "i1" },
3145 { OPERAND_TYPE_BASEINDEX
, "BaseIndex" },
3146 { OPERAND_TYPE_DISP8
, "d8" },
3147 { OPERAND_TYPE_DISP16
, "d16" },
3148 { OPERAND_TYPE_DISP32
, "d32" },
3149 { OPERAND_TYPE_DISP32S
, "d32s" },
3150 { OPERAND_TYPE_DISP64
, "d64" },
3151 { OPERAND_TYPE_INOUTPORTREG
, "InOutPortReg" },
3152 { OPERAND_TYPE_SHIFTCOUNT
, "ShiftCount" },
3153 { OPERAND_TYPE_CONTROL
, "control reg" },
3154 { OPERAND_TYPE_TEST
, "test reg" },
3155 { OPERAND_TYPE_DEBUG
, "debug reg" },
3156 { OPERAND_TYPE_FLOATREG
, "FReg" },
3157 { OPERAND_TYPE_FLOATACC
, "FAcc" },
3158 { OPERAND_TYPE_SREG
, "SReg" },
3159 { OPERAND_TYPE_REGMMX
, "rMMX" },
3160 { OPERAND_TYPE_REGXMM
, "rXMM" },
3161 { OPERAND_TYPE_REGYMM
, "rYMM" },
3162 { OPERAND_TYPE_REGZMM
, "rZMM" },
3163 { OPERAND_TYPE_REGMASK
, "Mask reg" },
3167 pt (i386_operand_type t
)
3170 i386_operand_type a
;
3172 for (j
= 0; j
< ARRAY_SIZE (type_names
); j
++)
3174 a
= operand_type_and (t
, type_names
[j
].mask
);
3175 if (operand_type_equal (&a
, &type_names
[j
].mask
))
3176 fprintf (stdout
, "%s, ", type_names
[j
].name
);
3181 #endif /* DEBUG386 */
3183 static bfd_reloc_code_real_type
3184 reloc (unsigned int size
,
3187 bfd_reloc_code_real_type other
)
3189 if (other
!= NO_RELOC
)
3191 reloc_howto_type
*rel
;
3196 case BFD_RELOC_X86_64_GOT32
:
3197 return BFD_RELOC_X86_64_GOT64
;
3199 case BFD_RELOC_X86_64_GOTPLT64
:
3200 return BFD_RELOC_X86_64_GOTPLT64
;
3202 case BFD_RELOC_X86_64_PLTOFF64
:
3203 return BFD_RELOC_X86_64_PLTOFF64
;
3205 case BFD_RELOC_X86_64_GOTPC32
:
3206 other
= BFD_RELOC_X86_64_GOTPC64
;
3208 case BFD_RELOC_X86_64_GOTPCREL
:
3209 other
= BFD_RELOC_X86_64_GOTPCREL64
;
3211 case BFD_RELOC_X86_64_TPOFF32
:
3212 other
= BFD_RELOC_X86_64_TPOFF64
;
3214 case BFD_RELOC_X86_64_DTPOFF32
:
3215 other
= BFD_RELOC_X86_64_DTPOFF64
;
3221 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3222 if (other
== BFD_RELOC_SIZE32
)
3225 other
= BFD_RELOC_SIZE64
;
3228 as_bad (_("there are no pc-relative size relocations"));
3234 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
3235 if (size
== 4 && (flag_code
!= CODE_64BIT
|| disallow_64bit_reloc
))
3238 rel
= bfd_reloc_type_lookup (stdoutput
, other
);
3240 as_bad (_("unknown relocation (%u)"), other
);
3241 else if (size
!= bfd_get_reloc_size (rel
))
3242 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
3243 bfd_get_reloc_size (rel
),
3245 else if (pcrel
&& !rel
->pc_relative
)
3246 as_bad (_("non-pc-relative relocation for pc-relative field"));
3247 else if ((rel
->complain_on_overflow
== complain_overflow_signed
3249 || (rel
->complain_on_overflow
== complain_overflow_unsigned
3251 as_bad (_("relocated field and relocation type differ in signedness"));
3260 as_bad (_("there are no unsigned pc-relative relocations"));
3263 case 1: return BFD_RELOC_8_PCREL
;
3264 case 2: return BFD_RELOC_16_PCREL
;
3265 case 4: return BFD_RELOC_32_PCREL
;
3266 case 8: return BFD_RELOC_64_PCREL
;
3268 as_bad (_("cannot do %u byte pc-relative relocation"), size
);
3275 case 4: return BFD_RELOC_X86_64_32S
;
3280 case 1: return BFD_RELOC_8
;
3281 case 2: return BFD_RELOC_16
;
3282 case 4: return BFD_RELOC_32
;
3283 case 8: return BFD_RELOC_64
;
3285 as_bad (_("cannot do %s %u byte relocation"),
3286 sign
> 0 ? "signed" : "unsigned", size
);
3292 /* Here we decide which fixups can be adjusted to make them relative to
3293 the beginning of the section instead of the symbol. Basically we need
3294 to make sure that the dynamic relocations are done correctly, so in
3295 some cases we force the original symbol to be used. */
3298 tc_i386_fix_adjustable (fixS
*fixP ATTRIBUTE_UNUSED
)
3300 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3304 /* Don't adjust pc-relative references to merge sections in 64-bit
3306 if (use_rela_relocations
3307 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
3311 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
3312 and changed later by validate_fix. */
3313 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
3314 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
3317 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
3318 for size relocations. */
3319 if (fixP
->fx_r_type
== BFD_RELOC_SIZE32
3320 || fixP
->fx_r_type
== BFD_RELOC_SIZE64
3321 || fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
3322 || fixP
->fx_r_type
== BFD_RELOC_386_PLT32
3323 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
3324 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32X
3325 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
3326 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
3327 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
3328 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
3329 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
3330 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
3331 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
3332 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
3333 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTDESC
3334 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_DESC_CALL
3335 || fixP
->fx_r_type
== BFD_RELOC_X86_64_PLT32
3336 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
3337 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
3338 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCRELX
3339 || fixP
->fx_r_type
== BFD_RELOC_X86_64_REX_GOTPCRELX
3340 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
3341 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
3342 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
3343 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
3344 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
3345 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
3346 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
3347 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
3348 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPC32_TLSDESC
3349 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSDESC_CALL
3350 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
3351 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
3358 intel_float_operand (const char *mnemonic
)
3360 /* Note that the value returned is meaningful only for opcodes with (memory)
3361 operands, hence the code here is free to improperly handle opcodes that
3362 have no operands (for better performance and smaller code). */
3364 if (mnemonic
[0] != 'f')
3365 return 0; /* non-math */
3367 switch (mnemonic
[1])
3369 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
3370 the fs segment override prefix not currently handled because no
3371 call path can make opcodes without operands get here */
3373 return 2 /* integer op */;
3375 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
3376 return 3; /* fldcw/fldenv */
3379 if (mnemonic
[2] != 'o' /* fnop */)
3380 return 3; /* non-waiting control op */
3383 if (mnemonic
[2] == 's')
3384 return 3; /* frstor/frstpm */
3387 if (mnemonic
[2] == 'a')
3388 return 3; /* fsave */
3389 if (mnemonic
[2] == 't')
3391 switch (mnemonic
[3])
3393 case 'c': /* fstcw */
3394 case 'd': /* fstdw */
3395 case 'e': /* fstenv */
3396 case 's': /* fsts[gw] */
3402 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
3403 return 0; /* fxsave/fxrstor are not really math ops */
3410 /* Build the VEX prefix. */
3413 build_vex_prefix (const insn_template
*t
)
3415 unsigned int register_specifier
;
3416 unsigned int implied_prefix
;
3417 unsigned int vector_length
;
3420 /* Check register specifier. */
3421 if (i
.vex
.register_specifier
)
3423 register_specifier
=
3424 ~register_number (i
.vex
.register_specifier
) & 0xf;
3425 gas_assert ((i
.vex
.register_specifier
->reg_flags
& RegVRex
) == 0);
3428 register_specifier
= 0xf;
3430 /* Use 2-byte VEX prefix by swapping destination and source operand
3431 if there are more than 1 register operand. */
3432 if (i
.reg_operands
> 1
3433 && i
.vec_encoding
!= vex_encoding_vex3
3434 && i
.dir_encoding
== dir_encoding_default
3435 && i
.operands
== i
.reg_operands
3436 && operand_type_equal (&i
.types
[0], &i
.types
[i
.operands
- 1])
3437 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3438 && (i
.tm
.opcode_modifier
.load
|| i
.tm
.opcode_modifier
.d
)
3441 unsigned int xchg
= i
.operands
- 1;
3442 union i386_op temp_op
;
3443 i386_operand_type temp_type
;
3445 temp_type
= i
.types
[xchg
];
3446 i
.types
[xchg
] = i
.types
[0];
3447 i
.types
[0] = temp_type
;
3448 temp_op
= i
.op
[xchg
];
3449 i
.op
[xchg
] = i
.op
[0];
3452 gas_assert (i
.rm
.mode
== 3);
3456 i
.rm
.regmem
= i
.rm
.reg
;
3459 if (i
.tm
.opcode_modifier
.d
)
3460 i
.tm
.base_opcode
^= (i
.tm
.base_opcode
& 0xee) != 0x6e
3461 ? Opcode_SIMD_FloatD
: Opcode_SIMD_IntD
;
3462 else /* Use the next insn. */
3466 /* Use 2-byte VEX prefix by swapping commutative source operands if there
3467 are no memory operands and at least 3 register ones. */
3468 if (i
.reg_operands
>= 3
3469 && i
.vec_encoding
!= vex_encoding_vex3
3470 && i
.reg_operands
== i
.operands
- i
.imm_operands
3471 && i
.tm
.opcode_modifier
.vex
3472 && i
.tm
.opcode_modifier
.commutative
3473 && (i
.tm
.opcode_modifier
.sse2avx
|| optimize
> 1)
3475 && i
.vex
.register_specifier
3476 && !(i
.vex
.register_specifier
->reg_flags
& RegRex
))
3478 unsigned int xchg
= i
.operands
- i
.reg_operands
;
3479 union i386_op temp_op
;
3480 i386_operand_type temp_type
;
3482 gas_assert (i
.tm
.opcode_modifier
.vexopcode
== VEX0F
);
3483 gas_assert (!i
.tm
.opcode_modifier
.sae
);
3484 gas_assert (operand_type_equal (&i
.types
[i
.operands
- 2],
3485 &i
.types
[i
.operands
- 3]));
3486 gas_assert (i
.rm
.mode
== 3);
3488 temp_type
= i
.types
[xchg
];
3489 i
.types
[xchg
] = i
.types
[xchg
+ 1];
3490 i
.types
[xchg
+ 1] = temp_type
;
3491 temp_op
= i
.op
[xchg
];
3492 i
.op
[xchg
] = i
.op
[xchg
+ 1];
3493 i
.op
[xchg
+ 1] = temp_op
;
3496 xchg
= i
.rm
.regmem
| 8;
3497 i
.rm
.regmem
= ~register_specifier
& 0xf;
3498 gas_assert (!(i
.rm
.regmem
& 8));
3499 i
.vex
.register_specifier
+= xchg
- i
.rm
.regmem
;
3500 register_specifier
= ~xchg
& 0xf;
3503 if (i
.tm
.opcode_modifier
.vex
== VEXScalar
)
3504 vector_length
= avxscalar
;
3505 else if (i
.tm
.opcode_modifier
.vex
== VEX256
)
3511 /* Determine vector length from the last multi-length vector
3514 for (op
= t
->operands
; op
--;)
3515 if (t
->operand_types
[op
].bitfield
.xmmword
3516 && t
->operand_types
[op
].bitfield
.ymmword
3517 && i
.types
[op
].bitfield
.ymmword
)
3524 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3529 case DATA_PREFIX_OPCODE
:
3532 case REPE_PREFIX_OPCODE
:
3535 case REPNE_PREFIX_OPCODE
:
3542 /* Check the REX.W bit and VEXW. */
3543 if (i
.tm
.opcode_modifier
.vexw
== VEXWIG
)
3544 w
= (vexwig
== vexw1
|| (i
.rex
& REX_W
)) ? 1 : 0;
3545 else if (i
.tm
.opcode_modifier
.vexw
)
3546 w
= i
.tm
.opcode_modifier
.vexw
== VEXW1
? 1 : 0;
3548 w
= (flag_code
== CODE_64BIT
? i
.rex
& REX_W
: vexwig
== vexw1
) ? 1 : 0;
3550 /* Use 2-byte VEX prefix if possible. */
3552 && i
.vec_encoding
!= vex_encoding_vex3
3553 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3554 && (i
.rex
& (REX_W
| REX_X
| REX_B
)) == 0)
3556 /* 2-byte VEX prefix. */
3560 i
.vex
.bytes
[0] = 0xc5;
3562 /* Check the REX.R bit. */
3563 r
= (i
.rex
& REX_R
) ? 0 : 1;
3564 i
.vex
.bytes
[1] = (r
<< 7
3565 | register_specifier
<< 3
3566 | vector_length
<< 2
3571 /* 3-byte VEX prefix. */
3576 switch (i
.tm
.opcode_modifier
.vexopcode
)
3580 i
.vex
.bytes
[0] = 0xc4;
3584 i
.vex
.bytes
[0] = 0xc4;
3588 i
.vex
.bytes
[0] = 0xc4;
3592 i
.vex
.bytes
[0] = 0x8f;
3596 i
.vex
.bytes
[0] = 0x8f;
3600 i
.vex
.bytes
[0] = 0x8f;
3606 /* The high 3 bits of the second VEX byte are 1's compliment
3607 of RXB bits from REX. */
3608 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3610 i
.vex
.bytes
[2] = (w
<< 7
3611 | register_specifier
<< 3
3612 | vector_length
<< 2
3617 static INLINE bfd_boolean
3618 is_evex_encoding (const insn_template
*t
)
3620 return t
->opcode_modifier
.evex
|| t
->opcode_modifier
.disp8memshift
3621 || t
->opcode_modifier
.broadcast
|| t
->opcode_modifier
.masking
3622 || t
->opcode_modifier
.sae
;
3625 static INLINE bfd_boolean
3626 is_any_vex_encoding (const insn_template
*t
)
3628 return t
->opcode_modifier
.vex
|| t
->opcode_modifier
.vexopcode
3629 || is_evex_encoding (t
);
3632 /* Build the EVEX prefix. */
3635 build_evex_prefix (void)
3637 unsigned int register_specifier
;
3638 unsigned int implied_prefix
;
3640 rex_byte vrex_used
= 0;
3642 /* Check register specifier. */
3643 if (i
.vex
.register_specifier
)
3645 gas_assert ((i
.vrex
& REX_X
) == 0);
3647 register_specifier
= i
.vex
.register_specifier
->reg_num
;
3648 if ((i
.vex
.register_specifier
->reg_flags
& RegRex
))
3649 register_specifier
+= 8;
3650 /* The upper 16 registers are encoded in the fourth byte of the
3652 if (!(i
.vex
.register_specifier
->reg_flags
& RegVRex
))
3653 i
.vex
.bytes
[3] = 0x8;
3654 register_specifier
= ~register_specifier
& 0xf;
3658 register_specifier
= 0xf;
3660 /* Encode upper 16 vector index register in the fourth byte of
3662 if (!(i
.vrex
& REX_X
))
3663 i
.vex
.bytes
[3] = 0x8;
3668 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3673 case DATA_PREFIX_OPCODE
:
3676 case REPE_PREFIX_OPCODE
:
3679 case REPNE_PREFIX_OPCODE
:
3686 /* 4 byte EVEX prefix. */
3688 i
.vex
.bytes
[0] = 0x62;
3691 switch (i
.tm
.opcode_modifier
.vexopcode
)
3707 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3709 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3711 /* The fifth bit of the second EVEX byte is 1's compliment of the
3712 REX_R bit in VREX. */
3713 if (!(i
.vrex
& REX_R
))
3714 i
.vex
.bytes
[1] |= 0x10;
3718 if ((i
.reg_operands
+ i
.imm_operands
) == i
.operands
)
3720 /* When all operands are registers, the REX_X bit in REX is not
3721 used. We reuse it to encode the upper 16 registers, which is
3722 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3723 as 1's compliment. */
3724 if ((i
.vrex
& REX_B
))
3727 i
.vex
.bytes
[1] &= ~0x40;
3731 /* EVEX instructions shouldn't need the REX prefix. */
3732 i
.vrex
&= ~vrex_used
;
3733 gas_assert (i
.vrex
== 0);
3735 /* Check the REX.W bit and VEXW. */
3736 if (i
.tm
.opcode_modifier
.vexw
== VEXWIG
)
3737 w
= (evexwig
== evexw1
|| (i
.rex
& REX_W
)) ? 1 : 0;
3738 else if (i
.tm
.opcode_modifier
.vexw
)
3739 w
= i
.tm
.opcode_modifier
.vexw
== VEXW1
? 1 : 0;
3741 w
= (flag_code
== CODE_64BIT
? i
.rex
& REX_W
: evexwig
== evexw1
) ? 1 : 0;
3743 /* Encode the U bit. */
3744 implied_prefix
|= 0x4;
3746 /* The third byte of the EVEX prefix. */
3747 i
.vex
.bytes
[2] = (w
<< 7 | register_specifier
<< 3 | implied_prefix
);
3749 /* The fourth byte of the EVEX prefix. */
3750 /* The zeroing-masking bit. */
3751 if (i
.mask
&& i
.mask
->zeroing
)
3752 i
.vex
.bytes
[3] |= 0x80;
3754 /* Don't always set the broadcast bit if there is no RC. */
3757 /* Encode the vector length. */
3758 unsigned int vec_length
;
3760 if (!i
.tm
.opcode_modifier
.evex
3761 || i
.tm
.opcode_modifier
.evex
== EVEXDYN
)
3765 /* Determine vector length from the last multi-length vector
3768 for (op
= i
.operands
; op
--;)
3769 if (i
.tm
.operand_types
[op
].bitfield
.xmmword
3770 + i
.tm
.operand_types
[op
].bitfield
.ymmword
3771 + i
.tm
.operand_types
[op
].bitfield
.zmmword
> 1)
3773 if (i
.types
[op
].bitfield
.zmmword
)
3775 i
.tm
.opcode_modifier
.evex
= EVEX512
;
3778 else if (i
.types
[op
].bitfield
.ymmword
)
3780 i
.tm
.opcode_modifier
.evex
= EVEX256
;
3783 else if (i
.types
[op
].bitfield
.xmmword
)
3785 i
.tm
.opcode_modifier
.evex
= EVEX128
;
3788 else if (i
.broadcast
&& (int) op
== i
.broadcast
->operand
)
3790 switch (i
.broadcast
->bytes
)
3793 i
.tm
.opcode_modifier
.evex
= EVEX512
;
3796 i
.tm
.opcode_modifier
.evex
= EVEX256
;
3799 i
.tm
.opcode_modifier
.evex
= EVEX128
;
3808 if (op
>= MAX_OPERANDS
)
3812 switch (i
.tm
.opcode_modifier
.evex
)
3814 case EVEXLIG
: /* LL' is ignored */
3815 vec_length
= evexlig
<< 5;
3818 vec_length
= 0 << 5;
3821 vec_length
= 1 << 5;
3824 vec_length
= 2 << 5;
3830 i
.vex
.bytes
[3] |= vec_length
;
3831 /* Encode the broadcast bit. */
3833 i
.vex
.bytes
[3] |= 0x10;
3837 if (i
.rounding
->type
!= saeonly
)
3838 i
.vex
.bytes
[3] |= 0x10 | (i
.rounding
->type
<< 5);
3840 i
.vex
.bytes
[3] |= 0x10 | (evexrcig
<< 5);
3843 if (i
.mask
&& i
.mask
->mask
)
3844 i
.vex
.bytes
[3] |= i
.mask
->mask
->reg_num
;
3848 process_immext (void)
3852 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
3853 which is coded in the same place as an 8-bit immediate field
3854 would be. Here we fake an 8-bit immediate operand from the
3855 opcode suffix stored in tm.extension_opcode.
3857 AVX instructions also use this encoding, for some of
3858 3 argument instructions. */
3860 gas_assert (i
.imm_operands
<= 1
3862 || (is_any_vex_encoding (&i
.tm
)
3863 && i
.operands
<= 4)));
3865 exp
= &im_expressions
[i
.imm_operands
++];
3866 i
.op
[i
.operands
].imms
= exp
;
3867 i
.types
[i
.operands
] = imm8
;
3869 exp
->X_op
= O_constant
;
3870 exp
->X_add_number
= i
.tm
.extension_opcode
;
3871 i
.tm
.extension_opcode
= None
;
3878 switch (i
.tm
.opcode_modifier
.hleprefixok
)
3883 as_bad (_("invalid instruction `%s' after `%s'"),
3884 i
.tm
.name
, i
.hle_prefix
);
3887 if (i
.prefix
[LOCK_PREFIX
])
3889 as_bad (_("missing `lock' with `%s'"), i
.hle_prefix
);
3893 case HLEPrefixRelease
:
3894 if (i
.prefix
[HLE_PREFIX
] != XRELEASE_PREFIX_OPCODE
)
3896 as_bad (_("instruction `%s' after `xacquire' not allowed"),
3900 if (i
.mem_operands
== 0 || !(i
.flags
[i
.operands
- 1] & Operand_Mem
))
3902 as_bad (_("memory destination needed for instruction `%s'"
3903 " after `xrelease'"), i
.tm
.name
);
3910 /* Try the shortest encoding by shortening operand size. */
3913 optimize_encoding (void)
3917 if (optimize_for_space
3918 && i
.reg_operands
== 1
3919 && i
.imm_operands
== 1
3920 && !i
.types
[1].bitfield
.byte
3921 && i
.op
[0].imms
->X_op
== O_constant
3922 && fits_in_imm7 (i
.op
[0].imms
->X_add_number
)
3923 && ((i
.tm
.base_opcode
== 0xa8
3924 && i
.tm
.extension_opcode
== None
)
3925 || (i
.tm
.base_opcode
== 0xf6
3926 && i
.tm
.extension_opcode
== 0x0)))
3929 test $imm7, %r64/%r32/%r16 -> test $imm7, %r8
3931 unsigned int base_regnum
= i
.op
[1].regs
->reg_num
;
3932 if (flag_code
== CODE_64BIT
|| base_regnum
< 4)
3934 i
.types
[1].bitfield
.byte
= 1;
3935 /* Ignore the suffix. */
3937 if (base_regnum
>= 4
3938 && !(i
.op
[1].regs
->reg_flags
& RegRex
))
3940 /* Handle SP, BP, SI and DI registers. */
3941 if (i
.types
[1].bitfield
.word
)
3943 else if (i
.types
[1].bitfield
.dword
)
3951 else if (flag_code
== CODE_64BIT
3952 && ((i
.types
[1].bitfield
.qword
3953 && i
.reg_operands
== 1
3954 && i
.imm_operands
== 1
3955 && i
.op
[0].imms
->X_op
== O_constant
3956 && ((i
.tm
.base_opcode
== 0xb8
3957 && i
.tm
.extension_opcode
== None
3958 && fits_in_unsigned_long (i
.op
[0].imms
->X_add_number
))
3959 || (fits_in_imm31 (i
.op
[0].imms
->X_add_number
)
3960 && (((i
.tm
.base_opcode
== 0x24
3961 || i
.tm
.base_opcode
== 0xa8)
3962 && i
.tm
.extension_opcode
== None
)
3963 || (i
.tm
.base_opcode
== 0x80
3964 && i
.tm
.extension_opcode
== 0x4)
3965 || ((i
.tm
.base_opcode
== 0xf6
3966 || (i
.tm
.base_opcode
| 1) == 0xc7)
3967 && i
.tm
.extension_opcode
== 0x0)))
3968 || (fits_in_imm7 (i
.op
[0].imms
->X_add_number
)
3969 && i
.tm
.base_opcode
== 0x83
3970 && i
.tm
.extension_opcode
== 0x4)))
3971 || (i
.types
[0].bitfield
.qword
3972 && ((i
.reg_operands
== 2
3973 && i
.op
[0].regs
== i
.op
[1].regs
3974 && ((i
.tm
.base_opcode
== 0x30
3975 || i
.tm
.base_opcode
== 0x28)
3976 && i
.tm
.extension_opcode
== None
))
3977 || (i
.reg_operands
== 1
3979 && i
.tm
.base_opcode
== 0x30
3980 && i
.tm
.extension_opcode
== None
)))))
3983 andq $imm31, %r64 -> andl $imm31, %r32
3984 andq $imm7, %r64 -> andl $imm7, %r32
3985 testq $imm31, %r64 -> testl $imm31, %r32
3986 xorq %r64, %r64 -> xorl %r32, %r32
3987 subq %r64, %r64 -> subl %r32, %r32
3988 movq $imm31, %r64 -> movl $imm31, %r32
3989 movq $imm32, %r64 -> movl $imm32, %r32
3991 i
.tm
.opcode_modifier
.norex64
= 1;
3992 if (i
.tm
.base_opcode
== 0xb8 || (i
.tm
.base_opcode
| 1) == 0xc7)
3995 movq $imm31, %r64 -> movl $imm31, %r32
3996 movq $imm32, %r64 -> movl $imm32, %r32
3998 i
.tm
.operand_types
[0].bitfield
.imm32
= 1;
3999 i
.tm
.operand_types
[0].bitfield
.imm32s
= 0;
4000 i
.tm
.operand_types
[0].bitfield
.imm64
= 0;
4001 i
.types
[0].bitfield
.imm32
= 1;
4002 i
.types
[0].bitfield
.imm32s
= 0;
4003 i
.types
[0].bitfield
.imm64
= 0;
4004 i
.types
[1].bitfield
.dword
= 1;
4005 i
.types
[1].bitfield
.qword
= 0;
4006 if ((i
.tm
.base_opcode
| 1) == 0xc7)
4009 movq $imm31, %r64 -> movl $imm31, %r32
4011 i
.tm
.base_opcode
= 0xb8;
4012 i
.tm
.extension_opcode
= None
;
4013 i
.tm
.opcode_modifier
.w
= 0;
4014 i
.tm
.opcode_modifier
.shortform
= 1;
4015 i
.tm
.opcode_modifier
.modrm
= 0;
4019 else if (optimize
> 1
4020 && !optimize_for_space
4021 && i
.reg_operands
== 2
4022 && i
.op
[0].regs
== i
.op
[1].regs
4023 && ((i
.tm
.base_opcode
& ~(Opcode_D
| 1)) == 0x8
4024 || (i
.tm
.base_opcode
& ~(Opcode_D
| 1)) == 0x20)
4025 && (flag_code
!= CODE_64BIT
|| !i
.types
[0].bitfield
.dword
))
4028 andb %rN, %rN -> testb %rN, %rN
4029 andw %rN, %rN -> testw %rN, %rN
4030 andq %rN, %rN -> testq %rN, %rN
4031 orb %rN, %rN -> testb %rN, %rN
4032 orw %rN, %rN -> testw %rN, %rN
4033 orq %rN, %rN -> testq %rN, %rN
4035 and outside of 64-bit mode
4037 andl %rN, %rN -> testl %rN, %rN
4038 orl %rN, %rN -> testl %rN, %rN
4040 i
.tm
.base_opcode
= 0x84 | (i
.tm
.base_opcode
& 1);
4042 else if (i
.reg_operands
== 3
4043 && i
.op
[0].regs
== i
.op
[1].regs
4044 && !i
.types
[2].bitfield
.xmmword
4045 && (i
.tm
.opcode_modifier
.vex
4046 || ((!i
.mask
|| i
.mask
->zeroing
)
4048 && is_evex_encoding (&i
.tm
)
4049 && (i
.vec_encoding
!= vex_encoding_evex
4050 || cpu_arch_isa_flags
.bitfield
.cpuavx512vl
4051 || i
.tm
.cpu_flags
.bitfield
.cpuavx512vl
4052 || (i
.tm
.operand_types
[2].bitfield
.zmmword
4053 && i
.types
[2].bitfield
.ymmword
))))
4054 && ((i
.tm
.base_opcode
== 0x55
4055 || i
.tm
.base_opcode
== 0x6655
4056 || i
.tm
.base_opcode
== 0x66df
4057 || i
.tm
.base_opcode
== 0x57
4058 || i
.tm
.base_opcode
== 0x6657
4059 || i
.tm
.base_opcode
== 0x66ef
4060 || i
.tm
.base_opcode
== 0x66f8
4061 || i
.tm
.base_opcode
== 0x66f9
4062 || i
.tm
.base_opcode
== 0x66fa
4063 || i
.tm
.base_opcode
== 0x66fb
4064 || i
.tm
.base_opcode
== 0x42
4065 || i
.tm
.base_opcode
== 0x6642
4066 || i
.tm
.base_opcode
== 0x47
4067 || i
.tm
.base_opcode
== 0x6647)
4068 && i
.tm
.extension_opcode
== None
))
4071 VOP, one of vandnps, vandnpd, vxorps, vxorpd, vpsubb, vpsubd,
4073 EVEX VOP %zmmM, %zmmM, %zmmN
4074 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
4075 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4076 EVEX VOP %ymmM, %ymmM, %ymmN
4077 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
4078 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4079 VEX VOP %ymmM, %ymmM, %ymmN
4080 -> VEX VOP %xmmM, %xmmM, %xmmN
4081 VOP, one of vpandn and vpxor:
4082 VEX VOP %ymmM, %ymmM, %ymmN
4083 -> VEX VOP %xmmM, %xmmM, %xmmN
4084 VOP, one of vpandnd and vpandnq:
4085 EVEX VOP %zmmM, %zmmM, %zmmN
4086 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
4087 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4088 EVEX VOP %ymmM, %ymmM, %ymmN
4089 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
4090 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4091 VOP, one of vpxord and vpxorq:
4092 EVEX VOP %zmmM, %zmmM, %zmmN
4093 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
4094 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4095 EVEX VOP %ymmM, %ymmM, %ymmN
4096 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
4097 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4098 VOP, one of kxord and kxorq:
4099 VEX VOP %kM, %kM, %kN
4100 -> VEX kxorw %kM, %kM, %kN
4101 VOP, one of kandnd and kandnq:
4102 VEX VOP %kM, %kM, %kN
4103 -> VEX kandnw %kM, %kM, %kN
4105 if (is_evex_encoding (&i
.tm
))
4107 if (i
.vec_encoding
!= vex_encoding_evex
)
4109 i
.tm
.opcode_modifier
.vex
= VEX128
;
4110 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4111 i
.tm
.opcode_modifier
.evex
= 0;
4113 else if (optimize
> 1)
4114 i
.tm
.opcode_modifier
.evex
= EVEX128
;
4118 else if (i
.tm
.operand_types
[0].bitfield
.class == RegMask
)
4120 i
.tm
.base_opcode
&= 0xff;
4121 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4124 i
.tm
.opcode_modifier
.vex
= VEX128
;
4126 if (i
.tm
.opcode_modifier
.vex
)
4127 for (j
= 0; j
< 3; j
++)
4129 i
.types
[j
].bitfield
.xmmword
= 1;
4130 i
.types
[j
].bitfield
.ymmword
= 0;
4133 else if (i
.vec_encoding
!= vex_encoding_evex
4134 && !i
.types
[0].bitfield
.zmmword
4135 && !i
.types
[1].bitfield
.zmmword
4138 && is_evex_encoding (&i
.tm
)
4139 && ((i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0x666f
4140 || (i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0xf36f
4141 || (i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0xf26f
4142 || (i
.tm
.base_opcode
& ~4) == 0x66db
4143 || (i
.tm
.base_opcode
& ~4) == 0x66eb)
4144 && i
.tm
.extension_opcode
== None
)
4147 VOP, one of vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16,
4148 vmovdqu32 and vmovdqu64:
4149 EVEX VOP %xmmM, %xmmN
4150 -> VEX vmovdqa|vmovdqu %xmmM, %xmmN (M and N < 16)
4151 EVEX VOP %ymmM, %ymmN
4152 -> VEX vmovdqa|vmovdqu %ymmM, %ymmN (M and N < 16)
4154 -> VEX vmovdqa|vmovdqu %xmmM, mem (M < 16)
4156 -> VEX vmovdqa|vmovdqu %ymmM, mem (M < 16)
4158 -> VEX mvmovdqa|vmovdquem, %xmmN (N < 16)
4160 -> VEX vmovdqa|vmovdqu mem, %ymmN (N < 16)
4161 VOP, one of vpand, vpandn, vpor, vpxor:
4162 EVEX VOP{d,q} %xmmL, %xmmM, %xmmN
4163 -> VEX VOP %xmmL, %xmmM, %xmmN (L, M, and N < 16)
4164 EVEX VOP{d,q} %ymmL, %ymmM, %ymmN
4165 -> VEX VOP %ymmL, %ymmM, %ymmN (L, M, and N < 16)
4166 EVEX VOP{d,q} mem, %xmmM, %xmmN
4167 -> VEX VOP mem, %xmmM, %xmmN (M and N < 16)
4168 EVEX VOP{d,q} mem, %ymmM, %ymmN
4169 -> VEX VOP mem, %ymmM, %ymmN (M and N < 16)
4171 for (j
= 0; j
< i
.operands
; j
++)
4172 if (operand_type_check (i
.types
[j
], disp
)
4173 && i
.op
[j
].disps
->X_op
== O_constant
)
4175 /* Since the VEX prefix has 2 or 3 bytes, the EVEX prefix
4176 has 4 bytes, EVEX Disp8 has 1 byte and VEX Disp32 has 4
4177 bytes, we choose EVEX Disp8 over VEX Disp32. */
4178 int evex_disp8
, vex_disp8
;
4179 unsigned int memshift
= i
.memshift
;
4180 offsetT n
= i
.op
[j
].disps
->X_add_number
;
4182 evex_disp8
= fits_in_disp8 (n
);
4184 vex_disp8
= fits_in_disp8 (n
);
4185 if (evex_disp8
!= vex_disp8
)
4187 i
.memshift
= memshift
;
4191 i
.types
[j
].bitfield
.disp8
= vex_disp8
;
4194 if ((i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0xf26f)
4195 i
.tm
.base_opcode
^= 0xf36f ^ 0xf26f;
4196 i
.tm
.opcode_modifier
.vex
4197 = i
.types
[0].bitfield
.ymmword
? VEX256
: VEX128
;
4198 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4199 /* VPAND, VPOR, and VPXOR are commutative. */
4200 if (i
.reg_operands
== 3 && i
.tm
.base_opcode
!= 0x66df)
4201 i
.tm
.opcode_modifier
.commutative
= 1;
4202 i
.tm
.opcode_modifier
.evex
= 0;
4203 i
.tm
.opcode_modifier
.masking
= 0;
4204 i
.tm
.opcode_modifier
.broadcast
= 0;
4205 i
.tm
.opcode_modifier
.disp8memshift
= 0;
4208 i
.types
[j
].bitfield
.disp8
4209 = fits_in_disp8 (i
.op
[j
].disps
->X_add_number
);
4213 /* This is the guts of the machine-dependent assembler. LINE points to a
4214 machine dependent instruction. This function is supposed to emit
4215 the frags/bytes it assembles to. */
4218 md_assemble (char *line
)
4221 char mnemonic
[MAX_MNEM_SIZE
], mnem_suffix
;
4222 const insn_template
*t
;
4224 /* Initialize globals. */
4225 memset (&i
, '\0', sizeof (i
));
4226 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4227 i
.reloc
[j
] = NO_RELOC
;
4228 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
4229 memset (im_expressions
, '\0', sizeof (im_expressions
));
4230 save_stack_p
= save_stack
;
4232 /* First parse an instruction mnemonic & call i386_operand for the operands.
4233 We assume that the scrubber has arranged it so that line[0] is the valid
4234 start of a (possibly prefixed) mnemonic. */
4236 line
= parse_insn (line
, mnemonic
);
4239 mnem_suffix
= i
.suffix
;
4241 line
= parse_operands (line
, mnemonic
);
4243 xfree (i
.memop1_string
);
4244 i
.memop1_string
= NULL
;
4248 /* Now we've parsed the mnemonic into a set of templates, and have the
4249 operands at hand. */
4251 /* All intel opcodes have reversed operands except for "bound" and
4252 "enter". We also don't reverse intersegment "jmp" and "call"
4253 instructions with 2 immediate operands so that the immediate segment
4254 precedes the offset, as it does when in AT&T mode. */
4257 && (strcmp (mnemonic
, "bound") != 0)
4258 && (strcmp (mnemonic
, "invlpga") != 0)
4259 && !(operand_type_check (i
.types
[0], imm
)
4260 && operand_type_check (i
.types
[1], imm
)))
4263 /* The order of the immediates should be reversed
4264 for 2 immediates extrq and insertq instructions */
4265 if (i
.imm_operands
== 2
4266 && (strcmp (mnemonic
, "extrq") == 0
4267 || strcmp (mnemonic
, "insertq") == 0))
4268 swap_2_operands (0, 1);
4273 /* Don't optimize displacement for movabs since it only takes 64bit
4276 && i
.disp_encoding
!= disp_encoding_32bit
4277 && (flag_code
!= CODE_64BIT
4278 || strcmp (mnemonic
, "movabs") != 0))
4281 /* Next, we find a template that matches the given insn,
4282 making sure the overlap of the given operands types is consistent
4283 with the template operand types. */
4285 if (!(t
= match_template (mnem_suffix
)))
4288 if (sse_check
!= check_none
4289 && !i
.tm
.opcode_modifier
.noavx
4290 && !i
.tm
.cpu_flags
.bitfield
.cpuavx
4291 && (i
.tm
.cpu_flags
.bitfield
.cpusse
4292 || i
.tm
.cpu_flags
.bitfield
.cpusse2
4293 || i
.tm
.cpu_flags
.bitfield
.cpusse3
4294 || i
.tm
.cpu_flags
.bitfield
.cpussse3
4295 || i
.tm
.cpu_flags
.bitfield
.cpusse4_1
4296 || i
.tm
.cpu_flags
.bitfield
.cpusse4_2
4297 || i
.tm
.cpu_flags
.bitfield
.cpupclmul
4298 || i
.tm
.cpu_flags
.bitfield
.cpuaes
4299 || i
.tm
.cpu_flags
.bitfield
.cpugfni
))
4301 (sse_check
== check_warning
4303 : as_bad
) (_("SSE instruction `%s' is used"), i
.tm
.name
);
4306 /* Zap movzx and movsx suffix. The suffix has been set from
4307 "word ptr" or "byte ptr" on the source operand in Intel syntax
4308 or extracted from mnemonic in AT&T syntax. But we'll use
4309 the destination register to choose the suffix for encoding. */
4310 if ((i
.tm
.base_opcode
& ~9) == 0x0fb6)
4312 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
4313 there is no suffix, the default will be byte extension. */
4314 if (i
.reg_operands
!= 2
4317 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
4322 if (i
.tm
.opcode_modifier
.fwait
)
4323 if (!add_prefix (FWAIT_OPCODE
))
4326 /* Check if REP prefix is OK. */
4327 if (i
.rep_prefix
&& !i
.tm
.opcode_modifier
.repprefixok
)
4329 as_bad (_("invalid instruction `%s' after `%s'"),
4330 i
.tm
.name
, i
.rep_prefix
);
4334 /* Check for lock without a lockable instruction. Destination operand
4335 must be memory unless it is xchg (0x86). */
4336 if (i
.prefix
[LOCK_PREFIX
]
4337 && (!i
.tm
.opcode_modifier
.islockable
4338 || i
.mem_operands
== 0
4339 || (i
.tm
.base_opcode
!= 0x86
4340 && !(i
.flags
[i
.operands
- 1] & Operand_Mem
))))
4342 as_bad (_("expecting lockable instruction after `lock'"));
4346 /* Check for data size prefix on VEX/XOP/EVEX encoded insns. */
4347 if (i
.prefix
[DATA_PREFIX
] && is_any_vex_encoding (&i
.tm
))
4349 as_bad (_("data size prefix invalid with `%s'"), i
.tm
.name
);
4353 /* Check if HLE prefix is OK. */
4354 if (i
.hle_prefix
&& !check_hle ())
4357 /* Check BND prefix. */
4358 if (i
.bnd_prefix
&& !i
.tm
.opcode_modifier
.bndprefixok
)
4359 as_bad (_("expecting valid branch instruction after `bnd'"));
4361 /* Check NOTRACK prefix. */
4362 if (i
.notrack_prefix
&& !i
.tm
.opcode_modifier
.notrackprefixok
)
4363 as_bad (_("expecting indirect branch instruction after `notrack'"));
4365 if (i
.tm
.cpu_flags
.bitfield
.cpumpx
)
4367 if (flag_code
== CODE_64BIT
&& i
.prefix
[ADDR_PREFIX
])
4368 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
4369 else if (flag_code
!= CODE_16BIT
4370 ? i
.prefix
[ADDR_PREFIX
]
4371 : i
.mem_operands
&& !i
.prefix
[ADDR_PREFIX
])
4372 as_bad (_("16-bit address isn't allowed in MPX instructions"));
4375 /* Insert BND prefix. */
4376 if (add_bnd_prefix
&& i
.tm
.opcode_modifier
.bndprefixok
)
4378 if (!i
.prefix
[BND_PREFIX
])
4379 add_prefix (BND_PREFIX_OPCODE
);
4380 else if (i
.prefix
[BND_PREFIX
] != BND_PREFIX_OPCODE
)
4382 as_warn (_("replacing `rep'/`repe' prefix by `bnd'"));
4383 i
.prefix
[BND_PREFIX
] = BND_PREFIX_OPCODE
;
4387 /* Check string instruction segment overrides. */
4388 if (i
.tm
.opcode_modifier
.isstring
>= IS_STRING_ES_OP0
)
4390 gas_assert (i
.mem_operands
);
4391 if (!check_string ())
4393 i
.disp_operands
= 0;
4396 if (optimize
&& !i
.no_optimize
&& i
.tm
.opcode_modifier
.optimize
)
4397 optimize_encoding ();
4399 if (!process_suffix ())
4402 /* Update operand types. */
4403 for (j
= 0; j
< i
.operands
; j
++)
4404 i
.types
[j
] = operand_type_and (i
.types
[j
], i
.tm
.operand_types
[j
]);
4406 /* Make still unresolved immediate matches conform to size of immediate
4407 given in i.suffix. */
4408 if (!finalize_imm ())
4411 if (i
.types
[0].bitfield
.imm1
)
4412 i
.imm_operands
= 0; /* kludge for shift insns. */
4414 /* We only need to check those implicit registers for instructions
4415 with 3 operands or less. */
4416 if (i
.operands
<= 3)
4417 for (j
= 0; j
< i
.operands
; j
++)
4418 if (i
.types
[j
].bitfield
.instance
!= InstanceNone
4419 && !i
.types
[j
].bitfield
.xmmword
)
4422 /* ImmExt should be processed after SSE2AVX. */
4423 if (!i
.tm
.opcode_modifier
.sse2avx
4424 && i
.tm
.opcode_modifier
.immext
)
4427 /* For insns with operands there are more diddles to do to the opcode. */
4430 if (!process_operands ())
4433 else if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
4435 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
4436 as_warn (_("translating to `%sp'"), i
.tm
.name
);
4439 if (is_any_vex_encoding (&i
.tm
))
4441 if (!cpu_arch_flags
.bitfield
.cpui286
)
4443 as_bad (_("instruction `%s' isn't supported outside of protected mode."),
4448 if (i
.tm
.opcode_modifier
.vex
)
4449 build_vex_prefix (t
);
4451 build_evex_prefix ();
4454 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
4455 instructions may define INT_OPCODE as well, so avoid this corner
4456 case for those instructions that use MODRM. */
4457 if (i
.tm
.base_opcode
== INT_OPCODE
4458 && !i
.tm
.opcode_modifier
.modrm
4459 && i
.op
[0].imms
->X_add_number
== 3)
4461 i
.tm
.base_opcode
= INT3_OPCODE
;
4465 if ((i
.tm
.opcode_modifier
.jump
4466 || i
.tm
.opcode_modifier
.jumpbyte
4467 || i
.tm
.opcode_modifier
.jumpdword
)
4468 && i
.op
[0].disps
->X_op
== O_constant
)
4470 /* Convert "jmp constant" (and "call constant") to a jump (call) to
4471 the absolute address given by the constant. Since ix86 jumps and
4472 calls are pc relative, we need to generate a reloc. */
4473 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
4474 i
.op
[0].disps
->X_op
= O_symbol
;
4477 if (i
.tm
.opcode_modifier
.rex64
)
4480 /* For 8 bit registers we need an empty rex prefix. Also if the
4481 instruction already has a prefix, we need to convert old
4482 registers to new ones. */
4484 if ((i
.types
[0].bitfield
.class == Reg
&& i
.types
[0].bitfield
.byte
4485 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
4486 || (i
.types
[1].bitfield
.class == Reg
&& i
.types
[1].bitfield
.byte
4487 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
4488 || (((i
.types
[0].bitfield
.class == Reg
&& i
.types
[0].bitfield
.byte
)
4489 || (i
.types
[1].bitfield
.class == Reg
&& i
.types
[1].bitfield
.byte
))
4494 i
.rex
|= REX_OPCODE
;
4495 for (x
= 0; x
< 2; x
++)
4497 /* Look for 8 bit operand that uses old registers. */
4498 if (i
.types
[x
].bitfield
.class == Reg
&& i
.types
[x
].bitfield
.byte
4499 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
4501 /* In case it is "hi" register, give up. */
4502 if (i
.op
[x
].regs
->reg_num
> 3)
4503 as_bad (_("can't encode register '%s%s' in an "
4504 "instruction requiring REX prefix."),
4505 register_prefix
, i
.op
[x
].regs
->reg_name
);
4507 /* Otherwise it is equivalent to the extended register.
4508 Since the encoding doesn't change this is merely
4509 cosmetic cleanup for debug output. */
4511 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
4516 if (i
.rex
== 0 && i
.rex_encoding
)
4518 /* Check if we can add a REX_OPCODE byte. Look for 8 bit operand
4519 that uses legacy register. If it is "hi" register, don't add
4520 the REX_OPCODE byte. */
4522 for (x
= 0; x
< 2; x
++)
4523 if (i
.types
[x
].bitfield
.class == Reg
4524 && i
.types
[x
].bitfield
.byte
4525 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0
4526 && i
.op
[x
].regs
->reg_num
> 3)
4528 i
.rex_encoding
= FALSE
;
4537 add_prefix (REX_OPCODE
| i
.rex
);
4539 /* We are ready to output the insn. */
4544 parse_insn (char *line
, char *mnemonic
)
4547 char *token_start
= l
;
4550 const insn_template
*t
;
4556 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
4561 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
4563 as_bad (_("no such instruction: `%s'"), token_start
);
4568 if (!is_space_char (*l
)
4569 && *l
!= END_OF_INSN
4571 || (*l
!= PREFIX_SEPARATOR
4574 as_bad (_("invalid character %s in mnemonic"),
4575 output_invalid (*l
));
4578 if (token_start
== l
)
4580 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
4581 as_bad (_("expecting prefix; got nothing"));
4583 as_bad (_("expecting mnemonic; got nothing"));
4587 /* Look up instruction (or prefix) via hash table. */
4588 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
4590 if (*l
!= END_OF_INSN
4591 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
4592 && current_templates
4593 && current_templates
->start
->opcode_modifier
.isprefix
)
4595 if (!cpu_flags_check_cpu64 (current_templates
->start
->cpu_flags
))
4597 as_bad ((flag_code
!= CODE_64BIT
4598 ? _("`%s' is only supported in 64-bit mode")
4599 : _("`%s' is not supported in 64-bit mode")),
4600 current_templates
->start
->name
);
4603 /* If we are in 16-bit mode, do not allow addr16 or data16.
4604 Similarly, in 32-bit mode, do not allow addr32 or data32. */
4605 if ((current_templates
->start
->opcode_modifier
.size
== SIZE16
4606 || current_templates
->start
->opcode_modifier
.size
== SIZE32
)
4607 && flag_code
!= CODE_64BIT
4608 && ((current_templates
->start
->opcode_modifier
.size
== SIZE32
)
4609 ^ (flag_code
== CODE_16BIT
)))
4611 as_bad (_("redundant %s prefix"),
4612 current_templates
->start
->name
);
4615 if (current_templates
->start
->opcode_length
== 0)
4617 /* Handle pseudo prefixes. */
4618 switch (current_templates
->start
->base_opcode
)
4622 i
.disp_encoding
= disp_encoding_8bit
;
4626 i
.disp_encoding
= disp_encoding_32bit
;
4630 i
.dir_encoding
= dir_encoding_load
;
4634 i
.dir_encoding
= dir_encoding_store
;
4638 i
.vec_encoding
= vex_encoding_vex2
;
4642 i
.vec_encoding
= vex_encoding_vex3
;
4646 i
.vec_encoding
= vex_encoding_evex
;
4650 i
.rex_encoding
= TRUE
;
4654 i
.no_optimize
= TRUE
;
4662 /* Add prefix, checking for repeated prefixes. */
4663 switch (add_prefix (current_templates
->start
->base_opcode
))
4668 if (current_templates
->start
->cpu_flags
.bitfield
.cpuibt
)
4669 i
.notrack_prefix
= current_templates
->start
->name
;
4672 if (current_templates
->start
->cpu_flags
.bitfield
.cpuhle
)
4673 i
.hle_prefix
= current_templates
->start
->name
;
4674 else if (current_templates
->start
->cpu_flags
.bitfield
.cpumpx
)
4675 i
.bnd_prefix
= current_templates
->start
->name
;
4677 i
.rep_prefix
= current_templates
->start
->name
;
4683 /* Skip past PREFIX_SEPARATOR and reset token_start. */
4690 if (!current_templates
)
4692 /* Deprecated functionality (new code should use pseudo-prefixes instead):
4693 Check if we should swap operand or force 32bit displacement in
4695 if (mnem_p
- 2 == dot_p
&& dot_p
[1] == 's')
4696 i
.dir_encoding
= dir_encoding_swap
;
4697 else if (mnem_p
- 3 == dot_p
4700 i
.disp_encoding
= disp_encoding_8bit
;
4701 else if (mnem_p
- 4 == dot_p
4705 i
.disp_encoding
= disp_encoding_32bit
;
4710 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
4713 if (!current_templates
)
4716 if (mnem_p
> mnemonic
)
4718 /* See if we can get a match by trimming off a suffix. */
4721 case WORD_MNEM_SUFFIX
:
4722 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
4723 i
.suffix
= SHORT_MNEM_SUFFIX
;
4726 case BYTE_MNEM_SUFFIX
:
4727 case QWORD_MNEM_SUFFIX
:
4728 i
.suffix
= mnem_p
[-1];
4730 current_templates
= (const templates
*) hash_find (op_hash
,
4733 case SHORT_MNEM_SUFFIX
:
4734 case LONG_MNEM_SUFFIX
:
4737 i
.suffix
= mnem_p
[-1];
4739 current_templates
= (const templates
*) hash_find (op_hash
,
4748 if (intel_float_operand (mnemonic
) == 1)
4749 i
.suffix
= SHORT_MNEM_SUFFIX
;
4751 i
.suffix
= LONG_MNEM_SUFFIX
;
4753 current_templates
= (const templates
*) hash_find (op_hash
,
4760 if (!current_templates
)
4762 as_bad (_("no such instruction: `%s'"), token_start
);
4767 if (current_templates
->start
->opcode_modifier
.jump
4768 || current_templates
->start
->opcode_modifier
.jumpbyte
)
4770 /* Check for a branch hint. We allow ",pt" and ",pn" for
4771 predict taken and predict not taken respectively.
4772 I'm not sure that branch hints actually do anything on loop
4773 and jcxz insns (JumpByte) for current Pentium4 chips. They
4774 may work in the future and it doesn't hurt to accept them
4776 if (l
[0] == ',' && l
[1] == 'p')
4780 if (!add_prefix (DS_PREFIX_OPCODE
))
4784 else if (l
[2] == 'n')
4786 if (!add_prefix (CS_PREFIX_OPCODE
))
4792 /* Any other comma loses. */
4795 as_bad (_("invalid character %s in mnemonic"),
4796 output_invalid (*l
));
4800 /* Check if instruction is supported on specified architecture. */
4802 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
4804 supported
|= cpu_flags_match (t
);
4805 if (supported
== CPU_FLAGS_PERFECT_MATCH
)
4807 if (!cpu_arch_flags
.bitfield
.cpui386
&& (flag_code
!= CODE_16BIT
))
4808 as_warn (_("use .code16 to ensure correct addressing mode"));
4814 if (!(supported
& CPU_FLAGS_64BIT_MATCH
))
4815 as_bad (flag_code
== CODE_64BIT
4816 ? _("`%s' is not supported in 64-bit mode")
4817 : _("`%s' is only supported in 64-bit mode"),
4818 current_templates
->start
->name
);
4820 as_bad (_("`%s' is not supported on `%s%s'"),
4821 current_templates
->start
->name
,
4822 cpu_arch_name
? cpu_arch_name
: default_arch
,
4823 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
4829 parse_operands (char *l
, const char *mnemonic
)
4833 /* 1 if operand is pending after ','. */
4834 unsigned int expecting_operand
= 0;
4836 /* Non-zero if operand parens not balanced. */
4837 unsigned int paren_not_balanced
;
4839 while (*l
!= END_OF_INSN
)
4841 /* Skip optional white space before operand. */
4842 if (is_space_char (*l
))
4844 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
&& *l
!= '"')
4846 as_bad (_("invalid character %s before operand %d"),
4847 output_invalid (*l
),
4851 token_start
= l
; /* After white space. */
4852 paren_not_balanced
= 0;
4853 while (paren_not_balanced
|| *l
!= ',')
4855 if (*l
== END_OF_INSN
)
4857 if (paren_not_balanced
)
4860 as_bad (_("unbalanced parenthesis in operand %d."),
4863 as_bad (_("unbalanced brackets in operand %d."),
4868 break; /* we are done */
4870 else if (!is_operand_char (*l
) && !is_space_char (*l
) && *l
!= '"')
4872 as_bad (_("invalid character %s in operand %d"),
4873 output_invalid (*l
),
4880 ++paren_not_balanced
;
4882 --paren_not_balanced
;
4887 ++paren_not_balanced
;
4889 --paren_not_balanced
;
4893 if (l
!= token_start
)
4894 { /* Yes, we've read in another operand. */
4895 unsigned int operand_ok
;
4896 this_operand
= i
.operands
++;
4897 if (i
.operands
> MAX_OPERANDS
)
4899 as_bad (_("spurious operands; (%d operands/instruction max)"),
4903 i
.types
[this_operand
].bitfield
.unspecified
= 1;
4904 /* Now parse operand adding info to 'i' as we go along. */
4905 END_STRING_AND_SAVE (l
);
4907 if (i
.mem_operands
> 1)
4909 as_bad (_("too many memory references for `%s'"),
4916 i386_intel_operand (token_start
,
4917 intel_float_operand (mnemonic
));
4919 operand_ok
= i386_att_operand (token_start
);
4921 RESTORE_END_STRING (l
);
4927 if (expecting_operand
)
4929 expecting_operand_after_comma
:
4930 as_bad (_("expecting operand after ','; got nothing"));
4935 as_bad (_("expecting operand before ','; got nothing"));
4940 /* Now *l must be either ',' or END_OF_INSN. */
4943 if (*++l
== END_OF_INSN
)
4945 /* Just skip it, if it's \n complain. */
4946 goto expecting_operand_after_comma
;
4948 expecting_operand
= 1;
4955 swap_2_operands (int xchg1
, int xchg2
)
4957 union i386_op temp_op
;
4958 i386_operand_type temp_type
;
4959 unsigned int temp_flags
;
4960 enum bfd_reloc_code_real temp_reloc
;
4962 temp_type
= i
.types
[xchg2
];
4963 i
.types
[xchg2
] = i
.types
[xchg1
];
4964 i
.types
[xchg1
] = temp_type
;
4966 temp_flags
= i
.flags
[xchg2
];
4967 i
.flags
[xchg2
] = i
.flags
[xchg1
];
4968 i
.flags
[xchg1
] = temp_flags
;
4970 temp_op
= i
.op
[xchg2
];
4971 i
.op
[xchg2
] = i
.op
[xchg1
];
4972 i
.op
[xchg1
] = temp_op
;
4974 temp_reloc
= i
.reloc
[xchg2
];
4975 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
4976 i
.reloc
[xchg1
] = temp_reloc
;
4980 if (i
.mask
->operand
== xchg1
)
4981 i
.mask
->operand
= xchg2
;
4982 else if (i
.mask
->operand
== xchg2
)
4983 i
.mask
->operand
= xchg1
;
4987 if (i
.broadcast
->operand
== xchg1
)
4988 i
.broadcast
->operand
= xchg2
;
4989 else if (i
.broadcast
->operand
== xchg2
)
4990 i
.broadcast
->operand
= xchg1
;
4994 if (i
.rounding
->operand
== xchg1
)
4995 i
.rounding
->operand
= xchg2
;
4996 else if (i
.rounding
->operand
== xchg2
)
4997 i
.rounding
->operand
= xchg1
;
5002 swap_operands (void)
5008 swap_2_operands (1, i
.operands
- 2);
5012 swap_2_operands (0, i
.operands
- 1);
5018 if (i
.mem_operands
== 2)
5020 const seg_entry
*temp_seg
;
5021 temp_seg
= i
.seg
[0];
5022 i
.seg
[0] = i
.seg
[1];
5023 i
.seg
[1] = temp_seg
;
5027 /* Try to ensure constant immediates are represented in the smallest
5032 char guess_suffix
= 0;
5036 guess_suffix
= i
.suffix
;
5037 else if (i
.reg_operands
)
5039 /* Figure out a suffix from the last register operand specified.
5040 We can't do this properly yet, i.e. excluding special register
5041 instances, but the following works for instructions with
5042 immediates. In any case, we can't set i.suffix yet. */
5043 for (op
= i
.operands
; --op
>= 0;)
5044 if (i
.types
[op
].bitfield
.class != Reg
)
5046 else if (i
.types
[op
].bitfield
.byte
)
5048 guess_suffix
= BYTE_MNEM_SUFFIX
;
5051 else if (i
.types
[op
].bitfield
.word
)
5053 guess_suffix
= WORD_MNEM_SUFFIX
;
5056 else if (i
.types
[op
].bitfield
.dword
)
5058 guess_suffix
= LONG_MNEM_SUFFIX
;
5061 else if (i
.types
[op
].bitfield
.qword
)
5063 guess_suffix
= QWORD_MNEM_SUFFIX
;
5067 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
5068 guess_suffix
= WORD_MNEM_SUFFIX
;
5070 for (op
= i
.operands
; --op
>= 0;)
5071 if (operand_type_check (i
.types
[op
], imm
))
5073 switch (i
.op
[op
].imms
->X_op
)
5076 /* If a suffix is given, this operand may be shortened. */
5077 switch (guess_suffix
)
5079 case LONG_MNEM_SUFFIX
:
5080 i
.types
[op
].bitfield
.imm32
= 1;
5081 i
.types
[op
].bitfield
.imm64
= 1;
5083 case WORD_MNEM_SUFFIX
:
5084 i
.types
[op
].bitfield
.imm16
= 1;
5085 i
.types
[op
].bitfield
.imm32
= 1;
5086 i
.types
[op
].bitfield
.imm32s
= 1;
5087 i
.types
[op
].bitfield
.imm64
= 1;
5089 case BYTE_MNEM_SUFFIX
:
5090 i
.types
[op
].bitfield
.imm8
= 1;
5091 i
.types
[op
].bitfield
.imm8s
= 1;
5092 i
.types
[op
].bitfield
.imm16
= 1;
5093 i
.types
[op
].bitfield
.imm32
= 1;
5094 i
.types
[op
].bitfield
.imm32s
= 1;
5095 i
.types
[op
].bitfield
.imm64
= 1;
5099 /* If this operand is at most 16 bits, convert it
5100 to a signed 16 bit number before trying to see
5101 whether it will fit in an even smaller size.
5102 This allows a 16-bit operand such as $0xffe0 to
5103 be recognised as within Imm8S range. */
5104 if ((i
.types
[op
].bitfield
.imm16
)
5105 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
5107 i
.op
[op
].imms
->X_add_number
=
5108 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
5111 /* Store 32-bit immediate in 64-bit for 64-bit BFD. */
5112 if ((i
.types
[op
].bitfield
.imm32
)
5113 && ((i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1))
5116 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
5117 ^ ((offsetT
) 1 << 31))
5118 - ((offsetT
) 1 << 31));
5122 = operand_type_or (i
.types
[op
],
5123 smallest_imm_type (i
.op
[op
].imms
->X_add_number
));
5125 /* We must avoid matching of Imm32 templates when 64bit
5126 only immediate is available. */
5127 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
5128 i
.types
[op
].bitfield
.imm32
= 0;
5135 /* Symbols and expressions. */
5137 /* Convert symbolic operand to proper sizes for matching, but don't
5138 prevent matching a set of insns that only supports sizes other
5139 than those matching the insn suffix. */
5141 i386_operand_type mask
, allowed
;
5142 const insn_template
*t
;
5144 operand_type_set (&mask
, 0);
5145 operand_type_set (&allowed
, 0);
5147 for (t
= current_templates
->start
;
5148 t
< current_templates
->end
;
5151 allowed
= operand_type_or (allowed
, t
->operand_types
[op
]);
5152 allowed
= operand_type_and (allowed
, anyimm
);
5154 switch (guess_suffix
)
5156 case QWORD_MNEM_SUFFIX
:
5157 mask
.bitfield
.imm64
= 1;
5158 mask
.bitfield
.imm32s
= 1;
5160 case LONG_MNEM_SUFFIX
:
5161 mask
.bitfield
.imm32
= 1;
5163 case WORD_MNEM_SUFFIX
:
5164 mask
.bitfield
.imm16
= 1;
5166 case BYTE_MNEM_SUFFIX
:
5167 mask
.bitfield
.imm8
= 1;
5172 allowed
= operand_type_and (mask
, allowed
);
5173 if (!operand_type_all_zero (&allowed
))
5174 i
.types
[op
] = operand_type_and (i
.types
[op
], mask
);
5181 /* Try to use the smallest displacement type too. */
5183 optimize_disp (void)
5187 for (op
= i
.operands
; --op
>= 0;)
5188 if (operand_type_check (i
.types
[op
], disp
))
5190 if (i
.op
[op
].disps
->X_op
== O_constant
)
5192 offsetT op_disp
= i
.op
[op
].disps
->X_add_number
;
5194 if (i
.types
[op
].bitfield
.disp16
5195 && (op_disp
& ~(offsetT
) 0xffff) == 0)
5197 /* If this operand is at most 16 bits, convert
5198 to a signed 16 bit number and don't use 64bit
5200 op_disp
= (((op_disp
& 0xffff) ^ 0x8000) - 0x8000);
5201 i
.types
[op
].bitfield
.disp64
= 0;
5204 /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */
5205 if (i
.types
[op
].bitfield
.disp32
5206 && (op_disp
& ~(((offsetT
) 2 << 31) - 1)) == 0)
5208 /* If this operand is at most 32 bits, convert
5209 to a signed 32 bit number and don't use 64bit
5211 op_disp
&= (((offsetT
) 2 << 31) - 1);
5212 op_disp
= (op_disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
5213 i
.types
[op
].bitfield
.disp64
= 0;
5216 if (!op_disp
&& i
.types
[op
].bitfield
.baseindex
)
5218 i
.types
[op
].bitfield
.disp8
= 0;
5219 i
.types
[op
].bitfield
.disp16
= 0;
5220 i
.types
[op
].bitfield
.disp32
= 0;
5221 i
.types
[op
].bitfield
.disp32s
= 0;
5222 i
.types
[op
].bitfield
.disp64
= 0;
5226 else if (flag_code
== CODE_64BIT
)
5228 if (fits_in_signed_long (op_disp
))
5230 i
.types
[op
].bitfield
.disp64
= 0;
5231 i
.types
[op
].bitfield
.disp32s
= 1;
5233 if (i
.prefix
[ADDR_PREFIX
]
5234 && fits_in_unsigned_long (op_disp
))
5235 i
.types
[op
].bitfield
.disp32
= 1;
5237 if ((i
.types
[op
].bitfield
.disp32
5238 || i
.types
[op
].bitfield
.disp32s
5239 || i
.types
[op
].bitfield
.disp16
)
5240 && fits_in_disp8 (op_disp
))
5241 i
.types
[op
].bitfield
.disp8
= 1;
5243 else if (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
5244 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
)
5246 fix_new_exp (frag_now
, frag_more (0) - frag_now
->fr_literal
, 0,
5247 i
.op
[op
].disps
, 0, i
.reloc
[op
]);
5248 i
.types
[op
].bitfield
.disp8
= 0;
5249 i
.types
[op
].bitfield
.disp16
= 0;
5250 i
.types
[op
].bitfield
.disp32
= 0;
5251 i
.types
[op
].bitfield
.disp32s
= 0;
5252 i
.types
[op
].bitfield
.disp64
= 0;
5255 /* We only support 64bit displacement on constants. */
5256 i
.types
[op
].bitfield
.disp64
= 0;
5260 /* Return 1 if there is a match in broadcast bytes between operand
5261 GIVEN and instruction template T. */
5264 match_broadcast_size (const insn_template
*t
, unsigned int given
)
5266 return ((t
->opcode_modifier
.broadcast
== BYTE_BROADCAST
5267 && i
.types
[given
].bitfield
.byte
)
5268 || (t
->opcode_modifier
.broadcast
== WORD_BROADCAST
5269 && i
.types
[given
].bitfield
.word
)
5270 || (t
->opcode_modifier
.broadcast
== DWORD_BROADCAST
5271 && i
.types
[given
].bitfield
.dword
)
5272 || (t
->opcode_modifier
.broadcast
== QWORD_BROADCAST
5273 && i
.types
[given
].bitfield
.qword
));
5276 /* Check if operands are valid for the instruction. */
5279 check_VecOperands (const insn_template
*t
)
5283 static const i386_cpu_flags avx512
= CPU_ANY_AVX512F_FLAGS
;
5285 /* Templates allowing for ZMMword as well as YMMword and/or XMMword for
5286 any one operand are implicity requiring AVX512VL support if the actual
5287 operand size is YMMword or XMMword. Since this function runs after
5288 template matching, there's no need to check for YMMword/XMMword in
5290 cpu
= cpu_flags_and (t
->cpu_flags
, avx512
);
5291 if (!cpu_flags_all_zero (&cpu
)
5292 && !t
->cpu_flags
.bitfield
.cpuavx512vl
5293 && !cpu_arch_flags
.bitfield
.cpuavx512vl
)
5295 for (op
= 0; op
< t
->operands
; ++op
)
5297 if (t
->operand_types
[op
].bitfield
.zmmword
5298 && (i
.types
[op
].bitfield
.ymmword
5299 || i
.types
[op
].bitfield
.xmmword
))
5301 i
.error
= unsupported
;
5307 /* Without VSIB byte, we can't have a vector register for index. */
5308 if (!t
->opcode_modifier
.vecsib
5310 && (i
.index_reg
->reg_type
.bitfield
.xmmword
5311 || i
.index_reg
->reg_type
.bitfield
.ymmword
5312 || i
.index_reg
->reg_type
.bitfield
.zmmword
))
5314 i
.error
= unsupported_vector_index_register
;
5318 /* Check if default mask is allowed. */
5319 if (t
->opcode_modifier
.nodefmask
5320 && (!i
.mask
|| i
.mask
->mask
->reg_num
== 0))
5322 i
.error
= no_default_mask
;
5326 /* For VSIB byte, we need a vector register for index, and all vector
5327 registers must be distinct. */
5328 if (t
->opcode_modifier
.vecsib
)
5331 || !((t
->opcode_modifier
.vecsib
== VecSIB128
5332 && i
.index_reg
->reg_type
.bitfield
.xmmword
)
5333 || (t
->opcode_modifier
.vecsib
== VecSIB256
5334 && i
.index_reg
->reg_type
.bitfield
.ymmword
)
5335 || (t
->opcode_modifier
.vecsib
== VecSIB512
5336 && i
.index_reg
->reg_type
.bitfield
.zmmword
)))
5338 i
.error
= invalid_vsib_address
;
5342 gas_assert (i
.reg_operands
== 2 || i
.mask
);
5343 if (i
.reg_operands
== 2 && !i
.mask
)
5345 gas_assert (i
.types
[0].bitfield
.class == RegSIMD
);
5346 gas_assert (i
.types
[0].bitfield
.xmmword
5347 || i
.types
[0].bitfield
.ymmword
);
5348 gas_assert (i
.types
[2].bitfield
.class == RegSIMD
);
5349 gas_assert (i
.types
[2].bitfield
.xmmword
5350 || i
.types
[2].bitfield
.ymmword
);
5351 if (operand_check
== check_none
)
5353 if (register_number (i
.op
[0].regs
)
5354 != register_number (i
.index_reg
)
5355 && register_number (i
.op
[2].regs
)
5356 != register_number (i
.index_reg
)
5357 && register_number (i
.op
[0].regs
)
5358 != register_number (i
.op
[2].regs
))
5360 if (operand_check
== check_error
)
5362 i
.error
= invalid_vector_register_set
;
5365 as_warn (_("mask, index, and destination registers should be distinct"));
5367 else if (i
.reg_operands
== 1 && i
.mask
)
5369 if (i
.types
[1].bitfield
.class == RegSIMD
5370 && (i
.types
[1].bitfield
.xmmword
5371 || i
.types
[1].bitfield
.ymmword
5372 || i
.types
[1].bitfield
.zmmword
)
5373 && (register_number (i
.op
[1].regs
)
5374 == register_number (i
.index_reg
)))
5376 if (operand_check
== check_error
)
5378 i
.error
= invalid_vector_register_set
;
5381 if (operand_check
!= check_none
)
5382 as_warn (_("index and destination registers should be distinct"));
5387 /* Check if broadcast is supported by the instruction and is applied
5388 to the memory operand. */
5391 i386_operand_type type
, overlap
;
5393 /* Check if specified broadcast is supported in this instruction,
5394 and its broadcast bytes match the memory operand. */
5395 op
= i
.broadcast
->operand
;
5396 if (!t
->opcode_modifier
.broadcast
5397 || !(i
.flags
[op
] & Operand_Mem
)
5398 || (!i
.types
[op
].bitfield
.unspecified
5399 && !match_broadcast_size (t
, op
)))
5402 i
.error
= unsupported_broadcast
;
5406 i
.broadcast
->bytes
= ((1 << (t
->opcode_modifier
.broadcast
- 1))
5407 * i
.broadcast
->type
);
5408 operand_type_set (&type
, 0);
5409 switch (i
.broadcast
->bytes
)
5412 type
.bitfield
.word
= 1;
5415 type
.bitfield
.dword
= 1;
5418 type
.bitfield
.qword
= 1;
5421 type
.bitfield
.xmmword
= 1;
5424 type
.bitfield
.ymmword
= 1;
5427 type
.bitfield
.zmmword
= 1;
5433 overlap
= operand_type_and (type
, t
->operand_types
[op
]);
5434 if (operand_type_all_zero (&overlap
))
5437 if (t
->opcode_modifier
.checkregsize
)
5441 type
.bitfield
.baseindex
= 1;
5442 for (j
= 0; j
< i
.operands
; ++j
)
5445 && !operand_type_register_match(i
.types
[j
],
5446 t
->operand_types
[j
],
5448 t
->operand_types
[op
]))
5453 /* If broadcast is supported in this instruction, we need to check if
5454 operand of one-element size isn't specified without broadcast. */
5455 else if (t
->opcode_modifier
.broadcast
&& i
.mem_operands
)
5457 /* Find memory operand. */
5458 for (op
= 0; op
< i
.operands
; op
++)
5459 if (i
.flags
[op
] & Operand_Mem
)
5461 gas_assert (op
< i
.operands
);
5462 /* Check size of the memory operand. */
5463 if (match_broadcast_size (t
, op
))
5465 i
.error
= broadcast_needed
;
5470 op
= MAX_OPERANDS
- 1; /* Avoid uninitialized variable warning. */
5472 /* Check if requested masking is supported. */
5475 switch (t
->opcode_modifier
.masking
)
5479 case MERGING_MASKING
:
5480 if (i
.mask
->zeroing
)
5483 i
.error
= unsupported_masking
;
5487 case DYNAMIC_MASKING
:
5488 /* Memory destinations allow only merging masking. */
5489 if (i
.mask
->zeroing
&& i
.mem_operands
)
5491 /* Find memory operand. */
5492 for (op
= 0; op
< i
.operands
; op
++)
5493 if (i
.flags
[op
] & Operand_Mem
)
5495 gas_assert (op
< i
.operands
);
5496 if (op
== i
.operands
- 1)
5498 i
.error
= unsupported_masking
;
5508 /* Check if masking is applied to dest operand. */
5509 if (i
.mask
&& (i
.mask
->operand
!= (int) (i
.operands
- 1)))
5511 i
.error
= mask_not_on_destination
;
5518 if (!t
->opcode_modifier
.sae
5519 || (i
.rounding
->type
!= saeonly
&& !t
->opcode_modifier
.staticrounding
))
5521 i
.error
= unsupported_rc_sae
;
5524 /* If the instruction has several immediate operands and one of
5525 them is rounding, the rounding operand should be the last
5526 immediate operand. */
5527 if (i
.imm_operands
> 1
5528 && i
.rounding
->operand
!= (int) (i
.imm_operands
- 1))
5530 i
.error
= rc_sae_operand_not_last_imm
;
5535 /* Check vector Disp8 operand. */
5536 if (t
->opcode_modifier
.disp8memshift
5537 && i
.disp_encoding
!= disp_encoding_32bit
)
5540 i
.memshift
= t
->opcode_modifier
.broadcast
- 1;
5541 else if (t
->opcode_modifier
.disp8memshift
!= DISP8_SHIFT_VL
)
5542 i
.memshift
= t
->opcode_modifier
.disp8memshift
;
5545 const i386_operand_type
*type
= NULL
;
5548 for (op
= 0; op
< i
.operands
; op
++)
5549 if (i
.flags
[op
] & Operand_Mem
)
5551 if (t
->opcode_modifier
.evex
== EVEXLIG
)
5552 i
.memshift
= 2 + (i
.suffix
== QWORD_MNEM_SUFFIX
);
5553 else if (t
->operand_types
[op
].bitfield
.xmmword
5554 + t
->operand_types
[op
].bitfield
.ymmword
5555 + t
->operand_types
[op
].bitfield
.zmmword
<= 1)
5556 type
= &t
->operand_types
[op
];
5557 else if (!i
.types
[op
].bitfield
.unspecified
)
5558 type
= &i
.types
[op
];
5560 else if (i
.types
[op
].bitfield
.class == RegSIMD
5561 && t
->opcode_modifier
.evex
!= EVEXLIG
)
5563 if (i
.types
[op
].bitfield
.zmmword
)
5565 else if (i
.types
[op
].bitfield
.ymmword
&& i
.memshift
< 5)
5567 else if (i
.types
[op
].bitfield
.xmmword
&& i
.memshift
< 4)
5573 if (type
->bitfield
.zmmword
)
5575 else if (type
->bitfield
.ymmword
)
5577 else if (type
->bitfield
.xmmword
)
5581 /* For the check in fits_in_disp8(). */
5582 if (i
.memshift
== 0)
5586 for (op
= 0; op
< i
.operands
; op
++)
5587 if (operand_type_check (i
.types
[op
], disp
)
5588 && i
.op
[op
].disps
->X_op
== O_constant
)
5590 if (fits_in_disp8 (i
.op
[op
].disps
->X_add_number
))
5592 i
.types
[op
].bitfield
.disp8
= 1;
5595 i
.types
[op
].bitfield
.disp8
= 0;
5604 /* Check if operands are valid for the instruction. Update VEX
5608 VEX_check_operands (const insn_template
*t
)
5610 if (i
.vec_encoding
== vex_encoding_evex
)
5612 /* This instruction must be encoded with EVEX prefix. */
5613 if (!is_evex_encoding (t
))
5615 i
.error
= unsupported
;
5621 if (!t
->opcode_modifier
.vex
)
5623 /* This instruction template doesn't have VEX prefix. */
5624 if (i
.vec_encoding
!= vex_encoding_default
)
5626 i
.error
= unsupported
;
5632 /* Check the special Imm4 cases; must be the first operand. */
5633 if (t
->cpu_flags
.bitfield
.cpuxop
&& t
->operands
== 5)
5635 if (i
.op
[0].imms
->X_op
!= O_constant
5636 || !fits_in_imm4 (i
.op
[0].imms
->X_add_number
))
5642 /* Turn off Imm<N> so that update_imm won't complain. */
5643 operand_type_set (&i
.types
[0], 0);
5649 static const insn_template
*
5650 match_template (char mnem_suffix
)
5652 /* Points to template once we've found it. */
5653 const insn_template
*t
;
5654 i386_operand_type overlap0
, overlap1
, overlap2
, overlap3
;
5655 i386_operand_type overlap4
;
5656 unsigned int found_reverse_match
;
5657 i386_opcode_modifier suffix_check
;
5658 i386_operand_type operand_types
[MAX_OPERANDS
];
5659 int addr_prefix_disp
;
5661 unsigned int found_cpu_match
, size_match
;
5662 unsigned int check_register
;
5663 enum i386_error specific_error
= 0;
5665 #if MAX_OPERANDS != 5
5666 # error "MAX_OPERANDS must be 5."
5669 found_reverse_match
= 0;
5670 addr_prefix_disp
= -1;
5672 /* Prepare for mnemonic suffix check. */
5673 memset (&suffix_check
, 0, sizeof (suffix_check
));
5674 switch (mnem_suffix
)
5676 case BYTE_MNEM_SUFFIX
:
5677 suffix_check
.no_bsuf
= 1;
5679 case WORD_MNEM_SUFFIX
:
5680 suffix_check
.no_wsuf
= 1;
5682 case SHORT_MNEM_SUFFIX
:
5683 suffix_check
.no_ssuf
= 1;
5685 case LONG_MNEM_SUFFIX
:
5686 suffix_check
.no_lsuf
= 1;
5688 case QWORD_MNEM_SUFFIX
:
5689 suffix_check
.no_qsuf
= 1;
5692 /* NB: In Intel syntax, normally we can check for memory operand
5693 size when there is no mnemonic suffix. But jmp and call have
5694 2 different encodings with Dword memory operand size, one with
5695 No_ldSuf and the other without. i.suffix is set to
5696 LONG_DOUBLE_MNEM_SUFFIX to skip the one with No_ldSuf. */
5697 if (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
)
5698 suffix_check
.no_ldsuf
= 1;
5701 /* Must have right number of operands. */
5702 i
.error
= number_of_operands_mismatch
;
5704 for (t
= current_templates
->start
; t
< current_templates
->end
; t
++)
5706 addr_prefix_disp
= -1;
5707 found_reverse_match
= 0;
5709 if (i
.operands
!= t
->operands
)
5712 /* Check processor support. */
5713 i
.error
= unsupported
;
5714 found_cpu_match
= (cpu_flags_match (t
)
5715 == CPU_FLAGS_PERFECT_MATCH
);
5716 if (!found_cpu_match
)
5719 /* Check AT&T mnemonic. */
5720 i
.error
= unsupported_with_intel_mnemonic
;
5721 if (intel_mnemonic
&& t
->opcode_modifier
.attmnemonic
)
5724 /* Check AT&T/Intel syntax and Intel64/AMD64 ISA. */
5725 i
.error
= unsupported_syntax
;
5726 if ((intel_syntax
&& t
->opcode_modifier
.attsyntax
)
5727 || (!intel_syntax
&& t
->opcode_modifier
.intelsyntax
)
5728 || (intel64
&& t
->opcode_modifier
.amd64
)
5729 || (!intel64
&& t
->opcode_modifier
.intel64
))
5732 /* Check the suffix. */
5733 i
.error
= invalid_instruction_suffix
;
5734 if ((t
->opcode_modifier
.no_bsuf
&& suffix_check
.no_bsuf
)
5735 || (t
->opcode_modifier
.no_wsuf
&& suffix_check
.no_wsuf
)
5736 || (t
->opcode_modifier
.no_lsuf
&& suffix_check
.no_lsuf
)
5737 || (t
->opcode_modifier
.no_ssuf
&& suffix_check
.no_ssuf
)
5738 || (t
->opcode_modifier
.no_qsuf
&& suffix_check
.no_qsuf
)
5739 || (t
->opcode_modifier
.no_ldsuf
&& suffix_check
.no_ldsuf
))
5742 size_match
= operand_size_match (t
);
5746 /* This is intentionally not
5748 if (i.jumpabsolute != t->opcode_modifier.jumpabsolute)
5750 as the case of a missing * on the operand is accepted (perhaps with
5751 a warning, issued further down). */
5752 if (i
.jumpabsolute
&& !t
->opcode_modifier
.jumpabsolute
)
5754 i
.error
= operand_type_mismatch
;
5758 for (j
= 0; j
< MAX_OPERANDS
; j
++)
5759 operand_types
[j
] = t
->operand_types
[j
];
5761 /* In general, don't allow 64-bit operands in 32-bit mode. */
5762 if (i
.suffix
== QWORD_MNEM_SUFFIX
5763 && flag_code
!= CODE_64BIT
5765 ? (!t
->opcode_modifier
.ignoresize
5766 && !t
->opcode_modifier
.broadcast
5767 && !intel_float_operand (t
->name
))
5768 : intel_float_operand (t
->name
) != 2)
5769 && ((operand_types
[0].bitfield
.class != RegMMX
5770 && operand_types
[0].bitfield
.class != RegSIMD
)
5771 || (operand_types
[t
->operands
> 1].bitfield
.class != RegMMX
5772 && operand_types
[t
->operands
> 1].bitfield
.class != RegSIMD
))
5773 && (t
->base_opcode
!= 0x0fc7
5774 || t
->extension_opcode
!= 1 /* cmpxchg8b */))
5777 /* In general, don't allow 32-bit operands on pre-386. */
5778 else if (i
.suffix
== LONG_MNEM_SUFFIX
5779 && !cpu_arch_flags
.bitfield
.cpui386
5781 ? (!t
->opcode_modifier
.ignoresize
5782 && !intel_float_operand (t
->name
))
5783 : intel_float_operand (t
->name
) != 2)
5784 && ((operand_types
[0].bitfield
.class != RegMMX
5785 && operand_types
[0].bitfield
.class != RegSIMD
)
5786 || (operand_types
[t
->operands
> 1].bitfield
.class != RegMMX
5787 && operand_types
[t
->operands
> 1].bitfield
.class
5791 /* Do not verify operands when there are none. */
5795 /* We've found a match; break out of loop. */
5799 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
5800 into Disp32/Disp16/Disp32 operand. */
5801 if (i
.prefix
[ADDR_PREFIX
] != 0)
5803 /* There should be only one Disp operand. */
5807 for (j
= 0; j
< MAX_OPERANDS
; j
++)
5809 if (operand_types
[j
].bitfield
.disp16
)
5811 addr_prefix_disp
= j
;
5812 operand_types
[j
].bitfield
.disp32
= 1;
5813 operand_types
[j
].bitfield
.disp16
= 0;
5819 for (j
= 0; j
< MAX_OPERANDS
; j
++)
5821 if (operand_types
[j
].bitfield
.disp32
)
5823 addr_prefix_disp
= j
;
5824 operand_types
[j
].bitfield
.disp32
= 0;
5825 operand_types
[j
].bitfield
.disp16
= 1;
5831 for (j
= 0; j
< MAX_OPERANDS
; j
++)
5833 if (operand_types
[j
].bitfield
.disp64
)
5835 addr_prefix_disp
= j
;
5836 operand_types
[j
].bitfield
.disp64
= 0;
5837 operand_types
[j
].bitfield
.disp32
= 1;
5845 /* Force 0x8b encoding for "mov foo@GOT, %eax". */
5846 if (i
.reloc
[0] == BFD_RELOC_386_GOT32
&& t
->base_opcode
== 0xa0)
5849 /* We check register size if needed. */
5850 if (t
->opcode_modifier
.checkregsize
)
5852 check_register
= (1 << t
->operands
) - 1;
5854 check_register
&= ~(1 << i
.broadcast
->operand
);
5859 overlap0
= operand_type_and (i
.types
[0], operand_types
[0]);
5860 switch (t
->operands
)
5863 if (!operand_type_match (overlap0
, i
.types
[0]))
5867 /* xchg %eax, %eax is a special case. It is an alias for nop
5868 only in 32bit mode and we can use opcode 0x90. In 64bit
5869 mode, we can't use 0x90 for xchg %eax, %eax since it should
5870 zero-extend %eax to %rax. */
5871 if (flag_code
== CODE_64BIT
5872 && t
->base_opcode
== 0x90
5873 && i
.types
[0].bitfield
.instance
== Accum
5874 && i
.types
[0].bitfield
.dword
5875 && i
.types
[1].bitfield
.instance
== Accum
5876 && i
.types
[1].bitfield
.dword
)
5878 /* xrelease mov %eax, <disp> is another special case. It must not
5879 match the accumulator-only encoding of mov. */
5880 if (flag_code
!= CODE_64BIT
5882 && t
->base_opcode
== 0xa0
5883 && i
.types
[0].bitfield
.instance
== Accum
5884 && (i
.flags
[1] & Operand_Mem
))
5889 if (!(size_match
& MATCH_STRAIGHT
))
5891 /* Reverse direction of operands if swapping is possible in the first
5892 place (operands need to be symmetric) and
5893 - the load form is requested, and the template is a store form,
5894 - the store form is requested, and the template is a load form,
5895 - the non-default (swapped) form is requested. */
5896 overlap1
= operand_type_and (operand_types
[0], operand_types
[1]);
5897 if (t
->opcode_modifier
.d
&& i
.reg_operands
== i
.operands
5898 && !operand_type_all_zero (&overlap1
))
5899 switch (i
.dir_encoding
)
5901 case dir_encoding_load
:
5902 if (operand_type_check (operand_types
[i
.operands
- 1], anymem
)
5903 || t
->opcode_modifier
.regmem
)
5907 case dir_encoding_store
:
5908 if (!operand_type_check (operand_types
[i
.operands
- 1], anymem
)
5909 && !t
->opcode_modifier
.regmem
)
5913 case dir_encoding_swap
:
5916 case dir_encoding_default
:
5919 /* If we want store form, we skip the current load. */
5920 if ((i
.dir_encoding
== dir_encoding_store
5921 || i
.dir_encoding
== dir_encoding_swap
)
5922 && i
.mem_operands
== 0
5923 && t
->opcode_modifier
.load
)
5928 overlap1
= operand_type_and (i
.types
[1], operand_types
[1]);
5929 if (!operand_type_match (overlap0
, i
.types
[0])
5930 || !operand_type_match (overlap1
, i
.types
[1])
5931 || ((check_register
& 3) == 3
5932 && !operand_type_register_match (i
.types
[0],
5937 /* Check if other direction is valid ... */
5938 if (!t
->opcode_modifier
.d
)
5942 if (!(size_match
& MATCH_REVERSE
))
5944 /* Try reversing direction of operands. */
5945 overlap0
= operand_type_and (i
.types
[0], operand_types
[i
.operands
- 1]);
5946 overlap1
= operand_type_and (i
.types
[i
.operands
- 1], operand_types
[0]);
5947 if (!operand_type_match (overlap0
, i
.types
[0])
5948 || !operand_type_match (overlap1
, i
.types
[i
.operands
- 1])
5950 && !operand_type_register_match (i
.types
[0],
5951 operand_types
[i
.operands
- 1],
5952 i
.types
[i
.operands
- 1],
5955 /* Does not match either direction. */
5958 /* found_reverse_match holds which of D or FloatR
5960 if (!t
->opcode_modifier
.d
)
5961 found_reverse_match
= 0;
5962 else if (operand_types
[0].bitfield
.tbyte
)
5963 found_reverse_match
= Opcode_FloatD
;
5964 else if (operand_types
[0].bitfield
.xmmword
5965 || operand_types
[i
.operands
- 1].bitfield
.xmmword
5966 || operand_types
[0].bitfield
.class == RegMMX
5967 || operand_types
[i
.operands
- 1].bitfield
.class == RegMMX
5968 || is_any_vex_encoding(t
))
5969 found_reverse_match
= (t
->base_opcode
& 0xee) != 0x6e
5970 ? Opcode_SIMD_FloatD
: Opcode_SIMD_IntD
;
5972 found_reverse_match
= Opcode_D
;
5973 if (t
->opcode_modifier
.floatr
)
5974 found_reverse_match
|= Opcode_FloatR
;
5978 /* Found a forward 2 operand match here. */
5979 switch (t
->operands
)
5982 overlap4
= operand_type_and (i
.types
[4],
5986 overlap3
= operand_type_and (i
.types
[3],
5990 overlap2
= operand_type_and (i
.types
[2],
5995 switch (t
->operands
)
5998 if (!operand_type_match (overlap4
, i
.types
[4])
5999 || !operand_type_register_match (i
.types
[3],
6006 if (!operand_type_match (overlap3
, i
.types
[3])
6007 || ((check_register
& 0xa) == 0xa
6008 && !operand_type_register_match (i
.types
[1],
6012 || ((check_register
& 0xc) == 0xc
6013 && !operand_type_register_match (i
.types
[2],
6020 /* Here we make use of the fact that there are no
6021 reverse match 3 operand instructions. */
6022 if (!operand_type_match (overlap2
, i
.types
[2])
6023 || ((check_register
& 5) == 5
6024 && !operand_type_register_match (i
.types
[0],
6028 || ((check_register
& 6) == 6
6029 && !operand_type_register_match (i
.types
[1],
6037 /* Found either forward/reverse 2, 3 or 4 operand match here:
6038 slip through to break. */
6040 if (!found_cpu_match
)
6043 /* Check if vector and VEX operands are valid. */
6044 if (check_VecOperands (t
) || VEX_check_operands (t
))
6046 specific_error
= i
.error
;
6050 /* We've found a match; break out of loop. */
6054 if (t
== current_templates
->end
)
6056 /* We found no match. */
6057 const char *err_msg
;
6058 switch (specific_error
? specific_error
: i
.error
)
6062 case operand_size_mismatch
:
6063 err_msg
= _("operand size mismatch");
6065 case operand_type_mismatch
:
6066 err_msg
= _("operand type mismatch");
6068 case register_type_mismatch
:
6069 err_msg
= _("register type mismatch");
6071 case number_of_operands_mismatch
:
6072 err_msg
= _("number of operands mismatch");
6074 case invalid_instruction_suffix
:
6075 err_msg
= _("invalid instruction suffix");
6078 err_msg
= _("constant doesn't fit in 4 bits");
6080 case unsupported_with_intel_mnemonic
:
6081 err_msg
= _("unsupported with Intel mnemonic");
6083 case unsupported_syntax
:
6084 err_msg
= _("unsupported syntax");
6087 as_bad (_("unsupported instruction `%s'"),
6088 current_templates
->start
->name
);
6090 case invalid_vsib_address
:
6091 err_msg
= _("invalid VSIB address");
6093 case invalid_vector_register_set
:
6094 err_msg
= _("mask, index, and destination registers must be distinct");
6096 case unsupported_vector_index_register
:
6097 err_msg
= _("unsupported vector index register");
6099 case unsupported_broadcast
:
6100 err_msg
= _("unsupported broadcast");
6102 case broadcast_needed
:
6103 err_msg
= _("broadcast is needed for operand of such type");
6105 case unsupported_masking
:
6106 err_msg
= _("unsupported masking");
6108 case mask_not_on_destination
:
6109 err_msg
= _("mask not on destination operand");
6111 case no_default_mask
:
6112 err_msg
= _("default mask isn't allowed");
6114 case unsupported_rc_sae
:
6115 err_msg
= _("unsupported static rounding/sae");
6117 case rc_sae_operand_not_last_imm
:
6119 err_msg
= _("RC/SAE operand must precede immediate operands");
6121 err_msg
= _("RC/SAE operand must follow immediate operands");
6123 case invalid_register_operand
:
6124 err_msg
= _("invalid register operand");
6127 as_bad (_("%s for `%s'"), err_msg
,
6128 current_templates
->start
->name
);
6132 if (!quiet_warnings
)
6135 && (i
.jumpabsolute
!= t
->opcode_modifier
.jumpabsolute
))
6136 as_warn (_("indirect %s without `*'"), t
->name
);
6138 if (t
->opcode_modifier
.isprefix
6139 && t
->opcode_modifier
.ignoresize
)
6141 /* Warn them that a data or address size prefix doesn't
6142 affect assembly of the next line of code. */
6143 as_warn (_("stand-alone `%s' prefix"), t
->name
);
6147 /* Copy the template we found. */
6150 if (addr_prefix_disp
!= -1)
6151 i
.tm
.operand_types
[addr_prefix_disp
]
6152 = operand_types
[addr_prefix_disp
];
6154 if (found_reverse_match
)
6156 /* If we found a reverse match we must alter the opcode direction
6157 bit and clear/flip the regmem modifier one. found_reverse_match
6158 holds bits to change (different for int & float insns). */
6160 i
.tm
.base_opcode
^= found_reverse_match
;
6162 i
.tm
.operand_types
[0] = operand_types
[i
.operands
- 1];
6163 i
.tm
.operand_types
[i
.operands
- 1] = operand_types
[0];
6165 /* Certain SIMD insns have their load forms specified in the opcode
6166 table, and hence we need to _set_ RegMem instead of clearing it.
6167 We need to avoid setting the bit though on insns like KMOVW. */
6168 i
.tm
.opcode_modifier
.regmem
6169 = i
.tm
.opcode_modifier
.modrm
&& i
.tm
.opcode_modifier
.d
6170 && i
.tm
.operands
> 2U - i
.tm
.opcode_modifier
.sse2avx
6171 && !i
.tm
.opcode_modifier
.regmem
;
6180 unsigned int es_op
= i
.tm
.opcode_modifier
.isstring
- IS_STRING_ES_OP0
;
6181 unsigned int op
= i
.tm
.operand_types
[0].bitfield
.baseindex
? es_op
: 0;
6183 if (i
.seg
[op
] != NULL
&& i
.seg
[op
] != &es
)
6185 as_bad (_("`%s' operand %u must use `%ses' segment"),
6187 intel_syntax
? i
.tm
.operands
- es_op
: es_op
+ 1,
6192 /* There's only ever one segment override allowed per instruction.
6193 This instruction possibly has a legal segment override on the
6194 second operand, so copy the segment to where non-string
6195 instructions store it, allowing common code. */
6196 i
.seg
[op
] = i
.seg
[1];
6202 process_suffix (void)
6204 /* If matched instruction specifies an explicit instruction mnemonic
6206 if (i
.tm
.opcode_modifier
.size
== SIZE16
)
6207 i
.suffix
= WORD_MNEM_SUFFIX
;
6208 else if (i
.tm
.opcode_modifier
.size
== SIZE32
)
6209 i
.suffix
= LONG_MNEM_SUFFIX
;
6210 else if (i
.tm
.opcode_modifier
.size
== SIZE64
)
6211 i
.suffix
= QWORD_MNEM_SUFFIX
;
6212 else if (i
.reg_operands
)
6214 /* If there's no instruction mnemonic suffix we try to invent one
6215 based on register operands. */
6218 /* We take i.suffix from the last register operand specified,
6219 Destination register type is more significant than source
6220 register type. crc32 in SSE4.2 prefers source register
6222 if (i
.tm
.base_opcode
== 0xf20f38f0
6223 && i
.types
[0].bitfield
.class == Reg
)
6225 if (i
.types
[0].bitfield
.byte
)
6226 i
.suffix
= BYTE_MNEM_SUFFIX
;
6227 else if (i
.types
[0].bitfield
.word
)
6228 i
.suffix
= WORD_MNEM_SUFFIX
;
6229 else if (i
.types
[0].bitfield
.dword
)
6230 i
.suffix
= LONG_MNEM_SUFFIX
;
6231 else if (i
.types
[0].bitfield
.qword
)
6232 i
.suffix
= QWORD_MNEM_SUFFIX
;
6239 if (i
.tm
.base_opcode
== 0xf20f38f0)
6241 /* We have to know the operand size for crc32. */
6242 as_bad (_("ambiguous memory operand size for `%s`"),
6247 for (op
= i
.operands
; --op
>= 0;)
6248 if (i
.tm
.operand_types
[op
].bitfield
.instance
== InstanceNone
6249 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
6251 if (i
.types
[op
].bitfield
.class != Reg
)
6253 if (i
.types
[op
].bitfield
.byte
)
6254 i
.suffix
= BYTE_MNEM_SUFFIX
;
6255 else if (i
.types
[op
].bitfield
.word
)
6256 i
.suffix
= WORD_MNEM_SUFFIX
;
6257 else if (i
.types
[op
].bitfield
.dword
)
6258 i
.suffix
= LONG_MNEM_SUFFIX
;
6259 else if (i
.types
[op
].bitfield
.qword
)
6260 i
.suffix
= QWORD_MNEM_SUFFIX
;
6267 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
6270 && i
.tm
.opcode_modifier
.ignoresize
6271 && i
.tm
.opcode_modifier
.no_bsuf
)
6273 else if (!check_byte_reg ())
6276 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
6279 && i
.tm
.opcode_modifier
.ignoresize
6280 && i
.tm
.opcode_modifier
.no_lsuf
6281 && !i
.tm
.opcode_modifier
.todword
6282 && !i
.tm
.opcode_modifier
.toqword
)
6284 else if (!check_long_reg ())
6287 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
6290 && i
.tm
.opcode_modifier
.ignoresize
6291 && i
.tm
.opcode_modifier
.no_qsuf
6292 && !i
.tm
.opcode_modifier
.todword
6293 && !i
.tm
.opcode_modifier
.toqword
)
6295 else if (!check_qword_reg ())
6298 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
6301 && i
.tm
.opcode_modifier
.ignoresize
6302 && i
.tm
.opcode_modifier
.no_wsuf
)
6304 else if (!check_word_reg ())
6307 else if (intel_syntax
&& i
.tm
.opcode_modifier
.ignoresize
)
6308 /* Do nothing if the instruction is going to ignore the prefix. */
6313 else if (i
.tm
.opcode_modifier
.defaultsize
6315 /* exclude fldenv/frstor/fsave/fstenv */
6316 && i
.tm
.opcode_modifier
.no_ssuf
)
6318 if (stackop_size
== LONG_MNEM_SUFFIX
6319 && i
.tm
.base_opcode
== 0xcf)
6321 /* stackop_size is set to LONG_MNEM_SUFFIX for the
6322 .code16gcc directive to support 16-bit mode with
6323 32-bit address. For IRET without a suffix, generate
6324 16-bit IRET (opcode 0xcf) to return from an interrupt
6326 i
.suffix
= WORD_MNEM_SUFFIX
;
6327 as_warn (_("generating 16-bit `iret' for .code16gcc directive"));
6330 i
.suffix
= stackop_size
;
6332 else if (intel_syntax
6334 && (i
.tm
.opcode_modifier
.jumpabsolute
6335 || i
.tm
.opcode_modifier
.jumpbyte
6336 || i
.tm
.opcode_modifier
.jumpintersegment
6337 || (i
.tm
.base_opcode
== 0x0f01 /* [ls][gi]dt */
6338 && i
.tm
.extension_opcode
<= 3)))
6343 if (!i
.tm
.opcode_modifier
.no_qsuf
)
6345 i
.suffix
= QWORD_MNEM_SUFFIX
;
6350 if (!i
.tm
.opcode_modifier
.no_lsuf
)
6351 i
.suffix
= LONG_MNEM_SUFFIX
;
6354 if (!i
.tm
.opcode_modifier
.no_wsuf
)
6355 i
.suffix
= WORD_MNEM_SUFFIX
;
6364 if (i
.tm
.opcode_modifier
.w
)
6366 as_bad (_("no instruction mnemonic suffix given and "
6367 "no register operands; can't size instruction"));
6373 unsigned int suffixes
;
6375 suffixes
= !i
.tm
.opcode_modifier
.no_bsuf
;
6376 if (!i
.tm
.opcode_modifier
.no_wsuf
)
6378 if (!i
.tm
.opcode_modifier
.no_lsuf
)
6380 if (!i
.tm
.opcode_modifier
.no_ldsuf
)
6382 if (!i
.tm
.opcode_modifier
.no_ssuf
)
6384 if (flag_code
== CODE_64BIT
&& !i
.tm
.opcode_modifier
.no_qsuf
)
6387 /* There are more than suffix matches. */
6388 if (i
.tm
.opcode_modifier
.w
6389 || ((suffixes
& (suffixes
- 1))
6390 && !i
.tm
.opcode_modifier
.defaultsize
6391 && !i
.tm
.opcode_modifier
.ignoresize
))
6393 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
6399 /* Change the opcode based on the operand size given by i.suffix. */
6402 /* Size floating point instruction. */
6403 case LONG_MNEM_SUFFIX
:
6404 if (i
.tm
.opcode_modifier
.floatmf
)
6406 i
.tm
.base_opcode
^= 4;
6410 case WORD_MNEM_SUFFIX
:
6411 case QWORD_MNEM_SUFFIX
:
6412 /* It's not a byte, select word/dword operation. */
6413 if (i
.tm
.opcode_modifier
.w
)
6415 if (i
.tm
.opcode_modifier
.shortform
)
6416 i
.tm
.base_opcode
|= 8;
6418 i
.tm
.base_opcode
|= 1;
6421 case SHORT_MNEM_SUFFIX
:
6422 /* Now select between word & dword operations via the operand
6423 size prefix, except for instructions that will ignore this
6425 if (i
.reg_operands
> 0
6426 && i
.types
[0].bitfield
.class == Reg
6427 && i
.tm
.opcode_modifier
.addrprefixopreg
6428 && (i
.tm
.operand_types
[0].bitfield
.instance
== Accum
6429 || i
.operands
== 1))
6431 /* The address size override prefix changes the size of the
6433 if ((flag_code
== CODE_32BIT
6434 && i
.op
[0].regs
->reg_type
.bitfield
.word
)
6435 || (flag_code
!= CODE_32BIT
6436 && i
.op
[0].regs
->reg_type
.bitfield
.dword
))
6437 if (!add_prefix (ADDR_PREFIX_OPCODE
))
6440 else if (i
.suffix
!= QWORD_MNEM_SUFFIX
6441 && !i
.tm
.opcode_modifier
.ignoresize
6442 && !i
.tm
.opcode_modifier
.floatmf
6443 && !is_any_vex_encoding (&i
.tm
)
6444 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
6445 || (flag_code
== CODE_64BIT
6446 && i
.tm
.opcode_modifier
.jumpbyte
)))
6448 unsigned int prefix
= DATA_PREFIX_OPCODE
;
6450 if (i
.tm
.opcode_modifier
.jumpbyte
) /* jcxz, loop */
6451 prefix
= ADDR_PREFIX_OPCODE
;
6453 if (!add_prefix (prefix
))
6457 /* Set mode64 for an operand. */
6458 if (i
.suffix
== QWORD_MNEM_SUFFIX
6459 && flag_code
== CODE_64BIT
6460 && !i
.tm
.opcode_modifier
.norex64
6461 /* Special case for xchg %rax,%rax. It is NOP and doesn't
6463 && ! (i
.operands
== 2
6464 && i
.tm
.base_opcode
== 0x90
6465 && i
.tm
.extension_opcode
== None
6466 && i
.types
[0].bitfield
.instance
== Accum
6467 && i
.types
[0].bitfield
.qword
6468 && i
.types
[1].bitfield
.instance
== Accum
6469 && i
.types
[1].bitfield
.qword
))
6475 if (i
.reg_operands
!= 0
6477 && i
.tm
.opcode_modifier
.addrprefixopreg
6478 && i
.tm
.operand_types
[0].bitfield
.instance
!= Accum
)
6480 /* Check invalid register operand when the address size override
6481 prefix changes the size of register operands. */
6483 enum { need_word
, need_dword
, need_qword
} need
;
6485 if (flag_code
== CODE_32BIT
)
6486 need
= i
.prefix
[ADDR_PREFIX
] ? need_word
: need_dword
;
6489 if (i
.prefix
[ADDR_PREFIX
])
6492 need
= flag_code
== CODE_64BIT
? need_qword
: need_word
;
6495 for (op
= 0; op
< i
.operands
; op
++)
6496 if (i
.types
[op
].bitfield
.class == Reg
6497 && ((need
== need_word
6498 && !i
.op
[op
].regs
->reg_type
.bitfield
.word
)
6499 || (need
== need_dword
6500 && !i
.op
[op
].regs
->reg_type
.bitfield
.dword
)
6501 || (need
== need_qword
6502 && !i
.op
[op
].regs
->reg_type
.bitfield
.qword
)))
6504 as_bad (_("invalid register operand size for `%s'"),
6514 check_byte_reg (void)
6518 for (op
= i
.operands
; --op
>= 0;)
6520 /* Skip non-register operands. */
6521 if (i
.types
[op
].bitfield
.class != Reg
)
6524 /* If this is an eight bit register, it's OK. If it's the 16 or
6525 32 bit version of an eight bit register, we will just use the
6526 low portion, and that's OK too. */
6527 if (i
.types
[op
].bitfield
.byte
)
6530 /* I/O port address operands are OK too. */
6531 if (i
.tm
.operand_types
[op
].bitfield
.instance
== RegD
6532 && i
.tm
.operand_types
[op
].bitfield
.word
)
6535 /* crc32 doesn't generate this warning. */
6536 if (i
.tm
.base_opcode
== 0xf20f38f0)
6539 if ((i
.types
[op
].bitfield
.word
6540 || i
.types
[op
].bitfield
.dword
6541 || i
.types
[op
].bitfield
.qword
)
6542 && i
.op
[op
].regs
->reg_num
< 4
6543 /* Prohibit these changes in 64bit mode, since the lowering
6544 would be more complicated. */
6545 && flag_code
!= CODE_64BIT
)
6547 #if REGISTER_WARNINGS
6548 if (!quiet_warnings
)
6549 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6551 (i
.op
[op
].regs
+ (i
.types
[op
].bitfield
.word
6552 ? REGNAM_AL
- REGNAM_AX
6553 : REGNAM_AL
- REGNAM_EAX
))->reg_name
,
6555 i
.op
[op
].regs
->reg_name
,
6560 /* Any other register is bad. */
6561 if (i
.types
[op
].bitfield
.class == Reg
6562 || i
.types
[op
].bitfield
.class == RegMMX
6563 || i
.types
[op
].bitfield
.class == RegSIMD
6564 || i
.types
[op
].bitfield
.class == SReg
6565 || i
.types
[op
].bitfield
.class == RegCR
6566 || i
.types
[op
].bitfield
.class == RegDR
6567 || i
.types
[op
].bitfield
.class == RegTR
)
6569 as_bad (_("`%s%s' not allowed with `%s%c'"),
6571 i
.op
[op
].regs
->reg_name
,
6581 check_long_reg (void)
6585 for (op
= i
.operands
; --op
>= 0;)
6586 /* Skip non-register operands. */
6587 if (i
.types
[op
].bitfield
.class != Reg
)
6589 /* Reject eight bit registers, except where the template requires
6590 them. (eg. movzb) */
6591 else if (i
.types
[op
].bitfield
.byte
6592 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
6593 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
6594 && (i
.tm
.operand_types
[op
].bitfield
.word
6595 || i
.tm
.operand_types
[op
].bitfield
.dword
))
6597 as_bad (_("`%s%s' not allowed with `%s%c'"),
6599 i
.op
[op
].regs
->reg_name
,
6604 /* Warn if the e prefix on a general reg is missing. */
6605 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
6606 && i
.types
[op
].bitfield
.word
6607 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
6608 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
6609 && i
.tm
.operand_types
[op
].bitfield
.dword
)
6611 /* Prohibit these changes in the 64bit mode, since the
6612 lowering is more complicated. */
6613 if (flag_code
== CODE_64BIT
)
6615 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6616 register_prefix
, i
.op
[op
].regs
->reg_name
,
6620 #if REGISTER_WARNINGS
6621 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6623 (i
.op
[op
].regs
+ REGNAM_EAX
- REGNAM_AX
)->reg_name
,
6624 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
6627 /* Warn if the r prefix on a general reg is present. */
6628 else if (i
.types
[op
].bitfield
.qword
6629 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
6630 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
6631 && i
.tm
.operand_types
[op
].bitfield
.dword
)
6634 && i
.tm
.opcode_modifier
.toqword
6635 && i
.types
[0].bitfield
.class != RegSIMD
)
6637 /* Convert to QWORD. We want REX byte. */
6638 i
.suffix
= QWORD_MNEM_SUFFIX
;
6642 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6643 register_prefix
, i
.op
[op
].regs
->reg_name
,
6652 check_qword_reg (void)
6656 for (op
= i
.operands
; --op
>= 0; )
6657 /* Skip non-register operands. */
6658 if (i
.types
[op
].bitfield
.class != Reg
)
6660 /* Reject eight bit registers, except where the template requires
6661 them. (eg. movzb) */
6662 else if (i
.types
[op
].bitfield
.byte
6663 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
6664 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
6665 && (i
.tm
.operand_types
[op
].bitfield
.word
6666 || i
.tm
.operand_types
[op
].bitfield
.dword
))
6668 as_bad (_("`%s%s' not allowed with `%s%c'"),
6670 i
.op
[op
].regs
->reg_name
,
6675 /* Warn if the r prefix on a general reg is missing. */
6676 else if ((i
.types
[op
].bitfield
.word
6677 || i
.types
[op
].bitfield
.dword
)
6678 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
6679 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
6680 && i
.tm
.operand_types
[op
].bitfield
.qword
)
6682 /* Prohibit these changes in the 64bit mode, since the
6683 lowering is more complicated. */
6685 && i
.tm
.opcode_modifier
.todword
6686 && i
.types
[0].bitfield
.class != RegSIMD
)
6688 /* Convert to DWORD. We don't want REX byte. */
6689 i
.suffix
= LONG_MNEM_SUFFIX
;
6693 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6694 register_prefix
, i
.op
[op
].regs
->reg_name
,
6703 check_word_reg (void)
6706 for (op
= i
.operands
; --op
>= 0;)
6707 /* Skip non-register operands. */
6708 if (i
.types
[op
].bitfield
.class != Reg
)
6710 /* Reject eight bit registers, except where the template requires
6711 them. (eg. movzb) */
6712 else if (i
.types
[op
].bitfield
.byte
6713 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
6714 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
6715 && (i
.tm
.operand_types
[op
].bitfield
.word
6716 || i
.tm
.operand_types
[op
].bitfield
.dword
))
6718 as_bad (_("`%s%s' not allowed with `%s%c'"),
6720 i
.op
[op
].regs
->reg_name
,
6725 /* Warn if the e or r prefix on a general reg is present. */
6726 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
6727 && (i
.types
[op
].bitfield
.dword
6728 || i
.types
[op
].bitfield
.qword
)
6729 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
6730 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
6731 && i
.tm
.operand_types
[op
].bitfield
.word
)
6733 /* Prohibit these changes in the 64bit mode, since the
6734 lowering is more complicated. */
6735 if (flag_code
== CODE_64BIT
)
6737 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6738 register_prefix
, i
.op
[op
].regs
->reg_name
,
6742 #if REGISTER_WARNINGS
6743 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6745 (i
.op
[op
].regs
+ REGNAM_AX
- REGNAM_EAX
)->reg_name
,
6746 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
6753 update_imm (unsigned int j
)
6755 i386_operand_type overlap
= i
.types
[j
];
6756 if ((overlap
.bitfield
.imm8
6757 || overlap
.bitfield
.imm8s
6758 || overlap
.bitfield
.imm16
6759 || overlap
.bitfield
.imm32
6760 || overlap
.bitfield
.imm32s
6761 || overlap
.bitfield
.imm64
)
6762 && !operand_type_equal (&overlap
, &imm8
)
6763 && !operand_type_equal (&overlap
, &imm8s
)
6764 && !operand_type_equal (&overlap
, &imm16
)
6765 && !operand_type_equal (&overlap
, &imm32
)
6766 && !operand_type_equal (&overlap
, &imm32s
)
6767 && !operand_type_equal (&overlap
, &imm64
))
6771 i386_operand_type temp
;
6773 operand_type_set (&temp
, 0);
6774 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
6776 temp
.bitfield
.imm8
= overlap
.bitfield
.imm8
;
6777 temp
.bitfield
.imm8s
= overlap
.bitfield
.imm8s
;
6779 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
6780 temp
.bitfield
.imm16
= overlap
.bitfield
.imm16
;
6781 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
6783 temp
.bitfield
.imm64
= overlap
.bitfield
.imm64
;
6784 temp
.bitfield
.imm32s
= overlap
.bitfield
.imm32s
;
6787 temp
.bitfield
.imm32
= overlap
.bitfield
.imm32
;
6790 else if (operand_type_equal (&overlap
, &imm16_32_32s
)
6791 || operand_type_equal (&overlap
, &imm16_32
)
6792 || operand_type_equal (&overlap
, &imm16_32s
))
6794 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
6799 if (!operand_type_equal (&overlap
, &imm8
)
6800 && !operand_type_equal (&overlap
, &imm8s
)
6801 && !operand_type_equal (&overlap
, &imm16
)
6802 && !operand_type_equal (&overlap
, &imm32
)
6803 && !operand_type_equal (&overlap
, &imm32s
)
6804 && !operand_type_equal (&overlap
, &imm64
))
6806 as_bad (_("no instruction mnemonic suffix given; "
6807 "can't determine immediate size"));
6811 i
.types
[j
] = overlap
;
6821 /* Update the first 2 immediate operands. */
6822 n
= i
.operands
> 2 ? 2 : i
.operands
;
6825 for (j
= 0; j
< n
; j
++)
6826 if (update_imm (j
) == 0)
6829 /* The 3rd operand can't be immediate operand. */
6830 gas_assert (operand_type_check (i
.types
[2], imm
) == 0);
6837 process_operands (void)
6839 /* Default segment register this instruction will use for memory
6840 accesses. 0 means unknown. This is only for optimizing out
6841 unnecessary segment overrides. */
6842 const seg_entry
*default_seg
= 0;
6844 if (i
.tm
.opcode_modifier
.sse2avx
&& i
.tm
.opcode_modifier
.vexvvvv
)
6846 unsigned int dupl
= i
.operands
;
6847 unsigned int dest
= dupl
- 1;
6850 /* The destination must be an xmm register. */
6851 gas_assert (i
.reg_operands
6852 && MAX_OPERANDS
> dupl
6853 && operand_type_equal (&i
.types
[dest
], ®xmm
));
6855 if (i
.tm
.operand_types
[0].bitfield
.instance
== Accum
6856 && i
.tm
.operand_types
[0].bitfield
.xmmword
)
6858 if (i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
)
6860 /* Keep xmm0 for instructions with VEX prefix and 3
6862 i
.tm
.operand_types
[0].bitfield
.instance
= InstanceNone
;
6863 i
.tm
.operand_types
[0].bitfield
.class = RegSIMD
;
6868 /* We remove the first xmm0 and keep the number of
6869 operands unchanged, which in fact duplicates the
6871 for (j
= 1; j
< i
.operands
; j
++)
6873 i
.op
[j
- 1] = i
.op
[j
];
6874 i
.types
[j
- 1] = i
.types
[j
];
6875 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
6876 i
.flags
[j
- 1] = i
.flags
[j
];
6880 else if (i
.tm
.opcode_modifier
.implicit1stxmm0
)
6882 gas_assert ((MAX_OPERANDS
- 1) > dupl
6883 && (i
.tm
.opcode_modifier
.vexsources
6886 /* Add the implicit xmm0 for instructions with VEX prefix
6888 for (j
= i
.operands
; j
> 0; j
--)
6890 i
.op
[j
] = i
.op
[j
- 1];
6891 i
.types
[j
] = i
.types
[j
- 1];
6892 i
.tm
.operand_types
[j
] = i
.tm
.operand_types
[j
- 1];
6893 i
.flags
[j
] = i
.flags
[j
- 1];
6896 = (const reg_entry
*) hash_find (reg_hash
, "xmm0");
6897 i
.types
[0] = regxmm
;
6898 i
.tm
.operand_types
[0] = regxmm
;
6901 i
.reg_operands
+= 2;
6906 i
.op
[dupl
] = i
.op
[dest
];
6907 i
.types
[dupl
] = i
.types
[dest
];
6908 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
6909 i
.flags
[dupl
] = i
.flags
[dest
];
6918 i
.op
[dupl
] = i
.op
[dest
];
6919 i
.types
[dupl
] = i
.types
[dest
];
6920 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
6921 i
.flags
[dupl
] = i
.flags
[dest
];
6924 if (i
.tm
.opcode_modifier
.immext
)
6927 else if (i
.tm
.operand_types
[0].bitfield
.instance
== Accum
6928 && i
.tm
.operand_types
[0].bitfield
.xmmword
)
6932 for (j
= 1; j
< i
.operands
; j
++)
6934 i
.op
[j
- 1] = i
.op
[j
];
6935 i
.types
[j
- 1] = i
.types
[j
];
6937 /* We need to adjust fields in i.tm since they are used by
6938 build_modrm_byte. */
6939 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
6941 i
.flags
[j
- 1] = i
.flags
[j
];
6948 else if (i
.tm
.opcode_modifier
.implicitquadgroup
)
6950 unsigned int regnum
, first_reg_in_group
, last_reg_in_group
;
6952 /* The second operand must be {x,y,z}mmN, where N is a multiple of 4. */
6953 gas_assert (i
.operands
>= 2 && i
.types
[1].bitfield
.class == RegSIMD
);
6954 regnum
= register_number (i
.op
[1].regs
);
6955 first_reg_in_group
= regnum
& ~3;
6956 last_reg_in_group
= first_reg_in_group
+ 3;
6957 if (regnum
!= first_reg_in_group
)
6958 as_warn (_("source register `%s%s' implicitly denotes"
6959 " `%s%.3s%u' to `%s%.3s%u' source group in `%s'"),
6960 register_prefix
, i
.op
[1].regs
->reg_name
,
6961 register_prefix
, i
.op
[1].regs
->reg_name
, first_reg_in_group
,
6962 register_prefix
, i
.op
[1].regs
->reg_name
, last_reg_in_group
,
6965 else if (i
.tm
.opcode_modifier
.regkludge
)
6967 /* The imul $imm, %reg instruction is converted into
6968 imul $imm, %reg, %reg, and the clr %reg instruction
6969 is converted into xor %reg, %reg. */
6971 unsigned int first_reg_op
;
6973 if (operand_type_check (i
.types
[0], reg
))
6977 /* Pretend we saw the extra register operand. */
6978 gas_assert (i
.reg_operands
== 1
6979 && i
.op
[first_reg_op
+ 1].regs
== 0);
6980 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
6981 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
6986 if (i
.tm
.opcode_modifier
.modrm
)
6988 /* The opcode is completed (modulo i.tm.extension_opcode which
6989 must be put into the modrm byte). Now, we make the modrm and
6990 index base bytes based on all the info we've collected. */
6992 default_seg
= build_modrm_byte ();
6994 else if (i
.types
[0].bitfield
.class == SReg
)
6996 if (flag_code
!= CODE_64BIT
6997 ? i
.tm
.base_opcode
== POP_SEG_SHORT
6998 && i
.op
[0].regs
->reg_num
== 1
6999 : (i
.tm
.base_opcode
| 1) == POP_SEG386_SHORT
7000 && i
.op
[0].regs
->reg_num
< 4)
7002 as_bad (_("you can't `%s %s%s'"),
7003 i
.tm
.name
, register_prefix
, i
.op
[0].regs
->reg_name
);
7006 if ( i
.op
[0].regs
->reg_num
> 3 && i
.tm
.opcode_length
== 1 )
7008 i
.tm
.base_opcode
^= POP_SEG_SHORT
^ POP_SEG386_SHORT
;
7009 i
.tm
.opcode_length
= 2;
7011 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
7013 else if ((i
.tm
.base_opcode
& ~0x3) == MOV_AX_DISP32
)
7017 else if (i
.tm
.opcode_modifier
.isstring
)
7019 /* For the string instructions that allow a segment override
7020 on one of their operands, the default segment is ds. */
7023 else if (i
.tm
.opcode_modifier
.shortform
)
7025 /* The register or float register operand is in operand
7027 unsigned int op
= i
.tm
.operand_types
[0].bitfield
.class != Reg
;
7029 /* Register goes in low 3 bits of opcode. */
7030 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
7031 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
7033 if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
7035 /* Warn about some common errors, but press on regardless.
7036 The first case can be generated by gcc (<= 2.8.1). */
7037 if (i
.operands
== 2)
7039 /* Reversed arguments on faddp, fsubp, etc. */
7040 as_warn (_("translating to `%s %s%s,%s%s'"), i
.tm
.name
,
7041 register_prefix
, i
.op
[!intel_syntax
].regs
->reg_name
,
7042 register_prefix
, i
.op
[intel_syntax
].regs
->reg_name
);
7046 /* Extraneous `l' suffix on fp insn. */
7047 as_warn (_("translating to `%s %s%s'"), i
.tm
.name
,
7048 register_prefix
, i
.op
[0].regs
->reg_name
);
7053 if (i
.tm
.base_opcode
== 0x8d /* lea */
7056 as_warn (_("segment override on `%s' is ineffectual"), i
.tm
.name
);
7058 /* If a segment was explicitly specified, and the specified segment
7059 is not the default, use an opcode prefix to select it. If we
7060 never figured out what the default segment is, then default_seg
7061 will be zero at this point, and the specified segment prefix will
7063 if ((i
.seg
[0]) && (i
.seg
[0] != default_seg
))
7065 if (!add_prefix (i
.seg
[0]->seg_prefix
))
7071 static const seg_entry
*
7072 build_modrm_byte (void)
7074 const seg_entry
*default_seg
= 0;
7075 unsigned int source
, dest
;
7078 vex_3_sources
= i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
;
7081 unsigned int nds
, reg_slot
;
7084 dest
= i
.operands
- 1;
7087 /* There are 2 kinds of instructions:
7088 1. 5 operands: 4 register operands or 3 register operands
7089 plus 1 memory operand plus one Imm4 operand, VexXDS, and
7090 VexW0 or VexW1. The destination must be either XMM, YMM or
7092 2. 4 operands: 4 register operands or 3 register operands
7093 plus 1 memory operand, with VexXDS. */
7094 gas_assert ((i
.reg_operands
== 4
7095 || (i
.reg_operands
== 3 && i
.mem_operands
== 1))
7096 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
7097 && i
.tm
.opcode_modifier
.vexw
7098 && i
.tm
.operand_types
[dest
].bitfield
.class == RegSIMD
);
7100 /* If VexW1 is set, the first non-immediate operand is the source and
7101 the second non-immediate one is encoded in the immediate operand. */
7102 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
7104 source
= i
.imm_operands
;
7105 reg_slot
= i
.imm_operands
+ 1;
7109 source
= i
.imm_operands
+ 1;
7110 reg_slot
= i
.imm_operands
;
7113 if (i
.imm_operands
== 0)
7115 /* When there is no immediate operand, generate an 8bit
7116 immediate operand to encode the first operand. */
7117 exp
= &im_expressions
[i
.imm_operands
++];
7118 i
.op
[i
.operands
].imms
= exp
;
7119 i
.types
[i
.operands
] = imm8
;
7122 gas_assert (i
.tm
.operand_types
[reg_slot
].bitfield
.class == RegSIMD
);
7123 exp
->X_op
= O_constant
;
7124 exp
->X_add_number
= register_number (i
.op
[reg_slot
].regs
) << 4;
7125 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
7129 gas_assert (i
.imm_operands
== 1);
7130 gas_assert (fits_in_imm4 (i
.op
[0].imms
->X_add_number
));
7131 gas_assert (!i
.tm
.opcode_modifier
.immext
);
7133 /* Turn on Imm8 again so that output_imm will generate it. */
7134 i
.types
[0].bitfield
.imm8
= 1;
7136 gas_assert (i
.tm
.operand_types
[reg_slot
].bitfield
.class == RegSIMD
);
7137 i
.op
[0].imms
->X_add_number
7138 |= register_number (i
.op
[reg_slot
].regs
) << 4;
7139 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
7142 gas_assert (i
.tm
.operand_types
[nds
].bitfield
.class == RegSIMD
);
7143 i
.vex
.register_specifier
= i
.op
[nds
].regs
;
7148 /* i.reg_operands MUST be the number of real register operands;
7149 implicit registers do not count. If there are 3 register
7150 operands, it must be a instruction with VexNDS. For a
7151 instruction with VexNDD, the destination register is encoded
7152 in VEX prefix. If there are 4 register operands, it must be
7153 a instruction with VEX prefix and 3 sources. */
7154 if (i
.mem_operands
== 0
7155 && ((i
.reg_operands
== 2
7156 && i
.tm
.opcode_modifier
.vexvvvv
<= VEXXDS
)
7157 || (i
.reg_operands
== 3
7158 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
7159 || (i
.reg_operands
== 4 && vex_3_sources
)))
7167 /* When there are 3 operands, one of them may be immediate,
7168 which may be the first or the last operand. Otherwise,
7169 the first operand must be shift count register (cl) or it
7170 is an instruction with VexNDS. */
7171 gas_assert (i
.imm_operands
== 1
7172 || (i
.imm_operands
== 0
7173 && (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
7174 || (i
.types
[0].bitfield
.instance
== RegC
7175 && i
.types
[0].bitfield
.byte
))));
7176 if (operand_type_check (i
.types
[0], imm
)
7177 || (i
.types
[0].bitfield
.instance
== RegC
7178 && i
.types
[0].bitfield
.byte
))
7184 /* When there are 4 operands, the first two must be 8bit
7185 immediate operands. The source operand will be the 3rd
7188 For instructions with VexNDS, if the first operand
7189 an imm8, the source operand is the 2nd one. If the last
7190 operand is imm8, the source operand is the first one. */
7191 gas_assert ((i
.imm_operands
== 2
7192 && i
.types
[0].bitfield
.imm8
7193 && i
.types
[1].bitfield
.imm8
)
7194 || (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
7195 && i
.imm_operands
== 1
7196 && (i
.types
[0].bitfield
.imm8
7197 || i
.types
[i
.operands
- 1].bitfield
.imm8
7199 if (i
.imm_operands
== 2)
7203 if (i
.types
[0].bitfield
.imm8
)
7210 if (is_evex_encoding (&i
.tm
))
7212 /* For EVEX instructions, when there are 5 operands, the
7213 first one must be immediate operand. If the second one
7214 is immediate operand, the source operand is the 3th
7215 one. If the last one is immediate operand, the source
7216 operand is the 2nd one. */
7217 gas_assert (i
.imm_operands
== 2
7218 && i
.tm
.opcode_modifier
.sae
7219 && operand_type_check (i
.types
[0], imm
));
7220 if (operand_type_check (i
.types
[1], imm
))
7222 else if (operand_type_check (i
.types
[4], imm
))
7236 /* RC/SAE operand could be between DEST and SRC. That happens
7237 when one operand is GPR and the other one is XMM/YMM/ZMM
7239 if (i
.rounding
&& i
.rounding
->operand
== (int) dest
)
7242 if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
7244 /* For instructions with VexNDS, the register-only source
7245 operand must be a 32/64bit integer, XMM, YMM, ZMM, or mask
7246 register. It is encoded in VEX prefix. */
7248 i386_operand_type op
;
7251 /* Check register-only source operand when two source
7252 operands are swapped. */
7253 if (!i
.tm
.operand_types
[source
].bitfield
.baseindex
7254 && i
.tm
.operand_types
[dest
].bitfield
.baseindex
)
7262 op
= i
.tm
.operand_types
[vvvv
];
7263 if ((dest
+ 1) >= i
.operands
7264 || ((op
.bitfield
.class != Reg
7265 || (!op
.bitfield
.dword
&& !op
.bitfield
.qword
))
7266 && op
.bitfield
.class != RegSIMD
7267 && !operand_type_equal (&op
, ®mask
)))
7269 i
.vex
.register_specifier
= i
.op
[vvvv
].regs
;
7275 /* One of the register operands will be encoded in the i.rm.reg
7276 field, the other in the combined i.rm.mode and i.rm.regmem
7277 fields. If no form of this instruction supports a memory
7278 destination operand, then we assume the source operand may
7279 sometimes be a memory operand and so we need to store the
7280 destination in the i.rm.reg field. */
7281 if (!i
.tm
.opcode_modifier
.regmem
7282 && operand_type_check (i
.tm
.operand_types
[dest
], anymem
) == 0)
7284 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
7285 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
7286 if (i
.op
[dest
].regs
->reg_type
.bitfield
.class == RegMMX
7287 || i
.op
[source
].regs
->reg_type
.bitfield
.class == RegMMX
)
7288 i
.has_regmmx
= TRUE
;
7289 else if (i
.op
[dest
].regs
->reg_type
.bitfield
.class == RegSIMD
7290 || i
.op
[source
].regs
->reg_type
.bitfield
.class == RegSIMD
)
7292 if (i
.types
[dest
].bitfield
.zmmword
7293 || i
.types
[source
].bitfield
.zmmword
)
7294 i
.has_regzmm
= TRUE
;
7295 else if (i
.types
[dest
].bitfield
.ymmword
7296 || i
.types
[source
].bitfield
.ymmword
)
7297 i
.has_regymm
= TRUE
;
7299 i
.has_regxmm
= TRUE
;
7301 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
7303 if ((i
.op
[dest
].regs
->reg_flags
& RegVRex
) != 0)
7305 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
7307 if ((i
.op
[source
].regs
->reg_flags
& RegVRex
) != 0)
7312 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
7313 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
7314 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
7316 if ((i
.op
[dest
].regs
->reg_flags
& RegVRex
) != 0)
7318 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
7320 if ((i
.op
[source
].regs
->reg_flags
& RegVRex
) != 0)
7323 if (flag_code
!= CODE_64BIT
&& (i
.rex
& REX_R
))
7325 if (i
.types
[!i
.tm
.opcode_modifier
.regmem
].bitfield
.class != RegCR
)
7328 add_prefix (LOCK_PREFIX_OPCODE
);
7332 { /* If it's not 2 reg operands... */
7337 unsigned int fake_zero_displacement
= 0;
7340 for (op
= 0; op
< i
.operands
; op
++)
7341 if (i
.flags
[op
] & Operand_Mem
)
7343 gas_assert (op
< i
.operands
);
7345 if (i
.tm
.opcode_modifier
.vecsib
)
7347 if (i
.index_reg
->reg_num
== RegIZ
)
7350 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
7353 i
.sib
.base
= NO_BASE_REGISTER
;
7354 i
.sib
.scale
= i
.log2_scale_factor
;
7355 i
.types
[op
].bitfield
.disp8
= 0;
7356 i
.types
[op
].bitfield
.disp16
= 0;
7357 i
.types
[op
].bitfield
.disp64
= 0;
7358 if (flag_code
!= CODE_64BIT
|| i
.prefix
[ADDR_PREFIX
])
7360 /* Must be 32 bit */
7361 i
.types
[op
].bitfield
.disp32
= 1;
7362 i
.types
[op
].bitfield
.disp32s
= 0;
7366 i
.types
[op
].bitfield
.disp32
= 0;
7367 i
.types
[op
].bitfield
.disp32s
= 1;
7370 i
.sib
.index
= i
.index_reg
->reg_num
;
7371 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
7373 if ((i
.index_reg
->reg_flags
& RegVRex
) != 0)
7379 if (i
.base_reg
== 0)
7382 if (!i
.disp_operands
)
7383 fake_zero_displacement
= 1;
7384 if (i
.index_reg
== 0)
7386 i386_operand_type newdisp
;
7388 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
7389 /* Operand is just <disp> */
7390 if (flag_code
== CODE_64BIT
)
7392 /* 64bit mode overwrites the 32bit absolute
7393 addressing by RIP relative addressing and
7394 absolute addressing is encoded by one of the
7395 redundant SIB forms. */
7396 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
7397 i
.sib
.base
= NO_BASE_REGISTER
;
7398 i
.sib
.index
= NO_INDEX_REGISTER
;
7399 newdisp
= (!i
.prefix
[ADDR_PREFIX
] ? disp32s
: disp32
);
7401 else if ((flag_code
== CODE_16BIT
)
7402 ^ (i
.prefix
[ADDR_PREFIX
] != 0))
7404 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
7409 i
.rm
.regmem
= NO_BASE_REGISTER
;
7412 i
.types
[op
] = operand_type_and_not (i
.types
[op
], anydisp
);
7413 i
.types
[op
] = operand_type_or (i
.types
[op
], newdisp
);
7415 else if (!i
.tm
.opcode_modifier
.vecsib
)
7417 /* !i.base_reg && i.index_reg */
7418 if (i
.index_reg
->reg_num
== RegIZ
)
7419 i
.sib
.index
= NO_INDEX_REGISTER
;
7421 i
.sib
.index
= i
.index_reg
->reg_num
;
7422 i
.sib
.base
= NO_BASE_REGISTER
;
7423 i
.sib
.scale
= i
.log2_scale_factor
;
7424 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
7425 i
.types
[op
].bitfield
.disp8
= 0;
7426 i
.types
[op
].bitfield
.disp16
= 0;
7427 i
.types
[op
].bitfield
.disp64
= 0;
7428 if (flag_code
!= CODE_64BIT
|| i
.prefix
[ADDR_PREFIX
])
7430 /* Must be 32 bit */
7431 i
.types
[op
].bitfield
.disp32
= 1;
7432 i
.types
[op
].bitfield
.disp32s
= 0;
7436 i
.types
[op
].bitfield
.disp32
= 0;
7437 i
.types
[op
].bitfield
.disp32s
= 1;
7439 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
7443 /* RIP addressing for 64bit mode. */
7444 else if (i
.base_reg
->reg_num
== RegIP
)
7446 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
7447 i
.rm
.regmem
= NO_BASE_REGISTER
;
7448 i
.types
[op
].bitfield
.disp8
= 0;
7449 i
.types
[op
].bitfield
.disp16
= 0;
7450 i
.types
[op
].bitfield
.disp32
= 0;
7451 i
.types
[op
].bitfield
.disp32s
= 1;
7452 i
.types
[op
].bitfield
.disp64
= 0;
7453 i
.flags
[op
] |= Operand_PCrel
;
7454 if (! i
.disp_operands
)
7455 fake_zero_displacement
= 1;
7457 else if (i
.base_reg
->reg_type
.bitfield
.word
)
7459 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
7460 switch (i
.base_reg
->reg_num
)
7463 if (i
.index_reg
== 0)
7465 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
7466 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
7470 if (i
.index_reg
== 0)
7473 if (operand_type_check (i
.types
[op
], disp
) == 0)
7475 /* fake (%bp) into 0(%bp) */
7476 i
.types
[op
].bitfield
.disp8
= 1;
7477 fake_zero_displacement
= 1;
7480 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
7481 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
7483 default: /* (%si) -> 4 or (%di) -> 5 */
7484 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
7486 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
7488 else /* i.base_reg and 32/64 bit mode */
7490 if (flag_code
== CODE_64BIT
7491 && operand_type_check (i
.types
[op
], disp
))
7493 i
.types
[op
].bitfield
.disp16
= 0;
7494 i
.types
[op
].bitfield
.disp64
= 0;
7495 if (i
.prefix
[ADDR_PREFIX
] == 0)
7497 i
.types
[op
].bitfield
.disp32
= 0;
7498 i
.types
[op
].bitfield
.disp32s
= 1;
7502 i
.types
[op
].bitfield
.disp32
= 1;
7503 i
.types
[op
].bitfield
.disp32s
= 0;
7507 if (!i
.tm
.opcode_modifier
.vecsib
)
7508 i
.rm
.regmem
= i
.base_reg
->reg_num
;
7509 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
7511 i
.sib
.base
= i
.base_reg
->reg_num
;
7512 /* x86-64 ignores REX prefix bit here to avoid decoder
7514 if (!(i
.base_reg
->reg_flags
& RegRex
)
7515 && (i
.base_reg
->reg_num
== EBP_REG_NUM
7516 || i
.base_reg
->reg_num
== ESP_REG_NUM
))
7518 if (i
.base_reg
->reg_num
== 5 && i
.disp_operands
== 0)
7520 fake_zero_displacement
= 1;
7521 i
.types
[op
].bitfield
.disp8
= 1;
7523 i
.sib
.scale
= i
.log2_scale_factor
;
7524 if (i
.index_reg
== 0)
7526 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
7527 /* <disp>(%esp) becomes two byte modrm with no index
7528 register. We've already stored the code for esp
7529 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
7530 Any base register besides %esp will not use the
7531 extra modrm byte. */
7532 i
.sib
.index
= NO_INDEX_REGISTER
;
7534 else if (!i
.tm
.opcode_modifier
.vecsib
)
7536 if (i
.index_reg
->reg_num
== RegIZ
)
7537 i
.sib
.index
= NO_INDEX_REGISTER
;
7539 i
.sib
.index
= i
.index_reg
->reg_num
;
7540 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
7541 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
7546 && (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
7547 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
))
7551 if (!fake_zero_displacement
7555 fake_zero_displacement
= 1;
7556 if (i
.disp_encoding
== disp_encoding_8bit
)
7557 i
.types
[op
].bitfield
.disp8
= 1;
7559 i
.types
[op
].bitfield
.disp32
= 1;
7561 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
7565 if (fake_zero_displacement
)
7567 /* Fakes a zero displacement assuming that i.types[op]
7568 holds the correct displacement size. */
7571 gas_assert (i
.op
[op
].disps
== 0);
7572 exp
= &disp_expressions
[i
.disp_operands
++];
7573 i
.op
[op
].disps
= exp
;
7574 exp
->X_op
= O_constant
;
7575 exp
->X_add_number
= 0;
7576 exp
->X_add_symbol
= (symbolS
*) 0;
7577 exp
->X_op_symbol
= (symbolS
*) 0;
7585 if (i
.tm
.opcode_modifier
.vexsources
== XOP2SOURCES
)
7587 if (operand_type_check (i
.types
[0], imm
))
7588 i
.vex
.register_specifier
= NULL
;
7591 /* VEX.vvvv encodes one of the sources when the first
7592 operand is not an immediate. */
7593 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
7594 i
.vex
.register_specifier
= i
.op
[0].regs
;
7596 i
.vex
.register_specifier
= i
.op
[1].regs
;
7599 /* Destination is a XMM register encoded in the ModRM.reg
7601 i
.rm
.reg
= i
.op
[2].regs
->reg_num
;
7602 if ((i
.op
[2].regs
->reg_flags
& RegRex
) != 0)
7605 /* ModRM.rm and VEX.B encodes the other source. */
7606 if (!i
.mem_operands
)
7610 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
7611 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
7613 i
.rm
.regmem
= i
.op
[0].regs
->reg_num
;
7615 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
7619 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXLWP
)
7621 i
.vex
.register_specifier
= i
.op
[2].regs
;
7622 if (!i
.mem_operands
)
7625 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
7626 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
7630 /* Fill in i.rm.reg or i.rm.regmem field with register operand
7631 (if any) based on i.tm.extension_opcode. Again, we must be
7632 careful to make sure that segment/control/debug/test/MMX
7633 registers are coded into the i.rm.reg field. */
7634 else if (i
.reg_operands
)
7637 unsigned int vex_reg
= ~0;
7639 for (op
= 0; op
< i
.operands
; op
++)
7641 if (i
.types
[op
].bitfield
.class == Reg
7642 || i
.types
[op
].bitfield
.class == RegBND
7643 || i
.types
[op
].bitfield
.class == RegMask
7644 || i
.types
[op
].bitfield
.class == SReg
7645 || i
.types
[op
].bitfield
.class == RegCR
7646 || i
.types
[op
].bitfield
.class == RegDR
7647 || i
.types
[op
].bitfield
.class == RegTR
)
7649 if (i
.types
[op
].bitfield
.class == RegSIMD
)
7651 if (i
.types
[op
].bitfield
.zmmword
)
7652 i
.has_regzmm
= TRUE
;
7653 else if (i
.types
[op
].bitfield
.ymmword
)
7654 i
.has_regymm
= TRUE
;
7656 i
.has_regxmm
= TRUE
;
7659 if (i
.types
[op
].bitfield
.class == RegMMX
)
7661 i
.has_regmmx
= TRUE
;
7668 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
7670 /* For instructions with VexNDS, the register-only
7671 source operand is encoded in VEX prefix. */
7672 gas_assert (mem
!= (unsigned int) ~0);
7677 gas_assert (op
< i
.operands
);
7681 /* Check register-only source operand when two source
7682 operands are swapped. */
7683 if (!i
.tm
.operand_types
[op
].bitfield
.baseindex
7684 && i
.tm
.operand_types
[op
+ 1].bitfield
.baseindex
)
7688 gas_assert (mem
== (vex_reg
+ 1)
7689 && op
< i
.operands
);
7694 gas_assert (vex_reg
< i
.operands
);
7698 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXNDD
)
7700 /* For instructions with VexNDD, the register destination
7701 is encoded in VEX prefix. */
7702 if (i
.mem_operands
== 0)
7704 /* There is no memory operand. */
7705 gas_assert ((op
+ 2) == i
.operands
);
7710 /* There are only 2 non-immediate operands. */
7711 gas_assert (op
< i
.imm_operands
+ 2
7712 && i
.operands
== i
.imm_operands
+ 2);
7713 vex_reg
= i
.imm_operands
+ 1;
7717 gas_assert (op
< i
.operands
);
7719 if (vex_reg
!= (unsigned int) ~0)
7721 i386_operand_type
*type
= &i
.tm
.operand_types
[vex_reg
];
7723 if ((type
->bitfield
.class != Reg
7724 || (!type
->bitfield
.dword
&& !type
->bitfield
.qword
))
7725 && type
->bitfield
.class != RegSIMD
7726 && !operand_type_equal (type
, ®mask
))
7729 i
.vex
.register_specifier
= i
.op
[vex_reg
].regs
;
7732 /* Don't set OP operand twice. */
7735 /* If there is an extension opcode to put here, the
7736 register number must be put into the regmem field. */
7737 if (i
.tm
.extension_opcode
!= None
)
7739 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
7740 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
7742 if ((i
.op
[op
].regs
->reg_flags
& RegVRex
) != 0)
7747 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
7748 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
7750 if ((i
.op
[op
].regs
->reg_flags
& RegVRex
) != 0)
7755 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
7756 must set it to 3 to indicate this is a register operand
7757 in the regmem field. */
7758 if (!i
.mem_operands
)
7762 /* Fill in i.rm.reg field with extension opcode (if any). */
7763 if (i
.tm
.extension_opcode
!= None
)
7764 i
.rm
.reg
= i
.tm
.extension_opcode
;
7770 output_branch (void)
7776 relax_substateT subtype
;
7780 code16
= flag_code
== CODE_16BIT
? CODE16
: 0;
7781 size
= i
.disp_encoding
== disp_encoding_32bit
? BIG
: SMALL
;
7784 if (i
.prefix
[DATA_PREFIX
] != 0)
7790 /* Pentium4 branch hints. */
7791 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
7792 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
7797 if (i
.prefix
[REX_PREFIX
] != 0)
7803 /* BND prefixed jump. */
7804 if (i
.prefix
[BND_PREFIX
] != 0)
7806 FRAG_APPEND_1_CHAR (i
.prefix
[BND_PREFIX
]);
7810 if (i
.prefixes
!= 0 && !intel_syntax
)
7811 as_warn (_("skipping prefixes on this instruction"));
7813 /* It's always a symbol; End frag & setup for relax.
7814 Make sure there is enough room in this frag for the largest
7815 instruction we may generate in md_convert_frag. This is 2
7816 bytes for the opcode and room for the prefix and largest
7818 frag_grow (prefix
+ 2 + 4);
7819 /* Prefix and 1 opcode byte go in fr_fix. */
7820 p
= frag_more (prefix
+ 1);
7821 if (i
.prefix
[DATA_PREFIX
] != 0)
7822 *p
++ = DATA_PREFIX_OPCODE
;
7823 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
7824 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
7825 *p
++ = i
.prefix
[SEG_PREFIX
];
7826 if (i
.prefix
[REX_PREFIX
] != 0)
7827 *p
++ = i
.prefix
[REX_PREFIX
];
7828 *p
= i
.tm
.base_opcode
;
7830 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
7831 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, size
);
7832 else if (cpu_arch_flags
.bitfield
.cpui386
)
7833 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, size
);
7835 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, size
);
7838 sym
= i
.op
[0].disps
->X_add_symbol
;
7839 off
= i
.op
[0].disps
->X_add_number
;
7841 if (i
.op
[0].disps
->X_op
!= O_constant
7842 && i
.op
[0].disps
->X_op
!= O_symbol
)
7844 /* Handle complex expressions. */
7845 sym
= make_expr_symbol (i
.op
[0].disps
);
7849 /* 1 possible extra opcode + 4 byte displacement go in var part.
7850 Pass reloc in fr_var. */
7851 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
7854 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7855 /* Return TRUE iff PLT32 relocation should be used for branching to
7859 need_plt32_p (symbolS
*s
)
7861 /* PLT32 relocation is ELF only. */
7866 /* Don't emit PLT32 relocation on Solaris: neither native linker nor
7867 krtld support it. */
7871 /* Since there is no need to prepare for PLT branch on x86-64, we
7872 can generate R_X86_64_PLT32, instead of R_X86_64_PC32, which can
7873 be used as a marker for 32-bit PC-relative branches. */
7877 /* Weak or undefined symbol need PLT32 relocation. */
7878 if (S_IS_WEAK (s
) || !S_IS_DEFINED (s
))
7881 /* Non-global symbol doesn't need PLT32 relocation. */
7882 if (! S_IS_EXTERNAL (s
))
7885 /* Other global symbols need PLT32 relocation. NB: Symbol with
7886 non-default visibilities are treated as normal global symbol
7887 so that PLT32 relocation can be used as a marker for 32-bit
7888 PC-relative branches. It is useful for linker relaxation. */
7899 bfd_reloc_code_real_type jump_reloc
= i
.reloc
[0];
7901 if (i
.tm
.opcode_modifier
.jumpbyte
)
7903 /* This is a loop or jecxz type instruction. */
7905 if (i
.prefix
[ADDR_PREFIX
] != 0)
7907 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
7910 /* Pentium4 branch hints. */
7911 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
7912 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
7914 FRAG_APPEND_1_CHAR (i
.prefix
[SEG_PREFIX
]);
7923 if (flag_code
== CODE_16BIT
)
7926 if (i
.prefix
[DATA_PREFIX
] != 0)
7928 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
7938 if (i
.prefix
[REX_PREFIX
] != 0)
7940 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
7944 /* BND prefixed jump. */
7945 if (i
.prefix
[BND_PREFIX
] != 0)
7947 FRAG_APPEND_1_CHAR (i
.prefix
[BND_PREFIX
]);
7951 if (i
.prefixes
!= 0 && !intel_syntax
)
7952 as_warn (_("skipping prefixes on this instruction"));
7954 p
= frag_more (i
.tm
.opcode_length
+ size
);
7955 switch (i
.tm
.opcode_length
)
7958 *p
++ = i
.tm
.base_opcode
>> 8;
7961 *p
++ = i
.tm
.base_opcode
;
7967 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7969 && jump_reloc
== NO_RELOC
7970 && need_plt32_p (i
.op
[0].disps
->X_add_symbol
))
7971 jump_reloc
= BFD_RELOC_X86_64_PLT32
;
7974 jump_reloc
= reloc (size
, 1, 1, jump_reloc
);
7976 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
7977 i
.op
[0].disps
, 1, jump_reloc
);
7979 /* All jumps handled here are signed, but don't use a signed limit
7980 check for 32 and 16 bit jumps as we want to allow wrap around at
7981 4G and 64k respectively. */
7983 fixP
->fx_signed
= 1;
7987 output_interseg_jump (void)
7995 if (flag_code
== CODE_16BIT
)
7999 if (i
.prefix
[DATA_PREFIX
] != 0)
8005 if (i
.prefix
[REX_PREFIX
] != 0)
8015 if (i
.prefixes
!= 0 && !intel_syntax
)
8016 as_warn (_("skipping prefixes on this instruction"));
8018 /* 1 opcode; 2 segment; offset */
8019 p
= frag_more (prefix
+ 1 + 2 + size
);
8021 if (i
.prefix
[DATA_PREFIX
] != 0)
8022 *p
++ = DATA_PREFIX_OPCODE
;
8024 if (i
.prefix
[REX_PREFIX
] != 0)
8025 *p
++ = i
.prefix
[REX_PREFIX
];
8027 *p
++ = i
.tm
.base_opcode
;
8028 if (i
.op
[1].imms
->X_op
== O_constant
)
8030 offsetT n
= i
.op
[1].imms
->X_add_number
;
8033 && !fits_in_unsigned_word (n
)
8034 && !fits_in_signed_word (n
))
8036 as_bad (_("16-bit jump out of range"));
8039 md_number_to_chars (p
, n
, size
);
8042 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
8043 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
8044 if (i
.op
[0].imms
->X_op
!= O_constant
)
8045 as_bad (_("can't handle non absolute segment in `%s'"),
8047 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
8050 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8055 asection
*seg
= now_seg
;
8056 subsegT subseg
= now_subseg
;
8058 unsigned int alignment
, align_size_1
;
8059 unsigned int isa_1_descsz
, feature_2_descsz
, descsz
;
8060 unsigned int isa_1_descsz_raw
, feature_2_descsz_raw
;
8061 unsigned int padding
;
8063 if (!IS_ELF
|| !x86_used_note
)
8066 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_X86
;
8068 /* The .note.gnu.property section layout:
8070 Field Length Contents
8073 n_descsz 4 The note descriptor size
8074 n_type 4 NT_GNU_PROPERTY_TYPE_0
8076 n_desc n_descsz The program property array
8080 /* Create the .note.gnu.property section. */
8081 sec
= subseg_new (NOTE_GNU_PROPERTY_SECTION_NAME
, 0);
8082 bfd_set_section_flags (sec
,
8089 if (get_elf_backend_data (stdoutput
)->s
->elfclass
== ELFCLASS64
)
8100 bfd_set_section_alignment (sec
, alignment
);
8101 elf_section_type (sec
) = SHT_NOTE
;
8103 /* GNU_PROPERTY_X86_ISA_1_USED: 4-byte type + 4-byte data size
8105 isa_1_descsz_raw
= 4 + 4 + 4;
8106 /* Align GNU_PROPERTY_X86_ISA_1_USED. */
8107 isa_1_descsz
= (isa_1_descsz_raw
+ align_size_1
) & ~align_size_1
;
8109 feature_2_descsz_raw
= isa_1_descsz
;
8110 /* GNU_PROPERTY_X86_FEATURE_2_USED: 4-byte type + 4-byte data size
8112 feature_2_descsz_raw
+= 4 + 4 + 4;
8113 /* Align GNU_PROPERTY_X86_FEATURE_2_USED. */
8114 feature_2_descsz
= ((feature_2_descsz_raw
+ align_size_1
)
8117 descsz
= feature_2_descsz
;
8118 /* Section size: n_namsz + n_descsz + n_type + n_name + n_descsz. */
8119 p
= frag_more (4 + 4 + 4 + 4 + descsz
);
8121 /* Write n_namsz. */
8122 md_number_to_chars (p
, (valueT
) 4, 4);
8124 /* Write n_descsz. */
8125 md_number_to_chars (p
+ 4, (valueT
) descsz
, 4);
8128 md_number_to_chars (p
+ 4 * 2, (valueT
) NT_GNU_PROPERTY_TYPE_0
, 4);
8131 memcpy (p
+ 4 * 3, "GNU", 4);
8133 /* Write 4-byte type. */
8134 md_number_to_chars (p
+ 4 * 4,
8135 (valueT
) GNU_PROPERTY_X86_ISA_1_USED
, 4);
8137 /* Write 4-byte data size. */
8138 md_number_to_chars (p
+ 4 * 5, (valueT
) 4, 4);
8140 /* Write 4-byte data. */
8141 md_number_to_chars (p
+ 4 * 6, (valueT
) x86_isa_1_used
, 4);
8143 /* Zero out paddings. */
8144 padding
= isa_1_descsz
- isa_1_descsz_raw
;
8146 memset (p
+ 4 * 7, 0, padding
);
8148 /* Write 4-byte type. */
8149 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 4,
8150 (valueT
) GNU_PROPERTY_X86_FEATURE_2_USED
, 4);
8152 /* Write 4-byte data size. */
8153 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 5, (valueT
) 4, 4);
8155 /* Write 4-byte data. */
8156 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 6,
8157 (valueT
) x86_feature_2_used
, 4);
8159 /* Zero out paddings. */
8160 padding
= feature_2_descsz
- feature_2_descsz_raw
;
8162 memset (p
+ isa_1_descsz
+ 4 * 7, 0, padding
);
8164 /* We probably can't restore the current segment, for there likely
8167 subseg_set (seg
, subseg
);
8172 encoding_length (const fragS
*start_frag
, offsetT start_off
,
8173 const char *frag_now_ptr
)
8175 unsigned int len
= 0;
8177 if (start_frag
!= frag_now
)
8179 const fragS
*fr
= start_frag
;
8184 } while (fr
&& fr
!= frag_now
);
8187 return len
- start_off
+ (frag_now_ptr
- frag_now
->fr_literal
);
8193 fragS
*insn_start_frag
;
8194 offsetT insn_start_off
;
8196 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8197 if (IS_ELF
&& x86_used_note
)
8199 if (i
.tm
.cpu_flags
.bitfield
.cpucmov
)
8200 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_CMOV
;
8201 if (i
.tm
.cpu_flags
.bitfield
.cpusse
)
8202 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE
;
8203 if (i
.tm
.cpu_flags
.bitfield
.cpusse2
)
8204 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE2
;
8205 if (i
.tm
.cpu_flags
.bitfield
.cpusse3
)
8206 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE3
;
8207 if (i
.tm
.cpu_flags
.bitfield
.cpussse3
)
8208 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSSE3
;
8209 if (i
.tm
.cpu_flags
.bitfield
.cpusse4_1
)
8210 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE4_1
;
8211 if (i
.tm
.cpu_flags
.bitfield
.cpusse4_2
)
8212 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE4_2
;
8213 if (i
.tm
.cpu_flags
.bitfield
.cpuavx
)
8214 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX
;
8215 if (i
.tm
.cpu_flags
.bitfield
.cpuavx2
)
8216 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX2
;
8217 if (i
.tm
.cpu_flags
.bitfield
.cpufma
)
8218 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_FMA
;
8219 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512f
)
8220 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512F
;
8221 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512cd
)
8222 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512CD
;
8223 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512er
)
8224 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512ER
;
8225 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512pf
)
8226 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512PF
;
8227 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512vl
)
8228 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512VL
;
8229 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512dq
)
8230 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512DQ
;
8231 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512bw
)
8232 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512BW
;
8233 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_4fmaps
)
8234 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_4FMAPS
;
8235 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_4vnniw
)
8236 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_4VNNIW
;
8237 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_bitalg
)
8238 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_BITALG
;
8239 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512ifma
)
8240 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_IFMA
;
8241 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512vbmi
)
8242 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_VBMI
;
8243 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_vbmi2
)
8244 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_VBMI2
;
8245 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_vnni
)
8246 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_VNNI
;
8247 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_bf16
)
8248 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_BF16
;
8250 if (i
.tm
.cpu_flags
.bitfield
.cpu8087
8251 || i
.tm
.cpu_flags
.bitfield
.cpu287
8252 || i
.tm
.cpu_flags
.bitfield
.cpu387
8253 || i
.tm
.cpu_flags
.bitfield
.cpu687
8254 || i
.tm
.cpu_flags
.bitfield
.cpufisttp
)
8255 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_X87
;
8256 /* Don't set GNU_PROPERTY_X86_FEATURE_2_MMX for prefetchtXXX nor
8257 Xfence instructions. */
8258 if (i
.tm
.base_opcode
!= 0xf18
8259 && i
.tm
.base_opcode
!= 0xf0d
8260 && i
.tm
.base_opcode
!= 0xfaef8
8262 || i
.tm
.cpu_flags
.bitfield
.cpummx
8263 || i
.tm
.cpu_flags
.bitfield
.cpua3dnow
8264 || i
.tm
.cpu_flags
.bitfield
.cpua3dnowa
))
8265 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_MMX
;
8267 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XMM
;
8269 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_YMM
;
8271 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_ZMM
;
8272 if (i
.tm
.cpu_flags
.bitfield
.cpufxsr
)
8273 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_FXSR
;
8274 if (i
.tm
.cpu_flags
.bitfield
.cpuxsave
)
8275 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVE
;
8276 if (i
.tm
.cpu_flags
.bitfield
.cpuxsaveopt
)
8277 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVEOPT
;
8278 if (i
.tm
.cpu_flags
.bitfield
.cpuxsavec
)
8279 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVEC
;
8283 /* Tie dwarf2 debug info to the address at the start of the insn.
8284 We can't do this after the insn has been output as the current
8285 frag may have been closed off. eg. by frag_var. */
8286 dwarf2_emit_insn (0);
8288 insn_start_frag
= frag_now
;
8289 insn_start_off
= frag_now_fix ();
8292 if (i
.tm
.opcode_modifier
.jump
)
8294 else if (i
.tm
.opcode_modifier
.jumpbyte
8295 || i
.tm
.opcode_modifier
.jumpdword
)
8297 else if (i
.tm
.opcode_modifier
.jumpintersegment
)
8298 output_interseg_jump ();
8301 /* Output normal instructions here. */
8305 unsigned int prefix
;
8308 && (i
.tm
.base_opcode
== 0xfaee8
8309 || i
.tm
.base_opcode
== 0xfaef0
8310 || i
.tm
.base_opcode
== 0xfaef8))
8312 /* Encode lfence, mfence, and sfence as
8313 f0 83 04 24 00 lock addl $0x0, (%{re}sp). */
8314 offsetT val
= 0x240483f0ULL
;
8316 md_number_to_chars (p
, val
, 5);
8320 /* Some processors fail on LOCK prefix. This options makes
8321 assembler ignore LOCK prefix and serves as a workaround. */
8322 if (omit_lock_prefix
)
8324 if (i
.tm
.base_opcode
== LOCK_PREFIX_OPCODE
)
8326 i
.prefix
[LOCK_PREFIX
] = 0;
8329 /* Since the VEX/EVEX prefix contains the implicit prefix, we
8330 don't need the explicit prefix. */
8331 if (!i
.tm
.opcode_modifier
.vex
&& !i
.tm
.opcode_modifier
.evex
)
8333 switch (i
.tm
.opcode_length
)
8336 if (i
.tm
.base_opcode
& 0xff000000)
8338 prefix
= (i
.tm
.base_opcode
>> 24) & 0xff;
8339 if (!i
.tm
.cpu_flags
.bitfield
.cpupadlock
8340 || prefix
!= REPE_PREFIX_OPCODE
8341 || (i
.prefix
[REP_PREFIX
] != REPE_PREFIX_OPCODE
))
8342 add_prefix (prefix
);
8346 if ((i
.tm
.base_opcode
& 0xff0000) != 0)
8348 prefix
= (i
.tm
.base_opcode
>> 16) & 0xff;
8349 add_prefix (prefix
);
8355 /* Check for pseudo prefixes. */
8356 as_bad_where (insn_start_frag
->fr_file
,
8357 insn_start_frag
->fr_line
,
8358 _("pseudo prefix without instruction"));
8364 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
8365 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
8366 R_X86_64_GOTTPOFF relocation so that linker can safely
8367 perform IE->LE optimization. */
8368 if (x86_elf_abi
== X86_64_X32_ABI
8370 && i
.reloc
[0] == BFD_RELOC_X86_64_GOTTPOFF
8371 && i
.prefix
[REX_PREFIX
] == 0)
8372 add_prefix (REX_OPCODE
);
8375 /* The prefix bytes. */
8376 for (j
= ARRAY_SIZE (i
.prefix
), q
= i
.prefix
; j
> 0; j
--, q
++)
8378 FRAG_APPEND_1_CHAR (*q
);
8382 for (j
= 0, q
= i
.prefix
; j
< ARRAY_SIZE (i
.prefix
); j
++, q
++)
8387 /* REX byte is encoded in VEX prefix. */
8391 FRAG_APPEND_1_CHAR (*q
);
8394 /* There should be no other prefixes for instructions
8399 /* For EVEX instructions i.vrex should become 0 after
8400 build_evex_prefix. For VEX instructions upper 16 registers
8401 aren't available, so VREX should be 0. */
8404 /* Now the VEX prefix. */
8405 p
= frag_more (i
.vex
.length
);
8406 for (j
= 0; j
< i
.vex
.length
; j
++)
8407 p
[j
] = i
.vex
.bytes
[j
];
8410 /* Now the opcode; be careful about word order here! */
8411 if (i
.tm
.opcode_length
== 1)
8413 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
8417 switch (i
.tm
.opcode_length
)
8421 *p
++ = (i
.tm
.base_opcode
>> 24) & 0xff;
8422 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
8426 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
8436 /* Put out high byte first: can't use md_number_to_chars! */
8437 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
8438 *p
= i
.tm
.base_opcode
& 0xff;
8441 /* Now the modrm byte and sib byte (if present). */
8442 if (i
.tm
.opcode_modifier
.modrm
)
8444 FRAG_APPEND_1_CHAR ((i
.rm
.regmem
<< 0
8447 /* If i.rm.regmem == ESP (4)
8448 && i.rm.mode != (Register mode)
8450 ==> need second modrm byte. */
8451 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
8453 && !(i
.base_reg
&& i
.base_reg
->reg_type
.bitfield
.word
))
8454 FRAG_APPEND_1_CHAR ((i
.sib
.base
<< 0
8456 | i
.sib
.scale
<< 6));
8459 if (i
.disp_operands
)
8460 output_disp (insn_start_frag
, insn_start_off
);
8463 output_imm (insn_start_frag
, insn_start_off
);
8466 * frag_now_fix () returning plain abs_section_offset when we're in the
8467 * absolute section, and abs_section_offset not getting updated as data
8468 * gets added to the frag breaks the logic below.
8470 if (now_seg
!= absolute_section
)
8472 j
= encoding_length (insn_start_frag
, insn_start_off
, frag_more (0));
8474 as_warn (_("instruction length of %u bytes exceeds the limit of 15"),
8482 pi ("" /*line*/, &i
);
8484 #endif /* DEBUG386 */
8487 /* Return the size of the displacement operand N. */
8490 disp_size (unsigned int n
)
8494 if (i
.types
[n
].bitfield
.disp64
)
8496 else if (i
.types
[n
].bitfield
.disp8
)
8498 else if (i
.types
[n
].bitfield
.disp16
)
8503 /* Return the size of the immediate operand N. */
8506 imm_size (unsigned int n
)
8509 if (i
.types
[n
].bitfield
.imm64
)
8511 else if (i
.types
[n
].bitfield
.imm8
|| i
.types
[n
].bitfield
.imm8s
)
8513 else if (i
.types
[n
].bitfield
.imm16
)
8519 output_disp (fragS
*insn_start_frag
, offsetT insn_start_off
)
8524 for (n
= 0; n
< i
.operands
; n
++)
8526 if (operand_type_check (i
.types
[n
], disp
))
8528 if (i
.op
[n
].disps
->X_op
== O_constant
)
8530 int size
= disp_size (n
);
8531 offsetT val
= i
.op
[n
].disps
->X_add_number
;
8533 val
= offset_in_range (val
>> (size
== 1 ? i
.memshift
: 0),
8535 p
= frag_more (size
);
8536 md_number_to_chars (p
, val
, size
);
8540 enum bfd_reloc_code_real reloc_type
;
8541 int size
= disp_size (n
);
8542 int sign
= i
.types
[n
].bitfield
.disp32s
;
8543 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
8546 /* We can't have 8 bit displacement here. */
8547 gas_assert (!i
.types
[n
].bitfield
.disp8
);
8549 /* The PC relative address is computed relative
8550 to the instruction boundary, so in case immediate
8551 fields follows, we need to adjust the value. */
8552 if (pcrel
&& i
.imm_operands
)
8557 for (n1
= 0; n1
< i
.operands
; n1
++)
8558 if (operand_type_check (i
.types
[n1
], imm
))
8560 /* Only one immediate is allowed for PC
8561 relative address. */
8562 gas_assert (sz
== 0);
8564 i
.op
[n
].disps
->X_add_number
-= sz
;
8566 /* We should find the immediate. */
8567 gas_assert (sz
!= 0);
8570 p
= frag_more (size
);
8571 reloc_type
= reloc (size
, pcrel
, sign
, i
.reloc
[n
]);
8573 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
8574 && (((reloc_type
== BFD_RELOC_32
8575 || reloc_type
== BFD_RELOC_X86_64_32S
8576 || (reloc_type
== BFD_RELOC_64
8578 && (i
.op
[n
].disps
->X_op
== O_symbol
8579 || (i
.op
[n
].disps
->X_op
== O_add
8580 && ((symbol_get_value_expression
8581 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
8583 || reloc_type
== BFD_RELOC_32_PCREL
))
8587 reloc_type
= BFD_RELOC_386_GOTPC
;
8588 i
.op
[n
].imms
->X_add_number
+=
8589 encoding_length (insn_start_frag
, insn_start_off
, p
);
8591 else if (reloc_type
== BFD_RELOC_64
)
8592 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
8594 /* Don't do the adjustment for x86-64, as there
8595 the pcrel addressing is relative to the _next_
8596 insn, and that is taken care of in other code. */
8597 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
8599 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
8600 size
, i
.op
[n
].disps
, pcrel
,
8602 /* Check for "call/jmp *mem", "mov mem, %reg",
8603 "test %reg, mem" and "binop mem, %reg" where binop
8604 is one of adc, add, and, cmp, or, sbb, sub, xor
8605 instructions without data prefix. Always generate
8606 R_386_GOT32X for "sym*GOT" operand in 32-bit mode. */
8607 if (i
.prefix
[DATA_PREFIX
] == 0
8608 && (generate_relax_relocations
8611 && i
.rm
.regmem
== 5))
8613 || (i
.rm
.mode
== 0 && i
.rm
.regmem
== 5))
8614 && ((i
.operands
== 1
8615 && i
.tm
.base_opcode
== 0xff
8616 && (i
.rm
.reg
== 2 || i
.rm
.reg
== 4))
8618 && (i
.tm
.base_opcode
== 0x8b
8619 || i
.tm
.base_opcode
== 0x85
8620 || (i
.tm
.base_opcode
& 0xc7) == 0x03))))
8624 fixP
->fx_tcbit
= i
.rex
!= 0;
8626 && (i
.base_reg
->reg_num
== RegIP
))
8627 fixP
->fx_tcbit2
= 1;
8630 fixP
->fx_tcbit2
= 1;
8638 output_imm (fragS
*insn_start_frag
, offsetT insn_start_off
)
8643 for (n
= 0; n
< i
.operands
; n
++)
8645 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
8646 if (i
.rounding
&& (int) n
== i
.rounding
->operand
)
8649 if (operand_type_check (i
.types
[n
], imm
))
8651 if (i
.op
[n
].imms
->X_op
== O_constant
)
8653 int size
= imm_size (n
);
8656 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
8658 p
= frag_more (size
);
8659 md_number_to_chars (p
, val
, size
);
8663 /* Not absolute_section.
8664 Need a 32-bit fixup (don't support 8bit
8665 non-absolute imms). Try to support other
8667 enum bfd_reloc_code_real reloc_type
;
8668 int size
= imm_size (n
);
8671 if (i
.types
[n
].bitfield
.imm32s
8672 && (i
.suffix
== QWORD_MNEM_SUFFIX
8673 || (!i
.suffix
&& i
.tm
.opcode_modifier
.no_lsuf
)))
8678 p
= frag_more (size
);
8679 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
8681 /* This is tough to explain. We end up with this one if we
8682 * have operands that look like
8683 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
8684 * obtain the absolute address of the GOT, and it is strongly
8685 * preferable from a performance point of view to avoid using
8686 * a runtime relocation for this. The actual sequence of
8687 * instructions often look something like:
8692 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
8694 * The call and pop essentially return the absolute address
8695 * of the label .L66 and store it in %ebx. The linker itself
8696 * will ultimately change the first operand of the addl so
8697 * that %ebx points to the GOT, but to keep things simple, the
8698 * .o file must have this operand set so that it generates not
8699 * the absolute address of .L66, but the absolute address of
8700 * itself. This allows the linker itself simply treat a GOTPC
8701 * relocation as asking for a pcrel offset to the GOT to be
8702 * added in, and the addend of the relocation is stored in the
8703 * operand field for the instruction itself.
8705 * Our job here is to fix the operand so that it would add
8706 * the correct offset so that %ebx would point to itself. The
8707 * thing that is tricky is that .-.L66 will point to the
8708 * beginning of the instruction, so we need to further modify
8709 * the operand so that it will point to itself. There are
8710 * other cases where you have something like:
8712 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
8714 * and here no correction would be required. Internally in
8715 * the assembler we treat operands of this form as not being
8716 * pcrel since the '.' is explicitly mentioned, and I wonder
8717 * whether it would simplify matters to do it this way. Who
8718 * knows. In earlier versions of the PIC patches, the
8719 * pcrel_adjust field was used to store the correction, but
8720 * since the expression is not pcrel, I felt it would be
8721 * confusing to do it this way. */
8723 if ((reloc_type
== BFD_RELOC_32
8724 || reloc_type
== BFD_RELOC_X86_64_32S
8725 || reloc_type
== BFD_RELOC_64
)
8727 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
8728 && (i
.op
[n
].imms
->X_op
== O_symbol
8729 || (i
.op
[n
].imms
->X_op
== O_add
8730 && ((symbol_get_value_expression
8731 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
8735 reloc_type
= BFD_RELOC_386_GOTPC
;
8737 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
8739 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
8740 i
.op
[n
].imms
->X_add_number
+=
8741 encoding_length (insn_start_frag
, insn_start_off
, p
);
8743 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
8744 i
.op
[n
].imms
, 0, reloc_type
);
8750 /* x86_cons_fix_new is called via the expression parsing code when a
8751 reloc is needed. We use this hook to get the correct .got reloc. */
8752 static int cons_sign
= -1;
8755 x86_cons_fix_new (fragS
*frag
, unsigned int off
, unsigned int len
,
8756 expressionS
*exp
, bfd_reloc_code_real_type r
)
8758 r
= reloc (len
, 0, cons_sign
, r
);
8761 if (exp
->X_op
== O_secrel
)
8763 exp
->X_op
= O_symbol
;
8764 r
= BFD_RELOC_32_SECREL
;
8768 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
8771 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
8772 purpose of the `.dc.a' internal pseudo-op. */
8775 x86_address_bytes (void)
8777 if ((stdoutput
->arch_info
->mach
& bfd_mach_x64_32
))
8779 return stdoutput
->arch_info
->bits_per_address
/ 8;
8782 #if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
8784 # define lex_got(reloc, adjust, types) NULL
8786 /* Parse operands of the form
8787 <symbol>@GOTOFF+<nnn>
8788 and similar .plt or .got references.
8790 If we find one, set up the correct relocation in RELOC and copy the
8791 input string, minus the `@GOTOFF' into a malloc'd buffer for
8792 parsing by the calling routine. Return this buffer, and if ADJUST
8793 is non-null set it to the length of the string we removed from the
8794 input line. Otherwise return NULL. */
8796 lex_got (enum bfd_reloc_code_real
*rel
,
8798 i386_operand_type
*types
)
8800 /* Some of the relocations depend on the size of what field is to
8801 be relocated. But in our callers i386_immediate and i386_displacement
8802 we don't yet know the operand size (this will be set by insn
8803 matching). Hence we record the word32 relocation here,
8804 and adjust the reloc according to the real size in reloc(). */
8805 static const struct {
8808 const enum bfd_reloc_code_real rel
[2];
8809 const i386_operand_type types64
;
8811 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8812 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32
,
8814 OPERAND_TYPE_IMM32_64
},
8816 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real
,
8817 BFD_RELOC_X86_64_PLTOFF64
},
8818 OPERAND_TYPE_IMM64
},
8819 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32
,
8820 BFD_RELOC_X86_64_PLT32
},
8821 OPERAND_TYPE_IMM32_32S_DISP32
},
8822 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real
,
8823 BFD_RELOC_X86_64_GOTPLT64
},
8824 OPERAND_TYPE_IMM64_DISP64
},
8825 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF
,
8826 BFD_RELOC_X86_64_GOTOFF64
},
8827 OPERAND_TYPE_IMM64_DISP64
},
8828 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real
,
8829 BFD_RELOC_X86_64_GOTPCREL
},
8830 OPERAND_TYPE_IMM32_32S_DISP32
},
8831 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD
,
8832 BFD_RELOC_X86_64_TLSGD
},
8833 OPERAND_TYPE_IMM32_32S_DISP32
},
8834 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM
,
8835 _dummy_first_bfd_reloc_code_real
},
8836 OPERAND_TYPE_NONE
},
8837 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real
,
8838 BFD_RELOC_X86_64_TLSLD
},
8839 OPERAND_TYPE_IMM32_32S_DISP32
},
8840 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32
,
8841 BFD_RELOC_X86_64_GOTTPOFF
},
8842 OPERAND_TYPE_IMM32_32S_DISP32
},
8843 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32
,
8844 BFD_RELOC_X86_64_TPOFF32
},
8845 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
8846 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE
,
8847 _dummy_first_bfd_reloc_code_real
},
8848 OPERAND_TYPE_NONE
},
8849 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32
,
8850 BFD_RELOC_X86_64_DTPOFF32
},
8851 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
8852 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE
,
8853 _dummy_first_bfd_reloc_code_real
},
8854 OPERAND_TYPE_NONE
},
8855 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE
,
8856 _dummy_first_bfd_reloc_code_real
},
8857 OPERAND_TYPE_NONE
},
8858 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32
,
8859 BFD_RELOC_X86_64_GOT32
},
8860 OPERAND_TYPE_IMM32_32S_64_DISP32
},
8861 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC
,
8862 BFD_RELOC_X86_64_GOTPC32_TLSDESC
},
8863 OPERAND_TYPE_IMM32_32S_DISP32
},
8864 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL
,
8865 BFD_RELOC_X86_64_TLSDESC_CALL
},
8866 OPERAND_TYPE_IMM32_32S_DISP32
},
8871 #if defined (OBJ_MAYBE_ELF)
8876 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
8877 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
8880 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
8882 int len
= gotrel
[j
].len
;
8883 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
8885 if (gotrel
[j
].rel
[object_64bit
] != 0)
8888 char *tmpbuf
, *past_reloc
;
8890 *rel
= gotrel
[j
].rel
[object_64bit
];
8894 if (flag_code
!= CODE_64BIT
)
8896 types
->bitfield
.imm32
= 1;
8897 types
->bitfield
.disp32
= 1;
8900 *types
= gotrel
[j
].types64
;
8903 if (j
!= 0 && GOT_symbol
== NULL
)
8904 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
8906 /* The length of the first part of our input line. */
8907 first
= cp
- input_line_pointer
;
8909 /* The second part goes from after the reloc token until
8910 (and including) an end_of_line char or comma. */
8911 past_reloc
= cp
+ 1 + len
;
8913 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
8915 second
= cp
+ 1 - past_reloc
;
8917 /* Allocate and copy string. The trailing NUL shouldn't
8918 be necessary, but be safe. */
8919 tmpbuf
= XNEWVEC (char, first
+ second
+ 2);
8920 memcpy (tmpbuf
, input_line_pointer
, first
);
8921 if (second
!= 0 && *past_reloc
!= ' ')
8922 /* Replace the relocation token with ' ', so that
8923 errors like foo@GOTOFF1 will be detected. */
8924 tmpbuf
[first
++] = ' ';
8926 /* Increment length by 1 if the relocation token is
8931 memcpy (tmpbuf
+ first
, past_reloc
, second
);
8932 tmpbuf
[first
+ second
] = '\0';
8936 as_bad (_("@%s reloc is not supported with %d-bit output format"),
8937 gotrel
[j
].str
, 1 << (5 + object_64bit
));
8942 /* Might be a symbol version string. Don't as_bad here. */
8951 /* Parse operands of the form
8952 <symbol>@SECREL32+<nnn>
8954 If we find one, set up the correct relocation in RELOC and copy the
8955 input string, minus the `@SECREL32' into a malloc'd buffer for
8956 parsing by the calling routine. Return this buffer, and if ADJUST
8957 is non-null set it to the length of the string we removed from the
8958 input line. Otherwise return NULL.
8960 This function is copied from the ELF version above adjusted for PE targets. */
8963 lex_got (enum bfd_reloc_code_real
*rel ATTRIBUTE_UNUSED
,
8964 int *adjust ATTRIBUTE_UNUSED
,
8965 i386_operand_type
*types
)
8971 const enum bfd_reloc_code_real rel
[2];
8972 const i386_operand_type types64
;
8976 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL
,
8977 BFD_RELOC_32_SECREL
},
8978 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
8984 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
8985 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
8988 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
8990 int len
= gotrel
[j
].len
;
8992 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
8994 if (gotrel
[j
].rel
[object_64bit
] != 0)
8997 char *tmpbuf
, *past_reloc
;
8999 *rel
= gotrel
[j
].rel
[object_64bit
];
9005 if (flag_code
!= CODE_64BIT
)
9007 types
->bitfield
.imm32
= 1;
9008 types
->bitfield
.disp32
= 1;
9011 *types
= gotrel
[j
].types64
;
9014 /* The length of the first part of our input line. */
9015 first
= cp
- input_line_pointer
;
9017 /* The second part goes from after the reloc token until
9018 (and including) an end_of_line char or comma. */
9019 past_reloc
= cp
+ 1 + len
;
9021 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
9023 second
= cp
+ 1 - past_reloc
;
9025 /* Allocate and copy string. The trailing NUL shouldn't
9026 be necessary, but be safe. */
9027 tmpbuf
= XNEWVEC (char, first
+ second
+ 2);
9028 memcpy (tmpbuf
, input_line_pointer
, first
);
9029 if (second
!= 0 && *past_reloc
!= ' ')
9030 /* Replace the relocation token with ' ', so that
9031 errors like foo@SECLREL321 will be detected. */
9032 tmpbuf
[first
++] = ' ';
9033 memcpy (tmpbuf
+ first
, past_reloc
, second
);
9034 tmpbuf
[first
+ second
] = '\0';
9038 as_bad (_("@%s reloc is not supported with %d-bit output format"),
9039 gotrel
[j
].str
, 1 << (5 + object_64bit
));
9044 /* Might be a symbol version string. Don't as_bad here. */
9050 bfd_reloc_code_real_type
9051 x86_cons (expressionS
*exp
, int size
)
9053 bfd_reloc_code_real_type got_reloc
= NO_RELOC
;
9055 intel_syntax
= -intel_syntax
;
9058 if (size
== 4 || (object_64bit
&& size
== 8))
9060 /* Handle @GOTOFF and the like in an expression. */
9062 char *gotfree_input_line
;
9065 save
= input_line_pointer
;
9066 gotfree_input_line
= lex_got (&got_reloc
, &adjust
, NULL
);
9067 if (gotfree_input_line
)
9068 input_line_pointer
= gotfree_input_line
;
9072 if (gotfree_input_line
)
9074 /* expression () has merrily parsed up to the end of line,
9075 or a comma - in the wrong buffer. Transfer how far
9076 input_line_pointer has moved to the right buffer. */
9077 input_line_pointer
= (save
9078 + (input_line_pointer
- gotfree_input_line
)
9080 free (gotfree_input_line
);
9081 if (exp
->X_op
== O_constant
9082 || exp
->X_op
== O_absent
9083 || exp
->X_op
== O_illegal
9084 || exp
->X_op
== O_register
9085 || exp
->X_op
== O_big
)
9087 char c
= *input_line_pointer
;
9088 *input_line_pointer
= 0;
9089 as_bad (_("missing or invalid expression `%s'"), save
);
9090 *input_line_pointer
= c
;
9092 else if ((got_reloc
== BFD_RELOC_386_PLT32
9093 || got_reloc
== BFD_RELOC_X86_64_PLT32
)
9094 && exp
->X_op
!= O_symbol
)
9096 char c
= *input_line_pointer
;
9097 *input_line_pointer
= 0;
9098 as_bad (_("invalid PLT expression `%s'"), save
);
9099 *input_line_pointer
= c
;
9106 intel_syntax
= -intel_syntax
;
9109 i386_intel_simplify (exp
);
9115 signed_cons (int size
)
9117 if (flag_code
== CODE_64BIT
)
9125 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
9132 if (exp
.X_op
== O_symbol
)
9133 exp
.X_op
= O_secrel
;
9135 emit_expr (&exp
, 4);
9137 while (*input_line_pointer
++ == ',');
9139 input_line_pointer
--;
9140 demand_empty_rest_of_line ();
9144 /* Handle Vector operations. */
9147 check_VecOperations (char *op_string
, char *op_end
)
9149 const reg_entry
*mask
;
9154 && (op_end
== NULL
|| op_string
< op_end
))
9157 if (*op_string
== '{')
9161 /* Check broadcasts. */
9162 if (strncmp (op_string
, "1to", 3) == 0)
9167 goto duplicated_vec_op
;
9170 if (*op_string
== '8')
9172 else if (*op_string
== '4')
9174 else if (*op_string
== '2')
9176 else if (*op_string
== '1'
9177 && *(op_string
+1) == '6')
9184 as_bad (_("Unsupported broadcast: `%s'"), saved
);
9189 broadcast_op
.type
= bcst_type
;
9190 broadcast_op
.operand
= this_operand
;
9191 broadcast_op
.bytes
= 0;
9192 i
.broadcast
= &broadcast_op
;
9194 /* Check masking operation. */
9195 else if ((mask
= parse_register (op_string
, &end_op
)) != NULL
)
9197 /* k0 can't be used for write mask. */
9198 if (mask
->reg_type
.bitfield
.class != RegMask
|| !mask
->reg_num
)
9200 as_bad (_("`%s%s' can't be used for write mask"),
9201 register_prefix
, mask
->reg_name
);
9207 mask_op
.mask
= mask
;
9208 mask_op
.zeroing
= 0;
9209 mask_op
.operand
= this_operand
;
9215 goto duplicated_vec_op
;
9217 i
.mask
->mask
= mask
;
9219 /* Only "{z}" is allowed here. No need to check
9220 zeroing mask explicitly. */
9221 if (i
.mask
->operand
!= this_operand
)
9223 as_bad (_("invalid write mask `%s'"), saved
);
9230 /* Check zeroing-flag for masking operation. */
9231 else if (*op_string
== 'z')
9235 mask_op
.mask
= NULL
;
9236 mask_op
.zeroing
= 1;
9237 mask_op
.operand
= this_operand
;
9242 if (i
.mask
->zeroing
)
9245 as_bad (_("duplicated `%s'"), saved
);
9249 i
.mask
->zeroing
= 1;
9251 /* Only "{%k}" is allowed here. No need to check mask
9252 register explicitly. */
9253 if (i
.mask
->operand
!= this_operand
)
9255 as_bad (_("invalid zeroing-masking `%s'"),
9264 goto unknown_vec_op
;
9266 if (*op_string
!= '}')
9268 as_bad (_("missing `}' in `%s'"), saved
);
9273 /* Strip whitespace since the addition of pseudo prefixes
9274 changed how the scrubber treats '{'. */
9275 if (is_space_char (*op_string
))
9281 /* We don't know this one. */
9282 as_bad (_("unknown vector operation: `%s'"), saved
);
9286 if (i
.mask
&& i
.mask
->zeroing
&& !i
.mask
->mask
)
9288 as_bad (_("zeroing-masking only allowed with write mask"));
9296 i386_immediate (char *imm_start
)
9298 char *save_input_line_pointer
;
9299 char *gotfree_input_line
;
9302 i386_operand_type types
;
9304 operand_type_set (&types
, ~0);
9306 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
9308 as_bad (_("at most %d immediate operands are allowed"),
9309 MAX_IMMEDIATE_OPERANDS
);
9313 exp
= &im_expressions
[i
.imm_operands
++];
9314 i
.op
[this_operand
].imms
= exp
;
9316 if (is_space_char (*imm_start
))
9319 save_input_line_pointer
= input_line_pointer
;
9320 input_line_pointer
= imm_start
;
9322 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
9323 if (gotfree_input_line
)
9324 input_line_pointer
= gotfree_input_line
;
9326 exp_seg
= expression (exp
);
9330 /* Handle vector operations. */
9331 if (*input_line_pointer
== '{')
9333 input_line_pointer
= check_VecOperations (input_line_pointer
,
9335 if (input_line_pointer
== NULL
)
9339 if (*input_line_pointer
)
9340 as_bad (_("junk `%s' after expression"), input_line_pointer
);
9342 input_line_pointer
= save_input_line_pointer
;
9343 if (gotfree_input_line
)
9345 free (gotfree_input_line
);
9347 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
9348 exp
->X_op
= O_illegal
;
9351 return i386_finalize_immediate (exp_seg
, exp
, types
, imm_start
);
9355 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
9356 i386_operand_type types
, const char *imm_start
)
9358 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_illegal
|| exp
->X_op
== O_big
)
9361 as_bad (_("missing or invalid immediate expression `%s'"),
9365 else if (exp
->X_op
== O_constant
)
9367 /* Size it properly later. */
9368 i
.types
[this_operand
].bitfield
.imm64
= 1;
9369 /* If not 64bit, sign extend val. */
9370 if (flag_code
!= CODE_64BIT
9371 && (exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
9373 = (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
9375 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
9376 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
9377 && exp_seg
!= absolute_section
9378 && exp_seg
!= text_section
9379 && exp_seg
!= data_section
9380 && exp_seg
!= bss_section
9381 && exp_seg
!= undefined_section
9382 && !bfd_is_com_section (exp_seg
))
9384 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
9388 else if (!intel_syntax
&& exp_seg
== reg_section
)
9391 as_bad (_("illegal immediate register operand %s"), imm_start
);
9396 /* This is an address. The size of the address will be
9397 determined later, depending on destination register,
9398 suffix, or the default for the section. */
9399 i
.types
[this_operand
].bitfield
.imm8
= 1;
9400 i
.types
[this_operand
].bitfield
.imm16
= 1;
9401 i
.types
[this_operand
].bitfield
.imm32
= 1;
9402 i
.types
[this_operand
].bitfield
.imm32s
= 1;
9403 i
.types
[this_operand
].bitfield
.imm64
= 1;
9404 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
9412 i386_scale (char *scale
)
9415 char *save
= input_line_pointer
;
9417 input_line_pointer
= scale
;
9418 val
= get_absolute_expression ();
9423 i
.log2_scale_factor
= 0;
9426 i
.log2_scale_factor
= 1;
9429 i
.log2_scale_factor
= 2;
9432 i
.log2_scale_factor
= 3;
9436 char sep
= *input_line_pointer
;
9438 *input_line_pointer
= '\0';
9439 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
9441 *input_line_pointer
= sep
;
9442 input_line_pointer
= save
;
9446 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
9448 as_warn (_("scale factor of %d without an index register"),
9449 1 << i
.log2_scale_factor
);
9450 i
.log2_scale_factor
= 0;
9452 scale
= input_line_pointer
;
9453 input_line_pointer
= save
;
9458 i386_displacement (char *disp_start
, char *disp_end
)
9462 char *save_input_line_pointer
;
9463 char *gotfree_input_line
;
9465 i386_operand_type bigdisp
, types
= anydisp
;
9468 if (i
.disp_operands
== MAX_MEMORY_OPERANDS
)
9470 as_bad (_("at most %d displacement operands are allowed"),
9471 MAX_MEMORY_OPERANDS
);
9475 operand_type_set (&bigdisp
, 0);
9477 || (!current_templates
->start
->opcode_modifier
.jump
9478 && !current_templates
->start
->opcode_modifier
.jumpdword
))
9480 bigdisp
.bitfield
.disp32
= 1;
9481 override
= (i
.prefix
[ADDR_PREFIX
] != 0);
9482 if (flag_code
== CODE_64BIT
)
9486 bigdisp
.bitfield
.disp32s
= 1;
9487 bigdisp
.bitfield
.disp64
= 1;
9490 else if ((flag_code
== CODE_16BIT
) ^ override
)
9492 bigdisp
.bitfield
.disp32
= 0;
9493 bigdisp
.bitfield
.disp16
= 1;
9498 /* For PC-relative branches, the width of the displacement
9499 is dependent upon data size, not address size. */
9500 override
= (i
.prefix
[DATA_PREFIX
] != 0);
9501 if (flag_code
== CODE_64BIT
)
9503 if (override
|| i
.suffix
== WORD_MNEM_SUFFIX
)
9504 bigdisp
.bitfield
.disp16
= 1;
9507 bigdisp
.bitfield
.disp32
= 1;
9508 bigdisp
.bitfield
.disp32s
= 1;
9514 override
= (i
.suffix
== (flag_code
!= CODE_16BIT
9516 : LONG_MNEM_SUFFIX
));
9517 bigdisp
.bitfield
.disp32
= 1;
9518 if ((flag_code
== CODE_16BIT
) ^ override
)
9520 bigdisp
.bitfield
.disp32
= 0;
9521 bigdisp
.bitfield
.disp16
= 1;
9525 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
9528 exp
= &disp_expressions
[i
.disp_operands
];
9529 i
.op
[this_operand
].disps
= exp
;
9531 save_input_line_pointer
= input_line_pointer
;
9532 input_line_pointer
= disp_start
;
9533 END_STRING_AND_SAVE (disp_end
);
9535 #ifndef GCC_ASM_O_HACK
9536 #define GCC_ASM_O_HACK 0
9539 END_STRING_AND_SAVE (disp_end
+ 1);
9540 if (i
.types
[this_operand
].bitfield
.baseIndex
9541 && displacement_string_end
[-1] == '+')
9543 /* This hack is to avoid a warning when using the "o"
9544 constraint within gcc asm statements.
9547 #define _set_tssldt_desc(n,addr,limit,type) \
9548 __asm__ __volatile__ ( \
9550 "movw %w1,2+%0\n\t" \
9552 "movb %b1,4+%0\n\t" \
9553 "movb %4,5+%0\n\t" \
9554 "movb $0,6+%0\n\t" \
9555 "movb %h1,7+%0\n\t" \
9557 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
9559 This works great except that the output assembler ends
9560 up looking a bit weird if it turns out that there is
9561 no offset. You end up producing code that looks like:
9574 So here we provide the missing zero. */
9576 *displacement_string_end
= '0';
9579 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
9580 if (gotfree_input_line
)
9581 input_line_pointer
= gotfree_input_line
;
9583 exp_seg
= expression (exp
);
9586 if (*input_line_pointer
)
9587 as_bad (_("junk `%s' after expression"), input_line_pointer
);
9589 RESTORE_END_STRING (disp_end
+ 1);
9591 input_line_pointer
= save_input_line_pointer
;
9592 if (gotfree_input_line
)
9594 free (gotfree_input_line
);
9596 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
9597 exp
->X_op
= O_illegal
;
9600 ret
= i386_finalize_displacement (exp_seg
, exp
, types
, disp_start
);
9602 RESTORE_END_STRING (disp_end
);
9608 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
9609 i386_operand_type types
, const char *disp_start
)
9611 i386_operand_type bigdisp
;
9614 /* We do this to make sure that the section symbol is in
9615 the symbol table. We will ultimately change the relocation
9616 to be relative to the beginning of the section. */
9617 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
9618 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
9619 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
9621 if (exp
->X_op
!= O_symbol
)
9624 if (S_IS_LOCAL (exp
->X_add_symbol
)
9625 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
9626 && S_GET_SEGMENT (exp
->X_add_symbol
) != expr_section
)
9627 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
9628 exp
->X_op
= O_subtract
;
9629 exp
->X_op_symbol
= GOT_symbol
;
9630 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
9631 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
9632 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
9633 i
.reloc
[this_operand
] = BFD_RELOC_64
;
9635 i
.reloc
[this_operand
] = BFD_RELOC_32
;
9638 else if (exp
->X_op
== O_absent
9639 || exp
->X_op
== O_illegal
9640 || exp
->X_op
== O_big
)
9643 as_bad (_("missing or invalid displacement expression `%s'"),
9648 else if (flag_code
== CODE_64BIT
9649 && !i
.prefix
[ADDR_PREFIX
]
9650 && exp
->X_op
== O_constant
)
9652 /* Since displacement is signed extended to 64bit, don't allow
9653 disp32 and turn off disp32s if they are out of range. */
9654 i
.types
[this_operand
].bitfield
.disp32
= 0;
9655 if (!fits_in_signed_long (exp
->X_add_number
))
9657 i
.types
[this_operand
].bitfield
.disp32s
= 0;
9658 if (i
.types
[this_operand
].bitfield
.baseindex
)
9660 as_bad (_("0x%lx out range of signed 32bit displacement"),
9661 (long) exp
->X_add_number
);
9667 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
9668 else if (exp
->X_op
!= O_constant
9669 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
9670 && exp_seg
!= absolute_section
9671 && exp_seg
!= text_section
9672 && exp_seg
!= data_section
9673 && exp_seg
!= bss_section
9674 && exp_seg
!= undefined_section
9675 && !bfd_is_com_section (exp_seg
))
9677 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
9682 /* Check if this is a displacement only operand. */
9683 bigdisp
= i
.types
[this_operand
];
9684 bigdisp
.bitfield
.disp8
= 0;
9685 bigdisp
.bitfield
.disp16
= 0;
9686 bigdisp
.bitfield
.disp32
= 0;
9687 bigdisp
.bitfield
.disp32s
= 0;
9688 bigdisp
.bitfield
.disp64
= 0;
9689 if (operand_type_all_zero (&bigdisp
))
9690 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
9696 /* Return the active addressing mode, taking address override and
9697 registers forming the address into consideration. Update the
9698 address override prefix if necessary. */
9700 static enum flag_code
9701 i386_addressing_mode (void)
9703 enum flag_code addr_mode
;
9705 if (i
.prefix
[ADDR_PREFIX
])
9706 addr_mode
= flag_code
== CODE_32BIT
? CODE_16BIT
: CODE_32BIT
;
9709 addr_mode
= flag_code
;
9711 #if INFER_ADDR_PREFIX
9712 if (i
.mem_operands
== 0)
9714 /* Infer address prefix from the first memory operand. */
9715 const reg_entry
*addr_reg
= i
.base_reg
;
9717 if (addr_reg
== NULL
)
9718 addr_reg
= i
.index_reg
;
9722 if (addr_reg
->reg_type
.bitfield
.dword
)
9723 addr_mode
= CODE_32BIT
;
9724 else if (flag_code
!= CODE_64BIT
9725 && addr_reg
->reg_type
.bitfield
.word
)
9726 addr_mode
= CODE_16BIT
;
9728 if (addr_mode
!= flag_code
)
9730 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
9732 /* Change the size of any displacement too. At most one
9733 of Disp16 or Disp32 is set.
9734 FIXME. There doesn't seem to be any real need for
9735 separate Disp16 and Disp32 flags. The same goes for
9736 Imm16 and Imm32. Removing them would probably clean
9737 up the code quite a lot. */
9738 if (flag_code
!= CODE_64BIT
9739 && (i
.types
[this_operand
].bitfield
.disp16
9740 || i
.types
[this_operand
].bitfield
.disp32
))
9741 i
.types
[this_operand
]
9742 = operand_type_xor (i
.types
[this_operand
], disp16_32
);
9752 /* Make sure the memory operand we've been dealt is valid.
9753 Return 1 on success, 0 on a failure. */
9756 i386_index_check (const char *operand_string
)
9758 const char *kind
= "base/index";
9759 enum flag_code addr_mode
= i386_addressing_mode ();
9761 if (current_templates
->start
->opcode_modifier
.isstring
9762 && !current_templates
->start
->cpu_flags
.bitfield
.cpupadlock
9763 && (current_templates
->end
[-1].opcode_modifier
.isstring
9766 /* Memory operands of string insns are special in that they only allow
9767 a single register (rDI, rSI, or rBX) as their memory address. */
9768 const reg_entry
*expected_reg
;
9769 static const char *di_si
[][2] =
9775 static const char *bx
[] = { "ebx", "bx", "rbx" };
9777 kind
= "string address";
9779 if (current_templates
->start
->opcode_modifier
.repprefixok
)
9781 int es_op
= current_templates
->end
[-1].opcode_modifier
.isstring
9785 if (!current_templates
->end
[-1].operand_types
[0].bitfield
.baseindex
9786 || ((!i
.mem_operands
!= !intel_syntax
)
9787 && current_templates
->end
[-1].operand_types
[1]
9788 .bitfield
.baseindex
))
9790 expected_reg
= hash_find (reg_hash
, di_si
[addr_mode
][op
== es_op
]);
9793 expected_reg
= hash_find (reg_hash
, bx
[addr_mode
]);
9795 if (i
.base_reg
!= expected_reg
9797 || operand_type_check (i
.types
[this_operand
], disp
))
9799 /* The second memory operand must have the same size as
9803 && !((addr_mode
== CODE_64BIT
9804 && i
.base_reg
->reg_type
.bitfield
.qword
)
9805 || (addr_mode
== CODE_32BIT
9806 ? i
.base_reg
->reg_type
.bitfield
.dword
9807 : i
.base_reg
->reg_type
.bitfield
.word
)))
9810 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
9812 intel_syntax
? '[' : '(',
9814 expected_reg
->reg_name
,
9815 intel_syntax
? ']' : ')');
9822 as_bad (_("`%s' is not a valid %s expression"),
9823 operand_string
, kind
);
9828 if (addr_mode
!= CODE_16BIT
)
9830 /* 32-bit/64-bit checks. */
9832 && ((addr_mode
== CODE_64BIT
9833 ? !i
.base_reg
->reg_type
.bitfield
.qword
9834 : !i
.base_reg
->reg_type
.bitfield
.dword
)
9835 || (i
.index_reg
&& i
.base_reg
->reg_num
== RegIP
)
9836 || i
.base_reg
->reg_num
== RegIZ
))
9838 && !i
.index_reg
->reg_type
.bitfield
.xmmword
9839 && !i
.index_reg
->reg_type
.bitfield
.ymmword
9840 && !i
.index_reg
->reg_type
.bitfield
.zmmword
9841 && ((addr_mode
== CODE_64BIT
9842 ? !i
.index_reg
->reg_type
.bitfield
.qword
9843 : !i
.index_reg
->reg_type
.bitfield
.dword
)
9844 || !i
.index_reg
->reg_type
.bitfield
.baseindex
)))
9847 /* bndmk, bndldx, and bndstx have special restrictions. */
9848 if (current_templates
->start
->base_opcode
== 0xf30f1b
9849 || (current_templates
->start
->base_opcode
& ~1) == 0x0f1a)
9851 /* They cannot use RIP-relative addressing. */
9852 if (i
.base_reg
&& i
.base_reg
->reg_num
== RegIP
)
9854 as_bad (_("`%s' cannot be used here"), operand_string
);
9858 /* bndldx and bndstx ignore their scale factor. */
9859 if (current_templates
->start
->base_opcode
!= 0xf30f1b
9860 && i
.log2_scale_factor
)
9861 as_warn (_("register scaling is being ignored here"));
9866 /* 16-bit checks. */
9868 && (!i
.base_reg
->reg_type
.bitfield
.word
9869 || !i
.base_reg
->reg_type
.bitfield
.baseindex
))
9871 && (!i
.index_reg
->reg_type
.bitfield
.word
9872 || !i
.index_reg
->reg_type
.bitfield
.baseindex
9874 && i
.base_reg
->reg_num
< 6
9875 && i
.index_reg
->reg_num
>= 6
9876 && i
.log2_scale_factor
== 0))))
9883 /* Handle vector immediates. */
9886 RC_SAE_immediate (const char *imm_start
)
9888 unsigned int match_found
, j
;
9889 const char *pstr
= imm_start
;
9897 for (j
= 0; j
< ARRAY_SIZE (RC_NamesTable
); j
++)
9899 if (!strncmp (pstr
, RC_NamesTable
[j
].name
, RC_NamesTable
[j
].len
))
9903 rc_op
.type
= RC_NamesTable
[j
].type
;
9904 rc_op
.operand
= this_operand
;
9905 i
.rounding
= &rc_op
;
9909 as_bad (_("duplicated `%s'"), imm_start
);
9912 pstr
+= RC_NamesTable
[j
].len
;
9922 as_bad (_("Missing '}': '%s'"), imm_start
);
9925 /* RC/SAE immediate string should contain nothing more. */;
9928 as_bad (_("Junk after '}': '%s'"), imm_start
);
9932 exp
= &im_expressions
[i
.imm_operands
++];
9933 i
.op
[this_operand
].imms
= exp
;
9935 exp
->X_op
= O_constant
;
9936 exp
->X_add_number
= 0;
9937 exp
->X_add_symbol
= (symbolS
*) 0;
9938 exp
->X_op_symbol
= (symbolS
*) 0;
9940 i
.types
[this_operand
].bitfield
.imm8
= 1;
9944 /* Only string instructions can have a second memory operand, so
9945 reduce current_templates to just those if it contains any. */
9947 maybe_adjust_templates (void)
9949 const insn_template
*t
;
9951 gas_assert (i
.mem_operands
== 1);
9953 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
9954 if (t
->opcode_modifier
.isstring
)
9957 if (t
< current_templates
->end
)
9959 static templates aux_templates
;
9960 bfd_boolean recheck
;
9962 aux_templates
.start
= t
;
9963 for (; t
< current_templates
->end
; ++t
)
9964 if (!t
->opcode_modifier
.isstring
)
9966 aux_templates
.end
= t
;
9968 /* Determine whether to re-check the first memory operand. */
9969 recheck
= (aux_templates
.start
!= current_templates
->start
9970 || t
!= current_templates
->end
);
9972 current_templates
= &aux_templates
;
9977 if (i
.memop1_string
!= NULL
9978 && i386_index_check (i
.memop1_string
) == 0)
9987 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
9991 i386_att_operand (char *operand_string
)
9995 char *op_string
= operand_string
;
9997 if (is_space_char (*op_string
))
10000 /* We check for an absolute prefix (differentiating,
10001 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
10002 if (*op_string
== ABSOLUTE_PREFIX
)
10005 if (is_space_char (*op_string
))
10007 i
.jumpabsolute
= TRUE
;
10010 /* Check if operand is a register. */
10011 if ((r
= parse_register (op_string
, &end_op
)) != NULL
)
10013 i386_operand_type temp
;
10015 /* Check for a segment override by searching for ':' after a
10016 segment register. */
10017 op_string
= end_op
;
10018 if (is_space_char (*op_string
))
10020 if (*op_string
== ':' && r
->reg_type
.bitfield
.class == SReg
)
10022 switch (r
->reg_num
)
10025 i
.seg
[i
.mem_operands
] = &es
;
10028 i
.seg
[i
.mem_operands
] = &cs
;
10031 i
.seg
[i
.mem_operands
] = &ss
;
10034 i
.seg
[i
.mem_operands
] = &ds
;
10037 i
.seg
[i
.mem_operands
] = &fs
;
10040 i
.seg
[i
.mem_operands
] = &gs
;
10044 /* Skip the ':' and whitespace. */
10046 if (is_space_char (*op_string
))
10049 if (!is_digit_char (*op_string
)
10050 && !is_identifier_char (*op_string
)
10051 && *op_string
!= '('
10052 && *op_string
!= ABSOLUTE_PREFIX
)
10054 as_bad (_("bad memory operand `%s'"), op_string
);
10057 /* Handle case of %es:*foo. */
10058 if (*op_string
== ABSOLUTE_PREFIX
)
10061 if (is_space_char (*op_string
))
10063 i
.jumpabsolute
= TRUE
;
10065 goto do_memory_reference
;
10068 /* Handle vector operations. */
10069 if (*op_string
== '{')
10071 op_string
= check_VecOperations (op_string
, NULL
);
10072 if (op_string
== NULL
)
10078 as_bad (_("junk `%s' after register"), op_string
);
10081 temp
= r
->reg_type
;
10082 temp
.bitfield
.baseindex
= 0;
10083 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
10085 i
.types
[this_operand
].bitfield
.unspecified
= 0;
10086 i
.op
[this_operand
].regs
= r
;
10089 else if (*op_string
== REGISTER_PREFIX
)
10091 as_bad (_("bad register name `%s'"), op_string
);
10094 else if (*op_string
== IMMEDIATE_PREFIX
)
10097 if (i
.jumpabsolute
)
10099 as_bad (_("immediate operand illegal with absolute jump"));
10102 if (!i386_immediate (op_string
))
10105 else if (RC_SAE_immediate (operand_string
))
10107 /* If it is a RC or SAE immediate, do nothing. */
10110 else if (is_digit_char (*op_string
)
10111 || is_identifier_char (*op_string
)
10112 || *op_string
== '"'
10113 || *op_string
== '(')
10115 /* This is a memory reference of some sort. */
10118 /* Start and end of displacement string expression (if found). */
10119 char *displacement_string_start
;
10120 char *displacement_string_end
;
10123 do_memory_reference
:
10124 if (i
.mem_operands
== 1 && !maybe_adjust_templates ())
10126 if ((i
.mem_operands
== 1
10127 && !current_templates
->start
->opcode_modifier
.isstring
)
10128 || i
.mem_operands
== 2)
10130 as_bad (_("too many memory references for `%s'"),
10131 current_templates
->start
->name
);
10135 /* Check for base index form. We detect the base index form by
10136 looking for an ')' at the end of the operand, searching
10137 for the '(' matching it, and finding a REGISTER_PREFIX or ','
10139 base_string
= op_string
+ strlen (op_string
);
10141 /* Handle vector operations. */
10142 vop_start
= strchr (op_string
, '{');
10143 if (vop_start
&& vop_start
< base_string
)
10145 if (check_VecOperations (vop_start
, base_string
) == NULL
)
10147 base_string
= vop_start
;
10151 if (is_space_char (*base_string
))
10154 /* If we only have a displacement, set-up for it to be parsed later. */
10155 displacement_string_start
= op_string
;
10156 displacement_string_end
= base_string
+ 1;
10158 if (*base_string
== ')')
10161 unsigned int parens_balanced
= 1;
10162 /* We've already checked that the number of left & right ()'s are
10163 equal, so this loop will not be infinite. */
10167 if (*base_string
== ')')
10169 if (*base_string
== '(')
10172 while (parens_balanced
);
10174 temp_string
= base_string
;
10176 /* Skip past '(' and whitespace. */
10178 if (is_space_char (*base_string
))
10181 if (*base_string
== ','
10182 || ((i
.base_reg
= parse_register (base_string
, &end_op
))
10185 displacement_string_end
= temp_string
;
10187 i
.types
[this_operand
].bitfield
.baseindex
= 1;
10191 base_string
= end_op
;
10192 if (is_space_char (*base_string
))
10196 /* There may be an index reg or scale factor here. */
10197 if (*base_string
== ',')
10200 if (is_space_char (*base_string
))
10203 if ((i
.index_reg
= parse_register (base_string
, &end_op
))
10206 base_string
= end_op
;
10207 if (is_space_char (*base_string
))
10209 if (*base_string
== ',')
10212 if (is_space_char (*base_string
))
10215 else if (*base_string
!= ')')
10217 as_bad (_("expecting `,' or `)' "
10218 "after index register in `%s'"),
10223 else if (*base_string
== REGISTER_PREFIX
)
10225 end_op
= strchr (base_string
, ',');
10228 as_bad (_("bad register name `%s'"), base_string
);
10232 /* Check for scale factor. */
10233 if (*base_string
!= ')')
10235 char *end_scale
= i386_scale (base_string
);
10240 base_string
= end_scale
;
10241 if (is_space_char (*base_string
))
10243 if (*base_string
!= ')')
10245 as_bad (_("expecting `)' "
10246 "after scale factor in `%s'"),
10251 else if (!i
.index_reg
)
10253 as_bad (_("expecting index register or scale factor "
10254 "after `,'; got '%c'"),
10259 else if (*base_string
!= ')')
10261 as_bad (_("expecting `,' or `)' "
10262 "after base register in `%s'"),
10267 else if (*base_string
== REGISTER_PREFIX
)
10269 end_op
= strchr (base_string
, ',');
10272 as_bad (_("bad register name `%s'"), base_string
);
10277 /* If there's an expression beginning the operand, parse it,
10278 assuming displacement_string_start and
10279 displacement_string_end are meaningful. */
10280 if (displacement_string_start
!= displacement_string_end
)
10282 if (!i386_displacement (displacement_string_start
,
10283 displacement_string_end
))
10287 /* Special case for (%dx) while doing input/output op. */
10289 && i
.base_reg
->reg_type
.bitfield
.instance
== RegD
10290 && i
.base_reg
->reg_type
.bitfield
.word
10291 && i
.index_reg
== 0
10292 && i
.log2_scale_factor
== 0
10293 && i
.seg
[i
.mem_operands
] == 0
10294 && !operand_type_check (i
.types
[this_operand
], disp
))
10296 i
.types
[this_operand
] = i
.base_reg
->reg_type
;
10300 if (i386_index_check (operand_string
) == 0)
10302 i
.flags
[this_operand
] |= Operand_Mem
;
10303 if (i
.mem_operands
== 0)
10304 i
.memop1_string
= xstrdup (operand_string
);
10309 /* It's not a memory operand; argh! */
10310 as_bad (_("invalid char %s beginning operand %d `%s'"),
10311 output_invalid (*op_string
),
10316 return 1; /* Normal return. */
10319 /* Calculate the maximum variable size (i.e., excluding fr_fix)
10320 that an rs_machine_dependent frag may reach. */
10323 i386_frag_max_var (fragS
*frag
)
10325 /* The only relaxable frags are for jumps.
10326 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
10327 gas_assert (frag
->fr_type
== rs_machine_dependent
);
10328 return TYPE_FROM_RELAX_STATE (frag
->fr_subtype
) == UNCOND_JUMP
? 4 : 5;
10331 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10333 elf_symbol_resolved_in_segment_p (symbolS
*fr_symbol
, offsetT fr_var
)
10335 /* STT_GNU_IFUNC symbol must go through PLT. */
10336 if ((symbol_get_bfdsym (fr_symbol
)->flags
10337 & BSF_GNU_INDIRECT_FUNCTION
) != 0)
10340 if (!S_IS_EXTERNAL (fr_symbol
))
10341 /* Symbol may be weak or local. */
10342 return !S_IS_WEAK (fr_symbol
);
10344 /* Global symbols with non-default visibility can't be preempted. */
10345 if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol
)) != STV_DEFAULT
)
10348 if (fr_var
!= NO_RELOC
)
10349 switch ((enum bfd_reloc_code_real
) fr_var
)
10351 case BFD_RELOC_386_PLT32
:
10352 case BFD_RELOC_X86_64_PLT32
:
10353 /* Symbol with PLT relocation may be preempted. */
10359 /* Global symbols with default visibility in a shared library may be
10360 preempted by another definition. */
10365 /* md_estimate_size_before_relax()
10367 Called just before relax() for rs_machine_dependent frags. The x86
10368 assembler uses these frags to handle variable size jump
10371 Any symbol that is now undefined will not become defined.
10372 Return the correct fr_subtype in the frag.
10373 Return the initial "guess for variable size of frag" to caller.
10374 The guess is actually the growth beyond the fixed part. Whatever
10375 we do to grow the fixed or variable part contributes to our
10379 md_estimate_size_before_relax (fragS
*fragP
, segT segment
)
10381 /* We've already got fragP->fr_subtype right; all we have to do is
10382 check for un-relaxable symbols. On an ELF system, we can't relax
10383 an externally visible symbol, because it may be overridden by a
10385 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
10386 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10388 && !elf_symbol_resolved_in_segment_p (fragP
->fr_symbol
,
10391 #if defined (OBJ_COFF) && defined (TE_PE)
10392 || (OUTPUT_FLAVOR
== bfd_target_coff_flavour
10393 && S_IS_WEAK (fragP
->fr_symbol
))
10397 /* Symbol is undefined in this segment, or we need to keep a
10398 reloc so that weak symbols can be overridden. */
10399 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
10400 enum bfd_reloc_code_real reloc_type
;
10401 unsigned char *opcode
;
10404 if (fragP
->fr_var
!= NO_RELOC
)
10405 reloc_type
= (enum bfd_reloc_code_real
) fragP
->fr_var
;
10406 else if (size
== 2)
10407 reloc_type
= BFD_RELOC_16_PCREL
;
10408 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10409 else if (need_plt32_p (fragP
->fr_symbol
))
10410 reloc_type
= BFD_RELOC_X86_64_PLT32
;
10413 reloc_type
= BFD_RELOC_32_PCREL
;
10415 old_fr_fix
= fragP
->fr_fix
;
10416 opcode
= (unsigned char *) fragP
->fr_opcode
;
10418 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
10421 /* Make jmp (0xeb) a (d)word displacement jump. */
10423 fragP
->fr_fix
+= size
;
10424 fix_new (fragP
, old_fr_fix
, size
,
10426 fragP
->fr_offset
, 1,
10432 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
10434 /* Negate the condition, and branch past an
10435 unconditional jump. */
10438 /* Insert an unconditional jump. */
10440 /* We added two extra opcode bytes, and have a two byte
10442 fragP
->fr_fix
+= 2 + 2;
10443 fix_new (fragP
, old_fr_fix
+ 2, 2,
10445 fragP
->fr_offset
, 1,
10449 /* Fall through. */
10452 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
10456 fragP
->fr_fix
+= 1;
10457 fixP
= fix_new (fragP
, old_fr_fix
, 1,
10459 fragP
->fr_offset
, 1,
10460 BFD_RELOC_8_PCREL
);
10461 fixP
->fx_signed
= 1;
10465 /* This changes the byte-displacement jump 0x7N
10466 to the (d)word-displacement jump 0x0f,0x8N. */
10467 opcode
[1] = opcode
[0] + 0x10;
10468 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
10469 /* We've added an opcode byte. */
10470 fragP
->fr_fix
+= 1 + size
;
10471 fix_new (fragP
, old_fr_fix
+ 1, size
,
10473 fragP
->fr_offset
, 1,
10478 BAD_CASE (fragP
->fr_subtype
);
10482 return fragP
->fr_fix
- old_fr_fix
;
10485 /* Guess size depending on current relax state. Initially the relax
10486 state will correspond to a short jump and we return 1, because
10487 the variable part of the frag (the branch offset) is one byte
10488 long. However, we can relax a section more than once and in that
10489 case we must either set fr_subtype back to the unrelaxed state,
10490 or return the value for the appropriate branch. */
10491 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
10494 /* Called after relax() is finished.
10496 In: Address of frag.
10497 fr_type == rs_machine_dependent.
10498 fr_subtype is what the address relaxed to.
10500 Out: Any fixSs and constants are set up.
10501 Caller will turn frag into a ".space 0". */
10504 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec ATTRIBUTE_UNUSED
,
10507 unsigned char *opcode
;
10508 unsigned char *where_to_put_displacement
= NULL
;
10509 offsetT target_address
;
10510 offsetT opcode_address
;
10511 unsigned int extension
= 0;
10512 offsetT displacement_from_opcode_start
;
10514 opcode
= (unsigned char *) fragP
->fr_opcode
;
10516 /* Address we want to reach in file space. */
10517 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
10519 /* Address opcode resides at in file space. */
10520 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
10522 /* Displacement from opcode start to fill into instruction. */
10523 displacement_from_opcode_start
= target_address
- opcode_address
;
10525 if ((fragP
->fr_subtype
& BIG
) == 0)
10527 /* Don't have to change opcode. */
10528 extension
= 1; /* 1 opcode + 1 displacement */
10529 where_to_put_displacement
= &opcode
[1];
10533 if (no_cond_jump_promotion
10534 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
10535 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
10536 _("long jump required"));
10538 switch (fragP
->fr_subtype
)
10540 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
10541 extension
= 4; /* 1 opcode + 4 displacement */
10543 where_to_put_displacement
= &opcode
[1];
10546 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
10547 extension
= 2; /* 1 opcode + 2 displacement */
10549 where_to_put_displacement
= &opcode
[1];
10552 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
10553 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
10554 extension
= 5; /* 2 opcode + 4 displacement */
10555 opcode
[1] = opcode
[0] + 0x10;
10556 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
10557 where_to_put_displacement
= &opcode
[2];
10560 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
10561 extension
= 3; /* 2 opcode + 2 displacement */
10562 opcode
[1] = opcode
[0] + 0x10;
10563 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
10564 where_to_put_displacement
= &opcode
[2];
10567 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
10572 where_to_put_displacement
= &opcode
[3];
10576 BAD_CASE (fragP
->fr_subtype
);
10581 /* If size if less then four we are sure that the operand fits,
10582 but if it's 4, then it could be that the displacement is larger
10584 if (DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
) == 4
10586 && ((addressT
) (displacement_from_opcode_start
- extension
10587 + ((addressT
) 1 << 31))
10588 > (((addressT
) 2 << 31) - 1)))
10590 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
10591 _("jump target out of range"));
10592 /* Make us emit 0. */
10593 displacement_from_opcode_start
= extension
;
10595 /* Now put displacement after opcode. */
10596 md_number_to_chars ((char *) where_to_put_displacement
,
10597 (valueT
) (displacement_from_opcode_start
- extension
),
10598 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
10599 fragP
->fr_fix
+= extension
;
10602 /* Apply a fixup (fixP) to segment data, once it has been determined
10603 by our caller that we have all the info we need to fix it up.
10605 Parameter valP is the pointer to the value of the bits.
10607 On the 386, immediates, displacements, and data pointers are all in
10608 the same (little-endian) format, so we don't need to care about which
10609 we are handling. */
10612 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
10614 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
10615 valueT value
= *valP
;
10617 #if !defined (TE_Mach)
10618 if (fixP
->fx_pcrel
)
10620 switch (fixP
->fx_r_type
)
10626 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
10629 case BFD_RELOC_X86_64_32S
:
10630 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
10633 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
10636 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
10641 if (fixP
->fx_addsy
!= NULL
10642 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
10643 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
10644 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
10645 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
10646 && !use_rela_relocations
)
10648 /* This is a hack. There should be a better way to handle this.
10649 This covers for the fact that bfd_install_relocation will
10650 subtract the current location (for partial_inplace, PC relative
10651 relocations); see more below. */
10655 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
10658 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
10660 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10663 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
10665 if ((sym_seg
== seg
10666 || (symbol_section_p (fixP
->fx_addsy
)
10667 && sym_seg
!= absolute_section
))
10668 && !generic_force_reloc (fixP
))
10670 /* Yes, we add the values in twice. This is because
10671 bfd_install_relocation subtracts them out again. I think
10672 bfd_install_relocation is broken, but I don't dare change
10674 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
10678 #if defined (OBJ_COFF) && defined (TE_PE)
10679 /* For some reason, the PE format does not store a
10680 section address offset for a PC relative symbol. */
10681 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
10682 || S_IS_WEAK (fixP
->fx_addsy
))
10683 value
+= md_pcrel_from (fixP
);
10686 #if defined (OBJ_COFF) && defined (TE_PE)
10687 if (fixP
->fx_addsy
!= NULL
10688 && S_IS_WEAK (fixP
->fx_addsy
)
10689 /* PR 16858: Do not modify weak function references. */
10690 && ! fixP
->fx_pcrel
)
10692 #if !defined (TE_PEP)
10693 /* For x86 PE weak function symbols are neither PC-relative
10694 nor do they set S_IS_FUNCTION. So the only reliable way
10695 to detect them is to check the flags of their containing
10697 if (S_GET_SEGMENT (fixP
->fx_addsy
) != NULL
10698 && S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_CODE
)
10702 value
-= S_GET_VALUE (fixP
->fx_addsy
);
10706 /* Fix a few things - the dynamic linker expects certain values here,
10707 and we must not disappoint it. */
10708 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10709 if (IS_ELF
&& fixP
->fx_addsy
)
10710 switch (fixP
->fx_r_type
)
10712 case BFD_RELOC_386_PLT32
:
10713 case BFD_RELOC_X86_64_PLT32
:
10714 /* Make the jump instruction point to the address of the operand.
10715 At runtime we merely add the offset to the actual PLT entry.
10716 NB: Subtract the offset size only for jump instructions. */
10717 if (fixP
->fx_pcrel
)
10721 case BFD_RELOC_386_TLS_GD
:
10722 case BFD_RELOC_386_TLS_LDM
:
10723 case BFD_RELOC_386_TLS_IE_32
:
10724 case BFD_RELOC_386_TLS_IE
:
10725 case BFD_RELOC_386_TLS_GOTIE
:
10726 case BFD_RELOC_386_TLS_GOTDESC
:
10727 case BFD_RELOC_X86_64_TLSGD
:
10728 case BFD_RELOC_X86_64_TLSLD
:
10729 case BFD_RELOC_X86_64_GOTTPOFF
:
10730 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
10731 value
= 0; /* Fully resolved at runtime. No addend. */
10733 case BFD_RELOC_386_TLS_LE
:
10734 case BFD_RELOC_386_TLS_LDO_32
:
10735 case BFD_RELOC_386_TLS_LE_32
:
10736 case BFD_RELOC_X86_64_DTPOFF32
:
10737 case BFD_RELOC_X86_64_DTPOFF64
:
10738 case BFD_RELOC_X86_64_TPOFF32
:
10739 case BFD_RELOC_X86_64_TPOFF64
:
10740 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
10743 case BFD_RELOC_386_TLS_DESC_CALL
:
10744 case BFD_RELOC_X86_64_TLSDESC_CALL
:
10745 value
= 0; /* Fully resolved at runtime. No addend. */
10746 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
10750 case BFD_RELOC_VTABLE_INHERIT
:
10751 case BFD_RELOC_VTABLE_ENTRY
:
10758 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
10760 #endif /* !defined (TE_Mach) */
10762 /* Are we finished with this relocation now? */
10763 if (fixP
->fx_addsy
== NULL
)
10765 #if defined (OBJ_COFF) && defined (TE_PE)
10766 else if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
10769 /* Remember value for tc_gen_reloc. */
10770 fixP
->fx_addnumber
= value
;
10771 /* Clear out the frag for now. */
10775 else if (use_rela_relocations
)
10777 fixP
->fx_no_overflow
= 1;
10778 /* Remember value for tc_gen_reloc. */
10779 fixP
->fx_addnumber
= value
;
10783 md_number_to_chars (p
, value
, fixP
->fx_size
);
10787 md_atof (int type
, char *litP
, int *sizeP
)
10789 /* This outputs the LITTLENUMs in REVERSE order;
10790 in accord with the bigendian 386. */
10791 return ieee_md_atof (type
, litP
, sizeP
, FALSE
);
10794 static char output_invalid_buf
[sizeof (unsigned char) * 2 + 6];
10797 output_invalid (int c
)
10800 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
10803 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
10804 "(0x%x)", (unsigned char) c
);
10805 return output_invalid_buf
;
10808 /* REG_STRING starts *before* REGISTER_PREFIX. */
10810 static const reg_entry
*
10811 parse_real_register (char *reg_string
, char **end_op
)
10813 char *s
= reg_string
;
10815 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
10816 const reg_entry
*r
;
10818 /* Skip possible REGISTER_PREFIX and possible whitespace. */
10819 if (*s
== REGISTER_PREFIX
)
10822 if (is_space_char (*s
))
10825 p
= reg_name_given
;
10826 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
10828 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
10829 return (const reg_entry
*) NULL
;
10833 /* For naked regs, make sure that we are not dealing with an identifier.
10834 This prevents confusing an identifier like `eax_var' with register
10836 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
10837 return (const reg_entry
*) NULL
;
10841 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
10843 /* Handle floating point regs, allowing spaces in the (i) part. */
10844 if (r
== i386_regtab
/* %st is first entry of table */)
10846 if (!cpu_arch_flags
.bitfield
.cpu8087
10847 && !cpu_arch_flags
.bitfield
.cpu287
10848 && !cpu_arch_flags
.bitfield
.cpu387
)
10849 return (const reg_entry
*) NULL
;
10851 if (is_space_char (*s
))
10856 if (is_space_char (*s
))
10858 if (*s
>= '0' && *s
<= '7')
10860 int fpr
= *s
- '0';
10862 if (is_space_char (*s
))
10867 r
= (const reg_entry
*) hash_find (reg_hash
, "st(0)");
10872 /* We have "%st(" then garbage. */
10873 return (const reg_entry
*) NULL
;
10877 if (r
== NULL
|| allow_pseudo_reg
)
10880 if (operand_type_all_zero (&r
->reg_type
))
10881 return (const reg_entry
*) NULL
;
10883 if ((r
->reg_type
.bitfield
.dword
10884 || (r
->reg_type
.bitfield
.class == SReg
&& r
->reg_num
> 3)
10885 || r
->reg_type
.bitfield
.class == RegCR
10886 || r
->reg_type
.bitfield
.class == RegDR
10887 || r
->reg_type
.bitfield
.class == RegTR
)
10888 && !cpu_arch_flags
.bitfield
.cpui386
)
10889 return (const reg_entry
*) NULL
;
10891 if (r
->reg_type
.bitfield
.class == RegMMX
&& !cpu_arch_flags
.bitfield
.cpummx
)
10892 return (const reg_entry
*) NULL
;
10894 if (!cpu_arch_flags
.bitfield
.cpuavx512f
)
10896 if (r
->reg_type
.bitfield
.zmmword
10897 || r
->reg_type
.bitfield
.class == RegMask
)
10898 return (const reg_entry
*) NULL
;
10900 if (!cpu_arch_flags
.bitfield
.cpuavx
)
10902 if (r
->reg_type
.bitfield
.ymmword
)
10903 return (const reg_entry
*) NULL
;
10905 if (!cpu_arch_flags
.bitfield
.cpusse
&& r
->reg_type
.bitfield
.xmmword
)
10906 return (const reg_entry
*) NULL
;
10910 if (r
->reg_type
.bitfield
.class == RegBND
&& !cpu_arch_flags
.bitfield
.cpumpx
)
10911 return (const reg_entry
*) NULL
;
10913 /* Don't allow fake index register unless allow_index_reg isn't 0. */
10914 if (!allow_index_reg
&& r
->reg_num
== RegIZ
)
10915 return (const reg_entry
*) NULL
;
10917 /* Upper 16 vector registers are only available with VREX in 64bit
10918 mode, and require EVEX encoding. */
10919 if (r
->reg_flags
& RegVRex
)
10921 if (!cpu_arch_flags
.bitfield
.cpuavx512f
10922 || flag_code
!= CODE_64BIT
)
10923 return (const reg_entry
*) NULL
;
10925 i
.vec_encoding
= vex_encoding_evex
;
10928 if (((r
->reg_flags
& (RegRex64
| RegRex
)) || r
->reg_type
.bitfield
.qword
)
10929 && (!cpu_arch_flags
.bitfield
.cpulm
|| r
->reg_type
.bitfield
.class != RegCR
)
10930 && flag_code
!= CODE_64BIT
)
10931 return (const reg_entry
*) NULL
;
10933 if (r
->reg_type
.bitfield
.class == SReg
&& r
->reg_num
== RegFlat
10935 return (const reg_entry
*) NULL
;
10940 /* REG_STRING starts *before* REGISTER_PREFIX. */
10942 static const reg_entry
*
10943 parse_register (char *reg_string
, char **end_op
)
10945 const reg_entry
*r
;
10947 if (*reg_string
== REGISTER_PREFIX
|| allow_naked_reg
)
10948 r
= parse_real_register (reg_string
, end_op
);
10953 char *save
= input_line_pointer
;
10957 input_line_pointer
= reg_string
;
10958 c
= get_symbol_name (®_string
);
10959 symbolP
= symbol_find (reg_string
);
10960 if (symbolP
&& S_GET_SEGMENT (symbolP
) == reg_section
)
10962 const expressionS
*e
= symbol_get_value_expression (symbolP
);
10964 know (e
->X_op
== O_register
);
10965 know (e
->X_add_number
>= 0
10966 && (valueT
) e
->X_add_number
< i386_regtab_size
);
10967 r
= i386_regtab
+ e
->X_add_number
;
10968 if ((r
->reg_flags
& RegVRex
))
10969 i
.vec_encoding
= vex_encoding_evex
;
10970 *end_op
= input_line_pointer
;
10972 *input_line_pointer
= c
;
10973 input_line_pointer
= save
;
10979 i386_parse_name (char *name
, expressionS
*e
, char *nextcharP
)
10981 const reg_entry
*r
;
10982 char *end
= input_line_pointer
;
10985 r
= parse_register (name
, &input_line_pointer
);
10986 if (r
&& end
<= input_line_pointer
)
10988 *nextcharP
= *input_line_pointer
;
10989 *input_line_pointer
= 0;
10990 e
->X_op
= O_register
;
10991 e
->X_add_number
= r
- i386_regtab
;
10994 input_line_pointer
= end
;
10996 return intel_syntax
? i386_intel_parse_name (name
, e
) : 0;
11000 md_operand (expressionS
*e
)
11003 const reg_entry
*r
;
11005 switch (*input_line_pointer
)
11007 case REGISTER_PREFIX
:
11008 r
= parse_real_register (input_line_pointer
, &end
);
11011 e
->X_op
= O_register
;
11012 e
->X_add_number
= r
- i386_regtab
;
11013 input_line_pointer
= end
;
11018 gas_assert (intel_syntax
);
11019 end
= input_line_pointer
++;
11021 if (*input_line_pointer
== ']')
11023 ++input_line_pointer
;
11024 e
->X_op_symbol
= make_expr_symbol (e
);
11025 e
->X_add_symbol
= NULL
;
11026 e
->X_add_number
= 0;
11031 e
->X_op
= O_absent
;
11032 input_line_pointer
= end
;
11039 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11040 const char *md_shortopts
= "kVQ:sqnO::";
11042 const char *md_shortopts
= "qnO::";
11045 #define OPTION_32 (OPTION_MD_BASE + 0)
11046 #define OPTION_64 (OPTION_MD_BASE + 1)
11047 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
11048 #define OPTION_MARCH (OPTION_MD_BASE + 3)
11049 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
11050 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
11051 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
11052 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
11053 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
11054 #define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 9)
11055 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
11056 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
11057 #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
11058 #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
11059 #define OPTION_X32 (OPTION_MD_BASE + 14)
11060 #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
11061 #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
11062 #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
11063 #define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
11064 #define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
11065 #define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
11066 #define OPTION_MSHARED (OPTION_MD_BASE + 21)
11067 #define OPTION_MAMD64 (OPTION_MD_BASE + 22)
11068 #define OPTION_MINTEL64 (OPTION_MD_BASE + 23)
11069 #define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24)
11070 #define OPTION_X86_USED_NOTE (OPTION_MD_BASE + 25)
11071 #define OPTION_MVEXWIG (OPTION_MD_BASE + 26)
11073 struct option md_longopts
[] =
11075 {"32", no_argument
, NULL
, OPTION_32
},
11076 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
11077 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
11078 {"64", no_argument
, NULL
, OPTION_64
},
11080 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11081 {"x32", no_argument
, NULL
, OPTION_X32
},
11082 {"mshared", no_argument
, NULL
, OPTION_MSHARED
},
11083 {"mx86-used-note", required_argument
, NULL
, OPTION_X86_USED_NOTE
},
11085 {"divide", no_argument
, NULL
, OPTION_DIVIDE
},
11086 {"march", required_argument
, NULL
, OPTION_MARCH
},
11087 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
11088 {"mmnemonic", required_argument
, NULL
, OPTION_MMNEMONIC
},
11089 {"msyntax", required_argument
, NULL
, OPTION_MSYNTAX
},
11090 {"mindex-reg", no_argument
, NULL
, OPTION_MINDEX_REG
},
11091 {"mnaked-reg", no_argument
, NULL
, OPTION_MNAKED_REG
},
11092 {"msse2avx", no_argument
, NULL
, OPTION_MSSE2AVX
},
11093 {"msse-check", required_argument
, NULL
, OPTION_MSSE_CHECK
},
11094 {"moperand-check", required_argument
, NULL
, OPTION_MOPERAND_CHECK
},
11095 {"mavxscalar", required_argument
, NULL
, OPTION_MAVXSCALAR
},
11096 {"mvexwig", required_argument
, NULL
, OPTION_MVEXWIG
},
11097 {"madd-bnd-prefix", no_argument
, NULL
, OPTION_MADD_BND_PREFIX
},
11098 {"mevexlig", required_argument
, NULL
, OPTION_MEVEXLIG
},
11099 {"mevexwig", required_argument
, NULL
, OPTION_MEVEXWIG
},
11100 # if defined (TE_PE) || defined (TE_PEP)
11101 {"mbig-obj", no_argument
, NULL
, OPTION_MBIG_OBJ
},
11103 {"momit-lock-prefix", required_argument
, NULL
, OPTION_MOMIT_LOCK_PREFIX
},
11104 {"mfence-as-lock-add", required_argument
, NULL
, OPTION_MFENCE_AS_LOCK_ADD
},
11105 {"mrelax-relocations", required_argument
, NULL
, OPTION_MRELAX_RELOCATIONS
},
11106 {"mevexrcig", required_argument
, NULL
, OPTION_MEVEXRCIG
},
11107 {"mamd64", no_argument
, NULL
, OPTION_MAMD64
},
11108 {"mintel64", no_argument
, NULL
, OPTION_MINTEL64
},
11109 {NULL
, no_argument
, NULL
, 0}
11111 size_t md_longopts_size
= sizeof (md_longopts
);
11114 md_parse_option (int c
, const char *arg
)
11117 char *arch
, *next
, *saved
;
11122 optimize_align_code
= 0;
11126 quiet_warnings
= 1;
11129 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11130 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
11131 should be emitted or not. FIXME: Not implemented. */
11133 if ((arg
[0] != 'y' && arg
[0] != 'n') || arg
[1])
11137 /* -V: SVR4 argument to print version ID. */
11139 print_version_id ();
11142 /* -k: Ignore for FreeBSD compatibility. */
11147 /* -s: On i386 Solaris, this tells the native assembler to use
11148 .stab instead of .stab.excl. We always use .stab anyhow. */
11151 case OPTION_MSHARED
:
11155 case OPTION_X86_USED_NOTE
:
11156 if (strcasecmp (arg
, "yes") == 0)
11158 else if (strcasecmp (arg
, "no") == 0)
11161 as_fatal (_("invalid -mx86-used-note= option: `%s'"), arg
);
11166 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
11167 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
11170 const char **list
, **l
;
11172 list
= bfd_target_list ();
11173 for (l
= list
; *l
!= NULL
; l
++)
11174 if (CONST_STRNEQ (*l
, "elf64-x86-64")
11175 || strcmp (*l
, "coff-x86-64") == 0
11176 || strcmp (*l
, "pe-x86-64") == 0
11177 || strcmp (*l
, "pei-x86-64") == 0
11178 || strcmp (*l
, "mach-o-x86-64") == 0)
11180 default_arch
= "x86_64";
11184 as_fatal (_("no compiled in support for x86_64"));
11190 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11194 const char **list
, **l
;
11196 list
= bfd_target_list ();
11197 for (l
= list
; *l
!= NULL
; l
++)
11198 if (CONST_STRNEQ (*l
, "elf32-x86-64"))
11200 default_arch
= "x86_64:32";
11204 as_fatal (_("no compiled in support for 32bit x86_64"));
11208 as_fatal (_("32bit x86_64 is only supported for ELF"));
11213 default_arch
= "i386";
11216 case OPTION_DIVIDE
:
11217 #ifdef SVR4_COMMENT_CHARS
11222 n
= XNEWVEC (char, strlen (i386_comment_chars
) + 1);
11224 for (s
= i386_comment_chars
; *s
!= '\0'; s
++)
11228 i386_comment_chars
= n
;
11234 saved
= xstrdup (arg
);
11236 /* Allow -march=+nosse. */
11242 as_fatal (_("invalid -march= option: `%s'"), arg
);
11243 next
= strchr (arch
, '+');
11246 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
11248 if (strcmp (arch
, cpu_arch
[j
].name
) == 0)
11251 if (! cpu_arch
[j
].flags
.bitfield
.cpui386
)
11254 cpu_arch_name
= cpu_arch
[j
].name
;
11255 cpu_sub_arch_name
= NULL
;
11256 cpu_arch_flags
= cpu_arch
[j
].flags
;
11257 cpu_arch_isa
= cpu_arch
[j
].type
;
11258 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
11259 if (!cpu_arch_tune_set
)
11261 cpu_arch_tune
= cpu_arch_isa
;
11262 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
11266 else if (*cpu_arch
[j
].name
== '.'
11267 && strcmp (arch
, cpu_arch
[j
].name
+ 1) == 0)
11269 /* ISA extension. */
11270 i386_cpu_flags flags
;
11272 flags
= cpu_flags_or (cpu_arch_flags
,
11273 cpu_arch
[j
].flags
);
11275 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
11277 if (cpu_sub_arch_name
)
11279 char *name
= cpu_sub_arch_name
;
11280 cpu_sub_arch_name
= concat (name
,
11282 (const char *) NULL
);
11286 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
11287 cpu_arch_flags
= flags
;
11288 cpu_arch_isa_flags
= flags
;
11292 = cpu_flags_or (cpu_arch_isa_flags
,
11293 cpu_arch
[j
].flags
);
11298 if (j
>= ARRAY_SIZE (cpu_arch
))
11300 /* Disable an ISA extension. */
11301 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
11302 if (strcmp (arch
, cpu_noarch
[j
].name
) == 0)
11304 i386_cpu_flags flags
;
11306 flags
= cpu_flags_and_not (cpu_arch_flags
,
11307 cpu_noarch
[j
].flags
);
11308 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
11310 if (cpu_sub_arch_name
)
11312 char *name
= cpu_sub_arch_name
;
11313 cpu_sub_arch_name
= concat (arch
,
11314 (const char *) NULL
);
11318 cpu_sub_arch_name
= xstrdup (arch
);
11319 cpu_arch_flags
= flags
;
11320 cpu_arch_isa_flags
= flags
;
11325 if (j
>= ARRAY_SIZE (cpu_noarch
))
11326 j
= ARRAY_SIZE (cpu_arch
);
11329 if (j
>= ARRAY_SIZE (cpu_arch
))
11330 as_fatal (_("invalid -march= option: `%s'"), arg
);
11334 while (next
!= NULL
);
11340 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
11341 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
11343 if (strcmp (arg
, cpu_arch
[j
].name
) == 0)
11345 cpu_arch_tune_set
= 1;
11346 cpu_arch_tune
= cpu_arch
[j
].type
;
11347 cpu_arch_tune_flags
= cpu_arch
[j
].flags
;
11351 if (j
>= ARRAY_SIZE (cpu_arch
))
11352 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
11355 case OPTION_MMNEMONIC
:
11356 if (strcasecmp (arg
, "att") == 0)
11357 intel_mnemonic
= 0;
11358 else if (strcasecmp (arg
, "intel") == 0)
11359 intel_mnemonic
= 1;
11361 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg
);
11364 case OPTION_MSYNTAX
:
11365 if (strcasecmp (arg
, "att") == 0)
11367 else if (strcasecmp (arg
, "intel") == 0)
11370 as_fatal (_("invalid -msyntax= option: `%s'"), arg
);
11373 case OPTION_MINDEX_REG
:
11374 allow_index_reg
= 1;
11377 case OPTION_MNAKED_REG
:
11378 allow_naked_reg
= 1;
11381 case OPTION_MSSE2AVX
:
11385 case OPTION_MSSE_CHECK
:
11386 if (strcasecmp (arg
, "error") == 0)
11387 sse_check
= check_error
;
11388 else if (strcasecmp (arg
, "warning") == 0)
11389 sse_check
= check_warning
;
11390 else if (strcasecmp (arg
, "none") == 0)
11391 sse_check
= check_none
;
11393 as_fatal (_("invalid -msse-check= option: `%s'"), arg
);
11396 case OPTION_MOPERAND_CHECK
:
11397 if (strcasecmp (arg
, "error") == 0)
11398 operand_check
= check_error
;
11399 else if (strcasecmp (arg
, "warning") == 0)
11400 operand_check
= check_warning
;
11401 else if (strcasecmp (arg
, "none") == 0)
11402 operand_check
= check_none
;
11404 as_fatal (_("invalid -moperand-check= option: `%s'"), arg
);
11407 case OPTION_MAVXSCALAR
:
11408 if (strcasecmp (arg
, "128") == 0)
11409 avxscalar
= vex128
;
11410 else if (strcasecmp (arg
, "256") == 0)
11411 avxscalar
= vex256
;
11413 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg
);
11416 case OPTION_MVEXWIG
:
11417 if (strcmp (arg
, "0") == 0)
11419 else if (strcmp (arg
, "1") == 0)
11422 as_fatal (_("invalid -mvexwig= option: `%s'"), arg
);
11425 case OPTION_MADD_BND_PREFIX
:
11426 add_bnd_prefix
= 1;
11429 case OPTION_MEVEXLIG
:
11430 if (strcmp (arg
, "128") == 0)
11431 evexlig
= evexl128
;
11432 else if (strcmp (arg
, "256") == 0)
11433 evexlig
= evexl256
;
11434 else if (strcmp (arg
, "512") == 0)
11435 evexlig
= evexl512
;
11437 as_fatal (_("invalid -mevexlig= option: `%s'"), arg
);
11440 case OPTION_MEVEXRCIG
:
11441 if (strcmp (arg
, "rne") == 0)
11443 else if (strcmp (arg
, "rd") == 0)
11445 else if (strcmp (arg
, "ru") == 0)
11447 else if (strcmp (arg
, "rz") == 0)
11450 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg
);
11453 case OPTION_MEVEXWIG
:
11454 if (strcmp (arg
, "0") == 0)
11456 else if (strcmp (arg
, "1") == 0)
11459 as_fatal (_("invalid -mevexwig= option: `%s'"), arg
);
11462 # if defined (TE_PE) || defined (TE_PEP)
11463 case OPTION_MBIG_OBJ
:
11468 case OPTION_MOMIT_LOCK_PREFIX
:
11469 if (strcasecmp (arg
, "yes") == 0)
11470 omit_lock_prefix
= 1;
11471 else if (strcasecmp (arg
, "no") == 0)
11472 omit_lock_prefix
= 0;
11474 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg
);
11477 case OPTION_MFENCE_AS_LOCK_ADD
:
11478 if (strcasecmp (arg
, "yes") == 0)
11480 else if (strcasecmp (arg
, "no") == 0)
11483 as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg
);
11486 case OPTION_MRELAX_RELOCATIONS
:
11487 if (strcasecmp (arg
, "yes") == 0)
11488 generate_relax_relocations
= 1;
11489 else if (strcasecmp (arg
, "no") == 0)
11490 generate_relax_relocations
= 0;
11492 as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg
);
11495 case OPTION_MAMD64
:
11499 case OPTION_MINTEL64
:
11507 /* Turn off -Os. */
11508 optimize_for_space
= 0;
11510 else if (*arg
== 's')
11512 optimize_for_space
= 1;
11513 /* Turn on all encoding optimizations. */
11514 optimize
= INT_MAX
;
11518 optimize
= atoi (arg
);
11519 /* Turn off -Os. */
11520 optimize_for_space
= 0;
11530 #define MESSAGE_TEMPLATE \
11534 output_message (FILE *stream
, char *p
, char *message
, char *start
,
11535 int *left_p
, const char *name
, int len
)
11537 int size
= sizeof (MESSAGE_TEMPLATE
);
11538 int left
= *left_p
;
11540 /* Reserve 2 spaces for ", " or ",\0" */
11543 /* Check if there is any room. */
11551 p
= mempcpy (p
, name
, len
);
11555 /* Output the current message now and start a new one. */
11558 fprintf (stream
, "%s\n", message
);
11560 left
= size
- (start
- message
) - len
- 2;
11562 gas_assert (left
>= 0);
11564 p
= mempcpy (p
, name
, len
);
11572 show_arch (FILE *stream
, int ext
, int check
)
11574 static char message
[] = MESSAGE_TEMPLATE
;
11575 char *start
= message
+ 27;
11577 int size
= sizeof (MESSAGE_TEMPLATE
);
11584 left
= size
- (start
- message
);
11585 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
11587 /* Should it be skipped? */
11588 if (cpu_arch
[j
].skip
)
11591 name
= cpu_arch
[j
].name
;
11592 len
= cpu_arch
[j
].len
;
11595 /* It is an extension. Skip if we aren't asked to show it. */
11606 /* It is an processor. Skip if we show only extension. */
11609 else if (check
&& ! cpu_arch
[j
].flags
.bitfield
.cpui386
)
11611 /* It is an impossible processor - skip. */
11615 p
= output_message (stream
, p
, message
, start
, &left
, name
, len
);
11618 /* Display disabled extensions. */
11620 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
11622 name
= cpu_noarch
[j
].name
;
11623 len
= cpu_noarch
[j
].len
;
11624 p
= output_message (stream
, p
, message
, start
, &left
, name
,
11629 fprintf (stream
, "%s\n", message
);
11633 md_show_usage (FILE *stream
)
11635 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11636 fprintf (stream
, _("\
11637 -Qy, -Qn ignored\n\
11638 -V print assembler version number\n\
11641 fprintf (stream
, _("\
11642 -n Do not optimize code alignment\n\
11643 -q quieten some warnings\n"));
11644 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11645 fprintf (stream
, _("\
11648 #if defined BFD64 && (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
11649 || defined (TE_PE) || defined (TE_PEP))
11650 fprintf (stream
, _("\
11651 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
11653 #ifdef SVR4_COMMENT_CHARS
11654 fprintf (stream
, _("\
11655 --divide do not treat `/' as a comment character\n"));
11657 fprintf (stream
, _("\
11658 --divide ignored\n"));
11660 fprintf (stream
, _("\
11661 -march=CPU[,+EXTENSION...]\n\
11662 generate code for CPU and EXTENSION, CPU is one of:\n"));
11663 show_arch (stream
, 0, 1);
11664 fprintf (stream
, _("\
11665 EXTENSION is combination of:\n"));
11666 show_arch (stream
, 1, 0);
11667 fprintf (stream
, _("\
11668 -mtune=CPU optimize for CPU, CPU is one of:\n"));
11669 show_arch (stream
, 0, 0);
11670 fprintf (stream
, _("\
11671 -msse2avx encode SSE instructions with VEX prefix\n"));
11672 fprintf (stream
, _("\
11673 -msse-check=[none|error|warning] (default: warning)\n\
11674 check SSE instructions\n"));
11675 fprintf (stream
, _("\
11676 -moperand-check=[none|error|warning] (default: warning)\n\
11677 check operand combinations for validity\n"));
11678 fprintf (stream
, _("\
11679 -mavxscalar=[128|256] (default: 128)\n\
11680 encode scalar AVX instructions with specific vector\n\
11682 fprintf (stream
, _("\
11683 -mvexwig=[0|1] (default: 0)\n\
11684 encode VEX instructions with specific VEX.W value\n\
11685 for VEX.W bit ignored instructions\n"));
11686 fprintf (stream
, _("\
11687 -mevexlig=[128|256|512] (default: 128)\n\
11688 encode scalar EVEX instructions with specific vector\n\
11690 fprintf (stream
, _("\
11691 -mevexwig=[0|1] (default: 0)\n\
11692 encode EVEX instructions with specific EVEX.W value\n\
11693 for EVEX.W bit ignored instructions\n"));
11694 fprintf (stream
, _("\
11695 -mevexrcig=[rne|rd|ru|rz] (default: rne)\n\
11696 encode EVEX instructions with specific EVEX.RC value\n\
11697 for SAE-only ignored instructions\n"));
11698 fprintf (stream
, _("\
11699 -mmnemonic=[att|intel] "));
11700 if (SYSV386_COMPAT
)
11701 fprintf (stream
, _("(default: att)\n"));
11703 fprintf (stream
, _("(default: intel)\n"));
11704 fprintf (stream
, _("\
11705 use AT&T/Intel mnemonic\n"));
11706 fprintf (stream
, _("\
11707 -msyntax=[att|intel] (default: att)\n\
11708 use AT&T/Intel syntax\n"));
11709 fprintf (stream
, _("\
11710 -mindex-reg support pseudo index registers\n"));
11711 fprintf (stream
, _("\
11712 -mnaked-reg don't require `%%' prefix for registers\n"));
11713 fprintf (stream
, _("\
11714 -madd-bnd-prefix add BND prefix for all valid branches\n"));
11715 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11716 fprintf (stream
, _("\
11717 -mshared disable branch optimization for shared code\n"));
11718 fprintf (stream
, _("\
11719 -mx86-used-note=[no|yes] "));
11720 if (DEFAULT_X86_USED_NOTE
)
11721 fprintf (stream
, _("(default: yes)\n"));
11723 fprintf (stream
, _("(default: no)\n"));
11724 fprintf (stream
, _("\
11725 generate x86 used ISA and feature properties\n"));
11727 #if defined (TE_PE) || defined (TE_PEP)
11728 fprintf (stream
, _("\
11729 -mbig-obj generate big object files\n"));
11731 fprintf (stream
, _("\
11732 -momit-lock-prefix=[no|yes] (default: no)\n\
11733 strip all lock prefixes\n"));
11734 fprintf (stream
, _("\
11735 -mfence-as-lock-add=[no|yes] (default: no)\n\
11736 encode lfence, mfence and sfence as\n\
11737 lock addl $0x0, (%%{re}sp)\n"));
11738 fprintf (stream
, _("\
11739 -mrelax-relocations=[no|yes] "));
11740 if (DEFAULT_GENERATE_X86_RELAX_RELOCATIONS
)
11741 fprintf (stream
, _("(default: yes)\n"));
11743 fprintf (stream
, _("(default: no)\n"));
11744 fprintf (stream
, _("\
11745 generate relax relocations\n"));
11746 fprintf (stream
, _("\
11747 -mamd64 accept only AMD64 ISA [default]\n"));
11748 fprintf (stream
, _("\
11749 -mintel64 accept only Intel64 ISA\n"));
11752 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
11753 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
11754 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
11756 /* Pick the target format to use. */
11759 i386_target_format (void)
11761 if (!strncmp (default_arch
, "x86_64", 6))
11763 update_code_flag (CODE_64BIT
, 1);
11764 if (default_arch
[6] == '\0')
11765 x86_elf_abi
= X86_64_ABI
;
11767 x86_elf_abi
= X86_64_X32_ABI
;
11769 else if (!strcmp (default_arch
, "i386"))
11770 update_code_flag (CODE_32BIT
, 1);
11771 else if (!strcmp (default_arch
, "iamcu"))
11773 update_code_flag (CODE_32BIT
, 1);
11774 if (cpu_arch_isa
== PROCESSOR_UNKNOWN
)
11776 static const i386_cpu_flags iamcu_flags
= CPU_IAMCU_FLAGS
;
11777 cpu_arch_name
= "iamcu";
11778 cpu_sub_arch_name
= NULL
;
11779 cpu_arch_flags
= iamcu_flags
;
11780 cpu_arch_isa
= PROCESSOR_IAMCU
;
11781 cpu_arch_isa_flags
= iamcu_flags
;
11782 if (!cpu_arch_tune_set
)
11784 cpu_arch_tune
= cpu_arch_isa
;
11785 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
11788 else if (cpu_arch_isa
!= PROCESSOR_IAMCU
)
11789 as_fatal (_("Intel MCU doesn't support `%s' architecture"),
11793 as_fatal (_("unknown architecture"));
11795 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
11796 cpu_arch_isa_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
11797 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
11798 cpu_arch_tune_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
11800 switch (OUTPUT_FLAVOR
)
11802 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
11803 case bfd_target_aout_flavour
:
11804 return AOUT_TARGET_FORMAT
;
11806 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
11807 # if defined (TE_PE) || defined (TE_PEP)
11808 case bfd_target_coff_flavour
:
11809 if (flag_code
== CODE_64BIT
)
11810 return use_big_obj
? "pe-bigobj-x86-64" : "pe-x86-64";
11813 # elif defined (TE_GO32)
11814 case bfd_target_coff_flavour
:
11815 return "coff-go32";
11817 case bfd_target_coff_flavour
:
11818 return "coff-i386";
11821 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
11822 case bfd_target_elf_flavour
:
11824 const char *format
;
11826 switch (x86_elf_abi
)
11829 format
= ELF_TARGET_FORMAT
;
11832 use_rela_relocations
= 1;
11834 format
= ELF_TARGET_FORMAT64
;
11836 case X86_64_X32_ABI
:
11837 use_rela_relocations
= 1;
11839 disallow_64bit_reloc
= 1;
11840 format
= ELF_TARGET_FORMAT32
;
11843 if (cpu_arch_isa
== PROCESSOR_L1OM
)
11845 if (x86_elf_abi
!= X86_64_ABI
)
11846 as_fatal (_("Intel L1OM is 64bit only"));
11847 return ELF_TARGET_L1OM_FORMAT
;
11849 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
11851 if (x86_elf_abi
!= X86_64_ABI
)
11852 as_fatal (_("Intel K1OM is 64bit only"));
11853 return ELF_TARGET_K1OM_FORMAT
;
11855 else if (cpu_arch_isa
== PROCESSOR_IAMCU
)
11857 if (x86_elf_abi
!= I386_ABI
)
11858 as_fatal (_("Intel MCU is 32bit only"));
11859 return ELF_TARGET_IAMCU_FORMAT
;
11865 #if defined (OBJ_MACH_O)
11866 case bfd_target_mach_o_flavour
:
11867 if (flag_code
== CODE_64BIT
)
11869 use_rela_relocations
= 1;
11871 return "mach-o-x86-64";
11874 return "mach-o-i386";
11882 #endif /* OBJ_MAYBE_ more than one */
11885 md_undefined_symbol (char *name
)
11887 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
11888 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
11889 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
11890 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
11894 if (symbol_find (name
))
11895 as_bad (_("GOT already in symbol table"));
11896 GOT_symbol
= symbol_new (name
, undefined_section
,
11897 (valueT
) 0, &zero_address_frag
);
11904 /* Round up a section size to the appropriate boundary. */
11907 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
11909 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
11910 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
11912 /* For a.out, force the section size to be aligned. If we don't do
11913 this, BFD will align it for us, but it will not write out the
11914 final bytes of the section. This may be a bug in BFD, but it is
11915 easier to fix it here since that is how the other a.out targets
11919 align
= bfd_section_alignment (segment
);
11920 size
= ((size
+ (1 << align
) - 1) & (-((valueT
) 1 << align
)));
11927 /* On the i386, PC-relative offsets are relative to the start of the
11928 next instruction. That is, the address of the offset, plus its
11929 size, since the offset is always the last part of the insn. */
11932 md_pcrel_from (fixS
*fixP
)
11934 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
11940 s_bss (int ignore ATTRIBUTE_UNUSED
)
11944 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11946 obj_elf_section_change_hook ();
11948 temp
= get_absolute_expression ();
11949 subseg_set (bss_section
, (subsegT
) temp
);
11950 demand_empty_rest_of_line ();
11956 i386_validate_fix (fixS
*fixp
)
11958 if (fixp
->fx_subsy
)
11960 if (fixp
->fx_subsy
== GOT_symbol
)
11962 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
11966 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11967 if (fixp
->fx_tcbit2
)
11968 fixp
->fx_r_type
= (fixp
->fx_tcbit
11969 ? BFD_RELOC_X86_64_REX_GOTPCRELX
11970 : BFD_RELOC_X86_64_GOTPCRELX
);
11973 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
11978 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
11980 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
11982 fixp
->fx_subsy
= 0;
11985 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11986 else if (!object_64bit
)
11988 if (fixp
->fx_r_type
== BFD_RELOC_386_GOT32
11989 && fixp
->fx_tcbit2
)
11990 fixp
->fx_r_type
= BFD_RELOC_386_GOT32X
;
11996 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
11999 bfd_reloc_code_real_type code
;
12001 switch (fixp
->fx_r_type
)
12003 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12004 case BFD_RELOC_SIZE32
:
12005 case BFD_RELOC_SIZE64
:
12006 if (S_IS_DEFINED (fixp
->fx_addsy
)
12007 && !S_IS_EXTERNAL (fixp
->fx_addsy
))
12009 /* Resolve size relocation against local symbol to size of
12010 the symbol plus addend. */
12011 valueT value
= S_GET_SIZE (fixp
->fx_addsy
) + fixp
->fx_offset
;
12012 if (fixp
->fx_r_type
== BFD_RELOC_SIZE32
12013 && !fits_in_unsigned_long (value
))
12014 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
12015 _("symbol size computation overflow"));
12016 fixp
->fx_addsy
= NULL
;
12017 fixp
->fx_subsy
= NULL
;
12018 md_apply_fix (fixp
, (valueT
*) &value
, NULL
);
12022 /* Fall through. */
12024 case BFD_RELOC_X86_64_PLT32
:
12025 case BFD_RELOC_X86_64_GOT32
:
12026 case BFD_RELOC_X86_64_GOTPCREL
:
12027 case BFD_RELOC_X86_64_GOTPCRELX
:
12028 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
12029 case BFD_RELOC_386_PLT32
:
12030 case BFD_RELOC_386_GOT32
:
12031 case BFD_RELOC_386_GOT32X
:
12032 case BFD_RELOC_386_GOTOFF
:
12033 case BFD_RELOC_386_GOTPC
:
12034 case BFD_RELOC_386_TLS_GD
:
12035 case BFD_RELOC_386_TLS_LDM
:
12036 case BFD_RELOC_386_TLS_LDO_32
:
12037 case BFD_RELOC_386_TLS_IE_32
:
12038 case BFD_RELOC_386_TLS_IE
:
12039 case BFD_RELOC_386_TLS_GOTIE
:
12040 case BFD_RELOC_386_TLS_LE_32
:
12041 case BFD_RELOC_386_TLS_LE
:
12042 case BFD_RELOC_386_TLS_GOTDESC
:
12043 case BFD_RELOC_386_TLS_DESC_CALL
:
12044 case BFD_RELOC_X86_64_TLSGD
:
12045 case BFD_RELOC_X86_64_TLSLD
:
12046 case BFD_RELOC_X86_64_DTPOFF32
:
12047 case BFD_RELOC_X86_64_DTPOFF64
:
12048 case BFD_RELOC_X86_64_GOTTPOFF
:
12049 case BFD_RELOC_X86_64_TPOFF32
:
12050 case BFD_RELOC_X86_64_TPOFF64
:
12051 case BFD_RELOC_X86_64_GOTOFF64
:
12052 case BFD_RELOC_X86_64_GOTPC32
:
12053 case BFD_RELOC_X86_64_GOT64
:
12054 case BFD_RELOC_X86_64_GOTPCREL64
:
12055 case BFD_RELOC_X86_64_GOTPC64
:
12056 case BFD_RELOC_X86_64_GOTPLT64
:
12057 case BFD_RELOC_X86_64_PLTOFF64
:
12058 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
12059 case BFD_RELOC_X86_64_TLSDESC_CALL
:
12060 case BFD_RELOC_RVA
:
12061 case BFD_RELOC_VTABLE_ENTRY
:
12062 case BFD_RELOC_VTABLE_INHERIT
:
12064 case BFD_RELOC_32_SECREL
:
12066 code
= fixp
->fx_r_type
;
12068 case BFD_RELOC_X86_64_32S
:
12069 if (!fixp
->fx_pcrel
)
12071 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
12072 code
= fixp
->fx_r_type
;
12075 /* Fall through. */
12077 if (fixp
->fx_pcrel
)
12079 switch (fixp
->fx_size
)
12082 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
12083 _("can not do %d byte pc-relative relocation"),
12085 code
= BFD_RELOC_32_PCREL
;
12087 case 1: code
= BFD_RELOC_8_PCREL
; break;
12088 case 2: code
= BFD_RELOC_16_PCREL
; break;
12089 case 4: code
= BFD_RELOC_32_PCREL
; break;
12091 case 8: code
= BFD_RELOC_64_PCREL
; break;
12097 switch (fixp
->fx_size
)
12100 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
12101 _("can not do %d byte relocation"),
12103 code
= BFD_RELOC_32
;
12105 case 1: code
= BFD_RELOC_8
; break;
12106 case 2: code
= BFD_RELOC_16
; break;
12107 case 4: code
= BFD_RELOC_32
; break;
12109 case 8: code
= BFD_RELOC_64
; break;
12116 if ((code
== BFD_RELOC_32
12117 || code
== BFD_RELOC_32_PCREL
12118 || code
== BFD_RELOC_X86_64_32S
)
12120 && fixp
->fx_addsy
== GOT_symbol
)
12123 code
= BFD_RELOC_386_GOTPC
;
12125 code
= BFD_RELOC_X86_64_GOTPC32
;
12127 if ((code
== BFD_RELOC_64
|| code
== BFD_RELOC_64_PCREL
)
12129 && fixp
->fx_addsy
== GOT_symbol
)
12131 code
= BFD_RELOC_X86_64_GOTPC64
;
12134 rel
= XNEW (arelent
);
12135 rel
->sym_ptr_ptr
= XNEW (asymbol
*);
12136 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
12138 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
12140 if (!use_rela_relocations
)
12142 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
12143 vtable entry to be used in the relocation's section offset. */
12144 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
12145 rel
->address
= fixp
->fx_offset
;
12146 #if defined (OBJ_COFF) && defined (TE_PE)
12147 else if (fixp
->fx_addsy
&& S_IS_WEAK (fixp
->fx_addsy
))
12148 rel
->addend
= fixp
->fx_addnumber
- (S_GET_VALUE (fixp
->fx_addsy
) * 2);
12153 /* Use the rela in 64bit mode. */
12156 if (disallow_64bit_reloc
)
12159 case BFD_RELOC_X86_64_DTPOFF64
:
12160 case BFD_RELOC_X86_64_TPOFF64
:
12161 case BFD_RELOC_64_PCREL
:
12162 case BFD_RELOC_X86_64_GOTOFF64
:
12163 case BFD_RELOC_X86_64_GOT64
:
12164 case BFD_RELOC_X86_64_GOTPCREL64
:
12165 case BFD_RELOC_X86_64_GOTPC64
:
12166 case BFD_RELOC_X86_64_GOTPLT64
:
12167 case BFD_RELOC_X86_64_PLTOFF64
:
12168 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
12169 _("cannot represent relocation type %s in x32 mode"),
12170 bfd_get_reloc_code_name (code
));
12176 if (!fixp
->fx_pcrel
)
12177 rel
->addend
= fixp
->fx_offset
;
12181 case BFD_RELOC_X86_64_PLT32
:
12182 case BFD_RELOC_X86_64_GOT32
:
12183 case BFD_RELOC_X86_64_GOTPCREL
:
12184 case BFD_RELOC_X86_64_GOTPCRELX
:
12185 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
12186 case BFD_RELOC_X86_64_TLSGD
:
12187 case BFD_RELOC_X86_64_TLSLD
:
12188 case BFD_RELOC_X86_64_GOTTPOFF
:
12189 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
12190 case BFD_RELOC_X86_64_TLSDESC_CALL
:
12191 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
12194 rel
->addend
= (section
->vma
12196 + fixp
->fx_addnumber
12197 + md_pcrel_from (fixp
));
12202 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
12203 if (rel
->howto
== NULL
)
12205 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
12206 _("cannot represent relocation type %s"),
12207 bfd_get_reloc_code_name (code
));
12208 /* Set howto to a garbage value so that we can keep going. */
12209 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
12210 gas_assert (rel
->howto
!= NULL
);
12216 #include "tc-i386-intel.c"
12219 tc_x86_parse_to_dw2regnum (expressionS
*exp
)
12221 int saved_naked_reg
;
12222 char saved_register_dot
;
12224 saved_naked_reg
= allow_naked_reg
;
12225 allow_naked_reg
= 1;
12226 saved_register_dot
= register_chars
['.'];
12227 register_chars
['.'] = '.';
12228 allow_pseudo_reg
= 1;
12229 expression_and_evaluate (exp
);
12230 allow_pseudo_reg
= 0;
12231 register_chars
['.'] = saved_register_dot
;
12232 allow_naked_reg
= saved_naked_reg
;
12234 if (exp
->X_op
== O_register
&& exp
->X_add_number
>= 0)
12236 if ((addressT
) exp
->X_add_number
< i386_regtab_size
)
12238 exp
->X_op
= O_constant
;
12239 exp
->X_add_number
= i386_regtab
[exp
->X_add_number
]
12240 .dw2_regnum
[flag_code
>> 1];
12243 exp
->X_op
= O_illegal
;
12248 tc_x86_frame_initial_instructions (void)
12250 static unsigned int sp_regno
[2];
12252 if (!sp_regno
[flag_code
>> 1])
12254 char *saved_input
= input_line_pointer
;
12255 char sp
[][4] = {"esp", "rsp"};
12258 input_line_pointer
= sp
[flag_code
>> 1];
12259 tc_x86_parse_to_dw2regnum (&exp
);
12260 gas_assert (exp
.X_op
== O_constant
);
12261 sp_regno
[flag_code
>> 1] = exp
.X_add_number
;
12262 input_line_pointer
= saved_input
;
12265 cfi_add_CFA_def_cfa (sp_regno
[flag_code
>> 1], -x86_cie_data_alignment
);
12266 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
12270 x86_dwarf2_addr_size (void)
12272 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
12273 if (x86_elf_abi
== X86_64_X32_ABI
)
12276 return bfd_arch_bits_per_address (stdoutput
) / 8;
12280 i386_elf_section_type (const char *str
, size_t len
)
12282 if (flag_code
== CODE_64BIT
12283 && len
== sizeof ("unwind") - 1
12284 && strncmp (str
, "unwind", 6) == 0)
12285 return SHT_X86_64_UNWIND
;
12292 i386_solaris_fix_up_eh_frame (segT sec
)
12294 if (flag_code
== CODE_64BIT
)
12295 elf_section_type (sec
) = SHT_X86_64_UNWIND
;
12301 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
12305 exp
.X_op
= O_secrel
;
12306 exp
.X_add_symbol
= symbol
;
12307 exp
.X_add_number
= 0;
12308 emit_expr (&exp
, size
);
12312 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12313 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
12316 x86_64_section_letter (int letter
, const char **ptr_msg
)
12318 if (flag_code
== CODE_64BIT
)
12321 return SHF_X86_64_LARGE
;
12323 *ptr_msg
= _("bad .section directive: want a,l,w,x,M,S,G,T in string");
12326 *ptr_msg
= _("bad .section directive: want a,w,x,M,S,G,T in string");
12331 x86_64_section_word (char *str
, size_t len
)
12333 if (len
== 5 && flag_code
== CODE_64BIT
&& CONST_STRNEQ (str
, "large"))
12334 return SHF_X86_64_LARGE
;
12340 handle_large_common (int small ATTRIBUTE_UNUSED
)
12342 if (flag_code
!= CODE_64BIT
)
12344 s_comm_internal (0, elf_common_parse
);
12345 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
12349 static segT lbss_section
;
12350 asection
*saved_com_section_ptr
= elf_com_section_ptr
;
12351 asection
*saved_bss_section
= bss_section
;
12353 if (lbss_section
== NULL
)
12355 flagword applicable
;
12356 segT seg
= now_seg
;
12357 subsegT subseg
= now_subseg
;
12359 /* The .lbss section is for local .largecomm symbols. */
12360 lbss_section
= subseg_new (".lbss", 0);
12361 applicable
= bfd_applicable_section_flags (stdoutput
);
12362 bfd_set_section_flags (lbss_section
, applicable
& SEC_ALLOC
);
12363 seg_info (lbss_section
)->bss
= 1;
12365 subseg_set (seg
, subseg
);
12368 elf_com_section_ptr
= &_bfd_elf_large_com_section
;
12369 bss_section
= lbss_section
;
12371 s_comm_internal (0, elf_common_parse
);
12373 elf_com_section_ptr
= saved_com_section_ptr
;
12374 bss_section
= saved_bss_section
;
12377 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */