1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
4 Free Software Foundation, Inc.
6 This file is part of GAS, the GNU Assembler.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
23 /* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
25 x86_64 support by Jan Hubicka (jh@suse.cz)
26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
27 Bugs & suggestions are completely welcome. This is free software.
28 Please help us make it better. */
31 #include "safe-ctype.h"
33 #include "dwarf2dbg.h"
34 #include "dw2gencfi.h"
35 #include "elf/x86-64.h"
36 #include "opcodes/i386-init.h"
38 #ifndef REGISTER_WARNINGS
39 #define REGISTER_WARNINGS 1
42 #ifndef INFER_ADDR_PREFIX
43 #define INFER_ADDR_PREFIX 1
47 #define DEFAULT_ARCH "i386"
52 #define INLINE __inline__
58 /* Prefixes will be emitted in the order defined below.
59 WAIT_PREFIX must be the first prefix since FWAIT is really is an
60 instruction, and so must come before any prefixes.
61 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
67 #define LOCKREP_PREFIX 4
68 #define REX_PREFIX 5 /* must come last. */
69 #define MAX_PREFIXES 6 /* max prefixes per opcode */
71 /* we define the syntax here (modulo base,index,scale syntax) */
72 #define REGISTER_PREFIX '%'
73 #define IMMEDIATE_PREFIX '$'
74 #define ABSOLUTE_PREFIX '*'
76 /* these are the instruction mnemonic suffixes in AT&T syntax or
77 memory operand size in Intel syntax. */
78 #define WORD_MNEM_SUFFIX 'w'
79 #define BYTE_MNEM_SUFFIX 'b'
80 #define SHORT_MNEM_SUFFIX 's'
81 #define LONG_MNEM_SUFFIX 'l'
82 #define QWORD_MNEM_SUFFIX 'q'
83 #define XMMWORD_MNEM_SUFFIX 'x'
84 #define YMMWORD_MNEM_SUFFIX 'y'
85 /* Intel Syntax. Use a non-ascii letter since since it never appears
87 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
89 #define END_OF_INSN '\0'
92 'templates' is for grouping together 'template' structures for opcodes
93 of the same name. This is only used for storing the insns in the grand
94 ole hash table of insns.
95 The templates themselves start at START and range up to (but not including)
100 const template *start
;
105 /* 386 operand encoding bytes: see 386 book for details of this. */
108 unsigned int regmem
; /* codes register or memory operand */
109 unsigned int reg
; /* codes register operand (or extended opcode) */
110 unsigned int mode
; /* how to interpret regmem & reg */
114 /* x86-64 extension prefix. */
115 typedef int rex_byte
;
117 /* The SSE5 instructions have a two bit instruction modifier (OC) that
118 is stored in two separate bytes in the instruction. Pick apart OC
119 into the 2 separate bits for instruction. */
120 #define DREX_OC0(x) (((x) & 1) != 0)
121 #define DREX_OC1(x) (((x) & 2) != 0)
123 #define DREX_OC0_MASK (1 << 3) /* set OC0 in byte 4 */
124 #define DREX_OC1_MASK (1 << 2) /* set OC1 in byte 3 */
127 #define DREX_XMEM_X1_X2_X2 0 /* 4 op insn, dest = src3, src1 = reg/mem */
128 #define DREX_X1_XMEM_X2_X2 1 /* 4 op insn, dest = src3, src2 = reg/mem */
129 #define DREX_X1_XMEM_X2_X1 2 /* 4 op insn, dest = src1, src2 = reg/mem */
130 #define DREX_X1_X2_XMEM_X1 3 /* 4 op insn, dest = src1, src3 = reg/mem */
132 #define DREX_XMEM_X1_X2 0 /* 3 op insn, src1 = reg/mem */
133 #define DREX_X1_XMEM_X2 1 /* 3 op insn, src1 = reg/mem */
135 /* Information needed to create the DREX byte in SSE5 instructions. */
138 unsigned int reg
; /* register */
139 unsigned int rex
; /* REX flags */
140 unsigned int modrm_reg
; /* which arg goes in the modrm.reg field */
141 unsigned int modrm_regmem
; /* which arg goes in the modrm.regmem field */
144 /* 386 opcode byte to code indirect addressing. */
153 /* x86 arch names, types and features */
156 const char *name
; /* arch name */
157 enum processor_type type
; /* arch type */
158 i386_cpu_flags flags
; /* cpu feature flags */
162 static void set_code_flag (int);
163 static void set_16bit_gcc_code_flag (int);
164 static void set_intel_syntax (int);
165 static void set_intel_mnemonic (int);
166 static void set_allow_index_reg (int);
167 static void set_sse_check (int);
168 static void set_cpu_arch (int);
170 static void pe_directive_secrel (int);
172 static void signed_cons (int);
173 static char *output_invalid (int c
);
174 static int i386_att_operand (char *);
175 static int i386_intel_operand (char *, int);
176 static const reg_entry
*parse_register (char *, char **);
177 static char *parse_insn (char *, char *);
178 static char *parse_operands (char *, const char *);
179 static void swap_operands (void);
180 static void swap_2_operands (int, int);
181 static void optimize_imm (void);
182 static void optimize_disp (void);
183 static const template *match_template (void);
184 static int check_string (void);
185 static int process_suffix (void);
186 static int check_byte_reg (void);
187 static int check_long_reg (void);
188 static int check_qword_reg (void);
189 static int check_word_reg (void);
190 static int finalize_imm (void);
191 static void process_drex (void);
192 static int process_operands (void);
193 static const seg_entry
*build_modrm_byte (void);
194 static void output_insn (void);
195 static void output_imm (fragS
*, offsetT
);
196 static void output_disp (fragS
*, offsetT
);
198 static void s_bss (int);
200 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
201 static void handle_large_common (int small ATTRIBUTE_UNUSED
);
204 static const char *default_arch
= DEFAULT_ARCH
;
209 /* VEX prefix is either 2 byte or 3 byte. */
210 unsigned char bytes
[3];
212 /* Destination or source register specifier. */
213 const reg_entry
*register_specifier
;
216 /* 'md_assemble ()' gathers together information and puts it into a
223 const reg_entry
*regs
;
228 /* TM holds the template for the insn were currently assembling. */
231 /* SUFFIX holds the instruction size suffix for byte, word, dword
232 or qword, if given. */
235 /* OPERANDS gives the number of given operands. */
236 unsigned int operands
;
238 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
239 of given register, displacement, memory operands and immediate
241 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
243 /* TYPES [i] is the type (see above #defines) which tells us how to
244 use OP[i] for the corresponding operand. */
245 i386_operand_type types
[MAX_OPERANDS
];
247 /* Displacement expression, immediate expression, or register for each
249 union i386_op op
[MAX_OPERANDS
];
251 /* Flags for operands. */
252 unsigned int flags
[MAX_OPERANDS
];
253 #define Operand_PCrel 1
255 /* Relocation type for operand */
256 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
258 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
259 the base index byte below. */
260 const reg_entry
*base_reg
;
261 const reg_entry
*index_reg
;
262 unsigned int log2_scale_factor
;
264 /* SEG gives the seg_entries of this insn. They are zero unless
265 explicit segment overrides are given. */
266 const seg_entry
*seg
[2];
268 /* PREFIX holds all the given prefix opcodes (usually null).
269 PREFIXES is the number of prefix opcodes. */
270 unsigned int prefixes
;
271 unsigned char prefix
[MAX_PREFIXES
];
273 /* RM and SIB are the modrm byte and the sib byte where the
274 addressing modes of this insn are encoded. DREX is the byte
275 added by the SSE5 instructions. */
283 /* Swap operand in encoding. */
284 unsigned int swap_operand
: 1;
287 typedef struct _i386_insn i386_insn
;
289 /* List of chars besides those in app.c:symbol_chars that can start an
290 operand. Used to prevent the scrubber eating vital white-space. */
291 const char extra_symbol_chars
[] = "*%-(["
300 #if (defined (TE_I386AIX) \
301 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
302 && !defined (TE_GNU) \
303 && !defined (TE_LINUX) \
304 && !defined (TE_NETWARE) \
305 && !defined (TE_FreeBSD) \
306 && !defined (TE_NetBSD)))
307 /* This array holds the chars that always start a comment. If the
308 pre-processor is disabled, these aren't very useful. The option
309 --divide will remove '/' from this list. */
310 const char *i386_comment_chars
= "#/";
311 #define SVR4_COMMENT_CHARS 1
312 #define PREFIX_SEPARATOR '\\'
315 const char *i386_comment_chars
= "#";
316 #define PREFIX_SEPARATOR '/'
319 /* This array holds the chars that only start a comment at the beginning of
320 a line. If the line seems to have the form '# 123 filename'
321 .line and .file directives will appear in the pre-processed output.
322 Note that input_file.c hand checks for '#' at the beginning of the
323 first line of the input file. This is because the compiler outputs
324 #NO_APP at the beginning of its output.
325 Also note that comments started like this one will always work if
326 '/' isn't otherwise defined. */
327 const char line_comment_chars
[] = "#/";
329 const char line_separator_chars
[] = ";";
331 /* Chars that can be used to separate mant from exp in floating point
333 const char EXP_CHARS
[] = "eE";
335 /* Chars that mean this number is a floating point constant
338 const char FLT_CHARS
[] = "fFdDxX";
340 /* Tables for lexical analysis. */
341 static char mnemonic_chars
[256];
342 static char register_chars
[256];
343 static char operand_chars
[256];
344 static char identifier_chars
[256];
345 static char digit_chars
[256];
347 /* Lexical macros. */
348 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
349 #define is_operand_char(x) (operand_chars[(unsigned char) x])
350 #define is_register_char(x) (register_chars[(unsigned char) x])
351 #define is_space_char(x) ((x) == ' ')
352 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
353 #define is_digit_char(x) (digit_chars[(unsigned char) x])
355 /* All non-digit non-letter characters that may occur in an operand. */
356 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
358 /* md_assemble() always leaves the strings it's passed unaltered. To
359 effect this we maintain a stack of saved characters that we've smashed
360 with '\0's (indicating end of strings for various sub-fields of the
361 assembler instruction). */
362 static char save_stack
[32];
363 static char *save_stack_p
;
364 #define END_STRING_AND_SAVE(s) \
365 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
366 #define RESTORE_END_STRING(s) \
367 do { *(s) = *--save_stack_p; } while (0)
369 /* The instruction we're assembling. */
372 /* Possible templates for current insn. */
373 static const templates
*current_templates
;
375 /* Per instruction expressionS buffers: max displacements & immediates. */
376 static expressionS disp_expressions
[MAX_MEMORY_OPERANDS
];
377 static expressionS im_expressions
[MAX_IMMEDIATE_OPERANDS
];
379 /* Current operand we are working on. */
380 static int this_operand
;
382 /* We support four different modes. FLAG_CODE variable is used to distinguish
390 static enum flag_code flag_code
;
391 static unsigned int object_64bit
;
392 static int use_rela_relocations
= 0;
394 /* The names used to print error messages. */
395 static const char *flag_code_names
[] =
402 /* 1 for intel syntax,
404 static int intel_syntax
= 0;
406 /* 1 for intel mnemonic,
407 0 if att mnemonic. */
408 static int intel_mnemonic
= !SYSV386_COMPAT
;
410 /* 1 if support old (<= 2.8.1) versions of gcc. */
411 static int old_gcc
= OLDGCC_COMPAT
;
413 /* 1 if pseudo registers are permitted. */
414 static int allow_pseudo_reg
= 0;
416 /* 1 if register prefix % not required. */
417 static int allow_naked_reg
= 0;
419 /* 1 if pseudo index register, eiz/riz, is allowed . */
420 static int allow_index_reg
= 0;
430 /* Register prefix used for error message. */
431 static const char *register_prefix
= "%";
433 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
434 leave, push, and pop instructions so that gcc has the same stack
435 frame as in 32 bit mode. */
436 static char stackop_size
= '\0';
438 /* Non-zero to optimize code alignment. */
439 int optimize_align_code
= 1;
441 /* Non-zero to quieten some warnings. */
442 static int quiet_warnings
= 0;
445 static const char *cpu_arch_name
= NULL
;
446 static char *cpu_sub_arch_name
= NULL
;
448 /* CPU feature flags. */
449 static i386_cpu_flags cpu_arch_flags
= CPU_UNKNOWN_FLAGS
;
451 /* If we have selected a cpu we are generating instructions for. */
452 static int cpu_arch_tune_set
= 0;
454 /* Cpu we are generating instructions for. */
455 enum processor_type cpu_arch_tune
= PROCESSOR_UNKNOWN
;
457 /* CPU feature flags of cpu we are generating instructions for. */
458 static i386_cpu_flags cpu_arch_tune_flags
;
460 /* CPU instruction set architecture used. */
461 enum processor_type cpu_arch_isa
= PROCESSOR_UNKNOWN
;
463 /* CPU feature flags of instruction set architecture used. */
464 i386_cpu_flags cpu_arch_isa_flags
;
466 /* If set, conditional jumps are not automatically promoted to handle
467 larger than a byte offset. */
468 static unsigned int no_cond_jump_promotion
= 0;
470 /* Encode SSE instructions with VEX prefix. */
471 static unsigned int sse2avx
;
473 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
474 static symbolS
*GOT_symbol
;
476 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
477 unsigned int x86_dwarf2_return_column
;
479 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
480 int x86_cie_data_alignment
;
482 /* Interface to relax_segment.
483 There are 3 major relax states for 386 jump insns because the
484 different types of jumps add different sizes to frags when we're
485 figuring out what sort of jump to choose to reach a given label. */
488 #define UNCOND_JUMP 0
490 #define COND_JUMP86 2
495 #define SMALL16 (SMALL | CODE16)
497 #define BIG16 (BIG | CODE16)
501 #define INLINE __inline__
507 #define ENCODE_RELAX_STATE(type, size) \
508 ((relax_substateT) (((type) << 2) | (size)))
509 #define TYPE_FROM_RELAX_STATE(s) \
511 #define DISP_SIZE_FROM_RELAX_STATE(s) \
512 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
514 /* This table is used by relax_frag to promote short jumps to long
515 ones where necessary. SMALL (short) jumps may be promoted to BIG
516 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
517 don't allow a short jump in a 32 bit code segment to be promoted to
518 a 16 bit offset jump because it's slower (requires data size
519 prefix), and doesn't work, unless the destination is in the bottom
520 64k of the code segment (The top 16 bits of eip are zeroed). */
522 const relax_typeS md_relax_table
[] =
525 1) most positive reach of this state,
526 2) most negative reach of this state,
527 3) how many bytes this mode will have in the variable part of the frag
528 4) which index into the table to try if we can't fit into this one. */
530 /* UNCOND_JUMP states. */
531 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
532 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
533 /* dword jmp adds 4 bytes to frag:
534 0 extra opcode bytes, 4 displacement bytes. */
536 /* word jmp adds 2 byte2 to frag:
537 0 extra opcode bytes, 2 displacement bytes. */
540 /* COND_JUMP states. */
541 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
542 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
543 /* dword conditionals adds 5 bytes to frag:
544 1 extra opcode byte, 4 displacement bytes. */
546 /* word conditionals add 3 bytes to frag:
547 1 extra opcode byte, 2 displacement bytes. */
550 /* COND_JUMP86 states. */
551 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
552 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
553 /* dword conditionals adds 5 bytes to frag:
554 1 extra opcode byte, 4 displacement bytes. */
556 /* word conditionals add 4 bytes to frag:
557 1 displacement byte and a 3 byte long branch insn. */
561 static const arch_entry cpu_arch
[] =
563 { "generic32", PROCESSOR_GENERIC32
,
564 CPU_GENERIC32_FLAGS
},
565 { "generic64", PROCESSOR_GENERIC64
,
566 CPU_GENERIC64_FLAGS
},
567 { "i8086", PROCESSOR_UNKNOWN
,
569 { "i186", PROCESSOR_UNKNOWN
,
571 { "i286", PROCESSOR_UNKNOWN
,
573 { "i386", PROCESSOR_I386
,
575 { "i486", PROCESSOR_I486
,
577 { "i586", PROCESSOR_PENTIUM
,
579 { "i686", PROCESSOR_PENTIUMPRO
,
581 { "pentium", PROCESSOR_PENTIUM
,
583 { "pentiumpro", PROCESSOR_PENTIUMPRO
,
585 { "pentiumii", PROCESSOR_PENTIUMPRO
,
587 { "pentiumiii",PROCESSOR_PENTIUMPRO
,
589 { "pentium4", PROCESSOR_PENTIUM4
,
591 { "prescott", PROCESSOR_NOCONA
,
593 { "nocona", PROCESSOR_NOCONA
,
595 { "yonah", PROCESSOR_CORE
,
597 { "core", PROCESSOR_CORE
,
599 { "merom", PROCESSOR_CORE2
,
601 { "core2", PROCESSOR_CORE2
,
603 { "k6", PROCESSOR_K6
,
605 { "k6_2", PROCESSOR_K6
,
607 { "athlon", PROCESSOR_ATHLON
,
609 { "sledgehammer", PROCESSOR_K8
,
611 { "opteron", PROCESSOR_K8
,
613 { "k8", PROCESSOR_K8
,
615 { "amdfam10", PROCESSOR_AMDFAM10
,
616 CPU_AMDFAM10_FLAGS
},
617 { ".mmx", PROCESSOR_UNKNOWN
,
619 { ".sse", PROCESSOR_UNKNOWN
,
621 { ".sse2", PROCESSOR_UNKNOWN
,
623 { ".sse3", PROCESSOR_UNKNOWN
,
625 { ".ssse3", PROCESSOR_UNKNOWN
,
627 { ".sse4.1", PROCESSOR_UNKNOWN
,
629 { ".sse4.2", PROCESSOR_UNKNOWN
,
631 { ".sse4", PROCESSOR_UNKNOWN
,
633 { ".avx", PROCESSOR_UNKNOWN
,
635 { ".vmx", PROCESSOR_UNKNOWN
,
637 { ".smx", PROCESSOR_UNKNOWN
,
639 { ".xsave", PROCESSOR_UNKNOWN
,
641 { ".aes", PROCESSOR_UNKNOWN
,
643 { ".pclmul", PROCESSOR_UNKNOWN
,
645 { ".clmul", PROCESSOR_UNKNOWN
,
647 { ".fma", PROCESSOR_UNKNOWN
,
649 { ".movbe", PROCESSOR_UNKNOWN
,
651 { ".ept", PROCESSOR_UNKNOWN
,
653 { ".3dnow", PROCESSOR_UNKNOWN
,
655 { ".3dnowa", PROCESSOR_UNKNOWN
,
657 { ".padlock", PROCESSOR_UNKNOWN
,
659 { ".pacifica", PROCESSOR_UNKNOWN
,
661 { ".svme", PROCESSOR_UNKNOWN
,
663 { ".sse4a", PROCESSOR_UNKNOWN
,
665 { ".abm", PROCESSOR_UNKNOWN
,
667 { ".sse5", PROCESSOR_UNKNOWN
,
672 /* Like s_lcomm_internal in gas/read.c but the alignment string
673 is allowed to be optional. */
676 pe_lcomm_internal (int needs_align
, symbolS
*symbolP
, addressT size
)
683 && *input_line_pointer
== ',')
685 align
= parse_align (needs_align
- 1);
687 if (align
== (addressT
) -1)
702 bss_alloc (symbolP
, size
, align
);
707 pe_lcomm (int needs_align
)
709 s_comm_internal (needs_align
* 2, pe_lcomm_internal
);
713 const pseudo_typeS md_pseudo_table
[] =
715 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
716 {"align", s_align_bytes
, 0},
718 {"align", s_align_ptwo
, 0},
720 {"arch", set_cpu_arch
, 0},
724 {"lcomm", pe_lcomm
, 1},
726 {"ffloat", float_cons
, 'f'},
727 {"dfloat", float_cons
, 'd'},
728 {"tfloat", float_cons
, 'x'},
730 {"slong", signed_cons
, 4},
731 {"noopt", s_ignore
, 0},
732 {"optim", s_ignore
, 0},
733 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
734 {"code16", set_code_flag
, CODE_16BIT
},
735 {"code32", set_code_flag
, CODE_32BIT
},
736 {"code64", set_code_flag
, CODE_64BIT
},
737 {"intel_syntax", set_intel_syntax
, 1},
738 {"att_syntax", set_intel_syntax
, 0},
739 {"intel_mnemonic", set_intel_mnemonic
, 1},
740 {"att_mnemonic", set_intel_mnemonic
, 0},
741 {"allow_index_reg", set_allow_index_reg
, 1},
742 {"disallow_index_reg", set_allow_index_reg
, 0},
743 {"sse_check", set_sse_check
, 0},
744 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
745 {"largecomm", handle_large_common
, 0},
747 {"file", (void (*) (int)) dwarf2_directive_file
, 0},
748 {"loc", dwarf2_directive_loc
, 0},
749 {"loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0},
752 {"secrel32", pe_directive_secrel
, 0},
757 /* For interface with expression (). */
758 extern char *input_line_pointer
;
760 /* Hash table for instruction mnemonic lookup. */
761 static struct hash_control
*op_hash
;
763 /* Hash table for register lookup. */
764 static struct hash_control
*reg_hash
;
767 i386_align_code (fragS
*fragP
, int count
)
769 /* Various efficient no-op patterns for aligning code labels.
770 Note: Don't try to assemble the instructions in the comments.
771 0L and 0w are not legal. */
772 static const char f32_1
[] =
774 static const char f32_2
[] =
775 {0x66,0x90}; /* xchg %ax,%ax */
776 static const char f32_3
[] =
777 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
778 static const char f32_4
[] =
779 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
780 static const char f32_5
[] =
782 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
783 static const char f32_6
[] =
784 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
785 static const char f32_7
[] =
786 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
787 static const char f32_8
[] =
789 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
790 static const char f32_9
[] =
791 {0x89,0xf6, /* movl %esi,%esi */
792 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
793 static const char f32_10
[] =
794 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
795 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
796 static const char f32_11
[] =
797 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
798 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
799 static const char f32_12
[] =
800 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
801 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
802 static const char f32_13
[] =
803 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
804 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
805 static const char f32_14
[] =
806 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
807 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
808 static const char f16_3
[] =
809 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
810 static const char f16_4
[] =
811 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
812 static const char f16_5
[] =
814 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
815 static const char f16_6
[] =
816 {0x89,0xf6, /* mov %si,%si */
817 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
818 static const char f16_7
[] =
819 {0x8d,0x74,0x00, /* lea 0(%si),%si */
820 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
821 static const char f16_8
[] =
822 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
823 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
824 static const char jump_31
[] =
825 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
826 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
827 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
828 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
829 static const char *const f32_patt
[] = {
830 f32_1
, f32_2
, f32_3
, f32_4
, f32_5
, f32_6
, f32_7
, f32_8
,
831 f32_9
, f32_10
, f32_11
, f32_12
, f32_13
, f32_14
833 static const char *const f16_patt
[] = {
834 f32_1
, f32_2
, f16_3
, f16_4
, f16_5
, f16_6
, f16_7
, f16_8
837 static const char alt_3
[] =
839 /* nopl 0(%[re]ax) */
840 static const char alt_4
[] =
841 {0x0f,0x1f,0x40,0x00};
842 /* nopl 0(%[re]ax,%[re]ax,1) */
843 static const char alt_5
[] =
844 {0x0f,0x1f,0x44,0x00,0x00};
845 /* nopw 0(%[re]ax,%[re]ax,1) */
846 static const char alt_6
[] =
847 {0x66,0x0f,0x1f,0x44,0x00,0x00};
848 /* nopl 0L(%[re]ax) */
849 static const char alt_7
[] =
850 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
851 /* nopl 0L(%[re]ax,%[re]ax,1) */
852 static const char alt_8
[] =
853 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
854 /* nopw 0L(%[re]ax,%[re]ax,1) */
855 static const char alt_9
[] =
856 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
857 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
858 static const char alt_10
[] =
859 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
861 nopw %cs:0L(%[re]ax,%[re]ax,1) */
862 static const char alt_long_11
[] =
864 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
867 nopw %cs:0L(%[re]ax,%[re]ax,1) */
868 static const char alt_long_12
[] =
871 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
875 nopw %cs:0L(%[re]ax,%[re]ax,1) */
876 static const char alt_long_13
[] =
880 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
885 nopw %cs:0L(%[re]ax,%[re]ax,1) */
886 static const char alt_long_14
[] =
891 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
897 nopw %cs:0L(%[re]ax,%[re]ax,1) */
898 static const char alt_long_15
[] =
904 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
905 /* nopl 0(%[re]ax,%[re]ax,1)
906 nopw 0(%[re]ax,%[re]ax,1) */
907 static const char alt_short_11
[] =
908 {0x0f,0x1f,0x44,0x00,0x00,
909 0x66,0x0f,0x1f,0x44,0x00,0x00};
910 /* nopw 0(%[re]ax,%[re]ax,1)
911 nopw 0(%[re]ax,%[re]ax,1) */
912 static const char alt_short_12
[] =
913 {0x66,0x0f,0x1f,0x44,0x00,0x00,
914 0x66,0x0f,0x1f,0x44,0x00,0x00};
915 /* nopw 0(%[re]ax,%[re]ax,1)
917 static const char alt_short_13
[] =
918 {0x66,0x0f,0x1f,0x44,0x00,0x00,
919 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
922 static const char alt_short_14
[] =
923 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
924 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
926 nopl 0L(%[re]ax,%[re]ax,1) */
927 static const char alt_short_15
[] =
928 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
929 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
930 static const char *const alt_short_patt
[] = {
931 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
932 alt_9
, alt_10
, alt_short_11
, alt_short_12
, alt_short_13
,
933 alt_short_14
, alt_short_15
935 static const char *const alt_long_patt
[] = {
936 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
937 alt_9
, alt_10
, alt_long_11
, alt_long_12
, alt_long_13
,
938 alt_long_14
, alt_long_15
941 /* Only align for at least a positive non-zero boundary. */
942 if (count
<= 0 || count
> MAX_MEM_FOR_RS_ALIGN_CODE
)
945 /* We need to decide which NOP sequence to use for 32bit and
946 64bit. When -mtune= is used:
948 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
949 PROCESSOR_GENERIC32, f32_patt will be used.
950 2. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
951 PROCESSOR_CORE, PROCESSOR_CORE2, and PROCESSOR_GENERIC64,
952 alt_long_patt will be used.
953 3. For PROCESSOR_ATHLON, PROCESSOR_K6, PROCESSOR_K8 and
954 PROCESSOR_AMDFAM10, alt_short_patt will be used.
956 When -mtune= isn't used, alt_long_patt will be used if
957 cpu_arch_isa_flags has Cpu686. Otherwise, f32_patt will
960 When -march= or .arch is used, we can't use anything beyond
961 cpu_arch_isa_flags. */
963 if (flag_code
== CODE_16BIT
)
967 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
969 /* Adjust jump offset. */
970 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
973 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
974 f16_patt
[count
- 1], count
);
978 const char *const *patt
= NULL
;
980 if (fragP
->tc_frag_data
.isa
== PROCESSOR_UNKNOWN
)
982 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
983 switch (cpu_arch_tune
)
985 case PROCESSOR_UNKNOWN
:
986 /* We use cpu_arch_isa_flags to check if we SHOULD
987 optimize for Cpu686. */
988 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpui686
)
989 patt
= alt_long_patt
;
993 case PROCESSOR_PENTIUMPRO
:
994 case PROCESSOR_PENTIUM4
:
995 case PROCESSOR_NOCONA
:
997 case PROCESSOR_CORE2
:
998 case PROCESSOR_GENERIC64
:
999 patt
= alt_long_patt
;
1002 case PROCESSOR_ATHLON
:
1004 case PROCESSOR_AMDFAM10
:
1005 patt
= alt_short_patt
;
1007 case PROCESSOR_I386
:
1008 case PROCESSOR_I486
:
1009 case PROCESSOR_PENTIUM
:
1010 case PROCESSOR_GENERIC32
:
1017 switch (fragP
->tc_frag_data
.tune
)
1019 case PROCESSOR_UNKNOWN
:
1020 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1021 PROCESSOR_UNKNOWN. */
1025 case PROCESSOR_I386
:
1026 case PROCESSOR_I486
:
1027 case PROCESSOR_PENTIUM
:
1029 case PROCESSOR_ATHLON
:
1031 case PROCESSOR_AMDFAM10
:
1032 case PROCESSOR_GENERIC32
:
1033 /* We use cpu_arch_isa_flags to check if we CAN optimize
1035 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpui686
)
1036 patt
= alt_short_patt
;
1040 case PROCESSOR_PENTIUMPRO
:
1041 case PROCESSOR_PENTIUM4
:
1042 case PROCESSOR_NOCONA
:
1043 case PROCESSOR_CORE
:
1044 case PROCESSOR_CORE2
:
1045 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpui686
)
1046 patt
= alt_long_patt
;
1050 case PROCESSOR_GENERIC64
:
1051 patt
= alt_long_patt
;
1056 if (patt
== f32_patt
)
1058 /* If the padding is less than 15 bytes, we use the normal
1059 ones. Otherwise, we use a jump instruction and adjust
1062 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1063 patt
[count
- 1], count
);
1066 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1068 /* Adjust jump offset. */
1069 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
1074 /* Maximum length of an instruction is 15 byte. If the
1075 padding is greater than 15 bytes and we don't use jump,
1076 we have to break it into smaller pieces. */
1077 int padding
= count
;
1078 while (padding
> 15)
1081 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
+ padding
,
1086 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1087 patt
[padding
- 1], padding
);
1090 fragP
->fr_var
= count
;
1094 operand_type_all_zero (const union i386_operand_type
*x
)
1096 switch (ARRAY_SIZE(x
->array
))
1105 return !x
->array
[0];
1112 operand_type_set (union i386_operand_type
*x
, unsigned int v
)
1114 switch (ARRAY_SIZE(x
->array
))
1129 operand_type_equal (const union i386_operand_type
*x
,
1130 const union i386_operand_type
*y
)
1132 switch (ARRAY_SIZE(x
->array
))
1135 if (x
->array
[2] != y
->array
[2])
1138 if (x
->array
[1] != y
->array
[1])
1141 return x
->array
[0] == y
->array
[0];
1149 cpu_flags_all_zero (const union i386_cpu_flags
*x
)
1151 switch (ARRAY_SIZE(x
->array
))
1160 return !x
->array
[0];
1167 cpu_flags_set (union i386_cpu_flags
*x
, unsigned int v
)
1169 switch (ARRAY_SIZE(x
->array
))
1184 cpu_flags_equal (const union i386_cpu_flags
*x
,
1185 const union i386_cpu_flags
*y
)
1187 switch (ARRAY_SIZE(x
->array
))
1190 if (x
->array
[2] != y
->array
[2])
1193 if (x
->array
[1] != y
->array
[1])
1196 return x
->array
[0] == y
->array
[0];
1204 cpu_flags_check_cpu64 (i386_cpu_flags f
)
1206 return !((flag_code
== CODE_64BIT
&& f
.bitfield
.cpuno64
)
1207 || (flag_code
!= CODE_64BIT
&& f
.bitfield
.cpu64
));
1210 static INLINE i386_cpu_flags
1211 cpu_flags_and (i386_cpu_flags x
, i386_cpu_flags y
)
1213 switch (ARRAY_SIZE (x
.array
))
1216 x
.array
[2] &= y
.array
[2];
1218 x
.array
[1] &= y
.array
[1];
1220 x
.array
[0] &= y
.array
[0];
1228 static INLINE i386_cpu_flags
1229 cpu_flags_or (i386_cpu_flags x
, i386_cpu_flags y
)
1231 switch (ARRAY_SIZE (x
.array
))
1234 x
.array
[2] |= y
.array
[2];
1236 x
.array
[1] |= y
.array
[1];
1238 x
.array
[0] |= y
.array
[0];
1246 #define CPU_FLAGS_ARCH_MATCH 0x1
1247 #define CPU_FLAGS_64BIT_MATCH 0x2
1248 #define CPU_FLAGS_AES_MATCH 0x4
1249 #define CPU_FLAGS_AVX_MATCH 0x8
1251 #define CPU_FLAGS_32BIT_MATCH \
1252 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH | CPU_FLAGS_AVX_MATCH)
1253 #define CPU_FLAGS_PERFECT_MATCH \
1254 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)
1256 /* Return CPU flags match bits. */
1259 cpu_flags_match (const template *t
)
1261 i386_cpu_flags x
= t
->cpu_flags
;
1262 int match
= cpu_flags_check_cpu64 (x
) ? CPU_FLAGS_64BIT_MATCH
: 0;
1264 x
.bitfield
.cpu64
= 0;
1265 x
.bitfield
.cpuno64
= 0;
1267 if (cpu_flags_all_zero (&x
))
1269 /* This instruction is available on all archs. */
1270 match
|= CPU_FLAGS_32BIT_MATCH
;
1274 /* This instruction is available only on some archs. */
1275 i386_cpu_flags cpu
= cpu_arch_flags
;
1277 cpu
.bitfield
.cpu64
= 0;
1278 cpu
.bitfield
.cpuno64
= 0;
1279 cpu
= cpu_flags_and (x
, cpu
);
1280 if (!cpu_flags_all_zero (&cpu
))
1282 if (x
.bitfield
.cpuavx
)
1284 /* We only need to check AES/SSE2AVX with AVX. */
1285 if (cpu
.bitfield
.cpuavx
)
1287 /* Check SSE2AVX. */
1288 if (!t
->opcode_modifier
.sse2avx
|| sse2avx
)
1290 match
|= (CPU_FLAGS_ARCH_MATCH
1291 | CPU_FLAGS_AVX_MATCH
);
1293 if (!x
.bitfield
.cpuaes
|| cpu
.bitfield
.cpuaes
)
1294 match
|= CPU_FLAGS_AES_MATCH
;
1298 match
|= CPU_FLAGS_ARCH_MATCH
;
1301 match
|= CPU_FLAGS_32BIT_MATCH
;
1307 static INLINE i386_operand_type
1308 operand_type_and (i386_operand_type x
, i386_operand_type y
)
1310 switch (ARRAY_SIZE (x
.array
))
1313 x
.array
[2] &= y
.array
[2];
1315 x
.array
[1] &= y
.array
[1];
1317 x
.array
[0] &= y
.array
[0];
1325 static INLINE i386_operand_type
1326 operand_type_or (i386_operand_type x
, i386_operand_type y
)
1328 switch (ARRAY_SIZE (x
.array
))
1331 x
.array
[2] |= y
.array
[2];
1333 x
.array
[1] |= y
.array
[1];
1335 x
.array
[0] |= y
.array
[0];
1343 static INLINE i386_operand_type
1344 operand_type_xor (i386_operand_type x
, i386_operand_type y
)
1346 switch (ARRAY_SIZE (x
.array
))
1349 x
.array
[2] ^= y
.array
[2];
1351 x
.array
[1] ^= y
.array
[1];
1353 x
.array
[0] ^= y
.array
[0];
1361 static const i386_operand_type acc32
= OPERAND_TYPE_ACC32
;
1362 static const i386_operand_type acc64
= OPERAND_TYPE_ACC64
;
1363 static const i386_operand_type control
= OPERAND_TYPE_CONTROL
;
1364 static const i386_operand_type inoutportreg
1365 = OPERAND_TYPE_INOUTPORTREG
;
1366 static const i386_operand_type reg16_inoutportreg
1367 = OPERAND_TYPE_REG16_INOUTPORTREG
;
1368 static const i386_operand_type disp16
= OPERAND_TYPE_DISP16
;
1369 static const i386_operand_type disp32
= OPERAND_TYPE_DISP32
;
1370 static const i386_operand_type disp32s
= OPERAND_TYPE_DISP32S
;
1371 static const i386_operand_type disp16_32
= OPERAND_TYPE_DISP16_32
;
1372 static const i386_operand_type anydisp
1373 = OPERAND_TYPE_ANYDISP
;
1374 static const i386_operand_type regxmm
= OPERAND_TYPE_REGXMM
;
1375 static const i386_operand_type regymm
= OPERAND_TYPE_REGYMM
;
1376 static const i386_operand_type imm8
= OPERAND_TYPE_IMM8
;
1377 static const i386_operand_type imm8s
= OPERAND_TYPE_IMM8S
;
1378 static const i386_operand_type imm16
= OPERAND_TYPE_IMM16
;
1379 static const i386_operand_type imm32
= OPERAND_TYPE_IMM32
;
1380 static const i386_operand_type imm32s
= OPERAND_TYPE_IMM32S
;
1381 static const i386_operand_type imm64
= OPERAND_TYPE_IMM64
;
1382 static const i386_operand_type imm16_32
= OPERAND_TYPE_IMM16_32
;
1383 static const i386_operand_type imm16_32s
= OPERAND_TYPE_IMM16_32S
;
1384 static const i386_operand_type imm16_32_32s
= OPERAND_TYPE_IMM16_32_32S
;
1385 static const i386_operand_type vex_imm4
= OPERAND_TYPE_VEX_IMM4
;
1396 operand_type_check (i386_operand_type t
, enum operand_type c
)
1401 return (t
.bitfield
.reg8
1404 || t
.bitfield
.reg64
);
1407 return (t
.bitfield
.imm8
1411 || t
.bitfield
.imm32s
1412 || t
.bitfield
.imm64
);
1415 return (t
.bitfield
.disp8
1416 || t
.bitfield
.disp16
1417 || t
.bitfield
.disp32
1418 || t
.bitfield
.disp32s
1419 || t
.bitfield
.disp64
);
1422 return (t
.bitfield
.disp8
1423 || t
.bitfield
.disp16
1424 || t
.bitfield
.disp32
1425 || t
.bitfield
.disp32s
1426 || t
.bitfield
.disp64
1427 || t
.bitfield
.baseindex
);
1436 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1437 operand J for instruction template T. */
1440 match_reg_size (const template *t
, unsigned int j
)
1442 return !((i
.types
[j
].bitfield
.byte
1443 && !t
->operand_types
[j
].bitfield
.byte
)
1444 || (i
.types
[j
].bitfield
.word
1445 && !t
->operand_types
[j
].bitfield
.word
)
1446 || (i
.types
[j
].bitfield
.dword
1447 && !t
->operand_types
[j
].bitfield
.dword
)
1448 || (i
.types
[j
].bitfield
.qword
1449 && !t
->operand_types
[j
].bitfield
.qword
));
1452 /* Return 1 if there is no conflict in any size on operand J for
1453 instruction template T. */
1456 match_mem_size (const template *t
, unsigned int j
)
1458 return (match_reg_size (t
, j
)
1459 && !((i
.types
[j
].bitfield
.unspecified
1460 && !t
->operand_types
[j
].bitfield
.unspecified
)
1461 || (i
.types
[j
].bitfield
.fword
1462 && !t
->operand_types
[j
].bitfield
.fword
)
1463 || (i
.types
[j
].bitfield
.tbyte
1464 && !t
->operand_types
[j
].bitfield
.tbyte
)
1465 || (i
.types
[j
].bitfield
.xmmword
1466 && !t
->operand_types
[j
].bitfield
.xmmword
)
1467 || (i
.types
[j
].bitfield
.ymmword
1468 && !t
->operand_types
[j
].bitfield
.ymmword
)));
1471 /* Return 1 if there is no size conflict on any operands for
1472 instruction template T. */
1475 operand_size_match (const template *t
)
1480 /* Don't check jump instructions. */
1481 if (t
->opcode_modifier
.jump
1482 || t
->opcode_modifier
.jumpbyte
1483 || t
->opcode_modifier
.jumpdword
1484 || t
->opcode_modifier
.jumpintersegment
)
1487 /* Check memory and accumulator operand size. */
1488 for (j
= 0; j
< i
.operands
; j
++)
1490 if (t
->operand_types
[j
].bitfield
.anysize
)
1493 if (t
->operand_types
[j
].bitfield
.acc
&& !match_reg_size (t
, j
))
1499 if (i
.types
[j
].bitfield
.mem
&& !match_mem_size (t
, j
))
1507 || (!t
->opcode_modifier
.d
&& !t
->opcode_modifier
.floatd
))
1510 /* Check reverse. */
1511 assert (i
.operands
== 2);
1514 for (j
= 0; j
< 2; j
++)
1516 if (t
->operand_types
[j
].bitfield
.acc
1517 && !match_reg_size (t
, j
? 0 : 1))
1523 if (i
.types
[j
].bitfield
.mem
1524 && !match_mem_size (t
, j
? 0 : 1))
1535 operand_type_match (i386_operand_type overlap
,
1536 i386_operand_type given
)
1538 i386_operand_type temp
= overlap
;
1540 temp
.bitfield
.jumpabsolute
= 0;
1541 temp
.bitfield
.unspecified
= 0;
1542 temp
.bitfield
.byte
= 0;
1543 temp
.bitfield
.word
= 0;
1544 temp
.bitfield
.dword
= 0;
1545 temp
.bitfield
.fword
= 0;
1546 temp
.bitfield
.qword
= 0;
1547 temp
.bitfield
.tbyte
= 0;
1548 temp
.bitfield
.xmmword
= 0;
1549 temp
.bitfield
.ymmword
= 0;
1550 if (operand_type_all_zero (&temp
))
1553 return (given
.bitfield
.baseindex
== overlap
.bitfield
.baseindex
1554 && given
.bitfield
.jumpabsolute
== overlap
.bitfield
.jumpabsolute
);
1557 /* If given types g0 and g1 are registers they must be of the same type
1558 unless the expected operand type register overlap is null.
1559 Note that Acc in a template matches every size of reg. */
1562 operand_type_register_match (i386_operand_type m0
,
1563 i386_operand_type g0
,
1564 i386_operand_type t0
,
1565 i386_operand_type m1
,
1566 i386_operand_type g1
,
1567 i386_operand_type t1
)
1569 if (!operand_type_check (g0
, reg
))
1572 if (!operand_type_check (g1
, reg
))
1575 if (g0
.bitfield
.reg8
== g1
.bitfield
.reg8
1576 && g0
.bitfield
.reg16
== g1
.bitfield
.reg16
1577 && g0
.bitfield
.reg32
== g1
.bitfield
.reg32
1578 && g0
.bitfield
.reg64
== g1
.bitfield
.reg64
)
1581 if (m0
.bitfield
.acc
)
1583 t0
.bitfield
.reg8
= 1;
1584 t0
.bitfield
.reg16
= 1;
1585 t0
.bitfield
.reg32
= 1;
1586 t0
.bitfield
.reg64
= 1;
1589 if (m1
.bitfield
.acc
)
1591 t1
.bitfield
.reg8
= 1;
1592 t1
.bitfield
.reg16
= 1;
1593 t1
.bitfield
.reg32
= 1;
1594 t1
.bitfield
.reg64
= 1;
1597 return (!(t0
.bitfield
.reg8
& t1
.bitfield
.reg8
)
1598 && !(t0
.bitfield
.reg16
& t1
.bitfield
.reg16
)
1599 && !(t0
.bitfield
.reg32
& t1
.bitfield
.reg32
)
1600 && !(t0
.bitfield
.reg64
& t1
.bitfield
.reg64
));
1603 static INLINE
unsigned int
1604 mode_from_disp_size (i386_operand_type t
)
1606 if (t
.bitfield
.disp8
)
1608 else if (t
.bitfield
.disp16
1609 || t
.bitfield
.disp32
1610 || t
.bitfield
.disp32s
)
1617 fits_in_signed_byte (offsetT num
)
1619 return (num
>= -128) && (num
<= 127);
1623 fits_in_unsigned_byte (offsetT num
)
1625 return (num
& 0xff) == num
;
1629 fits_in_unsigned_word (offsetT num
)
1631 return (num
& 0xffff) == num
;
1635 fits_in_signed_word (offsetT num
)
1637 return (-32768 <= num
) && (num
<= 32767);
1641 fits_in_signed_long (offsetT num ATTRIBUTE_UNUSED
)
1646 return (!(((offsetT
) -1 << 31) & num
)
1647 || (((offsetT
) -1 << 31) & num
) == ((offsetT
) -1 << 31));
1649 } /* fits_in_signed_long() */
1652 fits_in_unsigned_long (offsetT num ATTRIBUTE_UNUSED
)
1657 return (num
& (((offsetT
) 2 << 31) - 1)) == num
;
1659 } /* fits_in_unsigned_long() */
1662 fits_in_imm4 (offsetT num
)
1664 return (num
& 0xf) == num
;
1667 static i386_operand_type
1668 smallest_imm_type (offsetT num
)
1670 i386_operand_type t
;
1672 operand_type_set (&t
, 0);
1673 t
.bitfield
.imm64
= 1;
1675 if (cpu_arch_tune
!= PROCESSOR_I486
&& num
== 1)
1677 /* This code is disabled on the 486 because all the Imm1 forms
1678 in the opcode table are slower on the i486. They're the
1679 versions with the implicitly specified single-position
1680 displacement, which has another syntax if you really want to
1682 t
.bitfield
.imm1
= 1;
1683 t
.bitfield
.imm8
= 1;
1684 t
.bitfield
.imm8s
= 1;
1685 t
.bitfield
.imm16
= 1;
1686 t
.bitfield
.imm32
= 1;
1687 t
.bitfield
.imm32s
= 1;
1689 else if (fits_in_signed_byte (num
))
1691 t
.bitfield
.imm8
= 1;
1692 t
.bitfield
.imm8s
= 1;
1693 t
.bitfield
.imm16
= 1;
1694 t
.bitfield
.imm32
= 1;
1695 t
.bitfield
.imm32s
= 1;
1697 else if (fits_in_unsigned_byte (num
))
1699 t
.bitfield
.imm8
= 1;
1700 t
.bitfield
.imm16
= 1;
1701 t
.bitfield
.imm32
= 1;
1702 t
.bitfield
.imm32s
= 1;
1704 else if (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
1706 t
.bitfield
.imm16
= 1;
1707 t
.bitfield
.imm32
= 1;
1708 t
.bitfield
.imm32s
= 1;
1710 else if (fits_in_signed_long (num
))
1712 t
.bitfield
.imm32
= 1;
1713 t
.bitfield
.imm32s
= 1;
1715 else if (fits_in_unsigned_long (num
))
1716 t
.bitfield
.imm32
= 1;
1722 offset_in_range (offsetT val
, int size
)
1728 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
1729 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
1730 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
1732 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
1737 /* If BFD64, sign extend val. */
1738 if (!use_rela_relocations
)
1739 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
1740 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
1742 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
1744 char buf1
[40], buf2
[40];
1746 sprint_value (buf1
, val
);
1747 sprint_value (buf2
, val
& mask
);
1748 as_warn (_("%s shortened to %s"), buf1
, buf2
);
1753 /* Returns 0 if attempting to add a prefix where one from the same
1754 class already exists, 1 if non rep/repne added, 2 if rep/repne
1757 add_prefix (unsigned int prefix
)
1762 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
1763 && flag_code
== CODE_64BIT
)
1765 if ((i
.prefix
[REX_PREFIX
] & prefix
& REX_W
)
1766 || ((i
.prefix
[REX_PREFIX
] & (REX_R
| REX_X
| REX_B
))
1767 && (prefix
& (REX_R
| REX_X
| REX_B
))))
1778 case CS_PREFIX_OPCODE
:
1779 case DS_PREFIX_OPCODE
:
1780 case ES_PREFIX_OPCODE
:
1781 case FS_PREFIX_OPCODE
:
1782 case GS_PREFIX_OPCODE
:
1783 case SS_PREFIX_OPCODE
:
1787 case REPNE_PREFIX_OPCODE
:
1788 case REPE_PREFIX_OPCODE
:
1791 case LOCK_PREFIX_OPCODE
:
1799 case ADDR_PREFIX_OPCODE
:
1803 case DATA_PREFIX_OPCODE
:
1807 if (i
.prefix
[q
] != 0)
1815 i
.prefix
[q
] |= prefix
;
1818 as_bad (_("same type of prefix used twice"));
1824 set_code_flag (int value
)
1827 if (flag_code
== CODE_64BIT
)
1829 cpu_arch_flags
.bitfield
.cpu64
= 1;
1830 cpu_arch_flags
.bitfield
.cpuno64
= 0;
1834 cpu_arch_flags
.bitfield
.cpu64
= 0;
1835 cpu_arch_flags
.bitfield
.cpuno64
= 1;
1837 if (value
== CODE_64BIT
&& !cpu_arch_flags
.bitfield
.cpulm
)
1839 as_bad (_("64bit mode not supported on this CPU."));
1841 if (value
== CODE_32BIT
&& !cpu_arch_flags
.bitfield
.cpui386
)
1843 as_bad (_("32bit mode not supported on this CPU."));
1845 stackop_size
= '\0';
1849 set_16bit_gcc_code_flag (int new_code_flag
)
1851 flag_code
= new_code_flag
;
1852 if (flag_code
!= CODE_16BIT
)
1854 cpu_arch_flags
.bitfield
.cpu64
= 0;
1855 cpu_arch_flags
.bitfield
.cpuno64
= 1;
1856 stackop_size
= LONG_MNEM_SUFFIX
;
1860 set_intel_syntax (int syntax_flag
)
1862 /* Find out if register prefixing is specified. */
1863 int ask_naked_reg
= 0;
1866 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
1868 char *string
= input_line_pointer
;
1869 int e
= get_symbol_end ();
1871 if (strcmp (string
, "prefix") == 0)
1873 else if (strcmp (string
, "noprefix") == 0)
1876 as_bad (_("bad argument to syntax directive."));
1877 *input_line_pointer
= e
;
1879 demand_empty_rest_of_line ();
1881 intel_syntax
= syntax_flag
;
1883 if (ask_naked_reg
== 0)
1884 allow_naked_reg
= (intel_syntax
1885 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
1887 allow_naked_reg
= (ask_naked_reg
< 0);
1889 identifier_chars
['%'] = intel_syntax
&& allow_naked_reg
? '%' : 0;
1890 identifier_chars
['$'] = intel_syntax
? '$' : 0;
1891 register_prefix
= allow_naked_reg
? "" : "%";
1895 set_intel_mnemonic (int mnemonic_flag
)
1897 intel_mnemonic
= mnemonic_flag
;
1901 set_allow_index_reg (int flag
)
1903 allow_index_reg
= flag
;
1907 set_sse_check (int dummy ATTRIBUTE_UNUSED
)
1911 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
1913 char *string
= input_line_pointer
;
1914 int e
= get_symbol_end ();
1916 if (strcmp (string
, "none") == 0)
1917 sse_check
= sse_check_none
;
1918 else if (strcmp (string
, "warning") == 0)
1919 sse_check
= sse_check_warning
;
1920 else if (strcmp (string
, "error") == 0)
1921 sse_check
= sse_check_error
;
1923 as_bad (_("bad argument to sse_check directive."));
1924 *input_line_pointer
= e
;
1927 as_bad (_("missing argument for sse_check directive"));
1929 demand_empty_rest_of_line ();
1933 set_cpu_arch (int dummy ATTRIBUTE_UNUSED
)
1937 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
1939 char *string
= input_line_pointer
;
1940 int e
= get_symbol_end ();
1942 i386_cpu_flags flags
;
1944 for (i
= 0; i
< ARRAY_SIZE (cpu_arch
); i
++)
1946 if (strcmp (string
, cpu_arch
[i
].name
) == 0)
1950 cpu_arch_name
= cpu_arch
[i
].name
;
1951 cpu_sub_arch_name
= NULL
;
1952 cpu_arch_flags
= cpu_arch
[i
].flags
;
1953 if (flag_code
== CODE_64BIT
)
1955 cpu_arch_flags
.bitfield
.cpu64
= 1;
1956 cpu_arch_flags
.bitfield
.cpuno64
= 0;
1960 cpu_arch_flags
.bitfield
.cpu64
= 0;
1961 cpu_arch_flags
.bitfield
.cpuno64
= 1;
1963 cpu_arch_isa
= cpu_arch
[i
].type
;
1964 cpu_arch_isa_flags
= cpu_arch
[i
].flags
;
1965 if (!cpu_arch_tune_set
)
1967 cpu_arch_tune
= cpu_arch_isa
;
1968 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
1973 flags
= cpu_flags_or (cpu_arch_flags
,
1975 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
1977 if (cpu_sub_arch_name
)
1979 char *name
= cpu_sub_arch_name
;
1980 cpu_sub_arch_name
= concat (name
,
1982 (const char *) NULL
);
1986 cpu_sub_arch_name
= xstrdup (cpu_arch
[i
].name
);
1987 cpu_arch_flags
= flags
;
1989 *input_line_pointer
= e
;
1990 demand_empty_rest_of_line ();
1994 if (i
>= ARRAY_SIZE (cpu_arch
))
1995 as_bad (_("no such architecture: `%s'"), string
);
1997 *input_line_pointer
= e
;
2000 as_bad (_("missing cpu architecture"));
2002 no_cond_jump_promotion
= 0;
2003 if (*input_line_pointer
== ','
2004 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
2006 char *string
= ++input_line_pointer
;
2007 int e
= get_symbol_end ();
2009 if (strcmp (string
, "nojumps") == 0)
2010 no_cond_jump_promotion
= 1;
2011 else if (strcmp (string
, "jumps") == 0)
2014 as_bad (_("no such architecture modifier: `%s'"), string
);
2016 *input_line_pointer
= e
;
2019 demand_empty_rest_of_line ();
2025 if (!strcmp (default_arch
, "x86_64"))
2026 return bfd_mach_x86_64
;
2027 else if (!strcmp (default_arch
, "i386"))
2028 return bfd_mach_i386_i386
;
2030 as_fatal (_("Unknown architecture"));
2036 const char *hash_err
;
2038 /* Initialize op_hash hash table. */
2039 op_hash
= hash_new ();
2042 const template *optab
;
2043 templates
*core_optab
;
2045 /* Setup for loop. */
2047 core_optab
= (templates
*) xmalloc (sizeof (templates
));
2048 core_optab
->start
= optab
;
2053 if (optab
->name
== NULL
2054 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
2056 /* different name --> ship out current template list;
2057 add to hash table; & begin anew. */
2058 core_optab
->end
= optab
;
2059 hash_err
= hash_insert (op_hash
,
2061 (void *) core_optab
);
2064 as_fatal (_("Internal Error: Can't hash %s: %s"),
2068 if (optab
->name
== NULL
)
2070 core_optab
= (templates
*) xmalloc (sizeof (templates
));
2071 core_optab
->start
= optab
;
2076 /* Initialize reg_hash hash table. */
2077 reg_hash
= hash_new ();
2079 const reg_entry
*regtab
;
2080 unsigned int regtab_size
= i386_regtab_size
;
2082 for (regtab
= i386_regtab
; regtab_size
--; regtab
++)
2084 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (void *) regtab
);
2086 as_fatal (_("Internal Error: Can't hash %s: %s"),
2092 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
2097 for (c
= 0; c
< 256; c
++)
2102 mnemonic_chars
[c
] = c
;
2103 register_chars
[c
] = c
;
2104 operand_chars
[c
] = c
;
2106 else if (ISLOWER (c
))
2108 mnemonic_chars
[c
] = c
;
2109 register_chars
[c
] = c
;
2110 operand_chars
[c
] = c
;
2112 else if (ISUPPER (c
))
2114 mnemonic_chars
[c
] = TOLOWER (c
);
2115 register_chars
[c
] = mnemonic_chars
[c
];
2116 operand_chars
[c
] = c
;
2119 if (ISALPHA (c
) || ISDIGIT (c
))
2120 identifier_chars
[c
] = c
;
2123 identifier_chars
[c
] = c
;
2124 operand_chars
[c
] = c
;
2129 identifier_chars
['@'] = '@';
2132 identifier_chars
['?'] = '?';
2133 operand_chars
['?'] = '?';
2135 digit_chars
['-'] = '-';
2136 mnemonic_chars
['_'] = '_';
2137 mnemonic_chars
['-'] = '-';
2138 mnemonic_chars
['.'] = '.';
2139 identifier_chars
['_'] = '_';
2140 identifier_chars
['.'] = '.';
2142 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
2143 operand_chars
[(unsigned char) *p
] = *p
;
2146 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2149 record_alignment (text_section
, 2);
2150 record_alignment (data_section
, 2);
2151 record_alignment (bss_section
, 2);
2155 if (flag_code
== CODE_64BIT
)
2157 x86_dwarf2_return_column
= 16;
2158 x86_cie_data_alignment
= -8;
2162 x86_dwarf2_return_column
= 8;
2163 x86_cie_data_alignment
= -4;
2168 i386_print_statistics (FILE *file
)
2170 hash_print_statistics (file
, "i386 opcode", op_hash
);
2171 hash_print_statistics (file
, "i386 register", reg_hash
);
2176 /* Debugging routines for md_assemble. */
2177 static void pte (template *);
2178 static void pt (i386_operand_type
);
2179 static void pe (expressionS
*);
2180 static void ps (symbolS
*);
2183 pi (char *line
, i386_insn
*x
)
2187 fprintf (stdout
, "%s: template ", line
);
2189 fprintf (stdout
, " address: base %s index %s scale %x\n",
2190 x
->base_reg
? x
->base_reg
->reg_name
: "none",
2191 x
->index_reg
? x
->index_reg
->reg_name
: "none",
2192 x
->log2_scale_factor
);
2193 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
2194 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
2195 fprintf (stdout
, " sib: base %x index %x scale %x\n",
2196 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
2197 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
2198 (x
->rex
& REX_W
) != 0,
2199 (x
->rex
& REX_R
) != 0,
2200 (x
->rex
& REX_X
) != 0,
2201 (x
->rex
& REX_B
) != 0);
2202 fprintf (stdout
, " drex: reg %d rex 0x%x\n",
2203 x
->drex
.reg
, x
->drex
.rex
);
2204 for (i
= 0; i
< x
->operands
; i
++)
2206 fprintf (stdout
, " #%d: ", i
+ 1);
2208 fprintf (stdout
, "\n");
2209 if (x
->types
[i
].bitfield
.reg8
2210 || x
->types
[i
].bitfield
.reg16
2211 || x
->types
[i
].bitfield
.reg32
2212 || x
->types
[i
].bitfield
.reg64
2213 || x
->types
[i
].bitfield
.regmmx
2214 || x
->types
[i
].bitfield
.regxmm
2215 || x
->types
[i
].bitfield
.regymm
2216 || x
->types
[i
].bitfield
.sreg2
2217 || x
->types
[i
].bitfield
.sreg3
2218 || x
->types
[i
].bitfield
.control
2219 || x
->types
[i
].bitfield
.debug
2220 || x
->types
[i
].bitfield
.test
)
2221 fprintf (stdout
, "%s\n", x
->op
[i
].regs
->reg_name
);
2222 if (operand_type_check (x
->types
[i
], imm
))
2224 if (operand_type_check (x
->types
[i
], disp
))
2225 pe (x
->op
[i
].disps
);
2233 fprintf (stdout
, " %d operands ", t
->operands
);
2234 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
2235 if (t
->extension_opcode
!= None
)
2236 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
2237 if (t
->opcode_modifier
.d
)
2238 fprintf (stdout
, "D");
2239 if (t
->opcode_modifier
.w
)
2240 fprintf (stdout
, "W");
2241 fprintf (stdout
, "\n");
2242 for (i
= 0; i
< t
->operands
; i
++)
2244 fprintf (stdout
, " #%d type ", i
+ 1);
2245 pt (t
->operand_types
[i
]);
2246 fprintf (stdout
, "\n");
2253 fprintf (stdout
, " operation %d\n", e
->X_op
);
2254 fprintf (stdout
, " add_number %ld (%lx)\n",
2255 (long) e
->X_add_number
, (long) e
->X_add_number
);
2256 if (e
->X_add_symbol
)
2258 fprintf (stdout
, " add_symbol ");
2259 ps (e
->X_add_symbol
);
2260 fprintf (stdout
, "\n");
2264 fprintf (stdout
, " op_symbol ");
2265 ps (e
->X_op_symbol
);
2266 fprintf (stdout
, "\n");
2273 fprintf (stdout
, "%s type %s%s",
2275 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
2276 segment_name (S_GET_SEGMENT (s
)));
2279 static struct type_name
2281 i386_operand_type mask
;
2284 const type_names
[] =
2286 { OPERAND_TYPE_REG8
, "r8" },
2287 { OPERAND_TYPE_REG16
, "r16" },
2288 { OPERAND_TYPE_REG32
, "r32" },
2289 { OPERAND_TYPE_REG64
, "r64" },
2290 { OPERAND_TYPE_IMM8
, "i8" },
2291 { OPERAND_TYPE_IMM8
, "i8s" },
2292 { OPERAND_TYPE_IMM16
, "i16" },
2293 { OPERAND_TYPE_IMM32
, "i32" },
2294 { OPERAND_TYPE_IMM32S
, "i32s" },
2295 { OPERAND_TYPE_IMM64
, "i64" },
2296 { OPERAND_TYPE_IMM1
, "i1" },
2297 { OPERAND_TYPE_BASEINDEX
, "BaseIndex" },
2298 { OPERAND_TYPE_DISP8
, "d8" },
2299 { OPERAND_TYPE_DISP16
, "d16" },
2300 { OPERAND_TYPE_DISP32
, "d32" },
2301 { OPERAND_TYPE_DISP32S
, "d32s" },
2302 { OPERAND_TYPE_DISP64
, "d64" },
2303 { OPERAND_TYPE_INOUTPORTREG
, "InOutPortReg" },
2304 { OPERAND_TYPE_SHIFTCOUNT
, "ShiftCount" },
2305 { OPERAND_TYPE_CONTROL
, "control reg" },
2306 { OPERAND_TYPE_TEST
, "test reg" },
2307 { OPERAND_TYPE_DEBUG
, "debug reg" },
2308 { OPERAND_TYPE_FLOATREG
, "FReg" },
2309 { OPERAND_TYPE_FLOATACC
, "FAcc" },
2310 { OPERAND_TYPE_SREG2
, "SReg2" },
2311 { OPERAND_TYPE_SREG3
, "SReg3" },
2312 { OPERAND_TYPE_ACC
, "Acc" },
2313 { OPERAND_TYPE_JUMPABSOLUTE
, "Jump Absolute" },
2314 { OPERAND_TYPE_REGMMX
, "rMMX" },
2315 { OPERAND_TYPE_REGXMM
, "rXMM" },
2316 { OPERAND_TYPE_ESSEG
, "es" },
2317 { OPERAND_TYPE_VEX_IMM4
, "VEX i4" },
2321 pt (i386_operand_type t
)
2324 i386_operand_type a
;
2326 for (j
= 0; j
< ARRAY_SIZE (type_names
); j
++)
2328 a
= operand_type_and (t
, type_names
[j
].mask
);
2329 if (!UINTS_ALL_ZERO (a
))
2330 fprintf (stdout
, "%s, ", type_names
[j
].name
);
2335 #endif /* DEBUG386 */
2337 static bfd_reloc_code_real_type
2338 reloc (unsigned int size
,
2341 bfd_reloc_code_real_type other
)
2343 if (other
!= NO_RELOC
)
2345 reloc_howto_type
*reloc
;
2350 case BFD_RELOC_X86_64_GOT32
:
2351 return BFD_RELOC_X86_64_GOT64
;
2353 case BFD_RELOC_X86_64_PLTOFF64
:
2354 return BFD_RELOC_X86_64_PLTOFF64
;
2356 case BFD_RELOC_X86_64_GOTPC32
:
2357 other
= BFD_RELOC_X86_64_GOTPC64
;
2359 case BFD_RELOC_X86_64_GOTPCREL
:
2360 other
= BFD_RELOC_X86_64_GOTPCREL64
;
2362 case BFD_RELOC_X86_64_TPOFF32
:
2363 other
= BFD_RELOC_X86_64_TPOFF64
;
2365 case BFD_RELOC_X86_64_DTPOFF32
:
2366 other
= BFD_RELOC_X86_64_DTPOFF64
;
2372 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
2373 if (size
== 4 && flag_code
!= CODE_64BIT
)
2376 reloc
= bfd_reloc_type_lookup (stdoutput
, other
);
2378 as_bad (_("unknown relocation (%u)"), other
);
2379 else if (size
!= bfd_get_reloc_size (reloc
))
2380 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
2381 bfd_get_reloc_size (reloc
),
2383 else if (pcrel
&& !reloc
->pc_relative
)
2384 as_bad (_("non-pc-relative relocation for pc-relative field"));
2385 else if ((reloc
->complain_on_overflow
== complain_overflow_signed
2387 || (reloc
->complain_on_overflow
== complain_overflow_unsigned
2389 as_bad (_("relocated field and relocation type differ in signedness"));
2398 as_bad (_("there are no unsigned pc-relative relocations"));
2401 case 1: return BFD_RELOC_8_PCREL
;
2402 case 2: return BFD_RELOC_16_PCREL
;
2403 case 4: return BFD_RELOC_32_PCREL
;
2404 case 8: return BFD_RELOC_64_PCREL
;
2406 as_bad (_("cannot do %u byte pc-relative relocation"), size
);
2413 case 4: return BFD_RELOC_X86_64_32S
;
2418 case 1: return BFD_RELOC_8
;
2419 case 2: return BFD_RELOC_16
;
2420 case 4: return BFD_RELOC_32
;
2421 case 8: return BFD_RELOC_64
;
2423 as_bad (_("cannot do %s %u byte relocation"),
2424 sign
> 0 ? "signed" : "unsigned", size
);
2428 return BFD_RELOC_NONE
;
2431 /* Here we decide which fixups can be adjusted to make them relative to
2432 the beginning of the section instead of the symbol. Basically we need
2433 to make sure that the dynamic relocations are done correctly, so in
2434 some cases we force the original symbol to be used. */
2437 tc_i386_fix_adjustable (fixS
*fixP ATTRIBUTE_UNUSED
)
2439 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2443 /* Don't adjust pc-relative references to merge sections in 64-bit
2445 if (use_rela_relocations
2446 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
2450 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
2451 and changed later by validate_fix. */
2452 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
2453 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
2456 /* adjust_reloc_syms doesn't know about the GOT. */
2457 if (fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
2458 || fixP
->fx_r_type
== BFD_RELOC_386_PLT32
2459 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
2460 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
2461 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
2462 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
2463 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
2464 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
2465 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
2466 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
2467 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
2468 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTDESC
2469 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_DESC_CALL
2470 || fixP
->fx_r_type
== BFD_RELOC_X86_64_PLT32
2471 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
2472 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
2473 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
2474 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
2475 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
2476 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
2477 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
2478 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
2479 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
2480 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
2481 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPC32_TLSDESC
2482 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSDESC_CALL
2483 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
2484 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
2491 intel_float_operand (const char *mnemonic
)
2493 /* Note that the value returned is meaningful only for opcodes with (memory)
2494 operands, hence the code here is free to improperly handle opcodes that
2495 have no operands (for better performance and smaller code). */
2497 if (mnemonic
[0] != 'f')
2498 return 0; /* non-math */
2500 switch (mnemonic
[1])
2502 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
2503 the fs segment override prefix not currently handled because no
2504 call path can make opcodes without operands get here */
2506 return 2 /* integer op */;
2508 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
2509 return 3; /* fldcw/fldenv */
2512 if (mnemonic
[2] != 'o' /* fnop */)
2513 return 3; /* non-waiting control op */
2516 if (mnemonic
[2] == 's')
2517 return 3; /* frstor/frstpm */
2520 if (mnemonic
[2] == 'a')
2521 return 3; /* fsave */
2522 if (mnemonic
[2] == 't')
2524 switch (mnemonic
[3])
2526 case 'c': /* fstcw */
2527 case 'd': /* fstdw */
2528 case 'e': /* fstenv */
2529 case 's': /* fsts[gw] */
2535 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
2536 return 0; /* fxsave/fxrstor are not really math ops */
2543 /* Build the VEX prefix. */
2546 build_vex_prefix (const template *t
)
2548 unsigned int register_specifier
;
2549 unsigned int implied_prefix
;
2550 unsigned int vector_length
;
2552 /* Check register specifier. */
2553 if (i
.vex
.register_specifier
)
2555 register_specifier
= i
.vex
.register_specifier
->reg_num
;
2556 if ((i
.vex
.register_specifier
->reg_flags
& RegRex
))
2557 register_specifier
+= 8;
2558 register_specifier
= ~register_specifier
& 0xf;
2561 register_specifier
= 0xf;
2563 /* Use 2-byte VEX prefix by swappping destination and source
2566 && i
.operands
== i
.reg_operands
2567 && i
.tm
.opcode_modifier
.vex0f
2568 && i
.tm
.opcode_modifier
.s
2571 unsigned int xchg
= i
.operands
- 1;
2572 union i386_op temp_op
;
2573 i386_operand_type temp_type
;
2575 temp_type
= i
.types
[xchg
];
2576 i
.types
[xchg
] = i
.types
[0];
2577 i
.types
[0] = temp_type
;
2578 temp_op
= i
.op
[xchg
];
2579 i
.op
[xchg
] = i
.op
[0];
2582 assert (i
.rm
.mode
== 3);
2586 i
.rm
.regmem
= i
.rm
.reg
;
2589 /* Use the next insn. */
2593 vector_length
= i
.tm
.opcode_modifier
.vex256
? 1 : 0;
2595 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
2600 case DATA_PREFIX_OPCODE
:
2603 case REPE_PREFIX_OPCODE
:
2606 case REPNE_PREFIX_OPCODE
:
2613 /* Use 2-byte VEX prefix if possible. */
2614 if (i
.tm
.opcode_modifier
.vex0f
2615 && (i
.rex
& (REX_W
| REX_X
| REX_B
)) == 0)
2617 /* 2-byte VEX prefix. */
2621 i
.vex
.bytes
[0] = 0xc5;
2623 /* Check the REX.R bit. */
2624 r
= (i
.rex
& REX_R
) ? 0 : 1;
2625 i
.vex
.bytes
[1] = (r
<< 7
2626 | register_specifier
<< 3
2627 | vector_length
<< 2
2632 /* 3-byte VEX prefix. */
2635 if (i
.tm
.opcode_modifier
.vex0f
)
2637 else if (i
.tm
.opcode_modifier
.vex0f38
)
2639 else if (i
.tm
.opcode_modifier
.vex0f3a
)
2645 i
.vex
.bytes
[0] = 0xc4;
2647 /* The high 3 bits of the second VEX byte are 1's compliment
2648 of RXB bits from REX. */
2649 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
2651 /* Check the REX.W bit. */
2652 w
= (i
.rex
& REX_W
) ? 1 : 0;
2653 if (i
.tm
.opcode_modifier
.vexw0
|| i
.tm
.opcode_modifier
.vexw1
)
2658 if (i
.tm
.opcode_modifier
.vexw1
)
2662 i
.vex
.bytes
[2] = (w
<< 7
2663 | register_specifier
<< 3
2664 | vector_length
<< 2
2670 process_immext (void)
2674 if (i
.tm
.cpu_flags
.bitfield
.cpusse3
&& i
.operands
> 0)
2676 /* SSE3 Instructions have the fixed operands with an opcode
2677 suffix which is coded in the same place as an 8-bit immediate
2678 field would be. Here we check those operands and remove them
2682 for (x
= 0; x
< i
.operands
; x
++)
2683 if (i
.op
[x
].regs
->reg_num
!= x
)
2684 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
2685 register_prefix
, i
.op
[x
].regs
->reg_name
, x
+ 1,
2691 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
2692 which is coded in the same place as an 8-bit immediate field
2693 would be. Here we fake an 8-bit immediate operand from the
2694 opcode suffix stored in tm.extension_opcode.
2696 SSE5 and AVX instructions also use this encoding, for some of
2697 3 argument instructions. */
2699 assert (i
.imm_operands
== 0
2701 || (i
.tm
.cpu_flags
.bitfield
.cpusse5
2703 || (i
.tm
.opcode_modifier
.vex
2704 && i
.operands
<= 4)));
2706 exp
= &im_expressions
[i
.imm_operands
++];
2707 i
.op
[i
.operands
].imms
= exp
;
2708 i
.types
[i
.operands
] = imm8
;
2710 exp
->X_op
= O_constant
;
2711 exp
->X_add_number
= i
.tm
.extension_opcode
;
2712 i
.tm
.extension_opcode
= None
;
2715 /* This is the guts of the machine-dependent assembler. LINE points to a
2716 machine dependent instruction. This function is supposed to emit
2717 the frags/bytes it assembles to. */
2720 md_assemble (char *line
)
2723 char mnemonic
[MAX_MNEM_SIZE
];
2726 /* Initialize globals. */
2727 memset (&i
, '\0', sizeof (i
));
2728 for (j
= 0; j
< MAX_OPERANDS
; j
++)
2729 i
.reloc
[j
] = NO_RELOC
;
2730 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
2731 memset (im_expressions
, '\0', sizeof (im_expressions
));
2732 save_stack_p
= save_stack
;
2734 /* First parse an instruction mnemonic & call i386_operand for the operands.
2735 We assume that the scrubber has arranged it so that line[0] is the valid
2736 start of a (possibly prefixed) mnemonic. */
2738 line
= parse_insn (line
, mnemonic
);
2742 line
= parse_operands (line
, mnemonic
);
2746 /* Now we've parsed the mnemonic into a set of templates, and have the
2747 operands at hand. */
2749 /* All intel opcodes have reversed operands except for "bound" and
2750 "enter". We also don't reverse intersegment "jmp" and "call"
2751 instructions with 2 immediate operands so that the immediate segment
2752 precedes the offset, as it does when in AT&T mode. */
2755 && (strcmp (mnemonic
, "bound") != 0)
2756 && (strcmp (mnemonic
, "invlpga") != 0)
2757 && !(operand_type_check (i
.types
[0], imm
)
2758 && operand_type_check (i
.types
[1], imm
)))
2761 /* The order of the immediates should be reversed
2762 for 2 immediates extrq and insertq instructions */
2763 if (i
.imm_operands
== 2
2764 && (strcmp (mnemonic
, "extrq") == 0
2765 || strcmp (mnemonic
, "insertq") == 0))
2766 swap_2_operands (0, 1);
2771 /* Don't optimize displacement for movabs since it only takes 64bit
2774 && (flag_code
!= CODE_64BIT
2775 || strcmp (mnemonic
, "movabs") != 0))
2778 /* Next, we find a template that matches the given insn,
2779 making sure the overlap of the given operands types is consistent
2780 with the template operand types. */
2782 if (!(t
= match_template ()))
2785 if (sse_check
!= sse_check_none
2786 && !i
.tm
.opcode_modifier
.noavx
2787 && (i
.tm
.cpu_flags
.bitfield
.cpusse
2788 || i
.tm
.cpu_flags
.bitfield
.cpusse2
2789 || i
.tm
.cpu_flags
.bitfield
.cpusse3
2790 || i
.tm
.cpu_flags
.bitfield
.cpussse3
2791 || i
.tm
.cpu_flags
.bitfield
.cpusse4_1
2792 || i
.tm
.cpu_flags
.bitfield
.cpusse4_2
))
2794 (sse_check
== sse_check_warning
2796 : as_bad
) (_("SSE instruction `%s' is used"), i
.tm
.name
);
2799 /* Zap movzx and movsx suffix. The suffix has been set from
2800 "word ptr" or "byte ptr" on the source operand in Intel syntax
2801 or extracted from mnemonic in AT&T syntax. But we'll use
2802 the destination register to choose the suffix for encoding. */
2803 if ((i
.tm
.base_opcode
& ~9) == 0x0fb6)
2805 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
2806 there is no suffix, the default will be byte extension. */
2807 if (i
.reg_operands
!= 2
2810 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
2815 if (i
.tm
.opcode_modifier
.fwait
)
2816 if (!add_prefix (FWAIT_OPCODE
))
2819 /* Check string instruction segment overrides. */
2820 if (i
.tm
.opcode_modifier
.isstring
&& i
.mem_operands
!= 0)
2822 if (!check_string ())
2824 i
.disp_operands
= 0;
2827 if (!process_suffix ())
2830 /* Make still unresolved immediate matches conform to size of immediate
2831 given in i.suffix. */
2832 if (!finalize_imm ())
2835 if (i
.types
[0].bitfield
.imm1
)
2836 i
.imm_operands
= 0; /* kludge for shift insns. */
2838 for (j
= 0; j
< 3; j
++)
2839 if (i
.types
[j
].bitfield
.inoutportreg
2840 || i
.types
[j
].bitfield
.shiftcount
2841 || i
.types
[j
].bitfield
.acc
2842 || i
.types
[j
].bitfield
.floatacc
)
2845 /* ImmExt should be processed after SSE2AVX. */
2846 if (!i
.tm
.opcode_modifier
.sse2avx
2847 && i
.tm
.opcode_modifier
.immext
)
2850 /* For insns with operands there are more diddles to do to the opcode. */
2853 if (!process_operands ())
2856 else if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
2858 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
2859 as_warn (_("translating to `%sp'"), i
.tm
.name
);
2862 if (i
.tm
.opcode_modifier
.vex
)
2863 build_vex_prefix (t
);
2865 /* Handle conversion of 'int $3' --> special int3 insn. */
2866 if (i
.tm
.base_opcode
== INT_OPCODE
&& i
.op
[0].imms
->X_add_number
== 3)
2868 i
.tm
.base_opcode
= INT3_OPCODE
;
2872 if ((i
.tm
.opcode_modifier
.jump
2873 || i
.tm
.opcode_modifier
.jumpbyte
2874 || i
.tm
.opcode_modifier
.jumpdword
)
2875 && i
.op
[0].disps
->X_op
== O_constant
)
2877 /* Convert "jmp constant" (and "call constant") to a jump (call) to
2878 the absolute address given by the constant. Since ix86 jumps and
2879 calls are pc relative, we need to generate a reloc. */
2880 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
2881 i
.op
[0].disps
->X_op
= O_symbol
;
2884 if (i
.tm
.opcode_modifier
.rex64
)
2887 /* For 8 bit registers we need an empty rex prefix. Also if the
2888 instruction already has a prefix, we need to convert old
2889 registers to new ones. */
2891 if ((i
.types
[0].bitfield
.reg8
2892 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
2893 || (i
.types
[1].bitfield
.reg8
2894 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
2895 || ((i
.types
[0].bitfield
.reg8
2896 || i
.types
[1].bitfield
.reg8
)
2901 i
.rex
|= REX_OPCODE
;
2902 for (x
= 0; x
< 2; x
++)
2904 /* Look for 8 bit operand that uses old registers. */
2905 if (i
.types
[x
].bitfield
.reg8
2906 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
2908 /* In case it is "hi" register, give up. */
2909 if (i
.op
[x
].regs
->reg_num
> 3)
2910 as_bad (_("can't encode register '%s%s' in an "
2911 "instruction requiring REX prefix."),
2912 register_prefix
, i
.op
[x
].regs
->reg_name
);
2914 /* Otherwise it is equivalent to the extended register.
2915 Since the encoding doesn't change this is merely
2916 cosmetic cleanup for debug output. */
2918 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
2923 /* If the instruction has the DREX attribute (aka SSE5), don't emit a
2925 if (i
.tm
.opcode_modifier
.drex
|| i
.tm
.opcode_modifier
.drexc
)
2930 else if (i
.rex
!= 0)
2931 add_prefix (REX_OPCODE
| i
.rex
);
2933 /* We are ready to output the insn. */
2938 parse_insn (char *line
, char *mnemonic
)
2941 char *token_start
= l
;
2947 /* Non-zero if we found a prefix only acceptable with string insns. */
2948 const char *expecting_string_instruction
= NULL
;
2953 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
2958 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
2960 as_bad (_("no such instruction: `%s'"), token_start
);
2965 if (!is_space_char (*l
)
2966 && *l
!= END_OF_INSN
2968 || (*l
!= PREFIX_SEPARATOR
2971 as_bad (_("invalid character %s in mnemonic"),
2972 output_invalid (*l
));
2975 if (token_start
== l
)
2977 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
2978 as_bad (_("expecting prefix; got nothing"));
2980 as_bad (_("expecting mnemonic; got nothing"));
2984 /* Look up instruction (or prefix) via hash table. */
2985 current_templates
= hash_find (op_hash
, mnemonic
);
2987 if (*l
!= END_OF_INSN
2988 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
2989 && current_templates
2990 && current_templates
->start
->opcode_modifier
.isprefix
)
2992 if (!cpu_flags_check_cpu64 (current_templates
->start
->cpu_flags
))
2994 as_bad ((flag_code
!= CODE_64BIT
2995 ? _("`%s' is only supported in 64-bit mode")
2996 : _("`%s' is not supported in 64-bit mode")),
2997 current_templates
->start
->name
);
3000 /* If we are in 16-bit mode, do not allow addr16 or data16.
3001 Similarly, in 32-bit mode, do not allow addr32 or data32. */
3002 if ((current_templates
->start
->opcode_modifier
.size16
3003 || current_templates
->start
->opcode_modifier
.size32
)
3004 && flag_code
!= CODE_64BIT
3005 && (current_templates
->start
->opcode_modifier
.size32
3006 ^ (flag_code
== CODE_16BIT
)))
3008 as_bad (_("redundant %s prefix"),
3009 current_templates
->start
->name
);
3012 /* Add prefix, checking for repeated prefixes. */
3013 switch (add_prefix (current_templates
->start
->base_opcode
))
3018 expecting_string_instruction
= current_templates
->start
->name
;
3021 /* Skip past PREFIX_SEPARATOR and reset token_start. */
3028 if (!current_templates
)
3030 /* Check if we should swap operand in encoding. */
3031 if (mnem_p
- 2 == dot_p
&& dot_p
[1] == 's')
3037 current_templates
= hash_find (op_hash
, mnemonic
);
3040 if (!current_templates
)
3043 /* See if we can get a match by trimming off a suffix. */
3046 case WORD_MNEM_SUFFIX
:
3047 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
3048 i
.suffix
= SHORT_MNEM_SUFFIX
;
3050 case BYTE_MNEM_SUFFIX
:
3051 case QWORD_MNEM_SUFFIX
:
3052 i
.suffix
= mnem_p
[-1];
3054 current_templates
= hash_find (op_hash
, mnemonic
);
3056 case SHORT_MNEM_SUFFIX
:
3057 case LONG_MNEM_SUFFIX
:
3060 i
.suffix
= mnem_p
[-1];
3062 current_templates
= hash_find (op_hash
, mnemonic
);
3070 if (intel_float_operand (mnemonic
) == 1)
3071 i
.suffix
= SHORT_MNEM_SUFFIX
;
3073 i
.suffix
= LONG_MNEM_SUFFIX
;
3075 current_templates
= hash_find (op_hash
, mnemonic
);
3079 if (!current_templates
)
3081 as_bad (_("no such instruction: `%s'"), token_start
);
3086 if (current_templates
->start
->opcode_modifier
.jump
3087 || current_templates
->start
->opcode_modifier
.jumpbyte
)
3089 /* Check for a branch hint. We allow ",pt" and ",pn" for
3090 predict taken and predict not taken respectively.
3091 I'm not sure that branch hints actually do anything on loop
3092 and jcxz insns (JumpByte) for current Pentium4 chips. They
3093 may work in the future and it doesn't hurt to accept them
3095 if (l
[0] == ',' && l
[1] == 'p')
3099 if (!add_prefix (DS_PREFIX_OPCODE
))
3103 else if (l
[2] == 'n')
3105 if (!add_prefix (CS_PREFIX_OPCODE
))
3111 /* Any other comma loses. */
3114 as_bad (_("invalid character %s in mnemonic"),
3115 output_invalid (*l
));
3119 /* Check if instruction is supported on specified architecture. */
3121 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
3123 supported
|= cpu_flags_match (t
);
3124 if (supported
== CPU_FLAGS_PERFECT_MATCH
)
3128 if (!(supported
& CPU_FLAGS_64BIT_MATCH
))
3130 as_bad (flag_code
== CODE_64BIT
3131 ? _("`%s' is not supported in 64-bit mode")
3132 : _("`%s' is only supported in 64-bit mode"),
3133 current_templates
->start
->name
);
3136 if (supported
!= CPU_FLAGS_PERFECT_MATCH
)
3138 as_bad (_("`%s' is not supported on `%s%s'"),
3139 current_templates
->start
->name
, cpu_arch_name
,
3140 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
3145 if (!cpu_arch_flags
.bitfield
.cpui386
3146 && (flag_code
!= CODE_16BIT
))
3148 as_warn (_("use .code16 to ensure correct addressing mode"));
3151 /* Check for rep/repne without a string instruction. */
3152 if (expecting_string_instruction
)
3154 static templates override
;
3156 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
3157 if (t
->opcode_modifier
.isstring
)
3159 if (t
>= current_templates
->end
)
3161 as_bad (_("expecting string instruction after `%s'"),
3162 expecting_string_instruction
);
3165 for (override
.start
= t
; t
< current_templates
->end
; ++t
)
3166 if (!t
->opcode_modifier
.isstring
)
3169 current_templates
= &override
;
3176 parse_operands (char *l
, const char *mnemonic
)
3180 /* 1 if operand is pending after ','. */
3181 unsigned int expecting_operand
= 0;
3183 /* Non-zero if operand parens not balanced. */
3184 unsigned int paren_not_balanced
;
3186 while (*l
!= END_OF_INSN
)
3188 /* Skip optional white space before operand. */
3189 if (is_space_char (*l
))
3191 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
)
3193 as_bad (_("invalid character %s before operand %d"),
3194 output_invalid (*l
),
3198 token_start
= l
; /* after white space */
3199 paren_not_balanced
= 0;
3200 while (paren_not_balanced
|| *l
!= ',')
3202 if (*l
== END_OF_INSN
)
3204 if (paren_not_balanced
)
3207 as_bad (_("unbalanced parenthesis in operand %d."),
3210 as_bad (_("unbalanced brackets in operand %d."),
3215 break; /* we are done */
3217 else if (!is_operand_char (*l
) && !is_space_char (*l
))
3219 as_bad (_("invalid character %s in operand %d"),
3220 output_invalid (*l
),
3227 ++paren_not_balanced
;
3229 --paren_not_balanced
;
3234 ++paren_not_balanced
;
3236 --paren_not_balanced
;
3240 if (l
!= token_start
)
3241 { /* Yes, we've read in another operand. */
3242 unsigned int operand_ok
;
3243 this_operand
= i
.operands
++;
3244 i
.types
[this_operand
].bitfield
.unspecified
= 1;
3245 if (i
.operands
> MAX_OPERANDS
)
3247 as_bad (_("spurious operands; (%d operands/instruction max)"),
3251 /* Now parse operand adding info to 'i' as we go along. */
3252 END_STRING_AND_SAVE (l
);
3256 i386_intel_operand (token_start
,
3257 intel_float_operand (mnemonic
));
3259 operand_ok
= i386_att_operand (token_start
);
3261 RESTORE_END_STRING (l
);
3267 if (expecting_operand
)
3269 expecting_operand_after_comma
:
3270 as_bad (_("expecting operand after ','; got nothing"));
3275 as_bad (_("expecting operand before ','; got nothing"));
3280 /* Now *l must be either ',' or END_OF_INSN. */
3283 if (*++l
== END_OF_INSN
)
3285 /* Just skip it, if it's \n complain. */
3286 goto expecting_operand_after_comma
;
3288 expecting_operand
= 1;
3295 swap_2_operands (int xchg1
, int xchg2
)
3297 union i386_op temp_op
;
3298 i386_operand_type temp_type
;
3299 enum bfd_reloc_code_real temp_reloc
;
3301 temp_type
= i
.types
[xchg2
];
3302 i
.types
[xchg2
] = i
.types
[xchg1
];
3303 i
.types
[xchg1
] = temp_type
;
3304 temp_op
= i
.op
[xchg2
];
3305 i
.op
[xchg2
] = i
.op
[xchg1
];
3306 i
.op
[xchg1
] = temp_op
;
3307 temp_reloc
= i
.reloc
[xchg2
];
3308 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
3309 i
.reloc
[xchg1
] = temp_reloc
;
3313 swap_operands (void)
3319 swap_2_operands (1, i
.operands
- 2);
3322 swap_2_operands (0, i
.operands
- 1);
3328 if (i
.mem_operands
== 2)
3330 const seg_entry
*temp_seg
;
3331 temp_seg
= i
.seg
[0];
3332 i
.seg
[0] = i
.seg
[1];
3333 i
.seg
[1] = temp_seg
;
3337 /* Try to ensure constant immediates are represented in the smallest
3342 char guess_suffix
= 0;
3346 guess_suffix
= i
.suffix
;
3347 else if (i
.reg_operands
)
3349 /* Figure out a suffix from the last register operand specified.
3350 We can't do this properly yet, ie. excluding InOutPortReg,
3351 but the following works for instructions with immediates.
3352 In any case, we can't set i.suffix yet. */
3353 for (op
= i
.operands
; --op
>= 0;)
3354 if (i
.types
[op
].bitfield
.reg8
)
3356 guess_suffix
= BYTE_MNEM_SUFFIX
;
3359 else if (i
.types
[op
].bitfield
.reg16
)
3361 guess_suffix
= WORD_MNEM_SUFFIX
;
3364 else if (i
.types
[op
].bitfield
.reg32
)
3366 guess_suffix
= LONG_MNEM_SUFFIX
;
3369 else if (i
.types
[op
].bitfield
.reg64
)
3371 guess_suffix
= QWORD_MNEM_SUFFIX
;
3375 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
3376 guess_suffix
= WORD_MNEM_SUFFIX
;
3378 for (op
= i
.operands
; --op
>= 0;)
3379 if (operand_type_check (i
.types
[op
], imm
))
3381 switch (i
.op
[op
].imms
->X_op
)
3384 /* If a suffix is given, this operand may be shortened. */
3385 switch (guess_suffix
)
3387 case LONG_MNEM_SUFFIX
:
3388 i
.types
[op
].bitfield
.imm32
= 1;
3389 i
.types
[op
].bitfield
.imm64
= 1;
3391 case WORD_MNEM_SUFFIX
:
3392 i
.types
[op
].bitfield
.imm16
= 1;
3393 i
.types
[op
].bitfield
.imm32
= 1;
3394 i
.types
[op
].bitfield
.imm32s
= 1;
3395 i
.types
[op
].bitfield
.imm64
= 1;
3397 case BYTE_MNEM_SUFFIX
:
3398 i
.types
[op
].bitfield
.imm8
= 1;
3399 i
.types
[op
].bitfield
.imm8s
= 1;
3400 i
.types
[op
].bitfield
.imm16
= 1;
3401 i
.types
[op
].bitfield
.imm32
= 1;
3402 i
.types
[op
].bitfield
.imm32s
= 1;
3403 i
.types
[op
].bitfield
.imm64
= 1;
3407 /* If this operand is at most 16 bits, convert it
3408 to a signed 16 bit number before trying to see
3409 whether it will fit in an even smaller size.
3410 This allows a 16-bit operand such as $0xffe0 to
3411 be recognised as within Imm8S range. */
3412 if ((i
.types
[op
].bitfield
.imm16
)
3413 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
3415 i
.op
[op
].imms
->X_add_number
=
3416 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
3418 if ((i
.types
[op
].bitfield
.imm32
)
3419 && ((i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1))
3422 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
3423 ^ ((offsetT
) 1 << 31))
3424 - ((offsetT
) 1 << 31));
3427 = operand_type_or (i
.types
[op
],
3428 smallest_imm_type (i
.op
[op
].imms
->X_add_number
));
3430 /* We must avoid matching of Imm32 templates when 64bit
3431 only immediate is available. */
3432 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
3433 i
.types
[op
].bitfield
.imm32
= 0;
3440 /* Symbols and expressions. */
3442 /* Convert symbolic operand to proper sizes for matching, but don't
3443 prevent matching a set of insns that only supports sizes other
3444 than those matching the insn suffix. */
3446 i386_operand_type mask
, allowed
;
3449 operand_type_set (&mask
, 0);
3450 operand_type_set (&allowed
, 0);
3452 for (t
= current_templates
->start
;
3453 t
< current_templates
->end
;
3455 allowed
= operand_type_or (allowed
,
3456 t
->operand_types
[op
]);
3457 switch (guess_suffix
)
3459 case QWORD_MNEM_SUFFIX
:
3460 mask
.bitfield
.imm64
= 1;
3461 mask
.bitfield
.imm32s
= 1;
3463 case LONG_MNEM_SUFFIX
:
3464 mask
.bitfield
.imm32
= 1;
3466 case WORD_MNEM_SUFFIX
:
3467 mask
.bitfield
.imm16
= 1;
3469 case BYTE_MNEM_SUFFIX
:
3470 mask
.bitfield
.imm8
= 1;
3475 allowed
= operand_type_and (mask
, allowed
);
3476 if (!operand_type_all_zero (&allowed
))
3477 i
.types
[op
] = operand_type_and (i
.types
[op
], mask
);
3484 /* Try to use the smallest displacement type too. */
3486 optimize_disp (void)
3490 for (op
= i
.operands
; --op
>= 0;)
3491 if (operand_type_check (i
.types
[op
], disp
))
3493 if (i
.op
[op
].disps
->X_op
== O_constant
)
3495 offsetT disp
= i
.op
[op
].disps
->X_add_number
;
3497 if (i
.types
[op
].bitfield
.disp16
3498 && (disp
& ~(offsetT
) 0xffff) == 0)
3500 /* If this operand is at most 16 bits, convert
3501 to a signed 16 bit number and don't use 64bit
3503 disp
= (((disp
& 0xffff) ^ 0x8000) - 0x8000);
3504 i
.types
[op
].bitfield
.disp64
= 0;
3506 if (i
.types
[op
].bitfield
.disp32
3507 && (disp
& ~(((offsetT
) 2 << 31) - 1)) == 0)
3509 /* If this operand is at most 32 bits, convert
3510 to a signed 32 bit number and don't use 64bit
3512 disp
&= (((offsetT
) 2 << 31) - 1);
3513 disp
= (disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
3514 i
.types
[op
].bitfield
.disp64
= 0;
3516 if (!disp
&& i
.types
[op
].bitfield
.baseindex
)
3518 i
.types
[op
].bitfield
.disp8
= 0;
3519 i
.types
[op
].bitfield
.disp16
= 0;
3520 i
.types
[op
].bitfield
.disp32
= 0;
3521 i
.types
[op
].bitfield
.disp32s
= 0;
3522 i
.types
[op
].bitfield
.disp64
= 0;
3526 else if (flag_code
== CODE_64BIT
)
3528 if (fits_in_signed_long (disp
))
3530 i
.types
[op
].bitfield
.disp64
= 0;
3531 i
.types
[op
].bitfield
.disp32s
= 1;
3533 if (fits_in_unsigned_long (disp
))
3534 i
.types
[op
].bitfield
.disp32
= 1;
3536 if ((i
.types
[op
].bitfield
.disp32
3537 || i
.types
[op
].bitfield
.disp32s
3538 || i
.types
[op
].bitfield
.disp16
)
3539 && fits_in_signed_byte (disp
))
3540 i
.types
[op
].bitfield
.disp8
= 1;
3542 else if (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
3543 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
)
3545 fix_new_exp (frag_now
, frag_more (0) - frag_now
->fr_literal
, 0,
3546 i
.op
[op
].disps
, 0, i
.reloc
[op
]);
3547 i
.types
[op
].bitfield
.disp8
= 0;
3548 i
.types
[op
].bitfield
.disp16
= 0;
3549 i
.types
[op
].bitfield
.disp32
= 0;
3550 i
.types
[op
].bitfield
.disp32s
= 0;
3551 i
.types
[op
].bitfield
.disp64
= 0;
3554 /* We only support 64bit displacement on constants. */
3555 i
.types
[op
].bitfield
.disp64
= 0;
3559 /* Check if operands are valid for the instrucrtion. Update VEX
3563 VEX_check_operands (const template *t
)
3565 if (!t
->opcode_modifier
.vex
)
3568 /* Only check VEX_Imm4, which must be the first operand. */
3569 if (t
->operand_types
[0].bitfield
.vex_imm4
)
3571 if (i
.op
[0].imms
->X_op
!= O_constant
3572 || !fits_in_imm4 (i
.op
[0].imms
->X_add_number
))
3575 /* Turn off Imm8 so that update_imm won't complain. */
3576 i
.types
[0] = vex_imm4
;
3582 static const template *
3583 match_template (void)
3585 /* Points to template once we've found it. */
3587 i386_operand_type overlap0
, overlap1
, overlap2
, overlap3
;
3588 i386_operand_type overlap4
;
3589 unsigned int found_reverse_match
;
3590 i386_opcode_modifier suffix_check
;
3591 i386_operand_type operand_types
[MAX_OPERANDS
];
3592 int addr_prefix_disp
;
3594 unsigned int found_cpu_match
;
3595 unsigned int check_register
;
3597 #if MAX_OPERANDS != 5
3598 # error "MAX_OPERANDS must be 5."
3601 found_reverse_match
= 0;
3602 addr_prefix_disp
= -1;
3604 memset (&suffix_check
, 0, sizeof (suffix_check
));
3605 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
3606 suffix_check
.no_bsuf
= 1;
3607 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
3608 suffix_check
.no_wsuf
= 1;
3609 else if (i
.suffix
== SHORT_MNEM_SUFFIX
)
3610 suffix_check
.no_ssuf
= 1;
3611 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
3612 suffix_check
.no_lsuf
= 1;
3613 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
3614 suffix_check
.no_qsuf
= 1;
3615 else if (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
)
3616 suffix_check
.no_ldsuf
= 1;
3618 for (t
= current_templates
->start
; t
< current_templates
->end
; t
++)
3620 addr_prefix_disp
= -1;
3622 /* Must have right number of operands. */
3623 if (i
.operands
!= t
->operands
)
3626 /* Check processor support. */
3627 found_cpu_match
= (cpu_flags_match (t
)
3628 == CPU_FLAGS_PERFECT_MATCH
);
3629 if (!found_cpu_match
)
3632 /* Check old gcc support. */
3633 if (!old_gcc
&& t
->opcode_modifier
.oldgcc
)
3636 /* Check AT&T mnemonic. */
3637 if (intel_mnemonic
&& t
->opcode_modifier
.attmnemonic
)
3640 /* Check AT&T syntax Intel syntax. */
3641 if ((intel_syntax
&& t
->opcode_modifier
.attsyntax
)
3642 || (!intel_syntax
&& t
->opcode_modifier
.intelsyntax
))
3645 /* Check the suffix, except for some instructions in intel mode. */
3646 if ((!intel_syntax
|| !t
->opcode_modifier
.ignoresize
)
3647 && ((t
->opcode_modifier
.no_bsuf
&& suffix_check
.no_bsuf
)
3648 || (t
->opcode_modifier
.no_wsuf
&& suffix_check
.no_wsuf
)
3649 || (t
->opcode_modifier
.no_lsuf
&& suffix_check
.no_lsuf
)
3650 || (t
->opcode_modifier
.no_ssuf
&& suffix_check
.no_ssuf
)
3651 || (t
->opcode_modifier
.no_qsuf
&& suffix_check
.no_qsuf
)
3652 || (t
->opcode_modifier
.no_ldsuf
&& suffix_check
.no_ldsuf
)))
3655 if (!operand_size_match (t
))
3658 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3659 operand_types
[j
] = t
->operand_types
[j
];
3661 /* In general, don't allow 64-bit operands in 32-bit mode. */
3662 if (i
.suffix
== QWORD_MNEM_SUFFIX
3663 && flag_code
!= CODE_64BIT
3665 ? (!t
->opcode_modifier
.ignoresize
3666 && !intel_float_operand (t
->name
))
3667 : intel_float_operand (t
->name
) != 2)
3668 && ((!operand_types
[0].bitfield
.regmmx
3669 && !operand_types
[0].bitfield
.regxmm
3670 && !operand_types
[0].bitfield
.regymm
)
3671 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
3672 && !!operand_types
[t
->operands
> 1].bitfield
.regxmm
3673 && !!operand_types
[t
->operands
> 1].bitfield
.regymm
))
3674 && (t
->base_opcode
!= 0x0fc7
3675 || t
->extension_opcode
!= 1 /* cmpxchg8b */))
3678 /* In general, don't allow 32-bit operands on pre-386. */
3679 else if (i
.suffix
== LONG_MNEM_SUFFIX
3680 && !cpu_arch_flags
.bitfield
.cpui386
3682 ? (!t
->opcode_modifier
.ignoresize
3683 && !intel_float_operand (t
->name
))
3684 : intel_float_operand (t
->name
) != 2)
3685 && ((!operand_types
[0].bitfield
.regmmx
3686 && !operand_types
[0].bitfield
.regxmm
)
3687 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
3688 && !!operand_types
[t
->operands
> 1].bitfield
.regxmm
)))
3691 /* Do not verify operands when there are none. */
3695 /* We've found a match; break out of loop. */
3699 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
3700 into Disp32/Disp16/Disp32 operand. */
3701 if (i
.prefix
[ADDR_PREFIX
] != 0)
3703 /* There should be only one Disp operand. */
3707 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3709 if (operand_types
[j
].bitfield
.disp16
)
3711 addr_prefix_disp
= j
;
3712 operand_types
[j
].bitfield
.disp32
= 1;
3713 operand_types
[j
].bitfield
.disp16
= 0;
3719 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3721 if (operand_types
[j
].bitfield
.disp32
)
3723 addr_prefix_disp
= j
;
3724 operand_types
[j
].bitfield
.disp32
= 0;
3725 operand_types
[j
].bitfield
.disp16
= 1;
3731 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3733 if (operand_types
[j
].bitfield
.disp64
)
3735 addr_prefix_disp
= j
;
3736 operand_types
[j
].bitfield
.disp64
= 0;
3737 operand_types
[j
].bitfield
.disp32
= 1;
3745 /* We check register size only if size of operands can be
3746 encoded the canonical way. */
3747 check_register
= t
->opcode_modifier
.w
;
3748 overlap0
= operand_type_and (i
.types
[0], operand_types
[0]);
3749 switch (t
->operands
)
3752 if (!operand_type_match (overlap0
, i
.types
[0]))
3756 /* xchg %eax, %eax is a special case. It is an aliase for nop
3757 only in 32bit mode and we can use opcode 0x90. In 64bit
3758 mode, we can't use 0x90 for xchg %eax, %eax since it should
3759 zero-extend %eax to %rax. */
3760 if (flag_code
== CODE_64BIT
3761 && t
->base_opcode
== 0x90
3762 && operand_type_equal (&i
.types
[0], &acc32
)
3763 && operand_type_equal (&i
.types
[1], &acc32
))
3767 /* If we swap operand in encoding, we either match
3768 the next one or reverse direction of operands. */
3769 if (t
->opcode_modifier
.s
)
3771 else if (t
->opcode_modifier
.d
)
3776 /* If we swap operand in encoding, we match the next one. */
3777 if (i
.swap_operand
&& t
->opcode_modifier
.s
)
3781 overlap1
= operand_type_and (i
.types
[1], operand_types
[1]);
3782 if (!operand_type_match (overlap0
, i
.types
[0])
3783 || !operand_type_match (overlap1
, i
.types
[1])
3785 && !operand_type_register_match (overlap0
, i
.types
[0],
3787 overlap1
, i
.types
[1],
3790 /* Check if other direction is valid ... */
3791 if (!t
->opcode_modifier
.d
&& !t
->opcode_modifier
.floatd
)
3795 /* Try reversing direction of operands. */
3796 overlap0
= operand_type_and (i
.types
[0], operand_types
[1]);
3797 overlap1
= operand_type_and (i
.types
[1], operand_types
[0]);
3798 if (!operand_type_match (overlap0
, i
.types
[0])
3799 || !operand_type_match (overlap1
, i
.types
[1])
3801 && !operand_type_register_match (overlap0
,
3808 /* Does not match either direction. */
3811 /* found_reverse_match holds which of D or FloatDR
3813 if (t
->opcode_modifier
.d
)
3814 found_reverse_match
= Opcode_D
;
3815 else if (t
->opcode_modifier
.floatd
)
3816 found_reverse_match
= Opcode_FloatD
;
3818 found_reverse_match
= 0;
3819 if (t
->opcode_modifier
.floatr
)
3820 found_reverse_match
|= Opcode_FloatR
;
3824 /* Found a forward 2 operand match here. */
3825 switch (t
->operands
)
3828 overlap4
= operand_type_and (i
.types
[4],
3831 overlap3
= operand_type_and (i
.types
[3],
3834 overlap2
= operand_type_and (i
.types
[2],
3839 switch (t
->operands
)
3842 if (!operand_type_match (overlap4
, i
.types
[4])
3843 || !operand_type_register_match (overlap3
,
3851 if (!operand_type_match (overlap3
, i
.types
[3])
3853 && !operand_type_register_match (overlap2
,
3861 /* Here we make use of the fact that there are no
3862 reverse match 3 operand instructions, and all 3
3863 operand instructions only need to be checked for
3864 register consistency between operands 2 and 3. */
3865 if (!operand_type_match (overlap2
, i
.types
[2])
3867 && !operand_type_register_match (overlap1
,
3877 /* Found either forward/reverse 2, 3 or 4 operand match here:
3878 slip through to break. */
3880 if (!found_cpu_match
)
3882 found_reverse_match
= 0;
3886 /* Check if VEX operands are valid. */
3887 if (VEX_check_operands (t
))
3890 /* We've found a match; break out of loop. */
3894 if (t
== current_templates
->end
)
3896 /* We found no match. */
3898 as_bad (_("ambiguous operand size or operands invalid for `%s'"),
3899 current_templates
->start
->name
);
3901 as_bad (_("suffix or operands invalid for `%s'"),
3902 current_templates
->start
->name
);
3906 if (!quiet_warnings
)
3909 && (i
.types
[0].bitfield
.jumpabsolute
3910 != operand_types
[0].bitfield
.jumpabsolute
))
3912 as_warn (_("indirect %s without `*'"), t
->name
);
3915 if (t
->opcode_modifier
.isprefix
3916 && t
->opcode_modifier
.ignoresize
)
3918 /* Warn them that a data or address size prefix doesn't
3919 affect assembly of the next line of code. */
3920 as_warn (_("stand-alone `%s' prefix"), t
->name
);
3924 /* Copy the template we found. */
3927 if (addr_prefix_disp
!= -1)
3928 i
.tm
.operand_types
[addr_prefix_disp
]
3929 = operand_types
[addr_prefix_disp
];
3931 if (found_reverse_match
)
3933 /* If we found a reverse match we must alter the opcode
3934 direction bit. found_reverse_match holds bits to change
3935 (different for int & float insns). */
3937 i
.tm
.base_opcode
^= found_reverse_match
;
3939 i
.tm
.operand_types
[0] = operand_types
[1];
3940 i
.tm
.operand_types
[1] = operand_types
[0];
3949 int mem_op
= operand_type_check (i
.types
[0], anymem
) ? 0 : 1;
3950 if (i
.tm
.operand_types
[mem_op
].bitfield
.esseg
)
3952 if (i
.seg
[0] != NULL
&& i
.seg
[0] != &es
)
3954 as_bad (_("`%s' operand %d must use `%ses' segment"),
3960 /* There's only ever one segment override allowed per instruction.
3961 This instruction possibly has a legal segment override on the
3962 second operand, so copy the segment to where non-string
3963 instructions store it, allowing common code. */
3964 i
.seg
[0] = i
.seg
[1];
3966 else if (i
.tm
.operand_types
[mem_op
+ 1].bitfield
.esseg
)
3968 if (i
.seg
[1] != NULL
&& i
.seg
[1] != &es
)
3970 as_bad (_("`%s' operand %d must use `%ses' segment"),
3981 process_suffix (void)
3983 /* If matched instruction specifies an explicit instruction mnemonic
3985 if (i
.tm
.opcode_modifier
.size16
)
3986 i
.suffix
= WORD_MNEM_SUFFIX
;
3987 else if (i
.tm
.opcode_modifier
.size32
)
3988 i
.suffix
= LONG_MNEM_SUFFIX
;
3989 else if (i
.tm
.opcode_modifier
.size64
)
3990 i
.suffix
= QWORD_MNEM_SUFFIX
;
3991 else if (i
.reg_operands
)
3993 /* If there's no instruction mnemonic suffix we try to invent one
3994 based on register operands. */
3997 /* We take i.suffix from the last register operand specified,
3998 Destination register type is more significant than source
3999 register type. crc32 in SSE4.2 prefers source register
4001 if (i
.tm
.base_opcode
== 0xf20f38f1)
4003 if (i
.types
[0].bitfield
.reg16
)
4004 i
.suffix
= WORD_MNEM_SUFFIX
;
4005 else if (i
.types
[0].bitfield
.reg32
)
4006 i
.suffix
= LONG_MNEM_SUFFIX
;
4007 else if (i
.types
[0].bitfield
.reg64
)
4008 i
.suffix
= QWORD_MNEM_SUFFIX
;
4010 else if (i
.tm
.base_opcode
== 0xf20f38f0)
4012 if (i
.types
[0].bitfield
.reg8
)
4013 i
.suffix
= BYTE_MNEM_SUFFIX
;
4020 if (i
.tm
.base_opcode
== 0xf20f38f1
4021 || i
.tm
.base_opcode
== 0xf20f38f0)
4023 /* We have to know the operand size for crc32. */
4024 as_bad (_("ambiguous memory operand size for `%s`"),
4029 for (op
= i
.operands
; --op
>= 0;)
4030 if (!i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
4032 if (i
.types
[op
].bitfield
.reg8
)
4034 i
.suffix
= BYTE_MNEM_SUFFIX
;
4037 else if (i
.types
[op
].bitfield
.reg16
)
4039 i
.suffix
= WORD_MNEM_SUFFIX
;
4042 else if (i
.types
[op
].bitfield
.reg32
)
4044 i
.suffix
= LONG_MNEM_SUFFIX
;
4047 else if (i
.types
[op
].bitfield
.reg64
)
4049 i
.suffix
= QWORD_MNEM_SUFFIX
;
4055 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
4057 if (!check_byte_reg ())
4060 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
4062 if (!check_long_reg ())
4065 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
4068 && i
.tm
.opcode_modifier
.ignoresize
4069 && i
.tm
.opcode_modifier
.no_qsuf
)
4071 else if (!check_qword_reg ())
4074 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
4076 if (!check_word_reg ())
4079 else if (i
.suffix
== XMMWORD_MNEM_SUFFIX
4080 || i
.suffix
== YMMWORD_MNEM_SUFFIX
)
4082 /* Skip if the instruction has x/y suffix. match_template
4083 should check if it is a valid suffix. */
4085 else if (intel_syntax
&& i
.tm
.opcode_modifier
.ignoresize
)
4086 /* Do nothing if the instruction is going to ignore the prefix. */
4091 else if (i
.tm
.opcode_modifier
.defaultsize
4093 /* exclude fldenv/frstor/fsave/fstenv */
4094 && i
.tm
.opcode_modifier
.no_ssuf
)
4096 i
.suffix
= stackop_size
;
4098 else if (intel_syntax
4100 && (i
.tm
.operand_types
[0].bitfield
.jumpabsolute
4101 || i
.tm
.opcode_modifier
.jumpbyte
4102 || i
.tm
.opcode_modifier
.jumpintersegment
4103 || (i
.tm
.base_opcode
== 0x0f01 /* [ls][gi]dt */
4104 && i
.tm
.extension_opcode
<= 3)))
4109 if (!i
.tm
.opcode_modifier
.no_qsuf
)
4111 i
.suffix
= QWORD_MNEM_SUFFIX
;
4115 if (!i
.tm
.opcode_modifier
.no_lsuf
)
4116 i
.suffix
= LONG_MNEM_SUFFIX
;
4119 if (!i
.tm
.opcode_modifier
.no_wsuf
)
4120 i
.suffix
= WORD_MNEM_SUFFIX
;
4129 if (i
.tm
.opcode_modifier
.w
)
4131 as_bad (_("no instruction mnemonic suffix given and "
4132 "no register operands; can't size instruction"));
4138 unsigned int suffixes
;
4140 suffixes
= !i
.tm
.opcode_modifier
.no_bsuf
;
4141 if (!i
.tm
.opcode_modifier
.no_wsuf
)
4143 if (!i
.tm
.opcode_modifier
.no_lsuf
)
4145 if (!i
.tm
.opcode_modifier
.no_ldsuf
)
4147 if (!i
.tm
.opcode_modifier
.no_ssuf
)
4149 if (!i
.tm
.opcode_modifier
.no_qsuf
)
4152 /* There are more than suffix matches. */
4153 if (i
.tm
.opcode_modifier
.w
4154 || ((suffixes
& (suffixes
- 1))
4155 && !i
.tm
.opcode_modifier
.defaultsize
4156 && !i
.tm
.opcode_modifier
.ignoresize
))
4158 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
4164 /* Change the opcode based on the operand size given by i.suffix;
4165 We don't need to change things for byte insns. */
4168 && i
.suffix
!= BYTE_MNEM_SUFFIX
4169 && i
.suffix
!= XMMWORD_MNEM_SUFFIX
4170 && i
.suffix
!= YMMWORD_MNEM_SUFFIX
)
4172 /* It's not a byte, select word/dword operation. */
4173 if (i
.tm
.opcode_modifier
.w
)
4175 if (i
.tm
.opcode_modifier
.shortform
)
4176 i
.tm
.base_opcode
|= 8;
4178 i
.tm
.base_opcode
|= 1;
4181 /* Now select between word & dword operations via the operand
4182 size prefix, except for instructions that will ignore this
4184 if (i
.tm
.opcode_modifier
.addrprefixop0
)
4186 /* The address size override prefix changes the size of the
4188 if ((flag_code
== CODE_32BIT
4189 && i
.op
->regs
[0].reg_type
.bitfield
.reg16
)
4190 || (flag_code
!= CODE_32BIT
4191 && i
.op
->regs
[0].reg_type
.bitfield
.reg32
))
4192 if (!add_prefix (ADDR_PREFIX_OPCODE
))
4195 else if (i
.suffix
!= QWORD_MNEM_SUFFIX
4196 && i
.suffix
!= LONG_DOUBLE_MNEM_SUFFIX
4197 && !i
.tm
.opcode_modifier
.ignoresize
4198 && !i
.tm
.opcode_modifier
.floatmf
4199 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
4200 || (flag_code
== CODE_64BIT
4201 && i
.tm
.opcode_modifier
.jumpbyte
)))
4203 unsigned int prefix
= DATA_PREFIX_OPCODE
;
4205 if (i
.tm
.opcode_modifier
.jumpbyte
) /* jcxz, loop */
4206 prefix
= ADDR_PREFIX_OPCODE
;
4208 if (!add_prefix (prefix
))
4212 /* Set mode64 for an operand. */
4213 if (i
.suffix
== QWORD_MNEM_SUFFIX
4214 && flag_code
== CODE_64BIT
4215 && !i
.tm
.opcode_modifier
.norex64
)
4217 /* Special case for xchg %rax,%rax. It is NOP and doesn't
4218 need rex64. cmpxchg8b is also a special case. */
4219 if (! (i
.operands
== 2
4220 && i
.tm
.base_opcode
== 0x90
4221 && i
.tm
.extension_opcode
== None
4222 && operand_type_equal (&i
.types
[0], &acc64
)
4223 && operand_type_equal (&i
.types
[1], &acc64
))
4224 && ! (i
.operands
== 1
4225 && i
.tm
.base_opcode
== 0xfc7
4226 && i
.tm
.extension_opcode
== 1
4227 && !operand_type_check (i
.types
[0], reg
)
4228 && operand_type_check (i
.types
[0], anymem
)))
4232 /* Size floating point instruction. */
4233 if (i
.suffix
== LONG_MNEM_SUFFIX
)
4234 if (i
.tm
.opcode_modifier
.floatmf
)
4235 i
.tm
.base_opcode
^= 4;
4242 check_byte_reg (void)
4246 for (op
= i
.operands
; --op
>= 0;)
4248 /* If this is an eight bit register, it's OK. If it's the 16 or
4249 32 bit version of an eight bit register, we will just use the
4250 low portion, and that's OK too. */
4251 if (i
.types
[op
].bitfield
.reg8
)
4254 /* Don't generate this warning if not needed. */
4255 if (intel_syntax
&& i
.tm
.opcode_modifier
.byteokintel
)
4258 /* crc32 doesn't generate this warning. */
4259 if (i
.tm
.base_opcode
== 0xf20f38f0)
4262 if ((i
.types
[op
].bitfield
.reg16
4263 || i
.types
[op
].bitfield
.reg32
4264 || i
.types
[op
].bitfield
.reg64
)
4265 && i
.op
[op
].regs
->reg_num
< 4)
4267 /* Prohibit these changes in the 64bit mode, since the
4268 lowering is more complicated. */
4269 if (flag_code
== CODE_64BIT
4270 && !i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
4272 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4273 register_prefix
, i
.op
[op
].regs
->reg_name
,
4277 #if REGISTER_WARNINGS
4279 && !i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
4280 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4282 (i
.op
[op
].regs
+ (i
.types
[op
].bitfield
.reg16
4283 ? REGNAM_AL
- REGNAM_AX
4284 : REGNAM_AL
- REGNAM_EAX
))->reg_name
,
4286 i
.op
[op
].regs
->reg_name
,
4291 /* Any other register is bad. */
4292 if (i
.types
[op
].bitfield
.reg16
4293 || i
.types
[op
].bitfield
.reg32
4294 || i
.types
[op
].bitfield
.reg64
4295 || i
.types
[op
].bitfield
.regmmx
4296 || i
.types
[op
].bitfield
.regxmm
4297 || i
.types
[op
].bitfield
.regymm
4298 || i
.types
[op
].bitfield
.sreg2
4299 || i
.types
[op
].bitfield
.sreg3
4300 || i
.types
[op
].bitfield
.control
4301 || i
.types
[op
].bitfield
.debug
4302 || i
.types
[op
].bitfield
.test
4303 || i
.types
[op
].bitfield
.floatreg
4304 || i
.types
[op
].bitfield
.floatacc
)
4306 as_bad (_("`%s%s' not allowed with `%s%c'"),
4308 i
.op
[op
].regs
->reg_name
,
4318 check_long_reg (void)
4322 for (op
= i
.operands
; --op
>= 0;)
4323 /* Reject eight bit registers, except where the template requires
4324 them. (eg. movzb) */
4325 if (i
.types
[op
].bitfield
.reg8
4326 && (i
.tm
.operand_types
[op
].bitfield
.reg16
4327 || i
.tm
.operand_types
[op
].bitfield
.reg32
4328 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4330 as_bad (_("`%s%s' not allowed with `%s%c'"),
4332 i
.op
[op
].regs
->reg_name
,
4337 /* Warn if the e prefix on a general reg is missing. */
4338 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
4339 && i
.types
[op
].bitfield
.reg16
4340 && (i
.tm
.operand_types
[op
].bitfield
.reg32
4341 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4343 /* Prohibit these changes in the 64bit mode, since the
4344 lowering is more complicated. */
4345 if (flag_code
== CODE_64BIT
)
4347 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4348 register_prefix
, i
.op
[op
].regs
->reg_name
,
4352 #if REGISTER_WARNINGS
4354 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4356 (i
.op
[op
].regs
+ REGNAM_EAX
- REGNAM_AX
)->reg_name
,
4358 i
.op
[op
].regs
->reg_name
,
4362 /* Warn if the r prefix on a general reg is missing. */
4363 else if (i
.types
[op
].bitfield
.reg64
4364 && (i
.tm
.operand_types
[op
].bitfield
.reg32
4365 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4368 && i
.tm
.opcode_modifier
.toqword
4369 && !i
.types
[0].bitfield
.regxmm
)
4371 /* Convert to QWORD. We want REX byte. */
4372 i
.suffix
= QWORD_MNEM_SUFFIX
;
4376 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4377 register_prefix
, i
.op
[op
].regs
->reg_name
,
4386 check_qword_reg (void)
4390 for (op
= i
.operands
; --op
>= 0; )
4391 /* Reject eight bit registers, except where the template requires
4392 them. (eg. movzb) */
4393 if (i
.types
[op
].bitfield
.reg8
4394 && (i
.tm
.operand_types
[op
].bitfield
.reg16
4395 || i
.tm
.operand_types
[op
].bitfield
.reg32
4396 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4398 as_bad (_("`%s%s' not allowed with `%s%c'"),
4400 i
.op
[op
].regs
->reg_name
,
4405 /* Warn if the e prefix on a general reg is missing. */
4406 else if ((i
.types
[op
].bitfield
.reg16
4407 || i
.types
[op
].bitfield
.reg32
)
4408 && (i
.tm
.operand_types
[op
].bitfield
.reg32
4409 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4411 /* Prohibit these changes in the 64bit mode, since the
4412 lowering is more complicated. */
4414 && i
.tm
.opcode_modifier
.todword
4415 && !i
.types
[0].bitfield
.regxmm
)
4417 /* Convert to DWORD. We don't want REX byte. */
4418 i
.suffix
= LONG_MNEM_SUFFIX
;
4422 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4423 register_prefix
, i
.op
[op
].regs
->reg_name
,
4432 check_word_reg (void)
4435 for (op
= i
.operands
; --op
>= 0;)
4436 /* Reject eight bit registers, except where the template requires
4437 them. (eg. movzb) */
4438 if (i
.types
[op
].bitfield
.reg8
4439 && (i
.tm
.operand_types
[op
].bitfield
.reg16
4440 || i
.tm
.operand_types
[op
].bitfield
.reg32
4441 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4443 as_bad (_("`%s%s' not allowed with `%s%c'"),
4445 i
.op
[op
].regs
->reg_name
,
4450 /* Warn if the e prefix on a general reg is present. */
4451 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
4452 && i
.types
[op
].bitfield
.reg32
4453 && (i
.tm
.operand_types
[op
].bitfield
.reg16
4454 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4456 /* Prohibit these changes in the 64bit mode, since the
4457 lowering is more complicated. */
4458 if (flag_code
== CODE_64BIT
)
4460 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4461 register_prefix
, i
.op
[op
].regs
->reg_name
,
4466 #if REGISTER_WARNINGS
4467 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4469 (i
.op
[op
].regs
+ REGNAM_AX
- REGNAM_EAX
)->reg_name
,
4471 i
.op
[op
].regs
->reg_name
,
4479 update_imm (unsigned int j
)
4481 i386_operand_type overlap
;
4483 overlap
= operand_type_and (i
.types
[j
], i
.tm
.operand_types
[j
]);
4484 if ((overlap
.bitfield
.imm8
4485 || overlap
.bitfield
.imm8s
4486 || overlap
.bitfield
.imm16
4487 || overlap
.bitfield
.imm32
4488 || overlap
.bitfield
.imm32s
4489 || overlap
.bitfield
.imm64
)
4490 && !operand_type_equal (&overlap
, &imm8
)
4491 && !operand_type_equal (&overlap
, &imm8s
)
4492 && !operand_type_equal (&overlap
, &imm16
)
4493 && !operand_type_equal (&overlap
, &imm32
)
4494 && !operand_type_equal (&overlap
, &imm32s
)
4495 && !operand_type_equal (&overlap
, &imm64
))
4499 i386_operand_type temp
;
4501 operand_type_set (&temp
, 0);
4502 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
4504 temp
.bitfield
.imm8
= overlap
.bitfield
.imm8
;
4505 temp
.bitfield
.imm8s
= overlap
.bitfield
.imm8s
;
4507 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
4508 temp
.bitfield
.imm16
= overlap
.bitfield
.imm16
;
4509 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
4511 temp
.bitfield
.imm64
= overlap
.bitfield
.imm64
;
4512 temp
.bitfield
.imm32s
= overlap
.bitfield
.imm32s
;
4515 temp
.bitfield
.imm32
= overlap
.bitfield
.imm32
;
4518 else if (operand_type_equal (&overlap
, &imm16_32_32s
)
4519 || operand_type_equal (&overlap
, &imm16_32
)
4520 || operand_type_equal (&overlap
, &imm16_32s
))
4522 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
4527 if (!operand_type_equal (&overlap
, &imm8
)
4528 && !operand_type_equal (&overlap
, &imm8s
)
4529 && !operand_type_equal (&overlap
, &imm16
)
4530 && !operand_type_equal (&overlap
, &imm32
)
4531 && !operand_type_equal (&overlap
, &imm32s
)
4532 && !operand_type_equal (&overlap
, &imm64
))
4534 as_bad (_("no instruction mnemonic suffix given; "
4535 "can't determine immediate size"));
4539 i
.types
[j
] = overlap
;
4549 for (j
= 0; j
< 2; j
++)
4550 if (update_imm (j
) == 0)
4553 i
.types
[2] = operand_type_and (i
.types
[2], i
.tm
.operand_types
[2]);
4554 assert (operand_type_check (i
.types
[2], imm
) == 0);
4562 i
.drex
.modrm_reg
= 0;
4563 i
.drex
.modrm_regmem
= 0;
4565 /* SSE5 4 operand instructions must have the destination the same as
4566 one of the inputs. Figure out the destination register and cache
4567 it away in the drex field, and remember which fields to use for
4569 if (i
.tm
.opcode_modifier
.drex
4570 && i
.tm
.opcode_modifier
.drexv
4573 i
.tm
.extension_opcode
= None
;
4575 /* Case 1: 4 operand insn, dest = src1, src3 = register. */
4576 if (i
.types
[0].bitfield
.regxmm
!= 0
4577 && i
.types
[1].bitfield
.regxmm
!= 0
4578 && i
.types
[2].bitfield
.regxmm
!= 0
4579 && i
.types
[3].bitfield
.regxmm
!= 0
4580 && i
.op
[0].regs
->reg_num
== i
.op
[3].regs
->reg_num
4581 && i
.op
[0].regs
->reg_flags
== i
.op
[3].regs
->reg_flags
)
4583 /* Clear the arguments that are stored in drex. */
4584 operand_type_set (&i
.types
[0], 0);
4585 operand_type_set (&i
.types
[3], 0);
4586 i
.reg_operands
-= 2;
4588 /* There are two different ways to encode a 4 operand
4589 instruction with all registers that uses OC1 set to
4590 0 or 1. Favor setting OC1 to 0 since this mimics the
4591 actions of other SSE5 assemblers. Use modrm encoding 2
4592 for register/register. Include the high order bit that
4593 is normally stored in the REX byte in the register
4595 i
.tm
.extension_opcode
= DREX_X1_XMEM_X2_X1
;
4596 i
.drex
.modrm_reg
= 2;
4597 i
.drex
.modrm_regmem
= 1;
4598 i
.drex
.reg
= (i
.op
[3].regs
->reg_num
4599 + ((i
.op
[3].regs
->reg_flags
& RegRex
) ? 8 : 0));
4602 /* Case 2: 4 operand insn, dest = src1, src3 = memory. */
4603 else if (i
.types
[0].bitfield
.regxmm
!= 0
4604 && i
.types
[1].bitfield
.regxmm
!= 0
4605 && (i
.types
[2].bitfield
.regxmm
4606 || operand_type_check (i
.types
[2], anymem
))
4607 && i
.types
[3].bitfield
.regxmm
!= 0
4608 && i
.op
[0].regs
->reg_num
== i
.op
[3].regs
->reg_num
4609 && i
.op
[0].regs
->reg_flags
== i
.op
[3].regs
->reg_flags
)
4611 /* clear the arguments that are stored in drex */
4612 operand_type_set (&i
.types
[0], 0);
4613 operand_type_set (&i
.types
[3], 0);
4614 i
.reg_operands
-= 2;
4616 /* Specify the modrm encoding for memory addressing. Include
4617 the high order bit that is normally stored in the REX byte
4618 in the register field. */
4619 i
.tm
.extension_opcode
= DREX_X1_X2_XMEM_X1
;
4620 i
.drex
.modrm_reg
= 1;
4621 i
.drex
.modrm_regmem
= 2;
4622 i
.drex
.reg
= (i
.op
[3].regs
->reg_num
4623 + ((i
.op
[3].regs
->reg_flags
& RegRex
) ? 8 : 0));
4626 /* Case 3: 4 operand insn, dest = src1, src2 = memory. */
4627 else if (i
.types
[0].bitfield
.regxmm
!= 0
4628 && operand_type_check (i
.types
[1], anymem
) != 0
4629 && i
.types
[2].bitfield
.regxmm
!= 0
4630 && i
.types
[3].bitfield
.regxmm
!= 0
4631 && i
.op
[0].regs
->reg_num
== i
.op
[3].regs
->reg_num
4632 && i
.op
[0].regs
->reg_flags
== i
.op
[3].regs
->reg_flags
)
4634 /* Clear the arguments that are stored in drex. */
4635 operand_type_set (&i
.types
[0], 0);
4636 operand_type_set (&i
.types
[3], 0);
4637 i
.reg_operands
-= 2;
4639 /* Specify the modrm encoding for memory addressing. Include
4640 the high order bit that is normally stored in the REX byte
4641 in the register field. */
4642 i
.tm
.extension_opcode
= DREX_X1_XMEM_X2_X1
;
4643 i
.drex
.modrm_reg
= 2;
4644 i
.drex
.modrm_regmem
= 1;
4645 i
.drex
.reg
= (i
.op
[3].regs
->reg_num
4646 + ((i
.op
[3].regs
->reg_flags
& RegRex
) ? 8 : 0));
4649 /* Case 4: 4 operand insn, dest = src3, src2 = register. */
4650 else if (i
.types
[0].bitfield
.regxmm
!= 0
4651 && i
.types
[1].bitfield
.regxmm
!= 0
4652 && i
.types
[2].bitfield
.regxmm
!= 0
4653 && i
.types
[3].bitfield
.regxmm
!= 0
4654 && i
.op
[2].regs
->reg_num
== i
.op
[3].regs
->reg_num
4655 && i
.op
[2].regs
->reg_flags
== i
.op
[3].regs
->reg_flags
)
4657 /* clear the arguments that are stored in drex */
4658 operand_type_set (&i
.types
[2], 0);
4659 operand_type_set (&i
.types
[3], 0);
4660 i
.reg_operands
-= 2;
4662 /* There are two different ways to encode a 4 operand
4663 instruction with all registers that uses OC1 set to
4664 0 or 1. Favor setting OC1 to 0 since this mimics the
4665 actions of other SSE5 assemblers. Use modrm encoding
4666 2 for register/register. Include the high order bit that
4667 is normally stored in the REX byte in the register
4669 i
.tm
.extension_opcode
= DREX_XMEM_X1_X2_X2
;
4670 i
.drex
.modrm_reg
= 1;
4671 i
.drex
.modrm_regmem
= 0;
4673 /* Remember the register, including the upper bits */
4674 i
.drex
.reg
= (i
.op
[3].regs
->reg_num
4675 + ((i
.op
[3].regs
->reg_flags
& RegRex
) ? 8 : 0));
4678 /* Case 5: 4 operand insn, dest = src3, src2 = memory. */
4679 else if (i
.types
[0].bitfield
.regxmm
!= 0
4680 && (i
.types
[1].bitfield
.regxmm
4681 || operand_type_check (i
.types
[1], anymem
))
4682 && i
.types
[2].bitfield
.regxmm
!= 0
4683 && i
.types
[3].bitfield
.regxmm
!= 0
4684 && i
.op
[2].regs
->reg_num
== i
.op
[3].regs
->reg_num
4685 && i
.op
[2].regs
->reg_flags
== i
.op
[3].regs
->reg_flags
)
4687 /* Clear the arguments that are stored in drex. */
4688 operand_type_set (&i
.types
[2], 0);
4689 operand_type_set (&i
.types
[3], 0);
4690 i
.reg_operands
-= 2;
4692 /* Specify the modrm encoding and remember the register
4693 including the bits normally stored in the REX byte. */
4694 i
.tm
.extension_opcode
= DREX_X1_XMEM_X2_X2
;
4695 i
.drex
.modrm_reg
= 0;
4696 i
.drex
.modrm_regmem
= 1;
4697 i
.drex
.reg
= (i
.op
[3].regs
->reg_num
4698 + ((i
.op
[3].regs
->reg_flags
& RegRex
) ? 8 : 0));
4701 /* Case 6: 4 operand insn, dest = src3, src1 = memory. */
4702 else if (operand_type_check (i
.types
[0], anymem
) != 0
4703 && i
.types
[1].bitfield
.regxmm
!= 0
4704 && i
.types
[2].bitfield
.regxmm
!= 0
4705 && i
.types
[3].bitfield
.regxmm
!= 0
4706 && i
.op
[2].regs
->reg_num
== i
.op
[3].regs
->reg_num
4707 && i
.op
[2].regs
->reg_flags
== i
.op
[3].regs
->reg_flags
)
4709 /* clear the arguments that are stored in drex */
4710 operand_type_set (&i
.types
[2], 0);
4711 operand_type_set (&i
.types
[3], 0);
4712 i
.reg_operands
-= 2;
4714 /* Specify the modrm encoding and remember the register
4715 including the bits normally stored in the REX byte. */
4716 i
.tm
.extension_opcode
= DREX_XMEM_X1_X2_X2
;
4717 i
.drex
.modrm_reg
= 1;
4718 i
.drex
.modrm_regmem
= 0;
4719 i
.drex
.reg
= (i
.op
[3].regs
->reg_num
4720 + ((i
.op
[3].regs
->reg_flags
& RegRex
) ? 8 : 0));
4724 as_bad (_("Incorrect operands for the '%s' instruction"),
4728 /* SSE5 instructions with the DREX byte where the only memory operand
4729 is in the 2nd argument, and the first and last xmm register must
4730 match, and is encoded in the DREX byte. */
4731 else if (i
.tm
.opcode_modifier
.drex
4732 && !i
.tm
.opcode_modifier
.drexv
4735 /* Case 1: 4 operand insn, dest = src1, src3 = reg/mem. */
4736 if (i
.types
[0].bitfield
.regxmm
!= 0
4737 && (i
.types
[1].bitfield
.regxmm
4738 || operand_type_check(i
.types
[1], anymem
))
4739 && i
.types
[2].bitfield
.regxmm
!= 0
4740 && i
.types
[3].bitfield
.regxmm
!= 0
4741 && i
.op
[0].regs
->reg_num
== i
.op
[3].regs
->reg_num
4742 && i
.op
[0].regs
->reg_flags
== i
.op
[3].regs
->reg_flags
)
4744 /* clear the arguments that are stored in drex */
4745 operand_type_set (&i
.types
[0], 0);
4746 operand_type_set (&i
.types
[3], 0);
4747 i
.reg_operands
-= 2;
4749 /* Specify the modrm encoding and remember the register
4750 including the high bit normally stored in the REX
4752 i
.drex
.modrm_reg
= 2;
4753 i
.drex
.modrm_regmem
= 1;
4754 i
.drex
.reg
= (i
.op
[3].regs
->reg_num
4755 + ((i
.op
[3].regs
->reg_flags
& RegRex
) ? 8 : 0));
4759 as_bad (_("Incorrect operands for the '%s' instruction"),
4763 /* SSE5 3 operand instructions that the result is a register, being
4764 either operand can be a memory operand, using OC0 to note which
4765 one is the memory. */
4766 else if (i
.tm
.opcode_modifier
.drex
4767 && i
.tm
.opcode_modifier
.drexv
4770 i
.tm
.extension_opcode
= None
;
4772 /* Case 1: 3 operand insn, src1 = register. */
4773 if (i
.types
[0].bitfield
.regxmm
!= 0
4774 && i
.types
[1].bitfield
.regxmm
!= 0
4775 && i
.types
[2].bitfield
.regxmm
!= 0)
4777 /* Clear the arguments that are stored in drex. */
4778 operand_type_set (&i
.types
[2], 0);
4781 /* Specify the modrm encoding and remember the register
4782 including the high bit normally stored in the REX byte. */
4783 i
.tm
.extension_opcode
= DREX_XMEM_X1_X2
;
4784 i
.drex
.modrm_reg
= 1;
4785 i
.drex
.modrm_regmem
= 0;
4786 i
.drex
.reg
= (i
.op
[2].regs
->reg_num
4787 + ((i
.op
[2].regs
->reg_flags
& RegRex
) ? 8 : 0));
4790 /* Case 2: 3 operand insn, src1 = memory. */
4791 else if (operand_type_check (i
.types
[0], anymem
) != 0
4792 && i
.types
[1].bitfield
.regxmm
!= 0
4793 && i
.types
[2].bitfield
.regxmm
!= 0)
4795 /* Clear the arguments that are stored in drex. */
4796 operand_type_set (&i
.types
[2], 0);
4799 /* Specify the modrm encoding and remember the register
4800 including the high bit normally stored in the REX
4802 i
.tm
.extension_opcode
= DREX_XMEM_X1_X2
;
4803 i
.drex
.modrm_reg
= 1;
4804 i
.drex
.modrm_regmem
= 0;
4805 i
.drex
.reg
= (i
.op
[2].regs
->reg_num
4806 + ((i
.op
[2].regs
->reg_flags
& RegRex
) ? 8 : 0));
4809 /* Case 3: 3 operand insn, src2 = memory. */
4810 else if (i
.types
[0].bitfield
.regxmm
!= 0
4811 && operand_type_check (i
.types
[1], anymem
) != 0
4812 && i
.types
[2].bitfield
.regxmm
!= 0)
4814 /* Clear the arguments that are stored in drex. */
4815 operand_type_set (&i
.types
[2], 0);
4818 /* Specify the modrm encoding and remember the register
4819 including the high bit normally stored in the REX byte. */
4820 i
.tm
.extension_opcode
= DREX_X1_XMEM_X2
;
4821 i
.drex
.modrm_reg
= 0;
4822 i
.drex
.modrm_regmem
= 1;
4823 i
.drex
.reg
= (i
.op
[2].regs
->reg_num
4824 + ((i
.op
[2].regs
->reg_flags
& RegRex
) ? 8 : 0));
4828 as_bad (_("Incorrect operands for the '%s' instruction"),
4832 /* SSE5 4 operand instructions that are the comparison instructions
4833 where the first operand is the immediate value of the comparison
4835 else if (i
.tm
.opcode_modifier
.drexc
!= 0 && i
.operands
== 4)
4837 /* Case 1: 4 operand insn, src1 = reg/memory. */
4838 if (operand_type_check (i
.types
[0], imm
) != 0
4839 && (i
.types
[1].bitfield
.regxmm
4840 || operand_type_check (i
.types
[1], anymem
))
4841 && i
.types
[2].bitfield
.regxmm
!= 0
4842 && i
.types
[3].bitfield
.regxmm
!= 0)
4844 /* clear the arguments that are stored in drex */
4845 operand_type_set (&i
.types
[3], 0);
4848 /* Specify the modrm encoding and remember the register
4849 including the high bit normally stored in the REX byte. */
4850 i
.drex
.modrm_reg
= 2;
4851 i
.drex
.modrm_regmem
= 1;
4852 i
.drex
.reg
= (i
.op
[3].regs
->reg_num
4853 + ((i
.op
[3].regs
->reg_flags
& RegRex
) ? 8 : 0));
4856 /* Case 2: 3 operand insn with ImmExt that places the
4857 opcode_extension as an immediate argument. This is used for
4858 all of the varients of comparison that supplies the appropriate
4859 value as part of the instruction. */
4860 else if ((i
.types
[0].bitfield
.regxmm
4861 || operand_type_check (i
.types
[0], anymem
))
4862 && i
.types
[1].bitfield
.regxmm
!= 0
4863 && i
.types
[2].bitfield
.regxmm
!= 0
4864 && operand_type_check (i
.types
[3], imm
) != 0)
4866 /* clear the arguments that are stored in drex */
4867 operand_type_set (&i
.types
[2], 0);
4870 /* Specify the modrm encoding and remember the register
4871 including the high bit normally stored in the REX byte. */
4872 i
.drex
.modrm_reg
= 1;
4873 i
.drex
.modrm_regmem
= 0;
4874 i
.drex
.reg
= (i
.op
[2].regs
->reg_num
4875 + ((i
.op
[2].regs
->reg_flags
& RegRex
) ? 8 : 0));
4879 as_bad (_("Incorrect operands for the '%s' instruction"),
4883 else if (i
.tm
.opcode_modifier
.drex
4884 || i
.tm
.opcode_modifier
.drexv
4885 || i
.tm
.opcode_modifier
.drexc
)
4886 as_bad (_("Internal error for the '%s' instruction"), i
.tm
.name
);
4890 bad_implicit_operand (int xmm
)
4892 const char *reg
= xmm
? "xmm0" : "ymm0";
4894 as_bad (_("the last operand of `%s' must be `%s%s'"),
4895 i
.tm
.name
, register_prefix
, reg
);
4897 as_bad (_("the first operand of `%s' must be `%s%s'"),
4898 i
.tm
.name
, register_prefix
, reg
);
4903 process_operands (void)
4905 /* Default segment register this instruction will use for memory
4906 accesses. 0 means unknown. This is only for optimizing out
4907 unnecessary segment overrides. */
4908 const seg_entry
*default_seg
= 0;
4910 /* Handle all of the DREX munging that SSE5 needs. */
4911 if (i
.tm
.opcode_modifier
.drex
4912 || i
.tm
.opcode_modifier
.drexv
4913 || i
.tm
.opcode_modifier
.drexc
)
4916 if (i
.tm
.opcode_modifier
.sse2avx
4917 && (i
.tm
.opcode_modifier
.vexnds
4918 || i
.tm
.opcode_modifier
.vexndd
))
4920 unsigned int dup
= i
.operands
;
4921 unsigned int dest
= dup
- 1;
4924 /* The destination must be an xmm register. */
4925 assert (i
.reg_operands
4926 && MAX_OPERANDS
> dup
4927 && operand_type_equal (&i
.types
[dest
], ®xmm
));
4929 if (i
.tm
.opcode_modifier
.firstxmm0
)
4931 /* The first operand is implicit and must be xmm0. */
4932 assert (operand_type_equal (&i
.types
[0], ®xmm
));
4933 if (i
.op
[0].regs
->reg_num
!= 0)
4934 return bad_implicit_operand (1);
4936 if (i
.tm
.opcode_modifier
.vex3sources
)
4938 /* Keep xmm0 for instructions with VEX prefix and 3
4944 /* We remove the first xmm0 and keep the number of
4945 operands unchanged, which in fact duplicates the
4947 for (j
= 1; j
< i
.operands
; j
++)
4949 i
.op
[j
- 1] = i
.op
[j
];
4950 i
.types
[j
- 1] = i
.types
[j
];
4951 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
4955 else if (i
.tm
.opcode_modifier
.implicit1stxmm0
)
4957 assert ((MAX_OPERANDS
- 1) > dup
4958 && i
.tm
.opcode_modifier
.vex3sources
);
4960 /* Add the implicit xmm0 for instructions with VEX prefix
4962 for (j
= i
.operands
; j
> 0; j
--)
4964 i
.op
[j
] = i
.op
[j
- 1];
4965 i
.types
[j
] = i
.types
[j
- 1];
4966 i
.tm
.operand_types
[j
] = i
.tm
.operand_types
[j
- 1];
4969 = (const reg_entry
*) hash_find (reg_hash
, "xmm0");
4970 i
.types
[0] = regxmm
;
4971 i
.tm
.operand_types
[0] = regxmm
;
4974 i
.reg_operands
+= 2;
4979 i
.op
[dup
] = i
.op
[dest
];
4980 i
.types
[dup
] = i
.types
[dest
];
4981 i
.tm
.operand_types
[dup
] = i
.tm
.operand_types
[dest
];
4990 i
.op
[dup
] = i
.op
[dest
];
4991 i
.types
[dup
] = i
.types
[dest
];
4992 i
.tm
.operand_types
[dup
] = i
.tm
.operand_types
[dest
];
4995 if (i
.tm
.opcode_modifier
.immext
)
4998 else if (i
.tm
.opcode_modifier
.firstxmm0
)
5002 /* The first operand is implicit and must be xmm0/ymm0. */
5003 assert (i
.reg_operands
5004 && (operand_type_equal (&i
.types
[0], ®xmm
)
5005 || operand_type_equal (&i
.types
[0], ®ymm
)));
5006 if (i
.op
[0].regs
->reg_num
!= 0)
5007 return bad_implicit_operand (i
.types
[0].bitfield
.regxmm
);
5009 for (j
= 1; j
< i
.operands
; j
++)
5011 i
.op
[j
- 1] = i
.op
[j
];
5012 i
.types
[j
- 1] = i
.types
[j
];
5014 /* We need to adjust fields in i.tm since they are used by
5015 build_modrm_byte. */
5016 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
5023 else if (i
.tm
.opcode_modifier
.regkludge
)
5025 /* The imul $imm, %reg instruction is converted into
5026 imul $imm, %reg, %reg, and the clr %reg instruction
5027 is converted into xor %reg, %reg. */
5029 unsigned int first_reg_op
;
5031 if (operand_type_check (i
.types
[0], reg
))
5035 /* Pretend we saw the extra register operand. */
5036 assert (i
.reg_operands
== 1
5037 && i
.op
[first_reg_op
+ 1].regs
== 0);
5038 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
5039 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
5044 if (i
.tm
.opcode_modifier
.shortform
)
5046 if (i
.types
[0].bitfield
.sreg2
5047 || i
.types
[0].bitfield
.sreg3
)
5049 if (i
.tm
.base_opcode
== POP_SEG_SHORT
5050 && i
.op
[0].regs
->reg_num
== 1)
5052 as_bad (_("you can't `pop %scs'"), register_prefix
);
5055 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
5056 if ((i
.op
[0].regs
->reg_flags
& RegRex
) != 0)
5061 /* The register or float register operand is in operand
5065 if (i
.types
[0].bitfield
.floatreg
5066 || operand_type_check (i
.types
[0], reg
))
5070 /* Register goes in low 3 bits of opcode. */
5071 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
5072 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
5074 if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
5076 /* Warn about some common errors, but press on regardless.
5077 The first case can be generated by gcc (<= 2.8.1). */
5078 if (i
.operands
== 2)
5080 /* Reversed arguments on faddp, fsubp, etc. */
5081 as_warn (_("translating to `%s %s%s,%s%s'"), i
.tm
.name
,
5082 register_prefix
, i
.op
[1].regs
->reg_name
,
5083 register_prefix
, i
.op
[0].regs
->reg_name
);
5087 /* Extraneous `l' suffix on fp insn. */
5088 as_warn (_("translating to `%s %s%s'"), i
.tm
.name
,
5089 register_prefix
, i
.op
[0].regs
->reg_name
);
5094 else if (i
.tm
.opcode_modifier
.modrm
)
5096 /* The opcode is completed (modulo i.tm.extension_opcode which
5097 must be put into the modrm byte). Now, we make the modrm and
5098 index base bytes based on all the info we've collected. */
5100 default_seg
= build_modrm_byte ();
5102 else if ((i
.tm
.base_opcode
& ~0x3) == MOV_AX_DISP32
)
5106 else if (i
.tm
.opcode_modifier
.isstring
)
5108 /* For the string instructions that allow a segment override
5109 on one of their operands, the default segment is ds. */
5113 if (i
.tm
.base_opcode
== 0x8d /* lea */
5116 as_warn (_("segment override on `%s' is ineffectual"), i
.tm
.name
);
5118 /* If a segment was explicitly specified, and the specified segment
5119 is not the default, use an opcode prefix to select it. If we
5120 never figured out what the default segment is, then default_seg
5121 will be zero at this point, and the specified segment prefix will
5123 if ((i
.seg
[0]) && (i
.seg
[0] != default_seg
))
5125 if (!add_prefix (i
.seg
[0]->seg_prefix
))
5131 static const seg_entry
*
5132 build_modrm_byte (void)
5134 const seg_entry
*default_seg
= 0;
5135 unsigned int source
, dest
;
5138 /* The first operand of instructions with VEX prefix and 3 sources
5139 must be VEX_Imm4. */
5140 vex_3_sources
= i
.tm
.opcode_modifier
.vex3sources
;
5143 unsigned int nds
, reg
;
5145 dest
= i
.operands
- 1;
5150 /* This instruction must have 4 operands: 4 register operands
5151 or 3 register operands plus 1 memory operand. It must have
5152 VexNDS and VexImmExt. */
5153 assert (i
.operands
== 4
5154 && (i
.reg_operands
== 4
5155 || (i
.reg_operands
== 3 && i
.mem_operands
== 1))
5156 && i
.tm
.opcode_modifier
.vexnds
5157 && i
.tm
.opcode_modifier
.veximmext
5158 && (operand_type_equal (&i
.tm
.operand_types
[dest
],
5160 || operand_type_equal (&i
.tm
.operand_types
[dest
],
5162 && (operand_type_equal (&i
.tm
.operand_types
[nds
],
5164 || operand_type_equal (&i
.tm
.operand_types
[nds
],
5166 && (operand_type_equal (&i
.tm
.operand_types
[reg
],
5168 || operand_type_equal (&i
.tm
.operand_types
[reg
],
5171 /* Generate an 8bit immediate operand to encode the register
5173 expressionS
*exp
= &im_expressions
[i
.imm_operands
++];
5174 i
.op
[i
.operands
].imms
= exp
;
5175 i
.types
[i
.operands
] = imm8
;
5177 exp
->X_op
= O_constant
;
5179 = ((i
.op
[0].regs
->reg_num
5180 + ((i
.op
[0].regs
->reg_flags
& RegRex
) ? 8 : 0)) << 4);
5182 i
.vex
.register_specifier
= i
.op
[nds
].regs
;
5187 /* SSE5 4 operand instructions are encoded in such a way that one of
5188 the inputs must match the destination register. Process_drex hides
5189 the 3rd argument in the drex field, so that by the time we get
5190 here, it looks to GAS as if this is a 2 operand instruction. */
5191 if ((i
.tm
.opcode_modifier
.drex
5192 || i
.tm
.opcode_modifier
.drexv
5193 || i
.tm
.opcode_modifier
.drexc
)
5194 && i
.reg_operands
== 2)
5196 const reg_entry
*reg
= i
.op
[i
.drex
.modrm_reg
].regs
;
5197 const reg_entry
*regmem
= i
.op
[i
.drex
.modrm_regmem
].regs
;
5199 i
.rm
.reg
= reg
->reg_num
;
5200 i
.rm
.regmem
= regmem
->reg_num
;
5202 if ((reg
->reg_flags
& RegRex
) != 0)
5204 if ((regmem
->reg_flags
& RegRex
) != 0)
5208 /* i.reg_operands MUST be the number of real register operands;
5209 implicit registers do not count. If there are 3 register
5210 operands, it must be a instruction with VexNDS. For a
5211 instruction with VexNDD, the destination register is encoded
5212 in VEX prefix. If there are 4 register operands, it must be
5213 a instruction with VEX prefix and 3 sources. */
5214 else if (i
.mem_operands
== 0
5215 && ((i
.reg_operands
== 2
5216 && !i
.tm
.opcode_modifier
.vexndd
)
5217 || (i
.reg_operands
== 3
5218 && i
.tm
.opcode_modifier
.vexnds
)
5219 || (i
.reg_operands
== 4 && vex_3_sources
)))
5227 /* When there are 3 operands, one of them may be immediate,
5228 which may be the first or the last operand. Otherwise,
5229 the first operand must be shift count register (cl) or it
5230 is an instruction with VexNDS. */
5231 assert (i
.imm_operands
== 1
5232 || (i
.imm_operands
== 0
5233 && (i
.tm
.opcode_modifier
.vexnds
5234 || i
.types
[0].bitfield
.shiftcount
)));
5235 if (operand_type_check (i
.types
[0], imm
)
5236 || i
.types
[0].bitfield
.shiftcount
)
5242 /* When there are 4 operands, the first two must be 8bit
5243 immediate operands. The source operand will be the 3rd
5246 For instructions with VexNDS, if the first operand
5247 an imm8, the source operand is the 2nd one. If the last
5248 operand is imm8, the source operand is the first one. */
5249 assert ((i
.imm_operands
== 2
5250 && i
.types
[0].bitfield
.imm8
5251 && i
.types
[1].bitfield
.imm8
)
5252 || (i
.tm
.opcode_modifier
.vexnds
5253 && i
.imm_operands
== 1
5254 && (i
.types
[0].bitfield
.imm8
5255 || i
.types
[i
.operands
- 1].bitfield
.imm8
)));
5256 if (i
.tm
.opcode_modifier
.vexnds
)
5258 if (i
.types
[0].bitfield
.imm8
)
5276 if (i
.tm
.opcode_modifier
.vexnds
)
5278 /* For instructions with VexNDS, the register-only
5279 source operand must be XMM or YMM register. It is
5280 encoded in VEX prefix. We need to clear RegMem bit
5281 before calling operand_type_equal. */
5282 i386_operand_type op
= i
.tm
.operand_types
[dest
];
5283 op
.bitfield
.regmem
= 0;
5284 if ((dest
+ 1) >= i
.operands
5285 || (!operand_type_equal (&op
, ®xmm
)
5286 && !operand_type_equal (&op
, ®ymm
)))
5288 i
.vex
.register_specifier
= i
.op
[dest
].regs
;
5294 /* One of the register operands will be encoded in the i.tm.reg
5295 field, the other in the combined i.tm.mode and i.tm.regmem
5296 fields. If no form of this instruction supports a memory
5297 destination operand, then we assume the source operand may
5298 sometimes be a memory operand and so we need to store the
5299 destination in the i.rm.reg field. */
5300 if (!i
.tm
.operand_types
[dest
].bitfield
.regmem
5301 && operand_type_check (i
.tm
.operand_types
[dest
], anymem
) == 0)
5303 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
5304 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
5305 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
5307 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
5312 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
5313 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
5314 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
5316 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
5319 if (flag_code
!= CODE_64BIT
&& (i
.rex
& (REX_R
| REX_B
)))
5321 if (!i
.types
[0].bitfield
.control
5322 && !i
.types
[1].bitfield
.control
)
5324 i
.rex
&= ~(REX_R
| REX_B
);
5325 add_prefix (LOCK_PREFIX_OPCODE
);
5329 { /* If it's not 2 reg operands... */
5334 unsigned int fake_zero_displacement
= 0;
5337 /* This has been precalculated for SSE5 instructions
5338 that have a DREX field earlier in process_drex. */
5339 if (i
.tm
.opcode_modifier
.drex
5340 || i
.tm
.opcode_modifier
.drexv
5341 || i
.tm
.opcode_modifier
.drexc
)
5342 op
= i
.drex
.modrm_regmem
;
5345 for (op
= 0; op
< i
.operands
; op
++)
5346 if (operand_type_check (i
.types
[op
], anymem
))
5348 assert (op
< i
.operands
);
5353 if (i
.base_reg
== 0)
5356 if (!i
.disp_operands
)
5357 fake_zero_displacement
= 1;
5358 if (i
.index_reg
== 0)
5360 /* Operand is just <disp> */
5361 if (flag_code
== CODE_64BIT
)
5363 /* 64bit mode overwrites the 32bit absolute
5364 addressing by RIP relative addressing and
5365 absolute addressing is encoded by one of the
5366 redundant SIB forms. */
5367 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
5368 i
.sib
.base
= NO_BASE_REGISTER
;
5369 i
.sib
.index
= NO_INDEX_REGISTER
;
5370 i
.types
[op
] = ((i
.prefix
[ADDR_PREFIX
] == 0)
5371 ? disp32s
: disp32
);
5373 else if ((flag_code
== CODE_16BIT
)
5374 ^ (i
.prefix
[ADDR_PREFIX
] != 0))
5376 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
5377 i
.types
[op
] = disp16
;
5381 i
.rm
.regmem
= NO_BASE_REGISTER
;
5382 i
.types
[op
] = disp32
;
5385 else /* !i.base_reg && i.index_reg */
5387 if (i
.index_reg
->reg_num
== RegEiz
5388 || i
.index_reg
->reg_num
== RegRiz
)
5389 i
.sib
.index
= NO_INDEX_REGISTER
;
5391 i
.sib
.index
= i
.index_reg
->reg_num
;
5392 i
.sib
.base
= NO_BASE_REGISTER
;
5393 i
.sib
.scale
= i
.log2_scale_factor
;
5394 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
5395 i
.types
[op
].bitfield
.disp8
= 0;
5396 i
.types
[op
].bitfield
.disp16
= 0;
5397 i
.types
[op
].bitfield
.disp64
= 0;
5398 if (flag_code
!= CODE_64BIT
)
5400 /* Must be 32 bit */
5401 i
.types
[op
].bitfield
.disp32
= 1;
5402 i
.types
[op
].bitfield
.disp32s
= 0;
5406 i
.types
[op
].bitfield
.disp32
= 0;
5407 i
.types
[op
].bitfield
.disp32s
= 1;
5409 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
5413 /* RIP addressing for 64bit mode. */
5414 else if (i
.base_reg
->reg_num
== RegRip
||
5415 i
.base_reg
->reg_num
== RegEip
)
5417 i
.rm
.regmem
= NO_BASE_REGISTER
;
5418 i
.types
[op
].bitfield
.disp8
= 0;
5419 i
.types
[op
].bitfield
.disp16
= 0;
5420 i
.types
[op
].bitfield
.disp32
= 0;
5421 i
.types
[op
].bitfield
.disp32s
= 1;
5422 i
.types
[op
].bitfield
.disp64
= 0;
5423 i
.flags
[op
] |= Operand_PCrel
;
5424 if (! i
.disp_operands
)
5425 fake_zero_displacement
= 1;
5427 else if (i
.base_reg
->reg_type
.bitfield
.reg16
)
5429 switch (i
.base_reg
->reg_num
)
5432 if (i
.index_reg
== 0)
5434 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
5435 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
5439 if (i
.index_reg
== 0)
5442 if (operand_type_check (i
.types
[op
], disp
) == 0)
5444 /* fake (%bp) into 0(%bp) */
5445 i
.types
[op
].bitfield
.disp8
= 1;
5446 fake_zero_displacement
= 1;
5449 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
5450 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
5452 default: /* (%si) -> 4 or (%di) -> 5 */
5453 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
5455 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
5457 else /* i.base_reg and 32/64 bit mode */
5459 if (flag_code
== CODE_64BIT
5460 && operand_type_check (i
.types
[op
], disp
))
5462 i386_operand_type temp
;
5463 operand_type_set (&temp
, 0);
5464 temp
.bitfield
.disp8
= i
.types
[op
].bitfield
.disp8
;
5466 if (i
.prefix
[ADDR_PREFIX
] == 0)
5467 i
.types
[op
].bitfield
.disp32s
= 1;
5469 i
.types
[op
].bitfield
.disp32
= 1;
5472 i
.rm
.regmem
= i
.base_reg
->reg_num
;
5473 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
5475 i
.sib
.base
= i
.base_reg
->reg_num
;
5476 /* x86-64 ignores REX prefix bit here to avoid decoder
5478 if ((i
.base_reg
->reg_num
& 7) == EBP_REG_NUM
)
5481 if (i
.disp_operands
== 0)
5483 fake_zero_displacement
= 1;
5484 i
.types
[op
].bitfield
.disp8
= 1;
5487 else if (i
.base_reg
->reg_num
== ESP_REG_NUM
)
5491 i
.sib
.scale
= i
.log2_scale_factor
;
5492 if (i
.index_reg
== 0)
5494 /* <disp>(%esp) becomes two byte modrm with no index
5495 register. We've already stored the code for esp
5496 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
5497 Any base register besides %esp will not use the
5498 extra modrm byte. */
5499 i
.sib
.index
= NO_INDEX_REGISTER
;
5503 if (i
.index_reg
->reg_num
== RegEiz
5504 || i
.index_reg
->reg_num
== RegRiz
)
5505 i
.sib
.index
= NO_INDEX_REGISTER
;
5507 i
.sib
.index
= i
.index_reg
->reg_num
;
5508 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
5509 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
5514 && (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
5515 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
))
5518 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
5521 if (fake_zero_displacement
)
5523 /* Fakes a zero displacement assuming that i.types[op]
5524 holds the correct displacement size. */
5527 assert (i
.op
[op
].disps
== 0);
5528 exp
= &disp_expressions
[i
.disp_operands
++];
5529 i
.op
[op
].disps
= exp
;
5530 exp
->X_op
= O_constant
;
5531 exp
->X_add_number
= 0;
5532 exp
->X_add_symbol
= (symbolS
*) 0;
5533 exp
->X_op_symbol
= (symbolS
*) 0;
5541 /* Fill in i.rm.reg or i.rm.regmem field with register operand
5542 (if any) based on i.tm.extension_opcode. Again, we must be
5543 careful to make sure that segment/control/debug/test/MMX
5544 registers are coded into the i.rm.reg field. */
5549 /* This has been precalculated for SSE5 instructions
5550 that have a DREX field earlier in process_drex. */
5551 if (i
.tm
.opcode_modifier
.drex
5552 || i
.tm
.opcode_modifier
.drexv
5553 || i
.tm
.opcode_modifier
.drexc
)
5555 op
= i
.drex
.modrm_reg
;
5556 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
5557 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
5562 unsigned int vex_reg
= ~0;
5564 for (op
= 0; op
< i
.operands
; op
++)
5565 if (i
.types
[op
].bitfield
.reg8
5566 || i
.types
[op
].bitfield
.reg16
5567 || i
.types
[op
].bitfield
.reg32
5568 || i
.types
[op
].bitfield
.reg64
5569 || i
.types
[op
].bitfield
.regmmx
5570 || i
.types
[op
].bitfield
.regxmm
5571 || i
.types
[op
].bitfield
.regymm
5572 || i
.types
[op
].bitfield
.sreg2
5573 || i
.types
[op
].bitfield
.sreg3
5574 || i
.types
[op
].bitfield
.control
5575 || i
.types
[op
].bitfield
.debug
5576 || i
.types
[op
].bitfield
.test
)
5581 else if (i
.tm
.opcode_modifier
.vexnds
)
5583 /* For instructions with VexNDS, the register-only
5584 source operand is encoded in VEX prefix. */
5585 assert (mem
!= (unsigned int) ~0);
5590 assert (op
< i
.operands
);
5595 assert (vex_reg
< i
.operands
);
5598 else if (i
.tm
.opcode_modifier
.vexndd
)
5600 /* For instructions with VexNDD, there should be
5601 no memory operand and the register destination
5602 is encoded in VEX prefix. */
5603 assert (i
.mem_operands
== 0
5604 && (op
+ 2) == i
.operands
);
5608 assert (op
< i
.operands
);
5610 if (vex_reg
!= (unsigned int) ~0)
5612 assert (i
.reg_operands
== 2);
5614 if (!operand_type_equal (&i
.tm
.operand_types
[vex_reg
],
5616 && !operand_type_equal (&i
.tm
.operand_types
[vex_reg
],
5619 i
.vex
.register_specifier
= i
.op
[vex_reg
].regs
;
5622 /* If there is an extension opcode to put here, the
5623 register number must be put into the regmem field. */
5624 if (i
.tm
.extension_opcode
!= None
)
5626 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
5627 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
5632 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
5633 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
5638 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
5639 must set it to 3 to indicate this is a register operand
5640 in the regmem field. */
5641 if (!i
.mem_operands
)
5645 /* Fill in i.rm.reg field with extension opcode (if any). */
5646 if (i
.tm
.extension_opcode
!= None
5647 && !(i
.tm
.opcode_modifier
.drex
5648 || i
.tm
.opcode_modifier
.drexv
5649 || i
.tm
.opcode_modifier
.drexc
))
5650 i
.rm
.reg
= i
.tm
.extension_opcode
;
5656 output_branch (void)
5661 relax_substateT subtype
;
5666 if (flag_code
== CODE_16BIT
)
5670 if (i
.prefix
[DATA_PREFIX
] != 0)
5676 /* Pentium4 branch hints. */
5677 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
5678 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
5683 if (i
.prefix
[REX_PREFIX
] != 0)
5689 if (i
.prefixes
!= 0 && !intel_syntax
)
5690 as_warn (_("skipping prefixes on this instruction"));
5692 /* It's always a symbol; End frag & setup for relax.
5693 Make sure there is enough room in this frag for the largest
5694 instruction we may generate in md_convert_frag. This is 2
5695 bytes for the opcode and room for the prefix and largest
5697 frag_grow (prefix
+ 2 + 4);
5698 /* Prefix and 1 opcode byte go in fr_fix. */
5699 p
= frag_more (prefix
+ 1);
5700 if (i
.prefix
[DATA_PREFIX
] != 0)
5701 *p
++ = DATA_PREFIX_OPCODE
;
5702 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
5703 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
5704 *p
++ = i
.prefix
[SEG_PREFIX
];
5705 if (i
.prefix
[REX_PREFIX
] != 0)
5706 *p
++ = i
.prefix
[REX_PREFIX
];
5707 *p
= i
.tm
.base_opcode
;
5709 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
5710 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, SMALL
);
5711 else if (cpu_arch_flags
.bitfield
.cpui386
)
5712 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, SMALL
);
5714 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, SMALL
);
5717 sym
= i
.op
[0].disps
->X_add_symbol
;
5718 off
= i
.op
[0].disps
->X_add_number
;
5720 if (i
.op
[0].disps
->X_op
!= O_constant
5721 && i
.op
[0].disps
->X_op
!= O_symbol
)
5723 /* Handle complex expressions. */
5724 sym
= make_expr_symbol (i
.op
[0].disps
);
5728 /* 1 possible extra opcode + 4 byte displacement go in var part.
5729 Pass reloc in fr_var. */
5730 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
5740 if (i
.tm
.opcode_modifier
.jumpbyte
)
5742 /* This is a loop or jecxz type instruction. */
5744 if (i
.prefix
[ADDR_PREFIX
] != 0)
5746 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
5749 /* Pentium4 branch hints. */
5750 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
5751 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
5753 FRAG_APPEND_1_CHAR (i
.prefix
[SEG_PREFIX
]);
5762 if (flag_code
== CODE_16BIT
)
5765 if (i
.prefix
[DATA_PREFIX
] != 0)
5767 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
5777 if (i
.prefix
[REX_PREFIX
] != 0)
5779 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
5783 if (i
.prefixes
!= 0 && !intel_syntax
)
5784 as_warn (_("skipping prefixes on this instruction"));
5786 p
= frag_more (1 + size
);
5787 *p
++ = i
.tm
.base_opcode
;
5789 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
5790 i
.op
[0].disps
, 1, reloc (size
, 1, 1, i
.reloc
[0]));
5792 /* All jumps handled here are signed, but don't use a signed limit
5793 check for 32 and 16 bit jumps as we want to allow wrap around at
5794 4G and 64k respectively. */
5796 fixP
->fx_signed
= 1;
5800 output_interseg_jump (void)
5808 if (flag_code
== CODE_16BIT
)
5812 if (i
.prefix
[DATA_PREFIX
] != 0)
5818 if (i
.prefix
[REX_PREFIX
] != 0)
5828 if (i
.prefixes
!= 0 && !intel_syntax
)
5829 as_warn (_("skipping prefixes on this instruction"));
5831 /* 1 opcode; 2 segment; offset */
5832 p
= frag_more (prefix
+ 1 + 2 + size
);
5834 if (i
.prefix
[DATA_PREFIX
] != 0)
5835 *p
++ = DATA_PREFIX_OPCODE
;
5837 if (i
.prefix
[REX_PREFIX
] != 0)
5838 *p
++ = i
.prefix
[REX_PREFIX
];
5840 *p
++ = i
.tm
.base_opcode
;
5841 if (i
.op
[1].imms
->X_op
== O_constant
)
5843 offsetT n
= i
.op
[1].imms
->X_add_number
;
5846 && !fits_in_unsigned_word (n
)
5847 && !fits_in_signed_word (n
))
5849 as_bad (_("16-bit jump out of range"));
5852 md_number_to_chars (p
, n
, size
);
5855 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
5856 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
5857 if (i
.op
[0].imms
->X_op
!= O_constant
)
5858 as_bad (_("can't handle non absolute segment in `%s'"),
5860 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
5866 fragS
*insn_start_frag
;
5867 offsetT insn_start_off
;
5869 /* Tie dwarf2 debug info to the address at the start of the insn.
5870 We can't do this after the insn has been output as the current
5871 frag may have been closed off. eg. by frag_var. */
5872 dwarf2_emit_insn (0);
5874 insn_start_frag
= frag_now
;
5875 insn_start_off
= frag_now_fix ();
5878 if (i
.tm
.opcode_modifier
.jump
)
5880 else if (i
.tm
.opcode_modifier
.jumpbyte
5881 || i
.tm
.opcode_modifier
.jumpdword
)
5883 else if (i
.tm
.opcode_modifier
.jumpintersegment
)
5884 output_interseg_jump ();
5887 /* Output normal instructions here. */
5891 unsigned int prefix
;
5893 /* Since the VEX prefix contains the implicit prefix, we don't
5894 need the explicit prefix. */
5895 if (!i
.tm
.opcode_modifier
.vex
)
5897 switch (i
.tm
.opcode_length
)
5900 if (i
.tm
.base_opcode
& 0xff000000)
5902 prefix
= (i
.tm
.base_opcode
>> 24) & 0xff;
5907 if ((i
.tm
.base_opcode
& 0xff0000) != 0)
5909 prefix
= (i
.tm
.base_opcode
>> 16) & 0xff;
5910 if (i
.tm
.cpu_flags
.bitfield
.cpupadlock
)
5913 if (prefix
!= REPE_PREFIX_OPCODE
5914 || (i
.prefix
[LOCKREP_PREFIX
]
5915 != REPE_PREFIX_OPCODE
))
5916 add_prefix (prefix
);
5919 add_prefix (prefix
);
5928 /* The prefix bytes. */
5929 for (j
= ARRAY_SIZE (i
.prefix
), q
= i
.prefix
; j
> 0; j
--, q
++)
5931 FRAG_APPEND_1_CHAR (*q
);
5934 if (i
.tm
.opcode_modifier
.vex
)
5936 for (j
= 0, q
= i
.prefix
; j
< ARRAY_SIZE (i
.prefix
); j
++, q
++)
5941 /* REX byte is encoded in VEX prefix. */
5945 FRAG_APPEND_1_CHAR (*q
);
5948 /* There should be no other prefixes for instructions
5953 /* Now the VEX prefix. */
5954 p
= frag_more (i
.vex
.length
);
5955 for (j
= 0; j
< i
.vex
.length
; j
++)
5956 p
[j
] = i
.vex
.bytes
[j
];
5959 /* Now the opcode; be careful about word order here! */
5960 if (i
.tm
.opcode_length
== 1)
5962 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
5966 switch (i
.tm
.opcode_length
)
5970 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
5980 /* Put out high byte first: can't use md_number_to_chars! */
5981 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
5982 *p
= i
.tm
.base_opcode
& 0xff;
5984 /* On SSE5, encode the OC1 bit in the DREX field if this
5985 encoding has multiple formats. */
5986 if (i
.tm
.opcode_modifier
.drex
5987 && i
.tm
.opcode_modifier
.drexv
5988 && DREX_OC1 (i
.tm
.extension_opcode
))
5989 *p
|= DREX_OC1_MASK
;
5992 /* Now the modrm byte and sib byte (if present). */
5993 if (i
.tm
.opcode_modifier
.modrm
)
5995 FRAG_APPEND_1_CHAR ((i
.rm
.regmem
<< 0
5998 /* If i.rm.regmem == ESP (4)
5999 && i.rm.mode != (Register mode)
6001 ==> need second modrm byte. */
6002 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
6004 && !(i
.base_reg
&& i
.base_reg
->reg_type
.bitfield
.reg16
))
6005 FRAG_APPEND_1_CHAR ((i
.sib
.base
<< 0
6007 | i
.sib
.scale
<< 6));
6010 /* Write the DREX byte if needed. */
6011 if (i
.tm
.opcode_modifier
.drex
|| i
.tm
.opcode_modifier
.drexc
)
6014 *p
= (((i
.drex
.reg
& 0xf) << 4) | (i
.drex
.rex
& 0x7));
6016 /* Encode the OC0 bit if this encoding has multiple
6018 if ((i
.tm
.opcode_modifier
.drex
6019 || i
.tm
.opcode_modifier
.drexv
)
6020 && DREX_OC0 (i
.tm
.extension_opcode
))
6021 *p
|= DREX_OC0_MASK
;
6024 if (i
.disp_operands
)
6025 output_disp (insn_start_frag
, insn_start_off
);
6028 output_imm (insn_start_frag
, insn_start_off
);
6034 pi ("" /*line*/, &i
);
6036 #endif /* DEBUG386 */
6039 /* Return the size of the displacement operand N. */
6042 disp_size (unsigned int n
)
6045 if (i
.types
[n
].bitfield
.disp64
)
6047 else if (i
.types
[n
].bitfield
.disp8
)
6049 else if (i
.types
[n
].bitfield
.disp16
)
6054 /* Return the size of the immediate operand N. */
6057 imm_size (unsigned int n
)
6060 if (i
.types
[n
].bitfield
.imm64
)
6062 else if (i
.types
[n
].bitfield
.imm8
|| i
.types
[n
].bitfield
.imm8s
)
6064 else if (i
.types
[n
].bitfield
.imm16
)
6070 output_disp (fragS
*insn_start_frag
, offsetT insn_start_off
)
6075 for (n
= 0; n
< i
.operands
; n
++)
6077 if (operand_type_check (i
.types
[n
], disp
))
6079 if (i
.op
[n
].disps
->X_op
== O_constant
)
6081 int size
= disp_size (n
);
6084 val
= offset_in_range (i
.op
[n
].disps
->X_add_number
,
6086 p
= frag_more (size
);
6087 md_number_to_chars (p
, val
, size
);
6091 enum bfd_reloc_code_real reloc_type
;
6092 int size
= disp_size (n
);
6093 int sign
= i
.types
[n
].bitfield
.disp32s
;
6094 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
6096 /* We can't have 8 bit displacement here. */
6097 assert (!i
.types
[n
].bitfield
.disp8
);
6099 /* The PC relative address is computed relative
6100 to the instruction boundary, so in case immediate
6101 fields follows, we need to adjust the value. */
6102 if (pcrel
&& i
.imm_operands
)
6107 for (n1
= 0; n1
< i
.operands
; n1
++)
6108 if (operand_type_check (i
.types
[n1
], imm
))
6110 /* Only one immediate is allowed for PC
6111 relative address. */
6114 i
.op
[n
].disps
->X_add_number
-= sz
;
6116 /* We should find the immediate. */
6120 p
= frag_more (size
);
6121 reloc_type
= reloc (size
, pcrel
, sign
, i
.reloc
[n
]);
6123 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
6124 && (((reloc_type
== BFD_RELOC_32
6125 || reloc_type
== BFD_RELOC_X86_64_32S
6126 || (reloc_type
== BFD_RELOC_64
6128 && (i
.op
[n
].disps
->X_op
== O_symbol
6129 || (i
.op
[n
].disps
->X_op
== O_add
6130 && ((symbol_get_value_expression
6131 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
6133 || reloc_type
== BFD_RELOC_32_PCREL
))
6137 if (insn_start_frag
== frag_now
)
6138 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
6143 add
= insn_start_frag
->fr_fix
- insn_start_off
;
6144 for (fr
= insn_start_frag
->fr_next
;
6145 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
6147 add
+= p
- frag_now
->fr_literal
;
6152 reloc_type
= BFD_RELOC_386_GOTPC
;
6153 i
.op
[n
].imms
->X_add_number
+= add
;
6155 else if (reloc_type
== BFD_RELOC_64
)
6156 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
6158 /* Don't do the adjustment for x86-64, as there
6159 the pcrel addressing is relative to the _next_
6160 insn, and that is taken care of in other code. */
6161 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
6163 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
6164 i
.op
[n
].disps
, pcrel
, reloc_type
);
6171 output_imm (fragS
*insn_start_frag
, offsetT insn_start_off
)
6176 for (n
= 0; n
< i
.operands
; n
++)
6178 if (operand_type_check (i
.types
[n
], imm
))
6180 if (i
.op
[n
].imms
->X_op
== O_constant
)
6182 int size
= imm_size (n
);
6185 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
6187 p
= frag_more (size
);
6188 md_number_to_chars (p
, val
, size
);
6192 /* Not absolute_section.
6193 Need a 32-bit fixup (don't support 8bit
6194 non-absolute imms). Try to support other
6196 enum bfd_reloc_code_real reloc_type
;
6197 int size
= imm_size (n
);
6200 if (i
.types
[n
].bitfield
.imm32s
6201 && (i
.suffix
== QWORD_MNEM_SUFFIX
6202 || (!i
.suffix
&& i
.tm
.opcode_modifier
.no_lsuf
)))
6207 p
= frag_more (size
);
6208 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
6210 /* This is tough to explain. We end up with this one if we
6211 * have operands that look like
6212 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
6213 * obtain the absolute address of the GOT, and it is strongly
6214 * preferable from a performance point of view to avoid using
6215 * a runtime relocation for this. The actual sequence of
6216 * instructions often look something like:
6221 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
6223 * The call and pop essentially return the absolute address
6224 * of the label .L66 and store it in %ebx. The linker itself
6225 * will ultimately change the first operand of the addl so
6226 * that %ebx points to the GOT, but to keep things simple, the
6227 * .o file must have this operand set so that it generates not
6228 * the absolute address of .L66, but the absolute address of
6229 * itself. This allows the linker itself simply treat a GOTPC
6230 * relocation as asking for a pcrel offset to the GOT to be
6231 * added in, and the addend of the relocation is stored in the
6232 * operand field for the instruction itself.
6234 * Our job here is to fix the operand so that it would add
6235 * the correct offset so that %ebx would point to itself. The
6236 * thing that is tricky is that .-.L66 will point to the
6237 * beginning of the instruction, so we need to further modify
6238 * the operand so that it will point to itself. There are
6239 * other cases where you have something like:
6241 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
6243 * and here no correction would be required. Internally in
6244 * the assembler we treat operands of this form as not being
6245 * pcrel since the '.' is explicitly mentioned, and I wonder
6246 * whether it would simplify matters to do it this way. Who
6247 * knows. In earlier versions of the PIC patches, the
6248 * pcrel_adjust field was used to store the correction, but
6249 * since the expression is not pcrel, I felt it would be
6250 * confusing to do it this way. */
6252 if ((reloc_type
== BFD_RELOC_32
6253 || reloc_type
== BFD_RELOC_X86_64_32S
6254 || reloc_type
== BFD_RELOC_64
)
6256 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
6257 && (i
.op
[n
].imms
->X_op
== O_symbol
6258 || (i
.op
[n
].imms
->X_op
== O_add
6259 && ((symbol_get_value_expression
6260 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
6265 if (insn_start_frag
== frag_now
)
6266 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
6271 add
= insn_start_frag
->fr_fix
- insn_start_off
;
6272 for (fr
= insn_start_frag
->fr_next
;
6273 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
6275 add
+= p
- frag_now
->fr_literal
;
6279 reloc_type
= BFD_RELOC_386_GOTPC
;
6281 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
6283 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
6284 i
.op
[n
].imms
->X_add_number
+= add
;
6286 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
6287 i
.op
[n
].imms
, 0, reloc_type
);
6293 /* x86_cons_fix_new is called via the expression parsing code when a
6294 reloc is needed. We use this hook to get the correct .got reloc. */
6295 static enum bfd_reloc_code_real got_reloc
= NO_RELOC
;
6296 static int cons_sign
= -1;
6299 x86_cons_fix_new (fragS
*frag
, unsigned int off
, unsigned int len
,
6302 enum bfd_reloc_code_real r
= reloc (len
, 0, cons_sign
, got_reloc
);
6304 got_reloc
= NO_RELOC
;
6307 if (exp
->X_op
== O_secrel
)
6309 exp
->X_op
= O_symbol
;
6310 r
= BFD_RELOC_32_SECREL
;
6314 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
6317 #if (!defined (OBJ_ELF) && !defined (OBJ_MAYBE_ELF)) || defined (LEX_AT)
6318 # define lex_got(reloc, adjust, types) NULL
6320 /* Parse operands of the form
6321 <symbol>@GOTOFF+<nnn>
6322 and similar .plt or .got references.
6324 If we find one, set up the correct relocation in RELOC and copy the
6325 input string, minus the `@GOTOFF' into a malloc'd buffer for
6326 parsing by the calling routine. Return this buffer, and if ADJUST
6327 is non-null set it to the length of the string we removed from the
6328 input line. Otherwise return NULL. */
6330 lex_got (enum bfd_reloc_code_real
*reloc
,
6332 i386_operand_type
*types
)
6334 /* Some of the relocations depend on the size of what field is to
6335 be relocated. But in our callers i386_immediate and i386_displacement
6336 we don't yet know the operand size (this will be set by insn
6337 matching). Hence we record the word32 relocation here,
6338 and adjust the reloc according to the real size in reloc(). */
6339 static const struct {
6341 const enum bfd_reloc_code_real rel
[2];
6342 const i386_operand_type types64
;
6345 BFD_RELOC_X86_64_PLTOFF64
},
6346 OPERAND_TYPE_IMM64
},
6347 { "PLT", { BFD_RELOC_386_PLT32
,
6348 BFD_RELOC_X86_64_PLT32
},
6349 OPERAND_TYPE_IMM32_32S_DISP32
},
6351 BFD_RELOC_X86_64_GOTPLT64
},
6352 OPERAND_TYPE_IMM64_DISP64
},
6353 { "GOTOFF", { BFD_RELOC_386_GOTOFF
,
6354 BFD_RELOC_X86_64_GOTOFF64
},
6355 OPERAND_TYPE_IMM64_DISP64
},
6357 BFD_RELOC_X86_64_GOTPCREL
},
6358 OPERAND_TYPE_IMM32_32S_DISP32
},
6359 { "TLSGD", { BFD_RELOC_386_TLS_GD
,
6360 BFD_RELOC_X86_64_TLSGD
},
6361 OPERAND_TYPE_IMM32_32S_DISP32
},
6362 { "TLSLDM", { BFD_RELOC_386_TLS_LDM
,
6364 OPERAND_TYPE_NONE
},
6366 BFD_RELOC_X86_64_TLSLD
},
6367 OPERAND_TYPE_IMM32_32S_DISP32
},
6368 { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32
,
6369 BFD_RELOC_X86_64_GOTTPOFF
},
6370 OPERAND_TYPE_IMM32_32S_DISP32
},
6371 { "TPOFF", { BFD_RELOC_386_TLS_LE_32
,
6372 BFD_RELOC_X86_64_TPOFF32
},
6373 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
6374 { "NTPOFF", { BFD_RELOC_386_TLS_LE
,
6376 OPERAND_TYPE_NONE
},
6377 { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32
,
6378 BFD_RELOC_X86_64_DTPOFF32
},
6380 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
6381 { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE
,
6383 OPERAND_TYPE_NONE
},
6384 { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE
,
6386 OPERAND_TYPE_NONE
},
6387 { "GOT", { BFD_RELOC_386_GOT32
,
6388 BFD_RELOC_X86_64_GOT32
},
6389 OPERAND_TYPE_IMM32_32S_64_DISP32
},
6390 { "TLSDESC", { BFD_RELOC_386_TLS_GOTDESC
,
6391 BFD_RELOC_X86_64_GOTPC32_TLSDESC
},
6392 OPERAND_TYPE_IMM32_32S_DISP32
},
6393 { "TLSCALL", { BFD_RELOC_386_TLS_DESC_CALL
,
6394 BFD_RELOC_X86_64_TLSDESC_CALL
},
6395 OPERAND_TYPE_IMM32_32S_DISP32
},
6403 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
6404 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
6407 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
6411 len
= strlen (gotrel
[j
].str
);
6412 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
6414 if (gotrel
[j
].rel
[object_64bit
] != 0)
6417 char *tmpbuf
, *past_reloc
;
6419 *reloc
= gotrel
[j
].rel
[object_64bit
];
6425 if (flag_code
!= CODE_64BIT
)
6427 types
->bitfield
.imm32
= 1;
6428 types
->bitfield
.disp32
= 1;
6431 *types
= gotrel
[j
].types64
;
6434 if (GOT_symbol
== NULL
)
6435 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
6437 /* The length of the first part of our input line. */
6438 first
= cp
- input_line_pointer
;
6440 /* The second part goes from after the reloc token until
6441 (and including) an end_of_line char or comma. */
6442 past_reloc
= cp
+ 1 + len
;
6444 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
6446 second
= cp
+ 1 - past_reloc
;
6448 /* Allocate and copy string. The trailing NUL shouldn't
6449 be necessary, but be safe. */
6450 tmpbuf
= xmalloc (first
+ second
+ 2);
6451 memcpy (tmpbuf
, input_line_pointer
, first
);
6452 if (second
!= 0 && *past_reloc
!= ' ')
6453 /* Replace the relocation token with ' ', so that
6454 errors like foo@GOTOFF1 will be detected. */
6455 tmpbuf
[first
++] = ' ';
6456 memcpy (tmpbuf
+ first
, past_reloc
, second
);
6457 tmpbuf
[first
+ second
] = '\0';
6461 as_bad (_("@%s reloc is not supported with %d-bit output format"),
6462 gotrel
[j
].str
, 1 << (5 + object_64bit
));
6467 /* Might be a symbol version string. Don't as_bad here. */
6472 x86_cons (expressionS
*exp
, int size
)
6474 if (size
== 4 || (object_64bit
&& size
== 8))
6476 /* Handle @GOTOFF and the like in an expression. */
6478 char *gotfree_input_line
;
6481 save
= input_line_pointer
;
6482 gotfree_input_line
= lex_got (&got_reloc
, &adjust
, NULL
);
6483 if (gotfree_input_line
)
6484 input_line_pointer
= gotfree_input_line
;
6488 if (gotfree_input_line
)
6490 /* expression () has merrily parsed up to the end of line,
6491 or a comma - in the wrong buffer. Transfer how far
6492 input_line_pointer has moved to the right buffer. */
6493 input_line_pointer
= (save
6494 + (input_line_pointer
- gotfree_input_line
)
6496 free (gotfree_input_line
);
6497 if (exp
->X_op
== O_constant
6498 || exp
->X_op
== O_absent
6499 || exp
->X_op
== O_illegal
6500 || exp
->X_op
== O_register
6501 || exp
->X_op
== O_big
)
6503 char c
= *input_line_pointer
;
6504 *input_line_pointer
= 0;
6505 as_bad (_("missing or invalid expression `%s'"), save
);
6506 *input_line_pointer
= c
;
6515 static void signed_cons (int size
)
6517 if (flag_code
== CODE_64BIT
)
6525 pe_directive_secrel (dummy
)
6526 int dummy ATTRIBUTE_UNUSED
;
6533 if (exp
.X_op
== O_symbol
)
6534 exp
.X_op
= O_secrel
;
6536 emit_expr (&exp
, 4);
6538 while (*input_line_pointer
++ == ',');
6540 input_line_pointer
--;
6541 demand_empty_rest_of_line ();
6546 i386_immediate (char *imm_start
)
6548 char *save_input_line_pointer
;
6549 char *gotfree_input_line
;
6552 i386_operand_type types
;
6554 operand_type_set (&types
, ~0);
6556 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
6558 as_bad (_("at most %d immediate operands are allowed"),
6559 MAX_IMMEDIATE_OPERANDS
);
6563 exp
= &im_expressions
[i
.imm_operands
++];
6564 i
.op
[this_operand
].imms
= exp
;
6566 if (is_space_char (*imm_start
))
6569 save_input_line_pointer
= input_line_pointer
;
6570 input_line_pointer
= imm_start
;
6572 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
6573 if (gotfree_input_line
)
6574 input_line_pointer
= gotfree_input_line
;
6576 exp_seg
= expression (exp
);
6579 if (*input_line_pointer
)
6580 as_bad (_("junk `%s' after expression"), input_line_pointer
);
6582 input_line_pointer
= save_input_line_pointer
;
6583 if (gotfree_input_line
)
6584 free (gotfree_input_line
);
6586 if (exp
->X_op
== O_absent
6587 || exp
->X_op
== O_illegal
6588 || exp
->X_op
== O_big
6589 || (gotfree_input_line
6590 && (exp
->X_op
== O_constant
6591 || exp
->X_op
== O_register
)))
6593 as_bad (_("missing or invalid immediate expression `%s'"),
6597 else if (exp
->X_op
== O_constant
)
6599 /* Size it properly later. */
6600 i
.types
[this_operand
].bitfield
.imm64
= 1;
6601 /* If BFD64, sign extend val. */
6602 if (!use_rela_relocations
6603 && (exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
6605 = (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
6607 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
6608 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
6609 && exp_seg
!= absolute_section
6610 && exp_seg
!= text_section
6611 && exp_seg
!= data_section
6612 && exp_seg
!= bss_section
6613 && exp_seg
!= undefined_section
6614 && !bfd_is_com_section (exp_seg
))
6616 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
6620 else if (!intel_syntax
&& exp
->X_op
== O_register
)
6622 as_bad (_("illegal immediate register operand %s"), imm_start
);
6627 /* This is an address. The size of the address will be
6628 determined later, depending on destination register,
6629 suffix, or the default for the section. */
6630 i
.types
[this_operand
].bitfield
.imm8
= 1;
6631 i
.types
[this_operand
].bitfield
.imm16
= 1;
6632 i
.types
[this_operand
].bitfield
.imm32
= 1;
6633 i
.types
[this_operand
].bitfield
.imm32s
= 1;
6634 i
.types
[this_operand
].bitfield
.imm64
= 1;
6635 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
6643 i386_scale (char *scale
)
6646 char *save
= input_line_pointer
;
6648 input_line_pointer
= scale
;
6649 val
= get_absolute_expression ();
6654 i
.log2_scale_factor
= 0;
6657 i
.log2_scale_factor
= 1;
6660 i
.log2_scale_factor
= 2;
6663 i
.log2_scale_factor
= 3;
6667 char sep
= *input_line_pointer
;
6669 *input_line_pointer
= '\0';
6670 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
6672 *input_line_pointer
= sep
;
6673 input_line_pointer
= save
;
6677 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
6679 as_warn (_("scale factor of %d without an index register"),
6680 1 << i
.log2_scale_factor
);
6681 i
.log2_scale_factor
= 0;
6683 scale
= input_line_pointer
;
6684 input_line_pointer
= save
;
6689 i386_displacement (char *disp_start
, char *disp_end
)
6693 char *save_input_line_pointer
;
6694 char *gotfree_input_line
;
6696 i386_operand_type bigdisp
, types
= anydisp
;
6699 if (i
.disp_operands
== MAX_MEMORY_OPERANDS
)
6701 as_bad (_("at most %d displacement operands are allowed"),
6702 MAX_MEMORY_OPERANDS
);
6706 operand_type_set (&bigdisp
, 0);
6707 if ((i
.types
[this_operand
].bitfield
.jumpabsolute
)
6708 || (!current_templates
->start
->opcode_modifier
.jump
6709 && !current_templates
->start
->opcode_modifier
.jumpdword
))
6711 bigdisp
.bitfield
.disp32
= 1;
6712 override
= (i
.prefix
[ADDR_PREFIX
] != 0);
6713 if (flag_code
== CODE_64BIT
)
6717 bigdisp
.bitfield
.disp32s
= 1;
6718 bigdisp
.bitfield
.disp64
= 1;
6721 else if ((flag_code
== CODE_16BIT
) ^ override
)
6723 bigdisp
.bitfield
.disp32
= 0;
6724 bigdisp
.bitfield
.disp16
= 1;
6729 /* For PC-relative branches, the width of the displacement
6730 is dependent upon data size, not address size. */
6731 override
= (i
.prefix
[DATA_PREFIX
] != 0);
6732 if (flag_code
== CODE_64BIT
)
6734 if (override
|| i
.suffix
== WORD_MNEM_SUFFIX
)
6735 bigdisp
.bitfield
.disp16
= 1;
6738 bigdisp
.bitfield
.disp32
= 1;
6739 bigdisp
.bitfield
.disp32s
= 1;
6745 override
= (i
.suffix
== (flag_code
!= CODE_16BIT
6747 : LONG_MNEM_SUFFIX
));
6748 bigdisp
.bitfield
.disp32
= 1;
6749 if ((flag_code
== CODE_16BIT
) ^ override
)
6751 bigdisp
.bitfield
.disp32
= 0;
6752 bigdisp
.bitfield
.disp16
= 1;
6756 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
6759 exp
= &disp_expressions
[i
.disp_operands
];
6760 i
.op
[this_operand
].disps
= exp
;
6762 save_input_line_pointer
= input_line_pointer
;
6763 input_line_pointer
= disp_start
;
6764 END_STRING_AND_SAVE (disp_end
);
6766 #ifndef GCC_ASM_O_HACK
6767 #define GCC_ASM_O_HACK 0
6770 END_STRING_AND_SAVE (disp_end
+ 1);
6771 if (i
.types
[this_operand
].bitfield
.baseIndex
6772 && displacement_string_end
[-1] == '+')
6774 /* This hack is to avoid a warning when using the "o"
6775 constraint within gcc asm statements.
6778 #define _set_tssldt_desc(n,addr,limit,type) \
6779 __asm__ __volatile__ ( \
6781 "movw %w1,2+%0\n\t" \
6783 "movb %b1,4+%0\n\t" \
6784 "movb %4,5+%0\n\t" \
6785 "movb $0,6+%0\n\t" \
6786 "movb %h1,7+%0\n\t" \
6788 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
6790 This works great except that the output assembler ends
6791 up looking a bit weird if it turns out that there is
6792 no offset. You end up producing code that looks like:
6805 So here we provide the missing zero. */
6807 *displacement_string_end
= '0';
6810 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
6811 if (gotfree_input_line
)
6812 input_line_pointer
= gotfree_input_line
;
6814 exp_seg
= expression (exp
);
6817 if (*input_line_pointer
)
6818 as_bad (_("junk `%s' after expression"), input_line_pointer
);
6820 RESTORE_END_STRING (disp_end
+ 1);
6822 input_line_pointer
= save_input_line_pointer
;
6823 if (gotfree_input_line
)
6824 free (gotfree_input_line
);
6827 /* We do this to make sure that the section symbol is in
6828 the symbol table. We will ultimately change the relocation
6829 to be relative to the beginning of the section. */
6830 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
6831 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
6832 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
6834 if (exp
->X_op
!= O_symbol
)
6837 if (S_IS_LOCAL (exp
->X_add_symbol
)
6838 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
)
6839 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
6840 exp
->X_op
= O_subtract
;
6841 exp
->X_op_symbol
= GOT_symbol
;
6842 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
6843 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
6844 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
6845 i
.reloc
[this_operand
] = BFD_RELOC_64
;
6847 i
.reloc
[this_operand
] = BFD_RELOC_32
;
6850 else if (exp
->X_op
== O_absent
6851 || exp
->X_op
== O_illegal
6852 || exp
->X_op
== O_big
6853 || (gotfree_input_line
6854 && (exp
->X_op
== O_constant
6855 || exp
->X_op
== O_register
)))
6858 as_bad (_("missing or invalid displacement expression `%s'"),
6863 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
6864 else if (exp
->X_op
!= O_constant
6865 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
6866 && exp_seg
!= absolute_section
6867 && exp_seg
!= text_section
6868 && exp_seg
!= data_section
6869 && exp_seg
!= bss_section
6870 && exp_seg
!= undefined_section
6871 && !bfd_is_com_section (exp_seg
))
6873 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
6878 RESTORE_END_STRING (disp_end
);
6880 /* Check if this is a displacement only operand. */
6881 bigdisp
= i
.types
[this_operand
];
6882 bigdisp
.bitfield
.disp8
= 0;
6883 bigdisp
.bitfield
.disp16
= 0;
6884 bigdisp
.bitfield
.disp32
= 0;
6885 bigdisp
.bitfield
.disp32s
= 0;
6886 bigdisp
.bitfield
.disp64
= 0;
6887 if (operand_type_all_zero (&bigdisp
))
6888 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
6894 /* Make sure the memory operand we've been dealt is valid.
6895 Return 1 on success, 0 on a failure. */
6898 i386_index_check (const char *operand_string
)
6901 const char *kind
= "base/index";
6902 #if INFER_ADDR_PREFIX
6908 if (current_templates
->start
->opcode_modifier
.isstring
6909 && !current_templates
->start
->opcode_modifier
.immext
6910 && (current_templates
->end
[-1].opcode_modifier
.isstring
6913 /* Memory operands of string insns are special in that they only allow
6914 a single register (rDI, rSI, or rBX) as their memory address. */
6915 unsigned int expected
;
6917 kind
= "string address";
6919 if (current_templates
->start
->opcode_modifier
.w
)
6921 i386_operand_type type
= current_templates
->end
[-1].operand_types
[0];
6923 if (!type
.bitfield
.baseindex
6924 || ((!i
.mem_operands
!= !intel_syntax
)
6925 && current_templates
->end
[-1].operand_types
[1]
6926 .bitfield
.baseindex
))
6927 type
= current_templates
->end
[-1].operand_types
[1];
6928 expected
= type
.bitfield
.esseg
? 7 /* rDI */ : 6 /* rSI */;
6931 expected
= 3 /* rBX */;
6933 if (!i
.base_reg
|| i
.index_reg
6934 || operand_type_check (i
.types
[this_operand
], disp
))
6936 else if (!(flag_code
== CODE_64BIT
6937 ? i
.prefix
[ADDR_PREFIX
]
6938 ? i
.base_reg
->reg_type
.bitfield
.reg32
6939 : i
.base_reg
->reg_type
.bitfield
.reg64
6940 : (flag_code
== CODE_16BIT
) ^ !i
.prefix
[ADDR_PREFIX
]
6941 ? i
.base_reg
->reg_type
.bitfield
.reg32
6942 : i
.base_reg
->reg_type
.bitfield
.reg16
))
6944 else if (i
.base_reg
->reg_num
!= expected
)
6951 for (j
= 0; j
< i386_regtab_size
; ++j
)
6952 if ((flag_code
== CODE_64BIT
6953 ? i
.prefix
[ADDR_PREFIX
]
6954 ? i386_regtab
[j
].reg_type
.bitfield
.reg32
6955 : i386_regtab
[j
].reg_type
.bitfield
.reg64
6956 : (flag_code
== CODE_16BIT
) ^ !i
.prefix
[ADDR_PREFIX
]
6957 ? i386_regtab
[j
].reg_type
.bitfield
.reg32
6958 : i386_regtab
[j
].reg_type
.bitfield
.reg16
)
6959 && i386_regtab
[j
].reg_num
== expected
)
6961 assert (j
< i386_regtab_size
);
6962 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
6964 intel_syntax
? '[' : '(',
6966 i386_regtab
[j
].reg_name
,
6967 intel_syntax
? ']' : ')');
6971 else if (flag_code
== CODE_64BIT
)
6974 && ((i
.prefix
[ADDR_PREFIX
] == 0
6975 && !i
.base_reg
->reg_type
.bitfield
.reg64
)
6976 || (i
.prefix
[ADDR_PREFIX
]
6977 && !i
.base_reg
->reg_type
.bitfield
.reg32
))
6979 || i
.base_reg
->reg_num
!=
6980 (i
.prefix
[ADDR_PREFIX
] == 0 ? RegRip
: RegEip
)))
6982 && (!i
.index_reg
->reg_type
.bitfield
.baseindex
6983 || (i
.prefix
[ADDR_PREFIX
] == 0
6984 && i
.index_reg
->reg_num
!= RegRiz
6985 && !i
.index_reg
->reg_type
.bitfield
.reg64
6987 || (i
.prefix
[ADDR_PREFIX
]
6988 && i
.index_reg
->reg_num
!= RegEiz
6989 && !i
.index_reg
->reg_type
.bitfield
.reg32
))))
6994 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[ADDR_PREFIX
] != 0))
6998 && (!i
.base_reg
->reg_type
.bitfield
.reg16
6999 || !i
.base_reg
->reg_type
.bitfield
.baseindex
))
7001 && (!i
.index_reg
->reg_type
.bitfield
.reg16
7002 || !i
.index_reg
->reg_type
.bitfield
.baseindex
7004 && i
.base_reg
->reg_num
< 6
7005 && i
.index_reg
->reg_num
>= 6
7006 && i
.log2_scale_factor
== 0))))
7013 && !i
.base_reg
->reg_type
.bitfield
.reg32
)
7015 && ((!i
.index_reg
->reg_type
.bitfield
.reg32
7016 && i
.index_reg
->reg_num
!= RegEiz
)
7017 || !i
.index_reg
->reg_type
.bitfield
.baseindex
)))
7023 #if INFER_ADDR_PREFIX
7024 if (!i
.mem_operands
&& !i
.prefix
[ADDR_PREFIX
])
7026 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
7028 /* Change the size of any displacement too. At most one of
7029 Disp16 or Disp32 is set.
7030 FIXME. There doesn't seem to be any real need for separate
7031 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
7032 Removing them would probably clean up the code quite a lot. */
7033 if (flag_code
!= CODE_64BIT
7034 && (i
.types
[this_operand
].bitfield
.disp16
7035 || i
.types
[this_operand
].bitfield
.disp32
))
7036 i
.types
[this_operand
]
7037 = operand_type_xor (i
.types
[this_operand
], disp16_32
);
7042 as_bad (_("`%s' is not a valid %s expression"),
7047 as_bad (_("`%s' is not a valid %s-bit %s expression"),
7049 flag_code_names
[i
.prefix
[ADDR_PREFIX
]
7050 ? flag_code
== CODE_32BIT
7059 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
7063 i386_att_operand (char *operand_string
)
7067 char *op_string
= operand_string
;
7069 if (is_space_char (*op_string
))
7072 /* We check for an absolute prefix (differentiating,
7073 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
7074 if (*op_string
== ABSOLUTE_PREFIX
)
7077 if (is_space_char (*op_string
))
7079 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
7082 /* Check if operand is a register. */
7083 if ((r
= parse_register (op_string
, &end_op
)) != NULL
)
7085 i386_operand_type temp
;
7087 /* Check for a segment override by searching for ':' after a
7088 segment register. */
7090 if (is_space_char (*op_string
))
7092 if (*op_string
== ':'
7093 && (r
->reg_type
.bitfield
.sreg2
7094 || r
->reg_type
.bitfield
.sreg3
))
7099 i
.seg
[i
.mem_operands
] = &es
;
7102 i
.seg
[i
.mem_operands
] = &cs
;
7105 i
.seg
[i
.mem_operands
] = &ss
;
7108 i
.seg
[i
.mem_operands
] = &ds
;
7111 i
.seg
[i
.mem_operands
] = &fs
;
7114 i
.seg
[i
.mem_operands
] = &gs
;
7118 /* Skip the ':' and whitespace. */
7120 if (is_space_char (*op_string
))
7123 if (!is_digit_char (*op_string
)
7124 && !is_identifier_char (*op_string
)
7125 && *op_string
!= '('
7126 && *op_string
!= ABSOLUTE_PREFIX
)
7128 as_bad (_("bad memory operand `%s'"), op_string
);
7131 /* Handle case of %es:*foo. */
7132 if (*op_string
== ABSOLUTE_PREFIX
)
7135 if (is_space_char (*op_string
))
7137 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
7139 goto do_memory_reference
;
7143 as_bad (_("junk `%s' after register"), op_string
);
7147 temp
.bitfield
.baseindex
= 0;
7148 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
7150 i
.types
[this_operand
].bitfield
.unspecified
= 0;
7151 i
.op
[this_operand
].regs
= r
;
7154 else if (*op_string
== REGISTER_PREFIX
)
7156 as_bad (_("bad register name `%s'"), op_string
);
7159 else if (*op_string
== IMMEDIATE_PREFIX
)
7162 if (i
.types
[this_operand
].bitfield
.jumpabsolute
)
7164 as_bad (_("immediate operand illegal with absolute jump"));
7167 if (!i386_immediate (op_string
))
7170 else if (is_digit_char (*op_string
)
7171 || is_identifier_char (*op_string
)
7172 || *op_string
== '(')
7174 /* This is a memory reference of some sort. */
7177 /* Start and end of displacement string expression (if found). */
7178 char *displacement_string_start
;
7179 char *displacement_string_end
;
7181 do_memory_reference
:
7182 if ((i
.mem_operands
== 1
7183 && !current_templates
->start
->opcode_modifier
.isstring
)
7184 || i
.mem_operands
== 2)
7186 as_bad (_("too many memory references for `%s'"),
7187 current_templates
->start
->name
);
7191 /* Check for base index form. We detect the base index form by
7192 looking for an ')' at the end of the operand, searching
7193 for the '(' matching it, and finding a REGISTER_PREFIX or ','
7195 base_string
= op_string
+ strlen (op_string
);
7198 if (is_space_char (*base_string
))
7201 /* If we only have a displacement, set-up for it to be parsed later. */
7202 displacement_string_start
= op_string
;
7203 displacement_string_end
= base_string
+ 1;
7205 if (*base_string
== ')')
7208 unsigned int parens_balanced
= 1;
7209 /* We've already checked that the number of left & right ()'s are
7210 equal, so this loop will not be infinite. */
7214 if (*base_string
== ')')
7216 if (*base_string
== '(')
7219 while (parens_balanced
);
7221 temp_string
= base_string
;
7223 /* Skip past '(' and whitespace. */
7225 if (is_space_char (*base_string
))
7228 if (*base_string
== ','
7229 || ((i
.base_reg
= parse_register (base_string
, &end_op
))
7232 displacement_string_end
= temp_string
;
7234 i
.types
[this_operand
].bitfield
.baseindex
= 1;
7238 base_string
= end_op
;
7239 if (is_space_char (*base_string
))
7243 /* There may be an index reg or scale factor here. */
7244 if (*base_string
== ',')
7247 if (is_space_char (*base_string
))
7250 if ((i
.index_reg
= parse_register (base_string
, &end_op
))
7253 base_string
= end_op
;
7254 if (is_space_char (*base_string
))
7256 if (*base_string
== ',')
7259 if (is_space_char (*base_string
))
7262 else if (*base_string
!= ')')
7264 as_bad (_("expecting `,' or `)' "
7265 "after index register in `%s'"),
7270 else if (*base_string
== REGISTER_PREFIX
)
7272 as_bad (_("bad register name `%s'"), base_string
);
7276 /* Check for scale factor. */
7277 if (*base_string
!= ')')
7279 char *end_scale
= i386_scale (base_string
);
7284 base_string
= end_scale
;
7285 if (is_space_char (*base_string
))
7287 if (*base_string
!= ')')
7289 as_bad (_("expecting `)' "
7290 "after scale factor in `%s'"),
7295 else if (!i
.index_reg
)
7297 as_bad (_("expecting index register or scale factor "
7298 "after `,'; got '%c'"),
7303 else if (*base_string
!= ')')
7305 as_bad (_("expecting `,' or `)' "
7306 "after base register in `%s'"),
7311 else if (*base_string
== REGISTER_PREFIX
)
7313 as_bad (_("bad register name `%s'"), base_string
);
7318 /* If there's an expression beginning the operand, parse it,
7319 assuming displacement_string_start and
7320 displacement_string_end are meaningful. */
7321 if (displacement_string_start
!= displacement_string_end
)
7323 if (!i386_displacement (displacement_string_start
,
7324 displacement_string_end
))
7328 /* Special case for (%dx) while doing input/output op. */
7330 && operand_type_equal (&i
.base_reg
->reg_type
,
7331 ®16_inoutportreg
)
7333 && i
.log2_scale_factor
== 0
7334 && i
.seg
[i
.mem_operands
] == 0
7335 && !operand_type_check (i
.types
[this_operand
], disp
))
7337 i
.types
[this_operand
] = inoutportreg
;
7341 if (i386_index_check (operand_string
) == 0)
7343 i
.types
[this_operand
].bitfield
.mem
= 1;
7348 /* It's not a memory operand; argh! */
7349 as_bad (_("invalid char %s beginning operand %d `%s'"),
7350 output_invalid (*op_string
),
7355 return 1; /* Normal return. */
7358 /* md_estimate_size_before_relax()
7360 Called just before relax() for rs_machine_dependent frags. The x86
7361 assembler uses these frags to handle variable size jump
7364 Any symbol that is now undefined will not become defined.
7365 Return the correct fr_subtype in the frag.
7366 Return the initial "guess for variable size of frag" to caller.
7367 The guess is actually the growth beyond the fixed part. Whatever
7368 we do to grow the fixed or variable part contributes to our
7372 md_estimate_size_before_relax (fragP
, segment
)
7376 /* We've already got fragP->fr_subtype right; all we have to do is
7377 check for un-relaxable symbols. On an ELF system, we can't relax
7378 an externally visible symbol, because it may be overridden by a
7380 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
7381 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7383 && (S_IS_EXTERNAL (fragP
->fr_symbol
)
7384 || S_IS_WEAK (fragP
->fr_symbol
)))
7388 /* Symbol is undefined in this segment, or we need to keep a
7389 reloc so that weak symbols can be overridden. */
7390 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
7391 enum bfd_reloc_code_real reloc_type
;
7392 unsigned char *opcode
;
7395 if (fragP
->fr_var
!= NO_RELOC
)
7396 reloc_type
= fragP
->fr_var
;
7398 reloc_type
= BFD_RELOC_16_PCREL
;
7400 reloc_type
= BFD_RELOC_32_PCREL
;
7402 old_fr_fix
= fragP
->fr_fix
;
7403 opcode
= (unsigned char *) fragP
->fr_opcode
;
7405 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
7408 /* Make jmp (0xeb) a (d)word displacement jump. */
7410 fragP
->fr_fix
+= size
;
7411 fix_new (fragP
, old_fr_fix
, size
,
7413 fragP
->fr_offset
, 1,
7419 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
7421 /* Negate the condition, and branch past an
7422 unconditional jump. */
7425 /* Insert an unconditional jump. */
7427 /* We added two extra opcode bytes, and have a two byte
7429 fragP
->fr_fix
+= 2 + 2;
7430 fix_new (fragP
, old_fr_fix
+ 2, 2,
7432 fragP
->fr_offset
, 1,
7439 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
7444 fixP
= fix_new (fragP
, old_fr_fix
, 1,
7446 fragP
->fr_offset
, 1,
7448 fixP
->fx_signed
= 1;
7452 /* This changes the byte-displacement jump 0x7N
7453 to the (d)word-displacement jump 0x0f,0x8N. */
7454 opcode
[1] = opcode
[0] + 0x10;
7455 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
7456 /* We've added an opcode byte. */
7457 fragP
->fr_fix
+= 1 + size
;
7458 fix_new (fragP
, old_fr_fix
+ 1, size
,
7460 fragP
->fr_offset
, 1,
7465 BAD_CASE (fragP
->fr_subtype
);
7469 return fragP
->fr_fix
- old_fr_fix
;
7472 /* Guess size depending on current relax state. Initially the relax
7473 state will correspond to a short jump and we return 1, because
7474 the variable part of the frag (the branch offset) is one byte
7475 long. However, we can relax a section more than once and in that
7476 case we must either set fr_subtype back to the unrelaxed state,
7477 or return the value for the appropriate branch. */
7478 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
7481 /* Called after relax() is finished.
7483 In: Address of frag.
7484 fr_type == rs_machine_dependent.
7485 fr_subtype is what the address relaxed to.
7487 Out: Any fixSs and constants are set up.
7488 Caller will turn frag into a ".space 0". */
7491 md_convert_frag (abfd
, sec
, fragP
)
7492 bfd
*abfd ATTRIBUTE_UNUSED
;
7493 segT sec ATTRIBUTE_UNUSED
;
7496 unsigned char *opcode
;
7497 unsigned char *where_to_put_displacement
= NULL
;
7498 offsetT target_address
;
7499 offsetT opcode_address
;
7500 unsigned int extension
= 0;
7501 offsetT displacement_from_opcode_start
;
7503 opcode
= (unsigned char *) fragP
->fr_opcode
;
7505 /* Address we want to reach in file space. */
7506 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
7508 /* Address opcode resides at in file space. */
7509 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
7511 /* Displacement from opcode start to fill into instruction. */
7512 displacement_from_opcode_start
= target_address
- opcode_address
;
7514 if ((fragP
->fr_subtype
& BIG
) == 0)
7516 /* Don't have to change opcode. */
7517 extension
= 1; /* 1 opcode + 1 displacement */
7518 where_to_put_displacement
= &opcode
[1];
7522 if (no_cond_jump_promotion
7523 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
7524 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
7525 _("long jump required"));
7527 switch (fragP
->fr_subtype
)
7529 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
7530 extension
= 4; /* 1 opcode + 4 displacement */
7532 where_to_put_displacement
= &opcode
[1];
7535 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
7536 extension
= 2; /* 1 opcode + 2 displacement */
7538 where_to_put_displacement
= &opcode
[1];
7541 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
7542 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
7543 extension
= 5; /* 2 opcode + 4 displacement */
7544 opcode
[1] = opcode
[0] + 0x10;
7545 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
7546 where_to_put_displacement
= &opcode
[2];
7549 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
7550 extension
= 3; /* 2 opcode + 2 displacement */
7551 opcode
[1] = opcode
[0] + 0x10;
7552 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
7553 where_to_put_displacement
= &opcode
[2];
7556 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
7561 where_to_put_displacement
= &opcode
[3];
7565 BAD_CASE (fragP
->fr_subtype
);
7570 /* If size if less then four we are sure that the operand fits,
7571 but if it's 4, then it could be that the displacement is larger
7573 if (DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
) == 4
7575 && ((addressT
) (displacement_from_opcode_start
- extension
7576 + ((addressT
) 1 << 31))
7577 > (((addressT
) 2 << 31) - 1)))
7579 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
7580 _("jump target out of range"));
7581 /* Make us emit 0. */
7582 displacement_from_opcode_start
= extension
;
7584 /* Now put displacement after opcode. */
7585 md_number_to_chars ((char *) where_to_put_displacement
,
7586 (valueT
) (displacement_from_opcode_start
- extension
),
7587 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
7588 fragP
->fr_fix
+= extension
;
7591 /* Apply a fixup (fixS) to segment data, once it has been determined
7592 by our caller that we have all the info we need to fix it up.
7594 On the 386, immediates, displacements, and data pointers are all in
7595 the same (little-endian) format, so we don't need to care about which
7599 md_apply_fix (fixP
, valP
, seg
)
7600 /* The fix we're to put in. */
7602 /* Pointer to the value of the bits. */
7604 /* Segment fix is from. */
7605 segT seg ATTRIBUTE_UNUSED
;
7607 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
7608 valueT value
= *valP
;
7610 #if !defined (TE_Mach)
7613 switch (fixP
->fx_r_type
)
7619 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
7622 case BFD_RELOC_X86_64_32S
:
7623 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
7626 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
7629 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
7634 if (fixP
->fx_addsy
!= NULL
7635 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
7636 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
7637 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
7638 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
7639 && !use_rela_relocations
)
7641 /* This is a hack. There should be a better way to handle this.
7642 This covers for the fact that bfd_install_relocation will
7643 subtract the current location (for partial_inplace, PC relative
7644 relocations); see more below. */
7648 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
7651 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
7653 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7656 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
7659 || (symbol_section_p (fixP
->fx_addsy
)
7660 && sym_seg
!= absolute_section
))
7661 && !generic_force_reloc (fixP
))
7663 /* Yes, we add the values in twice. This is because
7664 bfd_install_relocation subtracts them out again. I think
7665 bfd_install_relocation is broken, but I don't dare change
7667 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
7671 #if defined (OBJ_COFF) && defined (TE_PE)
7672 /* For some reason, the PE format does not store a
7673 section address offset for a PC relative symbol. */
7674 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
7675 || S_IS_WEAK (fixP
->fx_addsy
))
7676 value
+= md_pcrel_from (fixP
);
7680 /* Fix a few things - the dynamic linker expects certain values here,
7681 and we must not disappoint it. */
7682 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7683 if (IS_ELF
&& fixP
->fx_addsy
)
7684 switch (fixP
->fx_r_type
)
7686 case BFD_RELOC_386_PLT32
:
7687 case BFD_RELOC_X86_64_PLT32
:
7688 /* Make the jump instruction point to the address of the operand. At
7689 runtime we merely add the offset to the actual PLT entry. */
7693 case BFD_RELOC_386_TLS_GD
:
7694 case BFD_RELOC_386_TLS_LDM
:
7695 case BFD_RELOC_386_TLS_IE_32
:
7696 case BFD_RELOC_386_TLS_IE
:
7697 case BFD_RELOC_386_TLS_GOTIE
:
7698 case BFD_RELOC_386_TLS_GOTDESC
:
7699 case BFD_RELOC_X86_64_TLSGD
:
7700 case BFD_RELOC_X86_64_TLSLD
:
7701 case BFD_RELOC_X86_64_GOTTPOFF
:
7702 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
7703 value
= 0; /* Fully resolved at runtime. No addend. */
7705 case BFD_RELOC_386_TLS_LE
:
7706 case BFD_RELOC_386_TLS_LDO_32
:
7707 case BFD_RELOC_386_TLS_LE_32
:
7708 case BFD_RELOC_X86_64_DTPOFF32
:
7709 case BFD_RELOC_X86_64_DTPOFF64
:
7710 case BFD_RELOC_X86_64_TPOFF32
:
7711 case BFD_RELOC_X86_64_TPOFF64
:
7712 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
7715 case BFD_RELOC_386_TLS_DESC_CALL
:
7716 case BFD_RELOC_X86_64_TLSDESC_CALL
:
7717 value
= 0; /* Fully resolved at runtime. No addend. */
7718 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
7722 case BFD_RELOC_386_GOT32
:
7723 case BFD_RELOC_X86_64_GOT32
:
7724 value
= 0; /* Fully resolved at runtime. No addend. */
7727 case BFD_RELOC_VTABLE_INHERIT
:
7728 case BFD_RELOC_VTABLE_ENTRY
:
7735 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
7737 #endif /* !defined (TE_Mach) */
7739 /* Are we finished with this relocation now? */
7740 if (fixP
->fx_addsy
== NULL
)
7742 else if (use_rela_relocations
)
7744 fixP
->fx_no_overflow
= 1;
7745 /* Remember value for tc_gen_reloc. */
7746 fixP
->fx_addnumber
= value
;
7750 md_number_to_chars (p
, value
, fixP
->fx_size
);
7754 md_atof (int type
, char *litP
, int *sizeP
)
7756 /* This outputs the LITTLENUMs in REVERSE order;
7757 in accord with the bigendian 386. */
7758 return ieee_md_atof (type
, litP
, sizeP
, FALSE
);
7761 static char output_invalid_buf
[sizeof (unsigned char) * 2 + 6];
7764 output_invalid (int c
)
7767 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
7770 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
7771 "(0x%x)", (unsigned char) c
);
7772 return output_invalid_buf
;
7775 /* REG_STRING starts *before* REGISTER_PREFIX. */
7777 static const reg_entry
*
7778 parse_real_register (char *reg_string
, char **end_op
)
7780 char *s
= reg_string
;
7782 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
7785 /* Skip possible REGISTER_PREFIX and possible whitespace. */
7786 if (*s
== REGISTER_PREFIX
)
7789 if (is_space_char (*s
))
7793 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
7795 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
7796 return (const reg_entry
*) NULL
;
7800 /* For naked regs, make sure that we are not dealing with an identifier.
7801 This prevents confusing an identifier like `eax_var' with register
7803 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
7804 return (const reg_entry
*) NULL
;
7808 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
7810 /* Handle floating point regs, allowing spaces in the (i) part. */
7811 if (r
== i386_regtab
/* %st is first entry of table */)
7813 if (is_space_char (*s
))
7818 if (is_space_char (*s
))
7820 if (*s
>= '0' && *s
<= '7')
7824 if (is_space_char (*s
))
7829 r
= hash_find (reg_hash
, "st(0)");
7834 /* We have "%st(" then garbage. */
7835 return (const reg_entry
*) NULL
;
7839 if (r
== NULL
|| allow_pseudo_reg
)
7842 if (operand_type_all_zero (&r
->reg_type
))
7843 return (const reg_entry
*) NULL
;
7845 if ((r
->reg_type
.bitfield
.reg32
7846 || r
->reg_type
.bitfield
.sreg3
7847 || r
->reg_type
.bitfield
.control
7848 || r
->reg_type
.bitfield
.debug
7849 || r
->reg_type
.bitfield
.test
)
7850 && !cpu_arch_flags
.bitfield
.cpui386
)
7851 return (const reg_entry
*) NULL
;
7853 if (r
->reg_type
.bitfield
.regmmx
&& !cpu_arch_flags
.bitfield
.cpummx
)
7854 return (const reg_entry
*) NULL
;
7856 if (r
->reg_type
.bitfield
.regxmm
&& !cpu_arch_flags
.bitfield
.cpusse
)
7857 return (const reg_entry
*) NULL
;
7859 if (r
->reg_type
.bitfield
.regymm
&& !cpu_arch_flags
.bitfield
.cpuavx
)
7860 return (const reg_entry
*) NULL
;
7862 /* Don't allow fake index register unless allow_index_reg isn't 0. */
7863 if (!allow_index_reg
7864 && (r
->reg_num
== RegEiz
|| r
->reg_num
== RegRiz
))
7865 return (const reg_entry
*) NULL
;
7867 if (((r
->reg_flags
& (RegRex64
| RegRex
))
7868 || r
->reg_type
.bitfield
.reg64
)
7869 && (!cpu_arch_flags
.bitfield
.cpulm
7870 || !operand_type_equal (&r
->reg_type
, &control
))
7871 && flag_code
!= CODE_64BIT
)
7872 return (const reg_entry
*) NULL
;
7874 if (r
->reg_type
.bitfield
.sreg3
&& r
->reg_num
== RegFlat
&& !intel_syntax
)
7875 return (const reg_entry
*) NULL
;
7880 /* REG_STRING starts *before* REGISTER_PREFIX. */
7882 static const reg_entry
*
7883 parse_register (char *reg_string
, char **end_op
)
7887 if (*reg_string
== REGISTER_PREFIX
|| allow_naked_reg
)
7888 r
= parse_real_register (reg_string
, end_op
);
7893 char *save
= input_line_pointer
;
7897 input_line_pointer
= reg_string
;
7898 c
= get_symbol_end ();
7899 symbolP
= symbol_find (reg_string
);
7900 if (symbolP
&& S_GET_SEGMENT (symbolP
) == reg_section
)
7902 const expressionS
*e
= symbol_get_value_expression (symbolP
);
7904 know (e
->X_op
== O_register
);
7905 know (e
->X_add_number
>= 0
7906 && (valueT
) e
->X_add_number
< i386_regtab_size
);
7907 r
= i386_regtab
+ e
->X_add_number
;
7908 *end_op
= input_line_pointer
;
7910 *input_line_pointer
= c
;
7911 input_line_pointer
= save
;
7917 i386_parse_name (char *name
, expressionS
*e
, char *nextcharP
)
7920 char *end
= input_line_pointer
;
7923 r
= parse_register (name
, &input_line_pointer
);
7924 if (r
&& end
<= input_line_pointer
)
7926 *nextcharP
= *input_line_pointer
;
7927 *input_line_pointer
= 0;
7928 e
->X_op
= O_register
;
7929 e
->X_add_number
= r
- i386_regtab
;
7932 input_line_pointer
= end
;
7938 md_operand (expressionS
*e
)
7940 if (*input_line_pointer
== REGISTER_PREFIX
)
7943 const reg_entry
*r
= parse_real_register (input_line_pointer
, &end
);
7947 e
->X_op
= O_register
;
7948 e
->X_add_number
= r
- i386_regtab
;
7949 input_line_pointer
= end
;
7955 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7956 const char *md_shortopts
= "kVQ:sqn";
7958 const char *md_shortopts
= "qn";
7961 #define OPTION_32 (OPTION_MD_BASE + 0)
7962 #define OPTION_64 (OPTION_MD_BASE + 1)
7963 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
7964 #define OPTION_MARCH (OPTION_MD_BASE + 3)
7965 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
7966 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
7967 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
7968 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
7969 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
7970 #define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
7971 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
7972 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
7974 struct option md_longopts
[] =
7976 {"32", no_argument
, NULL
, OPTION_32
},
7977 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
7978 {"64", no_argument
, NULL
, OPTION_64
},
7980 {"divide", no_argument
, NULL
, OPTION_DIVIDE
},
7981 {"march", required_argument
, NULL
, OPTION_MARCH
},
7982 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
7983 {"mmnemonic", required_argument
, NULL
, OPTION_MMNEMONIC
},
7984 {"msyntax", required_argument
, NULL
, OPTION_MSYNTAX
},
7985 {"mindex-reg", no_argument
, NULL
, OPTION_MINDEX_REG
},
7986 {"mnaked-reg", no_argument
, NULL
, OPTION_MNAKED_REG
},
7987 {"mold-gcc", no_argument
, NULL
, OPTION_MOLD_GCC
},
7988 {"msse2avx", no_argument
, NULL
, OPTION_MSSE2AVX
},
7989 {"msse-check", required_argument
, NULL
, OPTION_MSSE_CHECK
},
7990 {NULL
, no_argument
, NULL
, 0}
7992 size_t md_longopts_size
= sizeof (md_longopts
);
7995 md_parse_option (int c
, char *arg
)
8003 optimize_align_code
= 0;
8010 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8011 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
8012 should be emitted or not. FIXME: Not implemented. */
8016 /* -V: SVR4 argument to print version ID. */
8018 print_version_id ();
8021 /* -k: Ignore for FreeBSD compatibility. */
8026 /* -s: On i386 Solaris, this tells the native assembler to use
8027 .stab instead of .stab.excl. We always use .stab anyhow. */
8030 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
8033 const char **list
, **l
;
8035 list
= bfd_target_list ();
8036 for (l
= list
; *l
!= NULL
; l
++)
8037 if (CONST_STRNEQ (*l
, "elf64-x86-64")
8038 || strcmp (*l
, "coff-x86-64") == 0
8039 || strcmp (*l
, "pe-x86-64") == 0
8040 || strcmp (*l
, "pei-x86-64") == 0)
8042 default_arch
= "x86_64";
8046 as_fatal (_("No compiled in support for x86_64"));
8053 default_arch
= "i386";
8057 #ifdef SVR4_COMMENT_CHARS
8062 n
= (char *) xmalloc (strlen (i386_comment_chars
) + 1);
8064 for (s
= i386_comment_chars
; *s
!= '\0'; s
++)
8068 i386_comment_chars
= n
;
8074 arch
= xstrdup (arg
);
8078 as_fatal (_("Invalid -march= option: `%s'"), arg
);
8079 next
= strchr (arch
, '+');
8082 for (i
= 0; i
< ARRAY_SIZE (cpu_arch
); i
++)
8084 if (strcmp (arch
, cpu_arch
[i
].name
) == 0)
8087 cpu_arch_name
= cpu_arch
[i
].name
;
8088 cpu_sub_arch_name
= NULL
;
8089 cpu_arch_flags
= cpu_arch
[i
].flags
;
8090 cpu_arch_isa
= cpu_arch
[i
].type
;
8091 cpu_arch_isa_flags
= cpu_arch
[i
].flags
;
8092 if (!cpu_arch_tune_set
)
8094 cpu_arch_tune
= cpu_arch_isa
;
8095 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
8099 else if (*cpu_arch
[i
].name
== '.'
8100 && strcmp (arch
, cpu_arch
[i
].name
+ 1) == 0)
8102 /* ISA entension. */
8103 i386_cpu_flags flags
;
8104 flags
= cpu_flags_or (cpu_arch_flags
,
8106 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
8108 if (cpu_sub_arch_name
)
8110 char *name
= cpu_sub_arch_name
;
8111 cpu_sub_arch_name
= concat (name
,
8113 (const char *) NULL
);
8117 cpu_sub_arch_name
= xstrdup (cpu_arch
[i
].name
);
8118 cpu_arch_flags
= flags
;
8124 if (i
>= ARRAY_SIZE (cpu_arch
))
8125 as_fatal (_("Invalid -march= option: `%s'"), arg
);
8129 while (next
!= NULL
);
8134 as_fatal (_("Invalid -mtune= option: `%s'"), arg
);
8135 for (i
= 0; i
< ARRAY_SIZE (cpu_arch
); i
++)
8137 if (strcmp (arg
, cpu_arch
[i
].name
) == 0)
8139 cpu_arch_tune_set
= 1;
8140 cpu_arch_tune
= cpu_arch
[i
].type
;
8141 cpu_arch_tune_flags
= cpu_arch
[i
].flags
;
8145 if (i
>= ARRAY_SIZE (cpu_arch
))
8146 as_fatal (_("Invalid -mtune= option: `%s'"), arg
);
8149 case OPTION_MMNEMONIC
:
8150 if (strcasecmp (arg
, "att") == 0)
8152 else if (strcasecmp (arg
, "intel") == 0)
8155 as_fatal (_("Invalid -mmnemonic= option: `%s'"), arg
);
8158 case OPTION_MSYNTAX
:
8159 if (strcasecmp (arg
, "att") == 0)
8161 else if (strcasecmp (arg
, "intel") == 0)
8164 as_fatal (_("Invalid -msyntax= option: `%s'"), arg
);
8167 case OPTION_MINDEX_REG
:
8168 allow_index_reg
= 1;
8171 case OPTION_MNAKED_REG
:
8172 allow_naked_reg
= 1;
8175 case OPTION_MOLD_GCC
:
8179 case OPTION_MSSE2AVX
:
8183 case OPTION_MSSE_CHECK
:
8184 if (strcasecmp (arg
, "error") == 0)
8185 sse_check
= sse_check_error
;
8186 else if (strcasecmp (arg
, "warning") == 0)
8187 sse_check
= sse_check_warning
;
8188 else if (strcasecmp (arg
, "none") == 0)
8189 sse_check
= sse_check_none
;
8191 as_fatal (_("Invalid -msse-check= option: `%s'"), arg
);
8201 md_show_usage (stream
)
8204 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8205 fprintf (stream
, _("\
8207 -V print assembler version number\n\
8210 fprintf (stream
, _("\
8211 -n Do not optimize code alignment\n\
8212 -q quieten some warnings\n"));
8213 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8214 fprintf (stream
, _("\
8217 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
8218 fprintf (stream
, _("\
8219 --32/--64 generate 32bit/64bit code\n"));
8221 #ifdef SVR4_COMMENT_CHARS
8222 fprintf (stream
, _("\
8223 --divide do not treat `/' as a comment character\n"));
8225 fprintf (stream
, _("\
8226 --divide ignored\n"));
8228 fprintf (stream
, _("\
8229 -march=CPU[,+EXTENSION...]\n\
8230 generate code for CPU and EXTENSION, CPU is one of:\n\
8231 i8086, i186, i286, i386, i486, pentium, pentiumpro,\n\
8232 pentiumii, pentiumiii, pentium4, prescott, nocona,\n\
8233 core, core2, k6, k6_2, athlon, k8, amdfam10,\n\
8234 generic32, generic64\n\
8235 EXTENSION is combination of:\n\
8236 mmx, sse, sse2, sse3, ssse3, sse4.1, sse4.2, sse4,\n\
8237 avx, vmx, smx, xsave, movbe, ept, aes, pclmul, fma,\n\
8238 3dnow, 3dnowa, sse4a, sse5, svme, abm, padlock\n"));
8239 fprintf (stream
, _("\
8240 -mtune=CPU optimize for CPU, CPU is one of:\n\
8241 i8086, i186, i286, i386, i486, pentium, pentiumpro,\n\
8242 pentiumii, pentiumiii, pentium4, prescott, nocona,\n\
8243 core, core2, k6, k6_2, athlon, k8, amdfam10,\n\
8244 generic32, generic64\n"));
8245 fprintf (stream
, _("\
8246 -msse2avx encode SSE instructions with VEX prefix\n"));
8247 fprintf (stream
, _("\
8248 -msse-check=[none|error|warning]\n\
8249 check SSE instructions\n"));
8250 fprintf (stream
, _("\
8251 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
8252 fprintf (stream
, _("\
8253 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
8254 fprintf (stream
, _("\
8255 -mindex-reg support pseudo index registers\n"));
8256 fprintf (stream
, _("\
8257 -mnaked-reg don't require `%%' prefix for registers\n"));
8258 fprintf (stream
, _("\
8259 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
8262 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
8263 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (TE_PEP))
8265 /* Pick the target format to use. */
8268 i386_target_format (void)
8270 if (!strcmp (default_arch
, "x86_64"))
8272 set_code_flag (CODE_64BIT
);
8273 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
8275 cpu_arch_isa_flags
.bitfield
.cpui186
= 1;
8276 cpu_arch_isa_flags
.bitfield
.cpui286
= 1;
8277 cpu_arch_isa_flags
.bitfield
.cpui386
= 1;
8278 cpu_arch_isa_flags
.bitfield
.cpui486
= 1;
8279 cpu_arch_isa_flags
.bitfield
.cpui586
= 1;
8280 cpu_arch_isa_flags
.bitfield
.cpui686
= 1;
8281 cpu_arch_isa_flags
.bitfield
.cpup4
= 1;
8282 cpu_arch_isa_flags
.bitfield
.cpummx
= 1;
8283 cpu_arch_isa_flags
.bitfield
.cpusse
= 1;
8284 cpu_arch_isa_flags
.bitfield
.cpusse2
= 1;
8286 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
8288 cpu_arch_tune_flags
.bitfield
.cpui186
= 1;
8289 cpu_arch_tune_flags
.bitfield
.cpui286
= 1;
8290 cpu_arch_tune_flags
.bitfield
.cpui386
= 1;
8291 cpu_arch_tune_flags
.bitfield
.cpui486
= 1;
8292 cpu_arch_tune_flags
.bitfield
.cpui586
= 1;
8293 cpu_arch_tune_flags
.bitfield
.cpui686
= 1;
8294 cpu_arch_tune_flags
.bitfield
.cpup4
= 1;
8295 cpu_arch_tune_flags
.bitfield
.cpummx
= 1;
8296 cpu_arch_tune_flags
.bitfield
.cpusse
= 1;
8297 cpu_arch_tune_flags
.bitfield
.cpusse2
= 1;
8300 else if (!strcmp (default_arch
, "i386"))
8302 set_code_flag (CODE_32BIT
);
8303 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
8305 cpu_arch_isa_flags
.bitfield
.cpui186
= 1;
8306 cpu_arch_isa_flags
.bitfield
.cpui286
= 1;
8307 cpu_arch_isa_flags
.bitfield
.cpui386
= 1;
8309 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
8311 cpu_arch_tune_flags
.bitfield
.cpui186
= 1;
8312 cpu_arch_tune_flags
.bitfield
.cpui286
= 1;
8313 cpu_arch_tune_flags
.bitfield
.cpui386
= 1;
8317 as_fatal (_("Unknown architecture"));
8318 switch (OUTPUT_FLAVOR
)
8321 case bfd_target_coff_flavour
:
8322 return flag_code
== CODE_64BIT
? COFF_TARGET_FORMAT
: "pe-i386";
8325 #ifdef OBJ_MAYBE_AOUT
8326 case bfd_target_aout_flavour
:
8327 return AOUT_TARGET_FORMAT
;
8329 #ifdef OBJ_MAYBE_COFF
8330 case bfd_target_coff_flavour
:
8333 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
8334 case bfd_target_elf_flavour
:
8336 if (flag_code
== CODE_64BIT
)
8339 use_rela_relocations
= 1;
8341 return flag_code
== CODE_64BIT
? ELF_TARGET_FORMAT64
: ELF_TARGET_FORMAT
;
8350 #endif /* OBJ_MAYBE_ more than one */
8352 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
8354 i386_elf_emit_arch_note (void)
8356 if (IS_ELF
&& cpu_arch_name
!= NULL
)
8359 asection
*seg
= now_seg
;
8360 subsegT subseg
= now_subseg
;
8361 Elf_Internal_Note i_note
;
8362 Elf_External_Note e_note
;
8363 asection
*note_secp
;
8366 /* Create the .note section. */
8367 note_secp
= subseg_new (".note", 0);
8368 bfd_set_section_flags (stdoutput
,
8370 SEC_HAS_CONTENTS
| SEC_READONLY
);
8372 /* Process the arch string. */
8373 len
= strlen (cpu_arch_name
);
8375 i_note
.namesz
= len
+ 1;
8377 i_note
.type
= NT_ARCH
;
8378 p
= frag_more (sizeof (e_note
.namesz
));
8379 md_number_to_chars (p
, (valueT
) i_note
.namesz
, sizeof (e_note
.namesz
));
8380 p
= frag_more (sizeof (e_note
.descsz
));
8381 md_number_to_chars (p
, (valueT
) i_note
.descsz
, sizeof (e_note
.descsz
));
8382 p
= frag_more (sizeof (e_note
.type
));
8383 md_number_to_chars (p
, (valueT
) i_note
.type
, sizeof (e_note
.type
));
8384 p
= frag_more (len
+ 1);
8385 strcpy (p
, cpu_arch_name
);
8387 frag_align (2, 0, 0);
8389 subseg_set (seg
, subseg
);
8395 md_undefined_symbol (name
)
8398 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
8399 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
8400 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
8401 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
8405 if (symbol_find (name
))
8406 as_bad (_("GOT already in symbol table"));
8407 GOT_symbol
= symbol_new (name
, undefined_section
,
8408 (valueT
) 0, &zero_address_frag
);
8415 /* Round up a section size to the appropriate boundary. */
8418 md_section_align (segment
, size
)
8419 segT segment ATTRIBUTE_UNUSED
;
8422 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8423 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
8425 /* For a.out, force the section size to be aligned. If we don't do
8426 this, BFD will align it for us, but it will not write out the
8427 final bytes of the section. This may be a bug in BFD, but it is
8428 easier to fix it here since that is how the other a.out targets
8432 align
= bfd_get_section_alignment (stdoutput
, segment
);
8433 size
= ((size
+ (1 << align
) - 1) & ((valueT
) -1 << align
));
8440 /* On the i386, PC-relative offsets are relative to the start of the
8441 next instruction. That is, the address of the offset, plus its
8442 size, since the offset is always the last part of the insn. */
8445 md_pcrel_from (fixS
*fixP
)
8447 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
8453 s_bss (int ignore ATTRIBUTE_UNUSED
)
8457 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8459 obj_elf_section_change_hook ();
8461 temp
= get_absolute_expression ();
8462 subseg_set (bss_section
, (subsegT
) temp
);
8463 demand_empty_rest_of_line ();
8469 i386_validate_fix (fixS
*fixp
)
8471 if (fixp
->fx_subsy
&& fixp
->fx_subsy
== GOT_symbol
)
8473 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
8477 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
8482 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
8484 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
8491 tc_gen_reloc (section
, fixp
)
8492 asection
*section ATTRIBUTE_UNUSED
;
8496 bfd_reloc_code_real_type code
;
8498 switch (fixp
->fx_r_type
)
8500 case BFD_RELOC_X86_64_PLT32
:
8501 case BFD_RELOC_X86_64_GOT32
:
8502 case BFD_RELOC_X86_64_GOTPCREL
:
8503 case BFD_RELOC_386_PLT32
:
8504 case BFD_RELOC_386_GOT32
:
8505 case BFD_RELOC_386_GOTOFF
:
8506 case BFD_RELOC_386_GOTPC
:
8507 case BFD_RELOC_386_TLS_GD
:
8508 case BFD_RELOC_386_TLS_LDM
:
8509 case BFD_RELOC_386_TLS_LDO_32
:
8510 case BFD_RELOC_386_TLS_IE_32
:
8511 case BFD_RELOC_386_TLS_IE
:
8512 case BFD_RELOC_386_TLS_GOTIE
:
8513 case BFD_RELOC_386_TLS_LE_32
:
8514 case BFD_RELOC_386_TLS_LE
:
8515 case BFD_RELOC_386_TLS_GOTDESC
:
8516 case BFD_RELOC_386_TLS_DESC_CALL
:
8517 case BFD_RELOC_X86_64_TLSGD
:
8518 case BFD_RELOC_X86_64_TLSLD
:
8519 case BFD_RELOC_X86_64_DTPOFF32
:
8520 case BFD_RELOC_X86_64_DTPOFF64
:
8521 case BFD_RELOC_X86_64_GOTTPOFF
:
8522 case BFD_RELOC_X86_64_TPOFF32
:
8523 case BFD_RELOC_X86_64_TPOFF64
:
8524 case BFD_RELOC_X86_64_GOTOFF64
:
8525 case BFD_RELOC_X86_64_GOTPC32
:
8526 case BFD_RELOC_X86_64_GOT64
:
8527 case BFD_RELOC_X86_64_GOTPCREL64
:
8528 case BFD_RELOC_X86_64_GOTPC64
:
8529 case BFD_RELOC_X86_64_GOTPLT64
:
8530 case BFD_RELOC_X86_64_PLTOFF64
:
8531 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
8532 case BFD_RELOC_X86_64_TLSDESC_CALL
:
8534 case BFD_RELOC_VTABLE_ENTRY
:
8535 case BFD_RELOC_VTABLE_INHERIT
:
8537 case BFD_RELOC_32_SECREL
:
8539 code
= fixp
->fx_r_type
;
8541 case BFD_RELOC_X86_64_32S
:
8542 if (!fixp
->fx_pcrel
)
8544 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
8545 code
= fixp
->fx_r_type
;
8551 switch (fixp
->fx_size
)
8554 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
8555 _("can not do %d byte pc-relative relocation"),
8557 code
= BFD_RELOC_32_PCREL
;
8559 case 1: code
= BFD_RELOC_8_PCREL
; break;
8560 case 2: code
= BFD_RELOC_16_PCREL
; break;
8561 case 4: code
= BFD_RELOC_32_PCREL
; break;
8563 case 8: code
= BFD_RELOC_64_PCREL
; break;
8569 switch (fixp
->fx_size
)
8572 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
8573 _("can not do %d byte relocation"),
8575 code
= BFD_RELOC_32
;
8577 case 1: code
= BFD_RELOC_8
; break;
8578 case 2: code
= BFD_RELOC_16
; break;
8579 case 4: code
= BFD_RELOC_32
; break;
8581 case 8: code
= BFD_RELOC_64
; break;
8588 if ((code
== BFD_RELOC_32
8589 || code
== BFD_RELOC_32_PCREL
8590 || code
== BFD_RELOC_X86_64_32S
)
8592 && fixp
->fx_addsy
== GOT_symbol
)
8595 code
= BFD_RELOC_386_GOTPC
;
8597 code
= BFD_RELOC_X86_64_GOTPC32
;
8599 if ((code
== BFD_RELOC_64
|| code
== BFD_RELOC_64_PCREL
)
8601 && fixp
->fx_addsy
== GOT_symbol
)
8603 code
= BFD_RELOC_X86_64_GOTPC64
;
8606 rel
= (arelent
*) xmalloc (sizeof (arelent
));
8607 rel
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
8608 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
8610 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
8612 if (!use_rela_relocations
)
8614 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
8615 vtable entry to be used in the relocation's section offset. */
8616 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
8617 rel
->address
= fixp
->fx_offset
;
8621 /* Use the rela in 64bit mode. */
8624 if (!fixp
->fx_pcrel
)
8625 rel
->addend
= fixp
->fx_offset
;
8629 case BFD_RELOC_X86_64_PLT32
:
8630 case BFD_RELOC_X86_64_GOT32
:
8631 case BFD_RELOC_X86_64_GOTPCREL
:
8632 case BFD_RELOC_X86_64_TLSGD
:
8633 case BFD_RELOC_X86_64_TLSLD
:
8634 case BFD_RELOC_X86_64_GOTTPOFF
:
8635 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
8636 case BFD_RELOC_X86_64_TLSDESC_CALL
:
8637 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
8640 rel
->addend
= (section
->vma
8642 + fixp
->fx_addnumber
8643 + md_pcrel_from (fixp
));
8648 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
8649 if (rel
->howto
== NULL
)
8651 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
8652 _("cannot represent relocation type %s"),
8653 bfd_get_reloc_code_name (code
));
8654 /* Set howto to a garbage value so that we can keep going. */
8655 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
8656 assert (rel
->howto
!= NULL
);
8663 /* Parse operands using Intel syntax. This implements a recursive descent
8664 parser based on the BNF grammar published in Appendix B of the MASM 6.1
8667 FIXME: We do not recognize the full operand grammar defined in the MASM
8668 documentation. In particular, all the structure/union and
8669 high-level macro operands are missing.
8671 Uppercase words are terminals, lower case words are non-terminals.
8672 Objects surrounded by double brackets '[[' ']]' are optional. Vertical
8673 bars '|' denote choices. Most grammar productions are implemented in
8674 functions called 'intel_<production>'.
8676 Initial production is 'expr'.
8682 binOp & | AND | \| | OR | ^ | XOR
8684 byteRegister AL | AH | BL | BH | CL | CH | DL | DH
8686 constant digits [[ radixOverride ]]
8688 dataType BYTE | WORD | DWORD | FWORD | QWORD | TBYTE | OWORD | XMMWORD | YMMWORD
8726 => expr expr cmpOp e04
8729 gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX
8730 | BP | EBP | SP | ESP | DI | EDI | SI | ESI
8732 hexdigit a | b | c | d | e | f
8733 | A | B | C | D | E | F
8739 mulOp * | / | % | MOD | << | SHL | >> | SHR
8743 register specialRegister
8747 segmentRegister CS | DS | ES | FS | GS | SS
8749 specialRegister CR0 | CR2 | CR3 | CR4
8750 | DR0 | DR1 | DR2 | DR3 | DR6 | DR7
8751 | TR3 | TR4 | TR5 | TR6 | TR7
8753 We simplify the grammar in obvious places (e.g., register parsing is
8754 done by calling parse_register) and eliminate immediate left recursion
8755 to implement a recursive-descent parser.
8759 expr' cmpOp e04 expr'
8811 /* Parsing structure for the intel syntax parser. Used to implement the
8812 semantic actions for the operand grammar. */
8813 struct intel_parser_s
8815 char *op_string
; /* The string being parsed. */
8816 int got_a_float
; /* Whether the operand is a float. */
8817 int op_modifier
; /* Operand modifier. */
8818 int is_mem
; /* 1 if operand is memory reference. */
8819 int in_offset
; /* >=1 if parsing operand of offset. */
8820 int in_bracket
; /* >=1 if parsing operand in brackets. */
8821 const reg_entry
*reg
; /* Last register reference found. */
8822 char *disp
; /* Displacement string being built. */
8823 char *next_operand
; /* Resume point when splitting operands. */
8826 static struct intel_parser_s intel_parser
;
8828 /* Token structure for parsing intel syntax. */
8831 int code
; /* Token code. */
8832 const reg_entry
*reg
; /* Register entry for register tokens. */
8833 char *str
; /* String representation. */
8836 static struct intel_token cur_token
, prev_token
;
8838 /* Token codes for the intel parser. Since T_SHORT is already used
8839 by COFF, undefine it first to prevent a warning. */
8857 #define T_YMMWORD 16
8859 /* Prototypes for intel parser functions. */
8860 static int intel_match_token (int);
8861 static void intel_putback_token (void);
8862 static void intel_get_token (void);
8863 static int intel_expr (void);
8864 static int intel_e04 (void);
8865 static int intel_e05 (void);
8866 static int intel_e06 (void);
8867 static int intel_e09 (void);
8868 static int intel_e10 (void);
8869 static int intel_e11 (void);
8872 i386_intel_operand (char *operand_string
, int got_a_float
)
8876 const reg_entry
*final_base
= i
.base_reg
;
8877 const reg_entry
*final_index
= i
.index_reg
;
8879 p
= intel_parser
.op_string
= xstrdup (operand_string
);
8880 intel_parser
.disp
= (char *) xmalloc (strlen (operand_string
) + 1);
8884 /* Initialize token holders. */
8885 cur_token
.code
= prev_token
.code
= T_NIL
;
8886 cur_token
.reg
= prev_token
.reg
= NULL
;
8887 cur_token
.str
= prev_token
.str
= NULL
;
8889 /* Initialize parser structure. */
8890 intel_parser
.got_a_float
= got_a_float
;
8891 intel_parser
.op_modifier
= 0;
8892 intel_parser
.is_mem
= 0;
8893 intel_parser
.in_offset
= 0;
8894 intel_parser
.in_bracket
= 0;
8895 intel_parser
.reg
= NULL
;
8896 intel_parser
.disp
[0] = '\0';
8897 intel_parser
.next_operand
= NULL
;
8902 /* Read the first token and start the parser. */
8904 ret
= intel_expr ();
8909 if (cur_token
.code
!= T_NIL
)
8911 as_bad (_("invalid operand for '%s' ('%s' unexpected)"),
8912 current_templates
->start
->name
, cur_token
.str
);
8915 /* If we found a memory reference, hand it over to i386_displacement
8916 to fill in the rest of the operand fields. */
8917 else if (intel_parser
.is_mem
)
8919 if ((i
.mem_operands
== 1
8920 && !current_templates
->start
->opcode_modifier
.isstring
)
8921 || i
.mem_operands
== 2)
8923 as_bad (_("too many memory references for '%s'"),
8924 current_templates
->start
->name
);
8929 char *s
= intel_parser
.disp
;
8931 if (!quiet_warnings
&& intel_parser
.is_mem
< 0)
8932 /* See the comments in intel_bracket_expr. */
8933 as_warn (_("Treating `%s' as memory reference"), operand_string
);
8935 /* Add the displacement expression. */
8937 ret
= i386_displacement (s
, s
+ strlen (s
));
8940 /* Swap base and index in 16-bit memory operands like
8941 [si+bx]. Since i386_index_check is also used in AT&T
8942 mode we have to do that here. */
8945 && i
.base_reg
->reg_type
.bitfield
.reg16
8946 && i
.index_reg
->reg_type
.bitfield
.reg16
8947 && i
.base_reg
->reg_num
>= 6
8948 && i
.index_reg
->reg_num
< 6)
8950 const reg_entry
*base
= i
.index_reg
;
8952 i
.index_reg
= i
.base_reg
;
8955 ret
= i386_index_check (operand_string
);
8959 i
.types
[this_operand
].bitfield
.mem
= 1;
8965 /* Constant and OFFSET expressions are handled by i386_immediate. */
8966 else if ((intel_parser
.op_modifier
& (1 << T_OFFSET
))
8967 || intel_parser
.reg
== NULL
)
8969 if (i
.mem_operands
< 2 && i
.seg
[i
.mem_operands
])
8971 if (!(intel_parser
.op_modifier
& (1 << T_OFFSET
)))
8972 as_warn (_("Segment override ignored"));
8973 i
.seg
[i
.mem_operands
] = NULL
;
8975 ret
= i386_immediate (intel_parser
.disp
);
8978 if (!final_base
&& !final_index
)
8980 final_base
= i
.base_reg
;
8981 final_index
= i
.index_reg
;
8984 if (intel_parser
.next_operand
&& this_operand
>= MAX_OPERANDS
- 1)
8986 if (!ret
|| !intel_parser
.next_operand
)
8988 intel_parser
.op_string
= intel_parser
.next_operand
;
8989 this_operand
= i
.operands
++;
8990 i
.types
[this_operand
].bitfield
.unspecified
= 1;
8994 free (intel_parser
.disp
);
8996 if (final_base
|| final_index
)
8998 i
.base_reg
= final_base
;
8999 i
.index_reg
= final_index
;
9005 #define NUM_ADDRESS_REGS (!!i.base_reg + !!i.index_reg)
9009 expr' cmpOp e04 expr'
9014 /* XXX Implement the comparison operators. */
9015 return intel_e04 ();
9032 if (nregs
>= 0 && NUM_ADDRESS_REGS
> nregs
)
9033 i
.base_reg
= i386_regtab
+ REGNAM_AL
; /* al is invalid as base */
9035 if (cur_token
.code
== '+')
9037 else if (cur_token
.code
== '-')
9038 nregs
= NUM_ADDRESS_REGS
;
9042 strcat (intel_parser
.disp
, cur_token
.str
);
9043 intel_match_token (cur_token
.code
);
9054 int nregs
= ~NUM_ADDRESS_REGS
;
9061 if (cur_token
.code
== '&'
9062 || cur_token
.code
== '|'
9063 || cur_token
.code
== '^')
9067 str
[0] = cur_token
.code
;
9069 strcat (intel_parser
.disp
, str
);
9074 intel_match_token (cur_token
.code
);
9079 if (nregs
>= 0 && NUM_ADDRESS_REGS
> nregs
)
9080 i
.base_reg
= i386_regtab
+ REGNAM_AL
+ 1; /* cl is invalid as base */
9091 int nregs
= ~NUM_ADDRESS_REGS
;
9098 if (cur_token
.code
== '*'
9099 || cur_token
.code
== '/'
9100 || cur_token
.code
== '%')
9104 str
[0] = cur_token
.code
;
9106 strcat (intel_parser
.disp
, str
);
9108 else if (cur_token
.code
== T_SHL
)
9109 strcat (intel_parser
.disp
, "<<");
9110 else if (cur_token
.code
== T_SHR
)
9111 strcat (intel_parser
.disp
, ">>");
9115 intel_match_token (cur_token
.code
);
9120 if (nregs
>= 0 && NUM_ADDRESS_REGS
> nregs
)
9121 i
.base_reg
= i386_regtab
+ REGNAM_AL
+ 2; /* dl is invalid as base */
9139 int nregs
= ~NUM_ADDRESS_REGS
;
9144 /* Don't consume constants here. */
9145 if (cur_token
.code
== '+' || cur_token
.code
== '-')
9147 /* Need to look one token ahead - if the next token
9148 is a constant, the current token is its sign. */
9151 intel_match_token (cur_token
.code
);
9152 next_code
= cur_token
.code
;
9153 intel_putback_token ();
9154 if (next_code
== T_CONST
)
9158 /* e09 OFFSET e09 */
9159 if (cur_token
.code
== T_OFFSET
)
9162 ++intel_parser
.in_offset
;
9166 else if (cur_token
.code
== T_SHORT
)
9167 intel_parser
.op_modifier
|= 1 << T_SHORT
;
9170 else if (cur_token
.code
== '+')
9171 strcat (intel_parser
.disp
, "+");
9176 else if (cur_token
.code
== '-' || cur_token
.code
== '~')
9182 str
[0] = cur_token
.code
;
9184 strcat (intel_parser
.disp
, str
);
9191 intel_match_token (cur_token
.code
);
9199 /* e09' PTR e10 e09' */
9200 if (cur_token
.code
== T_PTR
)
9204 if (prev_token
.code
== T_BYTE
)
9206 suffix
= BYTE_MNEM_SUFFIX
;
9207 i
.types
[this_operand
].bitfield
.byte
= 1;
9210 else if (prev_token
.code
== T_WORD
)
9212 if ((current_templates
->start
->name
[0] == 'l'
9213 && current_templates
->start
->name
[2] == 's'
9214 && current_templates
->start
->name
[3] == 0)
9215 || current_templates
->start
->base_opcode
== 0x62 /* bound */)
9216 suffix
= BYTE_MNEM_SUFFIX
; /* so it will cause an error */
9217 else if (intel_parser
.got_a_float
== 2) /* "fi..." */
9218 suffix
= SHORT_MNEM_SUFFIX
;
9220 suffix
= WORD_MNEM_SUFFIX
;
9221 i
.types
[this_operand
].bitfield
.word
= 1;
9224 else if (prev_token
.code
== T_DWORD
)
9226 if ((current_templates
->start
->name
[0] == 'l'
9227 && current_templates
->start
->name
[2] == 's'
9228 && current_templates
->start
->name
[3] == 0)
9229 || current_templates
->start
->base_opcode
== 0x62 /* bound */)
9230 suffix
= WORD_MNEM_SUFFIX
;
9231 else if (flag_code
== CODE_16BIT
9232 && (current_templates
->start
->opcode_modifier
.jump
9233 || current_templates
->start
->opcode_modifier
.jumpdword
))
9234 suffix
= LONG_DOUBLE_MNEM_SUFFIX
;
9235 else if (intel_parser
.got_a_float
== 1) /* "f..." */
9236 suffix
= SHORT_MNEM_SUFFIX
;
9238 suffix
= LONG_MNEM_SUFFIX
;
9239 i
.types
[this_operand
].bitfield
.dword
= 1;
9242 else if (prev_token
.code
== T_FWORD
)
9244 if (current_templates
->start
->name
[0] == 'l'
9245 && current_templates
->start
->name
[2] == 's'
9246 && current_templates
->start
->name
[3] == 0)
9247 suffix
= LONG_MNEM_SUFFIX
;
9248 else if (!intel_parser
.got_a_float
)
9250 if (flag_code
== CODE_16BIT
)
9251 add_prefix (DATA_PREFIX_OPCODE
);
9252 suffix
= LONG_DOUBLE_MNEM_SUFFIX
;
9255 suffix
= BYTE_MNEM_SUFFIX
; /* so it will cause an error */
9256 i
.types
[this_operand
].bitfield
.fword
= 1;
9259 else if (prev_token
.code
== T_QWORD
)
9261 if (current_templates
->start
->base_opcode
== 0x62 /* bound */
9262 || intel_parser
.got_a_float
== 1) /* "f..." */
9263 suffix
= LONG_MNEM_SUFFIX
;
9265 suffix
= QWORD_MNEM_SUFFIX
;
9266 i
.types
[this_operand
].bitfield
.qword
= 1;
9269 else if (prev_token
.code
== T_TBYTE
)
9271 if (intel_parser
.got_a_float
== 1)
9272 suffix
= LONG_DOUBLE_MNEM_SUFFIX
;
9274 suffix
= BYTE_MNEM_SUFFIX
; /* so it will cause an error */
9277 else if (prev_token
.code
== T_XMMWORD
)
9279 suffix
= XMMWORD_MNEM_SUFFIX
;
9280 i
.types
[this_operand
].bitfield
.xmmword
= 1;
9283 else if (prev_token
.code
== T_YMMWORD
)
9285 suffix
= YMMWORD_MNEM_SUFFIX
;
9286 i
.types
[this_operand
].bitfield
.ymmword
= 1;
9291 as_bad (_("Unknown operand modifier `%s'"), prev_token
.str
);
9295 i
.types
[this_operand
].bitfield
.unspecified
= 0;
9297 /* Operands for jump/call using 'ptr' notation denote absolute
9299 if (current_templates
->start
->opcode_modifier
.jump
9300 || current_templates
->start
->opcode_modifier
.jumpdword
)
9301 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
9303 if (current_templates
->start
->base_opcode
== 0x8d /* lea */)
9307 else if (i
.suffix
!= suffix
)
9309 as_bad (_("Conflicting operand modifiers"));
9315 /* e09' : e10 e09' */
9316 else if (cur_token
.code
== ':')
9318 if (prev_token
.code
!= T_REG
)
9320 /* While {call,jmp} SSSS:OOOO is MASM syntax only when SSSS is a
9321 segment/group identifier (which we don't have), using comma
9322 as the operand separator there is even less consistent, since
9323 there all branches only have a single operand. */
9324 if (this_operand
!= 0
9325 || intel_parser
.in_offset
9326 || intel_parser
.in_bracket
9327 || (!current_templates
->start
->opcode_modifier
.jump
9328 && !current_templates
->start
->opcode_modifier
.jumpdword
9329 && !current_templates
->start
->opcode_modifier
.jumpintersegment
9330 && !current_templates
->start
->operand_types
[0].bitfield
.jumpabsolute
))
9331 return intel_match_token (T_NIL
);
9332 /* Remember the start of the 2nd operand and terminate 1st
9334 XXX This isn't right, yet (when SSSS:OOOO is right operand of
9335 another expression), but it gets at least the simplest case
9336 (a plain number or symbol on the left side) right. */
9337 intel_parser
.next_operand
= intel_parser
.op_string
;
9338 *--intel_parser
.op_string
= '\0';
9339 return intel_match_token (':');
9347 intel_match_token (cur_token
.code
);
9353 --intel_parser
.in_offset
;
9356 if (NUM_ADDRESS_REGS
> nregs
)
9358 as_bad (_("Invalid operand to `OFFSET'"));
9361 intel_parser
.op_modifier
|= 1 << T_OFFSET
;
9364 if (nregs
>= 0 && NUM_ADDRESS_REGS
> nregs
)
9365 i
.base_reg
= i386_regtab
+ REGNAM_AL
+ 3; /* bl is invalid as base */
9370 intel_bracket_expr (void)
9372 int was_offset
= intel_parser
.op_modifier
& (1 << T_OFFSET
);
9373 const char *start
= intel_parser
.op_string
;
9376 if (i
.op
[this_operand
].regs
)
9377 return intel_match_token (T_NIL
);
9379 intel_match_token ('[');
9381 /* Mark as a memory operand only if it's not already known to be an
9382 offset expression. If it's an offset expression, we need to keep
9384 if (!intel_parser
.in_offset
)
9386 ++intel_parser
.in_bracket
;
9388 /* Operands for jump/call inside brackets denote absolute addresses. */
9389 if (current_templates
->start
->opcode_modifier
.jump
9390 || current_templates
->start
->opcode_modifier
.jumpdword
)
9391 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
9393 /* Unfortunately gas always diverged from MASM in a respect that can't
9394 be easily fixed without risking to break code sequences likely to be
9395 encountered (the testsuite even check for this): MASM doesn't consider
9396 an expression inside brackets unconditionally as a memory reference.
9397 When that is e.g. a constant, an offset expression, or the sum of the
9398 two, this is still taken as a constant load. gas, however, always
9399 treated these as memory references. As a compromise, we'll try to make
9400 offset expressions inside brackets work the MASM way (since that's
9401 less likely to be found in real world code), but make constants alone
9402 continue to work the traditional gas way. In either case, issue a
9404 intel_parser
.op_modifier
&= ~was_offset
;
9407 strcat (intel_parser
.disp
, "[");
9409 /* Add a '+' to the displacement string if necessary. */
9410 if (*intel_parser
.disp
!= '\0'
9411 && *(intel_parser
.disp
+ strlen (intel_parser
.disp
) - 1) != '+')
9412 strcat (intel_parser
.disp
, "+");
9415 && (len
= intel_parser
.op_string
- start
- 1,
9416 intel_match_token (']')))
9418 /* Preserve brackets when the operand is an offset expression. */
9419 if (intel_parser
.in_offset
)
9420 strcat (intel_parser
.disp
, "]");
9423 --intel_parser
.in_bracket
;
9424 if (i
.base_reg
|| i
.index_reg
)
9425 intel_parser
.is_mem
= 1;
9426 if (!intel_parser
.is_mem
)
9428 if (!(intel_parser
.op_modifier
& (1 << T_OFFSET
)))
9429 /* Defer the warning until all of the operand was parsed. */
9430 intel_parser
.is_mem
= -1;
9431 else if (!quiet_warnings
)
9432 as_warn (_("`[%.*s]' taken to mean just `%.*s'"),
9433 len
, start
, len
, start
);
9436 intel_parser
.op_modifier
|= was_offset
;
9453 while (cur_token
.code
== '[')
9455 if (!intel_bracket_expr ())
9481 switch (cur_token
.code
)
9485 intel_match_token ('(');
9486 strcat (intel_parser
.disp
, "(");
9488 if (intel_expr () && intel_match_token (')'))
9490 strcat (intel_parser
.disp
, ")");
9497 return intel_bracket_expr ();
9502 strcat (intel_parser
.disp
, cur_token
.str
);
9503 intel_match_token (cur_token
.code
);
9505 /* Mark as a memory operand only if it's not already known to be an
9506 offset expression. */
9507 if (!intel_parser
.in_offset
)
9508 intel_parser
.is_mem
= 1;
9515 const reg_entry
*reg
= intel_parser
.reg
= cur_token
.reg
;
9517 intel_match_token (T_REG
);
9519 /* Check for segment change. */
9520 if (cur_token
.code
== ':')
9522 if (!reg
->reg_type
.bitfield
.sreg2
9523 && !reg
->reg_type
.bitfield
.sreg3
)
9525 as_bad (_("`%s' is not a valid segment register"),
9529 else if (i
.mem_operands
>= 2)
9530 as_warn (_("Segment override ignored"));
9531 else if (i
.seg
[i
.mem_operands
])
9532 as_warn (_("Extra segment override ignored"));
9535 if (!intel_parser
.in_offset
)
9536 intel_parser
.is_mem
= 1;
9537 switch (reg
->reg_num
)
9540 i
.seg
[i
.mem_operands
] = &es
;
9543 i
.seg
[i
.mem_operands
] = &cs
;
9546 i
.seg
[i
.mem_operands
] = &ss
;
9549 i
.seg
[i
.mem_operands
] = &ds
;
9552 i
.seg
[i
.mem_operands
] = &fs
;
9555 i
.seg
[i
.mem_operands
] = &gs
;
9561 else if (reg
->reg_type
.bitfield
.sreg3
&& reg
->reg_num
== RegFlat
)
9563 as_bad (_("cannot use `FLAT' here"));
9567 /* Not a segment register. Check for register scaling. */
9568 else if (cur_token
.code
== '*')
9570 if (!intel_parser
.in_bracket
)
9572 as_bad (_("Register scaling only allowed in memory operands"));
9576 if (reg
->reg_type
.bitfield
.reg16
) /* Disallow things like [si*1]. */
9577 reg
= i386_regtab
+ REGNAM_AX
+ 4; /* sp is invalid as index */
9578 else if (i
.index_reg
)
9579 reg
= i386_regtab
+ REGNAM_EAX
+ 4; /* esp is invalid as index */
9581 /* What follows must be a valid scale. */
9582 intel_match_token ('*');
9584 i
.types
[this_operand
].bitfield
.baseindex
= 1;
9586 /* Set the scale after setting the register (otherwise,
9587 i386_scale will complain) */
9588 if (cur_token
.code
== '+' || cur_token
.code
== '-')
9590 char *str
, sign
= cur_token
.code
;
9591 intel_match_token (cur_token
.code
);
9592 if (cur_token
.code
!= T_CONST
)
9594 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
9598 str
= (char *) xmalloc (strlen (cur_token
.str
) + 2);
9599 strcpy (str
+ 1, cur_token
.str
);
9601 if (!i386_scale (str
))
9605 else if (!i386_scale (cur_token
.str
))
9607 intel_match_token (cur_token
.code
);
9610 /* No scaling. If this is a memory operand, the register is either a
9611 base register (first occurrence) or an index register (second
9613 else if (intel_parser
.in_bracket
)
9618 else if (!i
.index_reg
)
9622 as_bad (_("Too many register references in memory operand"));
9626 i
.types
[this_operand
].bitfield
.baseindex
= 1;
9629 /* It's neither base nor index. */
9630 else if (!intel_parser
.in_offset
&& !intel_parser
.is_mem
)
9632 i386_operand_type temp
= reg
->reg_type
;
9633 temp
.bitfield
.baseindex
= 0;
9634 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
9636 i
.types
[this_operand
].bitfield
.unspecified
= 0;
9637 i
.op
[this_operand
].regs
= reg
;
9642 as_bad (_("Invalid use of register"));
9646 /* Since registers are not part of the displacement string (except
9647 when we're parsing offset operands), we may need to remove any
9648 preceding '+' from the displacement string. */
9649 if (*intel_parser
.disp
!= '\0'
9650 && !intel_parser
.in_offset
)
9652 char *s
= intel_parser
.disp
;
9653 s
+= strlen (s
) - 1;
9678 intel_match_token (cur_token
.code
);
9680 if (cur_token
.code
== T_PTR
)
9683 /* It must have been an identifier. */
9684 intel_putback_token ();
9685 cur_token
.code
= T_ID
;
9691 if (!intel_parser
.in_offset
&& intel_parser
.is_mem
<= 0)
9695 /* The identifier represents a memory reference only if it's not
9696 preceded by an offset modifier and if it's not an equate. */
9697 symbolP
= symbol_find(cur_token
.str
);
9698 if (!symbolP
|| S_GET_SEGMENT(symbolP
) != absolute_section
)
9699 intel_parser
.is_mem
= 1;
9707 char *save_str
, sign
= 0;
9709 /* Allow constants that start with `+' or `-'. */
9710 if (cur_token
.code
== '-' || cur_token
.code
== '+')
9712 sign
= cur_token
.code
;
9713 intel_match_token (cur_token
.code
);
9714 if (cur_token
.code
!= T_CONST
)
9716 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
9722 save_str
= (char *) xmalloc (strlen (cur_token
.str
) + 2);
9723 strcpy (save_str
+ !!sign
, cur_token
.str
);
9727 /* Get the next token to check for register scaling. */
9728 intel_match_token (cur_token
.code
);
9730 /* Check if this constant is a scaling factor for an
9732 if (cur_token
.code
== '*')
9734 if (intel_match_token ('*') && cur_token
.code
== T_REG
)
9736 const reg_entry
*reg
= cur_token
.reg
;
9738 if (!intel_parser
.in_bracket
)
9740 as_bad (_("Register scaling only allowed "
9741 "in memory operands"));
9745 /* Disallow things like [1*si].
9746 sp and esp are invalid as index. */
9747 if (reg
->reg_type
.bitfield
.reg16
)
9748 reg
= i386_regtab
+ REGNAM_AX
+ 4;
9749 else if (i
.index_reg
)
9750 reg
= i386_regtab
+ REGNAM_EAX
+ 4;
9752 /* The constant is followed by `* reg', so it must be
9755 i
.types
[this_operand
].bitfield
.baseindex
= 1;
9757 /* Set the scale after setting the register (otherwise,
9758 i386_scale will complain) */
9759 if (!i386_scale (save_str
))
9761 intel_match_token (T_REG
);
9763 /* Since registers are not part of the displacement
9764 string, we may need to remove any preceding '+' from
9765 the displacement string. */
9766 if (*intel_parser
.disp
!= '\0')
9768 char *s
= intel_parser
.disp
;
9769 s
+= strlen (s
) - 1;
9779 /* The constant was not used for register scaling. Since we have
9780 already consumed the token following `*' we now need to put it
9781 back in the stream. */
9782 intel_putback_token ();
9785 /* Add the constant to the displacement string. */
9786 strcat (intel_parser
.disp
, save_str
);
9793 as_bad (_("Unrecognized token '%s'"), cur_token
.str
);
9797 /* Match the given token against cur_token. If they match, read the next
9798 token from the operand string. */
9800 intel_match_token (int code
)
9802 if (cur_token
.code
== code
)
9809 as_bad (_("Unexpected token `%s'"), cur_token
.str
);
9814 /* Read a new token from intel_parser.op_string and store it in cur_token. */
9816 intel_get_token (void)
9819 const reg_entry
*reg
;
9820 struct intel_token new_token
;
9822 new_token
.code
= T_NIL
;
9823 new_token
.reg
= NULL
;
9824 new_token
.str
= NULL
;
9826 /* Free the memory allocated to the previous token and move
9827 cur_token to prev_token. */
9829 free (prev_token
.str
);
9831 prev_token
= cur_token
;
9833 /* Skip whitespace. */
9834 while (is_space_char (*intel_parser
.op_string
))
9835 intel_parser
.op_string
++;
9837 /* Return an empty token if we find nothing else on the line. */
9838 if (*intel_parser
.op_string
== '\0')
9840 cur_token
= new_token
;
9844 /* The new token cannot be larger than the remainder of the operand
9846 new_token
.str
= (char *) xmalloc (strlen (intel_parser
.op_string
) + 1);
9847 new_token
.str
[0] = '\0';
9849 if (strchr ("0123456789", *intel_parser
.op_string
))
9851 char *p
= new_token
.str
;
9852 char *q
= intel_parser
.op_string
;
9853 new_token
.code
= T_CONST
;
9855 /* Allow any kind of identifier char to encompass floating point and
9856 hexadecimal numbers. */
9857 while (is_identifier_char (*q
))
9861 /* Recognize special symbol names [0-9][bf]. */
9862 if (strlen (intel_parser
.op_string
) == 2
9863 && (intel_parser
.op_string
[1] == 'b'
9864 || intel_parser
.op_string
[1] == 'f'))
9865 new_token
.code
= T_ID
;
9868 else if ((reg
= parse_register (intel_parser
.op_string
, &end_op
)) != NULL
)
9870 size_t len
= end_op
- intel_parser
.op_string
;
9872 new_token
.code
= T_REG
;
9873 new_token
.reg
= reg
;
9875 memcpy (new_token
.str
, intel_parser
.op_string
, len
);
9876 new_token
.str
[len
] = '\0';
9879 else if (is_identifier_char (*intel_parser
.op_string
))
9881 char *p
= new_token
.str
;
9882 char *q
= intel_parser
.op_string
;
9884 /* A '.' or '$' followed by an identifier char is an identifier.
9885 Otherwise, it's operator '.' followed by an expression. */
9886 if ((*q
== '.' || *q
== '$') && !is_identifier_char (*(q
+ 1)))
9888 new_token
.code
= '.';
9889 new_token
.str
[0] = '.';
9890 new_token
.str
[1] = '\0';
9894 while (is_identifier_char (*q
) || *q
== '@')
9898 if (strcasecmp (new_token
.str
, "NOT") == 0)
9899 new_token
.code
= '~';
9901 else if (strcasecmp (new_token
.str
, "MOD") == 0)
9902 new_token
.code
= '%';
9904 else if (strcasecmp (new_token
.str
, "AND") == 0)
9905 new_token
.code
= '&';
9907 else if (strcasecmp (new_token
.str
, "OR") == 0)
9908 new_token
.code
= '|';
9910 else if (strcasecmp (new_token
.str
, "XOR") == 0)
9911 new_token
.code
= '^';
9913 else if (strcasecmp (new_token
.str
, "SHL") == 0)
9914 new_token
.code
= T_SHL
;
9916 else if (strcasecmp (new_token
.str
, "SHR") == 0)
9917 new_token
.code
= T_SHR
;
9919 else if (strcasecmp (new_token
.str
, "BYTE") == 0)
9920 new_token
.code
= T_BYTE
;
9922 else if (strcasecmp (new_token
.str
, "WORD") == 0)
9923 new_token
.code
= T_WORD
;
9925 else if (strcasecmp (new_token
.str
, "DWORD") == 0)
9926 new_token
.code
= T_DWORD
;
9928 else if (strcasecmp (new_token
.str
, "FWORD") == 0)
9929 new_token
.code
= T_FWORD
;
9931 else if (strcasecmp (new_token
.str
, "QWORD") == 0)
9932 new_token
.code
= T_QWORD
;
9934 else if (strcasecmp (new_token
.str
, "TBYTE") == 0
9935 /* XXX remove (gcc still uses it) */
9936 || strcasecmp (new_token
.str
, "XWORD") == 0)
9937 new_token
.code
= T_TBYTE
;
9939 else if (strcasecmp (new_token
.str
, "XMMWORD") == 0
9940 || strcasecmp (new_token
.str
, "OWORD") == 0)
9941 new_token
.code
= T_XMMWORD
;
9943 else if (strcasecmp (new_token
.str
, "YMMWORD") == 0)
9944 new_token
.code
= T_YMMWORD
;
9946 else if (strcasecmp (new_token
.str
, "PTR") == 0)
9947 new_token
.code
= T_PTR
;
9949 else if (strcasecmp (new_token
.str
, "SHORT") == 0)
9950 new_token
.code
= T_SHORT
;
9952 else if (strcasecmp (new_token
.str
, "OFFSET") == 0)
9954 new_token
.code
= T_OFFSET
;
9956 /* ??? This is not mentioned in the MASM grammar but gcc
9957 makes use of it with -mintel-syntax. OFFSET may be
9958 followed by FLAT: */
9959 if (strncasecmp (q
, " FLAT:", 6) == 0)
9960 strcat (new_token
.str
, " FLAT:");
9964 new_token
.code
= T_ID
;
9968 else if (strchr ("+-/*%|&^:[]()~", *intel_parser
.op_string
))
9970 new_token
.code
= *intel_parser
.op_string
;
9971 new_token
.str
[0] = *intel_parser
.op_string
;
9972 new_token
.str
[1] = '\0';
9975 else if (strchr ("<>", *intel_parser
.op_string
)
9976 && *intel_parser
.op_string
== *(intel_parser
.op_string
+ 1))
9978 new_token
.code
= *intel_parser
.op_string
== '<' ? T_SHL
: T_SHR
;
9979 new_token
.str
[0] = *intel_parser
.op_string
;
9980 new_token
.str
[1] = *intel_parser
.op_string
;
9981 new_token
.str
[2] = '\0';
9985 as_bad (_("Unrecognized token `%s'"), intel_parser
.op_string
);
9987 intel_parser
.op_string
+= strlen (new_token
.str
);
9988 cur_token
= new_token
;
9991 /* Put cur_token back into the token stream and make cur_token point to
9994 intel_putback_token (void)
9996 if (cur_token
.code
!= T_NIL
)
9998 intel_parser
.op_string
-= strlen (cur_token
.str
);
9999 free (cur_token
.str
);
10001 cur_token
= prev_token
;
10003 /* Forget prev_token. */
10004 prev_token
.code
= T_NIL
;
10005 prev_token
.reg
= NULL
;
10006 prev_token
.str
= NULL
;
10010 tc_x86_parse_to_dw2regnum (expressionS
*exp
)
10012 int saved_naked_reg
;
10013 char saved_register_dot
;
10015 saved_naked_reg
= allow_naked_reg
;
10016 allow_naked_reg
= 1;
10017 saved_register_dot
= register_chars
['.'];
10018 register_chars
['.'] = '.';
10019 allow_pseudo_reg
= 1;
10020 expression_and_evaluate (exp
);
10021 allow_pseudo_reg
= 0;
10022 register_chars
['.'] = saved_register_dot
;
10023 allow_naked_reg
= saved_naked_reg
;
10025 if (exp
->X_op
== O_register
&& exp
->X_add_number
>= 0)
10027 if ((addressT
) exp
->X_add_number
< i386_regtab_size
)
10029 exp
->X_op
= O_constant
;
10030 exp
->X_add_number
= i386_regtab
[exp
->X_add_number
]
10031 .dw2_regnum
[flag_code
>> 1];
10034 exp
->X_op
= O_illegal
;
10039 tc_x86_frame_initial_instructions (void)
10041 static unsigned int sp_regno
[2];
10043 if (!sp_regno
[flag_code
>> 1])
10045 char *saved_input
= input_line_pointer
;
10046 char sp
[][4] = {"esp", "rsp"};
10049 input_line_pointer
= sp
[flag_code
>> 1];
10050 tc_x86_parse_to_dw2regnum (&exp
);
10051 assert (exp
.X_op
== O_constant
);
10052 sp_regno
[flag_code
>> 1] = exp
.X_add_number
;
10053 input_line_pointer
= saved_input
;
10056 cfi_add_CFA_def_cfa (sp_regno
[flag_code
>> 1], -x86_cie_data_alignment
);
10057 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
10061 i386_elf_section_type (const char *str
, size_t len
)
10063 if (flag_code
== CODE_64BIT
10064 && len
== sizeof ("unwind") - 1
10065 && strncmp (str
, "unwind", 6) == 0)
10066 return SHT_X86_64_UNWIND
;
10073 i386_solaris_fix_up_eh_frame (segT sec
)
10075 if (flag_code
== CODE_64BIT
)
10076 elf_section_type (sec
) = SHT_X86_64_UNWIND
;
10082 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
10086 expr
.X_op
= O_secrel
;
10087 expr
.X_add_symbol
= symbol
;
10088 expr
.X_add_number
= 0;
10089 emit_expr (&expr
, size
);
10093 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10094 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
10097 x86_64_section_letter (int letter
, char **ptr_msg
)
10099 if (flag_code
== CODE_64BIT
)
10102 return SHF_X86_64_LARGE
;
10104 *ptr_msg
= _("Bad .section directive: want a,l,w,x,M,S,G,T in string");
10107 *ptr_msg
= _("Bad .section directive: want a,w,x,M,S,G,T in string");
10112 x86_64_section_word (char *str
, size_t len
)
10114 if (len
== 5 && flag_code
== CODE_64BIT
&& CONST_STRNEQ (str
, "large"))
10115 return SHF_X86_64_LARGE
;
10121 handle_large_common (int small ATTRIBUTE_UNUSED
)
10123 if (flag_code
!= CODE_64BIT
)
10125 s_comm_internal (0, elf_common_parse
);
10126 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
10130 static segT lbss_section
;
10131 asection
*saved_com_section_ptr
= elf_com_section_ptr
;
10132 asection
*saved_bss_section
= bss_section
;
10134 if (lbss_section
== NULL
)
10136 flagword applicable
;
10137 segT seg
= now_seg
;
10138 subsegT subseg
= now_subseg
;
10140 /* The .lbss section is for local .largecomm symbols. */
10141 lbss_section
= subseg_new (".lbss", 0);
10142 applicable
= bfd_applicable_section_flags (stdoutput
);
10143 bfd_set_section_flags (stdoutput
, lbss_section
,
10144 applicable
& SEC_ALLOC
);
10145 seg_info (lbss_section
)->bss
= 1;
10147 subseg_set (seg
, subseg
);
10150 elf_com_section_ptr
= &_bfd_elf_large_com_section
;
10151 bss_section
= lbss_section
;
10153 s_comm_internal (0, elf_common_parse
);
10155 elf_com_section_ptr
= saved_com_section_ptr
;
10156 bss_section
= saved_bss_section
;
10159 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */