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Enable Intel AVX512_VBMI2 instructions.
[deliverable/binutils-gdb.git] / gas / config / tc-i386.c
1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright (C) 1989-2017 Free Software Foundation, Inc.
3
4 This file is part of GAS, the GNU Assembler.
5
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
9 any later version.
10
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
19 02110-1301, USA. */
20
21 /* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
23 x86_64 support by Jan Hubicka (jh@suse.cz)
24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
27
28 #include "as.h"
29 #include "safe-ctype.h"
30 #include "subsegs.h"
31 #include "dwarf2dbg.h"
32 #include "dw2gencfi.h"
33 #include "elf/x86-64.h"
34 #include "opcodes/i386-init.h"
35
36 #ifndef REGISTER_WARNINGS
37 #define REGISTER_WARNINGS 1
38 #endif
39
40 #ifndef INFER_ADDR_PREFIX
41 #define INFER_ADDR_PREFIX 1
42 #endif
43
44 #ifndef DEFAULT_ARCH
45 #define DEFAULT_ARCH "i386"
46 #endif
47
48 #ifndef INLINE
49 #if __GNUC__ >= 2
50 #define INLINE __inline__
51 #else
52 #define INLINE
53 #endif
54 #endif
55
56 /* Prefixes will be emitted in the order defined below.
57 WAIT_PREFIX must be the first prefix since FWAIT is really is an
58 instruction, and so must come before any prefixes.
59 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
60 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
61 #define WAIT_PREFIX 0
62 #define SEG_PREFIX 1
63 #define ADDR_PREFIX 2
64 #define DATA_PREFIX 3
65 #define REP_PREFIX 4
66 #define HLE_PREFIX REP_PREFIX
67 #define BND_PREFIX REP_PREFIX
68 #define LOCK_PREFIX 5
69 #define REX_PREFIX 6 /* must come last. */
70 #define MAX_PREFIXES 7 /* max prefixes per opcode */
71
72 /* we define the syntax here (modulo base,index,scale syntax) */
73 #define REGISTER_PREFIX '%'
74 #define IMMEDIATE_PREFIX '$'
75 #define ABSOLUTE_PREFIX '*'
76
77 /* these are the instruction mnemonic suffixes in AT&T syntax or
78 memory operand size in Intel syntax. */
79 #define WORD_MNEM_SUFFIX 'w'
80 #define BYTE_MNEM_SUFFIX 'b'
81 #define SHORT_MNEM_SUFFIX 's'
82 #define LONG_MNEM_SUFFIX 'l'
83 #define QWORD_MNEM_SUFFIX 'q'
84 #define XMMWORD_MNEM_SUFFIX 'x'
85 #define YMMWORD_MNEM_SUFFIX 'y'
86 #define ZMMWORD_MNEM_SUFFIX 'z'
87 /* Intel Syntax. Use a non-ascii letter since since it never appears
88 in instructions. */
89 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
90
91 #define END_OF_INSN '\0'
92
93 /*
94 'templates' is for grouping together 'template' structures for opcodes
95 of the same name. This is only used for storing the insns in the grand
96 ole hash table of insns.
97 The templates themselves start at START and range up to (but not including)
98 END.
99 */
100 typedef struct
101 {
102 const insn_template *start;
103 const insn_template *end;
104 }
105 templates;
106
107 /* 386 operand encoding bytes: see 386 book for details of this. */
108 typedef struct
109 {
110 unsigned int regmem; /* codes register or memory operand */
111 unsigned int reg; /* codes register operand (or extended opcode) */
112 unsigned int mode; /* how to interpret regmem & reg */
113 }
114 modrm_byte;
115
116 /* x86-64 extension prefix. */
117 typedef int rex_byte;
118
119 /* 386 opcode byte to code indirect addressing. */
120 typedef struct
121 {
122 unsigned base;
123 unsigned index;
124 unsigned scale;
125 }
126 sib_byte;
127
128 /* x86 arch names, types and features */
129 typedef struct
130 {
131 const char *name; /* arch name */
132 unsigned int len; /* arch string length */
133 enum processor_type type; /* arch type */
134 i386_cpu_flags flags; /* cpu feature flags */
135 unsigned int skip; /* show_arch should skip this. */
136 }
137 arch_entry;
138
139 /* Used to turn off indicated flags. */
140 typedef struct
141 {
142 const char *name; /* arch name */
143 unsigned int len; /* arch string length */
144 i386_cpu_flags flags; /* cpu feature flags */
145 }
146 noarch_entry;
147
148 static void update_code_flag (int, int);
149 static void set_code_flag (int);
150 static void set_16bit_gcc_code_flag (int);
151 static void set_intel_syntax (int);
152 static void set_intel_mnemonic (int);
153 static void set_allow_index_reg (int);
154 static void set_check (int);
155 static void set_cpu_arch (int);
156 #ifdef TE_PE
157 static void pe_directive_secrel (int);
158 #endif
159 static void signed_cons (int);
160 static char *output_invalid (int c);
161 static int i386_finalize_immediate (segT, expressionS *, i386_operand_type,
162 const char *);
163 static int i386_finalize_displacement (segT, expressionS *, i386_operand_type,
164 const char *);
165 static int i386_att_operand (char *);
166 static int i386_intel_operand (char *, int);
167 static int i386_intel_simplify (expressionS *);
168 static int i386_intel_parse_name (const char *, expressionS *);
169 static const reg_entry *parse_register (char *, char **);
170 static char *parse_insn (char *, char *);
171 static char *parse_operands (char *, const char *);
172 static void swap_operands (void);
173 static void swap_2_operands (int, int);
174 static void optimize_imm (void);
175 static void optimize_disp (void);
176 static const insn_template *match_template (char);
177 static int check_string (void);
178 static int process_suffix (void);
179 static int check_byte_reg (void);
180 static int check_long_reg (void);
181 static int check_qword_reg (void);
182 static int check_word_reg (void);
183 static int finalize_imm (void);
184 static int process_operands (void);
185 static const seg_entry *build_modrm_byte (void);
186 static void output_insn (void);
187 static void output_imm (fragS *, offsetT);
188 static void output_disp (fragS *, offsetT);
189 #ifndef I386COFF
190 static void s_bss (int);
191 #endif
192 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
193 static void handle_large_common (int small ATTRIBUTE_UNUSED);
194 #endif
195
196 static const char *default_arch = DEFAULT_ARCH;
197
198 /* This struct describes rounding control and SAE in the instruction. */
199 struct RC_Operation
200 {
201 enum rc_type
202 {
203 rne = 0,
204 rd,
205 ru,
206 rz,
207 saeonly
208 } type;
209 int operand;
210 };
211
212 static struct RC_Operation rc_op;
213
214 /* The struct describes masking, applied to OPERAND in the instruction.
215 MASK is a pointer to the corresponding mask register. ZEROING tells
216 whether merging or zeroing mask is used. */
217 struct Mask_Operation
218 {
219 const reg_entry *mask;
220 unsigned int zeroing;
221 /* The operand where this operation is associated. */
222 int operand;
223 };
224
225 static struct Mask_Operation mask_op;
226
227 /* The struct describes broadcasting, applied to OPERAND. FACTOR is
228 broadcast factor. */
229 struct Broadcast_Operation
230 {
231 /* Type of broadcast: no broadcast, {1to8}, or {1to16}. */
232 int type;
233
234 /* Index of broadcasted operand. */
235 int operand;
236 };
237
238 static struct Broadcast_Operation broadcast_op;
239
240 /* VEX prefix. */
241 typedef struct
242 {
243 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
244 unsigned char bytes[4];
245 unsigned int length;
246 /* Destination or source register specifier. */
247 const reg_entry *register_specifier;
248 } vex_prefix;
249
250 /* 'md_assemble ()' gathers together information and puts it into a
251 i386_insn. */
252
253 union i386_op
254 {
255 expressionS *disps;
256 expressionS *imms;
257 const reg_entry *regs;
258 };
259
260 enum i386_error
261 {
262 operand_size_mismatch,
263 operand_type_mismatch,
264 register_type_mismatch,
265 number_of_operands_mismatch,
266 invalid_instruction_suffix,
267 bad_imm4,
268 old_gcc_only,
269 unsupported_with_intel_mnemonic,
270 unsupported_syntax,
271 unsupported,
272 invalid_vsib_address,
273 invalid_vector_register_set,
274 unsupported_vector_index_register,
275 unsupported_broadcast,
276 broadcast_not_on_src_operand,
277 broadcast_needed,
278 unsupported_masking,
279 mask_not_on_destination,
280 no_default_mask,
281 unsupported_rc_sae,
282 rc_sae_operand_not_last_imm,
283 invalid_register_operand,
284 try_vector_disp8
285 };
286
287 struct _i386_insn
288 {
289 /* TM holds the template for the insn were currently assembling. */
290 insn_template tm;
291
292 /* SUFFIX holds the instruction size suffix for byte, word, dword
293 or qword, if given. */
294 char suffix;
295
296 /* OPERANDS gives the number of given operands. */
297 unsigned int operands;
298
299 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
300 of given register, displacement, memory operands and immediate
301 operands. */
302 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
303
304 /* TYPES [i] is the type (see above #defines) which tells us how to
305 use OP[i] for the corresponding operand. */
306 i386_operand_type types[MAX_OPERANDS];
307
308 /* Displacement expression, immediate expression, or register for each
309 operand. */
310 union i386_op op[MAX_OPERANDS];
311
312 /* Flags for operands. */
313 unsigned int flags[MAX_OPERANDS];
314 #define Operand_PCrel 1
315
316 /* Relocation type for operand */
317 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
318
319 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
320 the base index byte below. */
321 const reg_entry *base_reg;
322 const reg_entry *index_reg;
323 unsigned int log2_scale_factor;
324
325 /* SEG gives the seg_entries of this insn. They are zero unless
326 explicit segment overrides are given. */
327 const seg_entry *seg[2];
328
329 /* Copied first memory operand string, for re-checking. */
330 char *memop1_string;
331
332 /* PREFIX holds all the given prefix opcodes (usually null).
333 PREFIXES is the number of prefix opcodes. */
334 unsigned int prefixes;
335 unsigned char prefix[MAX_PREFIXES];
336
337 /* RM and SIB are the modrm byte and the sib byte where the
338 addressing modes of this insn are encoded. */
339 modrm_byte rm;
340 rex_byte rex;
341 rex_byte vrex;
342 sib_byte sib;
343 vex_prefix vex;
344
345 /* Masking attributes. */
346 struct Mask_Operation *mask;
347
348 /* Rounding control and SAE attributes. */
349 struct RC_Operation *rounding;
350
351 /* Broadcasting attributes. */
352 struct Broadcast_Operation *broadcast;
353
354 /* Compressed disp8*N attribute. */
355 unsigned int memshift;
356
357 /* Prefer load or store in encoding. */
358 enum
359 {
360 dir_encoding_default = 0,
361 dir_encoding_load,
362 dir_encoding_store
363 } dir_encoding;
364
365 /* Prefer 8bit or 32bit displacement in encoding. */
366 enum
367 {
368 disp_encoding_default = 0,
369 disp_encoding_8bit,
370 disp_encoding_32bit
371 } disp_encoding;
372
373 /* How to encode vector instructions. */
374 enum
375 {
376 vex_encoding_default = 0,
377 vex_encoding_vex2,
378 vex_encoding_vex3,
379 vex_encoding_evex
380 } vec_encoding;
381
382 /* REP prefix. */
383 const char *rep_prefix;
384
385 /* HLE prefix. */
386 const char *hle_prefix;
387
388 /* Have BND prefix. */
389 const char *bnd_prefix;
390
391 /* Have NOTRACK prefix. */
392 const char *notrack_prefix;
393
394 /* Error message. */
395 enum i386_error error;
396 };
397
398 typedef struct _i386_insn i386_insn;
399
400 /* Link RC type with corresponding string, that'll be looked for in
401 asm. */
402 struct RC_name
403 {
404 enum rc_type type;
405 const char *name;
406 unsigned int len;
407 };
408
409 static const struct RC_name RC_NamesTable[] =
410 {
411 { rne, STRING_COMMA_LEN ("rn-sae") },
412 { rd, STRING_COMMA_LEN ("rd-sae") },
413 { ru, STRING_COMMA_LEN ("ru-sae") },
414 { rz, STRING_COMMA_LEN ("rz-sae") },
415 { saeonly, STRING_COMMA_LEN ("sae") },
416 };
417
418 /* List of chars besides those in app.c:symbol_chars that can start an
419 operand. Used to prevent the scrubber eating vital white-space. */
420 const char extra_symbol_chars[] = "*%-([{}"
421 #ifdef LEX_AT
422 "@"
423 #endif
424 #ifdef LEX_QM
425 "?"
426 #endif
427 ;
428
429 #if (defined (TE_I386AIX) \
430 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
431 && !defined (TE_GNU) \
432 && !defined (TE_LINUX) \
433 && !defined (TE_NACL) \
434 && !defined (TE_NETWARE) \
435 && !defined (TE_FreeBSD) \
436 && !defined (TE_DragonFly) \
437 && !defined (TE_NetBSD)))
438 /* This array holds the chars that always start a comment. If the
439 pre-processor is disabled, these aren't very useful. The option
440 --divide will remove '/' from this list. */
441 const char *i386_comment_chars = "#/";
442 #define SVR4_COMMENT_CHARS 1
443 #define PREFIX_SEPARATOR '\\'
444
445 #else
446 const char *i386_comment_chars = "#";
447 #define PREFIX_SEPARATOR '/'
448 #endif
449
450 /* This array holds the chars that only start a comment at the beginning of
451 a line. If the line seems to have the form '# 123 filename'
452 .line and .file directives will appear in the pre-processed output.
453 Note that input_file.c hand checks for '#' at the beginning of the
454 first line of the input file. This is because the compiler outputs
455 #NO_APP at the beginning of its output.
456 Also note that comments started like this one will always work if
457 '/' isn't otherwise defined. */
458 const char line_comment_chars[] = "#/";
459
460 const char line_separator_chars[] = ";";
461
462 /* Chars that can be used to separate mant from exp in floating point
463 nums. */
464 const char EXP_CHARS[] = "eE";
465
466 /* Chars that mean this number is a floating point constant
467 As in 0f12.456
468 or 0d1.2345e12. */
469 const char FLT_CHARS[] = "fFdDxX";
470
471 /* Tables for lexical analysis. */
472 static char mnemonic_chars[256];
473 static char register_chars[256];
474 static char operand_chars[256];
475 static char identifier_chars[256];
476 static char digit_chars[256];
477
478 /* Lexical macros. */
479 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
480 #define is_operand_char(x) (operand_chars[(unsigned char) x])
481 #define is_register_char(x) (register_chars[(unsigned char) x])
482 #define is_space_char(x) ((x) == ' ')
483 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
484 #define is_digit_char(x) (digit_chars[(unsigned char) x])
485
486 /* All non-digit non-letter characters that may occur in an operand. */
487 static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
488
489 /* md_assemble() always leaves the strings it's passed unaltered. To
490 effect this we maintain a stack of saved characters that we've smashed
491 with '\0's (indicating end of strings for various sub-fields of the
492 assembler instruction). */
493 static char save_stack[32];
494 static char *save_stack_p;
495 #define END_STRING_AND_SAVE(s) \
496 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
497 #define RESTORE_END_STRING(s) \
498 do { *(s) = *--save_stack_p; } while (0)
499
500 /* The instruction we're assembling. */
501 static i386_insn i;
502
503 /* Possible templates for current insn. */
504 static const templates *current_templates;
505
506 /* Per instruction expressionS buffers: max displacements & immediates. */
507 static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
508 static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
509
510 /* Current operand we are working on. */
511 static int this_operand = -1;
512
513 /* We support four different modes. FLAG_CODE variable is used to distinguish
514 these. */
515
516 enum flag_code {
517 CODE_32BIT,
518 CODE_16BIT,
519 CODE_64BIT };
520
521 static enum flag_code flag_code;
522 static unsigned int object_64bit;
523 static unsigned int disallow_64bit_reloc;
524 static int use_rela_relocations = 0;
525
526 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
527 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
528 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
529
530 /* The ELF ABI to use. */
531 enum x86_elf_abi
532 {
533 I386_ABI,
534 X86_64_ABI,
535 X86_64_X32_ABI
536 };
537
538 static enum x86_elf_abi x86_elf_abi = I386_ABI;
539 #endif
540
541 #if defined (TE_PE) || defined (TE_PEP)
542 /* Use big object file format. */
543 static int use_big_obj = 0;
544 #endif
545
546 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
547 /* 1 if generating code for a shared library. */
548 static int shared = 0;
549 #endif
550
551 /* 1 for intel syntax,
552 0 if att syntax. */
553 static int intel_syntax = 0;
554
555 /* 1 for Intel64 ISA,
556 0 if AMD64 ISA. */
557 static int intel64;
558
559 /* 1 for intel mnemonic,
560 0 if att mnemonic. */
561 static int intel_mnemonic = !SYSV386_COMPAT;
562
563 /* 1 if support old (<= 2.8.1) versions of gcc. */
564 static int old_gcc = OLDGCC_COMPAT;
565
566 /* 1 if pseudo registers are permitted. */
567 static int allow_pseudo_reg = 0;
568
569 /* 1 if register prefix % not required. */
570 static int allow_naked_reg = 0;
571
572 /* 1 if the assembler should add BND prefix for all control-transferring
573 instructions supporting it, even if this prefix wasn't specified
574 explicitly. */
575 static int add_bnd_prefix = 0;
576
577 /* 1 if pseudo index register, eiz/riz, is allowed . */
578 static int allow_index_reg = 0;
579
580 /* 1 if the assembler should ignore LOCK prefix, even if it was
581 specified explicitly. */
582 static int omit_lock_prefix = 0;
583
584 /* 1 if the assembler should encode lfence, mfence, and sfence as
585 "lock addl $0, (%{re}sp)". */
586 static int avoid_fence = 0;
587
588 /* 1 if the assembler should generate relax relocations. */
589
590 static int generate_relax_relocations
591 = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS;
592
593 static enum check_kind
594 {
595 check_none = 0,
596 check_warning,
597 check_error
598 }
599 sse_check, operand_check = check_warning;
600
601 /* Register prefix used for error message. */
602 static const char *register_prefix = "%";
603
604 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
605 leave, push, and pop instructions so that gcc has the same stack
606 frame as in 32 bit mode. */
607 static char stackop_size = '\0';
608
609 /* Non-zero to optimize code alignment. */
610 int optimize_align_code = 1;
611
612 /* Non-zero to quieten some warnings. */
613 static int quiet_warnings = 0;
614
615 /* CPU name. */
616 static const char *cpu_arch_name = NULL;
617 static char *cpu_sub_arch_name = NULL;
618
619 /* CPU feature flags. */
620 static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS;
621
622 /* If we have selected a cpu we are generating instructions for. */
623 static int cpu_arch_tune_set = 0;
624
625 /* Cpu we are generating instructions for. */
626 enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
627
628 /* CPU feature flags of cpu we are generating instructions for. */
629 static i386_cpu_flags cpu_arch_tune_flags;
630
631 /* CPU instruction set architecture used. */
632 enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
633
634 /* CPU feature flags of instruction set architecture used. */
635 i386_cpu_flags cpu_arch_isa_flags;
636
637 /* If set, conditional jumps are not automatically promoted to handle
638 larger than a byte offset. */
639 static unsigned int no_cond_jump_promotion = 0;
640
641 /* Encode SSE instructions with VEX prefix. */
642 static unsigned int sse2avx;
643
644 /* Encode scalar AVX instructions with specific vector length. */
645 static enum
646 {
647 vex128 = 0,
648 vex256
649 } avxscalar;
650
651 /* Encode scalar EVEX LIG instructions with specific vector length. */
652 static enum
653 {
654 evexl128 = 0,
655 evexl256,
656 evexl512
657 } evexlig;
658
659 /* Encode EVEX WIG instructions with specific evex.w. */
660 static enum
661 {
662 evexw0 = 0,
663 evexw1
664 } evexwig;
665
666 /* Value to encode in EVEX RC bits, for SAE-only instructions. */
667 static enum rc_type evexrcig = rne;
668
669 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
670 static symbolS *GOT_symbol;
671
672 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
673 unsigned int x86_dwarf2_return_column;
674
675 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
676 int x86_cie_data_alignment;
677
678 /* Interface to relax_segment.
679 There are 3 major relax states for 386 jump insns because the
680 different types of jumps add different sizes to frags when we're
681 figuring out what sort of jump to choose to reach a given label. */
682
683 /* Types. */
684 #define UNCOND_JUMP 0
685 #define COND_JUMP 1
686 #define COND_JUMP86 2
687
688 /* Sizes. */
689 #define CODE16 1
690 #define SMALL 0
691 #define SMALL16 (SMALL | CODE16)
692 #define BIG 2
693 #define BIG16 (BIG | CODE16)
694
695 #ifndef INLINE
696 #ifdef __GNUC__
697 #define INLINE __inline__
698 #else
699 #define INLINE
700 #endif
701 #endif
702
703 #define ENCODE_RELAX_STATE(type, size) \
704 ((relax_substateT) (((type) << 2) | (size)))
705 #define TYPE_FROM_RELAX_STATE(s) \
706 ((s) >> 2)
707 #define DISP_SIZE_FROM_RELAX_STATE(s) \
708 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
709
710 /* This table is used by relax_frag to promote short jumps to long
711 ones where necessary. SMALL (short) jumps may be promoted to BIG
712 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
713 don't allow a short jump in a 32 bit code segment to be promoted to
714 a 16 bit offset jump because it's slower (requires data size
715 prefix), and doesn't work, unless the destination is in the bottom
716 64k of the code segment (The top 16 bits of eip are zeroed). */
717
718 const relax_typeS md_relax_table[] =
719 {
720 /* The fields are:
721 1) most positive reach of this state,
722 2) most negative reach of this state,
723 3) how many bytes this mode will have in the variable part of the frag
724 4) which index into the table to try if we can't fit into this one. */
725
726 /* UNCOND_JUMP states. */
727 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
728 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
729 /* dword jmp adds 4 bytes to frag:
730 0 extra opcode bytes, 4 displacement bytes. */
731 {0, 0, 4, 0},
732 /* word jmp adds 2 byte2 to frag:
733 0 extra opcode bytes, 2 displacement bytes. */
734 {0, 0, 2, 0},
735
736 /* COND_JUMP states. */
737 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
738 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
739 /* dword conditionals adds 5 bytes to frag:
740 1 extra opcode byte, 4 displacement bytes. */
741 {0, 0, 5, 0},
742 /* word conditionals add 3 bytes to frag:
743 1 extra opcode byte, 2 displacement bytes. */
744 {0, 0, 3, 0},
745
746 /* COND_JUMP86 states. */
747 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
748 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
749 /* dword conditionals adds 5 bytes to frag:
750 1 extra opcode byte, 4 displacement bytes. */
751 {0, 0, 5, 0},
752 /* word conditionals add 4 bytes to frag:
753 1 displacement byte and a 3 byte long branch insn. */
754 {0, 0, 4, 0}
755 };
756
757 static const arch_entry cpu_arch[] =
758 {
759 /* Do not replace the first two entries - i386_target_format()
760 relies on them being there in this order. */
761 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32,
762 CPU_GENERIC32_FLAGS, 0 },
763 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64,
764 CPU_GENERIC64_FLAGS, 0 },
765 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN,
766 CPU_NONE_FLAGS, 0 },
767 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN,
768 CPU_I186_FLAGS, 0 },
769 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN,
770 CPU_I286_FLAGS, 0 },
771 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386,
772 CPU_I386_FLAGS, 0 },
773 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486,
774 CPU_I486_FLAGS, 0 },
775 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM,
776 CPU_I586_FLAGS, 0 },
777 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO,
778 CPU_I686_FLAGS, 0 },
779 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM,
780 CPU_I586_FLAGS, 0 },
781 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO,
782 CPU_PENTIUMPRO_FLAGS, 0 },
783 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO,
784 CPU_P2_FLAGS, 0 },
785 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO,
786 CPU_P3_FLAGS, 0 },
787 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4,
788 CPU_P4_FLAGS, 0 },
789 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA,
790 CPU_CORE_FLAGS, 0 },
791 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA,
792 CPU_NOCONA_FLAGS, 0 },
793 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE,
794 CPU_CORE_FLAGS, 1 },
795 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE,
796 CPU_CORE_FLAGS, 0 },
797 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2,
798 CPU_CORE2_FLAGS, 1 },
799 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2,
800 CPU_CORE2_FLAGS, 0 },
801 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7,
802 CPU_COREI7_FLAGS, 0 },
803 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM,
804 CPU_L1OM_FLAGS, 0 },
805 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM,
806 CPU_K1OM_FLAGS, 0 },
807 { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU,
808 CPU_IAMCU_FLAGS, 0 },
809 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6,
810 CPU_K6_FLAGS, 0 },
811 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6,
812 CPU_K6_2_FLAGS, 0 },
813 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON,
814 CPU_ATHLON_FLAGS, 0 },
815 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8,
816 CPU_K8_FLAGS, 1 },
817 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8,
818 CPU_K8_FLAGS, 0 },
819 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8,
820 CPU_K8_FLAGS, 0 },
821 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10,
822 CPU_AMDFAM10_FLAGS, 0 },
823 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD,
824 CPU_BDVER1_FLAGS, 0 },
825 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD,
826 CPU_BDVER2_FLAGS, 0 },
827 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD,
828 CPU_BDVER3_FLAGS, 0 },
829 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD,
830 CPU_BDVER4_FLAGS, 0 },
831 { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER,
832 CPU_ZNVER1_FLAGS, 0 },
833 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT,
834 CPU_BTVER1_FLAGS, 0 },
835 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT,
836 CPU_BTVER2_FLAGS, 0 },
837 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN,
838 CPU_8087_FLAGS, 0 },
839 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN,
840 CPU_287_FLAGS, 0 },
841 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN,
842 CPU_387_FLAGS, 0 },
843 { STRING_COMMA_LEN (".687"), PROCESSOR_UNKNOWN,
844 CPU_687_FLAGS, 0 },
845 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN,
846 CPU_MMX_FLAGS, 0 },
847 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN,
848 CPU_SSE_FLAGS, 0 },
849 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN,
850 CPU_SSE2_FLAGS, 0 },
851 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN,
852 CPU_SSE3_FLAGS, 0 },
853 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN,
854 CPU_SSSE3_FLAGS, 0 },
855 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN,
856 CPU_SSE4_1_FLAGS, 0 },
857 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN,
858 CPU_SSE4_2_FLAGS, 0 },
859 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN,
860 CPU_SSE4_2_FLAGS, 0 },
861 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN,
862 CPU_AVX_FLAGS, 0 },
863 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN,
864 CPU_AVX2_FLAGS, 0 },
865 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN,
866 CPU_AVX512F_FLAGS, 0 },
867 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN,
868 CPU_AVX512CD_FLAGS, 0 },
869 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN,
870 CPU_AVX512ER_FLAGS, 0 },
871 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN,
872 CPU_AVX512PF_FLAGS, 0 },
873 { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN,
874 CPU_AVX512DQ_FLAGS, 0 },
875 { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN,
876 CPU_AVX512BW_FLAGS, 0 },
877 { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN,
878 CPU_AVX512VL_FLAGS, 0 },
879 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN,
880 CPU_VMX_FLAGS, 0 },
881 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN,
882 CPU_VMFUNC_FLAGS, 0 },
883 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN,
884 CPU_SMX_FLAGS, 0 },
885 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN,
886 CPU_XSAVE_FLAGS, 0 },
887 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN,
888 CPU_XSAVEOPT_FLAGS, 0 },
889 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN,
890 CPU_XSAVEC_FLAGS, 0 },
891 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN,
892 CPU_XSAVES_FLAGS, 0 },
893 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN,
894 CPU_AES_FLAGS, 0 },
895 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN,
896 CPU_PCLMUL_FLAGS, 0 },
897 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN,
898 CPU_PCLMUL_FLAGS, 1 },
899 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN,
900 CPU_FSGSBASE_FLAGS, 0 },
901 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN,
902 CPU_RDRND_FLAGS, 0 },
903 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN,
904 CPU_F16C_FLAGS, 0 },
905 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN,
906 CPU_BMI2_FLAGS, 0 },
907 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN,
908 CPU_FMA_FLAGS, 0 },
909 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN,
910 CPU_FMA4_FLAGS, 0 },
911 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN,
912 CPU_XOP_FLAGS, 0 },
913 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN,
914 CPU_LWP_FLAGS, 0 },
915 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN,
916 CPU_MOVBE_FLAGS, 0 },
917 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN,
918 CPU_CX16_FLAGS, 0 },
919 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN,
920 CPU_EPT_FLAGS, 0 },
921 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN,
922 CPU_LZCNT_FLAGS, 0 },
923 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN,
924 CPU_HLE_FLAGS, 0 },
925 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN,
926 CPU_RTM_FLAGS, 0 },
927 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN,
928 CPU_INVPCID_FLAGS, 0 },
929 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN,
930 CPU_CLFLUSH_FLAGS, 0 },
931 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN,
932 CPU_NOP_FLAGS, 0 },
933 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN,
934 CPU_SYSCALL_FLAGS, 0 },
935 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN,
936 CPU_RDTSCP_FLAGS, 0 },
937 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN,
938 CPU_3DNOW_FLAGS, 0 },
939 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN,
940 CPU_3DNOWA_FLAGS, 0 },
941 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN,
942 CPU_PADLOCK_FLAGS, 0 },
943 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN,
944 CPU_SVME_FLAGS, 1 },
945 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN,
946 CPU_SVME_FLAGS, 0 },
947 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN,
948 CPU_SSE4A_FLAGS, 0 },
949 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN,
950 CPU_ABM_FLAGS, 0 },
951 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN,
952 CPU_BMI_FLAGS, 0 },
953 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN,
954 CPU_TBM_FLAGS, 0 },
955 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN,
956 CPU_ADX_FLAGS, 0 },
957 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN,
958 CPU_RDSEED_FLAGS, 0 },
959 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN,
960 CPU_PRFCHW_FLAGS, 0 },
961 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN,
962 CPU_SMAP_FLAGS, 0 },
963 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN,
964 CPU_MPX_FLAGS, 0 },
965 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN,
966 CPU_SHA_FLAGS, 0 },
967 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN,
968 CPU_CLFLUSHOPT_FLAGS, 0 },
969 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN,
970 CPU_PREFETCHWT1_FLAGS, 0 },
971 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN,
972 CPU_SE1_FLAGS, 0 },
973 { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN,
974 CPU_CLWB_FLAGS, 0 },
975 { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN,
976 CPU_AVX512IFMA_FLAGS, 0 },
977 { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN,
978 CPU_AVX512VBMI_FLAGS, 0 },
979 { STRING_COMMA_LEN (".avx512_4fmaps"), PROCESSOR_UNKNOWN,
980 CPU_AVX512_4FMAPS_FLAGS, 0 },
981 { STRING_COMMA_LEN (".avx512_4vnniw"), PROCESSOR_UNKNOWN,
982 CPU_AVX512_4VNNIW_FLAGS, 0 },
983 { STRING_COMMA_LEN (".avx512_vpopcntdq"), PROCESSOR_UNKNOWN,
984 CPU_AVX512_VPOPCNTDQ_FLAGS, 0 },
985 { STRING_COMMA_LEN (".avx512_vbmi2"), PROCESSOR_UNKNOWN,
986 CPU_AVX512_VBMI2_FLAGS, 0 },
987 { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN,
988 CPU_CLZERO_FLAGS, 0 },
989 { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN,
990 CPU_MWAITX_FLAGS, 0 },
991 { STRING_COMMA_LEN (".ospke"), PROCESSOR_UNKNOWN,
992 CPU_OSPKE_FLAGS, 0 },
993 { STRING_COMMA_LEN (".rdpid"), PROCESSOR_UNKNOWN,
994 CPU_RDPID_FLAGS, 0 },
995 { STRING_COMMA_LEN (".ptwrite"), PROCESSOR_UNKNOWN,
996 CPU_PTWRITE_FLAGS, 0 },
997 { STRING_COMMA_LEN (".cet"), PROCESSOR_UNKNOWN,
998 CPU_CET_FLAGS, 0 },
999 };
1000
1001 static const noarch_entry cpu_noarch[] =
1002 {
1003 { STRING_COMMA_LEN ("no87"), CPU_ANY_X87_FLAGS },
1004 { STRING_COMMA_LEN ("no287"), CPU_ANY_287_FLAGS },
1005 { STRING_COMMA_LEN ("no387"), CPU_ANY_387_FLAGS },
1006 { STRING_COMMA_LEN ("no687"), CPU_ANY_687_FLAGS },
1007 { STRING_COMMA_LEN ("nommx"), CPU_ANY_MMX_FLAGS },
1008 { STRING_COMMA_LEN ("nosse"), CPU_ANY_SSE_FLAGS },
1009 { STRING_COMMA_LEN ("nosse2"), CPU_ANY_SSE2_FLAGS },
1010 { STRING_COMMA_LEN ("nosse3"), CPU_ANY_SSE3_FLAGS },
1011 { STRING_COMMA_LEN ("nossse3"), CPU_ANY_SSSE3_FLAGS },
1012 { STRING_COMMA_LEN ("nosse4.1"), CPU_ANY_SSE4_1_FLAGS },
1013 { STRING_COMMA_LEN ("nosse4.2"), CPU_ANY_SSE4_2_FLAGS },
1014 { STRING_COMMA_LEN ("nosse4"), CPU_ANY_SSE4_1_FLAGS },
1015 { STRING_COMMA_LEN ("noavx"), CPU_ANY_AVX_FLAGS },
1016 { STRING_COMMA_LEN ("noavx2"), CPU_ANY_AVX2_FLAGS },
1017 { STRING_COMMA_LEN ("noavx512f"), CPU_ANY_AVX512F_FLAGS },
1018 { STRING_COMMA_LEN ("noavx512cd"), CPU_ANY_AVX512CD_FLAGS },
1019 { STRING_COMMA_LEN ("noavx512er"), CPU_ANY_AVX512ER_FLAGS },
1020 { STRING_COMMA_LEN ("noavx512pf"), CPU_ANY_AVX512PF_FLAGS },
1021 { STRING_COMMA_LEN ("noavx512dq"), CPU_ANY_AVX512DQ_FLAGS },
1022 { STRING_COMMA_LEN ("noavx512bw"), CPU_ANY_AVX512BW_FLAGS },
1023 { STRING_COMMA_LEN ("noavx512vl"), CPU_ANY_AVX512VL_FLAGS },
1024 { STRING_COMMA_LEN ("noavx512ifma"), CPU_ANY_AVX512IFMA_FLAGS },
1025 { STRING_COMMA_LEN ("noavx512vbmi"), CPU_ANY_AVX512VBMI_FLAGS },
1026 { STRING_COMMA_LEN ("noavx512_4fmaps"), CPU_ANY_AVX512_4FMAPS_FLAGS },
1027 { STRING_COMMA_LEN ("noavx512_4vnniw"), CPU_ANY_AVX512_4VNNIW_FLAGS },
1028 { STRING_COMMA_LEN ("noavx512_vpopcntdq"), CPU_ANY_AVX512_VPOPCNTDQ_FLAGS },
1029 { STRING_COMMA_LEN ("noavx512_vbmi2"), CPU_ANY_AVX512_VBMI2_FLAGS },
1030 };
1031
1032 #ifdef I386COFF
1033 /* Like s_lcomm_internal in gas/read.c but the alignment string
1034 is allowed to be optional. */
1035
1036 static symbolS *
1037 pe_lcomm_internal (int needs_align, symbolS *symbolP, addressT size)
1038 {
1039 addressT align = 0;
1040
1041 SKIP_WHITESPACE ();
1042
1043 if (needs_align
1044 && *input_line_pointer == ',')
1045 {
1046 align = parse_align (needs_align - 1);
1047
1048 if (align == (addressT) -1)
1049 return NULL;
1050 }
1051 else
1052 {
1053 if (size >= 8)
1054 align = 3;
1055 else if (size >= 4)
1056 align = 2;
1057 else if (size >= 2)
1058 align = 1;
1059 else
1060 align = 0;
1061 }
1062
1063 bss_alloc (symbolP, size, align);
1064 return symbolP;
1065 }
1066
1067 static void
1068 pe_lcomm (int needs_align)
1069 {
1070 s_comm_internal (needs_align * 2, pe_lcomm_internal);
1071 }
1072 #endif
1073
1074 const pseudo_typeS md_pseudo_table[] =
1075 {
1076 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
1077 {"align", s_align_bytes, 0},
1078 #else
1079 {"align", s_align_ptwo, 0},
1080 #endif
1081 {"arch", set_cpu_arch, 0},
1082 #ifndef I386COFF
1083 {"bss", s_bss, 0},
1084 #else
1085 {"lcomm", pe_lcomm, 1},
1086 #endif
1087 {"ffloat", float_cons, 'f'},
1088 {"dfloat", float_cons, 'd'},
1089 {"tfloat", float_cons, 'x'},
1090 {"value", cons, 2},
1091 {"slong", signed_cons, 4},
1092 {"noopt", s_ignore, 0},
1093 {"optim", s_ignore, 0},
1094 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
1095 {"code16", set_code_flag, CODE_16BIT},
1096 {"code32", set_code_flag, CODE_32BIT},
1097 {"code64", set_code_flag, CODE_64BIT},
1098 {"intel_syntax", set_intel_syntax, 1},
1099 {"att_syntax", set_intel_syntax, 0},
1100 {"intel_mnemonic", set_intel_mnemonic, 1},
1101 {"att_mnemonic", set_intel_mnemonic, 0},
1102 {"allow_index_reg", set_allow_index_reg, 1},
1103 {"disallow_index_reg", set_allow_index_reg, 0},
1104 {"sse_check", set_check, 0},
1105 {"operand_check", set_check, 1},
1106 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1107 {"largecomm", handle_large_common, 0},
1108 #else
1109 {"file", (void (*) (int)) dwarf2_directive_file, 0},
1110 {"loc", dwarf2_directive_loc, 0},
1111 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
1112 #endif
1113 #ifdef TE_PE
1114 {"secrel32", pe_directive_secrel, 0},
1115 #endif
1116 {0, 0, 0}
1117 };
1118
1119 /* For interface with expression (). */
1120 extern char *input_line_pointer;
1121
1122 /* Hash table for instruction mnemonic lookup. */
1123 static struct hash_control *op_hash;
1124
1125 /* Hash table for register lookup. */
1126 static struct hash_control *reg_hash;
1127 \f
1128 void
1129 i386_align_code (fragS *fragP, int count)
1130 {
1131 /* Various efficient no-op patterns for aligning code labels.
1132 Note: Don't try to assemble the instructions in the comments.
1133 0L and 0w are not legal. */
1134 static const unsigned char f32_1[] =
1135 {0x90}; /* nop */
1136 static const unsigned char f32_2[] =
1137 {0x66,0x90}; /* xchg %ax,%ax */
1138 static const unsigned char f32_3[] =
1139 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1140 static const unsigned char f32_4[] =
1141 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1142 static const unsigned char f32_5[] =
1143 {0x90, /* nop */
1144 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1145 static const unsigned char f32_6[] =
1146 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1147 static const unsigned char f32_7[] =
1148 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1149 static const unsigned char f32_8[] =
1150 {0x90, /* nop */
1151 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1152 static const unsigned char f32_9[] =
1153 {0x89,0xf6, /* movl %esi,%esi */
1154 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1155 static const unsigned char f32_10[] =
1156 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
1157 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1158 static const unsigned char f32_11[] =
1159 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
1160 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1161 static const unsigned char f32_12[] =
1162 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1163 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
1164 static const unsigned char f32_13[] =
1165 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1166 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1167 static const unsigned char f32_14[] =
1168 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
1169 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1170 static const unsigned char f16_3[] =
1171 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
1172 static const unsigned char f16_4[] =
1173 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
1174 static const unsigned char f16_5[] =
1175 {0x90, /* nop */
1176 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
1177 static const unsigned char f16_6[] =
1178 {0x89,0xf6, /* mov %si,%si */
1179 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1180 static const unsigned char f16_7[] =
1181 {0x8d,0x74,0x00, /* lea 0(%si),%si */
1182 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1183 static const unsigned char f16_8[] =
1184 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
1185 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1186 static const unsigned char jump_31[] =
1187 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
1188 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1189 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1190 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
1191 static const unsigned char *const f32_patt[] = {
1192 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
1193 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14
1194 };
1195 static const unsigned char *const f16_patt[] = {
1196 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8
1197 };
1198 /* nopl (%[re]ax) */
1199 static const unsigned char alt_3[] =
1200 {0x0f,0x1f,0x00};
1201 /* nopl 0(%[re]ax) */
1202 static const unsigned char alt_4[] =
1203 {0x0f,0x1f,0x40,0x00};
1204 /* nopl 0(%[re]ax,%[re]ax,1) */
1205 static const unsigned char alt_5[] =
1206 {0x0f,0x1f,0x44,0x00,0x00};
1207 /* nopw 0(%[re]ax,%[re]ax,1) */
1208 static const unsigned char alt_6[] =
1209 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1210 /* nopl 0L(%[re]ax) */
1211 static const unsigned char alt_7[] =
1212 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1213 /* nopl 0L(%[re]ax,%[re]ax,1) */
1214 static const unsigned char alt_8[] =
1215 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1216 /* nopw 0L(%[re]ax,%[re]ax,1) */
1217 static const unsigned char alt_9[] =
1218 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1219 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1220 static const unsigned char alt_10[] =
1221 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1222 static const unsigned char *const alt_patt[] = {
1223 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
1224 alt_9, alt_10
1225 };
1226
1227 /* Only align for at least a positive non-zero boundary. */
1228 if (count <= 0 || count > MAX_MEM_FOR_RS_ALIGN_CODE)
1229 return;
1230
1231 /* We need to decide which NOP sequence to use for 32bit and
1232 64bit. When -mtune= is used:
1233
1234 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1235 PROCESSOR_GENERIC32, f32_patt will be used.
1236 2. For the rest, alt_patt will be used.
1237
1238 When -mtune= isn't used, alt_patt will be used if
1239 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
1240 be used.
1241
1242 When -march= or .arch is used, we can't use anything beyond
1243 cpu_arch_isa_flags. */
1244
1245 if (flag_code == CODE_16BIT)
1246 {
1247 if (count > 8)
1248 {
1249 memcpy (fragP->fr_literal + fragP->fr_fix,
1250 jump_31, count);
1251 /* Adjust jump offset. */
1252 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
1253 }
1254 else
1255 memcpy (fragP->fr_literal + fragP->fr_fix,
1256 f16_patt[count - 1], count);
1257 }
1258 else
1259 {
1260 const unsigned char *const *patt = NULL;
1261
1262 if (fragP->tc_frag_data.isa == PROCESSOR_UNKNOWN)
1263 {
1264 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1265 switch (cpu_arch_tune)
1266 {
1267 case PROCESSOR_UNKNOWN:
1268 /* We use cpu_arch_isa_flags to check if we SHOULD
1269 optimize with nops. */
1270 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
1271 patt = alt_patt;
1272 else
1273 patt = f32_patt;
1274 break;
1275 case PROCESSOR_PENTIUM4:
1276 case PROCESSOR_NOCONA:
1277 case PROCESSOR_CORE:
1278 case PROCESSOR_CORE2:
1279 case PROCESSOR_COREI7:
1280 case PROCESSOR_L1OM:
1281 case PROCESSOR_K1OM:
1282 case PROCESSOR_GENERIC64:
1283 case PROCESSOR_K6:
1284 case PROCESSOR_ATHLON:
1285 case PROCESSOR_K8:
1286 case PROCESSOR_AMDFAM10:
1287 case PROCESSOR_BD:
1288 case PROCESSOR_ZNVER:
1289 case PROCESSOR_BT:
1290 patt = alt_patt;
1291 break;
1292 case PROCESSOR_I386:
1293 case PROCESSOR_I486:
1294 case PROCESSOR_PENTIUM:
1295 case PROCESSOR_PENTIUMPRO:
1296 case PROCESSOR_IAMCU:
1297 case PROCESSOR_GENERIC32:
1298 patt = f32_patt;
1299 break;
1300 }
1301 }
1302 else
1303 {
1304 switch (fragP->tc_frag_data.tune)
1305 {
1306 case PROCESSOR_UNKNOWN:
1307 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1308 PROCESSOR_UNKNOWN. */
1309 abort ();
1310 break;
1311
1312 case PROCESSOR_I386:
1313 case PROCESSOR_I486:
1314 case PROCESSOR_PENTIUM:
1315 case PROCESSOR_IAMCU:
1316 case PROCESSOR_K6:
1317 case PROCESSOR_ATHLON:
1318 case PROCESSOR_K8:
1319 case PROCESSOR_AMDFAM10:
1320 case PROCESSOR_BD:
1321 case PROCESSOR_ZNVER:
1322 case PROCESSOR_BT:
1323 case PROCESSOR_GENERIC32:
1324 /* We use cpu_arch_isa_flags to check if we CAN optimize
1325 with nops. */
1326 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
1327 patt = alt_patt;
1328 else
1329 patt = f32_patt;
1330 break;
1331 case PROCESSOR_PENTIUMPRO:
1332 case PROCESSOR_PENTIUM4:
1333 case PROCESSOR_NOCONA:
1334 case PROCESSOR_CORE:
1335 case PROCESSOR_CORE2:
1336 case PROCESSOR_COREI7:
1337 case PROCESSOR_L1OM:
1338 case PROCESSOR_K1OM:
1339 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
1340 patt = alt_patt;
1341 else
1342 patt = f32_patt;
1343 break;
1344 case PROCESSOR_GENERIC64:
1345 patt = alt_patt;
1346 break;
1347 }
1348 }
1349
1350 if (patt == f32_patt)
1351 {
1352 /* If the padding is less than 15 bytes, we use the normal
1353 ones. Otherwise, we use a jump instruction and adjust
1354 its offset. */
1355 int limit;
1356
1357 /* For 64bit, the limit is 3 bytes. */
1358 if (flag_code == CODE_64BIT
1359 && fragP->tc_frag_data.isa_flags.bitfield.cpulm)
1360 limit = 3;
1361 else
1362 limit = 15;
1363 if (count < limit)
1364 memcpy (fragP->fr_literal + fragP->fr_fix,
1365 patt[count - 1], count);
1366 else
1367 {
1368 memcpy (fragP->fr_literal + fragP->fr_fix,
1369 jump_31, count);
1370 /* Adjust jump offset. */
1371 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
1372 }
1373 }
1374 else
1375 {
1376 /* Maximum length of an instruction is 10 byte. If the
1377 padding is greater than 10 bytes and we don't use jump,
1378 we have to break it into smaller pieces. */
1379 int padding = count;
1380 while (padding > 10)
1381 {
1382 padding -= 10;
1383 memcpy (fragP->fr_literal + fragP->fr_fix + padding,
1384 patt [9], 10);
1385 }
1386
1387 if (padding)
1388 memcpy (fragP->fr_literal + fragP->fr_fix,
1389 patt [padding - 1], padding);
1390 }
1391 }
1392 fragP->fr_var = count;
1393 }
1394
1395 static INLINE int
1396 operand_type_all_zero (const union i386_operand_type *x)
1397 {
1398 switch (ARRAY_SIZE(x->array))
1399 {
1400 case 3:
1401 if (x->array[2])
1402 return 0;
1403 /* Fall through. */
1404 case 2:
1405 if (x->array[1])
1406 return 0;
1407 /* Fall through. */
1408 case 1:
1409 return !x->array[0];
1410 default:
1411 abort ();
1412 }
1413 }
1414
1415 static INLINE void
1416 operand_type_set (union i386_operand_type *x, unsigned int v)
1417 {
1418 switch (ARRAY_SIZE(x->array))
1419 {
1420 case 3:
1421 x->array[2] = v;
1422 /* Fall through. */
1423 case 2:
1424 x->array[1] = v;
1425 /* Fall through. */
1426 case 1:
1427 x->array[0] = v;
1428 /* Fall through. */
1429 break;
1430 default:
1431 abort ();
1432 }
1433 }
1434
1435 static INLINE int
1436 operand_type_equal (const union i386_operand_type *x,
1437 const union i386_operand_type *y)
1438 {
1439 switch (ARRAY_SIZE(x->array))
1440 {
1441 case 3:
1442 if (x->array[2] != y->array[2])
1443 return 0;
1444 /* Fall through. */
1445 case 2:
1446 if (x->array[1] != y->array[1])
1447 return 0;
1448 /* Fall through. */
1449 case 1:
1450 return x->array[0] == y->array[0];
1451 break;
1452 default:
1453 abort ();
1454 }
1455 }
1456
1457 static INLINE int
1458 cpu_flags_all_zero (const union i386_cpu_flags *x)
1459 {
1460 switch (ARRAY_SIZE(x->array))
1461 {
1462 case 4:
1463 if (x->array[3])
1464 return 0;
1465 /* Fall through. */
1466 case 3:
1467 if (x->array[2])
1468 return 0;
1469 /* Fall through. */
1470 case 2:
1471 if (x->array[1])
1472 return 0;
1473 /* Fall through. */
1474 case 1:
1475 return !x->array[0];
1476 default:
1477 abort ();
1478 }
1479 }
1480
1481 static INLINE int
1482 cpu_flags_equal (const union i386_cpu_flags *x,
1483 const union i386_cpu_flags *y)
1484 {
1485 switch (ARRAY_SIZE(x->array))
1486 {
1487 case 4:
1488 if (x->array[3] != y->array[3])
1489 return 0;
1490 /* Fall through. */
1491 case 3:
1492 if (x->array[2] != y->array[2])
1493 return 0;
1494 /* Fall through. */
1495 case 2:
1496 if (x->array[1] != y->array[1])
1497 return 0;
1498 /* Fall through. */
1499 case 1:
1500 return x->array[0] == y->array[0];
1501 break;
1502 default:
1503 abort ();
1504 }
1505 }
1506
1507 static INLINE int
1508 cpu_flags_check_cpu64 (i386_cpu_flags f)
1509 {
1510 return !((flag_code == CODE_64BIT && f.bitfield.cpuno64)
1511 || (flag_code != CODE_64BIT && f.bitfield.cpu64));
1512 }
1513
1514 static INLINE i386_cpu_flags
1515 cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y)
1516 {
1517 switch (ARRAY_SIZE (x.array))
1518 {
1519 case 4:
1520 x.array [3] &= y.array [3];
1521 /* Fall through. */
1522 case 3:
1523 x.array [2] &= y.array [2];
1524 /* Fall through. */
1525 case 2:
1526 x.array [1] &= y.array [1];
1527 /* Fall through. */
1528 case 1:
1529 x.array [0] &= y.array [0];
1530 break;
1531 default:
1532 abort ();
1533 }
1534 return x;
1535 }
1536
1537 static INLINE i386_cpu_flags
1538 cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y)
1539 {
1540 switch (ARRAY_SIZE (x.array))
1541 {
1542 case 4:
1543 x.array [3] |= y.array [3];
1544 /* Fall through. */
1545 case 3:
1546 x.array [2] |= y.array [2];
1547 /* Fall through. */
1548 case 2:
1549 x.array [1] |= y.array [1];
1550 /* Fall through. */
1551 case 1:
1552 x.array [0] |= y.array [0];
1553 break;
1554 default:
1555 abort ();
1556 }
1557 return x;
1558 }
1559
1560 static INLINE i386_cpu_flags
1561 cpu_flags_and_not (i386_cpu_flags x, i386_cpu_flags y)
1562 {
1563 switch (ARRAY_SIZE (x.array))
1564 {
1565 case 4:
1566 x.array [3] &= ~y.array [3];
1567 /* Fall through. */
1568 case 3:
1569 x.array [2] &= ~y.array [2];
1570 /* Fall through. */
1571 case 2:
1572 x.array [1] &= ~y.array [1];
1573 /* Fall through. */
1574 case 1:
1575 x.array [0] &= ~y.array [0];
1576 break;
1577 default:
1578 abort ();
1579 }
1580 return x;
1581 }
1582
1583 #define CPU_FLAGS_ARCH_MATCH 0x1
1584 #define CPU_FLAGS_64BIT_MATCH 0x2
1585 #define CPU_FLAGS_AES_MATCH 0x4
1586 #define CPU_FLAGS_PCLMUL_MATCH 0x8
1587 #define CPU_FLAGS_AVX_MATCH 0x10
1588
1589 #define CPU_FLAGS_32BIT_MATCH \
1590 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH \
1591 | CPU_FLAGS_PCLMUL_MATCH | CPU_FLAGS_AVX_MATCH)
1592 #define CPU_FLAGS_PERFECT_MATCH \
1593 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)
1594
1595 /* Return CPU flags match bits. */
1596
1597 static int
1598 cpu_flags_match (const insn_template *t)
1599 {
1600 i386_cpu_flags x = t->cpu_flags;
1601 int match = cpu_flags_check_cpu64 (x) ? CPU_FLAGS_64BIT_MATCH : 0;
1602
1603 x.bitfield.cpu64 = 0;
1604 x.bitfield.cpuno64 = 0;
1605
1606 if (cpu_flags_all_zero (&x))
1607 {
1608 /* This instruction is available on all archs. */
1609 match |= CPU_FLAGS_32BIT_MATCH;
1610 }
1611 else
1612 {
1613 /* This instruction is available only on some archs. */
1614 i386_cpu_flags cpu = cpu_arch_flags;
1615
1616 cpu = cpu_flags_and (x, cpu);
1617 if (!cpu_flags_all_zero (&cpu))
1618 {
1619 if (x.bitfield.cpuavx)
1620 {
1621 /* We only need to check AES/PCLMUL/SSE2AVX with AVX. */
1622 if (cpu.bitfield.cpuavx)
1623 {
1624 /* Check SSE2AVX. */
1625 if (!t->opcode_modifier.sse2avx|| sse2avx)
1626 {
1627 match |= (CPU_FLAGS_ARCH_MATCH
1628 | CPU_FLAGS_AVX_MATCH);
1629 /* Check AES. */
1630 if (!x.bitfield.cpuaes || cpu.bitfield.cpuaes)
1631 match |= CPU_FLAGS_AES_MATCH;
1632 /* Check PCLMUL. */
1633 if (!x.bitfield.cpupclmul
1634 || cpu.bitfield.cpupclmul)
1635 match |= CPU_FLAGS_PCLMUL_MATCH;
1636 }
1637 }
1638 else
1639 match |= CPU_FLAGS_ARCH_MATCH;
1640 }
1641 else if (x.bitfield.cpuavx512vl)
1642 {
1643 /* Match AVX512VL. */
1644 if (cpu.bitfield.cpuavx512vl)
1645 {
1646 /* Need another match. */
1647 cpu.bitfield.cpuavx512vl = 0;
1648 if (!cpu_flags_all_zero (&cpu))
1649 match |= CPU_FLAGS_32BIT_MATCH;
1650 else
1651 match |= CPU_FLAGS_ARCH_MATCH;
1652 }
1653 else
1654 match |= CPU_FLAGS_ARCH_MATCH;
1655 }
1656 else
1657 match |= CPU_FLAGS_32BIT_MATCH;
1658 }
1659 }
1660 return match;
1661 }
1662
1663 static INLINE i386_operand_type
1664 operand_type_and (i386_operand_type x, i386_operand_type y)
1665 {
1666 switch (ARRAY_SIZE (x.array))
1667 {
1668 case 3:
1669 x.array [2] &= y.array [2];
1670 /* Fall through. */
1671 case 2:
1672 x.array [1] &= y.array [1];
1673 /* Fall through. */
1674 case 1:
1675 x.array [0] &= y.array [0];
1676 break;
1677 default:
1678 abort ();
1679 }
1680 return x;
1681 }
1682
1683 static INLINE i386_operand_type
1684 operand_type_or (i386_operand_type x, i386_operand_type y)
1685 {
1686 switch (ARRAY_SIZE (x.array))
1687 {
1688 case 3:
1689 x.array [2] |= y.array [2];
1690 /* Fall through. */
1691 case 2:
1692 x.array [1] |= y.array [1];
1693 /* Fall through. */
1694 case 1:
1695 x.array [0] |= y.array [0];
1696 break;
1697 default:
1698 abort ();
1699 }
1700 return x;
1701 }
1702
1703 static INLINE i386_operand_type
1704 operand_type_xor (i386_operand_type x, i386_operand_type y)
1705 {
1706 switch (ARRAY_SIZE (x.array))
1707 {
1708 case 3:
1709 x.array [2] ^= y.array [2];
1710 /* Fall through. */
1711 case 2:
1712 x.array [1] ^= y.array [1];
1713 /* Fall through. */
1714 case 1:
1715 x.array [0] ^= y.array [0];
1716 break;
1717 default:
1718 abort ();
1719 }
1720 return x;
1721 }
1722
1723 static const i386_operand_type acc32 = OPERAND_TYPE_ACC32;
1724 static const i386_operand_type acc64 = OPERAND_TYPE_ACC64;
1725 static const i386_operand_type control = OPERAND_TYPE_CONTROL;
1726 static const i386_operand_type inoutportreg
1727 = OPERAND_TYPE_INOUTPORTREG;
1728 static const i386_operand_type reg16_inoutportreg
1729 = OPERAND_TYPE_REG16_INOUTPORTREG;
1730 static const i386_operand_type disp16 = OPERAND_TYPE_DISP16;
1731 static const i386_operand_type disp32 = OPERAND_TYPE_DISP32;
1732 static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S;
1733 static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32;
1734 static const i386_operand_type anydisp
1735 = OPERAND_TYPE_ANYDISP;
1736 static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM;
1737 static const i386_operand_type regymm = OPERAND_TYPE_REGYMM;
1738 static const i386_operand_type regzmm = OPERAND_TYPE_REGZMM;
1739 static const i386_operand_type regmask = OPERAND_TYPE_REGMASK;
1740 static const i386_operand_type imm8 = OPERAND_TYPE_IMM8;
1741 static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S;
1742 static const i386_operand_type imm16 = OPERAND_TYPE_IMM16;
1743 static const i386_operand_type imm32 = OPERAND_TYPE_IMM32;
1744 static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S;
1745 static const i386_operand_type imm64 = OPERAND_TYPE_IMM64;
1746 static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32;
1747 static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S;
1748 static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S;
1749 static const i386_operand_type vec_imm4 = OPERAND_TYPE_VEC_IMM4;
1750
1751 enum operand_type
1752 {
1753 reg,
1754 imm,
1755 disp,
1756 anymem
1757 };
1758
1759 static INLINE int
1760 operand_type_check (i386_operand_type t, enum operand_type c)
1761 {
1762 switch (c)
1763 {
1764 case reg:
1765 return (t.bitfield.reg8
1766 || t.bitfield.reg16
1767 || t.bitfield.reg32
1768 || t.bitfield.reg64);
1769
1770 case imm:
1771 return (t.bitfield.imm8
1772 || t.bitfield.imm8s
1773 || t.bitfield.imm16
1774 || t.bitfield.imm32
1775 || t.bitfield.imm32s
1776 || t.bitfield.imm64);
1777
1778 case disp:
1779 return (t.bitfield.disp8
1780 || t.bitfield.disp16
1781 || t.bitfield.disp32
1782 || t.bitfield.disp32s
1783 || t.bitfield.disp64);
1784
1785 case anymem:
1786 return (t.bitfield.disp8
1787 || t.bitfield.disp16
1788 || t.bitfield.disp32
1789 || t.bitfield.disp32s
1790 || t.bitfield.disp64
1791 || t.bitfield.baseindex);
1792
1793 default:
1794 abort ();
1795 }
1796
1797 return 0;
1798 }
1799
1800 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1801 operand J for instruction template T. */
1802
1803 static INLINE int
1804 match_reg_size (const insn_template *t, unsigned int j)
1805 {
1806 return !((i.types[j].bitfield.byte
1807 && !t->operand_types[j].bitfield.byte)
1808 || (i.types[j].bitfield.word
1809 && !t->operand_types[j].bitfield.word)
1810 || (i.types[j].bitfield.dword
1811 && !t->operand_types[j].bitfield.dword)
1812 || (i.types[j].bitfield.qword
1813 && !t->operand_types[j].bitfield.qword));
1814 }
1815
1816 /* Return 1 if there is no conflict in any size on operand J for
1817 instruction template T. */
1818
1819 static INLINE int
1820 match_mem_size (const insn_template *t, unsigned int j)
1821 {
1822 return (match_reg_size (t, j)
1823 && !((i.types[j].bitfield.unspecified
1824 && !i.broadcast
1825 && !t->operand_types[j].bitfield.unspecified)
1826 || (i.types[j].bitfield.fword
1827 && !t->operand_types[j].bitfield.fword)
1828 || (i.types[j].bitfield.tbyte
1829 && !t->operand_types[j].bitfield.tbyte)
1830 || (i.types[j].bitfield.xmmword
1831 && !t->operand_types[j].bitfield.xmmword)
1832 || (i.types[j].bitfield.ymmword
1833 && !t->operand_types[j].bitfield.ymmword)
1834 || (i.types[j].bitfield.zmmword
1835 && !t->operand_types[j].bitfield.zmmword)));
1836 }
1837
1838 /* Return 1 if there is no size conflict on any operands for
1839 instruction template T. */
1840
1841 static INLINE int
1842 operand_size_match (const insn_template *t)
1843 {
1844 unsigned int j;
1845 int match = 1;
1846
1847 /* Don't check jump instructions. */
1848 if (t->opcode_modifier.jump
1849 || t->opcode_modifier.jumpbyte
1850 || t->opcode_modifier.jumpdword
1851 || t->opcode_modifier.jumpintersegment)
1852 return match;
1853
1854 /* Check memory and accumulator operand size. */
1855 for (j = 0; j < i.operands; j++)
1856 {
1857 if (t->operand_types[j].bitfield.anysize)
1858 continue;
1859
1860 if (t->operand_types[j].bitfield.acc && !match_reg_size (t, j))
1861 {
1862 match = 0;
1863 break;
1864 }
1865
1866 if (i.types[j].bitfield.mem && !match_mem_size (t, j))
1867 {
1868 match = 0;
1869 break;
1870 }
1871 }
1872
1873 if (match)
1874 return match;
1875 else if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
1876 {
1877 mismatch:
1878 i.error = operand_size_mismatch;
1879 return 0;
1880 }
1881
1882 /* Check reverse. */
1883 gas_assert (i.operands == 2);
1884
1885 match = 1;
1886 for (j = 0; j < 2; j++)
1887 {
1888 if (t->operand_types[j].bitfield.acc
1889 && !match_reg_size (t, j ? 0 : 1))
1890 goto mismatch;
1891
1892 if (i.types[j].bitfield.mem
1893 && !match_mem_size (t, j ? 0 : 1))
1894 goto mismatch;
1895 }
1896
1897 return match;
1898 }
1899
1900 static INLINE int
1901 operand_type_match (i386_operand_type overlap,
1902 i386_operand_type given)
1903 {
1904 i386_operand_type temp = overlap;
1905
1906 temp.bitfield.jumpabsolute = 0;
1907 temp.bitfield.unspecified = 0;
1908 temp.bitfield.byte = 0;
1909 temp.bitfield.word = 0;
1910 temp.bitfield.dword = 0;
1911 temp.bitfield.fword = 0;
1912 temp.bitfield.qword = 0;
1913 temp.bitfield.tbyte = 0;
1914 temp.bitfield.xmmword = 0;
1915 temp.bitfield.ymmword = 0;
1916 temp.bitfield.zmmword = 0;
1917 if (operand_type_all_zero (&temp))
1918 goto mismatch;
1919
1920 if (given.bitfield.baseindex == overlap.bitfield.baseindex
1921 && given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute)
1922 return 1;
1923
1924 mismatch:
1925 i.error = operand_type_mismatch;
1926 return 0;
1927 }
1928
1929 /* If given types g0 and g1 are registers they must be of the same type
1930 unless the expected operand type register overlap is null.
1931 Note that Acc in a template matches every size of reg. */
1932
1933 static INLINE int
1934 operand_type_register_match (i386_operand_type m0,
1935 i386_operand_type g0,
1936 i386_operand_type t0,
1937 i386_operand_type m1,
1938 i386_operand_type g1,
1939 i386_operand_type t1)
1940 {
1941 if (!operand_type_check (g0, reg))
1942 return 1;
1943
1944 if (!operand_type_check (g1, reg))
1945 return 1;
1946
1947 if (g0.bitfield.reg8 == g1.bitfield.reg8
1948 && g0.bitfield.reg16 == g1.bitfield.reg16
1949 && g0.bitfield.reg32 == g1.bitfield.reg32
1950 && g0.bitfield.reg64 == g1.bitfield.reg64)
1951 return 1;
1952
1953 if (m0.bitfield.acc)
1954 {
1955 t0.bitfield.reg8 = 1;
1956 t0.bitfield.reg16 = 1;
1957 t0.bitfield.reg32 = 1;
1958 t0.bitfield.reg64 = 1;
1959 }
1960
1961 if (m1.bitfield.acc)
1962 {
1963 t1.bitfield.reg8 = 1;
1964 t1.bitfield.reg16 = 1;
1965 t1.bitfield.reg32 = 1;
1966 t1.bitfield.reg64 = 1;
1967 }
1968
1969 if (!(t0.bitfield.reg8 & t1.bitfield.reg8)
1970 && !(t0.bitfield.reg16 & t1.bitfield.reg16)
1971 && !(t0.bitfield.reg32 & t1.bitfield.reg32)
1972 && !(t0.bitfield.reg64 & t1.bitfield.reg64))
1973 return 1;
1974
1975 i.error = register_type_mismatch;
1976
1977 return 0;
1978 }
1979
1980 static INLINE unsigned int
1981 register_number (const reg_entry *r)
1982 {
1983 unsigned int nr = r->reg_num;
1984
1985 if (r->reg_flags & RegRex)
1986 nr += 8;
1987
1988 if (r->reg_flags & RegVRex)
1989 nr += 16;
1990
1991 return nr;
1992 }
1993
1994 static INLINE unsigned int
1995 mode_from_disp_size (i386_operand_type t)
1996 {
1997 if (t.bitfield.disp8 || t.bitfield.vec_disp8)
1998 return 1;
1999 else if (t.bitfield.disp16
2000 || t.bitfield.disp32
2001 || t.bitfield.disp32s)
2002 return 2;
2003 else
2004 return 0;
2005 }
2006
2007 static INLINE int
2008 fits_in_signed_byte (addressT num)
2009 {
2010 return num + 0x80 <= 0xff;
2011 }
2012
2013 static INLINE int
2014 fits_in_unsigned_byte (addressT num)
2015 {
2016 return num <= 0xff;
2017 }
2018
2019 static INLINE int
2020 fits_in_unsigned_word (addressT num)
2021 {
2022 return num <= 0xffff;
2023 }
2024
2025 static INLINE int
2026 fits_in_signed_word (addressT num)
2027 {
2028 return num + 0x8000 <= 0xffff;
2029 }
2030
2031 static INLINE int
2032 fits_in_signed_long (addressT num ATTRIBUTE_UNUSED)
2033 {
2034 #ifndef BFD64
2035 return 1;
2036 #else
2037 return num + 0x80000000 <= 0xffffffff;
2038 #endif
2039 } /* fits_in_signed_long() */
2040
2041 static INLINE int
2042 fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED)
2043 {
2044 #ifndef BFD64
2045 return 1;
2046 #else
2047 return num <= 0xffffffff;
2048 #endif
2049 } /* fits_in_unsigned_long() */
2050
2051 static INLINE int
2052 fits_in_vec_disp8 (offsetT num)
2053 {
2054 int shift = i.memshift;
2055 unsigned int mask;
2056
2057 if (shift == -1)
2058 abort ();
2059
2060 mask = (1 << shift) - 1;
2061
2062 /* Return 0 if NUM isn't properly aligned. */
2063 if ((num & mask))
2064 return 0;
2065
2066 /* Check if NUM will fit in 8bit after shift. */
2067 return fits_in_signed_byte (num >> shift);
2068 }
2069
2070 static INLINE int
2071 fits_in_imm4 (offsetT num)
2072 {
2073 return (num & 0xf) == num;
2074 }
2075
2076 static i386_operand_type
2077 smallest_imm_type (offsetT num)
2078 {
2079 i386_operand_type t;
2080
2081 operand_type_set (&t, 0);
2082 t.bitfield.imm64 = 1;
2083
2084 if (cpu_arch_tune != PROCESSOR_I486 && num == 1)
2085 {
2086 /* This code is disabled on the 486 because all the Imm1 forms
2087 in the opcode table are slower on the i486. They're the
2088 versions with the implicitly specified single-position
2089 displacement, which has another syntax if you really want to
2090 use that form. */
2091 t.bitfield.imm1 = 1;
2092 t.bitfield.imm8 = 1;
2093 t.bitfield.imm8s = 1;
2094 t.bitfield.imm16 = 1;
2095 t.bitfield.imm32 = 1;
2096 t.bitfield.imm32s = 1;
2097 }
2098 else if (fits_in_signed_byte (num))
2099 {
2100 t.bitfield.imm8 = 1;
2101 t.bitfield.imm8s = 1;
2102 t.bitfield.imm16 = 1;
2103 t.bitfield.imm32 = 1;
2104 t.bitfield.imm32s = 1;
2105 }
2106 else if (fits_in_unsigned_byte (num))
2107 {
2108 t.bitfield.imm8 = 1;
2109 t.bitfield.imm16 = 1;
2110 t.bitfield.imm32 = 1;
2111 t.bitfield.imm32s = 1;
2112 }
2113 else if (fits_in_signed_word (num) || fits_in_unsigned_word (num))
2114 {
2115 t.bitfield.imm16 = 1;
2116 t.bitfield.imm32 = 1;
2117 t.bitfield.imm32s = 1;
2118 }
2119 else if (fits_in_signed_long (num))
2120 {
2121 t.bitfield.imm32 = 1;
2122 t.bitfield.imm32s = 1;
2123 }
2124 else if (fits_in_unsigned_long (num))
2125 t.bitfield.imm32 = 1;
2126
2127 return t;
2128 }
2129
2130 static offsetT
2131 offset_in_range (offsetT val, int size)
2132 {
2133 addressT mask;
2134
2135 switch (size)
2136 {
2137 case 1: mask = ((addressT) 1 << 8) - 1; break;
2138 case 2: mask = ((addressT) 1 << 16) - 1; break;
2139 case 4: mask = ((addressT) 2 << 31) - 1; break;
2140 #ifdef BFD64
2141 case 8: mask = ((addressT) 2 << 63) - 1; break;
2142 #endif
2143 default: abort ();
2144 }
2145
2146 #ifdef BFD64
2147 /* If BFD64, sign extend val for 32bit address mode. */
2148 if (flag_code != CODE_64BIT
2149 || i.prefix[ADDR_PREFIX])
2150 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
2151 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
2152 #endif
2153
2154 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
2155 {
2156 char buf1[40], buf2[40];
2157
2158 sprint_value (buf1, val);
2159 sprint_value (buf2, val & mask);
2160 as_warn (_("%s shortened to %s"), buf1, buf2);
2161 }
2162 return val & mask;
2163 }
2164
2165 enum PREFIX_GROUP
2166 {
2167 PREFIX_EXIST = 0,
2168 PREFIX_LOCK,
2169 PREFIX_REP,
2170 PREFIX_DS,
2171 PREFIX_OTHER
2172 };
2173
2174 /* Returns
2175 a. PREFIX_EXIST if attempting to add a prefix where one from the
2176 same class already exists.
2177 b. PREFIX_LOCK if lock prefix is added.
2178 c. PREFIX_REP if rep/repne prefix is added.
2179 d. PREFIX_DS if ds prefix is added.
2180 e. PREFIX_OTHER if other prefix is added.
2181 */
2182
2183 static enum PREFIX_GROUP
2184 add_prefix (unsigned int prefix)
2185 {
2186 enum PREFIX_GROUP ret = PREFIX_OTHER;
2187 unsigned int q;
2188
2189 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
2190 && flag_code == CODE_64BIT)
2191 {
2192 if ((i.prefix[REX_PREFIX] & prefix & REX_W)
2193 || ((i.prefix[REX_PREFIX] & (REX_R | REX_X | REX_B))
2194 && (prefix & (REX_R | REX_X | REX_B))))
2195 ret = PREFIX_EXIST;
2196 q = REX_PREFIX;
2197 }
2198 else
2199 {
2200 switch (prefix)
2201 {
2202 default:
2203 abort ();
2204
2205 case DS_PREFIX_OPCODE:
2206 ret = PREFIX_DS;
2207 /* Fall through. */
2208 case CS_PREFIX_OPCODE:
2209 case ES_PREFIX_OPCODE:
2210 case FS_PREFIX_OPCODE:
2211 case GS_PREFIX_OPCODE:
2212 case SS_PREFIX_OPCODE:
2213 q = SEG_PREFIX;
2214 break;
2215
2216 case REPNE_PREFIX_OPCODE:
2217 case REPE_PREFIX_OPCODE:
2218 q = REP_PREFIX;
2219 ret = PREFIX_REP;
2220 break;
2221
2222 case LOCK_PREFIX_OPCODE:
2223 q = LOCK_PREFIX;
2224 ret = PREFIX_LOCK;
2225 break;
2226
2227 case FWAIT_OPCODE:
2228 q = WAIT_PREFIX;
2229 break;
2230
2231 case ADDR_PREFIX_OPCODE:
2232 q = ADDR_PREFIX;
2233 break;
2234
2235 case DATA_PREFIX_OPCODE:
2236 q = DATA_PREFIX;
2237 break;
2238 }
2239 if (i.prefix[q] != 0)
2240 ret = PREFIX_EXIST;
2241 }
2242
2243 if (ret)
2244 {
2245 if (!i.prefix[q])
2246 ++i.prefixes;
2247 i.prefix[q] |= prefix;
2248 }
2249 else
2250 as_bad (_("same type of prefix used twice"));
2251
2252 return ret;
2253 }
2254
2255 static void
2256 update_code_flag (int value, int check)
2257 {
2258 PRINTF_LIKE ((*as_error));
2259
2260 flag_code = (enum flag_code) value;
2261 if (flag_code == CODE_64BIT)
2262 {
2263 cpu_arch_flags.bitfield.cpu64 = 1;
2264 cpu_arch_flags.bitfield.cpuno64 = 0;
2265 }
2266 else
2267 {
2268 cpu_arch_flags.bitfield.cpu64 = 0;
2269 cpu_arch_flags.bitfield.cpuno64 = 1;
2270 }
2271 if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm )
2272 {
2273 if (check)
2274 as_error = as_fatal;
2275 else
2276 as_error = as_bad;
2277 (*as_error) (_("64bit mode not supported on `%s'."),
2278 cpu_arch_name ? cpu_arch_name : default_arch);
2279 }
2280 if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386)
2281 {
2282 if (check)
2283 as_error = as_fatal;
2284 else
2285 as_error = as_bad;
2286 (*as_error) (_("32bit mode not supported on `%s'."),
2287 cpu_arch_name ? cpu_arch_name : default_arch);
2288 }
2289 stackop_size = '\0';
2290 }
2291
2292 static void
2293 set_code_flag (int value)
2294 {
2295 update_code_flag (value, 0);
2296 }
2297
2298 static void
2299 set_16bit_gcc_code_flag (int new_code_flag)
2300 {
2301 flag_code = (enum flag_code) new_code_flag;
2302 if (flag_code != CODE_16BIT)
2303 abort ();
2304 cpu_arch_flags.bitfield.cpu64 = 0;
2305 cpu_arch_flags.bitfield.cpuno64 = 1;
2306 stackop_size = LONG_MNEM_SUFFIX;
2307 }
2308
2309 static void
2310 set_intel_syntax (int syntax_flag)
2311 {
2312 /* Find out if register prefixing is specified. */
2313 int ask_naked_reg = 0;
2314
2315 SKIP_WHITESPACE ();
2316 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2317 {
2318 char *string;
2319 int e = get_symbol_name (&string);
2320
2321 if (strcmp (string, "prefix") == 0)
2322 ask_naked_reg = 1;
2323 else if (strcmp (string, "noprefix") == 0)
2324 ask_naked_reg = -1;
2325 else
2326 as_bad (_("bad argument to syntax directive."));
2327 (void) restore_line_pointer (e);
2328 }
2329 demand_empty_rest_of_line ();
2330
2331 intel_syntax = syntax_flag;
2332
2333 if (ask_naked_reg == 0)
2334 allow_naked_reg = (intel_syntax
2335 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
2336 else
2337 allow_naked_reg = (ask_naked_reg < 0);
2338
2339 expr_set_rank (O_full_ptr, syntax_flag ? 10 : 0);
2340
2341 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
2342 identifier_chars['$'] = intel_syntax ? '$' : 0;
2343 register_prefix = allow_naked_reg ? "" : "%";
2344 }
2345
2346 static void
2347 set_intel_mnemonic (int mnemonic_flag)
2348 {
2349 intel_mnemonic = mnemonic_flag;
2350 }
2351
2352 static void
2353 set_allow_index_reg (int flag)
2354 {
2355 allow_index_reg = flag;
2356 }
2357
2358 static void
2359 set_check (int what)
2360 {
2361 enum check_kind *kind;
2362 const char *str;
2363
2364 if (what)
2365 {
2366 kind = &operand_check;
2367 str = "operand";
2368 }
2369 else
2370 {
2371 kind = &sse_check;
2372 str = "sse";
2373 }
2374
2375 SKIP_WHITESPACE ();
2376
2377 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2378 {
2379 char *string;
2380 int e = get_symbol_name (&string);
2381
2382 if (strcmp (string, "none") == 0)
2383 *kind = check_none;
2384 else if (strcmp (string, "warning") == 0)
2385 *kind = check_warning;
2386 else if (strcmp (string, "error") == 0)
2387 *kind = check_error;
2388 else
2389 as_bad (_("bad argument to %s_check directive."), str);
2390 (void) restore_line_pointer (e);
2391 }
2392 else
2393 as_bad (_("missing argument for %s_check directive"), str);
2394
2395 demand_empty_rest_of_line ();
2396 }
2397
2398 static void
2399 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED,
2400 i386_cpu_flags new_flag ATTRIBUTE_UNUSED)
2401 {
2402 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2403 static const char *arch;
2404
2405 /* Intel LIOM is only supported on ELF. */
2406 if (!IS_ELF)
2407 return;
2408
2409 if (!arch)
2410 {
2411 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2412 use default_arch. */
2413 arch = cpu_arch_name;
2414 if (!arch)
2415 arch = default_arch;
2416 }
2417
2418 /* If we are targeting Intel MCU, we must enable it. */
2419 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_IAMCU
2420 || new_flag.bitfield.cpuiamcu)
2421 return;
2422
2423 /* If we are targeting Intel L1OM, we must enable it. */
2424 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_L1OM
2425 || new_flag.bitfield.cpul1om)
2426 return;
2427
2428 /* If we are targeting Intel K1OM, we must enable it. */
2429 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_K1OM
2430 || new_flag.bitfield.cpuk1om)
2431 return;
2432
2433 as_bad (_("`%s' is not supported on `%s'"), name, arch);
2434 #endif
2435 }
2436
2437 static void
2438 set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
2439 {
2440 SKIP_WHITESPACE ();
2441
2442 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2443 {
2444 char *string;
2445 int e = get_symbol_name (&string);
2446 unsigned int j;
2447 i386_cpu_flags flags;
2448
2449 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
2450 {
2451 if (strcmp (string, cpu_arch[j].name) == 0)
2452 {
2453 check_cpu_arch_compatible (string, cpu_arch[j].flags);
2454
2455 if (*string != '.')
2456 {
2457 cpu_arch_name = cpu_arch[j].name;
2458 cpu_sub_arch_name = NULL;
2459 cpu_arch_flags = cpu_arch[j].flags;
2460 if (flag_code == CODE_64BIT)
2461 {
2462 cpu_arch_flags.bitfield.cpu64 = 1;
2463 cpu_arch_flags.bitfield.cpuno64 = 0;
2464 }
2465 else
2466 {
2467 cpu_arch_flags.bitfield.cpu64 = 0;
2468 cpu_arch_flags.bitfield.cpuno64 = 1;
2469 }
2470 cpu_arch_isa = cpu_arch[j].type;
2471 cpu_arch_isa_flags = cpu_arch[j].flags;
2472 if (!cpu_arch_tune_set)
2473 {
2474 cpu_arch_tune = cpu_arch_isa;
2475 cpu_arch_tune_flags = cpu_arch_isa_flags;
2476 }
2477 break;
2478 }
2479
2480 flags = cpu_flags_or (cpu_arch_flags,
2481 cpu_arch[j].flags);
2482
2483 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
2484 {
2485 if (cpu_sub_arch_name)
2486 {
2487 char *name = cpu_sub_arch_name;
2488 cpu_sub_arch_name = concat (name,
2489 cpu_arch[j].name,
2490 (const char *) NULL);
2491 free (name);
2492 }
2493 else
2494 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
2495 cpu_arch_flags = flags;
2496 cpu_arch_isa_flags = flags;
2497 }
2498 (void) restore_line_pointer (e);
2499 demand_empty_rest_of_line ();
2500 return;
2501 }
2502 }
2503
2504 if (*string == '.' && j >= ARRAY_SIZE (cpu_arch))
2505 {
2506 /* Disable an ISA extension. */
2507 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
2508 if (strcmp (string + 1, cpu_noarch [j].name) == 0)
2509 {
2510 flags = cpu_flags_and_not (cpu_arch_flags,
2511 cpu_noarch[j].flags);
2512 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
2513 {
2514 if (cpu_sub_arch_name)
2515 {
2516 char *name = cpu_sub_arch_name;
2517 cpu_sub_arch_name = concat (name, string,
2518 (const char *) NULL);
2519 free (name);
2520 }
2521 else
2522 cpu_sub_arch_name = xstrdup (string);
2523 cpu_arch_flags = flags;
2524 cpu_arch_isa_flags = flags;
2525 }
2526 (void) restore_line_pointer (e);
2527 demand_empty_rest_of_line ();
2528 return;
2529 }
2530
2531 j = ARRAY_SIZE (cpu_arch);
2532 }
2533
2534 if (j >= ARRAY_SIZE (cpu_arch))
2535 as_bad (_("no such architecture: `%s'"), string);
2536
2537 *input_line_pointer = e;
2538 }
2539 else
2540 as_bad (_("missing cpu architecture"));
2541
2542 no_cond_jump_promotion = 0;
2543 if (*input_line_pointer == ','
2544 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
2545 {
2546 char *string;
2547 char e;
2548
2549 ++input_line_pointer;
2550 e = get_symbol_name (&string);
2551
2552 if (strcmp (string, "nojumps") == 0)
2553 no_cond_jump_promotion = 1;
2554 else if (strcmp (string, "jumps") == 0)
2555 ;
2556 else
2557 as_bad (_("no such architecture modifier: `%s'"), string);
2558
2559 (void) restore_line_pointer (e);
2560 }
2561
2562 demand_empty_rest_of_line ();
2563 }
2564
2565 enum bfd_architecture
2566 i386_arch (void)
2567 {
2568 if (cpu_arch_isa == PROCESSOR_L1OM)
2569 {
2570 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2571 || flag_code != CODE_64BIT)
2572 as_fatal (_("Intel L1OM is 64bit ELF only"));
2573 return bfd_arch_l1om;
2574 }
2575 else if (cpu_arch_isa == PROCESSOR_K1OM)
2576 {
2577 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2578 || flag_code != CODE_64BIT)
2579 as_fatal (_("Intel K1OM is 64bit ELF only"));
2580 return bfd_arch_k1om;
2581 }
2582 else if (cpu_arch_isa == PROCESSOR_IAMCU)
2583 {
2584 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2585 || flag_code == CODE_64BIT)
2586 as_fatal (_("Intel MCU is 32bit ELF only"));
2587 return bfd_arch_iamcu;
2588 }
2589 else
2590 return bfd_arch_i386;
2591 }
2592
2593 unsigned long
2594 i386_mach (void)
2595 {
2596 if (!strncmp (default_arch, "x86_64", 6))
2597 {
2598 if (cpu_arch_isa == PROCESSOR_L1OM)
2599 {
2600 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2601 || default_arch[6] != '\0')
2602 as_fatal (_("Intel L1OM is 64bit ELF only"));
2603 return bfd_mach_l1om;
2604 }
2605 else if (cpu_arch_isa == PROCESSOR_K1OM)
2606 {
2607 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2608 || default_arch[6] != '\0')
2609 as_fatal (_("Intel K1OM is 64bit ELF only"));
2610 return bfd_mach_k1om;
2611 }
2612 else if (default_arch[6] == '\0')
2613 return bfd_mach_x86_64;
2614 else
2615 return bfd_mach_x64_32;
2616 }
2617 else if (!strcmp (default_arch, "i386")
2618 || !strcmp (default_arch, "iamcu"))
2619 {
2620 if (cpu_arch_isa == PROCESSOR_IAMCU)
2621 {
2622 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
2623 as_fatal (_("Intel MCU is 32bit ELF only"));
2624 return bfd_mach_i386_iamcu;
2625 }
2626 else
2627 return bfd_mach_i386_i386;
2628 }
2629 else
2630 as_fatal (_("unknown architecture"));
2631 }
2632 \f
2633 void
2634 md_begin (void)
2635 {
2636 const char *hash_err;
2637
2638 /* Support pseudo prefixes like {disp32}. */
2639 lex_type ['{'] = LEX_BEGIN_NAME;
2640
2641 /* Initialize op_hash hash table. */
2642 op_hash = hash_new ();
2643
2644 {
2645 const insn_template *optab;
2646 templates *core_optab;
2647
2648 /* Setup for loop. */
2649 optab = i386_optab;
2650 core_optab = XNEW (templates);
2651 core_optab->start = optab;
2652
2653 while (1)
2654 {
2655 ++optab;
2656 if (optab->name == NULL
2657 || strcmp (optab->name, (optab - 1)->name) != 0)
2658 {
2659 /* different name --> ship out current template list;
2660 add to hash table; & begin anew. */
2661 core_optab->end = optab;
2662 hash_err = hash_insert (op_hash,
2663 (optab - 1)->name,
2664 (void *) core_optab);
2665 if (hash_err)
2666 {
2667 as_fatal (_("can't hash %s: %s"),
2668 (optab - 1)->name,
2669 hash_err);
2670 }
2671 if (optab->name == NULL)
2672 break;
2673 core_optab = XNEW (templates);
2674 core_optab->start = optab;
2675 }
2676 }
2677 }
2678
2679 /* Initialize reg_hash hash table. */
2680 reg_hash = hash_new ();
2681 {
2682 const reg_entry *regtab;
2683 unsigned int regtab_size = i386_regtab_size;
2684
2685 for (regtab = i386_regtab; regtab_size--; regtab++)
2686 {
2687 hash_err = hash_insert (reg_hash, regtab->reg_name, (void *) regtab);
2688 if (hash_err)
2689 as_fatal (_("can't hash %s: %s"),
2690 regtab->reg_name,
2691 hash_err);
2692 }
2693 }
2694
2695 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
2696 {
2697 int c;
2698 char *p;
2699
2700 for (c = 0; c < 256; c++)
2701 {
2702 if (ISDIGIT (c))
2703 {
2704 digit_chars[c] = c;
2705 mnemonic_chars[c] = c;
2706 register_chars[c] = c;
2707 operand_chars[c] = c;
2708 }
2709 else if (ISLOWER (c))
2710 {
2711 mnemonic_chars[c] = c;
2712 register_chars[c] = c;
2713 operand_chars[c] = c;
2714 }
2715 else if (ISUPPER (c))
2716 {
2717 mnemonic_chars[c] = TOLOWER (c);
2718 register_chars[c] = mnemonic_chars[c];
2719 operand_chars[c] = c;
2720 }
2721 else if (c == '{' || c == '}')
2722 {
2723 mnemonic_chars[c] = c;
2724 operand_chars[c] = c;
2725 }
2726
2727 if (ISALPHA (c) || ISDIGIT (c))
2728 identifier_chars[c] = c;
2729 else if (c >= 128)
2730 {
2731 identifier_chars[c] = c;
2732 operand_chars[c] = c;
2733 }
2734 }
2735
2736 #ifdef LEX_AT
2737 identifier_chars['@'] = '@';
2738 #endif
2739 #ifdef LEX_QM
2740 identifier_chars['?'] = '?';
2741 operand_chars['?'] = '?';
2742 #endif
2743 digit_chars['-'] = '-';
2744 mnemonic_chars['_'] = '_';
2745 mnemonic_chars['-'] = '-';
2746 mnemonic_chars['.'] = '.';
2747 identifier_chars['_'] = '_';
2748 identifier_chars['.'] = '.';
2749
2750 for (p = operand_special_chars; *p != '\0'; p++)
2751 operand_chars[(unsigned char) *p] = *p;
2752 }
2753
2754 if (flag_code == CODE_64BIT)
2755 {
2756 #if defined (OBJ_COFF) && defined (TE_PE)
2757 x86_dwarf2_return_column = (OUTPUT_FLAVOR == bfd_target_coff_flavour
2758 ? 32 : 16);
2759 #else
2760 x86_dwarf2_return_column = 16;
2761 #endif
2762 x86_cie_data_alignment = -8;
2763 }
2764 else
2765 {
2766 x86_dwarf2_return_column = 8;
2767 x86_cie_data_alignment = -4;
2768 }
2769 }
2770
2771 void
2772 i386_print_statistics (FILE *file)
2773 {
2774 hash_print_statistics (file, "i386 opcode", op_hash);
2775 hash_print_statistics (file, "i386 register", reg_hash);
2776 }
2777 \f
2778 #ifdef DEBUG386
2779
2780 /* Debugging routines for md_assemble. */
2781 static void pte (insn_template *);
2782 static void pt (i386_operand_type);
2783 static void pe (expressionS *);
2784 static void ps (symbolS *);
2785
2786 static void
2787 pi (char *line, i386_insn *x)
2788 {
2789 unsigned int j;
2790
2791 fprintf (stdout, "%s: template ", line);
2792 pte (&x->tm);
2793 fprintf (stdout, " address: base %s index %s scale %x\n",
2794 x->base_reg ? x->base_reg->reg_name : "none",
2795 x->index_reg ? x->index_reg->reg_name : "none",
2796 x->log2_scale_factor);
2797 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
2798 x->rm.mode, x->rm.reg, x->rm.regmem);
2799 fprintf (stdout, " sib: base %x index %x scale %x\n",
2800 x->sib.base, x->sib.index, x->sib.scale);
2801 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
2802 (x->rex & REX_W) != 0,
2803 (x->rex & REX_R) != 0,
2804 (x->rex & REX_X) != 0,
2805 (x->rex & REX_B) != 0);
2806 for (j = 0; j < x->operands; j++)
2807 {
2808 fprintf (stdout, " #%d: ", j + 1);
2809 pt (x->types[j]);
2810 fprintf (stdout, "\n");
2811 if (x->types[j].bitfield.reg8
2812 || x->types[j].bitfield.reg16
2813 || x->types[j].bitfield.reg32
2814 || x->types[j].bitfield.reg64
2815 || x->types[j].bitfield.regmmx
2816 || x->types[j].bitfield.regxmm
2817 || x->types[j].bitfield.regymm
2818 || x->types[j].bitfield.regzmm
2819 || x->types[j].bitfield.sreg2
2820 || x->types[j].bitfield.sreg3
2821 || x->types[j].bitfield.control
2822 || x->types[j].bitfield.debug
2823 || x->types[j].bitfield.test)
2824 fprintf (stdout, "%s\n", x->op[j].regs->reg_name);
2825 if (operand_type_check (x->types[j], imm))
2826 pe (x->op[j].imms);
2827 if (operand_type_check (x->types[j], disp))
2828 pe (x->op[j].disps);
2829 }
2830 }
2831
2832 static void
2833 pte (insn_template *t)
2834 {
2835 unsigned int j;
2836 fprintf (stdout, " %d operands ", t->operands);
2837 fprintf (stdout, "opcode %x ", t->base_opcode);
2838 if (t->extension_opcode != None)
2839 fprintf (stdout, "ext %x ", t->extension_opcode);
2840 if (t->opcode_modifier.d)
2841 fprintf (stdout, "D");
2842 if (t->opcode_modifier.w)
2843 fprintf (stdout, "W");
2844 fprintf (stdout, "\n");
2845 for (j = 0; j < t->operands; j++)
2846 {
2847 fprintf (stdout, " #%d type ", j + 1);
2848 pt (t->operand_types[j]);
2849 fprintf (stdout, "\n");
2850 }
2851 }
2852
2853 static void
2854 pe (expressionS *e)
2855 {
2856 fprintf (stdout, " operation %d\n", e->X_op);
2857 fprintf (stdout, " add_number %ld (%lx)\n",
2858 (long) e->X_add_number, (long) e->X_add_number);
2859 if (e->X_add_symbol)
2860 {
2861 fprintf (stdout, " add_symbol ");
2862 ps (e->X_add_symbol);
2863 fprintf (stdout, "\n");
2864 }
2865 if (e->X_op_symbol)
2866 {
2867 fprintf (stdout, " op_symbol ");
2868 ps (e->X_op_symbol);
2869 fprintf (stdout, "\n");
2870 }
2871 }
2872
2873 static void
2874 ps (symbolS *s)
2875 {
2876 fprintf (stdout, "%s type %s%s",
2877 S_GET_NAME (s),
2878 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
2879 segment_name (S_GET_SEGMENT (s)));
2880 }
2881
2882 static struct type_name
2883 {
2884 i386_operand_type mask;
2885 const char *name;
2886 }
2887 const type_names[] =
2888 {
2889 { OPERAND_TYPE_REG8, "r8" },
2890 { OPERAND_TYPE_REG16, "r16" },
2891 { OPERAND_TYPE_REG32, "r32" },
2892 { OPERAND_TYPE_REG64, "r64" },
2893 { OPERAND_TYPE_IMM8, "i8" },
2894 { OPERAND_TYPE_IMM8, "i8s" },
2895 { OPERAND_TYPE_IMM16, "i16" },
2896 { OPERAND_TYPE_IMM32, "i32" },
2897 { OPERAND_TYPE_IMM32S, "i32s" },
2898 { OPERAND_TYPE_IMM64, "i64" },
2899 { OPERAND_TYPE_IMM1, "i1" },
2900 { OPERAND_TYPE_BASEINDEX, "BaseIndex" },
2901 { OPERAND_TYPE_DISP8, "d8" },
2902 { OPERAND_TYPE_DISP16, "d16" },
2903 { OPERAND_TYPE_DISP32, "d32" },
2904 { OPERAND_TYPE_DISP32S, "d32s" },
2905 { OPERAND_TYPE_DISP64, "d64" },
2906 { OPERAND_TYPE_VEC_DISP8, "Vector d8" },
2907 { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" },
2908 { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" },
2909 { OPERAND_TYPE_CONTROL, "control reg" },
2910 { OPERAND_TYPE_TEST, "test reg" },
2911 { OPERAND_TYPE_DEBUG, "debug reg" },
2912 { OPERAND_TYPE_FLOATREG, "FReg" },
2913 { OPERAND_TYPE_FLOATACC, "FAcc" },
2914 { OPERAND_TYPE_SREG2, "SReg2" },
2915 { OPERAND_TYPE_SREG3, "SReg3" },
2916 { OPERAND_TYPE_ACC, "Acc" },
2917 { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" },
2918 { OPERAND_TYPE_REGMMX, "rMMX" },
2919 { OPERAND_TYPE_REGXMM, "rXMM" },
2920 { OPERAND_TYPE_REGYMM, "rYMM" },
2921 { OPERAND_TYPE_REGZMM, "rZMM" },
2922 { OPERAND_TYPE_REGMASK, "Mask reg" },
2923 { OPERAND_TYPE_ESSEG, "es" },
2924 };
2925
2926 static void
2927 pt (i386_operand_type t)
2928 {
2929 unsigned int j;
2930 i386_operand_type a;
2931
2932 for (j = 0; j < ARRAY_SIZE (type_names); j++)
2933 {
2934 a = operand_type_and (t, type_names[j].mask);
2935 if (!operand_type_all_zero (&a))
2936 fprintf (stdout, "%s, ", type_names[j].name);
2937 }
2938 fflush (stdout);
2939 }
2940
2941 #endif /* DEBUG386 */
2942 \f
2943 static bfd_reloc_code_real_type
2944 reloc (unsigned int size,
2945 int pcrel,
2946 int sign,
2947 bfd_reloc_code_real_type other)
2948 {
2949 if (other != NO_RELOC)
2950 {
2951 reloc_howto_type *rel;
2952
2953 if (size == 8)
2954 switch (other)
2955 {
2956 case BFD_RELOC_X86_64_GOT32:
2957 return BFD_RELOC_X86_64_GOT64;
2958 break;
2959 case BFD_RELOC_X86_64_GOTPLT64:
2960 return BFD_RELOC_X86_64_GOTPLT64;
2961 break;
2962 case BFD_RELOC_X86_64_PLTOFF64:
2963 return BFD_RELOC_X86_64_PLTOFF64;
2964 break;
2965 case BFD_RELOC_X86_64_GOTPC32:
2966 other = BFD_RELOC_X86_64_GOTPC64;
2967 break;
2968 case BFD_RELOC_X86_64_GOTPCREL:
2969 other = BFD_RELOC_X86_64_GOTPCREL64;
2970 break;
2971 case BFD_RELOC_X86_64_TPOFF32:
2972 other = BFD_RELOC_X86_64_TPOFF64;
2973 break;
2974 case BFD_RELOC_X86_64_DTPOFF32:
2975 other = BFD_RELOC_X86_64_DTPOFF64;
2976 break;
2977 default:
2978 break;
2979 }
2980
2981 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2982 if (other == BFD_RELOC_SIZE32)
2983 {
2984 if (size == 8)
2985 other = BFD_RELOC_SIZE64;
2986 if (pcrel)
2987 {
2988 as_bad (_("there are no pc-relative size relocations"));
2989 return NO_RELOC;
2990 }
2991 }
2992 #endif
2993
2994 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
2995 if (size == 4 && (flag_code != CODE_64BIT || disallow_64bit_reloc))
2996 sign = -1;
2997
2998 rel = bfd_reloc_type_lookup (stdoutput, other);
2999 if (!rel)
3000 as_bad (_("unknown relocation (%u)"), other);
3001 else if (size != bfd_get_reloc_size (rel))
3002 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
3003 bfd_get_reloc_size (rel),
3004 size);
3005 else if (pcrel && !rel->pc_relative)
3006 as_bad (_("non-pc-relative relocation for pc-relative field"));
3007 else if ((rel->complain_on_overflow == complain_overflow_signed
3008 && !sign)
3009 || (rel->complain_on_overflow == complain_overflow_unsigned
3010 && sign > 0))
3011 as_bad (_("relocated field and relocation type differ in signedness"));
3012 else
3013 return other;
3014 return NO_RELOC;
3015 }
3016
3017 if (pcrel)
3018 {
3019 if (!sign)
3020 as_bad (_("there are no unsigned pc-relative relocations"));
3021 switch (size)
3022 {
3023 case 1: return BFD_RELOC_8_PCREL;
3024 case 2: return BFD_RELOC_16_PCREL;
3025 case 4: return BFD_RELOC_32_PCREL;
3026 case 8: return BFD_RELOC_64_PCREL;
3027 }
3028 as_bad (_("cannot do %u byte pc-relative relocation"), size);
3029 }
3030 else
3031 {
3032 if (sign > 0)
3033 switch (size)
3034 {
3035 case 4: return BFD_RELOC_X86_64_32S;
3036 }
3037 else
3038 switch (size)
3039 {
3040 case 1: return BFD_RELOC_8;
3041 case 2: return BFD_RELOC_16;
3042 case 4: return BFD_RELOC_32;
3043 case 8: return BFD_RELOC_64;
3044 }
3045 as_bad (_("cannot do %s %u byte relocation"),
3046 sign > 0 ? "signed" : "unsigned", size);
3047 }
3048
3049 return NO_RELOC;
3050 }
3051
3052 /* Here we decide which fixups can be adjusted to make them relative to
3053 the beginning of the section instead of the symbol. Basically we need
3054 to make sure that the dynamic relocations are done correctly, so in
3055 some cases we force the original symbol to be used. */
3056
3057 int
3058 tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED)
3059 {
3060 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3061 if (!IS_ELF)
3062 return 1;
3063
3064 /* Don't adjust pc-relative references to merge sections in 64-bit
3065 mode. */
3066 if (use_rela_relocations
3067 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
3068 && fixP->fx_pcrel)
3069 return 0;
3070
3071 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
3072 and changed later by validate_fix. */
3073 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
3074 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
3075 return 0;
3076
3077 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
3078 for size relocations. */
3079 if (fixP->fx_r_type == BFD_RELOC_SIZE32
3080 || fixP->fx_r_type == BFD_RELOC_SIZE64
3081 || fixP->fx_r_type == BFD_RELOC_386_GOTOFF
3082 || fixP->fx_r_type == BFD_RELOC_386_PLT32
3083 || fixP->fx_r_type == BFD_RELOC_386_GOT32
3084 || fixP->fx_r_type == BFD_RELOC_386_GOT32X
3085 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
3086 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
3087 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
3088 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
3089 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
3090 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
3091 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
3092 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
3093 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
3094 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
3095 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
3096 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
3097 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
3098 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCRELX
3099 || fixP->fx_r_type == BFD_RELOC_X86_64_REX_GOTPCRELX
3100 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
3101 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
3102 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
3103 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
3104 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
3105 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
3106 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
3107 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
3108 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
3109 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
3110 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
3111 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
3112 return 0;
3113 #endif
3114 return 1;
3115 }
3116
3117 static int
3118 intel_float_operand (const char *mnemonic)
3119 {
3120 /* Note that the value returned is meaningful only for opcodes with (memory)
3121 operands, hence the code here is free to improperly handle opcodes that
3122 have no operands (for better performance and smaller code). */
3123
3124 if (mnemonic[0] != 'f')
3125 return 0; /* non-math */
3126
3127 switch (mnemonic[1])
3128 {
3129 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
3130 the fs segment override prefix not currently handled because no
3131 call path can make opcodes without operands get here */
3132 case 'i':
3133 return 2 /* integer op */;
3134 case 'l':
3135 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
3136 return 3; /* fldcw/fldenv */
3137 break;
3138 case 'n':
3139 if (mnemonic[2] != 'o' /* fnop */)
3140 return 3; /* non-waiting control op */
3141 break;
3142 case 'r':
3143 if (mnemonic[2] == 's')
3144 return 3; /* frstor/frstpm */
3145 break;
3146 case 's':
3147 if (mnemonic[2] == 'a')
3148 return 3; /* fsave */
3149 if (mnemonic[2] == 't')
3150 {
3151 switch (mnemonic[3])
3152 {
3153 case 'c': /* fstcw */
3154 case 'd': /* fstdw */
3155 case 'e': /* fstenv */
3156 case 's': /* fsts[gw] */
3157 return 3;
3158 }
3159 }
3160 break;
3161 case 'x':
3162 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
3163 return 0; /* fxsave/fxrstor are not really math ops */
3164 break;
3165 }
3166
3167 return 1;
3168 }
3169
3170 /* Build the VEX prefix. */
3171
3172 static void
3173 build_vex_prefix (const insn_template *t)
3174 {
3175 unsigned int register_specifier;
3176 unsigned int implied_prefix;
3177 unsigned int vector_length;
3178
3179 /* Check register specifier. */
3180 if (i.vex.register_specifier)
3181 {
3182 register_specifier =
3183 ~register_number (i.vex.register_specifier) & 0xf;
3184 gas_assert ((i.vex.register_specifier->reg_flags & RegVRex) == 0);
3185 }
3186 else
3187 register_specifier = 0xf;
3188
3189 /* Use 2-byte VEX prefix by swapping destination and source
3190 operand. */
3191 if (i.vec_encoding != vex_encoding_vex3
3192 && i.dir_encoding == dir_encoding_default
3193 && i.operands == i.reg_operands
3194 && i.tm.opcode_modifier.vexopcode == VEX0F
3195 && i.tm.opcode_modifier.load
3196 && i.rex == REX_B)
3197 {
3198 unsigned int xchg = i.operands - 1;
3199 union i386_op temp_op;
3200 i386_operand_type temp_type;
3201
3202 temp_type = i.types[xchg];
3203 i.types[xchg] = i.types[0];
3204 i.types[0] = temp_type;
3205 temp_op = i.op[xchg];
3206 i.op[xchg] = i.op[0];
3207 i.op[0] = temp_op;
3208
3209 gas_assert (i.rm.mode == 3);
3210
3211 i.rex = REX_R;
3212 xchg = i.rm.regmem;
3213 i.rm.regmem = i.rm.reg;
3214 i.rm.reg = xchg;
3215
3216 /* Use the next insn. */
3217 i.tm = t[1];
3218 }
3219
3220 if (i.tm.opcode_modifier.vex == VEXScalar)
3221 vector_length = avxscalar;
3222 else
3223 vector_length = i.tm.opcode_modifier.vex == VEX256 ? 1 : 0;
3224
3225 switch ((i.tm.base_opcode >> 8) & 0xff)
3226 {
3227 case 0:
3228 implied_prefix = 0;
3229 break;
3230 case DATA_PREFIX_OPCODE:
3231 implied_prefix = 1;
3232 break;
3233 case REPE_PREFIX_OPCODE:
3234 implied_prefix = 2;
3235 break;
3236 case REPNE_PREFIX_OPCODE:
3237 implied_prefix = 3;
3238 break;
3239 default:
3240 abort ();
3241 }
3242
3243 /* Use 2-byte VEX prefix if possible. */
3244 if (i.vec_encoding != vex_encoding_vex3
3245 && i.tm.opcode_modifier.vexopcode == VEX0F
3246 && i.tm.opcode_modifier.vexw != VEXW1
3247 && (i.rex & (REX_W | REX_X | REX_B)) == 0)
3248 {
3249 /* 2-byte VEX prefix. */
3250 unsigned int r;
3251
3252 i.vex.length = 2;
3253 i.vex.bytes[0] = 0xc5;
3254
3255 /* Check the REX.R bit. */
3256 r = (i.rex & REX_R) ? 0 : 1;
3257 i.vex.bytes[1] = (r << 7
3258 | register_specifier << 3
3259 | vector_length << 2
3260 | implied_prefix);
3261 }
3262 else
3263 {
3264 /* 3-byte VEX prefix. */
3265 unsigned int m, w;
3266
3267 i.vex.length = 3;
3268
3269 switch (i.tm.opcode_modifier.vexopcode)
3270 {
3271 case VEX0F:
3272 m = 0x1;
3273 i.vex.bytes[0] = 0xc4;
3274 break;
3275 case VEX0F38:
3276 m = 0x2;
3277 i.vex.bytes[0] = 0xc4;
3278 break;
3279 case VEX0F3A:
3280 m = 0x3;
3281 i.vex.bytes[0] = 0xc4;
3282 break;
3283 case XOP08:
3284 m = 0x8;
3285 i.vex.bytes[0] = 0x8f;
3286 break;
3287 case XOP09:
3288 m = 0x9;
3289 i.vex.bytes[0] = 0x8f;
3290 break;
3291 case XOP0A:
3292 m = 0xa;
3293 i.vex.bytes[0] = 0x8f;
3294 break;
3295 default:
3296 abort ();
3297 }
3298
3299 /* The high 3 bits of the second VEX byte are 1's compliment
3300 of RXB bits from REX. */
3301 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
3302
3303 /* Check the REX.W bit. */
3304 w = (i.rex & REX_W) ? 1 : 0;
3305 if (i.tm.opcode_modifier.vexw == VEXW1)
3306 w = 1;
3307
3308 i.vex.bytes[2] = (w << 7
3309 | register_specifier << 3
3310 | vector_length << 2
3311 | implied_prefix);
3312 }
3313 }
3314
3315 /* Build the EVEX prefix. */
3316
3317 static void
3318 build_evex_prefix (void)
3319 {
3320 unsigned int register_specifier;
3321 unsigned int implied_prefix;
3322 unsigned int m, w;
3323 rex_byte vrex_used = 0;
3324
3325 /* Check register specifier. */
3326 if (i.vex.register_specifier)
3327 {
3328 gas_assert ((i.vrex & REX_X) == 0);
3329
3330 register_specifier = i.vex.register_specifier->reg_num;
3331 if ((i.vex.register_specifier->reg_flags & RegRex))
3332 register_specifier += 8;
3333 /* The upper 16 registers are encoded in the fourth byte of the
3334 EVEX prefix. */
3335 if (!(i.vex.register_specifier->reg_flags & RegVRex))
3336 i.vex.bytes[3] = 0x8;
3337 register_specifier = ~register_specifier & 0xf;
3338 }
3339 else
3340 {
3341 register_specifier = 0xf;
3342
3343 /* Encode upper 16 vector index register in the fourth byte of
3344 the EVEX prefix. */
3345 if (!(i.vrex & REX_X))
3346 i.vex.bytes[3] = 0x8;
3347 else
3348 vrex_used |= REX_X;
3349 }
3350
3351 switch ((i.tm.base_opcode >> 8) & 0xff)
3352 {
3353 case 0:
3354 implied_prefix = 0;
3355 break;
3356 case DATA_PREFIX_OPCODE:
3357 implied_prefix = 1;
3358 break;
3359 case REPE_PREFIX_OPCODE:
3360 implied_prefix = 2;
3361 break;
3362 case REPNE_PREFIX_OPCODE:
3363 implied_prefix = 3;
3364 break;
3365 default:
3366 abort ();
3367 }
3368
3369 /* 4 byte EVEX prefix. */
3370 i.vex.length = 4;
3371 i.vex.bytes[0] = 0x62;
3372
3373 /* mmmm bits. */
3374 switch (i.tm.opcode_modifier.vexopcode)
3375 {
3376 case VEX0F:
3377 m = 1;
3378 break;
3379 case VEX0F38:
3380 m = 2;
3381 break;
3382 case VEX0F3A:
3383 m = 3;
3384 break;
3385 default:
3386 abort ();
3387 break;
3388 }
3389
3390 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3391 bits from REX. */
3392 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
3393
3394 /* The fifth bit of the second EVEX byte is 1's compliment of the
3395 REX_R bit in VREX. */
3396 if (!(i.vrex & REX_R))
3397 i.vex.bytes[1] |= 0x10;
3398 else
3399 vrex_used |= REX_R;
3400
3401 if ((i.reg_operands + i.imm_operands) == i.operands)
3402 {
3403 /* When all operands are registers, the REX_X bit in REX is not
3404 used. We reuse it to encode the upper 16 registers, which is
3405 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3406 as 1's compliment. */
3407 if ((i.vrex & REX_B))
3408 {
3409 vrex_used |= REX_B;
3410 i.vex.bytes[1] &= ~0x40;
3411 }
3412 }
3413
3414 /* EVEX instructions shouldn't need the REX prefix. */
3415 i.vrex &= ~vrex_used;
3416 gas_assert (i.vrex == 0);
3417
3418 /* Check the REX.W bit. */
3419 w = (i.rex & REX_W) ? 1 : 0;
3420 if (i.tm.opcode_modifier.vexw)
3421 {
3422 if (i.tm.opcode_modifier.vexw == VEXW1)
3423 w = 1;
3424 }
3425 /* If w is not set it means we are dealing with WIG instruction. */
3426 else if (!w)
3427 {
3428 if (evexwig == evexw1)
3429 w = 1;
3430 }
3431
3432 /* Encode the U bit. */
3433 implied_prefix |= 0x4;
3434
3435 /* The third byte of the EVEX prefix. */
3436 i.vex.bytes[2] = (w << 7 | register_specifier << 3 | implied_prefix);
3437
3438 /* The fourth byte of the EVEX prefix. */
3439 /* The zeroing-masking bit. */
3440 if (i.mask && i.mask->zeroing)
3441 i.vex.bytes[3] |= 0x80;
3442
3443 /* Don't always set the broadcast bit if there is no RC. */
3444 if (!i.rounding)
3445 {
3446 /* Encode the vector length. */
3447 unsigned int vec_length;
3448
3449 switch (i.tm.opcode_modifier.evex)
3450 {
3451 case EVEXLIG: /* LL' is ignored */
3452 vec_length = evexlig << 5;
3453 break;
3454 case EVEX128:
3455 vec_length = 0 << 5;
3456 break;
3457 case EVEX256:
3458 vec_length = 1 << 5;
3459 break;
3460 case EVEX512:
3461 vec_length = 2 << 5;
3462 break;
3463 default:
3464 abort ();
3465 break;
3466 }
3467 i.vex.bytes[3] |= vec_length;
3468 /* Encode the broadcast bit. */
3469 if (i.broadcast)
3470 i.vex.bytes[3] |= 0x10;
3471 }
3472 else
3473 {
3474 if (i.rounding->type != saeonly)
3475 i.vex.bytes[3] |= 0x10 | (i.rounding->type << 5);
3476 else
3477 i.vex.bytes[3] |= 0x10 | (evexrcig << 5);
3478 }
3479
3480 if (i.mask && i.mask->mask)
3481 i.vex.bytes[3] |= i.mask->mask->reg_num;
3482 }
3483
3484 static void
3485 process_immext (void)
3486 {
3487 expressionS *exp;
3488
3489 if ((i.tm.cpu_flags.bitfield.cpusse3 || i.tm.cpu_flags.bitfield.cpusvme)
3490 && i.operands > 0)
3491 {
3492 /* MONITOR/MWAIT as well as SVME instructions have fixed operands
3493 with an opcode suffix which is coded in the same place as an
3494 8-bit immediate field would be.
3495 Here we check those operands and remove them afterwards. */
3496 unsigned int x;
3497
3498 for (x = 0; x < i.operands; x++)
3499 if (register_number (i.op[x].regs) != x)
3500 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3501 register_prefix, i.op[x].regs->reg_name, x + 1,
3502 i.tm.name);
3503
3504 i.operands = 0;
3505 }
3506
3507 if (i.tm.cpu_flags.bitfield.cpumwaitx && i.operands > 0)
3508 {
3509 /* MONITORX/MWAITX instructions have fixed operands with an opcode
3510 suffix which is coded in the same place as an 8-bit immediate
3511 field would be.
3512 Here we check those operands and remove them afterwards. */
3513 unsigned int x;
3514
3515 if (i.operands != 3)
3516 abort();
3517
3518 for (x = 0; x < 2; x++)
3519 if (register_number (i.op[x].regs) != x)
3520 goto bad_register_operand;
3521
3522 /* Check for third operand for mwaitx/monitorx insn. */
3523 if (register_number (i.op[x].regs)
3524 != (x + (i.tm.extension_opcode == 0xfb)))
3525 {
3526 bad_register_operand:
3527 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3528 register_prefix, i.op[x].regs->reg_name, x+1,
3529 i.tm.name);
3530 }
3531
3532 i.operands = 0;
3533 }
3534
3535 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
3536 which is coded in the same place as an 8-bit immediate field
3537 would be. Here we fake an 8-bit immediate operand from the
3538 opcode suffix stored in tm.extension_opcode.
3539
3540 AVX instructions also use this encoding, for some of
3541 3 argument instructions. */
3542
3543 gas_assert (i.imm_operands <= 1
3544 && (i.operands <= 2
3545 || ((i.tm.opcode_modifier.vex
3546 || i.tm.opcode_modifier.evex)
3547 && i.operands <= 4)));
3548
3549 exp = &im_expressions[i.imm_operands++];
3550 i.op[i.operands].imms = exp;
3551 i.types[i.operands] = imm8;
3552 i.operands++;
3553 exp->X_op = O_constant;
3554 exp->X_add_number = i.tm.extension_opcode;
3555 i.tm.extension_opcode = None;
3556 }
3557
3558
3559 static int
3560 check_hle (void)
3561 {
3562 switch (i.tm.opcode_modifier.hleprefixok)
3563 {
3564 default:
3565 abort ();
3566 case HLEPrefixNone:
3567 as_bad (_("invalid instruction `%s' after `%s'"),
3568 i.tm.name, i.hle_prefix);
3569 return 0;
3570 case HLEPrefixLock:
3571 if (i.prefix[LOCK_PREFIX])
3572 return 1;
3573 as_bad (_("missing `lock' with `%s'"), i.hle_prefix);
3574 return 0;
3575 case HLEPrefixAny:
3576 return 1;
3577 case HLEPrefixRelease:
3578 if (i.prefix[HLE_PREFIX] != XRELEASE_PREFIX_OPCODE)
3579 {
3580 as_bad (_("instruction `%s' after `xacquire' not allowed"),
3581 i.tm.name);
3582 return 0;
3583 }
3584 if (i.mem_operands == 0
3585 || !operand_type_check (i.types[i.operands - 1], anymem))
3586 {
3587 as_bad (_("memory destination needed for instruction `%s'"
3588 " after `xrelease'"), i.tm.name);
3589 return 0;
3590 }
3591 return 1;
3592 }
3593 }
3594
3595 /* This is the guts of the machine-dependent assembler. LINE points to a
3596 machine dependent instruction. This function is supposed to emit
3597 the frags/bytes it assembles to. */
3598
3599 void
3600 md_assemble (char *line)
3601 {
3602 unsigned int j;
3603 char mnemonic[MAX_MNEM_SIZE], mnem_suffix;
3604 const insn_template *t;
3605
3606 /* Initialize globals. */
3607 memset (&i, '\0', sizeof (i));
3608 for (j = 0; j < MAX_OPERANDS; j++)
3609 i.reloc[j] = NO_RELOC;
3610 memset (disp_expressions, '\0', sizeof (disp_expressions));
3611 memset (im_expressions, '\0', sizeof (im_expressions));
3612 save_stack_p = save_stack;
3613
3614 /* First parse an instruction mnemonic & call i386_operand for the operands.
3615 We assume that the scrubber has arranged it so that line[0] is the valid
3616 start of a (possibly prefixed) mnemonic. */
3617
3618 line = parse_insn (line, mnemonic);
3619 if (line == NULL)
3620 return;
3621 mnem_suffix = i.suffix;
3622
3623 line = parse_operands (line, mnemonic);
3624 this_operand = -1;
3625 xfree (i.memop1_string);
3626 i.memop1_string = NULL;
3627 if (line == NULL)
3628 return;
3629
3630 /* Now we've parsed the mnemonic into a set of templates, and have the
3631 operands at hand. */
3632
3633 /* All intel opcodes have reversed operands except for "bound" and
3634 "enter". We also don't reverse intersegment "jmp" and "call"
3635 instructions with 2 immediate operands so that the immediate segment
3636 precedes the offset, as it does when in AT&T mode. */
3637 if (intel_syntax
3638 && i.operands > 1
3639 && (strcmp (mnemonic, "bound") != 0)
3640 && (strcmp (mnemonic, "invlpga") != 0)
3641 && !(operand_type_check (i.types[0], imm)
3642 && operand_type_check (i.types[1], imm)))
3643 swap_operands ();
3644
3645 /* The order of the immediates should be reversed
3646 for 2 immediates extrq and insertq instructions */
3647 if (i.imm_operands == 2
3648 && (strcmp (mnemonic, "extrq") == 0
3649 || strcmp (mnemonic, "insertq") == 0))
3650 swap_2_operands (0, 1);
3651
3652 if (i.imm_operands)
3653 optimize_imm ();
3654
3655 /* Don't optimize displacement for movabs since it only takes 64bit
3656 displacement. */
3657 if (i.disp_operands
3658 && i.disp_encoding != disp_encoding_32bit
3659 && (flag_code != CODE_64BIT
3660 || strcmp (mnemonic, "movabs") != 0))
3661 optimize_disp ();
3662
3663 /* Next, we find a template that matches the given insn,
3664 making sure the overlap of the given operands types is consistent
3665 with the template operand types. */
3666
3667 if (!(t = match_template (mnem_suffix)))
3668 return;
3669
3670 if (sse_check != check_none
3671 && !i.tm.opcode_modifier.noavx
3672 && (i.tm.cpu_flags.bitfield.cpusse
3673 || i.tm.cpu_flags.bitfield.cpusse2
3674 || i.tm.cpu_flags.bitfield.cpusse3
3675 || i.tm.cpu_flags.bitfield.cpussse3
3676 || i.tm.cpu_flags.bitfield.cpusse4_1
3677 || i.tm.cpu_flags.bitfield.cpusse4_2))
3678 {
3679 (sse_check == check_warning
3680 ? as_warn
3681 : as_bad) (_("SSE instruction `%s' is used"), i.tm.name);
3682 }
3683
3684 /* Zap movzx and movsx suffix. The suffix has been set from
3685 "word ptr" or "byte ptr" on the source operand in Intel syntax
3686 or extracted from mnemonic in AT&T syntax. But we'll use
3687 the destination register to choose the suffix for encoding. */
3688 if ((i.tm.base_opcode & ~9) == 0x0fb6)
3689 {
3690 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
3691 there is no suffix, the default will be byte extension. */
3692 if (i.reg_operands != 2
3693 && !i.suffix
3694 && intel_syntax)
3695 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
3696
3697 i.suffix = 0;
3698 }
3699
3700 if (i.tm.opcode_modifier.fwait)
3701 if (!add_prefix (FWAIT_OPCODE))
3702 return;
3703
3704 /* Check if REP prefix is OK. */
3705 if (i.rep_prefix && !i.tm.opcode_modifier.repprefixok)
3706 {
3707 as_bad (_("invalid instruction `%s' after `%s'"),
3708 i.tm.name, i.rep_prefix);
3709 return;
3710 }
3711
3712 /* Check for lock without a lockable instruction. Destination operand
3713 must be memory unless it is xchg (0x86). */
3714 if (i.prefix[LOCK_PREFIX]
3715 && (!i.tm.opcode_modifier.islockable
3716 || i.mem_operands == 0
3717 || (i.tm.base_opcode != 0x86
3718 && !operand_type_check (i.types[i.operands - 1], anymem))))
3719 {
3720 as_bad (_("expecting lockable instruction after `lock'"));
3721 return;
3722 }
3723
3724 /* Check if HLE prefix is OK. */
3725 if (i.hle_prefix && !check_hle ())
3726 return;
3727
3728 /* Check BND prefix. */
3729 if (i.bnd_prefix && !i.tm.opcode_modifier.bndprefixok)
3730 as_bad (_("expecting valid branch instruction after `bnd'"));
3731
3732 /* Check NOTRACK prefix. */
3733 if (i.notrack_prefix && !i.tm.opcode_modifier.notrackprefixok)
3734 as_bad (_("expecting indirect branch instruction after `notrack'"));
3735
3736 if (i.tm.cpu_flags.bitfield.cpumpx)
3737 {
3738 if (flag_code == CODE_64BIT && i.prefix[ADDR_PREFIX])
3739 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
3740 else if (flag_code != CODE_16BIT
3741 ? i.prefix[ADDR_PREFIX]
3742 : i.mem_operands && !i.prefix[ADDR_PREFIX])
3743 as_bad (_("16-bit address isn't allowed in MPX instructions"));
3744 }
3745
3746 /* Insert BND prefix. */
3747 if (add_bnd_prefix
3748 && i.tm.opcode_modifier.bndprefixok
3749 && !i.prefix[BND_PREFIX])
3750 add_prefix (BND_PREFIX_OPCODE);
3751
3752 /* Check string instruction segment overrides. */
3753 if (i.tm.opcode_modifier.isstring && i.mem_operands != 0)
3754 {
3755 if (!check_string ())
3756 return;
3757 i.disp_operands = 0;
3758 }
3759
3760 if (!process_suffix ())
3761 return;
3762
3763 /* Update operand types. */
3764 for (j = 0; j < i.operands; j++)
3765 i.types[j] = operand_type_and (i.types[j], i.tm.operand_types[j]);
3766
3767 /* Make still unresolved immediate matches conform to size of immediate
3768 given in i.suffix. */
3769 if (!finalize_imm ())
3770 return;
3771
3772 if (i.types[0].bitfield.imm1)
3773 i.imm_operands = 0; /* kludge for shift insns. */
3774
3775 /* We only need to check those implicit registers for instructions
3776 with 3 operands or less. */
3777 if (i.operands <= 3)
3778 for (j = 0; j < i.operands; j++)
3779 if (i.types[j].bitfield.inoutportreg
3780 || i.types[j].bitfield.shiftcount
3781 || i.types[j].bitfield.acc
3782 || i.types[j].bitfield.floatacc)
3783 i.reg_operands--;
3784
3785 /* ImmExt should be processed after SSE2AVX. */
3786 if (!i.tm.opcode_modifier.sse2avx
3787 && i.tm.opcode_modifier.immext)
3788 process_immext ();
3789
3790 /* For insns with operands there are more diddles to do to the opcode. */
3791 if (i.operands)
3792 {
3793 if (!process_operands ())
3794 return;
3795 }
3796 else if (!quiet_warnings && i.tm.opcode_modifier.ugh)
3797 {
3798 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
3799 as_warn (_("translating to `%sp'"), i.tm.name);
3800 }
3801
3802 if (i.tm.opcode_modifier.vex || i.tm.opcode_modifier.evex)
3803 {
3804 if (flag_code == CODE_16BIT)
3805 {
3806 as_bad (_("instruction `%s' isn't supported in 16-bit mode."),
3807 i.tm.name);
3808 return;
3809 }
3810
3811 if (i.tm.opcode_modifier.vex)
3812 build_vex_prefix (t);
3813 else
3814 build_evex_prefix ();
3815 }
3816
3817 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
3818 instructions may define INT_OPCODE as well, so avoid this corner
3819 case for those instructions that use MODRM. */
3820 if (i.tm.base_opcode == INT_OPCODE
3821 && !i.tm.opcode_modifier.modrm
3822 && i.op[0].imms->X_add_number == 3)
3823 {
3824 i.tm.base_opcode = INT3_OPCODE;
3825 i.imm_operands = 0;
3826 }
3827
3828 if ((i.tm.opcode_modifier.jump
3829 || i.tm.opcode_modifier.jumpbyte
3830 || i.tm.opcode_modifier.jumpdword)
3831 && i.op[0].disps->X_op == O_constant)
3832 {
3833 /* Convert "jmp constant" (and "call constant") to a jump (call) to
3834 the absolute address given by the constant. Since ix86 jumps and
3835 calls are pc relative, we need to generate a reloc. */
3836 i.op[0].disps->X_add_symbol = &abs_symbol;
3837 i.op[0].disps->X_op = O_symbol;
3838 }
3839
3840 if (i.tm.opcode_modifier.rex64)
3841 i.rex |= REX_W;
3842
3843 /* For 8 bit registers we need an empty rex prefix. Also if the
3844 instruction already has a prefix, we need to convert old
3845 registers to new ones. */
3846
3847 if ((i.types[0].bitfield.reg8
3848 && (i.op[0].regs->reg_flags & RegRex64) != 0)
3849 || (i.types[1].bitfield.reg8
3850 && (i.op[1].regs->reg_flags & RegRex64) != 0)
3851 || ((i.types[0].bitfield.reg8
3852 || i.types[1].bitfield.reg8)
3853 && i.rex != 0))
3854 {
3855 int x;
3856
3857 i.rex |= REX_OPCODE;
3858 for (x = 0; x < 2; x++)
3859 {
3860 /* Look for 8 bit operand that uses old registers. */
3861 if (i.types[x].bitfield.reg8
3862 && (i.op[x].regs->reg_flags & RegRex64) == 0)
3863 {
3864 /* In case it is "hi" register, give up. */
3865 if (i.op[x].regs->reg_num > 3)
3866 as_bad (_("can't encode register '%s%s' in an "
3867 "instruction requiring REX prefix."),
3868 register_prefix, i.op[x].regs->reg_name);
3869
3870 /* Otherwise it is equivalent to the extended register.
3871 Since the encoding doesn't change this is merely
3872 cosmetic cleanup for debug output. */
3873
3874 i.op[x].regs = i.op[x].regs + 8;
3875 }
3876 }
3877 }
3878
3879 if (i.rex != 0)
3880 add_prefix (REX_OPCODE | i.rex);
3881
3882 /* We are ready to output the insn. */
3883 output_insn ();
3884 }
3885
3886 static char *
3887 parse_insn (char *line, char *mnemonic)
3888 {
3889 char *l = line;
3890 char *token_start = l;
3891 char *mnem_p;
3892 int supported;
3893 const insn_template *t;
3894 char *dot_p = NULL;
3895
3896 while (1)
3897 {
3898 mnem_p = mnemonic;
3899 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
3900 {
3901 if (*mnem_p == '.')
3902 dot_p = mnem_p;
3903 mnem_p++;
3904 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
3905 {
3906 as_bad (_("no such instruction: `%s'"), token_start);
3907 return NULL;
3908 }
3909 l++;
3910 }
3911 if (!is_space_char (*l)
3912 && *l != END_OF_INSN
3913 && (intel_syntax
3914 || (*l != PREFIX_SEPARATOR
3915 && *l != ',')))
3916 {
3917 as_bad (_("invalid character %s in mnemonic"),
3918 output_invalid (*l));
3919 return NULL;
3920 }
3921 if (token_start == l)
3922 {
3923 if (!intel_syntax && *l == PREFIX_SEPARATOR)
3924 as_bad (_("expecting prefix; got nothing"));
3925 else
3926 as_bad (_("expecting mnemonic; got nothing"));
3927 return NULL;
3928 }
3929
3930 /* Look up instruction (or prefix) via hash table. */
3931 current_templates = (const templates *) hash_find (op_hash, mnemonic);
3932
3933 if (*l != END_OF_INSN
3934 && (!is_space_char (*l) || l[1] != END_OF_INSN)
3935 && current_templates
3936 && current_templates->start->opcode_modifier.isprefix)
3937 {
3938 if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags))
3939 {
3940 as_bad ((flag_code != CODE_64BIT
3941 ? _("`%s' is only supported in 64-bit mode")
3942 : _("`%s' is not supported in 64-bit mode")),
3943 current_templates->start->name);
3944 return NULL;
3945 }
3946 /* If we are in 16-bit mode, do not allow addr16 or data16.
3947 Similarly, in 32-bit mode, do not allow addr32 or data32. */
3948 if ((current_templates->start->opcode_modifier.size16
3949 || current_templates->start->opcode_modifier.size32)
3950 && flag_code != CODE_64BIT
3951 && (current_templates->start->opcode_modifier.size32
3952 ^ (flag_code == CODE_16BIT)))
3953 {
3954 as_bad (_("redundant %s prefix"),
3955 current_templates->start->name);
3956 return NULL;
3957 }
3958 if (current_templates->start->opcode_length == 0)
3959 {
3960 /* Handle pseudo prefixes. */
3961 switch (current_templates->start->base_opcode)
3962 {
3963 case 0x0:
3964 /* {disp8} */
3965 i.disp_encoding = disp_encoding_8bit;
3966 break;
3967 case 0x1:
3968 /* {disp32} */
3969 i.disp_encoding = disp_encoding_32bit;
3970 break;
3971 case 0x2:
3972 /* {load} */
3973 i.dir_encoding = dir_encoding_load;
3974 break;
3975 case 0x3:
3976 /* {store} */
3977 i.dir_encoding = dir_encoding_store;
3978 break;
3979 case 0x4:
3980 /* {vex2} */
3981 i.vec_encoding = vex_encoding_vex2;
3982 break;
3983 case 0x5:
3984 /* {vex3} */
3985 i.vec_encoding = vex_encoding_vex3;
3986 break;
3987 case 0x6:
3988 /* {evex} */
3989 i.vec_encoding = vex_encoding_evex;
3990 break;
3991 default:
3992 abort ();
3993 }
3994 }
3995 else
3996 {
3997 /* Add prefix, checking for repeated prefixes. */
3998 switch (add_prefix (current_templates->start->base_opcode))
3999 {
4000 case PREFIX_EXIST:
4001 return NULL;
4002 case PREFIX_DS:
4003 if (current_templates->start->cpu_flags.bitfield.cpucet)
4004 i.notrack_prefix = current_templates->start->name;
4005 break;
4006 case PREFIX_REP:
4007 if (current_templates->start->cpu_flags.bitfield.cpuhle)
4008 i.hle_prefix = current_templates->start->name;
4009 else if (current_templates->start->cpu_flags.bitfield.cpumpx)
4010 i.bnd_prefix = current_templates->start->name;
4011 else
4012 i.rep_prefix = current_templates->start->name;
4013 break;
4014 default:
4015 break;
4016 }
4017 }
4018 /* Skip past PREFIX_SEPARATOR and reset token_start. */
4019 token_start = ++l;
4020 }
4021 else
4022 break;
4023 }
4024
4025 if (!current_templates)
4026 {
4027 /* Check if we should swap operand or force 32bit displacement in
4028 encoding. */
4029 if (mnem_p - 2 == dot_p && dot_p[1] == 's')
4030 i.dir_encoding = dir_encoding_store;
4031 else if (mnem_p - 3 == dot_p
4032 && dot_p[1] == 'd'
4033 && dot_p[2] == '8')
4034 i.disp_encoding = disp_encoding_8bit;
4035 else if (mnem_p - 4 == dot_p
4036 && dot_p[1] == 'd'
4037 && dot_p[2] == '3'
4038 && dot_p[3] == '2')
4039 i.disp_encoding = disp_encoding_32bit;
4040 else
4041 goto check_suffix;
4042 mnem_p = dot_p;
4043 *dot_p = '\0';
4044 current_templates = (const templates *) hash_find (op_hash, mnemonic);
4045 }
4046
4047 if (!current_templates)
4048 {
4049 check_suffix:
4050 /* See if we can get a match by trimming off a suffix. */
4051 switch (mnem_p[-1])
4052 {
4053 case WORD_MNEM_SUFFIX:
4054 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
4055 i.suffix = SHORT_MNEM_SUFFIX;
4056 else
4057 /* Fall through. */
4058 case BYTE_MNEM_SUFFIX:
4059 case QWORD_MNEM_SUFFIX:
4060 i.suffix = mnem_p[-1];
4061 mnem_p[-1] = '\0';
4062 current_templates = (const templates *) hash_find (op_hash,
4063 mnemonic);
4064 break;
4065 case SHORT_MNEM_SUFFIX:
4066 case LONG_MNEM_SUFFIX:
4067 if (!intel_syntax)
4068 {
4069 i.suffix = mnem_p[-1];
4070 mnem_p[-1] = '\0';
4071 current_templates = (const templates *) hash_find (op_hash,
4072 mnemonic);
4073 }
4074 break;
4075
4076 /* Intel Syntax. */
4077 case 'd':
4078 if (intel_syntax)
4079 {
4080 if (intel_float_operand (mnemonic) == 1)
4081 i.suffix = SHORT_MNEM_SUFFIX;
4082 else
4083 i.suffix = LONG_MNEM_SUFFIX;
4084 mnem_p[-1] = '\0';
4085 current_templates = (const templates *) hash_find (op_hash,
4086 mnemonic);
4087 }
4088 break;
4089 }
4090 if (!current_templates)
4091 {
4092 as_bad (_("no such instruction: `%s'"), token_start);
4093 return NULL;
4094 }
4095 }
4096
4097 if (current_templates->start->opcode_modifier.jump
4098 || current_templates->start->opcode_modifier.jumpbyte)
4099 {
4100 /* Check for a branch hint. We allow ",pt" and ",pn" for
4101 predict taken and predict not taken respectively.
4102 I'm not sure that branch hints actually do anything on loop
4103 and jcxz insns (JumpByte) for current Pentium4 chips. They
4104 may work in the future and it doesn't hurt to accept them
4105 now. */
4106 if (l[0] == ',' && l[1] == 'p')
4107 {
4108 if (l[2] == 't')
4109 {
4110 if (!add_prefix (DS_PREFIX_OPCODE))
4111 return NULL;
4112 l += 3;
4113 }
4114 else if (l[2] == 'n')
4115 {
4116 if (!add_prefix (CS_PREFIX_OPCODE))
4117 return NULL;
4118 l += 3;
4119 }
4120 }
4121 }
4122 /* Any other comma loses. */
4123 if (*l == ',')
4124 {
4125 as_bad (_("invalid character %s in mnemonic"),
4126 output_invalid (*l));
4127 return NULL;
4128 }
4129
4130 /* Check if instruction is supported on specified architecture. */
4131 supported = 0;
4132 for (t = current_templates->start; t < current_templates->end; ++t)
4133 {
4134 supported |= cpu_flags_match (t);
4135 if (supported == CPU_FLAGS_PERFECT_MATCH)
4136 goto skip;
4137 }
4138
4139 if (!(supported & CPU_FLAGS_64BIT_MATCH))
4140 {
4141 as_bad (flag_code == CODE_64BIT
4142 ? _("`%s' is not supported in 64-bit mode")
4143 : _("`%s' is only supported in 64-bit mode"),
4144 current_templates->start->name);
4145 return NULL;
4146 }
4147 if (supported != CPU_FLAGS_PERFECT_MATCH)
4148 {
4149 as_bad (_("`%s' is not supported on `%s%s'"),
4150 current_templates->start->name,
4151 cpu_arch_name ? cpu_arch_name : default_arch,
4152 cpu_sub_arch_name ? cpu_sub_arch_name : "");
4153 return NULL;
4154 }
4155
4156 skip:
4157 if (!cpu_arch_flags.bitfield.cpui386
4158 && (flag_code != CODE_16BIT))
4159 {
4160 as_warn (_("use .code16 to ensure correct addressing mode"));
4161 }
4162
4163 return l;
4164 }
4165
4166 static char *
4167 parse_operands (char *l, const char *mnemonic)
4168 {
4169 char *token_start;
4170
4171 /* 1 if operand is pending after ','. */
4172 unsigned int expecting_operand = 0;
4173
4174 /* Non-zero if operand parens not balanced. */
4175 unsigned int paren_not_balanced;
4176
4177 while (*l != END_OF_INSN)
4178 {
4179 /* Skip optional white space before operand. */
4180 if (is_space_char (*l))
4181 ++l;
4182 if (!is_operand_char (*l) && *l != END_OF_INSN && *l != '"')
4183 {
4184 as_bad (_("invalid character %s before operand %d"),
4185 output_invalid (*l),
4186 i.operands + 1);
4187 return NULL;
4188 }
4189 token_start = l; /* After white space. */
4190 paren_not_balanced = 0;
4191 while (paren_not_balanced || *l != ',')
4192 {
4193 if (*l == END_OF_INSN)
4194 {
4195 if (paren_not_balanced)
4196 {
4197 if (!intel_syntax)
4198 as_bad (_("unbalanced parenthesis in operand %d."),
4199 i.operands + 1);
4200 else
4201 as_bad (_("unbalanced brackets in operand %d."),
4202 i.operands + 1);
4203 return NULL;
4204 }
4205 else
4206 break; /* we are done */
4207 }
4208 else if (!is_operand_char (*l) && !is_space_char (*l) && *l != '"')
4209 {
4210 as_bad (_("invalid character %s in operand %d"),
4211 output_invalid (*l),
4212 i.operands + 1);
4213 return NULL;
4214 }
4215 if (!intel_syntax)
4216 {
4217 if (*l == '(')
4218 ++paren_not_balanced;
4219 if (*l == ')')
4220 --paren_not_balanced;
4221 }
4222 else
4223 {
4224 if (*l == '[')
4225 ++paren_not_balanced;
4226 if (*l == ']')
4227 --paren_not_balanced;
4228 }
4229 l++;
4230 }
4231 if (l != token_start)
4232 { /* Yes, we've read in another operand. */
4233 unsigned int operand_ok;
4234 this_operand = i.operands++;
4235 if (i.operands > MAX_OPERANDS)
4236 {
4237 as_bad (_("spurious operands; (%d operands/instruction max)"),
4238 MAX_OPERANDS);
4239 return NULL;
4240 }
4241 i.types[this_operand].bitfield.unspecified = 1;
4242 /* Now parse operand adding info to 'i' as we go along. */
4243 END_STRING_AND_SAVE (l);
4244
4245 if (intel_syntax)
4246 operand_ok =
4247 i386_intel_operand (token_start,
4248 intel_float_operand (mnemonic));
4249 else
4250 operand_ok = i386_att_operand (token_start);
4251
4252 RESTORE_END_STRING (l);
4253 if (!operand_ok)
4254 return NULL;
4255 }
4256 else
4257 {
4258 if (expecting_operand)
4259 {
4260 expecting_operand_after_comma:
4261 as_bad (_("expecting operand after ','; got nothing"));
4262 return NULL;
4263 }
4264 if (*l == ',')
4265 {
4266 as_bad (_("expecting operand before ','; got nothing"));
4267 return NULL;
4268 }
4269 }
4270
4271 /* Now *l must be either ',' or END_OF_INSN. */
4272 if (*l == ',')
4273 {
4274 if (*++l == END_OF_INSN)
4275 {
4276 /* Just skip it, if it's \n complain. */
4277 goto expecting_operand_after_comma;
4278 }
4279 expecting_operand = 1;
4280 }
4281 }
4282 return l;
4283 }
4284
4285 static void
4286 swap_2_operands (int xchg1, int xchg2)
4287 {
4288 union i386_op temp_op;
4289 i386_operand_type temp_type;
4290 enum bfd_reloc_code_real temp_reloc;
4291
4292 temp_type = i.types[xchg2];
4293 i.types[xchg2] = i.types[xchg1];
4294 i.types[xchg1] = temp_type;
4295 temp_op = i.op[xchg2];
4296 i.op[xchg2] = i.op[xchg1];
4297 i.op[xchg1] = temp_op;
4298 temp_reloc = i.reloc[xchg2];
4299 i.reloc[xchg2] = i.reloc[xchg1];
4300 i.reloc[xchg1] = temp_reloc;
4301
4302 if (i.mask)
4303 {
4304 if (i.mask->operand == xchg1)
4305 i.mask->operand = xchg2;
4306 else if (i.mask->operand == xchg2)
4307 i.mask->operand = xchg1;
4308 }
4309 if (i.broadcast)
4310 {
4311 if (i.broadcast->operand == xchg1)
4312 i.broadcast->operand = xchg2;
4313 else if (i.broadcast->operand == xchg2)
4314 i.broadcast->operand = xchg1;
4315 }
4316 if (i.rounding)
4317 {
4318 if (i.rounding->operand == xchg1)
4319 i.rounding->operand = xchg2;
4320 else if (i.rounding->operand == xchg2)
4321 i.rounding->operand = xchg1;
4322 }
4323 }
4324
4325 static void
4326 swap_operands (void)
4327 {
4328 switch (i.operands)
4329 {
4330 case 5:
4331 case 4:
4332 swap_2_operands (1, i.operands - 2);
4333 /* Fall through. */
4334 case 3:
4335 case 2:
4336 swap_2_operands (0, i.operands - 1);
4337 break;
4338 default:
4339 abort ();
4340 }
4341
4342 if (i.mem_operands == 2)
4343 {
4344 const seg_entry *temp_seg;
4345 temp_seg = i.seg[0];
4346 i.seg[0] = i.seg[1];
4347 i.seg[1] = temp_seg;
4348 }
4349 }
4350
4351 /* Try to ensure constant immediates are represented in the smallest
4352 opcode possible. */
4353 static void
4354 optimize_imm (void)
4355 {
4356 char guess_suffix = 0;
4357 int op;
4358
4359 if (i.suffix)
4360 guess_suffix = i.suffix;
4361 else if (i.reg_operands)
4362 {
4363 /* Figure out a suffix from the last register operand specified.
4364 We can't do this properly yet, ie. excluding InOutPortReg,
4365 but the following works for instructions with immediates.
4366 In any case, we can't set i.suffix yet. */
4367 for (op = i.operands; --op >= 0;)
4368 if (i.types[op].bitfield.reg8)
4369 {
4370 guess_suffix = BYTE_MNEM_SUFFIX;
4371 break;
4372 }
4373 else if (i.types[op].bitfield.reg16)
4374 {
4375 guess_suffix = WORD_MNEM_SUFFIX;
4376 break;
4377 }
4378 else if (i.types[op].bitfield.reg32)
4379 {
4380 guess_suffix = LONG_MNEM_SUFFIX;
4381 break;
4382 }
4383 else if (i.types[op].bitfield.reg64)
4384 {
4385 guess_suffix = QWORD_MNEM_SUFFIX;
4386 break;
4387 }
4388 }
4389 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
4390 guess_suffix = WORD_MNEM_SUFFIX;
4391
4392 for (op = i.operands; --op >= 0;)
4393 if (operand_type_check (i.types[op], imm))
4394 {
4395 switch (i.op[op].imms->X_op)
4396 {
4397 case O_constant:
4398 /* If a suffix is given, this operand may be shortened. */
4399 switch (guess_suffix)
4400 {
4401 case LONG_MNEM_SUFFIX:
4402 i.types[op].bitfield.imm32 = 1;
4403 i.types[op].bitfield.imm64 = 1;
4404 break;
4405 case WORD_MNEM_SUFFIX:
4406 i.types[op].bitfield.imm16 = 1;
4407 i.types[op].bitfield.imm32 = 1;
4408 i.types[op].bitfield.imm32s = 1;
4409 i.types[op].bitfield.imm64 = 1;
4410 break;
4411 case BYTE_MNEM_SUFFIX:
4412 i.types[op].bitfield.imm8 = 1;
4413 i.types[op].bitfield.imm8s = 1;
4414 i.types[op].bitfield.imm16 = 1;
4415 i.types[op].bitfield.imm32 = 1;
4416 i.types[op].bitfield.imm32s = 1;
4417 i.types[op].bitfield.imm64 = 1;
4418 break;
4419 }
4420
4421 /* If this operand is at most 16 bits, convert it
4422 to a signed 16 bit number before trying to see
4423 whether it will fit in an even smaller size.
4424 This allows a 16-bit operand such as $0xffe0 to
4425 be recognised as within Imm8S range. */
4426 if ((i.types[op].bitfield.imm16)
4427 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
4428 {
4429 i.op[op].imms->X_add_number =
4430 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
4431 }
4432 #ifdef BFD64
4433 /* Store 32-bit immediate in 64-bit for 64-bit BFD. */
4434 if ((i.types[op].bitfield.imm32)
4435 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
4436 == 0))
4437 {
4438 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
4439 ^ ((offsetT) 1 << 31))
4440 - ((offsetT) 1 << 31));
4441 }
4442 #endif
4443 i.types[op]
4444 = operand_type_or (i.types[op],
4445 smallest_imm_type (i.op[op].imms->X_add_number));
4446
4447 /* We must avoid matching of Imm32 templates when 64bit
4448 only immediate is available. */
4449 if (guess_suffix == QWORD_MNEM_SUFFIX)
4450 i.types[op].bitfield.imm32 = 0;
4451 break;
4452
4453 case O_absent:
4454 case O_register:
4455 abort ();
4456
4457 /* Symbols and expressions. */
4458 default:
4459 /* Convert symbolic operand to proper sizes for matching, but don't
4460 prevent matching a set of insns that only supports sizes other
4461 than those matching the insn suffix. */
4462 {
4463 i386_operand_type mask, allowed;
4464 const insn_template *t;
4465
4466 operand_type_set (&mask, 0);
4467 operand_type_set (&allowed, 0);
4468
4469 for (t = current_templates->start;
4470 t < current_templates->end;
4471 ++t)
4472 allowed = operand_type_or (allowed,
4473 t->operand_types[op]);
4474 switch (guess_suffix)
4475 {
4476 case QWORD_MNEM_SUFFIX:
4477 mask.bitfield.imm64 = 1;
4478 mask.bitfield.imm32s = 1;
4479 break;
4480 case LONG_MNEM_SUFFIX:
4481 mask.bitfield.imm32 = 1;
4482 break;
4483 case WORD_MNEM_SUFFIX:
4484 mask.bitfield.imm16 = 1;
4485 break;
4486 case BYTE_MNEM_SUFFIX:
4487 mask.bitfield.imm8 = 1;
4488 break;
4489 default:
4490 break;
4491 }
4492 allowed = operand_type_and (mask, allowed);
4493 if (!operand_type_all_zero (&allowed))
4494 i.types[op] = operand_type_and (i.types[op], mask);
4495 }
4496 break;
4497 }
4498 }
4499 }
4500
4501 /* Try to use the smallest displacement type too. */
4502 static void
4503 optimize_disp (void)
4504 {
4505 int op;
4506
4507 for (op = i.operands; --op >= 0;)
4508 if (operand_type_check (i.types[op], disp))
4509 {
4510 if (i.op[op].disps->X_op == O_constant)
4511 {
4512 offsetT op_disp = i.op[op].disps->X_add_number;
4513
4514 if (i.types[op].bitfield.disp16
4515 && (op_disp & ~(offsetT) 0xffff) == 0)
4516 {
4517 /* If this operand is at most 16 bits, convert
4518 to a signed 16 bit number and don't use 64bit
4519 displacement. */
4520 op_disp = (((op_disp & 0xffff) ^ 0x8000) - 0x8000);
4521 i.types[op].bitfield.disp64 = 0;
4522 }
4523 #ifdef BFD64
4524 /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */
4525 if (i.types[op].bitfield.disp32
4526 && (op_disp & ~(((offsetT) 2 << 31) - 1)) == 0)
4527 {
4528 /* If this operand is at most 32 bits, convert
4529 to a signed 32 bit number and don't use 64bit
4530 displacement. */
4531 op_disp &= (((offsetT) 2 << 31) - 1);
4532 op_disp = (op_disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
4533 i.types[op].bitfield.disp64 = 0;
4534 }
4535 #endif
4536 if (!op_disp && i.types[op].bitfield.baseindex)
4537 {
4538 i.types[op].bitfield.disp8 = 0;
4539 i.types[op].bitfield.disp16 = 0;
4540 i.types[op].bitfield.disp32 = 0;
4541 i.types[op].bitfield.disp32s = 0;
4542 i.types[op].bitfield.disp64 = 0;
4543 i.op[op].disps = 0;
4544 i.disp_operands--;
4545 }
4546 else if (flag_code == CODE_64BIT)
4547 {
4548 if (fits_in_signed_long (op_disp))
4549 {
4550 i.types[op].bitfield.disp64 = 0;
4551 i.types[op].bitfield.disp32s = 1;
4552 }
4553 if (i.prefix[ADDR_PREFIX]
4554 && fits_in_unsigned_long (op_disp))
4555 i.types[op].bitfield.disp32 = 1;
4556 }
4557 if ((i.types[op].bitfield.disp32
4558 || i.types[op].bitfield.disp32s
4559 || i.types[op].bitfield.disp16)
4560 && fits_in_signed_byte (op_disp))
4561 i.types[op].bitfield.disp8 = 1;
4562 }
4563 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
4564 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
4565 {
4566 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
4567 i.op[op].disps, 0, i.reloc[op]);
4568 i.types[op].bitfield.disp8 = 0;
4569 i.types[op].bitfield.disp16 = 0;
4570 i.types[op].bitfield.disp32 = 0;
4571 i.types[op].bitfield.disp32s = 0;
4572 i.types[op].bitfield.disp64 = 0;
4573 }
4574 else
4575 /* We only support 64bit displacement on constants. */
4576 i.types[op].bitfield.disp64 = 0;
4577 }
4578 }
4579
4580 /* Check if operands are valid for the instruction. */
4581
4582 static int
4583 check_VecOperands (const insn_template *t)
4584 {
4585 unsigned int op;
4586
4587 /* Without VSIB byte, we can't have a vector register for index. */
4588 if (!t->opcode_modifier.vecsib
4589 && i.index_reg
4590 && (i.index_reg->reg_type.bitfield.regxmm
4591 || i.index_reg->reg_type.bitfield.regymm
4592 || i.index_reg->reg_type.bitfield.regzmm))
4593 {
4594 i.error = unsupported_vector_index_register;
4595 return 1;
4596 }
4597
4598 /* Check if default mask is allowed. */
4599 if (t->opcode_modifier.nodefmask
4600 && (!i.mask || i.mask->mask->reg_num == 0))
4601 {
4602 i.error = no_default_mask;
4603 return 1;
4604 }
4605
4606 /* For VSIB byte, we need a vector register for index, and all vector
4607 registers must be distinct. */
4608 if (t->opcode_modifier.vecsib)
4609 {
4610 if (!i.index_reg
4611 || !((t->opcode_modifier.vecsib == VecSIB128
4612 && i.index_reg->reg_type.bitfield.regxmm)
4613 || (t->opcode_modifier.vecsib == VecSIB256
4614 && i.index_reg->reg_type.bitfield.regymm)
4615 || (t->opcode_modifier.vecsib == VecSIB512
4616 && i.index_reg->reg_type.bitfield.regzmm)))
4617 {
4618 i.error = invalid_vsib_address;
4619 return 1;
4620 }
4621
4622 gas_assert (i.reg_operands == 2 || i.mask);
4623 if (i.reg_operands == 2 && !i.mask)
4624 {
4625 gas_assert (i.types[0].bitfield.regxmm
4626 || i.types[0].bitfield.regymm);
4627 gas_assert (i.types[2].bitfield.regxmm
4628 || i.types[2].bitfield.regymm);
4629 if (operand_check == check_none)
4630 return 0;
4631 if (register_number (i.op[0].regs)
4632 != register_number (i.index_reg)
4633 && register_number (i.op[2].regs)
4634 != register_number (i.index_reg)
4635 && register_number (i.op[0].regs)
4636 != register_number (i.op[2].regs))
4637 return 0;
4638 if (operand_check == check_error)
4639 {
4640 i.error = invalid_vector_register_set;
4641 return 1;
4642 }
4643 as_warn (_("mask, index, and destination registers should be distinct"));
4644 }
4645 else if (i.reg_operands == 1 && i.mask)
4646 {
4647 if ((i.types[1].bitfield.regymm
4648 || i.types[1].bitfield.regzmm)
4649 && (register_number (i.op[1].regs)
4650 == register_number (i.index_reg)))
4651 {
4652 if (operand_check == check_error)
4653 {
4654 i.error = invalid_vector_register_set;
4655 return 1;
4656 }
4657 if (operand_check != check_none)
4658 as_warn (_("index and destination registers should be distinct"));
4659 }
4660 }
4661 }
4662
4663 /* Check if broadcast is supported by the instruction and is applied
4664 to the memory operand. */
4665 if (i.broadcast)
4666 {
4667 int broadcasted_opnd_size;
4668
4669 /* Check if specified broadcast is supported in this instruction,
4670 and it's applied to memory operand of DWORD or QWORD type,
4671 depending on VecESize. */
4672 if (i.broadcast->type != t->opcode_modifier.broadcast
4673 || !i.types[i.broadcast->operand].bitfield.mem
4674 || (t->opcode_modifier.vecesize == 0
4675 && !i.types[i.broadcast->operand].bitfield.dword
4676 && !i.types[i.broadcast->operand].bitfield.unspecified)
4677 || (t->opcode_modifier.vecesize == 1
4678 && !i.types[i.broadcast->operand].bitfield.qword
4679 && !i.types[i.broadcast->operand].bitfield.unspecified))
4680 goto bad_broadcast;
4681
4682 broadcasted_opnd_size = t->opcode_modifier.vecesize ? 64 : 32;
4683 if (i.broadcast->type == BROADCAST_1TO16)
4684 broadcasted_opnd_size <<= 4; /* Broadcast 1to16. */
4685 else if (i.broadcast->type == BROADCAST_1TO8)
4686 broadcasted_opnd_size <<= 3; /* Broadcast 1to8. */
4687 else if (i.broadcast->type == BROADCAST_1TO4)
4688 broadcasted_opnd_size <<= 2; /* Broadcast 1to4. */
4689 else if (i.broadcast->type == BROADCAST_1TO2)
4690 broadcasted_opnd_size <<= 1; /* Broadcast 1to2. */
4691 else
4692 goto bad_broadcast;
4693
4694 if ((broadcasted_opnd_size == 256
4695 && !t->operand_types[i.broadcast->operand].bitfield.ymmword)
4696 || (broadcasted_opnd_size == 512
4697 && !t->operand_types[i.broadcast->operand].bitfield.zmmword))
4698 {
4699 bad_broadcast:
4700 i.error = unsupported_broadcast;
4701 return 1;
4702 }
4703 }
4704 /* If broadcast is supported in this instruction, we need to check if
4705 operand of one-element size isn't specified without broadcast. */
4706 else if (t->opcode_modifier.broadcast && i.mem_operands)
4707 {
4708 /* Find memory operand. */
4709 for (op = 0; op < i.operands; op++)
4710 if (operand_type_check (i.types[op], anymem))
4711 break;
4712 gas_assert (op < i.operands);
4713 /* Check size of the memory operand. */
4714 if ((t->opcode_modifier.vecesize == 0
4715 && i.types[op].bitfield.dword)
4716 || (t->opcode_modifier.vecesize == 1
4717 && i.types[op].bitfield.qword))
4718 {
4719 i.error = broadcast_needed;
4720 return 1;
4721 }
4722 }
4723
4724 /* Check if requested masking is supported. */
4725 if (i.mask
4726 && (!t->opcode_modifier.masking
4727 || (i.mask->zeroing
4728 && t->opcode_modifier.masking == MERGING_MASKING)))
4729 {
4730 i.error = unsupported_masking;
4731 return 1;
4732 }
4733
4734 /* Check if masking is applied to dest operand. */
4735 if (i.mask && (i.mask->operand != (int) (i.operands - 1)))
4736 {
4737 i.error = mask_not_on_destination;
4738 return 1;
4739 }
4740
4741 /* Check RC/SAE. */
4742 if (i.rounding)
4743 {
4744 if ((i.rounding->type != saeonly
4745 && !t->opcode_modifier.staticrounding)
4746 || (i.rounding->type == saeonly
4747 && (t->opcode_modifier.staticrounding
4748 || !t->opcode_modifier.sae)))
4749 {
4750 i.error = unsupported_rc_sae;
4751 return 1;
4752 }
4753 /* If the instruction has several immediate operands and one of
4754 them is rounding, the rounding operand should be the last
4755 immediate operand. */
4756 if (i.imm_operands > 1
4757 && i.rounding->operand != (int) (i.imm_operands - 1))
4758 {
4759 i.error = rc_sae_operand_not_last_imm;
4760 return 1;
4761 }
4762 }
4763
4764 /* Check vector Disp8 operand. */
4765 if (t->opcode_modifier.disp8memshift)
4766 {
4767 if (i.broadcast)
4768 i.memshift = t->opcode_modifier.vecesize ? 3 : 2;
4769 else
4770 i.memshift = t->opcode_modifier.disp8memshift;
4771
4772 for (op = 0; op < i.operands; op++)
4773 if (operand_type_check (i.types[op], disp)
4774 && i.op[op].disps->X_op == O_constant)
4775 {
4776 offsetT value = i.op[op].disps->X_add_number;
4777 int vec_disp8_ok
4778 = (i.disp_encoding != disp_encoding_32bit
4779 && fits_in_vec_disp8 (value));
4780 if (t->operand_types [op].bitfield.vec_disp8)
4781 {
4782 if (vec_disp8_ok)
4783 i.types[op].bitfield.vec_disp8 = 1;
4784 else
4785 {
4786 /* Vector insn can only have Vec_Disp8/Disp32 in
4787 32/64bit modes, and Vec_Disp8/Disp16 in 16bit
4788 mode. */
4789 i.types[op].bitfield.disp8 = 0;
4790 if (flag_code != CODE_16BIT)
4791 i.types[op].bitfield.disp16 = 0;
4792 }
4793 }
4794 else if (flag_code != CODE_16BIT)
4795 {
4796 /* One form of this instruction supports vector Disp8.
4797 Try vector Disp8 if we need to use Disp32. */
4798 if (vec_disp8_ok && !fits_in_signed_byte (value))
4799 {
4800 i.error = try_vector_disp8;
4801 return 1;
4802 }
4803 }
4804 }
4805 }
4806 else
4807 i.memshift = -1;
4808
4809 return 0;
4810 }
4811
4812 /* Check if operands are valid for the instruction. Update VEX
4813 operand types. */
4814
4815 static int
4816 VEX_check_operands (const insn_template *t)
4817 {
4818 if (i.vec_encoding == vex_encoding_evex)
4819 {
4820 /* This instruction must be encoded with EVEX prefix. */
4821 if (!t->opcode_modifier.evex)
4822 {
4823 i.error = unsupported;
4824 return 1;
4825 }
4826 return 0;
4827 }
4828
4829 if (!t->opcode_modifier.vex)
4830 {
4831 /* This instruction template doesn't have VEX prefix. */
4832 if (i.vec_encoding != vex_encoding_default)
4833 {
4834 i.error = unsupported;
4835 return 1;
4836 }
4837 return 0;
4838 }
4839
4840 /* Only check VEX_Imm4, which must be the first operand. */
4841 if (t->operand_types[0].bitfield.vec_imm4)
4842 {
4843 if (i.op[0].imms->X_op != O_constant
4844 || !fits_in_imm4 (i.op[0].imms->X_add_number))
4845 {
4846 i.error = bad_imm4;
4847 return 1;
4848 }
4849
4850 /* Turn off Imm8 so that update_imm won't complain. */
4851 i.types[0] = vec_imm4;
4852 }
4853
4854 return 0;
4855 }
4856
4857 static const insn_template *
4858 match_template (char mnem_suffix)
4859 {
4860 /* Points to template once we've found it. */
4861 const insn_template *t;
4862 i386_operand_type overlap0, overlap1, overlap2, overlap3;
4863 i386_operand_type overlap4;
4864 unsigned int found_reverse_match;
4865 i386_opcode_modifier suffix_check, mnemsuf_check;
4866 i386_operand_type operand_types [MAX_OPERANDS];
4867 int addr_prefix_disp;
4868 unsigned int j;
4869 unsigned int found_cpu_match;
4870 unsigned int check_register;
4871 enum i386_error specific_error = 0;
4872
4873 #if MAX_OPERANDS != 5
4874 # error "MAX_OPERANDS must be 5."
4875 #endif
4876
4877 found_reverse_match = 0;
4878 addr_prefix_disp = -1;
4879
4880 memset (&suffix_check, 0, sizeof (suffix_check));
4881 if (i.suffix == BYTE_MNEM_SUFFIX)
4882 suffix_check.no_bsuf = 1;
4883 else if (i.suffix == WORD_MNEM_SUFFIX)
4884 suffix_check.no_wsuf = 1;
4885 else if (i.suffix == SHORT_MNEM_SUFFIX)
4886 suffix_check.no_ssuf = 1;
4887 else if (i.suffix == LONG_MNEM_SUFFIX)
4888 suffix_check.no_lsuf = 1;
4889 else if (i.suffix == QWORD_MNEM_SUFFIX)
4890 suffix_check.no_qsuf = 1;
4891 else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX)
4892 suffix_check.no_ldsuf = 1;
4893
4894 memset (&mnemsuf_check, 0, sizeof (mnemsuf_check));
4895 if (intel_syntax)
4896 {
4897 switch (mnem_suffix)
4898 {
4899 case BYTE_MNEM_SUFFIX: mnemsuf_check.no_bsuf = 1; break;
4900 case WORD_MNEM_SUFFIX: mnemsuf_check.no_wsuf = 1; break;
4901 case SHORT_MNEM_SUFFIX: mnemsuf_check.no_ssuf = 1; break;
4902 case LONG_MNEM_SUFFIX: mnemsuf_check.no_lsuf = 1; break;
4903 case QWORD_MNEM_SUFFIX: mnemsuf_check.no_qsuf = 1; break;
4904 }
4905 }
4906
4907 /* Must have right number of operands. */
4908 i.error = number_of_operands_mismatch;
4909
4910 for (t = current_templates->start; t < current_templates->end; t++)
4911 {
4912 addr_prefix_disp = -1;
4913
4914 if (i.operands != t->operands)
4915 continue;
4916
4917 /* Check processor support. */
4918 i.error = unsupported;
4919 found_cpu_match = (cpu_flags_match (t)
4920 == CPU_FLAGS_PERFECT_MATCH);
4921 if (!found_cpu_match)
4922 continue;
4923
4924 /* Check old gcc support. */
4925 i.error = old_gcc_only;
4926 if (!old_gcc && t->opcode_modifier.oldgcc)
4927 continue;
4928
4929 /* Check AT&T mnemonic. */
4930 i.error = unsupported_with_intel_mnemonic;
4931 if (intel_mnemonic && t->opcode_modifier.attmnemonic)
4932 continue;
4933
4934 /* Check AT&T/Intel syntax and Intel64/AMD64 ISA. */
4935 i.error = unsupported_syntax;
4936 if ((intel_syntax && t->opcode_modifier.attsyntax)
4937 || (!intel_syntax && t->opcode_modifier.intelsyntax)
4938 || (intel64 && t->opcode_modifier.amd64)
4939 || (!intel64 && t->opcode_modifier.intel64))
4940 continue;
4941
4942 /* Check the suffix, except for some instructions in intel mode. */
4943 i.error = invalid_instruction_suffix;
4944 if ((!intel_syntax || !t->opcode_modifier.ignoresize)
4945 && ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf)
4946 || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf)
4947 || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf)
4948 || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf)
4949 || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf)
4950 || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf)))
4951 continue;
4952 /* In Intel mode all mnemonic suffixes must be explicitly allowed. */
4953 if ((t->opcode_modifier.no_bsuf && mnemsuf_check.no_bsuf)
4954 || (t->opcode_modifier.no_wsuf && mnemsuf_check.no_wsuf)
4955 || (t->opcode_modifier.no_lsuf && mnemsuf_check.no_lsuf)
4956 || (t->opcode_modifier.no_ssuf && mnemsuf_check.no_ssuf)
4957 || (t->opcode_modifier.no_qsuf && mnemsuf_check.no_qsuf)
4958 || (t->opcode_modifier.no_ldsuf && mnemsuf_check.no_ldsuf))
4959 continue;
4960
4961 if (!operand_size_match (t))
4962 continue;
4963
4964 for (j = 0; j < MAX_OPERANDS; j++)
4965 operand_types[j] = t->operand_types[j];
4966
4967 /* In general, don't allow 64-bit operands in 32-bit mode. */
4968 if (i.suffix == QWORD_MNEM_SUFFIX
4969 && flag_code != CODE_64BIT
4970 && (intel_syntax
4971 ? (!t->opcode_modifier.ignoresize
4972 && !intel_float_operand (t->name))
4973 : intel_float_operand (t->name) != 2)
4974 && ((!operand_types[0].bitfield.regmmx
4975 && !operand_types[0].bitfield.regxmm
4976 && !operand_types[0].bitfield.regymm
4977 && !operand_types[0].bitfield.regzmm)
4978 || (!operand_types[t->operands > 1].bitfield.regmmx
4979 && operand_types[t->operands > 1].bitfield.regxmm
4980 && operand_types[t->operands > 1].bitfield.regymm
4981 && operand_types[t->operands > 1].bitfield.regzmm))
4982 && (t->base_opcode != 0x0fc7
4983 || t->extension_opcode != 1 /* cmpxchg8b */))
4984 continue;
4985
4986 /* In general, don't allow 32-bit operands on pre-386. */
4987 else if (i.suffix == LONG_MNEM_SUFFIX
4988 && !cpu_arch_flags.bitfield.cpui386
4989 && (intel_syntax
4990 ? (!t->opcode_modifier.ignoresize
4991 && !intel_float_operand (t->name))
4992 : intel_float_operand (t->name) != 2)
4993 && ((!operand_types[0].bitfield.regmmx
4994 && !operand_types[0].bitfield.regxmm)
4995 || (!operand_types[t->operands > 1].bitfield.regmmx
4996 && operand_types[t->operands > 1].bitfield.regxmm)))
4997 continue;
4998
4999 /* Do not verify operands when there are none. */
5000 else
5001 {
5002 if (!t->operands)
5003 /* We've found a match; break out of loop. */
5004 break;
5005 }
5006
5007 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
5008 into Disp32/Disp16/Disp32 operand. */
5009 if (i.prefix[ADDR_PREFIX] != 0)
5010 {
5011 /* There should be only one Disp operand. */
5012 switch (flag_code)
5013 {
5014 case CODE_16BIT:
5015 for (j = 0; j < MAX_OPERANDS; j++)
5016 {
5017 if (operand_types[j].bitfield.disp16)
5018 {
5019 addr_prefix_disp = j;
5020 operand_types[j].bitfield.disp32 = 1;
5021 operand_types[j].bitfield.disp16 = 0;
5022 break;
5023 }
5024 }
5025 break;
5026 case CODE_32BIT:
5027 for (j = 0; j < MAX_OPERANDS; j++)
5028 {
5029 if (operand_types[j].bitfield.disp32)
5030 {
5031 addr_prefix_disp = j;
5032 operand_types[j].bitfield.disp32 = 0;
5033 operand_types[j].bitfield.disp16 = 1;
5034 break;
5035 }
5036 }
5037 break;
5038 case CODE_64BIT:
5039 for (j = 0; j < MAX_OPERANDS; j++)
5040 {
5041 if (operand_types[j].bitfield.disp64)
5042 {
5043 addr_prefix_disp = j;
5044 operand_types[j].bitfield.disp64 = 0;
5045 operand_types[j].bitfield.disp32 = 1;
5046 break;
5047 }
5048 }
5049 break;
5050 }
5051 }
5052
5053 /* Force 0x8b encoding for "mov foo@GOT, %eax". */
5054 if (i.reloc[0] == BFD_RELOC_386_GOT32 && t->base_opcode == 0xa0)
5055 continue;
5056
5057 /* We check register size if needed. */
5058 check_register = t->opcode_modifier.checkregsize;
5059 overlap0 = operand_type_and (i.types[0], operand_types[0]);
5060 switch (t->operands)
5061 {
5062 case 1:
5063 if (!operand_type_match (overlap0, i.types[0]))
5064 continue;
5065 break;
5066 case 2:
5067 /* xchg %eax, %eax is a special case. It is an alias for nop
5068 only in 32bit mode and we can use opcode 0x90. In 64bit
5069 mode, we can't use 0x90 for xchg %eax, %eax since it should
5070 zero-extend %eax to %rax. */
5071 if (flag_code == CODE_64BIT
5072 && t->base_opcode == 0x90
5073 && operand_type_equal (&i.types [0], &acc32)
5074 && operand_type_equal (&i.types [1], &acc32))
5075 continue;
5076 /* If we want store form, we reverse direction of operands. */
5077 if (i.dir_encoding == dir_encoding_store
5078 && t->opcode_modifier.d)
5079 goto check_reverse;
5080 /* Fall through. */
5081
5082 case 3:
5083 /* If we want store form, we skip the current load. */
5084 if (i.dir_encoding == dir_encoding_store
5085 && i.mem_operands == 0
5086 && t->opcode_modifier.load)
5087 continue;
5088 /* Fall through. */
5089 case 4:
5090 case 5:
5091 overlap1 = operand_type_and (i.types[1], operand_types[1]);
5092 if (!operand_type_match (overlap0, i.types[0])
5093 || !operand_type_match (overlap1, i.types[1])
5094 || (check_register
5095 && !operand_type_register_match (overlap0, i.types[0],
5096 operand_types[0],
5097 overlap1, i.types[1],
5098 operand_types[1])))
5099 {
5100 /* Check if other direction is valid ... */
5101 if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
5102 continue;
5103
5104 check_reverse:
5105 /* Try reversing direction of operands. */
5106 overlap0 = operand_type_and (i.types[0], operand_types[1]);
5107 overlap1 = operand_type_and (i.types[1], operand_types[0]);
5108 if (!operand_type_match (overlap0, i.types[0])
5109 || !operand_type_match (overlap1, i.types[1])
5110 || (check_register
5111 && !operand_type_register_match (overlap0,
5112 i.types[0],
5113 operand_types[1],
5114 overlap1,
5115 i.types[1],
5116 operand_types[0])))
5117 {
5118 /* Does not match either direction. */
5119 continue;
5120 }
5121 /* found_reverse_match holds which of D or FloatDR
5122 we've found. */
5123 if (t->opcode_modifier.d)
5124 found_reverse_match = Opcode_D;
5125 else if (t->opcode_modifier.floatd)
5126 found_reverse_match = Opcode_FloatD;
5127 else
5128 found_reverse_match = 0;
5129 if (t->opcode_modifier.floatr)
5130 found_reverse_match |= Opcode_FloatR;
5131 }
5132 else
5133 {
5134 /* Found a forward 2 operand match here. */
5135 switch (t->operands)
5136 {
5137 case 5:
5138 overlap4 = operand_type_and (i.types[4],
5139 operand_types[4]);
5140 /* Fall through. */
5141 case 4:
5142 overlap3 = operand_type_and (i.types[3],
5143 operand_types[3]);
5144 /* Fall through. */
5145 case 3:
5146 overlap2 = operand_type_and (i.types[2],
5147 operand_types[2]);
5148 break;
5149 }
5150
5151 switch (t->operands)
5152 {
5153 case 5:
5154 if (!operand_type_match (overlap4, i.types[4])
5155 || !operand_type_register_match (overlap3,
5156 i.types[3],
5157 operand_types[3],
5158 overlap4,
5159 i.types[4],
5160 operand_types[4]))
5161 continue;
5162 /* Fall through. */
5163 case 4:
5164 if (!operand_type_match (overlap3, i.types[3])
5165 || (check_register
5166 && !operand_type_register_match (overlap2,
5167 i.types[2],
5168 operand_types[2],
5169 overlap3,
5170 i.types[3],
5171 operand_types[3])))
5172 continue;
5173 /* Fall through. */
5174 case 3:
5175 /* Here we make use of the fact that there are no
5176 reverse match 3 operand instructions, and all 3
5177 operand instructions only need to be checked for
5178 register consistency between operands 2 and 3. */
5179 if (!operand_type_match (overlap2, i.types[2])
5180 || (check_register
5181 && !operand_type_register_match (overlap1,
5182 i.types[1],
5183 operand_types[1],
5184 overlap2,
5185 i.types[2],
5186 operand_types[2])))
5187 continue;
5188 break;
5189 }
5190 }
5191 /* Found either forward/reverse 2, 3 or 4 operand match here:
5192 slip through to break. */
5193 }
5194 if (!found_cpu_match)
5195 {
5196 found_reverse_match = 0;
5197 continue;
5198 }
5199
5200 /* Check if vector and VEX operands are valid. */
5201 if (check_VecOperands (t) || VEX_check_operands (t))
5202 {
5203 specific_error = i.error;
5204 continue;
5205 }
5206
5207 /* We've found a match; break out of loop. */
5208 break;
5209 }
5210
5211 if (t == current_templates->end)
5212 {
5213 /* We found no match. */
5214 const char *err_msg;
5215 switch (specific_error ? specific_error : i.error)
5216 {
5217 default:
5218 abort ();
5219 case operand_size_mismatch:
5220 err_msg = _("operand size mismatch");
5221 break;
5222 case operand_type_mismatch:
5223 err_msg = _("operand type mismatch");
5224 break;
5225 case register_type_mismatch:
5226 err_msg = _("register type mismatch");
5227 break;
5228 case number_of_operands_mismatch:
5229 err_msg = _("number of operands mismatch");
5230 break;
5231 case invalid_instruction_suffix:
5232 err_msg = _("invalid instruction suffix");
5233 break;
5234 case bad_imm4:
5235 err_msg = _("constant doesn't fit in 4 bits");
5236 break;
5237 case old_gcc_only:
5238 err_msg = _("only supported with old gcc");
5239 break;
5240 case unsupported_with_intel_mnemonic:
5241 err_msg = _("unsupported with Intel mnemonic");
5242 break;
5243 case unsupported_syntax:
5244 err_msg = _("unsupported syntax");
5245 break;
5246 case unsupported:
5247 as_bad (_("unsupported instruction `%s'"),
5248 current_templates->start->name);
5249 return NULL;
5250 case invalid_vsib_address:
5251 err_msg = _("invalid VSIB address");
5252 break;
5253 case invalid_vector_register_set:
5254 err_msg = _("mask, index, and destination registers must be distinct");
5255 break;
5256 case unsupported_vector_index_register:
5257 err_msg = _("unsupported vector index register");
5258 break;
5259 case unsupported_broadcast:
5260 err_msg = _("unsupported broadcast");
5261 break;
5262 case broadcast_not_on_src_operand:
5263 err_msg = _("broadcast not on source memory operand");
5264 break;
5265 case broadcast_needed:
5266 err_msg = _("broadcast is needed for operand of such type");
5267 break;
5268 case unsupported_masking:
5269 err_msg = _("unsupported masking");
5270 break;
5271 case mask_not_on_destination:
5272 err_msg = _("mask not on destination operand");
5273 break;
5274 case no_default_mask:
5275 err_msg = _("default mask isn't allowed");
5276 break;
5277 case unsupported_rc_sae:
5278 err_msg = _("unsupported static rounding/sae");
5279 break;
5280 case rc_sae_operand_not_last_imm:
5281 if (intel_syntax)
5282 err_msg = _("RC/SAE operand must precede immediate operands");
5283 else
5284 err_msg = _("RC/SAE operand must follow immediate operands");
5285 break;
5286 case invalid_register_operand:
5287 err_msg = _("invalid register operand");
5288 break;
5289 }
5290 as_bad (_("%s for `%s'"), err_msg,
5291 current_templates->start->name);
5292 return NULL;
5293 }
5294
5295 if (!quiet_warnings)
5296 {
5297 if (!intel_syntax
5298 && (i.types[0].bitfield.jumpabsolute
5299 != operand_types[0].bitfield.jumpabsolute))
5300 {
5301 as_warn (_("indirect %s without `*'"), t->name);
5302 }
5303
5304 if (t->opcode_modifier.isprefix
5305 && t->opcode_modifier.ignoresize)
5306 {
5307 /* Warn them that a data or address size prefix doesn't
5308 affect assembly of the next line of code. */
5309 as_warn (_("stand-alone `%s' prefix"), t->name);
5310 }
5311 }
5312
5313 /* Copy the template we found. */
5314 i.tm = *t;
5315
5316 if (addr_prefix_disp != -1)
5317 i.tm.operand_types[addr_prefix_disp]
5318 = operand_types[addr_prefix_disp];
5319
5320 if (found_reverse_match)
5321 {
5322 /* If we found a reverse match we must alter the opcode
5323 direction bit. found_reverse_match holds bits to change
5324 (different for int & float insns). */
5325
5326 i.tm.base_opcode ^= found_reverse_match;
5327
5328 i.tm.operand_types[0] = operand_types[1];
5329 i.tm.operand_types[1] = operand_types[0];
5330 }
5331
5332 return t;
5333 }
5334
5335 static int
5336 check_string (void)
5337 {
5338 int mem_op = operand_type_check (i.types[0], anymem) ? 0 : 1;
5339 if (i.tm.operand_types[mem_op].bitfield.esseg)
5340 {
5341 if (i.seg[0] != NULL && i.seg[0] != &es)
5342 {
5343 as_bad (_("`%s' operand %d must use `%ses' segment"),
5344 i.tm.name,
5345 mem_op + 1,
5346 register_prefix);
5347 return 0;
5348 }
5349 /* There's only ever one segment override allowed per instruction.
5350 This instruction possibly has a legal segment override on the
5351 second operand, so copy the segment to where non-string
5352 instructions store it, allowing common code. */
5353 i.seg[0] = i.seg[1];
5354 }
5355 else if (i.tm.operand_types[mem_op + 1].bitfield.esseg)
5356 {
5357 if (i.seg[1] != NULL && i.seg[1] != &es)
5358 {
5359 as_bad (_("`%s' operand %d must use `%ses' segment"),
5360 i.tm.name,
5361 mem_op + 2,
5362 register_prefix);
5363 return 0;
5364 }
5365 }
5366 return 1;
5367 }
5368
5369 static int
5370 process_suffix (void)
5371 {
5372 /* If matched instruction specifies an explicit instruction mnemonic
5373 suffix, use it. */
5374 if (i.tm.opcode_modifier.size16)
5375 i.suffix = WORD_MNEM_SUFFIX;
5376 else if (i.tm.opcode_modifier.size32)
5377 i.suffix = LONG_MNEM_SUFFIX;
5378 else if (i.tm.opcode_modifier.size64)
5379 i.suffix = QWORD_MNEM_SUFFIX;
5380 else if (i.reg_operands)
5381 {
5382 /* If there's no instruction mnemonic suffix we try to invent one
5383 based on register operands. */
5384 if (!i.suffix)
5385 {
5386 /* We take i.suffix from the last register operand specified,
5387 Destination register type is more significant than source
5388 register type. crc32 in SSE4.2 prefers source register
5389 type. */
5390 if (i.tm.base_opcode == 0xf20f38f1)
5391 {
5392 if (i.types[0].bitfield.reg16)
5393 i.suffix = WORD_MNEM_SUFFIX;
5394 else if (i.types[0].bitfield.reg32)
5395 i.suffix = LONG_MNEM_SUFFIX;
5396 else if (i.types[0].bitfield.reg64)
5397 i.suffix = QWORD_MNEM_SUFFIX;
5398 }
5399 else if (i.tm.base_opcode == 0xf20f38f0)
5400 {
5401 if (i.types[0].bitfield.reg8)
5402 i.suffix = BYTE_MNEM_SUFFIX;
5403 }
5404
5405 if (!i.suffix)
5406 {
5407 int op;
5408
5409 if (i.tm.base_opcode == 0xf20f38f1
5410 || i.tm.base_opcode == 0xf20f38f0)
5411 {
5412 /* We have to know the operand size for crc32. */
5413 as_bad (_("ambiguous memory operand size for `%s`"),
5414 i.tm.name);
5415 return 0;
5416 }
5417
5418 for (op = i.operands; --op >= 0;)
5419 if (!i.tm.operand_types[op].bitfield.inoutportreg)
5420 {
5421 if (i.types[op].bitfield.reg8)
5422 {
5423 i.suffix = BYTE_MNEM_SUFFIX;
5424 break;
5425 }
5426 else if (i.types[op].bitfield.reg16)
5427 {
5428 i.suffix = WORD_MNEM_SUFFIX;
5429 break;
5430 }
5431 else if (i.types[op].bitfield.reg32)
5432 {
5433 i.suffix = LONG_MNEM_SUFFIX;
5434 break;
5435 }
5436 else if (i.types[op].bitfield.reg64)
5437 {
5438 i.suffix = QWORD_MNEM_SUFFIX;
5439 break;
5440 }
5441 }
5442 }
5443 }
5444 else if (i.suffix == BYTE_MNEM_SUFFIX)
5445 {
5446 if (intel_syntax
5447 && i.tm.opcode_modifier.ignoresize
5448 && i.tm.opcode_modifier.no_bsuf)
5449 i.suffix = 0;
5450 else if (!check_byte_reg ())
5451 return 0;
5452 }
5453 else if (i.suffix == LONG_MNEM_SUFFIX)
5454 {
5455 if (intel_syntax
5456 && i.tm.opcode_modifier.ignoresize
5457 && i.tm.opcode_modifier.no_lsuf)
5458 i.suffix = 0;
5459 else if (!check_long_reg ())
5460 return 0;
5461 }
5462 else if (i.suffix == QWORD_MNEM_SUFFIX)
5463 {
5464 if (intel_syntax
5465 && i.tm.opcode_modifier.ignoresize
5466 && i.tm.opcode_modifier.no_qsuf)
5467 i.suffix = 0;
5468 else if (!check_qword_reg ())
5469 return 0;
5470 }
5471 else if (i.suffix == WORD_MNEM_SUFFIX)
5472 {
5473 if (intel_syntax
5474 && i.tm.opcode_modifier.ignoresize
5475 && i.tm.opcode_modifier.no_wsuf)
5476 i.suffix = 0;
5477 else if (!check_word_reg ())
5478 return 0;
5479 }
5480 else if (i.suffix == XMMWORD_MNEM_SUFFIX
5481 || i.suffix == YMMWORD_MNEM_SUFFIX
5482 || i.suffix == ZMMWORD_MNEM_SUFFIX)
5483 {
5484 /* Skip if the instruction has x/y/z suffix. match_template
5485 should check if it is a valid suffix. */
5486 }
5487 else if (intel_syntax && i.tm.opcode_modifier.ignoresize)
5488 /* Do nothing if the instruction is going to ignore the prefix. */
5489 ;
5490 else
5491 abort ();
5492 }
5493 else if (i.tm.opcode_modifier.defaultsize
5494 && !i.suffix
5495 /* exclude fldenv/frstor/fsave/fstenv */
5496 && i.tm.opcode_modifier.no_ssuf)
5497 {
5498 i.suffix = stackop_size;
5499 }
5500 else if (intel_syntax
5501 && !i.suffix
5502 && (i.tm.operand_types[0].bitfield.jumpabsolute
5503 || i.tm.opcode_modifier.jumpbyte
5504 || i.tm.opcode_modifier.jumpintersegment
5505 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
5506 && i.tm.extension_opcode <= 3)))
5507 {
5508 switch (flag_code)
5509 {
5510 case CODE_64BIT:
5511 if (!i.tm.opcode_modifier.no_qsuf)
5512 {
5513 i.suffix = QWORD_MNEM_SUFFIX;
5514 break;
5515 }
5516 /* Fall through. */
5517 case CODE_32BIT:
5518 if (!i.tm.opcode_modifier.no_lsuf)
5519 i.suffix = LONG_MNEM_SUFFIX;
5520 break;
5521 case CODE_16BIT:
5522 if (!i.tm.opcode_modifier.no_wsuf)
5523 i.suffix = WORD_MNEM_SUFFIX;
5524 break;
5525 }
5526 }
5527
5528 if (!i.suffix)
5529 {
5530 if (!intel_syntax)
5531 {
5532 if (i.tm.opcode_modifier.w)
5533 {
5534 as_bad (_("no instruction mnemonic suffix given and "
5535 "no register operands; can't size instruction"));
5536 return 0;
5537 }
5538 }
5539 else
5540 {
5541 unsigned int suffixes;
5542
5543 suffixes = !i.tm.opcode_modifier.no_bsuf;
5544 if (!i.tm.opcode_modifier.no_wsuf)
5545 suffixes |= 1 << 1;
5546 if (!i.tm.opcode_modifier.no_lsuf)
5547 suffixes |= 1 << 2;
5548 if (!i.tm.opcode_modifier.no_ldsuf)
5549 suffixes |= 1 << 3;
5550 if (!i.tm.opcode_modifier.no_ssuf)
5551 suffixes |= 1 << 4;
5552 if (!i.tm.opcode_modifier.no_qsuf)
5553 suffixes |= 1 << 5;
5554
5555 /* There are more than suffix matches. */
5556 if (i.tm.opcode_modifier.w
5557 || ((suffixes & (suffixes - 1))
5558 && !i.tm.opcode_modifier.defaultsize
5559 && !i.tm.opcode_modifier.ignoresize))
5560 {
5561 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
5562 return 0;
5563 }
5564 }
5565 }
5566
5567 /* Change the opcode based on the operand size given by i.suffix;
5568 We don't need to change things for byte insns. */
5569
5570 if (i.suffix
5571 && i.suffix != BYTE_MNEM_SUFFIX
5572 && i.suffix != XMMWORD_MNEM_SUFFIX
5573 && i.suffix != YMMWORD_MNEM_SUFFIX
5574 && i.suffix != ZMMWORD_MNEM_SUFFIX)
5575 {
5576 /* It's not a byte, select word/dword operation. */
5577 if (i.tm.opcode_modifier.w)
5578 {
5579 if (i.tm.opcode_modifier.shortform)
5580 i.tm.base_opcode |= 8;
5581 else
5582 i.tm.base_opcode |= 1;
5583 }
5584
5585 /* Now select between word & dword operations via the operand
5586 size prefix, except for instructions that will ignore this
5587 prefix anyway. */
5588 if (i.tm.opcode_modifier.addrprefixop0)
5589 {
5590 /* The address size override prefix changes the size of the
5591 first operand. */
5592 if ((flag_code == CODE_32BIT
5593 && i.op->regs[0].reg_type.bitfield.reg16)
5594 || (flag_code != CODE_32BIT
5595 && i.op->regs[0].reg_type.bitfield.reg32))
5596 if (!add_prefix (ADDR_PREFIX_OPCODE))
5597 return 0;
5598 }
5599 else if (i.suffix != QWORD_MNEM_SUFFIX
5600 && i.suffix != LONG_DOUBLE_MNEM_SUFFIX
5601 && !i.tm.opcode_modifier.ignoresize
5602 && !i.tm.opcode_modifier.floatmf
5603 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
5604 || (flag_code == CODE_64BIT
5605 && i.tm.opcode_modifier.jumpbyte)))
5606 {
5607 unsigned int prefix = DATA_PREFIX_OPCODE;
5608
5609 if (i.tm.opcode_modifier.jumpbyte) /* jcxz, loop */
5610 prefix = ADDR_PREFIX_OPCODE;
5611
5612 if (!add_prefix (prefix))
5613 return 0;
5614 }
5615
5616 /* Set mode64 for an operand. */
5617 if (i.suffix == QWORD_MNEM_SUFFIX
5618 && flag_code == CODE_64BIT
5619 && !i.tm.opcode_modifier.norex64)
5620 {
5621 /* Special case for xchg %rax,%rax. It is NOP and doesn't
5622 need rex64. cmpxchg8b is also a special case. */
5623 if (! (i.operands == 2
5624 && i.tm.base_opcode == 0x90
5625 && i.tm.extension_opcode == None
5626 && operand_type_equal (&i.types [0], &acc64)
5627 && operand_type_equal (&i.types [1], &acc64))
5628 && ! (i.operands == 1
5629 && i.tm.base_opcode == 0xfc7
5630 && i.tm.extension_opcode == 1
5631 && !operand_type_check (i.types [0], reg)
5632 && operand_type_check (i.types [0], anymem)))
5633 i.rex |= REX_W;
5634 }
5635
5636 /* Size floating point instruction. */
5637 if (i.suffix == LONG_MNEM_SUFFIX)
5638 if (i.tm.opcode_modifier.floatmf)
5639 i.tm.base_opcode ^= 4;
5640 }
5641
5642 return 1;
5643 }
5644
5645 static int
5646 check_byte_reg (void)
5647 {
5648 int op;
5649
5650 for (op = i.operands; --op >= 0;)
5651 {
5652 /* If this is an eight bit register, it's OK. If it's the 16 or
5653 32 bit version of an eight bit register, we will just use the
5654 low portion, and that's OK too. */
5655 if (i.types[op].bitfield.reg8)
5656 continue;
5657
5658 /* I/O port address operands are OK too. */
5659 if (i.tm.operand_types[op].bitfield.inoutportreg)
5660 continue;
5661
5662 /* crc32 doesn't generate this warning. */
5663 if (i.tm.base_opcode == 0xf20f38f0)
5664 continue;
5665
5666 if ((i.types[op].bitfield.reg16
5667 || i.types[op].bitfield.reg32
5668 || i.types[op].bitfield.reg64)
5669 && i.op[op].regs->reg_num < 4
5670 /* Prohibit these changes in 64bit mode, since the lowering
5671 would be more complicated. */
5672 && flag_code != CODE_64BIT)
5673 {
5674 #if REGISTER_WARNINGS
5675 if (!quiet_warnings)
5676 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5677 register_prefix,
5678 (i.op[op].regs + (i.types[op].bitfield.reg16
5679 ? REGNAM_AL - REGNAM_AX
5680 : REGNAM_AL - REGNAM_EAX))->reg_name,
5681 register_prefix,
5682 i.op[op].regs->reg_name,
5683 i.suffix);
5684 #endif
5685 continue;
5686 }
5687 /* Any other register is bad. */
5688 if (i.types[op].bitfield.reg16
5689 || i.types[op].bitfield.reg32
5690 || i.types[op].bitfield.reg64
5691 || i.types[op].bitfield.regmmx
5692 || i.types[op].bitfield.regxmm
5693 || i.types[op].bitfield.regymm
5694 || i.types[op].bitfield.regzmm
5695 || i.types[op].bitfield.sreg2
5696 || i.types[op].bitfield.sreg3
5697 || i.types[op].bitfield.control
5698 || i.types[op].bitfield.debug
5699 || i.types[op].bitfield.test
5700 || i.types[op].bitfield.floatreg
5701 || i.types[op].bitfield.floatacc)
5702 {
5703 as_bad (_("`%s%s' not allowed with `%s%c'"),
5704 register_prefix,
5705 i.op[op].regs->reg_name,
5706 i.tm.name,
5707 i.suffix);
5708 return 0;
5709 }
5710 }
5711 return 1;
5712 }
5713
5714 static int
5715 check_long_reg (void)
5716 {
5717 int op;
5718
5719 for (op = i.operands; --op >= 0;)
5720 /* Reject eight bit registers, except where the template requires
5721 them. (eg. movzb) */
5722 if (i.types[op].bitfield.reg8
5723 && (i.tm.operand_types[op].bitfield.reg16
5724 || i.tm.operand_types[op].bitfield.reg32
5725 || i.tm.operand_types[op].bitfield.acc))
5726 {
5727 as_bad (_("`%s%s' not allowed with `%s%c'"),
5728 register_prefix,
5729 i.op[op].regs->reg_name,
5730 i.tm.name,
5731 i.suffix);
5732 return 0;
5733 }
5734 /* Warn if the e prefix on a general reg is missing. */
5735 else if ((!quiet_warnings || flag_code == CODE_64BIT)
5736 && i.types[op].bitfield.reg16
5737 && (i.tm.operand_types[op].bitfield.reg32
5738 || i.tm.operand_types[op].bitfield.acc))
5739 {
5740 /* Prohibit these changes in the 64bit mode, since the
5741 lowering is more complicated. */
5742 if (flag_code == CODE_64BIT)
5743 {
5744 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5745 register_prefix, i.op[op].regs->reg_name,
5746 i.suffix);
5747 return 0;
5748 }
5749 #if REGISTER_WARNINGS
5750 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5751 register_prefix,
5752 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
5753 register_prefix, i.op[op].regs->reg_name, i.suffix);
5754 #endif
5755 }
5756 /* Warn if the r prefix on a general reg is present. */
5757 else if (i.types[op].bitfield.reg64
5758 && (i.tm.operand_types[op].bitfield.reg32
5759 || i.tm.operand_types[op].bitfield.acc))
5760 {
5761 if (intel_syntax
5762 && i.tm.opcode_modifier.toqword
5763 && !i.types[0].bitfield.regxmm)
5764 {
5765 /* Convert to QWORD. We want REX byte. */
5766 i.suffix = QWORD_MNEM_SUFFIX;
5767 }
5768 else
5769 {
5770 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5771 register_prefix, i.op[op].regs->reg_name,
5772 i.suffix);
5773 return 0;
5774 }
5775 }
5776 return 1;
5777 }
5778
5779 static int
5780 check_qword_reg (void)
5781 {
5782 int op;
5783
5784 for (op = i.operands; --op >= 0; )
5785 /* Reject eight bit registers, except where the template requires
5786 them. (eg. movzb) */
5787 if (i.types[op].bitfield.reg8
5788 && (i.tm.operand_types[op].bitfield.reg16
5789 || i.tm.operand_types[op].bitfield.reg32
5790 || i.tm.operand_types[op].bitfield.acc))
5791 {
5792 as_bad (_("`%s%s' not allowed with `%s%c'"),
5793 register_prefix,
5794 i.op[op].regs->reg_name,
5795 i.tm.name,
5796 i.suffix);
5797 return 0;
5798 }
5799 /* Warn if the r prefix on a general reg is missing. */
5800 else if ((i.types[op].bitfield.reg16
5801 || i.types[op].bitfield.reg32)
5802 && (i.tm.operand_types[op].bitfield.reg64
5803 || i.tm.operand_types[op].bitfield.acc))
5804 {
5805 /* Prohibit these changes in the 64bit mode, since the
5806 lowering is more complicated. */
5807 if (intel_syntax
5808 && i.tm.opcode_modifier.todword
5809 && !i.types[0].bitfield.regxmm)
5810 {
5811 /* Convert to DWORD. We don't want REX byte. */
5812 i.suffix = LONG_MNEM_SUFFIX;
5813 }
5814 else
5815 {
5816 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5817 register_prefix, i.op[op].regs->reg_name,
5818 i.suffix);
5819 return 0;
5820 }
5821 }
5822 return 1;
5823 }
5824
5825 static int
5826 check_word_reg (void)
5827 {
5828 int op;
5829 for (op = i.operands; --op >= 0;)
5830 /* Reject eight bit registers, except where the template requires
5831 them. (eg. movzb) */
5832 if (i.types[op].bitfield.reg8
5833 && (i.tm.operand_types[op].bitfield.reg16
5834 || i.tm.operand_types[op].bitfield.reg32
5835 || i.tm.operand_types[op].bitfield.acc))
5836 {
5837 as_bad (_("`%s%s' not allowed with `%s%c'"),
5838 register_prefix,
5839 i.op[op].regs->reg_name,
5840 i.tm.name,
5841 i.suffix);
5842 return 0;
5843 }
5844 /* Warn if the e or r prefix on a general reg is present. */
5845 else if ((!quiet_warnings || flag_code == CODE_64BIT)
5846 && (i.types[op].bitfield.reg32
5847 || i.types[op].bitfield.reg64)
5848 && (i.tm.operand_types[op].bitfield.reg16
5849 || i.tm.operand_types[op].bitfield.acc))
5850 {
5851 /* Prohibit these changes in the 64bit mode, since the
5852 lowering is more complicated. */
5853 if (flag_code == CODE_64BIT)
5854 {
5855 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5856 register_prefix, i.op[op].regs->reg_name,
5857 i.suffix);
5858 return 0;
5859 }
5860 #if REGISTER_WARNINGS
5861 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5862 register_prefix,
5863 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
5864 register_prefix, i.op[op].regs->reg_name, i.suffix);
5865 #endif
5866 }
5867 return 1;
5868 }
5869
5870 static int
5871 update_imm (unsigned int j)
5872 {
5873 i386_operand_type overlap = i.types[j];
5874 if ((overlap.bitfield.imm8
5875 || overlap.bitfield.imm8s
5876 || overlap.bitfield.imm16
5877 || overlap.bitfield.imm32
5878 || overlap.bitfield.imm32s
5879 || overlap.bitfield.imm64)
5880 && !operand_type_equal (&overlap, &imm8)
5881 && !operand_type_equal (&overlap, &imm8s)
5882 && !operand_type_equal (&overlap, &imm16)
5883 && !operand_type_equal (&overlap, &imm32)
5884 && !operand_type_equal (&overlap, &imm32s)
5885 && !operand_type_equal (&overlap, &imm64))
5886 {
5887 if (i.suffix)
5888 {
5889 i386_operand_type temp;
5890
5891 operand_type_set (&temp, 0);
5892 if (i.suffix == BYTE_MNEM_SUFFIX)
5893 {
5894 temp.bitfield.imm8 = overlap.bitfield.imm8;
5895 temp.bitfield.imm8s = overlap.bitfield.imm8s;
5896 }
5897 else if (i.suffix == WORD_MNEM_SUFFIX)
5898 temp.bitfield.imm16 = overlap.bitfield.imm16;
5899 else if (i.suffix == QWORD_MNEM_SUFFIX)
5900 {
5901 temp.bitfield.imm64 = overlap.bitfield.imm64;
5902 temp.bitfield.imm32s = overlap.bitfield.imm32s;
5903 }
5904 else
5905 temp.bitfield.imm32 = overlap.bitfield.imm32;
5906 overlap = temp;
5907 }
5908 else if (operand_type_equal (&overlap, &imm16_32_32s)
5909 || operand_type_equal (&overlap, &imm16_32)
5910 || operand_type_equal (&overlap, &imm16_32s))
5911 {
5912 if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
5913 overlap = imm16;
5914 else
5915 overlap = imm32s;
5916 }
5917 if (!operand_type_equal (&overlap, &imm8)
5918 && !operand_type_equal (&overlap, &imm8s)
5919 && !operand_type_equal (&overlap, &imm16)
5920 && !operand_type_equal (&overlap, &imm32)
5921 && !operand_type_equal (&overlap, &imm32s)
5922 && !operand_type_equal (&overlap, &imm64))
5923 {
5924 as_bad (_("no instruction mnemonic suffix given; "
5925 "can't determine immediate size"));
5926 return 0;
5927 }
5928 }
5929 i.types[j] = overlap;
5930
5931 return 1;
5932 }
5933
5934 static int
5935 finalize_imm (void)
5936 {
5937 unsigned int j, n;
5938
5939 /* Update the first 2 immediate operands. */
5940 n = i.operands > 2 ? 2 : i.operands;
5941 if (n)
5942 {
5943 for (j = 0; j < n; j++)
5944 if (update_imm (j) == 0)
5945 return 0;
5946
5947 /* The 3rd operand can't be immediate operand. */
5948 gas_assert (operand_type_check (i.types[2], imm) == 0);
5949 }
5950
5951 return 1;
5952 }
5953
5954 static int
5955 bad_implicit_operand (int xmm)
5956 {
5957 const char *ireg = xmm ? "xmm0" : "ymm0";
5958
5959 if (intel_syntax)
5960 as_bad (_("the last operand of `%s' must be `%s%s'"),
5961 i.tm.name, register_prefix, ireg);
5962 else
5963 as_bad (_("the first operand of `%s' must be `%s%s'"),
5964 i.tm.name, register_prefix, ireg);
5965 return 0;
5966 }
5967
5968 static int
5969 process_operands (void)
5970 {
5971 /* Default segment register this instruction will use for memory
5972 accesses. 0 means unknown. This is only for optimizing out
5973 unnecessary segment overrides. */
5974 const seg_entry *default_seg = 0;
5975
5976 if (i.tm.opcode_modifier.sse2avx && i.tm.opcode_modifier.vexvvvv)
5977 {
5978 unsigned int dupl = i.operands;
5979 unsigned int dest = dupl - 1;
5980 unsigned int j;
5981
5982 /* The destination must be an xmm register. */
5983 gas_assert (i.reg_operands
5984 && MAX_OPERANDS > dupl
5985 && operand_type_equal (&i.types[dest], &regxmm));
5986
5987 if (i.tm.opcode_modifier.firstxmm0)
5988 {
5989 /* The first operand is implicit and must be xmm0. */
5990 gas_assert (operand_type_equal (&i.types[0], &regxmm));
5991 if (register_number (i.op[0].regs) != 0)
5992 return bad_implicit_operand (1);
5993
5994 if (i.tm.opcode_modifier.vexsources == VEX3SOURCES)
5995 {
5996 /* Keep xmm0 for instructions with VEX prefix and 3
5997 sources. */
5998 goto duplicate;
5999 }
6000 else
6001 {
6002 /* We remove the first xmm0 and keep the number of
6003 operands unchanged, which in fact duplicates the
6004 destination. */
6005 for (j = 1; j < i.operands; j++)
6006 {
6007 i.op[j - 1] = i.op[j];
6008 i.types[j - 1] = i.types[j];
6009 i.tm.operand_types[j - 1] = i.tm.operand_types[j];
6010 }
6011 }
6012 }
6013 else if (i.tm.opcode_modifier.implicit1stxmm0)
6014 {
6015 gas_assert ((MAX_OPERANDS - 1) > dupl
6016 && (i.tm.opcode_modifier.vexsources
6017 == VEX3SOURCES));
6018
6019 /* Add the implicit xmm0 for instructions with VEX prefix
6020 and 3 sources. */
6021 for (j = i.operands; j > 0; j--)
6022 {
6023 i.op[j] = i.op[j - 1];
6024 i.types[j] = i.types[j - 1];
6025 i.tm.operand_types[j] = i.tm.operand_types[j - 1];
6026 }
6027 i.op[0].regs
6028 = (const reg_entry *) hash_find (reg_hash, "xmm0");
6029 i.types[0] = regxmm;
6030 i.tm.operand_types[0] = regxmm;
6031
6032 i.operands += 2;
6033 i.reg_operands += 2;
6034 i.tm.operands += 2;
6035
6036 dupl++;
6037 dest++;
6038 i.op[dupl] = i.op[dest];
6039 i.types[dupl] = i.types[dest];
6040 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
6041 }
6042 else
6043 {
6044 duplicate:
6045 i.operands++;
6046 i.reg_operands++;
6047 i.tm.operands++;
6048
6049 i.op[dupl] = i.op[dest];
6050 i.types[dupl] = i.types[dest];
6051 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
6052 }
6053
6054 if (i.tm.opcode_modifier.immext)
6055 process_immext ();
6056 }
6057 else if (i.tm.opcode_modifier.firstxmm0)
6058 {
6059 unsigned int j;
6060
6061 /* The first operand is implicit and must be xmm0/ymm0/zmm0. */
6062 gas_assert (i.reg_operands
6063 && (operand_type_equal (&i.types[0], &regxmm)
6064 || operand_type_equal (&i.types[0], &regymm)
6065 || operand_type_equal (&i.types[0], &regzmm)));
6066 if (register_number (i.op[0].regs) != 0)
6067 return bad_implicit_operand (i.types[0].bitfield.regxmm);
6068
6069 for (j = 1; j < i.operands; j++)
6070 {
6071 i.op[j - 1] = i.op[j];
6072 i.types[j - 1] = i.types[j];
6073
6074 /* We need to adjust fields in i.tm since they are used by
6075 build_modrm_byte. */
6076 i.tm.operand_types [j - 1] = i.tm.operand_types [j];
6077 }
6078
6079 i.operands--;
6080 i.reg_operands--;
6081 i.tm.operands--;
6082 }
6083 else if (i.tm.opcode_modifier.implicitquadgroup)
6084 {
6085 /* The second operand must be {x,y,z}mmN, where N is a multiple of 4. */
6086 gas_assert (i.operands >= 2
6087 && (operand_type_equal (&i.types[1], &regxmm)
6088 || operand_type_equal (&i.types[1], &regymm)
6089 || operand_type_equal (&i.types[1], &regzmm)));
6090 unsigned int regnum = register_number (i.op[1].regs);
6091 unsigned int first_reg_in_group = regnum & ~3;
6092 unsigned int last_reg_in_group = first_reg_in_group + 3;
6093 if (regnum != first_reg_in_group) {
6094 as_warn (_("the second source register `%s%s' implicitly denotes"
6095 " `%s%.3s%d' to `%s%.3s%d' source group in `%s'"),
6096 register_prefix, i.op[1].regs->reg_name,
6097 register_prefix, i.op[1].regs->reg_name, first_reg_in_group,
6098 register_prefix, i.op[1].regs->reg_name, last_reg_in_group,
6099 i.tm.name);
6100 }
6101 }
6102 else if (i.tm.opcode_modifier.regkludge)
6103 {
6104 /* The imul $imm, %reg instruction is converted into
6105 imul $imm, %reg, %reg, and the clr %reg instruction
6106 is converted into xor %reg, %reg. */
6107
6108 unsigned int first_reg_op;
6109
6110 if (operand_type_check (i.types[0], reg))
6111 first_reg_op = 0;
6112 else
6113 first_reg_op = 1;
6114 /* Pretend we saw the extra register operand. */
6115 gas_assert (i.reg_operands == 1
6116 && i.op[first_reg_op + 1].regs == 0);
6117 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
6118 i.types[first_reg_op + 1] = i.types[first_reg_op];
6119 i.operands++;
6120 i.reg_operands++;
6121 }
6122
6123 if (i.tm.opcode_modifier.shortform)
6124 {
6125 if (i.types[0].bitfield.sreg2
6126 || i.types[0].bitfield.sreg3)
6127 {
6128 if (i.tm.base_opcode == POP_SEG_SHORT
6129 && i.op[0].regs->reg_num == 1)
6130 {
6131 as_bad (_("you can't `pop %scs'"), register_prefix);
6132 return 0;
6133 }
6134 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
6135 if ((i.op[0].regs->reg_flags & RegRex) != 0)
6136 i.rex |= REX_B;
6137 }
6138 else
6139 {
6140 /* The register or float register operand is in operand
6141 0 or 1. */
6142 unsigned int op;
6143
6144 if (i.types[0].bitfield.floatreg
6145 || operand_type_check (i.types[0], reg))
6146 op = 0;
6147 else
6148 op = 1;
6149 /* Register goes in low 3 bits of opcode. */
6150 i.tm.base_opcode |= i.op[op].regs->reg_num;
6151 if ((i.op[op].regs->reg_flags & RegRex) != 0)
6152 i.rex |= REX_B;
6153 if (!quiet_warnings && i.tm.opcode_modifier.ugh)
6154 {
6155 /* Warn about some common errors, but press on regardless.
6156 The first case can be generated by gcc (<= 2.8.1). */
6157 if (i.operands == 2)
6158 {
6159 /* Reversed arguments on faddp, fsubp, etc. */
6160 as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name,
6161 register_prefix, i.op[!intel_syntax].regs->reg_name,
6162 register_prefix, i.op[intel_syntax].regs->reg_name);
6163 }
6164 else
6165 {
6166 /* Extraneous `l' suffix on fp insn. */
6167 as_warn (_("translating to `%s %s%s'"), i.tm.name,
6168 register_prefix, i.op[0].regs->reg_name);
6169 }
6170 }
6171 }
6172 }
6173 else if (i.tm.opcode_modifier.modrm)
6174 {
6175 /* The opcode is completed (modulo i.tm.extension_opcode which
6176 must be put into the modrm byte). Now, we make the modrm and
6177 index base bytes based on all the info we've collected. */
6178
6179 default_seg = build_modrm_byte ();
6180 }
6181 else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32)
6182 {
6183 default_seg = &ds;
6184 }
6185 else if (i.tm.opcode_modifier.isstring)
6186 {
6187 /* For the string instructions that allow a segment override
6188 on one of their operands, the default segment is ds. */
6189 default_seg = &ds;
6190 }
6191
6192 if (i.tm.base_opcode == 0x8d /* lea */
6193 && i.seg[0]
6194 && !quiet_warnings)
6195 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
6196
6197 /* If a segment was explicitly specified, and the specified segment
6198 is not the default, use an opcode prefix to select it. If we
6199 never figured out what the default segment is, then default_seg
6200 will be zero at this point, and the specified segment prefix will
6201 always be used. */
6202 if ((i.seg[0]) && (i.seg[0] != default_seg))
6203 {
6204 if (!add_prefix (i.seg[0]->seg_prefix))
6205 return 0;
6206 }
6207 return 1;
6208 }
6209
6210 static const seg_entry *
6211 build_modrm_byte (void)
6212 {
6213 const seg_entry *default_seg = 0;
6214 unsigned int source, dest;
6215 int vex_3_sources;
6216
6217 /* The first operand of instructions with VEX prefix and 3 sources
6218 must be VEX_Imm4. */
6219 vex_3_sources = i.tm.opcode_modifier.vexsources == VEX3SOURCES;
6220 if (vex_3_sources)
6221 {
6222 unsigned int nds, reg_slot;
6223 expressionS *exp;
6224
6225 if (i.tm.opcode_modifier.veximmext
6226 && i.tm.opcode_modifier.immext)
6227 {
6228 dest = i.operands - 2;
6229 gas_assert (dest == 3);
6230 }
6231 else
6232 dest = i.operands - 1;
6233 nds = dest - 1;
6234
6235 /* There are 2 kinds of instructions:
6236 1. 5 operands: 4 register operands or 3 register operands
6237 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
6238 VexW0 or VexW1. The destination must be either XMM, YMM or
6239 ZMM register.
6240 2. 4 operands: 4 register operands or 3 register operands
6241 plus 1 memory operand, VexXDS, and VexImmExt */
6242 gas_assert ((i.reg_operands == 4
6243 || (i.reg_operands == 3 && i.mem_operands == 1))
6244 && i.tm.opcode_modifier.vexvvvv == VEXXDS
6245 && (i.tm.opcode_modifier.veximmext
6246 || (i.imm_operands == 1
6247 && i.types[0].bitfield.vec_imm4
6248 && (i.tm.opcode_modifier.vexw == VEXW0
6249 || i.tm.opcode_modifier.vexw == VEXW1)
6250 && (operand_type_equal (&i.tm.operand_types[dest], &regxmm)
6251 || operand_type_equal (&i.tm.operand_types[dest], &regymm)
6252 || operand_type_equal (&i.tm.operand_types[dest], &regzmm)))));
6253
6254 if (i.imm_operands == 0)
6255 {
6256 /* When there is no immediate operand, generate an 8bit
6257 immediate operand to encode the first operand. */
6258 exp = &im_expressions[i.imm_operands++];
6259 i.op[i.operands].imms = exp;
6260 i.types[i.operands] = imm8;
6261 i.operands++;
6262 /* If VexW1 is set, the first operand is the source and
6263 the second operand is encoded in the immediate operand. */
6264 if (i.tm.opcode_modifier.vexw == VEXW1)
6265 {
6266 source = 0;
6267 reg_slot = 1;
6268 }
6269 else
6270 {
6271 source = 1;
6272 reg_slot = 0;
6273 }
6274
6275 /* FMA swaps REG and NDS. */
6276 if (i.tm.cpu_flags.bitfield.cpufma)
6277 {
6278 unsigned int tmp;
6279 tmp = reg_slot;
6280 reg_slot = nds;
6281 nds = tmp;
6282 }
6283
6284 gas_assert (operand_type_equal (&i.tm.operand_types[reg_slot],
6285 &regxmm)
6286 || operand_type_equal (&i.tm.operand_types[reg_slot],
6287 &regymm)
6288 || operand_type_equal (&i.tm.operand_types[reg_slot],
6289 &regzmm));
6290 exp->X_op = O_constant;
6291 exp->X_add_number = register_number (i.op[reg_slot].regs) << 4;
6292 gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
6293 }
6294 else
6295 {
6296 unsigned int imm_slot;
6297
6298 if (i.tm.opcode_modifier.vexw == VEXW0)
6299 {
6300 /* If VexW0 is set, the third operand is the source and
6301 the second operand is encoded in the immediate
6302 operand. */
6303 source = 2;
6304 reg_slot = 1;
6305 }
6306 else
6307 {
6308 /* VexW1 is set, the second operand is the source and
6309 the third operand is encoded in the immediate
6310 operand. */
6311 source = 1;
6312 reg_slot = 2;
6313 }
6314
6315 if (i.tm.opcode_modifier.immext)
6316 {
6317 /* When ImmExt is set, the immediate byte is the last
6318 operand. */
6319 imm_slot = i.operands - 1;
6320 source--;
6321 reg_slot--;
6322 }
6323 else
6324 {
6325 imm_slot = 0;
6326
6327 /* Turn on Imm8 so that output_imm will generate it. */
6328 i.types[imm_slot].bitfield.imm8 = 1;
6329 }
6330
6331 gas_assert (operand_type_equal (&i.tm.operand_types[reg_slot],
6332 &regxmm)
6333 || operand_type_equal (&i.tm.operand_types[reg_slot],
6334 &regymm)
6335 || operand_type_equal (&i.tm.operand_types[reg_slot],
6336 &regzmm));
6337 i.op[imm_slot].imms->X_add_number
6338 |= register_number (i.op[reg_slot].regs) << 4;
6339 gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
6340 }
6341
6342 gas_assert (operand_type_equal (&i.tm.operand_types[nds], &regxmm)
6343 || operand_type_equal (&i.tm.operand_types[nds],
6344 &regymm)
6345 || operand_type_equal (&i.tm.operand_types[nds],
6346 &regzmm));
6347 i.vex.register_specifier = i.op[nds].regs;
6348 }
6349 else
6350 source = dest = 0;
6351
6352 /* i.reg_operands MUST be the number of real register operands;
6353 implicit registers do not count. If there are 3 register
6354 operands, it must be a instruction with VexNDS. For a
6355 instruction with VexNDD, the destination register is encoded
6356 in VEX prefix. If there are 4 register operands, it must be
6357 a instruction with VEX prefix and 3 sources. */
6358 if (i.mem_operands == 0
6359 && ((i.reg_operands == 2
6360 && i.tm.opcode_modifier.vexvvvv <= VEXXDS)
6361 || (i.reg_operands == 3
6362 && i.tm.opcode_modifier.vexvvvv == VEXXDS)
6363 || (i.reg_operands == 4 && vex_3_sources)))
6364 {
6365 switch (i.operands)
6366 {
6367 case 2:
6368 source = 0;
6369 break;
6370 case 3:
6371 /* When there are 3 operands, one of them may be immediate,
6372 which may be the first or the last operand. Otherwise,
6373 the first operand must be shift count register (cl) or it
6374 is an instruction with VexNDS. */
6375 gas_assert (i.imm_operands == 1
6376 || (i.imm_operands == 0
6377 && (i.tm.opcode_modifier.vexvvvv == VEXXDS
6378 || i.types[0].bitfield.shiftcount)));
6379 if (operand_type_check (i.types[0], imm)
6380 || i.types[0].bitfield.shiftcount)
6381 source = 1;
6382 else
6383 source = 0;
6384 break;
6385 case 4:
6386 /* When there are 4 operands, the first two must be 8bit
6387 immediate operands. The source operand will be the 3rd
6388 one.
6389
6390 For instructions with VexNDS, if the first operand
6391 an imm8, the source operand is the 2nd one. If the last
6392 operand is imm8, the source operand is the first one. */
6393 gas_assert ((i.imm_operands == 2
6394 && i.types[0].bitfield.imm8
6395 && i.types[1].bitfield.imm8)
6396 || (i.tm.opcode_modifier.vexvvvv == VEXXDS
6397 && i.imm_operands == 1
6398 && (i.types[0].bitfield.imm8
6399 || i.types[i.operands - 1].bitfield.imm8
6400 || i.rounding)));
6401 if (i.imm_operands == 2)
6402 source = 2;
6403 else
6404 {
6405 if (i.types[0].bitfield.imm8)
6406 source = 1;
6407 else
6408 source = 0;
6409 }
6410 break;
6411 case 5:
6412 if (i.tm.opcode_modifier.evex)
6413 {
6414 /* For EVEX instructions, when there are 5 operands, the
6415 first one must be immediate operand. If the second one
6416 is immediate operand, the source operand is the 3th
6417 one. If the last one is immediate operand, the source
6418 operand is the 2nd one. */
6419 gas_assert (i.imm_operands == 2
6420 && i.tm.opcode_modifier.sae
6421 && operand_type_check (i.types[0], imm));
6422 if (operand_type_check (i.types[1], imm))
6423 source = 2;
6424 else if (operand_type_check (i.types[4], imm))
6425 source = 1;
6426 else
6427 abort ();
6428 }
6429 break;
6430 default:
6431 abort ();
6432 }
6433
6434 if (!vex_3_sources)
6435 {
6436 dest = source + 1;
6437
6438 /* RC/SAE operand could be between DEST and SRC. That happens
6439 when one operand is GPR and the other one is XMM/YMM/ZMM
6440 register. */
6441 if (i.rounding && i.rounding->operand == (int) dest)
6442 dest++;
6443
6444 if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
6445 {
6446 /* For instructions with VexNDS, the register-only source
6447 operand must be 32/64bit integer, XMM, YMM or ZMM
6448 register. It is encoded in VEX prefix. We need to
6449 clear RegMem bit before calling operand_type_equal. */
6450
6451 i386_operand_type op;
6452 unsigned int vvvv;
6453
6454 /* Check register-only source operand when two source
6455 operands are swapped. */
6456 if (!i.tm.operand_types[source].bitfield.baseindex
6457 && i.tm.operand_types[dest].bitfield.baseindex)
6458 {
6459 vvvv = source;
6460 source = dest;
6461 }
6462 else
6463 vvvv = dest;
6464
6465 op = i.tm.operand_types[vvvv];
6466 op.bitfield.regmem = 0;
6467 if ((dest + 1) >= i.operands
6468 || (!op.bitfield.reg32
6469 && op.bitfield.reg64
6470 && !operand_type_equal (&op, &regxmm)
6471 && !operand_type_equal (&op, &regymm)
6472 && !operand_type_equal (&op, &regzmm)
6473 && !operand_type_equal (&op, &regmask)))
6474 abort ();
6475 i.vex.register_specifier = i.op[vvvv].regs;
6476 dest++;
6477 }
6478 }
6479
6480 i.rm.mode = 3;
6481 /* One of the register operands will be encoded in the i.tm.reg
6482 field, the other in the combined i.tm.mode and i.tm.regmem
6483 fields. If no form of this instruction supports a memory
6484 destination operand, then we assume the source operand may
6485 sometimes be a memory operand and so we need to store the
6486 destination in the i.rm.reg field. */
6487 if (!i.tm.operand_types[dest].bitfield.regmem
6488 && operand_type_check (i.tm.operand_types[dest], anymem) == 0)
6489 {
6490 i.rm.reg = i.op[dest].regs->reg_num;
6491 i.rm.regmem = i.op[source].regs->reg_num;
6492 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
6493 i.rex |= REX_R;
6494 if ((i.op[dest].regs->reg_flags & RegVRex) != 0)
6495 i.vrex |= REX_R;
6496 if ((i.op[source].regs->reg_flags & RegRex) != 0)
6497 i.rex |= REX_B;
6498 if ((i.op[source].regs->reg_flags & RegVRex) != 0)
6499 i.vrex |= REX_B;
6500 }
6501 else
6502 {
6503 i.rm.reg = i.op[source].regs->reg_num;
6504 i.rm.regmem = i.op[dest].regs->reg_num;
6505 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
6506 i.rex |= REX_B;
6507 if ((i.op[dest].regs->reg_flags & RegVRex) != 0)
6508 i.vrex |= REX_B;
6509 if ((i.op[source].regs->reg_flags & RegRex) != 0)
6510 i.rex |= REX_R;
6511 if ((i.op[source].regs->reg_flags & RegVRex) != 0)
6512 i.vrex |= REX_R;
6513 }
6514 if (flag_code != CODE_64BIT && (i.rex & (REX_R | REX_B)))
6515 {
6516 if (!i.types[0].bitfield.control
6517 && !i.types[1].bitfield.control)
6518 abort ();
6519 i.rex &= ~(REX_R | REX_B);
6520 add_prefix (LOCK_PREFIX_OPCODE);
6521 }
6522 }
6523 else
6524 { /* If it's not 2 reg operands... */
6525 unsigned int mem;
6526
6527 if (i.mem_operands)
6528 {
6529 unsigned int fake_zero_displacement = 0;
6530 unsigned int op;
6531
6532 for (op = 0; op < i.operands; op++)
6533 if (operand_type_check (i.types[op], anymem))
6534 break;
6535 gas_assert (op < i.operands);
6536
6537 if (i.tm.opcode_modifier.vecsib)
6538 {
6539 if (i.index_reg->reg_num == RegEiz
6540 || i.index_reg->reg_num == RegRiz)
6541 abort ();
6542
6543 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6544 if (!i.base_reg)
6545 {
6546 i.sib.base = NO_BASE_REGISTER;
6547 i.sib.scale = i.log2_scale_factor;
6548 /* No Vec_Disp8 if there is no base. */
6549 i.types[op].bitfield.vec_disp8 = 0;
6550 i.types[op].bitfield.disp8 = 0;
6551 i.types[op].bitfield.disp16 = 0;
6552 i.types[op].bitfield.disp64 = 0;
6553 if (flag_code != CODE_64BIT)
6554 {
6555 /* Must be 32 bit */
6556 i.types[op].bitfield.disp32 = 1;
6557 i.types[op].bitfield.disp32s = 0;
6558 }
6559 else
6560 {
6561 i.types[op].bitfield.disp32 = 0;
6562 i.types[op].bitfield.disp32s = 1;
6563 }
6564 }
6565 i.sib.index = i.index_reg->reg_num;
6566 if ((i.index_reg->reg_flags & RegRex) != 0)
6567 i.rex |= REX_X;
6568 if ((i.index_reg->reg_flags & RegVRex) != 0)
6569 i.vrex |= REX_X;
6570 }
6571
6572 default_seg = &ds;
6573
6574 if (i.base_reg == 0)
6575 {
6576 i.rm.mode = 0;
6577 if (!i.disp_operands)
6578 {
6579 fake_zero_displacement = 1;
6580 /* Instructions with VSIB byte need 32bit displacement
6581 if there is no base register. */
6582 if (i.tm.opcode_modifier.vecsib)
6583 i.types[op].bitfield.disp32 = 1;
6584 }
6585 if (i.index_reg == 0)
6586 {
6587 gas_assert (!i.tm.opcode_modifier.vecsib);
6588 /* Operand is just <disp> */
6589 if (flag_code == CODE_64BIT)
6590 {
6591 /* 64bit mode overwrites the 32bit absolute
6592 addressing by RIP relative addressing and
6593 absolute addressing is encoded by one of the
6594 redundant SIB forms. */
6595 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6596 i.sib.base = NO_BASE_REGISTER;
6597 i.sib.index = NO_INDEX_REGISTER;
6598 i.types[op] = ((i.prefix[ADDR_PREFIX] == 0)
6599 ? disp32s : disp32);
6600 }
6601 else if ((flag_code == CODE_16BIT)
6602 ^ (i.prefix[ADDR_PREFIX] != 0))
6603 {
6604 i.rm.regmem = NO_BASE_REGISTER_16;
6605 i.types[op] = disp16;
6606 }
6607 else
6608 {
6609 i.rm.regmem = NO_BASE_REGISTER;
6610 i.types[op] = disp32;
6611 }
6612 }
6613 else if (!i.tm.opcode_modifier.vecsib)
6614 {
6615 /* !i.base_reg && i.index_reg */
6616 if (i.index_reg->reg_num == RegEiz
6617 || i.index_reg->reg_num == RegRiz)
6618 i.sib.index = NO_INDEX_REGISTER;
6619 else
6620 i.sib.index = i.index_reg->reg_num;
6621 i.sib.base = NO_BASE_REGISTER;
6622 i.sib.scale = i.log2_scale_factor;
6623 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6624 /* No Vec_Disp8 if there is no base. */
6625 i.types[op].bitfield.vec_disp8 = 0;
6626 i.types[op].bitfield.disp8 = 0;
6627 i.types[op].bitfield.disp16 = 0;
6628 i.types[op].bitfield.disp64 = 0;
6629 if (flag_code != CODE_64BIT)
6630 {
6631 /* Must be 32 bit */
6632 i.types[op].bitfield.disp32 = 1;
6633 i.types[op].bitfield.disp32s = 0;
6634 }
6635 else
6636 {
6637 i.types[op].bitfield.disp32 = 0;
6638 i.types[op].bitfield.disp32s = 1;
6639 }
6640 if ((i.index_reg->reg_flags & RegRex) != 0)
6641 i.rex |= REX_X;
6642 }
6643 }
6644 /* RIP addressing for 64bit mode. */
6645 else if (i.base_reg->reg_num == RegRip ||
6646 i.base_reg->reg_num == RegEip)
6647 {
6648 gas_assert (!i.tm.opcode_modifier.vecsib);
6649 i.rm.regmem = NO_BASE_REGISTER;
6650 i.types[op].bitfield.disp8 = 0;
6651 i.types[op].bitfield.disp16 = 0;
6652 i.types[op].bitfield.disp32 = 0;
6653 i.types[op].bitfield.disp32s = 1;
6654 i.types[op].bitfield.disp64 = 0;
6655 i.types[op].bitfield.vec_disp8 = 0;
6656 i.flags[op] |= Operand_PCrel;
6657 if (! i.disp_operands)
6658 fake_zero_displacement = 1;
6659 }
6660 else if (i.base_reg->reg_type.bitfield.reg16)
6661 {
6662 gas_assert (!i.tm.opcode_modifier.vecsib);
6663 switch (i.base_reg->reg_num)
6664 {
6665 case 3: /* (%bx) */
6666 if (i.index_reg == 0)
6667 i.rm.regmem = 7;
6668 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
6669 i.rm.regmem = i.index_reg->reg_num - 6;
6670 break;
6671 case 5: /* (%bp) */
6672 default_seg = &ss;
6673 if (i.index_reg == 0)
6674 {
6675 i.rm.regmem = 6;
6676 if (operand_type_check (i.types[op], disp) == 0)
6677 {
6678 /* fake (%bp) into 0(%bp) */
6679 if (i.tm.operand_types[op].bitfield.vec_disp8)
6680 i.types[op].bitfield.vec_disp8 = 1;
6681 else
6682 i.types[op].bitfield.disp8 = 1;
6683 fake_zero_displacement = 1;
6684 }
6685 }
6686 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
6687 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
6688 break;
6689 default: /* (%si) -> 4 or (%di) -> 5 */
6690 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
6691 }
6692 i.rm.mode = mode_from_disp_size (i.types[op]);
6693 }
6694 else /* i.base_reg and 32/64 bit mode */
6695 {
6696 if (flag_code == CODE_64BIT
6697 && operand_type_check (i.types[op], disp))
6698 {
6699 i386_operand_type temp;
6700 operand_type_set (&temp, 0);
6701 temp.bitfield.disp8 = i.types[op].bitfield.disp8;
6702 temp.bitfield.vec_disp8
6703 = i.types[op].bitfield.vec_disp8;
6704 i.types[op] = temp;
6705 if (i.prefix[ADDR_PREFIX] == 0)
6706 i.types[op].bitfield.disp32s = 1;
6707 else
6708 i.types[op].bitfield.disp32 = 1;
6709 }
6710
6711 if (!i.tm.opcode_modifier.vecsib)
6712 i.rm.regmem = i.base_reg->reg_num;
6713 if ((i.base_reg->reg_flags & RegRex) != 0)
6714 i.rex |= REX_B;
6715 i.sib.base = i.base_reg->reg_num;
6716 /* x86-64 ignores REX prefix bit here to avoid decoder
6717 complications. */
6718 if (!(i.base_reg->reg_flags & RegRex)
6719 && (i.base_reg->reg_num == EBP_REG_NUM
6720 || i.base_reg->reg_num == ESP_REG_NUM))
6721 default_seg = &ss;
6722 if (i.base_reg->reg_num == 5 && i.disp_operands == 0)
6723 {
6724 fake_zero_displacement = 1;
6725 if (i.tm.operand_types [op].bitfield.vec_disp8)
6726 i.types[op].bitfield.vec_disp8 = 1;
6727 else
6728 i.types[op].bitfield.disp8 = 1;
6729 }
6730 i.sib.scale = i.log2_scale_factor;
6731 if (i.index_reg == 0)
6732 {
6733 gas_assert (!i.tm.opcode_modifier.vecsib);
6734 /* <disp>(%esp) becomes two byte modrm with no index
6735 register. We've already stored the code for esp
6736 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
6737 Any base register besides %esp will not use the
6738 extra modrm byte. */
6739 i.sib.index = NO_INDEX_REGISTER;
6740 }
6741 else if (!i.tm.opcode_modifier.vecsib)
6742 {
6743 if (i.index_reg->reg_num == RegEiz
6744 || i.index_reg->reg_num == RegRiz)
6745 i.sib.index = NO_INDEX_REGISTER;
6746 else
6747 i.sib.index = i.index_reg->reg_num;
6748 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6749 if ((i.index_reg->reg_flags & RegRex) != 0)
6750 i.rex |= REX_X;
6751 }
6752
6753 if (i.disp_operands
6754 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
6755 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
6756 i.rm.mode = 0;
6757 else
6758 {
6759 if (!fake_zero_displacement
6760 && !i.disp_operands
6761 && i.disp_encoding)
6762 {
6763 fake_zero_displacement = 1;
6764 if (i.disp_encoding == disp_encoding_8bit)
6765 i.types[op].bitfield.disp8 = 1;
6766 else
6767 i.types[op].bitfield.disp32 = 1;
6768 }
6769 i.rm.mode = mode_from_disp_size (i.types[op]);
6770 }
6771 }
6772
6773 if (fake_zero_displacement)
6774 {
6775 /* Fakes a zero displacement assuming that i.types[op]
6776 holds the correct displacement size. */
6777 expressionS *exp;
6778
6779 gas_assert (i.op[op].disps == 0);
6780 exp = &disp_expressions[i.disp_operands++];
6781 i.op[op].disps = exp;
6782 exp->X_op = O_constant;
6783 exp->X_add_number = 0;
6784 exp->X_add_symbol = (symbolS *) 0;
6785 exp->X_op_symbol = (symbolS *) 0;
6786 }
6787
6788 mem = op;
6789 }
6790 else
6791 mem = ~0;
6792
6793 if (i.tm.opcode_modifier.vexsources == XOP2SOURCES)
6794 {
6795 if (operand_type_check (i.types[0], imm))
6796 i.vex.register_specifier = NULL;
6797 else
6798 {
6799 /* VEX.vvvv encodes one of the sources when the first
6800 operand is not an immediate. */
6801 if (i.tm.opcode_modifier.vexw == VEXW0)
6802 i.vex.register_specifier = i.op[0].regs;
6803 else
6804 i.vex.register_specifier = i.op[1].regs;
6805 }
6806
6807 /* Destination is a XMM register encoded in the ModRM.reg
6808 and VEX.R bit. */
6809 i.rm.reg = i.op[2].regs->reg_num;
6810 if ((i.op[2].regs->reg_flags & RegRex) != 0)
6811 i.rex |= REX_R;
6812
6813 /* ModRM.rm and VEX.B encodes the other source. */
6814 if (!i.mem_operands)
6815 {
6816 i.rm.mode = 3;
6817
6818 if (i.tm.opcode_modifier.vexw == VEXW0)
6819 i.rm.regmem = i.op[1].regs->reg_num;
6820 else
6821 i.rm.regmem = i.op[0].regs->reg_num;
6822
6823 if ((i.op[1].regs->reg_flags & RegRex) != 0)
6824 i.rex |= REX_B;
6825 }
6826 }
6827 else if (i.tm.opcode_modifier.vexvvvv == VEXLWP)
6828 {
6829 i.vex.register_specifier = i.op[2].regs;
6830 if (!i.mem_operands)
6831 {
6832 i.rm.mode = 3;
6833 i.rm.regmem = i.op[1].regs->reg_num;
6834 if ((i.op[1].regs->reg_flags & RegRex) != 0)
6835 i.rex |= REX_B;
6836 }
6837 }
6838 /* Fill in i.rm.reg or i.rm.regmem field with register operand
6839 (if any) based on i.tm.extension_opcode. Again, we must be
6840 careful to make sure that segment/control/debug/test/MMX
6841 registers are coded into the i.rm.reg field. */
6842 else if (i.reg_operands)
6843 {
6844 unsigned int op;
6845 unsigned int vex_reg = ~0;
6846
6847 for (op = 0; op < i.operands; op++)
6848 if (i.types[op].bitfield.reg8
6849 || i.types[op].bitfield.reg16
6850 || i.types[op].bitfield.reg32
6851 || i.types[op].bitfield.reg64
6852 || i.types[op].bitfield.regmmx
6853 || i.types[op].bitfield.regxmm
6854 || i.types[op].bitfield.regymm
6855 || i.types[op].bitfield.regbnd
6856 || i.types[op].bitfield.regzmm
6857 || i.types[op].bitfield.regmask
6858 || i.types[op].bitfield.sreg2
6859 || i.types[op].bitfield.sreg3
6860 || i.types[op].bitfield.control
6861 || i.types[op].bitfield.debug
6862 || i.types[op].bitfield.test)
6863 break;
6864
6865 if (vex_3_sources)
6866 op = dest;
6867 else if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
6868 {
6869 /* For instructions with VexNDS, the register-only
6870 source operand is encoded in VEX prefix. */
6871 gas_assert (mem != (unsigned int) ~0);
6872
6873 if (op > mem)
6874 {
6875 vex_reg = op++;
6876 gas_assert (op < i.operands);
6877 }
6878 else
6879 {
6880 /* Check register-only source operand when two source
6881 operands are swapped. */
6882 if (!i.tm.operand_types[op].bitfield.baseindex
6883 && i.tm.operand_types[op + 1].bitfield.baseindex)
6884 {
6885 vex_reg = op;
6886 op += 2;
6887 gas_assert (mem == (vex_reg + 1)
6888 && op < i.operands);
6889 }
6890 else
6891 {
6892 vex_reg = op + 1;
6893 gas_assert (vex_reg < i.operands);
6894 }
6895 }
6896 }
6897 else if (i.tm.opcode_modifier.vexvvvv == VEXNDD)
6898 {
6899 /* For instructions with VexNDD, the register destination
6900 is encoded in VEX prefix. */
6901 if (i.mem_operands == 0)
6902 {
6903 /* There is no memory operand. */
6904 gas_assert ((op + 2) == i.operands);
6905 vex_reg = op + 1;
6906 }
6907 else
6908 {
6909 /* There are only 2 operands. */
6910 gas_assert (op < 2 && i.operands == 2);
6911 vex_reg = 1;
6912 }
6913 }
6914 else
6915 gas_assert (op < i.operands);
6916
6917 if (vex_reg != (unsigned int) ~0)
6918 {
6919 i386_operand_type *type = &i.tm.operand_types[vex_reg];
6920
6921 if (type->bitfield.reg32 != 1
6922 && type->bitfield.reg64 != 1
6923 && !operand_type_equal (type, &regxmm)
6924 && !operand_type_equal (type, &regymm)
6925 && !operand_type_equal (type, &regzmm)
6926 && !operand_type_equal (type, &regmask))
6927 abort ();
6928
6929 i.vex.register_specifier = i.op[vex_reg].regs;
6930 }
6931
6932 /* Don't set OP operand twice. */
6933 if (vex_reg != op)
6934 {
6935 /* If there is an extension opcode to put here, the
6936 register number must be put into the regmem field. */
6937 if (i.tm.extension_opcode != None)
6938 {
6939 i.rm.regmem = i.op[op].regs->reg_num;
6940 if ((i.op[op].regs->reg_flags & RegRex) != 0)
6941 i.rex |= REX_B;
6942 if ((i.op[op].regs->reg_flags & RegVRex) != 0)
6943 i.vrex |= REX_B;
6944 }
6945 else
6946 {
6947 i.rm.reg = i.op[op].regs->reg_num;
6948 if ((i.op[op].regs->reg_flags & RegRex) != 0)
6949 i.rex |= REX_R;
6950 if ((i.op[op].regs->reg_flags & RegVRex) != 0)
6951 i.vrex |= REX_R;
6952 }
6953 }
6954
6955 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
6956 must set it to 3 to indicate this is a register operand
6957 in the regmem field. */
6958 if (!i.mem_operands)
6959 i.rm.mode = 3;
6960 }
6961
6962 /* Fill in i.rm.reg field with extension opcode (if any). */
6963 if (i.tm.extension_opcode != None)
6964 i.rm.reg = i.tm.extension_opcode;
6965 }
6966 return default_seg;
6967 }
6968
6969 static void
6970 output_branch (void)
6971 {
6972 char *p;
6973 int size;
6974 int code16;
6975 int prefix;
6976 relax_substateT subtype;
6977 symbolS *sym;
6978 offsetT off;
6979
6980 code16 = flag_code == CODE_16BIT ? CODE16 : 0;
6981 size = i.disp_encoding == disp_encoding_32bit ? BIG : SMALL;
6982
6983 prefix = 0;
6984 if (i.prefix[DATA_PREFIX] != 0)
6985 {
6986 prefix = 1;
6987 i.prefixes -= 1;
6988 code16 ^= CODE16;
6989 }
6990 /* Pentium4 branch hints. */
6991 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
6992 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
6993 {
6994 prefix++;
6995 i.prefixes--;
6996 }
6997 if (i.prefix[REX_PREFIX] != 0)
6998 {
6999 prefix++;
7000 i.prefixes--;
7001 }
7002
7003 /* BND prefixed jump. */
7004 if (i.prefix[BND_PREFIX] != 0)
7005 {
7006 FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]);
7007 i.prefixes -= 1;
7008 }
7009
7010 if (i.prefixes != 0 && !intel_syntax)
7011 as_warn (_("skipping prefixes on this instruction"));
7012
7013 /* It's always a symbol; End frag & setup for relax.
7014 Make sure there is enough room in this frag for the largest
7015 instruction we may generate in md_convert_frag. This is 2
7016 bytes for the opcode and room for the prefix and largest
7017 displacement. */
7018 frag_grow (prefix + 2 + 4);
7019 /* Prefix and 1 opcode byte go in fr_fix. */
7020 p = frag_more (prefix + 1);
7021 if (i.prefix[DATA_PREFIX] != 0)
7022 *p++ = DATA_PREFIX_OPCODE;
7023 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
7024 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
7025 *p++ = i.prefix[SEG_PREFIX];
7026 if (i.prefix[REX_PREFIX] != 0)
7027 *p++ = i.prefix[REX_PREFIX];
7028 *p = i.tm.base_opcode;
7029
7030 if ((unsigned char) *p == JUMP_PC_RELATIVE)
7031 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, size);
7032 else if (cpu_arch_flags.bitfield.cpui386)
7033 subtype = ENCODE_RELAX_STATE (COND_JUMP, size);
7034 else
7035 subtype = ENCODE_RELAX_STATE (COND_JUMP86, size);
7036 subtype |= code16;
7037
7038 sym = i.op[0].disps->X_add_symbol;
7039 off = i.op[0].disps->X_add_number;
7040
7041 if (i.op[0].disps->X_op != O_constant
7042 && i.op[0].disps->X_op != O_symbol)
7043 {
7044 /* Handle complex expressions. */
7045 sym = make_expr_symbol (i.op[0].disps);
7046 off = 0;
7047 }
7048
7049 /* 1 possible extra opcode + 4 byte displacement go in var part.
7050 Pass reloc in fr_var. */
7051 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
7052 }
7053
7054 static void
7055 output_jump (void)
7056 {
7057 char *p;
7058 int size;
7059 fixS *fixP;
7060
7061 if (i.tm.opcode_modifier.jumpbyte)
7062 {
7063 /* This is a loop or jecxz type instruction. */
7064 size = 1;
7065 if (i.prefix[ADDR_PREFIX] != 0)
7066 {
7067 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
7068 i.prefixes -= 1;
7069 }
7070 /* Pentium4 branch hints. */
7071 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
7072 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
7073 {
7074 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
7075 i.prefixes--;
7076 }
7077 }
7078 else
7079 {
7080 int code16;
7081
7082 code16 = 0;
7083 if (flag_code == CODE_16BIT)
7084 code16 = CODE16;
7085
7086 if (i.prefix[DATA_PREFIX] != 0)
7087 {
7088 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
7089 i.prefixes -= 1;
7090 code16 ^= CODE16;
7091 }
7092
7093 size = 4;
7094 if (code16)
7095 size = 2;
7096 }
7097
7098 if (i.prefix[REX_PREFIX] != 0)
7099 {
7100 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
7101 i.prefixes -= 1;
7102 }
7103
7104 /* BND prefixed jump. */
7105 if (i.prefix[BND_PREFIX] != 0)
7106 {
7107 FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]);
7108 i.prefixes -= 1;
7109 }
7110
7111 if (i.prefixes != 0 && !intel_syntax)
7112 as_warn (_("skipping prefixes on this instruction"));
7113
7114 p = frag_more (i.tm.opcode_length + size);
7115 switch (i.tm.opcode_length)
7116 {
7117 case 2:
7118 *p++ = i.tm.base_opcode >> 8;
7119 /* Fall through. */
7120 case 1:
7121 *p++ = i.tm.base_opcode;
7122 break;
7123 default:
7124 abort ();
7125 }
7126
7127 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
7128 i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0]));
7129
7130 /* All jumps handled here are signed, but don't use a signed limit
7131 check for 32 and 16 bit jumps as we want to allow wrap around at
7132 4G and 64k respectively. */
7133 if (size == 1)
7134 fixP->fx_signed = 1;
7135 }
7136
7137 static void
7138 output_interseg_jump (void)
7139 {
7140 char *p;
7141 int size;
7142 int prefix;
7143 int code16;
7144
7145 code16 = 0;
7146 if (flag_code == CODE_16BIT)
7147 code16 = CODE16;
7148
7149 prefix = 0;
7150 if (i.prefix[DATA_PREFIX] != 0)
7151 {
7152 prefix = 1;
7153 i.prefixes -= 1;
7154 code16 ^= CODE16;
7155 }
7156 if (i.prefix[REX_PREFIX] != 0)
7157 {
7158 prefix++;
7159 i.prefixes -= 1;
7160 }
7161
7162 size = 4;
7163 if (code16)
7164 size = 2;
7165
7166 if (i.prefixes != 0 && !intel_syntax)
7167 as_warn (_("skipping prefixes on this instruction"));
7168
7169 /* 1 opcode; 2 segment; offset */
7170 p = frag_more (prefix + 1 + 2 + size);
7171
7172 if (i.prefix[DATA_PREFIX] != 0)
7173 *p++ = DATA_PREFIX_OPCODE;
7174
7175 if (i.prefix[REX_PREFIX] != 0)
7176 *p++ = i.prefix[REX_PREFIX];
7177
7178 *p++ = i.tm.base_opcode;
7179 if (i.op[1].imms->X_op == O_constant)
7180 {
7181 offsetT n = i.op[1].imms->X_add_number;
7182
7183 if (size == 2
7184 && !fits_in_unsigned_word (n)
7185 && !fits_in_signed_word (n))
7186 {
7187 as_bad (_("16-bit jump out of range"));
7188 return;
7189 }
7190 md_number_to_chars (p, n, size);
7191 }
7192 else
7193 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
7194 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
7195 if (i.op[0].imms->X_op != O_constant)
7196 as_bad (_("can't handle non absolute segment in `%s'"),
7197 i.tm.name);
7198 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
7199 }
7200
7201 static void
7202 output_insn (void)
7203 {
7204 fragS *insn_start_frag;
7205 offsetT insn_start_off;
7206
7207 /* Tie dwarf2 debug info to the address at the start of the insn.
7208 We can't do this after the insn has been output as the current
7209 frag may have been closed off. eg. by frag_var. */
7210 dwarf2_emit_insn (0);
7211
7212 insn_start_frag = frag_now;
7213 insn_start_off = frag_now_fix ();
7214
7215 /* Output jumps. */
7216 if (i.tm.opcode_modifier.jump)
7217 output_branch ();
7218 else if (i.tm.opcode_modifier.jumpbyte
7219 || i.tm.opcode_modifier.jumpdword)
7220 output_jump ();
7221 else if (i.tm.opcode_modifier.jumpintersegment)
7222 output_interseg_jump ();
7223 else
7224 {
7225 /* Output normal instructions here. */
7226 char *p;
7227 unsigned char *q;
7228 unsigned int j;
7229 unsigned int prefix;
7230
7231 if (avoid_fence
7232 && i.tm.base_opcode == 0xfae
7233 && i.operands == 1
7234 && i.imm_operands == 1
7235 && (i.op[0].imms->X_add_number == 0xe8
7236 || i.op[0].imms->X_add_number == 0xf0
7237 || i.op[0].imms->X_add_number == 0xf8))
7238 {
7239 /* Encode lfence, mfence, and sfence as
7240 f0 83 04 24 00 lock addl $0x0, (%{re}sp). */
7241 offsetT val = 0x240483f0ULL;
7242 p = frag_more (5);
7243 md_number_to_chars (p, val, 5);
7244 return;
7245 }
7246
7247 /* Some processors fail on LOCK prefix. This options makes
7248 assembler ignore LOCK prefix and serves as a workaround. */
7249 if (omit_lock_prefix)
7250 {
7251 if (i.tm.base_opcode == LOCK_PREFIX_OPCODE)
7252 return;
7253 i.prefix[LOCK_PREFIX] = 0;
7254 }
7255
7256 /* Since the VEX/EVEX prefix contains the implicit prefix, we
7257 don't need the explicit prefix. */
7258 if (!i.tm.opcode_modifier.vex && !i.tm.opcode_modifier.evex)
7259 {
7260 switch (i.tm.opcode_length)
7261 {
7262 case 3:
7263 if (i.tm.base_opcode & 0xff000000)
7264 {
7265 prefix = (i.tm.base_opcode >> 24) & 0xff;
7266 goto check_prefix;
7267 }
7268 break;
7269 case 2:
7270 if ((i.tm.base_opcode & 0xff0000) != 0)
7271 {
7272 prefix = (i.tm.base_opcode >> 16) & 0xff;
7273 if (i.tm.cpu_flags.bitfield.cpupadlock)
7274 {
7275 check_prefix:
7276 if (prefix != REPE_PREFIX_OPCODE
7277 || (i.prefix[REP_PREFIX]
7278 != REPE_PREFIX_OPCODE))
7279 add_prefix (prefix);
7280 }
7281 else
7282 add_prefix (prefix);
7283 }
7284 break;
7285 case 1:
7286 break;
7287 default:
7288 abort ();
7289 }
7290
7291 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
7292 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
7293 R_X86_64_GOTTPOFF relocation so that linker can safely
7294 perform IE->LE optimization. */
7295 if (x86_elf_abi == X86_64_X32_ABI
7296 && i.operands == 2
7297 && i.reloc[0] == BFD_RELOC_X86_64_GOTTPOFF
7298 && i.prefix[REX_PREFIX] == 0)
7299 add_prefix (REX_OPCODE);
7300 #endif
7301
7302 /* The prefix bytes. */
7303 for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++)
7304 if (*q)
7305 FRAG_APPEND_1_CHAR (*q);
7306 }
7307 else
7308 {
7309 for (j = 0, q = i.prefix; j < ARRAY_SIZE (i.prefix); j++, q++)
7310 if (*q)
7311 switch (j)
7312 {
7313 case REX_PREFIX:
7314 /* REX byte is encoded in VEX prefix. */
7315 break;
7316 case SEG_PREFIX:
7317 case ADDR_PREFIX:
7318 FRAG_APPEND_1_CHAR (*q);
7319 break;
7320 default:
7321 /* There should be no other prefixes for instructions
7322 with VEX prefix. */
7323 abort ();
7324 }
7325
7326 /* For EVEX instructions i.vrex should become 0 after
7327 build_evex_prefix. For VEX instructions upper 16 registers
7328 aren't available, so VREX should be 0. */
7329 if (i.vrex)
7330 abort ();
7331 /* Now the VEX prefix. */
7332 p = frag_more (i.vex.length);
7333 for (j = 0; j < i.vex.length; j++)
7334 p[j] = i.vex.bytes[j];
7335 }
7336
7337 /* Now the opcode; be careful about word order here! */
7338 if (i.tm.opcode_length == 1)
7339 {
7340 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
7341 }
7342 else
7343 {
7344 switch (i.tm.opcode_length)
7345 {
7346 case 4:
7347 p = frag_more (4);
7348 *p++ = (i.tm.base_opcode >> 24) & 0xff;
7349 *p++ = (i.tm.base_opcode >> 16) & 0xff;
7350 break;
7351 case 3:
7352 p = frag_more (3);
7353 *p++ = (i.tm.base_opcode >> 16) & 0xff;
7354 break;
7355 case 2:
7356 p = frag_more (2);
7357 break;
7358 default:
7359 abort ();
7360 break;
7361 }
7362
7363 /* Put out high byte first: can't use md_number_to_chars! */
7364 *p++ = (i.tm.base_opcode >> 8) & 0xff;
7365 *p = i.tm.base_opcode & 0xff;
7366 }
7367
7368 /* Now the modrm byte and sib byte (if present). */
7369 if (i.tm.opcode_modifier.modrm)
7370 {
7371 FRAG_APPEND_1_CHAR ((i.rm.regmem << 0
7372 | i.rm.reg << 3
7373 | i.rm.mode << 6));
7374 /* If i.rm.regmem == ESP (4)
7375 && i.rm.mode != (Register mode)
7376 && not 16 bit
7377 ==> need second modrm byte. */
7378 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
7379 && i.rm.mode != 3
7380 && !(i.base_reg && i.base_reg->reg_type.bitfield.reg16))
7381 FRAG_APPEND_1_CHAR ((i.sib.base << 0
7382 | i.sib.index << 3
7383 | i.sib.scale << 6));
7384 }
7385
7386 if (i.disp_operands)
7387 output_disp (insn_start_frag, insn_start_off);
7388
7389 if (i.imm_operands)
7390 output_imm (insn_start_frag, insn_start_off);
7391 }
7392
7393 #ifdef DEBUG386
7394 if (flag_debug)
7395 {
7396 pi ("" /*line*/, &i);
7397 }
7398 #endif /* DEBUG386 */
7399 }
7400
7401 /* Return the size of the displacement operand N. */
7402
7403 static int
7404 disp_size (unsigned int n)
7405 {
7406 int size = 4;
7407
7408 /* Vec_Disp8 has to be 8bit. */
7409 if (i.types[n].bitfield.vec_disp8)
7410 size = 1;
7411 else if (i.types[n].bitfield.disp64)
7412 size = 8;
7413 else if (i.types[n].bitfield.disp8)
7414 size = 1;
7415 else if (i.types[n].bitfield.disp16)
7416 size = 2;
7417 return size;
7418 }
7419
7420 /* Return the size of the immediate operand N. */
7421
7422 static int
7423 imm_size (unsigned int n)
7424 {
7425 int size = 4;
7426 if (i.types[n].bitfield.imm64)
7427 size = 8;
7428 else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s)
7429 size = 1;
7430 else if (i.types[n].bitfield.imm16)
7431 size = 2;
7432 return size;
7433 }
7434
7435 static void
7436 output_disp (fragS *insn_start_frag, offsetT insn_start_off)
7437 {
7438 char *p;
7439 unsigned int n;
7440
7441 for (n = 0; n < i.operands; n++)
7442 {
7443 if (i.types[n].bitfield.vec_disp8
7444 || operand_type_check (i.types[n], disp))
7445 {
7446 if (i.op[n].disps->X_op == O_constant)
7447 {
7448 int size = disp_size (n);
7449 offsetT val = i.op[n].disps->X_add_number;
7450
7451 if (i.types[n].bitfield.vec_disp8)
7452 val >>= i.memshift;
7453 val = offset_in_range (val, size);
7454 p = frag_more (size);
7455 md_number_to_chars (p, val, size);
7456 }
7457 else
7458 {
7459 enum bfd_reloc_code_real reloc_type;
7460 int size = disp_size (n);
7461 int sign = i.types[n].bitfield.disp32s;
7462 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
7463 fixS *fixP;
7464
7465 /* We can't have 8 bit displacement here. */
7466 gas_assert (!i.types[n].bitfield.disp8);
7467
7468 /* The PC relative address is computed relative
7469 to the instruction boundary, so in case immediate
7470 fields follows, we need to adjust the value. */
7471 if (pcrel && i.imm_operands)
7472 {
7473 unsigned int n1;
7474 int sz = 0;
7475
7476 for (n1 = 0; n1 < i.operands; n1++)
7477 if (operand_type_check (i.types[n1], imm))
7478 {
7479 /* Only one immediate is allowed for PC
7480 relative address. */
7481 gas_assert (sz == 0);
7482 sz = imm_size (n1);
7483 i.op[n].disps->X_add_number -= sz;
7484 }
7485 /* We should find the immediate. */
7486 gas_assert (sz != 0);
7487 }
7488
7489 p = frag_more (size);
7490 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
7491 if (GOT_symbol
7492 && GOT_symbol == i.op[n].disps->X_add_symbol
7493 && (((reloc_type == BFD_RELOC_32
7494 || reloc_type == BFD_RELOC_X86_64_32S
7495 || (reloc_type == BFD_RELOC_64
7496 && object_64bit))
7497 && (i.op[n].disps->X_op == O_symbol
7498 || (i.op[n].disps->X_op == O_add
7499 && ((symbol_get_value_expression
7500 (i.op[n].disps->X_op_symbol)->X_op)
7501 == O_subtract))))
7502 || reloc_type == BFD_RELOC_32_PCREL))
7503 {
7504 offsetT add;
7505
7506 if (insn_start_frag == frag_now)
7507 add = (p - frag_now->fr_literal) - insn_start_off;
7508 else
7509 {
7510 fragS *fr;
7511
7512 add = insn_start_frag->fr_fix - insn_start_off;
7513 for (fr = insn_start_frag->fr_next;
7514 fr && fr != frag_now; fr = fr->fr_next)
7515 add += fr->fr_fix;
7516 add += p - frag_now->fr_literal;
7517 }
7518
7519 if (!object_64bit)
7520 {
7521 reloc_type = BFD_RELOC_386_GOTPC;
7522 i.op[n].imms->X_add_number += add;
7523 }
7524 else if (reloc_type == BFD_RELOC_64)
7525 reloc_type = BFD_RELOC_X86_64_GOTPC64;
7526 else
7527 /* Don't do the adjustment for x86-64, as there
7528 the pcrel addressing is relative to the _next_
7529 insn, and that is taken care of in other code. */
7530 reloc_type = BFD_RELOC_X86_64_GOTPC32;
7531 }
7532 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal,
7533 size, i.op[n].disps, pcrel,
7534 reloc_type);
7535 /* Check for "call/jmp *mem", "mov mem, %reg",
7536 "test %reg, mem" and "binop mem, %reg" where binop
7537 is one of adc, add, and, cmp, or, sbb, sub, xor
7538 instructions. Always generate R_386_GOT32X for
7539 "sym*GOT" operand in 32-bit mode. */
7540 if ((generate_relax_relocations
7541 || (!object_64bit
7542 && i.rm.mode == 0
7543 && i.rm.regmem == 5))
7544 && (i.rm.mode == 2
7545 || (i.rm.mode == 0 && i.rm.regmem == 5))
7546 && ((i.operands == 1
7547 && i.tm.base_opcode == 0xff
7548 && (i.rm.reg == 2 || i.rm.reg == 4))
7549 || (i.operands == 2
7550 && (i.tm.base_opcode == 0x8b
7551 || i.tm.base_opcode == 0x85
7552 || (i.tm.base_opcode & 0xc7) == 0x03))))
7553 {
7554 if (object_64bit)
7555 {
7556 fixP->fx_tcbit = i.rex != 0;
7557 if (i.base_reg
7558 && (i.base_reg->reg_num == RegRip
7559 || i.base_reg->reg_num == RegEip))
7560 fixP->fx_tcbit2 = 1;
7561 }
7562 else
7563 fixP->fx_tcbit2 = 1;
7564 }
7565 }
7566 }
7567 }
7568 }
7569
7570 static void
7571 output_imm (fragS *insn_start_frag, offsetT insn_start_off)
7572 {
7573 char *p;
7574 unsigned int n;
7575
7576 for (n = 0; n < i.operands; n++)
7577 {
7578 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
7579 if (i.rounding && (int) n == i.rounding->operand)
7580 continue;
7581
7582 if (operand_type_check (i.types[n], imm))
7583 {
7584 if (i.op[n].imms->X_op == O_constant)
7585 {
7586 int size = imm_size (n);
7587 offsetT val;
7588
7589 val = offset_in_range (i.op[n].imms->X_add_number,
7590 size);
7591 p = frag_more (size);
7592 md_number_to_chars (p, val, size);
7593 }
7594 else
7595 {
7596 /* Not absolute_section.
7597 Need a 32-bit fixup (don't support 8bit
7598 non-absolute imms). Try to support other
7599 sizes ... */
7600 enum bfd_reloc_code_real reloc_type;
7601 int size = imm_size (n);
7602 int sign;
7603
7604 if (i.types[n].bitfield.imm32s
7605 && (i.suffix == QWORD_MNEM_SUFFIX
7606 || (!i.suffix && i.tm.opcode_modifier.no_lsuf)))
7607 sign = 1;
7608 else
7609 sign = 0;
7610
7611 p = frag_more (size);
7612 reloc_type = reloc (size, 0, sign, i.reloc[n]);
7613
7614 /* This is tough to explain. We end up with this one if we
7615 * have operands that look like
7616 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
7617 * obtain the absolute address of the GOT, and it is strongly
7618 * preferable from a performance point of view to avoid using
7619 * a runtime relocation for this. The actual sequence of
7620 * instructions often look something like:
7621 *
7622 * call .L66
7623 * .L66:
7624 * popl %ebx
7625 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
7626 *
7627 * The call and pop essentially return the absolute address
7628 * of the label .L66 and store it in %ebx. The linker itself
7629 * will ultimately change the first operand of the addl so
7630 * that %ebx points to the GOT, but to keep things simple, the
7631 * .o file must have this operand set so that it generates not
7632 * the absolute address of .L66, but the absolute address of
7633 * itself. This allows the linker itself simply treat a GOTPC
7634 * relocation as asking for a pcrel offset to the GOT to be
7635 * added in, and the addend of the relocation is stored in the
7636 * operand field for the instruction itself.
7637 *
7638 * Our job here is to fix the operand so that it would add
7639 * the correct offset so that %ebx would point to itself. The
7640 * thing that is tricky is that .-.L66 will point to the
7641 * beginning of the instruction, so we need to further modify
7642 * the operand so that it will point to itself. There are
7643 * other cases where you have something like:
7644 *
7645 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
7646 *
7647 * and here no correction would be required. Internally in
7648 * the assembler we treat operands of this form as not being
7649 * pcrel since the '.' is explicitly mentioned, and I wonder
7650 * whether it would simplify matters to do it this way. Who
7651 * knows. In earlier versions of the PIC patches, the
7652 * pcrel_adjust field was used to store the correction, but
7653 * since the expression is not pcrel, I felt it would be
7654 * confusing to do it this way. */
7655
7656 if ((reloc_type == BFD_RELOC_32
7657 || reloc_type == BFD_RELOC_X86_64_32S
7658 || reloc_type == BFD_RELOC_64)
7659 && GOT_symbol
7660 && GOT_symbol == i.op[n].imms->X_add_symbol
7661 && (i.op[n].imms->X_op == O_symbol
7662 || (i.op[n].imms->X_op == O_add
7663 && ((symbol_get_value_expression
7664 (i.op[n].imms->X_op_symbol)->X_op)
7665 == O_subtract))))
7666 {
7667 offsetT add;
7668
7669 if (insn_start_frag == frag_now)
7670 add = (p - frag_now->fr_literal) - insn_start_off;
7671 else
7672 {
7673 fragS *fr;
7674
7675 add = insn_start_frag->fr_fix - insn_start_off;
7676 for (fr = insn_start_frag->fr_next;
7677 fr && fr != frag_now; fr = fr->fr_next)
7678 add += fr->fr_fix;
7679 add += p - frag_now->fr_literal;
7680 }
7681
7682 if (!object_64bit)
7683 reloc_type = BFD_RELOC_386_GOTPC;
7684 else if (size == 4)
7685 reloc_type = BFD_RELOC_X86_64_GOTPC32;
7686 else if (size == 8)
7687 reloc_type = BFD_RELOC_X86_64_GOTPC64;
7688 i.op[n].imms->X_add_number += add;
7689 }
7690 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
7691 i.op[n].imms, 0, reloc_type);
7692 }
7693 }
7694 }
7695 }
7696 \f
7697 /* x86_cons_fix_new is called via the expression parsing code when a
7698 reloc is needed. We use this hook to get the correct .got reloc. */
7699 static int cons_sign = -1;
7700
7701 void
7702 x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len,
7703 expressionS *exp, bfd_reloc_code_real_type r)
7704 {
7705 r = reloc (len, 0, cons_sign, r);
7706
7707 #ifdef TE_PE
7708 if (exp->X_op == O_secrel)
7709 {
7710 exp->X_op = O_symbol;
7711 r = BFD_RELOC_32_SECREL;
7712 }
7713 #endif
7714
7715 fix_new_exp (frag, off, len, exp, 0, r);
7716 }
7717
7718 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
7719 purpose of the `.dc.a' internal pseudo-op. */
7720
7721 int
7722 x86_address_bytes (void)
7723 {
7724 if ((stdoutput->arch_info->mach & bfd_mach_x64_32))
7725 return 4;
7726 return stdoutput->arch_info->bits_per_address / 8;
7727 }
7728
7729 #if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
7730 || defined (LEX_AT)
7731 # define lex_got(reloc, adjust, types) NULL
7732 #else
7733 /* Parse operands of the form
7734 <symbol>@GOTOFF+<nnn>
7735 and similar .plt or .got references.
7736
7737 If we find one, set up the correct relocation in RELOC and copy the
7738 input string, minus the `@GOTOFF' into a malloc'd buffer for
7739 parsing by the calling routine. Return this buffer, and if ADJUST
7740 is non-null set it to the length of the string we removed from the
7741 input line. Otherwise return NULL. */
7742 static char *
7743 lex_got (enum bfd_reloc_code_real *rel,
7744 int *adjust,
7745 i386_operand_type *types)
7746 {
7747 /* Some of the relocations depend on the size of what field is to
7748 be relocated. But in our callers i386_immediate and i386_displacement
7749 we don't yet know the operand size (this will be set by insn
7750 matching). Hence we record the word32 relocation here,
7751 and adjust the reloc according to the real size in reloc(). */
7752 static const struct {
7753 const char *str;
7754 int len;
7755 const enum bfd_reloc_code_real rel[2];
7756 const i386_operand_type types64;
7757 } gotrel[] = {
7758 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7759 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32,
7760 BFD_RELOC_SIZE32 },
7761 OPERAND_TYPE_IMM32_64 },
7762 #endif
7763 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real,
7764 BFD_RELOC_X86_64_PLTOFF64 },
7765 OPERAND_TYPE_IMM64 },
7766 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32,
7767 BFD_RELOC_X86_64_PLT32 },
7768 OPERAND_TYPE_IMM32_32S_DISP32 },
7769 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real,
7770 BFD_RELOC_X86_64_GOTPLT64 },
7771 OPERAND_TYPE_IMM64_DISP64 },
7772 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF,
7773 BFD_RELOC_X86_64_GOTOFF64 },
7774 OPERAND_TYPE_IMM64_DISP64 },
7775 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real,
7776 BFD_RELOC_X86_64_GOTPCREL },
7777 OPERAND_TYPE_IMM32_32S_DISP32 },
7778 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD,
7779 BFD_RELOC_X86_64_TLSGD },
7780 OPERAND_TYPE_IMM32_32S_DISP32 },
7781 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM,
7782 _dummy_first_bfd_reloc_code_real },
7783 OPERAND_TYPE_NONE },
7784 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real,
7785 BFD_RELOC_X86_64_TLSLD },
7786 OPERAND_TYPE_IMM32_32S_DISP32 },
7787 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32,
7788 BFD_RELOC_X86_64_GOTTPOFF },
7789 OPERAND_TYPE_IMM32_32S_DISP32 },
7790 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32,
7791 BFD_RELOC_X86_64_TPOFF32 },
7792 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
7793 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE,
7794 _dummy_first_bfd_reloc_code_real },
7795 OPERAND_TYPE_NONE },
7796 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32,
7797 BFD_RELOC_X86_64_DTPOFF32 },
7798 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
7799 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE,
7800 _dummy_first_bfd_reloc_code_real },
7801 OPERAND_TYPE_NONE },
7802 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE,
7803 _dummy_first_bfd_reloc_code_real },
7804 OPERAND_TYPE_NONE },
7805 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32,
7806 BFD_RELOC_X86_64_GOT32 },
7807 OPERAND_TYPE_IMM32_32S_64_DISP32 },
7808 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC,
7809 BFD_RELOC_X86_64_GOTPC32_TLSDESC },
7810 OPERAND_TYPE_IMM32_32S_DISP32 },
7811 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL,
7812 BFD_RELOC_X86_64_TLSDESC_CALL },
7813 OPERAND_TYPE_IMM32_32S_DISP32 },
7814 };
7815 char *cp;
7816 unsigned int j;
7817
7818 #if defined (OBJ_MAYBE_ELF)
7819 if (!IS_ELF)
7820 return NULL;
7821 #endif
7822
7823 for (cp = input_line_pointer; *cp != '@'; cp++)
7824 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
7825 return NULL;
7826
7827 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
7828 {
7829 int len = gotrel[j].len;
7830 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
7831 {
7832 if (gotrel[j].rel[object_64bit] != 0)
7833 {
7834 int first, second;
7835 char *tmpbuf, *past_reloc;
7836
7837 *rel = gotrel[j].rel[object_64bit];
7838
7839 if (types)
7840 {
7841 if (flag_code != CODE_64BIT)
7842 {
7843 types->bitfield.imm32 = 1;
7844 types->bitfield.disp32 = 1;
7845 }
7846 else
7847 *types = gotrel[j].types64;
7848 }
7849
7850 if (j != 0 && GOT_symbol == NULL)
7851 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
7852
7853 /* The length of the first part of our input line. */
7854 first = cp - input_line_pointer;
7855
7856 /* The second part goes from after the reloc token until
7857 (and including) an end_of_line char or comma. */
7858 past_reloc = cp + 1 + len;
7859 cp = past_reloc;
7860 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
7861 ++cp;
7862 second = cp + 1 - past_reloc;
7863
7864 /* Allocate and copy string. The trailing NUL shouldn't
7865 be necessary, but be safe. */
7866 tmpbuf = XNEWVEC (char, first + second + 2);
7867 memcpy (tmpbuf, input_line_pointer, first);
7868 if (second != 0 && *past_reloc != ' ')
7869 /* Replace the relocation token with ' ', so that
7870 errors like foo@GOTOFF1 will be detected. */
7871 tmpbuf[first++] = ' ';
7872 else
7873 /* Increment length by 1 if the relocation token is
7874 removed. */
7875 len++;
7876 if (adjust)
7877 *adjust = len;
7878 memcpy (tmpbuf + first, past_reloc, second);
7879 tmpbuf[first + second] = '\0';
7880 return tmpbuf;
7881 }
7882
7883 as_bad (_("@%s reloc is not supported with %d-bit output format"),
7884 gotrel[j].str, 1 << (5 + object_64bit));
7885 return NULL;
7886 }
7887 }
7888
7889 /* Might be a symbol version string. Don't as_bad here. */
7890 return NULL;
7891 }
7892 #endif
7893
7894 #ifdef TE_PE
7895 #ifdef lex_got
7896 #undef lex_got
7897 #endif
7898 /* Parse operands of the form
7899 <symbol>@SECREL32+<nnn>
7900
7901 If we find one, set up the correct relocation in RELOC and copy the
7902 input string, minus the `@SECREL32' into a malloc'd buffer for
7903 parsing by the calling routine. Return this buffer, and if ADJUST
7904 is non-null set it to the length of the string we removed from the
7905 input line. Otherwise return NULL.
7906
7907 This function is copied from the ELF version above adjusted for PE targets. */
7908
7909 static char *
7910 lex_got (enum bfd_reloc_code_real *rel ATTRIBUTE_UNUSED,
7911 int *adjust ATTRIBUTE_UNUSED,
7912 i386_operand_type *types)
7913 {
7914 static const struct
7915 {
7916 const char *str;
7917 int len;
7918 const enum bfd_reloc_code_real rel[2];
7919 const i386_operand_type types64;
7920 }
7921 gotrel[] =
7922 {
7923 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL,
7924 BFD_RELOC_32_SECREL },
7925 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
7926 };
7927
7928 char *cp;
7929 unsigned j;
7930
7931 for (cp = input_line_pointer; *cp != '@'; cp++)
7932 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
7933 return NULL;
7934
7935 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
7936 {
7937 int len = gotrel[j].len;
7938
7939 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
7940 {
7941 if (gotrel[j].rel[object_64bit] != 0)
7942 {
7943 int first, second;
7944 char *tmpbuf, *past_reloc;
7945
7946 *rel = gotrel[j].rel[object_64bit];
7947 if (adjust)
7948 *adjust = len;
7949
7950 if (types)
7951 {
7952 if (flag_code != CODE_64BIT)
7953 {
7954 types->bitfield.imm32 = 1;
7955 types->bitfield.disp32 = 1;
7956 }
7957 else
7958 *types = gotrel[j].types64;
7959 }
7960
7961 /* The length of the first part of our input line. */
7962 first = cp - input_line_pointer;
7963
7964 /* The second part goes from after the reloc token until
7965 (and including) an end_of_line char or comma. */
7966 past_reloc = cp + 1 + len;
7967 cp = past_reloc;
7968 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
7969 ++cp;
7970 second = cp + 1 - past_reloc;
7971
7972 /* Allocate and copy string. The trailing NUL shouldn't
7973 be necessary, but be safe. */
7974 tmpbuf = XNEWVEC (char, first + second + 2);
7975 memcpy (tmpbuf, input_line_pointer, first);
7976 if (second != 0 && *past_reloc != ' ')
7977 /* Replace the relocation token with ' ', so that
7978 errors like foo@SECLREL321 will be detected. */
7979 tmpbuf[first++] = ' ';
7980 memcpy (tmpbuf + first, past_reloc, second);
7981 tmpbuf[first + second] = '\0';
7982 return tmpbuf;
7983 }
7984
7985 as_bad (_("@%s reloc is not supported with %d-bit output format"),
7986 gotrel[j].str, 1 << (5 + object_64bit));
7987 return NULL;
7988 }
7989 }
7990
7991 /* Might be a symbol version string. Don't as_bad here. */
7992 return NULL;
7993 }
7994
7995 #endif /* TE_PE */
7996
7997 bfd_reloc_code_real_type
7998 x86_cons (expressionS *exp, int size)
7999 {
8000 bfd_reloc_code_real_type got_reloc = NO_RELOC;
8001
8002 intel_syntax = -intel_syntax;
8003
8004 exp->X_md = 0;
8005 if (size == 4 || (object_64bit && size == 8))
8006 {
8007 /* Handle @GOTOFF and the like in an expression. */
8008 char *save;
8009 char *gotfree_input_line;
8010 int adjust = 0;
8011
8012 save = input_line_pointer;
8013 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
8014 if (gotfree_input_line)
8015 input_line_pointer = gotfree_input_line;
8016
8017 expression (exp);
8018
8019 if (gotfree_input_line)
8020 {
8021 /* expression () has merrily parsed up to the end of line,
8022 or a comma - in the wrong buffer. Transfer how far
8023 input_line_pointer has moved to the right buffer. */
8024 input_line_pointer = (save
8025 + (input_line_pointer - gotfree_input_line)
8026 + adjust);
8027 free (gotfree_input_line);
8028 if (exp->X_op == O_constant
8029 || exp->X_op == O_absent
8030 || exp->X_op == O_illegal
8031 || exp->X_op == O_register
8032 || exp->X_op == O_big)
8033 {
8034 char c = *input_line_pointer;
8035 *input_line_pointer = 0;
8036 as_bad (_("missing or invalid expression `%s'"), save);
8037 *input_line_pointer = c;
8038 }
8039 }
8040 }
8041 else
8042 expression (exp);
8043
8044 intel_syntax = -intel_syntax;
8045
8046 if (intel_syntax)
8047 i386_intel_simplify (exp);
8048
8049 return got_reloc;
8050 }
8051
8052 static void
8053 signed_cons (int size)
8054 {
8055 if (flag_code == CODE_64BIT)
8056 cons_sign = 1;
8057 cons (size);
8058 cons_sign = -1;
8059 }
8060
8061 #ifdef TE_PE
8062 static void
8063 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED)
8064 {
8065 expressionS exp;
8066
8067 do
8068 {
8069 expression (&exp);
8070 if (exp.X_op == O_symbol)
8071 exp.X_op = O_secrel;
8072
8073 emit_expr (&exp, 4);
8074 }
8075 while (*input_line_pointer++ == ',');
8076
8077 input_line_pointer--;
8078 demand_empty_rest_of_line ();
8079 }
8080 #endif
8081
8082 /* Handle Vector operations. */
8083
8084 static char *
8085 check_VecOperations (char *op_string, char *op_end)
8086 {
8087 const reg_entry *mask;
8088 const char *saved;
8089 char *end_op;
8090
8091 while (*op_string
8092 && (op_end == NULL || op_string < op_end))
8093 {
8094 saved = op_string;
8095 if (*op_string == '{')
8096 {
8097 op_string++;
8098
8099 /* Check broadcasts. */
8100 if (strncmp (op_string, "1to", 3) == 0)
8101 {
8102 int bcst_type;
8103
8104 if (i.broadcast)
8105 goto duplicated_vec_op;
8106
8107 op_string += 3;
8108 if (*op_string == '8')
8109 bcst_type = BROADCAST_1TO8;
8110 else if (*op_string == '4')
8111 bcst_type = BROADCAST_1TO4;
8112 else if (*op_string == '2')
8113 bcst_type = BROADCAST_1TO2;
8114 else if (*op_string == '1'
8115 && *(op_string+1) == '6')
8116 {
8117 bcst_type = BROADCAST_1TO16;
8118 op_string++;
8119 }
8120 else
8121 {
8122 as_bad (_("Unsupported broadcast: `%s'"), saved);
8123 return NULL;
8124 }
8125 op_string++;
8126
8127 broadcast_op.type = bcst_type;
8128 broadcast_op.operand = this_operand;
8129 i.broadcast = &broadcast_op;
8130 }
8131 /* Check masking operation. */
8132 else if ((mask = parse_register (op_string, &end_op)) != NULL)
8133 {
8134 /* k0 can't be used for write mask. */
8135 if (mask->reg_num == 0)
8136 {
8137 as_bad (_("`%s' can't be used for write mask"),
8138 op_string);
8139 return NULL;
8140 }
8141
8142 if (!i.mask)
8143 {
8144 mask_op.mask = mask;
8145 mask_op.zeroing = 0;
8146 mask_op.operand = this_operand;
8147 i.mask = &mask_op;
8148 }
8149 else
8150 {
8151 if (i.mask->mask)
8152 goto duplicated_vec_op;
8153
8154 i.mask->mask = mask;
8155
8156 /* Only "{z}" is allowed here. No need to check
8157 zeroing mask explicitly. */
8158 if (i.mask->operand != this_operand)
8159 {
8160 as_bad (_("invalid write mask `%s'"), saved);
8161 return NULL;
8162 }
8163 }
8164
8165 op_string = end_op;
8166 }
8167 /* Check zeroing-flag for masking operation. */
8168 else if (*op_string == 'z')
8169 {
8170 if (!i.mask)
8171 {
8172 mask_op.mask = NULL;
8173 mask_op.zeroing = 1;
8174 mask_op.operand = this_operand;
8175 i.mask = &mask_op;
8176 }
8177 else
8178 {
8179 if (i.mask->zeroing)
8180 {
8181 duplicated_vec_op:
8182 as_bad (_("duplicated `%s'"), saved);
8183 return NULL;
8184 }
8185
8186 i.mask->zeroing = 1;
8187
8188 /* Only "{%k}" is allowed here. No need to check mask
8189 register explicitly. */
8190 if (i.mask->operand != this_operand)
8191 {
8192 as_bad (_("invalid zeroing-masking `%s'"),
8193 saved);
8194 return NULL;
8195 }
8196 }
8197
8198 op_string++;
8199 }
8200 else
8201 goto unknown_vec_op;
8202
8203 if (*op_string != '}')
8204 {
8205 as_bad (_("missing `}' in `%s'"), saved);
8206 return NULL;
8207 }
8208 op_string++;
8209 continue;
8210 }
8211 unknown_vec_op:
8212 /* We don't know this one. */
8213 as_bad (_("unknown vector operation: `%s'"), saved);
8214 return NULL;
8215 }
8216
8217 return op_string;
8218 }
8219
8220 static int
8221 i386_immediate (char *imm_start)
8222 {
8223 char *save_input_line_pointer;
8224 char *gotfree_input_line;
8225 segT exp_seg = 0;
8226 expressionS *exp;
8227 i386_operand_type types;
8228
8229 operand_type_set (&types, ~0);
8230
8231 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
8232 {
8233 as_bad (_("at most %d immediate operands are allowed"),
8234 MAX_IMMEDIATE_OPERANDS);
8235 return 0;
8236 }
8237
8238 exp = &im_expressions[i.imm_operands++];
8239 i.op[this_operand].imms = exp;
8240
8241 if (is_space_char (*imm_start))
8242 ++imm_start;
8243
8244 save_input_line_pointer = input_line_pointer;
8245 input_line_pointer = imm_start;
8246
8247 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
8248 if (gotfree_input_line)
8249 input_line_pointer = gotfree_input_line;
8250
8251 exp_seg = expression (exp);
8252
8253 SKIP_WHITESPACE ();
8254
8255 /* Handle vector operations. */
8256 if (*input_line_pointer == '{')
8257 {
8258 input_line_pointer = check_VecOperations (input_line_pointer,
8259 NULL);
8260 if (input_line_pointer == NULL)
8261 return 0;
8262 }
8263
8264 if (*input_line_pointer)
8265 as_bad (_("junk `%s' after expression"), input_line_pointer);
8266
8267 input_line_pointer = save_input_line_pointer;
8268 if (gotfree_input_line)
8269 {
8270 free (gotfree_input_line);
8271
8272 if (exp->X_op == O_constant || exp->X_op == O_register)
8273 exp->X_op = O_illegal;
8274 }
8275
8276 return i386_finalize_immediate (exp_seg, exp, types, imm_start);
8277 }
8278
8279 static int
8280 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
8281 i386_operand_type types, const char *imm_start)
8282 {
8283 if (exp->X_op == O_absent || exp->X_op == O_illegal || exp->X_op == O_big)
8284 {
8285 if (imm_start)
8286 as_bad (_("missing or invalid immediate expression `%s'"),
8287 imm_start);
8288 return 0;
8289 }
8290 else if (exp->X_op == O_constant)
8291 {
8292 /* Size it properly later. */
8293 i.types[this_operand].bitfield.imm64 = 1;
8294 /* If not 64bit, sign extend val. */
8295 if (flag_code != CODE_64BIT
8296 && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
8297 exp->X_add_number
8298 = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
8299 }
8300 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8301 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
8302 && exp_seg != absolute_section
8303 && exp_seg != text_section
8304 && exp_seg != data_section
8305 && exp_seg != bss_section
8306 && exp_seg != undefined_section
8307 && !bfd_is_com_section (exp_seg))
8308 {
8309 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
8310 return 0;
8311 }
8312 #endif
8313 else if (!intel_syntax && exp_seg == reg_section)
8314 {
8315 if (imm_start)
8316 as_bad (_("illegal immediate register operand %s"), imm_start);
8317 return 0;
8318 }
8319 else
8320 {
8321 /* This is an address. The size of the address will be
8322 determined later, depending on destination register,
8323 suffix, or the default for the section. */
8324 i.types[this_operand].bitfield.imm8 = 1;
8325 i.types[this_operand].bitfield.imm16 = 1;
8326 i.types[this_operand].bitfield.imm32 = 1;
8327 i.types[this_operand].bitfield.imm32s = 1;
8328 i.types[this_operand].bitfield.imm64 = 1;
8329 i.types[this_operand] = operand_type_and (i.types[this_operand],
8330 types);
8331 }
8332
8333 return 1;
8334 }
8335
8336 static char *
8337 i386_scale (char *scale)
8338 {
8339 offsetT val;
8340 char *save = input_line_pointer;
8341
8342 input_line_pointer = scale;
8343 val = get_absolute_expression ();
8344
8345 switch (val)
8346 {
8347 case 1:
8348 i.log2_scale_factor = 0;
8349 break;
8350 case 2:
8351 i.log2_scale_factor = 1;
8352 break;
8353 case 4:
8354 i.log2_scale_factor = 2;
8355 break;
8356 case 8:
8357 i.log2_scale_factor = 3;
8358 break;
8359 default:
8360 {
8361 char sep = *input_line_pointer;
8362
8363 *input_line_pointer = '\0';
8364 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
8365 scale);
8366 *input_line_pointer = sep;
8367 input_line_pointer = save;
8368 return NULL;
8369 }
8370 }
8371 if (i.log2_scale_factor != 0 && i.index_reg == 0)
8372 {
8373 as_warn (_("scale factor of %d without an index register"),
8374 1 << i.log2_scale_factor);
8375 i.log2_scale_factor = 0;
8376 }
8377 scale = input_line_pointer;
8378 input_line_pointer = save;
8379 return scale;
8380 }
8381
8382 static int
8383 i386_displacement (char *disp_start, char *disp_end)
8384 {
8385 expressionS *exp;
8386 segT exp_seg = 0;
8387 char *save_input_line_pointer;
8388 char *gotfree_input_line;
8389 int override;
8390 i386_operand_type bigdisp, types = anydisp;
8391 int ret;
8392
8393 if (i.disp_operands == MAX_MEMORY_OPERANDS)
8394 {
8395 as_bad (_("at most %d displacement operands are allowed"),
8396 MAX_MEMORY_OPERANDS);
8397 return 0;
8398 }
8399
8400 operand_type_set (&bigdisp, 0);
8401 if ((i.types[this_operand].bitfield.jumpabsolute)
8402 || (!current_templates->start->opcode_modifier.jump
8403 && !current_templates->start->opcode_modifier.jumpdword))
8404 {
8405 bigdisp.bitfield.disp32 = 1;
8406 override = (i.prefix[ADDR_PREFIX] != 0);
8407 if (flag_code == CODE_64BIT)
8408 {
8409 if (!override)
8410 {
8411 bigdisp.bitfield.disp32s = 1;
8412 bigdisp.bitfield.disp64 = 1;
8413 }
8414 }
8415 else if ((flag_code == CODE_16BIT) ^ override)
8416 {
8417 bigdisp.bitfield.disp32 = 0;
8418 bigdisp.bitfield.disp16 = 1;
8419 }
8420 }
8421 else
8422 {
8423 /* For PC-relative branches, the width of the displacement
8424 is dependent upon data size, not address size. */
8425 override = (i.prefix[DATA_PREFIX] != 0);
8426 if (flag_code == CODE_64BIT)
8427 {
8428 if (override || i.suffix == WORD_MNEM_SUFFIX)
8429 bigdisp.bitfield.disp16 = 1;
8430 else
8431 {
8432 bigdisp.bitfield.disp32 = 1;
8433 bigdisp.bitfield.disp32s = 1;
8434 }
8435 }
8436 else
8437 {
8438 if (!override)
8439 override = (i.suffix == (flag_code != CODE_16BIT
8440 ? WORD_MNEM_SUFFIX
8441 : LONG_MNEM_SUFFIX));
8442 bigdisp.bitfield.disp32 = 1;
8443 if ((flag_code == CODE_16BIT) ^ override)
8444 {
8445 bigdisp.bitfield.disp32 = 0;
8446 bigdisp.bitfield.disp16 = 1;
8447 }
8448 }
8449 }
8450 i.types[this_operand] = operand_type_or (i.types[this_operand],
8451 bigdisp);
8452
8453 exp = &disp_expressions[i.disp_operands];
8454 i.op[this_operand].disps = exp;
8455 i.disp_operands++;
8456 save_input_line_pointer = input_line_pointer;
8457 input_line_pointer = disp_start;
8458 END_STRING_AND_SAVE (disp_end);
8459
8460 #ifndef GCC_ASM_O_HACK
8461 #define GCC_ASM_O_HACK 0
8462 #endif
8463 #if GCC_ASM_O_HACK
8464 END_STRING_AND_SAVE (disp_end + 1);
8465 if (i.types[this_operand].bitfield.baseIndex
8466 && displacement_string_end[-1] == '+')
8467 {
8468 /* This hack is to avoid a warning when using the "o"
8469 constraint within gcc asm statements.
8470 For instance:
8471
8472 #define _set_tssldt_desc(n,addr,limit,type) \
8473 __asm__ __volatile__ ( \
8474 "movw %w2,%0\n\t" \
8475 "movw %w1,2+%0\n\t" \
8476 "rorl $16,%1\n\t" \
8477 "movb %b1,4+%0\n\t" \
8478 "movb %4,5+%0\n\t" \
8479 "movb $0,6+%0\n\t" \
8480 "movb %h1,7+%0\n\t" \
8481 "rorl $16,%1" \
8482 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
8483
8484 This works great except that the output assembler ends
8485 up looking a bit weird if it turns out that there is
8486 no offset. You end up producing code that looks like:
8487
8488 #APP
8489 movw $235,(%eax)
8490 movw %dx,2+(%eax)
8491 rorl $16,%edx
8492 movb %dl,4+(%eax)
8493 movb $137,5+(%eax)
8494 movb $0,6+(%eax)
8495 movb %dh,7+(%eax)
8496 rorl $16,%edx
8497 #NO_APP
8498
8499 So here we provide the missing zero. */
8500
8501 *displacement_string_end = '0';
8502 }
8503 #endif
8504 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
8505 if (gotfree_input_line)
8506 input_line_pointer = gotfree_input_line;
8507
8508 exp_seg = expression (exp);
8509
8510 SKIP_WHITESPACE ();
8511 if (*input_line_pointer)
8512 as_bad (_("junk `%s' after expression"), input_line_pointer);
8513 #if GCC_ASM_O_HACK
8514 RESTORE_END_STRING (disp_end + 1);
8515 #endif
8516 input_line_pointer = save_input_line_pointer;
8517 if (gotfree_input_line)
8518 {
8519 free (gotfree_input_line);
8520
8521 if (exp->X_op == O_constant || exp->X_op == O_register)
8522 exp->X_op = O_illegal;
8523 }
8524
8525 ret = i386_finalize_displacement (exp_seg, exp, types, disp_start);
8526
8527 RESTORE_END_STRING (disp_end);
8528
8529 return ret;
8530 }
8531
8532 static int
8533 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
8534 i386_operand_type types, const char *disp_start)
8535 {
8536 i386_operand_type bigdisp;
8537 int ret = 1;
8538
8539 /* We do this to make sure that the section symbol is in
8540 the symbol table. We will ultimately change the relocation
8541 to be relative to the beginning of the section. */
8542 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
8543 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
8544 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
8545 {
8546 if (exp->X_op != O_symbol)
8547 goto inv_disp;
8548
8549 if (S_IS_LOCAL (exp->X_add_symbol)
8550 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section
8551 && S_GET_SEGMENT (exp->X_add_symbol) != expr_section)
8552 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
8553 exp->X_op = O_subtract;
8554 exp->X_op_symbol = GOT_symbol;
8555 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
8556 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
8557 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
8558 i.reloc[this_operand] = BFD_RELOC_64;
8559 else
8560 i.reloc[this_operand] = BFD_RELOC_32;
8561 }
8562
8563 else if (exp->X_op == O_absent
8564 || exp->X_op == O_illegal
8565 || exp->X_op == O_big)
8566 {
8567 inv_disp:
8568 as_bad (_("missing or invalid displacement expression `%s'"),
8569 disp_start);
8570 ret = 0;
8571 }
8572
8573 else if (flag_code == CODE_64BIT
8574 && !i.prefix[ADDR_PREFIX]
8575 && exp->X_op == O_constant)
8576 {
8577 /* Since displacement is signed extended to 64bit, don't allow
8578 disp32 and turn off disp32s if they are out of range. */
8579 i.types[this_operand].bitfield.disp32 = 0;
8580 if (!fits_in_signed_long (exp->X_add_number))
8581 {
8582 i.types[this_operand].bitfield.disp32s = 0;
8583 if (i.types[this_operand].bitfield.baseindex)
8584 {
8585 as_bad (_("0x%lx out range of signed 32bit displacement"),
8586 (long) exp->X_add_number);
8587 ret = 0;
8588 }
8589 }
8590 }
8591
8592 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8593 else if (exp->X_op != O_constant
8594 && OUTPUT_FLAVOR == bfd_target_aout_flavour
8595 && exp_seg != absolute_section
8596 && exp_seg != text_section
8597 && exp_seg != data_section
8598 && exp_seg != bss_section
8599 && exp_seg != undefined_section
8600 && !bfd_is_com_section (exp_seg))
8601 {
8602 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
8603 ret = 0;
8604 }
8605 #endif
8606
8607 /* Check if this is a displacement only operand. */
8608 bigdisp = i.types[this_operand];
8609 bigdisp.bitfield.disp8 = 0;
8610 bigdisp.bitfield.disp16 = 0;
8611 bigdisp.bitfield.disp32 = 0;
8612 bigdisp.bitfield.disp32s = 0;
8613 bigdisp.bitfield.disp64 = 0;
8614 if (operand_type_all_zero (&bigdisp))
8615 i.types[this_operand] = operand_type_and (i.types[this_operand],
8616 types);
8617
8618 return ret;
8619 }
8620
8621 /* Make sure the memory operand we've been dealt is valid.
8622 Return 1 on success, 0 on a failure. */
8623
8624 static int
8625 i386_index_check (const char *operand_string)
8626 {
8627 const char *kind = "base/index";
8628 enum flag_code addr_mode;
8629
8630 if (i.prefix[ADDR_PREFIX])
8631 addr_mode = flag_code == CODE_32BIT ? CODE_16BIT : CODE_32BIT;
8632 else
8633 {
8634 addr_mode = flag_code;
8635
8636 #if INFER_ADDR_PREFIX
8637 if (i.mem_operands == 0)
8638 {
8639 /* Infer address prefix from the first memory operand. */
8640 const reg_entry *addr_reg = i.base_reg;
8641
8642 if (addr_reg == NULL)
8643 addr_reg = i.index_reg;
8644
8645 if (addr_reg)
8646 {
8647 if (addr_reg->reg_num == RegEip
8648 || addr_reg->reg_num == RegEiz
8649 || addr_reg->reg_type.bitfield.reg32)
8650 addr_mode = CODE_32BIT;
8651 else if (flag_code != CODE_64BIT
8652 && addr_reg->reg_type.bitfield.reg16)
8653 addr_mode = CODE_16BIT;
8654
8655 if (addr_mode != flag_code)
8656 {
8657 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
8658 i.prefixes += 1;
8659 /* Change the size of any displacement too. At most one
8660 of Disp16 or Disp32 is set.
8661 FIXME. There doesn't seem to be any real need for
8662 separate Disp16 and Disp32 flags. The same goes for
8663 Imm16 and Imm32. Removing them would probably clean
8664 up the code quite a lot. */
8665 if (flag_code != CODE_64BIT
8666 && (i.types[this_operand].bitfield.disp16
8667 || i.types[this_operand].bitfield.disp32))
8668 i.types[this_operand]
8669 = operand_type_xor (i.types[this_operand], disp16_32);
8670 }
8671 }
8672 }
8673 #endif
8674 }
8675
8676 if (current_templates->start->opcode_modifier.isstring
8677 && !current_templates->start->opcode_modifier.immext
8678 && (current_templates->end[-1].opcode_modifier.isstring
8679 || i.mem_operands))
8680 {
8681 /* Memory operands of string insns are special in that they only allow
8682 a single register (rDI, rSI, or rBX) as their memory address. */
8683 const reg_entry *expected_reg;
8684 static const char *di_si[][2] =
8685 {
8686 { "esi", "edi" },
8687 { "si", "di" },
8688 { "rsi", "rdi" }
8689 };
8690 static const char *bx[] = { "ebx", "bx", "rbx" };
8691
8692 kind = "string address";
8693
8694 if (current_templates->start->opcode_modifier.repprefixok)
8695 {
8696 i386_operand_type type = current_templates->end[-1].operand_types[0];
8697
8698 if (!type.bitfield.baseindex
8699 || ((!i.mem_operands != !intel_syntax)
8700 && current_templates->end[-1].operand_types[1]
8701 .bitfield.baseindex))
8702 type = current_templates->end[-1].operand_types[1];
8703 expected_reg = hash_find (reg_hash,
8704 di_si[addr_mode][type.bitfield.esseg]);
8705
8706 }
8707 else
8708 expected_reg = hash_find (reg_hash, bx[addr_mode]);
8709
8710 if (i.base_reg != expected_reg
8711 || i.index_reg
8712 || operand_type_check (i.types[this_operand], disp))
8713 {
8714 /* The second memory operand must have the same size as
8715 the first one. */
8716 if (i.mem_operands
8717 && i.base_reg
8718 && !((addr_mode == CODE_64BIT
8719 && i.base_reg->reg_type.bitfield.reg64)
8720 || (addr_mode == CODE_32BIT
8721 ? i.base_reg->reg_type.bitfield.reg32
8722 : i.base_reg->reg_type.bitfield.reg16)))
8723 goto bad_address;
8724
8725 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
8726 operand_string,
8727 intel_syntax ? '[' : '(',
8728 register_prefix,
8729 expected_reg->reg_name,
8730 intel_syntax ? ']' : ')');
8731 return 1;
8732 }
8733 else
8734 return 1;
8735
8736 bad_address:
8737 as_bad (_("`%s' is not a valid %s expression"),
8738 operand_string, kind);
8739 return 0;
8740 }
8741 else
8742 {
8743 if (addr_mode != CODE_16BIT)
8744 {
8745 /* 32-bit/64-bit checks. */
8746 if ((i.base_reg
8747 && (addr_mode == CODE_64BIT
8748 ? !i.base_reg->reg_type.bitfield.reg64
8749 : !i.base_reg->reg_type.bitfield.reg32)
8750 && (i.index_reg
8751 || (i.base_reg->reg_num
8752 != (addr_mode == CODE_64BIT ? RegRip : RegEip))))
8753 || (i.index_reg
8754 && !i.index_reg->reg_type.bitfield.regxmm
8755 && !i.index_reg->reg_type.bitfield.regymm
8756 && !i.index_reg->reg_type.bitfield.regzmm
8757 && ((addr_mode == CODE_64BIT
8758 ? !(i.index_reg->reg_type.bitfield.reg64
8759 || i.index_reg->reg_num == RegRiz)
8760 : !(i.index_reg->reg_type.bitfield.reg32
8761 || i.index_reg->reg_num == RegEiz))
8762 || !i.index_reg->reg_type.bitfield.baseindex)))
8763 goto bad_address;
8764
8765 /* bndmk, bndldx, and bndstx have special restrictions. */
8766 if (current_templates->start->base_opcode == 0xf30f1b
8767 || (current_templates->start->base_opcode & ~1) == 0x0f1a)
8768 {
8769 /* They cannot use RIP-relative addressing. */
8770 if (i.base_reg && i.base_reg->reg_num == RegRip)
8771 {
8772 as_bad (_("`%s' cannot be used here"), operand_string);
8773 return 0;
8774 }
8775
8776 /* bndldx and bndstx ignore their scale factor. */
8777 if (current_templates->start->base_opcode != 0xf30f1b
8778 && i.log2_scale_factor)
8779 as_warn (_("register scaling is being ignored here"));
8780 }
8781 }
8782 else
8783 {
8784 /* 16-bit checks. */
8785 if ((i.base_reg
8786 && (!i.base_reg->reg_type.bitfield.reg16
8787 || !i.base_reg->reg_type.bitfield.baseindex))
8788 || (i.index_reg
8789 && (!i.index_reg->reg_type.bitfield.reg16
8790 || !i.index_reg->reg_type.bitfield.baseindex
8791 || !(i.base_reg
8792 && i.base_reg->reg_num < 6
8793 && i.index_reg->reg_num >= 6
8794 && i.log2_scale_factor == 0))))
8795 goto bad_address;
8796 }
8797 }
8798 return 1;
8799 }
8800
8801 /* Handle vector immediates. */
8802
8803 static int
8804 RC_SAE_immediate (const char *imm_start)
8805 {
8806 unsigned int match_found, j;
8807 const char *pstr = imm_start;
8808 expressionS *exp;
8809
8810 if (*pstr != '{')
8811 return 0;
8812
8813 pstr++;
8814 match_found = 0;
8815 for (j = 0; j < ARRAY_SIZE (RC_NamesTable); j++)
8816 {
8817 if (!strncmp (pstr, RC_NamesTable[j].name, RC_NamesTable[j].len))
8818 {
8819 if (!i.rounding)
8820 {
8821 rc_op.type = RC_NamesTable[j].type;
8822 rc_op.operand = this_operand;
8823 i.rounding = &rc_op;
8824 }
8825 else
8826 {
8827 as_bad (_("duplicated `%s'"), imm_start);
8828 return 0;
8829 }
8830 pstr += RC_NamesTable[j].len;
8831 match_found = 1;
8832 break;
8833 }
8834 }
8835 if (!match_found)
8836 return 0;
8837
8838 if (*pstr++ != '}')
8839 {
8840 as_bad (_("Missing '}': '%s'"), imm_start);
8841 return 0;
8842 }
8843 /* RC/SAE immediate string should contain nothing more. */;
8844 if (*pstr != 0)
8845 {
8846 as_bad (_("Junk after '}': '%s'"), imm_start);
8847 return 0;
8848 }
8849
8850 exp = &im_expressions[i.imm_operands++];
8851 i.op[this_operand].imms = exp;
8852
8853 exp->X_op = O_constant;
8854 exp->X_add_number = 0;
8855 exp->X_add_symbol = (symbolS *) 0;
8856 exp->X_op_symbol = (symbolS *) 0;
8857
8858 i.types[this_operand].bitfield.imm8 = 1;
8859 return 1;
8860 }
8861
8862 /* Only string instructions can have a second memory operand, so
8863 reduce current_templates to just those if it contains any. */
8864 static int
8865 maybe_adjust_templates (void)
8866 {
8867 const insn_template *t;
8868
8869 gas_assert (i.mem_operands == 1);
8870
8871 for (t = current_templates->start; t < current_templates->end; ++t)
8872 if (t->opcode_modifier.isstring)
8873 break;
8874
8875 if (t < current_templates->end)
8876 {
8877 static templates aux_templates;
8878 bfd_boolean recheck;
8879
8880 aux_templates.start = t;
8881 for (; t < current_templates->end; ++t)
8882 if (!t->opcode_modifier.isstring)
8883 break;
8884 aux_templates.end = t;
8885
8886 /* Determine whether to re-check the first memory operand. */
8887 recheck = (aux_templates.start != current_templates->start
8888 || t != current_templates->end);
8889
8890 current_templates = &aux_templates;
8891
8892 if (recheck)
8893 {
8894 i.mem_operands = 0;
8895 if (i.memop1_string != NULL
8896 && i386_index_check (i.memop1_string) == 0)
8897 return 0;
8898 i.mem_operands = 1;
8899 }
8900 }
8901
8902 return 1;
8903 }
8904
8905 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
8906 on error. */
8907
8908 static int
8909 i386_att_operand (char *operand_string)
8910 {
8911 const reg_entry *r;
8912 char *end_op;
8913 char *op_string = operand_string;
8914
8915 if (is_space_char (*op_string))
8916 ++op_string;
8917
8918 /* We check for an absolute prefix (differentiating,
8919 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
8920 if (*op_string == ABSOLUTE_PREFIX)
8921 {
8922 ++op_string;
8923 if (is_space_char (*op_string))
8924 ++op_string;
8925 i.types[this_operand].bitfield.jumpabsolute = 1;
8926 }
8927
8928 /* Check if operand is a register. */
8929 if ((r = parse_register (op_string, &end_op)) != NULL)
8930 {
8931 i386_operand_type temp;
8932
8933 /* Check for a segment override by searching for ':' after a
8934 segment register. */
8935 op_string = end_op;
8936 if (is_space_char (*op_string))
8937 ++op_string;
8938 if (*op_string == ':'
8939 && (r->reg_type.bitfield.sreg2
8940 || r->reg_type.bitfield.sreg3))
8941 {
8942 switch (r->reg_num)
8943 {
8944 case 0:
8945 i.seg[i.mem_operands] = &es;
8946 break;
8947 case 1:
8948 i.seg[i.mem_operands] = &cs;
8949 break;
8950 case 2:
8951 i.seg[i.mem_operands] = &ss;
8952 break;
8953 case 3:
8954 i.seg[i.mem_operands] = &ds;
8955 break;
8956 case 4:
8957 i.seg[i.mem_operands] = &fs;
8958 break;
8959 case 5:
8960 i.seg[i.mem_operands] = &gs;
8961 break;
8962 }
8963
8964 /* Skip the ':' and whitespace. */
8965 ++op_string;
8966 if (is_space_char (*op_string))
8967 ++op_string;
8968
8969 if (!is_digit_char (*op_string)
8970 && !is_identifier_char (*op_string)
8971 && *op_string != '('
8972 && *op_string != ABSOLUTE_PREFIX)
8973 {
8974 as_bad (_("bad memory operand `%s'"), op_string);
8975 return 0;
8976 }
8977 /* Handle case of %es:*foo. */
8978 if (*op_string == ABSOLUTE_PREFIX)
8979 {
8980 ++op_string;
8981 if (is_space_char (*op_string))
8982 ++op_string;
8983 i.types[this_operand].bitfield.jumpabsolute = 1;
8984 }
8985 goto do_memory_reference;
8986 }
8987
8988 /* Handle vector operations. */
8989 if (*op_string == '{')
8990 {
8991 op_string = check_VecOperations (op_string, NULL);
8992 if (op_string == NULL)
8993 return 0;
8994 }
8995
8996 if (*op_string)
8997 {
8998 as_bad (_("junk `%s' after register"), op_string);
8999 return 0;
9000 }
9001 temp = r->reg_type;
9002 temp.bitfield.baseindex = 0;
9003 i.types[this_operand] = operand_type_or (i.types[this_operand],
9004 temp);
9005 i.types[this_operand].bitfield.unspecified = 0;
9006 i.op[this_operand].regs = r;
9007 i.reg_operands++;
9008 }
9009 else if (*op_string == REGISTER_PREFIX)
9010 {
9011 as_bad (_("bad register name `%s'"), op_string);
9012 return 0;
9013 }
9014 else if (*op_string == IMMEDIATE_PREFIX)
9015 {
9016 ++op_string;
9017 if (i.types[this_operand].bitfield.jumpabsolute)
9018 {
9019 as_bad (_("immediate operand illegal with absolute jump"));
9020 return 0;
9021 }
9022 if (!i386_immediate (op_string))
9023 return 0;
9024 }
9025 else if (RC_SAE_immediate (operand_string))
9026 {
9027 /* If it is a RC or SAE immediate, do nothing. */
9028 ;
9029 }
9030 else if (is_digit_char (*op_string)
9031 || is_identifier_char (*op_string)
9032 || *op_string == '"'
9033 || *op_string == '(')
9034 {
9035 /* This is a memory reference of some sort. */
9036 char *base_string;
9037
9038 /* Start and end of displacement string expression (if found). */
9039 char *displacement_string_start;
9040 char *displacement_string_end;
9041 char *vop_start;
9042
9043 do_memory_reference:
9044 if (i.mem_operands == 1 && !maybe_adjust_templates ())
9045 return 0;
9046 if ((i.mem_operands == 1
9047 && !current_templates->start->opcode_modifier.isstring)
9048 || i.mem_operands == 2)
9049 {
9050 as_bad (_("too many memory references for `%s'"),
9051 current_templates->start->name);
9052 return 0;
9053 }
9054
9055 /* Check for base index form. We detect the base index form by
9056 looking for an ')' at the end of the operand, searching
9057 for the '(' matching it, and finding a REGISTER_PREFIX or ','
9058 after the '('. */
9059 base_string = op_string + strlen (op_string);
9060
9061 /* Handle vector operations. */
9062 vop_start = strchr (op_string, '{');
9063 if (vop_start && vop_start < base_string)
9064 {
9065 if (check_VecOperations (vop_start, base_string) == NULL)
9066 return 0;
9067 base_string = vop_start;
9068 }
9069
9070 --base_string;
9071 if (is_space_char (*base_string))
9072 --base_string;
9073
9074 /* If we only have a displacement, set-up for it to be parsed later. */
9075 displacement_string_start = op_string;
9076 displacement_string_end = base_string + 1;
9077
9078 if (*base_string == ')')
9079 {
9080 char *temp_string;
9081 unsigned int parens_balanced = 1;
9082 /* We've already checked that the number of left & right ()'s are
9083 equal, so this loop will not be infinite. */
9084 do
9085 {
9086 base_string--;
9087 if (*base_string == ')')
9088 parens_balanced++;
9089 if (*base_string == '(')
9090 parens_balanced--;
9091 }
9092 while (parens_balanced);
9093
9094 temp_string = base_string;
9095
9096 /* Skip past '(' and whitespace. */
9097 ++base_string;
9098 if (is_space_char (*base_string))
9099 ++base_string;
9100
9101 if (*base_string == ','
9102 || ((i.base_reg = parse_register (base_string, &end_op))
9103 != NULL))
9104 {
9105 displacement_string_end = temp_string;
9106
9107 i.types[this_operand].bitfield.baseindex = 1;
9108
9109 if (i.base_reg)
9110 {
9111 base_string = end_op;
9112 if (is_space_char (*base_string))
9113 ++base_string;
9114 }
9115
9116 /* There may be an index reg or scale factor here. */
9117 if (*base_string == ',')
9118 {
9119 ++base_string;
9120 if (is_space_char (*base_string))
9121 ++base_string;
9122
9123 if ((i.index_reg = parse_register (base_string, &end_op))
9124 != NULL)
9125 {
9126 base_string = end_op;
9127 if (is_space_char (*base_string))
9128 ++base_string;
9129 if (*base_string == ',')
9130 {
9131 ++base_string;
9132 if (is_space_char (*base_string))
9133 ++base_string;
9134 }
9135 else if (*base_string != ')')
9136 {
9137 as_bad (_("expecting `,' or `)' "
9138 "after index register in `%s'"),
9139 operand_string);
9140 return 0;
9141 }
9142 }
9143 else if (*base_string == REGISTER_PREFIX)
9144 {
9145 end_op = strchr (base_string, ',');
9146 if (end_op)
9147 *end_op = '\0';
9148 as_bad (_("bad register name `%s'"), base_string);
9149 return 0;
9150 }
9151
9152 /* Check for scale factor. */
9153 if (*base_string != ')')
9154 {
9155 char *end_scale = i386_scale (base_string);
9156
9157 if (!end_scale)
9158 return 0;
9159
9160 base_string = end_scale;
9161 if (is_space_char (*base_string))
9162 ++base_string;
9163 if (*base_string != ')')
9164 {
9165 as_bad (_("expecting `)' "
9166 "after scale factor in `%s'"),
9167 operand_string);
9168 return 0;
9169 }
9170 }
9171 else if (!i.index_reg)
9172 {
9173 as_bad (_("expecting index register or scale factor "
9174 "after `,'; got '%c'"),
9175 *base_string);
9176 return 0;
9177 }
9178 }
9179 else if (*base_string != ')')
9180 {
9181 as_bad (_("expecting `,' or `)' "
9182 "after base register in `%s'"),
9183 operand_string);
9184 return 0;
9185 }
9186 }
9187 else if (*base_string == REGISTER_PREFIX)
9188 {
9189 end_op = strchr (base_string, ',');
9190 if (end_op)
9191 *end_op = '\0';
9192 as_bad (_("bad register name `%s'"), base_string);
9193 return 0;
9194 }
9195 }
9196
9197 /* If there's an expression beginning the operand, parse it,
9198 assuming displacement_string_start and
9199 displacement_string_end are meaningful. */
9200 if (displacement_string_start != displacement_string_end)
9201 {
9202 if (!i386_displacement (displacement_string_start,
9203 displacement_string_end))
9204 return 0;
9205 }
9206
9207 /* Special case for (%dx) while doing input/output op. */
9208 if (i.base_reg
9209 && operand_type_equal (&i.base_reg->reg_type,
9210 &reg16_inoutportreg)
9211 && i.index_reg == 0
9212 && i.log2_scale_factor == 0
9213 && i.seg[i.mem_operands] == 0
9214 && !operand_type_check (i.types[this_operand], disp))
9215 {
9216 i.types[this_operand] = inoutportreg;
9217 return 1;
9218 }
9219
9220 if (i386_index_check (operand_string) == 0)
9221 return 0;
9222 i.types[this_operand].bitfield.mem = 1;
9223 if (i.mem_operands == 0)
9224 i.memop1_string = xstrdup (operand_string);
9225 i.mem_operands++;
9226 }
9227 else
9228 {
9229 /* It's not a memory operand; argh! */
9230 as_bad (_("invalid char %s beginning operand %d `%s'"),
9231 output_invalid (*op_string),
9232 this_operand + 1,
9233 op_string);
9234 return 0;
9235 }
9236 return 1; /* Normal return. */
9237 }
9238 \f
9239 /* Calculate the maximum variable size (i.e., excluding fr_fix)
9240 that an rs_machine_dependent frag may reach. */
9241
9242 unsigned int
9243 i386_frag_max_var (fragS *frag)
9244 {
9245 /* The only relaxable frags are for jumps.
9246 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
9247 gas_assert (frag->fr_type == rs_machine_dependent);
9248 return TYPE_FROM_RELAX_STATE (frag->fr_subtype) == UNCOND_JUMP ? 4 : 5;
9249 }
9250
9251 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9252 static int
9253 elf_symbol_resolved_in_segment_p (symbolS *fr_symbol, offsetT fr_var)
9254 {
9255 /* STT_GNU_IFUNC symbol must go through PLT. */
9256 if ((symbol_get_bfdsym (fr_symbol)->flags
9257 & BSF_GNU_INDIRECT_FUNCTION) != 0)
9258 return 0;
9259
9260 if (!S_IS_EXTERNAL (fr_symbol))
9261 /* Symbol may be weak or local. */
9262 return !S_IS_WEAK (fr_symbol);
9263
9264 /* Global symbols with non-default visibility can't be preempted. */
9265 if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol)) != STV_DEFAULT)
9266 return 1;
9267
9268 if (fr_var != NO_RELOC)
9269 switch ((enum bfd_reloc_code_real) fr_var)
9270 {
9271 case BFD_RELOC_386_PLT32:
9272 case BFD_RELOC_X86_64_PLT32:
9273 /* Symbol with PLT relocation may be preempted. */
9274 return 0;
9275 default:
9276 abort ();
9277 }
9278
9279 /* Global symbols with default visibility in a shared library may be
9280 preempted by another definition. */
9281 return !shared;
9282 }
9283 #endif
9284
9285 /* md_estimate_size_before_relax()
9286
9287 Called just before relax() for rs_machine_dependent frags. The x86
9288 assembler uses these frags to handle variable size jump
9289 instructions.
9290
9291 Any symbol that is now undefined will not become defined.
9292 Return the correct fr_subtype in the frag.
9293 Return the initial "guess for variable size of frag" to caller.
9294 The guess is actually the growth beyond the fixed part. Whatever
9295 we do to grow the fixed or variable part contributes to our
9296 returned value. */
9297
9298 int
9299 md_estimate_size_before_relax (fragS *fragP, segT segment)
9300 {
9301 /* We've already got fragP->fr_subtype right; all we have to do is
9302 check for un-relaxable symbols. On an ELF system, we can't relax
9303 an externally visible symbol, because it may be overridden by a
9304 shared library. */
9305 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
9306 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9307 || (IS_ELF
9308 && !elf_symbol_resolved_in_segment_p (fragP->fr_symbol,
9309 fragP->fr_var))
9310 #endif
9311 #if defined (OBJ_COFF) && defined (TE_PE)
9312 || (OUTPUT_FLAVOR == bfd_target_coff_flavour
9313 && S_IS_WEAK (fragP->fr_symbol))
9314 #endif
9315 )
9316 {
9317 /* Symbol is undefined in this segment, or we need to keep a
9318 reloc so that weak symbols can be overridden. */
9319 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
9320 enum bfd_reloc_code_real reloc_type;
9321 unsigned char *opcode;
9322 int old_fr_fix;
9323
9324 if (fragP->fr_var != NO_RELOC)
9325 reloc_type = (enum bfd_reloc_code_real) fragP->fr_var;
9326 else if (size == 2)
9327 reloc_type = BFD_RELOC_16_PCREL;
9328 else
9329 reloc_type = BFD_RELOC_32_PCREL;
9330
9331 old_fr_fix = fragP->fr_fix;
9332 opcode = (unsigned char *) fragP->fr_opcode;
9333
9334 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
9335 {
9336 case UNCOND_JUMP:
9337 /* Make jmp (0xeb) a (d)word displacement jump. */
9338 opcode[0] = 0xe9;
9339 fragP->fr_fix += size;
9340 fix_new (fragP, old_fr_fix, size,
9341 fragP->fr_symbol,
9342 fragP->fr_offset, 1,
9343 reloc_type);
9344 break;
9345
9346 case COND_JUMP86:
9347 if (size == 2
9348 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
9349 {
9350 /* Negate the condition, and branch past an
9351 unconditional jump. */
9352 opcode[0] ^= 1;
9353 opcode[1] = 3;
9354 /* Insert an unconditional jump. */
9355 opcode[2] = 0xe9;
9356 /* We added two extra opcode bytes, and have a two byte
9357 offset. */
9358 fragP->fr_fix += 2 + 2;
9359 fix_new (fragP, old_fr_fix + 2, 2,
9360 fragP->fr_symbol,
9361 fragP->fr_offset, 1,
9362 reloc_type);
9363 break;
9364 }
9365 /* Fall through. */
9366
9367 case COND_JUMP:
9368 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
9369 {
9370 fixS *fixP;
9371
9372 fragP->fr_fix += 1;
9373 fixP = fix_new (fragP, old_fr_fix, 1,
9374 fragP->fr_symbol,
9375 fragP->fr_offset, 1,
9376 BFD_RELOC_8_PCREL);
9377 fixP->fx_signed = 1;
9378 break;
9379 }
9380
9381 /* This changes the byte-displacement jump 0x7N
9382 to the (d)word-displacement jump 0x0f,0x8N. */
9383 opcode[1] = opcode[0] + 0x10;
9384 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
9385 /* We've added an opcode byte. */
9386 fragP->fr_fix += 1 + size;
9387 fix_new (fragP, old_fr_fix + 1, size,
9388 fragP->fr_symbol,
9389 fragP->fr_offset, 1,
9390 reloc_type);
9391 break;
9392
9393 default:
9394 BAD_CASE (fragP->fr_subtype);
9395 break;
9396 }
9397 frag_wane (fragP);
9398 return fragP->fr_fix - old_fr_fix;
9399 }
9400
9401 /* Guess size depending on current relax state. Initially the relax
9402 state will correspond to a short jump and we return 1, because
9403 the variable part of the frag (the branch offset) is one byte
9404 long. However, we can relax a section more than once and in that
9405 case we must either set fr_subtype back to the unrelaxed state,
9406 or return the value for the appropriate branch. */
9407 return md_relax_table[fragP->fr_subtype].rlx_length;
9408 }
9409
9410 /* Called after relax() is finished.
9411
9412 In: Address of frag.
9413 fr_type == rs_machine_dependent.
9414 fr_subtype is what the address relaxed to.
9415
9416 Out: Any fixSs and constants are set up.
9417 Caller will turn frag into a ".space 0". */
9418
9419 void
9420 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT sec ATTRIBUTE_UNUSED,
9421 fragS *fragP)
9422 {
9423 unsigned char *opcode;
9424 unsigned char *where_to_put_displacement = NULL;
9425 offsetT target_address;
9426 offsetT opcode_address;
9427 unsigned int extension = 0;
9428 offsetT displacement_from_opcode_start;
9429
9430 opcode = (unsigned char *) fragP->fr_opcode;
9431
9432 /* Address we want to reach in file space. */
9433 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
9434
9435 /* Address opcode resides at in file space. */
9436 opcode_address = fragP->fr_address + fragP->fr_fix;
9437
9438 /* Displacement from opcode start to fill into instruction. */
9439 displacement_from_opcode_start = target_address - opcode_address;
9440
9441 if ((fragP->fr_subtype & BIG) == 0)
9442 {
9443 /* Don't have to change opcode. */
9444 extension = 1; /* 1 opcode + 1 displacement */
9445 where_to_put_displacement = &opcode[1];
9446 }
9447 else
9448 {
9449 if (no_cond_jump_promotion
9450 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
9451 as_warn_where (fragP->fr_file, fragP->fr_line,
9452 _("long jump required"));
9453
9454 switch (fragP->fr_subtype)
9455 {
9456 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
9457 extension = 4; /* 1 opcode + 4 displacement */
9458 opcode[0] = 0xe9;
9459 where_to_put_displacement = &opcode[1];
9460 break;
9461
9462 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
9463 extension = 2; /* 1 opcode + 2 displacement */
9464 opcode[0] = 0xe9;
9465 where_to_put_displacement = &opcode[1];
9466 break;
9467
9468 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
9469 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
9470 extension = 5; /* 2 opcode + 4 displacement */
9471 opcode[1] = opcode[0] + 0x10;
9472 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
9473 where_to_put_displacement = &opcode[2];
9474 break;
9475
9476 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
9477 extension = 3; /* 2 opcode + 2 displacement */
9478 opcode[1] = opcode[0] + 0x10;
9479 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
9480 where_to_put_displacement = &opcode[2];
9481 break;
9482
9483 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
9484 extension = 4;
9485 opcode[0] ^= 1;
9486 opcode[1] = 3;
9487 opcode[2] = 0xe9;
9488 where_to_put_displacement = &opcode[3];
9489 break;
9490
9491 default:
9492 BAD_CASE (fragP->fr_subtype);
9493 break;
9494 }
9495 }
9496
9497 /* If size if less then four we are sure that the operand fits,
9498 but if it's 4, then it could be that the displacement is larger
9499 then -/+ 2GB. */
9500 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
9501 && object_64bit
9502 && ((addressT) (displacement_from_opcode_start - extension
9503 + ((addressT) 1 << 31))
9504 > (((addressT) 2 << 31) - 1)))
9505 {
9506 as_bad_where (fragP->fr_file, fragP->fr_line,
9507 _("jump target out of range"));
9508 /* Make us emit 0. */
9509 displacement_from_opcode_start = extension;
9510 }
9511 /* Now put displacement after opcode. */
9512 md_number_to_chars ((char *) where_to_put_displacement,
9513 (valueT) (displacement_from_opcode_start - extension),
9514 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
9515 fragP->fr_fix += extension;
9516 }
9517 \f
9518 /* Apply a fixup (fixP) to segment data, once it has been determined
9519 by our caller that we have all the info we need to fix it up.
9520
9521 Parameter valP is the pointer to the value of the bits.
9522
9523 On the 386, immediates, displacements, and data pointers are all in
9524 the same (little-endian) format, so we don't need to care about which
9525 we are handling. */
9526
9527 void
9528 md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
9529 {
9530 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
9531 valueT value = *valP;
9532
9533 #if !defined (TE_Mach)
9534 if (fixP->fx_pcrel)
9535 {
9536 switch (fixP->fx_r_type)
9537 {
9538 default:
9539 break;
9540
9541 case BFD_RELOC_64:
9542 fixP->fx_r_type = BFD_RELOC_64_PCREL;
9543 break;
9544 case BFD_RELOC_32:
9545 case BFD_RELOC_X86_64_32S:
9546 fixP->fx_r_type = BFD_RELOC_32_PCREL;
9547 break;
9548 case BFD_RELOC_16:
9549 fixP->fx_r_type = BFD_RELOC_16_PCREL;
9550 break;
9551 case BFD_RELOC_8:
9552 fixP->fx_r_type = BFD_RELOC_8_PCREL;
9553 break;
9554 }
9555 }
9556
9557 if (fixP->fx_addsy != NULL
9558 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
9559 || fixP->fx_r_type == BFD_RELOC_64_PCREL
9560 || fixP->fx_r_type == BFD_RELOC_16_PCREL
9561 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
9562 && !use_rela_relocations)
9563 {
9564 /* This is a hack. There should be a better way to handle this.
9565 This covers for the fact that bfd_install_relocation will
9566 subtract the current location (for partial_inplace, PC relative
9567 relocations); see more below. */
9568 #ifndef OBJ_AOUT
9569 if (IS_ELF
9570 #ifdef TE_PE
9571 || OUTPUT_FLAVOR == bfd_target_coff_flavour
9572 #endif
9573 )
9574 value += fixP->fx_where + fixP->fx_frag->fr_address;
9575 #endif
9576 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9577 if (IS_ELF)
9578 {
9579 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
9580
9581 if ((sym_seg == seg
9582 || (symbol_section_p (fixP->fx_addsy)
9583 && sym_seg != absolute_section))
9584 && !generic_force_reloc (fixP))
9585 {
9586 /* Yes, we add the values in twice. This is because
9587 bfd_install_relocation subtracts them out again. I think
9588 bfd_install_relocation is broken, but I don't dare change
9589 it. FIXME. */
9590 value += fixP->fx_where + fixP->fx_frag->fr_address;
9591 }
9592 }
9593 #endif
9594 #if defined (OBJ_COFF) && defined (TE_PE)
9595 /* For some reason, the PE format does not store a
9596 section address offset for a PC relative symbol. */
9597 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
9598 || S_IS_WEAK (fixP->fx_addsy))
9599 value += md_pcrel_from (fixP);
9600 #endif
9601 }
9602 #if defined (OBJ_COFF) && defined (TE_PE)
9603 if (fixP->fx_addsy != NULL
9604 && S_IS_WEAK (fixP->fx_addsy)
9605 /* PR 16858: Do not modify weak function references. */
9606 && ! fixP->fx_pcrel)
9607 {
9608 #if !defined (TE_PEP)
9609 /* For x86 PE weak function symbols are neither PC-relative
9610 nor do they set S_IS_FUNCTION. So the only reliable way
9611 to detect them is to check the flags of their containing
9612 section. */
9613 if (S_GET_SEGMENT (fixP->fx_addsy) != NULL
9614 && S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_CODE)
9615 ;
9616 else
9617 #endif
9618 value -= S_GET_VALUE (fixP->fx_addsy);
9619 }
9620 #endif
9621
9622 /* Fix a few things - the dynamic linker expects certain values here,
9623 and we must not disappoint it. */
9624 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9625 if (IS_ELF && fixP->fx_addsy)
9626 switch (fixP->fx_r_type)
9627 {
9628 case BFD_RELOC_386_PLT32:
9629 case BFD_RELOC_X86_64_PLT32:
9630 /* Make the jump instruction point to the address of the operand. At
9631 runtime we merely add the offset to the actual PLT entry. */
9632 value = -4;
9633 break;
9634
9635 case BFD_RELOC_386_TLS_GD:
9636 case BFD_RELOC_386_TLS_LDM:
9637 case BFD_RELOC_386_TLS_IE_32:
9638 case BFD_RELOC_386_TLS_IE:
9639 case BFD_RELOC_386_TLS_GOTIE:
9640 case BFD_RELOC_386_TLS_GOTDESC:
9641 case BFD_RELOC_X86_64_TLSGD:
9642 case BFD_RELOC_X86_64_TLSLD:
9643 case BFD_RELOC_X86_64_GOTTPOFF:
9644 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
9645 value = 0; /* Fully resolved at runtime. No addend. */
9646 /* Fallthrough */
9647 case BFD_RELOC_386_TLS_LE:
9648 case BFD_RELOC_386_TLS_LDO_32:
9649 case BFD_RELOC_386_TLS_LE_32:
9650 case BFD_RELOC_X86_64_DTPOFF32:
9651 case BFD_RELOC_X86_64_DTPOFF64:
9652 case BFD_RELOC_X86_64_TPOFF32:
9653 case BFD_RELOC_X86_64_TPOFF64:
9654 S_SET_THREAD_LOCAL (fixP->fx_addsy);
9655 break;
9656
9657 case BFD_RELOC_386_TLS_DESC_CALL:
9658 case BFD_RELOC_X86_64_TLSDESC_CALL:
9659 value = 0; /* Fully resolved at runtime. No addend. */
9660 S_SET_THREAD_LOCAL (fixP->fx_addsy);
9661 fixP->fx_done = 0;
9662 return;
9663
9664 case BFD_RELOC_VTABLE_INHERIT:
9665 case BFD_RELOC_VTABLE_ENTRY:
9666 fixP->fx_done = 0;
9667 return;
9668
9669 default:
9670 break;
9671 }
9672 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
9673 *valP = value;
9674 #endif /* !defined (TE_Mach) */
9675
9676 /* Are we finished with this relocation now? */
9677 if (fixP->fx_addsy == NULL)
9678 fixP->fx_done = 1;
9679 #if defined (OBJ_COFF) && defined (TE_PE)
9680 else if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy))
9681 {
9682 fixP->fx_done = 0;
9683 /* Remember value for tc_gen_reloc. */
9684 fixP->fx_addnumber = value;
9685 /* Clear out the frag for now. */
9686 value = 0;
9687 }
9688 #endif
9689 else if (use_rela_relocations)
9690 {
9691 fixP->fx_no_overflow = 1;
9692 /* Remember value for tc_gen_reloc. */
9693 fixP->fx_addnumber = value;
9694 value = 0;
9695 }
9696
9697 md_number_to_chars (p, value, fixP->fx_size);
9698 }
9699 \f
9700 const char *
9701 md_atof (int type, char *litP, int *sizeP)
9702 {
9703 /* This outputs the LITTLENUMs in REVERSE order;
9704 in accord with the bigendian 386. */
9705 return ieee_md_atof (type, litP, sizeP, FALSE);
9706 }
9707 \f
9708 static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
9709
9710 static char *
9711 output_invalid (int c)
9712 {
9713 if (ISPRINT (c))
9714 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
9715 "'%c'", c);
9716 else
9717 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
9718 "(0x%x)", (unsigned char) c);
9719 return output_invalid_buf;
9720 }
9721
9722 /* REG_STRING starts *before* REGISTER_PREFIX. */
9723
9724 static const reg_entry *
9725 parse_real_register (char *reg_string, char **end_op)
9726 {
9727 char *s = reg_string;
9728 char *p;
9729 char reg_name_given[MAX_REG_NAME_SIZE + 1];
9730 const reg_entry *r;
9731
9732 /* Skip possible REGISTER_PREFIX and possible whitespace. */
9733 if (*s == REGISTER_PREFIX)
9734 ++s;
9735
9736 if (is_space_char (*s))
9737 ++s;
9738
9739 p = reg_name_given;
9740 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
9741 {
9742 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
9743 return (const reg_entry *) NULL;
9744 s++;
9745 }
9746
9747 /* For naked regs, make sure that we are not dealing with an identifier.
9748 This prevents confusing an identifier like `eax_var' with register
9749 `eax'. */
9750 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
9751 return (const reg_entry *) NULL;
9752
9753 *end_op = s;
9754
9755 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
9756
9757 /* Handle floating point regs, allowing spaces in the (i) part. */
9758 if (r == i386_regtab /* %st is first entry of table */)
9759 {
9760 if (is_space_char (*s))
9761 ++s;
9762 if (*s == '(')
9763 {
9764 ++s;
9765 if (is_space_char (*s))
9766 ++s;
9767 if (*s >= '0' && *s <= '7')
9768 {
9769 int fpr = *s - '0';
9770 ++s;
9771 if (is_space_char (*s))
9772 ++s;
9773 if (*s == ')')
9774 {
9775 *end_op = s + 1;
9776 r = (const reg_entry *) hash_find (reg_hash, "st(0)");
9777 know (r);
9778 return r + fpr;
9779 }
9780 }
9781 /* We have "%st(" then garbage. */
9782 return (const reg_entry *) NULL;
9783 }
9784 }
9785
9786 if (r == NULL || allow_pseudo_reg)
9787 return r;
9788
9789 if (operand_type_all_zero (&r->reg_type))
9790 return (const reg_entry *) NULL;
9791
9792 if ((r->reg_type.bitfield.reg32
9793 || r->reg_type.bitfield.sreg3
9794 || r->reg_type.bitfield.control
9795 || r->reg_type.bitfield.debug
9796 || r->reg_type.bitfield.test)
9797 && !cpu_arch_flags.bitfield.cpui386)
9798 return (const reg_entry *) NULL;
9799
9800 if (r->reg_type.bitfield.floatreg
9801 && !cpu_arch_flags.bitfield.cpu8087
9802 && !cpu_arch_flags.bitfield.cpu287
9803 && !cpu_arch_flags.bitfield.cpu387)
9804 return (const reg_entry *) NULL;
9805
9806 if (r->reg_type.bitfield.regmmx && !cpu_arch_flags.bitfield.cpuregmmx)
9807 return (const reg_entry *) NULL;
9808
9809 if (r->reg_type.bitfield.regxmm && !cpu_arch_flags.bitfield.cpuregxmm)
9810 return (const reg_entry *) NULL;
9811
9812 if (r->reg_type.bitfield.regymm && !cpu_arch_flags.bitfield.cpuregymm)
9813 return (const reg_entry *) NULL;
9814
9815 if (r->reg_type.bitfield.regzmm && !cpu_arch_flags.bitfield.cpuregzmm)
9816 return (const reg_entry *) NULL;
9817
9818 if (r->reg_type.bitfield.regmask
9819 && !cpu_arch_flags.bitfield.cpuregmask)
9820 return (const reg_entry *) NULL;
9821
9822 /* Don't allow fake index register unless allow_index_reg isn't 0. */
9823 if (!allow_index_reg
9824 && (r->reg_num == RegEiz || r->reg_num == RegRiz))
9825 return (const reg_entry *) NULL;
9826
9827 /* Upper 16 vector register is only available with VREX in 64bit
9828 mode. */
9829 if ((r->reg_flags & RegVRex))
9830 {
9831 if (i.vec_encoding == vex_encoding_default)
9832 i.vec_encoding = vex_encoding_evex;
9833
9834 if (!cpu_arch_flags.bitfield.cpuvrex
9835 || i.vec_encoding != vex_encoding_evex
9836 || flag_code != CODE_64BIT)
9837 return (const reg_entry *) NULL;
9838 }
9839
9840 if (((r->reg_flags & (RegRex64 | RegRex))
9841 || r->reg_type.bitfield.reg64)
9842 && (!cpu_arch_flags.bitfield.cpulm
9843 || !operand_type_equal (&r->reg_type, &control))
9844 && flag_code != CODE_64BIT)
9845 return (const reg_entry *) NULL;
9846
9847 if (r->reg_type.bitfield.sreg3 && r->reg_num == RegFlat && !intel_syntax)
9848 return (const reg_entry *) NULL;
9849
9850 return r;
9851 }
9852
9853 /* REG_STRING starts *before* REGISTER_PREFIX. */
9854
9855 static const reg_entry *
9856 parse_register (char *reg_string, char **end_op)
9857 {
9858 const reg_entry *r;
9859
9860 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
9861 r = parse_real_register (reg_string, end_op);
9862 else
9863 r = NULL;
9864 if (!r)
9865 {
9866 char *save = input_line_pointer;
9867 char c;
9868 symbolS *symbolP;
9869
9870 input_line_pointer = reg_string;
9871 c = get_symbol_name (&reg_string);
9872 symbolP = symbol_find (reg_string);
9873 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
9874 {
9875 const expressionS *e = symbol_get_value_expression (symbolP);
9876
9877 know (e->X_op == O_register);
9878 know (e->X_add_number >= 0
9879 && (valueT) e->X_add_number < i386_regtab_size);
9880 r = i386_regtab + e->X_add_number;
9881 if ((r->reg_flags & RegVRex))
9882 i.vec_encoding = vex_encoding_evex;
9883 *end_op = input_line_pointer;
9884 }
9885 *input_line_pointer = c;
9886 input_line_pointer = save;
9887 }
9888 return r;
9889 }
9890
9891 int
9892 i386_parse_name (char *name, expressionS *e, char *nextcharP)
9893 {
9894 const reg_entry *r;
9895 char *end = input_line_pointer;
9896
9897 *end = *nextcharP;
9898 r = parse_register (name, &input_line_pointer);
9899 if (r && end <= input_line_pointer)
9900 {
9901 *nextcharP = *input_line_pointer;
9902 *input_line_pointer = 0;
9903 e->X_op = O_register;
9904 e->X_add_number = r - i386_regtab;
9905 return 1;
9906 }
9907 input_line_pointer = end;
9908 *end = 0;
9909 return intel_syntax ? i386_intel_parse_name (name, e) : 0;
9910 }
9911
9912 void
9913 md_operand (expressionS *e)
9914 {
9915 char *end;
9916 const reg_entry *r;
9917
9918 switch (*input_line_pointer)
9919 {
9920 case REGISTER_PREFIX:
9921 r = parse_real_register (input_line_pointer, &end);
9922 if (r)
9923 {
9924 e->X_op = O_register;
9925 e->X_add_number = r - i386_regtab;
9926 input_line_pointer = end;
9927 }
9928 break;
9929
9930 case '[':
9931 gas_assert (intel_syntax);
9932 end = input_line_pointer++;
9933 expression (e);
9934 if (*input_line_pointer == ']')
9935 {
9936 ++input_line_pointer;
9937 e->X_op_symbol = make_expr_symbol (e);
9938 e->X_add_symbol = NULL;
9939 e->X_add_number = 0;
9940 e->X_op = O_index;
9941 }
9942 else
9943 {
9944 e->X_op = O_absent;
9945 input_line_pointer = end;
9946 }
9947 break;
9948 }
9949 }
9950
9951 \f
9952 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9953 const char *md_shortopts = "kVQ:sqn";
9954 #else
9955 const char *md_shortopts = "qn";
9956 #endif
9957
9958 #define OPTION_32 (OPTION_MD_BASE + 0)
9959 #define OPTION_64 (OPTION_MD_BASE + 1)
9960 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
9961 #define OPTION_MARCH (OPTION_MD_BASE + 3)
9962 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
9963 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
9964 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
9965 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
9966 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
9967 #define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
9968 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
9969 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
9970 #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
9971 #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
9972 #define OPTION_X32 (OPTION_MD_BASE + 14)
9973 #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
9974 #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
9975 #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
9976 #define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
9977 #define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
9978 #define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
9979 #define OPTION_MSHARED (OPTION_MD_BASE + 21)
9980 #define OPTION_MAMD64 (OPTION_MD_BASE + 22)
9981 #define OPTION_MINTEL64 (OPTION_MD_BASE + 23)
9982 #define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24)
9983 #define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 25)
9984
9985 struct option md_longopts[] =
9986 {
9987 {"32", no_argument, NULL, OPTION_32},
9988 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
9989 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
9990 {"64", no_argument, NULL, OPTION_64},
9991 #endif
9992 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9993 {"x32", no_argument, NULL, OPTION_X32},
9994 {"mshared", no_argument, NULL, OPTION_MSHARED},
9995 #endif
9996 {"divide", no_argument, NULL, OPTION_DIVIDE},
9997 {"march", required_argument, NULL, OPTION_MARCH},
9998 {"mtune", required_argument, NULL, OPTION_MTUNE},
9999 {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC},
10000 {"msyntax", required_argument, NULL, OPTION_MSYNTAX},
10001 {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG},
10002 {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG},
10003 {"mold-gcc", no_argument, NULL, OPTION_MOLD_GCC},
10004 {"msse2avx", no_argument, NULL, OPTION_MSSE2AVX},
10005 {"msse-check", required_argument, NULL, OPTION_MSSE_CHECK},
10006 {"moperand-check", required_argument, NULL, OPTION_MOPERAND_CHECK},
10007 {"mavxscalar", required_argument, NULL, OPTION_MAVXSCALAR},
10008 {"madd-bnd-prefix", no_argument, NULL, OPTION_MADD_BND_PREFIX},
10009 {"mevexlig", required_argument, NULL, OPTION_MEVEXLIG},
10010 {"mevexwig", required_argument, NULL, OPTION_MEVEXWIG},
10011 # if defined (TE_PE) || defined (TE_PEP)
10012 {"mbig-obj", no_argument, NULL, OPTION_MBIG_OBJ},
10013 #endif
10014 {"momit-lock-prefix", required_argument, NULL, OPTION_MOMIT_LOCK_PREFIX},
10015 {"mfence-as-lock-add", required_argument, NULL, OPTION_MFENCE_AS_LOCK_ADD},
10016 {"mrelax-relocations", required_argument, NULL, OPTION_MRELAX_RELOCATIONS},
10017 {"mevexrcig", required_argument, NULL, OPTION_MEVEXRCIG},
10018 {"mamd64", no_argument, NULL, OPTION_MAMD64},
10019 {"mintel64", no_argument, NULL, OPTION_MINTEL64},
10020 {NULL, no_argument, NULL, 0}
10021 };
10022 size_t md_longopts_size = sizeof (md_longopts);
10023
10024 int
10025 md_parse_option (int c, const char *arg)
10026 {
10027 unsigned int j;
10028 char *arch, *next, *saved;
10029
10030 switch (c)
10031 {
10032 case 'n':
10033 optimize_align_code = 0;
10034 break;
10035
10036 case 'q':
10037 quiet_warnings = 1;
10038 break;
10039
10040 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10041 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
10042 should be emitted or not. FIXME: Not implemented. */
10043 case 'Q':
10044 break;
10045
10046 /* -V: SVR4 argument to print version ID. */
10047 case 'V':
10048 print_version_id ();
10049 break;
10050
10051 /* -k: Ignore for FreeBSD compatibility. */
10052 case 'k':
10053 break;
10054
10055 case 's':
10056 /* -s: On i386 Solaris, this tells the native assembler to use
10057 .stab instead of .stab.excl. We always use .stab anyhow. */
10058 break;
10059
10060 case OPTION_MSHARED:
10061 shared = 1;
10062 break;
10063 #endif
10064 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10065 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
10066 case OPTION_64:
10067 {
10068 const char **list, **l;
10069
10070 list = bfd_target_list ();
10071 for (l = list; *l != NULL; l++)
10072 if (CONST_STRNEQ (*l, "elf64-x86-64")
10073 || strcmp (*l, "coff-x86-64") == 0
10074 || strcmp (*l, "pe-x86-64") == 0
10075 || strcmp (*l, "pei-x86-64") == 0
10076 || strcmp (*l, "mach-o-x86-64") == 0)
10077 {
10078 default_arch = "x86_64";
10079 break;
10080 }
10081 if (*l == NULL)
10082 as_fatal (_("no compiled in support for x86_64"));
10083 free (list);
10084 }
10085 break;
10086 #endif
10087
10088 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10089 case OPTION_X32:
10090 if (IS_ELF)
10091 {
10092 const char **list, **l;
10093
10094 list = bfd_target_list ();
10095 for (l = list; *l != NULL; l++)
10096 if (CONST_STRNEQ (*l, "elf32-x86-64"))
10097 {
10098 default_arch = "x86_64:32";
10099 break;
10100 }
10101 if (*l == NULL)
10102 as_fatal (_("no compiled in support for 32bit x86_64"));
10103 free (list);
10104 }
10105 else
10106 as_fatal (_("32bit x86_64 is only supported for ELF"));
10107 break;
10108 #endif
10109
10110 case OPTION_32:
10111 default_arch = "i386";
10112 break;
10113
10114 case OPTION_DIVIDE:
10115 #ifdef SVR4_COMMENT_CHARS
10116 {
10117 char *n, *t;
10118 const char *s;
10119
10120 n = XNEWVEC (char, strlen (i386_comment_chars) + 1);
10121 t = n;
10122 for (s = i386_comment_chars; *s != '\0'; s++)
10123 if (*s != '/')
10124 *t++ = *s;
10125 *t = '\0';
10126 i386_comment_chars = n;
10127 }
10128 #endif
10129 break;
10130
10131 case OPTION_MARCH:
10132 saved = xstrdup (arg);
10133 arch = saved;
10134 /* Allow -march=+nosse. */
10135 if (*arch == '+')
10136 arch++;
10137 do
10138 {
10139 if (*arch == '.')
10140 as_fatal (_("invalid -march= option: `%s'"), arg);
10141 next = strchr (arch, '+');
10142 if (next)
10143 *next++ = '\0';
10144 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
10145 {
10146 if (strcmp (arch, cpu_arch [j].name) == 0)
10147 {
10148 /* Processor. */
10149 if (! cpu_arch[j].flags.bitfield.cpui386)
10150 continue;
10151
10152 cpu_arch_name = cpu_arch[j].name;
10153 cpu_sub_arch_name = NULL;
10154 cpu_arch_flags = cpu_arch[j].flags;
10155 cpu_arch_isa = cpu_arch[j].type;
10156 cpu_arch_isa_flags = cpu_arch[j].flags;
10157 if (!cpu_arch_tune_set)
10158 {
10159 cpu_arch_tune = cpu_arch_isa;
10160 cpu_arch_tune_flags = cpu_arch_isa_flags;
10161 }
10162 break;
10163 }
10164 else if (*cpu_arch [j].name == '.'
10165 && strcmp (arch, cpu_arch [j].name + 1) == 0)
10166 {
10167 /* ISA extension. */
10168 i386_cpu_flags flags;
10169
10170 flags = cpu_flags_or (cpu_arch_flags,
10171 cpu_arch[j].flags);
10172
10173 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
10174 {
10175 if (cpu_sub_arch_name)
10176 {
10177 char *name = cpu_sub_arch_name;
10178 cpu_sub_arch_name = concat (name,
10179 cpu_arch[j].name,
10180 (const char *) NULL);
10181 free (name);
10182 }
10183 else
10184 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
10185 cpu_arch_flags = flags;
10186 cpu_arch_isa_flags = flags;
10187 }
10188 break;
10189 }
10190 }
10191
10192 if (j >= ARRAY_SIZE (cpu_arch))
10193 {
10194 /* Disable an ISA extension. */
10195 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
10196 if (strcmp (arch, cpu_noarch [j].name) == 0)
10197 {
10198 i386_cpu_flags flags;
10199
10200 flags = cpu_flags_and_not (cpu_arch_flags,
10201 cpu_noarch[j].flags);
10202 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
10203 {
10204 if (cpu_sub_arch_name)
10205 {
10206 char *name = cpu_sub_arch_name;
10207 cpu_sub_arch_name = concat (arch,
10208 (const char *) NULL);
10209 free (name);
10210 }
10211 else
10212 cpu_sub_arch_name = xstrdup (arch);
10213 cpu_arch_flags = flags;
10214 cpu_arch_isa_flags = flags;
10215 }
10216 break;
10217 }
10218
10219 if (j >= ARRAY_SIZE (cpu_noarch))
10220 j = ARRAY_SIZE (cpu_arch);
10221 }
10222
10223 if (j >= ARRAY_SIZE (cpu_arch))
10224 as_fatal (_("invalid -march= option: `%s'"), arg);
10225
10226 arch = next;
10227 }
10228 while (next != NULL);
10229 free (saved);
10230 break;
10231
10232 case OPTION_MTUNE:
10233 if (*arg == '.')
10234 as_fatal (_("invalid -mtune= option: `%s'"), arg);
10235 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
10236 {
10237 if (strcmp (arg, cpu_arch [j].name) == 0)
10238 {
10239 cpu_arch_tune_set = 1;
10240 cpu_arch_tune = cpu_arch [j].type;
10241 cpu_arch_tune_flags = cpu_arch[j].flags;
10242 break;
10243 }
10244 }
10245 if (j >= ARRAY_SIZE (cpu_arch))
10246 as_fatal (_("invalid -mtune= option: `%s'"), arg);
10247 break;
10248
10249 case OPTION_MMNEMONIC:
10250 if (strcasecmp (arg, "att") == 0)
10251 intel_mnemonic = 0;
10252 else if (strcasecmp (arg, "intel") == 0)
10253 intel_mnemonic = 1;
10254 else
10255 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg);
10256 break;
10257
10258 case OPTION_MSYNTAX:
10259 if (strcasecmp (arg, "att") == 0)
10260 intel_syntax = 0;
10261 else if (strcasecmp (arg, "intel") == 0)
10262 intel_syntax = 1;
10263 else
10264 as_fatal (_("invalid -msyntax= option: `%s'"), arg);
10265 break;
10266
10267 case OPTION_MINDEX_REG:
10268 allow_index_reg = 1;
10269 break;
10270
10271 case OPTION_MNAKED_REG:
10272 allow_naked_reg = 1;
10273 break;
10274
10275 case OPTION_MOLD_GCC:
10276 old_gcc = 1;
10277 break;
10278
10279 case OPTION_MSSE2AVX:
10280 sse2avx = 1;
10281 break;
10282
10283 case OPTION_MSSE_CHECK:
10284 if (strcasecmp (arg, "error") == 0)
10285 sse_check = check_error;
10286 else if (strcasecmp (arg, "warning") == 0)
10287 sse_check = check_warning;
10288 else if (strcasecmp (arg, "none") == 0)
10289 sse_check = check_none;
10290 else
10291 as_fatal (_("invalid -msse-check= option: `%s'"), arg);
10292 break;
10293
10294 case OPTION_MOPERAND_CHECK:
10295 if (strcasecmp (arg, "error") == 0)
10296 operand_check = check_error;
10297 else if (strcasecmp (arg, "warning") == 0)
10298 operand_check = check_warning;
10299 else if (strcasecmp (arg, "none") == 0)
10300 operand_check = check_none;
10301 else
10302 as_fatal (_("invalid -moperand-check= option: `%s'"), arg);
10303 break;
10304
10305 case OPTION_MAVXSCALAR:
10306 if (strcasecmp (arg, "128") == 0)
10307 avxscalar = vex128;
10308 else if (strcasecmp (arg, "256") == 0)
10309 avxscalar = vex256;
10310 else
10311 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg);
10312 break;
10313
10314 case OPTION_MADD_BND_PREFIX:
10315 add_bnd_prefix = 1;
10316 break;
10317
10318 case OPTION_MEVEXLIG:
10319 if (strcmp (arg, "128") == 0)
10320 evexlig = evexl128;
10321 else if (strcmp (arg, "256") == 0)
10322 evexlig = evexl256;
10323 else if (strcmp (arg, "512") == 0)
10324 evexlig = evexl512;
10325 else
10326 as_fatal (_("invalid -mevexlig= option: `%s'"), arg);
10327 break;
10328
10329 case OPTION_MEVEXRCIG:
10330 if (strcmp (arg, "rne") == 0)
10331 evexrcig = rne;
10332 else if (strcmp (arg, "rd") == 0)
10333 evexrcig = rd;
10334 else if (strcmp (arg, "ru") == 0)
10335 evexrcig = ru;
10336 else if (strcmp (arg, "rz") == 0)
10337 evexrcig = rz;
10338 else
10339 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg);
10340 break;
10341
10342 case OPTION_MEVEXWIG:
10343 if (strcmp (arg, "0") == 0)
10344 evexwig = evexw0;
10345 else if (strcmp (arg, "1") == 0)
10346 evexwig = evexw1;
10347 else
10348 as_fatal (_("invalid -mevexwig= option: `%s'"), arg);
10349 break;
10350
10351 # if defined (TE_PE) || defined (TE_PEP)
10352 case OPTION_MBIG_OBJ:
10353 use_big_obj = 1;
10354 break;
10355 #endif
10356
10357 case OPTION_MOMIT_LOCK_PREFIX:
10358 if (strcasecmp (arg, "yes") == 0)
10359 omit_lock_prefix = 1;
10360 else if (strcasecmp (arg, "no") == 0)
10361 omit_lock_prefix = 0;
10362 else
10363 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg);
10364 break;
10365
10366 case OPTION_MFENCE_AS_LOCK_ADD:
10367 if (strcasecmp (arg, "yes") == 0)
10368 avoid_fence = 1;
10369 else if (strcasecmp (arg, "no") == 0)
10370 avoid_fence = 0;
10371 else
10372 as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg);
10373 break;
10374
10375 case OPTION_MRELAX_RELOCATIONS:
10376 if (strcasecmp (arg, "yes") == 0)
10377 generate_relax_relocations = 1;
10378 else if (strcasecmp (arg, "no") == 0)
10379 generate_relax_relocations = 0;
10380 else
10381 as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg);
10382 break;
10383
10384 case OPTION_MAMD64:
10385 intel64 = 0;
10386 break;
10387
10388 case OPTION_MINTEL64:
10389 intel64 = 1;
10390 break;
10391
10392 default:
10393 return 0;
10394 }
10395 return 1;
10396 }
10397
10398 #define MESSAGE_TEMPLATE \
10399 " "
10400
10401 static char *
10402 output_message (FILE *stream, char *p, char *message, char *start,
10403 int *left_p, const char *name, int len)
10404 {
10405 int size = sizeof (MESSAGE_TEMPLATE);
10406 int left = *left_p;
10407
10408 /* Reserve 2 spaces for ", " or ",\0" */
10409 left -= len + 2;
10410
10411 /* Check if there is any room. */
10412 if (left >= 0)
10413 {
10414 if (p != start)
10415 {
10416 *p++ = ',';
10417 *p++ = ' ';
10418 }
10419 p = mempcpy (p, name, len);
10420 }
10421 else
10422 {
10423 /* Output the current message now and start a new one. */
10424 *p++ = ',';
10425 *p = '\0';
10426 fprintf (stream, "%s\n", message);
10427 p = start;
10428 left = size - (start - message) - len - 2;
10429
10430 gas_assert (left >= 0);
10431
10432 p = mempcpy (p, name, len);
10433 }
10434
10435 *left_p = left;
10436 return p;
10437 }
10438
10439 static void
10440 show_arch (FILE *stream, int ext, int check)
10441 {
10442 static char message[] = MESSAGE_TEMPLATE;
10443 char *start = message + 27;
10444 char *p;
10445 int size = sizeof (MESSAGE_TEMPLATE);
10446 int left;
10447 const char *name;
10448 int len;
10449 unsigned int j;
10450
10451 p = start;
10452 left = size - (start - message);
10453 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
10454 {
10455 /* Should it be skipped? */
10456 if (cpu_arch [j].skip)
10457 continue;
10458
10459 name = cpu_arch [j].name;
10460 len = cpu_arch [j].len;
10461 if (*name == '.')
10462 {
10463 /* It is an extension. Skip if we aren't asked to show it. */
10464 if (ext)
10465 {
10466 name++;
10467 len--;
10468 }
10469 else
10470 continue;
10471 }
10472 else if (ext)
10473 {
10474 /* It is an processor. Skip if we show only extension. */
10475 continue;
10476 }
10477 else if (check && ! cpu_arch[j].flags.bitfield.cpui386)
10478 {
10479 /* It is an impossible processor - skip. */
10480 continue;
10481 }
10482
10483 p = output_message (stream, p, message, start, &left, name, len);
10484 }
10485
10486 /* Display disabled extensions. */
10487 if (ext)
10488 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
10489 {
10490 name = cpu_noarch [j].name;
10491 len = cpu_noarch [j].len;
10492 p = output_message (stream, p, message, start, &left, name,
10493 len);
10494 }
10495
10496 *p = '\0';
10497 fprintf (stream, "%s\n", message);
10498 }
10499
10500 void
10501 md_show_usage (FILE *stream)
10502 {
10503 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10504 fprintf (stream, _("\
10505 -Q ignored\n\
10506 -V print assembler version number\n\
10507 -k ignored\n"));
10508 #endif
10509 fprintf (stream, _("\
10510 -n Do not optimize code alignment\n\
10511 -q quieten some warnings\n"));
10512 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10513 fprintf (stream, _("\
10514 -s ignored\n"));
10515 #endif
10516 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10517 || defined (TE_PE) || defined (TE_PEP))
10518 fprintf (stream, _("\
10519 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
10520 #endif
10521 #ifdef SVR4_COMMENT_CHARS
10522 fprintf (stream, _("\
10523 --divide do not treat `/' as a comment character\n"));
10524 #else
10525 fprintf (stream, _("\
10526 --divide ignored\n"));
10527 #endif
10528 fprintf (stream, _("\
10529 -march=CPU[,+EXTENSION...]\n\
10530 generate code for CPU and EXTENSION, CPU is one of:\n"));
10531 show_arch (stream, 0, 1);
10532 fprintf (stream, _("\
10533 EXTENSION is combination of:\n"));
10534 show_arch (stream, 1, 0);
10535 fprintf (stream, _("\
10536 -mtune=CPU optimize for CPU, CPU is one of:\n"));
10537 show_arch (stream, 0, 0);
10538 fprintf (stream, _("\
10539 -msse2avx encode SSE instructions with VEX prefix\n"));
10540 fprintf (stream, _("\
10541 -msse-check=[none|error|warning]\n\
10542 check SSE instructions\n"));
10543 fprintf (stream, _("\
10544 -moperand-check=[none|error|warning]\n\
10545 check operand combinations for validity\n"));
10546 fprintf (stream, _("\
10547 -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n\
10548 length\n"));
10549 fprintf (stream, _("\
10550 -mevexlig=[128|256|512] encode scalar EVEX instructions with specific vector\n\
10551 length\n"));
10552 fprintf (stream, _("\
10553 -mevexwig=[0|1] encode EVEX instructions with specific EVEX.W value\n\
10554 for EVEX.W bit ignored instructions\n"));
10555 fprintf (stream, _("\
10556 -mevexrcig=[rne|rd|ru|rz]\n\
10557 encode EVEX instructions with specific EVEX.RC value\n\
10558 for SAE-only ignored instructions\n"));
10559 fprintf (stream, _("\
10560 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
10561 fprintf (stream, _("\
10562 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
10563 fprintf (stream, _("\
10564 -mindex-reg support pseudo index registers\n"));
10565 fprintf (stream, _("\
10566 -mnaked-reg don't require `%%' prefix for registers\n"));
10567 fprintf (stream, _("\
10568 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
10569 fprintf (stream, _("\
10570 -madd-bnd-prefix add BND prefix for all valid branches\n"));
10571 fprintf (stream, _("\
10572 -mshared disable branch optimization for shared code\n"));
10573 # if defined (TE_PE) || defined (TE_PEP)
10574 fprintf (stream, _("\
10575 -mbig-obj generate big object files\n"));
10576 #endif
10577 fprintf (stream, _("\
10578 -momit-lock-prefix=[no|yes]\n\
10579 strip all lock prefixes\n"));
10580 fprintf (stream, _("\
10581 -mfence-as-lock-add=[no|yes]\n\
10582 encode lfence, mfence and sfence as\n\
10583 lock addl $0x0, (%%{re}sp)\n"));
10584 fprintf (stream, _("\
10585 -mrelax-relocations=[no|yes]\n\
10586 generate relax relocations\n"));
10587 fprintf (stream, _("\
10588 -mamd64 accept only AMD64 ISA\n"));
10589 fprintf (stream, _("\
10590 -mintel64 accept only Intel64 ISA\n"));
10591 }
10592
10593 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
10594 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10595 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
10596
10597 /* Pick the target format to use. */
10598
10599 const char *
10600 i386_target_format (void)
10601 {
10602 if (!strncmp (default_arch, "x86_64", 6))
10603 {
10604 update_code_flag (CODE_64BIT, 1);
10605 if (default_arch[6] == '\0')
10606 x86_elf_abi = X86_64_ABI;
10607 else
10608 x86_elf_abi = X86_64_X32_ABI;
10609 }
10610 else if (!strcmp (default_arch, "i386"))
10611 update_code_flag (CODE_32BIT, 1);
10612 else if (!strcmp (default_arch, "iamcu"))
10613 {
10614 update_code_flag (CODE_32BIT, 1);
10615 if (cpu_arch_isa == PROCESSOR_UNKNOWN)
10616 {
10617 static const i386_cpu_flags iamcu_flags = CPU_IAMCU_FLAGS;
10618 cpu_arch_name = "iamcu";
10619 cpu_sub_arch_name = NULL;
10620 cpu_arch_flags = iamcu_flags;
10621 cpu_arch_isa = PROCESSOR_IAMCU;
10622 cpu_arch_isa_flags = iamcu_flags;
10623 if (!cpu_arch_tune_set)
10624 {
10625 cpu_arch_tune = cpu_arch_isa;
10626 cpu_arch_tune_flags = cpu_arch_isa_flags;
10627 }
10628 }
10629 else if (cpu_arch_isa != PROCESSOR_IAMCU)
10630 as_fatal (_("Intel MCU doesn't support `%s' architecture"),
10631 cpu_arch_name);
10632 }
10633 else
10634 as_fatal (_("unknown architecture"));
10635
10636 if (cpu_flags_all_zero (&cpu_arch_isa_flags))
10637 cpu_arch_isa_flags = cpu_arch[flag_code == CODE_64BIT].flags;
10638 if (cpu_flags_all_zero (&cpu_arch_tune_flags))
10639 cpu_arch_tune_flags = cpu_arch[flag_code == CODE_64BIT].flags;
10640
10641 switch (OUTPUT_FLAVOR)
10642 {
10643 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
10644 case bfd_target_aout_flavour:
10645 return AOUT_TARGET_FORMAT;
10646 #endif
10647 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
10648 # if defined (TE_PE) || defined (TE_PEP)
10649 case bfd_target_coff_flavour:
10650 if (flag_code == CODE_64BIT)
10651 return use_big_obj ? "pe-bigobj-x86-64" : "pe-x86-64";
10652 else
10653 return "pe-i386";
10654 # elif defined (TE_GO32)
10655 case bfd_target_coff_flavour:
10656 return "coff-go32";
10657 # else
10658 case bfd_target_coff_flavour:
10659 return "coff-i386";
10660 # endif
10661 #endif
10662 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
10663 case bfd_target_elf_flavour:
10664 {
10665 const char *format;
10666
10667 switch (x86_elf_abi)
10668 {
10669 default:
10670 format = ELF_TARGET_FORMAT;
10671 break;
10672 case X86_64_ABI:
10673 use_rela_relocations = 1;
10674 object_64bit = 1;
10675 format = ELF_TARGET_FORMAT64;
10676 break;
10677 case X86_64_X32_ABI:
10678 use_rela_relocations = 1;
10679 object_64bit = 1;
10680 disallow_64bit_reloc = 1;
10681 format = ELF_TARGET_FORMAT32;
10682 break;
10683 }
10684 if (cpu_arch_isa == PROCESSOR_L1OM)
10685 {
10686 if (x86_elf_abi != X86_64_ABI)
10687 as_fatal (_("Intel L1OM is 64bit only"));
10688 return ELF_TARGET_L1OM_FORMAT;
10689 }
10690 else if (cpu_arch_isa == PROCESSOR_K1OM)
10691 {
10692 if (x86_elf_abi != X86_64_ABI)
10693 as_fatal (_("Intel K1OM is 64bit only"));
10694 return ELF_TARGET_K1OM_FORMAT;
10695 }
10696 else if (cpu_arch_isa == PROCESSOR_IAMCU)
10697 {
10698 if (x86_elf_abi != I386_ABI)
10699 as_fatal (_("Intel MCU is 32bit only"));
10700 return ELF_TARGET_IAMCU_FORMAT;
10701 }
10702 else
10703 return format;
10704 }
10705 #endif
10706 #if defined (OBJ_MACH_O)
10707 case bfd_target_mach_o_flavour:
10708 if (flag_code == CODE_64BIT)
10709 {
10710 use_rela_relocations = 1;
10711 object_64bit = 1;
10712 return "mach-o-x86-64";
10713 }
10714 else
10715 return "mach-o-i386";
10716 #endif
10717 default:
10718 abort ();
10719 return NULL;
10720 }
10721 }
10722
10723 #endif /* OBJ_MAYBE_ more than one */
10724 \f
10725 symbolS *
10726 md_undefined_symbol (char *name)
10727 {
10728 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
10729 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
10730 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
10731 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
10732 {
10733 if (!GOT_symbol)
10734 {
10735 if (symbol_find (name))
10736 as_bad (_("GOT already in symbol table"));
10737 GOT_symbol = symbol_new (name, undefined_section,
10738 (valueT) 0, &zero_address_frag);
10739 };
10740 return GOT_symbol;
10741 }
10742 return 0;
10743 }
10744
10745 /* Round up a section size to the appropriate boundary. */
10746
10747 valueT
10748 md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size)
10749 {
10750 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
10751 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
10752 {
10753 /* For a.out, force the section size to be aligned. If we don't do
10754 this, BFD will align it for us, but it will not write out the
10755 final bytes of the section. This may be a bug in BFD, but it is
10756 easier to fix it here since that is how the other a.out targets
10757 work. */
10758 int align;
10759
10760 align = bfd_get_section_alignment (stdoutput, segment);
10761 size = ((size + (1 << align) - 1) & (-((valueT) 1 << align)));
10762 }
10763 #endif
10764
10765 return size;
10766 }
10767
10768 /* On the i386, PC-relative offsets are relative to the start of the
10769 next instruction. That is, the address of the offset, plus its
10770 size, since the offset is always the last part of the insn. */
10771
10772 long
10773 md_pcrel_from (fixS *fixP)
10774 {
10775 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
10776 }
10777
10778 #ifndef I386COFF
10779
10780 static void
10781 s_bss (int ignore ATTRIBUTE_UNUSED)
10782 {
10783 int temp;
10784
10785 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10786 if (IS_ELF)
10787 obj_elf_section_change_hook ();
10788 #endif
10789 temp = get_absolute_expression ();
10790 subseg_set (bss_section, (subsegT) temp);
10791 demand_empty_rest_of_line ();
10792 }
10793
10794 #endif
10795
10796 void
10797 i386_validate_fix (fixS *fixp)
10798 {
10799 if (fixp->fx_subsy)
10800 {
10801 if (fixp->fx_subsy == GOT_symbol)
10802 {
10803 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
10804 {
10805 if (!object_64bit)
10806 abort ();
10807 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10808 if (fixp->fx_tcbit2)
10809 fixp->fx_r_type = (fixp->fx_tcbit
10810 ? BFD_RELOC_X86_64_REX_GOTPCRELX
10811 : BFD_RELOC_X86_64_GOTPCRELX);
10812 else
10813 #endif
10814 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
10815 }
10816 else
10817 {
10818 if (!object_64bit)
10819 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
10820 else
10821 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
10822 }
10823 fixp->fx_subsy = 0;
10824 }
10825 }
10826 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10827 else if (!object_64bit)
10828 {
10829 if (fixp->fx_r_type == BFD_RELOC_386_GOT32
10830 && fixp->fx_tcbit2)
10831 fixp->fx_r_type = BFD_RELOC_386_GOT32X;
10832 }
10833 #endif
10834 }
10835
10836 arelent *
10837 tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
10838 {
10839 arelent *rel;
10840 bfd_reloc_code_real_type code;
10841
10842 switch (fixp->fx_r_type)
10843 {
10844 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10845 case BFD_RELOC_SIZE32:
10846 case BFD_RELOC_SIZE64:
10847 if (S_IS_DEFINED (fixp->fx_addsy)
10848 && !S_IS_EXTERNAL (fixp->fx_addsy))
10849 {
10850 /* Resolve size relocation against local symbol to size of
10851 the symbol plus addend. */
10852 valueT value = S_GET_SIZE (fixp->fx_addsy) + fixp->fx_offset;
10853 if (fixp->fx_r_type == BFD_RELOC_SIZE32
10854 && !fits_in_unsigned_long (value))
10855 as_bad_where (fixp->fx_file, fixp->fx_line,
10856 _("symbol size computation overflow"));
10857 fixp->fx_addsy = NULL;
10858 fixp->fx_subsy = NULL;
10859 md_apply_fix (fixp, (valueT *) &value, NULL);
10860 return NULL;
10861 }
10862 #endif
10863 /* Fall through. */
10864
10865 case BFD_RELOC_X86_64_PLT32:
10866 case BFD_RELOC_X86_64_GOT32:
10867 case BFD_RELOC_X86_64_GOTPCREL:
10868 case BFD_RELOC_X86_64_GOTPCRELX:
10869 case BFD_RELOC_X86_64_REX_GOTPCRELX:
10870 case BFD_RELOC_386_PLT32:
10871 case BFD_RELOC_386_GOT32:
10872 case BFD_RELOC_386_GOT32X:
10873 case BFD_RELOC_386_GOTOFF:
10874 case BFD_RELOC_386_GOTPC:
10875 case BFD_RELOC_386_TLS_GD:
10876 case BFD_RELOC_386_TLS_LDM:
10877 case BFD_RELOC_386_TLS_LDO_32:
10878 case BFD_RELOC_386_TLS_IE_32:
10879 case BFD_RELOC_386_TLS_IE:
10880 case BFD_RELOC_386_TLS_GOTIE:
10881 case BFD_RELOC_386_TLS_LE_32:
10882 case BFD_RELOC_386_TLS_LE:
10883 case BFD_RELOC_386_TLS_GOTDESC:
10884 case BFD_RELOC_386_TLS_DESC_CALL:
10885 case BFD_RELOC_X86_64_TLSGD:
10886 case BFD_RELOC_X86_64_TLSLD:
10887 case BFD_RELOC_X86_64_DTPOFF32:
10888 case BFD_RELOC_X86_64_DTPOFF64:
10889 case BFD_RELOC_X86_64_GOTTPOFF:
10890 case BFD_RELOC_X86_64_TPOFF32:
10891 case BFD_RELOC_X86_64_TPOFF64:
10892 case BFD_RELOC_X86_64_GOTOFF64:
10893 case BFD_RELOC_X86_64_GOTPC32:
10894 case BFD_RELOC_X86_64_GOT64:
10895 case BFD_RELOC_X86_64_GOTPCREL64:
10896 case BFD_RELOC_X86_64_GOTPC64:
10897 case BFD_RELOC_X86_64_GOTPLT64:
10898 case BFD_RELOC_X86_64_PLTOFF64:
10899 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
10900 case BFD_RELOC_X86_64_TLSDESC_CALL:
10901 case BFD_RELOC_RVA:
10902 case BFD_RELOC_VTABLE_ENTRY:
10903 case BFD_RELOC_VTABLE_INHERIT:
10904 #ifdef TE_PE
10905 case BFD_RELOC_32_SECREL:
10906 #endif
10907 code = fixp->fx_r_type;
10908 break;
10909 case BFD_RELOC_X86_64_32S:
10910 if (!fixp->fx_pcrel)
10911 {
10912 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
10913 code = fixp->fx_r_type;
10914 break;
10915 }
10916 /* Fall through. */
10917 default:
10918 if (fixp->fx_pcrel)
10919 {
10920 switch (fixp->fx_size)
10921 {
10922 default:
10923 as_bad_where (fixp->fx_file, fixp->fx_line,
10924 _("can not do %d byte pc-relative relocation"),
10925 fixp->fx_size);
10926 code = BFD_RELOC_32_PCREL;
10927 break;
10928 case 1: code = BFD_RELOC_8_PCREL; break;
10929 case 2: code = BFD_RELOC_16_PCREL; break;
10930 case 4: code = BFD_RELOC_32_PCREL; break;
10931 #ifdef BFD64
10932 case 8: code = BFD_RELOC_64_PCREL; break;
10933 #endif
10934 }
10935 }
10936 else
10937 {
10938 switch (fixp->fx_size)
10939 {
10940 default:
10941 as_bad_where (fixp->fx_file, fixp->fx_line,
10942 _("can not do %d byte relocation"),
10943 fixp->fx_size);
10944 code = BFD_RELOC_32;
10945 break;
10946 case 1: code = BFD_RELOC_8; break;
10947 case 2: code = BFD_RELOC_16; break;
10948 case 4: code = BFD_RELOC_32; break;
10949 #ifdef BFD64
10950 case 8: code = BFD_RELOC_64; break;
10951 #endif
10952 }
10953 }
10954 break;
10955 }
10956
10957 if ((code == BFD_RELOC_32
10958 || code == BFD_RELOC_32_PCREL
10959 || code == BFD_RELOC_X86_64_32S)
10960 && GOT_symbol
10961 && fixp->fx_addsy == GOT_symbol)
10962 {
10963 if (!object_64bit)
10964 code = BFD_RELOC_386_GOTPC;
10965 else
10966 code = BFD_RELOC_X86_64_GOTPC32;
10967 }
10968 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
10969 && GOT_symbol
10970 && fixp->fx_addsy == GOT_symbol)
10971 {
10972 code = BFD_RELOC_X86_64_GOTPC64;
10973 }
10974
10975 rel = XNEW (arelent);
10976 rel->sym_ptr_ptr = XNEW (asymbol *);
10977 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
10978
10979 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
10980
10981 if (!use_rela_relocations)
10982 {
10983 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
10984 vtable entry to be used in the relocation's section offset. */
10985 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
10986 rel->address = fixp->fx_offset;
10987 #if defined (OBJ_COFF) && defined (TE_PE)
10988 else if (fixp->fx_addsy && S_IS_WEAK (fixp->fx_addsy))
10989 rel->addend = fixp->fx_addnumber - (S_GET_VALUE (fixp->fx_addsy) * 2);
10990 else
10991 #endif
10992 rel->addend = 0;
10993 }
10994 /* Use the rela in 64bit mode. */
10995 else
10996 {
10997 if (disallow_64bit_reloc)
10998 switch (code)
10999 {
11000 case BFD_RELOC_X86_64_DTPOFF64:
11001 case BFD_RELOC_X86_64_TPOFF64:
11002 case BFD_RELOC_64_PCREL:
11003 case BFD_RELOC_X86_64_GOTOFF64:
11004 case BFD_RELOC_X86_64_GOT64:
11005 case BFD_RELOC_X86_64_GOTPCREL64:
11006 case BFD_RELOC_X86_64_GOTPC64:
11007 case BFD_RELOC_X86_64_GOTPLT64:
11008 case BFD_RELOC_X86_64_PLTOFF64:
11009 as_bad_where (fixp->fx_file, fixp->fx_line,
11010 _("cannot represent relocation type %s in x32 mode"),
11011 bfd_get_reloc_code_name (code));
11012 break;
11013 default:
11014 break;
11015 }
11016
11017 if (!fixp->fx_pcrel)
11018 rel->addend = fixp->fx_offset;
11019 else
11020 switch (code)
11021 {
11022 case BFD_RELOC_X86_64_PLT32:
11023 case BFD_RELOC_X86_64_GOT32:
11024 case BFD_RELOC_X86_64_GOTPCREL:
11025 case BFD_RELOC_X86_64_GOTPCRELX:
11026 case BFD_RELOC_X86_64_REX_GOTPCRELX:
11027 case BFD_RELOC_X86_64_TLSGD:
11028 case BFD_RELOC_X86_64_TLSLD:
11029 case BFD_RELOC_X86_64_GOTTPOFF:
11030 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
11031 case BFD_RELOC_X86_64_TLSDESC_CALL:
11032 rel->addend = fixp->fx_offset - fixp->fx_size;
11033 break;
11034 default:
11035 rel->addend = (section->vma
11036 - fixp->fx_size
11037 + fixp->fx_addnumber
11038 + md_pcrel_from (fixp));
11039 break;
11040 }
11041 }
11042
11043 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
11044 if (rel->howto == NULL)
11045 {
11046 as_bad_where (fixp->fx_file, fixp->fx_line,
11047 _("cannot represent relocation type %s"),
11048 bfd_get_reloc_code_name (code));
11049 /* Set howto to a garbage value so that we can keep going. */
11050 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
11051 gas_assert (rel->howto != NULL);
11052 }
11053
11054 return rel;
11055 }
11056
11057 #include "tc-i386-intel.c"
11058
11059 void
11060 tc_x86_parse_to_dw2regnum (expressionS *exp)
11061 {
11062 int saved_naked_reg;
11063 char saved_register_dot;
11064
11065 saved_naked_reg = allow_naked_reg;
11066 allow_naked_reg = 1;
11067 saved_register_dot = register_chars['.'];
11068 register_chars['.'] = '.';
11069 allow_pseudo_reg = 1;
11070 expression_and_evaluate (exp);
11071 allow_pseudo_reg = 0;
11072 register_chars['.'] = saved_register_dot;
11073 allow_naked_reg = saved_naked_reg;
11074
11075 if (exp->X_op == O_register && exp->X_add_number >= 0)
11076 {
11077 if ((addressT) exp->X_add_number < i386_regtab_size)
11078 {
11079 exp->X_op = O_constant;
11080 exp->X_add_number = i386_regtab[exp->X_add_number]
11081 .dw2_regnum[flag_code >> 1];
11082 }
11083 else
11084 exp->X_op = O_illegal;
11085 }
11086 }
11087
11088 void
11089 tc_x86_frame_initial_instructions (void)
11090 {
11091 static unsigned int sp_regno[2];
11092
11093 if (!sp_regno[flag_code >> 1])
11094 {
11095 char *saved_input = input_line_pointer;
11096 char sp[][4] = {"esp", "rsp"};
11097 expressionS exp;
11098
11099 input_line_pointer = sp[flag_code >> 1];
11100 tc_x86_parse_to_dw2regnum (&exp);
11101 gas_assert (exp.X_op == O_constant);
11102 sp_regno[flag_code >> 1] = exp.X_add_number;
11103 input_line_pointer = saved_input;
11104 }
11105
11106 cfi_add_CFA_def_cfa (sp_regno[flag_code >> 1], -x86_cie_data_alignment);
11107 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
11108 }
11109
11110 int
11111 x86_dwarf2_addr_size (void)
11112 {
11113 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
11114 if (x86_elf_abi == X86_64_X32_ABI)
11115 return 4;
11116 #endif
11117 return bfd_arch_bits_per_address (stdoutput) / 8;
11118 }
11119
11120 int
11121 i386_elf_section_type (const char *str, size_t len)
11122 {
11123 if (flag_code == CODE_64BIT
11124 && len == sizeof ("unwind") - 1
11125 && strncmp (str, "unwind", 6) == 0)
11126 return SHT_X86_64_UNWIND;
11127
11128 return -1;
11129 }
11130
11131 #ifdef TE_SOLARIS
11132 void
11133 i386_solaris_fix_up_eh_frame (segT sec)
11134 {
11135 if (flag_code == CODE_64BIT)
11136 elf_section_type (sec) = SHT_X86_64_UNWIND;
11137 }
11138 #endif
11139
11140 #ifdef TE_PE
11141 void
11142 tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
11143 {
11144 expressionS exp;
11145
11146 exp.X_op = O_secrel;
11147 exp.X_add_symbol = symbol;
11148 exp.X_add_number = 0;
11149 emit_expr (&exp, size);
11150 }
11151 #endif
11152
11153 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11154 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
11155
11156 bfd_vma
11157 x86_64_section_letter (int letter, const char **ptr_msg)
11158 {
11159 if (flag_code == CODE_64BIT)
11160 {
11161 if (letter == 'l')
11162 return SHF_X86_64_LARGE;
11163
11164 *ptr_msg = _("bad .section directive: want a,l,w,x,M,S,G,T in string");
11165 }
11166 else
11167 *ptr_msg = _("bad .section directive: want a,w,x,M,S,G,T in string");
11168 return -1;
11169 }
11170
11171 bfd_vma
11172 x86_64_section_word (char *str, size_t len)
11173 {
11174 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
11175 return SHF_X86_64_LARGE;
11176
11177 return -1;
11178 }
11179
11180 static void
11181 handle_large_common (int small ATTRIBUTE_UNUSED)
11182 {
11183 if (flag_code != CODE_64BIT)
11184 {
11185 s_comm_internal (0, elf_common_parse);
11186 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
11187 }
11188 else
11189 {
11190 static segT lbss_section;
11191 asection *saved_com_section_ptr = elf_com_section_ptr;
11192 asection *saved_bss_section = bss_section;
11193
11194 if (lbss_section == NULL)
11195 {
11196 flagword applicable;
11197 segT seg = now_seg;
11198 subsegT subseg = now_subseg;
11199
11200 /* The .lbss section is for local .largecomm symbols. */
11201 lbss_section = subseg_new (".lbss", 0);
11202 applicable = bfd_applicable_section_flags (stdoutput);
11203 bfd_set_section_flags (stdoutput, lbss_section,
11204 applicable & SEC_ALLOC);
11205 seg_info (lbss_section)->bss = 1;
11206
11207 subseg_set (seg, subseg);
11208 }
11209
11210 elf_com_section_ptr = &_bfd_elf_large_com_section;
11211 bss_section = lbss_section;
11212
11213 s_comm_internal (0, elf_common_parse);
11214
11215 elf_com_section_ptr = saved_com_section_ptr;
11216 bss_section = saved_bss_section;
11217 }
11218 }
11219 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
GDB Binutils - Deliverables
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