Patch by matz@suse.de:
[deliverable/binutils-gdb.git] / gas / config / tc-i386.c
1 /* i386.c -- Assemble code for the Intel 80386
2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005, 2006
4 Free Software Foundation, Inc.
5
6 This file is part of GAS, the GNU Assembler.
7
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
11 any later version.
12
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 02110-1301, USA. */
22
23 /* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
25 x86_64 support by Jan Hubicka (jh@suse.cz)
26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
27 Bugs & suggestions are completely welcome. This is free software.
28 Please help us make it better. */
29
30 #include "as.h"
31 #include "safe-ctype.h"
32 #include "subsegs.h"
33 #include "dwarf2dbg.h"
34 #include "dw2gencfi.h"
35 #include "opcode/i386.h"
36 #include "elf/x86-64.h"
37
38 #ifndef REGISTER_WARNINGS
39 #define REGISTER_WARNINGS 1
40 #endif
41
42 #ifndef INFER_ADDR_PREFIX
43 #define INFER_ADDR_PREFIX 1
44 #endif
45
46 #ifndef SCALE1_WHEN_NO_INDEX
47 /* Specifying a scale factor besides 1 when there is no index is
48 futile. eg. `mov (%ebx,2),%al' does exactly the same as
49 `mov (%ebx),%al'. To slavishly follow what the programmer
50 specified, set SCALE1_WHEN_NO_INDEX to 0. */
51 #define SCALE1_WHEN_NO_INDEX 1
52 #endif
53
54 #ifndef DEFAULT_ARCH
55 #define DEFAULT_ARCH "i386"
56 #endif
57
58 #ifndef INLINE
59 #if __GNUC__ >= 2
60 #define INLINE __inline__
61 #else
62 #define INLINE
63 #endif
64 #endif
65
66 static INLINE unsigned int mode_from_disp_size PARAMS ((unsigned int));
67 static INLINE int fits_in_signed_byte PARAMS ((offsetT));
68 static INLINE int fits_in_unsigned_byte PARAMS ((offsetT));
69 static INLINE int fits_in_unsigned_word PARAMS ((offsetT));
70 static INLINE int fits_in_signed_word PARAMS ((offsetT));
71 static INLINE int fits_in_unsigned_long PARAMS ((offsetT));
72 static INLINE int fits_in_signed_long PARAMS ((offsetT));
73 static int smallest_imm_type PARAMS ((offsetT));
74 static offsetT offset_in_range PARAMS ((offsetT, int));
75 static int add_prefix PARAMS ((unsigned int));
76 static void set_code_flag PARAMS ((int));
77 static void set_16bit_gcc_code_flag PARAMS ((int));
78 static void set_intel_syntax PARAMS ((int));
79 static void set_cpu_arch PARAMS ((int));
80 #ifdef TE_PE
81 static void pe_directive_secrel PARAMS ((int));
82 #endif
83 static void signed_cons PARAMS ((int));
84 static char *output_invalid PARAMS ((int c));
85 static int i386_operand PARAMS ((char *operand_string));
86 static int i386_intel_operand PARAMS ((char *operand_string, int got_a_float));
87 static const reg_entry *parse_register PARAMS ((char *reg_string,
88 char **end_op));
89 static char *parse_insn PARAMS ((char *, char *));
90 static char *parse_operands PARAMS ((char *, const char *));
91 static void swap_operands PARAMS ((void));
92 static void optimize_imm PARAMS ((void));
93 static void optimize_disp PARAMS ((void));
94 static int match_template PARAMS ((void));
95 static int check_string PARAMS ((void));
96 static int process_suffix PARAMS ((void));
97 static int check_byte_reg PARAMS ((void));
98 static int check_long_reg PARAMS ((void));
99 static int check_qword_reg PARAMS ((void));
100 static int check_word_reg PARAMS ((void));
101 static int finalize_imm PARAMS ((void));
102 static int process_operands PARAMS ((void));
103 static const seg_entry *build_modrm_byte PARAMS ((void));
104 static void output_insn PARAMS ((void));
105 static void output_branch PARAMS ((void));
106 static void output_jump PARAMS ((void));
107 static void output_interseg_jump PARAMS ((void));
108 static void output_imm PARAMS ((fragS *insn_start_frag,
109 offsetT insn_start_off));
110 static void output_disp PARAMS ((fragS *insn_start_frag,
111 offsetT insn_start_off));
112 #ifndef I386COFF
113 static void s_bss PARAMS ((int));
114 #endif
115 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
116 static void handle_large_common (int small ATTRIBUTE_UNUSED);
117 #endif
118
119 static const char *default_arch = DEFAULT_ARCH;
120
121 /* 'md_assemble ()' gathers together information and puts it into a
122 i386_insn. */
123
124 union i386_op
125 {
126 expressionS *disps;
127 expressionS *imms;
128 const reg_entry *regs;
129 };
130
131 struct _i386_insn
132 {
133 /* TM holds the template for the insn were currently assembling. */
134 template tm;
135
136 /* SUFFIX holds the instruction mnemonic suffix if given.
137 (e.g. 'l' for 'movl') */
138 char suffix;
139
140 /* OPERANDS gives the number of given operands. */
141 unsigned int operands;
142
143 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
144 of given register, displacement, memory operands and immediate
145 operands. */
146 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
147
148 /* TYPES [i] is the type (see above #defines) which tells us how to
149 use OP[i] for the corresponding operand. */
150 unsigned int types[MAX_OPERANDS];
151
152 /* Displacement expression, immediate expression, or register for each
153 operand. */
154 union i386_op op[MAX_OPERANDS];
155
156 /* Flags for operands. */
157 unsigned int flags[MAX_OPERANDS];
158 #define Operand_PCrel 1
159
160 /* Relocation type for operand */
161 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
162
163 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
164 the base index byte below. */
165 const reg_entry *base_reg;
166 const reg_entry *index_reg;
167 unsigned int log2_scale_factor;
168
169 /* SEG gives the seg_entries of this insn. They are zero unless
170 explicit segment overrides are given. */
171 const seg_entry *seg[2];
172
173 /* PREFIX holds all the given prefix opcodes (usually null).
174 PREFIXES is the number of prefix opcodes. */
175 unsigned int prefixes;
176 unsigned char prefix[MAX_PREFIXES];
177
178 /* RM and SIB are the modrm byte and the sib byte where the
179 addressing modes of this insn are encoded. */
180
181 modrm_byte rm;
182 rex_byte rex;
183 sib_byte sib;
184 };
185
186 typedef struct _i386_insn i386_insn;
187
188 /* List of chars besides those in app.c:symbol_chars that can start an
189 operand. Used to prevent the scrubber eating vital white-space. */
190 const char extra_symbol_chars[] = "*%-(["
191 #ifdef LEX_AT
192 "@"
193 #endif
194 #ifdef LEX_QM
195 "?"
196 #endif
197 ;
198
199 #if (defined (TE_I386AIX) \
200 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
201 && !defined (TE_GNU) \
202 && !defined (TE_LINUX) \
203 && !defined (TE_NETWARE) \
204 && !defined (TE_FreeBSD) \
205 && !defined (TE_NetBSD)))
206 /* This array holds the chars that always start a comment. If the
207 pre-processor is disabled, these aren't very useful. The option
208 --divide will remove '/' from this list. */
209 const char *i386_comment_chars = "#/";
210 #define SVR4_COMMENT_CHARS 1
211 #define PREFIX_SEPARATOR '\\'
212
213 #else
214 const char *i386_comment_chars = "#";
215 #define PREFIX_SEPARATOR '/'
216 #endif
217
218 /* This array holds the chars that only start a comment at the beginning of
219 a line. If the line seems to have the form '# 123 filename'
220 .line and .file directives will appear in the pre-processed output.
221 Note that input_file.c hand checks for '#' at the beginning of the
222 first line of the input file. This is because the compiler outputs
223 #NO_APP at the beginning of its output.
224 Also note that comments started like this one will always work if
225 '/' isn't otherwise defined. */
226 const char line_comment_chars[] = "#/";
227
228 const char line_separator_chars[] = ";";
229
230 /* Chars that can be used to separate mant from exp in floating point
231 nums. */
232 const char EXP_CHARS[] = "eE";
233
234 /* Chars that mean this number is a floating point constant
235 As in 0f12.456
236 or 0d1.2345e12. */
237 const char FLT_CHARS[] = "fFdDxX";
238
239 /* Tables for lexical analysis. */
240 static char mnemonic_chars[256];
241 static char register_chars[256];
242 static char operand_chars[256];
243 static char identifier_chars[256];
244 static char digit_chars[256];
245
246 /* Lexical macros. */
247 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
248 #define is_operand_char(x) (operand_chars[(unsigned char) x])
249 #define is_register_char(x) (register_chars[(unsigned char) x])
250 #define is_space_char(x) ((x) == ' ')
251 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
252 #define is_digit_char(x) (digit_chars[(unsigned char) x])
253
254 /* All non-digit non-letter characters that may occur in an operand. */
255 static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
256
257 /* md_assemble() always leaves the strings it's passed unaltered. To
258 effect this we maintain a stack of saved characters that we've smashed
259 with '\0's (indicating end of strings for various sub-fields of the
260 assembler instruction). */
261 static char save_stack[32];
262 static char *save_stack_p;
263 #define END_STRING_AND_SAVE(s) \
264 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
265 #define RESTORE_END_STRING(s) \
266 do { *(s) = *--save_stack_p; } while (0)
267
268 /* The instruction we're assembling. */
269 static i386_insn i;
270
271 /* Possible templates for current insn. */
272 static const templates *current_templates;
273
274 /* Per instruction expressionS buffers: 2 displacements & 2 immediate max. */
275 static expressionS disp_expressions[2], im_expressions[2];
276
277 /* Current operand we are working on. */
278 static int this_operand;
279
280 /* We support four different modes. FLAG_CODE variable is used to distinguish
281 these. */
282
283 enum flag_code {
284 CODE_32BIT,
285 CODE_16BIT,
286 CODE_64BIT };
287 #define NUM_FLAG_CODE ((int) CODE_64BIT + 1)
288
289 static enum flag_code flag_code;
290 static unsigned int object_64bit;
291 static int use_rela_relocations = 0;
292
293 /* The names used to print error messages. */
294 static const char *flag_code_names[] =
295 {
296 "32",
297 "16",
298 "64"
299 };
300
301 /* 1 for intel syntax,
302 0 if att syntax. */
303 static int intel_syntax = 0;
304
305 /* 1 if register prefix % not required. */
306 static int allow_naked_reg = 0;
307
308 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
309 leave, push, and pop instructions so that gcc has the same stack
310 frame as in 32 bit mode. */
311 static char stackop_size = '\0';
312
313 /* Non-zero to optimize code alignment. */
314 int optimize_align_code = 1;
315
316 /* Non-zero to quieten some warnings. */
317 static int quiet_warnings = 0;
318
319 /* CPU name. */
320 static const char *cpu_arch_name = NULL;
321 static const char *cpu_sub_arch_name = NULL;
322
323 /* CPU feature flags. */
324 static unsigned int cpu_arch_flags = CpuUnknownFlags | CpuNo64;
325
326 /* If set, conditional jumps are not automatically promoted to handle
327 larger than a byte offset. */
328 static unsigned int no_cond_jump_promotion = 0;
329
330 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
331 static symbolS *GOT_symbol;
332
333 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
334 unsigned int x86_dwarf2_return_column;
335
336 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
337 int x86_cie_data_alignment;
338
339 /* Interface to relax_segment.
340 There are 3 major relax states for 386 jump insns because the
341 different types of jumps add different sizes to frags when we're
342 figuring out what sort of jump to choose to reach a given label. */
343
344 /* Types. */
345 #define UNCOND_JUMP 0
346 #define COND_JUMP 1
347 #define COND_JUMP86 2
348
349 /* Sizes. */
350 #define CODE16 1
351 #define SMALL 0
352 #define SMALL16 (SMALL | CODE16)
353 #define BIG 2
354 #define BIG16 (BIG | CODE16)
355
356 #ifndef INLINE
357 #ifdef __GNUC__
358 #define INLINE __inline__
359 #else
360 #define INLINE
361 #endif
362 #endif
363
364 #define ENCODE_RELAX_STATE(type, size) \
365 ((relax_substateT) (((type) << 2) | (size)))
366 #define TYPE_FROM_RELAX_STATE(s) \
367 ((s) >> 2)
368 #define DISP_SIZE_FROM_RELAX_STATE(s) \
369 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
370
371 /* This table is used by relax_frag to promote short jumps to long
372 ones where necessary. SMALL (short) jumps may be promoted to BIG
373 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
374 don't allow a short jump in a 32 bit code segment to be promoted to
375 a 16 bit offset jump because it's slower (requires data size
376 prefix), and doesn't work, unless the destination is in the bottom
377 64k of the code segment (The top 16 bits of eip are zeroed). */
378
379 const relax_typeS md_relax_table[] =
380 {
381 /* The fields are:
382 1) most positive reach of this state,
383 2) most negative reach of this state,
384 3) how many bytes this mode will have in the variable part of the frag
385 4) which index into the table to try if we can't fit into this one. */
386
387 /* UNCOND_JUMP states. */
388 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
389 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
390 /* dword jmp adds 4 bytes to frag:
391 0 extra opcode bytes, 4 displacement bytes. */
392 {0, 0, 4, 0},
393 /* word jmp adds 2 byte2 to frag:
394 0 extra opcode bytes, 2 displacement bytes. */
395 {0, 0, 2, 0},
396
397 /* COND_JUMP states. */
398 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
399 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
400 /* dword conditionals adds 5 bytes to frag:
401 1 extra opcode byte, 4 displacement bytes. */
402 {0, 0, 5, 0},
403 /* word conditionals add 3 bytes to frag:
404 1 extra opcode byte, 2 displacement bytes. */
405 {0, 0, 3, 0},
406
407 /* COND_JUMP86 states. */
408 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
409 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
410 /* dword conditionals adds 5 bytes to frag:
411 1 extra opcode byte, 4 displacement bytes. */
412 {0, 0, 5, 0},
413 /* word conditionals add 4 bytes to frag:
414 1 displacement byte and a 3 byte long branch insn. */
415 {0, 0, 4, 0}
416 };
417
418 static const arch_entry cpu_arch[] = {
419 {"i8086", Cpu086 },
420 {"i186", Cpu086|Cpu186 },
421 {"i286", Cpu086|Cpu186|Cpu286 },
422 {"i386", Cpu086|Cpu186|Cpu286|Cpu386 },
423 {"i486", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486 },
424 {"i586", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586 },
425 {"i686", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686 },
426 {"pentium", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586 },
427 {"pentiumpro",Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686 },
428 {"pentiumii", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX },
429 {"pentiumiii",Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX|CpuMMX2|CpuSSE },
430 {"pentium4", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX|CpuMMX2|CpuSSE|CpuSSE2 },
431 {"prescott", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuPNI },
432 {"k6", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuK6|CpuMMX },
433 {"k6_2", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuK6|CpuMMX|Cpu3dnow },
434 {"athlon", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuAthlon|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA },
435 {"sledgehammer",Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuAthlon|CpuSledgehammer|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2 },
436 {"opteron", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuAthlon|CpuSledgehammer|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2 },
437 {".mmx", CpuMMX },
438 {".sse", CpuMMX|CpuMMX2|CpuSSE },
439 {".sse2", CpuMMX|CpuMMX2|CpuSSE|CpuSSE2 },
440 {".sse3", CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3 },
441 {".3dnow", CpuMMX|Cpu3dnow },
442 {".3dnowa", CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA },
443 {".padlock", CpuPadLock },
444 {".pacifica", CpuSVME },
445 {".svme", CpuSVME },
446 {NULL, 0 }
447 };
448
449 const pseudo_typeS md_pseudo_table[] =
450 {
451 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
452 {"align", s_align_bytes, 0},
453 #else
454 {"align", s_align_ptwo, 0},
455 #endif
456 {"arch", set_cpu_arch, 0},
457 #ifndef I386COFF
458 {"bss", s_bss, 0},
459 #endif
460 {"ffloat", float_cons, 'f'},
461 {"dfloat", float_cons, 'd'},
462 {"tfloat", float_cons, 'x'},
463 {"value", cons, 2},
464 {"slong", signed_cons, 4},
465 {"noopt", s_ignore, 0},
466 {"optim", s_ignore, 0},
467 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
468 {"code16", set_code_flag, CODE_16BIT},
469 {"code32", set_code_flag, CODE_32BIT},
470 {"code64", set_code_flag, CODE_64BIT},
471 {"intel_syntax", set_intel_syntax, 1},
472 {"att_syntax", set_intel_syntax, 0},
473 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
474 {"largecomm", handle_large_common, 0},
475 #else
476 {"file", (void (*) PARAMS ((int))) dwarf2_directive_file, 0},
477 {"loc", dwarf2_directive_loc, 0},
478 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
479 #endif
480 #ifdef TE_PE
481 {"secrel32", pe_directive_secrel, 0},
482 #endif
483 {0, 0, 0}
484 };
485
486 /* For interface with expression (). */
487 extern char *input_line_pointer;
488
489 /* Hash table for instruction mnemonic lookup. */
490 static struct hash_control *op_hash;
491
492 /* Hash table for register lookup. */
493 static struct hash_control *reg_hash;
494 \f
495 void
496 i386_align_code (fragP, count)
497 fragS *fragP;
498 int count;
499 {
500 /* Various efficient no-op patterns for aligning code labels.
501 Note: Don't try to assemble the instructions in the comments.
502 0L and 0w are not legal. */
503 static const char f32_1[] =
504 {0x90}; /* nop */
505 static const char f32_2[] =
506 {0x89,0xf6}; /* movl %esi,%esi */
507 static const char f32_3[] =
508 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
509 static const char f32_4[] =
510 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
511 static const char f32_5[] =
512 {0x90, /* nop */
513 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
514 static const char f32_6[] =
515 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
516 static const char f32_7[] =
517 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
518 static const char f32_8[] =
519 {0x90, /* nop */
520 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
521 static const char f32_9[] =
522 {0x89,0xf6, /* movl %esi,%esi */
523 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
524 static const char f32_10[] =
525 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
526 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
527 static const char f32_11[] =
528 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
529 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
530 static const char f32_12[] =
531 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
532 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
533 static const char f32_13[] =
534 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
535 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
536 static const char f32_14[] =
537 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
538 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
539 static const char f32_15[] =
540 {0xeb,0x0d,0x90,0x90,0x90,0x90,0x90, /* jmp .+15; lotsa nops */
541 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
542 static const char f16_3[] =
543 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
544 static const char f16_4[] =
545 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
546 static const char f16_5[] =
547 {0x90, /* nop */
548 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
549 static const char f16_6[] =
550 {0x89,0xf6, /* mov %si,%si */
551 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
552 static const char f16_7[] =
553 {0x8d,0x74,0x00, /* lea 0(%si),%si */
554 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
555 static const char f16_8[] =
556 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
557 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
558 static const char *const f32_patt[] = {
559 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
560 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14, f32_15
561 };
562 static const char *const f16_patt[] = {
563 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8,
564 f32_15, f32_15, f32_15, f32_15, f32_15, f32_15, f32_15
565 };
566
567 if (count <= 0 || count > 15)
568 return;
569
570 /* The recommended way to pad 64bit code is to use NOPs preceded by
571 maximally four 0x66 prefixes. Balance the size of nops. */
572 if (flag_code == CODE_64BIT)
573 {
574 int i;
575 int nnops = (count + 3) / 4;
576 int len = count / nnops;
577 int remains = count - nnops * len;
578 int pos = 0;
579
580 for (i = 0; i < remains; i++)
581 {
582 memset (fragP->fr_literal + fragP->fr_fix + pos, 0x66, len);
583 fragP->fr_literal[fragP->fr_fix + pos + len] = 0x90;
584 pos += len + 1;
585 }
586 for (; i < nnops; i++)
587 {
588 memset (fragP->fr_literal + fragP->fr_fix + pos, 0x66, len - 1);
589 fragP->fr_literal[fragP->fr_fix + pos + len - 1] = 0x90;
590 pos += len;
591 }
592 }
593 else
594 if (flag_code == CODE_16BIT)
595 {
596 memcpy (fragP->fr_literal + fragP->fr_fix,
597 f16_patt[count - 1], count);
598 if (count > 8)
599 /* Adjust jump offset. */
600 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
601 }
602 else
603 memcpy (fragP->fr_literal + fragP->fr_fix,
604 f32_patt[count - 1], count);
605 fragP->fr_var = count;
606 }
607
608 static INLINE unsigned int
609 mode_from_disp_size (t)
610 unsigned int t;
611 {
612 return (t & Disp8) ? 1 : (t & (Disp16 | Disp32 | Disp32S)) ? 2 : 0;
613 }
614
615 static INLINE int
616 fits_in_signed_byte (num)
617 offsetT num;
618 {
619 return (num >= -128) && (num <= 127);
620 }
621
622 static INLINE int
623 fits_in_unsigned_byte (num)
624 offsetT num;
625 {
626 return (num & 0xff) == num;
627 }
628
629 static INLINE int
630 fits_in_unsigned_word (num)
631 offsetT num;
632 {
633 return (num & 0xffff) == num;
634 }
635
636 static INLINE int
637 fits_in_signed_word (num)
638 offsetT num;
639 {
640 return (-32768 <= num) && (num <= 32767);
641 }
642 static INLINE int
643 fits_in_signed_long (num)
644 offsetT num ATTRIBUTE_UNUSED;
645 {
646 #ifndef BFD64
647 return 1;
648 #else
649 return (!(((offsetT) -1 << 31) & num)
650 || (((offsetT) -1 << 31) & num) == ((offsetT) -1 << 31));
651 #endif
652 } /* fits_in_signed_long() */
653 static INLINE int
654 fits_in_unsigned_long (num)
655 offsetT num ATTRIBUTE_UNUSED;
656 {
657 #ifndef BFD64
658 return 1;
659 #else
660 return (num & (((offsetT) 2 << 31) - 1)) == num;
661 #endif
662 } /* fits_in_unsigned_long() */
663
664 static int
665 smallest_imm_type (num)
666 offsetT num;
667 {
668 if (cpu_arch_flags != (Cpu086 | Cpu186 | Cpu286 | Cpu386 | Cpu486 | CpuNo64))
669 {
670 /* This code is disabled on the 486 because all the Imm1 forms
671 in the opcode table are slower on the i486. They're the
672 versions with the implicitly specified single-position
673 displacement, which has another syntax if you really want to
674 use that form. */
675 if (num == 1)
676 return Imm1 | Imm8 | Imm8S | Imm16 | Imm32 | Imm32S | Imm64;
677 }
678 return (fits_in_signed_byte (num)
679 ? (Imm8S | Imm8 | Imm16 | Imm32 | Imm32S | Imm64)
680 : fits_in_unsigned_byte (num)
681 ? (Imm8 | Imm16 | Imm32 | Imm32S | Imm64)
682 : (fits_in_signed_word (num) || fits_in_unsigned_word (num))
683 ? (Imm16 | Imm32 | Imm32S | Imm64)
684 : fits_in_signed_long (num)
685 ? (Imm32 | Imm32S | Imm64)
686 : fits_in_unsigned_long (num)
687 ? (Imm32 | Imm64)
688 : Imm64);
689 }
690
691 static offsetT
692 offset_in_range (val, size)
693 offsetT val;
694 int size;
695 {
696 addressT mask;
697
698 switch (size)
699 {
700 case 1: mask = ((addressT) 1 << 8) - 1; break;
701 case 2: mask = ((addressT) 1 << 16) - 1; break;
702 case 4: mask = ((addressT) 2 << 31) - 1; break;
703 #ifdef BFD64
704 case 8: mask = ((addressT) 2 << 63) - 1; break;
705 #endif
706 default: abort ();
707 }
708
709 /* If BFD64, sign extend val. */
710 if (!use_rela_relocations)
711 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
712 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
713
714 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
715 {
716 char buf1[40], buf2[40];
717
718 sprint_value (buf1, val);
719 sprint_value (buf2, val & mask);
720 as_warn (_("%s shortened to %s"), buf1, buf2);
721 }
722 return val & mask;
723 }
724
725 /* Returns 0 if attempting to add a prefix where one from the same
726 class already exists, 1 if non rep/repne added, 2 if rep/repne
727 added. */
728 static int
729 add_prefix (prefix)
730 unsigned int prefix;
731 {
732 int ret = 1;
733 unsigned int q;
734
735 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
736 && flag_code == CODE_64BIT)
737 {
738 if ((i.prefix[REX_PREFIX] & prefix & REX_MODE64)
739 || ((i.prefix[REX_PREFIX] & (REX_EXTX | REX_EXTY | REX_EXTZ))
740 && (prefix & (REX_EXTX | REX_EXTY | REX_EXTZ))))
741 ret = 0;
742 q = REX_PREFIX;
743 }
744 else
745 {
746 switch (prefix)
747 {
748 default:
749 abort ();
750
751 case CS_PREFIX_OPCODE:
752 case DS_PREFIX_OPCODE:
753 case ES_PREFIX_OPCODE:
754 case FS_PREFIX_OPCODE:
755 case GS_PREFIX_OPCODE:
756 case SS_PREFIX_OPCODE:
757 q = SEG_PREFIX;
758 break;
759
760 case REPNE_PREFIX_OPCODE:
761 case REPE_PREFIX_OPCODE:
762 ret = 2;
763 /* fall thru */
764 case LOCK_PREFIX_OPCODE:
765 q = LOCKREP_PREFIX;
766 break;
767
768 case FWAIT_OPCODE:
769 q = WAIT_PREFIX;
770 break;
771
772 case ADDR_PREFIX_OPCODE:
773 q = ADDR_PREFIX;
774 break;
775
776 case DATA_PREFIX_OPCODE:
777 q = DATA_PREFIX;
778 break;
779 }
780 if (i.prefix[q] != 0)
781 ret = 0;
782 }
783
784 if (ret)
785 {
786 if (!i.prefix[q])
787 ++i.prefixes;
788 i.prefix[q] |= prefix;
789 }
790 else
791 as_bad (_("same type of prefix used twice"));
792
793 return ret;
794 }
795
796 static void
797 set_code_flag (value)
798 int value;
799 {
800 flag_code = value;
801 cpu_arch_flags &= ~(Cpu64 | CpuNo64);
802 cpu_arch_flags |= (flag_code == CODE_64BIT ? Cpu64 : CpuNo64);
803 if (value == CODE_64BIT && !(cpu_arch_flags & CpuSledgehammer))
804 {
805 as_bad (_("64bit mode not supported on this CPU."));
806 }
807 if (value == CODE_32BIT && !(cpu_arch_flags & Cpu386))
808 {
809 as_bad (_("32bit mode not supported on this CPU."));
810 }
811 stackop_size = '\0';
812 }
813
814 static void
815 set_16bit_gcc_code_flag (new_code_flag)
816 int new_code_flag;
817 {
818 flag_code = new_code_flag;
819 cpu_arch_flags &= ~(Cpu64 | CpuNo64);
820 cpu_arch_flags |= (flag_code == CODE_64BIT ? Cpu64 : CpuNo64);
821 stackop_size = LONG_MNEM_SUFFIX;
822 }
823
824 static void
825 set_intel_syntax (syntax_flag)
826 int syntax_flag;
827 {
828 /* Find out if register prefixing is specified. */
829 int ask_naked_reg = 0;
830
831 SKIP_WHITESPACE ();
832 if (!is_end_of_line[(unsigned char) *input_line_pointer])
833 {
834 char *string = input_line_pointer;
835 int e = get_symbol_end ();
836
837 if (strcmp (string, "prefix") == 0)
838 ask_naked_reg = 1;
839 else if (strcmp (string, "noprefix") == 0)
840 ask_naked_reg = -1;
841 else
842 as_bad (_("bad argument to syntax directive."));
843 *input_line_pointer = e;
844 }
845 demand_empty_rest_of_line ();
846
847 intel_syntax = syntax_flag;
848
849 if (ask_naked_reg == 0)
850 allow_naked_reg = (intel_syntax
851 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
852 else
853 allow_naked_reg = (ask_naked_reg < 0);
854
855 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
856 identifier_chars['$'] = intel_syntax ? '$' : 0;
857 }
858
859 static void
860 set_cpu_arch (dummy)
861 int dummy ATTRIBUTE_UNUSED;
862 {
863 SKIP_WHITESPACE ();
864
865 if (!is_end_of_line[(unsigned char) *input_line_pointer])
866 {
867 char *string = input_line_pointer;
868 int e = get_symbol_end ();
869 int i;
870
871 for (i = 0; cpu_arch[i].name; i++)
872 {
873 if (strcmp (string, cpu_arch[i].name) == 0)
874 {
875 if (*string != '.')
876 {
877 cpu_arch_name = cpu_arch[i].name;
878 cpu_sub_arch_name = NULL;
879 cpu_arch_flags = (cpu_arch[i].flags
880 | (flag_code == CODE_64BIT ? Cpu64 : CpuNo64));
881 break;
882 }
883 if ((cpu_arch_flags | cpu_arch[i].flags) != cpu_arch_flags)
884 {
885 cpu_sub_arch_name = cpu_arch[i].name;
886 cpu_arch_flags |= cpu_arch[i].flags;
887 }
888 *input_line_pointer = e;
889 demand_empty_rest_of_line ();
890 return;
891 }
892 }
893 if (!cpu_arch[i].name)
894 as_bad (_("no such architecture: `%s'"), string);
895
896 *input_line_pointer = e;
897 }
898 else
899 as_bad (_("missing cpu architecture"));
900
901 no_cond_jump_promotion = 0;
902 if (*input_line_pointer == ','
903 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
904 {
905 char *string = ++input_line_pointer;
906 int e = get_symbol_end ();
907
908 if (strcmp (string, "nojumps") == 0)
909 no_cond_jump_promotion = 1;
910 else if (strcmp (string, "jumps") == 0)
911 ;
912 else
913 as_bad (_("no such architecture modifier: `%s'"), string);
914
915 *input_line_pointer = e;
916 }
917
918 demand_empty_rest_of_line ();
919 }
920
921 unsigned long
922 i386_mach ()
923 {
924 if (!strcmp (default_arch, "x86_64"))
925 return bfd_mach_x86_64;
926 else if (!strcmp (default_arch, "i386"))
927 return bfd_mach_i386_i386;
928 else
929 as_fatal (_("Unknown architecture"));
930 }
931 \f
932 void
933 md_begin ()
934 {
935 const char *hash_err;
936
937 /* Initialize op_hash hash table. */
938 op_hash = hash_new ();
939
940 {
941 const template *optab;
942 templates *core_optab;
943
944 /* Setup for loop. */
945 optab = i386_optab;
946 core_optab = (templates *) xmalloc (sizeof (templates));
947 core_optab->start = optab;
948
949 while (1)
950 {
951 ++optab;
952 if (optab->name == NULL
953 || strcmp (optab->name, (optab - 1)->name) != 0)
954 {
955 /* different name --> ship out current template list;
956 add to hash table; & begin anew. */
957 core_optab->end = optab;
958 hash_err = hash_insert (op_hash,
959 (optab - 1)->name,
960 (PTR) core_optab);
961 if (hash_err)
962 {
963 as_fatal (_("Internal Error: Can't hash %s: %s"),
964 (optab - 1)->name,
965 hash_err);
966 }
967 if (optab->name == NULL)
968 break;
969 core_optab = (templates *) xmalloc (sizeof (templates));
970 core_optab->start = optab;
971 }
972 }
973 }
974
975 /* Initialize reg_hash hash table. */
976 reg_hash = hash_new ();
977 {
978 const reg_entry *regtab;
979
980 for (regtab = i386_regtab;
981 regtab < i386_regtab + sizeof (i386_regtab) / sizeof (i386_regtab[0]);
982 regtab++)
983 {
984 hash_err = hash_insert (reg_hash, regtab->reg_name, (PTR) regtab);
985 if (hash_err)
986 as_fatal (_("Internal Error: Can't hash %s: %s"),
987 regtab->reg_name,
988 hash_err);
989 }
990 }
991
992 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
993 {
994 int c;
995 char *p;
996
997 for (c = 0; c < 256; c++)
998 {
999 if (ISDIGIT (c))
1000 {
1001 digit_chars[c] = c;
1002 mnemonic_chars[c] = c;
1003 register_chars[c] = c;
1004 operand_chars[c] = c;
1005 }
1006 else if (ISLOWER (c))
1007 {
1008 mnemonic_chars[c] = c;
1009 register_chars[c] = c;
1010 operand_chars[c] = c;
1011 }
1012 else if (ISUPPER (c))
1013 {
1014 mnemonic_chars[c] = TOLOWER (c);
1015 register_chars[c] = mnemonic_chars[c];
1016 operand_chars[c] = c;
1017 }
1018
1019 if (ISALPHA (c) || ISDIGIT (c))
1020 identifier_chars[c] = c;
1021 else if (c >= 128)
1022 {
1023 identifier_chars[c] = c;
1024 operand_chars[c] = c;
1025 }
1026 }
1027
1028 #ifdef LEX_AT
1029 identifier_chars['@'] = '@';
1030 #endif
1031 #ifdef LEX_QM
1032 identifier_chars['?'] = '?';
1033 operand_chars['?'] = '?';
1034 #endif
1035 digit_chars['-'] = '-';
1036 mnemonic_chars['-'] = '-';
1037 identifier_chars['_'] = '_';
1038 identifier_chars['.'] = '.';
1039
1040 for (p = operand_special_chars; *p != '\0'; p++)
1041 operand_chars[(unsigned char) *p] = *p;
1042 }
1043
1044 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1045 if (IS_ELF)
1046 {
1047 record_alignment (text_section, 2);
1048 record_alignment (data_section, 2);
1049 record_alignment (bss_section, 2);
1050 }
1051 #endif
1052
1053 if (flag_code == CODE_64BIT)
1054 {
1055 x86_dwarf2_return_column = 16;
1056 x86_cie_data_alignment = -8;
1057 }
1058 else
1059 {
1060 x86_dwarf2_return_column = 8;
1061 x86_cie_data_alignment = -4;
1062 }
1063 }
1064
1065 void
1066 i386_print_statistics (file)
1067 FILE *file;
1068 {
1069 hash_print_statistics (file, "i386 opcode", op_hash);
1070 hash_print_statistics (file, "i386 register", reg_hash);
1071 }
1072 \f
1073 #ifdef DEBUG386
1074
1075 /* Debugging routines for md_assemble. */
1076 static void pi PARAMS ((char *, i386_insn *));
1077 static void pte PARAMS ((template *));
1078 static void pt PARAMS ((unsigned int));
1079 static void pe PARAMS ((expressionS *));
1080 static void ps PARAMS ((symbolS *));
1081
1082 static void
1083 pi (line, x)
1084 char *line;
1085 i386_insn *x;
1086 {
1087 unsigned int i;
1088
1089 fprintf (stdout, "%s: template ", line);
1090 pte (&x->tm);
1091 fprintf (stdout, " address: base %s index %s scale %x\n",
1092 x->base_reg ? x->base_reg->reg_name : "none",
1093 x->index_reg ? x->index_reg->reg_name : "none",
1094 x->log2_scale_factor);
1095 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
1096 x->rm.mode, x->rm.reg, x->rm.regmem);
1097 fprintf (stdout, " sib: base %x index %x scale %x\n",
1098 x->sib.base, x->sib.index, x->sib.scale);
1099 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
1100 (x->rex & REX_MODE64) != 0,
1101 (x->rex & REX_EXTX) != 0,
1102 (x->rex & REX_EXTY) != 0,
1103 (x->rex & REX_EXTZ) != 0);
1104 for (i = 0; i < x->operands; i++)
1105 {
1106 fprintf (stdout, " #%d: ", i + 1);
1107 pt (x->types[i]);
1108 fprintf (stdout, "\n");
1109 if (x->types[i]
1110 & (Reg | SReg2 | SReg3 | Control | Debug | Test | RegMMX | RegXMM))
1111 fprintf (stdout, "%s\n", x->op[i].regs->reg_name);
1112 if (x->types[i] & Imm)
1113 pe (x->op[i].imms);
1114 if (x->types[i] & Disp)
1115 pe (x->op[i].disps);
1116 }
1117 }
1118
1119 static void
1120 pte (t)
1121 template *t;
1122 {
1123 unsigned int i;
1124 fprintf (stdout, " %d operands ", t->operands);
1125 fprintf (stdout, "opcode %x ", t->base_opcode);
1126 if (t->extension_opcode != None)
1127 fprintf (stdout, "ext %x ", t->extension_opcode);
1128 if (t->opcode_modifier & D)
1129 fprintf (stdout, "D");
1130 if (t->opcode_modifier & W)
1131 fprintf (stdout, "W");
1132 fprintf (stdout, "\n");
1133 for (i = 0; i < t->operands; i++)
1134 {
1135 fprintf (stdout, " #%d type ", i + 1);
1136 pt (t->operand_types[i]);
1137 fprintf (stdout, "\n");
1138 }
1139 }
1140
1141 static void
1142 pe (e)
1143 expressionS *e;
1144 {
1145 fprintf (stdout, " operation %d\n", e->X_op);
1146 fprintf (stdout, " add_number %ld (%lx)\n",
1147 (long) e->X_add_number, (long) e->X_add_number);
1148 if (e->X_add_symbol)
1149 {
1150 fprintf (stdout, " add_symbol ");
1151 ps (e->X_add_symbol);
1152 fprintf (stdout, "\n");
1153 }
1154 if (e->X_op_symbol)
1155 {
1156 fprintf (stdout, " op_symbol ");
1157 ps (e->X_op_symbol);
1158 fprintf (stdout, "\n");
1159 }
1160 }
1161
1162 static void
1163 ps (s)
1164 symbolS *s;
1165 {
1166 fprintf (stdout, "%s type %s%s",
1167 S_GET_NAME (s),
1168 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
1169 segment_name (S_GET_SEGMENT (s)));
1170 }
1171
1172 static struct type_name
1173 {
1174 unsigned int mask;
1175 char *tname;
1176 }
1177 const type_names[] =
1178 {
1179 { Reg8, "r8" },
1180 { Reg16, "r16" },
1181 { Reg32, "r32" },
1182 { Reg64, "r64" },
1183 { Imm8, "i8" },
1184 { Imm8S, "i8s" },
1185 { Imm16, "i16" },
1186 { Imm32, "i32" },
1187 { Imm32S, "i32s" },
1188 { Imm64, "i64" },
1189 { Imm1, "i1" },
1190 { BaseIndex, "BaseIndex" },
1191 { Disp8, "d8" },
1192 { Disp16, "d16" },
1193 { Disp32, "d32" },
1194 { Disp32S, "d32s" },
1195 { Disp64, "d64" },
1196 { InOutPortReg, "InOutPortReg" },
1197 { ShiftCount, "ShiftCount" },
1198 { Control, "control reg" },
1199 { Test, "test reg" },
1200 { Debug, "debug reg" },
1201 { FloatReg, "FReg" },
1202 { FloatAcc, "FAcc" },
1203 { SReg2, "SReg2" },
1204 { SReg3, "SReg3" },
1205 { Acc, "Acc" },
1206 { JumpAbsolute, "Jump Absolute" },
1207 { RegMMX, "rMMX" },
1208 { RegXMM, "rXMM" },
1209 { EsSeg, "es" },
1210 { 0, "" }
1211 };
1212
1213 static void
1214 pt (t)
1215 unsigned int t;
1216 {
1217 const struct type_name *ty;
1218
1219 for (ty = type_names; ty->mask; ty++)
1220 if (t & ty->mask)
1221 fprintf (stdout, "%s, ", ty->tname);
1222 fflush (stdout);
1223 }
1224
1225 #endif /* DEBUG386 */
1226 \f
1227 static bfd_reloc_code_real_type
1228 reloc (unsigned int size,
1229 int pcrel,
1230 int sign,
1231 bfd_reloc_code_real_type other)
1232 {
1233 if (other != NO_RELOC)
1234 {
1235 reloc_howto_type *reloc;
1236
1237 if (size == 8)
1238 switch (other)
1239 {
1240 case BFD_RELOC_X86_64_GOT32:
1241 return BFD_RELOC_X86_64_GOT64;
1242 break;
1243 case BFD_RELOC_X86_64_PLTOFF64:
1244 return BFD_RELOC_X86_64_PLTOFF64;
1245 break;
1246 case BFD_RELOC_X86_64_GOTPC32:
1247 other = BFD_RELOC_X86_64_GOTPC64;
1248 break;
1249 case BFD_RELOC_X86_64_GOTPCREL:
1250 other = BFD_RELOC_X86_64_GOTPCREL64;
1251 break;
1252 case BFD_RELOC_X86_64_TPOFF32:
1253 other = BFD_RELOC_X86_64_TPOFF64;
1254 break;
1255 case BFD_RELOC_X86_64_DTPOFF32:
1256 other = BFD_RELOC_X86_64_DTPOFF64;
1257 break;
1258 default:
1259 break;
1260 }
1261
1262 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
1263 if (size == 4 && flag_code != CODE_64BIT)
1264 sign = -1;
1265
1266 reloc = bfd_reloc_type_lookup (stdoutput, other);
1267 if (!reloc)
1268 as_bad (_("unknown relocation (%u)"), other);
1269 else if (size != bfd_get_reloc_size (reloc))
1270 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
1271 bfd_get_reloc_size (reloc),
1272 size);
1273 else if (pcrel && !reloc->pc_relative)
1274 as_bad (_("non-pc-relative relocation for pc-relative field"));
1275 else if ((reloc->complain_on_overflow == complain_overflow_signed
1276 && !sign)
1277 || (reloc->complain_on_overflow == complain_overflow_unsigned
1278 && sign > 0))
1279 as_bad (_("relocated field and relocation type differ in signedness"));
1280 else
1281 return other;
1282 return NO_RELOC;
1283 }
1284
1285 if (pcrel)
1286 {
1287 if (!sign)
1288 as_bad (_("there are no unsigned pc-relative relocations"));
1289 switch (size)
1290 {
1291 case 1: return BFD_RELOC_8_PCREL;
1292 case 2: return BFD_RELOC_16_PCREL;
1293 case 4: return BFD_RELOC_32_PCREL;
1294 case 8: return BFD_RELOC_64_PCREL;
1295 }
1296 as_bad (_("cannot do %u byte pc-relative relocation"), size);
1297 }
1298 else
1299 {
1300 if (sign > 0)
1301 switch (size)
1302 {
1303 case 4: return BFD_RELOC_X86_64_32S;
1304 }
1305 else
1306 switch (size)
1307 {
1308 case 1: return BFD_RELOC_8;
1309 case 2: return BFD_RELOC_16;
1310 case 4: return BFD_RELOC_32;
1311 case 8: return BFD_RELOC_64;
1312 }
1313 as_bad (_("cannot do %s %u byte relocation"),
1314 sign > 0 ? "signed" : "unsigned", size);
1315 }
1316
1317 abort ();
1318 return BFD_RELOC_NONE;
1319 }
1320
1321 /* Here we decide which fixups can be adjusted to make them relative to
1322 the beginning of the section instead of the symbol. Basically we need
1323 to make sure that the dynamic relocations are done correctly, so in
1324 some cases we force the original symbol to be used. */
1325
1326 int
1327 tc_i386_fix_adjustable (fixP)
1328 fixS *fixP ATTRIBUTE_UNUSED;
1329 {
1330 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1331 if (!IS_ELF)
1332 return 1;
1333
1334 /* Don't adjust pc-relative references to merge sections in 64-bit
1335 mode. */
1336 if (use_rela_relocations
1337 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
1338 && fixP->fx_pcrel)
1339 return 0;
1340
1341 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
1342 and changed later by validate_fix. */
1343 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
1344 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
1345 return 0;
1346
1347 /* adjust_reloc_syms doesn't know about the GOT. */
1348 if (fixP->fx_r_type == BFD_RELOC_386_GOTOFF
1349 || fixP->fx_r_type == BFD_RELOC_386_PLT32
1350 || fixP->fx_r_type == BFD_RELOC_386_GOT32
1351 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
1352 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
1353 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
1354 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
1355 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
1356 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
1357 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
1358 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
1359 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
1360 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
1361 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
1362 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
1363 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
1364 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
1365 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
1366 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
1367 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
1368 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
1369 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
1370 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
1371 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
1372 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
1373 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
1374 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
1375 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
1376 return 0;
1377 #endif
1378 return 1;
1379 }
1380
1381 static int intel_float_operand PARAMS ((const char *mnemonic));
1382
1383 static int
1384 intel_float_operand (mnemonic)
1385 const char *mnemonic;
1386 {
1387 /* Note that the value returned is meaningful only for opcodes with (memory)
1388 operands, hence the code here is free to improperly handle opcodes that
1389 have no operands (for better performance and smaller code). */
1390
1391 if (mnemonic[0] != 'f')
1392 return 0; /* non-math */
1393
1394 switch (mnemonic[1])
1395 {
1396 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
1397 the fs segment override prefix not currently handled because no
1398 call path can make opcodes without operands get here */
1399 case 'i':
1400 return 2 /* integer op */;
1401 case 'l':
1402 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
1403 return 3; /* fldcw/fldenv */
1404 break;
1405 case 'n':
1406 if (mnemonic[2] != 'o' /* fnop */)
1407 return 3; /* non-waiting control op */
1408 break;
1409 case 'r':
1410 if (mnemonic[2] == 's')
1411 return 3; /* frstor/frstpm */
1412 break;
1413 case 's':
1414 if (mnemonic[2] == 'a')
1415 return 3; /* fsave */
1416 if (mnemonic[2] == 't')
1417 {
1418 switch (mnemonic[3])
1419 {
1420 case 'c': /* fstcw */
1421 case 'd': /* fstdw */
1422 case 'e': /* fstenv */
1423 case 's': /* fsts[gw] */
1424 return 3;
1425 }
1426 }
1427 break;
1428 case 'x':
1429 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
1430 return 0; /* fxsave/fxrstor are not really math ops */
1431 break;
1432 }
1433
1434 return 1;
1435 }
1436
1437 /* This is the guts of the machine-dependent assembler. LINE points to a
1438 machine dependent instruction. This function is supposed to emit
1439 the frags/bytes it assembles to. */
1440
1441 void
1442 md_assemble (line)
1443 char *line;
1444 {
1445 int j;
1446 char mnemonic[MAX_MNEM_SIZE];
1447
1448 /* Initialize globals. */
1449 memset (&i, '\0', sizeof (i));
1450 for (j = 0; j < MAX_OPERANDS; j++)
1451 i.reloc[j] = NO_RELOC;
1452 memset (disp_expressions, '\0', sizeof (disp_expressions));
1453 memset (im_expressions, '\0', sizeof (im_expressions));
1454 save_stack_p = save_stack;
1455
1456 /* First parse an instruction mnemonic & call i386_operand for the operands.
1457 We assume that the scrubber has arranged it so that line[0] is the valid
1458 start of a (possibly prefixed) mnemonic. */
1459
1460 line = parse_insn (line, mnemonic);
1461 if (line == NULL)
1462 return;
1463
1464 line = parse_operands (line, mnemonic);
1465 if (line == NULL)
1466 return;
1467
1468 /* Now we've parsed the mnemonic into a set of templates, and have the
1469 operands at hand. */
1470
1471 /* All intel opcodes have reversed operands except for "bound" and
1472 "enter". We also don't reverse intersegment "jmp" and "call"
1473 instructions with 2 immediate operands so that the immediate segment
1474 precedes the offset, as it does when in AT&T mode. "enter" and the
1475 intersegment "jmp" and "call" instructions are the only ones that
1476 have two immediate operands. */
1477 if (intel_syntax && i.operands > 1
1478 && (strcmp (mnemonic, "bound") != 0)
1479 && (strcmp (mnemonic, "invlpga") != 0)
1480 && !((i.types[0] & Imm) && (i.types[1] & Imm)))
1481 swap_operands ();
1482
1483 if (i.imm_operands)
1484 optimize_imm ();
1485
1486 /* Don't optimize displacement for movabs since it only takes 64bit
1487 displacement. */
1488 if (i.disp_operands
1489 && (flag_code != CODE_64BIT
1490 || strcmp (mnemonic, "movabs") != 0))
1491 optimize_disp ();
1492
1493 /* Next, we find a template that matches the given insn,
1494 making sure the overlap of the given operands types is consistent
1495 with the template operand types. */
1496
1497 if (!match_template ())
1498 return;
1499
1500 if (intel_syntax)
1501 {
1502 /* Undo SYSV386_COMPAT brokenness when in Intel mode. See i386.h */
1503 if (SYSV386_COMPAT
1504 && (i.tm.base_opcode & 0xfffffde0) == 0xdce0)
1505 i.tm.base_opcode ^= FloatR;
1506
1507 /* Zap movzx and movsx suffix. The suffix may have been set from
1508 "word ptr" or "byte ptr" on the source operand, but we'll use
1509 the suffix later to choose the destination register. */
1510 if ((i.tm.base_opcode & ~9) == 0x0fb6)
1511 {
1512 if (i.reg_operands < 2
1513 && !i.suffix
1514 && (~i.tm.opcode_modifier
1515 & (No_bSuf
1516 | No_wSuf
1517 | No_lSuf
1518 | No_sSuf
1519 | No_xSuf
1520 | No_qSuf)))
1521 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
1522
1523 i.suffix = 0;
1524 }
1525 }
1526
1527 if (i.tm.opcode_modifier & FWait)
1528 if (!add_prefix (FWAIT_OPCODE))
1529 return;
1530
1531 /* Check string instruction segment overrides. */
1532 if ((i.tm.opcode_modifier & IsString) != 0 && i.mem_operands != 0)
1533 {
1534 if (!check_string ())
1535 return;
1536 }
1537
1538 if (!process_suffix ())
1539 return;
1540
1541 /* Make still unresolved immediate matches conform to size of immediate
1542 given in i.suffix. */
1543 if (!finalize_imm ())
1544 return;
1545
1546 if (i.types[0] & Imm1)
1547 i.imm_operands = 0; /* kludge for shift insns. */
1548 if (i.types[0] & ImplicitRegister)
1549 i.reg_operands--;
1550 if (i.types[1] & ImplicitRegister)
1551 i.reg_operands--;
1552 if (i.types[2] & ImplicitRegister)
1553 i.reg_operands--;
1554
1555 if (i.tm.opcode_modifier & ImmExt)
1556 {
1557 expressionS *exp;
1558
1559 if ((i.tm.cpu_flags & CpuPNI) && i.operands > 0)
1560 {
1561 /* These Intel Prescott New Instructions have the fixed
1562 operands with an opcode suffix which is coded in the same
1563 place as an 8-bit immediate field would be. Here we check
1564 those operands and remove them afterwards. */
1565 unsigned int x;
1566
1567 for (x = 0; x < i.operands; x++)
1568 if (i.op[x].regs->reg_num != x)
1569 as_bad (_("can't use register '%%%s' as operand %d in '%s'."),
1570 i.op[x].regs->reg_name, x + 1, i.tm.name);
1571 i.operands = 0;
1572 }
1573
1574 /* These AMD 3DNow! and Intel Katmai New Instructions have an
1575 opcode suffix which is coded in the same place as an 8-bit
1576 immediate field would be. Here we fake an 8-bit immediate
1577 operand from the opcode suffix stored in tm.extension_opcode. */
1578
1579 assert (i.imm_operands == 0 && i.operands <= 2 && 2 < MAX_OPERANDS);
1580
1581 exp = &im_expressions[i.imm_operands++];
1582 i.op[i.operands].imms = exp;
1583 i.types[i.operands++] = Imm8;
1584 exp->X_op = O_constant;
1585 exp->X_add_number = i.tm.extension_opcode;
1586 i.tm.extension_opcode = None;
1587 }
1588
1589 /* For insns with operands there are more diddles to do to the opcode. */
1590 if (i.operands)
1591 {
1592 if (!process_operands ())
1593 return;
1594 }
1595 else if (!quiet_warnings && (i.tm.opcode_modifier & Ugh) != 0)
1596 {
1597 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
1598 as_warn (_("translating to `%sp'"), i.tm.name);
1599 }
1600
1601 /* Handle conversion of 'int $3' --> special int3 insn. */
1602 if (i.tm.base_opcode == INT_OPCODE && i.op[0].imms->X_add_number == 3)
1603 {
1604 i.tm.base_opcode = INT3_OPCODE;
1605 i.imm_operands = 0;
1606 }
1607
1608 if ((i.tm.opcode_modifier & (Jump | JumpByte | JumpDword))
1609 && i.op[0].disps->X_op == O_constant)
1610 {
1611 /* Convert "jmp constant" (and "call constant") to a jump (call) to
1612 the absolute address given by the constant. Since ix86 jumps and
1613 calls are pc relative, we need to generate a reloc. */
1614 i.op[0].disps->X_add_symbol = &abs_symbol;
1615 i.op[0].disps->X_op = O_symbol;
1616 }
1617
1618 if ((i.tm.opcode_modifier & Rex64) != 0)
1619 i.rex |= REX_MODE64;
1620
1621 /* For 8 bit registers we need an empty rex prefix. Also if the
1622 instruction already has a prefix, we need to convert old
1623 registers to new ones. */
1624
1625 if (((i.types[0] & Reg8) != 0
1626 && (i.op[0].regs->reg_flags & RegRex64) != 0)
1627 || ((i.types[1] & Reg8) != 0
1628 && (i.op[1].regs->reg_flags & RegRex64) != 0)
1629 || (((i.types[0] & Reg8) != 0 || (i.types[1] & Reg8) != 0)
1630 && i.rex != 0))
1631 {
1632 int x;
1633
1634 i.rex |= REX_OPCODE;
1635 for (x = 0; x < 2; x++)
1636 {
1637 /* Look for 8 bit operand that uses old registers. */
1638 if ((i.types[x] & Reg8) != 0
1639 && (i.op[x].regs->reg_flags & RegRex64) == 0)
1640 {
1641 /* In case it is "hi" register, give up. */
1642 if (i.op[x].regs->reg_num > 3)
1643 as_bad (_("can't encode register '%%%s' in an instruction requiring REX prefix."),
1644 i.op[x].regs->reg_name);
1645
1646 /* Otherwise it is equivalent to the extended register.
1647 Since the encoding doesn't change this is merely
1648 cosmetic cleanup for debug output. */
1649
1650 i.op[x].regs = i.op[x].regs + 8;
1651 }
1652 }
1653 }
1654
1655 if (i.rex != 0)
1656 add_prefix (REX_OPCODE | i.rex);
1657
1658 /* We are ready to output the insn. */
1659 output_insn ();
1660 }
1661
1662 static char *
1663 parse_insn (line, mnemonic)
1664 char *line;
1665 char *mnemonic;
1666 {
1667 char *l = line;
1668 char *token_start = l;
1669 char *mnem_p;
1670 int supported;
1671 const template *t;
1672
1673 /* Non-zero if we found a prefix only acceptable with string insns. */
1674 const char *expecting_string_instruction = NULL;
1675
1676 while (1)
1677 {
1678 mnem_p = mnemonic;
1679 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
1680 {
1681 mnem_p++;
1682 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
1683 {
1684 as_bad (_("no such instruction: `%s'"), token_start);
1685 return NULL;
1686 }
1687 l++;
1688 }
1689 if (!is_space_char (*l)
1690 && *l != END_OF_INSN
1691 && (intel_syntax
1692 || (*l != PREFIX_SEPARATOR
1693 && *l != ',')))
1694 {
1695 as_bad (_("invalid character %s in mnemonic"),
1696 output_invalid (*l));
1697 return NULL;
1698 }
1699 if (token_start == l)
1700 {
1701 if (!intel_syntax && *l == PREFIX_SEPARATOR)
1702 as_bad (_("expecting prefix; got nothing"));
1703 else
1704 as_bad (_("expecting mnemonic; got nothing"));
1705 return NULL;
1706 }
1707
1708 /* Look up instruction (or prefix) via hash table. */
1709 current_templates = hash_find (op_hash, mnemonic);
1710
1711 if (*l != END_OF_INSN
1712 && (!is_space_char (*l) || l[1] != END_OF_INSN)
1713 && current_templates
1714 && (current_templates->start->opcode_modifier & IsPrefix))
1715 {
1716 if (current_templates->start->cpu_flags
1717 & (flag_code != CODE_64BIT ? Cpu64 : CpuNo64))
1718 {
1719 as_bad ((flag_code != CODE_64BIT
1720 ? _("`%s' is only supported in 64-bit mode")
1721 : _("`%s' is not supported in 64-bit mode")),
1722 current_templates->start->name);
1723 return NULL;
1724 }
1725 /* If we are in 16-bit mode, do not allow addr16 or data16.
1726 Similarly, in 32-bit mode, do not allow addr32 or data32. */
1727 if ((current_templates->start->opcode_modifier & (Size16 | Size32))
1728 && flag_code != CODE_64BIT
1729 && (((current_templates->start->opcode_modifier & Size32) != 0)
1730 ^ (flag_code == CODE_16BIT)))
1731 {
1732 as_bad (_("redundant %s prefix"),
1733 current_templates->start->name);
1734 return NULL;
1735 }
1736 /* Add prefix, checking for repeated prefixes. */
1737 switch (add_prefix (current_templates->start->base_opcode))
1738 {
1739 case 0:
1740 return NULL;
1741 case 2:
1742 expecting_string_instruction = current_templates->start->name;
1743 break;
1744 }
1745 /* Skip past PREFIX_SEPARATOR and reset token_start. */
1746 token_start = ++l;
1747 }
1748 else
1749 break;
1750 }
1751
1752 if (!current_templates)
1753 {
1754 /* See if we can get a match by trimming off a suffix. */
1755 switch (mnem_p[-1])
1756 {
1757 case WORD_MNEM_SUFFIX:
1758 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
1759 i.suffix = SHORT_MNEM_SUFFIX;
1760 else
1761 case BYTE_MNEM_SUFFIX:
1762 case QWORD_MNEM_SUFFIX:
1763 i.suffix = mnem_p[-1];
1764 mnem_p[-1] = '\0';
1765 current_templates = hash_find (op_hash, mnemonic);
1766 break;
1767 case SHORT_MNEM_SUFFIX:
1768 case LONG_MNEM_SUFFIX:
1769 if (!intel_syntax)
1770 {
1771 i.suffix = mnem_p[-1];
1772 mnem_p[-1] = '\0';
1773 current_templates = hash_find (op_hash, mnemonic);
1774 }
1775 break;
1776
1777 /* Intel Syntax. */
1778 case 'd':
1779 if (intel_syntax)
1780 {
1781 if (intel_float_operand (mnemonic) == 1)
1782 i.suffix = SHORT_MNEM_SUFFIX;
1783 else
1784 i.suffix = LONG_MNEM_SUFFIX;
1785 mnem_p[-1] = '\0';
1786 current_templates = hash_find (op_hash, mnemonic);
1787 }
1788 break;
1789 }
1790 if (!current_templates)
1791 {
1792 as_bad (_("no such instruction: `%s'"), token_start);
1793 return NULL;
1794 }
1795 }
1796
1797 if (current_templates->start->opcode_modifier & (Jump | JumpByte))
1798 {
1799 /* Check for a branch hint. We allow ",pt" and ",pn" for
1800 predict taken and predict not taken respectively.
1801 I'm not sure that branch hints actually do anything on loop
1802 and jcxz insns (JumpByte) for current Pentium4 chips. They
1803 may work in the future and it doesn't hurt to accept them
1804 now. */
1805 if (l[0] == ',' && l[1] == 'p')
1806 {
1807 if (l[2] == 't')
1808 {
1809 if (!add_prefix (DS_PREFIX_OPCODE))
1810 return NULL;
1811 l += 3;
1812 }
1813 else if (l[2] == 'n')
1814 {
1815 if (!add_prefix (CS_PREFIX_OPCODE))
1816 return NULL;
1817 l += 3;
1818 }
1819 }
1820 }
1821 /* Any other comma loses. */
1822 if (*l == ',')
1823 {
1824 as_bad (_("invalid character %s in mnemonic"),
1825 output_invalid (*l));
1826 return NULL;
1827 }
1828
1829 /* Check if instruction is supported on specified architecture. */
1830 supported = 0;
1831 for (t = current_templates->start; t < current_templates->end; ++t)
1832 {
1833 if (!((t->cpu_flags & ~(Cpu64 | CpuNo64))
1834 & ~(cpu_arch_flags & ~(Cpu64 | CpuNo64))))
1835 supported |= 1;
1836 if (!(t->cpu_flags & (flag_code == CODE_64BIT ? CpuNo64 : Cpu64)))
1837 supported |= 2;
1838 }
1839 if (!(supported & 2))
1840 {
1841 as_bad (flag_code == CODE_64BIT
1842 ? _("`%s' is not supported in 64-bit mode")
1843 : _("`%s' is only supported in 64-bit mode"),
1844 current_templates->start->name);
1845 return NULL;
1846 }
1847 if (!(supported & 1))
1848 {
1849 as_warn (_("`%s' is not supported on `%s%s'"),
1850 current_templates->start->name,
1851 cpu_arch_name,
1852 cpu_sub_arch_name ? cpu_sub_arch_name : "");
1853 }
1854 else if ((Cpu386 & ~cpu_arch_flags) && (flag_code != CODE_16BIT))
1855 {
1856 as_warn (_("use .code16 to ensure correct addressing mode"));
1857 }
1858
1859 /* Check for rep/repne without a string instruction. */
1860 if (expecting_string_instruction)
1861 {
1862 static templates override;
1863
1864 for (t = current_templates->start; t < current_templates->end; ++t)
1865 if (t->opcode_modifier & IsString)
1866 break;
1867 if (t >= current_templates->end)
1868 {
1869 as_bad (_("expecting string instruction after `%s'"),
1870 expecting_string_instruction);
1871 return NULL;
1872 }
1873 for (override.start = t; t < current_templates->end; ++t)
1874 if (!(t->opcode_modifier & IsString))
1875 break;
1876 override.end = t;
1877 current_templates = &override;
1878 }
1879
1880 return l;
1881 }
1882
1883 static char *
1884 parse_operands (l, mnemonic)
1885 char *l;
1886 const char *mnemonic;
1887 {
1888 char *token_start;
1889
1890 /* 1 if operand is pending after ','. */
1891 unsigned int expecting_operand = 0;
1892
1893 /* Non-zero if operand parens not balanced. */
1894 unsigned int paren_not_balanced;
1895
1896 while (*l != END_OF_INSN)
1897 {
1898 /* Skip optional white space before operand. */
1899 if (is_space_char (*l))
1900 ++l;
1901 if (!is_operand_char (*l) && *l != END_OF_INSN)
1902 {
1903 as_bad (_("invalid character %s before operand %d"),
1904 output_invalid (*l),
1905 i.operands + 1);
1906 return NULL;
1907 }
1908 token_start = l; /* after white space */
1909 paren_not_balanced = 0;
1910 while (paren_not_balanced || *l != ',')
1911 {
1912 if (*l == END_OF_INSN)
1913 {
1914 if (paren_not_balanced)
1915 {
1916 if (!intel_syntax)
1917 as_bad (_("unbalanced parenthesis in operand %d."),
1918 i.operands + 1);
1919 else
1920 as_bad (_("unbalanced brackets in operand %d."),
1921 i.operands + 1);
1922 return NULL;
1923 }
1924 else
1925 break; /* we are done */
1926 }
1927 else if (!is_operand_char (*l) && !is_space_char (*l))
1928 {
1929 as_bad (_("invalid character %s in operand %d"),
1930 output_invalid (*l),
1931 i.operands + 1);
1932 return NULL;
1933 }
1934 if (!intel_syntax)
1935 {
1936 if (*l == '(')
1937 ++paren_not_balanced;
1938 if (*l == ')')
1939 --paren_not_balanced;
1940 }
1941 else
1942 {
1943 if (*l == '[')
1944 ++paren_not_balanced;
1945 if (*l == ']')
1946 --paren_not_balanced;
1947 }
1948 l++;
1949 }
1950 if (l != token_start)
1951 { /* Yes, we've read in another operand. */
1952 unsigned int operand_ok;
1953 this_operand = i.operands++;
1954 if (i.operands > MAX_OPERANDS)
1955 {
1956 as_bad (_("spurious operands; (%d operands/instruction max)"),
1957 MAX_OPERANDS);
1958 return NULL;
1959 }
1960 /* Now parse operand adding info to 'i' as we go along. */
1961 END_STRING_AND_SAVE (l);
1962
1963 if (intel_syntax)
1964 operand_ok =
1965 i386_intel_operand (token_start,
1966 intel_float_operand (mnemonic));
1967 else
1968 operand_ok = i386_operand (token_start);
1969
1970 RESTORE_END_STRING (l);
1971 if (!operand_ok)
1972 return NULL;
1973 }
1974 else
1975 {
1976 if (expecting_operand)
1977 {
1978 expecting_operand_after_comma:
1979 as_bad (_("expecting operand after ','; got nothing"));
1980 return NULL;
1981 }
1982 if (*l == ',')
1983 {
1984 as_bad (_("expecting operand before ','; got nothing"));
1985 return NULL;
1986 }
1987 }
1988
1989 /* Now *l must be either ',' or END_OF_INSN. */
1990 if (*l == ',')
1991 {
1992 if (*++l == END_OF_INSN)
1993 {
1994 /* Just skip it, if it's \n complain. */
1995 goto expecting_operand_after_comma;
1996 }
1997 expecting_operand = 1;
1998 }
1999 }
2000 return l;
2001 }
2002
2003 static void
2004 swap_operands ()
2005 {
2006 union i386_op temp_op;
2007 unsigned int temp_type;
2008 enum bfd_reloc_code_real temp_reloc;
2009 int xchg1 = 0;
2010 int xchg2 = 0;
2011
2012 if (i.operands == 2)
2013 {
2014 xchg1 = 0;
2015 xchg2 = 1;
2016 }
2017 else if (i.operands == 3)
2018 {
2019 xchg1 = 0;
2020 xchg2 = 2;
2021 }
2022 temp_type = i.types[xchg2];
2023 i.types[xchg2] = i.types[xchg1];
2024 i.types[xchg1] = temp_type;
2025 temp_op = i.op[xchg2];
2026 i.op[xchg2] = i.op[xchg1];
2027 i.op[xchg1] = temp_op;
2028 temp_reloc = i.reloc[xchg2];
2029 i.reloc[xchg2] = i.reloc[xchg1];
2030 i.reloc[xchg1] = temp_reloc;
2031
2032 if (i.mem_operands == 2)
2033 {
2034 const seg_entry *temp_seg;
2035 temp_seg = i.seg[0];
2036 i.seg[0] = i.seg[1];
2037 i.seg[1] = temp_seg;
2038 }
2039 }
2040
2041 /* Try to ensure constant immediates are represented in the smallest
2042 opcode possible. */
2043 static void
2044 optimize_imm ()
2045 {
2046 char guess_suffix = 0;
2047 int op;
2048
2049 if (i.suffix)
2050 guess_suffix = i.suffix;
2051 else if (i.reg_operands)
2052 {
2053 /* Figure out a suffix from the last register operand specified.
2054 We can't do this properly yet, ie. excluding InOutPortReg,
2055 but the following works for instructions with immediates.
2056 In any case, we can't set i.suffix yet. */
2057 for (op = i.operands; --op >= 0;)
2058 if (i.types[op] & Reg)
2059 {
2060 if (i.types[op] & Reg8)
2061 guess_suffix = BYTE_MNEM_SUFFIX;
2062 else if (i.types[op] & Reg16)
2063 guess_suffix = WORD_MNEM_SUFFIX;
2064 else if (i.types[op] & Reg32)
2065 guess_suffix = LONG_MNEM_SUFFIX;
2066 else if (i.types[op] & Reg64)
2067 guess_suffix = QWORD_MNEM_SUFFIX;
2068 break;
2069 }
2070 }
2071 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
2072 guess_suffix = WORD_MNEM_SUFFIX;
2073
2074 for (op = i.operands; --op >= 0;)
2075 if (i.types[op] & Imm)
2076 {
2077 switch (i.op[op].imms->X_op)
2078 {
2079 case O_constant:
2080 /* If a suffix is given, this operand may be shortened. */
2081 switch (guess_suffix)
2082 {
2083 case LONG_MNEM_SUFFIX:
2084 i.types[op] |= Imm32 | Imm64;
2085 break;
2086 case WORD_MNEM_SUFFIX:
2087 i.types[op] |= Imm16 | Imm32S | Imm32 | Imm64;
2088 break;
2089 case BYTE_MNEM_SUFFIX:
2090 i.types[op] |= Imm16 | Imm8 | Imm8S | Imm32S | Imm32 | Imm64;
2091 break;
2092 }
2093
2094 /* If this operand is at most 16 bits, convert it
2095 to a signed 16 bit number before trying to see
2096 whether it will fit in an even smaller size.
2097 This allows a 16-bit operand such as $0xffe0 to
2098 be recognised as within Imm8S range. */
2099 if ((i.types[op] & Imm16)
2100 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
2101 {
2102 i.op[op].imms->X_add_number =
2103 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
2104 }
2105 if ((i.types[op] & Imm32)
2106 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
2107 == 0))
2108 {
2109 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
2110 ^ ((offsetT) 1 << 31))
2111 - ((offsetT) 1 << 31));
2112 }
2113 i.types[op] |= smallest_imm_type (i.op[op].imms->X_add_number);
2114
2115 /* We must avoid matching of Imm32 templates when 64bit
2116 only immediate is available. */
2117 if (guess_suffix == QWORD_MNEM_SUFFIX)
2118 i.types[op] &= ~Imm32;
2119 break;
2120
2121 case O_absent:
2122 case O_register:
2123 abort ();
2124
2125 /* Symbols and expressions. */
2126 default:
2127 /* Convert symbolic operand to proper sizes for matching, but don't
2128 prevent matching a set of insns that only supports sizes other
2129 than those matching the insn suffix. */
2130 {
2131 unsigned int mask, allowed = 0;
2132 const template *t;
2133
2134 for (t = current_templates->start; t < current_templates->end; ++t)
2135 allowed |= t->operand_types[op];
2136 switch (guess_suffix)
2137 {
2138 case QWORD_MNEM_SUFFIX:
2139 mask = Imm64 | Imm32S;
2140 break;
2141 case LONG_MNEM_SUFFIX:
2142 mask = Imm32;
2143 break;
2144 case WORD_MNEM_SUFFIX:
2145 mask = Imm16;
2146 break;
2147 case BYTE_MNEM_SUFFIX:
2148 mask = Imm8;
2149 break;
2150 default:
2151 mask = 0;
2152 break;
2153 }
2154 if (mask & allowed)
2155 i.types[op] &= mask;
2156 }
2157 break;
2158 }
2159 }
2160 }
2161
2162 /* Try to use the smallest displacement type too. */
2163 static void
2164 optimize_disp ()
2165 {
2166 int op;
2167
2168 for (op = i.operands; --op >= 0;)
2169 if (i.types[op] & Disp)
2170 {
2171 if (i.op[op].disps->X_op == O_constant)
2172 {
2173 offsetT disp = i.op[op].disps->X_add_number;
2174
2175 if ((i.types[op] & Disp16)
2176 && (disp & ~(offsetT) 0xffff) == 0)
2177 {
2178 /* If this operand is at most 16 bits, convert
2179 to a signed 16 bit number and don't use 64bit
2180 displacement. */
2181 disp = (((disp & 0xffff) ^ 0x8000) - 0x8000);
2182 i.types[op] &= ~Disp64;
2183 }
2184 if ((i.types[op] & Disp32)
2185 && (disp & ~(((offsetT) 2 << 31) - 1)) == 0)
2186 {
2187 /* If this operand is at most 32 bits, convert
2188 to a signed 32 bit number and don't use 64bit
2189 displacement. */
2190 disp &= (((offsetT) 2 << 31) - 1);
2191 disp = (disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
2192 i.types[op] &= ~Disp64;
2193 }
2194 if (!disp && (i.types[op] & BaseIndex))
2195 {
2196 i.types[op] &= ~Disp;
2197 i.op[op].disps = 0;
2198 i.disp_operands--;
2199 }
2200 else if (flag_code == CODE_64BIT)
2201 {
2202 if (fits_in_signed_long (disp))
2203 {
2204 i.types[op] &= ~Disp64;
2205 i.types[op] |= Disp32S;
2206 }
2207 if (fits_in_unsigned_long (disp))
2208 i.types[op] |= Disp32;
2209 }
2210 if ((i.types[op] & (Disp32 | Disp32S | Disp16))
2211 && fits_in_signed_byte (disp))
2212 i.types[op] |= Disp8;
2213 }
2214 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
2215 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
2216 {
2217 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
2218 i.op[op].disps, 0, i.reloc[op]);
2219 i.types[op] &= ~Disp;
2220 }
2221 else
2222 /* We only support 64bit displacement on constants. */
2223 i.types[op] &= ~Disp64;
2224 }
2225 }
2226
2227 static int
2228 match_template ()
2229 {
2230 /* Points to template once we've found it. */
2231 const template *t;
2232 unsigned int overlap0, overlap1, overlap2;
2233 unsigned int found_reverse_match;
2234 int suffix_check;
2235
2236 #define MATCH(overlap, given, template) \
2237 ((overlap & ~JumpAbsolute) \
2238 && (((given) & (BaseIndex | JumpAbsolute)) \
2239 == ((overlap) & (BaseIndex | JumpAbsolute))))
2240
2241 /* If given types r0 and r1 are registers they must be of the same type
2242 unless the expected operand type register overlap is null.
2243 Note that Acc in a template matches every size of reg. */
2244 #define CONSISTENT_REGISTER_MATCH(m0, g0, t0, m1, g1, t1) \
2245 (((g0) & Reg) == 0 || ((g1) & Reg) == 0 \
2246 || ((g0) & Reg) == ((g1) & Reg) \
2247 || ((((m0) & Acc) ? Reg : (t0)) & (((m1) & Acc) ? Reg : (t1)) & Reg) == 0 )
2248
2249 overlap0 = 0;
2250 overlap1 = 0;
2251 overlap2 = 0;
2252 found_reverse_match = 0;
2253 suffix_check = (i.suffix == BYTE_MNEM_SUFFIX
2254 ? No_bSuf
2255 : (i.suffix == WORD_MNEM_SUFFIX
2256 ? No_wSuf
2257 : (i.suffix == SHORT_MNEM_SUFFIX
2258 ? No_sSuf
2259 : (i.suffix == LONG_MNEM_SUFFIX
2260 ? No_lSuf
2261 : (i.suffix == QWORD_MNEM_SUFFIX
2262 ? No_qSuf
2263 : (i.suffix == LONG_DOUBLE_MNEM_SUFFIX
2264 ? No_xSuf : 0))))));
2265
2266 t = current_templates->start;
2267 if (i.suffix == QWORD_MNEM_SUFFIX
2268 && flag_code != CODE_64BIT
2269 && (intel_syntax
2270 ? !(t->opcode_modifier & IgnoreSize)
2271 && !intel_float_operand (t->name)
2272 : intel_float_operand (t->name) != 2)
2273 && (!(t->operand_types[0] & (RegMMX | RegXMM))
2274 || !(t->operand_types[t->operands > 1] & (RegMMX | RegXMM)))
2275 && (t->base_opcode != 0x0fc7
2276 || t->extension_opcode != 1 /* cmpxchg8b */))
2277 t = current_templates->end;
2278 for (; t < current_templates->end; t++)
2279 {
2280 /* Must have right number of operands. */
2281 if (i.operands != t->operands)
2282 continue;
2283
2284 /* Check the suffix, except for some instructions in intel mode. */
2285 if ((t->opcode_modifier & suffix_check)
2286 && !(intel_syntax
2287 && (t->opcode_modifier & IgnoreSize)))
2288 continue;
2289
2290 /* Do not verify operands when there are none. */
2291 else if (!t->operands)
2292 {
2293 if (t->cpu_flags & ~cpu_arch_flags)
2294 continue;
2295 /* We've found a match; break out of loop. */
2296 break;
2297 }
2298
2299 overlap0 = i.types[0] & t->operand_types[0];
2300 switch (t->operands)
2301 {
2302 case 1:
2303 if (!MATCH (overlap0, i.types[0], t->operand_types[0]))
2304 continue;
2305 break;
2306 case 2:
2307 case 3:
2308 overlap1 = i.types[1] & t->operand_types[1];
2309 if (!MATCH (overlap0, i.types[0], t->operand_types[0])
2310 || !MATCH (overlap1, i.types[1], t->operand_types[1])
2311 /* monitor in SSE3 is a very special case. The first
2312 register and the second register may have differnet
2313 sizes. */
2314 || !((t->base_opcode == 0x0f01
2315 && t->extension_opcode == 0xc8)
2316 || CONSISTENT_REGISTER_MATCH (overlap0, i.types[0],
2317 t->operand_types[0],
2318 overlap1, i.types[1],
2319 t->operand_types[1])))
2320 {
2321 /* Check if other direction is valid ... */
2322 if ((t->opcode_modifier & (D | FloatD)) == 0)
2323 continue;
2324
2325 /* Try reversing direction of operands. */
2326 overlap0 = i.types[0] & t->operand_types[1];
2327 overlap1 = i.types[1] & t->operand_types[0];
2328 if (!MATCH (overlap0, i.types[0], t->operand_types[1])
2329 || !MATCH (overlap1, i.types[1], t->operand_types[0])
2330 || !CONSISTENT_REGISTER_MATCH (overlap0, i.types[0],
2331 t->operand_types[1],
2332 overlap1, i.types[1],
2333 t->operand_types[0]))
2334 {
2335 /* Does not match either direction. */
2336 continue;
2337 }
2338 /* found_reverse_match holds which of D or FloatDR
2339 we've found. */
2340 found_reverse_match = t->opcode_modifier & (D | FloatDR);
2341 }
2342 /* Found a forward 2 operand match here. */
2343 else if (t->operands == 3)
2344 {
2345 /* Here we make use of the fact that there are no
2346 reverse match 3 operand instructions, and all 3
2347 operand instructions only need to be checked for
2348 register consistency between operands 2 and 3. */
2349 overlap2 = i.types[2] & t->operand_types[2];
2350 if (!MATCH (overlap2, i.types[2], t->operand_types[2])
2351 || !CONSISTENT_REGISTER_MATCH (overlap1, i.types[1],
2352 t->operand_types[1],
2353 overlap2, i.types[2],
2354 t->operand_types[2]))
2355
2356 continue;
2357 }
2358 /* Found either forward/reverse 2 or 3 operand match here:
2359 slip through to break. */
2360 }
2361 if (t->cpu_flags & ~cpu_arch_flags)
2362 {
2363 found_reverse_match = 0;
2364 continue;
2365 }
2366 /* We've found a match; break out of loop. */
2367 break;
2368 }
2369
2370 if (t == current_templates->end)
2371 {
2372 /* We found no match. */
2373 as_bad (_("suffix or operands invalid for `%s'"),
2374 current_templates->start->name);
2375 return 0;
2376 }
2377
2378 if (!quiet_warnings)
2379 {
2380 if (!intel_syntax
2381 && ((i.types[0] & JumpAbsolute)
2382 != (t->operand_types[0] & JumpAbsolute)))
2383 {
2384 as_warn (_("indirect %s without `*'"), t->name);
2385 }
2386
2387 if ((t->opcode_modifier & (IsPrefix | IgnoreSize))
2388 == (IsPrefix | IgnoreSize))
2389 {
2390 /* Warn them that a data or address size prefix doesn't
2391 affect assembly of the next line of code. */
2392 as_warn (_("stand-alone `%s' prefix"), t->name);
2393 }
2394 }
2395
2396 /* Copy the template we found. */
2397 i.tm = *t;
2398 if (found_reverse_match)
2399 {
2400 /* If we found a reverse match we must alter the opcode
2401 direction bit. found_reverse_match holds bits to change
2402 (different for int & float insns). */
2403
2404 i.tm.base_opcode ^= found_reverse_match;
2405
2406 i.tm.operand_types[0] = t->operand_types[1];
2407 i.tm.operand_types[1] = t->operand_types[0];
2408 }
2409
2410 return 1;
2411 }
2412
2413 static int
2414 check_string ()
2415 {
2416 int mem_op = (i.types[0] & AnyMem) ? 0 : 1;
2417 if ((i.tm.operand_types[mem_op] & EsSeg) != 0)
2418 {
2419 if (i.seg[0] != NULL && i.seg[0] != &es)
2420 {
2421 as_bad (_("`%s' operand %d must use `%%es' segment"),
2422 i.tm.name,
2423 mem_op + 1);
2424 return 0;
2425 }
2426 /* There's only ever one segment override allowed per instruction.
2427 This instruction possibly has a legal segment override on the
2428 second operand, so copy the segment to where non-string
2429 instructions store it, allowing common code. */
2430 i.seg[0] = i.seg[1];
2431 }
2432 else if ((i.tm.operand_types[mem_op + 1] & EsSeg) != 0)
2433 {
2434 if (i.seg[1] != NULL && i.seg[1] != &es)
2435 {
2436 as_bad (_("`%s' operand %d must use `%%es' segment"),
2437 i.tm.name,
2438 mem_op + 2);
2439 return 0;
2440 }
2441 }
2442 return 1;
2443 }
2444
2445 static int
2446 process_suffix (void)
2447 {
2448 /* If matched instruction specifies an explicit instruction mnemonic
2449 suffix, use it. */
2450 if (i.tm.opcode_modifier & (Size16 | Size32 | Size64))
2451 {
2452 if (i.tm.opcode_modifier & Size16)
2453 i.suffix = WORD_MNEM_SUFFIX;
2454 else if (i.tm.opcode_modifier & Size64)
2455 i.suffix = QWORD_MNEM_SUFFIX;
2456 else
2457 i.suffix = LONG_MNEM_SUFFIX;
2458 }
2459 else if (i.reg_operands)
2460 {
2461 /* If there's no instruction mnemonic suffix we try to invent one
2462 based on register operands. */
2463 if (!i.suffix)
2464 {
2465 /* We take i.suffix from the last register operand specified,
2466 Destination register type is more significant than source
2467 register type. */
2468 int op;
2469
2470 for (op = i.operands; --op >= 0;)
2471 if ((i.types[op] & Reg)
2472 && !(i.tm.operand_types[op] & InOutPortReg))
2473 {
2474 i.suffix = ((i.types[op] & Reg8) ? BYTE_MNEM_SUFFIX :
2475 (i.types[op] & Reg16) ? WORD_MNEM_SUFFIX :
2476 (i.types[op] & Reg64) ? QWORD_MNEM_SUFFIX :
2477 LONG_MNEM_SUFFIX);
2478 break;
2479 }
2480 }
2481 else if (i.suffix == BYTE_MNEM_SUFFIX)
2482 {
2483 if (!check_byte_reg ())
2484 return 0;
2485 }
2486 else if (i.suffix == LONG_MNEM_SUFFIX)
2487 {
2488 if (!check_long_reg ())
2489 return 0;
2490 }
2491 else if (i.suffix == QWORD_MNEM_SUFFIX)
2492 {
2493 if (!check_qword_reg ())
2494 return 0;
2495 }
2496 else if (i.suffix == WORD_MNEM_SUFFIX)
2497 {
2498 if (!check_word_reg ())
2499 return 0;
2500 }
2501 else if (intel_syntax && (i.tm.opcode_modifier & IgnoreSize))
2502 /* Do nothing if the instruction is going to ignore the prefix. */
2503 ;
2504 else
2505 abort ();
2506 }
2507 else if ((i.tm.opcode_modifier & DefaultSize)
2508 && !i.suffix
2509 /* exclude fldenv/frstor/fsave/fstenv */
2510 && (i.tm.opcode_modifier & No_sSuf))
2511 {
2512 i.suffix = stackop_size;
2513 }
2514 else if (intel_syntax
2515 && !i.suffix
2516 && ((i.tm.operand_types[0] & JumpAbsolute)
2517 || (i.tm.opcode_modifier & (JumpByte|JumpInterSegment))
2518 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
2519 && i.tm.extension_opcode <= 3)))
2520 {
2521 switch (flag_code)
2522 {
2523 case CODE_64BIT:
2524 if (!(i.tm.opcode_modifier & No_qSuf))
2525 {
2526 i.suffix = QWORD_MNEM_SUFFIX;
2527 break;
2528 }
2529 case CODE_32BIT:
2530 if (!(i.tm.opcode_modifier & No_lSuf))
2531 i.suffix = LONG_MNEM_SUFFIX;
2532 break;
2533 case CODE_16BIT:
2534 if (!(i.tm.opcode_modifier & No_wSuf))
2535 i.suffix = WORD_MNEM_SUFFIX;
2536 break;
2537 }
2538 }
2539
2540 if (!i.suffix)
2541 {
2542 if (!intel_syntax)
2543 {
2544 if (i.tm.opcode_modifier & W)
2545 {
2546 as_bad (_("no instruction mnemonic suffix given and no register operands; can't size instruction"));
2547 return 0;
2548 }
2549 }
2550 else
2551 {
2552 unsigned int suffixes = ~i.tm.opcode_modifier
2553 & (No_bSuf
2554 | No_wSuf
2555 | No_lSuf
2556 | No_sSuf
2557 | No_xSuf
2558 | No_qSuf);
2559
2560 if ((i.tm.opcode_modifier & W)
2561 || ((suffixes & (suffixes - 1))
2562 && !(i.tm.opcode_modifier & (DefaultSize | IgnoreSize))))
2563 {
2564 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
2565 return 0;
2566 }
2567 }
2568 }
2569
2570 /* Change the opcode based on the operand size given by i.suffix;
2571 We don't need to change things for byte insns. */
2572
2573 if (i.suffix && i.suffix != BYTE_MNEM_SUFFIX)
2574 {
2575 /* It's not a byte, select word/dword operation. */
2576 if (i.tm.opcode_modifier & W)
2577 {
2578 if (i.tm.opcode_modifier & ShortForm)
2579 i.tm.base_opcode |= 8;
2580 else
2581 i.tm.base_opcode |= 1;
2582 }
2583
2584 /* Now select between word & dword operations via the operand
2585 size prefix, except for instructions that will ignore this
2586 prefix anyway. */
2587 if (i.tm.base_opcode == 0x0f01 && i.tm.extension_opcode == 0xc8)
2588 {
2589 /* monitor in SSE3 is a very special case. The default size
2590 of AX is the size of mode. The address size override
2591 prefix will change the size of AX. */
2592 if (i.op->regs[0].reg_type &
2593 (flag_code == CODE_32BIT ? Reg16 : Reg32))
2594 if (!add_prefix (ADDR_PREFIX_OPCODE))
2595 return 0;
2596 }
2597 else if (i.suffix != QWORD_MNEM_SUFFIX
2598 && i.suffix != LONG_DOUBLE_MNEM_SUFFIX
2599 && !(i.tm.opcode_modifier & (IgnoreSize | FloatMF))
2600 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
2601 || (flag_code == CODE_64BIT
2602 && (i.tm.opcode_modifier & JumpByte))))
2603 {
2604 unsigned int prefix = DATA_PREFIX_OPCODE;
2605
2606 if (i.tm.opcode_modifier & JumpByte) /* jcxz, loop */
2607 prefix = ADDR_PREFIX_OPCODE;
2608
2609 if (!add_prefix (prefix))
2610 return 0;
2611 }
2612
2613 /* Set mode64 for an operand. */
2614 if (i.suffix == QWORD_MNEM_SUFFIX
2615 && flag_code == CODE_64BIT
2616 && (i.tm.opcode_modifier & NoRex64) == 0)
2617 i.rex |= REX_MODE64;
2618
2619 /* Size floating point instruction. */
2620 if (i.suffix == LONG_MNEM_SUFFIX)
2621 if (i.tm.opcode_modifier & FloatMF)
2622 i.tm.base_opcode ^= 4;
2623 }
2624
2625 return 1;
2626 }
2627
2628 static int
2629 check_byte_reg (void)
2630 {
2631 int op;
2632
2633 for (op = i.operands; --op >= 0;)
2634 {
2635 /* If this is an eight bit register, it's OK. If it's the 16 or
2636 32 bit version of an eight bit register, we will just use the
2637 low portion, and that's OK too. */
2638 if (i.types[op] & Reg8)
2639 continue;
2640
2641 /* movzx and movsx should not generate this warning. */
2642 if (intel_syntax
2643 && (i.tm.base_opcode == 0xfb7
2644 || i.tm.base_opcode == 0xfb6
2645 || i.tm.base_opcode == 0x63
2646 || i.tm.base_opcode == 0xfbe
2647 || i.tm.base_opcode == 0xfbf))
2648 continue;
2649
2650 if ((i.types[op] & WordReg) && i.op[op].regs->reg_num < 4)
2651 {
2652 /* Prohibit these changes in the 64bit mode, since the
2653 lowering is more complicated. */
2654 if (flag_code == CODE_64BIT
2655 && (i.tm.operand_types[op] & InOutPortReg) == 0)
2656 {
2657 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
2658 i.op[op].regs->reg_name,
2659 i.suffix);
2660 return 0;
2661 }
2662 #if REGISTER_WARNINGS
2663 if (!quiet_warnings
2664 && (i.tm.operand_types[op] & InOutPortReg) == 0)
2665 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2666 (i.op[op].regs + (i.types[op] & Reg16
2667 ? REGNAM_AL - REGNAM_AX
2668 : REGNAM_AL - REGNAM_EAX))->reg_name,
2669 i.op[op].regs->reg_name,
2670 i.suffix);
2671 #endif
2672 continue;
2673 }
2674 /* Any other register is bad. */
2675 if (i.types[op] & (Reg | RegMMX | RegXMM
2676 | SReg2 | SReg3
2677 | Control | Debug | Test
2678 | FloatReg | FloatAcc))
2679 {
2680 as_bad (_("`%%%s' not allowed with `%s%c'"),
2681 i.op[op].regs->reg_name,
2682 i.tm.name,
2683 i.suffix);
2684 return 0;
2685 }
2686 }
2687 return 1;
2688 }
2689
2690 static int
2691 check_long_reg ()
2692 {
2693 int op;
2694
2695 for (op = i.operands; --op >= 0;)
2696 /* Reject eight bit registers, except where the template requires
2697 them. (eg. movzb) */
2698 if ((i.types[op] & Reg8) != 0
2699 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
2700 {
2701 as_bad (_("`%%%s' not allowed with `%s%c'"),
2702 i.op[op].regs->reg_name,
2703 i.tm.name,
2704 i.suffix);
2705 return 0;
2706 }
2707 /* Warn if the e prefix on a general reg is missing. */
2708 else if ((!quiet_warnings || flag_code == CODE_64BIT)
2709 && (i.types[op] & Reg16) != 0
2710 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
2711 {
2712 /* Prohibit these changes in the 64bit mode, since the
2713 lowering is more complicated. */
2714 if (flag_code == CODE_64BIT)
2715 {
2716 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
2717 i.op[op].regs->reg_name,
2718 i.suffix);
2719 return 0;
2720 }
2721 #if REGISTER_WARNINGS
2722 else
2723 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2724 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
2725 i.op[op].regs->reg_name,
2726 i.suffix);
2727 #endif
2728 }
2729 /* Warn if the r prefix on a general reg is missing. */
2730 else if ((i.types[op] & Reg64) != 0
2731 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
2732 {
2733 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
2734 i.op[op].regs->reg_name,
2735 i.suffix);
2736 return 0;
2737 }
2738 return 1;
2739 }
2740
2741 static int
2742 check_qword_reg ()
2743 {
2744 int op;
2745
2746 for (op = i.operands; --op >= 0; )
2747 /* Reject eight bit registers, except where the template requires
2748 them. (eg. movzb) */
2749 if ((i.types[op] & Reg8) != 0
2750 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
2751 {
2752 as_bad (_("`%%%s' not allowed with `%s%c'"),
2753 i.op[op].regs->reg_name,
2754 i.tm.name,
2755 i.suffix);
2756 return 0;
2757 }
2758 /* Warn if the e prefix on a general reg is missing. */
2759 else if (((i.types[op] & Reg16) != 0
2760 || (i.types[op] & Reg32) != 0)
2761 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
2762 {
2763 /* Prohibit these changes in the 64bit mode, since the
2764 lowering is more complicated. */
2765 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
2766 i.op[op].regs->reg_name,
2767 i.suffix);
2768 return 0;
2769 }
2770 return 1;
2771 }
2772
2773 static int
2774 check_word_reg ()
2775 {
2776 int op;
2777 for (op = i.operands; --op >= 0;)
2778 /* Reject eight bit registers, except where the template requires
2779 them. (eg. movzb) */
2780 if ((i.types[op] & Reg8) != 0
2781 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
2782 {
2783 as_bad (_("`%%%s' not allowed with `%s%c'"),
2784 i.op[op].regs->reg_name,
2785 i.tm.name,
2786 i.suffix);
2787 return 0;
2788 }
2789 /* Warn if the e prefix on a general reg is present. */
2790 else if ((!quiet_warnings || flag_code == CODE_64BIT)
2791 && (i.types[op] & Reg32) != 0
2792 && (i.tm.operand_types[op] & (Reg16 | Acc)) != 0)
2793 {
2794 /* Prohibit these changes in the 64bit mode, since the
2795 lowering is more complicated. */
2796 if (flag_code == CODE_64BIT)
2797 {
2798 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
2799 i.op[op].regs->reg_name,
2800 i.suffix);
2801 return 0;
2802 }
2803 else
2804 #if REGISTER_WARNINGS
2805 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2806 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
2807 i.op[op].regs->reg_name,
2808 i.suffix);
2809 #endif
2810 }
2811 return 1;
2812 }
2813
2814 static int
2815 finalize_imm ()
2816 {
2817 unsigned int overlap0, overlap1, overlap2;
2818
2819 overlap0 = i.types[0] & i.tm.operand_types[0];
2820 if ((overlap0 & (Imm8 | Imm8S | Imm16 | Imm32 | Imm32S | Imm64))
2821 && overlap0 != Imm8 && overlap0 != Imm8S
2822 && overlap0 != Imm16 && overlap0 != Imm32S
2823 && overlap0 != Imm32 && overlap0 != Imm64)
2824 {
2825 if (i.suffix)
2826 {
2827 overlap0 &= (i.suffix == BYTE_MNEM_SUFFIX
2828 ? Imm8 | Imm8S
2829 : (i.suffix == WORD_MNEM_SUFFIX
2830 ? Imm16
2831 : (i.suffix == QWORD_MNEM_SUFFIX
2832 ? Imm64 | Imm32S
2833 : Imm32)));
2834 }
2835 else if (overlap0 == (Imm16 | Imm32S | Imm32)
2836 || overlap0 == (Imm16 | Imm32)
2837 || overlap0 == (Imm16 | Imm32S))
2838 {
2839 overlap0 = ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)
2840 ? Imm16 : Imm32S);
2841 }
2842 if (overlap0 != Imm8 && overlap0 != Imm8S
2843 && overlap0 != Imm16 && overlap0 != Imm32S
2844 && overlap0 != Imm32 && overlap0 != Imm64)
2845 {
2846 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size"));
2847 return 0;
2848 }
2849 }
2850 i.types[0] = overlap0;
2851
2852 overlap1 = i.types[1] & i.tm.operand_types[1];
2853 if ((overlap1 & (Imm8 | Imm8S | Imm16 | Imm32S | Imm32 | Imm64))
2854 && overlap1 != Imm8 && overlap1 != Imm8S
2855 && overlap1 != Imm16 && overlap1 != Imm32S
2856 && overlap1 != Imm32 && overlap1 != Imm64)
2857 {
2858 if (i.suffix)
2859 {
2860 overlap1 &= (i.suffix == BYTE_MNEM_SUFFIX
2861 ? Imm8 | Imm8S
2862 : (i.suffix == WORD_MNEM_SUFFIX
2863 ? Imm16
2864 : (i.suffix == QWORD_MNEM_SUFFIX
2865 ? Imm64 | Imm32S
2866 : Imm32)));
2867 }
2868 else if (overlap1 == (Imm16 | Imm32 | Imm32S)
2869 || overlap1 == (Imm16 | Imm32)
2870 || overlap1 == (Imm16 | Imm32S))
2871 {
2872 overlap1 = ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)
2873 ? Imm16 : Imm32S);
2874 }
2875 if (overlap1 != Imm8 && overlap1 != Imm8S
2876 && overlap1 != Imm16 && overlap1 != Imm32S
2877 && overlap1 != Imm32 && overlap1 != Imm64)
2878 {
2879 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size %x %c"),overlap1, i.suffix);
2880 return 0;
2881 }
2882 }
2883 i.types[1] = overlap1;
2884
2885 overlap2 = i.types[2] & i.tm.operand_types[2];
2886 assert ((overlap2 & Imm) == 0);
2887 i.types[2] = overlap2;
2888
2889 return 1;
2890 }
2891
2892 static int
2893 process_operands ()
2894 {
2895 /* Default segment register this instruction will use for memory
2896 accesses. 0 means unknown. This is only for optimizing out
2897 unnecessary segment overrides. */
2898 const seg_entry *default_seg = 0;
2899
2900 /* The imul $imm, %reg instruction is converted into
2901 imul $imm, %reg, %reg, and the clr %reg instruction
2902 is converted into xor %reg, %reg. */
2903 if (i.tm.opcode_modifier & regKludge)
2904 {
2905 unsigned int first_reg_op = (i.types[0] & Reg) ? 0 : 1;
2906 /* Pretend we saw the extra register operand. */
2907 assert (i.op[first_reg_op + 1].regs == 0);
2908 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
2909 i.types[first_reg_op + 1] = i.types[first_reg_op];
2910 i.reg_operands = 2;
2911 }
2912
2913 if (i.tm.opcode_modifier & ShortForm)
2914 {
2915 /* The register or float register operand is in operand 0 or 1. */
2916 unsigned int op = (i.types[0] & (Reg | FloatReg)) ? 0 : 1;
2917 /* Register goes in low 3 bits of opcode. */
2918 i.tm.base_opcode |= i.op[op].regs->reg_num;
2919 if ((i.op[op].regs->reg_flags & RegRex) != 0)
2920 i.rex |= REX_EXTZ;
2921 if (!quiet_warnings && (i.tm.opcode_modifier & Ugh) != 0)
2922 {
2923 /* Warn about some common errors, but press on regardless.
2924 The first case can be generated by gcc (<= 2.8.1). */
2925 if (i.operands == 2)
2926 {
2927 /* Reversed arguments on faddp, fsubp, etc. */
2928 as_warn (_("translating to `%s %%%s,%%%s'"), i.tm.name,
2929 i.op[1].regs->reg_name,
2930 i.op[0].regs->reg_name);
2931 }
2932 else
2933 {
2934 /* Extraneous `l' suffix on fp insn. */
2935 as_warn (_("translating to `%s %%%s'"), i.tm.name,
2936 i.op[0].regs->reg_name);
2937 }
2938 }
2939 }
2940 else if (i.tm.opcode_modifier & Modrm)
2941 {
2942 /* The opcode is completed (modulo i.tm.extension_opcode which
2943 must be put into the modrm byte). Now, we make the modrm and
2944 index base bytes based on all the info we've collected. */
2945
2946 default_seg = build_modrm_byte ();
2947 }
2948 else if (i.tm.opcode_modifier & (Seg2ShortForm | Seg3ShortForm))
2949 {
2950 if (i.tm.base_opcode == POP_SEG_SHORT
2951 && i.op[0].regs->reg_num == 1)
2952 {
2953 as_bad (_("you can't `pop %%cs'"));
2954 return 0;
2955 }
2956 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
2957 if ((i.op[0].regs->reg_flags & RegRex) != 0)
2958 i.rex |= REX_EXTZ;
2959 }
2960 else if ((i.tm.base_opcode & ~(D | W)) == MOV_AX_DISP32)
2961 {
2962 default_seg = &ds;
2963 }
2964 else if ((i.tm.opcode_modifier & IsString) != 0)
2965 {
2966 /* For the string instructions that allow a segment override
2967 on one of their operands, the default segment is ds. */
2968 default_seg = &ds;
2969 }
2970
2971 if ((i.tm.base_opcode == 0x8d /* lea */
2972 || (i.tm.cpu_flags & CpuSVME))
2973 && i.seg[0] && !quiet_warnings)
2974 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
2975
2976 /* If a segment was explicitly specified, and the specified segment
2977 is not the default, use an opcode prefix to select it. If we
2978 never figured out what the default segment is, then default_seg
2979 will be zero at this point, and the specified segment prefix will
2980 always be used. */
2981 if ((i.seg[0]) && (i.seg[0] != default_seg))
2982 {
2983 if (!add_prefix (i.seg[0]->seg_prefix))
2984 return 0;
2985 }
2986 return 1;
2987 }
2988
2989 static const seg_entry *
2990 build_modrm_byte ()
2991 {
2992 const seg_entry *default_seg = 0;
2993
2994 /* i.reg_operands MUST be the number of real register operands;
2995 implicit registers do not count. */
2996 if (i.reg_operands == 2)
2997 {
2998 unsigned int source, dest;
2999 source = ((i.types[0]
3000 & (Reg | RegMMX | RegXMM
3001 | SReg2 | SReg3
3002 | Control | Debug | Test))
3003 ? 0 : 1);
3004 dest = source + 1;
3005
3006 i.rm.mode = 3;
3007 /* One of the register operands will be encoded in the i.tm.reg
3008 field, the other in the combined i.tm.mode and i.tm.regmem
3009 fields. If no form of this instruction supports a memory
3010 destination operand, then we assume the source operand may
3011 sometimes be a memory operand and so we need to store the
3012 destination in the i.rm.reg field. */
3013 if ((i.tm.operand_types[dest] & AnyMem) == 0)
3014 {
3015 i.rm.reg = i.op[dest].regs->reg_num;
3016 i.rm.regmem = i.op[source].regs->reg_num;
3017 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
3018 i.rex |= REX_EXTX;
3019 if ((i.op[source].regs->reg_flags & RegRex) != 0)
3020 i.rex |= REX_EXTZ;
3021 }
3022 else
3023 {
3024 i.rm.reg = i.op[source].regs->reg_num;
3025 i.rm.regmem = i.op[dest].regs->reg_num;
3026 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
3027 i.rex |= REX_EXTZ;
3028 if ((i.op[source].regs->reg_flags & RegRex) != 0)
3029 i.rex |= REX_EXTX;
3030 }
3031 if (flag_code != CODE_64BIT && (i.rex & (REX_EXTX | REX_EXTZ)))
3032 {
3033 if (!((i.types[0] | i.types[1]) & Control))
3034 abort ();
3035 i.rex &= ~(REX_EXTX | REX_EXTZ);
3036 add_prefix (LOCK_PREFIX_OPCODE);
3037 }
3038 }
3039 else
3040 { /* If it's not 2 reg operands... */
3041 if (i.mem_operands)
3042 {
3043 unsigned int fake_zero_displacement = 0;
3044 unsigned int op = ((i.types[0] & AnyMem)
3045 ? 0
3046 : (i.types[1] & AnyMem) ? 1 : 2);
3047
3048 default_seg = &ds;
3049
3050 if (i.base_reg == 0)
3051 {
3052 i.rm.mode = 0;
3053 if (!i.disp_operands)
3054 fake_zero_displacement = 1;
3055 if (i.index_reg == 0)
3056 {
3057 /* Operand is just <disp> */
3058 if (flag_code == CODE_64BIT)
3059 {
3060 /* 64bit mode overwrites the 32bit absolute
3061 addressing by RIP relative addressing and
3062 absolute addressing is encoded by one of the
3063 redundant SIB forms. */
3064 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
3065 i.sib.base = NO_BASE_REGISTER;
3066 i.sib.index = NO_INDEX_REGISTER;
3067 i.types[op] = ((i.prefix[ADDR_PREFIX] == 0) ? Disp32S : Disp32);
3068 }
3069 else if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
3070 {
3071 i.rm.regmem = NO_BASE_REGISTER_16;
3072 i.types[op] = Disp16;
3073 }
3074 else
3075 {
3076 i.rm.regmem = NO_BASE_REGISTER;
3077 i.types[op] = Disp32;
3078 }
3079 }
3080 else /* !i.base_reg && i.index_reg */
3081 {
3082 i.sib.index = i.index_reg->reg_num;
3083 i.sib.base = NO_BASE_REGISTER;
3084 i.sib.scale = i.log2_scale_factor;
3085 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
3086 i.types[op] &= ~Disp;
3087 if (flag_code != CODE_64BIT)
3088 i.types[op] |= Disp32; /* Must be 32 bit */
3089 else
3090 i.types[op] |= Disp32S;
3091 if ((i.index_reg->reg_flags & RegRex) != 0)
3092 i.rex |= REX_EXTY;
3093 }
3094 }
3095 /* RIP addressing for 64bit mode. */
3096 else if (i.base_reg->reg_type == BaseIndex)
3097 {
3098 i.rm.regmem = NO_BASE_REGISTER;
3099 i.types[op] &= ~ Disp;
3100 i.types[op] |= Disp32S;
3101 i.flags[op] = Operand_PCrel;
3102 if (! i.disp_operands)
3103 fake_zero_displacement = 1;
3104 }
3105 else if (i.base_reg->reg_type & Reg16)
3106 {
3107 switch (i.base_reg->reg_num)
3108 {
3109 case 3: /* (%bx) */
3110 if (i.index_reg == 0)
3111 i.rm.regmem = 7;
3112 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
3113 i.rm.regmem = i.index_reg->reg_num - 6;
3114 break;
3115 case 5: /* (%bp) */
3116 default_seg = &ss;
3117 if (i.index_reg == 0)
3118 {
3119 i.rm.regmem = 6;
3120 if ((i.types[op] & Disp) == 0)
3121 {
3122 /* fake (%bp) into 0(%bp) */
3123 i.types[op] |= Disp8;
3124 fake_zero_displacement = 1;
3125 }
3126 }
3127 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
3128 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
3129 break;
3130 default: /* (%si) -> 4 or (%di) -> 5 */
3131 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
3132 }
3133 i.rm.mode = mode_from_disp_size (i.types[op]);
3134 }
3135 else /* i.base_reg and 32/64 bit mode */
3136 {
3137 if (flag_code == CODE_64BIT
3138 && (i.types[op] & Disp))
3139 i.types[op] = (i.types[op] & Disp8) | (i.prefix[ADDR_PREFIX] == 0 ? Disp32S : Disp32);
3140
3141 i.rm.regmem = i.base_reg->reg_num;
3142 if ((i.base_reg->reg_flags & RegRex) != 0)
3143 i.rex |= REX_EXTZ;
3144 i.sib.base = i.base_reg->reg_num;
3145 /* x86-64 ignores REX prefix bit here to avoid decoder
3146 complications. */
3147 if ((i.base_reg->reg_num & 7) == EBP_REG_NUM)
3148 {
3149 default_seg = &ss;
3150 if (i.disp_operands == 0)
3151 {
3152 fake_zero_displacement = 1;
3153 i.types[op] |= Disp8;
3154 }
3155 }
3156 else if (i.base_reg->reg_num == ESP_REG_NUM)
3157 {
3158 default_seg = &ss;
3159 }
3160 i.sib.scale = i.log2_scale_factor;
3161 if (i.index_reg == 0)
3162 {
3163 /* <disp>(%esp) becomes two byte modrm with no index
3164 register. We've already stored the code for esp
3165 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
3166 Any base register besides %esp will not use the
3167 extra modrm byte. */
3168 i.sib.index = NO_INDEX_REGISTER;
3169 #if !SCALE1_WHEN_NO_INDEX
3170 /* Another case where we force the second modrm byte. */
3171 if (i.log2_scale_factor)
3172 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
3173 #endif
3174 }
3175 else
3176 {
3177 i.sib.index = i.index_reg->reg_num;
3178 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
3179 if ((i.index_reg->reg_flags & RegRex) != 0)
3180 i.rex |= REX_EXTY;
3181 }
3182
3183 if (i.disp_operands
3184 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
3185 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
3186 i.rm.mode = 0;
3187 else
3188 i.rm.mode = mode_from_disp_size (i.types[op]);
3189 }
3190
3191 if (fake_zero_displacement)
3192 {
3193 /* Fakes a zero displacement assuming that i.types[op]
3194 holds the correct displacement size. */
3195 expressionS *exp;
3196
3197 assert (i.op[op].disps == 0);
3198 exp = &disp_expressions[i.disp_operands++];
3199 i.op[op].disps = exp;
3200 exp->X_op = O_constant;
3201 exp->X_add_number = 0;
3202 exp->X_add_symbol = (symbolS *) 0;
3203 exp->X_op_symbol = (symbolS *) 0;
3204 }
3205 }
3206
3207 /* Fill in i.rm.reg or i.rm.regmem field with register operand
3208 (if any) based on i.tm.extension_opcode. Again, we must be
3209 careful to make sure that segment/control/debug/test/MMX
3210 registers are coded into the i.rm.reg field. */
3211 if (i.reg_operands)
3212 {
3213 unsigned int op =
3214 ((i.types[0]
3215 & (Reg | RegMMX | RegXMM
3216 | SReg2 | SReg3
3217 | Control | Debug | Test))
3218 ? 0
3219 : ((i.types[1]
3220 & (Reg | RegMMX | RegXMM
3221 | SReg2 | SReg3
3222 | Control | Debug | Test))
3223 ? 1
3224 : 2));
3225 /* If there is an extension opcode to put here, the register
3226 number must be put into the regmem field. */
3227 if (i.tm.extension_opcode != None)
3228 {
3229 i.rm.regmem = i.op[op].regs->reg_num;
3230 if ((i.op[op].regs->reg_flags & RegRex) != 0)
3231 i.rex |= REX_EXTZ;
3232 }
3233 else
3234 {
3235 i.rm.reg = i.op[op].regs->reg_num;
3236 if ((i.op[op].regs->reg_flags & RegRex) != 0)
3237 i.rex |= REX_EXTX;
3238 }
3239
3240 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
3241 must set it to 3 to indicate this is a register operand
3242 in the regmem field. */
3243 if (!i.mem_operands)
3244 i.rm.mode = 3;
3245 }
3246
3247 /* Fill in i.rm.reg field with extension opcode (if any). */
3248 if (i.tm.extension_opcode != None)
3249 i.rm.reg = i.tm.extension_opcode;
3250 }
3251 return default_seg;
3252 }
3253
3254 static void
3255 output_branch ()
3256 {
3257 char *p;
3258 int code16;
3259 int prefix;
3260 relax_substateT subtype;
3261 symbolS *sym;
3262 offsetT off;
3263
3264 code16 = 0;
3265 if (flag_code == CODE_16BIT)
3266 code16 = CODE16;
3267
3268 prefix = 0;
3269 if (i.prefix[DATA_PREFIX] != 0)
3270 {
3271 prefix = 1;
3272 i.prefixes -= 1;
3273 code16 ^= CODE16;
3274 }
3275 /* Pentium4 branch hints. */
3276 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
3277 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
3278 {
3279 prefix++;
3280 i.prefixes--;
3281 }
3282 if (i.prefix[REX_PREFIX] != 0)
3283 {
3284 prefix++;
3285 i.prefixes--;
3286 }
3287
3288 if (i.prefixes != 0 && !intel_syntax)
3289 as_warn (_("skipping prefixes on this instruction"));
3290
3291 /* It's always a symbol; End frag & setup for relax.
3292 Make sure there is enough room in this frag for the largest
3293 instruction we may generate in md_convert_frag. This is 2
3294 bytes for the opcode and room for the prefix and largest
3295 displacement. */
3296 frag_grow (prefix + 2 + 4);
3297 /* Prefix and 1 opcode byte go in fr_fix. */
3298 p = frag_more (prefix + 1);
3299 if (i.prefix[DATA_PREFIX] != 0)
3300 *p++ = DATA_PREFIX_OPCODE;
3301 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
3302 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
3303 *p++ = i.prefix[SEG_PREFIX];
3304 if (i.prefix[REX_PREFIX] != 0)
3305 *p++ = i.prefix[REX_PREFIX];
3306 *p = i.tm.base_opcode;
3307
3308 if ((unsigned char) *p == JUMP_PC_RELATIVE)
3309 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL);
3310 else if ((cpu_arch_flags & Cpu386) != 0)
3311 subtype = ENCODE_RELAX_STATE (COND_JUMP, SMALL);
3312 else
3313 subtype = ENCODE_RELAX_STATE (COND_JUMP86, SMALL);
3314 subtype |= code16;
3315
3316 sym = i.op[0].disps->X_add_symbol;
3317 off = i.op[0].disps->X_add_number;
3318
3319 if (i.op[0].disps->X_op != O_constant
3320 && i.op[0].disps->X_op != O_symbol)
3321 {
3322 /* Handle complex expressions. */
3323 sym = make_expr_symbol (i.op[0].disps);
3324 off = 0;
3325 }
3326
3327 /* 1 possible extra opcode + 4 byte displacement go in var part.
3328 Pass reloc in fr_var. */
3329 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
3330 }
3331
3332 static void
3333 output_jump ()
3334 {
3335 char *p;
3336 int size;
3337 fixS *fixP;
3338
3339 if (i.tm.opcode_modifier & JumpByte)
3340 {
3341 /* This is a loop or jecxz type instruction. */
3342 size = 1;
3343 if (i.prefix[ADDR_PREFIX] != 0)
3344 {
3345 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
3346 i.prefixes -= 1;
3347 }
3348 /* Pentium4 branch hints. */
3349 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
3350 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
3351 {
3352 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
3353 i.prefixes--;
3354 }
3355 }
3356 else
3357 {
3358 int code16;
3359
3360 code16 = 0;
3361 if (flag_code == CODE_16BIT)
3362 code16 = CODE16;
3363
3364 if (i.prefix[DATA_PREFIX] != 0)
3365 {
3366 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
3367 i.prefixes -= 1;
3368 code16 ^= CODE16;
3369 }
3370
3371 size = 4;
3372 if (code16)
3373 size = 2;
3374 }
3375
3376 if (i.prefix[REX_PREFIX] != 0)
3377 {
3378 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
3379 i.prefixes -= 1;
3380 }
3381
3382 if (i.prefixes != 0 && !intel_syntax)
3383 as_warn (_("skipping prefixes on this instruction"));
3384
3385 p = frag_more (1 + size);
3386 *p++ = i.tm.base_opcode;
3387
3388 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
3389 i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0]));
3390
3391 /* All jumps handled here are signed, but don't use a signed limit
3392 check for 32 and 16 bit jumps as we want to allow wrap around at
3393 4G and 64k respectively. */
3394 if (size == 1)
3395 fixP->fx_signed = 1;
3396 }
3397
3398 static void
3399 output_interseg_jump ()
3400 {
3401 char *p;
3402 int size;
3403 int prefix;
3404 int code16;
3405
3406 code16 = 0;
3407 if (flag_code == CODE_16BIT)
3408 code16 = CODE16;
3409
3410 prefix = 0;
3411 if (i.prefix[DATA_PREFIX] != 0)
3412 {
3413 prefix = 1;
3414 i.prefixes -= 1;
3415 code16 ^= CODE16;
3416 }
3417 if (i.prefix[REX_PREFIX] != 0)
3418 {
3419 prefix++;
3420 i.prefixes -= 1;
3421 }
3422
3423 size = 4;
3424 if (code16)
3425 size = 2;
3426
3427 if (i.prefixes != 0 && !intel_syntax)
3428 as_warn (_("skipping prefixes on this instruction"));
3429
3430 /* 1 opcode; 2 segment; offset */
3431 p = frag_more (prefix + 1 + 2 + size);
3432
3433 if (i.prefix[DATA_PREFIX] != 0)
3434 *p++ = DATA_PREFIX_OPCODE;
3435
3436 if (i.prefix[REX_PREFIX] != 0)
3437 *p++ = i.prefix[REX_PREFIX];
3438
3439 *p++ = i.tm.base_opcode;
3440 if (i.op[1].imms->X_op == O_constant)
3441 {
3442 offsetT n = i.op[1].imms->X_add_number;
3443
3444 if (size == 2
3445 && !fits_in_unsigned_word (n)
3446 && !fits_in_signed_word (n))
3447 {
3448 as_bad (_("16-bit jump out of range"));
3449 return;
3450 }
3451 md_number_to_chars (p, n, size);
3452 }
3453 else
3454 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
3455 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
3456 if (i.op[0].imms->X_op != O_constant)
3457 as_bad (_("can't handle non absolute segment in `%s'"),
3458 i.tm.name);
3459 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
3460 }
3461
3462 static void
3463 output_insn ()
3464 {
3465 fragS *insn_start_frag;
3466 offsetT insn_start_off;
3467
3468 /* Tie dwarf2 debug info to the address at the start of the insn.
3469 We can't do this after the insn has been output as the current
3470 frag may have been closed off. eg. by frag_var. */
3471 dwarf2_emit_insn (0);
3472
3473 insn_start_frag = frag_now;
3474 insn_start_off = frag_now_fix ();
3475
3476 /* Output jumps. */
3477 if (i.tm.opcode_modifier & Jump)
3478 output_branch ();
3479 else if (i.tm.opcode_modifier & (JumpByte | JumpDword))
3480 output_jump ();
3481 else if (i.tm.opcode_modifier & JumpInterSegment)
3482 output_interseg_jump ();
3483 else
3484 {
3485 /* Output normal instructions here. */
3486 char *p;
3487 unsigned char *q;
3488 unsigned int prefix;
3489
3490 /* All opcodes on i386 have either 1 or 2 bytes. Merom New
3491 Instructions have 3 bytes. We may use one more higher byte
3492 to specify a prefix the instruction requires. */
3493 if ((i.tm.cpu_flags & CpuMNI) != 0)
3494 {
3495 if (i.tm.base_opcode & 0xff000000)
3496 {
3497 prefix = (i.tm.base_opcode >> 24) & 0xff;
3498 goto check_prefix;
3499 }
3500 }
3501 else if ((i.tm.base_opcode & 0xff0000) != 0)
3502 {
3503 prefix = (i.tm.base_opcode >> 16) & 0xff;
3504 if ((i.tm.cpu_flags & CpuPadLock) != 0)
3505 {
3506 check_prefix:
3507 if (prefix != REPE_PREFIX_OPCODE
3508 || i.prefix[LOCKREP_PREFIX] != REPE_PREFIX_OPCODE)
3509 add_prefix (prefix);
3510 }
3511 else
3512 add_prefix (prefix);
3513 }
3514
3515 /* The prefix bytes. */
3516 for (q = i.prefix;
3517 q < i.prefix + sizeof (i.prefix) / sizeof (i.prefix[0]);
3518 q++)
3519 {
3520 if (*q)
3521 {
3522 p = frag_more (1);
3523 md_number_to_chars (p, (valueT) *q, 1);
3524 }
3525 }
3526
3527 /* Now the opcode; be careful about word order here! */
3528 if (fits_in_unsigned_byte (i.tm.base_opcode))
3529 {
3530 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
3531 }
3532 else
3533 {
3534 if ((i.tm.cpu_flags & CpuMNI) != 0)
3535 {
3536 p = frag_more (3);
3537 *p++ = (i.tm.base_opcode >> 16) & 0xff;
3538 }
3539 else
3540 p = frag_more (2);
3541
3542 /* Put out high byte first: can't use md_number_to_chars! */
3543 *p++ = (i.tm.base_opcode >> 8) & 0xff;
3544 *p = i.tm.base_opcode & 0xff;
3545 }
3546
3547 /* Now the modrm byte and sib byte (if present). */
3548 if (i.tm.opcode_modifier & Modrm)
3549 {
3550 p = frag_more (1);
3551 md_number_to_chars (p,
3552 (valueT) (i.rm.regmem << 0
3553 | i.rm.reg << 3
3554 | i.rm.mode << 6),
3555 1);
3556 /* If i.rm.regmem == ESP (4)
3557 && i.rm.mode != (Register mode)
3558 && not 16 bit
3559 ==> need second modrm byte. */
3560 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
3561 && i.rm.mode != 3
3562 && !(i.base_reg && (i.base_reg->reg_type & Reg16) != 0))
3563 {
3564 p = frag_more (1);
3565 md_number_to_chars (p,
3566 (valueT) (i.sib.base << 0
3567 | i.sib.index << 3
3568 | i.sib.scale << 6),
3569 1);
3570 }
3571 }
3572
3573 if (i.disp_operands)
3574 output_disp (insn_start_frag, insn_start_off);
3575
3576 if (i.imm_operands)
3577 output_imm (insn_start_frag, insn_start_off);
3578 }
3579
3580 #ifdef DEBUG386
3581 if (flag_debug)
3582 {
3583 pi ("" /*line*/, &i);
3584 }
3585 #endif /* DEBUG386 */
3586 }
3587
3588 static void
3589 output_disp (insn_start_frag, insn_start_off)
3590 fragS *insn_start_frag;
3591 offsetT insn_start_off;
3592 {
3593 char *p;
3594 unsigned int n;
3595
3596 for (n = 0; n < i.operands; n++)
3597 {
3598 if (i.types[n] & Disp)
3599 {
3600 if (i.op[n].disps->X_op == O_constant)
3601 {
3602 int size;
3603 offsetT val;
3604
3605 size = 4;
3606 if (i.types[n] & (Disp8 | Disp16 | Disp64))
3607 {
3608 size = 2;
3609 if (i.types[n] & Disp8)
3610 size = 1;
3611 if (i.types[n] & Disp64)
3612 size = 8;
3613 }
3614 val = offset_in_range (i.op[n].disps->X_add_number,
3615 size);
3616 p = frag_more (size);
3617 md_number_to_chars (p, val, size);
3618 }
3619 else
3620 {
3621 enum bfd_reloc_code_real reloc_type;
3622 int size = 4;
3623 int sign = 0;
3624 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
3625
3626 /* The PC relative address is computed relative
3627 to the instruction boundary, so in case immediate
3628 fields follows, we need to adjust the value. */
3629 if (pcrel && i.imm_operands)
3630 {
3631 int imm_size = 4;
3632 unsigned int n1;
3633
3634 for (n1 = 0; n1 < i.operands; n1++)
3635 if (i.types[n1] & Imm)
3636 {
3637 if (i.types[n1] & (Imm8 | Imm8S | Imm16 | Imm64))
3638 {
3639 imm_size = 2;
3640 if (i.types[n1] & (Imm8 | Imm8S))
3641 imm_size = 1;
3642 if (i.types[n1] & Imm64)
3643 imm_size = 8;
3644 }
3645 break;
3646 }
3647 /* We should find the immediate. */
3648 if (n1 == i.operands)
3649 abort ();
3650 i.op[n].disps->X_add_number -= imm_size;
3651 }
3652
3653 if (i.types[n] & Disp32S)
3654 sign = 1;
3655
3656 if (i.types[n] & (Disp16 | Disp64))
3657 {
3658 size = 2;
3659 if (i.types[n] & Disp64)
3660 size = 8;
3661 }
3662
3663 p = frag_more (size);
3664 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
3665 if (GOT_symbol
3666 && GOT_symbol == i.op[n].disps->X_add_symbol
3667 && (((reloc_type == BFD_RELOC_32
3668 || reloc_type == BFD_RELOC_X86_64_32S
3669 || (reloc_type == BFD_RELOC_64
3670 && object_64bit))
3671 && (i.op[n].disps->X_op == O_symbol
3672 || (i.op[n].disps->X_op == O_add
3673 && ((symbol_get_value_expression
3674 (i.op[n].disps->X_op_symbol)->X_op)
3675 == O_subtract))))
3676 || reloc_type == BFD_RELOC_32_PCREL))
3677 {
3678 offsetT add;
3679
3680 if (insn_start_frag == frag_now)
3681 add = (p - frag_now->fr_literal) - insn_start_off;
3682 else
3683 {
3684 fragS *fr;
3685
3686 add = insn_start_frag->fr_fix - insn_start_off;
3687 for (fr = insn_start_frag->fr_next;
3688 fr && fr != frag_now; fr = fr->fr_next)
3689 add += fr->fr_fix;
3690 add += p - frag_now->fr_literal;
3691 }
3692
3693 if (!object_64bit)
3694 {
3695 reloc_type = BFD_RELOC_386_GOTPC;
3696 i.op[n].imms->X_add_number += add;
3697 }
3698 else if (reloc_type == BFD_RELOC_64)
3699 reloc_type = BFD_RELOC_X86_64_GOTPC64;
3700 else
3701 /* Don't do the adjustment for x86-64, as there
3702 the pcrel addressing is relative to the _next_
3703 insn, and that is taken care of in other code. */
3704 reloc_type = BFD_RELOC_X86_64_GOTPC32;
3705 }
3706 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
3707 i.op[n].disps, pcrel, reloc_type);
3708 }
3709 }
3710 }
3711 }
3712
3713 static void
3714 output_imm (insn_start_frag, insn_start_off)
3715 fragS *insn_start_frag;
3716 offsetT insn_start_off;
3717 {
3718 char *p;
3719 unsigned int n;
3720
3721 for (n = 0; n < i.operands; n++)
3722 {
3723 if (i.types[n] & Imm)
3724 {
3725 if (i.op[n].imms->X_op == O_constant)
3726 {
3727 int size;
3728 offsetT val;
3729
3730 size = 4;
3731 if (i.types[n] & (Imm8 | Imm8S | Imm16 | Imm64))
3732 {
3733 size = 2;
3734 if (i.types[n] & (Imm8 | Imm8S))
3735 size = 1;
3736 else if (i.types[n] & Imm64)
3737 size = 8;
3738 }
3739 val = offset_in_range (i.op[n].imms->X_add_number,
3740 size);
3741 p = frag_more (size);
3742 md_number_to_chars (p, val, size);
3743 }
3744 else
3745 {
3746 /* Not absolute_section.
3747 Need a 32-bit fixup (don't support 8bit
3748 non-absolute imms). Try to support other
3749 sizes ... */
3750 enum bfd_reloc_code_real reloc_type;
3751 int size = 4;
3752 int sign = 0;
3753
3754 if ((i.types[n] & (Imm32S))
3755 && (i.suffix == QWORD_MNEM_SUFFIX
3756 || (!i.suffix && (i.tm.opcode_modifier & No_lSuf))))
3757 sign = 1;
3758 if (i.types[n] & (Imm8 | Imm8S | Imm16 | Imm64))
3759 {
3760 size = 2;
3761 if (i.types[n] & (Imm8 | Imm8S))
3762 size = 1;
3763 if (i.types[n] & Imm64)
3764 size = 8;
3765 }
3766
3767 p = frag_more (size);
3768 reloc_type = reloc (size, 0, sign, i.reloc[n]);
3769
3770 /* This is tough to explain. We end up with this one if we
3771 * have operands that look like
3772 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
3773 * obtain the absolute address of the GOT, and it is strongly
3774 * preferable from a performance point of view to avoid using
3775 * a runtime relocation for this. The actual sequence of
3776 * instructions often look something like:
3777 *
3778 * call .L66
3779 * .L66:
3780 * popl %ebx
3781 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
3782 *
3783 * The call and pop essentially return the absolute address
3784 * of the label .L66 and store it in %ebx. The linker itself
3785 * will ultimately change the first operand of the addl so
3786 * that %ebx points to the GOT, but to keep things simple, the
3787 * .o file must have this operand set so that it generates not
3788 * the absolute address of .L66, but the absolute address of
3789 * itself. This allows the linker itself simply treat a GOTPC
3790 * relocation as asking for a pcrel offset to the GOT to be
3791 * added in, and the addend of the relocation is stored in the
3792 * operand field for the instruction itself.
3793 *
3794 * Our job here is to fix the operand so that it would add
3795 * the correct offset so that %ebx would point to itself. The
3796 * thing that is tricky is that .-.L66 will point to the
3797 * beginning of the instruction, so we need to further modify
3798 * the operand so that it will point to itself. There are
3799 * other cases where you have something like:
3800 *
3801 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
3802 *
3803 * and here no correction would be required. Internally in
3804 * the assembler we treat operands of this form as not being
3805 * pcrel since the '.' is explicitly mentioned, and I wonder
3806 * whether it would simplify matters to do it this way. Who
3807 * knows. In earlier versions of the PIC patches, the
3808 * pcrel_adjust field was used to store the correction, but
3809 * since the expression is not pcrel, I felt it would be
3810 * confusing to do it this way. */
3811
3812 if ((reloc_type == BFD_RELOC_32
3813 || reloc_type == BFD_RELOC_X86_64_32S
3814 || reloc_type == BFD_RELOC_64)
3815 && GOT_symbol
3816 && GOT_symbol == i.op[n].imms->X_add_symbol
3817 && (i.op[n].imms->X_op == O_symbol
3818 || (i.op[n].imms->X_op == O_add
3819 && ((symbol_get_value_expression
3820 (i.op[n].imms->X_op_symbol)->X_op)
3821 == O_subtract))))
3822 {
3823 offsetT add;
3824
3825 if (insn_start_frag == frag_now)
3826 add = (p - frag_now->fr_literal) - insn_start_off;
3827 else
3828 {
3829 fragS *fr;
3830
3831 add = insn_start_frag->fr_fix - insn_start_off;
3832 for (fr = insn_start_frag->fr_next;
3833 fr && fr != frag_now; fr = fr->fr_next)
3834 add += fr->fr_fix;
3835 add += p - frag_now->fr_literal;
3836 }
3837
3838 if (!object_64bit)
3839 reloc_type = BFD_RELOC_386_GOTPC;
3840 else if (size == 4)
3841 reloc_type = BFD_RELOC_X86_64_GOTPC32;
3842 else if (size == 8)
3843 reloc_type = BFD_RELOC_X86_64_GOTPC64;
3844 i.op[n].imms->X_add_number += add;
3845 }
3846 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
3847 i.op[n].imms, 0, reloc_type);
3848 }
3849 }
3850 }
3851 }
3852 \f
3853 /* x86_cons_fix_new is called via the expression parsing code when a
3854 reloc is needed. We use this hook to get the correct .got reloc. */
3855 static enum bfd_reloc_code_real got_reloc = NO_RELOC;
3856 static int cons_sign = -1;
3857
3858 void
3859 x86_cons_fix_new (fragS *frag,
3860 unsigned int off,
3861 unsigned int len,
3862 expressionS *exp)
3863 {
3864 enum bfd_reloc_code_real r = reloc (len, 0, cons_sign, got_reloc);
3865
3866 got_reloc = NO_RELOC;
3867
3868 #ifdef TE_PE
3869 if (exp->X_op == O_secrel)
3870 {
3871 exp->X_op = O_symbol;
3872 r = BFD_RELOC_32_SECREL;
3873 }
3874 #endif
3875
3876 fix_new_exp (frag, off, len, exp, 0, r);
3877 }
3878
3879 #if (!defined (OBJ_ELF) && !defined (OBJ_MAYBE_ELF)) || defined (LEX_AT)
3880 # define lex_got(reloc, adjust, types) NULL
3881 #else
3882 /* Parse operands of the form
3883 <symbol>@GOTOFF+<nnn>
3884 and similar .plt or .got references.
3885
3886 If we find one, set up the correct relocation in RELOC and copy the
3887 input string, minus the `@GOTOFF' into a malloc'd buffer for
3888 parsing by the calling routine. Return this buffer, and if ADJUST
3889 is non-null set it to the length of the string we removed from the
3890 input line. Otherwise return NULL. */
3891 static char *
3892 lex_got (enum bfd_reloc_code_real *reloc,
3893 int *adjust,
3894 unsigned int *types)
3895 {
3896 /* Some of the relocations depend on the size of what field is to
3897 be relocated. But in our callers i386_immediate and i386_displacement
3898 we don't yet know the operand size (this will be set by insn
3899 matching). Hence we record the word32 relocation here,
3900 and adjust the reloc according to the real size in reloc(). */
3901 static const struct {
3902 const char *str;
3903 const enum bfd_reloc_code_real rel[2];
3904 const unsigned int types64;
3905 } gotrel[] = {
3906 { "PLTOFF", { 0, BFD_RELOC_X86_64_PLTOFF64 }, Imm64 },
3907 { "PLT", { BFD_RELOC_386_PLT32, BFD_RELOC_X86_64_PLT32 }, Imm32|Imm32S|Disp32 },
3908 { "GOTPLT", { 0, BFD_RELOC_X86_64_GOTPLT64 }, Imm64|Disp64 },
3909 { "GOTOFF", { BFD_RELOC_386_GOTOFF, BFD_RELOC_X86_64_GOTOFF64 }, Imm64|Disp64 },
3910 { "GOTPCREL", { 0, BFD_RELOC_X86_64_GOTPCREL }, Imm32|Imm32S|Disp32 },
3911 { "TLSGD", { BFD_RELOC_386_TLS_GD, BFD_RELOC_X86_64_TLSGD }, Imm32|Imm32S|Disp32 },
3912 { "TLSLDM", { BFD_RELOC_386_TLS_LDM, 0 }, 0 },
3913 { "TLSLD", { 0, BFD_RELOC_X86_64_TLSLD }, Imm32|Imm32S|Disp32 },
3914 { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32, BFD_RELOC_X86_64_GOTTPOFF }, Imm32|Imm32S|Disp32 },
3915 { "TPOFF", { BFD_RELOC_386_TLS_LE_32, BFD_RELOC_X86_64_TPOFF32 }, Imm32|Imm32S|Imm64|Disp32|Disp64 },
3916 { "NTPOFF", { BFD_RELOC_386_TLS_LE, 0 }, 0 },
3917 { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32, BFD_RELOC_X86_64_DTPOFF32 }, Imm32|Imm32S|Imm64|Disp32|Disp64 },
3918 { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE, 0 }, 0 },
3919 { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE, 0 }, 0 },
3920 { "GOT", { BFD_RELOC_386_GOT32, BFD_RELOC_X86_64_GOT32 }, Imm32|Imm32S|Disp32|Imm64 },
3921 { "TLSDESC", { BFD_RELOC_386_TLS_GOTDESC, BFD_RELOC_X86_64_GOTPC32_TLSDESC }, Imm32|Imm32S|Disp32 },
3922 { "TLSCALL", { BFD_RELOC_386_TLS_DESC_CALL, BFD_RELOC_X86_64_TLSDESC_CALL }, Imm32|Imm32S|Disp32 }
3923 };
3924 char *cp;
3925 unsigned int j;
3926
3927 if (!IS_ELF)
3928 return NULL;
3929
3930 for (cp = input_line_pointer; *cp != '@'; cp++)
3931 if (is_end_of_line[(unsigned char) *cp])
3932 return NULL;
3933
3934 for (j = 0; j < sizeof (gotrel) / sizeof (gotrel[0]); j++)
3935 {
3936 int len;
3937
3938 len = strlen (gotrel[j].str);
3939 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
3940 {
3941 if (gotrel[j].rel[object_64bit] != 0)
3942 {
3943 int first, second;
3944 char *tmpbuf, *past_reloc;
3945
3946 *reloc = gotrel[j].rel[object_64bit];
3947 if (adjust)
3948 *adjust = len;
3949
3950 if (types)
3951 {
3952 if (flag_code != CODE_64BIT)
3953 *types = Imm32|Disp32;
3954 else
3955 *types = gotrel[j].types64;
3956 }
3957
3958 if (GOT_symbol == NULL)
3959 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
3960
3961 /* Replace the relocation token with ' ', so that
3962 errors like foo@GOTOFF1 will be detected. */
3963
3964 /* The length of the first part of our input line. */
3965 first = cp - input_line_pointer;
3966
3967 /* The second part goes from after the reloc token until
3968 (and including) an end_of_line char. Don't use strlen
3969 here as the end_of_line char may not be a NUL. */
3970 past_reloc = cp + 1 + len;
3971 for (cp = past_reloc; !is_end_of_line[(unsigned char) *cp++]; )
3972 ;
3973 second = cp - past_reloc;
3974
3975 /* Allocate and copy string. The trailing NUL shouldn't
3976 be necessary, but be safe. */
3977 tmpbuf = xmalloc (first + second + 2);
3978 memcpy (tmpbuf, input_line_pointer, first);
3979 tmpbuf[first] = ' ';
3980 memcpy (tmpbuf + first + 1, past_reloc, second);
3981 tmpbuf[first + second + 1] = '\0';
3982 return tmpbuf;
3983 }
3984
3985 as_bad (_("@%s reloc is not supported with %d-bit output format"),
3986 gotrel[j].str, 1 << (5 + object_64bit));
3987 return NULL;
3988 }
3989 }
3990
3991 /* Might be a symbol version string. Don't as_bad here. */
3992 return NULL;
3993 }
3994
3995 void
3996 x86_cons (exp, size)
3997 expressionS *exp;
3998 int size;
3999 {
4000 if (size == 4 || (object_64bit && size == 8))
4001 {
4002 /* Handle @GOTOFF and the like in an expression. */
4003 char *save;
4004 char *gotfree_input_line;
4005 int adjust;
4006
4007 save = input_line_pointer;
4008 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
4009 if (gotfree_input_line)
4010 input_line_pointer = gotfree_input_line;
4011
4012 expression (exp);
4013
4014 if (gotfree_input_line)
4015 {
4016 /* expression () has merrily parsed up to the end of line,
4017 or a comma - in the wrong buffer. Transfer how far
4018 input_line_pointer has moved to the right buffer. */
4019 input_line_pointer = (save
4020 + (input_line_pointer - gotfree_input_line)
4021 + adjust);
4022 free (gotfree_input_line);
4023 }
4024 }
4025 else
4026 expression (exp);
4027 }
4028 #endif
4029
4030 static void signed_cons (int size)
4031 {
4032 if (flag_code == CODE_64BIT)
4033 cons_sign = 1;
4034 cons (size);
4035 cons_sign = -1;
4036 }
4037
4038 #ifdef TE_PE
4039 static void
4040 pe_directive_secrel (dummy)
4041 int dummy ATTRIBUTE_UNUSED;
4042 {
4043 expressionS exp;
4044
4045 do
4046 {
4047 expression (&exp);
4048 if (exp.X_op == O_symbol)
4049 exp.X_op = O_secrel;
4050
4051 emit_expr (&exp, 4);
4052 }
4053 while (*input_line_pointer++ == ',');
4054
4055 input_line_pointer--;
4056 demand_empty_rest_of_line ();
4057 }
4058 #endif
4059
4060 static int i386_immediate PARAMS ((char *));
4061
4062 static int
4063 i386_immediate (imm_start)
4064 char *imm_start;
4065 {
4066 char *save_input_line_pointer;
4067 char *gotfree_input_line;
4068 segT exp_seg = 0;
4069 expressionS *exp;
4070 unsigned int types = ~0U;
4071
4072 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
4073 {
4074 as_bad (_("only 1 or 2 immediate operands are allowed"));
4075 return 0;
4076 }
4077
4078 exp = &im_expressions[i.imm_operands++];
4079 i.op[this_operand].imms = exp;
4080
4081 if (is_space_char (*imm_start))
4082 ++imm_start;
4083
4084 save_input_line_pointer = input_line_pointer;
4085 input_line_pointer = imm_start;
4086
4087 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
4088 if (gotfree_input_line)
4089 input_line_pointer = gotfree_input_line;
4090
4091 exp_seg = expression (exp);
4092
4093 SKIP_WHITESPACE ();
4094 if (*input_line_pointer)
4095 as_bad (_("junk `%s' after expression"), input_line_pointer);
4096
4097 input_line_pointer = save_input_line_pointer;
4098 if (gotfree_input_line)
4099 free (gotfree_input_line);
4100
4101 if (exp->X_op == O_absent || exp->X_op == O_big)
4102 {
4103 /* Missing or bad expr becomes absolute 0. */
4104 as_bad (_("missing or invalid immediate expression `%s' taken as 0"),
4105 imm_start);
4106 exp->X_op = O_constant;
4107 exp->X_add_number = 0;
4108 exp->X_add_symbol = (symbolS *) 0;
4109 exp->X_op_symbol = (symbolS *) 0;
4110 }
4111 else if (exp->X_op == O_constant)
4112 {
4113 /* Size it properly later. */
4114 i.types[this_operand] |= Imm64;
4115 /* If BFD64, sign extend val. */
4116 if (!use_rela_relocations)
4117 if ((exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
4118 exp->X_add_number = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
4119 }
4120 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
4121 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
4122 && exp_seg != absolute_section
4123 && exp_seg != text_section
4124 && exp_seg != data_section
4125 && exp_seg != bss_section
4126 && exp_seg != undefined_section
4127 && !bfd_is_com_section (exp_seg))
4128 {
4129 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
4130 return 0;
4131 }
4132 #endif
4133 else
4134 {
4135 /* This is an address. The size of the address will be
4136 determined later, depending on destination register,
4137 suffix, or the default for the section. */
4138 i.types[this_operand] |= Imm8 | Imm16 | Imm32 | Imm32S | Imm64;
4139 i.types[this_operand] &= types;
4140 }
4141
4142 return 1;
4143 }
4144
4145 static char *i386_scale PARAMS ((char *));
4146
4147 static char *
4148 i386_scale (scale)
4149 char *scale;
4150 {
4151 offsetT val;
4152 char *save = input_line_pointer;
4153
4154 input_line_pointer = scale;
4155 val = get_absolute_expression ();
4156
4157 switch (val)
4158 {
4159 case 1:
4160 i.log2_scale_factor = 0;
4161 break;
4162 case 2:
4163 i.log2_scale_factor = 1;
4164 break;
4165 case 4:
4166 i.log2_scale_factor = 2;
4167 break;
4168 case 8:
4169 i.log2_scale_factor = 3;
4170 break;
4171 default:
4172 {
4173 char sep = *input_line_pointer;
4174
4175 *input_line_pointer = '\0';
4176 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
4177 scale);
4178 *input_line_pointer = sep;
4179 input_line_pointer = save;
4180 return NULL;
4181 }
4182 }
4183 if (i.log2_scale_factor != 0 && i.index_reg == 0)
4184 {
4185 as_warn (_("scale factor of %d without an index register"),
4186 1 << i.log2_scale_factor);
4187 #if SCALE1_WHEN_NO_INDEX
4188 i.log2_scale_factor = 0;
4189 #endif
4190 }
4191 scale = input_line_pointer;
4192 input_line_pointer = save;
4193 return scale;
4194 }
4195
4196 static int i386_displacement PARAMS ((char *, char *));
4197
4198 static int
4199 i386_displacement (disp_start, disp_end)
4200 char *disp_start;
4201 char *disp_end;
4202 {
4203 expressionS *exp;
4204 segT exp_seg = 0;
4205 char *save_input_line_pointer;
4206 char *gotfree_input_line;
4207 int bigdisp, override;
4208 unsigned int types = Disp;
4209
4210 if ((i.types[this_operand] & JumpAbsolute)
4211 || !(current_templates->start->opcode_modifier & (Jump | JumpDword)))
4212 {
4213 bigdisp = Disp32;
4214 override = (i.prefix[ADDR_PREFIX] != 0);
4215 }
4216 else
4217 {
4218 /* For PC-relative branches, the width of the displacement
4219 is dependent upon data size, not address size. */
4220 bigdisp = 0;
4221 override = (i.prefix[DATA_PREFIX] != 0);
4222 }
4223 if (flag_code == CODE_64BIT)
4224 {
4225 if (!bigdisp)
4226 bigdisp = (override || i.suffix == WORD_MNEM_SUFFIX)
4227 ? Disp16
4228 : Disp32S | Disp32;
4229 else if (!override)
4230 bigdisp = Disp64 | Disp32S | Disp32;
4231 }
4232 else
4233 {
4234 if (!bigdisp)
4235 {
4236 if (!override)
4237 override = (i.suffix == (flag_code != CODE_16BIT
4238 ? WORD_MNEM_SUFFIX
4239 : LONG_MNEM_SUFFIX));
4240 bigdisp = Disp32;
4241 }
4242 if ((flag_code == CODE_16BIT) ^ override)
4243 bigdisp = Disp16;
4244 }
4245 i.types[this_operand] |= bigdisp;
4246
4247 exp = &disp_expressions[i.disp_operands];
4248 i.op[this_operand].disps = exp;
4249 i.disp_operands++;
4250 save_input_line_pointer = input_line_pointer;
4251 input_line_pointer = disp_start;
4252 END_STRING_AND_SAVE (disp_end);
4253
4254 #ifndef GCC_ASM_O_HACK
4255 #define GCC_ASM_O_HACK 0
4256 #endif
4257 #if GCC_ASM_O_HACK
4258 END_STRING_AND_SAVE (disp_end + 1);
4259 if ((i.types[this_operand] & BaseIndex) != 0
4260 && displacement_string_end[-1] == '+')
4261 {
4262 /* This hack is to avoid a warning when using the "o"
4263 constraint within gcc asm statements.
4264 For instance:
4265
4266 #define _set_tssldt_desc(n,addr,limit,type) \
4267 __asm__ __volatile__ ( \
4268 "movw %w2,%0\n\t" \
4269 "movw %w1,2+%0\n\t" \
4270 "rorl $16,%1\n\t" \
4271 "movb %b1,4+%0\n\t" \
4272 "movb %4,5+%0\n\t" \
4273 "movb $0,6+%0\n\t" \
4274 "movb %h1,7+%0\n\t" \
4275 "rorl $16,%1" \
4276 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
4277
4278 This works great except that the output assembler ends
4279 up looking a bit weird if it turns out that there is
4280 no offset. You end up producing code that looks like:
4281
4282 #APP
4283 movw $235,(%eax)
4284 movw %dx,2+(%eax)
4285 rorl $16,%edx
4286 movb %dl,4+(%eax)
4287 movb $137,5+(%eax)
4288 movb $0,6+(%eax)
4289 movb %dh,7+(%eax)
4290 rorl $16,%edx
4291 #NO_APP
4292
4293 So here we provide the missing zero. */
4294
4295 *displacement_string_end = '0';
4296 }
4297 #endif
4298 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
4299 if (gotfree_input_line)
4300 input_line_pointer = gotfree_input_line;
4301
4302 exp_seg = expression (exp);
4303
4304 SKIP_WHITESPACE ();
4305 if (*input_line_pointer)
4306 as_bad (_("junk `%s' after expression"), input_line_pointer);
4307 #if GCC_ASM_O_HACK
4308 RESTORE_END_STRING (disp_end + 1);
4309 #endif
4310 RESTORE_END_STRING (disp_end);
4311 input_line_pointer = save_input_line_pointer;
4312 if (gotfree_input_line)
4313 free (gotfree_input_line);
4314
4315 /* We do this to make sure that the section symbol is in
4316 the symbol table. We will ultimately change the relocation
4317 to be relative to the beginning of the section. */
4318 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
4319 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
4320 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
4321 {
4322 if (exp->X_op != O_symbol)
4323 {
4324 as_bad (_("bad expression used with @%s"),
4325 (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
4326 ? "GOTPCREL"
4327 : "GOTOFF"));
4328 return 0;
4329 }
4330
4331 if (S_IS_LOCAL (exp->X_add_symbol)
4332 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section)
4333 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
4334 exp->X_op = O_subtract;
4335 exp->X_op_symbol = GOT_symbol;
4336 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
4337 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
4338 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
4339 i.reloc[this_operand] = BFD_RELOC_64;
4340 else
4341 i.reloc[this_operand] = BFD_RELOC_32;
4342 }
4343
4344 if (exp->X_op == O_absent || exp->X_op == O_big)
4345 {
4346 /* Missing or bad expr becomes absolute 0. */
4347 as_bad (_("missing or invalid displacement expression `%s' taken as 0"),
4348 disp_start);
4349 exp->X_op = O_constant;
4350 exp->X_add_number = 0;
4351 exp->X_add_symbol = (symbolS *) 0;
4352 exp->X_op_symbol = (symbolS *) 0;
4353 }
4354
4355 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
4356 if (exp->X_op != O_constant
4357 && OUTPUT_FLAVOR == bfd_target_aout_flavour
4358 && exp_seg != absolute_section
4359 && exp_seg != text_section
4360 && exp_seg != data_section
4361 && exp_seg != bss_section
4362 && exp_seg != undefined_section
4363 && !bfd_is_com_section (exp_seg))
4364 {
4365 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
4366 return 0;
4367 }
4368 #endif
4369
4370 if (!(i.types[this_operand] & ~Disp))
4371 i.types[this_operand] &= types;
4372
4373 return 1;
4374 }
4375
4376 static int i386_index_check PARAMS ((const char *));
4377
4378 /* Make sure the memory operand we've been dealt is valid.
4379 Return 1 on success, 0 on a failure. */
4380
4381 static int
4382 i386_index_check (operand_string)
4383 const char *operand_string;
4384 {
4385 int ok;
4386 #if INFER_ADDR_PREFIX
4387 int fudged = 0;
4388
4389 tryprefix:
4390 #endif
4391 ok = 1;
4392 if ((current_templates->start->cpu_flags & CpuSVME)
4393 && current_templates->end[-1].operand_types[0] == AnyMem)
4394 {
4395 /* Memory operands of SVME insns are special in that they only allow
4396 rAX as their memory address and ignore any segment override. */
4397 unsigned RegXX;
4398
4399 /* SKINIT is even more restrictive: it always requires EAX. */
4400 if (strcmp (current_templates->start->name, "skinit") == 0)
4401 RegXX = Reg32;
4402 else if (flag_code == CODE_64BIT)
4403 RegXX = i.prefix[ADDR_PREFIX] == 0 ? Reg64 : Reg32;
4404 else
4405 RegXX = (flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0)
4406 ? Reg16
4407 : Reg32;
4408 if (!i.base_reg
4409 || !(i.base_reg->reg_type & Acc)
4410 || !(i.base_reg->reg_type & RegXX)
4411 || i.index_reg
4412 || (i.types[0] & Disp))
4413 ok = 0;
4414 }
4415 else if (flag_code == CODE_64BIT)
4416 {
4417 unsigned RegXX = (i.prefix[ADDR_PREFIX] == 0 ? Reg64 : Reg32);
4418
4419 if ((i.base_reg
4420 && ((i.base_reg->reg_type & RegXX) == 0)
4421 && (i.base_reg->reg_type != BaseIndex
4422 || i.index_reg))
4423 || (i.index_reg
4424 && ((i.index_reg->reg_type & (RegXX | BaseIndex))
4425 != (RegXX | BaseIndex))))
4426 ok = 0;
4427 }
4428 else
4429 {
4430 if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
4431 {
4432 /* 16bit checks. */
4433 if ((i.base_reg
4434 && ((i.base_reg->reg_type & (Reg16 | BaseIndex | RegRex))
4435 != (Reg16 | BaseIndex)))
4436 || (i.index_reg
4437 && (((i.index_reg->reg_type & (Reg16 | BaseIndex))
4438 != (Reg16 | BaseIndex))
4439 || !(i.base_reg
4440 && i.base_reg->reg_num < 6
4441 && i.index_reg->reg_num >= 6
4442 && i.log2_scale_factor == 0))))
4443 ok = 0;
4444 }
4445 else
4446 {
4447 /* 32bit checks. */
4448 if ((i.base_reg
4449 && (i.base_reg->reg_type & (Reg32 | RegRex)) != Reg32)
4450 || (i.index_reg
4451 && ((i.index_reg->reg_type & (Reg32 | BaseIndex | RegRex))
4452 != (Reg32 | BaseIndex))))
4453 ok = 0;
4454 }
4455 }
4456 if (!ok)
4457 {
4458 #if INFER_ADDR_PREFIX
4459 if (i.prefix[ADDR_PREFIX] == 0)
4460 {
4461 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
4462 i.prefixes += 1;
4463 /* Change the size of any displacement too. At most one of
4464 Disp16 or Disp32 is set.
4465 FIXME. There doesn't seem to be any real need for separate
4466 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
4467 Removing them would probably clean up the code quite a lot. */
4468 if (flag_code != CODE_64BIT && (i.types[this_operand] & (Disp16 | Disp32)))
4469 i.types[this_operand] ^= (Disp16 | Disp32);
4470 fudged = 1;
4471 goto tryprefix;
4472 }
4473 if (fudged)
4474 as_bad (_("`%s' is not a valid base/index expression"),
4475 operand_string);
4476 else
4477 #endif
4478 as_bad (_("`%s' is not a valid %s bit base/index expression"),
4479 operand_string,
4480 flag_code_names[flag_code]);
4481 }
4482 return ok;
4483 }
4484
4485 /* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero
4486 on error. */
4487
4488 static int
4489 i386_operand (operand_string)
4490 char *operand_string;
4491 {
4492 const reg_entry *r;
4493 char *end_op;
4494 char *op_string = operand_string;
4495
4496 if (is_space_char (*op_string))
4497 ++op_string;
4498
4499 /* We check for an absolute prefix (differentiating,
4500 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
4501 if (*op_string == ABSOLUTE_PREFIX)
4502 {
4503 ++op_string;
4504 if (is_space_char (*op_string))
4505 ++op_string;
4506 i.types[this_operand] |= JumpAbsolute;
4507 }
4508
4509 /* Check if operand is a register. */
4510 if ((r = parse_register (op_string, &end_op)) != NULL)
4511 {
4512 /* Check for a segment override by searching for ':' after a
4513 segment register. */
4514 op_string = end_op;
4515 if (is_space_char (*op_string))
4516 ++op_string;
4517 if (*op_string == ':' && (r->reg_type & (SReg2 | SReg3)))
4518 {
4519 switch (r->reg_num)
4520 {
4521 case 0:
4522 i.seg[i.mem_operands] = &es;
4523 break;
4524 case 1:
4525 i.seg[i.mem_operands] = &cs;
4526 break;
4527 case 2:
4528 i.seg[i.mem_operands] = &ss;
4529 break;
4530 case 3:
4531 i.seg[i.mem_operands] = &ds;
4532 break;
4533 case 4:
4534 i.seg[i.mem_operands] = &fs;
4535 break;
4536 case 5:
4537 i.seg[i.mem_operands] = &gs;
4538 break;
4539 }
4540
4541 /* Skip the ':' and whitespace. */
4542 ++op_string;
4543 if (is_space_char (*op_string))
4544 ++op_string;
4545
4546 if (!is_digit_char (*op_string)
4547 && !is_identifier_char (*op_string)
4548 && *op_string != '('
4549 && *op_string != ABSOLUTE_PREFIX)
4550 {
4551 as_bad (_("bad memory operand `%s'"), op_string);
4552 return 0;
4553 }
4554 /* Handle case of %es:*foo. */
4555 if (*op_string == ABSOLUTE_PREFIX)
4556 {
4557 ++op_string;
4558 if (is_space_char (*op_string))
4559 ++op_string;
4560 i.types[this_operand] |= JumpAbsolute;
4561 }
4562 goto do_memory_reference;
4563 }
4564 if (*op_string)
4565 {
4566 as_bad (_("junk `%s' after register"), op_string);
4567 return 0;
4568 }
4569 i.types[this_operand] |= r->reg_type & ~BaseIndex;
4570 i.op[this_operand].regs = r;
4571 i.reg_operands++;
4572 }
4573 else if (*op_string == REGISTER_PREFIX)
4574 {
4575 as_bad (_("bad register name `%s'"), op_string);
4576 return 0;
4577 }
4578 else if (*op_string == IMMEDIATE_PREFIX)
4579 {
4580 ++op_string;
4581 if (i.types[this_operand] & JumpAbsolute)
4582 {
4583 as_bad (_("immediate operand illegal with absolute jump"));
4584 return 0;
4585 }
4586 if (!i386_immediate (op_string))
4587 return 0;
4588 }
4589 else if (is_digit_char (*op_string)
4590 || is_identifier_char (*op_string)
4591 || *op_string == '(')
4592 {
4593 /* This is a memory reference of some sort. */
4594 char *base_string;
4595
4596 /* Start and end of displacement string expression (if found). */
4597 char *displacement_string_start;
4598 char *displacement_string_end;
4599
4600 do_memory_reference:
4601 if ((i.mem_operands == 1
4602 && (current_templates->start->opcode_modifier & IsString) == 0)
4603 || i.mem_operands == 2)
4604 {
4605 as_bad (_("too many memory references for `%s'"),
4606 current_templates->start->name);
4607 return 0;
4608 }
4609
4610 /* Check for base index form. We detect the base index form by
4611 looking for an ')' at the end of the operand, searching
4612 for the '(' matching it, and finding a REGISTER_PREFIX or ','
4613 after the '('. */
4614 base_string = op_string + strlen (op_string);
4615
4616 --base_string;
4617 if (is_space_char (*base_string))
4618 --base_string;
4619
4620 /* If we only have a displacement, set-up for it to be parsed later. */
4621 displacement_string_start = op_string;
4622 displacement_string_end = base_string + 1;
4623
4624 if (*base_string == ')')
4625 {
4626 char *temp_string;
4627 unsigned int parens_balanced = 1;
4628 /* We've already checked that the number of left & right ()'s are
4629 equal, so this loop will not be infinite. */
4630 do
4631 {
4632 base_string--;
4633 if (*base_string == ')')
4634 parens_balanced++;
4635 if (*base_string == '(')
4636 parens_balanced--;
4637 }
4638 while (parens_balanced);
4639
4640 temp_string = base_string;
4641
4642 /* Skip past '(' and whitespace. */
4643 ++base_string;
4644 if (is_space_char (*base_string))
4645 ++base_string;
4646
4647 if (*base_string == ','
4648 || ((i.base_reg = parse_register (base_string, &end_op)) != NULL))
4649 {
4650 displacement_string_end = temp_string;
4651
4652 i.types[this_operand] |= BaseIndex;
4653
4654 if (i.base_reg)
4655 {
4656 base_string = end_op;
4657 if (is_space_char (*base_string))
4658 ++base_string;
4659 }
4660
4661 /* There may be an index reg or scale factor here. */
4662 if (*base_string == ',')
4663 {
4664 ++base_string;
4665 if (is_space_char (*base_string))
4666 ++base_string;
4667
4668 if ((i.index_reg = parse_register (base_string, &end_op)) != NULL)
4669 {
4670 base_string = end_op;
4671 if (is_space_char (*base_string))
4672 ++base_string;
4673 if (*base_string == ',')
4674 {
4675 ++base_string;
4676 if (is_space_char (*base_string))
4677 ++base_string;
4678 }
4679 else if (*base_string != ')')
4680 {
4681 as_bad (_("expecting `,' or `)' after index register in `%s'"),
4682 operand_string);
4683 return 0;
4684 }
4685 }
4686 else if (*base_string == REGISTER_PREFIX)
4687 {
4688 as_bad (_("bad register name `%s'"), base_string);
4689 return 0;
4690 }
4691
4692 /* Check for scale factor. */
4693 if (*base_string != ')')
4694 {
4695 char *end_scale = i386_scale (base_string);
4696
4697 if (!end_scale)
4698 return 0;
4699
4700 base_string = end_scale;
4701 if (is_space_char (*base_string))
4702 ++base_string;
4703 if (*base_string != ')')
4704 {
4705 as_bad (_("expecting `)' after scale factor in `%s'"),
4706 operand_string);
4707 return 0;
4708 }
4709 }
4710 else if (!i.index_reg)
4711 {
4712 as_bad (_("expecting index register or scale factor after `,'; got '%c'"),
4713 *base_string);
4714 return 0;
4715 }
4716 }
4717 else if (*base_string != ')')
4718 {
4719 as_bad (_("expecting `,' or `)' after base register in `%s'"),
4720 operand_string);
4721 return 0;
4722 }
4723 }
4724 else if (*base_string == REGISTER_PREFIX)
4725 {
4726 as_bad (_("bad register name `%s'"), base_string);
4727 return 0;
4728 }
4729 }
4730
4731 /* If there's an expression beginning the operand, parse it,
4732 assuming displacement_string_start and
4733 displacement_string_end are meaningful. */
4734 if (displacement_string_start != displacement_string_end)
4735 {
4736 if (!i386_displacement (displacement_string_start,
4737 displacement_string_end))
4738 return 0;
4739 }
4740
4741 /* Special case for (%dx) while doing input/output op. */
4742 if (i.base_reg
4743 && i.base_reg->reg_type == (Reg16 | InOutPortReg)
4744 && i.index_reg == 0
4745 && i.log2_scale_factor == 0
4746 && i.seg[i.mem_operands] == 0
4747 && (i.types[this_operand] & Disp) == 0)
4748 {
4749 i.types[this_operand] = InOutPortReg;
4750 return 1;
4751 }
4752
4753 if (i386_index_check (operand_string) == 0)
4754 return 0;
4755 i.mem_operands++;
4756 }
4757 else
4758 {
4759 /* It's not a memory operand; argh! */
4760 as_bad (_("invalid char %s beginning operand %d `%s'"),
4761 output_invalid (*op_string),
4762 this_operand + 1,
4763 op_string);
4764 return 0;
4765 }
4766 return 1; /* Normal return. */
4767 }
4768 \f
4769 /* md_estimate_size_before_relax()
4770
4771 Called just before relax() for rs_machine_dependent frags. The x86
4772 assembler uses these frags to handle variable size jump
4773 instructions.
4774
4775 Any symbol that is now undefined will not become defined.
4776 Return the correct fr_subtype in the frag.
4777 Return the initial "guess for variable size of frag" to caller.
4778 The guess is actually the growth beyond the fixed part. Whatever
4779 we do to grow the fixed or variable part contributes to our
4780 returned value. */
4781
4782 int
4783 md_estimate_size_before_relax (fragP, segment)
4784 fragS *fragP;
4785 segT segment;
4786 {
4787 /* We've already got fragP->fr_subtype right; all we have to do is
4788 check for un-relaxable symbols. On an ELF system, we can't relax
4789 an externally visible symbol, because it may be overridden by a
4790 shared library. */
4791 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
4792 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4793 || (IS_ELF
4794 && (S_IS_EXTERNAL (fragP->fr_symbol)
4795 || S_IS_WEAK (fragP->fr_symbol)))
4796 #endif
4797 )
4798 {
4799 /* Symbol is undefined in this segment, or we need to keep a
4800 reloc so that weak symbols can be overridden. */
4801 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
4802 enum bfd_reloc_code_real reloc_type;
4803 unsigned char *opcode;
4804 int old_fr_fix;
4805
4806 if (fragP->fr_var != NO_RELOC)
4807 reloc_type = fragP->fr_var;
4808 else if (size == 2)
4809 reloc_type = BFD_RELOC_16_PCREL;
4810 else
4811 reloc_type = BFD_RELOC_32_PCREL;
4812
4813 old_fr_fix = fragP->fr_fix;
4814 opcode = (unsigned char *) fragP->fr_opcode;
4815
4816 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
4817 {
4818 case UNCOND_JUMP:
4819 /* Make jmp (0xeb) a (d)word displacement jump. */
4820 opcode[0] = 0xe9;
4821 fragP->fr_fix += size;
4822 fix_new (fragP, old_fr_fix, size,
4823 fragP->fr_symbol,
4824 fragP->fr_offset, 1,
4825 reloc_type);
4826 break;
4827
4828 case COND_JUMP86:
4829 if (size == 2
4830 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
4831 {
4832 /* Negate the condition, and branch past an
4833 unconditional jump. */
4834 opcode[0] ^= 1;
4835 opcode[1] = 3;
4836 /* Insert an unconditional jump. */
4837 opcode[2] = 0xe9;
4838 /* We added two extra opcode bytes, and have a two byte
4839 offset. */
4840 fragP->fr_fix += 2 + 2;
4841 fix_new (fragP, old_fr_fix + 2, 2,
4842 fragP->fr_symbol,
4843 fragP->fr_offset, 1,
4844 reloc_type);
4845 break;
4846 }
4847 /* Fall through. */
4848
4849 case COND_JUMP:
4850 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
4851 {
4852 fixS *fixP;
4853
4854 fragP->fr_fix += 1;
4855 fixP = fix_new (fragP, old_fr_fix, 1,
4856 fragP->fr_symbol,
4857 fragP->fr_offset, 1,
4858 BFD_RELOC_8_PCREL);
4859 fixP->fx_signed = 1;
4860 break;
4861 }
4862
4863 /* This changes the byte-displacement jump 0x7N
4864 to the (d)word-displacement jump 0x0f,0x8N. */
4865 opcode[1] = opcode[0] + 0x10;
4866 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
4867 /* We've added an opcode byte. */
4868 fragP->fr_fix += 1 + size;
4869 fix_new (fragP, old_fr_fix + 1, size,
4870 fragP->fr_symbol,
4871 fragP->fr_offset, 1,
4872 reloc_type);
4873 break;
4874
4875 default:
4876 BAD_CASE (fragP->fr_subtype);
4877 break;
4878 }
4879 frag_wane (fragP);
4880 return fragP->fr_fix - old_fr_fix;
4881 }
4882
4883 /* Guess size depending on current relax state. Initially the relax
4884 state will correspond to a short jump and we return 1, because
4885 the variable part of the frag (the branch offset) is one byte
4886 long. However, we can relax a section more than once and in that
4887 case we must either set fr_subtype back to the unrelaxed state,
4888 or return the value for the appropriate branch. */
4889 return md_relax_table[fragP->fr_subtype].rlx_length;
4890 }
4891
4892 /* Called after relax() is finished.
4893
4894 In: Address of frag.
4895 fr_type == rs_machine_dependent.
4896 fr_subtype is what the address relaxed to.
4897
4898 Out: Any fixSs and constants are set up.
4899 Caller will turn frag into a ".space 0". */
4900
4901 void
4902 md_convert_frag (abfd, sec, fragP)
4903 bfd *abfd ATTRIBUTE_UNUSED;
4904 segT sec ATTRIBUTE_UNUSED;
4905 fragS *fragP;
4906 {
4907 unsigned char *opcode;
4908 unsigned char *where_to_put_displacement = NULL;
4909 offsetT target_address;
4910 offsetT opcode_address;
4911 unsigned int extension = 0;
4912 offsetT displacement_from_opcode_start;
4913
4914 opcode = (unsigned char *) fragP->fr_opcode;
4915
4916 /* Address we want to reach in file space. */
4917 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
4918
4919 /* Address opcode resides at in file space. */
4920 opcode_address = fragP->fr_address + fragP->fr_fix;
4921
4922 /* Displacement from opcode start to fill into instruction. */
4923 displacement_from_opcode_start = target_address - opcode_address;
4924
4925 if ((fragP->fr_subtype & BIG) == 0)
4926 {
4927 /* Don't have to change opcode. */
4928 extension = 1; /* 1 opcode + 1 displacement */
4929 where_to_put_displacement = &opcode[1];
4930 }
4931 else
4932 {
4933 if (no_cond_jump_promotion
4934 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
4935 as_warn_where (fragP->fr_file, fragP->fr_line, _("long jump required"));
4936
4937 switch (fragP->fr_subtype)
4938 {
4939 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
4940 extension = 4; /* 1 opcode + 4 displacement */
4941 opcode[0] = 0xe9;
4942 where_to_put_displacement = &opcode[1];
4943 break;
4944
4945 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
4946 extension = 2; /* 1 opcode + 2 displacement */
4947 opcode[0] = 0xe9;
4948 where_to_put_displacement = &opcode[1];
4949 break;
4950
4951 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
4952 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
4953 extension = 5; /* 2 opcode + 4 displacement */
4954 opcode[1] = opcode[0] + 0x10;
4955 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
4956 where_to_put_displacement = &opcode[2];
4957 break;
4958
4959 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
4960 extension = 3; /* 2 opcode + 2 displacement */
4961 opcode[1] = opcode[0] + 0x10;
4962 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
4963 where_to_put_displacement = &opcode[2];
4964 break;
4965
4966 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
4967 extension = 4;
4968 opcode[0] ^= 1;
4969 opcode[1] = 3;
4970 opcode[2] = 0xe9;
4971 where_to_put_displacement = &opcode[3];
4972 break;
4973
4974 default:
4975 BAD_CASE (fragP->fr_subtype);
4976 break;
4977 }
4978 }
4979
4980 /* If size if less then four we are sure that the operand fits,
4981 but if it's 4, then it could be that the displacement is larger
4982 then -/+ 2GB. */
4983 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
4984 && object_64bit
4985 && ((addressT) (displacement_from_opcode_start - extension
4986 + ((addressT) 1 << 31))
4987 > (((addressT) 2 << 31) - 1)))
4988 {
4989 as_bad_where (fragP->fr_file, fragP->fr_line,
4990 _("jump target out of range"));
4991 /* Make us emit 0. */
4992 displacement_from_opcode_start = extension;
4993 }
4994 /* Now put displacement after opcode. */
4995 md_number_to_chars ((char *) where_to_put_displacement,
4996 (valueT) (displacement_from_opcode_start - extension),
4997 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
4998 fragP->fr_fix += extension;
4999 }
5000 \f
5001 /* Size of byte displacement jmp. */
5002 int md_short_jump_size = 2;
5003
5004 /* Size of dword displacement jmp. */
5005 int md_long_jump_size = 5;
5006
5007 void
5008 md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol)
5009 char *ptr;
5010 addressT from_addr, to_addr;
5011 fragS *frag ATTRIBUTE_UNUSED;
5012 symbolS *to_symbol ATTRIBUTE_UNUSED;
5013 {
5014 offsetT offset;
5015
5016 offset = to_addr - (from_addr + 2);
5017 /* Opcode for byte-disp jump. */
5018 md_number_to_chars (ptr, (valueT) 0xeb, 1);
5019 md_number_to_chars (ptr + 1, (valueT) offset, 1);
5020 }
5021
5022 void
5023 md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol)
5024 char *ptr;
5025 addressT from_addr, to_addr;
5026 fragS *frag ATTRIBUTE_UNUSED;
5027 symbolS *to_symbol ATTRIBUTE_UNUSED;
5028 {
5029 offsetT offset;
5030
5031 offset = to_addr - (from_addr + 5);
5032 md_number_to_chars (ptr, (valueT) 0xe9, 1);
5033 md_number_to_chars (ptr + 1, (valueT) offset, 4);
5034 }
5035 \f
5036 /* Apply a fixup (fixS) to segment data, once it has been determined
5037 by our caller that we have all the info we need to fix it up.
5038
5039 On the 386, immediates, displacements, and data pointers are all in
5040 the same (little-endian) format, so we don't need to care about which
5041 we are handling. */
5042
5043 void
5044 md_apply_fix (fixP, valP, seg)
5045 /* The fix we're to put in. */
5046 fixS *fixP;
5047 /* Pointer to the value of the bits. */
5048 valueT *valP;
5049 /* Segment fix is from. */
5050 segT seg ATTRIBUTE_UNUSED;
5051 {
5052 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
5053 valueT value = *valP;
5054
5055 #if !defined (TE_Mach)
5056 if (fixP->fx_pcrel)
5057 {
5058 switch (fixP->fx_r_type)
5059 {
5060 default:
5061 break;
5062
5063 case BFD_RELOC_64:
5064 fixP->fx_r_type = BFD_RELOC_64_PCREL;
5065 break;
5066 case BFD_RELOC_32:
5067 case BFD_RELOC_X86_64_32S:
5068 fixP->fx_r_type = BFD_RELOC_32_PCREL;
5069 break;
5070 case BFD_RELOC_16:
5071 fixP->fx_r_type = BFD_RELOC_16_PCREL;
5072 break;
5073 case BFD_RELOC_8:
5074 fixP->fx_r_type = BFD_RELOC_8_PCREL;
5075 break;
5076 }
5077 }
5078
5079 if (fixP->fx_addsy != NULL
5080 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
5081 || fixP->fx_r_type == BFD_RELOC_64_PCREL
5082 || fixP->fx_r_type == BFD_RELOC_16_PCREL
5083 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
5084 && !use_rela_relocations)
5085 {
5086 /* This is a hack. There should be a better way to handle this.
5087 This covers for the fact that bfd_install_relocation will
5088 subtract the current location (for partial_inplace, PC relative
5089 relocations); see more below. */
5090 #ifndef OBJ_AOUT
5091 if (IS_ELF
5092 #ifdef TE_PE
5093 || OUTPUT_FLAVOR == bfd_target_coff_flavour
5094 #endif
5095 )
5096 value += fixP->fx_where + fixP->fx_frag->fr_address;
5097 #endif
5098 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5099 if (IS_ELF)
5100 {
5101 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
5102
5103 if ((sym_seg == seg
5104 || (symbol_section_p (fixP->fx_addsy)
5105 && sym_seg != absolute_section))
5106 && !generic_force_reloc (fixP))
5107 {
5108 /* Yes, we add the values in twice. This is because
5109 bfd_install_relocation subtracts them out again. I think
5110 bfd_install_relocation is broken, but I don't dare change
5111 it. FIXME. */
5112 value += fixP->fx_where + fixP->fx_frag->fr_address;
5113 }
5114 }
5115 #endif
5116 #if defined (OBJ_COFF) && defined (TE_PE)
5117 /* For some reason, the PE format does not store a
5118 section address offset for a PC relative symbol. */
5119 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
5120 || S_IS_WEAK (fixP->fx_addsy))
5121 value += md_pcrel_from (fixP);
5122 #endif
5123 }
5124
5125 /* Fix a few things - the dynamic linker expects certain values here,
5126 and we must not disappoint it. */
5127 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5128 if (IS_ELF && fixP->fx_addsy)
5129 switch (fixP->fx_r_type)
5130 {
5131 case BFD_RELOC_386_PLT32:
5132 case BFD_RELOC_X86_64_PLT32:
5133 /* Make the jump instruction point to the address of the operand. At
5134 runtime we merely add the offset to the actual PLT entry. */
5135 value = -4;
5136 break;
5137
5138 case BFD_RELOC_386_TLS_GD:
5139 case BFD_RELOC_386_TLS_LDM:
5140 case BFD_RELOC_386_TLS_IE_32:
5141 case BFD_RELOC_386_TLS_IE:
5142 case BFD_RELOC_386_TLS_GOTIE:
5143 case BFD_RELOC_386_TLS_GOTDESC:
5144 case BFD_RELOC_X86_64_TLSGD:
5145 case BFD_RELOC_X86_64_TLSLD:
5146 case BFD_RELOC_X86_64_GOTTPOFF:
5147 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
5148 value = 0; /* Fully resolved at runtime. No addend. */
5149 /* Fallthrough */
5150 case BFD_RELOC_386_TLS_LE:
5151 case BFD_RELOC_386_TLS_LDO_32:
5152 case BFD_RELOC_386_TLS_LE_32:
5153 case BFD_RELOC_X86_64_DTPOFF32:
5154 case BFD_RELOC_X86_64_DTPOFF64:
5155 case BFD_RELOC_X86_64_TPOFF32:
5156 case BFD_RELOC_X86_64_TPOFF64:
5157 S_SET_THREAD_LOCAL (fixP->fx_addsy);
5158 break;
5159
5160 case BFD_RELOC_386_TLS_DESC_CALL:
5161 case BFD_RELOC_X86_64_TLSDESC_CALL:
5162 value = 0; /* Fully resolved at runtime. No addend. */
5163 S_SET_THREAD_LOCAL (fixP->fx_addsy);
5164 fixP->fx_done = 0;
5165 return;
5166
5167 case BFD_RELOC_386_GOT32:
5168 case BFD_RELOC_X86_64_GOT32:
5169 value = 0; /* Fully resolved at runtime. No addend. */
5170 break;
5171
5172 case BFD_RELOC_VTABLE_INHERIT:
5173 case BFD_RELOC_VTABLE_ENTRY:
5174 fixP->fx_done = 0;
5175 return;
5176
5177 default:
5178 break;
5179 }
5180 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
5181 *valP = value;
5182 #endif /* !defined (TE_Mach) */
5183
5184 /* Are we finished with this relocation now? */
5185 if (fixP->fx_addsy == NULL)
5186 fixP->fx_done = 1;
5187 else if (use_rela_relocations)
5188 {
5189 fixP->fx_no_overflow = 1;
5190 /* Remember value for tc_gen_reloc. */
5191 fixP->fx_addnumber = value;
5192 value = 0;
5193 }
5194
5195 md_number_to_chars (p, value, fixP->fx_size);
5196 }
5197 \f
5198 #define MAX_LITTLENUMS 6
5199
5200 /* Turn the string pointed to by litP into a floating point constant
5201 of type TYPE, and emit the appropriate bytes. The number of
5202 LITTLENUMS emitted is stored in *SIZEP. An error message is
5203 returned, or NULL on OK. */
5204
5205 char *
5206 md_atof (type, litP, sizeP)
5207 int type;
5208 char *litP;
5209 int *sizeP;
5210 {
5211 int prec;
5212 LITTLENUM_TYPE words[MAX_LITTLENUMS];
5213 LITTLENUM_TYPE *wordP;
5214 char *t;
5215
5216 switch (type)
5217 {
5218 case 'f':
5219 case 'F':
5220 prec = 2;
5221 break;
5222
5223 case 'd':
5224 case 'D':
5225 prec = 4;
5226 break;
5227
5228 case 'x':
5229 case 'X':
5230 prec = 5;
5231 break;
5232
5233 default:
5234 *sizeP = 0;
5235 return _("Bad call to md_atof ()");
5236 }
5237 t = atof_ieee (input_line_pointer, type, words);
5238 if (t)
5239 input_line_pointer = t;
5240
5241 *sizeP = prec * sizeof (LITTLENUM_TYPE);
5242 /* This loops outputs the LITTLENUMs in REVERSE order; in accord with
5243 the bigendian 386. */
5244 for (wordP = words + prec - 1; prec--;)
5245 {
5246 md_number_to_chars (litP, (valueT) (*wordP--), sizeof (LITTLENUM_TYPE));
5247 litP += sizeof (LITTLENUM_TYPE);
5248 }
5249 return 0;
5250 }
5251 \f
5252 static char output_invalid_buf[8];
5253
5254 static char *
5255 output_invalid (c)
5256 int c;
5257 {
5258 if (ISPRINT (c))
5259 sprintf (output_invalid_buf, "'%c'", c);
5260 else
5261 sprintf (output_invalid_buf, "(0x%x)", (unsigned) c);
5262 return output_invalid_buf;
5263 }
5264
5265 /* REG_STRING starts *before* REGISTER_PREFIX. */
5266
5267 static const reg_entry *
5268 parse_real_register (char *reg_string, char **end_op)
5269 {
5270 char *s = reg_string;
5271 char *p;
5272 char reg_name_given[MAX_REG_NAME_SIZE + 1];
5273 const reg_entry *r;
5274
5275 /* Skip possible REGISTER_PREFIX and possible whitespace. */
5276 if (*s == REGISTER_PREFIX)
5277 ++s;
5278
5279 if (is_space_char (*s))
5280 ++s;
5281
5282 p = reg_name_given;
5283 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
5284 {
5285 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
5286 return (const reg_entry *) NULL;
5287 s++;
5288 }
5289
5290 /* For naked regs, make sure that we are not dealing with an identifier.
5291 This prevents confusing an identifier like `eax_var' with register
5292 `eax'. */
5293 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
5294 return (const reg_entry *) NULL;
5295
5296 *end_op = s;
5297
5298 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
5299
5300 /* Handle floating point regs, allowing spaces in the (i) part. */
5301 if (r == i386_regtab /* %st is first entry of table */)
5302 {
5303 if (is_space_char (*s))
5304 ++s;
5305 if (*s == '(')
5306 {
5307 ++s;
5308 if (is_space_char (*s))
5309 ++s;
5310 if (*s >= '0' && *s <= '7')
5311 {
5312 r = &i386_float_regtab[*s - '0'];
5313 ++s;
5314 if (is_space_char (*s))
5315 ++s;
5316 if (*s == ')')
5317 {
5318 *end_op = s + 1;
5319 return r;
5320 }
5321 }
5322 /* We have "%st(" then garbage. */
5323 return (const reg_entry *) NULL;
5324 }
5325 }
5326
5327 if (r != NULL
5328 && ((r->reg_flags & (RegRex64 | RegRex)) | (r->reg_type & Reg64)) != 0
5329 && (r->reg_type != Control || !(cpu_arch_flags & CpuSledgehammer))
5330 && flag_code != CODE_64BIT)
5331 return (const reg_entry *) NULL;
5332
5333 return r;
5334 }
5335
5336 /* REG_STRING starts *before* REGISTER_PREFIX. */
5337
5338 static const reg_entry *
5339 parse_register (char *reg_string, char **end_op)
5340 {
5341 const reg_entry *r;
5342
5343 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
5344 r = parse_real_register (reg_string, end_op);
5345 else
5346 r = NULL;
5347 if (!r)
5348 {
5349 char *save = input_line_pointer;
5350 char c;
5351 symbolS *symbolP;
5352
5353 input_line_pointer = reg_string;
5354 c = get_symbol_end ();
5355 symbolP = symbol_find (reg_string);
5356 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
5357 {
5358 const expressionS *e = symbol_get_value_expression (symbolP);
5359
5360 know (e->X_op == O_register);
5361 know (e->X_add_number >= 0 && (valueT) e->X_add_number < ARRAY_SIZE (i386_regtab));
5362 r = i386_regtab + e->X_add_number;
5363 *end_op = input_line_pointer;
5364 }
5365 *input_line_pointer = c;
5366 input_line_pointer = save;
5367 }
5368 return r;
5369 }
5370
5371 int
5372 i386_parse_name (char *name, expressionS *e, char *nextcharP)
5373 {
5374 const reg_entry *r;
5375 char *end = input_line_pointer;
5376
5377 *end = *nextcharP;
5378 r = parse_register (name, &input_line_pointer);
5379 if (r && end <= input_line_pointer)
5380 {
5381 *nextcharP = *input_line_pointer;
5382 *input_line_pointer = 0;
5383 e->X_op = O_register;
5384 e->X_add_number = r - i386_regtab;
5385 return 1;
5386 }
5387 input_line_pointer = end;
5388 *end = 0;
5389 return 0;
5390 }
5391
5392 void
5393 md_operand (expressionS *e)
5394 {
5395 if (*input_line_pointer == REGISTER_PREFIX)
5396 {
5397 char *end;
5398 const reg_entry *r = parse_real_register (input_line_pointer, &end);
5399
5400 if (r)
5401 {
5402 e->X_op = O_register;
5403 e->X_add_number = r - i386_regtab;
5404 input_line_pointer = end;
5405 }
5406 }
5407 }
5408
5409 \f
5410 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5411 const char *md_shortopts = "kVQ:sqn";
5412 #else
5413 const char *md_shortopts = "qn";
5414 #endif
5415
5416 #define OPTION_32 (OPTION_MD_BASE + 0)
5417 #define OPTION_64 (OPTION_MD_BASE + 1)
5418 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
5419
5420 struct option md_longopts[] = {
5421 {"32", no_argument, NULL, OPTION_32},
5422 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5423 {"64", no_argument, NULL, OPTION_64},
5424 #endif
5425 {"divide", no_argument, NULL, OPTION_DIVIDE},
5426 {NULL, no_argument, NULL, 0}
5427 };
5428 size_t md_longopts_size = sizeof (md_longopts);
5429
5430 int
5431 md_parse_option (c, arg)
5432 int c;
5433 char *arg ATTRIBUTE_UNUSED;
5434 {
5435 switch (c)
5436 {
5437 case 'n':
5438 optimize_align_code = 0;
5439 break;
5440
5441 case 'q':
5442 quiet_warnings = 1;
5443 break;
5444
5445 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5446 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
5447 should be emitted or not. FIXME: Not implemented. */
5448 case 'Q':
5449 break;
5450
5451 /* -V: SVR4 argument to print version ID. */
5452 case 'V':
5453 print_version_id ();
5454 break;
5455
5456 /* -k: Ignore for FreeBSD compatibility. */
5457 case 'k':
5458 break;
5459
5460 case 's':
5461 /* -s: On i386 Solaris, this tells the native assembler to use
5462 .stab instead of .stab.excl. We always use .stab anyhow. */
5463 break;
5464
5465 case OPTION_64:
5466 {
5467 const char **list, **l;
5468
5469 list = bfd_target_list ();
5470 for (l = list; *l != NULL; l++)
5471 if (strcmp (*l, "elf64-x86-64") == 0)
5472 {
5473 default_arch = "x86_64";
5474 break;
5475 }
5476 if (*l == NULL)
5477 as_fatal (_("No compiled in support for x86_64"));
5478 free (list);
5479 }
5480 break;
5481 #endif
5482
5483 case OPTION_32:
5484 default_arch = "i386";
5485 break;
5486
5487 case OPTION_DIVIDE:
5488 #ifdef SVR4_COMMENT_CHARS
5489 {
5490 char *n, *t;
5491 const char *s;
5492
5493 n = (char *) xmalloc (strlen (i386_comment_chars) + 1);
5494 t = n;
5495 for (s = i386_comment_chars; *s != '\0'; s++)
5496 if (*s != '/')
5497 *t++ = *s;
5498 *t = '\0';
5499 i386_comment_chars = n;
5500 }
5501 #endif
5502 break;
5503
5504 default:
5505 return 0;
5506 }
5507 return 1;
5508 }
5509
5510 void
5511 md_show_usage (stream)
5512 FILE *stream;
5513 {
5514 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5515 fprintf (stream, _("\
5516 -Q ignored\n\
5517 -V print assembler version number\n\
5518 -k ignored\n"));
5519 #endif
5520 fprintf (stream, _("\
5521 -n Do not optimize code alignment\n\
5522 -q quieten some warnings\n"));
5523 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5524 fprintf (stream, _("\
5525 -s ignored\n"));
5526 #endif
5527 #ifdef SVR4_COMMENT_CHARS
5528 fprintf (stream, _("\
5529 --divide do not treat `/' as a comment character\n"));
5530 #else
5531 fprintf (stream, _("\
5532 --divide ignored\n"));
5533 #endif
5534 }
5535
5536 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
5537 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
5538
5539 /* Pick the target format to use. */
5540
5541 const char *
5542 i386_target_format ()
5543 {
5544 if (!strcmp (default_arch, "x86_64"))
5545 set_code_flag (CODE_64BIT);
5546 else if (!strcmp (default_arch, "i386"))
5547 set_code_flag (CODE_32BIT);
5548 else
5549 as_fatal (_("Unknown architecture"));
5550 switch (OUTPUT_FLAVOR)
5551 {
5552 #ifdef OBJ_MAYBE_AOUT
5553 case bfd_target_aout_flavour:
5554 return AOUT_TARGET_FORMAT;
5555 #endif
5556 #ifdef OBJ_MAYBE_COFF
5557 case bfd_target_coff_flavour:
5558 return "coff-i386";
5559 #endif
5560 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
5561 case bfd_target_elf_flavour:
5562 {
5563 if (flag_code == CODE_64BIT)
5564 {
5565 object_64bit = 1;
5566 use_rela_relocations = 1;
5567 }
5568 return flag_code == CODE_64BIT ? "elf64-x86-64" : ELF_TARGET_FORMAT;
5569 }
5570 #endif
5571 default:
5572 abort ();
5573 return NULL;
5574 }
5575 }
5576
5577 #endif /* OBJ_MAYBE_ more than one */
5578
5579 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
5580 void i386_elf_emit_arch_note ()
5581 {
5582 if (IS_ELF && cpu_arch_name != NULL)
5583 {
5584 char *p;
5585 asection *seg = now_seg;
5586 subsegT subseg = now_subseg;
5587 Elf_Internal_Note i_note;
5588 Elf_External_Note e_note;
5589 asection *note_secp;
5590 int len;
5591
5592 /* Create the .note section. */
5593 note_secp = subseg_new (".note", 0);
5594 bfd_set_section_flags (stdoutput,
5595 note_secp,
5596 SEC_HAS_CONTENTS | SEC_READONLY);
5597
5598 /* Process the arch string. */
5599 len = strlen (cpu_arch_name);
5600
5601 i_note.namesz = len + 1;
5602 i_note.descsz = 0;
5603 i_note.type = NT_ARCH;
5604 p = frag_more (sizeof (e_note.namesz));
5605 md_number_to_chars (p, (valueT) i_note.namesz, sizeof (e_note.namesz));
5606 p = frag_more (sizeof (e_note.descsz));
5607 md_number_to_chars (p, (valueT) i_note.descsz, sizeof (e_note.descsz));
5608 p = frag_more (sizeof (e_note.type));
5609 md_number_to_chars (p, (valueT) i_note.type, sizeof (e_note.type));
5610 p = frag_more (len + 1);
5611 strcpy (p, cpu_arch_name);
5612
5613 frag_align (2, 0, 0);
5614
5615 subseg_set (seg, subseg);
5616 }
5617 }
5618 #endif
5619 \f
5620 symbolS *
5621 md_undefined_symbol (name)
5622 char *name;
5623 {
5624 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
5625 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
5626 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
5627 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
5628 {
5629 if (!GOT_symbol)
5630 {
5631 if (symbol_find (name))
5632 as_bad (_("GOT already in symbol table"));
5633 GOT_symbol = symbol_new (name, undefined_section,
5634 (valueT) 0, &zero_address_frag);
5635 };
5636 return GOT_symbol;
5637 }
5638 return 0;
5639 }
5640
5641 /* Round up a section size to the appropriate boundary. */
5642
5643 valueT
5644 md_section_align (segment, size)
5645 segT segment ATTRIBUTE_UNUSED;
5646 valueT size;
5647 {
5648 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
5649 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
5650 {
5651 /* For a.out, force the section size to be aligned. If we don't do
5652 this, BFD will align it for us, but it will not write out the
5653 final bytes of the section. This may be a bug in BFD, but it is
5654 easier to fix it here since that is how the other a.out targets
5655 work. */
5656 int align;
5657
5658 align = bfd_get_section_alignment (stdoutput, segment);
5659 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
5660 }
5661 #endif
5662
5663 return size;
5664 }
5665
5666 /* On the i386, PC-relative offsets are relative to the start of the
5667 next instruction. That is, the address of the offset, plus its
5668 size, since the offset is always the last part of the insn. */
5669
5670 long
5671 md_pcrel_from (fixP)
5672 fixS *fixP;
5673 {
5674 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
5675 }
5676
5677 #ifndef I386COFF
5678
5679 static void
5680 s_bss (ignore)
5681 int ignore ATTRIBUTE_UNUSED;
5682 {
5683 int temp;
5684
5685 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5686 if (IS_ELF)
5687 obj_elf_section_change_hook ();
5688 #endif
5689 temp = get_absolute_expression ();
5690 subseg_set (bss_section, (subsegT) temp);
5691 demand_empty_rest_of_line ();
5692 }
5693
5694 #endif
5695
5696 void
5697 i386_validate_fix (fixp)
5698 fixS *fixp;
5699 {
5700 if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol)
5701 {
5702 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
5703 {
5704 if (!object_64bit)
5705 abort ();
5706 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
5707 }
5708 else
5709 {
5710 if (!object_64bit)
5711 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
5712 else
5713 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
5714 }
5715 fixp->fx_subsy = 0;
5716 }
5717 }
5718
5719 arelent *
5720 tc_gen_reloc (section, fixp)
5721 asection *section ATTRIBUTE_UNUSED;
5722 fixS *fixp;
5723 {
5724 arelent *rel;
5725 bfd_reloc_code_real_type code;
5726
5727 switch (fixp->fx_r_type)
5728 {
5729 case BFD_RELOC_X86_64_PLT32:
5730 case BFD_RELOC_X86_64_GOT32:
5731 case BFD_RELOC_X86_64_GOTPCREL:
5732 case BFD_RELOC_386_PLT32:
5733 case BFD_RELOC_386_GOT32:
5734 case BFD_RELOC_386_GOTOFF:
5735 case BFD_RELOC_386_GOTPC:
5736 case BFD_RELOC_386_TLS_GD:
5737 case BFD_RELOC_386_TLS_LDM:
5738 case BFD_RELOC_386_TLS_LDO_32:
5739 case BFD_RELOC_386_TLS_IE_32:
5740 case BFD_RELOC_386_TLS_IE:
5741 case BFD_RELOC_386_TLS_GOTIE:
5742 case BFD_RELOC_386_TLS_LE_32:
5743 case BFD_RELOC_386_TLS_LE:
5744 case BFD_RELOC_386_TLS_GOTDESC:
5745 case BFD_RELOC_386_TLS_DESC_CALL:
5746 case BFD_RELOC_X86_64_TLSGD:
5747 case BFD_RELOC_X86_64_TLSLD:
5748 case BFD_RELOC_X86_64_DTPOFF32:
5749 case BFD_RELOC_X86_64_DTPOFF64:
5750 case BFD_RELOC_X86_64_GOTTPOFF:
5751 case BFD_RELOC_X86_64_TPOFF32:
5752 case BFD_RELOC_X86_64_TPOFF64:
5753 case BFD_RELOC_X86_64_GOTOFF64:
5754 case BFD_RELOC_X86_64_GOTPC32:
5755 case BFD_RELOC_X86_64_GOT64:
5756 case BFD_RELOC_X86_64_GOTPCREL64:
5757 case BFD_RELOC_X86_64_GOTPC64:
5758 case BFD_RELOC_X86_64_GOTPLT64:
5759 case BFD_RELOC_X86_64_PLTOFF64:
5760 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
5761 case BFD_RELOC_X86_64_TLSDESC_CALL:
5762 case BFD_RELOC_RVA:
5763 case BFD_RELOC_VTABLE_ENTRY:
5764 case BFD_RELOC_VTABLE_INHERIT:
5765 #ifdef TE_PE
5766 case BFD_RELOC_32_SECREL:
5767 #endif
5768 code = fixp->fx_r_type;
5769 break;
5770 case BFD_RELOC_X86_64_32S:
5771 if (!fixp->fx_pcrel)
5772 {
5773 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
5774 code = fixp->fx_r_type;
5775 break;
5776 }
5777 default:
5778 if (fixp->fx_pcrel)
5779 {
5780 switch (fixp->fx_size)
5781 {
5782 default:
5783 as_bad_where (fixp->fx_file, fixp->fx_line,
5784 _("can not do %d byte pc-relative relocation"),
5785 fixp->fx_size);
5786 code = BFD_RELOC_32_PCREL;
5787 break;
5788 case 1: code = BFD_RELOC_8_PCREL; break;
5789 case 2: code = BFD_RELOC_16_PCREL; break;
5790 case 4: code = BFD_RELOC_32_PCREL; break;
5791 #ifdef BFD64
5792 case 8: code = BFD_RELOC_64_PCREL; break;
5793 #endif
5794 }
5795 }
5796 else
5797 {
5798 switch (fixp->fx_size)
5799 {
5800 default:
5801 as_bad_where (fixp->fx_file, fixp->fx_line,
5802 _("can not do %d byte relocation"),
5803 fixp->fx_size);
5804 code = BFD_RELOC_32;
5805 break;
5806 case 1: code = BFD_RELOC_8; break;
5807 case 2: code = BFD_RELOC_16; break;
5808 case 4: code = BFD_RELOC_32; break;
5809 #ifdef BFD64
5810 case 8: code = BFD_RELOC_64; break;
5811 #endif
5812 }
5813 }
5814 break;
5815 }
5816
5817 if ((code == BFD_RELOC_32
5818 || code == BFD_RELOC_32_PCREL
5819 || code == BFD_RELOC_X86_64_32S)
5820 && GOT_symbol
5821 && fixp->fx_addsy == GOT_symbol)
5822 {
5823 if (!object_64bit)
5824 code = BFD_RELOC_386_GOTPC;
5825 else
5826 code = BFD_RELOC_X86_64_GOTPC32;
5827 }
5828 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
5829 && GOT_symbol
5830 && fixp->fx_addsy == GOT_symbol)
5831 {
5832 code = BFD_RELOC_X86_64_GOTPC64;
5833 }
5834
5835 rel = (arelent *) xmalloc (sizeof (arelent));
5836 rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
5837 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
5838
5839 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
5840
5841 if (!use_rela_relocations)
5842 {
5843 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
5844 vtable entry to be used in the relocation's section offset. */
5845 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
5846 rel->address = fixp->fx_offset;
5847
5848 rel->addend = 0;
5849 }
5850 /* Use the rela in 64bit mode. */
5851 else
5852 {
5853 if (!fixp->fx_pcrel)
5854 rel->addend = fixp->fx_offset;
5855 else
5856 switch (code)
5857 {
5858 case BFD_RELOC_X86_64_PLT32:
5859 case BFD_RELOC_X86_64_GOT32:
5860 case BFD_RELOC_X86_64_GOTPCREL:
5861 case BFD_RELOC_X86_64_TLSGD:
5862 case BFD_RELOC_X86_64_TLSLD:
5863 case BFD_RELOC_X86_64_GOTTPOFF:
5864 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
5865 case BFD_RELOC_X86_64_TLSDESC_CALL:
5866 rel->addend = fixp->fx_offset - fixp->fx_size;
5867 break;
5868 default:
5869 rel->addend = (section->vma
5870 - fixp->fx_size
5871 + fixp->fx_addnumber
5872 + md_pcrel_from (fixp));
5873 break;
5874 }
5875 }
5876
5877 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
5878 if (rel->howto == NULL)
5879 {
5880 as_bad_where (fixp->fx_file, fixp->fx_line,
5881 _("cannot represent relocation type %s"),
5882 bfd_get_reloc_code_name (code));
5883 /* Set howto to a garbage value so that we can keep going. */
5884 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
5885 assert (rel->howto != NULL);
5886 }
5887
5888 return rel;
5889 }
5890
5891 \f
5892 /* Parse operands using Intel syntax. This implements a recursive descent
5893 parser based on the BNF grammar published in Appendix B of the MASM 6.1
5894 Programmer's Guide.
5895
5896 FIXME: We do not recognize the full operand grammar defined in the MASM
5897 documentation. In particular, all the structure/union and
5898 high-level macro operands are missing.
5899
5900 Uppercase words are terminals, lower case words are non-terminals.
5901 Objects surrounded by double brackets '[[' ']]' are optional. Vertical
5902 bars '|' denote choices. Most grammar productions are implemented in
5903 functions called 'intel_<production>'.
5904
5905 Initial production is 'expr'.
5906
5907 addOp + | -
5908
5909 alpha [a-zA-Z]
5910
5911 binOp & | AND | \| | OR | ^ | XOR
5912
5913 byteRegister AL | AH | BL | BH | CL | CH | DL | DH
5914
5915 constant digits [[ radixOverride ]]
5916
5917 dataType BYTE | WORD | DWORD | FWORD | QWORD | TBYTE | OWORD | XMMWORD
5918
5919 digits decdigit
5920 | digits decdigit
5921 | digits hexdigit
5922
5923 decdigit [0-9]
5924
5925 e04 e04 addOp e05
5926 | e05
5927
5928 e05 e05 binOp e06
5929 | e06
5930
5931 e06 e06 mulOp e09
5932 | e09
5933
5934 e09 OFFSET e10
5935 | SHORT e10
5936 | + e10
5937 | - e10
5938 | ~ e10
5939 | NOT e10
5940 | e09 PTR e10
5941 | e09 : e10
5942 | e10
5943
5944 e10 e10 [ expr ]
5945 | e11
5946
5947 e11 ( expr )
5948 | [ expr ]
5949 | constant
5950 | dataType
5951 | id
5952 | $
5953 | register
5954
5955 => expr expr cmpOp e04
5956 | e04
5957
5958 gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX
5959 | BP | EBP | SP | ESP | DI | EDI | SI | ESI
5960
5961 hexdigit a | b | c | d | e | f
5962 | A | B | C | D | E | F
5963
5964 id alpha
5965 | id alpha
5966 | id decdigit
5967
5968 mulOp * | / | % | MOD | << | SHL | >> | SHR
5969
5970 quote " | '
5971
5972 register specialRegister
5973 | gpRegister
5974 | byteRegister
5975
5976 segmentRegister CS | DS | ES | FS | GS | SS
5977
5978 specialRegister CR0 | CR2 | CR3 | CR4
5979 | DR0 | DR1 | DR2 | DR3 | DR6 | DR7
5980 | TR3 | TR4 | TR5 | TR6 | TR7
5981
5982 We simplify the grammar in obvious places (e.g., register parsing is
5983 done by calling parse_register) and eliminate immediate left recursion
5984 to implement a recursive-descent parser.
5985
5986 expr e04 expr'
5987
5988 expr' cmpOp e04 expr'
5989 | Empty
5990
5991 e04 e05 e04'
5992
5993 e04' addOp e05 e04'
5994 | Empty
5995
5996 e05 e06 e05'
5997
5998 e05' binOp e06 e05'
5999 | Empty
6000
6001 e06 e09 e06'
6002
6003 e06' mulOp e09 e06'
6004 | Empty
6005
6006 e09 OFFSET e10 e09'
6007 | SHORT e10'
6008 | + e10'
6009 | - e10'
6010 | ~ e10'
6011 | NOT e10'
6012 | e10 e09'
6013
6014 e09' PTR e10 e09'
6015 | : e10 e09'
6016 | Empty
6017
6018 e10 e11 e10'
6019
6020 e10' [ expr ] e10'
6021 | Empty
6022
6023 e11 ( expr )
6024 | [ expr ]
6025 | BYTE
6026 | WORD
6027 | DWORD
6028 | FWORD
6029 | QWORD
6030 | TBYTE
6031 | OWORD
6032 | XMMWORD
6033 | .
6034 | $
6035 | register
6036 | id
6037 | constant */
6038
6039 /* Parsing structure for the intel syntax parser. Used to implement the
6040 semantic actions for the operand grammar. */
6041 struct intel_parser_s
6042 {
6043 char *op_string; /* The string being parsed. */
6044 int got_a_float; /* Whether the operand is a float. */
6045 int op_modifier; /* Operand modifier. */
6046 int is_mem; /* 1 if operand is memory reference. */
6047 int in_offset; /* >=1 if parsing operand of offset. */
6048 int in_bracket; /* >=1 if parsing operand in brackets. */
6049 const reg_entry *reg; /* Last register reference found. */
6050 char *disp; /* Displacement string being built. */
6051 char *next_operand; /* Resume point when splitting operands. */
6052 };
6053
6054 static struct intel_parser_s intel_parser;
6055
6056 /* Token structure for parsing intel syntax. */
6057 struct intel_token
6058 {
6059 int code; /* Token code. */
6060 const reg_entry *reg; /* Register entry for register tokens. */
6061 char *str; /* String representation. */
6062 };
6063
6064 static struct intel_token cur_token, prev_token;
6065
6066 /* Token codes for the intel parser. Since T_SHORT is already used
6067 by COFF, undefine it first to prevent a warning. */
6068 #define T_NIL -1
6069 #define T_CONST 1
6070 #define T_REG 2
6071 #define T_BYTE 3
6072 #define T_WORD 4
6073 #define T_DWORD 5
6074 #define T_FWORD 6
6075 #define T_QWORD 7
6076 #define T_TBYTE 8
6077 #define T_XMMWORD 9
6078 #undef T_SHORT
6079 #define T_SHORT 10
6080 #define T_OFFSET 11
6081 #define T_PTR 12
6082 #define T_ID 13
6083 #define T_SHL 14
6084 #define T_SHR 15
6085
6086 /* Prototypes for intel parser functions. */
6087 static int intel_match_token PARAMS ((int code));
6088 static void intel_get_token PARAMS ((void));
6089 static void intel_putback_token PARAMS ((void));
6090 static int intel_expr PARAMS ((void));
6091 static int intel_e04 PARAMS ((void));
6092 static int intel_e05 PARAMS ((void));
6093 static int intel_e06 PARAMS ((void));
6094 static int intel_e09 PARAMS ((void));
6095 static int intel_bracket_expr PARAMS ((void));
6096 static int intel_e10 PARAMS ((void));
6097 static int intel_e11 PARAMS ((void));
6098
6099 static int
6100 i386_intel_operand (operand_string, got_a_float)
6101 char *operand_string;
6102 int got_a_float;
6103 {
6104 int ret;
6105 char *p;
6106
6107 p = intel_parser.op_string = xstrdup (operand_string);
6108 intel_parser.disp = (char *) xmalloc (strlen (operand_string) + 1);
6109
6110 for (;;)
6111 {
6112 /* Initialize token holders. */
6113 cur_token.code = prev_token.code = T_NIL;
6114 cur_token.reg = prev_token.reg = NULL;
6115 cur_token.str = prev_token.str = NULL;
6116
6117 /* Initialize parser structure. */
6118 intel_parser.got_a_float = got_a_float;
6119 intel_parser.op_modifier = 0;
6120 intel_parser.is_mem = 0;
6121 intel_parser.in_offset = 0;
6122 intel_parser.in_bracket = 0;
6123 intel_parser.reg = NULL;
6124 intel_parser.disp[0] = '\0';
6125 intel_parser.next_operand = NULL;
6126
6127 /* Read the first token and start the parser. */
6128 intel_get_token ();
6129 ret = intel_expr ();
6130
6131 if (!ret)
6132 break;
6133
6134 if (cur_token.code != T_NIL)
6135 {
6136 as_bad (_("invalid operand for '%s' ('%s' unexpected)"),
6137 current_templates->start->name, cur_token.str);
6138 ret = 0;
6139 }
6140 /* If we found a memory reference, hand it over to i386_displacement
6141 to fill in the rest of the operand fields. */
6142 else if (intel_parser.is_mem)
6143 {
6144 if ((i.mem_operands == 1
6145 && (current_templates->start->opcode_modifier & IsString) == 0)
6146 || i.mem_operands == 2)
6147 {
6148 as_bad (_("too many memory references for '%s'"),
6149 current_templates->start->name);
6150 ret = 0;
6151 }
6152 else
6153 {
6154 char *s = intel_parser.disp;
6155 i.mem_operands++;
6156
6157 if (!quiet_warnings && intel_parser.is_mem < 0)
6158 /* See the comments in intel_bracket_expr. */
6159 as_warn (_("Treating `%s' as memory reference"), operand_string);
6160
6161 /* Add the displacement expression. */
6162 if (*s != '\0')
6163 ret = i386_displacement (s, s + strlen (s));
6164 if (ret)
6165 {
6166 /* Swap base and index in 16-bit memory operands like
6167 [si+bx]. Since i386_index_check is also used in AT&T
6168 mode we have to do that here. */
6169 if (i.base_reg
6170 && i.index_reg
6171 && (i.base_reg->reg_type & Reg16)
6172 && (i.index_reg->reg_type & Reg16)
6173 && i.base_reg->reg_num >= 6
6174 && i.index_reg->reg_num < 6)
6175 {
6176 const reg_entry *base = i.index_reg;
6177
6178 i.index_reg = i.base_reg;
6179 i.base_reg = base;
6180 }
6181 ret = i386_index_check (operand_string);
6182 }
6183 }
6184 }
6185
6186 /* Constant and OFFSET expressions are handled by i386_immediate. */
6187 else if ((intel_parser.op_modifier & (1 << T_OFFSET))
6188 || intel_parser.reg == NULL)
6189 ret = i386_immediate (intel_parser.disp);
6190
6191 if (intel_parser.next_operand && this_operand >= MAX_OPERANDS - 1)
6192 ret = 0;
6193 if (!ret || !intel_parser.next_operand)
6194 break;
6195 intel_parser.op_string = intel_parser.next_operand;
6196 this_operand = i.operands++;
6197 }
6198
6199 free (p);
6200 free (intel_parser.disp);
6201
6202 return ret;
6203 }
6204
6205 #define NUM_ADDRESS_REGS (!!i.base_reg + !!i.index_reg)
6206
6207 /* expr e04 expr'
6208
6209 expr' cmpOp e04 expr'
6210 | Empty */
6211 static int
6212 intel_expr ()
6213 {
6214 /* XXX Implement the comparison operators. */
6215 return intel_e04 ();
6216 }
6217
6218 /* e04 e05 e04'
6219
6220 e04' addOp e05 e04'
6221 | Empty */
6222 static int
6223 intel_e04 ()
6224 {
6225 int nregs = -1;
6226
6227 for (;;)
6228 {
6229 if (!intel_e05())
6230 return 0;
6231
6232 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
6233 i.base_reg = i386_regtab + REGNAM_AL; /* al is invalid as base */
6234
6235 if (cur_token.code == '+')
6236 nregs = -1;
6237 else if (cur_token.code == '-')
6238 nregs = NUM_ADDRESS_REGS;
6239 else
6240 return 1;
6241
6242 strcat (intel_parser.disp, cur_token.str);
6243 intel_match_token (cur_token.code);
6244 }
6245 }
6246
6247 /* e05 e06 e05'
6248
6249 e05' binOp e06 e05'
6250 | Empty */
6251 static int
6252 intel_e05 ()
6253 {
6254 int nregs = ~NUM_ADDRESS_REGS;
6255
6256 for (;;)
6257 {
6258 if (!intel_e06())
6259 return 0;
6260
6261 if (cur_token.code == '&' || cur_token.code == '|' || cur_token.code == '^')
6262 {
6263 char str[2];
6264
6265 str[0] = cur_token.code;
6266 str[1] = 0;
6267 strcat (intel_parser.disp, str);
6268 }
6269 else
6270 break;
6271
6272 intel_match_token (cur_token.code);
6273
6274 if (nregs < 0)
6275 nregs = ~nregs;
6276 }
6277 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
6278 i.base_reg = i386_regtab + REGNAM_AL + 1; /* cl is invalid as base */
6279 return 1;
6280 }
6281
6282 /* e06 e09 e06'
6283
6284 e06' mulOp e09 e06'
6285 | Empty */
6286 static int
6287 intel_e06 ()
6288 {
6289 int nregs = ~NUM_ADDRESS_REGS;
6290
6291 for (;;)
6292 {
6293 if (!intel_e09())
6294 return 0;
6295
6296 if (cur_token.code == '*' || cur_token.code == '/' || cur_token.code == '%')
6297 {
6298 char str[2];
6299
6300 str[0] = cur_token.code;
6301 str[1] = 0;
6302 strcat (intel_parser.disp, str);
6303 }
6304 else if (cur_token.code == T_SHL)
6305 strcat (intel_parser.disp, "<<");
6306 else if (cur_token.code == T_SHR)
6307 strcat (intel_parser.disp, ">>");
6308 else
6309 break;
6310
6311 intel_match_token (cur_token.code);
6312
6313 if (nregs < 0)
6314 nregs = ~nregs;
6315 }
6316 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
6317 i.base_reg = i386_regtab + REGNAM_AL + 2; /* dl is invalid as base */
6318 return 1;
6319 }
6320
6321 /* e09 OFFSET e09
6322 | SHORT e09
6323 | + e09
6324 | - e09
6325 | ~ e09
6326 | NOT e09
6327 | e10 e09'
6328
6329 e09' PTR e10 e09'
6330 | : e10 e09'
6331 | Empty */
6332 static int
6333 intel_e09 ()
6334 {
6335 int nregs = ~NUM_ADDRESS_REGS;
6336 int in_offset = 0;
6337
6338 for (;;)
6339 {
6340 /* Don't consume constants here. */
6341 if (cur_token.code == '+' || cur_token.code == '-')
6342 {
6343 /* Need to look one token ahead - if the next token
6344 is a constant, the current token is its sign. */
6345 int next_code;
6346
6347 intel_match_token (cur_token.code);
6348 next_code = cur_token.code;
6349 intel_putback_token ();
6350 if (next_code == T_CONST)
6351 break;
6352 }
6353
6354 /* e09 OFFSET e09 */
6355 if (cur_token.code == T_OFFSET)
6356 {
6357 if (!in_offset++)
6358 ++intel_parser.in_offset;
6359 }
6360
6361 /* e09 SHORT e09 */
6362 else if (cur_token.code == T_SHORT)
6363 intel_parser.op_modifier |= 1 << T_SHORT;
6364
6365 /* e09 + e09 */
6366 else if (cur_token.code == '+')
6367 strcat (intel_parser.disp, "+");
6368
6369 /* e09 - e09
6370 | ~ e09
6371 | NOT e09 */
6372 else if (cur_token.code == '-' || cur_token.code == '~')
6373 {
6374 char str[2];
6375
6376 if (nregs < 0)
6377 nregs = ~nregs;
6378 str[0] = cur_token.code;
6379 str[1] = 0;
6380 strcat (intel_parser.disp, str);
6381 }
6382
6383 /* e09 e10 e09' */
6384 else
6385 break;
6386
6387 intel_match_token (cur_token.code);
6388 }
6389
6390 for (;;)
6391 {
6392 if (!intel_e10 ())
6393 return 0;
6394
6395 /* e09' PTR e10 e09' */
6396 if (cur_token.code == T_PTR)
6397 {
6398 char suffix;
6399
6400 if (prev_token.code == T_BYTE)
6401 suffix = BYTE_MNEM_SUFFIX;
6402
6403 else if (prev_token.code == T_WORD)
6404 {
6405 if (current_templates->start->name[0] == 'l'
6406 && current_templates->start->name[2] == 's'
6407 && current_templates->start->name[3] == 0)
6408 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
6409 else if (intel_parser.got_a_float == 2) /* "fi..." */
6410 suffix = SHORT_MNEM_SUFFIX;
6411 else
6412 suffix = WORD_MNEM_SUFFIX;
6413 }
6414
6415 else if (prev_token.code == T_DWORD)
6416 {
6417 if (current_templates->start->name[0] == 'l'
6418 && current_templates->start->name[2] == 's'
6419 && current_templates->start->name[3] == 0)
6420 suffix = WORD_MNEM_SUFFIX;
6421 else if (flag_code == CODE_16BIT
6422 && (current_templates->start->opcode_modifier
6423 & (Jump | JumpDword)))
6424 suffix = LONG_DOUBLE_MNEM_SUFFIX;
6425 else if (intel_parser.got_a_float == 1) /* "f..." */
6426 suffix = SHORT_MNEM_SUFFIX;
6427 else
6428 suffix = LONG_MNEM_SUFFIX;
6429 }
6430
6431 else if (prev_token.code == T_FWORD)
6432 {
6433 if (current_templates->start->name[0] == 'l'
6434 && current_templates->start->name[2] == 's'
6435 && current_templates->start->name[3] == 0)
6436 suffix = LONG_MNEM_SUFFIX;
6437 else if (!intel_parser.got_a_float)
6438 {
6439 if (flag_code == CODE_16BIT)
6440 add_prefix (DATA_PREFIX_OPCODE);
6441 suffix = LONG_DOUBLE_MNEM_SUFFIX;
6442 }
6443 else
6444 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
6445 }
6446
6447 else if (prev_token.code == T_QWORD)
6448 {
6449 if (intel_parser.got_a_float == 1) /* "f..." */
6450 suffix = LONG_MNEM_SUFFIX;
6451 else
6452 suffix = QWORD_MNEM_SUFFIX;
6453 }
6454
6455 else if (prev_token.code == T_TBYTE)
6456 {
6457 if (intel_parser.got_a_float == 1)
6458 suffix = LONG_DOUBLE_MNEM_SUFFIX;
6459 else
6460 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
6461 }
6462
6463 else if (prev_token.code == T_XMMWORD)
6464 {
6465 /* XXX ignored for now, but accepted since gcc uses it */
6466 suffix = 0;
6467 }
6468
6469 else
6470 {
6471 as_bad (_("Unknown operand modifier `%s'"), prev_token.str);
6472 return 0;
6473 }
6474
6475 /* Operands for jump/call using 'ptr' notation denote absolute
6476 addresses. */
6477 if (current_templates->start->opcode_modifier & (Jump | JumpDword))
6478 i.types[this_operand] |= JumpAbsolute;
6479
6480 if (current_templates->start->base_opcode == 0x8d /* lea */)
6481 ;
6482 else if (!i.suffix)
6483 i.suffix = suffix;
6484 else if (i.suffix != suffix)
6485 {
6486 as_bad (_("Conflicting operand modifiers"));
6487 return 0;
6488 }
6489
6490 }
6491
6492 /* e09' : e10 e09' */
6493 else if (cur_token.code == ':')
6494 {
6495 if (prev_token.code != T_REG)
6496 {
6497 /* While {call,jmp} SSSS:OOOO is MASM syntax only when SSSS is a
6498 segment/group identifier (which we don't have), using comma
6499 as the operand separator there is even less consistent, since
6500 there all branches only have a single operand. */
6501 if (this_operand != 0
6502 || intel_parser.in_offset
6503 || intel_parser.in_bracket
6504 || (!(current_templates->start->opcode_modifier
6505 & (Jump|JumpDword|JumpInterSegment))
6506 && !(current_templates->start->operand_types[0]
6507 & JumpAbsolute)))
6508 return intel_match_token (T_NIL);
6509 /* Remember the start of the 2nd operand and terminate 1st
6510 operand here.
6511 XXX This isn't right, yet (when SSSS:OOOO is right operand of
6512 another expression), but it gets at least the simplest case
6513 (a plain number or symbol on the left side) right. */
6514 intel_parser.next_operand = intel_parser.op_string;
6515 *--intel_parser.op_string = '\0';
6516 return intel_match_token (':');
6517 }
6518 }
6519
6520 /* e09' Empty */
6521 else
6522 break;
6523
6524 intel_match_token (cur_token.code);
6525
6526 }
6527
6528 if (in_offset)
6529 {
6530 --intel_parser.in_offset;
6531 if (nregs < 0)
6532 nregs = ~nregs;
6533 if (NUM_ADDRESS_REGS > nregs)
6534 {
6535 as_bad (_("Invalid operand to `OFFSET'"));
6536 return 0;
6537 }
6538 intel_parser.op_modifier |= 1 << T_OFFSET;
6539 }
6540
6541 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
6542 i.base_reg = i386_regtab + REGNAM_AL + 3; /* bl is invalid as base */
6543 return 1;
6544 }
6545
6546 static int
6547 intel_bracket_expr ()
6548 {
6549 int was_offset = intel_parser.op_modifier & (1 << T_OFFSET);
6550 const char *start = intel_parser.op_string;
6551 int len;
6552
6553 if (i.op[this_operand].regs)
6554 return intel_match_token (T_NIL);
6555
6556 intel_match_token ('[');
6557
6558 /* Mark as a memory operand only if it's not already known to be an
6559 offset expression. If it's an offset expression, we need to keep
6560 the brace in. */
6561 if (!intel_parser.in_offset)
6562 {
6563 ++intel_parser.in_bracket;
6564
6565 /* Operands for jump/call inside brackets denote absolute addresses. */
6566 if (current_templates->start->opcode_modifier & (Jump | JumpDword))
6567 i.types[this_operand] |= JumpAbsolute;
6568
6569 /* Unfortunately gas always diverged from MASM in a respect that can't
6570 be easily fixed without risking to break code sequences likely to be
6571 encountered (the testsuite even check for this): MASM doesn't consider
6572 an expression inside brackets unconditionally as a memory reference.
6573 When that is e.g. a constant, an offset expression, or the sum of the
6574 two, this is still taken as a constant load. gas, however, always
6575 treated these as memory references. As a compromise, we'll try to make
6576 offset expressions inside brackets work the MASM way (since that's
6577 less likely to be found in real world code), but make constants alone
6578 continue to work the traditional gas way. In either case, issue a
6579 warning. */
6580 intel_parser.op_modifier &= ~was_offset;
6581 }
6582 else
6583 strcat (intel_parser.disp, "[");
6584
6585 /* Add a '+' to the displacement string if necessary. */
6586 if (*intel_parser.disp != '\0'
6587 && *(intel_parser.disp + strlen (intel_parser.disp) - 1) != '+')
6588 strcat (intel_parser.disp, "+");
6589
6590 if (intel_expr ()
6591 && (len = intel_parser.op_string - start - 1,
6592 intel_match_token (']')))
6593 {
6594 /* Preserve brackets when the operand is an offset expression. */
6595 if (intel_parser.in_offset)
6596 strcat (intel_parser.disp, "]");
6597 else
6598 {
6599 --intel_parser.in_bracket;
6600 if (i.base_reg || i.index_reg)
6601 intel_parser.is_mem = 1;
6602 if (!intel_parser.is_mem)
6603 {
6604 if (!(intel_parser.op_modifier & (1 << T_OFFSET)))
6605 /* Defer the warning until all of the operand was parsed. */
6606 intel_parser.is_mem = -1;
6607 else if (!quiet_warnings)
6608 as_warn (_("`[%.*s]' taken to mean just `%.*s'"), len, start, len, start);
6609 }
6610 }
6611 intel_parser.op_modifier |= was_offset;
6612
6613 return 1;
6614 }
6615 return 0;
6616 }
6617
6618 /* e10 e11 e10'
6619
6620 e10' [ expr ] e10'
6621 | Empty */
6622 static int
6623 intel_e10 ()
6624 {
6625 if (!intel_e11 ())
6626 return 0;
6627
6628 while (cur_token.code == '[')
6629 {
6630 if (!intel_bracket_expr ())
6631 return 0;
6632 }
6633
6634 return 1;
6635 }
6636
6637 /* e11 ( expr )
6638 | [ expr ]
6639 | BYTE
6640 | WORD
6641 | DWORD
6642 | FWORD
6643 | QWORD
6644 | TBYTE
6645 | OWORD
6646 | XMMWORD
6647 | $
6648 | .
6649 | register
6650 | id
6651 | constant */
6652 static int
6653 intel_e11 ()
6654 {
6655 switch (cur_token.code)
6656 {
6657 /* e11 ( expr ) */
6658 case '(':
6659 intel_match_token ('(');
6660 strcat (intel_parser.disp, "(");
6661
6662 if (intel_expr () && intel_match_token (')'))
6663 {
6664 strcat (intel_parser.disp, ")");
6665 return 1;
6666 }
6667 return 0;
6668
6669 /* e11 [ expr ] */
6670 case '[':
6671 return intel_bracket_expr ();
6672
6673 /* e11 $
6674 | . */
6675 case '.':
6676 strcat (intel_parser.disp, cur_token.str);
6677 intel_match_token (cur_token.code);
6678
6679 /* Mark as a memory operand only if it's not already known to be an
6680 offset expression. */
6681 if (!intel_parser.in_offset)
6682 intel_parser.is_mem = 1;
6683
6684 return 1;
6685
6686 /* e11 register */
6687 case T_REG:
6688 {
6689 const reg_entry *reg = intel_parser.reg = cur_token.reg;
6690
6691 intel_match_token (T_REG);
6692
6693 /* Check for segment change. */
6694 if (cur_token.code == ':')
6695 {
6696 if (!(reg->reg_type & (SReg2 | SReg3)))
6697 {
6698 as_bad (_("`%s' is not a valid segment register"), reg->reg_name);
6699 return 0;
6700 }
6701 else if (i.seg[i.mem_operands])
6702 as_warn (_("Extra segment override ignored"));
6703 else
6704 {
6705 if (!intel_parser.in_offset)
6706 intel_parser.is_mem = 1;
6707 switch (reg->reg_num)
6708 {
6709 case 0:
6710 i.seg[i.mem_operands] = &es;
6711 break;
6712 case 1:
6713 i.seg[i.mem_operands] = &cs;
6714 break;
6715 case 2:
6716 i.seg[i.mem_operands] = &ss;
6717 break;
6718 case 3:
6719 i.seg[i.mem_operands] = &ds;
6720 break;
6721 case 4:
6722 i.seg[i.mem_operands] = &fs;
6723 break;
6724 case 5:
6725 i.seg[i.mem_operands] = &gs;
6726 break;
6727 }
6728 }
6729 }
6730
6731 /* Not a segment register. Check for register scaling. */
6732 else if (cur_token.code == '*')
6733 {
6734 if (!intel_parser.in_bracket)
6735 {
6736 as_bad (_("Register scaling only allowed in memory operands"));
6737 return 0;
6738 }
6739
6740 if (reg->reg_type & Reg16) /* Disallow things like [si*1]. */
6741 reg = i386_regtab + REGNAM_AX + 4; /* sp is invalid as index */
6742 else if (i.index_reg)
6743 reg = i386_regtab + REGNAM_EAX + 4; /* esp is invalid as index */
6744
6745 /* What follows must be a valid scale. */
6746 intel_match_token ('*');
6747 i.index_reg = reg;
6748 i.types[this_operand] |= BaseIndex;
6749
6750 /* Set the scale after setting the register (otherwise,
6751 i386_scale will complain) */
6752 if (cur_token.code == '+' || cur_token.code == '-')
6753 {
6754 char *str, sign = cur_token.code;
6755 intel_match_token (cur_token.code);
6756 if (cur_token.code != T_CONST)
6757 {
6758 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
6759 cur_token.str);
6760 return 0;
6761 }
6762 str = (char *) xmalloc (strlen (cur_token.str) + 2);
6763 strcpy (str + 1, cur_token.str);
6764 *str = sign;
6765 if (!i386_scale (str))
6766 return 0;
6767 free (str);
6768 }
6769 else if (!i386_scale (cur_token.str))
6770 return 0;
6771 intel_match_token (cur_token.code);
6772 }
6773
6774 /* No scaling. If this is a memory operand, the register is either a
6775 base register (first occurrence) or an index register (second
6776 occurrence). */
6777 else if (intel_parser.in_bracket)
6778 {
6779
6780 if (!i.base_reg)
6781 i.base_reg = reg;
6782 else if (!i.index_reg)
6783 i.index_reg = reg;
6784 else
6785 {
6786 as_bad (_("Too many register references in memory operand"));
6787 return 0;
6788 }
6789
6790 i.types[this_operand] |= BaseIndex;
6791 }
6792
6793 /* It's neither base nor index. */
6794 else if (!intel_parser.in_offset && !intel_parser.is_mem)
6795 {
6796 i.types[this_operand] |= reg->reg_type & ~BaseIndex;
6797 i.op[this_operand].regs = reg;
6798 i.reg_operands++;
6799 }
6800 else
6801 {
6802 as_bad (_("Invalid use of register"));
6803 return 0;
6804 }
6805
6806 /* Since registers are not part of the displacement string (except
6807 when we're parsing offset operands), we may need to remove any
6808 preceding '+' from the displacement string. */
6809 if (*intel_parser.disp != '\0'
6810 && !intel_parser.in_offset)
6811 {
6812 char *s = intel_parser.disp;
6813 s += strlen (s) - 1;
6814 if (*s == '+')
6815 *s = '\0';
6816 }
6817
6818 return 1;
6819 }
6820
6821 /* e11 BYTE
6822 | WORD
6823 | DWORD
6824 | FWORD
6825 | QWORD
6826 | TBYTE
6827 | OWORD
6828 | XMMWORD */
6829 case T_BYTE:
6830 case T_WORD:
6831 case T_DWORD:
6832 case T_FWORD:
6833 case T_QWORD:
6834 case T_TBYTE:
6835 case T_XMMWORD:
6836 intel_match_token (cur_token.code);
6837
6838 if (cur_token.code == T_PTR)
6839 return 1;
6840
6841 /* It must have been an identifier. */
6842 intel_putback_token ();
6843 cur_token.code = T_ID;
6844 /* FALLTHRU */
6845
6846 /* e11 id
6847 | constant */
6848 case T_ID:
6849 if (!intel_parser.in_offset && intel_parser.is_mem <= 0)
6850 {
6851 symbolS *symbolP;
6852
6853 /* The identifier represents a memory reference only if it's not
6854 preceded by an offset modifier and if it's not an equate. */
6855 symbolP = symbol_find(cur_token.str);
6856 if (!symbolP || S_GET_SEGMENT(symbolP) != absolute_section)
6857 intel_parser.is_mem = 1;
6858 }
6859 /* FALLTHRU */
6860
6861 case T_CONST:
6862 case '-':
6863 case '+':
6864 {
6865 char *save_str, sign = 0;
6866
6867 /* Allow constants that start with `+' or `-'. */
6868 if (cur_token.code == '-' || cur_token.code == '+')
6869 {
6870 sign = cur_token.code;
6871 intel_match_token (cur_token.code);
6872 if (cur_token.code != T_CONST)
6873 {
6874 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
6875 cur_token.str);
6876 return 0;
6877 }
6878 }
6879
6880 save_str = (char *) xmalloc (strlen (cur_token.str) + 2);
6881 strcpy (save_str + !!sign, cur_token.str);
6882 if (sign)
6883 *save_str = sign;
6884
6885 /* Get the next token to check for register scaling. */
6886 intel_match_token (cur_token.code);
6887
6888 /* Check if this constant is a scaling factor for an index register. */
6889 if (cur_token.code == '*')
6890 {
6891 if (intel_match_token ('*') && cur_token.code == T_REG)
6892 {
6893 const reg_entry *reg = cur_token.reg;
6894
6895 if (!intel_parser.in_bracket)
6896 {
6897 as_bad (_("Register scaling only allowed in memory operands"));
6898 return 0;
6899 }
6900
6901 if (reg->reg_type & Reg16) /* Disallow things like [1*si]. */
6902 reg = i386_regtab + REGNAM_AX + 4; /* sp is invalid as index */
6903 else if (i.index_reg)
6904 reg = i386_regtab + REGNAM_EAX + 4; /* esp is invalid as index */
6905
6906 /* The constant is followed by `* reg', so it must be
6907 a valid scale. */
6908 i.index_reg = reg;
6909 i.types[this_operand] |= BaseIndex;
6910
6911 /* Set the scale after setting the register (otherwise,
6912 i386_scale will complain) */
6913 if (!i386_scale (save_str))
6914 return 0;
6915 intel_match_token (T_REG);
6916
6917 /* Since registers are not part of the displacement
6918 string, we may need to remove any preceding '+' from
6919 the displacement string. */
6920 if (*intel_parser.disp != '\0')
6921 {
6922 char *s = intel_parser.disp;
6923 s += strlen (s) - 1;
6924 if (*s == '+')
6925 *s = '\0';
6926 }
6927
6928 free (save_str);
6929
6930 return 1;
6931 }
6932
6933 /* The constant was not used for register scaling. Since we have
6934 already consumed the token following `*' we now need to put it
6935 back in the stream. */
6936 intel_putback_token ();
6937 }
6938
6939 /* Add the constant to the displacement string. */
6940 strcat (intel_parser.disp, save_str);
6941 free (save_str);
6942
6943 return 1;
6944 }
6945 }
6946
6947 as_bad (_("Unrecognized token '%s'"), cur_token.str);
6948 return 0;
6949 }
6950
6951 /* Match the given token against cur_token. If they match, read the next
6952 token from the operand string. */
6953 static int
6954 intel_match_token (code)
6955 int code;
6956 {
6957 if (cur_token.code == code)
6958 {
6959 intel_get_token ();
6960 return 1;
6961 }
6962 else
6963 {
6964 as_bad (_("Unexpected token `%s'"), cur_token.str);
6965 return 0;
6966 }
6967 }
6968
6969 /* Read a new token from intel_parser.op_string and store it in cur_token. */
6970 static void
6971 intel_get_token ()
6972 {
6973 char *end_op;
6974 const reg_entry *reg;
6975 struct intel_token new_token;
6976
6977 new_token.code = T_NIL;
6978 new_token.reg = NULL;
6979 new_token.str = NULL;
6980
6981 /* Free the memory allocated to the previous token and move
6982 cur_token to prev_token. */
6983 if (prev_token.str)
6984 free (prev_token.str);
6985
6986 prev_token = cur_token;
6987
6988 /* Skip whitespace. */
6989 while (is_space_char (*intel_parser.op_string))
6990 intel_parser.op_string++;
6991
6992 /* Return an empty token if we find nothing else on the line. */
6993 if (*intel_parser.op_string == '\0')
6994 {
6995 cur_token = new_token;
6996 return;
6997 }
6998
6999 /* The new token cannot be larger than the remainder of the operand
7000 string. */
7001 new_token.str = (char *) xmalloc (strlen (intel_parser.op_string) + 1);
7002 new_token.str[0] = '\0';
7003
7004 if (strchr ("0123456789", *intel_parser.op_string))
7005 {
7006 char *p = new_token.str;
7007 char *q = intel_parser.op_string;
7008 new_token.code = T_CONST;
7009
7010 /* Allow any kind of identifier char to encompass floating point and
7011 hexadecimal numbers. */
7012 while (is_identifier_char (*q))
7013 *p++ = *q++;
7014 *p = '\0';
7015
7016 /* Recognize special symbol names [0-9][bf]. */
7017 if (strlen (intel_parser.op_string) == 2
7018 && (intel_parser.op_string[1] == 'b'
7019 || intel_parser.op_string[1] == 'f'))
7020 new_token.code = T_ID;
7021 }
7022
7023 else if ((reg = parse_register (intel_parser.op_string, &end_op)) != NULL)
7024 {
7025 size_t len = end_op - intel_parser.op_string;
7026
7027 new_token.code = T_REG;
7028 new_token.reg = reg;
7029
7030 memcpy (new_token.str, intel_parser.op_string, len);
7031 new_token.str[len] = '\0';
7032 }
7033
7034 else if (is_identifier_char (*intel_parser.op_string))
7035 {
7036 char *p = new_token.str;
7037 char *q = intel_parser.op_string;
7038
7039 /* A '.' or '$' followed by an identifier char is an identifier.
7040 Otherwise, it's operator '.' followed by an expression. */
7041 if ((*q == '.' || *q == '$') && !is_identifier_char (*(q + 1)))
7042 {
7043 new_token.code = '.';
7044 new_token.str[0] = '.';
7045 new_token.str[1] = '\0';
7046 }
7047 else
7048 {
7049 while (is_identifier_char (*q) || *q == '@')
7050 *p++ = *q++;
7051 *p = '\0';
7052
7053 if (strcasecmp (new_token.str, "NOT") == 0)
7054 new_token.code = '~';
7055
7056 else if (strcasecmp (new_token.str, "MOD") == 0)
7057 new_token.code = '%';
7058
7059 else if (strcasecmp (new_token.str, "AND") == 0)
7060 new_token.code = '&';
7061
7062 else if (strcasecmp (new_token.str, "OR") == 0)
7063 new_token.code = '|';
7064
7065 else if (strcasecmp (new_token.str, "XOR") == 0)
7066 new_token.code = '^';
7067
7068 else if (strcasecmp (new_token.str, "SHL") == 0)
7069 new_token.code = T_SHL;
7070
7071 else if (strcasecmp (new_token.str, "SHR") == 0)
7072 new_token.code = T_SHR;
7073
7074 else if (strcasecmp (new_token.str, "BYTE") == 0)
7075 new_token.code = T_BYTE;
7076
7077 else if (strcasecmp (new_token.str, "WORD") == 0)
7078 new_token.code = T_WORD;
7079
7080 else if (strcasecmp (new_token.str, "DWORD") == 0)
7081 new_token.code = T_DWORD;
7082
7083 else if (strcasecmp (new_token.str, "FWORD") == 0)
7084 new_token.code = T_FWORD;
7085
7086 else if (strcasecmp (new_token.str, "QWORD") == 0)
7087 new_token.code = T_QWORD;
7088
7089 else if (strcasecmp (new_token.str, "TBYTE") == 0
7090 /* XXX remove (gcc still uses it) */
7091 || strcasecmp (new_token.str, "XWORD") == 0)
7092 new_token.code = T_TBYTE;
7093
7094 else if (strcasecmp (new_token.str, "XMMWORD") == 0
7095 || strcasecmp (new_token.str, "OWORD") == 0)
7096 new_token.code = T_XMMWORD;
7097
7098 else if (strcasecmp (new_token.str, "PTR") == 0)
7099 new_token.code = T_PTR;
7100
7101 else if (strcasecmp (new_token.str, "SHORT") == 0)
7102 new_token.code = T_SHORT;
7103
7104 else if (strcasecmp (new_token.str, "OFFSET") == 0)
7105 {
7106 new_token.code = T_OFFSET;
7107
7108 /* ??? This is not mentioned in the MASM grammar but gcc
7109 makes use of it with -mintel-syntax. OFFSET may be
7110 followed by FLAT: */
7111 if (strncasecmp (q, " FLAT:", 6) == 0)
7112 strcat (new_token.str, " FLAT:");
7113 }
7114
7115 /* ??? This is not mentioned in the MASM grammar. */
7116 else if (strcasecmp (new_token.str, "FLAT") == 0)
7117 {
7118 new_token.code = T_OFFSET;
7119 if (*q == ':')
7120 strcat (new_token.str, ":");
7121 else
7122 as_bad (_("`:' expected"));
7123 }
7124
7125 else
7126 new_token.code = T_ID;
7127 }
7128 }
7129
7130 else if (strchr ("+-/*%|&^:[]()~", *intel_parser.op_string))
7131 {
7132 new_token.code = *intel_parser.op_string;
7133 new_token.str[0] = *intel_parser.op_string;
7134 new_token.str[1] = '\0';
7135 }
7136
7137 else if (strchr ("<>", *intel_parser.op_string)
7138 && *intel_parser.op_string == *(intel_parser.op_string + 1))
7139 {
7140 new_token.code = *intel_parser.op_string == '<' ? T_SHL : T_SHR;
7141 new_token.str[0] = *intel_parser.op_string;
7142 new_token.str[1] = *intel_parser.op_string;
7143 new_token.str[2] = '\0';
7144 }
7145
7146 else
7147 as_bad (_("Unrecognized token `%s'"), intel_parser.op_string);
7148
7149 intel_parser.op_string += strlen (new_token.str);
7150 cur_token = new_token;
7151 }
7152
7153 /* Put cur_token back into the token stream and make cur_token point to
7154 prev_token. */
7155 static void
7156 intel_putback_token ()
7157 {
7158 if (cur_token.code != T_NIL)
7159 {
7160 intel_parser.op_string -= strlen (cur_token.str);
7161 free (cur_token.str);
7162 }
7163 cur_token = prev_token;
7164
7165 /* Forget prev_token. */
7166 prev_token.code = T_NIL;
7167 prev_token.reg = NULL;
7168 prev_token.str = NULL;
7169 }
7170
7171 int
7172 tc_x86_regname_to_dw2regnum (const char *regname)
7173 {
7174 unsigned int regnum;
7175 unsigned int regnames_count;
7176 static const char *const regnames_32[] =
7177 {
7178 "eax", "ecx", "edx", "ebx",
7179 "esp", "ebp", "esi", "edi",
7180 "eip", "eflags", NULL,
7181 "st0", "st1", "st2", "st3",
7182 "st4", "st5", "st6", "st7",
7183 NULL, NULL,
7184 "xmm0", "xmm1", "xmm2", "xmm3",
7185 "xmm4", "xmm5", "xmm6", "xmm7",
7186 "mm0", "mm1", "mm2", "mm3",
7187 "mm4", "mm5", "mm6", "mm7",
7188 "fcw", "fsw", "mxcsr",
7189 "es", "cs", "ss", "ds", "fs", "gs", NULL, NULL,
7190 "tr", "ldtr"
7191 };
7192 static const char *const regnames_64[] =
7193 {
7194 "rax", "rdx", "rcx", "rbx",
7195 "rsi", "rdi", "rbp", "rsp",
7196 "r8", "r9", "r10", "r11",
7197 "r12", "r13", "r14", "r15",
7198 "rip",
7199 "xmm0", "xmm1", "xmm2", "xmm3",
7200 "xmm4", "xmm5", "xmm6", "xmm7",
7201 "xmm8", "xmm9", "xmm10", "xmm11",
7202 "xmm12", "xmm13", "xmm14", "xmm15",
7203 "st0", "st1", "st2", "st3",
7204 "st4", "st5", "st6", "st7",
7205 "mm0", "mm1", "mm2", "mm3",
7206 "mm4", "mm5", "mm6", "mm7",
7207 "rflags",
7208 "es", "cs", "ss", "ds", "fs", "gs", NULL, NULL,
7209 "fs.base", "gs.base", NULL, NULL,
7210 "tr", "ldtr",
7211 "mxcsr", "fcw", "fsw"
7212 };
7213 const char *const *regnames;
7214
7215 if (flag_code == CODE_64BIT)
7216 {
7217 regnames = regnames_64;
7218 regnames_count = ARRAY_SIZE (regnames_64);
7219 }
7220 else
7221 {
7222 regnames = regnames_32;
7223 regnames_count = ARRAY_SIZE (regnames_32);
7224 }
7225
7226 for (regnum = 0; regnum < regnames_count; regnum++)
7227 if (regnames[regnum] != NULL
7228 && strcmp (regname, regnames[regnum]) == 0)
7229 return regnum;
7230
7231 return -1;
7232 }
7233
7234 void
7235 tc_x86_frame_initial_instructions (void)
7236 {
7237 static unsigned int sp_regno;
7238
7239 if (!sp_regno)
7240 sp_regno = tc_x86_regname_to_dw2regnum (flag_code == CODE_64BIT
7241 ? "rsp" : "esp");
7242
7243 cfi_add_CFA_def_cfa (sp_regno, -x86_cie_data_alignment);
7244 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
7245 }
7246
7247 int
7248 i386_elf_section_type (const char *str, size_t len)
7249 {
7250 if (flag_code == CODE_64BIT
7251 && len == sizeof ("unwind") - 1
7252 && strncmp (str, "unwind", 6) == 0)
7253 return SHT_X86_64_UNWIND;
7254
7255 return -1;
7256 }
7257
7258 #ifdef TE_PE
7259 void
7260 tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
7261 {
7262 expressionS expr;
7263
7264 expr.X_op = O_secrel;
7265 expr.X_add_symbol = symbol;
7266 expr.X_add_number = 0;
7267 emit_expr (&expr, size);
7268 }
7269 #endif
7270
7271 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7272 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
7273
7274 int
7275 x86_64_section_letter (int letter, char **ptr_msg)
7276 {
7277 if (flag_code == CODE_64BIT)
7278 {
7279 if (letter == 'l')
7280 return SHF_X86_64_LARGE;
7281
7282 *ptr_msg = _("Bad .section directive: want a,l,w,x,M,S,G,T in string");
7283 }
7284 else
7285 *ptr_msg = _("Bad .section directive: want a,w,x,M,S,G,T in string");
7286 return -1;
7287 }
7288
7289 int
7290 x86_64_section_word (char *str, size_t len)
7291 {
7292 if (len == 5 && flag_code == CODE_64BIT && strncmp (str, "large", 5) == 0)
7293 return SHF_X86_64_LARGE;
7294
7295 return -1;
7296 }
7297
7298 static void
7299 handle_large_common (int small ATTRIBUTE_UNUSED)
7300 {
7301 if (flag_code != CODE_64BIT)
7302 {
7303 s_comm_internal (0, elf_common_parse);
7304 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
7305 }
7306 else
7307 {
7308 static segT lbss_section;
7309 asection *saved_com_section_ptr = elf_com_section_ptr;
7310 asection *saved_bss_section = bss_section;
7311
7312 if (lbss_section == NULL)
7313 {
7314 flagword applicable;
7315 segT seg = now_seg;
7316 subsegT subseg = now_subseg;
7317
7318 /* The .lbss section is for local .largecomm symbols. */
7319 lbss_section = subseg_new (".lbss", 0);
7320 applicable = bfd_applicable_section_flags (stdoutput);
7321 bfd_set_section_flags (stdoutput, lbss_section,
7322 applicable & SEC_ALLOC);
7323 seg_info (lbss_section)->bss = 1;
7324
7325 subseg_set (seg, subseg);
7326 }
7327
7328 elf_com_section_ptr = &_bfd_elf_large_com_section;
7329 bss_section = lbss_section;
7330
7331 s_comm_internal (0, elf_common_parse);
7332
7333 elf_com_section_ptr = saved_com_section_ptr;
7334 bss_section = saved_bss_section;
7335 }
7336 }
7337 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
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