1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright (C) 1989-2015 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 /* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
23 x86_64 support by Jan Hubicka (jh@suse.cz)
24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
29 #include "safe-ctype.h"
31 #include "dwarf2dbg.h"
32 #include "dw2gencfi.h"
33 #include "elf/x86-64.h"
34 #include "opcodes/i386-init.h"
37 /* Default to compress debug sections for Linux. */
38 int flag_compress_debug
= 1;
41 #ifndef REGISTER_WARNINGS
42 #define REGISTER_WARNINGS 1
45 #ifndef INFER_ADDR_PREFIX
46 #define INFER_ADDR_PREFIX 1
50 #define DEFAULT_ARCH "i386"
55 #define INLINE __inline__
61 /* Prefixes will be emitted in the order defined below.
62 WAIT_PREFIX must be the first prefix since FWAIT is really is an
63 instruction, and so must come before any prefixes.
64 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
65 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
71 #define HLE_PREFIX REP_PREFIX
72 #define BND_PREFIX REP_PREFIX
74 #define REX_PREFIX 6 /* must come last. */
75 #define MAX_PREFIXES 7 /* max prefixes per opcode */
77 /* we define the syntax here (modulo base,index,scale syntax) */
78 #define REGISTER_PREFIX '%'
79 #define IMMEDIATE_PREFIX '$'
80 #define ABSOLUTE_PREFIX '*'
82 /* these are the instruction mnemonic suffixes in AT&T syntax or
83 memory operand size in Intel syntax. */
84 #define WORD_MNEM_SUFFIX 'w'
85 #define BYTE_MNEM_SUFFIX 'b'
86 #define SHORT_MNEM_SUFFIX 's'
87 #define LONG_MNEM_SUFFIX 'l'
88 #define QWORD_MNEM_SUFFIX 'q'
89 #define XMMWORD_MNEM_SUFFIX 'x'
90 #define YMMWORD_MNEM_SUFFIX 'y'
91 #define ZMMWORD_MNEM_SUFFIX 'z'
92 /* Intel Syntax. Use a non-ascii letter since since it never appears
94 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
96 #define END_OF_INSN '\0'
99 'templates' is for grouping together 'template' structures for opcodes
100 of the same name. This is only used for storing the insns in the grand
101 ole hash table of insns.
102 The templates themselves start at START and range up to (but not including)
107 const insn_template
*start
;
108 const insn_template
*end
;
112 /* 386 operand encoding bytes: see 386 book for details of this. */
115 unsigned int regmem
; /* codes register or memory operand */
116 unsigned int reg
; /* codes register operand (or extended opcode) */
117 unsigned int mode
; /* how to interpret regmem & reg */
121 /* x86-64 extension prefix. */
122 typedef int rex_byte
;
124 /* 386 opcode byte to code indirect addressing. */
133 /* x86 arch names, types and features */
136 const char *name
; /* arch name */
137 unsigned int len
; /* arch string length */
138 enum processor_type type
; /* arch type */
139 i386_cpu_flags flags
; /* cpu feature flags */
140 unsigned int skip
; /* show_arch should skip this. */
141 unsigned int negated
; /* turn off indicated flags. */
145 static void update_code_flag (int, int);
146 static void set_code_flag (int);
147 static void set_16bit_gcc_code_flag (int);
148 static void set_intel_syntax (int);
149 static void set_intel_mnemonic (int);
150 static void set_allow_index_reg (int);
151 static void set_check (int);
152 static void set_cpu_arch (int);
154 static void pe_directive_secrel (int);
156 static void signed_cons (int);
157 static char *output_invalid (int c
);
158 static int i386_finalize_immediate (segT
, expressionS
*, i386_operand_type
,
160 static int i386_finalize_displacement (segT
, expressionS
*, i386_operand_type
,
162 static int i386_att_operand (char *);
163 static int i386_intel_operand (char *, int);
164 static int i386_intel_simplify (expressionS
*);
165 static int i386_intel_parse_name (const char *, expressionS
*);
166 static const reg_entry
*parse_register (char *, char **);
167 static char *parse_insn (char *, char *);
168 static char *parse_operands (char *, const char *);
169 static void swap_operands (void);
170 static void swap_2_operands (int, int);
171 static void optimize_imm (void);
172 static void optimize_disp (void);
173 static const insn_template
*match_template (void);
174 static int check_string (void);
175 static int process_suffix (void);
176 static int check_byte_reg (void);
177 static int check_long_reg (void);
178 static int check_qword_reg (void);
179 static int check_word_reg (void);
180 static int finalize_imm (void);
181 static int process_operands (void);
182 static const seg_entry
*build_modrm_byte (void);
183 static void output_insn (void);
184 static void output_imm (fragS
*, offsetT
);
185 static void output_disp (fragS
*, offsetT
);
187 static void s_bss (int);
189 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
190 static void handle_large_common (int small ATTRIBUTE_UNUSED
);
193 static const char *default_arch
= DEFAULT_ARCH
;
195 /* This struct describes rounding control and SAE in the instruction. */
209 static struct RC_Operation rc_op
;
211 /* The struct describes masking, applied to OPERAND in the instruction.
212 MASK is a pointer to the corresponding mask register. ZEROING tells
213 whether merging or zeroing mask is used. */
214 struct Mask_Operation
216 const reg_entry
*mask
;
217 unsigned int zeroing
;
218 /* The operand where this operation is associated. */
222 static struct Mask_Operation mask_op
;
224 /* The struct describes broadcasting, applied to OPERAND. FACTOR is
226 struct Broadcast_Operation
228 /* Type of broadcast: no broadcast, {1to8}, or {1to16}. */
231 /* Index of broadcasted operand. */
235 static struct Broadcast_Operation broadcast_op
;
240 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
241 unsigned char bytes
[4];
243 /* Destination or source register specifier. */
244 const reg_entry
*register_specifier
;
247 /* 'md_assemble ()' gathers together information and puts it into a
254 const reg_entry
*regs
;
259 operand_size_mismatch
,
260 operand_type_mismatch
,
261 register_type_mismatch
,
262 number_of_operands_mismatch
,
263 invalid_instruction_suffix
,
266 unsupported_with_intel_mnemonic
,
269 invalid_vsib_address
,
270 invalid_vector_register_set
,
271 unsupported_vector_index_register
,
272 unsupported_broadcast
,
273 broadcast_not_on_src_operand
,
276 mask_not_on_destination
,
279 rc_sae_operand_not_last_imm
,
280 invalid_register_operand
,
286 /* TM holds the template for the insn were currently assembling. */
289 /* SUFFIX holds the instruction size suffix for byte, word, dword
290 or qword, if given. */
293 /* OPERANDS gives the number of given operands. */
294 unsigned int operands
;
296 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
297 of given register, displacement, memory operands and immediate
299 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
301 /* TYPES [i] is the type (see above #defines) which tells us how to
302 use OP[i] for the corresponding operand. */
303 i386_operand_type types
[MAX_OPERANDS
];
305 /* Displacement expression, immediate expression, or register for each
307 union i386_op op
[MAX_OPERANDS
];
309 /* Flags for operands. */
310 unsigned int flags
[MAX_OPERANDS
];
311 #define Operand_PCrel 1
313 /* Relocation type for operand */
314 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
316 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
317 the base index byte below. */
318 const reg_entry
*base_reg
;
319 const reg_entry
*index_reg
;
320 unsigned int log2_scale_factor
;
322 /* SEG gives the seg_entries of this insn. They are zero unless
323 explicit segment overrides are given. */
324 const seg_entry
*seg
[2];
326 /* PREFIX holds all the given prefix opcodes (usually null).
327 PREFIXES is the number of prefix opcodes. */
328 unsigned int prefixes
;
329 unsigned char prefix
[MAX_PREFIXES
];
331 /* RM and SIB are the modrm byte and the sib byte where the
332 addressing modes of this insn are encoded. */
339 /* Masking attributes. */
340 struct Mask_Operation
*mask
;
342 /* Rounding control and SAE attributes. */
343 struct RC_Operation
*rounding
;
345 /* Broadcasting attributes. */
346 struct Broadcast_Operation
*broadcast
;
348 /* Compressed disp8*N attribute. */
349 unsigned int memshift
;
351 /* Swap operand in encoding. */
352 unsigned int swap_operand
;
354 /* Prefer 8bit or 32bit displacement in encoding. */
357 disp_encoding_default
= 0,
363 const char *rep_prefix
;
366 const char *hle_prefix
;
368 /* Have BND prefix. */
369 const char *bnd_prefix
;
371 /* Need VREX to support upper 16 registers. */
375 enum i386_error error
;
378 typedef struct _i386_insn i386_insn
;
380 /* Link RC type with corresponding string, that'll be looked for in
389 static const struct RC_name RC_NamesTable
[] =
391 { rne
, STRING_COMMA_LEN ("rn-sae") },
392 { rd
, STRING_COMMA_LEN ("rd-sae") },
393 { ru
, STRING_COMMA_LEN ("ru-sae") },
394 { rz
, STRING_COMMA_LEN ("rz-sae") },
395 { saeonly
, STRING_COMMA_LEN ("sae") },
398 /* List of chars besides those in app.c:symbol_chars that can start an
399 operand. Used to prevent the scrubber eating vital white-space. */
400 const char extra_symbol_chars
[] = "*%-([{"
409 #if (defined (TE_I386AIX) \
410 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
411 && !defined (TE_GNU) \
412 && !defined (TE_LINUX) \
413 && !defined (TE_NACL) \
414 && !defined (TE_NETWARE) \
415 && !defined (TE_FreeBSD) \
416 && !defined (TE_DragonFly) \
417 && !defined (TE_NetBSD)))
418 /* This array holds the chars that always start a comment. If the
419 pre-processor is disabled, these aren't very useful. The option
420 --divide will remove '/' from this list. */
421 const char *i386_comment_chars
= "#/";
422 #define SVR4_COMMENT_CHARS 1
423 #define PREFIX_SEPARATOR '\\'
426 const char *i386_comment_chars
= "#";
427 #define PREFIX_SEPARATOR '/'
430 /* This array holds the chars that only start a comment at the beginning of
431 a line. If the line seems to have the form '# 123 filename'
432 .line and .file directives will appear in the pre-processed output.
433 Note that input_file.c hand checks for '#' at the beginning of the
434 first line of the input file. This is because the compiler outputs
435 #NO_APP at the beginning of its output.
436 Also note that comments started like this one will always work if
437 '/' isn't otherwise defined. */
438 const char line_comment_chars
[] = "#/";
440 const char line_separator_chars
[] = ";";
442 /* Chars that can be used to separate mant from exp in floating point
444 const char EXP_CHARS
[] = "eE";
446 /* Chars that mean this number is a floating point constant
449 const char FLT_CHARS
[] = "fFdDxX";
451 /* Tables for lexical analysis. */
452 static char mnemonic_chars
[256];
453 static char register_chars
[256];
454 static char operand_chars
[256];
455 static char identifier_chars
[256];
456 static char digit_chars
[256];
458 /* Lexical macros. */
459 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
460 #define is_operand_char(x) (operand_chars[(unsigned char) x])
461 #define is_register_char(x) (register_chars[(unsigned char) x])
462 #define is_space_char(x) ((x) == ' ')
463 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
464 #define is_digit_char(x) (digit_chars[(unsigned char) x])
466 /* All non-digit non-letter characters that may occur in an operand. */
467 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
469 /* md_assemble() always leaves the strings it's passed unaltered. To
470 effect this we maintain a stack of saved characters that we've smashed
471 with '\0's (indicating end of strings for various sub-fields of the
472 assembler instruction). */
473 static char save_stack
[32];
474 static char *save_stack_p
;
475 #define END_STRING_AND_SAVE(s) \
476 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
477 #define RESTORE_END_STRING(s) \
478 do { *(s) = *--save_stack_p; } while (0)
480 /* The instruction we're assembling. */
483 /* Possible templates for current insn. */
484 static const templates
*current_templates
;
486 /* Per instruction expressionS buffers: max displacements & immediates. */
487 static expressionS disp_expressions
[MAX_MEMORY_OPERANDS
];
488 static expressionS im_expressions
[MAX_IMMEDIATE_OPERANDS
];
490 /* Current operand we are working on. */
491 static int this_operand
= -1;
493 /* We support four different modes. FLAG_CODE variable is used to distinguish
501 static enum flag_code flag_code
;
502 static unsigned int object_64bit
;
503 static unsigned int disallow_64bit_reloc
;
504 static int use_rela_relocations
= 0;
506 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
507 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
508 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
510 /* The ELF ABI to use. */
518 static enum x86_elf_abi x86_elf_abi
= I386_ABI
;
521 #if defined (TE_PE) || defined (TE_PEP)
522 /* Use big object file format. */
523 static int use_big_obj
= 0;
526 /* 1 for intel syntax,
528 static int intel_syntax
= 0;
530 /* 1 for intel mnemonic,
531 0 if att mnemonic. */
532 static int intel_mnemonic
= !SYSV386_COMPAT
;
534 /* 1 if support old (<= 2.8.1) versions of gcc. */
535 static int old_gcc
= OLDGCC_COMPAT
;
537 /* 1 if pseudo registers are permitted. */
538 static int allow_pseudo_reg
= 0;
540 /* 1 if register prefix % not required. */
541 static int allow_naked_reg
= 0;
543 /* 1 if the assembler should add BND prefix for all control-tranferring
544 instructions supporting it, even if this prefix wasn't specified
546 static int add_bnd_prefix
= 0;
548 /* 1 if pseudo index register, eiz/riz, is allowed . */
549 static int allow_index_reg
= 0;
551 /* 1 if the assembler should ignore LOCK prefix, even if it was
552 specified explicitly. */
553 static int omit_lock_prefix
= 0;
555 static enum check_kind
561 sse_check
, operand_check
= check_warning
;
563 /* Register prefix used for error message. */
564 static const char *register_prefix
= "%";
566 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
567 leave, push, and pop instructions so that gcc has the same stack
568 frame as in 32 bit mode. */
569 static char stackop_size
= '\0';
571 /* Non-zero to optimize code alignment. */
572 int optimize_align_code
= 1;
574 /* Non-zero to quieten some warnings. */
575 static int quiet_warnings
= 0;
578 static const char *cpu_arch_name
= NULL
;
579 static char *cpu_sub_arch_name
= NULL
;
581 /* CPU feature flags. */
582 static i386_cpu_flags cpu_arch_flags
= CPU_UNKNOWN_FLAGS
;
584 /* If we have selected a cpu we are generating instructions for. */
585 static int cpu_arch_tune_set
= 0;
587 /* Cpu we are generating instructions for. */
588 enum processor_type cpu_arch_tune
= PROCESSOR_UNKNOWN
;
590 /* CPU feature flags of cpu we are generating instructions for. */
591 static i386_cpu_flags cpu_arch_tune_flags
;
593 /* CPU instruction set architecture used. */
594 enum processor_type cpu_arch_isa
= PROCESSOR_UNKNOWN
;
596 /* CPU feature flags of instruction set architecture used. */
597 i386_cpu_flags cpu_arch_isa_flags
;
599 /* If set, conditional jumps are not automatically promoted to handle
600 larger than a byte offset. */
601 static unsigned int no_cond_jump_promotion
= 0;
603 /* Encode SSE instructions with VEX prefix. */
604 static unsigned int sse2avx
;
606 /* Encode scalar AVX instructions with specific vector length. */
613 /* Encode scalar EVEX LIG instructions with specific vector length. */
621 /* Encode EVEX WIG instructions with specific evex.w. */
628 /* Value to encode in EVEX RC bits, for SAE-only instructions. */
629 static enum rc_type evexrcig
= rne
;
631 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
632 static symbolS
*GOT_symbol
;
634 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
635 unsigned int x86_dwarf2_return_column
;
637 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
638 int x86_cie_data_alignment
;
640 /* Interface to relax_segment.
641 There are 3 major relax states for 386 jump insns because the
642 different types of jumps add different sizes to frags when we're
643 figuring out what sort of jump to choose to reach a given label. */
646 #define UNCOND_JUMP 0
648 #define COND_JUMP86 2
653 #define SMALL16 (SMALL | CODE16)
655 #define BIG16 (BIG | CODE16)
659 #define INLINE __inline__
665 #define ENCODE_RELAX_STATE(type, size) \
666 ((relax_substateT) (((type) << 2) | (size)))
667 #define TYPE_FROM_RELAX_STATE(s) \
669 #define DISP_SIZE_FROM_RELAX_STATE(s) \
670 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
672 /* This table is used by relax_frag to promote short jumps to long
673 ones where necessary. SMALL (short) jumps may be promoted to BIG
674 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
675 don't allow a short jump in a 32 bit code segment to be promoted to
676 a 16 bit offset jump because it's slower (requires data size
677 prefix), and doesn't work, unless the destination is in the bottom
678 64k of the code segment (The top 16 bits of eip are zeroed). */
680 const relax_typeS md_relax_table
[] =
683 1) most positive reach of this state,
684 2) most negative reach of this state,
685 3) how many bytes this mode will have in the variable part of the frag
686 4) which index into the table to try if we can't fit into this one. */
688 /* UNCOND_JUMP states. */
689 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
690 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
691 /* dword jmp adds 4 bytes to frag:
692 0 extra opcode bytes, 4 displacement bytes. */
694 /* word jmp adds 2 byte2 to frag:
695 0 extra opcode bytes, 2 displacement bytes. */
698 /* COND_JUMP states. */
699 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
700 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
701 /* dword conditionals adds 5 bytes to frag:
702 1 extra opcode byte, 4 displacement bytes. */
704 /* word conditionals add 3 bytes to frag:
705 1 extra opcode byte, 2 displacement bytes. */
708 /* COND_JUMP86 states. */
709 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
710 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
711 /* dword conditionals adds 5 bytes to frag:
712 1 extra opcode byte, 4 displacement bytes. */
714 /* word conditionals add 4 bytes to frag:
715 1 displacement byte and a 3 byte long branch insn. */
719 static const arch_entry cpu_arch
[] =
721 /* Do not replace the first two entries - i386_target_format()
722 relies on them being there in this order. */
723 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32
,
724 CPU_GENERIC32_FLAGS
, 0, 0 },
725 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64
,
726 CPU_GENERIC64_FLAGS
, 0, 0 },
727 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN
,
728 CPU_NONE_FLAGS
, 0, 0 },
729 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN
,
730 CPU_I186_FLAGS
, 0, 0 },
731 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN
,
732 CPU_I286_FLAGS
, 0, 0 },
733 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386
,
734 CPU_I386_FLAGS
, 0, 0 },
735 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486
,
736 CPU_I486_FLAGS
, 0, 0 },
737 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM
,
738 CPU_I586_FLAGS
, 0, 0 },
739 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO
,
740 CPU_I686_FLAGS
, 0, 0 },
741 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM
,
742 CPU_I586_FLAGS
, 0, 0 },
743 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO
,
744 CPU_PENTIUMPRO_FLAGS
, 0, 0 },
745 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO
,
746 CPU_P2_FLAGS
, 0, 0 },
747 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO
,
748 CPU_P3_FLAGS
, 0, 0 },
749 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4
,
750 CPU_P4_FLAGS
, 0, 0 },
751 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA
,
752 CPU_CORE_FLAGS
, 0, 0 },
753 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA
,
754 CPU_NOCONA_FLAGS
, 0, 0 },
755 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE
,
756 CPU_CORE_FLAGS
, 1, 0 },
757 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE
,
758 CPU_CORE_FLAGS
, 0, 0 },
759 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2
,
760 CPU_CORE2_FLAGS
, 1, 0 },
761 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2
,
762 CPU_CORE2_FLAGS
, 0, 0 },
763 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7
,
764 CPU_COREI7_FLAGS
, 0, 0 },
765 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM
,
766 CPU_L1OM_FLAGS
, 0, 0 },
767 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM
,
768 CPU_K1OM_FLAGS
, 0, 0 },
769 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6
,
770 CPU_K6_FLAGS
, 0, 0 },
771 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6
,
772 CPU_K6_2_FLAGS
, 0, 0 },
773 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON
,
774 CPU_ATHLON_FLAGS
, 0, 0 },
775 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8
,
776 CPU_K8_FLAGS
, 1, 0 },
777 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8
,
778 CPU_K8_FLAGS
, 0, 0 },
779 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8
,
780 CPU_K8_FLAGS
, 0, 0 },
781 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10
,
782 CPU_AMDFAM10_FLAGS
, 0, 0 },
783 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD
,
784 CPU_BDVER1_FLAGS
, 0, 0 },
785 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD
,
786 CPU_BDVER2_FLAGS
, 0, 0 },
787 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD
,
788 CPU_BDVER3_FLAGS
, 0, 0 },
789 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD
,
790 CPU_BDVER4_FLAGS
, 0, 0 },
791 { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER
,
792 CPU_ZNVER1_FLAGS
, 0, 0 },
793 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT
,
794 CPU_BTVER1_FLAGS
, 0, 0 },
795 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT
,
796 CPU_BTVER2_FLAGS
, 0, 0 },
797 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN
,
798 CPU_8087_FLAGS
, 0, 0 },
799 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN
,
800 CPU_287_FLAGS
, 0, 0 },
801 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN
,
802 CPU_387_FLAGS
, 0, 0 },
803 { STRING_COMMA_LEN (".no87"), PROCESSOR_UNKNOWN
,
804 CPU_ANY87_FLAGS
, 0, 1 },
805 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN
,
806 CPU_MMX_FLAGS
, 0, 0 },
807 { STRING_COMMA_LEN (".nommx"), PROCESSOR_UNKNOWN
,
808 CPU_3DNOWA_FLAGS
, 0, 1 },
809 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN
,
810 CPU_SSE_FLAGS
, 0, 0 },
811 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN
,
812 CPU_SSE2_FLAGS
, 0, 0 },
813 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN
,
814 CPU_SSE3_FLAGS
, 0, 0 },
815 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN
,
816 CPU_SSSE3_FLAGS
, 0, 0 },
817 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN
,
818 CPU_SSE4_1_FLAGS
, 0, 0 },
819 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN
,
820 CPU_SSE4_2_FLAGS
, 0, 0 },
821 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN
,
822 CPU_SSE4_2_FLAGS
, 0, 0 },
823 { STRING_COMMA_LEN (".nosse"), PROCESSOR_UNKNOWN
,
824 CPU_ANY_SSE_FLAGS
, 0, 1 },
825 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN
,
826 CPU_AVX_FLAGS
, 0, 0 },
827 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN
,
828 CPU_AVX2_FLAGS
, 0, 0 },
829 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN
,
830 CPU_AVX512F_FLAGS
, 0, 0 },
831 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN
,
832 CPU_AVX512CD_FLAGS
, 0, 0 },
833 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN
,
834 CPU_AVX512ER_FLAGS
, 0, 0 },
835 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN
,
836 CPU_AVX512PF_FLAGS
, 0, 0 },
837 { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN
,
838 CPU_AVX512DQ_FLAGS
, 0, 0 },
839 { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN
,
840 CPU_AVX512BW_FLAGS
, 0, 0 },
841 { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN
,
842 CPU_AVX512VL_FLAGS
, 0, 0 },
843 { STRING_COMMA_LEN (".noavx"), PROCESSOR_UNKNOWN
,
844 CPU_ANY_AVX_FLAGS
, 0, 1 },
845 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN
,
846 CPU_VMX_FLAGS
, 0, 0 },
847 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN
,
848 CPU_VMFUNC_FLAGS
, 0, 0 },
849 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN
,
850 CPU_SMX_FLAGS
, 0, 0 },
851 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN
,
852 CPU_XSAVE_FLAGS
, 0, 0 },
853 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN
,
854 CPU_XSAVEOPT_FLAGS
, 0, 0 },
855 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN
,
856 CPU_XSAVEC_FLAGS
, 0, 0 },
857 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN
,
858 CPU_XSAVES_FLAGS
, 0, 0 },
859 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN
,
860 CPU_AES_FLAGS
, 0, 0 },
861 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN
,
862 CPU_PCLMUL_FLAGS
, 0, 0 },
863 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN
,
864 CPU_PCLMUL_FLAGS
, 1, 0 },
865 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN
,
866 CPU_FSGSBASE_FLAGS
, 0, 0 },
867 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN
,
868 CPU_RDRND_FLAGS
, 0, 0 },
869 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN
,
870 CPU_F16C_FLAGS
, 0, 0 },
871 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN
,
872 CPU_BMI2_FLAGS
, 0, 0 },
873 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN
,
874 CPU_FMA_FLAGS
, 0, 0 },
875 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN
,
876 CPU_FMA4_FLAGS
, 0, 0 },
877 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN
,
878 CPU_XOP_FLAGS
, 0, 0 },
879 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN
,
880 CPU_LWP_FLAGS
, 0, 0 },
881 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN
,
882 CPU_MOVBE_FLAGS
, 0, 0 },
883 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN
,
884 CPU_CX16_FLAGS
, 0, 0 },
885 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN
,
886 CPU_EPT_FLAGS
, 0, 0 },
887 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN
,
888 CPU_LZCNT_FLAGS
, 0, 0 },
889 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN
,
890 CPU_HLE_FLAGS
, 0, 0 },
891 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN
,
892 CPU_RTM_FLAGS
, 0, 0 },
893 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN
,
894 CPU_INVPCID_FLAGS
, 0, 0 },
895 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN
,
896 CPU_CLFLUSH_FLAGS
, 0, 0 },
897 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN
,
898 CPU_NOP_FLAGS
, 0, 0 },
899 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN
,
900 CPU_SYSCALL_FLAGS
, 0, 0 },
901 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN
,
902 CPU_RDTSCP_FLAGS
, 0, 0 },
903 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN
,
904 CPU_3DNOW_FLAGS
, 0, 0 },
905 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN
,
906 CPU_3DNOWA_FLAGS
, 0, 0 },
907 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN
,
908 CPU_PADLOCK_FLAGS
, 0, 0 },
909 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN
,
910 CPU_SVME_FLAGS
, 1, 0 },
911 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN
,
912 CPU_SVME_FLAGS
, 0, 0 },
913 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN
,
914 CPU_SSE4A_FLAGS
, 0, 0 },
915 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN
,
916 CPU_ABM_FLAGS
, 0, 0 },
917 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN
,
918 CPU_BMI_FLAGS
, 0, 0 },
919 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN
,
920 CPU_TBM_FLAGS
, 0, 0 },
921 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN
,
922 CPU_ADX_FLAGS
, 0, 0 },
923 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN
,
924 CPU_RDSEED_FLAGS
, 0, 0 },
925 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN
,
926 CPU_PRFCHW_FLAGS
, 0, 0 },
927 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN
,
928 CPU_SMAP_FLAGS
, 0, 0 },
929 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN
,
930 CPU_MPX_FLAGS
, 0, 0 },
931 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN
,
932 CPU_SHA_FLAGS
, 0, 0 },
933 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN
,
934 CPU_CLFLUSHOPT_FLAGS
, 0, 0 },
935 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN
,
936 CPU_PREFETCHWT1_FLAGS
, 0, 0 },
937 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN
,
938 CPU_SE1_FLAGS
, 0, 0 },
939 { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN
,
940 CPU_CLWB_FLAGS
, 0, 0 },
941 { STRING_COMMA_LEN (".pcommit"), PROCESSOR_UNKNOWN
,
942 CPU_PCOMMIT_FLAGS
, 0, 0 },
943 { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN
,
944 CPU_AVX512IFMA_FLAGS
, 0, 0 },
945 { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN
,
946 CPU_AVX512VBMI_FLAGS
, 0, 0 },
947 { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN
,
948 CPU_CLZERO_FLAGS
, 0, 0 },
952 /* Like s_lcomm_internal in gas/read.c but the alignment string
953 is allowed to be optional. */
956 pe_lcomm_internal (int needs_align
, symbolS
*symbolP
, addressT size
)
963 && *input_line_pointer
== ',')
965 align
= parse_align (needs_align
- 1);
967 if (align
== (addressT
) -1)
982 bss_alloc (symbolP
, size
, align
);
987 pe_lcomm (int needs_align
)
989 s_comm_internal (needs_align
* 2, pe_lcomm_internal
);
993 const pseudo_typeS md_pseudo_table
[] =
995 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
996 {"align", s_align_bytes
, 0},
998 {"align", s_align_ptwo
, 0},
1000 {"arch", set_cpu_arch
, 0},
1004 {"lcomm", pe_lcomm
, 1},
1006 {"ffloat", float_cons
, 'f'},
1007 {"dfloat", float_cons
, 'd'},
1008 {"tfloat", float_cons
, 'x'},
1010 {"slong", signed_cons
, 4},
1011 {"noopt", s_ignore
, 0},
1012 {"optim", s_ignore
, 0},
1013 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
1014 {"code16", set_code_flag
, CODE_16BIT
},
1015 {"code32", set_code_flag
, CODE_32BIT
},
1016 {"code64", set_code_flag
, CODE_64BIT
},
1017 {"intel_syntax", set_intel_syntax
, 1},
1018 {"att_syntax", set_intel_syntax
, 0},
1019 {"intel_mnemonic", set_intel_mnemonic
, 1},
1020 {"att_mnemonic", set_intel_mnemonic
, 0},
1021 {"allow_index_reg", set_allow_index_reg
, 1},
1022 {"disallow_index_reg", set_allow_index_reg
, 0},
1023 {"sse_check", set_check
, 0},
1024 {"operand_check", set_check
, 1},
1025 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1026 {"largecomm", handle_large_common
, 0},
1028 {"file", (void (*) (int)) dwarf2_directive_file
, 0},
1029 {"loc", dwarf2_directive_loc
, 0},
1030 {"loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0},
1033 {"secrel32", pe_directive_secrel
, 0},
1038 /* For interface with expression (). */
1039 extern char *input_line_pointer
;
1041 /* Hash table for instruction mnemonic lookup. */
1042 static struct hash_control
*op_hash
;
1044 /* Hash table for register lookup. */
1045 static struct hash_control
*reg_hash
;
1048 i386_align_code (fragS
*fragP
, int count
)
1050 /* Various efficient no-op patterns for aligning code labels.
1051 Note: Don't try to assemble the instructions in the comments.
1052 0L and 0w are not legal. */
1053 static const char f32_1
[] =
1055 static const char f32_2
[] =
1056 {0x66,0x90}; /* xchg %ax,%ax */
1057 static const char f32_3
[] =
1058 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1059 static const char f32_4
[] =
1060 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1061 static const char f32_5
[] =
1063 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1064 static const char f32_6
[] =
1065 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1066 static const char f32_7
[] =
1067 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1068 static const char f32_8
[] =
1070 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1071 static const char f32_9
[] =
1072 {0x89,0xf6, /* movl %esi,%esi */
1073 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1074 static const char f32_10
[] =
1075 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
1076 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1077 static const char f32_11
[] =
1078 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
1079 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1080 static const char f32_12
[] =
1081 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1082 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
1083 static const char f32_13
[] =
1084 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1085 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1086 static const char f32_14
[] =
1087 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
1088 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1089 static const char f16_3
[] =
1090 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
1091 static const char f16_4
[] =
1092 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
1093 static const char f16_5
[] =
1095 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
1096 static const char f16_6
[] =
1097 {0x89,0xf6, /* mov %si,%si */
1098 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1099 static const char f16_7
[] =
1100 {0x8d,0x74,0x00, /* lea 0(%si),%si */
1101 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1102 static const char f16_8
[] =
1103 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
1104 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1105 static const char jump_31
[] =
1106 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
1107 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1108 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1109 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
1110 static const char *const f32_patt
[] = {
1111 f32_1
, f32_2
, f32_3
, f32_4
, f32_5
, f32_6
, f32_7
, f32_8
,
1112 f32_9
, f32_10
, f32_11
, f32_12
, f32_13
, f32_14
1114 static const char *const f16_patt
[] = {
1115 f32_1
, f32_2
, f16_3
, f16_4
, f16_5
, f16_6
, f16_7
, f16_8
1117 /* nopl (%[re]ax) */
1118 static const char alt_3
[] =
1120 /* nopl 0(%[re]ax) */
1121 static const char alt_4
[] =
1122 {0x0f,0x1f,0x40,0x00};
1123 /* nopl 0(%[re]ax,%[re]ax,1) */
1124 static const char alt_5
[] =
1125 {0x0f,0x1f,0x44,0x00,0x00};
1126 /* nopw 0(%[re]ax,%[re]ax,1) */
1127 static const char alt_6
[] =
1128 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1129 /* nopl 0L(%[re]ax) */
1130 static const char alt_7
[] =
1131 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1132 /* nopl 0L(%[re]ax,%[re]ax,1) */
1133 static const char alt_8
[] =
1134 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1135 /* nopw 0L(%[re]ax,%[re]ax,1) */
1136 static const char alt_9
[] =
1137 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1138 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1139 static const char alt_10
[] =
1140 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1142 nopw %cs:0L(%[re]ax,%[re]ax,1) */
1143 static const char alt_long_11
[] =
1145 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1148 nopw %cs:0L(%[re]ax,%[re]ax,1) */
1149 static const char alt_long_12
[] =
1152 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1156 nopw %cs:0L(%[re]ax,%[re]ax,1) */
1157 static const char alt_long_13
[] =
1161 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1166 nopw %cs:0L(%[re]ax,%[re]ax,1) */
1167 static const char alt_long_14
[] =
1172 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1178 nopw %cs:0L(%[re]ax,%[re]ax,1) */
1179 static const char alt_long_15
[] =
1185 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1186 /* nopl 0(%[re]ax,%[re]ax,1)
1187 nopw 0(%[re]ax,%[re]ax,1) */
1188 static const char alt_short_11
[] =
1189 {0x0f,0x1f,0x44,0x00,0x00,
1190 0x66,0x0f,0x1f,0x44,0x00,0x00};
1191 /* nopw 0(%[re]ax,%[re]ax,1)
1192 nopw 0(%[re]ax,%[re]ax,1) */
1193 static const char alt_short_12
[] =
1194 {0x66,0x0f,0x1f,0x44,0x00,0x00,
1195 0x66,0x0f,0x1f,0x44,0x00,0x00};
1196 /* nopw 0(%[re]ax,%[re]ax,1)
1198 static const char alt_short_13
[] =
1199 {0x66,0x0f,0x1f,0x44,0x00,0x00,
1200 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1203 static const char alt_short_14
[] =
1204 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
1205 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1207 nopl 0L(%[re]ax,%[re]ax,1) */
1208 static const char alt_short_15
[] =
1209 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
1210 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1211 static const char *const alt_short_patt
[] = {
1212 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
1213 alt_9
, alt_10
, alt_short_11
, alt_short_12
, alt_short_13
,
1214 alt_short_14
, alt_short_15
1216 static const char *const alt_long_patt
[] = {
1217 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
1218 alt_9
, alt_10
, alt_long_11
, alt_long_12
, alt_long_13
,
1219 alt_long_14
, alt_long_15
1222 /* Only align for at least a positive non-zero boundary. */
1223 if (count
<= 0 || count
> MAX_MEM_FOR_RS_ALIGN_CODE
)
1226 /* We need to decide which NOP sequence to use for 32bit and
1227 64bit. When -mtune= is used:
1229 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1230 PROCESSOR_GENERIC32, f32_patt will be used.
1231 2. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
1232 PROCESSOR_CORE, PROCESSOR_CORE2, PROCESSOR_COREI7, and
1233 PROCESSOR_GENERIC64, alt_long_patt will be used.
1234 3. For PROCESSOR_ATHLON, PROCESSOR_K6, PROCESSOR_K8 and
1235 PROCESSOR_AMDFAM10, PROCESSOR_BD and PROCESSOR_BT, alt_short_patt
1238 When -mtune= isn't used, alt_long_patt will be used if
1239 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
1242 When -march= or .arch is used, we can't use anything beyond
1243 cpu_arch_isa_flags. */
1245 if (flag_code
== CODE_16BIT
)
1249 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1251 /* Adjust jump offset. */
1252 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
1255 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1256 f16_patt
[count
- 1], count
);
1260 const char *const *patt
= NULL
;
1262 if (fragP
->tc_frag_data
.isa
== PROCESSOR_UNKNOWN
)
1264 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1265 switch (cpu_arch_tune
)
1267 case PROCESSOR_UNKNOWN
:
1268 /* We use cpu_arch_isa_flags to check if we SHOULD
1269 optimize with nops. */
1270 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1271 patt
= alt_long_patt
;
1275 case PROCESSOR_PENTIUM4
:
1276 case PROCESSOR_NOCONA
:
1277 case PROCESSOR_CORE
:
1278 case PROCESSOR_CORE2
:
1279 case PROCESSOR_COREI7
:
1280 case PROCESSOR_L1OM
:
1281 case PROCESSOR_K1OM
:
1282 case PROCESSOR_GENERIC64
:
1283 patt
= alt_long_patt
;
1286 case PROCESSOR_ATHLON
:
1288 case PROCESSOR_AMDFAM10
:
1290 case PROCESSOR_ZNVER
:
1292 patt
= alt_short_patt
;
1294 case PROCESSOR_I386
:
1295 case PROCESSOR_I486
:
1296 case PROCESSOR_PENTIUM
:
1297 case PROCESSOR_PENTIUMPRO
:
1298 case PROCESSOR_GENERIC32
:
1305 switch (fragP
->tc_frag_data
.tune
)
1307 case PROCESSOR_UNKNOWN
:
1308 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1309 PROCESSOR_UNKNOWN. */
1313 case PROCESSOR_I386
:
1314 case PROCESSOR_I486
:
1315 case PROCESSOR_PENTIUM
:
1317 case PROCESSOR_ATHLON
:
1319 case PROCESSOR_AMDFAM10
:
1321 case PROCESSOR_ZNVER
:
1323 case PROCESSOR_GENERIC32
:
1324 /* We use cpu_arch_isa_flags to check if we CAN optimize
1326 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1327 patt
= alt_short_patt
;
1331 case PROCESSOR_PENTIUMPRO
:
1332 case PROCESSOR_PENTIUM4
:
1333 case PROCESSOR_NOCONA
:
1334 case PROCESSOR_CORE
:
1335 case PROCESSOR_CORE2
:
1336 case PROCESSOR_COREI7
:
1337 case PROCESSOR_L1OM
:
1338 case PROCESSOR_K1OM
:
1339 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1340 patt
= alt_long_patt
;
1344 case PROCESSOR_GENERIC64
:
1345 patt
= alt_long_patt
;
1350 if (patt
== f32_patt
)
1352 /* If the padding is less than 15 bytes, we use the normal
1353 ones. Otherwise, we use a jump instruction and adjust
1357 /* For 64bit, the limit is 3 bytes. */
1358 if (flag_code
== CODE_64BIT
1359 && fragP
->tc_frag_data
.isa_flags
.bitfield
.cpulm
)
1364 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1365 patt
[count
- 1], count
);
1368 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1370 /* Adjust jump offset. */
1371 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
1376 /* Maximum length of an instruction is 15 byte. If the
1377 padding is greater than 15 bytes and we don't use jump,
1378 we have to break it into smaller pieces. */
1379 int padding
= count
;
1380 while (padding
> 15)
1383 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
+ padding
,
1388 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1389 patt
[padding
- 1], padding
);
1392 fragP
->fr_var
= count
;
1396 operand_type_all_zero (const union i386_operand_type
*x
)
1398 switch (ARRAY_SIZE(x
->array
))
1407 return !x
->array
[0];
1414 operand_type_set (union i386_operand_type
*x
, unsigned int v
)
1416 switch (ARRAY_SIZE(x
->array
))
1431 operand_type_equal (const union i386_operand_type
*x
,
1432 const union i386_operand_type
*y
)
1434 switch (ARRAY_SIZE(x
->array
))
1437 if (x
->array
[2] != y
->array
[2])
1440 if (x
->array
[1] != y
->array
[1])
1443 return x
->array
[0] == y
->array
[0];
1451 cpu_flags_all_zero (const union i386_cpu_flags
*x
)
1453 switch (ARRAY_SIZE(x
->array
))
1462 return !x
->array
[0];
1469 cpu_flags_set (union i386_cpu_flags
*x
, unsigned int v
)
1471 switch (ARRAY_SIZE(x
->array
))
1486 cpu_flags_equal (const union i386_cpu_flags
*x
,
1487 const union i386_cpu_flags
*y
)
1489 switch (ARRAY_SIZE(x
->array
))
1492 if (x
->array
[2] != y
->array
[2])
1495 if (x
->array
[1] != y
->array
[1])
1498 return x
->array
[0] == y
->array
[0];
1506 cpu_flags_check_cpu64 (i386_cpu_flags f
)
1508 return !((flag_code
== CODE_64BIT
&& f
.bitfield
.cpuno64
)
1509 || (flag_code
!= CODE_64BIT
&& f
.bitfield
.cpu64
));
1512 static INLINE i386_cpu_flags
1513 cpu_flags_and (i386_cpu_flags x
, i386_cpu_flags y
)
1515 switch (ARRAY_SIZE (x
.array
))
1518 x
.array
[2] &= y
.array
[2];
1520 x
.array
[1] &= y
.array
[1];
1522 x
.array
[0] &= y
.array
[0];
1530 static INLINE i386_cpu_flags
1531 cpu_flags_or (i386_cpu_flags x
, i386_cpu_flags y
)
1533 switch (ARRAY_SIZE (x
.array
))
1536 x
.array
[2] |= y
.array
[2];
1538 x
.array
[1] |= y
.array
[1];
1540 x
.array
[0] |= y
.array
[0];
1548 static INLINE i386_cpu_flags
1549 cpu_flags_and_not (i386_cpu_flags x
, i386_cpu_flags y
)
1551 switch (ARRAY_SIZE (x
.array
))
1554 x
.array
[2] &= ~y
.array
[2];
1556 x
.array
[1] &= ~y
.array
[1];
1558 x
.array
[0] &= ~y
.array
[0];
1566 #define CPU_FLAGS_ARCH_MATCH 0x1
1567 #define CPU_FLAGS_64BIT_MATCH 0x2
1568 #define CPU_FLAGS_AES_MATCH 0x4
1569 #define CPU_FLAGS_PCLMUL_MATCH 0x8
1570 #define CPU_FLAGS_AVX_MATCH 0x10
1572 #define CPU_FLAGS_32BIT_MATCH \
1573 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH \
1574 | CPU_FLAGS_PCLMUL_MATCH | CPU_FLAGS_AVX_MATCH)
1575 #define CPU_FLAGS_PERFECT_MATCH \
1576 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)
1578 /* Return CPU flags match bits. */
1581 cpu_flags_match (const insn_template
*t
)
1583 i386_cpu_flags x
= t
->cpu_flags
;
1584 int match
= cpu_flags_check_cpu64 (x
) ? CPU_FLAGS_64BIT_MATCH
: 0;
1586 x
.bitfield
.cpu64
= 0;
1587 x
.bitfield
.cpuno64
= 0;
1589 if (cpu_flags_all_zero (&x
))
1591 /* This instruction is available on all archs. */
1592 match
|= CPU_FLAGS_32BIT_MATCH
;
1596 /* This instruction is available only on some archs. */
1597 i386_cpu_flags cpu
= cpu_arch_flags
;
1599 cpu
.bitfield
.cpu64
= 0;
1600 cpu
.bitfield
.cpuno64
= 0;
1601 cpu
= cpu_flags_and (x
, cpu
);
1602 if (!cpu_flags_all_zero (&cpu
))
1604 if (x
.bitfield
.cpuavx
)
1606 /* We only need to check AES/PCLMUL/SSE2AVX with AVX. */
1607 if (cpu
.bitfield
.cpuavx
)
1609 /* Check SSE2AVX. */
1610 if (!t
->opcode_modifier
.sse2avx
|| sse2avx
)
1612 match
|= (CPU_FLAGS_ARCH_MATCH
1613 | CPU_FLAGS_AVX_MATCH
);
1615 if (!x
.bitfield
.cpuaes
|| cpu
.bitfield
.cpuaes
)
1616 match
|= CPU_FLAGS_AES_MATCH
;
1618 if (!x
.bitfield
.cpupclmul
1619 || cpu
.bitfield
.cpupclmul
)
1620 match
|= CPU_FLAGS_PCLMUL_MATCH
;
1624 match
|= CPU_FLAGS_ARCH_MATCH
;
1627 match
|= CPU_FLAGS_32BIT_MATCH
;
1633 static INLINE i386_operand_type
1634 operand_type_and (i386_operand_type x
, i386_operand_type y
)
1636 switch (ARRAY_SIZE (x
.array
))
1639 x
.array
[2] &= y
.array
[2];
1641 x
.array
[1] &= y
.array
[1];
1643 x
.array
[0] &= y
.array
[0];
1651 static INLINE i386_operand_type
1652 operand_type_or (i386_operand_type x
, i386_operand_type y
)
1654 switch (ARRAY_SIZE (x
.array
))
1657 x
.array
[2] |= y
.array
[2];
1659 x
.array
[1] |= y
.array
[1];
1661 x
.array
[0] |= y
.array
[0];
1669 static INLINE i386_operand_type
1670 operand_type_xor (i386_operand_type x
, i386_operand_type y
)
1672 switch (ARRAY_SIZE (x
.array
))
1675 x
.array
[2] ^= y
.array
[2];
1677 x
.array
[1] ^= y
.array
[1];
1679 x
.array
[0] ^= y
.array
[0];
1687 static const i386_operand_type acc32
= OPERAND_TYPE_ACC32
;
1688 static const i386_operand_type acc64
= OPERAND_TYPE_ACC64
;
1689 static const i386_operand_type control
= OPERAND_TYPE_CONTROL
;
1690 static const i386_operand_type inoutportreg
1691 = OPERAND_TYPE_INOUTPORTREG
;
1692 static const i386_operand_type reg16_inoutportreg
1693 = OPERAND_TYPE_REG16_INOUTPORTREG
;
1694 static const i386_operand_type disp16
= OPERAND_TYPE_DISP16
;
1695 static const i386_operand_type disp32
= OPERAND_TYPE_DISP32
;
1696 static const i386_operand_type disp32s
= OPERAND_TYPE_DISP32S
;
1697 static const i386_operand_type disp16_32
= OPERAND_TYPE_DISP16_32
;
1698 static const i386_operand_type anydisp
1699 = OPERAND_TYPE_ANYDISP
;
1700 static const i386_operand_type regxmm
= OPERAND_TYPE_REGXMM
;
1701 static const i386_operand_type regymm
= OPERAND_TYPE_REGYMM
;
1702 static const i386_operand_type regzmm
= OPERAND_TYPE_REGZMM
;
1703 static const i386_operand_type regmask
= OPERAND_TYPE_REGMASK
;
1704 static const i386_operand_type imm8
= OPERAND_TYPE_IMM8
;
1705 static const i386_operand_type imm8s
= OPERAND_TYPE_IMM8S
;
1706 static const i386_operand_type imm16
= OPERAND_TYPE_IMM16
;
1707 static const i386_operand_type imm32
= OPERAND_TYPE_IMM32
;
1708 static const i386_operand_type imm32s
= OPERAND_TYPE_IMM32S
;
1709 static const i386_operand_type imm64
= OPERAND_TYPE_IMM64
;
1710 static const i386_operand_type imm16_32
= OPERAND_TYPE_IMM16_32
;
1711 static const i386_operand_type imm16_32s
= OPERAND_TYPE_IMM16_32S
;
1712 static const i386_operand_type imm16_32_32s
= OPERAND_TYPE_IMM16_32_32S
;
1713 static const i386_operand_type vec_imm4
= OPERAND_TYPE_VEC_IMM4
;
1724 operand_type_check (i386_operand_type t
, enum operand_type c
)
1729 return (t
.bitfield
.reg8
1732 || t
.bitfield
.reg64
);
1735 return (t
.bitfield
.imm8
1739 || t
.bitfield
.imm32s
1740 || t
.bitfield
.imm64
);
1743 return (t
.bitfield
.disp8
1744 || t
.bitfield
.disp16
1745 || t
.bitfield
.disp32
1746 || t
.bitfield
.disp32s
1747 || t
.bitfield
.disp64
);
1750 return (t
.bitfield
.disp8
1751 || t
.bitfield
.disp16
1752 || t
.bitfield
.disp32
1753 || t
.bitfield
.disp32s
1754 || t
.bitfield
.disp64
1755 || t
.bitfield
.baseindex
);
1764 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1765 operand J for instruction template T. */
1768 match_reg_size (const insn_template
*t
, unsigned int j
)
1770 return !((i
.types
[j
].bitfield
.byte
1771 && !t
->operand_types
[j
].bitfield
.byte
)
1772 || (i
.types
[j
].bitfield
.word
1773 && !t
->operand_types
[j
].bitfield
.word
)
1774 || (i
.types
[j
].bitfield
.dword
1775 && !t
->operand_types
[j
].bitfield
.dword
)
1776 || (i
.types
[j
].bitfield
.qword
1777 && !t
->operand_types
[j
].bitfield
.qword
));
1780 /* Return 1 if there is no conflict in any size on operand J for
1781 instruction template T. */
1784 match_mem_size (const insn_template
*t
, unsigned int j
)
1786 return (match_reg_size (t
, j
)
1787 && !((i
.types
[j
].bitfield
.unspecified
1788 && !t
->operand_types
[j
].bitfield
.unspecified
)
1789 || (i
.types
[j
].bitfield
.fword
1790 && !t
->operand_types
[j
].bitfield
.fword
)
1791 || (i
.types
[j
].bitfield
.tbyte
1792 && !t
->operand_types
[j
].bitfield
.tbyte
)
1793 || (i
.types
[j
].bitfield
.xmmword
1794 && !t
->operand_types
[j
].bitfield
.xmmword
)
1795 || (i
.types
[j
].bitfield
.ymmword
1796 && !t
->operand_types
[j
].bitfield
.ymmword
)
1797 || (i
.types
[j
].bitfield
.zmmword
1798 && !t
->operand_types
[j
].bitfield
.zmmword
)));
1801 /* Return 1 if there is no size conflict on any operands for
1802 instruction template T. */
1805 operand_size_match (const insn_template
*t
)
1810 /* Don't check jump instructions. */
1811 if (t
->opcode_modifier
.jump
1812 || t
->opcode_modifier
.jumpbyte
1813 || t
->opcode_modifier
.jumpdword
1814 || t
->opcode_modifier
.jumpintersegment
)
1817 /* Check memory and accumulator operand size. */
1818 for (j
= 0; j
< i
.operands
; j
++)
1820 if (t
->operand_types
[j
].bitfield
.anysize
)
1823 if (t
->operand_types
[j
].bitfield
.acc
&& !match_reg_size (t
, j
))
1829 if (i
.types
[j
].bitfield
.mem
&& !match_mem_size (t
, j
))
1838 else if (!t
->opcode_modifier
.d
&& !t
->opcode_modifier
.floatd
)
1841 i
.error
= operand_size_mismatch
;
1845 /* Check reverse. */
1846 gas_assert (i
.operands
== 2);
1849 for (j
= 0; j
< 2; j
++)
1851 if (t
->operand_types
[j
].bitfield
.acc
1852 && !match_reg_size (t
, j
? 0 : 1))
1855 if (i
.types
[j
].bitfield
.mem
1856 && !match_mem_size (t
, j
? 0 : 1))
1864 operand_type_match (i386_operand_type overlap
,
1865 i386_operand_type given
)
1867 i386_operand_type temp
= overlap
;
1869 temp
.bitfield
.jumpabsolute
= 0;
1870 temp
.bitfield
.unspecified
= 0;
1871 temp
.bitfield
.byte
= 0;
1872 temp
.bitfield
.word
= 0;
1873 temp
.bitfield
.dword
= 0;
1874 temp
.bitfield
.fword
= 0;
1875 temp
.bitfield
.qword
= 0;
1876 temp
.bitfield
.tbyte
= 0;
1877 temp
.bitfield
.xmmword
= 0;
1878 temp
.bitfield
.ymmword
= 0;
1879 temp
.bitfield
.zmmword
= 0;
1880 if (operand_type_all_zero (&temp
))
1883 if (given
.bitfield
.baseindex
== overlap
.bitfield
.baseindex
1884 && given
.bitfield
.jumpabsolute
== overlap
.bitfield
.jumpabsolute
)
1888 i
.error
= operand_type_mismatch
;
1892 /* If given types g0 and g1 are registers they must be of the same type
1893 unless the expected operand type register overlap is null.
1894 Note that Acc in a template matches every size of reg. */
1897 operand_type_register_match (i386_operand_type m0
,
1898 i386_operand_type g0
,
1899 i386_operand_type t0
,
1900 i386_operand_type m1
,
1901 i386_operand_type g1
,
1902 i386_operand_type t1
)
1904 if (!operand_type_check (g0
, reg
))
1907 if (!operand_type_check (g1
, reg
))
1910 if (g0
.bitfield
.reg8
== g1
.bitfield
.reg8
1911 && g0
.bitfield
.reg16
== g1
.bitfield
.reg16
1912 && g0
.bitfield
.reg32
== g1
.bitfield
.reg32
1913 && g0
.bitfield
.reg64
== g1
.bitfield
.reg64
)
1916 if (m0
.bitfield
.acc
)
1918 t0
.bitfield
.reg8
= 1;
1919 t0
.bitfield
.reg16
= 1;
1920 t0
.bitfield
.reg32
= 1;
1921 t0
.bitfield
.reg64
= 1;
1924 if (m1
.bitfield
.acc
)
1926 t1
.bitfield
.reg8
= 1;
1927 t1
.bitfield
.reg16
= 1;
1928 t1
.bitfield
.reg32
= 1;
1929 t1
.bitfield
.reg64
= 1;
1932 if (!(t0
.bitfield
.reg8
& t1
.bitfield
.reg8
)
1933 && !(t0
.bitfield
.reg16
& t1
.bitfield
.reg16
)
1934 && !(t0
.bitfield
.reg32
& t1
.bitfield
.reg32
)
1935 && !(t0
.bitfield
.reg64
& t1
.bitfield
.reg64
))
1938 i
.error
= register_type_mismatch
;
1943 static INLINE
unsigned int
1944 register_number (const reg_entry
*r
)
1946 unsigned int nr
= r
->reg_num
;
1948 if (r
->reg_flags
& RegRex
)
1954 static INLINE
unsigned int
1955 mode_from_disp_size (i386_operand_type t
)
1957 if (t
.bitfield
.disp8
|| t
.bitfield
.vec_disp8
)
1959 else if (t
.bitfield
.disp16
1960 || t
.bitfield
.disp32
1961 || t
.bitfield
.disp32s
)
1968 fits_in_signed_byte (addressT num
)
1970 return num
+ 0x80 <= 0xff;
1974 fits_in_unsigned_byte (addressT num
)
1980 fits_in_unsigned_word (addressT num
)
1982 return num
<= 0xffff;
1986 fits_in_signed_word (addressT num
)
1988 return num
+ 0x8000 <= 0xffff;
1992 fits_in_signed_long (addressT num ATTRIBUTE_UNUSED
)
1997 return num
+ 0x80000000 <= 0xffffffff;
1999 } /* fits_in_signed_long() */
2002 fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED
)
2007 return num
<= 0xffffffff;
2009 } /* fits_in_unsigned_long() */
2012 fits_in_vec_disp8 (offsetT num
)
2014 int shift
= i
.memshift
;
2020 mask
= (1 << shift
) - 1;
2022 /* Return 0 if NUM isn't properly aligned. */
2026 /* Check if NUM will fit in 8bit after shift. */
2027 return fits_in_signed_byte (num
>> shift
);
2031 fits_in_imm4 (offsetT num
)
2033 return (num
& 0xf) == num
;
2036 static i386_operand_type
2037 smallest_imm_type (offsetT num
)
2039 i386_operand_type t
;
2041 operand_type_set (&t
, 0);
2042 t
.bitfield
.imm64
= 1;
2044 if (cpu_arch_tune
!= PROCESSOR_I486
&& num
== 1)
2046 /* This code is disabled on the 486 because all the Imm1 forms
2047 in the opcode table are slower on the i486. They're the
2048 versions with the implicitly specified single-position
2049 displacement, which has another syntax if you really want to
2051 t
.bitfield
.imm1
= 1;
2052 t
.bitfield
.imm8
= 1;
2053 t
.bitfield
.imm8s
= 1;
2054 t
.bitfield
.imm16
= 1;
2055 t
.bitfield
.imm32
= 1;
2056 t
.bitfield
.imm32s
= 1;
2058 else if (fits_in_signed_byte (num
))
2060 t
.bitfield
.imm8
= 1;
2061 t
.bitfield
.imm8s
= 1;
2062 t
.bitfield
.imm16
= 1;
2063 t
.bitfield
.imm32
= 1;
2064 t
.bitfield
.imm32s
= 1;
2066 else if (fits_in_unsigned_byte (num
))
2068 t
.bitfield
.imm8
= 1;
2069 t
.bitfield
.imm16
= 1;
2070 t
.bitfield
.imm32
= 1;
2071 t
.bitfield
.imm32s
= 1;
2073 else if (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
2075 t
.bitfield
.imm16
= 1;
2076 t
.bitfield
.imm32
= 1;
2077 t
.bitfield
.imm32s
= 1;
2079 else if (fits_in_signed_long (num
))
2081 t
.bitfield
.imm32
= 1;
2082 t
.bitfield
.imm32s
= 1;
2084 else if (fits_in_unsigned_long (num
))
2085 t
.bitfield
.imm32
= 1;
2091 offset_in_range (offsetT val
, int size
)
2097 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
2098 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
2099 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
2101 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
2107 /* If BFD64, sign extend val for 32bit address mode. */
2108 if (flag_code
!= CODE_64BIT
2109 || i
.prefix
[ADDR_PREFIX
])
2110 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
2111 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
2114 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
2116 char buf1
[40], buf2
[40];
2118 sprint_value (buf1
, val
);
2119 sprint_value (buf2
, val
& mask
);
2120 as_warn (_("%s shortened to %s"), buf1
, buf2
);
2134 a. PREFIX_EXIST if attempting to add a prefix where one from the
2135 same class already exists.
2136 b. PREFIX_LOCK if lock prefix is added.
2137 c. PREFIX_REP if rep/repne prefix is added.
2138 d. PREFIX_OTHER if other prefix is added.
2141 static enum PREFIX_GROUP
2142 add_prefix (unsigned int prefix
)
2144 enum PREFIX_GROUP ret
= PREFIX_OTHER
;
2147 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
2148 && flag_code
== CODE_64BIT
)
2150 if ((i
.prefix
[REX_PREFIX
] & prefix
& REX_W
)
2151 || ((i
.prefix
[REX_PREFIX
] & (REX_R
| REX_X
| REX_B
))
2152 && (prefix
& (REX_R
| REX_X
| REX_B
))))
2163 case CS_PREFIX_OPCODE
:
2164 case DS_PREFIX_OPCODE
:
2165 case ES_PREFIX_OPCODE
:
2166 case FS_PREFIX_OPCODE
:
2167 case GS_PREFIX_OPCODE
:
2168 case SS_PREFIX_OPCODE
:
2172 case REPNE_PREFIX_OPCODE
:
2173 case REPE_PREFIX_OPCODE
:
2178 case LOCK_PREFIX_OPCODE
:
2187 case ADDR_PREFIX_OPCODE
:
2191 case DATA_PREFIX_OPCODE
:
2195 if (i
.prefix
[q
] != 0)
2203 i
.prefix
[q
] |= prefix
;
2206 as_bad (_("same type of prefix used twice"));
2212 update_code_flag (int value
, int check
)
2214 PRINTF_LIKE ((*as_error
));
2216 flag_code
= (enum flag_code
) value
;
2217 if (flag_code
== CODE_64BIT
)
2219 cpu_arch_flags
.bitfield
.cpu64
= 1;
2220 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2224 cpu_arch_flags
.bitfield
.cpu64
= 0;
2225 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2227 if (value
== CODE_64BIT
&& !cpu_arch_flags
.bitfield
.cpulm
)
2230 as_error
= as_fatal
;
2233 (*as_error
) (_("64bit mode not supported on `%s'."),
2234 cpu_arch_name
? cpu_arch_name
: default_arch
);
2236 if (value
== CODE_32BIT
&& !cpu_arch_flags
.bitfield
.cpui386
)
2239 as_error
= as_fatal
;
2242 (*as_error
) (_("32bit mode not supported on `%s'."),
2243 cpu_arch_name
? cpu_arch_name
: default_arch
);
2245 stackop_size
= '\0';
2249 set_code_flag (int value
)
2251 update_code_flag (value
, 0);
2255 set_16bit_gcc_code_flag (int new_code_flag
)
2257 flag_code
= (enum flag_code
) new_code_flag
;
2258 if (flag_code
!= CODE_16BIT
)
2260 cpu_arch_flags
.bitfield
.cpu64
= 0;
2261 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2262 stackop_size
= LONG_MNEM_SUFFIX
;
2266 set_intel_syntax (int syntax_flag
)
2268 /* Find out if register prefixing is specified. */
2269 int ask_naked_reg
= 0;
2272 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2274 char *string
= input_line_pointer
;
2275 int e
= get_symbol_end ();
2277 if (strcmp (string
, "prefix") == 0)
2279 else if (strcmp (string
, "noprefix") == 0)
2282 as_bad (_("bad argument to syntax directive."));
2283 *input_line_pointer
= e
;
2285 demand_empty_rest_of_line ();
2287 intel_syntax
= syntax_flag
;
2289 if (ask_naked_reg
== 0)
2290 allow_naked_reg
= (intel_syntax
2291 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
2293 allow_naked_reg
= (ask_naked_reg
< 0);
2295 expr_set_rank (O_full_ptr
, syntax_flag
? 10 : 0);
2297 identifier_chars
['%'] = intel_syntax
&& allow_naked_reg
? '%' : 0;
2298 identifier_chars
['$'] = intel_syntax
? '$' : 0;
2299 register_prefix
= allow_naked_reg
? "" : "%";
2303 set_intel_mnemonic (int mnemonic_flag
)
2305 intel_mnemonic
= mnemonic_flag
;
2309 set_allow_index_reg (int flag
)
2311 allow_index_reg
= flag
;
2315 set_check (int what
)
2317 enum check_kind
*kind
;
2322 kind
= &operand_check
;
2333 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2335 char *string
= input_line_pointer
;
2336 int e
= get_symbol_end ();
2338 if (strcmp (string
, "none") == 0)
2340 else if (strcmp (string
, "warning") == 0)
2341 *kind
= check_warning
;
2342 else if (strcmp (string
, "error") == 0)
2343 *kind
= check_error
;
2345 as_bad (_("bad argument to %s_check directive."), str
);
2346 *input_line_pointer
= e
;
2349 as_bad (_("missing argument for %s_check directive"), str
);
2351 demand_empty_rest_of_line ();
2355 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED
,
2356 i386_cpu_flags new_flag ATTRIBUTE_UNUSED
)
2358 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2359 static const char *arch
;
2361 /* Intel LIOM is only supported on ELF. */
2367 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2368 use default_arch. */
2369 arch
= cpu_arch_name
;
2371 arch
= default_arch
;
2374 /* If we are targeting Intel L1OM, we must enable it. */
2375 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_L1OM
2376 || new_flag
.bitfield
.cpul1om
)
2379 /* If we are targeting Intel K1OM, we must enable it. */
2380 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_K1OM
2381 || new_flag
.bitfield
.cpuk1om
)
2384 as_bad (_("`%s' is not supported on `%s'"), name
, arch
);
2389 set_cpu_arch (int dummy ATTRIBUTE_UNUSED
)
2393 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2395 char *string
= input_line_pointer
;
2396 int e
= get_symbol_end ();
2398 i386_cpu_flags flags
;
2400 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
2402 if (strcmp (string
, cpu_arch
[j
].name
) == 0)
2404 check_cpu_arch_compatible (string
, cpu_arch
[j
].flags
);
2408 cpu_arch_name
= cpu_arch
[j
].name
;
2409 cpu_sub_arch_name
= NULL
;
2410 cpu_arch_flags
= cpu_arch
[j
].flags
;
2411 if (flag_code
== CODE_64BIT
)
2413 cpu_arch_flags
.bitfield
.cpu64
= 1;
2414 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2418 cpu_arch_flags
.bitfield
.cpu64
= 0;
2419 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2421 cpu_arch_isa
= cpu_arch
[j
].type
;
2422 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
2423 if (!cpu_arch_tune_set
)
2425 cpu_arch_tune
= cpu_arch_isa
;
2426 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
2431 if (!cpu_arch
[j
].negated
)
2432 flags
= cpu_flags_or (cpu_arch_flags
,
2435 flags
= cpu_flags_and_not (cpu_arch_flags
,
2437 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2439 if (cpu_sub_arch_name
)
2441 char *name
= cpu_sub_arch_name
;
2442 cpu_sub_arch_name
= concat (name
,
2444 (const char *) NULL
);
2448 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
2449 cpu_arch_flags
= flags
;
2450 cpu_arch_isa_flags
= flags
;
2452 *input_line_pointer
= e
;
2453 demand_empty_rest_of_line ();
2457 if (j
>= ARRAY_SIZE (cpu_arch
))
2458 as_bad (_("no such architecture: `%s'"), string
);
2460 *input_line_pointer
= e
;
2463 as_bad (_("missing cpu architecture"));
2465 no_cond_jump_promotion
= 0;
2466 if (*input_line_pointer
== ','
2467 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
2469 char *string
= ++input_line_pointer
;
2470 int e
= get_symbol_end ();
2472 if (strcmp (string
, "nojumps") == 0)
2473 no_cond_jump_promotion
= 1;
2474 else if (strcmp (string
, "jumps") == 0)
2477 as_bad (_("no such architecture modifier: `%s'"), string
);
2479 *input_line_pointer
= e
;
2482 demand_empty_rest_of_line ();
2485 enum bfd_architecture
2488 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2490 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2491 || flag_code
!= CODE_64BIT
)
2492 as_fatal (_("Intel L1OM is 64bit ELF only"));
2493 return bfd_arch_l1om
;
2495 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2497 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2498 || flag_code
!= CODE_64BIT
)
2499 as_fatal (_("Intel K1OM is 64bit ELF only"));
2500 return bfd_arch_k1om
;
2503 return bfd_arch_i386
;
2509 if (!strncmp (default_arch
, "x86_64", 6))
2511 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2513 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2514 || default_arch
[6] != '\0')
2515 as_fatal (_("Intel L1OM is 64bit ELF only"));
2516 return bfd_mach_l1om
;
2518 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2520 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2521 || default_arch
[6] != '\0')
2522 as_fatal (_("Intel K1OM is 64bit ELF only"));
2523 return bfd_mach_k1om
;
2525 else if (default_arch
[6] == '\0')
2526 return bfd_mach_x86_64
;
2528 return bfd_mach_x64_32
;
2530 else if (!strcmp (default_arch
, "i386"))
2531 return bfd_mach_i386_i386
;
2533 as_fatal (_("unknown architecture"));
2539 const char *hash_err
;
2541 /* Initialize op_hash hash table. */
2542 op_hash
= hash_new ();
2545 const insn_template
*optab
;
2546 templates
*core_optab
;
2548 /* Setup for loop. */
2550 core_optab
= (templates
*) xmalloc (sizeof (templates
));
2551 core_optab
->start
= optab
;
2556 if (optab
->name
== NULL
2557 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
2559 /* different name --> ship out current template list;
2560 add to hash table; & begin anew. */
2561 core_optab
->end
= optab
;
2562 hash_err
= hash_insert (op_hash
,
2564 (void *) core_optab
);
2567 as_fatal (_("can't hash %s: %s"),
2571 if (optab
->name
== NULL
)
2573 core_optab
= (templates
*) xmalloc (sizeof (templates
));
2574 core_optab
->start
= optab
;
2579 /* Initialize reg_hash hash table. */
2580 reg_hash
= hash_new ();
2582 const reg_entry
*regtab
;
2583 unsigned int regtab_size
= i386_regtab_size
;
2585 for (regtab
= i386_regtab
; regtab_size
--; regtab
++)
2587 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (void *) regtab
);
2589 as_fatal (_("can't hash %s: %s"),
2595 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
2600 for (c
= 0; c
< 256; c
++)
2605 mnemonic_chars
[c
] = c
;
2606 register_chars
[c
] = c
;
2607 operand_chars
[c
] = c
;
2609 else if (ISLOWER (c
))
2611 mnemonic_chars
[c
] = c
;
2612 register_chars
[c
] = c
;
2613 operand_chars
[c
] = c
;
2615 else if (ISUPPER (c
))
2617 mnemonic_chars
[c
] = TOLOWER (c
);
2618 register_chars
[c
] = mnemonic_chars
[c
];
2619 operand_chars
[c
] = c
;
2621 else if (c
== '{' || c
== '}')
2622 operand_chars
[c
] = c
;
2624 if (ISALPHA (c
) || ISDIGIT (c
))
2625 identifier_chars
[c
] = c
;
2628 identifier_chars
[c
] = c
;
2629 operand_chars
[c
] = c
;
2634 identifier_chars
['@'] = '@';
2637 identifier_chars
['?'] = '?';
2638 operand_chars
['?'] = '?';
2640 digit_chars
['-'] = '-';
2641 mnemonic_chars
['_'] = '_';
2642 mnemonic_chars
['-'] = '-';
2643 mnemonic_chars
['.'] = '.';
2644 identifier_chars
['_'] = '_';
2645 identifier_chars
['.'] = '.';
2647 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
2648 operand_chars
[(unsigned char) *p
] = *p
;
2651 if (flag_code
== CODE_64BIT
)
2653 #if defined (OBJ_COFF) && defined (TE_PE)
2654 x86_dwarf2_return_column
= (OUTPUT_FLAVOR
== bfd_target_coff_flavour
2657 x86_dwarf2_return_column
= 16;
2659 x86_cie_data_alignment
= -8;
2663 x86_dwarf2_return_column
= 8;
2664 x86_cie_data_alignment
= -4;
2669 i386_print_statistics (FILE *file
)
2671 hash_print_statistics (file
, "i386 opcode", op_hash
);
2672 hash_print_statistics (file
, "i386 register", reg_hash
);
2677 /* Debugging routines for md_assemble. */
2678 static void pte (insn_template
*);
2679 static void pt (i386_operand_type
);
2680 static void pe (expressionS
*);
2681 static void ps (symbolS
*);
2684 pi (char *line
, i386_insn
*x
)
2688 fprintf (stdout
, "%s: template ", line
);
2690 fprintf (stdout
, " address: base %s index %s scale %x\n",
2691 x
->base_reg
? x
->base_reg
->reg_name
: "none",
2692 x
->index_reg
? x
->index_reg
->reg_name
: "none",
2693 x
->log2_scale_factor
);
2694 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
2695 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
2696 fprintf (stdout
, " sib: base %x index %x scale %x\n",
2697 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
2698 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
2699 (x
->rex
& REX_W
) != 0,
2700 (x
->rex
& REX_R
) != 0,
2701 (x
->rex
& REX_X
) != 0,
2702 (x
->rex
& REX_B
) != 0);
2703 for (j
= 0; j
< x
->operands
; j
++)
2705 fprintf (stdout
, " #%d: ", j
+ 1);
2707 fprintf (stdout
, "\n");
2708 if (x
->types
[j
].bitfield
.reg8
2709 || x
->types
[j
].bitfield
.reg16
2710 || x
->types
[j
].bitfield
.reg32
2711 || x
->types
[j
].bitfield
.reg64
2712 || x
->types
[j
].bitfield
.regmmx
2713 || x
->types
[j
].bitfield
.regxmm
2714 || x
->types
[j
].bitfield
.regymm
2715 || x
->types
[j
].bitfield
.regzmm
2716 || x
->types
[j
].bitfield
.sreg2
2717 || x
->types
[j
].bitfield
.sreg3
2718 || x
->types
[j
].bitfield
.control
2719 || x
->types
[j
].bitfield
.debug
2720 || x
->types
[j
].bitfield
.test
)
2721 fprintf (stdout
, "%s\n", x
->op
[j
].regs
->reg_name
);
2722 if (operand_type_check (x
->types
[j
], imm
))
2724 if (operand_type_check (x
->types
[j
], disp
))
2725 pe (x
->op
[j
].disps
);
2730 pte (insn_template
*t
)
2733 fprintf (stdout
, " %d operands ", t
->operands
);
2734 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
2735 if (t
->extension_opcode
!= None
)
2736 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
2737 if (t
->opcode_modifier
.d
)
2738 fprintf (stdout
, "D");
2739 if (t
->opcode_modifier
.w
)
2740 fprintf (stdout
, "W");
2741 fprintf (stdout
, "\n");
2742 for (j
= 0; j
< t
->operands
; j
++)
2744 fprintf (stdout
, " #%d type ", j
+ 1);
2745 pt (t
->operand_types
[j
]);
2746 fprintf (stdout
, "\n");
2753 fprintf (stdout
, " operation %d\n", e
->X_op
);
2754 fprintf (stdout
, " add_number %ld (%lx)\n",
2755 (long) e
->X_add_number
, (long) e
->X_add_number
);
2756 if (e
->X_add_symbol
)
2758 fprintf (stdout
, " add_symbol ");
2759 ps (e
->X_add_symbol
);
2760 fprintf (stdout
, "\n");
2764 fprintf (stdout
, " op_symbol ");
2765 ps (e
->X_op_symbol
);
2766 fprintf (stdout
, "\n");
2773 fprintf (stdout
, "%s type %s%s",
2775 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
2776 segment_name (S_GET_SEGMENT (s
)));
2779 static struct type_name
2781 i386_operand_type mask
;
2784 const type_names
[] =
2786 { OPERAND_TYPE_REG8
, "r8" },
2787 { OPERAND_TYPE_REG16
, "r16" },
2788 { OPERAND_TYPE_REG32
, "r32" },
2789 { OPERAND_TYPE_REG64
, "r64" },
2790 { OPERAND_TYPE_IMM8
, "i8" },
2791 { OPERAND_TYPE_IMM8
, "i8s" },
2792 { OPERAND_TYPE_IMM16
, "i16" },
2793 { OPERAND_TYPE_IMM32
, "i32" },
2794 { OPERAND_TYPE_IMM32S
, "i32s" },
2795 { OPERAND_TYPE_IMM64
, "i64" },
2796 { OPERAND_TYPE_IMM1
, "i1" },
2797 { OPERAND_TYPE_BASEINDEX
, "BaseIndex" },
2798 { OPERAND_TYPE_DISP8
, "d8" },
2799 { OPERAND_TYPE_DISP16
, "d16" },
2800 { OPERAND_TYPE_DISP32
, "d32" },
2801 { OPERAND_TYPE_DISP32S
, "d32s" },
2802 { OPERAND_TYPE_DISP64
, "d64" },
2803 { OPERAND_TYPE_VEC_DISP8
, "Vector d8" },
2804 { OPERAND_TYPE_INOUTPORTREG
, "InOutPortReg" },
2805 { OPERAND_TYPE_SHIFTCOUNT
, "ShiftCount" },
2806 { OPERAND_TYPE_CONTROL
, "control reg" },
2807 { OPERAND_TYPE_TEST
, "test reg" },
2808 { OPERAND_TYPE_DEBUG
, "debug reg" },
2809 { OPERAND_TYPE_FLOATREG
, "FReg" },
2810 { OPERAND_TYPE_FLOATACC
, "FAcc" },
2811 { OPERAND_TYPE_SREG2
, "SReg2" },
2812 { OPERAND_TYPE_SREG3
, "SReg3" },
2813 { OPERAND_TYPE_ACC
, "Acc" },
2814 { OPERAND_TYPE_JUMPABSOLUTE
, "Jump Absolute" },
2815 { OPERAND_TYPE_REGMMX
, "rMMX" },
2816 { OPERAND_TYPE_REGXMM
, "rXMM" },
2817 { OPERAND_TYPE_REGYMM
, "rYMM" },
2818 { OPERAND_TYPE_REGZMM
, "rZMM" },
2819 { OPERAND_TYPE_REGMASK
, "Mask reg" },
2820 { OPERAND_TYPE_ESSEG
, "es" },
2824 pt (i386_operand_type t
)
2827 i386_operand_type a
;
2829 for (j
= 0; j
< ARRAY_SIZE (type_names
); j
++)
2831 a
= operand_type_and (t
, type_names
[j
].mask
);
2832 if (!operand_type_all_zero (&a
))
2833 fprintf (stdout
, "%s, ", type_names
[j
].name
);
2838 #endif /* DEBUG386 */
2840 static bfd_reloc_code_real_type
2841 reloc (unsigned int size
,
2844 bfd_reloc_code_real_type other
)
2846 if (other
!= NO_RELOC
)
2848 reloc_howto_type
*rel
;
2853 case BFD_RELOC_X86_64_GOT32
:
2854 return BFD_RELOC_X86_64_GOT64
;
2856 case BFD_RELOC_X86_64_GOTPLT64
:
2857 return BFD_RELOC_X86_64_GOTPLT64
;
2859 case BFD_RELOC_X86_64_PLTOFF64
:
2860 return BFD_RELOC_X86_64_PLTOFF64
;
2862 case BFD_RELOC_X86_64_GOTPC32
:
2863 other
= BFD_RELOC_X86_64_GOTPC64
;
2865 case BFD_RELOC_X86_64_GOTPCREL
:
2866 other
= BFD_RELOC_X86_64_GOTPCREL64
;
2868 case BFD_RELOC_X86_64_TPOFF32
:
2869 other
= BFD_RELOC_X86_64_TPOFF64
;
2871 case BFD_RELOC_X86_64_DTPOFF32
:
2872 other
= BFD_RELOC_X86_64_DTPOFF64
;
2878 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2879 if (other
== BFD_RELOC_SIZE32
)
2882 other
= BFD_RELOC_SIZE64
;
2885 as_bad (_("there are no pc-relative size relocations"));
2891 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
2892 if (size
== 4 && (flag_code
!= CODE_64BIT
|| disallow_64bit_reloc
))
2895 rel
= bfd_reloc_type_lookup (stdoutput
, other
);
2897 as_bad (_("unknown relocation (%u)"), other
);
2898 else if (size
!= bfd_get_reloc_size (rel
))
2899 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
2900 bfd_get_reloc_size (rel
),
2902 else if (pcrel
&& !rel
->pc_relative
)
2903 as_bad (_("non-pc-relative relocation for pc-relative field"));
2904 else if ((rel
->complain_on_overflow
== complain_overflow_signed
2906 || (rel
->complain_on_overflow
== complain_overflow_unsigned
2908 as_bad (_("relocated field and relocation type differ in signedness"));
2917 as_bad (_("there are no unsigned pc-relative relocations"));
2920 case 1: return BFD_RELOC_8_PCREL
;
2921 case 2: return BFD_RELOC_16_PCREL
;
2922 case 4: return BFD_RELOC_32_PCREL
;
2923 case 8: return BFD_RELOC_64_PCREL
;
2925 as_bad (_("cannot do %u byte pc-relative relocation"), size
);
2932 case 4: return BFD_RELOC_X86_64_32S
;
2937 case 1: return BFD_RELOC_8
;
2938 case 2: return BFD_RELOC_16
;
2939 case 4: return BFD_RELOC_32
;
2940 case 8: return BFD_RELOC_64
;
2942 as_bad (_("cannot do %s %u byte relocation"),
2943 sign
> 0 ? "signed" : "unsigned", size
);
2949 /* Here we decide which fixups can be adjusted to make them relative to
2950 the beginning of the section instead of the symbol. Basically we need
2951 to make sure that the dynamic relocations are done correctly, so in
2952 some cases we force the original symbol to be used. */
2955 tc_i386_fix_adjustable (fixS
*fixP ATTRIBUTE_UNUSED
)
2957 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2961 /* Don't adjust pc-relative references to merge sections in 64-bit
2963 if (use_rela_relocations
2964 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
2968 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
2969 and changed later by validate_fix. */
2970 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
2971 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
2974 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
2975 for size relocations. */
2976 if (fixP
->fx_r_type
== BFD_RELOC_SIZE32
2977 || fixP
->fx_r_type
== BFD_RELOC_SIZE64
2978 || fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
2979 || fixP
->fx_r_type
== BFD_RELOC_386_PLT32
2980 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
2981 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
2982 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
2983 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
2984 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
2985 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
2986 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
2987 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
2988 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
2989 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTDESC
2990 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_DESC_CALL
2991 || fixP
->fx_r_type
== BFD_RELOC_X86_64_PLT32
2992 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
2993 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
2994 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
2995 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
2996 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
2997 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
2998 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
2999 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
3000 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
3001 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
3002 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPC32_TLSDESC
3003 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSDESC_CALL
3004 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
3005 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
3012 intel_float_operand (const char *mnemonic
)
3014 /* Note that the value returned is meaningful only for opcodes with (memory)
3015 operands, hence the code here is free to improperly handle opcodes that
3016 have no operands (for better performance and smaller code). */
3018 if (mnemonic
[0] != 'f')
3019 return 0; /* non-math */
3021 switch (mnemonic
[1])
3023 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
3024 the fs segment override prefix not currently handled because no
3025 call path can make opcodes without operands get here */
3027 return 2 /* integer op */;
3029 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
3030 return 3; /* fldcw/fldenv */
3033 if (mnemonic
[2] != 'o' /* fnop */)
3034 return 3; /* non-waiting control op */
3037 if (mnemonic
[2] == 's')
3038 return 3; /* frstor/frstpm */
3041 if (mnemonic
[2] == 'a')
3042 return 3; /* fsave */
3043 if (mnemonic
[2] == 't')
3045 switch (mnemonic
[3])
3047 case 'c': /* fstcw */
3048 case 'd': /* fstdw */
3049 case 'e': /* fstenv */
3050 case 's': /* fsts[gw] */
3056 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
3057 return 0; /* fxsave/fxrstor are not really math ops */
3064 /* Build the VEX prefix. */
3067 build_vex_prefix (const insn_template
*t
)
3069 unsigned int register_specifier
;
3070 unsigned int implied_prefix
;
3071 unsigned int vector_length
;
3073 /* Check register specifier. */
3074 if (i
.vex
.register_specifier
)
3076 register_specifier
=
3077 ~register_number (i
.vex
.register_specifier
) & 0xf;
3078 gas_assert ((i
.vex
.register_specifier
->reg_flags
& RegVRex
) == 0);
3081 register_specifier
= 0xf;
3083 /* Use 2-byte VEX prefix by swappping destination and source
3086 && i
.operands
== i
.reg_operands
3087 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3088 && i
.tm
.opcode_modifier
.s
3091 unsigned int xchg
= i
.operands
- 1;
3092 union i386_op temp_op
;
3093 i386_operand_type temp_type
;
3095 temp_type
= i
.types
[xchg
];
3096 i
.types
[xchg
] = i
.types
[0];
3097 i
.types
[0] = temp_type
;
3098 temp_op
= i
.op
[xchg
];
3099 i
.op
[xchg
] = i
.op
[0];
3102 gas_assert (i
.rm
.mode
== 3);
3106 i
.rm
.regmem
= i
.rm
.reg
;
3109 /* Use the next insn. */
3113 if (i
.tm
.opcode_modifier
.vex
== VEXScalar
)
3114 vector_length
= avxscalar
;
3116 vector_length
= i
.tm
.opcode_modifier
.vex
== VEX256
? 1 : 0;
3118 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3123 case DATA_PREFIX_OPCODE
:
3126 case REPE_PREFIX_OPCODE
:
3129 case REPNE_PREFIX_OPCODE
:
3136 /* Use 2-byte VEX prefix if possible. */
3137 if (i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3138 && i
.tm
.opcode_modifier
.vexw
!= VEXW1
3139 && (i
.rex
& (REX_W
| REX_X
| REX_B
)) == 0)
3141 /* 2-byte VEX prefix. */
3145 i
.vex
.bytes
[0] = 0xc5;
3147 /* Check the REX.R bit. */
3148 r
= (i
.rex
& REX_R
) ? 0 : 1;
3149 i
.vex
.bytes
[1] = (r
<< 7
3150 | register_specifier
<< 3
3151 | vector_length
<< 2
3156 /* 3-byte VEX prefix. */
3161 switch (i
.tm
.opcode_modifier
.vexopcode
)
3165 i
.vex
.bytes
[0] = 0xc4;
3169 i
.vex
.bytes
[0] = 0xc4;
3173 i
.vex
.bytes
[0] = 0xc4;
3177 i
.vex
.bytes
[0] = 0x8f;
3181 i
.vex
.bytes
[0] = 0x8f;
3185 i
.vex
.bytes
[0] = 0x8f;
3191 /* The high 3 bits of the second VEX byte are 1's compliment
3192 of RXB bits from REX. */
3193 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3195 /* Check the REX.W bit. */
3196 w
= (i
.rex
& REX_W
) ? 1 : 0;
3197 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
3200 i
.vex
.bytes
[2] = (w
<< 7
3201 | register_specifier
<< 3
3202 | vector_length
<< 2
3207 /* Build the EVEX prefix. */
3210 build_evex_prefix (void)
3212 unsigned int register_specifier
;
3213 unsigned int implied_prefix
;
3215 rex_byte vrex_used
= 0;
3217 /* Check register specifier. */
3218 if (i
.vex
.register_specifier
)
3220 gas_assert ((i
.vrex
& REX_X
) == 0);
3222 register_specifier
= i
.vex
.register_specifier
->reg_num
;
3223 if ((i
.vex
.register_specifier
->reg_flags
& RegRex
))
3224 register_specifier
+= 8;
3225 /* The upper 16 registers are encoded in the fourth byte of the
3227 if (!(i
.vex
.register_specifier
->reg_flags
& RegVRex
))
3228 i
.vex
.bytes
[3] = 0x8;
3229 register_specifier
= ~register_specifier
& 0xf;
3233 register_specifier
= 0xf;
3235 /* Encode upper 16 vector index register in the fourth byte of
3237 if (!(i
.vrex
& REX_X
))
3238 i
.vex
.bytes
[3] = 0x8;
3243 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3248 case DATA_PREFIX_OPCODE
:
3251 case REPE_PREFIX_OPCODE
:
3254 case REPNE_PREFIX_OPCODE
:
3261 /* 4 byte EVEX prefix. */
3263 i
.vex
.bytes
[0] = 0x62;
3266 switch (i
.tm
.opcode_modifier
.vexopcode
)
3282 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3284 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3286 /* The fifth bit of the second EVEX byte is 1's compliment of the
3287 REX_R bit in VREX. */
3288 if (!(i
.vrex
& REX_R
))
3289 i
.vex
.bytes
[1] |= 0x10;
3293 if ((i
.reg_operands
+ i
.imm_operands
) == i
.operands
)
3295 /* When all operands are registers, the REX_X bit in REX is not
3296 used. We reuse it to encode the upper 16 registers, which is
3297 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3298 as 1's compliment. */
3299 if ((i
.vrex
& REX_B
))
3302 i
.vex
.bytes
[1] &= ~0x40;
3306 /* EVEX instructions shouldn't need the REX prefix. */
3307 i
.vrex
&= ~vrex_used
;
3308 gas_assert (i
.vrex
== 0);
3310 /* Check the REX.W bit. */
3311 w
= (i
.rex
& REX_W
) ? 1 : 0;
3312 if (i
.tm
.opcode_modifier
.vexw
)
3314 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
3317 /* If w is not set it means we are dealing with WIG instruction. */
3320 if (evexwig
== evexw1
)
3324 /* Encode the U bit. */
3325 implied_prefix
|= 0x4;
3327 /* The third byte of the EVEX prefix. */
3328 i
.vex
.bytes
[2] = (w
<< 7 | register_specifier
<< 3 | implied_prefix
);
3330 /* The fourth byte of the EVEX prefix. */
3331 /* The zeroing-masking bit. */
3332 if (i
.mask
&& i
.mask
->zeroing
)
3333 i
.vex
.bytes
[3] |= 0x80;
3335 /* Don't always set the broadcast bit if there is no RC. */
3338 /* Encode the vector length. */
3339 unsigned int vec_length
;
3341 switch (i
.tm
.opcode_modifier
.evex
)
3343 case EVEXLIG
: /* LL' is ignored */
3344 vec_length
= evexlig
<< 5;
3347 vec_length
= 0 << 5;
3350 vec_length
= 1 << 5;
3353 vec_length
= 2 << 5;
3359 i
.vex
.bytes
[3] |= vec_length
;
3360 /* Encode the broadcast bit. */
3362 i
.vex
.bytes
[3] |= 0x10;
3366 if (i
.rounding
->type
!= saeonly
)
3367 i
.vex
.bytes
[3] |= 0x10 | (i
.rounding
->type
<< 5);
3369 i
.vex
.bytes
[3] |= 0x10 | (evexrcig
<< 5);
3372 if (i
.mask
&& i
.mask
->mask
)
3373 i
.vex
.bytes
[3] |= i
.mask
->mask
->reg_num
;
3377 process_immext (void)
3381 if ((i
.tm
.cpu_flags
.bitfield
.cpusse3
|| i
.tm
.cpu_flags
.bitfield
.cpusvme
)
3384 /* MONITOR/MWAIT as well as SVME instructions have fixed operands
3385 with an opcode suffix which is coded in the same place as an
3386 8-bit immediate field would be.
3387 Here we check those operands and remove them afterwards. */
3390 for (x
= 0; x
< i
.operands
; x
++)
3391 if (register_number (i
.op
[x
].regs
) != x
)
3392 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3393 register_prefix
, i
.op
[x
].regs
->reg_name
, x
+ 1,
3399 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
3400 which is coded in the same place as an 8-bit immediate field
3401 would be. Here we fake an 8-bit immediate operand from the
3402 opcode suffix stored in tm.extension_opcode.
3404 AVX instructions also use this encoding, for some of
3405 3 argument instructions. */
3407 gas_assert (i
.imm_operands
<= 1
3409 || ((i
.tm
.opcode_modifier
.vex
3410 || i
.tm
.opcode_modifier
.evex
)
3411 && i
.operands
<= 4)));
3413 exp
= &im_expressions
[i
.imm_operands
++];
3414 i
.op
[i
.operands
].imms
= exp
;
3415 i
.types
[i
.operands
] = imm8
;
3417 exp
->X_op
= O_constant
;
3418 exp
->X_add_number
= i
.tm
.extension_opcode
;
3419 i
.tm
.extension_opcode
= None
;
3426 switch (i
.tm
.opcode_modifier
.hleprefixok
)
3431 as_bad (_("invalid instruction `%s' after `%s'"),
3432 i
.tm
.name
, i
.hle_prefix
);
3435 if (i
.prefix
[LOCK_PREFIX
])
3437 as_bad (_("missing `lock' with `%s'"), i
.hle_prefix
);
3441 case HLEPrefixRelease
:
3442 if (i
.prefix
[HLE_PREFIX
] != XRELEASE_PREFIX_OPCODE
)
3444 as_bad (_("instruction `%s' after `xacquire' not allowed"),
3448 if (i
.mem_operands
== 0
3449 || !operand_type_check (i
.types
[i
.operands
- 1], anymem
))
3451 as_bad (_("memory destination needed for instruction `%s'"
3452 " after `xrelease'"), i
.tm
.name
);
3459 /* This is the guts of the machine-dependent assembler. LINE points to a
3460 machine dependent instruction. This function is supposed to emit
3461 the frags/bytes it assembles to. */
3464 md_assemble (char *line
)
3467 char mnemonic
[MAX_MNEM_SIZE
];
3468 const insn_template
*t
;
3470 /* Initialize globals. */
3471 memset (&i
, '\0', sizeof (i
));
3472 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3473 i
.reloc
[j
] = NO_RELOC
;
3474 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
3475 memset (im_expressions
, '\0', sizeof (im_expressions
));
3476 save_stack_p
= save_stack
;
3478 /* First parse an instruction mnemonic & call i386_operand for the operands.
3479 We assume that the scrubber has arranged it so that line[0] is the valid
3480 start of a (possibly prefixed) mnemonic. */
3482 line
= parse_insn (line
, mnemonic
);
3486 line
= parse_operands (line
, mnemonic
);
3491 /* Now we've parsed the mnemonic into a set of templates, and have the
3492 operands at hand. */
3494 /* All intel opcodes have reversed operands except for "bound" and
3495 "enter". We also don't reverse intersegment "jmp" and "call"
3496 instructions with 2 immediate operands so that the immediate segment
3497 precedes the offset, as it does when in AT&T mode. */
3500 && (strcmp (mnemonic
, "bound") != 0)
3501 && (strcmp (mnemonic
, "invlpga") != 0)
3502 && !(operand_type_check (i
.types
[0], imm
)
3503 && operand_type_check (i
.types
[1], imm
)))
3506 /* The order of the immediates should be reversed
3507 for 2 immediates extrq and insertq instructions */
3508 if (i
.imm_operands
== 2
3509 && (strcmp (mnemonic
, "extrq") == 0
3510 || strcmp (mnemonic
, "insertq") == 0))
3511 swap_2_operands (0, 1);
3516 /* Don't optimize displacement for movabs since it only takes 64bit
3519 && i
.disp_encoding
!= disp_encoding_32bit
3520 && (flag_code
!= CODE_64BIT
3521 || strcmp (mnemonic
, "movabs") != 0))
3524 /* Next, we find a template that matches the given insn,
3525 making sure the overlap of the given operands types is consistent
3526 with the template operand types. */
3528 if (!(t
= match_template ()))
3531 if (sse_check
!= check_none
3532 && !i
.tm
.opcode_modifier
.noavx
3533 && (i
.tm
.cpu_flags
.bitfield
.cpusse
3534 || i
.tm
.cpu_flags
.bitfield
.cpusse2
3535 || i
.tm
.cpu_flags
.bitfield
.cpusse3
3536 || i
.tm
.cpu_flags
.bitfield
.cpussse3
3537 || i
.tm
.cpu_flags
.bitfield
.cpusse4_1
3538 || i
.tm
.cpu_flags
.bitfield
.cpusse4_2
))
3540 (sse_check
== check_warning
3542 : as_bad
) (_("SSE instruction `%s' is used"), i
.tm
.name
);
3545 /* Zap movzx and movsx suffix. The suffix has been set from
3546 "word ptr" or "byte ptr" on the source operand in Intel syntax
3547 or extracted from mnemonic in AT&T syntax. But we'll use
3548 the destination register to choose the suffix for encoding. */
3549 if ((i
.tm
.base_opcode
& ~9) == 0x0fb6)
3551 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
3552 there is no suffix, the default will be byte extension. */
3553 if (i
.reg_operands
!= 2
3556 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
3561 if (i
.tm
.opcode_modifier
.fwait
)
3562 if (!add_prefix (FWAIT_OPCODE
))
3565 /* Check if REP prefix is OK. */
3566 if (i
.rep_prefix
&& !i
.tm
.opcode_modifier
.repprefixok
)
3568 as_bad (_("invalid instruction `%s' after `%s'"),
3569 i
.tm
.name
, i
.rep_prefix
);
3573 /* Check for lock without a lockable instruction. Destination operand
3574 must be memory unless it is xchg (0x86). */
3575 if (i
.prefix
[LOCK_PREFIX
]
3576 && (!i
.tm
.opcode_modifier
.islockable
3577 || i
.mem_operands
== 0
3578 || (i
.tm
.base_opcode
!= 0x86
3579 && !operand_type_check (i
.types
[i
.operands
- 1], anymem
))))
3581 as_bad (_("expecting lockable instruction after `lock'"));
3585 /* Check if HLE prefix is OK. */
3586 if (i
.hle_prefix
&& !check_hle ())
3589 /* Check BND prefix. */
3590 if (i
.bnd_prefix
&& !i
.tm
.opcode_modifier
.bndprefixok
)
3591 as_bad (_("expecting valid branch instruction after `bnd'"));
3593 if (i
.tm
.cpu_flags
.bitfield
.cpumpx
3594 && flag_code
== CODE_64BIT
3595 && i
.prefix
[ADDR_PREFIX
])
3596 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
3598 /* Insert BND prefix. */
3600 && i
.tm
.opcode_modifier
.bndprefixok
3601 && !i
.prefix
[BND_PREFIX
])
3602 add_prefix (BND_PREFIX_OPCODE
);
3604 /* Check string instruction segment overrides. */
3605 if (i
.tm
.opcode_modifier
.isstring
&& i
.mem_operands
!= 0)
3607 if (!check_string ())
3609 i
.disp_operands
= 0;
3612 if (!process_suffix ())
3615 /* Update operand types. */
3616 for (j
= 0; j
< i
.operands
; j
++)
3617 i
.types
[j
] = operand_type_and (i
.types
[j
], i
.tm
.operand_types
[j
]);
3619 /* Make still unresolved immediate matches conform to size of immediate
3620 given in i.suffix. */
3621 if (!finalize_imm ())
3624 if (i
.types
[0].bitfield
.imm1
)
3625 i
.imm_operands
= 0; /* kludge for shift insns. */
3627 /* We only need to check those implicit registers for instructions
3628 with 3 operands or less. */
3629 if (i
.operands
<= 3)
3630 for (j
= 0; j
< i
.operands
; j
++)
3631 if (i
.types
[j
].bitfield
.inoutportreg
3632 || i
.types
[j
].bitfield
.shiftcount
3633 || i
.types
[j
].bitfield
.acc
3634 || i
.types
[j
].bitfield
.floatacc
)
3637 /* ImmExt should be processed after SSE2AVX. */
3638 if (!i
.tm
.opcode_modifier
.sse2avx
3639 && i
.tm
.opcode_modifier
.immext
)
3642 /* For insns with operands there are more diddles to do to the opcode. */
3645 if (!process_operands ())
3648 else if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
3650 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
3651 as_warn (_("translating to `%sp'"), i
.tm
.name
);
3654 if (i
.tm
.opcode_modifier
.vex
|| i
.tm
.opcode_modifier
.evex
)
3656 if (flag_code
== CODE_16BIT
)
3658 as_bad (_("instruction `%s' isn't supported in 16-bit mode."),
3663 if (i
.tm
.opcode_modifier
.vex
)
3664 build_vex_prefix (t
);
3666 build_evex_prefix ();
3669 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
3670 instructions may define INT_OPCODE as well, so avoid this corner
3671 case for those instructions that use MODRM. */
3672 if (i
.tm
.base_opcode
== INT_OPCODE
3673 && !i
.tm
.opcode_modifier
.modrm
3674 && i
.op
[0].imms
->X_add_number
== 3)
3676 i
.tm
.base_opcode
= INT3_OPCODE
;
3680 if ((i
.tm
.opcode_modifier
.jump
3681 || i
.tm
.opcode_modifier
.jumpbyte
3682 || i
.tm
.opcode_modifier
.jumpdword
)
3683 && i
.op
[0].disps
->X_op
== O_constant
)
3685 /* Convert "jmp constant" (and "call constant") to a jump (call) to
3686 the absolute address given by the constant. Since ix86 jumps and
3687 calls are pc relative, we need to generate a reloc. */
3688 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
3689 i
.op
[0].disps
->X_op
= O_symbol
;
3692 if (i
.tm
.opcode_modifier
.rex64
)
3695 /* For 8 bit registers we need an empty rex prefix. Also if the
3696 instruction already has a prefix, we need to convert old
3697 registers to new ones. */
3699 if ((i
.types
[0].bitfield
.reg8
3700 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
3701 || (i
.types
[1].bitfield
.reg8
3702 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
3703 || ((i
.types
[0].bitfield
.reg8
3704 || i
.types
[1].bitfield
.reg8
)
3709 i
.rex
|= REX_OPCODE
;
3710 for (x
= 0; x
< 2; x
++)
3712 /* Look for 8 bit operand that uses old registers. */
3713 if (i
.types
[x
].bitfield
.reg8
3714 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
3716 /* In case it is "hi" register, give up. */
3717 if (i
.op
[x
].regs
->reg_num
> 3)
3718 as_bad (_("can't encode register '%s%s' in an "
3719 "instruction requiring REX prefix."),
3720 register_prefix
, i
.op
[x
].regs
->reg_name
);
3722 /* Otherwise it is equivalent to the extended register.
3723 Since the encoding doesn't change this is merely
3724 cosmetic cleanup for debug output. */
3726 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
3732 add_prefix (REX_OPCODE
| i
.rex
);
3734 /* We are ready to output the insn. */
3739 parse_insn (char *line
, char *mnemonic
)
3742 char *token_start
= l
;
3745 const insn_template
*t
;
3751 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
3756 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
3758 as_bad (_("no such instruction: `%s'"), token_start
);
3763 if (!is_space_char (*l
)
3764 && *l
!= END_OF_INSN
3766 || (*l
!= PREFIX_SEPARATOR
3769 as_bad (_("invalid character %s in mnemonic"),
3770 output_invalid (*l
));
3773 if (token_start
== l
)
3775 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
3776 as_bad (_("expecting prefix; got nothing"));
3778 as_bad (_("expecting mnemonic; got nothing"));
3782 /* Look up instruction (or prefix) via hash table. */
3783 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
3785 if (*l
!= END_OF_INSN
3786 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
3787 && current_templates
3788 && current_templates
->start
->opcode_modifier
.isprefix
)
3790 if (!cpu_flags_check_cpu64 (current_templates
->start
->cpu_flags
))
3792 as_bad ((flag_code
!= CODE_64BIT
3793 ? _("`%s' is only supported in 64-bit mode")
3794 : _("`%s' is not supported in 64-bit mode")),
3795 current_templates
->start
->name
);
3798 /* If we are in 16-bit mode, do not allow addr16 or data16.
3799 Similarly, in 32-bit mode, do not allow addr32 or data32. */
3800 if ((current_templates
->start
->opcode_modifier
.size16
3801 || current_templates
->start
->opcode_modifier
.size32
)
3802 && flag_code
!= CODE_64BIT
3803 && (current_templates
->start
->opcode_modifier
.size32
3804 ^ (flag_code
== CODE_16BIT
)))
3806 as_bad (_("redundant %s prefix"),
3807 current_templates
->start
->name
);
3810 /* Add prefix, checking for repeated prefixes. */
3811 switch (add_prefix (current_templates
->start
->base_opcode
))
3816 if (current_templates
->start
->cpu_flags
.bitfield
.cpuhle
)
3817 i
.hle_prefix
= current_templates
->start
->name
;
3818 else if (current_templates
->start
->cpu_flags
.bitfield
.cpumpx
)
3819 i
.bnd_prefix
= current_templates
->start
->name
;
3821 i
.rep_prefix
= current_templates
->start
->name
;
3826 /* Skip past PREFIX_SEPARATOR and reset token_start. */
3833 if (!current_templates
)
3835 /* Check if we should swap operand or force 32bit displacement in
3837 if (mnem_p
- 2 == dot_p
&& dot_p
[1] == 's')
3839 else if (mnem_p
- 3 == dot_p
3842 i
.disp_encoding
= disp_encoding_8bit
;
3843 else if (mnem_p
- 4 == dot_p
3847 i
.disp_encoding
= disp_encoding_32bit
;
3852 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
3855 if (!current_templates
)
3858 /* See if we can get a match by trimming off a suffix. */
3861 case WORD_MNEM_SUFFIX
:
3862 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
3863 i
.suffix
= SHORT_MNEM_SUFFIX
;
3865 case BYTE_MNEM_SUFFIX
:
3866 case QWORD_MNEM_SUFFIX
:
3867 i
.suffix
= mnem_p
[-1];
3869 current_templates
= (const templates
*) hash_find (op_hash
,
3872 case SHORT_MNEM_SUFFIX
:
3873 case LONG_MNEM_SUFFIX
:
3876 i
.suffix
= mnem_p
[-1];
3878 current_templates
= (const templates
*) hash_find (op_hash
,
3887 if (intel_float_operand (mnemonic
) == 1)
3888 i
.suffix
= SHORT_MNEM_SUFFIX
;
3890 i
.suffix
= LONG_MNEM_SUFFIX
;
3892 current_templates
= (const templates
*) hash_find (op_hash
,
3897 if (!current_templates
)
3899 as_bad (_("no such instruction: `%s'"), token_start
);
3904 if (current_templates
->start
->opcode_modifier
.jump
3905 || current_templates
->start
->opcode_modifier
.jumpbyte
)
3907 /* Check for a branch hint. We allow ",pt" and ",pn" for
3908 predict taken and predict not taken respectively.
3909 I'm not sure that branch hints actually do anything on loop
3910 and jcxz insns (JumpByte) for current Pentium4 chips. They
3911 may work in the future and it doesn't hurt to accept them
3913 if (l
[0] == ',' && l
[1] == 'p')
3917 if (!add_prefix (DS_PREFIX_OPCODE
))
3921 else if (l
[2] == 'n')
3923 if (!add_prefix (CS_PREFIX_OPCODE
))
3929 /* Any other comma loses. */
3932 as_bad (_("invalid character %s in mnemonic"),
3933 output_invalid (*l
));
3937 /* Check if instruction is supported on specified architecture. */
3939 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
3941 supported
|= cpu_flags_match (t
);
3942 if (supported
== CPU_FLAGS_PERFECT_MATCH
)
3946 if (!(supported
& CPU_FLAGS_64BIT_MATCH
))
3948 as_bad (flag_code
== CODE_64BIT
3949 ? _("`%s' is not supported in 64-bit mode")
3950 : _("`%s' is only supported in 64-bit mode"),
3951 current_templates
->start
->name
);
3954 if (supported
!= CPU_FLAGS_PERFECT_MATCH
)
3956 as_bad (_("`%s' is not supported on `%s%s'"),
3957 current_templates
->start
->name
,
3958 cpu_arch_name
? cpu_arch_name
: default_arch
,
3959 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
3964 if (!cpu_arch_flags
.bitfield
.cpui386
3965 && (flag_code
!= CODE_16BIT
))
3967 as_warn (_("use .code16 to ensure correct addressing mode"));
3974 parse_operands (char *l
, const char *mnemonic
)
3978 /* 1 if operand is pending after ','. */
3979 unsigned int expecting_operand
= 0;
3981 /* Non-zero if operand parens not balanced. */
3982 unsigned int paren_not_balanced
;
3984 while (*l
!= END_OF_INSN
)
3986 /* Skip optional white space before operand. */
3987 if (is_space_char (*l
))
3989 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
)
3991 as_bad (_("invalid character %s before operand %d"),
3992 output_invalid (*l
),
3996 token_start
= l
; /* after white space */
3997 paren_not_balanced
= 0;
3998 while (paren_not_balanced
|| *l
!= ',')
4000 if (*l
== END_OF_INSN
)
4002 if (paren_not_balanced
)
4005 as_bad (_("unbalanced parenthesis in operand %d."),
4008 as_bad (_("unbalanced brackets in operand %d."),
4013 break; /* we are done */
4015 else if (!is_operand_char (*l
) && !is_space_char (*l
))
4017 as_bad (_("invalid character %s in operand %d"),
4018 output_invalid (*l
),
4025 ++paren_not_balanced
;
4027 --paren_not_balanced
;
4032 ++paren_not_balanced
;
4034 --paren_not_balanced
;
4038 if (l
!= token_start
)
4039 { /* Yes, we've read in another operand. */
4040 unsigned int operand_ok
;
4041 this_operand
= i
.operands
++;
4042 i
.types
[this_operand
].bitfield
.unspecified
= 1;
4043 if (i
.operands
> MAX_OPERANDS
)
4045 as_bad (_("spurious operands; (%d operands/instruction max)"),
4049 /* Now parse operand adding info to 'i' as we go along. */
4050 END_STRING_AND_SAVE (l
);
4054 i386_intel_operand (token_start
,
4055 intel_float_operand (mnemonic
));
4057 operand_ok
= i386_att_operand (token_start
);
4059 RESTORE_END_STRING (l
);
4065 if (expecting_operand
)
4067 expecting_operand_after_comma
:
4068 as_bad (_("expecting operand after ','; got nothing"));
4073 as_bad (_("expecting operand before ','; got nothing"));
4078 /* Now *l must be either ',' or END_OF_INSN. */
4081 if (*++l
== END_OF_INSN
)
4083 /* Just skip it, if it's \n complain. */
4084 goto expecting_operand_after_comma
;
4086 expecting_operand
= 1;
4093 swap_2_operands (int xchg1
, int xchg2
)
4095 union i386_op temp_op
;
4096 i386_operand_type temp_type
;
4097 enum bfd_reloc_code_real temp_reloc
;
4099 temp_type
= i
.types
[xchg2
];
4100 i
.types
[xchg2
] = i
.types
[xchg1
];
4101 i
.types
[xchg1
] = temp_type
;
4102 temp_op
= i
.op
[xchg2
];
4103 i
.op
[xchg2
] = i
.op
[xchg1
];
4104 i
.op
[xchg1
] = temp_op
;
4105 temp_reloc
= i
.reloc
[xchg2
];
4106 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
4107 i
.reloc
[xchg1
] = temp_reloc
;
4111 if (i
.mask
->operand
== xchg1
)
4112 i
.mask
->operand
= xchg2
;
4113 else if (i
.mask
->operand
== xchg2
)
4114 i
.mask
->operand
= xchg1
;
4118 if (i
.broadcast
->operand
== xchg1
)
4119 i
.broadcast
->operand
= xchg2
;
4120 else if (i
.broadcast
->operand
== xchg2
)
4121 i
.broadcast
->operand
= xchg1
;
4125 if (i
.rounding
->operand
== xchg1
)
4126 i
.rounding
->operand
= xchg2
;
4127 else if (i
.rounding
->operand
== xchg2
)
4128 i
.rounding
->operand
= xchg1
;
4133 swap_operands (void)
4139 swap_2_operands (1, i
.operands
- 2);
4142 swap_2_operands (0, i
.operands
- 1);
4148 if (i
.mem_operands
== 2)
4150 const seg_entry
*temp_seg
;
4151 temp_seg
= i
.seg
[0];
4152 i
.seg
[0] = i
.seg
[1];
4153 i
.seg
[1] = temp_seg
;
4157 /* Try to ensure constant immediates are represented in the smallest
4162 char guess_suffix
= 0;
4166 guess_suffix
= i
.suffix
;
4167 else if (i
.reg_operands
)
4169 /* Figure out a suffix from the last register operand specified.
4170 We can't do this properly yet, ie. excluding InOutPortReg,
4171 but the following works for instructions with immediates.
4172 In any case, we can't set i.suffix yet. */
4173 for (op
= i
.operands
; --op
>= 0;)
4174 if (i
.types
[op
].bitfield
.reg8
)
4176 guess_suffix
= BYTE_MNEM_SUFFIX
;
4179 else if (i
.types
[op
].bitfield
.reg16
)
4181 guess_suffix
= WORD_MNEM_SUFFIX
;
4184 else if (i
.types
[op
].bitfield
.reg32
)
4186 guess_suffix
= LONG_MNEM_SUFFIX
;
4189 else if (i
.types
[op
].bitfield
.reg64
)
4191 guess_suffix
= QWORD_MNEM_SUFFIX
;
4195 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
4196 guess_suffix
= WORD_MNEM_SUFFIX
;
4198 for (op
= i
.operands
; --op
>= 0;)
4199 if (operand_type_check (i
.types
[op
], imm
))
4201 switch (i
.op
[op
].imms
->X_op
)
4204 /* If a suffix is given, this operand may be shortened. */
4205 switch (guess_suffix
)
4207 case LONG_MNEM_SUFFIX
:
4208 i
.types
[op
].bitfield
.imm32
= 1;
4209 i
.types
[op
].bitfield
.imm64
= 1;
4211 case WORD_MNEM_SUFFIX
:
4212 i
.types
[op
].bitfield
.imm16
= 1;
4213 i
.types
[op
].bitfield
.imm32
= 1;
4214 i
.types
[op
].bitfield
.imm32s
= 1;
4215 i
.types
[op
].bitfield
.imm64
= 1;
4217 case BYTE_MNEM_SUFFIX
:
4218 i
.types
[op
].bitfield
.imm8
= 1;
4219 i
.types
[op
].bitfield
.imm8s
= 1;
4220 i
.types
[op
].bitfield
.imm16
= 1;
4221 i
.types
[op
].bitfield
.imm32
= 1;
4222 i
.types
[op
].bitfield
.imm32s
= 1;
4223 i
.types
[op
].bitfield
.imm64
= 1;
4227 /* If this operand is at most 16 bits, convert it
4228 to a signed 16 bit number before trying to see
4229 whether it will fit in an even smaller size.
4230 This allows a 16-bit operand such as $0xffe0 to
4231 be recognised as within Imm8S range. */
4232 if ((i
.types
[op
].bitfield
.imm16
)
4233 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
4235 i
.op
[op
].imms
->X_add_number
=
4236 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
4238 if ((i
.types
[op
].bitfield
.imm32
)
4239 && ((i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1))
4242 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
4243 ^ ((offsetT
) 1 << 31))
4244 - ((offsetT
) 1 << 31));
4247 = operand_type_or (i
.types
[op
],
4248 smallest_imm_type (i
.op
[op
].imms
->X_add_number
));
4250 /* We must avoid matching of Imm32 templates when 64bit
4251 only immediate is available. */
4252 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
4253 i
.types
[op
].bitfield
.imm32
= 0;
4260 /* Symbols and expressions. */
4262 /* Convert symbolic operand to proper sizes for matching, but don't
4263 prevent matching a set of insns that only supports sizes other
4264 than those matching the insn suffix. */
4266 i386_operand_type mask
, allowed
;
4267 const insn_template
*t
;
4269 operand_type_set (&mask
, 0);
4270 operand_type_set (&allowed
, 0);
4272 for (t
= current_templates
->start
;
4273 t
< current_templates
->end
;
4275 allowed
= operand_type_or (allowed
,
4276 t
->operand_types
[op
]);
4277 switch (guess_suffix
)
4279 case QWORD_MNEM_SUFFIX
:
4280 mask
.bitfield
.imm64
= 1;
4281 mask
.bitfield
.imm32s
= 1;
4283 case LONG_MNEM_SUFFIX
:
4284 mask
.bitfield
.imm32
= 1;
4286 case WORD_MNEM_SUFFIX
:
4287 mask
.bitfield
.imm16
= 1;
4289 case BYTE_MNEM_SUFFIX
:
4290 mask
.bitfield
.imm8
= 1;
4295 allowed
= operand_type_and (mask
, allowed
);
4296 if (!operand_type_all_zero (&allowed
))
4297 i
.types
[op
] = operand_type_and (i
.types
[op
], mask
);
4304 /* Try to use the smallest displacement type too. */
4306 optimize_disp (void)
4310 for (op
= i
.operands
; --op
>= 0;)
4311 if (operand_type_check (i
.types
[op
], disp
))
4313 if (i
.op
[op
].disps
->X_op
== O_constant
)
4315 offsetT op_disp
= i
.op
[op
].disps
->X_add_number
;
4317 if (i
.types
[op
].bitfield
.disp16
4318 && (op_disp
& ~(offsetT
) 0xffff) == 0)
4320 /* If this operand is at most 16 bits, convert
4321 to a signed 16 bit number and don't use 64bit
4323 op_disp
= (((op_disp
& 0xffff) ^ 0x8000) - 0x8000);
4324 i
.types
[op
].bitfield
.disp64
= 0;
4326 if (i
.types
[op
].bitfield
.disp32
4327 && (op_disp
& ~(((offsetT
) 2 << 31) - 1)) == 0)
4329 /* If this operand is at most 32 bits, convert
4330 to a signed 32 bit number and don't use 64bit
4332 op_disp
&= (((offsetT
) 2 << 31) - 1);
4333 op_disp
= (op_disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
4334 i
.types
[op
].bitfield
.disp64
= 0;
4336 if (!op_disp
&& i
.types
[op
].bitfield
.baseindex
)
4338 i
.types
[op
].bitfield
.disp8
= 0;
4339 i
.types
[op
].bitfield
.disp16
= 0;
4340 i
.types
[op
].bitfield
.disp32
= 0;
4341 i
.types
[op
].bitfield
.disp32s
= 0;
4342 i
.types
[op
].bitfield
.disp64
= 0;
4346 else if (flag_code
== CODE_64BIT
)
4348 if (fits_in_signed_long (op_disp
))
4350 i
.types
[op
].bitfield
.disp64
= 0;
4351 i
.types
[op
].bitfield
.disp32s
= 1;
4353 if (i
.prefix
[ADDR_PREFIX
]
4354 && fits_in_unsigned_long (op_disp
))
4355 i
.types
[op
].bitfield
.disp32
= 1;
4357 if ((i
.types
[op
].bitfield
.disp32
4358 || i
.types
[op
].bitfield
.disp32s
4359 || i
.types
[op
].bitfield
.disp16
)
4360 && fits_in_signed_byte (op_disp
))
4361 i
.types
[op
].bitfield
.disp8
= 1;
4363 else if (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
4364 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
)
4366 fix_new_exp (frag_now
, frag_more (0) - frag_now
->fr_literal
, 0,
4367 i
.op
[op
].disps
, 0, i
.reloc
[op
]);
4368 i
.types
[op
].bitfield
.disp8
= 0;
4369 i
.types
[op
].bitfield
.disp16
= 0;
4370 i
.types
[op
].bitfield
.disp32
= 0;
4371 i
.types
[op
].bitfield
.disp32s
= 0;
4372 i
.types
[op
].bitfield
.disp64
= 0;
4375 /* We only support 64bit displacement on constants. */
4376 i
.types
[op
].bitfield
.disp64
= 0;
4380 /* Check if operands are valid for the instruction. */
4383 check_VecOperands (const insn_template
*t
)
4387 /* Without VSIB byte, we can't have a vector register for index. */
4388 if (!t
->opcode_modifier
.vecsib
4390 && (i
.index_reg
->reg_type
.bitfield
.regxmm
4391 || i
.index_reg
->reg_type
.bitfield
.regymm
4392 || i
.index_reg
->reg_type
.bitfield
.regzmm
))
4394 i
.error
= unsupported_vector_index_register
;
4398 /* Check if default mask is allowed. */
4399 if (t
->opcode_modifier
.nodefmask
4400 && (!i
.mask
|| i
.mask
->mask
->reg_num
== 0))
4402 i
.error
= no_default_mask
;
4406 /* For VSIB byte, we need a vector register for index, and all vector
4407 registers must be distinct. */
4408 if (t
->opcode_modifier
.vecsib
)
4411 || !((t
->opcode_modifier
.vecsib
== VecSIB128
4412 && i
.index_reg
->reg_type
.bitfield
.regxmm
)
4413 || (t
->opcode_modifier
.vecsib
== VecSIB256
4414 && i
.index_reg
->reg_type
.bitfield
.regymm
)
4415 || (t
->opcode_modifier
.vecsib
== VecSIB512
4416 && i
.index_reg
->reg_type
.bitfield
.regzmm
)))
4418 i
.error
= invalid_vsib_address
;
4422 gas_assert (i
.reg_operands
== 2 || i
.mask
);
4423 if (i
.reg_operands
== 2 && !i
.mask
)
4425 gas_assert (i
.types
[0].bitfield
.regxmm
4426 || i
.types
[0].bitfield
.regymm
);
4427 gas_assert (i
.types
[2].bitfield
.regxmm
4428 || i
.types
[2].bitfield
.regymm
);
4429 if (operand_check
== check_none
)
4431 if (register_number (i
.op
[0].regs
)
4432 != register_number (i
.index_reg
)
4433 && register_number (i
.op
[2].regs
)
4434 != register_number (i
.index_reg
)
4435 && register_number (i
.op
[0].regs
)
4436 != register_number (i
.op
[2].regs
))
4438 if (operand_check
== check_error
)
4440 i
.error
= invalid_vector_register_set
;
4443 as_warn (_("mask, index, and destination registers should be distinct"));
4445 else if (i
.reg_operands
== 1 && i
.mask
)
4447 if ((i
.types
[1].bitfield
.regymm
4448 || i
.types
[1].bitfield
.regzmm
)
4449 && (register_number (i
.op
[1].regs
)
4450 == register_number (i
.index_reg
)))
4452 if (operand_check
== check_error
)
4454 i
.error
= invalid_vector_register_set
;
4457 if (operand_check
!= check_none
)
4458 as_warn (_("index and destination registers should be distinct"));
4463 /* Check if broadcast is supported by the instruction and is applied
4464 to the memory operand. */
4467 int broadcasted_opnd_size
;
4469 /* Check if specified broadcast is supported in this instruction,
4470 and it's applied to memory operand of DWORD or QWORD type,
4471 depending on VecESize. */
4472 if (i
.broadcast
->type
!= t
->opcode_modifier
.broadcast
4473 || !i
.types
[i
.broadcast
->operand
].bitfield
.mem
4474 || (t
->opcode_modifier
.vecesize
== 0
4475 && !i
.types
[i
.broadcast
->operand
].bitfield
.dword
4476 && !i
.types
[i
.broadcast
->operand
].bitfield
.unspecified
)
4477 || (t
->opcode_modifier
.vecesize
== 1
4478 && !i
.types
[i
.broadcast
->operand
].bitfield
.qword
4479 && !i
.types
[i
.broadcast
->operand
].bitfield
.unspecified
))
4482 broadcasted_opnd_size
= t
->opcode_modifier
.vecesize
? 64 : 32;
4483 if (i
.broadcast
->type
== BROADCAST_1TO16
)
4484 broadcasted_opnd_size
<<= 4; /* Broadcast 1to16. */
4485 else if (i
.broadcast
->type
== BROADCAST_1TO8
)
4486 broadcasted_opnd_size
<<= 3; /* Broadcast 1to8. */
4487 else if (i
.broadcast
->type
== BROADCAST_1TO4
)
4488 broadcasted_opnd_size
<<= 2; /* Broadcast 1to4. */
4489 else if (i
.broadcast
->type
== BROADCAST_1TO2
)
4490 broadcasted_opnd_size
<<= 1; /* Broadcast 1to2. */
4494 if ((broadcasted_opnd_size
== 256
4495 && !t
->operand_types
[i
.broadcast
->operand
].bitfield
.ymmword
)
4496 || (broadcasted_opnd_size
== 512
4497 && !t
->operand_types
[i
.broadcast
->operand
].bitfield
.zmmword
))
4500 i
.error
= unsupported_broadcast
;
4504 /* If broadcast is supported in this instruction, we need to check if
4505 operand of one-element size isn't specified without broadcast. */
4506 else if (t
->opcode_modifier
.broadcast
&& i
.mem_operands
)
4508 /* Find memory operand. */
4509 for (op
= 0; op
< i
.operands
; op
++)
4510 if (operand_type_check (i
.types
[op
], anymem
))
4512 gas_assert (op
< i
.operands
);
4513 /* Check size of the memory operand. */
4514 if ((t
->opcode_modifier
.vecesize
== 0
4515 && i
.types
[op
].bitfield
.dword
)
4516 || (t
->opcode_modifier
.vecesize
== 1
4517 && i
.types
[op
].bitfield
.qword
))
4519 i
.error
= broadcast_needed
;
4524 /* Check if requested masking is supported. */
4526 && (!t
->opcode_modifier
.masking
4528 && t
->opcode_modifier
.masking
== MERGING_MASKING
)))
4530 i
.error
= unsupported_masking
;
4534 /* Check if masking is applied to dest operand. */
4535 if (i
.mask
&& (i
.mask
->operand
!= (int) (i
.operands
- 1)))
4537 i
.error
= mask_not_on_destination
;
4544 if ((i
.rounding
->type
!= saeonly
4545 && !t
->opcode_modifier
.staticrounding
)
4546 || (i
.rounding
->type
== saeonly
4547 && (t
->opcode_modifier
.staticrounding
4548 || !t
->opcode_modifier
.sae
)))
4550 i
.error
= unsupported_rc_sae
;
4553 /* If the instruction has several immediate operands and one of
4554 them is rounding, the rounding operand should be the last
4555 immediate operand. */
4556 if (i
.imm_operands
> 1
4557 && i
.rounding
->operand
!= (int) (i
.imm_operands
- 1))
4559 i
.error
= rc_sae_operand_not_last_imm
;
4564 /* Check vector Disp8 operand. */
4565 if (t
->opcode_modifier
.disp8memshift
)
4568 i
.memshift
= t
->opcode_modifier
.vecesize
? 3 : 2;
4570 i
.memshift
= t
->opcode_modifier
.disp8memshift
;
4572 for (op
= 0; op
< i
.operands
; op
++)
4573 if (operand_type_check (i
.types
[op
], disp
)
4574 && i
.op
[op
].disps
->X_op
== O_constant
)
4576 offsetT value
= i
.op
[op
].disps
->X_add_number
;
4577 int vec_disp8_ok
= fits_in_vec_disp8 (value
);
4578 if (t
->operand_types
[op
].bitfield
.vec_disp8
)
4581 i
.types
[op
].bitfield
.vec_disp8
= 1;
4584 /* Vector insn can only have Vec_Disp8/Disp32 in
4585 32/64bit modes, and Vec_Disp8/Disp16 in 16bit
4587 i
.types
[op
].bitfield
.disp8
= 0;
4588 if (flag_code
!= CODE_16BIT
)
4589 i
.types
[op
].bitfield
.disp16
= 0;
4592 else if (flag_code
!= CODE_16BIT
)
4594 /* One form of this instruction supports vector Disp8.
4595 Try vector Disp8 if we need to use Disp32. */
4596 if (vec_disp8_ok
&& !fits_in_signed_byte (value
))
4598 i
.error
= try_vector_disp8
;
4610 /* Check if operands are valid for the instruction. Update VEX
4614 VEX_check_operands (const insn_template
*t
)
4616 /* VREX is only valid with EVEX prefix. */
4617 if (i
.need_vrex
&& !t
->opcode_modifier
.evex
)
4619 i
.error
= invalid_register_operand
;
4623 if (!t
->opcode_modifier
.vex
)
4626 /* Only check VEX_Imm4, which must be the first operand. */
4627 if (t
->operand_types
[0].bitfield
.vec_imm4
)
4629 if (i
.op
[0].imms
->X_op
!= O_constant
4630 || !fits_in_imm4 (i
.op
[0].imms
->X_add_number
))
4636 /* Turn off Imm8 so that update_imm won't complain. */
4637 i
.types
[0] = vec_imm4
;
4643 static const insn_template
*
4644 match_template (void)
4646 /* Points to template once we've found it. */
4647 const insn_template
*t
;
4648 i386_operand_type overlap0
, overlap1
, overlap2
, overlap3
;
4649 i386_operand_type overlap4
;
4650 unsigned int found_reverse_match
;
4651 i386_opcode_modifier suffix_check
;
4652 i386_operand_type operand_types
[MAX_OPERANDS
];
4653 int addr_prefix_disp
;
4655 unsigned int found_cpu_match
;
4656 unsigned int check_register
;
4657 enum i386_error specific_error
= 0;
4659 #if MAX_OPERANDS != 5
4660 # error "MAX_OPERANDS must be 5."
4663 found_reverse_match
= 0;
4664 addr_prefix_disp
= -1;
4666 memset (&suffix_check
, 0, sizeof (suffix_check
));
4667 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
4668 suffix_check
.no_bsuf
= 1;
4669 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
4670 suffix_check
.no_wsuf
= 1;
4671 else if (i
.suffix
== SHORT_MNEM_SUFFIX
)
4672 suffix_check
.no_ssuf
= 1;
4673 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
4674 suffix_check
.no_lsuf
= 1;
4675 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
4676 suffix_check
.no_qsuf
= 1;
4677 else if (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
)
4678 suffix_check
.no_ldsuf
= 1;
4680 /* Must have right number of operands. */
4681 i
.error
= number_of_operands_mismatch
;
4683 for (t
= current_templates
->start
; t
< current_templates
->end
; t
++)
4685 addr_prefix_disp
= -1;
4687 if (i
.operands
!= t
->operands
)
4690 /* Check processor support. */
4691 i
.error
= unsupported
;
4692 found_cpu_match
= (cpu_flags_match (t
)
4693 == CPU_FLAGS_PERFECT_MATCH
);
4694 if (!found_cpu_match
)
4697 /* Check old gcc support. */
4698 i
.error
= old_gcc_only
;
4699 if (!old_gcc
&& t
->opcode_modifier
.oldgcc
)
4702 /* Check AT&T mnemonic. */
4703 i
.error
= unsupported_with_intel_mnemonic
;
4704 if (intel_mnemonic
&& t
->opcode_modifier
.attmnemonic
)
4707 /* Check AT&T/Intel syntax. */
4708 i
.error
= unsupported_syntax
;
4709 if ((intel_syntax
&& t
->opcode_modifier
.attsyntax
)
4710 || (!intel_syntax
&& t
->opcode_modifier
.intelsyntax
))
4713 /* Check the suffix, except for some instructions in intel mode. */
4714 i
.error
= invalid_instruction_suffix
;
4715 if ((!intel_syntax
|| !t
->opcode_modifier
.ignoresize
)
4716 && ((t
->opcode_modifier
.no_bsuf
&& suffix_check
.no_bsuf
)
4717 || (t
->opcode_modifier
.no_wsuf
&& suffix_check
.no_wsuf
)
4718 || (t
->opcode_modifier
.no_lsuf
&& suffix_check
.no_lsuf
)
4719 || (t
->opcode_modifier
.no_ssuf
&& suffix_check
.no_ssuf
)
4720 || (t
->opcode_modifier
.no_qsuf
&& suffix_check
.no_qsuf
)
4721 || (t
->opcode_modifier
.no_ldsuf
&& suffix_check
.no_ldsuf
)))
4724 if (!operand_size_match (t
))
4727 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4728 operand_types
[j
] = t
->operand_types
[j
];
4730 /* In general, don't allow 64-bit operands in 32-bit mode. */
4731 if (i
.suffix
== QWORD_MNEM_SUFFIX
4732 && flag_code
!= CODE_64BIT
4734 ? (!t
->opcode_modifier
.ignoresize
4735 && !intel_float_operand (t
->name
))
4736 : intel_float_operand (t
->name
) != 2)
4737 && ((!operand_types
[0].bitfield
.regmmx
4738 && !operand_types
[0].bitfield
.regxmm
4739 && !operand_types
[0].bitfield
.regymm
4740 && !operand_types
[0].bitfield
.regzmm
)
4741 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
4742 && operand_types
[t
->operands
> 1].bitfield
.regxmm
4743 && operand_types
[t
->operands
> 1].bitfield
.regymm
4744 && operand_types
[t
->operands
> 1].bitfield
.regzmm
))
4745 && (t
->base_opcode
!= 0x0fc7
4746 || t
->extension_opcode
!= 1 /* cmpxchg8b */))
4749 /* In general, don't allow 32-bit operands on pre-386. */
4750 else if (i
.suffix
== LONG_MNEM_SUFFIX
4751 && !cpu_arch_flags
.bitfield
.cpui386
4753 ? (!t
->opcode_modifier
.ignoresize
4754 && !intel_float_operand (t
->name
))
4755 : intel_float_operand (t
->name
) != 2)
4756 && ((!operand_types
[0].bitfield
.regmmx
4757 && !operand_types
[0].bitfield
.regxmm
)
4758 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
4759 && operand_types
[t
->operands
> 1].bitfield
.regxmm
)))
4762 /* Do not verify operands when there are none. */
4766 /* We've found a match; break out of loop. */
4770 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
4771 into Disp32/Disp16/Disp32 operand. */
4772 if (i
.prefix
[ADDR_PREFIX
] != 0)
4774 /* There should be only one Disp operand. */
4778 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4780 if (operand_types
[j
].bitfield
.disp16
)
4782 addr_prefix_disp
= j
;
4783 operand_types
[j
].bitfield
.disp32
= 1;
4784 operand_types
[j
].bitfield
.disp16
= 0;
4790 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4792 if (operand_types
[j
].bitfield
.disp32
)
4794 addr_prefix_disp
= j
;
4795 operand_types
[j
].bitfield
.disp32
= 0;
4796 operand_types
[j
].bitfield
.disp16
= 1;
4802 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4804 if (operand_types
[j
].bitfield
.disp64
)
4806 addr_prefix_disp
= j
;
4807 operand_types
[j
].bitfield
.disp64
= 0;
4808 operand_types
[j
].bitfield
.disp32
= 1;
4816 /* We check register size if needed. */
4817 check_register
= t
->opcode_modifier
.checkregsize
;
4818 overlap0
= operand_type_and (i
.types
[0], operand_types
[0]);
4819 switch (t
->operands
)
4822 if (!operand_type_match (overlap0
, i
.types
[0]))
4826 /* xchg %eax, %eax is a special case. It is an aliase for nop
4827 only in 32bit mode and we can use opcode 0x90. In 64bit
4828 mode, we can't use 0x90 for xchg %eax, %eax since it should
4829 zero-extend %eax to %rax. */
4830 if (flag_code
== CODE_64BIT
4831 && t
->base_opcode
== 0x90
4832 && operand_type_equal (&i
.types
[0], &acc32
)
4833 && operand_type_equal (&i
.types
[1], &acc32
))
4837 /* If we swap operand in encoding, we either match
4838 the next one or reverse direction of operands. */
4839 if (t
->opcode_modifier
.s
)
4841 else if (t
->opcode_modifier
.d
)
4846 /* If we swap operand in encoding, we match the next one. */
4847 if (i
.swap_operand
&& t
->opcode_modifier
.s
)
4851 overlap1
= operand_type_and (i
.types
[1], operand_types
[1]);
4852 if (!operand_type_match (overlap0
, i
.types
[0])
4853 || !operand_type_match (overlap1
, i
.types
[1])
4855 && !operand_type_register_match (overlap0
, i
.types
[0],
4857 overlap1
, i
.types
[1],
4860 /* Check if other direction is valid ... */
4861 if (!t
->opcode_modifier
.d
&& !t
->opcode_modifier
.floatd
)
4865 /* Try reversing direction of operands. */
4866 overlap0
= operand_type_and (i
.types
[0], operand_types
[1]);
4867 overlap1
= operand_type_and (i
.types
[1], operand_types
[0]);
4868 if (!operand_type_match (overlap0
, i
.types
[0])
4869 || !operand_type_match (overlap1
, i
.types
[1])
4871 && !operand_type_register_match (overlap0
,
4878 /* Does not match either direction. */
4881 /* found_reverse_match holds which of D or FloatDR
4883 if (t
->opcode_modifier
.d
)
4884 found_reverse_match
= Opcode_D
;
4885 else if (t
->opcode_modifier
.floatd
)
4886 found_reverse_match
= Opcode_FloatD
;
4888 found_reverse_match
= 0;
4889 if (t
->opcode_modifier
.floatr
)
4890 found_reverse_match
|= Opcode_FloatR
;
4894 /* Found a forward 2 operand match here. */
4895 switch (t
->operands
)
4898 overlap4
= operand_type_and (i
.types
[4],
4901 overlap3
= operand_type_and (i
.types
[3],
4904 overlap2
= operand_type_and (i
.types
[2],
4909 switch (t
->operands
)
4912 if (!operand_type_match (overlap4
, i
.types
[4])
4913 || !operand_type_register_match (overlap3
,
4921 if (!operand_type_match (overlap3
, i
.types
[3])
4923 && !operand_type_register_match (overlap2
,
4931 /* Here we make use of the fact that there are no
4932 reverse match 3 operand instructions, and all 3
4933 operand instructions only need to be checked for
4934 register consistency between operands 2 and 3. */
4935 if (!operand_type_match (overlap2
, i
.types
[2])
4937 && !operand_type_register_match (overlap1
,
4947 /* Found either forward/reverse 2, 3 or 4 operand match here:
4948 slip through to break. */
4950 if (!found_cpu_match
)
4952 found_reverse_match
= 0;
4956 /* Check if vector and VEX operands are valid. */
4957 if (check_VecOperands (t
) || VEX_check_operands (t
))
4959 specific_error
= i
.error
;
4963 /* We've found a match; break out of loop. */
4967 if (t
== current_templates
->end
)
4969 /* We found no match. */
4970 const char *err_msg
;
4971 switch (specific_error
? specific_error
: i
.error
)
4975 case operand_size_mismatch
:
4976 err_msg
= _("operand size mismatch");
4978 case operand_type_mismatch
:
4979 err_msg
= _("operand type mismatch");
4981 case register_type_mismatch
:
4982 err_msg
= _("register type mismatch");
4984 case number_of_operands_mismatch
:
4985 err_msg
= _("number of operands mismatch");
4987 case invalid_instruction_suffix
:
4988 err_msg
= _("invalid instruction suffix");
4991 err_msg
= _("constant doesn't fit in 4 bits");
4994 err_msg
= _("only supported with old gcc");
4996 case unsupported_with_intel_mnemonic
:
4997 err_msg
= _("unsupported with Intel mnemonic");
4999 case unsupported_syntax
:
5000 err_msg
= _("unsupported syntax");
5003 as_bad (_("unsupported instruction `%s'"),
5004 current_templates
->start
->name
);
5006 case invalid_vsib_address
:
5007 err_msg
= _("invalid VSIB address");
5009 case invalid_vector_register_set
:
5010 err_msg
= _("mask, index, and destination registers must be distinct");
5012 case unsupported_vector_index_register
:
5013 err_msg
= _("unsupported vector index register");
5015 case unsupported_broadcast
:
5016 err_msg
= _("unsupported broadcast");
5018 case broadcast_not_on_src_operand
:
5019 err_msg
= _("broadcast not on source memory operand");
5021 case broadcast_needed
:
5022 err_msg
= _("broadcast is needed for operand of such type");
5024 case unsupported_masking
:
5025 err_msg
= _("unsupported masking");
5027 case mask_not_on_destination
:
5028 err_msg
= _("mask not on destination operand");
5030 case no_default_mask
:
5031 err_msg
= _("default mask isn't allowed");
5033 case unsupported_rc_sae
:
5034 err_msg
= _("unsupported static rounding/sae");
5036 case rc_sae_operand_not_last_imm
:
5038 err_msg
= _("RC/SAE operand must precede immediate operands");
5040 err_msg
= _("RC/SAE operand must follow immediate operands");
5042 case invalid_register_operand
:
5043 err_msg
= _("invalid register operand");
5046 as_bad (_("%s for `%s'"), err_msg
,
5047 current_templates
->start
->name
);
5051 if (!quiet_warnings
)
5054 && (i
.types
[0].bitfield
.jumpabsolute
5055 != operand_types
[0].bitfield
.jumpabsolute
))
5057 as_warn (_("indirect %s without `*'"), t
->name
);
5060 if (t
->opcode_modifier
.isprefix
5061 && t
->opcode_modifier
.ignoresize
)
5063 /* Warn them that a data or address size prefix doesn't
5064 affect assembly of the next line of code. */
5065 as_warn (_("stand-alone `%s' prefix"), t
->name
);
5069 /* Copy the template we found. */
5072 if (addr_prefix_disp
!= -1)
5073 i
.tm
.operand_types
[addr_prefix_disp
]
5074 = operand_types
[addr_prefix_disp
];
5076 if (found_reverse_match
)
5078 /* If we found a reverse match we must alter the opcode
5079 direction bit. found_reverse_match holds bits to change
5080 (different for int & float insns). */
5082 i
.tm
.base_opcode
^= found_reverse_match
;
5084 i
.tm
.operand_types
[0] = operand_types
[1];
5085 i
.tm
.operand_types
[1] = operand_types
[0];
5094 int mem_op
= operand_type_check (i
.types
[0], anymem
) ? 0 : 1;
5095 if (i
.tm
.operand_types
[mem_op
].bitfield
.esseg
)
5097 if (i
.seg
[0] != NULL
&& i
.seg
[0] != &es
)
5099 as_bad (_("`%s' operand %d must use `%ses' segment"),
5105 /* There's only ever one segment override allowed per instruction.
5106 This instruction possibly has a legal segment override on the
5107 second operand, so copy the segment to where non-string
5108 instructions store it, allowing common code. */
5109 i
.seg
[0] = i
.seg
[1];
5111 else if (i
.tm
.operand_types
[mem_op
+ 1].bitfield
.esseg
)
5113 if (i
.seg
[1] != NULL
&& i
.seg
[1] != &es
)
5115 as_bad (_("`%s' operand %d must use `%ses' segment"),
5126 process_suffix (void)
5128 /* If matched instruction specifies an explicit instruction mnemonic
5130 if (i
.tm
.opcode_modifier
.size16
)
5131 i
.suffix
= WORD_MNEM_SUFFIX
;
5132 else if (i
.tm
.opcode_modifier
.size32
)
5133 i
.suffix
= LONG_MNEM_SUFFIX
;
5134 else if (i
.tm
.opcode_modifier
.size64
)
5135 i
.suffix
= QWORD_MNEM_SUFFIX
;
5136 else if (i
.reg_operands
)
5138 /* If there's no instruction mnemonic suffix we try to invent one
5139 based on register operands. */
5142 /* We take i.suffix from the last register operand specified,
5143 Destination register type is more significant than source
5144 register type. crc32 in SSE4.2 prefers source register
5146 if (i
.tm
.base_opcode
== 0xf20f38f1)
5148 if (i
.types
[0].bitfield
.reg16
)
5149 i
.suffix
= WORD_MNEM_SUFFIX
;
5150 else if (i
.types
[0].bitfield
.reg32
)
5151 i
.suffix
= LONG_MNEM_SUFFIX
;
5152 else if (i
.types
[0].bitfield
.reg64
)
5153 i
.suffix
= QWORD_MNEM_SUFFIX
;
5155 else if (i
.tm
.base_opcode
== 0xf20f38f0)
5157 if (i
.types
[0].bitfield
.reg8
)
5158 i
.suffix
= BYTE_MNEM_SUFFIX
;
5165 if (i
.tm
.base_opcode
== 0xf20f38f1
5166 || i
.tm
.base_opcode
== 0xf20f38f0)
5168 /* We have to know the operand size for crc32. */
5169 as_bad (_("ambiguous memory operand size for `%s`"),
5174 for (op
= i
.operands
; --op
>= 0;)
5175 if (!i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
5177 if (i
.types
[op
].bitfield
.reg8
)
5179 i
.suffix
= BYTE_MNEM_SUFFIX
;
5182 else if (i
.types
[op
].bitfield
.reg16
)
5184 i
.suffix
= WORD_MNEM_SUFFIX
;
5187 else if (i
.types
[op
].bitfield
.reg32
)
5189 i
.suffix
= LONG_MNEM_SUFFIX
;
5192 else if (i
.types
[op
].bitfield
.reg64
)
5194 i
.suffix
= QWORD_MNEM_SUFFIX
;
5200 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
5203 && i
.tm
.opcode_modifier
.ignoresize
5204 && i
.tm
.opcode_modifier
.no_bsuf
)
5206 else if (!check_byte_reg ())
5209 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
5212 && i
.tm
.opcode_modifier
.ignoresize
5213 && i
.tm
.opcode_modifier
.no_lsuf
)
5215 else if (!check_long_reg ())
5218 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
5221 && i
.tm
.opcode_modifier
.ignoresize
5222 && i
.tm
.opcode_modifier
.no_qsuf
)
5224 else if (!check_qword_reg ())
5227 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
5230 && i
.tm
.opcode_modifier
.ignoresize
5231 && i
.tm
.opcode_modifier
.no_wsuf
)
5233 else if (!check_word_reg ())
5236 else if (i
.suffix
== XMMWORD_MNEM_SUFFIX
5237 || i
.suffix
== YMMWORD_MNEM_SUFFIX
5238 || i
.suffix
== ZMMWORD_MNEM_SUFFIX
)
5240 /* Skip if the instruction has x/y/z suffix. match_template
5241 should check if it is a valid suffix. */
5243 else if (intel_syntax
&& i
.tm
.opcode_modifier
.ignoresize
)
5244 /* Do nothing if the instruction is going to ignore the prefix. */
5249 else if (i
.tm
.opcode_modifier
.defaultsize
5251 /* exclude fldenv/frstor/fsave/fstenv */
5252 && i
.tm
.opcode_modifier
.no_ssuf
)
5254 i
.suffix
= stackop_size
;
5256 else if (intel_syntax
5258 && (i
.tm
.operand_types
[0].bitfield
.jumpabsolute
5259 || i
.tm
.opcode_modifier
.jumpbyte
5260 || i
.tm
.opcode_modifier
.jumpintersegment
5261 || (i
.tm
.base_opcode
== 0x0f01 /* [ls][gi]dt */
5262 && i
.tm
.extension_opcode
<= 3)))
5267 if (!i
.tm
.opcode_modifier
.no_qsuf
)
5269 i
.suffix
= QWORD_MNEM_SUFFIX
;
5273 if (!i
.tm
.opcode_modifier
.no_lsuf
)
5274 i
.suffix
= LONG_MNEM_SUFFIX
;
5277 if (!i
.tm
.opcode_modifier
.no_wsuf
)
5278 i
.suffix
= WORD_MNEM_SUFFIX
;
5287 if (i
.tm
.opcode_modifier
.w
)
5289 as_bad (_("no instruction mnemonic suffix given and "
5290 "no register operands; can't size instruction"));
5296 unsigned int suffixes
;
5298 suffixes
= !i
.tm
.opcode_modifier
.no_bsuf
;
5299 if (!i
.tm
.opcode_modifier
.no_wsuf
)
5301 if (!i
.tm
.opcode_modifier
.no_lsuf
)
5303 if (!i
.tm
.opcode_modifier
.no_ldsuf
)
5305 if (!i
.tm
.opcode_modifier
.no_ssuf
)
5307 if (!i
.tm
.opcode_modifier
.no_qsuf
)
5310 /* There are more than suffix matches. */
5311 if (i
.tm
.opcode_modifier
.w
5312 || ((suffixes
& (suffixes
- 1))
5313 && !i
.tm
.opcode_modifier
.defaultsize
5314 && !i
.tm
.opcode_modifier
.ignoresize
))
5316 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
5322 /* Change the opcode based on the operand size given by i.suffix;
5323 We don't need to change things for byte insns. */
5326 && i
.suffix
!= BYTE_MNEM_SUFFIX
5327 && i
.suffix
!= XMMWORD_MNEM_SUFFIX
5328 && i
.suffix
!= YMMWORD_MNEM_SUFFIX
5329 && i
.suffix
!= ZMMWORD_MNEM_SUFFIX
)
5331 /* It's not a byte, select word/dword operation. */
5332 if (i
.tm
.opcode_modifier
.w
)
5334 if (i
.tm
.opcode_modifier
.shortform
)
5335 i
.tm
.base_opcode
|= 8;
5337 i
.tm
.base_opcode
|= 1;
5340 /* Now select between word & dword operations via the operand
5341 size prefix, except for instructions that will ignore this
5343 if (i
.tm
.opcode_modifier
.addrprefixop0
)
5345 /* The address size override prefix changes the size of the
5347 if ((flag_code
== CODE_32BIT
5348 && i
.op
->regs
[0].reg_type
.bitfield
.reg16
)
5349 || (flag_code
!= CODE_32BIT
5350 && i
.op
->regs
[0].reg_type
.bitfield
.reg32
))
5351 if (!add_prefix (ADDR_PREFIX_OPCODE
))
5354 else if (i
.suffix
!= QWORD_MNEM_SUFFIX
5355 && i
.suffix
!= LONG_DOUBLE_MNEM_SUFFIX
5356 && !i
.tm
.opcode_modifier
.ignoresize
5357 && !i
.tm
.opcode_modifier
.floatmf
5358 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
5359 || (flag_code
== CODE_64BIT
5360 && i
.tm
.opcode_modifier
.jumpbyte
)))
5362 unsigned int prefix
= DATA_PREFIX_OPCODE
;
5364 if (i
.tm
.opcode_modifier
.jumpbyte
) /* jcxz, loop */
5365 prefix
= ADDR_PREFIX_OPCODE
;
5367 if (!add_prefix (prefix
))
5371 /* Set mode64 for an operand. */
5372 if (i
.suffix
== QWORD_MNEM_SUFFIX
5373 && flag_code
== CODE_64BIT
5374 && !i
.tm
.opcode_modifier
.norex64
)
5376 /* Special case for xchg %rax,%rax. It is NOP and doesn't
5377 need rex64. cmpxchg8b is also a special case. */
5378 if (! (i
.operands
== 2
5379 && i
.tm
.base_opcode
== 0x90
5380 && i
.tm
.extension_opcode
== None
5381 && operand_type_equal (&i
.types
[0], &acc64
)
5382 && operand_type_equal (&i
.types
[1], &acc64
))
5383 && ! (i
.operands
== 1
5384 && i
.tm
.base_opcode
== 0xfc7
5385 && i
.tm
.extension_opcode
== 1
5386 && !operand_type_check (i
.types
[0], reg
)
5387 && operand_type_check (i
.types
[0], anymem
)))
5391 /* Size floating point instruction. */
5392 if (i
.suffix
== LONG_MNEM_SUFFIX
)
5393 if (i
.tm
.opcode_modifier
.floatmf
)
5394 i
.tm
.base_opcode
^= 4;
5401 check_byte_reg (void)
5405 for (op
= i
.operands
; --op
>= 0;)
5407 /* If this is an eight bit register, it's OK. If it's the 16 or
5408 32 bit version of an eight bit register, we will just use the
5409 low portion, and that's OK too. */
5410 if (i
.types
[op
].bitfield
.reg8
)
5413 /* I/O port address operands are OK too. */
5414 if (i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
5417 /* crc32 doesn't generate this warning. */
5418 if (i
.tm
.base_opcode
== 0xf20f38f0)
5421 if ((i
.types
[op
].bitfield
.reg16
5422 || i
.types
[op
].bitfield
.reg32
5423 || i
.types
[op
].bitfield
.reg64
)
5424 && i
.op
[op
].regs
->reg_num
< 4
5425 /* Prohibit these changes in 64bit mode, since the lowering
5426 would be more complicated. */
5427 && flag_code
!= CODE_64BIT
)
5429 #if REGISTER_WARNINGS
5430 if (!quiet_warnings
)
5431 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5433 (i
.op
[op
].regs
+ (i
.types
[op
].bitfield
.reg16
5434 ? REGNAM_AL
- REGNAM_AX
5435 : REGNAM_AL
- REGNAM_EAX
))->reg_name
,
5437 i
.op
[op
].regs
->reg_name
,
5442 /* Any other register is bad. */
5443 if (i
.types
[op
].bitfield
.reg16
5444 || i
.types
[op
].bitfield
.reg32
5445 || i
.types
[op
].bitfield
.reg64
5446 || i
.types
[op
].bitfield
.regmmx
5447 || i
.types
[op
].bitfield
.regxmm
5448 || i
.types
[op
].bitfield
.regymm
5449 || i
.types
[op
].bitfield
.regzmm
5450 || i
.types
[op
].bitfield
.sreg2
5451 || i
.types
[op
].bitfield
.sreg3
5452 || i
.types
[op
].bitfield
.control
5453 || i
.types
[op
].bitfield
.debug
5454 || i
.types
[op
].bitfield
.test
5455 || i
.types
[op
].bitfield
.floatreg
5456 || i
.types
[op
].bitfield
.floatacc
)
5458 as_bad (_("`%s%s' not allowed with `%s%c'"),
5460 i
.op
[op
].regs
->reg_name
,
5470 check_long_reg (void)
5474 for (op
= i
.operands
; --op
>= 0;)
5475 /* Reject eight bit registers, except where the template requires
5476 them. (eg. movzb) */
5477 if (i
.types
[op
].bitfield
.reg8
5478 && (i
.tm
.operand_types
[op
].bitfield
.reg16
5479 || i
.tm
.operand_types
[op
].bitfield
.reg32
5480 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5482 as_bad (_("`%s%s' not allowed with `%s%c'"),
5484 i
.op
[op
].regs
->reg_name
,
5489 /* Warn if the e prefix on a general reg is missing. */
5490 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
5491 && i
.types
[op
].bitfield
.reg16
5492 && (i
.tm
.operand_types
[op
].bitfield
.reg32
5493 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5495 /* Prohibit these changes in the 64bit mode, since the
5496 lowering is more complicated. */
5497 if (flag_code
== CODE_64BIT
)
5499 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5500 register_prefix
, i
.op
[op
].regs
->reg_name
,
5504 #if REGISTER_WARNINGS
5505 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5507 (i
.op
[op
].regs
+ REGNAM_EAX
- REGNAM_AX
)->reg_name
,
5508 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
5511 /* Warn if the r prefix on a general reg is present. */
5512 else if (i
.types
[op
].bitfield
.reg64
5513 && (i
.tm
.operand_types
[op
].bitfield
.reg32
5514 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5517 && i
.tm
.opcode_modifier
.toqword
5518 && !i
.types
[0].bitfield
.regxmm
)
5520 /* Convert to QWORD. We want REX byte. */
5521 i
.suffix
= QWORD_MNEM_SUFFIX
;
5525 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5526 register_prefix
, i
.op
[op
].regs
->reg_name
,
5535 check_qword_reg (void)
5539 for (op
= i
.operands
; --op
>= 0; )
5540 /* Reject eight bit registers, except where the template requires
5541 them. (eg. movzb) */
5542 if (i
.types
[op
].bitfield
.reg8
5543 && (i
.tm
.operand_types
[op
].bitfield
.reg16
5544 || i
.tm
.operand_types
[op
].bitfield
.reg32
5545 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5547 as_bad (_("`%s%s' not allowed with `%s%c'"),
5549 i
.op
[op
].regs
->reg_name
,
5554 /* Warn if the r prefix on a general reg is missing. */
5555 else if ((i
.types
[op
].bitfield
.reg16
5556 || i
.types
[op
].bitfield
.reg32
)
5557 && (i
.tm
.operand_types
[op
].bitfield
.reg32
5558 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5560 /* Prohibit these changes in the 64bit mode, since the
5561 lowering is more complicated. */
5563 && i
.tm
.opcode_modifier
.todword
5564 && !i
.types
[0].bitfield
.regxmm
)
5566 /* Convert to DWORD. We don't want REX byte. */
5567 i
.suffix
= LONG_MNEM_SUFFIX
;
5571 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5572 register_prefix
, i
.op
[op
].regs
->reg_name
,
5581 check_word_reg (void)
5584 for (op
= i
.operands
; --op
>= 0;)
5585 /* Reject eight bit registers, except where the template requires
5586 them. (eg. movzb) */
5587 if (i
.types
[op
].bitfield
.reg8
5588 && (i
.tm
.operand_types
[op
].bitfield
.reg16
5589 || i
.tm
.operand_types
[op
].bitfield
.reg32
5590 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5592 as_bad (_("`%s%s' not allowed with `%s%c'"),
5594 i
.op
[op
].regs
->reg_name
,
5599 /* Warn if the e or r prefix on a general reg is present. */
5600 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
5601 && (i
.types
[op
].bitfield
.reg32
5602 || i
.types
[op
].bitfield
.reg64
)
5603 && (i
.tm
.operand_types
[op
].bitfield
.reg16
5604 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5606 /* Prohibit these changes in the 64bit mode, since the
5607 lowering is more complicated. */
5608 if (flag_code
== CODE_64BIT
)
5610 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5611 register_prefix
, i
.op
[op
].regs
->reg_name
,
5615 #if REGISTER_WARNINGS
5616 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5618 (i
.op
[op
].regs
+ REGNAM_AX
- REGNAM_EAX
)->reg_name
,
5619 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
5626 update_imm (unsigned int j
)
5628 i386_operand_type overlap
= i
.types
[j
];
5629 if ((overlap
.bitfield
.imm8
5630 || overlap
.bitfield
.imm8s
5631 || overlap
.bitfield
.imm16
5632 || overlap
.bitfield
.imm32
5633 || overlap
.bitfield
.imm32s
5634 || overlap
.bitfield
.imm64
)
5635 && !operand_type_equal (&overlap
, &imm8
)
5636 && !operand_type_equal (&overlap
, &imm8s
)
5637 && !operand_type_equal (&overlap
, &imm16
)
5638 && !operand_type_equal (&overlap
, &imm32
)
5639 && !operand_type_equal (&overlap
, &imm32s
)
5640 && !operand_type_equal (&overlap
, &imm64
))
5644 i386_operand_type temp
;
5646 operand_type_set (&temp
, 0);
5647 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
5649 temp
.bitfield
.imm8
= overlap
.bitfield
.imm8
;
5650 temp
.bitfield
.imm8s
= overlap
.bitfield
.imm8s
;
5652 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
5653 temp
.bitfield
.imm16
= overlap
.bitfield
.imm16
;
5654 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
5656 temp
.bitfield
.imm64
= overlap
.bitfield
.imm64
;
5657 temp
.bitfield
.imm32s
= overlap
.bitfield
.imm32s
;
5660 temp
.bitfield
.imm32
= overlap
.bitfield
.imm32
;
5663 else if (operand_type_equal (&overlap
, &imm16_32_32s
)
5664 || operand_type_equal (&overlap
, &imm16_32
)
5665 || operand_type_equal (&overlap
, &imm16_32s
))
5667 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
5672 if (!operand_type_equal (&overlap
, &imm8
)
5673 && !operand_type_equal (&overlap
, &imm8s
)
5674 && !operand_type_equal (&overlap
, &imm16
)
5675 && !operand_type_equal (&overlap
, &imm32
)
5676 && !operand_type_equal (&overlap
, &imm32s
)
5677 && !operand_type_equal (&overlap
, &imm64
))
5679 as_bad (_("no instruction mnemonic suffix given; "
5680 "can't determine immediate size"));
5684 i
.types
[j
] = overlap
;
5694 /* Update the first 2 immediate operands. */
5695 n
= i
.operands
> 2 ? 2 : i
.operands
;
5698 for (j
= 0; j
< n
; j
++)
5699 if (update_imm (j
) == 0)
5702 /* The 3rd operand can't be immediate operand. */
5703 gas_assert (operand_type_check (i
.types
[2], imm
) == 0);
5710 bad_implicit_operand (int xmm
)
5712 const char *ireg
= xmm
? "xmm0" : "ymm0";
5715 as_bad (_("the last operand of `%s' must be `%s%s'"),
5716 i
.tm
.name
, register_prefix
, ireg
);
5718 as_bad (_("the first operand of `%s' must be `%s%s'"),
5719 i
.tm
.name
, register_prefix
, ireg
);
5724 process_operands (void)
5726 /* Default segment register this instruction will use for memory
5727 accesses. 0 means unknown. This is only for optimizing out
5728 unnecessary segment overrides. */
5729 const seg_entry
*default_seg
= 0;
5731 if (i
.tm
.opcode_modifier
.sse2avx
&& i
.tm
.opcode_modifier
.vexvvvv
)
5733 unsigned int dupl
= i
.operands
;
5734 unsigned int dest
= dupl
- 1;
5737 /* The destination must be an xmm register. */
5738 gas_assert (i
.reg_operands
5739 && MAX_OPERANDS
> dupl
5740 && operand_type_equal (&i
.types
[dest
], ®xmm
));
5742 if (i
.tm
.opcode_modifier
.firstxmm0
)
5744 /* The first operand is implicit and must be xmm0. */
5745 gas_assert (operand_type_equal (&i
.types
[0], ®xmm
));
5746 if (register_number (i
.op
[0].regs
) != 0)
5747 return bad_implicit_operand (1);
5749 if (i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
)
5751 /* Keep xmm0 for instructions with VEX prefix and 3
5757 /* We remove the first xmm0 and keep the number of
5758 operands unchanged, which in fact duplicates the
5760 for (j
= 1; j
< i
.operands
; j
++)
5762 i
.op
[j
- 1] = i
.op
[j
];
5763 i
.types
[j
- 1] = i
.types
[j
];
5764 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
5768 else if (i
.tm
.opcode_modifier
.implicit1stxmm0
)
5770 gas_assert ((MAX_OPERANDS
- 1) > dupl
5771 && (i
.tm
.opcode_modifier
.vexsources
5774 /* Add the implicit xmm0 for instructions with VEX prefix
5776 for (j
= i
.operands
; j
> 0; j
--)
5778 i
.op
[j
] = i
.op
[j
- 1];
5779 i
.types
[j
] = i
.types
[j
- 1];
5780 i
.tm
.operand_types
[j
] = i
.tm
.operand_types
[j
- 1];
5783 = (const reg_entry
*) hash_find (reg_hash
, "xmm0");
5784 i
.types
[0] = regxmm
;
5785 i
.tm
.operand_types
[0] = regxmm
;
5788 i
.reg_operands
+= 2;
5793 i
.op
[dupl
] = i
.op
[dest
];
5794 i
.types
[dupl
] = i
.types
[dest
];
5795 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
5804 i
.op
[dupl
] = i
.op
[dest
];
5805 i
.types
[dupl
] = i
.types
[dest
];
5806 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
5809 if (i
.tm
.opcode_modifier
.immext
)
5812 else if (i
.tm
.opcode_modifier
.firstxmm0
)
5816 /* The first operand is implicit and must be xmm0/ymm0/zmm0. */
5817 gas_assert (i
.reg_operands
5818 && (operand_type_equal (&i
.types
[0], ®xmm
)
5819 || operand_type_equal (&i
.types
[0], ®ymm
)
5820 || operand_type_equal (&i
.types
[0], ®zmm
)));
5821 if (register_number (i
.op
[0].regs
) != 0)
5822 return bad_implicit_operand (i
.types
[0].bitfield
.regxmm
);
5824 for (j
= 1; j
< i
.operands
; j
++)
5826 i
.op
[j
- 1] = i
.op
[j
];
5827 i
.types
[j
- 1] = i
.types
[j
];
5829 /* We need to adjust fields in i.tm since they are used by
5830 build_modrm_byte. */
5831 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
5838 else if (i
.tm
.opcode_modifier
.regkludge
)
5840 /* The imul $imm, %reg instruction is converted into
5841 imul $imm, %reg, %reg, and the clr %reg instruction
5842 is converted into xor %reg, %reg. */
5844 unsigned int first_reg_op
;
5846 if (operand_type_check (i
.types
[0], reg
))
5850 /* Pretend we saw the extra register operand. */
5851 gas_assert (i
.reg_operands
== 1
5852 && i
.op
[first_reg_op
+ 1].regs
== 0);
5853 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
5854 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
5859 if (i
.tm
.opcode_modifier
.shortform
)
5861 if (i
.types
[0].bitfield
.sreg2
5862 || i
.types
[0].bitfield
.sreg3
)
5864 if (i
.tm
.base_opcode
== POP_SEG_SHORT
5865 && i
.op
[0].regs
->reg_num
== 1)
5867 as_bad (_("you can't `pop %scs'"), register_prefix
);
5870 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
5871 if ((i
.op
[0].regs
->reg_flags
& RegRex
) != 0)
5876 /* The register or float register operand is in operand
5880 if (i
.types
[0].bitfield
.floatreg
5881 || operand_type_check (i
.types
[0], reg
))
5885 /* Register goes in low 3 bits of opcode. */
5886 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
5887 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
5889 if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
5891 /* Warn about some common errors, but press on regardless.
5892 The first case can be generated by gcc (<= 2.8.1). */
5893 if (i
.operands
== 2)
5895 /* Reversed arguments on faddp, fsubp, etc. */
5896 as_warn (_("translating to `%s %s%s,%s%s'"), i
.tm
.name
,
5897 register_prefix
, i
.op
[!intel_syntax
].regs
->reg_name
,
5898 register_prefix
, i
.op
[intel_syntax
].regs
->reg_name
);
5902 /* Extraneous `l' suffix on fp insn. */
5903 as_warn (_("translating to `%s %s%s'"), i
.tm
.name
,
5904 register_prefix
, i
.op
[0].regs
->reg_name
);
5909 else if (i
.tm
.opcode_modifier
.modrm
)
5911 /* The opcode is completed (modulo i.tm.extension_opcode which
5912 must be put into the modrm byte). Now, we make the modrm and
5913 index base bytes based on all the info we've collected. */
5915 default_seg
= build_modrm_byte ();
5917 else if ((i
.tm
.base_opcode
& ~0x3) == MOV_AX_DISP32
)
5921 else if (i
.tm
.opcode_modifier
.isstring
)
5923 /* For the string instructions that allow a segment override
5924 on one of their operands, the default segment is ds. */
5928 if (i
.tm
.base_opcode
== 0x8d /* lea */
5931 as_warn (_("segment override on `%s' is ineffectual"), i
.tm
.name
);
5933 /* If a segment was explicitly specified, and the specified segment
5934 is not the default, use an opcode prefix to select it. If we
5935 never figured out what the default segment is, then default_seg
5936 will be zero at this point, and the specified segment prefix will
5938 if ((i
.seg
[0]) && (i
.seg
[0] != default_seg
))
5940 if (!add_prefix (i
.seg
[0]->seg_prefix
))
5946 static const seg_entry
*
5947 build_modrm_byte (void)
5949 const seg_entry
*default_seg
= 0;
5950 unsigned int source
, dest
;
5953 /* The first operand of instructions with VEX prefix and 3 sources
5954 must be VEX_Imm4. */
5955 vex_3_sources
= i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
;
5958 unsigned int nds
, reg_slot
;
5961 if (i
.tm
.opcode_modifier
.veximmext
5962 && i
.tm
.opcode_modifier
.immext
)
5964 dest
= i
.operands
- 2;
5965 gas_assert (dest
== 3);
5968 dest
= i
.operands
- 1;
5971 /* There are 2 kinds of instructions:
5972 1. 5 operands: 4 register operands or 3 register operands
5973 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
5974 VexW0 or VexW1. The destination must be either XMM, YMM or
5976 2. 4 operands: 4 register operands or 3 register operands
5977 plus 1 memory operand, VexXDS, and VexImmExt */
5978 gas_assert ((i
.reg_operands
== 4
5979 || (i
.reg_operands
== 3 && i
.mem_operands
== 1))
5980 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
5981 && (i
.tm
.opcode_modifier
.veximmext
5982 || (i
.imm_operands
== 1
5983 && i
.types
[0].bitfield
.vec_imm4
5984 && (i
.tm
.opcode_modifier
.vexw
== VEXW0
5985 || i
.tm
.opcode_modifier
.vexw
== VEXW1
)
5986 && (operand_type_equal (&i
.tm
.operand_types
[dest
], ®xmm
)
5987 || operand_type_equal (&i
.tm
.operand_types
[dest
], ®ymm
)
5988 || operand_type_equal (&i
.tm
.operand_types
[dest
], ®zmm
)))));
5990 if (i
.imm_operands
== 0)
5992 /* When there is no immediate operand, generate an 8bit
5993 immediate operand to encode the first operand. */
5994 exp
= &im_expressions
[i
.imm_operands
++];
5995 i
.op
[i
.operands
].imms
= exp
;
5996 i
.types
[i
.operands
] = imm8
;
5998 /* If VexW1 is set, the first operand is the source and
5999 the second operand is encoded in the immediate operand. */
6000 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
6011 /* FMA swaps REG and NDS. */
6012 if (i
.tm
.cpu_flags
.bitfield
.cpufma
)
6020 gas_assert (operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6022 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6024 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6026 exp
->X_op
= O_constant
;
6027 exp
->X_add_number
= register_number (i
.op
[reg_slot
].regs
) << 4;
6028 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
6032 unsigned int imm_slot
;
6034 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
6036 /* If VexW0 is set, the third operand is the source and
6037 the second operand is encoded in the immediate
6044 /* VexW1 is set, the second operand is the source and
6045 the third operand is encoded in the immediate
6051 if (i
.tm
.opcode_modifier
.immext
)
6053 /* When ImmExt is set, the immdiate byte is the last
6055 imm_slot
= i
.operands
- 1;
6063 /* Turn on Imm8 so that output_imm will generate it. */
6064 i
.types
[imm_slot
].bitfield
.imm8
= 1;
6067 gas_assert (operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6069 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6071 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6073 i
.op
[imm_slot
].imms
->X_add_number
6074 |= register_number (i
.op
[reg_slot
].regs
) << 4;
6075 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
6078 gas_assert (operand_type_equal (&i
.tm
.operand_types
[nds
], ®xmm
)
6079 || operand_type_equal (&i
.tm
.operand_types
[nds
],
6081 || operand_type_equal (&i
.tm
.operand_types
[nds
],
6083 i
.vex
.register_specifier
= i
.op
[nds
].regs
;
6088 /* i.reg_operands MUST be the number of real register operands;
6089 implicit registers do not count. If there are 3 register
6090 operands, it must be a instruction with VexNDS. For a
6091 instruction with VexNDD, the destination register is encoded
6092 in VEX prefix. If there are 4 register operands, it must be
6093 a instruction with VEX prefix and 3 sources. */
6094 if (i
.mem_operands
== 0
6095 && ((i
.reg_operands
== 2
6096 && i
.tm
.opcode_modifier
.vexvvvv
<= VEXXDS
)
6097 || (i
.reg_operands
== 3
6098 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
6099 || (i
.reg_operands
== 4 && vex_3_sources
)))
6107 /* When there are 3 operands, one of them may be immediate,
6108 which may be the first or the last operand. Otherwise,
6109 the first operand must be shift count register (cl) or it
6110 is an instruction with VexNDS. */
6111 gas_assert (i
.imm_operands
== 1
6112 || (i
.imm_operands
== 0
6113 && (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
6114 || i
.types
[0].bitfield
.shiftcount
)));
6115 if (operand_type_check (i
.types
[0], imm
)
6116 || i
.types
[0].bitfield
.shiftcount
)
6122 /* When there are 4 operands, the first two must be 8bit
6123 immediate operands. The source operand will be the 3rd
6126 For instructions with VexNDS, if the first operand
6127 an imm8, the source operand is the 2nd one. If the last
6128 operand is imm8, the source operand is the first one. */
6129 gas_assert ((i
.imm_operands
== 2
6130 && i
.types
[0].bitfield
.imm8
6131 && i
.types
[1].bitfield
.imm8
)
6132 || (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
6133 && i
.imm_operands
== 1
6134 && (i
.types
[0].bitfield
.imm8
6135 || i
.types
[i
.operands
- 1].bitfield
.imm8
6137 if (i
.imm_operands
== 2)
6141 if (i
.types
[0].bitfield
.imm8
)
6148 if (i
.tm
.opcode_modifier
.evex
)
6150 /* For EVEX instructions, when there are 5 operands, the
6151 first one must be immediate operand. If the second one
6152 is immediate operand, the source operand is the 3th
6153 one. If the last one is immediate operand, the source
6154 operand is the 2nd one. */
6155 gas_assert (i
.imm_operands
== 2
6156 && i
.tm
.opcode_modifier
.sae
6157 && operand_type_check (i
.types
[0], imm
));
6158 if (operand_type_check (i
.types
[1], imm
))
6160 else if (operand_type_check (i
.types
[4], imm
))
6174 /* RC/SAE operand could be between DEST and SRC. That happens
6175 when one operand is GPR and the other one is XMM/YMM/ZMM
6177 if (i
.rounding
&& i
.rounding
->operand
== (int) dest
)
6180 if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
6182 /* For instructions with VexNDS, the register-only source
6183 operand must be 32/64bit integer, XMM, YMM or ZMM
6184 register. It is encoded in VEX prefix. We need to
6185 clear RegMem bit before calling operand_type_equal. */
6187 i386_operand_type op
;
6190 /* Check register-only source operand when two source
6191 operands are swapped. */
6192 if (!i
.tm
.operand_types
[source
].bitfield
.baseindex
6193 && i
.tm
.operand_types
[dest
].bitfield
.baseindex
)
6201 op
= i
.tm
.operand_types
[vvvv
];
6202 op
.bitfield
.regmem
= 0;
6203 if ((dest
+ 1) >= i
.operands
6204 || (!op
.bitfield
.reg32
6205 && op
.bitfield
.reg64
6206 && !operand_type_equal (&op
, ®xmm
)
6207 && !operand_type_equal (&op
, ®ymm
)
6208 && !operand_type_equal (&op
, ®zmm
)
6209 && !operand_type_equal (&op
, ®mask
)))
6211 i
.vex
.register_specifier
= i
.op
[vvvv
].regs
;
6217 /* One of the register operands will be encoded in the i.tm.reg
6218 field, the other in the combined i.tm.mode and i.tm.regmem
6219 fields. If no form of this instruction supports a memory
6220 destination operand, then we assume the source operand may
6221 sometimes be a memory operand and so we need to store the
6222 destination in the i.rm.reg field. */
6223 if (!i
.tm
.operand_types
[dest
].bitfield
.regmem
6224 && operand_type_check (i
.tm
.operand_types
[dest
], anymem
) == 0)
6226 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
6227 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
6228 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
6230 if ((i
.op
[dest
].regs
->reg_flags
& RegVRex
) != 0)
6232 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
6234 if ((i
.op
[source
].regs
->reg_flags
& RegVRex
) != 0)
6239 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
6240 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
6241 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
6243 if ((i
.op
[dest
].regs
->reg_flags
& RegVRex
) != 0)
6245 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
6247 if ((i
.op
[source
].regs
->reg_flags
& RegVRex
) != 0)
6250 if (flag_code
!= CODE_64BIT
&& (i
.rex
& (REX_R
| REX_B
)))
6252 if (!i
.types
[0].bitfield
.control
6253 && !i
.types
[1].bitfield
.control
)
6255 i
.rex
&= ~(REX_R
| REX_B
);
6256 add_prefix (LOCK_PREFIX_OPCODE
);
6260 { /* If it's not 2 reg operands... */
6265 unsigned int fake_zero_displacement
= 0;
6268 for (op
= 0; op
< i
.operands
; op
++)
6269 if (operand_type_check (i
.types
[op
], anymem
))
6271 gas_assert (op
< i
.operands
);
6273 if (i
.tm
.opcode_modifier
.vecsib
)
6275 if (i
.index_reg
->reg_num
== RegEiz
6276 || i
.index_reg
->reg_num
== RegRiz
)
6279 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6282 i
.sib
.base
= NO_BASE_REGISTER
;
6283 i
.sib
.scale
= i
.log2_scale_factor
;
6284 /* No Vec_Disp8 if there is no base. */
6285 i
.types
[op
].bitfield
.vec_disp8
= 0;
6286 i
.types
[op
].bitfield
.disp8
= 0;
6287 i
.types
[op
].bitfield
.disp16
= 0;
6288 i
.types
[op
].bitfield
.disp64
= 0;
6289 if (flag_code
!= CODE_64BIT
)
6291 /* Must be 32 bit */
6292 i
.types
[op
].bitfield
.disp32
= 1;
6293 i
.types
[op
].bitfield
.disp32s
= 0;
6297 i
.types
[op
].bitfield
.disp32
= 0;
6298 i
.types
[op
].bitfield
.disp32s
= 1;
6301 i
.sib
.index
= i
.index_reg
->reg_num
;
6302 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
6304 if ((i
.index_reg
->reg_flags
& RegVRex
) != 0)
6310 if (i
.base_reg
== 0)
6313 if (!i
.disp_operands
)
6315 fake_zero_displacement
= 1;
6316 /* Instructions with VSIB byte need 32bit displacement
6317 if there is no base register. */
6318 if (i
.tm
.opcode_modifier
.vecsib
)
6319 i
.types
[op
].bitfield
.disp32
= 1;
6321 if (i
.index_reg
== 0)
6323 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6324 /* Operand is just <disp> */
6325 if (flag_code
== CODE_64BIT
)
6327 /* 64bit mode overwrites the 32bit absolute
6328 addressing by RIP relative addressing and
6329 absolute addressing is encoded by one of the
6330 redundant SIB forms. */
6331 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6332 i
.sib
.base
= NO_BASE_REGISTER
;
6333 i
.sib
.index
= NO_INDEX_REGISTER
;
6334 i
.types
[op
] = ((i
.prefix
[ADDR_PREFIX
] == 0)
6335 ? disp32s
: disp32
);
6337 else if ((flag_code
== CODE_16BIT
)
6338 ^ (i
.prefix
[ADDR_PREFIX
] != 0))
6340 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
6341 i
.types
[op
] = disp16
;
6345 i
.rm
.regmem
= NO_BASE_REGISTER
;
6346 i
.types
[op
] = disp32
;
6349 else if (!i
.tm
.opcode_modifier
.vecsib
)
6351 /* !i.base_reg && i.index_reg */
6352 if (i
.index_reg
->reg_num
== RegEiz
6353 || i
.index_reg
->reg_num
== RegRiz
)
6354 i
.sib
.index
= NO_INDEX_REGISTER
;
6356 i
.sib
.index
= i
.index_reg
->reg_num
;
6357 i
.sib
.base
= NO_BASE_REGISTER
;
6358 i
.sib
.scale
= i
.log2_scale_factor
;
6359 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6360 /* No Vec_Disp8 if there is no base. */
6361 i
.types
[op
].bitfield
.vec_disp8
= 0;
6362 i
.types
[op
].bitfield
.disp8
= 0;
6363 i
.types
[op
].bitfield
.disp16
= 0;
6364 i
.types
[op
].bitfield
.disp64
= 0;
6365 if (flag_code
!= CODE_64BIT
)
6367 /* Must be 32 bit */
6368 i
.types
[op
].bitfield
.disp32
= 1;
6369 i
.types
[op
].bitfield
.disp32s
= 0;
6373 i
.types
[op
].bitfield
.disp32
= 0;
6374 i
.types
[op
].bitfield
.disp32s
= 1;
6376 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
6380 /* RIP addressing for 64bit mode. */
6381 else if (i
.base_reg
->reg_num
== RegRip
||
6382 i
.base_reg
->reg_num
== RegEip
)
6384 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6385 i
.rm
.regmem
= NO_BASE_REGISTER
;
6386 i
.types
[op
].bitfield
.disp8
= 0;
6387 i
.types
[op
].bitfield
.disp16
= 0;
6388 i
.types
[op
].bitfield
.disp32
= 0;
6389 i
.types
[op
].bitfield
.disp32s
= 1;
6390 i
.types
[op
].bitfield
.disp64
= 0;
6391 i
.types
[op
].bitfield
.vec_disp8
= 0;
6392 i
.flags
[op
] |= Operand_PCrel
;
6393 if (! i
.disp_operands
)
6394 fake_zero_displacement
= 1;
6396 else if (i
.base_reg
->reg_type
.bitfield
.reg16
)
6398 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6399 switch (i
.base_reg
->reg_num
)
6402 if (i
.index_reg
== 0)
6404 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
6405 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
6409 if (i
.index_reg
== 0)
6412 if (operand_type_check (i
.types
[op
], disp
) == 0)
6414 /* fake (%bp) into 0(%bp) */
6415 if (i
.tm
.operand_types
[op
].bitfield
.vec_disp8
)
6416 i
.types
[op
].bitfield
.vec_disp8
= 1;
6418 i
.types
[op
].bitfield
.disp8
= 1;
6419 fake_zero_displacement
= 1;
6422 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
6423 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
6425 default: /* (%si) -> 4 or (%di) -> 5 */
6426 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
6428 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
6430 else /* i.base_reg and 32/64 bit mode */
6432 if (flag_code
== CODE_64BIT
6433 && operand_type_check (i
.types
[op
], disp
))
6435 i386_operand_type temp
;
6436 operand_type_set (&temp
, 0);
6437 temp
.bitfield
.disp8
= i
.types
[op
].bitfield
.disp8
;
6438 temp
.bitfield
.vec_disp8
6439 = i
.types
[op
].bitfield
.vec_disp8
;
6441 if (i
.prefix
[ADDR_PREFIX
] == 0)
6442 i
.types
[op
].bitfield
.disp32s
= 1;
6444 i
.types
[op
].bitfield
.disp32
= 1;
6447 if (!i
.tm
.opcode_modifier
.vecsib
)
6448 i
.rm
.regmem
= i
.base_reg
->reg_num
;
6449 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
6451 i
.sib
.base
= i
.base_reg
->reg_num
;
6452 /* x86-64 ignores REX prefix bit here to avoid decoder
6454 if (!(i
.base_reg
->reg_flags
& RegRex
)
6455 && (i
.base_reg
->reg_num
== EBP_REG_NUM
6456 || i
.base_reg
->reg_num
== ESP_REG_NUM
))
6458 if (i
.base_reg
->reg_num
== 5 && i
.disp_operands
== 0)
6460 fake_zero_displacement
= 1;
6461 if (i
.tm
.operand_types
[op
].bitfield
.vec_disp8
)
6462 i
.types
[op
].bitfield
.vec_disp8
= 1;
6464 i
.types
[op
].bitfield
.disp8
= 1;
6466 i
.sib
.scale
= i
.log2_scale_factor
;
6467 if (i
.index_reg
== 0)
6469 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6470 /* <disp>(%esp) becomes two byte modrm with no index
6471 register. We've already stored the code for esp
6472 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
6473 Any base register besides %esp will not use the
6474 extra modrm byte. */
6475 i
.sib
.index
= NO_INDEX_REGISTER
;
6477 else if (!i
.tm
.opcode_modifier
.vecsib
)
6479 if (i
.index_reg
->reg_num
== RegEiz
6480 || i
.index_reg
->reg_num
== RegRiz
)
6481 i
.sib
.index
= NO_INDEX_REGISTER
;
6483 i
.sib
.index
= i
.index_reg
->reg_num
;
6484 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6485 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
6490 && (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
6491 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
))
6495 if (!fake_zero_displacement
6499 fake_zero_displacement
= 1;
6500 if (i
.disp_encoding
== disp_encoding_8bit
)
6501 i
.types
[op
].bitfield
.disp8
= 1;
6503 i
.types
[op
].bitfield
.disp32
= 1;
6505 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
6509 if (fake_zero_displacement
)
6511 /* Fakes a zero displacement assuming that i.types[op]
6512 holds the correct displacement size. */
6515 gas_assert (i
.op
[op
].disps
== 0);
6516 exp
= &disp_expressions
[i
.disp_operands
++];
6517 i
.op
[op
].disps
= exp
;
6518 exp
->X_op
= O_constant
;
6519 exp
->X_add_number
= 0;
6520 exp
->X_add_symbol
= (symbolS
*) 0;
6521 exp
->X_op_symbol
= (symbolS
*) 0;
6529 if (i
.tm
.opcode_modifier
.vexsources
== XOP2SOURCES
)
6531 if (operand_type_check (i
.types
[0], imm
))
6532 i
.vex
.register_specifier
= NULL
;
6535 /* VEX.vvvv encodes one of the sources when the first
6536 operand is not an immediate. */
6537 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
6538 i
.vex
.register_specifier
= i
.op
[0].regs
;
6540 i
.vex
.register_specifier
= i
.op
[1].regs
;
6543 /* Destination is a XMM register encoded in the ModRM.reg
6545 i
.rm
.reg
= i
.op
[2].regs
->reg_num
;
6546 if ((i
.op
[2].regs
->reg_flags
& RegRex
) != 0)
6549 /* ModRM.rm and VEX.B encodes the other source. */
6550 if (!i
.mem_operands
)
6554 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
6555 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
6557 i
.rm
.regmem
= i
.op
[0].regs
->reg_num
;
6559 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
6563 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXLWP
)
6565 i
.vex
.register_specifier
= i
.op
[2].regs
;
6566 if (!i
.mem_operands
)
6569 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
6570 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
6574 /* Fill in i.rm.reg or i.rm.regmem field with register operand
6575 (if any) based on i.tm.extension_opcode. Again, we must be
6576 careful to make sure that segment/control/debug/test/MMX
6577 registers are coded into the i.rm.reg field. */
6578 else if (i
.reg_operands
)
6581 unsigned int vex_reg
= ~0;
6583 for (op
= 0; op
< i
.operands
; op
++)
6584 if (i
.types
[op
].bitfield
.reg8
6585 || i
.types
[op
].bitfield
.reg16
6586 || i
.types
[op
].bitfield
.reg32
6587 || i
.types
[op
].bitfield
.reg64
6588 || i
.types
[op
].bitfield
.regmmx
6589 || i
.types
[op
].bitfield
.regxmm
6590 || i
.types
[op
].bitfield
.regymm
6591 || i
.types
[op
].bitfield
.regbnd
6592 || i
.types
[op
].bitfield
.regzmm
6593 || i
.types
[op
].bitfield
.regmask
6594 || i
.types
[op
].bitfield
.sreg2
6595 || i
.types
[op
].bitfield
.sreg3
6596 || i
.types
[op
].bitfield
.control
6597 || i
.types
[op
].bitfield
.debug
6598 || i
.types
[op
].bitfield
.test
)
6603 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
6605 /* For instructions with VexNDS, the register-only
6606 source operand is encoded in VEX prefix. */
6607 gas_assert (mem
!= (unsigned int) ~0);
6612 gas_assert (op
< i
.operands
);
6616 /* Check register-only source operand when two source
6617 operands are swapped. */
6618 if (!i
.tm
.operand_types
[op
].bitfield
.baseindex
6619 && i
.tm
.operand_types
[op
+ 1].bitfield
.baseindex
)
6623 gas_assert (mem
== (vex_reg
+ 1)
6624 && op
< i
.operands
);
6629 gas_assert (vex_reg
< i
.operands
);
6633 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXNDD
)
6635 /* For instructions with VexNDD, the register destination
6636 is encoded in VEX prefix. */
6637 if (i
.mem_operands
== 0)
6639 /* There is no memory operand. */
6640 gas_assert ((op
+ 2) == i
.operands
);
6645 /* There are only 2 operands. */
6646 gas_assert (op
< 2 && i
.operands
== 2);
6651 gas_assert (op
< i
.operands
);
6653 if (vex_reg
!= (unsigned int) ~0)
6655 i386_operand_type
*type
= &i
.tm
.operand_types
[vex_reg
];
6657 if (type
->bitfield
.reg32
!= 1
6658 && type
->bitfield
.reg64
!= 1
6659 && !operand_type_equal (type
, ®xmm
)
6660 && !operand_type_equal (type
, ®ymm
)
6661 && !operand_type_equal (type
, ®zmm
)
6662 && !operand_type_equal (type
, ®mask
))
6665 i
.vex
.register_specifier
= i
.op
[vex_reg
].regs
;
6668 /* Don't set OP operand twice. */
6671 /* If there is an extension opcode to put here, the
6672 register number must be put into the regmem field. */
6673 if (i
.tm
.extension_opcode
!= None
)
6675 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
6676 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
6678 if ((i
.op
[op
].regs
->reg_flags
& RegVRex
) != 0)
6683 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
6684 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
6686 if ((i
.op
[op
].regs
->reg_flags
& RegVRex
) != 0)
6691 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
6692 must set it to 3 to indicate this is a register operand
6693 in the regmem field. */
6694 if (!i
.mem_operands
)
6698 /* Fill in i.rm.reg field with extension opcode (if any). */
6699 if (i
.tm
.extension_opcode
!= None
)
6700 i
.rm
.reg
= i
.tm
.extension_opcode
;
6706 output_branch (void)
6712 relax_substateT subtype
;
6716 code16
= flag_code
== CODE_16BIT
? CODE16
: 0;
6717 size
= i
.disp_encoding
== disp_encoding_32bit
? BIG
: SMALL
;
6720 if (i
.prefix
[DATA_PREFIX
] != 0)
6726 /* Pentium4 branch hints. */
6727 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
6728 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
6733 if (i
.prefix
[REX_PREFIX
] != 0)
6739 /* BND prefixed jump. */
6740 if (i
.prefix
[BND_PREFIX
] != 0)
6742 FRAG_APPEND_1_CHAR (i
.prefix
[BND_PREFIX
]);
6746 if (i
.prefixes
!= 0 && !intel_syntax
)
6747 as_warn (_("skipping prefixes on this instruction"));
6749 /* It's always a symbol; End frag & setup for relax.
6750 Make sure there is enough room in this frag for the largest
6751 instruction we may generate in md_convert_frag. This is 2
6752 bytes for the opcode and room for the prefix and largest
6754 frag_grow (prefix
+ 2 + 4);
6755 /* Prefix and 1 opcode byte go in fr_fix. */
6756 p
= frag_more (prefix
+ 1);
6757 if (i
.prefix
[DATA_PREFIX
] != 0)
6758 *p
++ = DATA_PREFIX_OPCODE
;
6759 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
6760 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
6761 *p
++ = i
.prefix
[SEG_PREFIX
];
6762 if (i
.prefix
[REX_PREFIX
] != 0)
6763 *p
++ = i
.prefix
[REX_PREFIX
];
6764 *p
= i
.tm
.base_opcode
;
6766 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
6767 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, size
);
6768 else if (cpu_arch_flags
.bitfield
.cpui386
)
6769 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, size
);
6771 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, size
);
6774 sym
= i
.op
[0].disps
->X_add_symbol
;
6775 off
= i
.op
[0].disps
->X_add_number
;
6777 if (i
.op
[0].disps
->X_op
!= O_constant
6778 && i
.op
[0].disps
->X_op
!= O_symbol
)
6780 /* Handle complex expressions. */
6781 sym
= make_expr_symbol (i
.op
[0].disps
);
6785 /* 1 possible extra opcode + 4 byte displacement go in var part.
6786 Pass reloc in fr_var. */
6787 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
6797 if (i
.tm
.opcode_modifier
.jumpbyte
)
6799 /* This is a loop or jecxz type instruction. */
6801 if (i
.prefix
[ADDR_PREFIX
] != 0)
6803 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
6806 /* Pentium4 branch hints. */
6807 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
6808 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
6810 FRAG_APPEND_1_CHAR (i
.prefix
[SEG_PREFIX
]);
6819 if (flag_code
== CODE_16BIT
)
6822 if (i
.prefix
[DATA_PREFIX
] != 0)
6824 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
6834 if (i
.prefix
[REX_PREFIX
] != 0)
6836 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
6840 /* BND prefixed jump. */
6841 if (i
.prefix
[BND_PREFIX
] != 0)
6843 FRAG_APPEND_1_CHAR (i
.prefix
[BND_PREFIX
]);
6847 if (i
.prefixes
!= 0 && !intel_syntax
)
6848 as_warn (_("skipping prefixes on this instruction"));
6850 p
= frag_more (i
.tm
.opcode_length
+ size
);
6851 switch (i
.tm
.opcode_length
)
6854 *p
++ = i
.tm
.base_opcode
>> 8;
6856 *p
++ = i
.tm
.base_opcode
;
6862 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
6863 i
.op
[0].disps
, 1, reloc (size
, 1, 1, i
.reloc
[0]));
6865 /* All jumps handled here are signed, but don't use a signed limit
6866 check for 32 and 16 bit jumps as we want to allow wrap around at
6867 4G and 64k respectively. */
6869 fixP
->fx_signed
= 1;
6873 output_interseg_jump (void)
6881 if (flag_code
== CODE_16BIT
)
6885 if (i
.prefix
[DATA_PREFIX
] != 0)
6891 if (i
.prefix
[REX_PREFIX
] != 0)
6901 if (i
.prefixes
!= 0 && !intel_syntax
)
6902 as_warn (_("skipping prefixes on this instruction"));
6904 /* 1 opcode; 2 segment; offset */
6905 p
= frag_more (prefix
+ 1 + 2 + size
);
6907 if (i
.prefix
[DATA_PREFIX
] != 0)
6908 *p
++ = DATA_PREFIX_OPCODE
;
6910 if (i
.prefix
[REX_PREFIX
] != 0)
6911 *p
++ = i
.prefix
[REX_PREFIX
];
6913 *p
++ = i
.tm
.base_opcode
;
6914 if (i
.op
[1].imms
->X_op
== O_constant
)
6916 offsetT n
= i
.op
[1].imms
->X_add_number
;
6919 && !fits_in_unsigned_word (n
)
6920 && !fits_in_signed_word (n
))
6922 as_bad (_("16-bit jump out of range"));
6925 md_number_to_chars (p
, n
, size
);
6928 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
6929 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
6930 if (i
.op
[0].imms
->X_op
!= O_constant
)
6931 as_bad (_("can't handle non absolute segment in `%s'"),
6933 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
6939 fragS
*insn_start_frag
;
6940 offsetT insn_start_off
;
6942 /* Tie dwarf2 debug info to the address at the start of the insn.
6943 We can't do this after the insn has been output as the current
6944 frag may have been closed off. eg. by frag_var. */
6945 dwarf2_emit_insn (0);
6947 insn_start_frag
= frag_now
;
6948 insn_start_off
= frag_now_fix ();
6951 if (i
.tm
.opcode_modifier
.jump
)
6953 else if (i
.tm
.opcode_modifier
.jumpbyte
6954 || i
.tm
.opcode_modifier
.jumpdword
)
6956 else if (i
.tm
.opcode_modifier
.jumpintersegment
)
6957 output_interseg_jump ();
6960 /* Output normal instructions here. */
6964 unsigned int prefix
;
6966 /* Some processors fail on LOCK prefix. This options makes
6967 assembler ignore LOCK prefix and serves as a workaround. */
6968 if (omit_lock_prefix
)
6970 if (i
.tm
.base_opcode
== LOCK_PREFIX_OPCODE
)
6972 i
.prefix
[LOCK_PREFIX
] = 0;
6975 /* Since the VEX/EVEX prefix contains the implicit prefix, we
6976 don't need the explicit prefix. */
6977 if (!i
.tm
.opcode_modifier
.vex
&& !i
.tm
.opcode_modifier
.evex
)
6979 switch (i
.tm
.opcode_length
)
6982 if (i
.tm
.base_opcode
& 0xff000000)
6984 prefix
= (i
.tm
.base_opcode
>> 24) & 0xff;
6989 if ((i
.tm
.base_opcode
& 0xff0000) != 0)
6991 prefix
= (i
.tm
.base_opcode
>> 16) & 0xff;
6992 if (i
.tm
.cpu_flags
.bitfield
.cpupadlock
)
6995 if (prefix
!= REPE_PREFIX_OPCODE
6996 || (i
.prefix
[REP_PREFIX
]
6997 != REPE_PREFIX_OPCODE
))
6998 add_prefix (prefix
);
7001 add_prefix (prefix
);
7010 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
7011 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
7012 R_X86_64_GOTTPOFF relocation so that linker can safely
7013 perform IE->LE optimization. */
7014 if (x86_elf_abi
== X86_64_X32_ABI
7016 && i
.reloc
[0] == BFD_RELOC_X86_64_GOTTPOFF
7017 && i
.prefix
[REX_PREFIX
] == 0)
7018 add_prefix (REX_OPCODE
);
7021 /* The prefix bytes. */
7022 for (j
= ARRAY_SIZE (i
.prefix
), q
= i
.prefix
; j
> 0; j
--, q
++)
7024 FRAG_APPEND_1_CHAR (*q
);
7028 for (j
= 0, q
= i
.prefix
; j
< ARRAY_SIZE (i
.prefix
); j
++, q
++)
7033 /* REX byte is encoded in VEX prefix. */
7037 FRAG_APPEND_1_CHAR (*q
);
7040 /* There should be no other prefixes for instructions
7045 /* For EVEX instructions i.vrex should become 0 after
7046 build_evex_prefix. For VEX instructions upper 16 registers
7047 aren't available, so VREX should be 0. */
7050 /* Now the VEX prefix. */
7051 p
= frag_more (i
.vex
.length
);
7052 for (j
= 0; j
< i
.vex
.length
; j
++)
7053 p
[j
] = i
.vex
.bytes
[j
];
7056 /* Now the opcode; be careful about word order here! */
7057 if (i
.tm
.opcode_length
== 1)
7059 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
7063 switch (i
.tm
.opcode_length
)
7067 *p
++ = (i
.tm
.base_opcode
>> 24) & 0xff;
7068 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
7072 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
7082 /* Put out high byte first: can't use md_number_to_chars! */
7083 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
7084 *p
= i
.tm
.base_opcode
& 0xff;
7087 /* Now the modrm byte and sib byte (if present). */
7088 if (i
.tm
.opcode_modifier
.modrm
)
7090 FRAG_APPEND_1_CHAR ((i
.rm
.regmem
<< 0
7093 /* If i.rm.regmem == ESP (4)
7094 && i.rm.mode != (Register mode)
7096 ==> need second modrm byte. */
7097 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
7099 && !(i
.base_reg
&& i
.base_reg
->reg_type
.bitfield
.reg16
))
7100 FRAG_APPEND_1_CHAR ((i
.sib
.base
<< 0
7102 | i
.sib
.scale
<< 6));
7105 if (i
.disp_operands
)
7106 output_disp (insn_start_frag
, insn_start_off
);
7109 output_imm (insn_start_frag
, insn_start_off
);
7115 pi ("" /*line*/, &i
);
7117 #endif /* DEBUG386 */
7120 /* Return the size of the displacement operand N. */
7123 disp_size (unsigned int n
)
7127 /* Vec_Disp8 has to be 8bit. */
7128 if (i
.types
[n
].bitfield
.vec_disp8
)
7130 else if (i
.types
[n
].bitfield
.disp64
)
7132 else if (i
.types
[n
].bitfield
.disp8
)
7134 else if (i
.types
[n
].bitfield
.disp16
)
7139 /* Return the size of the immediate operand N. */
7142 imm_size (unsigned int n
)
7145 if (i
.types
[n
].bitfield
.imm64
)
7147 else if (i
.types
[n
].bitfield
.imm8
|| i
.types
[n
].bitfield
.imm8s
)
7149 else if (i
.types
[n
].bitfield
.imm16
)
7155 output_disp (fragS
*insn_start_frag
, offsetT insn_start_off
)
7160 for (n
= 0; n
< i
.operands
; n
++)
7162 if (i
.types
[n
].bitfield
.vec_disp8
7163 || operand_type_check (i
.types
[n
], disp
))
7165 if (i
.op
[n
].disps
->X_op
== O_constant
)
7167 int size
= disp_size (n
);
7168 offsetT val
= i
.op
[n
].disps
->X_add_number
;
7170 if (i
.types
[n
].bitfield
.vec_disp8
)
7172 val
= offset_in_range (val
, size
);
7173 p
= frag_more (size
);
7174 md_number_to_chars (p
, val
, size
);
7178 enum bfd_reloc_code_real reloc_type
;
7179 int size
= disp_size (n
);
7180 int sign
= i
.types
[n
].bitfield
.disp32s
;
7181 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
7183 /* We can't have 8 bit displacement here. */
7184 gas_assert (!i
.types
[n
].bitfield
.disp8
);
7186 /* The PC relative address is computed relative
7187 to the instruction boundary, so in case immediate
7188 fields follows, we need to adjust the value. */
7189 if (pcrel
&& i
.imm_operands
)
7194 for (n1
= 0; n1
< i
.operands
; n1
++)
7195 if (operand_type_check (i
.types
[n1
], imm
))
7197 /* Only one immediate is allowed for PC
7198 relative address. */
7199 gas_assert (sz
== 0);
7201 i
.op
[n
].disps
->X_add_number
-= sz
;
7203 /* We should find the immediate. */
7204 gas_assert (sz
!= 0);
7207 p
= frag_more (size
);
7208 reloc_type
= reloc (size
, pcrel
, sign
, i
.reloc
[n
]);
7210 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
7211 && (((reloc_type
== BFD_RELOC_32
7212 || reloc_type
== BFD_RELOC_X86_64_32S
7213 || (reloc_type
== BFD_RELOC_64
7215 && (i
.op
[n
].disps
->X_op
== O_symbol
7216 || (i
.op
[n
].disps
->X_op
== O_add
7217 && ((symbol_get_value_expression
7218 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
7220 || reloc_type
== BFD_RELOC_32_PCREL
))
7224 if (insn_start_frag
== frag_now
)
7225 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
7230 add
= insn_start_frag
->fr_fix
- insn_start_off
;
7231 for (fr
= insn_start_frag
->fr_next
;
7232 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
7234 add
+= p
- frag_now
->fr_literal
;
7239 reloc_type
= BFD_RELOC_386_GOTPC
;
7240 i
.op
[n
].imms
->X_add_number
+= add
;
7242 else if (reloc_type
== BFD_RELOC_64
)
7243 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
7245 /* Don't do the adjustment for x86-64, as there
7246 the pcrel addressing is relative to the _next_
7247 insn, and that is taken care of in other code. */
7248 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
7250 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
7251 i
.op
[n
].disps
, pcrel
, reloc_type
);
7258 output_imm (fragS
*insn_start_frag
, offsetT insn_start_off
)
7263 for (n
= 0; n
< i
.operands
; n
++)
7265 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
7266 if (i
.rounding
&& (int) n
== i
.rounding
->operand
)
7269 if (operand_type_check (i
.types
[n
], imm
))
7271 if (i
.op
[n
].imms
->X_op
== O_constant
)
7273 int size
= imm_size (n
);
7276 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
7278 p
= frag_more (size
);
7279 md_number_to_chars (p
, val
, size
);
7283 /* Not absolute_section.
7284 Need a 32-bit fixup (don't support 8bit
7285 non-absolute imms). Try to support other
7287 enum bfd_reloc_code_real reloc_type
;
7288 int size
= imm_size (n
);
7291 if (i
.types
[n
].bitfield
.imm32s
7292 && (i
.suffix
== QWORD_MNEM_SUFFIX
7293 || (!i
.suffix
&& i
.tm
.opcode_modifier
.no_lsuf
)))
7298 p
= frag_more (size
);
7299 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
7301 /* This is tough to explain. We end up with this one if we
7302 * have operands that look like
7303 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
7304 * obtain the absolute address of the GOT, and it is strongly
7305 * preferable from a performance point of view to avoid using
7306 * a runtime relocation for this. The actual sequence of
7307 * instructions often look something like:
7312 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
7314 * The call and pop essentially return the absolute address
7315 * of the label .L66 and store it in %ebx. The linker itself
7316 * will ultimately change the first operand of the addl so
7317 * that %ebx points to the GOT, but to keep things simple, the
7318 * .o file must have this operand set so that it generates not
7319 * the absolute address of .L66, but the absolute address of
7320 * itself. This allows the linker itself simply treat a GOTPC
7321 * relocation as asking for a pcrel offset to the GOT to be
7322 * added in, and the addend of the relocation is stored in the
7323 * operand field for the instruction itself.
7325 * Our job here is to fix the operand so that it would add
7326 * the correct offset so that %ebx would point to itself. The
7327 * thing that is tricky is that .-.L66 will point to the
7328 * beginning of the instruction, so we need to further modify
7329 * the operand so that it will point to itself. There are
7330 * other cases where you have something like:
7332 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
7334 * and here no correction would be required. Internally in
7335 * the assembler we treat operands of this form as not being
7336 * pcrel since the '.' is explicitly mentioned, and I wonder
7337 * whether it would simplify matters to do it this way. Who
7338 * knows. In earlier versions of the PIC patches, the
7339 * pcrel_adjust field was used to store the correction, but
7340 * since the expression is not pcrel, I felt it would be
7341 * confusing to do it this way. */
7343 if ((reloc_type
== BFD_RELOC_32
7344 || reloc_type
== BFD_RELOC_X86_64_32S
7345 || reloc_type
== BFD_RELOC_64
)
7347 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
7348 && (i
.op
[n
].imms
->X_op
== O_symbol
7349 || (i
.op
[n
].imms
->X_op
== O_add
7350 && ((symbol_get_value_expression
7351 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
7356 if (insn_start_frag
== frag_now
)
7357 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
7362 add
= insn_start_frag
->fr_fix
- insn_start_off
;
7363 for (fr
= insn_start_frag
->fr_next
;
7364 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
7366 add
+= p
- frag_now
->fr_literal
;
7370 reloc_type
= BFD_RELOC_386_GOTPC
;
7372 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
7374 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
7375 i
.op
[n
].imms
->X_add_number
+= add
;
7377 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
7378 i
.op
[n
].imms
, 0, reloc_type
);
7384 /* x86_cons_fix_new is called via the expression parsing code when a
7385 reloc is needed. We use this hook to get the correct .got reloc. */
7386 static int cons_sign
= -1;
7389 x86_cons_fix_new (fragS
*frag
, unsigned int off
, unsigned int len
,
7390 expressionS
*exp
, bfd_reloc_code_real_type r
)
7392 r
= reloc (len
, 0, cons_sign
, r
);
7395 if (exp
->X_op
== O_secrel
)
7397 exp
->X_op
= O_symbol
;
7398 r
= BFD_RELOC_32_SECREL
;
7402 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
7405 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
7406 purpose of the `.dc.a' internal pseudo-op. */
7409 x86_address_bytes (void)
7411 if ((stdoutput
->arch_info
->mach
& bfd_mach_x64_32
))
7413 return stdoutput
->arch_info
->bits_per_address
/ 8;
7416 #if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
7418 # define lex_got(reloc, adjust, types) NULL
7420 /* Parse operands of the form
7421 <symbol>@GOTOFF+<nnn>
7422 and similar .plt or .got references.
7424 If we find one, set up the correct relocation in RELOC and copy the
7425 input string, minus the `@GOTOFF' into a malloc'd buffer for
7426 parsing by the calling routine. Return this buffer, and if ADJUST
7427 is non-null set it to the length of the string we removed from the
7428 input line. Otherwise return NULL. */
7430 lex_got (enum bfd_reloc_code_real
*rel
,
7432 i386_operand_type
*types
)
7434 /* Some of the relocations depend on the size of what field is to
7435 be relocated. But in our callers i386_immediate and i386_displacement
7436 we don't yet know the operand size (this will be set by insn
7437 matching). Hence we record the word32 relocation here,
7438 and adjust the reloc according to the real size in reloc(). */
7439 static const struct {
7442 const enum bfd_reloc_code_real rel
[2];
7443 const i386_operand_type types64
;
7445 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7446 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32
,
7448 OPERAND_TYPE_IMM32_64
},
7450 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real
,
7451 BFD_RELOC_X86_64_PLTOFF64
},
7452 OPERAND_TYPE_IMM64
},
7453 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32
,
7454 BFD_RELOC_X86_64_PLT32
},
7455 OPERAND_TYPE_IMM32_32S_DISP32
},
7456 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real
,
7457 BFD_RELOC_X86_64_GOTPLT64
},
7458 OPERAND_TYPE_IMM64_DISP64
},
7459 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF
,
7460 BFD_RELOC_X86_64_GOTOFF64
},
7461 OPERAND_TYPE_IMM64_DISP64
},
7462 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real
,
7463 BFD_RELOC_X86_64_GOTPCREL
},
7464 OPERAND_TYPE_IMM32_32S_DISP32
},
7465 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD
,
7466 BFD_RELOC_X86_64_TLSGD
},
7467 OPERAND_TYPE_IMM32_32S_DISP32
},
7468 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM
,
7469 _dummy_first_bfd_reloc_code_real
},
7470 OPERAND_TYPE_NONE
},
7471 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real
,
7472 BFD_RELOC_X86_64_TLSLD
},
7473 OPERAND_TYPE_IMM32_32S_DISP32
},
7474 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32
,
7475 BFD_RELOC_X86_64_GOTTPOFF
},
7476 OPERAND_TYPE_IMM32_32S_DISP32
},
7477 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32
,
7478 BFD_RELOC_X86_64_TPOFF32
},
7479 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
7480 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE
,
7481 _dummy_first_bfd_reloc_code_real
},
7482 OPERAND_TYPE_NONE
},
7483 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32
,
7484 BFD_RELOC_X86_64_DTPOFF32
},
7485 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
7486 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE
,
7487 _dummy_first_bfd_reloc_code_real
},
7488 OPERAND_TYPE_NONE
},
7489 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE
,
7490 _dummy_first_bfd_reloc_code_real
},
7491 OPERAND_TYPE_NONE
},
7492 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32
,
7493 BFD_RELOC_X86_64_GOT32
},
7494 OPERAND_TYPE_IMM32_32S_64_DISP32
},
7495 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC
,
7496 BFD_RELOC_X86_64_GOTPC32_TLSDESC
},
7497 OPERAND_TYPE_IMM32_32S_DISP32
},
7498 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL
,
7499 BFD_RELOC_X86_64_TLSDESC_CALL
},
7500 OPERAND_TYPE_IMM32_32S_DISP32
},
7505 #if defined (OBJ_MAYBE_ELF)
7510 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
7511 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
7514 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
7516 int len
= gotrel
[j
].len
;
7517 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
7519 if (gotrel
[j
].rel
[object_64bit
] != 0)
7522 char *tmpbuf
, *past_reloc
;
7524 *rel
= gotrel
[j
].rel
[object_64bit
];
7528 if (flag_code
!= CODE_64BIT
)
7530 types
->bitfield
.imm32
= 1;
7531 types
->bitfield
.disp32
= 1;
7534 *types
= gotrel
[j
].types64
;
7537 if (j
!= 0 && GOT_symbol
== NULL
)
7538 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
7540 /* The length of the first part of our input line. */
7541 first
= cp
- input_line_pointer
;
7543 /* The second part goes from after the reloc token until
7544 (and including) an end_of_line char or comma. */
7545 past_reloc
= cp
+ 1 + len
;
7547 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
7549 second
= cp
+ 1 - past_reloc
;
7551 /* Allocate and copy string. The trailing NUL shouldn't
7552 be necessary, but be safe. */
7553 tmpbuf
= (char *) xmalloc (first
+ second
+ 2);
7554 memcpy (tmpbuf
, input_line_pointer
, first
);
7555 if (second
!= 0 && *past_reloc
!= ' ')
7556 /* Replace the relocation token with ' ', so that
7557 errors like foo@GOTOFF1 will be detected. */
7558 tmpbuf
[first
++] = ' ';
7560 /* Increment length by 1 if the relocation token is
7565 memcpy (tmpbuf
+ first
, past_reloc
, second
);
7566 tmpbuf
[first
+ second
] = '\0';
7570 as_bad (_("@%s reloc is not supported with %d-bit output format"),
7571 gotrel
[j
].str
, 1 << (5 + object_64bit
));
7576 /* Might be a symbol version string. Don't as_bad here. */
7585 /* Parse operands of the form
7586 <symbol>@SECREL32+<nnn>
7588 If we find one, set up the correct relocation in RELOC and copy the
7589 input string, minus the `@SECREL32' into a malloc'd buffer for
7590 parsing by the calling routine. Return this buffer, and if ADJUST
7591 is non-null set it to the length of the string we removed from the
7592 input line. Otherwise return NULL.
7594 This function is copied from the ELF version above adjusted for PE targets. */
7597 lex_got (enum bfd_reloc_code_real
*rel ATTRIBUTE_UNUSED
,
7598 int *adjust ATTRIBUTE_UNUSED
,
7599 i386_operand_type
*types
)
7605 const enum bfd_reloc_code_real rel
[2];
7606 const i386_operand_type types64
;
7610 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL
,
7611 BFD_RELOC_32_SECREL
},
7612 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
7618 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
7619 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
7622 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
7624 int len
= gotrel
[j
].len
;
7626 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
7628 if (gotrel
[j
].rel
[object_64bit
] != 0)
7631 char *tmpbuf
, *past_reloc
;
7633 *rel
= gotrel
[j
].rel
[object_64bit
];
7639 if (flag_code
!= CODE_64BIT
)
7641 types
->bitfield
.imm32
= 1;
7642 types
->bitfield
.disp32
= 1;
7645 *types
= gotrel
[j
].types64
;
7648 /* The length of the first part of our input line. */
7649 first
= cp
- input_line_pointer
;
7651 /* The second part goes from after the reloc token until
7652 (and including) an end_of_line char or comma. */
7653 past_reloc
= cp
+ 1 + len
;
7655 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
7657 second
= cp
+ 1 - past_reloc
;
7659 /* Allocate and copy string. The trailing NUL shouldn't
7660 be necessary, but be safe. */
7661 tmpbuf
= (char *) xmalloc (first
+ second
+ 2);
7662 memcpy (tmpbuf
, input_line_pointer
, first
);
7663 if (second
!= 0 && *past_reloc
!= ' ')
7664 /* Replace the relocation token with ' ', so that
7665 errors like foo@SECLREL321 will be detected. */
7666 tmpbuf
[first
++] = ' ';
7667 memcpy (tmpbuf
+ first
, past_reloc
, second
);
7668 tmpbuf
[first
+ second
] = '\0';
7672 as_bad (_("@%s reloc is not supported with %d-bit output format"),
7673 gotrel
[j
].str
, 1 << (5 + object_64bit
));
7678 /* Might be a symbol version string. Don't as_bad here. */
7684 bfd_reloc_code_real_type
7685 x86_cons (expressionS
*exp
, int size
)
7687 bfd_reloc_code_real_type got_reloc
= NO_RELOC
;
7689 intel_syntax
= -intel_syntax
;
7692 if (size
== 4 || (object_64bit
&& size
== 8))
7694 /* Handle @GOTOFF and the like in an expression. */
7696 char *gotfree_input_line
;
7699 save
= input_line_pointer
;
7700 gotfree_input_line
= lex_got (&got_reloc
, &adjust
, NULL
);
7701 if (gotfree_input_line
)
7702 input_line_pointer
= gotfree_input_line
;
7706 if (gotfree_input_line
)
7708 /* expression () has merrily parsed up to the end of line,
7709 or a comma - in the wrong buffer. Transfer how far
7710 input_line_pointer has moved to the right buffer. */
7711 input_line_pointer
= (save
7712 + (input_line_pointer
- gotfree_input_line
)
7714 free (gotfree_input_line
);
7715 if (exp
->X_op
== O_constant
7716 || exp
->X_op
== O_absent
7717 || exp
->X_op
== O_illegal
7718 || exp
->X_op
== O_register
7719 || exp
->X_op
== O_big
)
7721 char c
= *input_line_pointer
;
7722 *input_line_pointer
= 0;
7723 as_bad (_("missing or invalid expression `%s'"), save
);
7724 *input_line_pointer
= c
;
7731 intel_syntax
= -intel_syntax
;
7734 i386_intel_simplify (exp
);
7740 signed_cons (int size
)
7742 if (flag_code
== CODE_64BIT
)
7750 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
7757 if (exp
.X_op
== O_symbol
)
7758 exp
.X_op
= O_secrel
;
7760 emit_expr (&exp
, 4);
7762 while (*input_line_pointer
++ == ',');
7764 input_line_pointer
--;
7765 demand_empty_rest_of_line ();
7769 /* Handle Vector operations. */
7772 check_VecOperations (char *op_string
, char *op_end
)
7774 const reg_entry
*mask
;
7779 && (op_end
== NULL
|| op_string
< op_end
))
7782 if (*op_string
== '{')
7786 /* Check broadcasts. */
7787 if (strncmp (op_string
, "1to", 3) == 0)
7792 goto duplicated_vec_op
;
7795 if (*op_string
== '8')
7796 bcst_type
= BROADCAST_1TO8
;
7797 else if (*op_string
== '4')
7798 bcst_type
= BROADCAST_1TO4
;
7799 else if (*op_string
== '2')
7800 bcst_type
= BROADCAST_1TO2
;
7801 else if (*op_string
== '1'
7802 && *(op_string
+1) == '6')
7804 bcst_type
= BROADCAST_1TO16
;
7809 as_bad (_("Unsupported broadcast: `%s'"), saved
);
7814 broadcast_op
.type
= bcst_type
;
7815 broadcast_op
.operand
= this_operand
;
7816 i
.broadcast
= &broadcast_op
;
7818 /* Check masking operation. */
7819 else if ((mask
= parse_register (op_string
, &end_op
)) != NULL
)
7821 /* k0 can't be used for write mask. */
7822 if (mask
->reg_num
== 0)
7824 as_bad (_("`%s' can't be used for write mask"),
7831 mask_op
.mask
= mask
;
7832 mask_op
.zeroing
= 0;
7833 mask_op
.operand
= this_operand
;
7839 goto duplicated_vec_op
;
7841 i
.mask
->mask
= mask
;
7843 /* Only "{z}" is allowed here. No need to check
7844 zeroing mask explicitly. */
7845 if (i
.mask
->operand
!= this_operand
)
7847 as_bad (_("invalid write mask `%s'"), saved
);
7854 /* Check zeroing-flag for masking operation. */
7855 else if (*op_string
== 'z')
7859 mask_op
.mask
= NULL
;
7860 mask_op
.zeroing
= 1;
7861 mask_op
.operand
= this_operand
;
7866 if (i
.mask
->zeroing
)
7869 as_bad (_("duplicated `%s'"), saved
);
7873 i
.mask
->zeroing
= 1;
7875 /* Only "{%k}" is allowed here. No need to check mask
7876 register explicitly. */
7877 if (i
.mask
->operand
!= this_operand
)
7879 as_bad (_("invalid zeroing-masking `%s'"),
7888 goto unknown_vec_op
;
7890 if (*op_string
!= '}')
7892 as_bad (_("missing `}' in `%s'"), saved
);
7899 /* We don't know this one. */
7900 as_bad (_("unknown vector operation: `%s'"), saved
);
7908 i386_immediate (char *imm_start
)
7910 char *save_input_line_pointer
;
7911 char *gotfree_input_line
;
7914 i386_operand_type types
;
7916 operand_type_set (&types
, ~0);
7918 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
7920 as_bad (_("at most %d immediate operands are allowed"),
7921 MAX_IMMEDIATE_OPERANDS
);
7925 exp
= &im_expressions
[i
.imm_operands
++];
7926 i
.op
[this_operand
].imms
= exp
;
7928 if (is_space_char (*imm_start
))
7931 save_input_line_pointer
= input_line_pointer
;
7932 input_line_pointer
= imm_start
;
7934 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
7935 if (gotfree_input_line
)
7936 input_line_pointer
= gotfree_input_line
;
7938 exp_seg
= expression (exp
);
7942 /* Handle vector operations. */
7943 if (*input_line_pointer
== '{')
7945 input_line_pointer
= check_VecOperations (input_line_pointer
,
7947 if (input_line_pointer
== NULL
)
7951 if (*input_line_pointer
)
7952 as_bad (_("junk `%s' after expression"), input_line_pointer
);
7954 input_line_pointer
= save_input_line_pointer
;
7955 if (gotfree_input_line
)
7957 free (gotfree_input_line
);
7959 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
7960 exp
->X_op
= O_illegal
;
7963 return i386_finalize_immediate (exp_seg
, exp
, types
, imm_start
);
7967 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
7968 i386_operand_type types
, const char *imm_start
)
7970 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_illegal
|| exp
->X_op
== O_big
)
7973 as_bad (_("missing or invalid immediate expression `%s'"),
7977 else if (exp
->X_op
== O_constant
)
7979 /* Size it properly later. */
7980 i
.types
[this_operand
].bitfield
.imm64
= 1;
7981 /* If not 64bit, sign extend val. */
7982 if (flag_code
!= CODE_64BIT
7983 && (exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
7985 = (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
7987 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
7988 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
7989 && exp_seg
!= absolute_section
7990 && exp_seg
!= text_section
7991 && exp_seg
!= data_section
7992 && exp_seg
!= bss_section
7993 && exp_seg
!= undefined_section
7994 && !bfd_is_com_section (exp_seg
))
7996 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
8000 else if (!intel_syntax
&& exp_seg
== reg_section
)
8003 as_bad (_("illegal immediate register operand %s"), imm_start
);
8008 /* This is an address. The size of the address will be
8009 determined later, depending on destination register,
8010 suffix, or the default for the section. */
8011 i
.types
[this_operand
].bitfield
.imm8
= 1;
8012 i
.types
[this_operand
].bitfield
.imm16
= 1;
8013 i
.types
[this_operand
].bitfield
.imm32
= 1;
8014 i
.types
[this_operand
].bitfield
.imm32s
= 1;
8015 i
.types
[this_operand
].bitfield
.imm64
= 1;
8016 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
8024 i386_scale (char *scale
)
8027 char *save
= input_line_pointer
;
8029 input_line_pointer
= scale
;
8030 val
= get_absolute_expression ();
8035 i
.log2_scale_factor
= 0;
8038 i
.log2_scale_factor
= 1;
8041 i
.log2_scale_factor
= 2;
8044 i
.log2_scale_factor
= 3;
8048 char sep
= *input_line_pointer
;
8050 *input_line_pointer
= '\0';
8051 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
8053 *input_line_pointer
= sep
;
8054 input_line_pointer
= save
;
8058 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
8060 as_warn (_("scale factor of %d without an index register"),
8061 1 << i
.log2_scale_factor
);
8062 i
.log2_scale_factor
= 0;
8064 scale
= input_line_pointer
;
8065 input_line_pointer
= save
;
8070 i386_displacement (char *disp_start
, char *disp_end
)
8074 char *save_input_line_pointer
;
8075 char *gotfree_input_line
;
8077 i386_operand_type bigdisp
, types
= anydisp
;
8080 if (i
.disp_operands
== MAX_MEMORY_OPERANDS
)
8082 as_bad (_("at most %d displacement operands are allowed"),
8083 MAX_MEMORY_OPERANDS
);
8087 operand_type_set (&bigdisp
, 0);
8088 if ((i
.types
[this_operand
].bitfield
.jumpabsolute
)
8089 || (!current_templates
->start
->opcode_modifier
.jump
8090 && !current_templates
->start
->opcode_modifier
.jumpdword
))
8092 bigdisp
.bitfield
.disp32
= 1;
8093 override
= (i
.prefix
[ADDR_PREFIX
] != 0);
8094 if (flag_code
== CODE_64BIT
)
8098 bigdisp
.bitfield
.disp32s
= 1;
8099 bigdisp
.bitfield
.disp64
= 1;
8102 else if ((flag_code
== CODE_16BIT
) ^ override
)
8104 bigdisp
.bitfield
.disp32
= 0;
8105 bigdisp
.bitfield
.disp16
= 1;
8110 /* For PC-relative branches, the width of the displacement
8111 is dependent upon data size, not address size. */
8112 override
= (i
.prefix
[DATA_PREFIX
] != 0);
8113 if (flag_code
== CODE_64BIT
)
8115 if (override
|| i
.suffix
== WORD_MNEM_SUFFIX
)
8116 bigdisp
.bitfield
.disp16
= 1;
8119 bigdisp
.bitfield
.disp32
= 1;
8120 bigdisp
.bitfield
.disp32s
= 1;
8126 override
= (i
.suffix
== (flag_code
!= CODE_16BIT
8128 : LONG_MNEM_SUFFIX
));
8129 bigdisp
.bitfield
.disp32
= 1;
8130 if ((flag_code
== CODE_16BIT
) ^ override
)
8132 bigdisp
.bitfield
.disp32
= 0;
8133 bigdisp
.bitfield
.disp16
= 1;
8137 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
8140 exp
= &disp_expressions
[i
.disp_operands
];
8141 i
.op
[this_operand
].disps
= exp
;
8143 save_input_line_pointer
= input_line_pointer
;
8144 input_line_pointer
= disp_start
;
8145 END_STRING_AND_SAVE (disp_end
);
8147 #ifndef GCC_ASM_O_HACK
8148 #define GCC_ASM_O_HACK 0
8151 END_STRING_AND_SAVE (disp_end
+ 1);
8152 if (i
.types
[this_operand
].bitfield
.baseIndex
8153 && displacement_string_end
[-1] == '+')
8155 /* This hack is to avoid a warning when using the "o"
8156 constraint within gcc asm statements.
8159 #define _set_tssldt_desc(n,addr,limit,type) \
8160 __asm__ __volatile__ ( \
8162 "movw %w1,2+%0\n\t" \
8164 "movb %b1,4+%0\n\t" \
8165 "movb %4,5+%0\n\t" \
8166 "movb $0,6+%0\n\t" \
8167 "movb %h1,7+%0\n\t" \
8169 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
8171 This works great except that the output assembler ends
8172 up looking a bit weird if it turns out that there is
8173 no offset. You end up producing code that looks like:
8186 So here we provide the missing zero. */
8188 *displacement_string_end
= '0';
8191 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
8192 if (gotfree_input_line
)
8193 input_line_pointer
= gotfree_input_line
;
8195 exp_seg
= expression (exp
);
8198 if (*input_line_pointer
)
8199 as_bad (_("junk `%s' after expression"), input_line_pointer
);
8201 RESTORE_END_STRING (disp_end
+ 1);
8203 input_line_pointer
= save_input_line_pointer
;
8204 if (gotfree_input_line
)
8206 free (gotfree_input_line
);
8208 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
8209 exp
->X_op
= O_illegal
;
8212 ret
= i386_finalize_displacement (exp_seg
, exp
, types
, disp_start
);
8214 RESTORE_END_STRING (disp_end
);
8220 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
8221 i386_operand_type types
, const char *disp_start
)
8223 i386_operand_type bigdisp
;
8226 /* We do this to make sure that the section symbol is in
8227 the symbol table. We will ultimately change the relocation
8228 to be relative to the beginning of the section. */
8229 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
8230 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
8231 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
8233 if (exp
->X_op
!= O_symbol
)
8236 if (S_IS_LOCAL (exp
->X_add_symbol
)
8237 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
8238 && S_GET_SEGMENT (exp
->X_add_symbol
) != expr_section
)
8239 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
8240 exp
->X_op
= O_subtract
;
8241 exp
->X_op_symbol
= GOT_symbol
;
8242 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
8243 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
8244 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
8245 i
.reloc
[this_operand
] = BFD_RELOC_64
;
8247 i
.reloc
[this_operand
] = BFD_RELOC_32
;
8250 else if (exp
->X_op
== O_absent
8251 || exp
->X_op
== O_illegal
8252 || exp
->X_op
== O_big
)
8255 as_bad (_("missing or invalid displacement expression `%s'"),
8260 else if (flag_code
== CODE_64BIT
8261 && !i
.prefix
[ADDR_PREFIX
]
8262 && exp
->X_op
== O_constant
)
8264 /* Since displacement is signed extended to 64bit, don't allow
8265 disp32 and turn off disp32s if they are out of range. */
8266 i
.types
[this_operand
].bitfield
.disp32
= 0;
8267 if (!fits_in_signed_long (exp
->X_add_number
))
8269 i
.types
[this_operand
].bitfield
.disp32s
= 0;
8270 if (i
.types
[this_operand
].bitfield
.baseindex
)
8272 as_bad (_("0x%lx out range of signed 32bit displacement"),
8273 (long) exp
->X_add_number
);
8279 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8280 else if (exp
->X_op
!= O_constant
8281 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
8282 && exp_seg
!= absolute_section
8283 && exp_seg
!= text_section
8284 && exp_seg
!= data_section
8285 && exp_seg
!= bss_section
8286 && exp_seg
!= undefined_section
8287 && !bfd_is_com_section (exp_seg
))
8289 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
8294 /* Check if this is a displacement only operand. */
8295 bigdisp
= i
.types
[this_operand
];
8296 bigdisp
.bitfield
.disp8
= 0;
8297 bigdisp
.bitfield
.disp16
= 0;
8298 bigdisp
.bitfield
.disp32
= 0;
8299 bigdisp
.bitfield
.disp32s
= 0;
8300 bigdisp
.bitfield
.disp64
= 0;
8301 if (operand_type_all_zero (&bigdisp
))
8302 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
8308 /* Make sure the memory operand we've been dealt is valid.
8309 Return 1 on success, 0 on a failure. */
8312 i386_index_check (const char *operand_string
)
8314 const char *kind
= "base/index";
8315 enum flag_code addr_mode
;
8317 if (i
.prefix
[ADDR_PREFIX
])
8318 addr_mode
= flag_code
== CODE_32BIT
? CODE_16BIT
: CODE_32BIT
;
8321 addr_mode
= flag_code
;
8323 #if INFER_ADDR_PREFIX
8324 if (i
.mem_operands
== 0)
8326 /* Infer address prefix from the first memory operand. */
8327 const reg_entry
*addr_reg
= i
.base_reg
;
8329 if (addr_reg
== NULL
)
8330 addr_reg
= i
.index_reg
;
8334 if (addr_reg
->reg_num
== RegEip
8335 || addr_reg
->reg_num
== RegEiz
8336 || addr_reg
->reg_type
.bitfield
.reg32
)
8337 addr_mode
= CODE_32BIT
;
8338 else if (flag_code
!= CODE_64BIT
8339 && addr_reg
->reg_type
.bitfield
.reg16
)
8340 addr_mode
= CODE_16BIT
;
8342 if (addr_mode
!= flag_code
)
8344 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
8346 /* Change the size of any displacement too. At most one
8347 of Disp16 or Disp32 is set.
8348 FIXME. There doesn't seem to be any real need for
8349 separate Disp16 and Disp32 flags. The same goes for
8350 Imm16 and Imm32. Removing them would probably clean
8351 up the code quite a lot. */
8352 if (flag_code
!= CODE_64BIT
8353 && (i
.types
[this_operand
].bitfield
.disp16
8354 || i
.types
[this_operand
].bitfield
.disp32
))
8355 i
.types
[this_operand
]
8356 = operand_type_xor (i
.types
[this_operand
], disp16_32
);
8363 if (current_templates
->start
->opcode_modifier
.isstring
8364 && !current_templates
->start
->opcode_modifier
.immext
8365 && (current_templates
->end
[-1].opcode_modifier
.isstring
8368 /* Memory operands of string insns are special in that they only allow
8369 a single register (rDI, rSI, or rBX) as their memory address. */
8370 const reg_entry
*expected_reg
;
8371 static const char *di_si
[][2] =
8377 static const char *bx
[] = { "ebx", "bx", "rbx" };
8379 kind
= "string address";
8381 if (current_templates
->start
->opcode_modifier
.w
)
8383 i386_operand_type type
= current_templates
->end
[-1].operand_types
[0];
8385 if (!type
.bitfield
.baseindex
8386 || ((!i
.mem_operands
!= !intel_syntax
)
8387 && current_templates
->end
[-1].operand_types
[1]
8388 .bitfield
.baseindex
))
8389 type
= current_templates
->end
[-1].operand_types
[1];
8390 expected_reg
= hash_find (reg_hash
,
8391 di_si
[addr_mode
][type
.bitfield
.esseg
]);
8395 expected_reg
= hash_find (reg_hash
, bx
[addr_mode
]);
8397 if (i
.base_reg
!= expected_reg
8399 || operand_type_check (i
.types
[this_operand
], disp
))
8401 /* The second memory operand must have the same size as
8405 && !((addr_mode
== CODE_64BIT
8406 && i
.base_reg
->reg_type
.bitfield
.reg64
)
8407 || (addr_mode
== CODE_32BIT
8408 ? i
.base_reg
->reg_type
.bitfield
.reg32
8409 : i
.base_reg
->reg_type
.bitfield
.reg16
)))
8412 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
8414 intel_syntax
? '[' : '(',
8416 expected_reg
->reg_name
,
8417 intel_syntax
? ']' : ')');
8424 as_bad (_("`%s' is not a valid %s expression"),
8425 operand_string
, kind
);
8430 if (addr_mode
!= CODE_16BIT
)
8432 /* 32-bit/64-bit checks. */
8434 && (addr_mode
== CODE_64BIT
8435 ? !i
.base_reg
->reg_type
.bitfield
.reg64
8436 : !i
.base_reg
->reg_type
.bitfield
.reg32
)
8438 || (i
.base_reg
->reg_num
8439 != (addr_mode
== CODE_64BIT
? RegRip
: RegEip
))))
8441 && !i
.index_reg
->reg_type
.bitfield
.regxmm
8442 && !i
.index_reg
->reg_type
.bitfield
.regymm
8443 && !i
.index_reg
->reg_type
.bitfield
.regzmm
8444 && ((addr_mode
== CODE_64BIT
8445 ? !(i
.index_reg
->reg_type
.bitfield
.reg64
8446 || i
.index_reg
->reg_num
== RegRiz
)
8447 : !(i
.index_reg
->reg_type
.bitfield
.reg32
8448 || i
.index_reg
->reg_num
== RegEiz
))
8449 || !i
.index_reg
->reg_type
.bitfield
.baseindex
)))
8454 /* 16-bit checks. */
8456 && (!i
.base_reg
->reg_type
.bitfield
.reg16
8457 || !i
.base_reg
->reg_type
.bitfield
.baseindex
))
8459 && (!i
.index_reg
->reg_type
.bitfield
.reg16
8460 || !i
.index_reg
->reg_type
.bitfield
.baseindex
8462 && i
.base_reg
->reg_num
< 6
8463 && i
.index_reg
->reg_num
>= 6
8464 && i
.log2_scale_factor
== 0))))
8471 /* Handle vector immediates. */
8474 RC_SAE_immediate (const char *imm_start
)
8476 unsigned int match_found
, j
;
8477 const char *pstr
= imm_start
;
8485 for (j
= 0; j
< ARRAY_SIZE (RC_NamesTable
); j
++)
8487 if (!strncmp (pstr
, RC_NamesTable
[j
].name
, RC_NamesTable
[j
].len
))
8491 rc_op
.type
= RC_NamesTable
[j
].type
;
8492 rc_op
.operand
= this_operand
;
8493 i
.rounding
= &rc_op
;
8497 as_bad (_("duplicated `%s'"), imm_start
);
8500 pstr
+= RC_NamesTable
[j
].len
;
8510 as_bad (_("Missing '}': '%s'"), imm_start
);
8513 /* RC/SAE immediate string should contain nothing more. */;
8516 as_bad (_("Junk after '}': '%s'"), imm_start
);
8520 exp
= &im_expressions
[i
.imm_operands
++];
8521 i
.op
[this_operand
].imms
= exp
;
8523 exp
->X_op
= O_constant
;
8524 exp
->X_add_number
= 0;
8525 exp
->X_add_symbol
= (symbolS
*) 0;
8526 exp
->X_op_symbol
= (symbolS
*) 0;
8528 i
.types
[this_operand
].bitfield
.imm8
= 1;
8532 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
8536 i386_att_operand (char *operand_string
)
8540 char *op_string
= operand_string
;
8542 if (is_space_char (*op_string
))
8545 /* We check for an absolute prefix (differentiating,
8546 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
8547 if (*op_string
== ABSOLUTE_PREFIX
)
8550 if (is_space_char (*op_string
))
8552 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
8555 /* Check if operand is a register. */
8556 if ((r
= parse_register (op_string
, &end_op
)) != NULL
)
8558 i386_operand_type temp
;
8560 /* Check for a segment override by searching for ':' after a
8561 segment register. */
8563 if (is_space_char (*op_string
))
8565 if (*op_string
== ':'
8566 && (r
->reg_type
.bitfield
.sreg2
8567 || r
->reg_type
.bitfield
.sreg3
))
8572 i
.seg
[i
.mem_operands
] = &es
;
8575 i
.seg
[i
.mem_operands
] = &cs
;
8578 i
.seg
[i
.mem_operands
] = &ss
;
8581 i
.seg
[i
.mem_operands
] = &ds
;
8584 i
.seg
[i
.mem_operands
] = &fs
;
8587 i
.seg
[i
.mem_operands
] = &gs
;
8591 /* Skip the ':' and whitespace. */
8593 if (is_space_char (*op_string
))
8596 if (!is_digit_char (*op_string
)
8597 && !is_identifier_char (*op_string
)
8598 && *op_string
!= '('
8599 && *op_string
!= ABSOLUTE_PREFIX
)
8601 as_bad (_("bad memory operand `%s'"), op_string
);
8604 /* Handle case of %es:*foo. */
8605 if (*op_string
== ABSOLUTE_PREFIX
)
8608 if (is_space_char (*op_string
))
8610 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
8612 goto do_memory_reference
;
8615 /* Handle vector operations. */
8616 if (*op_string
== '{')
8618 op_string
= check_VecOperations (op_string
, NULL
);
8619 if (op_string
== NULL
)
8625 as_bad (_("junk `%s' after register"), op_string
);
8629 temp
.bitfield
.baseindex
= 0;
8630 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
8632 i
.types
[this_operand
].bitfield
.unspecified
= 0;
8633 i
.op
[this_operand
].regs
= r
;
8636 else if (*op_string
== REGISTER_PREFIX
)
8638 as_bad (_("bad register name `%s'"), op_string
);
8641 else if (*op_string
== IMMEDIATE_PREFIX
)
8644 if (i
.types
[this_operand
].bitfield
.jumpabsolute
)
8646 as_bad (_("immediate operand illegal with absolute jump"));
8649 if (!i386_immediate (op_string
))
8652 else if (RC_SAE_immediate (operand_string
))
8654 /* If it is a RC or SAE immediate, do nothing. */
8657 else if (is_digit_char (*op_string
)
8658 || is_identifier_char (*op_string
)
8659 || *op_string
== '(')
8661 /* This is a memory reference of some sort. */
8664 /* Start and end of displacement string expression (if found). */
8665 char *displacement_string_start
;
8666 char *displacement_string_end
;
8669 do_memory_reference
:
8670 if ((i
.mem_operands
== 1
8671 && !current_templates
->start
->opcode_modifier
.isstring
)
8672 || i
.mem_operands
== 2)
8674 as_bad (_("too many memory references for `%s'"),
8675 current_templates
->start
->name
);
8679 /* Check for base index form. We detect the base index form by
8680 looking for an ')' at the end of the operand, searching
8681 for the '(' matching it, and finding a REGISTER_PREFIX or ','
8683 base_string
= op_string
+ strlen (op_string
);
8685 /* Handle vector operations. */
8686 vop_start
= strchr (op_string
, '{');
8687 if (vop_start
&& vop_start
< base_string
)
8689 if (check_VecOperations (vop_start
, base_string
) == NULL
)
8691 base_string
= vop_start
;
8695 if (is_space_char (*base_string
))
8698 /* If we only have a displacement, set-up for it to be parsed later. */
8699 displacement_string_start
= op_string
;
8700 displacement_string_end
= base_string
+ 1;
8702 if (*base_string
== ')')
8705 unsigned int parens_balanced
= 1;
8706 /* We've already checked that the number of left & right ()'s are
8707 equal, so this loop will not be infinite. */
8711 if (*base_string
== ')')
8713 if (*base_string
== '(')
8716 while (parens_balanced
);
8718 temp_string
= base_string
;
8720 /* Skip past '(' and whitespace. */
8722 if (is_space_char (*base_string
))
8725 if (*base_string
== ','
8726 || ((i
.base_reg
= parse_register (base_string
, &end_op
))
8729 displacement_string_end
= temp_string
;
8731 i
.types
[this_operand
].bitfield
.baseindex
= 1;
8735 base_string
= end_op
;
8736 if (is_space_char (*base_string
))
8740 /* There may be an index reg or scale factor here. */
8741 if (*base_string
== ',')
8744 if (is_space_char (*base_string
))
8747 if ((i
.index_reg
= parse_register (base_string
, &end_op
))
8750 base_string
= end_op
;
8751 if (is_space_char (*base_string
))
8753 if (*base_string
== ',')
8756 if (is_space_char (*base_string
))
8759 else if (*base_string
!= ')')
8761 as_bad (_("expecting `,' or `)' "
8762 "after index register in `%s'"),
8767 else if (*base_string
== REGISTER_PREFIX
)
8769 end_op
= strchr (base_string
, ',');
8772 as_bad (_("bad register name `%s'"), base_string
);
8776 /* Check for scale factor. */
8777 if (*base_string
!= ')')
8779 char *end_scale
= i386_scale (base_string
);
8784 base_string
= end_scale
;
8785 if (is_space_char (*base_string
))
8787 if (*base_string
!= ')')
8789 as_bad (_("expecting `)' "
8790 "after scale factor in `%s'"),
8795 else if (!i
.index_reg
)
8797 as_bad (_("expecting index register or scale factor "
8798 "after `,'; got '%c'"),
8803 else if (*base_string
!= ')')
8805 as_bad (_("expecting `,' or `)' "
8806 "after base register in `%s'"),
8811 else if (*base_string
== REGISTER_PREFIX
)
8813 end_op
= strchr (base_string
, ',');
8816 as_bad (_("bad register name `%s'"), base_string
);
8821 /* If there's an expression beginning the operand, parse it,
8822 assuming displacement_string_start and
8823 displacement_string_end are meaningful. */
8824 if (displacement_string_start
!= displacement_string_end
)
8826 if (!i386_displacement (displacement_string_start
,
8827 displacement_string_end
))
8831 /* Special case for (%dx) while doing input/output op. */
8833 && operand_type_equal (&i
.base_reg
->reg_type
,
8834 ®16_inoutportreg
)
8836 && i
.log2_scale_factor
== 0
8837 && i
.seg
[i
.mem_operands
] == 0
8838 && !operand_type_check (i
.types
[this_operand
], disp
))
8840 i
.types
[this_operand
] = inoutportreg
;
8844 if (i386_index_check (operand_string
) == 0)
8846 i
.types
[this_operand
].bitfield
.mem
= 1;
8851 /* It's not a memory operand; argh! */
8852 as_bad (_("invalid char %s beginning operand %d `%s'"),
8853 output_invalid (*op_string
),
8858 return 1; /* Normal return. */
8861 /* Calculate the maximum variable size (i.e., excluding fr_fix)
8862 that an rs_machine_dependent frag may reach. */
8865 i386_frag_max_var (fragS
*frag
)
8867 /* The only relaxable frags are for jumps.
8868 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
8869 gas_assert (frag
->fr_type
== rs_machine_dependent
);
8870 return TYPE_FROM_RELAX_STATE (frag
->fr_subtype
) == UNCOND_JUMP
? 4 : 5;
8873 /* md_estimate_size_before_relax()
8875 Called just before relax() for rs_machine_dependent frags. The x86
8876 assembler uses these frags to handle variable size jump
8879 Any symbol that is now undefined will not become defined.
8880 Return the correct fr_subtype in the frag.
8881 Return the initial "guess for variable size of frag" to caller.
8882 The guess is actually the growth beyond the fixed part. Whatever
8883 we do to grow the fixed or variable part contributes to our
8887 md_estimate_size_before_relax (fragS
*fragP
, segT segment
)
8889 /* We've already got fragP->fr_subtype right; all we have to do is
8890 check for un-relaxable symbols. On an ELF system, we can't relax
8891 an externally visible symbol, because it may be overridden by a
8893 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
8894 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8896 && (S_IS_EXTERNAL (fragP
->fr_symbol
)
8897 || S_IS_WEAK (fragP
->fr_symbol
)
8898 || ((symbol_get_bfdsym (fragP
->fr_symbol
)->flags
8899 & BSF_GNU_INDIRECT_FUNCTION
))))
8901 #if defined (OBJ_COFF) && defined (TE_PE)
8902 || (OUTPUT_FLAVOR
== bfd_target_coff_flavour
8903 && S_IS_WEAK (fragP
->fr_symbol
))
8907 /* Symbol is undefined in this segment, or we need to keep a
8908 reloc so that weak symbols can be overridden. */
8909 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
8910 enum bfd_reloc_code_real reloc_type
;
8911 unsigned char *opcode
;
8914 if (fragP
->fr_var
!= NO_RELOC
)
8915 reloc_type
= (enum bfd_reloc_code_real
) fragP
->fr_var
;
8917 reloc_type
= BFD_RELOC_16_PCREL
;
8919 reloc_type
= BFD_RELOC_32_PCREL
;
8921 old_fr_fix
= fragP
->fr_fix
;
8922 opcode
= (unsigned char *) fragP
->fr_opcode
;
8924 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
8927 /* Make jmp (0xeb) a (d)word displacement jump. */
8929 fragP
->fr_fix
+= size
;
8930 fix_new (fragP
, old_fr_fix
, size
,
8932 fragP
->fr_offset
, 1,
8938 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
8940 /* Negate the condition, and branch past an
8941 unconditional jump. */
8944 /* Insert an unconditional jump. */
8946 /* We added two extra opcode bytes, and have a two byte
8948 fragP
->fr_fix
+= 2 + 2;
8949 fix_new (fragP
, old_fr_fix
+ 2, 2,
8951 fragP
->fr_offset
, 1,
8958 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
8963 fixP
= fix_new (fragP
, old_fr_fix
, 1,
8965 fragP
->fr_offset
, 1,
8967 fixP
->fx_signed
= 1;
8971 /* This changes the byte-displacement jump 0x7N
8972 to the (d)word-displacement jump 0x0f,0x8N. */
8973 opcode
[1] = opcode
[0] + 0x10;
8974 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
8975 /* We've added an opcode byte. */
8976 fragP
->fr_fix
+= 1 + size
;
8977 fix_new (fragP
, old_fr_fix
+ 1, size
,
8979 fragP
->fr_offset
, 1,
8984 BAD_CASE (fragP
->fr_subtype
);
8988 return fragP
->fr_fix
- old_fr_fix
;
8991 /* Guess size depending on current relax state. Initially the relax
8992 state will correspond to a short jump and we return 1, because
8993 the variable part of the frag (the branch offset) is one byte
8994 long. However, we can relax a section more than once and in that
8995 case we must either set fr_subtype back to the unrelaxed state,
8996 or return the value for the appropriate branch. */
8997 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
9000 /* Called after relax() is finished.
9002 In: Address of frag.
9003 fr_type == rs_machine_dependent.
9004 fr_subtype is what the address relaxed to.
9006 Out: Any fixSs and constants are set up.
9007 Caller will turn frag into a ".space 0". */
9010 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec ATTRIBUTE_UNUSED
,
9013 unsigned char *opcode
;
9014 unsigned char *where_to_put_displacement
= NULL
;
9015 offsetT target_address
;
9016 offsetT opcode_address
;
9017 unsigned int extension
= 0;
9018 offsetT displacement_from_opcode_start
;
9020 opcode
= (unsigned char *) fragP
->fr_opcode
;
9022 /* Address we want to reach in file space. */
9023 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
9025 /* Address opcode resides at in file space. */
9026 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
9028 /* Displacement from opcode start to fill into instruction. */
9029 displacement_from_opcode_start
= target_address
- opcode_address
;
9031 if ((fragP
->fr_subtype
& BIG
) == 0)
9033 /* Don't have to change opcode. */
9034 extension
= 1; /* 1 opcode + 1 displacement */
9035 where_to_put_displacement
= &opcode
[1];
9039 if (no_cond_jump_promotion
9040 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
9041 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
9042 _("long jump required"));
9044 switch (fragP
->fr_subtype
)
9046 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
9047 extension
= 4; /* 1 opcode + 4 displacement */
9049 where_to_put_displacement
= &opcode
[1];
9052 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
9053 extension
= 2; /* 1 opcode + 2 displacement */
9055 where_to_put_displacement
= &opcode
[1];
9058 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
9059 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
9060 extension
= 5; /* 2 opcode + 4 displacement */
9061 opcode
[1] = opcode
[0] + 0x10;
9062 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
9063 where_to_put_displacement
= &opcode
[2];
9066 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
9067 extension
= 3; /* 2 opcode + 2 displacement */
9068 opcode
[1] = opcode
[0] + 0x10;
9069 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
9070 where_to_put_displacement
= &opcode
[2];
9073 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
9078 where_to_put_displacement
= &opcode
[3];
9082 BAD_CASE (fragP
->fr_subtype
);
9087 /* If size if less then four we are sure that the operand fits,
9088 but if it's 4, then it could be that the displacement is larger
9090 if (DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
) == 4
9092 && ((addressT
) (displacement_from_opcode_start
- extension
9093 + ((addressT
) 1 << 31))
9094 > (((addressT
) 2 << 31) - 1)))
9096 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
9097 _("jump target out of range"));
9098 /* Make us emit 0. */
9099 displacement_from_opcode_start
= extension
;
9101 /* Now put displacement after opcode. */
9102 md_number_to_chars ((char *) where_to_put_displacement
,
9103 (valueT
) (displacement_from_opcode_start
- extension
),
9104 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
9105 fragP
->fr_fix
+= extension
;
9108 /* Apply a fixup (fixP) to segment data, once it has been determined
9109 by our caller that we have all the info we need to fix it up.
9111 Parameter valP is the pointer to the value of the bits.
9113 On the 386, immediates, displacements, and data pointers are all in
9114 the same (little-endian) format, so we don't need to care about which
9118 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
9120 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
9121 valueT value
= *valP
;
9123 #if !defined (TE_Mach)
9126 switch (fixP
->fx_r_type
)
9132 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
9135 case BFD_RELOC_X86_64_32S
:
9136 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
9139 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
9142 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
9147 if (fixP
->fx_addsy
!= NULL
9148 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
9149 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
9150 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
9151 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
9152 && !use_rela_relocations
)
9154 /* This is a hack. There should be a better way to handle this.
9155 This covers for the fact that bfd_install_relocation will
9156 subtract the current location (for partial_inplace, PC relative
9157 relocations); see more below. */
9161 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
9164 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
9166 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9169 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
9172 || (symbol_section_p (fixP
->fx_addsy
)
9173 && sym_seg
!= absolute_section
))
9174 && !generic_force_reloc (fixP
))
9176 /* Yes, we add the values in twice. This is because
9177 bfd_install_relocation subtracts them out again. I think
9178 bfd_install_relocation is broken, but I don't dare change
9180 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
9184 #if defined (OBJ_COFF) && defined (TE_PE)
9185 /* For some reason, the PE format does not store a
9186 section address offset for a PC relative symbol. */
9187 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
9188 || S_IS_WEAK (fixP
->fx_addsy
))
9189 value
+= md_pcrel_from (fixP
);
9192 #if defined (OBJ_COFF) && defined (TE_PE)
9193 if (fixP
->fx_addsy
!= NULL
9194 && S_IS_WEAK (fixP
->fx_addsy
)
9195 /* PR 16858: Do not modify weak function references. */
9196 && ! fixP
->fx_pcrel
)
9198 #if !defined (TE_PEP)
9199 /* For x86 PE weak function symbols are neither PC-relative
9200 nor do they set S_IS_FUNCTION. So the only reliable way
9201 to detect them is to check the flags of their containing
9203 if (S_GET_SEGMENT (fixP
->fx_addsy
) != NULL
9204 && S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_CODE
)
9208 value
-= S_GET_VALUE (fixP
->fx_addsy
);
9212 /* Fix a few things - the dynamic linker expects certain values here,
9213 and we must not disappoint it. */
9214 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9215 if (IS_ELF
&& fixP
->fx_addsy
)
9216 switch (fixP
->fx_r_type
)
9218 case BFD_RELOC_386_PLT32
:
9219 case BFD_RELOC_X86_64_PLT32
:
9220 /* Make the jump instruction point to the address of the operand. At
9221 runtime we merely add the offset to the actual PLT entry. */
9225 case BFD_RELOC_386_TLS_GD
:
9226 case BFD_RELOC_386_TLS_LDM
:
9227 case BFD_RELOC_386_TLS_IE_32
:
9228 case BFD_RELOC_386_TLS_IE
:
9229 case BFD_RELOC_386_TLS_GOTIE
:
9230 case BFD_RELOC_386_TLS_GOTDESC
:
9231 case BFD_RELOC_X86_64_TLSGD
:
9232 case BFD_RELOC_X86_64_TLSLD
:
9233 case BFD_RELOC_X86_64_GOTTPOFF
:
9234 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
9235 value
= 0; /* Fully resolved at runtime. No addend. */
9237 case BFD_RELOC_386_TLS_LE
:
9238 case BFD_RELOC_386_TLS_LDO_32
:
9239 case BFD_RELOC_386_TLS_LE_32
:
9240 case BFD_RELOC_X86_64_DTPOFF32
:
9241 case BFD_RELOC_X86_64_DTPOFF64
:
9242 case BFD_RELOC_X86_64_TPOFF32
:
9243 case BFD_RELOC_X86_64_TPOFF64
:
9244 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
9247 case BFD_RELOC_386_TLS_DESC_CALL
:
9248 case BFD_RELOC_X86_64_TLSDESC_CALL
:
9249 value
= 0; /* Fully resolved at runtime. No addend. */
9250 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
9254 case BFD_RELOC_386_GOT32
:
9255 case BFD_RELOC_X86_64_GOT32
:
9256 value
= 0; /* Fully resolved at runtime. No addend. */
9259 case BFD_RELOC_VTABLE_INHERIT
:
9260 case BFD_RELOC_VTABLE_ENTRY
:
9267 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
9269 #endif /* !defined (TE_Mach) */
9271 /* Are we finished with this relocation now? */
9272 if (fixP
->fx_addsy
== NULL
)
9274 #if defined (OBJ_COFF) && defined (TE_PE)
9275 else if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
9278 /* Remember value for tc_gen_reloc. */
9279 fixP
->fx_addnumber
= value
;
9280 /* Clear out the frag for now. */
9284 else if (use_rela_relocations
)
9286 fixP
->fx_no_overflow
= 1;
9287 /* Remember value for tc_gen_reloc. */
9288 fixP
->fx_addnumber
= value
;
9292 md_number_to_chars (p
, value
, fixP
->fx_size
);
9296 md_atof (int type
, char *litP
, int *sizeP
)
9298 /* This outputs the LITTLENUMs in REVERSE order;
9299 in accord with the bigendian 386. */
9300 return ieee_md_atof (type
, litP
, sizeP
, FALSE
);
9303 static char output_invalid_buf
[sizeof (unsigned char) * 2 + 6];
9306 output_invalid (int c
)
9309 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
9312 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
9313 "(0x%x)", (unsigned char) c
);
9314 return output_invalid_buf
;
9317 /* REG_STRING starts *before* REGISTER_PREFIX. */
9319 static const reg_entry
*
9320 parse_real_register (char *reg_string
, char **end_op
)
9322 char *s
= reg_string
;
9324 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
9327 /* Skip possible REGISTER_PREFIX and possible whitespace. */
9328 if (*s
== REGISTER_PREFIX
)
9331 if (is_space_char (*s
))
9335 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
9337 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
9338 return (const reg_entry
*) NULL
;
9342 /* For naked regs, make sure that we are not dealing with an identifier.
9343 This prevents confusing an identifier like `eax_var' with register
9345 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
9346 return (const reg_entry
*) NULL
;
9350 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
9352 /* Handle floating point regs, allowing spaces in the (i) part. */
9353 if (r
== i386_regtab
/* %st is first entry of table */)
9355 if (is_space_char (*s
))
9360 if (is_space_char (*s
))
9362 if (*s
>= '0' && *s
<= '7')
9366 if (is_space_char (*s
))
9371 r
= (const reg_entry
*) hash_find (reg_hash
, "st(0)");
9376 /* We have "%st(" then garbage. */
9377 return (const reg_entry
*) NULL
;
9381 if (r
== NULL
|| allow_pseudo_reg
)
9384 if (operand_type_all_zero (&r
->reg_type
))
9385 return (const reg_entry
*) NULL
;
9387 if ((r
->reg_type
.bitfield
.reg32
9388 || r
->reg_type
.bitfield
.sreg3
9389 || r
->reg_type
.bitfield
.control
9390 || r
->reg_type
.bitfield
.debug
9391 || r
->reg_type
.bitfield
.test
)
9392 && !cpu_arch_flags
.bitfield
.cpui386
)
9393 return (const reg_entry
*) NULL
;
9395 if (r
->reg_type
.bitfield
.floatreg
9396 && !cpu_arch_flags
.bitfield
.cpu8087
9397 && !cpu_arch_flags
.bitfield
.cpu287
9398 && !cpu_arch_flags
.bitfield
.cpu387
)
9399 return (const reg_entry
*) NULL
;
9401 if (r
->reg_type
.bitfield
.regmmx
&& !cpu_arch_flags
.bitfield
.cpummx
)
9402 return (const reg_entry
*) NULL
;
9404 if (r
->reg_type
.bitfield
.regxmm
&& !cpu_arch_flags
.bitfield
.cpusse
)
9405 return (const reg_entry
*) NULL
;
9407 if (r
->reg_type
.bitfield
.regymm
&& !cpu_arch_flags
.bitfield
.cpuavx
)
9408 return (const reg_entry
*) NULL
;
9410 if ((r
->reg_type
.bitfield
.regzmm
|| r
->reg_type
.bitfield
.regmask
)
9411 && !cpu_arch_flags
.bitfield
.cpuavx512f
)
9412 return (const reg_entry
*) NULL
;
9414 /* Don't allow fake index register unless allow_index_reg isn't 0. */
9415 if (!allow_index_reg
9416 && (r
->reg_num
== RegEiz
|| r
->reg_num
== RegRiz
))
9417 return (const reg_entry
*) NULL
;
9419 /* Upper 16 vector register is only available with VREX in 64bit
9421 if ((r
->reg_flags
& RegVRex
))
9423 if (!cpu_arch_flags
.bitfield
.cpuvrex
9424 || flag_code
!= CODE_64BIT
)
9425 return (const reg_entry
*) NULL
;
9430 if (((r
->reg_flags
& (RegRex64
| RegRex
))
9431 || r
->reg_type
.bitfield
.reg64
)
9432 && (!cpu_arch_flags
.bitfield
.cpulm
9433 || !operand_type_equal (&r
->reg_type
, &control
))
9434 && flag_code
!= CODE_64BIT
)
9435 return (const reg_entry
*) NULL
;
9437 if (r
->reg_type
.bitfield
.sreg3
&& r
->reg_num
== RegFlat
&& !intel_syntax
)
9438 return (const reg_entry
*) NULL
;
9443 /* REG_STRING starts *before* REGISTER_PREFIX. */
9445 static const reg_entry
*
9446 parse_register (char *reg_string
, char **end_op
)
9450 if (*reg_string
== REGISTER_PREFIX
|| allow_naked_reg
)
9451 r
= parse_real_register (reg_string
, end_op
);
9456 char *save
= input_line_pointer
;
9460 input_line_pointer
= reg_string
;
9461 c
= get_symbol_end ();
9462 symbolP
= symbol_find (reg_string
);
9463 if (symbolP
&& S_GET_SEGMENT (symbolP
) == reg_section
)
9465 const expressionS
*e
= symbol_get_value_expression (symbolP
);
9467 know (e
->X_op
== O_register
);
9468 know (e
->X_add_number
>= 0
9469 && (valueT
) e
->X_add_number
< i386_regtab_size
);
9470 r
= i386_regtab
+ e
->X_add_number
;
9471 if ((r
->reg_flags
& RegVRex
))
9473 *end_op
= input_line_pointer
;
9475 *input_line_pointer
= c
;
9476 input_line_pointer
= save
;
9482 i386_parse_name (char *name
, expressionS
*e
, char *nextcharP
)
9485 char *end
= input_line_pointer
;
9488 r
= parse_register (name
, &input_line_pointer
);
9489 if (r
&& end
<= input_line_pointer
)
9491 *nextcharP
= *input_line_pointer
;
9492 *input_line_pointer
= 0;
9493 e
->X_op
= O_register
;
9494 e
->X_add_number
= r
- i386_regtab
;
9497 input_line_pointer
= end
;
9499 return intel_syntax
? i386_intel_parse_name (name
, e
) : 0;
9503 md_operand (expressionS
*e
)
9508 switch (*input_line_pointer
)
9510 case REGISTER_PREFIX
:
9511 r
= parse_real_register (input_line_pointer
, &end
);
9514 e
->X_op
= O_register
;
9515 e
->X_add_number
= r
- i386_regtab
;
9516 input_line_pointer
= end
;
9521 gas_assert (intel_syntax
);
9522 end
= input_line_pointer
++;
9524 if (*input_line_pointer
== ']')
9526 ++input_line_pointer
;
9527 e
->X_op_symbol
= make_expr_symbol (e
);
9528 e
->X_add_symbol
= NULL
;
9529 e
->X_add_number
= 0;
9535 input_line_pointer
= end
;
9542 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9543 const char *md_shortopts
= "kVQ:sqn";
9545 const char *md_shortopts
= "qn";
9548 #define OPTION_32 (OPTION_MD_BASE + 0)
9549 #define OPTION_64 (OPTION_MD_BASE + 1)
9550 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
9551 #define OPTION_MARCH (OPTION_MD_BASE + 3)
9552 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
9553 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
9554 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
9555 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
9556 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
9557 #define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
9558 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
9559 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
9560 #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
9561 #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
9562 #define OPTION_X32 (OPTION_MD_BASE + 14)
9563 #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
9564 #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
9565 #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
9566 #define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
9567 #define OPTION_OMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
9568 #define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
9570 struct option md_longopts
[] =
9572 {"32", no_argument
, NULL
, OPTION_32
},
9573 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
9574 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
9575 {"64", no_argument
, NULL
, OPTION_64
},
9577 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9578 {"x32", no_argument
, NULL
, OPTION_X32
},
9580 {"divide", no_argument
, NULL
, OPTION_DIVIDE
},
9581 {"march", required_argument
, NULL
, OPTION_MARCH
},
9582 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
9583 {"mmnemonic", required_argument
, NULL
, OPTION_MMNEMONIC
},
9584 {"msyntax", required_argument
, NULL
, OPTION_MSYNTAX
},
9585 {"mindex-reg", no_argument
, NULL
, OPTION_MINDEX_REG
},
9586 {"mnaked-reg", no_argument
, NULL
, OPTION_MNAKED_REG
},
9587 {"mold-gcc", no_argument
, NULL
, OPTION_MOLD_GCC
},
9588 {"msse2avx", no_argument
, NULL
, OPTION_MSSE2AVX
},
9589 {"msse-check", required_argument
, NULL
, OPTION_MSSE_CHECK
},
9590 {"moperand-check", required_argument
, NULL
, OPTION_MOPERAND_CHECK
},
9591 {"mavxscalar", required_argument
, NULL
, OPTION_MAVXSCALAR
},
9592 {"madd-bnd-prefix", no_argument
, NULL
, OPTION_MADD_BND_PREFIX
},
9593 {"mevexlig", required_argument
, NULL
, OPTION_MEVEXLIG
},
9594 {"mevexwig", required_argument
, NULL
, OPTION_MEVEXWIG
},
9595 # if defined (TE_PE) || defined (TE_PEP)
9596 {"mbig-obj", no_argument
, NULL
, OPTION_MBIG_OBJ
},
9598 {"momit-lock-prefix", required_argument
, NULL
, OPTION_OMIT_LOCK_PREFIX
},
9599 {"mevexrcig", required_argument
, NULL
, OPTION_MEVEXRCIG
},
9600 {NULL
, no_argument
, NULL
, 0}
9602 size_t md_longopts_size
= sizeof (md_longopts
);
9605 md_parse_option (int c
, char *arg
)
9613 optimize_align_code
= 0;
9620 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9621 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
9622 should be emitted or not. FIXME: Not implemented. */
9626 /* -V: SVR4 argument to print version ID. */
9628 print_version_id ();
9631 /* -k: Ignore for FreeBSD compatibility. */
9636 /* -s: On i386 Solaris, this tells the native assembler to use
9637 .stab instead of .stab.excl. We always use .stab anyhow. */
9640 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
9641 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
9644 const char **list
, **l
;
9646 list
= bfd_target_list ();
9647 for (l
= list
; *l
!= NULL
; l
++)
9648 if (CONST_STRNEQ (*l
, "elf64-x86-64")
9649 || strcmp (*l
, "coff-x86-64") == 0
9650 || strcmp (*l
, "pe-x86-64") == 0
9651 || strcmp (*l
, "pei-x86-64") == 0
9652 || strcmp (*l
, "mach-o-x86-64") == 0)
9654 default_arch
= "x86_64";
9658 as_fatal (_("no compiled in support for x86_64"));
9664 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9668 const char **list
, **l
;
9670 list
= bfd_target_list ();
9671 for (l
= list
; *l
!= NULL
; l
++)
9672 if (CONST_STRNEQ (*l
, "elf32-x86-64"))
9674 default_arch
= "x86_64:32";
9678 as_fatal (_("no compiled in support for 32bit x86_64"));
9682 as_fatal (_("32bit x86_64 is only supported for ELF"));
9687 default_arch
= "i386";
9691 #ifdef SVR4_COMMENT_CHARS
9696 n
= (char *) xmalloc (strlen (i386_comment_chars
) + 1);
9698 for (s
= i386_comment_chars
; *s
!= '\0'; s
++)
9702 i386_comment_chars
= n
;
9708 arch
= xstrdup (arg
);
9712 as_fatal (_("invalid -march= option: `%s'"), arg
);
9713 next
= strchr (arch
, '+');
9716 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
9718 if (strcmp (arch
, cpu_arch
[j
].name
) == 0)
9721 if (! cpu_arch
[j
].flags
.bitfield
.cpui386
)
9724 cpu_arch_name
= cpu_arch
[j
].name
;
9725 cpu_sub_arch_name
= NULL
;
9726 cpu_arch_flags
= cpu_arch
[j
].flags
;
9727 cpu_arch_isa
= cpu_arch
[j
].type
;
9728 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
9729 if (!cpu_arch_tune_set
)
9731 cpu_arch_tune
= cpu_arch_isa
;
9732 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
9736 else if (*cpu_arch
[j
].name
== '.'
9737 && strcmp (arch
, cpu_arch
[j
].name
+ 1) == 0)
9739 /* ISA entension. */
9740 i386_cpu_flags flags
;
9742 if (!cpu_arch
[j
].negated
)
9743 flags
= cpu_flags_or (cpu_arch_flags
,
9746 flags
= cpu_flags_and_not (cpu_arch_flags
,
9748 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
9750 if (cpu_sub_arch_name
)
9752 char *name
= cpu_sub_arch_name
;
9753 cpu_sub_arch_name
= concat (name
,
9755 (const char *) NULL
);
9759 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
9760 cpu_arch_flags
= flags
;
9761 cpu_arch_isa_flags
= flags
;
9767 if (j
>= ARRAY_SIZE (cpu_arch
))
9768 as_fatal (_("invalid -march= option: `%s'"), arg
);
9772 while (next
!= NULL
);
9777 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
9778 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
9780 if (strcmp (arg
, cpu_arch
[j
].name
) == 0)
9782 cpu_arch_tune_set
= 1;
9783 cpu_arch_tune
= cpu_arch
[j
].type
;
9784 cpu_arch_tune_flags
= cpu_arch
[j
].flags
;
9788 if (j
>= ARRAY_SIZE (cpu_arch
))
9789 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
9792 case OPTION_MMNEMONIC
:
9793 if (strcasecmp (arg
, "att") == 0)
9795 else if (strcasecmp (arg
, "intel") == 0)
9798 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg
);
9801 case OPTION_MSYNTAX
:
9802 if (strcasecmp (arg
, "att") == 0)
9804 else if (strcasecmp (arg
, "intel") == 0)
9807 as_fatal (_("invalid -msyntax= option: `%s'"), arg
);
9810 case OPTION_MINDEX_REG
:
9811 allow_index_reg
= 1;
9814 case OPTION_MNAKED_REG
:
9815 allow_naked_reg
= 1;
9818 case OPTION_MOLD_GCC
:
9822 case OPTION_MSSE2AVX
:
9826 case OPTION_MSSE_CHECK
:
9827 if (strcasecmp (arg
, "error") == 0)
9828 sse_check
= check_error
;
9829 else if (strcasecmp (arg
, "warning") == 0)
9830 sse_check
= check_warning
;
9831 else if (strcasecmp (arg
, "none") == 0)
9832 sse_check
= check_none
;
9834 as_fatal (_("invalid -msse-check= option: `%s'"), arg
);
9837 case OPTION_MOPERAND_CHECK
:
9838 if (strcasecmp (arg
, "error") == 0)
9839 operand_check
= check_error
;
9840 else if (strcasecmp (arg
, "warning") == 0)
9841 operand_check
= check_warning
;
9842 else if (strcasecmp (arg
, "none") == 0)
9843 operand_check
= check_none
;
9845 as_fatal (_("invalid -moperand-check= option: `%s'"), arg
);
9848 case OPTION_MAVXSCALAR
:
9849 if (strcasecmp (arg
, "128") == 0)
9851 else if (strcasecmp (arg
, "256") == 0)
9854 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg
);
9857 case OPTION_MADD_BND_PREFIX
:
9861 case OPTION_MEVEXLIG
:
9862 if (strcmp (arg
, "128") == 0)
9864 else if (strcmp (arg
, "256") == 0)
9866 else if (strcmp (arg
, "512") == 0)
9869 as_fatal (_("invalid -mevexlig= option: `%s'"), arg
);
9872 case OPTION_MEVEXRCIG
:
9873 if (strcmp (arg
, "rne") == 0)
9875 else if (strcmp (arg
, "rd") == 0)
9877 else if (strcmp (arg
, "ru") == 0)
9879 else if (strcmp (arg
, "rz") == 0)
9882 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg
);
9885 case OPTION_MEVEXWIG
:
9886 if (strcmp (arg
, "0") == 0)
9888 else if (strcmp (arg
, "1") == 0)
9891 as_fatal (_("invalid -mevexwig= option: `%s'"), arg
);
9894 # if defined (TE_PE) || defined (TE_PEP)
9895 case OPTION_MBIG_OBJ
:
9900 case OPTION_OMIT_LOCK_PREFIX
:
9901 if (strcasecmp (arg
, "yes") == 0)
9902 omit_lock_prefix
= 1;
9903 else if (strcasecmp (arg
, "no") == 0)
9904 omit_lock_prefix
= 0;
9906 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg
);
9915 #define MESSAGE_TEMPLATE \
9919 show_arch (FILE *stream
, int ext
, int check
)
9921 static char message
[] = MESSAGE_TEMPLATE
;
9922 char *start
= message
+ 27;
9924 int size
= sizeof (MESSAGE_TEMPLATE
);
9931 left
= size
- (start
- message
);
9932 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
9934 /* Should it be skipped? */
9935 if (cpu_arch
[j
].skip
)
9938 name
= cpu_arch
[j
].name
;
9939 len
= cpu_arch
[j
].len
;
9942 /* It is an extension. Skip if we aren't asked to show it. */
9953 /* It is an processor. Skip if we show only extension. */
9956 else if (check
&& ! cpu_arch
[j
].flags
.bitfield
.cpui386
)
9958 /* It is an impossible processor - skip. */
9962 /* Reserve 2 spaces for ", " or ",\0" */
9965 /* Check if there is any room. */
9973 p
= mempcpy (p
, name
, len
);
9977 /* Output the current message now and start a new one. */
9980 fprintf (stream
, "%s\n", message
);
9982 left
= size
- (start
- message
) - len
- 2;
9984 gas_assert (left
>= 0);
9986 p
= mempcpy (p
, name
, len
);
9991 fprintf (stream
, "%s\n", message
);
9995 md_show_usage (FILE *stream
)
9997 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9998 fprintf (stream
, _("\
10000 -V print assembler version number\n\
10003 fprintf (stream
, _("\
10004 -n Do not optimize code alignment\n\
10005 -q quieten some warnings\n"));
10006 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10007 fprintf (stream
, _("\
10010 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10011 || defined (TE_PE) || defined (TE_PEP))
10012 fprintf (stream
, _("\
10013 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
10015 #ifdef SVR4_COMMENT_CHARS
10016 fprintf (stream
, _("\
10017 --divide do not treat `/' as a comment character\n"));
10019 fprintf (stream
, _("\
10020 --divide ignored\n"));
10022 fprintf (stream
, _("\
10023 -march=CPU[,+EXTENSION...]\n\
10024 generate code for CPU and EXTENSION, CPU is one of:\n"));
10025 show_arch (stream
, 0, 1);
10026 fprintf (stream
, _("\
10027 EXTENSION is combination of:\n"));
10028 show_arch (stream
, 1, 0);
10029 fprintf (stream
, _("\
10030 -mtune=CPU optimize for CPU, CPU is one of:\n"));
10031 show_arch (stream
, 0, 0);
10032 fprintf (stream
, _("\
10033 -msse2avx encode SSE instructions with VEX prefix\n"));
10034 fprintf (stream
, _("\
10035 -msse-check=[none|error|warning]\n\
10036 check SSE instructions\n"));
10037 fprintf (stream
, _("\
10038 -moperand-check=[none|error|warning]\n\
10039 check operand combinations for validity\n"));
10040 fprintf (stream
, _("\
10041 -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n\
10043 fprintf (stream
, _("\
10044 -mevexlig=[128|256|512] encode scalar EVEX instructions with specific vector\n\
10046 fprintf (stream
, _("\
10047 -mevexwig=[0|1] encode EVEX instructions with specific EVEX.W value\n\
10048 for EVEX.W bit ignored instructions\n"));
10049 fprintf (stream
, _("\
10050 -mevexrcig=[rne|rd|ru|rz]\n\
10051 encode EVEX instructions with specific EVEX.RC value\n\
10052 for SAE-only ignored instructions\n"));
10053 fprintf (stream
, _("\
10054 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
10055 fprintf (stream
, _("\
10056 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
10057 fprintf (stream
, _("\
10058 -mindex-reg support pseudo index registers\n"));
10059 fprintf (stream
, _("\
10060 -mnaked-reg don't require `%%' prefix for registers\n"));
10061 fprintf (stream
, _("\
10062 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
10063 fprintf (stream
, _("\
10064 -madd-bnd-prefix add BND prefix for all valid branches\n"));
10065 # if defined (TE_PE) || defined (TE_PEP)
10066 fprintf (stream
, _("\
10067 -mbig-obj generate big object files\n"));
10069 fprintf (stream
, _("\
10070 -momit-lock-prefix=[no|yes]\n\
10071 strip all lock prefixes\n"));
10074 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
10075 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10076 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
10078 /* Pick the target format to use. */
10081 i386_target_format (void)
10083 if (!strncmp (default_arch
, "x86_64", 6))
10085 update_code_flag (CODE_64BIT
, 1);
10086 if (default_arch
[6] == '\0')
10087 x86_elf_abi
= X86_64_ABI
;
10089 x86_elf_abi
= X86_64_X32_ABI
;
10091 else if (!strcmp (default_arch
, "i386"))
10092 update_code_flag (CODE_32BIT
, 1);
10094 as_fatal (_("unknown architecture"));
10096 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
10097 cpu_arch_isa_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
10098 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
10099 cpu_arch_tune_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
10101 switch (OUTPUT_FLAVOR
)
10103 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
10104 case bfd_target_aout_flavour
:
10105 return AOUT_TARGET_FORMAT
;
10107 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
10108 # if defined (TE_PE) || defined (TE_PEP)
10109 case bfd_target_coff_flavour
:
10110 if (flag_code
== CODE_64BIT
)
10111 return use_big_obj
? "pe-bigobj-x86-64" : "pe-x86-64";
10114 # elif defined (TE_GO32)
10115 case bfd_target_coff_flavour
:
10116 return "coff-go32";
10118 case bfd_target_coff_flavour
:
10119 return "coff-i386";
10122 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
10123 case bfd_target_elf_flavour
:
10125 const char *format
;
10127 switch (x86_elf_abi
)
10130 format
= ELF_TARGET_FORMAT
;
10133 use_rela_relocations
= 1;
10135 format
= ELF_TARGET_FORMAT64
;
10137 case X86_64_X32_ABI
:
10138 use_rela_relocations
= 1;
10140 disallow_64bit_reloc
= 1;
10141 format
= ELF_TARGET_FORMAT32
;
10144 if (cpu_arch_isa
== PROCESSOR_L1OM
)
10146 if (x86_elf_abi
!= X86_64_ABI
)
10147 as_fatal (_("Intel L1OM is 64bit only"));
10148 return ELF_TARGET_L1OM_FORMAT
;
10150 if (cpu_arch_isa
== PROCESSOR_K1OM
)
10152 if (x86_elf_abi
!= X86_64_ABI
)
10153 as_fatal (_("Intel K1OM is 64bit only"));
10154 return ELF_TARGET_K1OM_FORMAT
;
10160 #if defined (OBJ_MACH_O)
10161 case bfd_target_mach_o_flavour
:
10162 if (flag_code
== CODE_64BIT
)
10164 use_rela_relocations
= 1;
10166 return "mach-o-x86-64";
10169 return "mach-o-i386";
10177 #endif /* OBJ_MAYBE_ more than one */
10179 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
10181 i386_elf_emit_arch_note (void)
10183 if (IS_ELF
&& cpu_arch_name
!= NULL
)
10186 asection
*seg
= now_seg
;
10187 subsegT subseg
= now_subseg
;
10188 Elf_Internal_Note i_note
;
10189 Elf_External_Note e_note
;
10190 asection
*note_secp
;
10193 /* Create the .note section. */
10194 note_secp
= subseg_new (".note", 0);
10195 bfd_set_section_flags (stdoutput
,
10197 SEC_HAS_CONTENTS
| SEC_READONLY
);
10199 /* Process the arch string. */
10200 len
= strlen (cpu_arch_name
);
10202 i_note
.namesz
= len
+ 1;
10204 i_note
.type
= NT_ARCH
;
10205 p
= frag_more (sizeof (e_note
.namesz
));
10206 md_number_to_chars (p
, (valueT
) i_note
.namesz
, sizeof (e_note
.namesz
));
10207 p
= frag_more (sizeof (e_note
.descsz
));
10208 md_number_to_chars (p
, (valueT
) i_note
.descsz
, sizeof (e_note
.descsz
));
10209 p
= frag_more (sizeof (e_note
.type
));
10210 md_number_to_chars (p
, (valueT
) i_note
.type
, sizeof (e_note
.type
));
10211 p
= frag_more (len
+ 1);
10212 strcpy (p
, cpu_arch_name
);
10214 frag_align (2, 0, 0);
10216 subseg_set (seg
, subseg
);
10222 md_undefined_symbol (char *name
)
10224 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
10225 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
10226 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
10227 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
10231 if (symbol_find (name
))
10232 as_bad (_("GOT already in symbol table"));
10233 GOT_symbol
= symbol_new (name
, undefined_section
,
10234 (valueT
) 0, &zero_address_frag
);
10241 /* Round up a section size to the appropriate boundary. */
10244 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
10246 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
10247 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
10249 /* For a.out, force the section size to be aligned. If we don't do
10250 this, BFD will align it for us, but it will not write out the
10251 final bytes of the section. This may be a bug in BFD, but it is
10252 easier to fix it here since that is how the other a.out targets
10256 align
= bfd_get_section_alignment (stdoutput
, segment
);
10257 size
= ((size
+ (1 << align
) - 1) & ((valueT
) -1 << align
));
10264 /* On the i386, PC-relative offsets are relative to the start of the
10265 next instruction. That is, the address of the offset, plus its
10266 size, since the offset is always the last part of the insn. */
10269 md_pcrel_from (fixS
*fixP
)
10271 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
10277 s_bss (int ignore ATTRIBUTE_UNUSED
)
10281 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10283 obj_elf_section_change_hook ();
10285 temp
= get_absolute_expression ();
10286 subseg_set (bss_section
, (subsegT
) temp
);
10287 demand_empty_rest_of_line ();
10293 i386_validate_fix (fixS
*fixp
)
10295 if (fixp
->fx_subsy
&& fixp
->fx_subsy
== GOT_symbol
)
10297 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
10301 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
10306 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
10308 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
10310 fixp
->fx_subsy
= 0;
10315 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
10318 bfd_reloc_code_real_type code
;
10320 switch (fixp
->fx_r_type
)
10322 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10323 case BFD_RELOC_SIZE32
:
10324 case BFD_RELOC_SIZE64
:
10325 if (S_IS_DEFINED (fixp
->fx_addsy
)
10326 && !S_IS_EXTERNAL (fixp
->fx_addsy
))
10328 /* Resolve size relocation against local symbol to size of
10329 the symbol plus addend. */
10330 valueT value
= S_GET_SIZE (fixp
->fx_addsy
) + fixp
->fx_offset
;
10331 if (fixp
->fx_r_type
== BFD_RELOC_SIZE32
10332 && !fits_in_unsigned_long (value
))
10333 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10334 _("symbol size computation overflow"));
10335 fixp
->fx_addsy
= NULL
;
10336 fixp
->fx_subsy
= NULL
;
10337 md_apply_fix (fixp
, (valueT
*) &value
, NULL
);
10342 case BFD_RELOC_X86_64_PLT32
:
10343 case BFD_RELOC_X86_64_GOT32
:
10344 case BFD_RELOC_X86_64_GOTPCREL
:
10345 case BFD_RELOC_386_PLT32
:
10346 case BFD_RELOC_386_GOT32
:
10347 case BFD_RELOC_386_GOTOFF
:
10348 case BFD_RELOC_386_GOTPC
:
10349 case BFD_RELOC_386_TLS_GD
:
10350 case BFD_RELOC_386_TLS_LDM
:
10351 case BFD_RELOC_386_TLS_LDO_32
:
10352 case BFD_RELOC_386_TLS_IE_32
:
10353 case BFD_RELOC_386_TLS_IE
:
10354 case BFD_RELOC_386_TLS_GOTIE
:
10355 case BFD_RELOC_386_TLS_LE_32
:
10356 case BFD_RELOC_386_TLS_LE
:
10357 case BFD_RELOC_386_TLS_GOTDESC
:
10358 case BFD_RELOC_386_TLS_DESC_CALL
:
10359 case BFD_RELOC_X86_64_TLSGD
:
10360 case BFD_RELOC_X86_64_TLSLD
:
10361 case BFD_RELOC_X86_64_DTPOFF32
:
10362 case BFD_RELOC_X86_64_DTPOFF64
:
10363 case BFD_RELOC_X86_64_GOTTPOFF
:
10364 case BFD_RELOC_X86_64_TPOFF32
:
10365 case BFD_RELOC_X86_64_TPOFF64
:
10366 case BFD_RELOC_X86_64_GOTOFF64
:
10367 case BFD_RELOC_X86_64_GOTPC32
:
10368 case BFD_RELOC_X86_64_GOT64
:
10369 case BFD_RELOC_X86_64_GOTPCREL64
:
10370 case BFD_RELOC_X86_64_GOTPC64
:
10371 case BFD_RELOC_X86_64_GOTPLT64
:
10372 case BFD_RELOC_X86_64_PLTOFF64
:
10373 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
10374 case BFD_RELOC_X86_64_TLSDESC_CALL
:
10375 case BFD_RELOC_RVA
:
10376 case BFD_RELOC_VTABLE_ENTRY
:
10377 case BFD_RELOC_VTABLE_INHERIT
:
10379 case BFD_RELOC_32_SECREL
:
10381 code
= fixp
->fx_r_type
;
10383 case BFD_RELOC_X86_64_32S
:
10384 if (!fixp
->fx_pcrel
)
10386 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
10387 code
= fixp
->fx_r_type
;
10391 if (fixp
->fx_pcrel
)
10393 switch (fixp
->fx_size
)
10396 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10397 _("can not do %d byte pc-relative relocation"),
10399 code
= BFD_RELOC_32_PCREL
;
10401 case 1: code
= BFD_RELOC_8_PCREL
; break;
10402 case 2: code
= BFD_RELOC_16_PCREL
; break;
10403 case 4: code
= BFD_RELOC_32_PCREL
; break;
10405 case 8: code
= BFD_RELOC_64_PCREL
; break;
10411 switch (fixp
->fx_size
)
10414 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10415 _("can not do %d byte relocation"),
10417 code
= BFD_RELOC_32
;
10419 case 1: code
= BFD_RELOC_8
; break;
10420 case 2: code
= BFD_RELOC_16
; break;
10421 case 4: code
= BFD_RELOC_32
; break;
10423 case 8: code
= BFD_RELOC_64
; break;
10430 if ((code
== BFD_RELOC_32
10431 || code
== BFD_RELOC_32_PCREL
10432 || code
== BFD_RELOC_X86_64_32S
)
10434 && fixp
->fx_addsy
== GOT_symbol
)
10437 code
= BFD_RELOC_386_GOTPC
;
10439 code
= BFD_RELOC_X86_64_GOTPC32
;
10441 if ((code
== BFD_RELOC_64
|| code
== BFD_RELOC_64_PCREL
)
10443 && fixp
->fx_addsy
== GOT_symbol
)
10445 code
= BFD_RELOC_X86_64_GOTPC64
;
10448 rel
= (arelent
*) xmalloc (sizeof (arelent
));
10449 rel
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
10450 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
10452 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
10454 if (!use_rela_relocations
)
10456 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
10457 vtable entry to be used in the relocation's section offset. */
10458 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
10459 rel
->address
= fixp
->fx_offset
;
10460 #if defined (OBJ_COFF) && defined (TE_PE)
10461 else if (fixp
->fx_addsy
&& S_IS_WEAK (fixp
->fx_addsy
))
10462 rel
->addend
= fixp
->fx_addnumber
- (S_GET_VALUE (fixp
->fx_addsy
) * 2);
10467 /* Use the rela in 64bit mode. */
10470 if (disallow_64bit_reloc
)
10473 case BFD_RELOC_X86_64_DTPOFF64
:
10474 case BFD_RELOC_X86_64_TPOFF64
:
10475 case BFD_RELOC_64_PCREL
:
10476 case BFD_RELOC_X86_64_GOTOFF64
:
10477 case BFD_RELOC_X86_64_GOT64
:
10478 case BFD_RELOC_X86_64_GOTPCREL64
:
10479 case BFD_RELOC_X86_64_GOTPC64
:
10480 case BFD_RELOC_X86_64_GOTPLT64
:
10481 case BFD_RELOC_X86_64_PLTOFF64
:
10482 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10483 _("cannot represent relocation type %s in x32 mode"),
10484 bfd_get_reloc_code_name (code
));
10490 if (!fixp
->fx_pcrel
)
10491 rel
->addend
= fixp
->fx_offset
;
10495 case BFD_RELOC_X86_64_PLT32
:
10496 case BFD_RELOC_X86_64_GOT32
:
10497 case BFD_RELOC_X86_64_GOTPCREL
:
10498 case BFD_RELOC_X86_64_TLSGD
:
10499 case BFD_RELOC_X86_64_TLSLD
:
10500 case BFD_RELOC_X86_64_GOTTPOFF
:
10501 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
10502 case BFD_RELOC_X86_64_TLSDESC_CALL
:
10503 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
10506 rel
->addend
= (section
->vma
10508 + fixp
->fx_addnumber
10509 + md_pcrel_from (fixp
));
10514 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
10515 if (rel
->howto
== NULL
)
10517 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10518 _("cannot represent relocation type %s"),
10519 bfd_get_reloc_code_name (code
));
10520 /* Set howto to a garbage value so that we can keep going. */
10521 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
10522 gas_assert (rel
->howto
!= NULL
);
10528 #include "tc-i386-intel.c"
10531 tc_x86_parse_to_dw2regnum (expressionS
*exp
)
10533 int saved_naked_reg
;
10534 char saved_register_dot
;
10536 saved_naked_reg
= allow_naked_reg
;
10537 allow_naked_reg
= 1;
10538 saved_register_dot
= register_chars
['.'];
10539 register_chars
['.'] = '.';
10540 allow_pseudo_reg
= 1;
10541 expression_and_evaluate (exp
);
10542 allow_pseudo_reg
= 0;
10543 register_chars
['.'] = saved_register_dot
;
10544 allow_naked_reg
= saved_naked_reg
;
10546 if (exp
->X_op
== O_register
&& exp
->X_add_number
>= 0)
10548 if ((addressT
) exp
->X_add_number
< i386_regtab_size
)
10550 exp
->X_op
= O_constant
;
10551 exp
->X_add_number
= i386_regtab
[exp
->X_add_number
]
10552 .dw2_regnum
[flag_code
>> 1];
10555 exp
->X_op
= O_illegal
;
10560 tc_x86_frame_initial_instructions (void)
10562 static unsigned int sp_regno
[2];
10564 if (!sp_regno
[flag_code
>> 1])
10566 char *saved_input
= input_line_pointer
;
10567 char sp
[][4] = {"esp", "rsp"};
10570 input_line_pointer
= sp
[flag_code
>> 1];
10571 tc_x86_parse_to_dw2regnum (&exp
);
10572 gas_assert (exp
.X_op
== O_constant
);
10573 sp_regno
[flag_code
>> 1] = exp
.X_add_number
;
10574 input_line_pointer
= saved_input
;
10577 cfi_add_CFA_def_cfa (sp_regno
[flag_code
>> 1], -x86_cie_data_alignment
);
10578 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
10582 x86_dwarf2_addr_size (void)
10584 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
10585 if (x86_elf_abi
== X86_64_X32_ABI
)
10588 return bfd_arch_bits_per_address (stdoutput
) / 8;
10592 i386_elf_section_type (const char *str
, size_t len
)
10594 if (flag_code
== CODE_64BIT
10595 && len
== sizeof ("unwind") - 1
10596 && strncmp (str
, "unwind", 6) == 0)
10597 return SHT_X86_64_UNWIND
;
10604 i386_solaris_fix_up_eh_frame (segT sec
)
10606 if (flag_code
== CODE_64BIT
)
10607 elf_section_type (sec
) = SHT_X86_64_UNWIND
;
10613 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
10617 exp
.X_op
= O_secrel
;
10618 exp
.X_add_symbol
= symbol
;
10619 exp
.X_add_number
= 0;
10620 emit_expr (&exp
, size
);
10624 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10625 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
10628 x86_64_section_letter (int letter
, char **ptr_msg
)
10630 if (flag_code
== CODE_64BIT
)
10633 return SHF_X86_64_LARGE
;
10635 *ptr_msg
= _("bad .section directive: want a,l,w,x,M,S,G,T in string");
10638 *ptr_msg
= _("bad .section directive: want a,w,x,M,S,G,T in string");
10643 x86_64_section_word (char *str
, size_t len
)
10645 if (len
== 5 && flag_code
== CODE_64BIT
&& CONST_STRNEQ (str
, "large"))
10646 return SHF_X86_64_LARGE
;
10652 handle_large_common (int small ATTRIBUTE_UNUSED
)
10654 if (flag_code
!= CODE_64BIT
)
10656 s_comm_internal (0, elf_common_parse
);
10657 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
10661 static segT lbss_section
;
10662 asection
*saved_com_section_ptr
= elf_com_section_ptr
;
10663 asection
*saved_bss_section
= bss_section
;
10665 if (lbss_section
== NULL
)
10667 flagword applicable
;
10668 segT seg
= now_seg
;
10669 subsegT subseg
= now_subseg
;
10671 /* The .lbss section is for local .largecomm symbols. */
10672 lbss_section
= subseg_new (".lbss", 0);
10673 applicable
= bfd_applicable_section_flags (stdoutput
);
10674 bfd_set_section_flags (stdoutput
, lbss_section
,
10675 applicable
& SEC_ALLOC
);
10676 seg_info (lbss_section
)->bss
= 1;
10678 subseg_set (seg
, subseg
);
10681 elf_com_section_ptr
= &_bfd_elf_large_com_section
;
10682 bss_section
= lbss_section
;
10684 s_comm_internal (0, elf_common_parse
);
10686 elf_com_section_ptr
= saved_com_section_ptr
;
10687 bss_section
= saved_bss_section
;
10690 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */