1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright (C) 1989-2019 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 /* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
23 x86_64 support by Jan Hubicka (jh@suse.cz)
24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
29 #include "safe-ctype.h"
31 #include "dwarf2dbg.h"
32 #include "dw2gencfi.h"
33 #include "elf/x86-64.h"
34 #include "opcodes/i386-init.h"
39 #ifdef HAVE_SYS_PARAM_H
40 #include <sys/param.h>
43 #define INT_MAX (int) (((unsigned) (-1)) >> 1)
47 #ifndef REGISTER_WARNINGS
48 #define REGISTER_WARNINGS 1
51 #ifndef INFER_ADDR_PREFIX
52 #define INFER_ADDR_PREFIX 1
56 #define DEFAULT_ARCH "i386"
61 #define INLINE __inline__
67 /* Prefixes will be emitted in the order defined below.
68 WAIT_PREFIX must be the first prefix since FWAIT is really is an
69 instruction, and so must come before any prefixes.
70 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
71 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
77 #define HLE_PREFIX REP_PREFIX
78 #define BND_PREFIX REP_PREFIX
80 #define REX_PREFIX 6 /* must come last. */
81 #define MAX_PREFIXES 7 /* max prefixes per opcode */
83 /* we define the syntax here (modulo base,index,scale syntax) */
84 #define REGISTER_PREFIX '%'
85 #define IMMEDIATE_PREFIX '$'
86 #define ABSOLUTE_PREFIX '*'
88 /* these are the instruction mnemonic suffixes in AT&T syntax or
89 memory operand size in Intel syntax. */
90 #define WORD_MNEM_SUFFIX 'w'
91 #define BYTE_MNEM_SUFFIX 'b'
92 #define SHORT_MNEM_SUFFIX 's'
93 #define LONG_MNEM_SUFFIX 'l'
94 #define QWORD_MNEM_SUFFIX 'q'
95 /* Intel Syntax. Use a non-ascii letter since since it never appears
97 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
99 #define END_OF_INSN '\0'
102 'templates' is for grouping together 'template' structures for opcodes
103 of the same name. This is only used for storing the insns in the grand
104 ole hash table of insns.
105 The templates themselves start at START and range up to (but not including)
110 const insn_template
*start
;
111 const insn_template
*end
;
115 /* 386 operand encoding bytes: see 386 book for details of this. */
118 unsigned int regmem
; /* codes register or memory operand */
119 unsigned int reg
; /* codes register operand (or extended opcode) */
120 unsigned int mode
; /* how to interpret regmem & reg */
124 /* x86-64 extension prefix. */
125 typedef int rex_byte
;
127 /* 386 opcode byte to code indirect addressing. */
136 /* x86 arch names, types and features */
139 const char *name
; /* arch name */
140 unsigned int len
; /* arch string length */
141 enum processor_type type
; /* arch type */
142 i386_cpu_flags flags
; /* cpu feature flags */
143 unsigned int skip
; /* show_arch should skip this. */
147 /* Used to turn off indicated flags. */
150 const char *name
; /* arch name */
151 unsigned int len
; /* arch string length */
152 i386_cpu_flags flags
; /* cpu feature flags */
156 static void update_code_flag (int, int);
157 static void set_code_flag (int);
158 static void set_16bit_gcc_code_flag (int);
159 static void set_intel_syntax (int);
160 static void set_intel_mnemonic (int);
161 static void set_allow_index_reg (int);
162 static void set_check (int);
163 static void set_cpu_arch (int);
165 static void pe_directive_secrel (int);
167 static void signed_cons (int);
168 static char *output_invalid (int c
);
169 static int i386_finalize_immediate (segT
, expressionS
*, i386_operand_type
,
171 static int i386_finalize_displacement (segT
, expressionS
*, i386_operand_type
,
173 static int i386_att_operand (char *);
174 static int i386_intel_operand (char *, int);
175 static int i386_intel_simplify (expressionS
*);
176 static int i386_intel_parse_name (const char *, expressionS
*);
177 static const reg_entry
*parse_register (char *, char **);
178 static char *parse_insn (char *, char *);
179 static char *parse_operands (char *, const char *);
180 static void swap_operands (void);
181 static void swap_2_operands (int, int);
182 static void optimize_imm (void);
183 static void optimize_disp (void);
184 static const insn_template
*match_template (char);
185 static int check_string (void);
186 static int process_suffix (void);
187 static int check_byte_reg (void);
188 static int check_long_reg (void);
189 static int check_qword_reg (void);
190 static int check_word_reg (void);
191 static int finalize_imm (void);
192 static int process_operands (void);
193 static const seg_entry
*build_modrm_byte (void);
194 static void output_insn (void);
195 static void output_imm (fragS
*, offsetT
);
196 static void output_disp (fragS
*, offsetT
);
198 static void s_bss (int);
200 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
201 static void handle_large_common (int small ATTRIBUTE_UNUSED
);
203 /* GNU_PROPERTY_X86_ISA_1_USED. */
204 static unsigned int x86_isa_1_used
;
205 /* GNU_PROPERTY_X86_FEATURE_2_USED. */
206 static unsigned int x86_feature_2_used
;
207 /* Generate x86 used ISA and feature properties. */
208 static unsigned int x86_used_note
= DEFAULT_X86_USED_NOTE
;
211 static const char *default_arch
= DEFAULT_ARCH
;
213 /* This struct describes rounding control and SAE in the instruction. */
227 static struct RC_Operation rc_op
;
229 /* The struct describes masking, applied to OPERAND in the instruction.
230 MASK is a pointer to the corresponding mask register. ZEROING tells
231 whether merging or zeroing mask is used. */
232 struct Mask_Operation
234 const reg_entry
*mask
;
235 unsigned int zeroing
;
236 /* The operand where this operation is associated. */
240 static struct Mask_Operation mask_op
;
242 /* The struct describes broadcasting, applied to OPERAND. FACTOR is
244 struct Broadcast_Operation
246 /* Type of broadcast: {1to2}, {1to4}, {1to8}, or {1to16}. */
249 /* Index of broadcasted operand. */
252 /* Number of bytes to broadcast. */
256 static struct Broadcast_Operation broadcast_op
;
261 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
262 unsigned char bytes
[4];
264 /* Destination or source register specifier. */
265 const reg_entry
*register_specifier
;
268 /* 'md_assemble ()' gathers together information and puts it into a
275 const reg_entry
*regs
;
280 operand_size_mismatch
,
281 operand_type_mismatch
,
282 register_type_mismatch
,
283 number_of_operands_mismatch
,
284 invalid_instruction_suffix
,
286 unsupported_with_intel_mnemonic
,
289 invalid_vsib_address
,
290 invalid_vector_register_set
,
291 unsupported_vector_index_register
,
292 unsupported_broadcast
,
295 mask_not_on_destination
,
298 rc_sae_operand_not_last_imm
,
299 invalid_register_operand
,
304 /* TM holds the template for the insn were currently assembling. */
307 /* SUFFIX holds the instruction size suffix for byte, word, dword
308 or qword, if given. */
311 /* OPERANDS gives the number of given operands. */
312 unsigned int operands
;
314 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
315 of given register, displacement, memory operands and immediate
317 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
319 /* TYPES [i] is the type (see above #defines) which tells us how to
320 use OP[i] for the corresponding operand. */
321 i386_operand_type types
[MAX_OPERANDS
];
323 /* Displacement expression, immediate expression, or register for each
325 union i386_op op
[MAX_OPERANDS
];
327 /* Flags for operands. */
328 unsigned int flags
[MAX_OPERANDS
];
329 #define Operand_PCrel 1
330 #define Operand_Mem 2
332 /* Relocation type for operand */
333 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
335 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
336 the base index byte below. */
337 const reg_entry
*base_reg
;
338 const reg_entry
*index_reg
;
339 unsigned int log2_scale_factor
;
341 /* SEG gives the seg_entries of this insn. They are zero unless
342 explicit segment overrides are given. */
343 const seg_entry
*seg
[2];
345 /* Copied first memory operand string, for re-checking. */
348 /* PREFIX holds all the given prefix opcodes (usually null).
349 PREFIXES is the number of prefix opcodes. */
350 unsigned int prefixes
;
351 unsigned char prefix
[MAX_PREFIXES
];
353 /* Has MMX register operands. */
354 bfd_boolean has_regmmx
;
356 /* Has XMM register operands. */
357 bfd_boolean has_regxmm
;
359 /* Has YMM register operands. */
360 bfd_boolean has_regymm
;
362 /* Has ZMM register operands. */
363 bfd_boolean has_regzmm
;
365 /* RM and SIB are the modrm byte and the sib byte where the
366 addressing modes of this insn are encoded. */
373 /* Masking attributes. */
374 struct Mask_Operation
*mask
;
376 /* Rounding control and SAE attributes. */
377 struct RC_Operation
*rounding
;
379 /* Broadcasting attributes. */
380 struct Broadcast_Operation
*broadcast
;
382 /* Compressed disp8*N attribute. */
383 unsigned int memshift
;
385 /* Prefer load or store in encoding. */
388 dir_encoding_default
= 0,
394 /* Prefer 8bit or 32bit displacement in encoding. */
397 disp_encoding_default
= 0,
402 /* Prefer the REX byte in encoding. */
403 bfd_boolean rex_encoding
;
405 /* Disable instruction size optimization. */
406 bfd_boolean no_optimize
;
408 /* How to encode vector instructions. */
411 vex_encoding_default
= 0,
418 const char *rep_prefix
;
421 const char *hle_prefix
;
423 /* Have BND prefix. */
424 const char *bnd_prefix
;
426 /* Have NOTRACK prefix. */
427 const char *notrack_prefix
;
430 enum i386_error error
;
433 typedef struct _i386_insn i386_insn
;
435 /* Link RC type with corresponding string, that'll be looked for in
444 static const struct RC_name RC_NamesTable
[] =
446 { rne
, STRING_COMMA_LEN ("rn-sae") },
447 { rd
, STRING_COMMA_LEN ("rd-sae") },
448 { ru
, STRING_COMMA_LEN ("ru-sae") },
449 { rz
, STRING_COMMA_LEN ("rz-sae") },
450 { saeonly
, STRING_COMMA_LEN ("sae") },
453 /* List of chars besides those in app.c:symbol_chars that can start an
454 operand. Used to prevent the scrubber eating vital white-space. */
455 const char extra_symbol_chars
[] = "*%-([{}"
464 #if (defined (TE_I386AIX) \
465 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
466 && !defined (TE_GNU) \
467 && !defined (TE_LINUX) \
468 && !defined (TE_NACL) \
469 && !defined (TE_FreeBSD) \
470 && !defined (TE_DragonFly) \
471 && !defined (TE_NetBSD)))
472 /* This array holds the chars that always start a comment. If the
473 pre-processor is disabled, these aren't very useful. The option
474 --divide will remove '/' from this list. */
475 const char *i386_comment_chars
= "#/";
476 #define SVR4_COMMENT_CHARS 1
477 #define PREFIX_SEPARATOR '\\'
480 const char *i386_comment_chars
= "#";
481 #define PREFIX_SEPARATOR '/'
484 /* This array holds the chars that only start a comment at the beginning of
485 a line. If the line seems to have the form '# 123 filename'
486 .line and .file directives will appear in the pre-processed output.
487 Note that input_file.c hand checks for '#' at the beginning of the
488 first line of the input file. This is because the compiler outputs
489 #NO_APP at the beginning of its output.
490 Also note that comments started like this one will always work if
491 '/' isn't otherwise defined. */
492 const char line_comment_chars
[] = "#/";
494 const char line_separator_chars
[] = ";";
496 /* Chars that can be used to separate mant from exp in floating point
498 const char EXP_CHARS
[] = "eE";
500 /* Chars that mean this number is a floating point constant
503 const char FLT_CHARS
[] = "fFdDxX";
505 /* Tables for lexical analysis. */
506 static char mnemonic_chars
[256];
507 static char register_chars
[256];
508 static char operand_chars
[256];
509 static char identifier_chars
[256];
510 static char digit_chars
[256];
512 /* Lexical macros. */
513 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
514 #define is_operand_char(x) (operand_chars[(unsigned char) x])
515 #define is_register_char(x) (register_chars[(unsigned char) x])
516 #define is_space_char(x) ((x) == ' ')
517 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
518 #define is_digit_char(x) (digit_chars[(unsigned char) x])
520 /* All non-digit non-letter characters that may occur in an operand. */
521 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
523 /* md_assemble() always leaves the strings it's passed unaltered. To
524 effect this we maintain a stack of saved characters that we've smashed
525 with '\0's (indicating end of strings for various sub-fields of the
526 assembler instruction). */
527 static char save_stack
[32];
528 static char *save_stack_p
;
529 #define END_STRING_AND_SAVE(s) \
530 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
531 #define RESTORE_END_STRING(s) \
532 do { *(s) = *--save_stack_p; } while (0)
534 /* The instruction we're assembling. */
537 /* Possible templates for current insn. */
538 static const templates
*current_templates
;
540 /* Per instruction expressionS buffers: max displacements & immediates. */
541 static expressionS disp_expressions
[MAX_MEMORY_OPERANDS
];
542 static expressionS im_expressions
[MAX_IMMEDIATE_OPERANDS
];
544 /* Current operand we are working on. */
545 static int this_operand
= -1;
547 /* We support four different modes. FLAG_CODE variable is used to distinguish
555 static enum flag_code flag_code
;
556 static unsigned int object_64bit
;
557 static unsigned int disallow_64bit_reloc
;
558 static int use_rela_relocations
= 0;
560 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
561 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
562 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
564 /* The ELF ABI to use. */
572 static enum x86_elf_abi x86_elf_abi
= I386_ABI
;
575 #if defined (TE_PE) || defined (TE_PEP)
576 /* Use big object file format. */
577 static int use_big_obj
= 0;
580 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
581 /* 1 if generating code for a shared library. */
582 static int shared
= 0;
585 /* 1 for intel syntax,
587 static int intel_syntax
= 0;
589 /* 1 for Intel64 ISA,
593 /* 1 for intel mnemonic,
594 0 if att mnemonic. */
595 static int intel_mnemonic
= !SYSV386_COMPAT
;
597 /* 1 if pseudo registers are permitted. */
598 static int allow_pseudo_reg
= 0;
600 /* 1 if register prefix % not required. */
601 static int allow_naked_reg
= 0;
603 /* 1 if the assembler should add BND prefix for all control-transferring
604 instructions supporting it, even if this prefix wasn't specified
606 static int add_bnd_prefix
= 0;
608 /* 1 if pseudo index register, eiz/riz, is allowed . */
609 static int allow_index_reg
= 0;
611 /* 1 if the assembler should ignore LOCK prefix, even if it was
612 specified explicitly. */
613 static int omit_lock_prefix
= 0;
615 /* 1 if the assembler should encode lfence, mfence, and sfence as
616 "lock addl $0, (%{re}sp)". */
617 static int avoid_fence
= 0;
619 /* 1 if the assembler should generate relax relocations. */
621 static int generate_relax_relocations
622 = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS
;
624 static enum check_kind
630 sse_check
, operand_check
= check_warning
;
633 1. Clear the REX_W bit with register operand if possible.
634 2. Above plus use 128bit vector instruction to clear the full vector
637 static int optimize
= 0;
640 1. Clear the REX_W bit with register operand if possible.
641 2. Above plus use 128bit vector instruction to clear the full vector
643 3. Above plus optimize "test{q,l,w} $imm8,%r{64,32,16}" to
646 static int optimize_for_space
= 0;
648 /* Register prefix used for error message. */
649 static const char *register_prefix
= "%";
651 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
652 leave, push, and pop instructions so that gcc has the same stack
653 frame as in 32 bit mode. */
654 static char stackop_size
= '\0';
656 /* Non-zero to optimize code alignment. */
657 int optimize_align_code
= 1;
659 /* Non-zero to quieten some warnings. */
660 static int quiet_warnings
= 0;
663 static const char *cpu_arch_name
= NULL
;
664 static char *cpu_sub_arch_name
= NULL
;
666 /* CPU feature flags. */
667 static i386_cpu_flags cpu_arch_flags
= CPU_UNKNOWN_FLAGS
;
669 /* If we have selected a cpu we are generating instructions for. */
670 static int cpu_arch_tune_set
= 0;
672 /* Cpu we are generating instructions for. */
673 enum processor_type cpu_arch_tune
= PROCESSOR_UNKNOWN
;
675 /* CPU feature flags of cpu we are generating instructions for. */
676 static i386_cpu_flags cpu_arch_tune_flags
;
678 /* CPU instruction set architecture used. */
679 enum processor_type cpu_arch_isa
= PROCESSOR_UNKNOWN
;
681 /* CPU feature flags of instruction set architecture used. */
682 i386_cpu_flags cpu_arch_isa_flags
;
684 /* If set, conditional jumps are not automatically promoted to handle
685 larger than a byte offset. */
686 static unsigned int no_cond_jump_promotion
= 0;
688 /* Encode SSE instructions with VEX prefix. */
689 static unsigned int sse2avx
;
691 /* Encode scalar AVX instructions with specific vector length. */
698 /* Encode VEX WIG instructions with specific vex.w. */
705 /* Encode scalar EVEX LIG instructions with specific vector length. */
713 /* Encode EVEX WIG instructions with specific evex.w. */
720 /* Value to encode in EVEX RC bits, for SAE-only instructions. */
721 static enum rc_type evexrcig
= rne
;
723 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
724 static symbolS
*GOT_symbol
;
726 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
727 unsigned int x86_dwarf2_return_column
;
729 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
730 int x86_cie_data_alignment
;
732 /* Interface to relax_segment.
733 There are 3 major relax states for 386 jump insns because the
734 different types of jumps add different sizes to frags when we're
735 figuring out what sort of jump to choose to reach a given label. */
738 #define UNCOND_JUMP 0
740 #define COND_JUMP86 2
745 #define SMALL16 (SMALL | CODE16)
747 #define BIG16 (BIG | CODE16)
751 #define INLINE __inline__
757 #define ENCODE_RELAX_STATE(type, size) \
758 ((relax_substateT) (((type) << 2) | (size)))
759 #define TYPE_FROM_RELAX_STATE(s) \
761 #define DISP_SIZE_FROM_RELAX_STATE(s) \
762 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
764 /* This table is used by relax_frag to promote short jumps to long
765 ones where necessary. SMALL (short) jumps may be promoted to BIG
766 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
767 don't allow a short jump in a 32 bit code segment to be promoted to
768 a 16 bit offset jump because it's slower (requires data size
769 prefix), and doesn't work, unless the destination is in the bottom
770 64k of the code segment (The top 16 bits of eip are zeroed). */
772 const relax_typeS md_relax_table
[] =
775 1) most positive reach of this state,
776 2) most negative reach of this state,
777 3) how many bytes this mode will have in the variable part of the frag
778 4) which index into the table to try if we can't fit into this one. */
780 /* UNCOND_JUMP states. */
781 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
782 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
783 /* dword jmp adds 4 bytes to frag:
784 0 extra opcode bytes, 4 displacement bytes. */
786 /* word jmp adds 2 byte2 to frag:
787 0 extra opcode bytes, 2 displacement bytes. */
790 /* COND_JUMP states. */
791 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
792 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
793 /* dword conditionals adds 5 bytes to frag:
794 1 extra opcode byte, 4 displacement bytes. */
796 /* word conditionals add 3 bytes to frag:
797 1 extra opcode byte, 2 displacement bytes. */
800 /* COND_JUMP86 states. */
801 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
802 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
803 /* dword conditionals adds 5 bytes to frag:
804 1 extra opcode byte, 4 displacement bytes. */
806 /* word conditionals add 4 bytes to frag:
807 1 displacement byte and a 3 byte long branch insn. */
811 static const arch_entry cpu_arch
[] =
813 /* Do not replace the first two entries - i386_target_format()
814 relies on them being there in this order. */
815 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32
,
816 CPU_GENERIC32_FLAGS
, 0 },
817 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64
,
818 CPU_GENERIC64_FLAGS
, 0 },
819 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN
,
821 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN
,
823 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN
,
825 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386
,
827 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486
,
829 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM
,
831 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO
,
833 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM
,
835 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO
,
836 CPU_PENTIUMPRO_FLAGS
, 0 },
837 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO
,
839 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO
,
841 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4
,
843 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA
,
845 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA
,
846 CPU_NOCONA_FLAGS
, 0 },
847 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE
,
849 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE
,
851 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2
,
852 CPU_CORE2_FLAGS
, 1 },
853 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2
,
854 CPU_CORE2_FLAGS
, 0 },
855 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7
,
856 CPU_COREI7_FLAGS
, 0 },
857 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM
,
859 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM
,
861 { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU
,
862 CPU_IAMCU_FLAGS
, 0 },
863 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6
,
865 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6
,
867 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON
,
868 CPU_ATHLON_FLAGS
, 0 },
869 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8
,
871 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8
,
873 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8
,
875 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10
,
876 CPU_AMDFAM10_FLAGS
, 0 },
877 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD
,
878 CPU_BDVER1_FLAGS
, 0 },
879 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD
,
880 CPU_BDVER2_FLAGS
, 0 },
881 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD
,
882 CPU_BDVER3_FLAGS
, 0 },
883 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD
,
884 CPU_BDVER4_FLAGS
, 0 },
885 { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER
,
886 CPU_ZNVER1_FLAGS
, 0 },
887 { STRING_COMMA_LEN ("znver2"), PROCESSOR_ZNVER
,
888 CPU_ZNVER2_FLAGS
, 0 },
889 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT
,
890 CPU_BTVER1_FLAGS
, 0 },
891 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT
,
892 CPU_BTVER2_FLAGS
, 0 },
893 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN
,
895 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN
,
897 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN
,
899 { STRING_COMMA_LEN (".687"), PROCESSOR_UNKNOWN
,
901 { STRING_COMMA_LEN (".cmov"), PROCESSOR_UNKNOWN
,
903 { STRING_COMMA_LEN (".fxsr"), PROCESSOR_UNKNOWN
,
905 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN
,
907 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN
,
909 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN
,
911 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN
,
913 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN
,
914 CPU_SSSE3_FLAGS
, 0 },
915 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN
,
916 CPU_SSE4_1_FLAGS
, 0 },
917 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN
,
918 CPU_SSE4_2_FLAGS
, 0 },
919 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN
,
920 CPU_SSE4_2_FLAGS
, 0 },
921 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN
,
923 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN
,
925 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN
,
926 CPU_AVX512F_FLAGS
, 0 },
927 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN
,
928 CPU_AVX512CD_FLAGS
, 0 },
929 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN
,
930 CPU_AVX512ER_FLAGS
, 0 },
931 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN
,
932 CPU_AVX512PF_FLAGS
, 0 },
933 { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN
,
934 CPU_AVX512DQ_FLAGS
, 0 },
935 { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN
,
936 CPU_AVX512BW_FLAGS
, 0 },
937 { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN
,
938 CPU_AVX512VL_FLAGS
, 0 },
939 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN
,
941 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN
,
942 CPU_VMFUNC_FLAGS
, 0 },
943 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN
,
945 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN
,
946 CPU_XSAVE_FLAGS
, 0 },
947 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN
,
948 CPU_XSAVEOPT_FLAGS
, 0 },
949 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN
,
950 CPU_XSAVEC_FLAGS
, 0 },
951 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN
,
952 CPU_XSAVES_FLAGS
, 0 },
953 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN
,
955 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN
,
956 CPU_PCLMUL_FLAGS
, 0 },
957 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN
,
958 CPU_PCLMUL_FLAGS
, 1 },
959 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN
,
960 CPU_FSGSBASE_FLAGS
, 0 },
961 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN
,
962 CPU_RDRND_FLAGS
, 0 },
963 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN
,
965 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN
,
967 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN
,
969 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN
,
971 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN
,
973 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN
,
975 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN
,
976 CPU_MOVBE_FLAGS
, 0 },
977 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN
,
979 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN
,
981 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN
,
982 CPU_LZCNT_FLAGS
, 0 },
983 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN
,
985 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN
,
987 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN
,
988 CPU_INVPCID_FLAGS
, 0 },
989 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN
,
990 CPU_CLFLUSH_FLAGS
, 0 },
991 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN
,
993 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN
,
994 CPU_SYSCALL_FLAGS
, 0 },
995 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN
,
996 CPU_RDTSCP_FLAGS
, 0 },
997 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN
,
998 CPU_3DNOW_FLAGS
, 0 },
999 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN
,
1000 CPU_3DNOWA_FLAGS
, 0 },
1001 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN
,
1002 CPU_PADLOCK_FLAGS
, 0 },
1003 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN
,
1004 CPU_SVME_FLAGS
, 1 },
1005 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN
,
1006 CPU_SVME_FLAGS
, 0 },
1007 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN
,
1008 CPU_SSE4A_FLAGS
, 0 },
1009 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN
,
1011 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN
,
1013 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN
,
1015 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN
,
1017 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN
,
1018 CPU_RDSEED_FLAGS
, 0 },
1019 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN
,
1020 CPU_PRFCHW_FLAGS
, 0 },
1021 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN
,
1022 CPU_SMAP_FLAGS
, 0 },
1023 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN
,
1025 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN
,
1027 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN
,
1028 CPU_CLFLUSHOPT_FLAGS
, 0 },
1029 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN
,
1030 CPU_PREFETCHWT1_FLAGS
, 0 },
1031 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN
,
1033 { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN
,
1034 CPU_CLWB_FLAGS
, 0 },
1035 { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN
,
1036 CPU_AVX512IFMA_FLAGS
, 0 },
1037 { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN
,
1038 CPU_AVX512VBMI_FLAGS
, 0 },
1039 { STRING_COMMA_LEN (".avx512_4fmaps"), PROCESSOR_UNKNOWN
,
1040 CPU_AVX512_4FMAPS_FLAGS
, 0 },
1041 { STRING_COMMA_LEN (".avx512_4vnniw"), PROCESSOR_UNKNOWN
,
1042 CPU_AVX512_4VNNIW_FLAGS
, 0 },
1043 { STRING_COMMA_LEN (".avx512_vpopcntdq"), PROCESSOR_UNKNOWN
,
1044 CPU_AVX512_VPOPCNTDQ_FLAGS
, 0 },
1045 { STRING_COMMA_LEN (".avx512_vbmi2"), PROCESSOR_UNKNOWN
,
1046 CPU_AVX512_VBMI2_FLAGS
, 0 },
1047 { STRING_COMMA_LEN (".avx512_vnni"), PROCESSOR_UNKNOWN
,
1048 CPU_AVX512_VNNI_FLAGS
, 0 },
1049 { STRING_COMMA_LEN (".avx512_bitalg"), PROCESSOR_UNKNOWN
,
1050 CPU_AVX512_BITALG_FLAGS
, 0 },
1051 { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN
,
1052 CPU_CLZERO_FLAGS
, 0 },
1053 { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN
,
1054 CPU_MWAITX_FLAGS
, 0 },
1055 { STRING_COMMA_LEN (".ospke"), PROCESSOR_UNKNOWN
,
1056 CPU_OSPKE_FLAGS
, 0 },
1057 { STRING_COMMA_LEN (".rdpid"), PROCESSOR_UNKNOWN
,
1058 CPU_RDPID_FLAGS
, 0 },
1059 { STRING_COMMA_LEN (".ptwrite"), PROCESSOR_UNKNOWN
,
1060 CPU_PTWRITE_FLAGS
, 0 },
1061 { STRING_COMMA_LEN (".ibt"), PROCESSOR_UNKNOWN
,
1063 { STRING_COMMA_LEN (".shstk"), PROCESSOR_UNKNOWN
,
1064 CPU_SHSTK_FLAGS
, 0 },
1065 { STRING_COMMA_LEN (".gfni"), PROCESSOR_UNKNOWN
,
1066 CPU_GFNI_FLAGS
, 0 },
1067 { STRING_COMMA_LEN (".vaes"), PROCESSOR_UNKNOWN
,
1068 CPU_VAES_FLAGS
, 0 },
1069 { STRING_COMMA_LEN (".vpclmulqdq"), PROCESSOR_UNKNOWN
,
1070 CPU_VPCLMULQDQ_FLAGS
, 0 },
1071 { STRING_COMMA_LEN (".wbnoinvd"), PROCESSOR_UNKNOWN
,
1072 CPU_WBNOINVD_FLAGS
, 0 },
1073 { STRING_COMMA_LEN (".pconfig"), PROCESSOR_UNKNOWN
,
1074 CPU_PCONFIG_FLAGS
, 0 },
1075 { STRING_COMMA_LEN (".waitpkg"), PROCESSOR_UNKNOWN
,
1076 CPU_WAITPKG_FLAGS
, 0 },
1077 { STRING_COMMA_LEN (".cldemote"), PROCESSOR_UNKNOWN
,
1078 CPU_CLDEMOTE_FLAGS
, 0 },
1079 { STRING_COMMA_LEN (".movdiri"), PROCESSOR_UNKNOWN
,
1080 CPU_MOVDIRI_FLAGS
, 0 },
1081 { STRING_COMMA_LEN (".movdir64b"), PROCESSOR_UNKNOWN
,
1082 CPU_MOVDIR64B_FLAGS
, 0 },
1085 static const noarch_entry cpu_noarch
[] =
1087 { STRING_COMMA_LEN ("no87"), CPU_ANY_X87_FLAGS
},
1088 { STRING_COMMA_LEN ("no287"), CPU_ANY_287_FLAGS
},
1089 { STRING_COMMA_LEN ("no387"), CPU_ANY_387_FLAGS
},
1090 { STRING_COMMA_LEN ("no687"), CPU_ANY_687_FLAGS
},
1091 { STRING_COMMA_LEN ("nocmov"), CPU_ANY_CMOV_FLAGS
},
1092 { STRING_COMMA_LEN ("nofxsr"), CPU_ANY_FXSR_FLAGS
},
1093 { STRING_COMMA_LEN ("nommx"), CPU_ANY_MMX_FLAGS
},
1094 { STRING_COMMA_LEN ("nosse"), CPU_ANY_SSE_FLAGS
},
1095 { STRING_COMMA_LEN ("nosse2"), CPU_ANY_SSE2_FLAGS
},
1096 { STRING_COMMA_LEN ("nosse3"), CPU_ANY_SSE3_FLAGS
},
1097 { STRING_COMMA_LEN ("nossse3"), CPU_ANY_SSSE3_FLAGS
},
1098 { STRING_COMMA_LEN ("nosse4.1"), CPU_ANY_SSE4_1_FLAGS
},
1099 { STRING_COMMA_LEN ("nosse4.2"), CPU_ANY_SSE4_2_FLAGS
},
1100 { STRING_COMMA_LEN ("nosse4"), CPU_ANY_SSE4_1_FLAGS
},
1101 { STRING_COMMA_LEN ("noavx"), CPU_ANY_AVX_FLAGS
},
1102 { STRING_COMMA_LEN ("noavx2"), CPU_ANY_AVX2_FLAGS
},
1103 { STRING_COMMA_LEN ("noavx512f"), CPU_ANY_AVX512F_FLAGS
},
1104 { STRING_COMMA_LEN ("noavx512cd"), CPU_ANY_AVX512CD_FLAGS
},
1105 { STRING_COMMA_LEN ("noavx512er"), CPU_ANY_AVX512ER_FLAGS
},
1106 { STRING_COMMA_LEN ("noavx512pf"), CPU_ANY_AVX512PF_FLAGS
},
1107 { STRING_COMMA_LEN ("noavx512dq"), CPU_ANY_AVX512DQ_FLAGS
},
1108 { STRING_COMMA_LEN ("noavx512bw"), CPU_ANY_AVX512BW_FLAGS
},
1109 { STRING_COMMA_LEN ("noavx512vl"), CPU_ANY_AVX512VL_FLAGS
},
1110 { STRING_COMMA_LEN ("noavx512ifma"), CPU_ANY_AVX512IFMA_FLAGS
},
1111 { STRING_COMMA_LEN ("noavx512vbmi"), CPU_ANY_AVX512VBMI_FLAGS
},
1112 { STRING_COMMA_LEN ("noavx512_4fmaps"), CPU_ANY_AVX512_4FMAPS_FLAGS
},
1113 { STRING_COMMA_LEN ("noavx512_4vnniw"), CPU_ANY_AVX512_4VNNIW_FLAGS
},
1114 { STRING_COMMA_LEN ("noavx512_vpopcntdq"), CPU_ANY_AVX512_VPOPCNTDQ_FLAGS
},
1115 { STRING_COMMA_LEN ("noavx512_vbmi2"), CPU_ANY_AVX512_VBMI2_FLAGS
},
1116 { STRING_COMMA_LEN ("noavx512_vnni"), CPU_ANY_AVX512_VNNI_FLAGS
},
1117 { STRING_COMMA_LEN ("noavx512_bitalg"), CPU_ANY_AVX512_BITALG_FLAGS
},
1118 { STRING_COMMA_LEN ("noibt"), CPU_ANY_IBT_FLAGS
},
1119 { STRING_COMMA_LEN ("noshstk"), CPU_ANY_SHSTK_FLAGS
},
1120 { STRING_COMMA_LEN ("nomovdiri"), CPU_ANY_MOVDIRI_FLAGS
},
1121 { STRING_COMMA_LEN ("nomovdir64b"), CPU_ANY_MOVDIR64B_FLAGS
},
1125 /* Like s_lcomm_internal in gas/read.c but the alignment string
1126 is allowed to be optional. */
1129 pe_lcomm_internal (int needs_align
, symbolS
*symbolP
, addressT size
)
1136 && *input_line_pointer
== ',')
1138 align
= parse_align (needs_align
- 1);
1140 if (align
== (addressT
) -1)
1155 bss_alloc (symbolP
, size
, align
);
1160 pe_lcomm (int needs_align
)
1162 s_comm_internal (needs_align
* 2, pe_lcomm_internal
);
1166 const pseudo_typeS md_pseudo_table
[] =
1168 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
1169 {"align", s_align_bytes
, 0},
1171 {"align", s_align_ptwo
, 0},
1173 {"arch", set_cpu_arch
, 0},
1177 {"lcomm", pe_lcomm
, 1},
1179 {"ffloat", float_cons
, 'f'},
1180 {"dfloat", float_cons
, 'd'},
1181 {"tfloat", float_cons
, 'x'},
1183 {"slong", signed_cons
, 4},
1184 {"noopt", s_ignore
, 0},
1185 {"optim", s_ignore
, 0},
1186 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
1187 {"code16", set_code_flag
, CODE_16BIT
},
1188 {"code32", set_code_flag
, CODE_32BIT
},
1190 {"code64", set_code_flag
, CODE_64BIT
},
1192 {"intel_syntax", set_intel_syntax
, 1},
1193 {"att_syntax", set_intel_syntax
, 0},
1194 {"intel_mnemonic", set_intel_mnemonic
, 1},
1195 {"att_mnemonic", set_intel_mnemonic
, 0},
1196 {"allow_index_reg", set_allow_index_reg
, 1},
1197 {"disallow_index_reg", set_allow_index_reg
, 0},
1198 {"sse_check", set_check
, 0},
1199 {"operand_check", set_check
, 1},
1200 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1201 {"largecomm", handle_large_common
, 0},
1203 {"file", dwarf2_directive_file
, 0},
1204 {"loc", dwarf2_directive_loc
, 0},
1205 {"loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0},
1208 {"secrel32", pe_directive_secrel
, 0},
1213 /* For interface with expression (). */
1214 extern char *input_line_pointer
;
1216 /* Hash table for instruction mnemonic lookup. */
1217 static struct hash_control
*op_hash
;
1219 /* Hash table for register lookup. */
1220 static struct hash_control
*reg_hash
;
1222 /* Various efficient no-op patterns for aligning code labels.
1223 Note: Don't try to assemble the instructions in the comments.
1224 0L and 0w are not legal. */
1225 static const unsigned char f32_1
[] =
1227 static const unsigned char f32_2
[] =
1228 {0x66,0x90}; /* xchg %ax,%ax */
1229 static const unsigned char f32_3
[] =
1230 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1231 static const unsigned char f32_4
[] =
1232 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1233 static const unsigned char f32_6
[] =
1234 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1235 static const unsigned char f32_7
[] =
1236 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1237 static const unsigned char f16_3
[] =
1238 {0x8d,0x74,0x00}; /* lea 0(%si),%si */
1239 static const unsigned char f16_4
[] =
1240 {0x8d,0xb4,0x00,0x00}; /* lea 0W(%si),%si */
1241 static const unsigned char jump_disp8
[] =
1242 {0xeb}; /* jmp disp8 */
1243 static const unsigned char jump32_disp32
[] =
1244 {0xe9}; /* jmp disp32 */
1245 static const unsigned char jump16_disp32
[] =
1246 {0x66,0xe9}; /* jmp disp32 */
1247 /* 32-bit NOPs patterns. */
1248 static const unsigned char *const f32_patt
[] = {
1249 f32_1
, f32_2
, f32_3
, f32_4
, NULL
, f32_6
, f32_7
1251 /* 16-bit NOPs patterns. */
1252 static const unsigned char *const f16_patt
[] = {
1253 f32_1
, f32_2
, f16_3
, f16_4
1255 /* nopl (%[re]ax) */
1256 static const unsigned char alt_3
[] =
1258 /* nopl 0(%[re]ax) */
1259 static const unsigned char alt_4
[] =
1260 {0x0f,0x1f,0x40,0x00};
1261 /* nopl 0(%[re]ax,%[re]ax,1) */
1262 static const unsigned char alt_5
[] =
1263 {0x0f,0x1f,0x44,0x00,0x00};
1264 /* nopw 0(%[re]ax,%[re]ax,1) */
1265 static const unsigned char alt_6
[] =
1266 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1267 /* nopl 0L(%[re]ax) */
1268 static const unsigned char alt_7
[] =
1269 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1270 /* nopl 0L(%[re]ax,%[re]ax,1) */
1271 static const unsigned char alt_8
[] =
1272 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1273 /* nopw 0L(%[re]ax,%[re]ax,1) */
1274 static const unsigned char alt_9
[] =
1275 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1276 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1277 static const unsigned char alt_10
[] =
1278 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1279 /* data16 nopw %cs:0L(%eax,%eax,1) */
1280 static const unsigned char alt_11
[] =
1281 {0x66,0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1282 /* 32-bit and 64-bit NOPs patterns. */
1283 static const unsigned char *const alt_patt
[] = {
1284 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
1285 alt_9
, alt_10
, alt_11
1288 /* Genenerate COUNT bytes of NOPs to WHERE from PATT with the maximum
1289 size of a single NOP instruction MAX_SINGLE_NOP_SIZE. */
1292 i386_output_nops (char *where
, const unsigned char *const *patt
,
1293 int count
, int max_single_nop_size
)
1296 /* Place the longer NOP first. */
1299 const unsigned char *nops
= patt
[max_single_nop_size
- 1];
1301 /* Use the smaller one if the requsted one isn't available. */
1304 max_single_nop_size
--;
1305 nops
= patt
[max_single_nop_size
- 1];
1308 last
= count
% max_single_nop_size
;
1311 for (offset
= 0; offset
< count
; offset
+= max_single_nop_size
)
1312 memcpy (where
+ offset
, nops
, max_single_nop_size
);
1316 nops
= patt
[last
- 1];
1319 /* Use the smaller one plus one-byte NOP if the needed one
1322 nops
= patt
[last
- 1];
1323 memcpy (where
+ offset
, nops
, last
);
1324 where
[offset
+ last
] = *patt
[0];
1327 memcpy (where
+ offset
, nops
, last
);
1332 fits_in_imm7 (offsetT num
)
1334 return (num
& 0x7f) == num
;
1338 fits_in_imm31 (offsetT num
)
1340 return (num
& 0x7fffffff) == num
;
1343 /* Genenerate COUNT bytes of NOPs to WHERE with the maximum size of a
1344 single NOP instruction LIMIT. */
1347 i386_generate_nops (fragS
*fragP
, char *where
, offsetT count
, int limit
)
1349 const unsigned char *const *patt
= NULL
;
1350 int max_single_nop_size
;
1351 /* Maximum number of NOPs before switching to jump over NOPs. */
1352 int max_number_of_nops
;
1354 switch (fragP
->fr_type
)
1363 /* We need to decide which NOP sequence to use for 32bit and
1364 64bit. When -mtune= is used:
1366 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1367 PROCESSOR_GENERIC32, f32_patt will be used.
1368 2. For the rest, alt_patt will be used.
1370 When -mtune= isn't used, alt_patt will be used if
1371 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
1374 When -march= or .arch is used, we can't use anything beyond
1375 cpu_arch_isa_flags. */
1377 if (flag_code
== CODE_16BIT
)
1380 max_single_nop_size
= sizeof (f16_patt
) / sizeof (f16_patt
[0]);
1381 /* Limit number of NOPs to 2 in 16-bit mode. */
1382 max_number_of_nops
= 2;
1386 if (fragP
->tc_frag_data
.isa
== PROCESSOR_UNKNOWN
)
1388 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1389 switch (cpu_arch_tune
)
1391 case PROCESSOR_UNKNOWN
:
1392 /* We use cpu_arch_isa_flags to check if we SHOULD
1393 optimize with nops. */
1394 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1399 case PROCESSOR_PENTIUM4
:
1400 case PROCESSOR_NOCONA
:
1401 case PROCESSOR_CORE
:
1402 case PROCESSOR_CORE2
:
1403 case PROCESSOR_COREI7
:
1404 case PROCESSOR_L1OM
:
1405 case PROCESSOR_K1OM
:
1406 case PROCESSOR_GENERIC64
:
1408 case PROCESSOR_ATHLON
:
1410 case PROCESSOR_AMDFAM10
:
1412 case PROCESSOR_ZNVER
:
1416 case PROCESSOR_I386
:
1417 case PROCESSOR_I486
:
1418 case PROCESSOR_PENTIUM
:
1419 case PROCESSOR_PENTIUMPRO
:
1420 case PROCESSOR_IAMCU
:
1421 case PROCESSOR_GENERIC32
:
1428 switch (fragP
->tc_frag_data
.tune
)
1430 case PROCESSOR_UNKNOWN
:
1431 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1432 PROCESSOR_UNKNOWN. */
1436 case PROCESSOR_I386
:
1437 case PROCESSOR_I486
:
1438 case PROCESSOR_PENTIUM
:
1439 case PROCESSOR_IAMCU
:
1441 case PROCESSOR_ATHLON
:
1443 case PROCESSOR_AMDFAM10
:
1445 case PROCESSOR_ZNVER
:
1447 case PROCESSOR_GENERIC32
:
1448 /* We use cpu_arch_isa_flags to check if we CAN optimize
1450 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1455 case PROCESSOR_PENTIUMPRO
:
1456 case PROCESSOR_PENTIUM4
:
1457 case PROCESSOR_NOCONA
:
1458 case PROCESSOR_CORE
:
1459 case PROCESSOR_CORE2
:
1460 case PROCESSOR_COREI7
:
1461 case PROCESSOR_L1OM
:
1462 case PROCESSOR_K1OM
:
1463 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1468 case PROCESSOR_GENERIC64
:
1474 if (patt
== f32_patt
)
1476 max_single_nop_size
= sizeof (f32_patt
) / sizeof (f32_patt
[0]);
1477 /* Limit number of NOPs to 2 for older processors. */
1478 max_number_of_nops
= 2;
1482 max_single_nop_size
= sizeof (alt_patt
) / sizeof (alt_patt
[0]);
1483 /* Limit number of NOPs to 7 for newer processors. */
1484 max_number_of_nops
= 7;
1489 limit
= max_single_nop_size
;
1491 if (fragP
->fr_type
== rs_fill_nop
)
1493 /* Output NOPs for .nop directive. */
1494 if (limit
> max_single_nop_size
)
1496 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
1497 _("invalid single nop size: %d "
1498 "(expect within [0, %d])"),
1499 limit
, max_single_nop_size
);
1504 fragP
->fr_var
= count
;
1506 if ((count
/ max_single_nop_size
) > max_number_of_nops
)
1508 /* Generate jump over NOPs. */
1509 offsetT disp
= count
- 2;
1510 if (fits_in_imm7 (disp
))
1512 /* Use "jmp disp8" if possible. */
1514 where
[0] = jump_disp8
[0];
1520 unsigned int size_of_jump
;
1522 if (flag_code
== CODE_16BIT
)
1524 where
[0] = jump16_disp32
[0];
1525 where
[1] = jump16_disp32
[1];
1530 where
[0] = jump32_disp32
[0];
1534 count
-= size_of_jump
+ 4;
1535 if (!fits_in_imm31 (count
))
1537 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
1538 _("jump over nop padding out of range"));
1542 md_number_to_chars (where
+ size_of_jump
, count
, 4);
1543 where
+= size_of_jump
+ 4;
1547 /* Generate multiple NOPs. */
1548 i386_output_nops (where
, patt
, count
, limit
);
1552 operand_type_all_zero (const union i386_operand_type
*x
)
1554 switch (ARRAY_SIZE(x
->array
))
1565 return !x
->array
[0];
1572 operand_type_set (union i386_operand_type
*x
, unsigned int v
)
1574 switch (ARRAY_SIZE(x
->array
))
1592 operand_type_equal (const union i386_operand_type
*x
,
1593 const union i386_operand_type
*y
)
1595 switch (ARRAY_SIZE(x
->array
))
1598 if (x
->array
[2] != y
->array
[2])
1602 if (x
->array
[1] != y
->array
[1])
1606 return x
->array
[0] == y
->array
[0];
1614 cpu_flags_all_zero (const union i386_cpu_flags
*x
)
1616 switch (ARRAY_SIZE(x
->array
))
1631 return !x
->array
[0];
1638 cpu_flags_equal (const union i386_cpu_flags
*x
,
1639 const union i386_cpu_flags
*y
)
1641 switch (ARRAY_SIZE(x
->array
))
1644 if (x
->array
[3] != y
->array
[3])
1648 if (x
->array
[2] != y
->array
[2])
1652 if (x
->array
[1] != y
->array
[1])
1656 return x
->array
[0] == y
->array
[0];
1664 cpu_flags_check_cpu64 (i386_cpu_flags f
)
1666 return !((flag_code
== CODE_64BIT
&& f
.bitfield
.cpuno64
)
1667 || (flag_code
!= CODE_64BIT
&& f
.bitfield
.cpu64
));
1670 static INLINE i386_cpu_flags
1671 cpu_flags_and (i386_cpu_flags x
, i386_cpu_flags y
)
1673 switch (ARRAY_SIZE (x
.array
))
1676 x
.array
[3] &= y
.array
[3];
1679 x
.array
[2] &= y
.array
[2];
1682 x
.array
[1] &= y
.array
[1];
1685 x
.array
[0] &= y
.array
[0];
1693 static INLINE i386_cpu_flags
1694 cpu_flags_or (i386_cpu_flags x
, i386_cpu_flags y
)
1696 switch (ARRAY_SIZE (x
.array
))
1699 x
.array
[3] |= y
.array
[3];
1702 x
.array
[2] |= y
.array
[2];
1705 x
.array
[1] |= y
.array
[1];
1708 x
.array
[0] |= y
.array
[0];
1716 static INLINE i386_cpu_flags
1717 cpu_flags_and_not (i386_cpu_flags x
, i386_cpu_flags y
)
1719 switch (ARRAY_SIZE (x
.array
))
1722 x
.array
[3] &= ~y
.array
[3];
1725 x
.array
[2] &= ~y
.array
[2];
1728 x
.array
[1] &= ~y
.array
[1];
1731 x
.array
[0] &= ~y
.array
[0];
1739 #define CPU_FLAGS_ARCH_MATCH 0x1
1740 #define CPU_FLAGS_64BIT_MATCH 0x2
1742 #define CPU_FLAGS_PERFECT_MATCH \
1743 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_64BIT_MATCH)
1745 /* Return CPU flags match bits. */
1748 cpu_flags_match (const insn_template
*t
)
1750 i386_cpu_flags x
= t
->cpu_flags
;
1751 int match
= cpu_flags_check_cpu64 (x
) ? CPU_FLAGS_64BIT_MATCH
: 0;
1753 x
.bitfield
.cpu64
= 0;
1754 x
.bitfield
.cpuno64
= 0;
1756 if (cpu_flags_all_zero (&x
))
1758 /* This instruction is available on all archs. */
1759 match
|= CPU_FLAGS_ARCH_MATCH
;
1763 /* This instruction is available only on some archs. */
1764 i386_cpu_flags cpu
= cpu_arch_flags
;
1766 /* AVX512VL is no standalone feature - match it and then strip it. */
1767 if (x
.bitfield
.cpuavx512vl
&& !cpu
.bitfield
.cpuavx512vl
)
1769 x
.bitfield
.cpuavx512vl
= 0;
1771 cpu
= cpu_flags_and (x
, cpu
);
1772 if (!cpu_flags_all_zero (&cpu
))
1774 if (x
.bitfield
.cpuavx
)
1776 /* We need to check a few extra flags with AVX. */
1777 if (cpu
.bitfield
.cpuavx
1778 && (!t
->opcode_modifier
.sse2avx
|| sse2avx
)
1779 && (!x
.bitfield
.cpuaes
|| cpu
.bitfield
.cpuaes
)
1780 && (!x
.bitfield
.cpugfni
|| cpu
.bitfield
.cpugfni
)
1781 && (!x
.bitfield
.cpupclmul
|| cpu
.bitfield
.cpupclmul
))
1782 match
|= CPU_FLAGS_ARCH_MATCH
;
1784 else if (x
.bitfield
.cpuavx512f
)
1786 /* We need to check a few extra flags with AVX512F. */
1787 if (cpu
.bitfield
.cpuavx512f
1788 && (!x
.bitfield
.cpugfni
|| cpu
.bitfield
.cpugfni
)
1789 && (!x
.bitfield
.cpuvaes
|| cpu
.bitfield
.cpuvaes
)
1790 && (!x
.bitfield
.cpuvpclmulqdq
|| cpu
.bitfield
.cpuvpclmulqdq
))
1791 match
|= CPU_FLAGS_ARCH_MATCH
;
1794 match
|= CPU_FLAGS_ARCH_MATCH
;
1800 static INLINE i386_operand_type
1801 operand_type_and (i386_operand_type x
, i386_operand_type y
)
1803 switch (ARRAY_SIZE (x
.array
))
1806 x
.array
[2] &= y
.array
[2];
1809 x
.array
[1] &= y
.array
[1];
1812 x
.array
[0] &= y
.array
[0];
1820 static INLINE i386_operand_type
1821 operand_type_and_not (i386_operand_type x
, i386_operand_type y
)
1823 switch (ARRAY_SIZE (x
.array
))
1826 x
.array
[2] &= ~y
.array
[2];
1829 x
.array
[1] &= ~y
.array
[1];
1832 x
.array
[0] &= ~y
.array
[0];
1840 static INLINE i386_operand_type
1841 operand_type_or (i386_operand_type x
, i386_operand_type y
)
1843 switch (ARRAY_SIZE (x
.array
))
1846 x
.array
[2] |= y
.array
[2];
1849 x
.array
[1] |= y
.array
[1];
1852 x
.array
[0] |= y
.array
[0];
1860 static INLINE i386_operand_type
1861 operand_type_xor (i386_operand_type x
, i386_operand_type y
)
1863 switch (ARRAY_SIZE (x
.array
))
1866 x
.array
[2] ^= y
.array
[2];
1869 x
.array
[1] ^= y
.array
[1];
1872 x
.array
[0] ^= y
.array
[0];
1880 static const i386_operand_type acc32
= OPERAND_TYPE_ACC32
;
1881 static const i386_operand_type acc64
= OPERAND_TYPE_ACC64
;
1882 static const i386_operand_type disp16
= OPERAND_TYPE_DISP16
;
1883 static const i386_operand_type disp32
= OPERAND_TYPE_DISP32
;
1884 static const i386_operand_type disp32s
= OPERAND_TYPE_DISP32S
;
1885 static const i386_operand_type disp16_32
= OPERAND_TYPE_DISP16_32
;
1886 static const i386_operand_type anydisp
1887 = OPERAND_TYPE_ANYDISP
;
1888 static const i386_operand_type regxmm
= OPERAND_TYPE_REGXMM
;
1889 static const i386_operand_type regmask
= OPERAND_TYPE_REGMASK
;
1890 static const i386_operand_type imm8
= OPERAND_TYPE_IMM8
;
1891 static const i386_operand_type imm8s
= OPERAND_TYPE_IMM8S
;
1892 static const i386_operand_type imm16
= OPERAND_TYPE_IMM16
;
1893 static const i386_operand_type imm32
= OPERAND_TYPE_IMM32
;
1894 static const i386_operand_type imm32s
= OPERAND_TYPE_IMM32S
;
1895 static const i386_operand_type imm64
= OPERAND_TYPE_IMM64
;
1896 static const i386_operand_type imm16_32
= OPERAND_TYPE_IMM16_32
;
1897 static const i386_operand_type imm16_32s
= OPERAND_TYPE_IMM16_32S
;
1898 static const i386_operand_type imm16_32_32s
= OPERAND_TYPE_IMM16_32_32S
;
1899 static const i386_operand_type vec_imm4
= OPERAND_TYPE_VEC_IMM4
;
1910 operand_type_check (i386_operand_type t
, enum operand_type c
)
1915 return t
.bitfield
.reg
;
1918 return (t
.bitfield
.imm8
1922 || t
.bitfield
.imm32s
1923 || t
.bitfield
.imm64
);
1926 return (t
.bitfield
.disp8
1927 || t
.bitfield
.disp16
1928 || t
.bitfield
.disp32
1929 || t
.bitfield
.disp32s
1930 || t
.bitfield
.disp64
);
1933 return (t
.bitfield
.disp8
1934 || t
.bitfield
.disp16
1935 || t
.bitfield
.disp32
1936 || t
.bitfield
.disp32s
1937 || t
.bitfield
.disp64
1938 || t
.bitfield
.baseindex
);
1947 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit/80bit size
1948 between operand GIVEN and opeand WANTED for instruction template T. */
1951 match_operand_size (const insn_template
*t
, unsigned int wanted
,
1954 return !((i
.types
[given
].bitfield
.byte
1955 && !t
->operand_types
[wanted
].bitfield
.byte
)
1956 || (i
.types
[given
].bitfield
.word
1957 && !t
->operand_types
[wanted
].bitfield
.word
)
1958 || (i
.types
[given
].bitfield
.dword
1959 && !t
->operand_types
[wanted
].bitfield
.dword
)
1960 || (i
.types
[given
].bitfield
.qword
1961 && !t
->operand_types
[wanted
].bitfield
.qword
)
1962 || (i
.types
[given
].bitfield
.tbyte
1963 && !t
->operand_types
[wanted
].bitfield
.tbyte
));
1966 /* Return 1 if there is no conflict in SIMD register between operand
1967 GIVEN and opeand WANTED for instruction template T. */
1970 match_simd_size (const insn_template
*t
, unsigned int wanted
,
1973 return !((i
.types
[given
].bitfield
.xmmword
1974 && !t
->operand_types
[wanted
].bitfield
.xmmword
)
1975 || (i
.types
[given
].bitfield
.ymmword
1976 && !t
->operand_types
[wanted
].bitfield
.ymmword
)
1977 || (i
.types
[given
].bitfield
.zmmword
1978 && !t
->operand_types
[wanted
].bitfield
.zmmword
));
1981 /* Return 1 if there is no conflict in any size between operand GIVEN
1982 and opeand WANTED for instruction template T. */
1985 match_mem_size (const insn_template
*t
, unsigned int wanted
,
1988 return (match_operand_size (t
, wanted
, given
)
1989 && !((i
.types
[given
].bitfield
.unspecified
1991 && !t
->operand_types
[wanted
].bitfield
.unspecified
)
1992 || (i
.types
[given
].bitfield
.fword
1993 && !t
->operand_types
[wanted
].bitfield
.fword
)
1994 /* For scalar opcode templates to allow register and memory
1995 operands at the same time, some special casing is needed
1996 here. Also for v{,p}broadcast*, {,v}pmov{s,z}*, and
1997 down-conversion vpmov*. */
1998 || ((t
->operand_types
[wanted
].bitfield
.regsimd
1999 && !t
->opcode_modifier
.broadcast
2000 && (t
->operand_types
[wanted
].bitfield
.byte
2001 || t
->operand_types
[wanted
].bitfield
.word
2002 || t
->operand_types
[wanted
].bitfield
.dword
2003 || t
->operand_types
[wanted
].bitfield
.qword
))
2004 ? (i
.types
[given
].bitfield
.xmmword
2005 || i
.types
[given
].bitfield
.ymmword
2006 || i
.types
[given
].bitfield
.zmmword
)
2007 : !match_simd_size(t
, wanted
, given
))));
2010 /* Return value has MATCH_STRAIGHT set if there is no size conflict on any
2011 operands for instruction template T, and it has MATCH_REVERSE set if there
2012 is no size conflict on any operands for the template with operands reversed
2013 (and the template allows for reversing in the first place). */
2015 #define MATCH_STRAIGHT 1
2016 #define MATCH_REVERSE 2
2018 static INLINE
unsigned int
2019 operand_size_match (const insn_template
*t
)
2021 unsigned int j
, match
= MATCH_STRAIGHT
;
2023 /* Don't check jump instructions. */
2024 if (t
->opcode_modifier
.jump
2025 || t
->opcode_modifier
.jumpbyte
2026 || t
->opcode_modifier
.jumpdword
2027 || t
->opcode_modifier
.jumpintersegment
)
2030 /* Check memory and accumulator operand size. */
2031 for (j
= 0; j
< i
.operands
; j
++)
2033 if (!i
.types
[j
].bitfield
.reg
&& !i
.types
[j
].bitfield
.regsimd
2034 && t
->operand_types
[j
].bitfield
.anysize
)
2037 if (t
->operand_types
[j
].bitfield
.reg
2038 && !match_operand_size (t
, j
, j
))
2044 if (t
->operand_types
[j
].bitfield
.regsimd
2045 && !match_simd_size (t
, j
, j
))
2051 if (t
->operand_types
[j
].bitfield
.acc
2052 && (!match_operand_size (t
, j
, j
) || !match_simd_size (t
, j
, j
)))
2058 if ((i
.flags
[j
] & Operand_Mem
) && !match_mem_size (t
, j
, j
))
2065 if (!t
->opcode_modifier
.d
)
2069 i
.error
= operand_size_mismatch
;
2073 /* Check reverse. */
2074 gas_assert (i
.operands
>= 2 && i
.operands
<= 3);
2076 for (j
= 0; j
< i
.operands
; j
++)
2078 unsigned int given
= i
.operands
- j
- 1;
2080 if (t
->operand_types
[j
].bitfield
.reg
2081 && !match_operand_size (t
, j
, given
))
2084 if (t
->operand_types
[j
].bitfield
.regsimd
2085 && !match_simd_size (t
, j
, given
))
2088 if (t
->operand_types
[j
].bitfield
.acc
2089 && (!match_operand_size (t
, j
, given
)
2090 || !match_simd_size (t
, j
, given
)))
2093 if ((i
.flags
[given
] & Operand_Mem
) && !match_mem_size (t
, j
, given
))
2097 return match
| MATCH_REVERSE
;
2101 operand_type_match (i386_operand_type overlap
,
2102 i386_operand_type given
)
2104 i386_operand_type temp
= overlap
;
2106 temp
.bitfield
.jumpabsolute
= 0;
2107 temp
.bitfield
.unspecified
= 0;
2108 temp
.bitfield
.byte
= 0;
2109 temp
.bitfield
.word
= 0;
2110 temp
.bitfield
.dword
= 0;
2111 temp
.bitfield
.fword
= 0;
2112 temp
.bitfield
.qword
= 0;
2113 temp
.bitfield
.tbyte
= 0;
2114 temp
.bitfield
.xmmword
= 0;
2115 temp
.bitfield
.ymmword
= 0;
2116 temp
.bitfield
.zmmword
= 0;
2117 if (operand_type_all_zero (&temp
))
2120 if (given
.bitfield
.baseindex
== overlap
.bitfield
.baseindex
2121 && given
.bitfield
.jumpabsolute
== overlap
.bitfield
.jumpabsolute
)
2125 i
.error
= operand_type_mismatch
;
2129 /* If given types g0 and g1 are registers they must be of the same type
2130 unless the expected operand type register overlap is null.
2131 Memory operand size of certain SIMD instructions is also being checked
2135 operand_type_register_match (i386_operand_type g0
,
2136 i386_operand_type t0
,
2137 i386_operand_type g1
,
2138 i386_operand_type t1
)
2140 if (!g0
.bitfield
.reg
2141 && !g0
.bitfield
.regsimd
2142 && (!operand_type_check (g0
, anymem
)
2143 || g0
.bitfield
.unspecified
2144 || !t0
.bitfield
.regsimd
))
2147 if (!g1
.bitfield
.reg
2148 && !g1
.bitfield
.regsimd
2149 && (!operand_type_check (g1
, anymem
)
2150 || g1
.bitfield
.unspecified
2151 || !t1
.bitfield
.regsimd
))
2154 if (g0
.bitfield
.byte
== g1
.bitfield
.byte
2155 && g0
.bitfield
.word
== g1
.bitfield
.word
2156 && g0
.bitfield
.dword
== g1
.bitfield
.dword
2157 && g0
.bitfield
.qword
== g1
.bitfield
.qword
2158 && g0
.bitfield
.xmmword
== g1
.bitfield
.xmmword
2159 && g0
.bitfield
.ymmword
== g1
.bitfield
.ymmword
2160 && g0
.bitfield
.zmmword
== g1
.bitfield
.zmmword
)
2163 if (!(t0
.bitfield
.byte
& t1
.bitfield
.byte
)
2164 && !(t0
.bitfield
.word
& t1
.bitfield
.word
)
2165 && !(t0
.bitfield
.dword
& t1
.bitfield
.dword
)
2166 && !(t0
.bitfield
.qword
& t1
.bitfield
.qword
)
2167 && !(t0
.bitfield
.xmmword
& t1
.bitfield
.xmmword
)
2168 && !(t0
.bitfield
.ymmword
& t1
.bitfield
.ymmword
)
2169 && !(t0
.bitfield
.zmmword
& t1
.bitfield
.zmmword
))
2172 i
.error
= register_type_mismatch
;
2177 static INLINE
unsigned int
2178 register_number (const reg_entry
*r
)
2180 unsigned int nr
= r
->reg_num
;
2182 if (r
->reg_flags
& RegRex
)
2185 if (r
->reg_flags
& RegVRex
)
2191 static INLINE
unsigned int
2192 mode_from_disp_size (i386_operand_type t
)
2194 if (t
.bitfield
.disp8
)
2196 else if (t
.bitfield
.disp16
2197 || t
.bitfield
.disp32
2198 || t
.bitfield
.disp32s
)
2205 fits_in_signed_byte (addressT num
)
2207 return num
+ 0x80 <= 0xff;
2211 fits_in_unsigned_byte (addressT num
)
2217 fits_in_unsigned_word (addressT num
)
2219 return num
<= 0xffff;
2223 fits_in_signed_word (addressT num
)
2225 return num
+ 0x8000 <= 0xffff;
2229 fits_in_signed_long (addressT num ATTRIBUTE_UNUSED
)
2234 return num
+ 0x80000000 <= 0xffffffff;
2236 } /* fits_in_signed_long() */
2239 fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED
)
2244 return num
<= 0xffffffff;
2246 } /* fits_in_unsigned_long() */
2249 fits_in_disp8 (offsetT num
)
2251 int shift
= i
.memshift
;
2257 mask
= (1 << shift
) - 1;
2259 /* Return 0 if NUM isn't properly aligned. */
2263 /* Check if NUM will fit in 8bit after shift. */
2264 return fits_in_signed_byte (num
>> shift
);
2268 fits_in_imm4 (offsetT num
)
2270 return (num
& 0xf) == num
;
2273 static i386_operand_type
2274 smallest_imm_type (offsetT num
)
2276 i386_operand_type t
;
2278 operand_type_set (&t
, 0);
2279 t
.bitfield
.imm64
= 1;
2281 if (cpu_arch_tune
!= PROCESSOR_I486
&& num
== 1)
2283 /* This code is disabled on the 486 because all the Imm1 forms
2284 in the opcode table are slower on the i486. They're the
2285 versions with the implicitly specified single-position
2286 displacement, which has another syntax if you really want to
2288 t
.bitfield
.imm1
= 1;
2289 t
.bitfield
.imm8
= 1;
2290 t
.bitfield
.imm8s
= 1;
2291 t
.bitfield
.imm16
= 1;
2292 t
.bitfield
.imm32
= 1;
2293 t
.bitfield
.imm32s
= 1;
2295 else if (fits_in_signed_byte (num
))
2297 t
.bitfield
.imm8
= 1;
2298 t
.bitfield
.imm8s
= 1;
2299 t
.bitfield
.imm16
= 1;
2300 t
.bitfield
.imm32
= 1;
2301 t
.bitfield
.imm32s
= 1;
2303 else if (fits_in_unsigned_byte (num
))
2305 t
.bitfield
.imm8
= 1;
2306 t
.bitfield
.imm16
= 1;
2307 t
.bitfield
.imm32
= 1;
2308 t
.bitfield
.imm32s
= 1;
2310 else if (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
2312 t
.bitfield
.imm16
= 1;
2313 t
.bitfield
.imm32
= 1;
2314 t
.bitfield
.imm32s
= 1;
2316 else if (fits_in_signed_long (num
))
2318 t
.bitfield
.imm32
= 1;
2319 t
.bitfield
.imm32s
= 1;
2321 else if (fits_in_unsigned_long (num
))
2322 t
.bitfield
.imm32
= 1;
2328 offset_in_range (offsetT val
, int size
)
2334 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
2335 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
2336 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
2338 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
2344 /* If BFD64, sign extend val for 32bit address mode. */
2345 if (flag_code
!= CODE_64BIT
2346 || i
.prefix
[ADDR_PREFIX
])
2347 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
2348 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
2351 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
2353 char buf1
[40], buf2
[40];
2355 sprint_value (buf1
, val
);
2356 sprint_value (buf2
, val
& mask
);
2357 as_warn (_("%s shortened to %s"), buf1
, buf2
);
2372 a. PREFIX_EXIST if attempting to add a prefix where one from the
2373 same class already exists.
2374 b. PREFIX_LOCK if lock prefix is added.
2375 c. PREFIX_REP if rep/repne prefix is added.
2376 d. PREFIX_DS if ds prefix is added.
2377 e. PREFIX_OTHER if other prefix is added.
2380 static enum PREFIX_GROUP
2381 add_prefix (unsigned int prefix
)
2383 enum PREFIX_GROUP ret
= PREFIX_OTHER
;
2386 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
2387 && flag_code
== CODE_64BIT
)
2389 if ((i
.prefix
[REX_PREFIX
] & prefix
& REX_W
)
2390 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_R
)
2391 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_X
)
2392 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_B
))
2403 case DS_PREFIX_OPCODE
:
2406 case CS_PREFIX_OPCODE
:
2407 case ES_PREFIX_OPCODE
:
2408 case FS_PREFIX_OPCODE
:
2409 case GS_PREFIX_OPCODE
:
2410 case SS_PREFIX_OPCODE
:
2414 case REPNE_PREFIX_OPCODE
:
2415 case REPE_PREFIX_OPCODE
:
2420 case LOCK_PREFIX_OPCODE
:
2429 case ADDR_PREFIX_OPCODE
:
2433 case DATA_PREFIX_OPCODE
:
2437 if (i
.prefix
[q
] != 0)
2445 i
.prefix
[q
] |= prefix
;
2448 as_bad (_("same type of prefix used twice"));
2454 update_code_flag (int value
, int check
)
2456 PRINTF_LIKE ((*as_error
));
2458 flag_code
= (enum flag_code
) value
;
2459 if (flag_code
== CODE_64BIT
)
2461 cpu_arch_flags
.bitfield
.cpu64
= 1;
2462 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2466 cpu_arch_flags
.bitfield
.cpu64
= 0;
2467 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2469 if (value
== CODE_64BIT
&& !cpu_arch_flags
.bitfield
.cpulm
)
2472 as_error
= as_fatal
;
2475 (*as_error
) (_("64bit mode not supported on `%s'."),
2476 cpu_arch_name
? cpu_arch_name
: default_arch
);
2478 if (value
== CODE_32BIT
&& !cpu_arch_flags
.bitfield
.cpui386
)
2481 as_error
= as_fatal
;
2484 (*as_error
) (_("32bit mode not supported on `%s'."),
2485 cpu_arch_name
? cpu_arch_name
: default_arch
);
2487 stackop_size
= '\0';
2491 set_code_flag (int value
)
2493 update_code_flag (value
, 0);
2497 set_16bit_gcc_code_flag (int new_code_flag
)
2499 flag_code
= (enum flag_code
) new_code_flag
;
2500 if (flag_code
!= CODE_16BIT
)
2502 cpu_arch_flags
.bitfield
.cpu64
= 0;
2503 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2504 stackop_size
= LONG_MNEM_SUFFIX
;
2508 set_intel_syntax (int syntax_flag
)
2510 /* Find out if register prefixing is specified. */
2511 int ask_naked_reg
= 0;
2514 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2517 int e
= get_symbol_name (&string
);
2519 if (strcmp (string
, "prefix") == 0)
2521 else if (strcmp (string
, "noprefix") == 0)
2524 as_bad (_("bad argument to syntax directive."));
2525 (void) restore_line_pointer (e
);
2527 demand_empty_rest_of_line ();
2529 intel_syntax
= syntax_flag
;
2531 if (ask_naked_reg
== 0)
2532 allow_naked_reg
= (intel_syntax
2533 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
2535 allow_naked_reg
= (ask_naked_reg
< 0);
2537 expr_set_rank (O_full_ptr
, syntax_flag
? 10 : 0);
2539 identifier_chars
['%'] = intel_syntax
&& allow_naked_reg
? '%' : 0;
2540 identifier_chars
['$'] = intel_syntax
? '$' : 0;
2541 register_prefix
= allow_naked_reg
? "" : "%";
2545 set_intel_mnemonic (int mnemonic_flag
)
2547 intel_mnemonic
= mnemonic_flag
;
2551 set_allow_index_reg (int flag
)
2553 allow_index_reg
= flag
;
2557 set_check (int what
)
2559 enum check_kind
*kind
;
2564 kind
= &operand_check
;
2575 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2578 int e
= get_symbol_name (&string
);
2580 if (strcmp (string
, "none") == 0)
2582 else if (strcmp (string
, "warning") == 0)
2583 *kind
= check_warning
;
2584 else if (strcmp (string
, "error") == 0)
2585 *kind
= check_error
;
2587 as_bad (_("bad argument to %s_check directive."), str
);
2588 (void) restore_line_pointer (e
);
2591 as_bad (_("missing argument for %s_check directive"), str
);
2593 demand_empty_rest_of_line ();
2597 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED
,
2598 i386_cpu_flags new_flag ATTRIBUTE_UNUSED
)
2600 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2601 static const char *arch
;
2603 /* Intel LIOM is only supported on ELF. */
2609 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2610 use default_arch. */
2611 arch
= cpu_arch_name
;
2613 arch
= default_arch
;
2616 /* If we are targeting Intel MCU, we must enable it. */
2617 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_IAMCU
2618 || new_flag
.bitfield
.cpuiamcu
)
2621 /* If we are targeting Intel L1OM, we must enable it. */
2622 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_L1OM
2623 || new_flag
.bitfield
.cpul1om
)
2626 /* If we are targeting Intel K1OM, we must enable it. */
2627 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_K1OM
2628 || new_flag
.bitfield
.cpuk1om
)
2631 as_bad (_("`%s' is not supported on `%s'"), name
, arch
);
2636 set_cpu_arch (int dummy ATTRIBUTE_UNUSED
)
2640 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2643 int e
= get_symbol_name (&string
);
2645 i386_cpu_flags flags
;
2647 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
2649 if (strcmp (string
, cpu_arch
[j
].name
) == 0)
2651 check_cpu_arch_compatible (string
, cpu_arch
[j
].flags
);
2655 cpu_arch_name
= cpu_arch
[j
].name
;
2656 cpu_sub_arch_name
= NULL
;
2657 cpu_arch_flags
= cpu_arch
[j
].flags
;
2658 if (flag_code
== CODE_64BIT
)
2660 cpu_arch_flags
.bitfield
.cpu64
= 1;
2661 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2665 cpu_arch_flags
.bitfield
.cpu64
= 0;
2666 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2668 cpu_arch_isa
= cpu_arch
[j
].type
;
2669 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
2670 if (!cpu_arch_tune_set
)
2672 cpu_arch_tune
= cpu_arch_isa
;
2673 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
2678 flags
= cpu_flags_or (cpu_arch_flags
,
2681 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2683 if (cpu_sub_arch_name
)
2685 char *name
= cpu_sub_arch_name
;
2686 cpu_sub_arch_name
= concat (name
,
2688 (const char *) NULL
);
2692 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
2693 cpu_arch_flags
= flags
;
2694 cpu_arch_isa_flags
= flags
;
2698 = cpu_flags_or (cpu_arch_isa_flags
,
2700 (void) restore_line_pointer (e
);
2701 demand_empty_rest_of_line ();
2706 if (*string
== '.' && j
>= ARRAY_SIZE (cpu_arch
))
2708 /* Disable an ISA extension. */
2709 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
2710 if (strcmp (string
+ 1, cpu_noarch
[j
].name
) == 0)
2712 flags
= cpu_flags_and_not (cpu_arch_flags
,
2713 cpu_noarch
[j
].flags
);
2714 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2716 if (cpu_sub_arch_name
)
2718 char *name
= cpu_sub_arch_name
;
2719 cpu_sub_arch_name
= concat (name
, string
,
2720 (const char *) NULL
);
2724 cpu_sub_arch_name
= xstrdup (string
);
2725 cpu_arch_flags
= flags
;
2726 cpu_arch_isa_flags
= flags
;
2728 (void) restore_line_pointer (e
);
2729 demand_empty_rest_of_line ();
2733 j
= ARRAY_SIZE (cpu_arch
);
2736 if (j
>= ARRAY_SIZE (cpu_arch
))
2737 as_bad (_("no such architecture: `%s'"), string
);
2739 *input_line_pointer
= e
;
2742 as_bad (_("missing cpu architecture"));
2744 no_cond_jump_promotion
= 0;
2745 if (*input_line_pointer
== ','
2746 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
2751 ++input_line_pointer
;
2752 e
= get_symbol_name (&string
);
2754 if (strcmp (string
, "nojumps") == 0)
2755 no_cond_jump_promotion
= 1;
2756 else if (strcmp (string
, "jumps") == 0)
2759 as_bad (_("no such architecture modifier: `%s'"), string
);
2761 (void) restore_line_pointer (e
);
2764 demand_empty_rest_of_line ();
2767 enum bfd_architecture
2770 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2772 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2773 || flag_code
!= CODE_64BIT
)
2774 as_fatal (_("Intel L1OM is 64bit ELF only"));
2775 return bfd_arch_l1om
;
2777 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2779 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2780 || flag_code
!= CODE_64BIT
)
2781 as_fatal (_("Intel K1OM is 64bit ELF only"));
2782 return bfd_arch_k1om
;
2784 else if (cpu_arch_isa
== PROCESSOR_IAMCU
)
2786 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2787 || flag_code
== CODE_64BIT
)
2788 as_fatal (_("Intel MCU is 32bit ELF only"));
2789 return bfd_arch_iamcu
;
2792 return bfd_arch_i386
;
2798 if (!strncmp (default_arch
, "x86_64", 6))
2800 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2802 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2803 || default_arch
[6] != '\0')
2804 as_fatal (_("Intel L1OM is 64bit ELF only"));
2805 return bfd_mach_l1om
;
2807 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2809 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2810 || default_arch
[6] != '\0')
2811 as_fatal (_("Intel K1OM is 64bit ELF only"));
2812 return bfd_mach_k1om
;
2814 else if (default_arch
[6] == '\0')
2815 return bfd_mach_x86_64
;
2817 return bfd_mach_x64_32
;
2819 else if (!strcmp (default_arch
, "i386")
2820 || !strcmp (default_arch
, "iamcu"))
2822 if (cpu_arch_isa
== PROCESSOR_IAMCU
)
2824 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
2825 as_fatal (_("Intel MCU is 32bit ELF only"));
2826 return bfd_mach_i386_iamcu
;
2829 return bfd_mach_i386_i386
;
2832 as_fatal (_("unknown architecture"));
2838 const char *hash_err
;
2840 /* Support pseudo prefixes like {disp32}. */
2841 lex_type
['{'] = LEX_BEGIN_NAME
;
2843 /* Initialize op_hash hash table. */
2844 op_hash
= hash_new ();
2847 const insn_template
*optab
;
2848 templates
*core_optab
;
2850 /* Setup for loop. */
2852 core_optab
= XNEW (templates
);
2853 core_optab
->start
= optab
;
2858 if (optab
->name
== NULL
2859 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
2861 /* different name --> ship out current template list;
2862 add to hash table; & begin anew. */
2863 core_optab
->end
= optab
;
2864 hash_err
= hash_insert (op_hash
,
2866 (void *) core_optab
);
2869 as_fatal (_("can't hash %s: %s"),
2873 if (optab
->name
== NULL
)
2875 core_optab
= XNEW (templates
);
2876 core_optab
->start
= optab
;
2881 /* Initialize reg_hash hash table. */
2882 reg_hash
= hash_new ();
2884 const reg_entry
*regtab
;
2885 unsigned int regtab_size
= i386_regtab_size
;
2887 for (regtab
= i386_regtab
; regtab_size
--; regtab
++)
2889 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (void *) regtab
);
2891 as_fatal (_("can't hash %s: %s"),
2897 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
2902 for (c
= 0; c
< 256; c
++)
2907 mnemonic_chars
[c
] = c
;
2908 register_chars
[c
] = c
;
2909 operand_chars
[c
] = c
;
2911 else if (ISLOWER (c
))
2913 mnemonic_chars
[c
] = c
;
2914 register_chars
[c
] = c
;
2915 operand_chars
[c
] = c
;
2917 else if (ISUPPER (c
))
2919 mnemonic_chars
[c
] = TOLOWER (c
);
2920 register_chars
[c
] = mnemonic_chars
[c
];
2921 operand_chars
[c
] = c
;
2923 else if (c
== '{' || c
== '}')
2925 mnemonic_chars
[c
] = c
;
2926 operand_chars
[c
] = c
;
2929 if (ISALPHA (c
) || ISDIGIT (c
))
2930 identifier_chars
[c
] = c
;
2933 identifier_chars
[c
] = c
;
2934 operand_chars
[c
] = c
;
2939 identifier_chars
['@'] = '@';
2942 identifier_chars
['?'] = '?';
2943 operand_chars
['?'] = '?';
2945 digit_chars
['-'] = '-';
2946 mnemonic_chars
['_'] = '_';
2947 mnemonic_chars
['-'] = '-';
2948 mnemonic_chars
['.'] = '.';
2949 identifier_chars
['_'] = '_';
2950 identifier_chars
['.'] = '.';
2952 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
2953 operand_chars
[(unsigned char) *p
] = *p
;
2956 if (flag_code
== CODE_64BIT
)
2958 #if defined (OBJ_COFF) && defined (TE_PE)
2959 x86_dwarf2_return_column
= (OUTPUT_FLAVOR
== bfd_target_coff_flavour
2962 x86_dwarf2_return_column
= 16;
2964 x86_cie_data_alignment
= -8;
2968 x86_dwarf2_return_column
= 8;
2969 x86_cie_data_alignment
= -4;
2974 i386_print_statistics (FILE *file
)
2976 hash_print_statistics (file
, "i386 opcode", op_hash
);
2977 hash_print_statistics (file
, "i386 register", reg_hash
);
2982 /* Debugging routines for md_assemble. */
2983 static void pte (insn_template
*);
2984 static void pt (i386_operand_type
);
2985 static void pe (expressionS
*);
2986 static void ps (symbolS
*);
2989 pi (char *line
, i386_insn
*x
)
2993 fprintf (stdout
, "%s: template ", line
);
2995 fprintf (stdout
, " address: base %s index %s scale %x\n",
2996 x
->base_reg
? x
->base_reg
->reg_name
: "none",
2997 x
->index_reg
? x
->index_reg
->reg_name
: "none",
2998 x
->log2_scale_factor
);
2999 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
3000 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
3001 fprintf (stdout
, " sib: base %x index %x scale %x\n",
3002 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
3003 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
3004 (x
->rex
& REX_W
) != 0,
3005 (x
->rex
& REX_R
) != 0,
3006 (x
->rex
& REX_X
) != 0,
3007 (x
->rex
& REX_B
) != 0);
3008 for (j
= 0; j
< x
->operands
; j
++)
3010 fprintf (stdout
, " #%d: ", j
+ 1);
3012 fprintf (stdout
, "\n");
3013 if (x
->types
[j
].bitfield
.reg
3014 || x
->types
[j
].bitfield
.regmmx
3015 || x
->types
[j
].bitfield
.regsimd
3016 || x
->types
[j
].bitfield
.sreg2
3017 || x
->types
[j
].bitfield
.sreg3
3018 || x
->types
[j
].bitfield
.control
3019 || x
->types
[j
].bitfield
.debug
3020 || x
->types
[j
].bitfield
.test
)
3021 fprintf (stdout
, "%s\n", x
->op
[j
].regs
->reg_name
);
3022 if (operand_type_check (x
->types
[j
], imm
))
3024 if (operand_type_check (x
->types
[j
], disp
))
3025 pe (x
->op
[j
].disps
);
3030 pte (insn_template
*t
)
3033 fprintf (stdout
, " %d operands ", t
->operands
);
3034 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
3035 if (t
->extension_opcode
!= None
)
3036 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
3037 if (t
->opcode_modifier
.d
)
3038 fprintf (stdout
, "D");
3039 if (t
->opcode_modifier
.w
)
3040 fprintf (stdout
, "W");
3041 fprintf (stdout
, "\n");
3042 for (j
= 0; j
< t
->operands
; j
++)
3044 fprintf (stdout
, " #%d type ", j
+ 1);
3045 pt (t
->operand_types
[j
]);
3046 fprintf (stdout
, "\n");
3053 fprintf (stdout
, " operation %d\n", e
->X_op
);
3054 fprintf (stdout
, " add_number %ld (%lx)\n",
3055 (long) e
->X_add_number
, (long) e
->X_add_number
);
3056 if (e
->X_add_symbol
)
3058 fprintf (stdout
, " add_symbol ");
3059 ps (e
->X_add_symbol
);
3060 fprintf (stdout
, "\n");
3064 fprintf (stdout
, " op_symbol ");
3065 ps (e
->X_op_symbol
);
3066 fprintf (stdout
, "\n");
3073 fprintf (stdout
, "%s type %s%s",
3075 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
3076 segment_name (S_GET_SEGMENT (s
)));
3079 static struct type_name
3081 i386_operand_type mask
;
3084 const type_names
[] =
3086 { OPERAND_TYPE_REG8
, "r8" },
3087 { OPERAND_TYPE_REG16
, "r16" },
3088 { OPERAND_TYPE_REG32
, "r32" },
3089 { OPERAND_TYPE_REG64
, "r64" },
3090 { OPERAND_TYPE_IMM8
, "i8" },
3091 { OPERAND_TYPE_IMM8
, "i8s" },
3092 { OPERAND_TYPE_IMM16
, "i16" },
3093 { OPERAND_TYPE_IMM32
, "i32" },
3094 { OPERAND_TYPE_IMM32S
, "i32s" },
3095 { OPERAND_TYPE_IMM64
, "i64" },
3096 { OPERAND_TYPE_IMM1
, "i1" },
3097 { OPERAND_TYPE_BASEINDEX
, "BaseIndex" },
3098 { OPERAND_TYPE_DISP8
, "d8" },
3099 { OPERAND_TYPE_DISP16
, "d16" },
3100 { OPERAND_TYPE_DISP32
, "d32" },
3101 { OPERAND_TYPE_DISP32S
, "d32s" },
3102 { OPERAND_TYPE_DISP64
, "d64" },
3103 { OPERAND_TYPE_INOUTPORTREG
, "InOutPortReg" },
3104 { OPERAND_TYPE_SHIFTCOUNT
, "ShiftCount" },
3105 { OPERAND_TYPE_CONTROL
, "control reg" },
3106 { OPERAND_TYPE_TEST
, "test reg" },
3107 { OPERAND_TYPE_DEBUG
, "debug reg" },
3108 { OPERAND_TYPE_FLOATREG
, "FReg" },
3109 { OPERAND_TYPE_FLOATACC
, "FAcc" },
3110 { OPERAND_TYPE_SREG2
, "SReg2" },
3111 { OPERAND_TYPE_SREG3
, "SReg3" },
3112 { OPERAND_TYPE_ACC
, "Acc" },
3113 { OPERAND_TYPE_JUMPABSOLUTE
, "Jump Absolute" },
3114 { OPERAND_TYPE_REGMMX
, "rMMX" },
3115 { OPERAND_TYPE_REGXMM
, "rXMM" },
3116 { OPERAND_TYPE_REGYMM
, "rYMM" },
3117 { OPERAND_TYPE_REGZMM
, "rZMM" },
3118 { OPERAND_TYPE_REGMASK
, "Mask reg" },
3119 { OPERAND_TYPE_ESSEG
, "es" },
3123 pt (i386_operand_type t
)
3126 i386_operand_type a
;
3128 for (j
= 0; j
< ARRAY_SIZE (type_names
); j
++)
3130 a
= operand_type_and (t
, type_names
[j
].mask
);
3131 if (!operand_type_all_zero (&a
))
3132 fprintf (stdout
, "%s, ", type_names
[j
].name
);
3137 #endif /* DEBUG386 */
3139 static bfd_reloc_code_real_type
3140 reloc (unsigned int size
,
3143 bfd_reloc_code_real_type other
)
3145 if (other
!= NO_RELOC
)
3147 reloc_howto_type
*rel
;
3152 case BFD_RELOC_X86_64_GOT32
:
3153 return BFD_RELOC_X86_64_GOT64
;
3155 case BFD_RELOC_X86_64_GOTPLT64
:
3156 return BFD_RELOC_X86_64_GOTPLT64
;
3158 case BFD_RELOC_X86_64_PLTOFF64
:
3159 return BFD_RELOC_X86_64_PLTOFF64
;
3161 case BFD_RELOC_X86_64_GOTPC32
:
3162 other
= BFD_RELOC_X86_64_GOTPC64
;
3164 case BFD_RELOC_X86_64_GOTPCREL
:
3165 other
= BFD_RELOC_X86_64_GOTPCREL64
;
3167 case BFD_RELOC_X86_64_TPOFF32
:
3168 other
= BFD_RELOC_X86_64_TPOFF64
;
3170 case BFD_RELOC_X86_64_DTPOFF32
:
3171 other
= BFD_RELOC_X86_64_DTPOFF64
;
3177 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3178 if (other
== BFD_RELOC_SIZE32
)
3181 other
= BFD_RELOC_SIZE64
;
3184 as_bad (_("there are no pc-relative size relocations"));
3190 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
3191 if (size
== 4 && (flag_code
!= CODE_64BIT
|| disallow_64bit_reloc
))
3194 rel
= bfd_reloc_type_lookup (stdoutput
, other
);
3196 as_bad (_("unknown relocation (%u)"), other
);
3197 else if (size
!= bfd_get_reloc_size (rel
))
3198 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
3199 bfd_get_reloc_size (rel
),
3201 else if (pcrel
&& !rel
->pc_relative
)
3202 as_bad (_("non-pc-relative relocation for pc-relative field"));
3203 else if ((rel
->complain_on_overflow
== complain_overflow_signed
3205 || (rel
->complain_on_overflow
== complain_overflow_unsigned
3207 as_bad (_("relocated field and relocation type differ in signedness"));
3216 as_bad (_("there are no unsigned pc-relative relocations"));
3219 case 1: return BFD_RELOC_8_PCREL
;
3220 case 2: return BFD_RELOC_16_PCREL
;
3221 case 4: return BFD_RELOC_32_PCREL
;
3222 case 8: return BFD_RELOC_64_PCREL
;
3224 as_bad (_("cannot do %u byte pc-relative relocation"), size
);
3231 case 4: return BFD_RELOC_X86_64_32S
;
3236 case 1: return BFD_RELOC_8
;
3237 case 2: return BFD_RELOC_16
;
3238 case 4: return BFD_RELOC_32
;
3239 case 8: return BFD_RELOC_64
;
3241 as_bad (_("cannot do %s %u byte relocation"),
3242 sign
> 0 ? "signed" : "unsigned", size
);
3248 /* Here we decide which fixups can be adjusted to make them relative to
3249 the beginning of the section instead of the symbol. Basically we need
3250 to make sure that the dynamic relocations are done correctly, so in
3251 some cases we force the original symbol to be used. */
3254 tc_i386_fix_adjustable (fixS
*fixP ATTRIBUTE_UNUSED
)
3256 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3260 /* Don't adjust pc-relative references to merge sections in 64-bit
3262 if (use_rela_relocations
3263 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
3267 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
3268 and changed later by validate_fix. */
3269 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
3270 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
3273 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
3274 for size relocations. */
3275 if (fixP
->fx_r_type
== BFD_RELOC_SIZE32
3276 || fixP
->fx_r_type
== BFD_RELOC_SIZE64
3277 || fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
3278 || fixP
->fx_r_type
== BFD_RELOC_386_PLT32
3279 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
3280 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32X
3281 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
3282 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
3283 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
3284 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
3285 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
3286 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
3287 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
3288 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
3289 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTDESC
3290 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_DESC_CALL
3291 || fixP
->fx_r_type
== BFD_RELOC_X86_64_PLT32
3292 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
3293 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
3294 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCRELX
3295 || fixP
->fx_r_type
== BFD_RELOC_X86_64_REX_GOTPCRELX
3296 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
3297 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
3298 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
3299 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
3300 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
3301 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
3302 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
3303 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
3304 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPC32_TLSDESC
3305 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSDESC_CALL
3306 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
3307 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
3314 intel_float_operand (const char *mnemonic
)
3316 /* Note that the value returned is meaningful only for opcodes with (memory)
3317 operands, hence the code here is free to improperly handle opcodes that
3318 have no operands (for better performance and smaller code). */
3320 if (mnemonic
[0] != 'f')
3321 return 0; /* non-math */
3323 switch (mnemonic
[1])
3325 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
3326 the fs segment override prefix not currently handled because no
3327 call path can make opcodes without operands get here */
3329 return 2 /* integer op */;
3331 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
3332 return 3; /* fldcw/fldenv */
3335 if (mnemonic
[2] != 'o' /* fnop */)
3336 return 3; /* non-waiting control op */
3339 if (mnemonic
[2] == 's')
3340 return 3; /* frstor/frstpm */
3343 if (mnemonic
[2] == 'a')
3344 return 3; /* fsave */
3345 if (mnemonic
[2] == 't')
3347 switch (mnemonic
[3])
3349 case 'c': /* fstcw */
3350 case 'd': /* fstdw */
3351 case 'e': /* fstenv */
3352 case 's': /* fsts[gw] */
3358 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
3359 return 0; /* fxsave/fxrstor are not really math ops */
3366 /* Build the VEX prefix. */
3369 build_vex_prefix (const insn_template
*t
)
3371 unsigned int register_specifier
;
3372 unsigned int implied_prefix
;
3373 unsigned int vector_length
;
3376 /* Check register specifier. */
3377 if (i
.vex
.register_specifier
)
3379 register_specifier
=
3380 ~register_number (i
.vex
.register_specifier
) & 0xf;
3381 gas_assert ((i
.vex
.register_specifier
->reg_flags
& RegVRex
) == 0);
3384 register_specifier
= 0xf;
3386 /* Use 2-byte VEX prefix by swapping destination and source operand
3387 if there are more than 1 register operand. */
3388 if (i
.reg_operands
> 1
3389 && i
.vec_encoding
!= vex_encoding_vex3
3390 && i
.dir_encoding
== dir_encoding_default
3391 && i
.operands
== i
.reg_operands
3392 && operand_type_equal (&i
.types
[0], &i
.types
[i
.operands
- 1])
3393 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3394 && (i
.tm
.opcode_modifier
.load
|| i
.tm
.opcode_modifier
.d
)
3397 unsigned int xchg
= i
.operands
- 1;
3398 union i386_op temp_op
;
3399 i386_operand_type temp_type
;
3401 temp_type
= i
.types
[xchg
];
3402 i
.types
[xchg
] = i
.types
[0];
3403 i
.types
[0] = temp_type
;
3404 temp_op
= i
.op
[xchg
];
3405 i
.op
[xchg
] = i
.op
[0];
3408 gas_assert (i
.rm
.mode
== 3);
3412 i
.rm
.regmem
= i
.rm
.reg
;
3415 if (i
.tm
.opcode_modifier
.d
)
3416 i
.tm
.base_opcode
^= (i
.tm
.base_opcode
& 0xee) != 0x6e
3417 ? Opcode_SIMD_FloatD
: Opcode_SIMD_IntD
;
3418 else /* Use the next insn. */
3422 if (i
.tm
.opcode_modifier
.vex
== VEXScalar
)
3423 vector_length
= avxscalar
;
3424 else if (i
.tm
.opcode_modifier
.vex
== VEX256
)
3430 /* Determine vector length from the last multi-length vector
3433 for (op
= t
->operands
; op
--;)
3434 if (t
->operand_types
[op
].bitfield
.xmmword
3435 && t
->operand_types
[op
].bitfield
.ymmword
3436 && i
.types
[op
].bitfield
.ymmword
)
3443 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3448 case DATA_PREFIX_OPCODE
:
3451 case REPE_PREFIX_OPCODE
:
3454 case REPNE_PREFIX_OPCODE
:
3461 /* Check the REX.W bit and VEXW. */
3462 if (i
.tm
.opcode_modifier
.vexw
== VEXWIG
)
3463 w
= (vexwig
== vexw1
|| (i
.rex
& REX_W
)) ? 1 : 0;
3464 else if (i
.tm
.opcode_modifier
.vexw
)
3465 w
= i
.tm
.opcode_modifier
.vexw
== VEXW1
? 1 : 0;
3467 w
= (flag_code
== CODE_64BIT
? i
.rex
& REX_W
: vexwig
== vexw1
) ? 1 : 0;
3469 /* Use 2-byte VEX prefix if possible. */
3471 && i
.vec_encoding
!= vex_encoding_vex3
3472 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3473 && (i
.rex
& (REX_W
| REX_X
| REX_B
)) == 0)
3475 /* 2-byte VEX prefix. */
3479 i
.vex
.bytes
[0] = 0xc5;
3481 /* Check the REX.R bit. */
3482 r
= (i
.rex
& REX_R
) ? 0 : 1;
3483 i
.vex
.bytes
[1] = (r
<< 7
3484 | register_specifier
<< 3
3485 | vector_length
<< 2
3490 /* 3-byte VEX prefix. */
3495 switch (i
.tm
.opcode_modifier
.vexopcode
)
3499 i
.vex
.bytes
[0] = 0xc4;
3503 i
.vex
.bytes
[0] = 0xc4;
3507 i
.vex
.bytes
[0] = 0xc4;
3511 i
.vex
.bytes
[0] = 0x8f;
3515 i
.vex
.bytes
[0] = 0x8f;
3519 i
.vex
.bytes
[0] = 0x8f;
3525 /* The high 3 bits of the second VEX byte are 1's compliment
3526 of RXB bits from REX. */
3527 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3529 i
.vex
.bytes
[2] = (w
<< 7
3530 | register_specifier
<< 3
3531 | vector_length
<< 2
3536 static INLINE bfd_boolean
3537 is_evex_encoding (const insn_template
*t
)
3539 return t
->opcode_modifier
.evex
|| t
->opcode_modifier
.disp8memshift
3540 || t
->opcode_modifier
.broadcast
|| t
->opcode_modifier
.masking
3541 || t
->opcode_modifier
.staticrounding
|| t
->opcode_modifier
.sae
;
3544 static INLINE bfd_boolean
3545 is_any_vex_encoding (const insn_template
*t
)
3547 return t
->opcode_modifier
.vex
|| t
->opcode_modifier
.vexopcode
3548 || is_evex_encoding (t
);
3551 /* Build the EVEX prefix. */
3554 build_evex_prefix (void)
3556 unsigned int register_specifier
;
3557 unsigned int implied_prefix
;
3559 rex_byte vrex_used
= 0;
3561 /* Check register specifier. */
3562 if (i
.vex
.register_specifier
)
3564 gas_assert ((i
.vrex
& REX_X
) == 0);
3566 register_specifier
= i
.vex
.register_specifier
->reg_num
;
3567 if ((i
.vex
.register_specifier
->reg_flags
& RegRex
))
3568 register_specifier
+= 8;
3569 /* The upper 16 registers are encoded in the fourth byte of the
3571 if (!(i
.vex
.register_specifier
->reg_flags
& RegVRex
))
3572 i
.vex
.bytes
[3] = 0x8;
3573 register_specifier
= ~register_specifier
& 0xf;
3577 register_specifier
= 0xf;
3579 /* Encode upper 16 vector index register in the fourth byte of
3581 if (!(i
.vrex
& REX_X
))
3582 i
.vex
.bytes
[3] = 0x8;
3587 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3592 case DATA_PREFIX_OPCODE
:
3595 case REPE_PREFIX_OPCODE
:
3598 case REPNE_PREFIX_OPCODE
:
3605 /* 4 byte EVEX prefix. */
3607 i
.vex
.bytes
[0] = 0x62;
3610 switch (i
.tm
.opcode_modifier
.vexopcode
)
3626 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3628 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3630 /* The fifth bit of the second EVEX byte is 1's compliment of the
3631 REX_R bit in VREX. */
3632 if (!(i
.vrex
& REX_R
))
3633 i
.vex
.bytes
[1] |= 0x10;
3637 if ((i
.reg_operands
+ i
.imm_operands
) == i
.operands
)
3639 /* When all operands are registers, the REX_X bit in REX is not
3640 used. We reuse it to encode the upper 16 registers, which is
3641 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3642 as 1's compliment. */
3643 if ((i
.vrex
& REX_B
))
3646 i
.vex
.bytes
[1] &= ~0x40;
3650 /* EVEX instructions shouldn't need the REX prefix. */
3651 i
.vrex
&= ~vrex_used
;
3652 gas_assert (i
.vrex
== 0);
3654 /* Check the REX.W bit and VEXW. */
3655 if (i
.tm
.opcode_modifier
.vexw
== VEXWIG
)
3656 w
= (evexwig
== evexw1
|| (i
.rex
& REX_W
)) ? 1 : 0;
3657 else if (i
.tm
.opcode_modifier
.vexw
)
3658 w
= i
.tm
.opcode_modifier
.vexw
== VEXW1
? 1 : 0;
3660 w
= (flag_code
== CODE_64BIT
? i
.rex
& REX_W
: evexwig
== evexw1
) ? 1 : 0;
3662 /* Encode the U bit. */
3663 implied_prefix
|= 0x4;
3665 /* The third byte of the EVEX prefix. */
3666 i
.vex
.bytes
[2] = (w
<< 7 | register_specifier
<< 3 | implied_prefix
);
3668 /* The fourth byte of the EVEX prefix. */
3669 /* The zeroing-masking bit. */
3670 if (i
.mask
&& i
.mask
->zeroing
)
3671 i
.vex
.bytes
[3] |= 0x80;
3673 /* Don't always set the broadcast bit if there is no RC. */
3676 /* Encode the vector length. */
3677 unsigned int vec_length
;
3679 if (!i
.tm
.opcode_modifier
.evex
3680 || i
.tm
.opcode_modifier
.evex
== EVEXDYN
)
3684 /* Determine vector length from the last multi-length vector
3687 for (op
= i
.operands
; op
--;)
3688 if (i
.tm
.operand_types
[op
].bitfield
.xmmword
3689 + i
.tm
.operand_types
[op
].bitfield
.ymmword
3690 + i
.tm
.operand_types
[op
].bitfield
.zmmword
> 1)
3692 if (i
.types
[op
].bitfield
.zmmword
)
3694 i
.tm
.opcode_modifier
.evex
= EVEX512
;
3697 else if (i
.types
[op
].bitfield
.ymmword
)
3699 i
.tm
.opcode_modifier
.evex
= EVEX256
;
3702 else if (i
.types
[op
].bitfield
.xmmword
)
3704 i
.tm
.opcode_modifier
.evex
= EVEX128
;
3707 else if (i
.broadcast
&& (int) op
== i
.broadcast
->operand
)
3709 switch (i
.broadcast
->bytes
)
3712 i
.tm
.opcode_modifier
.evex
= EVEX512
;
3715 i
.tm
.opcode_modifier
.evex
= EVEX256
;
3718 i
.tm
.opcode_modifier
.evex
= EVEX128
;
3727 if (op
>= MAX_OPERANDS
)
3731 switch (i
.tm
.opcode_modifier
.evex
)
3733 case EVEXLIG
: /* LL' is ignored */
3734 vec_length
= evexlig
<< 5;
3737 vec_length
= 0 << 5;
3740 vec_length
= 1 << 5;
3743 vec_length
= 2 << 5;
3749 i
.vex
.bytes
[3] |= vec_length
;
3750 /* Encode the broadcast bit. */
3752 i
.vex
.bytes
[3] |= 0x10;
3756 if (i
.rounding
->type
!= saeonly
)
3757 i
.vex
.bytes
[3] |= 0x10 | (i
.rounding
->type
<< 5);
3759 i
.vex
.bytes
[3] |= 0x10 | (evexrcig
<< 5);
3762 if (i
.mask
&& i
.mask
->mask
)
3763 i
.vex
.bytes
[3] |= i
.mask
->mask
->reg_num
;
3767 process_immext (void)
3771 if ((i
.tm
.cpu_flags
.bitfield
.cpusse3
|| i
.tm
.cpu_flags
.bitfield
.cpusvme
)
3774 /* MONITOR/MWAIT as well as SVME instructions have fixed operands
3775 with an opcode suffix which is coded in the same place as an
3776 8-bit immediate field would be.
3777 Here we check those operands and remove them afterwards. */
3780 for (x
= 0; x
< i
.operands
; x
++)
3781 if (register_number (i
.op
[x
].regs
) != x
)
3782 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3783 register_prefix
, i
.op
[x
].regs
->reg_name
, x
+ 1,
3789 if (i
.tm
.cpu_flags
.bitfield
.cpumwaitx
&& i
.operands
> 0)
3791 /* MONITORX/MWAITX instructions have fixed operands with an opcode
3792 suffix which is coded in the same place as an 8-bit immediate
3794 Here we check those operands and remove them afterwards. */
3797 if (i
.operands
!= 3)
3800 for (x
= 0; x
< 2; x
++)
3801 if (register_number (i
.op
[x
].regs
) != x
)
3802 goto bad_register_operand
;
3804 /* Check for third operand for mwaitx/monitorx insn. */
3805 if (register_number (i
.op
[x
].regs
)
3806 != (x
+ (i
.tm
.extension_opcode
== 0xfb)))
3808 bad_register_operand
:
3809 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3810 register_prefix
, i
.op
[x
].regs
->reg_name
, x
+1,
3817 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
3818 which is coded in the same place as an 8-bit immediate field
3819 would be. Here we fake an 8-bit immediate operand from the
3820 opcode suffix stored in tm.extension_opcode.
3822 AVX instructions also use this encoding, for some of
3823 3 argument instructions. */
3825 gas_assert (i
.imm_operands
<= 1
3827 || (is_any_vex_encoding (&i
.tm
)
3828 && i
.operands
<= 4)));
3830 exp
= &im_expressions
[i
.imm_operands
++];
3831 i
.op
[i
.operands
].imms
= exp
;
3832 i
.types
[i
.operands
] = imm8
;
3834 exp
->X_op
= O_constant
;
3835 exp
->X_add_number
= i
.tm
.extension_opcode
;
3836 i
.tm
.extension_opcode
= None
;
3843 switch (i
.tm
.opcode_modifier
.hleprefixok
)
3848 as_bad (_("invalid instruction `%s' after `%s'"),
3849 i
.tm
.name
, i
.hle_prefix
);
3852 if (i
.prefix
[LOCK_PREFIX
])
3854 as_bad (_("missing `lock' with `%s'"), i
.hle_prefix
);
3858 case HLEPrefixRelease
:
3859 if (i
.prefix
[HLE_PREFIX
] != XRELEASE_PREFIX_OPCODE
)
3861 as_bad (_("instruction `%s' after `xacquire' not allowed"),
3865 if (i
.mem_operands
== 0
3866 || !operand_type_check (i
.types
[i
.operands
- 1], anymem
))
3868 as_bad (_("memory destination needed for instruction `%s'"
3869 " after `xrelease'"), i
.tm
.name
);
3876 /* Try the shortest encoding by shortening operand size. */
3879 optimize_encoding (void)
3883 if (optimize_for_space
3884 && i
.reg_operands
== 1
3885 && i
.imm_operands
== 1
3886 && !i
.types
[1].bitfield
.byte
3887 && i
.op
[0].imms
->X_op
== O_constant
3888 && fits_in_imm7 (i
.op
[0].imms
->X_add_number
)
3889 && ((i
.tm
.base_opcode
== 0xa8
3890 && i
.tm
.extension_opcode
== None
)
3891 || (i
.tm
.base_opcode
== 0xf6
3892 && i
.tm
.extension_opcode
== 0x0)))
3895 test $imm7, %r64/%r32/%r16 -> test $imm7, %r8
3897 unsigned int base_regnum
= i
.op
[1].regs
->reg_num
;
3898 if (flag_code
== CODE_64BIT
|| base_regnum
< 4)
3900 i
.types
[1].bitfield
.byte
= 1;
3901 /* Ignore the suffix. */
3903 if (base_regnum
>= 4
3904 && !(i
.op
[1].regs
->reg_flags
& RegRex
))
3906 /* Handle SP, BP, SI and DI registers. */
3907 if (i
.types
[1].bitfield
.word
)
3909 else if (i
.types
[1].bitfield
.dword
)
3917 else if (flag_code
== CODE_64BIT
3918 && ((i
.types
[1].bitfield
.qword
3919 && i
.reg_operands
== 1
3920 && i
.imm_operands
== 1
3921 && i
.op
[0].imms
->X_op
== O_constant
3922 && ((i
.tm
.base_opcode
== 0xb0
3923 && i
.tm
.extension_opcode
== None
3924 && fits_in_unsigned_long (i
.op
[0].imms
->X_add_number
))
3925 || (fits_in_imm31 (i
.op
[0].imms
->X_add_number
)
3926 && (((i
.tm
.base_opcode
== 0x24
3927 || i
.tm
.base_opcode
== 0xa8)
3928 && i
.tm
.extension_opcode
== None
)
3929 || (i
.tm
.base_opcode
== 0x80
3930 && i
.tm
.extension_opcode
== 0x4)
3931 || ((i
.tm
.base_opcode
== 0xf6
3932 || i
.tm
.base_opcode
== 0xc6)
3933 && i
.tm
.extension_opcode
== 0x0)))))
3934 || (i
.types
[0].bitfield
.qword
3935 && ((i
.reg_operands
== 2
3936 && i
.op
[0].regs
== i
.op
[1].regs
3937 && ((i
.tm
.base_opcode
== 0x30
3938 || i
.tm
.base_opcode
== 0x28)
3939 && i
.tm
.extension_opcode
== None
))
3940 || (i
.reg_operands
== 1
3942 && i
.tm
.base_opcode
== 0x30
3943 && i
.tm
.extension_opcode
== None
)))))
3946 andq $imm31, %r64 -> andl $imm31, %r32
3947 testq $imm31, %r64 -> testl $imm31, %r32
3948 xorq %r64, %r64 -> xorl %r32, %r32
3949 subq %r64, %r64 -> subl %r32, %r32
3950 movq $imm31, %r64 -> movl $imm31, %r32
3951 movq $imm32, %r64 -> movl $imm32, %r32
3953 i
.tm
.opcode_modifier
.norex64
= 1;
3954 if (i
.tm
.base_opcode
== 0xb0 || i
.tm
.base_opcode
== 0xc6)
3957 movq $imm31, %r64 -> movl $imm31, %r32
3958 movq $imm32, %r64 -> movl $imm32, %r32
3960 i
.tm
.operand_types
[0].bitfield
.imm32
= 1;
3961 i
.tm
.operand_types
[0].bitfield
.imm32s
= 0;
3962 i
.tm
.operand_types
[0].bitfield
.imm64
= 0;
3963 i
.types
[0].bitfield
.imm32
= 1;
3964 i
.types
[0].bitfield
.imm32s
= 0;
3965 i
.types
[0].bitfield
.imm64
= 0;
3966 i
.types
[1].bitfield
.dword
= 1;
3967 i
.types
[1].bitfield
.qword
= 0;
3968 if (i
.tm
.base_opcode
== 0xc6)
3971 movq $imm31, %r64 -> movl $imm31, %r32
3973 i
.tm
.base_opcode
= 0xb0;
3974 i
.tm
.extension_opcode
= None
;
3975 i
.tm
.opcode_modifier
.shortform
= 1;
3976 i
.tm
.opcode_modifier
.modrm
= 0;
3980 else if (i
.reg_operands
== 3
3981 && i
.op
[0].regs
== i
.op
[1].regs
3982 && !i
.types
[2].bitfield
.xmmword
3983 && (i
.tm
.opcode_modifier
.vex
3984 || ((!i
.mask
|| i
.mask
->zeroing
)
3986 && is_evex_encoding (&i
.tm
)
3987 && (i
.vec_encoding
!= vex_encoding_evex
3988 || cpu_arch_isa_flags
.bitfield
.cpuavx512vl
3989 || i
.tm
.cpu_flags
.bitfield
.cpuavx512vl
3990 || (i
.tm
.operand_types
[2].bitfield
.zmmword
3991 && i
.types
[2].bitfield
.ymmword
))))
3992 && ((i
.tm
.base_opcode
== 0x55
3993 || i
.tm
.base_opcode
== 0x6655
3994 || i
.tm
.base_opcode
== 0x66df
3995 || i
.tm
.base_opcode
== 0x57
3996 || i
.tm
.base_opcode
== 0x6657
3997 || i
.tm
.base_opcode
== 0x66ef
3998 || i
.tm
.base_opcode
== 0x66f8
3999 || i
.tm
.base_opcode
== 0x66f9
4000 || i
.tm
.base_opcode
== 0x66fa
4001 || i
.tm
.base_opcode
== 0x66fb
4002 || i
.tm
.base_opcode
== 0x42
4003 || i
.tm
.base_opcode
== 0x6642
4004 || i
.tm
.base_opcode
== 0x47
4005 || i
.tm
.base_opcode
== 0x6647)
4006 && i
.tm
.extension_opcode
== None
))
4009 VOP, one of vandnps, vandnpd, vxorps, vxorpd, vpsubb, vpsubd,
4011 EVEX VOP %zmmM, %zmmM, %zmmN
4012 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
4013 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4014 EVEX VOP %ymmM, %ymmM, %ymmN
4015 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
4016 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4017 VEX VOP %ymmM, %ymmM, %ymmN
4018 -> VEX VOP %xmmM, %xmmM, %xmmN
4019 VOP, one of vpandn and vpxor:
4020 VEX VOP %ymmM, %ymmM, %ymmN
4021 -> VEX VOP %xmmM, %xmmM, %xmmN
4022 VOP, one of vpandnd and vpandnq:
4023 EVEX VOP %zmmM, %zmmM, %zmmN
4024 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
4025 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4026 EVEX VOP %ymmM, %ymmM, %ymmN
4027 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
4028 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4029 VOP, one of vpxord and vpxorq:
4030 EVEX VOP %zmmM, %zmmM, %zmmN
4031 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
4032 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4033 EVEX VOP %ymmM, %ymmM, %ymmN
4034 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
4035 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4036 VOP, one of kxord and kxorq:
4037 VEX VOP %kM, %kM, %kN
4038 -> VEX kxorw %kM, %kM, %kN
4039 VOP, one of kandnd and kandnq:
4040 VEX VOP %kM, %kM, %kN
4041 -> VEX kandnw %kM, %kM, %kN
4043 if (is_evex_encoding (&i
.tm
))
4045 if (i
.vec_encoding
!= vex_encoding_evex
)
4047 i
.tm
.opcode_modifier
.vex
= VEX128
;
4048 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4049 i
.tm
.opcode_modifier
.evex
= 0;
4051 else if (optimize
> 1)
4052 i
.tm
.opcode_modifier
.evex
= EVEX128
;
4056 else if (i
.tm
.operand_types
[0].bitfield
.regmask
)
4058 i
.tm
.base_opcode
&= 0xff;
4059 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4062 i
.tm
.opcode_modifier
.vex
= VEX128
;
4064 if (i
.tm
.opcode_modifier
.vex
)
4065 for (j
= 0; j
< 3; j
++)
4067 i
.types
[j
].bitfield
.xmmword
= 1;
4068 i
.types
[j
].bitfield
.ymmword
= 0;
4071 else if (i
.vec_encoding
!= vex_encoding_evex
4072 && !i
.types
[0].bitfield
.zmmword
4073 && !i
.types
[1].bitfield
.zmmword
4075 && is_evex_encoding (&i
.tm
)
4076 && ((i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0x666f
4077 || (i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0xf36f
4078 || (i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0xf26f)
4079 && i
.tm
.extension_opcode
== None
)
4082 VOP, one of vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16,
4083 vmovdqu32 and vmovdqu64:
4084 EVEX VOP %xmmM, %xmmN
4085 -> VEX vmovdqa|vmovdqu %xmmM, %xmmN (M and N < 16)
4086 EVEX VOP %ymmM, %ymmN
4087 -> VEX vmovdqa|vmovdqu %ymmM, %ymmN (M and N < 16)
4089 -> VEX vmovdqa|vmovdqu %xmmM, mem (M < 16)
4091 -> VEX vmovdqa|vmovdqu %ymmM, mem (M < 16)
4093 -> VEX mvmovdqa|vmovdquem, %xmmN (N < 16)
4095 -> VEX vmovdqa|vmovdqu mem, %ymmN (N < 16)
4097 for (j
= 0; j
< 2; j
++)
4098 if (operand_type_check (i
.types
[j
], disp
)
4099 && i
.op
[j
].disps
->X_op
== O_constant
)
4101 /* Since the VEX prefix has 2 or 3 bytes, the EVEX prefix
4102 has 4 bytes, EVEX Disp8 has 1 byte and VEX Disp32 has 4
4103 bytes, we choose EVEX Disp8 over VEX Disp32. */
4104 int evex_disp8
, vex_disp8
;
4105 unsigned int memshift
= i
.memshift
;
4106 offsetT n
= i
.op
[j
].disps
->X_add_number
;
4108 evex_disp8
= fits_in_disp8 (n
);
4110 vex_disp8
= fits_in_disp8 (n
);
4111 if (evex_disp8
!= vex_disp8
)
4113 i
.memshift
= memshift
;
4117 i
.types
[j
].bitfield
.disp8
= vex_disp8
;
4120 if ((i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0xf26f)
4121 i
.tm
.base_opcode
^= 0xf36f ^ 0xf26f;
4122 i
.tm
.opcode_modifier
.vex
4123 = i
.types
[0].bitfield
.ymmword
? VEX256
: VEX128
;
4124 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4125 i
.tm
.opcode_modifier
.evex
= 0;
4126 i
.tm
.opcode_modifier
.masking
= 0;
4127 i
.tm
.opcode_modifier
.disp8memshift
= 0;
4129 for (j
= 0; j
< 2; j
++)
4130 if (operand_type_check (i
.types
[j
], disp
)
4131 && i
.op
[j
].disps
->X_op
== O_constant
)
4133 i
.types
[j
].bitfield
.disp8
4134 = fits_in_disp8 (i
.op
[j
].disps
->X_add_number
);
4140 /* This is the guts of the machine-dependent assembler. LINE points to a
4141 machine dependent instruction. This function is supposed to emit
4142 the frags/bytes it assembles to. */
4145 md_assemble (char *line
)
4148 char mnemonic
[MAX_MNEM_SIZE
], mnem_suffix
;
4149 const insn_template
*t
;
4151 /* Initialize globals. */
4152 memset (&i
, '\0', sizeof (i
));
4153 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4154 i
.reloc
[j
] = NO_RELOC
;
4155 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
4156 memset (im_expressions
, '\0', sizeof (im_expressions
));
4157 save_stack_p
= save_stack
;
4159 /* First parse an instruction mnemonic & call i386_operand for the operands.
4160 We assume that the scrubber has arranged it so that line[0] is the valid
4161 start of a (possibly prefixed) mnemonic. */
4163 line
= parse_insn (line
, mnemonic
);
4166 mnem_suffix
= i
.suffix
;
4168 line
= parse_operands (line
, mnemonic
);
4170 xfree (i
.memop1_string
);
4171 i
.memop1_string
= NULL
;
4175 /* Now we've parsed the mnemonic into a set of templates, and have the
4176 operands at hand. */
4178 /* All intel opcodes have reversed operands except for "bound" and
4179 "enter". We also don't reverse intersegment "jmp" and "call"
4180 instructions with 2 immediate operands so that the immediate segment
4181 precedes the offset, as it does when in AT&T mode. */
4184 && (strcmp (mnemonic
, "bound") != 0)
4185 && (strcmp (mnemonic
, "invlpga") != 0)
4186 && !(operand_type_check (i
.types
[0], imm
)
4187 && operand_type_check (i
.types
[1], imm
)))
4190 /* The order of the immediates should be reversed
4191 for 2 immediates extrq and insertq instructions */
4192 if (i
.imm_operands
== 2
4193 && (strcmp (mnemonic
, "extrq") == 0
4194 || strcmp (mnemonic
, "insertq") == 0))
4195 swap_2_operands (0, 1);
4200 /* Don't optimize displacement for movabs since it only takes 64bit
4203 && i
.disp_encoding
!= disp_encoding_32bit
4204 && (flag_code
!= CODE_64BIT
4205 || strcmp (mnemonic
, "movabs") != 0))
4208 /* Next, we find a template that matches the given insn,
4209 making sure the overlap of the given operands types is consistent
4210 with the template operand types. */
4212 if (!(t
= match_template (mnem_suffix
)))
4215 if (sse_check
!= check_none
4216 && !i
.tm
.opcode_modifier
.noavx
4217 && !i
.tm
.cpu_flags
.bitfield
.cpuavx
4218 && (i
.tm
.cpu_flags
.bitfield
.cpusse
4219 || i
.tm
.cpu_flags
.bitfield
.cpusse2
4220 || i
.tm
.cpu_flags
.bitfield
.cpusse3
4221 || i
.tm
.cpu_flags
.bitfield
.cpussse3
4222 || i
.tm
.cpu_flags
.bitfield
.cpusse4_1
4223 || i
.tm
.cpu_flags
.bitfield
.cpusse4_2
4224 || i
.tm
.cpu_flags
.bitfield
.cpupclmul
4225 || i
.tm
.cpu_flags
.bitfield
.cpuaes
4226 || i
.tm
.cpu_flags
.bitfield
.cpugfni
))
4228 (sse_check
== check_warning
4230 : as_bad
) (_("SSE instruction `%s' is used"), i
.tm
.name
);
4233 /* Zap movzx and movsx suffix. The suffix has been set from
4234 "word ptr" or "byte ptr" on the source operand in Intel syntax
4235 or extracted from mnemonic in AT&T syntax. But we'll use
4236 the destination register to choose the suffix for encoding. */
4237 if ((i
.tm
.base_opcode
& ~9) == 0x0fb6)
4239 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
4240 there is no suffix, the default will be byte extension. */
4241 if (i
.reg_operands
!= 2
4244 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
4249 if (i
.tm
.opcode_modifier
.fwait
)
4250 if (!add_prefix (FWAIT_OPCODE
))
4253 /* Check if REP prefix is OK. */
4254 if (i
.rep_prefix
&& !i
.tm
.opcode_modifier
.repprefixok
)
4256 as_bad (_("invalid instruction `%s' after `%s'"),
4257 i
.tm
.name
, i
.rep_prefix
);
4261 /* Check for lock without a lockable instruction. Destination operand
4262 must be memory unless it is xchg (0x86). */
4263 if (i
.prefix
[LOCK_PREFIX
]
4264 && (!i
.tm
.opcode_modifier
.islockable
4265 || i
.mem_operands
== 0
4266 || (i
.tm
.base_opcode
!= 0x86
4267 && !operand_type_check (i
.types
[i
.operands
- 1], anymem
))))
4269 as_bad (_("expecting lockable instruction after `lock'"));
4273 /* Check for data size prefix on VEX/XOP/EVEX encoded insns. */
4274 if (i
.prefix
[DATA_PREFIX
] && is_any_vex_encoding (&i
.tm
))
4276 as_bad (_("data size prefix invalid with `%s'"), i
.tm
.name
);
4280 /* Check if HLE prefix is OK. */
4281 if (i
.hle_prefix
&& !check_hle ())
4284 /* Check BND prefix. */
4285 if (i
.bnd_prefix
&& !i
.tm
.opcode_modifier
.bndprefixok
)
4286 as_bad (_("expecting valid branch instruction after `bnd'"));
4288 /* Check NOTRACK prefix. */
4289 if (i
.notrack_prefix
&& !i
.tm
.opcode_modifier
.notrackprefixok
)
4290 as_bad (_("expecting indirect branch instruction after `notrack'"));
4292 if (i
.tm
.cpu_flags
.bitfield
.cpumpx
)
4294 if (flag_code
== CODE_64BIT
&& i
.prefix
[ADDR_PREFIX
])
4295 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
4296 else if (flag_code
!= CODE_16BIT
4297 ? i
.prefix
[ADDR_PREFIX
]
4298 : i
.mem_operands
&& !i
.prefix
[ADDR_PREFIX
])
4299 as_bad (_("16-bit address isn't allowed in MPX instructions"));
4302 /* Insert BND prefix. */
4303 if (add_bnd_prefix
&& i
.tm
.opcode_modifier
.bndprefixok
)
4305 if (!i
.prefix
[BND_PREFIX
])
4306 add_prefix (BND_PREFIX_OPCODE
);
4307 else if (i
.prefix
[BND_PREFIX
] != BND_PREFIX_OPCODE
)
4309 as_warn (_("replacing `rep'/`repe' prefix by `bnd'"));
4310 i
.prefix
[BND_PREFIX
] = BND_PREFIX_OPCODE
;
4314 /* Check string instruction segment overrides. */
4315 if (i
.tm
.opcode_modifier
.isstring
&& i
.mem_operands
!= 0)
4317 if (!check_string ())
4319 i
.disp_operands
= 0;
4322 if (optimize
&& !i
.no_optimize
&& i
.tm
.opcode_modifier
.optimize
)
4323 optimize_encoding ();
4325 if (!process_suffix ())
4328 /* Update operand types. */
4329 for (j
= 0; j
< i
.operands
; j
++)
4330 i
.types
[j
] = operand_type_and (i
.types
[j
], i
.tm
.operand_types
[j
]);
4332 /* Make still unresolved immediate matches conform to size of immediate
4333 given in i.suffix. */
4334 if (!finalize_imm ())
4337 if (i
.types
[0].bitfield
.imm1
)
4338 i
.imm_operands
= 0; /* kludge for shift insns. */
4340 /* We only need to check those implicit registers for instructions
4341 with 3 operands or less. */
4342 if (i
.operands
<= 3)
4343 for (j
= 0; j
< i
.operands
; j
++)
4344 if (i
.types
[j
].bitfield
.inoutportreg
4345 || i
.types
[j
].bitfield
.shiftcount
4346 || (i
.types
[j
].bitfield
.acc
&& !i
.types
[j
].bitfield
.xmmword
))
4349 /* ImmExt should be processed after SSE2AVX. */
4350 if (!i
.tm
.opcode_modifier
.sse2avx
4351 && i
.tm
.opcode_modifier
.immext
)
4354 /* For insns with operands there are more diddles to do to the opcode. */
4357 if (!process_operands ())
4360 else if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
4362 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
4363 as_warn (_("translating to `%sp'"), i
.tm
.name
);
4366 if (is_any_vex_encoding (&i
.tm
))
4368 if (flag_code
== CODE_16BIT
)
4370 as_bad (_("instruction `%s' isn't supported in 16-bit mode."),
4375 if (i
.tm
.opcode_modifier
.vex
)
4376 build_vex_prefix (t
);
4378 build_evex_prefix ();
4381 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
4382 instructions may define INT_OPCODE as well, so avoid this corner
4383 case for those instructions that use MODRM. */
4384 if (i
.tm
.base_opcode
== INT_OPCODE
4385 && !i
.tm
.opcode_modifier
.modrm
4386 && i
.op
[0].imms
->X_add_number
== 3)
4388 i
.tm
.base_opcode
= INT3_OPCODE
;
4392 if ((i
.tm
.opcode_modifier
.jump
4393 || i
.tm
.opcode_modifier
.jumpbyte
4394 || i
.tm
.opcode_modifier
.jumpdword
)
4395 && i
.op
[0].disps
->X_op
== O_constant
)
4397 /* Convert "jmp constant" (and "call constant") to a jump (call) to
4398 the absolute address given by the constant. Since ix86 jumps and
4399 calls are pc relative, we need to generate a reloc. */
4400 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
4401 i
.op
[0].disps
->X_op
= O_symbol
;
4404 if (i
.tm
.opcode_modifier
.rex64
)
4407 /* For 8 bit registers we need an empty rex prefix. Also if the
4408 instruction already has a prefix, we need to convert old
4409 registers to new ones. */
4411 if ((i
.types
[0].bitfield
.reg
&& i
.types
[0].bitfield
.byte
4412 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
4413 || (i
.types
[1].bitfield
.reg
&& i
.types
[1].bitfield
.byte
4414 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
4415 || (((i
.types
[0].bitfield
.reg
&& i
.types
[0].bitfield
.byte
)
4416 || (i
.types
[1].bitfield
.reg
&& i
.types
[1].bitfield
.byte
))
4421 i
.rex
|= REX_OPCODE
;
4422 for (x
= 0; x
< 2; x
++)
4424 /* Look for 8 bit operand that uses old registers. */
4425 if (i
.types
[x
].bitfield
.reg
&& i
.types
[x
].bitfield
.byte
4426 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
4428 /* In case it is "hi" register, give up. */
4429 if (i
.op
[x
].regs
->reg_num
> 3)
4430 as_bad (_("can't encode register '%s%s' in an "
4431 "instruction requiring REX prefix."),
4432 register_prefix
, i
.op
[x
].regs
->reg_name
);
4434 /* Otherwise it is equivalent to the extended register.
4435 Since the encoding doesn't change this is merely
4436 cosmetic cleanup for debug output. */
4438 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
4443 if (i
.rex
== 0 && i
.rex_encoding
)
4445 /* Check if we can add a REX_OPCODE byte. Look for 8 bit operand
4446 that uses legacy register. If it is "hi" register, don't add
4447 the REX_OPCODE byte. */
4449 for (x
= 0; x
< 2; x
++)
4450 if (i
.types
[x
].bitfield
.reg
4451 && i
.types
[x
].bitfield
.byte
4452 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0
4453 && i
.op
[x
].regs
->reg_num
> 3)
4455 i
.rex_encoding
= FALSE
;
4464 add_prefix (REX_OPCODE
| i
.rex
);
4466 /* We are ready to output the insn. */
4471 parse_insn (char *line
, char *mnemonic
)
4474 char *token_start
= l
;
4477 const insn_template
*t
;
4483 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
4488 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
4490 as_bad (_("no such instruction: `%s'"), token_start
);
4495 if (!is_space_char (*l
)
4496 && *l
!= END_OF_INSN
4498 || (*l
!= PREFIX_SEPARATOR
4501 as_bad (_("invalid character %s in mnemonic"),
4502 output_invalid (*l
));
4505 if (token_start
== l
)
4507 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
4508 as_bad (_("expecting prefix; got nothing"));
4510 as_bad (_("expecting mnemonic; got nothing"));
4514 /* Look up instruction (or prefix) via hash table. */
4515 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
4517 if (*l
!= END_OF_INSN
4518 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
4519 && current_templates
4520 && current_templates
->start
->opcode_modifier
.isprefix
)
4522 if (!cpu_flags_check_cpu64 (current_templates
->start
->cpu_flags
))
4524 as_bad ((flag_code
!= CODE_64BIT
4525 ? _("`%s' is only supported in 64-bit mode")
4526 : _("`%s' is not supported in 64-bit mode")),
4527 current_templates
->start
->name
);
4530 /* If we are in 16-bit mode, do not allow addr16 or data16.
4531 Similarly, in 32-bit mode, do not allow addr32 or data32. */
4532 if ((current_templates
->start
->opcode_modifier
.size
== SIZE16
4533 || current_templates
->start
->opcode_modifier
.size
== SIZE32
)
4534 && flag_code
!= CODE_64BIT
4535 && ((current_templates
->start
->opcode_modifier
.size
== SIZE32
)
4536 ^ (flag_code
== CODE_16BIT
)))
4538 as_bad (_("redundant %s prefix"),
4539 current_templates
->start
->name
);
4542 if (current_templates
->start
->opcode_length
== 0)
4544 /* Handle pseudo prefixes. */
4545 switch (current_templates
->start
->base_opcode
)
4549 i
.disp_encoding
= disp_encoding_8bit
;
4553 i
.disp_encoding
= disp_encoding_32bit
;
4557 i
.dir_encoding
= dir_encoding_load
;
4561 i
.dir_encoding
= dir_encoding_store
;
4565 i
.vec_encoding
= vex_encoding_vex2
;
4569 i
.vec_encoding
= vex_encoding_vex3
;
4573 i
.vec_encoding
= vex_encoding_evex
;
4577 i
.rex_encoding
= TRUE
;
4581 i
.no_optimize
= TRUE
;
4589 /* Add prefix, checking for repeated prefixes. */
4590 switch (add_prefix (current_templates
->start
->base_opcode
))
4595 if (current_templates
->start
->cpu_flags
.bitfield
.cpuibt
)
4596 i
.notrack_prefix
= current_templates
->start
->name
;
4599 if (current_templates
->start
->cpu_flags
.bitfield
.cpuhle
)
4600 i
.hle_prefix
= current_templates
->start
->name
;
4601 else if (current_templates
->start
->cpu_flags
.bitfield
.cpumpx
)
4602 i
.bnd_prefix
= current_templates
->start
->name
;
4604 i
.rep_prefix
= current_templates
->start
->name
;
4610 /* Skip past PREFIX_SEPARATOR and reset token_start. */
4617 if (!current_templates
)
4619 /* Deprecated functionality (new code should use pseudo-prefixes instead):
4620 Check if we should swap operand or force 32bit displacement in
4622 if (mnem_p
- 2 == dot_p
&& dot_p
[1] == 's')
4623 i
.dir_encoding
= dir_encoding_swap
;
4624 else if (mnem_p
- 3 == dot_p
4627 i
.disp_encoding
= disp_encoding_8bit
;
4628 else if (mnem_p
- 4 == dot_p
4632 i
.disp_encoding
= disp_encoding_32bit
;
4637 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
4640 if (!current_templates
)
4643 if (mnem_p
> mnemonic
)
4645 /* See if we can get a match by trimming off a suffix. */
4648 case WORD_MNEM_SUFFIX
:
4649 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
4650 i
.suffix
= SHORT_MNEM_SUFFIX
;
4653 case BYTE_MNEM_SUFFIX
:
4654 case QWORD_MNEM_SUFFIX
:
4655 i
.suffix
= mnem_p
[-1];
4657 current_templates
= (const templates
*) hash_find (op_hash
,
4660 case SHORT_MNEM_SUFFIX
:
4661 case LONG_MNEM_SUFFIX
:
4664 i
.suffix
= mnem_p
[-1];
4666 current_templates
= (const templates
*) hash_find (op_hash
,
4675 if (intel_float_operand (mnemonic
) == 1)
4676 i
.suffix
= SHORT_MNEM_SUFFIX
;
4678 i
.suffix
= LONG_MNEM_SUFFIX
;
4680 current_templates
= (const templates
*) hash_find (op_hash
,
4687 if (!current_templates
)
4689 as_bad (_("no such instruction: `%s'"), token_start
);
4694 if (current_templates
->start
->opcode_modifier
.jump
4695 || current_templates
->start
->opcode_modifier
.jumpbyte
)
4697 /* Check for a branch hint. We allow ",pt" and ",pn" for
4698 predict taken and predict not taken respectively.
4699 I'm not sure that branch hints actually do anything on loop
4700 and jcxz insns (JumpByte) for current Pentium4 chips. They
4701 may work in the future and it doesn't hurt to accept them
4703 if (l
[0] == ',' && l
[1] == 'p')
4707 if (!add_prefix (DS_PREFIX_OPCODE
))
4711 else if (l
[2] == 'n')
4713 if (!add_prefix (CS_PREFIX_OPCODE
))
4719 /* Any other comma loses. */
4722 as_bad (_("invalid character %s in mnemonic"),
4723 output_invalid (*l
));
4727 /* Check if instruction is supported on specified architecture. */
4729 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
4731 supported
|= cpu_flags_match (t
);
4732 if (supported
== CPU_FLAGS_PERFECT_MATCH
)
4734 if (!cpu_arch_flags
.bitfield
.cpui386
&& (flag_code
!= CODE_16BIT
))
4735 as_warn (_("use .code16 to ensure correct addressing mode"));
4741 if (!(supported
& CPU_FLAGS_64BIT_MATCH
))
4742 as_bad (flag_code
== CODE_64BIT
4743 ? _("`%s' is not supported in 64-bit mode")
4744 : _("`%s' is only supported in 64-bit mode"),
4745 current_templates
->start
->name
);
4747 as_bad (_("`%s' is not supported on `%s%s'"),
4748 current_templates
->start
->name
,
4749 cpu_arch_name
? cpu_arch_name
: default_arch
,
4750 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
4756 parse_operands (char *l
, const char *mnemonic
)
4760 /* 1 if operand is pending after ','. */
4761 unsigned int expecting_operand
= 0;
4763 /* Non-zero if operand parens not balanced. */
4764 unsigned int paren_not_balanced
;
4766 while (*l
!= END_OF_INSN
)
4768 /* Skip optional white space before operand. */
4769 if (is_space_char (*l
))
4771 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
&& *l
!= '"')
4773 as_bad (_("invalid character %s before operand %d"),
4774 output_invalid (*l
),
4778 token_start
= l
; /* After white space. */
4779 paren_not_balanced
= 0;
4780 while (paren_not_balanced
|| *l
!= ',')
4782 if (*l
== END_OF_INSN
)
4784 if (paren_not_balanced
)
4787 as_bad (_("unbalanced parenthesis in operand %d."),
4790 as_bad (_("unbalanced brackets in operand %d."),
4795 break; /* we are done */
4797 else if (!is_operand_char (*l
) && !is_space_char (*l
) && *l
!= '"')
4799 as_bad (_("invalid character %s in operand %d"),
4800 output_invalid (*l
),
4807 ++paren_not_balanced
;
4809 --paren_not_balanced
;
4814 ++paren_not_balanced
;
4816 --paren_not_balanced
;
4820 if (l
!= token_start
)
4821 { /* Yes, we've read in another operand. */
4822 unsigned int operand_ok
;
4823 this_operand
= i
.operands
++;
4824 if (i
.operands
> MAX_OPERANDS
)
4826 as_bad (_("spurious operands; (%d operands/instruction max)"),
4830 i
.types
[this_operand
].bitfield
.unspecified
= 1;
4831 /* Now parse operand adding info to 'i' as we go along. */
4832 END_STRING_AND_SAVE (l
);
4834 if (i
.mem_operands
> 1)
4836 as_bad (_("too many memory references for `%s'"),
4843 i386_intel_operand (token_start
,
4844 intel_float_operand (mnemonic
));
4846 operand_ok
= i386_att_operand (token_start
);
4848 RESTORE_END_STRING (l
);
4854 if (expecting_operand
)
4856 expecting_operand_after_comma
:
4857 as_bad (_("expecting operand after ','; got nothing"));
4862 as_bad (_("expecting operand before ','; got nothing"));
4867 /* Now *l must be either ',' or END_OF_INSN. */
4870 if (*++l
== END_OF_INSN
)
4872 /* Just skip it, if it's \n complain. */
4873 goto expecting_operand_after_comma
;
4875 expecting_operand
= 1;
4882 swap_2_operands (int xchg1
, int xchg2
)
4884 union i386_op temp_op
;
4885 i386_operand_type temp_type
;
4886 unsigned int temp_flags
;
4887 enum bfd_reloc_code_real temp_reloc
;
4889 temp_type
= i
.types
[xchg2
];
4890 i
.types
[xchg2
] = i
.types
[xchg1
];
4891 i
.types
[xchg1
] = temp_type
;
4893 temp_flags
= i
.flags
[xchg2
];
4894 i
.flags
[xchg2
] = i
.flags
[xchg1
];
4895 i
.flags
[xchg1
] = temp_flags
;
4897 temp_op
= i
.op
[xchg2
];
4898 i
.op
[xchg2
] = i
.op
[xchg1
];
4899 i
.op
[xchg1
] = temp_op
;
4901 temp_reloc
= i
.reloc
[xchg2
];
4902 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
4903 i
.reloc
[xchg1
] = temp_reloc
;
4907 if (i
.mask
->operand
== xchg1
)
4908 i
.mask
->operand
= xchg2
;
4909 else if (i
.mask
->operand
== xchg2
)
4910 i
.mask
->operand
= xchg1
;
4914 if (i
.broadcast
->operand
== xchg1
)
4915 i
.broadcast
->operand
= xchg2
;
4916 else if (i
.broadcast
->operand
== xchg2
)
4917 i
.broadcast
->operand
= xchg1
;
4921 if (i
.rounding
->operand
== xchg1
)
4922 i
.rounding
->operand
= xchg2
;
4923 else if (i
.rounding
->operand
== xchg2
)
4924 i
.rounding
->operand
= xchg1
;
4929 swap_operands (void)
4935 swap_2_operands (1, i
.operands
- 2);
4939 swap_2_operands (0, i
.operands
- 1);
4945 if (i
.mem_operands
== 2)
4947 const seg_entry
*temp_seg
;
4948 temp_seg
= i
.seg
[0];
4949 i
.seg
[0] = i
.seg
[1];
4950 i
.seg
[1] = temp_seg
;
4954 /* Try to ensure constant immediates are represented in the smallest
4959 char guess_suffix
= 0;
4963 guess_suffix
= i
.suffix
;
4964 else if (i
.reg_operands
)
4966 /* Figure out a suffix from the last register operand specified.
4967 We can't do this properly yet, ie. excluding InOutPortReg,
4968 but the following works for instructions with immediates.
4969 In any case, we can't set i.suffix yet. */
4970 for (op
= i
.operands
; --op
>= 0;)
4971 if (i
.types
[op
].bitfield
.reg
&& i
.types
[op
].bitfield
.byte
)
4973 guess_suffix
= BYTE_MNEM_SUFFIX
;
4976 else if (i
.types
[op
].bitfield
.reg
&& i
.types
[op
].bitfield
.word
)
4978 guess_suffix
= WORD_MNEM_SUFFIX
;
4981 else if (i
.types
[op
].bitfield
.reg
&& i
.types
[op
].bitfield
.dword
)
4983 guess_suffix
= LONG_MNEM_SUFFIX
;
4986 else if (i
.types
[op
].bitfield
.reg
&& i
.types
[op
].bitfield
.qword
)
4988 guess_suffix
= QWORD_MNEM_SUFFIX
;
4992 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
4993 guess_suffix
= WORD_MNEM_SUFFIX
;
4995 for (op
= i
.operands
; --op
>= 0;)
4996 if (operand_type_check (i
.types
[op
], imm
))
4998 switch (i
.op
[op
].imms
->X_op
)
5001 /* If a suffix is given, this operand may be shortened. */
5002 switch (guess_suffix
)
5004 case LONG_MNEM_SUFFIX
:
5005 i
.types
[op
].bitfield
.imm32
= 1;
5006 i
.types
[op
].bitfield
.imm64
= 1;
5008 case WORD_MNEM_SUFFIX
:
5009 i
.types
[op
].bitfield
.imm16
= 1;
5010 i
.types
[op
].bitfield
.imm32
= 1;
5011 i
.types
[op
].bitfield
.imm32s
= 1;
5012 i
.types
[op
].bitfield
.imm64
= 1;
5014 case BYTE_MNEM_SUFFIX
:
5015 i
.types
[op
].bitfield
.imm8
= 1;
5016 i
.types
[op
].bitfield
.imm8s
= 1;
5017 i
.types
[op
].bitfield
.imm16
= 1;
5018 i
.types
[op
].bitfield
.imm32
= 1;
5019 i
.types
[op
].bitfield
.imm32s
= 1;
5020 i
.types
[op
].bitfield
.imm64
= 1;
5024 /* If this operand is at most 16 bits, convert it
5025 to a signed 16 bit number before trying to see
5026 whether it will fit in an even smaller size.
5027 This allows a 16-bit operand such as $0xffe0 to
5028 be recognised as within Imm8S range. */
5029 if ((i
.types
[op
].bitfield
.imm16
)
5030 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
5032 i
.op
[op
].imms
->X_add_number
=
5033 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
5036 /* Store 32-bit immediate in 64-bit for 64-bit BFD. */
5037 if ((i
.types
[op
].bitfield
.imm32
)
5038 && ((i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1))
5041 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
5042 ^ ((offsetT
) 1 << 31))
5043 - ((offsetT
) 1 << 31));
5047 = operand_type_or (i
.types
[op
],
5048 smallest_imm_type (i
.op
[op
].imms
->X_add_number
));
5050 /* We must avoid matching of Imm32 templates when 64bit
5051 only immediate is available. */
5052 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
5053 i
.types
[op
].bitfield
.imm32
= 0;
5060 /* Symbols and expressions. */
5062 /* Convert symbolic operand to proper sizes for matching, but don't
5063 prevent matching a set of insns that only supports sizes other
5064 than those matching the insn suffix. */
5066 i386_operand_type mask
, allowed
;
5067 const insn_template
*t
;
5069 operand_type_set (&mask
, 0);
5070 operand_type_set (&allowed
, 0);
5072 for (t
= current_templates
->start
;
5073 t
< current_templates
->end
;
5075 allowed
= operand_type_or (allowed
,
5076 t
->operand_types
[op
]);
5077 switch (guess_suffix
)
5079 case QWORD_MNEM_SUFFIX
:
5080 mask
.bitfield
.imm64
= 1;
5081 mask
.bitfield
.imm32s
= 1;
5083 case LONG_MNEM_SUFFIX
:
5084 mask
.bitfield
.imm32
= 1;
5086 case WORD_MNEM_SUFFIX
:
5087 mask
.bitfield
.imm16
= 1;
5089 case BYTE_MNEM_SUFFIX
:
5090 mask
.bitfield
.imm8
= 1;
5095 allowed
= operand_type_and (mask
, allowed
);
5096 if (!operand_type_all_zero (&allowed
))
5097 i
.types
[op
] = operand_type_and (i
.types
[op
], mask
);
5104 /* Try to use the smallest displacement type too. */
5106 optimize_disp (void)
5110 for (op
= i
.operands
; --op
>= 0;)
5111 if (operand_type_check (i
.types
[op
], disp
))
5113 if (i
.op
[op
].disps
->X_op
== O_constant
)
5115 offsetT op_disp
= i
.op
[op
].disps
->X_add_number
;
5117 if (i
.types
[op
].bitfield
.disp16
5118 && (op_disp
& ~(offsetT
) 0xffff) == 0)
5120 /* If this operand is at most 16 bits, convert
5121 to a signed 16 bit number and don't use 64bit
5123 op_disp
= (((op_disp
& 0xffff) ^ 0x8000) - 0x8000);
5124 i
.types
[op
].bitfield
.disp64
= 0;
5127 /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */
5128 if (i
.types
[op
].bitfield
.disp32
5129 && (op_disp
& ~(((offsetT
) 2 << 31) - 1)) == 0)
5131 /* If this operand is at most 32 bits, convert
5132 to a signed 32 bit number and don't use 64bit
5134 op_disp
&= (((offsetT
) 2 << 31) - 1);
5135 op_disp
= (op_disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
5136 i
.types
[op
].bitfield
.disp64
= 0;
5139 if (!op_disp
&& i
.types
[op
].bitfield
.baseindex
)
5141 i
.types
[op
].bitfield
.disp8
= 0;
5142 i
.types
[op
].bitfield
.disp16
= 0;
5143 i
.types
[op
].bitfield
.disp32
= 0;
5144 i
.types
[op
].bitfield
.disp32s
= 0;
5145 i
.types
[op
].bitfield
.disp64
= 0;
5149 else if (flag_code
== CODE_64BIT
)
5151 if (fits_in_signed_long (op_disp
))
5153 i
.types
[op
].bitfield
.disp64
= 0;
5154 i
.types
[op
].bitfield
.disp32s
= 1;
5156 if (i
.prefix
[ADDR_PREFIX
]
5157 && fits_in_unsigned_long (op_disp
))
5158 i
.types
[op
].bitfield
.disp32
= 1;
5160 if ((i
.types
[op
].bitfield
.disp32
5161 || i
.types
[op
].bitfield
.disp32s
5162 || i
.types
[op
].bitfield
.disp16
)
5163 && fits_in_disp8 (op_disp
))
5164 i
.types
[op
].bitfield
.disp8
= 1;
5166 else if (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
5167 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
)
5169 fix_new_exp (frag_now
, frag_more (0) - frag_now
->fr_literal
, 0,
5170 i
.op
[op
].disps
, 0, i
.reloc
[op
]);
5171 i
.types
[op
].bitfield
.disp8
= 0;
5172 i
.types
[op
].bitfield
.disp16
= 0;
5173 i
.types
[op
].bitfield
.disp32
= 0;
5174 i
.types
[op
].bitfield
.disp32s
= 0;
5175 i
.types
[op
].bitfield
.disp64
= 0;
5178 /* We only support 64bit displacement on constants. */
5179 i
.types
[op
].bitfield
.disp64
= 0;
5183 /* Return 1 if there is a match in broadcast bytes between operand
5184 GIVEN and instruction template T. */
5187 match_broadcast_size (const insn_template
*t
, unsigned int given
)
5189 return ((t
->opcode_modifier
.broadcast
== BYTE_BROADCAST
5190 && i
.types
[given
].bitfield
.byte
)
5191 || (t
->opcode_modifier
.broadcast
== WORD_BROADCAST
5192 && i
.types
[given
].bitfield
.word
)
5193 || (t
->opcode_modifier
.broadcast
== DWORD_BROADCAST
5194 && i
.types
[given
].bitfield
.dword
)
5195 || (t
->opcode_modifier
.broadcast
== QWORD_BROADCAST
5196 && i
.types
[given
].bitfield
.qword
));
5199 /* Check if operands are valid for the instruction. */
5202 check_VecOperands (const insn_template
*t
)
5206 static const i386_cpu_flags avx512
= CPU_ANY_AVX512F_FLAGS
;
5208 /* Templates allowing for ZMMword as well as YMMword and/or XMMword for
5209 any one operand are implicity requiring AVX512VL support if the actual
5210 operand size is YMMword or XMMword. Since this function runs after
5211 template matching, there's no need to check for YMMword/XMMword in
5213 cpu
= cpu_flags_and (t
->cpu_flags
, avx512
);
5214 if (!cpu_flags_all_zero (&cpu
)
5215 && !t
->cpu_flags
.bitfield
.cpuavx512vl
5216 && !cpu_arch_flags
.bitfield
.cpuavx512vl
)
5218 for (op
= 0; op
< t
->operands
; ++op
)
5220 if (t
->operand_types
[op
].bitfield
.zmmword
5221 && (i
.types
[op
].bitfield
.ymmword
5222 || i
.types
[op
].bitfield
.xmmword
))
5224 i
.error
= unsupported
;
5230 /* Without VSIB byte, we can't have a vector register for index. */
5231 if (!t
->opcode_modifier
.vecsib
5233 && (i
.index_reg
->reg_type
.bitfield
.xmmword
5234 || i
.index_reg
->reg_type
.bitfield
.ymmword
5235 || i
.index_reg
->reg_type
.bitfield
.zmmword
))
5237 i
.error
= unsupported_vector_index_register
;
5241 /* Check if default mask is allowed. */
5242 if (t
->opcode_modifier
.nodefmask
5243 && (!i
.mask
|| i
.mask
->mask
->reg_num
== 0))
5245 i
.error
= no_default_mask
;
5249 /* For VSIB byte, we need a vector register for index, and all vector
5250 registers must be distinct. */
5251 if (t
->opcode_modifier
.vecsib
)
5254 || !((t
->opcode_modifier
.vecsib
== VecSIB128
5255 && i
.index_reg
->reg_type
.bitfield
.xmmword
)
5256 || (t
->opcode_modifier
.vecsib
== VecSIB256
5257 && i
.index_reg
->reg_type
.bitfield
.ymmword
)
5258 || (t
->opcode_modifier
.vecsib
== VecSIB512
5259 && i
.index_reg
->reg_type
.bitfield
.zmmword
)))
5261 i
.error
= invalid_vsib_address
;
5265 gas_assert (i
.reg_operands
== 2 || i
.mask
);
5266 if (i
.reg_operands
== 2 && !i
.mask
)
5268 gas_assert (i
.types
[0].bitfield
.regsimd
);
5269 gas_assert (i
.types
[0].bitfield
.xmmword
5270 || i
.types
[0].bitfield
.ymmword
);
5271 gas_assert (i
.types
[2].bitfield
.regsimd
);
5272 gas_assert (i
.types
[2].bitfield
.xmmword
5273 || i
.types
[2].bitfield
.ymmword
);
5274 if (operand_check
== check_none
)
5276 if (register_number (i
.op
[0].regs
)
5277 != register_number (i
.index_reg
)
5278 && register_number (i
.op
[2].regs
)
5279 != register_number (i
.index_reg
)
5280 && register_number (i
.op
[0].regs
)
5281 != register_number (i
.op
[2].regs
))
5283 if (operand_check
== check_error
)
5285 i
.error
= invalid_vector_register_set
;
5288 as_warn (_("mask, index, and destination registers should be distinct"));
5290 else if (i
.reg_operands
== 1 && i
.mask
)
5292 if (i
.types
[1].bitfield
.regsimd
5293 && (i
.types
[1].bitfield
.xmmword
5294 || i
.types
[1].bitfield
.ymmword
5295 || i
.types
[1].bitfield
.zmmword
)
5296 && (register_number (i
.op
[1].regs
)
5297 == register_number (i
.index_reg
)))
5299 if (operand_check
== check_error
)
5301 i
.error
= invalid_vector_register_set
;
5304 if (operand_check
!= check_none
)
5305 as_warn (_("index and destination registers should be distinct"));
5310 /* Check if broadcast is supported by the instruction and is applied
5311 to the memory operand. */
5314 i386_operand_type type
, overlap
;
5316 /* Check if specified broadcast is supported in this instruction,
5317 and its broadcast bytes match the memory operand. */
5318 op
= i
.broadcast
->operand
;
5319 if (!t
->opcode_modifier
.broadcast
5320 || !(i
.flags
[op
] & Operand_Mem
)
5321 || (!i
.types
[op
].bitfield
.unspecified
5322 && !match_broadcast_size (t
, op
)))
5325 i
.error
= unsupported_broadcast
;
5329 i
.broadcast
->bytes
= ((1 << (t
->opcode_modifier
.broadcast
- 1))
5330 * i
.broadcast
->type
);
5331 operand_type_set (&type
, 0);
5332 switch (i
.broadcast
->bytes
)
5335 type
.bitfield
.word
= 1;
5338 type
.bitfield
.dword
= 1;
5341 type
.bitfield
.qword
= 1;
5344 type
.bitfield
.xmmword
= 1;
5347 type
.bitfield
.ymmword
= 1;
5350 type
.bitfield
.zmmword
= 1;
5356 overlap
= operand_type_and (type
, t
->operand_types
[op
]);
5357 if (operand_type_all_zero (&overlap
))
5360 if (t
->opcode_modifier
.checkregsize
)
5364 type
.bitfield
.baseindex
= 1;
5365 for (j
= 0; j
< i
.operands
; ++j
)
5368 && !operand_type_register_match(i
.types
[j
],
5369 t
->operand_types
[j
],
5371 t
->operand_types
[op
]))
5376 /* If broadcast is supported in this instruction, we need to check if
5377 operand of one-element size isn't specified without broadcast. */
5378 else if (t
->opcode_modifier
.broadcast
&& i
.mem_operands
)
5380 /* Find memory operand. */
5381 for (op
= 0; op
< i
.operands
; op
++)
5382 if (operand_type_check (i
.types
[op
], anymem
))
5384 gas_assert (op
< i
.operands
);
5385 /* Check size of the memory operand. */
5386 if (match_broadcast_size (t
, op
))
5388 i
.error
= broadcast_needed
;
5393 op
= MAX_OPERANDS
- 1; /* Avoid uninitialized variable warning. */
5395 /* Check if requested masking is supported. */
5398 switch (t
->opcode_modifier
.masking
)
5402 case MERGING_MASKING
:
5403 if (i
.mask
->zeroing
)
5406 i
.error
= unsupported_masking
;
5410 case DYNAMIC_MASKING
:
5411 /* Memory destinations allow only merging masking. */
5412 if (i
.mask
->zeroing
&& i
.mem_operands
)
5414 /* Find memory operand. */
5415 for (op
= 0; op
< i
.operands
; op
++)
5416 if (i
.flags
[op
] & Operand_Mem
)
5418 gas_assert (op
< i
.operands
);
5419 if (op
== i
.operands
- 1)
5421 i
.error
= unsupported_masking
;
5431 /* Check if masking is applied to dest operand. */
5432 if (i
.mask
&& (i
.mask
->operand
!= (int) (i
.operands
- 1)))
5434 i
.error
= mask_not_on_destination
;
5441 if ((i
.rounding
->type
!= saeonly
5442 && !t
->opcode_modifier
.staticrounding
)
5443 || (i
.rounding
->type
== saeonly
5444 && (t
->opcode_modifier
.staticrounding
5445 || !t
->opcode_modifier
.sae
)))
5447 i
.error
= unsupported_rc_sae
;
5450 /* If the instruction has several immediate operands and one of
5451 them is rounding, the rounding operand should be the last
5452 immediate operand. */
5453 if (i
.imm_operands
> 1
5454 && i
.rounding
->operand
!= (int) (i
.imm_operands
- 1))
5456 i
.error
= rc_sae_operand_not_last_imm
;
5461 /* Check vector Disp8 operand. */
5462 if (t
->opcode_modifier
.disp8memshift
5463 && i
.disp_encoding
!= disp_encoding_32bit
)
5466 i
.memshift
= t
->opcode_modifier
.broadcast
- 1;
5467 else if (t
->opcode_modifier
.disp8memshift
!= DISP8_SHIFT_VL
)
5468 i
.memshift
= t
->opcode_modifier
.disp8memshift
;
5471 const i386_operand_type
*type
= NULL
;
5474 for (op
= 0; op
< i
.operands
; op
++)
5475 if (operand_type_check (i
.types
[op
], anymem
))
5477 if (t
->opcode_modifier
.evex
== EVEXLIG
)
5478 i
.memshift
= 2 + (i
.suffix
== QWORD_MNEM_SUFFIX
);
5479 else if (t
->operand_types
[op
].bitfield
.xmmword
5480 + t
->operand_types
[op
].bitfield
.ymmword
5481 + t
->operand_types
[op
].bitfield
.zmmword
<= 1)
5482 type
= &t
->operand_types
[op
];
5483 else if (!i
.types
[op
].bitfield
.unspecified
)
5484 type
= &i
.types
[op
];
5486 else if (i
.types
[op
].bitfield
.regsimd
5487 && t
->opcode_modifier
.evex
!= EVEXLIG
)
5489 if (i
.types
[op
].bitfield
.zmmword
)
5491 else if (i
.types
[op
].bitfield
.ymmword
&& i
.memshift
< 5)
5493 else if (i
.types
[op
].bitfield
.xmmword
&& i
.memshift
< 4)
5499 if (type
->bitfield
.zmmword
)
5501 else if (type
->bitfield
.ymmword
)
5503 else if (type
->bitfield
.xmmword
)
5507 /* For the check in fits_in_disp8(). */
5508 if (i
.memshift
== 0)
5512 for (op
= 0; op
< i
.operands
; op
++)
5513 if (operand_type_check (i
.types
[op
], disp
)
5514 && i
.op
[op
].disps
->X_op
== O_constant
)
5516 if (fits_in_disp8 (i
.op
[op
].disps
->X_add_number
))
5518 i
.types
[op
].bitfield
.disp8
= 1;
5521 i
.types
[op
].bitfield
.disp8
= 0;
5530 /* Check if operands are valid for the instruction. Update VEX
5534 VEX_check_operands (const insn_template
*t
)
5536 if (i
.vec_encoding
== vex_encoding_evex
)
5538 /* This instruction must be encoded with EVEX prefix. */
5539 if (!is_evex_encoding (t
))
5541 i
.error
= unsupported
;
5547 if (!t
->opcode_modifier
.vex
)
5549 /* This instruction template doesn't have VEX prefix. */
5550 if (i
.vec_encoding
!= vex_encoding_default
)
5552 i
.error
= unsupported
;
5558 /* Only check VEX_Imm4, which must be the first operand. */
5559 if (t
->operand_types
[0].bitfield
.vec_imm4
)
5561 if (i
.op
[0].imms
->X_op
!= O_constant
5562 || !fits_in_imm4 (i
.op
[0].imms
->X_add_number
))
5568 /* Turn off Imm8 so that update_imm won't complain. */
5569 i
.types
[0] = vec_imm4
;
5575 static const insn_template
*
5576 match_template (char mnem_suffix
)
5578 /* Points to template once we've found it. */
5579 const insn_template
*t
;
5580 i386_operand_type overlap0
, overlap1
, overlap2
, overlap3
;
5581 i386_operand_type overlap4
;
5582 unsigned int found_reverse_match
;
5583 i386_opcode_modifier suffix_check
, mnemsuf_check
;
5584 i386_operand_type operand_types
[MAX_OPERANDS
];
5585 int addr_prefix_disp
;
5587 unsigned int found_cpu_match
, size_match
;
5588 unsigned int check_register
;
5589 enum i386_error specific_error
= 0;
5591 #if MAX_OPERANDS != 5
5592 # error "MAX_OPERANDS must be 5."
5595 found_reverse_match
= 0;
5596 addr_prefix_disp
= -1;
5598 memset (&suffix_check
, 0, sizeof (suffix_check
));
5599 if (intel_syntax
&& i
.broadcast
)
5601 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
5602 suffix_check
.no_bsuf
= 1;
5603 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
5604 suffix_check
.no_wsuf
= 1;
5605 else if (i
.suffix
== SHORT_MNEM_SUFFIX
)
5606 suffix_check
.no_ssuf
= 1;
5607 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
5608 suffix_check
.no_lsuf
= 1;
5609 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
5610 suffix_check
.no_qsuf
= 1;
5611 else if (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
)
5612 suffix_check
.no_ldsuf
= 1;
5614 memset (&mnemsuf_check
, 0, sizeof (mnemsuf_check
));
5617 switch (mnem_suffix
)
5619 case BYTE_MNEM_SUFFIX
: mnemsuf_check
.no_bsuf
= 1; break;
5620 case WORD_MNEM_SUFFIX
: mnemsuf_check
.no_wsuf
= 1; break;
5621 case SHORT_MNEM_SUFFIX
: mnemsuf_check
.no_ssuf
= 1; break;
5622 case LONG_MNEM_SUFFIX
: mnemsuf_check
.no_lsuf
= 1; break;
5623 case QWORD_MNEM_SUFFIX
: mnemsuf_check
.no_qsuf
= 1; break;
5627 /* Must have right number of operands. */
5628 i
.error
= number_of_operands_mismatch
;
5630 for (t
= current_templates
->start
; t
< current_templates
->end
; t
++)
5632 addr_prefix_disp
= -1;
5633 found_reverse_match
= 0;
5635 if (i
.operands
!= t
->operands
)
5638 /* Check processor support. */
5639 i
.error
= unsupported
;
5640 found_cpu_match
= (cpu_flags_match (t
)
5641 == CPU_FLAGS_PERFECT_MATCH
);
5642 if (!found_cpu_match
)
5645 /* Check AT&T mnemonic. */
5646 i
.error
= unsupported_with_intel_mnemonic
;
5647 if (intel_mnemonic
&& t
->opcode_modifier
.attmnemonic
)
5650 /* Check AT&T/Intel syntax and Intel64/AMD64 ISA. */
5651 i
.error
= unsupported_syntax
;
5652 if ((intel_syntax
&& t
->opcode_modifier
.attsyntax
)
5653 || (!intel_syntax
&& t
->opcode_modifier
.intelsyntax
)
5654 || (intel64
&& t
->opcode_modifier
.amd64
)
5655 || (!intel64
&& t
->opcode_modifier
.intel64
))
5658 /* Check the suffix, except for some instructions in intel mode. */
5659 i
.error
= invalid_instruction_suffix
;
5660 if ((!intel_syntax
|| !t
->opcode_modifier
.ignoresize
)
5661 && ((t
->opcode_modifier
.no_bsuf
&& suffix_check
.no_bsuf
)
5662 || (t
->opcode_modifier
.no_wsuf
&& suffix_check
.no_wsuf
)
5663 || (t
->opcode_modifier
.no_lsuf
&& suffix_check
.no_lsuf
)
5664 || (t
->opcode_modifier
.no_ssuf
&& suffix_check
.no_ssuf
)
5665 || (t
->opcode_modifier
.no_qsuf
&& suffix_check
.no_qsuf
)
5666 || (t
->opcode_modifier
.no_ldsuf
&& suffix_check
.no_ldsuf
)))
5668 /* In Intel mode all mnemonic suffixes must be explicitly allowed. */
5669 if ((t
->opcode_modifier
.no_bsuf
&& mnemsuf_check
.no_bsuf
)
5670 || (t
->opcode_modifier
.no_wsuf
&& mnemsuf_check
.no_wsuf
)
5671 || (t
->opcode_modifier
.no_lsuf
&& mnemsuf_check
.no_lsuf
)
5672 || (t
->opcode_modifier
.no_ssuf
&& mnemsuf_check
.no_ssuf
)
5673 || (t
->opcode_modifier
.no_qsuf
&& mnemsuf_check
.no_qsuf
)
5674 || (t
->opcode_modifier
.no_ldsuf
&& mnemsuf_check
.no_ldsuf
))
5677 size_match
= operand_size_match (t
);
5681 for (j
= 0; j
< MAX_OPERANDS
; j
++)
5682 operand_types
[j
] = t
->operand_types
[j
];
5684 /* In general, don't allow 64-bit operands in 32-bit mode. */
5685 if (i
.suffix
== QWORD_MNEM_SUFFIX
5686 && flag_code
!= CODE_64BIT
5688 ? (!t
->opcode_modifier
.ignoresize
5689 && !t
->opcode_modifier
.broadcast
5690 && !intel_float_operand (t
->name
))
5691 : intel_float_operand (t
->name
) != 2)
5692 && ((!operand_types
[0].bitfield
.regmmx
5693 && !operand_types
[0].bitfield
.regsimd
)
5694 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
5695 && !operand_types
[t
->operands
> 1].bitfield
.regsimd
))
5696 && (t
->base_opcode
!= 0x0fc7
5697 || t
->extension_opcode
!= 1 /* cmpxchg8b */))
5700 /* In general, don't allow 32-bit operands on pre-386. */
5701 else if (i
.suffix
== LONG_MNEM_SUFFIX
5702 && !cpu_arch_flags
.bitfield
.cpui386
5704 ? (!t
->opcode_modifier
.ignoresize
5705 && !intel_float_operand (t
->name
))
5706 : intel_float_operand (t
->name
) != 2)
5707 && ((!operand_types
[0].bitfield
.regmmx
5708 && !operand_types
[0].bitfield
.regsimd
)
5709 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
5710 && !operand_types
[t
->operands
> 1].bitfield
.regsimd
)))
5713 /* Do not verify operands when there are none. */
5717 /* We've found a match; break out of loop. */
5721 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
5722 into Disp32/Disp16/Disp32 operand. */
5723 if (i
.prefix
[ADDR_PREFIX
] != 0)
5725 /* There should be only one Disp operand. */
5729 for (j
= 0; j
< MAX_OPERANDS
; j
++)
5731 if (operand_types
[j
].bitfield
.disp16
)
5733 addr_prefix_disp
= j
;
5734 operand_types
[j
].bitfield
.disp32
= 1;
5735 operand_types
[j
].bitfield
.disp16
= 0;
5741 for (j
= 0; j
< MAX_OPERANDS
; j
++)
5743 if (operand_types
[j
].bitfield
.disp32
)
5745 addr_prefix_disp
= j
;
5746 operand_types
[j
].bitfield
.disp32
= 0;
5747 operand_types
[j
].bitfield
.disp16
= 1;
5753 for (j
= 0; j
< MAX_OPERANDS
; j
++)
5755 if (operand_types
[j
].bitfield
.disp64
)
5757 addr_prefix_disp
= j
;
5758 operand_types
[j
].bitfield
.disp64
= 0;
5759 operand_types
[j
].bitfield
.disp32
= 1;
5767 /* Force 0x8b encoding for "mov foo@GOT, %eax". */
5768 if (i
.reloc
[0] == BFD_RELOC_386_GOT32
&& t
->base_opcode
== 0xa0)
5771 /* We check register size if needed. */
5772 if (t
->opcode_modifier
.checkregsize
)
5774 check_register
= (1 << t
->operands
) - 1;
5776 check_register
&= ~(1 << i
.broadcast
->operand
);
5781 overlap0
= operand_type_and (i
.types
[0], operand_types
[0]);
5782 switch (t
->operands
)
5785 if (!operand_type_match (overlap0
, i
.types
[0]))
5789 /* xchg %eax, %eax is a special case. It is an alias for nop
5790 only in 32bit mode and we can use opcode 0x90. In 64bit
5791 mode, we can't use 0x90 for xchg %eax, %eax since it should
5792 zero-extend %eax to %rax. */
5793 if (flag_code
== CODE_64BIT
5794 && t
->base_opcode
== 0x90
5795 && operand_type_equal (&i
.types
[0], &acc32
)
5796 && operand_type_equal (&i
.types
[1], &acc32
))
5798 /* xrelease mov %eax, <disp> is another special case. It must not
5799 match the accumulator-only encoding of mov. */
5800 if (flag_code
!= CODE_64BIT
5802 && t
->base_opcode
== 0xa0
5803 && i
.types
[0].bitfield
.acc
5804 && operand_type_check (i
.types
[1], anymem
))
5809 if (!(size_match
& MATCH_STRAIGHT
))
5811 /* Reverse direction of operands if swapping is possible in the first
5812 place (operands need to be symmetric) and
5813 - the load form is requested, and the template is a store form,
5814 - the store form is requested, and the template is a load form,
5815 - the non-default (swapped) form is requested. */
5816 overlap1
= operand_type_and (operand_types
[0], operand_types
[1]);
5817 if (t
->opcode_modifier
.d
&& i
.reg_operands
== i
.operands
5818 && !operand_type_all_zero (&overlap1
))
5819 switch (i
.dir_encoding
)
5821 case dir_encoding_load
:
5822 if (operand_type_check (operand_types
[i
.operands
- 1], anymem
)
5823 || operand_types
[i
.operands
- 1].bitfield
.regmem
)
5827 case dir_encoding_store
:
5828 if (!operand_type_check (operand_types
[i
.operands
- 1], anymem
)
5829 && !operand_types
[i
.operands
- 1].bitfield
.regmem
)
5833 case dir_encoding_swap
:
5836 case dir_encoding_default
:
5839 /* If we want store form, we skip the current load. */
5840 if ((i
.dir_encoding
== dir_encoding_store
5841 || i
.dir_encoding
== dir_encoding_swap
)
5842 && i
.mem_operands
== 0
5843 && t
->opcode_modifier
.load
)
5848 overlap1
= operand_type_and (i
.types
[1], operand_types
[1]);
5849 if (!operand_type_match (overlap0
, i
.types
[0])
5850 || !operand_type_match (overlap1
, i
.types
[1])
5851 || ((check_register
& 3) == 3
5852 && !operand_type_register_match (i
.types
[0],
5857 /* Check if other direction is valid ... */
5858 if (!t
->opcode_modifier
.d
)
5862 if (!(size_match
& MATCH_REVERSE
))
5864 /* Try reversing direction of operands. */
5865 overlap0
= operand_type_and (i
.types
[0], operand_types
[i
.operands
- 1]);
5866 overlap1
= operand_type_and (i
.types
[i
.operands
- 1], operand_types
[0]);
5867 if (!operand_type_match (overlap0
, i
.types
[0])
5868 || !operand_type_match (overlap1
, i
.types
[i
.operands
- 1])
5870 && !operand_type_register_match (i
.types
[0],
5871 operand_types
[i
.operands
- 1],
5872 i
.types
[i
.operands
- 1],
5875 /* Does not match either direction. */
5878 /* found_reverse_match holds which of D or FloatR
5880 if (!t
->opcode_modifier
.d
)
5881 found_reverse_match
= 0;
5882 else if (operand_types
[0].bitfield
.tbyte
)
5883 found_reverse_match
= Opcode_FloatD
;
5884 else if (operand_types
[0].bitfield
.xmmword
5885 || operand_types
[i
.operands
- 1].bitfield
.xmmword
5886 || operand_types
[0].bitfield
.regmmx
5887 || operand_types
[i
.operands
- 1].bitfield
.regmmx
5888 || is_any_vex_encoding(t
))
5889 found_reverse_match
= (t
->base_opcode
& 0xee) != 0x6e
5890 ? Opcode_SIMD_FloatD
: Opcode_SIMD_IntD
;
5892 found_reverse_match
= Opcode_D
;
5893 if (t
->opcode_modifier
.floatr
)
5894 found_reverse_match
|= Opcode_FloatR
;
5898 /* Found a forward 2 operand match here. */
5899 switch (t
->operands
)
5902 overlap4
= operand_type_and (i
.types
[4],
5906 overlap3
= operand_type_and (i
.types
[3],
5910 overlap2
= operand_type_and (i
.types
[2],
5915 switch (t
->operands
)
5918 if (!operand_type_match (overlap4
, i
.types
[4])
5919 || !operand_type_register_match (i
.types
[3],
5926 if (!operand_type_match (overlap3
, i
.types
[3])
5927 || ((check_register
& 0xa) == 0xa
5928 && !operand_type_register_match (i
.types
[1],
5932 || ((check_register
& 0xc) == 0xc
5933 && !operand_type_register_match (i
.types
[2],
5940 /* Here we make use of the fact that there are no
5941 reverse match 3 operand instructions. */
5942 if (!operand_type_match (overlap2
, i
.types
[2])
5943 || ((check_register
& 5) == 5
5944 && !operand_type_register_match (i
.types
[0],
5948 || ((check_register
& 6) == 6
5949 && !operand_type_register_match (i
.types
[1],
5957 /* Found either forward/reverse 2, 3 or 4 operand match here:
5958 slip through to break. */
5960 if (!found_cpu_match
)
5963 /* Check if vector and VEX operands are valid. */
5964 if (check_VecOperands (t
) || VEX_check_operands (t
))
5966 specific_error
= i
.error
;
5970 /* We've found a match; break out of loop. */
5974 if (t
== current_templates
->end
)
5976 /* We found no match. */
5977 const char *err_msg
;
5978 switch (specific_error
? specific_error
: i
.error
)
5982 case operand_size_mismatch
:
5983 err_msg
= _("operand size mismatch");
5985 case operand_type_mismatch
:
5986 err_msg
= _("operand type mismatch");
5988 case register_type_mismatch
:
5989 err_msg
= _("register type mismatch");
5991 case number_of_operands_mismatch
:
5992 err_msg
= _("number of operands mismatch");
5994 case invalid_instruction_suffix
:
5995 err_msg
= _("invalid instruction suffix");
5998 err_msg
= _("constant doesn't fit in 4 bits");
6000 case unsupported_with_intel_mnemonic
:
6001 err_msg
= _("unsupported with Intel mnemonic");
6003 case unsupported_syntax
:
6004 err_msg
= _("unsupported syntax");
6007 as_bad (_("unsupported instruction `%s'"),
6008 current_templates
->start
->name
);
6010 case invalid_vsib_address
:
6011 err_msg
= _("invalid VSIB address");
6013 case invalid_vector_register_set
:
6014 err_msg
= _("mask, index, and destination registers must be distinct");
6016 case unsupported_vector_index_register
:
6017 err_msg
= _("unsupported vector index register");
6019 case unsupported_broadcast
:
6020 err_msg
= _("unsupported broadcast");
6022 case broadcast_needed
:
6023 err_msg
= _("broadcast is needed for operand of such type");
6025 case unsupported_masking
:
6026 err_msg
= _("unsupported masking");
6028 case mask_not_on_destination
:
6029 err_msg
= _("mask not on destination operand");
6031 case no_default_mask
:
6032 err_msg
= _("default mask isn't allowed");
6034 case unsupported_rc_sae
:
6035 err_msg
= _("unsupported static rounding/sae");
6037 case rc_sae_operand_not_last_imm
:
6039 err_msg
= _("RC/SAE operand must precede immediate operands");
6041 err_msg
= _("RC/SAE operand must follow immediate operands");
6043 case invalid_register_operand
:
6044 err_msg
= _("invalid register operand");
6047 as_bad (_("%s for `%s'"), err_msg
,
6048 current_templates
->start
->name
);
6052 if (!quiet_warnings
)
6055 && (i
.types
[0].bitfield
.jumpabsolute
6056 != operand_types
[0].bitfield
.jumpabsolute
))
6058 as_warn (_("indirect %s without `*'"), t
->name
);
6061 if (t
->opcode_modifier
.isprefix
6062 && t
->opcode_modifier
.ignoresize
)
6064 /* Warn them that a data or address size prefix doesn't
6065 affect assembly of the next line of code. */
6066 as_warn (_("stand-alone `%s' prefix"), t
->name
);
6070 /* Copy the template we found. */
6073 if (addr_prefix_disp
!= -1)
6074 i
.tm
.operand_types
[addr_prefix_disp
]
6075 = operand_types
[addr_prefix_disp
];
6077 if (found_reverse_match
)
6079 /* If we found a reverse match we must alter the opcode
6080 direction bit. found_reverse_match holds bits to change
6081 (different for int & float insns). */
6083 i
.tm
.base_opcode
^= found_reverse_match
;
6085 i
.tm
.operand_types
[0] = operand_types
[i
.operands
- 1];
6086 i
.tm
.operand_types
[i
.operands
- 1] = operand_types
[0];
6095 int mem_op
= operand_type_check (i
.types
[0], anymem
) ? 0 : 1;
6096 if (i
.tm
.operand_types
[mem_op
].bitfield
.esseg
)
6098 if (i
.seg
[0] != NULL
&& i
.seg
[0] != &es
)
6100 as_bad (_("`%s' operand %d must use `%ses' segment"),
6106 /* There's only ever one segment override allowed per instruction.
6107 This instruction possibly has a legal segment override on the
6108 second operand, so copy the segment to where non-string
6109 instructions store it, allowing common code. */
6110 i
.seg
[0] = i
.seg
[1];
6112 else if (i
.tm
.operand_types
[mem_op
+ 1].bitfield
.esseg
)
6114 if (i
.seg
[1] != NULL
&& i
.seg
[1] != &es
)
6116 as_bad (_("`%s' operand %d must use `%ses' segment"),
6127 process_suffix (void)
6129 /* If matched instruction specifies an explicit instruction mnemonic
6131 if (i
.tm
.opcode_modifier
.size
== SIZE16
)
6132 i
.suffix
= WORD_MNEM_SUFFIX
;
6133 else if (i
.tm
.opcode_modifier
.size
== SIZE32
)
6134 i
.suffix
= LONG_MNEM_SUFFIX
;
6135 else if (i
.tm
.opcode_modifier
.size
== SIZE64
)
6136 i
.suffix
= QWORD_MNEM_SUFFIX
;
6137 else if (i
.reg_operands
)
6139 /* If there's no instruction mnemonic suffix we try to invent one
6140 based on register operands. */
6143 /* We take i.suffix from the last register operand specified,
6144 Destination register type is more significant than source
6145 register type. crc32 in SSE4.2 prefers source register
6147 if (i
.tm
.base_opcode
== 0xf20f38f0 && i
.types
[0].bitfield
.reg
)
6149 if (i
.types
[0].bitfield
.byte
)
6150 i
.suffix
= BYTE_MNEM_SUFFIX
;
6151 else if (i
.types
[0].bitfield
.word
)
6152 i
.suffix
= WORD_MNEM_SUFFIX
;
6153 else if (i
.types
[0].bitfield
.dword
)
6154 i
.suffix
= LONG_MNEM_SUFFIX
;
6155 else if (i
.types
[0].bitfield
.qword
)
6156 i
.suffix
= QWORD_MNEM_SUFFIX
;
6163 if (i
.tm
.base_opcode
== 0xf20f38f0)
6165 /* We have to know the operand size for crc32. */
6166 as_bad (_("ambiguous memory operand size for `%s`"),
6171 for (op
= i
.operands
; --op
>= 0;)
6172 if (!i
.tm
.operand_types
[op
].bitfield
.inoutportreg
6173 && !i
.tm
.operand_types
[op
].bitfield
.shiftcount
)
6175 if (!i
.types
[op
].bitfield
.reg
)
6177 if (i
.types
[op
].bitfield
.byte
)
6178 i
.suffix
= BYTE_MNEM_SUFFIX
;
6179 else if (i
.types
[op
].bitfield
.word
)
6180 i
.suffix
= WORD_MNEM_SUFFIX
;
6181 else if (i
.types
[op
].bitfield
.dword
)
6182 i
.suffix
= LONG_MNEM_SUFFIX
;
6183 else if (i
.types
[op
].bitfield
.qword
)
6184 i
.suffix
= QWORD_MNEM_SUFFIX
;
6191 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
6194 && i
.tm
.opcode_modifier
.ignoresize
6195 && i
.tm
.opcode_modifier
.no_bsuf
)
6197 else if (!check_byte_reg ())
6200 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
6203 && i
.tm
.opcode_modifier
.ignoresize
6204 && i
.tm
.opcode_modifier
.no_lsuf
6205 && !i
.tm
.opcode_modifier
.todword
6206 && !i
.tm
.opcode_modifier
.toqword
)
6208 else if (!check_long_reg ())
6211 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
6214 && i
.tm
.opcode_modifier
.ignoresize
6215 && i
.tm
.opcode_modifier
.no_qsuf
6216 && !i
.tm
.opcode_modifier
.todword
6217 && !i
.tm
.opcode_modifier
.toqword
)
6219 else if (!check_qword_reg ())
6222 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
6225 && i
.tm
.opcode_modifier
.ignoresize
6226 && i
.tm
.opcode_modifier
.no_wsuf
)
6228 else if (!check_word_reg ())
6231 else if (intel_syntax
&& i
.tm
.opcode_modifier
.ignoresize
)
6232 /* Do nothing if the instruction is going to ignore the prefix. */
6237 else if (i
.tm
.opcode_modifier
.defaultsize
6239 /* exclude fldenv/frstor/fsave/fstenv */
6240 && i
.tm
.opcode_modifier
.no_ssuf
)
6242 i
.suffix
= stackop_size
;
6244 else if (intel_syntax
6246 && (i
.tm
.operand_types
[0].bitfield
.jumpabsolute
6247 || i
.tm
.opcode_modifier
.jumpbyte
6248 || i
.tm
.opcode_modifier
.jumpintersegment
6249 || (i
.tm
.base_opcode
== 0x0f01 /* [ls][gi]dt */
6250 && i
.tm
.extension_opcode
<= 3)))
6255 if (!i
.tm
.opcode_modifier
.no_qsuf
)
6257 i
.suffix
= QWORD_MNEM_SUFFIX
;
6262 if (!i
.tm
.opcode_modifier
.no_lsuf
)
6263 i
.suffix
= LONG_MNEM_SUFFIX
;
6266 if (!i
.tm
.opcode_modifier
.no_wsuf
)
6267 i
.suffix
= WORD_MNEM_SUFFIX
;
6276 if (i
.tm
.opcode_modifier
.w
)
6278 as_bad (_("no instruction mnemonic suffix given and "
6279 "no register operands; can't size instruction"));
6285 unsigned int suffixes
;
6287 suffixes
= !i
.tm
.opcode_modifier
.no_bsuf
;
6288 if (!i
.tm
.opcode_modifier
.no_wsuf
)
6290 if (!i
.tm
.opcode_modifier
.no_lsuf
)
6292 if (!i
.tm
.opcode_modifier
.no_ldsuf
)
6294 if (!i
.tm
.opcode_modifier
.no_ssuf
)
6296 if (flag_code
== CODE_64BIT
&& !i
.tm
.opcode_modifier
.no_qsuf
)
6299 /* There are more than suffix matches. */
6300 if (i
.tm
.opcode_modifier
.w
6301 || ((suffixes
& (suffixes
- 1))
6302 && !i
.tm
.opcode_modifier
.defaultsize
6303 && !i
.tm
.opcode_modifier
.ignoresize
))
6305 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
6311 /* Change the opcode based on the operand size given by i.suffix. */
6314 /* Size floating point instruction. */
6315 case LONG_MNEM_SUFFIX
:
6316 if (i
.tm
.opcode_modifier
.floatmf
)
6318 i
.tm
.base_opcode
^= 4;
6322 case WORD_MNEM_SUFFIX
:
6323 case QWORD_MNEM_SUFFIX
:
6324 /* It's not a byte, select word/dword operation. */
6325 if (i
.tm
.opcode_modifier
.w
)
6327 if (i
.tm
.opcode_modifier
.shortform
)
6328 i
.tm
.base_opcode
|= 8;
6330 i
.tm
.base_opcode
|= 1;
6333 case SHORT_MNEM_SUFFIX
:
6334 /* Now select between word & dword operations via the operand
6335 size prefix, except for instructions that will ignore this
6337 if (i
.reg_operands
> 0
6338 && i
.types
[0].bitfield
.reg
6339 && i
.tm
.opcode_modifier
.addrprefixopreg
6340 && (i
.tm
.opcode_modifier
.immext
6341 || i
.operands
== 1))
6343 /* The address size override prefix changes the size of the
6345 if ((flag_code
== CODE_32BIT
6346 && i
.op
[0].regs
->reg_type
.bitfield
.word
)
6347 || (flag_code
!= CODE_32BIT
6348 && i
.op
[0].regs
->reg_type
.bitfield
.dword
))
6349 if (!add_prefix (ADDR_PREFIX_OPCODE
))
6352 else if (i
.suffix
!= QWORD_MNEM_SUFFIX
6353 && !i
.tm
.opcode_modifier
.ignoresize
6354 && !i
.tm
.opcode_modifier
.floatmf
6355 && !i
.tm
.opcode_modifier
.vex
6356 && !i
.tm
.opcode_modifier
.vexopcode
6357 && !is_evex_encoding (&i
.tm
)
6358 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
6359 || (flag_code
== CODE_64BIT
6360 && i
.tm
.opcode_modifier
.jumpbyte
)))
6362 unsigned int prefix
= DATA_PREFIX_OPCODE
;
6364 if (i
.tm
.opcode_modifier
.jumpbyte
) /* jcxz, loop */
6365 prefix
= ADDR_PREFIX_OPCODE
;
6367 if (!add_prefix (prefix
))
6371 /* Set mode64 for an operand. */
6372 if (i
.suffix
== QWORD_MNEM_SUFFIX
6373 && flag_code
== CODE_64BIT
6374 && !i
.tm
.opcode_modifier
.norex64
6375 /* Special case for xchg %rax,%rax. It is NOP and doesn't
6377 && ! (i
.operands
== 2
6378 && i
.tm
.base_opcode
== 0x90
6379 && i
.tm
.extension_opcode
== None
6380 && operand_type_equal (&i
.types
[0], &acc64
)
6381 && operand_type_equal (&i
.types
[1], &acc64
)))
6387 if (i
.reg_operands
!= 0
6389 && i
.tm
.opcode_modifier
.addrprefixopreg
6390 && !i
.tm
.opcode_modifier
.immext
)
6392 /* Check invalid register operand when the address size override
6393 prefix changes the size of register operands. */
6395 enum { need_word
, need_dword
, need_qword
} need
;
6397 if (flag_code
== CODE_32BIT
)
6398 need
= i
.prefix
[ADDR_PREFIX
] ? need_word
: need_dword
;
6401 if (i
.prefix
[ADDR_PREFIX
])
6404 need
= flag_code
== CODE_64BIT
? need_qword
: need_word
;
6407 for (op
= 0; op
< i
.operands
; op
++)
6408 if (i
.types
[op
].bitfield
.reg
6409 && ((need
== need_word
6410 && !i
.op
[op
].regs
->reg_type
.bitfield
.word
)
6411 || (need
== need_dword
6412 && !i
.op
[op
].regs
->reg_type
.bitfield
.dword
)
6413 || (need
== need_qword
6414 && !i
.op
[op
].regs
->reg_type
.bitfield
.qword
)))
6416 as_bad (_("invalid register operand size for `%s'"),
6426 check_byte_reg (void)
6430 for (op
= i
.operands
; --op
>= 0;)
6432 /* Skip non-register operands. */
6433 if (!i
.types
[op
].bitfield
.reg
)
6436 /* If this is an eight bit register, it's OK. If it's the 16 or
6437 32 bit version of an eight bit register, we will just use the
6438 low portion, and that's OK too. */
6439 if (i
.types
[op
].bitfield
.byte
)
6442 /* I/O port address operands are OK too. */
6443 if (i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
6446 /* crc32 doesn't generate this warning. */
6447 if (i
.tm
.base_opcode
== 0xf20f38f0)
6450 if ((i
.types
[op
].bitfield
.word
6451 || i
.types
[op
].bitfield
.dword
6452 || i
.types
[op
].bitfield
.qword
)
6453 && i
.op
[op
].regs
->reg_num
< 4
6454 /* Prohibit these changes in 64bit mode, since the lowering
6455 would be more complicated. */
6456 && flag_code
!= CODE_64BIT
)
6458 #if REGISTER_WARNINGS
6459 if (!quiet_warnings
)
6460 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6462 (i
.op
[op
].regs
+ (i
.types
[op
].bitfield
.word
6463 ? REGNAM_AL
- REGNAM_AX
6464 : REGNAM_AL
- REGNAM_EAX
))->reg_name
,
6466 i
.op
[op
].regs
->reg_name
,
6471 /* Any other register is bad. */
6472 if (i
.types
[op
].bitfield
.reg
6473 || i
.types
[op
].bitfield
.regmmx
6474 || i
.types
[op
].bitfield
.regsimd
6475 || i
.types
[op
].bitfield
.sreg2
6476 || i
.types
[op
].bitfield
.sreg3
6477 || i
.types
[op
].bitfield
.control
6478 || i
.types
[op
].bitfield
.debug
6479 || i
.types
[op
].bitfield
.test
)
6481 as_bad (_("`%s%s' not allowed with `%s%c'"),
6483 i
.op
[op
].regs
->reg_name
,
6493 check_long_reg (void)
6497 for (op
= i
.operands
; --op
>= 0;)
6498 /* Skip non-register operands. */
6499 if (!i
.types
[op
].bitfield
.reg
)
6501 /* Reject eight bit registers, except where the template requires
6502 them. (eg. movzb) */
6503 else if (i
.types
[op
].bitfield
.byte
6504 && (i
.tm
.operand_types
[op
].bitfield
.reg
6505 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6506 && (i
.tm
.operand_types
[op
].bitfield
.word
6507 || i
.tm
.operand_types
[op
].bitfield
.dword
))
6509 as_bad (_("`%s%s' not allowed with `%s%c'"),
6511 i
.op
[op
].regs
->reg_name
,
6516 /* Warn if the e prefix on a general reg is missing. */
6517 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
6518 && i
.types
[op
].bitfield
.word
6519 && (i
.tm
.operand_types
[op
].bitfield
.reg
6520 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6521 && i
.tm
.operand_types
[op
].bitfield
.dword
)
6523 /* Prohibit these changes in the 64bit mode, since the
6524 lowering is more complicated. */
6525 if (flag_code
== CODE_64BIT
)
6527 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6528 register_prefix
, i
.op
[op
].regs
->reg_name
,
6532 #if REGISTER_WARNINGS
6533 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6535 (i
.op
[op
].regs
+ REGNAM_EAX
- REGNAM_AX
)->reg_name
,
6536 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
6539 /* Warn if the r prefix on a general reg is present. */
6540 else if (i
.types
[op
].bitfield
.qword
6541 && (i
.tm
.operand_types
[op
].bitfield
.reg
6542 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6543 && i
.tm
.operand_types
[op
].bitfield
.dword
)
6546 && i
.tm
.opcode_modifier
.toqword
6547 && !i
.types
[0].bitfield
.regsimd
)
6549 /* Convert to QWORD. We want REX byte. */
6550 i
.suffix
= QWORD_MNEM_SUFFIX
;
6554 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6555 register_prefix
, i
.op
[op
].regs
->reg_name
,
6564 check_qword_reg (void)
6568 for (op
= i
.operands
; --op
>= 0; )
6569 /* Skip non-register operands. */
6570 if (!i
.types
[op
].bitfield
.reg
)
6572 /* Reject eight bit registers, except where the template requires
6573 them. (eg. movzb) */
6574 else if (i
.types
[op
].bitfield
.byte
6575 && (i
.tm
.operand_types
[op
].bitfield
.reg
6576 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6577 && (i
.tm
.operand_types
[op
].bitfield
.word
6578 || i
.tm
.operand_types
[op
].bitfield
.dword
))
6580 as_bad (_("`%s%s' not allowed with `%s%c'"),
6582 i
.op
[op
].regs
->reg_name
,
6587 /* Warn if the r prefix on a general reg is missing. */
6588 else if ((i
.types
[op
].bitfield
.word
6589 || i
.types
[op
].bitfield
.dword
)
6590 && (i
.tm
.operand_types
[op
].bitfield
.reg
6591 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6592 && i
.tm
.operand_types
[op
].bitfield
.qword
)
6594 /* Prohibit these changes in the 64bit mode, since the
6595 lowering is more complicated. */
6597 && i
.tm
.opcode_modifier
.todword
6598 && !i
.types
[0].bitfield
.regsimd
)
6600 /* Convert to DWORD. We don't want REX byte. */
6601 i
.suffix
= LONG_MNEM_SUFFIX
;
6605 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6606 register_prefix
, i
.op
[op
].regs
->reg_name
,
6615 check_word_reg (void)
6618 for (op
= i
.operands
; --op
>= 0;)
6619 /* Skip non-register operands. */
6620 if (!i
.types
[op
].bitfield
.reg
)
6622 /* Reject eight bit registers, except where the template requires
6623 them. (eg. movzb) */
6624 else if (i
.types
[op
].bitfield
.byte
6625 && (i
.tm
.operand_types
[op
].bitfield
.reg
6626 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6627 && (i
.tm
.operand_types
[op
].bitfield
.word
6628 || i
.tm
.operand_types
[op
].bitfield
.dword
))
6630 as_bad (_("`%s%s' not allowed with `%s%c'"),
6632 i
.op
[op
].regs
->reg_name
,
6637 /* Warn if the e or r prefix on a general reg is present. */
6638 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
6639 && (i
.types
[op
].bitfield
.dword
6640 || i
.types
[op
].bitfield
.qword
)
6641 && (i
.tm
.operand_types
[op
].bitfield
.reg
6642 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6643 && i
.tm
.operand_types
[op
].bitfield
.word
)
6645 /* Prohibit these changes in the 64bit mode, since the
6646 lowering is more complicated. */
6647 if (flag_code
== CODE_64BIT
)
6649 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6650 register_prefix
, i
.op
[op
].regs
->reg_name
,
6654 #if REGISTER_WARNINGS
6655 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6657 (i
.op
[op
].regs
+ REGNAM_AX
- REGNAM_EAX
)->reg_name
,
6658 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
6665 update_imm (unsigned int j
)
6667 i386_operand_type overlap
= i
.types
[j
];
6668 if ((overlap
.bitfield
.imm8
6669 || overlap
.bitfield
.imm8s
6670 || overlap
.bitfield
.imm16
6671 || overlap
.bitfield
.imm32
6672 || overlap
.bitfield
.imm32s
6673 || overlap
.bitfield
.imm64
)
6674 && !operand_type_equal (&overlap
, &imm8
)
6675 && !operand_type_equal (&overlap
, &imm8s
)
6676 && !operand_type_equal (&overlap
, &imm16
)
6677 && !operand_type_equal (&overlap
, &imm32
)
6678 && !operand_type_equal (&overlap
, &imm32s
)
6679 && !operand_type_equal (&overlap
, &imm64
))
6683 i386_operand_type temp
;
6685 operand_type_set (&temp
, 0);
6686 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
6688 temp
.bitfield
.imm8
= overlap
.bitfield
.imm8
;
6689 temp
.bitfield
.imm8s
= overlap
.bitfield
.imm8s
;
6691 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
6692 temp
.bitfield
.imm16
= overlap
.bitfield
.imm16
;
6693 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
6695 temp
.bitfield
.imm64
= overlap
.bitfield
.imm64
;
6696 temp
.bitfield
.imm32s
= overlap
.bitfield
.imm32s
;
6699 temp
.bitfield
.imm32
= overlap
.bitfield
.imm32
;
6702 else if (operand_type_equal (&overlap
, &imm16_32_32s
)
6703 || operand_type_equal (&overlap
, &imm16_32
)
6704 || operand_type_equal (&overlap
, &imm16_32s
))
6706 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
6711 if (!operand_type_equal (&overlap
, &imm8
)
6712 && !operand_type_equal (&overlap
, &imm8s
)
6713 && !operand_type_equal (&overlap
, &imm16
)
6714 && !operand_type_equal (&overlap
, &imm32
)
6715 && !operand_type_equal (&overlap
, &imm32s
)
6716 && !operand_type_equal (&overlap
, &imm64
))
6718 as_bad (_("no instruction mnemonic suffix given; "
6719 "can't determine immediate size"));
6723 i
.types
[j
] = overlap
;
6733 /* Update the first 2 immediate operands. */
6734 n
= i
.operands
> 2 ? 2 : i
.operands
;
6737 for (j
= 0; j
< n
; j
++)
6738 if (update_imm (j
) == 0)
6741 /* The 3rd operand can't be immediate operand. */
6742 gas_assert (operand_type_check (i
.types
[2], imm
) == 0);
6749 process_operands (void)
6751 /* Default segment register this instruction will use for memory
6752 accesses. 0 means unknown. This is only for optimizing out
6753 unnecessary segment overrides. */
6754 const seg_entry
*default_seg
= 0;
6756 if (i
.tm
.opcode_modifier
.sse2avx
&& i
.tm
.opcode_modifier
.vexvvvv
)
6758 unsigned int dupl
= i
.operands
;
6759 unsigned int dest
= dupl
- 1;
6762 /* The destination must be an xmm register. */
6763 gas_assert (i
.reg_operands
6764 && MAX_OPERANDS
> dupl
6765 && operand_type_equal (&i
.types
[dest
], ®xmm
));
6767 if (i
.tm
.operand_types
[0].bitfield
.acc
6768 && i
.tm
.operand_types
[0].bitfield
.xmmword
)
6770 if (i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
)
6772 /* Keep xmm0 for instructions with VEX prefix and 3
6774 i
.tm
.operand_types
[0].bitfield
.acc
= 0;
6775 i
.tm
.operand_types
[0].bitfield
.regsimd
= 1;
6780 /* We remove the first xmm0 and keep the number of
6781 operands unchanged, which in fact duplicates the
6783 for (j
= 1; j
< i
.operands
; j
++)
6785 i
.op
[j
- 1] = i
.op
[j
];
6786 i
.types
[j
- 1] = i
.types
[j
];
6787 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
6791 else if (i
.tm
.opcode_modifier
.implicit1stxmm0
)
6793 gas_assert ((MAX_OPERANDS
- 1) > dupl
6794 && (i
.tm
.opcode_modifier
.vexsources
6797 /* Add the implicit xmm0 for instructions with VEX prefix
6799 for (j
= i
.operands
; j
> 0; j
--)
6801 i
.op
[j
] = i
.op
[j
- 1];
6802 i
.types
[j
] = i
.types
[j
- 1];
6803 i
.tm
.operand_types
[j
] = i
.tm
.operand_types
[j
- 1];
6806 = (const reg_entry
*) hash_find (reg_hash
, "xmm0");
6807 i
.types
[0] = regxmm
;
6808 i
.tm
.operand_types
[0] = regxmm
;
6811 i
.reg_operands
+= 2;
6816 i
.op
[dupl
] = i
.op
[dest
];
6817 i
.types
[dupl
] = i
.types
[dest
];
6818 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
6827 i
.op
[dupl
] = i
.op
[dest
];
6828 i
.types
[dupl
] = i
.types
[dest
];
6829 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
6832 if (i
.tm
.opcode_modifier
.immext
)
6835 else if (i
.tm
.operand_types
[0].bitfield
.acc
6836 && i
.tm
.operand_types
[0].bitfield
.xmmword
)
6840 for (j
= 1; j
< i
.operands
; j
++)
6842 i
.op
[j
- 1] = i
.op
[j
];
6843 i
.types
[j
- 1] = i
.types
[j
];
6845 /* We need to adjust fields in i.tm since they are used by
6846 build_modrm_byte. */
6847 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
6854 else if (i
.tm
.opcode_modifier
.implicitquadgroup
)
6856 unsigned int regnum
, first_reg_in_group
, last_reg_in_group
;
6858 /* The second operand must be {x,y,z}mmN, where N is a multiple of 4. */
6859 gas_assert (i
.operands
>= 2 && i
.types
[1].bitfield
.regsimd
);
6860 regnum
= register_number (i
.op
[1].regs
);
6861 first_reg_in_group
= regnum
& ~3;
6862 last_reg_in_group
= first_reg_in_group
+ 3;
6863 if (regnum
!= first_reg_in_group
)
6864 as_warn (_("source register `%s%s' implicitly denotes"
6865 " `%s%.3s%u' to `%s%.3s%u' source group in `%s'"),
6866 register_prefix
, i
.op
[1].regs
->reg_name
,
6867 register_prefix
, i
.op
[1].regs
->reg_name
, first_reg_in_group
,
6868 register_prefix
, i
.op
[1].regs
->reg_name
, last_reg_in_group
,
6871 else if (i
.tm
.opcode_modifier
.regkludge
)
6873 /* The imul $imm, %reg instruction is converted into
6874 imul $imm, %reg, %reg, and the clr %reg instruction
6875 is converted into xor %reg, %reg. */
6877 unsigned int first_reg_op
;
6879 if (operand_type_check (i
.types
[0], reg
))
6883 /* Pretend we saw the extra register operand. */
6884 gas_assert (i
.reg_operands
== 1
6885 && i
.op
[first_reg_op
+ 1].regs
== 0);
6886 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
6887 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
6892 if (i
.tm
.opcode_modifier
.shortform
)
6894 if (i
.types
[0].bitfield
.sreg2
6895 || i
.types
[0].bitfield
.sreg3
)
6897 if (i
.tm
.base_opcode
== POP_SEG_SHORT
6898 && i
.op
[0].regs
->reg_num
== 1)
6900 as_bad (_("you can't `pop %scs'"), register_prefix
);
6903 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
6904 if ((i
.op
[0].regs
->reg_flags
& RegRex
) != 0)
6909 /* The register or float register operand is in operand
6913 if ((i
.types
[0].bitfield
.reg
&& i
.types
[0].bitfield
.tbyte
)
6914 || operand_type_check (i
.types
[0], reg
))
6918 /* Register goes in low 3 bits of opcode. */
6919 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
6920 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
6922 if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
6924 /* Warn about some common errors, but press on regardless.
6925 The first case can be generated by gcc (<= 2.8.1). */
6926 if (i
.operands
== 2)
6928 /* Reversed arguments on faddp, fsubp, etc. */
6929 as_warn (_("translating to `%s %s%s,%s%s'"), i
.tm
.name
,
6930 register_prefix
, i
.op
[!intel_syntax
].regs
->reg_name
,
6931 register_prefix
, i
.op
[intel_syntax
].regs
->reg_name
);
6935 /* Extraneous `l' suffix on fp insn. */
6936 as_warn (_("translating to `%s %s%s'"), i
.tm
.name
,
6937 register_prefix
, i
.op
[0].regs
->reg_name
);
6942 else if (i
.tm
.opcode_modifier
.modrm
)
6944 /* The opcode is completed (modulo i.tm.extension_opcode which
6945 must be put into the modrm byte). Now, we make the modrm and
6946 index base bytes based on all the info we've collected. */
6948 default_seg
= build_modrm_byte ();
6950 else if ((i
.tm
.base_opcode
& ~0x3) == MOV_AX_DISP32
)
6954 else if (i
.tm
.opcode_modifier
.isstring
)
6956 /* For the string instructions that allow a segment override
6957 on one of their operands, the default segment is ds. */
6961 if (i
.tm
.base_opcode
== 0x8d /* lea */
6964 as_warn (_("segment override on `%s' is ineffectual"), i
.tm
.name
);
6966 /* If a segment was explicitly specified, and the specified segment
6967 is not the default, use an opcode prefix to select it. If we
6968 never figured out what the default segment is, then default_seg
6969 will be zero at this point, and the specified segment prefix will
6971 if ((i
.seg
[0]) && (i
.seg
[0] != default_seg
))
6973 if (!add_prefix (i
.seg
[0]->seg_prefix
))
6979 static const seg_entry
*
6980 build_modrm_byte (void)
6982 const seg_entry
*default_seg
= 0;
6983 unsigned int source
, dest
;
6986 vex_3_sources
= i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
;
6989 unsigned int nds
, reg_slot
;
6992 dest
= i
.operands
- 1;
6995 /* There are 2 kinds of instructions:
6996 1. 5 operands: 4 register operands or 3 register operands
6997 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
6998 VexW0 or VexW1. The destination must be either XMM, YMM or
7000 2. 4 operands: 4 register operands or 3 register operands
7001 plus 1 memory operand, with VexXDS. */
7002 gas_assert ((i
.reg_operands
== 4
7003 || (i
.reg_operands
== 3 && i
.mem_operands
== 1))
7004 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
7005 && i
.tm
.opcode_modifier
.vexw
7006 && i
.tm
.operand_types
[dest
].bitfield
.regsimd
);
7008 /* If VexW1 is set, the first non-immediate operand is the source and
7009 the second non-immediate one is encoded in the immediate operand. */
7010 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
7012 source
= i
.imm_operands
;
7013 reg_slot
= i
.imm_operands
+ 1;
7017 source
= i
.imm_operands
+ 1;
7018 reg_slot
= i
.imm_operands
;
7021 if (i
.imm_operands
== 0)
7023 /* When there is no immediate operand, generate an 8bit
7024 immediate operand to encode the first operand. */
7025 exp
= &im_expressions
[i
.imm_operands
++];
7026 i
.op
[i
.operands
].imms
= exp
;
7027 i
.types
[i
.operands
] = imm8
;
7030 gas_assert (i
.tm
.operand_types
[reg_slot
].bitfield
.regsimd
);
7031 exp
->X_op
= O_constant
;
7032 exp
->X_add_number
= register_number (i
.op
[reg_slot
].regs
) << 4;
7033 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
7037 unsigned int imm_slot
;
7039 gas_assert (i
.imm_operands
== 1 && i
.types
[0].bitfield
.vec_imm4
);
7041 if (i
.tm
.opcode_modifier
.immext
)
7043 /* When ImmExt is set, the immediate byte is the last
7045 imm_slot
= i
.operands
- 1;
7053 /* Turn on Imm8 so that output_imm will generate it. */
7054 i
.types
[imm_slot
].bitfield
.imm8
= 1;
7057 gas_assert (i
.tm
.operand_types
[reg_slot
].bitfield
.regsimd
);
7058 i
.op
[imm_slot
].imms
->X_add_number
7059 |= register_number (i
.op
[reg_slot
].regs
) << 4;
7060 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
7063 gas_assert (i
.tm
.operand_types
[nds
].bitfield
.regsimd
);
7064 i
.vex
.register_specifier
= i
.op
[nds
].regs
;
7069 /* i.reg_operands MUST be the number of real register operands;
7070 implicit registers do not count. If there are 3 register
7071 operands, it must be a instruction with VexNDS. For a
7072 instruction with VexNDD, the destination register is encoded
7073 in VEX prefix. If there are 4 register operands, it must be
7074 a instruction with VEX prefix and 3 sources. */
7075 if (i
.mem_operands
== 0
7076 && ((i
.reg_operands
== 2
7077 && i
.tm
.opcode_modifier
.vexvvvv
<= VEXXDS
)
7078 || (i
.reg_operands
== 3
7079 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
7080 || (i
.reg_operands
== 4 && vex_3_sources
)))
7088 /* When there are 3 operands, one of them may be immediate,
7089 which may be the first or the last operand. Otherwise,
7090 the first operand must be shift count register (cl) or it
7091 is an instruction with VexNDS. */
7092 gas_assert (i
.imm_operands
== 1
7093 || (i
.imm_operands
== 0
7094 && (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
7095 || i
.types
[0].bitfield
.shiftcount
)));
7096 if (operand_type_check (i
.types
[0], imm
)
7097 || i
.types
[0].bitfield
.shiftcount
)
7103 /* When there are 4 operands, the first two must be 8bit
7104 immediate operands. The source operand will be the 3rd
7107 For instructions with VexNDS, if the first operand
7108 an imm8, the source operand is the 2nd one. If the last
7109 operand is imm8, the source operand is the first one. */
7110 gas_assert ((i
.imm_operands
== 2
7111 && i
.types
[0].bitfield
.imm8
7112 && i
.types
[1].bitfield
.imm8
)
7113 || (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
7114 && i
.imm_operands
== 1
7115 && (i
.types
[0].bitfield
.imm8
7116 || i
.types
[i
.operands
- 1].bitfield
.imm8
7118 if (i
.imm_operands
== 2)
7122 if (i
.types
[0].bitfield
.imm8
)
7129 if (is_evex_encoding (&i
.tm
))
7131 /* For EVEX instructions, when there are 5 operands, the
7132 first one must be immediate operand. If the second one
7133 is immediate operand, the source operand is the 3th
7134 one. If the last one is immediate operand, the source
7135 operand is the 2nd one. */
7136 gas_assert (i
.imm_operands
== 2
7137 && i
.tm
.opcode_modifier
.sae
7138 && operand_type_check (i
.types
[0], imm
));
7139 if (operand_type_check (i
.types
[1], imm
))
7141 else if (operand_type_check (i
.types
[4], imm
))
7155 /* RC/SAE operand could be between DEST and SRC. That happens
7156 when one operand is GPR and the other one is XMM/YMM/ZMM
7158 if (i
.rounding
&& i
.rounding
->operand
== (int) dest
)
7161 if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
7163 /* For instructions with VexNDS, the register-only source
7164 operand must be a 32/64bit integer, XMM, YMM, ZMM, or mask
7165 register. It is encoded in VEX prefix. We need to
7166 clear RegMem bit before calling operand_type_equal. */
7168 i386_operand_type op
;
7171 /* Check register-only source operand when two source
7172 operands are swapped. */
7173 if (!i
.tm
.operand_types
[source
].bitfield
.baseindex
7174 && i
.tm
.operand_types
[dest
].bitfield
.baseindex
)
7182 op
= i
.tm
.operand_types
[vvvv
];
7183 op
.bitfield
.regmem
= 0;
7184 if ((dest
+ 1) >= i
.operands
7185 || ((!op
.bitfield
.reg
7186 || (!op
.bitfield
.dword
&& !op
.bitfield
.qword
))
7187 && !op
.bitfield
.regsimd
7188 && !operand_type_equal (&op
, ®mask
)))
7190 i
.vex
.register_specifier
= i
.op
[vvvv
].regs
;
7196 /* One of the register operands will be encoded in the i.tm.reg
7197 field, the other in the combined i.tm.mode and i.tm.regmem
7198 fields. If no form of this instruction supports a memory
7199 destination operand, then we assume the source operand may
7200 sometimes be a memory operand and so we need to store the
7201 destination in the i.rm.reg field. */
7202 if (!i
.tm
.operand_types
[dest
].bitfield
.regmem
7203 && operand_type_check (i
.tm
.operand_types
[dest
], anymem
) == 0)
7205 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
7206 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
7207 if (i
.op
[dest
].regs
->reg_type
.bitfield
.regmmx
7208 || i
.op
[source
].regs
->reg_type
.bitfield
.regmmx
)
7209 i
.has_regmmx
= TRUE
;
7210 else if (i
.op
[dest
].regs
->reg_type
.bitfield
.regsimd
7211 || i
.op
[source
].regs
->reg_type
.bitfield
.regsimd
)
7213 if (i
.types
[dest
].bitfield
.zmmword
7214 || i
.types
[source
].bitfield
.zmmword
)
7215 i
.has_regzmm
= TRUE
;
7216 else if (i
.types
[dest
].bitfield
.ymmword
7217 || i
.types
[source
].bitfield
.ymmword
)
7218 i
.has_regymm
= TRUE
;
7220 i
.has_regxmm
= TRUE
;
7222 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
7224 if ((i
.op
[dest
].regs
->reg_flags
& RegVRex
) != 0)
7226 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
7228 if ((i
.op
[source
].regs
->reg_flags
& RegVRex
) != 0)
7233 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
7234 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
7235 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
7237 if ((i
.op
[dest
].regs
->reg_flags
& RegVRex
) != 0)
7239 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
7241 if ((i
.op
[source
].regs
->reg_flags
& RegVRex
) != 0)
7244 if (flag_code
!= CODE_64BIT
&& (i
.rex
& REX_R
))
7246 if (!i
.types
[i
.tm
.operand_types
[0].bitfield
.regmem
].bitfield
.control
)
7249 add_prefix (LOCK_PREFIX_OPCODE
);
7253 { /* If it's not 2 reg operands... */
7258 unsigned int fake_zero_displacement
= 0;
7261 for (op
= 0; op
< i
.operands
; op
++)
7262 if (operand_type_check (i
.types
[op
], anymem
))
7264 gas_assert (op
< i
.operands
);
7266 if (i
.tm
.opcode_modifier
.vecsib
)
7268 if (i
.index_reg
->reg_num
== RegIZ
)
7271 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
7274 i
.sib
.base
= NO_BASE_REGISTER
;
7275 i
.sib
.scale
= i
.log2_scale_factor
;
7276 i
.types
[op
].bitfield
.disp8
= 0;
7277 i
.types
[op
].bitfield
.disp16
= 0;
7278 i
.types
[op
].bitfield
.disp64
= 0;
7279 if (flag_code
!= CODE_64BIT
|| i
.prefix
[ADDR_PREFIX
])
7281 /* Must be 32 bit */
7282 i
.types
[op
].bitfield
.disp32
= 1;
7283 i
.types
[op
].bitfield
.disp32s
= 0;
7287 i
.types
[op
].bitfield
.disp32
= 0;
7288 i
.types
[op
].bitfield
.disp32s
= 1;
7291 i
.sib
.index
= i
.index_reg
->reg_num
;
7292 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
7294 if ((i
.index_reg
->reg_flags
& RegVRex
) != 0)
7300 if (i
.base_reg
== 0)
7303 if (!i
.disp_operands
)
7304 fake_zero_displacement
= 1;
7305 if (i
.index_reg
== 0)
7307 i386_operand_type newdisp
;
7309 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
7310 /* Operand is just <disp> */
7311 if (flag_code
== CODE_64BIT
)
7313 /* 64bit mode overwrites the 32bit absolute
7314 addressing by RIP relative addressing and
7315 absolute addressing is encoded by one of the
7316 redundant SIB forms. */
7317 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
7318 i
.sib
.base
= NO_BASE_REGISTER
;
7319 i
.sib
.index
= NO_INDEX_REGISTER
;
7320 newdisp
= (!i
.prefix
[ADDR_PREFIX
] ? disp32s
: disp32
);
7322 else if ((flag_code
== CODE_16BIT
)
7323 ^ (i
.prefix
[ADDR_PREFIX
] != 0))
7325 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
7330 i
.rm
.regmem
= NO_BASE_REGISTER
;
7333 i
.types
[op
] = operand_type_and_not (i
.types
[op
], anydisp
);
7334 i
.types
[op
] = operand_type_or (i
.types
[op
], newdisp
);
7336 else if (!i
.tm
.opcode_modifier
.vecsib
)
7338 /* !i.base_reg && i.index_reg */
7339 if (i
.index_reg
->reg_num
== RegIZ
)
7340 i
.sib
.index
= NO_INDEX_REGISTER
;
7342 i
.sib
.index
= i
.index_reg
->reg_num
;
7343 i
.sib
.base
= NO_BASE_REGISTER
;
7344 i
.sib
.scale
= i
.log2_scale_factor
;
7345 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
7346 i
.types
[op
].bitfield
.disp8
= 0;
7347 i
.types
[op
].bitfield
.disp16
= 0;
7348 i
.types
[op
].bitfield
.disp64
= 0;
7349 if (flag_code
!= CODE_64BIT
|| i
.prefix
[ADDR_PREFIX
])
7351 /* Must be 32 bit */
7352 i
.types
[op
].bitfield
.disp32
= 1;
7353 i
.types
[op
].bitfield
.disp32s
= 0;
7357 i
.types
[op
].bitfield
.disp32
= 0;
7358 i
.types
[op
].bitfield
.disp32s
= 1;
7360 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
7364 /* RIP addressing for 64bit mode. */
7365 else if (i
.base_reg
->reg_num
== RegIP
)
7367 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
7368 i
.rm
.regmem
= NO_BASE_REGISTER
;
7369 i
.types
[op
].bitfield
.disp8
= 0;
7370 i
.types
[op
].bitfield
.disp16
= 0;
7371 i
.types
[op
].bitfield
.disp32
= 0;
7372 i
.types
[op
].bitfield
.disp32s
= 1;
7373 i
.types
[op
].bitfield
.disp64
= 0;
7374 i
.flags
[op
] |= Operand_PCrel
;
7375 if (! i
.disp_operands
)
7376 fake_zero_displacement
= 1;
7378 else if (i
.base_reg
->reg_type
.bitfield
.word
)
7380 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
7381 switch (i
.base_reg
->reg_num
)
7384 if (i
.index_reg
== 0)
7386 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
7387 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
7391 if (i
.index_reg
== 0)
7394 if (operand_type_check (i
.types
[op
], disp
) == 0)
7396 /* fake (%bp) into 0(%bp) */
7397 i
.types
[op
].bitfield
.disp8
= 1;
7398 fake_zero_displacement
= 1;
7401 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
7402 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
7404 default: /* (%si) -> 4 or (%di) -> 5 */
7405 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
7407 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
7409 else /* i.base_reg and 32/64 bit mode */
7411 if (flag_code
== CODE_64BIT
7412 && operand_type_check (i
.types
[op
], disp
))
7414 i
.types
[op
].bitfield
.disp16
= 0;
7415 i
.types
[op
].bitfield
.disp64
= 0;
7416 if (i
.prefix
[ADDR_PREFIX
] == 0)
7418 i
.types
[op
].bitfield
.disp32
= 0;
7419 i
.types
[op
].bitfield
.disp32s
= 1;
7423 i
.types
[op
].bitfield
.disp32
= 1;
7424 i
.types
[op
].bitfield
.disp32s
= 0;
7428 if (!i
.tm
.opcode_modifier
.vecsib
)
7429 i
.rm
.regmem
= i
.base_reg
->reg_num
;
7430 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
7432 i
.sib
.base
= i
.base_reg
->reg_num
;
7433 /* x86-64 ignores REX prefix bit here to avoid decoder
7435 if (!(i
.base_reg
->reg_flags
& RegRex
)
7436 && (i
.base_reg
->reg_num
== EBP_REG_NUM
7437 || i
.base_reg
->reg_num
== ESP_REG_NUM
))
7439 if (i
.base_reg
->reg_num
== 5 && i
.disp_operands
== 0)
7441 fake_zero_displacement
= 1;
7442 i
.types
[op
].bitfield
.disp8
= 1;
7444 i
.sib
.scale
= i
.log2_scale_factor
;
7445 if (i
.index_reg
== 0)
7447 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
7448 /* <disp>(%esp) becomes two byte modrm with no index
7449 register. We've already stored the code for esp
7450 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
7451 Any base register besides %esp will not use the
7452 extra modrm byte. */
7453 i
.sib
.index
= NO_INDEX_REGISTER
;
7455 else if (!i
.tm
.opcode_modifier
.vecsib
)
7457 if (i
.index_reg
->reg_num
== RegIZ
)
7458 i
.sib
.index
= NO_INDEX_REGISTER
;
7460 i
.sib
.index
= i
.index_reg
->reg_num
;
7461 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
7462 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
7467 && (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
7468 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
))
7472 if (!fake_zero_displacement
7476 fake_zero_displacement
= 1;
7477 if (i
.disp_encoding
== disp_encoding_8bit
)
7478 i
.types
[op
].bitfield
.disp8
= 1;
7480 i
.types
[op
].bitfield
.disp32
= 1;
7482 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
7486 if (fake_zero_displacement
)
7488 /* Fakes a zero displacement assuming that i.types[op]
7489 holds the correct displacement size. */
7492 gas_assert (i
.op
[op
].disps
== 0);
7493 exp
= &disp_expressions
[i
.disp_operands
++];
7494 i
.op
[op
].disps
= exp
;
7495 exp
->X_op
= O_constant
;
7496 exp
->X_add_number
= 0;
7497 exp
->X_add_symbol
= (symbolS
*) 0;
7498 exp
->X_op_symbol
= (symbolS
*) 0;
7506 if (i
.tm
.opcode_modifier
.vexsources
== XOP2SOURCES
)
7508 if (operand_type_check (i
.types
[0], imm
))
7509 i
.vex
.register_specifier
= NULL
;
7512 /* VEX.vvvv encodes one of the sources when the first
7513 operand is not an immediate. */
7514 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
7515 i
.vex
.register_specifier
= i
.op
[0].regs
;
7517 i
.vex
.register_specifier
= i
.op
[1].regs
;
7520 /* Destination is a XMM register encoded in the ModRM.reg
7522 i
.rm
.reg
= i
.op
[2].regs
->reg_num
;
7523 if ((i
.op
[2].regs
->reg_flags
& RegRex
) != 0)
7526 /* ModRM.rm and VEX.B encodes the other source. */
7527 if (!i
.mem_operands
)
7531 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
7532 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
7534 i
.rm
.regmem
= i
.op
[0].regs
->reg_num
;
7536 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
7540 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXLWP
)
7542 i
.vex
.register_specifier
= i
.op
[2].regs
;
7543 if (!i
.mem_operands
)
7546 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
7547 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
7551 /* Fill in i.rm.reg or i.rm.regmem field with register operand
7552 (if any) based on i.tm.extension_opcode. Again, we must be
7553 careful to make sure that segment/control/debug/test/MMX
7554 registers are coded into the i.rm.reg field. */
7555 else if (i
.reg_operands
)
7558 unsigned int vex_reg
= ~0;
7560 for (op
= 0; op
< i
.operands
; op
++)
7562 if (i
.types
[op
].bitfield
.reg
7563 || i
.types
[op
].bitfield
.regbnd
7564 || i
.types
[op
].bitfield
.regmask
7565 || i
.types
[op
].bitfield
.sreg2
7566 || i
.types
[op
].bitfield
.sreg3
7567 || i
.types
[op
].bitfield
.control
7568 || i
.types
[op
].bitfield
.debug
7569 || i
.types
[op
].bitfield
.test
)
7571 if (i
.types
[op
].bitfield
.regsimd
)
7573 if (i
.types
[op
].bitfield
.zmmword
)
7574 i
.has_regzmm
= TRUE
;
7575 else if (i
.types
[op
].bitfield
.ymmword
)
7576 i
.has_regymm
= TRUE
;
7578 i
.has_regxmm
= TRUE
;
7581 if (i
.types
[op
].bitfield
.regmmx
)
7583 i
.has_regmmx
= TRUE
;
7590 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
7592 /* For instructions with VexNDS, the register-only
7593 source operand is encoded in VEX prefix. */
7594 gas_assert (mem
!= (unsigned int) ~0);
7599 gas_assert (op
< i
.operands
);
7603 /* Check register-only source operand when two source
7604 operands are swapped. */
7605 if (!i
.tm
.operand_types
[op
].bitfield
.baseindex
7606 && i
.tm
.operand_types
[op
+ 1].bitfield
.baseindex
)
7610 gas_assert (mem
== (vex_reg
+ 1)
7611 && op
< i
.operands
);
7616 gas_assert (vex_reg
< i
.operands
);
7620 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXNDD
)
7622 /* For instructions with VexNDD, the register destination
7623 is encoded in VEX prefix. */
7624 if (i
.mem_operands
== 0)
7626 /* There is no memory operand. */
7627 gas_assert ((op
+ 2) == i
.operands
);
7632 /* There are only 2 non-immediate operands. */
7633 gas_assert (op
< i
.imm_operands
+ 2
7634 && i
.operands
== i
.imm_operands
+ 2);
7635 vex_reg
= i
.imm_operands
+ 1;
7639 gas_assert (op
< i
.operands
);
7641 if (vex_reg
!= (unsigned int) ~0)
7643 i386_operand_type
*type
= &i
.tm
.operand_types
[vex_reg
];
7645 if ((!type
->bitfield
.reg
7646 || (!type
->bitfield
.dword
&& !type
->bitfield
.qword
))
7647 && !type
->bitfield
.regsimd
7648 && !operand_type_equal (type
, ®mask
))
7651 i
.vex
.register_specifier
= i
.op
[vex_reg
].regs
;
7654 /* Don't set OP operand twice. */
7657 /* If there is an extension opcode to put here, the
7658 register number must be put into the regmem field. */
7659 if (i
.tm
.extension_opcode
!= None
)
7661 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
7662 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
7664 if ((i
.op
[op
].regs
->reg_flags
& RegVRex
) != 0)
7669 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
7670 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
7672 if ((i
.op
[op
].regs
->reg_flags
& RegVRex
) != 0)
7677 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
7678 must set it to 3 to indicate this is a register operand
7679 in the regmem field. */
7680 if (!i
.mem_operands
)
7684 /* Fill in i.rm.reg field with extension opcode (if any). */
7685 if (i
.tm
.extension_opcode
!= None
)
7686 i
.rm
.reg
= i
.tm
.extension_opcode
;
7692 output_branch (void)
7698 relax_substateT subtype
;
7702 code16
= flag_code
== CODE_16BIT
? CODE16
: 0;
7703 size
= i
.disp_encoding
== disp_encoding_32bit
? BIG
: SMALL
;
7706 if (i
.prefix
[DATA_PREFIX
] != 0)
7712 /* Pentium4 branch hints. */
7713 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
7714 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
7719 if (i
.prefix
[REX_PREFIX
] != 0)
7725 /* BND prefixed jump. */
7726 if (i
.prefix
[BND_PREFIX
] != 0)
7728 FRAG_APPEND_1_CHAR (i
.prefix
[BND_PREFIX
]);
7732 if (i
.prefixes
!= 0 && !intel_syntax
)
7733 as_warn (_("skipping prefixes on this instruction"));
7735 /* It's always a symbol; End frag & setup for relax.
7736 Make sure there is enough room in this frag for the largest
7737 instruction we may generate in md_convert_frag. This is 2
7738 bytes for the opcode and room for the prefix and largest
7740 frag_grow (prefix
+ 2 + 4);
7741 /* Prefix and 1 opcode byte go in fr_fix. */
7742 p
= frag_more (prefix
+ 1);
7743 if (i
.prefix
[DATA_PREFIX
] != 0)
7744 *p
++ = DATA_PREFIX_OPCODE
;
7745 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
7746 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
7747 *p
++ = i
.prefix
[SEG_PREFIX
];
7748 if (i
.prefix
[REX_PREFIX
] != 0)
7749 *p
++ = i
.prefix
[REX_PREFIX
];
7750 *p
= i
.tm
.base_opcode
;
7752 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
7753 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, size
);
7754 else if (cpu_arch_flags
.bitfield
.cpui386
)
7755 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, size
);
7757 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, size
);
7760 sym
= i
.op
[0].disps
->X_add_symbol
;
7761 off
= i
.op
[0].disps
->X_add_number
;
7763 if (i
.op
[0].disps
->X_op
!= O_constant
7764 && i
.op
[0].disps
->X_op
!= O_symbol
)
7766 /* Handle complex expressions. */
7767 sym
= make_expr_symbol (i
.op
[0].disps
);
7771 /* 1 possible extra opcode + 4 byte displacement go in var part.
7772 Pass reloc in fr_var. */
7773 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
7776 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7777 /* Return TRUE iff PLT32 relocation should be used for branching to
7781 need_plt32_p (symbolS
*s
)
7783 /* PLT32 relocation is ELF only. */
7787 /* Since there is no need to prepare for PLT branch on x86-64, we
7788 can generate R_X86_64_PLT32, instead of R_X86_64_PC32, which can
7789 be used as a marker for 32-bit PC-relative branches. */
7793 /* Weak or undefined symbol need PLT32 relocation. */
7794 if (S_IS_WEAK (s
) || !S_IS_DEFINED (s
))
7797 /* Non-global symbol doesn't need PLT32 relocation. */
7798 if (! S_IS_EXTERNAL (s
))
7801 /* Other global symbols need PLT32 relocation. NB: Symbol with
7802 non-default visibilities are treated as normal global symbol
7803 so that PLT32 relocation can be used as a marker for 32-bit
7804 PC-relative branches. It is useful for linker relaxation. */
7815 bfd_reloc_code_real_type jump_reloc
= i
.reloc
[0];
7817 if (i
.tm
.opcode_modifier
.jumpbyte
)
7819 /* This is a loop or jecxz type instruction. */
7821 if (i
.prefix
[ADDR_PREFIX
] != 0)
7823 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
7826 /* Pentium4 branch hints. */
7827 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
7828 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
7830 FRAG_APPEND_1_CHAR (i
.prefix
[SEG_PREFIX
]);
7839 if (flag_code
== CODE_16BIT
)
7842 if (i
.prefix
[DATA_PREFIX
] != 0)
7844 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
7854 if (i
.prefix
[REX_PREFIX
] != 0)
7856 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
7860 /* BND prefixed jump. */
7861 if (i
.prefix
[BND_PREFIX
] != 0)
7863 FRAG_APPEND_1_CHAR (i
.prefix
[BND_PREFIX
]);
7867 if (i
.prefixes
!= 0 && !intel_syntax
)
7868 as_warn (_("skipping prefixes on this instruction"));
7870 p
= frag_more (i
.tm
.opcode_length
+ size
);
7871 switch (i
.tm
.opcode_length
)
7874 *p
++ = i
.tm
.base_opcode
>> 8;
7877 *p
++ = i
.tm
.base_opcode
;
7883 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7885 && jump_reloc
== NO_RELOC
7886 && need_plt32_p (i
.op
[0].disps
->X_add_symbol
))
7887 jump_reloc
= BFD_RELOC_X86_64_PLT32
;
7890 jump_reloc
= reloc (size
, 1, 1, jump_reloc
);
7892 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
7893 i
.op
[0].disps
, 1, jump_reloc
);
7895 /* All jumps handled here are signed, but don't use a signed limit
7896 check for 32 and 16 bit jumps as we want to allow wrap around at
7897 4G and 64k respectively. */
7899 fixP
->fx_signed
= 1;
7903 output_interseg_jump (void)
7911 if (flag_code
== CODE_16BIT
)
7915 if (i
.prefix
[DATA_PREFIX
] != 0)
7921 if (i
.prefix
[REX_PREFIX
] != 0)
7931 if (i
.prefixes
!= 0 && !intel_syntax
)
7932 as_warn (_("skipping prefixes on this instruction"));
7934 /* 1 opcode; 2 segment; offset */
7935 p
= frag_more (prefix
+ 1 + 2 + size
);
7937 if (i
.prefix
[DATA_PREFIX
] != 0)
7938 *p
++ = DATA_PREFIX_OPCODE
;
7940 if (i
.prefix
[REX_PREFIX
] != 0)
7941 *p
++ = i
.prefix
[REX_PREFIX
];
7943 *p
++ = i
.tm
.base_opcode
;
7944 if (i
.op
[1].imms
->X_op
== O_constant
)
7946 offsetT n
= i
.op
[1].imms
->X_add_number
;
7949 && !fits_in_unsigned_word (n
)
7950 && !fits_in_signed_word (n
))
7952 as_bad (_("16-bit jump out of range"));
7955 md_number_to_chars (p
, n
, size
);
7958 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
7959 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
7960 if (i
.op
[0].imms
->X_op
!= O_constant
)
7961 as_bad (_("can't handle non absolute segment in `%s'"),
7963 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
7966 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7971 asection
*seg
= now_seg
;
7972 subsegT subseg
= now_subseg
;
7974 unsigned int alignment
, align_size_1
;
7975 unsigned int isa_1_descsz
, feature_2_descsz
, descsz
;
7976 unsigned int isa_1_descsz_raw
, feature_2_descsz_raw
;
7977 unsigned int padding
;
7979 if (!IS_ELF
|| !x86_used_note
)
7982 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_X86
;
7984 /* The .note.gnu.property section layout:
7986 Field Length Contents
7989 n_descsz 4 The note descriptor size
7990 n_type 4 NT_GNU_PROPERTY_TYPE_0
7992 n_desc n_descsz The program property array
7996 /* Create the .note.gnu.property section. */
7997 sec
= subseg_new (NOTE_GNU_PROPERTY_SECTION_NAME
, 0);
7998 bfd_set_section_flags (stdoutput
, sec
,
8005 if (get_elf_backend_data (stdoutput
)->s
->elfclass
== ELFCLASS64
)
8016 bfd_set_section_alignment (stdoutput
, sec
, alignment
);
8017 elf_section_type (sec
) = SHT_NOTE
;
8019 /* GNU_PROPERTY_X86_ISA_1_USED: 4-byte type + 4-byte data size
8021 isa_1_descsz_raw
= 4 + 4 + 4;
8022 /* Align GNU_PROPERTY_X86_ISA_1_USED. */
8023 isa_1_descsz
= (isa_1_descsz_raw
+ align_size_1
) & ~align_size_1
;
8025 feature_2_descsz_raw
= isa_1_descsz
;
8026 /* GNU_PROPERTY_X86_FEATURE_2_USED: 4-byte type + 4-byte data size
8028 feature_2_descsz_raw
+= 4 + 4 + 4;
8029 /* Align GNU_PROPERTY_X86_FEATURE_2_USED. */
8030 feature_2_descsz
= ((feature_2_descsz_raw
+ align_size_1
)
8033 descsz
= feature_2_descsz
;
8034 /* Section size: n_namsz + n_descsz + n_type + n_name + n_descsz. */
8035 p
= frag_more (4 + 4 + 4 + 4 + descsz
);
8037 /* Write n_namsz. */
8038 md_number_to_chars (p
, (valueT
) 4, 4);
8040 /* Write n_descsz. */
8041 md_number_to_chars (p
+ 4, (valueT
) descsz
, 4);
8044 md_number_to_chars (p
+ 4 * 2, (valueT
) NT_GNU_PROPERTY_TYPE_0
, 4);
8047 memcpy (p
+ 4 * 3, "GNU", 4);
8049 /* Write 4-byte type. */
8050 md_number_to_chars (p
+ 4 * 4,
8051 (valueT
) GNU_PROPERTY_X86_ISA_1_USED
, 4);
8053 /* Write 4-byte data size. */
8054 md_number_to_chars (p
+ 4 * 5, (valueT
) 4, 4);
8056 /* Write 4-byte data. */
8057 md_number_to_chars (p
+ 4 * 6, (valueT
) x86_isa_1_used
, 4);
8059 /* Zero out paddings. */
8060 padding
= isa_1_descsz
- isa_1_descsz_raw
;
8062 memset (p
+ 4 * 7, 0, padding
);
8064 /* Write 4-byte type. */
8065 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 4,
8066 (valueT
) GNU_PROPERTY_X86_FEATURE_2_USED
, 4);
8068 /* Write 4-byte data size. */
8069 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 5, (valueT
) 4, 4);
8071 /* Write 4-byte data. */
8072 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 6,
8073 (valueT
) x86_feature_2_used
, 4);
8075 /* Zero out paddings. */
8076 padding
= feature_2_descsz
- feature_2_descsz_raw
;
8078 memset (p
+ isa_1_descsz
+ 4 * 7, 0, padding
);
8080 /* We probably can't restore the current segment, for there likely
8083 subseg_set (seg
, subseg
);
8090 fragS
*insn_start_frag
;
8091 offsetT insn_start_off
;
8093 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8094 if (IS_ELF
&& x86_used_note
)
8096 if (i
.tm
.cpu_flags
.bitfield
.cpucmov
)
8097 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_CMOV
;
8098 if (i
.tm
.cpu_flags
.bitfield
.cpusse
)
8099 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE
;
8100 if (i
.tm
.cpu_flags
.bitfield
.cpusse2
)
8101 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE2
;
8102 if (i
.tm
.cpu_flags
.bitfield
.cpusse3
)
8103 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE3
;
8104 if (i
.tm
.cpu_flags
.bitfield
.cpussse3
)
8105 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSSE3
;
8106 if (i
.tm
.cpu_flags
.bitfield
.cpusse4_1
)
8107 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE4_1
;
8108 if (i
.tm
.cpu_flags
.bitfield
.cpusse4_2
)
8109 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE4_2
;
8110 if (i
.tm
.cpu_flags
.bitfield
.cpuavx
)
8111 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX
;
8112 if (i
.tm
.cpu_flags
.bitfield
.cpuavx2
)
8113 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX2
;
8114 if (i
.tm
.cpu_flags
.bitfield
.cpufma
)
8115 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_FMA
;
8116 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512f
)
8117 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512F
;
8118 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512cd
)
8119 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512CD
;
8120 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512er
)
8121 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512ER
;
8122 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512pf
)
8123 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512PF
;
8124 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512vl
)
8125 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512VL
;
8126 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512dq
)
8127 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512DQ
;
8128 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512bw
)
8129 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512BW
;
8130 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_4fmaps
)
8131 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_4FMAPS
;
8132 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_4vnniw
)
8133 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_4VNNIW
;
8134 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_bitalg
)
8135 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_BITALG
;
8136 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512ifma
)
8137 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_IFMA
;
8138 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512vbmi
)
8139 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_VBMI
;
8140 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_vbmi2
)
8141 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_VBMI2
;
8142 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_vnni
)
8143 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_VNNI
;
8145 if (i
.tm
.cpu_flags
.bitfield
.cpu8087
8146 || i
.tm
.cpu_flags
.bitfield
.cpu287
8147 || i
.tm
.cpu_flags
.bitfield
.cpu387
8148 || i
.tm
.cpu_flags
.bitfield
.cpu687
8149 || i
.tm
.cpu_flags
.bitfield
.cpufisttp
)
8150 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_X87
;
8151 /* Don't set GNU_PROPERTY_X86_FEATURE_2_MMX for prefetchtXXX nor
8152 Xfence instructions. */
8153 if (i
.tm
.base_opcode
!= 0xf18
8154 && i
.tm
.base_opcode
!= 0xf0d
8155 && i
.tm
.base_opcode
!= 0xfae
8157 || i
.tm
.cpu_flags
.bitfield
.cpummx
8158 || i
.tm
.cpu_flags
.bitfield
.cpua3dnow
8159 || i
.tm
.cpu_flags
.bitfield
.cpua3dnowa
))
8160 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_MMX
;
8162 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XMM
;
8164 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_YMM
;
8166 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_ZMM
;
8167 if (i
.tm
.cpu_flags
.bitfield
.cpufxsr
)
8168 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_FXSR
;
8169 if (i
.tm
.cpu_flags
.bitfield
.cpuxsave
)
8170 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVE
;
8171 if (i
.tm
.cpu_flags
.bitfield
.cpuxsaveopt
)
8172 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVEOPT
;
8173 if (i
.tm
.cpu_flags
.bitfield
.cpuxsavec
)
8174 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVEC
;
8178 /* Tie dwarf2 debug info to the address at the start of the insn.
8179 We can't do this after the insn has been output as the current
8180 frag may have been closed off. eg. by frag_var. */
8181 dwarf2_emit_insn (0);
8183 insn_start_frag
= frag_now
;
8184 insn_start_off
= frag_now_fix ();
8187 if (i
.tm
.opcode_modifier
.jump
)
8189 else if (i
.tm
.opcode_modifier
.jumpbyte
8190 || i
.tm
.opcode_modifier
.jumpdword
)
8192 else if (i
.tm
.opcode_modifier
.jumpintersegment
)
8193 output_interseg_jump ();
8196 /* Output normal instructions here. */
8200 unsigned int prefix
;
8203 && i
.tm
.base_opcode
== 0xfae
8205 && i
.imm_operands
== 1
8206 && (i
.op
[0].imms
->X_add_number
== 0xe8
8207 || i
.op
[0].imms
->X_add_number
== 0xf0
8208 || i
.op
[0].imms
->X_add_number
== 0xf8))
8210 /* Encode lfence, mfence, and sfence as
8211 f0 83 04 24 00 lock addl $0x0, (%{re}sp). */
8212 offsetT val
= 0x240483f0ULL
;
8214 md_number_to_chars (p
, val
, 5);
8218 /* Some processors fail on LOCK prefix. This options makes
8219 assembler ignore LOCK prefix and serves as a workaround. */
8220 if (omit_lock_prefix
)
8222 if (i
.tm
.base_opcode
== LOCK_PREFIX_OPCODE
)
8224 i
.prefix
[LOCK_PREFIX
] = 0;
8227 /* Since the VEX/EVEX prefix contains the implicit prefix, we
8228 don't need the explicit prefix. */
8229 if (!i
.tm
.opcode_modifier
.vex
&& !i
.tm
.opcode_modifier
.evex
)
8231 switch (i
.tm
.opcode_length
)
8234 if (i
.tm
.base_opcode
& 0xff000000)
8236 prefix
= (i
.tm
.base_opcode
>> 24) & 0xff;
8237 add_prefix (prefix
);
8241 if ((i
.tm
.base_opcode
& 0xff0000) != 0)
8243 prefix
= (i
.tm
.base_opcode
>> 16) & 0xff;
8244 if (!i
.tm
.cpu_flags
.bitfield
.cpupadlock
8245 || prefix
!= REPE_PREFIX_OPCODE
8246 || (i
.prefix
[REP_PREFIX
] != REPE_PREFIX_OPCODE
))
8247 add_prefix (prefix
);
8253 /* Check for pseudo prefixes. */
8254 as_bad_where (insn_start_frag
->fr_file
,
8255 insn_start_frag
->fr_line
,
8256 _("pseudo prefix without instruction"));
8262 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
8263 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
8264 R_X86_64_GOTTPOFF relocation so that linker can safely
8265 perform IE->LE optimization. */
8266 if (x86_elf_abi
== X86_64_X32_ABI
8268 && i
.reloc
[0] == BFD_RELOC_X86_64_GOTTPOFF
8269 && i
.prefix
[REX_PREFIX
] == 0)
8270 add_prefix (REX_OPCODE
);
8273 /* The prefix bytes. */
8274 for (j
= ARRAY_SIZE (i
.prefix
), q
= i
.prefix
; j
> 0; j
--, q
++)
8276 FRAG_APPEND_1_CHAR (*q
);
8280 for (j
= 0, q
= i
.prefix
; j
< ARRAY_SIZE (i
.prefix
); j
++, q
++)
8285 /* REX byte is encoded in VEX prefix. */
8289 FRAG_APPEND_1_CHAR (*q
);
8292 /* There should be no other prefixes for instructions
8297 /* For EVEX instructions i.vrex should become 0 after
8298 build_evex_prefix. For VEX instructions upper 16 registers
8299 aren't available, so VREX should be 0. */
8302 /* Now the VEX prefix. */
8303 p
= frag_more (i
.vex
.length
);
8304 for (j
= 0; j
< i
.vex
.length
; j
++)
8305 p
[j
] = i
.vex
.bytes
[j
];
8308 /* Now the opcode; be careful about word order here! */
8309 if (i
.tm
.opcode_length
== 1)
8311 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
8315 switch (i
.tm
.opcode_length
)
8319 *p
++ = (i
.tm
.base_opcode
>> 24) & 0xff;
8320 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
8324 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
8334 /* Put out high byte first: can't use md_number_to_chars! */
8335 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
8336 *p
= i
.tm
.base_opcode
& 0xff;
8339 /* Now the modrm byte and sib byte (if present). */
8340 if (i
.tm
.opcode_modifier
.modrm
)
8342 FRAG_APPEND_1_CHAR ((i
.rm
.regmem
<< 0
8345 /* If i.rm.regmem == ESP (4)
8346 && i.rm.mode != (Register mode)
8348 ==> need second modrm byte. */
8349 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
8351 && !(i
.base_reg
&& i
.base_reg
->reg_type
.bitfield
.word
))
8352 FRAG_APPEND_1_CHAR ((i
.sib
.base
<< 0
8354 | i
.sib
.scale
<< 6));
8357 if (i
.disp_operands
)
8358 output_disp (insn_start_frag
, insn_start_off
);
8361 output_imm (insn_start_frag
, insn_start_off
);
8367 pi ("" /*line*/, &i
);
8369 #endif /* DEBUG386 */
8372 /* Return the size of the displacement operand N. */
8375 disp_size (unsigned int n
)
8379 if (i
.types
[n
].bitfield
.disp64
)
8381 else if (i
.types
[n
].bitfield
.disp8
)
8383 else if (i
.types
[n
].bitfield
.disp16
)
8388 /* Return the size of the immediate operand N. */
8391 imm_size (unsigned int n
)
8394 if (i
.types
[n
].bitfield
.imm64
)
8396 else if (i
.types
[n
].bitfield
.imm8
|| i
.types
[n
].bitfield
.imm8s
)
8398 else if (i
.types
[n
].bitfield
.imm16
)
8404 output_disp (fragS
*insn_start_frag
, offsetT insn_start_off
)
8409 for (n
= 0; n
< i
.operands
; n
++)
8411 if (operand_type_check (i
.types
[n
], disp
))
8413 if (i
.op
[n
].disps
->X_op
== O_constant
)
8415 int size
= disp_size (n
);
8416 offsetT val
= i
.op
[n
].disps
->X_add_number
;
8418 val
= offset_in_range (val
>> (size
== 1 ? i
.memshift
: 0),
8420 p
= frag_more (size
);
8421 md_number_to_chars (p
, val
, size
);
8425 enum bfd_reloc_code_real reloc_type
;
8426 int size
= disp_size (n
);
8427 int sign
= i
.types
[n
].bitfield
.disp32s
;
8428 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
8431 /* We can't have 8 bit displacement here. */
8432 gas_assert (!i
.types
[n
].bitfield
.disp8
);
8434 /* The PC relative address is computed relative
8435 to the instruction boundary, so in case immediate
8436 fields follows, we need to adjust the value. */
8437 if (pcrel
&& i
.imm_operands
)
8442 for (n1
= 0; n1
< i
.operands
; n1
++)
8443 if (operand_type_check (i
.types
[n1
], imm
))
8445 /* Only one immediate is allowed for PC
8446 relative address. */
8447 gas_assert (sz
== 0);
8449 i
.op
[n
].disps
->X_add_number
-= sz
;
8451 /* We should find the immediate. */
8452 gas_assert (sz
!= 0);
8455 p
= frag_more (size
);
8456 reloc_type
= reloc (size
, pcrel
, sign
, i
.reloc
[n
]);
8458 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
8459 && (((reloc_type
== BFD_RELOC_32
8460 || reloc_type
== BFD_RELOC_X86_64_32S
8461 || (reloc_type
== BFD_RELOC_64
8463 && (i
.op
[n
].disps
->X_op
== O_symbol
8464 || (i
.op
[n
].disps
->X_op
== O_add
8465 && ((symbol_get_value_expression
8466 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
8468 || reloc_type
== BFD_RELOC_32_PCREL
))
8472 if (insn_start_frag
== frag_now
)
8473 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
8478 add
= insn_start_frag
->fr_fix
- insn_start_off
;
8479 for (fr
= insn_start_frag
->fr_next
;
8480 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
8482 add
+= p
- frag_now
->fr_literal
;
8487 reloc_type
= BFD_RELOC_386_GOTPC
;
8488 i
.op
[n
].imms
->X_add_number
+= add
;
8490 else if (reloc_type
== BFD_RELOC_64
)
8491 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
8493 /* Don't do the adjustment for x86-64, as there
8494 the pcrel addressing is relative to the _next_
8495 insn, and that is taken care of in other code. */
8496 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
8498 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
8499 size
, i
.op
[n
].disps
, pcrel
,
8501 /* Check for "call/jmp *mem", "mov mem, %reg",
8502 "test %reg, mem" and "binop mem, %reg" where binop
8503 is one of adc, add, and, cmp, or, sbb, sub, xor
8504 instructions without data prefix. Always generate
8505 R_386_GOT32X for "sym*GOT" operand in 32-bit mode. */
8506 if (i
.prefix
[DATA_PREFIX
] == 0
8507 && (generate_relax_relocations
8510 && i
.rm
.regmem
== 5))
8512 || (i
.rm
.mode
== 0 && i
.rm
.regmem
== 5))
8513 && ((i
.operands
== 1
8514 && i
.tm
.base_opcode
== 0xff
8515 && (i
.rm
.reg
== 2 || i
.rm
.reg
== 4))
8517 && (i
.tm
.base_opcode
== 0x8b
8518 || i
.tm
.base_opcode
== 0x85
8519 || (i
.tm
.base_opcode
& 0xc7) == 0x03))))
8523 fixP
->fx_tcbit
= i
.rex
!= 0;
8525 && (i
.base_reg
->reg_num
== RegIP
))
8526 fixP
->fx_tcbit2
= 1;
8529 fixP
->fx_tcbit2
= 1;
8537 output_imm (fragS
*insn_start_frag
, offsetT insn_start_off
)
8542 for (n
= 0; n
< i
.operands
; n
++)
8544 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
8545 if (i
.rounding
&& (int) n
== i
.rounding
->operand
)
8548 if (operand_type_check (i
.types
[n
], imm
))
8550 if (i
.op
[n
].imms
->X_op
== O_constant
)
8552 int size
= imm_size (n
);
8555 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
8557 p
= frag_more (size
);
8558 md_number_to_chars (p
, val
, size
);
8562 /* Not absolute_section.
8563 Need a 32-bit fixup (don't support 8bit
8564 non-absolute imms). Try to support other
8566 enum bfd_reloc_code_real reloc_type
;
8567 int size
= imm_size (n
);
8570 if (i
.types
[n
].bitfield
.imm32s
8571 && (i
.suffix
== QWORD_MNEM_SUFFIX
8572 || (!i
.suffix
&& i
.tm
.opcode_modifier
.no_lsuf
)))
8577 p
= frag_more (size
);
8578 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
8580 /* This is tough to explain. We end up with this one if we
8581 * have operands that look like
8582 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
8583 * obtain the absolute address of the GOT, and it is strongly
8584 * preferable from a performance point of view to avoid using
8585 * a runtime relocation for this. The actual sequence of
8586 * instructions often look something like:
8591 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
8593 * The call and pop essentially return the absolute address
8594 * of the label .L66 and store it in %ebx. The linker itself
8595 * will ultimately change the first operand of the addl so
8596 * that %ebx points to the GOT, but to keep things simple, the
8597 * .o file must have this operand set so that it generates not
8598 * the absolute address of .L66, but the absolute address of
8599 * itself. This allows the linker itself simply treat a GOTPC
8600 * relocation as asking for a pcrel offset to the GOT to be
8601 * added in, and the addend of the relocation is stored in the
8602 * operand field for the instruction itself.
8604 * Our job here is to fix the operand so that it would add
8605 * the correct offset so that %ebx would point to itself. The
8606 * thing that is tricky is that .-.L66 will point to the
8607 * beginning of the instruction, so we need to further modify
8608 * the operand so that it will point to itself. There are
8609 * other cases where you have something like:
8611 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
8613 * and here no correction would be required. Internally in
8614 * the assembler we treat operands of this form as not being
8615 * pcrel since the '.' is explicitly mentioned, and I wonder
8616 * whether it would simplify matters to do it this way. Who
8617 * knows. In earlier versions of the PIC patches, the
8618 * pcrel_adjust field was used to store the correction, but
8619 * since the expression is not pcrel, I felt it would be
8620 * confusing to do it this way. */
8622 if ((reloc_type
== BFD_RELOC_32
8623 || reloc_type
== BFD_RELOC_X86_64_32S
8624 || reloc_type
== BFD_RELOC_64
)
8626 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
8627 && (i
.op
[n
].imms
->X_op
== O_symbol
8628 || (i
.op
[n
].imms
->X_op
== O_add
8629 && ((symbol_get_value_expression
8630 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
8635 if (insn_start_frag
== frag_now
)
8636 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
8641 add
= insn_start_frag
->fr_fix
- insn_start_off
;
8642 for (fr
= insn_start_frag
->fr_next
;
8643 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
8645 add
+= p
- frag_now
->fr_literal
;
8649 reloc_type
= BFD_RELOC_386_GOTPC
;
8651 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
8653 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
8654 i
.op
[n
].imms
->X_add_number
+= add
;
8656 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
8657 i
.op
[n
].imms
, 0, reloc_type
);
8663 /* x86_cons_fix_new is called via the expression parsing code when a
8664 reloc is needed. We use this hook to get the correct .got reloc. */
8665 static int cons_sign
= -1;
8668 x86_cons_fix_new (fragS
*frag
, unsigned int off
, unsigned int len
,
8669 expressionS
*exp
, bfd_reloc_code_real_type r
)
8671 r
= reloc (len
, 0, cons_sign
, r
);
8674 if (exp
->X_op
== O_secrel
)
8676 exp
->X_op
= O_symbol
;
8677 r
= BFD_RELOC_32_SECREL
;
8681 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
8684 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
8685 purpose of the `.dc.a' internal pseudo-op. */
8688 x86_address_bytes (void)
8690 if ((stdoutput
->arch_info
->mach
& bfd_mach_x64_32
))
8692 return stdoutput
->arch_info
->bits_per_address
/ 8;
8695 #if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
8697 # define lex_got(reloc, adjust, types) NULL
8699 /* Parse operands of the form
8700 <symbol>@GOTOFF+<nnn>
8701 and similar .plt or .got references.
8703 If we find one, set up the correct relocation in RELOC and copy the
8704 input string, minus the `@GOTOFF' into a malloc'd buffer for
8705 parsing by the calling routine. Return this buffer, and if ADJUST
8706 is non-null set it to the length of the string we removed from the
8707 input line. Otherwise return NULL. */
8709 lex_got (enum bfd_reloc_code_real
*rel
,
8711 i386_operand_type
*types
)
8713 /* Some of the relocations depend on the size of what field is to
8714 be relocated. But in our callers i386_immediate and i386_displacement
8715 we don't yet know the operand size (this will be set by insn
8716 matching). Hence we record the word32 relocation here,
8717 and adjust the reloc according to the real size in reloc(). */
8718 static const struct {
8721 const enum bfd_reloc_code_real rel
[2];
8722 const i386_operand_type types64
;
8724 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8725 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32
,
8727 OPERAND_TYPE_IMM32_64
},
8729 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real
,
8730 BFD_RELOC_X86_64_PLTOFF64
},
8731 OPERAND_TYPE_IMM64
},
8732 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32
,
8733 BFD_RELOC_X86_64_PLT32
},
8734 OPERAND_TYPE_IMM32_32S_DISP32
},
8735 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real
,
8736 BFD_RELOC_X86_64_GOTPLT64
},
8737 OPERAND_TYPE_IMM64_DISP64
},
8738 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF
,
8739 BFD_RELOC_X86_64_GOTOFF64
},
8740 OPERAND_TYPE_IMM64_DISP64
},
8741 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real
,
8742 BFD_RELOC_X86_64_GOTPCREL
},
8743 OPERAND_TYPE_IMM32_32S_DISP32
},
8744 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD
,
8745 BFD_RELOC_X86_64_TLSGD
},
8746 OPERAND_TYPE_IMM32_32S_DISP32
},
8747 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM
,
8748 _dummy_first_bfd_reloc_code_real
},
8749 OPERAND_TYPE_NONE
},
8750 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real
,
8751 BFD_RELOC_X86_64_TLSLD
},
8752 OPERAND_TYPE_IMM32_32S_DISP32
},
8753 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32
,
8754 BFD_RELOC_X86_64_GOTTPOFF
},
8755 OPERAND_TYPE_IMM32_32S_DISP32
},
8756 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32
,
8757 BFD_RELOC_X86_64_TPOFF32
},
8758 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
8759 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE
,
8760 _dummy_first_bfd_reloc_code_real
},
8761 OPERAND_TYPE_NONE
},
8762 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32
,
8763 BFD_RELOC_X86_64_DTPOFF32
},
8764 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
8765 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE
,
8766 _dummy_first_bfd_reloc_code_real
},
8767 OPERAND_TYPE_NONE
},
8768 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE
,
8769 _dummy_first_bfd_reloc_code_real
},
8770 OPERAND_TYPE_NONE
},
8771 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32
,
8772 BFD_RELOC_X86_64_GOT32
},
8773 OPERAND_TYPE_IMM32_32S_64_DISP32
},
8774 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC
,
8775 BFD_RELOC_X86_64_GOTPC32_TLSDESC
},
8776 OPERAND_TYPE_IMM32_32S_DISP32
},
8777 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL
,
8778 BFD_RELOC_X86_64_TLSDESC_CALL
},
8779 OPERAND_TYPE_IMM32_32S_DISP32
},
8784 #if defined (OBJ_MAYBE_ELF)
8789 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
8790 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
8793 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
8795 int len
= gotrel
[j
].len
;
8796 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
8798 if (gotrel
[j
].rel
[object_64bit
] != 0)
8801 char *tmpbuf
, *past_reloc
;
8803 *rel
= gotrel
[j
].rel
[object_64bit
];
8807 if (flag_code
!= CODE_64BIT
)
8809 types
->bitfield
.imm32
= 1;
8810 types
->bitfield
.disp32
= 1;
8813 *types
= gotrel
[j
].types64
;
8816 if (j
!= 0 && GOT_symbol
== NULL
)
8817 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
8819 /* The length of the first part of our input line. */
8820 first
= cp
- input_line_pointer
;
8822 /* The second part goes from after the reloc token until
8823 (and including) an end_of_line char or comma. */
8824 past_reloc
= cp
+ 1 + len
;
8826 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
8828 second
= cp
+ 1 - past_reloc
;
8830 /* Allocate and copy string. The trailing NUL shouldn't
8831 be necessary, but be safe. */
8832 tmpbuf
= XNEWVEC (char, first
+ second
+ 2);
8833 memcpy (tmpbuf
, input_line_pointer
, first
);
8834 if (second
!= 0 && *past_reloc
!= ' ')
8835 /* Replace the relocation token with ' ', so that
8836 errors like foo@GOTOFF1 will be detected. */
8837 tmpbuf
[first
++] = ' ';
8839 /* Increment length by 1 if the relocation token is
8844 memcpy (tmpbuf
+ first
, past_reloc
, second
);
8845 tmpbuf
[first
+ second
] = '\0';
8849 as_bad (_("@%s reloc is not supported with %d-bit output format"),
8850 gotrel
[j
].str
, 1 << (5 + object_64bit
));
8855 /* Might be a symbol version string. Don't as_bad here. */
8864 /* Parse operands of the form
8865 <symbol>@SECREL32+<nnn>
8867 If we find one, set up the correct relocation in RELOC and copy the
8868 input string, minus the `@SECREL32' into a malloc'd buffer for
8869 parsing by the calling routine. Return this buffer, and if ADJUST
8870 is non-null set it to the length of the string we removed from the
8871 input line. Otherwise return NULL.
8873 This function is copied from the ELF version above adjusted for PE targets. */
8876 lex_got (enum bfd_reloc_code_real
*rel ATTRIBUTE_UNUSED
,
8877 int *adjust ATTRIBUTE_UNUSED
,
8878 i386_operand_type
*types
)
8884 const enum bfd_reloc_code_real rel
[2];
8885 const i386_operand_type types64
;
8889 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL
,
8890 BFD_RELOC_32_SECREL
},
8891 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
8897 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
8898 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
8901 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
8903 int len
= gotrel
[j
].len
;
8905 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
8907 if (gotrel
[j
].rel
[object_64bit
] != 0)
8910 char *tmpbuf
, *past_reloc
;
8912 *rel
= gotrel
[j
].rel
[object_64bit
];
8918 if (flag_code
!= CODE_64BIT
)
8920 types
->bitfield
.imm32
= 1;
8921 types
->bitfield
.disp32
= 1;
8924 *types
= gotrel
[j
].types64
;
8927 /* The length of the first part of our input line. */
8928 first
= cp
- input_line_pointer
;
8930 /* The second part goes from after the reloc token until
8931 (and including) an end_of_line char or comma. */
8932 past_reloc
= cp
+ 1 + len
;
8934 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
8936 second
= cp
+ 1 - past_reloc
;
8938 /* Allocate and copy string. The trailing NUL shouldn't
8939 be necessary, but be safe. */
8940 tmpbuf
= XNEWVEC (char, first
+ second
+ 2);
8941 memcpy (tmpbuf
, input_line_pointer
, first
);
8942 if (second
!= 0 && *past_reloc
!= ' ')
8943 /* Replace the relocation token with ' ', so that
8944 errors like foo@SECLREL321 will be detected. */
8945 tmpbuf
[first
++] = ' ';
8946 memcpy (tmpbuf
+ first
, past_reloc
, second
);
8947 tmpbuf
[first
+ second
] = '\0';
8951 as_bad (_("@%s reloc is not supported with %d-bit output format"),
8952 gotrel
[j
].str
, 1 << (5 + object_64bit
));
8957 /* Might be a symbol version string. Don't as_bad here. */
8963 bfd_reloc_code_real_type
8964 x86_cons (expressionS
*exp
, int size
)
8966 bfd_reloc_code_real_type got_reloc
= NO_RELOC
;
8968 intel_syntax
= -intel_syntax
;
8971 if (size
== 4 || (object_64bit
&& size
== 8))
8973 /* Handle @GOTOFF and the like in an expression. */
8975 char *gotfree_input_line
;
8978 save
= input_line_pointer
;
8979 gotfree_input_line
= lex_got (&got_reloc
, &adjust
, NULL
);
8980 if (gotfree_input_line
)
8981 input_line_pointer
= gotfree_input_line
;
8985 if (gotfree_input_line
)
8987 /* expression () has merrily parsed up to the end of line,
8988 or a comma - in the wrong buffer. Transfer how far
8989 input_line_pointer has moved to the right buffer. */
8990 input_line_pointer
= (save
8991 + (input_line_pointer
- gotfree_input_line
)
8993 free (gotfree_input_line
);
8994 if (exp
->X_op
== O_constant
8995 || exp
->X_op
== O_absent
8996 || exp
->X_op
== O_illegal
8997 || exp
->X_op
== O_register
8998 || exp
->X_op
== O_big
)
9000 char c
= *input_line_pointer
;
9001 *input_line_pointer
= 0;
9002 as_bad (_("missing or invalid expression `%s'"), save
);
9003 *input_line_pointer
= c
;
9005 else if ((got_reloc
== BFD_RELOC_386_PLT32
9006 || got_reloc
== BFD_RELOC_X86_64_PLT32
)
9007 && exp
->X_op
!= O_symbol
)
9009 char c
= *input_line_pointer
;
9010 *input_line_pointer
= 0;
9011 as_bad (_("invalid PLT expression `%s'"), save
);
9012 *input_line_pointer
= c
;
9019 intel_syntax
= -intel_syntax
;
9022 i386_intel_simplify (exp
);
9028 signed_cons (int size
)
9030 if (flag_code
== CODE_64BIT
)
9038 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
9045 if (exp
.X_op
== O_symbol
)
9046 exp
.X_op
= O_secrel
;
9048 emit_expr (&exp
, 4);
9050 while (*input_line_pointer
++ == ',');
9052 input_line_pointer
--;
9053 demand_empty_rest_of_line ();
9057 /* Handle Vector operations. */
9060 check_VecOperations (char *op_string
, char *op_end
)
9062 const reg_entry
*mask
;
9067 && (op_end
== NULL
|| op_string
< op_end
))
9070 if (*op_string
== '{')
9074 /* Check broadcasts. */
9075 if (strncmp (op_string
, "1to", 3) == 0)
9080 goto duplicated_vec_op
;
9083 if (*op_string
== '8')
9085 else if (*op_string
== '4')
9087 else if (*op_string
== '2')
9089 else if (*op_string
== '1'
9090 && *(op_string
+1) == '6')
9097 as_bad (_("Unsupported broadcast: `%s'"), saved
);
9102 broadcast_op
.type
= bcst_type
;
9103 broadcast_op
.operand
= this_operand
;
9104 broadcast_op
.bytes
= 0;
9105 i
.broadcast
= &broadcast_op
;
9107 /* Check masking operation. */
9108 else if ((mask
= parse_register (op_string
, &end_op
)) != NULL
)
9110 /* k0 can't be used for write mask. */
9111 if (!mask
->reg_type
.bitfield
.regmask
|| mask
->reg_num
== 0)
9113 as_bad (_("`%s%s' can't be used for write mask"),
9114 register_prefix
, mask
->reg_name
);
9120 mask_op
.mask
= mask
;
9121 mask_op
.zeroing
= 0;
9122 mask_op
.operand
= this_operand
;
9128 goto duplicated_vec_op
;
9130 i
.mask
->mask
= mask
;
9132 /* Only "{z}" is allowed here. No need to check
9133 zeroing mask explicitly. */
9134 if (i
.mask
->operand
!= this_operand
)
9136 as_bad (_("invalid write mask `%s'"), saved
);
9143 /* Check zeroing-flag for masking operation. */
9144 else if (*op_string
== 'z')
9148 mask_op
.mask
= NULL
;
9149 mask_op
.zeroing
= 1;
9150 mask_op
.operand
= this_operand
;
9155 if (i
.mask
->zeroing
)
9158 as_bad (_("duplicated `%s'"), saved
);
9162 i
.mask
->zeroing
= 1;
9164 /* Only "{%k}" is allowed here. No need to check mask
9165 register explicitly. */
9166 if (i
.mask
->operand
!= this_operand
)
9168 as_bad (_("invalid zeroing-masking `%s'"),
9177 goto unknown_vec_op
;
9179 if (*op_string
!= '}')
9181 as_bad (_("missing `}' in `%s'"), saved
);
9186 /* Strip whitespace since the addition of pseudo prefixes
9187 changed how the scrubber treats '{'. */
9188 if (is_space_char (*op_string
))
9194 /* We don't know this one. */
9195 as_bad (_("unknown vector operation: `%s'"), saved
);
9199 if (i
.mask
&& i
.mask
->zeroing
&& !i
.mask
->mask
)
9201 as_bad (_("zeroing-masking only allowed with write mask"));
9209 i386_immediate (char *imm_start
)
9211 char *save_input_line_pointer
;
9212 char *gotfree_input_line
;
9215 i386_operand_type types
;
9217 operand_type_set (&types
, ~0);
9219 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
9221 as_bad (_("at most %d immediate operands are allowed"),
9222 MAX_IMMEDIATE_OPERANDS
);
9226 exp
= &im_expressions
[i
.imm_operands
++];
9227 i
.op
[this_operand
].imms
= exp
;
9229 if (is_space_char (*imm_start
))
9232 save_input_line_pointer
= input_line_pointer
;
9233 input_line_pointer
= imm_start
;
9235 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
9236 if (gotfree_input_line
)
9237 input_line_pointer
= gotfree_input_line
;
9239 exp_seg
= expression (exp
);
9243 /* Handle vector operations. */
9244 if (*input_line_pointer
== '{')
9246 input_line_pointer
= check_VecOperations (input_line_pointer
,
9248 if (input_line_pointer
== NULL
)
9252 if (*input_line_pointer
)
9253 as_bad (_("junk `%s' after expression"), input_line_pointer
);
9255 input_line_pointer
= save_input_line_pointer
;
9256 if (gotfree_input_line
)
9258 free (gotfree_input_line
);
9260 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
9261 exp
->X_op
= O_illegal
;
9264 return i386_finalize_immediate (exp_seg
, exp
, types
, imm_start
);
9268 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
9269 i386_operand_type types
, const char *imm_start
)
9271 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_illegal
|| exp
->X_op
== O_big
)
9274 as_bad (_("missing or invalid immediate expression `%s'"),
9278 else if (exp
->X_op
== O_constant
)
9280 /* Size it properly later. */
9281 i
.types
[this_operand
].bitfield
.imm64
= 1;
9282 /* If not 64bit, sign extend val. */
9283 if (flag_code
!= CODE_64BIT
9284 && (exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
9286 = (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
9288 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
9289 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
9290 && exp_seg
!= absolute_section
9291 && exp_seg
!= text_section
9292 && exp_seg
!= data_section
9293 && exp_seg
!= bss_section
9294 && exp_seg
!= undefined_section
9295 && !bfd_is_com_section (exp_seg
))
9297 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
9301 else if (!intel_syntax
&& exp_seg
== reg_section
)
9304 as_bad (_("illegal immediate register operand %s"), imm_start
);
9309 /* This is an address. The size of the address will be
9310 determined later, depending on destination register,
9311 suffix, or the default for the section. */
9312 i
.types
[this_operand
].bitfield
.imm8
= 1;
9313 i
.types
[this_operand
].bitfield
.imm16
= 1;
9314 i
.types
[this_operand
].bitfield
.imm32
= 1;
9315 i
.types
[this_operand
].bitfield
.imm32s
= 1;
9316 i
.types
[this_operand
].bitfield
.imm64
= 1;
9317 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
9325 i386_scale (char *scale
)
9328 char *save
= input_line_pointer
;
9330 input_line_pointer
= scale
;
9331 val
= get_absolute_expression ();
9336 i
.log2_scale_factor
= 0;
9339 i
.log2_scale_factor
= 1;
9342 i
.log2_scale_factor
= 2;
9345 i
.log2_scale_factor
= 3;
9349 char sep
= *input_line_pointer
;
9351 *input_line_pointer
= '\0';
9352 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
9354 *input_line_pointer
= sep
;
9355 input_line_pointer
= save
;
9359 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
9361 as_warn (_("scale factor of %d without an index register"),
9362 1 << i
.log2_scale_factor
);
9363 i
.log2_scale_factor
= 0;
9365 scale
= input_line_pointer
;
9366 input_line_pointer
= save
;
9371 i386_displacement (char *disp_start
, char *disp_end
)
9375 char *save_input_line_pointer
;
9376 char *gotfree_input_line
;
9378 i386_operand_type bigdisp
, types
= anydisp
;
9381 if (i
.disp_operands
== MAX_MEMORY_OPERANDS
)
9383 as_bad (_("at most %d displacement operands are allowed"),
9384 MAX_MEMORY_OPERANDS
);
9388 operand_type_set (&bigdisp
, 0);
9389 if ((i
.types
[this_operand
].bitfield
.jumpabsolute
)
9390 || (!current_templates
->start
->opcode_modifier
.jump
9391 && !current_templates
->start
->opcode_modifier
.jumpdword
))
9393 bigdisp
.bitfield
.disp32
= 1;
9394 override
= (i
.prefix
[ADDR_PREFIX
] != 0);
9395 if (flag_code
== CODE_64BIT
)
9399 bigdisp
.bitfield
.disp32s
= 1;
9400 bigdisp
.bitfield
.disp64
= 1;
9403 else if ((flag_code
== CODE_16BIT
) ^ override
)
9405 bigdisp
.bitfield
.disp32
= 0;
9406 bigdisp
.bitfield
.disp16
= 1;
9411 /* For PC-relative branches, the width of the displacement
9412 is dependent upon data size, not address size. */
9413 override
= (i
.prefix
[DATA_PREFIX
] != 0);
9414 if (flag_code
== CODE_64BIT
)
9416 if (override
|| i
.suffix
== WORD_MNEM_SUFFIX
)
9417 bigdisp
.bitfield
.disp16
= 1;
9420 bigdisp
.bitfield
.disp32
= 1;
9421 bigdisp
.bitfield
.disp32s
= 1;
9427 override
= (i
.suffix
== (flag_code
!= CODE_16BIT
9429 : LONG_MNEM_SUFFIX
));
9430 bigdisp
.bitfield
.disp32
= 1;
9431 if ((flag_code
== CODE_16BIT
) ^ override
)
9433 bigdisp
.bitfield
.disp32
= 0;
9434 bigdisp
.bitfield
.disp16
= 1;
9438 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
9441 exp
= &disp_expressions
[i
.disp_operands
];
9442 i
.op
[this_operand
].disps
= exp
;
9444 save_input_line_pointer
= input_line_pointer
;
9445 input_line_pointer
= disp_start
;
9446 END_STRING_AND_SAVE (disp_end
);
9448 #ifndef GCC_ASM_O_HACK
9449 #define GCC_ASM_O_HACK 0
9452 END_STRING_AND_SAVE (disp_end
+ 1);
9453 if (i
.types
[this_operand
].bitfield
.baseIndex
9454 && displacement_string_end
[-1] == '+')
9456 /* This hack is to avoid a warning when using the "o"
9457 constraint within gcc asm statements.
9460 #define _set_tssldt_desc(n,addr,limit,type) \
9461 __asm__ __volatile__ ( \
9463 "movw %w1,2+%0\n\t" \
9465 "movb %b1,4+%0\n\t" \
9466 "movb %4,5+%0\n\t" \
9467 "movb $0,6+%0\n\t" \
9468 "movb %h1,7+%0\n\t" \
9470 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
9472 This works great except that the output assembler ends
9473 up looking a bit weird if it turns out that there is
9474 no offset. You end up producing code that looks like:
9487 So here we provide the missing zero. */
9489 *displacement_string_end
= '0';
9492 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
9493 if (gotfree_input_line
)
9494 input_line_pointer
= gotfree_input_line
;
9496 exp_seg
= expression (exp
);
9499 if (*input_line_pointer
)
9500 as_bad (_("junk `%s' after expression"), input_line_pointer
);
9502 RESTORE_END_STRING (disp_end
+ 1);
9504 input_line_pointer
= save_input_line_pointer
;
9505 if (gotfree_input_line
)
9507 free (gotfree_input_line
);
9509 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
9510 exp
->X_op
= O_illegal
;
9513 ret
= i386_finalize_displacement (exp_seg
, exp
, types
, disp_start
);
9515 RESTORE_END_STRING (disp_end
);
9521 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
9522 i386_operand_type types
, const char *disp_start
)
9524 i386_operand_type bigdisp
;
9527 /* We do this to make sure that the section symbol is in
9528 the symbol table. We will ultimately change the relocation
9529 to be relative to the beginning of the section. */
9530 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
9531 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
9532 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
9534 if (exp
->X_op
!= O_symbol
)
9537 if (S_IS_LOCAL (exp
->X_add_symbol
)
9538 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
9539 && S_GET_SEGMENT (exp
->X_add_symbol
) != expr_section
)
9540 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
9541 exp
->X_op
= O_subtract
;
9542 exp
->X_op_symbol
= GOT_symbol
;
9543 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
9544 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
9545 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
9546 i
.reloc
[this_operand
] = BFD_RELOC_64
;
9548 i
.reloc
[this_operand
] = BFD_RELOC_32
;
9551 else if (exp
->X_op
== O_absent
9552 || exp
->X_op
== O_illegal
9553 || exp
->X_op
== O_big
)
9556 as_bad (_("missing or invalid displacement expression `%s'"),
9561 else if (flag_code
== CODE_64BIT
9562 && !i
.prefix
[ADDR_PREFIX
]
9563 && exp
->X_op
== O_constant
)
9565 /* Since displacement is signed extended to 64bit, don't allow
9566 disp32 and turn off disp32s if they are out of range. */
9567 i
.types
[this_operand
].bitfield
.disp32
= 0;
9568 if (!fits_in_signed_long (exp
->X_add_number
))
9570 i
.types
[this_operand
].bitfield
.disp32s
= 0;
9571 if (i
.types
[this_operand
].bitfield
.baseindex
)
9573 as_bad (_("0x%lx out range of signed 32bit displacement"),
9574 (long) exp
->X_add_number
);
9580 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
9581 else if (exp
->X_op
!= O_constant
9582 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
9583 && exp_seg
!= absolute_section
9584 && exp_seg
!= text_section
9585 && exp_seg
!= data_section
9586 && exp_seg
!= bss_section
9587 && exp_seg
!= undefined_section
9588 && !bfd_is_com_section (exp_seg
))
9590 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
9595 /* Check if this is a displacement only operand. */
9596 bigdisp
= i
.types
[this_operand
];
9597 bigdisp
.bitfield
.disp8
= 0;
9598 bigdisp
.bitfield
.disp16
= 0;
9599 bigdisp
.bitfield
.disp32
= 0;
9600 bigdisp
.bitfield
.disp32s
= 0;
9601 bigdisp
.bitfield
.disp64
= 0;
9602 if (operand_type_all_zero (&bigdisp
))
9603 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
9609 /* Return the active addressing mode, taking address override and
9610 registers forming the address into consideration. Update the
9611 address override prefix if necessary. */
9613 static enum flag_code
9614 i386_addressing_mode (void)
9616 enum flag_code addr_mode
;
9618 if (i
.prefix
[ADDR_PREFIX
])
9619 addr_mode
= flag_code
== CODE_32BIT
? CODE_16BIT
: CODE_32BIT
;
9622 addr_mode
= flag_code
;
9624 #if INFER_ADDR_PREFIX
9625 if (i
.mem_operands
== 0)
9627 /* Infer address prefix from the first memory operand. */
9628 const reg_entry
*addr_reg
= i
.base_reg
;
9630 if (addr_reg
== NULL
)
9631 addr_reg
= i
.index_reg
;
9635 if (addr_reg
->reg_type
.bitfield
.dword
)
9636 addr_mode
= CODE_32BIT
;
9637 else if (flag_code
!= CODE_64BIT
9638 && addr_reg
->reg_type
.bitfield
.word
)
9639 addr_mode
= CODE_16BIT
;
9641 if (addr_mode
!= flag_code
)
9643 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
9645 /* Change the size of any displacement too. At most one
9646 of Disp16 or Disp32 is set.
9647 FIXME. There doesn't seem to be any real need for
9648 separate Disp16 and Disp32 flags. The same goes for
9649 Imm16 and Imm32. Removing them would probably clean
9650 up the code quite a lot. */
9651 if (flag_code
!= CODE_64BIT
9652 && (i
.types
[this_operand
].bitfield
.disp16
9653 || i
.types
[this_operand
].bitfield
.disp32
))
9654 i
.types
[this_operand
]
9655 = operand_type_xor (i
.types
[this_operand
], disp16_32
);
9665 /* Make sure the memory operand we've been dealt is valid.
9666 Return 1 on success, 0 on a failure. */
9669 i386_index_check (const char *operand_string
)
9671 const char *kind
= "base/index";
9672 enum flag_code addr_mode
= i386_addressing_mode ();
9674 if (current_templates
->start
->opcode_modifier
.isstring
9675 && !current_templates
->start
->opcode_modifier
.immext
9676 && (current_templates
->end
[-1].opcode_modifier
.isstring
9679 /* Memory operands of string insns are special in that they only allow
9680 a single register (rDI, rSI, or rBX) as their memory address. */
9681 const reg_entry
*expected_reg
;
9682 static const char *di_si
[][2] =
9688 static const char *bx
[] = { "ebx", "bx", "rbx" };
9690 kind
= "string address";
9692 if (current_templates
->start
->opcode_modifier
.repprefixok
)
9694 i386_operand_type type
= current_templates
->end
[-1].operand_types
[0];
9696 if (!type
.bitfield
.baseindex
9697 || ((!i
.mem_operands
!= !intel_syntax
)
9698 && current_templates
->end
[-1].operand_types
[1]
9699 .bitfield
.baseindex
))
9700 type
= current_templates
->end
[-1].operand_types
[1];
9701 expected_reg
= hash_find (reg_hash
,
9702 di_si
[addr_mode
][type
.bitfield
.esseg
]);
9706 expected_reg
= hash_find (reg_hash
, bx
[addr_mode
]);
9708 if (i
.base_reg
!= expected_reg
9710 || operand_type_check (i
.types
[this_operand
], disp
))
9712 /* The second memory operand must have the same size as
9716 && !((addr_mode
== CODE_64BIT
9717 && i
.base_reg
->reg_type
.bitfield
.qword
)
9718 || (addr_mode
== CODE_32BIT
9719 ? i
.base_reg
->reg_type
.bitfield
.dword
9720 : i
.base_reg
->reg_type
.bitfield
.word
)))
9723 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
9725 intel_syntax
? '[' : '(',
9727 expected_reg
->reg_name
,
9728 intel_syntax
? ']' : ')');
9735 as_bad (_("`%s' is not a valid %s expression"),
9736 operand_string
, kind
);
9741 if (addr_mode
!= CODE_16BIT
)
9743 /* 32-bit/64-bit checks. */
9745 && ((addr_mode
== CODE_64BIT
9746 ? !i
.base_reg
->reg_type
.bitfield
.qword
9747 : !i
.base_reg
->reg_type
.bitfield
.dword
)
9748 || (i
.index_reg
&& i
.base_reg
->reg_num
== RegIP
)
9749 || i
.base_reg
->reg_num
== RegIZ
))
9751 && !i
.index_reg
->reg_type
.bitfield
.xmmword
9752 && !i
.index_reg
->reg_type
.bitfield
.ymmword
9753 && !i
.index_reg
->reg_type
.bitfield
.zmmword
9754 && ((addr_mode
== CODE_64BIT
9755 ? !i
.index_reg
->reg_type
.bitfield
.qword
9756 : !i
.index_reg
->reg_type
.bitfield
.dword
)
9757 || !i
.index_reg
->reg_type
.bitfield
.baseindex
)))
9760 /* bndmk, bndldx, and bndstx have special restrictions. */
9761 if (current_templates
->start
->base_opcode
== 0xf30f1b
9762 || (current_templates
->start
->base_opcode
& ~1) == 0x0f1a)
9764 /* They cannot use RIP-relative addressing. */
9765 if (i
.base_reg
&& i
.base_reg
->reg_num
== RegIP
)
9767 as_bad (_("`%s' cannot be used here"), operand_string
);
9771 /* bndldx and bndstx ignore their scale factor. */
9772 if (current_templates
->start
->base_opcode
!= 0xf30f1b
9773 && i
.log2_scale_factor
)
9774 as_warn (_("register scaling is being ignored here"));
9779 /* 16-bit checks. */
9781 && (!i
.base_reg
->reg_type
.bitfield
.word
9782 || !i
.base_reg
->reg_type
.bitfield
.baseindex
))
9784 && (!i
.index_reg
->reg_type
.bitfield
.word
9785 || !i
.index_reg
->reg_type
.bitfield
.baseindex
9787 && i
.base_reg
->reg_num
< 6
9788 && i
.index_reg
->reg_num
>= 6
9789 && i
.log2_scale_factor
== 0))))
9796 /* Handle vector immediates. */
9799 RC_SAE_immediate (const char *imm_start
)
9801 unsigned int match_found
, j
;
9802 const char *pstr
= imm_start
;
9810 for (j
= 0; j
< ARRAY_SIZE (RC_NamesTable
); j
++)
9812 if (!strncmp (pstr
, RC_NamesTable
[j
].name
, RC_NamesTable
[j
].len
))
9816 rc_op
.type
= RC_NamesTable
[j
].type
;
9817 rc_op
.operand
= this_operand
;
9818 i
.rounding
= &rc_op
;
9822 as_bad (_("duplicated `%s'"), imm_start
);
9825 pstr
+= RC_NamesTable
[j
].len
;
9835 as_bad (_("Missing '}': '%s'"), imm_start
);
9838 /* RC/SAE immediate string should contain nothing more. */;
9841 as_bad (_("Junk after '}': '%s'"), imm_start
);
9845 exp
= &im_expressions
[i
.imm_operands
++];
9846 i
.op
[this_operand
].imms
= exp
;
9848 exp
->X_op
= O_constant
;
9849 exp
->X_add_number
= 0;
9850 exp
->X_add_symbol
= (symbolS
*) 0;
9851 exp
->X_op_symbol
= (symbolS
*) 0;
9853 i
.types
[this_operand
].bitfield
.imm8
= 1;
9857 /* Only string instructions can have a second memory operand, so
9858 reduce current_templates to just those if it contains any. */
9860 maybe_adjust_templates (void)
9862 const insn_template
*t
;
9864 gas_assert (i
.mem_operands
== 1);
9866 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
9867 if (t
->opcode_modifier
.isstring
)
9870 if (t
< current_templates
->end
)
9872 static templates aux_templates
;
9873 bfd_boolean recheck
;
9875 aux_templates
.start
= t
;
9876 for (; t
< current_templates
->end
; ++t
)
9877 if (!t
->opcode_modifier
.isstring
)
9879 aux_templates
.end
= t
;
9881 /* Determine whether to re-check the first memory operand. */
9882 recheck
= (aux_templates
.start
!= current_templates
->start
9883 || t
!= current_templates
->end
);
9885 current_templates
= &aux_templates
;
9890 if (i
.memop1_string
!= NULL
9891 && i386_index_check (i
.memop1_string
) == 0)
9900 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
9904 i386_att_operand (char *operand_string
)
9908 char *op_string
= operand_string
;
9910 if (is_space_char (*op_string
))
9913 /* We check for an absolute prefix (differentiating,
9914 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
9915 if (*op_string
== ABSOLUTE_PREFIX
)
9918 if (is_space_char (*op_string
))
9920 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
9923 /* Check if operand is a register. */
9924 if ((r
= parse_register (op_string
, &end_op
)) != NULL
)
9926 i386_operand_type temp
;
9928 /* Check for a segment override by searching for ':' after a
9929 segment register. */
9931 if (is_space_char (*op_string
))
9933 if (*op_string
== ':'
9934 && (r
->reg_type
.bitfield
.sreg2
9935 || r
->reg_type
.bitfield
.sreg3
))
9940 i
.seg
[i
.mem_operands
] = &es
;
9943 i
.seg
[i
.mem_operands
] = &cs
;
9946 i
.seg
[i
.mem_operands
] = &ss
;
9949 i
.seg
[i
.mem_operands
] = &ds
;
9952 i
.seg
[i
.mem_operands
] = &fs
;
9955 i
.seg
[i
.mem_operands
] = &gs
;
9959 /* Skip the ':' and whitespace. */
9961 if (is_space_char (*op_string
))
9964 if (!is_digit_char (*op_string
)
9965 && !is_identifier_char (*op_string
)
9966 && *op_string
!= '('
9967 && *op_string
!= ABSOLUTE_PREFIX
)
9969 as_bad (_("bad memory operand `%s'"), op_string
);
9972 /* Handle case of %es:*foo. */
9973 if (*op_string
== ABSOLUTE_PREFIX
)
9976 if (is_space_char (*op_string
))
9978 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
9980 goto do_memory_reference
;
9983 /* Handle vector operations. */
9984 if (*op_string
== '{')
9986 op_string
= check_VecOperations (op_string
, NULL
);
9987 if (op_string
== NULL
)
9993 as_bad (_("junk `%s' after register"), op_string
);
9997 temp
.bitfield
.baseindex
= 0;
9998 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
10000 i
.types
[this_operand
].bitfield
.unspecified
= 0;
10001 i
.op
[this_operand
].regs
= r
;
10004 else if (*op_string
== REGISTER_PREFIX
)
10006 as_bad (_("bad register name `%s'"), op_string
);
10009 else if (*op_string
== IMMEDIATE_PREFIX
)
10012 if (i
.types
[this_operand
].bitfield
.jumpabsolute
)
10014 as_bad (_("immediate operand illegal with absolute jump"));
10017 if (!i386_immediate (op_string
))
10020 else if (RC_SAE_immediate (operand_string
))
10022 /* If it is a RC or SAE immediate, do nothing. */
10025 else if (is_digit_char (*op_string
)
10026 || is_identifier_char (*op_string
)
10027 || *op_string
== '"'
10028 || *op_string
== '(')
10030 /* This is a memory reference of some sort. */
10033 /* Start and end of displacement string expression (if found). */
10034 char *displacement_string_start
;
10035 char *displacement_string_end
;
10038 do_memory_reference
:
10039 if (i
.mem_operands
== 1 && !maybe_adjust_templates ())
10041 if ((i
.mem_operands
== 1
10042 && !current_templates
->start
->opcode_modifier
.isstring
)
10043 || i
.mem_operands
== 2)
10045 as_bad (_("too many memory references for `%s'"),
10046 current_templates
->start
->name
);
10050 /* Check for base index form. We detect the base index form by
10051 looking for an ')' at the end of the operand, searching
10052 for the '(' matching it, and finding a REGISTER_PREFIX or ','
10054 base_string
= op_string
+ strlen (op_string
);
10056 /* Handle vector operations. */
10057 vop_start
= strchr (op_string
, '{');
10058 if (vop_start
&& vop_start
< base_string
)
10060 if (check_VecOperations (vop_start
, base_string
) == NULL
)
10062 base_string
= vop_start
;
10066 if (is_space_char (*base_string
))
10069 /* If we only have a displacement, set-up for it to be parsed later. */
10070 displacement_string_start
= op_string
;
10071 displacement_string_end
= base_string
+ 1;
10073 if (*base_string
== ')')
10076 unsigned int parens_balanced
= 1;
10077 /* We've already checked that the number of left & right ()'s are
10078 equal, so this loop will not be infinite. */
10082 if (*base_string
== ')')
10084 if (*base_string
== '(')
10087 while (parens_balanced
);
10089 temp_string
= base_string
;
10091 /* Skip past '(' and whitespace. */
10093 if (is_space_char (*base_string
))
10096 if (*base_string
== ','
10097 || ((i
.base_reg
= parse_register (base_string
, &end_op
))
10100 displacement_string_end
= temp_string
;
10102 i
.types
[this_operand
].bitfield
.baseindex
= 1;
10106 base_string
= end_op
;
10107 if (is_space_char (*base_string
))
10111 /* There may be an index reg or scale factor here. */
10112 if (*base_string
== ',')
10115 if (is_space_char (*base_string
))
10118 if ((i
.index_reg
= parse_register (base_string
, &end_op
))
10121 base_string
= end_op
;
10122 if (is_space_char (*base_string
))
10124 if (*base_string
== ',')
10127 if (is_space_char (*base_string
))
10130 else if (*base_string
!= ')')
10132 as_bad (_("expecting `,' or `)' "
10133 "after index register in `%s'"),
10138 else if (*base_string
== REGISTER_PREFIX
)
10140 end_op
= strchr (base_string
, ',');
10143 as_bad (_("bad register name `%s'"), base_string
);
10147 /* Check for scale factor. */
10148 if (*base_string
!= ')')
10150 char *end_scale
= i386_scale (base_string
);
10155 base_string
= end_scale
;
10156 if (is_space_char (*base_string
))
10158 if (*base_string
!= ')')
10160 as_bad (_("expecting `)' "
10161 "after scale factor in `%s'"),
10166 else if (!i
.index_reg
)
10168 as_bad (_("expecting index register or scale factor "
10169 "after `,'; got '%c'"),
10174 else if (*base_string
!= ')')
10176 as_bad (_("expecting `,' or `)' "
10177 "after base register in `%s'"),
10182 else if (*base_string
== REGISTER_PREFIX
)
10184 end_op
= strchr (base_string
, ',');
10187 as_bad (_("bad register name `%s'"), base_string
);
10192 /* If there's an expression beginning the operand, parse it,
10193 assuming displacement_string_start and
10194 displacement_string_end are meaningful. */
10195 if (displacement_string_start
!= displacement_string_end
)
10197 if (!i386_displacement (displacement_string_start
,
10198 displacement_string_end
))
10202 /* Special case for (%dx) while doing input/output op. */
10204 && i
.base_reg
->reg_type
.bitfield
.inoutportreg
10205 && i
.index_reg
== 0
10206 && i
.log2_scale_factor
== 0
10207 && i
.seg
[i
.mem_operands
] == 0
10208 && !operand_type_check (i
.types
[this_operand
], disp
))
10210 i
.types
[this_operand
] = i
.base_reg
->reg_type
;
10214 if (i386_index_check (operand_string
) == 0)
10216 i
.flags
[this_operand
] |= Operand_Mem
;
10217 if (i
.mem_operands
== 0)
10218 i
.memop1_string
= xstrdup (operand_string
);
10223 /* It's not a memory operand; argh! */
10224 as_bad (_("invalid char %s beginning operand %d `%s'"),
10225 output_invalid (*op_string
),
10230 return 1; /* Normal return. */
10233 /* Calculate the maximum variable size (i.e., excluding fr_fix)
10234 that an rs_machine_dependent frag may reach. */
10237 i386_frag_max_var (fragS
*frag
)
10239 /* The only relaxable frags are for jumps.
10240 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
10241 gas_assert (frag
->fr_type
== rs_machine_dependent
);
10242 return TYPE_FROM_RELAX_STATE (frag
->fr_subtype
) == UNCOND_JUMP
? 4 : 5;
10245 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10247 elf_symbol_resolved_in_segment_p (symbolS
*fr_symbol
, offsetT fr_var
)
10249 /* STT_GNU_IFUNC symbol must go through PLT. */
10250 if ((symbol_get_bfdsym (fr_symbol
)->flags
10251 & BSF_GNU_INDIRECT_FUNCTION
) != 0)
10254 if (!S_IS_EXTERNAL (fr_symbol
))
10255 /* Symbol may be weak or local. */
10256 return !S_IS_WEAK (fr_symbol
);
10258 /* Global symbols with non-default visibility can't be preempted. */
10259 if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol
)) != STV_DEFAULT
)
10262 if (fr_var
!= NO_RELOC
)
10263 switch ((enum bfd_reloc_code_real
) fr_var
)
10265 case BFD_RELOC_386_PLT32
:
10266 case BFD_RELOC_X86_64_PLT32
:
10267 /* Symbol with PLT relocation may be preempted. */
10273 /* Global symbols with default visibility in a shared library may be
10274 preempted by another definition. */
10279 /* md_estimate_size_before_relax()
10281 Called just before relax() for rs_machine_dependent frags. The x86
10282 assembler uses these frags to handle variable size jump
10285 Any symbol that is now undefined will not become defined.
10286 Return the correct fr_subtype in the frag.
10287 Return the initial "guess for variable size of frag" to caller.
10288 The guess is actually the growth beyond the fixed part. Whatever
10289 we do to grow the fixed or variable part contributes to our
10293 md_estimate_size_before_relax (fragS
*fragP
, segT segment
)
10295 /* We've already got fragP->fr_subtype right; all we have to do is
10296 check for un-relaxable symbols. On an ELF system, we can't relax
10297 an externally visible symbol, because it may be overridden by a
10299 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
10300 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10302 && !elf_symbol_resolved_in_segment_p (fragP
->fr_symbol
,
10305 #if defined (OBJ_COFF) && defined (TE_PE)
10306 || (OUTPUT_FLAVOR
== bfd_target_coff_flavour
10307 && S_IS_WEAK (fragP
->fr_symbol
))
10311 /* Symbol is undefined in this segment, or we need to keep a
10312 reloc so that weak symbols can be overridden. */
10313 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
10314 enum bfd_reloc_code_real reloc_type
;
10315 unsigned char *opcode
;
10318 if (fragP
->fr_var
!= NO_RELOC
)
10319 reloc_type
= (enum bfd_reloc_code_real
) fragP
->fr_var
;
10320 else if (size
== 2)
10321 reloc_type
= BFD_RELOC_16_PCREL
;
10322 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10323 else if (need_plt32_p (fragP
->fr_symbol
))
10324 reloc_type
= BFD_RELOC_X86_64_PLT32
;
10327 reloc_type
= BFD_RELOC_32_PCREL
;
10329 old_fr_fix
= fragP
->fr_fix
;
10330 opcode
= (unsigned char *) fragP
->fr_opcode
;
10332 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
10335 /* Make jmp (0xeb) a (d)word displacement jump. */
10337 fragP
->fr_fix
+= size
;
10338 fix_new (fragP
, old_fr_fix
, size
,
10340 fragP
->fr_offset
, 1,
10346 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
10348 /* Negate the condition, and branch past an
10349 unconditional jump. */
10352 /* Insert an unconditional jump. */
10354 /* We added two extra opcode bytes, and have a two byte
10356 fragP
->fr_fix
+= 2 + 2;
10357 fix_new (fragP
, old_fr_fix
+ 2, 2,
10359 fragP
->fr_offset
, 1,
10363 /* Fall through. */
10366 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
10370 fragP
->fr_fix
+= 1;
10371 fixP
= fix_new (fragP
, old_fr_fix
, 1,
10373 fragP
->fr_offset
, 1,
10374 BFD_RELOC_8_PCREL
);
10375 fixP
->fx_signed
= 1;
10379 /* This changes the byte-displacement jump 0x7N
10380 to the (d)word-displacement jump 0x0f,0x8N. */
10381 opcode
[1] = opcode
[0] + 0x10;
10382 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
10383 /* We've added an opcode byte. */
10384 fragP
->fr_fix
+= 1 + size
;
10385 fix_new (fragP
, old_fr_fix
+ 1, size
,
10387 fragP
->fr_offset
, 1,
10392 BAD_CASE (fragP
->fr_subtype
);
10396 return fragP
->fr_fix
- old_fr_fix
;
10399 /* Guess size depending on current relax state. Initially the relax
10400 state will correspond to a short jump and we return 1, because
10401 the variable part of the frag (the branch offset) is one byte
10402 long. However, we can relax a section more than once and in that
10403 case we must either set fr_subtype back to the unrelaxed state,
10404 or return the value for the appropriate branch. */
10405 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
10408 /* Called after relax() is finished.
10410 In: Address of frag.
10411 fr_type == rs_machine_dependent.
10412 fr_subtype is what the address relaxed to.
10414 Out: Any fixSs and constants are set up.
10415 Caller will turn frag into a ".space 0". */
10418 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec ATTRIBUTE_UNUSED
,
10421 unsigned char *opcode
;
10422 unsigned char *where_to_put_displacement
= NULL
;
10423 offsetT target_address
;
10424 offsetT opcode_address
;
10425 unsigned int extension
= 0;
10426 offsetT displacement_from_opcode_start
;
10428 opcode
= (unsigned char *) fragP
->fr_opcode
;
10430 /* Address we want to reach in file space. */
10431 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
10433 /* Address opcode resides at in file space. */
10434 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
10436 /* Displacement from opcode start to fill into instruction. */
10437 displacement_from_opcode_start
= target_address
- opcode_address
;
10439 if ((fragP
->fr_subtype
& BIG
) == 0)
10441 /* Don't have to change opcode. */
10442 extension
= 1; /* 1 opcode + 1 displacement */
10443 where_to_put_displacement
= &opcode
[1];
10447 if (no_cond_jump_promotion
10448 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
10449 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
10450 _("long jump required"));
10452 switch (fragP
->fr_subtype
)
10454 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
10455 extension
= 4; /* 1 opcode + 4 displacement */
10457 where_to_put_displacement
= &opcode
[1];
10460 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
10461 extension
= 2; /* 1 opcode + 2 displacement */
10463 where_to_put_displacement
= &opcode
[1];
10466 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
10467 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
10468 extension
= 5; /* 2 opcode + 4 displacement */
10469 opcode
[1] = opcode
[0] + 0x10;
10470 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
10471 where_to_put_displacement
= &opcode
[2];
10474 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
10475 extension
= 3; /* 2 opcode + 2 displacement */
10476 opcode
[1] = opcode
[0] + 0x10;
10477 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
10478 where_to_put_displacement
= &opcode
[2];
10481 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
10486 where_to_put_displacement
= &opcode
[3];
10490 BAD_CASE (fragP
->fr_subtype
);
10495 /* If size if less then four we are sure that the operand fits,
10496 but if it's 4, then it could be that the displacement is larger
10498 if (DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
) == 4
10500 && ((addressT
) (displacement_from_opcode_start
- extension
10501 + ((addressT
) 1 << 31))
10502 > (((addressT
) 2 << 31) - 1)))
10504 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
10505 _("jump target out of range"));
10506 /* Make us emit 0. */
10507 displacement_from_opcode_start
= extension
;
10509 /* Now put displacement after opcode. */
10510 md_number_to_chars ((char *) where_to_put_displacement
,
10511 (valueT
) (displacement_from_opcode_start
- extension
),
10512 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
10513 fragP
->fr_fix
+= extension
;
10516 /* Apply a fixup (fixP) to segment data, once it has been determined
10517 by our caller that we have all the info we need to fix it up.
10519 Parameter valP is the pointer to the value of the bits.
10521 On the 386, immediates, displacements, and data pointers are all in
10522 the same (little-endian) format, so we don't need to care about which
10523 we are handling. */
10526 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
10528 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
10529 valueT value
= *valP
;
10531 #if !defined (TE_Mach)
10532 if (fixP
->fx_pcrel
)
10534 switch (fixP
->fx_r_type
)
10540 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
10543 case BFD_RELOC_X86_64_32S
:
10544 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
10547 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
10550 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
10555 if (fixP
->fx_addsy
!= NULL
10556 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
10557 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
10558 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
10559 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
10560 && !use_rela_relocations
)
10562 /* This is a hack. There should be a better way to handle this.
10563 This covers for the fact that bfd_install_relocation will
10564 subtract the current location (for partial_inplace, PC relative
10565 relocations); see more below. */
10569 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
10572 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
10574 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10577 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
10579 if ((sym_seg
== seg
10580 || (symbol_section_p (fixP
->fx_addsy
)
10581 && sym_seg
!= absolute_section
))
10582 && !generic_force_reloc (fixP
))
10584 /* Yes, we add the values in twice. This is because
10585 bfd_install_relocation subtracts them out again. I think
10586 bfd_install_relocation is broken, but I don't dare change
10588 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
10592 #if defined (OBJ_COFF) && defined (TE_PE)
10593 /* For some reason, the PE format does not store a
10594 section address offset for a PC relative symbol. */
10595 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
10596 || S_IS_WEAK (fixP
->fx_addsy
))
10597 value
+= md_pcrel_from (fixP
);
10600 #if defined (OBJ_COFF) && defined (TE_PE)
10601 if (fixP
->fx_addsy
!= NULL
10602 && S_IS_WEAK (fixP
->fx_addsy
)
10603 /* PR 16858: Do not modify weak function references. */
10604 && ! fixP
->fx_pcrel
)
10606 #if !defined (TE_PEP)
10607 /* For x86 PE weak function symbols are neither PC-relative
10608 nor do they set S_IS_FUNCTION. So the only reliable way
10609 to detect them is to check the flags of their containing
10611 if (S_GET_SEGMENT (fixP
->fx_addsy
) != NULL
10612 && S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_CODE
)
10616 value
-= S_GET_VALUE (fixP
->fx_addsy
);
10620 /* Fix a few things - the dynamic linker expects certain values here,
10621 and we must not disappoint it. */
10622 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10623 if (IS_ELF
&& fixP
->fx_addsy
)
10624 switch (fixP
->fx_r_type
)
10626 case BFD_RELOC_386_PLT32
:
10627 case BFD_RELOC_X86_64_PLT32
:
10628 /* Make the jump instruction point to the address of the operand.
10629 At runtime we merely add the offset to the actual PLT entry.
10630 NB: Subtract the offset size only for jump instructions. */
10631 if (fixP
->fx_pcrel
)
10635 case BFD_RELOC_386_TLS_GD
:
10636 case BFD_RELOC_386_TLS_LDM
:
10637 case BFD_RELOC_386_TLS_IE_32
:
10638 case BFD_RELOC_386_TLS_IE
:
10639 case BFD_RELOC_386_TLS_GOTIE
:
10640 case BFD_RELOC_386_TLS_GOTDESC
:
10641 case BFD_RELOC_X86_64_TLSGD
:
10642 case BFD_RELOC_X86_64_TLSLD
:
10643 case BFD_RELOC_X86_64_GOTTPOFF
:
10644 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
10645 value
= 0; /* Fully resolved at runtime. No addend. */
10647 case BFD_RELOC_386_TLS_LE
:
10648 case BFD_RELOC_386_TLS_LDO_32
:
10649 case BFD_RELOC_386_TLS_LE_32
:
10650 case BFD_RELOC_X86_64_DTPOFF32
:
10651 case BFD_RELOC_X86_64_DTPOFF64
:
10652 case BFD_RELOC_X86_64_TPOFF32
:
10653 case BFD_RELOC_X86_64_TPOFF64
:
10654 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
10657 case BFD_RELOC_386_TLS_DESC_CALL
:
10658 case BFD_RELOC_X86_64_TLSDESC_CALL
:
10659 value
= 0; /* Fully resolved at runtime. No addend. */
10660 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
10664 case BFD_RELOC_VTABLE_INHERIT
:
10665 case BFD_RELOC_VTABLE_ENTRY
:
10672 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
10674 #endif /* !defined (TE_Mach) */
10676 /* Are we finished with this relocation now? */
10677 if (fixP
->fx_addsy
== NULL
)
10679 #if defined (OBJ_COFF) && defined (TE_PE)
10680 else if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
10683 /* Remember value for tc_gen_reloc. */
10684 fixP
->fx_addnumber
= value
;
10685 /* Clear out the frag for now. */
10689 else if (use_rela_relocations
)
10691 fixP
->fx_no_overflow
= 1;
10692 /* Remember value for tc_gen_reloc. */
10693 fixP
->fx_addnumber
= value
;
10697 md_number_to_chars (p
, value
, fixP
->fx_size
);
10701 md_atof (int type
, char *litP
, int *sizeP
)
10703 /* This outputs the LITTLENUMs in REVERSE order;
10704 in accord with the bigendian 386. */
10705 return ieee_md_atof (type
, litP
, sizeP
, FALSE
);
10708 static char output_invalid_buf
[sizeof (unsigned char) * 2 + 6];
10711 output_invalid (int c
)
10714 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
10717 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
10718 "(0x%x)", (unsigned char) c
);
10719 return output_invalid_buf
;
10722 /* REG_STRING starts *before* REGISTER_PREFIX. */
10724 static const reg_entry
*
10725 parse_real_register (char *reg_string
, char **end_op
)
10727 char *s
= reg_string
;
10729 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
10730 const reg_entry
*r
;
10732 /* Skip possible REGISTER_PREFIX and possible whitespace. */
10733 if (*s
== REGISTER_PREFIX
)
10736 if (is_space_char (*s
))
10739 p
= reg_name_given
;
10740 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
10742 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
10743 return (const reg_entry
*) NULL
;
10747 /* For naked regs, make sure that we are not dealing with an identifier.
10748 This prevents confusing an identifier like `eax_var' with register
10750 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
10751 return (const reg_entry
*) NULL
;
10755 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
10757 /* Handle floating point regs, allowing spaces in the (i) part. */
10758 if (r
== i386_regtab
/* %st is first entry of table */)
10760 if (!cpu_arch_flags
.bitfield
.cpu8087
10761 && !cpu_arch_flags
.bitfield
.cpu287
10762 && !cpu_arch_flags
.bitfield
.cpu387
)
10763 return (const reg_entry
*) NULL
;
10765 if (is_space_char (*s
))
10770 if (is_space_char (*s
))
10772 if (*s
>= '0' && *s
<= '7')
10774 int fpr
= *s
- '0';
10776 if (is_space_char (*s
))
10781 r
= (const reg_entry
*) hash_find (reg_hash
, "st(0)");
10786 /* We have "%st(" then garbage. */
10787 return (const reg_entry
*) NULL
;
10791 if (r
== NULL
|| allow_pseudo_reg
)
10794 if (operand_type_all_zero (&r
->reg_type
))
10795 return (const reg_entry
*) NULL
;
10797 if ((r
->reg_type
.bitfield
.dword
10798 || r
->reg_type
.bitfield
.sreg3
10799 || r
->reg_type
.bitfield
.control
10800 || r
->reg_type
.bitfield
.debug
10801 || r
->reg_type
.bitfield
.test
)
10802 && !cpu_arch_flags
.bitfield
.cpui386
)
10803 return (const reg_entry
*) NULL
;
10805 if (r
->reg_type
.bitfield
.regmmx
&& !cpu_arch_flags
.bitfield
.cpummx
)
10806 return (const reg_entry
*) NULL
;
10808 if (!cpu_arch_flags
.bitfield
.cpuavx512f
)
10810 if (r
->reg_type
.bitfield
.zmmword
|| r
->reg_type
.bitfield
.regmask
)
10811 return (const reg_entry
*) NULL
;
10813 if (!cpu_arch_flags
.bitfield
.cpuavx
)
10815 if (r
->reg_type
.bitfield
.ymmword
)
10816 return (const reg_entry
*) NULL
;
10818 if (!cpu_arch_flags
.bitfield
.cpusse
&& r
->reg_type
.bitfield
.xmmword
)
10819 return (const reg_entry
*) NULL
;
10823 if (r
->reg_type
.bitfield
.regbnd
&& !cpu_arch_flags
.bitfield
.cpumpx
)
10824 return (const reg_entry
*) NULL
;
10826 /* Don't allow fake index register unless allow_index_reg isn't 0. */
10827 if (!allow_index_reg
&& r
->reg_num
== RegIZ
)
10828 return (const reg_entry
*) NULL
;
10830 /* Upper 16 vector registers are only available with VREX in 64bit
10831 mode, and require EVEX encoding. */
10832 if (r
->reg_flags
& RegVRex
)
10834 if (!cpu_arch_flags
.bitfield
.cpuavx512f
10835 || flag_code
!= CODE_64BIT
)
10836 return (const reg_entry
*) NULL
;
10838 i
.vec_encoding
= vex_encoding_evex
;
10841 if (((r
->reg_flags
& (RegRex64
| RegRex
)) || r
->reg_type
.bitfield
.qword
)
10842 && (!cpu_arch_flags
.bitfield
.cpulm
|| !r
->reg_type
.bitfield
.control
)
10843 && flag_code
!= CODE_64BIT
)
10844 return (const reg_entry
*) NULL
;
10846 if (r
->reg_type
.bitfield
.sreg3
&& r
->reg_num
== RegFlat
&& !intel_syntax
)
10847 return (const reg_entry
*) NULL
;
10852 /* REG_STRING starts *before* REGISTER_PREFIX. */
10854 static const reg_entry
*
10855 parse_register (char *reg_string
, char **end_op
)
10857 const reg_entry
*r
;
10859 if (*reg_string
== REGISTER_PREFIX
|| allow_naked_reg
)
10860 r
= parse_real_register (reg_string
, end_op
);
10865 char *save
= input_line_pointer
;
10869 input_line_pointer
= reg_string
;
10870 c
= get_symbol_name (®_string
);
10871 symbolP
= symbol_find (reg_string
);
10872 if (symbolP
&& S_GET_SEGMENT (symbolP
) == reg_section
)
10874 const expressionS
*e
= symbol_get_value_expression (symbolP
);
10876 know (e
->X_op
== O_register
);
10877 know (e
->X_add_number
>= 0
10878 && (valueT
) e
->X_add_number
< i386_regtab_size
);
10879 r
= i386_regtab
+ e
->X_add_number
;
10880 if ((r
->reg_flags
& RegVRex
))
10881 i
.vec_encoding
= vex_encoding_evex
;
10882 *end_op
= input_line_pointer
;
10884 *input_line_pointer
= c
;
10885 input_line_pointer
= save
;
10891 i386_parse_name (char *name
, expressionS
*e
, char *nextcharP
)
10893 const reg_entry
*r
;
10894 char *end
= input_line_pointer
;
10897 r
= parse_register (name
, &input_line_pointer
);
10898 if (r
&& end
<= input_line_pointer
)
10900 *nextcharP
= *input_line_pointer
;
10901 *input_line_pointer
= 0;
10902 e
->X_op
= O_register
;
10903 e
->X_add_number
= r
- i386_regtab
;
10906 input_line_pointer
= end
;
10908 return intel_syntax
? i386_intel_parse_name (name
, e
) : 0;
10912 md_operand (expressionS
*e
)
10915 const reg_entry
*r
;
10917 switch (*input_line_pointer
)
10919 case REGISTER_PREFIX
:
10920 r
= parse_real_register (input_line_pointer
, &end
);
10923 e
->X_op
= O_register
;
10924 e
->X_add_number
= r
- i386_regtab
;
10925 input_line_pointer
= end
;
10930 gas_assert (intel_syntax
);
10931 end
= input_line_pointer
++;
10933 if (*input_line_pointer
== ']')
10935 ++input_line_pointer
;
10936 e
->X_op_symbol
= make_expr_symbol (e
);
10937 e
->X_add_symbol
= NULL
;
10938 e
->X_add_number
= 0;
10943 e
->X_op
= O_absent
;
10944 input_line_pointer
= end
;
10951 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10952 const char *md_shortopts
= "kVQ:sqnO::";
10954 const char *md_shortopts
= "qnO::";
10957 #define OPTION_32 (OPTION_MD_BASE + 0)
10958 #define OPTION_64 (OPTION_MD_BASE + 1)
10959 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
10960 #define OPTION_MARCH (OPTION_MD_BASE + 3)
10961 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
10962 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
10963 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
10964 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
10965 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
10966 #define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 9)
10967 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
10968 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
10969 #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
10970 #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
10971 #define OPTION_X32 (OPTION_MD_BASE + 14)
10972 #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
10973 #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
10974 #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
10975 #define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
10976 #define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
10977 #define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
10978 #define OPTION_MSHARED (OPTION_MD_BASE + 21)
10979 #define OPTION_MAMD64 (OPTION_MD_BASE + 22)
10980 #define OPTION_MINTEL64 (OPTION_MD_BASE + 23)
10981 #define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24)
10982 #define OPTION_X86_USED_NOTE (OPTION_MD_BASE + 25)
10983 #define OPTION_MVEXWIG (OPTION_MD_BASE + 26)
10985 struct option md_longopts
[] =
10987 {"32", no_argument
, NULL
, OPTION_32
},
10988 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10989 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
10990 {"64", no_argument
, NULL
, OPTION_64
},
10992 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10993 {"x32", no_argument
, NULL
, OPTION_X32
},
10994 {"mshared", no_argument
, NULL
, OPTION_MSHARED
},
10995 {"mx86-used-note", required_argument
, NULL
, OPTION_X86_USED_NOTE
},
10997 {"divide", no_argument
, NULL
, OPTION_DIVIDE
},
10998 {"march", required_argument
, NULL
, OPTION_MARCH
},
10999 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
11000 {"mmnemonic", required_argument
, NULL
, OPTION_MMNEMONIC
},
11001 {"msyntax", required_argument
, NULL
, OPTION_MSYNTAX
},
11002 {"mindex-reg", no_argument
, NULL
, OPTION_MINDEX_REG
},
11003 {"mnaked-reg", no_argument
, NULL
, OPTION_MNAKED_REG
},
11004 {"msse2avx", no_argument
, NULL
, OPTION_MSSE2AVX
},
11005 {"msse-check", required_argument
, NULL
, OPTION_MSSE_CHECK
},
11006 {"moperand-check", required_argument
, NULL
, OPTION_MOPERAND_CHECK
},
11007 {"mavxscalar", required_argument
, NULL
, OPTION_MAVXSCALAR
},
11008 {"mvexwig", required_argument
, NULL
, OPTION_MVEXWIG
},
11009 {"madd-bnd-prefix", no_argument
, NULL
, OPTION_MADD_BND_PREFIX
},
11010 {"mevexlig", required_argument
, NULL
, OPTION_MEVEXLIG
},
11011 {"mevexwig", required_argument
, NULL
, OPTION_MEVEXWIG
},
11012 # if defined (TE_PE) || defined (TE_PEP)
11013 {"mbig-obj", no_argument
, NULL
, OPTION_MBIG_OBJ
},
11015 {"momit-lock-prefix", required_argument
, NULL
, OPTION_MOMIT_LOCK_PREFIX
},
11016 {"mfence-as-lock-add", required_argument
, NULL
, OPTION_MFENCE_AS_LOCK_ADD
},
11017 {"mrelax-relocations", required_argument
, NULL
, OPTION_MRELAX_RELOCATIONS
},
11018 {"mevexrcig", required_argument
, NULL
, OPTION_MEVEXRCIG
},
11019 {"mamd64", no_argument
, NULL
, OPTION_MAMD64
},
11020 {"mintel64", no_argument
, NULL
, OPTION_MINTEL64
},
11021 {NULL
, no_argument
, NULL
, 0}
11023 size_t md_longopts_size
= sizeof (md_longopts
);
11026 md_parse_option (int c
, const char *arg
)
11029 char *arch
, *next
, *saved
;
11034 optimize_align_code
= 0;
11038 quiet_warnings
= 1;
11041 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11042 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
11043 should be emitted or not. FIXME: Not implemented. */
11047 /* -V: SVR4 argument to print version ID. */
11049 print_version_id ();
11052 /* -k: Ignore for FreeBSD compatibility. */
11057 /* -s: On i386 Solaris, this tells the native assembler to use
11058 .stab instead of .stab.excl. We always use .stab anyhow. */
11061 case OPTION_MSHARED
:
11065 case OPTION_X86_USED_NOTE
:
11066 if (strcasecmp (arg
, "yes") == 0)
11068 else if (strcasecmp (arg
, "no") == 0)
11071 as_fatal (_("invalid -mx86-used-note= option: `%s'"), arg
);
11076 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
11077 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
11080 const char **list
, **l
;
11082 list
= bfd_target_list ();
11083 for (l
= list
; *l
!= NULL
; l
++)
11084 if (CONST_STRNEQ (*l
, "elf64-x86-64")
11085 || strcmp (*l
, "coff-x86-64") == 0
11086 || strcmp (*l
, "pe-x86-64") == 0
11087 || strcmp (*l
, "pei-x86-64") == 0
11088 || strcmp (*l
, "mach-o-x86-64") == 0)
11090 default_arch
= "x86_64";
11094 as_fatal (_("no compiled in support for x86_64"));
11100 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11104 const char **list
, **l
;
11106 list
= bfd_target_list ();
11107 for (l
= list
; *l
!= NULL
; l
++)
11108 if (CONST_STRNEQ (*l
, "elf32-x86-64"))
11110 default_arch
= "x86_64:32";
11114 as_fatal (_("no compiled in support for 32bit x86_64"));
11118 as_fatal (_("32bit x86_64 is only supported for ELF"));
11123 default_arch
= "i386";
11126 case OPTION_DIVIDE
:
11127 #ifdef SVR4_COMMENT_CHARS
11132 n
= XNEWVEC (char, strlen (i386_comment_chars
) + 1);
11134 for (s
= i386_comment_chars
; *s
!= '\0'; s
++)
11138 i386_comment_chars
= n
;
11144 saved
= xstrdup (arg
);
11146 /* Allow -march=+nosse. */
11152 as_fatal (_("invalid -march= option: `%s'"), arg
);
11153 next
= strchr (arch
, '+');
11156 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
11158 if (strcmp (arch
, cpu_arch
[j
].name
) == 0)
11161 if (! cpu_arch
[j
].flags
.bitfield
.cpui386
)
11164 cpu_arch_name
= cpu_arch
[j
].name
;
11165 cpu_sub_arch_name
= NULL
;
11166 cpu_arch_flags
= cpu_arch
[j
].flags
;
11167 cpu_arch_isa
= cpu_arch
[j
].type
;
11168 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
11169 if (!cpu_arch_tune_set
)
11171 cpu_arch_tune
= cpu_arch_isa
;
11172 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
11176 else if (*cpu_arch
[j
].name
== '.'
11177 && strcmp (arch
, cpu_arch
[j
].name
+ 1) == 0)
11179 /* ISA extension. */
11180 i386_cpu_flags flags
;
11182 flags
= cpu_flags_or (cpu_arch_flags
,
11183 cpu_arch
[j
].flags
);
11185 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
11187 if (cpu_sub_arch_name
)
11189 char *name
= cpu_sub_arch_name
;
11190 cpu_sub_arch_name
= concat (name
,
11192 (const char *) NULL
);
11196 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
11197 cpu_arch_flags
= flags
;
11198 cpu_arch_isa_flags
= flags
;
11202 = cpu_flags_or (cpu_arch_isa_flags
,
11203 cpu_arch
[j
].flags
);
11208 if (j
>= ARRAY_SIZE (cpu_arch
))
11210 /* Disable an ISA extension. */
11211 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
11212 if (strcmp (arch
, cpu_noarch
[j
].name
) == 0)
11214 i386_cpu_flags flags
;
11216 flags
= cpu_flags_and_not (cpu_arch_flags
,
11217 cpu_noarch
[j
].flags
);
11218 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
11220 if (cpu_sub_arch_name
)
11222 char *name
= cpu_sub_arch_name
;
11223 cpu_sub_arch_name
= concat (arch
,
11224 (const char *) NULL
);
11228 cpu_sub_arch_name
= xstrdup (arch
);
11229 cpu_arch_flags
= flags
;
11230 cpu_arch_isa_flags
= flags
;
11235 if (j
>= ARRAY_SIZE (cpu_noarch
))
11236 j
= ARRAY_SIZE (cpu_arch
);
11239 if (j
>= ARRAY_SIZE (cpu_arch
))
11240 as_fatal (_("invalid -march= option: `%s'"), arg
);
11244 while (next
!= NULL
);
11250 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
11251 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
11253 if (strcmp (arg
, cpu_arch
[j
].name
) == 0)
11255 cpu_arch_tune_set
= 1;
11256 cpu_arch_tune
= cpu_arch
[j
].type
;
11257 cpu_arch_tune_flags
= cpu_arch
[j
].flags
;
11261 if (j
>= ARRAY_SIZE (cpu_arch
))
11262 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
11265 case OPTION_MMNEMONIC
:
11266 if (strcasecmp (arg
, "att") == 0)
11267 intel_mnemonic
= 0;
11268 else if (strcasecmp (arg
, "intel") == 0)
11269 intel_mnemonic
= 1;
11271 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg
);
11274 case OPTION_MSYNTAX
:
11275 if (strcasecmp (arg
, "att") == 0)
11277 else if (strcasecmp (arg
, "intel") == 0)
11280 as_fatal (_("invalid -msyntax= option: `%s'"), arg
);
11283 case OPTION_MINDEX_REG
:
11284 allow_index_reg
= 1;
11287 case OPTION_MNAKED_REG
:
11288 allow_naked_reg
= 1;
11291 case OPTION_MSSE2AVX
:
11295 case OPTION_MSSE_CHECK
:
11296 if (strcasecmp (arg
, "error") == 0)
11297 sse_check
= check_error
;
11298 else if (strcasecmp (arg
, "warning") == 0)
11299 sse_check
= check_warning
;
11300 else if (strcasecmp (arg
, "none") == 0)
11301 sse_check
= check_none
;
11303 as_fatal (_("invalid -msse-check= option: `%s'"), arg
);
11306 case OPTION_MOPERAND_CHECK
:
11307 if (strcasecmp (arg
, "error") == 0)
11308 operand_check
= check_error
;
11309 else if (strcasecmp (arg
, "warning") == 0)
11310 operand_check
= check_warning
;
11311 else if (strcasecmp (arg
, "none") == 0)
11312 operand_check
= check_none
;
11314 as_fatal (_("invalid -moperand-check= option: `%s'"), arg
);
11317 case OPTION_MAVXSCALAR
:
11318 if (strcasecmp (arg
, "128") == 0)
11319 avxscalar
= vex128
;
11320 else if (strcasecmp (arg
, "256") == 0)
11321 avxscalar
= vex256
;
11323 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg
);
11326 case OPTION_MVEXWIG
:
11327 if (strcmp (arg
, "0") == 0)
11329 else if (strcmp (arg
, "1") == 0)
11332 as_fatal (_("invalid -mvexwig= option: `%s'"), arg
);
11335 case OPTION_MADD_BND_PREFIX
:
11336 add_bnd_prefix
= 1;
11339 case OPTION_MEVEXLIG
:
11340 if (strcmp (arg
, "128") == 0)
11341 evexlig
= evexl128
;
11342 else if (strcmp (arg
, "256") == 0)
11343 evexlig
= evexl256
;
11344 else if (strcmp (arg
, "512") == 0)
11345 evexlig
= evexl512
;
11347 as_fatal (_("invalid -mevexlig= option: `%s'"), arg
);
11350 case OPTION_MEVEXRCIG
:
11351 if (strcmp (arg
, "rne") == 0)
11353 else if (strcmp (arg
, "rd") == 0)
11355 else if (strcmp (arg
, "ru") == 0)
11357 else if (strcmp (arg
, "rz") == 0)
11360 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg
);
11363 case OPTION_MEVEXWIG
:
11364 if (strcmp (arg
, "0") == 0)
11366 else if (strcmp (arg
, "1") == 0)
11369 as_fatal (_("invalid -mevexwig= option: `%s'"), arg
);
11372 # if defined (TE_PE) || defined (TE_PEP)
11373 case OPTION_MBIG_OBJ
:
11378 case OPTION_MOMIT_LOCK_PREFIX
:
11379 if (strcasecmp (arg
, "yes") == 0)
11380 omit_lock_prefix
= 1;
11381 else if (strcasecmp (arg
, "no") == 0)
11382 omit_lock_prefix
= 0;
11384 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg
);
11387 case OPTION_MFENCE_AS_LOCK_ADD
:
11388 if (strcasecmp (arg
, "yes") == 0)
11390 else if (strcasecmp (arg
, "no") == 0)
11393 as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg
);
11396 case OPTION_MRELAX_RELOCATIONS
:
11397 if (strcasecmp (arg
, "yes") == 0)
11398 generate_relax_relocations
= 1;
11399 else if (strcasecmp (arg
, "no") == 0)
11400 generate_relax_relocations
= 0;
11402 as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg
);
11405 case OPTION_MAMD64
:
11409 case OPTION_MINTEL64
:
11417 /* Turn off -Os. */
11418 optimize_for_space
= 0;
11420 else if (*arg
== 's')
11422 optimize_for_space
= 1;
11423 /* Turn on all encoding optimizations. */
11424 optimize
= INT_MAX
;
11428 optimize
= atoi (arg
);
11429 /* Turn off -Os. */
11430 optimize_for_space
= 0;
11440 #define MESSAGE_TEMPLATE \
11444 output_message (FILE *stream
, char *p
, char *message
, char *start
,
11445 int *left_p
, const char *name
, int len
)
11447 int size
= sizeof (MESSAGE_TEMPLATE
);
11448 int left
= *left_p
;
11450 /* Reserve 2 spaces for ", " or ",\0" */
11453 /* Check if there is any room. */
11461 p
= mempcpy (p
, name
, len
);
11465 /* Output the current message now and start a new one. */
11468 fprintf (stream
, "%s\n", message
);
11470 left
= size
- (start
- message
) - len
- 2;
11472 gas_assert (left
>= 0);
11474 p
= mempcpy (p
, name
, len
);
11482 show_arch (FILE *stream
, int ext
, int check
)
11484 static char message
[] = MESSAGE_TEMPLATE
;
11485 char *start
= message
+ 27;
11487 int size
= sizeof (MESSAGE_TEMPLATE
);
11494 left
= size
- (start
- message
);
11495 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
11497 /* Should it be skipped? */
11498 if (cpu_arch
[j
].skip
)
11501 name
= cpu_arch
[j
].name
;
11502 len
= cpu_arch
[j
].len
;
11505 /* It is an extension. Skip if we aren't asked to show it. */
11516 /* It is an processor. Skip if we show only extension. */
11519 else if (check
&& ! cpu_arch
[j
].flags
.bitfield
.cpui386
)
11521 /* It is an impossible processor - skip. */
11525 p
= output_message (stream
, p
, message
, start
, &left
, name
, len
);
11528 /* Display disabled extensions. */
11530 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
11532 name
= cpu_noarch
[j
].name
;
11533 len
= cpu_noarch
[j
].len
;
11534 p
= output_message (stream
, p
, message
, start
, &left
, name
,
11539 fprintf (stream
, "%s\n", message
);
11543 md_show_usage (FILE *stream
)
11545 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11546 fprintf (stream
, _("\
11548 -V print assembler version number\n\
11551 fprintf (stream
, _("\
11552 -n Do not optimize code alignment\n\
11553 -q quieten some warnings\n"));
11554 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11555 fprintf (stream
, _("\
11558 #if defined BFD64 && (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
11559 || defined (TE_PE) || defined (TE_PEP))
11560 fprintf (stream
, _("\
11561 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
11563 #ifdef SVR4_COMMENT_CHARS
11564 fprintf (stream
, _("\
11565 --divide do not treat `/' as a comment character\n"));
11567 fprintf (stream
, _("\
11568 --divide ignored\n"));
11570 fprintf (stream
, _("\
11571 -march=CPU[,+EXTENSION...]\n\
11572 generate code for CPU and EXTENSION, CPU is one of:\n"));
11573 show_arch (stream
, 0, 1);
11574 fprintf (stream
, _("\
11575 EXTENSION is combination of:\n"));
11576 show_arch (stream
, 1, 0);
11577 fprintf (stream
, _("\
11578 -mtune=CPU optimize for CPU, CPU is one of:\n"));
11579 show_arch (stream
, 0, 0);
11580 fprintf (stream
, _("\
11581 -msse2avx encode SSE instructions with VEX prefix\n"));
11582 fprintf (stream
, _("\
11583 -msse-check=[none|error|warning] (default: warning)\n\
11584 check SSE instructions\n"));
11585 fprintf (stream
, _("\
11586 -moperand-check=[none|error|warning] (default: warning)\n\
11587 check operand combinations for validity\n"));
11588 fprintf (stream
, _("\
11589 -mavxscalar=[128|256] (default: 128)\n\
11590 encode scalar AVX instructions with specific vector\n\
11592 fprintf (stream
, _("\
11593 -mvexwig=[0|1] (default: 0)\n\
11594 encode VEX instructions with specific VEX.W value\n\
11595 for VEX.W bit ignored instructions\n"));
11596 fprintf (stream
, _("\
11597 -mevexlig=[128|256|512] (default: 128)\n\
11598 encode scalar EVEX instructions with specific vector\n\
11600 fprintf (stream
, _("\
11601 -mevexwig=[0|1] (default: 0)\n\
11602 encode EVEX instructions with specific EVEX.W value\n\
11603 for EVEX.W bit ignored instructions\n"));
11604 fprintf (stream
, _("\
11605 -mevexrcig=[rne|rd|ru|rz] (default: rne)\n\
11606 encode EVEX instructions with specific EVEX.RC value\n\
11607 for SAE-only ignored instructions\n"));
11608 fprintf (stream
, _("\
11609 -mmnemonic=[att|intel] "));
11610 if (SYSV386_COMPAT
)
11611 fprintf (stream
, _("(default: att)\n"));
11613 fprintf (stream
, _("(default: intel)\n"));
11614 fprintf (stream
, _("\
11615 use AT&T/Intel mnemonic\n"));
11616 fprintf (stream
, _("\
11617 -msyntax=[att|intel] (default: att)\n\
11618 use AT&T/Intel syntax\n"));
11619 fprintf (stream
, _("\
11620 -mindex-reg support pseudo index registers\n"));
11621 fprintf (stream
, _("\
11622 -mnaked-reg don't require `%%' prefix for registers\n"));
11623 fprintf (stream
, _("\
11624 -madd-bnd-prefix add BND prefix for all valid branches\n"));
11625 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11626 fprintf (stream
, _("\
11627 -mshared disable branch optimization for shared code\n"));
11628 fprintf (stream
, _("\
11629 -mx86-used-note=[no|yes] "));
11630 if (DEFAULT_X86_USED_NOTE
)
11631 fprintf (stream
, _("(default: yes)\n"));
11633 fprintf (stream
, _("(default: no)\n"));
11634 fprintf (stream
, _("\
11635 generate x86 used ISA and feature properties\n"));
11637 #if defined (TE_PE) || defined (TE_PEP)
11638 fprintf (stream
, _("\
11639 -mbig-obj generate big object files\n"));
11641 fprintf (stream
, _("\
11642 -momit-lock-prefix=[no|yes] (default: no)\n\
11643 strip all lock prefixes\n"));
11644 fprintf (stream
, _("\
11645 -mfence-as-lock-add=[no|yes] (default: no)\n\
11646 encode lfence, mfence and sfence as\n\
11647 lock addl $0x0, (%%{re}sp)\n"));
11648 fprintf (stream
, _("\
11649 -mrelax-relocations=[no|yes] "));
11650 if (DEFAULT_GENERATE_X86_RELAX_RELOCATIONS
)
11651 fprintf (stream
, _("(default: yes)\n"));
11653 fprintf (stream
, _("(default: no)\n"));
11654 fprintf (stream
, _("\
11655 generate relax relocations\n"));
11656 fprintf (stream
, _("\
11657 -mamd64 accept only AMD64 ISA [default]\n"));
11658 fprintf (stream
, _("\
11659 -mintel64 accept only Intel64 ISA\n"));
11662 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
11663 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
11664 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
11666 /* Pick the target format to use. */
11669 i386_target_format (void)
11671 if (!strncmp (default_arch
, "x86_64", 6))
11673 update_code_flag (CODE_64BIT
, 1);
11674 if (default_arch
[6] == '\0')
11675 x86_elf_abi
= X86_64_ABI
;
11677 x86_elf_abi
= X86_64_X32_ABI
;
11679 else if (!strcmp (default_arch
, "i386"))
11680 update_code_flag (CODE_32BIT
, 1);
11681 else if (!strcmp (default_arch
, "iamcu"))
11683 update_code_flag (CODE_32BIT
, 1);
11684 if (cpu_arch_isa
== PROCESSOR_UNKNOWN
)
11686 static const i386_cpu_flags iamcu_flags
= CPU_IAMCU_FLAGS
;
11687 cpu_arch_name
= "iamcu";
11688 cpu_sub_arch_name
= NULL
;
11689 cpu_arch_flags
= iamcu_flags
;
11690 cpu_arch_isa
= PROCESSOR_IAMCU
;
11691 cpu_arch_isa_flags
= iamcu_flags
;
11692 if (!cpu_arch_tune_set
)
11694 cpu_arch_tune
= cpu_arch_isa
;
11695 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
11698 else if (cpu_arch_isa
!= PROCESSOR_IAMCU
)
11699 as_fatal (_("Intel MCU doesn't support `%s' architecture"),
11703 as_fatal (_("unknown architecture"));
11705 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
11706 cpu_arch_isa_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
11707 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
11708 cpu_arch_tune_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
11710 switch (OUTPUT_FLAVOR
)
11712 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
11713 case bfd_target_aout_flavour
:
11714 return AOUT_TARGET_FORMAT
;
11716 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
11717 # if defined (TE_PE) || defined (TE_PEP)
11718 case bfd_target_coff_flavour
:
11719 if (flag_code
== CODE_64BIT
)
11720 return use_big_obj
? "pe-bigobj-x86-64" : "pe-x86-64";
11723 # elif defined (TE_GO32)
11724 case bfd_target_coff_flavour
:
11725 return "coff-go32";
11727 case bfd_target_coff_flavour
:
11728 return "coff-i386";
11731 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
11732 case bfd_target_elf_flavour
:
11734 const char *format
;
11736 switch (x86_elf_abi
)
11739 format
= ELF_TARGET_FORMAT
;
11742 use_rela_relocations
= 1;
11744 format
= ELF_TARGET_FORMAT64
;
11746 case X86_64_X32_ABI
:
11747 use_rela_relocations
= 1;
11749 disallow_64bit_reloc
= 1;
11750 format
= ELF_TARGET_FORMAT32
;
11753 if (cpu_arch_isa
== PROCESSOR_L1OM
)
11755 if (x86_elf_abi
!= X86_64_ABI
)
11756 as_fatal (_("Intel L1OM is 64bit only"));
11757 return ELF_TARGET_L1OM_FORMAT
;
11759 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
11761 if (x86_elf_abi
!= X86_64_ABI
)
11762 as_fatal (_("Intel K1OM is 64bit only"));
11763 return ELF_TARGET_K1OM_FORMAT
;
11765 else if (cpu_arch_isa
== PROCESSOR_IAMCU
)
11767 if (x86_elf_abi
!= I386_ABI
)
11768 as_fatal (_("Intel MCU is 32bit only"));
11769 return ELF_TARGET_IAMCU_FORMAT
;
11775 #if defined (OBJ_MACH_O)
11776 case bfd_target_mach_o_flavour
:
11777 if (flag_code
== CODE_64BIT
)
11779 use_rela_relocations
= 1;
11781 return "mach-o-x86-64";
11784 return "mach-o-i386";
11792 #endif /* OBJ_MAYBE_ more than one */
11795 md_undefined_symbol (char *name
)
11797 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
11798 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
11799 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
11800 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
11804 if (symbol_find (name
))
11805 as_bad (_("GOT already in symbol table"));
11806 GOT_symbol
= symbol_new (name
, undefined_section
,
11807 (valueT
) 0, &zero_address_frag
);
11814 /* Round up a section size to the appropriate boundary. */
11817 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
11819 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
11820 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
11822 /* For a.out, force the section size to be aligned. If we don't do
11823 this, BFD will align it for us, but it will not write out the
11824 final bytes of the section. This may be a bug in BFD, but it is
11825 easier to fix it here since that is how the other a.out targets
11829 align
= bfd_get_section_alignment (stdoutput
, segment
);
11830 size
= ((size
+ (1 << align
) - 1) & (-((valueT
) 1 << align
)));
11837 /* On the i386, PC-relative offsets are relative to the start of the
11838 next instruction. That is, the address of the offset, plus its
11839 size, since the offset is always the last part of the insn. */
11842 md_pcrel_from (fixS
*fixP
)
11844 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
11850 s_bss (int ignore ATTRIBUTE_UNUSED
)
11854 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11856 obj_elf_section_change_hook ();
11858 temp
= get_absolute_expression ();
11859 subseg_set (bss_section
, (subsegT
) temp
);
11860 demand_empty_rest_of_line ();
11866 i386_validate_fix (fixS
*fixp
)
11868 if (fixp
->fx_subsy
)
11870 if (fixp
->fx_subsy
== GOT_symbol
)
11872 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
11876 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11877 if (fixp
->fx_tcbit2
)
11878 fixp
->fx_r_type
= (fixp
->fx_tcbit
11879 ? BFD_RELOC_X86_64_REX_GOTPCRELX
11880 : BFD_RELOC_X86_64_GOTPCRELX
);
11883 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
11888 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
11890 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
11892 fixp
->fx_subsy
= 0;
11895 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11896 else if (!object_64bit
)
11898 if (fixp
->fx_r_type
== BFD_RELOC_386_GOT32
11899 && fixp
->fx_tcbit2
)
11900 fixp
->fx_r_type
= BFD_RELOC_386_GOT32X
;
11906 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
11909 bfd_reloc_code_real_type code
;
11911 switch (fixp
->fx_r_type
)
11913 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11914 case BFD_RELOC_SIZE32
:
11915 case BFD_RELOC_SIZE64
:
11916 if (S_IS_DEFINED (fixp
->fx_addsy
)
11917 && !S_IS_EXTERNAL (fixp
->fx_addsy
))
11919 /* Resolve size relocation against local symbol to size of
11920 the symbol plus addend. */
11921 valueT value
= S_GET_SIZE (fixp
->fx_addsy
) + fixp
->fx_offset
;
11922 if (fixp
->fx_r_type
== BFD_RELOC_SIZE32
11923 && !fits_in_unsigned_long (value
))
11924 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
11925 _("symbol size computation overflow"));
11926 fixp
->fx_addsy
= NULL
;
11927 fixp
->fx_subsy
= NULL
;
11928 md_apply_fix (fixp
, (valueT
*) &value
, NULL
);
11932 /* Fall through. */
11934 case BFD_RELOC_X86_64_PLT32
:
11935 case BFD_RELOC_X86_64_GOT32
:
11936 case BFD_RELOC_X86_64_GOTPCREL
:
11937 case BFD_RELOC_X86_64_GOTPCRELX
:
11938 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
11939 case BFD_RELOC_386_PLT32
:
11940 case BFD_RELOC_386_GOT32
:
11941 case BFD_RELOC_386_GOT32X
:
11942 case BFD_RELOC_386_GOTOFF
:
11943 case BFD_RELOC_386_GOTPC
:
11944 case BFD_RELOC_386_TLS_GD
:
11945 case BFD_RELOC_386_TLS_LDM
:
11946 case BFD_RELOC_386_TLS_LDO_32
:
11947 case BFD_RELOC_386_TLS_IE_32
:
11948 case BFD_RELOC_386_TLS_IE
:
11949 case BFD_RELOC_386_TLS_GOTIE
:
11950 case BFD_RELOC_386_TLS_LE_32
:
11951 case BFD_RELOC_386_TLS_LE
:
11952 case BFD_RELOC_386_TLS_GOTDESC
:
11953 case BFD_RELOC_386_TLS_DESC_CALL
:
11954 case BFD_RELOC_X86_64_TLSGD
:
11955 case BFD_RELOC_X86_64_TLSLD
:
11956 case BFD_RELOC_X86_64_DTPOFF32
:
11957 case BFD_RELOC_X86_64_DTPOFF64
:
11958 case BFD_RELOC_X86_64_GOTTPOFF
:
11959 case BFD_RELOC_X86_64_TPOFF32
:
11960 case BFD_RELOC_X86_64_TPOFF64
:
11961 case BFD_RELOC_X86_64_GOTOFF64
:
11962 case BFD_RELOC_X86_64_GOTPC32
:
11963 case BFD_RELOC_X86_64_GOT64
:
11964 case BFD_RELOC_X86_64_GOTPCREL64
:
11965 case BFD_RELOC_X86_64_GOTPC64
:
11966 case BFD_RELOC_X86_64_GOTPLT64
:
11967 case BFD_RELOC_X86_64_PLTOFF64
:
11968 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
11969 case BFD_RELOC_X86_64_TLSDESC_CALL
:
11970 case BFD_RELOC_RVA
:
11971 case BFD_RELOC_VTABLE_ENTRY
:
11972 case BFD_RELOC_VTABLE_INHERIT
:
11974 case BFD_RELOC_32_SECREL
:
11976 code
= fixp
->fx_r_type
;
11978 case BFD_RELOC_X86_64_32S
:
11979 if (!fixp
->fx_pcrel
)
11981 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
11982 code
= fixp
->fx_r_type
;
11985 /* Fall through. */
11987 if (fixp
->fx_pcrel
)
11989 switch (fixp
->fx_size
)
11992 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
11993 _("can not do %d byte pc-relative relocation"),
11995 code
= BFD_RELOC_32_PCREL
;
11997 case 1: code
= BFD_RELOC_8_PCREL
; break;
11998 case 2: code
= BFD_RELOC_16_PCREL
; break;
11999 case 4: code
= BFD_RELOC_32_PCREL
; break;
12001 case 8: code
= BFD_RELOC_64_PCREL
; break;
12007 switch (fixp
->fx_size
)
12010 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
12011 _("can not do %d byte relocation"),
12013 code
= BFD_RELOC_32
;
12015 case 1: code
= BFD_RELOC_8
; break;
12016 case 2: code
= BFD_RELOC_16
; break;
12017 case 4: code
= BFD_RELOC_32
; break;
12019 case 8: code
= BFD_RELOC_64
; break;
12026 if ((code
== BFD_RELOC_32
12027 || code
== BFD_RELOC_32_PCREL
12028 || code
== BFD_RELOC_X86_64_32S
)
12030 && fixp
->fx_addsy
== GOT_symbol
)
12033 code
= BFD_RELOC_386_GOTPC
;
12035 code
= BFD_RELOC_X86_64_GOTPC32
;
12037 if ((code
== BFD_RELOC_64
|| code
== BFD_RELOC_64_PCREL
)
12039 && fixp
->fx_addsy
== GOT_symbol
)
12041 code
= BFD_RELOC_X86_64_GOTPC64
;
12044 rel
= XNEW (arelent
);
12045 rel
->sym_ptr_ptr
= XNEW (asymbol
*);
12046 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
12048 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
12050 if (!use_rela_relocations
)
12052 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
12053 vtable entry to be used in the relocation's section offset. */
12054 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
12055 rel
->address
= fixp
->fx_offset
;
12056 #if defined (OBJ_COFF) && defined (TE_PE)
12057 else if (fixp
->fx_addsy
&& S_IS_WEAK (fixp
->fx_addsy
))
12058 rel
->addend
= fixp
->fx_addnumber
- (S_GET_VALUE (fixp
->fx_addsy
) * 2);
12063 /* Use the rela in 64bit mode. */
12066 if (disallow_64bit_reloc
)
12069 case BFD_RELOC_X86_64_DTPOFF64
:
12070 case BFD_RELOC_X86_64_TPOFF64
:
12071 case BFD_RELOC_64_PCREL
:
12072 case BFD_RELOC_X86_64_GOTOFF64
:
12073 case BFD_RELOC_X86_64_GOT64
:
12074 case BFD_RELOC_X86_64_GOTPCREL64
:
12075 case BFD_RELOC_X86_64_GOTPC64
:
12076 case BFD_RELOC_X86_64_GOTPLT64
:
12077 case BFD_RELOC_X86_64_PLTOFF64
:
12078 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
12079 _("cannot represent relocation type %s in x32 mode"),
12080 bfd_get_reloc_code_name (code
));
12086 if (!fixp
->fx_pcrel
)
12087 rel
->addend
= fixp
->fx_offset
;
12091 case BFD_RELOC_X86_64_PLT32
:
12092 case BFD_RELOC_X86_64_GOT32
:
12093 case BFD_RELOC_X86_64_GOTPCREL
:
12094 case BFD_RELOC_X86_64_GOTPCRELX
:
12095 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
12096 case BFD_RELOC_X86_64_TLSGD
:
12097 case BFD_RELOC_X86_64_TLSLD
:
12098 case BFD_RELOC_X86_64_GOTTPOFF
:
12099 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
12100 case BFD_RELOC_X86_64_TLSDESC_CALL
:
12101 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
12104 rel
->addend
= (section
->vma
12106 + fixp
->fx_addnumber
12107 + md_pcrel_from (fixp
));
12112 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
12113 if (rel
->howto
== NULL
)
12115 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
12116 _("cannot represent relocation type %s"),
12117 bfd_get_reloc_code_name (code
));
12118 /* Set howto to a garbage value so that we can keep going. */
12119 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
12120 gas_assert (rel
->howto
!= NULL
);
12126 #include "tc-i386-intel.c"
12129 tc_x86_parse_to_dw2regnum (expressionS
*exp
)
12131 int saved_naked_reg
;
12132 char saved_register_dot
;
12134 saved_naked_reg
= allow_naked_reg
;
12135 allow_naked_reg
= 1;
12136 saved_register_dot
= register_chars
['.'];
12137 register_chars
['.'] = '.';
12138 allow_pseudo_reg
= 1;
12139 expression_and_evaluate (exp
);
12140 allow_pseudo_reg
= 0;
12141 register_chars
['.'] = saved_register_dot
;
12142 allow_naked_reg
= saved_naked_reg
;
12144 if (exp
->X_op
== O_register
&& exp
->X_add_number
>= 0)
12146 if ((addressT
) exp
->X_add_number
< i386_regtab_size
)
12148 exp
->X_op
= O_constant
;
12149 exp
->X_add_number
= i386_regtab
[exp
->X_add_number
]
12150 .dw2_regnum
[flag_code
>> 1];
12153 exp
->X_op
= O_illegal
;
12158 tc_x86_frame_initial_instructions (void)
12160 static unsigned int sp_regno
[2];
12162 if (!sp_regno
[flag_code
>> 1])
12164 char *saved_input
= input_line_pointer
;
12165 char sp
[][4] = {"esp", "rsp"};
12168 input_line_pointer
= sp
[flag_code
>> 1];
12169 tc_x86_parse_to_dw2regnum (&exp
);
12170 gas_assert (exp
.X_op
== O_constant
);
12171 sp_regno
[flag_code
>> 1] = exp
.X_add_number
;
12172 input_line_pointer
= saved_input
;
12175 cfi_add_CFA_def_cfa (sp_regno
[flag_code
>> 1], -x86_cie_data_alignment
);
12176 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
12180 x86_dwarf2_addr_size (void)
12182 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
12183 if (x86_elf_abi
== X86_64_X32_ABI
)
12186 return bfd_arch_bits_per_address (stdoutput
) / 8;
12190 i386_elf_section_type (const char *str
, size_t len
)
12192 if (flag_code
== CODE_64BIT
12193 && len
== sizeof ("unwind") - 1
12194 && strncmp (str
, "unwind", 6) == 0)
12195 return SHT_X86_64_UNWIND
;
12202 i386_solaris_fix_up_eh_frame (segT sec
)
12204 if (flag_code
== CODE_64BIT
)
12205 elf_section_type (sec
) = SHT_X86_64_UNWIND
;
12211 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
12215 exp
.X_op
= O_secrel
;
12216 exp
.X_add_symbol
= symbol
;
12217 exp
.X_add_number
= 0;
12218 emit_expr (&exp
, size
);
12222 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12223 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
12226 x86_64_section_letter (int letter
, const char **ptr_msg
)
12228 if (flag_code
== CODE_64BIT
)
12231 return SHF_X86_64_LARGE
;
12233 *ptr_msg
= _("bad .section directive: want a,l,w,x,M,S,G,T in string");
12236 *ptr_msg
= _("bad .section directive: want a,w,x,M,S,G,T in string");
12241 x86_64_section_word (char *str
, size_t len
)
12243 if (len
== 5 && flag_code
== CODE_64BIT
&& CONST_STRNEQ (str
, "large"))
12244 return SHF_X86_64_LARGE
;
12250 handle_large_common (int small ATTRIBUTE_UNUSED
)
12252 if (flag_code
!= CODE_64BIT
)
12254 s_comm_internal (0, elf_common_parse
);
12255 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
12259 static segT lbss_section
;
12260 asection
*saved_com_section_ptr
= elf_com_section_ptr
;
12261 asection
*saved_bss_section
= bss_section
;
12263 if (lbss_section
== NULL
)
12265 flagword applicable
;
12266 segT seg
= now_seg
;
12267 subsegT subseg
= now_subseg
;
12269 /* The .lbss section is for local .largecomm symbols. */
12270 lbss_section
= subseg_new (".lbss", 0);
12271 applicable
= bfd_applicable_section_flags (stdoutput
);
12272 bfd_set_section_flags (stdoutput
, lbss_section
,
12273 applicable
& SEC_ALLOC
);
12274 seg_info (lbss_section
)->bss
= 1;
12276 subseg_set (seg
, subseg
);
12279 elf_com_section_ptr
= &_bfd_elf_large_com_section
;
12280 bss_section
= lbss_section
;
12282 s_comm_internal (0, elf_common_parse
);
12284 elf_com_section_ptr
= saved_com_section_ptr
;
12285 bss_section
= saved_bss_section
;
12288 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */