1 /* i386.c -- Assemble code for the Intel 80386
2 Copyright (C) 1989, 91, 92, 93, 94, 95, 96, 97, 98, 99, 2000
3 Free Software Foundation, Inc.
5 This file is part of GAS, the GNU Assembler.
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
22 /* Intel 80386 machine specific gas.
23 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
24 Bugs & suggestions are completely welcome. This is free software.
25 Please help us make it better. */
31 #include "opcode/i386.h"
33 #ifndef REGISTER_WARNINGS
34 #define REGISTER_WARNINGS 1
37 #ifndef INFER_ADDR_PREFIX
38 #define INFER_ADDR_PREFIX 1
41 #ifndef SCALE1_WHEN_NO_INDEX
42 /* Specifying a scale factor besides 1 when there is no index is
43 futile. eg. `mov (%ebx,2),%al' does exactly the same as
44 `mov (%ebx),%al'. To slavishly follow what the programmer
45 specified, set SCALE1_WHEN_NO_INDEX to 0. */
46 #define SCALE1_WHEN_NO_INDEX 1
52 static unsigned int mode_from_disp_size
PARAMS ((unsigned int));
53 static int fits_in_signed_byte
PARAMS ((offsetT
));
54 static int fits_in_unsigned_byte
PARAMS ((offsetT
));
55 static int fits_in_unsigned_word
PARAMS ((offsetT
));
56 static int fits_in_signed_word
PARAMS ((offsetT
));
57 static int smallest_imm_type
PARAMS ((offsetT
));
58 static offsetT offset_in_range
PARAMS ((offsetT
, int));
59 static int add_prefix
PARAMS ((unsigned int));
60 static void set_16bit_code_flag
PARAMS ((int));
61 static void set_16bit_gcc_code_flag
PARAMS ((int));
62 static void set_intel_syntax
PARAMS ((int));
63 static void set_cpu_arch
PARAMS ((int));
66 static bfd_reloc_code_real_type reloc
67 PARAMS ((int, int, bfd_reloc_code_real_type
));
70 /* 'md_assemble ()' gathers together information and puts it into a
77 const reg_entry
*regs
;
82 /* TM holds the template for the insn were currently assembling. */
85 /* SUFFIX holds the instruction mnemonic suffix if given.
86 (e.g. 'l' for 'movl') */
89 /* OPERANDS gives the number of given operands. */
90 unsigned int operands
;
92 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
93 of given register, displacement, memory operands and immediate
95 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
97 /* TYPES [i] is the type (see above #defines) which tells us how to
98 use OP[i] for the corresponding operand. */
99 unsigned int types
[MAX_OPERANDS
];
101 /* Displacement expression, immediate expression, or register for each
103 union i386_op op
[MAX_OPERANDS
];
105 /* Relocation type for operand */
107 enum bfd_reloc_code_real disp_reloc
[MAX_OPERANDS
];
109 int disp_reloc
[MAX_OPERANDS
];
112 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
113 the base index byte below. */
114 const reg_entry
*base_reg
;
115 const reg_entry
*index_reg
;
116 unsigned int log2_scale_factor
;
118 /* SEG gives the seg_entries of this insn. They are zero unless
119 explicit segment overrides are given. */
120 const seg_entry
*seg
[2]; /* segments for memory operands (if given) */
122 /* PREFIX holds all the given prefix opcodes (usually null).
123 PREFIXES is the number of prefix opcodes. */
124 unsigned int prefixes
;
125 unsigned char prefix
[MAX_PREFIXES
];
127 /* RM and SIB are the modrm byte and the sib byte where the
128 addressing modes of this insn are encoded. */
134 typedef struct _i386_insn i386_insn
;
136 /* List of chars besides those in app.c:symbol_chars that can start an
137 operand. Used to prevent the scrubber eating vital white-space. */
139 const char extra_symbol_chars
[] = "*%-(@";
141 const char extra_symbol_chars
[] = "*%-(";
144 /* This array holds the chars that always start a comment. If the
145 pre-processor is disabled, these aren't very useful */
146 #if defined (TE_I386AIX) || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) && ! defined (TE_LINUX) && !defined(TE_FreeBSD))
147 /* Putting '/' here makes it impossible to use the divide operator.
148 However, we need it for compatibility with SVR4 systems. */
149 const char comment_chars
[] = "#/";
150 #define PREFIX_SEPARATOR '\\'
152 const char comment_chars
[] = "#";
153 #define PREFIX_SEPARATOR '/'
156 /* This array holds the chars that only start a comment at the beginning of
157 a line. If the line seems to have the form '# 123 filename'
158 .line and .file directives will appear in the pre-processed output */
159 /* Note that input_file.c hand checks for '#' at the beginning of the
160 first line of the input file. This is because the compiler outputs
161 #NO_APP at the beginning of its output. */
162 /* Also note that comments started like this one will always work if
163 '/' isn't otherwise defined. */
164 #if defined (TE_I386AIX) || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) && ! defined (TE_LINUX) && !defined(TE_FreeBSD))
165 const char line_comment_chars
[] = "";
167 const char line_comment_chars
[] = "/";
170 const char line_separator_chars
[] = ";";
172 /* Chars that can be used to separate mant from exp in floating point nums */
173 const char EXP_CHARS
[] = "eE";
175 /* Chars that mean this number is a floating point constant */
178 const char FLT_CHARS
[] = "fFdDxX";
180 /* tables for lexical analysis */
181 static char mnemonic_chars
[256];
182 static char register_chars
[256];
183 static char operand_chars
[256];
184 static char identifier_chars
[256];
185 static char digit_chars
[256];
188 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
189 #define is_operand_char(x) (operand_chars[(unsigned char) x])
190 #define is_register_char(x) (register_chars[(unsigned char) x])
191 #define is_space_char(x) ((x) == ' ')
192 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
193 #define is_digit_char(x) (digit_chars[(unsigned char) x])
195 /* put here all non-digit non-letter charcters that may occur in an operand */
196 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
198 /* md_assemble() always leaves the strings it's passed unaltered. To
199 effect this we maintain a stack of saved characters that we've smashed
200 with '\0's (indicating end of strings for various sub-fields of the
201 assembler instruction). */
202 static char save_stack
[32];
203 static char *save_stack_p
; /* stack pointer */
204 #define END_STRING_AND_SAVE(s) \
205 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
206 #define RESTORE_END_STRING(s) \
207 do { *(s) = *--save_stack_p; } while (0)
209 /* The instruction we're assembling. */
212 /* Possible templates for current insn. */
213 static const templates
*current_templates
;
215 /* Per instruction expressionS buffers: 2 displacements & 2 immediate max. */
216 static expressionS disp_expressions
[2], im_expressions
[2];
218 /* Current operand we are working on. */
219 static int this_operand
;
221 /* 1 if we're writing 16-bit code,
223 static int flag_16bit_code
;
225 /* 1 for intel syntax,
227 static int intel_syntax
= 0;
229 /* 1 if register prefix % not required. */
230 static int allow_naked_reg
= 0;
232 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
233 leave, push, and pop instructions so that gcc has the same stack
234 frame as in 32 bit mode. */
235 static char stackop_size
= '\0';
237 /* Non-zero to quieten some warnings. */
238 static int quiet_warnings
= 0;
241 static const char *cpu_arch_name
= NULL
;
243 /* CPU feature flags. */
244 static unsigned int cpu_arch_flags
= 0;
246 /* Interface to relax_segment.
247 There are 2 relax states for 386 jump insns: one for conditional &
248 one for unconditional jumps. This is because these two types of
249 jumps add different sizes to frags when we're figuring out what
250 sort of jump to choose to reach a given label. */
253 #define COND_JUMP 1 /* Conditional jump. */
254 #define UNCOND_JUMP 2 /* Unconditional jump. */
258 #define SMALL16 (SMALL|CODE16)
260 #define BIG16 (BIG|CODE16)
264 #define INLINE __inline__
270 #define ENCODE_RELAX_STATE(type,size) \
271 ((relax_substateT)((type<<2) | (size)))
272 #define SIZE_FROM_RELAX_STATE(s) \
273 ( (((s) & 0x3) == BIG ? 4 : (((s) & 0x3) == BIG16 ? 2 : 1)) )
275 /* This table is used by relax_frag to promote short jumps to long
276 ones where necessary. SMALL (short) jumps may be promoted to BIG
277 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
278 don't allow a short jump in a 32 bit code segment to be promoted to
279 a 16 bit offset jump because it's slower (requires data size
280 prefix), and doesn't work, unless the destination is in the bottom
281 64k of the code segment (The top 16 bits of eip are zeroed). */
283 const relax_typeS md_relax_table
[] =
286 1) most positive reach of this state,
287 2) most negative reach of this state,
288 3) how many bytes this mode will add to the size of the current frag
289 4) which index into the table to try if we can't fit into this one.
296 {127 + 1, -128 + 1, 0, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
297 {127 + 1, -128 + 1, 0, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
298 /* dword conditionals adds 4 bytes to frag:
299 1 extra opcode byte, 3 extra displacement bytes. */
301 /* word conditionals add 2 bytes to frag:
302 1 extra opcode byte, 1 extra displacement byte. */
305 {127 + 1, -128 + 1, 0, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
306 {127 + 1, -128 + 1, 0, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
307 /* dword jmp adds 3 bytes to frag:
308 0 extra opcode bytes, 3 extra displacement bytes. */
310 /* word jmp adds 1 byte to frag:
311 0 extra opcode bytes, 1 extra displacement byte. */
316 static const arch_entry cpu_arch
[] = {
318 {"i186", Cpu086
|Cpu186
},
319 {"i286", Cpu086
|Cpu186
|Cpu286
},
320 {"i386", Cpu086
|Cpu186
|Cpu286
|Cpu386
},
321 {"i486", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
},
322 {"i586", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|CpuMMX
},
323 {"i686", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuMMX
|CpuSSE
},
324 {"pentium", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|CpuMMX
},
325 {"pentiumpro",Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuMMX
|CpuSSE
},
326 {"k6", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|CpuMMX
|Cpu3dnow
},
327 {"athlon", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuMMX
|Cpu3dnow
},
332 i386_align_code (fragP
, count
)
336 /* Various efficient no-op patterns for aligning code labels. */
337 /* Note: Don't try to assemble the instructions in the comments. */
338 /* 0L and 0w are not legal */
339 static const char f32_1
[] =
341 static const char f32_2
[] =
342 {0x89,0xf6}; /* movl %esi,%esi */
343 static const char f32_3
[] =
344 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
345 static const char f32_4
[] =
346 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
347 static const char f32_5
[] =
349 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
350 static const char f32_6
[] =
351 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
352 static const char f32_7
[] =
353 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
354 static const char f32_8
[] =
356 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
357 static const char f32_9
[] =
358 {0x89,0xf6, /* movl %esi,%esi */
359 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
360 static const char f32_10
[] =
361 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
362 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
363 static const char f32_11
[] =
364 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
365 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
366 static const char f32_12
[] =
367 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
368 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
369 static const char f32_13
[] =
370 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
371 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
372 static const char f32_14
[] =
373 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
374 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
375 static const char f32_15
[] =
376 {0xeb,0x0d,0x90,0x90,0x90,0x90,0x90, /* jmp .+15; lotsa nops */
377 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
378 static const char f16_3
[] =
379 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
380 static const char f16_4
[] =
381 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
382 static const char f16_5
[] =
384 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
385 static const char f16_6
[] =
386 {0x89,0xf6, /* mov %si,%si */
387 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
388 static const char f16_7
[] =
389 {0x8d,0x74,0x00, /* lea 0(%si),%si */
390 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
391 static const char f16_8
[] =
392 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
393 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
394 static const char *const f32_patt
[] = {
395 f32_1
, f32_2
, f32_3
, f32_4
, f32_5
, f32_6
, f32_7
, f32_8
,
396 f32_9
, f32_10
, f32_11
, f32_12
, f32_13
, f32_14
, f32_15
398 static const char *const f16_patt
[] = {
399 f32_1
, f32_2
, f16_3
, f16_4
, f16_5
, f16_6
, f16_7
, f16_8
,
400 f32_15
, f32_15
, f32_15
, f32_15
, f32_15
, f32_15
, f32_15
403 if (count
> 0 && count
<= 15)
407 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
408 f16_patt
[count
- 1], count
);
410 /* Adjust jump offset. */
411 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
414 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
415 f32_patt
[count
- 1], count
);
416 fragP
->fr_var
= count
;
420 static char *output_invalid
PARAMS ((int c
));
421 static int i386_operand
PARAMS ((char *operand_string
));
422 static int i386_intel_operand
PARAMS ((char *operand_string
, int got_a_float
));
423 static const reg_entry
*parse_register
PARAMS ((char *reg_string
,
427 static void s_bss
PARAMS ((int));
430 symbolS
*GOT_symbol
; /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
432 static INLINE
unsigned int
433 mode_from_disp_size (t
)
436 return (t
& Disp8
) ? 1 : (t
& (Disp16
| Disp32
)) ? 2 : 0;
440 fits_in_signed_byte (num
)
443 return (num
>= -128) && (num
<= 127);
447 fits_in_unsigned_byte (num
)
450 return (num
& 0xff) == num
;
454 fits_in_unsigned_word (num
)
457 return (num
& 0xffff) == num
;
461 fits_in_signed_word (num
)
464 return (-32768 <= num
) && (num
<= 32767);
468 smallest_imm_type (num
)
471 if (cpu_arch_flags
!= 0
472 && cpu_arch_flags
!= (Cpu086
| Cpu186
| Cpu286
| Cpu386
| Cpu486
))
474 /* This code is disabled on the 486 because all the Imm1 forms
475 in the opcode table are slower on the i486. They're the
476 versions with the implicitly specified single-position
477 displacement, which has another syntax if you really want to
480 return Imm1
| Imm8
| Imm8S
| Imm16
| Imm32
;
482 return (fits_in_signed_byte (num
)
483 ? (Imm8S
| Imm8
| Imm16
| Imm32
)
484 : fits_in_unsigned_byte (num
)
485 ? (Imm8
| Imm16
| Imm32
)
486 : (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
492 offset_in_range (val
, size
)
500 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
501 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
502 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
506 /* If BFD64, sign extend val. */
507 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
508 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
510 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
512 char buf1
[40], buf2
[40];
514 sprint_value (buf1
, val
);
515 sprint_value (buf2
, val
& mask
);
516 as_warn (_("%s shortened to %s"), buf1
, buf2
);
521 /* Returns 0 if attempting to add a prefix where one from the same
522 class already exists, 1 if non rep/repne added, 2 if rep/repne
536 case CS_PREFIX_OPCODE
:
537 case DS_PREFIX_OPCODE
:
538 case ES_PREFIX_OPCODE
:
539 case FS_PREFIX_OPCODE
:
540 case GS_PREFIX_OPCODE
:
541 case SS_PREFIX_OPCODE
:
545 case REPNE_PREFIX_OPCODE
:
546 case REPE_PREFIX_OPCODE
:
549 case LOCK_PREFIX_OPCODE
:
557 case ADDR_PREFIX_OPCODE
:
561 case DATA_PREFIX_OPCODE
:
568 as_bad (_("same type of prefix used twice"));
573 i
.prefix
[q
] = prefix
;
578 set_16bit_code_flag (new_16bit_code_flag
)
579 int new_16bit_code_flag
;
581 flag_16bit_code
= new_16bit_code_flag
;
586 set_16bit_gcc_code_flag (new_16bit_code_flag
)
587 int new_16bit_code_flag
;
589 flag_16bit_code
= new_16bit_code_flag
;
590 stackop_size
= new_16bit_code_flag
? 'l' : '\0';
594 set_intel_syntax (syntax_flag
)
597 /* Find out if register prefixing is specified. */
598 int ask_naked_reg
= 0;
601 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
603 char *string
= input_line_pointer
;
604 int e
= get_symbol_end ();
606 if (strcmp (string
, "prefix") == 0)
608 else if (strcmp (string
, "noprefix") == 0)
611 as_bad (_("bad argument to syntax directive."));
612 *input_line_pointer
= e
;
614 demand_empty_rest_of_line ();
616 intel_syntax
= syntax_flag
;
618 if (ask_naked_reg
== 0)
621 allow_naked_reg
= (intel_syntax
622 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
624 /* Conservative default. */
629 allow_naked_reg
= (ask_naked_reg
< 0);
634 int dummy ATTRIBUTE_UNUSED
;
638 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
640 char *string
= input_line_pointer
;
641 int e
= get_symbol_end ();
644 for (i
= 0; cpu_arch
[i
].name
; i
++)
646 if (strcmp (string
, cpu_arch
[i
].name
) == 0)
648 cpu_arch_name
= cpu_arch
[i
].name
;
649 cpu_arch_flags
= cpu_arch
[i
].flags
;
653 if (!cpu_arch
[i
].name
)
654 as_bad (_("no such architecture: `%s'"), string
);
656 *input_line_pointer
= e
;
659 as_bad (_("missing cpu architecture"));
661 demand_empty_rest_of_line ();
664 const pseudo_typeS md_pseudo_table
[] =
666 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
667 {"align", s_align_bytes
, 0},
669 {"align", s_align_ptwo
, 0},
671 {"arch", set_cpu_arch
, 0},
675 {"ffloat", float_cons
, 'f'},
676 {"dfloat", float_cons
, 'd'},
677 {"tfloat", float_cons
, 'x'},
679 {"noopt", s_ignore
, 0},
680 {"optim", s_ignore
, 0},
681 {"code16gcc", set_16bit_gcc_code_flag
, 1},
682 {"code16", set_16bit_code_flag
, 1},
683 {"code32", set_16bit_code_flag
, 0},
684 {"intel_syntax", set_intel_syntax
, 1},
685 {"att_syntax", set_intel_syntax
, 0},
689 /* For interface with expression (). */
690 extern char *input_line_pointer
;
692 /* Hash table for instruction mnemonic lookup. */
693 static struct hash_control
*op_hash
;
695 /* Hash table for register lookup. */
696 static struct hash_control
*reg_hash
;
701 const char *hash_err
;
703 /* Initialize op_hash hash table. */
704 op_hash
= hash_new ();
707 register const template *optab
;
708 register templates
*core_optab
;
710 /* Setup for loop. */
712 core_optab
= (templates
*) xmalloc (sizeof (templates
));
713 core_optab
->start
= optab
;
718 if (optab
->name
== NULL
719 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
721 /* different name --> ship out current template list;
722 add to hash table; & begin anew. */
723 core_optab
->end
= optab
;
724 hash_err
= hash_insert (op_hash
,
730 as_fatal (_("Internal Error: Can't hash %s: %s"),
734 if (optab
->name
== NULL
)
736 core_optab
= (templates
*) xmalloc (sizeof (templates
));
737 core_optab
->start
= optab
;
742 /* Initialize reg_hash hash table. */
743 reg_hash
= hash_new ();
745 register const reg_entry
*regtab
;
747 for (regtab
= i386_regtab
;
748 regtab
< i386_regtab
+ sizeof (i386_regtab
) / sizeof (i386_regtab
[0]);
751 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (PTR
) regtab
);
757 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
762 for (c
= 0; c
< 256; c
++)
767 mnemonic_chars
[c
] = c
;
768 register_chars
[c
] = c
;
769 operand_chars
[c
] = c
;
771 else if (islower (c
))
773 mnemonic_chars
[c
] = c
;
774 register_chars
[c
] = c
;
775 operand_chars
[c
] = c
;
777 else if (isupper (c
))
779 mnemonic_chars
[c
] = tolower (c
);
780 register_chars
[c
] = mnemonic_chars
[c
];
781 operand_chars
[c
] = c
;
784 if (isalpha (c
) || isdigit (c
))
785 identifier_chars
[c
] = c
;
788 identifier_chars
[c
] = c
;
789 operand_chars
[c
] = c
;
794 identifier_chars
['@'] = '@';
796 digit_chars
['-'] = '-';
797 identifier_chars
['_'] = '_';
798 identifier_chars
['.'] = '.';
800 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
801 operand_chars
[(unsigned char) *p
] = *p
;
804 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
805 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
807 record_alignment (text_section
, 2);
808 record_alignment (data_section
, 2);
809 record_alignment (bss_section
, 2);
815 i386_print_statistics (file
)
818 hash_print_statistics (file
, "i386 opcode", op_hash
);
819 hash_print_statistics (file
, "i386 register", reg_hash
);
824 /* debugging routines for md_assemble */
825 static void pi
PARAMS ((char *, i386_insn
*));
826 static void pte
PARAMS ((template *));
827 static void pt
PARAMS ((unsigned int));
828 static void pe
PARAMS ((expressionS
*));
829 static void ps
PARAMS ((symbolS
*));
836 register template *p
;
839 fprintf (stdout
, "%s: template ", line
);
841 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x",
842 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
843 fprintf (stdout
, " base %x index %x scale %x\n",
844 x
->bi
.base
, x
->bi
.index
, x
->bi
.scale
);
845 for (i
= 0; i
< x
->operands
; i
++)
847 fprintf (stdout
, " #%d: ", i
+ 1);
849 fprintf (stdout
, "\n");
851 & (Reg
| SReg2
| SReg3
| Control
| Debug
| Test
| RegMMX
| RegXMM
))
852 fprintf (stdout
, "%s\n", x
->op
[i
].regs
->reg_name
);
853 if (x
->types
[i
] & Imm
)
855 if (x
->types
[i
] & Disp
)
865 fprintf (stdout
, " %d operands ", t
->operands
);
866 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
867 if (t
->extension_opcode
!= None
)
868 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
869 if (t
->opcode_modifier
& D
)
870 fprintf (stdout
, "D");
871 if (t
->opcode_modifier
& W
)
872 fprintf (stdout
, "W");
873 fprintf (stdout
, "\n");
874 for (i
= 0; i
< t
->operands
; i
++)
876 fprintf (stdout
, " #%d type ", i
+ 1);
877 pt (t
->operand_types
[i
]);
878 fprintf (stdout
, "\n");
886 fprintf (stdout
, " operation %d\n", e
->X_op
);
887 fprintf (stdout
, " add_number %ld (%lx)\n",
888 (long) e
->X_add_number
, (long) e
->X_add_number
);
891 fprintf (stdout
, " add_symbol ");
892 ps (e
->X_add_symbol
);
893 fprintf (stdout
, "\n");
897 fprintf (stdout
, " op_symbol ");
899 fprintf (stdout
, "\n");
907 fprintf (stdout
, "%s type %s%s",
909 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
910 segment_name (S_GET_SEGMENT (s
)));
929 { BaseIndex
, "BaseIndex" },
933 { InOutPortReg
, "InOutPortReg" },
934 { ShiftCount
, "ShiftCount" },
935 { Control
, "control reg" },
936 { Test
, "test reg" },
937 { Debug
, "debug reg" },
938 { FloatReg
, "FReg" },
939 { FloatAcc
, "FAcc" },
943 { JumpAbsolute
, "Jump Absolute" },
954 register struct type_name
*ty
;
958 fprintf (stdout
, _("Unknown"));
962 for (ty
= type_names
; ty
->mask
; ty
++)
964 fprintf (stdout
, "%s, ", ty
->tname
);
969 #endif /* DEBUG386 */
972 tc_i386_force_relocation (fixp
)
976 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
977 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
982 return fixp
->fx_r_type
== 7;
987 static bfd_reloc_code_real_type reloc
988 PARAMS ((int, int, bfd_reloc_code_real_type
));
990 static bfd_reloc_code_real_type
991 reloc (size
, pcrel
, other
)
994 bfd_reloc_code_real_type other
;
996 if (other
!= NO_RELOC
)
1003 case 1: return BFD_RELOC_8_PCREL
;
1004 case 2: return BFD_RELOC_16_PCREL
;
1005 case 4: return BFD_RELOC_32_PCREL
;
1007 as_bad (_("can not do %d byte pc-relative relocation"), size
);
1013 case 1: return BFD_RELOC_8
;
1014 case 2: return BFD_RELOC_16
;
1015 case 4: return BFD_RELOC_32
;
1017 as_bad (_("can not do %d byte relocation"), size
);
1020 return BFD_RELOC_NONE
;
1023 /* Here we decide which fixups can be adjusted to make them relative to
1024 the beginning of the section instead of the symbol. Basically we need
1025 to make sure that the dynamic relocations are done correctly, so in
1026 some cases we force the original symbol to be used. */
1029 tc_i386_fix_adjustable (fixP
)
1032 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1033 /* Prevent all adjustments to global symbols, or else dynamic
1034 linking will not work correctly. */
1035 if (S_IS_EXTERNAL (fixP
->fx_addsy
)
1036 || S_IS_WEAK (fixP
->fx_addsy
))
1039 /* adjust_reloc_syms doesn't know about the GOT */
1040 if (fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
1041 || fixP
->fx_r_type
== BFD_RELOC_386_PLT32
1042 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
1043 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
1044 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
1049 #define reloc(SIZE,PCREL,OTHER) 0
1050 #define BFD_RELOC_16 0
1051 #define BFD_RELOC_32 0
1052 #define BFD_RELOC_16_PCREL 0
1053 #define BFD_RELOC_32_PCREL 0
1054 #define BFD_RELOC_386_PLT32 0
1055 #define BFD_RELOC_386_GOT32 0
1056 #define BFD_RELOC_386_GOTOFF 0
1059 static int intel_float_operand
PARAMS ((char *mnemonic
));
1062 intel_float_operand (mnemonic
)
1065 if (mnemonic
[0] == 'f' && mnemonic
[1] == 'i')
1068 if (mnemonic
[0] == 'f')
1074 /* This is the guts of the machine-dependent assembler. LINE points to a
1075 machine dependent instruction. This function is supposed to emit
1076 the frags/bytes it assembles to. */
1082 /* Points to template once we've found it. */
1085 /* Count the size of the instruction generated. */
1090 char mnemonic
[MAX_MNEM_SIZE
];
1092 /* Initialize globals. */
1093 memset (&i
, '\0', sizeof (i
));
1094 for (j
= 0; j
< MAX_OPERANDS
; j
++)
1095 i
.disp_reloc
[j
] = NO_RELOC
;
1096 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
1097 memset (im_expressions
, '\0', sizeof (im_expressions
));
1098 save_stack_p
= save_stack
; /* reset stack pointer */
1100 /* First parse an instruction mnemonic & call i386_operand for the operands.
1101 We assume that the scrubber has arranged it so that line[0] is the valid
1102 start of a (possibly prefixed) mnemonic. */
1105 char *token_start
= l
;
1108 /* Non-zero if we found a prefix only acceptable with string insns. */
1109 const char *expecting_string_instruction
= NULL
;
1114 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
1117 if (mnem_p
>= mnemonic
+ sizeof (mnemonic
))
1119 as_bad (_("no such instruction: `%s'"), token_start
);
1124 if (!is_space_char (*l
)
1125 && *l
!= END_OF_INSN
1126 && *l
!= PREFIX_SEPARATOR
)
1128 as_bad (_("invalid character %s in mnemonic"),
1129 output_invalid (*l
));
1132 if (token_start
== l
)
1134 if (*l
== PREFIX_SEPARATOR
)
1135 as_bad (_("expecting prefix; got nothing"));
1137 as_bad (_("expecting mnemonic; got nothing"));
1141 /* Look up instruction (or prefix) via hash table. */
1142 current_templates
= hash_find (op_hash
, mnemonic
);
1144 if (*l
!= END_OF_INSN
1145 && (! is_space_char (*l
) || l
[1] != END_OF_INSN
)
1146 && current_templates
1147 && (current_templates
->start
->opcode_modifier
& IsPrefix
))
1149 /* If we are in 16-bit mode, do not allow addr16 or data16.
1150 Similarly, in 32-bit mode, do not allow addr32 or data32. */
1151 if ((current_templates
->start
->opcode_modifier
& (Size16
| Size32
))
1152 && (((current_templates
->start
->opcode_modifier
& Size32
) != 0)
1155 as_bad (_("redundant %s prefix"),
1156 current_templates
->start
->name
);
1159 /* Add prefix, checking for repeated prefixes. */
1160 switch (add_prefix (current_templates
->start
->base_opcode
))
1165 expecting_string_instruction
= current_templates
->start
->name
;
1168 /* Skip past PREFIX_SEPARATOR and reset token_start. */
1175 if (!current_templates
)
1177 /* See if we can get a match by trimming off a suffix. */
1180 case WORD_MNEM_SUFFIX
:
1181 case BYTE_MNEM_SUFFIX
:
1182 case SHORT_MNEM_SUFFIX
:
1183 case LONG_MNEM_SUFFIX
:
1184 i
.suffix
= mnem_p
[-1];
1186 current_templates
= hash_find (op_hash
, mnemonic
);
1190 case DWORD_MNEM_SUFFIX
:
1193 i
.suffix
= mnem_p
[-1];
1195 current_templates
= hash_find (op_hash
, mnemonic
);
1199 if (!current_templates
)
1201 as_bad (_("no such instruction: `%s'"), token_start
);
1206 /* Check if instruction is supported on specified architecture. */
1207 if (cpu_arch_flags
!= 0)
1209 if (current_templates
->start
->cpu_flags
& ~cpu_arch_flags
)
1211 as_warn (_("`%s' is not supported on `%s'"),
1212 current_templates
->start
->name
, cpu_arch_name
);
1214 else if ((Cpu386
& ~cpu_arch_flags
) && !flag_16bit_code
)
1216 as_warn (_("use .code16 to ensure correct addressing mode"));
1220 /* check for rep/repne without a string instruction */
1221 if (expecting_string_instruction
1222 && !(current_templates
->start
->opcode_modifier
& IsString
))
1224 as_bad (_("expecting string instruction after `%s'"),
1225 expecting_string_instruction
);
1229 /* There may be operands to parse. */
1230 if (*l
!= END_OF_INSN
)
1232 /* parse operands */
1234 /* 1 if operand is pending after ','. */
1235 unsigned int expecting_operand
= 0;
1237 /* Non-zero if operand parens not balanced. */
1238 unsigned int paren_not_balanced
;
1242 /* skip optional white space before operand */
1243 if (is_space_char (*l
))
1245 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
)
1247 as_bad (_("invalid character %s before operand %d"),
1248 output_invalid (*l
),
1252 token_start
= l
; /* after white space */
1253 paren_not_balanced
= 0;
1254 while (paren_not_balanced
|| *l
!= ',')
1256 if (*l
== END_OF_INSN
)
1258 if (paren_not_balanced
)
1261 as_bad (_("unbalanced parenthesis in operand %d."),
1264 as_bad (_("unbalanced brackets in operand %d."),
1269 break; /* we are done */
1271 else if (!is_operand_char (*l
) && !is_space_char (*l
))
1273 as_bad (_("invalid character %s in operand %d"),
1274 output_invalid (*l
),
1281 ++paren_not_balanced
;
1283 --paren_not_balanced
;
1288 ++paren_not_balanced
;
1290 --paren_not_balanced
;
1294 if (l
!= token_start
)
1295 { /* Yes, we've read in another operand. */
1296 unsigned int operand_ok
;
1297 this_operand
= i
.operands
++;
1298 if (i
.operands
> MAX_OPERANDS
)
1300 as_bad (_("spurious operands; (%d operands/instruction max)"),
1304 /* Now parse operand adding info to 'i' as we go along. */
1305 END_STRING_AND_SAVE (l
);
1309 i386_intel_operand (token_start
,
1310 intel_float_operand (mnemonic
));
1312 operand_ok
= i386_operand (token_start
);
1314 RESTORE_END_STRING (l
); /* restore old contents */
1320 if (expecting_operand
)
1322 expecting_operand_after_comma
:
1323 as_bad (_("expecting operand after ','; got nothing"));
1328 as_bad (_("expecting operand before ','; got nothing"));
1333 /* now *l must be either ',' or END_OF_INSN */
1336 if (*++l
== END_OF_INSN
)
1337 { /* just skip it, if it's \n complain */
1338 goto expecting_operand_after_comma
;
1340 expecting_operand
= 1;
1343 while (*l
!= END_OF_INSN
); /* until we get end of insn */
1347 /* Now we've parsed the mnemonic into a set of templates, and have the
1350 Next, we find a template that matches the given insn,
1351 making sure the overlap of the given operands types is consistent
1352 with the template operand types. */
1354 #define MATCH(overlap, given, template) \
1355 ((overlap & ~JumpAbsolute) \
1356 && ((given) & (BaseIndex|JumpAbsolute)) == ((overlap) & (BaseIndex|JumpAbsolute)))
1358 /* If given types r0 and r1 are registers they must be of the same type
1359 unless the expected operand type register overlap is null.
1360 Note that Acc in a template matches every size of reg. */
1361 #define CONSISTENT_REGISTER_MATCH(m0, g0, t0, m1, g1, t1) \
1362 ( ((g0) & Reg) == 0 || ((g1) & Reg) == 0 || \
1363 ((g0) & Reg) == ((g1) & Reg) || \
1364 ((((m0) & Acc) ? Reg : (t0)) & (((m1) & Acc) ? Reg : (t1)) & Reg) == 0 )
1367 register unsigned int overlap0
, overlap1
;
1368 unsigned int overlap2
;
1369 unsigned int found_reverse_match
;
1372 /* All intel opcodes have reversed operands except for "bound" and
1373 "enter". We also don't reverse intersegment "jmp" and "call"
1374 instructions with 2 immediate operands so that the immediate segment
1375 precedes the offset, as it does when in AT&T mode. "enter" and the
1376 intersegment "jmp" and "call" instructions are the only ones that
1377 have two immediate operands. */
1378 if (intel_syntax
&& i
.operands
> 1
1379 && (strcmp (mnemonic
, "bound") != 0)
1380 && !((i
.types
[0] & Imm
) && (i
.types
[1] & Imm
)))
1382 union i386_op temp_op
;
1383 unsigned int temp_type
;
1387 if (i
.operands
== 2)
1392 else if (i
.operands
== 3)
1397 temp_type
= i
.types
[xchg2
];
1398 i
.types
[xchg2
] = i
.types
[xchg1
];
1399 i
.types
[xchg1
] = temp_type
;
1400 temp_op
= i
.op
[xchg2
];
1401 i
.op
[xchg2
] = i
.op
[xchg1
];
1402 i
.op
[xchg1
] = temp_op
;
1404 if (i
.mem_operands
== 2)
1406 const seg_entry
*temp_seg
;
1407 temp_seg
= i
.seg
[0];
1408 i
.seg
[0] = i
.seg
[1];
1409 i
.seg
[1] = temp_seg
;
1415 /* Try to ensure constant immediates are represented in the smallest
1417 char guess_suffix
= 0;
1421 guess_suffix
= i
.suffix
;
1422 else if (i
.reg_operands
)
1424 /* Figure out a suffix from the last register operand specified.
1425 We can't do this properly yet, ie. excluding InOutPortReg,
1426 but the following works for instructions with immediates.
1427 In any case, we can't set i.suffix yet. */
1428 for (op
= i
.operands
; --op
>= 0;)
1429 if (i
.types
[op
] & Reg
)
1431 if (i
.types
[op
] & Reg8
)
1432 guess_suffix
= BYTE_MNEM_SUFFIX
;
1433 else if (i
.types
[op
] & Reg16
)
1434 guess_suffix
= WORD_MNEM_SUFFIX
;
1438 else if (flag_16bit_code
^ (i
.prefix
[DATA_PREFIX
] != 0))
1439 guess_suffix
= WORD_MNEM_SUFFIX
;
1441 for (op
= i
.operands
; --op
>= 0;)
1442 if ((i
.types
[op
] & Imm
)
1443 && i
.op
[op
].imms
->X_op
== O_constant
)
1445 /* If a suffix is given, this operand may be shortened. */
1446 switch (guess_suffix
)
1448 case WORD_MNEM_SUFFIX
:
1449 i
.types
[op
] |= Imm16
;
1451 case BYTE_MNEM_SUFFIX
:
1452 i
.types
[op
] |= Imm16
| Imm8
| Imm8S
;
1456 /* If this operand is at most 16 bits, convert it to a
1457 signed 16 bit number before trying to see whether it will
1458 fit in an even smaller size. This allows a 16-bit operand
1459 such as $0xffe0 to be recognised as within Imm8S range. */
1460 if ((i
.types
[op
] & Imm16
)
1461 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
)0xffff) == 0)
1463 i
.op
[op
].imms
->X_add_number
=
1464 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
1466 i
.types
[op
] |= smallest_imm_type ((long) i
.op
[op
].imms
->X_add_number
);
1470 if (i
.disp_operands
)
1472 /* Try to use the smallest displacement type too. */
1475 for (op
= i
.operands
; --op
>= 0;)
1476 if ((i
.types
[op
] & Disp
)
1477 && i
.op
[op
].imms
->X_op
== O_constant
)
1479 offsetT disp
= i
.op
[op
].disps
->X_add_number
;
1481 if (i
.types
[op
] & Disp16
)
1483 /* We know this operand is at most 16 bits, so
1484 convert to a signed 16 bit number before trying
1485 to see whether it will fit in an even smaller
1488 disp
= (((disp
& 0xffff) ^ 0x8000) - 0x8000);
1490 if (fits_in_signed_byte (disp
))
1491 i
.types
[op
] |= Disp8
;
1498 found_reverse_match
= 0;
1499 suffix_check
= (i
.suffix
== BYTE_MNEM_SUFFIX
1501 : (i
.suffix
== WORD_MNEM_SUFFIX
1503 : (i
.suffix
== SHORT_MNEM_SUFFIX
1505 : (i
.suffix
== LONG_MNEM_SUFFIX
1507 : (i
.suffix
== DWORD_MNEM_SUFFIX
1509 : (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
? No_xSuf
: 0))))));
1511 for (t
= current_templates
->start
;
1512 t
< current_templates
->end
;
1515 /* Must have right number of operands. */
1516 if (i
.operands
!= t
->operands
)
1519 /* Check the suffix, except for some instructions in intel mode. */
1520 if ((t
->opcode_modifier
& suffix_check
)
1522 && (t
->opcode_modifier
& IgnoreSize
))
1524 && t
->base_opcode
== 0xd9
1525 && (t
->extension_opcode
== 5 /* 0xd9,5 "fldcw" */
1526 || t
->extension_opcode
== 7))) /* 0xd9,7 "f{n}stcw" */
1529 else if (!t
->operands
)
1530 /* 0 operands always matches. */
1533 overlap0
= i
.types
[0] & t
->operand_types
[0];
1534 switch (t
->operands
)
1537 if (!MATCH (overlap0
, i
.types
[0], t
->operand_types
[0]))
1542 overlap1
= i
.types
[1] & t
->operand_types
[1];
1543 if (!MATCH (overlap0
, i
.types
[0], t
->operand_types
[0])
1544 || !MATCH (overlap1
, i
.types
[1], t
->operand_types
[1])
1545 || !CONSISTENT_REGISTER_MATCH (overlap0
, i
.types
[0],
1546 t
->operand_types
[0],
1547 overlap1
, i
.types
[1],
1548 t
->operand_types
[1]))
1550 /* Check if other direction is valid ... */
1551 if ((t
->opcode_modifier
& (D
|FloatD
)) == 0)
1554 /* Try reversing direction of operands. */
1555 overlap0
= i
.types
[0] & t
->operand_types
[1];
1556 overlap1
= i
.types
[1] & t
->operand_types
[0];
1557 if (!MATCH (overlap0
, i
.types
[0], t
->operand_types
[1])
1558 || !MATCH (overlap1
, i
.types
[1], t
->operand_types
[0])
1559 || !CONSISTENT_REGISTER_MATCH (overlap0
, i
.types
[0],
1560 t
->operand_types
[1],
1561 overlap1
, i
.types
[1],
1562 t
->operand_types
[0]))
1564 /* Does not match either direction. */
1567 /* found_reverse_match holds which of D or FloatDR
1569 found_reverse_match
= t
->opcode_modifier
& (D
|FloatDR
);
1572 /* Found a forward 2 operand match here. */
1573 if (t
->operands
== 3)
1575 /* Here we make use of the fact that there are no
1576 reverse match 3 operand instructions, and all 3
1577 operand instructions only need to be checked for
1578 register consistency between operands 2 and 3. */
1579 overlap2
= i
.types
[2] & t
->operand_types
[2];
1580 if (!MATCH (overlap2
, i
.types
[2], t
->operand_types
[2])
1581 || !CONSISTENT_REGISTER_MATCH (overlap1
, i
.types
[1],
1582 t
->operand_types
[1],
1583 overlap2
, i
.types
[2],
1584 t
->operand_types
[2]))
1588 /* Found either forward/reverse 2 or 3 operand match here:
1589 slip through to break */
1591 /* We've found a match; break out of loop. */
1593 } /* for (t = ... */
1594 if (t
== current_templates
->end
)
1596 /* We found no match. */
1597 as_bad (_("suffix or operands invalid for `%s'"),
1598 current_templates
->start
->name
);
1602 if (!quiet_warnings
)
1605 && ((i
.types
[0] & JumpAbsolute
)
1606 != (t
->operand_types
[0] & JumpAbsolute
)))
1608 as_warn (_("indirect %s without `*'"), t
->name
);
1611 if ((t
->opcode_modifier
& (IsPrefix
|IgnoreSize
))
1612 == (IsPrefix
|IgnoreSize
))
1614 /* Warn them that a data or address size prefix doesn't
1615 affect assembly of the next line of code. */
1616 as_warn (_("stand-alone `%s' prefix"), t
->name
);
1620 /* Copy the template we found. */
1622 if (found_reverse_match
)
1624 /* If we found a reverse match we must alter the opcode
1625 direction bit. found_reverse_match holds bits to change
1626 (different for int & float insns). */
1628 i
.tm
.base_opcode
^= found_reverse_match
;
1630 i
.tm
.operand_types
[0] = t
->operand_types
[1];
1631 i
.tm
.operand_types
[1] = t
->operand_types
[0];
1634 /* Undo SYSV386_COMPAT brokenness when in Intel mode. See i386.h */
1637 && (i
.tm
.base_opcode
& 0xfffffde0) == 0xdce0)
1638 i
.tm
.base_opcode
^= FloatR
;
1640 if (i
.tm
.opcode_modifier
& FWait
)
1641 if (! add_prefix (FWAIT_OPCODE
))
1644 /* Check string instruction segment overrides */
1645 if ((i
.tm
.opcode_modifier
& IsString
) != 0 && i
.mem_operands
!= 0)
1647 int mem_op
= (i
.types
[0] & AnyMem
) ? 0 : 1;
1648 if ((i
.tm
.operand_types
[mem_op
] & EsSeg
) != 0)
1650 if (i
.seg
[0] != NULL
&& i
.seg
[0] != &es
)
1652 as_bad (_("`%s' operand %d must use `%%es' segment"),
1657 /* There's only ever one segment override allowed per instruction.
1658 This instruction possibly has a legal segment override on the
1659 second operand, so copy the segment to where non-string
1660 instructions store it, allowing common code. */
1661 i
.seg
[0] = i
.seg
[1];
1663 else if ((i
.tm
.operand_types
[mem_op
+ 1] & EsSeg
) != 0)
1665 if (i
.seg
[1] != NULL
&& i
.seg
[1] != &es
)
1667 as_bad (_("`%s' operand %d must use `%%es' segment"),
1675 /* If matched instruction specifies an explicit instruction mnemonic
1677 if (i
.tm
.opcode_modifier
& (Size16
| Size32
))
1679 if (i
.tm
.opcode_modifier
& Size16
)
1680 i
.suffix
= WORD_MNEM_SUFFIX
;
1682 i
.suffix
= LONG_MNEM_SUFFIX
;
1684 else if (i
.reg_operands
)
1686 /* If there's no instruction mnemonic suffix we try to invent one
1687 based on register operands. */
1690 /* We take i.suffix from the last register operand specified,
1691 Destination register type is more significant than source
1694 for (op
= i
.operands
; --op
>= 0;)
1695 if ((i
.types
[op
] & Reg
)
1696 && !(i
.tm
.operand_types
[op
] & InOutPortReg
))
1698 i
.suffix
= ((i
.types
[op
] & Reg8
) ? BYTE_MNEM_SUFFIX
:
1699 (i
.types
[op
] & Reg16
) ? WORD_MNEM_SUFFIX
:
1704 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
1707 for (op
= i
.operands
; --op
>= 0;)
1709 /* If this is an eight bit register, it's OK. If it's
1710 the 16 or 32 bit version of an eight bit register,
1711 we will just use the low portion, and that's OK too. */
1712 if (i
.types
[op
] & Reg8
)
1715 /* movzx and movsx should not generate this warning. */
1717 && (i
.tm
.base_opcode
== 0xfb7
1718 || i
.tm
.base_opcode
== 0xfb6
1719 || i
.tm
.base_opcode
== 0xfbe
1720 || i
.tm
.base_opcode
== 0xfbf))
1723 if ((i
.types
[op
] & WordReg
) && i
.op
[op
].regs
->reg_num
< 4
1725 /* Check that the template allows eight bit regs
1726 This kills insns such as `orb $1,%edx', which
1727 maybe should be allowed. */
1728 && (i
.tm
.operand_types
[op
] & (Reg8
|InOutPortReg
))
1732 #if REGISTER_WARNINGS
1734 && (i
.tm
.operand_types
[op
] & InOutPortReg
) == 0)
1735 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
1736 (i
.op
[op
].regs
- (i
.types
[op
] & Reg16
? 8 : 16))->reg_name
,
1737 i
.op
[op
].regs
->reg_name
,
1742 /* Any other register is bad */
1743 if (i
.types
[op
] & (Reg
| RegMMX
| RegXMM
1745 | Control
| Debug
| Test
1746 | FloatReg
| FloatAcc
))
1748 as_bad (_("`%%%s' not allowed with `%s%c'"),
1749 i
.op
[op
].regs
->reg_name
,
1756 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
1760 for (op
= i
.operands
; --op
>= 0;)
1761 /* Reject eight bit registers, except where the template
1762 requires them. (eg. movzb) */
1763 if ((i
.types
[op
] & Reg8
) != 0
1764 && (i
.tm
.operand_types
[op
] & (Reg16
| Reg32
| Acc
)) != 0)
1766 as_bad (_("`%%%s' not allowed with `%s%c'"),
1767 i
.op
[op
].regs
->reg_name
,
1772 #if REGISTER_WARNINGS
1773 /* Warn if the e prefix on a general reg is missing. */
1774 else if (!quiet_warnings
1775 && (i
.types
[op
] & Reg16
) != 0
1776 && (i
.tm
.operand_types
[op
] & (Reg32
|Acc
)) != 0)
1778 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
1779 (i
.op
[op
].regs
+ 8)->reg_name
,
1780 i
.op
[op
].regs
->reg_name
,
1785 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
1788 for (op
= i
.operands
; --op
>= 0;)
1789 /* Reject eight bit registers, except where the template
1790 requires them. (eg. movzb) */
1791 if ((i
.types
[op
] & Reg8
) != 0
1792 && (i
.tm
.operand_types
[op
] & (Reg16
|Reg32
|Acc
)) != 0)
1794 as_bad (_("`%%%s' not allowed with `%s%c'"),
1795 i
.op
[op
].regs
->reg_name
,
1800 #if REGISTER_WARNINGS
1801 /* Warn if the e prefix on a general reg is present. */
1802 else if (!quiet_warnings
1803 && (i
.types
[op
] & Reg32
) != 0
1804 && (i
.tm
.operand_types
[op
] & (Reg16
|Acc
)) != 0)
1806 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
1807 (i
.op
[op
].regs
- 8)->reg_name
,
1808 i
.op
[op
].regs
->reg_name
,
1813 else if (intel_syntax
&& (i
.tm
.opcode_modifier
& IgnoreSize
))
1814 /* Do nothing if the instruction is going to ignore the prefix. */
1819 else if ((i
.tm
.opcode_modifier
& DefaultSize
) && !i
.suffix
)
1821 i
.suffix
= stackop_size
;
1824 /* Make still unresolved immediate matches conform to size of immediate
1825 given in i.suffix. Note: overlap2 cannot be an immediate! */
1826 if ((overlap0
& (Imm8
| Imm8S
| Imm16
| Imm32
))
1827 && overlap0
!= Imm8
&& overlap0
!= Imm8S
1828 && overlap0
!= Imm16
&& overlap0
!= Imm32
)
1832 overlap0
&= (i
.suffix
== BYTE_MNEM_SUFFIX
? (Imm8
| Imm8S
) :
1833 (i
.suffix
== WORD_MNEM_SUFFIX
? Imm16
: Imm32
));
1835 else if (overlap0
== (Imm16
| Imm32
))
1838 (flag_16bit_code
^ (i
.prefix
[DATA_PREFIX
] != 0)) ? Imm16
: Imm32
;
1842 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size"));
1846 if ((overlap1
& (Imm8
| Imm8S
| Imm16
| Imm32
))
1847 && overlap1
!= Imm8
&& overlap1
!= Imm8S
1848 && overlap1
!= Imm16
&& overlap1
!= Imm32
)
1852 overlap1
&= (i
.suffix
== BYTE_MNEM_SUFFIX
? (Imm8
| Imm8S
) :
1853 (i
.suffix
== WORD_MNEM_SUFFIX
? Imm16
: Imm32
));
1855 else if (overlap1
== (Imm16
| Imm32
))
1858 (flag_16bit_code
^ (i
.prefix
[DATA_PREFIX
] != 0)) ? Imm16
: Imm32
;
1862 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size"));
1866 assert ((overlap2
& Imm
) == 0);
1868 i
.types
[0] = overlap0
;
1869 if (overlap0
& ImplicitRegister
)
1871 if (overlap0
& Imm1
)
1872 i
.imm_operands
= 0; /* kludge for shift insns */
1874 i
.types
[1] = overlap1
;
1875 if (overlap1
& ImplicitRegister
)
1878 i
.types
[2] = overlap2
;
1879 if (overlap2
& ImplicitRegister
)
1882 /* Finalize opcode. First, we change the opcode based on the operand
1883 size given by i.suffix: We need not change things for byte insns. */
1885 if (!i
.suffix
&& (i
.tm
.opcode_modifier
& W
))
1887 as_bad (_("no instruction mnemonic suffix given and no register operands; can't size instruction"));
1891 /* For movzx and movsx, need to check the register type */
1893 && (i
.tm
.base_opcode
== 0xfb6 || i
.tm
.base_opcode
== 0xfbe))
1894 if (i
.suffix
&& i
.suffix
== BYTE_MNEM_SUFFIX
)
1896 unsigned int prefix
= DATA_PREFIX_OPCODE
;
1898 if ((i
.op
[1].regs
->reg_type
& Reg16
) != 0)
1899 if (!add_prefix (prefix
))
1903 if (i
.suffix
&& i
.suffix
!= BYTE_MNEM_SUFFIX
)
1905 /* It's not a byte, select word/dword operation. */
1906 if (i
.tm
.opcode_modifier
& W
)
1908 if (i
.tm
.opcode_modifier
& ShortForm
)
1909 i
.tm
.base_opcode
|= 8;
1911 i
.tm
.base_opcode
|= 1;
1913 /* Now select between word & dword operations via the operand
1914 size prefix, except for instructions that will ignore this
1916 if (((intel_syntax
&& (i
.suffix
== DWORD_MNEM_SUFFIX
))
1917 || i
.suffix
== LONG_MNEM_SUFFIX
) == flag_16bit_code
1918 && !(i
.tm
.opcode_modifier
& IgnoreSize
))
1920 unsigned int prefix
= DATA_PREFIX_OPCODE
;
1921 if (i
.tm
.opcode_modifier
& JumpByte
) /* jcxz, loop */
1922 prefix
= ADDR_PREFIX_OPCODE
;
1924 if (! add_prefix (prefix
))
1927 /* Size floating point instruction. */
1928 if (i
.suffix
== LONG_MNEM_SUFFIX
1929 || (intel_syntax
&& i
.suffix
== DWORD_MNEM_SUFFIX
))
1931 if (i
.tm
.opcode_modifier
& FloatMF
)
1932 i
.tm
.base_opcode
^= 4;
1936 if (i
.tm
.opcode_modifier
& ImmExt
)
1938 /* These AMD 3DNow! and Intel Katmai New Instructions have an
1939 opcode suffix which is coded in the same place as an 8-bit
1940 immediate field would be. Here we fake an 8-bit immediate
1941 operand from the opcode suffix stored in tm.extension_opcode. */
1945 assert (i
.imm_operands
== 0 && i
.operands
<= 2 && 2 < MAX_OPERANDS
);
1947 exp
= &im_expressions
[i
.imm_operands
++];
1948 i
.op
[i
.operands
].imms
= exp
;
1949 i
.types
[i
.operands
++] = Imm8
;
1950 exp
->X_op
= O_constant
;
1951 exp
->X_add_number
= i
.tm
.extension_opcode
;
1952 i
.tm
.extension_opcode
= None
;
1955 /* For insns with operands there are more diddles to do to the opcode. */
1958 /* Default segment register this instruction will use
1959 for memory accesses. 0 means unknown.
1960 This is only for optimizing out unnecessary segment overrides. */
1961 const seg_entry
*default_seg
= 0;
1963 /* The imul $imm, %reg instruction is converted into
1964 imul $imm, %reg, %reg, and the clr %reg instruction
1965 is converted into xor %reg, %reg. */
1966 if (i
.tm
.opcode_modifier
& regKludge
)
1968 unsigned int first_reg_op
= (i
.types
[0] & Reg
) ? 0 : 1;
1969 /* Pretend we saw the extra register operand. */
1970 assert (i
.op
[first_reg_op
+ 1].regs
== 0);
1971 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
1972 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
1976 if (i
.tm
.opcode_modifier
& ShortForm
)
1978 /* The register or float register operand is in operand 0 or 1. */
1979 unsigned int op
= (i
.types
[0] & (Reg
| FloatReg
)) ? 0 : 1;
1980 /* Register goes in low 3 bits of opcode. */
1981 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
1982 if (!quiet_warnings
&& (i
.tm
.opcode_modifier
& Ugh
) != 0)
1984 /* Warn about some common errors, but press on regardless.
1985 The first case can be generated by gcc (<= 2.8.1). */
1986 if (i
.operands
== 2)
1988 /* Reversed arguments on faddp, fsubp, etc. */
1989 as_warn (_("translating to `%s %%%s,%%%s'"), i
.tm
.name
,
1990 i
.op
[1].regs
->reg_name
,
1991 i
.op
[0].regs
->reg_name
);
1995 /* Extraneous `l' suffix on fp insn. */
1996 as_warn (_("translating to `%s %%%s'"), i
.tm
.name
,
1997 i
.op
[0].regs
->reg_name
);
2001 else if (i
.tm
.opcode_modifier
& Modrm
)
2003 /* The opcode is completed (modulo i.tm.extension_opcode which
2004 must be put into the modrm byte).
2005 Now, we make the modrm & index base bytes based on all the
2006 info we've collected. */
2008 /* i.reg_operands MUST be the number of real register operands;
2009 implicit registers do not count. */
2010 if (i
.reg_operands
== 2)
2012 unsigned int source
, dest
;
2013 source
= ((i
.types
[0]
2014 & (Reg
| RegMMX
| RegXMM
2016 | Control
| Debug
| Test
))
2021 /* One of the register operands will be encoded in the
2022 i.tm.reg field, the other in the combined i.tm.mode
2023 and i.tm.regmem fields. If no form of this
2024 instruction supports a memory destination operand,
2025 then we assume the source operand may sometimes be
2026 a memory operand and so we need to store the
2027 destination in the i.rm.reg field. */
2028 if ((i
.tm
.operand_types
[dest
] & AnyMem
) == 0)
2030 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
2031 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
2035 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
2036 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
2040 { /* If it's not 2 reg operands... */
2043 unsigned int fake_zero_displacement
= 0;
2044 unsigned int op
= ((i
.types
[0] & AnyMem
)
2046 : (i
.types
[1] & AnyMem
) ? 1 : 2);
2053 if (! i
.disp_operands
)
2054 fake_zero_displacement
= 1;
2057 /* Operand is just <disp> */
2058 if (flag_16bit_code
^ (i
.prefix
[ADDR_PREFIX
] != 0))
2060 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
2061 i
.types
[op
] &= ~Disp
;
2062 i
.types
[op
] |= Disp16
;
2066 i
.rm
.regmem
= NO_BASE_REGISTER
;
2067 i
.types
[op
] &= ~Disp
;
2068 i
.types
[op
] |= Disp32
;
2071 else /* ! i.base_reg && i.index_reg */
2073 i
.sib
.index
= i
.index_reg
->reg_num
;
2074 i
.sib
.base
= NO_BASE_REGISTER
;
2075 i
.sib
.scale
= i
.log2_scale_factor
;
2076 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
2077 i
.types
[op
] &= ~Disp
;
2078 i
.types
[op
] |= Disp32
; /* Must be 32 bit. */
2081 else if (i
.base_reg
->reg_type
& Reg16
)
2083 switch (i
.base_reg
->reg_num
)
2088 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
2089 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
2096 if ((i
.types
[op
] & Disp
) == 0)
2098 /* fake (%bp) into 0(%bp) */
2099 i
.types
[op
] |= Disp8
;
2100 fake_zero_displacement
= 1;
2103 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
2104 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
2106 default: /* (%si) -> 4 or (%di) -> 5 */
2107 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
2109 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
2111 else /* i.base_reg and 32 bit mode */
2113 i
.rm
.regmem
= i
.base_reg
->reg_num
;
2114 i
.sib
.base
= i
.base_reg
->reg_num
;
2115 if (i
.base_reg
->reg_num
== EBP_REG_NUM
)
2118 if (i
.disp_operands
== 0)
2120 fake_zero_displacement
= 1;
2121 i
.types
[op
] |= Disp8
;
2124 else if (i
.base_reg
->reg_num
== ESP_REG_NUM
)
2128 i
.sib
.scale
= i
.log2_scale_factor
;
2131 /* <disp>(%esp) becomes two byte modrm
2132 with no index register. We've already
2133 stored the code for esp in i.rm.regmem
2134 ie. ESCAPE_TO_TWO_BYTE_ADDRESSING. Any
2135 base register besides %esp will not use
2136 the extra modrm byte. */
2137 i
.sib
.index
= NO_INDEX_REGISTER
;
2138 #if ! SCALE1_WHEN_NO_INDEX
2139 /* Another case where we force the second
2141 if (i
.log2_scale_factor
)
2142 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
2147 i
.sib
.index
= i
.index_reg
->reg_num
;
2148 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
2150 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
2153 if (fake_zero_displacement
)
2155 /* Fakes a zero displacement assuming that i.types[op]
2156 holds the correct displacement size. */
2159 assert (i
.op
[op
].disps
== 0);
2160 exp
= &disp_expressions
[i
.disp_operands
++];
2161 i
.op
[op
].disps
= exp
;
2162 exp
->X_op
= O_constant
;
2163 exp
->X_add_number
= 0;
2164 exp
->X_add_symbol
= (symbolS
*) 0;
2165 exp
->X_op_symbol
= (symbolS
*) 0;
2169 /* Fill in i.rm.reg or i.rm.regmem field with register
2170 operand (if any) based on i.tm.extension_opcode.
2171 Again, we must be careful to make sure that
2172 segment/control/debug/test/MMX registers are coded
2173 into the i.rm.reg field. */
2178 & (Reg
| RegMMX
| RegXMM
2180 | Control
| Debug
| Test
))
2183 & (Reg
| RegMMX
| RegXMM
2185 | Control
| Debug
| Test
))
2188 /* If there is an extension opcode to put here, the
2189 register number must be put into the regmem field. */
2190 if (i
.tm
.extension_opcode
!= None
)
2191 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
2193 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
2195 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2
2196 we must set it to 3 to indicate this is a register
2197 operand in the regmem field. */
2198 if (!i
.mem_operands
)
2202 /* Fill in i.rm.reg field with extension opcode (if any). */
2203 if (i
.tm
.extension_opcode
!= None
)
2204 i
.rm
.reg
= i
.tm
.extension_opcode
;
2207 else if (i
.tm
.opcode_modifier
& (Seg2ShortForm
| Seg3ShortForm
))
2209 if (i
.tm
.base_opcode
== POP_SEG_SHORT
2210 && i
.op
[0].regs
->reg_num
== 1)
2212 as_bad (_("you can't `pop %%cs'"));
2215 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
2217 else if ((i
.tm
.base_opcode
& ~(D
|W
)) == MOV_AX_DISP32
)
2221 else if ((i
.tm
.opcode_modifier
& IsString
) != 0)
2223 /* For the string instructions that allow a segment override
2224 on one of their operands, the default segment is ds. */
2228 /* If a segment was explicitly specified,
2229 and the specified segment is not the default,
2230 use an opcode prefix to select it.
2231 If we never figured out what the default segment is,
2232 then default_seg will be zero at this point,
2233 and the specified segment prefix will always be used. */
2234 if ((i
.seg
[0]) && (i
.seg
[0] != default_seg
))
2236 if (! add_prefix (i
.seg
[0]->seg_prefix
))
2240 else if (!quiet_warnings
&& (i
.tm
.opcode_modifier
& Ugh
) != 0)
2242 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
2243 as_warn (_("translating to `%sp'"), i
.tm
.name
);
2247 /* Handle conversion of 'int $3' --> special int3 insn. */
2248 if (i
.tm
.base_opcode
== INT_OPCODE
&& i
.op
[0].imms
->X_add_number
== 3)
2250 i
.tm
.base_opcode
= INT3_OPCODE
;
2254 if ((i
.tm
.opcode_modifier
& (Jump
| JumpByte
| JumpDword
))
2255 && i
.op
[0].disps
->X_op
== O_constant
)
2257 /* Convert "jmp constant" (and "call constant") to a jump (call) to
2258 the absolute address given by the constant. Since ix86 jumps and
2259 calls are pc relative, we need to generate a reloc. */
2260 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
2261 i
.op
[0].disps
->X_op
= O_symbol
;
2264 /* We are ready to output the insn. */
2269 if (i
.tm
.opcode_modifier
& Jump
)
2276 if (flag_16bit_code
)
2280 if (i
.prefix
[DATA_PREFIX
])
2291 if (i
.prefixes
!= 0 && !intel_syntax
)
2292 as_warn (_("skipping prefixes on this instruction"));
2294 /* It's always a symbol; End frag & setup for relax.
2295 Make sure there is enough room in this frag for the largest
2296 instruction we may generate in md_convert_frag. This is 2
2297 bytes for the opcode and room for the prefix and largest
2299 frag_grow (prefix
+ 2 + size
);
2300 insn_size
+= prefix
+ 1;
2301 /* Prefix and 1 opcode byte go in fr_fix. */
2302 p
= frag_more (prefix
+ 1);
2304 *p
++ = DATA_PREFIX_OPCODE
;
2305 *p
= i
.tm
.base_opcode
;
2306 /* 1 possible extra opcode + displacement go in var part.
2307 Pass reloc in fr_var. */
2308 frag_var (rs_machine_dependent
,
2311 ((unsigned char) *p
== JUMP_PC_RELATIVE
2312 ? ENCODE_RELAX_STATE (UNCOND_JUMP
, SMALL
) | code16
2313 : ENCODE_RELAX_STATE (COND_JUMP
, SMALL
) | code16
),
2314 i
.op
[0].disps
->X_add_symbol
,
2315 i
.op
[0].disps
->X_add_number
,
2318 else if (i
.tm
.opcode_modifier
& (JumpByte
| JumpDword
))
2322 if (i
.tm
.opcode_modifier
& JumpByte
)
2324 /* This is a loop or jecxz type instruction. */
2326 if (i
.prefix
[ADDR_PREFIX
])
2329 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
2338 if (flag_16bit_code
)
2341 if (i
.prefix
[DATA_PREFIX
])
2344 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
2354 if (i
.prefixes
!= 0 && !intel_syntax
)
2355 as_warn (_("skipping prefixes on this instruction"));
2357 if (fits_in_unsigned_byte (i
.tm
.base_opcode
))
2359 insn_size
+= 1 + size
;
2360 p
= frag_more (1 + size
);
2364 /* Opcode can be at most two bytes. */
2365 insn_size
+= 2 + size
;
2366 p
= frag_more (2 + size
);
2367 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
2369 *p
++ = i
.tm
.base_opcode
& 0xff;
2371 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
2372 i
.op
[0].disps
, 1, reloc (size
, 1, i
.disp_reloc
[0]));
2374 else if (i
.tm
.opcode_modifier
& JumpInterSegment
)
2381 if (flag_16bit_code
)
2385 if (i
.prefix
[DATA_PREFIX
])
2396 if (i
.prefixes
!= 0 && !intel_syntax
)
2397 as_warn (_("skipping prefixes on this instruction"));
2399 /* 1 opcode; 2 segment; offset */
2400 insn_size
+= prefix
+ 1 + 2 + size
;
2401 p
= frag_more (prefix
+ 1 + 2 + size
);
2403 *p
++ = DATA_PREFIX_OPCODE
;
2404 *p
++ = i
.tm
.base_opcode
;
2405 if (i
.op
[1].imms
->X_op
== O_constant
)
2407 offsetT n
= i
.op
[1].imms
->X_add_number
;
2410 && !fits_in_unsigned_word (n
)
2411 && !fits_in_signed_word (n
))
2413 as_bad (_("16-bit jump out of range"));
2416 md_number_to_chars (p
, n
, size
);
2419 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
2420 i
.op
[1].imms
, 0, reloc (size
, 0, i
.disp_reloc
[0]));
2421 if (i
.op
[0].imms
->X_op
!= O_constant
)
2422 as_bad (_("can't handle non absolute segment in `%s'"),
2424 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
2428 /* Output normal instructions here. */
2431 /* The prefix bytes. */
2433 q
< i
.prefix
+ sizeof (i
.prefix
) / sizeof (i
.prefix
[0]);
2440 md_number_to_chars (p
, (valueT
) *q
, 1);
2444 /* Now the opcode; be careful about word order here! */
2445 if (fits_in_unsigned_byte (i
.tm
.base_opcode
))
2448 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
2450 else if (fits_in_unsigned_word (i
.tm
.base_opcode
))
2454 /* Put out high byte first: can't use md_number_to_chars! */
2455 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
2456 *p
= i
.tm
.base_opcode
& 0xff;
2459 { /* Opcode is either 3 or 4 bytes. */
2460 if (i
.tm
.base_opcode
& 0xff000000)
2464 *p
++ = (i
.tm
.base_opcode
>> 24) & 0xff;
2471 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
2472 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
2473 *p
= (i
.tm
.base_opcode
) & 0xff;
2476 /* Now the modrm byte and sib byte (if present). */
2477 if (i
.tm
.opcode_modifier
& Modrm
)
2481 md_number_to_chars (p
,
2482 (valueT
) (i
.rm
.regmem
<< 0
2486 /* If i.rm.regmem == ESP (4)
2487 && i.rm.mode != (Register mode)
2489 ==> need second modrm byte. */
2490 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
2492 && !(i
.base_reg
&& (i
.base_reg
->reg_type
& Reg16
) != 0))
2496 md_number_to_chars (p
,
2497 (valueT
) (i
.sib
.base
<< 0
2499 | i
.sib
.scale
<< 6),
2504 if (i
.disp_operands
)
2506 register unsigned int n
;
2508 for (n
= 0; n
< i
.operands
; n
++)
2510 if (i
.types
[n
] & Disp
)
2512 if (i
.op
[n
].disps
->X_op
== O_constant
)
2518 if (i
.types
[n
] & (Disp8
| Disp16
))
2521 if (i
.types
[n
] & Disp8
)
2524 val
= offset_in_range (i
.op
[n
].disps
->X_add_number
,
2527 p
= frag_more (size
);
2528 md_number_to_chars (p
, val
, size
);
2534 if (i
.types
[n
] & Disp16
)
2538 p
= frag_more (size
);
2539 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
2541 reloc (size
, 0, i
.disp_reloc
[n
]));
2545 } /* End displacement output. */
2547 /* Output immediate. */
2550 register unsigned int n
;
2552 for (n
= 0; n
< i
.operands
; n
++)
2554 if (i
.types
[n
] & Imm
)
2556 if (i
.op
[n
].imms
->X_op
== O_constant
)
2562 if (i
.types
[n
] & (Imm8
| Imm8S
| Imm16
))
2565 if (i
.types
[n
] & (Imm8
| Imm8S
))
2568 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
2571 p
= frag_more (size
);
2572 md_number_to_chars (p
, val
, size
);
2575 { /* Not absolute_section. */
2576 /* Need a 32-bit fixup (don't support 8bit
2577 non-absolute imms). Try to support other
2579 #ifdef BFD_ASSEMBLER
2580 enum bfd_reloc_code_real reloc_type
;
2586 if (i
.types
[n
] & Imm16
)
2588 else if (i
.types
[n
] & (Imm8
| Imm8S
))
2592 p
= frag_more (size
);
2593 reloc_type
= reloc (size
, 0, i
.disp_reloc
[0]);
2594 #ifdef BFD_ASSEMBLER
2595 if (reloc_type
== BFD_RELOC_32
2597 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
2598 && (i
.op
[n
].imms
->X_op
== O_symbol
2599 || (i
.op
[n
].imms
->X_op
== O_add
2600 && ((symbol_get_value_expression
2601 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
2604 reloc_type
= BFD_RELOC_386_GOTPC
;
2605 i
.op
[n
].imms
->X_add_number
+= 3;
2608 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
2609 i
.op
[n
].imms
, 0, reloc_type
);
2613 } /* end immediate output */
2621 #endif /* DEBUG386 */
2625 static int i386_immediate
PARAMS ((char *));
2628 i386_immediate (imm_start
)
2631 char *save_input_line_pointer
;
2635 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
2637 as_bad (_("only 1 or 2 immediate operands are allowed"));
2641 exp
= &im_expressions
[i
.imm_operands
++];
2642 i
.op
[this_operand
].imms
= exp
;
2644 if (is_space_char (*imm_start
))
2647 save_input_line_pointer
= input_line_pointer
;
2648 input_line_pointer
= imm_start
;
2652 /* We can have operands of the form
2653 <symbol>@GOTOFF+<nnn>
2654 Take the easy way out here and copy everything
2655 into a temporary buffer... */
2658 cp
= strchr (input_line_pointer
, '@');
2665 /* GOT relocations are not supported in 16 bit mode. */
2666 if (flag_16bit_code
)
2667 as_bad (_("GOT relocations not supported in 16 bit mode"));
2669 if (GOT_symbol
== NULL
)
2670 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
2672 if (strncmp (cp
+ 1, "PLT", 3) == 0)
2674 i
.disp_reloc
[this_operand
] = BFD_RELOC_386_PLT32
;
2677 else if (strncmp (cp
+ 1, "GOTOFF", 6) == 0)
2679 i
.disp_reloc
[this_operand
] = BFD_RELOC_386_GOTOFF
;
2682 else if (strncmp (cp
+ 1, "GOT", 3) == 0)
2684 i
.disp_reloc
[this_operand
] = BFD_RELOC_386_GOT32
;
2688 as_bad (_("bad reloc specifier in expression"));
2690 /* Replace the relocation token with ' ', so that errors like
2691 foo@GOTOFF1 will be detected. */
2692 first
= cp
- input_line_pointer
;
2693 tmpbuf
= (char *) alloca (strlen (input_line_pointer
));
2694 memcpy (tmpbuf
, input_line_pointer
, first
);
2695 tmpbuf
[first
] = ' ';
2696 strcpy (tmpbuf
+ first
+ 1, cp
+ 1 + len
);
2697 input_line_pointer
= tmpbuf
;
2702 exp_seg
= expression (exp
);
2705 if (*input_line_pointer
)
2706 as_bad (_("ignoring junk `%s' after expression"), input_line_pointer
);
2708 input_line_pointer
= save_input_line_pointer
;
2710 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_big
)
2712 /* Missing or bad expr becomes absolute 0. */
2713 as_bad (_("missing or invalid immediate expression `%s' taken as 0"),
2715 exp
->X_op
= O_constant
;
2716 exp
->X_add_number
= 0;
2717 exp
->X_add_symbol
= (symbolS
*) 0;
2718 exp
->X_op_symbol
= (symbolS
*) 0;
2721 if (exp
->X_op
== O_constant
)
2723 /* Size it properly later. */
2724 i
.types
[this_operand
] |= Imm32
;
2726 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
2728 #ifdef BFD_ASSEMBLER
2729 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
2731 && exp_seg
!= text_section
2732 && exp_seg
!= data_section
2733 && exp_seg
!= bss_section
2734 && exp_seg
!= undefined_section
2735 #ifdef BFD_ASSEMBLER
2736 && !bfd_is_com_section (exp_seg
)
2740 #ifdef BFD_ASSEMBLER
2741 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
2743 as_bad (_("unimplemented segment type %d in operand"), exp_seg
);
2750 /* This is an address. The size of the address will be
2751 determined later, depending on destination register,
2752 suffix, or the default for the section. We exclude
2753 Imm8S here so that `push $foo' and other instructions
2754 with an Imm8S form will use Imm16 or Imm32. */
2755 i
.types
[this_operand
] |= (Imm8
| Imm16
| Imm32
);
2761 static int i386_scale
PARAMS ((char *));
2767 if (!isdigit (*scale
))
2774 i
.log2_scale_factor
= 0;
2777 i
.log2_scale_factor
= 1;
2780 i
.log2_scale_factor
= 2;
2783 i
.log2_scale_factor
= 3;
2787 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
2791 if (i
.log2_scale_factor
!= 0 && ! i
.index_reg
)
2793 as_warn (_("scale factor of %d without an index register"),
2794 1 << i
.log2_scale_factor
);
2795 #if SCALE1_WHEN_NO_INDEX
2796 i
.log2_scale_factor
= 0;
2802 static int i386_displacement
PARAMS ((char *, char *));
2805 i386_displacement (disp_start
, disp_end
)
2809 register expressionS
*exp
;
2811 char *save_input_line_pointer
;
2812 int bigdisp
= Disp32
;
2814 if (flag_16bit_code
^ (i
.prefix
[ADDR_PREFIX
] != 0))
2816 i
.types
[this_operand
] |= bigdisp
;
2818 exp
= &disp_expressions
[i
.disp_operands
];
2819 i
.op
[this_operand
].disps
= exp
;
2821 save_input_line_pointer
= input_line_pointer
;
2822 input_line_pointer
= disp_start
;
2823 END_STRING_AND_SAVE (disp_end
);
2825 #ifndef GCC_ASM_O_HACK
2826 #define GCC_ASM_O_HACK 0
2829 END_STRING_AND_SAVE (disp_end
+ 1);
2830 if ((i
.types
[this_operand
] & BaseIndex
) != 0
2831 && displacement_string_end
[-1] == '+')
2833 /* This hack is to avoid a warning when using the "o"
2834 constraint within gcc asm statements.
2837 #define _set_tssldt_desc(n,addr,limit,type) \
2838 __asm__ __volatile__ ( \
2840 "movw %w1,2+%0\n\t" \
2842 "movb %b1,4+%0\n\t" \
2843 "movb %4,5+%0\n\t" \
2844 "movb $0,6+%0\n\t" \
2845 "movb %h1,7+%0\n\t" \
2847 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
2849 This works great except that the output assembler ends
2850 up looking a bit weird if it turns out that there is
2851 no offset. You end up producing code that looks like:
2864 So here we provide the missing zero. */
2866 *displacement_string_end
= '0';
2871 /* We can have operands of the form
2872 <symbol>@GOTOFF+<nnn>
2873 Take the easy way out here and copy everything
2874 into a temporary buffer... */
2877 cp
= strchr (input_line_pointer
, '@');
2884 /* GOT relocations are not supported in 16 bit mode. */
2885 if (flag_16bit_code
)
2886 as_bad (_("GOT relocations not supported in 16 bit mode"));
2888 if (GOT_symbol
== NULL
)
2889 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
2891 if (strncmp (cp
+ 1, "PLT", 3) == 0)
2893 i
.disp_reloc
[this_operand
] = BFD_RELOC_386_PLT32
;
2896 else if (strncmp (cp
+ 1, "GOTOFF", 6) == 0)
2898 i
.disp_reloc
[this_operand
] = BFD_RELOC_386_GOTOFF
;
2901 else if (strncmp (cp
+ 1, "GOT", 3) == 0)
2903 i
.disp_reloc
[this_operand
] = BFD_RELOC_386_GOT32
;
2907 as_bad (_("bad reloc specifier in expression"));
2909 /* Replace the relocation token with ' ', so that errors like
2910 foo@GOTOFF1 will be detected. */
2911 first
= cp
- input_line_pointer
;
2912 tmpbuf
= (char *) alloca (strlen (input_line_pointer
));
2913 memcpy (tmpbuf
, input_line_pointer
, first
);
2914 tmpbuf
[first
] = ' ';
2915 strcpy (tmpbuf
+ first
+ 1, cp
+ 1 + len
);
2916 input_line_pointer
= tmpbuf
;
2921 exp_seg
= expression (exp
);
2923 #ifdef BFD_ASSEMBLER
2924 /* We do this to make sure that the section symbol is in
2925 the symbol table. We will ultimately change the relocation
2926 to be relative to the beginning of the section. */
2927 if (i
.disp_reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
)
2929 if (S_IS_LOCAL(exp
->X_add_symbol
)
2930 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
)
2931 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
2932 assert (exp
->X_op
== O_symbol
);
2933 exp
->X_op
= O_subtract
;
2934 exp
->X_op_symbol
= GOT_symbol
;
2935 i
.disp_reloc
[this_operand
] = BFD_RELOC_32
;
2940 if (*input_line_pointer
)
2941 as_bad (_("ignoring junk `%s' after expression"),
2942 input_line_pointer
);
2944 RESTORE_END_STRING (disp_end
+ 1);
2946 RESTORE_END_STRING (disp_end
);
2947 input_line_pointer
= save_input_line_pointer
;
2949 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_big
)
2951 /* Missing or bad expr becomes absolute 0. */
2952 as_bad (_("missing or invalid displacement expression `%s' taken as 0"),
2954 exp
->X_op
= O_constant
;
2955 exp
->X_add_number
= 0;
2956 exp
->X_add_symbol
= (symbolS
*) 0;
2957 exp
->X_op_symbol
= (symbolS
*) 0;
2960 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
2961 if (exp
->X_op
!= O_constant
2962 #ifdef BFD_ASSEMBLER
2963 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
2965 && exp_seg
!= text_section
2966 && exp_seg
!= data_section
2967 && exp_seg
!= bss_section
2968 && exp_seg
!= undefined_section
)
2970 #ifdef BFD_ASSEMBLER
2971 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
2973 as_bad (_("unimplemented segment type %d in operand"), exp_seg
);
2981 static int i386_operand_modifier
PARAMS ((char **, int));
2984 i386_operand_modifier (op_string
, got_a_float
)
2988 if (!strncasecmp (*op_string
, "BYTE PTR", 8))
2990 i
.suffix
= BYTE_MNEM_SUFFIX
;
2995 else if (!strncasecmp (*op_string
, "WORD PTR", 8))
2997 if (got_a_float
== 2) /* "fi..." */
2998 i
.suffix
= SHORT_MNEM_SUFFIX
;
3000 i
.suffix
= WORD_MNEM_SUFFIX
;
3005 else if (!strncasecmp (*op_string
, "DWORD PTR", 9))
3007 if (got_a_float
== 1) /* "f..." */
3008 i
.suffix
= SHORT_MNEM_SUFFIX
;
3010 i
.suffix
= LONG_MNEM_SUFFIX
;
3015 else if (!strncasecmp (*op_string
, "QWORD PTR", 9))
3017 i
.suffix
= DWORD_MNEM_SUFFIX
;
3022 else if (!strncasecmp (*op_string
, "XWORD PTR", 9))
3024 i
.suffix
= LONG_DOUBLE_MNEM_SUFFIX
;
3029 else if (!strncasecmp (*op_string
, "SHORT", 5))
3035 else if (!strncasecmp (*op_string
, "OFFSET FLAT:", 12))
3041 else if (!strncasecmp (*op_string
, "FLAT", 4))
3047 else return NONE_FOUND
;
3050 static char * build_displacement_string
PARAMS ((int, char *));
3053 build_displacement_string (initial_disp
, op_string
)
3057 char *temp_string
= (char *) malloc (strlen (op_string
) + 1);
3058 char *end_of_operand_string
;
3062 temp_string
[0] = '\0';
3063 tc
= end_of_operand_string
= strchr (op_string
, '[');
3064 if (initial_disp
&& !end_of_operand_string
)
3066 strcpy (temp_string
, op_string
);
3070 /* Build the whole displacement string. */
3073 strncpy (temp_string
, op_string
, end_of_operand_string
- op_string
);
3074 temp_string
[end_of_operand_string
- op_string
] = '\0';
3078 temp_disp
= op_string
;
3080 while (*temp_disp
!= '\0')
3083 int add_minus
= (*temp_disp
== '-');
3085 if (*temp_disp
== '+' || *temp_disp
== '-' || *temp_disp
== '[')
3088 if (is_space_char (*temp_disp
))
3091 /* Don't consider registers. */
3092 if ( !((*temp_disp
== REGISTER_PREFIX
|| allow_naked_reg
)
3093 && parse_register (temp_disp
, &end_op
)) )
3095 char *string_start
= temp_disp
;
3097 while (*temp_disp
!= ']'
3098 && *temp_disp
!= '+'
3099 && *temp_disp
!= '-'
3100 && *temp_disp
!= '*')
3104 strcat (temp_string
, "-");
3106 strcat (temp_string
, "+");
3108 strncat (temp_string
, string_start
, temp_disp
- string_start
);
3109 if (*temp_disp
== '+' || *temp_disp
== '-')
3113 while (*temp_disp
!= '\0'
3114 && *temp_disp
!= '+'
3115 && *temp_disp
!= '-')
3122 static int i386_parse_seg
PARAMS ((char *));
3125 i386_parse_seg (op_string
)
3128 if (is_space_char (*op_string
))
3131 /* Should be one of es, cs, ss, ds fs or gs. */
3132 switch (*op_string
++)
3135 i
.seg
[i
.mem_operands
] = &es
;
3138 i
.seg
[i
.mem_operands
] = &cs
;
3141 i
.seg
[i
.mem_operands
] = &ss
;
3144 i
.seg
[i
.mem_operands
] = &ds
;
3147 i
.seg
[i
.mem_operands
] = &fs
;
3150 i
.seg
[i
.mem_operands
] = &gs
;
3153 as_bad (_("bad segment name `%s'"), op_string
);
3157 if (*op_string
++ != 's')
3159 as_bad (_("bad segment name `%s'"), op_string
);
3163 if (is_space_char (*op_string
))
3166 if (*op_string
!= ':')
3168 as_bad (_("bad segment name `%s'"), op_string
);
3176 static int i386_index_check
PARAMS((const char *));
3178 /* Make sure the memory operand we've been dealt is valid.
3179 Return 1 on success, 0 on a failure. */
3182 i386_index_check (operand_string
)
3183 const char *operand_string
;
3185 #if INFER_ADDR_PREFIX
3190 if (flag_16bit_code
^ (i
.prefix
[ADDR_PREFIX
] != 0)
3191 /* 16 bit mode checks. */
3193 && ((i
.base_reg
->reg_type
& (Reg16
|BaseIndex
))
3194 != (Reg16
|BaseIndex
)))
3196 && (((i
.index_reg
->reg_type
& (Reg16
|BaseIndex
))
3197 != (Reg16
|BaseIndex
))
3199 && i
.base_reg
->reg_num
< 6
3200 && i
.index_reg
->reg_num
>= 6
3201 && i
.log2_scale_factor
== 0))))
3202 /* 32 bit mode checks. */
3204 && (i
.base_reg
->reg_type
& Reg32
) == 0)
3206 && ((i
.index_reg
->reg_type
& (Reg32
|BaseIndex
))
3207 != (Reg32
|BaseIndex
)))))
3209 #if INFER_ADDR_PREFIX
3210 if (i
.prefix
[ADDR_PREFIX
] == 0 && stackop_size
!= '\0')
3212 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
3214 /* Change the size of any displacement too. At most one of
3215 Disp16 or Disp32 is set.
3216 FIXME. There doesn't seem to be any real need for separate
3217 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
3218 Removing them would probably clean up the code quite a lot. */
3219 if (i
.types
[this_operand
] & (Disp16
|Disp32
))
3220 i
.types
[this_operand
] ^= (Disp16
|Disp32
);
3225 as_bad (_("`%s' is not a valid base/index expression"),
3229 as_bad (_("`%s' is not a valid %s bit base/index expression"),
3231 flag_16bit_code
^ (i
.prefix
[ADDR_PREFIX
] != 0) ? "16" : "32");
3237 static int i386_intel_memory_operand
PARAMS ((char *));
3240 i386_intel_memory_operand (operand_string
)
3241 char *operand_string
;
3243 char *op_string
= operand_string
;
3244 char *end_of_operand_string
;
3246 if ((i
.mem_operands
== 1
3247 && (current_templates
->start
->opcode_modifier
& IsString
) == 0)
3248 || i
.mem_operands
== 2)
3250 as_bad (_("too many memory references for `%s'"),
3251 current_templates
->start
->name
);
3255 /* First check for a segment override. */
3256 if (*op_string
!= '[')
3260 end_seg
= strchr (op_string
, ':');
3263 if (!i386_parse_seg (op_string
))
3265 op_string
= end_seg
+ 1;
3269 /* Look for displacement preceding open bracket. */
3270 if (*op_string
!= '[')
3274 if (i
.disp_operands
)
3277 temp_string
= build_displacement_string (true, op_string
);
3279 if (!i386_displacement (temp_string
, temp_string
+ strlen (temp_string
)))
3286 end_of_operand_string
= strchr (op_string
, '[');
3287 if (!end_of_operand_string
)
3288 end_of_operand_string
= op_string
+ strlen (op_string
);
3290 if (is_space_char (*end_of_operand_string
))
3291 --end_of_operand_string
;
3293 op_string
= end_of_operand_string
;
3296 if (*op_string
== '[')
3300 /* Pick off each component and figure out where it belongs */
3302 end_of_operand_string
= op_string
;
3304 while (*op_string
!= ']')
3306 const reg_entry
*temp_reg
;
3310 while (*end_of_operand_string
!= '+'
3311 && *end_of_operand_string
!= '-'
3312 && *end_of_operand_string
!= '*'
3313 && *end_of_operand_string
!= ']')
3314 end_of_operand_string
++;
3316 temp_string
= op_string
;
3317 if (*temp_string
== '+')
3320 if (is_space_char (*temp_string
))
3324 if ((*temp_string
== REGISTER_PREFIX
|| allow_naked_reg
)
3325 && (temp_reg
= parse_register (temp_string
, &end_op
)) != NULL
)
3327 if (i
.base_reg
== NULL
)
3328 i
.base_reg
= temp_reg
;
3330 i
.index_reg
= temp_reg
;
3332 i
.types
[this_operand
] |= BaseIndex
;
3334 else if (*temp_string
== REGISTER_PREFIX
)
3336 as_bad (_("bad register name `%s'"), temp_string
);
3339 else if (is_digit_char (*op_string
)
3340 || *op_string
== '+' || *op_string
== '-')
3344 if (i
.disp_operands
!= 0)
3347 temp_string
= build_displacement_string (false, op_string
);
3349 temp_str
= temp_string
;
3350 if (*temp_str
== '+')
3353 if (!i386_displacement (temp_str
, temp_str
+ strlen (temp_str
)))
3361 end_of_operand_string
= op_string
;
3362 while (*end_of_operand_string
!= ']'
3363 && *end_of_operand_string
!= '+'
3364 && *end_of_operand_string
!= '-'
3365 && *end_of_operand_string
!= '*')
3366 ++end_of_operand_string
;
3368 else if (*op_string
== '*')
3372 if (i
.base_reg
&& !i
.index_reg
)
3374 i
.index_reg
= i
.base_reg
;
3378 if (!i386_scale (op_string
))
3381 op_string
= end_of_operand_string
;
3382 ++end_of_operand_string
;
3386 if (i386_index_check (operand_string
) == 0)
3394 i386_intel_operand (operand_string
, got_a_float
)
3395 char *operand_string
;
3400 char *op_string
= operand_string
;
3402 int operand_modifier
= i386_operand_modifier (&op_string
, got_a_float
);
3403 if (is_space_char (*op_string
))
3406 switch (operand_modifier
)
3413 if (!i386_intel_memory_operand (op_string
))
3419 if (!i386_immediate (op_string
))
3425 /* Should be register or immediate */
3426 if (is_digit_char (*op_string
)
3427 && strchr (op_string
, '[') == 0)
3429 if (!i386_immediate (op_string
))
3432 else if ((*op_string
== REGISTER_PREFIX
|| allow_naked_reg
)
3433 && (r
= parse_register (op_string
, &end_op
)) != NULL
)
3435 /* Check for a segment override by searching for ':' after a
3436 segment register. */
3438 if (is_space_char (*op_string
))
3440 if (*op_string
== ':' && (r
->reg_type
& (SReg2
| SReg3
)))
3445 i
.seg
[i
.mem_operands
] = &es
;
3448 i
.seg
[i
.mem_operands
] = &cs
;
3451 i
.seg
[i
.mem_operands
] = &ss
;
3454 i
.seg
[i
.mem_operands
] = &ds
;
3457 i
.seg
[i
.mem_operands
] = &fs
;
3460 i
.seg
[i
.mem_operands
] = &gs
;
3465 i
.types
[this_operand
] |= r
->reg_type
& ~BaseIndex
;
3466 i
.op
[this_operand
].regs
= r
;
3469 else if (*op_string
== REGISTER_PREFIX
)
3471 as_bad (_("bad register name `%s'"), op_string
);
3474 else if (!i386_intel_memory_operand (op_string
))
3483 /* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero
3487 i386_operand (operand_string
)
3488 char *operand_string
;
3492 char *op_string
= operand_string
;
3494 if (is_space_char (*op_string
))
3497 /* We check for an absolute prefix (differentiating,
3498 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
3499 if (*op_string
== ABSOLUTE_PREFIX
)
3502 if (is_space_char (*op_string
))
3504 i
.types
[this_operand
] |= JumpAbsolute
;
3507 /* Check if operand is a register. */
3508 if ((*op_string
== REGISTER_PREFIX
|| allow_naked_reg
)
3509 && (r
= parse_register (op_string
, &end_op
)) != NULL
)
3511 /* Check for a segment override by searching for ':' after a
3512 segment register. */
3514 if (is_space_char (*op_string
))
3516 if (*op_string
== ':' && (r
->reg_type
& (SReg2
| SReg3
)))
3521 i
.seg
[i
.mem_operands
] = &es
;
3524 i
.seg
[i
.mem_operands
] = &cs
;
3527 i
.seg
[i
.mem_operands
] = &ss
;
3530 i
.seg
[i
.mem_operands
] = &ds
;
3533 i
.seg
[i
.mem_operands
] = &fs
;
3536 i
.seg
[i
.mem_operands
] = &gs
;
3540 /* Skip the ':' and whitespace. */
3542 if (is_space_char (*op_string
))
3545 if (!is_digit_char (*op_string
)
3546 && !is_identifier_char (*op_string
)
3547 && *op_string
!= '('
3548 && *op_string
!= ABSOLUTE_PREFIX
)
3550 as_bad (_("bad memory operand `%s'"), op_string
);
3553 /* Handle case of %es:*foo. */
3554 if (*op_string
== ABSOLUTE_PREFIX
)
3557 if (is_space_char (*op_string
))
3559 i
.types
[this_operand
] |= JumpAbsolute
;
3561 goto do_memory_reference
;
3565 as_bad (_("junk `%s' after register"), op_string
);
3568 i
.types
[this_operand
] |= r
->reg_type
& ~BaseIndex
;
3569 i
.op
[this_operand
].regs
= r
;
3572 else if (*op_string
== REGISTER_PREFIX
)
3574 as_bad (_("bad register name `%s'"), op_string
);
3577 else if (*op_string
== IMMEDIATE_PREFIX
)
3578 { /* ... or an immediate */
3580 if (i
.types
[this_operand
] & JumpAbsolute
)
3582 as_bad (_("immediate operand illegal with absolute jump"));
3585 if (!i386_immediate (op_string
))
3588 else if (is_digit_char (*op_string
)
3589 || is_identifier_char (*op_string
)
3590 || *op_string
== '(' )
3592 /* This is a memory reference of some sort. */
3595 /* Start and end of displacement string expression (if found). */
3596 char *displacement_string_start
;
3597 char *displacement_string_end
;
3599 do_memory_reference
:
3600 if ((i
.mem_operands
== 1
3601 && (current_templates
->start
->opcode_modifier
& IsString
) == 0)
3602 || i
.mem_operands
== 2)
3604 as_bad (_("too many memory references for `%s'"),
3605 current_templates
->start
->name
);
3609 /* Check for base index form. We detect the base index form by
3610 looking for an ')' at the end of the operand, searching
3611 for the '(' matching it, and finding a REGISTER_PREFIX or ','
3613 base_string
= op_string
+ strlen (op_string
);
3616 if (is_space_char (*base_string
))
3619 /* If we only have a displacement, set-up for it to be parsed later. */
3620 displacement_string_start
= op_string
;
3621 displacement_string_end
= base_string
+ 1;
3623 if (*base_string
== ')')
3626 unsigned int parens_balanced
= 1;
3627 /* We've already checked that the number of left & right ()'s are
3628 equal, so this loop will not be infinite. */
3632 if (*base_string
== ')')
3634 if (*base_string
== '(')
3637 while (parens_balanced
);
3639 temp_string
= base_string
;
3641 /* Skip past '(' and whitespace. */
3643 if (is_space_char (*base_string
))
3646 if (*base_string
== ','
3647 || ((*base_string
== REGISTER_PREFIX
|| allow_naked_reg
)
3648 && (i
.base_reg
= parse_register (base_string
, &end_op
)) != NULL
))
3650 displacement_string_end
= temp_string
;
3652 i
.types
[this_operand
] |= BaseIndex
;
3656 base_string
= end_op
;
3657 if (is_space_char (*base_string
))
3661 /* There may be an index reg or scale factor here. */
3662 if (*base_string
== ',')
3665 if (is_space_char (*base_string
))
3668 if ((*base_string
== REGISTER_PREFIX
|| allow_naked_reg
)
3669 && (i
.index_reg
= parse_register (base_string
, &end_op
)) != NULL
)
3671 base_string
= end_op
;
3672 if (is_space_char (*base_string
))
3674 if (*base_string
== ',')
3677 if (is_space_char (*base_string
))
3680 else if (*base_string
!= ')' )
3682 as_bad (_("expecting `,' or `)' after index register in `%s'"),
3687 else if (*base_string
== REGISTER_PREFIX
)
3689 as_bad (_("bad register name `%s'"), base_string
);
3693 /* Check for scale factor. */
3694 if (isdigit ((unsigned char) *base_string
))
3696 if (!i386_scale (base_string
))
3700 if (is_space_char (*base_string
))
3702 if (*base_string
!= ')')
3704 as_bad (_("expecting `)' after scale factor in `%s'"),
3709 else if (!i
.index_reg
)
3711 as_bad (_("expecting index register or scale factor after `,'; got '%c'"),
3716 else if (*base_string
!= ')')
3718 as_bad (_("expecting `,' or `)' after base register in `%s'"),
3723 else if (*base_string
== REGISTER_PREFIX
)
3725 as_bad (_("bad register name `%s'"), base_string
);
3730 /* If there's an expression beginning the operand, parse it,
3731 assuming displacement_string_start and
3732 displacement_string_end are meaningful. */
3733 if (displacement_string_start
!= displacement_string_end
)
3735 if (!i386_displacement (displacement_string_start
,
3736 displacement_string_end
))
3740 /* Special case for (%dx) while doing input/output op. */
3742 && i
.base_reg
->reg_type
== (Reg16
| InOutPortReg
)
3744 && i
.log2_scale_factor
== 0
3745 && i
.seg
[i
.mem_operands
] == 0
3746 && (i
.types
[this_operand
] & Disp
) == 0)
3748 i
.types
[this_operand
] = InOutPortReg
;
3752 if (i386_index_check (operand_string
) == 0)
3757 { /* It's not a memory operand; argh! */
3758 as_bad (_("invalid char %s beginning operand %d `%s'"),
3759 output_invalid (*op_string
),
3764 return 1; /* Normal return. */
3767 /* md_estimate_size_before_relax()
3769 Called just before relax() for rs_machine_dependent frags. The x86
3770 assembler uses these frags to handle variable size jump
3773 Any symbol that is now undefined will not become defined.
3774 Return the correct fr_subtype in the frag.
3775 Return the initial "guess for variable size of frag" to caller.
3776 The guess is actually the growth beyond the fixed part. Whatever
3777 we do to grow the fixed or variable part contributes to our
3781 md_estimate_size_before_relax (fragP
, segment
)
3782 register fragS
*fragP
;
3783 register segT segment
;
3785 /* We've already got fragP->fr_subtype right; all we have to do is
3786 check for un-relaxable symbols. On an ELF system, we can't relax
3787 an externally visible symbol, because it may be overridden by a
3789 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
3790 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3791 || S_IS_EXTERNAL (fragP
->fr_symbol
)
3792 || S_IS_WEAK (fragP
->fr_symbol
)
3796 /* Symbol is undefined in this segment, or we need to keep a
3797 reloc so that weak symbols can be overridden. */
3798 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
3799 #ifdef BFD_ASSEMBLER
3800 enum bfd_reloc_code_real reloc_type
;
3804 unsigned char *opcode
;
3807 if (fragP
->fr_var
!= NO_RELOC
)
3808 reloc_type
= fragP
->fr_var
;
3810 reloc_type
= BFD_RELOC_16_PCREL
;
3812 reloc_type
= BFD_RELOC_32_PCREL
;
3814 old_fr_fix
= fragP
->fr_fix
;
3815 opcode
= (unsigned char *) fragP
->fr_opcode
;
3819 case JUMP_PC_RELATIVE
:
3820 /* Make jmp (0xeb) a dword displacement jump. */
3821 /* dword disp jmp */
3823 fragP
->fr_fix
+= size
;
3824 fix_new (fragP
, old_fr_fix
, size
,
3826 fragP
->fr_offset
, 1,
3831 /* This changes the byte-displacement jump 0x7N
3832 to the dword-displacement jump 0x0f,0x8N. */
3833 opcode
[1] = opcode
[0] + 0x10;
3834 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
3835 /* We've added an opcode byte. */
3836 fragP
->fr_fix
+= 1 + size
;
3837 fix_new (fragP
, old_fr_fix
+ 1, size
,
3839 fragP
->fr_offset
, 1,
3844 return fragP
->fr_fix
- old_fr_fix
;
3846 /* Guess a short jump. */
3850 /* Called after relax() is finished.
3852 In: Address of frag.
3853 fr_type == rs_machine_dependent.
3854 fr_subtype is what the address relaxed to.
3856 Out: Any fixSs and constants are set up.
3857 Caller will turn frag into a ".space 0". */
3859 #ifndef BFD_ASSEMBLER
3861 md_convert_frag (headers
, sec
, fragP
)
3862 object_headers
*headers ATTRIBUTE_UNUSED
;
3863 segT sec ATTRIBUTE_UNUSED
;
3864 register fragS
*fragP
;
3867 md_convert_frag (abfd
, sec
, fragP
)
3868 bfd
*abfd ATTRIBUTE_UNUSED
;
3869 segT sec ATTRIBUTE_UNUSED
;
3870 register fragS
*fragP
;
3873 register unsigned char *opcode
;
3874 unsigned char *where_to_put_displacement
= NULL
;
3875 offsetT target_address
;
3876 offsetT opcode_address
;
3877 unsigned int extension
= 0;
3878 offsetT displacement_from_opcode_start
;
3880 opcode
= (unsigned char *) fragP
->fr_opcode
;
3882 /* Address we want to reach in file space. */
3883 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
3884 #ifdef BFD_ASSEMBLER
3885 /* Not needed otherwise? */
3886 target_address
+= symbol_get_frag (fragP
->fr_symbol
)->fr_address
;
3889 /* Address opcode resides at in file space. */
3890 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
3892 /* Displacement from opcode start to fill into instruction. */
3893 displacement_from_opcode_start
= target_address
- opcode_address
;
3895 switch (fragP
->fr_subtype
)
3897 case ENCODE_RELAX_STATE (COND_JUMP
, SMALL
):
3898 case ENCODE_RELAX_STATE (COND_JUMP
, SMALL16
):
3899 case ENCODE_RELAX_STATE (UNCOND_JUMP
, SMALL
):
3900 case ENCODE_RELAX_STATE (UNCOND_JUMP
, SMALL16
):
3901 /* Don't have to change opcode. */
3902 extension
= 1; /* 1 opcode + 1 displacement */
3903 where_to_put_displacement
= &opcode
[1];
3906 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
3907 extension
= 5; /* 2 opcode + 4 displacement */
3908 opcode
[1] = opcode
[0] + 0x10;
3909 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
3910 where_to_put_displacement
= &opcode
[2];
3913 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
3914 extension
= 4; /* 1 opcode + 4 displacement */
3916 where_to_put_displacement
= &opcode
[1];
3919 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
3920 extension
= 3; /* 2 opcode + 2 displacement */
3921 opcode
[1] = opcode
[0] + 0x10;
3922 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
3923 where_to_put_displacement
= &opcode
[2];
3926 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
3927 extension
= 2; /* 1 opcode + 2 displacement */
3929 where_to_put_displacement
= &opcode
[1];
3933 BAD_CASE (fragP
->fr_subtype
);
3936 /* Now put displacement after opcode. */
3937 md_number_to_chars ((char *) where_to_put_displacement
,
3938 (valueT
) (displacement_from_opcode_start
- extension
),
3939 SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
3940 fragP
->fr_fix
+= extension
;
3943 /* Size of byte displacement jmp. */
3944 int md_short_jump_size
= 2;
3946 /* Size of dword displacement jmp. */
3947 int md_long_jump_size
= 5;
3949 /* Size of relocation record. */
3950 const int md_reloc_size
= 8;
3953 md_create_short_jump (ptr
, from_addr
, to_addr
, frag
, to_symbol
)
3955 addressT from_addr
, to_addr
;
3956 fragS
*frag ATTRIBUTE_UNUSED
;
3957 symbolS
*to_symbol ATTRIBUTE_UNUSED
;
3961 offset
= to_addr
- (from_addr
+ 2);
3962 /* Opcode for byte-disp jump. */
3963 md_number_to_chars (ptr
, (valueT
) 0xeb, 1);
3964 md_number_to_chars (ptr
+ 1, (valueT
) offset
, 1);
3968 md_create_long_jump (ptr
, from_addr
, to_addr
, frag
, to_symbol
)
3970 addressT from_addr
, to_addr
;
3971 fragS
*frag ATTRIBUTE_UNUSED
;
3972 symbolS
*to_symbol ATTRIBUTE_UNUSED
;
3976 offset
= to_addr
- (from_addr
+ 5);
3977 md_number_to_chars (ptr
, (valueT
) 0xe9, 1);
3978 md_number_to_chars (ptr
+ 1, (valueT
) offset
, 4);
3981 /* Apply a fixup (fixS) to segment data, once it has been determined
3982 by our caller that we have all the info we need to fix it up.
3984 On the 386, immediates, displacements, and data pointers are all in
3985 the same (little-endian) format, so we don't need to care about which
3989 md_apply_fix3 (fixP
, valp
, seg
)
3990 /* The fix we're to put in. */
3993 /* Pointer to the value of the bits. */
3996 /* Segment fix is from. */
3997 segT seg ATTRIBUTE_UNUSED
;
3999 register char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
4000 valueT value
= *valp
;
4002 #if defined (BFD_ASSEMBLER) && !defined (TE_Mach)
4005 switch (fixP
->fx_r_type
)
4011 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
4014 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
4017 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
4022 /* This is a hack. There should be a better way to handle this.
4023 This covers for the fact that bfd_install_relocation will
4024 subtract the current location (for partial_inplace, PC relative
4025 relocations); see more below. */
4026 if ((fixP
->fx_r_type
== BFD_RELOC_32_PCREL
4027 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
4028 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
4032 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
4034 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
4037 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
4039 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4040 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
4042 segT fseg
= S_GET_SEGMENT (fixP
->fx_addsy
);
4045 || (symbol_section_p (fixP
->fx_addsy
)
4046 && fseg
!= absolute_section
))
4047 && ! S_IS_EXTERNAL (fixP
->fx_addsy
)
4048 && ! S_IS_WEAK (fixP
->fx_addsy
)
4049 && S_IS_DEFINED (fixP
->fx_addsy
)
4050 && ! S_IS_COMMON (fixP
->fx_addsy
))
4052 /* Yes, we add the values in twice. This is because
4053 bfd_perform_relocation subtracts them out again. I think
4054 bfd_perform_relocation is broken, but I don't dare change
4056 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
4060 #if defined (OBJ_COFF) && defined (TE_PE)
4061 /* For some reason, the PE format does not store a section
4062 address offset for a PC relative symbol. */
4063 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
4064 value
+= md_pcrel_from (fixP
);
4068 /* Fix a few things - the dynamic linker expects certain values here,
4069 and we must not dissappoint it. */
4070 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4071 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
4073 switch (fixP
->fx_r_type
)
4075 case BFD_RELOC_386_PLT32
:
4076 /* Make the jump instruction point to the address of the operand. At
4077 runtime we merely add the offset to the actual PLT entry. */
4080 case BFD_RELOC_386_GOTPC
:
4082 /* This is tough to explain. We end up with this one if we have
4083 * operands that look like "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal
4084 * here is to obtain the absolute address of the GOT, and it is strongly
4085 * preferable from a performance point of view to avoid using a runtime
4086 * relocation for this. The actual sequence of instructions often look
4092 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
4094 * The call and pop essentially return the absolute address of
4095 * the label .L66 and store it in %ebx. The linker itself will
4096 * ultimately change the first operand of the addl so that %ebx points to
4097 * the GOT, but to keep things simple, the .o file must have this operand
4098 * set so that it generates not the absolute address of .L66, but the
4099 * absolute address of itself. This allows the linker itself simply
4100 * treat a GOTPC relocation as asking for a pcrel offset to the GOT to be
4101 * added in, and the addend of the relocation is stored in the operand
4102 * field for the instruction itself.
4104 * Our job here is to fix the operand so that it would add the correct
4105 * offset so that %ebx would point to itself. The thing that is tricky is
4106 * that .-.L66 will point to the beginning of the instruction, so we need
4107 * to further modify the operand so that it will point to itself.
4108 * There are other cases where you have something like:
4110 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
4112 * and here no correction would be required. Internally in the assembler
4113 * we treat operands of this form as not being pcrel since the '.' is
4114 * explicitly mentioned, and I wonder whether it would simplify matters
4115 * to do it this way. Who knows. In earlier versions of the PIC patches,
4116 * the pcrel_adjust field was used to store the correction, but since the
4117 * expression is not pcrel, I felt it would be confusing to do it this
4122 case BFD_RELOC_386_GOT32
:
4123 value
= 0; /* Fully resolved at runtime. No addend. */
4125 case BFD_RELOC_386_GOTOFF
:
4128 case BFD_RELOC_VTABLE_INHERIT
:
4129 case BFD_RELOC_VTABLE_ENTRY
:
4136 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
4138 #endif /* defined (BFD_ASSEMBLER) && !defined (TE_Mach) */
4139 md_number_to_chars (p
, value
, fixP
->fx_size
);
4144 #define MAX_LITTLENUMS 6
4146 /* Turn the string pointed to by litP into a floating point constant
4147 of type TYPE, and emit the appropriate bytes. The number of
4148 LITTLENUMS emitted is stored in *SIZEP. An error message is
4149 returned, or NULL on OK. */
4152 md_atof (type
, litP
, sizeP
)
4158 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4159 LITTLENUM_TYPE
*wordP
;
4181 return _("Bad call to md_atof ()");
4183 t
= atof_ieee (input_line_pointer
, type
, words
);
4185 input_line_pointer
= t
;
4187 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
4188 /* This loops outputs the LITTLENUMs in REVERSE order; in accord with
4189 the bigendian 386. */
4190 for (wordP
= words
+ prec
- 1; prec
--;)
4192 md_number_to_chars (litP
, (valueT
) (*wordP
--), sizeof (LITTLENUM_TYPE
));
4193 litP
+= sizeof (LITTLENUM_TYPE
);
4198 char output_invalid_buf
[8];
4205 sprintf (output_invalid_buf
, "'%c'", c
);
4207 sprintf (output_invalid_buf
, "(0x%x)", (unsigned) c
);
4208 return output_invalid_buf
;
4211 /* REG_STRING starts *before* REGISTER_PREFIX. */
4213 static const reg_entry
*
4214 parse_register (reg_string
, end_op
)
4218 char *s
= reg_string
;
4220 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
4223 /* Skip possible REGISTER_PREFIX and possible whitespace. */
4224 if (*s
== REGISTER_PREFIX
)
4227 if (is_space_char (*s
))
4231 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
4233 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
4234 return (const reg_entry
*) NULL
;
4240 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
4242 /* Handle floating point regs, allowing spaces in the (i) part. */
4243 if (r
== i386_regtab
/* %st is first entry of table */)
4245 if (is_space_char (*s
))
4250 if (is_space_char (*s
))
4252 if (*s
>= '0' && *s
<= '7')
4254 r
= &i386_float_regtab
[*s
- '0'];
4256 if (is_space_char (*s
))
4264 /* We have "%st(" then garbage. */
4265 return (const reg_entry
*) NULL
;
4272 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4273 const char *md_shortopts
= "kVQ:sq";
4275 const char *md_shortopts
= "q";
4277 struct option md_longopts
[] = {
4278 {NULL
, no_argument
, NULL
, 0}
4280 size_t md_longopts_size
= sizeof (md_longopts
);
4283 md_parse_option (c
, arg
)
4285 char *arg ATTRIBUTE_UNUSED
;
4293 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4294 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
4295 should be emitted or not. FIXME: Not implemented. */
4299 /* -V: SVR4 argument to print version ID. */
4301 print_version_id ();
4304 /* -k: Ignore for FreeBSD compatibility. */
4309 /* -s: On i386 Solaris, this tells the native assembler to use
4310 .stab instead of .stab.excl. We always use .stab anyhow. */
4321 md_show_usage (stream
)
4324 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4325 fprintf (stream
, _("\
4327 -V print assembler version number\n\
4329 -q quieten some warnings\n\
4332 fprintf (stream
, _("\
4333 -q quieten some warnings\n"));
4337 #ifdef BFD_ASSEMBLER
4338 #if ((defined (OBJ_MAYBE_ELF) && defined (OBJ_MAYBE_COFF)) \
4339 || (defined (OBJ_MAYBE_ELF) && defined (OBJ_MAYBE_AOUT)) \
4340 || (defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)))
4342 /* Pick the target format to use. */
4345 i386_target_format ()
4347 switch (OUTPUT_FLAVOR
)
4349 #ifdef OBJ_MAYBE_AOUT
4350 case bfd_target_aout_flavour
:
4351 return AOUT_TARGET_FORMAT
;
4353 #ifdef OBJ_MAYBE_COFF
4354 case bfd_target_coff_flavour
:
4357 #ifdef OBJ_MAYBE_ELF
4358 case bfd_target_elf_flavour
:
4359 return "elf32-i386";
4367 #endif /* OBJ_MAYBE_ more than one */
4368 #endif /* BFD_ASSEMBLER */
4371 md_undefined_symbol (name
)
4374 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
4375 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
4376 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
4377 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
4381 if (symbol_find (name
))
4382 as_bad (_("GOT already in symbol table"));
4383 GOT_symbol
= symbol_new (name
, undefined_section
,
4384 (valueT
) 0, &zero_address_frag
);
4391 /* Round up a section size to the appropriate boundary. */
4394 md_section_align (segment
, size
)
4395 segT segment ATTRIBUTE_UNUSED
;
4398 #ifdef BFD_ASSEMBLER
4399 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
4400 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
4402 /* For a.out, force the section size to be aligned. If we don't do
4403 this, BFD will align it for us, but it will not write out the
4404 final bytes of the section. This may be a bug in BFD, but it is
4405 easier to fix it here since that is how the other a.out targets
4409 align
= bfd_get_section_alignment (stdoutput
, segment
);
4410 size
= ((size
+ (1 << align
) - 1) & ((valueT
) -1 << align
));
4418 /* On the i386, PC-relative offsets are relative to the start of the
4419 next instruction. That is, the address of the offset, plus its
4420 size, since the offset is always the last part of the insn. */
4423 md_pcrel_from (fixP
)
4426 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
4433 int ignore ATTRIBUTE_UNUSED
;
4437 temp
= get_absolute_expression ();
4438 subseg_set (bss_section
, (subsegT
) temp
);
4439 demand_empty_rest_of_line ();
4444 #ifdef BFD_ASSEMBLER
4447 i386_validate_fix (fixp
)
4450 if (fixp
->fx_subsy
&& fixp
->fx_subsy
== GOT_symbol
)
4452 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
4458 tc_gen_reloc (section
, fixp
)
4459 asection
*section ATTRIBUTE_UNUSED
;
4463 bfd_reloc_code_real_type code
;
4465 switch (fixp
->fx_r_type
)
4467 case BFD_RELOC_386_PLT32
:
4468 case BFD_RELOC_386_GOT32
:
4469 case BFD_RELOC_386_GOTOFF
:
4470 case BFD_RELOC_386_GOTPC
:
4472 case BFD_RELOC_VTABLE_ENTRY
:
4473 case BFD_RELOC_VTABLE_INHERIT
:
4474 code
= fixp
->fx_r_type
;
4479 switch (fixp
->fx_size
)
4482 as_bad (_("can not do %d byte pc-relative relocation"),
4484 code
= BFD_RELOC_32_PCREL
;
4486 case 1: code
= BFD_RELOC_8_PCREL
; break;
4487 case 2: code
= BFD_RELOC_16_PCREL
; break;
4488 case 4: code
= BFD_RELOC_32_PCREL
; break;
4493 switch (fixp
->fx_size
)
4496 as_bad (_("can not do %d byte relocation"), fixp
->fx_size
);
4497 code
= BFD_RELOC_32
;
4499 case 1: code
= BFD_RELOC_8
; break;
4500 case 2: code
= BFD_RELOC_16
; break;
4501 case 4: code
= BFD_RELOC_32
; break;
4507 if (code
== BFD_RELOC_32
4509 && fixp
->fx_addsy
== GOT_symbol
)
4510 code
= BFD_RELOC_386_GOTPC
;
4512 rel
= (arelent
*) xmalloc (sizeof (arelent
));
4513 rel
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
4514 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
4516 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
4517 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
4518 vtable entry to be used in the relocation's section offset. */
4519 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
4520 rel
->address
= fixp
->fx_offset
;
4523 rel
->addend
= fixp
->fx_addnumber
;
4527 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
4528 if (rel
->howto
== NULL
)
4530 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
4531 _("cannot represent relocation type %s"),
4532 bfd_get_reloc_code_name (code
));
4533 /* Set howto to a garbage value so that we can keep going. */
4534 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
4535 assert (rel
->howto
!= NULL
);
4541 #else /* ! BFD_ASSEMBLER */
4543 #if (defined(OBJ_AOUT) | defined(OBJ_BOUT))
4545 tc_aout_fix_to_chars (where
, fixP
, segment_address_in_file
)
4548 relax_addressT segment_address_in_file
;
4550 /* In: length of relocation (or of address) in chars: 1, 2 or 4.
4551 Out: GNU LD relocation length code: 0, 1, or 2. */
4553 static const unsigned char nbytes_r_length
[] = { 42, 0, 1, 42, 2 };
4556 know (fixP
->fx_addsy
!= NULL
);
4558 md_number_to_chars (where
,
4559 (valueT
) (fixP
->fx_frag
->fr_address
4560 + fixP
->fx_where
- segment_address_in_file
),
4563 r_symbolnum
= (S_IS_DEFINED (fixP
->fx_addsy
)
4564 ? S_GET_TYPE (fixP
->fx_addsy
)
4565 : fixP
->fx_addsy
->sy_number
);
4567 where
[6] = (r_symbolnum
>> 16) & 0x0ff;
4568 where
[5] = (r_symbolnum
>> 8) & 0x0ff;
4569 where
[4] = r_symbolnum
& 0x0ff;
4570 where
[7] = ((((!S_IS_DEFINED (fixP
->fx_addsy
)) << 3) & 0x08)
4571 | ((nbytes_r_length
[fixP
->fx_size
] << 1) & 0x06)
4572 | (((fixP
->fx_pcrel
<< 0) & 0x01) & 0x0f));
4575 #endif /* OBJ_AOUT or OBJ_BOUT. */
4577 #if defined (I386COFF)
4580 tc_coff_fix2rtype (fixP
)
4583 if (fixP
->fx_r_type
== R_IMAGEBASE
)
4586 return (fixP
->fx_pcrel
?
4587 (fixP
->fx_size
== 1 ? R_PCRBYTE
:
4588 fixP
->fx_size
== 2 ? R_PCRWORD
:
4590 (fixP
->fx_size
== 1 ? R_RELBYTE
:
4591 fixP
->fx_size
== 2 ? R_RELWORD
:
4596 tc_coff_sizemachdep (frag
)
4600 return (frag
->fr_next
->fr_address
- frag
->fr_address
);
4605 #endif /* I386COFF */
4607 #endif /* ! BFD_ASSEMBLER */