1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
4 Free Software Foundation, Inc.
6 This file is part of GAS, the GNU Assembler.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
23 /* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
25 x86_64 support by Jan Hubicka (jh@suse.cz)
26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
27 Bugs & suggestions are completely welcome. This is free software.
28 Please help us make it better. */
31 #include "safe-ctype.h"
33 #include "dwarf2dbg.h"
34 #include "dw2gencfi.h"
35 #include "elf/x86-64.h"
36 #include "opcodes/i386-init.h"
38 #ifndef REGISTER_WARNINGS
39 #define REGISTER_WARNINGS 1
42 #ifndef INFER_ADDR_PREFIX
43 #define INFER_ADDR_PREFIX 1
47 #define DEFAULT_ARCH "i386"
52 #define INLINE __inline__
58 /* Prefixes will be emitted in the order defined below.
59 WAIT_PREFIX must be the first prefix since FWAIT is really is an
60 instruction, and so must come before any prefixes.
61 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
67 #define LOCKREP_PREFIX 4
68 #define REX_PREFIX 5 /* must come last. */
69 #define MAX_PREFIXES 6 /* max prefixes per opcode */
71 /* we define the syntax here (modulo base,index,scale syntax) */
72 #define REGISTER_PREFIX '%'
73 #define IMMEDIATE_PREFIX '$'
74 #define ABSOLUTE_PREFIX '*'
76 /* these are the instruction mnemonic suffixes in AT&T syntax or
77 memory operand size in Intel syntax. */
78 #define WORD_MNEM_SUFFIX 'w'
79 #define BYTE_MNEM_SUFFIX 'b'
80 #define SHORT_MNEM_SUFFIX 's'
81 #define LONG_MNEM_SUFFIX 'l'
82 #define QWORD_MNEM_SUFFIX 'q'
83 #define XMMWORD_MNEM_SUFFIX 'x'
84 #define YMMWORD_MNEM_SUFFIX 'y'
85 /* Intel Syntax. Use a non-ascii letter since since it never appears
87 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
89 #define END_OF_INSN '\0'
92 'templates' is for grouping together 'template' structures for opcodes
93 of the same name. This is only used for storing the insns in the grand
94 ole hash table of insns.
95 The templates themselves start at START and range up to (but not including)
100 const insn_template
*start
;
101 const insn_template
*end
;
105 /* 386 operand encoding bytes: see 386 book for details of this. */
108 unsigned int regmem
; /* codes register or memory operand */
109 unsigned int reg
; /* codes register operand (or extended opcode) */
110 unsigned int mode
; /* how to interpret regmem & reg */
114 /* x86-64 extension prefix. */
115 typedef int rex_byte
;
117 /* 386 opcode byte to code indirect addressing. */
126 /* x86 arch names, types and features */
129 const char *name
; /* arch name */
130 enum processor_type type
; /* arch type */
131 i386_cpu_flags flags
; /* cpu feature flags */
135 static void set_code_flag (int);
136 static void set_16bit_gcc_code_flag (int);
137 static void set_intel_syntax (int);
138 static void set_intel_mnemonic (int);
139 static void set_allow_index_reg (int);
140 static void set_sse_check (int);
141 static void set_cpu_arch (int);
143 static void pe_directive_secrel (int);
145 static void signed_cons (int);
146 static char *output_invalid (int c
);
147 static int i386_finalize_immediate (segT
, expressionS
*, i386_operand_type
,
149 static int i386_finalize_displacement (segT
, expressionS
*, i386_operand_type
,
151 static int i386_att_operand (char *);
152 static int i386_intel_operand (char *, int);
153 static int i386_intel_simplify (expressionS
*);
154 static int i386_intel_parse_name (const char *, expressionS
*);
155 static const reg_entry
*parse_register (char *, char **);
156 static char *parse_insn (char *, char *);
157 static char *parse_operands (char *, const char *);
158 static void swap_operands (void);
159 static void swap_2_operands (int, int);
160 static void optimize_imm (void);
161 static void optimize_disp (void);
162 static const insn_template
*match_template (void);
163 static int check_string (void);
164 static int process_suffix (void);
165 static int check_byte_reg (void);
166 static int check_long_reg (void);
167 static int check_qword_reg (void);
168 static int check_word_reg (void);
169 static int finalize_imm (void);
170 static int process_operands (void);
171 static const seg_entry
*build_modrm_byte (void);
172 static void output_insn (void);
173 static void output_imm (fragS
*, offsetT
);
174 static void output_disp (fragS
*, offsetT
);
176 static void s_bss (int);
178 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
179 static void handle_large_common (int small ATTRIBUTE_UNUSED
);
182 static const char *default_arch
= DEFAULT_ARCH
;
187 /* VEX prefix is either 2 byte or 3 byte. */
188 unsigned char bytes
[3];
190 /* Destination or source register specifier. */
191 const reg_entry
*register_specifier
;
194 /* 'md_assemble ()' gathers together information and puts it into a
201 const reg_entry
*regs
;
206 /* TM holds the template for the insn were currently assembling. */
209 /* SUFFIX holds the instruction size suffix for byte, word, dword
210 or qword, if given. */
213 /* OPERANDS gives the number of given operands. */
214 unsigned int operands
;
216 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
217 of given register, displacement, memory operands and immediate
219 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
221 /* TYPES [i] is the type (see above #defines) which tells us how to
222 use OP[i] for the corresponding operand. */
223 i386_operand_type types
[MAX_OPERANDS
];
225 /* Displacement expression, immediate expression, or register for each
227 union i386_op op
[MAX_OPERANDS
];
229 /* Flags for operands. */
230 unsigned int flags
[MAX_OPERANDS
];
231 #define Operand_PCrel 1
233 /* Relocation type for operand */
234 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
236 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
237 the base index byte below. */
238 const reg_entry
*base_reg
;
239 const reg_entry
*index_reg
;
240 unsigned int log2_scale_factor
;
242 /* SEG gives the seg_entries of this insn. They are zero unless
243 explicit segment overrides are given. */
244 const seg_entry
*seg
[2];
246 /* PREFIX holds all the given prefix opcodes (usually null).
247 PREFIXES is the number of prefix opcodes. */
248 unsigned int prefixes
;
249 unsigned char prefix
[MAX_PREFIXES
];
251 /* RM and SIB are the modrm byte and the sib byte where the
252 addressing modes of this insn are encoded. */
258 /* Swap operand in encoding. */
259 unsigned int swap_operand
: 1;
262 typedef struct _i386_insn i386_insn
;
264 /* List of chars besides those in app.c:symbol_chars that can start an
265 operand. Used to prevent the scrubber eating vital white-space. */
266 const char extra_symbol_chars
[] = "*%-(["
275 #if (defined (TE_I386AIX) \
276 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
277 && !defined (TE_GNU) \
278 && !defined (TE_LINUX) \
279 && !defined (TE_NETWARE) \
280 && !defined (TE_FreeBSD) \
281 && !defined (TE_NetBSD)))
282 /* This array holds the chars that always start a comment. If the
283 pre-processor is disabled, these aren't very useful. The option
284 --divide will remove '/' from this list. */
285 const char *i386_comment_chars
= "#/";
286 #define SVR4_COMMENT_CHARS 1
287 #define PREFIX_SEPARATOR '\\'
290 const char *i386_comment_chars
= "#";
291 #define PREFIX_SEPARATOR '/'
294 /* This array holds the chars that only start a comment at the beginning of
295 a line. If the line seems to have the form '# 123 filename'
296 .line and .file directives will appear in the pre-processed output.
297 Note that input_file.c hand checks for '#' at the beginning of the
298 first line of the input file. This is because the compiler outputs
299 #NO_APP at the beginning of its output.
300 Also note that comments started like this one will always work if
301 '/' isn't otherwise defined. */
302 const char line_comment_chars
[] = "#/";
304 const char line_separator_chars
[] = ";";
306 /* Chars that can be used to separate mant from exp in floating point
308 const char EXP_CHARS
[] = "eE";
310 /* Chars that mean this number is a floating point constant
313 const char FLT_CHARS
[] = "fFdDxX";
315 /* Tables for lexical analysis. */
316 static char mnemonic_chars
[256];
317 static char register_chars
[256];
318 static char operand_chars
[256];
319 static char identifier_chars
[256];
320 static char digit_chars
[256];
322 /* Lexical macros. */
323 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
324 #define is_operand_char(x) (operand_chars[(unsigned char) x])
325 #define is_register_char(x) (register_chars[(unsigned char) x])
326 #define is_space_char(x) ((x) == ' ')
327 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
328 #define is_digit_char(x) (digit_chars[(unsigned char) x])
330 /* All non-digit non-letter characters that may occur in an operand. */
331 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
333 /* md_assemble() always leaves the strings it's passed unaltered. To
334 effect this we maintain a stack of saved characters that we've smashed
335 with '\0's (indicating end of strings for various sub-fields of the
336 assembler instruction). */
337 static char save_stack
[32];
338 static char *save_stack_p
;
339 #define END_STRING_AND_SAVE(s) \
340 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
341 #define RESTORE_END_STRING(s) \
342 do { *(s) = *--save_stack_p; } while (0)
344 /* The instruction we're assembling. */
347 /* Possible templates for current insn. */
348 static const templates
*current_templates
;
350 /* Per instruction expressionS buffers: max displacements & immediates. */
351 static expressionS disp_expressions
[MAX_MEMORY_OPERANDS
];
352 static expressionS im_expressions
[MAX_IMMEDIATE_OPERANDS
];
354 /* Current operand we are working on. */
355 static int this_operand
= -1;
357 /* We support four different modes. FLAG_CODE variable is used to distinguish
365 static enum flag_code flag_code
;
366 static unsigned int object_64bit
;
367 static int use_rela_relocations
= 0;
369 /* The names used to print error messages. */
370 static const char *flag_code_names
[] =
377 /* 1 for intel syntax,
379 static int intel_syntax
= 0;
381 /* 1 for intel mnemonic,
382 0 if att mnemonic. */
383 static int intel_mnemonic
= !SYSV386_COMPAT
;
385 /* 1 if support old (<= 2.8.1) versions of gcc. */
386 static int old_gcc
= OLDGCC_COMPAT
;
388 /* 1 if pseudo registers are permitted. */
389 static int allow_pseudo_reg
= 0;
391 /* 1 if register prefix % not required. */
392 static int allow_naked_reg
= 0;
394 /* 1 if pseudo index register, eiz/riz, is allowed . */
395 static int allow_index_reg
= 0;
405 /* Register prefix used for error message. */
406 static const char *register_prefix
= "%";
408 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
409 leave, push, and pop instructions so that gcc has the same stack
410 frame as in 32 bit mode. */
411 static char stackop_size
= '\0';
413 /* Non-zero to optimize code alignment. */
414 int optimize_align_code
= 1;
416 /* Non-zero to quieten some warnings. */
417 static int quiet_warnings
= 0;
420 static const char *cpu_arch_name
= NULL
;
421 static char *cpu_sub_arch_name
= NULL
;
423 /* CPU feature flags. */
424 static i386_cpu_flags cpu_arch_flags
= CPU_UNKNOWN_FLAGS
;
426 /* If we have selected a cpu we are generating instructions for. */
427 static int cpu_arch_tune_set
= 0;
429 /* Cpu we are generating instructions for. */
430 enum processor_type cpu_arch_tune
= PROCESSOR_UNKNOWN
;
432 /* CPU feature flags of cpu we are generating instructions for. */
433 static i386_cpu_flags cpu_arch_tune_flags
;
435 /* CPU instruction set architecture used. */
436 enum processor_type cpu_arch_isa
= PROCESSOR_UNKNOWN
;
438 /* CPU feature flags of instruction set architecture used. */
439 i386_cpu_flags cpu_arch_isa_flags
;
441 /* If set, conditional jumps are not automatically promoted to handle
442 larger than a byte offset. */
443 static unsigned int no_cond_jump_promotion
= 0;
445 /* Encode SSE instructions with VEX prefix. */
446 static unsigned int sse2avx
;
448 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
449 static symbolS
*GOT_symbol
;
451 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
452 unsigned int x86_dwarf2_return_column
;
454 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
455 int x86_cie_data_alignment
;
457 /* Interface to relax_segment.
458 There are 3 major relax states for 386 jump insns because the
459 different types of jumps add different sizes to frags when we're
460 figuring out what sort of jump to choose to reach a given label. */
463 #define UNCOND_JUMP 0
465 #define COND_JUMP86 2
470 #define SMALL16 (SMALL | CODE16)
472 #define BIG16 (BIG | CODE16)
476 #define INLINE __inline__
482 #define ENCODE_RELAX_STATE(type, size) \
483 ((relax_substateT) (((type) << 2) | (size)))
484 #define TYPE_FROM_RELAX_STATE(s) \
486 #define DISP_SIZE_FROM_RELAX_STATE(s) \
487 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
489 /* This table is used by relax_frag to promote short jumps to long
490 ones where necessary. SMALL (short) jumps may be promoted to BIG
491 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
492 don't allow a short jump in a 32 bit code segment to be promoted to
493 a 16 bit offset jump because it's slower (requires data size
494 prefix), and doesn't work, unless the destination is in the bottom
495 64k of the code segment (The top 16 bits of eip are zeroed). */
497 const relax_typeS md_relax_table
[] =
500 1) most positive reach of this state,
501 2) most negative reach of this state,
502 3) how many bytes this mode will have in the variable part of the frag
503 4) which index into the table to try if we can't fit into this one. */
505 /* UNCOND_JUMP states. */
506 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
507 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
508 /* dword jmp adds 4 bytes to frag:
509 0 extra opcode bytes, 4 displacement bytes. */
511 /* word jmp adds 2 byte2 to frag:
512 0 extra opcode bytes, 2 displacement bytes. */
515 /* COND_JUMP states. */
516 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
517 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
518 /* dword conditionals adds 5 bytes to frag:
519 1 extra opcode byte, 4 displacement bytes. */
521 /* word conditionals add 3 bytes to frag:
522 1 extra opcode byte, 2 displacement bytes. */
525 /* COND_JUMP86 states. */
526 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
527 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
528 /* dword conditionals adds 5 bytes to frag:
529 1 extra opcode byte, 4 displacement bytes. */
531 /* word conditionals add 4 bytes to frag:
532 1 displacement byte and a 3 byte long branch insn. */
536 static const arch_entry cpu_arch
[] =
538 { "generic32", PROCESSOR_GENERIC32
,
539 CPU_GENERIC32_FLAGS
},
540 { "generic64", PROCESSOR_GENERIC64
,
541 CPU_GENERIC64_FLAGS
},
542 { "i8086", PROCESSOR_UNKNOWN
,
544 { "i186", PROCESSOR_UNKNOWN
,
546 { "i286", PROCESSOR_UNKNOWN
,
548 { "i386", PROCESSOR_I386
,
550 { "i486", PROCESSOR_I486
,
552 { "i586", PROCESSOR_PENTIUM
,
554 { "i686", PROCESSOR_PENTIUMPRO
,
556 { "pentium", PROCESSOR_PENTIUM
,
558 { "pentiumpro", PROCESSOR_PENTIUMPRO
,
560 { "pentiumii", PROCESSOR_PENTIUMPRO
,
562 { "pentiumiii",PROCESSOR_PENTIUMPRO
,
564 { "pentium4", PROCESSOR_PENTIUM4
,
566 { "prescott", PROCESSOR_NOCONA
,
568 { "nocona", PROCESSOR_NOCONA
,
570 { "yonah", PROCESSOR_CORE
,
572 { "core", PROCESSOR_CORE
,
574 { "merom", PROCESSOR_CORE2
,
576 { "core2", PROCESSOR_CORE2
,
578 { "corei7", PROCESSOR_COREI7
,
580 { "l1om", PROCESSOR_L1OM
,
582 { "k6", PROCESSOR_K6
,
584 { "k6_2", PROCESSOR_K6
,
586 { "athlon", PROCESSOR_ATHLON
,
588 { "sledgehammer", PROCESSOR_K8
,
590 { "opteron", PROCESSOR_K8
,
592 { "k8", PROCESSOR_K8
,
594 { "amdfam10", PROCESSOR_AMDFAM10
,
595 CPU_AMDFAM10_FLAGS
},
596 { ".8087", PROCESSOR_UNKNOWN
,
598 { ".287", PROCESSOR_UNKNOWN
,
600 { ".387", PROCESSOR_UNKNOWN
,
602 { ".no87", PROCESSOR_UNKNOWN
,
604 { ".mmx", PROCESSOR_UNKNOWN
,
606 { ".nommx", PROCESSOR_UNKNOWN
,
608 { ".sse", PROCESSOR_UNKNOWN
,
610 { ".sse2", PROCESSOR_UNKNOWN
,
612 { ".sse3", PROCESSOR_UNKNOWN
,
614 { ".ssse3", PROCESSOR_UNKNOWN
,
616 { ".sse4.1", PROCESSOR_UNKNOWN
,
618 { ".sse4.2", PROCESSOR_UNKNOWN
,
620 { ".sse4", PROCESSOR_UNKNOWN
,
622 { ".nosse", PROCESSOR_UNKNOWN
,
624 { ".avx", PROCESSOR_UNKNOWN
,
626 { ".noavx", PROCESSOR_UNKNOWN
,
628 { ".vmx", PROCESSOR_UNKNOWN
,
630 { ".smx", PROCESSOR_UNKNOWN
,
632 { ".xsave", PROCESSOR_UNKNOWN
,
634 { ".aes", PROCESSOR_UNKNOWN
,
636 { ".pclmul", PROCESSOR_UNKNOWN
,
638 { ".clmul", PROCESSOR_UNKNOWN
,
640 { ".fma", PROCESSOR_UNKNOWN
,
642 { ".fma4", PROCESSOR_UNKNOWN
,
644 { ".movbe", PROCESSOR_UNKNOWN
,
646 { ".ept", PROCESSOR_UNKNOWN
,
648 { ".clflush", PROCESSOR_UNKNOWN
,
650 { ".syscall", PROCESSOR_UNKNOWN
,
652 { ".rdtscp", PROCESSOR_UNKNOWN
,
654 { ".3dnow", PROCESSOR_UNKNOWN
,
656 { ".3dnowa", PROCESSOR_UNKNOWN
,
658 { ".padlock", PROCESSOR_UNKNOWN
,
660 { ".pacifica", PROCESSOR_UNKNOWN
,
662 { ".svme", PROCESSOR_UNKNOWN
,
664 { ".sse4a", PROCESSOR_UNKNOWN
,
666 { ".abm", PROCESSOR_UNKNOWN
,
671 /* Like s_lcomm_internal in gas/read.c but the alignment string
672 is allowed to be optional. */
675 pe_lcomm_internal (int needs_align
, symbolS
*symbolP
, addressT size
)
682 && *input_line_pointer
== ',')
684 align
= parse_align (needs_align
- 1);
686 if (align
== (addressT
) -1)
701 bss_alloc (symbolP
, size
, align
);
706 pe_lcomm (int needs_align
)
708 s_comm_internal (needs_align
* 2, pe_lcomm_internal
);
712 const pseudo_typeS md_pseudo_table
[] =
714 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
715 {"align", s_align_bytes
, 0},
717 {"align", s_align_ptwo
, 0},
719 {"arch", set_cpu_arch
, 0},
723 {"lcomm", pe_lcomm
, 1},
725 {"ffloat", float_cons
, 'f'},
726 {"dfloat", float_cons
, 'd'},
727 {"tfloat", float_cons
, 'x'},
729 {"slong", signed_cons
, 4},
730 {"noopt", s_ignore
, 0},
731 {"optim", s_ignore
, 0},
732 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
733 {"code16", set_code_flag
, CODE_16BIT
},
734 {"code32", set_code_flag
, CODE_32BIT
},
735 {"code64", set_code_flag
, CODE_64BIT
},
736 {"intel_syntax", set_intel_syntax
, 1},
737 {"att_syntax", set_intel_syntax
, 0},
738 {"intel_mnemonic", set_intel_mnemonic
, 1},
739 {"att_mnemonic", set_intel_mnemonic
, 0},
740 {"allow_index_reg", set_allow_index_reg
, 1},
741 {"disallow_index_reg", set_allow_index_reg
, 0},
742 {"sse_check", set_sse_check
, 0},
743 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
744 {"largecomm", handle_large_common
, 0},
746 {"file", (void (*) (int)) dwarf2_directive_file
, 0},
747 {"loc", dwarf2_directive_loc
, 0},
748 {"loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0},
751 {"secrel32", pe_directive_secrel
, 0},
756 /* For interface with expression (). */
757 extern char *input_line_pointer
;
759 /* Hash table for instruction mnemonic lookup. */
760 static struct hash_control
*op_hash
;
762 /* Hash table for register lookup. */
763 static struct hash_control
*reg_hash
;
766 i386_align_code (fragS
*fragP
, int count
)
768 /* Various efficient no-op patterns for aligning code labels.
769 Note: Don't try to assemble the instructions in the comments.
770 0L and 0w are not legal. */
771 static const char f32_1
[] =
773 static const char f32_2
[] =
774 {0x66,0x90}; /* xchg %ax,%ax */
775 static const char f32_3
[] =
776 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
777 static const char f32_4
[] =
778 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
779 static const char f32_5
[] =
781 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
782 static const char f32_6
[] =
783 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
784 static const char f32_7
[] =
785 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
786 static const char f32_8
[] =
788 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
789 static const char f32_9
[] =
790 {0x89,0xf6, /* movl %esi,%esi */
791 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
792 static const char f32_10
[] =
793 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
794 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
795 static const char f32_11
[] =
796 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
797 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
798 static const char f32_12
[] =
799 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
800 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
801 static const char f32_13
[] =
802 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
803 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
804 static const char f32_14
[] =
805 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
806 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
807 static const char f16_3
[] =
808 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
809 static const char f16_4
[] =
810 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
811 static const char f16_5
[] =
813 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
814 static const char f16_6
[] =
815 {0x89,0xf6, /* mov %si,%si */
816 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
817 static const char f16_7
[] =
818 {0x8d,0x74,0x00, /* lea 0(%si),%si */
819 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
820 static const char f16_8
[] =
821 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
822 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
823 static const char jump_31
[] =
824 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
825 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
826 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
827 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
828 static const char *const f32_patt
[] = {
829 f32_1
, f32_2
, f32_3
, f32_4
, f32_5
, f32_6
, f32_7
, f32_8
,
830 f32_9
, f32_10
, f32_11
, f32_12
, f32_13
, f32_14
832 static const char *const f16_patt
[] = {
833 f32_1
, f32_2
, f16_3
, f16_4
, f16_5
, f16_6
, f16_7
, f16_8
836 static const char alt_3
[] =
838 /* nopl 0(%[re]ax) */
839 static const char alt_4
[] =
840 {0x0f,0x1f,0x40,0x00};
841 /* nopl 0(%[re]ax,%[re]ax,1) */
842 static const char alt_5
[] =
843 {0x0f,0x1f,0x44,0x00,0x00};
844 /* nopw 0(%[re]ax,%[re]ax,1) */
845 static const char alt_6
[] =
846 {0x66,0x0f,0x1f,0x44,0x00,0x00};
847 /* nopl 0L(%[re]ax) */
848 static const char alt_7
[] =
849 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
850 /* nopl 0L(%[re]ax,%[re]ax,1) */
851 static const char alt_8
[] =
852 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
853 /* nopw 0L(%[re]ax,%[re]ax,1) */
854 static const char alt_9
[] =
855 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
856 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
857 static const char alt_10
[] =
858 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
860 nopw %cs:0L(%[re]ax,%[re]ax,1) */
861 static const char alt_long_11
[] =
863 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
866 nopw %cs:0L(%[re]ax,%[re]ax,1) */
867 static const char alt_long_12
[] =
870 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
874 nopw %cs:0L(%[re]ax,%[re]ax,1) */
875 static const char alt_long_13
[] =
879 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
884 nopw %cs:0L(%[re]ax,%[re]ax,1) */
885 static const char alt_long_14
[] =
890 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
896 nopw %cs:0L(%[re]ax,%[re]ax,1) */
897 static const char alt_long_15
[] =
903 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
904 /* nopl 0(%[re]ax,%[re]ax,1)
905 nopw 0(%[re]ax,%[re]ax,1) */
906 static const char alt_short_11
[] =
907 {0x0f,0x1f,0x44,0x00,0x00,
908 0x66,0x0f,0x1f,0x44,0x00,0x00};
909 /* nopw 0(%[re]ax,%[re]ax,1)
910 nopw 0(%[re]ax,%[re]ax,1) */
911 static const char alt_short_12
[] =
912 {0x66,0x0f,0x1f,0x44,0x00,0x00,
913 0x66,0x0f,0x1f,0x44,0x00,0x00};
914 /* nopw 0(%[re]ax,%[re]ax,1)
916 static const char alt_short_13
[] =
917 {0x66,0x0f,0x1f,0x44,0x00,0x00,
918 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
921 static const char alt_short_14
[] =
922 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
923 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
925 nopl 0L(%[re]ax,%[re]ax,1) */
926 static const char alt_short_15
[] =
927 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
928 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
929 static const char *const alt_short_patt
[] = {
930 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
931 alt_9
, alt_10
, alt_short_11
, alt_short_12
, alt_short_13
,
932 alt_short_14
, alt_short_15
934 static const char *const alt_long_patt
[] = {
935 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
936 alt_9
, alt_10
, alt_long_11
, alt_long_12
, alt_long_13
,
937 alt_long_14
, alt_long_15
940 /* Only align for at least a positive non-zero boundary. */
941 if (count
<= 0 || count
> MAX_MEM_FOR_RS_ALIGN_CODE
)
944 /* We need to decide which NOP sequence to use for 32bit and
945 64bit. When -mtune= is used:
947 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
948 PROCESSOR_GENERIC32, f32_patt will be used.
949 2. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
950 PROCESSOR_CORE, PROCESSOR_CORE2, PROCESSOR_COREI7, and
951 PROCESSOR_GENERIC64, alt_long_patt will be used.
952 3. For PROCESSOR_ATHLON, PROCESSOR_K6, PROCESSOR_K8 and
953 PROCESSOR_AMDFAM10, alt_short_patt will be used.
955 When -mtune= isn't used, alt_long_patt will be used if
956 cpu_arch_isa_flags has Cpu686. Otherwise, f32_patt will
959 When -march= or .arch is used, we can't use anything beyond
960 cpu_arch_isa_flags. */
962 if (flag_code
== CODE_16BIT
)
966 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
968 /* Adjust jump offset. */
969 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
972 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
973 f16_patt
[count
- 1], count
);
977 const char *const *patt
= NULL
;
979 if (fragP
->tc_frag_data
.isa
== PROCESSOR_UNKNOWN
)
981 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
982 switch (cpu_arch_tune
)
984 case PROCESSOR_UNKNOWN
:
985 /* We use cpu_arch_isa_flags to check if we SHOULD
986 optimize for Cpu686. */
987 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpui686
)
988 patt
= alt_long_patt
;
992 case PROCESSOR_PENTIUMPRO
:
993 case PROCESSOR_PENTIUM4
:
994 case PROCESSOR_NOCONA
:
996 case PROCESSOR_CORE2
:
997 case PROCESSOR_COREI7
:
999 case PROCESSOR_GENERIC64
:
1000 patt
= alt_long_patt
;
1003 case PROCESSOR_ATHLON
:
1005 case PROCESSOR_AMDFAM10
:
1006 patt
= alt_short_patt
;
1008 case PROCESSOR_I386
:
1009 case PROCESSOR_I486
:
1010 case PROCESSOR_PENTIUM
:
1011 case PROCESSOR_GENERIC32
:
1018 switch (fragP
->tc_frag_data
.tune
)
1020 case PROCESSOR_UNKNOWN
:
1021 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1022 PROCESSOR_UNKNOWN. */
1026 case PROCESSOR_I386
:
1027 case PROCESSOR_I486
:
1028 case PROCESSOR_PENTIUM
:
1030 case PROCESSOR_ATHLON
:
1032 case PROCESSOR_AMDFAM10
:
1033 case PROCESSOR_GENERIC32
:
1034 /* We use cpu_arch_isa_flags to check if we CAN optimize
1036 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpui686
)
1037 patt
= alt_short_patt
;
1041 case PROCESSOR_PENTIUMPRO
:
1042 case PROCESSOR_PENTIUM4
:
1043 case PROCESSOR_NOCONA
:
1044 case PROCESSOR_CORE
:
1045 case PROCESSOR_CORE2
:
1046 case PROCESSOR_COREI7
:
1047 case PROCESSOR_L1OM
:
1048 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpui686
)
1049 patt
= alt_long_patt
;
1053 case PROCESSOR_GENERIC64
:
1054 patt
= alt_long_patt
;
1059 if (patt
== f32_patt
)
1061 /* If the padding is less than 15 bytes, we use the normal
1062 ones. Otherwise, we use a jump instruction and adjust
1066 /* For 64bit, the limit is 3 bytes. */
1067 if (flag_code
== CODE_64BIT
1068 && fragP
->tc_frag_data
.isa_flags
.bitfield
.cpulm
)
1073 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1074 patt
[count
- 1], count
);
1077 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1079 /* Adjust jump offset. */
1080 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
1085 /* Maximum length of an instruction is 15 byte. If the
1086 padding is greater than 15 bytes and we don't use jump,
1087 we have to break it into smaller pieces. */
1088 int padding
= count
;
1089 while (padding
> 15)
1092 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
+ padding
,
1097 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1098 patt
[padding
- 1], padding
);
1101 fragP
->fr_var
= count
;
1105 operand_type_all_zero (const union i386_operand_type
*x
)
1107 switch (ARRAY_SIZE(x
->array
))
1116 return !x
->array
[0];
1123 operand_type_set (union i386_operand_type
*x
, unsigned int v
)
1125 switch (ARRAY_SIZE(x
->array
))
1140 operand_type_equal (const union i386_operand_type
*x
,
1141 const union i386_operand_type
*y
)
1143 switch (ARRAY_SIZE(x
->array
))
1146 if (x
->array
[2] != y
->array
[2])
1149 if (x
->array
[1] != y
->array
[1])
1152 return x
->array
[0] == y
->array
[0];
1160 cpu_flags_all_zero (const union i386_cpu_flags
*x
)
1162 switch (ARRAY_SIZE(x
->array
))
1171 return !x
->array
[0];
1178 cpu_flags_set (union i386_cpu_flags
*x
, unsigned int v
)
1180 switch (ARRAY_SIZE(x
->array
))
1195 cpu_flags_equal (const union i386_cpu_flags
*x
,
1196 const union i386_cpu_flags
*y
)
1198 switch (ARRAY_SIZE(x
->array
))
1201 if (x
->array
[2] != y
->array
[2])
1204 if (x
->array
[1] != y
->array
[1])
1207 return x
->array
[0] == y
->array
[0];
1215 cpu_flags_check_cpu64 (i386_cpu_flags f
)
1217 return !((flag_code
== CODE_64BIT
&& f
.bitfield
.cpuno64
)
1218 || (flag_code
!= CODE_64BIT
&& f
.bitfield
.cpu64
));
1221 static INLINE i386_cpu_flags
1222 cpu_flags_and (i386_cpu_flags x
, i386_cpu_flags y
)
1224 switch (ARRAY_SIZE (x
.array
))
1227 x
.array
[2] &= y
.array
[2];
1229 x
.array
[1] &= y
.array
[1];
1231 x
.array
[0] &= y
.array
[0];
1239 static INLINE i386_cpu_flags
1240 cpu_flags_or (i386_cpu_flags x
, i386_cpu_flags y
)
1242 switch (ARRAY_SIZE (x
.array
))
1245 x
.array
[2] |= y
.array
[2];
1247 x
.array
[1] |= y
.array
[1];
1249 x
.array
[0] |= y
.array
[0];
1257 static INLINE i386_cpu_flags
1258 cpu_flags_and_not (i386_cpu_flags x
, i386_cpu_flags y
)
1260 switch (ARRAY_SIZE (x
.array
))
1263 x
.array
[2] &= ~y
.array
[2];
1265 x
.array
[1] &= ~y
.array
[1];
1267 x
.array
[0] &= ~y
.array
[0];
1275 #define CPU_FLAGS_ARCH_MATCH 0x1
1276 #define CPU_FLAGS_64BIT_MATCH 0x2
1277 #define CPU_FLAGS_AES_MATCH 0x4
1278 #define CPU_FLAGS_PCLMUL_MATCH 0x8
1279 #define CPU_FLAGS_AVX_MATCH 0x10
1281 #define CPU_FLAGS_32BIT_MATCH \
1282 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH \
1283 | CPU_FLAGS_PCLMUL_MATCH | CPU_FLAGS_AVX_MATCH)
1284 #define CPU_FLAGS_PERFECT_MATCH \
1285 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)
1287 /* Return CPU flags match bits. */
1290 cpu_flags_match (const insn_template
*t
)
1292 i386_cpu_flags x
= t
->cpu_flags
;
1293 int match
= cpu_flags_check_cpu64 (x
) ? CPU_FLAGS_64BIT_MATCH
: 0;
1295 x
.bitfield
.cpu64
= 0;
1296 x
.bitfield
.cpuno64
= 0;
1298 if (cpu_flags_all_zero (&x
))
1300 /* This instruction is available on all archs. */
1301 match
|= CPU_FLAGS_32BIT_MATCH
;
1305 /* This instruction is available only on some archs. */
1306 i386_cpu_flags cpu
= cpu_arch_flags
;
1308 cpu
.bitfield
.cpu64
= 0;
1309 cpu
.bitfield
.cpuno64
= 0;
1310 cpu
= cpu_flags_and (x
, cpu
);
1311 if (!cpu_flags_all_zero (&cpu
))
1313 if (x
.bitfield
.cpuavx
)
1315 /* We only need to check AES/PCLMUL/SSE2AVX with AVX. */
1316 if (cpu
.bitfield
.cpuavx
)
1318 /* Check SSE2AVX. */
1319 if (!t
->opcode_modifier
.sse2avx
|| sse2avx
)
1321 match
|= (CPU_FLAGS_ARCH_MATCH
1322 | CPU_FLAGS_AVX_MATCH
);
1324 if (!x
.bitfield
.cpuaes
|| cpu
.bitfield
.cpuaes
)
1325 match
|= CPU_FLAGS_AES_MATCH
;
1327 if (!x
.bitfield
.cpupclmul
1328 || cpu
.bitfield
.cpupclmul
)
1329 match
|= CPU_FLAGS_PCLMUL_MATCH
;
1333 match
|= CPU_FLAGS_ARCH_MATCH
;
1336 match
|= CPU_FLAGS_32BIT_MATCH
;
1342 static INLINE i386_operand_type
1343 operand_type_and (i386_operand_type x
, i386_operand_type y
)
1345 switch (ARRAY_SIZE (x
.array
))
1348 x
.array
[2] &= y
.array
[2];
1350 x
.array
[1] &= y
.array
[1];
1352 x
.array
[0] &= y
.array
[0];
1360 static INLINE i386_operand_type
1361 operand_type_or (i386_operand_type x
, i386_operand_type y
)
1363 switch (ARRAY_SIZE (x
.array
))
1366 x
.array
[2] |= y
.array
[2];
1368 x
.array
[1] |= y
.array
[1];
1370 x
.array
[0] |= y
.array
[0];
1378 static INLINE i386_operand_type
1379 operand_type_xor (i386_operand_type x
, i386_operand_type y
)
1381 switch (ARRAY_SIZE (x
.array
))
1384 x
.array
[2] ^= y
.array
[2];
1386 x
.array
[1] ^= y
.array
[1];
1388 x
.array
[0] ^= y
.array
[0];
1396 static const i386_operand_type acc32
= OPERAND_TYPE_ACC32
;
1397 static const i386_operand_type acc64
= OPERAND_TYPE_ACC64
;
1398 static const i386_operand_type control
= OPERAND_TYPE_CONTROL
;
1399 static const i386_operand_type inoutportreg
1400 = OPERAND_TYPE_INOUTPORTREG
;
1401 static const i386_operand_type reg16_inoutportreg
1402 = OPERAND_TYPE_REG16_INOUTPORTREG
;
1403 static const i386_operand_type disp16
= OPERAND_TYPE_DISP16
;
1404 static const i386_operand_type disp32
= OPERAND_TYPE_DISP32
;
1405 static const i386_operand_type disp32s
= OPERAND_TYPE_DISP32S
;
1406 static const i386_operand_type disp16_32
= OPERAND_TYPE_DISP16_32
;
1407 static const i386_operand_type anydisp
1408 = OPERAND_TYPE_ANYDISP
;
1409 static const i386_operand_type regxmm
= OPERAND_TYPE_REGXMM
;
1410 static const i386_operand_type regymm
= OPERAND_TYPE_REGYMM
;
1411 static const i386_operand_type imm8
= OPERAND_TYPE_IMM8
;
1412 static const i386_operand_type imm8s
= OPERAND_TYPE_IMM8S
;
1413 static const i386_operand_type imm16
= OPERAND_TYPE_IMM16
;
1414 static const i386_operand_type imm32
= OPERAND_TYPE_IMM32
;
1415 static const i386_operand_type imm32s
= OPERAND_TYPE_IMM32S
;
1416 static const i386_operand_type imm64
= OPERAND_TYPE_IMM64
;
1417 static const i386_operand_type imm16_32
= OPERAND_TYPE_IMM16_32
;
1418 static const i386_operand_type imm16_32s
= OPERAND_TYPE_IMM16_32S
;
1419 static const i386_operand_type imm16_32_32s
= OPERAND_TYPE_IMM16_32_32S
;
1430 operand_type_check (i386_operand_type t
, enum operand_type c
)
1435 return (t
.bitfield
.reg8
1438 || t
.bitfield
.reg64
);
1441 return (t
.bitfield
.imm8
1445 || t
.bitfield
.imm32s
1446 || t
.bitfield
.imm64
);
1449 return (t
.bitfield
.disp8
1450 || t
.bitfield
.disp16
1451 || t
.bitfield
.disp32
1452 || t
.bitfield
.disp32s
1453 || t
.bitfield
.disp64
);
1456 return (t
.bitfield
.disp8
1457 || t
.bitfield
.disp16
1458 || t
.bitfield
.disp32
1459 || t
.bitfield
.disp32s
1460 || t
.bitfield
.disp64
1461 || t
.bitfield
.baseindex
);
1470 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1471 operand J for instruction template T. */
1474 match_reg_size (const insn_template
*t
, unsigned int j
)
1476 return !((i
.types
[j
].bitfield
.byte
1477 && !t
->operand_types
[j
].bitfield
.byte
)
1478 || (i
.types
[j
].bitfield
.word
1479 && !t
->operand_types
[j
].bitfield
.word
)
1480 || (i
.types
[j
].bitfield
.dword
1481 && !t
->operand_types
[j
].bitfield
.dword
)
1482 || (i
.types
[j
].bitfield
.qword
1483 && !t
->operand_types
[j
].bitfield
.qword
));
1486 /* Return 1 if there is no conflict in any size on operand J for
1487 instruction template T. */
1490 match_mem_size (const insn_template
*t
, unsigned int j
)
1492 return (match_reg_size (t
, j
)
1493 && !((i
.types
[j
].bitfield
.unspecified
1494 && !t
->operand_types
[j
].bitfield
.unspecified
)
1495 || (i
.types
[j
].bitfield
.fword
1496 && !t
->operand_types
[j
].bitfield
.fword
)
1497 || (i
.types
[j
].bitfield
.tbyte
1498 && !t
->operand_types
[j
].bitfield
.tbyte
)
1499 || (i
.types
[j
].bitfield
.xmmword
1500 && !t
->operand_types
[j
].bitfield
.xmmword
)
1501 || (i
.types
[j
].bitfield
.ymmword
1502 && !t
->operand_types
[j
].bitfield
.ymmword
)));
1505 /* Return 1 if there is no size conflict on any operands for
1506 instruction template T. */
1509 operand_size_match (const insn_template
*t
)
1514 /* Don't check jump instructions. */
1515 if (t
->opcode_modifier
.jump
1516 || t
->opcode_modifier
.jumpbyte
1517 || t
->opcode_modifier
.jumpdword
1518 || t
->opcode_modifier
.jumpintersegment
)
1521 /* Check memory and accumulator operand size. */
1522 for (j
= 0; j
< i
.operands
; j
++)
1524 if (t
->operand_types
[j
].bitfield
.anysize
)
1527 if (t
->operand_types
[j
].bitfield
.acc
&& !match_reg_size (t
, j
))
1533 if (i
.types
[j
].bitfield
.mem
&& !match_mem_size (t
, j
))
1541 || (!t
->opcode_modifier
.d
&& !t
->opcode_modifier
.floatd
))
1544 /* Check reverse. */
1545 gas_assert (i
.operands
== 2);
1548 for (j
= 0; j
< 2; j
++)
1550 if (t
->operand_types
[j
].bitfield
.acc
1551 && !match_reg_size (t
, j
? 0 : 1))
1557 if (i
.types
[j
].bitfield
.mem
1558 && !match_mem_size (t
, j
? 0 : 1))
1569 operand_type_match (i386_operand_type overlap
,
1570 i386_operand_type given
)
1572 i386_operand_type temp
= overlap
;
1574 temp
.bitfield
.jumpabsolute
= 0;
1575 temp
.bitfield
.unspecified
= 0;
1576 temp
.bitfield
.byte
= 0;
1577 temp
.bitfield
.word
= 0;
1578 temp
.bitfield
.dword
= 0;
1579 temp
.bitfield
.fword
= 0;
1580 temp
.bitfield
.qword
= 0;
1581 temp
.bitfield
.tbyte
= 0;
1582 temp
.bitfield
.xmmword
= 0;
1583 temp
.bitfield
.ymmword
= 0;
1584 if (operand_type_all_zero (&temp
))
1587 return (given
.bitfield
.baseindex
== overlap
.bitfield
.baseindex
1588 && given
.bitfield
.jumpabsolute
== overlap
.bitfield
.jumpabsolute
);
1591 /* If given types g0 and g1 are registers they must be of the same type
1592 unless the expected operand type register overlap is null.
1593 Note that Acc in a template matches every size of reg. */
1596 operand_type_register_match (i386_operand_type m0
,
1597 i386_operand_type g0
,
1598 i386_operand_type t0
,
1599 i386_operand_type m1
,
1600 i386_operand_type g1
,
1601 i386_operand_type t1
)
1603 if (!operand_type_check (g0
, reg
))
1606 if (!operand_type_check (g1
, reg
))
1609 if (g0
.bitfield
.reg8
== g1
.bitfield
.reg8
1610 && g0
.bitfield
.reg16
== g1
.bitfield
.reg16
1611 && g0
.bitfield
.reg32
== g1
.bitfield
.reg32
1612 && g0
.bitfield
.reg64
== g1
.bitfield
.reg64
)
1615 if (m0
.bitfield
.acc
)
1617 t0
.bitfield
.reg8
= 1;
1618 t0
.bitfield
.reg16
= 1;
1619 t0
.bitfield
.reg32
= 1;
1620 t0
.bitfield
.reg64
= 1;
1623 if (m1
.bitfield
.acc
)
1625 t1
.bitfield
.reg8
= 1;
1626 t1
.bitfield
.reg16
= 1;
1627 t1
.bitfield
.reg32
= 1;
1628 t1
.bitfield
.reg64
= 1;
1631 return (!(t0
.bitfield
.reg8
& t1
.bitfield
.reg8
)
1632 && !(t0
.bitfield
.reg16
& t1
.bitfield
.reg16
)
1633 && !(t0
.bitfield
.reg32
& t1
.bitfield
.reg32
)
1634 && !(t0
.bitfield
.reg64
& t1
.bitfield
.reg64
));
1637 static INLINE
unsigned int
1638 mode_from_disp_size (i386_operand_type t
)
1640 if (t
.bitfield
.disp8
)
1642 else if (t
.bitfield
.disp16
1643 || t
.bitfield
.disp32
1644 || t
.bitfield
.disp32s
)
1651 fits_in_signed_byte (offsetT num
)
1653 return (num
>= -128) && (num
<= 127);
1657 fits_in_unsigned_byte (offsetT num
)
1659 return (num
& 0xff) == num
;
1663 fits_in_unsigned_word (offsetT num
)
1665 return (num
& 0xffff) == num
;
1669 fits_in_signed_word (offsetT num
)
1671 return (-32768 <= num
) && (num
<= 32767);
1675 fits_in_signed_long (offsetT num ATTRIBUTE_UNUSED
)
1680 return (!(((offsetT
) -1 << 31) & num
)
1681 || (((offsetT
) -1 << 31) & num
) == ((offsetT
) -1 << 31));
1683 } /* fits_in_signed_long() */
1686 fits_in_unsigned_long (offsetT num ATTRIBUTE_UNUSED
)
1691 return (num
& (((offsetT
) 2 << 31) - 1)) == num
;
1693 } /* fits_in_unsigned_long() */
1695 static i386_operand_type
1696 smallest_imm_type (offsetT num
)
1698 i386_operand_type t
;
1700 operand_type_set (&t
, 0);
1701 t
.bitfield
.imm64
= 1;
1703 if (cpu_arch_tune
!= PROCESSOR_I486
&& num
== 1)
1705 /* This code is disabled on the 486 because all the Imm1 forms
1706 in the opcode table are slower on the i486. They're the
1707 versions with the implicitly specified single-position
1708 displacement, which has another syntax if you really want to
1710 t
.bitfield
.imm1
= 1;
1711 t
.bitfield
.imm8
= 1;
1712 t
.bitfield
.imm8s
= 1;
1713 t
.bitfield
.imm16
= 1;
1714 t
.bitfield
.imm32
= 1;
1715 t
.bitfield
.imm32s
= 1;
1717 else if (fits_in_signed_byte (num
))
1719 t
.bitfield
.imm8
= 1;
1720 t
.bitfield
.imm8s
= 1;
1721 t
.bitfield
.imm16
= 1;
1722 t
.bitfield
.imm32
= 1;
1723 t
.bitfield
.imm32s
= 1;
1725 else if (fits_in_unsigned_byte (num
))
1727 t
.bitfield
.imm8
= 1;
1728 t
.bitfield
.imm16
= 1;
1729 t
.bitfield
.imm32
= 1;
1730 t
.bitfield
.imm32s
= 1;
1732 else if (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
1734 t
.bitfield
.imm16
= 1;
1735 t
.bitfield
.imm32
= 1;
1736 t
.bitfield
.imm32s
= 1;
1738 else if (fits_in_signed_long (num
))
1740 t
.bitfield
.imm32
= 1;
1741 t
.bitfield
.imm32s
= 1;
1743 else if (fits_in_unsigned_long (num
))
1744 t
.bitfield
.imm32
= 1;
1750 offset_in_range (offsetT val
, int size
)
1756 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
1757 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
1758 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
1760 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
1765 /* If BFD64, sign extend val. */
1766 if (!use_rela_relocations
)
1767 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
1768 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
1770 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
1772 char buf1
[40], buf2
[40];
1774 sprint_value (buf1
, val
);
1775 sprint_value (buf2
, val
& mask
);
1776 as_warn (_("%s shortened to %s"), buf1
, buf2
);
1781 /* Returns 0 if attempting to add a prefix where one from the same
1782 class already exists, 1 if non rep/repne added, 2 if rep/repne
1785 add_prefix (unsigned int prefix
)
1790 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
1791 && flag_code
== CODE_64BIT
)
1793 if ((i
.prefix
[REX_PREFIX
] & prefix
& REX_W
)
1794 || ((i
.prefix
[REX_PREFIX
] & (REX_R
| REX_X
| REX_B
))
1795 && (prefix
& (REX_R
| REX_X
| REX_B
))))
1806 case CS_PREFIX_OPCODE
:
1807 case DS_PREFIX_OPCODE
:
1808 case ES_PREFIX_OPCODE
:
1809 case FS_PREFIX_OPCODE
:
1810 case GS_PREFIX_OPCODE
:
1811 case SS_PREFIX_OPCODE
:
1815 case REPNE_PREFIX_OPCODE
:
1816 case REPE_PREFIX_OPCODE
:
1819 case LOCK_PREFIX_OPCODE
:
1827 case ADDR_PREFIX_OPCODE
:
1831 case DATA_PREFIX_OPCODE
:
1835 if (i
.prefix
[q
] != 0)
1843 i
.prefix
[q
] |= prefix
;
1846 as_bad (_("same type of prefix used twice"));
1852 set_code_flag (int value
)
1854 flag_code
= (enum flag_code
) value
;
1855 if (flag_code
== CODE_64BIT
)
1857 cpu_arch_flags
.bitfield
.cpu64
= 1;
1858 cpu_arch_flags
.bitfield
.cpuno64
= 0;
1862 cpu_arch_flags
.bitfield
.cpu64
= 0;
1863 cpu_arch_flags
.bitfield
.cpuno64
= 1;
1865 if (value
== CODE_64BIT
&& !cpu_arch_flags
.bitfield
.cpulm
)
1867 as_bad (_("64bit mode not supported on this CPU."));
1869 if (value
== CODE_32BIT
&& !cpu_arch_flags
.bitfield
.cpui386
)
1871 as_bad (_("32bit mode not supported on this CPU."));
1873 stackop_size
= '\0';
1877 set_16bit_gcc_code_flag (int new_code_flag
)
1879 flag_code
= (enum flag_code
) new_code_flag
;
1880 if (flag_code
!= CODE_16BIT
)
1882 cpu_arch_flags
.bitfield
.cpu64
= 0;
1883 cpu_arch_flags
.bitfield
.cpuno64
= 1;
1884 stackop_size
= LONG_MNEM_SUFFIX
;
1888 set_intel_syntax (int syntax_flag
)
1890 /* Find out if register prefixing is specified. */
1891 int ask_naked_reg
= 0;
1894 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
1896 char *string
= input_line_pointer
;
1897 int e
= get_symbol_end ();
1899 if (strcmp (string
, "prefix") == 0)
1901 else if (strcmp (string
, "noprefix") == 0)
1904 as_bad (_("bad argument to syntax directive."));
1905 *input_line_pointer
= e
;
1907 demand_empty_rest_of_line ();
1909 intel_syntax
= syntax_flag
;
1911 if (ask_naked_reg
== 0)
1912 allow_naked_reg
= (intel_syntax
1913 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
1915 allow_naked_reg
= (ask_naked_reg
< 0);
1917 expr_set_rank (O_full_ptr
, syntax_flag
? 10 : 0);
1919 identifier_chars
['%'] = intel_syntax
&& allow_naked_reg
? '%' : 0;
1920 identifier_chars
['$'] = intel_syntax
? '$' : 0;
1921 register_prefix
= allow_naked_reg
? "" : "%";
1925 set_intel_mnemonic (int mnemonic_flag
)
1927 intel_mnemonic
= mnemonic_flag
;
1931 set_allow_index_reg (int flag
)
1933 allow_index_reg
= flag
;
1937 set_sse_check (int dummy ATTRIBUTE_UNUSED
)
1941 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
1943 char *string
= input_line_pointer
;
1944 int e
= get_symbol_end ();
1946 if (strcmp (string
, "none") == 0)
1947 sse_check
= sse_check_none
;
1948 else if (strcmp (string
, "warning") == 0)
1949 sse_check
= sse_check_warning
;
1950 else if (strcmp (string
, "error") == 0)
1951 sse_check
= sse_check_error
;
1953 as_bad (_("bad argument to sse_check directive."));
1954 *input_line_pointer
= e
;
1957 as_bad (_("missing argument for sse_check directive"));
1959 demand_empty_rest_of_line ();
1963 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED
,
1964 i386_cpu_flags new_flag ATTRIBUTE_UNUSED
)
1966 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1967 static const char *arch
;
1969 /* Intel LIOM is only supported on ELF. */
1975 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
1976 use default_arch. */
1977 arch
= cpu_arch_name
;
1979 arch
= default_arch
;
1982 /* If we are targeting Intel L1OM, we must enable it. */
1983 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_L1OM
1984 || new_flag
.bitfield
.cpul1om
)
1987 as_bad (_("`%s' is not supported on `%s'"), name
, arch
);
1992 set_cpu_arch (int dummy ATTRIBUTE_UNUSED
)
1996 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
1998 char *string
= input_line_pointer
;
1999 int e
= get_symbol_end ();
2001 i386_cpu_flags flags
;
2003 for (i
= 0; i
< ARRAY_SIZE (cpu_arch
); i
++)
2005 if (strcmp (string
, cpu_arch
[i
].name
) == 0)
2007 check_cpu_arch_compatible (string
, cpu_arch
[i
].flags
);
2011 cpu_arch_name
= cpu_arch
[i
].name
;
2012 cpu_sub_arch_name
= NULL
;
2013 cpu_arch_flags
= cpu_arch
[i
].flags
;
2014 if (flag_code
== CODE_64BIT
)
2016 cpu_arch_flags
.bitfield
.cpu64
= 1;
2017 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2021 cpu_arch_flags
.bitfield
.cpu64
= 0;
2022 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2024 cpu_arch_isa
= cpu_arch
[i
].type
;
2025 cpu_arch_isa_flags
= cpu_arch
[i
].flags
;
2026 if (!cpu_arch_tune_set
)
2028 cpu_arch_tune
= cpu_arch_isa
;
2029 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
2034 if (strncmp (string
+ 1, "no", 2))
2035 flags
= cpu_flags_or (cpu_arch_flags
,
2038 flags
= cpu_flags_and_not (cpu_arch_flags
,
2040 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2042 if (cpu_sub_arch_name
)
2044 char *name
= cpu_sub_arch_name
;
2045 cpu_sub_arch_name
= concat (name
,
2047 (const char *) NULL
);
2051 cpu_sub_arch_name
= xstrdup (cpu_arch
[i
].name
);
2052 cpu_arch_flags
= flags
;
2054 *input_line_pointer
= e
;
2055 demand_empty_rest_of_line ();
2059 if (i
>= ARRAY_SIZE (cpu_arch
))
2060 as_bad (_("no such architecture: `%s'"), string
);
2062 *input_line_pointer
= e
;
2065 as_bad (_("missing cpu architecture"));
2067 no_cond_jump_promotion
= 0;
2068 if (*input_line_pointer
== ','
2069 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
2071 char *string
= ++input_line_pointer
;
2072 int e
= get_symbol_end ();
2074 if (strcmp (string
, "nojumps") == 0)
2075 no_cond_jump_promotion
= 1;
2076 else if (strcmp (string
, "jumps") == 0)
2079 as_bad (_("no such architecture modifier: `%s'"), string
);
2081 *input_line_pointer
= e
;
2084 demand_empty_rest_of_line ();
2087 enum bfd_architecture
2090 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2092 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2093 || flag_code
!= CODE_64BIT
)
2094 as_fatal (_("Intel L1OM is 64bit ELF only"));
2095 return bfd_arch_l1om
;
2098 return bfd_arch_i386
;
2104 if (!strcmp (default_arch
, "x86_64"))
2106 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2108 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
2109 as_fatal (_("Intel L1OM is 64bit ELF only"));
2110 return bfd_mach_l1om
;
2113 return bfd_mach_x86_64
;
2115 else if (!strcmp (default_arch
, "i386"))
2116 return bfd_mach_i386_i386
;
2118 as_fatal (_("Unknown architecture"));
2124 const char *hash_err
;
2126 /* Initialize op_hash hash table. */
2127 op_hash
= hash_new ();
2130 const insn_template
*optab
;
2131 templates
*core_optab
;
2133 /* Setup for loop. */
2135 core_optab
= (templates
*) xmalloc (sizeof (templates
));
2136 core_optab
->start
= optab
;
2141 if (optab
->name
== NULL
2142 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
2144 /* different name --> ship out current template list;
2145 add to hash table; & begin anew. */
2146 core_optab
->end
= optab
;
2147 hash_err
= hash_insert (op_hash
,
2149 (void *) core_optab
);
2152 as_fatal (_("Internal Error: Can't hash %s: %s"),
2156 if (optab
->name
== NULL
)
2158 core_optab
= (templates
*) xmalloc (sizeof (templates
));
2159 core_optab
->start
= optab
;
2164 /* Initialize reg_hash hash table. */
2165 reg_hash
= hash_new ();
2167 const reg_entry
*regtab
;
2168 unsigned int regtab_size
= i386_regtab_size
;
2170 for (regtab
= i386_regtab
; regtab_size
--; regtab
++)
2172 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (void *) regtab
);
2174 as_fatal (_("Internal Error: Can't hash %s: %s"),
2180 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
2185 for (c
= 0; c
< 256; c
++)
2190 mnemonic_chars
[c
] = c
;
2191 register_chars
[c
] = c
;
2192 operand_chars
[c
] = c
;
2194 else if (ISLOWER (c
))
2196 mnemonic_chars
[c
] = c
;
2197 register_chars
[c
] = c
;
2198 operand_chars
[c
] = c
;
2200 else if (ISUPPER (c
))
2202 mnemonic_chars
[c
] = TOLOWER (c
);
2203 register_chars
[c
] = mnemonic_chars
[c
];
2204 operand_chars
[c
] = c
;
2207 if (ISALPHA (c
) || ISDIGIT (c
))
2208 identifier_chars
[c
] = c
;
2211 identifier_chars
[c
] = c
;
2212 operand_chars
[c
] = c
;
2217 identifier_chars
['@'] = '@';
2220 identifier_chars
['?'] = '?';
2221 operand_chars
['?'] = '?';
2223 digit_chars
['-'] = '-';
2224 mnemonic_chars
['_'] = '_';
2225 mnemonic_chars
['-'] = '-';
2226 mnemonic_chars
['.'] = '.';
2227 identifier_chars
['_'] = '_';
2228 identifier_chars
['.'] = '.';
2230 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
2231 operand_chars
[(unsigned char) *p
] = *p
;
2234 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2237 record_alignment (text_section
, 2);
2238 record_alignment (data_section
, 2);
2239 record_alignment (bss_section
, 2);
2243 if (flag_code
== CODE_64BIT
)
2245 x86_dwarf2_return_column
= 16;
2246 x86_cie_data_alignment
= -8;
2250 x86_dwarf2_return_column
= 8;
2251 x86_cie_data_alignment
= -4;
2256 i386_print_statistics (FILE *file
)
2258 hash_print_statistics (file
, "i386 opcode", op_hash
);
2259 hash_print_statistics (file
, "i386 register", reg_hash
);
2264 /* Debugging routines for md_assemble. */
2265 static void pte (insn_template
*);
2266 static void pt (i386_operand_type
);
2267 static void pe (expressionS
*);
2268 static void ps (symbolS
*);
2271 pi (char *line
, i386_insn
*x
)
2275 fprintf (stdout
, "%s: template ", line
);
2277 fprintf (stdout
, " address: base %s index %s scale %x\n",
2278 x
->base_reg
? x
->base_reg
->reg_name
: "none",
2279 x
->index_reg
? x
->index_reg
->reg_name
: "none",
2280 x
->log2_scale_factor
);
2281 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
2282 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
2283 fprintf (stdout
, " sib: base %x index %x scale %x\n",
2284 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
2285 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
2286 (x
->rex
& REX_W
) != 0,
2287 (x
->rex
& REX_R
) != 0,
2288 (x
->rex
& REX_X
) != 0,
2289 (x
->rex
& REX_B
) != 0);
2290 for (i
= 0; i
< x
->operands
; i
++)
2292 fprintf (stdout
, " #%d: ", i
+ 1);
2294 fprintf (stdout
, "\n");
2295 if (x
->types
[i
].bitfield
.reg8
2296 || x
->types
[i
].bitfield
.reg16
2297 || x
->types
[i
].bitfield
.reg32
2298 || x
->types
[i
].bitfield
.reg64
2299 || x
->types
[i
].bitfield
.regmmx
2300 || x
->types
[i
].bitfield
.regxmm
2301 || x
->types
[i
].bitfield
.regymm
2302 || x
->types
[i
].bitfield
.sreg2
2303 || x
->types
[i
].bitfield
.sreg3
2304 || x
->types
[i
].bitfield
.control
2305 || x
->types
[i
].bitfield
.debug
2306 || x
->types
[i
].bitfield
.test
)
2307 fprintf (stdout
, "%s\n", x
->op
[i
].regs
->reg_name
);
2308 if (operand_type_check (x
->types
[i
], imm
))
2310 if (operand_type_check (x
->types
[i
], disp
))
2311 pe (x
->op
[i
].disps
);
2316 pte (insn_template
*t
)
2319 fprintf (stdout
, " %d operands ", t
->operands
);
2320 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
2321 if (t
->extension_opcode
!= None
)
2322 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
2323 if (t
->opcode_modifier
.d
)
2324 fprintf (stdout
, "D");
2325 if (t
->opcode_modifier
.w
)
2326 fprintf (stdout
, "W");
2327 fprintf (stdout
, "\n");
2328 for (i
= 0; i
< t
->operands
; i
++)
2330 fprintf (stdout
, " #%d type ", i
+ 1);
2331 pt (t
->operand_types
[i
]);
2332 fprintf (stdout
, "\n");
2339 fprintf (stdout
, " operation %d\n", e
->X_op
);
2340 fprintf (stdout
, " add_number %ld (%lx)\n",
2341 (long) e
->X_add_number
, (long) e
->X_add_number
);
2342 if (e
->X_add_symbol
)
2344 fprintf (stdout
, " add_symbol ");
2345 ps (e
->X_add_symbol
);
2346 fprintf (stdout
, "\n");
2350 fprintf (stdout
, " op_symbol ");
2351 ps (e
->X_op_symbol
);
2352 fprintf (stdout
, "\n");
2359 fprintf (stdout
, "%s type %s%s",
2361 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
2362 segment_name (S_GET_SEGMENT (s
)));
2365 static struct type_name
2367 i386_operand_type mask
;
2370 const type_names
[] =
2372 { OPERAND_TYPE_REG8
, "r8" },
2373 { OPERAND_TYPE_REG16
, "r16" },
2374 { OPERAND_TYPE_REG32
, "r32" },
2375 { OPERAND_TYPE_REG64
, "r64" },
2376 { OPERAND_TYPE_IMM8
, "i8" },
2377 { OPERAND_TYPE_IMM8
, "i8s" },
2378 { OPERAND_TYPE_IMM16
, "i16" },
2379 { OPERAND_TYPE_IMM32
, "i32" },
2380 { OPERAND_TYPE_IMM32S
, "i32s" },
2381 { OPERAND_TYPE_IMM64
, "i64" },
2382 { OPERAND_TYPE_IMM1
, "i1" },
2383 { OPERAND_TYPE_BASEINDEX
, "BaseIndex" },
2384 { OPERAND_TYPE_DISP8
, "d8" },
2385 { OPERAND_TYPE_DISP16
, "d16" },
2386 { OPERAND_TYPE_DISP32
, "d32" },
2387 { OPERAND_TYPE_DISP32S
, "d32s" },
2388 { OPERAND_TYPE_DISP64
, "d64" },
2389 { OPERAND_TYPE_INOUTPORTREG
, "InOutPortReg" },
2390 { OPERAND_TYPE_SHIFTCOUNT
, "ShiftCount" },
2391 { OPERAND_TYPE_CONTROL
, "control reg" },
2392 { OPERAND_TYPE_TEST
, "test reg" },
2393 { OPERAND_TYPE_DEBUG
, "debug reg" },
2394 { OPERAND_TYPE_FLOATREG
, "FReg" },
2395 { OPERAND_TYPE_FLOATACC
, "FAcc" },
2396 { OPERAND_TYPE_SREG2
, "SReg2" },
2397 { OPERAND_TYPE_SREG3
, "SReg3" },
2398 { OPERAND_TYPE_ACC
, "Acc" },
2399 { OPERAND_TYPE_JUMPABSOLUTE
, "Jump Absolute" },
2400 { OPERAND_TYPE_REGMMX
, "rMMX" },
2401 { OPERAND_TYPE_REGXMM
, "rXMM" },
2402 { OPERAND_TYPE_REGYMM
, "rYMM" },
2403 { OPERAND_TYPE_ESSEG
, "es" },
2407 pt (i386_operand_type t
)
2410 i386_operand_type a
;
2412 for (j
= 0; j
< ARRAY_SIZE (type_names
); j
++)
2414 a
= operand_type_and (t
, type_names
[j
].mask
);
2415 if (!operand_type_all_zero (&a
))
2416 fprintf (stdout
, "%s, ", type_names
[j
].name
);
2421 #endif /* DEBUG386 */
2423 static bfd_reloc_code_real_type
2424 reloc (unsigned int size
,
2427 bfd_reloc_code_real_type other
)
2429 if (other
!= NO_RELOC
)
2431 reloc_howto_type
*reloc
;
2436 case BFD_RELOC_X86_64_GOT32
:
2437 return BFD_RELOC_X86_64_GOT64
;
2439 case BFD_RELOC_X86_64_PLTOFF64
:
2440 return BFD_RELOC_X86_64_PLTOFF64
;
2442 case BFD_RELOC_X86_64_GOTPC32
:
2443 other
= BFD_RELOC_X86_64_GOTPC64
;
2445 case BFD_RELOC_X86_64_GOTPCREL
:
2446 other
= BFD_RELOC_X86_64_GOTPCREL64
;
2448 case BFD_RELOC_X86_64_TPOFF32
:
2449 other
= BFD_RELOC_X86_64_TPOFF64
;
2451 case BFD_RELOC_X86_64_DTPOFF32
:
2452 other
= BFD_RELOC_X86_64_DTPOFF64
;
2458 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
2459 if (size
== 4 && flag_code
!= CODE_64BIT
)
2462 reloc
= bfd_reloc_type_lookup (stdoutput
, other
);
2464 as_bad (_("unknown relocation (%u)"), other
);
2465 else if (size
!= bfd_get_reloc_size (reloc
))
2466 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
2467 bfd_get_reloc_size (reloc
),
2469 else if (pcrel
&& !reloc
->pc_relative
)
2470 as_bad (_("non-pc-relative relocation for pc-relative field"));
2471 else if ((reloc
->complain_on_overflow
== complain_overflow_signed
2473 || (reloc
->complain_on_overflow
== complain_overflow_unsigned
2475 as_bad (_("relocated field and relocation type differ in signedness"));
2484 as_bad (_("there are no unsigned pc-relative relocations"));
2487 case 1: return BFD_RELOC_8_PCREL
;
2488 case 2: return BFD_RELOC_16_PCREL
;
2489 case 4: return BFD_RELOC_32_PCREL
;
2490 case 8: return BFD_RELOC_64_PCREL
;
2492 as_bad (_("cannot do %u byte pc-relative relocation"), size
);
2499 case 4: return BFD_RELOC_X86_64_32S
;
2504 case 1: return BFD_RELOC_8
;
2505 case 2: return BFD_RELOC_16
;
2506 case 4: return BFD_RELOC_32
;
2507 case 8: return BFD_RELOC_64
;
2509 as_bad (_("cannot do %s %u byte relocation"),
2510 sign
> 0 ? "signed" : "unsigned", size
);
2516 /* Here we decide which fixups can be adjusted to make them relative to
2517 the beginning of the section instead of the symbol. Basically we need
2518 to make sure that the dynamic relocations are done correctly, so in
2519 some cases we force the original symbol to be used. */
2522 tc_i386_fix_adjustable (fixS
*fixP ATTRIBUTE_UNUSED
)
2524 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2528 /* Don't adjust pc-relative references to merge sections in 64-bit
2530 if (use_rela_relocations
2531 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
2535 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
2536 and changed later by validate_fix. */
2537 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
2538 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
2541 /* adjust_reloc_syms doesn't know about the GOT. */
2542 if (fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
2543 || fixP
->fx_r_type
== BFD_RELOC_386_PLT32
2544 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
2545 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
2546 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
2547 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
2548 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
2549 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
2550 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
2551 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
2552 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
2553 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTDESC
2554 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_DESC_CALL
2555 || fixP
->fx_r_type
== BFD_RELOC_X86_64_PLT32
2556 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
2557 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
2558 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
2559 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
2560 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
2561 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
2562 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
2563 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
2564 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
2565 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
2566 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPC32_TLSDESC
2567 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSDESC_CALL
2568 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
2569 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
2576 intel_float_operand (const char *mnemonic
)
2578 /* Note that the value returned is meaningful only for opcodes with (memory)
2579 operands, hence the code here is free to improperly handle opcodes that
2580 have no operands (for better performance and smaller code). */
2582 if (mnemonic
[0] != 'f')
2583 return 0; /* non-math */
2585 switch (mnemonic
[1])
2587 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
2588 the fs segment override prefix not currently handled because no
2589 call path can make opcodes without operands get here */
2591 return 2 /* integer op */;
2593 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
2594 return 3; /* fldcw/fldenv */
2597 if (mnemonic
[2] != 'o' /* fnop */)
2598 return 3; /* non-waiting control op */
2601 if (mnemonic
[2] == 's')
2602 return 3; /* frstor/frstpm */
2605 if (mnemonic
[2] == 'a')
2606 return 3; /* fsave */
2607 if (mnemonic
[2] == 't')
2609 switch (mnemonic
[3])
2611 case 'c': /* fstcw */
2612 case 'd': /* fstdw */
2613 case 'e': /* fstenv */
2614 case 's': /* fsts[gw] */
2620 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
2621 return 0; /* fxsave/fxrstor are not really math ops */
2628 /* Build the VEX prefix. */
2631 build_vex_prefix (const insn_template
*t
)
2633 unsigned int register_specifier
;
2634 unsigned int implied_prefix
;
2635 unsigned int vector_length
;
2637 /* Check register specifier. */
2638 if (i
.vex
.register_specifier
)
2640 register_specifier
= i
.vex
.register_specifier
->reg_num
;
2641 if ((i
.vex
.register_specifier
->reg_flags
& RegRex
))
2642 register_specifier
+= 8;
2643 register_specifier
= ~register_specifier
& 0xf;
2646 register_specifier
= 0xf;
2648 /* Use 2-byte VEX prefix by swappping destination and source
2651 && i
.operands
== i
.reg_operands
2652 && i
.tm
.opcode_modifier
.vex0f
2653 && i
.tm
.opcode_modifier
.s
2656 unsigned int xchg
= i
.operands
- 1;
2657 union i386_op temp_op
;
2658 i386_operand_type temp_type
;
2660 temp_type
= i
.types
[xchg
];
2661 i
.types
[xchg
] = i
.types
[0];
2662 i
.types
[0] = temp_type
;
2663 temp_op
= i
.op
[xchg
];
2664 i
.op
[xchg
] = i
.op
[0];
2667 gas_assert (i
.rm
.mode
== 3);
2671 i
.rm
.regmem
= i
.rm
.reg
;
2674 /* Use the next insn. */
2678 vector_length
= i
.tm
.opcode_modifier
.vex256
? 1 : 0;
2680 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
2685 case DATA_PREFIX_OPCODE
:
2688 case REPE_PREFIX_OPCODE
:
2691 case REPNE_PREFIX_OPCODE
:
2698 /* Use 2-byte VEX prefix if possible. */
2699 if (i
.tm
.opcode_modifier
.vex0f
2700 && (i
.rex
& (REX_W
| REX_X
| REX_B
)) == 0)
2702 /* 2-byte VEX prefix. */
2706 i
.vex
.bytes
[0] = 0xc5;
2708 /* Check the REX.R bit. */
2709 r
= (i
.rex
& REX_R
) ? 0 : 1;
2710 i
.vex
.bytes
[1] = (r
<< 7
2711 | register_specifier
<< 3
2712 | vector_length
<< 2
2717 /* 3-byte VEX prefix. */
2720 if (i
.tm
.opcode_modifier
.vex0f
)
2722 else if (i
.tm
.opcode_modifier
.vex0f38
)
2724 else if (i
.tm
.opcode_modifier
.vex0f3a
)
2730 i
.vex
.bytes
[0] = 0xc4;
2732 /* The high 3 bits of the second VEX byte are 1's compliment
2733 of RXB bits from REX. */
2734 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
2736 /* Check the REX.W bit. */
2737 w
= (i
.rex
& REX_W
) ? 1 : 0;
2738 if (i
.tm
.opcode_modifier
.vexw0
|| i
.tm
.opcode_modifier
.vexw1
)
2743 if (i
.tm
.opcode_modifier
.vexw1
)
2747 i
.vex
.bytes
[2] = (w
<< 7
2748 | register_specifier
<< 3
2749 | vector_length
<< 2
2755 process_immext (void)
2759 if (i
.tm
.cpu_flags
.bitfield
.cpusse3
&& i
.operands
> 0)
2761 /* SSE3 Instructions have the fixed operands with an opcode
2762 suffix which is coded in the same place as an 8-bit immediate
2763 field would be. Here we check those operands and remove them
2767 for (x
= 0; x
< i
.operands
; x
++)
2768 if (i
.op
[x
].regs
->reg_num
!= x
)
2769 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
2770 register_prefix
, i
.op
[x
].regs
->reg_name
, x
+ 1,
2776 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
2777 which is coded in the same place as an 8-bit immediate field
2778 would be. Here we fake an 8-bit immediate operand from the
2779 opcode suffix stored in tm.extension_opcode.
2781 AVX instructions also use this encoding, for some of
2782 3 argument instructions. */
2784 gas_assert (i
.imm_operands
== 0
2786 || (i
.tm
.opcode_modifier
.vex
2787 && i
.operands
<= 4)));
2789 exp
= &im_expressions
[i
.imm_operands
++];
2790 i
.op
[i
.operands
].imms
= exp
;
2791 i
.types
[i
.operands
] = imm8
;
2793 exp
->X_op
= O_constant
;
2794 exp
->X_add_number
= i
.tm
.extension_opcode
;
2795 i
.tm
.extension_opcode
= None
;
2798 /* This is the guts of the machine-dependent assembler. LINE points to a
2799 machine dependent instruction. This function is supposed to emit
2800 the frags/bytes it assembles to. */
2803 md_assemble (char *line
)
2806 char mnemonic
[MAX_MNEM_SIZE
];
2807 const insn_template
*t
;
2809 /* Initialize globals. */
2810 memset (&i
, '\0', sizeof (i
));
2811 for (j
= 0; j
< MAX_OPERANDS
; j
++)
2812 i
.reloc
[j
] = NO_RELOC
;
2813 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
2814 memset (im_expressions
, '\0', sizeof (im_expressions
));
2815 save_stack_p
= save_stack
;
2817 /* First parse an instruction mnemonic & call i386_operand for the operands.
2818 We assume that the scrubber has arranged it so that line[0] is the valid
2819 start of a (possibly prefixed) mnemonic. */
2821 line
= parse_insn (line
, mnemonic
);
2825 line
= parse_operands (line
, mnemonic
);
2830 /* Now we've parsed the mnemonic into a set of templates, and have the
2831 operands at hand. */
2833 /* All intel opcodes have reversed operands except for "bound" and
2834 "enter". We also don't reverse intersegment "jmp" and "call"
2835 instructions with 2 immediate operands so that the immediate segment
2836 precedes the offset, as it does when in AT&T mode. */
2839 && (strcmp (mnemonic
, "bound") != 0)
2840 && (strcmp (mnemonic
, "invlpga") != 0)
2841 && !(operand_type_check (i
.types
[0], imm
)
2842 && operand_type_check (i
.types
[1], imm
)))
2845 /* The order of the immediates should be reversed
2846 for 2 immediates extrq and insertq instructions */
2847 if (i
.imm_operands
== 2
2848 && (strcmp (mnemonic
, "extrq") == 0
2849 || strcmp (mnemonic
, "insertq") == 0))
2850 swap_2_operands (0, 1);
2855 /* Don't optimize displacement for movabs since it only takes 64bit
2858 && (flag_code
!= CODE_64BIT
2859 || strcmp (mnemonic
, "movabs") != 0))
2862 /* Next, we find a template that matches the given insn,
2863 making sure the overlap of the given operands types is consistent
2864 with the template operand types. */
2866 if (!(t
= match_template ()))
2869 if (sse_check
!= sse_check_none
2870 && !i
.tm
.opcode_modifier
.noavx
2871 && (i
.tm
.cpu_flags
.bitfield
.cpusse
2872 || i
.tm
.cpu_flags
.bitfield
.cpusse2
2873 || i
.tm
.cpu_flags
.bitfield
.cpusse3
2874 || i
.tm
.cpu_flags
.bitfield
.cpussse3
2875 || i
.tm
.cpu_flags
.bitfield
.cpusse4_1
2876 || i
.tm
.cpu_flags
.bitfield
.cpusse4_2
))
2878 (sse_check
== sse_check_warning
2880 : as_bad
) (_("SSE instruction `%s' is used"), i
.tm
.name
);
2883 /* Zap movzx and movsx suffix. The suffix has been set from
2884 "word ptr" or "byte ptr" on the source operand in Intel syntax
2885 or extracted from mnemonic in AT&T syntax. But we'll use
2886 the destination register to choose the suffix for encoding. */
2887 if ((i
.tm
.base_opcode
& ~9) == 0x0fb6)
2889 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
2890 there is no suffix, the default will be byte extension. */
2891 if (i
.reg_operands
!= 2
2894 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
2899 if (i
.tm
.opcode_modifier
.fwait
)
2900 if (!add_prefix (FWAIT_OPCODE
))
2903 /* Check string instruction segment overrides. */
2904 if (i
.tm
.opcode_modifier
.isstring
&& i
.mem_operands
!= 0)
2906 if (!check_string ())
2908 i
.disp_operands
= 0;
2911 if (!process_suffix ())
2914 /* Update operand types. */
2915 for (j
= 0; j
< i
.operands
; j
++)
2916 i
.types
[j
] = operand_type_and (i
.types
[j
], i
.tm
.operand_types
[j
]);
2918 /* Make still unresolved immediate matches conform to size of immediate
2919 given in i.suffix. */
2920 if (!finalize_imm ())
2923 if (i
.types
[0].bitfield
.imm1
)
2924 i
.imm_operands
= 0; /* kludge for shift insns. */
2926 /* We only need to check those implicit registers for instructions
2927 with 3 operands or less. */
2928 if (i
.operands
<= 3)
2929 for (j
= 0; j
< i
.operands
; j
++)
2930 if (i
.types
[j
].bitfield
.inoutportreg
2931 || i
.types
[j
].bitfield
.shiftcount
2932 || i
.types
[j
].bitfield
.acc
2933 || i
.types
[j
].bitfield
.floatacc
)
2936 /* ImmExt should be processed after SSE2AVX. */
2937 if (!i
.tm
.opcode_modifier
.sse2avx
2938 && i
.tm
.opcode_modifier
.immext
)
2941 /* For insns with operands there are more diddles to do to the opcode. */
2944 if (!process_operands ())
2947 else if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
2949 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
2950 as_warn (_("translating to `%sp'"), i
.tm
.name
);
2953 if (i
.tm
.opcode_modifier
.vex
)
2954 build_vex_prefix (t
);
2956 /* Handle conversion of 'int $3' --> special int3 insn. */
2957 if (i
.tm
.base_opcode
== INT_OPCODE
&& i
.op
[0].imms
->X_add_number
== 3)
2959 i
.tm
.base_opcode
= INT3_OPCODE
;
2963 if ((i
.tm
.opcode_modifier
.jump
2964 || i
.tm
.opcode_modifier
.jumpbyte
2965 || i
.tm
.opcode_modifier
.jumpdword
)
2966 && i
.op
[0].disps
->X_op
== O_constant
)
2968 /* Convert "jmp constant" (and "call constant") to a jump (call) to
2969 the absolute address given by the constant. Since ix86 jumps and
2970 calls are pc relative, we need to generate a reloc. */
2971 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
2972 i
.op
[0].disps
->X_op
= O_symbol
;
2975 if (i
.tm
.opcode_modifier
.rex64
)
2978 /* For 8 bit registers we need an empty rex prefix. Also if the
2979 instruction already has a prefix, we need to convert old
2980 registers to new ones. */
2982 if ((i
.types
[0].bitfield
.reg8
2983 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
2984 || (i
.types
[1].bitfield
.reg8
2985 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
2986 || ((i
.types
[0].bitfield
.reg8
2987 || i
.types
[1].bitfield
.reg8
)
2992 i
.rex
|= REX_OPCODE
;
2993 for (x
= 0; x
< 2; x
++)
2995 /* Look for 8 bit operand that uses old registers. */
2996 if (i
.types
[x
].bitfield
.reg8
2997 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
2999 /* In case it is "hi" register, give up. */
3000 if (i
.op
[x
].regs
->reg_num
> 3)
3001 as_bad (_("can't encode register '%s%s' in an "
3002 "instruction requiring REX prefix."),
3003 register_prefix
, i
.op
[x
].regs
->reg_name
);
3005 /* Otherwise it is equivalent to the extended register.
3006 Since the encoding doesn't change this is merely
3007 cosmetic cleanup for debug output. */
3009 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
3015 add_prefix (REX_OPCODE
| i
.rex
);
3017 /* We are ready to output the insn. */
3022 parse_insn (char *line
, char *mnemonic
)
3025 char *token_start
= l
;
3028 const insn_template
*t
;
3031 /* Non-zero if we found a prefix only acceptable with string insns. */
3032 const char *expecting_string_instruction
= NULL
;
3037 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
3042 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
3044 as_bad (_("no such instruction: `%s'"), token_start
);
3049 if (!is_space_char (*l
)
3050 && *l
!= END_OF_INSN
3052 || (*l
!= PREFIX_SEPARATOR
3055 as_bad (_("invalid character %s in mnemonic"),
3056 output_invalid (*l
));
3059 if (token_start
== l
)
3061 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
3062 as_bad (_("expecting prefix; got nothing"));
3064 as_bad (_("expecting mnemonic; got nothing"));
3068 /* Look up instruction (or prefix) via hash table. */
3069 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
3071 if (*l
!= END_OF_INSN
3072 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
3073 && current_templates
3074 && current_templates
->start
->opcode_modifier
.isprefix
)
3076 if (!cpu_flags_check_cpu64 (current_templates
->start
->cpu_flags
))
3078 as_bad ((flag_code
!= CODE_64BIT
3079 ? _("`%s' is only supported in 64-bit mode")
3080 : _("`%s' is not supported in 64-bit mode")),
3081 current_templates
->start
->name
);
3084 /* If we are in 16-bit mode, do not allow addr16 or data16.
3085 Similarly, in 32-bit mode, do not allow addr32 or data32. */
3086 if ((current_templates
->start
->opcode_modifier
.size16
3087 || current_templates
->start
->opcode_modifier
.size32
)
3088 && flag_code
!= CODE_64BIT
3089 && (current_templates
->start
->opcode_modifier
.size32
3090 ^ (flag_code
== CODE_16BIT
)))
3092 as_bad (_("redundant %s prefix"),
3093 current_templates
->start
->name
);
3096 /* Add prefix, checking for repeated prefixes. */
3097 switch (add_prefix (current_templates
->start
->base_opcode
))
3102 expecting_string_instruction
= current_templates
->start
->name
;
3105 /* Skip past PREFIX_SEPARATOR and reset token_start. */
3112 if (!current_templates
)
3114 /* Check if we should swap operand in encoding. */
3115 if (mnem_p
- 2 == dot_p
&& dot_p
[1] == 's')
3121 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
3124 if (!current_templates
)
3127 /* See if we can get a match by trimming off a suffix. */
3130 case WORD_MNEM_SUFFIX
:
3131 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
3132 i
.suffix
= SHORT_MNEM_SUFFIX
;
3134 case BYTE_MNEM_SUFFIX
:
3135 case QWORD_MNEM_SUFFIX
:
3136 i
.suffix
= mnem_p
[-1];
3138 current_templates
= (const templates
*) hash_find (op_hash
,
3141 case SHORT_MNEM_SUFFIX
:
3142 case LONG_MNEM_SUFFIX
:
3145 i
.suffix
= mnem_p
[-1];
3147 current_templates
= (const templates
*) hash_find (op_hash
,
3156 if (intel_float_operand (mnemonic
) == 1)
3157 i
.suffix
= SHORT_MNEM_SUFFIX
;
3159 i
.suffix
= LONG_MNEM_SUFFIX
;
3161 current_templates
= (const templates
*) hash_find (op_hash
,
3166 if (!current_templates
)
3168 as_bad (_("no such instruction: `%s'"), token_start
);
3173 if (current_templates
->start
->opcode_modifier
.jump
3174 || current_templates
->start
->opcode_modifier
.jumpbyte
)
3176 /* Check for a branch hint. We allow ",pt" and ",pn" for
3177 predict taken and predict not taken respectively.
3178 I'm not sure that branch hints actually do anything on loop
3179 and jcxz insns (JumpByte) for current Pentium4 chips. They
3180 may work in the future and it doesn't hurt to accept them
3182 if (l
[0] == ',' && l
[1] == 'p')
3186 if (!add_prefix (DS_PREFIX_OPCODE
))
3190 else if (l
[2] == 'n')
3192 if (!add_prefix (CS_PREFIX_OPCODE
))
3198 /* Any other comma loses. */
3201 as_bad (_("invalid character %s in mnemonic"),
3202 output_invalid (*l
));
3206 /* Check if instruction is supported on specified architecture. */
3208 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
3210 supported
|= cpu_flags_match (t
);
3211 if (supported
== CPU_FLAGS_PERFECT_MATCH
)
3215 if (!(supported
& CPU_FLAGS_64BIT_MATCH
))
3217 as_bad (flag_code
== CODE_64BIT
3218 ? _("`%s' is not supported in 64-bit mode")
3219 : _("`%s' is only supported in 64-bit mode"),
3220 current_templates
->start
->name
);
3223 if (supported
!= CPU_FLAGS_PERFECT_MATCH
)
3225 as_bad (_("`%s' is not supported on `%s%s'"),
3226 current_templates
->start
->name
,
3227 cpu_arch_name
? cpu_arch_name
: default_arch
,
3228 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
3233 if (!cpu_arch_flags
.bitfield
.cpui386
3234 && (flag_code
!= CODE_16BIT
))
3236 as_warn (_("use .code16 to ensure correct addressing mode"));
3239 /* Check for rep/repne without a string instruction. */
3240 if (expecting_string_instruction
)
3242 static templates override
;
3244 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
3245 if (t
->opcode_modifier
.isstring
)
3247 if (t
>= current_templates
->end
)
3249 as_bad (_("expecting string instruction after `%s'"),
3250 expecting_string_instruction
);
3253 for (override
.start
= t
; t
< current_templates
->end
; ++t
)
3254 if (!t
->opcode_modifier
.isstring
)
3257 current_templates
= &override
;
3264 parse_operands (char *l
, const char *mnemonic
)
3268 /* 1 if operand is pending after ','. */
3269 unsigned int expecting_operand
= 0;
3271 /* Non-zero if operand parens not balanced. */
3272 unsigned int paren_not_balanced
;
3274 while (*l
!= END_OF_INSN
)
3276 /* Skip optional white space before operand. */
3277 if (is_space_char (*l
))
3279 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
)
3281 as_bad (_("invalid character %s before operand %d"),
3282 output_invalid (*l
),
3286 token_start
= l
; /* after white space */
3287 paren_not_balanced
= 0;
3288 while (paren_not_balanced
|| *l
!= ',')
3290 if (*l
== END_OF_INSN
)
3292 if (paren_not_balanced
)
3295 as_bad (_("unbalanced parenthesis in operand %d."),
3298 as_bad (_("unbalanced brackets in operand %d."),
3303 break; /* we are done */
3305 else if (!is_operand_char (*l
) && !is_space_char (*l
))
3307 as_bad (_("invalid character %s in operand %d"),
3308 output_invalid (*l
),
3315 ++paren_not_balanced
;
3317 --paren_not_balanced
;
3322 ++paren_not_balanced
;
3324 --paren_not_balanced
;
3328 if (l
!= token_start
)
3329 { /* Yes, we've read in another operand. */
3330 unsigned int operand_ok
;
3331 this_operand
= i
.operands
++;
3332 i
.types
[this_operand
].bitfield
.unspecified
= 1;
3333 if (i
.operands
> MAX_OPERANDS
)
3335 as_bad (_("spurious operands; (%d operands/instruction max)"),
3339 /* Now parse operand adding info to 'i' as we go along. */
3340 END_STRING_AND_SAVE (l
);
3344 i386_intel_operand (token_start
,
3345 intel_float_operand (mnemonic
));
3347 operand_ok
= i386_att_operand (token_start
);
3349 RESTORE_END_STRING (l
);
3355 if (expecting_operand
)
3357 expecting_operand_after_comma
:
3358 as_bad (_("expecting operand after ','; got nothing"));
3363 as_bad (_("expecting operand before ','; got nothing"));
3368 /* Now *l must be either ',' or END_OF_INSN. */
3371 if (*++l
== END_OF_INSN
)
3373 /* Just skip it, if it's \n complain. */
3374 goto expecting_operand_after_comma
;
3376 expecting_operand
= 1;
3383 swap_2_operands (int xchg1
, int xchg2
)
3385 union i386_op temp_op
;
3386 i386_operand_type temp_type
;
3387 enum bfd_reloc_code_real temp_reloc
;
3389 temp_type
= i
.types
[xchg2
];
3390 i
.types
[xchg2
] = i
.types
[xchg1
];
3391 i
.types
[xchg1
] = temp_type
;
3392 temp_op
= i
.op
[xchg2
];
3393 i
.op
[xchg2
] = i
.op
[xchg1
];
3394 i
.op
[xchg1
] = temp_op
;
3395 temp_reloc
= i
.reloc
[xchg2
];
3396 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
3397 i
.reloc
[xchg1
] = temp_reloc
;
3401 swap_operands (void)
3407 swap_2_operands (1, i
.operands
- 2);
3410 swap_2_operands (0, i
.operands
- 1);
3416 if (i
.mem_operands
== 2)
3418 const seg_entry
*temp_seg
;
3419 temp_seg
= i
.seg
[0];
3420 i
.seg
[0] = i
.seg
[1];
3421 i
.seg
[1] = temp_seg
;
3425 /* Try to ensure constant immediates are represented in the smallest
3430 char guess_suffix
= 0;
3434 guess_suffix
= i
.suffix
;
3435 else if (i
.reg_operands
)
3437 /* Figure out a suffix from the last register operand specified.
3438 We can't do this properly yet, ie. excluding InOutPortReg,
3439 but the following works for instructions with immediates.
3440 In any case, we can't set i.suffix yet. */
3441 for (op
= i
.operands
; --op
>= 0;)
3442 if (i
.types
[op
].bitfield
.reg8
)
3444 guess_suffix
= BYTE_MNEM_SUFFIX
;
3447 else if (i
.types
[op
].bitfield
.reg16
)
3449 guess_suffix
= WORD_MNEM_SUFFIX
;
3452 else if (i
.types
[op
].bitfield
.reg32
)
3454 guess_suffix
= LONG_MNEM_SUFFIX
;
3457 else if (i
.types
[op
].bitfield
.reg64
)
3459 guess_suffix
= QWORD_MNEM_SUFFIX
;
3463 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
3464 guess_suffix
= WORD_MNEM_SUFFIX
;
3466 for (op
= i
.operands
; --op
>= 0;)
3467 if (operand_type_check (i
.types
[op
], imm
))
3469 switch (i
.op
[op
].imms
->X_op
)
3472 /* If a suffix is given, this operand may be shortened. */
3473 switch (guess_suffix
)
3475 case LONG_MNEM_SUFFIX
:
3476 i
.types
[op
].bitfield
.imm32
= 1;
3477 i
.types
[op
].bitfield
.imm64
= 1;
3479 case WORD_MNEM_SUFFIX
:
3480 i
.types
[op
].bitfield
.imm16
= 1;
3481 i
.types
[op
].bitfield
.imm32
= 1;
3482 i
.types
[op
].bitfield
.imm32s
= 1;
3483 i
.types
[op
].bitfield
.imm64
= 1;
3485 case BYTE_MNEM_SUFFIX
:
3486 i
.types
[op
].bitfield
.imm8
= 1;
3487 i
.types
[op
].bitfield
.imm8s
= 1;
3488 i
.types
[op
].bitfield
.imm16
= 1;
3489 i
.types
[op
].bitfield
.imm32
= 1;
3490 i
.types
[op
].bitfield
.imm32s
= 1;
3491 i
.types
[op
].bitfield
.imm64
= 1;
3495 /* If this operand is at most 16 bits, convert it
3496 to a signed 16 bit number before trying to see
3497 whether it will fit in an even smaller size.
3498 This allows a 16-bit operand such as $0xffe0 to
3499 be recognised as within Imm8S range. */
3500 if ((i
.types
[op
].bitfield
.imm16
)
3501 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
3503 i
.op
[op
].imms
->X_add_number
=
3504 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
3506 if ((i
.types
[op
].bitfield
.imm32
)
3507 && ((i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1))
3510 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
3511 ^ ((offsetT
) 1 << 31))
3512 - ((offsetT
) 1 << 31));
3515 = operand_type_or (i
.types
[op
],
3516 smallest_imm_type (i
.op
[op
].imms
->X_add_number
));
3518 /* We must avoid matching of Imm32 templates when 64bit
3519 only immediate is available. */
3520 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
3521 i
.types
[op
].bitfield
.imm32
= 0;
3528 /* Symbols and expressions. */
3530 /* Convert symbolic operand to proper sizes for matching, but don't
3531 prevent matching a set of insns that only supports sizes other
3532 than those matching the insn suffix. */
3534 i386_operand_type mask
, allowed
;
3535 const insn_template
*t
;
3537 operand_type_set (&mask
, 0);
3538 operand_type_set (&allowed
, 0);
3540 for (t
= current_templates
->start
;
3541 t
< current_templates
->end
;
3543 allowed
= operand_type_or (allowed
,
3544 t
->operand_types
[op
]);
3545 switch (guess_suffix
)
3547 case QWORD_MNEM_SUFFIX
:
3548 mask
.bitfield
.imm64
= 1;
3549 mask
.bitfield
.imm32s
= 1;
3551 case LONG_MNEM_SUFFIX
:
3552 mask
.bitfield
.imm32
= 1;
3554 case WORD_MNEM_SUFFIX
:
3555 mask
.bitfield
.imm16
= 1;
3557 case BYTE_MNEM_SUFFIX
:
3558 mask
.bitfield
.imm8
= 1;
3563 allowed
= operand_type_and (mask
, allowed
);
3564 if (!operand_type_all_zero (&allowed
))
3565 i
.types
[op
] = operand_type_and (i
.types
[op
], mask
);
3572 /* Try to use the smallest displacement type too. */
3574 optimize_disp (void)
3578 for (op
= i
.operands
; --op
>= 0;)
3579 if (operand_type_check (i
.types
[op
], disp
))
3581 if (i
.op
[op
].disps
->X_op
== O_constant
)
3583 offsetT disp
= i
.op
[op
].disps
->X_add_number
;
3585 if (i
.types
[op
].bitfield
.disp16
3586 && (disp
& ~(offsetT
) 0xffff) == 0)
3588 /* If this operand is at most 16 bits, convert
3589 to a signed 16 bit number and don't use 64bit
3591 disp
= (((disp
& 0xffff) ^ 0x8000) - 0x8000);
3592 i
.types
[op
].bitfield
.disp64
= 0;
3594 if (i
.types
[op
].bitfield
.disp32
3595 && (disp
& ~(((offsetT
) 2 << 31) - 1)) == 0)
3597 /* If this operand is at most 32 bits, convert
3598 to a signed 32 bit number and don't use 64bit
3600 disp
&= (((offsetT
) 2 << 31) - 1);
3601 disp
= (disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
3602 i
.types
[op
].bitfield
.disp64
= 0;
3604 if (!disp
&& i
.types
[op
].bitfield
.baseindex
)
3606 i
.types
[op
].bitfield
.disp8
= 0;
3607 i
.types
[op
].bitfield
.disp16
= 0;
3608 i
.types
[op
].bitfield
.disp32
= 0;
3609 i
.types
[op
].bitfield
.disp32s
= 0;
3610 i
.types
[op
].bitfield
.disp64
= 0;
3614 else if (flag_code
== CODE_64BIT
)
3616 if (fits_in_signed_long (disp
))
3618 i
.types
[op
].bitfield
.disp64
= 0;
3619 i
.types
[op
].bitfield
.disp32s
= 1;
3621 if (i
.prefix
[ADDR_PREFIX
]
3622 && fits_in_unsigned_long (disp
))
3623 i
.types
[op
].bitfield
.disp32
= 1;
3625 if ((i
.types
[op
].bitfield
.disp32
3626 || i
.types
[op
].bitfield
.disp32s
3627 || i
.types
[op
].bitfield
.disp16
)
3628 && fits_in_signed_byte (disp
))
3629 i
.types
[op
].bitfield
.disp8
= 1;
3631 else if (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
3632 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
)
3634 fix_new_exp (frag_now
, frag_more (0) - frag_now
->fr_literal
, 0,
3635 i
.op
[op
].disps
, 0, i
.reloc
[op
]);
3636 i
.types
[op
].bitfield
.disp8
= 0;
3637 i
.types
[op
].bitfield
.disp16
= 0;
3638 i
.types
[op
].bitfield
.disp32
= 0;
3639 i
.types
[op
].bitfield
.disp32s
= 0;
3640 i
.types
[op
].bitfield
.disp64
= 0;
3643 /* We only support 64bit displacement on constants. */
3644 i
.types
[op
].bitfield
.disp64
= 0;
3648 static const insn_template
*
3649 match_template (void)
3651 /* Points to template once we've found it. */
3652 const insn_template
*t
;
3653 i386_operand_type overlap0
, overlap1
, overlap2
, overlap3
;
3654 i386_operand_type overlap4
;
3655 unsigned int found_reverse_match
;
3656 i386_opcode_modifier suffix_check
;
3657 i386_operand_type operand_types
[MAX_OPERANDS
];
3658 int addr_prefix_disp
;
3660 unsigned int found_cpu_match
;
3661 unsigned int check_register
;
3663 #if MAX_OPERANDS != 5
3664 # error "MAX_OPERANDS must be 5."
3667 found_reverse_match
= 0;
3668 addr_prefix_disp
= -1;
3670 memset (&suffix_check
, 0, sizeof (suffix_check
));
3671 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
3672 suffix_check
.no_bsuf
= 1;
3673 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
3674 suffix_check
.no_wsuf
= 1;
3675 else if (i
.suffix
== SHORT_MNEM_SUFFIX
)
3676 suffix_check
.no_ssuf
= 1;
3677 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
3678 suffix_check
.no_lsuf
= 1;
3679 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
3680 suffix_check
.no_qsuf
= 1;
3681 else if (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
)
3682 suffix_check
.no_ldsuf
= 1;
3684 for (t
= current_templates
->start
; t
< current_templates
->end
; t
++)
3686 addr_prefix_disp
= -1;
3688 /* Must have right number of operands. */
3689 if (i
.operands
!= t
->operands
)
3692 /* Check processor support. */
3693 found_cpu_match
= (cpu_flags_match (t
)
3694 == CPU_FLAGS_PERFECT_MATCH
);
3695 if (!found_cpu_match
)
3698 /* Check old gcc support. */
3699 if (!old_gcc
&& t
->opcode_modifier
.oldgcc
)
3702 /* Check AT&T mnemonic. */
3703 if (intel_mnemonic
&& t
->opcode_modifier
.attmnemonic
)
3706 /* Check AT&T syntax Intel syntax. */
3707 if ((intel_syntax
&& t
->opcode_modifier
.attsyntax
)
3708 || (!intel_syntax
&& t
->opcode_modifier
.intelsyntax
))
3711 /* Check the suffix, except for some instructions in intel mode. */
3712 if ((!intel_syntax
|| !t
->opcode_modifier
.ignoresize
)
3713 && ((t
->opcode_modifier
.no_bsuf
&& suffix_check
.no_bsuf
)
3714 || (t
->opcode_modifier
.no_wsuf
&& suffix_check
.no_wsuf
)
3715 || (t
->opcode_modifier
.no_lsuf
&& suffix_check
.no_lsuf
)
3716 || (t
->opcode_modifier
.no_ssuf
&& suffix_check
.no_ssuf
)
3717 || (t
->opcode_modifier
.no_qsuf
&& suffix_check
.no_qsuf
)
3718 || (t
->opcode_modifier
.no_ldsuf
&& suffix_check
.no_ldsuf
)))
3721 if (!operand_size_match (t
))
3724 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3725 operand_types
[j
] = t
->operand_types
[j
];
3727 /* In general, don't allow 64-bit operands in 32-bit mode. */
3728 if (i
.suffix
== QWORD_MNEM_SUFFIX
3729 && flag_code
!= CODE_64BIT
3731 ? (!t
->opcode_modifier
.ignoresize
3732 && !intel_float_operand (t
->name
))
3733 : intel_float_operand (t
->name
) != 2)
3734 && ((!operand_types
[0].bitfield
.regmmx
3735 && !operand_types
[0].bitfield
.regxmm
3736 && !operand_types
[0].bitfield
.regymm
)
3737 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
3738 && !!operand_types
[t
->operands
> 1].bitfield
.regxmm
3739 && !!operand_types
[t
->operands
> 1].bitfield
.regymm
))
3740 && (t
->base_opcode
!= 0x0fc7
3741 || t
->extension_opcode
!= 1 /* cmpxchg8b */))
3744 /* In general, don't allow 32-bit operands on pre-386. */
3745 else if (i
.suffix
== LONG_MNEM_SUFFIX
3746 && !cpu_arch_flags
.bitfield
.cpui386
3748 ? (!t
->opcode_modifier
.ignoresize
3749 && !intel_float_operand (t
->name
))
3750 : intel_float_operand (t
->name
) != 2)
3751 && ((!operand_types
[0].bitfield
.regmmx
3752 && !operand_types
[0].bitfield
.regxmm
)
3753 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
3754 && !!operand_types
[t
->operands
> 1].bitfield
.regxmm
)))
3757 /* Do not verify operands when there are none. */
3761 /* We've found a match; break out of loop. */
3765 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
3766 into Disp32/Disp16/Disp32 operand. */
3767 if (i
.prefix
[ADDR_PREFIX
] != 0)
3769 /* There should be only one Disp operand. */
3773 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3775 if (operand_types
[j
].bitfield
.disp16
)
3777 addr_prefix_disp
= j
;
3778 operand_types
[j
].bitfield
.disp32
= 1;
3779 operand_types
[j
].bitfield
.disp16
= 0;
3785 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3787 if (operand_types
[j
].bitfield
.disp32
)
3789 addr_prefix_disp
= j
;
3790 operand_types
[j
].bitfield
.disp32
= 0;
3791 operand_types
[j
].bitfield
.disp16
= 1;
3797 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3799 if (operand_types
[j
].bitfield
.disp64
)
3801 addr_prefix_disp
= j
;
3802 operand_types
[j
].bitfield
.disp64
= 0;
3803 operand_types
[j
].bitfield
.disp32
= 1;
3811 /* We check register size only if size of operands can be
3812 encoded the canonical way. */
3813 check_register
= t
->opcode_modifier
.w
;
3814 overlap0
= operand_type_and (i
.types
[0], operand_types
[0]);
3815 switch (t
->operands
)
3818 if (!operand_type_match (overlap0
, i
.types
[0]))
3822 /* xchg %eax, %eax is a special case. It is an aliase for nop
3823 only in 32bit mode and we can use opcode 0x90. In 64bit
3824 mode, we can't use 0x90 for xchg %eax, %eax since it should
3825 zero-extend %eax to %rax. */
3826 if (flag_code
== CODE_64BIT
3827 && t
->base_opcode
== 0x90
3828 && operand_type_equal (&i
.types
[0], &acc32
)
3829 && operand_type_equal (&i
.types
[1], &acc32
))
3833 /* If we swap operand in encoding, we either match
3834 the next one or reverse direction of operands. */
3835 if (t
->opcode_modifier
.s
)
3837 else if (t
->opcode_modifier
.d
)
3842 /* If we swap operand in encoding, we match the next one. */
3843 if (i
.swap_operand
&& t
->opcode_modifier
.s
)
3847 overlap1
= operand_type_and (i
.types
[1], operand_types
[1]);
3848 if (!operand_type_match (overlap0
, i
.types
[0])
3849 || !operand_type_match (overlap1
, i
.types
[1])
3851 && !operand_type_register_match (overlap0
, i
.types
[0],
3853 overlap1
, i
.types
[1],
3856 /* Check if other direction is valid ... */
3857 if (!t
->opcode_modifier
.d
&& !t
->opcode_modifier
.floatd
)
3861 /* Try reversing direction of operands. */
3862 overlap0
= operand_type_and (i
.types
[0], operand_types
[1]);
3863 overlap1
= operand_type_and (i
.types
[1], operand_types
[0]);
3864 if (!operand_type_match (overlap0
, i
.types
[0])
3865 || !operand_type_match (overlap1
, i
.types
[1])
3867 && !operand_type_register_match (overlap0
,
3874 /* Does not match either direction. */
3877 /* found_reverse_match holds which of D or FloatDR
3879 if (t
->opcode_modifier
.d
)
3880 found_reverse_match
= Opcode_D
;
3881 else if (t
->opcode_modifier
.floatd
)
3882 found_reverse_match
= Opcode_FloatD
;
3884 found_reverse_match
= 0;
3885 if (t
->opcode_modifier
.floatr
)
3886 found_reverse_match
|= Opcode_FloatR
;
3890 /* Found a forward 2 operand match here. */
3891 switch (t
->operands
)
3894 overlap4
= operand_type_and (i
.types
[4],
3897 overlap3
= operand_type_and (i
.types
[3],
3900 overlap2
= operand_type_and (i
.types
[2],
3905 switch (t
->operands
)
3908 if (!operand_type_match (overlap4
, i
.types
[4])
3909 || !operand_type_register_match (overlap3
,
3917 if (!operand_type_match (overlap3
, i
.types
[3])
3919 && !operand_type_register_match (overlap2
,
3927 /* Here we make use of the fact that there are no
3928 reverse match 3 operand instructions, and all 3
3929 operand instructions only need to be checked for
3930 register consistency between operands 2 and 3. */
3931 if (!operand_type_match (overlap2
, i
.types
[2])
3933 && !operand_type_register_match (overlap1
,
3943 /* Found either forward/reverse 2, 3 or 4 operand match here:
3944 slip through to break. */
3946 if (!found_cpu_match
)
3948 found_reverse_match
= 0;
3952 /* We've found a match; break out of loop. */
3956 if (t
== current_templates
->end
)
3958 /* We found no match. */
3960 as_bad (_("ambiguous operand size or operands invalid for `%s'"),
3961 current_templates
->start
->name
);
3963 as_bad (_("suffix or operands invalid for `%s'"),
3964 current_templates
->start
->name
);
3968 if (!quiet_warnings
)
3971 && (i
.types
[0].bitfield
.jumpabsolute
3972 != operand_types
[0].bitfield
.jumpabsolute
))
3974 as_warn (_("indirect %s without `*'"), t
->name
);
3977 if (t
->opcode_modifier
.isprefix
3978 && t
->opcode_modifier
.ignoresize
)
3980 /* Warn them that a data or address size prefix doesn't
3981 affect assembly of the next line of code. */
3982 as_warn (_("stand-alone `%s' prefix"), t
->name
);
3986 /* Copy the template we found. */
3989 if (addr_prefix_disp
!= -1)
3990 i
.tm
.operand_types
[addr_prefix_disp
]
3991 = operand_types
[addr_prefix_disp
];
3993 if (found_reverse_match
)
3995 /* If we found a reverse match we must alter the opcode
3996 direction bit. found_reverse_match holds bits to change
3997 (different for int & float insns). */
3999 i
.tm
.base_opcode
^= found_reverse_match
;
4001 i
.tm
.operand_types
[0] = operand_types
[1];
4002 i
.tm
.operand_types
[1] = operand_types
[0];
4011 int mem_op
= operand_type_check (i
.types
[0], anymem
) ? 0 : 1;
4012 if (i
.tm
.operand_types
[mem_op
].bitfield
.esseg
)
4014 if (i
.seg
[0] != NULL
&& i
.seg
[0] != &es
)
4016 as_bad (_("`%s' operand %d must use `%ses' segment"),
4022 /* There's only ever one segment override allowed per instruction.
4023 This instruction possibly has a legal segment override on the
4024 second operand, so copy the segment to where non-string
4025 instructions store it, allowing common code. */
4026 i
.seg
[0] = i
.seg
[1];
4028 else if (i
.tm
.operand_types
[mem_op
+ 1].bitfield
.esseg
)
4030 if (i
.seg
[1] != NULL
&& i
.seg
[1] != &es
)
4032 as_bad (_("`%s' operand %d must use `%ses' segment"),
4043 process_suffix (void)
4045 /* If matched instruction specifies an explicit instruction mnemonic
4047 if (i
.tm
.opcode_modifier
.size16
)
4048 i
.suffix
= WORD_MNEM_SUFFIX
;
4049 else if (i
.tm
.opcode_modifier
.size32
)
4050 i
.suffix
= LONG_MNEM_SUFFIX
;
4051 else if (i
.tm
.opcode_modifier
.size64
)
4052 i
.suffix
= QWORD_MNEM_SUFFIX
;
4053 else if (i
.reg_operands
)
4055 /* If there's no instruction mnemonic suffix we try to invent one
4056 based on register operands. */
4059 /* We take i.suffix from the last register operand specified,
4060 Destination register type is more significant than source
4061 register type. crc32 in SSE4.2 prefers source register
4063 if (i
.tm
.base_opcode
== 0xf20f38f1)
4065 if (i
.types
[0].bitfield
.reg16
)
4066 i
.suffix
= WORD_MNEM_SUFFIX
;
4067 else if (i
.types
[0].bitfield
.reg32
)
4068 i
.suffix
= LONG_MNEM_SUFFIX
;
4069 else if (i
.types
[0].bitfield
.reg64
)
4070 i
.suffix
= QWORD_MNEM_SUFFIX
;
4072 else if (i
.tm
.base_opcode
== 0xf20f38f0)
4074 if (i
.types
[0].bitfield
.reg8
)
4075 i
.suffix
= BYTE_MNEM_SUFFIX
;
4082 if (i
.tm
.base_opcode
== 0xf20f38f1
4083 || i
.tm
.base_opcode
== 0xf20f38f0)
4085 /* We have to know the operand size for crc32. */
4086 as_bad (_("ambiguous memory operand size for `%s`"),
4091 for (op
= i
.operands
; --op
>= 0;)
4092 if (!i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
4094 if (i
.types
[op
].bitfield
.reg8
)
4096 i
.suffix
= BYTE_MNEM_SUFFIX
;
4099 else if (i
.types
[op
].bitfield
.reg16
)
4101 i
.suffix
= WORD_MNEM_SUFFIX
;
4104 else if (i
.types
[op
].bitfield
.reg32
)
4106 i
.suffix
= LONG_MNEM_SUFFIX
;
4109 else if (i
.types
[op
].bitfield
.reg64
)
4111 i
.suffix
= QWORD_MNEM_SUFFIX
;
4117 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
4119 if (!check_byte_reg ())
4122 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
4124 if (!check_long_reg ())
4127 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
4130 && i
.tm
.opcode_modifier
.ignoresize
4131 && i
.tm
.opcode_modifier
.no_qsuf
)
4133 else if (!check_qword_reg ())
4136 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
4138 if (!check_word_reg ())
4141 else if (i
.suffix
== XMMWORD_MNEM_SUFFIX
4142 || i
.suffix
== YMMWORD_MNEM_SUFFIX
)
4144 /* Skip if the instruction has x/y suffix. match_template
4145 should check if it is a valid suffix. */
4147 else if (intel_syntax
&& i
.tm
.opcode_modifier
.ignoresize
)
4148 /* Do nothing if the instruction is going to ignore the prefix. */
4153 else if (i
.tm
.opcode_modifier
.defaultsize
4155 /* exclude fldenv/frstor/fsave/fstenv */
4156 && i
.tm
.opcode_modifier
.no_ssuf
)
4158 i
.suffix
= stackop_size
;
4160 else if (intel_syntax
4162 && (i
.tm
.operand_types
[0].bitfield
.jumpabsolute
4163 || i
.tm
.opcode_modifier
.jumpbyte
4164 || i
.tm
.opcode_modifier
.jumpintersegment
4165 || (i
.tm
.base_opcode
== 0x0f01 /* [ls][gi]dt */
4166 && i
.tm
.extension_opcode
<= 3)))
4171 if (!i
.tm
.opcode_modifier
.no_qsuf
)
4173 i
.suffix
= QWORD_MNEM_SUFFIX
;
4177 if (!i
.tm
.opcode_modifier
.no_lsuf
)
4178 i
.suffix
= LONG_MNEM_SUFFIX
;
4181 if (!i
.tm
.opcode_modifier
.no_wsuf
)
4182 i
.suffix
= WORD_MNEM_SUFFIX
;
4191 if (i
.tm
.opcode_modifier
.w
)
4193 as_bad (_("no instruction mnemonic suffix given and "
4194 "no register operands; can't size instruction"));
4200 unsigned int suffixes
;
4202 suffixes
= !i
.tm
.opcode_modifier
.no_bsuf
;
4203 if (!i
.tm
.opcode_modifier
.no_wsuf
)
4205 if (!i
.tm
.opcode_modifier
.no_lsuf
)
4207 if (!i
.tm
.opcode_modifier
.no_ldsuf
)
4209 if (!i
.tm
.opcode_modifier
.no_ssuf
)
4211 if (!i
.tm
.opcode_modifier
.no_qsuf
)
4214 /* There are more than suffix matches. */
4215 if (i
.tm
.opcode_modifier
.w
4216 || ((suffixes
& (suffixes
- 1))
4217 && !i
.tm
.opcode_modifier
.defaultsize
4218 && !i
.tm
.opcode_modifier
.ignoresize
))
4220 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
4226 /* Change the opcode based on the operand size given by i.suffix;
4227 We don't need to change things for byte insns. */
4230 && i
.suffix
!= BYTE_MNEM_SUFFIX
4231 && i
.suffix
!= XMMWORD_MNEM_SUFFIX
4232 && i
.suffix
!= YMMWORD_MNEM_SUFFIX
)
4234 /* It's not a byte, select word/dword operation. */
4235 if (i
.tm
.opcode_modifier
.w
)
4237 if (i
.tm
.opcode_modifier
.shortform
)
4238 i
.tm
.base_opcode
|= 8;
4240 i
.tm
.base_opcode
|= 1;
4243 /* Now select between word & dword operations via the operand
4244 size prefix, except for instructions that will ignore this
4246 if (i
.tm
.opcode_modifier
.addrprefixop0
)
4248 /* The address size override prefix changes the size of the
4250 if ((flag_code
== CODE_32BIT
4251 && i
.op
->regs
[0].reg_type
.bitfield
.reg16
)
4252 || (flag_code
!= CODE_32BIT
4253 && i
.op
->regs
[0].reg_type
.bitfield
.reg32
))
4254 if (!add_prefix (ADDR_PREFIX_OPCODE
))
4257 else if (i
.suffix
!= QWORD_MNEM_SUFFIX
4258 && i
.suffix
!= LONG_DOUBLE_MNEM_SUFFIX
4259 && !i
.tm
.opcode_modifier
.ignoresize
4260 && !i
.tm
.opcode_modifier
.floatmf
4261 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
4262 || (flag_code
== CODE_64BIT
4263 && i
.tm
.opcode_modifier
.jumpbyte
)))
4265 unsigned int prefix
= DATA_PREFIX_OPCODE
;
4267 if (i
.tm
.opcode_modifier
.jumpbyte
) /* jcxz, loop */
4268 prefix
= ADDR_PREFIX_OPCODE
;
4270 if (!add_prefix (prefix
))
4274 /* Set mode64 for an operand. */
4275 if (i
.suffix
== QWORD_MNEM_SUFFIX
4276 && flag_code
== CODE_64BIT
4277 && !i
.tm
.opcode_modifier
.norex64
)
4279 /* Special case for xchg %rax,%rax. It is NOP and doesn't
4280 need rex64. cmpxchg8b is also a special case. */
4281 if (! (i
.operands
== 2
4282 && i
.tm
.base_opcode
== 0x90
4283 && i
.tm
.extension_opcode
== None
4284 && operand_type_equal (&i
.types
[0], &acc64
)
4285 && operand_type_equal (&i
.types
[1], &acc64
))
4286 && ! (i
.operands
== 1
4287 && i
.tm
.base_opcode
== 0xfc7
4288 && i
.tm
.extension_opcode
== 1
4289 && !operand_type_check (i
.types
[0], reg
)
4290 && operand_type_check (i
.types
[0], anymem
)))
4294 /* Size floating point instruction. */
4295 if (i
.suffix
== LONG_MNEM_SUFFIX
)
4296 if (i
.tm
.opcode_modifier
.floatmf
)
4297 i
.tm
.base_opcode
^= 4;
4304 check_byte_reg (void)
4308 for (op
= i
.operands
; --op
>= 0;)
4310 /* If this is an eight bit register, it's OK. If it's the 16 or
4311 32 bit version of an eight bit register, we will just use the
4312 low portion, and that's OK too. */
4313 if (i
.types
[op
].bitfield
.reg8
)
4316 /* Don't generate this warning if not needed. */
4317 if (intel_syntax
&& i
.tm
.opcode_modifier
.byteokintel
)
4320 /* crc32 doesn't generate this warning. */
4321 if (i
.tm
.base_opcode
== 0xf20f38f0)
4324 if ((i
.types
[op
].bitfield
.reg16
4325 || i
.types
[op
].bitfield
.reg32
4326 || i
.types
[op
].bitfield
.reg64
)
4327 && i
.op
[op
].regs
->reg_num
< 4)
4329 /* Prohibit these changes in the 64bit mode, since the
4330 lowering is more complicated. */
4331 if (flag_code
== CODE_64BIT
4332 && !i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
4334 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4335 register_prefix
, i
.op
[op
].regs
->reg_name
,
4339 #if REGISTER_WARNINGS
4341 && !i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
4342 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4344 (i
.op
[op
].regs
+ (i
.types
[op
].bitfield
.reg16
4345 ? REGNAM_AL
- REGNAM_AX
4346 : REGNAM_AL
- REGNAM_EAX
))->reg_name
,
4348 i
.op
[op
].regs
->reg_name
,
4353 /* Any other register is bad. */
4354 if (i
.types
[op
].bitfield
.reg16
4355 || i
.types
[op
].bitfield
.reg32
4356 || i
.types
[op
].bitfield
.reg64
4357 || i
.types
[op
].bitfield
.regmmx
4358 || i
.types
[op
].bitfield
.regxmm
4359 || i
.types
[op
].bitfield
.regymm
4360 || i
.types
[op
].bitfield
.sreg2
4361 || i
.types
[op
].bitfield
.sreg3
4362 || i
.types
[op
].bitfield
.control
4363 || i
.types
[op
].bitfield
.debug
4364 || i
.types
[op
].bitfield
.test
4365 || i
.types
[op
].bitfield
.floatreg
4366 || i
.types
[op
].bitfield
.floatacc
)
4368 as_bad (_("`%s%s' not allowed with `%s%c'"),
4370 i
.op
[op
].regs
->reg_name
,
4380 check_long_reg (void)
4384 for (op
= i
.operands
; --op
>= 0;)
4385 /* Reject eight bit registers, except where the template requires
4386 them. (eg. movzb) */
4387 if (i
.types
[op
].bitfield
.reg8
4388 && (i
.tm
.operand_types
[op
].bitfield
.reg16
4389 || i
.tm
.operand_types
[op
].bitfield
.reg32
4390 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4392 as_bad (_("`%s%s' not allowed with `%s%c'"),
4394 i
.op
[op
].regs
->reg_name
,
4399 /* Warn if the e prefix on a general reg is missing. */
4400 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
4401 && i
.types
[op
].bitfield
.reg16
4402 && (i
.tm
.operand_types
[op
].bitfield
.reg32
4403 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4405 /* Prohibit these changes in the 64bit mode, since the
4406 lowering is more complicated. */
4407 if (flag_code
== CODE_64BIT
)
4409 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4410 register_prefix
, i
.op
[op
].regs
->reg_name
,
4414 #if REGISTER_WARNINGS
4416 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4418 (i
.op
[op
].regs
+ REGNAM_EAX
- REGNAM_AX
)->reg_name
,
4420 i
.op
[op
].regs
->reg_name
,
4424 /* Warn if the r prefix on a general reg is missing. */
4425 else if (i
.types
[op
].bitfield
.reg64
4426 && (i
.tm
.operand_types
[op
].bitfield
.reg32
4427 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4430 && i
.tm
.opcode_modifier
.toqword
4431 && !i
.types
[0].bitfield
.regxmm
)
4433 /* Convert to QWORD. We want REX byte. */
4434 i
.suffix
= QWORD_MNEM_SUFFIX
;
4438 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4439 register_prefix
, i
.op
[op
].regs
->reg_name
,
4448 check_qword_reg (void)
4452 for (op
= i
.operands
; --op
>= 0; )
4453 /* Reject eight bit registers, except where the template requires
4454 them. (eg. movzb) */
4455 if (i
.types
[op
].bitfield
.reg8
4456 && (i
.tm
.operand_types
[op
].bitfield
.reg16
4457 || i
.tm
.operand_types
[op
].bitfield
.reg32
4458 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4460 as_bad (_("`%s%s' not allowed with `%s%c'"),
4462 i
.op
[op
].regs
->reg_name
,
4467 /* Warn if the e prefix on a general reg is missing. */
4468 else if ((i
.types
[op
].bitfield
.reg16
4469 || i
.types
[op
].bitfield
.reg32
)
4470 && (i
.tm
.operand_types
[op
].bitfield
.reg32
4471 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4473 /* Prohibit these changes in the 64bit mode, since the
4474 lowering is more complicated. */
4476 && i
.tm
.opcode_modifier
.todword
4477 && !i
.types
[0].bitfield
.regxmm
)
4479 /* Convert to DWORD. We don't want REX byte. */
4480 i
.suffix
= LONG_MNEM_SUFFIX
;
4484 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4485 register_prefix
, i
.op
[op
].regs
->reg_name
,
4494 check_word_reg (void)
4497 for (op
= i
.operands
; --op
>= 0;)
4498 /* Reject eight bit registers, except where the template requires
4499 them. (eg. movzb) */
4500 if (i
.types
[op
].bitfield
.reg8
4501 && (i
.tm
.operand_types
[op
].bitfield
.reg16
4502 || i
.tm
.operand_types
[op
].bitfield
.reg32
4503 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4505 as_bad (_("`%s%s' not allowed with `%s%c'"),
4507 i
.op
[op
].regs
->reg_name
,
4512 /* Warn if the e prefix on a general reg is present. */
4513 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
4514 && i
.types
[op
].bitfield
.reg32
4515 && (i
.tm
.operand_types
[op
].bitfield
.reg16
4516 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4518 /* Prohibit these changes in the 64bit mode, since the
4519 lowering is more complicated. */
4520 if (flag_code
== CODE_64BIT
)
4522 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4523 register_prefix
, i
.op
[op
].regs
->reg_name
,
4528 #if REGISTER_WARNINGS
4529 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4531 (i
.op
[op
].regs
+ REGNAM_AX
- REGNAM_EAX
)->reg_name
,
4533 i
.op
[op
].regs
->reg_name
,
4541 update_imm (unsigned int j
)
4543 i386_operand_type overlap
= i
.types
[j
];
4544 if ((overlap
.bitfield
.imm8
4545 || overlap
.bitfield
.imm8s
4546 || overlap
.bitfield
.imm16
4547 || overlap
.bitfield
.imm32
4548 || overlap
.bitfield
.imm32s
4549 || overlap
.bitfield
.imm64
)
4550 && !operand_type_equal (&overlap
, &imm8
)
4551 && !operand_type_equal (&overlap
, &imm8s
)
4552 && !operand_type_equal (&overlap
, &imm16
)
4553 && !operand_type_equal (&overlap
, &imm32
)
4554 && !operand_type_equal (&overlap
, &imm32s
)
4555 && !operand_type_equal (&overlap
, &imm64
))
4559 i386_operand_type temp
;
4561 operand_type_set (&temp
, 0);
4562 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
4564 temp
.bitfield
.imm8
= overlap
.bitfield
.imm8
;
4565 temp
.bitfield
.imm8s
= overlap
.bitfield
.imm8s
;
4567 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
4568 temp
.bitfield
.imm16
= overlap
.bitfield
.imm16
;
4569 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
4571 temp
.bitfield
.imm64
= overlap
.bitfield
.imm64
;
4572 temp
.bitfield
.imm32s
= overlap
.bitfield
.imm32s
;
4575 temp
.bitfield
.imm32
= overlap
.bitfield
.imm32
;
4578 else if (operand_type_equal (&overlap
, &imm16_32_32s
)
4579 || operand_type_equal (&overlap
, &imm16_32
)
4580 || operand_type_equal (&overlap
, &imm16_32s
))
4582 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
4587 if (!operand_type_equal (&overlap
, &imm8
)
4588 && !operand_type_equal (&overlap
, &imm8s
)
4589 && !operand_type_equal (&overlap
, &imm16
)
4590 && !operand_type_equal (&overlap
, &imm32
)
4591 && !operand_type_equal (&overlap
, &imm32s
)
4592 && !operand_type_equal (&overlap
, &imm64
))
4594 as_bad (_("no instruction mnemonic suffix given; "
4595 "can't determine immediate size"));
4599 i
.types
[j
] = overlap
;
4609 /* Update the first 2 immediate operands. */
4610 n
= i
.operands
> 2 ? 2 : i
.operands
;
4613 for (j
= 0; j
< n
; j
++)
4614 if (update_imm (j
) == 0)
4617 /* The 3rd operand can't be immediate operand. */
4618 gas_assert (operand_type_check (i
.types
[2], imm
) == 0);
4625 bad_implicit_operand (int xmm
)
4627 const char *reg
= xmm
? "xmm0" : "ymm0";
4629 as_bad (_("the last operand of `%s' must be `%s%s'"),
4630 i
.tm
.name
, register_prefix
, reg
);
4632 as_bad (_("the first operand of `%s' must be `%s%s'"),
4633 i
.tm
.name
, register_prefix
, reg
);
4638 process_operands (void)
4640 /* Default segment register this instruction will use for memory
4641 accesses. 0 means unknown. This is only for optimizing out
4642 unnecessary segment overrides. */
4643 const seg_entry
*default_seg
= 0;
4645 if (i
.tm
.opcode_modifier
.sse2avx
4646 && (i
.tm
.opcode_modifier
.vexnds
4647 || i
.tm
.opcode_modifier
.vexndd
))
4649 unsigned int dup
= i
.operands
;
4650 unsigned int dest
= dup
- 1;
4653 /* The destination must be an xmm register. */
4654 gas_assert (i
.reg_operands
4655 && MAX_OPERANDS
> dup
4656 && operand_type_equal (&i
.types
[dest
], ®xmm
));
4658 if (i
.tm
.opcode_modifier
.firstxmm0
)
4660 /* The first operand is implicit and must be xmm0. */
4661 gas_assert (operand_type_equal (&i
.types
[0], ®xmm
));
4662 if (i
.op
[0].regs
->reg_num
!= 0)
4663 return bad_implicit_operand (1);
4665 if (i
.tm
.opcode_modifier
.vex3sources
)
4667 /* Keep xmm0 for instructions with VEX prefix and 3
4673 /* We remove the first xmm0 and keep the number of
4674 operands unchanged, which in fact duplicates the
4676 for (j
= 1; j
< i
.operands
; j
++)
4678 i
.op
[j
- 1] = i
.op
[j
];
4679 i
.types
[j
- 1] = i
.types
[j
];
4680 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
4684 else if (i
.tm
.opcode_modifier
.implicit1stxmm0
)
4686 gas_assert ((MAX_OPERANDS
- 1) > dup
4687 && i
.tm
.opcode_modifier
.vex3sources
);
4689 /* Add the implicit xmm0 for instructions with VEX prefix
4691 for (j
= i
.operands
; j
> 0; j
--)
4693 i
.op
[j
] = i
.op
[j
- 1];
4694 i
.types
[j
] = i
.types
[j
- 1];
4695 i
.tm
.operand_types
[j
] = i
.tm
.operand_types
[j
- 1];
4698 = (const reg_entry
*) hash_find (reg_hash
, "xmm0");
4699 i
.types
[0] = regxmm
;
4700 i
.tm
.operand_types
[0] = regxmm
;
4703 i
.reg_operands
+= 2;
4708 i
.op
[dup
] = i
.op
[dest
];
4709 i
.types
[dup
] = i
.types
[dest
];
4710 i
.tm
.operand_types
[dup
] = i
.tm
.operand_types
[dest
];
4719 i
.op
[dup
] = i
.op
[dest
];
4720 i
.types
[dup
] = i
.types
[dest
];
4721 i
.tm
.operand_types
[dup
] = i
.tm
.operand_types
[dest
];
4724 if (i
.tm
.opcode_modifier
.immext
)
4727 else if (i
.tm
.opcode_modifier
.firstxmm0
)
4731 /* The first operand is implicit and must be xmm0/ymm0. */
4732 gas_assert (i
.reg_operands
4733 && (operand_type_equal (&i
.types
[0], ®xmm
)
4734 || operand_type_equal (&i
.types
[0], ®ymm
)));
4735 if (i
.op
[0].regs
->reg_num
!= 0)
4736 return bad_implicit_operand (i
.types
[0].bitfield
.regxmm
);
4738 for (j
= 1; j
< i
.operands
; j
++)
4740 i
.op
[j
- 1] = i
.op
[j
];
4741 i
.types
[j
- 1] = i
.types
[j
];
4743 /* We need to adjust fields in i.tm since they are used by
4744 build_modrm_byte. */
4745 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
4752 else if (i
.tm
.opcode_modifier
.regkludge
)
4754 /* The imul $imm, %reg instruction is converted into
4755 imul $imm, %reg, %reg, and the clr %reg instruction
4756 is converted into xor %reg, %reg. */
4758 unsigned int first_reg_op
;
4760 if (operand_type_check (i
.types
[0], reg
))
4764 /* Pretend we saw the extra register operand. */
4765 gas_assert (i
.reg_operands
== 1
4766 && i
.op
[first_reg_op
+ 1].regs
== 0);
4767 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
4768 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
4773 if (i
.tm
.opcode_modifier
.shortform
)
4775 if (i
.types
[0].bitfield
.sreg2
4776 || i
.types
[0].bitfield
.sreg3
)
4778 if (i
.tm
.base_opcode
== POP_SEG_SHORT
4779 && i
.op
[0].regs
->reg_num
== 1)
4781 as_bad (_("you can't `pop %scs'"), register_prefix
);
4784 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
4785 if ((i
.op
[0].regs
->reg_flags
& RegRex
) != 0)
4790 /* The register or float register operand is in operand
4794 if (i
.types
[0].bitfield
.floatreg
4795 || operand_type_check (i
.types
[0], reg
))
4799 /* Register goes in low 3 bits of opcode. */
4800 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
4801 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
4803 if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
4805 /* Warn about some common errors, but press on regardless.
4806 The first case can be generated by gcc (<= 2.8.1). */
4807 if (i
.operands
== 2)
4809 /* Reversed arguments on faddp, fsubp, etc. */
4810 as_warn (_("translating to `%s %s%s,%s%s'"), i
.tm
.name
,
4811 register_prefix
, i
.op
[!intel_syntax
].regs
->reg_name
,
4812 register_prefix
, i
.op
[intel_syntax
].regs
->reg_name
);
4816 /* Extraneous `l' suffix on fp insn. */
4817 as_warn (_("translating to `%s %s%s'"), i
.tm
.name
,
4818 register_prefix
, i
.op
[0].regs
->reg_name
);
4823 else if (i
.tm
.opcode_modifier
.modrm
)
4825 /* The opcode is completed (modulo i.tm.extension_opcode which
4826 must be put into the modrm byte). Now, we make the modrm and
4827 index base bytes based on all the info we've collected. */
4829 default_seg
= build_modrm_byte ();
4831 else if ((i
.tm
.base_opcode
& ~0x3) == MOV_AX_DISP32
)
4835 else if (i
.tm
.opcode_modifier
.isstring
)
4837 /* For the string instructions that allow a segment override
4838 on one of their operands, the default segment is ds. */
4842 if (i
.tm
.base_opcode
== 0x8d /* lea */
4845 as_warn (_("segment override on `%s' is ineffectual"), i
.tm
.name
);
4847 /* If a segment was explicitly specified, and the specified segment
4848 is not the default, use an opcode prefix to select it. If we
4849 never figured out what the default segment is, then default_seg
4850 will be zero at this point, and the specified segment prefix will
4852 if ((i
.seg
[0]) && (i
.seg
[0] != default_seg
))
4854 if (!add_prefix (i
.seg
[0]->seg_prefix
))
4860 static const seg_entry
*
4861 build_modrm_byte (void)
4863 const seg_entry
*default_seg
= 0;
4864 unsigned int source
, dest
;
4867 /* The first operand of instructions with VEX prefix and 3 sources
4868 must be VEX_Imm4. */
4869 vex_3_sources
= i
.tm
.opcode_modifier
.vex3sources
;
4872 unsigned int nds
, reg
;
4874 if (i
.tm
.opcode_modifier
.veximmext
4875 && i
.tm
.opcode_modifier
.immext
)
4877 dest
= i
.operands
- 2;
4878 gas_assert (dest
== 3);
4881 dest
= i
.operands
- 1;
4884 /* This instruction must have 4 register operands
4885 or 3 register operands plus 1 memory operand.
4886 It must have VexNDS and VexImmExt. */
4887 gas_assert ((i
.reg_operands
== 4
4888 || (i
.reg_operands
== 3 && i
.mem_operands
== 1))
4889 && i
.tm
.opcode_modifier
.vexnds
4890 && i
.tm
.opcode_modifier
.veximmext
4891 && (operand_type_equal (&i
.tm
.operand_types
[dest
], ®xmm
)
4892 || operand_type_equal (&i
.tm
.operand_types
[dest
], ®ymm
)));
4894 /* Generate an 8bit immediate operand to encode the register
4896 expressionS
*exp
= &im_expressions
[i
.imm_operands
++];
4897 i
.op
[i
.operands
].imms
= exp
;
4898 i
.types
[i
.operands
] = imm8
;
4900 /* If VexW1 is set, the first operand is the source and
4901 the second operand is encoded in the immediate operand. */
4902 if (i
.tm
.opcode_modifier
.vexw1
)
4912 /* FMA4 swaps REG and NDS. */
4913 if (i
.tm
.cpu_flags
.bitfield
.cpufma4
)
4920 gas_assert ((operand_type_equal (&i
.tm
.operand_types
[reg
], ®xmm
)
4921 || operand_type_equal (&i
.tm
.operand_types
[reg
],
4923 && (operand_type_equal (&i
.tm
.operand_types
[nds
], ®xmm
)
4924 || operand_type_equal (&i
.tm
.operand_types
[nds
],
4926 exp
->X_op
= O_constant
;
4928 = ((i
.op
[reg
].regs
->reg_num
4929 + ((i
.op
[reg
].regs
->reg_flags
& RegRex
) ? 8 : 0)) << 4);
4930 i
.vex
.register_specifier
= i
.op
[nds
].regs
;
4935 /* i.reg_operands MUST be the number of real register operands;
4936 implicit registers do not count. If there are 3 register
4937 operands, it must be a instruction with VexNDS. For a
4938 instruction with VexNDD, the destination register is encoded
4939 in VEX prefix. If there are 4 register operands, it must be
4940 a instruction with VEX prefix and 3 sources. */
4941 if (i
.mem_operands
== 0
4942 && ((i
.reg_operands
== 2
4943 && !i
.tm
.opcode_modifier
.vexndd
)
4944 || (i
.reg_operands
== 3
4945 && i
.tm
.opcode_modifier
.vexnds
)
4946 || (i
.reg_operands
== 4 && vex_3_sources
)))
4954 /* When there are 3 operands, one of them may be immediate,
4955 which may be the first or the last operand. Otherwise,
4956 the first operand must be shift count register (cl) or it
4957 is an instruction with VexNDS. */
4958 gas_assert (i
.imm_operands
== 1
4959 || (i
.imm_operands
== 0
4960 && (i
.tm
.opcode_modifier
.vexnds
4961 || i
.types
[0].bitfield
.shiftcount
)));
4962 if (operand_type_check (i
.types
[0], imm
)
4963 || i
.types
[0].bitfield
.shiftcount
)
4969 /* When there are 4 operands, the first two must be 8bit
4970 immediate operands. The source operand will be the 3rd
4973 For instructions with VexNDS, if the first operand
4974 an imm8, the source operand is the 2nd one. If the last
4975 operand is imm8, the source operand is the first one. */
4976 gas_assert ((i
.imm_operands
== 2
4977 && i
.types
[0].bitfield
.imm8
4978 && i
.types
[1].bitfield
.imm8
)
4979 || (i
.tm
.opcode_modifier
.vexnds
4980 && i
.imm_operands
== 1
4981 && (i
.types
[0].bitfield
.imm8
4982 || i
.types
[i
.operands
- 1].bitfield
.imm8
)));
4983 if (i
.tm
.opcode_modifier
.vexnds
)
4985 if (i
.types
[0].bitfield
.imm8
)
5003 if (i
.tm
.opcode_modifier
.vexnds
)
5005 /* For instructions with VexNDS, the register-only
5006 source operand must be XMM or YMM register. It is
5007 encoded in VEX prefix. We need to clear RegMem bit
5008 before calling operand_type_equal. */
5009 i386_operand_type op
= i
.tm
.operand_types
[dest
];
5010 op
.bitfield
.regmem
= 0;
5011 if ((dest
+ 1) >= i
.operands
5012 || (!operand_type_equal (&op
, ®xmm
)
5013 && !operand_type_equal (&op
, ®ymm
)))
5015 i
.vex
.register_specifier
= i
.op
[dest
].regs
;
5021 /* One of the register operands will be encoded in the i.tm.reg
5022 field, the other in the combined i.tm.mode and i.tm.regmem
5023 fields. If no form of this instruction supports a memory
5024 destination operand, then we assume the source operand may
5025 sometimes be a memory operand and so we need to store the
5026 destination in the i.rm.reg field. */
5027 if (!i
.tm
.operand_types
[dest
].bitfield
.regmem
5028 && operand_type_check (i
.tm
.operand_types
[dest
], anymem
) == 0)
5030 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
5031 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
5032 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
5034 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
5039 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
5040 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
5041 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
5043 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
5046 if (flag_code
!= CODE_64BIT
&& (i
.rex
& (REX_R
| REX_B
)))
5048 if (!i
.types
[0].bitfield
.control
5049 && !i
.types
[1].bitfield
.control
)
5051 i
.rex
&= ~(REX_R
| REX_B
);
5052 add_prefix (LOCK_PREFIX_OPCODE
);
5056 { /* If it's not 2 reg operands... */
5061 unsigned int fake_zero_displacement
= 0;
5064 for (op
= 0; op
< i
.operands
; op
++)
5065 if (operand_type_check (i
.types
[op
], anymem
))
5067 gas_assert (op
< i
.operands
);
5071 if (i
.base_reg
== 0)
5074 if (!i
.disp_operands
)
5075 fake_zero_displacement
= 1;
5076 if (i
.index_reg
== 0)
5078 /* Operand is just <disp> */
5079 if (flag_code
== CODE_64BIT
)
5081 /* 64bit mode overwrites the 32bit absolute
5082 addressing by RIP relative addressing and
5083 absolute addressing is encoded by one of the
5084 redundant SIB forms. */
5085 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
5086 i
.sib
.base
= NO_BASE_REGISTER
;
5087 i
.sib
.index
= NO_INDEX_REGISTER
;
5088 i
.types
[op
] = ((i
.prefix
[ADDR_PREFIX
] == 0)
5089 ? disp32s
: disp32
);
5091 else if ((flag_code
== CODE_16BIT
)
5092 ^ (i
.prefix
[ADDR_PREFIX
] != 0))
5094 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
5095 i
.types
[op
] = disp16
;
5099 i
.rm
.regmem
= NO_BASE_REGISTER
;
5100 i
.types
[op
] = disp32
;
5103 else /* !i.base_reg && i.index_reg */
5105 if (i
.index_reg
->reg_num
== RegEiz
5106 || i
.index_reg
->reg_num
== RegRiz
)
5107 i
.sib
.index
= NO_INDEX_REGISTER
;
5109 i
.sib
.index
= i
.index_reg
->reg_num
;
5110 i
.sib
.base
= NO_BASE_REGISTER
;
5111 i
.sib
.scale
= i
.log2_scale_factor
;
5112 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
5113 i
.types
[op
].bitfield
.disp8
= 0;
5114 i
.types
[op
].bitfield
.disp16
= 0;
5115 i
.types
[op
].bitfield
.disp64
= 0;
5116 if (flag_code
!= CODE_64BIT
)
5118 /* Must be 32 bit */
5119 i
.types
[op
].bitfield
.disp32
= 1;
5120 i
.types
[op
].bitfield
.disp32s
= 0;
5124 i
.types
[op
].bitfield
.disp32
= 0;
5125 i
.types
[op
].bitfield
.disp32s
= 1;
5127 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
5131 /* RIP addressing for 64bit mode. */
5132 else if (i
.base_reg
->reg_num
== RegRip
||
5133 i
.base_reg
->reg_num
== RegEip
)
5135 i
.rm
.regmem
= NO_BASE_REGISTER
;
5136 i
.types
[op
].bitfield
.disp8
= 0;
5137 i
.types
[op
].bitfield
.disp16
= 0;
5138 i
.types
[op
].bitfield
.disp32
= 0;
5139 i
.types
[op
].bitfield
.disp32s
= 1;
5140 i
.types
[op
].bitfield
.disp64
= 0;
5141 i
.flags
[op
] |= Operand_PCrel
;
5142 if (! i
.disp_operands
)
5143 fake_zero_displacement
= 1;
5145 else if (i
.base_reg
->reg_type
.bitfield
.reg16
)
5147 switch (i
.base_reg
->reg_num
)
5150 if (i
.index_reg
== 0)
5152 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
5153 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
5157 if (i
.index_reg
== 0)
5160 if (operand_type_check (i
.types
[op
], disp
) == 0)
5162 /* fake (%bp) into 0(%bp) */
5163 i
.types
[op
].bitfield
.disp8
= 1;
5164 fake_zero_displacement
= 1;
5167 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
5168 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
5170 default: /* (%si) -> 4 or (%di) -> 5 */
5171 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
5173 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
5175 else /* i.base_reg and 32/64 bit mode */
5177 if (flag_code
== CODE_64BIT
5178 && operand_type_check (i
.types
[op
], disp
))
5180 i386_operand_type temp
;
5181 operand_type_set (&temp
, 0);
5182 temp
.bitfield
.disp8
= i
.types
[op
].bitfield
.disp8
;
5184 if (i
.prefix
[ADDR_PREFIX
] == 0)
5185 i
.types
[op
].bitfield
.disp32s
= 1;
5187 i
.types
[op
].bitfield
.disp32
= 1;
5190 i
.rm
.regmem
= i
.base_reg
->reg_num
;
5191 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
5193 i
.sib
.base
= i
.base_reg
->reg_num
;
5194 /* x86-64 ignores REX prefix bit here to avoid decoder
5196 if ((i
.base_reg
->reg_num
& 7) == EBP_REG_NUM
)
5199 if (i
.disp_operands
== 0)
5201 fake_zero_displacement
= 1;
5202 i
.types
[op
].bitfield
.disp8
= 1;
5205 else if (i
.base_reg
->reg_num
== ESP_REG_NUM
)
5209 i
.sib
.scale
= i
.log2_scale_factor
;
5210 if (i
.index_reg
== 0)
5212 /* <disp>(%esp) becomes two byte modrm with no index
5213 register. We've already stored the code for esp
5214 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
5215 Any base register besides %esp will not use the
5216 extra modrm byte. */
5217 i
.sib
.index
= NO_INDEX_REGISTER
;
5221 if (i
.index_reg
->reg_num
== RegEiz
5222 || i
.index_reg
->reg_num
== RegRiz
)
5223 i
.sib
.index
= NO_INDEX_REGISTER
;
5225 i
.sib
.index
= i
.index_reg
->reg_num
;
5226 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
5227 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
5232 && (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
5233 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
))
5236 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
5239 if (fake_zero_displacement
)
5241 /* Fakes a zero displacement assuming that i.types[op]
5242 holds the correct displacement size. */
5245 gas_assert (i
.op
[op
].disps
== 0);
5246 exp
= &disp_expressions
[i
.disp_operands
++];
5247 i
.op
[op
].disps
= exp
;
5248 exp
->X_op
= O_constant
;
5249 exp
->X_add_number
= 0;
5250 exp
->X_add_symbol
= (symbolS
*) 0;
5251 exp
->X_op_symbol
= (symbolS
*) 0;
5259 /* Fill in i.rm.reg or i.rm.regmem field with register operand
5260 (if any) based on i.tm.extension_opcode. Again, we must be
5261 careful to make sure that segment/control/debug/test/MMX
5262 registers are coded into the i.rm.reg field. */
5266 unsigned int vex_reg
= ~0;
5268 for (op
= 0; op
< i
.operands
; op
++)
5269 if (i
.types
[op
].bitfield
.reg8
5270 || i
.types
[op
].bitfield
.reg16
5271 || i
.types
[op
].bitfield
.reg32
5272 || i
.types
[op
].bitfield
.reg64
5273 || i
.types
[op
].bitfield
.regmmx
5274 || i
.types
[op
].bitfield
.regxmm
5275 || i
.types
[op
].bitfield
.regymm
5276 || i
.types
[op
].bitfield
.sreg2
5277 || i
.types
[op
].bitfield
.sreg3
5278 || i
.types
[op
].bitfield
.control
5279 || i
.types
[op
].bitfield
.debug
5280 || i
.types
[op
].bitfield
.test
)
5285 else if (i
.tm
.opcode_modifier
.vexnds
)
5287 /* For instructions with VexNDS, the register-only
5288 source operand is encoded in VEX prefix. */
5289 gas_assert (mem
!= (unsigned int) ~0);
5294 gas_assert (op
< i
.operands
);
5299 gas_assert (vex_reg
< i
.operands
);
5302 else if (i
.tm
.opcode_modifier
.vexndd
)
5304 /* For instructions with VexNDD, there should be
5305 no memory operand and the register destination
5306 is encoded in VEX prefix. */
5307 gas_assert (i
.mem_operands
== 0
5308 && (op
+ 2) == i
.operands
);
5312 gas_assert (op
< i
.operands
);
5314 if (vex_reg
!= (unsigned int) ~0)
5316 gas_assert (i
.reg_operands
== 2);
5318 if (!operand_type_equal (&i
.tm
.operand_types
[vex_reg
],
5320 && !operand_type_equal (&i
.tm
.operand_types
[vex_reg
],
5323 i
.vex
.register_specifier
= i
.op
[vex_reg
].regs
;
5326 /* If there is an extension opcode to put here, the
5327 register number must be put into the regmem field. */
5328 if (i
.tm
.extension_opcode
!= None
)
5330 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
5331 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
5336 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
5337 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
5341 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
5342 must set it to 3 to indicate this is a register operand
5343 in the regmem field. */
5344 if (!i
.mem_operands
)
5348 /* Fill in i.rm.reg field with extension opcode (if any). */
5349 if (i
.tm
.extension_opcode
!= None
)
5350 i
.rm
.reg
= i
.tm
.extension_opcode
;
5356 output_branch (void)
5361 relax_substateT subtype
;
5366 if (flag_code
== CODE_16BIT
)
5370 if (i
.prefix
[DATA_PREFIX
] != 0)
5376 /* Pentium4 branch hints. */
5377 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
5378 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
5383 if (i
.prefix
[REX_PREFIX
] != 0)
5389 if (i
.prefixes
!= 0 && !intel_syntax
)
5390 as_warn (_("skipping prefixes on this instruction"));
5392 /* It's always a symbol; End frag & setup for relax.
5393 Make sure there is enough room in this frag for the largest
5394 instruction we may generate in md_convert_frag. This is 2
5395 bytes for the opcode and room for the prefix and largest
5397 frag_grow (prefix
+ 2 + 4);
5398 /* Prefix and 1 opcode byte go in fr_fix. */
5399 p
= frag_more (prefix
+ 1);
5400 if (i
.prefix
[DATA_PREFIX
] != 0)
5401 *p
++ = DATA_PREFIX_OPCODE
;
5402 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
5403 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
5404 *p
++ = i
.prefix
[SEG_PREFIX
];
5405 if (i
.prefix
[REX_PREFIX
] != 0)
5406 *p
++ = i
.prefix
[REX_PREFIX
];
5407 *p
= i
.tm
.base_opcode
;
5409 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
5410 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, SMALL
);
5411 else if (cpu_arch_flags
.bitfield
.cpui386
)
5412 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, SMALL
);
5414 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, SMALL
);
5417 sym
= i
.op
[0].disps
->X_add_symbol
;
5418 off
= i
.op
[0].disps
->X_add_number
;
5420 if (i
.op
[0].disps
->X_op
!= O_constant
5421 && i
.op
[0].disps
->X_op
!= O_symbol
)
5423 /* Handle complex expressions. */
5424 sym
= make_expr_symbol (i
.op
[0].disps
);
5428 /* 1 possible extra opcode + 4 byte displacement go in var part.
5429 Pass reloc in fr_var. */
5430 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
5440 if (i
.tm
.opcode_modifier
.jumpbyte
)
5442 /* This is a loop or jecxz type instruction. */
5444 if (i
.prefix
[ADDR_PREFIX
] != 0)
5446 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
5449 /* Pentium4 branch hints. */
5450 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
5451 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
5453 FRAG_APPEND_1_CHAR (i
.prefix
[SEG_PREFIX
]);
5462 if (flag_code
== CODE_16BIT
)
5465 if (i
.prefix
[DATA_PREFIX
] != 0)
5467 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
5477 if (i
.prefix
[REX_PREFIX
] != 0)
5479 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
5483 if (i
.prefixes
!= 0 && !intel_syntax
)
5484 as_warn (_("skipping prefixes on this instruction"));
5486 p
= frag_more (1 + size
);
5487 *p
++ = i
.tm
.base_opcode
;
5489 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
5490 i
.op
[0].disps
, 1, reloc (size
, 1, 1, i
.reloc
[0]));
5492 /* All jumps handled here are signed, but don't use a signed limit
5493 check for 32 and 16 bit jumps as we want to allow wrap around at
5494 4G and 64k respectively. */
5496 fixP
->fx_signed
= 1;
5500 output_interseg_jump (void)
5508 if (flag_code
== CODE_16BIT
)
5512 if (i
.prefix
[DATA_PREFIX
] != 0)
5518 if (i
.prefix
[REX_PREFIX
] != 0)
5528 if (i
.prefixes
!= 0 && !intel_syntax
)
5529 as_warn (_("skipping prefixes on this instruction"));
5531 /* 1 opcode; 2 segment; offset */
5532 p
= frag_more (prefix
+ 1 + 2 + size
);
5534 if (i
.prefix
[DATA_PREFIX
] != 0)
5535 *p
++ = DATA_PREFIX_OPCODE
;
5537 if (i
.prefix
[REX_PREFIX
] != 0)
5538 *p
++ = i
.prefix
[REX_PREFIX
];
5540 *p
++ = i
.tm
.base_opcode
;
5541 if (i
.op
[1].imms
->X_op
== O_constant
)
5543 offsetT n
= i
.op
[1].imms
->X_add_number
;
5546 && !fits_in_unsigned_word (n
)
5547 && !fits_in_signed_word (n
))
5549 as_bad (_("16-bit jump out of range"));
5552 md_number_to_chars (p
, n
, size
);
5555 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
5556 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
5557 if (i
.op
[0].imms
->X_op
!= O_constant
)
5558 as_bad (_("can't handle non absolute segment in `%s'"),
5560 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
5566 fragS
*insn_start_frag
;
5567 offsetT insn_start_off
;
5569 /* Tie dwarf2 debug info to the address at the start of the insn.
5570 We can't do this after the insn has been output as the current
5571 frag may have been closed off. eg. by frag_var. */
5572 dwarf2_emit_insn (0);
5574 insn_start_frag
= frag_now
;
5575 insn_start_off
= frag_now_fix ();
5578 if (i
.tm
.opcode_modifier
.jump
)
5580 else if (i
.tm
.opcode_modifier
.jumpbyte
5581 || i
.tm
.opcode_modifier
.jumpdword
)
5583 else if (i
.tm
.opcode_modifier
.jumpintersegment
)
5584 output_interseg_jump ();
5587 /* Output normal instructions here. */
5591 unsigned int prefix
;
5593 /* Since the VEX prefix contains the implicit prefix, we don't
5594 need the explicit prefix. */
5595 if (!i
.tm
.opcode_modifier
.vex
)
5597 switch (i
.tm
.opcode_length
)
5600 if (i
.tm
.base_opcode
& 0xff000000)
5602 prefix
= (i
.tm
.base_opcode
>> 24) & 0xff;
5607 if ((i
.tm
.base_opcode
& 0xff0000) != 0)
5609 prefix
= (i
.tm
.base_opcode
>> 16) & 0xff;
5610 if (i
.tm
.cpu_flags
.bitfield
.cpupadlock
)
5613 if (prefix
!= REPE_PREFIX_OPCODE
5614 || (i
.prefix
[LOCKREP_PREFIX
]
5615 != REPE_PREFIX_OPCODE
))
5616 add_prefix (prefix
);
5619 add_prefix (prefix
);
5628 /* The prefix bytes. */
5629 for (j
= ARRAY_SIZE (i
.prefix
), q
= i
.prefix
; j
> 0; j
--, q
++)
5631 FRAG_APPEND_1_CHAR (*q
);
5634 if (i
.tm
.opcode_modifier
.vex
)
5636 for (j
= 0, q
= i
.prefix
; j
< ARRAY_SIZE (i
.prefix
); j
++, q
++)
5641 /* REX byte is encoded in VEX prefix. */
5645 FRAG_APPEND_1_CHAR (*q
);
5648 /* There should be no other prefixes for instructions
5653 /* Now the VEX prefix. */
5654 p
= frag_more (i
.vex
.length
);
5655 for (j
= 0; j
< i
.vex
.length
; j
++)
5656 p
[j
] = i
.vex
.bytes
[j
];
5659 /* Now the opcode; be careful about word order here! */
5660 if (i
.tm
.opcode_length
== 1)
5662 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
5666 switch (i
.tm
.opcode_length
)
5670 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
5680 /* Put out high byte first: can't use md_number_to_chars! */
5681 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
5682 *p
= i
.tm
.base_opcode
& 0xff;
5685 /* Now the modrm byte and sib byte (if present). */
5686 if (i
.tm
.opcode_modifier
.modrm
)
5688 FRAG_APPEND_1_CHAR ((i
.rm
.regmem
<< 0
5691 /* If i.rm.regmem == ESP (4)
5692 && i.rm.mode != (Register mode)
5694 ==> need second modrm byte. */
5695 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
5697 && !(i
.base_reg
&& i
.base_reg
->reg_type
.bitfield
.reg16
))
5698 FRAG_APPEND_1_CHAR ((i
.sib
.base
<< 0
5700 | i
.sib
.scale
<< 6));
5703 if (i
.disp_operands
)
5704 output_disp (insn_start_frag
, insn_start_off
);
5707 output_imm (insn_start_frag
, insn_start_off
);
5713 pi ("" /*line*/, &i
);
5715 #endif /* DEBUG386 */
5718 /* Return the size of the displacement operand N. */
5721 disp_size (unsigned int n
)
5724 if (i
.types
[n
].bitfield
.disp64
)
5726 else if (i
.types
[n
].bitfield
.disp8
)
5728 else if (i
.types
[n
].bitfield
.disp16
)
5733 /* Return the size of the immediate operand N. */
5736 imm_size (unsigned int n
)
5739 if (i
.types
[n
].bitfield
.imm64
)
5741 else if (i
.types
[n
].bitfield
.imm8
|| i
.types
[n
].bitfield
.imm8s
)
5743 else if (i
.types
[n
].bitfield
.imm16
)
5749 output_disp (fragS
*insn_start_frag
, offsetT insn_start_off
)
5754 for (n
= 0; n
< i
.operands
; n
++)
5756 if (operand_type_check (i
.types
[n
], disp
))
5758 if (i
.op
[n
].disps
->X_op
== O_constant
)
5760 int size
= disp_size (n
);
5763 val
= offset_in_range (i
.op
[n
].disps
->X_add_number
,
5765 p
= frag_more (size
);
5766 md_number_to_chars (p
, val
, size
);
5770 enum bfd_reloc_code_real reloc_type
;
5771 int size
= disp_size (n
);
5772 int sign
= i
.types
[n
].bitfield
.disp32s
;
5773 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
5775 /* We can't have 8 bit displacement here. */
5776 gas_assert (!i
.types
[n
].bitfield
.disp8
);
5778 /* The PC relative address is computed relative
5779 to the instruction boundary, so in case immediate
5780 fields follows, we need to adjust the value. */
5781 if (pcrel
&& i
.imm_operands
)
5786 for (n1
= 0; n1
< i
.operands
; n1
++)
5787 if (operand_type_check (i
.types
[n1
], imm
))
5789 /* Only one immediate is allowed for PC
5790 relative address. */
5791 gas_assert (sz
== 0);
5793 i
.op
[n
].disps
->X_add_number
-= sz
;
5795 /* We should find the immediate. */
5796 gas_assert (sz
!= 0);
5799 p
= frag_more (size
);
5800 reloc_type
= reloc (size
, pcrel
, sign
, i
.reloc
[n
]);
5802 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
5803 && (((reloc_type
== BFD_RELOC_32
5804 || reloc_type
== BFD_RELOC_X86_64_32S
5805 || (reloc_type
== BFD_RELOC_64
5807 && (i
.op
[n
].disps
->X_op
== O_symbol
5808 || (i
.op
[n
].disps
->X_op
== O_add
5809 && ((symbol_get_value_expression
5810 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
5812 || reloc_type
== BFD_RELOC_32_PCREL
))
5816 if (insn_start_frag
== frag_now
)
5817 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
5822 add
= insn_start_frag
->fr_fix
- insn_start_off
;
5823 for (fr
= insn_start_frag
->fr_next
;
5824 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
5826 add
+= p
- frag_now
->fr_literal
;
5831 reloc_type
= BFD_RELOC_386_GOTPC
;
5832 i
.op
[n
].imms
->X_add_number
+= add
;
5834 else if (reloc_type
== BFD_RELOC_64
)
5835 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
5837 /* Don't do the adjustment for x86-64, as there
5838 the pcrel addressing is relative to the _next_
5839 insn, and that is taken care of in other code. */
5840 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
5842 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
5843 i
.op
[n
].disps
, pcrel
, reloc_type
);
5850 output_imm (fragS
*insn_start_frag
, offsetT insn_start_off
)
5855 for (n
= 0; n
< i
.operands
; n
++)
5857 if (operand_type_check (i
.types
[n
], imm
))
5859 if (i
.op
[n
].imms
->X_op
== O_constant
)
5861 int size
= imm_size (n
);
5864 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
5866 p
= frag_more (size
);
5867 md_number_to_chars (p
, val
, size
);
5871 /* Not absolute_section.
5872 Need a 32-bit fixup (don't support 8bit
5873 non-absolute imms). Try to support other
5875 enum bfd_reloc_code_real reloc_type
;
5876 int size
= imm_size (n
);
5879 if (i
.types
[n
].bitfield
.imm32s
5880 && (i
.suffix
== QWORD_MNEM_SUFFIX
5881 || (!i
.suffix
&& i
.tm
.opcode_modifier
.no_lsuf
)))
5886 p
= frag_more (size
);
5887 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
5889 /* This is tough to explain. We end up with this one if we
5890 * have operands that look like
5891 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
5892 * obtain the absolute address of the GOT, and it is strongly
5893 * preferable from a performance point of view to avoid using
5894 * a runtime relocation for this. The actual sequence of
5895 * instructions often look something like:
5900 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
5902 * The call and pop essentially return the absolute address
5903 * of the label .L66 and store it in %ebx. The linker itself
5904 * will ultimately change the first operand of the addl so
5905 * that %ebx points to the GOT, but to keep things simple, the
5906 * .o file must have this operand set so that it generates not
5907 * the absolute address of .L66, but the absolute address of
5908 * itself. This allows the linker itself simply treat a GOTPC
5909 * relocation as asking for a pcrel offset to the GOT to be
5910 * added in, and the addend of the relocation is stored in the
5911 * operand field for the instruction itself.
5913 * Our job here is to fix the operand so that it would add
5914 * the correct offset so that %ebx would point to itself. The
5915 * thing that is tricky is that .-.L66 will point to the
5916 * beginning of the instruction, so we need to further modify
5917 * the operand so that it will point to itself. There are
5918 * other cases where you have something like:
5920 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
5922 * and here no correction would be required. Internally in
5923 * the assembler we treat operands of this form as not being
5924 * pcrel since the '.' is explicitly mentioned, and I wonder
5925 * whether it would simplify matters to do it this way. Who
5926 * knows. In earlier versions of the PIC patches, the
5927 * pcrel_adjust field was used to store the correction, but
5928 * since the expression is not pcrel, I felt it would be
5929 * confusing to do it this way. */
5931 if ((reloc_type
== BFD_RELOC_32
5932 || reloc_type
== BFD_RELOC_X86_64_32S
5933 || reloc_type
== BFD_RELOC_64
)
5935 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
5936 && (i
.op
[n
].imms
->X_op
== O_symbol
5937 || (i
.op
[n
].imms
->X_op
== O_add
5938 && ((symbol_get_value_expression
5939 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
5944 if (insn_start_frag
== frag_now
)
5945 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
5950 add
= insn_start_frag
->fr_fix
- insn_start_off
;
5951 for (fr
= insn_start_frag
->fr_next
;
5952 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
5954 add
+= p
- frag_now
->fr_literal
;
5958 reloc_type
= BFD_RELOC_386_GOTPC
;
5960 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
5962 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
5963 i
.op
[n
].imms
->X_add_number
+= add
;
5965 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
5966 i
.op
[n
].imms
, 0, reloc_type
);
5972 /* x86_cons_fix_new is called via the expression parsing code when a
5973 reloc is needed. We use this hook to get the correct .got reloc. */
5974 static enum bfd_reloc_code_real got_reloc
= NO_RELOC
;
5975 static int cons_sign
= -1;
5978 x86_cons_fix_new (fragS
*frag
, unsigned int off
, unsigned int len
,
5981 enum bfd_reloc_code_real r
= reloc (len
, 0, cons_sign
, got_reloc
);
5983 got_reloc
= NO_RELOC
;
5986 if (exp
->X_op
== O_secrel
)
5988 exp
->X_op
= O_symbol
;
5989 r
= BFD_RELOC_32_SECREL
;
5993 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
5996 #if (!defined (OBJ_ELF) && !defined (OBJ_MAYBE_ELF)) || defined (LEX_AT)
5997 # define lex_got(reloc, adjust, types) NULL
5999 /* Parse operands of the form
6000 <symbol>@GOTOFF+<nnn>
6001 and similar .plt or .got references.
6003 If we find one, set up the correct relocation in RELOC and copy the
6004 input string, minus the `@GOTOFF' into a malloc'd buffer for
6005 parsing by the calling routine. Return this buffer, and if ADJUST
6006 is non-null set it to the length of the string we removed from the
6007 input line. Otherwise return NULL. */
6009 lex_got (enum bfd_reloc_code_real
*reloc
,
6011 i386_operand_type
*types
)
6013 /* Some of the relocations depend on the size of what field is to
6014 be relocated. But in our callers i386_immediate and i386_displacement
6015 we don't yet know the operand size (this will be set by insn
6016 matching). Hence we record the word32 relocation here,
6017 and adjust the reloc according to the real size in reloc(). */
6018 static const struct {
6020 const enum bfd_reloc_code_real rel
[2];
6021 const i386_operand_type types64
;
6023 { "PLTOFF", { _dummy_first_bfd_reloc_code_real
,
6024 BFD_RELOC_X86_64_PLTOFF64
},
6025 OPERAND_TYPE_IMM64
},
6026 { "PLT", { BFD_RELOC_386_PLT32
,
6027 BFD_RELOC_X86_64_PLT32
},
6028 OPERAND_TYPE_IMM32_32S_DISP32
},
6029 { "GOTPLT", { _dummy_first_bfd_reloc_code_real
,
6030 BFD_RELOC_X86_64_GOTPLT64
},
6031 OPERAND_TYPE_IMM64_DISP64
},
6032 { "GOTOFF", { BFD_RELOC_386_GOTOFF
,
6033 BFD_RELOC_X86_64_GOTOFF64
},
6034 OPERAND_TYPE_IMM64_DISP64
},
6035 { "GOTPCREL", { _dummy_first_bfd_reloc_code_real
,
6036 BFD_RELOC_X86_64_GOTPCREL
},
6037 OPERAND_TYPE_IMM32_32S_DISP32
},
6038 { "TLSGD", { BFD_RELOC_386_TLS_GD
,
6039 BFD_RELOC_X86_64_TLSGD
},
6040 OPERAND_TYPE_IMM32_32S_DISP32
},
6041 { "TLSLDM", { BFD_RELOC_386_TLS_LDM
,
6042 _dummy_first_bfd_reloc_code_real
},
6043 OPERAND_TYPE_NONE
},
6044 { "TLSLD", { _dummy_first_bfd_reloc_code_real
,
6045 BFD_RELOC_X86_64_TLSLD
},
6046 OPERAND_TYPE_IMM32_32S_DISP32
},
6047 { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32
,
6048 BFD_RELOC_X86_64_GOTTPOFF
},
6049 OPERAND_TYPE_IMM32_32S_DISP32
},
6050 { "TPOFF", { BFD_RELOC_386_TLS_LE_32
,
6051 BFD_RELOC_X86_64_TPOFF32
},
6052 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
6053 { "NTPOFF", { BFD_RELOC_386_TLS_LE
,
6054 _dummy_first_bfd_reloc_code_real
},
6055 OPERAND_TYPE_NONE
},
6056 { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32
,
6057 BFD_RELOC_X86_64_DTPOFF32
},
6059 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
6060 { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE
,
6061 _dummy_first_bfd_reloc_code_real
},
6062 OPERAND_TYPE_NONE
},
6063 { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE
,
6064 _dummy_first_bfd_reloc_code_real
},
6065 OPERAND_TYPE_NONE
},
6066 { "GOT", { BFD_RELOC_386_GOT32
,
6067 BFD_RELOC_X86_64_GOT32
},
6068 OPERAND_TYPE_IMM32_32S_64_DISP32
},
6069 { "TLSDESC", { BFD_RELOC_386_TLS_GOTDESC
,
6070 BFD_RELOC_X86_64_GOTPC32_TLSDESC
},
6071 OPERAND_TYPE_IMM32_32S_DISP32
},
6072 { "TLSCALL", { BFD_RELOC_386_TLS_DESC_CALL
,
6073 BFD_RELOC_X86_64_TLSDESC_CALL
},
6074 OPERAND_TYPE_IMM32_32S_DISP32
},
6082 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
6083 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
6086 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
6090 len
= strlen (gotrel
[j
].str
);
6091 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
6093 if (gotrel
[j
].rel
[object_64bit
] != 0)
6096 char *tmpbuf
, *past_reloc
;
6098 *reloc
= gotrel
[j
].rel
[object_64bit
];
6104 if (flag_code
!= CODE_64BIT
)
6106 types
->bitfield
.imm32
= 1;
6107 types
->bitfield
.disp32
= 1;
6110 *types
= gotrel
[j
].types64
;
6113 if (GOT_symbol
== NULL
)
6114 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
6116 /* The length of the first part of our input line. */
6117 first
= cp
- input_line_pointer
;
6119 /* The second part goes from after the reloc token until
6120 (and including) an end_of_line char or comma. */
6121 past_reloc
= cp
+ 1 + len
;
6123 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
6125 second
= cp
+ 1 - past_reloc
;
6127 /* Allocate and copy string. The trailing NUL shouldn't
6128 be necessary, but be safe. */
6129 tmpbuf
= (char *) xmalloc (first
+ second
+ 2);
6130 memcpy (tmpbuf
, input_line_pointer
, first
);
6131 if (second
!= 0 && *past_reloc
!= ' ')
6132 /* Replace the relocation token with ' ', so that
6133 errors like foo@GOTOFF1 will be detected. */
6134 tmpbuf
[first
++] = ' ';
6135 memcpy (tmpbuf
+ first
, past_reloc
, second
);
6136 tmpbuf
[first
+ second
] = '\0';
6140 as_bad (_("@%s reloc is not supported with %d-bit output format"),
6141 gotrel
[j
].str
, 1 << (5 + object_64bit
));
6146 /* Might be a symbol version string. Don't as_bad here. */
6151 x86_cons (expressionS
*exp
, int size
)
6153 intel_syntax
= -intel_syntax
;
6155 if (size
== 4 || (object_64bit
&& size
== 8))
6157 /* Handle @GOTOFF and the like in an expression. */
6159 char *gotfree_input_line
;
6162 save
= input_line_pointer
;
6163 gotfree_input_line
= lex_got (&got_reloc
, &adjust
, NULL
);
6164 if (gotfree_input_line
)
6165 input_line_pointer
= gotfree_input_line
;
6169 if (gotfree_input_line
)
6171 /* expression () has merrily parsed up to the end of line,
6172 or a comma - in the wrong buffer. Transfer how far
6173 input_line_pointer has moved to the right buffer. */
6174 input_line_pointer
= (save
6175 + (input_line_pointer
- gotfree_input_line
)
6177 free (gotfree_input_line
);
6178 if (exp
->X_op
== O_constant
6179 || exp
->X_op
== O_absent
6180 || exp
->X_op
== O_illegal
6181 || exp
->X_op
== O_register
6182 || exp
->X_op
== O_big
)
6184 char c
= *input_line_pointer
;
6185 *input_line_pointer
= 0;
6186 as_bad (_("missing or invalid expression `%s'"), save
);
6187 *input_line_pointer
= c
;
6194 intel_syntax
= -intel_syntax
;
6197 i386_intel_simplify (exp
);
6201 static void signed_cons (int size
)
6203 if (flag_code
== CODE_64BIT
)
6211 pe_directive_secrel (dummy
)
6212 int dummy ATTRIBUTE_UNUSED
;
6219 if (exp
.X_op
== O_symbol
)
6220 exp
.X_op
= O_secrel
;
6222 emit_expr (&exp
, 4);
6224 while (*input_line_pointer
++ == ',');
6226 input_line_pointer
--;
6227 demand_empty_rest_of_line ();
6232 i386_immediate (char *imm_start
)
6234 char *save_input_line_pointer
;
6235 char *gotfree_input_line
;
6238 i386_operand_type types
;
6240 operand_type_set (&types
, ~0);
6242 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
6244 as_bad (_("at most %d immediate operands are allowed"),
6245 MAX_IMMEDIATE_OPERANDS
);
6249 exp
= &im_expressions
[i
.imm_operands
++];
6250 i
.op
[this_operand
].imms
= exp
;
6252 if (is_space_char (*imm_start
))
6255 save_input_line_pointer
= input_line_pointer
;
6256 input_line_pointer
= imm_start
;
6258 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
6259 if (gotfree_input_line
)
6260 input_line_pointer
= gotfree_input_line
;
6262 exp_seg
= expression (exp
);
6265 if (*input_line_pointer
)
6266 as_bad (_("junk `%s' after expression"), input_line_pointer
);
6268 input_line_pointer
= save_input_line_pointer
;
6269 if (gotfree_input_line
)
6271 free (gotfree_input_line
);
6273 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
6274 exp
->X_op
= O_illegal
;
6277 return i386_finalize_immediate (exp_seg
, exp
, types
, imm_start
);
6281 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
6282 i386_operand_type types
, const char *imm_start
)
6284 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_illegal
|| exp
->X_op
== O_big
)
6286 as_bad (_("missing or invalid immediate expression `%s'"),
6290 else if (exp
->X_op
== O_constant
)
6292 /* Size it properly later. */
6293 i
.types
[this_operand
].bitfield
.imm64
= 1;
6294 /* If BFD64, sign extend val. */
6295 if (!use_rela_relocations
6296 && (exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
6298 = (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
6300 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
6301 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
6302 && exp_seg
!= absolute_section
6303 && exp_seg
!= text_section
6304 && exp_seg
!= data_section
6305 && exp_seg
!= bss_section
6306 && exp_seg
!= undefined_section
6307 && !bfd_is_com_section (exp_seg
))
6309 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
6313 else if (!intel_syntax
&& exp
->X_op
== O_register
)
6315 as_bad (_("illegal immediate register operand %s"), imm_start
);
6320 /* This is an address. The size of the address will be
6321 determined later, depending on destination register,
6322 suffix, or the default for the section. */
6323 i
.types
[this_operand
].bitfield
.imm8
= 1;
6324 i
.types
[this_operand
].bitfield
.imm16
= 1;
6325 i
.types
[this_operand
].bitfield
.imm32
= 1;
6326 i
.types
[this_operand
].bitfield
.imm32s
= 1;
6327 i
.types
[this_operand
].bitfield
.imm64
= 1;
6328 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
6336 i386_scale (char *scale
)
6339 char *save
= input_line_pointer
;
6341 input_line_pointer
= scale
;
6342 val
= get_absolute_expression ();
6347 i
.log2_scale_factor
= 0;
6350 i
.log2_scale_factor
= 1;
6353 i
.log2_scale_factor
= 2;
6356 i
.log2_scale_factor
= 3;
6360 char sep
= *input_line_pointer
;
6362 *input_line_pointer
= '\0';
6363 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
6365 *input_line_pointer
= sep
;
6366 input_line_pointer
= save
;
6370 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
6372 as_warn (_("scale factor of %d without an index register"),
6373 1 << i
.log2_scale_factor
);
6374 i
.log2_scale_factor
= 0;
6376 scale
= input_line_pointer
;
6377 input_line_pointer
= save
;
6382 i386_displacement (char *disp_start
, char *disp_end
)
6386 char *save_input_line_pointer
;
6387 char *gotfree_input_line
;
6389 i386_operand_type bigdisp
, types
= anydisp
;
6392 if (i
.disp_operands
== MAX_MEMORY_OPERANDS
)
6394 as_bad (_("at most %d displacement operands are allowed"),
6395 MAX_MEMORY_OPERANDS
);
6399 operand_type_set (&bigdisp
, 0);
6400 if ((i
.types
[this_operand
].bitfield
.jumpabsolute
)
6401 || (!current_templates
->start
->opcode_modifier
.jump
6402 && !current_templates
->start
->opcode_modifier
.jumpdword
))
6404 bigdisp
.bitfield
.disp32
= 1;
6405 override
= (i
.prefix
[ADDR_PREFIX
] != 0);
6406 if (flag_code
== CODE_64BIT
)
6410 bigdisp
.bitfield
.disp32s
= 1;
6411 bigdisp
.bitfield
.disp64
= 1;
6414 else if ((flag_code
== CODE_16BIT
) ^ override
)
6416 bigdisp
.bitfield
.disp32
= 0;
6417 bigdisp
.bitfield
.disp16
= 1;
6422 /* For PC-relative branches, the width of the displacement
6423 is dependent upon data size, not address size. */
6424 override
= (i
.prefix
[DATA_PREFIX
] != 0);
6425 if (flag_code
== CODE_64BIT
)
6427 if (override
|| i
.suffix
== WORD_MNEM_SUFFIX
)
6428 bigdisp
.bitfield
.disp16
= 1;
6431 bigdisp
.bitfield
.disp32
= 1;
6432 bigdisp
.bitfield
.disp32s
= 1;
6438 override
= (i
.suffix
== (flag_code
!= CODE_16BIT
6440 : LONG_MNEM_SUFFIX
));
6441 bigdisp
.bitfield
.disp32
= 1;
6442 if ((flag_code
== CODE_16BIT
) ^ override
)
6444 bigdisp
.bitfield
.disp32
= 0;
6445 bigdisp
.bitfield
.disp16
= 1;
6449 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
6452 exp
= &disp_expressions
[i
.disp_operands
];
6453 i
.op
[this_operand
].disps
= exp
;
6455 save_input_line_pointer
= input_line_pointer
;
6456 input_line_pointer
= disp_start
;
6457 END_STRING_AND_SAVE (disp_end
);
6459 #ifndef GCC_ASM_O_HACK
6460 #define GCC_ASM_O_HACK 0
6463 END_STRING_AND_SAVE (disp_end
+ 1);
6464 if (i
.types
[this_operand
].bitfield
.baseIndex
6465 && displacement_string_end
[-1] == '+')
6467 /* This hack is to avoid a warning when using the "o"
6468 constraint within gcc asm statements.
6471 #define _set_tssldt_desc(n,addr,limit,type) \
6472 __asm__ __volatile__ ( \
6474 "movw %w1,2+%0\n\t" \
6476 "movb %b1,4+%0\n\t" \
6477 "movb %4,5+%0\n\t" \
6478 "movb $0,6+%0\n\t" \
6479 "movb %h1,7+%0\n\t" \
6481 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
6483 This works great except that the output assembler ends
6484 up looking a bit weird if it turns out that there is
6485 no offset. You end up producing code that looks like:
6498 So here we provide the missing zero. */
6500 *displacement_string_end
= '0';
6503 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
6504 if (gotfree_input_line
)
6505 input_line_pointer
= gotfree_input_line
;
6507 exp_seg
= expression (exp
);
6510 if (*input_line_pointer
)
6511 as_bad (_("junk `%s' after expression"), input_line_pointer
);
6513 RESTORE_END_STRING (disp_end
+ 1);
6515 input_line_pointer
= save_input_line_pointer
;
6516 if (gotfree_input_line
)
6518 free (gotfree_input_line
);
6520 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
6521 exp
->X_op
= O_illegal
;
6524 ret
= i386_finalize_displacement (exp_seg
, exp
, types
, disp_start
);
6526 RESTORE_END_STRING (disp_end
);
6532 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
6533 i386_operand_type types
, const char *disp_start
)
6535 i386_operand_type bigdisp
;
6538 /* We do this to make sure that the section symbol is in
6539 the symbol table. We will ultimately change the relocation
6540 to be relative to the beginning of the section. */
6541 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
6542 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
6543 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
6545 if (exp
->X_op
!= O_symbol
)
6548 if (S_IS_LOCAL (exp
->X_add_symbol
)
6549 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
)
6550 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
6551 exp
->X_op
= O_subtract
;
6552 exp
->X_op_symbol
= GOT_symbol
;
6553 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
6554 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
6555 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
6556 i
.reloc
[this_operand
] = BFD_RELOC_64
;
6558 i
.reloc
[this_operand
] = BFD_RELOC_32
;
6561 else if (exp
->X_op
== O_absent
6562 || exp
->X_op
== O_illegal
6563 || exp
->X_op
== O_big
)
6566 as_bad (_("missing or invalid displacement expression `%s'"),
6571 else if (flag_code
== CODE_64BIT
6572 && !i
.prefix
[ADDR_PREFIX
]
6573 && exp
->X_op
== O_constant
)
6575 /* Since displacement is signed extended to 64bit, don't allow
6576 disp32 and turn off disp32s if they are out of range. */
6577 i
.types
[this_operand
].bitfield
.disp32
= 0;
6578 if (!fits_in_signed_long (exp
->X_add_number
))
6580 i
.types
[this_operand
].bitfield
.disp32s
= 0;
6581 if (i
.types
[this_operand
].bitfield
.baseindex
)
6583 as_bad (_("0x%lx out range of signed 32bit displacement"),
6584 (long) exp
->X_add_number
);
6590 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
6591 else if (exp
->X_op
!= O_constant
6592 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
6593 && exp_seg
!= absolute_section
6594 && exp_seg
!= text_section
6595 && exp_seg
!= data_section
6596 && exp_seg
!= bss_section
6597 && exp_seg
!= undefined_section
6598 && !bfd_is_com_section (exp_seg
))
6600 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
6605 /* Check if this is a displacement only operand. */
6606 bigdisp
= i
.types
[this_operand
];
6607 bigdisp
.bitfield
.disp8
= 0;
6608 bigdisp
.bitfield
.disp16
= 0;
6609 bigdisp
.bitfield
.disp32
= 0;
6610 bigdisp
.bitfield
.disp32s
= 0;
6611 bigdisp
.bitfield
.disp64
= 0;
6612 if (operand_type_all_zero (&bigdisp
))
6613 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
6619 /* Make sure the memory operand we've been dealt is valid.
6620 Return 1 on success, 0 on a failure. */
6623 i386_index_check (const char *operand_string
)
6626 const char *kind
= "base/index";
6627 #if INFER_ADDR_PREFIX
6633 if (current_templates
->start
->opcode_modifier
.isstring
6634 && !current_templates
->start
->opcode_modifier
.immext
6635 && (current_templates
->end
[-1].opcode_modifier
.isstring
6638 /* Memory operands of string insns are special in that they only allow
6639 a single register (rDI, rSI, or rBX) as their memory address. */
6640 unsigned int expected
;
6642 kind
= "string address";
6644 if (current_templates
->start
->opcode_modifier
.w
)
6646 i386_operand_type type
= current_templates
->end
[-1].operand_types
[0];
6648 if (!type
.bitfield
.baseindex
6649 || ((!i
.mem_operands
!= !intel_syntax
)
6650 && current_templates
->end
[-1].operand_types
[1]
6651 .bitfield
.baseindex
))
6652 type
= current_templates
->end
[-1].operand_types
[1];
6653 expected
= type
.bitfield
.esseg
? 7 /* rDI */ : 6 /* rSI */;
6656 expected
= 3 /* rBX */;
6658 if (!i
.base_reg
|| i
.index_reg
6659 || operand_type_check (i
.types
[this_operand
], disp
))
6661 else if (!(flag_code
== CODE_64BIT
6662 ? i
.prefix
[ADDR_PREFIX
]
6663 ? i
.base_reg
->reg_type
.bitfield
.reg32
6664 : i
.base_reg
->reg_type
.bitfield
.reg64
6665 : (flag_code
== CODE_16BIT
) ^ !i
.prefix
[ADDR_PREFIX
]
6666 ? i
.base_reg
->reg_type
.bitfield
.reg32
6667 : i
.base_reg
->reg_type
.bitfield
.reg16
))
6669 else if (i
.base_reg
->reg_num
!= expected
)
6676 for (j
= 0; j
< i386_regtab_size
; ++j
)
6677 if ((flag_code
== CODE_64BIT
6678 ? i
.prefix
[ADDR_PREFIX
]
6679 ? i386_regtab
[j
].reg_type
.bitfield
.reg32
6680 : i386_regtab
[j
].reg_type
.bitfield
.reg64
6681 : (flag_code
== CODE_16BIT
) ^ !i
.prefix
[ADDR_PREFIX
]
6682 ? i386_regtab
[j
].reg_type
.bitfield
.reg32
6683 : i386_regtab
[j
].reg_type
.bitfield
.reg16
)
6684 && i386_regtab
[j
].reg_num
== expected
)
6686 gas_assert (j
< i386_regtab_size
);
6687 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
6689 intel_syntax
? '[' : '(',
6691 i386_regtab
[j
].reg_name
,
6692 intel_syntax
? ']' : ')');
6696 else if (flag_code
== CODE_64BIT
)
6699 && ((i
.prefix
[ADDR_PREFIX
] == 0
6700 && !i
.base_reg
->reg_type
.bitfield
.reg64
)
6701 || (i
.prefix
[ADDR_PREFIX
]
6702 && !i
.base_reg
->reg_type
.bitfield
.reg32
))
6704 || i
.base_reg
->reg_num
!=
6705 (i
.prefix
[ADDR_PREFIX
] == 0 ? RegRip
: RegEip
)))
6707 && (!i
.index_reg
->reg_type
.bitfield
.baseindex
6708 || (i
.prefix
[ADDR_PREFIX
] == 0
6709 && i
.index_reg
->reg_num
!= RegRiz
6710 && !i
.index_reg
->reg_type
.bitfield
.reg64
6712 || (i
.prefix
[ADDR_PREFIX
]
6713 && i
.index_reg
->reg_num
!= RegEiz
6714 && !i
.index_reg
->reg_type
.bitfield
.reg32
))))
6719 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[ADDR_PREFIX
] != 0))
6723 && (!i
.base_reg
->reg_type
.bitfield
.reg16
6724 || !i
.base_reg
->reg_type
.bitfield
.baseindex
))
6726 && (!i
.index_reg
->reg_type
.bitfield
.reg16
6727 || !i
.index_reg
->reg_type
.bitfield
.baseindex
6729 && i
.base_reg
->reg_num
< 6
6730 && i
.index_reg
->reg_num
>= 6
6731 && i
.log2_scale_factor
== 0))))
6738 && !i
.base_reg
->reg_type
.bitfield
.reg32
)
6740 && ((!i
.index_reg
->reg_type
.bitfield
.reg32
6741 && i
.index_reg
->reg_num
!= RegEiz
)
6742 || !i
.index_reg
->reg_type
.bitfield
.baseindex
)))
6748 #if INFER_ADDR_PREFIX
6749 if (!i
.mem_operands
&& !i
.prefix
[ADDR_PREFIX
])
6751 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
6753 /* Change the size of any displacement too. At most one of
6754 Disp16 or Disp32 is set.
6755 FIXME. There doesn't seem to be any real need for separate
6756 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
6757 Removing them would probably clean up the code quite a lot. */
6758 if (flag_code
!= CODE_64BIT
6759 && (i
.types
[this_operand
].bitfield
.disp16
6760 || i
.types
[this_operand
].bitfield
.disp32
))
6761 i
.types
[this_operand
]
6762 = operand_type_xor (i
.types
[this_operand
], disp16_32
);
6767 as_bad (_("`%s' is not a valid %s expression"),
6772 as_bad (_("`%s' is not a valid %s-bit %s expression"),
6774 flag_code_names
[i
.prefix
[ADDR_PREFIX
]
6775 ? flag_code
== CODE_32BIT
6784 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
6788 i386_att_operand (char *operand_string
)
6792 char *op_string
= operand_string
;
6794 if (is_space_char (*op_string
))
6797 /* We check for an absolute prefix (differentiating,
6798 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
6799 if (*op_string
== ABSOLUTE_PREFIX
)
6802 if (is_space_char (*op_string
))
6804 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
6807 /* Check if operand is a register. */
6808 if ((r
= parse_register (op_string
, &end_op
)) != NULL
)
6810 i386_operand_type temp
;
6812 /* Check for a segment override by searching for ':' after a
6813 segment register. */
6815 if (is_space_char (*op_string
))
6817 if (*op_string
== ':'
6818 && (r
->reg_type
.bitfield
.sreg2
6819 || r
->reg_type
.bitfield
.sreg3
))
6824 i
.seg
[i
.mem_operands
] = &es
;
6827 i
.seg
[i
.mem_operands
] = &cs
;
6830 i
.seg
[i
.mem_operands
] = &ss
;
6833 i
.seg
[i
.mem_operands
] = &ds
;
6836 i
.seg
[i
.mem_operands
] = &fs
;
6839 i
.seg
[i
.mem_operands
] = &gs
;
6843 /* Skip the ':' and whitespace. */
6845 if (is_space_char (*op_string
))
6848 if (!is_digit_char (*op_string
)
6849 && !is_identifier_char (*op_string
)
6850 && *op_string
!= '('
6851 && *op_string
!= ABSOLUTE_PREFIX
)
6853 as_bad (_("bad memory operand `%s'"), op_string
);
6856 /* Handle case of %es:*foo. */
6857 if (*op_string
== ABSOLUTE_PREFIX
)
6860 if (is_space_char (*op_string
))
6862 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
6864 goto do_memory_reference
;
6868 as_bad (_("junk `%s' after register"), op_string
);
6872 temp
.bitfield
.baseindex
= 0;
6873 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
6875 i
.types
[this_operand
].bitfield
.unspecified
= 0;
6876 i
.op
[this_operand
].regs
= r
;
6879 else if (*op_string
== REGISTER_PREFIX
)
6881 as_bad (_("bad register name `%s'"), op_string
);
6884 else if (*op_string
== IMMEDIATE_PREFIX
)
6887 if (i
.types
[this_operand
].bitfield
.jumpabsolute
)
6889 as_bad (_("immediate operand illegal with absolute jump"));
6892 if (!i386_immediate (op_string
))
6895 else if (is_digit_char (*op_string
)
6896 || is_identifier_char (*op_string
)
6897 || *op_string
== '(')
6899 /* This is a memory reference of some sort. */
6902 /* Start and end of displacement string expression (if found). */
6903 char *displacement_string_start
;
6904 char *displacement_string_end
;
6906 do_memory_reference
:
6907 if ((i
.mem_operands
== 1
6908 && !current_templates
->start
->opcode_modifier
.isstring
)
6909 || i
.mem_operands
== 2)
6911 as_bad (_("too many memory references for `%s'"),
6912 current_templates
->start
->name
);
6916 /* Check for base index form. We detect the base index form by
6917 looking for an ')' at the end of the operand, searching
6918 for the '(' matching it, and finding a REGISTER_PREFIX or ','
6920 base_string
= op_string
+ strlen (op_string
);
6923 if (is_space_char (*base_string
))
6926 /* If we only have a displacement, set-up for it to be parsed later. */
6927 displacement_string_start
= op_string
;
6928 displacement_string_end
= base_string
+ 1;
6930 if (*base_string
== ')')
6933 unsigned int parens_balanced
= 1;
6934 /* We've already checked that the number of left & right ()'s are
6935 equal, so this loop will not be infinite. */
6939 if (*base_string
== ')')
6941 if (*base_string
== '(')
6944 while (parens_balanced
);
6946 temp_string
= base_string
;
6948 /* Skip past '(' and whitespace. */
6950 if (is_space_char (*base_string
))
6953 if (*base_string
== ','
6954 || ((i
.base_reg
= parse_register (base_string
, &end_op
))
6957 displacement_string_end
= temp_string
;
6959 i
.types
[this_operand
].bitfield
.baseindex
= 1;
6963 base_string
= end_op
;
6964 if (is_space_char (*base_string
))
6968 /* There may be an index reg or scale factor here. */
6969 if (*base_string
== ',')
6972 if (is_space_char (*base_string
))
6975 if ((i
.index_reg
= parse_register (base_string
, &end_op
))
6978 base_string
= end_op
;
6979 if (is_space_char (*base_string
))
6981 if (*base_string
== ',')
6984 if (is_space_char (*base_string
))
6987 else if (*base_string
!= ')')
6989 as_bad (_("expecting `,' or `)' "
6990 "after index register in `%s'"),
6995 else if (*base_string
== REGISTER_PREFIX
)
6997 as_bad (_("bad register name `%s'"), base_string
);
7001 /* Check for scale factor. */
7002 if (*base_string
!= ')')
7004 char *end_scale
= i386_scale (base_string
);
7009 base_string
= end_scale
;
7010 if (is_space_char (*base_string
))
7012 if (*base_string
!= ')')
7014 as_bad (_("expecting `)' "
7015 "after scale factor in `%s'"),
7020 else if (!i
.index_reg
)
7022 as_bad (_("expecting index register or scale factor "
7023 "after `,'; got '%c'"),
7028 else if (*base_string
!= ')')
7030 as_bad (_("expecting `,' or `)' "
7031 "after base register in `%s'"),
7036 else if (*base_string
== REGISTER_PREFIX
)
7038 as_bad (_("bad register name `%s'"), base_string
);
7043 /* If there's an expression beginning the operand, parse it,
7044 assuming displacement_string_start and
7045 displacement_string_end are meaningful. */
7046 if (displacement_string_start
!= displacement_string_end
)
7048 if (!i386_displacement (displacement_string_start
,
7049 displacement_string_end
))
7053 /* Special case for (%dx) while doing input/output op. */
7055 && operand_type_equal (&i
.base_reg
->reg_type
,
7056 ®16_inoutportreg
)
7058 && i
.log2_scale_factor
== 0
7059 && i
.seg
[i
.mem_operands
] == 0
7060 && !operand_type_check (i
.types
[this_operand
], disp
))
7062 i
.types
[this_operand
] = inoutportreg
;
7066 if (i386_index_check (operand_string
) == 0)
7068 i
.types
[this_operand
].bitfield
.mem
= 1;
7073 /* It's not a memory operand; argh! */
7074 as_bad (_("invalid char %s beginning operand %d `%s'"),
7075 output_invalid (*op_string
),
7080 return 1; /* Normal return. */
7083 /* md_estimate_size_before_relax()
7085 Called just before relax() for rs_machine_dependent frags. The x86
7086 assembler uses these frags to handle variable size jump
7089 Any symbol that is now undefined will not become defined.
7090 Return the correct fr_subtype in the frag.
7091 Return the initial "guess for variable size of frag" to caller.
7092 The guess is actually the growth beyond the fixed part. Whatever
7093 we do to grow the fixed or variable part contributes to our
7097 md_estimate_size_before_relax (fragP
, segment
)
7101 /* We've already got fragP->fr_subtype right; all we have to do is
7102 check for un-relaxable symbols. On an ELF system, we can't relax
7103 an externally visible symbol, because it may be overridden by a
7105 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
7106 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7108 && (S_IS_EXTERNAL (fragP
->fr_symbol
)
7109 || S_IS_WEAK (fragP
->fr_symbol
)
7110 || ((symbol_get_bfdsym (fragP
->fr_symbol
)->flags
7111 & BSF_GNU_INDIRECT_FUNCTION
))))
7113 #if defined (OBJ_COFF) && defined (TE_PE)
7114 || (OUTPUT_FLAVOR
== bfd_target_coff_flavour
7115 && S_IS_WEAK (fragP
->fr_symbol
))
7119 /* Symbol is undefined in this segment, or we need to keep a
7120 reloc so that weak symbols can be overridden. */
7121 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
7122 enum bfd_reloc_code_real reloc_type
;
7123 unsigned char *opcode
;
7126 if (fragP
->fr_var
!= NO_RELOC
)
7127 reloc_type
= (enum bfd_reloc_code_real
) fragP
->fr_var
;
7129 reloc_type
= BFD_RELOC_16_PCREL
;
7131 reloc_type
= BFD_RELOC_32_PCREL
;
7133 old_fr_fix
= fragP
->fr_fix
;
7134 opcode
= (unsigned char *) fragP
->fr_opcode
;
7136 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
7139 /* Make jmp (0xeb) a (d)word displacement jump. */
7141 fragP
->fr_fix
+= size
;
7142 fix_new (fragP
, old_fr_fix
, size
,
7144 fragP
->fr_offset
, 1,
7150 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
7152 /* Negate the condition, and branch past an
7153 unconditional jump. */
7156 /* Insert an unconditional jump. */
7158 /* We added two extra opcode bytes, and have a two byte
7160 fragP
->fr_fix
+= 2 + 2;
7161 fix_new (fragP
, old_fr_fix
+ 2, 2,
7163 fragP
->fr_offset
, 1,
7170 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
7175 fixP
= fix_new (fragP
, old_fr_fix
, 1,
7177 fragP
->fr_offset
, 1,
7179 fixP
->fx_signed
= 1;
7183 /* This changes the byte-displacement jump 0x7N
7184 to the (d)word-displacement jump 0x0f,0x8N. */
7185 opcode
[1] = opcode
[0] + 0x10;
7186 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
7187 /* We've added an opcode byte. */
7188 fragP
->fr_fix
+= 1 + size
;
7189 fix_new (fragP
, old_fr_fix
+ 1, size
,
7191 fragP
->fr_offset
, 1,
7196 BAD_CASE (fragP
->fr_subtype
);
7200 return fragP
->fr_fix
- old_fr_fix
;
7203 /* Guess size depending on current relax state. Initially the relax
7204 state will correspond to a short jump and we return 1, because
7205 the variable part of the frag (the branch offset) is one byte
7206 long. However, we can relax a section more than once and in that
7207 case we must either set fr_subtype back to the unrelaxed state,
7208 or return the value for the appropriate branch. */
7209 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
7212 /* Called after relax() is finished.
7214 In: Address of frag.
7215 fr_type == rs_machine_dependent.
7216 fr_subtype is what the address relaxed to.
7218 Out: Any fixSs and constants are set up.
7219 Caller will turn frag into a ".space 0". */
7222 md_convert_frag (abfd
, sec
, fragP
)
7223 bfd
*abfd ATTRIBUTE_UNUSED
;
7224 segT sec ATTRIBUTE_UNUSED
;
7227 unsigned char *opcode
;
7228 unsigned char *where_to_put_displacement
= NULL
;
7229 offsetT target_address
;
7230 offsetT opcode_address
;
7231 unsigned int extension
= 0;
7232 offsetT displacement_from_opcode_start
;
7234 opcode
= (unsigned char *) fragP
->fr_opcode
;
7236 /* Address we want to reach in file space. */
7237 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
7239 /* Address opcode resides at in file space. */
7240 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
7242 /* Displacement from opcode start to fill into instruction. */
7243 displacement_from_opcode_start
= target_address
- opcode_address
;
7245 if ((fragP
->fr_subtype
& BIG
) == 0)
7247 /* Don't have to change opcode. */
7248 extension
= 1; /* 1 opcode + 1 displacement */
7249 where_to_put_displacement
= &opcode
[1];
7253 if (no_cond_jump_promotion
7254 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
7255 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
7256 _("long jump required"));
7258 switch (fragP
->fr_subtype
)
7260 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
7261 extension
= 4; /* 1 opcode + 4 displacement */
7263 where_to_put_displacement
= &opcode
[1];
7266 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
7267 extension
= 2; /* 1 opcode + 2 displacement */
7269 where_to_put_displacement
= &opcode
[1];
7272 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
7273 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
7274 extension
= 5; /* 2 opcode + 4 displacement */
7275 opcode
[1] = opcode
[0] + 0x10;
7276 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
7277 where_to_put_displacement
= &opcode
[2];
7280 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
7281 extension
= 3; /* 2 opcode + 2 displacement */
7282 opcode
[1] = opcode
[0] + 0x10;
7283 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
7284 where_to_put_displacement
= &opcode
[2];
7287 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
7292 where_to_put_displacement
= &opcode
[3];
7296 BAD_CASE (fragP
->fr_subtype
);
7301 /* If size if less then four we are sure that the operand fits,
7302 but if it's 4, then it could be that the displacement is larger
7304 if (DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
) == 4
7306 && ((addressT
) (displacement_from_opcode_start
- extension
7307 + ((addressT
) 1 << 31))
7308 > (((addressT
) 2 << 31) - 1)))
7310 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
7311 _("jump target out of range"));
7312 /* Make us emit 0. */
7313 displacement_from_opcode_start
= extension
;
7315 /* Now put displacement after opcode. */
7316 md_number_to_chars ((char *) where_to_put_displacement
,
7317 (valueT
) (displacement_from_opcode_start
- extension
),
7318 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
7319 fragP
->fr_fix
+= extension
;
7322 /* Apply a fixup (fixS) to segment data, once it has been determined
7323 by our caller that we have all the info we need to fix it up.
7325 On the 386, immediates, displacements, and data pointers are all in
7326 the same (little-endian) format, so we don't need to care about which
7330 md_apply_fix (fixP
, valP
, seg
)
7331 /* The fix we're to put in. */
7333 /* Pointer to the value of the bits. */
7335 /* Segment fix is from. */
7336 segT seg ATTRIBUTE_UNUSED
;
7338 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
7339 valueT value
= *valP
;
7341 #if !defined (TE_Mach)
7344 switch (fixP
->fx_r_type
)
7350 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
7353 case BFD_RELOC_X86_64_32S
:
7354 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
7357 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
7360 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
7365 if (fixP
->fx_addsy
!= NULL
7366 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
7367 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
7368 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
7369 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
7370 && !use_rela_relocations
)
7372 /* This is a hack. There should be a better way to handle this.
7373 This covers for the fact that bfd_install_relocation will
7374 subtract the current location (for partial_inplace, PC relative
7375 relocations); see more below. */
7379 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
7382 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
7384 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7387 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
7390 || (symbol_section_p (fixP
->fx_addsy
)
7391 && sym_seg
!= absolute_section
))
7392 && !generic_force_reloc (fixP
))
7394 /* Yes, we add the values in twice. This is because
7395 bfd_install_relocation subtracts them out again. I think
7396 bfd_install_relocation is broken, but I don't dare change
7398 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
7402 #if defined (OBJ_COFF) && defined (TE_PE)
7403 /* For some reason, the PE format does not store a
7404 section address offset for a PC relative symbol. */
7405 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
7406 || S_IS_WEAK (fixP
->fx_addsy
))
7407 value
+= md_pcrel_from (fixP
);
7410 #if defined (OBJ_COFF) && defined (TE_PE)
7411 if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
7413 value
-= S_GET_VALUE (fixP
->fx_addsy
);
7417 /* Fix a few things - the dynamic linker expects certain values here,
7418 and we must not disappoint it. */
7419 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7420 if (IS_ELF
&& fixP
->fx_addsy
)
7421 switch (fixP
->fx_r_type
)
7423 case BFD_RELOC_386_PLT32
:
7424 case BFD_RELOC_X86_64_PLT32
:
7425 /* Make the jump instruction point to the address of the operand. At
7426 runtime we merely add the offset to the actual PLT entry. */
7430 case BFD_RELOC_386_TLS_GD
:
7431 case BFD_RELOC_386_TLS_LDM
:
7432 case BFD_RELOC_386_TLS_IE_32
:
7433 case BFD_RELOC_386_TLS_IE
:
7434 case BFD_RELOC_386_TLS_GOTIE
:
7435 case BFD_RELOC_386_TLS_GOTDESC
:
7436 case BFD_RELOC_X86_64_TLSGD
:
7437 case BFD_RELOC_X86_64_TLSLD
:
7438 case BFD_RELOC_X86_64_GOTTPOFF
:
7439 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
7440 value
= 0; /* Fully resolved at runtime. No addend. */
7442 case BFD_RELOC_386_TLS_LE
:
7443 case BFD_RELOC_386_TLS_LDO_32
:
7444 case BFD_RELOC_386_TLS_LE_32
:
7445 case BFD_RELOC_X86_64_DTPOFF32
:
7446 case BFD_RELOC_X86_64_DTPOFF64
:
7447 case BFD_RELOC_X86_64_TPOFF32
:
7448 case BFD_RELOC_X86_64_TPOFF64
:
7449 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
7452 case BFD_RELOC_386_TLS_DESC_CALL
:
7453 case BFD_RELOC_X86_64_TLSDESC_CALL
:
7454 value
= 0; /* Fully resolved at runtime. No addend. */
7455 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
7459 case BFD_RELOC_386_GOT32
:
7460 case BFD_RELOC_X86_64_GOT32
:
7461 value
= 0; /* Fully resolved at runtime. No addend. */
7464 case BFD_RELOC_VTABLE_INHERIT
:
7465 case BFD_RELOC_VTABLE_ENTRY
:
7472 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
7474 #endif /* !defined (TE_Mach) */
7476 /* Are we finished with this relocation now? */
7477 if (fixP
->fx_addsy
== NULL
)
7479 #if defined (OBJ_COFF) && defined (TE_PE)
7480 else if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
7483 /* Remember value for tc_gen_reloc. */
7484 fixP
->fx_addnumber
= value
;
7485 /* Clear out the frag for now. */
7489 else if (use_rela_relocations
)
7491 fixP
->fx_no_overflow
= 1;
7492 /* Remember value for tc_gen_reloc. */
7493 fixP
->fx_addnumber
= value
;
7497 md_number_to_chars (p
, value
, fixP
->fx_size
);
7501 md_atof (int type
, char *litP
, int *sizeP
)
7503 /* This outputs the LITTLENUMs in REVERSE order;
7504 in accord with the bigendian 386. */
7505 return ieee_md_atof (type
, litP
, sizeP
, FALSE
);
7508 static char output_invalid_buf
[sizeof (unsigned char) * 2 + 6];
7511 output_invalid (int c
)
7514 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
7517 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
7518 "(0x%x)", (unsigned char) c
);
7519 return output_invalid_buf
;
7522 /* REG_STRING starts *before* REGISTER_PREFIX. */
7524 static const reg_entry
*
7525 parse_real_register (char *reg_string
, char **end_op
)
7527 char *s
= reg_string
;
7529 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
7532 /* Skip possible REGISTER_PREFIX and possible whitespace. */
7533 if (*s
== REGISTER_PREFIX
)
7536 if (is_space_char (*s
))
7540 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
7542 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
7543 return (const reg_entry
*) NULL
;
7547 /* For naked regs, make sure that we are not dealing with an identifier.
7548 This prevents confusing an identifier like `eax_var' with register
7550 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
7551 return (const reg_entry
*) NULL
;
7555 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
7557 /* Handle floating point regs, allowing spaces in the (i) part. */
7558 if (r
== i386_regtab
/* %st is first entry of table */)
7560 if (is_space_char (*s
))
7565 if (is_space_char (*s
))
7567 if (*s
>= '0' && *s
<= '7')
7571 if (is_space_char (*s
))
7576 r
= (const reg_entry
*) hash_find (reg_hash
, "st(0)");
7581 /* We have "%st(" then garbage. */
7582 return (const reg_entry
*) NULL
;
7586 if (r
== NULL
|| allow_pseudo_reg
)
7589 if (operand_type_all_zero (&r
->reg_type
))
7590 return (const reg_entry
*) NULL
;
7592 if ((r
->reg_type
.bitfield
.reg32
7593 || r
->reg_type
.bitfield
.sreg3
7594 || r
->reg_type
.bitfield
.control
7595 || r
->reg_type
.bitfield
.debug
7596 || r
->reg_type
.bitfield
.test
)
7597 && !cpu_arch_flags
.bitfield
.cpui386
)
7598 return (const reg_entry
*) NULL
;
7600 if (r
->reg_type
.bitfield
.floatreg
7601 && !cpu_arch_flags
.bitfield
.cpu8087
7602 && !cpu_arch_flags
.bitfield
.cpu287
7603 && !cpu_arch_flags
.bitfield
.cpu387
)
7604 return (const reg_entry
*) NULL
;
7606 if (r
->reg_type
.bitfield
.regmmx
&& !cpu_arch_flags
.bitfield
.cpummx
)
7607 return (const reg_entry
*) NULL
;
7609 if (r
->reg_type
.bitfield
.regxmm
&& !cpu_arch_flags
.bitfield
.cpusse
)
7610 return (const reg_entry
*) NULL
;
7612 if (r
->reg_type
.bitfield
.regymm
&& !cpu_arch_flags
.bitfield
.cpuavx
)
7613 return (const reg_entry
*) NULL
;
7615 /* Don't allow fake index register unless allow_index_reg isn't 0. */
7616 if (!allow_index_reg
7617 && (r
->reg_num
== RegEiz
|| r
->reg_num
== RegRiz
))
7618 return (const reg_entry
*) NULL
;
7620 if (((r
->reg_flags
& (RegRex64
| RegRex
))
7621 || r
->reg_type
.bitfield
.reg64
)
7622 && (!cpu_arch_flags
.bitfield
.cpulm
7623 || !operand_type_equal (&r
->reg_type
, &control
))
7624 && flag_code
!= CODE_64BIT
)
7625 return (const reg_entry
*) NULL
;
7627 if (r
->reg_type
.bitfield
.sreg3
&& r
->reg_num
== RegFlat
&& !intel_syntax
)
7628 return (const reg_entry
*) NULL
;
7633 /* REG_STRING starts *before* REGISTER_PREFIX. */
7635 static const reg_entry
*
7636 parse_register (char *reg_string
, char **end_op
)
7640 if (*reg_string
== REGISTER_PREFIX
|| allow_naked_reg
)
7641 r
= parse_real_register (reg_string
, end_op
);
7646 char *save
= input_line_pointer
;
7650 input_line_pointer
= reg_string
;
7651 c
= get_symbol_end ();
7652 symbolP
= symbol_find (reg_string
);
7653 if (symbolP
&& S_GET_SEGMENT (symbolP
) == reg_section
)
7655 const expressionS
*e
= symbol_get_value_expression (symbolP
);
7657 know (e
->X_op
== O_register
);
7658 know (e
->X_add_number
>= 0
7659 && (valueT
) e
->X_add_number
< i386_regtab_size
);
7660 r
= i386_regtab
+ e
->X_add_number
;
7661 *end_op
= input_line_pointer
;
7663 *input_line_pointer
= c
;
7664 input_line_pointer
= save
;
7670 i386_parse_name (char *name
, expressionS
*e
, char *nextcharP
)
7673 char *end
= input_line_pointer
;
7676 r
= parse_register (name
, &input_line_pointer
);
7677 if (r
&& end
<= input_line_pointer
)
7679 *nextcharP
= *input_line_pointer
;
7680 *input_line_pointer
= 0;
7681 e
->X_op
= O_register
;
7682 e
->X_add_number
= r
- i386_regtab
;
7685 input_line_pointer
= end
;
7687 return intel_syntax
? i386_intel_parse_name (name
, e
) : 0;
7691 md_operand (expressionS
*e
)
7696 switch (*input_line_pointer
)
7698 case REGISTER_PREFIX
:
7699 r
= parse_real_register (input_line_pointer
, &end
);
7702 e
->X_op
= O_register
;
7703 e
->X_add_number
= r
- i386_regtab
;
7704 input_line_pointer
= end
;
7709 gas_assert (intel_syntax
);
7710 end
= input_line_pointer
++;
7712 if (*input_line_pointer
== ']')
7714 ++input_line_pointer
;
7715 e
->X_op_symbol
= make_expr_symbol (e
);
7716 e
->X_add_symbol
= NULL
;
7717 e
->X_add_number
= 0;
7723 input_line_pointer
= end
;
7730 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7731 const char *md_shortopts
= "kVQ:sqn";
7733 const char *md_shortopts
= "qn";
7736 #define OPTION_32 (OPTION_MD_BASE + 0)
7737 #define OPTION_64 (OPTION_MD_BASE + 1)
7738 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
7739 #define OPTION_MARCH (OPTION_MD_BASE + 3)
7740 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
7741 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
7742 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
7743 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
7744 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
7745 #define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
7746 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
7747 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
7749 struct option md_longopts
[] =
7751 {"32", no_argument
, NULL
, OPTION_32
},
7752 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
7753 || defined (TE_PE) || defined (TE_PEP))
7754 {"64", no_argument
, NULL
, OPTION_64
},
7756 {"divide", no_argument
, NULL
, OPTION_DIVIDE
},
7757 {"march", required_argument
, NULL
, OPTION_MARCH
},
7758 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
7759 {"mmnemonic", required_argument
, NULL
, OPTION_MMNEMONIC
},
7760 {"msyntax", required_argument
, NULL
, OPTION_MSYNTAX
},
7761 {"mindex-reg", no_argument
, NULL
, OPTION_MINDEX_REG
},
7762 {"mnaked-reg", no_argument
, NULL
, OPTION_MNAKED_REG
},
7763 {"mold-gcc", no_argument
, NULL
, OPTION_MOLD_GCC
},
7764 {"msse2avx", no_argument
, NULL
, OPTION_MSSE2AVX
},
7765 {"msse-check", required_argument
, NULL
, OPTION_MSSE_CHECK
},
7766 {NULL
, no_argument
, NULL
, 0}
7768 size_t md_longopts_size
= sizeof (md_longopts
);
7771 md_parse_option (int c
, char *arg
)
7779 optimize_align_code
= 0;
7786 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7787 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
7788 should be emitted or not. FIXME: Not implemented. */
7792 /* -V: SVR4 argument to print version ID. */
7794 print_version_id ();
7797 /* -k: Ignore for FreeBSD compatibility. */
7802 /* -s: On i386 Solaris, this tells the native assembler to use
7803 .stab instead of .stab.excl. We always use .stab anyhow. */
7806 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
7807 || defined (TE_PE) || defined (TE_PEP))
7810 const char **list
, **l
;
7812 list
= bfd_target_list ();
7813 for (l
= list
; *l
!= NULL
; l
++)
7814 if (CONST_STRNEQ (*l
, "elf64-x86-64")
7815 || strcmp (*l
, "coff-x86-64") == 0
7816 || strcmp (*l
, "pe-x86-64") == 0
7817 || strcmp (*l
, "pei-x86-64") == 0)
7819 default_arch
= "x86_64";
7823 as_fatal (_("No compiled in support for x86_64"));
7830 default_arch
= "i386";
7834 #ifdef SVR4_COMMENT_CHARS
7839 n
= (char *) xmalloc (strlen (i386_comment_chars
) + 1);
7841 for (s
= i386_comment_chars
; *s
!= '\0'; s
++)
7845 i386_comment_chars
= n
;
7851 arch
= xstrdup (arg
);
7855 as_fatal (_("Invalid -march= option: `%s'"), arg
);
7856 next
= strchr (arch
, '+');
7859 for (i
= 0; i
< ARRAY_SIZE (cpu_arch
); i
++)
7861 if (strcmp (arch
, cpu_arch
[i
].name
) == 0)
7864 cpu_arch_name
= cpu_arch
[i
].name
;
7865 cpu_sub_arch_name
= NULL
;
7866 cpu_arch_flags
= cpu_arch
[i
].flags
;
7867 cpu_arch_isa
= cpu_arch
[i
].type
;
7868 cpu_arch_isa_flags
= cpu_arch
[i
].flags
;
7869 if (!cpu_arch_tune_set
)
7871 cpu_arch_tune
= cpu_arch_isa
;
7872 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
7876 else if (*cpu_arch
[i
].name
== '.'
7877 && strcmp (arch
, cpu_arch
[i
].name
+ 1) == 0)
7879 /* ISA entension. */
7880 i386_cpu_flags flags
;
7882 if (strncmp (arch
, "no", 2))
7883 flags
= cpu_flags_or (cpu_arch_flags
,
7886 flags
= cpu_flags_and_not (cpu_arch_flags
,
7888 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
7890 if (cpu_sub_arch_name
)
7892 char *name
= cpu_sub_arch_name
;
7893 cpu_sub_arch_name
= concat (name
,
7895 (const char *) NULL
);
7899 cpu_sub_arch_name
= xstrdup (cpu_arch
[i
].name
);
7900 cpu_arch_flags
= flags
;
7906 if (i
>= ARRAY_SIZE (cpu_arch
))
7907 as_fatal (_("Invalid -march= option: `%s'"), arg
);
7911 while (next
!= NULL
);
7916 as_fatal (_("Invalid -mtune= option: `%s'"), arg
);
7917 for (i
= 0; i
< ARRAY_SIZE (cpu_arch
); i
++)
7919 if (strcmp (arg
, cpu_arch
[i
].name
) == 0)
7921 cpu_arch_tune_set
= 1;
7922 cpu_arch_tune
= cpu_arch
[i
].type
;
7923 cpu_arch_tune_flags
= cpu_arch
[i
].flags
;
7927 if (i
>= ARRAY_SIZE (cpu_arch
))
7928 as_fatal (_("Invalid -mtune= option: `%s'"), arg
);
7931 case OPTION_MMNEMONIC
:
7932 if (strcasecmp (arg
, "att") == 0)
7934 else if (strcasecmp (arg
, "intel") == 0)
7937 as_fatal (_("Invalid -mmnemonic= option: `%s'"), arg
);
7940 case OPTION_MSYNTAX
:
7941 if (strcasecmp (arg
, "att") == 0)
7943 else if (strcasecmp (arg
, "intel") == 0)
7946 as_fatal (_("Invalid -msyntax= option: `%s'"), arg
);
7949 case OPTION_MINDEX_REG
:
7950 allow_index_reg
= 1;
7953 case OPTION_MNAKED_REG
:
7954 allow_naked_reg
= 1;
7957 case OPTION_MOLD_GCC
:
7961 case OPTION_MSSE2AVX
:
7965 case OPTION_MSSE_CHECK
:
7966 if (strcasecmp (arg
, "error") == 0)
7967 sse_check
= sse_check_error
;
7968 else if (strcasecmp (arg
, "warning") == 0)
7969 sse_check
= sse_check_warning
;
7970 else if (strcasecmp (arg
, "none") == 0)
7971 sse_check
= sse_check_none
;
7973 as_fatal (_("Invalid -msse-check= option: `%s'"), arg
);
7983 md_show_usage (stream
)
7986 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7987 fprintf (stream
, _("\
7989 -V print assembler version number\n\
7992 fprintf (stream
, _("\
7993 -n Do not optimize code alignment\n\
7994 -q quieten some warnings\n"));
7995 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7996 fprintf (stream
, _("\
7999 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
8000 || defined (TE_PE) || defined (TE_PEP))
8001 fprintf (stream
, _("\
8002 --32/--64 generate 32bit/64bit code\n"));
8004 #ifdef SVR4_COMMENT_CHARS
8005 fprintf (stream
, _("\
8006 --divide do not treat `/' as a comment character\n"));
8008 fprintf (stream
, _("\
8009 --divide ignored\n"));
8011 fprintf (stream
, _("\
8012 -march=CPU[,+EXTENSION...]\n\
8013 generate code for CPU and EXTENSION, CPU is one of:\n\
8014 i8086, i186, i286, i386, i486, pentium, pentiumpro,\n\
8015 pentiumii, pentiumiii, pentium4, prescott, nocona,\n\
8016 core, core2, corei7, l1om, k6, k6_2, athlon, k8,\n\
8017 amdfam10, generic32, generic64\n\
8018 EXTENSION is combination of:\n\
8019 8087, 287, 387, no87, mmx, nommx, sse, sse2, sse3,\n\
8020 ssse3, sse4.1, sse4.2, sse4, nosse, avx, noavx,\n\
8021 vmx, smx, xsave, movbe, ept, aes, pclmul, fma,\n\
8022 clflush, syscall, rdtscp, 3dnow, 3dnowa, sse4a,\n\
8023 svme, abm, padlock, fma4\n"));
8024 fprintf (stream
, _("\
8025 -mtune=CPU optimize for CPU, CPU is one of:\n\
8026 i8086, i186, i286, i386, i486, pentium, pentiumpro,\n\
8027 pentiumii, pentiumiii, pentium4, prescott, nocona,\n\
8028 core, core2, corei7, l1om, k6, k6_2, athlon, k8,\n\
8029 amdfam10, generic32, generic64\n"));
8030 fprintf (stream
, _("\
8031 -msse2avx encode SSE instructions with VEX prefix\n"));
8032 fprintf (stream
, _("\
8033 -msse-check=[none|error|warning]\n\
8034 check SSE instructions\n"));
8035 fprintf (stream
, _("\
8036 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
8037 fprintf (stream
, _("\
8038 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
8039 fprintf (stream
, _("\
8040 -mindex-reg support pseudo index registers\n"));
8041 fprintf (stream
, _("\
8042 -mnaked-reg don't require `%%' prefix for registers\n"));
8043 fprintf (stream
, _("\
8044 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
8047 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
8048 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
8049 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
8051 /* Pick the target format to use. */
8054 i386_target_format (void)
8056 if (!strcmp (default_arch
, "x86_64"))
8058 set_code_flag (CODE_64BIT
);
8059 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
8061 cpu_arch_isa_flags
.bitfield
.cpui186
= 1;
8062 cpu_arch_isa_flags
.bitfield
.cpui286
= 1;
8063 cpu_arch_isa_flags
.bitfield
.cpui386
= 1;
8064 cpu_arch_isa_flags
.bitfield
.cpui486
= 1;
8065 cpu_arch_isa_flags
.bitfield
.cpui586
= 1;
8066 cpu_arch_isa_flags
.bitfield
.cpui686
= 1;
8067 cpu_arch_isa_flags
.bitfield
.cpuclflush
= 1;
8068 cpu_arch_isa_flags
.bitfield
.cpummx
= 1;
8069 cpu_arch_isa_flags
.bitfield
.cpusse
= 1;
8070 cpu_arch_isa_flags
.bitfield
.cpusse2
= 1;
8071 cpu_arch_isa_flags
.bitfield
.cpulm
= 1;
8073 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
8075 cpu_arch_tune_flags
.bitfield
.cpui186
= 1;
8076 cpu_arch_tune_flags
.bitfield
.cpui286
= 1;
8077 cpu_arch_tune_flags
.bitfield
.cpui386
= 1;
8078 cpu_arch_tune_flags
.bitfield
.cpui486
= 1;
8079 cpu_arch_tune_flags
.bitfield
.cpui586
= 1;
8080 cpu_arch_tune_flags
.bitfield
.cpui686
= 1;
8081 cpu_arch_tune_flags
.bitfield
.cpuclflush
= 1;
8082 cpu_arch_tune_flags
.bitfield
.cpummx
= 1;
8083 cpu_arch_tune_flags
.bitfield
.cpusse
= 1;
8084 cpu_arch_tune_flags
.bitfield
.cpusse2
= 1;
8087 else if (!strcmp (default_arch
, "i386"))
8089 set_code_flag (CODE_32BIT
);
8090 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
8092 cpu_arch_isa_flags
.bitfield
.cpui186
= 1;
8093 cpu_arch_isa_flags
.bitfield
.cpui286
= 1;
8094 cpu_arch_isa_flags
.bitfield
.cpui386
= 1;
8096 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
8098 cpu_arch_tune_flags
.bitfield
.cpui186
= 1;
8099 cpu_arch_tune_flags
.bitfield
.cpui286
= 1;
8100 cpu_arch_tune_flags
.bitfield
.cpui386
= 1;
8104 as_fatal (_("Unknown architecture"));
8105 switch (OUTPUT_FLAVOR
)
8107 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
8108 case bfd_target_aout_flavour
:
8109 return AOUT_TARGET_FORMAT
;
8111 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
8112 # if defined (TE_PE) || defined (TE_PEP)
8113 case bfd_target_coff_flavour
:
8114 return flag_code
== CODE_64BIT
? "pe-x86-64" : "pe-i386";
8115 # elif defined (TE_GO32)
8116 case bfd_target_coff_flavour
:
8119 case bfd_target_coff_flavour
:
8123 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
8124 case bfd_target_elf_flavour
:
8126 if (flag_code
== CODE_64BIT
)
8129 use_rela_relocations
= 1;
8131 if (cpu_arch_isa
== PROCESSOR_L1OM
)
8133 if (flag_code
!= CODE_64BIT
)
8134 as_fatal (_("Intel L1OM is 64bit only"));
8135 return ELF_TARGET_L1OM_FORMAT
;
8138 return (flag_code
== CODE_64BIT
8139 ? ELF_TARGET_FORMAT64
: ELF_TARGET_FORMAT
);
8142 #if defined (OBJ_MACH_O)
8143 case bfd_target_mach_o_flavour
:
8144 return flag_code
== CODE_64BIT
? "mach-o-x86-64" : "mach-o-i386";
8152 #endif /* OBJ_MAYBE_ more than one */
8154 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
8156 i386_elf_emit_arch_note (void)
8158 if (IS_ELF
&& cpu_arch_name
!= NULL
)
8161 asection
*seg
= now_seg
;
8162 subsegT subseg
= now_subseg
;
8163 Elf_Internal_Note i_note
;
8164 Elf_External_Note e_note
;
8165 asection
*note_secp
;
8168 /* Create the .note section. */
8169 note_secp
= subseg_new (".note", 0);
8170 bfd_set_section_flags (stdoutput
,
8172 SEC_HAS_CONTENTS
| SEC_READONLY
);
8174 /* Process the arch string. */
8175 len
= strlen (cpu_arch_name
);
8177 i_note
.namesz
= len
+ 1;
8179 i_note
.type
= NT_ARCH
;
8180 p
= frag_more (sizeof (e_note
.namesz
));
8181 md_number_to_chars (p
, (valueT
) i_note
.namesz
, sizeof (e_note
.namesz
));
8182 p
= frag_more (sizeof (e_note
.descsz
));
8183 md_number_to_chars (p
, (valueT
) i_note
.descsz
, sizeof (e_note
.descsz
));
8184 p
= frag_more (sizeof (e_note
.type
));
8185 md_number_to_chars (p
, (valueT
) i_note
.type
, sizeof (e_note
.type
));
8186 p
= frag_more (len
+ 1);
8187 strcpy (p
, cpu_arch_name
);
8189 frag_align (2, 0, 0);
8191 subseg_set (seg
, subseg
);
8197 md_undefined_symbol (name
)
8200 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
8201 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
8202 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
8203 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
8207 if (symbol_find (name
))
8208 as_bad (_("GOT already in symbol table"));
8209 GOT_symbol
= symbol_new (name
, undefined_section
,
8210 (valueT
) 0, &zero_address_frag
);
8217 /* Round up a section size to the appropriate boundary. */
8220 md_section_align (segment
, size
)
8221 segT segment ATTRIBUTE_UNUSED
;
8224 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8225 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
8227 /* For a.out, force the section size to be aligned. If we don't do
8228 this, BFD will align it for us, but it will not write out the
8229 final bytes of the section. This may be a bug in BFD, but it is
8230 easier to fix it here since that is how the other a.out targets
8234 align
= bfd_get_section_alignment (stdoutput
, segment
);
8235 size
= ((size
+ (1 << align
) - 1) & ((valueT
) -1 << align
));
8242 /* On the i386, PC-relative offsets are relative to the start of the
8243 next instruction. That is, the address of the offset, plus its
8244 size, since the offset is always the last part of the insn. */
8247 md_pcrel_from (fixS
*fixP
)
8249 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
8255 s_bss (int ignore ATTRIBUTE_UNUSED
)
8259 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8261 obj_elf_section_change_hook ();
8263 temp
= get_absolute_expression ();
8264 subseg_set (bss_section
, (subsegT
) temp
);
8265 demand_empty_rest_of_line ();
8271 i386_validate_fix (fixS
*fixp
)
8273 if (fixp
->fx_subsy
&& fixp
->fx_subsy
== GOT_symbol
)
8275 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
8279 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
8284 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
8286 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
8293 tc_gen_reloc (section
, fixp
)
8294 asection
*section ATTRIBUTE_UNUSED
;
8298 bfd_reloc_code_real_type code
;
8300 switch (fixp
->fx_r_type
)
8302 case BFD_RELOC_X86_64_PLT32
:
8303 case BFD_RELOC_X86_64_GOT32
:
8304 case BFD_RELOC_X86_64_GOTPCREL
:
8305 case BFD_RELOC_386_PLT32
:
8306 case BFD_RELOC_386_GOT32
:
8307 case BFD_RELOC_386_GOTOFF
:
8308 case BFD_RELOC_386_GOTPC
:
8309 case BFD_RELOC_386_TLS_GD
:
8310 case BFD_RELOC_386_TLS_LDM
:
8311 case BFD_RELOC_386_TLS_LDO_32
:
8312 case BFD_RELOC_386_TLS_IE_32
:
8313 case BFD_RELOC_386_TLS_IE
:
8314 case BFD_RELOC_386_TLS_GOTIE
:
8315 case BFD_RELOC_386_TLS_LE_32
:
8316 case BFD_RELOC_386_TLS_LE
:
8317 case BFD_RELOC_386_TLS_GOTDESC
:
8318 case BFD_RELOC_386_TLS_DESC_CALL
:
8319 case BFD_RELOC_X86_64_TLSGD
:
8320 case BFD_RELOC_X86_64_TLSLD
:
8321 case BFD_RELOC_X86_64_DTPOFF32
:
8322 case BFD_RELOC_X86_64_DTPOFF64
:
8323 case BFD_RELOC_X86_64_GOTTPOFF
:
8324 case BFD_RELOC_X86_64_TPOFF32
:
8325 case BFD_RELOC_X86_64_TPOFF64
:
8326 case BFD_RELOC_X86_64_GOTOFF64
:
8327 case BFD_RELOC_X86_64_GOTPC32
:
8328 case BFD_RELOC_X86_64_GOT64
:
8329 case BFD_RELOC_X86_64_GOTPCREL64
:
8330 case BFD_RELOC_X86_64_GOTPC64
:
8331 case BFD_RELOC_X86_64_GOTPLT64
:
8332 case BFD_RELOC_X86_64_PLTOFF64
:
8333 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
8334 case BFD_RELOC_X86_64_TLSDESC_CALL
:
8336 case BFD_RELOC_VTABLE_ENTRY
:
8337 case BFD_RELOC_VTABLE_INHERIT
:
8339 case BFD_RELOC_32_SECREL
:
8341 code
= fixp
->fx_r_type
;
8343 case BFD_RELOC_X86_64_32S
:
8344 if (!fixp
->fx_pcrel
)
8346 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
8347 code
= fixp
->fx_r_type
;
8353 switch (fixp
->fx_size
)
8356 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
8357 _("can not do %d byte pc-relative relocation"),
8359 code
= BFD_RELOC_32_PCREL
;
8361 case 1: code
= BFD_RELOC_8_PCREL
; break;
8362 case 2: code
= BFD_RELOC_16_PCREL
; break;
8363 case 4: code
= BFD_RELOC_32_PCREL
; break;
8365 case 8: code
= BFD_RELOC_64_PCREL
; break;
8371 switch (fixp
->fx_size
)
8374 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
8375 _("can not do %d byte relocation"),
8377 code
= BFD_RELOC_32
;
8379 case 1: code
= BFD_RELOC_8
; break;
8380 case 2: code
= BFD_RELOC_16
; break;
8381 case 4: code
= BFD_RELOC_32
; break;
8383 case 8: code
= BFD_RELOC_64
; break;
8390 if ((code
== BFD_RELOC_32
8391 || code
== BFD_RELOC_32_PCREL
8392 || code
== BFD_RELOC_X86_64_32S
)
8394 && fixp
->fx_addsy
== GOT_symbol
)
8397 code
= BFD_RELOC_386_GOTPC
;
8399 code
= BFD_RELOC_X86_64_GOTPC32
;
8401 if ((code
== BFD_RELOC_64
|| code
== BFD_RELOC_64_PCREL
)
8403 && fixp
->fx_addsy
== GOT_symbol
)
8405 code
= BFD_RELOC_X86_64_GOTPC64
;
8408 rel
= (arelent
*) xmalloc (sizeof (arelent
));
8409 rel
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
8410 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
8412 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
8414 if (!use_rela_relocations
)
8416 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
8417 vtable entry to be used in the relocation's section offset. */
8418 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
8419 rel
->address
= fixp
->fx_offset
;
8420 #if defined (OBJ_COFF) && defined (TE_PE)
8421 else if (fixp
->fx_addsy
&& S_IS_WEAK (fixp
->fx_addsy
))
8422 rel
->addend
= fixp
->fx_addnumber
- (S_GET_VALUE (fixp
->fx_addsy
) * 2);
8427 /* Use the rela in 64bit mode. */
8430 if (!fixp
->fx_pcrel
)
8431 rel
->addend
= fixp
->fx_offset
;
8435 case BFD_RELOC_X86_64_PLT32
:
8436 case BFD_RELOC_X86_64_GOT32
:
8437 case BFD_RELOC_X86_64_GOTPCREL
:
8438 case BFD_RELOC_X86_64_TLSGD
:
8439 case BFD_RELOC_X86_64_TLSLD
:
8440 case BFD_RELOC_X86_64_GOTTPOFF
:
8441 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
8442 case BFD_RELOC_X86_64_TLSDESC_CALL
:
8443 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
8446 rel
->addend
= (section
->vma
8448 + fixp
->fx_addnumber
8449 + md_pcrel_from (fixp
));
8454 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
8455 if (rel
->howto
== NULL
)
8457 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
8458 _("cannot represent relocation type %s"),
8459 bfd_get_reloc_code_name (code
));
8460 /* Set howto to a garbage value so that we can keep going. */
8461 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
8462 gas_assert (rel
->howto
!= NULL
);
8468 #include "tc-i386-intel.c"
8471 tc_x86_parse_to_dw2regnum (expressionS
*exp
)
8473 int saved_naked_reg
;
8474 char saved_register_dot
;
8476 saved_naked_reg
= allow_naked_reg
;
8477 allow_naked_reg
= 1;
8478 saved_register_dot
= register_chars
['.'];
8479 register_chars
['.'] = '.';
8480 allow_pseudo_reg
= 1;
8481 expression_and_evaluate (exp
);
8482 allow_pseudo_reg
= 0;
8483 register_chars
['.'] = saved_register_dot
;
8484 allow_naked_reg
= saved_naked_reg
;
8486 if (exp
->X_op
== O_register
&& exp
->X_add_number
>= 0)
8488 if ((addressT
) exp
->X_add_number
< i386_regtab_size
)
8490 exp
->X_op
= O_constant
;
8491 exp
->X_add_number
= i386_regtab
[exp
->X_add_number
]
8492 .dw2_regnum
[flag_code
>> 1];
8495 exp
->X_op
= O_illegal
;
8500 tc_x86_frame_initial_instructions (void)
8502 static unsigned int sp_regno
[2];
8504 if (!sp_regno
[flag_code
>> 1])
8506 char *saved_input
= input_line_pointer
;
8507 char sp
[][4] = {"esp", "rsp"};
8510 input_line_pointer
= sp
[flag_code
>> 1];
8511 tc_x86_parse_to_dw2regnum (&exp
);
8512 gas_assert (exp
.X_op
== O_constant
);
8513 sp_regno
[flag_code
>> 1] = exp
.X_add_number
;
8514 input_line_pointer
= saved_input
;
8517 cfi_add_CFA_def_cfa (sp_regno
[flag_code
>> 1], -x86_cie_data_alignment
);
8518 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
8522 i386_elf_section_type (const char *str
, size_t len
)
8524 if (flag_code
== CODE_64BIT
8525 && len
== sizeof ("unwind") - 1
8526 && strncmp (str
, "unwind", 6) == 0)
8527 return SHT_X86_64_UNWIND
;
8534 i386_solaris_fix_up_eh_frame (segT sec
)
8536 if (flag_code
== CODE_64BIT
)
8537 elf_section_type (sec
) = SHT_X86_64_UNWIND
;
8543 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
8547 expr
.X_op
= O_secrel
;
8548 expr
.X_add_symbol
= symbol
;
8549 expr
.X_add_number
= 0;
8550 emit_expr (&expr
, size
);
8554 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8555 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
8558 x86_64_section_letter (int letter
, char **ptr_msg
)
8560 if (flag_code
== CODE_64BIT
)
8563 return SHF_X86_64_LARGE
;
8565 *ptr_msg
= _("Bad .section directive: want a,l,w,x,M,S,G,T in string");
8568 *ptr_msg
= _("Bad .section directive: want a,w,x,M,S,G,T in string");
8573 x86_64_section_word (char *str
, size_t len
)
8575 if (len
== 5 && flag_code
== CODE_64BIT
&& CONST_STRNEQ (str
, "large"))
8576 return SHF_X86_64_LARGE
;
8582 handle_large_common (int small ATTRIBUTE_UNUSED
)
8584 if (flag_code
!= CODE_64BIT
)
8586 s_comm_internal (0, elf_common_parse
);
8587 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
8591 static segT lbss_section
;
8592 asection
*saved_com_section_ptr
= elf_com_section_ptr
;
8593 asection
*saved_bss_section
= bss_section
;
8595 if (lbss_section
== NULL
)
8597 flagword applicable
;
8599 subsegT subseg
= now_subseg
;
8601 /* The .lbss section is for local .largecomm symbols. */
8602 lbss_section
= subseg_new (".lbss", 0);
8603 applicable
= bfd_applicable_section_flags (stdoutput
);
8604 bfd_set_section_flags (stdoutput
, lbss_section
,
8605 applicable
& SEC_ALLOC
);
8606 seg_info (lbss_section
)->bss
= 1;
8608 subseg_set (seg
, subseg
);
8611 elf_com_section_ptr
= &_bfd_elf_large_com_section
;
8612 bss_section
= lbss_section
;
8614 s_comm_internal (0, elf_common_parse
);
8616 elf_com_section_ptr
= saved_com_section_ptr
;
8617 bss_section
= saved_bss_section
;
8620 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */