1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright (C) 1989-2020 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 /* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
23 x86_64 support by Jan Hubicka (jh@suse.cz)
24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
29 #include "safe-ctype.h"
31 #include "dwarf2dbg.h"
32 #include "dw2gencfi.h"
33 #include "elf/x86-64.h"
34 #include "opcodes/i386-init.h"
39 #ifdef HAVE_SYS_PARAM_H
40 #include <sys/param.h>
43 #define INT_MAX (int) (((unsigned) (-1)) >> 1)
47 #ifndef INFER_ADDR_PREFIX
48 #define INFER_ADDR_PREFIX 1
52 #define DEFAULT_ARCH "i386"
57 #define INLINE __inline__
63 /* Prefixes will be emitted in the order defined below.
64 WAIT_PREFIX must be the first prefix since FWAIT is really is an
65 instruction, and so must come before any prefixes.
66 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
67 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
73 #define HLE_PREFIX REP_PREFIX
74 #define BND_PREFIX REP_PREFIX
76 #define REX_PREFIX 6 /* must come last. */
77 #define MAX_PREFIXES 7 /* max prefixes per opcode */
79 /* we define the syntax here (modulo base,index,scale syntax) */
80 #define REGISTER_PREFIX '%'
81 #define IMMEDIATE_PREFIX '$'
82 #define ABSOLUTE_PREFIX '*'
84 /* these are the instruction mnemonic suffixes in AT&T syntax or
85 memory operand size in Intel syntax. */
86 #define WORD_MNEM_SUFFIX 'w'
87 #define BYTE_MNEM_SUFFIX 'b'
88 #define SHORT_MNEM_SUFFIX 's'
89 #define LONG_MNEM_SUFFIX 'l'
90 #define QWORD_MNEM_SUFFIX 'q'
91 /* Intel Syntax. Use a non-ascii letter since since it never appears
93 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
95 #define END_OF_INSN '\0'
97 /* This matches the C -> StaticRounding alias in the opcode table. */
98 #define commutative staticrounding
101 'templates' is for grouping together 'template' structures for opcodes
102 of the same name. This is only used for storing the insns in the grand
103 ole hash table of insns.
104 The templates themselves start at START and range up to (but not including)
109 const insn_template
*start
;
110 const insn_template
*end
;
114 /* 386 operand encoding bytes: see 386 book for details of this. */
117 unsigned int regmem
; /* codes register or memory operand */
118 unsigned int reg
; /* codes register operand (or extended opcode) */
119 unsigned int mode
; /* how to interpret regmem & reg */
123 /* x86-64 extension prefix. */
124 typedef int rex_byte
;
126 /* 386 opcode byte to code indirect addressing. */
135 /* x86 arch names, types and features */
138 const char *name
; /* arch name */
139 unsigned int len
; /* arch string length */
140 enum processor_type type
; /* arch type */
141 i386_cpu_flags flags
; /* cpu feature flags */
142 unsigned int skip
; /* show_arch should skip this. */
146 /* Used to turn off indicated flags. */
149 const char *name
; /* arch name */
150 unsigned int len
; /* arch string length */
151 i386_cpu_flags flags
; /* cpu feature flags */
155 static void update_code_flag (int, int);
156 static void set_code_flag (int);
157 static void set_16bit_gcc_code_flag (int);
158 static void set_intel_syntax (int);
159 static void set_intel_mnemonic (int);
160 static void set_allow_index_reg (int);
161 static void set_check (int);
162 static void set_cpu_arch (int);
164 static void pe_directive_secrel (int);
166 static void signed_cons (int);
167 static char *output_invalid (int c
);
168 static int i386_finalize_immediate (segT
, expressionS
*, i386_operand_type
,
170 static int i386_finalize_displacement (segT
, expressionS
*, i386_operand_type
,
172 static int i386_att_operand (char *);
173 static int i386_intel_operand (char *, int);
174 static int i386_intel_simplify (expressionS
*);
175 static int i386_intel_parse_name (const char *, expressionS
*);
176 static const reg_entry
*parse_register (char *, char **);
177 static char *parse_insn (char *, char *);
178 static char *parse_operands (char *, const char *);
179 static void swap_operands (void);
180 static void swap_2_operands (int, int);
181 static enum flag_code
i386_addressing_mode (void);
182 static void optimize_imm (void);
183 static void optimize_disp (void);
184 static const insn_template
*match_template (char);
185 static int check_string (void);
186 static int process_suffix (void);
187 static int check_byte_reg (void);
188 static int check_long_reg (void);
189 static int check_qword_reg (void);
190 static int check_word_reg (void);
191 static int finalize_imm (void);
192 static int process_operands (void);
193 static const seg_entry
*build_modrm_byte (void);
194 static void output_insn (void);
195 static void output_imm (fragS
*, offsetT
);
196 static void output_disp (fragS
*, offsetT
);
198 static void s_bss (int);
200 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
201 static void handle_large_common (int small ATTRIBUTE_UNUSED
);
203 /* GNU_PROPERTY_X86_ISA_1_USED. */
204 static unsigned int x86_isa_1_used
;
205 /* GNU_PROPERTY_X86_FEATURE_2_USED. */
206 static unsigned int x86_feature_2_used
;
207 /* Generate x86 used ISA and feature properties. */
208 static unsigned int x86_used_note
= DEFAULT_X86_USED_NOTE
;
211 static const char *default_arch
= DEFAULT_ARCH
;
213 /* parse_register() returns this when a register alias cannot be used. */
214 static const reg_entry bad_reg
= { "<bad>", OPERAND_TYPE_NONE
, 0, 0,
215 { Dw2Inval
, Dw2Inval
} };
217 /* This struct describes rounding control and SAE in the instruction. */
231 static struct RC_Operation rc_op
;
233 /* The struct describes masking, applied to OPERAND in the instruction.
234 MASK is a pointer to the corresponding mask register. ZEROING tells
235 whether merging or zeroing mask is used. */
236 struct Mask_Operation
238 const reg_entry
*mask
;
239 unsigned int zeroing
;
240 /* The operand where this operation is associated. */
244 static struct Mask_Operation mask_op
;
246 /* The struct describes broadcasting, applied to OPERAND. FACTOR is
248 struct Broadcast_Operation
250 /* Type of broadcast: {1to2}, {1to4}, {1to8}, or {1to16}. */
253 /* Index of broadcasted operand. */
256 /* Number of bytes to broadcast. */
260 static struct Broadcast_Operation broadcast_op
;
265 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
266 unsigned char bytes
[4];
268 /* Destination or source register specifier. */
269 const reg_entry
*register_specifier
;
272 /* 'md_assemble ()' gathers together information and puts it into a
279 const reg_entry
*regs
;
284 operand_size_mismatch
,
285 operand_type_mismatch
,
286 register_type_mismatch
,
287 number_of_operands_mismatch
,
288 invalid_instruction_suffix
,
290 unsupported_with_intel_mnemonic
,
293 invalid_vsib_address
,
294 invalid_vector_register_set
,
295 unsupported_vector_index_register
,
296 unsupported_broadcast
,
299 mask_not_on_destination
,
302 rc_sae_operand_not_last_imm
,
303 invalid_register_operand
,
308 /* TM holds the template for the insn were currently assembling. */
311 /* SUFFIX holds the instruction size suffix for byte, word, dword
312 or qword, if given. */
315 /* OPERANDS gives the number of given operands. */
316 unsigned int operands
;
318 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
319 of given register, displacement, memory operands and immediate
321 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
323 /* TYPES [i] is the type (see above #defines) which tells us how to
324 use OP[i] for the corresponding operand. */
325 i386_operand_type types
[MAX_OPERANDS
];
327 /* Displacement expression, immediate expression, or register for each
329 union i386_op op
[MAX_OPERANDS
];
331 /* Flags for operands. */
332 unsigned int flags
[MAX_OPERANDS
];
333 #define Operand_PCrel 1
334 #define Operand_Mem 2
336 /* Relocation type for operand */
337 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
339 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
340 the base index byte below. */
341 const reg_entry
*base_reg
;
342 const reg_entry
*index_reg
;
343 unsigned int log2_scale_factor
;
345 /* SEG gives the seg_entries of this insn. They are zero unless
346 explicit segment overrides are given. */
347 const seg_entry
*seg
[2];
349 /* Copied first memory operand string, for re-checking. */
352 /* PREFIX holds all the given prefix opcodes (usually null).
353 PREFIXES is the number of prefix opcodes. */
354 unsigned int prefixes
;
355 unsigned char prefix
[MAX_PREFIXES
];
357 /* Register is in low 3 bits of opcode. */
358 bfd_boolean short_form
;
360 /* The operand to a branch insn indicates an absolute branch. */
361 bfd_boolean jumpabsolute
;
363 /* Has MMX register operands. */
364 bfd_boolean has_regmmx
;
366 /* Has XMM register operands. */
367 bfd_boolean has_regxmm
;
369 /* Has YMM register operands. */
370 bfd_boolean has_regymm
;
372 /* Has ZMM register operands. */
373 bfd_boolean has_regzmm
;
375 /* Has GOTPC or TLS relocation. */
376 bfd_boolean has_gotpc_tls_reloc
;
378 /* RM and SIB are the modrm byte and the sib byte where the
379 addressing modes of this insn are encoded. */
386 /* Masking attributes. */
387 struct Mask_Operation
*mask
;
389 /* Rounding control and SAE attributes. */
390 struct RC_Operation
*rounding
;
392 /* Broadcasting attributes. */
393 struct Broadcast_Operation
*broadcast
;
395 /* Compressed disp8*N attribute. */
396 unsigned int memshift
;
398 /* Prefer load or store in encoding. */
401 dir_encoding_default
= 0,
407 /* Prefer 8bit or 32bit displacement in encoding. */
410 disp_encoding_default
= 0,
415 /* Prefer the REX byte in encoding. */
416 bfd_boolean rex_encoding
;
418 /* Disable instruction size optimization. */
419 bfd_boolean no_optimize
;
421 /* How to encode vector instructions. */
424 vex_encoding_default
= 0,
432 const char *rep_prefix
;
435 const char *hle_prefix
;
437 /* Have BND prefix. */
438 const char *bnd_prefix
;
440 /* Have NOTRACK prefix. */
441 const char *notrack_prefix
;
444 enum i386_error error
;
447 typedef struct _i386_insn i386_insn
;
449 /* Link RC type with corresponding string, that'll be looked for in
458 static const struct RC_name RC_NamesTable
[] =
460 { rne
, STRING_COMMA_LEN ("rn-sae") },
461 { rd
, STRING_COMMA_LEN ("rd-sae") },
462 { ru
, STRING_COMMA_LEN ("ru-sae") },
463 { rz
, STRING_COMMA_LEN ("rz-sae") },
464 { saeonly
, STRING_COMMA_LEN ("sae") },
467 /* List of chars besides those in app.c:symbol_chars that can start an
468 operand. Used to prevent the scrubber eating vital white-space. */
469 const char extra_symbol_chars
[] = "*%-([{}"
478 #if (defined (TE_I386AIX) \
479 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
480 && !defined (TE_GNU) \
481 && !defined (TE_LINUX) \
482 && !defined (TE_NACL) \
483 && !defined (TE_FreeBSD) \
484 && !defined (TE_DragonFly) \
485 && !defined (TE_NetBSD)))
486 /* This array holds the chars that always start a comment. If the
487 pre-processor is disabled, these aren't very useful. The option
488 --divide will remove '/' from this list. */
489 const char *i386_comment_chars
= "#/";
490 #define SVR4_COMMENT_CHARS 1
491 #define PREFIX_SEPARATOR '\\'
494 const char *i386_comment_chars
= "#";
495 #define PREFIX_SEPARATOR '/'
498 /* This array holds the chars that only start a comment at the beginning of
499 a line. If the line seems to have the form '# 123 filename'
500 .line and .file directives will appear in the pre-processed output.
501 Note that input_file.c hand checks for '#' at the beginning of the
502 first line of the input file. This is because the compiler outputs
503 #NO_APP at the beginning of its output.
504 Also note that comments started like this one will always work if
505 '/' isn't otherwise defined. */
506 const char line_comment_chars
[] = "#/";
508 const char line_separator_chars
[] = ";";
510 /* Chars that can be used to separate mant from exp in floating point
512 const char EXP_CHARS
[] = "eE";
514 /* Chars that mean this number is a floating point constant
517 const char FLT_CHARS
[] = "fFdDxX";
519 /* Tables for lexical analysis. */
520 static char mnemonic_chars
[256];
521 static char register_chars
[256];
522 static char operand_chars
[256];
523 static char identifier_chars
[256];
524 static char digit_chars
[256];
526 /* Lexical macros. */
527 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
528 #define is_operand_char(x) (operand_chars[(unsigned char) x])
529 #define is_register_char(x) (register_chars[(unsigned char) x])
530 #define is_space_char(x) ((x) == ' ')
531 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
532 #define is_digit_char(x) (digit_chars[(unsigned char) x])
534 /* All non-digit non-letter characters that may occur in an operand. */
535 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
537 /* md_assemble() always leaves the strings it's passed unaltered. To
538 effect this we maintain a stack of saved characters that we've smashed
539 with '\0's (indicating end of strings for various sub-fields of the
540 assembler instruction). */
541 static char save_stack
[32];
542 static char *save_stack_p
;
543 #define END_STRING_AND_SAVE(s) \
544 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
545 #define RESTORE_END_STRING(s) \
546 do { *(s) = *--save_stack_p; } while (0)
548 /* The instruction we're assembling. */
551 /* Possible templates for current insn. */
552 static const templates
*current_templates
;
554 /* Per instruction expressionS buffers: max displacements & immediates. */
555 static expressionS disp_expressions
[MAX_MEMORY_OPERANDS
];
556 static expressionS im_expressions
[MAX_IMMEDIATE_OPERANDS
];
558 /* Current operand we are working on. */
559 static int this_operand
= -1;
561 /* We support four different modes. FLAG_CODE variable is used to distinguish
569 static enum flag_code flag_code
;
570 static unsigned int object_64bit
;
571 static unsigned int disallow_64bit_reloc
;
572 static int use_rela_relocations
= 0;
573 /* __tls_get_addr/___tls_get_addr symbol for TLS. */
574 static const char *tls_get_addr
;
576 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
577 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
578 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
580 /* The ELF ABI to use. */
588 static enum x86_elf_abi x86_elf_abi
= I386_ABI
;
591 #if defined (TE_PE) || defined (TE_PEP)
592 /* Use big object file format. */
593 static int use_big_obj
= 0;
596 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
597 /* 1 if generating code for a shared library. */
598 static int shared
= 0;
601 /* 1 for intel syntax,
603 static int intel_syntax
= 0;
605 static enum x86_64_isa
607 amd64
= 1, /* AMD64 ISA. */
608 intel64
/* Intel64 ISA. */
611 /* 1 for intel mnemonic,
612 0 if att mnemonic. */
613 static int intel_mnemonic
= !SYSV386_COMPAT
;
615 /* 1 if pseudo registers are permitted. */
616 static int allow_pseudo_reg
= 0;
618 /* 1 if register prefix % not required. */
619 static int allow_naked_reg
= 0;
621 /* 1 if the assembler should add BND prefix for all control-transferring
622 instructions supporting it, even if this prefix wasn't specified
624 static int add_bnd_prefix
= 0;
626 /* 1 if pseudo index register, eiz/riz, is allowed . */
627 static int allow_index_reg
= 0;
629 /* 1 if the assembler should ignore LOCK prefix, even if it was
630 specified explicitly. */
631 static int omit_lock_prefix
= 0;
633 /* 1 if the assembler should encode lfence, mfence, and sfence as
634 "lock addl $0, (%{re}sp)". */
635 static int avoid_fence
= 0;
637 /* 1 if lfence should be inserted after every load. */
638 static int lfence_after_load
= 0;
640 /* Non-zero if lfence should be inserted before indirect branch. */
641 static enum lfence_before_indirect_branch_kind
643 lfence_branch_none
= 0,
644 lfence_branch_register
,
645 lfence_branch_memory
,
648 lfence_before_indirect_branch
;
650 /* Non-zero if lfence should be inserted before ret. */
651 static enum lfence_before_ret_kind
653 lfence_before_ret_none
= 0,
654 lfence_before_ret_not
,
655 lfence_before_ret_or
,
656 lfence_before_ret_shl
660 /* Types of previous instruction is .byte or prefix. */
675 /* 1 if the assembler should generate relax relocations. */
677 static int generate_relax_relocations
678 = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS
;
680 static enum check_kind
686 sse_check
, operand_check
= check_warning
;
688 /* Non-zero if branches should be aligned within power of 2 boundary. */
689 static int align_branch_power
= 0;
691 /* Types of branches to align. */
692 enum align_branch_kind
694 align_branch_none
= 0,
695 align_branch_jcc
= 1,
696 align_branch_fused
= 2,
697 align_branch_jmp
= 3,
698 align_branch_call
= 4,
699 align_branch_indirect
= 5,
703 /* Type bits of branches to align. */
704 enum align_branch_bit
706 align_branch_jcc_bit
= 1 << align_branch_jcc
,
707 align_branch_fused_bit
= 1 << align_branch_fused
,
708 align_branch_jmp_bit
= 1 << align_branch_jmp
,
709 align_branch_call_bit
= 1 << align_branch_call
,
710 align_branch_indirect_bit
= 1 << align_branch_indirect
,
711 align_branch_ret_bit
= 1 << align_branch_ret
714 static unsigned int align_branch
= (align_branch_jcc_bit
715 | align_branch_fused_bit
716 | align_branch_jmp_bit
);
718 /* Types of condition jump used by macro-fusion. */
721 mf_jcc_jo
= 0, /* base opcode 0x70 */
722 mf_jcc_jc
, /* base opcode 0x72 */
723 mf_jcc_je
, /* base opcode 0x74 */
724 mf_jcc_jna
, /* base opcode 0x76 */
725 mf_jcc_js
, /* base opcode 0x78 */
726 mf_jcc_jp
, /* base opcode 0x7a */
727 mf_jcc_jl
, /* base opcode 0x7c */
728 mf_jcc_jle
, /* base opcode 0x7e */
731 /* Types of compare flag-modifying insntructions used by macro-fusion. */
734 mf_cmp_test_and
, /* test/cmp */
735 mf_cmp_alu_cmp
, /* add/sub/cmp */
736 mf_cmp_incdec
/* inc/dec */
739 /* The maximum padding size for fused jcc. CMP like instruction can
740 be 9 bytes and jcc can be 6 bytes. Leave room just in case for
742 #define MAX_FUSED_JCC_PADDING_SIZE 20
744 /* The maximum number of prefixes added for an instruction. */
745 static unsigned int align_branch_prefix_size
= 5;
748 1. Clear the REX_W bit with register operand if possible.
749 2. Above plus use 128bit vector instruction to clear the full vector
752 static int optimize
= 0;
755 1. Clear the REX_W bit with register operand if possible.
756 2. Above plus use 128bit vector instruction to clear the full vector
758 3. Above plus optimize "test{q,l,w} $imm8,%r{64,32,16}" to
761 static int optimize_for_space
= 0;
763 /* Register prefix used for error message. */
764 static const char *register_prefix
= "%";
766 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
767 leave, push, and pop instructions so that gcc has the same stack
768 frame as in 32 bit mode. */
769 static char stackop_size
= '\0';
771 /* Non-zero to optimize code alignment. */
772 int optimize_align_code
= 1;
774 /* Non-zero to quieten some warnings. */
775 static int quiet_warnings
= 0;
778 static const char *cpu_arch_name
= NULL
;
779 static char *cpu_sub_arch_name
= NULL
;
781 /* CPU feature flags. */
782 static i386_cpu_flags cpu_arch_flags
= CPU_UNKNOWN_FLAGS
;
784 /* If we have selected a cpu we are generating instructions for. */
785 static int cpu_arch_tune_set
= 0;
787 /* Cpu we are generating instructions for. */
788 enum processor_type cpu_arch_tune
= PROCESSOR_UNKNOWN
;
790 /* CPU feature flags of cpu we are generating instructions for. */
791 static i386_cpu_flags cpu_arch_tune_flags
;
793 /* CPU instruction set architecture used. */
794 enum processor_type cpu_arch_isa
= PROCESSOR_UNKNOWN
;
796 /* CPU feature flags of instruction set architecture used. */
797 i386_cpu_flags cpu_arch_isa_flags
;
799 /* If set, conditional jumps are not automatically promoted to handle
800 larger than a byte offset. */
801 static unsigned int no_cond_jump_promotion
= 0;
803 /* Encode SSE instructions with VEX prefix. */
804 static unsigned int sse2avx
;
806 /* Encode scalar AVX instructions with specific vector length. */
813 /* Encode VEX WIG instructions with specific vex.w. */
820 /* Encode scalar EVEX LIG instructions with specific vector length. */
828 /* Encode EVEX WIG instructions with specific evex.w. */
835 /* Value to encode in EVEX RC bits, for SAE-only instructions. */
836 static enum rc_type evexrcig
= rne
;
838 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
839 static symbolS
*GOT_symbol
;
841 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
842 unsigned int x86_dwarf2_return_column
;
844 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
845 int x86_cie_data_alignment
;
847 /* Interface to relax_segment.
848 There are 3 major relax states for 386 jump insns because the
849 different types of jumps add different sizes to frags when we're
850 figuring out what sort of jump to choose to reach a given label.
852 BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING are used to align
853 branches which are handled by md_estimate_size_before_relax() and
854 i386_generic_table_relax_frag(). */
857 #define UNCOND_JUMP 0
859 #define COND_JUMP86 2
860 #define BRANCH_PADDING 3
861 #define BRANCH_PREFIX 4
862 #define FUSED_JCC_PADDING 5
867 #define SMALL16 (SMALL | CODE16)
869 #define BIG16 (BIG | CODE16)
873 #define INLINE __inline__
879 #define ENCODE_RELAX_STATE(type, size) \
880 ((relax_substateT) (((type) << 2) | (size)))
881 #define TYPE_FROM_RELAX_STATE(s) \
883 #define DISP_SIZE_FROM_RELAX_STATE(s) \
884 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
886 /* This table is used by relax_frag to promote short jumps to long
887 ones where necessary. SMALL (short) jumps may be promoted to BIG
888 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
889 don't allow a short jump in a 32 bit code segment to be promoted to
890 a 16 bit offset jump because it's slower (requires data size
891 prefix), and doesn't work, unless the destination is in the bottom
892 64k of the code segment (The top 16 bits of eip are zeroed). */
894 const relax_typeS md_relax_table
[] =
897 1) most positive reach of this state,
898 2) most negative reach of this state,
899 3) how many bytes this mode will have in the variable part of the frag
900 4) which index into the table to try if we can't fit into this one. */
902 /* UNCOND_JUMP states. */
903 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
904 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
905 /* dword jmp adds 4 bytes to frag:
906 0 extra opcode bytes, 4 displacement bytes. */
908 /* word jmp adds 2 byte2 to frag:
909 0 extra opcode bytes, 2 displacement bytes. */
912 /* COND_JUMP states. */
913 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
914 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
915 /* dword conditionals adds 5 bytes to frag:
916 1 extra opcode byte, 4 displacement bytes. */
918 /* word conditionals add 3 bytes to frag:
919 1 extra opcode byte, 2 displacement bytes. */
922 /* COND_JUMP86 states. */
923 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
924 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
925 /* dword conditionals adds 5 bytes to frag:
926 1 extra opcode byte, 4 displacement bytes. */
928 /* word conditionals add 4 bytes to frag:
929 1 displacement byte and a 3 byte long branch insn. */
933 static const arch_entry cpu_arch
[] =
935 /* Do not replace the first two entries - i386_target_format()
936 relies on them being there in this order. */
937 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32
,
938 CPU_GENERIC32_FLAGS
, 0 },
939 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64
,
940 CPU_GENERIC64_FLAGS
, 0 },
941 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN
,
943 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN
,
945 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN
,
947 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386
,
949 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486
,
951 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM
,
953 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO
,
955 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM
,
957 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO
,
958 CPU_PENTIUMPRO_FLAGS
, 0 },
959 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO
,
961 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO
,
963 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4
,
965 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA
,
967 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA
,
968 CPU_NOCONA_FLAGS
, 0 },
969 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE
,
971 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE
,
973 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2
,
974 CPU_CORE2_FLAGS
, 1 },
975 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2
,
976 CPU_CORE2_FLAGS
, 0 },
977 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7
,
978 CPU_COREI7_FLAGS
, 0 },
979 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM
,
981 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM
,
983 { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU
,
984 CPU_IAMCU_FLAGS
, 0 },
985 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6
,
987 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6
,
989 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON
,
990 CPU_ATHLON_FLAGS
, 0 },
991 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8
,
993 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8
,
995 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8
,
997 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10
,
998 CPU_AMDFAM10_FLAGS
, 0 },
999 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD
,
1000 CPU_BDVER1_FLAGS
, 0 },
1001 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD
,
1002 CPU_BDVER2_FLAGS
, 0 },
1003 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD
,
1004 CPU_BDVER3_FLAGS
, 0 },
1005 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD
,
1006 CPU_BDVER4_FLAGS
, 0 },
1007 { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER
,
1008 CPU_ZNVER1_FLAGS
, 0 },
1009 { STRING_COMMA_LEN ("znver2"), PROCESSOR_ZNVER
,
1010 CPU_ZNVER2_FLAGS
, 0 },
1011 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT
,
1012 CPU_BTVER1_FLAGS
, 0 },
1013 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT
,
1014 CPU_BTVER2_FLAGS
, 0 },
1015 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN
,
1016 CPU_8087_FLAGS
, 0 },
1017 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN
,
1019 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN
,
1021 { STRING_COMMA_LEN (".687"), PROCESSOR_UNKNOWN
,
1023 { STRING_COMMA_LEN (".cmov"), PROCESSOR_UNKNOWN
,
1024 CPU_CMOV_FLAGS
, 0 },
1025 { STRING_COMMA_LEN (".fxsr"), PROCESSOR_UNKNOWN
,
1026 CPU_FXSR_FLAGS
, 0 },
1027 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN
,
1029 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN
,
1031 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN
,
1032 CPU_SSE2_FLAGS
, 0 },
1033 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN
,
1034 CPU_SSE3_FLAGS
, 0 },
1035 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN
,
1036 CPU_SSE4A_FLAGS
, 0 },
1037 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN
,
1038 CPU_SSSE3_FLAGS
, 0 },
1039 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN
,
1040 CPU_SSE4_1_FLAGS
, 0 },
1041 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN
,
1042 CPU_SSE4_2_FLAGS
, 0 },
1043 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN
,
1044 CPU_SSE4_2_FLAGS
, 0 },
1045 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN
,
1047 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN
,
1048 CPU_AVX2_FLAGS
, 0 },
1049 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN
,
1050 CPU_AVX512F_FLAGS
, 0 },
1051 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN
,
1052 CPU_AVX512CD_FLAGS
, 0 },
1053 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN
,
1054 CPU_AVX512ER_FLAGS
, 0 },
1055 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN
,
1056 CPU_AVX512PF_FLAGS
, 0 },
1057 { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN
,
1058 CPU_AVX512DQ_FLAGS
, 0 },
1059 { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN
,
1060 CPU_AVX512BW_FLAGS
, 0 },
1061 { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN
,
1062 CPU_AVX512VL_FLAGS
, 0 },
1063 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN
,
1065 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN
,
1066 CPU_VMFUNC_FLAGS
, 0 },
1067 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN
,
1069 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN
,
1070 CPU_XSAVE_FLAGS
, 0 },
1071 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN
,
1072 CPU_XSAVEOPT_FLAGS
, 0 },
1073 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN
,
1074 CPU_XSAVEC_FLAGS
, 0 },
1075 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN
,
1076 CPU_XSAVES_FLAGS
, 0 },
1077 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN
,
1079 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN
,
1080 CPU_PCLMUL_FLAGS
, 0 },
1081 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN
,
1082 CPU_PCLMUL_FLAGS
, 1 },
1083 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN
,
1084 CPU_FSGSBASE_FLAGS
, 0 },
1085 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN
,
1086 CPU_RDRND_FLAGS
, 0 },
1087 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN
,
1088 CPU_F16C_FLAGS
, 0 },
1089 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN
,
1090 CPU_BMI2_FLAGS
, 0 },
1091 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN
,
1093 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN
,
1094 CPU_FMA4_FLAGS
, 0 },
1095 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN
,
1097 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN
,
1099 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN
,
1100 CPU_MOVBE_FLAGS
, 0 },
1101 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN
,
1102 CPU_CX16_FLAGS
, 0 },
1103 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN
,
1105 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN
,
1106 CPU_LZCNT_FLAGS
, 0 },
1107 { STRING_COMMA_LEN (".popcnt"), PROCESSOR_UNKNOWN
,
1108 CPU_POPCNT_FLAGS
, 0 },
1109 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN
,
1111 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN
,
1113 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN
,
1114 CPU_INVPCID_FLAGS
, 0 },
1115 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN
,
1116 CPU_CLFLUSH_FLAGS
, 0 },
1117 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN
,
1119 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN
,
1120 CPU_SYSCALL_FLAGS
, 0 },
1121 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN
,
1122 CPU_RDTSCP_FLAGS
, 0 },
1123 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN
,
1124 CPU_3DNOW_FLAGS
, 0 },
1125 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN
,
1126 CPU_3DNOWA_FLAGS
, 0 },
1127 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN
,
1128 CPU_PADLOCK_FLAGS
, 0 },
1129 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN
,
1130 CPU_SVME_FLAGS
, 1 },
1131 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN
,
1132 CPU_SVME_FLAGS
, 0 },
1133 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN
,
1134 CPU_SSE4A_FLAGS
, 0 },
1135 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN
,
1137 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN
,
1139 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN
,
1141 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN
,
1143 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN
,
1144 CPU_RDSEED_FLAGS
, 0 },
1145 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN
,
1146 CPU_PRFCHW_FLAGS
, 0 },
1147 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN
,
1148 CPU_SMAP_FLAGS
, 0 },
1149 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN
,
1151 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN
,
1153 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN
,
1154 CPU_CLFLUSHOPT_FLAGS
, 0 },
1155 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN
,
1156 CPU_PREFETCHWT1_FLAGS
, 0 },
1157 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN
,
1159 { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN
,
1160 CPU_CLWB_FLAGS
, 0 },
1161 { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN
,
1162 CPU_AVX512IFMA_FLAGS
, 0 },
1163 { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN
,
1164 CPU_AVX512VBMI_FLAGS
, 0 },
1165 { STRING_COMMA_LEN (".avx512_4fmaps"), PROCESSOR_UNKNOWN
,
1166 CPU_AVX512_4FMAPS_FLAGS
, 0 },
1167 { STRING_COMMA_LEN (".avx512_4vnniw"), PROCESSOR_UNKNOWN
,
1168 CPU_AVX512_4VNNIW_FLAGS
, 0 },
1169 { STRING_COMMA_LEN (".avx512_vpopcntdq"), PROCESSOR_UNKNOWN
,
1170 CPU_AVX512_VPOPCNTDQ_FLAGS
, 0 },
1171 { STRING_COMMA_LEN (".avx512_vbmi2"), PROCESSOR_UNKNOWN
,
1172 CPU_AVX512_VBMI2_FLAGS
, 0 },
1173 { STRING_COMMA_LEN (".avx512_vnni"), PROCESSOR_UNKNOWN
,
1174 CPU_AVX512_VNNI_FLAGS
, 0 },
1175 { STRING_COMMA_LEN (".avx512_bitalg"), PROCESSOR_UNKNOWN
,
1176 CPU_AVX512_BITALG_FLAGS
, 0 },
1177 { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN
,
1178 CPU_CLZERO_FLAGS
, 0 },
1179 { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN
,
1180 CPU_MWAITX_FLAGS
, 0 },
1181 { STRING_COMMA_LEN (".ospke"), PROCESSOR_UNKNOWN
,
1182 CPU_OSPKE_FLAGS
, 0 },
1183 { STRING_COMMA_LEN (".rdpid"), PROCESSOR_UNKNOWN
,
1184 CPU_RDPID_FLAGS
, 0 },
1185 { STRING_COMMA_LEN (".ptwrite"), PROCESSOR_UNKNOWN
,
1186 CPU_PTWRITE_FLAGS
, 0 },
1187 { STRING_COMMA_LEN (".ibt"), PROCESSOR_UNKNOWN
,
1189 { STRING_COMMA_LEN (".shstk"), PROCESSOR_UNKNOWN
,
1190 CPU_SHSTK_FLAGS
, 0 },
1191 { STRING_COMMA_LEN (".gfni"), PROCESSOR_UNKNOWN
,
1192 CPU_GFNI_FLAGS
, 0 },
1193 { STRING_COMMA_LEN (".vaes"), PROCESSOR_UNKNOWN
,
1194 CPU_VAES_FLAGS
, 0 },
1195 { STRING_COMMA_LEN (".vpclmulqdq"), PROCESSOR_UNKNOWN
,
1196 CPU_VPCLMULQDQ_FLAGS
, 0 },
1197 { STRING_COMMA_LEN (".wbnoinvd"), PROCESSOR_UNKNOWN
,
1198 CPU_WBNOINVD_FLAGS
, 0 },
1199 { STRING_COMMA_LEN (".pconfig"), PROCESSOR_UNKNOWN
,
1200 CPU_PCONFIG_FLAGS
, 0 },
1201 { STRING_COMMA_LEN (".waitpkg"), PROCESSOR_UNKNOWN
,
1202 CPU_WAITPKG_FLAGS
, 0 },
1203 { STRING_COMMA_LEN (".cldemote"), PROCESSOR_UNKNOWN
,
1204 CPU_CLDEMOTE_FLAGS
, 0 },
1205 { STRING_COMMA_LEN (".movdiri"), PROCESSOR_UNKNOWN
,
1206 CPU_MOVDIRI_FLAGS
, 0 },
1207 { STRING_COMMA_LEN (".movdir64b"), PROCESSOR_UNKNOWN
,
1208 CPU_MOVDIR64B_FLAGS
, 0 },
1209 { STRING_COMMA_LEN (".avx512_bf16"), PROCESSOR_UNKNOWN
,
1210 CPU_AVX512_BF16_FLAGS
, 0 },
1211 { STRING_COMMA_LEN (".avx512_vp2intersect"), PROCESSOR_UNKNOWN
,
1212 CPU_AVX512_VP2INTERSECT_FLAGS
, 0 },
1213 { STRING_COMMA_LEN (".enqcmd"), PROCESSOR_UNKNOWN
,
1214 CPU_ENQCMD_FLAGS
, 0 },
1215 { STRING_COMMA_LEN (".serialize"), PROCESSOR_UNKNOWN
,
1216 CPU_SERIALIZE_FLAGS
, 0 },
1217 { STRING_COMMA_LEN (".rdpru"), PROCESSOR_UNKNOWN
,
1218 CPU_RDPRU_FLAGS
, 0 },
1219 { STRING_COMMA_LEN (".mcommit"), PROCESSOR_UNKNOWN
,
1220 CPU_MCOMMIT_FLAGS
, 0 },
1221 { STRING_COMMA_LEN (".sev_es"), PROCESSOR_UNKNOWN
,
1222 CPU_SEV_ES_FLAGS
, 0 },
1223 { STRING_COMMA_LEN (".tsxldtrk"), PROCESSOR_UNKNOWN
,
1224 CPU_TSXLDTRK_FLAGS
, 0 },
1227 static const noarch_entry cpu_noarch
[] =
1229 { STRING_COMMA_LEN ("no87"), CPU_ANY_X87_FLAGS
},
1230 { STRING_COMMA_LEN ("no287"), CPU_ANY_287_FLAGS
},
1231 { STRING_COMMA_LEN ("no387"), CPU_ANY_387_FLAGS
},
1232 { STRING_COMMA_LEN ("no687"), CPU_ANY_687_FLAGS
},
1233 { STRING_COMMA_LEN ("nocmov"), CPU_ANY_CMOV_FLAGS
},
1234 { STRING_COMMA_LEN ("nofxsr"), CPU_ANY_FXSR_FLAGS
},
1235 { STRING_COMMA_LEN ("nommx"), CPU_ANY_MMX_FLAGS
},
1236 { STRING_COMMA_LEN ("nosse"), CPU_ANY_SSE_FLAGS
},
1237 { STRING_COMMA_LEN ("nosse2"), CPU_ANY_SSE2_FLAGS
},
1238 { STRING_COMMA_LEN ("nosse3"), CPU_ANY_SSE3_FLAGS
},
1239 { STRING_COMMA_LEN ("nosse4a"), CPU_ANY_SSE4A_FLAGS
},
1240 { STRING_COMMA_LEN ("nossse3"), CPU_ANY_SSSE3_FLAGS
},
1241 { STRING_COMMA_LEN ("nosse4.1"), CPU_ANY_SSE4_1_FLAGS
},
1242 { STRING_COMMA_LEN ("nosse4.2"), CPU_ANY_SSE4_2_FLAGS
},
1243 { STRING_COMMA_LEN ("nosse4"), CPU_ANY_SSE4_1_FLAGS
},
1244 { STRING_COMMA_LEN ("noavx"), CPU_ANY_AVX_FLAGS
},
1245 { STRING_COMMA_LEN ("noavx2"), CPU_ANY_AVX2_FLAGS
},
1246 { STRING_COMMA_LEN ("noavx512f"), CPU_ANY_AVX512F_FLAGS
},
1247 { STRING_COMMA_LEN ("noavx512cd"), CPU_ANY_AVX512CD_FLAGS
},
1248 { STRING_COMMA_LEN ("noavx512er"), CPU_ANY_AVX512ER_FLAGS
},
1249 { STRING_COMMA_LEN ("noavx512pf"), CPU_ANY_AVX512PF_FLAGS
},
1250 { STRING_COMMA_LEN ("noavx512dq"), CPU_ANY_AVX512DQ_FLAGS
},
1251 { STRING_COMMA_LEN ("noavx512bw"), CPU_ANY_AVX512BW_FLAGS
},
1252 { STRING_COMMA_LEN ("noavx512vl"), CPU_ANY_AVX512VL_FLAGS
},
1253 { STRING_COMMA_LEN ("noavx512ifma"), CPU_ANY_AVX512IFMA_FLAGS
},
1254 { STRING_COMMA_LEN ("noavx512vbmi"), CPU_ANY_AVX512VBMI_FLAGS
},
1255 { STRING_COMMA_LEN ("noavx512_4fmaps"), CPU_ANY_AVX512_4FMAPS_FLAGS
},
1256 { STRING_COMMA_LEN ("noavx512_4vnniw"), CPU_ANY_AVX512_4VNNIW_FLAGS
},
1257 { STRING_COMMA_LEN ("noavx512_vpopcntdq"), CPU_ANY_AVX512_VPOPCNTDQ_FLAGS
},
1258 { STRING_COMMA_LEN ("noavx512_vbmi2"), CPU_ANY_AVX512_VBMI2_FLAGS
},
1259 { STRING_COMMA_LEN ("noavx512_vnni"), CPU_ANY_AVX512_VNNI_FLAGS
},
1260 { STRING_COMMA_LEN ("noavx512_bitalg"), CPU_ANY_AVX512_BITALG_FLAGS
},
1261 { STRING_COMMA_LEN ("noibt"), CPU_ANY_IBT_FLAGS
},
1262 { STRING_COMMA_LEN ("noshstk"), CPU_ANY_SHSTK_FLAGS
},
1263 { STRING_COMMA_LEN ("nomovdiri"), CPU_ANY_MOVDIRI_FLAGS
},
1264 { STRING_COMMA_LEN ("nomovdir64b"), CPU_ANY_MOVDIR64B_FLAGS
},
1265 { STRING_COMMA_LEN ("noavx512_bf16"), CPU_ANY_AVX512_BF16_FLAGS
},
1266 { STRING_COMMA_LEN ("noavx512_vp2intersect"),
1267 CPU_ANY_AVX512_VP2INTERSECT_FLAGS
},
1268 { STRING_COMMA_LEN ("noenqcmd"), CPU_ANY_ENQCMD_FLAGS
},
1269 { STRING_COMMA_LEN ("noserialize"), CPU_ANY_SERIALIZE_FLAGS
},
1270 { STRING_COMMA_LEN ("notsxldtrk"), CPU_ANY_TSXLDTRK_FLAGS
},
1274 /* Like s_lcomm_internal in gas/read.c but the alignment string
1275 is allowed to be optional. */
1278 pe_lcomm_internal (int needs_align
, symbolS
*symbolP
, addressT size
)
1285 && *input_line_pointer
== ',')
1287 align
= parse_align (needs_align
- 1);
1289 if (align
== (addressT
) -1)
1304 bss_alloc (symbolP
, size
, align
);
1309 pe_lcomm (int needs_align
)
1311 s_comm_internal (needs_align
* 2, pe_lcomm_internal
);
1315 const pseudo_typeS md_pseudo_table
[] =
1317 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
1318 {"align", s_align_bytes
, 0},
1320 {"align", s_align_ptwo
, 0},
1322 {"arch", set_cpu_arch
, 0},
1326 {"lcomm", pe_lcomm
, 1},
1328 {"ffloat", float_cons
, 'f'},
1329 {"dfloat", float_cons
, 'd'},
1330 {"tfloat", float_cons
, 'x'},
1332 {"slong", signed_cons
, 4},
1333 {"noopt", s_ignore
, 0},
1334 {"optim", s_ignore
, 0},
1335 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
1336 {"code16", set_code_flag
, CODE_16BIT
},
1337 {"code32", set_code_flag
, CODE_32BIT
},
1339 {"code64", set_code_flag
, CODE_64BIT
},
1341 {"intel_syntax", set_intel_syntax
, 1},
1342 {"att_syntax", set_intel_syntax
, 0},
1343 {"intel_mnemonic", set_intel_mnemonic
, 1},
1344 {"att_mnemonic", set_intel_mnemonic
, 0},
1345 {"allow_index_reg", set_allow_index_reg
, 1},
1346 {"disallow_index_reg", set_allow_index_reg
, 0},
1347 {"sse_check", set_check
, 0},
1348 {"operand_check", set_check
, 1},
1349 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1350 {"largecomm", handle_large_common
, 0},
1352 {"file", dwarf2_directive_file
, 0},
1353 {"loc", dwarf2_directive_loc
, 0},
1354 {"loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0},
1357 {"secrel32", pe_directive_secrel
, 0},
1362 /* For interface with expression (). */
1363 extern char *input_line_pointer
;
1365 /* Hash table for instruction mnemonic lookup. */
1366 static struct hash_control
*op_hash
;
1368 /* Hash table for register lookup. */
1369 static struct hash_control
*reg_hash
;
1371 /* Various efficient no-op patterns for aligning code labels.
1372 Note: Don't try to assemble the instructions in the comments.
1373 0L and 0w are not legal. */
1374 static const unsigned char f32_1
[] =
1376 static const unsigned char f32_2
[] =
1377 {0x66,0x90}; /* xchg %ax,%ax */
1378 static const unsigned char f32_3
[] =
1379 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1380 static const unsigned char f32_4
[] =
1381 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1382 static const unsigned char f32_6
[] =
1383 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1384 static const unsigned char f32_7
[] =
1385 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1386 static const unsigned char f16_3
[] =
1387 {0x8d,0x74,0x00}; /* lea 0(%si),%si */
1388 static const unsigned char f16_4
[] =
1389 {0x8d,0xb4,0x00,0x00}; /* lea 0W(%si),%si */
1390 static const unsigned char jump_disp8
[] =
1391 {0xeb}; /* jmp disp8 */
1392 static const unsigned char jump32_disp32
[] =
1393 {0xe9}; /* jmp disp32 */
1394 static const unsigned char jump16_disp32
[] =
1395 {0x66,0xe9}; /* jmp disp32 */
1396 /* 32-bit NOPs patterns. */
1397 static const unsigned char *const f32_patt
[] = {
1398 f32_1
, f32_2
, f32_3
, f32_4
, NULL
, f32_6
, f32_7
1400 /* 16-bit NOPs patterns. */
1401 static const unsigned char *const f16_patt
[] = {
1402 f32_1
, f32_2
, f16_3
, f16_4
1404 /* nopl (%[re]ax) */
1405 static const unsigned char alt_3
[] =
1407 /* nopl 0(%[re]ax) */
1408 static const unsigned char alt_4
[] =
1409 {0x0f,0x1f,0x40,0x00};
1410 /* nopl 0(%[re]ax,%[re]ax,1) */
1411 static const unsigned char alt_5
[] =
1412 {0x0f,0x1f,0x44,0x00,0x00};
1413 /* nopw 0(%[re]ax,%[re]ax,1) */
1414 static const unsigned char alt_6
[] =
1415 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1416 /* nopl 0L(%[re]ax) */
1417 static const unsigned char alt_7
[] =
1418 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1419 /* nopl 0L(%[re]ax,%[re]ax,1) */
1420 static const unsigned char alt_8
[] =
1421 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1422 /* nopw 0L(%[re]ax,%[re]ax,1) */
1423 static const unsigned char alt_9
[] =
1424 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1425 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1426 static const unsigned char alt_10
[] =
1427 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1428 /* data16 nopw %cs:0L(%eax,%eax,1) */
1429 static const unsigned char alt_11
[] =
1430 {0x66,0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1431 /* 32-bit and 64-bit NOPs patterns. */
1432 static const unsigned char *const alt_patt
[] = {
1433 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
1434 alt_9
, alt_10
, alt_11
1437 /* Genenerate COUNT bytes of NOPs to WHERE from PATT with the maximum
1438 size of a single NOP instruction MAX_SINGLE_NOP_SIZE. */
1441 i386_output_nops (char *where
, const unsigned char *const *patt
,
1442 int count
, int max_single_nop_size
)
1445 /* Place the longer NOP first. */
1448 const unsigned char *nops
;
1450 if (max_single_nop_size
< 1)
1452 as_fatal (_("i386_output_nops called to generate nops of at most %d bytes!"),
1453 max_single_nop_size
);
1457 nops
= patt
[max_single_nop_size
- 1];
1459 /* Use the smaller one if the requsted one isn't available. */
1462 max_single_nop_size
--;
1463 nops
= patt
[max_single_nop_size
- 1];
1466 last
= count
% max_single_nop_size
;
1469 for (offset
= 0; offset
< count
; offset
+= max_single_nop_size
)
1470 memcpy (where
+ offset
, nops
, max_single_nop_size
);
1474 nops
= patt
[last
- 1];
1477 /* Use the smaller one plus one-byte NOP if the needed one
1480 nops
= patt
[last
- 1];
1481 memcpy (where
+ offset
, nops
, last
);
1482 where
[offset
+ last
] = *patt
[0];
1485 memcpy (where
+ offset
, nops
, last
);
1490 fits_in_imm7 (offsetT num
)
1492 return (num
& 0x7f) == num
;
1496 fits_in_imm31 (offsetT num
)
1498 return (num
& 0x7fffffff) == num
;
1501 /* Genenerate COUNT bytes of NOPs to WHERE with the maximum size of a
1502 single NOP instruction LIMIT. */
1505 i386_generate_nops (fragS
*fragP
, char *where
, offsetT count
, int limit
)
1507 const unsigned char *const *patt
= NULL
;
1508 int max_single_nop_size
;
1509 /* Maximum number of NOPs before switching to jump over NOPs. */
1510 int max_number_of_nops
;
1512 switch (fragP
->fr_type
)
1517 case rs_machine_dependent
:
1518 /* Allow NOP padding for jumps and calls. */
1519 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
1520 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
)
1527 /* We need to decide which NOP sequence to use for 32bit and
1528 64bit. When -mtune= is used:
1530 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1531 PROCESSOR_GENERIC32, f32_patt will be used.
1532 2. For the rest, alt_patt will be used.
1534 When -mtune= isn't used, alt_patt will be used if
1535 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
1538 When -march= or .arch is used, we can't use anything beyond
1539 cpu_arch_isa_flags. */
1541 if (flag_code
== CODE_16BIT
)
1544 max_single_nop_size
= sizeof (f16_patt
) / sizeof (f16_patt
[0]);
1545 /* Limit number of NOPs to 2 in 16-bit mode. */
1546 max_number_of_nops
= 2;
1550 if (fragP
->tc_frag_data
.isa
== PROCESSOR_UNKNOWN
)
1552 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1553 switch (cpu_arch_tune
)
1555 case PROCESSOR_UNKNOWN
:
1556 /* We use cpu_arch_isa_flags to check if we SHOULD
1557 optimize with nops. */
1558 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1563 case PROCESSOR_PENTIUM4
:
1564 case PROCESSOR_NOCONA
:
1565 case PROCESSOR_CORE
:
1566 case PROCESSOR_CORE2
:
1567 case PROCESSOR_COREI7
:
1568 case PROCESSOR_L1OM
:
1569 case PROCESSOR_K1OM
:
1570 case PROCESSOR_GENERIC64
:
1572 case PROCESSOR_ATHLON
:
1574 case PROCESSOR_AMDFAM10
:
1576 case PROCESSOR_ZNVER
:
1580 case PROCESSOR_I386
:
1581 case PROCESSOR_I486
:
1582 case PROCESSOR_PENTIUM
:
1583 case PROCESSOR_PENTIUMPRO
:
1584 case PROCESSOR_IAMCU
:
1585 case PROCESSOR_GENERIC32
:
1592 switch (fragP
->tc_frag_data
.tune
)
1594 case PROCESSOR_UNKNOWN
:
1595 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1596 PROCESSOR_UNKNOWN. */
1600 case PROCESSOR_I386
:
1601 case PROCESSOR_I486
:
1602 case PROCESSOR_PENTIUM
:
1603 case PROCESSOR_IAMCU
:
1605 case PROCESSOR_ATHLON
:
1607 case PROCESSOR_AMDFAM10
:
1609 case PROCESSOR_ZNVER
:
1611 case PROCESSOR_GENERIC32
:
1612 /* We use cpu_arch_isa_flags to check if we CAN optimize
1614 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1619 case PROCESSOR_PENTIUMPRO
:
1620 case PROCESSOR_PENTIUM4
:
1621 case PROCESSOR_NOCONA
:
1622 case PROCESSOR_CORE
:
1623 case PROCESSOR_CORE2
:
1624 case PROCESSOR_COREI7
:
1625 case PROCESSOR_L1OM
:
1626 case PROCESSOR_K1OM
:
1627 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1632 case PROCESSOR_GENERIC64
:
1638 if (patt
== f32_patt
)
1640 max_single_nop_size
= sizeof (f32_patt
) / sizeof (f32_patt
[0]);
1641 /* Limit number of NOPs to 2 for older processors. */
1642 max_number_of_nops
= 2;
1646 max_single_nop_size
= sizeof (alt_patt
) / sizeof (alt_patt
[0]);
1647 /* Limit number of NOPs to 7 for newer processors. */
1648 max_number_of_nops
= 7;
1653 limit
= max_single_nop_size
;
1655 if (fragP
->fr_type
== rs_fill_nop
)
1657 /* Output NOPs for .nop directive. */
1658 if (limit
> max_single_nop_size
)
1660 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
1661 _("invalid single nop size: %d "
1662 "(expect within [0, %d])"),
1663 limit
, max_single_nop_size
);
1667 else if (fragP
->fr_type
!= rs_machine_dependent
)
1668 fragP
->fr_var
= count
;
1670 if ((count
/ max_single_nop_size
) > max_number_of_nops
)
1672 /* Generate jump over NOPs. */
1673 offsetT disp
= count
- 2;
1674 if (fits_in_imm7 (disp
))
1676 /* Use "jmp disp8" if possible. */
1678 where
[0] = jump_disp8
[0];
1684 unsigned int size_of_jump
;
1686 if (flag_code
== CODE_16BIT
)
1688 where
[0] = jump16_disp32
[0];
1689 where
[1] = jump16_disp32
[1];
1694 where
[0] = jump32_disp32
[0];
1698 count
-= size_of_jump
+ 4;
1699 if (!fits_in_imm31 (count
))
1701 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
1702 _("jump over nop padding out of range"));
1706 md_number_to_chars (where
+ size_of_jump
, count
, 4);
1707 where
+= size_of_jump
+ 4;
1711 /* Generate multiple NOPs. */
1712 i386_output_nops (where
, patt
, count
, limit
);
1716 operand_type_all_zero (const union i386_operand_type
*x
)
1718 switch (ARRAY_SIZE(x
->array
))
1729 return !x
->array
[0];
1736 operand_type_set (union i386_operand_type
*x
, unsigned int v
)
1738 switch (ARRAY_SIZE(x
->array
))
1754 x
->bitfield
.class = ClassNone
;
1755 x
->bitfield
.instance
= InstanceNone
;
1759 operand_type_equal (const union i386_operand_type
*x
,
1760 const union i386_operand_type
*y
)
1762 switch (ARRAY_SIZE(x
->array
))
1765 if (x
->array
[2] != y
->array
[2])
1769 if (x
->array
[1] != y
->array
[1])
1773 return x
->array
[0] == y
->array
[0];
1781 cpu_flags_all_zero (const union i386_cpu_flags
*x
)
1783 switch (ARRAY_SIZE(x
->array
))
1798 return !x
->array
[0];
1805 cpu_flags_equal (const union i386_cpu_flags
*x
,
1806 const union i386_cpu_flags
*y
)
1808 switch (ARRAY_SIZE(x
->array
))
1811 if (x
->array
[3] != y
->array
[3])
1815 if (x
->array
[2] != y
->array
[2])
1819 if (x
->array
[1] != y
->array
[1])
1823 return x
->array
[0] == y
->array
[0];
1831 cpu_flags_check_cpu64 (i386_cpu_flags f
)
1833 return !((flag_code
== CODE_64BIT
&& f
.bitfield
.cpuno64
)
1834 || (flag_code
!= CODE_64BIT
&& f
.bitfield
.cpu64
));
1837 static INLINE i386_cpu_flags
1838 cpu_flags_and (i386_cpu_flags x
, i386_cpu_flags y
)
1840 switch (ARRAY_SIZE (x
.array
))
1843 x
.array
[3] &= y
.array
[3];
1846 x
.array
[2] &= y
.array
[2];
1849 x
.array
[1] &= y
.array
[1];
1852 x
.array
[0] &= y
.array
[0];
1860 static INLINE i386_cpu_flags
1861 cpu_flags_or (i386_cpu_flags x
, i386_cpu_flags y
)
1863 switch (ARRAY_SIZE (x
.array
))
1866 x
.array
[3] |= y
.array
[3];
1869 x
.array
[2] |= y
.array
[2];
1872 x
.array
[1] |= y
.array
[1];
1875 x
.array
[0] |= y
.array
[0];
1883 static INLINE i386_cpu_flags
1884 cpu_flags_and_not (i386_cpu_flags x
, i386_cpu_flags y
)
1886 switch (ARRAY_SIZE (x
.array
))
1889 x
.array
[3] &= ~y
.array
[3];
1892 x
.array
[2] &= ~y
.array
[2];
1895 x
.array
[1] &= ~y
.array
[1];
1898 x
.array
[0] &= ~y
.array
[0];
1906 static const i386_cpu_flags avx512
= CPU_ANY_AVX512F_FLAGS
;
1908 #define CPU_FLAGS_ARCH_MATCH 0x1
1909 #define CPU_FLAGS_64BIT_MATCH 0x2
1911 #define CPU_FLAGS_PERFECT_MATCH \
1912 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_64BIT_MATCH)
1914 /* Return CPU flags match bits. */
1917 cpu_flags_match (const insn_template
*t
)
1919 i386_cpu_flags x
= t
->cpu_flags
;
1920 int match
= cpu_flags_check_cpu64 (x
) ? CPU_FLAGS_64BIT_MATCH
: 0;
1922 x
.bitfield
.cpu64
= 0;
1923 x
.bitfield
.cpuno64
= 0;
1925 if (cpu_flags_all_zero (&x
))
1927 /* This instruction is available on all archs. */
1928 match
|= CPU_FLAGS_ARCH_MATCH
;
1932 /* This instruction is available only on some archs. */
1933 i386_cpu_flags cpu
= cpu_arch_flags
;
1935 /* AVX512VL is no standalone feature - match it and then strip it. */
1936 if (x
.bitfield
.cpuavx512vl
&& !cpu
.bitfield
.cpuavx512vl
)
1938 x
.bitfield
.cpuavx512vl
= 0;
1940 cpu
= cpu_flags_and (x
, cpu
);
1941 if (!cpu_flags_all_zero (&cpu
))
1943 if (x
.bitfield
.cpuavx
)
1945 /* We need to check a few extra flags with AVX. */
1946 if (cpu
.bitfield
.cpuavx
1947 && (!t
->opcode_modifier
.sse2avx
|| sse2avx
)
1948 && (!x
.bitfield
.cpuaes
|| cpu
.bitfield
.cpuaes
)
1949 && (!x
.bitfield
.cpugfni
|| cpu
.bitfield
.cpugfni
)
1950 && (!x
.bitfield
.cpupclmul
|| cpu
.bitfield
.cpupclmul
))
1951 match
|= CPU_FLAGS_ARCH_MATCH
;
1953 else if (x
.bitfield
.cpuavx512f
)
1955 /* We need to check a few extra flags with AVX512F. */
1956 if (cpu
.bitfield
.cpuavx512f
1957 && (!x
.bitfield
.cpugfni
|| cpu
.bitfield
.cpugfni
)
1958 && (!x
.bitfield
.cpuvaes
|| cpu
.bitfield
.cpuvaes
)
1959 && (!x
.bitfield
.cpuvpclmulqdq
|| cpu
.bitfield
.cpuvpclmulqdq
))
1960 match
|= CPU_FLAGS_ARCH_MATCH
;
1963 match
|= CPU_FLAGS_ARCH_MATCH
;
1969 static INLINE i386_operand_type
1970 operand_type_and (i386_operand_type x
, i386_operand_type y
)
1972 if (x
.bitfield
.class != y
.bitfield
.class)
1973 x
.bitfield
.class = ClassNone
;
1974 if (x
.bitfield
.instance
!= y
.bitfield
.instance
)
1975 x
.bitfield
.instance
= InstanceNone
;
1977 switch (ARRAY_SIZE (x
.array
))
1980 x
.array
[2] &= y
.array
[2];
1983 x
.array
[1] &= y
.array
[1];
1986 x
.array
[0] &= y
.array
[0];
1994 static INLINE i386_operand_type
1995 operand_type_and_not (i386_operand_type x
, i386_operand_type y
)
1997 gas_assert (y
.bitfield
.class == ClassNone
);
1998 gas_assert (y
.bitfield
.instance
== InstanceNone
);
2000 switch (ARRAY_SIZE (x
.array
))
2003 x
.array
[2] &= ~y
.array
[2];
2006 x
.array
[1] &= ~y
.array
[1];
2009 x
.array
[0] &= ~y
.array
[0];
2017 static INLINE i386_operand_type
2018 operand_type_or (i386_operand_type x
, i386_operand_type y
)
2020 gas_assert (x
.bitfield
.class == ClassNone
||
2021 y
.bitfield
.class == ClassNone
||
2022 x
.bitfield
.class == y
.bitfield
.class);
2023 gas_assert (x
.bitfield
.instance
== InstanceNone
||
2024 y
.bitfield
.instance
== InstanceNone
||
2025 x
.bitfield
.instance
== y
.bitfield
.instance
);
2027 switch (ARRAY_SIZE (x
.array
))
2030 x
.array
[2] |= y
.array
[2];
2033 x
.array
[1] |= y
.array
[1];
2036 x
.array
[0] |= y
.array
[0];
2044 static INLINE i386_operand_type
2045 operand_type_xor (i386_operand_type x
, i386_operand_type y
)
2047 gas_assert (y
.bitfield
.class == ClassNone
);
2048 gas_assert (y
.bitfield
.instance
== InstanceNone
);
2050 switch (ARRAY_SIZE (x
.array
))
2053 x
.array
[2] ^= y
.array
[2];
2056 x
.array
[1] ^= y
.array
[1];
2059 x
.array
[0] ^= y
.array
[0];
2067 static const i386_operand_type disp16
= OPERAND_TYPE_DISP16
;
2068 static const i386_operand_type disp32
= OPERAND_TYPE_DISP32
;
2069 static const i386_operand_type disp32s
= OPERAND_TYPE_DISP32S
;
2070 static const i386_operand_type disp16_32
= OPERAND_TYPE_DISP16_32
;
2071 static const i386_operand_type anydisp
= OPERAND_TYPE_ANYDISP
;
2072 static const i386_operand_type anyimm
= OPERAND_TYPE_ANYIMM
;
2073 static const i386_operand_type regxmm
= OPERAND_TYPE_REGXMM
;
2074 static const i386_operand_type regmask
= OPERAND_TYPE_REGMASK
;
2075 static const i386_operand_type imm8
= OPERAND_TYPE_IMM8
;
2076 static const i386_operand_type imm8s
= OPERAND_TYPE_IMM8S
;
2077 static const i386_operand_type imm16
= OPERAND_TYPE_IMM16
;
2078 static const i386_operand_type imm32
= OPERAND_TYPE_IMM32
;
2079 static const i386_operand_type imm32s
= OPERAND_TYPE_IMM32S
;
2080 static const i386_operand_type imm64
= OPERAND_TYPE_IMM64
;
2081 static const i386_operand_type imm16_32
= OPERAND_TYPE_IMM16_32
;
2082 static const i386_operand_type imm16_32s
= OPERAND_TYPE_IMM16_32S
;
2083 static const i386_operand_type imm16_32_32s
= OPERAND_TYPE_IMM16_32_32S
;
2094 operand_type_check (i386_operand_type t
, enum operand_type c
)
2099 return t
.bitfield
.class == Reg
;
2102 return (t
.bitfield
.imm8
2106 || t
.bitfield
.imm32s
2107 || t
.bitfield
.imm64
);
2110 return (t
.bitfield
.disp8
2111 || t
.bitfield
.disp16
2112 || t
.bitfield
.disp32
2113 || t
.bitfield
.disp32s
2114 || t
.bitfield
.disp64
);
2117 return (t
.bitfield
.disp8
2118 || t
.bitfield
.disp16
2119 || t
.bitfield
.disp32
2120 || t
.bitfield
.disp32s
2121 || t
.bitfield
.disp64
2122 || t
.bitfield
.baseindex
);
2131 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit/80bit size
2132 between operand GIVEN and opeand WANTED for instruction template T. */
2135 match_operand_size (const insn_template
*t
, unsigned int wanted
,
2138 return !((i
.types
[given
].bitfield
.byte
2139 && !t
->operand_types
[wanted
].bitfield
.byte
)
2140 || (i
.types
[given
].bitfield
.word
2141 && !t
->operand_types
[wanted
].bitfield
.word
)
2142 || (i
.types
[given
].bitfield
.dword
2143 && !t
->operand_types
[wanted
].bitfield
.dword
)
2144 || (i
.types
[given
].bitfield
.qword
2145 && !t
->operand_types
[wanted
].bitfield
.qword
)
2146 || (i
.types
[given
].bitfield
.tbyte
2147 && !t
->operand_types
[wanted
].bitfield
.tbyte
));
2150 /* Return 1 if there is no conflict in SIMD register between operand
2151 GIVEN and opeand WANTED for instruction template T. */
2154 match_simd_size (const insn_template
*t
, unsigned int wanted
,
2157 return !((i
.types
[given
].bitfield
.xmmword
2158 && !t
->operand_types
[wanted
].bitfield
.xmmword
)
2159 || (i
.types
[given
].bitfield
.ymmword
2160 && !t
->operand_types
[wanted
].bitfield
.ymmword
)
2161 || (i
.types
[given
].bitfield
.zmmword
2162 && !t
->operand_types
[wanted
].bitfield
.zmmword
));
2165 /* Return 1 if there is no conflict in any size between operand GIVEN
2166 and opeand WANTED for instruction template T. */
2169 match_mem_size (const insn_template
*t
, unsigned int wanted
,
2172 return (match_operand_size (t
, wanted
, given
)
2173 && !((i
.types
[given
].bitfield
.unspecified
2175 && !t
->operand_types
[wanted
].bitfield
.unspecified
)
2176 || (i
.types
[given
].bitfield
.fword
2177 && !t
->operand_types
[wanted
].bitfield
.fword
)
2178 /* For scalar opcode templates to allow register and memory
2179 operands at the same time, some special casing is needed
2180 here. Also for v{,p}broadcast*, {,v}pmov{s,z}*, and
2181 down-conversion vpmov*. */
2182 || ((t
->operand_types
[wanted
].bitfield
.class == RegSIMD
2183 && t
->operand_types
[wanted
].bitfield
.byte
2184 + t
->operand_types
[wanted
].bitfield
.word
2185 + t
->operand_types
[wanted
].bitfield
.dword
2186 + t
->operand_types
[wanted
].bitfield
.qword
2187 > !!t
->opcode_modifier
.broadcast
)
2188 ? (i
.types
[given
].bitfield
.xmmword
2189 || i
.types
[given
].bitfield
.ymmword
2190 || i
.types
[given
].bitfield
.zmmword
)
2191 : !match_simd_size(t
, wanted
, given
))));
2194 /* Return value has MATCH_STRAIGHT set if there is no size conflict on any
2195 operands for instruction template T, and it has MATCH_REVERSE set if there
2196 is no size conflict on any operands for the template with operands reversed
2197 (and the template allows for reversing in the first place). */
2199 #define MATCH_STRAIGHT 1
2200 #define MATCH_REVERSE 2
2202 static INLINE
unsigned int
2203 operand_size_match (const insn_template
*t
)
2205 unsigned int j
, match
= MATCH_STRAIGHT
;
2207 /* Don't check non-absolute jump instructions. */
2208 if (t
->opcode_modifier
.jump
2209 && t
->opcode_modifier
.jump
!= JUMP_ABSOLUTE
)
2212 /* Check memory and accumulator operand size. */
2213 for (j
= 0; j
< i
.operands
; j
++)
2215 if (i
.types
[j
].bitfield
.class != Reg
2216 && i
.types
[j
].bitfield
.class != RegSIMD
2217 && t
->opcode_modifier
.anysize
)
2220 if (t
->operand_types
[j
].bitfield
.class == Reg
2221 && !match_operand_size (t
, j
, j
))
2227 if (t
->operand_types
[j
].bitfield
.class == RegSIMD
2228 && !match_simd_size (t
, j
, j
))
2234 if (t
->operand_types
[j
].bitfield
.instance
== Accum
2235 && (!match_operand_size (t
, j
, j
) || !match_simd_size (t
, j
, j
)))
2241 if ((i
.flags
[j
] & Operand_Mem
) && !match_mem_size (t
, j
, j
))
2248 if (!t
->opcode_modifier
.d
)
2252 i
.error
= operand_size_mismatch
;
2256 /* Check reverse. */
2257 gas_assert (i
.operands
>= 2 && i
.operands
<= 3);
2259 for (j
= 0; j
< i
.operands
; j
++)
2261 unsigned int given
= i
.operands
- j
- 1;
2263 if (t
->operand_types
[j
].bitfield
.class == Reg
2264 && !match_operand_size (t
, j
, given
))
2267 if (t
->operand_types
[j
].bitfield
.class == RegSIMD
2268 && !match_simd_size (t
, j
, given
))
2271 if (t
->operand_types
[j
].bitfield
.instance
== Accum
2272 && (!match_operand_size (t
, j
, given
)
2273 || !match_simd_size (t
, j
, given
)))
2276 if ((i
.flags
[given
] & Operand_Mem
) && !match_mem_size (t
, j
, given
))
2280 return match
| MATCH_REVERSE
;
2284 operand_type_match (i386_operand_type overlap
,
2285 i386_operand_type given
)
2287 i386_operand_type temp
= overlap
;
2289 temp
.bitfield
.unspecified
= 0;
2290 temp
.bitfield
.byte
= 0;
2291 temp
.bitfield
.word
= 0;
2292 temp
.bitfield
.dword
= 0;
2293 temp
.bitfield
.fword
= 0;
2294 temp
.bitfield
.qword
= 0;
2295 temp
.bitfield
.tbyte
= 0;
2296 temp
.bitfield
.xmmword
= 0;
2297 temp
.bitfield
.ymmword
= 0;
2298 temp
.bitfield
.zmmword
= 0;
2299 if (operand_type_all_zero (&temp
))
2302 if (given
.bitfield
.baseindex
== overlap
.bitfield
.baseindex
)
2306 i
.error
= operand_type_mismatch
;
2310 /* If given types g0 and g1 are registers they must be of the same type
2311 unless the expected operand type register overlap is null.
2312 Some Intel syntax memory operand size checking also happens here. */
2315 operand_type_register_match (i386_operand_type g0
,
2316 i386_operand_type t0
,
2317 i386_operand_type g1
,
2318 i386_operand_type t1
)
2320 if (g0
.bitfield
.class != Reg
2321 && g0
.bitfield
.class != RegSIMD
2322 && (!operand_type_check (g0
, anymem
)
2323 || g0
.bitfield
.unspecified
2324 || (t0
.bitfield
.class != Reg
2325 && t0
.bitfield
.class != RegSIMD
)))
2328 if (g1
.bitfield
.class != Reg
2329 && g1
.bitfield
.class != RegSIMD
2330 && (!operand_type_check (g1
, anymem
)
2331 || g1
.bitfield
.unspecified
2332 || (t1
.bitfield
.class != Reg
2333 && t1
.bitfield
.class != RegSIMD
)))
2336 if (g0
.bitfield
.byte
== g1
.bitfield
.byte
2337 && g0
.bitfield
.word
== g1
.bitfield
.word
2338 && g0
.bitfield
.dword
== g1
.bitfield
.dword
2339 && g0
.bitfield
.qword
== g1
.bitfield
.qword
2340 && g0
.bitfield
.xmmword
== g1
.bitfield
.xmmword
2341 && g0
.bitfield
.ymmword
== g1
.bitfield
.ymmword
2342 && g0
.bitfield
.zmmword
== g1
.bitfield
.zmmword
)
2345 if (!(t0
.bitfield
.byte
& t1
.bitfield
.byte
)
2346 && !(t0
.bitfield
.word
& t1
.bitfield
.word
)
2347 && !(t0
.bitfield
.dword
& t1
.bitfield
.dword
)
2348 && !(t0
.bitfield
.qword
& t1
.bitfield
.qword
)
2349 && !(t0
.bitfield
.xmmword
& t1
.bitfield
.xmmword
)
2350 && !(t0
.bitfield
.ymmword
& t1
.bitfield
.ymmword
)
2351 && !(t0
.bitfield
.zmmword
& t1
.bitfield
.zmmword
))
2354 i
.error
= register_type_mismatch
;
2359 static INLINE
unsigned int
2360 register_number (const reg_entry
*r
)
2362 unsigned int nr
= r
->reg_num
;
2364 if (r
->reg_flags
& RegRex
)
2367 if (r
->reg_flags
& RegVRex
)
2373 static INLINE
unsigned int
2374 mode_from_disp_size (i386_operand_type t
)
2376 if (t
.bitfield
.disp8
)
2378 else if (t
.bitfield
.disp16
2379 || t
.bitfield
.disp32
2380 || t
.bitfield
.disp32s
)
2387 fits_in_signed_byte (addressT num
)
2389 return num
+ 0x80 <= 0xff;
2393 fits_in_unsigned_byte (addressT num
)
2399 fits_in_unsigned_word (addressT num
)
2401 return num
<= 0xffff;
2405 fits_in_signed_word (addressT num
)
2407 return num
+ 0x8000 <= 0xffff;
2411 fits_in_signed_long (addressT num ATTRIBUTE_UNUSED
)
2416 return num
+ 0x80000000 <= 0xffffffff;
2418 } /* fits_in_signed_long() */
2421 fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED
)
2426 return num
<= 0xffffffff;
2428 } /* fits_in_unsigned_long() */
2431 fits_in_disp8 (offsetT num
)
2433 int shift
= i
.memshift
;
2439 mask
= (1 << shift
) - 1;
2441 /* Return 0 if NUM isn't properly aligned. */
2445 /* Check if NUM will fit in 8bit after shift. */
2446 return fits_in_signed_byte (num
>> shift
);
2450 fits_in_imm4 (offsetT num
)
2452 return (num
& 0xf) == num
;
2455 static i386_operand_type
2456 smallest_imm_type (offsetT num
)
2458 i386_operand_type t
;
2460 operand_type_set (&t
, 0);
2461 t
.bitfield
.imm64
= 1;
2463 if (cpu_arch_tune
!= PROCESSOR_I486
&& num
== 1)
2465 /* This code is disabled on the 486 because all the Imm1 forms
2466 in the opcode table are slower on the i486. They're the
2467 versions with the implicitly specified single-position
2468 displacement, which has another syntax if you really want to
2470 t
.bitfield
.imm1
= 1;
2471 t
.bitfield
.imm8
= 1;
2472 t
.bitfield
.imm8s
= 1;
2473 t
.bitfield
.imm16
= 1;
2474 t
.bitfield
.imm32
= 1;
2475 t
.bitfield
.imm32s
= 1;
2477 else if (fits_in_signed_byte (num
))
2479 t
.bitfield
.imm8
= 1;
2480 t
.bitfield
.imm8s
= 1;
2481 t
.bitfield
.imm16
= 1;
2482 t
.bitfield
.imm32
= 1;
2483 t
.bitfield
.imm32s
= 1;
2485 else if (fits_in_unsigned_byte (num
))
2487 t
.bitfield
.imm8
= 1;
2488 t
.bitfield
.imm16
= 1;
2489 t
.bitfield
.imm32
= 1;
2490 t
.bitfield
.imm32s
= 1;
2492 else if (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
2494 t
.bitfield
.imm16
= 1;
2495 t
.bitfield
.imm32
= 1;
2496 t
.bitfield
.imm32s
= 1;
2498 else if (fits_in_signed_long (num
))
2500 t
.bitfield
.imm32
= 1;
2501 t
.bitfield
.imm32s
= 1;
2503 else if (fits_in_unsigned_long (num
))
2504 t
.bitfield
.imm32
= 1;
2510 offset_in_range (offsetT val
, int size
)
2516 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
2517 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
2518 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
2520 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
2526 /* If BFD64, sign extend val for 32bit address mode. */
2527 if (flag_code
!= CODE_64BIT
2528 || i
.prefix
[ADDR_PREFIX
])
2529 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
2530 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
2533 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
2535 char buf1
[40], buf2
[40];
2537 sprint_value (buf1
, val
);
2538 sprint_value (buf2
, val
& mask
);
2539 as_warn (_("%s shortened to %s"), buf1
, buf2
);
2554 a. PREFIX_EXIST if attempting to add a prefix where one from the
2555 same class already exists.
2556 b. PREFIX_LOCK if lock prefix is added.
2557 c. PREFIX_REP if rep/repne prefix is added.
2558 d. PREFIX_DS if ds prefix is added.
2559 e. PREFIX_OTHER if other prefix is added.
2562 static enum PREFIX_GROUP
2563 add_prefix (unsigned int prefix
)
2565 enum PREFIX_GROUP ret
= PREFIX_OTHER
;
2568 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
2569 && flag_code
== CODE_64BIT
)
2571 if ((i
.prefix
[REX_PREFIX
] & prefix
& REX_W
)
2572 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_R
)
2573 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_X
)
2574 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_B
))
2585 case DS_PREFIX_OPCODE
:
2588 case CS_PREFIX_OPCODE
:
2589 case ES_PREFIX_OPCODE
:
2590 case FS_PREFIX_OPCODE
:
2591 case GS_PREFIX_OPCODE
:
2592 case SS_PREFIX_OPCODE
:
2596 case REPNE_PREFIX_OPCODE
:
2597 case REPE_PREFIX_OPCODE
:
2602 case LOCK_PREFIX_OPCODE
:
2611 case ADDR_PREFIX_OPCODE
:
2615 case DATA_PREFIX_OPCODE
:
2619 if (i
.prefix
[q
] != 0)
2627 i
.prefix
[q
] |= prefix
;
2630 as_bad (_("same type of prefix used twice"));
2636 update_code_flag (int value
, int check
)
2638 PRINTF_LIKE ((*as_error
));
2640 flag_code
= (enum flag_code
) value
;
2641 if (flag_code
== CODE_64BIT
)
2643 cpu_arch_flags
.bitfield
.cpu64
= 1;
2644 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2648 cpu_arch_flags
.bitfield
.cpu64
= 0;
2649 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2651 if (value
== CODE_64BIT
&& !cpu_arch_flags
.bitfield
.cpulm
)
2654 as_error
= as_fatal
;
2657 (*as_error
) (_("64bit mode not supported on `%s'."),
2658 cpu_arch_name
? cpu_arch_name
: default_arch
);
2660 if (value
== CODE_32BIT
&& !cpu_arch_flags
.bitfield
.cpui386
)
2663 as_error
= as_fatal
;
2666 (*as_error
) (_("32bit mode not supported on `%s'."),
2667 cpu_arch_name
? cpu_arch_name
: default_arch
);
2669 stackop_size
= '\0';
2673 set_code_flag (int value
)
2675 update_code_flag (value
, 0);
2679 set_16bit_gcc_code_flag (int new_code_flag
)
2681 flag_code
= (enum flag_code
) new_code_flag
;
2682 if (flag_code
!= CODE_16BIT
)
2684 cpu_arch_flags
.bitfield
.cpu64
= 0;
2685 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2686 stackop_size
= LONG_MNEM_SUFFIX
;
2690 set_intel_syntax (int syntax_flag
)
2692 /* Find out if register prefixing is specified. */
2693 int ask_naked_reg
= 0;
2696 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2699 int e
= get_symbol_name (&string
);
2701 if (strcmp (string
, "prefix") == 0)
2703 else if (strcmp (string
, "noprefix") == 0)
2706 as_bad (_("bad argument to syntax directive."));
2707 (void) restore_line_pointer (e
);
2709 demand_empty_rest_of_line ();
2711 intel_syntax
= syntax_flag
;
2713 if (ask_naked_reg
== 0)
2714 allow_naked_reg
= (intel_syntax
2715 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
2717 allow_naked_reg
= (ask_naked_reg
< 0);
2719 expr_set_rank (O_full_ptr
, syntax_flag
? 10 : 0);
2721 identifier_chars
['%'] = intel_syntax
&& allow_naked_reg
? '%' : 0;
2722 identifier_chars
['$'] = intel_syntax
? '$' : 0;
2723 register_prefix
= allow_naked_reg
? "" : "%";
2727 set_intel_mnemonic (int mnemonic_flag
)
2729 intel_mnemonic
= mnemonic_flag
;
2733 set_allow_index_reg (int flag
)
2735 allow_index_reg
= flag
;
2739 set_check (int what
)
2741 enum check_kind
*kind
;
2746 kind
= &operand_check
;
2757 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2760 int e
= get_symbol_name (&string
);
2762 if (strcmp (string
, "none") == 0)
2764 else if (strcmp (string
, "warning") == 0)
2765 *kind
= check_warning
;
2766 else if (strcmp (string
, "error") == 0)
2767 *kind
= check_error
;
2769 as_bad (_("bad argument to %s_check directive."), str
);
2770 (void) restore_line_pointer (e
);
2773 as_bad (_("missing argument for %s_check directive"), str
);
2775 demand_empty_rest_of_line ();
2779 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED
,
2780 i386_cpu_flags new_flag ATTRIBUTE_UNUSED
)
2782 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2783 static const char *arch
;
2785 /* Intel LIOM is only supported on ELF. */
2791 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2792 use default_arch. */
2793 arch
= cpu_arch_name
;
2795 arch
= default_arch
;
2798 /* If we are targeting Intel MCU, we must enable it. */
2799 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_IAMCU
2800 || new_flag
.bitfield
.cpuiamcu
)
2803 /* If we are targeting Intel L1OM, we must enable it. */
2804 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_L1OM
2805 || new_flag
.bitfield
.cpul1om
)
2808 /* If we are targeting Intel K1OM, we must enable it. */
2809 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_K1OM
2810 || new_flag
.bitfield
.cpuk1om
)
2813 as_bad (_("`%s' is not supported on `%s'"), name
, arch
);
2818 set_cpu_arch (int dummy ATTRIBUTE_UNUSED
)
2822 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2825 int e
= get_symbol_name (&string
);
2827 i386_cpu_flags flags
;
2829 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
2831 if (strcmp (string
, cpu_arch
[j
].name
) == 0)
2833 check_cpu_arch_compatible (string
, cpu_arch
[j
].flags
);
2837 cpu_arch_name
= cpu_arch
[j
].name
;
2838 cpu_sub_arch_name
= NULL
;
2839 cpu_arch_flags
= cpu_arch
[j
].flags
;
2840 if (flag_code
== CODE_64BIT
)
2842 cpu_arch_flags
.bitfield
.cpu64
= 1;
2843 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2847 cpu_arch_flags
.bitfield
.cpu64
= 0;
2848 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2850 cpu_arch_isa
= cpu_arch
[j
].type
;
2851 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
2852 if (!cpu_arch_tune_set
)
2854 cpu_arch_tune
= cpu_arch_isa
;
2855 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
2860 flags
= cpu_flags_or (cpu_arch_flags
,
2863 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2865 if (cpu_sub_arch_name
)
2867 char *name
= cpu_sub_arch_name
;
2868 cpu_sub_arch_name
= concat (name
,
2870 (const char *) NULL
);
2874 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
2875 cpu_arch_flags
= flags
;
2876 cpu_arch_isa_flags
= flags
;
2880 = cpu_flags_or (cpu_arch_isa_flags
,
2882 (void) restore_line_pointer (e
);
2883 demand_empty_rest_of_line ();
2888 if (*string
== '.' && j
>= ARRAY_SIZE (cpu_arch
))
2890 /* Disable an ISA extension. */
2891 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
2892 if (strcmp (string
+ 1, cpu_noarch
[j
].name
) == 0)
2894 flags
= cpu_flags_and_not (cpu_arch_flags
,
2895 cpu_noarch
[j
].flags
);
2896 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2898 if (cpu_sub_arch_name
)
2900 char *name
= cpu_sub_arch_name
;
2901 cpu_sub_arch_name
= concat (name
, string
,
2902 (const char *) NULL
);
2906 cpu_sub_arch_name
= xstrdup (string
);
2907 cpu_arch_flags
= flags
;
2908 cpu_arch_isa_flags
= flags
;
2910 (void) restore_line_pointer (e
);
2911 demand_empty_rest_of_line ();
2915 j
= ARRAY_SIZE (cpu_arch
);
2918 if (j
>= ARRAY_SIZE (cpu_arch
))
2919 as_bad (_("no such architecture: `%s'"), string
);
2921 *input_line_pointer
= e
;
2924 as_bad (_("missing cpu architecture"));
2926 no_cond_jump_promotion
= 0;
2927 if (*input_line_pointer
== ','
2928 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
2933 ++input_line_pointer
;
2934 e
= get_symbol_name (&string
);
2936 if (strcmp (string
, "nojumps") == 0)
2937 no_cond_jump_promotion
= 1;
2938 else if (strcmp (string
, "jumps") == 0)
2941 as_bad (_("no such architecture modifier: `%s'"), string
);
2943 (void) restore_line_pointer (e
);
2946 demand_empty_rest_of_line ();
2949 enum bfd_architecture
2952 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2954 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2955 || flag_code
!= CODE_64BIT
)
2956 as_fatal (_("Intel L1OM is 64bit ELF only"));
2957 return bfd_arch_l1om
;
2959 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2961 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2962 || flag_code
!= CODE_64BIT
)
2963 as_fatal (_("Intel K1OM is 64bit ELF only"));
2964 return bfd_arch_k1om
;
2966 else if (cpu_arch_isa
== PROCESSOR_IAMCU
)
2968 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2969 || flag_code
== CODE_64BIT
)
2970 as_fatal (_("Intel MCU is 32bit ELF only"));
2971 return bfd_arch_iamcu
;
2974 return bfd_arch_i386
;
2980 if (!strncmp (default_arch
, "x86_64", 6))
2982 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2984 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2985 || default_arch
[6] != '\0')
2986 as_fatal (_("Intel L1OM is 64bit ELF only"));
2987 return bfd_mach_l1om
;
2989 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2991 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2992 || default_arch
[6] != '\0')
2993 as_fatal (_("Intel K1OM is 64bit ELF only"));
2994 return bfd_mach_k1om
;
2996 else if (default_arch
[6] == '\0')
2997 return bfd_mach_x86_64
;
2999 return bfd_mach_x64_32
;
3001 else if (!strcmp (default_arch
, "i386")
3002 || !strcmp (default_arch
, "iamcu"))
3004 if (cpu_arch_isa
== PROCESSOR_IAMCU
)
3006 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
3007 as_fatal (_("Intel MCU is 32bit ELF only"));
3008 return bfd_mach_i386_iamcu
;
3011 return bfd_mach_i386_i386
;
3014 as_fatal (_("unknown architecture"));
3020 const char *hash_err
;
3022 /* Support pseudo prefixes like {disp32}. */
3023 lex_type
['{'] = LEX_BEGIN_NAME
;
3025 /* Initialize op_hash hash table. */
3026 op_hash
= hash_new ();
3029 const insn_template
*optab
;
3030 templates
*core_optab
;
3032 /* Setup for loop. */
3034 core_optab
= XNEW (templates
);
3035 core_optab
->start
= optab
;
3040 if (optab
->name
== NULL
3041 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
3043 /* different name --> ship out current template list;
3044 add to hash table; & begin anew. */
3045 core_optab
->end
= optab
;
3046 hash_err
= hash_insert (op_hash
,
3048 (void *) core_optab
);
3051 as_fatal (_("can't hash %s: %s"),
3055 if (optab
->name
== NULL
)
3057 core_optab
= XNEW (templates
);
3058 core_optab
->start
= optab
;
3063 /* Initialize reg_hash hash table. */
3064 reg_hash
= hash_new ();
3066 const reg_entry
*regtab
;
3067 unsigned int regtab_size
= i386_regtab_size
;
3069 for (regtab
= i386_regtab
; regtab_size
--; regtab
++)
3071 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (void *) regtab
);
3073 as_fatal (_("can't hash %s: %s"),
3079 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
3084 for (c
= 0; c
< 256; c
++)
3089 mnemonic_chars
[c
] = c
;
3090 register_chars
[c
] = c
;
3091 operand_chars
[c
] = c
;
3093 else if (ISLOWER (c
))
3095 mnemonic_chars
[c
] = c
;
3096 register_chars
[c
] = c
;
3097 operand_chars
[c
] = c
;
3099 else if (ISUPPER (c
))
3101 mnemonic_chars
[c
] = TOLOWER (c
);
3102 register_chars
[c
] = mnemonic_chars
[c
];
3103 operand_chars
[c
] = c
;
3105 else if (c
== '{' || c
== '}')
3107 mnemonic_chars
[c
] = c
;
3108 operand_chars
[c
] = c
;
3111 if (ISALPHA (c
) || ISDIGIT (c
))
3112 identifier_chars
[c
] = c
;
3115 identifier_chars
[c
] = c
;
3116 operand_chars
[c
] = c
;
3121 identifier_chars
['@'] = '@';
3124 identifier_chars
['?'] = '?';
3125 operand_chars
['?'] = '?';
3127 digit_chars
['-'] = '-';
3128 mnemonic_chars
['_'] = '_';
3129 mnemonic_chars
['-'] = '-';
3130 mnemonic_chars
['.'] = '.';
3131 identifier_chars
['_'] = '_';
3132 identifier_chars
['.'] = '.';
3134 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
3135 operand_chars
[(unsigned char) *p
] = *p
;
3138 if (flag_code
== CODE_64BIT
)
3140 #if defined (OBJ_COFF) && defined (TE_PE)
3141 x86_dwarf2_return_column
= (OUTPUT_FLAVOR
== bfd_target_coff_flavour
3144 x86_dwarf2_return_column
= 16;
3146 x86_cie_data_alignment
= -8;
3150 x86_dwarf2_return_column
= 8;
3151 x86_cie_data_alignment
= -4;
3154 /* NB: FUSED_JCC_PADDING frag must have sufficient room so that it
3155 can be turned into BRANCH_PREFIX frag. */
3156 if (align_branch_prefix_size
> MAX_FUSED_JCC_PADDING_SIZE
)
3161 i386_print_statistics (FILE *file
)
3163 hash_print_statistics (file
, "i386 opcode", op_hash
);
3164 hash_print_statistics (file
, "i386 register", reg_hash
);
3169 /* Debugging routines for md_assemble. */
3170 static void pte (insn_template
*);
3171 static void pt (i386_operand_type
);
3172 static void pe (expressionS
*);
3173 static void ps (symbolS
*);
3176 pi (const char *line
, i386_insn
*x
)
3180 fprintf (stdout
, "%s: template ", line
);
3182 fprintf (stdout
, " address: base %s index %s scale %x\n",
3183 x
->base_reg
? x
->base_reg
->reg_name
: "none",
3184 x
->index_reg
? x
->index_reg
->reg_name
: "none",
3185 x
->log2_scale_factor
);
3186 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
3187 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
3188 fprintf (stdout
, " sib: base %x index %x scale %x\n",
3189 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
3190 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
3191 (x
->rex
& REX_W
) != 0,
3192 (x
->rex
& REX_R
) != 0,
3193 (x
->rex
& REX_X
) != 0,
3194 (x
->rex
& REX_B
) != 0);
3195 for (j
= 0; j
< x
->operands
; j
++)
3197 fprintf (stdout
, " #%d: ", j
+ 1);
3199 fprintf (stdout
, "\n");
3200 if (x
->types
[j
].bitfield
.class == Reg
3201 || x
->types
[j
].bitfield
.class == RegMMX
3202 || x
->types
[j
].bitfield
.class == RegSIMD
3203 || x
->types
[j
].bitfield
.class == RegMask
3204 || x
->types
[j
].bitfield
.class == SReg
3205 || x
->types
[j
].bitfield
.class == RegCR
3206 || x
->types
[j
].bitfield
.class == RegDR
3207 || x
->types
[j
].bitfield
.class == RegTR
3208 || x
->types
[j
].bitfield
.class == RegBND
)
3209 fprintf (stdout
, "%s\n", x
->op
[j
].regs
->reg_name
);
3210 if (operand_type_check (x
->types
[j
], imm
))
3212 if (operand_type_check (x
->types
[j
], disp
))
3213 pe (x
->op
[j
].disps
);
3218 pte (insn_template
*t
)
3221 fprintf (stdout
, " %d operands ", t
->operands
);
3222 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
3223 if (t
->extension_opcode
!= None
)
3224 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
3225 if (t
->opcode_modifier
.d
)
3226 fprintf (stdout
, "D");
3227 if (t
->opcode_modifier
.w
)
3228 fprintf (stdout
, "W");
3229 fprintf (stdout
, "\n");
3230 for (j
= 0; j
< t
->operands
; j
++)
3232 fprintf (stdout
, " #%d type ", j
+ 1);
3233 pt (t
->operand_types
[j
]);
3234 fprintf (stdout
, "\n");
3241 fprintf (stdout
, " operation %d\n", e
->X_op
);
3242 fprintf (stdout
, " add_number %ld (%lx)\n",
3243 (long) e
->X_add_number
, (long) e
->X_add_number
);
3244 if (e
->X_add_symbol
)
3246 fprintf (stdout
, " add_symbol ");
3247 ps (e
->X_add_symbol
);
3248 fprintf (stdout
, "\n");
3252 fprintf (stdout
, " op_symbol ");
3253 ps (e
->X_op_symbol
);
3254 fprintf (stdout
, "\n");
3261 fprintf (stdout
, "%s type %s%s",
3263 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
3264 segment_name (S_GET_SEGMENT (s
)));
3267 static struct type_name
3269 i386_operand_type mask
;
3272 const type_names
[] =
3274 { OPERAND_TYPE_REG8
, "r8" },
3275 { OPERAND_TYPE_REG16
, "r16" },
3276 { OPERAND_TYPE_REG32
, "r32" },
3277 { OPERAND_TYPE_REG64
, "r64" },
3278 { OPERAND_TYPE_ACC8
, "acc8" },
3279 { OPERAND_TYPE_ACC16
, "acc16" },
3280 { OPERAND_TYPE_ACC32
, "acc32" },
3281 { OPERAND_TYPE_ACC64
, "acc64" },
3282 { OPERAND_TYPE_IMM8
, "i8" },
3283 { OPERAND_TYPE_IMM8
, "i8s" },
3284 { OPERAND_TYPE_IMM16
, "i16" },
3285 { OPERAND_TYPE_IMM32
, "i32" },
3286 { OPERAND_TYPE_IMM32S
, "i32s" },
3287 { OPERAND_TYPE_IMM64
, "i64" },
3288 { OPERAND_TYPE_IMM1
, "i1" },
3289 { OPERAND_TYPE_BASEINDEX
, "BaseIndex" },
3290 { OPERAND_TYPE_DISP8
, "d8" },
3291 { OPERAND_TYPE_DISP16
, "d16" },
3292 { OPERAND_TYPE_DISP32
, "d32" },
3293 { OPERAND_TYPE_DISP32S
, "d32s" },
3294 { OPERAND_TYPE_DISP64
, "d64" },
3295 { OPERAND_TYPE_INOUTPORTREG
, "InOutPortReg" },
3296 { OPERAND_TYPE_SHIFTCOUNT
, "ShiftCount" },
3297 { OPERAND_TYPE_CONTROL
, "control reg" },
3298 { OPERAND_TYPE_TEST
, "test reg" },
3299 { OPERAND_TYPE_DEBUG
, "debug reg" },
3300 { OPERAND_TYPE_FLOATREG
, "FReg" },
3301 { OPERAND_TYPE_FLOATACC
, "FAcc" },
3302 { OPERAND_TYPE_SREG
, "SReg" },
3303 { OPERAND_TYPE_REGMMX
, "rMMX" },
3304 { OPERAND_TYPE_REGXMM
, "rXMM" },
3305 { OPERAND_TYPE_REGYMM
, "rYMM" },
3306 { OPERAND_TYPE_REGZMM
, "rZMM" },
3307 { OPERAND_TYPE_REGMASK
, "Mask reg" },
3311 pt (i386_operand_type t
)
3314 i386_operand_type a
;
3316 for (j
= 0; j
< ARRAY_SIZE (type_names
); j
++)
3318 a
= operand_type_and (t
, type_names
[j
].mask
);
3319 if (operand_type_equal (&a
, &type_names
[j
].mask
))
3320 fprintf (stdout
, "%s, ", type_names
[j
].name
);
3325 #endif /* DEBUG386 */
3327 static bfd_reloc_code_real_type
3328 reloc (unsigned int size
,
3331 bfd_reloc_code_real_type other
)
3333 if (other
!= NO_RELOC
)
3335 reloc_howto_type
*rel
;
3340 case BFD_RELOC_X86_64_GOT32
:
3341 return BFD_RELOC_X86_64_GOT64
;
3343 case BFD_RELOC_X86_64_GOTPLT64
:
3344 return BFD_RELOC_X86_64_GOTPLT64
;
3346 case BFD_RELOC_X86_64_PLTOFF64
:
3347 return BFD_RELOC_X86_64_PLTOFF64
;
3349 case BFD_RELOC_X86_64_GOTPC32
:
3350 other
= BFD_RELOC_X86_64_GOTPC64
;
3352 case BFD_RELOC_X86_64_GOTPCREL
:
3353 other
= BFD_RELOC_X86_64_GOTPCREL64
;
3355 case BFD_RELOC_X86_64_TPOFF32
:
3356 other
= BFD_RELOC_X86_64_TPOFF64
;
3358 case BFD_RELOC_X86_64_DTPOFF32
:
3359 other
= BFD_RELOC_X86_64_DTPOFF64
;
3365 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3366 if (other
== BFD_RELOC_SIZE32
)
3369 other
= BFD_RELOC_SIZE64
;
3372 as_bad (_("there are no pc-relative size relocations"));
3378 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
3379 if (size
== 4 && (flag_code
!= CODE_64BIT
|| disallow_64bit_reloc
))
3382 rel
= bfd_reloc_type_lookup (stdoutput
, other
);
3384 as_bad (_("unknown relocation (%u)"), other
);
3385 else if (size
!= bfd_get_reloc_size (rel
))
3386 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
3387 bfd_get_reloc_size (rel
),
3389 else if (pcrel
&& !rel
->pc_relative
)
3390 as_bad (_("non-pc-relative relocation for pc-relative field"));
3391 else if ((rel
->complain_on_overflow
== complain_overflow_signed
3393 || (rel
->complain_on_overflow
== complain_overflow_unsigned
3395 as_bad (_("relocated field and relocation type differ in signedness"));
3404 as_bad (_("there are no unsigned pc-relative relocations"));
3407 case 1: return BFD_RELOC_8_PCREL
;
3408 case 2: return BFD_RELOC_16_PCREL
;
3409 case 4: return BFD_RELOC_32_PCREL
;
3410 case 8: return BFD_RELOC_64_PCREL
;
3412 as_bad (_("cannot do %u byte pc-relative relocation"), size
);
3419 case 4: return BFD_RELOC_X86_64_32S
;
3424 case 1: return BFD_RELOC_8
;
3425 case 2: return BFD_RELOC_16
;
3426 case 4: return BFD_RELOC_32
;
3427 case 8: return BFD_RELOC_64
;
3429 as_bad (_("cannot do %s %u byte relocation"),
3430 sign
> 0 ? "signed" : "unsigned", size
);
3436 /* Here we decide which fixups can be adjusted to make them relative to
3437 the beginning of the section instead of the symbol. Basically we need
3438 to make sure that the dynamic relocations are done correctly, so in
3439 some cases we force the original symbol to be used. */
3442 tc_i386_fix_adjustable (fixS
*fixP ATTRIBUTE_UNUSED
)
3444 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3448 /* Don't adjust pc-relative references to merge sections in 64-bit
3450 if (use_rela_relocations
3451 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
3455 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
3456 and changed later by validate_fix. */
3457 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
3458 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
3461 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
3462 for size relocations. */
3463 if (fixP
->fx_r_type
== BFD_RELOC_SIZE32
3464 || fixP
->fx_r_type
== BFD_RELOC_SIZE64
3465 || fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
3466 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
3467 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32X
3468 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
3469 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
3470 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
3471 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
3472 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
3473 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
3474 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
3475 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
3476 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTDESC
3477 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_DESC_CALL
3478 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
3479 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
3480 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCRELX
3481 || fixP
->fx_r_type
== BFD_RELOC_X86_64_REX_GOTPCRELX
3482 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
3483 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
3484 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
3485 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
3486 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
3487 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
3488 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
3489 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
3490 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPC32_TLSDESC
3491 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSDESC_CALL
3492 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
3493 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
3500 intel_float_operand (const char *mnemonic
)
3502 /* Note that the value returned is meaningful only for opcodes with (memory)
3503 operands, hence the code here is free to improperly handle opcodes that
3504 have no operands (for better performance and smaller code). */
3506 if (mnemonic
[0] != 'f')
3507 return 0; /* non-math */
3509 switch (mnemonic
[1])
3511 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
3512 the fs segment override prefix not currently handled because no
3513 call path can make opcodes without operands get here */
3515 return 2 /* integer op */;
3517 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
3518 return 3; /* fldcw/fldenv */
3521 if (mnemonic
[2] != 'o' /* fnop */)
3522 return 3; /* non-waiting control op */
3525 if (mnemonic
[2] == 's')
3526 return 3; /* frstor/frstpm */
3529 if (mnemonic
[2] == 'a')
3530 return 3; /* fsave */
3531 if (mnemonic
[2] == 't')
3533 switch (mnemonic
[3])
3535 case 'c': /* fstcw */
3536 case 'd': /* fstdw */
3537 case 'e': /* fstenv */
3538 case 's': /* fsts[gw] */
3544 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
3545 return 0; /* fxsave/fxrstor are not really math ops */
3552 /* Build the VEX prefix. */
3555 build_vex_prefix (const insn_template
*t
)
3557 unsigned int register_specifier
;
3558 unsigned int implied_prefix
;
3559 unsigned int vector_length
;
3562 /* Check register specifier. */
3563 if (i
.vex
.register_specifier
)
3565 register_specifier
=
3566 ~register_number (i
.vex
.register_specifier
) & 0xf;
3567 gas_assert ((i
.vex
.register_specifier
->reg_flags
& RegVRex
) == 0);
3570 register_specifier
= 0xf;
3572 /* Use 2-byte VEX prefix by swapping destination and source operand
3573 if there are more than 1 register operand. */
3574 if (i
.reg_operands
> 1
3575 && i
.vec_encoding
!= vex_encoding_vex3
3576 && i
.dir_encoding
== dir_encoding_default
3577 && i
.operands
== i
.reg_operands
3578 && operand_type_equal (&i
.types
[0], &i
.types
[i
.operands
- 1])
3579 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3580 && (i
.tm
.opcode_modifier
.load
|| i
.tm
.opcode_modifier
.d
)
3583 unsigned int xchg
= i
.operands
- 1;
3584 union i386_op temp_op
;
3585 i386_operand_type temp_type
;
3587 temp_type
= i
.types
[xchg
];
3588 i
.types
[xchg
] = i
.types
[0];
3589 i
.types
[0] = temp_type
;
3590 temp_op
= i
.op
[xchg
];
3591 i
.op
[xchg
] = i
.op
[0];
3594 gas_assert (i
.rm
.mode
== 3);
3598 i
.rm
.regmem
= i
.rm
.reg
;
3601 if (i
.tm
.opcode_modifier
.d
)
3602 i
.tm
.base_opcode
^= (i
.tm
.base_opcode
& 0xee) != 0x6e
3603 ? Opcode_SIMD_FloatD
: Opcode_SIMD_IntD
;
3604 else /* Use the next insn. */
3608 /* Use 2-byte VEX prefix by swapping commutative source operands if there
3609 are no memory operands and at least 3 register ones. */
3610 if (i
.reg_operands
>= 3
3611 && i
.vec_encoding
!= vex_encoding_vex3
3612 && i
.reg_operands
== i
.operands
- i
.imm_operands
3613 && i
.tm
.opcode_modifier
.vex
3614 && i
.tm
.opcode_modifier
.commutative
3615 && (i
.tm
.opcode_modifier
.sse2avx
|| optimize
> 1)
3617 && i
.vex
.register_specifier
3618 && !(i
.vex
.register_specifier
->reg_flags
& RegRex
))
3620 unsigned int xchg
= i
.operands
- i
.reg_operands
;
3621 union i386_op temp_op
;
3622 i386_operand_type temp_type
;
3624 gas_assert (i
.tm
.opcode_modifier
.vexopcode
== VEX0F
);
3625 gas_assert (!i
.tm
.opcode_modifier
.sae
);
3626 gas_assert (operand_type_equal (&i
.types
[i
.operands
- 2],
3627 &i
.types
[i
.operands
- 3]));
3628 gas_assert (i
.rm
.mode
== 3);
3630 temp_type
= i
.types
[xchg
];
3631 i
.types
[xchg
] = i
.types
[xchg
+ 1];
3632 i
.types
[xchg
+ 1] = temp_type
;
3633 temp_op
= i
.op
[xchg
];
3634 i
.op
[xchg
] = i
.op
[xchg
+ 1];
3635 i
.op
[xchg
+ 1] = temp_op
;
3638 xchg
= i
.rm
.regmem
| 8;
3639 i
.rm
.regmem
= ~register_specifier
& 0xf;
3640 gas_assert (!(i
.rm
.regmem
& 8));
3641 i
.vex
.register_specifier
+= xchg
- i
.rm
.regmem
;
3642 register_specifier
= ~xchg
& 0xf;
3645 if (i
.tm
.opcode_modifier
.vex
== VEXScalar
)
3646 vector_length
= avxscalar
;
3647 else if (i
.tm
.opcode_modifier
.vex
== VEX256
)
3653 /* Determine vector length from the last multi-length vector
3656 for (op
= t
->operands
; op
--;)
3657 if (t
->operand_types
[op
].bitfield
.xmmword
3658 && t
->operand_types
[op
].bitfield
.ymmword
3659 && i
.types
[op
].bitfield
.ymmword
)
3666 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3671 case DATA_PREFIX_OPCODE
:
3674 case REPE_PREFIX_OPCODE
:
3677 case REPNE_PREFIX_OPCODE
:
3684 /* Check the REX.W bit and VEXW. */
3685 if (i
.tm
.opcode_modifier
.vexw
== VEXWIG
)
3686 w
= (vexwig
== vexw1
|| (i
.rex
& REX_W
)) ? 1 : 0;
3687 else if (i
.tm
.opcode_modifier
.vexw
)
3688 w
= i
.tm
.opcode_modifier
.vexw
== VEXW1
? 1 : 0;
3690 w
= (flag_code
== CODE_64BIT
? i
.rex
& REX_W
: vexwig
== vexw1
) ? 1 : 0;
3692 /* Use 2-byte VEX prefix if possible. */
3694 && i
.vec_encoding
!= vex_encoding_vex3
3695 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3696 && (i
.rex
& (REX_W
| REX_X
| REX_B
)) == 0)
3698 /* 2-byte VEX prefix. */
3702 i
.vex
.bytes
[0] = 0xc5;
3704 /* Check the REX.R bit. */
3705 r
= (i
.rex
& REX_R
) ? 0 : 1;
3706 i
.vex
.bytes
[1] = (r
<< 7
3707 | register_specifier
<< 3
3708 | vector_length
<< 2
3713 /* 3-byte VEX prefix. */
3718 switch (i
.tm
.opcode_modifier
.vexopcode
)
3722 i
.vex
.bytes
[0] = 0xc4;
3726 i
.vex
.bytes
[0] = 0xc4;
3730 i
.vex
.bytes
[0] = 0xc4;
3734 i
.vex
.bytes
[0] = 0x8f;
3738 i
.vex
.bytes
[0] = 0x8f;
3742 i
.vex
.bytes
[0] = 0x8f;
3748 /* The high 3 bits of the second VEX byte are 1's compliment
3749 of RXB bits from REX. */
3750 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3752 i
.vex
.bytes
[2] = (w
<< 7
3753 | register_specifier
<< 3
3754 | vector_length
<< 2
3759 static INLINE bfd_boolean
3760 is_evex_encoding (const insn_template
*t
)
3762 return t
->opcode_modifier
.evex
|| t
->opcode_modifier
.disp8memshift
3763 || t
->opcode_modifier
.broadcast
|| t
->opcode_modifier
.masking
3764 || t
->opcode_modifier
.sae
;
3767 static INLINE bfd_boolean
3768 is_any_vex_encoding (const insn_template
*t
)
3770 return t
->opcode_modifier
.vex
|| t
->opcode_modifier
.vexopcode
3771 || is_evex_encoding (t
);
3774 /* Build the EVEX prefix. */
3777 build_evex_prefix (void)
3779 unsigned int register_specifier
;
3780 unsigned int implied_prefix
;
3782 rex_byte vrex_used
= 0;
3784 /* Check register specifier. */
3785 if (i
.vex
.register_specifier
)
3787 gas_assert ((i
.vrex
& REX_X
) == 0);
3789 register_specifier
= i
.vex
.register_specifier
->reg_num
;
3790 if ((i
.vex
.register_specifier
->reg_flags
& RegRex
))
3791 register_specifier
+= 8;
3792 /* The upper 16 registers are encoded in the fourth byte of the
3794 if (!(i
.vex
.register_specifier
->reg_flags
& RegVRex
))
3795 i
.vex
.bytes
[3] = 0x8;
3796 register_specifier
= ~register_specifier
& 0xf;
3800 register_specifier
= 0xf;
3802 /* Encode upper 16 vector index register in the fourth byte of
3804 if (!(i
.vrex
& REX_X
))
3805 i
.vex
.bytes
[3] = 0x8;
3810 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3815 case DATA_PREFIX_OPCODE
:
3818 case REPE_PREFIX_OPCODE
:
3821 case REPNE_PREFIX_OPCODE
:
3828 /* 4 byte EVEX prefix. */
3830 i
.vex
.bytes
[0] = 0x62;
3833 switch (i
.tm
.opcode_modifier
.vexopcode
)
3849 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3851 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3853 /* The fifth bit of the second EVEX byte is 1's compliment of the
3854 REX_R bit in VREX. */
3855 if (!(i
.vrex
& REX_R
))
3856 i
.vex
.bytes
[1] |= 0x10;
3860 if ((i
.reg_operands
+ i
.imm_operands
) == i
.operands
)
3862 /* When all operands are registers, the REX_X bit in REX is not
3863 used. We reuse it to encode the upper 16 registers, which is
3864 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3865 as 1's compliment. */
3866 if ((i
.vrex
& REX_B
))
3869 i
.vex
.bytes
[1] &= ~0x40;
3873 /* EVEX instructions shouldn't need the REX prefix. */
3874 i
.vrex
&= ~vrex_used
;
3875 gas_assert (i
.vrex
== 0);
3877 /* Check the REX.W bit and VEXW. */
3878 if (i
.tm
.opcode_modifier
.vexw
== VEXWIG
)
3879 w
= (evexwig
== evexw1
|| (i
.rex
& REX_W
)) ? 1 : 0;
3880 else if (i
.tm
.opcode_modifier
.vexw
)
3881 w
= i
.tm
.opcode_modifier
.vexw
== VEXW1
? 1 : 0;
3883 w
= (flag_code
== CODE_64BIT
? i
.rex
& REX_W
: evexwig
== evexw1
) ? 1 : 0;
3885 /* Encode the U bit. */
3886 implied_prefix
|= 0x4;
3888 /* The third byte of the EVEX prefix. */
3889 i
.vex
.bytes
[2] = (w
<< 7 | register_specifier
<< 3 | implied_prefix
);
3891 /* The fourth byte of the EVEX prefix. */
3892 /* The zeroing-masking bit. */
3893 if (i
.mask
&& i
.mask
->zeroing
)
3894 i
.vex
.bytes
[3] |= 0x80;
3896 /* Don't always set the broadcast bit if there is no RC. */
3899 /* Encode the vector length. */
3900 unsigned int vec_length
;
3902 if (!i
.tm
.opcode_modifier
.evex
3903 || i
.tm
.opcode_modifier
.evex
== EVEXDYN
)
3907 /* Determine vector length from the last multi-length vector
3909 for (op
= i
.operands
; op
--;)
3910 if (i
.tm
.operand_types
[op
].bitfield
.xmmword
3911 + i
.tm
.operand_types
[op
].bitfield
.ymmword
3912 + i
.tm
.operand_types
[op
].bitfield
.zmmword
> 1)
3914 if (i
.types
[op
].bitfield
.zmmword
)
3916 i
.tm
.opcode_modifier
.evex
= EVEX512
;
3919 else if (i
.types
[op
].bitfield
.ymmword
)
3921 i
.tm
.opcode_modifier
.evex
= EVEX256
;
3924 else if (i
.types
[op
].bitfield
.xmmword
)
3926 i
.tm
.opcode_modifier
.evex
= EVEX128
;
3929 else if (i
.broadcast
&& (int) op
== i
.broadcast
->operand
)
3931 switch (i
.broadcast
->bytes
)
3934 i
.tm
.opcode_modifier
.evex
= EVEX512
;
3937 i
.tm
.opcode_modifier
.evex
= EVEX256
;
3940 i
.tm
.opcode_modifier
.evex
= EVEX128
;
3949 if (op
>= MAX_OPERANDS
)
3953 switch (i
.tm
.opcode_modifier
.evex
)
3955 case EVEXLIG
: /* LL' is ignored */
3956 vec_length
= evexlig
<< 5;
3959 vec_length
= 0 << 5;
3962 vec_length
= 1 << 5;
3965 vec_length
= 2 << 5;
3971 i
.vex
.bytes
[3] |= vec_length
;
3972 /* Encode the broadcast bit. */
3974 i
.vex
.bytes
[3] |= 0x10;
3978 if (i
.rounding
->type
!= saeonly
)
3979 i
.vex
.bytes
[3] |= 0x10 | (i
.rounding
->type
<< 5);
3981 i
.vex
.bytes
[3] |= 0x10 | (evexrcig
<< 5);
3984 if (i
.mask
&& i
.mask
->mask
)
3985 i
.vex
.bytes
[3] |= i
.mask
->mask
->reg_num
;
3989 process_immext (void)
3993 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
3994 which is coded in the same place as an 8-bit immediate field
3995 would be. Here we fake an 8-bit immediate operand from the
3996 opcode suffix stored in tm.extension_opcode.
3998 AVX instructions also use this encoding, for some of
3999 3 argument instructions. */
4001 gas_assert (i
.imm_operands
<= 1
4003 || (is_any_vex_encoding (&i
.tm
)
4004 && i
.operands
<= 4)));
4006 exp
= &im_expressions
[i
.imm_operands
++];
4007 i
.op
[i
.operands
].imms
= exp
;
4008 i
.types
[i
.operands
] = imm8
;
4010 exp
->X_op
= O_constant
;
4011 exp
->X_add_number
= i
.tm
.extension_opcode
;
4012 i
.tm
.extension_opcode
= None
;
4019 switch (i
.tm
.opcode_modifier
.hleprefixok
)
4024 as_bad (_("invalid instruction `%s' after `%s'"),
4025 i
.tm
.name
, i
.hle_prefix
);
4028 if (i
.prefix
[LOCK_PREFIX
])
4030 as_bad (_("missing `lock' with `%s'"), i
.hle_prefix
);
4034 case HLEPrefixRelease
:
4035 if (i
.prefix
[HLE_PREFIX
] != XRELEASE_PREFIX_OPCODE
)
4037 as_bad (_("instruction `%s' after `xacquire' not allowed"),
4041 if (i
.mem_operands
== 0 || !(i
.flags
[i
.operands
- 1] & Operand_Mem
))
4043 as_bad (_("memory destination needed for instruction `%s'"
4044 " after `xrelease'"), i
.tm
.name
);
4051 /* Try the shortest encoding by shortening operand size. */
4054 optimize_encoding (void)
4058 if (optimize_for_space
4059 && !is_any_vex_encoding (&i
.tm
)
4060 && i
.reg_operands
== 1
4061 && i
.imm_operands
== 1
4062 && !i
.types
[1].bitfield
.byte
4063 && i
.op
[0].imms
->X_op
== O_constant
4064 && fits_in_imm7 (i
.op
[0].imms
->X_add_number
)
4065 && (i
.tm
.base_opcode
== 0xa8
4066 || (i
.tm
.base_opcode
== 0xf6
4067 && i
.tm
.extension_opcode
== 0x0)))
4070 test $imm7, %r64/%r32/%r16 -> test $imm7, %r8
4072 unsigned int base_regnum
= i
.op
[1].regs
->reg_num
;
4073 if (flag_code
== CODE_64BIT
|| base_regnum
< 4)
4075 i
.types
[1].bitfield
.byte
= 1;
4076 /* Ignore the suffix. */
4078 /* Convert to byte registers. */
4079 if (i
.types
[1].bitfield
.word
)
4081 else if (i
.types
[1].bitfield
.dword
)
4085 if (!(i
.op
[1].regs
->reg_flags
& RegRex
) && base_regnum
< 4)
4090 else if (flag_code
== CODE_64BIT
4091 && !is_any_vex_encoding (&i
.tm
)
4092 && ((i
.types
[1].bitfield
.qword
4093 && i
.reg_operands
== 1
4094 && i
.imm_operands
== 1
4095 && i
.op
[0].imms
->X_op
== O_constant
4096 && ((i
.tm
.base_opcode
== 0xb8
4097 && i
.tm
.extension_opcode
== None
4098 && fits_in_unsigned_long (i
.op
[0].imms
->X_add_number
))
4099 || (fits_in_imm31 (i
.op
[0].imms
->X_add_number
)
4100 && ((i
.tm
.base_opcode
== 0x24
4101 || i
.tm
.base_opcode
== 0xa8)
4102 || (i
.tm
.base_opcode
== 0x80
4103 && i
.tm
.extension_opcode
== 0x4)
4104 || ((i
.tm
.base_opcode
== 0xf6
4105 || (i
.tm
.base_opcode
| 1) == 0xc7)
4106 && i
.tm
.extension_opcode
== 0x0)))
4107 || (fits_in_imm7 (i
.op
[0].imms
->X_add_number
)
4108 && i
.tm
.base_opcode
== 0x83
4109 && i
.tm
.extension_opcode
== 0x4)))
4110 || (i
.types
[0].bitfield
.qword
4111 && ((i
.reg_operands
== 2
4112 && i
.op
[0].regs
== i
.op
[1].regs
4113 && (i
.tm
.base_opcode
== 0x30
4114 || i
.tm
.base_opcode
== 0x28))
4115 || (i
.reg_operands
== 1
4117 && i
.tm
.base_opcode
== 0x30)))))
4120 andq $imm31, %r64 -> andl $imm31, %r32
4121 andq $imm7, %r64 -> andl $imm7, %r32
4122 testq $imm31, %r64 -> testl $imm31, %r32
4123 xorq %r64, %r64 -> xorl %r32, %r32
4124 subq %r64, %r64 -> subl %r32, %r32
4125 movq $imm31, %r64 -> movl $imm31, %r32
4126 movq $imm32, %r64 -> movl $imm32, %r32
4128 i
.tm
.opcode_modifier
.norex64
= 1;
4129 if (i
.tm
.base_opcode
== 0xb8 || (i
.tm
.base_opcode
| 1) == 0xc7)
4132 movq $imm31, %r64 -> movl $imm31, %r32
4133 movq $imm32, %r64 -> movl $imm32, %r32
4135 i
.tm
.operand_types
[0].bitfield
.imm32
= 1;
4136 i
.tm
.operand_types
[0].bitfield
.imm32s
= 0;
4137 i
.tm
.operand_types
[0].bitfield
.imm64
= 0;
4138 i
.types
[0].bitfield
.imm32
= 1;
4139 i
.types
[0].bitfield
.imm32s
= 0;
4140 i
.types
[0].bitfield
.imm64
= 0;
4141 i
.types
[1].bitfield
.dword
= 1;
4142 i
.types
[1].bitfield
.qword
= 0;
4143 if ((i
.tm
.base_opcode
| 1) == 0xc7)
4146 movq $imm31, %r64 -> movl $imm31, %r32
4148 i
.tm
.base_opcode
= 0xb8;
4149 i
.tm
.extension_opcode
= None
;
4150 i
.tm
.opcode_modifier
.w
= 0;
4151 i
.tm
.opcode_modifier
.modrm
= 0;
4155 else if (optimize
> 1
4156 && !optimize_for_space
4157 && !is_any_vex_encoding (&i
.tm
)
4158 && i
.reg_operands
== 2
4159 && i
.op
[0].regs
== i
.op
[1].regs
4160 && ((i
.tm
.base_opcode
& ~(Opcode_D
| 1)) == 0x8
4161 || (i
.tm
.base_opcode
& ~(Opcode_D
| 1)) == 0x20)
4162 && (flag_code
!= CODE_64BIT
|| !i
.types
[0].bitfield
.dword
))
4165 andb %rN, %rN -> testb %rN, %rN
4166 andw %rN, %rN -> testw %rN, %rN
4167 andq %rN, %rN -> testq %rN, %rN
4168 orb %rN, %rN -> testb %rN, %rN
4169 orw %rN, %rN -> testw %rN, %rN
4170 orq %rN, %rN -> testq %rN, %rN
4172 and outside of 64-bit mode
4174 andl %rN, %rN -> testl %rN, %rN
4175 orl %rN, %rN -> testl %rN, %rN
4177 i
.tm
.base_opcode
= 0x84 | (i
.tm
.base_opcode
& 1);
4179 else if (i
.reg_operands
== 3
4180 && i
.op
[0].regs
== i
.op
[1].regs
4181 && !i
.types
[2].bitfield
.xmmword
4182 && (i
.tm
.opcode_modifier
.vex
4183 || ((!i
.mask
|| i
.mask
->zeroing
)
4185 && is_evex_encoding (&i
.tm
)
4186 && (i
.vec_encoding
!= vex_encoding_evex
4187 || cpu_arch_isa_flags
.bitfield
.cpuavx512vl
4188 || i
.tm
.cpu_flags
.bitfield
.cpuavx512vl
4189 || (i
.tm
.operand_types
[2].bitfield
.zmmword
4190 && i
.types
[2].bitfield
.ymmword
))))
4191 && ((i
.tm
.base_opcode
== 0x55
4192 || i
.tm
.base_opcode
== 0x6655
4193 || i
.tm
.base_opcode
== 0x66df
4194 || i
.tm
.base_opcode
== 0x57
4195 || i
.tm
.base_opcode
== 0x6657
4196 || i
.tm
.base_opcode
== 0x66ef
4197 || i
.tm
.base_opcode
== 0x66f8
4198 || i
.tm
.base_opcode
== 0x66f9
4199 || i
.tm
.base_opcode
== 0x66fa
4200 || i
.tm
.base_opcode
== 0x66fb
4201 || i
.tm
.base_opcode
== 0x42
4202 || i
.tm
.base_opcode
== 0x6642
4203 || i
.tm
.base_opcode
== 0x47
4204 || i
.tm
.base_opcode
== 0x6647)
4205 && i
.tm
.extension_opcode
== None
))
4208 VOP, one of vandnps, vandnpd, vxorps, vxorpd, vpsubb, vpsubd,
4210 EVEX VOP %zmmM, %zmmM, %zmmN
4211 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
4212 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4213 EVEX VOP %ymmM, %ymmM, %ymmN
4214 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
4215 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4216 VEX VOP %ymmM, %ymmM, %ymmN
4217 -> VEX VOP %xmmM, %xmmM, %xmmN
4218 VOP, one of vpandn and vpxor:
4219 VEX VOP %ymmM, %ymmM, %ymmN
4220 -> VEX VOP %xmmM, %xmmM, %xmmN
4221 VOP, one of vpandnd and vpandnq:
4222 EVEX VOP %zmmM, %zmmM, %zmmN
4223 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
4224 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4225 EVEX VOP %ymmM, %ymmM, %ymmN
4226 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
4227 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4228 VOP, one of vpxord and vpxorq:
4229 EVEX VOP %zmmM, %zmmM, %zmmN
4230 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
4231 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4232 EVEX VOP %ymmM, %ymmM, %ymmN
4233 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
4234 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4235 VOP, one of kxord and kxorq:
4236 VEX VOP %kM, %kM, %kN
4237 -> VEX kxorw %kM, %kM, %kN
4238 VOP, one of kandnd and kandnq:
4239 VEX VOP %kM, %kM, %kN
4240 -> VEX kandnw %kM, %kM, %kN
4242 if (is_evex_encoding (&i
.tm
))
4244 if (i
.vec_encoding
!= vex_encoding_evex
)
4246 i
.tm
.opcode_modifier
.vex
= VEX128
;
4247 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4248 i
.tm
.opcode_modifier
.evex
= 0;
4250 else if (optimize
> 1)
4251 i
.tm
.opcode_modifier
.evex
= EVEX128
;
4255 else if (i
.tm
.operand_types
[0].bitfield
.class == RegMask
)
4257 i
.tm
.base_opcode
&= 0xff;
4258 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4261 i
.tm
.opcode_modifier
.vex
= VEX128
;
4263 if (i
.tm
.opcode_modifier
.vex
)
4264 for (j
= 0; j
< 3; j
++)
4266 i
.types
[j
].bitfield
.xmmword
= 1;
4267 i
.types
[j
].bitfield
.ymmword
= 0;
4270 else if (i
.vec_encoding
!= vex_encoding_evex
4271 && !i
.types
[0].bitfield
.zmmword
4272 && !i
.types
[1].bitfield
.zmmword
4275 && is_evex_encoding (&i
.tm
)
4276 && ((i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0x666f
4277 || (i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0xf36f
4278 || (i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0xf26f
4279 || (i
.tm
.base_opcode
& ~4) == 0x66db
4280 || (i
.tm
.base_opcode
& ~4) == 0x66eb)
4281 && i
.tm
.extension_opcode
== None
)
4284 VOP, one of vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16,
4285 vmovdqu32 and vmovdqu64:
4286 EVEX VOP %xmmM, %xmmN
4287 -> VEX vmovdqa|vmovdqu %xmmM, %xmmN (M and N < 16)
4288 EVEX VOP %ymmM, %ymmN
4289 -> VEX vmovdqa|vmovdqu %ymmM, %ymmN (M and N < 16)
4291 -> VEX vmovdqa|vmovdqu %xmmM, mem (M < 16)
4293 -> VEX vmovdqa|vmovdqu %ymmM, mem (M < 16)
4295 -> VEX mvmovdqa|vmovdquem, %xmmN (N < 16)
4297 -> VEX vmovdqa|vmovdqu mem, %ymmN (N < 16)
4298 VOP, one of vpand, vpandn, vpor, vpxor:
4299 EVEX VOP{d,q} %xmmL, %xmmM, %xmmN
4300 -> VEX VOP %xmmL, %xmmM, %xmmN (L, M, and N < 16)
4301 EVEX VOP{d,q} %ymmL, %ymmM, %ymmN
4302 -> VEX VOP %ymmL, %ymmM, %ymmN (L, M, and N < 16)
4303 EVEX VOP{d,q} mem, %xmmM, %xmmN
4304 -> VEX VOP mem, %xmmM, %xmmN (M and N < 16)
4305 EVEX VOP{d,q} mem, %ymmM, %ymmN
4306 -> VEX VOP mem, %ymmM, %ymmN (M and N < 16)
4308 for (j
= 0; j
< i
.operands
; j
++)
4309 if (operand_type_check (i
.types
[j
], disp
)
4310 && i
.op
[j
].disps
->X_op
== O_constant
)
4312 /* Since the VEX prefix has 2 or 3 bytes, the EVEX prefix
4313 has 4 bytes, EVEX Disp8 has 1 byte and VEX Disp32 has 4
4314 bytes, we choose EVEX Disp8 over VEX Disp32. */
4315 int evex_disp8
, vex_disp8
;
4316 unsigned int memshift
= i
.memshift
;
4317 offsetT n
= i
.op
[j
].disps
->X_add_number
;
4319 evex_disp8
= fits_in_disp8 (n
);
4321 vex_disp8
= fits_in_disp8 (n
);
4322 if (evex_disp8
!= vex_disp8
)
4324 i
.memshift
= memshift
;
4328 i
.types
[j
].bitfield
.disp8
= vex_disp8
;
4331 if ((i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0xf26f)
4332 i
.tm
.base_opcode
^= 0xf36f ^ 0xf26f;
4333 i
.tm
.opcode_modifier
.vex
4334 = i
.types
[0].bitfield
.ymmword
? VEX256
: VEX128
;
4335 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4336 /* VPAND, VPOR, and VPXOR are commutative. */
4337 if (i
.reg_operands
== 3 && i
.tm
.base_opcode
!= 0x66df)
4338 i
.tm
.opcode_modifier
.commutative
= 1;
4339 i
.tm
.opcode_modifier
.evex
= 0;
4340 i
.tm
.opcode_modifier
.masking
= 0;
4341 i
.tm
.opcode_modifier
.broadcast
= 0;
4342 i
.tm
.opcode_modifier
.disp8memshift
= 0;
4345 i
.types
[j
].bitfield
.disp8
4346 = fits_in_disp8 (i
.op
[j
].disps
->X_add_number
);
4350 /* Return non-zero for load instruction. */
4356 int any_vex_p
= is_any_vex_encoding (&i
.tm
);
4357 unsigned int base_opcode
= i
.tm
.base_opcode
| 1;
4361 /* Anysize insns: lea, invlpg, clflush, prefetchnta, prefetcht0,
4362 prefetcht1, prefetcht2, prefetchtw, bndmk, bndcl, bndcu, bndcn,
4363 bndstx, bndldx, prefetchwt1, clflushopt, clwb, cldemote. */
4364 if (i
.tm
.opcode_modifier
.anysize
)
4367 /* pop, popf, popa. */
4368 if (strcmp (i
.tm
.name
, "pop") == 0
4369 || i
.tm
.base_opcode
== 0x9d
4370 || i
.tm
.base_opcode
== 0x61)
4373 /* movs, cmps, lods, scas. */
4374 if ((i
.tm
.base_opcode
| 0xb) == 0xaf)
4378 if (base_opcode
== 0x6f
4379 || i
.tm
.base_opcode
== 0xd7)
4381 /* NB: For AMD-specific insns with implicit memory operands,
4382 they're intentionally not covered. */
4385 /* No memory operand. */
4386 if (!i
.mem_operands
)
4392 if (i
.tm
.base_opcode
== 0xae
4393 && i
.tm
.opcode_modifier
.vex
4394 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
4395 && i
.tm
.extension_opcode
== 2)
4400 /* test, not, neg, mul, imul, div, idiv. */
4401 if ((i
.tm
.base_opcode
== 0xf6 || i
.tm
.base_opcode
== 0xf7)
4402 && i
.tm
.extension_opcode
!= 1)
4406 if (base_opcode
== 0xff && i
.tm
.extension_opcode
<= 1)
4409 /* add, or, adc, sbb, and, sub, xor, cmp. */
4410 if (i
.tm
.base_opcode
>= 0x80 && i
.tm
.base_opcode
<= 0x83)
4413 /* bt, bts, btr, btc. */
4414 if (i
.tm
.base_opcode
== 0xfba
4415 && (i
.tm
.extension_opcode
>= 4 && i
.tm
.extension_opcode
<= 7))
4418 /* rol, ror, rcl, rcr, shl/sal, shr, sar. */
4419 if ((base_opcode
== 0xc1
4420 || (i
.tm
.base_opcode
>= 0xd0 && i
.tm
.base_opcode
<= 0xd3))
4421 && i
.tm
.extension_opcode
!= 6)
4424 /* cmpxchg8b, cmpxchg16b, xrstors. */
4425 if (i
.tm
.base_opcode
== 0xfc7
4426 && (i
.tm
.extension_opcode
== 1 || i
.tm
.extension_opcode
== 3))
4429 /* fxrstor, ldmxcsr, xrstor. */
4430 if (i
.tm
.base_opcode
== 0xfae
4431 && (i
.tm
.extension_opcode
== 1
4432 || i
.tm
.extension_opcode
== 2
4433 || i
.tm
.extension_opcode
== 5))
4436 /* lgdt, lidt, lmsw. */
4437 if (i
.tm
.base_opcode
== 0xf01
4438 && (i
.tm
.extension_opcode
== 2
4439 || i
.tm
.extension_opcode
== 3
4440 || i
.tm
.extension_opcode
== 6))
4444 if (i
.tm
.base_opcode
== 0xfc7
4445 && i
.tm
.extension_opcode
== 6)
4448 /* Check for x87 instructions. */
4449 if (i
.tm
.base_opcode
>= 0xd8 && i
.tm
.base_opcode
<= 0xdf)
4451 /* Skip fst, fstp, fstenv, fstcw. */
4452 if (i
.tm
.base_opcode
== 0xd9
4453 && (i
.tm
.extension_opcode
== 2
4454 || i
.tm
.extension_opcode
== 3
4455 || i
.tm
.extension_opcode
== 6
4456 || i
.tm
.extension_opcode
== 7))
4459 /* Skip fisttp, fist, fistp, fstp. */
4460 if (i
.tm
.base_opcode
== 0xdb
4461 && (i
.tm
.extension_opcode
== 1
4462 || i
.tm
.extension_opcode
== 2
4463 || i
.tm
.extension_opcode
== 3
4464 || i
.tm
.extension_opcode
== 7))
4467 /* Skip fisttp, fst, fstp, fsave, fstsw. */
4468 if (i
.tm
.base_opcode
== 0xdd
4469 && (i
.tm
.extension_opcode
== 1
4470 || i
.tm
.extension_opcode
== 2
4471 || i
.tm
.extension_opcode
== 3
4472 || i
.tm
.extension_opcode
== 6
4473 || i
.tm
.extension_opcode
== 7))
4476 /* Skip fisttp, fist, fistp, fbstp, fistp. */
4477 if (i
.tm
.base_opcode
== 0xdf
4478 && (i
.tm
.extension_opcode
== 1
4479 || i
.tm
.extension_opcode
== 2
4480 || i
.tm
.extension_opcode
== 3
4481 || i
.tm
.extension_opcode
== 6
4482 || i
.tm
.extension_opcode
== 7))
4489 dest
= i
.operands
- 1;
4491 /* Check fake imm8 operand and 3 source operands. */
4492 if ((i
.tm
.opcode_modifier
.immext
4493 || i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
)
4494 && i
.types
[dest
].bitfield
.imm8
)
4497 /* add, or, adc, sbb, and, sub, xor, cmp, test, xchg, xadd */
4499 && (base_opcode
== 0x1
4500 || base_opcode
== 0x9
4501 || base_opcode
== 0x11
4502 || base_opcode
== 0x19
4503 || base_opcode
== 0x21
4504 || base_opcode
== 0x29
4505 || base_opcode
== 0x31
4506 || base_opcode
== 0x39
4507 || (i
.tm
.base_opcode
>= 0x84 && i
.tm
.base_opcode
<= 0x87)
4508 || base_opcode
== 0xfc1))
4511 /* Check for load instruction. */
4512 return (i
.types
[dest
].bitfield
.class != ClassNone
4513 || i
.types
[dest
].bitfield
.instance
== Accum
);
4516 /* Output lfence, 0xfaee8, after instruction. */
4519 insert_lfence_after (void)
4521 if (lfence_after_load
&& load_insn_p ())
4523 /* There are also two REP string instructions that require
4524 special treatment. Specifically, the compare string (CMPS)
4525 and scan string (SCAS) instructions set EFLAGS in a manner
4526 that depends on the data being compared/scanned. When used
4527 with a REP prefix, the number of iterations may therefore
4528 vary depending on this data. If the data is a program secret
4529 chosen by the adversary using an LVI method,
4530 then this data-dependent behavior may leak some aspect
4532 if (((i
.tm
.base_opcode
| 0x1) == 0xa7
4533 || (i
.tm
.base_opcode
| 0x1) == 0xaf)
4534 && i
.prefix
[REP_PREFIX
])
4536 as_warn (_("`%s` changes flags which would affect control flow behavior"),
4539 char *p
= frag_more (3);
4546 /* Output lfence, 0xfaee8, before instruction. */
4549 insert_lfence_before (void)
4553 if (is_any_vex_encoding (&i
.tm
))
4556 if (i
.tm
.base_opcode
== 0xff
4557 && (i
.tm
.extension_opcode
== 2 || i
.tm
.extension_opcode
== 4))
4559 /* Insert lfence before indirect branch if needed. */
4561 if (lfence_before_indirect_branch
== lfence_branch_none
)
4564 if (i
.operands
!= 1)
4567 if (i
.reg_operands
== 1)
4569 /* Indirect branch via register. Don't insert lfence with
4570 -mlfence-after-load=yes. */
4571 if (lfence_after_load
4572 || lfence_before_indirect_branch
== lfence_branch_memory
)
4575 else if (i
.mem_operands
== 1
4576 && lfence_before_indirect_branch
!= lfence_branch_register
)
4578 as_warn (_("indirect `%s` with memory operand should be avoided"),
4585 if (last_insn
.kind
!= last_insn_other
4586 && last_insn
.seg
== now_seg
)
4588 as_warn_where (last_insn
.file
, last_insn
.line
,
4589 _("`%s` skips -mlfence-before-indirect-branch on `%s`"),
4590 last_insn
.name
, i
.tm
.name
);
4601 /* Output or/not/shl and lfence before near ret. */
4602 if (lfence_before_ret
!= lfence_before_ret_none
4603 && (i
.tm
.base_opcode
== 0xc2
4604 || i
.tm
.base_opcode
== 0xc3))
4606 if (last_insn
.kind
!= last_insn_other
4607 && last_insn
.seg
== now_seg
)
4609 as_warn_where (last_insn
.file
, last_insn
.line
,
4610 _("`%s` skips -mlfence-before-ret on `%s`"),
4611 last_insn
.name
, i
.tm
.name
);
4615 /* Near ret ingore operand size override under CPU64. */
4616 char prefix
= flag_code
== CODE_64BIT
4618 : i
.prefix
[DATA_PREFIX
] ? 0x66 : 0x0;
4620 if (lfence_before_ret
== lfence_before_ret_not
)
4622 /* not: 0xf71424, may add prefix
4623 for operand size override or 64-bit code. */
4624 p
= frag_more ((prefix
? 2 : 0) + 6 + 3);
4638 p
= frag_more ((prefix
? 1 : 0) + 4 + 3);
4641 if (lfence_before_ret
== lfence_before_ret_or
)
4643 /* or: 0x830c2400, may add prefix
4644 for operand size override or 64-bit code. */
4650 /* shl: 0xc1242400, may add prefix
4651 for operand size override or 64-bit code. */
4666 /* This is the guts of the machine-dependent assembler. LINE points to a
4667 machine dependent instruction. This function is supposed to emit
4668 the frags/bytes it assembles to. */
4671 md_assemble (char *line
)
4674 char mnemonic
[MAX_MNEM_SIZE
], mnem_suffix
;
4675 const insn_template
*t
;
4677 /* Initialize globals. */
4678 memset (&i
, '\0', sizeof (i
));
4679 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4680 i
.reloc
[j
] = NO_RELOC
;
4681 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
4682 memset (im_expressions
, '\0', sizeof (im_expressions
));
4683 save_stack_p
= save_stack
;
4685 /* First parse an instruction mnemonic & call i386_operand for the operands.
4686 We assume that the scrubber has arranged it so that line[0] is the valid
4687 start of a (possibly prefixed) mnemonic. */
4689 line
= parse_insn (line
, mnemonic
);
4692 mnem_suffix
= i
.suffix
;
4694 line
= parse_operands (line
, mnemonic
);
4696 xfree (i
.memop1_string
);
4697 i
.memop1_string
= NULL
;
4701 /* Now we've parsed the mnemonic into a set of templates, and have the
4702 operands at hand. */
4704 /* All Intel opcodes have reversed operands except for "bound", "enter",
4705 "monitor*", "mwait*", "tpause", and "umwait". We also don't reverse
4706 intersegment "jmp" and "call" instructions with 2 immediate operands so
4707 that the immediate segment precedes the offset, as it does when in AT&T
4711 && (strcmp (mnemonic
, "bound") != 0)
4712 && (strcmp (mnemonic
, "invlpga") != 0)
4713 && (strncmp (mnemonic
, "monitor", 7) != 0)
4714 && (strncmp (mnemonic
, "mwait", 5) != 0)
4715 && (strcmp (mnemonic
, "tpause") != 0)
4716 && (strcmp (mnemonic
, "umwait") != 0)
4717 && !(operand_type_check (i
.types
[0], imm
)
4718 && operand_type_check (i
.types
[1], imm
)))
4721 /* The order of the immediates should be reversed
4722 for 2 immediates extrq and insertq instructions */
4723 if (i
.imm_operands
== 2
4724 && (strcmp (mnemonic
, "extrq") == 0
4725 || strcmp (mnemonic
, "insertq") == 0))
4726 swap_2_operands (0, 1);
4731 /* Don't optimize displacement for movabs since it only takes 64bit
4734 && i
.disp_encoding
!= disp_encoding_32bit
4735 && (flag_code
!= CODE_64BIT
4736 || strcmp (mnemonic
, "movabs") != 0))
4739 /* Next, we find a template that matches the given insn,
4740 making sure the overlap of the given operands types is consistent
4741 with the template operand types. */
4743 if (!(t
= match_template (mnem_suffix
)))
4746 if (sse_check
!= check_none
4747 && !i
.tm
.opcode_modifier
.noavx
4748 && !i
.tm
.cpu_flags
.bitfield
.cpuavx
4749 && !i
.tm
.cpu_flags
.bitfield
.cpuavx512f
4750 && (i
.tm
.cpu_flags
.bitfield
.cpusse
4751 || i
.tm
.cpu_flags
.bitfield
.cpusse2
4752 || i
.tm
.cpu_flags
.bitfield
.cpusse3
4753 || i
.tm
.cpu_flags
.bitfield
.cpussse3
4754 || i
.tm
.cpu_flags
.bitfield
.cpusse4_1
4755 || i
.tm
.cpu_flags
.bitfield
.cpusse4_2
4756 || i
.tm
.cpu_flags
.bitfield
.cpupclmul
4757 || i
.tm
.cpu_flags
.bitfield
.cpuaes
4758 || i
.tm
.cpu_flags
.bitfield
.cpusha
4759 || i
.tm
.cpu_flags
.bitfield
.cpugfni
))
4761 (sse_check
== check_warning
4763 : as_bad
) (_("SSE instruction `%s' is used"), i
.tm
.name
);
4766 if (i
.tm
.opcode_modifier
.fwait
)
4767 if (!add_prefix (FWAIT_OPCODE
))
4770 /* Check if REP prefix is OK. */
4771 if (i
.rep_prefix
&& !i
.tm
.opcode_modifier
.repprefixok
)
4773 as_bad (_("invalid instruction `%s' after `%s'"),
4774 i
.tm
.name
, i
.rep_prefix
);
4778 /* Check for lock without a lockable instruction. Destination operand
4779 must be memory unless it is xchg (0x86). */
4780 if (i
.prefix
[LOCK_PREFIX
]
4781 && (!i
.tm
.opcode_modifier
.islockable
4782 || i
.mem_operands
== 0
4783 || (i
.tm
.base_opcode
!= 0x86
4784 && !(i
.flags
[i
.operands
- 1] & Operand_Mem
))))
4786 as_bad (_("expecting lockable instruction after `lock'"));
4790 /* Check for data size prefix on VEX/XOP/EVEX encoded insns. */
4791 if (i
.prefix
[DATA_PREFIX
] && is_any_vex_encoding (&i
.tm
))
4793 as_bad (_("data size prefix invalid with `%s'"), i
.tm
.name
);
4797 /* Check if HLE prefix is OK. */
4798 if (i
.hle_prefix
&& !check_hle ())
4801 /* Check BND prefix. */
4802 if (i
.bnd_prefix
&& !i
.tm
.opcode_modifier
.bndprefixok
)
4803 as_bad (_("expecting valid branch instruction after `bnd'"));
4805 /* Check NOTRACK prefix. */
4806 if (i
.notrack_prefix
&& !i
.tm
.opcode_modifier
.notrackprefixok
)
4807 as_bad (_("expecting indirect branch instruction after `notrack'"));
4809 if (i
.tm
.cpu_flags
.bitfield
.cpumpx
)
4811 if (flag_code
== CODE_64BIT
&& i
.prefix
[ADDR_PREFIX
])
4812 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
4813 else if (flag_code
!= CODE_16BIT
4814 ? i
.prefix
[ADDR_PREFIX
]
4815 : i
.mem_operands
&& !i
.prefix
[ADDR_PREFIX
])
4816 as_bad (_("16-bit address isn't allowed in MPX instructions"));
4819 /* Insert BND prefix. */
4820 if (add_bnd_prefix
&& i
.tm
.opcode_modifier
.bndprefixok
)
4822 if (!i
.prefix
[BND_PREFIX
])
4823 add_prefix (BND_PREFIX_OPCODE
);
4824 else if (i
.prefix
[BND_PREFIX
] != BND_PREFIX_OPCODE
)
4826 as_warn (_("replacing `rep'/`repe' prefix by `bnd'"));
4827 i
.prefix
[BND_PREFIX
] = BND_PREFIX_OPCODE
;
4831 /* Check string instruction segment overrides. */
4832 if (i
.tm
.opcode_modifier
.isstring
>= IS_STRING_ES_OP0
)
4834 gas_assert (i
.mem_operands
);
4835 if (!check_string ())
4837 i
.disp_operands
= 0;
4840 if (optimize
&& !i
.no_optimize
&& i
.tm
.opcode_modifier
.optimize
)
4841 optimize_encoding ();
4843 if (!process_suffix ())
4846 /* Update operand types. */
4847 for (j
= 0; j
< i
.operands
; j
++)
4848 i
.types
[j
] = operand_type_and (i
.types
[j
], i
.tm
.operand_types
[j
]);
4850 /* Make still unresolved immediate matches conform to size of immediate
4851 given in i.suffix. */
4852 if (!finalize_imm ())
4855 if (i
.types
[0].bitfield
.imm1
)
4856 i
.imm_operands
= 0; /* kludge for shift insns. */
4858 /* We only need to check those implicit registers for instructions
4859 with 3 operands or less. */
4860 if (i
.operands
<= 3)
4861 for (j
= 0; j
< i
.operands
; j
++)
4862 if (i
.types
[j
].bitfield
.instance
!= InstanceNone
4863 && !i
.types
[j
].bitfield
.xmmword
)
4866 /* ImmExt should be processed after SSE2AVX. */
4867 if (!i
.tm
.opcode_modifier
.sse2avx
4868 && i
.tm
.opcode_modifier
.immext
)
4871 /* For insns with operands there are more diddles to do to the opcode. */
4874 if (!process_operands ())
4877 else if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
4879 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
4880 as_warn (_("translating to `%sp'"), i
.tm
.name
);
4883 if (is_any_vex_encoding (&i
.tm
))
4885 if (!cpu_arch_flags
.bitfield
.cpui286
)
4887 as_bad (_("instruction `%s' isn't supported outside of protected mode."),
4892 if (i
.tm
.opcode_modifier
.vex
)
4893 build_vex_prefix (t
);
4895 build_evex_prefix ();
4898 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
4899 instructions may define INT_OPCODE as well, so avoid this corner
4900 case for those instructions that use MODRM. */
4901 if (i
.tm
.base_opcode
== INT_OPCODE
4902 && !i
.tm
.opcode_modifier
.modrm
4903 && i
.op
[0].imms
->X_add_number
== 3)
4905 i
.tm
.base_opcode
= INT3_OPCODE
;
4909 if ((i
.tm
.opcode_modifier
.jump
== JUMP
4910 || i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
4911 || i
.tm
.opcode_modifier
.jump
== JUMP_DWORD
)
4912 && i
.op
[0].disps
->X_op
== O_constant
)
4914 /* Convert "jmp constant" (and "call constant") to a jump (call) to
4915 the absolute address given by the constant. Since ix86 jumps and
4916 calls are pc relative, we need to generate a reloc. */
4917 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
4918 i
.op
[0].disps
->X_op
= O_symbol
;
4921 /* For 8 bit registers we need an empty rex prefix. Also if the
4922 instruction already has a prefix, we need to convert old
4923 registers to new ones. */
4925 if ((i
.types
[0].bitfield
.class == Reg
&& i
.types
[0].bitfield
.byte
4926 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
4927 || (i
.types
[1].bitfield
.class == Reg
&& i
.types
[1].bitfield
.byte
4928 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
4929 || (((i
.types
[0].bitfield
.class == Reg
&& i
.types
[0].bitfield
.byte
)
4930 || (i
.types
[1].bitfield
.class == Reg
&& i
.types
[1].bitfield
.byte
))
4935 i
.rex
|= REX_OPCODE
;
4936 for (x
= 0; x
< 2; x
++)
4938 /* Look for 8 bit operand that uses old registers. */
4939 if (i
.types
[x
].bitfield
.class == Reg
&& i
.types
[x
].bitfield
.byte
4940 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
4942 gas_assert (!(i
.op
[x
].regs
->reg_flags
& RegRex
));
4943 /* In case it is "hi" register, give up. */
4944 if (i
.op
[x
].regs
->reg_num
> 3)
4945 as_bad (_("can't encode register '%s%s' in an "
4946 "instruction requiring REX prefix."),
4947 register_prefix
, i
.op
[x
].regs
->reg_name
);
4949 /* Otherwise it is equivalent to the extended register.
4950 Since the encoding doesn't change this is merely
4951 cosmetic cleanup for debug output. */
4953 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
4958 if (i
.rex
== 0 && i
.rex_encoding
)
4960 /* Check if we can add a REX_OPCODE byte. Look for 8 bit operand
4961 that uses legacy register. If it is "hi" register, don't add
4962 the REX_OPCODE byte. */
4964 for (x
= 0; x
< 2; x
++)
4965 if (i
.types
[x
].bitfield
.class == Reg
4966 && i
.types
[x
].bitfield
.byte
4967 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0
4968 && i
.op
[x
].regs
->reg_num
> 3)
4970 gas_assert (!(i
.op
[x
].regs
->reg_flags
& RegRex
));
4971 i
.rex_encoding
= FALSE
;
4980 add_prefix (REX_OPCODE
| i
.rex
);
4982 insert_lfence_before ();
4984 /* We are ready to output the insn. */
4987 insert_lfence_after ();
4989 last_insn
.seg
= now_seg
;
4991 if (i
.tm
.opcode_modifier
.isprefix
)
4993 last_insn
.kind
= last_insn_prefix
;
4994 last_insn
.name
= i
.tm
.name
;
4995 last_insn
.file
= as_where (&last_insn
.line
);
4998 last_insn
.kind
= last_insn_other
;
5002 parse_insn (char *line
, char *mnemonic
)
5005 char *token_start
= l
;
5008 const insn_template
*t
;
5014 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
5019 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
5021 as_bad (_("no such instruction: `%s'"), token_start
);
5026 if (!is_space_char (*l
)
5027 && *l
!= END_OF_INSN
5029 || (*l
!= PREFIX_SEPARATOR
5032 as_bad (_("invalid character %s in mnemonic"),
5033 output_invalid (*l
));
5036 if (token_start
== l
)
5038 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
5039 as_bad (_("expecting prefix; got nothing"));
5041 as_bad (_("expecting mnemonic; got nothing"));
5045 /* Look up instruction (or prefix) via hash table. */
5046 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
5048 if (*l
!= END_OF_INSN
5049 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
5050 && current_templates
5051 && current_templates
->start
->opcode_modifier
.isprefix
)
5053 if (!cpu_flags_check_cpu64 (current_templates
->start
->cpu_flags
))
5055 as_bad ((flag_code
!= CODE_64BIT
5056 ? _("`%s' is only supported in 64-bit mode")
5057 : _("`%s' is not supported in 64-bit mode")),
5058 current_templates
->start
->name
);
5061 /* If we are in 16-bit mode, do not allow addr16 or data16.
5062 Similarly, in 32-bit mode, do not allow addr32 or data32. */
5063 if ((current_templates
->start
->opcode_modifier
.size
== SIZE16
5064 || current_templates
->start
->opcode_modifier
.size
== SIZE32
)
5065 && flag_code
!= CODE_64BIT
5066 && ((current_templates
->start
->opcode_modifier
.size
== SIZE32
)
5067 ^ (flag_code
== CODE_16BIT
)))
5069 as_bad (_("redundant %s prefix"),
5070 current_templates
->start
->name
);
5073 if (current_templates
->start
->opcode_length
== 0)
5075 /* Handle pseudo prefixes. */
5076 switch (current_templates
->start
->base_opcode
)
5080 i
.disp_encoding
= disp_encoding_8bit
;
5084 i
.disp_encoding
= disp_encoding_32bit
;
5088 i
.dir_encoding
= dir_encoding_load
;
5092 i
.dir_encoding
= dir_encoding_store
;
5096 i
.vec_encoding
= vex_encoding_vex
;
5100 i
.vec_encoding
= vex_encoding_vex3
;
5104 i
.vec_encoding
= vex_encoding_evex
;
5108 i
.rex_encoding
= TRUE
;
5112 i
.no_optimize
= TRUE
;
5120 /* Add prefix, checking for repeated prefixes. */
5121 switch (add_prefix (current_templates
->start
->base_opcode
))
5126 if (current_templates
->start
->cpu_flags
.bitfield
.cpuibt
)
5127 i
.notrack_prefix
= current_templates
->start
->name
;
5130 if (current_templates
->start
->cpu_flags
.bitfield
.cpuhle
)
5131 i
.hle_prefix
= current_templates
->start
->name
;
5132 else if (current_templates
->start
->cpu_flags
.bitfield
.cpumpx
)
5133 i
.bnd_prefix
= current_templates
->start
->name
;
5135 i
.rep_prefix
= current_templates
->start
->name
;
5141 /* Skip past PREFIX_SEPARATOR and reset token_start. */
5148 if (!current_templates
)
5150 /* Deprecated functionality (new code should use pseudo-prefixes instead):
5151 Check if we should swap operand or force 32bit displacement in
5153 if (mnem_p
- 2 == dot_p
&& dot_p
[1] == 's')
5154 i
.dir_encoding
= dir_encoding_swap
;
5155 else if (mnem_p
- 3 == dot_p
5158 i
.disp_encoding
= disp_encoding_8bit
;
5159 else if (mnem_p
- 4 == dot_p
5163 i
.disp_encoding
= disp_encoding_32bit
;
5168 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
5171 if (!current_templates
)
5174 if (mnem_p
> mnemonic
)
5176 /* See if we can get a match by trimming off a suffix. */
5179 case WORD_MNEM_SUFFIX
:
5180 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
5181 i
.suffix
= SHORT_MNEM_SUFFIX
;
5184 case BYTE_MNEM_SUFFIX
:
5185 case QWORD_MNEM_SUFFIX
:
5186 i
.suffix
= mnem_p
[-1];
5188 current_templates
= (const templates
*) hash_find (op_hash
,
5191 case SHORT_MNEM_SUFFIX
:
5192 case LONG_MNEM_SUFFIX
:
5195 i
.suffix
= mnem_p
[-1];
5197 current_templates
= (const templates
*) hash_find (op_hash
,
5206 if (intel_float_operand (mnemonic
) == 1)
5207 i
.suffix
= SHORT_MNEM_SUFFIX
;
5209 i
.suffix
= LONG_MNEM_SUFFIX
;
5211 current_templates
= (const templates
*) hash_find (op_hash
,
5218 if (!current_templates
)
5220 as_bad (_("no such instruction: `%s'"), token_start
);
5225 if (current_templates
->start
->opcode_modifier
.jump
== JUMP
5226 || current_templates
->start
->opcode_modifier
.jump
== JUMP_BYTE
)
5228 /* Check for a branch hint. We allow ",pt" and ",pn" for
5229 predict taken and predict not taken respectively.
5230 I'm not sure that branch hints actually do anything on loop
5231 and jcxz insns (JumpByte) for current Pentium4 chips. They
5232 may work in the future and it doesn't hurt to accept them
5234 if (l
[0] == ',' && l
[1] == 'p')
5238 if (!add_prefix (DS_PREFIX_OPCODE
))
5242 else if (l
[2] == 'n')
5244 if (!add_prefix (CS_PREFIX_OPCODE
))
5250 /* Any other comma loses. */
5253 as_bad (_("invalid character %s in mnemonic"),
5254 output_invalid (*l
));
5258 /* Check if instruction is supported on specified architecture. */
5260 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
5262 supported
|= cpu_flags_match (t
);
5263 if (supported
== CPU_FLAGS_PERFECT_MATCH
)
5265 if (!cpu_arch_flags
.bitfield
.cpui386
&& (flag_code
!= CODE_16BIT
))
5266 as_warn (_("use .code16 to ensure correct addressing mode"));
5272 if (!(supported
& CPU_FLAGS_64BIT_MATCH
))
5273 as_bad (flag_code
== CODE_64BIT
5274 ? _("`%s' is not supported in 64-bit mode")
5275 : _("`%s' is only supported in 64-bit mode"),
5276 current_templates
->start
->name
);
5278 as_bad (_("`%s' is not supported on `%s%s'"),
5279 current_templates
->start
->name
,
5280 cpu_arch_name
? cpu_arch_name
: default_arch
,
5281 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
5287 parse_operands (char *l
, const char *mnemonic
)
5291 /* 1 if operand is pending after ','. */
5292 unsigned int expecting_operand
= 0;
5294 /* Non-zero if operand parens not balanced. */
5295 unsigned int paren_not_balanced
;
5297 while (*l
!= END_OF_INSN
)
5299 /* Skip optional white space before operand. */
5300 if (is_space_char (*l
))
5302 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
&& *l
!= '"')
5304 as_bad (_("invalid character %s before operand %d"),
5305 output_invalid (*l
),
5309 token_start
= l
; /* After white space. */
5310 paren_not_balanced
= 0;
5311 while (paren_not_balanced
|| *l
!= ',')
5313 if (*l
== END_OF_INSN
)
5315 if (paren_not_balanced
)
5318 as_bad (_("unbalanced parenthesis in operand %d."),
5321 as_bad (_("unbalanced brackets in operand %d."),
5326 break; /* we are done */
5328 else if (!is_operand_char (*l
) && !is_space_char (*l
) && *l
!= '"')
5330 as_bad (_("invalid character %s in operand %d"),
5331 output_invalid (*l
),
5338 ++paren_not_balanced
;
5340 --paren_not_balanced
;
5345 ++paren_not_balanced
;
5347 --paren_not_balanced
;
5351 if (l
!= token_start
)
5352 { /* Yes, we've read in another operand. */
5353 unsigned int operand_ok
;
5354 this_operand
= i
.operands
++;
5355 if (i
.operands
> MAX_OPERANDS
)
5357 as_bad (_("spurious operands; (%d operands/instruction max)"),
5361 i
.types
[this_operand
].bitfield
.unspecified
= 1;
5362 /* Now parse operand adding info to 'i' as we go along. */
5363 END_STRING_AND_SAVE (l
);
5365 if (i
.mem_operands
> 1)
5367 as_bad (_("too many memory references for `%s'"),
5374 i386_intel_operand (token_start
,
5375 intel_float_operand (mnemonic
));
5377 operand_ok
= i386_att_operand (token_start
);
5379 RESTORE_END_STRING (l
);
5385 if (expecting_operand
)
5387 expecting_operand_after_comma
:
5388 as_bad (_("expecting operand after ','; got nothing"));
5393 as_bad (_("expecting operand before ','; got nothing"));
5398 /* Now *l must be either ',' or END_OF_INSN. */
5401 if (*++l
== END_OF_INSN
)
5403 /* Just skip it, if it's \n complain. */
5404 goto expecting_operand_after_comma
;
5406 expecting_operand
= 1;
5413 swap_2_operands (int xchg1
, int xchg2
)
5415 union i386_op temp_op
;
5416 i386_operand_type temp_type
;
5417 unsigned int temp_flags
;
5418 enum bfd_reloc_code_real temp_reloc
;
5420 temp_type
= i
.types
[xchg2
];
5421 i
.types
[xchg2
] = i
.types
[xchg1
];
5422 i
.types
[xchg1
] = temp_type
;
5424 temp_flags
= i
.flags
[xchg2
];
5425 i
.flags
[xchg2
] = i
.flags
[xchg1
];
5426 i
.flags
[xchg1
] = temp_flags
;
5428 temp_op
= i
.op
[xchg2
];
5429 i
.op
[xchg2
] = i
.op
[xchg1
];
5430 i
.op
[xchg1
] = temp_op
;
5432 temp_reloc
= i
.reloc
[xchg2
];
5433 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
5434 i
.reloc
[xchg1
] = temp_reloc
;
5438 if (i
.mask
->operand
== xchg1
)
5439 i
.mask
->operand
= xchg2
;
5440 else if (i
.mask
->operand
== xchg2
)
5441 i
.mask
->operand
= xchg1
;
5445 if (i
.broadcast
->operand
== xchg1
)
5446 i
.broadcast
->operand
= xchg2
;
5447 else if (i
.broadcast
->operand
== xchg2
)
5448 i
.broadcast
->operand
= xchg1
;
5452 if (i
.rounding
->operand
== xchg1
)
5453 i
.rounding
->operand
= xchg2
;
5454 else if (i
.rounding
->operand
== xchg2
)
5455 i
.rounding
->operand
= xchg1
;
5460 swap_operands (void)
5466 swap_2_operands (1, i
.operands
- 2);
5470 swap_2_operands (0, i
.operands
- 1);
5476 if (i
.mem_operands
== 2)
5478 const seg_entry
*temp_seg
;
5479 temp_seg
= i
.seg
[0];
5480 i
.seg
[0] = i
.seg
[1];
5481 i
.seg
[1] = temp_seg
;
5485 /* Try to ensure constant immediates are represented in the smallest
5490 char guess_suffix
= 0;
5494 guess_suffix
= i
.suffix
;
5495 else if (i
.reg_operands
)
5497 /* Figure out a suffix from the last register operand specified.
5498 We can't do this properly yet, i.e. excluding special register
5499 instances, but the following works for instructions with
5500 immediates. In any case, we can't set i.suffix yet. */
5501 for (op
= i
.operands
; --op
>= 0;)
5502 if (i
.types
[op
].bitfield
.class != Reg
)
5504 else if (i
.types
[op
].bitfield
.byte
)
5506 guess_suffix
= BYTE_MNEM_SUFFIX
;
5509 else if (i
.types
[op
].bitfield
.word
)
5511 guess_suffix
= WORD_MNEM_SUFFIX
;
5514 else if (i
.types
[op
].bitfield
.dword
)
5516 guess_suffix
= LONG_MNEM_SUFFIX
;
5519 else if (i
.types
[op
].bitfield
.qword
)
5521 guess_suffix
= QWORD_MNEM_SUFFIX
;
5525 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
5526 guess_suffix
= WORD_MNEM_SUFFIX
;
5528 for (op
= i
.operands
; --op
>= 0;)
5529 if (operand_type_check (i
.types
[op
], imm
))
5531 switch (i
.op
[op
].imms
->X_op
)
5534 /* If a suffix is given, this operand may be shortened. */
5535 switch (guess_suffix
)
5537 case LONG_MNEM_SUFFIX
:
5538 i
.types
[op
].bitfield
.imm32
= 1;
5539 i
.types
[op
].bitfield
.imm64
= 1;
5541 case WORD_MNEM_SUFFIX
:
5542 i
.types
[op
].bitfield
.imm16
= 1;
5543 i
.types
[op
].bitfield
.imm32
= 1;
5544 i
.types
[op
].bitfield
.imm32s
= 1;
5545 i
.types
[op
].bitfield
.imm64
= 1;
5547 case BYTE_MNEM_SUFFIX
:
5548 i
.types
[op
].bitfield
.imm8
= 1;
5549 i
.types
[op
].bitfield
.imm8s
= 1;
5550 i
.types
[op
].bitfield
.imm16
= 1;
5551 i
.types
[op
].bitfield
.imm32
= 1;
5552 i
.types
[op
].bitfield
.imm32s
= 1;
5553 i
.types
[op
].bitfield
.imm64
= 1;
5557 /* If this operand is at most 16 bits, convert it
5558 to a signed 16 bit number before trying to see
5559 whether it will fit in an even smaller size.
5560 This allows a 16-bit operand such as $0xffe0 to
5561 be recognised as within Imm8S range. */
5562 if ((i
.types
[op
].bitfield
.imm16
)
5563 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
5565 i
.op
[op
].imms
->X_add_number
=
5566 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
5569 /* Store 32-bit immediate in 64-bit for 64-bit BFD. */
5570 if ((i
.types
[op
].bitfield
.imm32
)
5571 && ((i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1))
5574 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
5575 ^ ((offsetT
) 1 << 31))
5576 - ((offsetT
) 1 << 31));
5580 = operand_type_or (i
.types
[op
],
5581 smallest_imm_type (i
.op
[op
].imms
->X_add_number
));
5583 /* We must avoid matching of Imm32 templates when 64bit
5584 only immediate is available. */
5585 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
5586 i
.types
[op
].bitfield
.imm32
= 0;
5593 /* Symbols and expressions. */
5595 /* Convert symbolic operand to proper sizes for matching, but don't
5596 prevent matching a set of insns that only supports sizes other
5597 than those matching the insn suffix. */
5599 i386_operand_type mask
, allowed
;
5600 const insn_template
*t
;
5602 operand_type_set (&mask
, 0);
5603 operand_type_set (&allowed
, 0);
5605 for (t
= current_templates
->start
;
5606 t
< current_templates
->end
;
5609 allowed
= operand_type_or (allowed
, t
->operand_types
[op
]);
5610 allowed
= operand_type_and (allowed
, anyimm
);
5612 switch (guess_suffix
)
5614 case QWORD_MNEM_SUFFIX
:
5615 mask
.bitfield
.imm64
= 1;
5616 mask
.bitfield
.imm32s
= 1;
5618 case LONG_MNEM_SUFFIX
:
5619 mask
.bitfield
.imm32
= 1;
5621 case WORD_MNEM_SUFFIX
:
5622 mask
.bitfield
.imm16
= 1;
5624 case BYTE_MNEM_SUFFIX
:
5625 mask
.bitfield
.imm8
= 1;
5630 allowed
= operand_type_and (mask
, allowed
);
5631 if (!operand_type_all_zero (&allowed
))
5632 i
.types
[op
] = operand_type_and (i
.types
[op
], mask
);
5639 /* Try to use the smallest displacement type too. */
5641 optimize_disp (void)
5645 for (op
= i
.operands
; --op
>= 0;)
5646 if (operand_type_check (i
.types
[op
], disp
))
5648 if (i
.op
[op
].disps
->X_op
== O_constant
)
5650 offsetT op_disp
= i
.op
[op
].disps
->X_add_number
;
5652 if (i
.types
[op
].bitfield
.disp16
5653 && (op_disp
& ~(offsetT
) 0xffff) == 0)
5655 /* If this operand is at most 16 bits, convert
5656 to a signed 16 bit number and don't use 64bit
5658 op_disp
= (((op_disp
& 0xffff) ^ 0x8000) - 0x8000);
5659 i
.types
[op
].bitfield
.disp64
= 0;
5662 /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */
5663 if (i
.types
[op
].bitfield
.disp32
5664 && (op_disp
& ~(((offsetT
) 2 << 31) - 1)) == 0)
5666 /* If this operand is at most 32 bits, convert
5667 to a signed 32 bit number and don't use 64bit
5669 op_disp
&= (((offsetT
) 2 << 31) - 1);
5670 op_disp
= (op_disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
5671 i
.types
[op
].bitfield
.disp64
= 0;
5674 if (!op_disp
&& i
.types
[op
].bitfield
.baseindex
)
5676 i
.types
[op
].bitfield
.disp8
= 0;
5677 i
.types
[op
].bitfield
.disp16
= 0;
5678 i
.types
[op
].bitfield
.disp32
= 0;
5679 i
.types
[op
].bitfield
.disp32s
= 0;
5680 i
.types
[op
].bitfield
.disp64
= 0;
5684 else if (flag_code
== CODE_64BIT
)
5686 if (fits_in_signed_long (op_disp
))
5688 i
.types
[op
].bitfield
.disp64
= 0;
5689 i
.types
[op
].bitfield
.disp32s
= 1;
5691 if (i
.prefix
[ADDR_PREFIX
]
5692 && fits_in_unsigned_long (op_disp
))
5693 i
.types
[op
].bitfield
.disp32
= 1;
5695 if ((i
.types
[op
].bitfield
.disp32
5696 || i
.types
[op
].bitfield
.disp32s
5697 || i
.types
[op
].bitfield
.disp16
)
5698 && fits_in_disp8 (op_disp
))
5699 i
.types
[op
].bitfield
.disp8
= 1;
5701 else if (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
5702 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
)
5704 fix_new_exp (frag_now
, frag_more (0) - frag_now
->fr_literal
, 0,
5705 i
.op
[op
].disps
, 0, i
.reloc
[op
]);
5706 i
.types
[op
].bitfield
.disp8
= 0;
5707 i
.types
[op
].bitfield
.disp16
= 0;
5708 i
.types
[op
].bitfield
.disp32
= 0;
5709 i
.types
[op
].bitfield
.disp32s
= 0;
5710 i
.types
[op
].bitfield
.disp64
= 0;
5713 /* We only support 64bit displacement on constants. */
5714 i
.types
[op
].bitfield
.disp64
= 0;
5718 /* Return 1 if there is a match in broadcast bytes between operand
5719 GIVEN and instruction template T. */
5722 match_broadcast_size (const insn_template
*t
, unsigned int given
)
5724 return ((t
->opcode_modifier
.broadcast
== BYTE_BROADCAST
5725 && i
.types
[given
].bitfield
.byte
)
5726 || (t
->opcode_modifier
.broadcast
== WORD_BROADCAST
5727 && i
.types
[given
].bitfield
.word
)
5728 || (t
->opcode_modifier
.broadcast
== DWORD_BROADCAST
5729 && i
.types
[given
].bitfield
.dword
)
5730 || (t
->opcode_modifier
.broadcast
== QWORD_BROADCAST
5731 && i
.types
[given
].bitfield
.qword
));
5734 /* Check if operands are valid for the instruction. */
5737 check_VecOperands (const insn_template
*t
)
5742 /* Templates allowing for ZMMword as well as YMMword and/or XMMword for
5743 any one operand are implicity requiring AVX512VL support if the actual
5744 operand size is YMMword or XMMword. Since this function runs after
5745 template matching, there's no need to check for YMMword/XMMword in
5747 cpu
= cpu_flags_and (t
->cpu_flags
, avx512
);
5748 if (!cpu_flags_all_zero (&cpu
)
5749 && !t
->cpu_flags
.bitfield
.cpuavx512vl
5750 && !cpu_arch_flags
.bitfield
.cpuavx512vl
)
5752 for (op
= 0; op
< t
->operands
; ++op
)
5754 if (t
->operand_types
[op
].bitfield
.zmmword
5755 && (i
.types
[op
].bitfield
.ymmword
5756 || i
.types
[op
].bitfield
.xmmword
))
5758 i
.error
= unsupported
;
5764 /* Without VSIB byte, we can't have a vector register for index. */
5765 if (!t
->opcode_modifier
.vecsib
5767 && (i
.index_reg
->reg_type
.bitfield
.xmmword
5768 || i
.index_reg
->reg_type
.bitfield
.ymmword
5769 || i
.index_reg
->reg_type
.bitfield
.zmmword
))
5771 i
.error
= unsupported_vector_index_register
;
5775 /* Check if default mask is allowed. */
5776 if (t
->opcode_modifier
.nodefmask
5777 && (!i
.mask
|| i
.mask
->mask
->reg_num
== 0))
5779 i
.error
= no_default_mask
;
5783 /* For VSIB byte, we need a vector register for index, and all vector
5784 registers must be distinct. */
5785 if (t
->opcode_modifier
.vecsib
)
5788 || !((t
->opcode_modifier
.vecsib
== VecSIB128
5789 && i
.index_reg
->reg_type
.bitfield
.xmmword
)
5790 || (t
->opcode_modifier
.vecsib
== VecSIB256
5791 && i
.index_reg
->reg_type
.bitfield
.ymmword
)
5792 || (t
->opcode_modifier
.vecsib
== VecSIB512
5793 && i
.index_reg
->reg_type
.bitfield
.zmmword
)))
5795 i
.error
= invalid_vsib_address
;
5799 gas_assert (i
.reg_operands
== 2 || i
.mask
);
5800 if (i
.reg_operands
== 2 && !i
.mask
)
5802 gas_assert (i
.types
[0].bitfield
.class == RegSIMD
);
5803 gas_assert (i
.types
[0].bitfield
.xmmword
5804 || i
.types
[0].bitfield
.ymmword
);
5805 gas_assert (i
.types
[2].bitfield
.class == RegSIMD
);
5806 gas_assert (i
.types
[2].bitfield
.xmmword
5807 || i
.types
[2].bitfield
.ymmword
);
5808 if (operand_check
== check_none
)
5810 if (register_number (i
.op
[0].regs
)
5811 != register_number (i
.index_reg
)
5812 && register_number (i
.op
[2].regs
)
5813 != register_number (i
.index_reg
)
5814 && register_number (i
.op
[0].regs
)
5815 != register_number (i
.op
[2].regs
))
5817 if (operand_check
== check_error
)
5819 i
.error
= invalid_vector_register_set
;
5822 as_warn (_("mask, index, and destination registers should be distinct"));
5824 else if (i
.reg_operands
== 1 && i
.mask
)
5826 if (i
.types
[1].bitfield
.class == RegSIMD
5827 && (i
.types
[1].bitfield
.xmmword
5828 || i
.types
[1].bitfield
.ymmword
5829 || i
.types
[1].bitfield
.zmmword
)
5830 && (register_number (i
.op
[1].regs
)
5831 == register_number (i
.index_reg
)))
5833 if (operand_check
== check_error
)
5835 i
.error
= invalid_vector_register_set
;
5838 if (operand_check
!= check_none
)
5839 as_warn (_("index and destination registers should be distinct"));
5844 /* Check if broadcast is supported by the instruction and is applied
5845 to the memory operand. */
5848 i386_operand_type type
, overlap
;
5850 /* Check if specified broadcast is supported in this instruction,
5851 and its broadcast bytes match the memory operand. */
5852 op
= i
.broadcast
->operand
;
5853 if (!t
->opcode_modifier
.broadcast
5854 || !(i
.flags
[op
] & Operand_Mem
)
5855 || (!i
.types
[op
].bitfield
.unspecified
5856 && !match_broadcast_size (t
, op
)))
5859 i
.error
= unsupported_broadcast
;
5863 i
.broadcast
->bytes
= ((1 << (t
->opcode_modifier
.broadcast
- 1))
5864 * i
.broadcast
->type
);
5865 operand_type_set (&type
, 0);
5866 switch (i
.broadcast
->bytes
)
5869 type
.bitfield
.word
= 1;
5872 type
.bitfield
.dword
= 1;
5875 type
.bitfield
.qword
= 1;
5878 type
.bitfield
.xmmword
= 1;
5881 type
.bitfield
.ymmword
= 1;
5884 type
.bitfield
.zmmword
= 1;
5890 overlap
= operand_type_and (type
, t
->operand_types
[op
]);
5891 if (t
->operand_types
[op
].bitfield
.class == RegSIMD
5892 && t
->operand_types
[op
].bitfield
.byte
5893 + t
->operand_types
[op
].bitfield
.word
5894 + t
->operand_types
[op
].bitfield
.dword
5895 + t
->operand_types
[op
].bitfield
.qword
> 1)
5897 overlap
.bitfield
.xmmword
= 0;
5898 overlap
.bitfield
.ymmword
= 0;
5899 overlap
.bitfield
.zmmword
= 0;
5901 if (operand_type_all_zero (&overlap
))
5904 if (t
->opcode_modifier
.checkregsize
)
5908 type
.bitfield
.baseindex
= 1;
5909 for (j
= 0; j
< i
.operands
; ++j
)
5912 && !operand_type_register_match(i
.types
[j
],
5913 t
->operand_types
[j
],
5915 t
->operand_types
[op
]))
5920 /* If broadcast is supported in this instruction, we need to check if
5921 operand of one-element size isn't specified without broadcast. */
5922 else if (t
->opcode_modifier
.broadcast
&& i
.mem_operands
)
5924 /* Find memory operand. */
5925 for (op
= 0; op
< i
.operands
; op
++)
5926 if (i
.flags
[op
] & Operand_Mem
)
5928 gas_assert (op
< i
.operands
);
5929 /* Check size of the memory operand. */
5930 if (match_broadcast_size (t
, op
))
5932 i
.error
= broadcast_needed
;
5937 op
= MAX_OPERANDS
- 1; /* Avoid uninitialized variable warning. */
5939 /* Check if requested masking is supported. */
5942 switch (t
->opcode_modifier
.masking
)
5946 case MERGING_MASKING
:
5947 if (i
.mask
->zeroing
)
5950 i
.error
= unsupported_masking
;
5954 case DYNAMIC_MASKING
:
5955 /* Memory destinations allow only merging masking. */
5956 if (i
.mask
->zeroing
&& i
.mem_operands
)
5958 /* Find memory operand. */
5959 for (op
= 0; op
< i
.operands
; op
++)
5960 if (i
.flags
[op
] & Operand_Mem
)
5962 gas_assert (op
< i
.operands
);
5963 if (op
== i
.operands
- 1)
5965 i
.error
= unsupported_masking
;
5975 /* Check if masking is applied to dest operand. */
5976 if (i
.mask
&& (i
.mask
->operand
!= (int) (i
.operands
- 1)))
5978 i
.error
= mask_not_on_destination
;
5985 if (!t
->opcode_modifier
.sae
5986 || (i
.rounding
->type
!= saeonly
&& !t
->opcode_modifier
.staticrounding
))
5988 i
.error
= unsupported_rc_sae
;
5991 /* If the instruction has several immediate operands and one of
5992 them is rounding, the rounding operand should be the last
5993 immediate operand. */
5994 if (i
.imm_operands
> 1
5995 && i
.rounding
->operand
!= (int) (i
.imm_operands
- 1))
5997 i
.error
= rc_sae_operand_not_last_imm
;
6002 /* Check the special Imm4 cases; must be the first operand. */
6003 if (t
->cpu_flags
.bitfield
.cpuxop
&& t
->operands
== 5)
6005 if (i
.op
[0].imms
->X_op
!= O_constant
6006 || !fits_in_imm4 (i
.op
[0].imms
->X_add_number
))
6012 /* Turn off Imm<N> so that update_imm won't complain. */
6013 operand_type_set (&i
.types
[0], 0);
6016 /* Check vector Disp8 operand. */
6017 if (t
->opcode_modifier
.disp8memshift
6018 && i
.disp_encoding
!= disp_encoding_32bit
)
6021 i
.memshift
= t
->opcode_modifier
.broadcast
- 1;
6022 else if (t
->opcode_modifier
.disp8memshift
!= DISP8_SHIFT_VL
)
6023 i
.memshift
= t
->opcode_modifier
.disp8memshift
;
6026 const i386_operand_type
*type
= NULL
;
6029 for (op
= 0; op
< i
.operands
; op
++)
6030 if (i
.flags
[op
] & Operand_Mem
)
6032 if (t
->opcode_modifier
.evex
== EVEXLIG
)
6033 i
.memshift
= 2 + (i
.suffix
== QWORD_MNEM_SUFFIX
);
6034 else if (t
->operand_types
[op
].bitfield
.xmmword
6035 + t
->operand_types
[op
].bitfield
.ymmword
6036 + t
->operand_types
[op
].bitfield
.zmmword
<= 1)
6037 type
= &t
->operand_types
[op
];
6038 else if (!i
.types
[op
].bitfield
.unspecified
)
6039 type
= &i
.types
[op
];
6041 else if (i
.types
[op
].bitfield
.class == RegSIMD
6042 && t
->opcode_modifier
.evex
!= EVEXLIG
)
6044 if (i
.types
[op
].bitfield
.zmmword
)
6046 else if (i
.types
[op
].bitfield
.ymmword
&& i
.memshift
< 5)
6048 else if (i
.types
[op
].bitfield
.xmmword
&& i
.memshift
< 4)
6054 if (type
->bitfield
.zmmword
)
6056 else if (type
->bitfield
.ymmword
)
6058 else if (type
->bitfield
.xmmword
)
6062 /* For the check in fits_in_disp8(). */
6063 if (i
.memshift
== 0)
6067 for (op
= 0; op
< i
.operands
; op
++)
6068 if (operand_type_check (i
.types
[op
], disp
)
6069 && i
.op
[op
].disps
->X_op
== O_constant
)
6071 if (fits_in_disp8 (i
.op
[op
].disps
->X_add_number
))
6073 i
.types
[op
].bitfield
.disp8
= 1;
6076 i
.types
[op
].bitfield
.disp8
= 0;
6085 /* Check if encoding requirements are met by the instruction. */
6088 VEX_check_encoding (const insn_template
*t
)
6090 if (i
.vec_encoding
== vex_encoding_error
)
6092 i
.error
= unsupported
;
6096 if (i
.vec_encoding
== vex_encoding_evex
)
6098 /* This instruction must be encoded with EVEX prefix. */
6099 if (!is_evex_encoding (t
))
6101 i
.error
= unsupported
;
6107 if (!t
->opcode_modifier
.vex
)
6109 /* This instruction template doesn't have VEX prefix. */
6110 if (i
.vec_encoding
!= vex_encoding_default
)
6112 i
.error
= unsupported
;
6121 static const insn_template
*
6122 match_template (char mnem_suffix
)
6124 /* Points to template once we've found it. */
6125 const insn_template
*t
;
6126 i386_operand_type overlap0
, overlap1
, overlap2
, overlap3
;
6127 i386_operand_type overlap4
;
6128 unsigned int found_reverse_match
;
6129 i386_opcode_modifier suffix_check
;
6130 i386_operand_type operand_types
[MAX_OPERANDS
];
6131 int addr_prefix_disp
;
6132 unsigned int j
, size_match
, check_register
;
6133 enum i386_error specific_error
= 0;
6135 #if MAX_OPERANDS != 5
6136 # error "MAX_OPERANDS must be 5."
6139 found_reverse_match
= 0;
6140 addr_prefix_disp
= -1;
6142 /* Prepare for mnemonic suffix check. */
6143 memset (&suffix_check
, 0, sizeof (suffix_check
));
6144 switch (mnem_suffix
)
6146 case BYTE_MNEM_SUFFIX
:
6147 suffix_check
.no_bsuf
= 1;
6149 case WORD_MNEM_SUFFIX
:
6150 suffix_check
.no_wsuf
= 1;
6152 case SHORT_MNEM_SUFFIX
:
6153 suffix_check
.no_ssuf
= 1;
6155 case LONG_MNEM_SUFFIX
:
6156 suffix_check
.no_lsuf
= 1;
6158 case QWORD_MNEM_SUFFIX
:
6159 suffix_check
.no_qsuf
= 1;
6162 /* NB: In Intel syntax, normally we can check for memory operand
6163 size when there is no mnemonic suffix. But jmp and call have
6164 2 different encodings with Dword memory operand size, one with
6165 No_ldSuf and the other without. i.suffix is set to
6166 LONG_DOUBLE_MNEM_SUFFIX to skip the one with No_ldSuf. */
6167 if (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
)
6168 suffix_check
.no_ldsuf
= 1;
6171 /* Must have right number of operands. */
6172 i
.error
= number_of_operands_mismatch
;
6174 for (t
= current_templates
->start
; t
< current_templates
->end
; t
++)
6176 addr_prefix_disp
= -1;
6177 found_reverse_match
= 0;
6179 if (i
.operands
!= t
->operands
)
6182 /* Check processor support. */
6183 i
.error
= unsupported
;
6184 if (cpu_flags_match (t
) != CPU_FLAGS_PERFECT_MATCH
)
6187 /* Check AT&T mnemonic. */
6188 i
.error
= unsupported_with_intel_mnemonic
;
6189 if (intel_mnemonic
&& t
->opcode_modifier
.attmnemonic
)
6192 /* Check AT&T/Intel syntax. */
6193 i
.error
= unsupported_syntax
;
6194 if ((intel_syntax
&& t
->opcode_modifier
.attsyntax
)
6195 || (!intel_syntax
&& t
->opcode_modifier
.intelsyntax
))
6198 /* Check Intel64/AMD64 ISA. */
6202 /* Default: Don't accept Intel64. */
6203 if (t
->opcode_modifier
.isa64
== INTEL64
)
6207 /* -mamd64: Don't accept Intel64 and Intel64 only. */
6208 if (t
->opcode_modifier
.isa64
>= INTEL64
)
6212 /* -mintel64: Don't accept AMD64. */
6213 if (t
->opcode_modifier
.isa64
== AMD64
&& flag_code
== CODE_64BIT
)
6218 /* Check the suffix. */
6219 i
.error
= invalid_instruction_suffix
;
6220 if ((t
->opcode_modifier
.no_bsuf
&& suffix_check
.no_bsuf
)
6221 || (t
->opcode_modifier
.no_wsuf
&& suffix_check
.no_wsuf
)
6222 || (t
->opcode_modifier
.no_lsuf
&& suffix_check
.no_lsuf
)
6223 || (t
->opcode_modifier
.no_ssuf
&& suffix_check
.no_ssuf
)
6224 || (t
->opcode_modifier
.no_qsuf
&& suffix_check
.no_qsuf
)
6225 || (t
->opcode_modifier
.no_ldsuf
&& suffix_check
.no_ldsuf
))
6228 size_match
= operand_size_match (t
);
6232 /* This is intentionally not
6234 if (i.jumpabsolute != (t->opcode_modifier.jump == JUMP_ABSOLUTE))
6236 as the case of a missing * on the operand is accepted (perhaps with
6237 a warning, issued further down). */
6238 if (i
.jumpabsolute
&& t
->opcode_modifier
.jump
!= JUMP_ABSOLUTE
)
6240 i
.error
= operand_type_mismatch
;
6244 for (j
= 0; j
< MAX_OPERANDS
; j
++)
6245 operand_types
[j
] = t
->operand_types
[j
];
6247 /* In general, don't allow
6248 - 64-bit operands outside of 64-bit mode,
6249 - 32-bit operands on pre-386. */
6250 j
= i
.imm_operands
+ (t
->operands
> i
.imm_operands
+ 1);
6251 if (((i
.suffix
== QWORD_MNEM_SUFFIX
6252 && flag_code
!= CODE_64BIT
6253 && (t
->base_opcode
!= 0x0fc7
6254 || t
->extension_opcode
!= 1 /* cmpxchg8b */))
6255 || (i
.suffix
== LONG_MNEM_SUFFIX
6256 && !cpu_arch_flags
.bitfield
.cpui386
))
6258 ? (t
->opcode_modifier
.mnemonicsize
!= IGNORESIZE
6259 && !intel_float_operand (t
->name
))
6260 : intel_float_operand (t
->name
) != 2)
6261 && (t
->operands
== i
.imm_operands
6262 || (operand_types
[i
.imm_operands
].bitfield
.class != RegMMX
6263 && operand_types
[i
.imm_operands
].bitfield
.class != RegSIMD
6264 && operand_types
[i
.imm_operands
].bitfield
.class != RegMask
)
6265 || (operand_types
[j
].bitfield
.class != RegMMX
6266 && operand_types
[j
].bitfield
.class != RegSIMD
6267 && operand_types
[j
].bitfield
.class != RegMask
))
6268 && !t
->opcode_modifier
.vecsib
)
6271 /* Do not verify operands when there are none. */
6274 if (VEX_check_encoding (t
))
6276 specific_error
= i
.error
;
6280 /* We've found a match; break out of loop. */
6284 if (!t
->opcode_modifier
.jump
6285 || t
->opcode_modifier
.jump
== JUMP_ABSOLUTE
)
6287 /* There should be only one Disp operand. */
6288 for (j
= 0; j
< MAX_OPERANDS
; j
++)
6289 if (operand_type_check (operand_types
[j
], disp
))
6291 if (j
< MAX_OPERANDS
)
6293 bfd_boolean override
= (i
.prefix
[ADDR_PREFIX
] != 0);
6295 addr_prefix_disp
= j
;
6297 /* Address size prefix will turn Disp64/Disp32S/Disp32/Disp16
6298 operand into Disp32/Disp32/Disp16/Disp32 operand. */
6302 override
= !override
;
6305 if (operand_types
[j
].bitfield
.disp32
6306 && operand_types
[j
].bitfield
.disp16
)
6308 operand_types
[j
].bitfield
.disp16
= override
;
6309 operand_types
[j
].bitfield
.disp32
= !override
;
6311 operand_types
[j
].bitfield
.disp32s
= 0;
6312 operand_types
[j
].bitfield
.disp64
= 0;
6316 if (operand_types
[j
].bitfield
.disp32s
6317 || operand_types
[j
].bitfield
.disp64
)
6319 operand_types
[j
].bitfield
.disp64
&= !override
;
6320 operand_types
[j
].bitfield
.disp32s
&= !override
;
6321 operand_types
[j
].bitfield
.disp32
= override
;
6323 operand_types
[j
].bitfield
.disp16
= 0;
6329 /* Force 0x8b encoding for "mov foo@GOT, %eax". */
6330 if (i
.reloc
[0] == BFD_RELOC_386_GOT32
&& t
->base_opcode
== 0xa0)
6333 /* We check register size if needed. */
6334 if (t
->opcode_modifier
.checkregsize
)
6336 check_register
= (1 << t
->operands
) - 1;
6338 check_register
&= ~(1 << i
.broadcast
->operand
);
6343 overlap0
= operand_type_and (i
.types
[0], operand_types
[0]);
6344 switch (t
->operands
)
6347 if (!operand_type_match (overlap0
, i
.types
[0]))
6351 /* xchg %eax, %eax is a special case. It is an alias for nop
6352 only in 32bit mode and we can use opcode 0x90. In 64bit
6353 mode, we can't use 0x90 for xchg %eax, %eax since it should
6354 zero-extend %eax to %rax. */
6355 if (flag_code
== CODE_64BIT
6356 && t
->base_opcode
== 0x90
6357 && i
.types
[0].bitfield
.instance
== Accum
6358 && i
.types
[0].bitfield
.dword
6359 && i
.types
[1].bitfield
.instance
== Accum
6360 && i
.types
[1].bitfield
.dword
)
6362 /* xrelease mov %eax, <disp> is another special case. It must not
6363 match the accumulator-only encoding of mov. */
6364 if (flag_code
!= CODE_64BIT
6366 && t
->base_opcode
== 0xa0
6367 && i
.types
[0].bitfield
.instance
== Accum
6368 && (i
.flags
[1] & Operand_Mem
))
6373 if (!(size_match
& MATCH_STRAIGHT
))
6375 /* Reverse direction of operands if swapping is possible in the first
6376 place (operands need to be symmetric) and
6377 - the load form is requested, and the template is a store form,
6378 - the store form is requested, and the template is a load form,
6379 - the non-default (swapped) form is requested. */
6380 overlap1
= operand_type_and (operand_types
[0], operand_types
[1]);
6381 if (t
->opcode_modifier
.d
&& i
.reg_operands
== i
.operands
6382 && !operand_type_all_zero (&overlap1
))
6383 switch (i
.dir_encoding
)
6385 case dir_encoding_load
:
6386 if (operand_type_check (operand_types
[i
.operands
- 1], anymem
)
6387 || t
->opcode_modifier
.regmem
)
6391 case dir_encoding_store
:
6392 if (!operand_type_check (operand_types
[i
.operands
- 1], anymem
)
6393 && !t
->opcode_modifier
.regmem
)
6397 case dir_encoding_swap
:
6400 case dir_encoding_default
:
6403 /* If we want store form, we skip the current load. */
6404 if ((i
.dir_encoding
== dir_encoding_store
6405 || i
.dir_encoding
== dir_encoding_swap
)
6406 && i
.mem_operands
== 0
6407 && t
->opcode_modifier
.load
)
6412 overlap1
= operand_type_and (i
.types
[1], operand_types
[1]);
6413 if (!operand_type_match (overlap0
, i
.types
[0])
6414 || !operand_type_match (overlap1
, i
.types
[1])
6415 || ((check_register
& 3) == 3
6416 && !operand_type_register_match (i
.types
[0],
6421 /* Check if other direction is valid ... */
6422 if (!t
->opcode_modifier
.d
)
6426 if (!(size_match
& MATCH_REVERSE
))
6428 /* Try reversing direction of operands. */
6429 overlap0
= operand_type_and (i
.types
[0], operand_types
[i
.operands
- 1]);
6430 overlap1
= operand_type_and (i
.types
[i
.operands
- 1], operand_types
[0]);
6431 if (!operand_type_match (overlap0
, i
.types
[0])
6432 || !operand_type_match (overlap1
, i
.types
[i
.operands
- 1])
6434 && !operand_type_register_match (i
.types
[0],
6435 operand_types
[i
.operands
- 1],
6436 i
.types
[i
.operands
- 1],
6439 /* Does not match either direction. */
6442 /* found_reverse_match holds which of D or FloatR
6444 if (!t
->opcode_modifier
.d
)
6445 found_reverse_match
= 0;
6446 else if (operand_types
[0].bitfield
.tbyte
)
6447 found_reverse_match
= Opcode_FloatD
;
6448 else if (operand_types
[0].bitfield
.xmmword
6449 || operand_types
[i
.operands
- 1].bitfield
.xmmword
6450 || operand_types
[0].bitfield
.class == RegMMX
6451 || operand_types
[i
.operands
- 1].bitfield
.class == RegMMX
6452 || is_any_vex_encoding(t
))
6453 found_reverse_match
= (t
->base_opcode
& 0xee) != 0x6e
6454 ? Opcode_SIMD_FloatD
: Opcode_SIMD_IntD
;
6456 found_reverse_match
= Opcode_D
;
6457 if (t
->opcode_modifier
.floatr
)
6458 found_reverse_match
|= Opcode_FloatR
;
6462 /* Found a forward 2 operand match here. */
6463 switch (t
->operands
)
6466 overlap4
= operand_type_and (i
.types
[4],
6470 overlap3
= operand_type_and (i
.types
[3],
6474 overlap2
= operand_type_and (i
.types
[2],
6479 switch (t
->operands
)
6482 if (!operand_type_match (overlap4
, i
.types
[4])
6483 || !operand_type_register_match (i
.types
[3],
6490 if (!operand_type_match (overlap3
, i
.types
[3])
6491 || ((check_register
& 0xa) == 0xa
6492 && !operand_type_register_match (i
.types
[1],
6496 || ((check_register
& 0xc) == 0xc
6497 && !operand_type_register_match (i
.types
[2],
6504 /* Here we make use of the fact that there are no
6505 reverse match 3 operand instructions. */
6506 if (!operand_type_match (overlap2
, i
.types
[2])
6507 || ((check_register
& 5) == 5
6508 && !operand_type_register_match (i
.types
[0],
6512 || ((check_register
& 6) == 6
6513 && !operand_type_register_match (i
.types
[1],
6521 /* Found either forward/reverse 2, 3 or 4 operand match here:
6522 slip through to break. */
6525 /* Check if vector operands are valid. */
6526 if (check_VecOperands (t
))
6528 specific_error
= i
.error
;
6532 /* Check if VEX/EVEX encoding requirements can be satisfied. */
6533 if (VEX_check_encoding (t
))
6535 specific_error
= i
.error
;
6539 /* We've found a match; break out of loop. */
6543 if (t
== current_templates
->end
)
6545 /* We found no match. */
6546 const char *err_msg
;
6547 switch (specific_error
? specific_error
: i
.error
)
6551 case operand_size_mismatch
:
6552 err_msg
= _("operand size mismatch");
6554 case operand_type_mismatch
:
6555 err_msg
= _("operand type mismatch");
6557 case register_type_mismatch
:
6558 err_msg
= _("register type mismatch");
6560 case number_of_operands_mismatch
:
6561 err_msg
= _("number of operands mismatch");
6563 case invalid_instruction_suffix
:
6564 err_msg
= _("invalid instruction suffix");
6567 err_msg
= _("constant doesn't fit in 4 bits");
6569 case unsupported_with_intel_mnemonic
:
6570 err_msg
= _("unsupported with Intel mnemonic");
6572 case unsupported_syntax
:
6573 err_msg
= _("unsupported syntax");
6576 as_bad (_("unsupported instruction `%s'"),
6577 current_templates
->start
->name
);
6579 case invalid_vsib_address
:
6580 err_msg
= _("invalid VSIB address");
6582 case invalid_vector_register_set
:
6583 err_msg
= _("mask, index, and destination registers must be distinct");
6585 case unsupported_vector_index_register
:
6586 err_msg
= _("unsupported vector index register");
6588 case unsupported_broadcast
:
6589 err_msg
= _("unsupported broadcast");
6591 case broadcast_needed
:
6592 err_msg
= _("broadcast is needed for operand of such type");
6594 case unsupported_masking
:
6595 err_msg
= _("unsupported masking");
6597 case mask_not_on_destination
:
6598 err_msg
= _("mask not on destination operand");
6600 case no_default_mask
:
6601 err_msg
= _("default mask isn't allowed");
6603 case unsupported_rc_sae
:
6604 err_msg
= _("unsupported static rounding/sae");
6606 case rc_sae_operand_not_last_imm
:
6608 err_msg
= _("RC/SAE operand must precede immediate operands");
6610 err_msg
= _("RC/SAE operand must follow immediate operands");
6612 case invalid_register_operand
:
6613 err_msg
= _("invalid register operand");
6616 as_bad (_("%s for `%s'"), err_msg
,
6617 current_templates
->start
->name
);
6621 if (!quiet_warnings
)
6624 && (i
.jumpabsolute
!= (t
->opcode_modifier
.jump
== JUMP_ABSOLUTE
)))
6625 as_warn (_("indirect %s without `*'"), t
->name
);
6627 if (t
->opcode_modifier
.isprefix
6628 && t
->opcode_modifier
.mnemonicsize
== IGNORESIZE
)
6630 /* Warn them that a data or address size prefix doesn't
6631 affect assembly of the next line of code. */
6632 as_warn (_("stand-alone `%s' prefix"), t
->name
);
6636 /* Copy the template we found. */
6639 if (addr_prefix_disp
!= -1)
6640 i
.tm
.operand_types
[addr_prefix_disp
]
6641 = operand_types
[addr_prefix_disp
];
6643 if (found_reverse_match
)
6645 /* If we found a reverse match we must alter the opcode direction
6646 bit and clear/flip the regmem modifier one. found_reverse_match
6647 holds bits to change (different for int & float insns). */
6649 i
.tm
.base_opcode
^= found_reverse_match
;
6651 i
.tm
.operand_types
[0] = operand_types
[i
.operands
- 1];
6652 i
.tm
.operand_types
[i
.operands
- 1] = operand_types
[0];
6654 /* Certain SIMD insns have their load forms specified in the opcode
6655 table, and hence we need to _set_ RegMem instead of clearing it.
6656 We need to avoid setting the bit though on insns like KMOVW. */
6657 i
.tm
.opcode_modifier
.regmem
6658 = i
.tm
.opcode_modifier
.modrm
&& i
.tm
.opcode_modifier
.d
6659 && i
.tm
.operands
> 2U - i
.tm
.opcode_modifier
.sse2avx
6660 && !i
.tm
.opcode_modifier
.regmem
;
6669 unsigned int es_op
= i
.tm
.opcode_modifier
.isstring
- IS_STRING_ES_OP0
;
6670 unsigned int op
= i
.tm
.operand_types
[0].bitfield
.baseindex
? es_op
: 0;
6672 if (i
.seg
[op
] != NULL
&& i
.seg
[op
] != &es
)
6674 as_bad (_("`%s' operand %u must use `%ses' segment"),
6676 intel_syntax
? i
.tm
.operands
- es_op
: es_op
+ 1,
6681 /* There's only ever one segment override allowed per instruction.
6682 This instruction possibly has a legal segment override on the
6683 second operand, so copy the segment to where non-string
6684 instructions store it, allowing common code. */
6685 i
.seg
[op
] = i
.seg
[1];
6691 process_suffix (void)
6693 /* If matched instruction specifies an explicit instruction mnemonic
6695 if (i
.tm
.opcode_modifier
.size
== SIZE16
)
6696 i
.suffix
= WORD_MNEM_SUFFIX
;
6697 else if (i
.tm
.opcode_modifier
.size
== SIZE32
)
6698 i
.suffix
= LONG_MNEM_SUFFIX
;
6699 else if (i
.tm
.opcode_modifier
.size
== SIZE64
)
6700 i
.suffix
= QWORD_MNEM_SUFFIX
;
6701 else if (i
.reg_operands
6702 && (i
.operands
> 1 || i
.types
[0].bitfield
.class == Reg
)
6703 && !i
.tm
.opcode_modifier
.addrprefixopreg
)
6705 unsigned int numop
= i
.operands
;
6707 /* movsx/movzx want only their source operand considered here, for the
6708 ambiguity checking below. The suffix will be replaced afterwards
6709 to represent the destination (register). */
6710 if (((i
.tm
.base_opcode
| 8) == 0xfbe && i
.tm
.opcode_modifier
.w
)
6711 || (i
.tm
.base_opcode
== 0x63 && i
.tm
.cpu_flags
.bitfield
.cpu64
))
6714 /* crc32 needs REX.W set regardless of suffix / source operand size. */
6715 if (i
.tm
.base_opcode
== 0xf20f38f0
6716 && i
.tm
.operand_types
[1].bitfield
.qword
)
6719 /* If there's no instruction mnemonic suffix we try to invent one
6720 based on GPR operands. */
6723 /* We take i.suffix from the last register operand specified,
6724 Destination register type is more significant than source
6725 register type. crc32 in SSE4.2 prefers source register
6727 unsigned int op
= i
.tm
.base_opcode
!= 0xf20f38f0 ? i
.operands
: 1;
6730 if (i
.tm
.operand_types
[op
].bitfield
.instance
== InstanceNone
6731 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
6733 if (i
.types
[op
].bitfield
.class != Reg
)
6735 if (i
.types
[op
].bitfield
.byte
)
6736 i
.suffix
= BYTE_MNEM_SUFFIX
;
6737 else if (i
.types
[op
].bitfield
.word
)
6738 i
.suffix
= WORD_MNEM_SUFFIX
;
6739 else if (i
.types
[op
].bitfield
.dword
)
6740 i
.suffix
= LONG_MNEM_SUFFIX
;
6741 else if (i
.types
[op
].bitfield
.qword
)
6742 i
.suffix
= QWORD_MNEM_SUFFIX
;
6748 /* As an exception, movsx/movzx silently default to a byte source
6750 if ((i
.tm
.base_opcode
| 8) == 0xfbe && i
.tm
.opcode_modifier
.w
6751 && !i
.suffix
&& !intel_syntax
)
6752 i
.suffix
= BYTE_MNEM_SUFFIX
;
6754 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
6757 && i
.tm
.opcode_modifier
.mnemonicsize
== IGNORESIZE
6758 && i
.tm
.opcode_modifier
.no_bsuf
)
6760 else if (!check_byte_reg ())
6763 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
6766 && i
.tm
.opcode_modifier
.mnemonicsize
== IGNORESIZE
6767 && i
.tm
.opcode_modifier
.no_lsuf
6768 && !i
.tm
.opcode_modifier
.todword
6769 && !i
.tm
.opcode_modifier
.toqword
)
6771 else if (!check_long_reg ())
6774 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
6777 && i
.tm
.opcode_modifier
.mnemonicsize
== IGNORESIZE
6778 && i
.tm
.opcode_modifier
.no_qsuf
6779 && !i
.tm
.opcode_modifier
.todword
6780 && !i
.tm
.opcode_modifier
.toqword
)
6782 else if (!check_qword_reg ())
6785 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
6788 && i
.tm
.opcode_modifier
.mnemonicsize
== IGNORESIZE
6789 && i
.tm
.opcode_modifier
.no_wsuf
)
6791 else if (!check_word_reg ())
6794 else if (intel_syntax
6795 && i
.tm
.opcode_modifier
.mnemonicsize
== IGNORESIZE
)
6796 /* Do nothing if the instruction is going to ignore the prefix. */
6801 /* Undo the movsx/movzx change done above. */
6804 else if (i
.tm
.opcode_modifier
.mnemonicsize
== DEFAULTSIZE
6807 i
.suffix
= stackop_size
;
6808 if (stackop_size
== LONG_MNEM_SUFFIX
)
6810 /* stackop_size is set to LONG_MNEM_SUFFIX for the
6811 .code16gcc directive to support 16-bit mode with
6812 32-bit address. For IRET without a suffix, generate
6813 16-bit IRET (opcode 0xcf) to return from an interrupt
6815 if (i
.tm
.base_opcode
== 0xcf)
6817 i
.suffix
= WORD_MNEM_SUFFIX
;
6818 as_warn (_("generating 16-bit `iret' for .code16gcc directive"));
6820 /* Warn about changed behavior for segment register push/pop. */
6821 else if ((i
.tm
.base_opcode
| 1) == 0x07)
6822 as_warn (_("generating 32-bit `%s', unlike earlier gas versions"),
6827 && (i
.tm
.opcode_modifier
.jump
== JUMP_ABSOLUTE
6828 || i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
6829 || i
.tm
.opcode_modifier
.jump
== JUMP_INTERSEGMENT
6830 || (i
.tm
.base_opcode
== 0x0f01 /* [ls][gi]dt */
6831 && i
.tm
.extension_opcode
<= 3)))
6836 if (!i
.tm
.opcode_modifier
.no_qsuf
)
6838 if (i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
6839 || i
.tm
.opcode_modifier
.no_lsuf
)
6840 i
.suffix
= QWORD_MNEM_SUFFIX
;
6845 if (!i
.tm
.opcode_modifier
.no_lsuf
)
6846 i
.suffix
= LONG_MNEM_SUFFIX
;
6849 if (!i
.tm
.opcode_modifier
.no_wsuf
)
6850 i
.suffix
= WORD_MNEM_SUFFIX
;
6856 && (i
.tm
.opcode_modifier
.mnemonicsize
!= DEFAULTSIZE
6857 /* Also cover lret/retf/iret in 64-bit mode. */
6858 || (flag_code
== CODE_64BIT
6859 && !i
.tm
.opcode_modifier
.no_lsuf
6860 && !i
.tm
.opcode_modifier
.no_qsuf
))
6861 && i
.tm
.opcode_modifier
.mnemonicsize
!= IGNORESIZE
6862 /* Accept FLDENV et al without suffix. */
6863 && (i
.tm
.opcode_modifier
.no_ssuf
|| i
.tm
.opcode_modifier
.floatmf
))
6865 unsigned int suffixes
, evex
= 0;
6867 suffixes
= !i
.tm
.opcode_modifier
.no_bsuf
;
6868 if (!i
.tm
.opcode_modifier
.no_wsuf
)
6870 if (!i
.tm
.opcode_modifier
.no_lsuf
)
6872 if (!i
.tm
.opcode_modifier
.no_ldsuf
)
6874 if (!i
.tm
.opcode_modifier
.no_ssuf
)
6876 if (flag_code
== CODE_64BIT
&& !i
.tm
.opcode_modifier
.no_qsuf
)
6879 /* For [XYZ]MMWORD operands inspect operand sizes. While generally
6880 also suitable for AT&T syntax mode, it was requested that this be
6881 restricted to just Intel syntax. */
6882 if (intel_syntax
&& is_any_vex_encoding (&i
.tm
) && !i
.broadcast
)
6886 for (op
= 0; op
< i
.tm
.operands
; ++op
)
6888 if (is_evex_encoding (&i
.tm
)
6889 && !cpu_arch_flags
.bitfield
.cpuavx512vl
)
6891 if (i
.tm
.operand_types
[op
].bitfield
.ymmword
)
6892 i
.tm
.operand_types
[op
].bitfield
.xmmword
= 0;
6893 if (i
.tm
.operand_types
[op
].bitfield
.zmmword
)
6894 i
.tm
.operand_types
[op
].bitfield
.ymmword
= 0;
6895 if (!i
.tm
.opcode_modifier
.evex
6896 || i
.tm
.opcode_modifier
.evex
== EVEXDYN
)
6897 i
.tm
.opcode_modifier
.evex
= EVEX512
;
6900 if (i
.tm
.operand_types
[op
].bitfield
.xmmword
6901 + i
.tm
.operand_types
[op
].bitfield
.ymmword
6902 + i
.tm
.operand_types
[op
].bitfield
.zmmword
< 2)
6905 /* Any properly sized operand disambiguates the insn. */
6906 if (i
.types
[op
].bitfield
.xmmword
6907 || i
.types
[op
].bitfield
.ymmword
6908 || i
.types
[op
].bitfield
.zmmword
)
6910 suffixes
&= ~(7 << 6);
6915 if ((i
.flags
[op
] & Operand_Mem
)
6916 && i
.tm
.operand_types
[op
].bitfield
.unspecified
)
6918 if (i
.tm
.operand_types
[op
].bitfield
.xmmword
)
6920 if (i
.tm
.operand_types
[op
].bitfield
.ymmword
)
6922 if (i
.tm
.operand_types
[op
].bitfield
.zmmword
)
6924 if (is_evex_encoding (&i
.tm
))
6930 /* Are multiple suffixes / operand sizes allowed? */
6931 if (suffixes
& (suffixes
- 1))
6934 && (i
.tm
.opcode_modifier
.mnemonicsize
!= DEFAULTSIZE
6935 || operand_check
== check_error
))
6937 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
6940 if (operand_check
== check_error
)
6942 as_bad (_("no instruction mnemonic suffix given and "
6943 "no register operands; can't size `%s'"), i
.tm
.name
);
6946 if (operand_check
== check_warning
)
6947 as_warn (_("%s; using default for `%s'"),
6949 ? _("ambiguous operand size")
6950 : _("no instruction mnemonic suffix given and "
6951 "no register operands"),
6954 if (i
.tm
.opcode_modifier
.floatmf
)
6955 i
.suffix
= SHORT_MNEM_SUFFIX
;
6956 else if ((i
.tm
.base_opcode
| 8) == 0xfbe
6957 || (i
.tm
.base_opcode
== 0x63
6958 && i
.tm
.cpu_flags
.bitfield
.cpu64
))
6959 /* handled below */;
6961 i
.tm
.opcode_modifier
.evex
= evex
;
6962 else if (flag_code
== CODE_16BIT
)
6963 i
.suffix
= WORD_MNEM_SUFFIX
;
6964 else if (!i
.tm
.opcode_modifier
.no_lsuf
)
6965 i
.suffix
= LONG_MNEM_SUFFIX
;
6967 i
.suffix
= QWORD_MNEM_SUFFIX
;
6971 if ((i
.tm
.base_opcode
| 8) == 0xfbe
6972 || (i
.tm
.base_opcode
== 0x63 && i
.tm
.cpu_flags
.bitfield
.cpu64
))
6974 /* In Intel syntax, movsx/movzx must have a "suffix" (checked above).
6975 In AT&T syntax, if there is no suffix (warned about above), the default
6976 will be byte extension. */
6977 if (i
.tm
.opcode_modifier
.w
&& i
.suffix
&& i
.suffix
!= BYTE_MNEM_SUFFIX
)
6978 i
.tm
.base_opcode
|= 1;
6980 /* For further processing, the suffix should represent the destination
6981 (register). This is already the case when one was used with
6982 mov[sz][bw]*, but we need to replace it for mov[sz]x, or if there was
6983 no suffix to begin with. */
6984 if (i
.tm
.opcode_modifier
.w
|| i
.tm
.base_opcode
== 0x63 || !i
.suffix
)
6986 if (i
.types
[1].bitfield
.word
)
6987 i
.suffix
= WORD_MNEM_SUFFIX
;
6988 else if (i
.types
[1].bitfield
.qword
)
6989 i
.suffix
= QWORD_MNEM_SUFFIX
;
6991 i
.suffix
= LONG_MNEM_SUFFIX
;
6993 i
.tm
.opcode_modifier
.w
= 0;
6997 if (!i
.tm
.opcode_modifier
.modrm
&& i
.reg_operands
&& i
.tm
.operands
< 3)
6998 i
.short_form
= (i
.tm
.operand_types
[0].bitfield
.class == Reg
)
6999 != (i
.tm
.operand_types
[1].bitfield
.class == Reg
);
7001 /* Change the opcode based on the operand size given by i.suffix. */
7004 /* Size floating point instruction. */
7005 case LONG_MNEM_SUFFIX
:
7006 if (i
.tm
.opcode_modifier
.floatmf
)
7008 i
.tm
.base_opcode
^= 4;
7012 case WORD_MNEM_SUFFIX
:
7013 case QWORD_MNEM_SUFFIX
:
7014 /* It's not a byte, select word/dword operation. */
7015 if (i
.tm
.opcode_modifier
.w
)
7018 i
.tm
.base_opcode
|= 8;
7020 i
.tm
.base_opcode
|= 1;
7023 case SHORT_MNEM_SUFFIX
:
7024 /* Now select between word & dword operations via the operand
7025 size prefix, except for instructions that will ignore this
7027 if (i
.suffix
!= QWORD_MNEM_SUFFIX
7028 && i
.tm
.opcode_modifier
.mnemonicsize
!= IGNORESIZE
7029 && !i
.tm
.opcode_modifier
.floatmf
7030 && !is_any_vex_encoding (&i
.tm
)
7031 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
7032 || (flag_code
== CODE_64BIT
7033 && i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
)))
7035 unsigned int prefix
= DATA_PREFIX_OPCODE
;
7037 if (i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
) /* jcxz, loop */
7038 prefix
= ADDR_PREFIX_OPCODE
;
7040 if (!add_prefix (prefix
))
7044 /* Set mode64 for an operand. */
7045 if (i
.suffix
== QWORD_MNEM_SUFFIX
7046 && flag_code
== CODE_64BIT
7047 && !i
.tm
.opcode_modifier
.norex64
7048 && !i
.tm
.opcode_modifier
.vexw
7049 /* Special case for xchg %rax,%rax. It is NOP and doesn't
7051 && ! (i
.operands
== 2
7052 && i
.tm
.base_opcode
== 0x90
7053 && i
.tm
.extension_opcode
== None
7054 && i
.types
[0].bitfield
.instance
== Accum
7055 && i
.types
[0].bitfield
.qword
7056 && i
.types
[1].bitfield
.instance
== Accum
7057 && i
.types
[1].bitfield
.qword
))
7063 if (i
.tm
.opcode_modifier
.addrprefixopreg
)
7065 gas_assert (!i
.suffix
);
7066 gas_assert (i
.reg_operands
);
7068 if (i
.tm
.operand_types
[0].bitfield
.instance
== Accum
7071 /* The address size override prefix changes the size of the
7073 if (flag_code
== CODE_64BIT
7074 && i
.op
[0].regs
->reg_type
.bitfield
.word
)
7076 as_bad (_("16-bit addressing unavailable for `%s'"),
7081 if ((flag_code
== CODE_32BIT
7082 ? i
.op
[0].regs
->reg_type
.bitfield
.word
7083 : i
.op
[0].regs
->reg_type
.bitfield
.dword
)
7084 && !add_prefix (ADDR_PREFIX_OPCODE
))
7089 /* Check invalid register operand when the address size override
7090 prefix changes the size of register operands. */
7092 enum { need_word
, need_dword
, need_qword
} need
;
7094 if (flag_code
== CODE_32BIT
)
7095 need
= i
.prefix
[ADDR_PREFIX
] ? need_word
: need_dword
;
7096 else if (i
.prefix
[ADDR_PREFIX
])
7099 need
= flag_code
== CODE_64BIT
? need_qword
: need_word
;
7101 for (op
= 0; op
< i
.operands
; op
++)
7103 if (i
.types
[op
].bitfield
.class != Reg
)
7109 if (i
.op
[op
].regs
->reg_type
.bitfield
.word
)
7113 if (i
.op
[op
].regs
->reg_type
.bitfield
.dword
)
7117 if (i
.op
[op
].regs
->reg_type
.bitfield
.qword
)
7122 as_bad (_("invalid register operand size for `%s'"),
7133 check_byte_reg (void)
7137 for (op
= i
.operands
; --op
>= 0;)
7139 /* Skip non-register operands. */
7140 if (i
.types
[op
].bitfield
.class != Reg
)
7143 /* If this is an eight bit register, it's OK. If it's the 16 or
7144 32 bit version of an eight bit register, we will just use the
7145 low portion, and that's OK too. */
7146 if (i
.types
[op
].bitfield
.byte
)
7149 /* I/O port address operands are OK too. */
7150 if (i
.tm
.operand_types
[op
].bitfield
.instance
== RegD
7151 && i
.tm
.operand_types
[op
].bitfield
.word
)
7154 /* crc32 only wants its source operand checked here. */
7155 if (i
.tm
.base_opcode
== 0xf20f38f0 && op
)
7158 /* Any other register is bad. */
7159 as_bad (_("`%s%s' not allowed with `%s%c'"),
7160 register_prefix
, i
.op
[op
].regs
->reg_name
,
7161 i
.tm
.name
, i
.suffix
);
7168 check_long_reg (void)
7172 for (op
= i
.operands
; --op
>= 0;)
7173 /* Skip non-register operands. */
7174 if (i
.types
[op
].bitfield
.class != Reg
)
7176 /* Reject eight bit registers, except where the template requires
7177 them. (eg. movzb) */
7178 else if (i
.types
[op
].bitfield
.byte
7179 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
7180 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7181 && (i
.tm
.operand_types
[op
].bitfield
.word
7182 || i
.tm
.operand_types
[op
].bitfield
.dword
))
7184 as_bad (_("`%s%s' not allowed with `%s%c'"),
7186 i
.op
[op
].regs
->reg_name
,
7191 /* Error if the e prefix on a general reg is missing. */
7192 else if (i
.types
[op
].bitfield
.word
7193 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
7194 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7195 && i
.tm
.operand_types
[op
].bitfield
.dword
)
7197 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
7198 register_prefix
, i
.op
[op
].regs
->reg_name
,
7202 /* Warn if the r prefix on a general reg is present. */
7203 else if (i
.types
[op
].bitfield
.qword
7204 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
7205 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7206 && i
.tm
.operand_types
[op
].bitfield
.dword
)
7209 && i
.tm
.opcode_modifier
.toqword
7210 && i
.types
[0].bitfield
.class != RegSIMD
)
7212 /* Convert to QWORD. We want REX byte. */
7213 i
.suffix
= QWORD_MNEM_SUFFIX
;
7217 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
7218 register_prefix
, i
.op
[op
].regs
->reg_name
,
7227 check_qword_reg (void)
7231 for (op
= i
.operands
; --op
>= 0; )
7232 /* Skip non-register operands. */
7233 if (i
.types
[op
].bitfield
.class != Reg
)
7235 /* Reject eight bit registers, except where the template requires
7236 them. (eg. movzb) */
7237 else if (i
.types
[op
].bitfield
.byte
7238 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
7239 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7240 && (i
.tm
.operand_types
[op
].bitfield
.word
7241 || i
.tm
.operand_types
[op
].bitfield
.dword
))
7243 as_bad (_("`%s%s' not allowed with `%s%c'"),
7245 i
.op
[op
].regs
->reg_name
,
7250 /* Warn if the r prefix on a general reg is missing. */
7251 else if ((i
.types
[op
].bitfield
.word
7252 || i
.types
[op
].bitfield
.dword
)
7253 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
7254 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7255 && i
.tm
.operand_types
[op
].bitfield
.qword
)
7257 /* Prohibit these changes in the 64bit mode, since the
7258 lowering is more complicated. */
7260 && i
.tm
.opcode_modifier
.todword
7261 && i
.types
[0].bitfield
.class != RegSIMD
)
7263 /* Convert to DWORD. We don't want REX byte. */
7264 i
.suffix
= LONG_MNEM_SUFFIX
;
7268 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
7269 register_prefix
, i
.op
[op
].regs
->reg_name
,
7278 check_word_reg (void)
7281 for (op
= i
.operands
; --op
>= 0;)
7282 /* Skip non-register operands. */
7283 if (i
.types
[op
].bitfield
.class != Reg
)
7285 /* Reject eight bit registers, except where the template requires
7286 them. (eg. movzb) */
7287 else if (i
.types
[op
].bitfield
.byte
7288 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
7289 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7290 && (i
.tm
.operand_types
[op
].bitfield
.word
7291 || i
.tm
.operand_types
[op
].bitfield
.dword
))
7293 as_bad (_("`%s%s' not allowed with `%s%c'"),
7295 i
.op
[op
].regs
->reg_name
,
7300 /* Error if the e or r prefix on a general reg is present. */
7301 else if ((i
.types
[op
].bitfield
.dword
7302 || i
.types
[op
].bitfield
.qword
)
7303 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
7304 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7305 && i
.tm
.operand_types
[op
].bitfield
.word
)
7307 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
7308 register_prefix
, i
.op
[op
].regs
->reg_name
,
7316 update_imm (unsigned int j
)
7318 i386_operand_type overlap
= i
.types
[j
];
7319 if ((overlap
.bitfield
.imm8
7320 || overlap
.bitfield
.imm8s
7321 || overlap
.bitfield
.imm16
7322 || overlap
.bitfield
.imm32
7323 || overlap
.bitfield
.imm32s
7324 || overlap
.bitfield
.imm64
)
7325 && !operand_type_equal (&overlap
, &imm8
)
7326 && !operand_type_equal (&overlap
, &imm8s
)
7327 && !operand_type_equal (&overlap
, &imm16
)
7328 && !operand_type_equal (&overlap
, &imm32
)
7329 && !operand_type_equal (&overlap
, &imm32s
)
7330 && !operand_type_equal (&overlap
, &imm64
))
7334 i386_operand_type temp
;
7336 operand_type_set (&temp
, 0);
7337 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
7339 temp
.bitfield
.imm8
= overlap
.bitfield
.imm8
;
7340 temp
.bitfield
.imm8s
= overlap
.bitfield
.imm8s
;
7342 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
7343 temp
.bitfield
.imm16
= overlap
.bitfield
.imm16
;
7344 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
7346 temp
.bitfield
.imm64
= overlap
.bitfield
.imm64
;
7347 temp
.bitfield
.imm32s
= overlap
.bitfield
.imm32s
;
7350 temp
.bitfield
.imm32
= overlap
.bitfield
.imm32
;
7353 else if (operand_type_equal (&overlap
, &imm16_32_32s
)
7354 || operand_type_equal (&overlap
, &imm16_32
)
7355 || operand_type_equal (&overlap
, &imm16_32s
))
7357 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
7362 if (!operand_type_equal (&overlap
, &imm8
)
7363 && !operand_type_equal (&overlap
, &imm8s
)
7364 && !operand_type_equal (&overlap
, &imm16
)
7365 && !operand_type_equal (&overlap
, &imm32
)
7366 && !operand_type_equal (&overlap
, &imm32s
)
7367 && !operand_type_equal (&overlap
, &imm64
))
7369 as_bad (_("no instruction mnemonic suffix given; "
7370 "can't determine immediate size"));
7374 i
.types
[j
] = overlap
;
7384 /* Update the first 2 immediate operands. */
7385 n
= i
.operands
> 2 ? 2 : i
.operands
;
7388 for (j
= 0; j
< n
; j
++)
7389 if (update_imm (j
) == 0)
7392 /* The 3rd operand can't be immediate operand. */
7393 gas_assert (operand_type_check (i
.types
[2], imm
) == 0);
7400 process_operands (void)
7402 /* Default segment register this instruction will use for memory
7403 accesses. 0 means unknown. This is only for optimizing out
7404 unnecessary segment overrides. */
7405 const seg_entry
*default_seg
= 0;
7407 if (i
.tm
.opcode_modifier
.sse2avx
&& i
.tm
.opcode_modifier
.vexvvvv
)
7409 unsigned int dupl
= i
.operands
;
7410 unsigned int dest
= dupl
- 1;
7413 /* The destination must be an xmm register. */
7414 gas_assert (i
.reg_operands
7415 && MAX_OPERANDS
> dupl
7416 && operand_type_equal (&i
.types
[dest
], ®xmm
));
7418 if (i
.tm
.operand_types
[0].bitfield
.instance
== Accum
7419 && i
.tm
.operand_types
[0].bitfield
.xmmword
)
7421 if (i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
)
7423 /* Keep xmm0 for instructions with VEX prefix and 3
7425 i
.tm
.operand_types
[0].bitfield
.instance
= InstanceNone
;
7426 i
.tm
.operand_types
[0].bitfield
.class = RegSIMD
;
7431 /* We remove the first xmm0 and keep the number of
7432 operands unchanged, which in fact duplicates the
7434 for (j
= 1; j
< i
.operands
; j
++)
7436 i
.op
[j
- 1] = i
.op
[j
];
7437 i
.types
[j
- 1] = i
.types
[j
];
7438 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
7439 i
.flags
[j
- 1] = i
.flags
[j
];
7443 else if (i
.tm
.opcode_modifier
.implicit1stxmm0
)
7445 gas_assert ((MAX_OPERANDS
- 1) > dupl
7446 && (i
.tm
.opcode_modifier
.vexsources
7449 /* Add the implicit xmm0 for instructions with VEX prefix
7451 for (j
= i
.operands
; j
> 0; j
--)
7453 i
.op
[j
] = i
.op
[j
- 1];
7454 i
.types
[j
] = i
.types
[j
- 1];
7455 i
.tm
.operand_types
[j
] = i
.tm
.operand_types
[j
- 1];
7456 i
.flags
[j
] = i
.flags
[j
- 1];
7459 = (const reg_entry
*) hash_find (reg_hash
, "xmm0");
7460 i
.types
[0] = regxmm
;
7461 i
.tm
.operand_types
[0] = regxmm
;
7464 i
.reg_operands
+= 2;
7469 i
.op
[dupl
] = i
.op
[dest
];
7470 i
.types
[dupl
] = i
.types
[dest
];
7471 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
7472 i
.flags
[dupl
] = i
.flags
[dest
];
7481 i
.op
[dupl
] = i
.op
[dest
];
7482 i
.types
[dupl
] = i
.types
[dest
];
7483 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
7484 i
.flags
[dupl
] = i
.flags
[dest
];
7487 if (i
.tm
.opcode_modifier
.immext
)
7490 else if (i
.tm
.operand_types
[0].bitfield
.instance
== Accum
7491 && i
.tm
.operand_types
[0].bitfield
.xmmword
)
7495 for (j
= 1; j
< i
.operands
; j
++)
7497 i
.op
[j
- 1] = i
.op
[j
];
7498 i
.types
[j
- 1] = i
.types
[j
];
7500 /* We need to adjust fields in i.tm since they are used by
7501 build_modrm_byte. */
7502 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
7504 i
.flags
[j
- 1] = i
.flags
[j
];
7511 else if (i
.tm
.opcode_modifier
.implicitquadgroup
)
7513 unsigned int regnum
, first_reg_in_group
, last_reg_in_group
;
7515 /* The second operand must be {x,y,z}mmN, where N is a multiple of 4. */
7516 gas_assert (i
.operands
>= 2 && i
.types
[1].bitfield
.class == RegSIMD
);
7517 regnum
= register_number (i
.op
[1].regs
);
7518 first_reg_in_group
= regnum
& ~3;
7519 last_reg_in_group
= first_reg_in_group
+ 3;
7520 if (regnum
!= first_reg_in_group
)
7521 as_warn (_("source register `%s%s' implicitly denotes"
7522 " `%s%.3s%u' to `%s%.3s%u' source group in `%s'"),
7523 register_prefix
, i
.op
[1].regs
->reg_name
,
7524 register_prefix
, i
.op
[1].regs
->reg_name
, first_reg_in_group
,
7525 register_prefix
, i
.op
[1].regs
->reg_name
, last_reg_in_group
,
7528 else if (i
.tm
.opcode_modifier
.regkludge
)
7530 /* The imul $imm, %reg instruction is converted into
7531 imul $imm, %reg, %reg, and the clr %reg instruction
7532 is converted into xor %reg, %reg. */
7534 unsigned int first_reg_op
;
7536 if (operand_type_check (i
.types
[0], reg
))
7540 /* Pretend we saw the extra register operand. */
7541 gas_assert (i
.reg_operands
== 1
7542 && i
.op
[first_reg_op
+ 1].regs
== 0);
7543 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
7544 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
7549 if (i
.tm
.opcode_modifier
.modrm
)
7551 /* The opcode is completed (modulo i.tm.extension_opcode which
7552 must be put into the modrm byte). Now, we make the modrm and
7553 index base bytes based on all the info we've collected. */
7555 default_seg
= build_modrm_byte ();
7557 else if (i
.types
[0].bitfield
.class == SReg
)
7559 if (flag_code
!= CODE_64BIT
7560 ? i
.tm
.base_opcode
== POP_SEG_SHORT
7561 && i
.op
[0].regs
->reg_num
== 1
7562 : (i
.tm
.base_opcode
| 1) == POP_SEG386_SHORT
7563 && i
.op
[0].regs
->reg_num
< 4)
7565 as_bad (_("you can't `%s %s%s'"),
7566 i
.tm
.name
, register_prefix
, i
.op
[0].regs
->reg_name
);
7569 if ( i
.op
[0].regs
->reg_num
> 3 && i
.tm
.opcode_length
== 1 )
7571 i
.tm
.base_opcode
^= POP_SEG_SHORT
^ POP_SEG386_SHORT
;
7572 i
.tm
.opcode_length
= 2;
7574 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
7576 else if ((i
.tm
.base_opcode
& ~0x3) == MOV_AX_DISP32
)
7580 else if (i
.tm
.opcode_modifier
.isstring
)
7582 /* For the string instructions that allow a segment override
7583 on one of their operands, the default segment is ds. */
7586 else if (i
.short_form
)
7588 /* The register or float register operand is in operand
7590 unsigned int op
= i
.tm
.operand_types
[0].bitfield
.class != Reg
;
7592 /* Register goes in low 3 bits of opcode. */
7593 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
7594 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
7596 if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
7598 /* Warn about some common errors, but press on regardless.
7599 The first case can be generated by gcc (<= 2.8.1). */
7600 if (i
.operands
== 2)
7602 /* Reversed arguments on faddp, fsubp, etc. */
7603 as_warn (_("translating to `%s %s%s,%s%s'"), i
.tm
.name
,
7604 register_prefix
, i
.op
[!intel_syntax
].regs
->reg_name
,
7605 register_prefix
, i
.op
[intel_syntax
].regs
->reg_name
);
7609 /* Extraneous `l' suffix on fp insn. */
7610 as_warn (_("translating to `%s %s%s'"), i
.tm
.name
,
7611 register_prefix
, i
.op
[0].regs
->reg_name
);
7616 if ((i
.seg
[0] || i
.prefix
[SEG_PREFIX
])
7617 && i
.tm
.base_opcode
== 0x8d /* lea */
7618 && !is_any_vex_encoding(&i
.tm
))
7620 if (!quiet_warnings
)
7621 as_warn (_("segment override on `%s' is ineffectual"), i
.tm
.name
);
7625 i
.prefix
[SEG_PREFIX
] = 0;
7629 /* If a segment was explicitly specified, and the specified segment
7630 is neither the default nor the one already recorded from a prefix,
7631 use an opcode prefix to select it. If we never figured out what
7632 the default segment is, then default_seg will be zero at this
7633 point, and the specified segment prefix will always be used. */
7635 && i
.seg
[0] != default_seg
7636 && i
.seg
[0]->seg_prefix
!= i
.prefix
[SEG_PREFIX
])
7638 if (!add_prefix (i
.seg
[0]->seg_prefix
))
7644 static const seg_entry
*
7645 build_modrm_byte (void)
7647 const seg_entry
*default_seg
= 0;
7648 unsigned int source
, dest
;
7651 vex_3_sources
= i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
;
7654 unsigned int nds
, reg_slot
;
7657 dest
= i
.operands
- 1;
7660 /* There are 2 kinds of instructions:
7661 1. 5 operands: 4 register operands or 3 register operands
7662 plus 1 memory operand plus one Imm4 operand, VexXDS, and
7663 VexW0 or VexW1. The destination must be either XMM, YMM or
7665 2. 4 operands: 4 register operands or 3 register operands
7666 plus 1 memory operand, with VexXDS. */
7667 gas_assert ((i
.reg_operands
== 4
7668 || (i
.reg_operands
== 3 && i
.mem_operands
== 1))
7669 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
7670 && i
.tm
.opcode_modifier
.vexw
7671 && i
.tm
.operand_types
[dest
].bitfield
.class == RegSIMD
);
7673 /* If VexW1 is set, the first non-immediate operand is the source and
7674 the second non-immediate one is encoded in the immediate operand. */
7675 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
7677 source
= i
.imm_operands
;
7678 reg_slot
= i
.imm_operands
+ 1;
7682 source
= i
.imm_operands
+ 1;
7683 reg_slot
= i
.imm_operands
;
7686 if (i
.imm_operands
== 0)
7688 /* When there is no immediate operand, generate an 8bit
7689 immediate operand to encode the first operand. */
7690 exp
= &im_expressions
[i
.imm_operands
++];
7691 i
.op
[i
.operands
].imms
= exp
;
7692 i
.types
[i
.operands
] = imm8
;
7695 gas_assert (i
.tm
.operand_types
[reg_slot
].bitfield
.class == RegSIMD
);
7696 exp
->X_op
= O_constant
;
7697 exp
->X_add_number
= register_number (i
.op
[reg_slot
].regs
) << 4;
7698 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
7702 gas_assert (i
.imm_operands
== 1);
7703 gas_assert (fits_in_imm4 (i
.op
[0].imms
->X_add_number
));
7704 gas_assert (!i
.tm
.opcode_modifier
.immext
);
7706 /* Turn on Imm8 again so that output_imm will generate it. */
7707 i
.types
[0].bitfield
.imm8
= 1;
7709 gas_assert (i
.tm
.operand_types
[reg_slot
].bitfield
.class == RegSIMD
);
7710 i
.op
[0].imms
->X_add_number
7711 |= register_number (i
.op
[reg_slot
].regs
) << 4;
7712 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
7715 gas_assert (i
.tm
.operand_types
[nds
].bitfield
.class == RegSIMD
);
7716 i
.vex
.register_specifier
= i
.op
[nds
].regs
;
7721 /* i.reg_operands MUST be the number of real register operands;
7722 implicit registers do not count. If there are 3 register
7723 operands, it must be a instruction with VexNDS. For a
7724 instruction with VexNDD, the destination register is encoded
7725 in VEX prefix. If there are 4 register operands, it must be
7726 a instruction with VEX prefix and 3 sources. */
7727 if (i
.mem_operands
== 0
7728 && ((i
.reg_operands
== 2
7729 && i
.tm
.opcode_modifier
.vexvvvv
<= VEXXDS
)
7730 || (i
.reg_operands
== 3
7731 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
7732 || (i
.reg_operands
== 4 && vex_3_sources
)))
7740 /* When there are 3 operands, one of them may be immediate,
7741 which may be the first or the last operand. Otherwise,
7742 the first operand must be shift count register (cl) or it
7743 is an instruction with VexNDS. */
7744 gas_assert (i
.imm_operands
== 1
7745 || (i
.imm_operands
== 0
7746 && (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
7747 || (i
.types
[0].bitfield
.instance
== RegC
7748 && i
.types
[0].bitfield
.byte
))));
7749 if (operand_type_check (i
.types
[0], imm
)
7750 || (i
.types
[0].bitfield
.instance
== RegC
7751 && i
.types
[0].bitfield
.byte
))
7757 /* When there are 4 operands, the first two must be 8bit
7758 immediate operands. The source operand will be the 3rd
7761 For instructions with VexNDS, if the first operand
7762 an imm8, the source operand is the 2nd one. If the last
7763 operand is imm8, the source operand is the first one. */
7764 gas_assert ((i
.imm_operands
== 2
7765 && i
.types
[0].bitfield
.imm8
7766 && i
.types
[1].bitfield
.imm8
)
7767 || (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
7768 && i
.imm_operands
== 1
7769 && (i
.types
[0].bitfield
.imm8
7770 || i
.types
[i
.operands
- 1].bitfield
.imm8
7772 if (i
.imm_operands
== 2)
7776 if (i
.types
[0].bitfield
.imm8
)
7783 if (is_evex_encoding (&i
.tm
))
7785 /* For EVEX instructions, when there are 5 operands, the
7786 first one must be immediate operand. If the second one
7787 is immediate operand, the source operand is the 3th
7788 one. If the last one is immediate operand, the source
7789 operand is the 2nd one. */
7790 gas_assert (i
.imm_operands
== 2
7791 && i
.tm
.opcode_modifier
.sae
7792 && operand_type_check (i
.types
[0], imm
));
7793 if (operand_type_check (i
.types
[1], imm
))
7795 else if (operand_type_check (i
.types
[4], imm
))
7809 /* RC/SAE operand could be between DEST and SRC. That happens
7810 when one operand is GPR and the other one is XMM/YMM/ZMM
7812 if (i
.rounding
&& i
.rounding
->operand
== (int) dest
)
7815 if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
7817 /* For instructions with VexNDS, the register-only source
7818 operand must be a 32/64bit integer, XMM, YMM, ZMM, or mask
7819 register. It is encoded in VEX prefix. */
7821 i386_operand_type op
;
7824 /* Check register-only source operand when two source
7825 operands are swapped. */
7826 if (!i
.tm
.operand_types
[source
].bitfield
.baseindex
7827 && i
.tm
.operand_types
[dest
].bitfield
.baseindex
)
7835 op
= i
.tm
.operand_types
[vvvv
];
7836 if ((dest
+ 1) >= i
.operands
7837 || ((op
.bitfield
.class != Reg
7838 || (!op
.bitfield
.dword
&& !op
.bitfield
.qword
))
7839 && op
.bitfield
.class != RegSIMD
7840 && !operand_type_equal (&op
, ®mask
)))
7842 i
.vex
.register_specifier
= i
.op
[vvvv
].regs
;
7848 /* One of the register operands will be encoded in the i.rm.reg
7849 field, the other in the combined i.rm.mode and i.rm.regmem
7850 fields. If no form of this instruction supports a memory
7851 destination operand, then we assume the source operand may
7852 sometimes be a memory operand and so we need to store the
7853 destination in the i.rm.reg field. */
7854 if (!i
.tm
.opcode_modifier
.regmem
7855 && operand_type_check (i
.tm
.operand_types
[dest
], anymem
) == 0)
7857 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
7858 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
7859 if (i
.op
[dest
].regs
->reg_type
.bitfield
.class == RegMMX
7860 || i
.op
[source
].regs
->reg_type
.bitfield
.class == RegMMX
)
7861 i
.has_regmmx
= TRUE
;
7862 else if (i
.op
[dest
].regs
->reg_type
.bitfield
.class == RegSIMD
7863 || i
.op
[source
].regs
->reg_type
.bitfield
.class == RegSIMD
)
7865 if (i
.types
[dest
].bitfield
.zmmword
7866 || i
.types
[source
].bitfield
.zmmword
)
7867 i
.has_regzmm
= TRUE
;
7868 else if (i
.types
[dest
].bitfield
.ymmword
7869 || i
.types
[source
].bitfield
.ymmword
)
7870 i
.has_regymm
= TRUE
;
7872 i
.has_regxmm
= TRUE
;
7874 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
7876 if ((i
.op
[dest
].regs
->reg_flags
& RegVRex
) != 0)
7878 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
7880 if ((i
.op
[source
].regs
->reg_flags
& RegVRex
) != 0)
7885 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
7886 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
7887 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
7889 if ((i
.op
[dest
].regs
->reg_flags
& RegVRex
) != 0)
7891 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
7893 if ((i
.op
[source
].regs
->reg_flags
& RegVRex
) != 0)
7896 if (flag_code
!= CODE_64BIT
&& (i
.rex
& REX_R
))
7898 if (i
.types
[!i
.tm
.opcode_modifier
.regmem
].bitfield
.class != RegCR
)
7901 add_prefix (LOCK_PREFIX_OPCODE
);
7905 { /* If it's not 2 reg operands... */
7910 unsigned int fake_zero_displacement
= 0;
7913 for (op
= 0; op
< i
.operands
; op
++)
7914 if (i
.flags
[op
] & Operand_Mem
)
7916 gas_assert (op
< i
.operands
);
7918 if (i
.tm
.opcode_modifier
.vecsib
)
7920 if (i
.index_reg
->reg_num
== RegIZ
)
7923 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
7926 i
.sib
.base
= NO_BASE_REGISTER
;
7927 i
.sib
.scale
= i
.log2_scale_factor
;
7928 i
.types
[op
].bitfield
.disp8
= 0;
7929 i
.types
[op
].bitfield
.disp16
= 0;
7930 i
.types
[op
].bitfield
.disp64
= 0;
7931 if (flag_code
!= CODE_64BIT
|| i
.prefix
[ADDR_PREFIX
])
7933 /* Must be 32 bit */
7934 i
.types
[op
].bitfield
.disp32
= 1;
7935 i
.types
[op
].bitfield
.disp32s
= 0;
7939 i
.types
[op
].bitfield
.disp32
= 0;
7940 i
.types
[op
].bitfield
.disp32s
= 1;
7943 i
.sib
.index
= i
.index_reg
->reg_num
;
7944 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
7946 if ((i
.index_reg
->reg_flags
& RegVRex
) != 0)
7952 if (i
.base_reg
== 0)
7955 if (!i
.disp_operands
)
7956 fake_zero_displacement
= 1;
7957 if (i
.index_reg
== 0)
7959 i386_operand_type newdisp
;
7961 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
7962 /* Operand is just <disp> */
7963 if (flag_code
== CODE_64BIT
)
7965 /* 64bit mode overwrites the 32bit absolute
7966 addressing by RIP relative addressing and
7967 absolute addressing is encoded by one of the
7968 redundant SIB forms. */
7969 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
7970 i
.sib
.base
= NO_BASE_REGISTER
;
7971 i
.sib
.index
= NO_INDEX_REGISTER
;
7972 newdisp
= (!i
.prefix
[ADDR_PREFIX
] ? disp32s
: disp32
);
7974 else if ((flag_code
== CODE_16BIT
)
7975 ^ (i
.prefix
[ADDR_PREFIX
] != 0))
7977 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
7982 i
.rm
.regmem
= NO_BASE_REGISTER
;
7985 i
.types
[op
] = operand_type_and_not (i
.types
[op
], anydisp
);
7986 i
.types
[op
] = operand_type_or (i
.types
[op
], newdisp
);
7988 else if (!i
.tm
.opcode_modifier
.vecsib
)
7990 /* !i.base_reg && i.index_reg */
7991 if (i
.index_reg
->reg_num
== RegIZ
)
7992 i
.sib
.index
= NO_INDEX_REGISTER
;
7994 i
.sib
.index
= i
.index_reg
->reg_num
;
7995 i
.sib
.base
= NO_BASE_REGISTER
;
7996 i
.sib
.scale
= i
.log2_scale_factor
;
7997 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
7998 i
.types
[op
].bitfield
.disp8
= 0;
7999 i
.types
[op
].bitfield
.disp16
= 0;
8000 i
.types
[op
].bitfield
.disp64
= 0;
8001 if (flag_code
!= CODE_64BIT
|| i
.prefix
[ADDR_PREFIX
])
8003 /* Must be 32 bit */
8004 i
.types
[op
].bitfield
.disp32
= 1;
8005 i
.types
[op
].bitfield
.disp32s
= 0;
8009 i
.types
[op
].bitfield
.disp32
= 0;
8010 i
.types
[op
].bitfield
.disp32s
= 1;
8012 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
8016 /* RIP addressing for 64bit mode. */
8017 else if (i
.base_reg
->reg_num
== RegIP
)
8019 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
8020 i
.rm
.regmem
= NO_BASE_REGISTER
;
8021 i
.types
[op
].bitfield
.disp8
= 0;
8022 i
.types
[op
].bitfield
.disp16
= 0;
8023 i
.types
[op
].bitfield
.disp32
= 0;
8024 i
.types
[op
].bitfield
.disp32s
= 1;
8025 i
.types
[op
].bitfield
.disp64
= 0;
8026 i
.flags
[op
] |= Operand_PCrel
;
8027 if (! i
.disp_operands
)
8028 fake_zero_displacement
= 1;
8030 else if (i
.base_reg
->reg_type
.bitfield
.word
)
8032 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
8033 switch (i
.base_reg
->reg_num
)
8036 if (i
.index_reg
== 0)
8038 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
8039 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
8043 if (i
.index_reg
== 0)
8046 if (operand_type_check (i
.types
[op
], disp
) == 0)
8048 /* fake (%bp) into 0(%bp) */
8049 i
.types
[op
].bitfield
.disp8
= 1;
8050 fake_zero_displacement
= 1;
8053 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
8054 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
8056 default: /* (%si) -> 4 or (%di) -> 5 */
8057 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
8059 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
8061 else /* i.base_reg and 32/64 bit mode */
8063 if (flag_code
== CODE_64BIT
8064 && operand_type_check (i
.types
[op
], disp
))
8066 i
.types
[op
].bitfield
.disp16
= 0;
8067 i
.types
[op
].bitfield
.disp64
= 0;
8068 if (i
.prefix
[ADDR_PREFIX
] == 0)
8070 i
.types
[op
].bitfield
.disp32
= 0;
8071 i
.types
[op
].bitfield
.disp32s
= 1;
8075 i
.types
[op
].bitfield
.disp32
= 1;
8076 i
.types
[op
].bitfield
.disp32s
= 0;
8080 if (!i
.tm
.opcode_modifier
.vecsib
)
8081 i
.rm
.regmem
= i
.base_reg
->reg_num
;
8082 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
8084 i
.sib
.base
= i
.base_reg
->reg_num
;
8085 /* x86-64 ignores REX prefix bit here to avoid decoder
8087 if (!(i
.base_reg
->reg_flags
& RegRex
)
8088 && (i
.base_reg
->reg_num
== EBP_REG_NUM
8089 || i
.base_reg
->reg_num
== ESP_REG_NUM
))
8091 if (i
.base_reg
->reg_num
== 5 && i
.disp_operands
== 0)
8093 fake_zero_displacement
= 1;
8094 i
.types
[op
].bitfield
.disp8
= 1;
8096 i
.sib
.scale
= i
.log2_scale_factor
;
8097 if (i
.index_reg
== 0)
8099 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
8100 /* <disp>(%esp) becomes two byte modrm with no index
8101 register. We've already stored the code for esp
8102 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
8103 Any base register besides %esp will not use the
8104 extra modrm byte. */
8105 i
.sib
.index
= NO_INDEX_REGISTER
;
8107 else if (!i
.tm
.opcode_modifier
.vecsib
)
8109 if (i
.index_reg
->reg_num
== RegIZ
)
8110 i
.sib
.index
= NO_INDEX_REGISTER
;
8112 i
.sib
.index
= i
.index_reg
->reg_num
;
8113 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
8114 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
8119 && (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
8120 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
))
8124 if (!fake_zero_displacement
8128 fake_zero_displacement
= 1;
8129 if (i
.disp_encoding
== disp_encoding_8bit
)
8130 i
.types
[op
].bitfield
.disp8
= 1;
8132 i
.types
[op
].bitfield
.disp32
= 1;
8134 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
8138 if (fake_zero_displacement
)
8140 /* Fakes a zero displacement assuming that i.types[op]
8141 holds the correct displacement size. */
8144 gas_assert (i
.op
[op
].disps
== 0);
8145 exp
= &disp_expressions
[i
.disp_operands
++];
8146 i
.op
[op
].disps
= exp
;
8147 exp
->X_op
= O_constant
;
8148 exp
->X_add_number
= 0;
8149 exp
->X_add_symbol
= (symbolS
*) 0;
8150 exp
->X_op_symbol
= (symbolS
*) 0;
8158 if (i
.tm
.opcode_modifier
.vexsources
== XOP2SOURCES
)
8160 if (operand_type_check (i
.types
[0], imm
))
8161 i
.vex
.register_specifier
= NULL
;
8164 /* VEX.vvvv encodes one of the sources when the first
8165 operand is not an immediate. */
8166 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
8167 i
.vex
.register_specifier
= i
.op
[0].regs
;
8169 i
.vex
.register_specifier
= i
.op
[1].regs
;
8172 /* Destination is a XMM register encoded in the ModRM.reg
8174 i
.rm
.reg
= i
.op
[2].regs
->reg_num
;
8175 if ((i
.op
[2].regs
->reg_flags
& RegRex
) != 0)
8178 /* ModRM.rm and VEX.B encodes the other source. */
8179 if (!i
.mem_operands
)
8183 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
8184 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
8186 i
.rm
.regmem
= i
.op
[0].regs
->reg_num
;
8188 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
8192 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXLWP
)
8194 i
.vex
.register_specifier
= i
.op
[2].regs
;
8195 if (!i
.mem_operands
)
8198 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
8199 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
8203 /* Fill in i.rm.reg or i.rm.regmem field with register operand
8204 (if any) based on i.tm.extension_opcode. Again, we must be
8205 careful to make sure that segment/control/debug/test/MMX
8206 registers are coded into the i.rm.reg field. */
8207 else if (i
.reg_operands
)
8210 unsigned int vex_reg
= ~0;
8212 for (op
= 0; op
< i
.operands
; op
++)
8214 if (i
.types
[op
].bitfield
.class == Reg
8215 || i
.types
[op
].bitfield
.class == RegBND
8216 || i
.types
[op
].bitfield
.class == RegMask
8217 || i
.types
[op
].bitfield
.class == SReg
8218 || i
.types
[op
].bitfield
.class == RegCR
8219 || i
.types
[op
].bitfield
.class == RegDR
8220 || i
.types
[op
].bitfield
.class == RegTR
)
8222 if (i
.types
[op
].bitfield
.class == RegSIMD
)
8224 if (i
.types
[op
].bitfield
.zmmword
)
8225 i
.has_regzmm
= TRUE
;
8226 else if (i
.types
[op
].bitfield
.ymmword
)
8227 i
.has_regymm
= TRUE
;
8229 i
.has_regxmm
= TRUE
;
8232 if (i
.types
[op
].bitfield
.class == RegMMX
)
8234 i
.has_regmmx
= TRUE
;
8241 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
8243 /* For instructions with VexNDS, the register-only
8244 source operand is encoded in VEX prefix. */
8245 gas_assert (mem
!= (unsigned int) ~0);
8250 gas_assert (op
< i
.operands
);
8254 /* Check register-only source operand when two source
8255 operands are swapped. */
8256 if (!i
.tm
.operand_types
[op
].bitfield
.baseindex
8257 && i
.tm
.operand_types
[op
+ 1].bitfield
.baseindex
)
8261 gas_assert (mem
== (vex_reg
+ 1)
8262 && op
< i
.operands
);
8267 gas_assert (vex_reg
< i
.operands
);
8271 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXNDD
)
8273 /* For instructions with VexNDD, the register destination
8274 is encoded in VEX prefix. */
8275 if (i
.mem_operands
== 0)
8277 /* There is no memory operand. */
8278 gas_assert ((op
+ 2) == i
.operands
);
8283 /* There are only 2 non-immediate operands. */
8284 gas_assert (op
< i
.imm_operands
+ 2
8285 && i
.operands
== i
.imm_operands
+ 2);
8286 vex_reg
= i
.imm_operands
+ 1;
8290 gas_assert (op
< i
.operands
);
8292 if (vex_reg
!= (unsigned int) ~0)
8294 i386_operand_type
*type
= &i
.tm
.operand_types
[vex_reg
];
8296 if ((type
->bitfield
.class != Reg
8297 || (!type
->bitfield
.dword
&& !type
->bitfield
.qword
))
8298 && type
->bitfield
.class != RegSIMD
8299 && !operand_type_equal (type
, ®mask
))
8302 i
.vex
.register_specifier
= i
.op
[vex_reg
].regs
;
8305 /* Don't set OP operand twice. */
8308 /* If there is an extension opcode to put here, the
8309 register number must be put into the regmem field. */
8310 if (i
.tm
.extension_opcode
!= None
)
8312 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
8313 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
8315 if ((i
.op
[op
].regs
->reg_flags
& RegVRex
) != 0)
8320 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
8321 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
8323 if ((i
.op
[op
].regs
->reg_flags
& RegVRex
) != 0)
8328 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
8329 must set it to 3 to indicate this is a register operand
8330 in the regmem field. */
8331 if (!i
.mem_operands
)
8335 /* Fill in i.rm.reg field with extension opcode (if any). */
8336 if (i
.tm
.extension_opcode
!= None
)
8337 i
.rm
.reg
= i
.tm
.extension_opcode
;
8343 flip_code16 (unsigned int code16
)
8345 gas_assert (i
.tm
.operands
== 1);
8347 return !(i
.prefix
[REX_PREFIX
] & REX_W
)
8348 && (code16
? i
.tm
.operand_types
[0].bitfield
.disp32
8349 || i
.tm
.operand_types
[0].bitfield
.disp32s
8350 : i
.tm
.operand_types
[0].bitfield
.disp16
)
8355 output_branch (void)
8361 relax_substateT subtype
;
8365 code16
= flag_code
== CODE_16BIT
? CODE16
: 0;
8366 size
= i
.disp_encoding
== disp_encoding_32bit
? BIG
: SMALL
;
8369 if (i
.prefix
[DATA_PREFIX
] != 0)
8373 code16
^= flip_code16(code16
);
8375 /* Pentium4 branch hints. */
8376 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
8377 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
8382 if (i
.prefix
[REX_PREFIX
] != 0)
8388 /* BND prefixed jump. */
8389 if (i
.prefix
[BND_PREFIX
] != 0)
8395 if (i
.prefixes
!= 0)
8396 as_warn (_("skipping prefixes on `%s'"), i
.tm
.name
);
8398 /* It's always a symbol; End frag & setup for relax.
8399 Make sure there is enough room in this frag for the largest
8400 instruction we may generate in md_convert_frag. This is 2
8401 bytes for the opcode and room for the prefix and largest
8403 frag_grow (prefix
+ 2 + 4);
8404 /* Prefix and 1 opcode byte go in fr_fix. */
8405 p
= frag_more (prefix
+ 1);
8406 if (i
.prefix
[DATA_PREFIX
] != 0)
8407 *p
++ = DATA_PREFIX_OPCODE
;
8408 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
8409 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
8410 *p
++ = i
.prefix
[SEG_PREFIX
];
8411 if (i
.prefix
[BND_PREFIX
] != 0)
8412 *p
++ = BND_PREFIX_OPCODE
;
8413 if (i
.prefix
[REX_PREFIX
] != 0)
8414 *p
++ = i
.prefix
[REX_PREFIX
];
8415 *p
= i
.tm
.base_opcode
;
8417 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
8418 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, size
);
8419 else if (cpu_arch_flags
.bitfield
.cpui386
)
8420 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, size
);
8422 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, size
);
8425 sym
= i
.op
[0].disps
->X_add_symbol
;
8426 off
= i
.op
[0].disps
->X_add_number
;
8428 if (i
.op
[0].disps
->X_op
!= O_constant
8429 && i
.op
[0].disps
->X_op
!= O_symbol
)
8431 /* Handle complex expressions. */
8432 sym
= make_expr_symbol (i
.op
[0].disps
);
8436 /* 1 possible extra opcode + 4 byte displacement go in var part.
8437 Pass reloc in fr_var. */
8438 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
8441 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8442 /* Return TRUE iff PLT32 relocation should be used for branching to
8446 need_plt32_p (symbolS
*s
)
8448 /* PLT32 relocation is ELF only. */
8453 /* Don't emit PLT32 relocation on Solaris: neither native linker nor
8454 krtld support it. */
8458 /* Since there is no need to prepare for PLT branch on x86-64, we
8459 can generate R_X86_64_PLT32, instead of R_X86_64_PC32, which can
8460 be used as a marker for 32-bit PC-relative branches. */
8464 /* Weak or undefined symbol need PLT32 relocation. */
8465 if (S_IS_WEAK (s
) || !S_IS_DEFINED (s
))
8468 /* Non-global symbol doesn't need PLT32 relocation. */
8469 if (! S_IS_EXTERNAL (s
))
8472 /* Other global symbols need PLT32 relocation. NB: Symbol with
8473 non-default visibilities are treated as normal global symbol
8474 so that PLT32 relocation can be used as a marker for 32-bit
8475 PC-relative branches. It is useful for linker relaxation. */
8486 bfd_reloc_code_real_type jump_reloc
= i
.reloc
[0];
8488 if (i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
)
8490 /* This is a loop or jecxz type instruction. */
8492 if (i
.prefix
[ADDR_PREFIX
] != 0)
8494 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
8497 /* Pentium4 branch hints. */
8498 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
8499 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
8501 FRAG_APPEND_1_CHAR (i
.prefix
[SEG_PREFIX
]);
8510 if (flag_code
== CODE_16BIT
)
8513 if (i
.prefix
[DATA_PREFIX
] != 0)
8515 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
8517 code16
^= flip_code16(code16
);
8525 /* BND prefixed jump. */
8526 if (i
.prefix
[BND_PREFIX
] != 0)
8528 FRAG_APPEND_1_CHAR (i
.prefix
[BND_PREFIX
]);
8532 if (i
.prefix
[REX_PREFIX
] != 0)
8534 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
8538 if (i
.prefixes
!= 0)
8539 as_warn (_("skipping prefixes on `%s'"), i
.tm
.name
);
8541 p
= frag_more (i
.tm
.opcode_length
+ size
);
8542 switch (i
.tm
.opcode_length
)
8545 *p
++ = i
.tm
.base_opcode
>> 8;
8548 *p
++ = i
.tm
.base_opcode
;
8554 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8556 && jump_reloc
== NO_RELOC
8557 && need_plt32_p (i
.op
[0].disps
->X_add_symbol
))
8558 jump_reloc
= BFD_RELOC_X86_64_PLT32
;
8561 jump_reloc
= reloc (size
, 1, 1, jump_reloc
);
8563 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
8564 i
.op
[0].disps
, 1, jump_reloc
);
8566 /* All jumps handled here are signed, but don't use a signed limit
8567 check for 32 and 16 bit jumps as we want to allow wrap around at
8568 4G and 64k respectively. */
8570 fixP
->fx_signed
= 1;
8574 output_interseg_jump (void)
8582 if (flag_code
== CODE_16BIT
)
8586 if (i
.prefix
[DATA_PREFIX
] != 0)
8593 gas_assert (!i
.prefix
[REX_PREFIX
]);
8599 if (i
.prefixes
!= 0)
8600 as_warn (_("skipping prefixes on `%s'"), i
.tm
.name
);
8602 /* 1 opcode; 2 segment; offset */
8603 p
= frag_more (prefix
+ 1 + 2 + size
);
8605 if (i
.prefix
[DATA_PREFIX
] != 0)
8606 *p
++ = DATA_PREFIX_OPCODE
;
8608 if (i
.prefix
[REX_PREFIX
] != 0)
8609 *p
++ = i
.prefix
[REX_PREFIX
];
8611 *p
++ = i
.tm
.base_opcode
;
8612 if (i
.op
[1].imms
->X_op
== O_constant
)
8614 offsetT n
= i
.op
[1].imms
->X_add_number
;
8617 && !fits_in_unsigned_word (n
)
8618 && !fits_in_signed_word (n
))
8620 as_bad (_("16-bit jump out of range"));
8623 md_number_to_chars (p
, n
, size
);
8626 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
8627 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
8628 if (i
.op
[0].imms
->X_op
!= O_constant
)
8629 as_bad (_("can't handle non absolute segment in `%s'"),
8631 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
8634 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8639 asection
*seg
= now_seg
;
8640 subsegT subseg
= now_subseg
;
8642 unsigned int alignment
, align_size_1
;
8643 unsigned int isa_1_descsz
, feature_2_descsz
, descsz
;
8644 unsigned int isa_1_descsz_raw
, feature_2_descsz_raw
;
8645 unsigned int padding
;
8647 if (!IS_ELF
|| !x86_used_note
)
8650 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_X86
;
8652 /* The .note.gnu.property section layout:
8654 Field Length Contents
8657 n_descsz 4 The note descriptor size
8658 n_type 4 NT_GNU_PROPERTY_TYPE_0
8660 n_desc n_descsz The program property array
8664 /* Create the .note.gnu.property section. */
8665 sec
= subseg_new (NOTE_GNU_PROPERTY_SECTION_NAME
, 0);
8666 bfd_set_section_flags (sec
,
8673 if (get_elf_backend_data (stdoutput
)->s
->elfclass
== ELFCLASS64
)
8684 bfd_set_section_alignment (sec
, alignment
);
8685 elf_section_type (sec
) = SHT_NOTE
;
8687 /* GNU_PROPERTY_X86_ISA_1_USED: 4-byte type + 4-byte data size
8689 isa_1_descsz_raw
= 4 + 4 + 4;
8690 /* Align GNU_PROPERTY_X86_ISA_1_USED. */
8691 isa_1_descsz
= (isa_1_descsz_raw
+ align_size_1
) & ~align_size_1
;
8693 feature_2_descsz_raw
= isa_1_descsz
;
8694 /* GNU_PROPERTY_X86_FEATURE_2_USED: 4-byte type + 4-byte data size
8696 feature_2_descsz_raw
+= 4 + 4 + 4;
8697 /* Align GNU_PROPERTY_X86_FEATURE_2_USED. */
8698 feature_2_descsz
= ((feature_2_descsz_raw
+ align_size_1
)
8701 descsz
= feature_2_descsz
;
8702 /* Section size: n_namsz + n_descsz + n_type + n_name + n_descsz. */
8703 p
= frag_more (4 + 4 + 4 + 4 + descsz
);
8705 /* Write n_namsz. */
8706 md_number_to_chars (p
, (valueT
) 4, 4);
8708 /* Write n_descsz. */
8709 md_number_to_chars (p
+ 4, (valueT
) descsz
, 4);
8712 md_number_to_chars (p
+ 4 * 2, (valueT
) NT_GNU_PROPERTY_TYPE_0
, 4);
8715 memcpy (p
+ 4 * 3, "GNU", 4);
8717 /* Write 4-byte type. */
8718 md_number_to_chars (p
+ 4 * 4,
8719 (valueT
) GNU_PROPERTY_X86_ISA_1_USED
, 4);
8721 /* Write 4-byte data size. */
8722 md_number_to_chars (p
+ 4 * 5, (valueT
) 4, 4);
8724 /* Write 4-byte data. */
8725 md_number_to_chars (p
+ 4 * 6, (valueT
) x86_isa_1_used
, 4);
8727 /* Zero out paddings. */
8728 padding
= isa_1_descsz
- isa_1_descsz_raw
;
8730 memset (p
+ 4 * 7, 0, padding
);
8732 /* Write 4-byte type. */
8733 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 4,
8734 (valueT
) GNU_PROPERTY_X86_FEATURE_2_USED
, 4);
8736 /* Write 4-byte data size. */
8737 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 5, (valueT
) 4, 4);
8739 /* Write 4-byte data. */
8740 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 6,
8741 (valueT
) x86_feature_2_used
, 4);
8743 /* Zero out paddings. */
8744 padding
= feature_2_descsz
- feature_2_descsz_raw
;
8746 memset (p
+ isa_1_descsz
+ 4 * 7, 0, padding
);
8748 /* We probably can't restore the current segment, for there likely
8751 subseg_set (seg
, subseg
);
8756 encoding_length (const fragS
*start_frag
, offsetT start_off
,
8757 const char *frag_now_ptr
)
8759 unsigned int len
= 0;
8761 if (start_frag
!= frag_now
)
8763 const fragS
*fr
= start_frag
;
8768 } while (fr
&& fr
!= frag_now
);
8771 return len
- start_off
+ (frag_now_ptr
- frag_now
->fr_literal
);
8774 /* Return 1 for test, and, cmp, add, sub, inc and dec which may
8775 be macro-fused with conditional jumps.
8776 NB: If TEST/AND/CMP/ADD/SUB/INC/DEC is of RIP relative address,
8777 or is one of the following format:
8790 maybe_fused_with_jcc_p (enum mf_cmp_kind
* mf_cmp_p
)
8792 /* No RIP address. */
8793 if (i
.base_reg
&& i
.base_reg
->reg_num
== RegIP
)
8796 /* No VEX/EVEX encoding. */
8797 if (is_any_vex_encoding (&i
.tm
))
8800 /* add, sub without add/sub m, imm. */
8801 if (i
.tm
.base_opcode
<= 5
8802 || (i
.tm
.base_opcode
>= 0x28 && i
.tm
.base_opcode
<= 0x2d)
8803 || ((i
.tm
.base_opcode
| 3) == 0x83
8804 && (i
.tm
.extension_opcode
== 0x5
8805 || i
.tm
.extension_opcode
== 0x0)))
8807 *mf_cmp_p
= mf_cmp_alu_cmp
;
8808 return !(i
.mem_operands
&& i
.imm_operands
);
8811 /* and without and m, imm. */
8812 if ((i
.tm
.base_opcode
>= 0x20 && i
.tm
.base_opcode
<= 0x25)
8813 || ((i
.tm
.base_opcode
| 3) == 0x83
8814 && i
.tm
.extension_opcode
== 0x4))
8816 *mf_cmp_p
= mf_cmp_test_and
;
8817 return !(i
.mem_operands
&& i
.imm_operands
);
8820 /* test without test m imm. */
8821 if ((i
.tm
.base_opcode
| 1) == 0x85
8822 || (i
.tm
.base_opcode
| 1) == 0xa9
8823 || ((i
.tm
.base_opcode
| 1) == 0xf7
8824 && i
.tm
.extension_opcode
== 0))
8826 *mf_cmp_p
= mf_cmp_test_and
;
8827 return !(i
.mem_operands
&& i
.imm_operands
);
8830 /* cmp without cmp m, imm. */
8831 if ((i
.tm
.base_opcode
>= 0x38 && i
.tm
.base_opcode
<= 0x3d)
8832 || ((i
.tm
.base_opcode
| 3) == 0x83
8833 && (i
.tm
.extension_opcode
== 0x7)))
8835 *mf_cmp_p
= mf_cmp_alu_cmp
;
8836 return !(i
.mem_operands
&& i
.imm_operands
);
8839 /* inc, dec without inc/dec m. */
8840 if ((i
.tm
.cpu_flags
.bitfield
.cpuno64
8841 && (i
.tm
.base_opcode
| 0xf) == 0x4f)
8842 || ((i
.tm
.base_opcode
| 1) == 0xff
8843 && i
.tm
.extension_opcode
<= 0x1))
8845 *mf_cmp_p
= mf_cmp_incdec
;
8846 return !i
.mem_operands
;
8852 /* Return 1 if a FUSED_JCC_PADDING frag should be generated. */
8855 add_fused_jcc_padding_frag_p (enum mf_cmp_kind
* mf_cmp_p
)
8857 /* NB: Don't work with COND_JUMP86 without i386. */
8858 if (!align_branch_power
8859 || now_seg
== absolute_section
8860 || !cpu_arch_flags
.bitfield
.cpui386
8861 || !(align_branch
& align_branch_fused_bit
))
8864 if (maybe_fused_with_jcc_p (mf_cmp_p
))
8866 if (last_insn
.kind
== last_insn_other
8867 || last_insn
.seg
!= now_seg
)
8870 as_warn_where (last_insn
.file
, last_insn
.line
,
8871 _("`%s` skips -malign-branch-boundary on `%s`"),
8872 last_insn
.name
, i
.tm
.name
);
8878 /* Return 1 if a BRANCH_PREFIX frag should be generated. */
8881 add_branch_prefix_frag_p (void)
8883 /* NB: Don't work with COND_JUMP86 without i386. Don't add prefix
8884 to PadLock instructions since they include prefixes in opcode. */
8885 if (!align_branch_power
8886 || !align_branch_prefix_size
8887 || now_seg
== absolute_section
8888 || i
.tm
.cpu_flags
.bitfield
.cpupadlock
8889 || !cpu_arch_flags
.bitfield
.cpui386
)
8892 /* Don't add prefix if it is a prefix or there is no operand in case
8893 that segment prefix is special. */
8894 if (!i
.operands
|| i
.tm
.opcode_modifier
.isprefix
)
8897 if (last_insn
.kind
== last_insn_other
8898 || last_insn
.seg
!= now_seg
)
8902 as_warn_where (last_insn
.file
, last_insn
.line
,
8903 _("`%s` skips -malign-branch-boundary on `%s`"),
8904 last_insn
.name
, i
.tm
.name
);
8909 /* Return 1 if a BRANCH_PADDING frag should be generated. */
8912 add_branch_padding_frag_p (enum align_branch_kind
*branch_p
,
8913 enum mf_jcc_kind
*mf_jcc_p
)
8917 /* NB: Don't work with COND_JUMP86 without i386. */
8918 if (!align_branch_power
8919 || now_seg
== absolute_section
8920 || !cpu_arch_flags
.bitfield
.cpui386
)
8925 /* Check for jcc and direct jmp. */
8926 if (i
.tm
.opcode_modifier
.jump
== JUMP
)
8928 if (i
.tm
.base_opcode
== JUMP_PC_RELATIVE
)
8930 *branch_p
= align_branch_jmp
;
8931 add_padding
= align_branch
& align_branch_jmp_bit
;
8935 /* Because J<cc> and JN<cc> share same group in macro-fusible table,
8936 igore the lowest bit. */
8937 *mf_jcc_p
= (i
.tm
.base_opcode
& 0x0e) >> 1;
8938 *branch_p
= align_branch_jcc
;
8939 if ((align_branch
& align_branch_jcc_bit
))
8943 else if (is_any_vex_encoding (&i
.tm
))
8945 else if ((i
.tm
.base_opcode
| 1) == 0xc3)
8948 *branch_p
= align_branch_ret
;
8949 if ((align_branch
& align_branch_ret_bit
))
8954 /* Check for indirect jmp, direct and indirect calls. */
8955 if (i
.tm
.base_opcode
== 0xe8)
8958 *branch_p
= align_branch_call
;
8959 if ((align_branch
& align_branch_call_bit
))
8962 else if (i
.tm
.base_opcode
== 0xff
8963 && (i
.tm
.extension_opcode
== 2
8964 || i
.tm
.extension_opcode
== 4))
8966 /* Indirect call and jmp. */
8967 *branch_p
= align_branch_indirect
;
8968 if ((align_branch
& align_branch_indirect_bit
))
8975 && (i
.op
[0].disps
->X_op
== O_symbol
8976 || (i
.op
[0].disps
->X_op
== O_subtract
8977 && i
.op
[0].disps
->X_op_symbol
== GOT_symbol
)))
8979 symbolS
*s
= i
.op
[0].disps
->X_add_symbol
;
8980 /* No padding to call to global or undefined tls_get_addr. */
8981 if ((S_IS_EXTERNAL (s
) || !S_IS_DEFINED (s
))
8982 && strcmp (S_GET_NAME (s
), tls_get_addr
) == 0)
8988 && last_insn
.kind
!= last_insn_other
8989 && last_insn
.seg
== now_seg
)
8992 as_warn_where (last_insn
.file
, last_insn
.line
,
8993 _("`%s` skips -malign-branch-boundary on `%s`"),
8994 last_insn
.name
, i
.tm
.name
);
9004 fragS
*insn_start_frag
;
9005 offsetT insn_start_off
;
9006 fragS
*fragP
= NULL
;
9007 enum align_branch_kind branch
= align_branch_none
;
9008 /* The initializer is arbitrary just to avoid uninitialized error.
9009 it's actually either assigned in add_branch_padding_frag_p
9010 or never be used. */
9011 enum mf_jcc_kind mf_jcc
= mf_jcc_jo
;
9013 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9014 if (IS_ELF
&& x86_used_note
)
9016 if (i
.tm
.cpu_flags
.bitfield
.cpucmov
)
9017 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_CMOV
;
9018 if (i
.tm
.cpu_flags
.bitfield
.cpusse
)
9019 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE
;
9020 if (i
.tm
.cpu_flags
.bitfield
.cpusse2
)
9021 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE2
;
9022 if (i
.tm
.cpu_flags
.bitfield
.cpusse3
)
9023 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE3
;
9024 if (i
.tm
.cpu_flags
.bitfield
.cpussse3
)
9025 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSSE3
;
9026 if (i
.tm
.cpu_flags
.bitfield
.cpusse4_1
)
9027 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE4_1
;
9028 if (i
.tm
.cpu_flags
.bitfield
.cpusse4_2
)
9029 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE4_2
;
9030 if (i
.tm
.cpu_flags
.bitfield
.cpuavx
)
9031 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX
;
9032 if (i
.tm
.cpu_flags
.bitfield
.cpuavx2
)
9033 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX2
;
9034 if (i
.tm
.cpu_flags
.bitfield
.cpufma
)
9035 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_FMA
;
9036 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512f
)
9037 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512F
;
9038 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512cd
)
9039 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512CD
;
9040 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512er
)
9041 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512ER
;
9042 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512pf
)
9043 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512PF
;
9044 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512vl
)
9045 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512VL
;
9046 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512dq
)
9047 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512DQ
;
9048 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512bw
)
9049 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512BW
;
9050 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_4fmaps
)
9051 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_4FMAPS
;
9052 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_4vnniw
)
9053 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_4VNNIW
;
9054 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_bitalg
)
9055 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_BITALG
;
9056 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512ifma
)
9057 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_IFMA
;
9058 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512vbmi
)
9059 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_VBMI
;
9060 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_vbmi2
)
9061 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_VBMI2
;
9062 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_vnni
)
9063 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_VNNI
;
9064 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_bf16
)
9065 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_BF16
;
9067 if (i
.tm
.cpu_flags
.bitfield
.cpu8087
9068 || i
.tm
.cpu_flags
.bitfield
.cpu287
9069 || i
.tm
.cpu_flags
.bitfield
.cpu387
9070 || i
.tm
.cpu_flags
.bitfield
.cpu687
9071 || i
.tm
.cpu_flags
.bitfield
.cpufisttp
)
9072 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_X87
;
9074 || i
.tm
.base_opcode
== 0xf77 /* emms */
9075 || i
.tm
.base_opcode
== 0xf0e /* femms */
9076 || i
.tm
.base_opcode
== 0xf2a /* cvtpi2ps */
9077 || i
.tm
.base_opcode
== 0x660f2a /* cvtpi2pd */)
9078 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_MMX
;
9080 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XMM
;
9082 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_YMM
;
9084 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_ZMM
;
9085 if (i
.tm
.cpu_flags
.bitfield
.cpufxsr
)
9086 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_FXSR
;
9087 if (i
.tm
.cpu_flags
.bitfield
.cpuxsave
)
9088 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVE
;
9089 if (i
.tm
.cpu_flags
.bitfield
.cpuxsaveopt
)
9090 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVEOPT
;
9091 if (i
.tm
.cpu_flags
.bitfield
.cpuxsavec
)
9092 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVEC
;
9096 /* Tie dwarf2 debug info to the address at the start of the insn.
9097 We can't do this after the insn has been output as the current
9098 frag may have been closed off. eg. by frag_var. */
9099 dwarf2_emit_insn (0);
9101 insn_start_frag
= frag_now
;
9102 insn_start_off
= frag_now_fix ();
9104 if (add_branch_padding_frag_p (&branch
, &mf_jcc
))
9107 /* Branch can be 8 bytes. Leave some room for prefixes. */
9108 unsigned int max_branch_padding_size
= 14;
9110 /* Align section to boundary. */
9111 record_alignment (now_seg
, align_branch_power
);
9113 /* Make room for padding. */
9114 frag_grow (max_branch_padding_size
);
9116 /* Start of the padding. */
9121 frag_var (rs_machine_dependent
, max_branch_padding_size
, 0,
9122 ENCODE_RELAX_STATE (BRANCH_PADDING
, 0),
9125 fragP
->tc_frag_data
.mf_type
= mf_jcc
;
9126 fragP
->tc_frag_data
.branch_type
= branch
;
9127 fragP
->tc_frag_data
.max_bytes
= max_branch_padding_size
;
9131 if (i
.tm
.opcode_modifier
.jump
== JUMP
)
9133 else if (i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
9134 || i
.tm
.opcode_modifier
.jump
== JUMP_DWORD
)
9136 else if (i
.tm
.opcode_modifier
.jump
== JUMP_INTERSEGMENT
)
9137 output_interseg_jump ();
9140 /* Output normal instructions here. */
9144 unsigned int prefix
;
9145 enum mf_cmp_kind mf_cmp
;
9148 && (i
.tm
.base_opcode
== 0xfaee8
9149 || i
.tm
.base_opcode
== 0xfaef0
9150 || i
.tm
.base_opcode
== 0xfaef8))
9152 /* Encode lfence, mfence, and sfence as
9153 f0 83 04 24 00 lock addl $0x0, (%{re}sp). */
9154 offsetT val
= 0x240483f0ULL
;
9156 md_number_to_chars (p
, val
, 5);
9160 /* Some processors fail on LOCK prefix. This options makes
9161 assembler ignore LOCK prefix and serves as a workaround. */
9162 if (omit_lock_prefix
)
9164 if (i
.tm
.base_opcode
== LOCK_PREFIX_OPCODE
)
9166 i
.prefix
[LOCK_PREFIX
] = 0;
9170 /* Skip if this is a branch. */
9172 else if (add_fused_jcc_padding_frag_p (&mf_cmp
))
9174 /* Make room for padding. */
9175 frag_grow (MAX_FUSED_JCC_PADDING_SIZE
);
9180 frag_var (rs_machine_dependent
, MAX_FUSED_JCC_PADDING_SIZE
, 0,
9181 ENCODE_RELAX_STATE (FUSED_JCC_PADDING
, 0),
9184 fragP
->tc_frag_data
.mf_type
= mf_cmp
;
9185 fragP
->tc_frag_data
.branch_type
= align_branch_fused
;
9186 fragP
->tc_frag_data
.max_bytes
= MAX_FUSED_JCC_PADDING_SIZE
;
9188 else if (add_branch_prefix_frag_p ())
9190 unsigned int max_prefix_size
= align_branch_prefix_size
;
9192 /* Make room for padding. */
9193 frag_grow (max_prefix_size
);
9198 frag_var (rs_machine_dependent
, max_prefix_size
, 0,
9199 ENCODE_RELAX_STATE (BRANCH_PREFIX
, 0),
9202 fragP
->tc_frag_data
.max_bytes
= max_prefix_size
;
9205 /* Since the VEX/EVEX prefix contains the implicit prefix, we
9206 don't need the explicit prefix. */
9207 if (!i
.tm
.opcode_modifier
.vex
&& !i
.tm
.opcode_modifier
.evex
)
9209 switch (i
.tm
.opcode_length
)
9212 if (i
.tm
.base_opcode
& 0xff000000)
9214 prefix
= (i
.tm
.base_opcode
>> 24) & 0xff;
9215 if (!i
.tm
.cpu_flags
.bitfield
.cpupadlock
9216 || prefix
!= REPE_PREFIX_OPCODE
9217 || (i
.prefix
[REP_PREFIX
] != REPE_PREFIX_OPCODE
))
9218 add_prefix (prefix
);
9222 if ((i
.tm
.base_opcode
& 0xff0000) != 0)
9224 prefix
= (i
.tm
.base_opcode
>> 16) & 0xff;
9225 add_prefix (prefix
);
9231 /* Check for pseudo prefixes. */
9232 as_bad_where (insn_start_frag
->fr_file
,
9233 insn_start_frag
->fr_line
,
9234 _("pseudo prefix without instruction"));
9240 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
9241 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
9242 R_X86_64_GOTTPOFF relocation so that linker can safely
9243 perform IE->LE optimization. A dummy REX_OPCODE prefix
9244 is also needed for lea with R_X86_64_GOTPC32_TLSDESC
9245 relocation for GDesc -> IE/LE optimization. */
9246 if (x86_elf_abi
== X86_64_X32_ABI
9248 && (i
.reloc
[0] == BFD_RELOC_X86_64_GOTTPOFF
9249 || i
.reloc
[0] == BFD_RELOC_X86_64_GOTPC32_TLSDESC
)
9250 && i
.prefix
[REX_PREFIX
] == 0)
9251 add_prefix (REX_OPCODE
);
9254 /* The prefix bytes. */
9255 for (j
= ARRAY_SIZE (i
.prefix
), q
= i
.prefix
; j
> 0; j
--, q
++)
9257 FRAG_APPEND_1_CHAR (*q
);
9261 for (j
= 0, q
= i
.prefix
; j
< ARRAY_SIZE (i
.prefix
); j
++, q
++)
9266 /* REX byte is encoded in VEX prefix. */
9270 FRAG_APPEND_1_CHAR (*q
);
9273 /* There should be no other prefixes for instructions
9278 /* For EVEX instructions i.vrex should become 0 after
9279 build_evex_prefix. For VEX instructions upper 16 registers
9280 aren't available, so VREX should be 0. */
9283 /* Now the VEX prefix. */
9284 p
= frag_more (i
.vex
.length
);
9285 for (j
= 0; j
< i
.vex
.length
; j
++)
9286 p
[j
] = i
.vex
.bytes
[j
];
9289 /* Now the opcode; be careful about word order here! */
9290 if (i
.tm
.opcode_length
== 1)
9292 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
9296 switch (i
.tm
.opcode_length
)
9300 *p
++ = (i
.tm
.base_opcode
>> 24) & 0xff;
9301 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
9305 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
9315 /* Put out high byte first: can't use md_number_to_chars! */
9316 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
9317 *p
= i
.tm
.base_opcode
& 0xff;
9320 /* Now the modrm byte and sib byte (if present). */
9321 if (i
.tm
.opcode_modifier
.modrm
)
9323 FRAG_APPEND_1_CHAR ((i
.rm
.regmem
<< 0
9326 /* If i.rm.regmem == ESP (4)
9327 && i.rm.mode != (Register mode)
9329 ==> need second modrm byte. */
9330 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
9332 && !(i
.base_reg
&& i
.base_reg
->reg_type
.bitfield
.word
))
9333 FRAG_APPEND_1_CHAR ((i
.sib
.base
<< 0
9335 | i
.sib
.scale
<< 6));
9338 if (i
.disp_operands
)
9339 output_disp (insn_start_frag
, insn_start_off
);
9342 output_imm (insn_start_frag
, insn_start_off
);
9345 * frag_now_fix () returning plain abs_section_offset when we're in the
9346 * absolute section, and abs_section_offset not getting updated as data
9347 * gets added to the frag breaks the logic below.
9349 if (now_seg
!= absolute_section
)
9351 j
= encoding_length (insn_start_frag
, insn_start_off
, frag_more (0));
9353 as_warn (_("instruction length of %u bytes exceeds the limit of 15"),
9357 /* NB: Don't add prefix with GOTPC relocation since
9358 output_disp() above depends on the fixed encoding
9359 length. Can't add prefix with TLS relocation since
9360 it breaks TLS linker optimization. */
9361 unsigned int max
= i
.has_gotpc_tls_reloc
? 0 : 15 - j
;
9362 /* Prefix count on the current instruction. */
9363 unsigned int count
= i
.vex
.length
;
9365 for (k
= 0; k
< ARRAY_SIZE (i
.prefix
); k
++)
9366 /* REX byte is encoded in VEX/EVEX prefix. */
9367 if (i
.prefix
[k
] && (k
!= REX_PREFIX
|| !i
.vex
.length
))
9370 /* Count prefixes for extended opcode maps. */
9372 switch (i
.tm
.opcode_length
)
9375 if (((i
.tm
.base_opcode
>> 16) & 0xff) == 0xf)
9378 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
9390 if (((i
.tm
.base_opcode
>> 8) & 0xff) == 0xf)
9399 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
)
9402 /* Set the maximum prefix size in BRANCH_PREFIX
9404 if (fragP
->tc_frag_data
.max_bytes
> max
)
9405 fragP
->tc_frag_data
.max_bytes
= max
;
9406 if (fragP
->tc_frag_data
.max_bytes
> count
)
9407 fragP
->tc_frag_data
.max_bytes
-= count
;
9409 fragP
->tc_frag_data
.max_bytes
= 0;
9413 /* Remember the maximum prefix size in FUSED_JCC_PADDING
9415 unsigned int max_prefix_size
;
9416 if (align_branch_prefix_size
> max
)
9417 max_prefix_size
= max
;
9419 max_prefix_size
= align_branch_prefix_size
;
9420 if (max_prefix_size
> count
)
9421 fragP
->tc_frag_data
.max_prefix_length
9422 = max_prefix_size
- count
;
9425 /* Use existing segment prefix if possible. Use CS
9426 segment prefix in 64-bit mode. In 32-bit mode, use SS
9427 segment prefix with ESP/EBP base register and use DS
9428 segment prefix without ESP/EBP base register. */
9429 if (i
.prefix
[SEG_PREFIX
])
9430 fragP
->tc_frag_data
.default_prefix
= i
.prefix
[SEG_PREFIX
];
9431 else if (flag_code
== CODE_64BIT
)
9432 fragP
->tc_frag_data
.default_prefix
= CS_PREFIX_OPCODE
;
9434 && (i
.base_reg
->reg_num
== 4
9435 || i
.base_reg
->reg_num
== 5))
9436 fragP
->tc_frag_data
.default_prefix
= SS_PREFIX_OPCODE
;
9438 fragP
->tc_frag_data
.default_prefix
= DS_PREFIX_OPCODE
;
9443 /* NB: Don't work with COND_JUMP86 without i386. */
9444 if (align_branch_power
9445 && now_seg
!= absolute_section
9446 && cpu_arch_flags
.bitfield
.cpui386
)
9448 /* Terminate each frag so that we can add prefix and check for
9450 frag_wane (frag_now
);
9457 pi ("" /*line*/, &i
);
9459 #endif /* DEBUG386 */
9462 /* Return the size of the displacement operand N. */
9465 disp_size (unsigned int n
)
9469 if (i
.types
[n
].bitfield
.disp64
)
9471 else if (i
.types
[n
].bitfield
.disp8
)
9473 else if (i
.types
[n
].bitfield
.disp16
)
9478 /* Return the size of the immediate operand N. */
9481 imm_size (unsigned int n
)
9484 if (i
.types
[n
].bitfield
.imm64
)
9486 else if (i
.types
[n
].bitfield
.imm8
|| i
.types
[n
].bitfield
.imm8s
)
9488 else if (i
.types
[n
].bitfield
.imm16
)
9494 output_disp (fragS
*insn_start_frag
, offsetT insn_start_off
)
9499 for (n
= 0; n
< i
.operands
; n
++)
9501 if (operand_type_check (i
.types
[n
], disp
))
9503 if (i
.op
[n
].disps
->X_op
== O_constant
)
9505 int size
= disp_size (n
);
9506 offsetT val
= i
.op
[n
].disps
->X_add_number
;
9508 val
= offset_in_range (val
>> (size
== 1 ? i
.memshift
: 0),
9510 p
= frag_more (size
);
9511 md_number_to_chars (p
, val
, size
);
9515 enum bfd_reloc_code_real reloc_type
;
9516 int size
= disp_size (n
);
9517 int sign
= i
.types
[n
].bitfield
.disp32s
;
9518 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
9521 /* We can't have 8 bit displacement here. */
9522 gas_assert (!i
.types
[n
].bitfield
.disp8
);
9524 /* The PC relative address is computed relative
9525 to the instruction boundary, so in case immediate
9526 fields follows, we need to adjust the value. */
9527 if (pcrel
&& i
.imm_operands
)
9532 for (n1
= 0; n1
< i
.operands
; n1
++)
9533 if (operand_type_check (i
.types
[n1
], imm
))
9535 /* Only one immediate is allowed for PC
9536 relative address. */
9537 gas_assert (sz
== 0);
9539 i
.op
[n
].disps
->X_add_number
-= sz
;
9541 /* We should find the immediate. */
9542 gas_assert (sz
!= 0);
9545 p
= frag_more (size
);
9546 reloc_type
= reloc (size
, pcrel
, sign
, i
.reloc
[n
]);
9548 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
9549 && (((reloc_type
== BFD_RELOC_32
9550 || reloc_type
== BFD_RELOC_X86_64_32S
9551 || (reloc_type
== BFD_RELOC_64
9553 && (i
.op
[n
].disps
->X_op
== O_symbol
9554 || (i
.op
[n
].disps
->X_op
== O_add
9555 && ((symbol_get_value_expression
9556 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
9558 || reloc_type
== BFD_RELOC_32_PCREL
))
9562 reloc_type
= BFD_RELOC_386_GOTPC
;
9563 i
.has_gotpc_tls_reloc
= TRUE
;
9564 i
.op
[n
].imms
->X_add_number
+=
9565 encoding_length (insn_start_frag
, insn_start_off
, p
);
9567 else if (reloc_type
== BFD_RELOC_64
)
9568 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
9570 /* Don't do the adjustment for x86-64, as there
9571 the pcrel addressing is relative to the _next_
9572 insn, and that is taken care of in other code. */
9573 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
9575 else if (align_branch_power
)
9579 case BFD_RELOC_386_TLS_GD
:
9580 case BFD_RELOC_386_TLS_LDM
:
9581 case BFD_RELOC_386_TLS_IE
:
9582 case BFD_RELOC_386_TLS_IE_32
:
9583 case BFD_RELOC_386_TLS_GOTIE
:
9584 case BFD_RELOC_386_TLS_GOTDESC
:
9585 case BFD_RELOC_386_TLS_DESC_CALL
:
9586 case BFD_RELOC_X86_64_TLSGD
:
9587 case BFD_RELOC_X86_64_TLSLD
:
9588 case BFD_RELOC_X86_64_GOTTPOFF
:
9589 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
9590 case BFD_RELOC_X86_64_TLSDESC_CALL
:
9591 i
.has_gotpc_tls_reloc
= TRUE
;
9596 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
9597 size
, i
.op
[n
].disps
, pcrel
,
9599 /* Check for "call/jmp *mem", "mov mem, %reg",
9600 "test %reg, mem" and "binop mem, %reg" where binop
9601 is one of adc, add, and, cmp, or, sbb, sub, xor
9602 instructions without data prefix. Always generate
9603 R_386_GOT32X for "sym*GOT" operand in 32-bit mode. */
9604 if (i
.prefix
[DATA_PREFIX
] == 0
9605 && (generate_relax_relocations
9608 && i
.rm
.regmem
== 5))
9610 || (i
.rm
.mode
== 0 && i
.rm
.regmem
== 5))
9611 && !is_any_vex_encoding(&i
.tm
)
9612 && ((i
.operands
== 1
9613 && i
.tm
.base_opcode
== 0xff
9614 && (i
.rm
.reg
== 2 || i
.rm
.reg
== 4))
9616 && (i
.tm
.base_opcode
== 0x8b
9617 || i
.tm
.base_opcode
== 0x85
9618 || (i
.tm
.base_opcode
& ~0x38) == 0x03))))
9622 fixP
->fx_tcbit
= i
.rex
!= 0;
9624 && (i
.base_reg
->reg_num
== RegIP
))
9625 fixP
->fx_tcbit2
= 1;
9628 fixP
->fx_tcbit2
= 1;
9636 output_imm (fragS
*insn_start_frag
, offsetT insn_start_off
)
9641 for (n
= 0; n
< i
.operands
; n
++)
9643 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
9644 if (i
.rounding
&& (int) n
== i
.rounding
->operand
)
9647 if (operand_type_check (i
.types
[n
], imm
))
9649 if (i
.op
[n
].imms
->X_op
== O_constant
)
9651 int size
= imm_size (n
);
9654 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
9656 p
= frag_more (size
);
9657 md_number_to_chars (p
, val
, size
);
9661 /* Not absolute_section.
9662 Need a 32-bit fixup (don't support 8bit
9663 non-absolute imms). Try to support other
9665 enum bfd_reloc_code_real reloc_type
;
9666 int size
= imm_size (n
);
9669 if (i
.types
[n
].bitfield
.imm32s
9670 && (i
.suffix
== QWORD_MNEM_SUFFIX
9671 || (!i
.suffix
&& i
.tm
.opcode_modifier
.no_lsuf
)))
9676 p
= frag_more (size
);
9677 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
9679 /* This is tough to explain. We end up with this one if we
9680 * have operands that look like
9681 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
9682 * obtain the absolute address of the GOT, and it is strongly
9683 * preferable from a performance point of view to avoid using
9684 * a runtime relocation for this. The actual sequence of
9685 * instructions often look something like:
9690 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
9692 * The call and pop essentially return the absolute address
9693 * of the label .L66 and store it in %ebx. The linker itself
9694 * will ultimately change the first operand of the addl so
9695 * that %ebx points to the GOT, but to keep things simple, the
9696 * .o file must have this operand set so that it generates not
9697 * the absolute address of .L66, but the absolute address of
9698 * itself. This allows the linker itself simply treat a GOTPC
9699 * relocation as asking for a pcrel offset to the GOT to be
9700 * added in, and the addend of the relocation is stored in the
9701 * operand field for the instruction itself.
9703 * Our job here is to fix the operand so that it would add
9704 * the correct offset so that %ebx would point to itself. The
9705 * thing that is tricky is that .-.L66 will point to the
9706 * beginning of the instruction, so we need to further modify
9707 * the operand so that it will point to itself. There are
9708 * other cases where you have something like:
9710 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
9712 * and here no correction would be required. Internally in
9713 * the assembler we treat operands of this form as not being
9714 * pcrel since the '.' is explicitly mentioned, and I wonder
9715 * whether it would simplify matters to do it this way. Who
9716 * knows. In earlier versions of the PIC patches, the
9717 * pcrel_adjust field was used to store the correction, but
9718 * since the expression is not pcrel, I felt it would be
9719 * confusing to do it this way. */
9721 if ((reloc_type
== BFD_RELOC_32
9722 || reloc_type
== BFD_RELOC_X86_64_32S
9723 || reloc_type
== BFD_RELOC_64
)
9725 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
9726 && (i
.op
[n
].imms
->X_op
== O_symbol
9727 || (i
.op
[n
].imms
->X_op
== O_add
9728 && ((symbol_get_value_expression
9729 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
9733 reloc_type
= BFD_RELOC_386_GOTPC
;
9735 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
9737 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
9738 i
.has_gotpc_tls_reloc
= TRUE
;
9739 i
.op
[n
].imms
->X_add_number
+=
9740 encoding_length (insn_start_frag
, insn_start_off
, p
);
9742 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
9743 i
.op
[n
].imms
, 0, reloc_type
);
9749 /* x86_cons_fix_new is called via the expression parsing code when a
9750 reloc is needed. We use this hook to get the correct .got reloc. */
9751 static int cons_sign
= -1;
9754 x86_cons_fix_new (fragS
*frag
, unsigned int off
, unsigned int len
,
9755 expressionS
*exp
, bfd_reloc_code_real_type r
)
9757 r
= reloc (len
, 0, cons_sign
, r
);
9760 if (exp
->X_op
== O_secrel
)
9762 exp
->X_op
= O_symbol
;
9763 r
= BFD_RELOC_32_SECREL
;
9767 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
9770 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
9771 purpose of the `.dc.a' internal pseudo-op. */
9774 x86_address_bytes (void)
9776 if ((stdoutput
->arch_info
->mach
& bfd_mach_x64_32
))
9778 return stdoutput
->arch_info
->bits_per_address
/ 8;
9781 #if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
9783 # define lex_got(reloc, adjust, types) NULL
9785 /* Parse operands of the form
9786 <symbol>@GOTOFF+<nnn>
9787 and similar .plt or .got references.
9789 If we find one, set up the correct relocation in RELOC and copy the
9790 input string, minus the `@GOTOFF' into a malloc'd buffer for
9791 parsing by the calling routine. Return this buffer, and if ADJUST
9792 is non-null set it to the length of the string we removed from the
9793 input line. Otherwise return NULL. */
9795 lex_got (enum bfd_reloc_code_real
*rel
,
9797 i386_operand_type
*types
)
9799 /* Some of the relocations depend on the size of what field is to
9800 be relocated. But in our callers i386_immediate and i386_displacement
9801 we don't yet know the operand size (this will be set by insn
9802 matching). Hence we record the word32 relocation here,
9803 and adjust the reloc according to the real size in reloc(). */
9804 static const struct {
9807 const enum bfd_reloc_code_real rel
[2];
9808 const i386_operand_type types64
;
9810 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9811 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32
,
9813 OPERAND_TYPE_IMM32_64
},
9815 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real
,
9816 BFD_RELOC_X86_64_PLTOFF64
},
9817 OPERAND_TYPE_IMM64
},
9818 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32
,
9819 BFD_RELOC_X86_64_PLT32
},
9820 OPERAND_TYPE_IMM32_32S_DISP32
},
9821 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real
,
9822 BFD_RELOC_X86_64_GOTPLT64
},
9823 OPERAND_TYPE_IMM64_DISP64
},
9824 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF
,
9825 BFD_RELOC_X86_64_GOTOFF64
},
9826 OPERAND_TYPE_IMM64_DISP64
},
9827 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real
,
9828 BFD_RELOC_X86_64_GOTPCREL
},
9829 OPERAND_TYPE_IMM32_32S_DISP32
},
9830 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD
,
9831 BFD_RELOC_X86_64_TLSGD
},
9832 OPERAND_TYPE_IMM32_32S_DISP32
},
9833 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM
,
9834 _dummy_first_bfd_reloc_code_real
},
9835 OPERAND_TYPE_NONE
},
9836 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real
,
9837 BFD_RELOC_X86_64_TLSLD
},
9838 OPERAND_TYPE_IMM32_32S_DISP32
},
9839 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32
,
9840 BFD_RELOC_X86_64_GOTTPOFF
},
9841 OPERAND_TYPE_IMM32_32S_DISP32
},
9842 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32
,
9843 BFD_RELOC_X86_64_TPOFF32
},
9844 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
9845 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE
,
9846 _dummy_first_bfd_reloc_code_real
},
9847 OPERAND_TYPE_NONE
},
9848 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32
,
9849 BFD_RELOC_X86_64_DTPOFF32
},
9850 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
9851 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE
,
9852 _dummy_first_bfd_reloc_code_real
},
9853 OPERAND_TYPE_NONE
},
9854 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE
,
9855 _dummy_first_bfd_reloc_code_real
},
9856 OPERAND_TYPE_NONE
},
9857 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32
,
9858 BFD_RELOC_X86_64_GOT32
},
9859 OPERAND_TYPE_IMM32_32S_64_DISP32
},
9860 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC
,
9861 BFD_RELOC_X86_64_GOTPC32_TLSDESC
},
9862 OPERAND_TYPE_IMM32_32S_DISP32
},
9863 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL
,
9864 BFD_RELOC_X86_64_TLSDESC_CALL
},
9865 OPERAND_TYPE_IMM32_32S_DISP32
},
9870 #if defined (OBJ_MAYBE_ELF)
9875 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
9876 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
9879 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
9881 int len
= gotrel
[j
].len
;
9882 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
9884 if (gotrel
[j
].rel
[object_64bit
] != 0)
9887 char *tmpbuf
, *past_reloc
;
9889 *rel
= gotrel
[j
].rel
[object_64bit
];
9893 if (flag_code
!= CODE_64BIT
)
9895 types
->bitfield
.imm32
= 1;
9896 types
->bitfield
.disp32
= 1;
9899 *types
= gotrel
[j
].types64
;
9902 if (j
!= 0 && GOT_symbol
== NULL
)
9903 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
9905 /* The length of the first part of our input line. */
9906 first
= cp
- input_line_pointer
;
9908 /* The second part goes from after the reloc token until
9909 (and including) an end_of_line char or comma. */
9910 past_reloc
= cp
+ 1 + len
;
9912 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
9914 second
= cp
+ 1 - past_reloc
;
9916 /* Allocate and copy string. The trailing NUL shouldn't
9917 be necessary, but be safe. */
9918 tmpbuf
= XNEWVEC (char, first
+ second
+ 2);
9919 memcpy (tmpbuf
, input_line_pointer
, first
);
9920 if (second
!= 0 && *past_reloc
!= ' ')
9921 /* Replace the relocation token with ' ', so that
9922 errors like foo@GOTOFF1 will be detected. */
9923 tmpbuf
[first
++] = ' ';
9925 /* Increment length by 1 if the relocation token is
9930 memcpy (tmpbuf
+ first
, past_reloc
, second
);
9931 tmpbuf
[first
+ second
] = '\0';
9935 as_bad (_("@%s reloc is not supported with %d-bit output format"),
9936 gotrel
[j
].str
, 1 << (5 + object_64bit
));
9941 /* Might be a symbol version string. Don't as_bad here. */
9950 /* Parse operands of the form
9951 <symbol>@SECREL32+<nnn>
9953 If we find one, set up the correct relocation in RELOC and copy the
9954 input string, minus the `@SECREL32' into a malloc'd buffer for
9955 parsing by the calling routine. Return this buffer, and if ADJUST
9956 is non-null set it to the length of the string we removed from the
9957 input line. Otherwise return NULL.
9959 This function is copied from the ELF version above adjusted for PE targets. */
9962 lex_got (enum bfd_reloc_code_real
*rel ATTRIBUTE_UNUSED
,
9963 int *adjust ATTRIBUTE_UNUSED
,
9964 i386_operand_type
*types
)
9970 const enum bfd_reloc_code_real rel
[2];
9971 const i386_operand_type types64
;
9975 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL
,
9976 BFD_RELOC_32_SECREL
},
9977 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
9983 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
9984 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
9987 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
9989 int len
= gotrel
[j
].len
;
9991 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
9993 if (gotrel
[j
].rel
[object_64bit
] != 0)
9996 char *tmpbuf
, *past_reloc
;
9998 *rel
= gotrel
[j
].rel
[object_64bit
];
10004 if (flag_code
!= CODE_64BIT
)
10006 types
->bitfield
.imm32
= 1;
10007 types
->bitfield
.disp32
= 1;
10010 *types
= gotrel
[j
].types64
;
10013 /* The length of the first part of our input line. */
10014 first
= cp
- input_line_pointer
;
10016 /* The second part goes from after the reloc token until
10017 (and including) an end_of_line char or comma. */
10018 past_reloc
= cp
+ 1 + len
;
10020 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
10022 second
= cp
+ 1 - past_reloc
;
10024 /* Allocate and copy string. The trailing NUL shouldn't
10025 be necessary, but be safe. */
10026 tmpbuf
= XNEWVEC (char, first
+ second
+ 2);
10027 memcpy (tmpbuf
, input_line_pointer
, first
);
10028 if (second
!= 0 && *past_reloc
!= ' ')
10029 /* Replace the relocation token with ' ', so that
10030 errors like foo@SECLREL321 will be detected. */
10031 tmpbuf
[first
++] = ' ';
10032 memcpy (tmpbuf
+ first
, past_reloc
, second
);
10033 tmpbuf
[first
+ second
] = '\0';
10037 as_bad (_("@%s reloc is not supported with %d-bit output format"),
10038 gotrel
[j
].str
, 1 << (5 + object_64bit
));
10043 /* Might be a symbol version string. Don't as_bad here. */
10049 bfd_reloc_code_real_type
10050 x86_cons (expressionS
*exp
, int size
)
10052 bfd_reloc_code_real_type got_reloc
= NO_RELOC
;
10054 intel_syntax
= -intel_syntax
;
10057 if (size
== 4 || (object_64bit
&& size
== 8))
10059 /* Handle @GOTOFF and the like in an expression. */
10061 char *gotfree_input_line
;
10064 save
= input_line_pointer
;
10065 gotfree_input_line
= lex_got (&got_reloc
, &adjust
, NULL
);
10066 if (gotfree_input_line
)
10067 input_line_pointer
= gotfree_input_line
;
10071 if (gotfree_input_line
)
10073 /* expression () has merrily parsed up to the end of line,
10074 or a comma - in the wrong buffer. Transfer how far
10075 input_line_pointer has moved to the right buffer. */
10076 input_line_pointer
= (save
10077 + (input_line_pointer
- gotfree_input_line
)
10079 free (gotfree_input_line
);
10080 if (exp
->X_op
== O_constant
10081 || exp
->X_op
== O_absent
10082 || exp
->X_op
== O_illegal
10083 || exp
->X_op
== O_register
10084 || exp
->X_op
== O_big
)
10086 char c
= *input_line_pointer
;
10087 *input_line_pointer
= 0;
10088 as_bad (_("missing or invalid expression `%s'"), save
);
10089 *input_line_pointer
= c
;
10091 else if ((got_reloc
== BFD_RELOC_386_PLT32
10092 || got_reloc
== BFD_RELOC_X86_64_PLT32
)
10093 && exp
->X_op
!= O_symbol
)
10095 char c
= *input_line_pointer
;
10096 *input_line_pointer
= 0;
10097 as_bad (_("invalid PLT expression `%s'"), save
);
10098 *input_line_pointer
= c
;
10105 intel_syntax
= -intel_syntax
;
10108 i386_intel_simplify (exp
);
10114 signed_cons (int size
)
10116 if (flag_code
== CODE_64BIT
)
10124 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
10131 if (exp
.X_op
== O_symbol
)
10132 exp
.X_op
= O_secrel
;
10134 emit_expr (&exp
, 4);
10136 while (*input_line_pointer
++ == ',');
10138 input_line_pointer
--;
10139 demand_empty_rest_of_line ();
10143 /* Handle Vector operations. */
10146 check_VecOperations (char *op_string
, char *op_end
)
10148 const reg_entry
*mask
;
10153 && (op_end
== NULL
|| op_string
< op_end
))
10156 if (*op_string
== '{')
10160 /* Check broadcasts. */
10161 if (strncmp (op_string
, "1to", 3) == 0)
10166 goto duplicated_vec_op
;
10169 if (*op_string
== '8')
10171 else if (*op_string
== '4')
10173 else if (*op_string
== '2')
10175 else if (*op_string
== '1'
10176 && *(op_string
+1) == '6')
10183 as_bad (_("Unsupported broadcast: `%s'"), saved
);
10188 broadcast_op
.type
= bcst_type
;
10189 broadcast_op
.operand
= this_operand
;
10190 broadcast_op
.bytes
= 0;
10191 i
.broadcast
= &broadcast_op
;
10193 /* Check masking operation. */
10194 else if ((mask
= parse_register (op_string
, &end_op
)) != NULL
)
10196 if (mask
== &bad_reg
)
10199 /* k0 can't be used for write mask. */
10200 if (mask
->reg_type
.bitfield
.class != RegMask
|| !mask
->reg_num
)
10202 as_bad (_("`%s%s' can't be used for write mask"),
10203 register_prefix
, mask
->reg_name
);
10209 mask_op
.mask
= mask
;
10210 mask_op
.zeroing
= 0;
10211 mask_op
.operand
= this_operand
;
10217 goto duplicated_vec_op
;
10219 i
.mask
->mask
= mask
;
10221 /* Only "{z}" is allowed here. No need to check
10222 zeroing mask explicitly. */
10223 if (i
.mask
->operand
!= this_operand
)
10225 as_bad (_("invalid write mask `%s'"), saved
);
10230 op_string
= end_op
;
10232 /* Check zeroing-flag for masking operation. */
10233 else if (*op_string
== 'z')
10237 mask_op
.mask
= NULL
;
10238 mask_op
.zeroing
= 1;
10239 mask_op
.operand
= this_operand
;
10244 if (i
.mask
->zeroing
)
10247 as_bad (_("duplicated `%s'"), saved
);
10251 i
.mask
->zeroing
= 1;
10253 /* Only "{%k}" is allowed here. No need to check mask
10254 register explicitly. */
10255 if (i
.mask
->operand
!= this_operand
)
10257 as_bad (_("invalid zeroing-masking `%s'"),
10266 goto unknown_vec_op
;
10268 if (*op_string
!= '}')
10270 as_bad (_("missing `}' in `%s'"), saved
);
10275 /* Strip whitespace since the addition of pseudo prefixes
10276 changed how the scrubber treats '{'. */
10277 if (is_space_char (*op_string
))
10283 /* We don't know this one. */
10284 as_bad (_("unknown vector operation: `%s'"), saved
);
10288 if (i
.mask
&& i
.mask
->zeroing
&& !i
.mask
->mask
)
10290 as_bad (_("zeroing-masking only allowed with write mask"));
10298 i386_immediate (char *imm_start
)
10300 char *save_input_line_pointer
;
10301 char *gotfree_input_line
;
10304 i386_operand_type types
;
10306 operand_type_set (&types
, ~0);
10308 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
10310 as_bad (_("at most %d immediate operands are allowed"),
10311 MAX_IMMEDIATE_OPERANDS
);
10315 exp
= &im_expressions
[i
.imm_operands
++];
10316 i
.op
[this_operand
].imms
= exp
;
10318 if (is_space_char (*imm_start
))
10321 save_input_line_pointer
= input_line_pointer
;
10322 input_line_pointer
= imm_start
;
10324 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
10325 if (gotfree_input_line
)
10326 input_line_pointer
= gotfree_input_line
;
10328 exp_seg
= expression (exp
);
10330 SKIP_WHITESPACE ();
10332 /* Handle vector operations. */
10333 if (*input_line_pointer
== '{')
10335 input_line_pointer
= check_VecOperations (input_line_pointer
,
10337 if (input_line_pointer
== NULL
)
10341 if (*input_line_pointer
)
10342 as_bad (_("junk `%s' after expression"), input_line_pointer
);
10344 input_line_pointer
= save_input_line_pointer
;
10345 if (gotfree_input_line
)
10347 free (gotfree_input_line
);
10349 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
10350 exp
->X_op
= O_illegal
;
10353 return i386_finalize_immediate (exp_seg
, exp
, types
, imm_start
);
10357 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
10358 i386_operand_type types
, const char *imm_start
)
10360 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_illegal
|| exp
->X_op
== O_big
)
10363 as_bad (_("missing or invalid immediate expression `%s'"),
10367 else if (exp
->X_op
== O_constant
)
10369 /* Size it properly later. */
10370 i
.types
[this_operand
].bitfield
.imm64
= 1;
10371 /* If not 64bit, sign extend val. */
10372 if (flag_code
!= CODE_64BIT
10373 && (exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
10375 = (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
10377 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
10378 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
10379 && exp_seg
!= absolute_section
10380 && exp_seg
!= text_section
10381 && exp_seg
!= data_section
10382 && exp_seg
!= bss_section
10383 && exp_seg
!= undefined_section
10384 && !bfd_is_com_section (exp_seg
))
10386 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
10390 else if (!intel_syntax
&& exp_seg
== reg_section
)
10393 as_bad (_("illegal immediate register operand %s"), imm_start
);
10398 /* This is an address. The size of the address will be
10399 determined later, depending on destination register,
10400 suffix, or the default for the section. */
10401 i
.types
[this_operand
].bitfield
.imm8
= 1;
10402 i
.types
[this_operand
].bitfield
.imm16
= 1;
10403 i
.types
[this_operand
].bitfield
.imm32
= 1;
10404 i
.types
[this_operand
].bitfield
.imm32s
= 1;
10405 i
.types
[this_operand
].bitfield
.imm64
= 1;
10406 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
10414 i386_scale (char *scale
)
10417 char *save
= input_line_pointer
;
10419 input_line_pointer
= scale
;
10420 val
= get_absolute_expression ();
10425 i
.log2_scale_factor
= 0;
10428 i
.log2_scale_factor
= 1;
10431 i
.log2_scale_factor
= 2;
10434 i
.log2_scale_factor
= 3;
10438 char sep
= *input_line_pointer
;
10440 *input_line_pointer
= '\0';
10441 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
10443 *input_line_pointer
= sep
;
10444 input_line_pointer
= save
;
10448 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
10450 as_warn (_("scale factor of %d without an index register"),
10451 1 << i
.log2_scale_factor
);
10452 i
.log2_scale_factor
= 0;
10454 scale
= input_line_pointer
;
10455 input_line_pointer
= save
;
10460 i386_displacement (char *disp_start
, char *disp_end
)
10464 char *save_input_line_pointer
;
10465 char *gotfree_input_line
;
10467 i386_operand_type bigdisp
, types
= anydisp
;
10470 if (i
.disp_operands
== MAX_MEMORY_OPERANDS
)
10472 as_bad (_("at most %d displacement operands are allowed"),
10473 MAX_MEMORY_OPERANDS
);
10477 operand_type_set (&bigdisp
, 0);
10479 || i
.types
[this_operand
].bitfield
.baseindex
10480 || (current_templates
->start
->opcode_modifier
.jump
!= JUMP
10481 && current_templates
->start
->opcode_modifier
.jump
!= JUMP_DWORD
))
10483 i386_addressing_mode ();
10484 override
= (i
.prefix
[ADDR_PREFIX
] != 0);
10485 if (flag_code
== CODE_64BIT
)
10489 bigdisp
.bitfield
.disp32s
= 1;
10490 bigdisp
.bitfield
.disp64
= 1;
10493 bigdisp
.bitfield
.disp32
= 1;
10495 else if ((flag_code
== CODE_16BIT
) ^ override
)
10496 bigdisp
.bitfield
.disp16
= 1;
10498 bigdisp
.bitfield
.disp32
= 1;
10502 /* For PC-relative branches, the width of the displacement may be
10503 dependent upon data size, but is never dependent upon address size.
10504 Also make sure to not unintentionally match against a non-PC-relative
10505 branch template. */
10506 static templates aux_templates
;
10507 const insn_template
*t
= current_templates
->start
;
10508 bfd_boolean has_intel64
= FALSE
;
10510 aux_templates
.start
= t
;
10511 while (++t
< current_templates
->end
)
10513 if (t
->opcode_modifier
.jump
10514 != current_templates
->start
->opcode_modifier
.jump
)
10516 if ((t
->opcode_modifier
.isa64
>= INTEL64
))
10517 has_intel64
= TRUE
;
10519 if (t
< current_templates
->end
)
10521 aux_templates
.end
= t
;
10522 current_templates
= &aux_templates
;
10525 override
= (i
.prefix
[DATA_PREFIX
] != 0);
10526 if (flag_code
== CODE_64BIT
)
10528 if ((override
|| i
.suffix
== WORD_MNEM_SUFFIX
)
10529 && (!intel64
|| !has_intel64
))
10530 bigdisp
.bitfield
.disp16
= 1;
10532 bigdisp
.bitfield
.disp32s
= 1;
10537 override
= (i
.suffix
== (flag_code
!= CODE_16BIT
10539 : LONG_MNEM_SUFFIX
));
10540 bigdisp
.bitfield
.disp32
= 1;
10541 if ((flag_code
== CODE_16BIT
) ^ override
)
10543 bigdisp
.bitfield
.disp32
= 0;
10544 bigdisp
.bitfield
.disp16
= 1;
10548 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
10551 exp
= &disp_expressions
[i
.disp_operands
];
10552 i
.op
[this_operand
].disps
= exp
;
10554 save_input_line_pointer
= input_line_pointer
;
10555 input_line_pointer
= disp_start
;
10556 END_STRING_AND_SAVE (disp_end
);
10558 #ifndef GCC_ASM_O_HACK
10559 #define GCC_ASM_O_HACK 0
10562 END_STRING_AND_SAVE (disp_end
+ 1);
10563 if (i
.types
[this_operand
].bitfield
.baseIndex
10564 && displacement_string_end
[-1] == '+')
10566 /* This hack is to avoid a warning when using the "o"
10567 constraint within gcc asm statements.
10570 #define _set_tssldt_desc(n,addr,limit,type) \
10571 __asm__ __volatile__ ( \
10572 "movw %w2,%0\n\t" \
10573 "movw %w1,2+%0\n\t" \
10574 "rorl $16,%1\n\t" \
10575 "movb %b1,4+%0\n\t" \
10576 "movb %4,5+%0\n\t" \
10577 "movb $0,6+%0\n\t" \
10578 "movb %h1,7+%0\n\t" \
10580 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
10582 This works great except that the output assembler ends
10583 up looking a bit weird if it turns out that there is
10584 no offset. You end up producing code that looks like:
10597 So here we provide the missing zero. */
10599 *displacement_string_end
= '0';
10602 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
10603 if (gotfree_input_line
)
10604 input_line_pointer
= gotfree_input_line
;
10606 exp_seg
= expression (exp
);
10608 SKIP_WHITESPACE ();
10609 if (*input_line_pointer
)
10610 as_bad (_("junk `%s' after expression"), input_line_pointer
);
10612 RESTORE_END_STRING (disp_end
+ 1);
10614 input_line_pointer
= save_input_line_pointer
;
10615 if (gotfree_input_line
)
10617 free (gotfree_input_line
);
10619 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
10620 exp
->X_op
= O_illegal
;
10623 ret
= i386_finalize_displacement (exp_seg
, exp
, types
, disp_start
);
10625 RESTORE_END_STRING (disp_end
);
10631 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
10632 i386_operand_type types
, const char *disp_start
)
10634 i386_operand_type bigdisp
;
10637 /* We do this to make sure that the section symbol is in
10638 the symbol table. We will ultimately change the relocation
10639 to be relative to the beginning of the section. */
10640 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
10641 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
10642 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
10644 if (exp
->X_op
!= O_symbol
)
10647 if (S_IS_LOCAL (exp
->X_add_symbol
)
10648 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
10649 && S_GET_SEGMENT (exp
->X_add_symbol
) != expr_section
)
10650 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
10651 exp
->X_op
= O_subtract
;
10652 exp
->X_op_symbol
= GOT_symbol
;
10653 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
10654 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
10655 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
10656 i
.reloc
[this_operand
] = BFD_RELOC_64
;
10658 i
.reloc
[this_operand
] = BFD_RELOC_32
;
10661 else if (exp
->X_op
== O_absent
10662 || exp
->X_op
== O_illegal
10663 || exp
->X_op
== O_big
)
10666 as_bad (_("missing or invalid displacement expression `%s'"),
10671 else if (flag_code
== CODE_64BIT
10672 && !i
.prefix
[ADDR_PREFIX
]
10673 && exp
->X_op
== O_constant
)
10675 /* Since displacement is signed extended to 64bit, don't allow
10676 disp32 and turn off disp32s if they are out of range. */
10677 i
.types
[this_operand
].bitfield
.disp32
= 0;
10678 if (!fits_in_signed_long (exp
->X_add_number
))
10680 i
.types
[this_operand
].bitfield
.disp32s
= 0;
10681 if (i
.types
[this_operand
].bitfield
.baseindex
)
10683 as_bad (_("0x%lx out range of signed 32bit displacement"),
10684 (long) exp
->X_add_number
);
10690 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
10691 else if (exp
->X_op
!= O_constant
10692 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
10693 && exp_seg
!= absolute_section
10694 && exp_seg
!= text_section
10695 && exp_seg
!= data_section
10696 && exp_seg
!= bss_section
10697 && exp_seg
!= undefined_section
10698 && !bfd_is_com_section (exp_seg
))
10700 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
10705 if (current_templates
->start
->opcode_modifier
.jump
== JUMP_BYTE
10706 /* Constants get taken care of by optimize_disp(). */
10707 && exp
->X_op
!= O_constant
)
10708 i
.types
[this_operand
].bitfield
.disp8
= 1;
10710 /* Check if this is a displacement only operand. */
10711 bigdisp
= i
.types
[this_operand
];
10712 bigdisp
.bitfield
.disp8
= 0;
10713 bigdisp
.bitfield
.disp16
= 0;
10714 bigdisp
.bitfield
.disp32
= 0;
10715 bigdisp
.bitfield
.disp32s
= 0;
10716 bigdisp
.bitfield
.disp64
= 0;
10717 if (operand_type_all_zero (&bigdisp
))
10718 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
10724 /* Return the active addressing mode, taking address override and
10725 registers forming the address into consideration. Update the
10726 address override prefix if necessary. */
10728 static enum flag_code
10729 i386_addressing_mode (void)
10731 enum flag_code addr_mode
;
10733 if (i
.prefix
[ADDR_PREFIX
])
10734 addr_mode
= flag_code
== CODE_32BIT
? CODE_16BIT
: CODE_32BIT
;
10735 else if (flag_code
== CODE_16BIT
10736 && current_templates
->start
->cpu_flags
.bitfield
.cpumpx
10737 /* Avoid replacing the "16-bit addressing not allowed" diagnostic
10738 from md_assemble() by "is not a valid base/index expression"
10739 when there is a base and/or index. */
10740 && !i
.types
[this_operand
].bitfield
.baseindex
)
10742 /* MPX insn memory operands with neither base nor index must be forced
10743 to use 32-bit addressing in 16-bit mode. */
10744 addr_mode
= CODE_32BIT
;
10745 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
10747 gas_assert (!i
.types
[this_operand
].bitfield
.disp16
);
10748 gas_assert (!i
.types
[this_operand
].bitfield
.disp32
);
10752 addr_mode
= flag_code
;
10754 #if INFER_ADDR_PREFIX
10755 if (i
.mem_operands
== 0)
10757 /* Infer address prefix from the first memory operand. */
10758 const reg_entry
*addr_reg
= i
.base_reg
;
10760 if (addr_reg
== NULL
)
10761 addr_reg
= i
.index_reg
;
10765 if (addr_reg
->reg_type
.bitfield
.dword
)
10766 addr_mode
= CODE_32BIT
;
10767 else if (flag_code
!= CODE_64BIT
10768 && addr_reg
->reg_type
.bitfield
.word
)
10769 addr_mode
= CODE_16BIT
;
10771 if (addr_mode
!= flag_code
)
10773 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
10775 /* Change the size of any displacement too. At most one
10776 of Disp16 or Disp32 is set.
10777 FIXME. There doesn't seem to be any real need for
10778 separate Disp16 and Disp32 flags. The same goes for
10779 Imm16 and Imm32. Removing them would probably clean
10780 up the code quite a lot. */
10781 if (flag_code
!= CODE_64BIT
10782 && (i
.types
[this_operand
].bitfield
.disp16
10783 || i
.types
[this_operand
].bitfield
.disp32
))
10784 i
.types
[this_operand
]
10785 = operand_type_xor (i
.types
[this_operand
], disp16_32
);
10795 /* Make sure the memory operand we've been dealt is valid.
10796 Return 1 on success, 0 on a failure. */
10799 i386_index_check (const char *operand_string
)
10801 const char *kind
= "base/index";
10802 enum flag_code addr_mode
= i386_addressing_mode ();
10804 if (current_templates
->start
->opcode_modifier
.isstring
10805 && !current_templates
->start
->cpu_flags
.bitfield
.cpupadlock
10806 && (current_templates
->end
[-1].opcode_modifier
.isstring
10807 || i
.mem_operands
))
10809 /* Memory operands of string insns are special in that they only allow
10810 a single register (rDI, rSI, or rBX) as their memory address. */
10811 const reg_entry
*expected_reg
;
10812 static const char *di_si
[][2] =
10818 static const char *bx
[] = { "ebx", "bx", "rbx" };
10820 kind
= "string address";
10822 if (current_templates
->start
->opcode_modifier
.repprefixok
)
10824 int es_op
= current_templates
->end
[-1].opcode_modifier
.isstring
10825 - IS_STRING_ES_OP0
;
10828 if (!current_templates
->end
[-1].operand_types
[0].bitfield
.baseindex
10829 || ((!i
.mem_operands
!= !intel_syntax
)
10830 && current_templates
->end
[-1].operand_types
[1]
10831 .bitfield
.baseindex
))
10833 expected_reg
= hash_find (reg_hash
, di_si
[addr_mode
][op
== es_op
]);
10836 expected_reg
= hash_find (reg_hash
, bx
[addr_mode
]);
10838 if (i
.base_reg
!= expected_reg
10840 || operand_type_check (i
.types
[this_operand
], disp
))
10842 /* The second memory operand must have the same size as
10846 && !((addr_mode
== CODE_64BIT
10847 && i
.base_reg
->reg_type
.bitfield
.qword
)
10848 || (addr_mode
== CODE_32BIT
10849 ? i
.base_reg
->reg_type
.bitfield
.dword
10850 : i
.base_reg
->reg_type
.bitfield
.word
)))
10853 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
10855 intel_syntax
? '[' : '(',
10857 expected_reg
->reg_name
,
10858 intel_syntax
? ']' : ')');
10865 as_bad (_("`%s' is not a valid %s expression"),
10866 operand_string
, kind
);
10871 if (addr_mode
!= CODE_16BIT
)
10873 /* 32-bit/64-bit checks. */
10875 && ((addr_mode
== CODE_64BIT
10876 ? !i
.base_reg
->reg_type
.bitfield
.qword
10877 : !i
.base_reg
->reg_type
.bitfield
.dword
)
10878 || (i
.index_reg
&& i
.base_reg
->reg_num
== RegIP
)
10879 || i
.base_reg
->reg_num
== RegIZ
))
10881 && !i
.index_reg
->reg_type
.bitfield
.xmmword
10882 && !i
.index_reg
->reg_type
.bitfield
.ymmword
10883 && !i
.index_reg
->reg_type
.bitfield
.zmmword
10884 && ((addr_mode
== CODE_64BIT
10885 ? !i
.index_reg
->reg_type
.bitfield
.qword
10886 : !i
.index_reg
->reg_type
.bitfield
.dword
)
10887 || !i
.index_reg
->reg_type
.bitfield
.baseindex
)))
10890 /* bndmk, bndldx, and bndstx have special restrictions. */
10891 if (current_templates
->start
->base_opcode
== 0xf30f1b
10892 || (current_templates
->start
->base_opcode
& ~1) == 0x0f1a)
10894 /* They cannot use RIP-relative addressing. */
10895 if (i
.base_reg
&& i
.base_reg
->reg_num
== RegIP
)
10897 as_bad (_("`%s' cannot be used here"), operand_string
);
10901 /* bndldx and bndstx ignore their scale factor. */
10902 if (current_templates
->start
->base_opcode
!= 0xf30f1b
10903 && i
.log2_scale_factor
)
10904 as_warn (_("register scaling is being ignored here"));
10909 /* 16-bit checks. */
10911 && (!i
.base_reg
->reg_type
.bitfield
.word
10912 || !i
.base_reg
->reg_type
.bitfield
.baseindex
))
10914 && (!i
.index_reg
->reg_type
.bitfield
.word
10915 || !i
.index_reg
->reg_type
.bitfield
.baseindex
10917 && i
.base_reg
->reg_num
< 6
10918 && i
.index_reg
->reg_num
>= 6
10919 && i
.log2_scale_factor
== 0))))
10926 /* Handle vector immediates. */
10929 RC_SAE_immediate (const char *imm_start
)
10931 unsigned int match_found
, j
;
10932 const char *pstr
= imm_start
;
10940 for (j
= 0; j
< ARRAY_SIZE (RC_NamesTable
); j
++)
10942 if (!strncmp (pstr
, RC_NamesTable
[j
].name
, RC_NamesTable
[j
].len
))
10946 rc_op
.type
= RC_NamesTable
[j
].type
;
10947 rc_op
.operand
= this_operand
;
10948 i
.rounding
= &rc_op
;
10952 as_bad (_("duplicated `%s'"), imm_start
);
10955 pstr
+= RC_NamesTable
[j
].len
;
10963 if (*pstr
++ != '}')
10965 as_bad (_("Missing '}': '%s'"), imm_start
);
10968 /* RC/SAE immediate string should contain nothing more. */;
10971 as_bad (_("Junk after '}': '%s'"), imm_start
);
10975 exp
= &im_expressions
[i
.imm_operands
++];
10976 i
.op
[this_operand
].imms
= exp
;
10978 exp
->X_op
= O_constant
;
10979 exp
->X_add_number
= 0;
10980 exp
->X_add_symbol
= (symbolS
*) 0;
10981 exp
->X_op_symbol
= (symbolS
*) 0;
10983 i
.types
[this_operand
].bitfield
.imm8
= 1;
10987 /* Only string instructions can have a second memory operand, so
10988 reduce current_templates to just those if it contains any. */
10990 maybe_adjust_templates (void)
10992 const insn_template
*t
;
10994 gas_assert (i
.mem_operands
== 1);
10996 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
10997 if (t
->opcode_modifier
.isstring
)
11000 if (t
< current_templates
->end
)
11002 static templates aux_templates
;
11003 bfd_boolean recheck
;
11005 aux_templates
.start
= t
;
11006 for (; t
< current_templates
->end
; ++t
)
11007 if (!t
->opcode_modifier
.isstring
)
11009 aux_templates
.end
= t
;
11011 /* Determine whether to re-check the first memory operand. */
11012 recheck
= (aux_templates
.start
!= current_templates
->start
11013 || t
!= current_templates
->end
);
11015 current_templates
= &aux_templates
;
11019 i
.mem_operands
= 0;
11020 if (i
.memop1_string
!= NULL
11021 && i386_index_check (i
.memop1_string
) == 0)
11023 i
.mem_operands
= 1;
11030 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
11034 i386_att_operand (char *operand_string
)
11036 const reg_entry
*r
;
11038 char *op_string
= operand_string
;
11040 if (is_space_char (*op_string
))
11043 /* We check for an absolute prefix (differentiating,
11044 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
11045 if (*op_string
== ABSOLUTE_PREFIX
)
11048 if (is_space_char (*op_string
))
11050 i
.jumpabsolute
= TRUE
;
11053 /* Check if operand is a register. */
11054 if ((r
= parse_register (op_string
, &end_op
)) != NULL
)
11056 i386_operand_type temp
;
11061 /* Check for a segment override by searching for ':' after a
11062 segment register. */
11063 op_string
= end_op
;
11064 if (is_space_char (*op_string
))
11066 if (*op_string
== ':' && r
->reg_type
.bitfield
.class == SReg
)
11068 switch (r
->reg_num
)
11071 i
.seg
[i
.mem_operands
] = &es
;
11074 i
.seg
[i
.mem_operands
] = &cs
;
11077 i
.seg
[i
.mem_operands
] = &ss
;
11080 i
.seg
[i
.mem_operands
] = &ds
;
11083 i
.seg
[i
.mem_operands
] = &fs
;
11086 i
.seg
[i
.mem_operands
] = &gs
;
11090 /* Skip the ':' and whitespace. */
11092 if (is_space_char (*op_string
))
11095 if (!is_digit_char (*op_string
)
11096 && !is_identifier_char (*op_string
)
11097 && *op_string
!= '('
11098 && *op_string
!= ABSOLUTE_PREFIX
)
11100 as_bad (_("bad memory operand `%s'"), op_string
);
11103 /* Handle case of %es:*foo. */
11104 if (*op_string
== ABSOLUTE_PREFIX
)
11107 if (is_space_char (*op_string
))
11109 i
.jumpabsolute
= TRUE
;
11111 goto do_memory_reference
;
11114 /* Handle vector operations. */
11115 if (*op_string
== '{')
11117 op_string
= check_VecOperations (op_string
, NULL
);
11118 if (op_string
== NULL
)
11124 as_bad (_("junk `%s' after register"), op_string
);
11127 temp
= r
->reg_type
;
11128 temp
.bitfield
.baseindex
= 0;
11129 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
11131 i
.types
[this_operand
].bitfield
.unspecified
= 0;
11132 i
.op
[this_operand
].regs
= r
;
11135 else if (*op_string
== REGISTER_PREFIX
)
11137 as_bad (_("bad register name `%s'"), op_string
);
11140 else if (*op_string
== IMMEDIATE_PREFIX
)
11143 if (i
.jumpabsolute
)
11145 as_bad (_("immediate operand illegal with absolute jump"));
11148 if (!i386_immediate (op_string
))
11151 else if (RC_SAE_immediate (operand_string
))
11153 /* If it is a RC or SAE immediate, do nothing. */
11156 else if (is_digit_char (*op_string
)
11157 || is_identifier_char (*op_string
)
11158 || *op_string
== '"'
11159 || *op_string
== '(')
11161 /* This is a memory reference of some sort. */
11164 /* Start and end of displacement string expression (if found). */
11165 char *displacement_string_start
;
11166 char *displacement_string_end
;
11169 do_memory_reference
:
11170 if (i
.mem_operands
== 1 && !maybe_adjust_templates ())
11172 if ((i
.mem_operands
== 1
11173 && !current_templates
->start
->opcode_modifier
.isstring
)
11174 || i
.mem_operands
== 2)
11176 as_bad (_("too many memory references for `%s'"),
11177 current_templates
->start
->name
);
11181 /* Check for base index form. We detect the base index form by
11182 looking for an ')' at the end of the operand, searching
11183 for the '(' matching it, and finding a REGISTER_PREFIX or ','
11185 base_string
= op_string
+ strlen (op_string
);
11187 /* Handle vector operations. */
11188 vop_start
= strchr (op_string
, '{');
11189 if (vop_start
&& vop_start
< base_string
)
11191 if (check_VecOperations (vop_start
, base_string
) == NULL
)
11193 base_string
= vop_start
;
11197 if (is_space_char (*base_string
))
11200 /* If we only have a displacement, set-up for it to be parsed later. */
11201 displacement_string_start
= op_string
;
11202 displacement_string_end
= base_string
+ 1;
11204 if (*base_string
== ')')
11207 unsigned int parens_balanced
= 1;
11208 /* We've already checked that the number of left & right ()'s are
11209 equal, so this loop will not be infinite. */
11213 if (*base_string
== ')')
11215 if (*base_string
== '(')
11218 while (parens_balanced
);
11220 temp_string
= base_string
;
11222 /* Skip past '(' and whitespace. */
11224 if (is_space_char (*base_string
))
11227 if (*base_string
== ','
11228 || ((i
.base_reg
= parse_register (base_string
, &end_op
))
11231 displacement_string_end
= temp_string
;
11233 i
.types
[this_operand
].bitfield
.baseindex
= 1;
11237 if (i
.base_reg
== &bad_reg
)
11239 base_string
= end_op
;
11240 if (is_space_char (*base_string
))
11244 /* There may be an index reg or scale factor here. */
11245 if (*base_string
== ',')
11248 if (is_space_char (*base_string
))
11251 if ((i
.index_reg
= parse_register (base_string
, &end_op
))
11254 if (i
.index_reg
== &bad_reg
)
11256 base_string
= end_op
;
11257 if (is_space_char (*base_string
))
11259 if (*base_string
== ',')
11262 if (is_space_char (*base_string
))
11265 else if (*base_string
!= ')')
11267 as_bad (_("expecting `,' or `)' "
11268 "after index register in `%s'"),
11273 else if (*base_string
== REGISTER_PREFIX
)
11275 end_op
= strchr (base_string
, ',');
11278 as_bad (_("bad register name `%s'"), base_string
);
11282 /* Check for scale factor. */
11283 if (*base_string
!= ')')
11285 char *end_scale
= i386_scale (base_string
);
11290 base_string
= end_scale
;
11291 if (is_space_char (*base_string
))
11293 if (*base_string
!= ')')
11295 as_bad (_("expecting `)' "
11296 "after scale factor in `%s'"),
11301 else if (!i
.index_reg
)
11303 as_bad (_("expecting index register or scale factor "
11304 "after `,'; got '%c'"),
11309 else if (*base_string
!= ')')
11311 as_bad (_("expecting `,' or `)' "
11312 "after base register in `%s'"),
11317 else if (*base_string
== REGISTER_PREFIX
)
11319 end_op
= strchr (base_string
, ',');
11322 as_bad (_("bad register name `%s'"), base_string
);
11327 /* If there's an expression beginning the operand, parse it,
11328 assuming displacement_string_start and
11329 displacement_string_end are meaningful. */
11330 if (displacement_string_start
!= displacement_string_end
)
11332 if (!i386_displacement (displacement_string_start
,
11333 displacement_string_end
))
11337 /* Special case for (%dx) while doing input/output op. */
11339 && i
.base_reg
->reg_type
.bitfield
.instance
== RegD
11340 && i
.base_reg
->reg_type
.bitfield
.word
11341 && i
.index_reg
== 0
11342 && i
.log2_scale_factor
== 0
11343 && i
.seg
[i
.mem_operands
] == 0
11344 && !operand_type_check (i
.types
[this_operand
], disp
))
11346 i
.types
[this_operand
] = i
.base_reg
->reg_type
;
11350 if (i386_index_check (operand_string
) == 0)
11352 i
.flags
[this_operand
] |= Operand_Mem
;
11353 if (i
.mem_operands
== 0)
11354 i
.memop1_string
= xstrdup (operand_string
);
11359 /* It's not a memory operand; argh! */
11360 as_bad (_("invalid char %s beginning operand %d `%s'"),
11361 output_invalid (*op_string
),
11366 return 1; /* Normal return. */
11369 /* Calculate the maximum variable size (i.e., excluding fr_fix)
11370 that an rs_machine_dependent frag may reach. */
11373 i386_frag_max_var (fragS
*frag
)
11375 /* The only relaxable frags are for jumps.
11376 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
11377 gas_assert (frag
->fr_type
== rs_machine_dependent
);
11378 return TYPE_FROM_RELAX_STATE (frag
->fr_subtype
) == UNCOND_JUMP
? 4 : 5;
11381 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11383 elf_symbol_resolved_in_segment_p (symbolS
*fr_symbol
, offsetT fr_var
)
11385 /* STT_GNU_IFUNC symbol must go through PLT. */
11386 if ((symbol_get_bfdsym (fr_symbol
)->flags
11387 & BSF_GNU_INDIRECT_FUNCTION
) != 0)
11390 if (!S_IS_EXTERNAL (fr_symbol
))
11391 /* Symbol may be weak or local. */
11392 return !S_IS_WEAK (fr_symbol
);
11394 /* Global symbols with non-default visibility can't be preempted. */
11395 if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol
)) != STV_DEFAULT
)
11398 if (fr_var
!= NO_RELOC
)
11399 switch ((enum bfd_reloc_code_real
) fr_var
)
11401 case BFD_RELOC_386_PLT32
:
11402 case BFD_RELOC_X86_64_PLT32
:
11403 /* Symbol with PLT relocation may be preempted. */
11409 /* Global symbols with default visibility in a shared library may be
11410 preempted by another definition. */
11415 /* Table 3-2. Macro-Fusible Instructions in Haswell Microarchitecture
11416 Note also work for Skylake and Cascadelake.
11417 ---------------------------------------------------------------------
11418 | JCC | ADD/SUB/CMP | INC/DEC | TEST/AND |
11419 | ------ | ----------- | ------- | -------- |
11421 | Jno | N | N | Y |
11422 | Jc/Jb | Y | N | Y |
11423 | Jae/Jnb | Y | N | Y |
11424 | Je/Jz | Y | Y | Y |
11425 | Jne/Jnz | Y | Y | Y |
11426 | Jna/Jbe | Y | N | Y |
11427 | Ja/Jnbe | Y | N | Y |
11429 | Jns | N | N | Y |
11430 | Jp/Jpe | N | N | Y |
11431 | Jnp/Jpo | N | N | Y |
11432 | Jl/Jnge | Y | Y | Y |
11433 | Jge/Jnl | Y | Y | Y |
11434 | Jle/Jng | Y | Y | Y |
11435 | Jg/Jnle | Y | Y | Y |
11436 --------------------------------------------------------------------- */
11438 i386_macro_fusible_p (enum mf_cmp_kind mf_cmp
, enum mf_jcc_kind mf_jcc
)
11440 if (mf_cmp
== mf_cmp_alu_cmp
)
11441 return ((mf_jcc
>= mf_jcc_jc
&& mf_jcc
<= mf_jcc_jna
)
11442 || mf_jcc
== mf_jcc_jl
|| mf_jcc
== mf_jcc_jle
);
11443 if (mf_cmp
== mf_cmp_incdec
)
11444 return (mf_jcc
== mf_jcc_je
|| mf_jcc
== mf_jcc_jl
11445 || mf_jcc
== mf_jcc_jle
);
11446 if (mf_cmp
== mf_cmp_test_and
)
11451 /* Return the next non-empty frag. */
11454 i386_next_non_empty_frag (fragS
*fragP
)
11456 /* There may be a frag with a ".fill 0" when there is no room in
11457 the current frag for frag_grow in output_insn. */
11458 for (fragP
= fragP
->fr_next
;
11460 && fragP
->fr_type
== rs_fill
11461 && fragP
->fr_fix
== 0);
11462 fragP
= fragP
->fr_next
)
11467 /* Return the next jcc frag after BRANCH_PADDING. */
11470 i386_next_fusible_jcc_frag (fragS
*maybe_cmp_fragP
, fragS
*pad_fragP
)
11472 fragS
*branch_fragP
;
11476 if (pad_fragP
->fr_type
== rs_machine_dependent
11477 && (TYPE_FROM_RELAX_STATE (pad_fragP
->fr_subtype
)
11478 == BRANCH_PADDING
))
11480 branch_fragP
= i386_next_non_empty_frag (pad_fragP
);
11481 if (branch_fragP
->fr_type
!= rs_machine_dependent
)
11483 if (TYPE_FROM_RELAX_STATE (branch_fragP
->fr_subtype
) == COND_JUMP
11484 && i386_macro_fusible_p (maybe_cmp_fragP
->tc_frag_data
.mf_type
,
11485 pad_fragP
->tc_frag_data
.mf_type
))
11486 return branch_fragP
;
11492 /* Classify BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING frags. */
11495 i386_classify_machine_dependent_frag (fragS
*fragP
)
11499 fragS
*branch_fragP
;
11501 unsigned int max_prefix_length
;
11503 if (fragP
->tc_frag_data
.classified
)
11506 /* First scan for BRANCH_PADDING and FUSED_JCC_PADDING. Convert
11507 FUSED_JCC_PADDING and merge BRANCH_PADDING. */
11508 for (next_fragP
= fragP
;
11509 next_fragP
!= NULL
;
11510 next_fragP
= next_fragP
->fr_next
)
11512 next_fragP
->tc_frag_data
.classified
= 1;
11513 if (next_fragP
->fr_type
== rs_machine_dependent
)
11514 switch (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
))
11516 case BRANCH_PADDING
:
11517 /* The BRANCH_PADDING frag must be followed by a branch
11519 branch_fragP
= i386_next_non_empty_frag (next_fragP
);
11520 next_fragP
->tc_frag_data
.u
.branch_fragP
= branch_fragP
;
11522 case FUSED_JCC_PADDING
:
11523 /* Check if this is a fused jcc:
11525 CMP like instruction
11529 cmp_fragP
= i386_next_non_empty_frag (next_fragP
);
11530 pad_fragP
= i386_next_non_empty_frag (cmp_fragP
);
11531 branch_fragP
= i386_next_fusible_jcc_frag (next_fragP
, pad_fragP
);
11534 /* The BRANCH_PADDING frag is merged with the
11535 FUSED_JCC_PADDING frag. */
11536 next_fragP
->tc_frag_data
.u
.branch_fragP
= branch_fragP
;
11537 /* CMP like instruction size. */
11538 next_fragP
->tc_frag_data
.cmp_size
= cmp_fragP
->fr_fix
;
11539 frag_wane (pad_fragP
);
11540 /* Skip to branch_fragP. */
11541 next_fragP
= branch_fragP
;
11543 else if (next_fragP
->tc_frag_data
.max_prefix_length
)
11545 /* Turn FUSED_JCC_PADDING into BRANCH_PREFIX if it isn't
11547 next_fragP
->fr_subtype
11548 = ENCODE_RELAX_STATE (BRANCH_PREFIX
, 0);
11549 next_fragP
->tc_frag_data
.max_bytes
11550 = next_fragP
->tc_frag_data
.max_prefix_length
;
11551 /* This will be updated in the BRANCH_PREFIX scan. */
11552 next_fragP
->tc_frag_data
.max_prefix_length
= 0;
11555 frag_wane (next_fragP
);
11560 /* Stop if there is no BRANCH_PREFIX. */
11561 if (!align_branch_prefix_size
)
11564 /* Scan for BRANCH_PREFIX. */
11565 for (; fragP
!= NULL
; fragP
= fragP
->fr_next
)
11567 if (fragP
->fr_type
!= rs_machine_dependent
11568 || (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
)
11572 /* Count all BRANCH_PREFIX frags before BRANCH_PADDING and
11573 COND_JUMP_PREFIX. */
11574 max_prefix_length
= 0;
11575 for (next_fragP
= fragP
;
11576 next_fragP
!= NULL
;
11577 next_fragP
= next_fragP
->fr_next
)
11579 if (next_fragP
->fr_type
== rs_fill
)
11580 /* Skip rs_fill frags. */
11582 else if (next_fragP
->fr_type
!= rs_machine_dependent
)
11583 /* Stop for all other frags. */
11586 /* rs_machine_dependent frags. */
11587 if (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
11590 /* Count BRANCH_PREFIX frags. */
11591 if (max_prefix_length
>= MAX_FUSED_JCC_PADDING_SIZE
)
11593 max_prefix_length
= MAX_FUSED_JCC_PADDING_SIZE
;
11594 frag_wane (next_fragP
);
11598 += next_fragP
->tc_frag_data
.max_bytes
;
11600 else if ((TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
11602 || (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
11603 == FUSED_JCC_PADDING
))
11605 /* Stop at BRANCH_PADDING and FUSED_JCC_PADDING. */
11606 fragP
->tc_frag_data
.u
.padding_fragP
= next_fragP
;
11610 /* Stop for other rs_machine_dependent frags. */
11614 fragP
->tc_frag_data
.max_prefix_length
= max_prefix_length
;
11616 /* Skip to the next frag. */
11617 fragP
= next_fragP
;
11621 /* Compute padding size for
11624 CMP like instruction
11626 COND_JUMP/UNCOND_JUMP
11631 COND_JUMP/UNCOND_JUMP
11635 i386_branch_padding_size (fragS
*fragP
, offsetT address
)
11637 unsigned int offset
, size
, padding_size
;
11638 fragS
*branch_fragP
= fragP
->tc_frag_data
.u
.branch_fragP
;
11640 /* The start address of the BRANCH_PADDING or FUSED_JCC_PADDING frag. */
11642 address
= fragP
->fr_address
;
11643 address
+= fragP
->fr_fix
;
11645 /* CMP like instrunction size. */
11646 size
= fragP
->tc_frag_data
.cmp_size
;
11648 /* The base size of the branch frag. */
11649 size
+= branch_fragP
->fr_fix
;
11651 /* Add opcode and displacement bytes for the rs_machine_dependent
11653 if (branch_fragP
->fr_type
== rs_machine_dependent
)
11654 size
+= md_relax_table
[branch_fragP
->fr_subtype
].rlx_length
;
11656 /* Check if branch is within boundary and doesn't end at the last
11658 offset
= address
& ((1U << align_branch_power
) - 1);
11659 if ((offset
+ size
) >= (1U << align_branch_power
))
11660 /* Padding needed to avoid crossing boundary. */
11661 padding_size
= (1U << align_branch_power
) - offset
;
11663 /* No padding needed. */
11666 /* The return value may be saved in tc_frag_data.length which is
11668 if (!fits_in_unsigned_byte (padding_size
))
11671 return padding_size
;
11674 /* i386_generic_table_relax_frag()
11676 Handle BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING frags to
11677 grow/shrink padding to align branch frags. Hand others to
11681 i386_generic_table_relax_frag (segT segment
, fragS
*fragP
, long stretch
)
11683 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
11684 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
)
11686 long padding_size
= i386_branch_padding_size (fragP
, 0);
11687 long grow
= padding_size
- fragP
->tc_frag_data
.length
;
11689 /* When the BRANCH_PREFIX frag is used, the computed address
11690 must match the actual address and there should be no padding. */
11691 if (fragP
->tc_frag_data
.padding_address
11692 && (fragP
->tc_frag_data
.padding_address
!= fragP
->fr_address
11696 /* Update the padding size. */
11698 fragP
->tc_frag_data
.length
= padding_size
;
11702 else if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
)
11704 fragS
*padding_fragP
, *next_fragP
;
11705 long padding_size
, left_size
, last_size
;
11707 padding_fragP
= fragP
->tc_frag_data
.u
.padding_fragP
;
11708 if (!padding_fragP
)
11709 /* Use the padding set by the leading BRANCH_PREFIX frag. */
11710 return (fragP
->tc_frag_data
.length
11711 - fragP
->tc_frag_data
.last_length
);
11713 /* Compute the relative address of the padding frag in the very
11714 first time where the BRANCH_PREFIX frag sizes are zero. */
11715 if (!fragP
->tc_frag_data
.padding_address
)
11716 fragP
->tc_frag_data
.padding_address
11717 = padding_fragP
->fr_address
- (fragP
->fr_address
- stretch
);
11719 /* First update the last length from the previous interation. */
11720 left_size
= fragP
->tc_frag_data
.prefix_length
;
11721 for (next_fragP
= fragP
;
11722 next_fragP
!= padding_fragP
;
11723 next_fragP
= next_fragP
->fr_next
)
11724 if (next_fragP
->fr_type
== rs_machine_dependent
11725 && (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
11730 int max
= next_fragP
->tc_frag_data
.max_bytes
;
11734 if (max
> left_size
)
11739 next_fragP
->tc_frag_data
.last_length
= size
;
11743 next_fragP
->tc_frag_data
.last_length
= 0;
11746 /* Check the padding size for the padding frag. */
11747 padding_size
= i386_branch_padding_size
11748 (padding_fragP
, (fragP
->fr_address
11749 + fragP
->tc_frag_data
.padding_address
));
11751 last_size
= fragP
->tc_frag_data
.prefix_length
;
11752 /* Check if there is change from the last interation. */
11753 if (padding_size
== last_size
)
11755 /* Update the expected address of the padding frag. */
11756 padding_fragP
->tc_frag_data
.padding_address
11757 = (fragP
->fr_address
+ padding_size
11758 + fragP
->tc_frag_data
.padding_address
);
11762 if (padding_size
> fragP
->tc_frag_data
.max_prefix_length
)
11764 /* No padding if there is no sufficient room. Clear the
11765 expected address of the padding frag. */
11766 padding_fragP
->tc_frag_data
.padding_address
= 0;
11770 /* Store the expected address of the padding frag. */
11771 padding_fragP
->tc_frag_data
.padding_address
11772 = (fragP
->fr_address
+ padding_size
11773 + fragP
->tc_frag_data
.padding_address
);
11775 fragP
->tc_frag_data
.prefix_length
= padding_size
;
11777 /* Update the length for the current interation. */
11778 left_size
= padding_size
;
11779 for (next_fragP
= fragP
;
11780 next_fragP
!= padding_fragP
;
11781 next_fragP
= next_fragP
->fr_next
)
11782 if (next_fragP
->fr_type
== rs_machine_dependent
11783 && (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
11788 int max
= next_fragP
->tc_frag_data
.max_bytes
;
11792 if (max
> left_size
)
11797 next_fragP
->tc_frag_data
.length
= size
;
11801 next_fragP
->tc_frag_data
.length
= 0;
11804 return (fragP
->tc_frag_data
.length
11805 - fragP
->tc_frag_data
.last_length
);
11807 return relax_frag (segment
, fragP
, stretch
);
11810 /* md_estimate_size_before_relax()
11812 Called just before relax() for rs_machine_dependent frags. The x86
11813 assembler uses these frags to handle variable size jump
11816 Any symbol that is now undefined will not become defined.
11817 Return the correct fr_subtype in the frag.
11818 Return the initial "guess for variable size of frag" to caller.
11819 The guess is actually the growth beyond the fixed part. Whatever
11820 we do to grow the fixed or variable part contributes to our
11824 md_estimate_size_before_relax (fragS
*fragP
, segT segment
)
11826 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
11827 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
11828 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
)
11830 i386_classify_machine_dependent_frag (fragP
);
11831 return fragP
->tc_frag_data
.length
;
11834 /* We've already got fragP->fr_subtype right; all we have to do is
11835 check for un-relaxable symbols. On an ELF system, we can't relax
11836 an externally visible symbol, because it may be overridden by a
11838 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
11839 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11841 && !elf_symbol_resolved_in_segment_p (fragP
->fr_symbol
,
11844 #if defined (OBJ_COFF) && defined (TE_PE)
11845 || (OUTPUT_FLAVOR
== bfd_target_coff_flavour
11846 && S_IS_WEAK (fragP
->fr_symbol
))
11850 /* Symbol is undefined in this segment, or we need to keep a
11851 reloc so that weak symbols can be overridden. */
11852 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
11853 enum bfd_reloc_code_real reloc_type
;
11854 unsigned char *opcode
;
11857 if (fragP
->fr_var
!= NO_RELOC
)
11858 reloc_type
= (enum bfd_reloc_code_real
) fragP
->fr_var
;
11859 else if (size
== 2)
11860 reloc_type
= BFD_RELOC_16_PCREL
;
11861 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11862 else if (need_plt32_p (fragP
->fr_symbol
))
11863 reloc_type
= BFD_RELOC_X86_64_PLT32
;
11866 reloc_type
= BFD_RELOC_32_PCREL
;
11868 old_fr_fix
= fragP
->fr_fix
;
11869 opcode
= (unsigned char *) fragP
->fr_opcode
;
11871 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
11874 /* Make jmp (0xeb) a (d)word displacement jump. */
11876 fragP
->fr_fix
+= size
;
11877 fix_new (fragP
, old_fr_fix
, size
,
11879 fragP
->fr_offset
, 1,
11885 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
11887 /* Negate the condition, and branch past an
11888 unconditional jump. */
11891 /* Insert an unconditional jump. */
11893 /* We added two extra opcode bytes, and have a two byte
11895 fragP
->fr_fix
+= 2 + 2;
11896 fix_new (fragP
, old_fr_fix
+ 2, 2,
11898 fragP
->fr_offset
, 1,
11902 /* Fall through. */
11905 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
11909 fragP
->fr_fix
+= 1;
11910 fixP
= fix_new (fragP
, old_fr_fix
, 1,
11912 fragP
->fr_offset
, 1,
11913 BFD_RELOC_8_PCREL
);
11914 fixP
->fx_signed
= 1;
11918 /* This changes the byte-displacement jump 0x7N
11919 to the (d)word-displacement jump 0x0f,0x8N. */
11920 opcode
[1] = opcode
[0] + 0x10;
11921 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
11922 /* We've added an opcode byte. */
11923 fragP
->fr_fix
+= 1 + size
;
11924 fix_new (fragP
, old_fr_fix
+ 1, size
,
11926 fragP
->fr_offset
, 1,
11931 BAD_CASE (fragP
->fr_subtype
);
11935 return fragP
->fr_fix
- old_fr_fix
;
11938 /* Guess size depending on current relax state. Initially the relax
11939 state will correspond to a short jump and we return 1, because
11940 the variable part of the frag (the branch offset) is one byte
11941 long. However, we can relax a section more than once and in that
11942 case we must either set fr_subtype back to the unrelaxed state,
11943 or return the value for the appropriate branch. */
11944 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
11947 /* Called after relax() is finished.
11949 In: Address of frag.
11950 fr_type == rs_machine_dependent.
11951 fr_subtype is what the address relaxed to.
11953 Out: Any fixSs and constants are set up.
11954 Caller will turn frag into a ".space 0". */
11957 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec ATTRIBUTE_UNUSED
,
11960 unsigned char *opcode
;
11961 unsigned char *where_to_put_displacement
= NULL
;
11962 offsetT target_address
;
11963 offsetT opcode_address
;
11964 unsigned int extension
= 0;
11965 offsetT displacement_from_opcode_start
;
11967 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
11968 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
11969 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
)
11971 /* Generate nop padding. */
11972 unsigned int size
= fragP
->tc_frag_data
.length
;
11975 if (size
> fragP
->tc_frag_data
.max_bytes
)
11981 const char *branch
= "branch";
11982 const char *prefix
= "";
11983 fragS
*padding_fragP
;
11984 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
)
11987 padding_fragP
= fragP
->tc_frag_data
.u
.padding_fragP
;
11988 switch (fragP
->tc_frag_data
.default_prefix
)
11993 case CS_PREFIX_OPCODE
:
11996 case DS_PREFIX_OPCODE
:
11999 case ES_PREFIX_OPCODE
:
12002 case FS_PREFIX_OPCODE
:
12005 case GS_PREFIX_OPCODE
:
12008 case SS_PREFIX_OPCODE
:
12013 msg
= _("%s:%u: add %d%s at 0x%llx to align "
12014 "%s within %d-byte boundary\n");
12016 msg
= _("%s:%u: add additional %d%s at 0x%llx to "
12017 "align %s within %d-byte boundary\n");
12021 padding_fragP
= fragP
;
12022 msg
= _("%s:%u: add %d%s-byte nop at 0x%llx to align "
12023 "%s within %d-byte boundary\n");
12027 switch (padding_fragP
->tc_frag_data
.branch_type
)
12029 case align_branch_jcc
:
12032 case align_branch_fused
:
12033 branch
= "fused jcc";
12035 case align_branch_jmp
:
12038 case align_branch_call
:
12041 case align_branch_indirect
:
12042 branch
= "indiret branch";
12044 case align_branch_ret
:
12051 fprintf (stdout
, msg
,
12052 fragP
->fr_file
, fragP
->fr_line
, size
, prefix
,
12053 (long long) fragP
->fr_address
, branch
,
12054 1 << align_branch_power
);
12056 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
)
12057 memset (fragP
->fr_opcode
,
12058 fragP
->tc_frag_data
.default_prefix
, size
);
12060 i386_generate_nops (fragP
, (char *) fragP
->fr_opcode
,
12062 fragP
->fr_fix
+= size
;
12067 opcode
= (unsigned char *) fragP
->fr_opcode
;
12069 /* Address we want to reach in file space. */
12070 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
12072 /* Address opcode resides at in file space. */
12073 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
12075 /* Displacement from opcode start to fill into instruction. */
12076 displacement_from_opcode_start
= target_address
- opcode_address
;
12078 if ((fragP
->fr_subtype
& BIG
) == 0)
12080 /* Don't have to change opcode. */
12081 extension
= 1; /* 1 opcode + 1 displacement */
12082 where_to_put_displacement
= &opcode
[1];
12086 if (no_cond_jump_promotion
12087 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
12088 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
12089 _("long jump required"));
12091 switch (fragP
->fr_subtype
)
12093 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
12094 extension
= 4; /* 1 opcode + 4 displacement */
12096 where_to_put_displacement
= &opcode
[1];
12099 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
12100 extension
= 2; /* 1 opcode + 2 displacement */
12102 where_to_put_displacement
= &opcode
[1];
12105 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
12106 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
12107 extension
= 5; /* 2 opcode + 4 displacement */
12108 opcode
[1] = opcode
[0] + 0x10;
12109 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
12110 where_to_put_displacement
= &opcode
[2];
12113 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
12114 extension
= 3; /* 2 opcode + 2 displacement */
12115 opcode
[1] = opcode
[0] + 0x10;
12116 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
12117 where_to_put_displacement
= &opcode
[2];
12120 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
12125 where_to_put_displacement
= &opcode
[3];
12129 BAD_CASE (fragP
->fr_subtype
);
12134 /* If size if less then four we are sure that the operand fits,
12135 but if it's 4, then it could be that the displacement is larger
12137 if (DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
) == 4
12139 && ((addressT
) (displacement_from_opcode_start
- extension
12140 + ((addressT
) 1 << 31))
12141 > (((addressT
) 2 << 31) - 1)))
12143 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
12144 _("jump target out of range"));
12145 /* Make us emit 0. */
12146 displacement_from_opcode_start
= extension
;
12148 /* Now put displacement after opcode. */
12149 md_number_to_chars ((char *) where_to_put_displacement
,
12150 (valueT
) (displacement_from_opcode_start
- extension
),
12151 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
12152 fragP
->fr_fix
+= extension
;
12155 /* Apply a fixup (fixP) to segment data, once it has been determined
12156 by our caller that we have all the info we need to fix it up.
12158 Parameter valP is the pointer to the value of the bits.
12160 On the 386, immediates, displacements, and data pointers are all in
12161 the same (little-endian) format, so we don't need to care about which
12162 we are handling. */
12165 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
12167 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
12168 valueT value
= *valP
;
12170 #if !defined (TE_Mach)
12171 if (fixP
->fx_pcrel
)
12173 switch (fixP
->fx_r_type
)
12179 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
12182 case BFD_RELOC_X86_64_32S
:
12183 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
12186 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
12189 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
12194 if (fixP
->fx_addsy
!= NULL
12195 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
12196 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
12197 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
12198 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
12199 && !use_rela_relocations
)
12201 /* This is a hack. There should be a better way to handle this.
12202 This covers for the fact that bfd_install_relocation will
12203 subtract the current location (for partial_inplace, PC relative
12204 relocations); see more below. */
12208 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
12211 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
12213 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12216 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
12218 if ((sym_seg
== seg
12219 || (symbol_section_p (fixP
->fx_addsy
)
12220 && sym_seg
!= absolute_section
))
12221 && !generic_force_reloc (fixP
))
12223 /* Yes, we add the values in twice. This is because
12224 bfd_install_relocation subtracts them out again. I think
12225 bfd_install_relocation is broken, but I don't dare change
12227 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
12231 #if defined (OBJ_COFF) && defined (TE_PE)
12232 /* For some reason, the PE format does not store a
12233 section address offset for a PC relative symbol. */
12234 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
12235 || S_IS_WEAK (fixP
->fx_addsy
))
12236 value
+= md_pcrel_from (fixP
);
12239 #if defined (OBJ_COFF) && defined (TE_PE)
12240 if (fixP
->fx_addsy
!= NULL
12241 && S_IS_WEAK (fixP
->fx_addsy
)
12242 /* PR 16858: Do not modify weak function references. */
12243 && ! fixP
->fx_pcrel
)
12245 #if !defined (TE_PEP)
12246 /* For x86 PE weak function symbols are neither PC-relative
12247 nor do they set S_IS_FUNCTION. So the only reliable way
12248 to detect them is to check the flags of their containing
12250 if (S_GET_SEGMENT (fixP
->fx_addsy
) != NULL
12251 && S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_CODE
)
12255 value
-= S_GET_VALUE (fixP
->fx_addsy
);
12259 /* Fix a few things - the dynamic linker expects certain values here,
12260 and we must not disappoint it. */
12261 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12262 if (IS_ELF
&& fixP
->fx_addsy
)
12263 switch (fixP
->fx_r_type
)
12265 case BFD_RELOC_386_PLT32
:
12266 case BFD_RELOC_X86_64_PLT32
:
12267 /* Make the jump instruction point to the address of the operand.
12268 At runtime we merely add the offset to the actual PLT entry.
12269 NB: Subtract the offset size only for jump instructions. */
12270 if (fixP
->fx_pcrel
)
12274 case BFD_RELOC_386_TLS_GD
:
12275 case BFD_RELOC_386_TLS_LDM
:
12276 case BFD_RELOC_386_TLS_IE_32
:
12277 case BFD_RELOC_386_TLS_IE
:
12278 case BFD_RELOC_386_TLS_GOTIE
:
12279 case BFD_RELOC_386_TLS_GOTDESC
:
12280 case BFD_RELOC_X86_64_TLSGD
:
12281 case BFD_RELOC_X86_64_TLSLD
:
12282 case BFD_RELOC_X86_64_GOTTPOFF
:
12283 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
12284 value
= 0; /* Fully resolved at runtime. No addend. */
12286 case BFD_RELOC_386_TLS_LE
:
12287 case BFD_RELOC_386_TLS_LDO_32
:
12288 case BFD_RELOC_386_TLS_LE_32
:
12289 case BFD_RELOC_X86_64_DTPOFF32
:
12290 case BFD_RELOC_X86_64_DTPOFF64
:
12291 case BFD_RELOC_X86_64_TPOFF32
:
12292 case BFD_RELOC_X86_64_TPOFF64
:
12293 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
12296 case BFD_RELOC_386_TLS_DESC_CALL
:
12297 case BFD_RELOC_X86_64_TLSDESC_CALL
:
12298 value
= 0; /* Fully resolved at runtime. No addend. */
12299 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
12303 case BFD_RELOC_VTABLE_INHERIT
:
12304 case BFD_RELOC_VTABLE_ENTRY
:
12311 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
12313 #endif /* !defined (TE_Mach) */
12315 /* Are we finished with this relocation now? */
12316 if (fixP
->fx_addsy
== NULL
)
12318 #if defined (OBJ_COFF) && defined (TE_PE)
12319 else if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
12322 /* Remember value for tc_gen_reloc. */
12323 fixP
->fx_addnumber
= value
;
12324 /* Clear out the frag for now. */
12328 else if (use_rela_relocations
)
12330 fixP
->fx_no_overflow
= 1;
12331 /* Remember value for tc_gen_reloc. */
12332 fixP
->fx_addnumber
= value
;
12336 md_number_to_chars (p
, value
, fixP
->fx_size
);
12340 md_atof (int type
, char *litP
, int *sizeP
)
12342 /* This outputs the LITTLENUMs in REVERSE order;
12343 in accord with the bigendian 386. */
12344 return ieee_md_atof (type
, litP
, sizeP
, FALSE
);
12347 static char output_invalid_buf
[sizeof (unsigned char) * 2 + 6];
12350 output_invalid (int c
)
12353 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
12356 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
12357 "(0x%x)", (unsigned char) c
);
12358 return output_invalid_buf
;
12361 /* Verify that @r can be used in the current context. */
12363 static bfd_boolean
check_register (const reg_entry
*r
)
12365 if (allow_pseudo_reg
)
12368 if (operand_type_all_zero (&r
->reg_type
))
12371 if ((r
->reg_type
.bitfield
.dword
12372 || (r
->reg_type
.bitfield
.class == SReg
&& r
->reg_num
> 3)
12373 || r
->reg_type
.bitfield
.class == RegCR
12374 || r
->reg_type
.bitfield
.class == RegDR
)
12375 && !cpu_arch_flags
.bitfield
.cpui386
)
12378 if (r
->reg_type
.bitfield
.class == RegTR
12379 && (flag_code
== CODE_64BIT
12380 || !cpu_arch_flags
.bitfield
.cpui386
12381 || cpu_arch_isa_flags
.bitfield
.cpui586
12382 || cpu_arch_isa_flags
.bitfield
.cpui686
))
12385 if (r
->reg_type
.bitfield
.class == RegMMX
&& !cpu_arch_flags
.bitfield
.cpummx
)
12388 if (!cpu_arch_flags
.bitfield
.cpuavx512f
)
12390 if (r
->reg_type
.bitfield
.zmmword
12391 || r
->reg_type
.bitfield
.class == RegMask
)
12394 if (!cpu_arch_flags
.bitfield
.cpuavx
)
12396 if (r
->reg_type
.bitfield
.ymmword
)
12399 if (!cpu_arch_flags
.bitfield
.cpusse
&& r
->reg_type
.bitfield
.xmmword
)
12404 if (r
->reg_type
.bitfield
.class == RegBND
&& !cpu_arch_flags
.bitfield
.cpumpx
)
12407 /* Don't allow fake index register unless allow_index_reg isn't 0. */
12408 if (!allow_index_reg
&& r
->reg_num
== RegIZ
)
12411 /* Upper 16 vector registers are only available with VREX in 64bit
12412 mode, and require EVEX encoding. */
12413 if (r
->reg_flags
& RegVRex
)
12415 if (!cpu_arch_flags
.bitfield
.cpuavx512f
12416 || flag_code
!= CODE_64BIT
)
12419 if (i
.vec_encoding
== vex_encoding_default
)
12420 i
.vec_encoding
= vex_encoding_evex
;
12421 else if (i
.vec_encoding
!= vex_encoding_evex
)
12422 i
.vec_encoding
= vex_encoding_error
;
12425 if (((r
->reg_flags
& (RegRex64
| RegRex
)) || r
->reg_type
.bitfield
.qword
)
12426 && (!cpu_arch_flags
.bitfield
.cpulm
|| r
->reg_type
.bitfield
.class != RegCR
)
12427 && flag_code
!= CODE_64BIT
)
12430 if (r
->reg_type
.bitfield
.class == SReg
&& r
->reg_num
== RegFlat
12437 /* REG_STRING starts *before* REGISTER_PREFIX. */
12439 static const reg_entry
*
12440 parse_real_register (char *reg_string
, char **end_op
)
12442 char *s
= reg_string
;
12444 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
12445 const reg_entry
*r
;
12447 /* Skip possible REGISTER_PREFIX and possible whitespace. */
12448 if (*s
== REGISTER_PREFIX
)
12451 if (is_space_char (*s
))
12454 p
= reg_name_given
;
12455 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
12457 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
12458 return (const reg_entry
*) NULL
;
12462 /* For naked regs, make sure that we are not dealing with an identifier.
12463 This prevents confusing an identifier like `eax_var' with register
12465 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
12466 return (const reg_entry
*) NULL
;
12470 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
12472 /* Handle floating point regs, allowing spaces in the (i) part. */
12473 if (r
== i386_regtab
/* %st is first entry of table */)
12475 if (!cpu_arch_flags
.bitfield
.cpu8087
12476 && !cpu_arch_flags
.bitfield
.cpu287
12477 && !cpu_arch_flags
.bitfield
.cpu387
12478 && !allow_pseudo_reg
)
12479 return (const reg_entry
*) NULL
;
12481 if (is_space_char (*s
))
12486 if (is_space_char (*s
))
12488 if (*s
>= '0' && *s
<= '7')
12490 int fpr
= *s
- '0';
12492 if (is_space_char (*s
))
12497 r
= (const reg_entry
*) hash_find (reg_hash
, "st(0)");
12502 /* We have "%st(" then garbage. */
12503 return (const reg_entry
*) NULL
;
12507 return r
&& check_register (r
) ? r
: NULL
;
12510 /* REG_STRING starts *before* REGISTER_PREFIX. */
12512 static const reg_entry
*
12513 parse_register (char *reg_string
, char **end_op
)
12515 const reg_entry
*r
;
12517 if (*reg_string
== REGISTER_PREFIX
|| allow_naked_reg
)
12518 r
= parse_real_register (reg_string
, end_op
);
12523 char *save
= input_line_pointer
;
12527 input_line_pointer
= reg_string
;
12528 c
= get_symbol_name (®_string
);
12529 symbolP
= symbol_find (reg_string
);
12530 if (symbolP
&& S_GET_SEGMENT (symbolP
) == reg_section
)
12532 const expressionS
*e
= symbol_get_value_expression (symbolP
);
12534 know (e
->X_op
== O_register
);
12535 know (e
->X_add_number
>= 0
12536 && (valueT
) e
->X_add_number
< i386_regtab_size
);
12537 r
= i386_regtab
+ e
->X_add_number
;
12538 if (!check_register (r
))
12540 as_bad (_("register '%s%s' cannot be used here"),
12541 register_prefix
, r
->reg_name
);
12544 *end_op
= input_line_pointer
;
12546 *input_line_pointer
= c
;
12547 input_line_pointer
= save
;
12553 i386_parse_name (char *name
, expressionS
*e
, char *nextcharP
)
12555 const reg_entry
*r
;
12556 char *end
= input_line_pointer
;
12559 r
= parse_register (name
, &input_line_pointer
);
12560 if (r
&& end
<= input_line_pointer
)
12562 *nextcharP
= *input_line_pointer
;
12563 *input_line_pointer
= 0;
12566 e
->X_op
= O_register
;
12567 e
->X_add_number
= r
- i386_regtab
;
12570 e
->X_op
= O_illegal
;
12573 input_line_pointer
= end
;
12575 return intel_syntax
? i386_intel_parse_name (name
, e
) : 0;
12579 md_operand (expressionS
*e
)
12582 const reg_entry
*r
;
12584 switch (*input_line_pointer
)
12586 case REGISTER_PREFIX
:
12587 r
= parse_real_register (input_line_pointer
, &end
);
12590 e
->X_op
= O_register
;
12591 e
->X_add_number
= r
- i386_regtab
;
12592 input_line_pointer
= end
;
12597 gas_assert (intel_syntax
);
12598 end
= input_line_pointer
++;
12600 if (*input_line_pointer
== ']')
12602 ++input_line_pointer
;
12603 e
->X_op_symbol
= make_expr_symbol (e
);
12604 e
->X_add_symbol
= NULL
;
12605 e
->X_add_number
= 0;
12610 e
->X_op
= O_absent
;
12611 input_line_pointer
= end
;
12618 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12619 const char *md_shortopts
= "kVQ:sqnO::";
12621 const char *md_shortopts
= "qnO::";
12624 #define OPTION_32 (OPTION_MD_BASE + 0)
12625 #define OPTION_64 (OPTION_MD_BASE + 1)
12626 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
12627 #define OPTION_MARCH (OPTION_MD_BASE + 3)
12628 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
12629 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
12630 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
12631 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
12632 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
12633 #define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 9)
12634 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
12635 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
12636 #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
12637 #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
12638 #define OPTION_X32 (OPTION_MD_BASE + 14)
12639 #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
12640 #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
12641 #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
12642 #define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
12643 #define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
12644 #define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
12645 #define OPTION_MSHARED (OPTION_MD_BASE + 21)
12646 #define OPTION_MAMD64 (OPTION_MD_BASE + 22)
12647 #define OPTION_MINTEL64 (OPTION_MD_BASE + 23)
12648 #define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24)
12649 #define OPTION_X86_USED_NOTE (OPTION_MD_BASE + 25)
12650 #define OPTION_MVEXWIG (OPTION_MD_BASE + 26)
12651 #define OPTION_MALIGN_BRANCH_BOUNDARY (OPTION_MD_BASE + 27)
12652 #define OPTION_MALIGN_BRANCH_PREFIX_SIZE (OPTION_MD_BASE + 28)
12653 #define OPTION_MALIGN_BRANCH (OPTION_MD_BASE + 29)
12654 #define OPTION_MBRANCHES_WITH_32B_BOUNDARIES (OPTION_MD_BASE + 30)
12655 #define OPTION_MLFENCE_AFTER_LOAD (OPTION_MD_BASE + 31)
12656 #define OPTION_MLFENCE_BEFORE_INDIRECT_BRANCH (OPTION_MD_BASE + 32)
12657 #define OPTION_MLFENCE_BEFORE_RET (OPTION_MD_BASE + 33)
12659 struct option md_longopts
[] =
12661 {"32", no_argument
, NULL
, OPTION_32
},
12662 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
12663 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
12664 {"64", no_argument
, NULL
, OPTION_64
},
12666 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12667 {"x32", no_argument
, NULL
, OPTION_X32
},
12668 {"mshared", no_argument
, NULL
, OPTION_MSHARED
},
12669 {"mx86-used-note", required_argument
, NULL
, OPTION_X86_USED_NOTE
},
12671 {"divide", no_argument
, NULL
, OPTION_DIVIDE
},
12672 {"march", required_argument
, NULL
, OPTION_MARCH
},
12673 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
12674 {"mmnemonic", required_argument
, NULL
, OPTION_MMNEMONIC
},
12675 {"msyntax", required_argument
, NULL
, OPTION_MSYNTAX
},
12676 {"mindex-reg", no_argument
, NULL
, OPTION_MINDEX_REG
},
12677 {"mnaked-reg", no_argument
, NULL
, OPTION_MNAKED_REG
},
12678 {"msse2avx", no_argument
, NULL
, OPTION_MSSE2AVX
},
12679 {"msse-check", required_argument
, NULL
, OPTION_MSSE_CHECK
},
12680 {"moperand-check", required_argument
, NULL
, OPTION_MOPERAND_CHECK
},
12681 {"mavxscalar", required_argument
, NULL
, OPTION_MAVXSCALAR
},
12682 {"mvexwig", required_argument
, NULL
, OPTION_MVEXWIG
},
12683 {"madd-bnd-prefix", no_argument
, NULL
, OPTION_MADD_BND_PREFIX
},
12684 {"mevexlig", required_argument
, NULL
, OPTION_MEVEXLIG
},
12685 {"mevexwig", required_argument
, NULL
, OPTION_MEVEXWIG
},
12686 # if defined (TE_PE) || defined (TE_PEP)
12687 {"mbig-obj", no_argument
, NULL
, OPTION_MBIG_OBJ
},
12689 {"momit-lock-prefix", required_argument
, NULL
, OPTION_MOMIT_LOCK_PREFIX
},
12690 {"mfence-as-lock-add", required_argument
, NULL
, OPTION_MFENCE_AS_LOCK_ADD
},
12691 {"mrelax-relocations", required_argument
, NULL
, OPTION_MRELAX_RELOCATIONS
},
12692 {"mevexrcig", required_argument
, NULL
, OPTION_MEVEXRCIG
},
12693 {"malign-branch-boundary", required_argument
, NULL
, OPTION_MALIGN_BRANCH_BOUNDARY
},
12694 {"malign-branch-prefix-size", required_argument
, NULL
, OPTION_MALIGN_BRANCH_PREFIX_SIZE
},
12695 {"malign-branch", required_argument
, NULL
, OPTION_MALIGN_BRANCH
},
12696 {"mbranches-within-32B-boundaries", no_argument
, NULL
, OPTION_MBRANCHES_WITH_32B_BOUNDARIES
},
12697 {"mlfence-after-load", required_argument
, NULL
, OPTION_MLFENCE_AFTER_LOAD
},
12698 {"mlfence-before-indirect-branch", required_argument
, NULL
,
12699 OPTION_MLFENCE_BEFORE_INDIRECT_BRANCH
},
12700 {"mlfence-before-ret", required_argument
, NULL
, OPTION_MLFENCE_BEFORE_RET
},
12701 {"mamd64", no_argument
, NULL
, OPTION_MAMD64
},
12702 {"mintel64", no_argument
, NULL
, OPTION_MINTEL64
},
12703 {NULL
, no_argument
, NULL
, 0}
12705 size_t md_longopts_size
= sizeof (md_longopts
);
12708 md_parse_option (int c
, const char *arg
)
12711 char *arch
, *next
, *saved
, *type
;
12716 optimize_align_code
= 0;
12720 quiet_warnings
= 1;
12723 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12724 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
12725 should be emitted or not. FIXME: Not implemented. */
12727 if ((arg
[0] != 'y' && arg
[0] != 'n') || arg
[1])
12731 /* -V: SVR4 argument to print version ID. */
12733 print_version_id ();
12736 /* -k: Ignore for FreeBSD compatibility. */
12741 /* -s: On i386 Solaris, this tells the native assembler to use
12742 .stab instead of .stab.excl. We always use .stab anyhow. */
12745 case OPTION_MSHARED
:
12749 case OPTION_X86_USED_NOTE
:
12750 if (strcasecmp (arg
, "yes") == 0)
12752 else if (strcasecmp (arg
, "no") == 0)
12755 as_fatal (_("invalid -mx86-used-note= option: `%s'"), arg
);
12760 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
12761 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
12764 const char **list
, **l
;
12766 list
= bfd_target_list ();
12767 for (l
= list
; *l
!= NULL
; l
++)
12768 if (CONST_STRNEQ (*l
, "elf64-x86-64")
12769 || strcmp (*l
, "coff-x86-64") == 0
12770 || strcmp (*l
, "pe-x86-64") == 0
12771 || strcmp (*l
, "pei-x86-64") == 0
12772 || strcmp (*l
, "mach-o-x86-64") == 0)
12774 default_arch
= "x86_64";
12778 as_fatal (_("no compiled in support for x86_64"));
12784 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12788 const char **list
, **l
;
12790 list
= bfd_target_list ();
12791 for (l
= list
; *l
!= NULL
; l
++)
12792 if (CONST_STRNEQ (*l
, "elf32-x86-64"))
12794 default_arch
= "x86_64:32";
12798 as_fatal (_("no compiled in support for 32bit x86_64"));
12802 as_fatal (_("32bit x86_64 is only supported for ELF"));
12807 default_arch
= "i386";
12810 case OPTION_DIVIDE
:
12811 #ifdef SVR4_COMMENT_CHARS
12816 n
= XNEWVEC (char, strlen (i386_comment_chars
) + 1);
12818 for (s
= i386_comment_chars
; *s
!= '\0'; s
++)
12822 i386_comment_chars
= n
;
12828 saved
= xstrdup (arg
);
12830 /* Allow -march=+nosse. */
12836 as_fatal (_("invalid -march= option: `%s'"), arg
);
12837 next
= strchr (arch
, '+');
12840 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
12842 if (strcmp (arch
, cpu_arch
[j
].name
) == 0)
12845 if (! cpu_arch
[j
].flags
.bitfield
.cpui386
)
12848 cpu_arch_name
= cpu_arch
[j
].name
;
12849 cpu_sub_arch_name
= NULL
;
12850 cpu_arch_flags
= cpu_arch
[j
].flags
;
12851 cpu_arch_isa
= cpu_arch
[j
].type
;
12852 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
12853 if (!cpu_arch_tune_set
)
12855 cpu_arch_tune
= cpu_arch_isa
;
12856 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
12860 else if (*cpu_arch
[j
].name
== '.'
12861 && strcmp (arch
, cpu_arch
[j
].name
+ 1) == 0)
12863 /* ISA extension. */
12864 i386_cpu_flags flags
;
12866 flags
= cpu_flags_or (cpu_arch_flags
,
12867 cpu_arch
[j
].flags
);
12869 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
12871 if (cpu_sub_arch_name
)
12873 char *name
= cpu_sub_arch_name
;
12874 cpu_sub_arch_name
= concat (name
,
12876 (const char *) NULL
);
12880 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
12881 cpu_arch_flags
= flags
;
12882 cpu_arch_isa_flags
= flags
;
12886 = cpu_flags_or (cpu_arch_isa_flags
,
12887 cpu_arch
[j
].flags
);
12892 if (j
>= ARRAY_SIZE (cpu_arch
))
12894 /* Disable an ISA extension. */
12895 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
12896 if (strcmp (arch
, cpu_noarch
[j
].name
) == 0)
12898 i386_cpu_flags flags
;
12900 flags
= cpu_flags_and_not (cpu_arch_flags
,
12901 cpu_noarch
[j
].flags
);
12902 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
12904 if (cpu_sub_arch_name
)
12906 char *name
= cpu_sub_arch_name
;
12907 cpu_sub_arch_name
= concat (arch
,
12908 (const char *) NULL
);
12912 cpu_sub_arch_name
= xstrdup (arch
);
12913 cpu_arch_flags
= flags
;
12914 cpu_arch_isa_flags
= flags
;
12919 if (j
>= ARRAY_SIZE (cpu_noarch
))
12920 j
= ARRAY_SIZE (cpu_arch
);
12923 if (j
>= ARRAY_SIZE (cpu_arch
))
12924 as_fatal (_("invalid -march= option: `%s'"), arg
);
12928 while (next
!= NULL
);
12934 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
12935 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
12937 if (strcmp (arg
, cpu_arch
[j
].name
) == 0)
12939 cpu_arch_tune_set
= 1;
12940 cpu_arch_tune
= cpu_arch
[j
].type
;
12941 cpu_arch_tune_flags
= cpu_arch
[j
].flags
;
12945 if (j
>= ARRAY_SIZE (cpu_arch
))
12946 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
12949 case OPTION_MMNEMONIC
:
12950 if (strcasecmp (arg
, "att") == 0)
12951 intel_mnemonic
= 0;
12952 else if (strcasecmp (arg
, "intel") == 0)
12953 intel_mnemonic
= 1;
12955 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg
);
12958 case OPTION_MSYNTAX
:
12959 if (strcasecmp (arg
, "att") == 0)
12961 else if (strcasecmp (arg
, "intel") == 0)
12964 as_fatal (_("invalid -msyntax= option: `%s'"), arg
);
12967 case OPTION_MINDEX_REG
:
12968 allow_index_reg
= 1;
12971 case OPTION_MNAKED_REG
:
12972 allow_naked_reg
= 1;
12975 case OPTION_MSSE2AVX
:
12979 case OPTION_MSSE_CHECK
:
12980 if (strcasecmp (arg
, "error") == 0)
12981 sse_check
= check_error
;
12982 else if (strcasecmp (arg
, "warning") == 0)
12983 sse_check
= check_warning
;
12984 else if (strcasecmp (arg
, "none") == 0)
12985 sse_check
= check_none
;
12987 as_fatal (_("invalid -msse-check= option: `%s'"), arg
);
12990 case OPTION_MOPERAND_CHECK
:
12991 if (strcasecmp (arg
, "error") == 0)
12992 operand_check
= check_error
;
12993 else if (strcasecmp (arg
, "warning") == 0)
12994 operand_check
= check_warning
;
12995 else if (strcasecmp (arg
, "none") == 0)
12996 operand_check
= check_none
;
12998 as_fatal (_("invalid -moperand-check= option: `%s'"), arg
);
13001 case OPTION_MAVXSCALAR
:
13002 if (strcasecmp (arg
, "128") == 0)
13003 avxscalar
= vex128
;
13004 else if (strcasecmp (arg
, "256") == 0)
13005 avxscalar
= vex256
;
13007 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg
);
13010 case OPTION_MVEXWIG
:
13011 if (strcmp (arg
, "0") == 0)
13013 else if (strcmp (arg
, "1") == 0)
13016 as_fatal (_("invalid -mvexwig= option: `%s'"), arg
);
13019 case OPTION_MADD_BND_PREFIX
:
13020 add_bnd_prefix
= 1;
13023 case OPTION_MEVEXLIG
:
13024 if (strcmp (arg
, "128") == 0)
13025 evexlig
= evexl128
;
13026 else if (strcmp (arg
, "256") == 0)
13027 evexlig
= evexl256
;
13028 else if (strcmp (arg
, "512") == 0)
13029 evexlig
= evexl512
;
13031 as_fatal (_("invalid -mevexlig= option: `%s'"), arg
);
13034 case OPTION_MEVEXRCIG
:
13035 if (strcmp (arg
, "rne") == 0)
13037 else if (strcmp (arg
, "rd") == 0)
13039 else if (strcmp (arg
, "ru") == 0)
13041 else if (strcmp (arg
, "rz") == 0)
13044 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg
);
13047 case OPTION_MEVEXWIG
:
13048 if (strcmp (arg
, "0") == 0)
13050 else if (strcmp (arg
, "1") == 0)
13053 as_fatal (_("invalid -mevexwig= option: `%s'"), arg
);
13056 # if defined (TE_PE) || defined (TE_PEP)
13057 case OPTION_MBIG_OBJ
:
13062 case OPTION_MOMIT_LOCK_PREFIX
:
13063 if (strcasecmp (arg
, "yes") == 0)
13064 omit_lock_prefix
= 1;
13065 else if (strcasecmp (arg
, "no") == 0)
13066 omit_lock_prefix
= 0;
13068 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg
);
13071 case OPTION_MFENCE_AS_LOCK_ADD
:
13072 if (strcasecmp (arg
, "yes") == 0)
13074 else if (strcasecmp (arg
, "no") == 0)
13077 as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg
);
13080 case OPTION_MLFENCE_AFTER_LOAD
:
13081 if (strcasecmp (arg
, "yes") == 0)
13082 lfence_after_load
= 1;
13083 else if (strcasecmp (arg
, "no") == 0)
13084 lfence_after_load
= 0;
13086 as_fatal (_("invalid -mlfence-after-load= option: `%s'"), arg
);
13089 case OPTION_MLFENCE_BEFORE_INDIRECT_BRANCH
:
13090 if (strcasecmp (arg
, "all") == 0)
13092 lfence_before_indirect_branch
= lfence_branch_all
;
13093 if (lfence_before_ret
== lfence_before_ret_none
)
13094 lfence_before_ret
= lfence_before_ret_shl
;
13096 else if (strcasecmp (arg
, "memory") == 0)
13097 lfence_before_indirect_branch
= lfence_branch_memory
;
13098 else if (strcasecmp (arg
, "register") == 0)
13099 lfence_before_indirect_branch
= lfence_branch_register
;
13100 else if (strcasecmp (arg
, "none") == 0)
13101 lfence_before_indirect_branch
= lfence_branch_none
;
13103 as_fatal (_("invalid -mlfence-before-indirect-branch= option: `%s'"),
13107 case OPTION_MLFENCE_BEFORE_RET
:
13108 if (strcasecmp (arg
, "or") == 0)
13109 lfence_before_ret
= lfence_before_ret_or
;
13110 else if (strcasecmp (arg
, "not") == 0)
13111 lfence_before_ret
= lfence_before_ret_not
;
13112 else if (strcasecmp (arg
, "shl") == 0 || strcasecmp (arg
, "yes") == 0)
13113 lfence_before_ret
= lfence_before_ret_shl
;
13114 else if (strcasecmp (arg
, "none") == 0)
13115 lfence_before_ret
= lfence_before_ret_none
;
13117 as_fatal (_("invalid -mlfence-before-ret= option: `%s'"),
13121 case OPTION_MRELAX_RELOCATIONS
:
13122 if (strcasecmp (arg
, "yes") == 0)
13123 generate_relax_relocations
= 1;
13124 else if (strcasecmp (arg
, "no") == 0)
13125 generate_relax_relocations
= 0;
13127 as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg
);
13130 case OPTION_MALIGN_BRANCH_BOUNDARY
:
13133 long int align
= strtoul (arg
, &end
, 0);
13138 align_branch_power
= 0;
13141 else if (align
>= 16)
13144 for (align_power
= 0;
13146 align
>>= 1, align_power
++)
13148 /* Limit alignment power to 31. */
13149 if (align
== 1 && align_power
< 32)
13151 align_branch_power
= align_power
;
13156 as_fatal (_("invalid -malign-branch-boundary= value: %s"), arg
);
13160 case OPTION_MALIGN_BRANCH_PREFIX_SIZE
:
13163 int align
= strtoul (arg
, &end
, 0);
13164 /* Some processors only support 5 prefixes. */
13165 if (*end
== '\0' && align
>= 0 && align
< 6)
13167 align_branch_prefix_size
= align
;
13170 as_fatal (_("invalid -malign-branch-prefix-size= value: %s"),
13175 case OPTION_MALIGN_BRANCH
:
13177 saved
= xstrdup (arg
);
13181 next
= strchr (type
, '+');
13184 if (strcasecmp (type
, "jcc") == 0)
13185 align_branch
|= align_branch_jcc_bit
;
13186 else if (strcasecmp (type
, "fused") == 0)
13187 align_branch
|= align_branch_fused_bit
;
13188 else if (strcasecmp (type
, "jmp") == 0)
13189 align_branch
|= align_branch_jmp_bit
;
13190 else if (strcasecmp (type
, "call") == 0)
13191 align_branch
|= align_branch_call_bit
;
13192 else if (strcasecmp (type
, "ret") == 0)
13193 align_branch
|= align_branch_ret_bit
;
13194 else if (strcasecmp (type
, "indirect") == 0)
13195 align_branch
|= align_branch_indirect_bit
;
13197 as_fatal (_("invalid -malign-branch= option: `%s'"), arg
);
13200 while (next
!= NULL
);
13204 case OPTION_MBRANCHES_WITH_32B_BOUNDARIES
:
13205 align_branch_power
= 5;
13206 align_branch_prefix_size
= 5;
13207 align_branch
= (align_branch_jcc_bit
13208 | align_branch_fused_bit
13209 | align_branch_jmp_bit
);
13212 case OPTION_MAMD64
:
13216 case OPTION_MINTEL64
:
13224 /* Turn off -Os. */
13225 optimize_for_space
= 0;
13227 else if (*arg
== 's')
13229 optimize_for_space
= 1;
13230 /* Turn on all encoding optimizations. */
13231 optimize
= INT_MAX
;
13235 optimize
= atoi (arg
);
13236 /* Turn off -Os. */
13237 optimize_for_space
= 0;
13247 #define MESSAGE_TEMPLATE \
13251 output_message (FILE *stream
, char *p
, char *message
, char *start
,
13252 int *left_p
, const char *name
, int len
)
13254 int size
= sizeof (MESSAGE_TEMPLATE
);
13255 int left
= *left_p
;
13257 /* Reserve 2 spaces for ", " or ",\0" */
13260 /* Check if there is any room. */
13268 p
= mempcpy (p
, name
, len
);
13272 /* Output the current message now and start a new one. */
13275 fprintf (stream
, "%s\n", message
);
13277 left
= size
- (start
- message
) - len
- 2;
13279 gas_assert (left
>= 0);
13281 p
= mempcpy (p
, name
, len
);
13289 show_arch (FILE *stream
, int ext
, int check
)
13291 static char message
[] = MESSAGE_TEMPLATE
;
13292 char *start
= message
+ 27;
13294 int size
= sizeof (MESSAGE_TEMPLATE
);
13301 left
= size
- (start
- message
);
13302 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
13304 /* Should it be skipped? */
13305 if (cpu_arch
[j
].skip
)
13308 name
= cpu_arch
[j
].name
;
13309 len
= cpu_arch
[j
].len
;
13312 /* It is an extension. Skip if we aren't asked to show it. */
13323 /* It is an processor. Skip if we show only extension. */
13326 else if (check
&& ! cpu_arch
[j
].flags
.bitfield
.cpui386
)
13328 /* It is an impossible processor - skip. */
13332 p
= output_message (stream
, p
, message
, start
, &left
, name
, len
);
13335 /* Display disabled extensions. */
13337 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
13339 name
= cpu_noarch
[j
].name
;
13340 len
= cpu_noarch
[j
].len
;
13341 p
= output_message (stream
, p
, message
, start
, &left
, name
,
13346 fprintf (stream
, "%s\n", message
);
13350 md_show_usage (FILE *stream
)
13352 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13353 fprintf (stream
, _("\
13354 -Qy, -Qn ignored\n\
13355 -V print assembler version number\n\
13358 fprintf (stream
, _("\
13359 -n Do not optimize code alignment\n\
13360 -q quieten some warnings\n"));
13361 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13362 fprintf (stream
, _("\
13365 #if defined BFD64 && (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
13366 || defined (TE_PE) || defined (TE_PEP))
13367 fprintf (stream
, _("\
13368 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
13370 #ifdef SVR4_COMMENT_CHARS
13371 fprintf (stream
, _("\
13372 --divide do not treat `/' as a comment character\n"));
13374 fprintf (stream
, _("\
13375 --divide ignored\n"));
13377 fprintf (stream
, _("\
13378 -march=CPU[,+EXTENSION...]\n\
13379 generate code for CPU and EXTENSION, CPU is one of:\n"));
13380 show_arch (stream
, 0, 1);
13381 fprintf (stream
, _("\
13382 EXTENSION is combination of:\n"));
13383 show_arch (stream
, 1, 0);
13384 fprintf (stream
, _("\
13385 -mtune=CPU optimize for CPU, CPU is one of:\n"));
13386 show_arch (stream
, 0, 0);
13387 fprintf (stream
, _("\
13388 -msse2avx encode SSE instructions with VEX prefix\n"));
13389 fprintf (stream
, _("\
13390 -msse-check=[none|error|warning] (default: warning)\n\
13391 check SSE instructions\n"));
13392 fprintf (stream
, _("\
13393 -moperand-check=[none|error|warning] (default: warning)\n\
13394 check operand combinations for validity\n"));
13395 fprintf (stream
, _("\
13396 -mavxscalar=[128|256] (default: 128)\n\
13397 encode scalar AVX instructions with specific vector\n\
13399 fprintf (stream
, _("\
13400 -mvexwig=[0|1] (default: 0)\n\
13401 encode VEX instructions with specific VEX.W value\n\
13402 for VEX.W bit ignored instructions\n"));
13403 fprintf (stream
, _("\
13404 -mevexlig=[128|256|512] (default: 128)\n\
13405 encode scalar EVEX instructions with specific vector\n\
13407 fprintf (stream
, _("\
13408 -mevexwig=[0|1] (default: 0)\n\
13409 encode EVEX instructions with specific EVEX.W value\n\
13410 for EVEX.W bit ignored instructions\n"));
13411 fprintf (stream
, _("\
13412 -mevexrcig=[rne|rd|ru|rz] (default: rne)\n\
13413 encode EVEX instructions with specific EVEX.RC value\n\
13414 for SAE-only ignored instructions\n"));
13415 fprintf (stream
, _("\
13416 -mmnemonic=[att|intel] "));
13417 if (SYSV386_COMPAT
)
13418 fprintf (stream
, _("(default: att)\n"));
13420 fprintf (stream
, _("(default: intel)\n"));
13421 fprintf (stream
, _("\
13422 use AT&T/Intel mnemonic\n"));
13423 fprintf (stream
, _("\
13424 -msyntax=[att|intel] (default: att)\n\
13425 use AT&T/Intel syntax\n"));
13426 fprintf (stream
, _("\
13427 -mindex-reg support pseudo index registers\n"));
13428 fprintf (stream
, _("\
13429 -mnaked-reg don't require `%%' prefix for registers\n"));
13430 fprintf (stream
, _("\
13431 -madd-bnd-prefix add BND prefix for all valid branches\n"));
13432 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13433 fprintf (stream
, _("\
13434 -mshared disable branch optimization for shared code\n"));
13435 fprintf (stream
, _("\
13436 -mx86-used-note=[no|yes] "));
13437 if (DEFAULT_X86_USED_NOTE
)
13438 fprintf (stream
, _("(default: yes)\n"));
13440 fprintf (stream
, _("(default: no)\n"));
13441 fprintf (stream
, _("\
13442 generate x86 used ISA and feature properties\n"));
13444 #if defined (TE_PE) || defined (TE_PEP)
13445 fprintf (stream
, _("\
13446 -mbig-obj generate big object files\n"));
13448 fprintf (stream
, _("\
13449 -momit-lock-prefix=[no|yes] (default: no)\n\
13450 strip all lock prefixes\n"));
13451 fprintf (stream
, _("\
13452 -mfence-as-lock-add=[no|yes] (default: no)\n\
13453 encode lfence, mfence and sfence as\n\
13454 lock addl $0x0, (%%{re}sp)\n"));
13455 fprintf (stream
, _("\
13456 -mrelax-relocations=[no|yes] "));
13457 if (DEFAULT_GENERATE_X86_RELAX_RELOCATIONS
)
13458 fprintf (stream
, _("(default: yes)\n"));
13460 fprintf (stream
, _("(default: no)\n"));
13461 fprintf (stream
, _("\
13462 generate relax relocations\n"));
13463 fprintf (stream
, _("\
13464 -malign-branch-boundary=NUM (default: 0)\n\
13465 align branches within NUM byte boundary\n"));
13466 fprintf (stream
, _("\
13467 -malign-branch=TYPE[+TYPE...] (default: jcc+fused+jmp)\n\
13468 TYPE is combination of jcc, fused, jmp, call, ret,\n\
13470 specify types of branches to align\n"));
13471 fprintf (stream
, _("\
13472 -malign-branch-prefix-size=NUM (default: 5)\n\
13473 align branches with NUM prefixes per instruction\n"));
13474 fprintf (stream
, _("\
13475 -mbranches-within-32B-boundaries\n\
13476 align branches within 32 byte boundary\n"));
13477 fprintf (stream
, _("\
13478 -mlfence-after-load=[no|yes] (default: no)\n\
13479 generate lfence after load\n"));
13480 fprintf (stream
, _("\
13481 -mlfence-before-indirect-branch=[none|all|register|memory] (default: none)\n\
13482 generate lfence before indirect near branch\n"));
13483 fprintf (stream
, _("\
13484 -mlfence-before-ret=[none|or|not|shl|yes] (default: none)\n\
13485 generate lfence before ret\n"));
13486 fprintf (stream
, _("\
13487 -mamd64 accept only AMD64 ISA [default]\n"));
13488 fprintf (stream
, _("\
13489 -mintel64 accept only Intel64 ISA\n"));
13492 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
13493 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
13494 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
13496 /* Pick the target format to use. */
13499 i386_target_format (void)
13501 if (!strncmp (default_arch
, "x86_64", 6))
13503 update_code_flag (CODE_64BIT
, 1);
13504 if (default_arch
[6] == '\0')
13505 x86_elf_abi
= X86_64_ABI
;
13507 x86_elf_abi
= X86_64_X32_ABI
;
13509 else if (!strcmp (default_arch
, "i386"))
13510 update_code_flag (CODE_32BIT
, 1);
13511 else if (!strcmp (default_arch
, "iamcu"))
13513 update_code_flag (CODE_32BIT
, 1);
13514 if (cpu_arch_isa
== PROCESSOR_UNKNOWN
)
13516 static const i386_cpu_flags iamcu_flags
= CPU_IAMCU_FLAGS
;
13517 cpu_arch_name
= "iamcu";
13518 cpu_sub_arch_name
= NULL
;
13519 cpu_arch_flags
= iamcu_flags
;
13520 cpu_arch_isa
= PROCESSOR_IAMCU
;
13521 cpu_arch_isa_flags
= iamcu_flags
;
13522 if (!cpu_arch_tune_set
)
13524 cpu_arch_tune
= cpu_arch_isa
;
13525 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
13528 else if (cpu_arch_isa
!= PROCESSOR_IAMCU
)
13529 as_fatal (_("Intel MCU doesn't support `%s' architecture"),
13533 as_fatal (_("unknown architecture"));
13535 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
13536 cpu_arch_isa_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
13537 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
13538 cpu_arch_tune_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
13540 switch (OUTPUT_FLAVOR
)
13542 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
13543 case bfd_target_aout_flavour
:
13544 return AOUT_TARGET_FORMAT
;
13546 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
13547 # if defined (TE_PE) || defined (TE_PEP)
13548 case bfd_target_coff_flavour
:
13549 if (flag_code
== CODE_64BIT
)
13550 return use_big_obj
? "pe-bigobj-x86-64" : "pe-x86-64";
13552 return use_big_obj
? "pe-bigobj-i386" : "pe-i386";
13553 # elif defined (TE_GO32)
13554 case bfd_target_coff_flavour
:
13555 return "coff-go32";
13557 case bfd_target_coff_flavour
:
13558 return "coff-i386";
13561 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
13562 case bfd_target_elf_flavour
:
13564 const char *format
;
13566 switch (x86_elf_abi
)
13569 format
= ELF_TARGET_FORMAT
;
13571 tls_get_addr
= "___tls_get_addr";
13575 use_rela_relocations
= 1;
13578 tls_get_addr
= "__tls_get_addr";
13580 format
= ELF_TARGET_FORMAT64
;
13582 case X86_64_X32_ABI
:
13583 use_rela_relocations
= 1;
13586 tls_get_addr
= "__tls_get_addr";
13588 disallow_64bit_reloc
= 1;
13589 format
= ELF_TARGET_FORMAT32
;
13592 if (cpu_arch_isa
== PROCESSOR_L1OM
)
13594 if (x86_elf_abi
!= X86_64_ABI
)
13595 as_fatal (_("Intel L1OM is 64bit only"));
13596 return ELF_TARGET_L1OM_FORMAT
;
13598 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
13600 if (x86_elf_abi
!= X86_64_ABI
)
13601 as_fatal (_("Intel K1OM is 64bit only"));
13602 return ELF_TARGET_K1OM_FORMAT
;
13604 else if (cpu_arch_isa
== PROCESSOR_IAMCU
)
13606 if (x86_elf_abi
!= I386_ABI
)
13607 as_fatal (_("Intel MCU is 32bit only"));
13608 return ELF_TARGET_IAMCU_FORMAT
;
13614 #if defined (OBJ_MACH_O)
13615 case bfd_target_mach_o_flavour
:
13616 if (flag_code
== CODE_64BIT
)
13618 use_rela_relocations
= 1;
13620 return "mach-o-x86-64";
13623 return "mach-o-i386";
13631 #endif /* OBJ_MAYBE_ more than one */
13634 md_undefined_symbol (char *name
)
13636 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
13637 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
13638 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
13639 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
13643 if (symbol_find (name
))
13644 as_bad (_("GOT already in symbol table"));
13645 GOT_symbol
= symbol_new (name
, undefined_section
,
13646 (valueT
) 0, &zero_address_frag
);
13653 /* Round up a section size to the appropriate boundary. */
13656 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
13658 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
13659 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
13661 /* For a.out, force the section size to be aligned. If we don't do
13662 this, BFD will align it for us, but it will not write out the
13663 final bytes of the section. This may be a bug in BFD, but it is
13664 easier to fix it here since that is how the other a.out targets
13668 align
= bfd_section_alignment (segment
);
13669 size
= ((size
+ (1 << align
) - 1) & (-((valueT
) 1 << align
)));
13676 /* On the i386, PC-relative offsets are relative to the start of the
13677 next instruction. That is, the address of the offset, plus its
13678 size, since the offset is always the last part of the insn. */
13681 md_pcrel_from (fixS
*fixP
)
13683 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
13689 s_bss (int ignore ATTRIBUTE_UNUSED
)
13693 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13695 obj_elf_section_change_hook ();
13697 temp
= get_absolute_expression ();
13698 subseg_set (bss_section
, (subsegT
) temp
);
13699 demand_empty_rest_of_line ();
13704 /* Remember constant directive. */
13707 i386_cons_align (int ignore ATTRIBUTE_UNUSED
)
13709 if (last_insn
.kind
!= last_insn_directive
13710 && (bfd_section_flags (now_seg
) & SEC_CODE
))
13712 last_insn
.seg
= now_seg
;
13713 last_insn
.kind
= last_insn_directive
;
13714 last_insn
.name
= "constant directive";
13715 last_insn
.file
= as_where (&last_insn
.line
);
13716 if (lfence_before_ret
!= lfence_before_ret_none
)
13718 if (lfence_before_indirect_branch
!= lfence_branch_none
)
13719 as_warn (_("constant directive skips -mlfence-before-ret "
13720 "and -mlfence-before-indirect-branch"));
13722 as_warn (_("constant directive skips -mlfence-before-ret"));
13724 else if (lfence_before_indirect_branch
!= lfence_branch_none
)
13725 as_warn (_("constant directive skips -mlfence-before-indirect-branch"));
13730 i386_validate_fix (fixS
*fixp
)
13732 if (fixp
->fx_subsy
)
13734 if (fixp
->fx_subsy
== GOT_symbol
)
13736 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
13740 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13741 if (fixp
->fx_tcbit2
)
13742 fixp
->fx_r_type
= (fixp
->fx_tcbit
13743 ? BFD_RELOC_X86_64_REX_GOTPCRELX
13744 : BFD_RELOC_X86_64_GOTPCRELX
);
13747 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
13752 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
13754 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
13756 fixp
->fx_subsy
= 0;
13759 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13760 else if (!object_64bit
)
13762 if (fixp
->fx_r_type
== BFD_RELOC_386_GOT32
13763 && fixp
->fx_tcbit2
)
13764 fixp
->fx_r_type
= BFD_RELOC_386_GOT32X
;
13770 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
13773 bfd_reloc_code_real_type code
;
13775 switch (fixp
->fx_r_type
)
13777 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13778 case BFD_RELOC_SIZE32
:
13779 case BFD_RELOC_SIZE64
:
13780 if (S_IS_DEFINED (fixp
->fx_addsy
)
13781 && !S_IS_EXTERNAL (fixp
->fx_addsy
))
13783 /* Resolve size relocation against local symbol to size of
13784 the symbol plus addend. */
13785 valueT value
= S_GET_SIZE (fixp
->fx_addsy
) + fixp
->fx_offset
;
13786 if (fixp
->fx_r_type
== BFD_RELOC_SIZE32
13787 && !fits_in_unsigned_long (value
))
13788 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
13789 _("symbol size computation overflow"));
13790 fixp
->fx_addsy
= NULL
;
13791 fixp
->fx_subsy
= NULL
;
13792 md_apply_fix (fixp
, (valueT
*) &value
, NULL
);
13796 /* Fall through. */
13798 case BFD_RELOC_X86_64_PLT32
:
13799 case BFD_RELOC_X86_64_GOT32
:
13800 case BFD_RELOC_X86_64_GOTPCREL
:
13801 case BFD_RELOC_X86_64_GOTPCRELX
:
13802 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
13803 case BFD_RELOC_386_PLT32
:
13804 case BFD_RELOC_386_GOT32
:
13805 case BFD_RELOC_386_GOT32X
:
13806 case BFD_RELOC_386_GOTOFF
:
13807 case BFD_RELOC_386_GOTPC
:
13808 case BFD_RELOC_386_TLS_GD
:
13809 case BFD_RELOC_386_TLS_LDM
:
13810 case BFD_RELOC_386_TLS_LDO_32
:
13811 case BFD_RELOC_386_TLS_IE_32
:
13812 case BFD_RELOC_386_TLS_IE
:
13813 case BFD_RELOC_386_TLS_GOTIE
:
13814 case BFD_RELOC_386_TLS_LE_32
:
13815 case BFD_RELOC_386_TLS_LE
:
13816 case BFD_RELOC_386_TLS_GOTDESC
:
13817 case BFD_RELOC_386_TLS_DESC_CALL
:
13818 case BFD_RELOC_X86_64_TLSGD
:
13819 case BFD_RELOC_X86_64_TLSLD
:
13820 case BFD_RELOC_X86_64_DTPOFF32
:
13821 case BFD_RELOC_X86_64_DTPOFF64
:
13822 case BFD_RELOC_X86_64_GOTTPOFF
:
13823 case BFD_RELOC_X86_64_TPOFF32
:
13824 case BFD_RELOC_X86_64_TPOFF64
:
13825 case BFD_RELOC_X86_64_GOTOFF64
:
13826 case BFD_RELOC_X86_64_GOTPC32
:
13827 case BFD_RELOC_X86_64_GOT64
:
13828 case BFD_RELOC_X86_64_GOTPCREL64
:
13829 case BFD_RELOC_X86_64_GOTPC64
:
13830 case BFD_RELOC_X86_64_GOTPLT64
:
13831 case BFD_RELOC_X86_64_PLTOFF64
:
13832 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
13833 case BFD_RELOC_X86_64_TLSDESC_CALL
:
13834 case BFD_RELOC_RVA
:
13835 case BFD_RELOC_VTABLE_ENTRY
:
13836 case BFD_RELOC_VTABLE_INHERIT
:
13838 case BFD_RELOC_32_SECREL
:
13840 code
= fixp
->fx_r_type
;
13842 case BFD_RELOC_X86_64_32S
:
13843 if (!fixp
->fx_pcrel
)
13845 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
13846 code
= fixp
->fx_r_type
;
13849 /* Fall through. */
13851 if (fixp
->fx_pcrel
)
13853 switch (fixp
->fx_size
)
13856 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
13857 _("can not do %d byte pc-relative relocation"),
13859 code
= BFD_RELOC_32_PCREL
;
13861 case 1: code
= BFD_RELOC_8_PCREL
; break;
13862 case 2: code
= BFD_RELOC_16_PCREL
; break;
13863 case 4: code
= BFD_RELOC_32_PCREL
; break;
13865 case 8: code
= BFD_RELOC_64_PCREL
; break;
13871 switch (fixp
->fx_size
)
13874 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
13875 _("can not do %d byte relocation"),
13877 code
= BFD_RELOC_32
;
13879 case 1: code
= BFD_RELOC_8
; break;
13880 case 2: code
= BFD_RELOC_16
; break;
13881 case 4: code
= BFD_RELOC_32
; break;
13883 case 8: code
= BFD_RELOC_64
; break;
13890 if ((code
== BFD_RELOC_32
13891 || code
== BFD_RELOC_32_PCREL
13892 || code
== BFD_RELOC_X86_64_32S
)
13894 && fixp
->fx_addsy
== GOT_symbol
)
13897 code
= BFD_RELOC_386_GOTPC
;
13899 code
= BFD_RELOC_X86_64_GOTPC32
;
13901 if ((code
== BFD_RELOC_64
|| code
== BFD_RELOC_64_PCREL
)
13903 && fixp
->fx_addsy
== GOT_symbol
)
13905 code
= BFD_RELOC_X86_64_GOTPC64
;
13908 rel
= XNEW (arelent
);
13909 rel
->sym_ptr_ptr
= XNEW (asymbol
*);
13910 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
13912 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
13914 if (!use_rela_relocations
)
13916 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
13917 vtable entry to be used in the relocation's section offset. */
13918 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
13919 rel
->address
= fixp
->fx_offset
;
13920 #if defined (OBJ_COFF) && defined (TE_PE)
13921 else if (fixp
->fx_addsy
&& S_IS_WEAK (fixp
->fx_addsy
))
13922 rel
->addend
= fixp
->fx_addnumber
- (S_GET_VALUE (fixp
->fx_addsy
) * 2);
13927 /* Use the rela in 64bit mode. */
13930 if (disallow_64bit_reloc
)
13933 case BFD_RELOC_X86_64_DTPOFF64
:
13934 case BFD_RELOC_X86_64_TPOFF64
:
13935 case BFD_RELOC_64_PCREL
:
13936 case BFD_RELOC_X86_64_GOTOFF64
:
13937 case BFD_RELOC_X86_64_GOT64
:
13938 case BFD_RELOC_X86_64_GOTPCREL64
:
13939 case BFD_RELOC_X86_64_GOTPC64
:
13940 case BFD_RELOC_X86_64_GOTPLT64
:
13941 case BFD_RELOC_X86_64_PLTOFF64
:
13942 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
13943 _("cannot represent relocation type %s in x32 mode"),
13944 bfd_get_reloc_code_name (code
));
13950 if (!fixp
->fx_pcrel
)
13951 rel
->addend
= fixp
->fx_offset
;
13955 case BFD_RELOC_X86_64_PLT32
:
13956 case BFD_RELOC_X86_64_GOT32
:
13957 case BFD_RELOC_X86_64_GOTPCREL
:
13958 case BFD_RELOC_X86_64_GOTPCRELX
:
13959 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
13960 case BFD_RELOC_X86_64_TLSGD
:
13961 case BFD_RELOC_X86_64_TLSLD
:
13962 case BFD_RELOC_X86_64_GOTTPOFF
:
13963 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
13964 case BFD_RELOC_X86_64_TLSDESC_CALL
:
13965 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
13968 rel
->addend
= (section
->vma
13970 + fixp
->fx_addnumber
13971 + md_pcrel_from (fixp
));
13976 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
13977 if (rel
->howto
== NULL
)
13979 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
13980 _("cannot represent relocation type %s"),
13981 bfd_get_reloc_code_name (code
));
13982 /* Set howto to a garbage value so that we can keep going. */
13983 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
13984 gas_assert (rel
->howto
!= NULL
);
13990 #include "tc-i386-intel.c"
13993 tc_x86_parse_to_dw2regnum (expressionS
*exp
)
13995 int saved_naked_reg
;
13996 char saved_register_dot
;
13998 saved_naked_reg
= allow_naked_reg
;
13999 allow_naked_reg
= 1;
14000 saved_register_dot
= register_chars
['.'];
14001 register_chars
['.'] = '.';
14002 allow_pseudo_reg
= 1;
14003 expression_and_evaluate (exp
);
14004 allow_pseudo_reg
= 0;
14005 register_chars
['.'] = saved_register_dot
;
14006 allow_naked_reg
= saved_naked_reg
;
14008 if (exp
->X_op
== O_register
&& exp
->X_add_number
>= 0)
14010 if ((addressT
) exp
->X_add_number
< i386_regtab_size
)
14012 exp
->X_op
= O_constant
;
14013 exp
->X_add_number
= i386_regtab
[exp
->X_add_number
]
14014 .dw2_regnum
[flag_code
>> 1];
14017 exp
->X_op
= O_illegal
;
14022 tc_x86_frame_initial_instructions (void)
14024 static unsigned int sp_regno
[2];
14026 if (!sp_regno
[flag_code
>> 1])
14028 char *saved_input
= input_line_pointer
;
14029 char sp
[][4] = {"esp", "rsp"};
14032 input_line_pointer
= sp
[flag_code
>> 1];
14033 tc_x86_parse_to_dw2regnum (&exp
);
14034 gas_assert (exp
.X_op
== O_constant
);
14035 sp_regno
[flag_code
>> 1] = exp
.X_add_number
;
14036 input_line_pointer
= saved_input
;
14039 cfi_add_CFA_def_cfa (sp_regno
[flag_code
>> 1], -x86_cie_data_alignment
);
14040 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
14044 x86_dwarf2_addr_size (void)
14046 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
14047 if (x86_elf_abi
== X86_64_X32_ABI
)
14050 return bfd_arch_bits_per_address (stdoutput
) / 8;
14054 i386_elf_section_type (const char *str
, size_t len
)
14056 if (flag_code
== CODE_64BIT
14057 && len
== sizeof ("unwind") - 1
14058 && strncmp (str
, "unwind", 6) == 0)
14059 return SHT_X86_64_UNWIND
;
14066 i386_solaris_fix_up_eh_frame (segT sec
)
14068 if (flag_code
== CODE_64BIT
)
14069 elf_section_type (sec
) = SHT_X86_64_UNWIND
;
14075 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
14079 exp
.X_op
= O_secrel
;
14080 exp
.X_add_symbol
= symbol
;
14081 exp
.X_add_number
= 0;
14082 emit_expr (&exp
, size
);
14086 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
14087 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
14090 x86_64_section_letter (int letter
, const char **ptr_msg
)
14092 if (flag_code
== CODE_64BIT
)
14095 return SHF_X86_64_LARGE
;
14097 *ptr_msg
= _("bad .section directive: want a,l,w,x,M,S,G,T in string");
14100 *ptr_msg
= _("bad .section directive: want a,w,x,M,S,G,T in string");
14105 x86_64_section_word (char *str
, size_t len
)
14107 if (len
== 5 && flag_code
== CODE_64BIT
&& CONST_STRNEQ (str
, "large"))
14108 return SHF_X86_64_LARGE
;
14114 handle_large_common (int small ATTRIBUTE_UNUSED
)
14116 if (flag_code
!= CODE_64BIT
)
14118 s_comm_internal (0, elf_common_parse
);
14119 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
14123 static segT lbss_section
;
14124 asection
*saved_com_section_ptr
= elf_com_section_ptr
;
14125 asection
*saved_bss_section
= bss_section
;
14127 if (lbss_section
== NULL
)
14129 flagword applicable
;
14130 segT seg
= now_seg
;
14131 subsegT subseg
= now_subseg
;
14133 /* The .lbss section is for local .largecomm symbols. */
14134 lbss_section
= subseg_new (".lbss", 0);
14135 applicable
= bfd_applicable_section_flags (stdoutput
);
14136 bfd_set_section_flags (lbss_section
, applicable
& SEC_ALLOC
);
14137 seg_info (lbss_section
)->bss
= 1;
14139 subseg_set (seg
, subseg
);
14142 elf_com_section_ptr
= &_bfd_elf_large_com_section
;
14143 bss_section
= lbss_section
;
14145 s_comm_internal (0, elf_common_parse
);
14147 elf_com_section_ptr
= saved_com_section_ptr
;
14148 bss_section
= saved_bss_section
;
14151 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */