1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011,
5 Free Software Foundation, Inc.
7 This file is part of GAS, the GNU Assembler.
9 GAS is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3, or (at your option)
14 GAS is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GAS; see the file COPYING. If not, write to the Free
21 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
24 /* Intel 80386 machine specific gas.
25 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
26 x86_64 support by Jan Hubicka (jh@suse.cz)
27 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
28 Bugs & suggestions are completely welcome. This is free software.
29 Please help us make it better. */
32 #include "safe-ctype.h"
34 #include "dwarf2dbg.h"
35 #include "dw2gencfi.h"
36 #include "elf/x86-64.h"
37 #include "opcodes/i386-init.h"
39 #ifndef REGISTER_WARNINGS
40 #define REGISTER_WARNINGS 1
43 #ifndef INFER_ADDR_PREFIX
44 #define INFER_ADDR_PREFIX 1
48 #define DEFAULT_ARCH "i386"
53 #define INLINE __inline__
59 /* Prefixes will be emitted in the order defined below.
60 WAIT_PREFIX must be the first prefix since FWAIT is really is an
61 instruction, and so must come before any prefixes.
62 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
63 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
69 #define HLE_PREFIX REP_PREFIX
71 #define REX_PREFIX 6 /* must come last. */
72 #define MAX_PREFIXES 7 /* max prefixes per opcode */
74 /* we define the syntax here (modulo base,index,scale syntax) */
75 #define REGISTER_PREFIX '%'
76 #define IMMEDIATE_PREFIX '$'
77 #define ABSOLUTE_PREFIX '*'
79 /* these are the instruction mnemonic suffixes in AT&T syntax or
80 memory operand size in Intel syntax. */
81 #define WORD_MNEM_SUFFIX 'w'
82 #define BYTE_MNEM_SUFFIX 'b'
83 #define SHORT_MNEM_SUFFIX 's'
84 #define LONG_MNEM_SUFFIX 'l'
85 #define QWORD_MNEM_SUFFIX 'q'
86 #define XMMWORD_MNEM_SUFFIX 'x'
87 #define YMMWORD_MNEM_SUFFIX 'y'
88 /* Intel Syntax. Use a non-ascii letter since since it never appears
90 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
92 #define END_OF_INSN '\0'
95 'templates' is for grouping together 'template' structures for opcodes
96 of the same name. This is only used for storing the insns in the grand
97 ole hash table of insns.
98 The templates themselves start at START and range up to (but not including)
103 const insn_template
*start
;
104 const insn_template
*end
;
108 /* 386 operand encoding bytes: see 386 book for details of this. */
111 unsigned int regmem
; /* codes register or memory operand */
112 unsigned int reg
; /* codes register operand (or extended opcode) */
113 unsigned int mode
; /* how to interpret regmem & reg */
117 /* x86-64 extension prefix. */
118 typedef int rex_byte
;
120 /* 386 opcode byte to code indirect addressing. */
129 /* x86 arch names, types and features */
132 const char *name
; /* arch name */
133 unsigned int len
; /* arch string length */
134 enum processor_type type
; /* arch type */
135 i386_cpu_flags flags
; /* cpu feature flags */
136 unsigned int skip
; /* show_arch should skip this. */
137 unsigned int negated
; /* turn off indicated flags. */
141 static void update_code_flag (int, int);
142 static void set_code_flag (int);
143 static void set_16bit_gcc_code_flag (int);
144 static void set_intel_syntax (int);
145 static void set_intel_mnemonic (int);
146 static void set_allow_index_reg (int);
147 static void set_check (int);
148 static void set_cpu_arch (int);
150 static void pe_directive_secrel (int);
152 static void signed_cons (int);
153 static char *output_invalid (int c
);
154 static int i386_finalize_immediate (segT
, expressionS
*, i386_operand_type
,
156 static int i386_finalize_displacement (segT
, expressionS
*, i386_operand_type
,
158 static int i386_att_operand (char *);
159 static int i386_intel_operand (char *, int);
160 static int i386_intel_simplify (expressionS
*);
161 static int i386_intel_parse_name (const char *, expressionS
*);
162 static const reg_entry
*parse_register (char *, char **);
163 static char *parse_insn (char *, char *);
164 static char *parse_operands (char *, const char *);
165 static void swap_operands (void);
166 static void swap_2_operands (int, int);
167 static void optimize_imm (void);
168 static void optimize_disp (void);
169 static const insn_template
*match_template (void);
170 static int check_string (void);
171 static int process_suffix (void);
172 static int check_byte_reg (void);
173 static int check_long_reg (void);
174 static int check_qword_reg (void);
175 static int check_word_reg (void);
176 static int finalize_imm (void);
177 static int process_operands (void);
178 static const seg_entry
*build_modrm_byte (void);
179 static void output_insn (void);
180 static void output_imm (fragS
*, offsetT
);
181 static void output_disp (fragS
*, offsetT
);
183 static void s_bss (int);
185 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
186 static void handle_large_common (int small ATTRIBUTE_UNUSED
);
189 static const char *default_arch
= DEFAULT_ARCH
;
194 /* VEX prefix is either 2 byte or 3 byte. */
195 unsigned char bytes
[3];
197 /* Destination or source register specifier. */
198 const reg_entry
*register_specifier
;
201 /* 'md_assemble ()' gathers together information and puts it into a
208 const reg_entry
*regs
;
213 operand_size_mismatch
,
214 operand_type_mismatch
,
215 register_type_mismatch
,
216 number_of_operands_mismatch
,
217 invalid_instruction_suffix
,
220 unsupported_with_intel_mnemonic
,
223 invalid_vsib_address
,
224 invalid_vector_register_set
,
225 unsupported_vector_index_register
230 /* TM holds the template for the insn were currently assembling. */
233 /* SUFFIX holds the instruction size suffix for byte, word, dword
234 or qword, if given. */
237 /* OPERANDS gives the number of given operands. */
238 unsigned int operands
;
240 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
241 of given register, displacement, memory operands and immediate
243 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
245 /* TYPES [i] is the type (see above #defines) which tells us how to
246 use OP[i] for the corresponding operand. */
247 i386_operand_type types
[MAX_OPERANDS
];
249 /* Displacement expression, immediate expression, or register for each
251 union i386_op op
[MAX_OPERANDS
];
253 /* Flags for operands. */
254 unsigned int flags
[MAX_OPERANDS
];
255 #define Operand_PCrel 1
257 /* Relocation type for operand */
258 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
260 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
261 the base index byte below. */
262 const reg_entry
*base_reg
;
263 const reg_entry
*index_reg
;
264 unsigned int log2_scale_factor
;
266 /* SEG gives the seg_entries of this insn. They are zero unless
267 explicit segment overrides are given. */
268 const seg_entry
*seg
[2];
270 /* PREFIX holds all the given prefix opcodes (usually null).
271 PREFIXES is the number of prefix opcodes. */
272 unsigned int prefixes
;
273 unsigned char prefix
[MAX_PREFIXES
];
275 /* RM and SIB are the modrm byte and the sib byte where the
276 addressing modes of this insn are encoded. */
282 /* Swap operand in encoding. */
283 unsigned int swap_operand
;
285 /* Prefer 8bit or 32bit displacement in encoding. */
288 disp_encoding_default
= 0,
294 const char *rep_prefix
;
297 const char *hle_prefix
;
300 enum i386_error error
;
303 typedef struct _i386_insn i386_insn
;
305 /* List of chars besides those in app.c:symbol_chars that can start an
306 operand. Used to prevent the scrubber eating vital white-space. */
307 const char extra_symbol_chars
[] = "*%-(["
316 #if (defined (TE_I386AIX) \
317 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
318 && !defined (TE_GNU) \
319 && !defined (TE_LINUX) \
320 && !defined (TE_NACL) \
321 && !defined (TE_NETWARE) \
322 && !defined (TE_FreeBSD) \
323 && !defined (TE_DragonFly) \
324 && !defined (TE_NetBSD)))
325 /* This array holds the chars that always start a comment. If the
326 pre-processor is disabled, these aren't very useful. The option
327 --divide will remove '/' from this list. */
328 const char *i386_comment_chars
= "#/";
329 #define SVR4_COMMENT_CHARS 1
330 #define PREFIX_SEPARATOR '\\'
333 const char *i386_comment_chars
= "#";
334 #define PREFIX_SEPARATOR '/'
337 /* This array holds the chars that only start a comment at the beginning of
338 a line. If the line seems to have the form '# 123 filename'
339 .line and .file directives will appear in the pre-processed output.
340 Note that input_file.c hand checks for '#' at the beginning of the
341 first line of the input file. This is because the compiler outputs
342 #NO_APP at the beginning of its output.
343 Also note that comments started like this one will always work if
344 '/' isn't otherwise defined. */
345 const char line_comment_chars
[] = "#/";
347 const char line_separator_chars
[] = ";";
349 /* Chars that can be used to separate mant from exp in floating point
351 const char EXP_CHARS
[] = "eE";
353 /* Chars that mean this number is a floating point constant
356 const char FLT_CHARS
[] = "fFdDxX";
358 /* Tables for lexical analysis. */
359 static char mnemonic_chars
[256];
360 static char register_chars
[256];
361 static char operand_chars
[256];
362 static char identifier_chars
[256];
363 static char digit_chars
[256];
365 /* Lexical macros. */
366 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
367 #define is_operand_char(x) (operand_chars[(unsigned char) x])
368 #define is_register_char(x) (register_chars[(unsigned char) x])
369 #define is_space_char(x) ((x) == ' ')
370 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
371 #define is_digit_char(x) (digit_chars[(unsigned char) x])
373 /* All non-digit non-letter characters that may occur in an operand. */
374 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
376 /* md_assemble() always leaves the strings it's passed unaltered. To
377 effect this we maintain a stack of saved characters that we've smashed
378 with '\0's (indicating end of strings for various sub-fields of the
379 assembler instruction). */
380 static char save_stack
[32];
381 static char *save_stack_p
;
382 #define END_STRING_AND_SAVE(s) \
383 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
384 #define RESTORE_END_STRING(s) \
385 do { *(s) = *--save_stack_p; } while (0)
387 /* The instruction we're assembling. */
390 /* Possible templates for current insn. */
391 static const templates
*current_templates
;
393 /* Per instruction expressionS buffers: max displacements & immediates. */
394 static expressionS disp_expressions
[MAX_MEMORY_OPERANDS
];
395 static expressionS im_expressions
[MAX_IMMEDIATE_OPERANDS
];
397 /* Current operand we are working on. */
398 static int this_operand
= -1;
400 /* We support four different modes. FLAG_CODE variable is used to distinguish
408 static enum flag_code flag_code
;
409 static unsigned int object_64bit
;
410 static unsigned int disallow_64bit_reloc
;
411 static int use_rela_relocations
= 0;
413 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
414 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
415 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
417 /* The ELF ABI to use. */
425 static enum x86_elf_abi x86_elf_abi
= I386_ABI
;
428 /* The names used to print error messages. */
429 static const char *flag_code_names
[] =
436 /* 1 for intel syntax,
438 static int intel_syntax
= 0;
440 /* 1 for intel mnemonic,
441 0 if att mnemonic. */
442 static int intel_mnemonic
= !SYSV386_COMPAT
;
444 /* 1 if support old (<= 2.8.1) versions of gcc. */
445 static int old_gcc
= OLDGCC_COMPAT
;
447 /* 1 if pseudo registers are permitted. */
448 static int allow_pseudo_reg
= 0;
450 /* 1 if register prefix % not required. */
451 static int allow_naked_reg
= 0;
453 /* 1 if pseudo index register, eiz/riz, is allowed . */
454 static int allow_index_reg
= 0;
456 static enum check_kind
462 sse_check
, operand_check
= check_warning
;
464 /* Register prefix used for error message. */
465 static const char *register_prefix
= "%";
467 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
468 leave, push, and pop instructions so that gcc has the same stack
469 frame as in 32 bit mode. */
470 static char stackop_size
= '\0';
472 /* Non-zero to optimize code alignment. */
473 int optimize_align_code
= 1;
475 /* Non-zero to quieten some warnings. */
476 static int quiet_warnings
= 0;
479 static const char *cpu_arch_name
= NULL
;
480 static char *cpu_sub_arch_name
= NULL
;
482 /* CPU feature flags. */
483 static i386_cpu_flags cpu_arch_flags
= CPU_UNKNOWN_FLAGS
;
485 /* If we have selected a cpu we are generating instructions for. */
486 static int cpu_arch_tune_set
= 0;
488 /* Cpu we are generating instructions for. */
489 enum processor_type cpu_arch_tune
= PROCESSOR_UNKNOWN
;
491 /* CPU feature flags of cpu we are generating instructions for. */
492 static i386_cpu_flags cpu_arch_tune_flags
;
494 /* CPU instruction set architecture used. */
495 enum processor_type cpu_arch_isa
= PROCESSOR_UNKNOWN
;
497 /* CPU feature flags of instruction set architecture used. */
498 i386_cpu_flags cpu_arch_isa_flags
;
500 /* If set, conditional jumps are not automatically promoted to handle
501 larger than a byte offset. */
502 static unsigned int no_cond_jump_promotion
= 0;
504 /* Encode SSE instructions with VEX prefix. */
505 static unsigned int sse2avx
;
507 /* Encode scalar AVX instructions with specific vector length. */
514 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
515 static symbolS
*GOT_symbol
;
517 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
518 unsigned int x86_dwarf2_return_column
;
520 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
521 int x86_cie_data_alignment
;
523 /* Interface to relax_segment.
524 There are 3 major relax states for 386 jump insns because the
525 different types of jumps add different sizes to frags when we're
526 figuring out what sort of jump to choose to reach a given label. */
529 #define UNCOND_JUMP 0
531 #define COND_JUMP86 2
536 #define SMALL16 (SMALL | CODE16)
538 #define BIG16 (BIG | CODE16)
542 #define INLINE __inline__
548 #define ENCODE_RELAX_STATE(type, size) \
549 ((relax_substateT) (((type) << 2) | (size)))
550 #define TYPE_FROM_RELAX_STATE(s) \
552 #define DISP_SIZE_FROM_RELAX_STATE(s) \
553 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
555 /* This table is used by relax_frag to promote short jumps to long
556 ones where necessary. SMALL (short) jumps may be promoted to BIG
557 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
558 don't allow a short jump in a 32 bit code segment to be promoted to
559 a 16 bit offset jump because it's slower (requires data size
560 prefix), and doesn't work, unless the destination is in the bottom
561 64k of the code segment (The top 16 bits of eip are zeroed). */
563 const relax_typeS md_relax_table
[] =
566 1) most positive reach of this state,
567 2) most negative reach of this state,
568 3) how many bytes this mode will have in the variable part of the frag
569 4) which index into the table to try if we can't fit into this one. */
571 /* UNCOND_JUMP states. */
572 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
573 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
574 /* dword jmp adds 4 bytes to frag:
575 0 extra opcode bytes, 4 displacement bytes. */
577 /* word jmp adds 2 byte2 to frag:
578 0 extra opcode bytes, 2 displacement bytes. */
581 /* COND_JUMP states. */
582 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
583 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
584 /* dword conditionals adds 5 bytes to frag:
585 1 extra opcode byte, 4 displacement bytes. */
587 /* word conditionals add 3 bytes to frag:
588 1 extra opcode byte, 2 displacement bytes. */
591 /* COND_JUMP86 states. */
592 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
593 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
594 /* dword conditionals adds 5 bytes to frag:
595 1 extra opcode byte, 4 displacement bytes. */
597 /* word conditionals add 4 bytes to frag:
598 1 displacement byte and a 3 byte long branch insn. */
602 static const arch_entry cpu_arch
[] =
604 /* Do not replace the first two entries - i386_target_format()
605 relies on them being there in this order. */
606 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32
,
607 CPU_GENERIC32_FLAGS
, 0, 0 },
608 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64
,
609 CPU_GENERIC64_FLAGS
, 0, 0 },
610 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN
,
611 CPU_NONE_FLAGS
, 0, 0 },
612 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN
,
613 CPU_I186_FLAGS
, 0, 0 },
614 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN
,
615 CPU_I286_FLAGS
, 0, 0 },
616 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386
,
617 CPU_I386_FLAGS
, 0, 0 },
618 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486
,
619 CPU_I486_FLAGS
, 0, 0 },
620 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM
,
621 CPU_I586_FLAGS
, 0, 0 },
622 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO
,
623 CPU_I686_FLAGS
, 0, 0 },
624 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM
,
625 CPU_I586_FLAGS
, 0, 0 },
626 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO
,
627 CPU_PENTIUMPRO_FLAGS
, 0, 0 },
628 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO
,
629 CPU_P2_FLAGS
, 0, 0 },
630 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO
,
631 CPU_P3_FLAGS
, 0, 0 },
632 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4
,
633 CPU_P4_FLAGS
, 0, 0 },
634 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA
,
635 CPU_CORE_FLAGS
, 0, 0 },
636 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA
,
637 CPU_NOCONA_FLAGS
, 0, 0 },
638 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE
,
639 CPU_CORE_FLAGS
, 1, 0 },
640 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE
,
641 CPU_CORE_FLAGS
, 0, 0 },
642 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2
,
643 CPU_CORE2_FLAGS
, 1, 0 },
644 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2
,
645 CPU_CORE2_FLAGS
, 0, 0 },
646 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7
,
647 CPU_COREI7_FLAGS
, 0, 0 },
648 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM
,
649 CPU_L1OM_FLAGS
, 0, 0 },
650 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM
,
651 CPU_K1OM_FLAGS
, 0, 0 },
652 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6
,
653 CPU_K6_FLAGS
, 0, 0 },
654 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6
,
655 CPU_K6_2_FLAGS
, 0, 0 },
656 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON
,
657 CPU_ATHLON_FLAGS
, 0, 0 },
658 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8
,
659 CPU_K8_FLAGS
, 1, 0 },
660 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8
,
661 CPU_K8_FLAGS
, 0, 0 },
662 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8
,
663 CPU_K8_FLAGS
, 0, 0 },
664 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10
,
665 CPU_AMDFAM10_FLAGS
, 0, 0 },
666 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD
,
667 CPU_BDVER1_FLAGS
, 0, 0 },
668 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD
,
669 CPU_BDVER2_FLAGS
, 0, 0 },
670 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD
,
671 CPU_BDVER3_FLAGS
, 0, 0 },
672 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT
,
673 CPU_BTVER1_FLAGS
, 0, 0 },
674 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT
,
675 CPU_BTVER2_FLAGS
, 0, 0 },
676 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN
,
677 CPU_8087_FLAGS
, 0, 0 },
678 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN
,
679 CPU_287_FLAGS
, 0, 0 },
680 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN
,
681 CPU_387_FLAGS
, 0, 0 },
682 { STRING_COMMA_LEN (".no87"), PROCESSOR_UNKNOWN
,
683 CPU_ANY87_FLAGS
, 0, 1 },
684 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN
,
685 CPU_MMX_FLAGS
, 0, 0 },
686 { STRING_COMMA_LEN (".nommx"), PROCESSOR_UNKNOWN
,
687 CPU_3DNOWA_FLAGS
, 0, 1 },
688 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN
,
689 CPU_SSE_FLAGS
, 0, 0 },
690 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN
,
691 CPU_SSE2_FLAGS
, 0, 0 },
692 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN
,
693 CPU_SSE3_FLAGS
, 0, 0 },
694 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN
,
695 CPU_SSSE3_FLAGS
, 0, 0 },
696 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN
,
697 CPU_SSE4_1_FLAGS
, 0, 0 },
698 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN
,
699 CPU_SSE4_2_FLAGS
, 0, 0 },
700 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN
,
701 CPU_SSE4_2_FLAGS
, 0, 0 },
702 { STRING_COMMA_LEN (".nosse"), PROCESSOR_UNKNOWN
,
703 CPU_ANY_SSE_FLAGS
, 0, 1 },
704 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN
,
705 CPU_AVX_FLAGS
, 0, 0 },
706 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN
,
707 CPU_AVX2_FLAGS
, 0, 0 },
708 { STRING_COMMA_LEN (".noavx"), PROCESSOR_UNKNOWN
,
709 CPU_ANY_AVX_FLAGS
, 0, 1 },
710 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN
,
711 CPU_VMX_FLAGS
, 0, 0 },
712 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN
,
713 CPU_VMFUNC_FLAGS
, 0, 0 },
714 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN
,
715 CPU_SMX_FLAGS
, 0, 0 },
716 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN
,
717 CPU_XSAVE_FLAGS
, 0, 0 },
718 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN
,
719 CPU_XSAVEOPT_FLAGS
, 0, 0 },
720 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN
,
721 CPU_AES_FLAGS
, 0, 0 },
722 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN
,
723 CPU_PCLMUL_FLAGS
, 0, 0 },
724 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN
,
725 CPU_PCLMUL_FLAGS
, 1, 0 },
726 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN
,
727 CPU_FSGSBASE_FLAGS
, 0, 0 },
728 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN
,
729 CPU_RDRND_FLAGS
, 0, 0 },
730 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN
,
731 CPU_F16C_FLAGS
, 0, 0 },
732 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN
,
733 CPU_BMI2_FLAGS
, 0, 0 },
734 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN
,
735 CPU_FMA_FLAGS
, 0, 0 },
736 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN
,
737 CPU_FMA4_FLAGS
, 0, 0 },
738 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN
,
739 CPU_XOP_FLAGS
, 0, 0 },
740 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN
,
741 CPU_LWP_FLAGS
, 0, 0 },
742 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN
,
743 CPU_MOVBE_FLAGS
, 0, 0 },
744 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN
,
745 CPU_CX16_FLAGS
, 0, 0 },
746 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN
,
747 CPU_EPT_FLAGS
, 0, 0 },
748 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN
,
749 CPU_LZCNT_FLAGS
, 0, 0 },
750 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN
,
751 CPU_HLE_FLAGS
, 0, 0 },
752 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN
,
753 CPU_RTM_FLAGS
, 0, 0 },
754 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN
,
755 CPU_INVPCID_FLAGS
, 0, 0 },
756 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN
,
757 CPU_CLFLUSH_FLAGS
, 0, 0 },
758 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN
,
759 CPU_NOP_FLAGS
, 0, 0 },
760 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN
,
761 CPU_SYSCALL_FLAGS
, 0, 0 },
762 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN
,
763 CPU_RDTSCP_FLAGS
, 0, 0 },
764 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN
,
765 CPU_3DNOW_FLAGS
, 0, 0 },
766 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN
,
767 CPU_3DNOWA_FLAGS
, 0, 0 },
768 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN
,
769 CPU_PADLOCK_FLAGS
, 0, 0 },
770 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN
,
771 CPU_SVME_FLAGS
, 1, 0 },
772 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN
,
773 CPU_SVME_FLAGS
, 0, 0 },
774 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN
,
775 CPU_SSE4A_FLAGS
, 0, 0 },
776 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN
,
777 CPU_ABM_FLAGS
, 0, 0 },
778 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN
,
779 CPU_BMI_FLAGS
, 0, 0 },
780 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN
,
781 CPU_TBM_FLAGS
, 0, 0 },
782 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN
,
783 CPU_ADX_FLAGS
, 0, 0 },
784 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN
,
785 CPU_RDSEED_FLAGS
, 0, 0 },
786 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN
,
787 CPU_PRFCHW_FLAGS
, 0, 0 },
788 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN
,
789 CPU_SMAP_FLAGS
, 0, 0 },
793 /* Like s_lcomm_internal in gas/read.c but the alignment string
794 is allowed to be optional. */
797 pe_lcomm_internal (int needs_align
, symbolS
*symbolP
, addressT size
)
804 && *input_line_pointer
== ',')
806 align
= parse_align (needs_align
- 1);
808 if (align
== (addressT
) -1)
823 bss_alloc (symbolP
, size
, align
);
828 pe_lcomm (int needs_align
)
830 s_comm_internal (needs_align
* 2, pe_lcomm_internal
);
834 const pseudo_typeS md_pseudo_table
[] =
836 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
837 {"align", s_align_bytes
, 0},
839 {"align", s_align_ptwo
, 0},
841 {"arch", set_cpu_arch
, 0},
845 {"lcomm", pe_lcomm
, 1},
847 {"ffloat", float_cons
, 'f'},
848 {"dfloat", float_cons
, 'd'},
849 {"tfloat", float_cons
, 'x'},
851 {"slong", signed_cons
, 4},
852 {"noopt", s_ignore
, 0},
853 {"optim", s_ignore
, 0},
854 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
855 {"code16", set_code_flag
, CODE_16BIT
},
856 {"code32", set_code_flag
, CODE_32BIT
},
857 {"code64", set_code_flag
, CODE_64BIT
},
858 {"intel_syntax", set_intel_syntax
, 1},
859 {"att_syntax", set_intel_syntax
, 0},
860 {"intel_mnemonic", set_intel_mnemonic
, 1},
861 {"att_mnemonic", set_intel_mnemonic
, 0},
862 {"allow_index_reg", set_allow_index_reg
, 1},
863 {"disallow_index_reg", set_allow_index_reg
, 0},
864 {"sse_check", set_check
, 0},
865 {"operand_check", set_check
, 1},
866 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
867 {"largecomm", handle_large_common
, 0},
869 {"file", (void (*) (int)) dwarf2_directive_file
, 0},
870 {"loc", dwarf2_directive_loc
, 0},
871 {"loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0},
874 {"secrel32", pe_directive_secrel
, 0},
879 /* For interface with expression (). */
880 extern char *input_line_pointer
;
882 /* Hash table for instruction mnemonic lookup. */
883 static struct hash_control
*op_hash
;
885 /* Hash table for register lookup. */
886 static struct hash_control
*reg_hash
;
889 i386_align_code (fragS
*fragP
, int count
)
891 /* Various efficient no-op patterns for aligning code labels.
892 Note: Don't try to assemble the instructions in the comments.
893 0L and 0w are not legal. */
894 static const char f32_1
[] =
896 static const char f32_2
[] =
897 {0x66,0x90}; /* xchg %ax,%ax */
898 static const char f32_3
[] =
899 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
900 static const char f32_4
[] =
901 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
902 static const char f32_5
[] =
904 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
905 static const char f32_6
[] =
906 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
907 static const char f32_7
[] =
908 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
909 static const char f32_8
[] =
911 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
912 static const char f32_9
[] =
913 {0x89,0xf6, /* movl %esi,%esi */
914 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
915 static const char f32_10
[] =
916 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
917 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
918 static const char f32_11
[] =
919 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
920 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
921 static const char f32_12
[] =
922 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
923 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
924 static const char f32_13
[] =
925 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
926 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
927 static const char f32_14
[] =
928 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
929 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
930 static const char f16_3
[] =
931 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
932 static const char f16_4
[] =
933 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
934 static const char f16_5
[] =
936 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
937 static const char f16_6
[] =
938 {0x89,0xf6, /* mov %si,%si */
939 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
940 static const char f16_7
[] =
941 {0x8d,0x74,0x00, /* lea 0(%si),%si */
942 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
943 static const char f16_8
[] =
944 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
945 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
946 static const char jump_31
[] =
947 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
948 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
949 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
950 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
951 static const char *const f32_patt
[] = {
952 f32_1
, f32_2
, f32_3
, f32_4
, f32_5
, f32_6
, f32_7
, f32_8
,
953 f32_9
, f32_10
, f32_11
, f32_12
, f32_13
, f32_14
955 static const char *const f16_patt
[] = {
956 f32_1
, f32_2
, f16_3
, f16_4
, f16_5
, f16_6
, f16_7
, f16_8
959 static const char alt_3
[] =
961 /* nopl 0(%[re]ax) */
962 static const char alt_4
[] =
963 {0x0f,0x1f,0x40,0x00};
964 /* nopl 0(%[re]ax,%[re]ax,1) */
965 static const char alt_5
[] =
966 {0x0f,0x1f,0x44,0x00,0x00};
967 /* nopw 0(%[re]ax,%[re]ax,1) */
968 static const char alt_6
[] =
969 {0x66,0x0f,0x1f,0x44,0x00,0x00};
970 /* nopl 0L(%[re]ax) */
971 static const char alt_7
[] =
972 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
973 /* nopl 0L(%[re]ax,%[re]ax,1) */
974 static const char alt_8
[] =
975 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
976 /* nopw 0L(%[re]ax,%[re]ax,1) */
977 static const char alt_9
[] =
978 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
979 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
980 static const char alt_10
[] =
981 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
983 nopw %cs:0L(%[re]ax,%[re]ax,1) */
984 static const char alt_long_11
[] =
986 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
989 nopw %cs:0L(%[re]ax,%[re]ax,1) */
990 static const char alt_long_12
[] =
993 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
997 nopw %cs:0L(%[re]ax,%[re]ax,1) */
998 static const char alt_long_13
[] =
1002 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1007 nopw %cs:0L(%[re]ax,%[re]ax,1) */
1008 static const char alt_long_14
[] =
1013 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1019 nopw %cs:0L(%[re]ax,%[re]ax,1) */
1020 static const char alt_long_15
[] =
1026 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1027 /* nopl 0(%[re]ax,%[re]ax,1)
1028 nopw 0(%[re]ax,%[re]ax,1) */
1029 static const char alt_short_11
[] =
1030 {0x0f,0x1f,0x44,0x00,0x00,
1031 0x66,0x0f,0x1f,0x44,0x00,0x00};
1032 /* nopw 0(%[re]ax,%[re]ax,1)
1033 nopw 0(%[re]ax,%[re]ax,1) */
1034 static const char alt_short_12
[] =
1035 {0x66,0x0f,0x1f,0x44,0x00,0x00,
1036 0x66,0x0f,0x1f,0x44,0x00,0x00};
1037 /* nopw 0(%[re]ax,%[re]ax,1)
1039 static const char alt_short_13
[] =
1040 {0x66,0x0f,0x1f,0x44,0x00,0x00,
1041 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1044 static const char alt_short_14
[] =
1045 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
1046 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1048 nopl 0L(%[re]ax,%[re]ax,1) */
1049 static const char alt_short_15
[] =
1050 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
1051 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1052 static const char *const alt_short_patt
[] = {
1053 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
1054 alt_9
, alt_10
, alt_short_11
, alt_short_12
, alt_short_13
,
1055 alt_short_14
, alt_short_15
1057 static const char *const alt_long_patt
[] = {
1058 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
1059 alt_9
, alt_10
, alt_long_11
, alt_long_12
, alt_long_13
,
1060 alt_long_14
, alt_long_15
1063 /* Only align for at least a positive non-zero boundary. */
1064 if (count
<= 0 || count
> MAX_MEM_FOR_RS_ALIGN_CODE
)
1067 /* We need to decide which NOP sequence to use for 32bit and
1068 64bit. When -mtune= is used:
1070 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1071 PROCESSOR_GENERIC32, f32_patt will be used.
1072 2. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
1073 PROCESSOR_CORE, PROCESSOR_CORE2, PROCESSOR_COREI7, and
1074 PROCESSOR_GENERIC64, alt_long_patt will be used.
1075 3. For PROCESSOR_ATHLON, PROCESSOR_K6, PROCESSOR_K8 and
1076 PROCESSOR_AMDFAM10, PROCESSOR_BD and PROCESSOR_BT, alt_short_patt
1079 When -mtune= isn't used, alt_long_patt will be used if
1080 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
1083 When -march= or .arch is used, we can't use anything beyond
1084 cpu_arch_isa_flags. */
1086 if (flag_code
== CODE_16BIT
)
1090 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1092 /* Adjust jump offset. */
1093 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
1096 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1097 f16_patt
[count
- 1], count
);
1101 const char *const *patt
= NULL
;
1103 if (fragP
->tc_frag_data
.isa
== PROCESSOR_UNKNOWN
)
1105 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1106 switch (cpu_arch_tune
)
1108 case PROCESSOR_UNKNOWN
:
1109 /* We use cpu_arch_isa_flags to check if we SHOULD
1110 optimize with nops. */
1111 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1112 patt
= alt_long_patt
;
1116 case PROCESSOR_PENTIUM4
:
1117 case PROCESSOR_NOCONA
:
1118 case PROCESSOR_CORE
:
1119 case PROCESSOR_CORE2
:
1120 case PROCESSOR_COREI7
:
1121 case PROCESSOR_L1OM
:
1122 case PROCESSOR_K1OM
:
1123 case PROCESSOR_GENERIC64
:
1124 patt
= alt_long_patt
;
1127 case PROCESSOR_ATHLON
:
1129 case PROCESSOR_AMDFAM10
:
1132 patt
= alt_short_patt
;
1134 case PROCESSOR_I386
:
1135 case PROCESSOR_I486
:
1136 case PROCESSOR_PENTIUM
:
1137 case PROCESSOR_PENTIUMPRO
:
1138 case PROCESSOR_GENERIC32
:
1145 switch (fragP
->tc_frag_data
.tune
)
1147 case PROCESSOR_UNKNOWN
:
1148 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1149 PROCESSOR_UNKNOWN. */
1153 case PROCESSOR_I386
:
1154 case PROCESSOR_I486
:
1155 case PROCESSOR_PENTIUM
:
1157 case PROCESSOR_ATHLON
:
1159 case PROCESSOR_AMDFAM10
:
1162 case PROCESSOR_GENERIC32
:
1163 /* We use cpu_arch_isa_flags to check if we CAN optimize
1165 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1166 patt
= alt_short_patt
;
1170 case PROCESSOR_PENTIUMPRO
:
1171 case PROCESSOR_PENTIUM4
:
1172 case PROCESSOR_NOCONA
:
1173 case PROCESSOR_CORE
:
1174 case PROCESSOR_CORE2
:
1175 case PROCESSOR_COREI7
:
1176 case PROCESSOR_L1OM
:
1177 case PROCESSOR_K1OM
:
1178 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1179 patt
= alt_long_patt
;
1183 case PROCESSOR_GENERIC64
:
1184 patt
= alt_long_patt
;
1189 if (patt
== f32_patt
)
1191 /* If the padding is less than 15 bytes, we use the normal
1192 ones. Otherwise, we use a jump instruction and adjust
1196 /* For 64bit, the limit is 3 bytes. */
1197 if (flag_code
== CODE_64BIT
1198 && fragP
->tc_frag_data
.isa_flags
.bitfield
.cpulm
)
1203 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1204 patt
[count
- 1], count
);
1207 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1209 /* Adjust jump offset. */
1210 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
1215 /* Maximum length of an instruction is 15 byte. If the
1216 padding is greater than 15 bytes and we don't use jump,
1217 we have to break it into smaller pieces. */
1218 int padding
= count
;
1219 while (padding
> 15)
1222 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
+ padding
,
1227 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1228 patt
[padding
- 1], padding
);
1231 fragP
->fr_var
= count
;
1235 operand_type_all_zero (const union i386_operand_type
*x
)
1237 switch (ARRAY_SIZE(x
->array
))
1246 return !x
->array
[0];
1253 operand_type_set (union i386_operand_type
*x
, unsigned int v
)
1255 switch (ARRAY_SIZE(x
->array
))
1270 operand_type_equal (const union i386_operand_type
*x
,
1271 const union i386_operand_type
*y
)
1273 switch (ARRAY_SIZE(x
->array
))
1276 if (x
->array
[2] != y
->array
[2])
1279 if (x
->array
[1] != y
->array
[1])
1282 return x
->array
[0] == y
->array
[0];
1290 cpu_flags_all_zero (const union i386_cpu_flags
*x
)
1292 switch (ARRAY_SIZE(x
->array
))
1301 return !x
->array
[0];
1308 cpu_flags_set (union i386_cpu_flags
*x
, unsigned int v
)
1310 switch (ARRAY_SIZE(x
->array
))
1325 cpu_flags_equal (const union i386_cpu_flags
*x
,
1326 const union i386_cpu_flags
*y
)
1328 switch (ARRAY_SIZE(x
->array
))
1331 if (x
->array
[2] != y
->array
[2])
1334 if (x
->array
[1] != y
->array
[1])
1337 return x
->array
[0] == y
->array
[0];
1345 cpu_flags_check_cpu64 (i386_cpu_flags f
)
1347 return !((flag_code
== CODE_64BIT
&& f
.bitfield
.cpuno64
)
1348 || (flag_code
!= CODE_64BIT
&& f
.bitfield
.cpu64
));
1351 static INLINE i386_cpu_flags
1352 cpu_flags_and (i386_cpu_flags x
, i386_cpu_flags y
)
1354 switch (ARRAY_SIZE (x
.array
))
1357 x
.array
[2] &= y
.array
[2];
1359 x
.array
[1] &= y
.array
[1];
1361 x
.array
[0] &= y
.array
[0];
1369 static INLINE i386_cpu_flags
1370 cpu_flags_or (i386_cpu_flags x
, i386_cpu_flags y
)
1372 switch (ARRAY_SIZE (x
.array
))
1375 x
.array
[2] |= y
.array
[2];
1377 x
.array
[1] |= y
.array
[1];
1379 x
.array
[0] |= y
.array
[0];
1387 static INLINE i386_cpu_flags
1388 cpu_flags_and_not (i386_cpu_flags x
, i386_cpu_flags y
)
1390 switch (ARRAY_SIZE (x
.array
))
1393 x
.array
[2] &= ~y
.array
[2];
1395 x
.array
[1] &= ~y
.array
[1];
1397 x
.array
[0] &= ~y
.array
[0];
1405 #define CPU_FLAGS_ARCH_MATCH 0x1
1406 #define CPU_FLAGS_64BIT_MATCH 0x2
1407 #define CPU_FLAGS_AES_MATCH 0x4
1408 #define CPU_FLAGS_PCLMUL_MATCH 0x8
1409 #define CPU_FLAGS_AVX_MATCH 0x10
1411 #define CPU_FLAGS_32BIT_MATCH \
1412 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH \
1413 | CPU_FLAGS_PCLMUL_MATCH | CPU_FLAGS_AVX_MATCH)
1414 #define CPU_FLAGS_PERFECT_MATCH \
1415 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)
1417 /* Return CPU flags match bits. */
1420 cpu_flags_match (const insn_template
*t
)
1422 i386_cpu_flags x
= t
->cpu_flags
;
1423 int match
= cpu_flags_check_cpu64 (x
) ? CPU_FLAGS_64BIT_MATCH
: 0;
1425 x
.bitfield
.cpu64
= 0;
1426 x
.bitfield
.cpuno64
= 0;
1428 if (cpu_flags_all_zero (&x
))
1430 /* This instruction is available on all archs. */
1431 match
|= CPU_FLAGS_32BIT_MATCH
;
1435 /* This instruction is available only on some archs. */
1436 i386_cpu_flags cpu
= cpu_arch_flags
;
1438 cpu
.bitfield
.cpu64
= 0;
1439 cpu
.bitfield
.cpuno64
= 0;
1440 cpu
= cpu_flags_and (x
, cpu
);
1441 if (!cpu_flags_all_zero (&cpu
))
1443 if (x
.bitfield
.cpuavx
)
1445 /* We only need to check AES/PCLMUL/SSE2AVX with AVX. */
1446 if (cpu
.bitfield
.cpuavx
)
1448 /* Check SSE2AVX. */
1449 if (!t
->opcode_modifier
.sse2avx
|| sse2avx
)
1451 match
|= (CPU_FLAGS_ARCH_MATCH
1452 | CPU_FLAGS_AVX_MATCH
);
1454 if (!x
.bitfield
.cpuaes
|| cpu
.bitfield
.cpuaes
)
1455 match
|= CPU_FLAGS_AES_MATCH
;
1457 if (!x
.bitfield
.cpupclmul
1458 || cpu
.bitfield
.cpupclmul
)
1459 match
|= CPU_FLAGS_PCLMUL_MATCH
;
1463 match
|= CPU_FLAGS_ARCH_MATCH
;
1466 match
|= CPU_FLAGS_32BIT_MATCH
;
1472 static INLINE i386_operand_type
1473 operand_type_and (i386_operand_type x
, i386_operand_type y
)
1475 switch (ARRAY_SIZE (x
.array
))
1478 x
.array
[2] &= y
.array
[2];
1480 x
.array
[1] &= y
.array
[1];
1482 x
.array
[0] &= y
.array
[0];
1490 static INLINE i386_operand_type
1491 operand_type_or (i386_operand_type x
, i386_operand_type y
)
1493 switch (ARRAY_SIZE (x
.array
))
1496 x
.array
[2] |= y
.array
[2];
1498 x
.array
[1] |= y
.array
[1];
1500 x
.array
[0] |= y
.array
[0];
1508 static INLINE i386_operand_type
1509 operand_type_xor (i386_operand_type x
, i386_operand_type y
)
1511 switch (ARRAY_SIZE (x
.array
))
1514 x
.array
[2] ^= y
.array
[2];
1516 x
.array
[1] ^= y
.array
[1];
1518 x
.array
[0] ^= y
.array
[0];
1526 static const i386_operand_type acc32
= OPERAND_TYPE_ACC32
;
1527 static const i386_operand_type acc64
= OPERAND_TYPE_ACC64
;
1528 static const i386_operand_type control
= OPERAND_TYPE_CONTROL
;
1529 static const i386_operand_type inoutportreg
1530 = OPERAND_TYPE_INOUTPORTREG
;
1531 static const i386_operand_type reg16_inoutportreg
1532 = OPERAND_TYPE_REG16_INOUTPORTREG
;
1533 static const i386_operand_type disp16
= OPERAND_TYPE_DISP16
;
1534 static const i386_operand_type disp32
= OPERAND_TYPE_DISP32
;
1535 static const i386_operand_type disp32s
= OPERAND_TYPE_DISP32S
;
1536 static const i386_operand_type disp16_32
= OPERAND_TYPE_DISP16_32
;
1537 static const i386_operand_type anydisp
1538 = OPERAND_TYPE_ANYDISP
;
1539 static const i386_operand_type regxmm
= OPERAND_TYPE_REGXMM
;
1540 static const i386_operand_type regymm
= OPERAND_TYPE_REGYMM
;
1541 static const i386_operand_type imm8
= OPERAND_TYPE_IMM8
;
1542 static const i386_operand_type imm8s
= OPERAND_TYPE_IMM8S
;
1543 static const i386_operand_type imm16
= OPERAND_TYPE_IMM16
;
1544 static const i386_operand_type imm32
= OPERAND_TYPE_IMM32
;
1545 static const i386_operand_type imm32s
= OPERAND_TYPE_IMM32S
;
1546 static const i386_operand_type imm64
= OPERAND_TYPE_IMM64
;
1547 static const i386_operand_type imm16_32
= OPERAND_TYPE_IMM16_32
;
1548 static const i386_operand_type imm16_32s
= OPERAND_TYPE_IMM16_32S
;
1549 static const i386_operand_type imm16_32_32s
= OPERAND_TYPE_IMM16_32_32S
;
1550 static const i386_operand_type vec_imm4
= OPERAND_TYPE_VEC_IMM4
;
1561 operand_type_check (i386_operand_type t
, enum operand_type c
)
1566 return (t
.bitfield
.reg8
1569 || t
.bitfield
.reg64
);
1572 return (t
.bitfield
.imm8
1576 || t
.bitfield
.imm32s
1577 || t
.bitfield
.imm64
);
1580 return (t
.bitfield
.disp8
1581 || t
.bitfield
.disp16
1582 || t
.bitfield
.disp32
1583 || t
.bitfield
.disp32s
1584 || t
.bitfield
.disp64
);
1587 return (t
.bitfield
.disp8
1588 || t
.bitfield
.disp16
1589 || t
.bitfield
.disp32
1590 || t
.bitfield
.disp32s
1591 || t
.bitfield
.disp64
1592 || t
.bitfield
.baseindex
);
1601 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1602 operand J for instruction template T. */
1605 match_reg_size (const insn_template
*t
, unsigned int j
)
1607 return !((i
.types
[j
].bitfield
.byte
1608 && !t
->operand_types
[j
].bitfield
.byte
)
1609 || (i
.types
[j
].bitfield
.word
1610 && !t
->operand_types
[j
].bitfield
.word
)
1611 || (i
.types
[j
].bitfield
.dword
1612 && !t
->operand_types
[j
].bitfield
.dword
)
1613 || (i
.types
[j
].bitfield
.qword
1614 && !t
->operand_types
[j
].bitfield
.qword
));
1617 /* Return 1 if there is no conflict in any size on operand J for
1618 instruction template T. */
1621 match_mem_size (const insn_template
*t
, unsigned int j
)
1623 return (match_reg_size (t
, j
)
1624 && !((i
.types
[j
].bitfield
.unspecified
1625 && !t
->operand_types
[j
].bitfield
.unspecified
)
1626 || (i
.types
[j
].bitfield
.fword
1627 && !t
->operand_types
[j
].bitfield
.fword
)
1628 || (i
.types
[j
].bitfield
.tbyte
1629 && !t
->operand_types
[j
].bitfield
.tbyte
)
1630 || (i
.types
[j
].bitfield
.xmmword
1631 && !t
->operand_types
[j
].bitfield
.xmmword
)
1632 || (i
.types
[j
].bitfield
.ymmword
1633 && !t
->operand_types
[j
].bitfield
.ymmword
)));
1636 /* Return 1 if there is no size conflict on any operands for
1637 instruction template T. */
1640 operand_size_match (const insn_template
*t
)
1645 /* Don't check jump instructions. */
1646 if (t
->opcode_modifier
.jump
1647 || t
->opcode_modifier
.jumpbyte
1648 || t
->opcode_modifier
.jumpdword
1649 || t
->opcode_modifier
.jumpintersegment
)
1652 /* Check memory and accumulator operand size. */
1653 for (j
= 0; j
< i
.operands
; j
++)
1655 if (t
->operand_types
[j
].bitfield
.anysize
)
1658 if (t
->operand_types
[j
].bitfield
.acc
&& !match_reg_size (t
, j
))
1664 if (i
.types
[j
].bitfield
.mem
&& !match_mem_size (t
, j
))
1673 else if (!t
->opcode_modifier
.d
&& !t
->opcode_modifier
.floatd
)
1676 i
.error
= operand_size_mismatch
;
1680 /* Check reverse. */
1681 gas_assert (i
.operands
== 2);
1684 for (j
= 0; j
< 2; j
++)
1686 if (t
->operand_types
[j
].bitfield
.acc
1687 && !match_reg_size (t
, j
? 0 : 1))
1690 if (i
.types
[j
].bitfield
.mem
1691 && !match_mem_size (t
, j
? 0 : 1))
1699 operand_type_match (i386_operand_type overlap
,
1700 i386_operand_type given
)
1702 i386_operand_type temp
= overlap
;
1704 temp
.bitfield
.jumpabsolute
= 0;
1705 temp
.bitfield
.unspecified
= 0;
1706 temp
.bitfield
.byte
= 0;
1707 temp
.bitfield
.word
= 0;
1708 temp
.bitfield
.dword
= 0;
1709 temp
.bitfield
.fword
= 0;
1710 temp
.bitfield
.qword
= 0;
1711 temp
.bitfield
.tbyte
= 0;
1712 temp
.bitfield
.xmmword
= 0;
1713 temp
.bitfield
.ymmword
= 0;
1714 if (operand_type_all_zero (&temp
))
1717 if (given
.bitfield
.baseindex
== overlap
.bitfield
.baseindex
1718 && given
.bitfield
.jumpabsolute
== overlap
.bitfield
.jumpabsolute
)
1722 i
.error
= operand_type_mismatch
;
1726 /* If given types g0 and g1 are registers they must be of the same type
1727 unless the expected operand type register overlap is null.
1728 Note that Acc in a template matches every size of reg. */
1731 operand_type_register_match (i386_operand_type m0
,
1732 i386_operand_type g0
,
1733 i386_operand_type t0
,
1734 i386_operand_type m1
,
1735 i386_operand_type g1
,
1736 i386_operand_type t1
)
1738 if (!operand_type_check (g0
, reg
))
1741 if (!operand_type_check (g1
, reg
))
1744 if (g0
.bitfield
.reg8
== g1
.bitfield
.reg8
1745 && g0
.bitfield
.reg16
== g1
.bitfield
.reg16
1746 && g0
.bitfield
.reg32
== g1
.bitfield
.reg32
1747 && g0
.bitfield
.reg64
== g1
.bitfield
.reg64
)
1750 if (m0
.bitfield
.acc
)
1752 t0
.bitfield
.reg8
= 1;
1753 t0
.bitfield
.reg16
= 1;
1754 t0
.bitfield
.reg32
= 1;
1755 t0
.bitfield
.reg64
= 1;
1758 if (m1
.bitfield
.acc
)
1760 t1
.bitfield
.reg8
= 1;
1761 t1
.bitfield
.reg16
= 1;
1762 t1
.bitfield
.reg32
= 1;
1763 t1
.bitfield
.reg64
= 1;
1766 if (!(t0
.bitfield
.reg8
& t1
.bitfield
.reg8
)
1767 && !(t0
.bitfield
.reg16
& t1
.bitfield
.reg16
)
1768 && !(t0
.bitfield
.reg32
& t1
.bitfield
.reg32
)
1769 && !(t0
.bitfield
.reg64
& t1
.bitfield
.reg64
))
1772 i
.error
= register_type_mismatch
;
1777 static INLINE
unsigned int
1778 register_number (const reg_entry
*r
)
1780 unsigned int nr
= r
->reg_num
;
1782 if (r
->reg_flags
& RegRex
)
1788 static INLINE
unsigned int
1789 mode_from_disp_size (i386_operand_type t
)
1791 if (t
.bitfield
.disp8
)
1793 else if (t
.bitfield
.disp16
1794 || t
.bitfield
.disp32
1795 || t
.bitfield
.disp32s
)
1802 fits_in_signed_byte (offsetT num
)
1804 return (num
>= -128) && (num
<= 127);
1808 fits_in_unsigned_byte (offsetT num
)
1810 return (num
& 0xff) == num
;
1814 fits_in_unsigned_word (offsetT num
)
1816 return (num
& 0xffff) == num
;
1820 fits_in_signed_word (offsetT num
)
1822 return (-32768 <= num
) && (num
<= 32767);
1826 fits_in_signed_long (offsetT num ATTRIBUTE_UNUSED
)
1831 return (!(((offsetT
) -1 << 31) & num
)
1832 || (((offsetT
) -1 << 31) & num
) == ((offsetT
) -1 << 31));
1834 } /* fits_in_signed_long() */
1837 fits_in_unsigned_long (offsetT num ATTRIBUTE_UNUSED
)
1842 return (num
& (((offsetT
) 2 << 31) - 1)) == num
;
1844 } /* fits_in_unsigned_long() */
1847 fits_in_imm4 (offsetT num
)
1849 return (num
& 0xf) == num
;
1852 static i386_operand_type
1853 smallest_imm_type (offsetT num
)
1855 i386_operand_type t
;
1857 operand_type_set (&t
, 0);
1858 t
.bitfield
.imm64
= 1;
1860 if (cpu_arch_tune
!= PROCESSOR_I486
&& num
== 1)
1862 /* This code is disabled on the 486 because all the Imm1 forms
1863 in the opcode table are slower on the i486. They're the
1864 versions with the implicitly specified single-position
1865 displacement, which has another syntax if you really want to
1867 t
.bitfield
.imm1
= 1;
1868 t
.bitfield
.imm8
= 1;
1869 t
.bitfield
.imm8s
= 1;
1870 t
.bitfield
.imm16
= 1;
1871 t
.bitfield
.imm32
= 1;
1872 t
.bitfield
.imm32s
= 1;
1874 else if (fits_in_signed_byte (num
))
1876 t
.bitfield
.imm8
= 1;
1877 t
.bitfield
.imm8s
= 1;
1878 t
.bitfield
.imm16
= 1;
1879 t
.bitfield
.imm32
= 1;
1880 t
.bitfield
.imm32s
= 1;
1882 else if (fits_in_unsigned_byte (num
))
1884 t
.bitfield
.imm8
= 1;
1885 t
.bitfield
.imm16
= 1;
1886 t
.bitfield
.imm32
= 1;
1887 t
.bitfield
.imm32s
= 1;
1889 else if (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
1891 t
.bitfield
.imm16
= 1;
1892 t
.bitfield
.imm32
= 1;
1893 t
.bitfield
.imm32s
= 1;
1895 else if (fits_in_signed_long (num
))
1897 t
.bitfield
.imm32
= 1;
1898 t
.bitfield
.imm32s
= 1;
1900 else if (fits_in_unsigned_long (num
))
1901 t
.bitfield
.imm32
= 1;
1907 offset_in_range (offsetT val
, int size
)
1913 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
1914 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
1915 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
1917 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
1923 /* If BFD64, sign extend val for 32bit address mode. */
1924 if (flag_code
!= CODE_64BIT
1925 || i
.prefix
[ADDR_PREFIX
])
1926 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
1927 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
1930 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
1932 char buf1
[40], buf2
[40];
1934 sprint_value (buf1
, val
);
1935 sprint_value (buf2
, val
& mask
);
1936 as_warn (_("%s shortened to %s"), buf1
, buf2
);
1950 a. PREFIX_EXIST if attempting to add a prefix where one from the
1951 same class already exists.
1952 b. PREFIX_LOCK if lock prefix is added.
1953 c. PREFIX_REP if rep/repne prefix is added.
1954 d. PREFIX_OTHER if other prefix is added.
1957 static enum PREFIX_GROUP
1958 add_prefix (unsigned int prefix
)
1960 enum PREFIX_GROUP ret
= PREFIX_OTHER
;
1963 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
1964 && flag_code
== CODE_64BIT
)
1966 if ((i
.prefix
[REX_PREFIX
] & prefix
& REX_W
)
1967 || ((i
.prefix
[REX_PREFIX
] & (REX_R
| REX_X
| REX_B
))
1968 && (prefix
& (REX_R
| REX_X
| REX_B
))))
1979 case CS_PREFIX_OPCODE
:
1980 case DS_PREFIX_OPCODE
:
1981 case ES_PREFIX_OPCODE
:
1982 case FS_PREFIX_OPCODE
:
1983 case GS_PREFIX_OPCODE
:
1984 case SS_PREFIX_OPCODE
:
1988 case REPNE_PREFIX_OPCODE
:
1989 case REPE_PREFIX_OPCODE
:
1994 case LOCK_PREFIX_OPCODE
:
2003 case ADDR_PREFIX_OPCODE
:
2007 case DATA_PREFIX_OPCODE
:
2011 if (i
.prefix
[q
] != 0)
2019 i
.prefix
[q
] |= prefix
;
2022 as_bad (_("same type of prefix used twice"));
2028 update_code_flag (int value
, int check
)
2030 PRINTF_LIKE ((*as_error
));
2032 flag_code
= (enum flag_code
) value
;
2033 if (flag_code
== CODE_64BIT
)
2035 cpu_arch_flags
.bitfield
.cpu64
= 1;
2036 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2040 cpu_arch_flags
.bitfield
.cpu64
= 0;
2041 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2043 if (value
== CODE_64BIT
&& !cpu_arch_flags
.bitfield
.cpulm
)
2046 as_error
= as_fatal
;
2049 (*as_error
) (_("64bit mode not supported on `%s'."),
2050 cpu_arch_name
? cpu_arch_name
: default_arch
);
2052 if (value
== CODE_32BIT
&& !cpu_arch_flags
.bitfield
.cpui386
)
2055 as_error
= as_fatal
;
2058 (*as_error
) (_("32bit mode not supported on `%s'."),
2059 cpu_arch_name
? cpu_arch_name
: default_arch
);
2061 stackop_size
= '\0';
2065 set_code_flag (int value
)
2067 update_code_flag (value
, 0);
2071 set_16bit_gcc_code_flag (int new_code_flag
)
2073 flag_code
= (enum flag_code
) new_code_flag
;
2074 if (flag_code
!= CODE_16BIT
)
2076 cpu_arch_flags
.bitfield
.cpu64
= 0;
2077 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2078 stackop_size
= LONG_MNEM_SUFFIX
;
2082 set_intel_syntax (int syntax_flag
)
2084 /* Find out if register prefixing is specified. */
2085 int ask_naked_reg
= 0;
2088 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2090 char *string
= input_line_pointer
;
2091 int e
= get_symbol_end ();
2093 if (strcmp (string
, "prefix") == 0)
2095 else if (strcmp (string
, "noprefix") == 0)
2098 as_bad (_("bad argument to syntax directive."));
2099 *input_line_pointer
= e
;
2101 demand_empty_rest_of_line ();
2103 intel_syntax
= syntax_flag
;
2105 if (ask_naked_reg
== 0)
2106 allow_naked_reg
= (intel_syntax
2107 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
2109 allow_naked_reg
= (ask_naked_reg
< 0);
2111 expr_set_rank (O_full_ptr
, syntax_flag
? 10 : 0);
2113 identifier_chars
['%'] = intel_syntax
&& allow_naked_reg
? '%' : 0;
2114 identifier_chars
['$'] = intel_syntax
? '$' : 0;
2115 register_prefix
= allow_naked_reg
? "" : "%";
2119 set_intel_mnemonic (int mnemonic_flag
)
2121 intel_mnemonic
= mnemonic_flag
;
2125 set_allow_index_reg (int flag
)
2127 allow_index_reg
= flag
;
2131 set_check (int what
)
2133 enum check_kind
*kind
;
2138 kind
= &operand_check
;
2149 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2151 char *string
= input_line_pointer
;
2152 int e
= get_symbol_end ();
2154 if (strcmp (string
, "none") == 0)
2156 else if (strcmp (string
, "warning") == 0)
2157 *kind
= check_warning
;
2158 else if (strcmp (string
, "error") == 0)
2159 *kind
= check_error
;
2161 as_bad (_("bad argument to %s_check directive."), str
);
2162 *input_line_pointer
= e
;
2165 as_bad (_("missing argument for %s_check directive"), str
);
2167 demand_empty_rest_of_line ();
2171 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED
,
2172 i386_cpu_flags new_flag ATTRIBUTE_UNUSED
)
2174 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2175 static const char *arch
;
2177 /* Intel LIOM is only supported on ELF. */
2183 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2184 use default_arch. */
2185 arch
= cpu_arch_name
;
2187 arch
= default_arch
;
2190 /* If we are targeting Intel L1OM, we must enable it. */
2191 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_L1OM
2192 || new_flag
.bitfield
.cpul1om
)
2195 /* If we are targeting Intel K1OM, we must enable it. */
2196 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_K1OM
2197 || new_flag
.bitfield
.cpuk1om
)
2200 as_bad (_("`%s' is not supported on `%s'"), name
, arch
);
2205 set_cpu_arch (int dummy ATTRIBUTE_UNUSED
)
2209 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2211 char *string
= input_line_pointer
;
2212 int e
= get_symbol_end ();
2214 i386_cpu_flags flags
;
2216 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
2218 if (strcmp (string
, cpu_arch
[j
].name
) == 0)
2220 check_cpu_arch_compatible (string
, cpu_arch
[j
].flags
);
2224 cpu_arch_name
= cpu_arch
[j
].name
;
2225 cpu_sub_arch_name
= NULL
;
2226 cpu_arch_flags
= cpu_arch
[j
].flags
;
2227 if (flag_code
== CODE_64BIT
)
2229 cpu_arch_flags
.bitfield
.cpu64
= 1;
2230 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2234 cpu_arch_flags
.bitfield
.cpu64
= 0;
2235 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2237 cpu_arch_isa
= cpu_arch
[j
].type
;
2238 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
2239 if (!cpu_arch_tune_set
)
2241 cpu_arch_tune
= cpu_arch_isa
;
2242 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
2247 if (!cpu_arch
[j
].negated
)
2248 flags
= cpu_flags_or (cpu_arch_flags
,
2251 flags
= cpu_flags_and_not (cpu_arch_flags
,
2253 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2255 if (cpu_sub_arch_name
)
2257 char *name
= cpu_sub_arch_name
;
2258 cpu_sub_arch_name
= concat (name
,
2260 (const char *) NULL
);
2264 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
2265 cpu_arch_flags
= flags
;
2266 cpu_arch_isa_flags
= flags
;
2268 *input_line_pointer
= e
;
2269 demand_empty_rest_of_line ();
2273 if (j
>= ARRAY_SIZE (cpu_arch
))
2274 as_bad (_("no such architecture: `%s'"), string
);
2276 *input_line_pointer
= e
;
2279 as_bad (_("missing cpu architecture"));
2281 no_cond_jump_promotion
= 0;
2282 if (*input_line_pointer
== ','
2283 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
2285 char *string
= ++input_line_pointer
;
2286 int e
= get_symbol_end ();
2288 if (strcmp (string
, "nojumps") == 0)
2289 no_cond_jump_promotion
= 1;
2290 else if (strcmp (string
, "jumps") == 0)
2293 as_bad (_("no such architecture modifier: `%s'"), string
);
2295 *input_line_pointer
= e
;
2298 demand_empty_rest_of_line ();
2301 enum bfd_architecture
2304 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2306 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2307 || flag_code
!= CODE_64BIT
)
2308 as_fatal (_("Intel L1OM is 64bit ELF only"));
2309 return bfd_arch_l1om
;
2311 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2313 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2314 || flag_code
!= CODE_64BIT
)
2315 as_fatal (_("Intel K1OM is 64bit ELF only"));
2316 return bfd_arch_k1om
;
2319 return bfd_arch_i386
;
2325 if (!strncmp (default_arch
, "x86_64", 6))
2327 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2329 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2330 || default_arch
[6] != '\0')
2331 as_fatal (_("Intel L1OM is 64bit ELF only"));
2332 return bfd_mach_l1om
;
2334 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2336 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2337 || default_arch
[6] != '\0')
2338 as_fatal (_("Intel K1OM is 64bit ELF only"));
2339 return bfd_mach_k1om
;
2341 else if (default_arch
[6] == '\0')
2342 return bfd_mach_x86_64
;
2344 return bfd_mach_x64_32
;
2346 else if (!strcmp (default_arch
, "i386"))
2347 return bfd_mach_i386_i386
;
2349 as_fatal (_("unknown architecture"));
2355 const char *hash_err
;
2357 /* Initialize op_hash hash table. */
2358 op_hash
= hash_new ();
2361 const insn_template
*optab
;
2362 templates
*core_optab
;
2364 /* Setup for loop. */
2366 core_optab
= (templates
*) xmalloc (sizeof (templates
));
2367 core_optab
->start
= optab
;
2372 if (optab
->name
== NULL
2373 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
2375 /* different name --> ship out current template list;
2376 add to hash table; & begin anew. */
2377 core_optab
->end
= optab
;
2378 hash_err
= hash_insert (op_hash
,
2380 (void *) core_optab
);
2383 as_fatal (_("can't hash %s: %s"),
2387 if (optab
->name
== NULL
)
2389 core_optab
= (templates
*) xmalloc (sizeof (templates
));
2390 core_optab
->start
= optab
;
2395 /* Initialize reg_hash hash table. */
2396 reg_hash
= hash_new ();
2398 const reg_entry
*regtab
;
2399 unsigned int regtab_size
= i386_regtab_size
;
2401 for (regtab
= i386_regtab
; regtab_size
--; regtab
++)
2403 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (void *) regtab
);
2405 as_fatal (_("can't hash %s: %s"),
2411 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
2416 for (c
= 0; c
< 256; c
++)
2421 mnemonic_chars
[c
] = c
;
2422 register_chars
[c
] = c
;
2423 operand_chars
[c
] = c
;
2425 else if (ISLOWER (c
))
2427 mnemonic_chars
[c
] = c
;
2428 register_chars
[c
] = c
;
2429 operand_chars
[c
] = c
;
2431 else if (ISUPPER (c
))
2433 mnemonic_chars
[c
] = TOLOWER (c
);
2434 register_chars
[c
] = mnemonic_chars
[c
];
2435 operand_chars
[c
] = c
;
2438 if (ISALPHA (c
) || ISDIGIT (c
))
2439 identifier_chars
[c
] = c
;
2442 identifier_chars
[c
] = c
;
2443 operand_chars
[c
] = c
;
2448 identifier_chars
['@'] = '@';
2451 identifier_chars
['?'] = '?';
2452 operand_chars
['?'] = '?';
2454 digit_chars
['-'] = '-';
2455 mnemonic_chars
['_'] = '_';
2456 mnemonic_chars
['-'] = '-';
2457 mnemonic_chars
['.'] = '.';
2458 identifier_chars
['_'] = '_';
2459 identifier_chars
['.'] = '.';
2461 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
2462 operand_chars
[(unsigned char) *p
] = *p
;
2465 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2468 record_alignment (text_section
, 2);
2469 record_alignment (data_section
, 2);
2470 record_alignment (bss_section
, 2);
2474 if (flag_code
== CODE_64BIT
)
2476 #if defined (OBJ_COFF) && defined (TE_PE)
2477 x86_dwarf2_return_column
= (OUTPUT_FLAVOR
== bfd_target_coff_flavour
2480 x86_dwarf2_return_column
= 16;
2482 x86_cie_data_alignment
= -8;
2486 x86_dwarf2_return_column
= 8;
2487 x86_cie_data_alignment
= -4;
2492 i386_print_statistics (FILE *file
)
2494 hash_print_statistics (file
, "i386 opcode", op_hash
);
2495 hash_print_statistics (file
, "i386 register", reg_hash
);
2500 /* Debugging routines for md_assemble. */
2501 static void pte (insn_template
*);
2502 static void pt (i386_operand_type
);
2503 static void pe (expressionS
*);
2504 static void ps (symbolS
*);
2507 pi (char *line
, i386_insn
*x
)
2511 fprintf (stdout
, "%s: template ", line
);
2513 fprintf (stdout
, " address: base %s index %s scale %x\n",
2514 x
->base_reg
? x
->base_reg
->reg_name
: "none",
2515 x
->index_reg
? x
->index_reg
->reg_name
: "none",
2516 x
->log2_scale_factor
);
2517 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
2518 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
2519 fprintf (stdout
, " sib: base %x index %x scale %x\n",
2520 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
2521 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
2522 (x
->rex
& REX_W
) != 0,
2523 (x
->rex
& REX_R
) != 0,
2524 (x
->rex
& REX_X
) != 0,
2525 (x
->rex
& REX_B
) != 0);
2526 for (j
= 0; j
< x
->operands
; j
++)
2528 fprintf (stdout
, " #%d: ", j
+ 1);
2530 fprintf (stdout
, "\n");
2531 if (x
->types
[j
].bitfield
.reg8
2532 || x
->types
[j
].bitfield
.reg16
2533 || x
->types
[j
].bitfield
.reg32
2534 || x
->types
[j
].bitfield
.reg64
2535 || x
->types
[j
].bitfield
.regmmx
2536 || x
->types
[j
].bitfield
.regxmm
2537 || x
->types
[j
].bitfield
.regymm
2538 || x
->types
[j
].bitfield
.sreg2
2539 || x
->types
[j
].bitfield
.sreg3
2540 || x
->types
[j
].bitfield
.control
2541 || x
->types
[j
].bitfield
.debug
2542 || x
->types
[j
].bitfield
.test
)
2543 fprintf (stdout
, "%s\n", x
->op
[j
].regs
->reg_name
);
2544 if (operand_type_check (x
->types
[j
], imm
))
2546 if (operand_type_check (x
->types
[j
], disp
))
2547 pe (x
->op
[j
].disps
);
2552 pte (insn_template
*t
)
2555 fprintf (stdout
, " %d operands ", t
->operands
);
2556 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
2557 if (t
->extension_opcode
!= None
)
2558 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
2559 if (t
->opcode_modifier
.d
)
2560 fprintf (stdout
, "D");
2561 if (t
->opcode_modifier
.w
)
2562 fprintf (stdout
, "W");
2563 fprintf (stdout
, "\n");
2564 for (j
= 0; j
< t
->operands
; j
++)
2566 fprintf (stdout
, " #%d type ", j
+ 1);
2567 pt (t
->operand_types
[j
]);
2568 fprintf (stdout
, "\n");
2575 fprintf (stdout
, " operation %d\n", e
->X_op
);
2576 fprintf (stdout
, " add_number %ld (%lx)\n",
2577 (long) e
->X_add_number
, (long) e
->X_add_number
);
2578 if (e
->X_add_symbol
)
2580 fprintf (stdout
, " add_symbol ");
2581 ps (e
->X_add_symbol
);
2582 fprintf (stdout
, "\n");
2586 fprintf (stdout
, " op_symbol ");
2587 ps (e
->X_op_symbol
);
2588 fprintf (stdout
, "\n");
2595 fprintf (stdout
, "%s type %s%s",
2597 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
2598 segment_name (S_GET_SEGMENT (s
)));
2601 static struct type_name
2603 i386_operand_type mask
;
2606 const type_names
[] =
2608 { OPERAND_TYPE_REG8
, "r8" },
2609 { OPERAND_TYPE_REG16
, "r16" },
2610 { OPERAND_TYPE_REG32
, "r32" },
2611 { OPERAND_TYPE_REG64
, "r64" },
2612 { OPERAND_TYPE_IMM8
, "i8" },
2613 { OPERAND_TYPE_IMM8
, "i8s" },
2614 { OPERAND_TYPE_IMM16
, "i16" },
2615 { OPERAND_TYPE_IMM32
, "i32" },
2616 { OPERAND_TYPE_IMM32S
, "i32s" },
2617 { OPERAND_TYPE_IMM64
, "i64" },
2618 { OPERAND_TYPE_IMM1
, "i1" },
2619 { OPERAND_TYPE_BASEINDEX
, "BaseIndex" },
2620 { OPERAND_TYPE_DISP8
, "d8" },
2621 { OPERAND_TYPE_DISP16
, "d16" },
2622 { OPERAND_TYPE_DISP32
, "d32" },
2623 { OPERAND_TYPE_DISP32S
, "d32s" },
2624 { OPERAND_TYPE_DISP64
, "d64" },
2625 { OPERAND_TYPE_INOUTPORTREG
, "InOutPortReg" },
2626 { OPERAND_TYPE_SHIFTCOUNT
, "ShiftCount" },
2627 { OPERAND_TYPE_CONTROL
, "control reg" },
2628 { OPERAND_TYPE_TEST
, "test reg" },
2629 { OPERAND_TYPE_DEBUG
, "debug reg" },
2630 { OPERAND_TYPE_FLOATREG
, "FReg" },
2631 { OPERAND_TYPE_FLOATACC
, "FAcc" },
2632 { OPERAND_TYPE_SREG2
, "SReg2" },
2633 { OPERAND_TYPE_SREG3
, "SReg3" },
2634 { OPERAND_TYPE_ACC
, "Acc" },
2635 { OPERAND_TYPE_JUMPABSOLUTE
, "Jump Absolute" },
2636 { OPERAND_TYPE_REGMMX
, "rMMX" },
2637 { OPERAND_TYPE_REGXMM
, "rXMM" },
2638 { OPERAND_TYPE_REGYMM
, "rYMM" },
2639 { OPERAND_TYPE_ESSEG
, "es" },
2643 pt (i386_operand_type t
)
2646 i386_operand_type a
;
2648 for (j
= 0; j
< ARRAY_SIZE (type_names
); j
++)
2650 a
= operand_type_and (t
, type_names
[j
].mask
);
2651 if (!operand_type_all_zero (&a
))
2652 fprintf (stdout
, "%s, ", type_names
[j
].name
);
2657 #endif /* DEBUG386 */
2659 static bfd_reloc_code_real_type
2660 reloc (unsigned int size
,
2663 bfd_reloc_code_real_type other
)
2665 if (other
!= NO_RELOC
)
2667 reloc_howto_type
*rel
;
2672 case BFD_RELOC_X86_64_GOT32
:
2673 return BFD_RELOC_X86_64_GOT64
;
2675 case BFD_RELOC_X86_64_PLTOFF64
:
2676 return BFD_RELOC_X86_64_PLTOFF64
;
2678 case BFD_RELOC_X86_64_GOTPC32
:
2679 other
= BFD_RELOC_X86_64_GOTPC64
;
2681 case BFD_RELOC_X86_64_GOTPCREL
:
2682 other
= BFD_RELOC_X86_64_GOTPCREL64
;
2684 case BFD_RELOC_X86_64_TPOFF32
:
2685 other
= BFD_RELOC_X86_64_TPOFF64
;
2687 case BFD_RELOC_X86_64_DTPOFF32
:
2688 other
= BFD_RELOC_X86_64_DTPOFF64
;
2694 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2695 if (other
== BFD_RELOC_SIZE32
)
2698 return BFD_RELOC_SIZE64
;
2700 as_bad (_("there are no pc-relative size relocations"));
2704 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
2705 if (size
== 4 && (flag_code
!= CODE_64BIT
|| disallow_64bit_reloc
))
2708 rel
= bfd_reloc_type_lookup (stdoutput
, other
);
2710 as_bad (_("unknown relocation (%u)"), other
);
2711 else if (size
!= bfd_get_reloc_size (rel
))
2712 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
2713 bfd_get_reloc_size (rel
),
2715 else if (pcrel
&& !rel
->pc_relative
)
2716 as_bad (_("non-pc-relative relocation for pc-relative field"));
2717 else if ((rel
->complain_on_overflow
== complain_overflow_signed
2719 || (rel
->complain_on_overflow
== complain_overflow_unsigned
2721 as_bad (_("relocated field and relocation type differ in signedness"));
2730 as_bad (_("there are no unsigned pc-relative relocations"));
2733 case 1: return BFD_RELOC_8_PCREL
;
2734 case 2: return BFD_RELOC_16_PCREL
;
2735 case 4: return BFD_RELOC_32_PCREL
;
2736 case 8: return BFD_RELOC_64_PCREL
;
2738 as_bad (_("cannot do %u byte pc-relative relocation"), size
);
2745 case 4: return BFD_RELOC_X86_64_32S
;
2750 case 1: return BFD_RELOC_8
;
2751 case 2: return BFD_RELOC_16
;
2752 case 4: return BFD_RELOC_32
;
2753 case 8: return BFD_RELOC_64
;
2755 as_bad (_("cannot do %s %u byte relocation"),
2756 sign
> 0 ? "signed" : "unsigned", size
);
2762 /* Here we decide which fixups can be adjusted to make them relative to
2763 the beginning of the section instead of the symbol. Basically we need
2764 to make sure that the dynamic relocations are done correctly, so in
2765 some cases we force the original symbol to be used. */
2768 tc_i386_fix_adjustable (fixS
*fixP ATTRIBUTE_UNUSED
)
2770 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2774 /* Don't adjust pc-relative references to merge sections in 64-bit
2776 if (use_rela_relocations
2777 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
2781 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
2782 and changed later by validate_fix. */
2783 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
2784 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
2787 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
2788 for size relocations. */
2789 if (fixP
->fx_r_type
== BFD_RELOC_SIZE32
2790 || fixP
->fx_r_type
== BFD_RELOC_SIZE64
2791 || fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
2792 || fixP
->fx_r_type
== BFD_RELOC_386_PLT32
2793 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
2794 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
2795 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
2796 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
2797 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
2798 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
2799 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
2800 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
2801 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
2802 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTDESC
2803 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_DESC_CALL
2804 || fixP
->fx_r_type
== BFD_RELOC_X86_64_PLT32
2805 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
2806 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
2807 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
2808 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
2809 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
2810 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
2811 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
2812 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
2813 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
2814 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
2815 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPC32_TLSDESC
2816 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSDESC_CALL
2817 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
2818 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
2825 intel_float_operand (const char *mnemonic
)
2827 /* Note that the value returned is meaningful only for opcodes with (memory)
2828 operands, hence the code here is free to improperly handle opcodes that
2829 have no operands (for better performance and smaller code). */
2831 if (mnemonic
[0] != 'f')
2832 return 0; /* non-math */
2834 switch (mnemonic
[1])
2836 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
2837 the fs segment override prefix not currently handled because no
2838 call path can make opcodes without operands get here */
2840 return 2 /* integer op */;
2842 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
2843 return 3; /* fldcw/fldenv */
2846 if (mnemonic
[2] != 'o' /* fnop */)
2847 return 3; /* non-waiting control op */
2850 if (mnemonic
[2] == 's')
2851 return 3; /* frstor/frstpm */
2854 if (mnemonic
[2] == 'a')
2855 return 3; /* fsave */
2856 if (mnemonic
[2] == 't')
2858 switch (mnemonic
[3])
2860 case 'c': /* fstcw */
2861 case 'd': /* fstdw */
2862 case 'e': /* fstenv */
2863 case 's': /* fsts[gw] */
2869 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
2870 return 0; /* fxsave/fxrstor are not really math ops */
2877 /* Build the VEX prefix. */
2880 build_vex_prefix (const insn_template
*t
)
2882 unsigned int register_specifier
;
2883 unsigned int implied_prefix
;
2884 unsigned int vector_length
;
2886 /* Check register specifier. */
2887 if (i
.vex
.register_specifier
)
2888 register_specifier
= ~register_number (i
.vex
.register_specifier
) & 0xf;
2890 register_specifier
= 0xf;
2892 /* Use 2-byte VEX prefix by swappping destination and source
2895 && i
.operands
== i
.reg_operands
2896 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
2897 && i
.tm
.opcode_modifier
.s
2900 unsigned int xchg
= i
.operands
- 1;
2901 union i386_op temp_op
;
2902 i386_operand_type temp_type
;
2904 temp_type
= i
.types
[xchg
];
2905 i
.types
[xchg
] = i
.types
[0];
2906 i
.types
[0] = temp_type
;
2907 temp_op
= i
.op
[xchg
];
2908 i
.op
[xchg
] = i
.op
[0];
2911 gas_assert (i
.rm
.mode
== 3);
2915 i
.rm
.regmem
= i
.rm
.reg
;
2918 /* Use the next insn. */
2922 if (i
.tm
.opcode_modifier
.vex
== VEXScalar
)
2923 vector_length
= avxscalar
;
2925 vector_length
= i
.tm
.opcode_modifier
.vex
== VEX256
? 1 : 0;
2927 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
2932 case DATA_PREFIX_OPCODE
:
2935 case REPE_PREFIX_OPCODE
:
2938 case REPNE_PREFIX_OPCODE
:
2945 /* Use 2-byte VEX prefix if possible. */
2946 if (i
.tm
.opcode_modifier
.vexopcode
== VEX0F
2947 && i
.tm
.opcode_modifier
.vexw
!= VEXW1
2948 && (i
.rex
& (REX_W
| REX_X
| REX_B
)) == 0)
2950 /* 2-byte VEX prefix. */
2954 i
.vex
.bytes
[0] = 0xc5;
2956 /* Check the REX.R bit. */
2957 r
= (i
.rex
& REX_R
) ? 0 : 1;
2958 i
.vex
.bytes
[1] = (r
<< 7
2959 | register_specifier
<< 3
2960 | vector_length
<< 2
2965 /* 3-byte VEX prefix. */
2970 switch (i
.tm
.opcode_modifier
.vexopcode
)
2974 i
.vex
.bytes
[0] = 0xc4;
2978 i
.vex
.bytes
[0] = 0xc4;
2982 i
.vex
.bytes
[0] = 0xc4;
2986 i
.vex
.bytes
[0] = 0x8f;
2990 i
.vex
.bytes
[0] = 0x8f;
2994 i
.vex
.bytes
[0] = 0x8f;
3000 /* The high 3 bits of the second VEX byte are 1's compliment
3001 of RXB bits from REX. */
3002 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3004 /* Check the REX.W bit. */
3005 w
= (i
.rex
& REX_W
) ? 1 : 0;
3006 if (i
.tm
.opcode_modifier
.vexw
)
3011 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
3015 i
.vex
.bytes
[2] = (w
<< 7
3016 | register_specifier
<< 3
3017 | vector_length
<< 2
3023 process_immext (void)
3027 if ((i
.tm
.cpu_flags
.bitfield
.cpusse3
|| i
.tm
.cpu_flags
.bitfield
.cpusvme
)
3030 /* MONITOR/MWAIT as well as SVME instructions have fixed operands
3031 with an opcode suffix which is coded in the same place as an
3032 8-bit immediate field would be.
3033 Here we check those operands and remove them afterwards. */
3036 for (x
= 0; x
< i
.operands
; x
++)
3037 if (register_number (i
.op
[x
].regs
) != x
)
3038 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3039 register_prefix
, i
.op
[x
].regs
->reg_name
, x
+ 1,
3045 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
3046 which is coded in the same place as an 8-bit immediate field
3047 would be. Here we fake an 8-bit immediate operand from the
3048 opcode suffix stored in tm.extension_opcode.
3050 AVX instructions also use this encoding, for some of
3051 3 argument instructions. */
3053 gas_assert (i
.imm_operands
== 0
3055 || (i
.tm
.opcode_modifier
.vex
3056 && i
.operands
<= 4)));
3058 exp
= &im_expressions
[i
.imm_operands
++];
3059 i
.op
[i
.operands
].imms
= exp
;
3060 i
.types
[i
.operands
] = imm8
;
3062 exp
->X_op
= O_constant
;
3063 exp
->X_add_number
= i
.tm
.extension_opcode
;
3064 i
.tm
.extension_opcode
= None
;
3071 switch (i
.tm
.opcode_modifier
.hleprefixok
)
3076 as_bad (_("invalid instruction `%s' after `%s'"),
3077 i
.tm
.name
, i
.hle_prefix
);
3080 if (i
.prefix
[LOCK_PREFIX
])
3082 as_bad (_("missing `lock' with `%s'"), i
.hle_prefix
);
3086 case HLEPrefixRelease
:
3087 if (i
.prefix
[HLE_PREFIX
] != XRELEASE_PREFIX_OPCODE
)
3089 as_bad (_("instruction `%s' after `xacquire' not allowed"),
3093 if (i
.mem_operands
== 0
3094 || !operand_type_check (i
.types
[i
.operands
- 1], anymem
))
3096 as_bad (_("memory destination needed for instruction `%s'"
3097 " after `xrelease'"), i
.tm
.name
);
3104 /* This is the guts of the machine-dependent assembler. LINE points to a
3105 machine dependent instruction. This function is supposed to emit
3106 the frags/bytes it assembles to. */
3109 md_assemble (char *line
)
3112 char mnemonic
[MAX_MNEM_SIZE
];
3113 const insn_template
*t
;
3115 /* Initialize globals. */
3116 memset (&i
, '\0', sizeof (i
));
3117 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3118 i
.reloc
[j
] = NO_RELOC
;
3119 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
3120 memset (im_expressions
, '\0', sizeof (im_expressions
));
3121 save_stack_p
= save_stack
;
3123 /* First parse an instruction mnemonic & call i386_operand for the operands.
3124 We assume that the scrubber has arranged it so that line[0] is the valid
3125 start of a (possibly prefixed) mnemonic. */
3127 line
= parse_insn (line
, mnemonic
);
3131 line
= parse_operands (line
, mnemonic
);
3136 /* Now we've parsed the mnemonic into a set of templates, and have the
3137 operands at hand. */
3139 /* All intel opcodes have reversed operands except for "bound" and
3140 "enter". We also don't reverse intersegment "jmp" and "call"
3141 instructions with 2 immediate operands so that the immediate segment
3142 precedes the offset, as it does when in AT&T mode. */
3145 && (strcmp (mnemonic
, "bound") != 0)
3146 && (strcmp (mnemonic
, "invlpga") != 0)
3147 && !(operand_type_check (i
.types
[0], imm
)
3148 && operand_type_check (i
.types
[1], imm
)))
3151 /* The order of the immediates should be reversed
3152 for 2 immediates extrq and insertq instructions */
3153 if (i
.imm_operands
== 2
3154 && (strcmp (mnemonic
, "extrq") == 0
3155 || strcmp (mnemonic
, "insertq") == 0))
3156 swap_2_operands (0, 1);
3161 /* Don't optimize displacement for movabs since it only takes 64bit
3164 && i
.disp_encoding
!= disp_encoding_32bit
3165 && (flag_code
!= CODE_64BIT
3166 || strcmp (mnemonic
, "movabs") != 0))
3169 /* Next, we find a template that matches the given insn,
3170 making sure the overlap of the given operands types is consistent
3171 with the template operand types. */
3173 if (!(t
= match_template ()))
3176 if (sse_check
!= check_none
3177 && !i
.tm
.opcode_modifier
.noavx
3178 && (i
.tm
.cpu_flags
.bitfield
.cpusse
3179 || i
.tm
.cpu_flags
.bitfield
.cpusse2
3180 || i
.tm
.cpu_flags
.bitfield
.cpusse3
3181 || i
.tm
.cpu_flags
.bitfield
.cpussse3
3182 || i
.tm
.cpu_flags
.bitfield
.cpusse4_1
3183 || i
.tm
.cpu_flags
.bitfield
.cpusse4_2
))
3185 (sse_check
== check_warning
3187 : as_bad
) (_("SSE instruction `%s' is used"), i
.tm
.name
);
3190 /* Zap movzx and movsx suffix. The suffix has been set from
3191 "word ptr" or "byte ptr" on the source operand in Intel syntax
3192 or extracted from mnemonic in AT&T syntax. But we'll use
3193 the destination register to choose the suffix for encoding. */
3194 if ((i
.tm
.base_opcode
& ~9) == 0x0fb6)
3196 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
3197 there is no suffix, the default will be byte extension. */
3198 if (i
.reg_operands
!= 2
3201 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
3206 if (i
.tm
.opcode_modifier
.fwait
)
3207 if (!add_prefix (FWAIT_OPCODE
))
3210 /* Check if REP prefix is OK. */
3211 if (i
.rep_prefix
&& !i
.tm
.opcode_modifier
.repprefixok
)
3213 as_bad (_("invalid instruction `%s' after `%s'"),
3214 i
.tm
.name
, i
.rep_prefix
);
3218 /* Check for lock without a lockable instruction. Destination operand
3219 must be memory unless it is xchg (0x86). */
3220 if (i
.prefix
[LOCK_PREFIX
]
3221 && (!i
.tm
.opcode_modifier
.islockable
3222 || i
.mem_operands
== 0
3223 || (i
.tm
.base_opcode
!= 0x86
3224 && !operand_type_check (i
.types
[i
.operands
- 1], anymem
))))
3226 as_bad (_("expecting lockable instruction after `lock'"));
3230 /* Check if HLE prefix is OK. */
3231 if (i
.hle_prefix
&& !check_hle ())
3234 /* Check string instruction segment overrides. */
3235 if (i
.tm
.opcode_modifier
.isstring
&& i
.mem_operands
!= 0)
3237 if (!check_string ())
3239 i
.disp_operands
= 0;
3242 if (!process_suffix ())
3245 /* Update operand types. */
3246 for (j
= 0; j
< i
.operands
; j
++)
3247 i
.types
[j
] = operand_type_and (i
.types
[j
], i
.tm
.operand_types
[j
]);
3249 /* Make still unresolved immediate matches conform to size of immediate
3250 given in i.suffix. */
3251 if (!finalize_imm ())
3254 if (i
.types
[0].bitfield
.imm1
)
3255 i
.imm_operands
= 0; /* kludge for shift insns. */
3257 /* We only need to check those implicit registers for instructions
3258 with 3 operands or less. */
3259 if (i
.operands
<= 3)
3260 for (j
= 0; j
< i
.operands
; j
++)
3261 if (i
.types
[j
].bitfield
.inoutportreg
3262 || i
.types
[j
].bitfield
.shiftcount
3263 || i
.types
[j
].bitfield
.acc
3264 || i
.types
[j
].bitfield
.floatacc
)
3267 /* ImmExt should be processed after SSE2AVX. */
3268 if (!i
.tm
.opcode_modifier
.sse2avx
3269 && i
.tm
.opcode_modifier
.immext
)
3272 /* For insns with operands there are more diddles to do to the opcode. */
3275 if (!process_operands ())
3278 else if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
3280 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
3281 as_warn (_("translating to `%sp'"), i
.tm
.name
);
3284 if (i
.tm
.opcode_modifier
.vex
)
3285 build_vex_prefix (t
);
3287 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
3288 instructions may define INT_OPCODE as well, so avoid this corner
3289 case for those instructions that use MODRM. */
3290 if (i
.tm
.base_opcode
== INT_OPCODE
3291 && !i
.tm
.opcode_modifier
.modrm
3292 && i
.op
[0].imms
->X_add_number
== 3)
3294 i
.tm
.base_opcode
= INT3_OPCODE
;
3298 if ((i
.tm
.opcode_modifier
.jump
3299 || i
.tm
.opcode_modifier
.jumpbyte
3300 || i
.tm
.opcode_modifier
.jumpdword
)
3301 && i
.op
[0].disps
->X_op
== O_constant
)
3303 /* Convert "jmp constant" (and "call constant") to a jump (call) to
3304 the absolute address given by the constant. Since ix86 jumps and
3305 calls are pc relative, we need to generate a reloc. */
3306 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
3307 i
.op
[0].disps
->X_op
= O_symbol
;
3310 if (i
.tm
.opcode_modifier
.rex64
)
3313 /* For 8 bit registers we need an empty rex prefix. Also if the
3314 instruction already has a prefix, we need to convert old
3315 registers to new ones. */
3317 if ((i
.types
[0].bitfield
.reg8
3318 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
3319 || (i
.types
[1].bitfield
.reg8
3320 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
3321 || ((i
.types
[0].bitfield
.reg8
3322 || i
.types
[1].bitfield
.reg8
)
3327 i
.rex
|= REX_OPCODE
;
3328 for (x
= 0; x
< 2; x
++)
3330 /* Look for 8 bit operand that uses old registers. */
3331 if (i
.types
[x
].bitfield
.reg8
3332 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
3334 /* In case it is "hi" register, give up. */
3335 if (i
.op
[x
].regs
->reg_num
> 3)
3336 as_bad (_("can't encode register '%s%s' in an "
3337 "instruction requiring REX prefix."),
3338 register_prefix
, i
.op
[x
].regs
->reg_name
);
3340 /* Otherwise it is equivalent to the extended register.
3341 Since the encoding doesn't change this is merely
3342 cosmetic cleanup for debug output. */
3344 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
3350 add_prefix (REX_OPCODE
| i
.rex
);
3352 /* We are ready to output the insn. */
3357 parse_insn (char *line
, char *mnemonic
)
3360 char *token_start
= l
;
3363 const insn_template
*t
;
3369 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
3374 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
3376 as_bad (_("no such instruction: `%s'"), token_start
);
3381 if (!is_space_char (*l
)
3382 && *l
!= END_OF_INSN
3384 || (*l
!= PREFIX_SEPARATOR
3387 as_bad (_("invalid character %s in mnemonic"),
3388 output_invalid (*l
));
3391 if (token_start
== l
)
3393 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
3394 as_bad (_("expecting prefix; got nothing"));
3396 as_bad (_("expecting mnemonic; got nothing"));
3400 /* Look up instruction (or prefix) via hash table. */
3401 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
3403 if (*l
!= END_OF_INSN
3404 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
3405 && current_templates
3406 && current_templates
->start
->opcode_modifier
.isprefix
)
3408 if (!cpu_flags_check_cpu64 (current_templates
->start
->cpu_flags
))
3410 as_bad ((flag_code
!= CODE_64BIT
3411 ? _("`%s' is only supported in 64-bit mode")
3412 : _("`%s' is not supported in 64-bit mode")),
3413 current_templates
->start
->name
);
3416 /* If we are in 16-bit mode, do not allow addr16 or data16.
3417 Similarly, in 32-bit mode, do not allow addr32 or data32. */
3418 if ((current_templates
->start
->opcode_modifier
.size16
3419 || current_templates
->start
->opcode_modifier
.size32
)
3420 && flag_code
!= CODE_64BIT
3421 && (current_templates
->start
->opcode_modifier
.size32
3422 ^ (flag_code
== CODE_16BIT
)))
3424 as_bad (_("redundant %s prefix"),
3425 current_templates
->start
->name
);
3428 /* Add prefix, checking for repeated prefixes. */
3429 switch (add_prefix (current_templates
->start
->base_opcode
))
3434 if (current_templates
->start
->cpu_flags
.bitfield
.cpuhle
)
3435 i
.hle_prefix
= current_templates
->start
->name
;
3437 i
.rep_prefix
= current_templates
->start
->name
;
3442 /* Skip past PREFIX_SEPARATOR and reset token_start. */
3449 if (!current_templates
)
3451 /* Check if we should swap operand or force 32bit displacement in
3453 if (mnem_p
- 2 == dot_p
&& dot_p
[1] == 's')
3455 else if (mnem_p
- 3 == dot_p
3458 i
.disp_encoding
= disp_encoding_8bit
;
3459 else if (mnem_p
- 4 == dot_p
3463 i
.disp_encoding
= disp_encoding_32bit
;
3468 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
3471 if (!current_templates
)
3474 /* See if we can get a match by trimming off a suffix. */
3477 case WORD_MNEM_SUFFIX
:
3478 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
3479 i
.suffix
= SHORT_MNEM_SUFFIX
;
3481 case BYTE_MNEM_SUFFIX
:
3482 case QWORD_MNEM_SUFFIX
:
3483 i
.suffix
= mnem_p
[-1];
3485 current_templates
= (const templates
*) hash_find (op_hash
,
3488 case SHORT_MNEM_SUFFIX
:
3489 case LONG_MNEM_SUFFIX
:
3492 i
.suffix
= mnem_p
[-1];
3494 current_templates
= (const templates
*) hash_find (op_hash
,
3503 if (intel_float_operand (mnemonic
) == 1)
3504 i
.suffix
= SHORT_MNEM_SUFFIX
;
3506 i
.suffix
= LONG_MNEM_SUFFIX
;
3508 current_templates
= (const templates
*) hash_find (op_hash
,
3513 if (!current_templates
)
3515 as_bad (_("no such instruction: `%s'"), token_start
);
3520 if (current_templates
->start
->opcode_modifier
.jump
3521 || current_templates
->start
->opcode_modifier
.jumpbyte
)
3523 /* Check for a branch hint. We allow ",pt" and ",pn" for
3524 predict taken and predict not taken respectively.
3525 I'm not sure that branch hints actually do anything on loop
3526 and jcxz insns (JumpByte) for current Pentium4 chips. They
3527 may work in the future and it doesn't hurt to accept them
3529 if (l
[0] == ',' && l
[1] == 'p')
3533 if (!add_prefix (DS_PREFIX_OPCODE
))
3537 else if (l
[2] == 'n')
3539 if (!add_prefix (CS_PREFIX_OPCODE
))
3545 /* Any other comma loses. */
3548 as_bad (_("invalid character %s in mnemonic"),
3549 output_invalid (*l
));
3553 /* Check if instruction is supported on specified architecture. */
3555 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
3557 supported
|= cpu_flags_match (t
);
3558 if (supported
== CPU_FLAGS_PERFECT_MATCH
)
3562 if (!(supported
& CPU_FLAGS_64BIT_MATCH
))
3564 as_bad (flag_code
== CODE_64BIT
3565 ? _("`%s' is not supported in 64-bit mode")
3566 : _("`%s' is only supported in 64-bit mode"),
3567 current_templates
->start
->name
);
3570 if (supported
!= CPU_FLAGS_PERFECT_MATCH
)
3572 as_bad (_("`%s' is not supported on `%s%s'"),
3573 current_templates
->start
->name
,
3574 cpu_arch_name
? cpu_arch_name
: default_arch
,
3575 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
3580 if (!cpu_arch_flags
.bitfield
.cpui386
3581 && (flag_code
!= CODE_16BIT
))
3583 as_warn (_("use .code16 to ensure correct addressing mode"));
3590 parse_operands (char *l
, const char *mnemonic
)
3594 /* 1 if operand is pending after ','. */
3595 unsigned int expecting_operand
= 0;
3597 /* Non-zero if operand parens not balanced. */
3598 unsigned int paren_not_balanced
;
3600 while (*l
!= END_OF_INSN
)
3602 /* Skip optional white space before operand. */
3603 if (is_space_char (*l
))
3605 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
)
3607 as_bad (_("invalid character %s before operand %d"),
3608 output_invalid (*l
),
3612 token_start
= l
; /* after white space */
3613 paren_not_balanced
= 0;
3614 while (paren_not_balanced
|| *l
!= ',')
3616 if (*l
== END_OF_INSN
)
3618 if (paren_not_balanced
)
3621 as_bad (_("unbalanced parenthesis in operand %d."),
3624 as_bad (_("unbalanced brackets in operand %d."),
3629 break; /* we are done */
3631 else if (!is_operand_char (*l
) && !is_space_char (*l
))
3633 as_bad (_("invalid character %s in operand %d"),
3634 output_invalid (*l
),
3641 ++paren_not_balanced
;
3643 --paren_not_balanced
;
3648 ++paren_not_balanced
;
3650 --paren_not_balanced
;
3654 if (l
!= token_start
)
3655 { /* Yes, we've read in another operand. */
3656 unsigned int operand_ok
;
3657 this_operand
= i
.operands
++;
3658 i
.types
[this_operand
].bitfield
.unspecified
= 1;
3659 if (i
.operands
> MAX_OPERANDS
)
3661 as_bad (_("spurious operands; (%d operands/instruction max)"),
3665 /* Now parse operand adding info to 'i' as we go along. */
3666 END_STRING_AND_SAVE (l
);
3670 i386_intel_operand (token_start
,
3671 intel_float_operand (mnemonic
));
3673 operand_ok
= i386_att_operand (token_start
);
3675 RESTORE_END_STRING (l
);
3681 if (expecting_operand
)
3683 expecting_operand_after_comma
:
3684 as_bad (_("expecting operand after ','; got nothing"));
3689 as_bad (_("expecting operand before ','; got nothing"));
3694 /* Now *l must be either ',' or END_OF_INSN. */
3697 if (*++l
== END_OF_INSN
)
3699 /* Just skip it, if it's \n complain. */
3700 goto expecting_operand_after_comma
;
3702 expecting_operand
= 1;
3709 swap_2_operands (int xchg1
, int xchg2
)
3711 union i386_op temp_op
;
3712 i386_operand_type temp_type
;
3713 enum bfd_reloc_code_real temp_reloc
;
3715 temp_type
= i
.types
[xchg2
];
3716 i
.types
[xchg2
] = i
.types
[xchg1
];
3717 i
.types
[xchg1
] = temp_type
;
3718 temp_op
= i
.op
[xchg2
];
3719 i
.op
[xchg2
] = i
.op
[xchg1
];
3720 i
.op
[xchg1
] = temp_op
;
3721 temp_reloc
= i
.reloc
[xchg2
];
3722 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
3723 i
.reloc
[xchg1
] = temp_reloc
;
3727 swap_operands (void)
3733 swap_2_operands (1, i
.operands
- 2);
3736 swap_2_operands (0, i
.operands
- 1);
3742 if (i
.mem_operands
== 2)
3744 const seg_entry
*temp_seg
;
3745 temp_seg
= i
.seg
[0];
3746 i
.seg
[0] = i
.seg
[1];
3747 i
.seg
[1] = temp_seg
;
3751 /* Try to ensure constant immediates are represented in the smallest
3756 char guess_suffix
= 0;
3760 guess_suffix
= i
.suffix
;
3761 else if (i
.reg_operands
)
3763 /* Figure out a suffix from the last register operand specified.
3764 We can't do this properly yet, ie. excluding InOutPortReg,
3765 but the following works for instructions with immediates.
3766 In any case, we can't set i.suffix yet. */
3767 for (op
= i
.operands
; --op
>= 0;)
3768 if (i
.types
[op
].bitfield
.reg8
)
3770 guess_suffix
= BYTE_MNEM_SUFFIX
;
3773 else if (i
.types
[op
].bitfield
.reg16
)
3775 guess_suffix
= WORD_MNEM_SUFFIX
;
3778 else if (i
.types
[op
].bitfield
.reg32
)
3780 guess_suffix
= LONG_MNEM_SUFFIX
;
3783 else if (i
.types
[op
].bitfield
.reg64
)
3785 guess_suffix
= QWORD_MNEM_SUFFIX
;
3789 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
3790 guess_suffix
= WORD_MNEM_SUFFIX
;
3792 for (op
= i
.operands
; --op
>= 0;)
3793 if (operand_type_check (i
.types
[op
], imm
))
3795 switch (i
.op
[op
].imms
->X_op
)
3798 /* If a suffix is given, this operand may be shortened. */
3799 switch (guess_suffix
)
3801 case LONG_MNEM_SUFFIX
:
3802 i
.types
[op
].bitfield
.imm32
= 1;
3803 i
.types
[op
].bitfield
.imm64
= 1;
3805 case WORD_MNEM_SUFFIX
:
3806 i
.types
[op
].bitfield
.imm16
= 1;
3807 i
.types
[op
].bitfield
.imm32
= 1;
3808 i
.types
[op
].bitfield
.imm32s
= 1;
3809 i
.types
[op
].bitfield
.imm64
= 1;
3811 case BYTE_MNEM_SUFFIX
:
3812 i
.types
[op
].bitfield
.imm8
= 1;
3813 i
.types
[op
].bitfield
.imm8s
= 1;
3814 i
.types
[op
].bitfield
.imm16
= 1;
3815 i
.types
[op
].bitfield
.imm32
= 1;
3816 i
.types
[op
].bitfield
.imm32s
= 1;
3817 i
.types
[op
].bitfield
.imm64
= 1;
3821 /* If this operand is at most 16 bits, convert it
3822 to a signed 16 bit number before trying to see
3823 whether it will fit in an even smaller size.
3824 This allows a 16-bit operand such as $0xffe0 to
3825 be recognised as within Imm8S range. */
3826 if ((i
.types
[op
].bitfield
.imm16
)
3827 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
3829 i
.op
[op
].imms
->X_add_number
=
3830 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
3832 if ((i
.types
[op
].bitfield
.imm32
)
3833 && ((i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1))
3836 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
3837 ^ ((offsetT
) 1 << 31))
3838 - ((offsetT
) 1 << 31));
3841 = operand_type_or (i
.types
[op
],
3842 smallest_imm_type (i
.op
[op
].imms
->X_add_number
));
3844 /* We must avoid matching of Imm32 templates when 64bit
3845 only immediate is available. */
3846 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
3847 i
.types
[op
].bitfield
.imm32
= 0;
3854 /* Symbols and expressions. */
3856 /* Convert symbolic operand to proper sizes for matching, but don't
3857 prevent matching a set of insns that only supports sizes other
3858 than those matching the insn suffix. */
3860 i386_operand_type mask
, allowed
;
3861 const insn_template
*t
;
3863 operand_type_set (&mask
, 0);
3864 operand_type_set (&allowed
, 0);
3866 for (t
= current_templates
->start
;
3867 t
< current_templates
->end
;
3869 allowed
= operand_type_or (allowed
,
3870 t
->operand_types
[op
]);
3871 switch (guess_suffix
)
3873 case QWORD_MNEM_SUFFIX
:
3874 mask
.bitfield
.imm64
= 1;
3875 mask
.bitfield
.imm32s
= 1;
3877 case LONG_MNEM_SUFFIX
:
3878 mask
.bitfield
.imm32
= 1;
3880 case WORD_MNEM_SUFFIX
:
3881 mask
.bitfield
.imm16
= 1;
3883 case BYTE_MNEM_SUFFIX
:
3884 mask
.bitfield
.imm8
= 1;
3889 allowed
= operand_type_and (mask
, allowed
);
3890 if (!operand_type_all_zero (&allowed
))
3891 i
.types
[op
] = operand_type_and (i
.types
[op
], mask
);
3898 /* Try to use the smallest displacement type too. */
3900 optimize_disp (void)
3904 for (op
= i
.operands
; --op
>= 0;)
3905 if (operand_type_check (i
.types
[op
], disp
))
3907 if (i
.op
[op
].disps
->X_op
== O_constant
)
3909 offsetT op_disp
= i
.op
[op
].disps
->X_add_number
;
3911 if (i
.types
[op
].bitfield
.disp16
3912 && (op_disp
& ~(offsetT
) 0xffff) == 0)
3914 /* If this operand is at most 16 bits, convert
3915 to a signed 16 bit number and don't use 64bit
3917 op_disp
= (((op_disp
& 0xffff) ^ 0x8000) - 0x8000);
3918 i
.types
[op
].bitfield
.disp64
= 0;
3920 if (i
.types
[op
].bitfield
.disp32
3921 && (op_disp
& ~(((offsetT
) 2 << 31) - 1)) == 0)
3923 /* If this operand is at most 32 bits, convert
3924 to a signed 32 bit number and don't use 64bit
3926 op_disp
&= (((offsetT
) 2 << 31) - 1);
3927 op_disp
= (op_disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
3928 i
.types
[op
].bitfield
.disp64
= 0;
3930 if (!op_disp
&& i
.types
[op
].bitfield
.baseindex
)
3932 i
.types
[op
].bitfield
.disp8
= 0;
3933 i
.types
[op
].bitfield
.disp16
= 0;
3934 i
.types
[op
].bitfield
.disp32
= 0;
3935 i
.types
[op
].bitfield
.disp32s
= 0;
3936 i
.types
[op
].bitfield
.disp64
= 0;
3940 else if (flag_code
== CODE_64BIT
)
3942 if (fits_in_signed_long (op_disp
))
3944 i
.types
[op
].bitfield
.disp64
= 0;
3945 i
.types
[op
].bitfield
.disp32s
= 1;
3947 if (i
.prefix
[ADDR_PREFIX
]
3948 && fits_in_unsigned_long (op_disp
))
3949 i
.types
[op
].bitfield
.disp32
= 1;
3951 if ((i
.types
[op
].bitfield
.disp32
3952 || i
.types
[op
].bitfield
.disp32s
3953 || i
.types
[op
].bitfield
.disp16
)
3954 && fits_in_signed_byte (op_disp
))
3955 i
.types
[op
].bitfield
.disp8
= 1;
3957 else if (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
3958 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
)
3960 fix_new_exp (frag_now
, frag_more (0) - frag_now
->fr_literal
, 0,
3961 i
.op
[op
].disps
, 0, i
.reloc
[op
]);
3962 i
.types
[op
].bitfield
.disp8
= 0;
3963 i
.types
[op
].bitfield
.disp16
= 0;
3964 i
.types
[op
].bitfield
.disp32
= 0;
3965 i
.types
[op
].bitfield
.disp32s
= 0;
3966 i
.types
[op
].bitfield
.disp64
= 0;
3969 /* We only support 64bit displacement on constants. */
3970 i
.types
[op
].bitfield
.disp64
= 0;
3974 /* Check if operands are valid for the instruction. */
3977 check_VecOperands (const insn_template
*t
)
3979 /* Without VSIB byte, we can't have a vector register for index. */
3980 if (!t
->opcode_modifier
.vecsib
3982 && (i
.index_reg
->reg_type
.bitfield
.regxmm
3983 || i
.index_reg
->reg_type
.bitfield
.regymm
))
3985 i
.error
= unsupported_vector_index_register
;
3989 /* For VSIB byte, we need a vector register for index, and all vector
3990 registers must be distinct. */
3991 if (t
->opcode_modifier
.vecsib
)
3994 || !((t
->opcode_modifier
.vecsib
== VecSIB128
3995 && i
.index_reg
->reg_type
.bitfield
.regxmm
)
3996 || (t
->opcode_modifier
.vecsib
== VecSIB256
3997 && i
.index_reg
->reg_type
.bitfield
.regymm
)))
3999 i
.error
= invalid_vsib_address
;
4003 gas_assert (i
.reg_operands
== 2);
4004 gas_assert (i
.types
[0].bitfield
.regxmm
4005 || i
.types
[0].bitfield
.regymm
);
4006 gas_assert (i
.types
[2].bitfield
.regxmm
4007 || i
.types
[2].bitfield
.regymm
);
4009 if (operand_check
== check_none
)
4011 if (register_number (i
.op
[0].regs
) != register_number (i
.index_reg
)
4012 && register_number (i
.op
[2].regs
) != register_number (i
.index_reg
)
4013 && register_number (i
.op
[0].regs
) != register_number (i
.op
[2].regs
))
4015 if (operand_check
== check_error
)
4017 i
.error
= invalid_vector_register_set
;
4020 as_warn (_("mask, index, and destination registers should be distinct"));
4026 /* Check if operands are valid for the instruction. Update VEX
4030 VEX_check_operands (const insn_template
*t
)
4032 if (!t
->opcode_modifier
.vex
)
4035 /* Only check VEX_Imm4, which must be the first operand. */
4036 if (t
->operand_types
[0].bitfield
.vec_imm4
)
4038 if (i
.op
[0].imms
->X_op
!= O_constant
4039 || !fits_in_imm4 (i
.op
[0].imms
->X_add_number
))
4045 /* Turn off Imm8 so that update_imm won't complain. */
4046 i
.types
[0] = vec_imm4
;
4052 static const insn_template
*
4053 match_template (void)
4055 /* Points to template once we've found it. */
4056 const insn_template
*t
;
4057 i386_operand_type overlap0
, overlap1
, overlap2
, overlap3
;
4058 i386_operand_type overlap4
;
4059 unsigned int found_reverse_match
;
4060 i386_opcode_modifier suffix_check
;
4061 i386_operand_type operand_types
[MAX_OPERANDS
];
4062 int addr_prefix_disp
;
4064 unsigned int found_cpu_match
;
4065 unsigned int check_register
;
4066 enum i386_error specific_error
= 0;
4068 #if MAX_OPERANDS != 5
4069 # error "MAX_OPERANDS must be 5."
4072 found_reverse_match
= 0;
4073 addr_prefix_disp
= -1;
4075 memset (&suffix_check
, 0, sizeof (suffix_check
));
4076 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
4077 suffix_check
.no_bsuf
= 1;
4078 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
4079 suffix_check
.no_wsuf
= 1;
4080 else if (i
.suffix
== SHORT_MNEM_SUFFIX
)
4081 suffix_check
.no_ssuf
= 1;
4082 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
4083 suffix_check
.no_lsuf
= 1;
4084 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
4085 suffix_check
.no_qsuf
= 1;
4086 else if (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
)
4087 suffix_check
.no_ldsuf
= 1;
4089 /* Must have right number of operands. */
4090 i
.error
= number_of_operands_mismatch
;
4092 for (t
= current_templates
->start
; t
< current_templates
->end
; t
++)
4094 addr_prefix_disp
= -1;
4096 if (i
.operands
!= t
->operands
)
4099 /* Check processor support. */
4100 i
.error
= unsupported
;
4101 found_cpu_match
= (cpu_flags_match (t
)
4102 == CPU_FLAGS_PERFECT_MATCH
);
4103 if (!found_cpu_match
)
4106 /* Check old gcc support. */
4107 i
.error
= old_gcc_only
;
4108 if (!old_gcc
&& t
->opcode_modifier
.oldgcc
)
4111 /* Check AT&T mnemonic. */
4112 i
.error
= unsupported_with_intel_mnemonic
;
4113 if (intel_mnemonic
&& t
->opcode_modifier
.attmnemonic
)
4116 /* Check AT&T/Intel syntax. */
4117 i
.error
= unsupported_syntax
;
4118 if ((intel_syntax
&& t
->opcode_modifier
.attsyntax
)
4119 || (!intel_syntax
&& t
->opcode_modifier
.intelsyntax
))
4122 /* Check the suffix, except for some instructions in intel mode. */
4123 i
.error
= invalid_instruction_suffix
;
4124 if ((!intel_syntax
|| !t
->opcode_modifier
.ignoresize
)
4125 && ((t
->opcode_modifier
.no_bsuf
&& suffix_check
.no_bsuf
)
4126 || (t
->opcode_modifier
.no_wsuf
&& suffix_check
.no_wsuf
)
4127 || (t
->opcode_modifier
.no_lsuf
&& suffix_check
.no_lsuf
)
4128 || (t
->opcode_modifier
.no_ssuf
&& suffix_check
.no_ssuf
)
4129 || (t
->opcode_modifier
.no_qsuf
&& suffix_check
.no_qsuf
)
4130 || (t
->opcode_modifier
.no_ldsuf
&& suffix_check
.no_ldsuf
)))
4133 if (!operand_size_match (t
))
4136 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4137 operand_types
[j
] = t
->operand_types
[j
];
4139 /* In general, don't allow 64-bit operands in 32-bit mode. */
4140 if (i
.suffix
== QWORD_MNEM_SUFFIX
4141 && flag_code
!= CODE_64BIT
4143 ? (!t
->opcode_modifier
.ignoresize
4144 && !intel_float_operand (t
->name
))
4145 : intel_float_operand (t
->name
) != 2)
4146 && ((!operand_types
[0].bitfield
.regmmx
4147 && !operand_types
[0].bitfield
.regxmm
4148 && !operand_types
[0].bitfield
.regymm
)
4149 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
4150 && !!operand_types
[t
->operands
> 1].bitfield
.regxmm
4151 && !!operand_types
[t
->operands
> 1].bitfield
.regymm
))
4152 && (t
->base_opcode
!= 0x0fc7
4153 || t
->extension_opcode
!= 1 /* cmpxchg8b */))
4156 /* In general, don't allow 32-bit operands on pre-386. */
4157 else if (i
.suffix
== LONG_MNEM_SUFFIX
4158 && !cpu_arch_flags
.bitfield
.cpui386
4160 ? (!t
->opcode_modifier
.ignoresize
4161 && !intel_float_operand (t
->name
))
4162 : intel_float_operand (t
->name
) != 2)
4163 && ((!operand_types
[0].bitfield
.regmmx
4164 && !operand_types
[0].bitfield
.regxmm
)
4165 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
4166 && !!operand_types
[t
->operands
> 1].bitfield
.regxmm
)))
4169 /* Do not verify operands when there are none. */
4173 /* We've found a match; break out of loop. */
4177 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
4178 into Disp32/Disp16/Disp32 operand. */
4179 if (i
.prefix
[ADDR_PREFIX
] != 0)
4181 /* There should be only one Disp operand. */
4185 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4187 if (operand_types
[j
].bitfield
.disp16
)
4189 addr_prefix_disp
= j
;
4190 operand_types
[j
].bitfield
.disp32
= 1;
4191 operand_types
[j
].bitfield
.disp16
= 0;
4197 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4199 if (operand_types
[j
].bitfield
.disp32
)
4201 addr_prefix_disp
= j
;
4202 operand_types
[j
].bitfield
.disp32
= 0;
4203 operand_types
[j
].bitfield
.disp16
= 1;
4209 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4211 if (operand_types
[j
].bitfield
.disp64
)
4213 addr_prefix_disp
= j
;
4214 operand_types
[j
].bitfield
.disp64
= 0;
4215 operand_types
[j
].bitfield
.disp32
= 1;
4223 /* We check register size if needed. */
4224 check_register
= t
->opcode_modifier
.checkregsize
;
4225 overlap0
= operand_type_and (i
.types
[0], operand_types
[0]);
4226 switch (t
->operands
)
4229 if (!operand_type_match (overlap0
, i
.types
[0]))
4233 /* xchg %eax, %eax is a special case. It is an aliase for nop
4234 only in 32bit mode and we can use opcode 0x90. In 64bit
4235 mode, we can't use 0x90 for xchg %eax, %eax since it should
4236 zero-extend %eax to %rax. */
4237 if (flag_code
== CODE_64BIT
4238 && t
->base_opcode
== 0x90
4239 && operand_type_equal (&i
.types
[0], &acc32
)
4240 && operand_type_equal (&i
.types
[1], &acc32
))
4244 /* If we swap operand in encoding, we either match
4245 the next one or reverse direction of operands. */
4246 if (t
->opcode_modifier
.s
)
4248 else if (t
->opcode_modifier
.d
)
4253 /* If we swap operand in encoding, we match the next one. */
4254 if (i
.swap_operand
&& t
->opcode_modifier
.s
)
4258 overlap1
= operand_type_and (i
.types
[1], operand_types
[1]);
4259 if (!operand_type_match (overlap0
, i
.types
[0])
4260 || !operand_type_match (overlap1
, i
.types
[1])
4262 && !operand_type_register_match (overlap0
, i
.types
[0],
4264 overlap1
, i
.types
[1],
4267 /* Check if other direction is valid ... */
4268 if (!t
->opcode_modifier
.d
&& !t
->opcode_modifier
.floatd
)
4272 /* Try reversing direction of operands. */
4273 overlap0
= operand_type_and (i
.types
[0], operand_types
[1]);
4274 overlap1
= operand_type_and (i
.types
[1], operand_types
[0]);
4275 if (!operand_type_match (overlap0
, i
.types
[0])
4276 || !operand_type_match (overlap1
, i
.types
[1])
4278 && !operand_type_register_match (overlap0
,
4285 /* Does not match either direction. */
4288 /* found_reverse_match holds which of D or FloatDR
4290 if (t
->opcode_modifier
.d
)
4291 found_reverse_match
= Opcode_D
;
4292 else if (t
->opcode_modifier
.floatd
)
4293 found_reverse_match
= Opcode_FloatD
;
4295 found_reverse_match
= 0;
4296 if (t
->opcode_modifier
.floatr
)
4297 found_reverse_match
|= Opcode_FloatR
;
4301 /* Found a forward 2 operand match here. */
4302 switch (t
->operands
)
4305 overlap4
= operand_type_and (i
.types
[4],
4308 overlap3
= operand_type_and (i
.types
[3],
4311 overlap2
= operand_type_and (i
.types
[2],
4316 switch (t
->operands
)
4319 if (!operand_type_match (overlap4
, i
.types
[4])
4320 || !operand_type_register_match (overlap3
,
4328 if (!operand_type_match (overlap3
, i
.types
[3])
4330 && !operand_type_register_match (overlap2
,
4338 /* Here we make use of the fact that there are no
4339 reverse match 3 operand instructions, and all 3
4340 operand instructions only need to be checked for
4341 register consistency between operands 2 and 3. */
4342 if (!operand_type_match (overlap2
, i
.types
[2])
4344 && !operand_type_register_match (overlap1
,
4354 /* Found either forward/reverse 2, 3 or 4 operand match here:
4355 slip through to break. */
4357 if (!found_cpu_match
)
4359 found_reverse_match
= 0;
4363 /* Check if vector and VEX operands are valid. */
4364 if (check_VecOperands (t
) || VEX_check_operands (t
))
4366 specific_error
= i
.error
;
4370 /* We've found a match; break out of loop. */
4374 if (t
== current_templates
->end
)
4376 /* We found no match. */
4377 const char *err_msg
;
4378 switch (specific_error
? specific_error
: i
.error
)
4382 case operand_size_mismatch
:
4383 err_msg
= _("operand size mismatch");
4385 case operand_type_mismatch
:
4386 err_msg
= _("operand type mismatch");
4388 case register_type_mismatch
:
4389 err_msg
= _("register type mismatch");
4391 case number_of_operands_mismatch
:
4392 err_msg
= _("number of operands mismatch");
4394 case invalid_instruction_suffix
:
4395 err_msg
= _("invalid instruction suffix");
4398 err_msg
= _("constant doesn't fit in 4 bits");
4401 err_msg
= _("only supported with old gcc");
4403 case unsupported_with_intel_mnemonic
:
4404 err_msg
= _("unsupported with Intel mnemonic");
4406 case unsupported_syntax
:
4407 err_msg
= _("unsupported syntax");
4410 as_bad (_("unsupported instruction `%s'"),
4411 current_templates
->start
->name
);
4413 case invalid_vsib_address
:
4414 err_msg
= _("invalid VSIB address");
4416 case invalid_vector_register_set
:
4417 err_msg
= _("mask, index, and destination registers must be distinct");
4419 case unsupported_vector_index_register
:
4420 err_msg
= _("unsupported vector index register");
4423 as_bad (_("%s for `%s'"), err_msg
,
4424 current_templates
->start
->name
);
4428 if (!quiet_warnings
)
4431 && (i
.types
[0].bitfield
.jumpabsolute
4432 != operand_types
[0].bitfield
.jumpabsolute
))
4434 as_warn (_("indirect %s without `*'"), t
->name
);
4437 if (t
->opcode_modifier
.isprefix
4438 && t
->opcode_modifier
.ignoresize
)
4440 /* Warn them that a data or address size prefix doesn't
4441 affect assembly of the next line of code. */
4442 as_warn (_("stand-alone `%s' prefix"), t
->name
);
4446 /* Copy the template we found. */
4449 if (addr_prefix_disp
!= -1)
4450 i
.tm
.operand_types
[addr_prefix_disp
]
4451 = operand_types
[addr_prefix_disp
];
4453 if (found_reverse_match
)
4455 /* If we found a reverse match we must alter the opcode
4456 direction bit. found_reverse_match holds bits to change
4457 (different for int & float insns). */
4459 i
.tm
.base_opcode
^= found_reverse_match
;
4461 i
.tm
.operand_types
[0] = operand_types
[1];
4462 i
.tm
.operand_types
[1] = operand_types
[0];
4471 int mem_op
= operand_type_check (i
.types
[0], anymem
) ? 0 : 1;
4472 if (i
.tm
.operand_types
[mem_op
].bitfield
.esseg
)
4474 if (i
.seg
[0] != NULL
&& i
.seg
[0] != &es
)
4476 as_bad (_("`%s' operand %d must use `%ses' segment"),
4482 /* There's only ever one segment override allowed per instruction.
4483 This instruction possibly has a legal segment override on the
4484 second operand, so copy the segment to where non-string
4485 instructions store it, allowing common code. */
4486 i
.seg
[0] = i
.seg
[1];
4488 else if (i
.tm
.operand_types
[mem_op
+ 1].bitfield
.esseg
)
4490 if (i
.seg
[1] != NULL
&& i
.seg
[1] != &es
)
4492 as_bad (_("`%s' operand %d must use `%ses' segment"),
4503 process_suffix (void)
4505 /* If matched instruction specifies an explicit instruction mnemonic
4507 if (i
.tm
.opcode_modifier
.size16
)
4508 i
.suffix
= WORD_MNEM_SUFFIX
;
4509 else if (i
.tm
.opcode_modifier
.size32
)
4510 i
.suffix
= LONG_MNEM_SUFFIX
;
4511 else if (i
.tm
.opcode_modifier
.size64
)
4512 i
.suffix
= QWORD_MNEM_SUFFIX
;
4513 else if (i
.reg_operands
)
4515 /* If there's no instruction mnemonic suffix we try to invent one
4516 based on register operands. */
4519 /* We take i.suffix from the last register operand specified,
4520 Destination register type is more significant than source
4521 register type. crc32 in SSE4.2 prefers source register
4523 if (i
.tm
.base_opcode
== 0xf20f38f1)
4525 if (i
.types
[0].bitfield
.reg16
)
4526 i
.suffix
= WORD_MNEM_SUFFIX
;
4527 else if (i
.types
[0].bitfield
.reg32
)
4528 i
.suffix
= LONG_MNEM_SUFFIX
;
4529 else if (i
.types
[0].bitfield
.reg64
)
4530 i
.suffix
= QWORD_MNEM_SUFFIX
;
4532 else if (i
.tm
.base_opcode
== 0xf20f38f0)
4534 if (i
.types
[0].bitfield
.reg8
)
4535 i
.suffix
= BYTE_MNEM_SUFFIX
;
4542 if (i
.tm
.base_opcode
== 0xf20f38f1
4543 || i
.tm
.base_opcode
== 0xf20f38f0)
4545 /* We have to know the operand size for crc32. */
4546 as_bad (_("ambiguous memory operand size for `%s`"),
4551 for (op
= i
.operands
; --op
>= 0;)
4552 if (!i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
4554 if (i
.types
[op
].bitfield
.reg8
)
4556 i
.suffix
= BYTE_MNEM_SUFFIX
;
4559 else if (i
.types
[op
].bitfield
.reg16
)
4561 i
.suffix
= WORD_MNEM_SUFFIX
;
4564 else if (i
.types
[op
].bitfield
.reg32
)
4566 i
.suffix
= LONG_MNEM_SUFFIX
;
4569 else if (i
.types
[op
].bitfield
.reg64
)
4571 i
.suffix
= QWORD_MNEM_SUFFIX
;
4577 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
4580 && i
.tm
.opcode_modifier
.ignoresize
4581 && i
.tm
.opcode_modifier
.no_bsuf
)
4583 else if (!check_byte_reg ())
4586 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
4589 && i
.tm
.opcode_modifier
.ignoresize
4590 && i
.tm
.opcode_modifier
.no_lsuf
)
4592 else if (!check_long_reg ())
4595 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
4598 && i
.tm
.opcode_modifier
.ignoresize
4599 && i
.tm
.opcode_modifier
.no_qsuf
)
4601 else if (!check_qword_reg ())
4604 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
4607 && i
.tm
.opcode_modifier
.ignoresize
4608 && i
.tm
.opcode_modifier
.no_wsuf
)
4610 else if (!check_word_reg ())
4613 else if (i
.suffix
== XMMWORD_MNEM_SUFFIX
4614 || i
.suffix
== YMMWORD_MNEM_SUFFIX
)
4616 /* Skip if the instruction has x/y suffix. match_template
4617 should check if it is a valid suffix. */
4619 else if (intel_syntax
&& i
.tm
.opcode_modifier
.ignoresize
)
4620 /* Do nothing if the instruction is going to ignore the prefix. */
4625 else if (i
.tm
.opcode_modifier
.defaultsize
4627 /* exclude fldenv/frstor/fsave/fstenv */
4628 && i
.tm
.opcode_modifier
.no_ssuf
)
4630 i
.suffix
= stackop_size
;
4632 else if (intel_syntax
4634 && (i
.tm
.operand_types
[0].bitfield
.jumpabsolute
4635 || i
.tm
.opcode_modifier
.jumpbyte
4636 || i
.tm
.opcode_modifier
.jumpintersegment
4637 || (i
.tm
.base_opcode
== 0x0f01 /* [ls][gi]dt */
4638 && i
.tm
.extension_opcode
<= 3)))
4643 if (!i
.tm
.opcode_modifier
.no_qsuf
)
4645 i
.suffix
= QWORD_MNEM_SUFFIX
;
4649 if (!i
.tm
.opcode_modifier
.no_lsuf
)
4650 i
.suffix
= LONG_MNEM_SUFFIX
;
4653 if (!i
.tm
.opcode_modifier
.no_wsuf
)
4654 i
.suffix
= WORD_MNEM_SUFFIX
;
4663 if (i
.tm
.opcode_modifier
.w
)
4665 as_bad (_("no instruction mnemonic suffix given and "
4666 "no register operands; can't size instruction"));
4672 unsigned int suffixes
;
4674 suffixes
= !i
.tm
.opcode_modifier
.no_bsuf
;
4675 if (!i
.tm
.opcode_modifier
.no_wsuf
)
4677 if (!i
.tm
.opcode_modifier
.no_lsuf
)
4679 if (!i
.tm
.opcode_modifier
.no_ldsuf
)
4681 if (!i
.tm
.opcode_modifier
.no_ssuf
)
4683 if (!i
.tm
.opcode_modifier
.no_qsuf
)
4686 /* There are more than suffix matches. */
4687 if (i
.tm
.opcode_modifier
.w
4688 || ((suffixes
& (suffixes
- 1))
4689 && !i
.tm
.opcode_modifier
.defaultsize
4690 && !i
.tm
.opcode_modifier
.ignoresize
))
4692 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
4698 /* Change the opcode based on the operand size given by i.suffix;
4699 We don't need to change things for byte insns. */
4702 && i
.suffix
!= BYTE_MNEM_SUFFIX
4703 && i
.suffix
!= XMMWORD_MNEM_SUFFIX
4704 && i
.suffix
!= YMMWORD_MNEM_SUFFIX
)
4706 /* It's not a byte, select word/dword operation. */
4707 if (i
.tm
.opcode_modifier
.w
)
4709 if (i
.tm
.opcode_modifier
.shortform
)
4710 i
.tm
.base_opcode
|= 8;
4712 i
.tm
.base_opcode
|= 1;
4715 /* Now select between word & dword operations via the operand
4716 size prefix, except for instructions that will ignore this
4718 if (i
.tm
.opcode_modifier
.addrprefixop0
)
4720 /* The address size override prefix changes the size of the
4722 if ((flag_code
== CODE_32BIT
4723 && i
.op
->regs
[0].reg_type
.bitfield
.reg16
)
4724 || (flag_code
!= CODE_32BIT
4725 && i
.op
->regs
[0].reg_type
.bitfield
.reg32
))
4726 if (!add_prefix (ADDR_PREFIX_OPCODE
))
4729 else if (i
.suffix
!= QWORD_MNEM_SUFFIX
4730 && i
.suffix
!= LONG_DOUBLE_MNEM_SUFFIX
4731 && !i
.tm
.opcode_modifier
.ignoresize
4732 && !i
.tm
.opcode_modifier
.floatmf
4733 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
4734 || (flag_code
== CODE_64BIT
4735 && i
.tm
.opcode_modifier
.jumpbyte
)))
4737 unsigned int prefix
= DATA_PREFIX_OPCODE
;
4739 if (i
.tm
.opcode_modifier
.jumpbyte
) /* jcxz, loop */
4740 prefix
= ADDR_PREFIX_OPCODE
;
4742 if (!add_prefix (prefix
))
4746 /* Set mode64 for an operand. */
4747 if (i
.suffix
== QWORD_MNEM_SUFFIX
4748 && flag_code
== CODE_64BIT
4749 && !i
.tm
.opcode_modifier
.norex64
)
4751 /* Special case for xchg %rax,%rax. It is NOP and doesn't
4752 need rex64. cmpxchg8b is also a special case. */
4753 if (! (i
.operands
== 2
4754 && i
.tm
.base_opcode
== 0x90
4755 && i
.tm
.extension_opcode
== None
4756 && operand_type_equal (&i
.types
[0], &acc64
)
4757 && operand_type_equal (&i
.types
[1], &acc64
))
4758 && ! (i
.operands
== 1
4759 && i
.tm
.base_opcode
== 0xfc7
4760 && i
.tm
.extension_opcode
== 1
4761 && !operand_type_check (i
.types
[0], reg
)
4762 && operand_type_check (i
.types
[0], anymem
)))
4766 /* Size floating point instruction. */
4767 if (i
.suffix
== LONG_MNEM_SUFFIX
)
4768 if (i
.tm
.opcode_modifier
.floatmf
)
4769 i
.tm
.base_opcode
^= 4;
4776 check_byte_reg (void)
4780 for (op
= i
.operands
; --op
>= 0;)
4782 /* If this is an eight bit register, it's OK. If it's the 16 or
4783 32 bit version of an eight bit register, we will just use the
4784 low portion, and that's OK too. */
4785 if (i
.types
[op
].bitfield
.reg8
)
4788 /* I/O port address operands are OK too. */
4789 if (i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
4792 /* crc32 doesn't generate this warning. */
4793 if (i
.tm
.base_opcode
== 0xf20f38f0)
4796 if ((i
.types
[op
].bitfield
.reg16
4797 || i
.types
[op
].bitfield
.reg32
4798 || i
.types
[op
].bitfield
.reg64
)
4799 && i
.op
[op
].regs
->reg_num
< 4
4800 /* Prohibit these changes in 64bit mode, since the lowering
4801 would be more complicated. */
4802 && flag_code
!= CODE_64BIT
)
4804 #if REGISTER_WARNINGS
4805 if (!quiet_warnings
)
4806 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4808 (i
.op
[op
].regs
+ (i
.types
[op
].bitfield
.reg16
4809 ? REGNAM_AL
- REGNAM_AX
4810 : REGNAM_AL
- REGNAM_EAX
))->reg_name
,
4812 i
.op
[op
].regs
->reg_name
,
4817 /* Any other register is bad. */
4818 if (i
.types
[op
].bitfield
.reg16
4819 || i
.types
[op
].bitfield
.reg32
4820 || i
.types
[op
].bitfield
.reg64
4821 || i
.types
[op
].bitfield
.regmmx
4822 || i
.types
[op
].bitfield
.regxmm
4823 || i
.types
[op
].bitfield
.regymm
4824 || i
.types
[op
].bitfield
.sreg2
4825 || i
.types
[op
].bitfield
.sreg3
4826 || i
.types
[op
].bitfield
.control
4827 || i
.types
[op
].bitfield
.debug
4828 || i
.types
[op
].bitfield
.test
4829 || i
.types
[op
].bitfield
.floatreg
4830 || i
.types
[op
].bitfield
.floatacc
)
4832 as_bad (_("`%s%s' not allowed with `%s%c'"),
4834 i
.op
[op
].regs
->reg_name
,
4844 check_long_reg (void)
4848 for (op
= i
.operands
; --op
>= 0;)
4849 /* Reject eight bit registers, except where the template requires
4850 them. (eg. movzb) */
4851 if (i
.types
[op
].bitfield
.reg8
4852 && (i
.tm
.operand_types
[op
].bitfield
.reg16
4853 || i
.tm
.operand_types
[op
].bitfield
.reg32
4854 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4856 as_bad (_("`%s%s' not allowed with `%s%c'"),
4858 i
.op
[op
].regs
->reg_name
,
4863 /* Warn if the e prefix on a general reg is missing. */
4864 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
4865 && i
.types
[op
].bitfield
.reg16
4866 && (i
.tm
.operand_types
[op
].bitfield
.reg32
4867 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4869 /* Prohibit these changes in the 64bit mode, since the
4870 lowering is more complicated. */
4871 if (flag_code
== CODE_64BIT
)
4873 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
4874 register_prefix
, i
.op
[op
].regs
->reg_name
,
4878 #if REGISTER_WARNINGS
4880 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4882 (i
.op
[op
].regs
+ REGNAM_EAX
- REGNAM_AX
)->reg_name
,
4884 i
.op
[op
].regs
->reg_name
,
4888 /* Warn if the r prefix on a general reg is missing. */
4889 else if (i
.types
[op
].bitfield
.reg64
4890 && (i
.tm
.operand_types
[op
].bitfield
.reg32
4891 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4894 && i
.tm
.opcode_modifier
.toqword
4895 && !i
.types
[0].bitfield
.regxmm
)
4897 /* Convert to QWORD. We want REX byte. */
4898 i
.suffix
= QWORD_MNEM_SUFFIX
;
4902 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
4903 register_prefix
, i
.op
[op
].regs
->reg_name
,
4912 check_qword_reg (void)
4916 for (op
= i
.operands
; --op
>= 0; )
4917 /* Reject eight bit registers, except where the template requires
4918 them. (eg. movzb) */
4919 if (i
.types
[op
].bitfield
.reg8
4920 && (i
.tm
.operand_types
[op
].bitfield
.reg16
4921 || i
.tm
.operand_types
[op
].bitfield
.reg32
4922 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4924 as_bad (_("`%s%s' not allowed with `%s%c'"),
4926 i
.op
[op
].regs
->reg_name
,
4931 /* Warn if the e prefix on a general reg is missing. */
4932 else if ((i
.types
[op
].bitfield
.reg16
4933 || i
.types
[op
].bitfield
.reg32
)
4934 && (i
.tm
.operand_types
[op
].bitfield
.reg32
4935 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4937 /* Prohibit these changes in the 64bit mode, since the
4938 lowering is more complicated. */
4940 && i
.tm
.opcode_modifier
.todword
4941 && !i
.types
[0].bitfield
.regxmm
)
4943 /* Convert to DWORD. We don't want REX byte. */
4944 i
.suffix
= LONG_MNEM_SUFFIX
;
4948 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
4949 register_prefix
, i
.op
[op
].regs
->reg_name
,
4958 check_word_reg (void)
4961 for (op
= i
.operands
; --op
>= 0;)
4962 /* Reject eight bit registers, except where the template requires
4963 them. (eg. movzb) */
4964 if (i
.types
[op
].bitfield
.reg8
4965 && (i
.tm
.operand_types
[op
].bitfield
.reg16
4966 || i
.tm
.operand_types
[op
].bitfield
.reg32
4967 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4969 as_bad (_("`%s%s' not allowed with `%s%c'"),
4971 i
.op
[op
].regs
->reg_name
,
4976 /* Warn if the e prefix on a general reg is present. */
4977 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
4978 && i
.types
[op
].bitfield
.reg32
4979 && (i
.tm
.operand_types
[op
].bitfield
.reg16
4980 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4982 /* Prohibit these changes in the 64bit mode, since the
4983 lowering is more complicated. */
4984 if (flag_code
== CODE_64BIT
)
4986 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
4987 register_prefix
, i
.op
[op
].regs
->reg_name
,
4992 #if REGISTER_WARNINGS
4993 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4995 (i
.op
[op
].regs
+ REGNAM_AX
- REGNAM_EAX
)->reg_name
,
4997 i
.op
[op
].regs
->reg_name
,
5005 update_imm (unsigned int j
)
5007 i386_operand_type overlap
= i
.types
[j
];
5008 if ((overlap
.bitfield
.imm8
5009 || overlap
.bitfield
.imm8s
5010 || overlap
.bitfield
.imm16
5011 || overlap
.bitfield
.imm32
5012 || overlap
.bitfield
.imm32s
5013 || overlap
.bitfield
.imm64
)
5014 && !operand_type_equal (&overlap
, &imm8
)
5015 && !operand_type_equal (&overlap
, &imm8s
)
5016 && !operand_type_equal (&overlap
, &imm16
)
5017 && !operand_type_equal (&overlap
, &imm32
)
5018 && !operand_type_equal (&overlap
, &imm32s
)
5019 && !operand_type_equal (&overlap
, &imm64
))
5023 i386_operand_type temp
;
5025 operand_type_set (&temp
, 0);
5026 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
5028 temp
.bitfield
.imm8
= overlap
.bitfield
.imm8
;
5029 temp
.bitfield
.imm8s
= overlap
.bitfield
.imm8s
;
5031 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
5032 temp
.bitfield
.imm16
= overlap
.bitfield
.imm16
;
5033 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
5035 temp
.bitfield
.imm64
= overlap
.bitfield
.imm64
;
5036 temp
.bitfield
.imm32s
= overlap
.bitfield
.imm32s
;
5039 temp
.bitfield
.imm32
= overlap
.bitfield
.imm32
;
5042 else if (operand_type_equal (&overlap
, &imm16_32_32s
)
5043 || operand_type_equal (&overlap
, &imm16_32
)
5044 || operand_type_equal (&overlap
, &imm16_32s
))
5046 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
5051 if (!operand_type_equal (&overlap
, &imm8
)
5052 && !operand_type_equal (&overlap
, &imm8s
)
5053 && !operand_type_equal (&overlap
, &imm16
)
5054 && !operand_type_equal (&overlap
, &imm32
)
5055 && !operand_type_equal (&overlap
, &imm32s
)
5056 && !operand_type_equal (&overlap
, &imm64
))
5058 as_bad (_("no instruction mnemonic suffix given; "
5059 "can't determine immediate size"));
5063 i
.types
[j
] = overlap
;
5073 /* Update the first 2 immediate operands. */
5074 n
= i
.operands
> 2 ? 2 : i
.operands
;
5077 for (j
= 0; j
< n
; j
++)
5078 if (update_imm (j
) == 0)
5081 /* The 3rd operand can't be immediate operand. */
5082 gas_assert (operand_type_check (i
.types
[2], imm
) == 0);
5089 bad_implicit_operand (int xmm
)
5091 const char *ireg
= xmm
? "xmm0" : "ymm0";
5094 as_bad (_("the last operand of `%s' must be `%s%s'"),
5095 i
.tm
.name
, register_prefix
, ireg
);
5097 as_bad (_("the first operand of `%s' must be `%s%s'"),
5098 i
.tm
.name
, register_prefix
, ireg
);
5103 process_operands (void)
5105 /* Default segment register this instruction will use for memory
5106 accesses. 0 means unknown. This is only for optimizing out
5107 unnecessary segment overrides. */
5108 const seg_entry
*default_seg
= 0;
5110 if (i
.tm
.opcode_modifier
.sse2avx
&& i
.tm
.opcode_modifier
.vexvvvv
)
5112 unsigned int dupl
= i
.operands
;
5113 unsigned int dest
= dupl
- 1;
5116 /* The destination must be an xmm register. */
5117 gas_assert (i
.reg_operands
5118 && MAX_OPERANDS
> dupl
5119 && operand_type_equal (&i
.types
[dest
], ®xmm
));
5121 if (i
.tm
.opcode_modifier
.firstxmm0
)
5123 /* The first operand is implicit and must be xmm0. */
5124 gas_assert (operand_type_equal (&i
.types
[0], ®xmm
));
5125 if (register_number (i
.op
[0].regs
) != 0)
5126 return bad_implicit_operand (1);
5128 if (i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
)
5130 /* Keep xmm0 for instructions with VEX prefix and 3
5136 /* We remove the first xmm0 and keep the number of
5137 operands unchanged, which in fact duplicates the
5139 for (j
= 1; j
< i
.operands
; j
++)
5141 i
.op
[j
- 1] = i
.op
[j
];
5142 i
.types
[j
- 1] = i
.types
[j
];
5143 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
5147 else if (i
.tm
.opcode_modifier
.implicit1stxmm0
)
5149 gas_assert ((MAX_OPERANDS
- 1) > dupl
5150 && (i
.tm
.opcode_modifier
.vexsources
5153 /* Add the implicit xmm0 for instructions with VEX prefix
5155 for (j
= i
.operands
; j
> 0; j
--)
5157 i
.op
[j
] = i
.op
[j
- 1];
5158 i
.types
[j
] = i
.types
[j
- 1];
5159 i
.tm
.operand_types
[j
] = i
.tm
.operand_types
[j
- 1];
5162 = (const reg_entry
*) hash_find (reg_hash
, "xmm0");
5163 i
.types
[0] = regxmm
;
5164 i
.tm
.operand_types
[0] = regxmm
;
5167 i
.reg_operands
+= 2;
5172 i
.op
[dupl
] = i
.op
[dest
];
5173 i
.types
[dupl
] = i
.types
[dest
];
5174 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
5183 i
.op
[dupl
] = i
.op
[dest
];
5184 i
.types
[dupl
] = i
.types
[dest
];
5185 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
5188 if (i
.tm
.opcode_modifier
.immext
)
5191 else if (i
.tm
.opcode_modifier
.firstxmm0
)
5195 /* The first operand is implicit and must be xmm0/ymm0. */
5196 gas_assert (i
.reg_operands
5197 && (operand_type_equal (&i
.types
[0], ®xmm
)
5198 || operand_type_equal (&i
.types
[0], ®ymm
)));
5199 if (register_number (i
.op
[0].regs
) != 0)
5200 return bad_implicit_operand (i
.types
[0].bitfield
.regxmm
);
5202 for (j
= 1; j
< i
.operands
; j
++)
5204 i
.op
[j
- 1] = i
.op
[j
];
5205 i
.types
[j
- 1] = i
.types
[j
];
5207 /* We need to adjust fields in i.tm since they are used by
5208 build_modrm_byte. */
5209 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
5216 else if (i
.tm
.opcode_modifier
.regkludge
)
5218 /* The imul $imm, %reg instruction is converted into
5219 imul $imm, %reg, %reg, and the clr %reg instruction
5220 is converted into xor %reg, %reg. */
5222 unsigned int first_reg_op
;
5224 if (operand_type_check (i
.types
[0], reg
))
5228 /* Pretend we saw the extra register operand. */
5229 gas_assert (i
.reg_operands
== 1
5230 && i
.op
[first_reg_op
+ 1].regs
== 0);
5231 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
5232 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
5237 if (i
.tm
.opcode_modifier
.shortform
)
5239 if (i
.types
[0].bitfield
.sreg2
5240 || i
.types
[0].bitfield
.sreg3
)
5242 if (i
.tm
.base_opcode
== POP_SEG_SHORT
5243 && i
.op
[0].regs
->reg_num
== 1)
5245 as_bad (_("you can't `pop %scs'"), register_prefix
);
5248 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
5249 if ((i
.op
[0].regs
->reg_flags
& RegRex
) != 0)
5254 /* The register or float register operand is in operand
5258 if (i
.types
[0].bitfield
.floatreg
5259 || operand_type_check (i
.types
[0], reg
))
5263 /* Register goes in low 3 bits of opcode. */
5264 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
5265 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
5267 if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
5269 /* Warn about some common errors, but press on regardless.
5270 The first case can be generated by gcc (<= 2.8.1). */
5271 if (i
.operands
== 2)
5273 /* Reversed arguments on faddp, fsubp, etc. */
5274 as_warn (_("translating to `%s %s%s,%s%s'"), i
.tm
.name
,
5275 register_prefix
, i
.op
[!intel_syntax
].regs
->reg_name
,
5276 register_prefix
, i
.op
[intel_syntax
].regs
->reg_name
);
5280 /* Extraneous `l' suffix on fp insn. */
5281 as_warn (_("translating to `%s %s%s'"), i
.tm
.name
,
5282 register_prefix
, i
.op
[0].regs
->reg_name
);
5287 else if (i
.tm
.opcode_modifier
.modrm
)
5289 /* The opcode is completed (modulo i.tm.extension_opcode which
5290 must be put into the modrm byte). Now, we make the modrm and
5291 index base bytes based on all the info we've collected. */
5293 default_seg
= build_modrm_byte ();
5295 else if ((i
.tm
.base_opcode
& ~0x3) == MOV_AX_DISP32
)
5299 else if (i
.tm
.opcode_modifier
.isstring
)
5301 /* For the string instructions that allow a segment override
5302 on one of their operands, the default segment is ds. */
5306 if (i
.tm
.base_opcode
== 0x8d /* lea */
5309 as_warn (_("segment override on `%s' is ineffectual"), i
.tm
.name
);
5311 /* If a segment was explicitly specified, and the specified segment
5312 is not the default, use an opcode prefix to select it. If we
5313 never figured out what the default segment is, then default_seg
5314 will be zero at this point, and the specified segment prefix will
5316 if ((i
.seg
[0]) && (i
.seg
[0] != default_seg
))
5318 if (!add_prefix (i
.seg
[0]->seg_prefix
))
5324 static const seg_entry
*
5325 build_modrm_byte (void)
5327 const seg_entry
*default_seg
= 0;
5328 unsigned int source
, dest
;
5331 /* The first operand of instructions with VEX prefix and 3 sources
5332 must be VEX_Imm4. */
5333 vex_3_sources
= i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
;
5336 unsigned int nds
, reg_slot
;
5339 if (i
.tm
.opcode_modifier
.veximmext
5340 && i
.tm
.opcode_modifier
.immext
)
5342 dest
= i
.operands
- 2;
5343 gas_assert (dest
== 3);
5346 dest
= i
.operands
- 1;
5349 /* There are 2 kinds of instructions:
5350 1. 5 operands: 4 register operands or 3 register operands
5351 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
5352 VexW0 or VexW1. The destination must be either XMM or YMM
5354 2. 4 operands: 4 register operands or 3 register operands
5355 plus 1 memory operand, VexXDS, and VexImmExt */
5356 gas_assert ((i
.reg_operands
== 4
5357 || (i
.reg_operands
== 3 && i
.mem_operands
== 1))
5358 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
5359 && (i
.tm
.opcode_modifier
.veximmext
5360 || (i
.imm_operands
== 1
5361 && i
.types
[0].bitfield
.vec_imm4
5362 && (i
.tm
.opcode_modifier
.vexw
== VEXW0
5363 || i
.tm
.opcode_modifier
.vexw
== VEXW1
)
5364 && (operand_type_equal (&i
.tm
.operand_types
[dest
], ®xmm
)
5365 || operand_type_equal (&i
.tm
.operand_types
[dest
], ®ymm
)))));
5367 if (i
.imm_operands
== 0)
5369 /* When there is no immediate operand, generate an 8bit
5370 immediate operand to encode the first operand. */
5371 exp
= &im_expressions
[i
.imm_operands
++];
5372 i
.op
[i
.operands
].imms
= exp
;
5373 i
.types
[i
.operands
] = imm8
;
5375 /* If VexW1 is set, the first operand is the source and
5376 the second operand is encoded in the immediate operand. */
5377 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
5388 /* FMA swaps REG and NDS. */
5389 if (i
.tm
.cpu_flags
.bitfield
.cpufma
)
5397 gas_assert (operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
5399 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
5401 exp
->X_op
= O_constant
;
5402 exp
->X_add_number
= register_number (i
.op
[reg_slot
].regs
) << 4;
5406 unsigned int imm_slot
;
5408 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
5410 /* If VexW0 is set, the third operand is the source and
5411 the second operand is encoded in the immediate
5418 /* VexW1 is set, the second operand is the source and
5419 the third operand is encoded in the immediate
5425 if (i
.tm
.opcode_modifier
.immext
)
5427 /* When ImmExt is set, the immdiate byte is the last
5429 imm_slot
= i
.operands
- 1;
5437 /* Turn on Imm8 so that output_imm will generate it. */
5438 i
.types
[imm_slot
].bitfield
.imm8
= 1;
5441 gas_assert (operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
5443 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
5445 i
.op
[imm_slot
].imms
->X_add_number
5446 |= register_number (i
.op
[reg_slot
].regs
) << 4;
5449 gas_assert (operand_type_equal (&i
.tm
.operand_types
[nds
], ®xmm
)
5450 || operand_type_equal (&i
.tm
.operand_types
[nds
],
5452 i
.vex
.register_specifier
= i
.op
[nds
].regs
;
5457 /* i.reg_operands MUST be the number of real register operands;
5458 implicit registers do not count. If there are 3 register
5459 operands, it must be a instruction with VexNDS. For a
5460 instruction with VexNDD, the destination register is encoded
5461 in VEX prefix. If there are 4 register operands, it must be
5462 a instruction with VEX prefix and 3 sources. */
5463 if (i
.mem_operands
== 0
5464 && ((i
.reg_operands
== 2
5465 && i
.tm
.opcode_modifier
.vexvvvv
<= VEXXDS
)
5466 || (i
.reg_operands
== 3
5467 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
5468 || (i
.reg_operands
== 4 && vex_3_sources
)))
5476 /* When there are 3 operands, one of them may be immediate,
5477 which may be the first or the last operand. Otherwise,
5478 the first operand must be shift count register (cl) or it
5479 is an instruction with VexNDS. */
5480 gas_assert (i
.imm_operands
== 1
5481 || (i
.imm_operands
== 0
5482 && (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
5483 || i
.types
[0].bitfield
.shiftcount
)));
5484 if (operand_type_check (i
.types
[0], imm
)
5485 || i
.types
[0].bitfield
.shiftcount
)
5491 /* When there are 4 operands, the first two must be 8bit
5492 immediate operands. The source operand will be the 3rd
5495 For instructions with VexNDS, if the first operand
5496 an imm8, the source operand is the 2nd one. If the last
5497 operand is imm8, the source operand is the first one. */
5498 gas_assert ((i
.imm_operands
== 2
5499 && i
.types
[0].bitfield
.imm8
5500 && i
.types
[1].bitfield
.imm8
)
5501 || (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
5502 && i
.imm_operands
== 1
5503 && (i
.types
[0].bitfield
.imm8
5504 || i
.types
[i
.operands
- 1].bitfield
.imm8
)));
5505 if (i
.imm_operands
== 2)
5509 if (i
.types
[0].bitfield
.imm8
)
5525 if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
5527 /* For instructions with VexNDS, the register-only
5528 source operand must be 32/64bit integer, XMM or
5529 YMM register. It is encoded in VEX prefix. We
5530 need to clear RegMem bit before calling
5531 operand_type_equal. */
5533 i386_operand_type op
;
5536 /* Check register-only source operand when two source
5537 operands are swapped. */
5538 if (!i
.tm
.operand_types
[source
].bitfield
.baseindex
5539 && i
.tm
.operand_types
[dest
].bitfield
.baseindex
)
5547 op
= i
.tm
.operand_types
[vvvv
];
5548 op
.bitfield
.regmem
= 0;
5549 if ((dest
+ 1) >= i
.operands
5550 || (op
.bitfield
.reg32
!= 1
5551 && !op
.bitfield
.reg64
!= 1
5552 && !operand_type_equal (&op
, ®xmm
)
5553 && !operand_type_equal (&op
, ®ymm
)))
5555 i
.vex
.register_specifier
= i
.op
[vvvv
].regs
;
5561 /* One of the register operands will be encoded in the i.tm.reg
5562 field, the other in the combined i.tm.mode and i.tm.regmem
5563 fields. If no form of this instruction supports a memory
5564 destination operand, then we assume the source operand may
5565 sometimes be a memory operand and so we need to store the
5566 destination in the i.rm.reg field. */
5567 if (!i
.tm
.operand_types
[dest
].bitfield
.regmem
5568 && operand_type_check (i
.tm
.operand_types
[dest
], anymem
) == 0)
5570 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
5571 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
5572 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
5574 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
5579 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
5580 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
5581 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
5583 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
5586 if (flag_code
!= CODE_64BIT
&& (i
.rex
& (REX_R
| REX_B
)))
5588 if (!i
.types
[0].bitfield
.control
5589 && !i
.types
[1].bitfield
.control
)
5591 i
.rex
&= ~(REX_R
| REX_B
);
5592 add_prefix (LOCK_PREFIX_OPCODE
);
5596 { /* If it's not 2 reg operands... */
5601 unsigned int fake_zero_displacement
= 0;
5604 for (op
= 0; op
< i
.operands
; op
++)
5605 if (operand_type_check (i
.types
[op
], anymem
))
5607 gas_assert (op
< i
.operands
);
5609 if (i
.tm
.opcode_modifier
.vecsib
)
5611 if (i
.index_reg
->reg_num
== RegEiz
5612 || i
.index_reg
->reg_num
== RegRiz
)
5615 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
5618 i
.sib
.base
= NO_BASE_REGISTER
;
5619 i
.sib
.scale
= i
.log2_scale_factor
;
5620 i
.types
[op
].bitfield
.disp8
= 0;
5621 i
.types
[op
].bitfield
.disp16
= 0;
5622 i
.types
[op
].bitfield
.disp64
= 0;
5623 if (flag_code
!= CODE_64BIT
)
5625 /* Must be 32 bit */
5626 i
.types
[op
].bitfield
.disp32
= 1;
5627 i
.types
[op
].bitfield
.disp32s
= 0;
5631 i
.types
[op
].bitfield
.disp32
= 0;
5632 i
.types
[op
].bitfield
.disp32s
= 1;
5635 i
.sib
.index
= i
.index_reg
->reg_num
;
5636 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
5642 if (i
.base_reg
== 0)
5645 if (!i
.disp_operands
)
5647 fake_zero_displacement
= 1;
5648 /* Instructions with VSIB byte need 32bit displacement
5649 if there is no base register. */
5650 if (i
.tm
.opcode_modifier
.vecsib
)
5651 i
.types
[op
].bitfield
.disp32
= 1;
5653 if (i
.index_reg
== 0)
5655 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
5656 /* Operand is just <disp> */
5657 if (flag_code
== CODE_64BIT
)
5659 /* 64bit mode overwrites the 32bit absolute
5660 addressing by RIP relative addressing and
5661 absolute addressing is encoded by one of the
5662 redundant SIB forms. */
5663 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
5664 i
.sib
.base
= NO_BASE_REGISTER
;
5665 i
.sib
.index
= NO_INDEX_REGISTER
;
5666 i
.types
[op
] = ((i
.prefix
[ADDR_PREFIX
] == 0)
5667 ? disp32s
: disp32
);
5669 else if ((flag_code
== CODE_16BIT
)
5670 ^ (i
.prefix
[ADDR_PREFIX
] != 0))
5672 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
5673 i
.types
[op
] = disp16
;
5677 i
.rm
.regmem
= NO_BASE_REGISTER
;
5678 i
.types
[op
] = disp32
;
5681 else if (!i
.tm
.opcode_modifier
.vecsib
)
5683 /* !i.base_reg && i.index_reg */
5684 if (i
.index_reg
->reg_num
== RegEiz
5685 || i
.index_reg
->reg_num
== RegRiz
)
5686 i
.sib
.index
= NO_INDEX_REGISTER
;
5688 i
.sib
.index
= i
.index_reg
->reg_num
;
5689 i
.sib
.base
= NO_BASE_REGISTER
;
5690 i
.sib
.scale
= i
.log2_scale_factor
;
5691 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
5692 i
.types
[op
].bitfield
.disp8
= 0;
5693 i
.types
[op
].bitfield
.disp16
= 0;
5694 i
.types
[op
].bitfield
.disp64
= 0;
5695 if (flag_code
!= CODE_64BIT
)
5697 /* Must be 32 bit */
5698 i
.types
[op
].bitfield
.disp32
= 1;
5699 i
.types
[op
].bitfield
.disp32s
= 0;
5703 i
.types
[op
].bitfield
.disp32
= 0;
5704 i
.types
[op
].bitfield
.disp32s
= 1;
5706 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
5710 /* RIP addressing for 64bit mode. */
5711 else if (i
.base_reg
->reg_num
== RegRip
||
5712 i
.base_reg
->reg_num
== RegEip
)
5714 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
5715 i
.rm
.regmem
= NO_BASE_REGISTER
;
5716 i
.types
[op
].bitfield
.disp8
= 0;
5717 i
.types
[op
].bitfield
.disp16
= 0;
5718 i
.types
[op
].bitfield
.disp32
= 0;
5719 i
.types
[op
].bitfield
.disp32s
= 1;
5720 i
.types
[op
].bitfield
.disp64
= 0;
5721 i
.flags
[op
] |= Operand_PCrel
;
5722 if (! i
.disp_operands
)
5723 fake_zero_displacement
= 1;
5725 else if (i
.base_reg
->reg_type
.bitfield
.reg16
)
5727 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
5728 switch (i
.base_reg
->reg_num
)
5731 if (i
.index_reg
== 0)
5733 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
5734 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
5738 if (i
.index_reg
== 0)
5741 if (operand_type_check (i
.types
[op
], disp
) == 0)
5743 /* fake (%bp) into 0(%bp) */
5744 i
.types
[op
].bitfield
.disp8
= 1;
5745 fake_zero_displacement
= 1;
5748 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
5749 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
5751 default: /* (%si) -> 4 or (%di) -> 5 */
5752 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
5754 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
5756 else /* i.base_reg and 32/64 bit mode */
5758 if (flag_code
== CODE_64BIT
5759 && operand_type_check (i
.types
[op
], disp
))
5761 i386_operand_type temp
;
5762 operand_type_set (&temp
, 0);
5763 temp
.bitfield
.disp8
= i
.types
[op
].bitfield
.disp8
;
5765 if (i
.prefix
[ADDR_PREFIX
] == 0)
5766 i
.types
[op
].bitfield
.disp32s
= 1;
5768 i
.types
[op
].bitfield
.disp32
= 1;
5771 if (!i
.tm
.opcode_modifier
.vecsib
)
5772 i
.rm
.regmem
= i
.base_reg
->reg_num
;
5773 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
5775 i
.sib
.base
= i
.base_reg
->reg_num
;
5776 /* x86-64 ignores REX prefix bit here to avoid decoder
5778 if (!(i
.base_reg
->reg_flags
& RegRex
)
5779 && (i
.base_reg
->reg_num
== EBP_REG_NUM
5780 || i
.base_reg
->reg_num
== ESP_REG_NUM
))
5782 if (i
.base_reg
->reg_num
== 5 && i
.disp_operands
== 0)
5784 fake_zero_displacement
= 1;
5785 i
.types
[op
].bitfield
.disp8
= 1;
5787 i
.sib
.scale
= i
.log2_scale_factor
;
5788 if (i
.index_reg
== 0)
5790 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
5791 /* <disp>(%esp) becomes two byte modrm with no index
5792 register. We've already stored the code for esp
5793 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
5794 Any base register besides %esp will not use the
5795 extra modrm byte. */
5796 i
.sib
.index
= NO_INDEX_REGISTER
;
5798 else if (!i
.tm
.opcode_modifier
.vecsib
)
5800 if (i
.index_reg
->reg_num
== RegEiz
5801 || i
.index_reg
->reg_num
== RegRiz
)
5802 i
.sib
.index
= NO_INDEX_REGISTER
;
5804 i
.sib
.index
= i
.index_reg
->reg_num
;
5805 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
5806 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
5811 && (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
5812 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
))
5816 if (!fake_zero_displacement
5820 fake_zero_displacement
= 1;
5821 if (i
.disp_encoding
== disp_encoding_8bit
)
5822 i
.types
[op
].bitfield
.disp8
= 1;
5824 i
.types
[op
].bitfield
.disp32
= 1;
5826 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
5830 if (fake_zero_displacement
)
5832 /* Fakes a zero displacement assuming that i.types[op]
5833 holds the correct displacement size. */
5836 gas_assert (i
.op
[op
].disps
== 0);
5837 exp
= &disp_expressions
[i
.disp_operands
++];
5838 i
.op
[op
].disps
= exp
;
5839 exp
->X_op
= O_constant
;
5840 exp
->X_add_number
= 0;
5841 exp
->X_add_symbol
= (symbolS
*) 0;
5842 exp
->X_op_symbol
= (symbolS
*) 0;
5850 if (i
.tm
.opcode_modifier
.vexsources
== XOP2SOURCES
)
5852 if (operand_type_check (i
.types
[0], imm
))
5853 i
.vex
.register_specifier
= NULL
;
5856 /* VEX.vvvv encodes one of the sources when the first
5857 operand is not an immediate. */
5858 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
5859 i
.vex
.register_specifier
= i
.op
[0].regs
;
5861 i
.vex
.register_specifier
= i
.op
[1].regs
;
5864 /* Destination is a XMM register encoded in the ModRM.reg
5866 i
.rm
.reg
= i
.op
[2].regs
->reg_num
;
5867 if ((i
.op
[2].regs
->reg_flags
& RegRex
) != 0)
5870 /* ModRM.rm and VEX.B encodes the other source. */
5871 if (!i
.mem_operands
)
5875 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
5876 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
5878 i
.rm
.regmem
= i
.op
[0].regs
->reg_num
;
5880 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
5884 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXLWP
)
5886 i
.vex
.register_specifier
= i
.op
[2].regs
;
5887 if (!i
.mem_operands
)
5890 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
5891 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
5895 /* Fill in i.rm.reg or i.rm.regmem field with register operand
5896 (if any) based on i.tm.extension_opcode. Again, we must be
5897 careful to make sure that segment/control/debug/test/MMX
5898 registers are coded into the i.rm.reg field. */
5899 else if (i
.reg_operands
)
5902 unsigned int vex_reg
= ~0;
5904 for (op
= 0; op
< i
.operands
; op
++)
5905 if (i
.types
[op
].bitfield
.reg8
5906 || i
.types
[op
].bitfield
.reg16
5907 || i
.types
[op
].bitfield
.reg32
5908 || i
.types
[op
].bitfield
.reg64
5909 || i
.types
[op
].bitfield
.regmmx
5910 || i
.types
[op
].bitfield
.regxmm
5911 || i
.types
[op
].bitfield
.regymm
5912 || i
.types
[op
].bitfield
.sreg2
5913 || i
.types
[op
].bitfield
.sreg3
5914 || i
.types
[op
].bitfield
.control
5915 || i
.types
[op
].bitfield
.debug
5916 || i
.types
[op
].bitfield
.test
)
5921 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
5923 /* For instructions with VexNDS, the register-only
5924 source operand is encoded in VEX prefix. */
5925 gas_assert (mem
!= (unsigned int) ~0);
5930 gas_assert (op
< i
.operands
);
5934 /* Check register-only source operand when two source
5935 operands are swapped. */
5936 if (!i
.tm
.operand_types
[op
].bitfield
.baseindex
5937 && i
.tm
.operand_types
[op
+ 1].bitfield
.baseindex
)
5941 gas_assert (mem
== (vex_reg
+ 1)
5942 && op
< i
.operands
);
5947 gas_assert (vex_reg
< i
.operands
);
5951 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXNDD
)
5953 /* For instructions with VexNDD, the register destination
5954 is encoded in VEX prefix. */
5955 if (i
.mem_operands
== 0)
5957 /* There is no memory operand. */
5958 gas_assert ((op
+ 2) == i
.operands
);
5963 /* There are only 2 operands. */
5964 gas_assert (op
< 2 && i
.operands
== 2);
5969 gas_assert (op
< i
.operands
);
5971 if (vex_reg
!= (unsigned int) ~0)
5973 i386_operand_type
*type
= &i
.tm
.operand_types
[vex_reg
];
5975 if (type
->bitfield
.reg32
!= 1
5976 && type
->bitfield
.reg64
!= 1
5977 && !operand_type_equal (type
, ®xmm
)
5978 && !operand_type_equal (type
, ®ymm
))
5981 i
.vex
.register_specifier
= i
.op
[vex_reg
].regs
;
5984 /* Don't set OP operand twice. */
5987 /* If there is an extension opcode to put here, the
5988 register number must be put into the regmem field. */
5989 if (i
.tm
.extension_opcode
!= None
)
5991 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
5992 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
5997 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
5998 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
6003 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
6004 must set it to 3 to indicate this is a register operand
6005 in the regmem field. */
6006 if (!i
.mem_operands
)
6010 /* Fill in i.rm.reg field with extension opcode (if any). */
6011 if (i
.tm
.extension_opcode
!= None
)
6012 i
.rm
.reg
= i
.tm
.extension_opcode
;
6018 output_branch (void)
6024 relax_substateT subtype
;
6028 code16
= flag_code
== CODE_16BIT
? CODE16
: 0;
6029 size
= i
.disp_encoding
== disp_encoding_32bit
? BIG
: SMALL
;
6032 if (i
.prefix
[DATA_PREFIX
] != 0)
6038 /* Pentium4 branch hints. */
6039 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
6040 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
6045 if (i
.prefix
[REX_PREFIX
] != 0)
6051 if (i
.prefixes
!= 0 && !intel_syntax
)
6052 as_warn (_("skipping prefixes on this instruction"));
6054 /* It's always a symbol; End frag & setup for relax.
6055 Make sure there is enough room in this frag for the largest
6056 instruction we may generate in md_convert_frag. This is 2
6057 bytes for the opcode and room for the prefix and largest
6059 frag_grow (prefix
+ 2 + 4);
6060 /* Prefix and 1 opcode byte go in fr_fix. */
6061 p
= frag_more (prefix
+ 1);
6062 if (i
.prefix
[DATA_PREFIX
] != 0)
6063 *p
++ = DATA_PREFIX_OPCODE
;
6064 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
6065 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
6066 *p
++ = i
.prefix
[SEG_PREFIX
];
6067 if (i
.prefix
[REX_PREFIX
] != 0)
6068 *p
++ = i
.prefix
[REX_PREFIX
];
6069 *p
= i
.tm
.base_opcode
;
6071 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
6072 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, size
);
6073 else if (cpu_arch_flags
.bitfield
.cpui386
)
6074 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, size
);
6076 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, size
);
6079 sym
= i
.op
[0].disps
->X_add_symbol
;
6080 off
= i
.op
[0].disps
->X_add_number
;
6082 if (i
.op
[0].disps
->X_op
!= O_constant
6083 && i
.op
[0].disps
->X_op
!= O_symbol
)
6085 /* Handle complex expressions. */
6086 sym
= make_expr_symbol (i
.op
[0].disps
);
6090 /* 1 possible extra opcode + 4 byte displacement go in var part.
6091 Pass reloc in fr_var. */
6092 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
6102 if (i
.tm
.opcode_modifier
.jumpbyte
)
6104 /* This is a loop or jecxz type instruction. */
6106 if (i
.prefix
[ADDR_PREFIX
] != 0)
6108 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
6111 /* Pentium4 branch hints. */
6112 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
6113 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
6115 FRAG_APPEND_1_CHAR (i
.prefix
[SEG_PREFIX
]);
6124 if (flag_code
== CODE_16BIT
)
6127 if (i
.prefix
[DATA_PREFIX
] != 0)
6129 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
6139 if (i
.prefix
[REX_PREFIX
] != 0)
6141 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
6145 if (i
.prefixes
!= 0 && !intel_syntax
)
6146 as_warn (_("skipping prefixes on this instruction"));
6148 p
= frag_more (i
.tm
.opcode_length
+ size
);
6149 switch (i
.tm
.opcode_length
)
6152 *p
++ = i
.tm
.base_opcode
>> 8;
6154 *p
++ = i
.tm
.base_opcode
;
6160 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
6161 i
.op
[0].disps
, 1, reloc (size
, 1, 1, i
.reloc
[0]));
6163 /* All jumps handled here are signed, but don't use a signed limit
6164 check for 32 and 16 bit jumps as we want to allow wrap around at
6165 4G and 64k respectively. */
6167 fixP
->fx_signed
= 1;
6171 output_interseg_jump (void)
6179 if (flag_code
== CODE_16BIT
)
6183 if (i
.prefix
[DATA_PREFIX
] != 0)
6189 if (i
.prefix
[REX_PREFIX
] != 0)
6199 if (i
.prefixes
!= 0 && !intel_syntax
)
6200 as_warn (_("skipping prefixes on this instruction"));
6202 /* 1 opcode; 2 segment; offset */
6203 p
= frag_more (prefix
+ 1 + 2 + size
);
6205 if (i
.prefix
[DATA_PREFIX
] != 0)
6206 *p
++ = DATA_PREFIX_OPCODE
;
6208 if (i
.prefix
[REX_PREFIX
] != 0)
6209 *p
++ = i
.prefix
[REX_PREFIX
];
6211 *p
++ = i
.tm
.base_opcode
;
6212 if (i
.op
[1].imms
->X_op
== O_constant
)
6214 offsetT n
= i
.op
[1].imms
->X_add_number
;
6217 && !fits_in_unsigned_word (n
)
6218 && !fits_in_signed_word (n
))
6220 as_bad (_("16-bit jump out of range"));
6223 md_number_to_chars (p
, n
, size
);
6226 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
6227 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
6228 if (i
.op
[0].imms
->X_op
!= O_constant
)
6229 as_bad (_("can't handle non absolute segment in `%s'"),
6231 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
6237 fragS
*insn_start_frag
;
6238 offsetT insn_start_off
;
6240 /* Tie dwarf2 debug info to the address at the start of the insn.
6241 We can't do this after the insn has been output as the current
6242 frag may have been closed off. eg. by frag_var. */
6243 dwarf2_emit_insn (0);
6245 insn_start_frag
= frag_now
;
6246 insn_start_off
= frag_now_fix ();
6249 if (i
.tm
.opcode_modifier
.jump
)
6251 else if (i
.tm
.opcode_modifier
.jumpbyte
6252 || i
.tm
.opcode_modifier
.jumpdword
)
6254 else if (i
.tm
.opcode_modifier
.jumpintersegment
)
6255 output_interseg_jump ();
6258 /* Output normal instructions here. */
6262 unsigned int prefix
;
6264 /* Since the VEX prefix contains the implicit prefix, we don't
6265 need the explicit prefix. */
6266 if (!i
.tm
.opcode_modifier
.vex
)
6268 switch (i
.tm
.opcode_length
)
6271 if (i
.tm
.base_opcode
& 0xff000000)
6273 prefix
= (i
.tm
.base_opcode
>> 24) & 0xff;
6278 if ((i
.tm
.base_opcode
& 0xff0000) != 0)
6280 prefix
= (i
.tm
.base_opcode
>> 16) & 0xff;
6281 if (i
.tm
.cpu_flags
.bitfield
.cpupadlock
)
6284 if (prefix
!= REPE_PREFIX_OPCODE
6285 || (i
.prefix
[REP_PREFIX
]
6286 != REPE_PREFIX_OPCODE
))
6287 add_prefix (prefix
);
6290 add_prefix (prefix
);
6299 /* The prefix bytes. */
6300 for (j
= ARRAY_SIZE (i
.prefix
), q
= i
.prefix
; j
> 0; j
--, q
++)
6302 FRAG_APPEND_1_CHAR (*q
);
6306 for (j
= 0, q
= i
.prefix
; j
< ARRAY_SIZE (i
.prefix
); j
++, q
++)
6311 /* REX byte is encoded in VEX prefix. */
6315 FRAG_APPEND_1_CHAR (*q
);
6318 /* There should be no other prefixes for instructions
6323 /* Now the VEX prefix. */
6324 p
= frag_more (i
.vex
.length
);
6325 for (j
= 0; j
< i
.vex
.length
; j
++)
6326 p
[j
] = i
.vex
.bytes
[j
];
6329 /* Now the opcode; be careful about word order here! */
6330 if (i
.tm
.opcode_length
== 1)
6332 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
6336 switch (i
.tm
.opcode_length
)
6340 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
6350 /* Put out high byte first: can't use md_number_to_chars! */
6351 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
6352 *p
= i
.tm
.base_opcode
& 0xff;
6355 /* Now the modrm byte and sib byte (if present). */
6356 if (i
.tm
.opcode_modifier
.modrm
)
6358 FRAG_APPEND_1_CHAR ((i
.rm
.regmem
<< 0
6361 /* If i.rm.regmem == ESP (4)
6362 && i.rm.mode != (Register mode)
6364 ==> need second modrm byte. */
6365 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
6367 && !(i
.base_reg
&& i
.base_reg
->reg_type
.bitfield
.reg16
))
6368 FRAG_APPEND_1_CHAR ((i
.sib
.base
<< 0
6370 | i
.sib
.scale
<< 6));
6373 if (i
.disp_operands
)
6374 output_disp (insn_start_frag
, insn_start_off
);
6377 output_imm (insn_start_frag
, insn_start_off
);
6383 pi ("" /*line*/, &i
);
6385 #endif /* DEBUG386 */
6388 /* Return the size of the displacement operand N. */
6391 disp_size (unsigned int n
)
6394 if (i
.types
[n
].bitfield
.disp64
)
6396 else if (i
.types
[n
].bitfield
.disp8
)
6398 else if (i
.types
[n
].bitfield
.disp16
)
6403 /* Return the size of the immediate operand N. */
6406 imm_size (unsigned int n
)
6409 if (i
.types
[n
].bitfield
.imm64
)
6411 else if (i
.types
[n
].bitfield
.imm8
|| i
.types
[n
].bitfield
.imm8s
)
6413 else if (i
.types
[n
].bitfield
.imm16
)
6419 output_disp (fragS
*insn_start_frag
, offsetT insn_start_off
)
6424 for (n
= 0; n
< i
.operands
; n
++)
6426 if (operand_type_check (i
.types
[n
], disp
))
6428 if (i
.op
[n
].disps
->X_op
== O_constant
)
6430 int size
= disp_size (n
);
6433 val
= offset_in_range (i
.op
[n
].disps
->X_add_number
,
6435 p
= frag_more (size
);
6436 md_number_to_chars (p
, val
, size
);
6440 enum bfd_reloc_code_real reloc_type
;
6441 int size
= disp_size (n
);
6442 int sign
= i
.types
[n
].bitfield
.disp32s
;
6443 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
6445 /* We can't have 8 bit displacement here. */
6446 gas_assert (!i
.types
[n
].bitfield
.disp8
);
6448 /* The PC relative address is computed relative
6449 to the instruction boundary, so in case immediate
6450 fields follows, we need to adjust the value. */
6451 if (pcrel
&& i
.imm_operands
)
6456 for (n1
= 0; n1
< i
.operands
; n1
++)
6457 if (operand_type_check (i
.types
[n1
], imm
))
6459 /* Only one immediate is allowed for PC
6460 relative address. */
6461 gas_assert (sz
== 0);
6463 i
.op
[n
].disps
->X_add_number
-= sz
;
6465 /* We should find the immediate. */
6466 gas_assert (sz
!= 0);
6469 p
= frag_more (size
);
6470 reloc_type
= reloc (size
, pcrel
, sign
, i
.reloc
[n
]);
6472 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
6473 && (((reloc_type
== BFD_RELOC_32
6474 || reloc_type
== BFD_RELOC_X86_64_32S
6475 || (reloc_type
== BFD_RELOC_64
6477 && (i
.op
[n
].disps
->X_op
== O_symbol
6478 || (i
.op
[n
].disps
->X_op
== O_add
6479 && ((symbol_get_value_expression
6480 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
6482 || reloc_type
== BFD_RELOC_32_PCREL
))
6486 if (insn_start_frag
== frag_now
)
6487 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
6492 add
= insn_start_frag
->fr_fix
- insn_start_off
;
6493 for (fr
= insn_start_frag
->fr_next
;
6494 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
6496 add
+= p
- frag_now
->fr_literal
;
6501 reloc_type
= BFD_RELOC_386_GOTPC
;
6502 i
.op
[n
].imms
->X_add_number
+= add
;
6504 else if (reloc_type
== BFD_RELOC_64
)
6505 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
6507 /* Don't do the adjustment for x86-64, as there
6508 the pcrel addressing is relative to the _next_
6509 insn, and that is taken care of in other code. */
6510 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
6512 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
6513 i
.op
[n
].disps
, pcrel
, reloc_type
);
6520 output_imm (fragS
*insn_start_frag
, offsetT insn_start_off
)
6525 for (n
= 0; n
< i
.operands
; n
++)
6527 if (operand_type_check (i
.types
[n
], imm
))
6529 if (i
.op
[n
].imms
->X_op
== O_constant
)
6531 int size
= imm_size (n
);
6534 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
6536 p
= frag_more (size
);
6537 md_number_to_chars (p
, val
, size
);
6541 /* Not absolute_section.
6542 Need a 32-bit fixup (don't support 8bit
6543 non-absolute imms). Try to support other
6545 enum bfd_reloc_code_real reloc_type
;
6546 int size
= imm_size (n
);
6549 if (i
.types
[n
].bitfield
.imm32s
6550 && (i
.suffix
== QWORD_MNEM_SUFFIX
6551 || (!i
.suffix
&& i
.tm
.opcode_modifier
.no_lsuf
)))
6556 p
= frag_more (size
);
6557 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
6559 /* This is tough to explain. We end up with this one if we
6560 * have operands that look like
6561 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
6562 * obtain the absolute address of the GOT, and it is strongly
6563 * preferable from a performance point of view to avoid using
6564 * a runtime relocation for this. The actual sequence of
6565 * instructions often look something like:
6570 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
6572 * The call and pop essentially return the absolute address
6573 * of the label .L66 and store it in %ebx. The linker itself
6574 * will ultimately change the first operand of the addl so
6575 * that %ebx points to the GOT, but to keep things simple, the
6576 * .o file must have this operand set so that it generates not
6577 * the absolute address of .L66, but the absolute address of
6578 * itself. This allows the linker itself simply treat a GOTPC
6579 * relocation as asking for a pcrel offset to the GOT to be
6580 * added in, and the addend of the relocation is stored in the
6581 * operand field for the instruction itself.
6583 * Our job here is to fix the operand so that it would add
6584 * the correct offset so that %ebx would point to itself. The
6585 * thing that is tricky is that .-.L66 will point to the
6586 * beginning of the instruction, so we need to further modify
6587 * the operand so that it will point to itself. There are
6588 * other cases where you have something like:
6590 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
6592 * and here no correction would be required. Internally in
6593 * the assembler we treat operands of this form as not being
6594 * pcrel since the '.' is explicitly mentioned, and I wonder
6595 * whether it would simplify matters to do it this way. Who
6596 * knows. In earlier versions of the PIC patches, the
6597 * pcrel_adjust field was used to store the correction, but
6598 * since the expression is not pcrel, I felt it would be
6599 * confusing to do it this way. */
6601 if ((reloc_type
== BFD_RELOC_32
6602 || reloc_type
== BFD_RELOC_X86_64_32S
6603 || reloc_type
== BFD_RELOC_64
)
6605 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
6606 && (i
.op
[n
].imms
->X_op
== O_symbol
6607 || (i
.op
[n
].imms
->X_op
== O_add
6608 && ((symbol_get_value_expression
6609 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
6614 if (insn_start_frag
== frag_now
)
6615 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
6620 add
= insn_start_frag
->fr_fix
- insn_start_off
;
6621 for (fr
= insn_start_frag
->fr_next
;
6622 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
6624 add
+= p
- frag_now
->fr_literal
;
6628 reloc_type
= BFD_RELOC_386_GOTPC
;
6630 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
6632 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
6633 i
.op
[n
].imms
->X_add_number
+= add
;
6635 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
6636 i
.op
[n
].imms
, 0, reloc_type
);
6642 /* x86_cons_fix_new is called via the expression parsing code when a
6643 reloc is needed. We use this hook to get the correct .got reloc. */
6644 static enum bfd_reloc_code_real got_reloc
= NO_RELOC
;
6645 static int cons_sign
= -1;
6648 x86_cons_fix_new (fragS
*frag
, unsigned int off
, unsigned int len
,
6651 enum bfd_reloc_code_real r
= reloc (len
, 0, cons_sign
, got_reloc
);
6653 got_reloc
= NO_RELOC
;
6656 if (exp
->X_op
== O_secrel
)
6658 exp
->X_op
= O_symbol
;
6659 r
= BFD_RELOC_32_SECREL
;
6663 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
6666 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
6667 purpose of the `.dc.a' internal pseudo-op. */
6670 x86_address_bytes (void)
6672 if ((stdoutput
->arch_info
->mach
& bfd_mach_x64_32
))
6674 return stdoutput
->arch_info
->bits_per_address
/ 8;
6677 #if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
6679 # define lex_got(reloc, adjust, types) NULL
6681 /* Parse operands of the form
6682 <symbol>@GOTOFF+<nnn>
6683 and similar .plt or .got references.
6685 If we find one, set up the correct relocation in RELOC and copy the
6686 input string, minus the `@GOTOFF' into a malloc'd buffer for
6687 parsing by the calling routine. Return this buffer, and if ADJUST
6688 is non-null set it to the length of the string we removed from the
6689 input line. Otherwise return NULL. */
6691 lex_got (enum bfd_reloc_code_real
*rel
,
6693 i386_operand_type
*types
)
6695 /* Some of the relocations depend on the size of what field is to
6696 be relocated. But in our callers i386_immediate and i386_displacement
6697 we don't yet know the operand size (this will be set by insn
6698 matching). Hence we record the word32 relocation here,
6699 and adjust the reloc according to the real size in reloc(). */
6700 static const struct {
6703 const enum bfd_reloc_code_real rel
[2];
6704 const i386_operand_type types64
;
6706 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
6707 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32
,
6709 OPERAND_TYPE_IMM32_64
},
6711 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real
,
6712 BFD_RELOC_X86_64_PLTOFF64
},
6713 OPERAND_TYPE_IMM64
},
6714 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32
,
6715 BFD_RELOC_X86_64_PLT32
},
6716 OPERAND_TYPE_IMM32_32S_DISP32
},
6717 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real
,
6718 BFD_RELOC_X86_64_GOTPLT64
},
6719 OPERAND_TYPE_IMM64_DISP64
},
6720 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF
,
6721 BFD_RELOC_X86_64_GOTOFF64
},
6722 OPERAND_TYPE_IMM64_DISP64
},
6723 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real
,
6724 BFD_RELOC_X86_64_GOTPCREL
},
6725 OPERAND_TYPE_IMM32_32S_DISP32
},
6726 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD
,
6727 BFD_RELOC_X86_64_TLSGD
},
6728 OPERAND_TYPE_IMM32_32S_DISP32
},
6729 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM
,
6730 _dummy_first_bfd_reloc_code_real
},
6731 OPERAND_TYPE_NONE
},
6732 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real
,
6733 BFD_RELOC_X86_64_TLSLD
},
6734 OPERAND_TYPE_IMM32_32S_DISP32
},
6735 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32
,
6736 BFD_RELOC_X86_64_GOTTPOFF
},
6737 OPERAND_TYPE_IMM32_32S_DISP32
},
6738 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32
,
6739 BFD_RELOC_X86_64_TPOFF32
},
6740 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
6741 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE
,
6742 _dummy_first_bfd_reloc_code_real
},
6743 OPERAND_TYPE_NONE
},
6744 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32
,
6745 BFD_RELOC_X86_64_DTPOFF32
},
6746 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
6747 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE
,
6748 _dummy_first_bfd_reloc_code_real
},
6749 OPERAND_TYPE_NONE
},
6750 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE
,
6751 _dummy_first_bfd_reloc_code_real
},
6752 OPERAND_TYPE_NONE
},
6753 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32
,
6754 BFD_RELOC_X86_64_GOT32
},
6755 OPERAND_TYPE_IMM32_32S_64_DISP32
},
6756 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC
,
6757 BFD_RELOC_X86_64_GOTPC32_TLSDESC
},
6758 OPERAND_TYPE_IMM32_32S_DISP32
},
6759 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL
,
6760 BFD_RELOC_X86_64_TLSDESC_CALL
},
6761 OPERAND_TYPE_IMM32_32S_DISP32
},
6766 #if defined (OBJ_MAYBE_ELF)
6771 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
6772 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
6775 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
6777 int len
= gotrel
[j
].len
;
6778 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
6780 if (gotrel
[j
].rel
[object_64bit
] != 0)
6783 char *tmpbuf
, *past_reloc
;
6785 *rel
= gotrel
[j
].rel
[object_64bit
];
6789 if (flag_code
!= CODE_64BIT
)
6791 types
->bitfield
.imm32
= 1;
6792 types
->bitfield
.disp32
= 1;
6795 *types
= gotrel
[j
].types64
;
6798 if (j
!= 0 && GOT_symbol
== NULL
)
6799 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
6801 /* The length of the first part of our input line. */
6802 first
= cp
- input_line_pointer
;
6804 /* The second part goes from after the reloc token until
6805 (and including) an end_of_line char or comma. */
6806 past_reloc
= cp
+ 1 + len
;
6808 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
6810 second
= cp
+ 1 - past_reloc
;
6812 /* Allocate and copy string. The trailing NUL shouldn't
6813 be necessary, but be safe. */
6814 tmpbuf
= (char *) xmalloc (first
+ second
+ 2);
6815 memcpy (tmpbuf
, input_line_pointer
, first
);
6816 if (second
!= 0 && *past_reloc
!= ' ')
6817 /* Replace the relocation token with ' ', so that
6818 errors like foo@GOTOFF1 will be detected. */
6819 tmpbuf
[first
++] = ' ';
6821 /* Increment length by 1 if the relocation token is
6826 memcpy (tmpbuf
+ first
, past_reloc
, second
);
6827 tmpbuf
[first
+ second
] = '\0';
6831 as_bad (_("@%s reloc is not supported with %d-bit output format"),
6832 gotrel
[j
].str
, 1 << (5 + object_64bit
));
6837 /* Might be a symbol version string. Don't as_bad here. */
6846 /* Parse operands of the form
6847 <symbol>@SECREL32+<nnn>
6849 If we find one, set up the correct relocation in RELOC and copy the
6850 input string, minus the `@SECREL32' into a malloc'd buffer for
6851 parsing by the calling routine. Return this buffer, and if ADJUST
6852 is non-null set it to the length of the string we removed from the
6853 input line. Otherwise return NULL.
6855 This function is copied from the ELF version above adjusted for PE targets. */
6858 lex_got (enum bfd_reloc_code_real
*rel ATTRIBUTE_UNUSED
,
6859 int *adjust ATTRIBUTE_UNUSED
,
6860 i386_operand_type
*types ATTRIBUTE_UNUSED
)
6866 const enum bfd_reloc_code_real rel
[2];
6867 const i386_operand_type types64
;
6871 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL
,
6872 BFD_RELOC_32_SECREL
},
6873 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
6879 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
6880 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
6883 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
6885 int len
= gotrel
[j
].len
;
6887 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
6889 if (gotrel
[j
].rel
[object_64bit
] != 0)
6892 char *tmpbuf
, *past_reloc
;
6894 *rel
= gotrel
[j
].rel
[object_64bit
];
6900 if (flag_code
!= CODE_64BIT
)
6902 types
->bitfield
.imm32
= 1;
6903 types
->bitfield
.disp32
= 1;
6906 *types
= gotrel
[j
].types64
;
6909 /* The length of the first part of our input line. */
6910 first
= cp
- input_line_pointer
;
6912 /* The second part goes from after the reloc token until
6913 (and including) an end_of_line char or comma. */
6914 past_reloc
= cp
+ 1 + len
;
6916 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
6918 second
= cp
+ 1 - past_reloc
;
6920 /* Allocate and copy string. The trailing NUL shouldn't
6921 be necessary, but be safe. */
6922 tmpbuf
= (char *) xmalloc (first
+ second
+ 2);
6923 memcpy (tmpbuf
, input_line_pointer
, first
);
6924 if (second
!= 0 && *past_reloc
!= ' ')
6925 /* Replace the relocation token with ' ', so that
6926 errors like foo@SECLREL321 will be detected. */
6927 tmpbuf
[first
++] = ' ';
6928 memcpy (tmpbuf
+ first
, past_reloc
, second
);
6929 tmpbuf
[first
+ second
] = '\0';
6933 as_bad (_("@%s reloc is not supported with %d-bit output format"),
6934 gotrel
[j
].str
, 1 << (5 + object_64bit
));
6939 /* Might be a symbol version string. Don't as_bad here. */
6946 x86_cons (expressionS
*exp
, int size
)
6948 intel_syntax
= -intel_syntax
;
6951 if (size
== 4 || (object_64bit
&& size
== 8))
6953 /* Handle @GOTOFF and the like in an expression. */
6955 char *gotfree_input_line
;
6958 save
= input_line_pointer
;
6959 gotfree_input_line
= lex_got (&got_reloc
, &adjust
, NULL
);
6960 if (gotfree_input_line
)
6961 input_line_pointer
= gotfree_input_line
;
6965 if (gotfree_input_line
)
6967 /* expression () has merrily parsed up to the end of line,
6968 or a comma - in the wrong buffer. Transfer how far
6969 input_line_pointer has moved to the right buffer. */
6970 input_line_pointer
= (save
6971 + (input_line_pointer
- gotfree_input_line
)
6973 free (gotfree_input_line
);
6974 if (exp
->X_op
== O_constant
6975 || exp
->X_op
== O_absent
6976 || exp
->X_op
== O_illegal
6977 || exp
->X_op
== O_register
6978 || exp
->X_op
== O_big
)
6980 char c
= *input_line_pointer
;
6981 *input_line_pointer
= 0;
6982 as_bad (_("missing or invalid expression `%s'"), save
);
6983 *input_line_pointer
= c
;
6990 intel_syntax
= -intel_syntax
;
6993 i386_intel_simplify (exp
);
6997 signed_cons (int size
)
6999 if (flag_code
== CODE_64BIT
)
7007 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
7014 if (exp
.X_op
== O_symbol
)
7015 exp
.X_op
= O_secrel
;
7017 emit_expr (&exp
, 4);
7019 while (*input_line_pointer
++ == ',');
7021 input_line_pointer
--;
7022 demand_empty_rest_of_line ();
7027 i386_immediate (char *imm_start
)
7029 char *save_input_line_pointer
;
7030 char *gotfree_input_line
;
7033 i386_operand_type types
;
7035 operand_type_set (&types
, ~0);
7037 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
7039 as_bad (_("at most %d immediate operands are allowed"),
7040 MAX_IMMEDIATE_OPERANDS
);
7044 exp
= &im_expressions
[i
.imm_operands
++];
7045 i
.op
[this_operand
].imms
= exp
;
7047 if (is_space_char (*imm_start
))
7050 save_input_line_pointer
= input_line_pointer
;
7051 input_line_pointer
= imm_start
;
7053 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
7054 if (gotfree_input_line
)
7055 input_line_pointer
= gotfree_input_line
;
7057 exp_seg
= expression (exp
);
7060 if (*input_line_pointer
)
7061 as_bad (_("junk `%s' after expression"), input_line_pointer
);
7063 input_line_pointer
= save_input_line_pointer
;
7064 if (gotfree_input_line
)
7066 free (gotfree_input_line
);
7068 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
7069 exp
->X_op
= O_illegal
;
7072 return i386_finalize_immediate (exp_seg
, exp
, types
, imm_start
);
7076 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
7077 i386_operand_type types
, const char *imm_start
)
7079 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_illegal
|| exp
->X_op
== O_big
)
7082 as_bad (_("missing or invalid immediate expression `%s'"),
7086 else if (exp
->X_op
== O_constant
)
7088 /* Size it properly later. */
7089 i
.types
[this_operand
].bitfield
.imm64
= 1;
7090 /* If not 64bit, sign extend val. */
7091 if (flag_code
!= CODE_64BIT
7092 && (exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
7094 = (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
7096 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
7097 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
7098 && exp_seg
!= absolute_section
7099 && exp_seg
!= text_section
7100 && exp_seg
!= data_section
7101 && exp_seg
!= bss_section
7102 && exp_seg
!= undefined_section
7103 && !bfd_is_com_section (exp_seg
))
7105 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
7109 else if (!intel_syntax
&& exp
->X_op
== O_register
)
7112 as_bad (_("illegal immediate register operand %s"), imm_start
);
7117 /* This is an address. The size of the address will be
7118 determined later, depending on destination register,
7119 suffix, or the default for the section. */
7120 i
.types
[this_operand
].bitfield
.imm8
= 1;
7121 i
.types
[this_operand
].bitfield
.imm16
= 1;
7122 i
.types
[this_operand
].bitfield
.imm32
= 1;
7123 i
.types
[this_operand
].bitfield
.imm32s
= 1;
7124 i
.types
[this_operand
].bitfield
.imm64
= 1;
7125 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
7133 i386_scale (char *scale
)
7136 char *save
= input_line_pointer
;
7138 input_line_pointer
= scale
;
7139 val
= get_absolute_expression ();
7144 i
.log2_scale_factor
= 0;
7147 i
.log2_scale_factor
= 1;
7150 i
.log2_scale_factor
= 2;
7153 i
.log2_scale_factor
= 3;
7157 char sep
= *input_line_pointer
;
7159 *input_line_pointer
= '\0';
7160 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
7162 *input_line_pointer
= sep
;
7163 input_line_pointer
= save
;
7167 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
7169 as_warn (_("scale factor of %d without an index register"),
7170 1 << i
.log2_scale_factor
);
7171 i
.log2_scale_factor
= 0;
7173 scale
= input_line_pointer
;
7174 input_line_pointer
= save
;
7179 i386_displacement (char *disp_start
, char *disp_end
)
7183 char *save_input_line_pointer
;
7184 char *gotfree_input_line
;
7186 i386_operand_type bigdisp
, types
= anydisp
;
7189 if (i
.disp_operands
== MAX_MEMORY_OPERANDS
)
7191 as_bad (_("at most %d displacement operands are allowed"),
7192 MAX_MEMORY_OPERANDS
);
7196 operand_type_set (&bigdisp
, 0);
7197 if ((i
.types
[this_operand
].bitfield
.jumpabsolute
)
7198 || (!current_templates
->start
->opcode_modifier
.jump
7199 && !current_templates
->start
->opcode_modifier
.jumpdword
))
7201 bigdisp
.bitfield
.disp32
= 1;
7202 override
= (i
.prefix
[ADDR_PREFIX
] != 0);
7203 if (flag_code
== CODE_64BIT
)
7207 bigdisp
.bitfield
.disp32s
= 1;
7208 bigdisp
.bitfield
.disp64
= 1;
7211 else if ((flag_code
== CODE_16BIT
) ^ override
)
7213 bigdisp
.bitfield
.disp32
= 0;
7214 bigdisp
.bitfield
.disp16
= 1;
7219 /* For PC-relative branches, the width of the displacement
7220 is dependent upon data size, not address size. */
7221 override
= (i
.prefix
[DATA_PREFIX
] != 0);
7222 if (flag_code
== CODE_64BIT
)
7224 if (override
|| i
.suffix
== WORD_MNEM_SUFFIX
)
7225 bigdisp
.bitfield
.disp16
= 1;
7228 bigdisp
.bitfield
.disp32
= 1;
7229 bigdisp
.bitfield
.disp32s
= 1;
7235 override
= (i
.suffix
== (flag_code
!= CODE_16BIT
7237 : LONG_MNEM_SUFFIX
));
7238 bigdisp
.bitfield
.disp32
= 1;
7239 if ((flag_code
== CODE_16BIT
) ^ override
)
7241 bigdisp
.bitfield
.disp32
= 0;
7242 bigdisp
.bitfield
.disp16
= 1;
7246 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
7249 exp
= &disp_expressions
[i
.disp_operands
];
7250 i
.op
[this_operand
].disps
= exp
;
7252 save_input_line_pointer
= input_line_pointer
;
7253 input_line_pointer
= disp_start
;
7254 END_STRING_AND_SAVE (disp_end
);
7256 #ifndef GCC_ASM_O_HACK
7257 #define GCC_ASM_O_HACK 0
7260 END_STRING_AND_SAVE (disp_end
+ 1);
7261 if (i
.types
[this_operand
].bitfield
.baseIndex
7262 && displacement_string_end
[-1] == '+')
7264 /* This hack is to avoid a warning when using the "o"
7265 constraint within gcc asm statements.
7268 #define _set_tssldt_desc(n,addr,limit,type) \
7269 __asm__ __volatile__ ( \
7271 "movw %w1,2+%0\n\t" \
7273 "movb %b1,4+%0\n\t" \
7274 "movb %4,5+%0\n\t" \
7275 "movb $0,6+%0\n\t" \
7276 "movb %h1,7+%0\n\t" \
7278 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
7280 This works great except that the output assembler ends
7281 up looking a bit weird if it turns out that there is
7282 no offset. You end up producing code that looks like:
7295 So here we provide the missing zero. */
7297 *displacement_string_end
= '0';
7300 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
7301 if (gotfree_input_line
)
7302 input_line_pointer
= gotfree_input_line
;
7304 exp_seg
= expression (exp
);
7307 if (*input_line_pointer
)
7308 as_bad (_("junk `%s' after expression"), input_line_pointer
);
7310 RESTORE_END_STRING (disp_end
+ 1);
7312 input_line_pointer
= save_input_line_pointer
;
7313 if (gotfree_input_line
)
7315 free (gotfree_input_line
);
7317 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
7318 exp
->X_op
= O_illegal
;
7321 ret
= i386_finalize_displacement (exp_seg
, exp
, types
, disp_start
);
7323 RESTORE_END_STRING (disp_end
);
7329 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
7330 i386_operand_type types
, const char *disp_start
)
7332 i386_operand_type bigdisp
;
7335 /* We do this to make sure that the section symbol is in
7336 the symbol table. We will ultimately change the relocation
7337 to be relative to the beginning of the section. */
7338 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
7339 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
7340 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
7342 if (exp
->X_op
!= O_symbol
)
7345 if (S_IS_LOCAL (exp
->X_add_symbol
)
7346 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
7347 && S_GET_SEGMENT (exp
->X_add_symbol
) != expr_section
)
7348 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
7349 exp
->X_op
= O_subtract
;
7350 exp
->X_op_symbol
= GOT_symbol
;
7351 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
7352 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
7353 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
7354 i
.reloc
[this_operand
] = BFD_RELOC_64
;
7356 i
.reloc
[this_operand
] = BFD_RELOC_32
;
7359 else if (exp
->X_op
== O_absent
7360 || exp
->X_op
== O_illegal
7361 || exp
->X_op
== O_big
)
7364 as_bad (_("missing or invalid displacement expression `%s'"),
7369 else if (flag_code
== CODE_64BIT
7370 && !i
.prefix
[ADDR_PREFIX
]
7371 && exp
->X_op
== O_constant
)
7373 /* Since displacement is signed extended to 64bit, don't allow
7374 disp32 and turn off disp32s if they are out of range. */
7375 i
.types
[this_operand
].bitfield
.disp32
= 0;
7376 if (!fits_in_signed_long (exp
->X_add_number
))
7378 i
.types
[this_operand
].bitfield
.disp32s
= 0;
7379 if (i
.types
[this_operand
].bitfield
.baseindex
)
7381 as_bad (_("0x%lx out range of signed 32bit displacement"),
7382 (long) exp
->X_add_number
);
7388 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
7389 else if (exp
->X_op
!= O_constant
7390 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
7391 && exp_seg
!= absolute_section
7392 && exp_seg
!= text_section
7393 && exp_seg
!= data_section
7394 && exp_seg
!= bss_section
7395 && exp_seg
!= undefined_section
7396 && !bfd_is_com_section (exp_seg
))
7398 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
7403 /* Check if this is a displacement only operand. */
7404 bigdisp
= i
.types
[this_operand
];
7405 bigdisp
.bitfield
.disp8
= 0;
7406 bigdisp
.bitfield
.disp16
= 0;
7407 bigdisp
.bitfield
.disp32
= 0;
7408 bigdisp
.bitfield
.disp32s
= 0;
7409 bigdisp
.bitfield
.disp64
= 0;
7410 if (operand_type_all_zero (&bigdisp
))
7411 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
7417 /* Make sure the memory operand we've been dealt is valid.
7418 Return 1 on success, 0 on a failure. */
7421 i386_index_check (const char *operand_string
)
7424 const char *kind
= "base/index";
7425 #if INFER_ADDR_PREFIX
7431 if (current_templates
->start
->opcode_modifier
.isstring
7432 && !current_templates
->start
->opcode_modifier
.immext
7433 && (current_templates
->end
[-1].opcode_modifier
.isstring
7436 /* Memory operands of string insns are special in that they only allow
7437 a single register (rDI, rSI, or rBX) as their memory address. */
7438 unsigned int expected
;
7440 kind
= "string address";
7442 if (current_templates
->start
->opcode_modifier
.w
)
7444 i386_operand_type type
= current_templates
->end
[-1].operand_types
[0];
7446 if (!type
.bitfield
.baseindex
7447 || ((!i
.mem_operands
!= !intel_syntax
)
7448 && current_templates
->end
[-1].operand_types
[1]
7449 .bitfield
.baseindex
))
7450 type
= current_templates
->end
[-1].operand_types
[1];
7451 expected
= type
.bitfield
.esseg
? 7 /* rDI */ : 6 /* rSI */;
7454 expected
= 3 /* rBX */;
7456 if (!i
.base_reg
|| i
.index_reg
7457 || operand_type_check (i
.types
[this_operand
], disp
))
7459 else if (!(flag_code
== CODE_64BIT
7460 ? i
.prefix
[ADDR_PREFIX
]
7461 ? i
.base_reg
->reg_type
.bitfield
.reg32
7462 : i
.base_reg
->reg_type
.bitfield
.reg64
7463 : (flag_code
== CODE_16BIT
) ^ !i
.prefix
[ADDR_PREFIX
]
7464 ? i
.base_reg
->reg_type
.bitfield
.reg32
7465 : i
.base_reg
->reg_type
.bitfield
.reg16
))
7467 else if (register_number (i
.base_reg
) != expected
)
7474 for (j
= 0; j
< i386_regtab_size
; ++j
)
7475 if ((flag_code
== CODE_64BIT
7476 ? i
.prefix
[ADDR_PREFIX
]
7477 ? i386_regtab
[j
].reg_type
.bitfield
.reg32
7478 : i386_regtab
[j
].reg_type
.bitfield
.reg64
7479 : (flag_code
== CODE_16BIT
) ^ !i
.prefix
[ADDR_PREFIX
]
7480 ? i386_regtab
[j
].reg_type
.bitfield
.reg32
7481 : i386_regtab
[j
].reg_type
.bitfield
.reg16
)
7482 && register_number(i386_regtab
+ j
) == expected
)
7484 gas_assert (j
< i386_regtab_size
);
7485 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
7487 intel_syntax
? '[' : '(',
7489 i386_regtab
[j
].reg_name
,
7490 intel_syntax
? ']' : ')');
7494 else if (flag_code
== CODE_64BIT
)
7497 && ((i
.prefix
[ADDR_PREFIX
] == 0
7498 && !i
.base_reg
->reg_type
.bitfield
.reg64
)
7499 || (i
.prefix
[ADDR_PREFIX
]
7500 && !i
.base_reg
->reg_type
.bitfield
.reg32
))
7502 || i
.base_reg
->reg_num
!=
7503 (i
.prefix
[ADDR_PREFIX
] == 0 ? RegRip
: RegEip
)))
7505 && !(i
.index_reg
->reg_type
.bitfield
.regxmm
7506 || i
.index_reg
->reg_type
.bitfield
.regymm
)
7507 && (!i
.index_reg
->reg_type
.bitfield
.baseindex
7508 || (i
.prefix
[ADDR_PREFIX
] == 0
7509 && i
.index_reg
->reg_num
!= RegRiz
7510 && !i
.index_reg
->reg_type
.bitfield
.reg64
7512 || (i
.prefix
[ADDR_PREFIX
]
7513 && i
.index_reg
->reg_num
!= RegEiz
7514 && !i
.index_reg
->reg_type
.bitfield
.reg32
))))
7519 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[ADDR_PREFIX
] != 0))
7523 && (!i
.base_reg
->reg_type
.bitfield
.reg16
7524 || !i
.base_reg
->reg_type
.bitfield
.baseindex
))
7526 && (!i
.index_reg
->reg_type
.bitfield
.reg16
7527 || !i
.index_reg
->reg_type
.bitfield
.baseindex
7529 && i
.base_reg
->reg_num
< 6
7530 && i
.index_reg
->reg_num
>= 6
7531 && i
.log2_scale_factor
== 0))))
7538 && !i
.base_reg
->reg_type
.bitfield
.reg32
)
7540 && !i
.index_reg
->reg_type
.bitfield
.regxmm
7541 && !i
.index_reg
->reg_type
.bitfield
.regymm
7542 && ((!i
.index_reg
->reg_type
.bitfield
.reg32
7543 && i
.index_reg
->reg_num
!= RegEiz
)
7544 || !i
.index_reg
->reg_type
.bitfield
.baseindex
)))
7550 #if INFER_ADDR_PREFIX
7551 if (!i
.mem_operands
&& !i
.prefix
[ADDR_PREFIX
])
7553 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
7555 /* Change the size of any displacement too. At most one of
7556 Disp16 or Disp32 is set.
7557 FIXME. There doesn't seem to be any real need for separate
7558 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
7559 Removing them would probably clean up the code quite a lot. */
7560 if (flag_code
!= CODE_64BIT
7561 && (i
.types
[this_operand
].bitfield
.disp16
7562 || i
.types
[this_operand
].bitfield
.disp32
))
7563 i
.types
[this_operand
]
7564 = operand_type_xor (i
.types
[this_operand
], disp16_32
);
7569 as_bad (_("`%s' is not a valid %s expression"),
7574 as_bad (_("`%s' is not a valid %s-bit %s expression"),
7576 flag_code_names
[i
.prefix
[ADDR_PREFIX
]
7577 ? flag_code
== CODE_32BIT
7586 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
7590 i386_att_operand (char *operand_string
)
7594 char *op_string
= operand_string
;
7596 if (is_space_char (*op_string
))
7599 /* We check for an absolute prefix (differentiating,
7600 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
7601 if (*op_string
== ABSOLUTE_PREFIX
)
7604 if (is_space_char (*op_string
))
7606 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
7609 /* Check if operand is a register. */
7610 if ((r
= parse_register (op_string
, &end_op
)) != NULL
)
7612 i386_operand_type temp
;
7614 /* Check for a segment override by searching for ':' after a
7615 segment register. */
7617 if (is_space_char (*op_string
))
7619 if (*op_string
== ':'
7620 && (r
->reg_type
.bitfield
.sreg2
7621 || r
->reg_type
.bitfield
.sreg3
))
7626 i
.seg
[i
.mem_operands
] = &es
;
7629 i
.seg
[i
.mem_operands
] = &cs
;
7632 i
.seg
[i
.mem_operands
] = &ss
;
7635 i
.seg
[i
.mem_operands
] = &ds
;
7638 i
.seg
[i
.mem_operands
] = &fs
;
7641 i
.seg
[i
.mem_operands
] = &gs
;
7645 /* Skip the ':' and whitespace. */
7647 if (is_space_char (*op_string
))
7650 if (!is_digit_char (*op_string
)
7651 && !is_identifier_char (*op_string
)
7652 && *op_string
!= '('
7653 && *op_string
!= ABSOLUTE_PREFIX
)
7655 as_bad (_("bad memory operand `%s'"), op_string
);
7658 /* Handle case of %es:*foo. */
7659 if (*op_string
== ABSOLUTE_PREFIX
)
7662 if (is_space_char (*op_string
))
7664 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
7666 goto do_memory_reference
;
7670 as_bad (_("junk `%s' after register"), op_string
);
7674 temp
.bitfield
.baseindex
= 0;
7675 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
7677 i
.types
[this_operand
].bitfield
.unspecified
= 0;
7678 i
.op
[this_operand
].regs
= r
;
7681 else if (*op_string
== REGISTER_PREFIX
)
7683 as_bad (_("bad register name `%s'"), op_string
);
7686 else if (*op_string
== IMMEDIATE_PREFIX
)
7689 if (i
.types
[this_operand
].bitfield
.jumpabsolute
)
7691 as_bad (_("immediate operand illegal with absolute jump"));
7694 if (!i386_immediate (op_string
))
7697 else if (is_digit_char (*op_string
)
7698 || is_identifier_char (*op_string
)
7699 || *op_string
== '(')
7701 /* This is a memory reference of some sort. */
7704 /* Start and end of displacement string expression (if found). */
7705 char *displacement_string_start
;
7706 char *displacement_string_end
;
7708 do_memory_reference
:
7709 if ((i
.mem_operands
== 1
7710 && !current_templates
->start
->opcode_modifier
.isstring
)
7711 || i
.mem_operands
== 2)
7713 as_bad (_("too many memory references for `%s'"),
7714 current_templates
->start
->name
);
7718 /* Check for base index form. We detect the base index form by
7719 looking for an ')' at the end of the operand, searching
7720 for the '(' matching it, and finding a REGISTER_PREFIX or ','
7722 base_string
= op_string
+ strlen (op_string
);
7725 if (is_space_char (*base_string
))
7728 /* If we only have a displacement, set-up for it to be parsed later. */
7729 displacement_string_start
= op_string
;
7730 displacement_string_end
= base_string
+ 1;
7732 if (*base_string
== ')')
7735 unsigned int parens_balanced
= 1;
7736 /* We've already checked that the number of left & right ()'s are
7737 equal, so this loop will not be infinite. */
7741 if (*base_string
== ')')
7743 if (*base_string
== '(')
7746 while (parens_balanced
);
7748 temp_string
= base_string
;
7750 /* Skip past '(' and whitespace. */
7752 if (is_space_char (*base_string
))
7755 if (*base_string
== ','
7756 || ((i
.base_reg
= parse_register (base_string
, &end_op
))
7759 displacement_string_end
= temp_string
;
7761 i
.types
[this_operand
].bitfield
.baseindex
= 1;
7765 base_string
= end_op
;
7766 if (is_space_char (*base_string
))
7770 /* There may be an index reg or scale factor here. */
7771 if (*base_string
== ',')
7774 if (is_space_char (*base_string
))
7777 if ((i
.index_reg
= parse_register (base_string
, &end_op
))
7780 base_string
= end_op
;
7781 if (is_space_char (*base_string
))
7783 if (*base_string
== ',')
7786 if (is_space_char (*base_string
))
7789 else if (*base_string
!= ')')
7791 as_bad (_("expecting `,' or `)' "
7792 "after index register in `%s'"),
7797 else if (*base_string
== REGISTER_PREFIX
)
7799 end_op
= strchr (base_string
, ',');
7802 as_bad (_("bad register name `%s'"), base_string
);
7806 /* Check for scale factor. */
7807 if (*base_string
!= ')')
7809 char *end_scale
= i386_scale (base_string
);
7814 base_string
= end_scale
;
7815 if (is_space_char (*base_string
))
7817 if (*base_string
!= ')')
7819 as_bad (_("expecting `)' "
7820 "after scale factor in `%s'"),
7825 else if (!i
.index_reg
)
7827 as_bad (_("expecting index register or scale factor "
7828 "after `,'; got '%c'"),
7833 else if (*base_string
!= ')')
7835 as_bad (_("expecting `,' or `)' "
7836 "after base register in `%s'"),
7841 else if (*base_string
== REGISTER_PREFIX
)
7843 end_op
= strchr (base_string
, ',');
7846 as_bad (_("bad register name `%s'"), base_string
);
7851 /* If there's an expression beginning the operand, parse it,
7852 assuming displacement_string_start and
7853 displacement_string_end are meaningful. */
7854 if (displacement_string_start
!= displacement_string_end
)
7856 if (!i386_displacement (displacement_string_start
,
7857 displacement_string_end
))
7861 /* Special case for (%dx) while doing input/output op. */
7863 && operand_type_equal (&i
.base_reg
->reg_type
,
7864 ®16_inoutportreg
)
7866 && i
.log2_scale_factor
== 0
7867 && i
.seg
[i
.mem_operands
] == 0
7868 && !operand_type_check (i
.types
[this_operand
], disp
))
7870 i
.types
[this_operand
] = inoutportreg
;
7874 if (i386_index_check (operand_string
) == 0)
7876 i
.types
[this_operand
].bitfield
.mem
= 1;
7881 /* It's not a memory operand; argh! */
7882 as_bad (_("invalid char %s beginning operand %d `%s'"),
7883 output_invalid (*op_string
),
7888 return 1; /* Normal return. */
7891 /* Calculate the maximum variable size (i.e., excluding fr_fix)
7892 that an rs_machine_dependent frag may reach. */
7895 i386_frag_max_var (fragS
*frag
)
7897 /* The only relaxable frags are for jumps.
7898 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
7899 gas_assert (frag
->fr_type
== rs_machine_dependent
);
7900 return TYPE_FROM_RELAX_STATE (frag
->fr_subtype
) == UNCOND_JUMP
? 4 : 5;
7903 /* md_estimate_size_before_relax()
7905 Called just before relax() for rs_machine_dependent frags. The x86
7906 assembler uses these frags to handle variable size jump
7909 Any symbol that is now undefined will not become defined.
7910 Return the correct fr_subtype in the frag.
7911 Return the initial "guess for variable size of frag" to caller.
7912 The guess is actually the growth beyond the fixed part. Whatever
7913 we do to grow the fixed or variable part contributes to our
7917 md_estimate_size_before_relax (fragS
*fragP
, segT segment
)
7919 /* We've already got fragP->fr_subtype right; all we have to do is
7920 check for un-relaxable symbols. On an ELF system, we can't relax
7921 an externally visible symbol, because it may be overridden by a
7923 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
7924 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7926 && (S_IS_EXTERNAL (fragP
->fr_symbol
)
7927 || S_IS_WEAK (fragP
->fr_symbol
)
7928 || ((symbol_get_bfdsym (fragP
->fr_symbol
)->flags
7929 & BSF_GNU_INDIRECT_FUNCTION
))))
7931 #if defined (OBJ_COFF) && defined (TE_PE)
7932 || (OUTPUT_FLAVOR
== bfd_target_coff_flavour
7933 && S_IS_WEAK (fragP
->fr_symbol
))
7937 /* Symbol is undefined in this segment, or we need to keep a
7938 reloc so that weak symbols can be overridden. */
7939 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
7940 enum bfd_reloc_code_real reloc_type
;
7941 unsigned char *opcode
;
7944 if (fragP
->fr_var
!= NO_RELOC
)
7945 reloc_type
= (enum bfd_reloc_code_real
) fragP
->fr_var
;
7947 reloc_type
= BFD_RELOC_16_PCREL
;
7949 reloc_type
= BFD_RELOC_32_PCREL
;
7951 old_fr_fix
= fragP
->fr_fix
;
7952 opcode
= (unsigned char *) fragP
->fr_opcode
;
7954 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
7957 /* Make jmp (0xeb) a (d)word displacement jump. */
7959 fragP
->fr_fix
+= size
;
7960 fix_new (fragP
, old_fr_fix
, size
,
7962 fragP
->fr_offset
, 1,
7968 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
7970 /* Negate the condition, and branch past an
7971 unconditional jump. */
7974 /* Insert an unconditional jump. */
7976 /* We added two extra opcode bytes, and have a two byte
7978 fragP
->fr_fix
+= 2 + 2;
7979 fix_new (fragP
, old_fr_fix
+ 2, 2,
7981 fragP
->fr_offset
, 1,
7988 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
7993 fixP
= fix_new (fragP
, old_fr_fix
, 1,
7995 fragP
->fr_offset
, 1,
7997 fixP
->fx_signed
= 1;
8001 /* This changes the byte-displacement jump 0x7N
8002 to the (d)word-displacement jump 0x0f,0x8N. */
8003 opcode
[1] = opcode
[0] + 0x10;
8004 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
8005 /* We've added an opcode byte. */
8006 fragP
->fr_fix
+= 1 + size
;
8007 fix_new (fragP
, old_fr_fix
+ 1, size
,
8009 fragP
->fr_offset
, 1,
8014 BAD_CASE (fragP
->fr_subtype
);
8018 return fragP
->fr_fix
- old_fr_fix
;
8021 /* Guess size depending on current relax state. Initially the relax
8022 state will correspond to a short jump and we return 1, because
8023 the variable part of the frag (the branch offset) is one byte
8024 long. However, we can relax a section more than once and in that
8025 case we must either set fr_subtype back to the unrelaxed state,
8026 or return the value for the appropriate branch. */
8027 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
8030 /* Called after relax() is finished.
8032 In: Address of frag.
8033 fr_type == rs_machine_dependent.
8034 fr_subtype is what the address relaxed to.
8036 Out: Any fixSs and constants are set up.
8037 Caller will turn frag into a ".space 0". */
8040 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec ATTRIBUTE_UNUSED
,
8043 unsigned char *opcode
;
8044 unsigned char *where_to_put_displacement
= NULL
;
8045 offsetT target_address
;
8046 offsetT opcode_address
;
8047 unsigned int extension
= 0;
8048 offsetT displacement_from_opcode_start
;
8050 opcode
= (unsigned char *) fragP
->fr_opcode
;
8052 /* Address we want to reach in file space. */
8053 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
8055 /* Address opcode resides at in file space. */
8056 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
8058 /* Displacement from opcode start to fill into instruction. */
8059 displacement_from_opcode_start
= target_address
- opcode_address
;
8061 if ((fragP
->fr_subtype
& BIG
) == 0)
8063 /* Don't have to change opcode. */
8064 extension
= 1; /* 1 opcode + 1 displacement */
8065 where_to_put_displacement
= &opcode
[1];
8069 if (no_cond_jump_promotion
8070 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
8071 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
8072 _("long jump required"));
8074 switch (fragP
->fr_subtype
)
8076 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
8077 extension
= 4; /* 1 opcode + 4 displacement */
8079 where_to_put_displacement
= &opcode
[1];
8082 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
8083 extension
= 2; /* 1 opcode + 2 displacement */
8085 where_to_put_displacement
= &opcode
[1];
8088 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
8089 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
8090 extension
= 5; /* 2 opcode + 4 displacement */
8091 opcode
[1] = opcode
[0] + 0x10;
8092 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
8093 where_to_put_displacement
= &opcode
[2];
8096 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
8097 extension
= 3; /* 2 opcode + 2 displacement */
8098 opcode
[1] = opcode
[0] + 0x10;
8099 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
8100 where_to_put_displacement
= &opcode
[2];
8103 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
8108 where_to_put_displacement
= &opcode
[3];
8112 BAD_CASE (fragP
->fr_subtype
);
8117 /* If size if less then four we are sure that the operand fits,
8118 but if it's 4, then it could be that the displacement is larger
8120 if (DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
) == 4
8122 && ((addressT
) (displacement_from_opcode_start
- extension
8123 + ((addressT
) 1 << 31))
8124 > (((addressT
) 2 << 31) - 1)))
8126 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
8127 _("jump target out of range"));
8128 /* Make us emit 0. */
8129 displacement_from_opcode_start
= extension
;
8131 /* Now put displacement after opcode. */
8132 md_number_to_chars ((char *) where_to_put_displacement
,
8133 (valueT
) (displacement_from_opcode_start
- extension
),
8134 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
8135 fragP
->fr_fix
+= extension
;
8138 /* Apply a fixup (fixP) to segment data, once it has been determined
8139 by our caller that we have all the info we need to fix it up.
8141 Parameter valP is the pointer to the value of the bits.
8143 On the 386, immediates, displacements, and data pointers are all in
8144 the same (little-endian) format, so we don't need to care about which
8148 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
8150 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
8151 valueT value
= *valP
;
8153 #if !defined (TE_Mach)
8156 switch (fixP
->fx_r_type
)
8162 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
8165 case BFD_RELOC_X86_64_32S
:
8166 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
8169 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
8172 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
8177 if (fixP
->fx_addsy
!= NULL
8178 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
8179 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
8180 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
8181 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
8182 && !use_rela_relocations
)
8184 /* This is a hack. There should be a better way to handle this.
8185 This covers for the fact that bfd_install_relocation will
8186 subtract the current location (for partial_inplace, PC relative
8187 relocations); see more below. */
8191 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
8194 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
8196 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8199 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
8202 || (symbol_section_p (fixP
->fx_addsy
)
8203 && sym_seg
!= absolute_section
))
8204 && !generic_force_reloc (fixP
))
8206 /* Yes, we add the values in twice. This is because
8207 bfd_install_relocation subtracts them out again. I think
8208 bfd_install_relocation is broken, but I don't dare change
8210 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
8214 #if defined (OBJ_COFF) && defined (TE_PE)
8215 /* For some reason, the PE format does not store a
8216 section address offset for a PC relative symbol. */
8217 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
8218 || S_IS_WEAK (fixP
->fx_addsy
))
8219 value
+= md_pcrel_from (fixP
);
8222 #if defined (OBJ_COFF) && defined (TE_PE)
8223 if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
8225 value
-= S_GET_VALUE (fixP
->fx_addsy
);
8229 /* Fix a few things - the dynamic linker expects certain values here,
8230 and we must not disappoint it. */
8231 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8232 if (IS_ELF
&& fixP
->fx_addsy
)
8233 switch (fixP
->fx_r_type
)
8235 case BFD_RELOC_386_PLT32
:
8236 case BFD_RELOC_X86_64_PLT32
:
8237 /* Make the jump instruction point to the address of the operand. At
8238 runtime we merely add the offset to the actual PLT entry. */
8242 case BFD_RELOC_386_TLS_GD
:
8243 case BFD_RELOC_386_TLS_LDM
:
8244 case BFD_RELOC_386_TLS_IE_32
:
8245 case BFD_RELOC_386_TLS_IE
:
8246 case BFD_RELOC_386_TLS_GOTIE
:
8247 case BFD_RELOC_386_TLS_GOTDESC
:
8248 case BFD_RELOC_X86_64_TLSGD
:
8249 case BFD_RELOC_X86_64_TLSLD
:
8250 case BFD_RELOC_X86_64_GOTTPOFF
:
8251 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
8252 value
= 0; /* Fully resolved at runtime. No addend. */
8254 case BFD_RELOC_386_TLS_LE
:
8255 case BFD_RELOC_386_TLS_LDO_32
:
8256 case BFD_RELOC_386_TLS_LE_32
:
8257 case BFD_RELOC_X86_64_DTPOFF32
:
8258 case BFD_RELOC_X86_64_DTPOFF64
:
8259 case BFD_RELOC_X86_64_TPOFF32
:
8260 case BFD_RELOC_X86_64_TPOFF64
:
8261 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
8264 case BFD_RELOC_386_TLS_DESC_CALL
:
8265 case BFD_RELOC_X86_64_TLSDESC_CALL
:
8266 value
= 0; /* Fully resolved at runtime. No addend. */
8267 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
8271 case BFD_RELOC_386_GOT32
:
8272 case BFD_RELOC_X86_64_GOT32
:
8273 value
= 0; /* Fully resolved at runtime. No addend. */
8276 case BFD_RELOC_VTABLE_INHERIT
:
8277 case BFD_RELOC_VTABLE_ENTRY
:
8284 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
8286 #endif /* !defined (TE_Mach) */
8288 /* Are we finished with this relocation now? */
8289 if (fixP
->fx_addsy
== NULL
)
8291 #if defined (OBJ_COFF) && defined (TE_PE)
8292 else if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
8295 /* Remember value for tc_gen_reloc. */
8296 fixP
->fx_addnumber
= value
;
8297 /* Clear out the frag for now. */
8301 else if (use_rela_relocations
)
8303 fixP
->fx_no_overflow
= 1;
8304 /* Remember value for tc_gen_reloc. */
8305 fixP
->fx_addnumber
= value
;
8309 md_number_to_chars (p
, value
, fixP
->fx_size
);
8313 md_atof (int type
, char *litP
, int *sizeP
)
8315 /* This outputs the LITTLENUMs in REVERSE order;
8316 in accord with the bigendian 386. */
8317 return ieee_md_atof (type
, litP
, sizeP
, FALSE
);
8320 static char output_invalid_buf
[sizeof (unsigned char) * 2 + 6];
8323 output_invalid (int c
)
8326 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
8329 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
8330 "(0x%x)", (unsigned char) c
);
8331 return output_invalid_buf
;
8334 /* REG_STRING starts *before* REGISTER_PREFIX. */
8336 static const reg_entry
*
8337 parse_real_register (char *reg_string
, char **end_op
)
8339 char *s
= reg_string
;
8341 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
8344 /* Skip possible REGISTER_PREFIX and possible whitespace. */
8345 if (*s
== REGISTER_PREFIX
)
8348 if (is_space_char (*s
))
8352 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
8354 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
8355 return (const reg_entry
*) NULL
;
8359 /* For naked regs, make sure that we are not dealing with an identifier.
8360 This prevents confusing an identifier like `eax_var' with register
8362 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
8363 return (const reg_entry
*) NULL
;
8367 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
8369 /* Handle floating point regs, allowing spaces in the (i) part. */
8370 if (r
== i386_regtab
/* %st is first entry of table */)
8372 if (is_space_char (*s
))
8377 if (is_space_char (*s
))
8379 if (*s
>= '0' && *s
<= '7')
8383 if (is_space_char (*s
))
8388 r
= (const reg_entry
*) hash_find (reg_hash
, "st(0)");
8393 /* We have "%st(" then garbage. */
8394 return (const reg_entry
*) NULL
;
8398 if (r
== NULL
|| allow_pseudo_reg
)
8401 if (operand_type_all_zero (&r
->reg_type
))
8402 return (const reg_entry
*) NULL
;
8404 if ((r
->reg_type
.bitfield
.reg32
8405 || r
->reg_type
.bitfield
.sreg3
8406 || r
->reg_type
.bitfield
.control
8407 || r
->reg_type
.bitfield
.debug
8408 || r
->reg_type
.bitfield
.test
)
8409 && !cpu_arch_flags
.bitfield
.cpui386
)
8410 return (const reg_entry
*) NULL
;
8412 if (r
->reg_type
.bitfield
.floatreg
8413 && !cpu_arch_flags
.bitfield
.cpu8087
8414 && !cpu_arch_flags
.bitfield
.cpu287
8415 && !cpu_arch_flags
.bitfield
.cpu387
)
8416 return (const reg_entry
*) NULL
;
8418 if (r
->reg_type
.bitfield
.regmmx
&& !cpu_arch_flags
.bitfield
.cpummx
)
8419 return (const reg_entry
*) NULL
;
8421 if (r
->reg_type
.bitfield
.regxmm
&& !cpu_arch_flags
.bitfield
.cpusse
)
8422 return (const reg_entry
*) NULL
;
8424 if (r
->reg_type
.bitfield
.regymm
&& !cpu_arch_flags
.bitfield
.cpuavx
)
8425 return (const reg_entry
*) NULL
;
8427 /* Don't allow fake index register unless allow_index_reg isn't 0. */
8428 if (!allow_index_reg
8429 && (r
->reg_num
== RegEiz
|| r
->reg_num
== RegRiz
))
8430 return (const reg_entry
*) NULL
;
8432 if (((r
->reg_flags
& (RegRex64
| RegRex
))
8433 || r
->reg_type
.bitfield
.reg64
)
8434 && (!cpu_arch_flags
.bitfield
.cpulm
8435 || !operand_type_equal (&r
->reg_type
, &control
))
8436 && flag_code
!= CODE_64BIT
)
8437 return (const reg_entry
*) NULL
;
8439 if (r
->reg_type
.bitfield
.sreg3
&& r
->reg_num
== RegFlat
&& !intel_syntax
)
8440 return (const reg_entry
*) NULL
;
8445 /* REG_STRING starts *before* REGISTER_PREFIX. */
8447 static const reg_entry
*
8448 parse_register (char *reg_string
, char **end_op
)
8452 if (*reg_string
== REGISTER_PREFIX
|| allow_naked_reg
)
8453 r
= parse_real_register (reg_string
, end_op
);
8458 char *save
= input_line_pointer
;
8462 input_line_pointer
= reg_string
;
8463 c
= get_symbol_end ();
8464 symbolP
= symbol_find (reg_string
);
8465 if (symbolP
&& S_GET_SEGMENT (symbolP
) == reg_section
)
8467 const expressionS
*e
= symbol_get_value_expression (symbolP
);
8469 know (e
->X_op
== O_register
);
8470 know (e
->X_add_number
>= 0
8471 && (valueT
) e
->X_add_number
< i386_regtab_size
);
8472 r
= i386_regtab
+ e
->X_add_number
;
8473 *end_op
= input_line_pointer
;
8475 *input_line_pointer
= c
;
8476 input_line_pointer
= save
;
8482 i386_parse_name (char *name
, expressionS
*e
, char *nextcharP
)
8485 char *end
= input_line_pointer
;
8488 r
= parse_register (name
, &input_line_pointer
);
8489 if (r
&& end
<= input_line_pointer
)
8491 *nextcharP
= *input_line_pointer
;
8492 *input_line_pointer
= 0;
8493 e
->X_op
= O_register
;
8494 e
->X_add_number
= r
- i386_regtab
;
8497 input_line_pointer
= end
;
8499 return intel_syntax
? i386_intel_parse_name (name
, e
) : 0;
8503 md_operand (expressionS
*e
)
8508 switch (*input_line_pointer
)
8510 case REGISTER_PREFIX
:
8511 r
= parse_real_register (input_line_pointer
, &end
);
8514 e
->X_op
= O_register
;
8515 e
->X_add_number
= r
- i386_regtab
;
8516 input_line_pointer
= end
;
8521 gas_assert (intel_syntax
);
8522 end
= input_line_pointer
++;
8524 if (*input_line_pointer
== ']')
8526 ++input_line_pointer
;
8527 e
->X_op_symbol
= make_expr_symbol (e
);
8528 e
->X_add_symbol
= NULL
;
8529 e
->X_add_number
= 0;
8535 input_line_pointer
= end
;
8542 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8543 const char *md_shortopts
= "kVQ:sqn";
8545 const char *md_shortopts
= "qn";
8548 #define OPTION_32 (OPTION_MD_BASE + 0)
8549 #define OPTION_64 (OPTION_MD_BASE + 1)
8550 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
8551 #define OPTION_MARCH (OPTION_MD_BASE + 3)
8552 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
8553 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
8554 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
8555 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
8556 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
8557 #define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
8558 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
8559 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
8560 #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
8561 #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
8562 #define OPTION_X32 (OPTION_MD_BASE + 14)
8564 struct option md_longopts
[] =
8566 {"32", no_argument
, NULL
, OPTION_32
},
8567 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
8568 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
8569 {"64", no_argument
, NULL
, OPTION_64
},
8571 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8572 {"x32", no_argument
, NULL
, OPTION_X32
},
8574 {"divide", no_argument
, NULL
, OPTION_DIVIDE
},
8575 {"march", required_argument
, NULL
, OPTION_MARCH
},
8576 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
8577 {"mmnemonic", required_argument
, NULL
, OPTION_MMNEMONIC
},
8578 {"msyntax", required_argument
, NULL
, OPTION_MSYNTAX
},
8579 {"mindex-reg", no_argument
, NULL
, OPTION_MINDEX_REG
},
8580 {"mnaked-reg", no_argument
, NULL
, OPTION_MNAKED_REG
},
8581 {"mold-gcc", no_argument
, NULL
, OPTION_MOLD_GCC
},
8582 {"msse2avx", no_argument
, NULL
, OPTION_MSSE2AVX
},
8583 {"msse-check", required_argument
, NULL
, OPTION_MSSE_CHECK
},
8584 {"moperand-check", required_argument
, NULL
, OPTION_MOPERAND_CHECK
},
8585 {"mavxscalar", required_argument
, NULL
, OPTION_MAVXSCALAR
},
8586 {NULL
, no_argument
, NULL
, 0}
8588 size_t md_longopts_size
= sizeof (md_longopts
);
8591 md_parse_option (int c
, char *arg
)
8599 optimize_align_code
= 0;
8606 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8607 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
8608 should be emitted or not. FIXME: Not implemented. */
8612 /* -V: SVR4 argument to print version ID. */
8614 print_version_id ();
8617 /* -k: Ignore for FreeBSD compatibility. */
8622 /* -s: On i386 Solaris, this tells the native assembler to use
8623 .stab instead of .stab.excl. We always use .stab anyhow. */
8626 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
8627 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
8630 const char **list
, **l
;
8632 list
= bfd_target_list ();
8633 for (l
= list
; *l
!= NULL
; l
++)
8634 if (CONST_STRNEQ (*l
, "elf64-x86-64")
8635 || strcmp (*l
, "coff-x86-64") == 0
8636 || strcmp (*l
, "pe-x86-64") == 0
8637 || strcmp (*l
, "pei-x86-64") == 0
8638 || strcmp (*l
, "mach-o-x86-64") == 0)
8640 default_arch
= "x86_64";
8644 as_fatal (_("no compiled in support for x86_64"));
8650 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8654 const char **list
, **l
;
8656 list
= bfd_target_list ();
8657 for (l
= list
; *l
!= NULL
; l
++)
8658 if (CONST_STRNEQ (*l
, "elf32-x86-64"))
8660 default_arch
= "x86_64:32";
8664 as_fatal (_("no compiled in support for 32bit x86_64"));
8668 as_fatal (_("32bit x86_64 is only supported for ELF"));
8673 default_arch
= "i386";
8677 #ifdef SVR4_COMMENT_CHARS
8682 n
= (char *) xmalloc (strlen (i386_comment_chars
) + 1);
8684 for (s
= i386_comment_chars
; *s
!= '\0'; s
++)
8688 i386_comment_chars
= n
;
8694 arch
= xstrdup (arg
);
8698 as_fatal (_("invalid -march= option: `%s'"), arg
);
8699 next
= strchr (arch
, '+');
8702 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
8704 if (strcmp (arch
, cpu_arch
[j
].name
) == 0)
8707 if (! cpu_arch
[j
].flags
.bitfield
.cpui386
)
8710 cpu_arch_name
= cpu_arch
[j
].name
;
8711 cpu_sub_arch_name
= NULL
;
8712 cpu_arch_flags
= cpu_arch
[j
].flags
;
8713 cpu_arch_isa
= cpu_arch
[j
].type
;
8714 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
8715 if (!cpu_arch_tune_set
)
8717 cpu_arch_tune
= cpu_arch_isa
;
8718 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
8722 else if (*cpu_arch
[j
].name
== '.'
8723 && strcmp (arch
, cpu_arch
[j
].name
+ 1) == 0)
8725 /* ISA entension. */
8726 i386_cpu_flags flags
;
8728 if (!cpu_arch
[j
].negated
)
8729 flags
= cpu_flags_or (cpu_arch_flags
,
8732 flags
= cpu_flags_and_not (cpu_arch_flags
,
8734 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
8736 if (cpu_sub_arch_name
)
8738 char *name
= cpu_sub_arch_name
;
8739 cpu_sub_arch_name
= concat (name
,
8741 (const char *) NULL
);
8745 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
8746 cpu_arch_flags
= flags
;
8747 cpu_arch_isa_flags
= flags
;
8753 if (j
>= ARRAY_SIZE (cpu_arch
))
8754 as_fatal (_("invalid -march= option: `%s'"), arg
);
8758 while (next
!= NULL
);
8763 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
8764 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
8766 if (strcmp (arg
, cpu_arch
[j
].name
) == 0)
8768 cpu_arch_tune_set
= 1;
8769 cpu_arch_tune
= cpu_arch
[j
].type
;
8770 cpu_arch_tune_flags
= cpu_arch
[j
].flags
;
8774 if (j
>= ARRAY_SIZE (cpu_arch
))
8775 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
8778 case OPTION_MMNEMONIC
:
8779 if (strcasecmp (arg
, "att") == 0)
8781 else if (strcasecmp (arg
, "intel") == 0)
8784 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg
);
8787 case OPTION_MSYNTAX
:
8788 if (strcasecmp (arg
, "att") == 0)
8790 else if (strcasecmp (arg
, "intel") == 0)
8793 as_fatal (_("invalid -msyntax= option: `%s'"), arg
);
8796 case OPTION_MINDEX_REG
:
8797 allow_index_reg
= 1;
8800 case OPTION_MNAKED_REG
:
8801 allow_naked_reg
= 1;
8804 case OPTION_MOLD_GCC
:
8808 case OPTION_MSSE2AVX
:
8812 case OPTION_MSSE_CHECK
:
8813 if (strcasecmp (arg
, "error") == 0)
8814 sse_check
= check_error
;
8815 else if (strcasecmp (arg
, "warning") == 0)
8816 sse_check
= check_warning
;
8817 else if (strcasecmp (arg
, "none") == 0)
8818 sse_check
= check_none
;
8820 as_fatal (_("invalid -msse-check= option: `%s'"), arg
);
8823 case OPTION_MOPERAND_CHECK
:
8824 if (strcasecmp (arg
, "error") == 0)
8825 operand_check
= check_error
;
8826 else if (strcasecmp (arg
, "warning") == 0)
8827 operand_check
= check_warning
;
8828 else if (strcasecmp (arg
, "none") == 0)
8829 operand_check
= check_none
;
8831 as_fatal (_("invalid -moperand-check= option: `%s'"), arg
);
8834 case OPTION_MAVXSCALAR
:
8835 if (strcasecmp (arg
, "128") == 0)
8837 else if (strcasecmp (arg
, "256") == 0)
8840 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg
);
8849 #define MESSAGE_TEMPLATE \
8853 show_arch (FILE *stream
, int ext
, int check
)
8855 static char message
[] = MESSAGE_TEMPLATE
;
8856 char *start
= message
+ 27;
8858 int size
= sizeof (MESSAGE_TEMPLATE
);
8865 left
= size
- (start
- message
);
8866 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
8868 /* Should it be skipped? */
8869 if (cpu_arch
[j
].skip
)
8872 name
= cpu_arch
[j
].name
;
8873 len
= cpu_arch
[j
].len
;
8876 /* It is an extension. Skip if we aren't asked to show it. */
8887 /* It is an processor. Skip if we show only extension. */
8890 else if (check
&& ! cpu_arch
[j
].flags
.bitfield
.cpui386
)
8892 /* It is an impossible processor - skip. */
8896 /* Reserve 2 spaces for ", " or ",\0" */
8899 /* Check if there is any room. */
8907 p
= mempcpy (p
, name
, len
);
8911 /* Output the current message now and start a new one. */
8914 fprintf (stream
, "%s\n", message
);
8916 left
= size
- (start
- message
) - len
- 2;
8918 gas_assert (left
>= 0);
8920 p
= mempcpy (p
, name
, len
);
8925 fprintf (stream
, "%s\n", message
);
8929 md_show_usage (FILE *stream
)
8931 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8932 fprintf (stream
, _("\
8934 -V print assembler version number\n\
8937 fprintf (stream
, _("\
8938 -n Do not optimize code alignment\n\
8939 -q quieten some warnings\n"));
8940 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8941 fprintf (stream
, _("\
8944 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
8945 || defined (TE_PE) || defined (TE_PEP))
8946 fprintf (stream
, _("\
8947 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
8949 #ifdef SVR4_COMMENT_CHARS
8950 fprintf (stream
, _("\
8951 --divide do not treat `/' as a comment character\n"));
8953 fprintf (stream
, _("\
8954 --divide ignored\n"));
8956 fprintf (stream
, _("\
8957 -march=CPU[,+EXTENSION...]\n\
8958 generate code for CPU and EXTENSION, CPU is one of:\n"));
8959 show_arch (stream
, 0, 1);
8960 fprintf (stream
, _("\
8961 EXTENSION is combination of:\n"));
8962 show_arch (stream
, 1, 0);
8963 fprintf (stream
, _("\
8964 -mtune=CPU optimize for CPU, CPU is one of:\n"));
8965 show_arch (stream
, 0, 0);
8966 fprintf (stream
, _("\
8967 -msse2avx encode SSE instructions with VEX prefix\n"));
8968 fprintf (stream
, _("\
8969 -msse-check=[none|error|warning]\n\
8970 check SSE instructions\n"));
8971 fprintf (stream
, _("\
8972 -moperand-check=[none|error|warning]\n\
8973 check operand combinations for validity\n"));
8974 fprintf (stream
, _("\
8975 -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n\
8977 fprintf (stream
, _("\
8978 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
8979 fprintf (stream
, _("\
8980 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
8981 fprintf (stream
, _("\
8982 -mindex-reg support pseudo index registers\n"));
8983 fprintf (stream
, _("\
8984 -mnaked-reg don't require `%%' prefix for registers\n"));
8985 fprintf (stream
, _("\
8986 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
8989 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
8990 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
8991 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
8993 /* Pick the target format to use. */
8996 i386_target_format (void)
8998 if (!strncmp (default_arch
, "x86_64", 6))
9000 update_code_flag (CODE_64BIT
, 1);
9001 if (default_arch
[6] == '\0')
9002 x86_elf_abi
= X86_64_ABI
;
9004 x86_elf_abi
= X86_64_X32_ABI
;
9006 else if (!strcmp (default_arch
, "i386"))
9007 update_code_flag (CODE_32BIT
, 1);
9009 as_fatal (_("unknown architecture"));
9011 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
9012 cpu_arch_isa_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
9013 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
9014 cpu_arch_tune_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
9016 switch (OUTPUT_FLAVOR
)
9018 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
9019 case bfd_target_aout_flavour
:
9020 return AOUT_TARGET_FORMAT
;
9022 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
9023 # if defined (TE_PE) || defined (TE_PEP)
9024 case bfd_target_coff_flavour
:
9025 return flag_code
== CODE_64BIT
? "pe-x86-64" : "pe-i386";
9026 # elif defined (TE_GO32)
9027 case bfd_target_coff_flavour
:
9030 case bfd_target_coff_flavour
:
9034 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
9035 case bfd_target_elf_flavour
:
9039 switch (x86_elf_abi
)
9042 format
= ELF_TARGET_FORMAT
;
9045 use_rela_relocations
= 1;
9047 format
= ELF_TARGET_FORMAT64
;
9049 case X86_64_X32_ABI
:
9050 use_rela_relocations
= 1;
9052 disallow_64bit_reloc
= 1;
9053 format
= ELF_TARGET_FORMAT32
;
9056 if (cpu_arch_isa
== PROCESSOR_L1OM
)
9058 if (x86_elf_abi
!= X86_64_ABI
)
9059 as_fatal (_("Intel L1OM is 64bit only"));
9060 return ELF_TARGET_L1OM_FORMAT
;
9062 if (cpu_arch_isa
== PROCESSOR_K1OM
)
9064 if (x86_elf_abi
!= X86_64_ABI
)
9065 as_fatal (_("Intel K1OM is 64bit only"));
9066 return ELF_TARGET_K1OM_FORMAT
;
9072 #if defined (OBJ_MACH_O)
9073 case bfd_target_mach_o_flavour
:
9074 if (flag_code
== CODE_64BIT
)
9076 use_rela_relocations
= 1;
9078 return "mach-o-x86-64";
9081 return "mach-o-i386";
9089 #endif /* OBJ_MAYBE_ more than one */
9091 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
9093 i386_elf_emit_arch_note (void)
9095 if (IS_ELF
&& cpu_arch_name
!= NULL
)
9098 asection
*seg
= now_seg
;
9099 subsegT subseg
= now_subseg
;
9100 Elf_Internal_Note i_note
;
9101 Elf_External_Note e_note
;
9102 asection
*note_secp
;
9105 /* Create the .note section. */
9106 note_secp
= subseg_new (".note", 0);
9107 bfd_set_section_flags (stdoutput
,
9109 SEC_HAS_CONTENTS
| SEC_READONLY
);
9111 /* Process the arch string. */
9112 len
= strlen (cpu_arch_name
);
9114 i_note
.namesz
= len
+ 1;
9116 i_note
.type
= NT_ARCH
;
9117 p
= frag_more (sizeof (e_note
.namesz
));
9118 md_number_to_chars (p
, (valueT
) i_note
.namesz
, sizeof (e_note
.namesz
));
9119 p
= frag_more (sizeof (e_note
.descsz
));
9120 md_number_to_chars (p
, (valueT
) i_note
.descsz
, sizeof (e_note
.descsz
));
9121 p
= frag_more (sizeof (e_note
.type
));
9122 md_number_to_chars (p
, (valueT
) i_note
.type
, sizeof (e_note
.type
));
9123 p
= frag_more (len
+ 1);
9124 strcpy (p
, cpu_arch_name
);
9126 frag_align (2, 0, 0);
9128 subseg_set (seg
, subseg
);
9134 md_undefined_symbol (char *name
)
9136 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
9137 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
9138 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
9139 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
9143 if (symbol_find (name
))
9144 as_bad (_("GOT already in symbol table"));
9145 GOT_symbol
= symbol_new (name
, undefined_section
,
9146 (valueT
) 0, &zero_address_frag
);
9153 /* Round up a section size to the appropriate boundary. */
9156 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
9158 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
9159 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
9161 /* For a.out, force the section size to be aligned. If we don't do
9162 this, BFD will align it for us, but it will not write out the
9163 final bytes of the section. This may be a bug in BFD, but it is
9164 easier to fix it here since that is how the other a.out targets
9168 align
= bfd_get_section_alignment (stdoutput
, segment
);
9169 size
= ((size
+ (1 << align
) - 1) & ((valueT
) -1 << align
));
9176 /* On the i386, PC-relative offsets are relative to the start of the
9177 next instruction. That is, the address of the offset, plus its
9178 size, since the offset is always the last part of the insn. */
9181 md_pcrel_from (fixS
*fixP
)
9183 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
9189 s_bss (int ignore ATTRIBUTE_UNUSED
)
9193 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9195 obj_elf_section_change_hook ();
9197 temp
= get_absolute_expression ();
9198 subseg_set (bss_section
, (subsegT
) temp
);
9199 demand_empty_rest_of_line ();
9205 i386_validate_fix (fixS
*fixp
)
9207 if (fixp
->fx_subsy
&& fixp
->fx_subsy
== GOT_symbol
)
9209 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
9213 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
9218 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
9220 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
9227 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
9230 bfd_reloc_code_real_type code
;
9232 switch (fixp
->fx_r_type
)
9234 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9235 case BFD_RELOC_SIZE32
:
9236 case BFD_RELOC_SIZE64
:
9237 if (S_IS_DEFINED (fixp
->fx_addsy
)
9238 && !S_IS_EXTERNAL (fixp
->fx_addsy
))
9240 /* Resolve size relocation against local symbol to size of
9241 the symbol plus addend. */
9242 valueT value
= S_GET_SIZE (fixp
->fx_addsy
) + fixp
->fx_offset
;
9243 if (fixp
->fx_r_type
== BFD_RELOC_SIZE32
9244 && !fits_in_unsigned_long (value
))
9245 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
9246 _("symbol size computation overflow"));
9247 fixp
->fx_addsy
= NULL
;
9248 fixp
->fx_subsy
= NULL
;
9249 md_apply_fix (fixp
, (valueT
*) &value
, NULL
);
9254 case BFD_RELOC_X86_64_PLT32
:
9255 case BFD_RELOC_X86_64_GOT32
:
9256 case BFD_RELOC_X86_64_GOTPCREL
:
9257 case BFD_RELOC_386_PLT32
:
9258 case BFD_RELOC_386_GOT32
:
9259 case BFD_RELOC_386_GOTOFF
:
9260 case BFD_RELOC_386_GOTPC
:
9261 case BFD_RELOC_386_TLS_GD
:
9262 case BFD_RELOC_386_TLS_LDM
:
9263 case BFD_RELOC_386_TLS_LDO_32
:
9264 case BFD_RELOC_386_TLS_IE_32
:
9265 case BFD_RELOC_386_TLS_IE
:
9266 case BFD_RELOC_386_TLS_GOTIE
:
9267 case BFD_RELOC_386_TLS_LE_32
:
9268 case BFD_RELOC_386_TLS_LE
:
9269 case BFD_RELOC_386_TLS_GOTDESC
:
9270 case BFD_RELOC_386_TLS_DESC_CALL
:
9271 case BFD_RELOC_X86_64_TLSGD
:
9272 case BFD_RELOC_X86_64_TLSLD
:
9273 case BFD_RELOC_X86_64_DTPOFF32
:
9274 case BFD_RELOC_X86_64_DTPOFF64
:
9275 case BFD_RELOC_X86_64_GOTTPOFF
:
9276 case BFD_RELOC_X86_64_TPOFF32
:
9277 case BFD_RELOC_X86_64_TPOFF64
:
9278 case BFD_RELOC_X86_64_GOTOFF64
:
9279 case BFD_RELOC_X86_64_GOTPC32
:
9280 case BFD_RELOC_X86_64_GOT64
:
9281 case BFD_RELOC_X86_64_GOTPCREL64
:
9282 case BFD_RELOC_X86_64_GOTPC64
:
9283 case BFD_RELOC_X86_64_GOTPLT64
:
9284 case BFD_RELOC_X86_64_PLTOFF64
:
9285 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
9286 case BFD_RELOC_X86_64_TLSDESC_CALL
:
9288 case BFD_RELOC_VTABLE_ENTRY
:
9289 case BFD_RELOC_VTABLE_INHERIT
:
9291 case BFD_RELOC_32_SECREL
:
9293 code
= fixp
->fx_r_type
;
9295 case BFD_RELOC_X86_64_32S
:
9296 if (!fixp
->fx_pcrel
)
9298 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
9299 code
= fixp
->fx_r_type
;
9305 switch (fixp
->fx_size
)
9308 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
9309 _("can not do %d byte pc-relative relocation"),
9311 code
= BFD_RELOC_32_PCREL
;
9313 case 1: code
= BFD_RELOC_8_PCREL
; break;
9314 case 2: code
= BFD_RELOC_16_PCREL
; break;
9315 case 4: code
= BFD_RELOC_32_PCREL
; break;
9317 case 8: code
= BFD_RELOC_64_PCREL
; break;
9323 switch (fixp
->fx_size
)
9326 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
9327 _("can not do %d byte relocation"),
9329 code
= BFD_RELOC_32
;
9331 case 1: code
= BFD_RELOC_8
; break;
9332 case 2: code
= BFD_RELOC_16
; break;
9333 case 4: code
= BFD_RELOC_32
; break;
9335 case 8: code
= BFD_RELOC_64
; break;
9342 if ((code
== BFD_RELOC_32
9343 || code
== BFD_RELOC_32_PCREL
9344 || code
== BFD_RELOC_X86_64_32S
)
9346 && fixp
->fx_addsy
== GOT_symbol
)
9349 code
= BFD_RELOC_386_GOTPC
;
9351 code
= BFD_RELOC_X86_64_GOTPC32
;
9353 if ((code
== BFD_RELOC_64
|| code
== BFD_RELOC_64_PCREL
)
9355 && fixp
->fx_addsy
== GOT_symbol
)
9357 code
= BFD_RELOC_X86_64_GOTPC64
;
9360 rel
= (arelent
*) xmalloc (sizeof (arelent
));
9361 rel
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
9362 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
9364 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
9366 if (!use_rela_relocations
)
9368 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
9369 vtable entry to be used in the relocation's section offset. */
9370 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
9371 rel
->address
= fixp
->fx_offset
;
9372 #if defined (OBJ_COFF) && defined (TE_PE)
9373 else if (fixp
->fx_addsy
&& S_IS_WEAK (fixp
->fx_addsy
))
9374 rel
->addend
= fixp
->fx_addnumber
- (S_GET_VALUE (fixp
->fx_addsy
) * 2);
9379 /* Use the rela in 64bit mode. */
9382 if (disallow_64bit_reloc
)
9385 case BFD_RELOC_X86_64_DTPOFF64
:
9386 case BFD_RELOC_X86_64_TPOFF64
:
9387 case BFD_RELOC_64_PCREL
:
9388 case BFD_RELOC_X86_64_GOTOFF64
:
9389 case BFD_RELOC_X86_64_GOT64
:
9390 case BFD_RELOC_X86_64_GOTPCREL64
:
9391 case BFD_RELOC_X86_64_GOTPC64
:
9392 case BFD_RELOC_X86_64_GOTPLT64
:
9393 case BFD_RELOC_X86_64_PLTOFF64
:
9394 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
9395 _("cannot represent relocation type %s in x32 mode"),
9396 bfd_get_reloc_code_name (code
));
9402 if (!fixp
->fx_pcrel
)
9403 rel
->addend
= fixp
->fx_offset
;
9407 case BFD_RELOC_X86_64_PLT32
:
9408 case BFD_RELOC_X86_64_GOT32
:
9409 case BFD_RELOC_X86_64_GOTPCREL
:
9410 case BFD_RELOC_X86_64_TLSGD
:
9411 case BFD_RELOC_X86_64_TLSLD
:
9412 case BFD_RELOC_X86_64_GOTTPOFF
:
9413 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
9414 case BFD_RELOC_X86_64_TLSDESC_CALL
:
9415 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
9418 rel
->addend
= (section
->vma
9420 + fixp
->fx_addnumber
9421 + md_pcrel_from (fixp
));
9426 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
9427 if (rel
->howto
== NULL
)
9429 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
9430 _("cannot represent relocation type %s"),
9431 bfd_get_reloc_code_name (code
));
9432 /* Set howto to a garbage value so that we can keep going. */
9433 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
9434 gas_assert (rel
->howto
!= NULL
);
9440 #include "tc-i386-intel.c"
9443 tc_x86_parse_to_dw2regnum (expressionS
*exp
)
9445 int saved_naked_reg
;
9446 char saved_register_dot
;
9448 saved_naked_reg
= allow_naked_reg
;
9449 allow_naked_reg
= 1;
9450 saved_register_dot
= register_chars
['.'];
9451 register_chars
['.'] = '.';
9452 allow_pseudo_reg
= 1;
9453 expression_and_evaluate (exp
);
9454 allow_pseudo_reg
= 0;
9455 register_chars
['.'] = saved_register_dot
;
9456 allow_naked_reg
= saved_naked_reg
;
9458 if (exp
->X_op
== O_register
&& exp
->X_add_number
>= 0)
9460 if ((addressT
) exp
->X_add_number
< i386_regtab_size
)
9462 exp
->X_op
= O_constant
;
9463 exp
->X_add_number
= i386_regtab
[exp
->X_add_number
]
9464 .dw2_regnum
[flag_code
>> 1];
9467 exp
->X_op
= O_illegal
;
9472 tc_x86_frame_initial_instructions (void)
9474 static unsigned int sp_regno
[2];
9476 if (!sp_regno
[flag_code
>> 1])
9478 char *saved_input
= input_line_pointer
;
9479 char sp
[][4] = {"esp", "rsp"};
9482 input_line_pointer
= sp
[flag_code
>> 1];
9483 tc_x86_parse_to_dw2regnum (&exp
);
9484 gas_assert (exp
.X_op
== O_constant
);
9485 sp_regno
[flag_code
>> 1] = exp
.X_add_number
;
9486 input_line_pointer
= saved_input
;
9489 cfi_add_CFA_def_cfa (sp_regno
[flag_code
>> 1], -x86_cie_data_alignment
);
9490 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
9494 x86_dwarf2_addr_size (void)
9496 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
9497 if (x86_elf_abi
== X86_64_X32_ABI
)
9500 return bfd_arch_bits_per_address (stdoutput
) / 8;
9504 i386_elf_section_type (const char *str
, size_t len
)
9506 if (flag_code
== CODE_64BIT
9507 && len
== sizeof ("unwind") - 1
9508 && strncmp (str
, "unwind", 6) == 0)
9509 return SHT_X86_64_UNWIND
;
9516 i386_solaris_fix_up_eh_frame (segT sec
)
9518 if (flag_code
== CODE_64BIT
)
9519 elf_section_type (sec
) = SHT_X86_64_UNWIND
;
9525 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
9529 exp
.X_op
= O_secrel
;
9530 exp
.X_add_symbol
= symbol
;
9531 exp
.X_add_number
= 0;
9532 emit_expr (&exp
, size
);
9536 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9537 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
9540 x86_64_section_letter (int letter
, char **ptr_msg
)
9542 if (flag_code
== CODE_64BIT
)
9545 return SHF_X86_64_LARGE
;
9547 *ptr_msg
= _("bad .section directive: want a,l,w,x,M,S,G,T in string");
9550 *ptr_msg
= _("bad .section directive: want a,w,x,M,S,G,T in string");
9555 x86_64_section_word (char *str
, size_t len
)
9557 if (len
== 5 && flag_code
== CODE_64BIT
&& CONST_STRNEQ (str
, "large"))
9558 return SHF_X86_64_LARGE
;
9564 handle_large_common (int small ATTRIBUTE_UNUSED
)
9566 if (flag_code
!= CODE_64BIT
)
9568 s_comm_internal (0, elf_common_parse
);
9569 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
9573 static segT lbss_section
;
9574 asection
*saved_com_section_ptr
= elf_com_section_ptr
;
9575 asection
*saved_bss_section
= bss_section
;
9577 if (lbss_section
== NULL
)
9579 flagword applicable
;
9581 subsegT subseg
= now_subseg
;
9583 /* The .lbss section is for local .largecomm symbols. */
9584 lbss_section
= subseg_new (".lbss", 0);
9585 applicable
= bfd_applicable_section_flags (stdoutput
);
9586 bfd_set_section_flags (stdoutput
, lbss_section
,
9587 applicable
& SEC_ALLOC
);
9588 seg_info (lbss_section
)->bss
= 1;
9590 subseg_set (seg
, subseg
);
9593 elf_com_section_ptr
= &_bfd_elf_large_com_section
;
9594 bss_section
= lbss_section
;
9596 s_comm_internal (0, elf_common_parse
);
9598 elf_com_section_ptr
= saved_com_section_ptr
;
9599 bss_section
= saved_bss_section
;
9602 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */