1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright (C) 1989-2020 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 /* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
23 x86_64 support by Jan Hubicka (jh@suse.cz)
24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
29 #include "safe-ctype.h"
31 #include "dwarf2dbg.h"
32 #include "dw2gencfi.h"
33 #include "elf/x86-64.h"
34 #include "opcodes/i386-init.h"
39 #ifdef HAVE_SYS_PARAM_H
40 #include <sys/param.h>
43 #define INT_MAX (int) (((unsigned) (-1)) >> 1)
47 #ifndef INFER_ADDR_PREFIX
48 #define INFER_ADDR_PREFIX 1
52 #define DEFAULT_ARCH "i386"
57 #define INLINE __inline__
63 /* Prefixes will be emitted in the order defined below.
64 WAIT_PREFIX must be the first prefix since FWAIT is really is an
65 instruction, and so must come before any prefixes.
66 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
67 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
73 #define HLE_PREFIX REP_PREFIX
74 #define BND_PREFIX REP_PREFIX
76 #define REX_PREFIX 6 /* must come last. */
77 #define MAX_PREFIXES 7 /* max prefixes per opcode */
79 /* we define the syntax here (modulo base,index,scale syntax) */
80 #define REGISTER_PREFIX '%'
81 #define IMMEDIATE_PREFIX '$'
82 #define ABSOLUTE_PREFIX '*'
84 /* these are the instruction mnemonic suffixes in AT&T syntax or
85 memory operand size in Intel syntax. */
86 #define WORD_MNEM_SUFFIX 'w'
87 #define BYTE_MNEM_SUFFIX 'b'
88 #define SHORT_MNEM_SUFFIX 's'
89 #define LONG_MNEM_SUFFIX 'l'
90 #define QWORD_MNEM_SUFFIX 'q'
91 /* Intel Syntax. Use a non-ascii letter since since it never appears
93 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
95 #define END_OF_INSN '\0'
97 /* This matches the C -> StaticRounding alias in the opcode table. */
98 #define commutative staticrounding
101 'templates' is for grouping together 'template' structures for opcodes
102 of the same name. This is only used for storing the insns in the grand
103 ole hash table of insns.
104 The templates themselves start at START and range up to (but not including)
109 const insn_template
*start
;
110 const insn_template
*end
;
114 /* 386 operand encoding bytes: see 386 book for details of this. */
117 unsigned int regmem
; /* codes register or memory operand */
118 unsigned int reg
; /* codes register operand (or extended opcode) */
119 unsigned int mode
; /* how to interpret regmem & reg */
123 /* x86-64 extension prefix. */
124 typedef int rex_byte
;
126 /* 386 opcode byte to code indirect addressing. */
135 /* x86 arch names, types and features */
138 const char *name
; /* arch name */
139 unsigned int len
; /* arch string length */
140 enum processor_type type
; /* arch type */
141 i386_cpu_flags flags
; /* cpu feature flags */
142 unsigned int skip
; /* show_arch should skip this. */
146 /* Used to turn off indicated flags. */
149 const char *name
; /* arch name */
150 unsigned int len
; /* arch string length */
151 i386_cpu_flags flags
; /* cpu feature flags */
155 static void update_code_flag (int, int);
156 static void set_code_flag (int);
157 static void set_16bit_gcc_code_flag (int);
158 static void set_intel_syntax (int);
159 static void set_intel_mnemonic (int);
160 static void set_allow_index_reg (int);
161 static void set_check (int);
162 static void set_cpu_arch (int);
164 static void pe_directive_secrel (int);
166 static void signed_cons (int);
167 static char *output_invalid (int c
);
168 static int i386_finalize_immediate (segT
, expressionS
*, i386_operand_type
,
170 static int i386_finalize_displacement (segT
, expressionS
*, i386_operand_type
,
172 static int i386_att_operand (char *);
173 static int i386_intel_operand (char *, int);
174 static int i386_intel_simplify (expressionS
*);
175 static int i386_intel_parse_name (const char *, expressionS
*);
176 static const reg_entry
*parse_register (char *, char **);
177 static char *parse_insn (char *, char *);
178 static char *parse_operands (char *, const char *);
179 static void swap_operands (void);
180 static void swap_2_operands (int, int);
181 static enum flag_code
i386_addressing_mode (void);
182 static void optimize_imm (void);
183 static void optimize_disp (void);
184 static const insn_template
*match_template (char);
185 static int check_string (void);
186 static int process_suffix (void);
187 static int check_byte_reg (void);
188 static int check_long_reg (void);
189 static int check_qword_reg (void);
190 static int check_word_reg (void);
191 static int finalize_imm (void);
192 static int process_operands (void);
193 static const seg_entry
*build_modrm_byte (void);
194 static void output_insn (void);
195 static void output_imm (fragS
*, offsetT
);
196 static void output_disp (fragS
*, offsetT
);
198 static void s_bss (int);
200 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
201 static void handle_large_common (int small ATTRIBUTE_UNUSED
);
203 /* GNU_PROPERTY_X86_ISA_1_USED. */
204 static unsigned int x86_isa_1_used
;
205 /* GNU_PROPERTY_X86_FEATURE_2_USED. */
206 static unsigned int x86_feature_2_used
;
207 /* Generate x86 used ISA and feature properties. */
208 static unsigned int x86_used_note
= DEFAULT_X86_USED_NOTE
;
211 static const char *default_arch
= DEFAULT_ARCH
;
213 /* This struct describes rounding control and SAE in the instruction. */
227 static struct RC_Operation rc_op
;
229 /* The struct describes masking, applied to OPERAND in the instruction.
230 MASK is a pointer to the corresponding mask register. ZEROING tells
231 whether merging or zeroing mask is used. */
232 struct Mask_Operation
234 const reg_entry
*mask
;
235 unsigned int zeroing
;
236 /* The operand where this operation is associated. */
240 static struct Mask_Operation mask_op
;
242 /* The struct describes broadcasting, applied to OPERAND. FACTOR is
244 struct Broadcast_Operation
246 /* Type of broadcast: {1to2}, {1to4}, {1to8}, or {1to16}. */
249 /* Index of broadcasted operand. */
252 /* Number of bytes to broadcast. */
256 static struct Broadcast_Operation broadcast_op
;
261 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
262 unsigned char bytes
[4];
264 /* Destination or source register specifier. */
265 const reg_entry
*register_specifier
;
268 /* 'md_assemble ()' gathers together information and puts it into a
275 const reg_entry
*regs
;
280 operand_size_mismatch
,
281 operand_type_mismatch
,
282 register_type_mismatch
,
283 number_of_operands_mismatch
,
284 invalid_instruction_suffix
,
286 unsupported_with_intel_mnemonic
,
289 invalid_vsib_address
,
290 invalid_vector_register_set
,
291 unsupported_vector_index_register
,
292 unsupported_broadcast
,
295 mask_not_on_destination
,
298 rc_sae_operand_not_last_imm
,
299 invalid_register_operand
,
304 /* TM holds the template for the insn were currently assembling. */
307 /* SUFFIX holds the instruction size suffix for byte, word, dword
308 or qword, if given. */
311 /* OPERANDS gives the number of given operands. */
312 unsigned int operands
;
314 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
315 of given register, displacement, memory operands and immediate
317 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
319 /* TYPES [i] is the type (see above #defines) which tells us how to
320 use OP[i] for the corresponding operand. */
321 i386_operand_type types
[MAX_OPERANDS
];
323 /* Displacement expression, immediate expression, or register for each
325 union i386_op op
[MAX_OPERANDS
];
327 /* Flags for operands. */
328 unsigned int flags
[MAX_OPERANDS
];
329 #define Operand_PCrel 1
330 #define Operand_Mem 2
332 /* Relocation type for operand */
333 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
335 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
336 the base index byte below. */
337 const reg_entry
*base_reg
;
338 const reg_entry
*index_reg
;
339 unsigned int log2_scale_factor
;
341 /* SEG gives the seg_entries of this insn. They are zero unless
342 explicit segment overrides are given. */
343 const seg_entry
*seg
[2];
345 /* Copied first memory operand string, for re-checking. */
348 /* PREFIX holds all the given prefix opcodes (usually null).
349 PREFIXES is the number of prefix opcodes. */
350 unsigned int prefixes
;
351 unsigned char prefix
[MAX_PREFIXES
];
353 /* Register is in low 3 bits of opcode. */
354 bfd_boolean short_form
;
356 /* The operand to a branch insn indicates an absolute branch. */
357 bfd_boolean jumpabsolute
;
359 /* Has MMX register operands. */
360 bfd_boolean has_regmmx
;
362 /* Has XMM register operands. */
363 bfd_boolean has_regxmm
;
365 /* Has YMM register operands. */
366 bfd_boolean has_regymm
;
368 /* Has ZMM register operands. */
369 bfd_boolean has_regzmm
;
371 /* Has GOTPC or TLS relocation. */
372 bfd_boolean has_gotpc_tls_reloc
;
374 /* RM and SIB are the modrm byte and the sib byte where the
375 addressing modes of this insn are encoded. */
382 /* Masking attributes. */
383 struct Mask_Operation
*mask
;
385 /* Rounding control and SAE attributes. */
386 struct RC_Operation
*rounding
;
388 /* Broadcasting attributes. */
389 struct Broadcast_Operation
*broadcast
;
391 /* Compressed disp8*N attribute. */
392 unsigned int memshift
;
394 /* Prefer load or store in encoding. */
397 dir_encoding_default
= 0,
403 /* Prefer 8bit or 32bit displacement in encoding. */
406 disp_encoding_default
= 0,
411 /* Prefer the REX byte in encoding. */
412 bfd_boolean rex_encoding
;
414 /* Disable instruction size optimization. */
415 bfd_boolean no_optimize
;
417 /* How to encode vector instructions. */
420 vex_encoding_default
= 0,
427 const char *rep_prefix
;
430 const char *hle_prefix
;
432 /* Have BND prefix. */
433 const char *bnd_prefix
;
435 /* Have NOTRACK prefix. */
436 const char *notrack_prefix
;
439 enum i386_error error
;
442 typedef struct _i386_insn i386_insn
;
444 /* Link RC type with corresponding string, that'll be looked for in
453 static const struct RC_name RC_NamesTable
[] =
455 { rne
, STRING_COMMA_LEN ("rn-sae") },
456 { rd
, STRING_COMMA_LEN ("rd-sae") },
457 { ru
, STRING_COMMA_LEN ("ru-sae") },
458 { rz
, STRING_COMMA_LEN ("rz-sae") },
459 { saeonly
, STRING_COMMA_LEN ("sae") },
462 /* List of chars besides those in app.c:symbol_chars that can start an
463 operand. Used to prevent the scrubber eating vital white-space. */
464 const char extra_symbol_chars
[] = "*%-([{}"
473 #if (defined (TE_I386AIX) \
474 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
475 && !defined (TE_GNU) \
476 && !defined (TE_LINUX) \
477 && !defined (TE_NACL) \
478 && !defined (TE_FreeBSD) \
479 && !defined (TE_DragonFly) \
480 && !defined (TE_NetBSD)))
481 /* This array holds the chars that always start a comment. If the
482 pre-processor is disabled, these aren't very useful. The option
483 --divide will remove '/' from this list. */
484 const char *i386_comment_chars
= "#/";
485 #define SVR4_COMMENT_CHARS 1
486 #define PREFIX_SEPARATOR '\\'
489 const char *i386_comment_chars
= "#";
490 #define PREFIX_SEPARATOR '/'
493 /* This array holds the chars that only start a comment at the beginning of
494 a line. If the line seems to have the form '# 123 filename'
495 .line and .file directives will appear in the pre-processed output.
496 Note that input_file.c hand checks for '#' at the beginning of the
497 first line of the input file. This is because the compiler outputs
498 #NO_APP at the beginning of its output.
499 Also note that comments started like this one will always work if
500 '/' isn't otherwise defined. */
501 const char line_comment_chars
[] = "#/";
503 const char line_separator_chars
[] = ";";
505 /* Chars that can be used to separate mant from exp in floating point
507 const char EXP_CHARS
[] = "eE";
509 /* Chars that mean this number is a floating point constant
512 const char FLT_CHARS
[] = "fFdDxX";
514 /* Tables for lexical analysis. */
515 static char mnemonic_chars
[256];
516 static char register_chars
[256];
517 static char operand_chars
[256];
518 static char identifier_chars
[256];
519 static char digit_chars
[256];
521 /* Lexical macros. */
522 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
523 #define is_operand_char(x) (operand_chars[(unsigned char) x])
524 #define is_register_char(x) (register_chars[(unsigned char) x])
525 #define is_space_char(x) ((x) == ' ')
526 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
527 #define is_digit_char(x) (digit_chars[(unsigned char) x])
529 /* All non-digit non-letter characters that may occur in an operand. */
530 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
532 /* md_assemble() always leaves the strings it's passed unaltered. To
533 effect this we maintain a stack of saved characters that we've smashed
534 with '\0's (indicating end of strings for various sub-fields of the
535 assembler instruction). */
536 static char save_stack
[32];
537 static char *save_stack_p
;
538 #define END_STRING_AND_SAVE(s) \
539 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
540 #define RESTORE_END_STRING(s) \
541 do { *(s) = *--save_stack_p; } while (0)
543 /* The instruction we're assembling. */
546 /* Possible templates for current insn. */
547 static const templates
*current_templates
;
549 /* Per instruction expressionS buffers: max displacements & immediates. */
550 static expressionS disp_expressions
[MAX_MEMORY_OPERANDS
];
551 static expressionS im_expressions
[MAX_IMMEDIATE_OPERANDS
];
553 /* Current operand we are working on. */
554 static int this_operand
= -1;
556 /* We support four different modes. FLAG_CODE variable is used to distinguish
564 static enum flag_code flag_code
;
565 static unsigned int object_64bit
;
566 static unsigned int disallow_64bit_reloc
;
567 static int use_rela_relocations
= 0;
568 /* __tls_get_addr/___tls_get_addr symbol for TLS. */
569 static const char *tls_get_addr
;
571 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
572 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
573 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
575 /* The ELF ABI to use. */
583 static enum x86_elf_abi x86_elf_abi
= I386_ABI
;
586 #if defined (TE_PE) || defined (TE_PEP)
587 /* Use big object file format. */
588 static int use_big_obj
= 0;
591 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
592 /* 1 if generating code for a shared library. */
593 static int shared
= 0;
596 /* 1 for intel syntax,
598 static int intel_syntax
= 0;
600 static enum x86_64_isa
602 amd64
= 1, /* AMD64 ISA. */
603 intel64
/* Intel64 ISA. */
606 /* 1 for intel mnemonic,
607 0 if att mnemonic. */
608 static int intel_mnemonic
= !SYSV386_COMPAT
;
610 /* 1 if pseudo registers are permitted. */
611 static int allow_pseudo_reg
= 0;
613 /* 1 if register prefix % not required. */
614 static int allow_naked_reg
= 0;
616 /* 1 if the assembler should add BND prefix for all control-transferring
617 instructions supporting it, even if this prefix wasn't specified
619 static int add_bnd_prefix
= 0;
621 /* 1 if pseudo index register, eiz/riz, is allowed . */
622 static int allow_index_reg
= 0;
624 /* 1 if the assembler should ignore LOCK prefix, even if it was
625 specified explicitly. */
626 static int omit_lock_prefix
= 0;
628 /* 1 if the assembler should encode lfence, mfence, and sfence as
629 "lock addl $0, (%{re}sp)". */
630 static int avoid_fence
= 0;
632 /* Type of the previous instruction. */
647 /* 1 if the assembler should generate relax relocations. */
649 static int generate_relax_relocations
650 = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS
;
652 static enum check_kind
658 sse_check
, operand_check
= check_warning
;
660 /* Non-zero if branches should be aligned within power of 2 boundary. */
661 static int align_branch_power
= 0;
663 /* Types of branches to align. */
664 enum align_branch_kind
666 align_branch_none
= 0,
667 align_branch_jcc
= 1,
668 align_branch_fused
= 2,
669 align_branch_jmp
= 3,
670 align_branch_call
= 4,
671 align_branch_indirect
= 5,
675 /* Type bits of branches to align. */
676 enum align_branch_bit
678 align_branch_jcc_bit
= 1 << align_branch_jcc
,
679 align_branch_fused_bit
= 1 << align_branch_fused
,
680 align_branch_jmp_bit
= 1 << align_branch_jmp
,
681 align_branch_call_bit
= 1 << align_branch_call
,
682 align_branch_indirect_bit
= 1 << align_branch_indirect
,
683 align_branch_ret_bit
= 1 << align_branch_ret
686 static unsigned int align_branch
= (align_branch_jcc_bit
687 | align_branch_fused_bit
688 | align_branch_jmp_bit
);
690 /* The maximum padding size for fused jcc. CMP like instruction can
691 be 9 bytes and jcc can be 6 bytes. Leave room just in case for
693 #define MAX_FUSED_JCC_PADDING_SIZE 20
695 /* The maximum number of prefixes added for an instruction. */
696 static unsigned int align_branch_prefix_size
= 5;
699 1. Clear the REX_W bit with register operand if possible.
700 2. Above plus use 128bit vector instruction to clear the full vector
703 static int optimize
= 0;
706 1. Clear the REX_W bit with register operand if possible.
707 2. Above plus use 128bit vector instruction to clear the full vector
709 3. Above plus optimize "test{q,l,w} $imm8,%r{64,32,16}" to
712 static int optimize_for_space
= 0;
714 /* Register prefix used for error message. */
715 static const char *register_prefix
= "%";
717 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
718 leave, push, and pop instructions so that gcc has the same stack
719 frame as in 32 bit mode. */
720 static char stackop_size
= '\0';
722 /* Non-zero to optimize code alignment. */
723 int optimize_align_code
= 1;
725 /* Non-zero to quieten some warnings. */
726 static int quiet_warnings
= 0;
729 static const char *cpu_arch_name
= NULL
;
730 static char *cpu_sub_arch_name
= NULL
;
732 /* CPU feature flags. */
733 static i386_cpu_flags cpu_arch_flags
= CPU_UNKNOWN_FLAGS
;
735 /* If we have selected a cpu we are generating instructions for. */
736 static int cpu_arch_tune_set
= 0;
738 /* Cpu we are generating instructions for. */
739 enum processor_type cpu_arch_tune
= PROCESSOR_UNKNOWN
;
741 /* CPU feature flags of cpu we are generating instructions for. */
742 static i386_cpu_flags cpu_arch_tune_flags
;
744 /* CPU instruction set architecture used. */
745 enum processor_type cpu_arch_isa
= PROCESSOR_UNKNOWN
;
747 /* CPU feature flags of instruction set architecture used. */
748 i386_cpu_flags cpu_arch_isa_flags
;
750 /* If set, conditional jumps are not automatically promoted to handle
751 larger than a byte offset. */
752 static unsigned int no_cond_jump_promotion
= 0;
754 /* Encode SSE instructions with VEX prefix. */
755 static unsigned int sse2avx
;
757 /* Encode scalar AVX instructions with specific vector length. */
764 /* Encode VEX WIG instructions with specific vex.w. */
771 /* Encode scalar EVEX LIG instructions with specific vector length. */
779 /* Encode EVEX WIG instructions with specific evex.w. */
786 /* Value to encode in EVEX RC bits, for SAE-only instructions. */
787 static enum rc_type evexrcig
= rne
;
789 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
790 static symbolS
*GOT_symbol
;
792 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
793 unsigned int x86_dwarf2_return_column
;
795 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
796 int x86_cie_data_alignment
;
798 /* Interface to relax_segment.
799 There are 3 major relax states for 386 jump insns because the
800 different types of jumps add different sizes to frags when we're
801 figuring out what sort of jump to choose to reach a given label.
803 BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING are used to align
804 branches which are handled by md_estimate_size_before_relax() and
805 i386_generic_table_relax_frag(). */
808 #define UNCOND_JUMP 0
810 #define COND_JUMP86 2
811 #define BRANCH_PADDING 3
812 #define BRANCH_PREFIX 4
813 #define FUSED_JCC_PADDING 5
818 #define SMALL16 (SMALL | CODE16)
820 #define BIG16 (BIG | CODE16)
824 #define INLINE __inline__
830 #define ENCODE_RELAX_STATE(type, size) \
831 ((relax_substateT) (((type) << 2) | (size)))
832 #define TYPE_FROM_RELAX_STATE(s) \
834 #define DISP_SIZE_FROM_RELAX_STATE(s) \
835 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
837 /* This table is used by relax_frag to promote short jumps to long
838 ones where necessary. SMALL (short) jumps may be promoted to BIG
839 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
840 don't allow a short jump in a 32 bit code segment to be promoted to
841 a 16 bit offset jump because it's slower (requires data size
842 prefix), and doesn't work, unless the destination is in the bottom
843 64k of the code segment (The top 16 bits of eip are zeroed). */
845 const relax_typeS md_relax_table
[] =
848 1) most positive reach of this state,
849 2) most negative reach of this state,
850 3) how many bytes this mode will have in the variable part of the frag
851 4) which index into the table to try if we can't fit into this one. */
853 /* UNCOND_JUMP states. */
854 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
855 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
856 /* dword jmp adds 4 bytes to frag:
857 0 extra opcode bytes, 4 displacement bytes. */
859 /* word jmp adds 2 byte2 to frag:
860 0 extra opcode bytes, 2 displacement bytes. */
863 /* COND_JUMP states. */
864 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
865 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
866 /* dword conditionals adds 5 bytes to frag:
867 1 extra opcode byte, 4 displacement bytes. */
869 /* word conditionals add 3 bytes to frag:
870 1 extra opcode byte, 2 displacement bytes. */
873 /* COND_JUMP86 states. */
874 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
875 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
876 /* dword conditionals adds 5 bytes to frag:
877 1 extra opcode byte, 4 displacement bytes. */
879 /* word conditionals add 4 bytes to frag:
880 1 displacement byte and a 3 byte long branch insn. */
884 static const arch_entry cpu_arch
[] =
886 /* Do not replace the first two entries - i386_target_format()
887 relies on them being there in this order. */
888 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32
,
889 CPU_GENERIC32_FLAGS
, 0 },
890 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64
,
891 CPU_GENERIC64_FLAGS
, 0 },
892 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN
,
894 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN
,
896 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN
,
898 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386
,
900 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486
,
902 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM
,
904 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO
,
906 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM
,
908 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO
,
909 CPU_PENTIUMPRO_FLAGS
, 0 },
910 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO
,
912 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO
,
914 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4
,
916 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA
,
918 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA
,
919 CPU_NOCONA_FLAGS
, 0 },
920 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE
,
922 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE
,
924 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2
,
925 CPU_CORE2_FLAGS
, 1 },
926 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2
,
927 CPU_CORE2_FLAGS
, 0 },
928 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7
,
929 CPU_COREI7_FLAGS
, 0 },
930 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM
,
932 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM
,
934 { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU
,
935 CPU_IAMCU_FLAGS
, 0 },
936 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6
,
938 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6
,
940 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON
,
941 CPU_ATHLON_FLAGS
, 0 },
942 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8
,
944 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8
,
946 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8
,
948 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10
,
949 CPU_AMDFAM10_FLAGS
, 0 },
950 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD
,
951 CPU_BDVER1_FLAGS
, 0 },
952 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD
,
953 CPU_BDVER2_FLAGS
, 0 },
954 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD
,
955 CPU_BDVER3_FLAGS
, 0 },
956 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD
,
957 CPU_BDVER4_FLAGS
, 0 },
958 { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER
,
959 CPU_ZNVER1_FLAGS
, 0 },
960 { STRING_COMMA_LEN ("znver2"), PROCESSOR_ZNVER
,
961 CPU_ZNVER2_FLAGS
, 0 },
962 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT
,
963 CPU_BTVER1_FLAGS
, 0 },
964 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT
,
965 CPU_BTVER2_FLAGS
, 0 },
966 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN
,
968 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN
,
970 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN
,
972 { STRING_COMMA_LEN (".687"), PROCESSOR_UNKNOWN
,
974 { STRING_COMMA_LEN (".cmov"), PROCESSOR_UNKNOWN
,
976 { STRING_COMMA_LEN (".fxsr"), PROCESSOR_UNKNOWN
,
978 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN
,
980 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN
,
982 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN
,
984 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN
,
986 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN
,
987 CPU_SSSE3_FLAGS
, 0 },
988 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN
,
989 CPU_SSE4_1_FLAGS
, 0 },
990 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN
,
991 CPU_SSE4_2_FLAGS
, 0 },
992 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN
,
993 CPU_SSE4_2_FLAGS
, 0 },
994 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN
,
996 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN
,
998 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN
,
999 CPU_AVX512F_FLAGS
, 0 },
1000 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN
,
1001 CPU_AVX512CD_FLAGS
, 0 },
1002 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN
,
1003 CPU_AVX512ER_FLAGS
, 0 },
1004 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN
,
1005 CPU_AVX512PF_FLAGS
, 0 },
1006 { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN
,
1007 CPU_AVX512DQ_FLAGS
, 0 },
1008 { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN
,
1009 CPU_AVX512BW_FLAGS
, 0 },
1010 { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN
,
1011 CPU_AVX512VL_FLAGS
, 0 },
1012 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN
,
1014 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN
,
1015 CPU_VMFUNC_FLAGS
, 0 },
1016 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN
,
1018 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN
,
1019 CPU_XSAVE_FLAGS
, 0 },
1020 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN
,
1021 CPU_XSAVEOPT_FLAGS
, 0 },
1022 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN
,
1023 CPU_XSAVEC_FLAGS
, 0 },
1024 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN
,
1025 CPU_XSAVES_FLAGS
, 0 },
1026 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN
,
1028 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN
,
1029 CPU_PCLMUL_FLAGS
, 0 },
1030 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN
,
1031 CPU_PCLMUL_FLAGS
, 1 },
1032 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN
,
1033 CPU_FSGSBASE_FLAGS
, 0 },
1034 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN
,
1035 CPU_RDRND_FLAGS
, 0 },
1036 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN
,
1037 CPU_F16C_FLAGS
, 0 },
1038 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN
,
1039 CPU_BMI2_FLAGS
, 0 },
1040 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN
,
1042 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN
,
1043 CPU_FMA4_FLAGS
, 0 },
1044 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN
,
1046 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN
,
1048 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN
,
1049 CPU_MOVBE_FLAGS
, 0 },
1050 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN
,
1051 CPU_CX16_FLAGS
, 0 },
1052 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN
,
1054 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN
,
1055 CPU_LZCNT_FLAGS
, 0 },
1056 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN
,
1058 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN
,
1060 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN
,
1061 CPU_INVPCID_FLAGS
, 0 },
1062 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN
,
1063 CPU_CLFLUSH_FLAGS
, 0 },
1064 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN
,
1066 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN
,
1067 CPU_SYSCALL_FLAGS
, 0 },
1068 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN
,
1069 CPU_RDTSCP_FLAGS
, 0 },
1070 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN
,
1071 CPU_3DNOW_FLAGS
, 0 },
1072 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN
,
1073 CPU_3DNOWA_FLAGS
, 0 },
1074 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN
,
1075 CPU_PADLOCK_FLAGS
, 0 },
1076 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN
,
1077 CPU_SVME_FLAGS
, 1 },
1078 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN
,
1079 CPU_SVME_FLAGS
, 0 },
1080 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN
,
1081 CPU_SSE4A_FLAGS
, 0 },
1082 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN
,
1084 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN
,
1086 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN
,
1088 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN
,
1090 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN
,
1091 CPU_RDSEED_FLAGS
, 0 },
1092 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN
,
1093 CPU_PRFCHW_FLAGS
, 0 },
1094 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN
,
1095 CPU_SMAP_FLAGS
, 0 },
1096 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN
,
1098 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN
,
1100 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN
,
1101 CPU_CLFLUSHOPT_FLAGS
, 0 },
1102 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN
,
1103 CPU_PREFETCHWT1_FLAGS
, 0 },
1104 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN
,
1106 { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN
,
1107 CPU_CLWB_FLAGS
, 0 },
1108 { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN
,
1109 CPU_AVX512IFMA_FLAGS
, 0 },
1110 { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN
,
1111 CPU_AVX512VBMI_FLAGS
, 0 },
1112 { STRING_COMMA_LEN (".avx512_4fmaps"), PROCESSOR_UNKNOWN
,
1113 CPU_AVX512_4FMAPS_FLAGS
, 0 },
1114 { STRING_COMMA_LEN (".avx512_4vnniw"), PROCESSOR_UNKNOWN
,
1115 CPU_AVX512_4VNNIW_FLAGS
, 0 },
1116 { STRING_COMMA_LEN (".avx512_vpopcntdq"), PROCESSOR_UNKNOWN
,
1117 CPU_AVX512_VPOPCNTDQ_FLAGS
, 0 },
1118 { STRING_COMMA_LEN (".avx512_vbmi2"), PROCESSOR_UNKNOWN
,
1119 CPU_AVX512_VBMI2_FLAGS
, 0 },
1120 { STRING_COMMA_LEN (".avx512_vnni"), PROCESSOR_UNKNOWN
,
1121 CPU_AVX512_VNNI_FLAGS
, 0 },
1122 { STRING_COMMA_LEN (".avx512_bitalg"), PROCESSOR_UNKNOWN
,
1123 CPU_AVX512_BITALG_FLAGS
, 0 },
1124 { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN
,
1125 CPU_CLZERO_FLAGS
, 0 },
1126 { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN
,
1127 CPU_MWAITX_FLAGS
, 0 },
1128 { STRING_COMMA_LEN (".ospke"), PROCESSOR_UNKNOWN
,
1129 CPU_OSPKE_FLAGS
, 0 },
1130 { STRING_COMMA_LEN (".rdpid"), PROCESSOR_UNKNOWN
,
1131 CPU_RDPID_FLAGS
, 0 },
1132 { STRING_COMMA_LEN (".ptwrite"), PROCESSOR_UNKNOWN
,
1133 CPU_PTWRITE_FLAGS
, 0 },
1134 { STRING_COMMA_LEN (".ibt"), PROCESSOR_UNKNOWN
,
1136 { STRING_COMMA_LEN (".shstk"), PROCESSOR_UNKNOWN
,
1137 CPU_SHSTK_FLAGS
, 0 },
1138 { STRING_COMMA_LEN (".gfni"), PROCESSOR_UNKNOWN
,
1139 CPU_GFNI_FLAGS
, 0 },
1140 { STRING_COMMA_LEN (".vaes"), PROCESSOR_UNKNOWN
,
1141 CPU_VAES_FLAGS
, 0 },
1142 { STRING_COMMA_LEN (".vpclmulqdq"), PROCESSOR_UNKNOWN
,
1143 CPU_VPCLMULQDQ_FLAGS
, 0 },
1144 { STRING_COMMA_LEN (".wbnoinvd"), PROCESSOR_UNKNOWN
,
1145 CPU_WBNOINVD_FLAGS
, 0 },
1146 { STRING_COMMA_LEN (".pconfig"), PROCESSOR_UNKNOWN
,
1147 CPU_PCONFIG_FLAGS
, 0 },
1148 { STRING_COMMA_LEN (".waitpkg"), PROCESSOR_UNKNOWN
,
1149 CPU_WAITPKG_FLAGS
, 0 },
1150 { STRING_COMMA_LEN (".cldemote"), PROCESSOR_UNKNOWN
,
1151 CPU_CLDEMOTE_FLAGS
, 0 },
1152 { STRING_COMMA_LEN (".movdiri"), PROCESSOR_UNKNOWN
,
1153 CPU_MOVDIRI_FLAGS
, 0 },
1154 { STRING_COMMA_LEN (".movdir64b"), PROCESSOR_UNKNOWN
,
1155 CPU_MOVDIR64B_FLAGS
, 0 },
1156 { STRING_COMMA_LEN (".avx512_bf16"), PROCESSOR_UNKNOWN
,
1157 CPU_AVX512_BF16_FLAGS
, 0 },
1158 { STRING_COMMA_LEN (".avx512_vp2intersect"), PROCESSOR_UNKNOWN
,
1159 CPU_AVX512_VP2INTERSECT_FLAGS
, 0 },
1160 { STRING_COMMA_LEN (".enqcmd"), PROCESSOR_UNKNOWN
,
1161 CPU_ENQCMD_FLAGS
, 0 },
1162 { STRING_COMMA_LEN (".rdpru"), PROCESSOR_UNKNOWN
,
1163 CPU_RDPRU_FLAGS
, 0 },
1164 { STRING_COMMA_LEN (".mcommit"), PROCESSOR_UNKNOWN
,
1165 CPU_MCOMMIT_FLAGS
, 0 },
1168 static const noarch_entry cpu_noarch
[] =
1170 { STRING_COMMA_LEN ("no87"), CPU_ANY_X87_FLAGS
},
1171 { STRING_COMMA_LEN ("no287"), CPU_ANY_287_FLAGS
},
1172 { STRING_COMMA_LEN ("no387"), CPU_ANY_387_FLAGS
},
1173 { STRING_COMMA_LEN ("no687"), CPU_ANY_687_FLAGS
},
1174 { STRING_COMMA_LEN ("nocmov"), CPU_ANY_CMOV_FLAGS
},
1175 { STRING_COMMA_LEN ("nofxsr"), CPU_ANY_FXSR_FLAGS
},
1176 { STRING_COMMA_LEN ("nommx"), CPU_ANY_MMX_FLAGS
},
1177 { STRING_COMMA_LEN ("nosse"), CPU_ANY_SSE_FLAGS
},
1178 { STRING_COMMA_LEN ("nosse2"), CPU_ANY_SSE2_FLAGS
},
1179 { STRING_COMMA_LEN ("nosse3"), CPU_ANY_SSE3_FLAGS
},
1180 { STRING_COMMA_LEN ("nossse3"), CPU_ANY_SSSE3_FLAGS
},
1181 { STRING_COMMA_LEN ("nosse4.1"), CPU_ANY_SSE4_1_FLAGS
},
1182 { STRING_COMMA_LEN ("nosse4.2"), CPU_ANY_SSE4_2_FLAGS
},
1183 { STRING_COMMA_LEN ("nosse4"), CPU_ANY_SSE4_FLAGS
},
1184 { STRING_COMMA_LEN ("noavx"), CPU_ANY_AVX_FLAGS
},
1185 { STRING_COMMA_LEN ("noavx2"), CPU_ANY_AVX2_FLAGS
},
1186 { STRING_COMMA_LEN ("noavx512f"), CPU_ANY_AVX512F_FLAGS
},
1187 { STRING_COMMA_LEN ("noavx512cd"), CPU_ANY_AVX512CD_FLAGS
},
1188 { STRING_COMMA_LEN ("noavx512er"), CPU_ANY_AVX512ER_FLAGS
},
1189 { STRING_COMMA_LEN ("noavx512pf"), CPU_ANY_AVX512PF_FLAGS
},
1190 { STRING_COMMA_LEN ("noavx512dq"), CPU_ANY_AVX512DQ_FLAGS
},
1191 { STRING_COMMA_LEN ("noavx512bw"), CPU_ANY_AVX512BW_FLAGS
},
1192 { STRING_COMMA_LEN ("noavx512vl"), CPU_ANY_AVX512VL_FLAGS
},
1193 { STRING_COMMA_LEN ("noavx512ifma"), CPU_ANY_AVX512IFMA_FLAGS
},
1194 { STRING_COMMA_LEN ("noavx512vbmi"), CPU_ANY_AVX512VBMI_FLAGS
},
1195 { STRING_COMMA_LEN ("noavx512_4fmaps"), CPU_ANY_AVX512_4FMAPS_FLAGS
},
1196 { STRING_COMMA_LEN ("noavx512_4vnniw"), CPU_ANY_AVX512_4VNNIW_FLAGS
},
1197 { STRING_COMMA_LEN ("noavx512_vpopcntdq"), CPU_ANY_AVX512_VPOPCNTDQ_FLAGS
},
1198 { STRING_COMMA_LEN ("noavx512_vbmi2"), CPU_ANY_AVX512_VBMI2_FLAGS
},
1199 { STRING_COMMA_LEN ("noavx512_vnni"), CPU_ANY_AVX512_VNNI_FLAGS
},
1200 { STRING_COMMA_LEN ("noavx512_bitalg"), CPU_ANY_AVX512_BITALG_FLAGS
},
1201 { STRING_COMMA_LEN ("noibt"), CPU_ANY_IBT_FLAGS
},
1202 { STRING_COMMA_LEN ("noshstk"), CPU_ANY_SHSTK_FLAGS
},
1203 { STRING_COMMA_LEN ("nomovdiri"), CPU_ANY_MOVDIRI_FLAGS
},
1204 { STRING_COMMA_LEN ("nomovdir64b"), CPU_ANY_MOVDIR64B_FLAGS
},
1205 { STRING_COMMA_LEN ("noavx512_bf16"), CPU_ANY_AVX512_BF16_FLAGS
},
1206 { STRING_COMMA_LEN ("noavx512_vp2intersect"), CPU_ANY_SHSTK_FLAGS
},
1207 { STRING_COMMA_LEN ("noenqcmd"), CPU_ANY_ENQCMD_FLAGS
},
1211 /* Like s_lcomm_internal in gas/read.c but the alignment string
1212 is allowed to be optional. */
1215 pe_lcomm_internal (int needs_align
, symbolS
*symbolP
, addressT size
)
1222 && *input_line_pointer
== ',')
1224 align
= parse_align (needs_align
- 1);
1226 if (align
== (addressT
) -1)
1241 bss_alloc (symbolP
, size
, align
);
1246 pe_lcomm (int needs_align
)
1248 s_comm_internal (needs_align
* 2, pe_lcomm_internal
);
1252 const pseudo_typeS md_pseudo_table
[] =
1254 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
1255 {"align", s_align_bytes
, 0},
1257 {"align", s_align_ptwo
, 0},
1259 {"arch", set_cpu_arch
, 0},
1263 {"lcomm", pe_lcomm
, 1},
1265 {"ffloat", float_cons
, 'f'},
1266 {"dfloat", float_cons
, 'd'},
1267 {"tfloat", float_cons
, 'x'},
1269 {"slong", signed_cons
, 4},
1270 {"noopt", s_ignore
, 0},
1271 {"optim", s_ignore
, 0},
1272 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
1273 {"code16", set_code_flag
, CODE_16BIT
},
1274 {"code32", set_code_flag
, CODE_32BIT
},
1276 {"code64", set_code_flag
, CODE_64BIT
},
1278 {"intel_syntax", set_intel_syntax
, 1},
1279 {"att_syntax", set_intel_syntax
, 0},
1280 {"intel_mnemonic", set_intel_mnemonic
, 1},
1281 {"att_mnemonic", set_intel_mnemonic
, 0},
1282 {"allow_index_reg", set_allow_index_reg
, 1},
1283 {"disallow_index_reg", set_allow_index_reg
, 0},
1284 {"sse_check", set_check
, 0},
1285 {"operand_check", set_check
, 1},
1286 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1287 {"largecomm", handle_large_common
, 0},
1289 {"file", dwarf2_directive_file
, 0},
1290 {"loc", dwarf2_directive_loc
, 0},
1291 {"loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0},
1294 {"secrel32", pe_directive_secrel
, 0},
1299 /* For interface with expression (). */
1300 extern char *input_line_pointer
;
1302 /* Hash table for instruction mnemonic lookup. */
1303 static struct hash_control
*op_hash
;
1305 /* Hash table for register lookup. */
1306 static struct hash_control
*reg_hash
;
1308 /* Various efficient no-op patterns for aligning code labels.
1309 Note: Don't try to assemble the instructions in the comments.
1310 0L and 0w are not legal. */
1311 static const unsigned char f32_1
[] =
1313 static const unsigned char f32_2
[] =
1314 {0x66,0x90}; /* xchg %ax,%ax */
1315 static const unsigned char f32_3
[] =
1316 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1317 static const unsigned char f32_4
[] =
1318 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1319 static const unsigned char f32_6
[] =
1320 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1321 static const unsigned char f32_7
[] =
1322 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1323 static const unsigned char f16_3
[] =
1324 {0x8d,0x74,0x00}; /* lea 0(%si),%si */
1325 static const unsigned char f16_4
[] =
1326 {0x8d,0xb4,0x00,0x00}; /* lea 0W(%si),%si */
1327 static const unsigned char jump_disp8
[] =
1328 {0xeb}; /* jmp disp8 */
1329 static const unsigned char jump32_disp32
[] =
1330 {0xe9}; /* jmp disp32 */
1331 static const unsigned char jump16_disp32
[] =
1332 {0x66,0xe9}; /* jmp disp32 */
1333 /* 32-bit NOPs patterns. */
1334 static const unsigned char *const f32_patt
[] = {
1335 f32_1
, f32_2
, f32_3
, f32_4
, NULL
, f32_6
, f32_7
1337 /* 16-bit NOPs patterns. */
1338 static const unsigned char *const f16_patt
[] = {
1339 f32_1
, f32_2
, f16_3
, f16_4
1341 /* nopl (%[re]ax) */
1342 static const unsigned char alt_3
[] =
1344 /* nopl 0(%[re]ax) */
1345 static const unsigned char alt_4
[] =
1346 {0x0f,0x1f,0x40,0x00};
1347 /* nopl 0(%[re]ax,%[re]ax,1) */
1348 static const unsigned char alt_5
[] =
1349 {0x0f,0x1f,0x44,0x00,0x00};
1350 /* nopw 0(%[re]ax,%[re]ax,1) */
1351 static const unsigned char alt_6
[] =
1352 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1353 /* nopl 0L(%[re]ax) */
1354 static const unsigned char alt_7
[] =
1355 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1356 /* nopl 0L(%[re]ax,%[re]ax,1) */
1357 static const unsigned char alt_8
[] =
1358 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1359 /* nopw 0L(%[re]ax,%[re]ax,1) */
1360 static const unsigned char alt_9
[] =
1361 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1362 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1363 static const unsigned char alt_10
[] =
1364 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1365 /* data16 nopw %cs:0L(%eax,%eax,1) */
1366 static const unsigned char alt_11
[] =
1367 {0x66,0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1368 /* 32-bit and 64-bit NOPs patterns. */
1369 static const unsigned char *const alt_patt
[] = {
1370 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
1371 alt_9
, alt_10
, alt_11
1374 /* Genenerate COUNT bytes of NOPs to WHERE from PATT with the maximum
1375 size of a single NOP instruction MAX_SINGLE_NOP_SIZE. */
1378 i386_output_nops (char *where
, const unsigned char *const *patt
,
1379 int count
, int max_single_nop_size
)
1382 /* Place the longer NOP first. */
1385 const unsigned char *nops
;
1387 if (max_single_nop_size
< 1)
1389 as_fatal (_("i386_output_nops called to generate nops of at most %d bytes!"),
1390 max_single_nop_size
);
1394 nops
= patt
[max_single_nop_size
- 1];
1396 /* Use the smaller one if the requsted one isn't available. */
1399 max_single_nop_size
--;
1400 nops
= patt
[max_single_nop_size
- 1];
1403 last
= count
% max_single_nop_size
;
1406 for (offset
= 0; offset
< count
; offset
+= max_single_nop_size
)
1407 memcpy (where
+ offset
, nops
, max_single_nop_size
);
1411 nops
= patt
[last
- 1];
1414 /* Use the smaller one plus one-byte NOP if the needed one
1417 nops
= patt
[last
- 1];
1418 memcpy (where
+ offset
, nops
, last
);
1419 where
[offset
+ last
] = *patt
[0];
1422 memcpy (where
+ offset
, nops
, last
);
1427 fits_in_imm7 (offsetT num
)
1429 return (num
& 0x7f) == num
;
1433 fits_in_imm31 (offsetT num
)
1435 return (num
& 0x7fffffff) == num
;
1438 /* Genenerate COUNT bytes of NOPs to WHERE with the maximum size of a
1439 single NOP instruction LIMIT. */
1442 i386_generate_nops (fragS
*fragP
, char *where
, offsetT count
, int limit
)
1444 const unsigned char *const *patt
= NULL
;
1445 int max_single_nop_size
;
1446 /* Maximum number of NOPs before switching to jump over NOPs. */
1447 int max_number_of_nops
;
1449 switch (fragP
->fr_type
)
1454 case rs_machine_dependent
:
1455 /* Allow NOP padding for jumps and calls. */
1456 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
1457 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
)
1464 /* We need to decide which NOP sequence to use for 32bit and
1465 64bit. When -mtune= is used:
1467 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1468 PROCESSOR_GENERIC32, f32_patt will be used.
1469 2. For the rest, alt_patt will be used.
1471 When -mtune= isn't used, alt_patt will be used if
1472 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
1475 When -march= or .arch is used, we can't use anything beyond
1476 cpu_arch_isa_flags. */
1478 if (flag_code
== CODE_16BIT
)
1481 max_single_nop_size
= sizeof (f16_patt
) / sizeof (f16_patt
[0]);
1482 /* Limit number of NOPs to 2 in 16-bit mode. */
1483 max_number_of_nops
= 2;
1487 if (fragP
->tc_frag_data
.isa
== PROCESSOR_UNKNOWN
)
1489 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1490 switch (cpu_arch_tune
)
1492 case PROCESSOR_UNKNOWN
:
1493 /* We use cpu_arch_isa_flags to check if we SHOULD
1494 optimize with nops. */
1495 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1500 case PROCESSOR_PENTIUM4
:
1501 case PROCESSOR_NOCONA
:
1502 case PROCESSOR_CORE
:
1503 case PROCESSOR_CORE2
:
1504 case PROCESSOR_COREI7
:
1505 case PROCESSOR_L1OM
:
1506 case PROCESSOR_K1OM
:
1507 case PROCESSOR_GENERIC64
:
1509 case PROCESSOR_ATHLON
:
1511 case PROCESSOR_AMDFAM10
:
1513 case PROCESSOR_ZNVER
:
1517 case PROCESSOR_I386
:
1518 case PROCESSOR_I486
:
1519 case PROCESSOR_PENTIUM
:
1520 case PROCESSOR_PENTIUMPRO
:
1521 case PROCESSOR_IAMCU
:
1522 case PROCESSOR_GENERIC32
:
1529 switch (fragP
->tc_frag_data
.tune
)
1531 case PROCESSOR_UNKNOWN
:
1532 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1533 PROCESSOR_UNKNOWN. */
1537 case PROCESSOR_I386
:
1538 case PROCESSOR_I486
:
1539 case PROCESSOR_PENTIUM
:
1540 case PROCESSOR_IAMCU
:
1542 case PROCESSOR_ATHLON
:
1544 case PROCESSOR_AMDFAM10
:
1546 case PROCESSOR_ZNVER
:
1548 case PROCESSOR_GENERIC32
:
1549 /* We use cpu_arch_isa_flags to check if we CAN optimize
1551 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1556 case PROCESSOR_PENTIUMPRO
:
1557 case PROCESSOR_PENTIUM4
:
1558 case PROCESSOR_NOCONA
:
1559 case PROCESSOR_CORE
:
1560 case PROCESSOR_CORE2
:
1561 case PROCESSOR_COREI7
:
1562 case PROCESSOR_L1OM
:
1563 case PROCESSOR_K1OM
:
1564 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1569 case PROCESSOR_GENERIC64
:
1575 if (patt
== f32_patt
)
1577 max_single_nop_size
= sizeof (f32_patt
) / sizeof (f32_patt
[0]);
1578 /* Limit number of NOPs to 2 for older processors. */
1579 max_number_of_nops
= 2;
1583 max_single_nop_size
= sizeof (alt_patt
) / sizeof (alt_patt
[0]);
1584 /* Limit number of NOPs to 7 for newer processors. */
1585 max_number_of_nops
= 7;
1590 limit
= max_single_nop_size
;
1592 if (fragP
->fr_type
== rs_fill_nop
)
1594 /* Output NOPs for .nop directive. */
1595 if (limit
> max_single_nop_size
)
1597 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
1598 _("invalid single nop size: %d "
1599 "(expect within [0, %d])"),
1600 limit
, max_single_nop_size
);
1604 else if (fragP
->fr_type
!= rs_machine_dependent
)
1605 fragP
->fr_var
= count
;
1607 if ((count
/ max_single_nop_size
) > max_number_of_nops
)
1609 /* Generate jump over NOPs. */
1610 offsetT disp
= count
- 2;
1611 if (fits_in_imm7 (disp
))
1613 /* Use "jmp disp8" if possible. */
1615 where
[0] = jump_disp8
[0];
1621 unsigned int size_of_jump
;
1623 if (flag_code
== CODE_16BIT
)
1625 where
[0] = jump16_disp32
[0];
1626 where
[1] = jump16_disp32
[1];
1631 where
[0] = jump32_disp32
[0];
1635 count
-= size_of_jump
+ 4;
1636 if (!fits_in_imm31 (count
))
1638 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
1639 _("jump over nop padding out of range"));
1643 md_number_to_chars (where
+ size_of_jump
, count
, 4);
1644 where
+= size_of_jump
+ 4;
1648 /* Generate multiple NOPs. */
1649 i386_output_nops (where
, patt
, count
, limit
);
1653 operand_type_all_zero (const union i386_operand_type
*x
)
1655 switch (ARRAY_SIZE(x
->array
))
1666 return !x
->array
[0];
1673 operand_type_set (union i386_operand_type
*x
, unsigned int v
)
1675 switch (ARRAY_SIZE(x
->array
))
1691 x
->bitfield
.class = ClassNone
;
1692 x
->bitfield
.instance
= InstanceNone
;
1696 operand_type_equal (const union i386_operand_type
*x
,
1697 const union i386_operand_type
*y
)
1699 switch (ARRAY_SIZE(x
->array
))
1702 if (x
->array
[2] != y
->array
[2])
1706 if (x
->array
[1] != y
->array
[1])
1710 return x
->array
[0] == y
->array
[0];
1718 cpu_flags_all_zero (const union i386_cpu_flags
*x
)
1720 switch (ARRAY_SIZE(x
->array
))
1735 return !x
->array
[0];
1742 cpu_flags_equal (const union i386_cpu_flags
*x
,
1743 const union i386_cpu_flags
*y
)
1745 switch (ARRAY_SIZE(x
->array
))
1748 if (x
->array
[3] != y
->array
[3])
1752 if (x
->array
[2] != y
->array
[2])
1756 if (x
->array
[1] != y
->array
[1])
1760 return x
->array
[0] == y
->array
[0];
1768 cpu_flags_check_cpu64 (i386_cpu_flags f
)
1770 return !((flag_code
== CODE_64BIT
&& f
.bitfield
.cpuno64
)
1771 || (flag_code
!= CODE_64BIT
&& f
.bitfield
.cpu64
));
1774 static INLINE i386_cpu_flags
1775 cpu_flags_and (i386_cpu_flags x
, i386_cpu_flags y
)
1777 switch (ARRAY_SIZE (x
.array
))
1780 x
.array
[3] &= y
.array
[3];
1783 x
.array
[2] &= y
.array
[2];
1786 x
.array
[1] &= y
.array
[1];
1789 x
.array
[0] &= y
.array
[0];
1797 static INLINE i386_cpu_flags
1798 cpu_flags_or (i386_cpu_flags x
, i386_cpu_flags y
)
1800 switch (ARRAY_SIZE (x
.array
))
1803 x
.array
[3] |= y
.array
[3];
1806 x
.array
[2] |= y
.array
[2];
1809 x
.array
[1] |= y
.array
[1];
1812 x
.array
[0] |= y
.array
[0];
1820 static INLINE i386_cpu_flags
1821 cpu_flags_and_not (i386_cpu_flags x
, i386_cpu_flags y
)
1823 switch (ARRAY_SIZE (x
.array
))
1826 x
.array
[3] &= ~y
.array
[3];
1829 x
.array
[2] &= ~y
.array
[2];
1832 x
.array
[1] &= ~y
.array
[1];
1835 x
.array
[0] &= ~y
.array
[0];
1843 static const i386_cpu_flags avx512
= CPU_ANY_AVX512F_FLAGS
;
1845 #define CPU_FLAGS_ARCH_MATCH 0x1
1846 #define CPU_FLAGS_64BIT_MATCH 0x2
1848 #define CPU_FLAGS_PERFECT_MATCH \
1849 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_64BIT_MATCH)
1851 /* Return CPU flags match bits. */
1854 cpu_flags_match (const insn_template
*t
)
1856 i386_cpu_flags x
= t
->cpu_flags
;
1857 int match
= cpu_flags_check_cpu64 (x
) ? CPU_FLAGS_64BIT_MATCH
: 0;
1859 x
.bitfield
.cpu64
= 0;
1860 x
.bitfield
.cpuno64
= 0;
1862 if (cpu_flags_all_zero (&x
))
1864 /* This instruction is available on all archs. */
1865 match
|= CPU_FLAGS_ARCH_MATCH
;
1869 /* This instruction is available only on some archs. */
1870 i386_cpu_flags cpu
= cpu_arch_flags
;
1872 /* AVX512VL is no standalone feature - match it and then strip it. */
1873 if (x
.bitfield
.cpuavx512vl
&& !cpu
.bitfield
.cpuavx512vl
)
1875 x
.bitfield
.cpuavx512vl
= 0;
1877 cpu
= cpu_flags_and (x
, cpu
);
1878 if (!cpu_flags_all_zero (&cpu
))
1880 if (x
.bitfield
.cpuavx
)
1882 /* We need to check a few extra flags with AVX. */
1883 if (cpu
.bitfield
.cpuavx
1884 && (!t
->opcode_modifier
.sse2avx
|| sse2avx
)
1885 && (!x
.bitfield
.cpuaes
|| cpu
.bitfield
.cpuaes
)
1886 && (!x
.bitfield
.cpugfni
|| cpu
.bitfield
.cpugfni
)
1887 && (!x
.bitfield
.cpupclmul
|| cpu
.bitfield
.cpupclmul
))
1888 match
|= CPU_FLAGS_ARCH_MATCH
;
1890 else if (x
.bitfield
.cpuavx512f
)
1892 /* We need to check a few extra flags with AVX512F. */
1893 if (cpu
.bitfield
.cpuavx512f
1894 && (!x
.bitfield
.cpugfni
|| cpu
.bitfield
.cpugfni
)
1895 && (!x
.bitfield
.cpuvaes
|| cpu
.bitfield
.cpuvaes
)
1896 && (!x
.bitfield
.cpuvpclmulqdq
|| cpu
.bitfield
.cpuvpclmulqdq
))
1897 match
|= CPU_FLAGS_ARCH_MATCH
;
1900 match
|= CPU_FLAGS_ARCH_MATCH
;
1906 static INLINE i386_operand_type
1907 operand_type_and (i386_operand_type x
, i386_operand_type y
)
1909 if (x
.bitfield
.class != y
.bitfield
.class)
1910 x
.bitfield
.class = ClassNone
;
1911 if (x
.bitfield
.instance
!= y
.bitfield
.instance
)
1912 x
.bitfield
.instance
= InstanceNone
;
1914 switch (ARRAY_SIZE (x
.array
))
1917 x
.array
[2] &= y
.array
[2];
1920 x
.array
[1] &= y
.array
[1];
1923 x
.array
[0] &= y
.array
[0];
1931 static INLINE i386_operand_type
1932 operand_type_and_not (i386_operand_type x
, i386_operand_type y
)
1934 gas_assert (y
.bitfield
.class == ClassNone
);
1935 gas_assert (y
.bitfield
.instance
== InstanceNone
);
1937 switch (ARRAY_SIZE (x
.array
))
1940 x
.array
[2] &= ~y
.array
[2];
1943 x
.array
[1] &= ~y
.array
[1];
1946 x
.array
[0] &= ~y
.array
[0];
1954 static INLINE i386_operand_type
1955 operand_type_or (i386_operand_type x
, i386_operand_type y
)
1957 gas_assert (x
.bitfield
.class == ClassNone
||
1958 y
.bitfield
.class == ClassNone
||
1959 x
.bitfield
.class == y
.bitfield
.class);
1960 gas_assert (x
.bitfield
.instance
== InstanceNone
||
1961 y
.bitfield
.instance
== InstanceNone
||
1962 x
.bitfield
.instance
== y
.bitfield
.instance
);
1964 switch (ARRAY_SIZE (x
.array
))
1967 x
.array
[2] |= y
.array
[2];
1970 x
.array
[1] |= y
.array
[1];
1973 x
.array
[0] |= y
.array
[0];
1981 static INLINE i386_operand_type
1982 operand_type_xor (i386_operand_type x
, i386_operand_type y
)
1984 gas_assert (y
.bitfield
.class == ClassNone
);
1985 gas_assert (y
.bitfield
.instance
== InstanceNone
);
1987 switch (ARRAY_SIZE (x
.array
))
1990 x
.array
[2] ^= y
.array
[2];
1993 x
.array
[1] ^= y
.array
[1];
1996 x
.array
[0] ^= y
.array
[0];
2004 static const i386_operand_type disp16
= OPERAND_TYPE_DISP16
;
2005 static const i386_operand_type disp32
= OPERAND_TYPE_DISP32
;
2006 static const i386_operand_type disp32s
= OPERAND_TYPE_DISP32S
;
2007 static const i386_operand_type disp16_32
= OPERAND_TYPE_DISP16_32
;
2008 static const i386_operand_type anydisp
= OPERAND_TYPE_ANYDISP
;
2009 static const i386_operand_type anyimm
= OPERAND_TYPE_ANYIMM
;
2010 static const i386_operand_type regxmm
= OPERAND_TYPE_REGXMM
;
2011 static const i386_operand_type regmask
= OPERAND_TYPE_REGMASK
;
2012 static const i386_operand_type imm8
= OPERAND_TYPE_IMM8
;
2013 static const i386_operand_type imm8s
= OPERAND_TYPE_IMM8S
;
2014 static const i386_operand_type imm16
= OPERAND_TYPE_IMM16
;
2015 static const i386_operand_type imm32
= OPERAND_TYPE_IMM32
;
2016 static const i386_operand_type imm32s
= OPERAND_TYPE_IMM32S
;
2017 static const i386_operand_type imm64
= OPERAND_TYPE_IMM64
;
2018 static const i386_operand_type imm16_32
= OPERAND_TYPE_IMM16_32
;
2019 static const i386_operand_type imm16_32s
= OPERAND_TYPE_IMM16_32S
;
2020 static const i386_operand_type imm16_32_32s
= OPERAND_TYPE_IMM16_32_32S
;
2031 operand_type_check (i386_operand_type t
, enum operand_type c
)
2036 return t
.bitfield
.class == Reg
;
2039 return (t
.bitfield
.imm8
2043 || t
.bitfield
.imm32s
2044 || t
.bitfield
.imm64
);
2047 return (t
.bitfield
.disp8
2048 || t
.bitfield
.disp16
2049 || t
.bitfield
.disp32
2050 || t
.bitfield
.disp32s
2051 || t
.bitfield
.disp64
);
2054 return (t
.bitfield
.disp8
2055 || t
.bitfield
.disp16
2056 || t
.bitfield
.disp32
2057 || t
.bitfield
.disp32s
2058 || t
.bitfield
.disp64
2059 || t
.bitfield
.baseindex
);
2068 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit/80bit size
2069 between operand GIVEN and opeand WANTED for instruction template T. */
2072 match_operand_size (const insn_template
*t
, unsigned int wanted
,
2075 return !((i
.types
[given
].bitfield
.byte
2076 && !t
->operand_types
[wanted
].bitfield
.byte
)
2077 || (i
.types
[given
].bitfield
.word
2078 && !t
->operand_types
[wanted
].bitfield
.word
)
2079 || (i
.types
[given
].bitfield
.dword
2080 && !t
->operand_types
[wanted
].bitfield
.dword
)
2081 || (i
.types
[given
].bitfield
.qword
2082 && !t
->operand_types
[wanted
].bitfield
.qword
)
2083 || (i
.types
[given
].bitfield
.tbyte
2084 && !t
->operand_types
[wanted
].bitfield
.tbyte
));
2087 /* Return 1 if there is no conflict in SIMD register between operand
2088 GIVEN and opeand WANTED for instruction template T. */
2091 match_simd_size (const insn_template
*t
, unsigned int wanted
,
2094 return !((i
.types
[given
].bitfield
.xmmword
2095 && !t
->operand_types
[wanted
].bitfield
.xmmword
)
2096 || (i
.types
[given
].bitfield
.ymmword
2097 && !t
->operand_types
[wanted
].bitfield
.ymmword
)
2098 || (i
.types
[given
].bitfield
.zmmword
2099 && !t
->operand_types
[wanted
].bitfield
.zmmword
));
2102 /* Return 1 if there is no conflict in any size between operand GIVEN
2103 and opeand WANTED for instruction template T. */
2106 match_mem_size (const insn_template
*t
, unsigned int wanted
,
2109 return (match_operand_size (t
, wanted
, given
)
2110 && !((i
.types
[given
].bitfield
.unspecified
2112 && !t
->operand_types
[wanted
].bitfield
.unspecified
)
2113 || (i
.types
[given
].bitfield
.fword
2114 && !t
->operand_types
[wanted
].bitfield
.fword
)
2115 /* For scalar opcode templates to allow register and memory
2116 operands at the same time, some special casing is needed
2117 here. Also for v{,p}broadcast*, {,v}pmov{s,z}*, and
2118 down-conversion vpmov*. */
2119 || ((t
->operand_types
[wanted
].bitfield
.class == RegSIMD
2120 && !t
->opcode_modifier
.broadcast
2121 && (t
->operand_types
[wanted
].bitfield
.byte
2122 || t
->operand_types
[wanted
].bitfield
.word
2123 || t
->operand_types
[wanted
].bitfield
.dword
2124 || t
->operand_types
[wanted
].bitfield
.qword
))
2125 ? (i
.types
[given
].bitfield
.xmmword
2126 || i
.types
[given
].bitfield
.ymmword
2127 || i
.types
[given
].bitfield
.zmmword
)
2128 : !match_simd_size(t
, wanted
, given
))));
2131 /* Return value has MATCH_STRAIGHT set if there is no size conflict on any
2132 operands for instruction template T, and it has MATCH_REVERSE set if there
2133 is no size conflict on any operands for the template with operands reversed
2134 (and the template allows for reversing in the first place). */
2136 #define MATCH_STRAIGHT 1
2137 #define MATCH_REVERSE 2
2139 static INLINE
unsigned int
2140 operand_size_match (const insn_template
*t
)
2142 unsigned int j
, match
= MATCH_STRAIGHT
;
2144 /* Don't check non-absolute jump instructions. */
2145 if (t
->opcode_modifier
.jump
2146 && t
->opcode_modifier
.jump
!= JUMP_ABSOLUTE
)
2149 /* Check memory and accumulator operand size. */
2150 for (j
= 0; j
< i
.operands
; j
++)
2152 if (i
.types
[j
].bitfield
.class != Reg
2153 && i
.types
[j
].bitfield
.class != RegSIMD
2154 && t
->opcode_modifier
.anysize
)
2157 if (t
->operand_types
[j
].bitfield
.class == Reg
2158 && !match_operand_size (t
, j
, j
))
2164 if (t
->operand_types
[j
].bitfield
.class == RegSIMD
2165 && !match_simd_size (t
, j
, j
))
2171 if (t
->operand_types
[j
].bitfield
.instance
== Accum
2172 && (!match_operand_size (t
, j
, j
) || !match_simd_size (t
, j
, j
)))
2178 if ((i
.flags
[j
] & Operand_Mem
) && !match_mem_size (t
, j
, j
))
2185 if (!t
->opcode_modifier
.d
)
2189 i
.error
= operand_size_mismatch
;
2193 /* Check reverse. */
2194 gas_assert (i
.operands
>= 2 && i
.operands
<= 3);
2196 for (j
= 0; j
< i
.operands
; j
++)
2198 unsigned int given
= i
.operands
- j
- 1;
2200 if (t
->operand_types
[j
].bitfield
.class == Reg
2201 && !match_operand_size (t
, j
, given
))
2204 if (t
->operand_types
[j
].bitfield
.class == RegSIMD
2205 && !match_simd_size (t
, j
, given
))
2208 if (t
->operand_types
[j
].bitfield
.instance
== Accum
2209 && (!match_operand_size (t
, j
, given
)
2210 || !match_simd_size (t
, j
, given
)))
2213 if ((i
.flags
[given
] & Operand_Mem
) && !match_mem_size (t
, j
, given
))
2217 return match
| MATCH_REVERSE
;
2221 operand_type_match (i386_operand_type overlap
,
2222 i386_operand_type given
)
2224 i386_operand_type temp
= overlap
;
2226 temp
.bitfield
.unspecified
= 0;
2227 temp
.bitfield
.byte
= 0;
2228 temp
.bitfield
.word
= 0;
2229 temp
.bitfield
.dword
= 0;
2230 temp
.bitfield
.fword
= 0;
2231 temp
.bitfield
.qword
= 0;
2232 temp
.bitfield
.tbyte
= 0;
2233 temp
.bitfield
.xmmword
= 0;
2234 temp
.bitfield
.ymmword
= 0;
2235 temp
.bitfield
.zmmword
= 0;
2236 if (operand_type_all_zero (&temp
))
2239 if (given
.bitfield
.baseindex
== overlap
.bitfield
.baseindex
)
2243 i
.error
= operand_type_mismatch
;
2247 /* If given types g0 and g1 are registers they must be of the same type
2248 unless the expected operand type register overlap is null.
2249 Some Intel syntax memory operand size checking also happens here. */
2252 operand_type_register_match (i386_operand_type g0
,
2253 i386_operand_type t0
,
2254 i386_operand_type g1
,
2255 i386_operand_type t1
)
2257 if (g0
.bitfield
.class != Reg
2258 && g0
.bitfield
.class != RegSIMD
2259 && (!operand_type_check (g0
, anymem
)
2260 || g0
.bitfield
.unspecified
2261 || (t0
.bitfield
.class != Reg
2262 && t0
.bitfield
.class != RegSIMD
)))
2265 if (g1
.bitfield
.class != Reg
2266 && g1
.bitfield
.class != RegSIMD
2267 && (!operand_type_check (g1
, anymem
)
2268 || g1
.bitfield
.unspecified
2269 || (t1
.bitfield
.class != Reg
2270 && t1
.bitfield
.class != RegSIMD
)))
2273 if (g0
.bitfield
.byte
== g1
.bitfield
.byte
2274 && g0
.bitfield
.word
== g1
.bitfield
.word
2275 && g0
.bitfield
.dword
== g1
.bitfield
.dword
2276 && g0
.bitfield
.qword
== g1
.bitfield
.qword
2277 && g0
.bitfield
.xmmword
== g1
.bitfield
.xmmword
2278 && g0
.bitfield
.ymmword
== g1
.bitfield
.ymmword
2279 && g0
.bitfield
.zmmword
== g1
.bitfield
.zmmword
)
2282 if (!(t0
.bitfield
.byte
& t1
.bitfield
.byte
)
2283 && !(t0
.bitfield
.word
& t1
.bitfield
.word
)
2284 && !(t0
.bitfield
.dword
& t1
.bitfield
.dword
)
2285 && !(t0
.bitfield
.qword
& t1
.bitfield
.qword
)
2286 && !(t0
.bitfield
.xmmword
& t1
.bitfield
.xmmword
)
2287 && !(t0
.bitfield
.ymmword
& t1
.bitfield
.ymmword
)
2288 && !(t0
.bitfield
.zmmword
& t1
.bitfield
.zmmword
))
2291 i
.error
= register_type_mismatch
;
2296 static INLINE
unsigned int
2297 register_number (const reg_entry
*r
)
2299 unsigned int nr
= r
->reg_num
;
2301 if (r
->reg_flags
& RegRex
)
2304 if (r
->reg_flags
& RegVRex
)
2310 static INLINE
unsigned int
2311 mode_from_disp_size (i386_operand_type t
)
2313 if (t
.bitfield
.disp8
)
2315 else if (t
.bitfield
.disp16
2316 || t
.bitfield
.disp32
2317 || t
.bitfield
.disp32s
)
2324 fits_in_signed_byte (addressT num
)
2326 return num
+ 0x80 <= 0xff;
2330 fits_in_unsigned_byte (addressT num
)
2336 fits_in_unsigned_word (addressT num
)
2338 return num
<= 0xffff;
2342 fits_in_signed_word (addressT num
)
2344 return num
+ 0x8000 <= 0xffff;
2348 fits_in_signed_long (addressT num ATTRIBUTE_UNUSED
)
2353 return num
+ 0x80000000 <= 0xffffffff;
2355 } /* fits_in_signed_long() */
2358 fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED
)
2363 return num
<= 0xffffffff;
2365 } /* fits_in_unsigned_long() */
2368 fits_in_disp8 (offsetT num
)
2370 int shift
= i
.memshift
;
2376 mask
= (1 << shift
) - 1;
2378 /* Return 0 if NUM isn't properly aligned. */
2382 /* Check if NUM will fit in 8bit after shift. */
2383 return fits_in_signed_byte (num
>> shift
);
2387 fits_in_imm4 (offsetT num
)
2389 return (num
& 0xf) == num
;
2392 static i386_operand_type
2393 smallest_imm_type (offsetT num
)
2395 i386_operand_type t
;
2397 operand_type_set (&t
, 0);
2398 t
.bitfield
.imm64
= 1;
2400 if (cpu_arch_tune
!= PROCESSOR_I486
&& num
== 1)
2402 /* This code is disabled on the 486 because all the Imm1 forms
2403 in the opcode table are slower on the i486. They're the
2404 versions with the implicitly specified single-position
2405 displacement, which has another syntax if you really want to
2407 t
.bitfield
.imm1
= 1;
2408 t
.bitfield
.imm8
= 1;
2409 t
.bitfield
.imm8s
= 1;
2410 t
.bitfield
.imm16
= 1;
2411 t
.bitfield
.imm32
= 1;
2412 t
.bitfield
.imm32s
= 1;
2414 else if (fits_in_signed_byte (num
))
2416 t
.bitfield
.imm8
= 1;
2417 t
.bitfield
.imm8s
= 1;
2418 t
.bitfield
.imm16
= 1;
2419 t
.bitfield
.imm32
= 1;
2420 t
.bitfield
.imm32s
= 1;
2422 else if (fits_in_unsigned_byte (num
))
2424 t
.bitfield
.imm8
= 1;
2425 t
.bitfield
.imm16
= 1;
2426 t
.bitfield
.imm32
= 1;
2427 t
.bitfield
.imm32s
= 1;
2429 else if (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
2431 t
.bitfield
.imm16
= 1;
2432 t
.bitfield
.imm32
= 1;
2433 t
.bitfield
.imm32s
= 1;
2435 else if (fits_in_signed_long (num
))
2437 t
.bitfield
.imm32
= 1;
2438 t
.bitfield
.imm32s
= 1;
2440 else if (fits_in_unsigned_long (num
))
2441 t
.bitfield
.imm32
= 1;
2447 offset_in_range (offsetT val
, int size
)
2453 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
2454 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
2455 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
2457 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
2463 /* If BFD64, sign extend val for 32bit address mode. */
2464 if (flag_code
!= CODE_64BIT
2465 || i
.prefix
[ADDR_PREFIX
])
2466 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
2467 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
2470 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
2472 char buf1
[40], buf2
[40];
2474 sprint_value (buf1
, val
);
2475 sprint_value (buf2
, val
& mask
);
2476 as_warn (_("%s shortened to %s"), buf1
, buf2
);
2491 a. PREFIX_EXIST if attempting to add a prefix where one from the
2492 same class already exists.
2493 b. PREFIX_LOCK if lock prefix is added.
2494 c. PREFIX_REP if rep/repne prefix is added.
2495 d. PREFIX_DS if ds prefix is added.
2496 e. PREFIX_OTHER if other prefix is added.
2499 static enum PREFIX_GROUP
2500 add_prefix (unsigned int prefix
)
2502 enum PREFIX_GROUP ret
= PREFIX_OTHER
;
2505 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
2506 && flag_code
== CODE_64BIT
)
2508 if ((i
.prefix
[REX_PREFIX
] & prefix
& REX_W
)
2509 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_R
)
2510 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_X
)
2511 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_B
))
2522 case DS_PREFIX_OPCODE
:
2525 case CS_PREFIX_OPCODE
:
2526 case ES_PREFIX_OPCODE
:
2527 case FS_PREFIX_OPCODE
:
2528 case GS_PREFIX_OPCODE
:
2529 case SS_PREFIX_OPCODE
:
2533 case REPNE_PREFIX_OPCODE
:
2534 case REPE_PREFIX_OPCODE
:
2539 case LOCK_PREFIX_OPCODE
:
2548 case ADDR_PREFIX_OPCODE
:
2552 case DATA_PREFIX_OPCODE
:
2556 if (i
.prefix
[q
] != 0)
2564 i
.prefix
[q
] |= prefix
;
2567 as_bad (_("same type of prefix used twice"));
2573 update_code_flag (int value
, int check
)
2575 PRINTF_LIKE ((*as_error
));
2577 flag_code
= (enum flag_code
) value
;
2578 if (flag_code
== CODE_64BIT
)
2580 cpu_arch_flags
.bitfield
.cpu64
= 1;
2581 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2585 cpu_arch_flags
.bitfield
.cpu64
= 0;
2586 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2588 if (value
== CODE_64BIT
&& !cpu_arch_flags
.bitfield
.cpulm
)
2591 as_error
= as_fatal
;
2594 (*as_error
) (_("64bit mode not supported on `%s'."),
2595 cpu_arch_name
? cpu_arch_name
: default_arch
);
2597 if (value
== CODE_32BIT
&& !cpu_arch_flags
.bitfield
.cpui386
)
2600 as_error
= as_fatal
;
2603 (*as_error
) (_("32bit mode not supported on `%s'."),
2604 cpu_arch_name
? cpu_arch_name
: default_arch
);
2606 stackop_size
= '\0';
2610 set_code_flag (int value
)
2612 update_code_flag (value
, 0);
2616 set_16bit_gcc_code_flag (int new_code_flag
)
2618 flag_code
= (enum flag_code
) new_code_flag
;
2619 if (flag_code
!= CODE_16BIT
)
2621 cpu_arch_flags
.bitfield
.cpu64
= 0;
2622 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2623 stackop_size
= LONG_MNEM_SUFFIX
;
2627 set_intel_syntax (int syntax_flag
)
2629 /* Find out if register prefixing is specified. */
2630 int ask_naked_reg
= 0;
2633 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2636 int e
= get_symbol_name (&string
);
2638 if (strcmp (string
, "prefix") == 0)
2640 else if (strcmp (string
, "noprefix") == 0)
2643 as_bad (_("bad argument to syntax directive."));
2644 (void) restore_line_pointer (e
);
2646 demand_empty_rest_of_line ();
2648 intel_syntax
= syntax_flag
;
2650 if (ask_naked_reg
== 0)
2651 allow_naked_reg
= (intel_syntax
2652 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
2654 allow_naked_reg
= (ask_naked_reg
< 0);
2656 expr_set_rank (O_full_ptr
, syntax_flag
? 10 : 0);
2658 identifier_chars
['%'] = intel_syntax
&& allow_naked_reg
? '%' : 0;
2659 identifier_chars
['$'] = intel_syntax
? '$' : 0;
2660 register_prefix
= allow_naked_reg
? "" : "%";
2664 set_intel_mnemonic (int mnemonic_flag
)
2666 intel_mnemonic
= mnemonic_flag
;
2670 set_allow_index_reg (int flag
)
2672 allow_index_reg
= flag
;
2676 set_check (int what
)
2678 enum check_kind
*kind
;
2683 kind
= &operand_check
;
2694 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2697 int e
= get_symbol_name (&string
);
2699 if (strcmp (string
, "none") == 0)
2701 else if (strcmp (string
, "warning") == 0)
2702 *kind
= check_warning
;
2703 else if (strcmp (string
, "error") == 0)
2704 *kind
= check_error
;
2706 as_bad (_("bad argument to %s_check directive."), str
);
2707 (void) restore_line_pointer (e
);
2710 as_bad (_("missing argument for %s_check directive"), str
);
2712 demand_empty_rest_of_line ();
2716 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED
,
2717 i386_cpu_flags new_flag ATTRIBUTE_UNUSED
)
2719 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2720 static const char *arch
;
2722 /* Intel LIOM is only supported on ELF. */
2728 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2729 use default_arch. */
2730 arch
= cpu_arch_name
;
2732 arch
= default_arch
;
2735 /* If we are targeting Intel MCU, we must enable it. */
2736 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_IAMCU
2737 || new_flag
.bitfield
.cpuiamcu
)
2740 /* If we are targeting Intel L1OM, we must enable it. */
2741 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_L1OM
2742 || new_flag
.bitfield
.cpul1om
)
2745 /* If we are targeting Intel K1OM, we must enable it. */
2746 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_K1OM
2747 || new_flag
.bitfield
.cpuk1om
)
2750 as_bad (_("`%s' is not supported on `%s'"), name
, arch
);
2755 set_cpu_arch (int dummy ATTRIBUTE_UNUSED
)
2759 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2762 int e
= get_symbol_name (&string
);
2764 i386_cpu_flags flags
;
2766 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
2768 if (strcmp (string
, cpu_arch
[j
].name
) == 0)
2770 check_cpu_arch_compatible (string
, cpu_arch
[j
].flags
);
2774 cpu_arch_name
= cpu_arch
[j
].name
;
2775 cpu_sub_arch_name
= NULL
;
2776 cpu_arch_flags
= cpu_arch
[j
].flags
;
2777 if (flag_code
== CODE_64BIT
)
2779 cpu_arch_flags
.bitfield
.cpu64
= 1;
2780 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2784 cpu_arch_flags
.bitfield
.cpu64
= 0;
2785 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2787 cpu_arch_isa
= cpu_arch
[j
].type
;
2788 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
2789 if (!cpu_arch_tune_set
)
2791 cpu_arch_tune
= cpu_arch_isa
;
2792 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
2797 flags
= cpu_flags_or (cpu_arch_flags
,
2800 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2802 if (cpu_sub_arch_name
)
2804 char *name
= cpu_sub_arch_name
;
2805 cpu_sub_arch_name
= concat (name
,
2807 (const char *) NULL
);
2811 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
2812 cpu_arch_flags
= flags
;
2813 cpu_arch_isa_flags
= flags
;
2817 = cpu_flags_or (cpu_arch_isa_flags
,
2819 (void) restore_line_pointer (e
);
2820 demand_empty_rest_of_line ();
2825 if (*string
== '.' && j
>= ARRAY_SIZE (cpu_arch
))
2827 /* Disable an ISA extension. */
2828 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
2829 if (strcmp (string
+ 1, cpu_noarch
[j
].name
) == 0)
2831 flags
= cpu_flags_and_not (cpu_arch_flags
,
2832 cpu_noarch
[j
].flags
);
2833 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2835 if (cpu_sub_arch_name
)
2837 char *name
= cpu_sub_arch_name
;
2838 cpu_sub_arch_name
= concat (name
, string
,
2839 (const char *) NULL
);
2843 cpu_sub_arch_name
= xstrdup (string
);
2844 cpu_arch_flags
= flags
;
2845 cpu_arch_isa_flags
= flags
;
2847 (void) restore_line_pointer (e
);
2848 demand_empty_rest_of_line ();
2852 j
= ARRAY_SIZE (cpu_arch
);
2855 if (j
>= ARRAY_SIZE (cpu_arch
))
2856 as_bad (_("no such architecture: `%s'"), string
);
2858 *input_line_pointer
= e
;
2861 as_bad (_("missing cpu architecture"));
2863 no_cond_jump_promotion
= 0;
2864 if (*input_line_pointer
== ','
2865 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
2870 ++input_line_pointer
;
2871 e
= get_symbol_name (&string
);
2873 if (strcmp (string
, "nojumps") == 0)
2874 no_cond_jump_promotion
= 1;
2875 else if (strcmp (string
, "jumps") == 0)
2878 as_bad (_("no such architecture modifier: `%s'"), string
);
2880 (void) restore_line_pointer (e
);
2883 demand_empty_rest_of_line ();
2886 enum bfd_architecture
2889 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2891 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2892 || flag_code
!= CODE_64BIT
)
2893 as_fatal (_("Intel L1OM is 64bit ELF only"));
2894 return bfd_arch_l1om
;
2896 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2898 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2899 || flag_code
!= CODE_64BIT
)
2900 as_fatal (_("Intel K1OM is 64bit ELF only"));
2901 return bfd_arch_k1om
;
2903 else if (cpu_arch_isa
== PROCESSOR_IAMCU
)
2905 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2906 || flag_code
== CODE_64BIT
)
2907 as_fatal (_("Intel MCU is 32bit ELF only"));
2908 return bfd_arch_iamcu
;
2911 return bfd_arch_i386
;
2917 if (!strncmp (default_arch
, "x86_64", 6))
2919 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2921 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2922 || default_arch
[6] != '\0')
2923 as_fatal (_("Intel L1OM is 64bit ELF only"));
2924 return bfd_mach_l1om
;
2926 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2928 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2929 || default_arch
[6] != '\0')
2930 as_fatal (_("Intel K1OM is 64bit ELF only"));
2931 return bfd_mach_k1om
;
2933 else if (default_arch
[6] == '\0')
2934 return bfd_mach_x86_64
;
2936 return bfd_mach_x64_32
;
2938 else if (!strcmp (default_arch
, "i386")
2939 || !strcmp (default_arch
, "iamcu"))
2941 if (cpu_arch_isa
== PROCESSOR_IAMCU
)
2943 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
2944 as_fatal (_("Intel MCU is 32bit ELF only"));
2945 return bfd_mach_i386_iamcu
;
2948 return bfd_mach_i386_i386
;
2951 as_fatal (_("unknown architecture"));
2957 const char *hash_err
;
2959 /* Support pseudo prefixes like {disp32}. */
2960 lex_type
['{'] = LEX_BEGIN_NAME
;
2962 /* Initialize op_hash hash table. */
2963 op_hash
= hash_new ();
2966 const insn_template
*optab
;
2967 templates
*core_optab
;
2969 /* Setup for loop. */
2971 core_optab
= XNEW (templates
);
2972 core_optab
->start
= optab
;
2977 if (optab
->name
== NULL
2978 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
2980 /* different name --> ship out current template list;
2981 add to hash table; & begin anew. */
2982 core_optab
->end
= optab
;
2983 hash_err
= hash_insert (op_hash
,
2985 (void *) core_optab
);
2988 as_fatal (_("can't hash %s: %s"),
2992 if (optab
->name
== NULL
)
2994 core_optab
= XNEW (templates
);
2995 core_optab
->start
= optab
;
3000 /* Initialize reg_hash hash table. */
3001 reg_hash
= hash_new ();
3003 const reg_entry
*regtab
;
3004 unsigned int regtab_size
= i386_regtab_size
;
3006 for (regtab
= i386_regtab
; regtab_size
--; regtab
++)
3008 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (void *) regtab
);
3010 as_fatal (_("can't hash %s: %s"),
3016 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
3021 for (c
= 0; c
< 256; c
++)
3026 mnemonic_chars
[c
] = c
;
3027 register_chars
[c
] = c
;
3028 operand_chars
[c
] = c
;
3030 else if (ISLOWER (c
))
3032 mnemonic_chars
[c
] = c
;
3033 register_chars
[c
] = c
;
3034 operand_chars
[c
] = c
;
3036 else if (ISUPPER (c
))
3038 mnemonic_chars
[c
] = TOLOWER (c
);
3039 register_chars
[c
] = mnemonic_chars
[c
];
3040 operand_chars
[c
] = c
;
3042 else if (c
== '{' || c
== '}')
3044 mnemonic_chars
[c
] = c
;
3045 operand_chars
[c
] = c
;
3048 if (ISALPHA (c
) || ISDIGIT (c
))
3049 identifier_chars
[c
] = c
;
3052 identifier_chars
[c
] = c
;
3053 operand_chars
[c
] = c
;
3058 identifier_chars
['@'] = '@';
3061 identifier_chars
['?'] = '?';
3062 operand_chars
['?'] = '?';
3064 digit_chars
['-'] = '-';
3065 mnemonic_chars
['_'] = '_';
3066 mnemonic_chars
['-'] = '-';
3067 mnemonic_chars
['.'] = '.';
3068 identifier_chars
['_'] = '_';
3069 identifier_chars
['.'] = '.';
3071 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
3072 operand_chars
[(unsigned char) *p
] = *p
;
3075 if (flag_code
== CODE_64BIT
)
3077 #if defined (OBJ_COFF) && defined (TE_PE)
3078 x86_dwarf2_return_column
= (OUTPUT_FLAVOR
== bfd_target_coff_flavour
3081 x86_dwarf2_return_column
= 16;
3083 x86_cie_data_alignment
= -8;
3087 x86_dwarf2_return_column
= 8;
3088 x86_cie_data_alignment
= -4;
3091 /* NB: FUSED_JCC_PADDING frag must have sufficient room so that it
3092 can be turned into BRANCH_PREFIX frag. */
3093 if (align_branch_prefix_size
> MAX_FUSED_JCC_PADDING_SIZE
)
3098 i386_print_statistics (FILE *file
)
3100 hash_print_statistics (file
, "i386 opcode", op_hash
);
3101 hash_print_statistics (file
, "i386 register", reg_hash
);
3106 /* Debugging routines for md_assemble. */
3107 static void pte (insn_template
*);
3108 static void pt (i386_operand_type
);
3109 static void pe (expressionS
*);
3110 static void ps (symbolS
*);
3113 pi (const char *line
, i386_insn
*x
)
3117 fprintf (stdout
, "%s: template ", line
);
3119 fprintf (stdout
, " address: base %s index %s scale %x\n",
3120 x
->base_reg
? x
->base_reg
->reg_name
: "none",
3121 x
->index_reg
? x
->index_reg
->reg_name
: "none",
3122 x
->log2_scale_factor
);
3123 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
3124 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
3125 fprintf (stdout
, " sib: base %x index %x scale %x\n",
3126 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
3127 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
3128 (x
->rex
& REX_W
) != 0,
3129 (x
->rex
& REX_R
) != 0,
3130 (x
->rex
& REX_X
) != 0,
3131 (x
->rex
& REX_B
) != 0);
3132 for (j
= 0; j
< x
->operands
; j
++)
3134 fprintf (stdout
, " #%d: ", j
+ 1);
3136 fprintf (stdout
, "\n");
3137 if (x
->types
[j
].bitfield
.class == Reg
3138 || x
->types
[j
].bitfield
.class == RegMMX
3139 || x
->types
[j
].bitfield
.class == RegSIMD
3140 || x
->types
[j
].bitfield
.class == SReg
3141 || x
->types
[j
].bitfield
.class == RegCR
3142 || x
->types
[j
].bitfield
.class == RegDR
3143 || x
->types
[j
].bitfield
.class == RegTR
)
3144 fprintf (stdout
, "%s\n", x
->op
[j
].regs
->reg_name
);
3145 if (operand_type_check (x
->types
[j
], imm
))
3147 if (operand_type_check (x
->types
[j
], disp
))
3148 pe (x
->op
[j
].disps
);
3153 pte (insn_template
*t
)
3156 fprintf (stdout
, " %d operands ", t
->operands
);
3157 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
3158 if (t
->extension_opcode
!= None
)
3159 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
3160 if (t
->opcode_modifier
.d
)
3161 fprintf (stdout
, "D");
3162 if (t
->opcode_modifier
.w
)
3163 fprintf (stdout
, "W");
3164 fprintf (stdout
, "\n");
3165 for (j
= 0; j
< t
->operands
; j
++)
3167 fprintf (stdout
, " #%d type ", j
+ 1);
3168 pt (t
->operand_types
[j
]);
3169 fprintf (stdout
, "\n");
3176 fprintf (stdout
, " operation %d\n", e
->X_op
);
3177 fprintf (stdout
, " add_number %ld (%lx)\n",
3178 (long) e
->X_add_number
, (long) e
->X_add_number
);
3179 if (e
->X_add_symbol
)
3181 fprintf (stdout
, " add_symbol ");
3182 ps (e
->X_add_symbol
);
3183 fprintf (stdout
, "\n");
3187 fprintf (stdout
, " op_symbol ");
3188 ps (e
->X_op_symbol
);
3189 fprintf (stdout
, "\n");
3196 fprintf (stdout
, "%s type %s%s",
3198 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
3199 segment_name (S_GET_SEGMENT (s
)));
3202 static struct type_name
3204 i386_operand_type mask
;
3207 const type_names
[] =
3209 { OPERAND_TYPE_REG8
, "r8" },
3210 { OPERAND_TYPE_REG16
, "r16" },
3211 { OPERAND_TYPE_REG32
, "r32" },
3212 { OPERAND_TYPE_REG64
, "r64" },
3213 { OPERAND_TYPE_ACC8
, "acc8" },
3214 { OPERAND_TYPE_ACC16
, "acc16" },
3215 { OPERAND_TYPE_ACC32
, "acc32" },
3216 { OPERAND_TYPE_ACC64
, "acc64" },
3217 { OPERAND_TYPE_IMM8
, "i8" },
3218 { OPERAND_TYPE_IMM8
, "i8s" },
3219 { OPERAND_TYPE_IMM16
, "i16" },
3220 { OPERAND_TYPE_IMM32
, "i32" },
3221 { OPERAND_TYPE_IMM32S
, "i32s" },
3222 { OPERAND_TYPE_IMM64
, "i64" },
3223 { OPERAND_TYPE_IMM1
, "i1" },
3224 { OPERAND_TYPE_BASEINDEX
, "BaseIndex" },
3225 { OPERAND_TYPE_DISP8
, "d8" },
3226 { OPERAND_TYPE_DISP16
, "d16" },
3227 { OPERAND_TYPE_DISP32
, "d32" },
3228 { OPERAND_TYPE_DISP32S
, "d32s" },
3229 { OPERAND_TYPE_DISP64
, "d64" },
3230 { OPERAND_TYPE_INOUTPORTREG
, "InOutPortReg" },
3231 { OPERAND_TYPE_SHIFTCOUNT
, "ShiftCount" },
3232 { OPERAND_TYPE_CONTROL
, "control reg" },
3233 { OPERAND_TYPE_TEST
, "test reg" },
3234 { OPERAND_TYPE_DEBUG
, "debug reg" },
3235 { OPERAND_TYPE_FLOATREG
, "FReg" },
3236 { OPERAND_TYPE_FLOATACC
, "FAcc" },
3237 { OPERAND_TYPE_SREG
, "SReg" },
3238 { OPERAND_TYPE_REGMMX
, "rMMX" },
3239 { OPERAND_TYPE_REGXMM
, "rXMM" },
3240 { OPERAND_TYPE_REGYMM
, "rYMM" },
3241 { OPERAND_TYPE_REGZMM
, "rZMM" },
3242 { OPERAND_TYPE_REGMASK
, "Mask reg" },
3246 pt (i386_operand_type t
)
3249 i386_operand_type a
;
3251 for (j
= 0; j
< ARRAY_SIZE (type_names
); j
++)
3253 a
= operand_type_and (t
, type_names
[j
].mask
);
3254 if (operand_type_equal (&a
, &type_names
[j
].mask
))
3255 fprintf (stdout
, "%s, ", type_names
[j
].name
);
3260 #endif /* DEBUG386 */
3262 static bfd_reloc_code_real_type
3263 reloc (unsigned int size
,
3266 bfd_reloc_code_real_type other
)
3268 if (other
!= NO_RELOC
)
3270 reloc_howto_type
*rel
;
3275 case BFD_RELOC_X86_64_GOT32
:
3276 return BFD_RELOC_X86_64_GOT64
;
3278 case BFD_RELOC_X86_64_GOTPLT64
:
3279 return BFD_RELOC_X86_64_GOTPLT64
;
3281 case BFD_RELOC_X86_64_PLTOFF64
:
3282 return BFD_RELOC_X86_64_PLTOFF64
;
3284 case BFD_RELOC_X86_64_GOTPC32
:
3285 other
= BFD_RELOC_X86_64_GOTPC64
;
3287 case BFD_RELOC_X86_64_GOTPCREL
:
3288 other
= BFD_RELOC_X86_64_GOTPCREL64
;
3290 case BFD_RELOC_X86_64_TPOFF32
:
3291 other
= BFD_RELOC_X86_64_TPOFF64
;
3293 case BFD_RELOC_X86_64_DTPOFF32
:
3294 other
= BFD_RELOC_X86_64_DTPOFF64
;
3300 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3301 if (other
== BFD_RELOC_SIZE32
)
3304 other
= BFD_RELOC_SIZE64
;
3307 as_bad (_("there are no pc-relative size relocations"));
3313 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
3314 if (size
== 4 && (flag_code
!= CODE_64BIT
|| disallow_64bit_reloc
))
3317 rel
= bfd_reloc_type_lookup (stdoutput
, other
);
3319 as_bad (_("unknown relocation (%u)"), other
);
3320 else if (size
!= bfd_get_reloc_size (rel
))
3321 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
3322 bfd_get_reloc_size (rel
),
3324 else if (pcrel
&& !rel
->pc_relative
)
3325 as_bad (_("non-pc-relative relocation for pc-relative field"));
3326 else if ((rel
->complain_on_overflow
== complain_overflow_signed
3328 || (rel
->complain_on_overflow
== complain_overflow_unsigned
3330 as_bad (_("relocated field and relocation type differ in signedness"));
3339 as_bad (_("there are no unsigned pc-relative relocations"));
3342 case 1: return BFD_RELOC_8_PCREL
;
3343 case 2: return BFD_RELOC_16_PCREL
;
3344 case 4: return BFD_RELOC_32_PCREL
;
3345 case 8: return BFD_RELOC_64_PCREL
;
3347 as_bad (_("cannot do %u byte pc-relative relocation"), size
);
3354 case 4: return BFD_RELOC_X86_64_32S
;
3359 case 1: return BFD_RELOC_8
;
3360 case 2: return BFD_RELOC_16
;
3361 case 4: return BFD_RELOC_32
;
3362 case 8: return BFD_RELOC_64
;
3364 as_bad (_("cannot do %s %u byte relocation"),
3365 sign
> 0 ? "signed" : "unsigned", size
);
3371 /* Here we decide which fixups can be adjusted to make them relative to
3372 the beginning of the section instead of the symbol. Basically we need
3373 to make sure that the dynamic relocations are done correctly, so in
3374 some cases we force the original symbol to be used. */
3377 tc_i386_fix_adjustable (fixS
*fixP ATTRIBUTE_UNUSED
)
3379 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3383 /* Don't adjust pc-relative references to merge sections in 64-bit
3385 if (use_rela_relocations
3386 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
3390 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
3391 and changed later by validate_fix. */
3392 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
3393 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
3396 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
3397 for size relocations. */
3398 if (fixP
->fx_r_type
== BFD_RELOC_SIZE32
3399 || fixP
->fx_r_type
== BFD_RELOC_SIZE64
3400 || fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
3401 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
3402 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32X
3403 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
3404 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
3405 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
3406 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
3407 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
3408 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
3409 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
3410 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
3411 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTDESC
3412 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_DESC_CALL
3413 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
3414 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
3415 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCRELX
3416 || fixP
->fx_r_type
== BFD_RELOC_X86_64_REX_GOTPCRELX
3417 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
3418 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
3419 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
3420 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
3421 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
3422 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
3423 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
3424 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
3425 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPC32_TLSDESC
3426 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSDESC_CALL
3427 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
3428 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
3435 intel_float_operand (const char *mnemonic
)
3437 /* Note that the value returned is meaningful only for opcodes with (memory)
3438 operands, hence the code here is free to improperly handle opcodes that
3439 have no operands (for better performance and smaller code). */
3441 if (mnemonic
[0] != 'f')
3442 return 0; /* non-math */
3444 switch (mnemonic
[1])
3446 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
3447 the fs segment override prefix not currently handled because no
3448 call path can make opcodes without operands get here */
3450 return 2 /* integer op */;
3452 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
3453 return 3; /* fldcw/fldenv */
3456 if (mnemonic
[2] != 'o' /* fnop */)
3457 return 3; /* non-waiting control op */
3460 if (mnemonic
[2] == 's')
3461 return 3; /* frstor/frstpm */
3464 if (mnemonic
[2] == 'a')
3465 return 3; /* fsave */
3466 if (mnemonic
[2] == 't')
3468 switch (mnemonic
[3])
3470 case 'c': /* fstcw */
3471 case 'd': /* fstdw */
3472 case 'e': /* fstenv */
3473 case 's': /* fsts[gw] */
3479 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
3480 return 0; /* fxsave/fxrstor are not really math ops */
3487 /* Build the VEX prefix. */
3490 build_vex_prefix (const insn_template
*t
)
3492 unsigned int register_specifier
;
3493 unsigned int implied_prefix
;
3494 unsigned int vector_length
;
3497 /* Check register specifier. */
3498 if (i
.vex
.register_specifier
)
3500 register_specifier
=
3501 ~register_number (i
.vex
.register_specifier
) & 0xf;
3502 gas_assert ((i
.vex
.register_specifier
->reg_flags
& RegVRex
) == 0);
3505 register_specifier
= 0xf;
3507 /* Use 2-byte VEX prefix by swapping destination and source operand
3508 if there are more than 1 register operand. */
3509 if (i
.reg_operands
> 1
3510 && i
.vec_encoding
!= vex_encoding_vex3
3511 && i
.dir_encoding
== dir_encoding_default
3512 && i
.operands
== i
.reg_operands
3513 && operand_type_equal (&i
.types
[0], &i
.types
[i
.operands
- 1])
3514 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3515 && (i
.tm
.opcode_modifier
.load
|| i
.tm
.opcode_modifier
.d
)
3518 unsigned int xchg
= i
.operands
- 1;
3519 union i386_op temp_op
;
3520 i386_operand_type temp_type
;
3522 temp_type
= i
.types
[xchg
];
3523 i
.types
[xchg
] = i
.types
[0];
3524 i
.types
[0] = temp_type
;
3525 temp_op
= i
.op
[xchg
];
3526 i
.op
[xchg
] = i
.op
[0];
3529 gas_assert (i
.rm
.mode
== 3);
3533 i
.rm
.regmem
= i
.rm
.reg
;
3536 if (i
.tm
.opcode_modifier
.d
)
3537 i
.tm
.base_opcode
^= (i
.tm
.base_opcode
& 0xee) != 0x6e
3538 ? Opcode_SIMD_FloatD
: Opcode_SIMD_IntD
;
3539 else /* Use the next insn. */
3543 /* Use 2-byte VEX prefix by swapping commutative source operands if there
3544 are no memory operands and at least 3 register ones. */
3545 if (i
.reg_operands
>= 3
3546 && i
.vec_encoding
!= vex_encoding_vex3
3547 && i
.reg_operands
== i
.operands
- i
.imm_operands
3548 && i
.tm
.opcode_modifier
.vex
3549 && i
.tm
.opcode_modifier
.commutative
3550 && (i
.tm
.opcode_modifier
.sse2avx
|| optimize
> 1)
3552 && i
.vex
.register_specifier
3553 && !(i
.vex
.register_specifier
->reg_flags
& RegRex
))
3555 unsigned int xchg
= i
.operands
- i
.reg_operands
;
3556 union i386_op temp_op
;
3557 i386_operand_type temp_type
;
3559 gas_assert (i
.tm
.opcode_modifier
.vexopcode
== VEX0F
);
3560 gas_assert (!i
.tm
.opcode_modifier
.sae
);
3561 gas_assert (operand_type_equal (&i
.types
[i
.operands
- 2],
3562 &i
.types
[i
.operands
- 3]));
3563 gas_assert (i
.rm
.mode
== 3);
3565 temp_type
= i
.types
[xchg
];
3566 i
.types
[xchg
] = i
.types
[xchg
+ 1];
3567 i
.types
[xchg
+ 1] = temp_type
;
3568 temp_op
= i
.op
[xchg
];
3569 i
.op
[xchg
] = i
.op
[xchg
+ 1];
3570 i
.op
[xchg
+ 1] = temp_op
;
3573 xchg
= i
.rm
.regmem
| 8;
3574 i
.rm
.regmem
= ~register_specifier
& 0xf;
3575 gas_assert (!(i
.rm
.regmem
& 8));
3576 i
.vex
.register_specifier
+= xchg
- i
.rm
.regmem
;
3577 register_specifier
= ~xchg
& 0xf;
3580 if (i
.tm
.opcode_modifier
.vex
== VEXScalar
)
3581 vector_length
= avxscalar
;
3582 else if (i
.tm
.opcode_modifier
.vex
== VEX256
)
3588 /* Determine vector length from the last multi-length vector
3591 for (op
= t
->operands
; op
--;)
3592 if (t
->operand_types
[op
].bitfield
.xmmword
3593 && t
->operand_types
[op
].bitfield
.ymmword
3594 && i
.types
[op
].bitfield
.ymmword
)
3601 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3606 case DATA_PREFIX_OPCODE
:
3609 case REPE_PREFIX_OPCODE
:
3612 case REPNE_PREFIX_OPCODE
:
3619 /* Check the REX.W bit and VEXW. */
3620 if (i
.tm
.opcode_modifier
.vexw
== VEXWIG
)
3621 w
= (vexwig
== vexw1
|| (i
.rex
& REX_W
)) ? 1 : 0;
3622 else if (i
.tm
.opcode_modifier
.vexw
)
3623 w
= i
.tm
.opcode_modifier
.vexw
== VEXW1
? 1 : 0;
3625 w
= (flag_code
== CODE_64BIT
? i
.rex
& REX_W
: vexwig
== vexw1
) ? 1 : 0;
3627 /* Use 2-byte VEX prefix if possible. */
3629 && i
.vec_encoding
!= vex_encoding_vex3
3630 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3631 && (i
.rex
& (REX_W
| REX_X
| REX_B
)) == 0)
3633 /* 2-byte VEX prefix. */
3637 i
.vex
.bytes
[0] = 0xc5;
3639 /* Check the REX.R bit. */
3640 r
= (i
.rex
& REX_R
) ? 0 : 1;
3641 i
.vex
.bytes
[1] = (r
<< 7
3642 | register_specifier
<< 3
3643 | vector_length
<< 2
3648 /* 3-byte VEX prefix. */
3653 switch (i
.tm
.opcode_modifier
.vexopcode
)
3657 i
.vex
.bytes
[0] = 0xc4;
3661 i
.vex
.bytes
[0] = 0xc4;
3665 i
.vex
.bytes
[0] = 0xc4;
3669 i
.vex
.bytes
[0] = 0x8f;
3673 i
.vex
.bytes
[0] = 0x8f;
3677 i
.vex
.bytes
[0] = 0x8f;
3683 /* The high 3 bits of the second VEX byte are 1's compliment
3684 of RXB bits from REX. */
3685 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3687 i
.vex
.bytes
[2] = (w
<< 7
3688 | register_specifier
<< 3
3689 | vector_length
<< 2
3694 static INLINE bfd_boolean
3695 is_evex_encoding (const insn_template
*t
)
3697 return t
->opcode_modifier
.evex
|| t
->opcode_modifier
.disp8memshift
3698 || t
->opcode_modifier
.broadcast
|| t
->opcode_modifier
.masking
3699 || t
->opcode_modifier
.sae
;
3702 static INLINE bfd_boolean
3703 is_any_vex_encoding (const insn_template
*t
)
3705 return t
->opcode_modifier
.vex
|| t
->opcode_modifier
.vexopcode
3706 || is_evex_encoding (t
);
3709 /* Build the EVEX prefix. */
3712 build_evex_prefix (void)
3714 unsigned int register_specifier
;
3715 unsigned int implied_prefix
;
3717 rex_byte vrex_used
= 0;
3719 /* Check register specifier. */
3720 if (i
.vex
.register_specifier
)
3722 gas_assert ((i
.vrex
& REX_X
) == 0);
3724 register_specifier
= i
.vex
.register_specifier
->reg_num
;
3725 if ((i
.vex
.register_specifier
->reg_flags
& RegRex
))
3726 register_specifier
+= 8;
3727 /* The upper 16 registers are encoded in the fourth byte of the
3729 if (!(i
.vex
.register_specifier
->reg_flags
& RegVRex
))
3730 i
.vex
.bytes
[3] = 0x8;
3731 register_specifier
= ~register_specifier
& 0xf;
3735 register_specifier
= 0xf;
3737 /* Encode upper 16 vector index register in the fourth byte of
3739 if (!(i
.vrex
& REX_X
))
3740 i
.vex
.bytes
[3] = 0x8;
3745 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3750 case DATA_PREFIX_OPCODE
:
3753 case REPE_PREFIX_OPCODE
:
3756 case REPNE_PREFIX_OPCODE
:
3763 /* 4 byte EVEX prefix. */
3765 i
.vex
.bytes
[0] = 0x62;
3768 switch (i
.tm
.opcode_modifier
.vexopcode
)
3784 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3786 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3788 /* The fifth bit of the second EVEX byte is 1's compliment of the
3789 REX_R bit in VREX. */
3790 if (!(i
.vrex
& REX_R
))
3791 i
.vex
.bytes
[1] |= 0x10;
3795 if ((i
.reg_operands
+ i
.imm_operands
) == i
.operands
)
3797 /* When all operands are registers, the REX_X bit in REX is not
3798 used. We reuse it to encode the upper 16 registers, which is
3799 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3800 as 1's compliment. */
3801 if ((i
.vrex
& REX_B
))
3804 i
.vex
.bytes
[1] &= ~0x40;
3808 /* EVEX instructions shouldn't need the REX prefix. */
3809 i
.vrex
&= ~vrex_used
;
3810 gas_assert (i
.vrex
== 0);
3812 /* Check the REX.W bit and VEXW. */
3813 if (i
.tm
.opcode_modifier
.vexw
== VEXWIG
)
3814 w
= (evexwig
== evexw1
|| (i
.rex
& REX_W
)) ? 1 : 0;
3815 else if (i
.tm
.opcode_modifier
.vexw
)
3816 w
= i
.tm
.opcode_modifier
.vexw
== VEXW1
? 1 : 0;
3818 w
= (flag_code
== CODE_64BIT
? i
.rex
& REX_W
: evexwig
== evexw1
) ? 1 : 0;
3820 /* Encode the U bit. */
3821 implied_prefix
|= 0x4;
3823 /* The third byte of the EVEX prefix. */
3824 i
.vex
.bytes
[2] = (w
<< 7 | register_specifier
<< 3 | implied_prefix
);
3826 /* The fourth byte of the EVEX prefix. */
3827 /* The zeroing-masking bit. */
3828 if (i
.mask
&& i
.mask
->zeroing
)
3829 i
.vex
.bytes
[3] |= 0x80;
3831 /* Don't always set the broadcast bit if there is no RC. */
3834 /* Encode the vector length. */
3835 unsigned int vec_length
;
3837 if (!i
.tm
.opcode_modifier
.evex
3838 || i
.tm
.opcode_modifier
.evex
== EVEXDYN
)
3842 /* Determine vector length from the last multi-length vector
3845 for (op
= i
.operands
; op
--;)
3846 if (i
.tm
.operand_types
[op
].bitfield
.xmmword
3847 + i
.tm
.operand_types
[op
].bitfield
.ymmword
3848 + i
.tm
.operand_types
[op
].bitfield
.zmmword
> 1)
3850 if (i
.types
[op
].bitfield
.zmmword
)
3852 i
.tm
.opcode_modifier
.evex
= EVEX512
;
3855 else if (i
.types
[op
].bitfield
.ymmword
)
3857 i
.tm
.opcode_modifier
.evex
= EVEX256
;
3860 else if (i
.types
[op
].bitfield
.xmmword
)
3862 i
.tm
.opcode_modifier
.evex
= EVEX128
;
3865 else if (i
.broadcast
&& (int) op
== i
.broadcast
->operand
)
3867 switch (i
.broadcast
->bytes
)
3870 i
.tm
.opcode_modifier
.evex
= EVEX512
;
3873 i
.tm
.opcode_modifier
.evex
= EVEX256
;
3876 i
.tm
.opcode_modifier
.evex
= EVEX128
;
3885 if (op
>= MAX_OPERANDS
)
3889 switch (i
.tm
.opcode_modifier
.evex
)
3891 case EVEXLIG
: /* LL' is ignored */
3892 vec_length
= evexlig
<< 5;
3895 vec_length
= 0 << 5;
3898 vec_length
= 1 << 5;
3901 vec_length
= 2 << 5;
3907 i
.vex
.bytes
[3] |= vec_length
;
3908 /* Encode the broadcast bit. */
3910 i
.vex
.bytes
[3] |= 0x10;
3914 if (i
.rounding
->type
!= saeonly
)
3915 i
.vex
.bytes
[3] |= 0x10 | (i
.rounding
->type
<< 5);
3917 i
.vex
.bytes
[3] |= 0x10 | (evexrcig
<< 5);
3920 if (i
.mask
&& i
.mask
->mask
)
3921 i
.vex
.bytes
[3] |= i
.mask
->mask
->reg_num
;
3925 process_immext (void)
3929 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
3930 which is coded in the same place as an 8-bit immediate field
3931 would be. Here we fake an 8-bit immediate operand from the
3932 opcode suffix stored in tm.extension_opcode.
3934 AVX instructions also use this encoding, for some of
3935 3 argument instructions. */
3937 gas_assert (i
.imm_operands
<= 1
3939 || (is_any_vex_encoding (&i
.tm
)
3940 && i
.operands
<= 4)));
3942 exp
= &im_expressions
[i
.imm_operands
++];
3943 i
.op
[i
.operands
].imms
= exp
;
3944 i
.types
[i
.operands
] = imm8
;
3946 exp
->X_op
= O_constant
;
3947 exp
->X_add_number
= i
.tm
.extension_opcode
;
3948 i
.tm
.extension_opcode
= None
;
3955 switch (i
.tm
.opcode_modifier
.hleprefixok
)
3960 as_bad (_("invalid instruction `%s' after `%s'"),
3961 i
.tm
.name
, i
.hle_prefix
);
3964 if (i
.prefix
[LOCK_PREFIX
])
3966 as_bad (_("missing `lock' with `%s'"), i
.hle_prefix
);
3970 case HLEPrefixRelease
:
3971 if (i
.prefix
[HLE_PREFIX
] != XRELEASE_PREFIX_OPCODE
)
3973 as_bad (_("instruction `%s' after `xacquire' not allowed"),
3977 if (i
.mem_operands
== 0 || !(i
.flags
[i
.operands
- 1] & Operand_Mem
))
3979 as_bad (_("memory destination needed for instruction `%s'"
3980 " after `xrelease'"), i
.tm
.name
);
3987 /* Try the shortest encoding by shortening operand size. */
3990 optimize_encoding (void)
3994 if (optimize_for_space
3995 && !is_any_vex_encoding (&i
.tm
)
3996 && i
.reg_operands
== 1
3997 && i
.imm_operands
== 1
3998 && !i
.types
[1].bitfield
.byte
3999 && i
.op
[0].imms
->X_op
== O_constant
4000 && fits_in_imm7 (i
.op
[0].imms
->X_add_number
)
4001 && (i
.tm
.base_opcode
== 0xa8
4002 || (i
.tm
.base_opcode
== 0xf6
4003 && i
.tm
.extension_opcode
== 0x0)))
4006 test $imm7, %r64/%r32/%r16 -> test $imm7, %r8
4008 unsigned int base_regnum
= i
.op
[1].regs
->reg_num
;
4009 if (flag_code
== CODE_64BIT
|| base_regnum
< 4)
4011 i
.types
[1].bitfield
.byte
= 1;
4012 /* Ignore the suffix. */
4014 /* Convert to byte registers. */
4015 if (i
.types
[1].bitfield
.word
)
4017 else if (i
.types
[1].bitfield
.dword
)
4021 if (!(i
.op
[1].regs
->reg_flags
& RegRex
) && base_regnum
< 4)
4026 else if (flag_code
== CODE_64BIT
4027 && !is_any_vex_encoding (&i
.tm
)
4028 && ((i
.types
[1].bitfield
.qword
4029 && i
.reg_operands
== 1
4030 && i
.imm_operands
== 1
4031 && i
.op
[0].imms
->X_op
== O_constant
4032 && ((i
.tm
.base_opcode
== 0xb8
4033 && i
.tm
.extension_opcode
== None
4034 && fits_in_unsigned_long (i
.op
[0].imms
->X_add_number
))
4035 || (fits_in_imm31 (i
.op
[0].imms
->X_add_number
)
4036 && ((i
.tm
.base_opcode
== 0x24
4037 || i
.tm
.base_opcode
== 0xa8)
4038 || (i
.tm
.base_opcode
== 0x80
4039 && i
.tm
.extension_opcode
== 0x4)
4040 || ((i
.tm
.base_opcode
== 0xf6
4041 || (i
.tm
.base_opcode
| 1) == 0xc7)
4042 && i
.tm
.extension_opcode
== 0x0)))
4043 || (fits_in_imm7 (i
.op
[0].imms
->X_add_number
)
4044 && i
.tm
.base_opcode
== 0x83
4045 && i
.tm
.extension_opcode
== 0x4)))
4046 || (i
.types
[0].bitfield
.qword
4047 && ((i
.reg_operands
== 2
4048 && i
.op
[0].regs
== i
.op
[1].regs
4049 && (i
.tm
.base_opcode
== 0x30
4050 || i
.tm
.base_opcode
== 0x28))
4051 || (i
.reg_operands
== 1
4053 && i
.tm
.base_opcode
== 0x30)))))
4056 andq $imm31, %r64 -> andl $imm31, %r32
4057 andq $imm7, %r64 -> andl $imm7, %r32
4058 testq $imm31, %r64 -> testl $imm31, %r32
4059 xorq %r64, %r64 -> xorl %r32, %r32
4060 subq %r64, %r64 -> subl %r32, %r32
4061 movq $imm31, %r64 -> movl $imm31, %r32
4062 movq $imm32, %r64 -> movl $imm32, %r32
4064 i
.tm
.opcode_modifier
.norex64
= 1;
4065 if (i
.tm
.base_opcode
== 0xb8 || (i
.tm
.base_opcode
| 1) == 0xc7)
4068 movq $imm31, %r64 -> movl $imm31, %r32
4069 movq $imm32, %r64 -> movl $imm32, %r32
4071 i
.tm
.operand_types
[0].bitfield
.imm32
= 1;
4072 i
.tm
.operand_types
[0].bitfield
.imm32s
= 0;
4073 i
.tm
.operand_types
[0].bitfield
.imm64
= 0;
4074 i
.types
[0].bitfield
.imm32
= 1;
4075 i
.types
[0].bitfield
.imm32s
= 0;
4076 i
.types
[0].bitfield
.imm64
= 0;
4077 i
.types
[1].bitfield
.dword
= 1;
4078 i
.types
[1].bitfield
.qword
= 0;
4079 if ((i
.tm
.base_opcode
| 1) == 0xc7)
4082 movq $imm31, %r64 -> movl $imm31, %r32
4084 i
.tm
.base_opcode
= 0xb8;
4085 i
.tm
.extension_opcode
= None
;
4086 i
.tm
.opcode_modifier
.w
= 0;
4087 i
.tm
.opcode_modifier
.modrm
= 0;
4091 else if (optimize
> 1
4092 && !optimize_for_space
4093 && !is_any_vex_encoding (&i
.tm
)
4094 && i
.reg_operands
== 2
4095 && i
.op
[0].regs
== i
.op
[1].regs
4096 && ((i
.tm
.base_opcode
& ~(Opcode_D
| 1)) == 0x8
4097 || (i
.tm
.base_opcode
& ~(Opcode_D
| 1)) == 0x20)
4098 && (flag_code
!= CODE_64BIT
|| !i
.types
[0].bitfield
.dword
))
4101 andb %rN, %rN -> testb %rN, %rN
4102 andw %rN, %rN -> testw %rN, %rN
4103 andq %rN, %rN -> testq %rN, %rN
4104 orb %rN, %rN -> testb %rN, %rN
4105 orw %rN, %rN -> testw %rN, %rN
4106 orq %rN, %rN -> testq %rN, %rN
4108 and outside of 64-bit mode
4110 andl %rN, %rN -> testl %rN, %rN
4111 orl %rN, %rN -> testl %rN, %rN
4113 i
.tm
.base_opcode
= 0x84 | (i
.tm
.base_opcode
& 1);
4115 else if (i
.reg_operands
== 3
4116 && i
.op
[0].regs
== i
.op
[1].regs
4117 && !i
.types
[2].bitfield
.xmmword
4118 && (i
.tm
.opcode_modifier
.vex
4119 || ((!i
.mask
|| i
.mask
->zeroing
)
4121 && is_evex_encoding (&i
.tm
)
4122 && (i
.vec_encoding
!= vex_encoding_evex
4123 || cpu_arch_isa_flags
.bitfield
.cpuavx512vl
4124 || i
.tm
.cpu_flags
.bitfield
.cpuavx512vl
4125 || (i
.tm
.operand_types
[2].bitfield
.zmmword
4126 && i
.types
[2].bitfield
.ymmword
))))
4127 && ((i
.tm
.base_opcode
== 0x55
4128 || i
.tm
.base_opcode
== 0x6655
4129 || i
.tm
.base_opcode
== 0x66df
4130 || i
.tm
.base_opcode
== 0x57
4131 || i
.tm
.base_opcode
== 0x6657
4132 || i
.tm
.base_opcode
== 0x66ef
4133 || i
.tm
.base_opcode
== 0x66f8
4134 || i
.tm
.base_opcode
== 0x66f9
4135 || i
.tm
.base_opcode
== 0x66fa
4136 || i
.tm
.base_opcode
== 0x66fb
4137 || i
.tm
.base_opcode
== 0x42
4138 || i
.tm
.base_opcode
== 0x6642
4139 || i
.tm
.base_opcode
== 0x47
4140 || i
.tm
.base_opcode
== 0x6647)
4141 && i
.tm
.extension_opcode
== None
))
4144 VOP, one of vandnps, vandnpd, vxorps, vxorpd, vpsubb, vpsubd,
4146 EVEX VOP %zmmM, %zmmM, %zmmN
4147 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
4148 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4149 EVEX VOP %ymmM, %ymmM, %ymmN
4150 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
4151 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4152 VEX VOP %ymmM, %ymmM, %ymmN
4153 -> VEX VOP %xmmM, %xmmM, %xmmN
4154 VOP, one of vpandn and vpxor:
4155 VEX VOP %ymmM, %ymmM, %ymmN
4156 -> VEX VOP %xmmM, %xmmM, %xmmN
4157 VOP, one of vpandnd and vpandnq:
4158 EVEX VOP %zmmM, %zmmM, %zmmN
4159 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
4160 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4161 EVEX VOP %ymmM, %ymmM, %ymmN
4162 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
4163 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4164 VOP, one of vpxord and vpxorq:
4165 EVEX VOP %zmmM, %zmmM, %zmmN
4166 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
4167 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4168 EVEX VOP %ymmM, %ymmM, %ymmN
4169 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
4170 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4171 VOP, one of kxord and kxorq:
4172 VEX VOP %kM, %kM, %kN
4173 -> VEX kxorw %kM, %kM, %kN
4174 VOP, one of kandnd and kandnq:
4175 VEX VOP %kM, %kM, %kN
4176 -> VEX kandnw %kM, %kM, %kN
4178 if (is_evex_encoding (&i
.tm
))
4180 if (i
.vec_encoding
!= vex_encoding_evex
)
4182 i
.tm
.opcode_modifier
.vex
= VEX128
;
4183 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4184 i
.tm
.opcode_modifier
.evex
= 0;
4186 else if (optimize
> 1)
4187 i
.tm
.opcode_modifier
.evex
= EVEX128
;
4191 else if (i
.tm
.operand_types
[0].bitfield
.class == RegMask
)
4193 i
.tm
.base_opcode
&= 0xff;
4194 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4197 i
.tm
.opcode_modifier
.vex
= VEX128
;
4199 if (i
.tm
.opcode_modifier
.vex
)
4200 for (j
= 0; j
< 3; j
++)
4202 i
.types
[j
].bitfield
.xmmword
= 1;
4203 i
.types
[j
].bitfield
.ymmword
= 0;
4206 else if (i
.vec_encoding
!= vex_encoding_evex
4207 && !i
.types
[0].bitfield
.zmmword
4208 && !i
.types
[1].bitfield
.zmmword
4211 && is_evex_encoding (&i
.tm
)
4212 && ((i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0x666f
4213 || (i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0xf36f
4214 || (i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0xf26f
4215 || (i
.tm
.base_opcode
& ~4) == 0x66db
4216 || (i
.tm
.base_opcode
& ~4) == 0x66eb)
4217 && i
.tm
.extension_opcode
== None
)
4220 VOP, one of vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16,
4221 vmovdqu32 and vmovdqu64:
4222 EVEX VOP %xmmM, %xmmN
4223 -> VEX vmovdqa|vmovdqu %xmmM, %xmmN (M and N < 16)
4224 EVEX VOP %ymmM, %ymmN
4225 -> VEX vmovdqa|vmovdqu %ymmM, %ymmN (M and N < 16)
4227 -> VEX vmovdqa|vmovdqu %xmmM, mem (M < 16)
4229 -> VEX vmovdqa|vmovdqu %ymmM, mem (M < 16)
4231 -> VEX mvmovdqa|vmovdquem, %xmmN (N < 16)
4233 -> VEX vmovdqa|vmovdqu mem, %ymmN (N < 16)
4234 VOP, one of vpand, vpandn, vpor, vpxor:
4235 EVEX VOP{d,q} %xmmL, %xmmM, %xmmN
4236 -> VEX VOP %xmmL, %xmmM, %xmmN (L, M, and N < 16)
4237 EVEX VOP{d,q} %ymmL, %ymmM, %ymmN
4238 -> VEX VOP %ymmL, %ymmM, %ymmN (L, M, and N < 16)
4239 EVEX VOP{d,q} mem, %xmmM, %xmmN
4240 -> VEX VOP mem, %xmmM, %xmmN (M and N < 16)
4241 EVEX VOP{d,q} mem, %ymmM, %ymmN
4242 -> VEX VOP mem, %ymmM, %ymmN (M and N < 16)
4244 for (j
= 0; j
< i
.operands
; j
++)
4245 if (operand_type_check (i
.types
[j
], disp
)
4246 && i
.op
[j
].disps
->X_op
== O_constant
)
4248 /* Since the VEX prefix has 2 or 3 bytes, the EVEX prefix
4249 has 4 bytes, EVEX Disp8 has 1 byte and VEX Disp32 has 4
4250 bytes, we choose EVEX Disp8 over VEX Disp32. */
4251 int evex_disp8
, vex_disp8
;
4252 unsigned int memshift
= i
.memshift
;
4253 offsetT n
= i
.op
[j
].disps
->X_add_number
;
4255 evex_disp8
= fits_in_disp8 (n
);
4257 vex_disp8
= fits_in_disp8 (n
);
4258 if (evex_disp8
!= vex_disp8
)
4260 i
.memshift
= memshift
;
4264 i
.types
[j
].bitfield
.disp8
= vex_disp8
;
4267 if ((i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0xf26f)
4268 i
.tm
.base_opcode
^= 0xf36f ^ 0xf26f;
4269 i
.tm
.opcode_modifier
.vex
4270 = i
.types
[0].bitfield
.ymmword
? VEX256
: VEX128
;
4271 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4272 /* VPAND, VPOR, and VPXOR are commutative. */
4273 if (i
.reg_operands
== 3 && i
.tm
.base_opcode
!= 0x66df)
4274 i
.tm
.opcode_modifier
.commutative
= 1;
4275 i
.tm
.opcode_modifier
.evex
= 0;
4276 i
.tm
.opcode_modifier
.masking
= 0;
4277 i
.tm
.opcode_modifier
.broadcast
= 0;
4278 i
.tm
.opcode_modifier
.disp8memshift
= 0;
4281 i
.types
[j
].bitfield
.disp8
4282 = fits_in_disp8 (i
.op
[j
].disps
->X_add_number
);
4286 /* This is the guts of the machine-dependent assembler. LINE points to a
4287 machine dependent instruction. This function is supposed to emit
4288 the frags/bytes it assembles to. */
4291 md_assemble (char *line
)
4294 char mnemonic
[MAX_MNEM_SIZE
], mnem_suffix
;
4295 const insn_template
*t
;
4297 /* Initialize globals. */
4298 memset (&i
, '\0', sizeof (i
));
4299 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4300 i
.reloc
[j
] = NO_RELOC
;
4301 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
4302 memset (im_expressions
, '\0', sizeof (im_expressions
));
4303 save_stack_p
= save_stack
;
4305 /* First parse an instruction mnemonic & call i386_operand for the operands.
4306 We assume that the scrubber has arranged it so that line[0] is the valid
4307 start of a (possibly prefixed) mnemonic. */
4309 line
= parse_insn (line
, mnemonic
);
4312 mnem_suffix
= i
.suffix
;
4314 line
= parse_operands (line
, mnemonic
);
4316 xfree (i
.memop1_string
);
4317 i
.memop1_string
= NULL
;
4321 /* Now we've parsed the mnemonic into a set of templates, and have the
4322 operands at hand. */
4324 /* All intel opcodes have reversed operands except for "bound" and
4325 "enter". We also don't reverse intersegment "jmp" and "call"
4326 instructions with 2 immediate operands so that the immediate segment
4327 precedes the offset, as it does when in AT&T mode. */
4330 && (strcmp (mnemonic
, "bound") != 0)
4331 && (strcmp (mnemonic
, "invlpga") != 0)
4332 && !(operand_type_check (i
.types
[0], imm
)
4333 && operand_type_check (i
.types
[1], imm
)))
4336 /* The order of the immediates should be reversed
4337 for 2 immediates extrq and insertq instructions */
4338 if (i
.imm_operands
== 2
4339 && (strcmp (mnemonic
, "extrq") == 0
4340 || strcmp (mnemonic
, "insertq") == 0))
4341 swap_2_operands (0, 1);
4346 /* Don't optimize displacement for movabs since it only takes 64bit
4349 && i
.disp_encoding
!= disp_encoding_32bit
4350 && (flag_code
!= CODE_64BIT
4351 || strcmp (mnemonic
, "movabs") != 0))
4354 /* Next, we find a template that matches the given insn,
4355 making sure the overlap of the given operands types is consistent
4356 with the template operand types. */
4358 if (!(t
= match_template (mnem_suffix
)))
4361 if (sse_check
!= check_none
4362 && !i
.tm
.opcode_modifier
.noavx
4363 && !i
.tm
.cpu_flags
.bitfield
.cpuavx
4364 && !i
.tm
.cpu_flags
.bitfield
.cpuavx512f
4365 && (i
.tm
.cpu_flags
.bitfield
.cpusse
4366 || i
.tm
.cpu_flags
.bitfield
.cpusse2
4367 || i
.tm
.cpu_flags
.bitfield
.cpusse3
4368 || i
.tm
.cpu_flags
.bitfield
.cpussse3
4369 || i
.tm
.cpu_flags
.bitfield
.cpusse4_1
4370 || i
.tm
.cpu_flags
.bitfield
.cpusse4_2
4371 || i
.tm
.cpu_flags
.bitfield
.cpusse4a
4372 || i
.tm
.cpu_flags
.bitfield
.cpupclmul
4373 || i
.tm
.cpu_flags
.bitfield
.cpuaes
4374 || i
.tm
.cpu_flags
.bitfield
.cpusha
4375 || i
.tm
.cpu_flags
.bitfield
.cpugfni
))
4377 (sse_check
== check_warning
4379 : as_bad
) (_("SSE instruction `%s' is used"), i
.tm
.name
);
4382 /* Zap movzx and movsx suffix. The suffix has been set from
4383 "word ptr" or "byte ptr" on the source operand in Intel syntax
4384 or extracted from mnemonic in AT&T syntax. But we'll use
4385 the destination register to choose the suffix for encoding. */
4386 if ((i
.tm
.base_opcode
& ~9) == 0x0fb6)
4388 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
4389 there is no suffix, the default will be byte extension. */
4390 if (i
.reg_operands
!= 2
4393 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
4398 if (i
.tm
.opcode_modifier
.fwait
)
4399 if (!add_prefix (FWAIT_OPCODE
))
4402 /* Check if REP prefix is OK. */
4403 if (i
.rep_prefix
&& !i
.tm
.opcode_modifier
.repprefixok
)
4405 as_bad (_("invalid instruction `%s' after `%s'"),
4406 i
.tm
.name
, i
.rep_prefix
);
4410 /* Check for lock without a lockable instruction. Destination operand
4411 must be memory unless it is xchg (0x86). */
4412 if (i
.prefix
[LOCK_PREFIX
]
4413 && (!i
.tm
.opcode_modifier
.islockable
4414 || i
.mem_operands
== 0
4415 || (i
.tm
.base_opcode
!= 0x86
4416 && !(i
.flags
[i
.operands
- 1] & Operand_Mem
))))
4418 as_bad (_("expecting lockable instruction after `lock'"));
4422 /* Check for data size prefix on VEX/XOP/EVEX encoded insns. */
4423 if (i
.prefix
[DATA_PREFIX
] && is_any_vex_encoding (&i
.tm
))
4425 as_bad (_("data size prefix invalid with `%s'"), i
.tm
.name
);
4429 /* Check if HLE prefix is OK. */
4430 if (i
.hle_prefix
&& !check_hle ())
4433 /* Check BND prefix. */
4434 if (i
.bnd_prefix
&& !i
.tm
.opcode_modifier
.bndprefixok
)
4435 as_bad (_("expecting valid branch instruction after `bnd'"));
4437 /* Check NOTRACK prefix. */
4438 if (i
.notrack_prefix
&& !i
.tm
.opcode_modifier
.notrackprefixok
)
4439 as_bad (_("expecting indirect branch instruction after `notrack'"));
4441 if (i
.tm
.cpu_flags
.bitfield
.cpumpx
)
4443 if (flag_code
== CODE_64BIT
&& i
.prefix
[ADDR_PREFIX
])
4444 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
4445 else if (flag_code
!= CODE_16BIT
4446 ? i
.prefix
[ADDR_PREFIX
]
4447 : i
.mem_operands
&& !i
.prefix
[ADDR_PREFIX
])
4448 as_bad (_("16-bit address isn't allowed in MPX instructions"));
4451 /* Insert BND prefix. */
4452 if (add_bnd_prefix
&& i
.tm
.opcode_modifier
.bndprefixok
)
4454 if (!i
.prefix
[BND_PREFIX
])
4455 add_prefix (BND_PREFIX_OPCODE
);
4456 else if (i
.prefix
[BND_PREFIX
] != BND_PREFIX_OPCODE
)
4458 as_warn (_("replacing `rep'/`repe' prefix by `bnd'"));
4459 i
.prefix
[BND_PREFIX
] = BND_PREFIX_OPCODE
;
4463 /* Check string instruction segment overrides. */
4464 if (i
.tm
.opcode_modifier
.isstring
>= IS_STRING_ES_OP0
)
4466 gas_assert (i
.mem_operands
);
4467 if (!check_string ())
4469 i
.disp_operands
= 0;
4472 if (optimize
&& !i
.no_optimize
&& i
.tm
.opcode_modifier
.optimize
)
4473 optimize_encoding ();
4475 if (!process_suffix ())
4478 /* Update operand types. */
4479 for (j
= 0; j
< i
.operands
; j
++)
4480 i
.types
[j
] = operand_type_and (i
.types
[j
], i
.tm
.operand_types
[j
]);
4482 /* Make still unresolved immediate matches conform to size of immediate
4483 given in i.suffix. */
4484 if (!finalize_imm ())
4487 if (i
.types
[0].bitfield
.imm1
)
4488 i
.imm_operands
= 0; /* kludge for shift insns. */
4490 /* We only need to check those implicit registers for instructions
4491 with 3 operands or less. */
4492 if (i
.operands
<= 3)
4493 for (j
= 0; j
< i
.operands
; j
++)
4494 if (i
.types
[j
].bitfield
.instance
!= InstanceNone
4495 && !i
.types
[j
].bitfield
.xmmword
)
4498 /* ImmExt should be processed after SSE2AVX. */
4499 if (!i
.tm
.opcode_modifier
.sse2avx
4500 && i
.tm
.opcode_modifier
.immext
)
4503 /* For insns with operands there are more diddles to do to the opcode. */
4506 if (!process_operands ())
4509 else if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
4511 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
4512 as_warn (_("translating to `%sp'"), i
.tm
.name
);
4515 if (is_any_vex_encoding (&i
.tm
))
4517 if (!cpu_arch_flags
.bitfield
.cpui286
)
4519 as_bad (_("instruction `%s' isn't supported outside of protected mode."),
4524 if (i
.tm
.opcode_modifier
.vex
)
4525 build_vex_prefix (t
);
4527 build_evex_prefix ();
4530 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
4531 instructions may define INT_OPCODE as well, so avoid this corner
4532 case for those instructions that use MODRM. */
4533 if (i
.tm
.base_opcode
== INT_OPCODE
4534 && !i
.tm
.opcode_modifier
.modrm
4535 && i
.op
[0].imms
->X_add_number
== 3)
4537 i
.tm
.base_opcode
= INT3_OPCODE
;
4541 if ((i
.tm
.opcode_modifier
.jump
== JUMP
4542 || i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
4543 || i
.tm
.opcode_modifier
.jump
== JUMP_DWORD
)
4544 && i
.op
[0].disps
->X_op
== O_constant
)
4546 /* Convert "jmp constant" (and "call constant") to a jump (call) to
4547 the absolute address given by the constant. Since ix86 jumps and
4548 calls are pc relative, we need to generate a reloc. */
4549 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
4550 i
.op
[0].disps
->X_op
= O_symbol
;
4553 if (i
.tm
.opcode_modifier
.rex64
)
4556 /* For 8 bit registers we need an empty rex prefix. Also if the
4557 instruction already has a prefix, we need to convert old
4558 registers to new ones. */
4560 if ((i
.types
[0].bitfield
.class == Reg
&& i
.types
[0].bitfield
.byte
4561 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
4562 || (i
.types
[1].bitfield
.class == Reg
&& i
.types
[1].bitfield
.byte
4563 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
4564 || (((i
.types
[0].bitfield
.class == Reg
&& i
.types
[0].bitfield
.byte
)
4565 || (i
.types
[1].bitfield
.class == Reg
&& i
.types
[1].bitfield
.byte
))
4570 i
.rex
|= REX_OPCODE
;
4571 for (x
= 0; x
< 2; x
++)
4573 /* Look for 8 bit operand that uses old registers. */
4574 if (i
.types
[x
].bitfield
.class == Reg
&& i
.types
[x
].bitfield
.byte
4575 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
4577 gas_assert (!(i
.op
[x
].regs
->reg_flags
& RegRex
));
4578 /* In case it is "hi" register, give up. */
4579 if (i
.op
[x
].regs
->reg_num
> 3)
4580 as_bad (_("can't encode register '%s%s' in an "
4581 "instruction requiring REX prefix."),
4582 register_prefix
, i
.op
[x
].regs
->reg_name
);
4584 /* Otherwise it is equivalent to the extended register.
4585 Since the encoding doesn't change this is merely
4586 cosmetic cleanup for debug output. */
4588 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
4593 if (i
.rex
== 0 && i
.rex_encoding
)
4595 /* Check if we can add a REX_OPCODE byte. Look for 8 bit operand
4596 that uses legacy register. If it is "hi" register, don't add
4597 the REX_OPCODE byte. */
4599 for (x
= 0; x
< 2; x
++)
4600 if (i
.types
[x
].bitfield
.class == Reg
4601 && i
.types
[x
].bitfield
.byte
4602 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0
4603 && i
.op
[x
].regs
->reg_num
> 3)
4605 gas_assert (!(i
.op
[x
].regs
->reg_flags
& RegRex
));
4606 i
.rex_encoding
= FALSE
;
4615 add_prefix (REX_OPCODE
| i
.rex
);
4617 /* We are ready to output the insn. */
4620 last_insn
.seg
= now_seg
;
4622 if (i
.tm
.opcode_modifier
.isprefix
)
4624 last_insn
.kind
= last_insn_prefix
;
4625 last_insn
.name
= i
.tm
.name
;
4626 last_insn
.file
= as_where (&last_insn
.line
);
4629 last_insn
.kind
= last_insn_other
;
4633 parse_insn (char *line
, char *mnemonic
)
4636 char *token_start
= l
;
4639 const insn_template
*t
;
4645 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
4650 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
4652 as_bad (_("no such instruction: `%s'"), token_start
);
4657 if (!is_space_char (*l
)
4658 && *l
!= END_OF_INSN
4660 || (*l
!= PREFIX_SEPARATOR
4663 as_bad (_("invalid character %s in mnemonic"),
4664 output_invalid (*l
));
4667 if (token_start
== l
)
4669 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
4670 as_bad (_("expecting prefix; got nothing"));
4672 as_bad (_("expecting mnemonic; got nothing"));
4676 /* Look up instruction (or prefix) via hash table. */
4677 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
4679 if (*l
!= END_OF_INSN
4680 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
4681 && current_templates
4682 && current_templates
->start
->opcode_modifier
.isprefix
)
4684 if (!cpu_flags_check_cpu64 (current_templates
->start
->cpu_flags
))
4686 as_bad ((flag_code
!= CODE_64BIT
4687 ? _("`%s' is only supported in 64-bit mode")
4688 : _("`%s' is not supported in 64-bit mode")),
4689 current_templates
->start
->name
);
4692 /* If we are in 16-bit mode, do not allow addr16 or data16.
4693 Similarly, in 32-bit mode, do not allow addr32 or data32. */
4694 if ((current_templates
->start
->opcode_modifier
.size
== SIZE16
4695 || current_templates
->start
->opcode_modifier
.size
== SIZE32
)
4696 && flag_code
!= CODE_64BIT
4697 && ((current_templates
->start
->opcode_modifier
.size
== SIZE32
)
4698 ^ (flag_code
== CODE_16BIT
)))
4700 as_bad (_("redundant %s prefix"),
4701 current_templates
->start
->name
);
4704 if (current_templates
->start
->opcode_length
== 0)
4706 /* Handle pseudo prefixes. */
4707 switch (current_templates
->start
->base_opcode
)
4711 i
.disp_encoding
= disp_encoding_8bit
;
4715 i
.disp_encoding
= disp_encoding_32bit
;
4719 i
.dir_encoding
= dir_encoding_load
;
4723 i
.dir_encoding
= dir_encoding_store
;
4727 i
.vec_encoding
= vex_encoding_vex
;
4731 i
.vec_encoding
= vex_encoding_vex3
;
4735 i
.vec_encoding
= vex_encoding_evex
;
4739 i
.rex_encoding
= TRUE
;
4743 i
.no_optimize
= TRUE
;
4751 /* Add prefix, checking for repeated prefixes. */
4752 switch (add_prefix (current_templates
->start
->base_opcode
))
4757 if (current_templates
->start
->cpu_flags
.bitfield
.cpuibt
)
4758 i
.notrack_prefix
= current_templates
->start
->name
;
4761 if (current_templates
->start
->cpu_flags
.bitfield
.cpuhle
)
4762 i
.hle_prefix
= current_templates
->start
->name
;
4763 else if (current_templates
->start
->cpu_flags
.bitfield
.cpumpx
)
4764 i
.bnd_prefix
= current_templates
->start
->name
;
4766 i
.rep_prefix
= current_templates
->start
->name
;
4772 /* Skip past PREFIX_SEPARATOR and reset token_start. */
4779 if (!current_templates
)
4781 /* Deprecated functionality (new code should use pseudo-prefixes instead):
4782 Check if we should swap operand or force 32bit displacement in
4784 if (mnem_p
- 2 == dot_p
&& dot_p
[1] == 's')
4785 i
.dir_encoding
= dir_encoding_swap
;
4786 else if (mnem_p
- 3 == dot_p
4789 i
.disp_encoding
= disp_encoding_8bit
;
4790 else if (mnem_p
- 4 == dot_p
4794 i
.disp_encoding
= disp_encoding_32bit
;
4799 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
4802 if (!current_templates
)
4805 if (mnem_p
> mnemonic
)
4807 /* See if we can get a match by trimming off a suffix. */
4810 case WORD_MNEM_SUFFIX
:
4811 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
4812 i
.suffix
= SHORT_MNEM_SUFFIX
;
4815 case BYTE_MNEM_SUFFIX
:
4816 case QWORD_MNEM_SUFFIX
:
4817 i
.suffix
= mnem_p
[-1];
4819 current_templates
= (const templates
*) hash_find (op_hash
,
4822 case SHORT_MNEM_SUFFIX
:
4823 case LONG_MNEM_SUFFIX
:
4826 i
.suffix
= mnem_p
[-1];
4828 current_templates
= (const templates
*) hash_find (op_hash
,
4837 if (intel_float_operand (mnemonic
) == 1)
4838 i
.suffix
= SHORT_MNEM_SUFFIX
;
4840 i
.suffix
= LONG_MNEM_SUFFIX
;
4842 current_templates
= (const templates
*) hash_find (op_hash
,
4849 if (!current_templates
)
4851 as_bad (_("no such instruction: `%s'"), token_start
);
4856 if (current_templates
->start
->opcode_modifier
.jump
== JUMP
4857 || current_templates
->start
->opcode_modifier
.jump
== JUMP_BYTE
)
4859 /* Check for a branch hint. We allow ",pt" and ",pn" for
4860 predict taken and predict not taken respectively.
4861 I'm not sure that branch hints actually do anything on loop
4862 and jcxz insns (JumpByte) for current Pentium4 chips. They
4863 may work in the future and it doesn't hurt to accept them
4865 if (l
[0] == ',' && l
[1] == 'p')
4869 if (!add_prefix (DS_PREFIX_OPCODE
))
4873 else if (l
[2] == 'n')
4875 if (!add_prefix (CS_PREFIX_OPCODE
))
4881 /* Any other comma loses. */
4884 as_bad (_("invalid character %s in mnemonic"),
4885 output_invalid (*l
));
4889 /* Check if instruction is supported on specified architecture. */
4891 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
4893 supported
|= cpu_flags_match (t
);
4894 if (supported
== CPU_FLAGS_PERFECT_MATCH
)
4896 if (!cpu_arch_flags
.bitfield
.cpui386
&& (flag_code
!= CODE_16BIT
))
4897 as_warn (_("use .code16 to ensure correct addressing mode"));
4903 if (!(supported
& CPU_FLAGS_64BIT_MATCH
))
4904 as_bad (flag_code
== CODE_64BIT
4905 ? _("`%s' is not supported in 64-bit mode")
4906 : _("`%s' is only supported in 64-bit mode"),
4907 current_templates
->start
->name
);
4909 as_bad (_("`%s' is not supported on `%s%s'"),
4910 current_templates
->start
->name
,
4911 cpu_arch_name
? cpu_arch_name
: default_arch
,
4912 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
4918 parse_operands (char *l
, const char *mnemonic
)
4922 /* 1 if operand is pending after ','. */
4923 unsigned int expecting_operand
= 0;
4925 /* Non-zero if operand parens not balanced. */
4926 unsigned int paren_not_balanced
;
4928 while (*l
!= END_OF_INSN
)
4930 /* Skip optional white space before operand. */
4931 if (is_space_char (*l
))
4933 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
&& *l
!= '"')
4935 as_bad (_("invalid character %s before operand %d"),
4936 output_invalid (*l
),
4940 token_start
= l
; /* After white space. */
4941 paren_not_balanced
= 0;
4942 while (paren_not_balanced
|| *l
!= ',')
4944 if (*l
== END_OF_INSN
)
4946 if (paren_not_balanced
)
4949 as_bad (_("unbalanced parenthesis in operand %d."),
4952 as_bad (_("unbalanced brackets in operand %d."),
4957 break; /* we are done */
4959 else if (!is_operand_char (*l
) && !is_space_char (*l
) && *l
!= '"')
4961 as_bad (_("invalid character %s in operand %d"),
4962 output_invalid (*l
),
4969 ++paren_not_balanced
;
4971 --paren_not_balanced
;
4976 ++paren_not_balanced
;
4978 --paren_not_balanced
;
4982 if (l
!= token_start
)
4983 { /* Yes, we've read in another operand. */
4984 unsigned int operand_ok
;
4985 this_operand
= i
.operands
++;
4986 if (i
.operands
> MAX_OPERANDS
)
4988 as_bad (_("spurious operands; (%d operands/instruction max)"),
4992 i
.types
[this_operand
].bitfield
.unspecified
= 1;
4993 /* Now parse operand adding info to 'i' as we go along. */
4994 END_STRING_AND_SAVE (l
);
4996 if (i
.mem_operands
> 1)
4998 as_bad (_("too many memory references for `%s'"),
5005 i386_intel_operand (token_start
,
5006 intel_float_operand (mnemonic
));
5008 operand_ok
= i386_att_operand (token_start
);
5010 RESTORE_END_STRING (l
);
5016 if (expecting_operand
)
5018 expecting_operand_after_comma
:
5019 as_bad (_("expecting operand after ','; got nothing"));
5024 as_bad (_("expecting operand before ','; got nothing"));
5029 /* Now *l must be either ',' or END_OF_INSN. */
5032 if (*++l
== END_OF_INSN
)
5034 /* Just skip it, if it's \n complain. */
5035 goto expecting_operand_after_comma
;
5037 expecting_operand
= 1;
5044 swap_2_operands (int xchg1
, int xchg2
)
5046 union i386_op temp_op
;
5047 i386_operand_type temp_type
;
5048 unsigned int temp_flags
;
5049 enum bfd_reloc_code_real temp_reloc
;
5051 temp_type
= i
.types
[xchg2
];
5052 i
.types
[xchg2
] = i
.types
[xchg1
];
5053 i
.types
[xchg1
] = temp_type
;
5055 temp_flags
= i
.flags
[xchg2
];
5056 i
.flags
[xchg2
] = i
.flags
[xchg1
];
5057 i
.flags
[xchg1
] = temp_flags
;
5059 temp_op
= i
.op
[xchg2
];
5060 i
.op
[xchg2
] = i
.op
[xchg1
];
5061 i
.op
[xchg1
] = temp_op
;
5063 temp_reloc
= i
.reloc
[xchg2
];
5064 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
5065 i
.reloc
[xchg1
] = temp_reloc
;
5069 if (i
.mask
->operand
== xchg1
)
5070 i
.mask
->operand
= xchg2
;
5071 else if (i
.mask
->operand
== xchg2
)
5072 i
.mask
->operand
= xchg1
;
5076 if (i
.broadcast
->operand
== xchg1
)
5077 i
.broadcast
->operand
= xchg2
;
5078 else if (i
.broadcast
->operand
== xchg2
)
5079 i
.broadcast
->operand
= xchg1
;
5083 if (i
.rounding
->operand
== xchg1
)
5084 i
.rounding
->operand
= xchg2
;
5085 else if (i
.rounding
->operand
== xchg2
)
5086 i
.rounding
->operand
= xchg1
;
5091 swap_operands (void)
5097 swap_2_operands (1, i
.operands
- 2);
5101 swap_2_operands (0, i
.operands
- 1);
5107 if (i
.mem_operands
== 2)
5109 const seg_entry
*temp_seg
;
5110 temp_seg
= i
.seg
[0];
5111 i
.seg
[0] = i
.seg
[1];
5112 i
.seg
[1] = temp_seg
;
5116 /* Try to ensure constant immediates are represented in the smallest
5121 char guess_suffix
= 0;
5125 guess_suffix
= i
.suffix
;
5126 else if (i
.reg_operands
)
5128 /* Figure out a suffix from the last register operand specified.
5129 We can't do this properly yet, i.e. excluding special register
5130 instances, but the following works for instructions with
5131 immediates. In any case, we can't set i.suffix yet. */
5132 for (op
= i
.operands
; --op
>= 0;)
5133 if (i
.types
[op
].bitfield
.class != Reg
)
5135 else if (i
.types
[op
].bitfield
.byte
)
5137 guess_suffix
= BYTE_MNEM_SUFFIX
;
5140 else if (i
.types
[op
].bitfield
.word
)
5142 guess_suffix
= WORD_MNEM_SUFFIX
;
5145 else if (i
.types
[op
].bitfield
.dword
)
5147 guess_suffix
= LONG_MNEM_SUFFIX
;
5150 else if (i
.types
[op
].bitfield
.qword
)
5152 guess_suffix
= QWORD_MNEM_SUFFIX
;
5156 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
5157 guess_suffix
= WORD_MNEM_SUFFIX
;
5159 for (op
= i
.operands
; --op
>= 0;)
5160 if (operand_type_check (i
.types
[op
], imm
))
5162 switch (i
.op
[op
].imms
->X_op
)
5165 /* If a suffix is given, this operand may be shortened. */
5166 switch (guess_suffix
)
5168 case LONG_MNEM_SUFFIX
:
5169 i
.types
[op
].bitfield
.imm32
= 1;
5170 i
.types
[op
].bitfield
.imm64
= 1;
5172 case WORD_MNEM_SUFFIX
:
5173 i
.types
[op
].bitfield
.imm16
= 1;
5174 i
.types
[op
].bitfield
.imm32
= 1;
5175 i
.types
[op
].bitfield
.imm32s
= 1;
5176 i
.types
[op
].bitfield
.imm64
= 1;
5178 case BYTE_MNEM_SUFFIX
:
5179 i
.types
[op
].bitfield
.imm8
= 1;
5180 i
.types
[op
].bitfield
.imm8s
= 1;
5181 i
.types
[op
].bitfield
.imm16
= 1;
5182 i
.types
[op
].bitfield
.imm32
= 1;
5183 i
.types
[op
].bitfield
.imm32s
= 1;
5184 i
.types
[op
].bitfield
.imm64
= 1;
5188 /* If this operand is at most 16 bits, convert it
5189 to a signed 16 bit number before trying to see
5190 whether it will fit in an even smaller size.
5191 This allows a 16-bit operand such as $0xffe0 to
5192 be recognised as within Imm8S range. */
5193 if ((i
.types
[op
].bitfield
.imm16
)
5194 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
5196 i
.op
[op
].imms
->X_add_number
=
5197 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
5200 /* Store 32-bit immediate in 64-bit for 64-bit BFD. */
5201 if ((i
.types
[op
].bitfield
.imm32
)
5202 && ((i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1))
5205 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
5206 ^ ((offsetT
) 1 << 31))
5207 - ((offsetT
) 1 << 31));
5211 = operand_type_or (i
.types
[op
],
5212 smallest_imm_type (i
.op
[op
].imms
->X_add_number
));
5214 /* We must avoid matching of Imm32 templates when 64bit
5215 only immediate is available. */
5216 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
5217 i
.types
[op
].bitfield
.imm32
= 0;
5224 /* Symbols and expressions. */
5226 /* Convert symbolic operand to proper sizes for matching, but don't
5227 prevent matching a set of insns that only supports sizes other
5228 than those matching the insn suffix. */
5230 i386_operand_type mask
, allowed
;
5231 const insn_template
*t
;
5233 operand_type_set (&mask
, 0);
5234 operand_type_set (&allowed
, 0);
5236 for (t
= current_templates
->start
;
5237 t
< current_templates
->end
;
5240 allowed
= operand_type_or (allowed
, t
->operand_types
[op
]);
5241 allowed
= operand_type_and (allowed
, anyimm
);
5243 switch (guess_suffix
)
5245 case QWORD_MNEM_SUFFIX
:
5246 mask
.bitfield
.imm64
= 1;
5247 mask
.bitfield
.imm32s
= 1;
5249 case LONG_MNEM_SUFFIX
:
5250 mask
.bitfield
.imm32
= 1;
5252 case WORD_MNEM_SUFFIX
:
5253 mask
.bitfield
.imm16
= 1;
5255 case BYTE_MNEM_SUFFIX
:
5256 mask
.bitfield
.imm8
= 1;
5261 allowed
= operand_type_and (mask
, allowed
);
5262 if (!operand_type_all_zero (&allowed
))
5263 i
.types
[op
] = operand_type_and (i
.types
[op
], mask
);
5270 /* Try to use the smallest displacement type too. */
5272 optimize_disp (void)
5276 for (op
= i
.operands
; --op
>= 0;)
5277 if (operand_type_check (i
.types
[op
], disp
))
5279 if (i
.op
[op
].disps
->X_op
== O_constant
)
5281 offsetT op_disp
= i
.op
[op
].disps
->X_add_number
;
5283 if (i
.types
[op
].bitfield
.disp16
5284 && (op_disp
& ~(offsetT
) 0xffff) == 0)
5286 /* If this operand is at most 16 bits, convert
5287 to a signed 16 bit number and don't use 64bit
5289 op_disp
= (((op_disp
& 0xffff) ^ 0x8000) - 0x8000);
5290 i
.types
[op
].bitfield
.disp64
= 0;
5293 /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */
5294 if (i
.types
[op
].bitfield
.disp32
5295 && (op_disp
& ~(((offsetT
) 2 << 31) - 1)) == 0)
5297 /* If this operand is at most 32 bits, convert
5298 to a signed 32 bit number and don't use 64bit
5300 op_disp
&= (((offsetT
) 2 << 31) - 1);
5301 op_disp
= (op_disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
5302 i
.types
[op
].bitfield
.disp64
= 0;
5305 if (!op_disp
&& i
.types
[op
].bitfield
.baseindex
)
5307 i
.types
[op
].bitfield
.disp8
= 0;
5308 i
.types
[op
].bitfield
.disp16
= 0;
5309 i
.types
[op
].bitfield
.disp32
= 0;
5310 i
.types
[op
].bitfield
.disp32s
= 0;
5311 i
.types
[op
].bitfield
.disp64
= 0;
5315 else if (flag_code
== CODE_64BIT
)
5317 if (fits_in_signed_long (op_disp
))
5319 i
.types
[op
].bitfield
.disp64
= 0;
5320 i
.types
[op
].bitfield
.disp32s
= 1;
5322 if (i
.prefix
[ADDR_PREFIX
]
5323 && fits_in_unsigned_long (op_disp
))
5324 i
.types
[op
].bitfield
.disp32
= 1;
5326 if ((i
.types
[op
].bitfield
.disp32
5327 || i
.types
[op
].bitfield
.disp32s
5328 || i
.types
[op
].bitfield
.disp16
)
5329 && fits_in_disp8 (op_disp
))
5330 i
.types
[op
].bitfield
.disp8
= 1;
5332 else if (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
5333 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
)
5335 fix_new_exp (frag_now
, frag_more (0) - frag_now
->fr_literal
, 0,
5336 i
.op
[op
].disps
, 0, i
.reloc
[op
]);
5337 i
.types
[op
].bitfield
.disp8
= 0;
5338 i
.types
[op
].bitfield
.disp16
= 0;
5339 i
.types
[op
].bitfield
.disp32
= 0;
5340 i
.types
[op
].bitfield
.disp32s
= 0;
5341 i
.types
[op
].bitfield
.disp64
= 0;
5344 /* We only support 64bit displacement on constants. */
5345 i
.types
[op
].bitfield
.disp64
= 0;
5349 /* Return 1 if there is a match in broadcast bytes between operand
5350 GIVEN and instruction template T. */
5353 match_broadcast_size (const insn_template
*t
, unsigned int given
)
5355 return ((t
->opcode_modifier
.broadcast
== BYTE_BROADCAST
5356 && i
.types
[given
].bitfield
.byte
)
5357 || (t
->opcode_modifier
.broadcast
== WORD_BROADCAST
5358 && i
.types
[given
].bitfield
.word
)
5359 || (t
->opcode_modifier
.broadcast
== DWORD_BROADCAST
5360 && i
.types
[given
].bitfield
.dword
)
5361 || (t
->opcode_modifier
.broadcast
== QWORD_BROADCAST
5362 && i
.types
[given
].bitfield
.qword
));
5365 /* Check if operands are valid for the instruction. */
5368 check_VecOperands (const insn_template
*t
)
5373 /* Templates allowing for ZMMword as well as YMMword and/or XMMword for
5374 any one operand are implicity requiring AVX512VL support if the actual
5375 operand size is YMMword or XMMword. Since this function runs after
5376 template matching, there's no need to check for YMMword/XMMword in
5378 cpu
= cpu_flags_and (t
->cpu_flags
, avx512
);
5379 if (!cpu_flags_all_zero (&cpu
)
5380 && !t
->cpu_flags
.bitfield
.cpuavx512vl
5381 && !cpu_arch_flags
.bitfield
.cpuavx512vl
)
5383 for (op
= 0; op
< t
->operands
; ++op
)
5385 if (t
->operand_types
[op
].bitfield
.zmmword
5386 && (i
.types
[op
].bitfield
.ymmword
5387 || i
.types
[op
].bitfield
.xmmword
))
5389 i
.error
= unsupported
;
5395 /* Without VSIB byte, we can't have a vector register for index. */
5396 if (!t
->opcode_modifier
.vecsib
5398 && (i
.index_reg
->reg_type
.bitfield
.xmmword
5399 || i
.index_reg
->reg_type
.bitfield
.ymmword
5400 || i
.index_reg
->reg_type
.bitfield
.zmmword
))
5402 i
.error
= unsupported_vector_index_register
;
5406 /* Check if default mask is allowed. */
5407 if (t
->opcode_modifier
.nodefmask
5408 && (!i
.mask
|| i
.mask
->mask
->reg_num
== 0))
5410 i
.error
= no_default_mask
;
5414 /* For VSIB byte, we need a vector register for index, and all vector
5415 registers must be distinct. */
5416 if (t
->opcode_modifier
.vecsib
)
5419 || !((t
->opcode_modifier
.vecsib
== VecSIB128
5420 && i
.index_reg
->reg_type
.bitfield
.xmmword
)
5421 || (t
->opcode_modifier
.vecsib
== VecSIB256
5422 && i
.index_reg
->reg_type
.bitfield
.ymmword
)
5423 || (t
->opcode_modifier
.vecsib
== VecSIB512
5424 && i
.index_reg
->reg_type
.bitfield
.zmmword
)))
5426 i
.error
= invalid_vsib_address
;
5430 gas_assert (i
.reg_operands
== 2 || i
.mask
);
5431 if (i
.reg_operands
== 2 && !i
.mask
)
5433 gas_assert (i
.types
[0].bitfield
.class == RegSIMD
);
5434 gas_assert (i
.types
[0].bitfield
.xmmword
5435 || i
.types
[0].bitfield
.ymmword
);
5436 gas_assert (i
.types
[2].bitfield
.class == RegSIMD
);
5437 gas_assert (i
.types
[2].bitfield
.xmmword
5438 || i
.types
[2].bitfield
.ymmword
);
5439 if (operand_check
== check_none
)
5441 if (register_number (i
.op
[0].regs
)
5442 != register_number (i
.index_reg
)
5443 && register_number (i
.op
[2].regs
)
5444 != register_number (i
.index_reg
)
5445 && register_number (i
.op
[0].regs
)
5446 != register_number (i
.op
[2].regs
))
5448 if (operand_check
== check_error
)
5450 i
.error
= invalid_vector_register_set
;
5453 as_warn (_("mask, index, and destination registers should be distinct"));
5455 else if (i
.reg_operands
== 1 && i
.mask
)
5457 if (i
.types
[1].bitfield
.class == RegSIMD
5458 && (i
.types
[1].bitfield
.xmmword
5459 || i
.types
[1].bitfield
.ymmword
5460 || i
.types
[1].bitfield
.zmmword
)
5461 && (register_number (i
.op
[1].regs
)
5462 == register_number (i
.index_reg
)))
5464 if (operand_check
== check_error
)
5466 i
.error
= invalid_vector_register_set
;
5469 if (operand_check
!= check_none
)
5470 as_warn (_("index and destination registers should be distinct"));
5475 /* Check if broadcast is supported by the instruction and is applied
5476 to the memory operand. */
5479 i386_operand_type type
, overlap
;
5481 /* Check if specified broadcast is supported in this instruction,
5482 and its broadcast bytes match the memory operand. */
5483 op
= i
.broadcast
->operand
;
5484 if (!t
->opcode_modifier
.broadcast
5485 || !(i
.flags
[op
] & Operand_Mem
)
5486 || (!i
.types
[op
].bitfield
.unspecified
5487 && !match_broadcast_size (t
, op
)))
5490 i
.error
= unsupported_broadcast
;
5494 i
.broadcast
->bytes
= ((1 << (t
->opcode_modifier
.broadcast
- 1))
5495 * i
.broadcast
->type
);
5496 operand_type_set (&type
, 0);
5497 switch (i
.broadcast
->bytes
)
5500 type
.bitfield
.word
= 1;
5503 type
.bitfield
.dword
= 1;
5506 type
.bitfield
.qword
= 1;
5509 type
.bitfield
.xmmword
= 1;
5512 type
.bitfield
.ymmword
= 1;
5515 type
.bitfield
.zmmword
= 1;
5521 overlap
= operand_type_and (type
, t
->operand_types
[op
]);
5522 if (operand_type_all_zero (&overlap
))
5525 if (t
->opcode_modifier
.checkregsize
)
5529 type
.bitfield
.baseindex
= 1;
5530 for (j
= 0; j
< i
.operands
; ++j
)
5533 && !operand_type_register_match(i
.types
[j
],
5534 t
->operand_types
[j
],
5536 t
->operand_types
[op
]))
5541 /* If broadcast is supported in this instruction, we need to check if
5542 operand of one-element size isn't specified without broadcast. */
5543 else if (t
->opcode_modifier
.broadcast
&& i
.mem_operands
)
5545 /* Find memory operand. */
5546 for (op
= 0; op
< i
.operands
; op
++)
5547 if (i
.flags
[op
] & Operand_Mem
)
5549 gas_assert (op
< i
.operands
);
5550 /* Check size of the memory operand. */
5551 if (match_broadcast_size (t
, op
))
5553 i
.error
= broadcast_needed
;
5558 op
= MAX_OPERANDS
- 1; /* Avoid uninitialized variable warning. */
5560 /* Check if requested masking is supported. */
5563 switch (t
->opcode_modifier
.masking
)
5567 case MERGING_MASKING
:
5568 if (i
.mask
->zeroing
)
5571 i
.error
= unsupported_masking
;
5575 case DYNAMIC_MASKING
:
5576 /* Memory destinations allow only merging masking. */
5577 if (i
.mask
->zeroing
&& i
.mem_operands
)
5579 /* Find memory operand. */
5580 for (op
= 0; op
< i
.operands
; op
++)
5581 if (i
.flags
[op
] & Operand_Mem
)
5583 gas_assert (op
< i
.operands
);
5584 if (op
== i
.operands
- 1)
5586 i
.error
= unsupported_masking
;
5596 /* Check if masking is applied to dest operand. */
5597 if (i
.mask
&& (i
.mask
->operand
!= (int) (i
.operands
- 1)))
5599 i
.error
= mask_not_on_destination
;
5606 if (!t
->opcode_modifier
.sae
5607 || (i
.rounding
->type
!= saeonly
&& !t
->opcode_modifier
.staticrounding
))
5609 i
.error
= unsupported_rc_sae
;
5612 /* If the instruction has several immediate operands and one of
5613 them is rounding, the rounding operand should be the last
5614 immediate operand. */
5615 if (i
.imm_operands
> 1
5616 && i
.rounding
->operand
!= (int) (i
.imm_operands
- 1))
5618 i
.error
= rc_sae_operand_not_last_imm
;
5623 /* Check vector Disp8 operand. */
5624 if (t
->opcode_modifier
.disp8memshift
5625 && i
.disp_encoding
!= disp_encoding_32bit
)
5628 i
.memshift
= t
->opcode_modifier
.broadcast
- 1;
5629 else if (t
->opcode_modifier
.disp8memshift
!= DISP8_SHIFT_VL
)
5630 i
.memshift
= t
->opcode_modifier
.disp8memshift
;
5633 const i386_operand_type
*type
= NULL
;
5636 for (op
= 0; op
< i
.operands
; op
++)
5637 if (i
.flags
[op
] & Operand_Mem
)
5639 if (t
->opcode_modifier
.evex
== EVEXLIG
)
5640 i
.memshift
= 2 + (i
.suffix
== QWORD_MNEM_SUFFIX
);
5641 else if (t
->operand_types
[op
].bitfield
.xmmword
5642 + t
->operand_types
[op
].bitfield
.ymmword
5643 + t
->operand_types
[op
].bitfield
.zmmword
<= 1)
5644 type
= &t
->operand_types
[op
];
5645 else if (!i
.types
[op
].bitfield
.unspecified
)
5646 type
= &i
.types
[op
];
5648 else if (i
.types
[op
].bitfield
.class == RegSIMD
5649 && t
->opcode_modifier
.evex
!= EVEXLIG
)
5651 if (i
.types
[op
].bitfield
.zmmword
)
5653 else if (i
.types
[op
].bitfield
.ymmword
&& i
.memshift
< 5)
5655 else if (i
.types
[op
].bitfield
.xmmword
&& i
.memshift
< 4)
5661 if (type
->bitfield
.zmmword
)
5663 else if (type
->bitfield
.ymmword
)
5665 else if (type
->bitfield
.xmmword
)
5669 /* For the check in fits_in_disp8(). */
5670 if (i
.memshift
== 0)
5674 for (op
= 0; op
< i
.operands
; op
++)
5675 if (operand_type_check (i
.types
[op
], disp
)
5676 && i
.op
[op
].disps
->X_op
== O_constant
)
5678 if (fits_in_disp8 (i
.op
[op
].disps
->X_add_number
))
5680 i
.types
[op
].bitfield
.disp8
= 1;
5683 i
.types
[op
].bitfield
.disp8
= 0;
5692 /* Check if operands are valid for the instruction. Update VEX
5696 VEX_check_operands (const insn_template
*t
)
5698 if (i
.vec_encoding
== vex_encoding_evex
)
5700 /* This instruction must be encoded with EVEX prefix. */
5701 if (!is_evex_encoding (t
))
5703 i
.error
= unsupported
;
5709 if (!t
->opcode_modifier
.vex
)
5711 /* This instruction template doesn't have VEX prefix. */
5712 if (i
.vec_encoding
!= vex_encoding_default
)
5714 i
.error
= unsupported
;
5720 /* Check the special Imm4 cases; must be the first operand. */
5721 if (t
->cpu_flags
.bitfield
.cpuxop
&& t
->operands
== 5)
5723 if (i
.op
[0].imms
->X_op
!= O_constant
5724 || !fits_in_imm4 (i
.op
[0].imms
->X_add_number
))
5730 /* Turn off Imm<N> so that update_imm won't complain. */
5731 operand_type_set (&i
.types
[0], 0);
5737 static const insn_template
*
5738 match_template (char mnem_suffix
)
5740 /* Points to template once we've found it. */
5741 const insn_template
*t
;
5742 i386_operand_type overlap0
, overlap1
, overlap2
, overlap3
;
5743 i386_operand_type overlap4
;
5744 unsigned int found_reverse_match
;
5745 i386_opcode_modifier suffix_check
;
5746 i386_operand_type operand_types
[MAX_OPERANDS
];
5747 int addr_prefix_disp
;
5748 unsigned int j
, size_match
, check_register
;
5749 enum i386_error specific_error
= 0;
5751 #if MAX_OPERANDS != 5
5752 # error "MAX_OPERANDS must be 5."
5755 found_reverse_match
= 0;
5756 addr_prefix_disp
= -1;
5758 /* Prepare for mnemonic suffix check. */
5759 memset (&suffix_check
, 0, sizeof (suffix_check
));
5760 switch (mnem_suffix
)
5762 case BYTE_MNEM_SUFFIX
:
5763 suffix_check
.no_bsuf
= 1;
5765 case WORD_MNEM_SUFFIX
:
5766 suffix_check
.no_wsuf
= 1;
5768 case SHORT_MNEM_SUFFIX
:
5769 suffix_check
.no_ssuf
= 1;
5771 case LONG_MNEM_SUFFIX
:
5772 suffix_check
.no_lsuf
= 1;
5774 case QWORD_MNEM_SUFFIX
:
5775 suffix_check
.no_qsuf
= 1;
5778 /* NB: In Intel syntax, normally we can check for memory operand
5779 size when there is no mnemonic suffix. But jmp and call have
5780 2 different encodings with Dword memory operand size, one with
5781 No_ldSuf and the other without. i.suffix is set to
5782 LONG_DOUBLE_MNEM_SUFFIX to skip the one with No_ldSuf. */
5783 if (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
)
5784 suffix_check
.no_ldsuf
= 1;
5787 /* Must have right number of operands. */
5788 i
.error
= number_of_operands_mismatch
;
5790 for (t
= current_templates
->start
; t
< current_templates
->end
; t
++)
5792 addr_prefix_disp
= -1;
5793 found_reverse_match
= 0;
5795 if (i
.operands
!= t
->operands
)
5798 /* Check processor support. */
5799 i
.error
= unsupported
;
5800 if (cpu_flags_match (t
) != CPU_FLAGS_PERFECT_MATCH
)
5803 /* Check AT&T mnemonic. */
5804 i
.error
= unsupported_with_intel_mnemonic
;
5805 if (intel_mnemonic
&& t
->opcode_modifier
.attmnemonic
)
5808 /* Check AT&T/Intel syntax. */
5809 i
.error
= unsupported_syntax
;
5810 if ((intel_syntax
&& t
->opcode_modifier
.attsyntax
)
5811 || (!intel_syntax
&& t
->opcode_modifier
.intelsyntax
))
5814 /* Check Intel64/AMD64 ISA. */
5818 /* Default: Don't accept Intel64. */
5819 if (t
->opcode_modifier
.isa64
== INTEL64
)
5823 /* -mamd64: Don't accept Intel64 and Intel64 only. */
5824 if (t
->opcode_modifier
.isa64
>= INTEL64
)
5828 /* -mintel64: Don't accept AMD64. */
5829 if (t
->opcode_modifier
.isa64
== AMD64
&& flag_code
== CODE_64BIT
)
5834 /* Check the suffix. */
5835 i
.error
= invalid_instruction_suffix
;
5836 if ((t
->opcode_modifier
.no_bsuf
&& suffix_check
.no_bsuf
)
5837 || (t
->opcode_modifier
.no_wsuf
&& suffix_check
.no_wsuf
)
5838 || (t
->opcode_modifier
.no_lsuf
&& suffix_check
.no_lsuf
)
5839 || (t
->opcode_modifier
.no_ssuf
&& suffix_check
.no_ssuf
)
5840 || (t
->opcode_modifier
.no_qsuf
&& suffix_check
.no_qsuf
)
5841 || (t
->opcode_modifier
.no_ldsuf
&& suffix_check
.no_ldsuf
))
5844 size_match
= operand_size_match (t
);
5848 /* This is intentionally not
5850 if (i.jumpabsolute != (t->opcode_modifier.jump == JUMP_ABSOLUTE))
5852 as the case of a missing * on the operand is accepted (perhaps with
5853 a warning, issued further down). */
5854 if (i
.jumpabsolute
&& t
->opcode_modifier
.jump
!= JUMP_ABSOLUTE
)
5856 i
.error
= operand_type_mismatch
;
5860 for (j
= 0; j
< MAX_OPERANDS
; j
++)
5861 operand_types
[j
] = t
->operand_types
[j
];
5863 /* In general, don't allow 64-bit operands in 32-bit mode. */
5864 if (i
.suffix
== QWORD_MNEM_SUFFIX
5865 && flag_code
!= CODE_64BIT
5867 ? (!t
->opcode_modifier
.ignoresize
5868 && !t
->opcode_modifier
.broadcast
5869 && !intel_float_operand (t
->name
))
5870 : intel_float_operand (t
->name
) != 2)
5871 && ((operand_types
[0].bitfield
.class != RegMMX
5872 && operand_types
[0].bitfield
.class != RegSIMD
)
5873 || (operand_types
[t
->operands
> 1].bitfield
.class != RegMMX
5874 && operand_types
[t
->operands
> 1].bitfield
.class != RegSIMD
))
5875 && (t
->base_opcode
!= 0x0fc7
5876 || t
->extension_opcode
!= 1 /* cmpxchg8b */))
5879 /* In general, don't allow 32-bit operands on pre-386. */
5880 else if (i
.suffix
== LONG_MNEM_SUFFIX
5881 && !cpu_arch_flags
.bitfield
.cpui386
5883 ? (!t
->opcode_modifier
.ignoresize
5884 && !intel_float_operand (t
->name
))
5885 : intel_float_operand (t
->name
) != 2)
5886 && ((operand_types
[0].bitfield
.class != RegMMX
5887 && operand_types
[0].bitfield
.class != RegSIMD
)
5888 || (operand_types
[t
->operands
> 1].bitfield
.class != RegMMX
5889 && operand_types
[t
->operands
> 1].bitfield
.class
5893 /* Do not verify operands when there are none. */
5897 /* We've found a match; break out of loop. */
5901 if (!t
->opcode_modifier
.jump
5902 || t
->opcode_modifier
.jump
== JUMP_ABSOLUTE
)
5904 /* There should be only one Disp operand. */
5905 for (j
= 0; j
< MAX_OPERANDS
; j
++)
5906 if (operand_type_check (operand_types
[j
], disp
))
5908 if (j
< MAX_OPERANDS
)
5910 bfd_boolean override
= (i
.prefix
[ADDR_PREFIX
] != 0);
5912 addr_prefix_disp
= j
;
5914 /* Address size prefix will turn Disp64/Disp32S/Disp32/Disp16
5915 operand into Disp32/Disp32/Disp16/Disp32 operand. */
5919 override
= !override
;
5922 if (operand_types
[j
].bitfield
.disp32
5923 && operand_types
[j
].bitfield
.disp16
)
5925 operand_types
[j
].bitfield
.disp16
= override
;
5926 operand_types
[j
].bitfield
.disp32
= !override
;
5928 operand_types
[j
].bitfield
.disp32s
= 0;
5929 operand_types
[j
].bitfield
.disp64
= 0;
5933 if (operand_types
[j
].bitfield
.disp32s
5934 || operand_types
[j
].bitfield
.disp64
)
5936 operand_types
[j
].bitfield
.disp64
&= !override
;
5937 operand_types
[j
].bitfield
.disp32s
&= !override
;
5938 operand_types
[j
].bitfield
.disp32
= override
;
5940 operand_types
[j
].bitfield
.disp16
= 0;
5946 /* Force 0x8b encoding for "mov foo@GOT, %eax". */
5947 if (i
.reloc
[0] == BFD_RELOC_386_GOT32
&& t
->base_opcode
== 0xa0)
5950 /* We check register size if needed. */
5951 if (t
->opcode_modifier
.checkregsize
)
5953 check_register
= (1 << t
->operands
) - 1;
5955 check_register
&= ~(1 << i
.broadcast
->operand
);
5960 overlap0
= operand_type_and (i
.types
[0], operand_types
[0]);
5961 switch (t
->operands
)
5964 if (!operand_type_match (overlap0
, i
.types
[0]))
5968 /* xchg %eax, %eax is a special case. It is an alias for nop
5969 only in 32bit mode and we can use opcode 0x90. In 64bit
5970 mode, we can't use 0x90 for xchg %eax, %eax since it should
5971 zero-extend %eax to %rax. */
5972 if (flag_code
== CODE_64BIT
5973 && t
->base_opcode
== 0x90
5974 && i
.types
[0].bitfield
.instance
== Accum
5975 && i
.types
[0].bitfield
.dword
5976 && i
.types
[1].bitfield
.instance
== Accum
5977 && i
.types
[1].bitfield
.dword
)
5979 /* xrelease mov %eax, <disp> is another special case. It must not
5980 match the accumulator-only encoding of mov. */
5981 if (flag_code
!= CODE_64BIT
5983 && t
->base_opcode
== 0xa0
5984 && i
.types
[0].bitfield
.instance
== Accum
5985 && (i
.flags
[1] & Operand_Mem
))
5990 if (!(size_match
& MATCH_STRAIGHT
))
5992 /* Reverse direction of operands if swapping is possible in the first
5993 place (operands need to be symmetric) and
5994 - the load form is requested, and the template is a store form,
5995 - the store form is requested, and the template is a load form,
5996 - the non-default (swapped) form is requested. */
5997 overlap1
= operand_type_and (operand_types
[0], operand_types
[1]);
5998 if (t
->opcode_modifier
.d
&& i
.reg_operands
== i
.operands
5999 && !operand_type_all_zero (&overlap1
))
6000 switch (i
.dir_encoding
)
6002 case dir_encoding_load
:
6003 if (operand_type_check (operand_types
[i
.operands
- 1], anymem
)
6004 || t
->opcode_modifier
.regmem
)
6008 case dir_encoding_store
:
6009 if (!operand_type_check (operand_types
[i
.operands
- 1], anymem
)
6010 && !t
->opcode_modifier
.regmem
)
6014 case dir_encoding_swap
:
6017 case dir_encoding_default
:
6020 /* If we want store form, we skip the current load. */
6021 if ((i
.dir_encoding
== dir_encoding_store
6022 || i
.dir_encoding
== dir_encoding_swap
)
6023 && i
.mem_operands
== 0
6024 && t
->opcode_modifier
.load
)
6029 overlap1
= operand_type_and (i
.types
[1], operand_types
[1]);
6030 if (!operand_type_match (overlap0
, i
.types
[0])
6031 || !operand_type_match (overlap1
, i
.types
[1])
6032 || ((check_register
& 3) == 3
6033 && !operand_type_register_match (i
.types
[0],
6038 /* Check if other direction is valid ... */
6039 if (!t
->opcode_modifier
.d
)
6043 if (!(size_match
& MATCH_REVERSE
))
6045 /* Try reversing direction of operands. */
6046 overlap0
= operand_type_and (i
.types
[0], operand_types
[i
.operands
- 1]);
6047 overlap1
= operand_type_and (i
.types
[i
.operands
- 1], operand_types
[0]);
6048 if (!operand_type_match (overlap0
, i
.types
[0])
6049 || !operand_type_match (overlap1
, i
.types
[i
.operands
- 1])
6051 && !operand_type_register_match (i
.types
[0],
6052 operand_types
[i
.operands
- 1],
6053 i
.types
[i
.operands
- 1],
6056 /* Does not match either direction. */
6059 /* found_reverse_match holds which of D or FloatR
6061 if (!t
->opcode_modifier
.d
)
6062 found_reverse_match
= 0;
6063 else if (operand_types
[0].bitfield
.tbyte
)
6064 found_reverse_match
= Opcode_FloatD
;
6065 else if (operand_types
[0].bitfield
.xmmword
6066 || operand_types
[i
.operands
- 1].bitfield
.xmmword
6067 || operand_types
[0].bitfield
.class == RegMMX
6068 || operand_types
[i
.operands
- 1].bitfield
.class == RegMMX
6069 || is_any_vex_encoding(t
))
6070 found_reverse_match
= (t
->base_opcode
& 0xee) != 0x6e
6071 ? Opcode_SIMD_FloatD
: Opcode_SIMD_IntD
;
6073 found_reverse_match
= Opcode_D
;
6074 if (t
->opcode_modifier
.floatr
)
6075 found_reverse_match
|= Opcode_FloatR
;
6079 /* Found a forward 2 operand match here. */
6080 switch (t
->operands
)
6083 overlap4
= operand_type_and (i
.types
[4],
6087 overlap3
= operand_type_and (i
.types
[3],
6091 overlap2
= operand_type_and (i
.types
[2],
6096 switch (t
->operands
)
6099 if (!operand_type_match (overlap4
, i
.types
[4])
6100 || !operand_type_register_match (i
.types
[3],
6107 if (!operand_type_match (overlap3
, i
.types
[3])
6108 || ((check_register
& 0xa) == 0xa
6109 && !operand_type_register_match (i
.types
[1],
6113 || ((check_register
& 0xc) == 0xc
6114 && !operand_type_register_match (i
.types
[2],
6121 /* Here we make use of the fact that there are no
6122 reverse match 3 operand instructions. */
6123 if (!operand_type_match (overlap2
, i
.types
[2])
6124 || ((check_register
& 5) == 5
6125 && !operand_type_register_match (i
.types
[0],
6129 || ((check_register
& 6) == 6
6130 && !operand_type_register_match (i
.types
[1],
6138 /* Found either forward/reverse 2, 3 or 4 operand match here:
6139 slip through to break. */
6142 /* Check if vector and VEX operands are valid. */
6143 if (check_VecOperands (t
) || VEX_check_operands (t
))
6145 specific_error
= i
.error
;
6149 /* We've found a match; break out of loop. */
6153 if (t
== current_templates
->end
)
6155 /* We found no match. */
6156 const char *err_msg
;
6157 switch (specific_error
? specific_error
: i
.error
)
6161 case operand_size_mismatch
:
6162 err_msg
= _("operand size mismatch");
6164 case operand_type_mismatch
:
6165 err_msg
= _("operand type mismatch");
6167 case register_type_mismatch
:
6168 err_msg
= _("register type mismatch");
6170 case number_of_operands_mismatch
:
6171 err_msg
= _("number of operands mismatch");
6173 case invalid_instruction_suffix
:
6174 err_msg
= _("invalid instruction suffix");
6177 err_msg
= _("constant doesn't fit in 4 bits");
6179 case unsupported_with_intel_mnemonic
:
6180 err_msg
= _("unsupported with Intel mnemonic");
6182 case unsupported_syntax
:
6183 err_msg
= _("unsupported syntax");
6186 as_bad (_("unsupported instruction `%s'"),
6187 current_templates
->start
->name
);
6189 case invalid_vsib_address
:
6190 err_msg
= _("invalid VSIB address");
6192 case invalid_vector_register_set
:
6193 err_msg
= _("mask, index, and destination registers must be distinct");
6195 case unsupported_vector_index_register
:
6196 err_msg
= _("unsupported vector index register");
6198 case unsupported_broadcast
:
6199 err_msg
= _("unsupported broadcast");
6201 case broadcast_needed
:
6202 err_msg
= _("broadcast is needed for operand of such type");
6204 case unsupported_masking
:
6205 err_msg
= _("unsupported masking");
6207 case mask_not_on_destination
:
6208 err_msg
= _("mask not on destination operand");
6210 case no_default_mask
:
6211 err_msg
= _("default mask isn't allowed");
6213 case unsupported_rc_sae
:
6214 err_msg
= _("unsupported static rounding/sae");
6216 case rc_sae_operand_not_last_imm
:
6218 err_msg
= _("RC/SAE operand must precede immediate operands");
6220 err_msg
= _("RC/SAE operand must follow immediate operands");
6222 case invalid_register_operand
:
6223 err_msg
= _("invalid register operand");
6226 as_bad (_("%s for `%s'"), err_msg
,
6227 current_templates
->start
->name
);
6231 if (!quiet_warnings
)
6234 && (i
.jumpabsolute
!= (t
->opcode_modifier
.jump
== JUMP_ABSOLUTE
)))
6235 as_warn (_("indirect %s without `*'"), t
->name
);
6237 if (t
->opcode_modifier
.isprefix
6238 && t
->opcode_modifier
.ignoresize
)
6240 /* Warn them that a data or address size prefix doesn't
6241 affect assembly of the next line of code. */
6242 as_warn (_("stand-alone `%s' prefix"), t
->name
);
6246 /* Copy the template we found. */
6249 if (addr_prefix_disp
!= -1)
6250 i
.tm
.operand_types
[addr_prefix_disp
]
6251 = operand_types
[addr_prefix_disp
];
6253 if (found_reverse_match
)
6255 /* If we found a reverse match we must alter the opcode direction
6256 bit and clear/flip the regmem modifier one. found_reverse_match
6257 holds bits to change (different for int & float insns). */
6259 i
.tm
.base_opcode
^= found_reverse_match
;
6261 i
.tm
.operand_types
[0] = operand_types
[i
.operands
- 1];
6262 i
.tm
.operand_types
[i
.operands
- 1] = operand_types
[0];
6264 /* Certain SIMD insns have their load forms specified in the opcode
6265 table, and hence we need to _set_ RegMem instead of clearing it.
6266 We need to avoid setting the bit though on insns like KMOVW. */
6267 i
.tm
.opcode_modifier
.regmem
6268 = i
.tm
.opcode_modifier
.modrm
&& i
.tm
.opcode_modifier
.d
6269 && i
.tm
.operands
> 2U - i
.tm
.opcode_modifier
.sse2avx
6270 && !i
.tm
.opcode_modifier
.regmem
;
6279 unsigned int es_op
= i
.tm
.opcode_modifier
.isstring
- IS_STRING_ES_OP0
;
6280 unsigned int op
= i
.tm
.operand_types
[0].bitfield
.baseindex
? es_op
: 0;
6282 if (i
.seg
[op
] != NULL
&& i
.seg
[op
] != &es
)
6284 as_bad (_("`%s' operand %u must use `%ses' segment"),
6286 intel_syntax
? i
.tm
.operands
- es_op
: es_op
+ 1,
6291 /* There's only ever one segment override allowed per instruction.
6292 This instruction possibly has a legal segment override on the
6293 second operand, so copy the segment to where non-string
6294 instructions store it, allowing common code. */
6295 i
.seg
[op
] = i
.seg
[1];
6301 process_suffix (void)
6303 /* If matched instruction specifies an explicit instruction mnemonic
6305 if (i
.tm
.opcode_modifier
.size
== SIZE16
)
6306 i
.suffix
= WORD_MNEM_SUFFIX
;
6307 else if (i
.tm
.opcode_modifier
.size
== SIZE32
)
6308 i
.suffix
= LONG_MNEM_SUFFIX
;
6309 else if (i
.tm
.opcode_modifier
.size
== SIZE64
)
6310 i
.suffix
= QWORD_MNEM_SUFFIX
;
6311 else if (i
.reg_operands
6312 && (i
.operands
> 1 || i
.types
[0].bitfield
.class == Reg
))
6314 /* If there's no instruction mnemonic suffix we try to invent one
6315 based on GPR operands. */
6318 /* We take i.suffix from the last register operand specified,
6319 Destination register type is more significant than source
6320 register type. crc32 in SSE4.2 prefers source register
6322 unsigned int op
= i
.tm
.base_opcode
!= 0xf20f38f0 ? i
.operands
: 1;
6325 if (i
.tm
.operand_types
[op
].bitfield
.instance
== InstanceNone
6326 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
6328 if (i
.types
[op
].bitfield
.class != Reg
)
6330 if (i
.types
[op
].bitfield
.byte
)
6331 i
.suffix
= BYTE_MNEM_SUFFIX
;
6332 else if (i
.types
[op
].bitfield
.word
)
6333 i
.suffix
= WORD_MNEM_SUFFIX
;
6334 else if (i
.types
[op
].bitfield
.dword
)
6335 i
.suffix
= LONG_MNEM_SUFFIX
;
6336 else if (i
.types
[op
].bitfield
.qword
)
6337 i
.suffix
= QWORD_MNEM_SUFFIX
;
6343 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
6346 && i
.tm
.opcode_modifier
.ignoresize
6347 && i
.tm
.opcode_modifier
.no_bsuf
)
6349 else if (!check_byte_reg ())
6352 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
6355 && i
.tm
.opcode_modifier
.ignoresize
6356 && i
.tm
.opcode_modifier
.no_lsuf
6357 && !i
.tm
.opcode_modifier
.todword
6358 && !i
.tm
.opcode_modifier
.toqword
)
6360 else if (!check_long_reg ())
6363 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
6366 && i
.tm
.opcode_modifier
.ignoresize
6367 && i
.tm
.opcode_modifier
.no_qsuf
6368 && !i
.tm
.opcode_modifier
.todword
6369 && !i
.tm
.opcode_modifier
.toqword
)
6371 else if (!check_qword_reg ())
6374 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
6377 && i
.tm
.opcode_modifier
.ignoresize
6378 && i
.tm
.opcode_modifier
.no_wsuf
)
6380 else if (!check_word_reg ())
6383 else if (intel_syntax
&& i
.tm
.opcode_modifier
.ignoresize
)
6384 /* Do nothing if the instruction is going to ignore the prefix. */
6389 else if (i
.tm
.opcode_modifier
.defaultsize
&& !i
.suffix
)
6391 i
.suffix
= stackop_size
;
6392 if (stackop_size
== LONG_MNEM_SUFFIX
)
6394 /* stackop_size is set to LONG_MNEM_SUFFIX for the
6395 .code16gcc directive to support 16-bit mode with
6396 32-bit address. For IRET without a suffix, generate
6397 16-bit IRET (opcode 0xcf) to return from an interrupt
6399 if (i
.tm
.base_opcode
== 0xcf)
6401 i
.suffix
= WORD_MNEM_SUFFIX
;
6402 as_warn (_("generating 16-bit `iret' for .code16gcc directive"));
6404 /* Warn about changed behavior for segment register push/pop. */
6405 else if ((i
.tm
.base_opcode
| 1) == 0x07)
6406 as_warn (_("generating 32-bit `%s', unlike earlier gas versions"),
6411 && (i
.tm
.opcode_modifier
.jump
== JUMP_ABSOLUTE
6412 || i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
6413 || i
.tm
.opcode_modifier
.jump
== JUMP_INTERSEGMENT
6414 || (i
.tm
.base_opcode
== 0x0f01 /* [ls][gi]dt */
6415 && i
.tm
.extension_opcode
<= 3)))
6420 if (!i
.tm
.opcode_modifier
.no_qsuf
)
6422 i
.suffix
= QWORD_MNEM_SUFFIX
;
6427 if (!i
.tm
.opcode_modifier
.no_lsuf
)
6428 i
.suffix
= LONG_MNEM_SUFFIX
;
6431 if (!i
.tm
.opcode_modifier
.no_wsuf
)
6432 i
.suffix
= WORD_MNEM_SUFFIX
;
6438 && (!i
.tm
.opcode_modifier
.defaultsize
6439 /* Also cover lret/retf/iret in 64-bit mode. */
6440 || (flag_code
== CODE_64BIT
6441 && !i
.tm
.opcode_modifier
.no_lsuf
6442 && !i
.tm
.opcode_modifier
.no_qsuf
))
6443 && !i
.tm
.opcode_modifier
.ignoresize
6444 /* Accept FLDENV et al without suffix. */
6445 && (i
.tm
.opcode_modifier
.no_ssuf
|| i
.tm
.opcode_modifier
.floatmf
))
6447 unsigned int suffixes
, evex
= 0;
6449 suffixes
= !i
.tm
.opcode_modifier
.no_bsuf
;
6450 if (!i
.tm
.opcode_modifier
.no_wsuf
)
6452 if (!i
.tm
.opcode_modifier
.no_lsuf
)
6454 if (!i
.tm
.opcode_modifier
.no_ldsuf
)
6456 if (!i
.tm
.opcode_modifier
.no_ssuf
)
6458 if (flag_code
== CODE_64BIT
&& !i
.tm
.opcode_modifier
.no_qsuf
)
6461 /* For [XYZ]MMWORD operands inspect operand sizes. While generally
6462 also suitable for AT&T syntax mode, it was requested that this be
6463 restricted to just Intel syntax. */
6466 i386_cpu_flags cpu
= cpu_flags_and (i
.tm
.cpu_flags
, avx512
);
6468 if (!cpu_flags_all_zero (&cpu
) && !i
.broadcast
)
6472 for (op
= 0; op
< i
.tm
.operands
; ++op
)
6474 if (!cpu_arch_flags
.bitfield
.cpuavx512vl
)
6476 if (i
.tm
.operand_types
[op
].bitfield
.ymmword
)
6477 i
.tm
.operand_types
[op
].bitfield
.xmmword
= 0;
6478 if (i
.tm
.operand_types
[op
].bitfield
.zmmword
)
6479 i
.tm
.operand_types
[op
].bitfield
.ymmword
= 0;
6480 if (!i
.tm
.opcode_modifier
.evex
6481 || i
.tm
.opcode_modifier
.evex
== EVEXDYN
)
6482 i
.tm
.opcode_modifier
.evex
= EVEX512
;
6485 if (i
.tm
.operand_types
[op
].bitfield
.xmmword
6486 + i
.tm
.operand_types
[op
].bitfield
.ymmword
6487 + i
.tm
.operand_types
[op
].bitfield
.zmmword
< 2)
6490 /* Any properly sized operand disambiguates the insn. */
6491 if (i
.types
[op
].bitfield
.xmmword
6492 || i
.types
[op
].bitfield
.ymmword
6493 || i
.types
[op
].bitfield
.zmmword
)
6495 suffixes
&= ~(7 << 6);
6500 if ((i
.flags
[op
] & Operand_Mem
)
6501 && i
.tm
.operand_types
[op
].bitfield
.unspecified
)
6503 if (i
.tm
.operand_types
[op
].bitfield
.xmmword
)
6505 if (i
.tm
.operand_types
[op
].bitfield
.ymmword
)
6507 if (i
.tm
.operand_types
[op
].bitfield
.zmmword
)
6515 /* Are multiple suffixes / operand sizes allowed? */
6516 if (suffixes
& (suffixes
- 1))
6519 && (!i
.tm
.opcode_modifier
.defaultsize
6520 || operand_check
== check_error
))
6522 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
6525 if (operand_check
== check_error
)
6527 as_bad (_("no instruction mnemonic suffix given and "
6528 "no register operands; can't size `%s'"), i
.tm
.name
);
6531 if (operand_check
== check_warning
)
6532 as_warn (_("%s; using default for `%s'"),
6534 ? _("ambiguous operand size")
6535 : _("no instruction mnemonic suffix given and "
6536 "no register operands"),
6539 if (i
.tm
.opcode_modifier
.floatmf
)
6540 i
.suffix
= SHORT_MNEM_SUFFIX
;
6542 i
.tm
.opcode_modifier
.evex
= evex
;
6543 else if (flag_code
== CODE_16BIT
)
6544 i
.suffix
= WORD_MNEM_SUFFIX
;
6545 else if (!i
.tm
.opcode_modifier
.no_lsuf
)
6546 i
.suffix
= LONG_MNEM_SUFFIX
;
6548 i
.suffix
= QWORD_MNEM_SUFFIX
;
6552 if (!i
.tm
.opcode_modifier
.modrm
&& i
.reg_operands
&& i
.tm
.operands
< 3)
6553 i
.short_form
= (i
.tm
.operand_types
[0].bitfield
.class == Reg
)
6554 != (i
.tm
.operand_types
[1].bitfield
.class == Reg
);
6556 /* Change the opcode based on the operand size given by i.suffix. */
6559 /* Size floating point instruction. */
6560 case LONG_MNEM_SUFFIX
:
6561 if (i
.tm
.opcode_modifier
.floatmf
)
6563 i
.tm
.base_opcode
^= 4;
6567 case WORD_MNEM_SUFFIX
:
6568 case QWORD_MNEM_SUFFIX
:
6569 /* It's not a byte, select word/dword operation. */
6570 if (i
.tm
.opcode_modifier
.w
)
6573 i
.tm
.base_opcode
|= 8;
6575 i
.tm
.base_opcode
|= 1;
6578 case SHORT_MNEM_SUFFIX
:
6579 /* Now select between word & dword operations via the operand
6580 size prefix, except for instructions that will ignore this
6582 if (i
.reg_operands
> 0
6583 && i
.types
[0].bitfield
.class == Reg
6584 && i
.tm
.opcode_modifier
.addrprefixopreg
6585 && (i
.tm
.operand_types
[0].bitfield
.instance
== Accum
6586 || i
.operands
== 1))
6588 /* The address size override prefix changes the size of the
6590 if ((flag_code
== CODE_32BIT
6591 && i
.op
[0].regs
->reg_type
.bitfield
.word
)
6592 || (flag_code
!= CODE_32BIT
6593 && i
.op
[0].regs
->reg_type
.bitfield
.dword
))
6594 if (!add_prefix (ADDR_PREFIX_OPCODE
))
6597 else if (i
.suffix
!= QWORD_MNEM_SUFFIX
6598 && !i
.tm
.opcode_modifier
.ignoresize
6599 && !i
.tm
.opcode_modifier
.floatmf
6600 && !is_any_vex_encoding (&i
.tm
)
6601 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
6602 || (flag_code
== CODE_64BIT
6603 && i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
)))
6605 unsigned int prefix
= DATA_PREFIX_OPCODE
;
6607 if (i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
) /* jcxz, loop */
6608 prefix
= ADDR_PREFIX_OPCODE
;
6610 if (!add_prefix (prefix
))
6614 /* Set mode64 for an operand. */
6615 if (i
.suffix
== QWORD_MNEM_SUFFIX
6616 && flag_code
== CODE_64BIT
6617 && !i
.tm
.opcode_modifier
.norex64
6618 /* Special case for xchg %rax,%rax. It is NOP and doesn't
6620 && ! (i
.operands
== 2
6621 && i
.tm
.base_opcode
== 0x90
6622 && i
.tm
.extension_opcode
== None
6623 && i
.types
[0].bitfield
.instance
== Accum
6624 && i
.types
[0].bitfield
.qword
6625 && i
.types
[1].bitfield
.instance
== Accum
6626 && i
.types
[1].bitfield
.qword
))
6632 if (i
.reg_operands
!= 0
6634 && i
.tm
.opcode_modifier
.addrprefixopreg
6635 && i
.tm
.operand_types
[0].bitfield
.instance
!= Accum
)
6637 /* Check invalid register operand when the address size override
6638 prefix changes the size of register operands. */
6640 enum { need_word
, need_dword
, need_qword
} need
;
6642 if (flag_code
== CODE_32BIT
)
6643 need
= i
.prefix
[ADDR_PREFIX
] ? need_word
: need_dword
;
6646 if (i
.prefix
[ADDR_PREFIX
])
6649 need
= flag_code
== CODE_64BIT
? need_qword
: need_word
;
6652 for (op
= 0; op
< i
.operands
; op
++)
6653 if (i
.types
[op
].bitfield
.class == Reg
6654 && ((need
== need_word
6655 && !i
.op
[op
].regs
->reg_type
.bitfield
.word
)
6656 || (need
== need_dword
6657 && !i
.op
[op
].regs
->reg_type
.bitfield
.dword
)
6658 || (need
== need_qword
6659 && !i
.op
[op
].regs
->reg_type
.bitfield
.qword
)))
6661 as_bad (_("invalid register operand size for `%s'"),
6671 check_byte_reg (void)
6675 for (op
= i
.operands
; --op
>= 0;)
6677 /* Skip non-register operands. */
6678 if (i
.types
[op
].bitfield
.class != Reg
)
6681 /* If this is an eight bit register, it's OK. If it's the 16 or
6682 32 bit version of an eight bit register, we will just use the
6683 low portion, and that's OK too. */
6684 if (i
.types
[op
].bitfield
.byte
)
6687 /* I/O port address operands are OK too. */
6688 if (i
.tm
.operand_types
[op
].bitfield
.instance
== RegD
6689 && i
.tm
.operand_types
[op
].bitfield
.word
)
6692 /* crc32 only wants its source operand checked here. */
6693 if (i
.tm
.base_opcode
== 0xf20f38f0 && op
)
6696 /* Any other register is bad. */
6697 if (i
.types
[op
].bitfield
.class == Reg
6698 || i
.types
[op
].bitfield
.class == RegMMX
6699 || i
.types
[op
].bitfield
.class == RegSIMD
6700 || i
.types
[op
].bitfield
.class == SReg
6701 || i
.types
[op
].bitfield
.class == RegCR
6702 || i
.types
[op
].bitfield
.class == RegDR
6703 || i
.types
[op
].bitfield
.class == RegTR
)
6705 as_bad (_("`%s%s' not allowed with `%s%c'"),
6707 i
.op
[op
].regs
->reg_name
,
6717 check_long_reg (void)
6721 for (op
= i
.operands
; --op
>= 0;)
6722 /* Skip non-register operands. */
6723 if (i
.types
[op
].bitfield
.class != Reg
)
6725 /* Reject eight bit registers, except where the template requires
6726 them. (eg. movzb) */
6727 else if (i
.types
[op
].bitfield
.byte
6728 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
6729 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
6730 && (i
.tm
.operand_types
[op
].bitfield
.word
6731 || i
.tm
.operand_types
[op
].bitfield
.dword
))
6733 as_bad (_("`%s%s' not allowed with `%s%c'"),
6735 i
.op
[op
].regs
->reg_name
,
6740 /* Error if the e prefix on a general reg is missing. */
6741 else if (i
.types
[op
].bitfield
.word
6742 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
6743 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
6744 && i
.tm
.operand_types
[op
].bitfield
.dword
)
6746 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6747 register_prefix
, i
.op
[op
].regs
->reg_name
,
6751 /* Warn if the r prefix on a general reg is present. */
6752 else if (i
.types
[op
].bitfield
.qword
6753 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
6754 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
6755 && i
.tm
.operand_types
[op
].bitfield
.dword
)
6758 && (i
.tm
.opcode_modifier
.toqword
6759 /* Also convert to QWORD for MOVSXD. */
6760 || i
.tm
.base_opcode
== 0x63)
6761 && i
.types
[0].bitfield
.class != RegSIMD
)
6763 /* Convert to QWORD. We want REX byte. */
6764 i
.suffix
= QWORD_MNEM_SUFFIX
;
6768 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6769 register_prefix
, i
.op
[op
].regs
->reg_name
,
6778 check_qword_reg (void)
6782 for (op
= i
.operands
; --op
>= 0; )
6783 /* Skip non-register operands. */
6784 if (i
.types
[op
].bitfield
.class != Reg
)
6786 /* Reject eight bit registers, except where the template requires
6787 them. (eg. movzb) */
6788 else if (i
.types
[op
].bitfield
.byte
6789 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
6790 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
6791 && (i
.tm
.operand_types
[op
].bitfield
.word
6792 || i
.tm
.operand_types
[op
].bitfield
.dword
))
6794 as_bad (_("`%s%s' not allowed with `%s%c'"),
6796 i
.op
[op
].regs
->reg_name
,
6801 /* Warn if the r prefix on a general reg is missing. */
6802 else if ((i
.types
[op
].bitfield
.word
6803 || i
.types
[op
].bitfield
.dword
)
6804 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
6805 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
6806 && i
.tm
.operand_types
[op
].bitfield
.qword
)
6808 /* Prohibit these changes in the 64bit mode, since the
6809 lowering is more complicated. */
6811 && i
.tm
.opcode_modifier
.todword
6812 && i
.types
[0].bitfield
.class != RegSIMD
)
6814 /* Convert to DWORD. We don't want REX byte. */
6815 i
.suffix
= LONG_MNEM_SUFFIX
;
6819 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6820 register_prefix
, i
.op
[op
].regs
->reg_name
,
6829 check_word_reg (void)
6832 for (op
= i
.operands
; --op
>= 0;)
6833 /* Skip non-register operands. */
6834 if (i
.types
[op
].bitfield
.class != Reg
)
6836 /* Reject eight bit registers, except where the template requires
6837 them. (eg. movzb) */
6838 else if (i
.types
[op
].bitfield
.byte
6839 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
6840 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
6841 && (i
.tm
.operand_types
[op
].bitfield
.word
6842 || i
.tm
.operand_types
[op
].bitfield
.dword
))
6844 as_bad (_("`%s%s' not allowed with `%s%c'"),
6846 i
.op
[op
].regs
->reg_name
,
6851 /* Error if the e or r prefix on a general reg is present. */
6852 else if ((i
.types
[op
].bitfield
.dword
6853 || i
.types
[op
].bitfield
.qword
)
6854 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
6855 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
6856 && i
.tm
.operand_types
[op
].bitfield
.word
)
6858 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6859 register_prefix
, i
.op
[op
].regs
->reg_name
,
6867 update_imm (unsigned int j
)
6869 i386_operand_type overlap
= i
.types
[j
];
6870 if ((overlap
.bitfield
.imm8
6871 || overlap
.bitfield
.imm8s
6872 || overlap
.bitfield
.imm16
6873 || overlap
.bitfield
.imm32
6874 || overlap
.bitfield
.imm32s
6875 || overlap
.bitfield
.imm64
)
6876 && !operand_type_equal (&overlap
, &imm8
)
6877 && !operand_type_equal (&overlap
, &imm8s
)
6878 && !operand_type_equal (&overlap
, &imm16
)
6879 && !operand_type_equal (&overlap
, &imm32
)
6880 && !operand_type_equal (&overlap
, &imm32s
)
6881 && !operand_type_equal (&overlap
, &imm64
))
6885 i386_operand_type temp
;
6887 operand_type_set (&temp
, 0);
6888 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
6890 temp
.bitfield
.imm8
= overlap
.bitfield
.imm8
;
6891 temp
.bitfield
.imm8s
= overlap
.bitfield
.imm8s
;
6893 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
6894 temp
.bitfield
.imm16
= overlap
.bitfield
.imm16
;
6895 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
6897 temp
.bitfield
.imm64
= overlap
.bitfield
.imm64
;
6898 temp
.bitfield
.imm32s
= overlap
.bitfield
.imm32s
;
6901 temp
.bitfield
.imm32
= overlap
.bitfield
.imm32
;
6904 else if (operand_type_equal (&overlap
, &imm16_32_32s
)
6905 || operand_type_equal (&overlap
, &imm16_32
)
6906 || operand_type_equal (&overlap
, &imm16_32s
))
6908 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
6913 if (!operand_type_equal (&overlap
, &imm8
)
6914 && !operand_type_equal (&overlap
, &imm8s
)
6915 && !operand_type_equal (&overlap
, &imm16
)
6916 && !operand_type_equal (&overlap
, &imm32
)
6917 && !operand_type_equal (&overlap
, &imm32s
)
6918 && !operand_type_equal (&overlap
, &imm64
))
6920 as_bad (_("no instruction mnemonic suffix given; "
6921 "can't determine immediate size"));
6925 i
.types
[j
] = overlap
;
6935 /* Update the first 2 immediate operands. */
6936 n
= i
.operands
> 2 ? 2 : i
.operands
;
6939 for (j
= 0; j
< n
; j
++)
6940 if (update_imm (j
) == 0)
6943 /* The 3rd operand can't be immediate operand. */
6944 gas_assert (operand_type_check (i
.types
[2], imm
) == 0);
6951 process_operands (void)
6953 /* Default segment register this instruction will use for memory
6954 accesses. 0 means unknown. This is only for optimizing out
6955 unnecessary segment overrides. */
6956 const seg_entry
*default_seg
= 0;
6958 if (i
.tm
.opcode_modifier
.sse2avx
&& i
.tm
.opcode_modifier
.vexvvvv
)
6960 unsigned int dupl
= i
.operands
;
6961 unsigned int dest
= dupl
- 1;
6964 /* The destination must be an xmm register. */
6965 gas_assert (i
.reg_operands
6966 && MAX_OPERANDS
> dupl
6967 && operand_type_equal (&i
.types
[dest
], ®xmm
));
6969 if (i
.tm
.operand_types
[0].bitfield
.instance
== Accum
6970 && i
.tm
.operand_types
[0].bitfield
.xmmword
)
6972 if (i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
)
6974 /* Keep xmm0 for instructions with VEX prefix and 3
6976 i
.tm
.operand_types
[0].bitfield
.instance
= InstanceNone
;
6977 i
.tm
.operand_types
[0].bitfield
.class = RegSIMD
;
6982 /* We remove the first xmm0 and keep the number of
6983 operands unchanged, which in fact duplicates the
6985 for (j
= 1; j
< i
.operands
; j
++)
6987 i
.op
[j
- 1] = i
.op
[j
];
6988 i
.types
[j
- 1] = i
.types
[j
];
6989 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
6990 i
.flags
[j
- 1] = i
.flags
[j
];
6994 else if (i
.tm
.opcode_modifier
.implicit1stxmm0
)
6996 gas_assert ((MAX_OPERANDS
- 1) > dupl
6997 && (i
.tm
.opcode_modifier
.vexsources
7000 /* Add the implicit xmm0 for instructions with VEX prefix
7002 for (j
= i
.operands
; j
> 0; j
--)
7004 i
.op
[j
] = i
.op
[j
- 1];
7005 i
.types
[j
] = i
.types
[j
- 1];
7006 i
.tm
.operand_types
[j
] = i
.tm
.operand_types
[j
- 1];
7007 i
.flags
[j
] = i
.flags
[j
- 1];
7010 = (const reg_entry
*) hash_find (reg_hash
, "xmm0");
7011 i
.types
[0] = regxmm
;
7012 i
.tm
.operand_types
[0] = regxmm
;
7015 i
.reg_operands
+= 2;
7020 i
.op
[dupl
] = i
.op
[dest
];
7021 i
.types
[dupl
] = i
.types
[dest
];
7022 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
7023 i
.flags
[dupl
] = i
.flags
[dest
];
7032 i
.op
[dupl
] = i
.op
[dest
];
7033 i
.types
[dupl
] = i
.types
[dest
];
7034 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
7035 i
.flags
[dupl
] = i
.flags
[dest
];
7038 if (i
.tm
.opcode_modifier
.immext
)
7041 else if (i
.tm
.operand_types
[0].bitfield
.instance
== Accum
7042 && i
.tm
.operand_types
[0].bitfield
.xmmword
)
7046 for (j
= 1; j
< i
.operands
; j
++)
7048 i
.op
[j
- 1] = i
.op
[j
];
7049 i
.types
[j
- 1] = i
.types
[j
];
7051 /* We need to adjust fields in i.tm since they are used by
7052 build_modrm_byte. */
7053 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
7055 i
.flags
[j
- 1] = i
.flags
[j
];
7062 else if (i
.tm
.opcode_modifier
.implicitquadgroup
)
7064 unsigned int regnum
, first_reg_in_group
, last_reg_in_group
;
7066 /* The second operand must be {x,y,z}mmN, where N is a multiple of 4. */
7067 gas_assert (i
.operands
>= 2 && i
.types
[1].bitfield
.class == RegSIMD
);
7068 regnum
= register_number (i
.op
[1].regs
);
7069 first_reg_in_group
= regnum
& ~3;
7070 last_reg_in_group
= first_reg_in_group
+ 3;
7071 if (regnum
!= first_reg_in_group
)
7072 as_warn (_("source register `%s%s' implicitly denotes"
7073 " `%s%.3s%u' to `%s%.3s%u' source group in `%s'"),
7074 register_prefix
, i
.op
[1].regs
->reg_name
,
7075 register_prefix
, i
.op
[1].regs
->reg_name
, first_reg_in_group
,
7076 register_prefix
, i
.op
[1].regs
->reg_name
, last_reg_in_group
,
7079 else if (i
.tm
.opcode_modifier
.regkludge
)
7081 /* The imul $imm, %reg instruction is converted into
7082 imul $imm, %reg, %reg, and the clr %reg instruction
7083 is converted into xor %reg, %reg. */
7085 unsigned int first_reg_op
;
7087 if (operand_type_check (i
.types
[0], reg
))
7091 /* Pretend we saw the extra register operand. */
7092 gas_assert (i
.reg_operands
== 1
7093 && i
.op
[first_reg_op
+ 1].regs
== 0);
7094 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
7095 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
7100 if (i
.tm
.opcode_modifier
.modrm
)
7102 /* The opcode is completed (modulo i.tm.extension_opcode which
7103 must be put into the modrm byte). Now, we make the modrm and
7104 index base bytes based on all the info we've collected. */
7106 default_seg
= build_modrm_byte ();
7108 else if (i
.types
[0].bitfield
.class == SReg
)
7110 if (flag_code
!= CODE_64BIT
7111 ? i
.tm
.base_opcode
== POP_SEG_SHORT
7112 && i
.op
[0].regs
->reg_num
== 1
7113 : (i
.tm
.base_opcode
| 1) == POP_SEG386_SHORT
7114 && i
.op
[0].regs
->reg_num
< 4)
7116 as_bad (_("you can't `%s %s%s'"),
7117 i
.tm
.name
, register_prefix
, i
.op
[0].regs
->reg_name
);
7120 if ( i
.op
[0].regs
->reg_num
> 3 && i
.tm
.opcode_length
== 1 )
7122 i
.tm
.base_opcode
^= POP_SEG_SHORT
^ POP_SEG386_SHORT
;
7123 i
.tm
.opcode_length
= 2;
7125 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
7127 else if ((i
.tm
.base_opcode
& ~0x3) == MOV_AX_DISP32
)
7131 else if (i
.tm
.opcode_modifier
.isstring
)
7133 /* For the string instructions that allow a segment override
7134 on one of their operands, the default segment is ds. */
7137 else if (i
.short_form
)
7139 /* The register or float register operand is in operand
7141 unsigned int op
= i
.tm
.operand_types
[0].bitfield
.class != Reg
;
7143 /* Register goes in low 3 bits of opcode. */
7144 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
7145 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
7147 if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
7149 /* Warn about some common errors, but press on regardless.
7150 The first case can be generated by gcc (<= 2.8.1). */
7151 if (i
.operands
== 2)
7153 /* Reversed arguments on faddp, fsubp, etc. */
7154 as_warn (_("translating to `%s %s%s,%s%s'"), i
.tm
.name
,
7155 register_prefix
, i
.op
[!intel_syntax
].regs
->reg_name
,
7156 register_prefix
, i
.op
[intel_syntax
].regs
->reg_name
);
7160 /* Extraneous `l' suffix on fp insn. */
7161 as_warn (_("translating to `%s %s%s'"), i
.tm
.name
,
7162 register_prefix
, i
.op
[0].regs
->reg_name
);
7167 if (i
.tm
.base_opcode
== 0x8d /* lea */
7170 as_warn (_("segment override on `%s' is ineffectual"), i
.tm
.name
);
7172 /* If a segment was explicitly specified, and the specified segment
7173 is not the default, use an opcode prefix to select it. If we
7174 never figured out what the default segment is, then default_seg
7175 will be zero at this point, and the specified segment prefix will
7177 if ((i
.seg
[0]) && (i
.seg
[0] != default_seg
))
7179 if (!add_prefix (i
.seg
[0]->seg_prefix
))
7185 static const seg_entry
*
7186 build_modrm_byte (void)
7188 const seg_entry
*default_seg
= 0;
7189 unsigned int source
, dest
;
7192 vex_3_sources
= i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
;
7195 unsigned int nds
, reg_slot
;
7198 dest
= i
.operands
- 1;
7201 /* There are 2 kinds of instructions:
7202 1. 5 operands: 4 register operands or 3 register operands
7203 plus 1 memory operand plus one Imm4 operand, VexXDS, and
7204 VexW0 or VexW1. The destination must be either XMM, YMM or
7206 2. 4 operands: 4 register operands or 3 register operands
7207 plus 1 memory operand, with VexXDS. */
7208 gas_assert ((i
.reg_operands
== 4
7209 || (i
.reg_operands
== 3 && i
.mem_operands
== 1))
7210 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
7211 && i
.tm
.opcode_modifier
.vexw
7212 && i
.tm
.operand_types
[dest
].bitfield
.class == RegSIMD
);
7214 /* If VexW1 is set, the first non-immediate operand is the source and
7215 the second non-immediate one is encoded in the immediate operand. */
7216 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
7218 source
= i
.imm_operands
;
7219 reg_slot
= i
.imm_operands
+ 1;
7223 source
= i
.imm_operands
+ 1;
7224 reg_slot
= i
.imm_operands
;
7227 if (i
.imm_operands
== 0)
7229 /* When there is no immediate operand, generate an 8bit
7230 immediate operand to encode the first operand. */
7231 exp
= &im_expressions
[i
.imm_operands
++];
7232 i
.op
[i
.operands
].imms
= exp
;
7233 i
.types
[i
.operands
] = imm8
;
7236 gas_assert (i
.tm
.operand_types
[reg_slot
].bitfield
.class == RegSIMD
);
7237 exp
->X_op
= O_constant
;
7238 exp
->X_add_number
= register_number (i
.op
[reg_slot
].regs
) << 4;
7239 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
7243 gas_assert (i
.imm_operands
== 1);
7244 gas_assert (fits_in_imm4 (i
.op
[0].imms
->X_add_number
));
7245 gas_assert (!i
.tm
.opcode_modifier
.immext
);
7247 /* Turn on Imm8 again so that output_imm will generate it. */
7248 i
.types
[0].bitfield
.imm8
= 1;
7250 gas_assert (i
.tm
.operand_types
[reg_slot
].bitfield
.class == RegSIMD
);
7251 i
.op
[0].imms
->X_add_number
7252 |= register_number (i
.op
[reg_slot
].regs
) << 4;
7253 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
7256 gas_assert (i
.tm
.operand_types
[nds
].bitfield
.class == RegSIMD
);
7257 i
.vex
.register_specifier
= i
.op
[nds
].regs
;
7262 /* i.reg_operands MUST be the number of real register operands;
7263 implicit registers do not count. If there are 3 register
7264 operands, it must be a instruction with VexNDS. For a
7265 instruction with VexNDD, the destination register is encoded
7266 in VEX prefix. If there are 4 register operands, it must be
7267 a instruction with VEX prefix and 3 sources. */
7268 if (i
.mem_operands
== 0
7269 && ((i
.reg_operands
== 2
7270 && i
.tm
.opcode_modifier
.vexvvvv
<= VEXXDS
)
7271 || (i
.reg_operands
== 3
7272 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
7273 || (i
.reg_operands
== 4 && vex_3_sources
)))
7281 /* When there are 3 operands, one of them may be immediate,
7282 which may be the first or the last operand. Otherwise,
7283 the first operand must be shift count register (cl) or it
7284 is an instruction with VexNDS. */
7285 gas_assert (i
.imm_operands
== 1
7286 || (i
.imm_operands
== 0
7287 && (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
7288 || (i
.types
[0].bitfield
.instance
== RegC
7289 && i
.types
[0].bitfield
.byte
))));
7290 if (operand_type_check (i
.types
[0], imm
)
7291 || (i
.types
[0].bitfield
.instance
== RegC
7292 && i
.types
[0].bitfield
.byte
))
7298 /* When there are 4 operands, the first two must be 8bit
7299 immediate operands. The source operand will be the 3rd
7302 For instructions with VexNDS, if the first operand
7303 an imm8, the source operand is the 2nd one. If the last
7304 operand is imm8, the source operand is the first one. */
7305 gas_assert ((i
.imm_operands
== 2
7306 && i
.types
[0].bitfield
.imm8
7307 && i
.types
[1].bitfield
.imm8
)
7308 || (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
7309 && i
.imm_operands
== 1
7310 && (i
.types
[0].bitfield
.imm8
7311 || i
.types
[i
.operands
- 1].bitfield
.imm8
7313 if (i
.imm_operands
== 2)
7317 if (i
.types
[0].bitfield
.imm8
)
7324 if (is_evex_encoding (&i
.tm
))
7326 /* For EVEX instructions, when there are 5 operands, the
7327 first one must be immediate operand. If the second one
7328 is immediate operand, the source operand is the 3th
7329 one. If the last one is immediate operand, the source
7330 operand is the 2nd one. */
7331 gas_assert (i
.imm_operands
== 2
7332 && i
.tm
.opcode_modifier
.sae
7333 && operand_type_check (i
.types
[0], imm
));
7334 if (operand_type_check (i
.types
[1], imm
))
7336 else if (operand_type_check (i
.types
[4], imm
))
7350 /* RC/SAE operand could be between DEST and SRC. That happens
7351 when one operand is GPR and the other one is XMM/YMM/ZMM
7353 if (i
.rounding
&& i
.rounding
->operand
== (int) dest
)
7356 if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
7358 /* For instructions with VexNDS, the register-only source
7359 operand must be a 32/64bit integer, XMM, YMM, ZMM, or mask
7360 register. It is encoded in VEX prefix. */
7362 i386_operand_type op
;
7365 /* Check register-only source operand when two source
7366 operands are swapped. */
7367 if (!i
.tm
.operand_types
[source
].bitfield
.baseindex
7368 && i
.tm
.operand_types
[dest
].bitfield
.baseindex
)
7376 op
= i
.tm
.operand_types
[vvvv
];
7377 if ((dest
+ 1) >= i
.operands
7378 || ((op
.bitfield
.class != Reg
7379 || (!op
.bitfield
.dword
&& !op
.bitfield
.qword
))
7380 && op
.bitfield
.class != RegSIMD
7381 && !operand_type_equal (&op
, ®mask
)))
7383 i
.vex
.register_specifier
= i
.op
[vvvv
].regs
;
7389 /* One of the register operands will be encoded in the i.rm.reg
7390 field, the other in the combined i.rm.mode and i.rm.regmem
7391 fields. If no form of this instruction supports a memory
7392 destination operand, then we assume the source operand may
7393 sometimes be a memory operand and so we need to store the
7394 destination in the i.rm.reg field. */
7395 if (!i
.tm
.opcode_modifier
.regmem
7396 && operand_type_check (i
.tm
.operand_types
[dest
], anymem
) == 0)
7398 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
7399 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
7400 if (i
.op
[dest
].regs
->reg_type
.bitfield
.class == RegMMX
7401 || i
.op
[source
].regs
->reg_type
.bitfield
.class == RegMMX
)
7402 i
.has_regmmx
= TRUE
;
7403 else if (i
.op
[dest
].regs
->reg_type
.bitfield
.class == RegSIMD
7404 || i
.op
[source
].regs
->reg_type
.bitfield
.class == RegSIMD
)
7406 if (i
.types
[dest
].bitfield
.zmmword
7407 || i
.types
[source
].bitfield
.zmmword
)
7408 i
.has_regzmm
= TRUE
;
7409 else if (i
.types
[dest
].bitfield
.ymmword
7410 || i
.types
[source
].bitfield
.ymmword
)
7411 i
.has_regymm
= TRUE
;
7413 i
.has_regxmm
= TRUE
;
7415 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
7417 if ((i
.op
[dest
].regs
->reg_flags
& RegVRex
) != 0)
7419 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
7421 if ((i
.op
[source
].regs
->reg_flags
& RegVRex
) != 0)
7426 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
7427 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
7428 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
7430 if ((i
.op
[dest
].regs
->reg_flags
& RegVRex
) != 0)
7432 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
7434 if ((i
.op
[source
].regs
->reg_flags
& RegVRex
) != 0)
7437 if (flag_code
!= CODE_64BIT
&& (i
.rex
& REX_R
))
7439 if (i
.types
[!i
.tm
.opcode_modifier
.regmem
].bitfield
.class != RegCR
)
7442 add_prefix (LOCK_PREFIX_OPCODE
);
7446 { /* If it's not 2 reg operands... */
7451 unsigned int fake_zero_displacement
= 0;
7454 for (op
= 0; op
< i
.operands
; op
++)
7455 if (i
.flags
[op
] & Operand_Mem
)
7457 gas_assert (op
< i
.operands
);
7459 if (i
.tm
.opcode_modifier
.vecsib
)
7461 if (i
.index_reg
->reg_num
== RegIZ
)
7464 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
7467 i
.sib
.base
= NO_BASE_REGISTER
;
7468 i
.sib
.scale
= i
.log2_scale_factor
;
7469 i
.types
[op
].bitfield
.disp8
= 0;
7470 i
.types
[op
].bitfield
.disp16
= 0;
7471 i
.types
[op
].bitfield
.disp64
= 0;
7472 if (flag_code
!= CODE_64BIT
|| i
.prefix
[ADDR_PREFIX
])
7474 /* Must be 32 bit */
7475 i
.types
[op
].bitfield
.disp32
= 1;
7476 i
.types
[op
].bitfield
.disp32s
= 0;
7480 i
.types
[op
].bitfield
.disp32
= 0;
7481 i
.types
[op
].bitfield
.disp32s
= 1;
7484 i
.sib
.index
= i
.index_reg
->reg_num
;
7485 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
7487 if ((i
.index_reg
->reg_flags
& RegVRex
) != 0)
7493 if (i
.base_reg
== 0)
7496 if (!i
.disp_operands
)
7497 fake_zero_displacement
= 1;
7498 if (i
.index_reg
== 0)
7500 i386_operand_type newdisp
;
7502 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
7503 /* Operand is just <disp> */
7504 if (flag_code
== CODE_64BIT
)
7506 /* 64bit mode overwrites the 32bit absolute
7507 addressing by RIP relative addressing and
7508 absolute addressing is encoded by one of the
7509 redundant SIB forms. */
7510 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
7511 i
.sib
.base
= NO_BASE_REGISTER
;
7512 i
.sib
.index
= NO_INDEX_REGISTER
;
7513 newdisp
= (!i
.prefix
[ADDR_PREFIX
] ? disp32s
: disp32
);
7515 else if ((flag_code
== CODE_16BIT
)
7516 ^ (i
.prefix
[ADDR_PREFIX
] != 0))
7518 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
7523 i
.rm
.regmem
= NO_BASE_REGISTER
;
7526 i
.types
[op
] = operand_type_and_not (i
.types
[op
], anydisp
);
7527 i
.types
[op
] = operand_type_or (i
.types
[op
], newdisp
);
7529 else if (!i
.tm
.opcode_modifier
.vecsib
)
7531 /* !i.base_reg && i.index_reg */
7532 if (i
.index_reg
->reg_num
== RegIZ
)
7533 i
.sib
.index
= NO_INDEX_REGISTER
;
7535 i
.sib
.index
= i
.index_reg
->reg_num
;
7536 i
.sib
.base
= NO_BASE_REGISTER
;
7537 i
.sib
.scale
= i
.log2_scale_factor
;
7538 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
7539 i
.types
[op
].bitfield
.disp8
= 0;
7540 i
.types
[op
].bitfield
.disp16
= 0;
7541 i
.types
[op
].bitfield
.disp64
= 0;
7542 if (flag_code
!= CODE_64BIT
|| i
.prefix
[ADDR_PREFIX
])
7544 /* Must be 32 bit */
7545 i
.types
[op
].bitfield
.disp32
= 1;
7546 i
.types
[op
].bitfield
.disp32s
= 0;
7550 i
.types
[op
].bitfield
.disp32
= 0;
7551 i
.types
[op
].bitfield
.disp32s
= 1;
7553 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
7557 /* RIP addressing for 64bit mode. */
7558 else if (i
.base_reg
->reg_num
== RegIP
)
7560 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
7561 i
.rm
.regmem
= NO_BASE_REGISTER
;
7562 i
.types
[op
].bitfield
.disp8
= 0;
7563 i
.types
[op
].bitfield
.disp16
= 0;
7564 i
.types
[op
].bitfield
.disp32
= 0;
7565 i
.types
[op
].bitfield
.disp32s
= 1;
7566 i
.types
[op
].bitfield
.disp64
= 0;
7567 i
.flags
[op
] |= Operand_PCrel
;
7568 if (! i
.disp_operands
)
7569 fake_zero_displacement
= 1;
7571 else if (i
.base_reg
->reg_type
.bitfield
.word
)
7573 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
7574 switch (i
.base_reg
->reg_num
)
7577 if (i
.index_reg
== 0)
7579 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
7580 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
7584 if (i
.index_reg
== 0)
7587 if (operand_type_check (i
.types
[op
], disp
) == 0)
7589 /* fake (%bp) into 0(%bp) */
7590 i
.types
[op
].bitfield
.disp8
= 1;
7591 fake_zero_displacement
= 1;
7594 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
7595 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
7597 default: /* (%si) -> 4 or (%di) -> 5 */
7598 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
7600 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
7602 else /* i.base_reg and 32/64 bit mode */
7604 if (flag_code
== CODE_64BIT
7605 && operand_type_check (i
.types
[op
], disp
))
7607 i
.types
[op
].bitfield
.disp16
= 0;
7608 i
.types
[op
].bitfield
.disp64
= 0;
7609 if (i
.prefix
[ADDR_PREFIX
] == 0)
7611 i
.types
[op
].bitfield
.disp32
= 0;
7612 i
.types
[op
].bitfield
.disp32s
= 1;
7616 i
.types
[op
].bitfield
.disp32
= 1;
7617 i
.types
[op
].bitfield
.disp32s
= 0;
7621 if (!i
.tm
.opcode_modifier
.vecsib
)
7622 i
.rm
.regmem
= i
.base_reg
->reg_num
;
7623 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
7625 i
.sib
.base
= i
.base_reg
->reg_num
;
7626 /* x86-64 ignores REX prefix bit here to avoid decoder
7628 if (!(i
.base_reg
->reg_flags
& RegRex
)
7629 && (i
.base_reg
->reg_num
== EBP_REG_NUM
7630 || i
.base_reg
->reg_num
== ESP_REG_NUM
))
7632 if (i
.base_reg
->reg_num
== 5 && i
.disp_operands
== 0)
7634 fake_zero_displacement
= 1;
7635 i
.types
[op
].bitfield
.disp8
= 1;
7637 i
.sib
.scale
= i
.log2_scale_factor
;
7638 if (i
.index_reg
== 0)
7640 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
7641 /* <disp>(%esp) becomes two byte modrm with no index
7642 register. We've already stored the code for esp
7643 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
7644 Any base register besides %esp will not use the
7645 extra modrm byte. */
7646 i
.sib
.index
= NO_INDEX_REGISTER
;
7648 else if (!i
.tm
.opcode_modifier
.vecsib
)
7650 if (i
.index_reg
->reg_num
== RegIZ
)
7651 i
.sib
.index
= NO_INDEX_REGISTER
;
7653 i
.sib
.index
= i
.index_reg
->reg_num
;
7654 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
7655 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
7660 && (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
7661 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
))
7665 if (!fake_zero_displacement
7669 fake_zero_displacement
= 1;
7670 if (i
.disp_encoding
== disp_encoding_8bit
)
7671 i
.types
[op
].bitfield
.disp8
= 1;
7673 i
.types
[op
].bitfield
.disp32
= 1;
7675 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
7679 if (fake_zero_displacement
)
7681 /* Fakes a zero displacement assuming that i.types[op]
7682 holds the correct displacement size. */
7685 gas_assert (i
.op
[op
].disps
== 0);
7686 exp
= &disp_expressions
[i
.disp_operands
++];
7687 i
.op
[op
].disps
= exp
;
7688 exp
->X_op
= O_constant
;
7689 exp
->X_add_number
= 0;
7690 exp
->X_add_symbol
= (symbolS
*) 0;
7691 exp
->X_op_symbol
= (symbolS
*) 0;
7699 if (i
.tm
.opcode_modifier
.vexsources
== XOP2SOURCES
)
7701 if (operand_type_check (i
.types
[0], imm
))
7702 i
.vex
.register_specifier
= NULL
;
7705 /* VEX.vvvv encodes one of the sources when the first
7706 operand is not an immediate. */
7707 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
7708 i
.vex
.register_specifier
= i
.op
[0].regs
;
7710 i
.vex
.register_specifier
= i
.op
[1].regs
;
7713 /* Destination is a XMM register encoded in the ModRM.reg
7715 i
.rm
.reg
= i
.op
[2].regs
->reg_num
;
7716 if ((i
.op
[2].regs
->reg_flags
& RegRex
) != 0)
7719 /* ModRM.rm and VEX.B encodes the other source. */
7720 if (!i
.mem_operands
)
7724 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
7725 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
7727 i
.rm
.regmem
= i
.op
[0].regs
->reg_num
;
7729 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
7733 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXLWP
)
7735 i
.vex
.register_specifier
= i
.op
[2].regs
;
7736 if (!i
.mem_operands
)
7739 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
7740 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
7744 /* Fill in i.rm.reg or i.rm.regmem field with register operand
7745 (if any) based on i.tm.extension_opcode. Again, we must be
7746 careful to make sure that segment/control/debug/test/MMX
7747 registers are coded into the i.rm.reg field. */
7748 else if (i
.reg_operands
)
7751 unsigned int vex_reg
= ~0;
7753 for (op
= 0; op
< i
.operands
; op
++)
7755 if (i
.types
[op
].bitfield
.class == Reg
7756 || i
.types
[op
].bitfield
.class == RegBND
7757 || i
.types
[op
].bitfield
.class == RegMask
7758 || i
.types
[op
].bitfield
.class == SReg
7759 || i
.types
[op
].bitfield
.class == RegCR
7760 || i
.types
[op
].bitfield
.class == RegDR
7761 || i
.types
[op
].bitfield
.class == RegTR
)
7763 if (i
.types
[op
].bitfield
.class == RegSIMD
)
7765 if (i
.types
[op
].bitfield
.zmmword
)
7766 i
.has_regzmm
= TRUE
;
7767 else if (i
.types
[op
].bitfield
.ymmword
)
7768 i
.has_regymm
= TRUE
;
7770 i
.has_regxmm
= TRUE
;
7773 if (i
.types
[op
].bitfield
.class == RegMMX
)
7775 i
.has_regmmx
= TRUE
;
7782 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
7784 /* For instructions with VexNDS, the register-only
7785 source operand is encoded in VEX prefix. */
7786 gas_assert (mem
!= (unsigned int) ~0);
7791 gas_assert (op
< i
.operands
);
7795 /* Check register-only source operand when two source
7796 operands are swapped. */
7797 if (!i
.tm
.operand_types
[op
].bitfield
.baseindex
7798 && i
.tm
.operand_types
[op
+ 1].bitfield
.baseindex
)
7802 gas_assert (mem
== (vex_reg
+ 1)
7803 && op
< i
.operands
);
7808 gas_assert (vex_reg
< i
.operands
);
7812 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXNDD
)
7814 /* For instructions with VexNDD, the register destination
7815 is encoded in VEX prefix. */
7816 if (i
.mem_operands
== 0)
7818 /* There is no memory operand. */
7819 gas_assert ((op
+ 2) == i
.operands
);
7824 /* There are only 2 non-immediate operands. */
7825 gas_assert (op
< i
.imm_operands
+ 2
7826 && i
.operands
== i
.imm_operands
+ 2);
7827 vex_reg
= i
.imm_operands
+ 1;
7831 gas_assert (op
< i
.operands
);
7833 if (vex_reg
!= (unsigned int) ~0)
7835 i386_operand_type
*type
= &i
.tm
.operand_types
[vex_reg
];
7837 if ((type
->bitfield
.class != Reg
7838 || (!type
->bitfield
.dword
&& !type
->bitfield
.qword
))
7839 && type
->bitfield
.class != RegSIMD
7840 && !operand_type_equal (type
, ®mask
))
7843 i
.vex
.register_specifier
= i
.op
[vex_reg
].regs
;
7846 /* Don't set OP operand twice. */
7849 /* If there is an extension opcode to put here, the
7850 register number must be put into the regmem field. */
7851 if (i
.tm
.extension_opcode
!= None
)
7853 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
7854 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
7856 if ((i
.op
[op
].regs
->reg_flags
& RegVRex
) != 0)
7861 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
7862 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
7864 if ((i
.op
[op
].regs
->reg_flags
& RegVRex
) != 0)
7869 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
7870 must set it to 3 to indicate this is a register operand
7871 in the regmem field. */
7872 if (!i
.mem_operands
)
7876 /* Fill in i.rm.reg field with extension opcode (if any). */
7877 if (i
.tm
.extension_opcode
!= None
)
7878 i
.rm
.reg
= i
.tm
.extension_opcode
;
7884 flip_code16 (unsigned int code16
)
7886 gas_assert (i
.tm
.operands
== 1);
7888 return !(i
.prefix
[REX_PREFIX
] & REX_W
)
7889 && (code16
? i
.tm
.operand_types
[0].bitfield
.disp32
7890 || i
.tm
.operand_types
[0].bitfield
.disp32s
7891 : i
.tm
.operand_types
[0].bitfield
.disp16
)
7896 output_branch (void)
7902 relax_substateT subtype
;
7906 code16
= flag_code
== CODE_16BIT
? CODE16
: 0;
7907 size
= i
.disp_encoding
== disp_encoding_32bit
? BIG
: SMALL
;
7910 if (i
.prefix
[DATA_PREFIX
] != 0)
7914 code16
^= flip_code16(code16
);
7916 /* Pentium4 branch hints. */
7917 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
7918 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
7923 if (i
.prefix
[REX_PREFIX
] != 0)
7929 /* BND prefixed jump. */
7930 if (i
.prefix
[BND_PREFIX
] != 0)
7936 if (i
.prefixes
!= 0)
7937 as_warn (_("skipping prefixes on `%s'"), i
.tm
.name
);
7939 /* It's always a symbol; End frag & setup for relax.
7940 Make sure there is enough room in this frag for the largest
7941 instruction we may generate in md_convert_frag. This is 2
7942 bytes for the opcode and room for the prefix and largest
7944 frag_grow (prefix
+ 2 + 4);
7945 /* Prefix and 1 opcode byte go in fr_fix. */
7946 p
= frag_more (prefix
+ 1);
7947 if (i
.prefix
[DATA_PREFIX
] != 0)
7948 *p
++ = DATA_PREFIX_OPCODE
;
7949 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
7950 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
7951 *p
++ = i
.prefix
[SEG_PREFIX
];
7952 if (i
.prefix
[BND_PREFIX
] != 0)
7953 *p
++ = BND_PREFIX_OPCODE
;
7954 if (i
.prefix
[REX_PREFIX
] != 0)
7955 *p
++ = i
.prefix
[REX_PREFIX
];
7956 *p
= i
.tm
.base_opcode
;
7958 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
7959 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, size
);
7960 else if (cpu_arch_flags
.bitfield
.cpui386
)
7961 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, size
);
7963 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, size
);
7966 sym
= i
.op
[0].disps
->X_add_symbol
;
7967 off
= i
.op
[0].disps
->X_add_number
;
7969 if (i
.op
[0].disps
->X_op
!= O_constant
7970 && i
.op
[0].disps
->X_op
!= O_symbol
)
7972 /* Handle complex expressions. */
7973 sym
= make_expr_symbol (i
.op
[0].disps
);
7977 /* 1 possible extra opcode + 4 byte displacement go in var part.
7978 Pass reloc in fr_var. */
7979 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
7982 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7983 /* Return TRUE iff PLT32 relocation should be used for branching to
7987 need_plt32_p (symbolS
*s
)
7989 /* PLT32 relocation is ELF only. */
7994 /* Don't emit PLT32 relocation on Solaris: neither native linker nor
7995 krtld support it. */
7999 /* Since there is no need to prepare for PLT branch on x86-64, we
8000 can generate R_X86_64_PLT32, instead of R_X86_64_PC32, which can
8001 be used as a marker for 32-bit PC-relative branches. */
8005 /* Weak or undefined symbol need PLT32 relocation. */
8006 if (S_IS_WEAK (s
) || !S_IS_DEFINED (s
))
8009 /* Non-global symbol doesn't need PLT32 relocation. */
8010 if (! S_IS_EXTERNAL (s
))
8013 /* Other global symbols need PLT32 relocation. NB: Symbol with
8014 non-default visibilities are treated as normal global symbol
8015 so that PLT32 relocation can be used as a marker for 32-bit
8016 PC-relative branches. It is useful for linker relaxation. */
8027 bfd_reloc_code_real_type jump_reloc
= i
.reloc
[0];
8029 if (i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
)
8031 /* This is a loop or jecxz type instruction. */
8033 if (i
.prefix
[ADDR_PREFIX
] != 0)
8035 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
8038 /* Pentium4 branch hints. */
8039 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
8040 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
8042 FRAG_APPEND_1_CHAR (i
.prefix
[SEG_PREFIX
]);
8051 if (flag_code
== CODE_16BIT
)
8054 if (i
.prefix
[DATA_PREFIX
] != 0)
8056 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
8058 code16
^= flip_code16(code16
);
8066 /* BND prefixed jump. */
8067 if (i
.prefix
[BND_PREFIX
] != 0)
8069 FRAG_APPEND_1_CHAR (i
.prefix
[BND_PREFIX
]);
8073 if (i
.prefix
[REX_PREFIX
] != 0)
8075 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
8079 if (i
.prefixes
!= 0)
8080 as_warn (_("skipping prefixes on `%s'"), i
.tm
.name
);
8082 p
= frag_more (i
.tm
.opcode_length
+ size
);
8083 switch (i
.tm
.opcode_length
)
8086 *p
++ = i
.tm
.base_opcode
>> 8;
8089 *p
++ = i
.tm
.base_opcode
;
8095 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8097 && jump_reloc
== NO_RELOC
8098 && need_plt32_p (i
.op
[0].disps
->X_add_symbol
))
8099 jump_reloc
= BFD_RELOC_X86_64_PLT32
;
8102 jump_reloc
= reloc (size
, 1, 1, jump_reloc
);
8104 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
8105 i
.op
[0].disps
, 1, jump_reloc
);
8107 /* All jumps handled here are signed, but don't use a signed limit
8108 check for 32 and 16 bit jumps as we want to allow wrap around at
8109 4G and 64k respectively. */
8111 fixP
->fx_signed
= 1;
8115 output_interseg_jump (void)
8123 if (flag_code
== CODE_16BIT
)
8127 if (i
.prefix
[DATA_PREFIX
] != 0)
8134 gas_assert (!i
.prefix
[REX_PREFIX
]);
8140 if (i
.prefixes
!= 0)
8141 as_warn (_("skipping prefixes on `%s'"), i
.tm
.name
);
8143 /* 1 opcode; 2 segment; offset */
8144 p
= frag_more (prefix
+ 1 + 2 + size
);
8146 if (i
.prefix
[DATA_PREFIX
] != 0)
8147 *p
++ = DATA_PREFIX_OPCODE
;
8149 if (i
.prefix
[REX_PREFIX
] != 0)
8150 *p
++ = i
.prefix
[REX_PREFIX
];
8152 *p
++ = i
.tm
.base_opcode
;
8153 if (i
.op
[1].imms
->X_op
== O_constant
)
8155 offsetT n
= i
.op
[1].imms
->X_add_number
;
8158 && !fits_in_unsigned_word (n
)
8159 && !fits_in_signed_word (n
))
8161 as_bad (_("16-bit jump out of range"));
8164 md_number_to_chars (p
, n
, size
);
8167 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
8168 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
8169 if (i
.op
[0].imms
->X_op
!= O_constant
)
8170 as_bad (_("can't handle non absolute segment in `%s'"),
8172 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
8175 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8180 asection
*seg
= now_seg
;
8181 subsegT subseg
= now_subseg
;
8183 unsigned int alignment
, align_size_1
;
8184 unsigned int isa_1_descsz
, feature_2_descsz
, descsz
;
8185 unsigned int isa_1_descsz_raw
, feature_2_descsz_raw
;
8186 unsigned int padding
;
8188 if (!IS_ELF
|| !x86_used_note
)
8191 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_X86
;
8193 /* The .note.gnu.property section layout:
8195 Field Length Contents
8198 n_descsz 4 The note descriptor size
8199 n_type 4 NT_GNU_PROPERTY_TYPE_0
8201 n_desc n_descsz The program property array
8205 /* Create the .note.gnu.property section. */
8206 sec
= subseg_new (NOTE_GNU_PROPERTY_SECTION_NAME
, 0);
8207 bfd_set_section_flags (sec
,
8214 if (get_elf_backend_data (stdoutput
)->s
->elfclass
== ELFCLASS64
)
8225 bfd_set_section_alignment (sec
, alignment
);
8226 elf_section_type (sec
) = SHT_NOTE
;
8228 /* GNU_PROPERTY_X86_ISA_1_USED: 4-byte type + 4-byte data size
8230 isa_1_descsz_raw
= 4 + 4 + 4;
8231 /* Align GNU_PROPERTY_X86_ISA_1_USED. */
8232 isa_1_descsz
= (isa_1_descsz_raw
+ align_size_1
) & ~align_size_1
;
8234 feature_2_descsz_raw
= isa_1_descsz
;
8235 /* GNU_PROPERTY_X86_FEATURE_2_USED: 4-byte type + 4-byte data size
8237 feature_2_descsz_raw
+= 4 + 4 + 4;
8238 /* Align GNU_PROPERTY_X86_FEATURE_2_USED. */
8239 feature_2_descsz
= ((feature_2_descsz_raw
+ align_size_1
)
8242 descsz
= feature_2_descsz
;
8243 /* Section size: n_namsz + n_descsz + n_type + n_name + n_descsz. */
8244 p
= frag_more (4 + 4 + 4 + 4 + descsz
);
8246 /* Write n_namsz. */
8247 md_number_to_chars (p
, (valueT
) 4, 4);
8249 /* Write n_descsz. */
8250 md_number_to_chars (p
+ 4, (valueT
) descsz
, 4);
8253 md_number_to_chars (p
+ 4 * 2, (valueT
) NT_GNU_PROPERTY_TYPE_0
, 4);
8256 memcpy (p
+ 4 * 3, "GNU", 4);
8258 /* Write 4-byte type. */
8259 md_number_to_chars (p
+ 4 * 4,
8260 (valueT
) GNU_PROPERTY_X86_ISA_1_USED
, 4);
8262 /* Write 4-byte data size. */
8263 md_number_to_chars (p
+ 4 * 5, (valueT
) 4, 4);
8265 /* Write 4-byte data. */
8266 md_number_to_chars (p
+ 4 * 6, (valueT
) x86_isa_1_used
, 4);
8268 /* Zero out paddings. */
8269 padding
= isa_1_descsz
- isa_1_descsz_raw
;
8271 memset (p
+ 4 * 7, 0, padding
);
8273 /* Write 4-byte type. */
8274 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 4,
8275 (valueT
) GNU_PROPERTY_X86_FEATURE_2_USED
, 4);
8277 /* Write 4-byte data size. */
8278 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 5, (valueT
) 4, 4);
8280 /* Write 4-byte data. */
8281 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 6,
8282 (valueT
) x86_feature_2_used
, 4);
8284 /* Zero out paddings. */
8285 padding
= feature_2_descsz
- feature_2_descsz_raw
;
8287 memset (p
+ isa_1_descsz
+ 4 * 7, 0, padding
);
8289 /* We probably can't restore the current segment, for there likely
8292 subseg_set (seg
, subseg
);
8297 encoding_length (const fragS
*start_frag
, offsetT start_off
,
8298 const char *frag_now_ptr
)
8300 unsigned int len
= 0;
8302 if (start_frag
!= frag_now
)
8304 const fragS
*fr
= start_frag
;
8309 } while (fr
&& fr
!= frag_now
);
8312 return len
- start_off
+ (frag_now_ptr
- frag_now
->fr_literal
);
8315 /* Return 1 for test, and, cmp, add, sub, inc and dec which may
8316 be macro-fused with conditional jumps. */
8319 maybe_fused_with_jcc_p (void)
8321 /* No RIP address. */
8322 if (i
.base_reg
&& i
.base_reg
->reg_num
== RegIP
)
8325 /* No VEX/EVEX encoding. */
8326 if (is_any_vex_encoding (&i
.tm
))
8329 /* and, add, sub with destination register. */
8330 if ((i
.tm
.base_opcode
>= 0x20 && i
.tm
.base_opcode
<= 0x25)
8331 || i
.tm
.base_opcode
<= 5
8332 || (i
.tm
.base_opcode
>= 0x28 && i
.tm
.base_opcode
<= 0x2d)
8333 || ((i
.tm
.base_opcode
| 3) == 0x83
8334 && ((i
.tm
.extension_opcode
| 1) == 0x5
8335 || i
.tm
.extension_opcode
== 0x0)))
8336 return (i
.types
[1].bitfield
.class == Reg
8337 || i
.types
[1].bitfield
.instance
== Accum
);
8339 /* test, cmp with any register. */
8340 if ((i
.tm
.base_opcode
| 1) == 0x85
8341 || (i
.tm
.base_opcode
| 1) == 0xa9
8342 || ((i
.tm
.base_opcode
| 1) == 0xf7
8343 && i
.tm
.extension_opcode
== 0)
8344 || (i
.tm
.base_opcode
>= 0x38 && i
.tm
.base_opcode
<= 0x3d)
8345 || ((i
.tm
.base_opcode
| 3) == 0x83
8346 && (i
.tm
.extension_opcode
== 0x7)))
8347 return (i
.types
[0].bitfield
.class == Reg
8348 || i
.types
[0].bitfield
.instance
== Accum
8349 || i
.types
[1].bitfield
.class == Reg
8350 || i
.types
[1].bitfield
.instance
== Accum
);
8352 /* inc, dec with any register. */
8353 if ((i
.tm
.cpu_flags
.bitfield
.cpuno64
8354 && (i
.tm
.base_opcode
| 0xf) == 0x4f)
8355 || ((i
.tm
.base_opcode
| 1) == 0xff
8356 && i
.tm
.extension_opcode
<= 0x1))
8357 return (i
.types
[0].bitfield
.class == Reg
8358 || i
.types
[0].bitfield
.instance
== Accum
);
8363 /* Return 1 if a FUSED_JCC_PADDING frag should be generated. */
8366 add_fused_jcc_padding_frag_p (void)
8368 /* NB: Don't work with COND_JUMP86 without i386. */
8369 if (!align_branch_power
8370 || now_seg
== absolute_section
8371 || !cpu_arch_flags
.bitfield
.cpui386
8372 || !(align_branch
& align_branch_fused_bit
))
8375 if (maybe_fused_with_jcc_p ())
8377 if (last_insn
.kind
== last_insn_other
8378 || last_insn
.seg
!= now_seg
)
8381 as_warn_where (last_insn
.file
, last_insn
.line
,
8382 _("`%s` skips -malign-branch-boundary on `%s`"),
8383 last_insn
.name
, i
.tm
.name
);
8389 /* Return 1 if a BRANCH_PREFIX frag should be generated. */
8392 add_branch_prefix_frag_p (void)
8394 /* NB: Don't work with COND_JUMP86 without i386. Don't add prefix
8395 to PadLock instructions since they include prefixes in opcode. */
8396 if (!align_branch_power
8397 || !align_branch_prefix_size
8398 || now_seg
== absolute_section
8399 || i
.tm
.cpu_flags
.bitfield
.cpupadlock
8400 || !cpu_arch_flags
.bitfield
.cpui386
)
8403 /* Don't add prefix if it is a prefix or there is no operand in case
8404 that segment prefix is special. */
8405 if (!i
.operands
|| i
.tm
.opcode_modifier
.isprefix
)
8408 if (last_insn
.kind
== last_insn_other
8409 || last_insn
.seg
!= now_seg
)
8413 as_warn_where (last_insn
.file
, last_insn
.line
,
8414 _("`%s` skips -malign-branch-boundary on `%s`"),
8415 last_insn
.name
, i
.tm
.name
);
8420 /* Return 1 if a BRANCH_PADDING frag should be generated. */
8423 add_branch_padding_frag_p (enum align_branch_kind
*branch_p
)
8427 /* NB: Don't work with COND_JUMP86 without i386. */
8428 if (!align_branch_power
8429 || now_seg
== absolute_section
8430 || !cpu_arch_flags
.bitfield
.cpui386
)
8435 /* Check for jcc and direct jmp. */
8436 if (i
.tm
.opcode_modifier
.jump
== JUMP
)
8438 if (i
.tm
.base_opcode
== JUMP_PC_RELATIVE
)
8440 *branch_p
= align_branch_jmp
;
8441 add_padding
= align_branch
& align_branch_jmp_bit
;
8445 *branch_p
= align_branch_jcc
;
8446 if ((align_branch
& align_branch_jcc_bit
))
8450 else if (is_any_vex_encoding (&i
.tm
))
8452 else if ((i
.tm
.base_opcode
| 1) == 0xc3)
8455 *branch_p
= align_branch_ret
;
8456 if ((align_branch
& align_branch_ret_bit
))
8461 /* Check for indirect jmp, direct and indirect calls. */
8462 if (i
.tm
.base_opcode
== 0xe8)
8465 *branch_p
= align_branch_call
;
8466 if ((align_branch
& align_branch_call_bit
))
8469 else if (i
.tm
.base_opcode
== 0xff
8470 && (i
.tm
.extension_opcode
== 2
8471 || i
.tm
.extension_opcode
== 4))
8473 /* Indirect call and jmp. */
8474 *branch_p
= align_branch_indirect
;
8475 if ((align_branch
& align_branch_indirect_bit
))
8482 && (i
.op
[0].disps
->X_op
== O_symbol
8483 || (i
.op
[0].disps
->X_op
== O_subtract
8484 && i
.op
[0].disps
->X_op_symbol
== GOT_symbol
)))
8486 symbolS
*s
= i
.op
[0].disps
->X_add_symbol
;
8487 /* No padding to call to global or undefined tls_get_addr. */
8488 if ((S_IS_EXTERNAL (s
) || !S_IS_DEFINED (s
))
8489 && strcmp (S_GET_NAME (s
), tls_get_addr
) == 0)
8495 && last_insn
.kind
!= last_insn_other
8496 && last_insn
.seg
== now_seg
)
8499 as_warn_where (last_insn
.file
, last_insn
.line
,
8500 _("`%s` skips -malign-branch-boundary on `%s`"),
8501 last_insn
.name
, i
.tm
.name
);
8511 fragS
*insn_start_frag
;
8512 offsetT insn_start_off
;
8513 fragS
*fragP
= NULL
;
8514 enum align_branch_kind branch
= align_branch_none
;
8516 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8517 if (IS_ELF
&& x86_used_note
)
8519 if (i
.tm
.cpu_flags
.bitfield
.cpucmov
)
8520 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_CMOV
;
8521 if (i
.tm
.cpu_flags
.bitfield
.cpusse
)
8522 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE
;
8523 if (i
.tm
.cpu_flags
.bitfield
.cpusse2
)
8524 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE2
;
8525 if (i
.tm
.cpu_flags
.bitfield
.cpusse3
)
8526 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE3
;
8527 if (i
.tm
.cpu_flags
.bitfield
.cpussse3
)
8528 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSSE3
;
8529 if (i
.tm
.cpu_flags
.bitfield
.cpusse4_1
)
8530 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE4_1
;
8531 if (i
.tm
.cpu_flags
.bitfield
.cpusse4_2
)
8532 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE4_2
;
8533 if (i
.tm
.cpu_flags
.bitfield
.cpuavx
)
8534 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX
;
8535 if (i
.tm
.cpu_flags
.bitfield
.cpuavx2
)
8536 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX2
;
8537 if (i
.tm
.cpu_flags
.bitfield
.cpufma
)
8538 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_FMA
;
8539 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512f
)
8540 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512F
;
8541 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512cd
)
8542 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512CD
;
8543 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512er
)
8544 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512ER
;
8545 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512pf
)
8546 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512PF
;
8547 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512vl
)
8548 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512VL
;
8549 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512dq
)
8550 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512DQ
;
8551 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512bw
)
8552 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512BW
;
8553 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_4fmaps
)
8554 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_4FMAPS
;
8555 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_4vnniw
)
8556 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_4VNNIW
;
8557 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_bitalg
)
8558 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_BITALG
;
8559 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512ifma
)
8560 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_IFMA
;
8561 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512vbmi
)
8562 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_VBMI
;
8563 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_vbmi2
)
8564 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_VBMI2
;
8565 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_vnni
)
8566 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_VNNI
;
8567 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_bf16
)
8568 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_BF16
;
8570 if (i
.tm
.cpu_flags
.bitfield
.cpu8087
8571 || i
.tm
.cpu_flags
.bitfield
.cpu287
8572 || i
.tm
.cpu_flags
.bitfield
.cpu387
8573 || i
.tm
.cpu_flags
.bitfield
.cpu687
8574 || i
.tm
.cpu_flags
.bitfield
.cpufisttp
)
8575 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_X87
;
8577 || i
.tm
.base_opcode
== 0xf77 /* emms */
8578 || i
.tm
.base_opcode
== 0xf0e /* femms */)
8579 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_MMX
;
8581 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XMM
;
8583 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_YMM
;
8585 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_ZMM
;
8586 if (i
.tm
.cpu_flags
.bitfield
.cpufxsr
)
8587 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_FXSR
;
8588 if (i
.tm
.cpu_flags
.bitfield
.cpuxsave
)
8589 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVE
;
8590 if (i
.tm
.cpu_flags
.bitfield
.cpuxsaveopt
)
8591 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVEOPT
;
8592 if (i
.tm
.cpu_flags
.bitfield
.cpuxsavec
)
8593 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVEC
;
8597 /* Tie dwarf2 debug info to the address at the start of the insn.
8598 We can't do this after the insn has been output as the current
8599 frag may have been closed off. eg. by frag_var. */
8600 dwarf2_emit_insn (0);
8602 insn_start_frag
= frag_now
;
8603 insn_start_off
= frag_now_fix ();
8605 if (add_branch_padding_frag_p (&branch
))
8608 /* Branch can be 8 bytes. Leave some room for prefixes. */
8609 unsigned int max_branch_padding_size
= 14;
8611 /* Align section to boundary. */
8612 record_alignment (now_seg
, align_branch_power
);
8614 /* Make room for padding. */
8615 frag_grow (max_branch_padding_size
);
8617 /* Start of the padding. */
8622 frag_var (rs_machine_dependent
, max_branch_padding_size
, 0,
8623 ENCODE_RELAX_STATE (BRANCH_PADDING
, 0),
8626 fragP
->tc_frag_data
.branch_type
= branch
;
8627 fragP
->tc_frag_data
.max_bytes
= max_branch_padding_size
;
8631 if (i
.tm
.opcode_modifier
.jump
== JUMP
)
8633 else if (i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
8634 || i
.tm
.opcode_modifier
.jump
== JUMP_DWORD
)
8636 else if (i
.tm
.opcode_modifier
.jump
== JUMP_INTERSEGMENT
)
8637 output_interseg_jump ();
8640 /* Output normal instructions here. */
8644 unsigned int prefix
;
8647 && (i
.tm
.base_opcode
== 0xfaee8
8648 || i
.tm
.base_opcode
== 0xfaef0
8649 || i
.tm
.base_opcode
== 0xfaef8))
8651 /* Encode lfence, mfence, and sfence as
8652 f0 83 04 24 00 lock addl $0x0, (%{re}sp). */
8653 offsetT val
= 0x240483f0ULL
;
8655 md_number_to_chars (p
, val
, 5);
8659 /* Some processors fail on LOCK prefix. This options makes
8660 assembler ignore LOCK prefix and serves as a workaround. */
8661 if (omit_lock_prefix
)
8663 if (i
.tm
.base_opcode
== LOCK_PREFIX_OPCODE
)
8665 i
.prefix
[LOCK_PREFIX
] = 0;
8669 /* Skip if this is a branch. */
8671 else if (add_fused_jcc_padding_frag_p ())
8673 /* Make room for padding. */
8674 frag_grow (MAX_FUSED_JCC_PADDING_SIZE
);
8679 frag_var (rs_machine_dependent
, MAX_FUSED_JCC_PADDING_SIZE
, 0,
8680 ENCODE_RELAX_STATE (FUSED_JCC_PADDING
, 0),
8683 fragP
->tc_frag_data
.branch_type
= align_branch_fused
;
8684 fragP
->tc_frag_data
.max_bytes
= MAX_FUSED_JCC_PADDING_SIZE
;
8686 else if (add_branch_prefix_frag_p ())
8688 unsigned int max_prefix_size
= align_branch_prefix_size
;
8690 /* Make room for padding. */
8691 frag_grow (max_prefix_size
);
8696 frag_var (rs_machine_dependent
, max_prefix_size
, 0,
8697 ENCODE_RELAX_STATE (BRANCH_PREFIX
, 0),
8700 fragP
->tc_frag_data
.max_bytes
= max_prefix_size
;
8703 /* Since the VEX/EVEX prefix contains the implicit prefix, we
8704 don't need the explicit prefix. */
8705 if (!i
.tm
.opcode_modifier
.vex
&& !i
.tm
.opcode_modifier
.evex
)
8707 switch (i
.tm
.opcode_length
)
8710 if (i
.tm
.base_opcode
& 0xff000000)
8712 prefix
= (i
.tm
.base_opcode
>> 24) & 0xff;
8713 if (!i
.tm
.cpu_flags
.bitfield
.cpupadlock
8714 || prefix
!= REPE_PREFIX_OPCODE
8715 || (i
.prefix
[REP_PREFIX
] != REPE_PREFIX_OPCODE
))
8716 add_prefix (prefix
);
8720 if ((i
.tm
.base_opcode
& 0xff0000) != 0)
8722 prefix
= (i
.tm
.base_opcode
>> 16) & 0xff;
8723 add_prefix (prefix
);
8729 /* Check for pseudo prefixes. */
8730 as_bad_where (insn_start_frag
->fr_file
,
8731 insn_start_frag
->fr_line
,
8732 _("pseudo prefix without instruction"));
8738 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
8739 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
8740 R_X86_64_GOTTPOFF relocation so that linker can safely
8741 perform IE->LE optimization. A dummy REX_OPCODE prefix
8742 is also needed for lea with R_X86_64_GOTPC32_TLSDESC
8743 relocation for GDesc -> IE/LE optimization. */
8744 if (x86_elf_abi
== X86_64_X32_ABI
8746 && (i
.reloc
[0] == BFD_RELOC_X86_64_GOTTPOFF
8747 || i
.reloc
[0] == BFD_RELOC_X86_64_GOTPC32_TLSDESC
)
8748 && i
.prefix
[REX_PREFIX
] == 0)
8749 add_prefix (REX_OPCODE
);
8752 /* The prefix bytes. */
8753 for (j
= ARRAY_SIZE (i
.prefix
), q
= i
.prefix
; j
> 0; j
--, q
++)
8755 FRAG_APPEND_1_CHAR (*q
);
8759 for (j
= 0, q
= i
.prefix
; j
< ARRAY_SIZE (i
.prefix
); j
++, q
++)
8764 /* REX byte is encoded in VEX prefix. */
8768 FRAG_APPEND_1_CHAR (*q
);
8771 /* There should be no other prefixes for instructions
8776 /* For EVEX instructions i.vrex should become 0 after
8777 build_evex_prefix. For VEX instructions upper 16 registers
8778 aren't available, so VREX should be 0. */
8781 /* Now the VEX prefix. */
8782 p
= frag_more (i
.vex
.length
);
8783 for (j
= 0; j
< i
.vex
.length
; j
++)
8784 p
[j
] = i
.vex
.bytes
[j
];
8787 /* Now the opcode; be careful about word order here! */
8788 if (i
.tm
.opcode_length
== 1)
8790 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
8794 switch (i
.tm
.opcode_length
)
8798 *p
++ = (i
.tm
.base_opcode
>> 24) & 0xff;
8799 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
8803 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
8813 /* Put out high byte first: can't use md_number_to_chars! */
8814 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
8815 *p
= i
.tm
.base_opcode
& 0xff;
8818 /* Now the modrm byte and sib byte (if present). */
8819 if (i
.tm
.opcode_modifier
.modrm
)
8821 FRAG_APPEND_1_CHAR ((i
.rm
.regmem
<< 0
8824 /* If i.rm.regmem == ESP (4)
8825 && i.rm.mode != (Register mode)
8827 ==> need second modrm byte. */
8828 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
8830 && !(i
.base_reg
&& i
.base_reg
->reg_type
.bitfield
.word
))
8831 FRAG_APPEND_1_CHAR ((i
.sib
.base
<< 0
8833 | i
.sib
.scale
<< 6));
8836 if (i
.disp_operands
)
8837 output_disp (insn_start_frag
, insn_start_off
);
8840 output_imm (insn_start_frag
, insn_start_off
);
8843 * frag_now_fix () returning plain abs_section_offset when we're in the
8844 * absolute section, and abs_section_offset not getting updated as data
8845 * gets added to the frag breaks the logic below.
8847 if (now_seg
!= absolute_section
)
8849 j
= encoding_length (insn_start_frag
, insn_start_off
, frag_more (0));
8851 as_warn (_("instruction length of %u bytes exceeds the limit of 15"),
8855 /* NB: Don't add prefix with GOTPC relocation since
8856 output_disp() above depends on the fixed encoding
8857 length. Can't add prefix with TLS relocation since
8858 it breaks TLS linker optimization. */
8859 unsigned int max
= i
.has_gotpc_tls_reloc
? 0 : 15 - j
;
8860 /* Prefix count on the current instruction. */
8861 unsigned int count
= i
.vex
.length
;
8863 for (k
= 0; k
< ARRAY_SIZE (i
.prefix
); k
++)
8864 /* REX byte is encoded in VEX/EVEX prefix. */
8865 if (i
.prefix
[k
] && (k
!= REX_PREFIX
|| !i
.vex
.length
))
8868 /* Count prefixes for extended opcode maps. */
8870 switch (i
.tm
.opcode_length
)
8873 if (((i
.tm
.base_opcode
>> 16) & 0xff) == 0xf)
8876 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
8888 if (((i
.tm
.base_opcode
>> 8) & 0xff) == 0xf)
8897 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
)
8900 /* Set the maximum prefix size in BRANCH_PREFIX
8902 if (fragP
->tc_frag_data
.max_bytes
> max
)
8903 fragP
->tc_frag_data
.max_bytes
= max
;
8904 if (fragP
->tc_frag_data
.max_bytes
> count
)
8905 fragP
->tc_frag_data
.max_bytes
-= count
;
8907 fragP
->tc_frag_data
.max_bytes
= 0;
8911 /* Remember the maximum prefix size in FUSED_JCC_PADDING
8913 unsigned int max_prefix_size
;
8914 if (align_branch_prefix_size
> max
)
8915 max_prefix_size
= max
;
8917 max_prefix_size
= align_branch_prefix_size
;
8918 if (max_prefix_size
> count
)
8919 fragP
->tc_frag_data
.max_prefix_length
8920 = max_prefix_size
- count
;
8923 /* Use existing segment prefix if possible. Use CS
8924 segment prefix in 64-bit mode. In 32-bit mode, use SS
8925 segment prefix with ESP/EBP base register and use DS
8926 segment prefix without ESP/EBP base register. */
8927 if (i
.prefix
[SEG_PREFIX
])
8928 fragP
->tc_frag_data
.default_prefix
= i
.prefix
[SEG_PREFIX
];
8929 else if (flag_code
== CODE_64BIT
)
8930 fragP
->tc_frag_data
.default_prefix
= CS_PREFIX_OPCODE
;
8932 && (i
.base_reg
->reg_num
== 4
8933 || i
.base_reg
->reg_num
== 5))
8934 fragP
->tc_frag_data
.default_prefix
= SS_PREFIX_OPCODE
;
8936 fragP
->tc_frag_data
.default_prefix
= DS_PREFIX_OPCODE
;
8941 /* NB: Don't work with COND_JUMP86 without i386. */
8942 if (align_branch_power
8943 && now_seg
!= absolute_section
8944 && cpu_arch_flags
.bitfield
.cpui386
)
8946 /* Terminate each frag so that we can add prefix and check for
8948 frag_wane (frag_now
);
8955 pi ("" /*line*/, &i
);
8957 #endif /* DEBUG386 */
8960 /* Return the size of the displacement operand N. */
8963 disp_size (unsigned int n
)
8967 if (i
.types
[n
].bitfield
.disp64
)
8969 else if (i
.types
[n
].bitfield
.disp8
)
8971 else if (i
.types
[n
].bitfield
.disp16
)
8976 /* Return the size of the immediate operand N. */
8979 imm_size (unsigned int n
)
8982 if (i
.types
[n
].bitfield
.imm64
)
8984 else if (i
.types
[n
].bitfield
.imm8
|| i
.types
[n
].bitfield
.imm8s
)
8986 else if (i
.types
[n
].bitfield
.imm16
)
8992 output_disp (fragS
*insn_start_frag
, offsetT insn_start_off
)
8997 for (n
= 0; n
< i
.operands
; n
++)
8999 if (operand_type_check (i
.types
[n
], disp
))
9001 if (i
.op
[n
].disps
->X_op
== O_constant
)
9003 int size
= disp_size (n
);
9004 offsetT val
= i
.op
[n
].disps
->X_add_number
;
9006 val
= offset_in_range (val
>> (size
== 1 ? i
.memshift
: 0),
9008 p
= frag_more (size
);
9009 md_number_to_chars (p
, val
, size
);
9013 enum bfd_reloc_code_real reloc_type
;
9014 int size
= disp_size (n
);
9015 int sign
= i
.types
[n
].bitfield
.disp32s
;
9016 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
9019 /* We can't have 8 bit displacement here. */
9020 gas_assert (!i
.types
[n
].bitfield
.disp8
);
9022 /* The PC relative address is computed relative
9023 to the instruction boundary, so in case immediate
9024 fields follows, we need to adjust the value. */
9025 if (pcrel
&& i
.imm_operands
)
9030 for (n1
= 0; n1
< i
.operands
; n1
++)
9031 if (operand_type_check (i
.types
[n1
], imm
))
9033 /* Only one immediate is allowed for PC
9034 relative address. */
9035 gas_assert (sz
== 0);
9037 i
.op
[n
].disps
->X_add_number
-= sz
;
9039 /* We should find the immediate. */
9040 gas_assert (sz
!= 0);
9043 p
= frag_more (size
);
9044 reloc_type
= reloc (size
, pcrel
, sign
, i
.reloc
[n
]);
9046 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
9047 && (((reloc_type
== BFD_RELOC_32
9048 || reloc_type
== BFD_RELOC_X86_64_32S
9049 || (reloc_type
== BFD_RELOC_64
9051 && (i
.op
[n
].disps
->X_op
== O_symbol
9052 || (i
.op
[n
].disps
->X_op
== O_add
9053 && ((symbol_get_value_expression
9054 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
9056 || reloc_type
== BFD_RELOC_32_PCREL
))
9060 reloc_type
= BFD_RELOC_386_GOTPC
;
9061 i
.has_gotpc_tls_reloc
= TRUE
;
9062 i
.op
[n
].imms
->X_add_number
+=
9063 encoding_length (insn_start_frag
, insn_start_off
, p
);
9065 else if (reloc_type
== BFD_RELOC_64
)
9066 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
9068 /* Don't do the adjustment for x86-64, as there
9069 the pcrel addressing is relative to the _next_
9070 insn, and that is taken care of in other code. */
9071 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
9073 else if (align_branch_power
)
9077 case BFD_RELOC_386_TLS_GD
:
9078 case BFD_RELOC_386_TLS_LDM
:
9079 case BFD_RELOC_386_TLS_IE
:
9080 case BFD_RELOC_386_TLS_IE_32
:
9081 case BFD_RELOC_386_TLS_GOTIE
:
9082 case BFD_RELOC_386_TLS_GOTDESC
:
9083 case BFD_RELOC_386_TLS_DESC_CALL
:
9084 case BFD_RELOC_X86_64_TLSGD
:
9085 case BFD_RELOC_X86_64_TLSLD
:
9086 case BFD_RELOC_X86_64_GOTTPOFF
:
9087 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
9088 case BFD_RELOC_X86_64_TLSDESC_CALL
:
9089 i
.has_gotpc_tls_reloc
= TRUE
;
9094 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
9095 size
, i
.op
[n
].disps
, pcrel
,
9097 /* Check for "call/jmp *mem", "mov mem, %reg",
9098 "test %reg, mem" and "binop mem, %reg" where binop
9099 is one of adc, add, and, cmp, or, sbb, sub, xor
9100 instructions without data prefix. Always generate
9101 R_386_GOT32X for "sym*GOT" operand in 32-bit mode. */
9102 if (i
.prefix
[DATA_PREFIX
] == 0
9103 && (generate_relax_relocations
9106 && i
.rm
.regmem
== 5))
9108 || (i
.rm
.mode
== 0 && i
.rm
.regmem
== 5))
9109 && !is_any_vex_encoding(&i
.tm
)
9110 && ((i
.operands
== 1
9111 && i
.tm
.base_opcode
== 0xff
9112 && (i
.rm
.reg
== 2 || i
.rm
.reg
== 4))
9114 && (i
.tm
.base_opcode
== 0x8b
9115 || i
.tm
.base_opcode
== 0x85
9116 || (i
.tm
.base_opcode
& ~0x38) == 0x03))))
9120 fixP
->fx_tcbit
= i
.rex
!= 0;
9122 && (i
.base_reg
->reg_num
== RegIP
))
9123 fixP
->fx_tcbit2
= 1;
9126 fixP
->fx_tcbit2
= 1;
9134 output_imm (fragS
*insn_start_frag
, offsetT insn_start_off
)
9139 for (n
= 0; n
< i
.operands
; n
++)
9141 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
9142 if (i
.rounding
&& (int) n
== i
.rounding
->operand
)
9145 if (operand_type_check (i
.types
[n
], imm
))
9147 if (i
.op
[n
].imms
->X_op
== O_constant
)
9149 int size
= imm_size (n
);
9152 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
9154 p
= frag_more (size
);
9155 md_number_to_chars (p
, val
, size
);
9159 /* Not absolute_section.
9160 Need a 32-bit fixup (don't support 8bit
9161 non-absolute imms). Try to support other
9163 enum bfd_reloc_code_real reloc_type
;
9164 int size
= imm_size (n
);
9167 if (i
.types
[n
].bitfield
.imm32s
9168 && (i
.suffix
== QWORD_MNEM_SUFFIX
9169 || (!i
.suffix
&& i
.tm
.opcode_modifier
.no_lsuf
)))
9174 p
= frag_more (size
);
9175 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
9177 /* This is tough to explain. We end up with this one if we
9178 * have operands that look like
9179 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
9180 * obtain the absolute address of the GOT, and it is strongly
9181 * preferable from a performance point of view to avoid using
9182 * a runtime relocation for this. The actual sequence of
9183 * instructions often look something like:
9188 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
9190 * The call and pop essentially return the absolute address
9191 * of the label .L66 and store it in %ebx. The linker itself
9192 * will ultimately change the first operand of the addl so
9193 * that %ebx points to the GOT, but to keep things simple, the
9194 * .o file must have this operand set so that it generates not
9195 * the absolute address of .L66, but the absolute address of
9196 * itself. This allows the linker itself simply treat a GOTPC
9197 * relocation as asking for a pcrel offset to the GOT to be
9198 * added in, and the addend of the relocation is stored in the
9199 * operand field for the instruction itself.
9201 * Our job here is to fix the operand so that it would add
9202 * the correct offset so that %ebx would point to itself. The
9203 * thing that is tricky is that .-.L66 will point to the
9204 * beginning of the instruction, so we need to further modify
9205 * the operand so that it will point to itself. There are
9206 * other cases where you have something like:
9208 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
9210 * and here no correction would be required. Internally in
9211 * the assembler we treat operands of this form as not being
9212 * pcrel since the '.' is explicitly mentioned, and I wonder
9213 * whether it would simplify matters to do it this way. Who
9214 * knows. In earlier versions of the PIC patches, the
9215 * pcrel_adjust field was used to store the correction, but
9216 * since the expression is not pcrel, I felt it would be
9217 * confusing to do it this way. */
9219 if ((reloc_type
== BFD_RELOC_32
9220 || reloc_type
== BFD_RELOC_X86_64_32S
9221 || reloc_type
== BFD_RELOC_64
)
9223 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
9224 && (i
.op
[n
].imms
->X_op
== O_symbol
9225 || (i
.op
[n
].imms
->X_op
== O_add
9226 && ((symbol_get_value_expression
9227 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
9231 reloc_type
= BFD_RELOC_386_GOTPC
;
9233 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
9235 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
9236 i
.has_gotpc_tls_reloc
= TRUE
;
9237 i
.op
[n
].imms
->X_add_number
+=
9238 encoding_length (insn_start_frag
, insn_start_off
, p
);
9240 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
9241 i
.op
[n
].imms
, 0, reloc_type
);
9247 /* x86_cons_fix_new is called via the expression parsing code when a
9248 reloc is needed. We use this hook to get the correct .got reloc. */
9249 static int cons_sign
= -1;
9252 x86_cons_fix_new (fragS
*frag
, unsigned int off
, unsigned int len
,
9253 expressionS
*exp
, bfd_reloc_code_real_type r
)
9255 r
= reloc (len
, 0, cons_sign
, r
);
9258 if (exp
->X_op
== O_secrel
)
9260 exp
->X_op
= O_symbol
;
9261 r
= BFD_RELOC_32_SECREL
;
9265 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
9268 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
9269 purpose of the `.dc.a' internal pseudo-op. */
9272 x86_address_bytes (void)
9274 if ((stdoutput
->arch_info
->mach
& bfd_mach_x64_32
))
9276 return stdoutput
->arch_info
->bits_per_address
/ 8;
9279 #if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
9281 # define lex_got(reloc, adjust, types) NULL
9283 /* Parse operands of the form
9284 <symbol>@GOTOFF+<nnn>
9285 and similar .plt or .got references.
9287 If we find one, set up the correct relocation in RELOC and copy the
9288 input string, minus the `@GOTOFF' into a malloc'd buffer for
9289 parsing by the calling routine. Return this buffer, and if ADJUST
9290 is non-null set it to the length of the string we removed from the
9291 input line. Otherwise return NULL. */
9293 lex_got (enum bfd_reloc_code_real
*rel
,
9295 i386_operand_type
*types
)
9297 /* Some of the relocations depend on the size of what field is to
9298 be relocated. But in our callers i386_immediate and i386_displacement
9299 we don't yet know the operand size (this will be set by insn
9300 matching). Hence we record the word32 relocation here,
9301 and adjust the reloc according to the real size in reloc(). */
9302 static const struct {
9305 const enum bfd_reloc_code_real rel
[2];
9306 const i386_operand_type types64
;
9308 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9309 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32
,
9311 OPERAND_TYPE_IMM32_64
},
9313 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real
,
9314 BFD_RELOC_X86_64_PLTOFF64
},
9315 OPERAND_TYPE_IMM64
},
9316 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32
,
9317 BFD_RELOC_X86_64_PLT32
},
9318 OPERAND_TYPE_IMM32_32S_DISP32
},
9319 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real
,
9320 BFD_RELOC_X86_64_GOTPLT64
},
9321 OPERAND_TYPE_IMM64_DISP64
},
9322 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF
,
9323 BFD_RELOC_X86_64_GOTOFF64
},
9324 OPERAND_TYPE_IMM64_DISP64
},
9325 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real
,
9326 BFD_RELOC_X86_64_GOTPCREL
},
9327 OPERAND_TYPE_IMM32_32S_DISP32
},
9328 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD
,
9329 BFD_RELOC_X86_64_TLSGD
},
9330 OPERAND_TYPE_IMM32_32S_DISP32
},
9331 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM
,
9332 _dummy_first_bfd_reloc_code_real
},
9333 OPERAND_TYPE_NONE
},
9334 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real
,
9335 BFD_RELOC_X86_64_TLSLD
},
9336 OPERAND_TYPE_IMM32_32S_DISP32
},
9337 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32
,
9338 BFD_RELOC_X86_64_GOTTPOFF
},
9339 OPERAND_TYPE_IMM32_32S_DISP32
},
9340 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32
,
9341 BFD_RELOC_X86_64_TPOFF32
},
9342 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
9343 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE
,
9344 _dummy_first_bfd_reloc_code_real
},
9345 OPERAND_TYPE_NONE
},
9346 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32
,
9347 BFD_RELOC_X86_64_DTPOFF32
},
9348 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
9349 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE
,
9350 _dummy_first_bfd_reloc_code_real
},
9351 OPERAND_TYPE_NONE
},
9352 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE
,
9353 _dummy_first_bfd_reloc_code_real
},
9354 OPERAND_TYPE_NONE
},
9355 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32
,
9356 BFD_RELOC_X86_64_GOT32
},
9357 OPERAND_TYPE_IMM32_32S_64_DISP32
},
9358 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC
,
9359 BFD_RELOC_X86_64_GOTPC32_TLSDESC
},
9360 OPERAND_TYPE_IMM32_32S_DISP32
},
9361 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL
,
9362 BFD_RELOC_X86_64_TLSDESC_CALL
},
9363 OPERAND_TYPE_IMM32_32S_DISP32
},
9368 #if defined (OBJ_MAYBE_ELF)
9373 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
9374 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
9377 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
9379 int len
= gotrel
[j
].len
;
9380 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
9382 if (gotrel
[j
].rel
[object_64bit
] != 0)
9385 char *tmpbuf
, *past_reloc
;
9387 *rel
= gotrel
[j
].rel
[object_64bit
];
9391 if (flag_code
!= CODE_64BIT
)
9393 types
->bitfield
.imm32
= 1;
9394 types
->bitfield
.disp32
= 1;
9397 *types
= gotrel
[j
].types64
;
9400 if (j
!= 0 && GOT_symbol
== NULL
)
9401 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
9403 /* The length of the first part of our input line. */
9404 first
= cp
- input_line_pointer
;
9406 /* The second part goes from after the reloc token until
9407 (and including) an end_of_line char or comma. */
9408 past_reloc
= cp
+ 1 + len
;
9410 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
9412 second
= cp
+ 1 - past_reloc
;
9414 /* Allocate and copy string. The trailing NUL shouldn't
9415 be necessary, but be safe. */
9416 tmpbuf
= XNEWVEC (char, first
+ second
+ 2);
9417 memcpy (tmpbuf
, input_line_pointer
, first
);
9418 if (second
!= 0 && *past_reloc
!= ' ')
9419 /* Replace the relocation token with ' ', so that
9420 errors like foo@GOTOFF1 will be detected. */
9421 tmpbuf
[first
++] = ' ';
9423 /* Increment length by 1 if the relocation token is
9428 memcpy (tmpbuf
+ first
, past_reloc
, second
);
9429 tmpbuf
[first
+ second
] = '\0';
9433 as_bad (_("@%s reloc is not supported with %d-bit output format"),
9434 gotrel
[j
].str
, 1 << (5 + object_64bit
));
9439 /* Might be a symbol version string. Don't as_bad here. */
9448 /* Parse operands of the form
9449 <symbol>@SECREL32+<nnn>
9451 If we find one, set up the correct relocation in RELOC and copy the
9452 input string, minus the `@SECREL32' into a malloc'd buffer for
9453 parsing by the calling routine. Return this buffer, and if ADJUST
9454 is non-null set it to the length of the string we removed from the
9455 input line. Otherwise return NULL.
9457 This function is copied from the ELF version above adjusted for PE targets. */
9460 lex_got (enum bfd_reloc_code_real
*rel ATTRIBUTE_UNUSED
,
9461 int *adjust ATTRIBUTE_UNUSED
,
9462 i386_operand_type
*types
)
9468 const enum bfd_reloc_code_real rel
[2];
9469 const i386_operand_type types64
;
9473 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL
,
9474 BFD_RELOC_32_SECREL
},
9475 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
9481 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
9482 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
9485 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
9487 int len
= gotrel
[j
].len
;
9489 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
9491 if (gotrel
[j
].rel
[object_64bit
] != 0)
9494 char *tmpbuf
, *past_reloc
;
9496 *rel
= gotrel
[j
].rel
[object_64bit
];
9502 if (flag_code
!= CODE_64BIT
)
9504 types
->bitfield
.imm32
= 1;
9505 types
->bitfield
.disp32
= 1;
9508 *types
= gotrel
[j
].types64
;
9511 /* The length of the first part of our input line. */
9512 first
= cp
- input_line_pointer
;
9514 /* The second part goes from after the reloc token until
9515 (and including) an end_of_line char or comma. */
9516 past_reloc
= cp
+ 1 + len
;
9518 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
9520 second
= cp
+ 1 - past_reloc
;
9522 /* Allocate and copy string. The trailing NUL shouldn't
9523 be necessary, but be safe. */
9524 tmpbuf
= XNEWVEC (char, first
+ second
+ 2);
9525 memcpy (tmpbuf
, input_line_pointer
, first
);
9526 if (second
!= 0 && *past_reloc
!= ' ')
9527 /* Replace the relocation token with ' ', so that
9528 errors like foo@SECLREL321 will be detected. */
9529 tmpbuf
[first
++] = ' ';
9530 memcpy (tmpbuf
+ first
, past_reloc
, second
);
9531 tmpbuf
[first
+ second
] = '\0';
9535 as_bad (_("@%s reloc is not supported with %d-bit output format"),
9536 gotrel
[j
].str
, 1 << (5 + object_64bit
));
9541 /* Might be a symbol version string. Don't as_bad here. */
9547 bfd_reloc_code_real_type
9548 x86_cons (expressionS
*exp
, int size
)
9550 bfd_reloc_code_real_type got_reloc
= NO_RELOC
;
9552 intel_syntax
= -intel_syntax
;
9555 if (size
== 4 || (object_64bit
&& size
== 8))
9557 /* Handle @GOTOFF and the like in an expression. */
9559 char *gotfree_input_line
;
9562 save
= input_line_pointer
;
9563 gotfree_input_line
= lex_got (&got_reloc
, &adjust
, NULL
);
9564 if (gotfree_input_line
)
9565 input_line_pointer
= gotfree_input_line
;
9569 if (gotfree_input_line
)
9571 /* expression () has merrily parsed up to the end of line,
9572 or a comma - in the wrong buffer. Transfer how far
9573 input_line_pointer has moved to the right buffer. */
9574 input_line_pointer
= (save
9575 + (input_line_pointer
- gotfree_input_line
)
9577 free (gotfree_input_line
);
9578 if (exp
->X_op
== O_constant
9579 || exp
->X_op
== O_absent
9580 || exp
->X_op
== O_illegal
9581 || exp
->X_op
== O_register
9582 || exp
->X_op
== O_big
)
9584 char c
= *input_line_pointer
;
9585 *input_line_pointer
= 0;
9586 as_bad (_("missing or invalid expression `%s'"), save
);
9587 *input_line_pointer
= c
;
9589 else if ((got_reloc
== BFD_RELOC_386_PLT32
9590 || got_reloc
== BFD_RELOC_X86_64_PLT32
)
9591 && exp
->X_op
!= O_symbol
)
9593 char c
= *input_line_pointer
;
9594 *input_line_pointer
= 0;
9595 as_bad (_("invalid PLT expression `%s'"), save
);
9596 *input_line_pointer
= c
;
9603 intel_syntax
= -intel_syntax
;
9606 i386_intel_simplify (exp
);
9612 signed_cons (int size
)
9614 if (flag_code
== CODE_64BIT
)
9622 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
9629 if (exp
.X_op
== O_symbol
)
9630 exp
.X_op
= O_secrel
;
9632 emit_expr (&exp
, 4);
9634 while (*input_line_pointer
++ == ',');
9636 input_line_pointer
--;
9637 demand_empty_rest_of_line ();
9641 /* Handle Vector operations. */
9644 check_VecOperations (char *op_string
, char *op_end
)
9646 const reg_entry
*mask
;
9651 && (op_end
== NULL
|| op_string
< op_end
))
9654 if (*op_string
== '{')
9658 /* Check broadcasts. */
9659 if (strncmp (op_string
, "1to", 3) == 0)
9664 goto duplicated_vec_op
;
9667 if (*op_string
== '8')
9669 else if (*op_string
== '4')
9671 else if (*op_string
== '2')
9673 else if (*op_string
== '1'
9674 && *(op_string
+1) == '6')
9681 as_bad (_("Unsupported broadcast: `%s'"), saved
);
9686 broadcast_op
.type
= bcst_type
;
9687 broadcast_op
.operand
= this_operand
;
9688 broadcast_op
.bytes
= 0;
9689 i
.broadcast
= &broadcast_op
;
9691 /* Check masking operation. */
9692 else if ((mask
= parse_register (op_string
, &end_op
)) != NULL
)
9694 /* k0 can't be used for write mask. */
9695 if (mask
->reg_type
.bitfield
.class != RegMask
|| !mask
->reg_num
)
9697 as_bad (_("`%s%s' can't be used for write mask"),
9698 register_prefix
, mask
->reg_name
);
9704 mask_op
.mask
= mask
;
9705 mask_op
.zeroing
= 0;
9706 mask_op
.operand
= this_operand
;
9712 goto duplicated_vec_op
;
9714 i
.mask
->mask
= mask
;
9716 /* Only "{z}" is allowed here. No need to check
9717 zeroing mask explicitly. */
9718 if (i
.mask
->operand
!= this_operand
)
9720 as_bad (_("invalid write mask `%s'"), saved
);
9727 /* Check zeroing-flag for masking operation. */
9728 else if (*op_string
== 'z')
9732 mask_op
.mask
= NULL
;
9733 mask_op
.zeroing
= 1;
9734 mask_op
.operand
= this_operand
;
9739 if (i
.mask
->zeroing
)
9742 as_bad (_("duplicated `%s'"), saved
);
9746 i
.mask
->zeroing
= 1;
9748 /* Only "{%k}" is allowed here. No need to check mask
9749 register explicitly. */
9750 if (i
.mask
->operand
!= this_operand
)
9752 as_bad (_("invalid zeroing-masking `%s'"),
9761 goto unknown_vec_op
;
9763 if (*op_string
!= '}')
9765 as_bad (_("missing `}' in `%s'"), saved
);
9770 /* Strip whitespace since the addition of pseudo prefixes
9771 changed how the scrubber treats '{'. */
9772 if (is_space_char (*op_string
))
9778 /* We don't know this one. */
9779 as_bad (_("unknown vector operation: `%s'"), saved
);
9783 if (i
.mask
&& i
.mask
->zeroing
&& !i
.mask
->mask
)
9785 as_bad (_("zeroing-masking only allowed with write mask"));
9793 i386_immediate (char *imm_start
)
9795 char *save_input_line_pointer
;
9796 char *gotfree_input_line
;
9799 i386_operand_type types
;
9801 operand_type_set (&types
, ~0);
9803 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
9805 as_bad (_("at most %d immediate operands are allowed"),
9806 MAX_IMMEDIATE_OPERANDS
);
9810 exp
= &im_expressions
[i
.imm_operands
++];
9811 i
.op
[this_operand
].imms
= exp
;
9813 if (is_space_char (*imm_start
))
9816 save_input_line_pointer
= input_line_pointer
;
9817 input_line_pointer
= imm_start
;
9819 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
9820 if (gotfree_input_line
)
9821 input_line_pointer
= gotfree_input_line
;
9823 exp_seg
= expression (exp
);
9827 /* Handle vector operations. */
9828 if (*input_line_pointer
== '{')
9830 input_line_pointer
= check_VecOperations (input_line_pointer
,
9832 if (input_line_pointer
== NULL
)
9836 if (*input_line_pointer
)
9837 as_bad (_("junk `%s' after expression"), input_line_pointer
);
9839 input_line_pointer
= save_input_line_pointer
;
9840 if (gotfree_input_line
)
9842 free (gotfree_input_line
);
9844 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
9845 exp
->X_op
= O_illegal
;
9848 return i386_finalize_immediate (exp_seg
, exp
, types
, imm_start
);
9852 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
9853 i386_operand_type types
, const char *imm_start
)
9855 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_illegal
|| exp
->X_op
== O_big
)
9858 as_bad (_("missing or invalid immediate expression `%s'"),
9862 else if (exp
->X_op
== O_constant
)
9864 /* Size it properly later. */
9865 i
.types
[this_operand
].bitfield
.imm64
= 1;
9866 /* If not 64bit, sign extend val. */
9867 if (flag_code
!= CODE_64BIT
9868 && (exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
9870 = (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
9872 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
9873 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
9874 && exp_seg
!= absolute_section
9875 && exp_seg
!= text_section
9876 && exp_seg
!= data_section
9877 && exp_seg
!= bss_section
9878 && exp_seg
!= undefined_section
9879 && !bfd_is_com_section (exp_seg
))
9881 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
9885 else if (!intel_syntax
&& exp_seg
== reg_section
)
9888 as_bad (_("illegal immediate register operand %s"), imm_start
);
9893 /* This is an address. The size of the address will be
9894 determined later, depending on destination register,
9895 suffix, or the default for the section. */
9896 i
.types
[this_operand
].bitfield
.imm8
= 1;
9897 i
.types
[this_operand
].bitfield
.imm16
= 1;
9898 i
.types
[this_operand
].bitfield
.imm32
= 1;
9899 i
.types
[this_operand
].bitfield
.imm32s
= 1;
9900 i
.types
[this_operand
].bitfield
.imm64
= 1;
9901 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
9909 i386_scale (char *scale
)
9912 char *save
= input_line_pointer
;
9914 input_line_pointer
= scale
;
9915 val
= get_absolute_expression ();
9920 i
.log2_scale_factor
= 0;
9923 i
.log2_scale_factor
= 1;
9926 i
.log2_scale_factor
= 2;
9929 i
.log2_scale_factor
= 3;
9933 char sep
= *input_line_pointer
;
9935 *input_line_pointer
= '\0';
9936 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
9938 *input_line_pointer
= sep
;
9939 input_line_pointer
= save
;
9943 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
9945 as_warn (_("scale factor of %d without an index register"),
9946 1 << i
.log2_scale_factor
);
9947 i
.log2_scale_factor
= 0;
9949 scale
= input_line_pointer
;
9950 input_line_pointer
= save
;
9955 i386_displacement (char *disp_start
, char *disp_end
)
9959 char *save_input_line_pointer
;
9960 char *gotfree_input_line
;
9962 i386_operand_type bigdisp
, types
= anydisp
;
9965 if (i
.disp_operands
== MAX_MEMORY_OPERANDS
)
9967 as_bad (_("at most %d displacement operands are allowed"),
9968 MAX_MEMORY_OPERANDS
);
9972 operand_type_set (&bigdisp
, 0);
9974 || i
.types
[this_operand
].bitfield
.baseindex
9975 || (current_templates
->start
->opcode_modifier
.jump
!= JUMP
9976 && current_templates
->start
->opcode_modifier
.jump
!= JUMP_DWORD
))
9978 i386_addressing_mode ();
9979 override
= (i
.prefix
[ADDR_PREFIX
] != 0);
9980 if (flag_code
== CODE_64BIT
)
9984 bigdisp
.bitfield
.disp32s
= 1;
9985 bigdisp
.bitfield
.disp64
= 1;
9988 bigdisp
.bitfield
.disp32
= 1;
9990 else if ((flag_code
== CODE_16BIT
) ^ override
)
9991 bigdisp
.bitfield
.disp16
= 1;
9993 bigdisp
.bitfield
.disp32
= 1;
9997 /* For PC-relative branches, the width of the displacement may be
9998 dependent upon data size, but is never dependent upon address size.
9999 Also make sure to not unintentionally match against a non-PC-relative
10000 branch template. */
10001 static templates aux_templates
;
10002 const insn_template
*t
= current_templates
->start
;
10003 bfd_boolean has_intel64
= FALSE
;
10005 aux_templates
.start
= t
;
10006 while (++t
< current_templates
->end
)
10008 if (t
->opcode_modifier
.jump
10009 != current_templates
->start
->opcode_modifier
.jump
)
10011 if ((t
->opcode_modifier
.isa64
>= INTEL64
))
10012 has_intel64
= TRUE
;
10014 if (t
< current_templates
->end
)
10016 aux_templates
.end
= t
;
10017 current_templates
= &aux_templates
;
10020 override
= (i
.prefix
[DATA_PREFIX
] != 0);
10021 if (flag_code
== CODE_64BIT
)
10023 if ((override
|| i
.suffix
== WORD_MNEM_SUFFIX
)
10024 && (!intel64
|| !has_intel64
))
10025 bigdisp
.bitfield
.disp16
= 1;
10027 bigdisp
.bitfield
.disp32s
= 1;
10032 override
= (i
.suffix
== (flag_code
!= CODE_16BIT
10034 : LONG_MNEM_SUFFIX
));
10035 bigdisp
.bitfield
.disp32
= 1;
10036 if ((flag_code
== CODE_16BIT
) ^ override
)
10038 bigdisp
.bitfield
.disp32
= 0;
10039 bigdisp
.bitfield
.disp16
= 1;
10043 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
10046 exp
= &disp_expressions
[i
.disp_operands
];
10047 i
.op
[this_operand
].disps
= exp
;
10049 save_input_line_pointer
= input_line_pointer
;
10050 input_line_pointer
= disp_start
;
10051 END_STRING_AND_SAVE (disp_end
);
10053 #ifndef GCC_ASM_O_HACK
10054 #define GCC_ASM_O_HACK 0
10057 END_STRING_AND_SAVE (disp_end
+ 1);
10058 if (i
.types
[this_operand
].bitfield
.baseIndex
10059 && displacement_string_end
[-1] == '+')
10061 /* This hack is to avoid a warning when using the "o"
10062 constraint within gcc asm statements.
10065 #define _set_tssldt_desc(n,addr,limit,type) \
10066 __asm__ __volatile__ ( \
10067 "movw %w2,%0\n\t" \
10068 "movw %w1,2+%0\n\t" \
10069 "rorl $16,%1\n\t" \
10070 "movb %b1,4+%0\n\t" \
10071 "movb %4,5+%0\n\t" \
10072 "movb $0,6+%0\n\t" \
10073 "movb %h1,7+%0\n\t" \
10075 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
10077 This works great except that the output assembler ends
10078 up looking a bit weird if it turns out that there is
10079 no offset. You end up producing code that looks like:
10092 So here we provide the missing zero. */
10094 *displacement_string_end
= '0';
10097 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
10098 if (gotfree_input_line
)
10099 input_line_pointer
= gotfree_input_line
;
10101 exp_seg
= expression (exp
);
10103 SKIP_WHITESPACE ();
10104 if (*input_line_pointer
)
10105 as_bad (_("junk `%s' after expression"), input_line_pointer
);
10107 RESTORE_END_STRING (disp_end
+ 1);
10109 input_line_pointer
= save_input_line_pointer
;
10110 if (gotfree_input_line
)
10112 free (gotfree_input_line
);
10114 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
10115 exp
->X_op
= O_illegal
;
10118 ret
= i386_finalize_displacement (exp_seg
, exp
, types
, disp_start
);
10120 RESTORE_END_STRING (disp_end
);
10126 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
10127 i386_operand_type types
, const char *disp_start
)
10129 i386_operand_type bigdisp
;
10132 /* We do this to make sure that the section symbol is in
10133 the symbol table. We will ultimately change the relocation
10134 to be relative to the beginning of the section. */
10135 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
10136 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
10137 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
10139 if (exp
->X_op
!= O_symbol
)
10142 if (S_IS_LOCAL (exp
->X_add_symbol
)
10143 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
10144 && S_GET_SEGMENT (exp
->X_add_symbol
) != expr_section
)
10145 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
10146 exp
->X_op
= O_subtract
;
10147 exp
->X_op_symbol
= GOT_symbol
;
10148 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
10149 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
10150 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
10151 i
.reloc
[this_operand
] = BFD_RELOC_64
;
10153 i
.reloc
[this_operand
] = BFD_RELOC_32
;
10156 else if (exp
->X_op
== O_absent
10157 || exp
->X_op
== O_illegal
10158 || exp
->X_op
== O_big
)
10161 as_bad (_("missing or invalid displacement expression `%s'"),
10166 else if (flag_code
== CODE_64BIT
10167 && !i
.prefix
[ADDR_PREFIX
]
10168 && exp
->X_op
== O_constant
)
10170 /* Since displacement is signed extended to 64bit, don't allow
10171 disp32 and turn off disp32s if they are out of range. */
10172 i
.types
[this_operand
].bitfield
.disp32
= 0;
10173 if (!fits_in_signed_long (exp
->X_add_number
))
10175 i
.types
[this_operand
].bitfield
.disp32s
= 0;
10176 if (i
.types
[this_operand
].bitfield
.baseindex
)
10178 as_bad (_("0x%lx out range of signed 32bit displacement"),
10179 (long) exp
->X_add_number
);
10185 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
10186 else if (exp
->X_op
!= O_constant
10187 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
10188 && exp_seg
!= absolute_section
10189 && exp_seg
!= text_section
10190 && exp_seg
!= data_section
10191 && exp_seg
!= bss_section
10192 && exp_seg
!= undefined_section
10193 && !bfd_is_com_section (exp_seg
))
10195 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
10200 if (current_templates
->start
->opcode_modifier
.jump
== JUMP_BYTE
10201 /* Constants get taken care of by optimize_disp(). */
10202 && exp
->X_op
!= O_constant
)
10203 i
.types
[this_operand
].bitfield
.disp8
= 1;
10205 /* Check if this is a displacement only operand. */
10206 bigdisp
= i
.types
[this_operand
];
10207 bigdisp
.bitfield
.disp8
= 0;
10208 bigdisp
.bitfield
.disp16
= 0;
10209 bigdisp
.bitfield
.disp32
= 0;
10210 bigdisp
.bitfield
.disp32s
= 0;
10211 bigdisp
.bitfield
.disp64
= 0;
10212 if (operand_type_all_zero (&bigdisp
))
10213 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
10219 /* Return the active addressing mode, taking address override and
10220 registers forming the address into consideration. Update the
10221 address override prefix if necessary. */
10223 static enum flag_code
10224 i386_addressing_mode (void)
10226 enum flag_code addr_mode
;
10228 if (i
.prefix
[ADDR_PREFIX
])
10229 addr_mode
= flag_code
== CODE_32BIT
? CODE_16BIT
: CODE_32BIT
;
10232 addr_mode
= flag_code
;
10234 #if INFER_ADDR_PREFIX
10235 if (i
.mem_operands
== 0)
10237 /* Infer address prefix from the first memory operand. */
10238 const reg_entry
*addr_reg
= i
.base_reg
;
10240 if (addr_reg
== NULL
)
10241 addr_reg
= i
.index_reg
;
10245 if (addr_reg
->reg_type
.bitfield
.dword
)
10246 addr_mode
= CODE_32BIT
;
10247 else if (flag_code
!= CODE_64BIT
10248 && addr_reg
->reg_type
.bitfield
.word
)
10249 addr_mode
= CODE_16BIT
;
10251 if (addr_mode
!= flag_code
)
10253 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
10255 /* Change the size of any displacement too. At most one
10256 of Disp16 or Disp32 is set.
10257 FIXME. There doesn't seem to be any real need for
10258 separate Disp16 and Disp32 flags. The same goes for
10259 Imm16 and Imm32. Removing them would probably clean
10260 up the code quite a lot. */
10261 if (flag_code
!= CODE_64BIT
10262 && (i
.types
[this_operand
].bitfield
.disp16
10263 || i
.types
[this_operand
].bitfield
.disp32
))
10264 i
.types
[this_operand
]
10265 = operand_type_xor (i
.types
[this_operand
], disp16_32
);
10275 /* Make sure the memory operand we've been dealt is valid.
10276 Return 1 on success, 0 on a failure. */
10279 i386_index_check (const char *operand_string
)
10281 const char *kind
= "base/index";
10282 enum flag_code addr_mode
= i386_addressing_mode ();
10284 if (current_templates
->start
->opcode_modifier
.isstring
10285 && !current_templates
->start
->cpu_flags
.bitfield
.cpupadlock
10286 && (current_templates
->end
[-1].opcode_modifier
.isstring
10287 || i
.mem_operands
))
10289 /* Memory operands of string insns are special in that they only allow
10290 a single register (rDI, rSI, or rBX) as their memory address. */
10291 const reg_entry
*expected_reg
;
10292 static const char *di_si
[][2] =
10298 static const char *bx
[] = { "ebx", "bx", "rbx" };
10300 kind
= "string address";
10302 if (current_templates
->start
->opcode_modifier
.repprefixok
)
10304 int es_op
= current_templates
->end
[-1].opcode_modifier
.isstring
10305 - IS_STRING_ES_OP0
;
10308 if (!current_templates
->end
[-1].operand_types
[0].bitfield
.baseindex
10309 || ((!i
.mem_operands
!= !intel_syntax
)
10310 && current_templates
->end
[-1].operand_types
[1]
10311 .bitfield
.baseindex
))
10313 expected_reg
= hash_find (reg_hash
, di_si
[addr_mode
][op
== es_op
]);
10316 expected_reg
= hash_find (reg_hash
, bx
[addr_mode
]);
10318 if (i
.base_reg
!= expected_reg
10320 || operand_type_check (i
.types
[this_operand
], disp
))
10322 /* The second memory operand must have the same size as
10326 && !((addr_mode
== CODE_64BIT
10327 && i
.base_reg
->reg_type
.bitfield
.qword
)
10328 || (addr_mode
== CODE_32BIT
10329 ? i
.base_reg
->reg_type
.bitfield
.dword
10330 : i
.base_reg
->reg_type
.bitfield
.word
)))
10333 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
10335 intel_syntax
? '[' : '(',
10337 expected_reg
->reg_name
,
10338 intel_syntax
? ']' : ')');
10345 as_bad (_("`%s' is not a valid %s expression"),
10346 operand_string
, kind
);
10351 if (addr_mode
!= CODE_16BIT
)
10353 /* 32-bit/64-bit checks. */
10355 && ((addr_mode
== CODE_64BIT
10356 ? !i
.base_reg
->reg_type
.bitfield
.qword
10357 : !i
.base_reg
->reg_type
.bitfield
.dword
)
10358 || (i
.index_reg
&& i
.base_reg
->reg_num
== RegIP
)
10359 || i
.base_reg
->reg_num
== RegIZ
))
10361 && !i
.index_reg
->reg_type
.bitfield
.xmmword
10362 && !i
.index_reg
->reg_type
.bitfield
.ymmword
10363 && !i
.index_reg
->reg_type
.bitfield
.zmmword
10364 && ((addr_mode
== CODE_64BIT
10365 ? !i
.index_reg
->reg_type
.bitfield
.qword
10366 : !i
.index_reg
->reg_type
.bitfield
.dword
)
10367 || !i
.index_reg
->reg_type
.bitfield
.baseindex
)))
10370 /* bndmk, bndldx, and bndstx have special restrictions. */
10371 if (current_templates
->start
->base_opcode
== 0xf30f1b
10372 || (current_templates
->start
->base_opcode
& ~1) == 0x0f1a)
10374 /* They cannot use RIP-relative addressing. */
10375 if (i
.base_reg
&& i
.base_reg
->reg_num
== RegIP
)
10377 as_bad (_("`%s' cannot be used here"), operand_string
);
10381 /* bndldx and bndstx ignore their scale factor. */
10382 if (current_templates
->start
->base_opcode
!= 0xf30f1b
10383 && i
.log2_scale_factor
)
10384 as_warn (_("register scaling is being ignored here"));
10389 /* 16-bit checks. */
10391 && (!i
.base_reg
->reg_type
.bitfield
.word
10392 || !i
.base_reg
->reg_type
.bitfield
.baseindex
))
10394 && (!i
.index_reg
->reg_type
.bitfield
.word
10395 || !i
.index_reg
->reg_type
.bitfield
.baseindex
10397 && i
.base_reg
->reg_num
< 6
10398 && i
.index_reg
->reg_num
>= 6
10399 && i
.log2_scale_factor
== 0))))
10406 /* Handle vector immediates. */
10409 RC_SAE_immediate (const char *imm_start
)
10411 unsigned int match_found
, j
;
10412 const char *pstr
= imm_start
;
10420 for (j
= 0; j
< ARRAY_SIZE (RC_NamesTable
); j
++)
10422 if (!strncmp (pstr
, RC_NamesTable
[j
].name
, RC_NamesTable
[j
].len
))
10426 rc_op
.type
= RC_NamesTable
[j
].type
;
10427 rc_op
.operand
= this_operand
;
10428 i
.rounding
= &rc_op
;
10432 as_bad (_("duplicated `%s'"), imm_start
);
10435 pstr
+= RC_NamesTable
[j
].len
;
10443 if (*pstr
++ != '}')
10445 as_bad (_("Missing '}': '%s'"), imm_start
);
10448 /* RC/SAE immediate string should contain nothing more. */;
10451 as_bad (_("Junk after '}': '%s'"), imm_start
);
10455 exp
= &im_expressions
[i
.imm_operands
++];
10456 i
.op
[this_operand
].imms
= exp
;
10458 exp
->X_op
= O_constant
;
10459 exp
->X_add_number
= 0;
10460 exp
->X_add_symbol
= (symbolS
*) 0;
10461 exp
->X_op_symbol
= (symbolS
*) 0;
10463 i
.types
[this_operand
].bitfield
.imm8
= 1;
10467 /* Only string instructions can have a second memory operand, so
10468 reduce current_templates to just those if it contains any. */
10470 maybe_adjust_templates (void)
10472 const insn_template
*t
;
10474 gas_assert (i
.mem_operands
== 1);
10476 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
10477 if (t
->opcode_modifier
.isstring
)
10480 if (t
< current_templates
->end
)
10482 static templates aux_templates
;
10483 bfd_boolean recheck
;
10485 aux_templates
.start
= t
;
10486 for (; t
< current_templates
->end
; ++t
)
10487 if (!t
->opcode_modifier
.isstring
)
10489 aux_templates
.end
= t
;
10491 /* Determine whether to re-check the first memory operand. */
10492 recheck
= (aux_templates
.start
!= current_templates
->start
10493 || t
!= current_templates
->end
);
10495 current_templates
= &aux_templates
;
10499 i
.mem_operands
= 0;
10500 if (i
.memop1_string
!= NULL
10501 && i386_index_check (i
.memop1_string
) == 0)
10503 i
.mem_operands
= 1;
10510 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
10514 i386_att_operand (char *operand_string
)
10516 const reg_entry
*r
;
10518 char *op_string
= operand_string
;
10520 if (is_space_char (*op_string
))
10523 /* We check for an absolute prefix (differentiating,
10524 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
10525 if (*op_string
== ABSOLUTE_PREFIX
)
10528 if (is_space_char (*op_string
))
10530 i
.jumpabsolute
= TRUE
;
10533 /* Check if operand is a register. */
10534 if ((r
= parse_register (op_string
, &end_op
)) != NULL
)
10536 i386_operand_type temp
;
10538 /* Check for a segment override by searching for ':' after a
10539 segment register. */
10540 op_string
= end_op
;
10541 if (is_space_char (*op_string
))
10543 if (*op_string
== ':' && r
->reg_type
.bitfield
.class == SReg
)
10545 switch (r
->reg_num
)
10548 i
.seg
[i
.mem_operands
] = &es
;
10551 i
.seg
[i
.mem_operands
] = &cs
;
10554 i
.seg
[i
.mem_operands
] = &ss
;
10557 i
.seg
[i
.mem_operands
] = &ds
;
10560 i
.seg
[i
.mem_operands
] = &fs
;
10563 i
.seg
[i
.mem_operands
] = &gs
;
10567 /* Skip the ':' and whitespace. */
10569 if (is_space_char (*op_string
))
10572 if (!is_digit_char (*op_string
)
10573 && !is_identifier_char (*op_string
)
10574 && *op_string
!= '('
10575 && *op_string
!= ABSOLUTE_PREFIX
)
10577 as_bad (_("bad memory operand `%s'"), op_string
);
10580 /* Handle case of %es:*foo. */
10581 if (*op_string
== ABSOLUTE_PREFIX
)
10584 if (is_space_char (*op_string
))
10586 i
.jumpabsolute
= TRUE
;
10588 goto do_memory_reference
;
10591 /* Handle vector operations. */
10592 if (*op_string
== '{')
10594 op_string
= check_VecOperations (op_string
, NULL
);
10595 if (op_string
== NULL
)
10601 as_bad (_("junk `%s' after register"), op_string
);
10604 temp
= r
->reg_type
;
10605 temp
.bitfield
.baseindex
= 0;
10606 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
10608 i
.types
[this_operand
].bitfield
.unspecified
= 0;
10609 i
.op
[this_operand
].regs
= r
;
10612 else if (*op_string
== REGISTER_PREFIX
)
10614 as_bad (_("bad register name `%s'"), op_string
);
10617 else if (*op_string
== IMMEDIATE_PREFIX
)
10620 if (i
.jumpabsolute
)
10622 as_bad (_("immediate operand illegal with absolute jump"));
10625 if (!i386_immediate (op_string
))
10628 else if (RC_SAE_immediate (operand_string
))
10630 /* If it is a RC or SAE immediate, do nothing. */
10633 else if (is_digit_char (*op_string
)
10634 || is_identifier_char (*op_string
)
10635 || *op_string
== '"'
10636 || *op_string
== '(')
10638 /* This is a memory reference of some sort. */
10641 /* Start and end of displacement string expression (if found). */
10642 char *displacement_string_start
;
10643 char *displacement_string_end
;
10646 do_memory_reference
:
10647 if (i
.mem_operands
== 1 && !maybe_adjust_templates ())
10649 if ((i
.mem_operands
== 1
10650 && !current_templates
->start
->opcode_modifier
.isstring
)
10651 || i
.mem_operands
== 2)
10653 as_bad (_("too many memory references for `%s'"),
10654 current_templates
->start
->name
);
10658 /* Check for base index form. We detect the base index form by
10659 looking for an ')' at the end of the operand, searching
10660 for the '(' matching it, and finding a REGISTER_PREFIX or ','
10662 base_string
= op_string
+ strlen (op_string
);
10664 /* Handle vector operations. */
10665 vop_start
= strchr (op_string
, '{');
10666 if (vop_start
&& vop_start
< base_string
)
10668 if (check_VecOperations (vop_start
, base_string
) == NULL
)
10670 base_string
= vop_start
;
10674 if (is_space_char (*base_string
))
10677 /* If we only have a displacement, set-up for it to be parsed later. */
10678 displacement_string_start
= op_string
;
10679 displacement_string_end
= base_string
+ 1;
10681 if (*base_string
== ')')
10684 unsigned int parens_balanced
= 1;
10685 /* We've already checked that the number of left & right ()'s are
10686 equal, so this loop will not be infinite. */
10690 if (*base_string
== ')')
10692 if (*base_string
== '(')
10695 while (parens_balanced
);
10697 temp_string
= base_string
;
10699 /* Skip past '(' and whitespace. */
10701 if (is_space_char (*base_string
))
10704 if (*base_string
== ','
10705 || ((i
.base_reg
= parse_register (base_string
, &end_op
))
10708 displacement_string_end
= temp_string
;
10710 i
.types
[this_operand
].bitfield
.baseindex
= 1;
10714 base_string
= end_op
;
10715 if (is_space_char (*base_string
))
10719 /* There may be an index reg or scale factor here. */
10720 if (*base_string
== ',')
10723 if (is_space_char (*base_string
))
10726 if ((i
.index_reg
= parse_register (base_string
, &end_op
))
10729 base_string
= end_op
;
10730 if (is_space_char (*base_string
))
10732 if (*base_string
== ',')
10735 if (is_space_char (*base_string
))
10738 else if (*base_string
!= ')')
10740 as_bad (_("expecting `,' or `)' "
10741 "after index register in `%s'"),
10746 else if (*base_string
== REGISTER_PREFIX
)
10748 end_op
= strchr (base_string
, ',');
10751 as_bad (_("bad register name `%s'"), base_string
);
10755 /* Check for scale factor. */
10756 if (*base_string
!= ')')
10758 char *end_scale
= i386_scale (base_string
);
10763 base_string
= end_scale
;
10764 if (is_space_char (*base_string
))
10766 if (*base_string
!= ')')
10768 as_bad (_("expecting `)' "
10769 "after scale factor in `%s'"),
10774 else if (!i
.index_reg
)
10776 as_bad (_("expecting index register or scale factor "
10777 "after `,'; got '%c'"),
10782 else if (*base_string
!= ')')
10784 as_bad (_("expecting `,' or `)' "
10785 "after base register in `%s'"),
10790 else if (*base_string
== REGISTER_PREFIX
)
10792 end_op
= strchr (base_string
, ',');
10795 as_bad (_("bad register name `%s'"), base_string
);
10800 /* If there's an expression beginning the operand, parse it,
10801 assuming displacement_string_start and
10802 displacement_string_end are meaningful. */
10803 if (displacement_string_start
!= displacement_string_end
)
10805 if (!i386_displacement (displacement_string_start
,
10806 displacement_string_end
))
10810 /* Special case for (%dx) while doing input/output op. */
10812 && i
.base_reg
->reg_type
.bitfield
.instance
== RegD
10813 && i
.base_reg
->reg_type
.bitfield
.word
10814 && i
.index_reg
== 0
10815 && i
.log2_scale_factor
== 0
10816 && i
.seg
[i
.mem_operands
] == 0
10817 && !operand_type_check (i
.types
[this_operand
], disp
))
10819 i
.types
[this_operand
] = i
.base_reg
->reg_type
;
10823 if (i386_index_check (operand_string
) == 0)
10825 i
.flags
[this_operand
] |= Operand_Mem
;
10826 if (i
.mem_operands
== 0)
10827 i
.memop1_string
= xstrdup (operand_string
);
10832 /* It's not a memory operand; argh! */
10833 as_bad (_("invalid char %s beginning operand %d `%s'"),
10834 output_invalid (*op_string
),
10839 return 1; /* Normal return. */
10842 /* Calculate the maximum variable size (i.e., excluding fr_fix)
10843 that an rs_machine_dependent frag may reach. */
10846 i386_frag_max_var (fragS
*frag
)
10848 /* The only relaxable frags are for jumps.
10849 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
10850 gas_assert (frag
->fr_type
== rs_machine_dependent
);
10851 return TYPE_FROM_RELAX_STATE (frag
->fr_subtype
) == UNCOND_JUMP
? 4 : 5;
10854 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10856 elf_symbol_resolved_in_segment_p (symbolS
*fr_symbol
, offsetT fr_var
)
10858 /* STT_GNU_IFUNC symbol must go through PLT. */
10859 if ((symbol_get_bfdsym (fr_symbol
)->flags
10860 & BSF_GNU_INDIRECT_FUNCTION
) != 0)
10863 if (!S_IS_EXTERNAL (fr_symbol
))
10864 /* Symbol may be weak or local. */
10865 return !S_IS_WEAK (fr_symbol
);
10867 /* Global symbols with non-default visibility can't be preempted. */
10868 if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol
)) != STV_DEFAULT
)
10871 if (fr_var
!= NO_RELOC
)
10872 switch ((enum bfd_reloc_code_real
) fr_var
)
10874 case BFD_RELOC_386_PLT32
:
10875 case BFD_RELOC_X86_64_PLT32
:
10876 /* Symbol with PLT relocation may be preempted. */
10882 /* Global symbols with default visibility in a shared library may be
10883 preempted by another definition. */
10888 /* Return the next non-empty frag. */
10891 i386_next_non_empty_frag (fragS
*fragP
)
10893 /* There may be a frag with a ".fill 0" when there is no room in
10894 the current frag for frag_grow in output_insn. */
10895 for (fragP
= fragP
->fr_next
;
10897 && fragP
->fr_type
== rs_fill
10898 && fragP
->fr_fix
== 0);
10899 fragP
= fragP
->fr_next
)
10904 /* Return the next jcc frag after BRANCH_PADDING. */
10907 i386_next_jcc_frag (fragS
*fragP
)
10912 if (fragP
->fr_type
== rs_machine_dependent
10913 && (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
)
10914 == BRANCH_PADDING
))
10916 fragP
= i386_next_non_empty_frag (fragP
);
10917 if (fragP
->fr_type
!= rs_machine_dependent
)
10919 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == COND_JUMP
)
10926 /* Classify BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING frags. */
10929 i386_classify_machine_dependent_frag (fragS
*fragP
)
10933 fragS
*branch_fragP
;
10935 unsigned int max_prefix_length
;
10937 if (fragP
->tc_frag_data
.classified
)
10940 /* First scan for BRANCH_PADDING and FUSED_JCC_PADDING. Convert
10941 FUSED_JCC_PADDING and merge BRANCH_PADDING. */
10942 for (next_fragP
= fragP
;
10943 next_fragP
!= NULL
;
10944 next_fragP
= next_fragP
->fr_next
)
10946 next_fragP
->tc_frag_data
.classified
= 1;
10947 if (next_fragP
->fr_type
== rs_machine_dependent
)
10948 switch (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
))
10950 case BRANCH_PADDING
:
10951 /* The BRANCH_PADDING frag must be followed by a branch
10953 branch_fragP
= i386_next_non_empty_frag (next_fragP
);
10954 next_fragP
->tc_frag_data
.u
.branch_fragP
= branch_fragP
;
10956 case FUSED_JCC_PADDING
:
10957 /* Check if this is a fused jcc:
10959 CMP like instruction
10963 cmp_fragP
= i386_next_non_empty_frag (next_fragP
);
10964 pad_fragP
= i386_next_non_empty_frag (cmp_fragP
);
10965 branch_fragP
= i386_next_jcc_frag (pad_fragP
);
10968 /* The BRANCH_PADDING frag is merged with the
10969 FUSED_JCC_PADDING frag. */
10970 next_fragP
->tc_frag_data
.u
.branch_fragP
= branch_fragP
;
10971 /* CMP like instruction size. */
10972 next_fragP
->tc_frag_data
.cmp_size
= cmp_fragP
->fr_fix
;
10973 frag_wane (pad_fragP
);
10974 /* Skip to branch_fragP. */
10975 next_fragP
= branch_fragP
;
10977 else if (next_fragP
->tc_frag_data
.max_prefix_length
)
10979 /* Turn FUSED_JCC_PADDING into BRANCH_PREFIX if it isn't
10981 next_fragP
->fr_subtype
10982 = ENCODE_RELAX_STATE (BRANCH_PREFIX
, 0);
10983 next_fragP
->tc_frag_data
.max_bytes
10984 = next_fragP
->tc_frag_data
.max_prefix_length
;
10985 /* This will be updated in the BRANCH_PREFIX scan. */
10986 next_fragP
->tc_frag_data
.max_prefix_length
= 0;
10989 frag_wane (next_fragP
);
10994 /* Stop if there is no BRANCH_PREFIX. */
10995 if (!align_branch_prefix_size
)
10998 /* Scan for BRANCH_PREFIX. */
10999 for (; fragP
!= NULL
; fragP
= fragP
->fr_next
)
11001 if (fragP
->fr_type
!= rs_machine_dependent
11002 || (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
)
11006 /* Count all BRANCH_PREFIX frags before BRANCH_PADDING and
11007 COND_JUMP_PREFIX. */
11008 max_prefix_length
= 0;
11009 for (next_fragP
= fragP
;
11010 next_fragP
!= NULL
;
11011 next_fragP
= next_fragP
->fr_next
)
11013 if (next_fragP
->fr_type
== rs_fill
)
11014 /* Skip rs_fill frags. */
11016 else if (next_fragP
->fr_type
!= rs_machine_dependent
)
11017 /* Stop for all other frags. */
11020 /* rs_machine_dependent frags. */
11021 if (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
11024 /* Count BRANCH_PREFIX frags. */
11025 if (max_prefix_length
>= MAX_FUSED_JCC_PADDING_SIZE
)
11027 max_prefix_length
= MAX_FUSED_JCC_PADDING_SIZE
;
11028 frag_wane (next_fragP
);
11032 += next_fragP
->tc_frag_data
.max_bytes
;
11034 else if ((TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
11036 || (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
11037 == FUSED_JCC_PADDING
))
11039 /* Stop at BRANCH_PADDING and FUSED_JCC_PADDING. */
11040 fragP
->tc_frag_data
.u
.padding_fragP
= next_fragP
;
11044 /* Stop for other rs_machine_dependent frags. */
11048 fragP
->tc_frag_data
.max_prefix_length
= max_prefix_length
;
11050 /* Skip to the next frag. */
11051 fragP
= next_fragP
;
11055 /* Compute padding size for
11058 CMP like instruction
11060 COND_JUMP/UNCOND_JUMP
11065 COND_JUMP/UNCOND_JUMP
11069 i386_branch_padding_size (fragS
*fragP
, offsetT address
)
11071 unsigned int offset
, size
, padding_size
;
11072 fragS
*branch_fragP
= fragP
->tc_frag_data
.u
.branch_fragP
;
11074 /* The start address of the BRANCH_PADDING or FUSED_JCC_PADDING frag. */
11076 address
= fragP
->fr_address
;
11077 address
+= fragP
->fr_fix
;
11079 /* CMP like instrunction size. */
11080 size
= fragP
->tc_frag_data
.cmp_size
;
11082 /* The base size of the branch frag. */
11083 size
+= branch_fragP
->fr_fix
;
11085 /* Add opcode and displacement bytes for the rs_machine_dependent
11087 if (branch_fragP
->fr_type
== rs_machine_dependent
)
11088 size
+= md_relax_table
[branch_fragP
->fr_subtype
].rlx_length
;
11090 /* Check if branch is within boundary and doesn't end at the last
11092 offset
= address
& ((1U << align_branch_power
) - 1);
11093 if ((offset
+ size
) >= (1U << align_branch_power
))
11094 /* Padding needed to avoid crossing boundary. */
11095 padding_size
= (1U << align_branch_power
) - offset
;
11097 /* No padding needed. */
11100 /* The return value may be saved in tc_frag_data.length which is
11102 if (!fits_in_unsigned_byte (padding_size
))
11105 return padding_size
;
11108 /* i386_generic_table_relax_frag()
11110 Handle BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING frags to
11111 grow/shrink padding to align branch frags. Hand others to
11115 i386_generic_table_relax_frag (segT segment
, fragS
*fragP
, long stretch
)
11117 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
11118 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
)
11120 long padding_size
= i386_branch_padding_size (fragP
, 0);
11121 long grow
= padding_size
- fragP
->tc_frag_data
.length
;
11123 /* When the BRANCH_PREFIX frag is used, the computed address
11124 must match the actual address and there should be no padding. */
11125 if (fragP
->tc_frag_data
.padding_address
11126 && (fragP
->tc_frag_data
.padding_address
!= fragP
->fr_address
11130 /* Update the padding size. */
11132 fragP
->tc_frag_data
.length
= padding_size
;
11136 else if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
)
11138 fragS
*padding_fragP
, *next_fragP
;
11139 long padding_size
, left_size
, last_size
;
11141 padding_fragP
= fragP
->tc_frag_data
.u
.padding_fragP
;
11142 if (!padding_fragP
)
11143 /* Use the padding set by the leading BRANCH_PREFIX frag. */
11144 return (fragP
->tc_frag_data
.length
11145 - fragP
->tc_frag_data
.last_length
);
11147 /* Compute the relative address of the padding frag in the very
11148 first time where the BRANCH_PREFIX frag sizes are zero. */
11149 if (!fragP
->tc_frag_data
.padding_address
)
11150 fragP
->tc_frag_data
.padding_address
11151 = padding_fragP
->fr_address
- (fragP
->fr_address
- stretch
);
11153 /* First update the last length from the previous interation. */
11154 left_size
= fragP
->tc_frag_data
.prefix_length
;
11155 for (next_fragP
= fragP
;
11156 next_fragP
!= padding_fragP
;
11157 next_fragP
= next_fragP
->fr_next
)
11158 if (next_fragP
->fr_type
== rs_machine_dependent
11159 && (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
11164 int max
= next_fragP
->tc_frag_data
.max_bytes
;
11168 if (max
> left_size
)
11173 next_fragP
->tc_frag_data
.last_length
= size
;
11177 next_fragP
->tc_frag_data
.last_length
= 0;
11180 /* Check the padding size for the padding frag. */
11181 padding_size
= i386_branch_padding_size
11182 (padding_fragP
, (fragP
->fr_address
11183 + fragP
->tc_frag_data
.padding_address
));
11185 last_size
= fragP
->tc_frag_data
.prefix_length
;
11186 /* Check if there is change from the last interation. */
11187 if (padding_size
== last_size
)
11189 /* Update the expected address of the padding frag. */
11190 padding_fragP
->tc_frag_data
.padding_address
11191 = (fragP
->fr_address
+ padding_size
11192 + fragP
->tc_frag_data
.padding_address
);
11196 if (padding_size
> fragP
->tc_frag_data
.max_prefix_length
)
11198 /* No padding if there is no sufficient room. Clear the
11199 expected address of the padding frag. */
11200 padding_fragP
->tc_frag_data
.padding_address
= 0;
11204 /* Store the expected address of the padding frag. */
11205 padding_fragP
->tc_frag_data
.padding_address
11206 = (fragP
->fr_address
+ padding_size
11207 + fragP
->tc_frag_data
.padding_address
);
11209 fragP
->tc_frag_data
.prefix_length
= padding_size
;
11211 /* Update the length for the current interation. */
11212 left_size
= padding_size
;
11213 for (next_fragP
= fragP
;
11214 next_fragP
!= padding_fragP
;
11215 next_fragP
= next_fragP
->fr_next
)
11216 if (next_fragP
->fr_type
== rs_machine_dependent
11217 && (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
11222 int max
= next_fragP
->tc_frag_data
.max_bytes
;
11226 if (max
> left_size
)
11231 next_fragP
->tc_frag_data
.length
= size
;
11235 next_fragP
->tc_frag_data
.length
= 0;
11238 return (fragP
->tc_frag_data
.length
11239 - fragP
->tc_frag_data
.last_length
);
11241 return relax_frag (segment
, fragP
, stretch
);
11244 /* md_estimate_size_before_relax()
11246 Called just before relax() for rs_machine_dependent frags. The x86
11247 assembler uses these frags to handle variable size jump
11250 Any symbol that is now undefined will not become defined.
11251 Return the correct fr_subtype in the frag.
11252 Return the initial "guess for variable size of frag" to caller.
11253 The guess is actually the growth beyond the fixed part. Whatever
11254 we do to grow the fixed or variable part contributes to our
11258 md_estimate_size_before_relax (fragS
*fragP
, segT segment
)
11260 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
11261 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
11262 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
)
11264 i386_classify_machine_dependent_frag (fragP
);
11265 return fragP
->tc_frag_data
.length
;
11268 /* We've already got fragP->fr_subtype right; all we have to do is
11269 check for un-relaxable symbols. On an ELF system, we can't relax
11270 an externally visible symbol, because it may be overridden by a
11272 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
11273 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11275 && !elf_symbol_resolved_in_segment_p (fragP
->fr_symbol
,
11278 #if defined (OBJ_COFF) && defined (TE_PE)
11279 || (OUTPUT_FLAVOR
== bfd_target_coff_flavour
11280 && S_IS_WEAK (fragP
->fr_symbol
))
11284 /* Symbol is undefined in this segment, or we need to keep a
11285 reloc so that weak symbols can be overridden. */
11286 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
11287 enum bfd_reloc_code_real reloc_type
;
11288 unsigned char *opcode
;
11291 if (fragP
->fr_var
!= NO_RELOC
)
11292 reloc_type
= (enum bfd_reloc_code_real
) fragP
->fr_var
;
11293 else if (size
== 2)
11294 reloc_type
= BFD_RELOC_16_PCREL
;
11295 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11296 else if (need_plt32_p (fragP
->fr_symbol
))
11297 reloc_type
= BFD_RELOC_X86_64_PLT32
;
11300 reloc_type
= BFD_RELOC_32_PCREL
;
11302 old_fr_fix
= fragP
->fr_fix
;
11303 opcode
= (unsigned char *) fragP
->fr_opcode
;
11305 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
11308 /* Make jmp (0xeb) a (d)word displacement jump. */
11310 fragP
->fr_fix
+= size
;
11311 fix_new (fragP
, old_fr_fix
, size
,
11313 fragP
->fr_offset
, 1,
11319 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
11321 /* Negate the condition, and branch past an
11322 unconditional jump. */
11325 /* Insert an unconditional jump. */
11327 /* We added two extra opcode bytes, and have a two byte
11329 fragP
->fr_fix
+= 2 + 2;
11330 fix_new (fragP
, old_fr_fix
+ 2, 2,
11332 fragP
->fr_offset
, 1,
11336 /* Fall through. */
11339 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
11343 fragP
->fr_fix
+= 1;
11344 fixP
= fix_new (fragP
, old_fr_fix
, 1,
11346 fragP
->fr_offset
, 1,
11347 BFD_RELOC_8_PCREL
);
11348 fixP
->fx_signed
= 1;
11352 /* This changes the byte-displacement jump 0x7N
11353 to the (d)word-displacement jump 0x0f,0x8N. */
11354 opcode
[1] = opcode
[0] + 0x10;
11355 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
11356 /* We've added an opcode byte. */
11357 fragP
->fr_fix
+= 1 + size
;
11358 fix_new (fragP
, old_fr_fix
+ 1, size
,
11360 fragP
->fr_offset
, 1,
11365 BAD_CASE (fragP
->fr_subtype
);
11369 return fragP
->fr_fix
- old_fr_fix
;
11372 /* Guess size depending on current relax state. Initially the relax
11373 state will correspond to a short jump and we return 1, because
11374 the variable part of the frag (the branch offset) is one byte
11375 long. However, we can relax a section more than once and in that
11376 case we must either set fr_subtype back to the unrelaxed state,
11377 or return the value for the appropriate branch. */
11378 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
11381 /* Called after relax() is finished.
11383 In: Address of frag.
11384 fr_type == rs_machine_dependent.
11385 fr_subtype is what the address relaxed to.
11387 Out: Any fixSs and constants are set up.
11388 Caller will turn frag into a ".space 0". */
11391 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec ATTRIBUTE_UNUSED
,
11394 unsigned char *opcode
;
11395 unsigned char *where_to_put_displacement
= NULL
;
11396 offsetT target_address
;
11397 offsetT opcode_address
;
11398 unsigned int extension
= 0;
11399 offsetT displacement_from_opcode_start
;
11401 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
11402 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
11403 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
)
11405 /* Generate nop padding. */
11406 unsigned int size
= fragP
->tc_frag_data
.length
;
11409 if (size
> fragP
->tc_frag_data
.max_bytes
)
11415 const char *branch
= "branch";
11416 const char *prefix
= "";
11417 fragS
*padding_fragP
;
11418 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
)
11421 padding_fragP
= fragP
->tc_frag_data
.u
.padding_fragP
;
11422 switch (fragP
->tc_frag_data
.default_prefix
)
11427 case CS_PREFIX_OPCODE
:
11430 case DS_PREFIX_OPCODE
:
11433 case ES_PREFIX_OPCODE
:
11436 case FS_PREFIX_OPCODE
:
11439 case GS_PREFIX_OPCODE
:
11442 case SS_PREFIX_OPCODE
:
11447 msg
= _("%s:%u: add %d%s at 0x%llx to align "
11448 "%s within %d-byte boundary\n");
11450 msg
= _("%s:%u: add additional %d%s at 0x%llx to "
11451 "align %s within %d-byte boundary\n");
11455 padding_fragP
= fragP
;
11456 msg
= _("%s:%u: add %d%s-byte nop at 0x%llx to align "
11457 "%s within %d-byte boundary\n");
11461 switch (padding_fragP
->tc_frag_data
.branch_type
)
11463 case align_branch_jcc
:
11466 case align_branch_fused
:
11467 branch
= "fused jcc";
11469 case align_branch_jmp
:
11472 case align_branch_call
:
11475 case align_branch_indirect
:
11476 branch
= "indiret branch";
11478 case align_branch_ret
:
11485 fprintf (stdout
, msg
,
11486 fragP
->fr_file
, fragP
->fr_line
, size
, prefix
,
11487 (long long) fragP
->fr_address
, branch
,
11488 1 << align_branch_power
);
11490 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
)
11491 memset (fragP
->fr_opcode
,
11492 fragP
->tc_frag_data
.default_prefix
, size
);
11494 i386_generate_nops (fragP
, (char *) fragP
->fr_opcode
,
11496 fragP
->fr_fix
+= size
;
11501 opcode
= (unsigned char *) fragP
->fr_opcode
;
11503 /* Address we want to reach in file space. */
11504 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
11506 /* Address opcode resides at in file space. */
11507 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
11509 /* Displacement from opcode start to fill into instruction. */
11510 displacement_from_opcode_start
= target_address
- opcode_address
;
11512 if ((fragP
->fr_subtype
& BIG
) == 0)
11514 /* Don't have to change opcode. */
11515 extension
= 1; /* 1 opcode + 1 displacement */
11516 where_to_put_displacement
= &opcode
[1];
11520 if (no_cond_jump_promotion
11521 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
11522 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
11523 _("long jump required"));
11525 switch (fragP
->fr_subtype
)
11527 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
11528 extension
= 4; /* 1 opcode + 4 displacement */
11530 where_to_put_displacement
= &opcode
[1];
11533 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
11534 extension
= 2; /* 1 opcode + 2 displacement */
11536 where_to_put_displacement
= &opcode
[1];
11539 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
11540 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
11541 extension
= 5; /* 2 opcode + 4 displacement */
11542 opcode
[1] = opcode
[0] + 0x10;
11543 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
11544 where_to_put_displacement
= &opcode
[2];
11547 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
11548 extension
= 3; /* 2 opcode + 2 displacement */
11549 opcode
[1] = opcode
[0] + 0x10;
11550 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
11551 where_to_put_displacement
= &opcode
[2];
11554 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
11559 where_to_put_displacement
= &opcode
[3];
11563 BAD_CASE (fragP
->fr_subtype
);
11568 /* If size if less then four we are sure that the operand fits,
11569 but if it's 4, then it could be that the displacement is larger
11571 if (DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
) == 4
11573 && ((addressT
) (displacement_from_opcode_start
- extension
11574 + ((addressT
) 1 << 31))
11575 > (((addressT
) 2 << 31) - 1)))
11577 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
11578 _("jump target out of range"));
11579 /* Make us emit 0. */
11580 displacement_from_opcode_start
= extension
;
11582 /* Now put displacement after opcode. */
11583 md_number_to_chars ((char *) where_to_put_displacement
,
11584 (valueT
) (displacement_from_opcode_start
- extension
),
11585 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
11586 fragP
->fr_fix
+= extension
;
11589 /* Apply a fixup (fixP) to segment data, once it has been determined
11590 by our caller that we have all the info we need to fix it up.
11592 Parameter valP is the pointer to the value of the bits.
11594 On the 386, immediates, displacements, and data pointers are all in
11595 the same (little-endian) format, so we don't need to care about which
11596 we are handling. */
11599 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
11601 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
11602 valueT value
= *valP
;
11604 #if !defined (TE_Mach)
11605 if (fixP
->fx_pcrel
)
11607 switch (fixP
->fx_r_type
)
11613 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
11616 case BFD_RELOC_X86_64_32S
:
11617 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
11620 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
11623 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
11628 if (fixP
->fx_addsy
!= NULL
11629 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
11630 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
11631 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
11632 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
11633 && !use_rela_relocations
)
11635 /* This is a hack. There should be a better way to handle this.
11636 This covers for the fact that bfd_install_relocation will
11637 subtract the current location (for partial_inplace, PC relative
11638 relocations); see more below. */
11642 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
11645 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
11647 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11650 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
11652 if ((sym_seg
== seg
11653 || (symbol_section_p (fixP
->fx_addsy
)
11654 && sym_seg
!= absolute_section
))
11655 && !generic_force_reloc (fixP
))
11657 /* Yes, we add the values in twice. This is because
11658 bfd_install_relocation subtracts them out again. I think
11659 bfd_install_relocation is broken, but I don't dare change
11661 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
11665 #if defined (OBJ_COFF) && defined (TE_PE)
11666 /* For some reason, the PE format does not store a
11667 section address offset for a PC relative symbol. */
11668 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
11669 || S_IS_WEAK (fixP
->fx_addsy
))
11670 value
+= md_pcrel_from (fixP
);
11673 #if defined (OBJ_COFF) && defined (TE_PE)
11674 if (fixP
->fx_addsy
!= NULL
11675 && S_IS_WEAK (fixP
->fx_addsy
)
11676 /* PR 16858: Do not modify weak function references. */
11677 && ! fixP
->fx_pcrel
)
11679 #if !defined (TE_PEP)
11680 /* For x86 PE weak function symbols are neither PC-relative
11681 nor do they set S_IS_FUNCTION. So the only reliable way
11682 to detect them is to check the flags of their containing
11684 if (S_GET_SEGMENT (fixP
->fx_addsy
) != NULL
11685 && S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_CODE
)
11689 value
-= S_GET_VALUE (fixP
->fx_addsy
);
11693 /* Fix a few things - the dynamic linker expects certain values here,
11694 and we must not disappoint it. */
11695 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11696 if (IS_ELF
&& fixP
->fx_addsy
)
11697 switch (fixP
->fx_r_type
)
11699 case BFD_RELOC_386_PLT32
:
11700 case BFD_RELOC_X86_64_PLT32
:
11701 /* Make the jump instruction point to the address of the operand.
11702 At runtime we merely add the offset to the actual PLT entry.
11703 NB: Subtract the offset size only for jump instructions. */
11704 if (fixP
->fx_pcrel
)
11708 case BFD_RELOC_386_TLS_GD
:
11709 case BFD_RELOC_386_TLS_LDM
:
11710 case BFD_RELOC_386_TLS_IE_32
:
11711 case BFD_RELOC_386_TLS_IE
:
11712 case BFD_RELOC_386_TLS_GOTIE
:
11713 case BFD_RELOC_386_TLS_GOTDESC
:
11714 case BFD_RELOC_X86_64_TLSGD
:
11715 case BFD_RELOC_X86_64_TLSLD
:
11716 case BFD_RELOC_X86_64_GOTTPOFF
:
11717 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
11718 value
= 0; /* Fully resolved at runtime. No addend. */
11720 case BFD_RELOC_386_TLS_LE
:
11721 case BFD_RELOC_386_TLS_LDO_32
:
11722 case BFD_RELOC_386_TLS_LE_32
:
11723 case BFD_RELOC_X86_64_DTPOFF32
:
11724 case BFD_RELOC_X86_64_DTPOFF64
:
11725 case BFD_RELOC_X86_64_TPOFF32
:
11726 case BFD_RELOC_X86_64_TPOFF64
:
11727 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
11730 case BFD_RELOC_386_TLS_DESC_CALL
:
11731 case BFD_RELOC_X86_64_TLSDESC_CALL
:
11732 value
= 0; /* Fully resolved at runtime. No addend. */
11733 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
11737 case BFD_RELOC_VTABLE_INHERIT
:
11738 case BFD_RELOC_VTABLE_ENTRY
:
11745 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
11747 #endif /* !defined (TE_Mach) */
11749 /* Are we finished with this relocation now? */
11750 if (fixP
->fx_addsy
== NULL
)
11752 #if defined (OBJ_COFF) && defined (TE_PE)
11753 else if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
11756 /* Remember value for tc_gen_reloc. */
11757 fixP
->fx_addnumber
= value
;
11758 /* Clear out the frag for now. */
11762 else if (use_rela_relocations
)
11764 fixP
->fx_no_overflow
= 1;
11765 /* Remember value for tc_gen_reloc. */
11766 fixP
->fx_addnumber
= value
;
11770 md_number_to_chars (p
, value
, fixP
->fx_size
);
11774 md_atof (int type
, char *litP
, int *sizeP
)
11776 /* This outputs the LITTLENUMs in REVERSE order;
11777 in accord with the bigendian 386. */
11778 return ieee_md_atof (type
, litP
, sizeP
, FALSE
);
11781 static char output_invalid_buf
[sizeof (unsigned char) * 2 + 6];
11784 output_invalid (int c
)
11787 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
11790 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
11791 "(0x%x)", (unsigned char) c
);
11792 return output_invalid_buf
;
11795 /* REG_STRING starts *before* REGISTER_PREFIX. */
11797 static const reg_entry
*
11798 parse_real_register (char *reg_string
, char **end_op
)
11800 char *s
= reg_string
;
11802 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
11803 const reg_entry
*r
;
11805 /* Skip possible REGISTER_PREFIX and possible whitespace. */
11806 if (*s
== REGISTER_PREFIX
)
11809 if (is_space_char (*s
))
11812 p
= reg_name_given
;
11813 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
11815 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
11816 return (const reg_entry
*) NULL
;
11820 /* For naked regs, make sure that we are not dealing with an identifier.
11821 This prevents confusing an identifier like `eax_var' with register
11823 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
11824 return (const reg_entry
*) NULL
;
11828 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
11830 /* Handle floating point regs, allowing spaces in the (i) part. */
11831 if (r
== i386_regtab
/* %st is first entry of table */)
11833 if (!cpu_arch_flags
.bitfield
.cpu8087
11834 && !cpu_arch_flags
.bitfield
.cpu287
11835 && !cpu_arch_flags
.bitfield
.cpu387
)
11836 return (const reg_entry
*) NULL
;
11838 if (is_space_char (*s
))
11843 if (is_space_char (*s
))
11845 if (*s
>= '0' && *s
<= '7')
11847 int fpr
= *s
- '0';
11849 if (is_space_char (*s
))
11854 r
= (const reg_entry
*) hash_find (reg_hash
, "st(0)");
11859 /* We have "%st(" then garbage. */
11860 return (const reg_entry
*) NULL
;
11864 if (r
== NULL
|| allow_pseudo_reg
)
11867 if (operand_type_all_zero (&r
->reg_type
))
11868 return (const reg_entry
*) NULL
;
11870 if ((r
->reg_type
.bitfield
.dword
11871 || (r
->reg_type
.bitfield
.class == SReg
&& r
->reg_num
> 3)
11872 || r
->reg_type
.bitfield
.class == RegCR
11873 || r
->reg_type
.bitfield
.class == RegDR
11874 || r
->reg_type
.bitfield
.class == RegTR
)
11875 && !cpu_arch_flags
.bitfield
.cpui386
)
11876 return (const reg_entry
*) NULL
;
11878 if (r
->reg_type
.bitfield
.class == RegMMX
&& !cpu_arch_flags
.bitfield
.cpummx
)
11879 return (const reg_entry
*) NULL
;
11881 if (!cpu_arch_flags
.bitfield
.cpuavx512f
)
11883 if (r
->reg_type
.bitfield
.zmmword
11884 || r
->reg_type
.bitfield
.class == RegMask
)
11885 return (const reg_entry
*) NULL
;
11887 if (!cpu_arch_flags
.bitfield
.cpuavx
)
11889 if (r
->reg_type
.bitfield
.ymmword
)
11890 return (const reg_entry
*) NULL
;
11892 if (!cpu_arch_flags
.bitfield
.cpusse
&& r
->reg_type
.bitfield
.xmmword
)
11893 return (const reg_entry
*) NULL
;
11897 if (r
->reg_type
.bitfield
.class == RegBND
&& !cpu_arch_flags
.bitfield
.cpumpx
)
11898 return (const reg_entry
*) NULL
;
11900 /* Don't allow fake index register unless allow_index_reg isn't 0. */
11901 if (!allow_index_reg
&& r
->reg_num
== RegIZ
)
11902 return (const reg_entry
*) NULL
;
11904 /* Upper 16 vector registers are only available with VREX in 64bit
11905 mode, and require EVEX encoding. */
11906 if (r
->reg_flags
& RegVRex
)
11908 if (!cpu_arch_flags
.bitfield
.cpuavx512f
11909 || flag_code
!= CODE_64BIT
)
11910 return (const reg_entry
*) NULL
;
11912 i
.vec_encoding
= vex_encoding_evex
;
11915 if (((r
->reg_flags
& (RegRex64
| RegRex
)) || r
->reg_type
.bitfield
.qword
)
11916 && (!cpu_arch_flags
.bitfield
.cpulm
|| r
->reg_type
.bitfield
.class != RegCR
)
11917 && flag_code
!= CODE_64BIT
)
11918 return (const reg_entry
*) NULL
;
11920 if (r
->reg_type
.bitfield
.class == SReg
&& r
->reg_num
== RegFlat
11922 return (const reg_entry
*) NULL
;
11927 /* REG_STRING starts *before* REGISTER_PREFIX. */
11929 static const reg_entry
*
11930 parse_register (char *reg_string
, char **end_op
)
11932 const reg_entry
*r
;
11934 if (*reg_string
== REGISTER_PREFIX
|| allow_naked_reg
)
11935 r
= parse_real_register (reg_string
, end_op
);
11940 char *save
= input_line_pointer
;
11944 input_line_pointer
= reg_string
;
11945 c
= get_symbol_name (®_string
);
11946 symbolP
= symbol_find (reg_string
);
11947 if (symbolP
&& S_GET_SEGMENT (symbolP
) == reg_section
)
11949 const expressionS
*e
= symbol_get_value_expression (symbolP
);
11951 know (e
->X_op
== O_register
);
11952 know (e
->X_add_number
>= 0
11953 && (valueT
) e
->X_add_number
< i386_regtab_size
);
11954 r
= i386_regtab
+ e
->X_add_number
;
11955 if ((r
->reg_flags
& RegVRex
))
11956 i
.vec_encoding
= vex_encoding_evex
;
11957 *end_op
= input_line_pointer
;
11959 *input_line_pointer
= c
;
11960 input_line_pointer
= save
;
11966 i386_parse_name (char *name
, expressionS
*e
, char *nextcharP
)
11968 const reg_entry
*r
;
11969 char *end
= input_line_pointer
;
11972 r
= parse_register (name
, &input_line_pointer
);
11973 if (r
&& end
<= input_line_pointer
)
11975 *nextcharP
= *input_line_pointer
;
11976 *input_line_pointer
= 0;
11977 e
->X_op
= O_register
;
11978 e
->X_add_number
= r
- i386_regtab
;
11981 input_line_pointer
= end
;
11983 return intel_syntax
? i386_intel_parse_name (name
, e
) : 0;
11987 md_operand (expressionS
*e
)
11990 const reg_entry
*r
;
11992 switch (*input_line_pointer
)
11994 case REGISTER_PREFIX
:
11995 r
= parse_real_register (input_line_pointer
, &end
);
11998 e
->X_op
= O_register
;
11999 e
->X_add_number
= r
- i386_regtab
;
12000 input_line_pointer
= end
;
12005 gas_assert (intel_syntax
);
12006 end
= input_line_pointer
++;
12008 if (*input_line_pointer
== ']')
12010 ++input_line_pointer
;
12011 e
->X_op_symbol
= make_expr_symbol (e
);
12012 e
->X_add_symbol
= NULL
;
12013 e
->X_add_number
= 0;
12018 e
->X_op
= O_absent
;
12019 input_line_pointer
= end
;
12026 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12027 const char *md_shortopts
= "kVQ:sqnO::";
12029 const char *md_shortopts
= "qnO::";
12032 #define OPTION_32 (OPTION_MD_BASE + 0)
12033 #define OPTION_64 (OPTION_MD_BASE + 1)
12034 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
12035 #define OPTION_MARCH (OPTION_MD_BASE + 3)
12036 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
12037 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
12038 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
12039 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
12040 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
12041 #define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 9)
12042 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
12043 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
12044 #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
12045 #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
12046 #define OPTION_X32 (OPTION_MD_BASE + 14)
12047 #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
12048 #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
12049 #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
12050 #define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
12051 #define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
12052 #define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
12053 #define OPTION_MSHARED (OPTION_MD_BASE + 21)
12054 #define OPTION_MAMD64 (OPTION_MD_BASE + 22)
12055 #define OPTION_MINTEL64 (OPTION_MD_BASE + 23)
12056 #define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24)
12057 #define OPTION_X86_USED_NOTE (OPTION_MD_BASE + 25)
12058 #define OPTION_MVEXWIG (OPTION_MD_BASE + 26)
12059 #define OPTION_MALIGN_BRANCH_BOUNDARY (OPTION_MD_BASE + 27)
12060 #define OPTION_MALIGN_BRANCH_PREFIX_SIZE (OPTION_MD_BASE + 28)
12061 #define OPTION_MALIGN_BRANCH (OPTION_MD_BASE + 29)
12062 #define OPTION_MBRANCHES_WITH_32B_BOUNDARIES (OPTION_MD_BASE + 30)
12064 struct option md_longopts
[] =
12066 {"32", no_argument
, NULL
, OPTION_32
},
12067 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
12068 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
12069 {"64", no_argument
, NULL
, OPTION_64
},
12071 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12072 {"x32", no_argument
, NULL
, OPTION_X32
},
12073 {"mshared", no_argument
, NULL
, OPTION_MSHARED
},
12074 {"mx86-used-note", required_argument
, NULL
, OPTION_X86_USED_NOTE
},
12076 {"divide", no_argument
, NULL
, OPTION_DIVIDE
},
12077 {"march", required_argument
, NULL
, OPTION_MARCH
},
12078 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
12079 {"mmnemonic", required_argument
, NULL
, OPTION_MMNEMONIC
},
12080 {"msyntax", required_argument
, NULL
, OPTION_MSYNTAX
},
12081 {"mindex-reg", no_argument
, NULL
, OPTION_MINDEX_REG
},
12082 {"mnaked-reg", no_argument
, NULL
, OPTION_MNAKED_REG
},
12083 {"msse2avx", no_argument
, NULL
, OPTION_MSSE2AVX
},
12084 {"msse-check", required_argument
, NULL
, OPTION_MSSE_CHECK
},
12085 {"moperand-check", required_argument
, NULL
, OPTION_MOPERAND_CHECK
},
12086 {"mavxscalar", required_argument
, NULL
, OPTION_MAVXSCALAR
},
12087 {"mvexwig", required_argument
, NULL
, OPTION_MVEXWIG
},
12088 {"madd-bnd-prefix", no_argument
, NULL
, OPTION_MADD_BND_PREFIX
},
12089 {"mevexlig", required_argument
, NULL
, OPTION_MEVEXLIG
},
12090 {"mevexwig", required_argument
, NULL
, OPTION_MEVEXWIG
},
12091 # if defined (TE_PE) || defined (TE_PEP)
12092 {"mbig-obj", no_argument
, NULL
, OPTION_MBIG_OBJ
},
12094 {"momit-lock-prefix", required_argument
, NULL
, OPTION_MOMIT_LOCK_PREFIX
},
12095 {"mfence-as-lock-add", required_argument
, NULL
, OPTION_MFENCE_AS_LOCK_ADD
},
12096 {"mrelax-relocations", required_argument
, NULL
, OPTION_MRELAX_RELOCATIONS
},
12097 {"mevexrcig", required_argument
, NULL
, OPTION_MEVEXRCIG
},
12098 {"malign-branch-boundary", required_argument
, NULL
, OPTION_MALIGN_BRANCH_BOUNDARY
},
12099 {"malign-branch-prefix-size", required_argument
, NULL
, OPTION_MALIGN_BRANCH_PREFIX_SIZE
},
12100 {"malign-branch", required_argument
, NULL
, OPTION_MALIGN_BRANCH
},
12101 {"mbranches-within-32B-boundaries", no_argument
, NULL
, OPTION_MBRANCHES_WITH_32B_BOUNDARIES
},
12102 {"mamd64", no_argument
, NULL
, OPTION_MAMD64
},
12103 {"mintel64", no_argument
, NULL
, OPTION_MINTEL64
},
12104 {NULL
, no_argument
, NULL
, 0}
12106 size_t md_longopts_size
= sizeof (md_longopts
);
12109 md_parse_option (int c
, const char *arg
)
12112 char *arch
, *next
, *saved
, *type
;
12117 optimize_align_code
= 0;
12121 quiet_warnings
= 1;
12124 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12125 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
12126 should be emitted or not. FIXME: Not implemented. */
12128 if ((arg
[0] != 'y' && arg
[0] != 'n') || arg
[1])
12132 /* -V: SVR4 argument to print version ID. */
12134 print_version_id ();
12137 /* -k: Ignore for FreeBSD compatibility. */
12142 /* -s: On i386 Solaris, this tells the native assembler to use
12143 .stab instead of .stab.excl. We always use .stab anyhow. */
12146 case OPTION_MSHARED
:
12150 case OPTION_X86_USED_NOTE
:
12151 if (strcasecmp (arg
, "yes") == 0)
12153 else if (strcasecmp (arg
, "no") == 0)
12156 as_fatal (_("invalid -mx86-used-note= option: `%s'"), arg
);
12161 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
12162 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
12165 const char **list
, **l
;
12167 list
= bfd_target_list ();
12168 for (l
= list
; *l
!= NULL
; l
++)
12169 if (CONST_STRNEQ (*l
, "elf64-x86-64")
12170 || strcmp (*l
, "coff-x86-64") == 0
12171 || strcmp (*l
, "pe-x86-64") == 0
12172 || strcmp (*l
, "pei-x86-64") == 0
12173 || strcmp (*l
, "mach-o-x86-64") == 0)
12175 default_arch
= "x86_64";
12179 as_fatal (_("no compiled in support for x86_64"));
12185 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12189 const char **list
, **l
;
12191 list
= bfd_target_list ();
12192 for (l
= list
; *l
!= NULL
; l
++)
12193 if (CONST_STRNEQ (*l
, "elf32-x86-64"))
12195 default_arch
= "x86_64:32";
12199 as_fatal (_("no compiled in support for 32bit x86_64"));
12203 as_fatal (_("32bit x86_64 is only supported for ELF"));
12208 default_arch
= "i386";
12211 case OPTION_DIVIDE
:
12212 #ifdef SVR4_COMMENT_CHARS
12217 n
= XNEWVEC (char, strlen (i386_comment_chars
) + 1);
12219 for (s
= i386_comment_chars
; *s
!= '\0'; s
++)
12223 i386_comment_chars
= n
;
12229 saved
= xstrdup (arg
);
12231 /* Allow -march=+nosse. */
12237 as_fatal (_("invalid -march= option: `%s'"), arg
);
12238 next
= strchr (arch
, '+');
12241 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
12243 if (strcmp (arch
, cpu_arch
[j
].name
) == 0)
12246 if (! cpu_arch
[j
].flags
.bitfield
.cpui386
)
12249 cpu_arch_name
= cpu_arch
[j
].name
;
12250 cpu_sub_arch_name
= NULL
;
12251 cpu_arch_flags
= cpu_arch
[j
].flags
;
12252 cpu_arch_isa
= cpu_arch
[j
].type
;
12253 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
12254 if (!cpu_arch_tune_set
)
12256 cpu_arch_tune
= cpu_arch_isa
;
12257 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
12261 else if (*cpu_arch
[j
].name
== '.'
12262 && strcmp (arch
, cpu_arch
[j
].name
+ 1) == 0)
12264 /* ISA extension. */
12265 i386_cpu_flags flags
;
12267 flags
= cpu_flags_or (cpu_arch_flags
,
12268 cpu_arch
[j
].flags
);
12270 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
12272 if (cpu_sub_arch_name
)
12274 char *name
= cpu_sub_arch_name
;
12275 cpu_sub_arch_name
= concat (name
,
12277 (const char *) NULL
);
12281 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
12282 cpu_arch_flags
= flags
;
12283 cpu_arch_isa_flags
= flags
;
12287 = cpu_flags_or (cpu_arch_isa_flags
,
12288 cpu_arch
[j
].flags
);
12293 if (j
>= ARRAY_SIZE (cpu_arch
))
12295 /* Disable an ISA extension. */
12296 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
12297 if (strcmp (arch
, cpu_noarch
[j
].name
) == 0)
12299 i386_cpu_flags flags
;
12301 flags
= cpu_flags_and_not (cpu_arch_flags
,
12302 cpu_noarch
[j
].flags
);
12303 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
12305 if (cpu_sub_arch_name
)
12307 char *name
= cpu_sub_arch_name
;
12308 cpu_sub_arch_name
= concat (arch
,
12309 (const char *) NULL
);
12313 cpu_sub_arch_name
= xstrdup (arch
);
12314 cpu_arch_flags
= flags
;
12315 cpu_arch_isa_flags
= flags
;
12320 if (j
>= ARRAY_SIZE (cpu_noarch
))
12321 j
= ARRAY_SIZE (cpu_arch
);
12324 if (j
>= ARRAY_SIZE (cpu_arch
))
12325 as_fatal (_("invalid -march= option: `%s'"), arg
);
12329 while (next
!= NULL
);
12335 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
12336 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
12338 if (strcmp (arg
, cpu_arch
[j
].name
) == 0)
12340 cpu_arch_tune_set
= 1;
12341 cpu_arch_tune
= cpu_arch
[j
].type
;
12342 cpu_arch_tune_flags
= cpu_arch
[j
].flags
;
12346 if (j
>= ARRAY_SIZE (cpu_arch
))
12347 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
12350 case OPTION_MMNEMONIC
:
12351 if (strcasecmp (arg
, "att") == 0)
12352 intel_mnemonic
= 0;
12353 else if (strcasecmp (arg
, "intel") == 0)
12354 intel_mnemonic
= 1;
12356 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg
);
12359 case OPTION_MSYNTAX
:
12360 if (strcasecmp (arg
, "att") == 0)
12362 else if (strcasecmp (arg
, "intel") == 0)
12365 as_fatal (_("invalid -msyntax= option: `%s'"), arg
);
12368 case OPTION_MINDEX_REG
:
12369 allow_index_reg
= 1;
12372 case OPTION_MNAKED_REG
:
12373 allow_naked_reg
= 1;
12376 case OPTION_MSSE2AVX
:
12380 case OPTION_MSSE_CHECK
:
12381 if (strcasecmp (arg
, "error") == 0)
12382 sse_check
= check_error
;
12383 else if (strcasecmp (arg
, "warning") == 0)
12384 sse_check
= check_warning
;
12385 else if (strcasecmp (arg
, "none") == 0)
12386 sse_check
= check_none
;
12388 as_fatal (_("invalid -msse-check= option: `%s'"), arg
);
12391 case OPTION_MOPERAND_CHECK
:
12392 if (strcasecmp (arg
, "error") == 0)
12393 operand_check
= check_error
;
12394 else if (strcasecmp (arg
, "warning") == 0)
12395 operand_check
= check_warning
;
12396 else if (strcasecmp (arg
, "none") == 0)
12397 operand_check
= check_none
;
12399 as_fatal (_("invalid -moperand-check= option: `%s'"), arg
);
12402 case OPTION_MAVXSCALAR
:
12403 if (strcasecmp (arg
, "128") == 0)
12404 avxscalar
= vex128
;
12405 else if (strcasecmp (arg
, "256") == 0)
12406 avxscalar
= vex256
;
12408 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg
);
12411 case OPTION_MVEXWIG
:
12412 if (strcmp (arg
, "0") == 0)
12414 else if (strcmp (arg
, "1") == 0)
12417 as_fatal (_("invalid -mvexwig= option: `%s'"), arg
);
12420 case OPTION_MADD_BND_PREFIX
:
12421 add_bnd_prefix
= 1;
12424 case OPTION_MEVEXLIG
:
12425 if (strcmp (arg
, "128") == 0)
12426 evexlig
= evexl128
;
12427 else if (strcmp (arg
, "256") == 0)
12428 evexlig
= evexl256
;
12429 else if (strcmp (arg
, "512") == 0)
12430 evexlig
= evexl512
;
12432 as_fatal (_("invalid -mevexlig= option: `%s'"), arg
);
12435 case OPTION_MEVEXRCIG
:
12436 if (strcmp (arg
, "rne") == 0)
12438 else if (strcmp (arg
, "rd") == 0)
12440 else if (strcmp (arg
, "ru") == 0)
12442 else if (strcmp (arg
, "rz") == 0)
12445 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg
);
12448 case OPTION_MEVEXWIG
:
12449 if (strcmp (arg
, "0") == 0)
12451 else if (strcmp (arg
, "1") == 0)
12454 as_fatal (_("invalid -mevexwig= option: `%s'"), arg
);
12457 # if defined (TE_PE) || defined (TE_PEP)
12458 case OPTION_MBIG_OBJ
:
12463 case OPTION_MOMIT_LOCK_PREFIX
:
12464 if (strcasecmp (arg
, "yes") == 0)
12465 omit_lock_prefix
= 1;
12466 else if (strcasecmp (arg
, "no") == 0)
12467 omit_lock_prefix
= 0;
12469 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg
);
12472 case OPTION_MFENCE_AS_LOCK_ADD
:
12473 if (strcasecmp (arg
, "yes") == 0)
12475 else if (strcasecmp (arg
, "no") == 0)
12478 as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg
);
12481 case OPTION_MRELAX_RELOCATIONS
:
12482 if (strcasecmp (arg
, "yes") == 0)
12483 generate_relax_relocations
= 1;
12484 else if (strcasecmp (arg
, "no") == 0)
12485 generate_relax_relocations
= 0;
12487 as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg
);
12490 case OPTION_MALIGN_BRANCH_BOUNDARY
:
12493 long int align
= strtoul (arg
, &end
, 0);
12498 align_branch_power
= 0;
12501 else if (align
>= 16)
12504 for (align_power
= 0;
12506 align
>>= 1, align_power
++)
12508 /* Limit alignment power to 31. */
12509 if (align
== 1 && align_power
< 32)
12511 align_branch_power
= align_power
;
12516 as_fatal (_("invalid -malign-branch-boundary= value: %s"), arg
);
12520 case OPTION_MALIGN_BRANCH_PREFIX_SIZE
:
12523 int align
= strtoul (arg
, &end
, 0);
12524 /* Some processors only support 5 prefixes. */
12525 if (*end
== '\0' && align
>= 0 && align
< 6)
12527 align_branch_prefix_size
= align
;
12530 as_fatal (_("invalid -malign-branch-prefix-size= value: %s"),
12535 case OPTION_MALIGN_BRANCH
:
12537 saved
= xstrdup (arg
);
12541 next
= strchr (type
, '+');
12544 if (strcasecmp (type
, "jcc") == 0)
12545 align_branch
|= align_branch_jcc_bit
;
12546 else if (strcasecmp (type
, "fused") == 0)
12547 align_branch
|= align_branch_fused_bit
;
12548 else if (strcasecmp (type
, "jmp") == 0)
12549 align_branch
|= align_branch_jmp_bit
;
12550 else if (strcasecmp (type
, "call") == 0)
12551 align_branch
|= align_branch_call_bit
;
12552 else if (strcasecmp (type
, "ret") == 0)
12553 align_branch
|= align_branch_ret_bit
;
12554 else if (strcasecmp (type
, "indirect") == 0)
12555 align_branch
|= align_branch_indirect_bit
;
12557 as_fatal (_("invalid -malign-branch= option: `%s'"), arg
);
12560 while (next
!= NULL
);
12564 case OPTION_MBRANCHES_WITH_32B_BOUNDARIES
:
12565 align_branch_power
= 5;
12566 align_branch_prefix_size
= 5;
12567 align_branch
= (align_branch_jcc_bit
12568 | align_branch_fused_bit
12569 | align_branch_jmp_bit
);
12572 case OPTION_MAMD64
:
12576 case OPTION_MINTEL64
:
12584 /* Turn off -Os. */
12585 optimize_for_space
= 0;
12587 else if (*arg
== 's')
12589 optimize_for_space
= 1;
12590 /* Turn on all encoding optimizations. */
12591 optimize
= INT_MAX
;
12595 optimize
= atoi (arg
);
12596 /* Turn off -Os. */
12597 optimize_for_space
= 0;
12607 #define MESSAGE_TEMPLATE \
12611 output_message (FILE *stream
, char *p
, char *message
, char *start
,
12612 int *left_p
, const char *name
, int len
)
12614 int size
= sizeof (MESSAGE_TEMPLATE
);
12615 int left
= *left_p
;
12617 /* Reserve 2 spaces for ", " or ",\0" */
12620 /* Check if there is any room. */
12628 p
= mempcpy (p
, name
, len
);
12632 /* Output the current message now and start a new one. */
12635 fprintf (stream
, "%s\n", message
);
12637 left
= size
- (start
- message
) - len
- 2;
12639 gas_assert (left
>= 0);
12641 p
= mempcpy (p
, name
, len
);
12649 show_arch (FILE *stream
, int ext
, int check
)
12651 static char message
[] = MESSAGE_TEMPLATE
;
12652 char *start
= message
+ 27;
12654 int size
= sizeof (MESSAGE_TEMPLATE
);
12661 left
= size
- (start
- message
);
12662 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
12664 /* Should it be skipped? */
12665 if (cpu_arch
[j
].skip
)
12668 name
= cpu_arch
[j
].name
;
12669 len
= cpu_arch
[j
].len
;
12672 /* It is an extension. Skip if we aren't asked to show it. */
12683 /* It is an processor. Skip if we show only extension. */
12686 else if (check
&& ! cpu_arch
[j
].flags
.bitfield
.cpui386
)
12688 /* It is an impossible processor - skip. */
12692 p
= output_message (stream
, p
, message
, start
, &left
, name
, len
);
12695 /* Display disabled extensions. */
12697 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
12699 name
= cpu_noarch
[j
].name
;
12700 len
= cpu_noarch
[j
].len
;
12701 p
= output_message (stream
, p
, message
, start
, &left
, name
,
12706 fprintf (stream
, "%s\n", message
);
12710 md_show_usage (FILE *stream
)
12712 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12713 fprintf (stream
, _("\
12714 -Qy, -Qn ignored\n\
12715 -V print assembler version number\n\
12718 fprintf (stream
, _("\
12719 -n Do not optimize code alignment\n\
12720 -q quieten some warnings\n"));
12721 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12722 fprintf (stream
, _("\
12725 #if defined BFD64 && (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
12726 || defined (TE_PE) || defined (TE_PEP))
12727 fprintf (stream
, _("\
12728 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
12730 #ifdef SVR4_COMMENT_CHARS
12731 fprintf (stream
, _("\
12732 --divide do not treat `/' as a comment character\n"));
12734 fprintf (stream
, _("\
12735 --divide ignored\n"));
12737 fprintf (stream
, _("\
12738 -march=CPU[,+EXTENSION...]\n\
12739 generate code for CPU and EXTENSION, CPU is one of:\n"));
12740 show_arch (stream
, 0, 1);
12741 fprintf (stream
, _("\
12742 EXTENSION is combination of:\n"));
12743 show_arch (stream
, 1, 0);
12744 fprintf (stream
, _("\
12745 -mtune=CPU optimize for CPU, CPU is one of:\n"));
12746 show_arch (stream
, 0, 0);
12747 fprintf (stream
, _("\
12748 -msse2avx encode SSE instructions with VEX prefix\n"));
12749 fprintf (stream
, _("\
12750 -msse-check=[none|error|warning] (default: warning)\n\
12751 check SSE instructions\n"));
12752 fprintf (stream
, _("\
12753 -moperand-check=[none|error|warning] (default: warning)\n\
12754 check operand combinations for validity\n"));
12755 fprintf (stream
, _("\
12756 -mavxscalar=[128|256] (default: 128)\n\
12757 encode scalar AVX instructions with specific vector\n\
12759 fprintf (stream
, _("\
12760 -mvexwig=[0|1] (default: 0)\n\
12761 encode VEX instructions with specific VEX.W value\n\
12762 for VEX.W bit ignored instructions\n"));
12763 fprintf (stream
, _("\
12764 -mevexlig=[128|256|512] (default: 128)\n\
12765 encode scalar EVEX instructions with specific vector\n\
12767 fprintf (stream
, _("\
12768 -mevexwig=[0|1] (default: 0)\n\
12769 encode EVEX instructions with specific EVEX.W value\n\
12770 for EVEX.W bit ignored instructions\n"));
12771 fprintf (stream
, _("\
12772 -mevexrcig=[rne|rd|ru|rz] (default: rne)\n\
12773 encode EVEX instructions with specific EVEX.RC value\n\
12774 for SAE-only ignored instructions\n"));
12775 fprintf (stream
, _("\
12776 -mmnemonic=[att|intel] "));
12777 if (SYSV386_COMPAT
)
12778 fprintf (stream
, _("(default: att)\n"));
12780 fprintf (stream
, _("(default: intel)\n"));
12781 fprintf (stream
, _("\
12782 use AT&T/Intel mnemonic\n"));
12783 fprintf (stream
, _("\
12784 -msyntax=[att|intel] (default: att)\n\
12785 use AT&T/Intel syntax\n"));
12786 fprintf (stream
, _("\
12787 -mindex-reg support pseudo index registers\n"));
12788 fprintf (stream
, _("\
12789 -mnaked-reg don't require `%%' prefix for registers\n"));
12790 fprintf (stream
, _("\
12791 -madd-bnd-prefix add BND prefix for all valid branches\n"));
12792 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12793 fprintf (stream
, _("\
12794 -mshared disable branch optimization for shared code\n"));
12795 fprintf (stream
, _("\
12796 -mx86-used-note=[no|yes] "));
12797 if (DEFAULT_X86_USED_NOTE
)
12798 fprintf (stream
, _("(default: yes)\n"));
12800 fprintf (stream
, _("(default: no)\n"));
12801 fprintf (stream
, _("\
12802 generate x86 used ISA and feature properties\n"));
12804 #if defined (TE_PE) || defined (TE_PEP)
12805 fprintf (stream
, _("\
12806 -mbig-obj generate big object files\n"));
12808 fprintf (stream
, _("\
12809 -momit-lock-prefix=[no|yes] (default: no)\n\
12810 strip all lock prefixes\n"));
12811 fprintf (stream
, _("\
12812 -mfence-as-lock-add=[no|yes] (default: no)\n\
12813 encode lfence, mfence and sfence as\n\
12814 lock addl $0x0, (%%{re}sp)\n"));
12815 fprintf (stream
, _("\
12816 -mrelax-relocations=[no|yes] "));
12817 if (DEFAULT_GENERATE_X86_RELAX_RELOCATIONS
)
12818 fprintf (stream
, _("(default: yes)\n"));
12820 fprintf (stream
, _("(default: no)\n"));
12821 fprintf (stream
, _("\
12822 generate relax relocations\n"));
12823 fprintf (stream
, _("\
12824 -malign-branch-boundary=NUM (default: 0)\n\
12825 align branches within NUM byte boundary\n"));
12826 fprintf (stream
, _("\
12827 -malign-branch=TYPE[+TYPE...] (default: jcc+fused+jmp)\n\
12828 TYPE is combination of jcc, fused, jmp, call, ret,\n\
12830 specify types of branches to align\n"));
12831 fprintf (stream
, _("\
12832 -malign-branch-prefix-size=NUM (default: 5)\n\
12833 align branches with NUM prefixes per instruction\n"));
12834 fprintf (stream
, _("\
12835 -mbranches-within-32B-boundaries\n\
12836 align branches within 32 byte boundary\n"));
12837 fprintf (stream
, _("\
12838 -mamd64 accept only AMD64 ISA [default]\n"));
12839 fprintf (stream
, _("\
12840 -mintel64 accept only Intel64 ISA\n"));
12843 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
12844 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
12845 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
12847 /* Pick the target format to use. */
12850 i386_target_format (void)
12852 if (!strncmp (default_arch
, "x86_64", 6))
12854 update_code_flag (CODE_64BIT
, 1);
12855 if (default_arch
[6] == '\0')
12856 x86_elf_abi
= X86_64_ABI
;
12858 x86_elf_abi
= X86_64_X32_ABI
;
12860 else if (!strcmp (default_arch
, "i386"))
12861 update_code_flag (CODE_32BIT
, 1);
12862 else if (!strcmp (default_arch
, "iamcu"))
12864 update_code_flag (CODE_32BIT
, 1);
12865 if (cpu_arch_isa
== PROCESSOR_UNKNOWN
)
12867 static const i386_cpu_flags iamcu_flags
= CPU_IAMCU_FLAGS
;
12868 cpu_arch_name
= "iamcu";
12869 cpu_sub_arch_name
= NULL
;
12870 cpu_arch_flags
= iamcu_flags
;
12871 cpu_arch_isa
= PROCESSOR_IAMCU
;
12872 cpu_arch_isa_flags
= iamcu_flags
;
12873 if (!cpu_arch_tune_set
)
12875 cpu_arch_tune
= cpu_arch_isa
;
12876 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
12879 else if (cpu_arch_isa
!= PROCESSOR_IAMCU
)
12880 as_fatal (_("Intel MCU doesn't support `%s' architecture"),
12884 as_fatal (_("unknown architecture"));
12886 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
12887 cpu_arch_isa_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
12888 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
12889 cpu_arch_tune_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
12891 switch (OUTPUT_FLAVOR
)
12893 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
12894 case bfd_target_aout_flavour
:
12895 return AOUT_TARGET_FORMAT
;
12897 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
12898 # if defined (TE_PE) || defined (TE_PEP)
12899 case bfd_target_coff_flavour
:
12900 if (flag_code
== CODE_64BIT
)
12901 return use_big_obj
? "pe-bigobj-x86-64" : "pe-x86-64";
12904 # elif defined (TE_GO32)
12905 case bfd_target_coff_flavour
:
12906 return "coff-go32";
12908 case bfd_target_coff_flavour
:
12909 return "coff-i386";
12912 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
12913 case bfd_target_elf_flavour
:
12915 const char *format
;
12917 switch (x86_elf_abi
)
12920 format
= ELF_TARGET_FORMAT
;
12922 tls_get_addr
= "___tls_get_addr";
12926 use_rela_relocations
= 1;
12929 tls_get_addr
= "__tls_get_addr";
12931 format
= ELF_TARGET_FORMAT64
;
12933 case X86_64_X32_ABI
:
12934 use_rela_relocations
= 1;
12937 tls_get_addr
= "__tls_get_addr";
12939 disallow_64bit_reloc
= 1;
12940 format
= ELF_TARGET_FORMAT32
;
12943 if (cpu_arch_isa
== PROCESSOR_L1OM
)
12945 if (x86_elf_abi
!= X86_64_ABI
)
12946 as_fatal (_("Intel L1OM is 64bit only"));
12947 return ELF_TARGET_L1OM_FORMAT
;
12949 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
12951 if (x86_elf_abi
!= X86_64_ABI
)
12952 as_fatal (_("Intel K1OM is 64bit only"));
12953 return ELF_TARGET_K1OM_FORMAT
;
12955 else if (cpu_arch_isa
== PROCESSOR_IAMCU
)
12957 if (x86_elf_abi
!= I386_ABI
)
12958 as_fatal (_("Intel MCU is 32bit only"));
12959 return ELF_TARGET_IAMCU_FORMAT
;
12965 #if defined (OBJ_MACH_O)
12966 case bfd_target_mach_o_flavour
:
12967 if (flag_code
== CODE_64BIT
)
12969 use_rela_relocations
= 1;
12971 return "mach-o-x86-64";
12974 return "mach-o-i386";
12982 #endif /* OBJ_MAYBE_ more than one */
12985 md_undefined_symbol (char *name
)
12987 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
12988 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
12989 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
12990 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
12994 if (symbol_find (name
))
12995 as_bad (_("GOT already in symbol table"));
12996 GOT_symbol
= symbol_new (name
, undefined_section
,
12997 (valueT
) 0, &zero_address_frag
);
13004 /* Round up a section size to the appropriate boundary. */
13007 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
13009 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
13010 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
13012 /* For a.out, force the section size to be aligned. If we don't do
13013 this, BFD will align it for us, but it will not write out the
13014 final bytes of the section. This may be a bug in BFD, but it is
13015 easier to fix it here since that is how the other a.out targets
13019 align
= bfd_section_alignment (segment
);
13020 size
= ((size
+ (1 << align
) - 1) & (-((valueT
) 1 << align
)));
13027 /* On the i386, PC-relative offsets are relative to the start of the
13028 next instruction. That is, the address of the offset, plus its
13029 size, since the offset is always the last part of the insn. */
13032 md_pcrel_from (fixS
*fixP
)
13034 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
13040 s_bss (int ignore ATTRIBUTE_UNUSED
)
13044 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13046 obj_elf_section_change_hook ();
13048 temp
= get_absolute_expression ();
13049 subseg_set (bss_section
, (subsegT
) temp
);
13050 demand_empty_rest_of_line ();
13055 /* Remember constant directive. */
13058 i386_cons_align (int ignore ATTRIBUTE_UNUSED
)
13060 if (last_insn
.kind
!= last_insn_directive
13061 && (bfd_section_flags (now_seg
) & SEC_CODE
))
13063 last_insn
.seg
= now_seg
;
13064 last_insn
.kind
= last_insn_directive
;
13065 last_insn
.name
= "constant directive";
13066 last_insn
.file
= as_where (&last_insn
.line
);
13071 i386_validate_fix (fixS
*fixp
)
13073 if (fixp
->fx_subsy
)
13075 if (fixp
->fx_subsy
== GOT_symbol
)
13077 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
13081 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13082 if (fixp
->fx_tcbit2
)
13083 fixp
->fx_r_type
= (fixp
->fx_tcbit
13084 ? BFD_RELOC_X86_64_REX_GOTPCRELX
13085 : BFD_RELOC_X86_64_GOTPCRELX
);
13088 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
13093 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
13095 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
13097 fixp
->fx_subsy
= 0;
13100 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13101 else if (!object_64bit
)
13103 if (fixp
->fx_r_type
== BFD_RELOC_386_GOT32
13104 && fixp
->fx_tcbit2
)
13105 fixp
->fx_r_type
= BFD_RELOC_386_GOT32X
;
13111 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
13114 bfd_reloc_code_real_type code
;
13116 switch (fixp
->fx_r_type
)
13118 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13119 case BFD_RELOC_SIZE32
:
13120 case BFD_RELOC_SIZE64
:
13121 if (S_IS_DEFINED (fixp
->fx_addsy
)
13122 && !S_IS_EXTERNAL (fixp
->fx_addsy
))
13124 /* Resolve size relocation against local symbol to size of
13125 the symbol plus addend. */
13126 valueT value
= S_GET_SIZE (fixp
->fx_addsy
) + fixp
->fx_offset
;
13127 if (fixp
->fx_r_type
== BFD_RELOC_SIZE32
13128 && !fits_in_unsigned_long (value
))
13129 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
13130 _("symbol size computation overflow"));
13131 fixp
->fx_addsy
= NULL
;
13132 fixp
->fx_subsy
= NULL
;
13133 md_apply_fix (fixp
, (valueT
*) &value
, NULL
);
13137 /* Fall through. */
13139 case BFD_RELOC_X86_64_PLT32
:
13140 case BFD_RELOC_X86_64_GOT32
:
13141 case BFD_RELOC_X86_64_GOTPCREL
:
13142 case BFD_RELOC_X86_64_GOTPCRELX
:
13143 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
13144 case BFD_RELOC_386_PLT32
:
13145 case BFD_RELOC_386_GOT32
:
13146 case BFD_RELOC_386_GOT32X
:
13147 case BFD_RELOC_386_GOTOFF
:
13148 case BFD_RELOC_386_GOTPC
:
13149 case BFD_RELOC_386_TLS_GD
:
13150 case BFD_RELOC_386_TLS_LDM
:
13151 case BFD_RELOC_386_TLS_LDO_32
:
13152 case BFD_RELOC_386_TLS_IE_32
:
13153 case BFD_RELOC_386_TLS_IE
:
13154 case BFD_RELOC_386_TLS_GOTIE
:
13155 case BFD_RELOC_386_TLS_LE_32
:
13156 case BFD_RELOC_386_TLS_LE
:
13157 case BFD_RELOC_386_TLS_GOTDESC
:
13158 case BFD_RELOC_386_TLS_DESC_CALL
:
13159 case BFD_RELOC_X86_64_TLSGD
:
13160 case BFD_RELOC_X86_64_TLSLD
:
13161 case BFD_RELOC_X86_64_DTPOFF32
:
13162 case BFD_RELOC_X86_64_DTPOFF64
:
13163 case BFD_RELOC_X86_64_GOTTPOFF
:
13164 case BFD_RELOC_X86_64_TPOFF32
:
13165 case BFD_RELOC_X86_64_TPOFF64
:
13166 case BFD_RELOC_X86_64_GOTOFF64
:
13167 case BFD_RELOC_X86_64_GOTPC32
:
13168 case BFD_RELOC_X86_64_GOT64
:
13169 case BFD_RELOC_X86_64_GOTPCREL64
:
13170 case BFD_RELOC_X86_64_GOTPC64
:
13171 case BFD_RELOC_X86_64_GOTPLT64
:
13172 case BFD_RELOC_X86_64_PLTOFF64
:
13173 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
13174 case BFD_RELOC_X86_64_TLSDESC_CALL
:
13175 case BFD_RELOC_RVA
:
13176 case BFD_RELOC_VTABLE_ENTRY
:
13177 case BFD_RELOC_VTABLE_INHERIT
:
13179 case BFD_RELOC_32_SECREL
:
13181 code
= fixp
->fx_r_type
;
13183 case BFD_RELOC_X86_64_32S
:
13184 if (!fixp
->fx_pcrel
)
13186 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
13187 code
= fixp
->fx_r_type
;
13190 /* Fall through. */
13192 if (fixp
->fx_pcrel
)
13194 switch (fixp
->fx_size
)
13197 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
13198 _("can not do %d byte pc-relative relocation"),
13200 code
= BFD_RELOC_32_PCREL
;
13202 case 1: code
= BFD_RELOC_8_PCREL
; break;
13203 case 2: code
= BFD_RELOC_16_PCREL
; break;
13204 case 4: code
= BFD_RELOC_32_PCREL
; break;
13206 case 8: code
= BFD_RELOC_64_PCREL
; break;
13212 switch (fixp
->fx_size
)
13215 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
13216 _("can not do %d byte relocation"),
13218 code
= BFD_RELOC_32
;
13220 case 1: code
= BFD_RELOC_8
; break;
13221 case 2: code
= BFD_RELOC_16
; break;
13222 case 4: code
= BFD_RELOC_32
; break;
13224 case 8: code
= BFD_RELOC_64
; break;
13231 if ((code
== BFD_RELOC_32
13232 || code
== BFD_RELOC_32_PCREL
13233 || code
== BFD_RELOC_X86_64_32S
)
13235 && fixp
->fx_addsy
== GOT_symbol
)
13238 code
= BFD_RELOC_386_GOTPC
;
13240 code
= BFD_RELOC_X86_64_GOTPC32
;
13242 if ((code
== BFD_RELOC_64
|| code
== BFD_RELOC_64_PCREL
)
13244 && fixp
->fx_addsy
== GOT_symbol
)
13246 code
= BFD_RELOC_X86_64_GOTPC64
;
13249 rel
= XNEW (arelent
);
13250 rel
->sym_ptr_ptr
= XNEW (asymbol
*);
13251 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
13253 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
13255 if (!use_rela_relocations
)
13257 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
13258 vtable entry to be used in the relocation's section offset. */
13259 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
13260 rel
->address
= fixp
->fx_offset
;
13261 #if defined (OBJ_COFF) && defined (TE_PE)
13262 else if (fixp
->fx_addsy
&& S_IS_WEAK (fixp
->fx_addsy
))
13263 rel
->addend
= fixp
->fx_addnumber
- (S_GET_VALUE (fixp
->fx_addsy
) * 2);
13268 /* Use the rela in 64bit mode. */
13271 if (disallow_64bit_reloc
)
13274 case BFD_RELOC_X86_64_DTPOFF64
:
13275 case BFD_RELOC_X86_64_TPOFF64
:
13276 case BFD_RELOC_64_PCREL
:
13277 case BFD_RELOC_X86_64_GOTOFF64
:
13278 case BFD_RELOC_X86_64_GOT64
:
13279 case BFD_RELOC_X86_64_GOTPCREL64
:
13280 case BFD_RELOC_X86_64_GOTPC64
:
13281 case BFD_RELOC_X86_64_GOTPLT64
:
13282 case BFD_RELOC_X86_64_PLTOFF64
:
13283 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
13284 _("cannot represent relocation type %s in x32 mode"),
13285 bfd_get_reloc_code_name (code
));
13291 if (!fixp
->fx_pcrel
)
13292 rel
->addend
= fixp
->fx_offset
;
13296 case BFD_RELOC_X86_64_PLT32
:
13297 case BFD_RELOC_X86_64_GOT32
:
13298 case BFD_RELOC_X86_64_GOTPCREL
:
13299 case BFD_RELOC_X86_64_GOTPCRELX
:
13300 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
13301 case BFD_RELOC_X86_64_TLSGD
:
13302 case BFD_RELOC_X86_64_TLSLD
:
13303 case BFD_RELOC_X86_64_GOTTPOFF
:
13304 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
13305 case BFD_RELOC_X86_64_TLSDESC_CALL
:
13306 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
13309 rel
->addend
= (section
->vma
13311 + fixp
->fx_addnumber
13312 + md_pcrel_from (fixp
));
13317 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
13318 if (rel
->howto
== NULL
)
13320 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
13321 _("cannot represent relocation type %s"),
13322 bfd_get_reloc_code_name (code
));
13323 /* Set howto to a garbage value so that we can keep going. */
13324 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
13325 gas_assert (rel
->howto
!= NULL
);
13331 #include "tc-i386-intel.c"
13334 tc_x86_parse_to_dw2regnum (expressionS
*exp
)
13336 int saved_naked_reg
;
13337 char saved_register_dot
;
13339 saved_naked_reg
= allow_naked_reg
;
13340 allow_naked_reg
= 1;
13341 saved_register_dot
= register_chars
['.'];
13342 register_chars
['.'] = '.';
13343 allow_pseudo_reg
= 1;
13344 expression_and_evaluate (exp
);
13345 allow_pseudo_reg
= 0;
13346 register_chars
['.'] = saved_register_dot
;
13347 allow_naked_reg
= saved_naked_reg
;
13349 if (exp
->X_op
== O_register
&& exp
->X_add_number
>= 0)
13351 if ((addressT
) exp
->X_add_number
< i386_regtab_size
)
13353 exp
->X_op
= O_constant
;
13354 exp
->X_add_number
= i386_regtab
[exp
->X_add_number
]
13355 .dw2_regnum
[flag_code
>> 1];
13358 exp
->X_op
= O_illegal
;
13363 tc_x86_frame_initial_instructions (void)
13365 static unsigned int sp_regno
[2];
13367 if (!sp_regno
[flag_code
>> 1])
13369 char *saved_input
= input_line_pointer
;
13370 char sp
[][4] = {"esp", "rsp"};
13373 input_line_pointer
= sp
[flag_code
>> 1];
13374 tc_x86_parse_to_dw2regnum (&exp
);
13375 gas_assert (exp
.X_op
== O_constant
);
13376 sp_regno
[flag_code
>> 1] = exp
.X_add_number
;
13377 input_line_pointer
= saved_input
;
13380 cfi_add_CFA_def_cfa (sp_regno
[flag_code
>> 1], -x86_cie_data_alignment
);
13381 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
13385 x86_dwarf2_addr_size (void)
13387 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
13388 if (x86_elf_abi
== X86_64_X32_ABI
)
13391 return bfd_arch_bits_per_address (stdoutput
) / 8;
13395 i386_elf_section_type (const char *str
, size_t len
)
13397 if (flag_code
== CODE_64BIT
13398 && len
== sizeof ("unwind") - 1
13399 && strncmp (str
, "unwind", 6) == 0)
13400 return SHT_X86_64_UNWIND
;
13407 i386_solaris_fix_up_eh_frame (segT sec
)
13409 if (flag_code
== CODE_64BIT
)
13410 elf_section_type (sec
) = SHT_X86_64_UNWIND
;
13416 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
13420 exp
.X_op
= O_secrel
;
13421 exp
.X_add_symbol
= symbol
;
13422 exp
.X_add_number
= 0;
13423 emit_expr (&exp
, size
);
13427 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13428 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
13431 x86_64_section_letter (int letter
, const char **ptr_msg
)
13433 if (flag_code
== CODE_64BIT
)
13436 return SHF_X86_64_LARGE
;
13438 *ptr_msg
= _("bad .section directive: want a,l,w,x,M,S,G,T in string");
13441 *ptr_msg
= _("bad .section directive: want a,w,x,M,S,G,T in string");
13446 x86_64_section_word (char *str
, size_t len
)
13448 if (len
== 5 && flag_code
== CODE_64BIT
&& CONST_STRNEQ (str
, "large"))
13449 return SHF_X86_64_LARGE
;
13455 handle_large_common (int small ATTRIBUTE_UNUSED
)
13457 if (flag_code
!= CODE_64BIT
)
13459 s_comm_internal (0, elf_common_parse
);
13460 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
13464 static segT lbss_section
;
13465 asection
*saved_com_section_ptr
= elf_com_section_ptr
;
13466 asection
*saved_bss_section
= bss_section
;
13468 if (lbss_section
== NULL
)
13470 flagword applicable
;
13471 segT seg
= now_seg
;
13472 subsegT subseg
= now_subseg
;
13474 /* The .lbss section is for local .largecomm symbols. */
13475 lbss_section
= subseg_new (".lbss", 0);
13476 applicable
= bfd_applicable_section_flags (stdoutput
);
13477 bfd_set_section_flags (lbss_section
, applicable
& SEC_ALLOC
);
13478 seg_info (lbss_section
)->bss
= 1;
13480 subseg_set (seg
, subseg
);
13483 elf_com_section_ptr
= &_bfd_elf_large_com_section
;
13484 bss_section
= lbss_section
;
13486 s_comm_internal (0, elf_common_parse
);
13488 elf_com_section_ptr
= saved_com_section_ptr
;
13489 bss_section
= saved_bss_section
;
13492 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */