1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright (C) 1989-2018 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 /* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
23 x86_64 support by Jan Hubicka (jh@suse.cz)
24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
29 #include "safe-ctype.h"
31 #include "dwarf2dbg.h"
32 #include "dw2gencfi.h"
33 #include "elf/x86-64.h"
34 #include "opcodes/i386-init.h"
36 #ifndef REGISTER_WARNINGS
37 #define REGISTER_WARNINGS 1
40 #ifndef INFER_ADDR_PREFIX
41 #define INFER_ADDR_PREFIX 1
45 #define DEFAULT_ARCH "i386"
50 #define INLINE __inline__
56 /* Prefixes will be emitted in the order defined below.
57 WAIT_PREFIX must be the first prefix since FWAIT is really is an
58 instruction, and so must come before any prefixes.
59 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
60 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
66 #define HLE_PREFIX REP_PREFIX
67 #define BND_PREFIX REP_PREFIX
69 #define REX_PREFIX 6 /* must come last. */
70 #define MAX_PREFIXES 7 /* max prefixes per opcode */
72 /* we define the syntax here (modulo base,index,scale syntax) */
73 #define REGISTER_PREFIX '%'
74 #define IMMEDIATE_PREFIX '$'
75 #define ABSOLUTE_PREFIX '*'
77 /* these are the instruction mnemonic suffixes in AT&T syntax or
78 memory operand size in Intel syntax. */
79 #define WORD_MNEM_SUFFIX 'w'
80 #define BYTE_MNEM_SUFFIX 'b'
81 #define SHORT_MNEM_SUFFIX 's'
82 #define LONG_MNEM_SUFFIX 'l'
83 #define QWORD_MNEM_SUFFIX 'q'
84 /* Intel Syntax. Use a non-ascii letter since since it never appears
86 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
88 #define END_OF_INSN '\0'
91 'templates' is for grouping together 'template' structures for opcodes
92 of the same name. This is only used for storing the insns in the grand
93 ole hash table of insns.
94 The templates themselves start at START and range up to (but not including)
99 const insn_template
*start
;
100 const insn_template
*end
;
104 /* 386 operand encoding bytes: see 386 book for details of this. */
107 unsigned int regmem
; /* codes register or memory operand */
108 unsigned int reg
; /* codes register operand (or extended opcode) */
109 unsigned int mode
; /* how to interpret regmem & reg */
113 /* x86-64 extension prefix. */
114 typedef int rex_byte
;
116 /* 386 opcode byte to code indirect addressing. */
125 /* x86 arch names, types and features */
128 const char *name
; /* arch name */
129 unsigned int len
; /* arch string length */
130 enum processor_type type
; /* arch type */
131 i386_cpu_flags flags
; /* cpu feature flags */
132 unsigned int skip
; /* show_arch should skip this. */
136 /* Used to turn off indicated flags. */
139 const char *name
; /* arch name */
140 unsigned int len
; /* arch string length */
141 i386_cpu_flags flags
; /* cpu feature flags */
145 static void update_code_flag (int, int);
146 static void set_code_flag (int);
147 static void set_16bit_gcc_code_flag (int);
148 static void set_intel_syntax (int);
149 static void set_intel_mnemonic (int);
150 static void set_allow_index_reg (int);
151 static void set_check (int);
152 static void set_cpu_arch (int);
154 static void pe_directive_secrel (int);
156 static void signed_cons (int);
157 static char *output_invalid (int c
);
158 static int i386_finalize_immediate (segT
, expressionS
*, i386_operand_type
,
160 static int i386_finalize_displacement (segT
, expressionS
*, i386_operand_type
,
162 static int i386_att_operand (char *);
163 static int i386_intel_operand (char *, int);
164 static int i386_intel_simplify (expressionS
*);
165 static int i386_intel_parse_name (const char *, expressionS
*);
166 static const reg_entry
*parse_register (char *, char **);
167 static char *parse_insn (char *, char *);
168 static char *parse_operands (char *, const char *);
169 static void swap_operands (void);
170 static void swap_2_operands (int, int);
171 static void optimize_imm (void);
172 static void optimize_disp (void);
173 static const insn_template
*match_template (char);
174 static int check_string (void);
175 static int process_suffix (void);
176 static int check_byte_reg (void);
177 static int check_long_reg (void);
178 static int check_qword_reg (void);
179 static int check_word_reg (void);
180 static int finalize_imm (void);
181 static int process_operands (void);
182 static const seg_entry
*build_modrm_byte (void);
183 static void output_insn (void);
184 static void output_imm (fragS
*, offsetT
);
185 static void output_disp (fragS
*, offsetT
);
187 static void s_bss (int);
189 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
190 static void handle_large_common (int small ATTRIBUTE_UNUSED
);
193 static const char *default_arch
= DEFAULT_ARCH
;
195 /* This struct describes rounding control and SAE in the instruction. */
209 static struct RC_Operation rc_op
;
211 /* The struct describes masking, applied to OPERAND in the instruction.
212 MASK is a pointer to the corresponding mask register. ZEROING tells
213 whether merging or zeroing mask is used. */
214 struct Mask_Operation
216 const reg_entry
*mask
;
217 unsigned int zeroing
;
218 /* The operand where this operation is associated. */
222 static struct Mask_Operation mask_op
;
224 /* The struct describes broadcasting, applied to OPERAND. FACTOR is
226 struct Broadcast_Operation
228 /* Type of broadcast: {1to2}, {1to4}, {1to8}, or {1to16}. */
231 /* Index of broadcasted operand. */
235 static struct Broadcast_Operation broadcast_op
;
240 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
241 unsigned char bytes
[4];
243 /* Destination or source register specifier. */
244 const reg_entry
*register_specifier
;
247 /* 'md_assemble ()' gathers together information and puts it into a
254 const reg_entry
*regs
;
259 operand_size_mismatch
,
260 operand_type_mismatch
,
261 register_type_mismatch
,
262 number_of_operands_mismatch
,
263 invalid_instruction_suffix
,
265 unsupported_with_intel_mnemonic
,
268 invalid_vsib_address
,
269 invalid_vector_register_set
,
270 unsupported_vector_index_register
,
271 unsupported_broadcast
,
272 broadcast_not_on_src_operand
,
275 mask_not_on_destination
,
278 rc_sae_operand_not_last_imm
,
279 invalid_register_operand
,
284 /* TM holds the template for the insn were currently assembling. */
287 /* SUFFIX holds the instruction size suffix for byte, word, dword
288 or qword, if given. */
291 /* OPERANDS gives the number of given operands. */
292 unsigned int operands
;
294 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
295 of given register, displacement, memory operands and immediate
297 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
299 /* TYPES [i] is the type (see above #defines) which tells us how to
300 use OP[i] for the corresponding operand. */
301 i386_operand_type types
[MAX_OPERANDS
];
303 /* Displacement expression, immediate expression, or register for each
305 union i386_op op
[MAX_OPERANDS
];
307 /* Flags for operands. */
308 unsigned int flags
[MAX_OPERANDS
];
309 #define Operand_PCrel 1
311 /* Relocation type for operand */
312 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
314 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
315 the base index byte below. */
316 const reg_entry
*base_reg
;
317 const reg_entry
*index_reg
;
318 unsigned int log2_scale_factor
;
320 /* SEG gives the seg_entries of this insn. They are zero unless
321 explicit segment overrides are given. */
322 const seg_entry
*seg
[2];
324 /* Copied first memory operand string, for re-checking. */
327 /* PREFIX holds all the given prefix opcodes (usually null).
328 PREFIXES is the number of prefix opcodes. */
329 unsigned int prefixes
;
330 unsigned char prefix
[MAX_PREFIXES
];
332 /* RM and SIB are the modrm byte and the sib byte where the
333 addressing modes of this insn are encoded. */
340 /* Masking attributes. */
341 struct Mask_Operation
*mask
;
343 /* Rounding control and SAE attributes. */
344 struct RC_Operation
*rounding
;
346 /* Broadcasting attributes. */
347 struct Broadcast_Operation
*broadcast
;
349 /* Compressed disp8*N attribute. */
350 unsigned int memshift
;
352 /* Prefer load or store in encoding. */
355 dir_encoding_default
= 0,
360 /* Prefer 8bit or 32bit displacement in encoding. */
363 disp_encoding_default
= 0,
368 /* Prefer the REX byte in encoding. */
369 bfd_boolean rex_encoding
;
371 /* Disable instruction size optimization. */
372 bfd_boolean no_optimize
;
374 /* How to encode vector instructions. */
377 vex_encoding_default
= 0,
384 const char *rep_prefix
;
387 const char *hle_prefix
;
389 /* Have BND prefix. */
390 const char *bnd_prefix
;
392 /* Have NOTRACK prefix. */
393 const char *notrack_prefix
;
396 enum i386_error error
;
399 typedef struct _i386_insn i386_insn
;
401 /* Link RC type with corresponding string, that'll be looked for in
410 static const struct RC_name RC_NamesTable
[] =
412 { rne
, STRING_COMMA_LEN ("rn-sae") },
413 { rd
, STRING_COMMA_LEN ("rd-sae") },
414 { ru
, STRING_COMMA_LEN ("ru-sae") },
415 { rz
, STRING_COMMA_LEN ("rz-sae") },
416 { saeonly
, STRING_COMMA_LEN ("sae") },
419 /* List of chars besides those in app.c:symbol_chars that can start an
420 operand. Used to prevent the scrubber eating vital white-space. */
421 const char extra_symbol_chars
[] = "*%-([{}"
430 #if (defined (TE_I386AIX) \
431 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
432 && !defined (TE_GNU) \
433 && !defined (TE_LINUX) \
434 && !defined (TE_NACL) \
435 && !defined (TE_FreeBSD) \
436 && !defined (TE_DragonFly) \
437 && !defined (TE_NetBSD)))
438 /* This array holds the chars that always start a comment. If the
439 pre-processor is disabled, these aren't very useful. The option
440 --divide will remove '/' from this list. */
441 const char *i386_comment_chars
= "#/";
442 #define SVR4_COMMENT_CHARS 1
443 #define PREFIX_SEPARATOR '\\'
446 const char *i386_comment_chars
= "#";
447 #define PREFIX_SEPARATOR '/'
450 /* This array holds the chars that only start a comment at the beginning of
451 a line. If the line seems to have the form '# 123 filename'
452 .line and .file directives will appear in the pre-processed output.
453 Note that input_file.c hand checks for '#' at the beginning of the
454 first line of the input file. This is because the compiler outputs
455 #NO_APP at the beginning of its output.
456 Also note that comments started like this one will always work if
457 '/' isn't otherwise defined. */
458 const char line_comment_chars
[] = "#/";
460 const char line_separator_chars
[] = ";";
462 /* Chars that can be used to separate mant from exp in floating point
464 const char EXP_CHARS
[] = "eE";
466 /* Chars that mean this number is a floating point constant
469 const char FLT_CHARS
[] = "fFdDxX";
471 /* Tables for lexical analysis. */
472 static char mnemonic_chars
[256];
473 static char register_chars
[256];
474 static char operand_chars
[256];
475 static char identifier_chars
[256];
476 static char digit_chars
[256];
478 /* Lexical macros. */
479 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
480 #define is_operand_char(x) (operand_chars[(unsigned char) x])
481 #define is_register_char(x) (register_chars[(unsigned char) x])
482 #define is_space_char(x) ((x) == ' ')
483 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
484 #define is_digit_char(x) (digit_chars[(unsigned char) x])
486 /* All non-digit non-letter characters that may occur in an operand. */
487 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
489 /* md_assemble() always leaves the strings it's passed unaltered. To
490 effect this we maintain a stack of saved characters that we've smashed
491 with '\0's (indicating end of strings for various sub-fields of the
492 assembler instruction). */
493 static char save_stack
[32];
494 static char *save_stack_p
;
495 #define END_STRING_AND_SAVE(s) \
496 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
497 #define RESTORE_END_STRING(s) \
498 do { *(s) = *--save_stack_p; } while (0)
500 /* The instruction we're assembling. */
503 /* Possible templates for current insn. */
504 static const templates
*current_templates
;
506 /* Per instruction expressionS buffers: max displacements & immediates. */
507 static expressionS disp_expressions
[MAX_MEMORY_OPERANDS
];
508 static expressionS im_expressions
[MAX_IMMEDIATE_OPERANDS
];
510 /* Current operand we are working on. */
511 static int this_operand
= -1;
513 /* We support four different modes. FLAG_CODE variable is used to distinguish
521 static enum flag_code flag_code
;
522 static unsigned int object_64bit
;
523 static unsigned int disallow_64bit_reloc
;
524 static int use_rela_relocations
= 0;
526 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
527 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
528 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
530 /* The ELF ABI to use. */
538 static enum x86_elf_abi x86_elf_abi
= I386_ABI
;
541 #if defined (TE_PE) || defined (TE_PEP)
542 /* Use big object file format. */
543 static int use_big_obj
= 0;
546 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
547 /* 1 if generating code for a shared library. */
548 static int shared
= 0;
551 /* 1 for intel syntax,
553 static int intel_syntax
= 0;
555 /* 1 for Intel64 ISA,
559 /* 1 for intel mnemonic,
560 0 if att mnemonic. */
561 static int intel_mnemonic
= !SYSV386_COMPAT
;
563 /* 1 if pseudo registers are permitted. */
564 static int allow_pseudo_reg
= 0;
566 /* 1 if register prefix % not required. */
567 static int allow_naked_reg
= 0;
569 /* 1 if the assembler should add BND prefix for all control-transferring
570 instructions supporting it, even if this prefix wasn't specified
572 static int add_bnd_prefix
= 0;
574 /* 1 if pseudo index register, eiz/riz, is allowed . */
575 static int allow_index_reg
= 0;
577 /* 1 if the assembler should ignore LOCK prefix, even if it was
578 specified explicitly. */
579 static int omit_lock_prefix
= 0;
581 /* 1 if the assembler should encode lfence, mfence, and sfence as
582 "lock addl $0, (%{re}sp)". */
583 static int avoid_fence
= 0;
585 /* 1 if the assembler should generate relax relocations. */
587 static int generate_relax_relocations
588 = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS
;
590 static enum check_kind
596 sse_check
, operand_check
= check_warning
;
599 1. Clear the REX_W bit with register operand if possible.
600 2. Above plus use 128bit vector instruction to clear the full vector
603 static int optimize
= 0;
606 1. Clear the REX_W bit with register operand if possible.
607 2. Above plus use 128bit vector instruction to clear the full vector
609 3. Above plus optimize "test{q,l,w} $imm8,%r{64,32,16}" to
612 static int optimize_for_space
= 0;
614 /* Register prefix used for error message. */
615 static const char *register_prefix
= "%";
617 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
618 leave, push, and pop instructions so that gcc has the same stack
619 frame as in 32 bit mode. */
620 static char stackop_size
= '\0';
622 /* Non-zero to optimize code alignment. */
623 int optimize_align_code
= 1;
625 /* Non-zero to quieten some warnings. */
626 static int quiet_warnings
= 0;
629 static const char *cpu_arch_name
= NULL
;
630 static char *cpu_sub_arch_name
= NULL
;
632 /* CPU feature flags. */
633 static i386_cpu_flags cpu_arch_flags
= CPU_UNKNOWN_FLAGS
;
635 /* If we have selected a cpu we are generating instructions for. */
636 static int cpu_arch_tune_set
= 0;
638 /* Cpu we are generating instructions for. */
639 enum processor_type cpu_arch_tune
= PROCESSOR_UNKNOWN
;
641 /* CPU feature flags of cpu we are generating instructions for. */
642 static i386_cpu_flags cpu_arch_tune_flags
;
644 /* CPU instruction set architecture used. */
645 enum processor_type cpu_arch_isa
= PROCESSOR_UNKNOWN
;
647 /* CPU feature flags of instruction set architecture used. */
648 i386_cpu_flags cpu_arch_isa_flags
;
650 /* If set, conditional jumps are not automatically promoted to handle
651 larger than a byte offset. */
652 static unsigned int no_cond_jump_promotion
= 0;
654 /* Encode SSE instructions with VEX prefix. */
655 static unsigned int sse2avx
;
657 /* Encode scalar AVX instructions with specific vector length. */
664 /* Encode scalar EVEX LIG instructions with specific vector length. */
672 /* Encode EVEX WIG instructions with specific evex.w. */
679 /* Value to encode in EVEX RC bits, for SAE-only instructions. */
680 static enum rc_type evexrcig
= rne
;
682 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
683 static symbolS
*GOT_symbol
;
685 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
686 unsigned int x86_dwarf2_return_column
;
688 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
689 int x86_cie_data_alignment
;
691 /* Interface to relax_segment.
692 There are 3 major relax states for 386 jump insns because the
693 different types of jumps add different sizes to frags when we're
694 figuring out what sort of jump to choose to reach a given label. */
697 #define UNCOND_JUMP 0
699 #define COND_JUMP86 2
704 #define SMALL16 (SMALL | CODE16)
706 #define BIG16 (BIG | CODE16)
710 #define INLINE __inline__
716 #define ENCODE_RELAX_STATE(type, size) \
717 ((relax_substateT) (((type) << 2) | (size)))
718 #define TYPE_FROM_RELAX_STATE(s) \
720 #define DISP_SIZE_FROM_RELAX_STATE(s) \
721 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
723 /* This table is used by relax_frag to promote short jumps to long
724 ones where necessary. SMALL (short) jumps may be promoted to BIG
725 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
726 don't allow a short jump in a 32 bit code segment to be promoted to
727 a 16 bit offset jump because it's slower (requires data size
728 prefix), and doesn't work, unless the destination is in the bottom
729 64k of the code segment (The top 16 bits of eip are zeroed). */
731 const relax_typeS md_relax_table
[] =
734 1) most positive reach of this state,
735 2) most negative reach of this state,
736 3) how many bytes this mode will have in the variable part of the frag
737 4) which index into the table to try if we can't fit into this one. */
739 /* UNCOND_JUMP states. */
740 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
741 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
742 /* dword jmp adds 4 bytes to frag:
743 0 extra opcode bytes, 4 displacement bytes. */
745 /* word jmp adds 2 byte2 to frag:
746 0 extra opcode bytes, 2 displacement bytes. */
749 /* COND_JUMP states. */
750 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
751 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
752 /* dword conditionals adds 5 bytes to frag:
753 1 extra opcode byte, 4 displacement bytes. */
755 /* word conditionals add 3 bytes to frag:
756 1 extra opcode byte, 2 displacement bytes. */
759 /* COND_JUMP86 states. */
760 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
761 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
762 /* dword conditionals adds 5 bytes to frag:
763 1 extra opcode byte, 4 displacement bytes. */
765 /* word conditionals add 4 bytes to frag:
766 1 displacement byte and a 3 byte long branch insn. */
770 static const arch_entry cpu_arch
[] =
772 /* Do not replace the first two entries - i386_target_format()
773 relies on them being there in this order. */
774 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32
,
775 CPU_GENERIC32_FLAGS
, 0 },
776 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64
,
777 CPU_GENERIC64_FLAGS
, 0 },
778 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN
,
780 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN
,
782 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN
,
784 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386
,
786 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486
,
788 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM
,
790 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO
,
792 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM
,
794 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO
,
795 CPU_PENTIUMPRO_FLAGS
, 0 },
796 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO
,
798 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO
,
800 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4
,
802 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA
,
804 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA
,
805 CPU_NOCONA_FLAGS
, 0 },
806 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE
,
808 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE
,
810 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2
,
811 CPU_CORE2_FLAGS
, 1 },
812 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2
,
813 CPU_CORE2_FLAGS
, 0 },
814 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7
,
815 CPU_COREI7_FLAGS
, 0 },
816 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM
,
818 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM
,
820 { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU
,
821 CPU_IAMCU_FLAGS
, 0 },
822 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6
,
824 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6
,
826 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON
,
827 CPU_ATHLON_FLAGS
, 0 },
828 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8
,
830 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8
,
832 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8
,
834 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10
,
835 CPU_AMDFAM10_FLAGS
, 0 },
836 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD
,
837 CPU_BDVER1_FLAGS
, 0 },
838 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD
,
839 CPU_BDVER2_FLAGS
, 0 },
840 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD
,
841 CPU_BDVER3_FLAGS
, 0 },
842 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD
,
843 CPU_BDVER4_FLAGS
, 0 },
844 { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER
,
845 CPU_ZNVER1_FLAGS
, 0 },
846 { STRING_COMMA_LEN ("znver2"), PROCESSOR_ZNVER
,
847 CPU_ZNVER2_FLAGS
, 0 },
848 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT
,
849 CPU_BTVER1_FLAGS
, 0 },
850 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT
,
851 CPU_BTVER2_FLAGS
, 0 },
852 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN
,
854 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN
,
856 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN
,
858 { STRING_COMMA_LEN (".687"), PROCESSOR_UNKNOWN
,
860 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN
,
862 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN
,
864 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN
,
866 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN
,
868 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN
,
869 CPU_SSSE3_FLAGS
, 0 },
870 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN
,
871 CPU_SSE4_1_FLAGS
, 0 },
872 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN
,
873 CPU_SSE4_2_FLAGS
, 0 },
874 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN
,
875 CPU_SSE4_2_FLAGS
, 0 },
876 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN
,
878 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN
,
880 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN
,
881 CPU_AVX512F_FLAGS
, 0 },
882 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN
,
883 CPU_AVX512CD_FLAGS
, 0 },
884 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN
,
885 CPU_AVX512ER_FLAGS
, 0 },
886 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN
,
887 CPU_AVX512PF_FLAGS
, 0 },
888 { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN
,
889 CPU_AVX512DQ_FLAGS
, 0 },
890 { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN
,
891 CPU_AVX512BW_FLAGS
, 0 },
892 { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN
,
893 CPU_AVX512VL_FLAGS
, 0 },
894 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN
,
896 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN
,
897 CPU_VMFUNC_FLAGS
, 0 },
898 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN
,
900 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN
,
901 CPU_XSAVE_FLAGS
, 0 },
902 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN
,
903 CPU_XSAVEOPT_FLAGS
, 0 },
904 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN
,
905 CPU_XSAVEC_FLAGS
, 0 },
906 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN
,
907 CPU_XSAVES_FLAGS
, 0 },
908 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN
,
910 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN
,
911 CPU_PCLMUL_FLAGS
, 0 },
912 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN
,
913 CPU_PCLMUL_FLAGS
, 1 },
914 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN
,
915 CPU_FSGSBASE_FLAGS
, 0 },
916 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN
,
917 CPU_RDRND_FLAGS
, 0 },
918 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN
,
920 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN
,
922 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN
,
924 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN
,
926 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN
,
928 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN
,
930 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN
,
931 CPU_MOVBE_FLAGS
, 0 },
932 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN
,
934 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN
,
936 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN
,
937 CPU_LZCNT_FLAGS
, 0 },
938 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN
,
940 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN
,
942 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN
,
943 CPU_INVPCID_FLAGS
, 0 },
944 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN
,
945 CPU_CLFLUSH_FLAGS
, 0 },
946 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN
,
948 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN
,
949 CPU_SYSCALL_FLAGS
, 0 },
950 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN
,
951 CPU_RDTSCP_FLAGS
, 0 },
952 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN
,
953 CPU_3DNOW_FLAGS
, 0 },
954 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN
,
955 CPU_3DNOWA_FLAGS
, 0 },
956 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN
,
957 CPU_PADLOCK_FLAGS
, 0 },
958 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN
,
960 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN
,
962 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN
,
963 CPU_SSE4A_FLAGS
, 0 },
964 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN
,
966 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN
,
968 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN
,
970 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN
,
972 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN
,
973 CPU_RDSEED_FLAGS
, 0 },
974 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN
,
975 CPU_PRFCHW_FLAGS
, 0 },
976 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN
,
978 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN
,
980 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN
,
982 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN
,
983 CPU_CLFLUSHOPT_FLAGS
, 0 },
984 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN
,
985 CPU_PREFETCHWT1_FLAGS
, 0 },
986 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN
,
988 { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN
,
990 { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN
,
991 CPU_AVX512IFMA_FLAGS
, 0 },
992 { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN
,
993 CPU_AVX512VBMI_FLAGS
, 0 },
994 { STRING_COMMA_LEN (".avx512_4fmaps"), PROCESSOR_UNKNOWN
,
995 CPU_AVX512_4FMAPS_FLAGS
, 0 },
996 { STRING_COMMA_LEN (".avx512_4vnniw"), PROCESSOR_UNKNOWN
,
997 CPU_AVX512_4VNNIW_FLAGS
, 0 },
998 { STRING_COMMA_LEN (".avx512_vpopcntdq"), PROCESSOR_UNKNOWN
,
999 CPU_AVX512_VPOPCNTDQ_FLAGS
, 0 },
1000 { STRING_COMMA_LEN (".avx512_vbmi2"), PROCESSOR_UNKNOWN
,
1001 CPU_AVX512_VBMI2_FLAGS
, 0 },
1002 { STRING_COMMA_LEN (".avx512_vnni"), PROCESSOR_UNKNOWN
,
1003 CPU_AVX512_VNNI_FLAGS
, 0 },
1004 { STRING_COMMA_LEN (".avx512_bitalg"), PROCESSOR_UNKNOWN
,
1005 CPU_AVX512_BITALG_FLAGS
, 0 },
1006 { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN
,
1007 CPU_CLZERO_FLAGS
, 0 },
1008 { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN
,
1009 CPU_MWAITX_FLAGS
, 0 },
1010 { STRING_COMMA_LEN (".ospke"), PROCESSOR_UNKNOWN
,
1011 CPU_OSPKE_FLAGS
, 0 },
1012 { STRING_COMMA_LEN (".rdpid"), PROCESSOR_UNKNOWN
,
1013 CPU_RDPID_FLAGS
, 0 },
1014 { STRING_COMMA_LEN (".ptwrite"), PROCESSOR_UNKNOWN
,
1015 CPU_PTWRITE_FLAGS
, 0 },
1016 { STRING_COMMA_LEN (".ibt"), PROCESSOR_UNKNOWN
,
1018 { STRING_COMMA_LEN (".shstk"), PROCESSOR_UNKNOWN
,
1019 CPU_SHSTK_FLAGS
, 0 },
1020 { STRING_COMMA_LEN (".gfni"), PROCESSOR_UNKNOWN
,
1021 CPU_GFNI_FLAGS
, 0 },
1022 { STRING_COMMA_LEN (".vaes"), PROCESSOR_UNKNOWN
,
1023 CPU_VAES_FLAGS
, 0 },
1024 { STRING_COMMA_LEN (".vpclmulqdq"), PROCESSOR_UNKNOWN
,
1025 CPU_VPCLMULQDQ_FLAGS
, 0 },
1026 { STRING_COMMA_LEN (".wbnoinvd"), PROCESSOR_UNKNOWN
,
1027 CPU_WBNOINVD_FLAGS
, 0 },
1028 { STRING_COMMA_LEN (".pconfig"), PROCESSOR_UNKNOWN
,
1029 CPU_PCONFIG_FLAGS
, 0 },
1030 { STRING_COMMA_LEN (".waitpkg"), PROCESSOR_UNKNOWN
,
1031 CPU_WAITPKG_FLAGS
, 0 },
1032 { STRING_COMMA_LEN (".cldemote"), PROCESSOR_UNKNOWN
,
1033 CPU_CLDEMOTE_FLAGS
, 0 },
1034 { STRING_COMMA_LEN (".movdiri"), PROCESSOR_UNKNOWN
,
1035 CPU_MOVDIRI_FLAGS
, 0 },
1036 { STRING_COMMA_LEN (".movdir64b"), PROCESSOR_UNKNOWN
,
1037 CPU_MOVDIR64B_FLAGS
, 0 },
1040 static const noarch_entry cpu_noarch
[] =
1042 { STRING_COMMA_LEN ("no87"), CPU_ANY_X87_FLAGS
},
1043 { STRING_COMMA_LEN ("no287"), CPU_ANY_287_FLAGS
},
1044 { STRING_COMMA_LEN ("no387"), CPU_ANY_387_FLAGS
},
1045 { STRING_COMMA_LEN ("no687"), CPU_ANY_687_FLAGS
},
1046 { STRING_COMMA_LEN ("nommx"), CPU_ANY_MMX_FLAGS
},
1047 { STRING_COMMA_LEN ("nosse"), CPU_ANY_SSE_FLAGS
},
1048 { STRING_COMMA_LEN ("nosse2"), CPU_ANY_SSE2_FLAGS
},
1049 { STRING_COMMA_LEN ("nosse3"), CPU_ANY_SSE3_FLAGS
},
1050 { STRING_COMMA_LEN ("nossse3"), CPU_ANY_SSSE3_FLAGS
},
1051 { STRING_COMMA_LEN ("nosse4.1"), CPU_ANY_SSE4_1_FLAGS
},
1052 { STRING_COMMA_LEN ("nosse4.2"), CPU_ANY_SSE4_2_FLAGS
},
1053 { STRING_COMMA_LEN ("nosse4"), CPU_ANY_SSE4_1_FLAGS
},
1054 { STRING_COMMA_LEN ("noavx"), CPU_ANY_AVX_FLAGS
},
1055 { STRING_COMMA_LEN ("noavx2"), CPU_ANY_AVX2_FLAGS
},
1056 { STRING_COMMA_LEN ("noavx512f"), CPU_ANY_AVX512F_FLAGS
},
1057 { STRING_COMMA_LEN ("noavx512cd"), CPU_ANY_AVX512CD_FLAGS
},
1058 { STRING_COMMA_LEN ("noavx512er"), CPU_ANY_AVX512ER_FLAGS
},
1059 { STRING_COMMA_LEN ("noavx512pf"), CPU_ANY_AVX512PF_FLAGS
},
1060 { STRING_COMMA_LEN ("noavx512dq"), CPU_ANY_AVX512DQ_FLAGS
},
1061 { STRING_COMMA_LEN ("noavx512bw"), CPU_ANY_AVX512BW_FLAGS
},
1062 { STRING_COMMA_LEN ("noavx512vl"), CPU_ANY_AVX512VL_FLAGS
},
1063 { STRING_COMMA_LEN ("noavx512ifma"), CPU_ANY_AVX512IFMA_FLAGS
},
1064 { STRING_COMMA_LEN ("noavx512vbmi"), CPU_ANY_AVX512VBMI_FLAGS
},
1065 { STRING_COMMA_LEN ("noavx512_4fmaps"), CPU_ANY_AVX512_4FMAPS_FLAGS
},
1066 { STRING_COMMA_LEN ("noavx512_4vnniw"), CPU_ANY_AVX512_4VNNIW_FLAGS
},
1067 { STRING_COMMA_LEN ("noavx512_vpopcntdq"), CPU_ANY_AVX512_VPOPCNTDQ_FLAGS
},
1068 { STRING_COMMA_LEN ("noavx512_vbmi2"), CPU_ANY_AVX512_VBMI2_FLAGS
},
1069 { STRING_COMMA_LEN ("noavx512_vnni"), CPU_ANY_AVX512_VNNI_FLAGS
},
1070 { STRING_COMMA_LEN ("noavx512_bitalg"), CPU_ANY_AVX512_BITALG_FLAGS
},
1071 { STRING_COMMA_LEN ("noibt"), CPU_ANY_IBT_FLAGS
},
1072 { STRING_COMMA_LEN ("noshstk"), CPU_ANY_SHSTK_FLAGS
},
1073 { STRING_COMMA_LEN ("nomovdiri"), CPU_ANY_MOVDIRI_FLAGS
},
1074 { STRING_COMMA_LEN ("nomovdir64b"), CPU_ANY_MOVDIR64B_FLAGS
},
1078 /* Like s_lcomm_internal in gas/read.c but the alignment string
1079 is allowed to be optional. */
1082 pe_lcomm_internal (int needs_align
, symbolS
*symbolP
, addressT size
)
1089 && *input_line_pointer
== ',')
1091 align
= parse_align (needs_align
- 1);
1093 if (align
== (addressT
) -1)
1108 bss_alloc (symbolP
, size
, align
);
1113 pe_lcomm (int needs_align
)
1115 s_comm_internal (needs_align
* 2, pe_lcomm_internal
);
1119 const pseudo_typeS md_pseudo_table
[] =
1121 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
1122 {"align", s_align_bytes
, 0},
1124 {"align", s_align_ptwo
, 0},
1126 {"arch", set_cpu_arch
, 0},
1130 {"lcomm", pe_lcomm
, 1},
1132 {"ffloat", float_cons
, 'f'},
1133 {"dfloat", float_cons
, 'd'},
1134 {"tfloat", float_cons
, 'x'},
1136 {"slong", signed_cons
, 4},
1137 {"noopt", s_ignore
, 0},
1138 {"optim", s_ignore
, 0},
1139 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
1140 {"code16", set_code_flag
, CODE_16BIT
},
1141 {"code32", set_code_flag
, CODE_32BIT
},
1143 {"code64", set_code_flag
, CODE_64BIT
},
1145 {"intel_syntax", set_intel_syntax
, 1},
1146 {"att_syntax", set_intel_syntax
, 0},
1147 {"intel_mnemonic", set_intel_mnemonic
, 1},
1148 {"att_mnemonic", set_intel_mnemonic
, 0},
1149 {"allow_index_reg", set_allow_index_reg
, 1},
1150 {"disallow_index_reg", set_allow_index_reg
, 0},
1151 {"sse_check", set_check
, 0},
1152 {"operand_check", set_check
, 1},
1153 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1154 {"largecomm", handle_large_common
, 0},
1156 {"file", dwarf2_directive_file
, 0},
1157 {"loc", dwarf2_directive_loc
, 0},
1158 {"loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0},
1161 {"secrel32", pe_directive_secrel
, 0},
1166 /* For interface with expression (). */
1167 extern char *input_line_pointer
;
1169 /* Hash table for instruction mnemonic lookup. */
1170 static struct hash_control
*op_hash
;
1172 /* Hash table for register lookup. */
1173 static struct hash_control
*reg_hash
;
1175 /* Various efficient no-op patterns for aligning code labels.
1176 Note: Don't try to assemble the instructions in the comments.
1177 0L and 0w are not legal. */
1178 static const unsigned char f32_1
[] =
1180 static const unsigned char f32_2
[] =
1181 {0x66,0x90}; /* xchg %ax,%ax */
1182 static const unsigned char f32_3
[] =
1183 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1184 static const unsigned char f32_4
[] =
1185 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1186 static const unsigned char f32_6
[] =
1187 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1188 static const unsigned char f32_7
[] =
1189 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1190 static const unsigned char f16_3
[] =
1191 {0x8d,0x74,0x00}; /* lea 0(%si),%si */
1192 static const unsigned char f16_4
[] =
1193 {0x8d,0xb4,0x00,0x00}; /* lea 0W(%si),%si */
1194 static const unsigned char jump_disp8
[] =
1195 {0xeb}; /* jmp disp8 */
1196 static const unsigned char jump32_disp32
[] =
1197 {0xe9}; /* jmp disp32 */
1198 static const unsigned char jump16_disp32
[] =
1199 {0x66,0xe9}; /* jmp disp32 */
1200 /* 32-bit NOPs patterns. */
1201 static const unsigned char *const f32_patt
[] = {
1202 f32_1
, f32_2
, f32_3
, f32_4
, NULL
, f32_6
, f32_7
1204 /* 16-bit NOPs patterns. */
1205 static const unsigned char *const f16_patt
[] = {
1206 f32_1
, f32_2
, f16_3
, f16_4
1208 /* nopl (%[re]ax) */
1209 static const unsigned char alt_3
[] =
1211 /* nopl 0(%[re]ax) */
1212 static const unsigned char alt_4
[] =
1213 {0x0f,0x1f,0x40,0x00};
1214 /* nopl 0(%[re]ax,%[re]ax,1) */
1215 static const unsigned char alt_5
[] =
1216 {0x0f,0x1f,0x44,0x00,0x00};
1217 /* nopw 0(%[re]ax,%[re]ax,1) */
1218 static const unsigned char alt_6
[] =
1219 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1220 /* nopl 0L(%[re]ax) */
1221 static const unsigned char alt_7
[] =
1222 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1223 /* nopl 0L(%[re]ax,%[re]ax,1) */
1224 static const unsigned char alt_8
[] =
1225 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1226 /* nopw 0L(%[re]ax,%[re]ax,1) */
1227 static const unsigned char alt_9
[] =
1228 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1229 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1230 static const unsigned char alt_10
[] =
1231 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1232 /* data16 nopw %cs:0L(%eax,%eax,1) */
1233 static const unsigned char alt_11
[] =
1234 {0x66,0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1235 /* 32-bit and 64-bit NOPs patterns. */
1236 static const unsigned char *const alt_patt
[] = {
1237 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
1238 alt_9
, alt_10
, alt_11
1241 /* Genenerate COUNT bytes of NOPs to WHERE from PATT with the maximum
1242 size of a single NOP instruction MAX_SINGLE_NOP_SIZE. */
1245 i386_output_nops (char *where
, const unsigned char *const *patt
,
1246 int count
, int max_single_nop_size
)
1249 /* Place the longer NOP first. */
1252 const unsigned char *nops
= patt
[max_single_nop_size
- 1];
1254 /* Use the smaller one if the requsted one isn't available. */
1257 max_single_nop_size
--;
1258 nops
= patt
[max_single_nop_size
- 1];
1261 last
= count
% max_single_nop_size
;
1264 for (offset
= 0; offset
< count
; offset
+= max_single_nop_size
)
1265 memcpy (where
+ offset
, nops
, max_single_nop_size
);
1269 nops
= patt
[last
- 1];
1272 /* Use the smaller one plus one-byte NOP if the needed one
1275 nops
= patt
[last
- 1];
1276 memcpy (where
+ offset
, nops
, last
);
1277 where
[offset
+ last
] = *patt
[0];
1280 memcpy (where
+ offset
, nops
, last
);
1285 fits_in_imm7 (offsetT num
)
1287 return (num
& 0x7f) == num
;
1291 fits_in_imm31 (offsetT num
)
1293 return (num
& 0x7fffffff) == num
;
1296 /* Genenerate COUNT bytes of NOPs to WHERE with the maximum size of a
1297 single NOP instruction LIMIT. */
1300 i386_generate_nops (fragS
*fragP
, char *where
, offsetT count
, int limit
)
1302 const unsigned char *const *patt
= NULL
;
1303 int max_single_nop_size
;
1304 /* Maximum number of NOPs before switching to jump over NOPs. */
1305 int max_number_of_nops
;
1307 switch (fragP
->fr_type
)
1316 /* We need to decide which NOP sequence to use for 32bit and
1317 64bit. When -mtune= is used:
1319 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1320 PROCESSOR_GENERIC32, f32_patt will be used.
1321 2. For the rest, alt_patt will be used.
1323 When -mtune= isn't used, alt_patt will be used if
1324 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
1327 When -march= or .arch is used, we can't use anything beyond
1328 cpu_arch_isa_flags. */
1330 if (flag_code
== CODE_16BIT
)
1333 max_single_nop_size
= sizeof (f16_patt
) / sizeof (f16_patt
[0]);
1334 /* Limit number of NOPs to 2 in 16-bit mode. */
1335 max_number_of_nops
= 2;
1339 if (fragP
->tc_frag_data
.isa
== PROCESSOR_UNKNOWN
)
1341 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1342 switch (cpu_arch_tune
)
1344 case PROCESSOR_UNKNOWN
:
1345 /* We use cpu_arch_isa_flags to check if we SHOULD
1346 optimize with nops. */
1347 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1352 case PROCESSOR_PENTIUM4
:
1353 case PROCESSOR_NOCONA
:
1354 case PROCESSOR_CORE
:
1355 case PROCESSOR_CORE2
:
1356 case PROCESSOR_COREI7
:
1357 case PROCESSOR_L1OM
:
1358 case PROCESSOR_K1OM
:
1359 case PROCESSOR_GENERIC64
:
1361 case PROCESSOR_ATHLON
:
1363 case PROCESSOR_AMDFAM10
:
1365 case PROCESSOR_ZNVER
:
1369 case PROCESSOR_I386
:
1370 case PROCESSOR_I486
:
1371 case PROCESSOR_PENTIUM
:
1372 case PROCESSOR_PENTIUMPRO
:
1373 case PROCESSOR_IAMCU
:
1374 case PROCESSOR_GENERIC32
:
1381 switch (fragP
->tc_frag_data
.tune
)
1383 case PROCESSOR_UNKNOWN
:
1384 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1385 PROCESSOR_UNKNOWN. */
1389 case PROCESSOR_I386
:
1390 case PROCESSOR_I486
:
1391 case PROCESSOR_PENTIUM
:
1392 case PROCESSOR_IAMCU
:
1394 case PROCESSOR_ATHLON
:
1396 case PROCESSOR_AMDFAM10
:
1398 case PROCESSOR_ZNVER
:
1400 case PROCESSOR_GENERIC32
:
1401 /* We use cpu_arch_isa_flags to check if we CAN optimize
1403 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1408 case PROCESSOR_PENTIUMPRO
:
1409 case PROCESSOR_PENTIUM4
:
1410 case PROCESSOR_NOCONA
:
1411 case PROCESSOR_CORE
:
1412 case PROCESSOR_CORE2
:
1413 case PROCESSOR_COREI7
:
1414 case PROCESSOR_L1OM
:
1415 case PROCESSOR_K1OM
:
1416 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1421 case PROCESSOR_GENERIC64
:
1427 if (patt
== f32_patt
)
1429 max_single_nop_size
= sizeof (f32_patt
) / sizeof (f32_patt
[0]);
1430 /* Limit number of NOPs to 2 for older processors. */
1431 max_number_of_nops
= 2;
1435 max_single_nop_size
= sizeof (alt_patt
) / sizeof (alt_patt
[0]);
1436 /* Limit number of NOPs to 7 for newer processors. */
1437 max_number_of_nops
= 7;
1442 limit
= max_single_nop_size
;
1444 if (fragP
->fr_type
== rs_fill_nop
)
1446 /* Output NOPs for .nop directive. */
1447 if (limit
> max_single_nop_size
)
1449 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
1450 _("invalid single nop size: %d "
1451 "(expect within [0, %d])"),
1452 limit
, max_single_nop_size
);
1457 fragP
->fr_var
= count
;
1459 if ((count
/ max_single_nop_size
) > max_number_of_nops
)
1461 /* Generate jump over NOPs. */
1462 offsetT disp
= count
- 2;
1463 if (fits_in_imm7 (disp
))
1465 /* Use "jmp disp8" if possible. */
1467 where
[0] = jump_disp8
[0];
1473 unsigned int size_of_jump
;
1475 if (flag_code
== CODE_16BIT
)
1477 where
[0] = jump16_disp32
[0];
1478 where
[1] = jump16_disp32
[1];
1483 where
[0] = jump32_disp32
[0];
1487 count
-= size_of_jump
+ 4;
1488 if (!fits_in_imm31 (count
))
1490 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
1491 _("jump over nop padding out of range"));
1495 md_number_to_chars (where
+ size_of_jump
, count
, 4);
1496 where
+= size_of_jump
+ 4;
1500 /* Generate multiple NOPs. */
1501 i386_output_nops (where
, patt
, count
, limit
);
1505 operand_type_all_zero (const union i386_operand_type
*x
)
1507 switch (ARRAY_SIZE(x
->array
))
1518 return !x
->array
[0];
1525 operand_type_set (union i386_operand_type
*x
, unsigned int v
)
1527 switch (ARRAY_SIZE(x
->array
))
1545 operand_type_equal (const union i386_operand_type
*x
,
1546 const union i386_operand_type
*y
)
1548 switch (ARRAY_SIZE(x
->array
))
1551 if (x
->array
[2] != y
->array
[2])
1555 if (x
->array
[1] != y
->array
[1])
1559 return x
->array
[0] == y
->array
[0];
1567 cpu_flags_all_zero (const union i386_cpu_flags
*x
)
1569 switch (ARRAY_SIZE(x
->array
))
1584 return !x
->array
[0];
1591 cpu_flags_equal (const union i386_cpu_flags
*x
,
1592 const union i386_cpu_flags
*y
)
1594 switch (ARRAY_SIZE(x
->array
))
1597 if (x
->array
[3] != y
->array
[3])
1601 if (x
->array
[2] != y
->array
[2])
1605 if (x
->array
[1] != y
->array
[1])
1609 return x
->array
[0] == y
->array
[0];
1617 cpu_flags_check_cpu64 (i386_cpu_flags f
)
1619 return !((flag_code
== CODE_64BIT
&& f
.bitfield
.cpuno64
)
1620 || (flag_code
!= CODE_64BIT
&& f
.bitfield
.cpu64
));
1623 static INLINE i386_cpu_flags
1624 cpu_flags_and (i386_cpu_flags x
, i386_cpu_flags y
)
1626 switch (ARRAY_SIZE (x
.array
))
1629 x
.array
[3] &= y
.array
[3];
1632 x
.array
[2] &= y
.array
[2];
1635 x
.array
[1] &= y
.array
[1];
1638 x
.array
[0] &= y
.array
[0];
1646 static INLINE i386_cpu_flags
1647 cpu_flags_or (i386_cpu_flags x
, i386_cpu_flags y
)
1649 switch (ARRAY_SIZE (x
.array
))
1652 x
.array
[3] |= y
.array
[3];
1655 x
.array
[2] |= y
.array
[2];
1658 x
.array
[1] |= y
.array
[1];
1661 x
.array
[0] |= y
.array
[0];
1669 static INLINE i386_cpu_flags
1670 cpu_flags_and_not (i386_cpu_flags x
, i386_cpu_flags y
)
1672 switch (ARRAY_SIZE (x
.array
))
1675 x
.array
[3] &= ~y
.array
[3];
1678 x
.array
[2] &= ~y
.array
[2];
1681 x
.array
[1] &= ~y
.array
[1];
1684 x
.array
[0] &= ~y
.array
[0];
1692 #define CPU_FLAGS_ARCH_MATCH 0x1
1693 #define CPU_FLAGS_64BIT_MATCH 0x2
1695 #define CPU_FLAGS_PERFECT_MATCH \
1696 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_64BIT_MATCH)
1698 /* Return CPU flags match bits. */
1701 cpu_flags_match (const insn_template
*t
)
1703 i386_cpu_flags x
= t
->cpu_flags
;
1704 int match
= cpu_flags_check_cpu64 (x
) ? CPU_FLAGS_64BIT_MATCH
: 0;
1706 x
.bitfield
.cpu64
= 0;
1707 x
.bitfield
.cpuno64
= 0;
1709 if (cpu_flags_all_zero (&x
))
1711 /* This instruction is available on all archs. */
1712 match
|= CPU_FLAGS_ARCH_MATCH
;
1716 /* This instruction is available only on some archs. */
1717 i386_cpu_flags cpu
= cpu_arch_flags
;
1719 /* AVX512VL is no standalone feature - match it and then strip it. */
1720 if (x
.bitfield
.cpuavx512vl
&& !cpu
.bitfield
.cpuavx512vl
)
1722 x
.bitfield
.cpuavx512vl
= 0;
1724 cpu
= cpu_flags_and (x
, cpu
);
1725 if (!cpu_flags_all_zero (&cpu
))
1727 if (x
.bitfield
.cpuavx
)
1729 /* We need to check a few extra flags with AVX. */
1730 if (cpu
.bitfield
.cpuavx
1731 && (!t
->opcode_modifier
.sse2avx
|| sse2avx
)
1732 && (!x
.bitfield
.cpuaes
|| cpu
.bitfield
.cpuaes
)
1733 && (!x
.bitfield
.cpugfni
|| cpu
.bitfield
.cpugfni
)
1734 && (!x
.bitfield
.cpupclmul
|| cpu
.bitfield
.cpupclmul
))
1735 match
|= CPU_FLAGS_ARCH_MATCH
;
1737 else if (x
.bitfield
.cpuavx512f
)
1739 /* We need to check a few extra flags with AVX512F. */
1740 if (cpu
.bitfield
.cpuavx512f
1741 && (!x
.bitfield
.cpugfni
|| cpu
.bitfield
.cpugfni
)
1742 && (!x
.bitfield
.cpuvaes
|| cpu
.bitfield
.cpuvaes
)
1743 && (!x
.bitfield
.cpuvpclmulqdq
|| cpu
.bitfield
.cpuvpclmulqdq
))
1744 match
|= CPU_FLAGS_ARCH_MATCH
;
1747 match
|= CPU_FLAGS_ARCH_MATCH
;
1753 static INLINE i386_operand_type
1754 operand_type_and (i386_operand_type x
, i386_operand_type y
)
1756 switch (ARRAY_SIZE (x
.array
))
1759 x
.array
[2] &= y
.array
[2];
1762 x
.array
[1] &= y
.array
[1];
1765 x
.array
[0] &= y
.array
[0];
1773 static INLINE i386_operand_type
1774 operand_type_and_not (i386_operand_type x
, i386_operand_type y
)
1776 switch (ARRAY_SIZE (x
.array
))
1779 x
.array
[2] &= ~y
.array
[2];
1782 x
.array
[1] &= ~y
.array
[1];
1785 x
.array
[0] &= ~y
.array
[0];
1793 static INLINE i386_operand_type
1794 operand_type_or (i386_operand_type x
, i386_operand_type y
)
1796 switch (ARRAY_SIZE (x
.array
))
1799 x
.array
[2] |= y
.array
[2];
1802 x
.array
[1] |= y
.array
[1];
1805 x
.array
[0] |= y
.array
[0];
1813 static INLINE i386_operand_type
1814 operand_type_xor (i386_operand_type x
, i386_operand_type y
)
1816 switch (ARRAY_SIZE (x
.array
))
1819 x
.array
[2] ^= y
.array
[2];
1822 x
.array
[1] ^= y
.array
[1];
1825 x
.array
[0] ^= y
.array
[0];
1833 static const i386_operand_type acc32
= OPERAND_TYPE_ACC32
;
1834 static const i386_operand_type acc64
= OPERAND_TYPE_ACC64
;
1835 static const i386_operand_type disp16
= OPERAND_TYPE_DISP16
;
1836 static const i386_operand_type disp32
= OPERAND_TYPE_DISP32
;
1837 static const i386_operand_type disp32s
= OPERAND_TYPE_DISP32S
;
1838 static const i386_operand_type disp16_32
= OPERAND_TYPE_DISP16_32
;
1839 static const i386_operand_type anydisp
1840 = OPERAND_TYPE_ANYDISP
;
1841 static const i386_operand_type regxmm
= OPERAND_TYPE_REGXMM
;
1842 static const i386_operand_type regmask
= OPERAND_TYPE_REGMASK
;
1843 static const i386_operand_type imm8
= OPERAND_TYPE_IMM8
;
1844 static const i386_operand_type imm8s
= OPERAND_TYPE_IMM8S
;
1845 static const i386_operand_type imm16
= OPERAND_TYPE_IMM16
;
1846 static const i386_operand_type imm32
= OPERAND_TYPE_IMM32
;
1847 static const i386_operand_type imm32s
= OPERAND_TYPE_IMM32S
;
1848 static const i386_operand_type imm64
= OPERAND_TYPE_IMM64
;
1849 static const i386_operand_type imm16_32
= OPERAND_TYPE_IMM16_32
;
1850 static const i386_operand_type imm16_32s
= OPERAND_TYPE_IMM16_32S
;
1851 static const i386_operand_type imm16_32_32s
= OPERAND_TYPE_IMM16_32_32S
;
1852 static const i386_operand_type vec_imm4
= OPERAND_TYPE_VEC_IMM4
;
1863 operand_type_check (i386_operand_type t
, enum operand_type c
)
1868 return t
.bitfield
.reg
;
1871 return (t
.bitfield
.imm8
1875 || t
.bitfield
.imm32s
1876 || t
.bitfield
.imm64
);
1879 return (t
.bitfield
.disp8
1880 || t
.bitfield
.disp16
1881 || t
.bitfield
.disp32
1882 || t
.bitfield
.disp32s
1883 || t
.bitfield
.disp64
);
1886 return (t
.bitfield
.disp8
1887 || t
.bitfield
.disp16
1888 || t
.bitfield
.disp32
1889 || t
.bitfield
.disp32s
1890 || t
.bitfield
.disp64
1891 || t
.bitfield
.baseindex
);
1900 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit/80bit on
1901 operand J for instruction template T. */
1904 match_reg_size (const insn_template
*t
, unsigned int j
)
1906 return !((i
.types
[j
].bitfield
.byte
1907 && !t
->operand_types
[j
].bitfield
.byte
)
1908 || (i
.types
[j
].bitfield
.word
1909 && !t
->operand_types
[j
].bitfield
.word
)
1910 || (i
.types
[j
].bitfield
.dword
1911 && !t
->operand_types
[j
].bitfield
.dword
)
1912 || (i
.types
[j
].bitfield
.qword
1913 && !t
->operand_types
[j
].bitfield
.qword
)
1914 || (i
.types
[j
].bitfield
.tbyte
1915 && !t
->operand_types
[j
].bitfield
.tbyte
));
1918 /* Return 1 if there is no conflict in SIMD register on
1919 operand J for instruction template T. */
1922 match_simd_size (const insn_template
*t
, unsigned int j
)
1924 return !((i
.types
[j
].bitfield
.xmmword
1925 && !t
->operand_types
[j
].bitfield
.xmmword
)
1926 || (i
.types
[j
].bitfield
.ymmword
1927 && !t
->operand_types
[j
].bitfield
.ymmword
)
1928 || (i
.types
[j
].bitfield
.zmmword
1929 && !t
->operand_types
[j
].bitfield
.zmmword
));
1932 /* Return 1 if there is no conflict in any size on operand J for
1933 instruction template T. */
1936 match_mem_size (const insn_template
*t
, unsigned int j
)
1938 return (match_reg_size (t
, j
)
1939 && !((i
.types
[j
].bitfield
.unspecified
1941 && !t
->operand_types
[j
].bitfield
.unspecified
)
1942 || (i
.types
[j
].bitfield
.fword
1943 && !t
->operand_types
[j
].bitfield
.fword
)
1944 /* For scalar opcode templates to allow register and memory
1945 operands at the same time, some special casing is needed
1946 here. Also for v{,p}broadcast*, {,v}pmov{s,z}*, and
1947 down-conversion vpmov*. */
1948 || ((t
->operand_types
[j
].bitfield
.regsimd
1949 && !t
->opcode_modifier
.broadcast
1950 && (t
->operand_types
[j
].bitfield
.byte
1951 || t
->operand_types
[j
].bitfield
.word
1952 || t
->operand_types
[j
].bitfield
.dword
1953 || t
->operand_types
[j
].bitfield
.qword
))
1954 ? (i
.types
[j
].bitfield
.xmmword
1955 || i
.types
[j
].bitfield
.ymmword
1956 || i
.types
[j
].bitfield
.zmmword
)
1957 : !match_simd_size(t
, j
))));
1960 /* Return 1 if there is no size conflict on any operands for
1961 instruction template T. */
1964 operand_size_match (const insn_template
*t
)
1969 /* Don't check jump instructions. */
1970 if (t
->opcode_modifier
.jump
1971 || t
->opcode_modifier
.jumpbyte
1972 || t
->opcode_modifier
.jumpdword
1973 || t
->opcode_modifier
.jumpintersegment
)
1976 /* Check memory and accumulator operand size. */
1977 for (j
= 0; j
< i
.operands
; j
++)
1979 if (!i
.types
[j
].bitfield
.reg
&& !i
.types
[j
].bitfield
.regsimd
1980 && t
->operand_types
[j
].bitfield
.anysize
)
1983 if (t
->operand_types
[j
].bitfield
.reg
1984 && !match_reg_size (t
, j
))
1990 if (t
->operand_types
[j
].bitfield
.regsimd
1991 && !match_simd_size (t
, j
))
1997 if (t
->operand_types
[j
].bitfield
.acc
1998 && (!match_reg_size (t
, j
) || !match_simd_size (t
, j
)))
2004 if (i
.types
[j
].bitfield
.mem
&& !match_mem_size (t
, j
))
2013 else if (!t
->opcode_modifier
.d
)
2016 i
.error
= operand_size_mismatch
;
2020 /* Check reverse. */
2021 gas_assert (i
.operands
== 2);
2024 for (j
= 0; j
< 2; j
++)
2026 if ((t
->operand_types
[j
].bitfield
.reg
2027 || t
->operand_types
[j
].bitfield
.acc
)
2028 && !match_reg_size (t
, j
? 0 : 1))
2031 if (i
.types
[j
].bitfield
.mem
2032 && !match_mem_size (t
, j
? 0 : 1))
2040 operand_type_match (i386_operand_type overlap
,
2041 i386_operand_type given
)
2043 i386_operand_type temp
= overlap
;
2045 temp
.bitfield
.jumpabsolute
= 0;
2046 temp
.bitfield
.unspecified
= 0;
2047 temp
.bitfield
.byte
= 0;
2048 temp
.bitfield
.word
= 0;
2049 temp
.bitfield
.dword
= 0;
2050 temp
.bitfield
.fword
= 0;
2051 temp
.bitfield
.qword
= 0;
2052 temp
.bitfield
.tbyte
= 0;
2053 temp
.bitfield
.xmmword
= 0;
2054 temp
.bitfield
.ymmword
= 0;
2055 temp
.bitfield
.zmmword
= 0;
2056 if (operand_type_all_zero (&temp
))
2059 if (given
.bitfield
.baseindex
== overlap
.bitfield
.baseindex
2060 && given
.bitfield
.jumpabsolute
== overlap
.bitfield
.jumpabsolute
)
2064 i
.error
= operand_type_mismatch
;
2068 /* If given types g0 and g1 are registers they must be of the same type
2069 unless the expected operand type register overlap is null.
2070 Memory operand size of certain SIMD instructions is also being checked
2074 operand_type_register_match (i386_operand_type g0
,
2075 i386_operand_type t0
,
2076 i386_operand_type g1
,
2077 i386_operand_type t1
)
2079 if (!g0
.bitfield
.reg
2080 && !g0
.bitfield
.regsimd
2081 && (!operand_type_check (g0
, anymem
)
2082 || g0
.bitfield
.unspecified
2083 || !t0
.bitfield
.regsimd
))
2086 if (!g1
.bitfield
.reg
2087 && !g1
.bitfield
.regsimd
2088 && (!operand_type_check (g1
, anymem
)
2089 || g1
.bitfield
.unspecified
2090 || !t1
.bitfield
.regsimd
))
2093 if (g0
.bitfield
.byte
== g1
.bitfield
.byte
2094 && g0
.bitfield
.word
== g1
.bitfield
.word
2095 && g0
.bitfield
.dword
== g1
.bitfield
.dword
2096 && g0
.bitfield
.qword
== g1
.bitfield
.qword
2097 && g0
.bitfield
.xmmword
== g1
.bitfield
.xmmword
2098 && g0
.bitfield
.ymmword
== g1
.bitfield
.ymmword
2099 && g0
.bitfield
.zmmword
== g1
.bitfield
.zmmword
)
2102 if (!(t0
.bitfield
.byte
& t1
.bitfield
.byte
)
2103 && !(t0
.bitfield
.word
& t1
.bitfield
.word
)
2104 && !(t0
.bitfield
.dword
& t1
.bitfield
.dword
)
2105 && !(t0
.bitfield
.qword
& t1
.bitfield
.qword
)
2106 && !(t0
.bitfield
.xmmword
& t1
.bitfield
.xmmword
)
2107 && !(t0
.bitfield
.ymmword
& t1
.bitfield
.ymmword
)
2108 && !(t0
.bitfield
.zmmword
& t1
.bitfield
.zmmword
))
2111 i
.error
= register_type_mismatch
;
2116 static INLINE
unsigned int
2117 register_number (const reg_entry
*r
)
2119 unsigned int nr
= r
->reg_num
;
2121 if (r
->reg_flags
& RegRex
)
2124 if (r
->reg_flags
& RegVRex
)
2130 static INLINE
unsigned int
2131 mode_from_disp_size (i386_operand_type t
)
2133 if (t
.bitfield
.disp8
)
2135 else if (t
.bitfield
.disp16
2136 || t
.bitfield
.disp32
2137 || t
.bitfield
.disp32s
)
2144 fits_in_signed_byte (addressT num
)
2146 return num
+ 0x80 <= 0xff;
2150 fits_in_unsigned_byte (addressT num
)
2156 fits_in_unsigned_word (addressT num
)
2158 return num
<= 0xffff;
2162 fits_in_signed_word (addressT num
)
2164 return num
+ 0x8000 <= 0xffff;
2168 fits_in_signed_long (addressT num ATTRIBUTE_UNUSED
)
2173 return num
+ 0x80000000 <= 0xffffffff;
2175 } /* fits_in_signed_long() */
2178 fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED
)
2183 return num
<= 0xffffffff;
2185 } /* fits_in_unsigned_long() */
2188 fits_in_disp8 (offsetT num
)
2190 int shift
= i
.memshift
;
2196 mask
= (1 << shift
) - 1;
2198 /* Return 0 if NUM isn't properly aligned. */
2202 /* Check if NUM will fit in 8bit after shift. */
2203 return fits_in_signed_byte (num
>> shift
);
2207 fits_in_imm4 (offsetT num
)
2209 return (num
& 0xf) == num
;
2212 static i386_operand_type
2213 smallest_imm_type (offsetT num
)
2215 i386_operand_type t
;
2217 operand_type_set (&t
, 0);
2218 t
.bitfield
.imm64
= 1;
2220 if (cpu_arch_tune
!= PROCESSOR_I486
&& num
== 1)
2222 /* This code is disabled on the 486 because all the Imm1 forms
2223 in the opcode table are slower on the i486. They're the
2224 versions with the implicitly specified single-position
2225 displacement, which has another syntax if you really want to
2227 t
.bitfield
.imm1
= 1;
2228 t
.bitfield
.imm8
= 1;
2229 t
.bitfield
.imm8s
= 1;
2230 t
.bitfield
.imm16
= 1;
2231 t
.bitfield
.imm32
= 1;
2232 t
.bitfield
.imm32s
= 1;
2234 else if (fits_in_signed_byte (num
))
2236 t
.bitfield
.imm8
= 1;
2237 t
.bitfield
.imm8s
= 1;
2238 t
.bitfield
.imm16
= 1;
2239 t
.bitfield
.imm32
= 1;
2240 t
.bitfield
.imm32s
= 1;
2242 else if (fits_in_unsigned_byte (num
))
2244 t
.bitfield
.imm8
= 1;
2245 t
.bitfield
.imm16
= 1;
2246 t
.bitfield
.imm32
= 1;
2247 t
.bitfield
.imm32s
= 1;
2249 else if (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
2251 t
.bitfield
.imm16
= 1;
2252 t
.bitfield
.imm32
= 1;
2253 t
.bitfield
.imm32s
= 1;
2255 else if (fits_in_signed_long (num
))
2257 t
.bitfield
.imm32
= 1;
2258 t
.bitfield
.imm32s
= 1;
2260 else if (fits_in_unsigned_long (num
))
2261 t
.bitfield
.imm32
= 1;
2267 offset_in_range (offsetT val
, int size
)
2273 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
2274 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
2275 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
2277 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
2283 /* If BFD64, sign extend val for 32bit address mode. */
2284 if (flag_code
!= CODE_64BIT
2285 || i
.prefix
[ADDR_PREFIX
])
2286 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
2287 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
2290 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
2292 char buf1
[40], buf2
[40];
2294 sprint_value (buf1
, val
);
2295 sprint_value (buf2
, val
& mask
);
2296 as_warn (_("%s shortened to %s"), buf1
, buf2
);
2311 a. PREFIX_EXIST if attempting to add a prefix where one from the
2312 same class already exists.
2313 b. PREFIX_LOCK if lock prefix is added.
2314 c. PREFIX_REP if rep/repne prefix is added.
2315 d. PREFIX_DS if ds prefix is added.
2316 e. PREFIX_OTHER if other prefix is added.
2319 static enum PREFIX_GROUP
2320 add_prefix (unsigned int prefix
)
2322 enum PREFIX_GROUP ret
= PREFIX_OTHER
;
2325 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
2326 && flag_code
== CODE_64BIT
)
2328 if ((i
.prefix
[REX_PREFIX
] & prefix
& REX_W
)
2329 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_R
)
2330 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_X
)
2331 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_B
))
2342 case DS_PREFIX_OPCODE
:
2345 case CS_PREFIX_OPCODE
:
2346 case ES_PREFIX_OPCODE
:
2347 case FS_PREFIX_OPCODE
:
2348 case GS_PREFIX_OPCODE
:
2349 case SS_PREFIX_OPCODE
:
2353 case REPNE_PREFIX_OPCODE
:
2354 case REPE_PREFIX_OPCODE
:
2359 case LOCK_PREFIX_OPCODE
:
2368 case ADDR_PREFIX_OPCODE
:
2372 case DATA_PREFIX_OPCODE
:
2376 if (i
.prefix
[q
] != 0)
2384 i
.prefix
[q
] |= prefix
;
2387 as_bad (_("same type of prefix used twice"));
2393 update_code_flag (int value
, int check
)
2395 PRINTF_LIKE ((*as_error
));
2397 flag_code
= (enum flag_code
) value
;
2398 if (flag_code
== CODE_64BIT
)
2400 cpu_arch_flags
.bitfield
.cpu64
= 1;
2401 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2405 cpu_arch_flags
.bitfield
.cpu64
= 0;
2406 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2408 if (value
== CODE_64BIT
&& !cpu_arch_flags
.bitfield
.cpulm
)
2411 as_error
= as_fatal
;
2414 (*as_error
) (_("64bit mode not supported on `%s'."),
2415 cpu_arch_name
? cpu_arch_name
: default_arch
);
2417 if (value
== CODE_32BIT
&& !cpu_arch_flags
.bitfield
.cpui386
)
2420 as_error
= as_fatal
;
2423 (*as_error
) (_("32bit mode not supported on `%s'."),
2424 cpu_arch_name
? cpu_arch_name
: default_arch
);
2426 stackop_size
= '\0';
2430 set_code_flag (int value
)
2432 update_code_flag (value
, 0);
2436 set_16bit_gcc_code_flag (int new_code_flag
)
2438 flag_code
= (enum flag_code
) new_code_flag
;
2439 if (flag_code
!= CODE_16BIT
)
2441 cpu_arch_flags
.bitfield
.cpu64
= 0;
2442 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2443 stackop_size
= LONG_MNEM_SUFFIX
;
2447 set_intel_syntax (int syntax_flag
)
2449 /* Find out if register prefixing is specified. */
2450 int ask_naked_reg
= 0;
2453 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2456 int e
= get_symbol_name (&string
);
2458 if (strcmp (string
, "prefix") == 0)
2460 else if (strcmp (string
, "noprefix") == 0)
2463 as_bad (_("bad argument to syntax directive."));
2464 (void) restore_line_pointer (e
);
2466 demand_empty_rest_of_line ();
2468 intel_syntax
= syntax_flag
;
2470 if (ask_naked_reg
== 0)
2471 allow_naked_reg
= (intel_syntax
2472 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
2474 allow_naked_reg
= (ask_naked_reg
< 0);
2476 expr_set_rank (O_full_ptr
, syntax_flag
? 10 : 0);
2478 identifier_chars
['%'] = intel_syntax
&& allow_naked_reg
? '%' : 0;
2479 identifier_chars
['$'] = intel_syntax
? '$' : 0;
2480 register_prefix
= allow_naked_reg
? "" : "%";
2484 set_intel_mnemonic (int mnemonic_flag
)
2486 intel_mnemonic
= mnemonic_flag
;
2490 set_allow_index_reg (int flag
)
2492 allow_index_reg
= flag
;
2496 set_check (int what
)
2498 enum check_kind
*kind
;
2503 kind
= &operand_check
;
2514 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2517 int e
= get_symbol_name (&string
);
2519 if (strcmp (string
, "none") == 0)
2521 else if (strcmp (string
, "warning") == 0)
2522 *kind
= check_warning
;
2523 else if (strcmp (string
, "error") == 0)
2524 *kind
= check_error
;
2526 as_bad (_("bad argument to %s_check directive."), str
);
2527 (void) restore_line_pointer (e
);
2530 as_bad (_("missing argument for %s_check directive"), str
);
2532 demand_empty_rest_of_line ();
2536 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED
,
2537 i386_cpu_flags new_flag ATTRIBUTE_UNUSED
)
2539 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2540 static const char *arch
;
2542 /* Intel LIOM is only supported on ELF. */
2548 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2549 use default_arch. */
2550 arch
= cpu_arch_name
;
2552 arch
= default_arch
;
2555 /* If we are targeting Intel MCU, we must enable it. */
2556 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_IAMCU
2557 || new_flag
.bitfield
.cpuiamcu
)
2560 /* If we are targeting Intel L1OM, we must enable it. */
2561 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_L1OM
2562 || new_flag
.bitfield
.cpul1om
)
2565 /* If we are targeting Intel K1OM, we must enable it. */
2566 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_K1OM
2567 || new_flag
.bitfield
.cpuk1om
)
2570 as_bad (_("`%s' is not supported on `%s'"), name
, arch
);
2575 set_cpu_arch (int dummy ATTRIBUTE_UNUSED
)
2579 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2582 int e
= get_symbol_name (&string
);
2584 i386_cpu_flags flags
;
2586 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
2588 if (strcmp (string
, cpu_arch
[j
].name
) == 0)
2590 check_cpu_arch_compatible (string
, cpu_arch
[j
].flags
);
2594 cpu_arch_name
= cpu_arch
[j
].name
;
2595 cpu_sub_arch_name
= NULL
;
2596 cpu_arch_flags
= cpu_arch
[j
].flags
;
2597 if (flag_code
== CODE_64BIT
)
2599 cpu_arch_flags
.bitfield
.cpu64
= 1;
2600 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2604 cpu_arch_flags
.bitfield
.cpu64
= 0;
2605 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2607 cpu_arch_isa
= cpu_arch
[j
].type
;
2608 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
2609 if (!cpu_arch_tune_set
)
2611 cpu_arch_tune
= cpu_arch_isa
;
2612 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
2617 flags
= cpu_flags_or (cpu_arch_flags
,
2620 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2622 if (cpu_sub_arch_name
)
2624 char *name
= cpu_sub_arch_name
;
2625 cpu_sub_arch_name
= concat (name
,
2627 (const char *) NULL
);
2631 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
2632 cpu_arch_flags
= flags
;
2633 cpu_arch_isa_flags
= flags
;
2637 = cpu_flags_or (cpu_arch_isa_flags
,
2639 (void) restore_line_pointer (e
);
2640 demand_empty_rest_of_line ();
2645 if (*string
== '.' && j
>= ARRAY_SIZE (cpu_arch
))
2647 /* Disable an ISA extension. */
2648 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
2649 if (strcmp (string
+ 1, cpu_noarch
[j
].name
) == 0)
2651 flags
= cpu_flags_and_not (cpu_arch_flags
,
2652 cpu_noarch
[j
].flags
);
2653 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2655 if (cpu_sub_arch_name
)
2657 char *name
= cpu_sub_arch_name
;
2658 cpu_sub_arch_name
= concat (name
, string
,
2659 (const char *) NULL
);
2663 cpu_sub_arch_name
= xstrdup (string
);
2664 cpu_arch_flags
= flags
;
2665 cpu_arch_isa_flags
= flags
;
2667 (void) restore_line_pointer (e
);
2668 demand_empty_rest_of_line ();
2672 j
= ARRAY_SIZE (cpu_arch
);
2675 if (j
>= ARRAY_SIZE (cpu_arch
))
2676 as_bad (_("no such architecture: `%s'"), string
);
2678 *input_line_pointer
= e
;
2681 as_bad (_("missing cpu architecture"));
2683 no_cond_jump_promotion
= 0;
2684 if (*input_line_pointer
== ','
2685 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
2690 ++input_line_pointer
;
2691 e
= get_symbol_name (&string
);
2693 if (strcmp (string
, "nojumps") == 0)
2694 no_cond_jump_promotion
= 1;
2695 else if (strcmp (string
, "jumps") == 0)
2698 as_bad (_("no such architecture modifier: `%s'"), string
);
2700 (void) restore_line_pointer (e
);
2703 demand_empty_rest_of_line ();
2706 enum bfd_architecture
2709 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2711 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2712 || flag_code
!= CODE_64BIT
)
2713 as_fatal (_("Intel L1OM is 64bit ELF only"));
2714 return bfd_arch_l1om
;
2716 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2718 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2719 || flag_code
!= CODE_64BIT
)
2720 as_fatal (_("Intel K1OM is 64bit ELF only"));
2721 return bfd_arch_k1om
;
2723 else if (cpu_arch_isa
== PROCESSOR_IAMCU
)
2725 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2726 || flag_code
== CODE_64BIT
)
2727 as_fatal (_("Intel MCU is 32bit ELF only"));
2728 return bfd_arch_iamcu
;
2731 return bfd_arch_i386
;
2737 if (!strncmp (default_arch
, "x86_64", 6))
2739 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2741 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2742 || default_arch
[6] != '\0')
2743 as_fatal (_("Intel L1OM is 64bit ELF only"));
2744 return bfd_mach_l1om
;
2746 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2748 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2749 || default_arch
[6] != '\0')
2750 as_fatal (_("Intel K1OM is 64bit ELF only"));
2751 return bfd_mach_k1om
;
2753 else if (default_arch
[6] == '\0')
2754 return bfd_mach_x86_64
;
2756 return bfd_mach_x64_32
;
2758 else if (!strcmp (default_arch
, "i386")
2759 || !strcmp (default_arch
, "iamcu"))
2761 if (cpu_arch_isa
== PROCESSOR_IAMCU
)
2763 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
2764 as_fatal (_("Intel MCU is 32bit ELF only"));
2765 return bfd_mach_i386_iamcu
;
2768 return bfd_mach_i386_i386
;
2771 as_fatal (_("unknown architecture"));
2777 const char *hash_err
;
2779 /* Support pseudo prefixes like {disp32}. */
2780 lex_type
['{'] = LEX_BEGIN_NAME
;
2782 /* Initialize op_hash hash table. */
2783 op_hash
= hash_new ();
2786 const insn_template
*optab
;
2787 templates
*core_optab
;
2789 /* Setup for loop. */
2791 core_optab
= XNEW (templates
);
2792 core_optab
->start
= optab
;
2797 if (optab
->name
== NULL
2798 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
2800 /* different name --> ship out current template list;
2801 add to hash table; & begin anew. */
2802 core_optab
->end
= optab
;
2803 hash_err
= hash_insert (op_hash
,
2805 (void *) core_optab
);
2808 as_fatal (_("can't hash %s: %s"),
2812 if (optab
->name
== NULL
)
2814 core_optab
= XNEW (templates
);
2815 core_optab
->start
= optab
;
2820 /* Initialize reg_hash hash table. */
2821 reg_hash
= hash_new ();
2823 const reg_entry
*regtab
;
2824 unsigned int regtab_size
= i386_regtab_size
;
2826 for (regtab
= i386_regtab
; regtab_size
--; regtab
++)
2828 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (void *) regtab
);
2830 as_fatal (_("can't hash %s: %s"),
2836 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
2841 for (c
= 0; c
< 256; c
++)
2846 mnemonic_chars
[c
] = c
;
2847 register_chars
[c
] = c
;
2848 operand_chars
[c
] = c
;
2850 else if (ISLOWER (c
))
2852 mnemonic_chars
[c
] = c
;
2853 register_chars
[c
] = c
;
2854 operand_chars
[c
] = c
;
2856 else if (ISUPPER (c
))
2858 mnemonic_chars
[c
] = TOLOWER (c
);
2859 register_chars
[c
] = mnemonic_chars
[c
];
2860 operand_chars
[c
] = c
;
2862 else if (c
== '{' || c
== '}')
2864 mnemonic_chars
[c
] = c
;
2865 operand_chars
[c
] = c
;
2868 if (ISALPHA (c
) || ISDIGIT (c
))
2869 identifier_chars
[c
] = c
;
2872 identifier_chars
[c
] = c
;
2873 operand_chars
[c
] = c
;
2878 identifier_chars
['@'] = '@';
2881 identifier_chars
['?'] = '?';
2882 operand_chars
['?'] = '?';
2884 digit_chars
['-'] = '-';
2885 mnemonic_chars
['_'] = '_';
2886 mnemonic_chars
['-'] = '-';
2887 mnemonic_chars
['.'] = '.';
2888 identifier_chars
['_'] = '_';
2889 identifier_chars
['.'] = '.';
2891 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
2892 operand_chars
[(unsigned char) *p
] = *p
;
2895 if (flag_code
== CODE_64BIT
)
2897 #if defined (OBJ_COFF) && defined (TE_PE)
2898 x86_dwarf2_return_column
= (OUTPUT_FLAVOR
== bfd_target_coff_flavour
2901 x86_dwarf2_return_column
= 16;
2903 x86_cie_data_alignment
= -8;
2907 x86_dwarf2_return_column
= 8;
2908 x86_cie_data_alignment
= -4;
2913 i386_print_statistics (FILE *file
)
2915 hash_print_statistics (file
, "i386 opcode", op_hash
);
2916 hash_print_statistics (file
, "i386 register", reg_hash
);
2921 /* Debugging routines for md_assemble. */
2922 static void pte (insn_template
*);
2923 static void pt (i386_operand_type
);
2924 static void pe (expressionS
*);
2925 static void ps (symbolS
*);
2928 pi (char *line
, i386_insn
*x
)
2932 fprintf (stdout
, "%s: template ", line
);
2934 fprintf (stdout
, " address: base %s index %s scale %x\n",
2935 x
->base_reg
? x
->base_reg
->reg_name
: "none",
2936 x
->index_reg
? x
->index_reg
->reg_name
: "none",
2937 x
->log2_scale_factor
);
2938 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
2939 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
2940 fprintf (stdout
, " sib: base %x index %x scale %x\n",
2941 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
2942 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
2943 (x
->rex
& REX_W
) != 0,
2944 (x
->rex
& REX_R
) != 0,
2945 (x
->rex
& REX_X
) != 0,
2946 (x
->rex
& REX_B
) != 0);
2947 for (j
= 0; j
< x
->operands
; j
++)
2949 fprintf (stdout
, " #%d: ", j
+ 1);
2951 fprintf (stdout
, "\n");
2952 if (x
->types
[j
].bitfield
.reg
2953 || x
->types
[j
].bitfield
.regmmx
2954 || x
->types
[j
].bitfield
.regsimd
2955 || x
->types
[j
].bitfield
.sreg2
2956 || x
->types
[j
].bitfield
.sreg3
2957 || x
->types
[j
].bitfield
.control
2958 || x
->types
[j
].bitfield
.debug
2959 || x
->types
[j
].bitfield
.test
)
2960 fprintf (stdout
, "%s\n", x
->op
[j
].regs
->reg_name
);
2961 if (operand_type_check (x
->types
[j
], imm
))
2963 if (operand_type_check (x
->types
[j
], disp
))
2964 pe (x
->op
[j
].disps
);
2969 pte (insn_template
*t
)
2972 fprintf (stdout
, " %d operands ", t
->operands
);
2973 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
2974 if (t
->extension_opcode
!= None
)
2975 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
2976 if (t
->opcode_modifier
.d
)
2977 fprintf (stdout
, "D");
2978 if (t
->opcode_modifier
.w
)
2979 fprintf (stdout
, "W");
2980 fprintf (stdout
, "\n");
2981 for (j
= 0; j
< t
->operands
; j
++)
2983 fprintf (stdout
, " #%d type ", j
+ 1);
2984 pt (t
->operand_types
[j
]);
2985 fprintf (stdout
, "\n");
2992 fprintf (stdout
, " operation %d\n", e
->X_op
);
2993 fprintf (stdout
, " add_number %ld (%lx)\n",
2994 (long) e
->X_add_number
, (long) e
->X_add_number
);
2995 if (e
->X_add_symbol
)
2997 fprintf (stdout
, " add_symbol ");
2998 ps (e
->X_add_symbol
);
2999 fprintf (stdout
, "\n");
3003 fprintf (stdout
, " op_symbol ");
3004 ps (e
->X_op_symbol
);
3005 fprintf (stdout
, "\n");
3012 fprintf (stdout
, "%s type %s%s",
3014 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
3015 segment_name (S_GET_SEGMENT (s
)));
3018 static struct type_name
3020 i386_operand_type mask
;
3023 const type_names
[] =
3025 { OPERAND_TYPE_REG8
, "r8" },
3026 { OPERAND_TYPE_REG16
, "r16" },
3027 { OPERAND_TYPE_REG32
, "r32" },
3028 { OPERAND_TYPE_REG64
, "r64" },
3029 { OPERAND_TYPE_IMM8
, "i8" },
3030 { OPERAND_TYPE_IMM8
, "i8s" },
3031 { OPERAND_TYPE_IMM16
, "i16" },
3032 { OPERAND_TYPE_IMM32
, "i32" },
3033 { OPERAND_TYPE_IMM32S
, "i32s" },
3034 { OPERAND_TYPE_IMM64
, "i64" },
3035 { OPERAND_TYPE_IMM1
, "i1" },
3036 { OPERAND_TYPE_BASEINDEX
, "BaseIndex" },
3037 { OPERAND_TYPE_DISP8
, "d8" },
3038 { OPERAND_TYPE_DISP16
, "d16" },
3039 { OPERAND_TYPE_DISP32
, "d32" },
3040 { OPERAND_TYPE_DISP32S
, "d32s" },
3041 { OPERAND_TYPE_DISP64
, "d64" },
3042 { OPERAND_TYPE_INOUTPORTREG
, "InOutPortReg" },
3043 { OPERAND_TYPE_SHIFTCOUNT
, "ShiftCount" },
3044 { OPERAND_TYPE_CONTROL
, "control reg" },
3045 { OPERAND_TYPE_TEST
, "test reg" },
3046 { OPERAND_TYPE_DEBUG
, "debug reg" },
3047 { OPERAND_TYPE_FLOATREG
, "FReg" },
3048 { OPERAND_TYPE_FLOATACC
, "FAcc" },
3049 { OPERAND_TYPE_SREG2
, "SReg2" },
3050 { OPERAND_TYPE_SREG3
, "SReg3" },
3051 { OPERAND_TYPE_ACC
, "Acc" },
3052 { OPERAND_TYPE_JUMPABSOLUTE
, "Jump Absolute" },
3053 { OPERAND_TYPE_REGMMX
, "rMMX" },
3054 { OPERAND_TYPE_REGXMM
, "rXMM" },
3055 { OPERAND_TYPE_REGYMM
, "rYMM" },
3056 { OPERAND_TYPE_REGZMM
, "rZMM" },
3057 { OPERAND_TYPE_REGMASK
, "Mask reg" },
3058 { OPERAND_TYPE_ESSEG
, "es" },
3062 pt (i386_operand_type t
)
3065 i386_operand_type a
;
3067 for (j
= 0; j
< ARRAY_SIZE (type_names
); j
++)
3069 a
= operand_type_and (t
, type_names
[j
].mask
);
3070 if (!operand_type_all_zero (&a
))
3071 fprintf (stdout
, "%s, ", type_names
[j
].name
);
3076 #endif /* DEBUG386 */
3078 static bfd_reloc_code_real_type
3079 reloc (unsigned int size
,
3082 bfd_reloc_code_real_type other
)
3084 if (other
!= NO_RELOC
)
3086 reloc_howto_type
*rel
;
3091 case BFD_RELOC_X86_64_GOT32
:
3092 return BFD_RELOC_X86_64_GOT64
;
3094 case BFD_RELOC_X86_64_GOTPLT64
:
3095 return BFD_RELOC_X86_64_GOTPLT64
;
3097 case BFD_RELOC_X86_64_PLTOFF64
:
3098 return BFD_RELOC_X86_64_PLTOFF64
;
3100 case BFD_RELOC_X86_64_GOTPC32
:
3101 other
= BFD_RELOC_X86_64_GOTPC64
;
3103 case BFD_RELOC_X86_64_GOTPCREL
:
3104 other
= BFD_RELOC_X86_64_GOTPCREL64
;
3106 case BFD_RELOC_X86_64_TPOFF32
:
3107 other
= BFD_RELOC_X86_64_TPOFF64
;
3109 case BFD_RELOC_X86_64_DTPOFF32
:
3110 other
= BFD_RELOC_X86_64_DTPOFF64
;
3116 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3117 if (other
== BFD_RELOC_SIZE32
)
3120 other
= BFD_RELOC_SIZE64
;
3123 as_bad (_("there are no pc-relative size relocations"));
3129 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
3130 if (size
== 4 && (flag_code
!= CODE_64BIT
|| disallow_64bit_reloc
))
3133 rel
= bfd_reloc_type_lookup (stdoutput
, other
);
3135 as_bad (_("unknown relocation (%u)"), other
);
3136 else if (size
!= bfd_get_reloc_size (rel
))
3137 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
3138 bfd_get_reloc_size (rel
),
3140 else if (pcrel
&& !rel
->pc_relative
)
3141 as_bad (_("non-pc-relative relocation for pc-relative field"));
3142 else if ((rel
->complain_on_overflow
== complain_overflow_signed
3144 || (rel
->complain_on_overflow
== complain_overflow_unsigned
3146 as_bad (_("relocated field and relocation type differ in signedness"));
3155 as_bad (_("there are no unsigned pc-relative relocations"));
3158 case 1: return BFD_RELOC_8_PCREL
;
3159 case 2: return BFD_RELOC_16_PCREL
;
3160 case 4: return BFD_RELOC_32_PCREL
;
3161 case 8: return BFD_RELOC_64_PCREL
;
3163 as_bad (_("cannot do %u byte pc-relative relocation"), size
);
3170 case 4: return BFD_RELOC_X86_64_32S
;
3175 case 1: return BFD_RELOC_8
;
3176 case 2: return BFD_RELOC_16
;
3177 case 4: return BFD_RELOC_32
;
3178 case 8: return BFD_RELOC_64
;
3180 as_bad (_("cannot do %s %u byte relocation"),
3181 sign
> 0 ? "signed" : "unsigned", size
);
3187 /* Here we decide which fixups can be adjusted to make them relative to
3188 the beginning of the section instead of the symbol. Basically we need
3189 to make sure that the dynamic relocations are done correctly, so in
3190 some cases we force the original symbol to be used. */
3193 tc_i386_fix_adjustable (fixS
*fixP ATTRIBUTE_UNUSED
)
3195 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3199 /* Don't adjust pc-relative references to merge sections in 64-bit
3201 if (use_rela_relocations
3202 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
3206 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
3207 and changed later by validate_fix. */
3208 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
3209 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
3212 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
3213 for size relocations. */
3214 if (fixP
->fx_r_type
== BFD_RELOC_SIZE32
3215 || fixP
->fx_r_type
== BFD_RELOC_SIZE64
3216 || fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
3217 || fixP
->fx_r_type
== BFD_RELOC_386_PLT32
3218 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
3219 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32X
3220 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
3221 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
3222 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
3223 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
3224 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
3225 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
3226 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
3227 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
3228 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTDESC
3229 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_DESC_CALL
3230 || fixP
->fx_r_type
== BFD_RELOC_X86_64_PLT32
3231 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
3232 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
3233 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCRELX
3234 || fixP
->fx_r_type
== BFD_RELOC_X86_64_REX_GOTPCRELX
3235 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
3236 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
3237 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
3238 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
3239 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
3240 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
3241 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
3242 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
3243 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPC32_TLSDESC
3244 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSDESC_CALL
3245 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
3246 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
3253 intel_float_operand (const char *mnemonic
)
3255 /* Note that the value returned is meaningful only for opcodes with (memory)
3256 operands, hence the code here is free to improperly handle opcodes that
3257 have no operands (for better performance and smaller code). */
3259 if (mnemonic
[0] != 'f')
3260 return 0; /* non-math */
3262 switch (mnemonic
[1])
3264 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
3265 the fs segment override prefix not currently handled because no
3266 call path can make opcodes without operands get here */
3268 return 2 /* integer op */;
3270 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
3271 return 3; /* fldcw/fldenv */
3274 if (mnemonic
[2] != 'o' /* fnop */)
3275 return 3; /* non-waiting control op */
3278 if (mnemonic
[2] == 's')
3279 return 3; /* frstor/frstpm */
3282 if (mnemonic
[2] == 'a')
3283 return 3; /* fsave */
3284 if (mnemonic
[2] == 't')
3286 switch (mnemonic
[3])
3288 case 'c': /* fstcw */
3289 case 'd': /* fstdw */
3290 case 'e': /* fstenv */
3291 case 's': /* fsts[gw] */
3297 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
3298 return 0; /* fxsave/fxrstor are not really math ops */
3305 /* Build the VEX prefix. */
3308 build_vex_prefix (const insn_template
*t
)
3310 unsigned int register_specifier
;
3311 unsigned int implied_prefix
;
3312 unsigned int vector_length
;
3314 /* Check register specifier. */
3315 if (i
.vex
.register_specifier
)
3317 register_specifier
=
3318 ~register_number (i
.vex
.register_specifier
) & 0xf;
3319 gas_assert ((i
.vex
.register_specifier
->reg_flags
& RegVRex
) == 0);
3322 register_specifier
= 0xf;
3324 /* Use 2-byte VEX prefix by swapping destination and source
3326 if (i
.vec_encoding
!= vex_encoding_vex3
3327 && i
.dir_encoding
== dir_encoding_default
3328 && i
.operands
== i
.reg_operands
3329 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3330 && i
.tm
.opcode_modifier
.load
3333 unsigned int xchg
= i
.operands
- 1;
3334 union i386_op temp_op
;
3335 i386_operand_type temp_type
;
3337 temp_type
= i
.types
[xchg
];
3338 i
.types
[xchg
] = i
.types
[0];
3339 i
.types
[0] = temp_type
;
3340 temp_op
= i
.op
[xchg
];
3341 i
.op
[xchg
] = i
.op
[0];
3344 gas_assert (i
.rm
.mode
== 3);
3348 i
.rm
.regmem
= i
.rm
.reg
;
3351 /* Use the next insn. */
3355 if (i
.tm
.opcode_modifier
.vex
== VEXScalar
)
3356 vector_length
= avxscalar
;
3357 else if (i
.tm
.opcode_modifier
.vex
== VEX256
)
3364 for (op
= 0; op
< t
->operands
; ++op
)
3365 if (t
->operand_types
[op
].bitfield
.xmmword
3366 && t
->operand_types
[op
].bitfield
.ymmword
3367 && i
.types
[op
].bitfield
.ymmword
)
3374 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3379 case DATA_PREFIX_OPCODE
:
3382 case REPE_PREFIX_OPCODE
:
3385 case REPNE_PREFIX_OPCODE
:
3392 /* Use 2-byte VEX prefix if possible. */
3393 if (i
.vec_encoding
!= vex_encoding_vex3
3394 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3395 && i
.tm
.opcode_modifier
.vexw
!= VEXW1
3396 && (i
.rex
& (REX_W
| REX_X
| REX_B
)) == 0)
3398 /* 2-byte VEX prefix. */
3402 i
.vex
.bytes
[0] = 0xc5;
3404 /* Check the REX.R bit. */
3405 r
= (i
.rex
& REX_R
) ? 0 : 1;
3406 i
.vex
.bytes
[1] = (r
<< 7
3407 | register_specifier
<< 3
3408 | vector_length
<< 2
3413 /* 3-byte VEX prefix. */
3418 switch (i
.tm
.opcode_modifier
.vexopcode
)
3422 i
.vex
.bytes
[0] = 0xc4;
3426 i
.vex
.bytes
[0] = 0xc4;
3430 i
.vex
.bytes
[0] = 0xc4;
3434 i
.vex
.bytes
[0] = 0x8f;
3438 i
.vex
.bytes
[0] = 0x8f;
3442 i
.vex
.bytes
[0] = 0x8f;
3448 /* The high 3 bits of the second VEX byte are 1's compliment
3449 of RXB bits from REX. */
3450 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3452 /* Check the REX.W bit. */
3453 w
= (i
.rex
& REX_W
) ? 1 : 0;
3454 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
3457 i
.vex
.bytes
[2] = (w
<< 7
3458 | register_specifier
<< 3
3459 | vector_length
<< 2
3464 static INLINE bfd_boolean
3465 is_evex_encoding (const insn_template
*t
)
3467 return t
->opcode_modifier
.evex
3468 || t
->opcode_modifier
.broadcast
|| t
->opcode_modifier
.masking
3469 || t
->opcode_modifier
.staticrounding
|| t
->opcode_modifier
.sae
;
3472 /* Build the EVEX prefix. */
3475 build_evex_prefix (void)
3477 unsigned int register_specifier
;
3478 unsigned int implied_prefix
;
3480 rex_byte vrex_used
= 0;
3482 /* Check register specifier. */
3483 if (i
.vex
.register_specifier
)
3485 gas_assert ((i
.vrex
& REX_X
) == 0);
3487 register_specifier
= i
.vex
.register_specifier
->reg_num
;
3488 if ((i
.vex
.register_specifier
->reg_flags
& RegRex
))
3489 register_specifier
+= 8;
3490 /* The upper 16 registers are encoded in the fourth byte of the
3492 if (!(i
.vex
.register_specifier
->reg_flags
& RegVRex
))
3493 i
.vex
.bytes
[3] = 0x8;
3494 register_specifier
= ~register_specifier
& 0xf;
3498 register_specifier
= 0xf;
3500 /* Encode upper 16 vector index register in the fourth byte of
3502 if (!(i
.vrex
& REX_X
))
3503 i
.vex
.bytes
[3] = 0x8;
3508 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3513 case DATA_PREFIX_OPCODE
:
3516 case REPE_PREFIX_OPCODE
:
3519 case REPNE_PREFIX_OPCODE
:
3526 /* 4 byte EVEX prefix. */
3528 i
.vex
.bytes
[0] = 0x62;
3531 switch (i
.tm
.opcode_modifier
.vexopcode
)
3547 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3549 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3551 /* The fifth bit of the second EVEX byte is 1's compliment of the
3552 REX_R bit in VREX. */
3553 if (!(i
.vrex
& REX_R
))
3554 i
.vex
.bytes
[1] |= 0x10;
3558 if ((i
.reg_operands
+ i
.imm_operands
) == i
.operands
)
3560 /* When all operands are registers, the REX_X bit in REX is not
3561 used. We reuse it to encode the upper 16 registers, which is
3562 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3563 as 1's compliment. */
3564 if ((i
.vrex
& REX_B
))
3567 i
.vex
.bytes
[1] &= ~0x40;
3571 /* EVEX instructions shouldn't need the REX prefix. */
3572 i
.vrex
&= ~vrex_used
;
3573 gas_assert (i
.vrex
== 0);
3575 /* Check the REX.W bit. */
3576 w
= (i
.rex
& REX_W
) ? 1 : 0;
3577 if (i
.tm
.opcode_modifier
.vexw
)
3579 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
3582 /* If w is not set it means we are dealing with WIG instruction. */
3585 if (evexwig
== evexw1
)
3589 /* Encode the U bit. */
3590 implied_prefix
|= 0x4;
3592 /* The third byte of the EVEX prefix. */
3593 i
.vex
.bytes
[2] = (w
<< 7 | register_specifier
<< 3 | implied_prefix
);
3595 /* The fourth byte of the EVEX prefix. */
3596 /* The zeroing-masking bit. */
3597 if (i
.mask
&& i
.mask
->zeroing
)
3598 i
.vex
.bytes
[3] |= 0x80;
3600 /* Don't always set the broadcast bit if there is no RC. */
3603 /* Encode the vector length. */
3604 unsigned int vec_length
;
3606 if (!i
.tm
.opcode_modifier
.evex
3607 || i
.tm
.opcode_modifier
.evex
== EVEXDYN
)
3612 for (op
= 0; op
< i
.tm
.operands
; ++op
)
3613 if (i
.tm
.operand_types
[op
].bitfield
.xmmword
3614 + i
.tm
.operand_types
[op
].bitfield
.ymmword
3615 + i
.tm
.operand_types
[op
].bitfield
.zmmword
> 1)
3617 if (i
.types
[op
].bitfield
.zmmword
)
3618 i
.tm
.opcode_modifier
.evex
= EVEX512
;
3619 else if (i
.types
[op
].bitfield
.ymmword
)
3620 i
.tm
.opcode_modifier
.evex
= EVEX256
;
3621 else if (i
.types
[op
].bitfield
.xmmword
)
3622 i
.tm
.opcode_modifier
.evex
= EVEX128
;
3629 switch (i
.tm
.opcode_modifier
.evex
)
3631 case EVEXLIG
: /* LL' is ignored */
3632 vec_length
= evexlig
<< 5;
3635 vec_length
= 0 << 5;
3638 vec_length
= 1 << 5;
3641 vec_length
= 2 << 5;
3647 i
.vex
.bytes
[3] |= vec_length
;
3648 /* Encode the broadcast bit. */
3650 i
.vex
.bytes
[3] |= 0x10;
3654 if (i
.rounding
->type
!= saeonly
)
3655 i
.vex
.bytes
[3] |= 0x10 | (i
.rounding
->type
<< 5);
3657 i
.vex
.bytes
[3] |= 0x10 | (evexrcig
<< 5);
3660 if (i
.mask
&& i
.mask
->mask
)
3661 i
.vex
.bytes
[3] |= i
.mask
->mask
->reg_num
;
3665 process_immext (void)
3669 if ((i
.tm
.cpu_flags
.bitfield
.cpusse3
|| i
.tm
.cpu_flags
.bitfield
.cpusvme
)
3672 /* MONITOR/MWAIT as well as SVME instructions have fixed operands
3673 with an opcode suffix which is coded in the same place as an
3674 8-bit immediate field would be.
3675 Here we check those operands and remove them afterwards. */
3678 for (x
= 0; x
< i
.operands
; x
++)
3679 if (register_number (i
.op
[x
].regs
) != x
)
3680 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3681 register_prefix
, i
.op
[x
].regs
->reg_name
, x
+ 1,
3687 if (i
.tm
.cpu_flags
.bitfield
.cpumwaitx
&& i
.operands
> 0)
3689 /* MONITORX/MWAITX instructions have fixed operands with an opcode
3690 suffix which is coded in the same place as an 8-bit immediate
3692 Here we check those operands and remove them afterwards. */
3695 if (i
.operands
!= 3)
3698 for (x
= 0; x
< 2; x
++)
3699 if (register_number (i
.op
[x
].regs
) != x
)
3700 goto bad_register_operand
;
3702 /* Check for third operand for mwaitx/monitorx insn. */
3703 if (register_number (i
.op
[x
].regs
)
3704 != (x
+ (i
.tm
.extension_opcode
== 0xfb)))
3706 bad_register_operand
:
3707 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3708 register_prefix
, i
.op
[x
].regs
->reg_name
, x
+1,
3715 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
3716 which is coded in the same place as an 8-bit immediate field
3717 would be. Here we fake an 8-bit immediate operand from the
3718 opcode suffix stored in tm.extension_opcode.
3720 AVX instructions also use this encoding, for some of
3721 3 argument instructions. */
3723 gas_assert (i
.imm_operands
<= 1
3725 || ((i
.tm
.opcode_modifier
.vex
3726 || i
.tm
.opcode_modifier
.vexopcode
3727 || is_evex_encoding (&i
.tm
))
3728 && i
.operands
<= 4)));
3730 exp
= &im_expressions
[i
.imm_operands
++];
3731 i
.op
[i
.operands
].imms
= exp
;
3732 i
.types
[i
.operands
] = imm8
;
3734 exp
->X_op
= O_constant
;
3735 exp
->X_add_number
= i
.tm
.extension_opcode
;
3736 i
.tm
.extension_opcode
= None
;
3743 switch (i
.tm
.opcode_modifier
.hleprefixok
)
3748 as_bad (_("invalid instruction `%s' after `%s'"),
3749 i
.tm
.name
, i
.hle_prefix
);
3752 if (i
.prefix
[LOCK_PREFIX
])
3754 as_bad (_("missing `lock' with `%s'"), i
.hle_prefix
);
3758 case HLEPrefixRelease
:
3759 if (i
.prefix
[HLE_PREFIX
] != XRELEASE_PREFIX_OPCODE
)
3761 as_bad (_("instruction `%s' after `xacquire' not allowed"),
3765 if (i
.mem_operands
== 0
3766 || !operand_type_check (i
.types
[i
.operands
- 1], anymem
))
3768 as_bad (_("memory destination needed for instruction `%s'"
3769 " after `xrelease'"), i
.tm
.name
);
3776 /* Try the shortest encoding by shortening operand size. */
3779 optimize_encoding (void)
3783 if (optimize_for_space
3784 && i
.reg_operands
== 1
3785 && i
.imm_operands
== 1
3786 && !i
.types
[1].bitfield
.byte
3787 && i
.op
[0].imms
->X_op
== O_constant
3788 && fits_in_imm7 (i
.op
[0].imms
->X_add_number
)
3789 && ((i
.tm
.base_opcode
== 0xa8
3790 && i
.tm
.extension_opcode
== None
)
3791 || (i
.tm
.base_opcode
== 0xf6
3792 && i
.tm
.extension_opcode
== 0x0)))
3795 test $imm7, %r64/%r32/%r16 -> test $imm7, %r8
3797 unsigned int base_regnum
= i
.op
[1].regs
->reg_num
;
3798 if (flag_code
== CODE_64BIT
|| base_regnum
< 4)
3800 i
.types
[1].bitfield
.byte
= 1;
3801 /* Ignore the suffix. */
3803 if (base_regnum
>= 4
3804 && !(i
.op
[1].regs
->reg_flags
& RegRex
))
3806 /* Handle SP, BP, SI and DI registers. */
3807 if (i
.types
[1].bitfield
.word
)
3809 else if (i
.types
[1].bitfield
.dword
)
3817 else if (flag_code
== CODE_64BIT
3818 && ((i
.types
[1].bitfield
.qword
3819 && i
.reg_operands
== 1
3820 && i
.imm_operands
== 1
3821 && i
.op
[0].imms
->X_op
== O_constant
3822 && ((i
.tm
.base_opcode
== 0xb0
3823 && i
.tm
.extension_opcode
== None
3824 && fits_in_unsigned_long (i
.op
[0].imms
->X_add_number
))
3825 || (fits_in_imm31 (i
.op
[0].imms
->X_add_number
)
3826 && (((i
.tm
.base_opcode
== 0x24
3827 || i
.tm
.base_opcode
== 0xa8)
3828 && i
.tm
.extension_opcode
== None
)
3829 || (i
.tm
.base_opcode
== 0x80
3830 && i
.tm
.extension_opcode
== 0x4)
3831 || ((i
.tm
.base_opcode
== 0xf6
3832 || i
.tm
.base_opcode
== 0xc6)
3833 && i
.tm
.extension_opcode
== 0x0)))))
3834 || (i
.types
[0].bitfield
.qword
3835 && ((i
.reg_operands
== 2
3836 && i
.op
[0].regs
== i
.op
[1].regs
3837 && ((i
.tm
.base_opcode
== 0x30
3838 || i
.tm
.base_opcode
== 0x28)
3839 && i
.tm
.extension_opcode
== None
))
3840 || (i
.reg_operands
== 1
3842 && i
.tm
.base_opcode
== 0x30
3843 && i
.tm
.extension_opcode
== None
)))))
3846 andq $imm31, %r64 -> andl $imm31, %r32
3847 testq $imm31, %r64 -> testl $imm31, %r32
3848 xorq %r64, %r64 -> xorl %r32, %r32
3849 subq %r64, %r64 -> subl %r32, %r32
3850 movq $imm31, %r64 -> movl $imm31, %r32
3851 movq $imm32, %r64 -> movl $imm32, %r32
3853 i
.tm
.opcode_modifier
.norex64
= 1;
3854 if (i
.tm
.base_opcode
== 0xb0 || i
.tm
.base_opcode
== 0xc6)
3857 movq $imm31, %r64 -> movl $imm31, %r32
3858 movq $imm32, %r64 -> movl $imm32, %r32
3860 i
.tm
.operand_types
[0].bitfield
.imm32
= 1;
3861 i
.tm
.operand_types
[0].bitfield
.imm32s
= 0;
3862 i
.tm
.operand_types
[0].bitfield
.imm64
= 0;
3863 i
.types
[0].bitfield
.imm32
= 1;
3864 i
.types
[0].bitfield
.imm32s
= 0;
3865 i
.types
[0].bitfield
.imm64
= 0;
3866 i
.types
[1].bitfield
.dword
= 1;
3867 i
.types
[1].bitfield
.qword
= 0;
3868 if (i
.tm
.base_opcode
== 0xc6)
3871 movq $imm31, %r64 -> movl $imm31, %r32
3873 i
.tm
.base_opcode
= 0xb0;
3874 i
.tm
.extension_opcode
= None
;
3875 i
.tm
.opcode_modifier
.shortform
= 1;
3876 i
.tm
.opcode_modifier
.modrm
= 0;
3880 else if (optimize
> 1
3881 && i
.reg_operands
== 3
3882 && i
.op
[0].regs
== i
.op
[1].regs
3883 && !i
.types
[2].bitfield
.xmmword
3884 && (i
.tm
.opcode_modifier
.vex
3885 || ((!i
.mask
|| i
.mask
->zeroing
)
3887 && is_evex_encoding (&i
.tm
)
3888 && (i
.vec_encoding
!= vex_encoding_evex
3889 || i
.tm
.cpu_flags
.bitfield
.cpuavx512vl
3890 || cpu_arch_isa_flags
.bitfield
.cpuavx512vl
)))
3891 && ((i
.tm
.base_opcode
== 0x55
3892 || i
.tm
.base_opcode
== 0x6655
3893 || i
.tm
.base_opcode
== 0x66df
3894 || i
.tm
.base_opcode
== 0x57
3895 || i
.tm
.base_opcode
== 0x6657
3896 || i
.tm
.base_opcode
== 0x66ef
3897 || i
.tm
.base_opcode
== 0x66f8
3898 || i
.tm
.base_opcode
== 0x66f9
3899 || i
.tm
.base_opcode
== 0x66fa
3900 || i
.tm
.base_opcode
== 0x66fb)
3901 && i
.tm
.extension_opcode
== None
))
3904 VOP, one of vandnps, vandnpd, vxorps, vxorpd, vpsubb, vpsubd,
3906 EVEX VOP %zmmM, %zmmM, %zmmN
3907 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
3908 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3909 EVEX VOP %ymmM, %ymmM, %ymmN
3910 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
3911 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3912 VEX VOP %ymmM, %ymmM, %ymmN
3913 -> VEX VOP %xmmM, %xmmM, %xmmN
3914 VOP, one of vpandn and vpxor:
3915 VEX VOP %ymmM, %ymmM, %ymmN
3916 -> VEX VOP %xmmM, %xmmM, %xmmN
3917 VOP, one of vpandnd and vpandnq:
3918 EVEX VOP %zmmM, %zmmM, %zmmN
3919 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
3920 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3921 EVEX VOP %ymmM, %ymmM, %ymmN
3922 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
3923 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3924 VOP, one of vpxord and vpxorq:
3925 EVEX VOP %zmmM, %zmmM, %zmmN
3926 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
3927 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3928 EVEX VOP %ymmM, %ymmM, %ymmN
3929 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
3930 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3932 if (is_evex_encoding (&i
.tm
))
3934 if (i
.vec_encoding
== vex_encoding_evex
)
3935 i
.tm
.opcode_modifier
.evex
= EVEX128
;
3938 i
.tm
.opcode_modifier
.vex
= VEX128
;
3939 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
3940 i
.tm
.opcode_modifier
.evex
= 0;
3944 i
.tm
.opcode_modifier
.vex
= VEX128
;
3946 if (i
.tm
.opcode_modifier
.vex
)
3947 for (j
= 0; j
< 3; j
++)
3949 i
.types
[j
].bitfield
.xmmword
= 1;
3950 i
.types
[j
].bitfield
.ymmword
= 0;
3955 /* This is the guts of the machine-dependent assembler. LINE points to a
3956 machine dependent instruction. This function is supposed to emit
3957 the frags/bytes it assembles to. */
3960 md_assemble (char *line
)
3963 char mnemonic
[MAX_MNEM_SIZE
], mnem_suffix
;
3964 const insn_template
*t
;
3966 /* Initialize globals. */
3967 memset (&i
, '\0', sizeof (i
));
3968 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3969 i
.reloc
[j
] = NO_RELOC
;
3970 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
3971 memset (im_expressions
, '\0', sizeof (im_expressions
));
3972 save_stack_p
= save_stack
;
3974 /* First parse an instruction mnemonic & call i386_operand for the operands.
3975 We assume that the scrubber has arranged it so that line[0] is the valid
3976 start of a (possibly prefixed) mnemonic. */
3978 line
= parse_insn (line
, mnemonic
);
3981 mnem_suffix
= i
.suffix
;
3983 line
= parse_operands (line
, mnemonic
);
3985 xfree (i
.memop1_string
);
3986 i
.memop1_string
= NULL
;
3990 /* Now we've parsed the mnemonic into a set of templates, and have the
3991 operands at hand. */
3993 /* All intel opcodes have reversed operands except for "bound" and
3994 "enter". We also don't reverse intersegment "jmp" and "call"
3995 instructions with 2 immediate operands so that the immediate segment
3996 precedes the offset, as it does when in AT&T mode. */
3999 && (strcmp (mnemonic
, "bound") != 0)
4000 && (strcmp (mnemonic
, "invlpga") != 0)
4001 && !(operand_type_check (i
.types
[0], imm
)
4002 && operand_type_check (i
.types
[1], imm
)))
4005 /* The order of the immediates should be reversed
4006 for 2 immediates extrq and insertq instructions */
4007 if (i
.imm_operands
== 2
4008 && (strcmp (mnemonic
, "extrq") == 0
4009 || strcmp (mnemonic
, "insertq") == 0))
4010 swap_2_operands (0, 1);
4015 /* Don't optimize displacement for movabs since it only takes 64bit
4018 && i
.disp_encoding
!= disp_encoding_32bit
4019 && (flag_code
!= CODE_64BIT
4020 || strcmp (mnemonic
, "movabs") != 0))
4023 /* Next, we find a template that matches the given insn,
4024 making sure the overlap of the given operands types is consistent
4025 with the template operand types. */
4027 if (!(t
= match_template (mnem_suffix
)))
4030 if (sse_check
!= check_none
4031 && !i
.tm
.opcode_modifier
.noavx
4032 && !i
.tm
.cpu_flags
.bitfield
.cpuavx
4033 && (i
.tm
.cpu_flags
.bitfield
.cpusse
4034 || i
.tm
.cpu_flags
.bitfield
.cpusse2
4035 || i
.tm
.cpu_flags
.bitfield
.cpusse3
4036 || i
.tm
.cpu_flags
.bitfield
.cpussse3
4037 || i
.tm
.cpu_flags
.bitfield
.cpusse4_1
4038 || i
.tm
.cpu_flags
.bitfield
.cpusse4_2
4039 || i
.tm
.cpu_flags
.bitfield
.cpupclmul
4040 || i
.tm
.cpu_flags
.bitfield
.cpuaes
4041 || i
.tm
.cpu_flags
.bitfield
.cpugfni
))
4043 (sse_check
== check_warning
4045 : as_bad
) (_("SSE instruction `%s' is used"), i
.tm
.name
);
4048 /* Zap movzx and movsx suffix. The suffix has been set from
4049 "word ptr" or "byte ptr" on the source operand in Intel syntax
4050 or extracted from mnemonic in AT&T syntax. But we'll use
4051 the destination register to choose the suffix for encoding. */
4052 if ((i
.tm
.base_opcode
& ~9) == 0x0fb6)
4054 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
4055 there is no suffix, the default will be byte extension. */
4056 if (i
.reg_operands
!= 2
4059 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
4064 if (i
.tm
.opcode_modifier
.fwait
)
4065 if (!add_prefix (FWAIT_OPCODE
))
4068 /* Check if REP prefix is OK. */
4069 if (i
.rep_prefix
&& !i
.tm
.opcode_modifier
.repprefixok
)
4071 as_bad (_("invalid instruction `%s' after `%s'"),
4072 i
.tm
.name
, i
.rep_prefix
);
4076 /* Check for lock without a lockable instruction. Destination operand
4077 must be memory unless it is xchg (0x86). */
4078 if (i
.prefix
[LOCK_PREFIX
]
4079 && (!i
.tm
.opcode_modifier
.islockable
4080 || i
.mem_operands
== 0
4081 || (i
.tm
.base_opcode
!= 0x86
4082 && !operand_type_check (i
.types
[i
.operands
- 1], anymem
))))
4084 as_bad (_("expecting lockable instruction after `lock'"));
4088 /* Check if HLE prefix is OK. */
4089 if (i
.hle_prefix
&& !check_hle ())
4092 /* Check BND prefix. */
4093 if (i
.bnd_prefix
&& !i
.tm
.opcode_modifier
.bndprefixok
)
4094 as_bad (_("expecting valid branch instruction after `bnd'"));
4096 /* Check NOTRACK prefix. */
4097 if (i
.notrack_prefix
&& !i
.tm
.opcode_modifier
.notrackprefixok
)
4098 as_bad (_("expecting indirect branch instruction after `notrack'"));
4100 if (i
.tm
.cpu_flags
.bitfield
.cpumpx
)
4102 if (flag_code
== CODE_64BIT
&& i
.prefix
[ADDR_PREFIX
])
4103 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
4104 else if (flag_code
!= CODE_16BIT
4105 ? i
.prefix
[ADDR_PREFIX
]
4106 : i
.mem_operands
&& !i
.prefix
[ADDR_PREFIX
])
4107 as_bad (_("16-bit address isn't allowed in MPX instructions"));
4110 /* Insert BND prefix. */
4111 if (add_bnd_prefix
&& i
.tm
.opcode_modifier
.bndprefixok
)
4113 if (!i
.prefix
[BND_PREFIX
])
4114 add_prefix (BND_PREFIX_OPCODE
);
4115 else if (i
.prefix
[BND_PREFIX
] != BND_PREFIX_OPCODE
)
4117 as_warn (_("replacing `rep'/`repe' prefix by `bnd'"));
4118 i
.prefix
[BND_PREFIX
] = BND_PREFIX_OPCODE
;
4122 /* Check string instruction segment overrides. */
4123 if (i
.tm
.opcode_modifier
.isstring
&& i
.mem_operands
!= 0)
4125 if (!check_string ())
4127 i
.disp_operands
= 0;
4130 if (optimize
&& !i
.no_optimize
&& i
.tm
.opcode_modifier
.optimize
)
4131 optimize_encoding ();
4133 if (!process_suffix ())
4136 /* Update operand types. */
4137 for (j
= 0; j
< i
.operands
; j
++)
4138 i
.types
[j
] = operand_type_and (i
.types
[j
], i
.tm
.operand_types
[j
]);
4140 /* Make still unresolved immediate matches conform to size of immediate
4141 given in i.suffix. */
4142 if (!finalize_imm ())
4145 if (i
.types
[0].bitfield
.imm1
)
4146 i
.imm_operands
= 0; /* kludge for shift insns. */
4148 /* We only need to check those implicit registers for instructions
4149 with 3 operands or less. */
4150 if (i
.operands
<= 3)
4151 for (j
= 0; j
< i
.operands
; j
++)
4152 if (i
.types
[j
].bitfield
.inoutportreg
4153 || i
.types
[j
].bitfield
.shiftcount
4154 || (i
.types
[j
].bitfield
.acc
&& !i
.types
[j
].bitfield
.xmmword
))
4157 /* ImmExt should be processed after SSE2AVX. */
4158 if (!i
.tm
.opcode_modifier
.sse2avx
4159 && i
.tm
.opcode_modifier
.immext
)
4162 /* For insns with operands there are more diddles to do to the opcode. */
4165 if (!process_operands ())
4168 else if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
4170 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
4171 as_warn (_("translating to `%sp'"), i
.tm
.name
);
4174 if (i
.tm
.opcode_modifier
.vex
|| i
.tm
.opcode_modifier
.vexopcode
4175 || is_evex_encoding (&i
.tm
))
4177 if (flag_code
== CODE_16BIT
)
4179 as_bad (_("instruction `%s' isn't supported in 16-bit mode."),
4184 if (i
.tm
.opcode_modifier
.vex
)
4185 build_vex_prefix (t
);
4187 build_evex_prefix ();
4190 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
4191 instructions may define INT_OPCODE as well, so avoid this corner
4192 case for those instructions that use MODRM. */
4193 if (i
.tm
.base_opcode
== INT_OPCODE
4194 && !i
.tm
.opcode_modifier
.modrm
4195 && i
.op
[0].imms
->X_add_number
== 3)
4197 i
.tm
.base_opcode
= INT3_OPCODE
;
4201 if ((i
.tm
.opcode_modifier
.jump
4202 || i
.tm
.opcode_modifier
.jumpbyte
4203 || i
.tm
.opcode_modifier
.jumpdword
)
4204 && i
.op
[0].disps
->X_op
== O_constant
)
4206 /* Convert "jmp constant" (and "call constant") to a jump (call) to
4207 the absolute address given by the constant. Since ix86 jumps and
4208 calls are pc relative, we need to generate a reloc. */
4209 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
4210 i
.op
[0].disps
->X_op
= O_symbol
;
4213 if (i
.tm
.opcode_modifier
.rex64
)
4216 /* For 8 bit registers we need an empty rex prefix. Also if the
4217 instruction already has a prefix, we need to convert old
4218 registers to new ones. */
4220 if ((i
.types
[0].bitfield
.reg
&& i
.types
[0].bitfield
.byte
4221 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
4222 || (i
.types
[1].bitfield
.reg
&& i
.types
[1].bitfield
.byte
4223 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
4224 || (((i
.types
[0].bitfield
.reg
&& i
.types
[0].bitfield
.byte
)
4225 || (i
.types
[1].bitfield
.reg
&& i
.types
[1].bitfield
.byte
))
4230 i
.rex
|= REX_OPCODE
;
4231 for (x
= 0; x
< 2; x
++)
4233 /* Look for 8 bit operand that uses old registers. */
4234 if (i
.types
[x
].bitfield
.reg
&& i
.types
[x
].bitfield
.byte
4235 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
4237 /* In case it is "hi" register, give up. */
4238 if (i
.op
[x
].regs
->reg_num
> 3)
4239 as_bad (_("can't encode register '%s%s' in an "
4240 "instruction requiring REX prefix."),
4241 register_prefix
, i
.op
[x
].regs
->reg_name
);
4243 /* Otherwise it is equivalent to the extended register.
4244 Since the encoding doesn't change this is merely
4245 cosmetic cleanup for debug output. */
4247 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
4252 if (i
.rex
== 0 && i
.rex_encoding
)
4254 /* Check if we can add a REX_OPCODE byte. Look for 8 bit operand
4255 that uses legacy register. If it is "hi" register, don't add
4256 the REX_OPCODE byte. */
4258 for (x
= 0; x
< 2; x
++)
4259 if (i
.types
[x
].bitfield
.reg
4260 && i
.types
[x
].bitfield
.byte
4261 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0
4262 && i
.op
[x
].regs
->reg_num
> 3)
4264 i
.rex_encoding
= FALSE
;
4273 add_prefix (REX_OPCODE
| i
.rex
);
4275 /* We are ready to output the insn. */
4280 parse_insn (char *line
, char *mnemonic
)
4283 char *token_start
= l
;
4286 const insn_template
*t
;
4292 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
4297 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
4299 as_bad (_("no such instruction: `%s'"), token_start
);
4304 if (!is_space_char (*l
)
4305 && *l
!= END_OF_INSN
4307 || (*l
!= PREFIX_SEPARATOR
4310 as_bad (_("invalid character %s in mnemonic"),
4311 output_invalid (*l
));
4314 if (token_start
== l
)
4316 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
4317 as_bad (_("expecting prefix; got nothing"));
4319 as_bad (_("expecting mnemonic; got nothing"));
4323 /* Look up instruction (or prefix) via hash table. */
4324 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
4326 if (*l
!= END_OF_INSN
4327 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
4328 && current_templates
4329 && current_templates
->start
->opcode_modifier
.isprefix
)
4331 if (!cpu_flags_check_cpu64 (current_templates
->start
->cpu_flags
))
4333 as_bad ((flag_code
!= CODE_64BIT
4334 ? _("`%s' is only supported in 64-bit mode")
4335 : _("`%s' is not supported in 64-bit mode")),
4336 current_templates
->start
->name
);
4339 /* If we are in 16-bit mode, do not allow addr16 or data16.
4340 Similarly, in 32-bit mode, do not allow addr32 or data32. */
4341 if ((current_templates
->start
->opcode_modifier
.size16
4342 || current_templates
->start
->opcode_modifier
.size32
)
4343 && flag_code
!= CODE_64BIT
4344 && (current_templates
->start
->opcode_modifier
.size32
4345 ^ (flag_code
== CODE_16BIT
)))
4347 as_bad (_("redundant %s prefix"),
4348 current_templates
->start
->name
);
4351 if (current_templates
->start
->opcode_length
== 0)
4353 /* Handle pseudo prefixes. */
4354 switch (current_templates
->start
->base_opcode
)
4358 i
.disp_encoding
= disp_encoding_8bit
;
4362 i
.disp_encoding
= disp_encoding_32bit
;
4366 i
.dir_encoding
= dir_encoding_load
;
4370 i
.dir_encoding
= dir_encoding_store
;
4374 i
.vec_encoding
= vex_encoding_vex2
;
4378 i
.vec_encoding
= vex_encoding_vex3
;
4382 i
.vec_encoding
= vex_encoding_evex
;
4386 i
.rex_encoding
= TRUE
;
4390 i
.no_optimize
= TRUE
;
4398 /* Add prefix, checking for repeated prefixes. */
4399 switch (add_prefix (current_templates
->start
->base_opcode
))
4404 if (current_templates
->start
->cpu_flags
.bitfield
.cpuibt
)
4405 i
.notrack_prefix
= current_templates
->start
->name
;
4408 if (current_templates
->start
->cpu_flags
.bitfield
.cpuhle
)
4409 i
.hle_prefix
= current_templates
->start
->name
;
4410 else if (current_templates
->start
->cpu_flags
.bitfield
.cpumpx
)
4411 i
.bnd_prefix
= current_templates
->start
->name
;
4413 i
.rep_prefix
= current_templates
->start
->name
;
4419 /* Skip past PREFIX_SEPARATOR and reset token_start. */
4426 if (!current_templates
)
4428 /* Check if we should swap operand or force 32bit displacement in
4430 if (mnem_p
- 2 == dot_p
&& dot_p
[1] == 's')
4431 i
.dir_encoding
= dir_encoding_store
;
4432 else if (mnem_p
- 3 == dot_p
4435 i
.disp_encoding
= disp_encoding_8bit
;
4436 else if (mnem_p
- 4 == dot_p
4440 i
.disp_encoding
= disp_encoding_32bit
;
4445 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
4448 if (!current_templates
)
4451 /* See if we can get a match by trimming off a suffix. */
4454 case WORD_MNEM_SUFFIX
:
4455 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
4456 i
.suffix
= SHORT_MNEM_SUFFIX
;
4459 case BYTE_MNEM_SUFFIX
:
4460 case QWORD_MNEM_SUFFIX
:
4461 i
.suffix
= mnem_p
[-1];
4463 current_templates
= (const templates
*) hash_find (op_hash
,
4466 case SHORT_MNEM_SUFFIX
:
4467 case LONG_MNEM_SUFFIX
:
4470 i
.suffix
= mnem_p
[-1];
4472 current_templates
= (const templates
*) hash_find (op_hash
,
4481 if (intel_float_operand (mnemonic
) == 1)
4482 i
.suffix
= SHORT_MNEM_SUFFIX
;
4484 i
.suffix
= LONG_MNEM_SUFFIX
;
4486 current_templates
= (const templates
*) hash_find (op_hash
,
4491 if (!current_templates
)
4493 as_bad (_("no such instruction: `%s'"), token_start
);
4498 if (current_templates
->start
->opcode_modifier
.jump
4499 || current_templates
->start
->opcode_modifier
.jumpbyte
)
4501 /* Check for a branch hint. We allow ",pt" and ",pn" for
4502 predict taken and predict not taken respectively.
4503 I'm not sure that branch hints actually do anything on loop
4504 and jcxz insns (JumpByte) for current Pentium4 chips. They
4505 may work in the future and it doesn't hurt to accept them
4507 if (l
[0] == ',' && l
[1] == 'p')
4511 if (!add_prefix (DS_PREFIX_OPCODE
))
4515 else if (l
[2] == 'n')
4517 if (!add_prefix (CS_PREFIX_OPCODE
))
4523 /* Any other comma loses. */
4526 as_bad (_("invalid character %s in mnemonic"),
4527 output_invalid (*l
));
4531 /* Check if instruction is supported on specified architecture. */
4533 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
4535 supported
|= cpu_flags_match (t
);
4536 if (supported
== CPU_FLAGS_PERFECT_MATCH
)
4538 if (!cpu_arch_flags
.bitfield
.cpui386
&& (flag_code
!= CODE_16BIT
))
4539 as_warn (_("use .code16 to ensure correct addressing mode"));
4545 if (!(supported
& CPU_FLAGS_64BIT_MATCH
))
4546 as_bad (flag_code
== CODE_64BIT
4547 ? _("`%s' is not supported in 64-bit mode")
4548 : _("`%s' is only supported in 64-bit mode"),
4549 current_templates
->start
->name
);
4551 as_bad (_("`%s' is not supported on `%s%s'"),
4552 current_templates
->start
->name
,
4553 cpu_arch_name
? cpu_arch_name
: default_arch
,
4554 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
4560 parse_operands (char *l
, const char *mnemonic
)
4564 /* 1 if operand is pending after ','. */
4565 unsigned int expecting_operand
= 0;
4567 /* Non-zero if operand parens not balanced. */
4568 unsigned int paren_not_balanced
;
4570 while (*l
!= END_OF_INSN
)
4572 /* Skip optional white space before operand. */
4573 if (is_space_char (*l
))
4575 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
&& *l
!= '"')
4577 as_bad (_("invalid character %s before operand %d"),
4578 output_invalid (*l
),
4582 token_start
= l
; /* After white space. */
4583 paren_not_balanced
= 0;
4584 while (paren_not_balanced
|| *l
!= ',')
4586 if (*l
== END_OF_INSN
)
4588 if (paren_not_balanced
)
4591 as_bad (_("unbalanced parenthesis in operand %d."),
4594 as_bad (_("unbalanced brackets in operand %d."),
4599 break; /* we are done */
4601 else if (!is_operand_char (*l
) && !is_space_char (*l
) && *l
!= '"')
4603 as_bad (_("invalid character %s in operand %d"),
4604 output_invalid (*l
),
4611 ++paren_not_balanced
;
4613 --paren_not_balanced
;
4618 ++paren_not_balanced
;
4620 --paren_not_balanced
;
4624 if (l
!= token_start
)
4625 { /* Yes, we've read in another operand. */
4626 unsigned int operand_ok
;
4627 this_operand
= i
.operands
++;
4628 if (i
.operands
> MAX_OPERANDS
)
4630 as_bad (_("spurious operands; (%d operands/instruction max)"),
4634 i
.types
[this_operand
].bitfield
.unspecified
= 1;
4635 /* Now parse operand adding info to 'i' as we go along. */
4636 END_STRING_AND_SAVE (l
);
4640 i386_intel_operand (token_start
,
4641 intel_float_operand (mnemonic
));
4643 operand_ok
= i386_att_operand (token_start
);
4645 RESTORE_END_STRING (l
);
4651 if (expecting_operand
)
4653 expecting_operand_after_comma
:
4654 as_bad (_("expecting operand after ','; got nothing"));
4659 as_bad (_("expecting operand before ','; got nothing"));
4664 /* Now *l must be either ',' or END_OF_INSN. */
4667 if (*++l
== END_OF_INSN
)
4669 /* Just skip it, if it's \n complain. */
4670 goto expecting_operand_after_comma
;
4672 expecting_operand
= 1;
4679 swap_2_operands (int xchg1
, int xchg2
)
4681 union i386_op temp_op
;
4682 i386_operand_type temp_type
;
4683 enum bfd_reloc_code_real temp_reloc
;
4685 temp_type
= i
.types
[xchg2
];
4686 i
.types
[xchg2
] = i
.types
[xchg1
];
4687 i
.types
[xchg1
] = temp_type
;
4688 temp_op
= i
.op
[xchg2
];
4689 i
.op
[xchg2
] = i
.op
[xchg1
];
4690 i
.op
[xchg1
] = temp_op
;
4691 temp_reloc
= i
.reloc
[xchg2
];
4692 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
4693 i
.reloc
[xchg1
] = temp_reloc
;
4697 if (i
.mask
->operand
== xchg1
)
4698 i
.mask
->operand
= xchg2
;
4699 else if (i
.mask
->operand
== xchg2
)
4700 i
.mask
->operand
= xchg1
;
4704 if (i
.broadcast
->operand
== xchg1
)
4705 i
.broadcast
->operand
= xchg2
;
4706 else if (i
.broadcast
->operand
== xchg2
)
4707 i
.broadcast
->operand
= xchg1
;
4711 if (i
.rounding
->operand
== xchg1
)
4712 i
.rounding
->operand
= xchg2
;
4713 else if (i
.rounding
->operand
== xchg2
)
4714 i
.rounding
->operand
= xchg1
;
4719 swap_operands (void)
4725 swap_2_operands (1, i
.operands
- 2);
4729 swap_2_operands (0, i
.operands
- 1);
4735 if (i
.mem_operands
== 2)
4737 const seg_entry
*temp_seg
;
4738 temp_seg
= i
.seg
[0];
4739 i
.seg
[0] = i
.seg
[1];
4740 i
.seg
[1] = temp_seg
;
4744 /* Try to ensure constant immediates are represented in the smallest
4749 char guess_suffix
= 0;
4753 guess_suffix
= i
.suffix
;
4754 else if (i
.reg_operands
)
4756 /* Figure out a suffix from the last register operand specified.
4757 We can't do this properly yet, ie. excluding InOutPortReg,
4758 but the following works for instructions with immediates.
4759 In any case, we can't set i.suffix yet. */
4760 for (op
= i
.operands
; --op
>= 0;)
4761 if (i
.types
[op
].bitfield
.reg
&& i
.types
[op
].bitfield
.byte
)
4763 guess_suffix
= BYTE_MNEM_SUFFIX
;
4766 else if (i
.types
[op
].bitfield
.reg
&& i
.types
[op
].bitfield
.word
)
4768 guess_suffix
= WORD_MNEM_SUFFIX
;
4771 else if (i
.types
[op
].bitfield
.reg
&& i
.types
[op
].bitfield
.dword
)
4773 guess_suffix
= LONG_MNEM_SUFFIX
;
4776 else if (i
.types
[op
].bitfield
.reg
&& i
.types
[op
].bitfield
.qword
)
4778 guess_suffix
= QWORD_MNEM_SUFFIX
;
4782 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
4783 guess_suffix
= WORD_MNEM_SUFFIX
;
4785 for (op
= i
.operands
; --op
>= 0;)
4786 if (operand_type_check (i
.types
[op
], imm
))
4788 switch (i
.op
[op
].imms
->X_op
)
4791 /* If a suffix is given, this operand may be shortened. */
4792 switch (guess_suffix
)
4794 case LONG_MNEM_SUFFIX
:
4795 i
.types
[op
].bitfield
.imm32
= 1;
4796 i
.types
[op
].bitfield
.imm64
= 1;
4798 case WORD_MNEM_SUFFIX
:
4799 i
.types
[op
].bitfield
.imm16
= 1;
4800 i
.types
[op
].bitfield
.imm32
= 1;
4801 i
.types
[op
].bitfield
.imm32s
= 1;
4802 i
.types
[op
].bitfield
.imm64
= 1;
4804 case BYTE_MNEM_SUFFIX
:
4805 i
.types
[op
].bitfield
.imm8
= 1;
4806 i
.types
[op
].bitfield
.imm8s
= 1;
4807 i
.types
[op
].bitfield
.imm16
= 1;
4808 i
.types
[op
].bitfield
.imm32
= 1;
4809 i
.types
[op
].bitfield
.imm32s
= 1;
4810 i
.types
[op
].bitfield
.imm64
= 1;
4814 /* If this operand is at most 16 bits, convert it
4815 to a signed 16 bit number before trying to see
4816 whether it will fit in an even smaller size.
4817 This allows a 16-bit operand such as $0xffe0 to
4818 be recognised as within Imm8S range. */
4819 if ((i
.types
[op
].bitfield
.imm16
)
4820 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
4822 i
.op
[op
].imms
->X_add_number
=
4823 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
4826 /* Store 32-bit immediate in 64-bit for 64-bit BFD. */
4827 if ((i
.types
[op
].bitfield
.imm32
)
4828 && ((i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1))
4831 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
4832 ^ ((offsetT
) 1 << 31))
4833 - ((offsetT
) 1 << 31));
4837 = operand_type_or (i
.types
[op
],
4838 smallest_imm_type (i
.op
[op
].imms
->X_add_number
));
4840 /* We must avoid matching of Imm32 templates when 64bit
4841 only immediate is available. */
4842 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
4843 i
.types
[op
].bitfield
.imm32
= 0;
4850 /* Symbols and expressions. */
4852 /* Convert symbolic operand to proper sizes for matching, but don't
4853 prevent matching a set of insns that only supports sizes other
4854 than those matching the insn suffix. */
4856 i386_operand_type mask
, allowed
;
4857 const insn_template
*t
;
4859 operand_type_set (&mask
, 0);
4860 operand_type_set (&allowed
, 0);
4862 for (t
= current_templates
->start
;
4863 t
< current_templates
->end
;
4865 allowed
= operand_type_or (allowed
,
4866 t
->operand_types
[op
]);
4867 switch (guess_suffix
)
4869 case QWORD_MNEM_SUFFIX
:
4870 mask
.bitfield
.imm64
= 1;
4871 mask
.bitfield
.imm32s
= 1;
4873 case LONG_MNEM_SUFFIX
:
4874 mask
.bitfield
.imm32
= 1;
4876 case WORD_MNEM_SUFFIX
:
4877 mask
.bitfield
.imm16
= 1;
4879 case BYTE_MNEM_SUFFIX
:
4880 mask
.bitfield
.imm8
= 1;
4885 allowed
= operand_type_and (mask
, allowed
);
4886 if (!operand_type_all_zero (&allowed
))
4887 i
.types
[op
] = operand_type_and (i
.types
[op
], mask
);
4894 /* Try to use the smallest displacement type too. */
4896 optimize_disp (void)
4900 for (op
= i
.operands
; --op
>= 0;)
4901 if (operand_type_check (i
.types
[op
], disp
))
4903 if (i
.op
[op
].disps
->X_op
== O_constant
)
4905 offsetT op_disp
= i
.op
[op
].disps
->X_add_number
;
4907 if (i
.types
[op
].bitfield
.disp16
4908 && (op_disp
& ~(offsetT
) 0xffff) == 0)
4910 /* If this operand is at most 16 bits, convert
4911 to a signed 16 bit number and don't use 64bit
4913 op_disp
= (((op_disp
& 0xffff) ^ 0x8000) - 0x8000);
4914 i
.types
[op
].bitfield
.disp64
= 0;
4917 /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */
4918 if (i
.types
[op
].bitfield
.disp32
4919 && (op_disp
& ~(((offsetT
) 2 << 31) - 1)) == 0)
4921 /* If this operand is at most 32 bits, convert
4922 to a signed 32 bit number and don't use 64bit
4924 op_disp
&= (((offsetT
) 2 << 31) - 1);
4925 op_disp
= (op_disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
4926 i
.types
[op
].bitfield
.disp64
= 0;
4929 if (!op_disp
&& i
.types
[op
].bitfield
.baseindex
)
4931 i
.types
[op
].bitfield
.disp8
= 0;
4932 i
.types
[op
].bitfield
.disp16
= 0;
4933 i
.types
[op
].bitfield
.disp32
= 0;
4934 i
.types
[op
].bitfield
.disp32s
= 0;
4935 i
.types
[op
].bitfield
.disp64
= 0;
4939 else if (flag_code
== CODE_64BIT
)
4941 if (fits_in_signed_long (op_disp
))
4943 i
.types
[op
].bitfield
.disp64
= 0;
4944 i
.types
[op
].bitfield
.disp32s
= 1;
4946 if (i
.prefix
[ADDR_PREFIX
]
4947 && fits_in_unsigned_long (op_disp
))
4948 i
.types
[op
].bitfield
.disp32
= 1;
4950 if ((i
.types
[op
].bitfield
.disp32
4951 || i
.types
[op
].bitfield
.disp32s
4952 || i
.types
[op
].bitfield
.disp16
)
4953 && fits_in_disp8 (op_disp
))
4954 i
.types
[op
].bitfield
.disp8
= 1;
4956 else if (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
4957 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
)
4959 fix_new_exp (frag_now
, frag_more (0) - frag_now
->fr_literal
, 0,
4960 i
.op
[op
].disps
, 0, i
.reloc
[op
]);
4961 i
.types
[op
].bitfield
.disp8
= 0;
4962 i
.types
[op
].bitfield
.disp16
= 0;
4963 i
.types
[op
].bitfield
.disp32
= 0;
4964 i
.types
[op
].bitfield
.disp32s
= 0;
4965 i
.types
[op
].bitfield
.disp64
= 0;
4968 /* We only support 64bit displacement on constants. */
4969 i
.types
[op
].bitfield
.disp64
= 0;
4973 /* Check if operands are valid for the instruction. */
4976 check_VecOperands (const insn_template
*t
)
4980 static const i386_cpu_flags avx512
= CPU_ANY_AVX512F_FLAGS
;
4982 /* Templates allowing for ZMMword as well as YMMword and/or XMMword for
4983 any one operand are implicity requiring AVX512VL support if the actual
4984 operand size is YMMword or XMMword. Since this function runs after
4985 template matching, there's no need to check for YMMword/XMMword in
4987 cpu
= cpu_flags_and (t
->cpu_flags
, avx512
);
4988 if (!cpu_flags_all_zero (&cpu
)
4989 && !t
->cpu_flags
.bitfield
.cpuavx512vl
4990 && !cpu_arch_flags
.bitfield
.cpuavx512vl
)
4992 for (op
= 0; op
< t
->operands
; ++op
)
4994 if (t
->operand_types
[op
].bitfield
.zmmword
4995 && (i
.types
[op
].bitfield
.ymmword
4996 || i
.types
[op
].bitfield
.xmmword
))
4998 i
.error
= unsupported
;
5004 /* Without VSIB byte, we can't have a vector register for index. */
5005 if (!t
->opcode_modifier
.vecsib
5007 && (i
.index_reg
->reg_type
.bitfield
.xmmword
5008 || i
.index_reg
->reg_type
.bitfield
.ymmword
5009 || i
.index_reg
->reg_type
.bitfield
.zmmword
))
5011 i
.error
= unsupported_vector_index_register
;
5015 /* Check if default mask is allowed. */
5016 if (t
->opcode_modifier
.nodefmask
5017 && (!i
.mask
|| i
.mask
->mask
->reg_num
== 0))
5019 i
.error
= no_default_mask
;
5023 /* For VSIB byte, we need a vector register for index, and all vector
5024 registers must be distinct. */
5025 if (t
->opcode_modifier
.vecsib
)
5028 || !((t
->opcode_modifier
.vecsib
== VecSIB128
5029 && i
.index_reg
->reg_type
.bitfield
.xmmword
)
5030 || (t
->opcode_modifier
.vecsib
== VecSIB256
5031 && i
.index_reg
->reg_type
.bitfield
.ymmword
)
5032 || (t
->opcode_modifier
.vecsib
== VecSIB512
5033 && i
.index_reg
->reg_type
.bitfield
.zmmword
)))
5035 i
.error
= invalid_vsib_address
;
5039 gas_assert (i
.reg_operands
== 2 || i
.mask
);
5040 if (i
.reg_operands
== 2 && !i
.mask
)
5042 gas_assert (i
.types
[0].bitfield
.regsimd
);
5043 gas_assert (i
.types
[0].bitfield
.xmmword
5044 || i
.types
[0].bitfield
.ymmword
);
5045 gas_assert (i
.types
[2].bitfield
.regsimd
);
5046 gas_assert (i
.types
[2].bitfield
.xmmword
5047 || i
.types
[2].bitfield
.ymmword
);
5048 if (operand_check
== check_none
)
5050 if (register_number (i
.op
[0].regs
)
5051 != register_number (i
.index_reg
)
5052 && register_number (i
.op
[2].regs
)
5053 != register_number (i
.index_reg
)
5054 && register_number (i
.op
[0].regs
)
5055 != register_number (i
.op
[2].regs
))
5057 if (operand_check
== check_error
)
5059 i
.error
= invalid_vector_register_set
;
5062 as_warn (_("mask, index, and destination registers should be distinct"));
5064 else if (i
.reg_operands
== 1 && i
.mask
)
5066 if (i
.types
[1].bitfield
.regsimd
5067 && (i
.types
[1].bitfield
.xmmword
5068 || i
.types
[1].bitfield
.ymmword
5069 || i
.types
[1].bitfield
.zmmword
)
5070 && (register_number (i
.op
[1].regs
)
5071 == register_number (i
.index_reg
)))
5073 if (operand_check
== check_error
)
5075 i
.error
= invalid_vector_register_set
;
5078 if (operand_check
!= check_none
)
5079 as_warn (_("index and destination registers should be distinct"));
5084 /* Check if broadcast is supported by the instruction and is applied
5085 to the memory operand. */
5088 i386_operand_type type
, overlap
;
5090 /* Check if specified broadcast is supported in this instruction,
5091 and it's applied to memory operand of DWORD or QWORD type. */
5092 op
= i
.broadcast
->operand
;
5093 if (!t
->opcode_modifier
.broadcast
5094 || !i
.types
[op
].bitfield
.mem
5095 || (!i
.types
[op
].bitfield
.unspecified
5096 && (t
->operand_types
[op
].bitfield
.dword
5097 ? !i
.types
[op
].bitfield
.dword
5098 : !i
.types
[op
].bitfield
.qword
)))
5101 i
.error
= unsupported_broadcast
;
5105 operand_type_set (&type
, 0);
5106 switch ((t
->operand_types
[op
].bitfield
.dword
? 4 : 8) * i
.broadcast
->type
)
5109 type
.bitfield
.qword
= 1;
5112 type
.bitfield
.xmmword
= 1;
5115 type
.bitfield
.ymmword
= 1;
5118 type
.bitfield
.zmmword
= 1;
5124 overlap
= operand_type_and (type
, t
->operand_types
[op
]);
5125 if (operand_type_all_zero (&overlap
))
5128 if (t
->opcode_modifier
.checkregsize
)
5132 type
.bitfield
.baseindex
= 1;
5133 for (j
= 0; j
< i
.operands
; ++j
)
5136 && !operand_type_register_match(i
.types
[j
],
5137 t
->operand_types
[j
],
5139 t
->operand_types
[op
]))
5144 /* If broadcast is supported in this instruction, we need to check if
5145 operand of one-element size isn't specified without broadcast. */
5146 else if (t
->opcode_modifier
.broadcast
&& i
.mem_operands
)
5148 /* Find memory operand. */
5149 for (op
= 0; op
< i
.operands
; op
++)
5150 if (operand_type_check (i
.types
[op
], anymem
))
5152 gas_assert (op
< i
.operands
);
5153 /* Check size of the memory operand. */
5154 if (t
->operand_types
[op
].bitfield
.dword
5155 ? i
.types
[op
].bitfield
.dword
5156 : i
.types
[op
].bitfield
.qword
)
5158 i
.error
= broadcast_needed
;
5163 op
= MAX_OPERANDS
- 1; /* Avoid uninitialized variable warning. */
5165 /* Check if requested masking is supported. */
5167 && (!t
->opcode_modifier
.masking
5169 && t
->opcode_modifier
.masking
== MERGING_MASKING
)))
5171 i
.error
= unsupported_masking
;
5175 /* Check if masking is applied to dest operand. */
5176 if (i
.mask
&& (i
.mask
->operand
!= (int) (i
.operands
- 1)))
5178 i
.error
= mask_not_on_destination
;
5185 if ((i
.rounding
->type
!= saeonly
5186 && !t
->opcode_modifier
.staticrounding
)
5187 || (i
.rounding
->type
== saeonly
5188 && (t
->opcode_modifier
.staticrounding
5189 || !t
->opcode_modifier
.sae
)))
5191 i
.error
= unsupported_rc_sae
;
5194 /* If the instruction has several immediate operands and one of
5195 them is rounding, the rounding operand should be the last
5196 immediate operand. */
5197 if (i
.imm_operands
> 1
5198 && i
.rounding
->operand
!= (int) (i
.imm_operands
- 1))
5200 i
.error
= rc_sae_operand_not_last_imm
;
5205 /* Check vector Disp8 operand. */
5206 if (t
->opcode_modifier
.disp8memshift
5207 && i
.disp_encoding
!= disp_encoding_32bit
)
5210 i
.memshift
= t
->operand_types
[op
].bitfield
.dword
? 2 : 3;
5212 i
.memshift
= t
->opcode_modifier
.disp8memshift
;
5214 for (op
= 0; op
< i
.operands
; op
++)
5215 if (operand_type_check (i
.types
[op
], disp
)
5216 && i
.op
[op
].disps
->X_op
== O_constant
)
5218 if (fits_in_disp8 (i
.op
[op
].disps
->X_add_number
))
5220 i
.types
[op
].bitfield
.disp8
= 1;
5223 i
.types
[op
].bitfield
.disp8
= 0;
5232 /* Check if operands are valid for the instruction. Update VEX
5236 VEX_check_operands (const insn_template
*t
)
5238 if (i
.vec_encoding
== vex_encoding_evex
)
5240 /* This instruction must be encoded with EVEX prefix. */
5241 if (!is_evex_encoding (t
))
5243 i
.error
= unsupported
;
5249 if (!t
->opcode_modifier
.vex
)
5251 /* This instruction template doesn't have VEX prefix. */
5252 if (i
.vec_encoding
!= vex_encoding_default
)
5254 i
.error
= unsupported
;
5260 /* Only check VEX_Imm4, which must be the first operand. */
5261 if (t
->operand_types
[0].bitfield
.vec_imm4
)
5263 if (i
.op
[0].imms
->X_op
!= O_constant
5264 || !fits_in_imm4 (i
.op
[0].imms
->X_add_number
))
5270 /* Turn off Imm8 so that update_imm won't complain. */
5271 i
.types
[0] = vec_imm4
;
5277 static const insn_template
*
5278 match_template (char mnem_suffix
)
5280 /* Points to template once we've found it. */
5281 const insn_template
*t
;
5282 i386_operand_type overlap0
, overlap1
, overlap2
, overlap3
;
5283 i386_operand_type overlap4
;
5284 unsigned int found_reverse_match
;
5285 i386_opcode_modifier suffix_check
, mnemsuf_check
;
5286 i386_operand_type operand_types
[MAX_OPERANDS
];
5287 int addr_prefix_disp
;
5289 unsigned int found_cpu_match
;
5290 unsigned int check_register
;
5291 enum i386_error specific_error
= 0;
5293 #if MAX_OPERANDS != 5
5294 # error "MAX_OPERANDS must be 5."
5297 found_reverse_match
= 0;
5298 addr_prefix_disp
= -1;
5300 memset (&suffix_check
, 0, sizeof (suffix_check
));
5301 if (intel_syntax
&& i
.broadcast
)
5303 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
5304 suffix_check
.no_bsuf
= 1;
5305 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
5306 suffix_check
.no_wsuf
= 1;
5307 else if (i
.suffix
== SHORT_MNEM_SUFFIX
)
5308 suffix_check
.no_ssuf
= 1;
5309 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
5310 suffix_check
.no_lsuf
= 1;
5311 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
5312 suffix_check
.no_qsuf
= 1;
5313 else if (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
)
5314 suffix_check
.no_ldsuf
= 1;
5316 memset (&mnemsuf_check
, 0, sizeof (mnemsuf_check
));
5319 switch (mnem_suffix
)
5321 case BYTE_MNEM_SUFFIX
: mnemsuf_check
.no_bsuf
= 1; break;
5322 case WORD_MNEM_SUFFIX
: mnemsuf_check
.no_wsuf
= 1; break;
5323 case SHORT_MNEM_SUFFIX
: mnemsuf_check
.no_ssuf
= 1; break;
5324 case LONG_MNEM_SUFFIX
: mnemsuf_check
.no_lsuf
= 1; break;
5325 case QWORD_MNEM_SUFFIX
: mnemsuf_check
.no_qsuf
= 1; break;
5329 /* Must have right number of operands. */
5330 i
.error
= number_of_operands_mismatch
;
5332 for (t
= current_templates
->start
; t
< current_templates
->end
; t
++)
5334 addr_prefix_disp
= -1;
5336 if (i
.operands
!= t
->operands
)
5339 /* Check processor support. */
5340 i
.error
= unsupported
;
5341 found_cpu_match
= (cpu_flags_match (t
)
5342 == CPU_FLAGS_PERFECT_MATCH
);
5343 if (!found_cpu_match
)
5346 /* Check AT&T mnemonic. */
5347 i
.error
= unsupported_with_intel_mnemonic
;
5348 if (intel_mnemonic
&& t
->opcode_modifier
.attmnemonic
)
5351 /* Check AT&T/Intel syntax and Intel64/AMD64 ISA. */
5352 i
.error
= unsupported_syntax
;
5353 if ((intel_syntax
&& t
->opcode_modifier
.attsyntax
)
5354 || (!intel_syntax
&& t
->opcode_modifier
.intelsyntax
)
5355 || (intel64
&& t
->opcode_modifier
.amd64
)
5356 || (!intel64
&& t
->opcode_modifier
.intel64
))
5359 /* Check the suffix, except for some instructions in intel mode. */
5360 i
.error
= invalid_instruction_suffix
;
5361 if ((!intel_syntax
|| !t
->opcode_modifier
.ignoresize
)
5362 && ((t
->opcode_modifier
.no_bsuf
&& suffix_check
.no_bsuf
)
5363 || (t
->opcode_modifier
.no_wsuf
&& suffix_check
.no_wsuf
)
5364 || (t
->opcode_modifier
.no_lsuf
&& suffix_check
.no_lsuf
)
5365 || (t
->opcode_modifier
.no_ssuf
&& suffix_check
.no_ssuf
)
5366 || (t
->opcode_modifier
.no_qsuf
&& suffix_check
.no_qsuf
)
5367 || (t
->opcode_modifier
.no_ldsuf
&& suffix_check
.no_ldsuf
)))
5369 /* In Intel mode all mnemonic suffixes must be explicitly allowed. */
5370 if ((t
->opcode_modifier
.no_bsuf
&& mnemsuf_check
.no_bsuf
)
5371 || (t
->opcode_modifier
.no_wsuf
&& mnemsuf_check
.no_wsuf
)
5372 || (t
->opcode_modifier
.no_lsuf
&& mnemsuf_check
.no_lsuf
)
5373 || (t
->opcode_modifier
.no_ssuf
&& mnemsuf_check
.no_ssuf
)
5374 || (t
->opcode_modifier
.no_qsuf
&& mnemsuf_check
.no_qsuf
)
5375 || (t
->opcode_modifier
.no_ldsuf
&& mnemsuf_check
.no_ldsuf
))
5378 if (!operand_size_match (t
))
5381 for (j
= 0; j
< MAX_OPERANDS
; j
++)
5382 operand_types
[j
] = t
->operand_types
[j
];
5384 /* In general, don't allow 64-bit operands in 32-bit mode. */
5385 if (i
.suffix
== QWORD_MNEM_SUFFIX
5386 && flag_code
!= CODE_64BIT
5388 ? (!t
->opcode_modifier
.ignoresize
5389 && !intel_float_operand (t
->name
))
5390 : intel_float_operand (t
->name
) != 2)
5391 && ((!operand_types
[0].bitfield
.regmmx
5392 && !operand_types
[0].bitfield
.regsimd
)
5393 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
5394 && !operand_types
[t
->operands
> 1].bitfield
.regsimd
))
5395 && (t
->base_opcode
!= 0x0fc7
5396 || t
->extension_opcode
!= 1 /* cmpxchg8b */))
5399 /* In general, don't allow 32-bit operands on pre-386. */
5400 else if (i
.suffix
== LONG_MNEM_SUFFIX
5401 && !cpu_arch_flags
.bitfield
.cpui386
5403 ? (!t
->opcode_modifier
.ignoresize
5404 && !intel_float_operand (t
->name
))
5405 : intel_float_operand (t
->name
) != 2)
5406 && ((!operand_types
[0].bitfield
.regmmx
5407 && !operand_types
[0].bitfield
.regsimd
)
5408 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
5409 && !operand_types
[t
->operands
> 1].bitfield
.regsimd
)))
5412 /* Do not verify operands when there are none. */
5416 /* We've found a match; break out of loop. */
5420 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
5421 into Disp32/Disp16/Disp32 operand. */
5422 if (i
.prefix
[ADDR_PREFIX
] != 0)
5424 /* There should be only one Disp operand. */
5428 for (j
= 0; j
< MAX_OPERANDS
; j
++)
5430 if (operand_types
[j
].bitfield
.disp16
)
5432 addr_prefix_disp
= j
;
5433 operand_types
[j
].bitfield
.disp32
= 1;
5434 operand_types
[j
].bitfield
.disp16
= 0;
5440 for (j
= 0; j
< MAX_OPERANDS
; j
++)
5442 if (operand_types
[j
].bitfield
.disp32
)
5444 addr_prefix_disp
= j
;
5445 operand_types
[j
].bitfield
.disp32
= 0;
5446 operand_types
[j
].bitfield
.disp16
= 1;
5452 for (j
= 0; j
< MAX_OPERANDS
; j
++)
5454 if (operand_types
[j
].bitfield
.disp64
)
5456 addr_prefix_disp
= j
;
5457 operand_types
[j
].bitfield
.disp64
= 0;
5458 operand_types
[j
].bitfield
.disp32
= 1;
5466 /* Force 0x8b encoding for "mov foo@GOT, %eax". */
5467 if (i
.reloc
[0] == BFD_RELOC_386_GOT32
&& t
->base_opcode
== 0xa0)
5470 /* We check register size if needed. */
5471 if (t
->opcode_modifier
.checkregsize
)
5473 check_register
= (1 << t
->operands
) - 1;
5475 check_register
&= ~(1 << i
.broadcast
->operand
);
5480 overlap0
= operand_type_and (i
.types
[0], operand_types
[0]);
5481 switch (t
->operands
)
5484 if (!operand_type_match (overlap0
, i
.types
[0]))
5488 /* xchg %eax, %eax is a special case. It is an alias for nop
5489 only in 32bit mode and we can use opcode 0x90. In 64bit
5490 mode, we can't use 0x90 for xchg %eax, %eax since it should
5491 zero-extend %eax to %rax. */
5492 if (flag_code
== CODE_64BIT
5493 && t
->base_opcode
== 0x90
5494 && operand_type_equal (&i
.types
[0], &acc32
)
5495 && operand_type_equal (&i
.types
[1], &acc32
))
5497 /* xrelease mov %eax, <disp> is another special case. It must not
5498 match the accumulator-only encoding of mov. */
5499 if (flag_code
!= CODE_64BIT
5501 && t
->base_opcode
== 0xa0
5502 && i
.types
[0].bitfield
.acc
5503 && operand_type_check (i
.types
[1], anymem
))
5505 /* If we want store form, we reverse direction of operands. */
5506 if (i
.dir_encoding
== dir_encoding_store
5507 && t
->opcode_modifier
.d
)
5512 /* If we want store form, we skip the current load. */
5513 if (i
.dir_encoding
== dir_encoding_store
5514 && i
.mem_operands
== 0
5515 && t
->opcode_modifier
.load
)
5520 overlap1
= operand_type_and (i
.types
[1], operand_types
[1]);
5521 if (!operand_type_match (overlap0
, i
.types
[0])
5522 || !operand_type_match (overlap1
, i
.types
[1])
5523 || ((check_register
& 3) == 3
5524 && !operand_type_register_match (i
.types
[0],
5529 /* Check if other direction is valid ... */
5530 if (!t
->opcode_modifier
.d
)
5534 /* Try reversing direction of operands. */
5535 overlap0
= operand_type_and (i
.types
[0], operand_types
[1]);
5536 overlap1
= operand_type_and (i
.types
[1], operand_types
[0]);
5537 if (!operand_type_match (overlap0
, i
.types
[0])
5538 || !operand_type_match (overlap1
, i
.types
[1])
5540 && !operand_type_register_match (i
.types
[0],
5545 /* Does not match either direction. */
5548 /* found_reverse_match holds which of D or FloatR
5550 if (!t
->opcode_modifier
.d
)
5551 found_reverse_match
= 0;
5552 else if (operand_types
[0].bitfield
.tbyte
)
5553 found_reverse_match
= Opcode_FloatD
;
5555 found_reverse_match
= Opcode_D
;
5556 if (t
->opcode_modifier
.floatr
)
5557 found_reverse_match
|= Opcode_FloatR
;
5561 /* Found a forward 2 operand match here. */
5562 switch (t
->operands
)
5565 overlap4
= operand_type_and (i
.types
[4],
5569 overlap3
= operand_type_and (i
.types
[3],
5573 overlap2
= operand_type_and (i
.types
[2],
5578 switch (t
->operands
)
5581 if (!operand_type_match (overlap4
, i
.types
[4])
5582 || !operand_type_register_match (i
.types
[3],
5589 if (!operand_type_match (overlap3
, i
.types
[3])
5590 || ((check_register
& 0xa) == 0xa
5591 && !operand_type_register_match (i
.types
[1],
5595 || ((check_register
& 0xc) == 0xc
5596 && !operand_type_register_match (i
.types
[2],
5603 /* Here we make use of the fact that there are no
5604 reverse match 3 operand instructions. */
5605 if (!operand_type_match (overlap2
, i
.types
[2])
5606 || ((check_register
& 5) == 5
5607 && !operand_type_register_match (i
.types
[0],
5611 || ((check_register
& 6) == 6
5612 && !operand_type_register_match (i
.types
[1],
5620 /* Found either forward/reverse 2, 3 or 4 operand match here:
5621 slip through to break. */
5623 if (!found_cpu_match
)
5625 found_reverse_match
= 0;
5629 /* Check if vector and VEX operands are valid. */
5630 if (check_VecOperands (t
) || VEX_check_operands (t
))
5632 specific_error
= i
.error
;
5636 /* We've found a match; break out of loop. */
5640 if (t
== current_templates
->end
)
5642 /* We found no match. */
5643 const char *err_msg
;
5644 switch (specific_error
? specific_error
: i
.error
)
5648 case operand_size_mismatch
:
5649 err_msg
= _("operand size mismatch");
5651 case operand_type_mismatch
:
5652 err_msg
= _("operand type mismatch");
5654 case register_type_mismatch
:
5655 err_msg
= _("register type mismatch");
5657 case number_of_operands_mismatch
:
5658 err_msg
= _("number of operands mismatch");
5660 case invalid_instruction_suffix
:
5661 err_msg
= _("invalid instruction suffix");
5664 err_msg
= _("constant doesn't fit in 4 bits");
5666 case unsupported_with_intel_mnemonic
:
5667 err_msg
= _("unsupported with Intel mnemonic");
5669 case unsupported_syntax
:
5670 err_msg
= _("unsupported syntax");
5673 as_bad (_("unsupported instruction `%s'"),
5674 current_templates
->start
->name
);
5676 case invalid_vsib_address
:
5677 err_msg
= _("invalid VSIB address");
5679 case invalid_vector_register_set
:
5680 err_msg
= _("mask, index, and destination registers must be distinct");
5682 case unsupported_vector_index_register
:
5683 err_msg
= _("unsupported vector index register");
5685 case unsupported_broadcast
:
5686 err_msg
= _("unsupported broadcast");
5688 case broadcast_not_on_src_operand
:
5689 err_msg
= _("broadcast not on source memory operand");
5691 case broadcast_needed
:
5692 err_msg
= _("broadcast is needed for operand of such type");
5694 case unsupported_masking
:
5695 err_msg
= _("unsupported masking");
5697 case mask_not_on_destination
:
5698 err_msg
= _("mask not on destination operand");
5700 case no_default_mask
:
5701 err_msg
= _("default mask isn't allowed");
5703 case unsupported_rc_sae
:
5704 err_msg
= _("unsupported static rounding/sae");
5706 case rc_sae_operand_not_last_imm
:
5708 err_msg
= _("RC/SAE operand must precede immediate operands");
5710 err_msg
= _("RC/SAE operand must follow immediate operands");
5712 case invalid_register_operand
:
5713 err_msg
= _("invalid register operand");
5716 as_bad (_("%s for `%s'"), err_msg
,
5717 current_templates
->start
->name
);
5721 if (!quiet_warnings
)
5724 && (i
.types
[0].bitfield
.jumpabsolute
5725 != operand_types
[0].bitfield
.jumpabsolute
))
5727 as_warn (_("indirect %s without `*'"), t
->name
);
5730 if (t
->opcode_modifier
.isprefix
5731 && t
->opcode_modifier
.ignoresize
)
5733 /* Warn them that a data or address size prefix doesn't
5734 affect assembly of the next line of code. */
5735 as_warn (_("stand-alone `%s' prefix"), t
->name
);
5739 /* Copy the template we found. */
5742 if (addr_prefix_disp
!= -1)
5743 i
.tm
.operand_types
[addr_prefix_disp
]
5744 = operand_types
[addr_prefix_disp
];
5746 if (found_reverse_match
)
5748 /* If we found a reverse match we must alter the opcode
5749 direction bit. found_reverse_match holds bits to change
5750 (different for int & float insns). */
5752 i
.tm
.base_opcode
^= found_reverse_match
;
5754 i
.tm
.operand_types
[0] = operand_types
[1];
5755 i
.tm
.operand_types
[1] = operand_types
[0];
5764 int mem_op
= operand_type_check (i
.types
[0], anymem
) ? 0 : 1;
5765 if (i
.tm
.operand_types
[mem_op
].bitfield
.esseg
)
5767 if (i
.seg
[0] != NULL
&& i
.seg
[0] != &es
)
5769 as_bad (_("`%s' operand %d must use `%ses' segment"),
5775 /* There's only ever one segment override allowed per instruction.
5776 This instruction possibly has a legal segment override on the
5777 second operand, so copy the segment to where non-string
5778 instructions store it, allowing common code. */
5779 i
.seg
[0] = i
.seg
[1];
5781 else if (i
.tm
.operand_types
[mem_op
+ 1].bitfield
.esseg
)
5783 if (i
.seg
[1] != NULL
&& i
.seg
[1] != &es
)
5785 as_bad (_("`%s' operand %d must use `%ses' segment"),
5796 process_suffix (void)
5798 /* If matched instruction specifies an explicit instruction mnemonic
5800 if (i
.tm
.opcode_modifier
.size16
)
5801 i
.suffix
= WORD_MNEM_SUFFIX
;
5802 else if (i
.tm
.opcode_modifier
.size32
)
5803 i
.suffix
= LONG_MNEM_SUFFIX
;
5804 else if (i
.tm
.opcode_modifier
.size64
)
5805 i
.suffix
= QWORD_MNEM_SUFFIX
;
5806 else if (i
.reg_operands
)
5808 /* If there's no instruction mnemonic suffix we try to invent one
5809 based on register operands. */
5812 /* We take i.suffix from the last register operand specified,
5813 Destination register type is more significant than source
5814 register type. crc32 in SSE4.2 prefers source register
5816 if (i
.tm
.base_opcode
== 0xf20f38f1)
5818 if (i
.types
[0].bitfield
.reg
&& i
.types
[0].bitfield
.word
)
5819 i
.suffix
= WORD_MNEM_SUFFIX
;
5820 else if (i
.types
[0].bitfield
.reg
&& i
.types
[0].bitfield
.dword
)
5821 i
.suffix
= LONG_MNEM_SUFFIX
;
5822 else if (i
.types
[0].bitfield
.reg
&& i
.types
[0].bitfield
.qword
)
5823 i
.suffix
= QWORD_MNEM_SUFFIX
;
5825 else if (i
.tm
.base_opcode
== 0xf20f38f0)
5827 if (i
.types
[0].bitfield
.reg
&& i
.types
[0].bitfield
.byte
)
5828 i
.suffix
= BYTE_MNEM_SUFFIX
;
5835 if (i
.tm
.base_opcode
== 0xf20f38f1
5836 || i
.tm
.base_opcode
== 0xf20f38f0)
5838 /* We have to know the operand size for crc32. */
5839 as_bad (_("ambiguous memory operand size for `%s`"),
5844 for (op
= i
.operands
; --op
>= 0;)
5845 if (!i
.tm
.operand_types
[op
].bitfield
.inoutportreg
5846 && !i
.tm
.operand_types
[op
].bitfield
.shiftcount
)
5848 if (!i
.types
[op
].bitfield
.reg
)
5850 if (i
.types
[op
].bitfield
.byte
)
5851 i
.suffix
= BYTE_MNEM_SUFFIX
;
5852 else if (i
.types
[op
].bitfield
.word
)
5853 i
.suffix
= WORD_MNEM_SUFFIX
;
5854 else if (i
.types
[op
].bitfield
.dword
)
5855 i
.suffix
= LONG_MNEM_SUFFIX
;
5856 else if (i
.types
[op
].bitfield
.qword
)
5857 i
.suffix
= QWORD_MNEM_SUFFIX
;
5864 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
5867 && i
.tm
.opcode_modifier
.ignoresize
5868 && i
.tm
.opcode_modifier
.no_bsuf
)
5870 else if (!check_byte_reg ())
5873 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
5876 && i
.tm
.opcode_modifier
.ignoresize
5877 && i
.tm
.opcode_modifier
.no_lsuf
5878 && !i
.tm
.opcode_modifier
.todword
5879 && !i
.tm
.opcode_modifier
.toqword
)
5881 else if (!check_long_reg ())
5884 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
5887 && i
.tm
.opcode_modifier
.ignoresize
5888 && i
.tm
.opcode_modifier
.no_qsuf
5889 && !i
.tm
.opcode_modifier
.todword
5890 && !i
.tm
.opcode_modifier
.toqword
)
5892 else if (!check_qword_reg ())
5895 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
5898 && i
.tm
.opcode_modifier
.ignoresize
5899 && i
.tm
.opcode_modifier
.no_wsuf
)
5901 else if (!check_word_reg ())
5904 else if (intel_syntax
&& i
.tm
.opcode_modifier
.ignoresize
)
5905 /* Do nothing if the instruction is going to ignore the prefix. */
5910 else if (i
.tm
.opcode_modifier
.defaultsize
5912 /* exclude fldenv/frstor/fsave/fstenv */
5913 && i
.tm
.opcode_modifier
.no_ssuf
)
5915 i
.suffix
= stackop_size
;
5917 else if (intel_syntax
5919 && (i
.tm
.operand_types
[0].bitfield
.jumpabsolute
5920 || i
.tm
.opcode_modifier
.jumpbyte
5921 || i
.tm
.opcode_modifier
.jumpintersegment
5922 || (i
.tm
.base_opcode
== 0x0f01 /* [ls][gi]dt */
5923 && i
.tm
.extension_opcode
<= 3)))
5928 if (!i
.tm
.opcode_modifier
.no_qsuf
)
5930 i
.suffix
= QWORD_MNEM_SUFFIX
;
5935 if (!i
.tm
.opcode_modifier
.no_lsuf
)
5936 i
.suffix
= LONG_MNEM_SUFFIX
;
5939 if (!i
.tm
.opcode_modifier
.no_wsuf
)
5940 i
.suffix
= WORD_MNEM_SUFFIX
;
5949 if (i
.tm
.opcode_modifier
.w
)
5951 as_bad (_("no instruction mnemonic suffix given and "
5952 "no register operands; can't size instruction"));
5958 unsigned int suffixes
;
5960 suffixes
= !i
.tm
.opcode_modifier
.no_bsuf
;
5961 if (!i
.tm
.opcode_modifier
.no_wsuf
)
5963 if (!i
.tm
.opcode_modifier
.no_lsuf
)
5965 if (!i
.tm
.opcode_modifier
.no_ldsuf
)
5967 if (!i
.tm
.opcode_modifier
.no_ssuf
)
5969 if (flag_code
== CODE_64BIT
&& !i
.tm
.opcode_modifier
.no_qsuf
)
5972 /* There are more than suffix matches. */
5973 if (i
.tm
.opcode_modifier
.w
5974 || ((suffixes
& (suffixes
- 1))
5975 && !i
.tm
.opcode_modifier
.defaultsize
5976 && !i
.tm
.opcode_modifier
.ignoresize
))
5978 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
5984 /* Change the opcode based on the operand size given by i.suffix. */
5987 /* Size floating point instruction. */
5988 case LONG_MNEM_SUFFIX
:
5989 if (i
.tm
.opcode_modifier
.floatmf
)
5991 i
.tm
.base_opcode
^= 4;
5995 case WORD_MNEM_SUFFIX
:
5996 case QWORD_MNEM_SUFFIX
:
5997 /* It's not a byte, select word/dword operation. */
5998 if (i
.tm
.opcode_modifier
.w
)
6000 if (i
.tm
.opcode_modifier
.shortform
)
6001 i
.tm
.base_opcode
|= 8;
6003 i
.tm
.base_opcode
|= 1;
6006 case SHORT_MNEM_SUFFIX
:
6007 /* Now select between word & dword operations via the operand
6008 size prefix, except for instructions that will ignore this
6010 if (i
.reg_operands
> 0
6011 && i
.types
[0].bitfield
.reg
6012 && i
.tm
.opcode_modifier
.addrprefixopreg
6013 && (i
.tm
.opcode_modifier
.immext
6014 || i
.operands
== 1))
6016 /* The address size override prefix changes the size of the
6018 if ((flag_code
== CODE_32BIT
6019 && i
.op
[0].regs
->reg_type
.bitfield
.word
)
6020 || (flag_code
!= CODE_32BIT
6021 && i
.op
[0].regs
->reg_type
.bitfield
.dword
))
6022 if (!add_prefix (ADDR_PREFIX_OPCODE
))
6025 else if (i
.suffix
!= QWORD_MNEM_SUFFIX
6026 && !i
.tm
.opcode_modifier
.ignoresize
6027 && !i
.tm
.opcode_modifier
.floatmf
6028 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
6029 || (flag_code
== CODE_64BIT
6030 && i
.tm
.opcode_modifier
.jumpbyte
)))
6032 unsigned int prefix
= DATA_PREFIX_OPCODE
;
6034 if (i
.tm
.opcode_modifier
.jumpbyte
) /* jcxz, loop */
6035 prefix
= ADDR_PREFIX_OPCODE
;
6037 if (!add_prefix (prefix
))
6041 /* Set mode64 for an operand. */
6042 if (i
.suffix
== QWORD_MNEM_SUFFIX
6043 && flag_code
== CODE_64BIT
6044 && !i
.tm
.opcode_modifier
.norex64
6045 /* Special case for xchg %rax,%rax. It is NOP and doesn't
6047 && ! (i
.operands
== 2
6048 && i
.tm
.base_opcode
== 0x90
6049 && i
.tm
.extension_opcode
== None
6050 && operand_type_equal (&i
.types
[0], &acc64
)
6051 && operand_type_equal (&i
.types
[1], &acc64
)))
6057 if (i
.reg_operands
!= 0
6059 && i
.tm
.opcode_modifier
.addrprefixopreg
6060 && !i
.tm
.opcode_modifier
.immext
)
6062 /* Check invalid register operand when the address size override
6063 prefix changes the size of register operands. */
6065 enum { need_word
, need_dword
, need_qword
} need
;
6067 if (flag_code
== CODE_32BIT
)
6068 need
= i
.prefix
[ADDR_PREFIX
] ? need_word
: need_dword
;
6071 if (i
.prefix
[ADDR_PREFIX
])
6074 need
= flag_code
== CODE_64BIT
? need_qword
: need_word
;
6077 for (op
= 0; op
< i
.operands
; op
++)
6078 if (i
.types
[op
].bitfield
.reg
6079 && ((need
== need_word
6080 && !i
.op
[op
].regs
->reg_type
.bitfield
.word
)
6081 || (need
== need_dword
6082 && !i
.op
[op
].regs
->reg_type
.bitfield
.dword
)
6083 || (need
== need_qword
6084 && !i
.op
[op
].regs
->reg_type
.bitfield
.qword
)))
6086 as_bad (_("invalid register operand size for `%s'"),
6096 check_byte_reg (void)
6100 for (op
= i
.operands
; --op
>= 0;)
6102 /* Skip non-register operands. */
6103 if (!i
.types
[op
].bitfield
.reg
)
6106 /* If this is an eight bit register, it's OK. If it's the 16 or
6107 32 bit version of an eight bit register, we will just use the
6108 low portion, and that's OK too. */
6109 if (i
.types
[op
].bitfield
.byte
)
6112 /* I/O port address operands are OK too. */
6113 if (i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
6116 /* crc32 doesn't generate this warning. */
6117 if (i
.tm
.base_opcode
== 0xf20f38f0)
6120 if ((i
.types
[op
].bitfield
.word
6121 || i
.types
[op
].bitfield
.dword
6122 || i
.types
[op
].bitfield
.qword
)
6123 && i
.op
[op
].regs
->reg_num
< 4
6124 /* Prohibit these changes in 64bit mode, since the lowering
6125 would be more complicated. */
6126 && flag_code
!= CODE_64BIT
)
6128 #if REGISTER_WARNINGS
6129 if (!quiet_warnings
)
6130 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6132 (i
.op
[op
].regs
+ (i
.types
[op
].bitfield
.word
6133 ? REGNAM_AL
- REGNAM_AX
6134 : REGNAM_AL
- REGNAM_EAX
))->reg_name
,
6136 i
.op
[op
].regs
->reg_name
,
6141 /* Any other register is bad. */
6142 if (i
.types
[op
].bitfield
.reg
6143 || i
.types
[op
].bitfield
.regmmx
6144 || i
.types
[op
].bitfield
.regsimd
6145 || i
.types
[op
].bitfield
.sreg2
6146 || i
.types
[op
].bitfield
.sreg3
6147 || i
.types
[op
].bitfield
.control
6148 || i
.types
[op
].bitfield
.debug
6149 || i
.types
[op
].bitfield
.test
)
6151 as_bad (_("`%s%s' not allowed with `%s%c'"),
6153 i
.op
[op
].regs
->reg_name
,
6163 check_long_reg (void)
6167 for (op
= i
.operands
; --op
>= 0;)
6168 /* Skip non-register operands. */
6169 if (!i
.types
[op
].bitfield
.reg
)
6171 /* Reject eight bit registers, except where the template requires
6172 them. (eg. movzb) */
6173 else if (i
.types
[op
].bitfield
.byte
6174 && (i
.tm
.operand_types
[op
].bitfield
.reg
6175 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6176 && (i
.tm
.operand_types
[op
].bitfield
.word
6177 || i
.tm
.operand_types
[op
].bitfield
.dword
))
6179 as_bad (_("`%s%s' not allowed with `%s%c'"),
6181 i
.op
[op
].regs
->reg_name
,
6186 /* Warn if the e prefix on a general reg is missing. */
6187 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
6188 && i
.types
[op
].bitfield
.word
6189 && (i
.tm
.operand_types
[op
].bitfield
.reg
6190 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6191 && i
.tm
.operand_types
[op
].bitfield
.dword
)
6193 /* Prohibit these changes in the 64bit mode, since the
6194 lowering is more complicated. */
6195 if (flag_code
== CODE_64BIT
)
6197 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6198 register_prefix
, i
.op
[op
].regs
->reg_name
,
6202 #if REGISTER_WARNINGS
6203 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6205 (i
.op
[op
].regs
+ REGNAM_EAX
- REGNAM_AX
)->reg_name
,
6206 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
6209 /* Warn if the r prefix on a general reg is present. */
6210 else if (i
.types
[op
].bitfield
.qword
6211 && (i
.tm
.operand_types
[op
].bitfield
.reg
6212 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6213 && i
.tm
.operand_types
[op
].bitfield
.dword
)
6216 && i
.tm
.opcode_modifier
.toqword
6217 && !i
.types
[0].bitfield
.regsimd
)
6219 /* Convert to QWORD. We want REX byte. */
6220 i
.suffix
= QWORD_MNEM_SUFFIX
;
6224 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6225 register_prefix
, i
.op
[op
].regs
->reg_name
,
6234 check_qword_reg (void)
6238 for (op
= i
.operands
; --op
>= 0; )
6239 /* Skip non-register operands. */
6240 if (!i
.types
[op
].bitfield
.reg
)
6242 /* Reject eight bit registers, except where the template requires
6243 them. (eg. movzb) */
6244 else if (i
.types
[op
].bitfield
.byte
6245 && (i
.tm
.operand_types
[op
].bitfield
.reg
6246 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6247 && (i
.tm
.operand_types
[op
].bitfield
.word
6248 || i
.tm
.operand_types
[op
].bitfield
.dword
))
6250 as_bad (_("`%s%s' not allowed with `%s%c'"),
6252 i
.op
[op
].regs
->reg_name
,
6257 /* Warn if the r prefix on a general reg is missing. */
6258 else if ((i
.types
[op
].bitfield
.word
6259 || i
.types
[op
].bitfield
.dword
)
6260 && (i
.tm
.operand_types
[op
].bitfield
.reg
6261 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6262 && i
.tm
.operand_types
[op
].bitfield
.qword
)
6264 /* Prohibit these changes in the 64bit mode, since the
6265 lowering is more complicated. */
6267 && i
.tm
.opcode_modifier
.todword
6268 && !i
.types
[0].bitfield
.regsimd
)
6270 /* Convert to DWORD. We don't want REX byte. */
6271 i
.suffix
= LONG_MNEM_SUFFIX
;
6275 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6276 register_prefix
, i
.op
[op
].regs
->reg_name
,
6285 check_word_reg (void)
6288 for (op
= i
.operands
; --op
>= 0;)
6289 /* Skip non-register operands. */
6290 if (!i
.types
[op
].bitfield
.reg
)
6292 /* Reject eight bit registers, except where the template requires
6293 them. (eg. movzb) */
6294 else if (i
.types
[op
].bitfield
.byte
6295 && (i
.tm
.operand_types
[op
].bitfield
.reg
6296 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6297 && (i
.tm
.operand_types
[op
].bitfield
.word
6298 || i
.tm
.operand_types
[op
].bitfield
.dword
))
6300 as_bad (_("`%s%s' not allowed with `%s%c'"),
6302 i
.op
[op
].regs
->reg_name
,
6307 /* Warn if the e or r prefix on a general reg is present. */
6308 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
6309 && (i
.types
[op
].bitfield
.dword
6310 || i
.types
[op
].bitfield
.qword
)
6311 && (i
.tm
.operand_types
[op
].bitfield
.reg
6312 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6313 && i
.tm
.operand_types
[op
].bitfield
.word
)
6315 /* Prohibit these changes in the 64bit mode, since the
6316 lowering is more complicated. */
6317 if (flag_code
== CODE_64BIT
)
6319 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6320 register_prefix
, i
.op
[op
].regs
->reg_name
,
6324 #if REGISTER_WARNINGS
6325 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6327 (i
.op
[op
].regs
+ REGNAM_AX
- REGNAM_EAX
)->reg_name
,
6328 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
6335 update_imm (unsigned int j
)
6337 i386_operand_type overlap
= i
.types
[j
];
6338 if ((overlap
.bitfield
.imm8
6339 || overlap
.bitfield
.imm8s
6340 || overlap
.bitfield
.imm16
6341 || overlap
.bitfield
.imm32
6342 || overlap
.bitfield
.imm32s
6343 || overlap
.bitfield
.imm64
)
6344 && !operand_type_equal (&overlap
, &imm8
)
6345 && !operand_type_equal (&overlap
, &imm8s
)
6346 && !operand_type_equal (&overlap
, &imm16
)
6347 && !operand_type_equal (&overlap
, &imm32
)
6348 && !operand_type_equal (&overlap
, &imm32s
)
6349 && !operand_type_equal (&overlap
, &imm64
))
6353 i386_operand_type temp
;
6355 operand_type_set (&temp
, 0);
6356 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
6358 temp
.bitfield
.imm8
= overlap
.bitfield
.imm8
;
6359 temp
.bitfield
.imm8s
= overlap
.bitfield
.imm8s
;
6361 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
6362 temp
.bitfield
.imm16
= overlap
.bitfield
.imm16
;
6363 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
6365 temp
.bitfield
.imm64
= overlap
.bitfield
.imm64
;
6366 temp
.bitfield
.imm32s
= overlap
.bitfield
.imm32s
;
6369 temp
.bitfield
.imm32
= overlap
.bitfield
.imm32
;
6372 else if (operand_type_equal (&overlap
, &imm16_32_32s
)
6373 || operand_type_equal (&overlap
, &imm16_32
)
6374 || operand_type_equal (&overlap
, &imm16_32s
))
6376 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
6381 if (!operand_type_equal (&overlap
, &imm8
)
6382 && !operand_type_equal (&overlap
, &imm8s
)
6383 && !operand_type_equal (&overlap
, &imm16
)
6384 && !operand_type_equal (&overlap
, &imm32
)
6385 && !operand_type_equal (&overlap
, &imm32s
)
6386 && !operand_type_equal (&overlap
, &imm64
))
6388 as_bad (_("no instruction mnemonic suffix given; "
6389 "can't determine immediate size"));
6393 i
.types
[j
] = overlap
;
6403 /* Update the first 2 immediate operands. */
6404 n
= i
.operands
> 2 ? 2 : i
.operands
;
6407 for (j
= 0; j
< n
; j
++)
6408 if (update_imm (j
) == 0)
6411 /* The 3rd operand can't be immediate operand. */
6412 gas_assert (operand_type_check (i
.types
[2], imm
) == 0);
6419 process_operands (void)
6421 /* Default segment register this instruction will use for memory
6422 accesses. 0 means unknown. This is only for optimizing out
6423 unnecessary segment overrides. */
6424 const seg_entry
*default_seg
= 0;
6426 if (i
.tm
.opcode_modifier
.sse2avx
&& i
.tm
.opcode_modifier
.vexvvvv
)
6428 unsigned int dupl
= i
.operands
;
6429 unsigned int dest
= dupl
- 1;
6432 /* The destination must be an xmm register. */
6433 gas_assert (i
.reg_operands
6434 && MAX_OPERANDS
> dupl
6435 && operand_type_equal (&i
.types
[dest
], ®xmm
));
6437 if (i
.tm
.operand_types
[0].bitfield
.acc
6438 && i
.tm
.operand_types
[0].bitfield
.xmmword
)
6440 if (i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
)
6442 /* Keep xmm0 for instructions with VEX prefix and 3
6444 i
.tm
.operand_types
[0].bitfield
.acc
= 0;
6445 i
.tm
.operand_types
[0].bitfield
.regsimd
= 1;
6450 /* We remove the first xmm0 and keep the number of
6451 operands unchanged, which in fact duplicates the
6453 for (j
= 1; j
< i
.operands
; j
++)
6455 i
.op
[j
- 1] = i
.op
[j
];
6456 i
.types
[j
- 1] = i
.types
[j
];
6457 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
6461 else if (i
.tm
.opcode_modifier
.implicit1stxmm0
)
6463 gas_assert ((MAX_OPERANDS
- 1) > dupl
6464 && (i
.tm
.opcode_modifier
.vexsources
6467 /* Add the implicit xmm0 for instructions with VEX prefix
6469 for (j
= i
.operands
; j
> 0; j
--)
6471 i
.op
[j
] = i
.op
[j
- 1];
6472 i
.types
[j
] = i
.types
[j
- 1];
6473 i
.tm
.operand_types
[j
] = i
.tm
.operand_types
[j
- 1];
6476 = (const reg_entry
*) hash_find (reg_hash
, "xmm0");
6477 i
.types
[0] = regxmm
;
6478 i
.tm
.operand_types
[0] = regxmm
;
6481 i
.reg_operands
+= 2;
6486 i
.op
[dupl
] = i
.op
[dest
];
6487 i
.types
[dupl
] = i
.types
[dest
];
6488 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
6497 i
.op
[dupl
] = i
.op
[dest
];
6498 i
.types
[dupl
] = i
.types
[dest
];
6499 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
6502 if (i
.tm
.opcode_modifier
.immext
)
6505 else if (i
.tm
.operand_types
[0].bitfield
.acc
6506 && i
.tm
.operand_types
[0].bitfield
.xmmword
)
6510 for (j
= 1; j
< i
.operands
; j
++)
6512 i
.op
[j
- 1] = i
.op
[j
];
6513 i
.types
[j
- 1] = i
.types
[j
];
6515 /* We need to adjust fields in i.tm since they are used by
6516 build_modrm_byte. */
6517 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
6524 else if (i
.tm
.opcode_modifier
.implicitquadgroup
)
6526 unsigned int regnum
, first_reg_in_group
, last_reg_in_group
;
6528 /* The second operand must be {x,y,z}mmN, where N is a multiple of 4. */
6529 gas_assert (i
.operands
>= 2 && i
.types
[1].bitfield
.regsimd
);
6530 regnum
= register_number (i
.op
[1].regs
);
6531 first_reg_in_group
= regnum
& ~3;
6532 last_reg_in_group
= first_reg_in_group
+ 3;
6533 if (regnum
!= first_reg_in_group
)
6534 as_warn (_("source register `%s%s' implicitly denotes"
6535 " `%s%.3s%u' to `%s%.3s%u' source group in `%s'"),
6536 register_prefix
, i
.op
[1].regs
->reg_name
,
6537 register_prefix
, i
.op
[1].regs
->reg_name
, first_reg_in_group
,
6538 register_prefix
, i
.op
[1].regs
->reg_name
, last_reg_in_group
,
6541 else if (i
.tm
.opcode_modifier
.regkludge
)
6543 /* The imul $imm, %reg instruction is converted into
6544 imul $imm, %reg, %reg, and the clr %reg instruction
6545 is converted into xor %reg, %reg. */
6547 unsigned int first_reg_op
;
6549 if (operand_type_check (i
.types
[0], reg
))
6553 /* Pretend we saw the extra register operand. */
6554 gas_assert (i
.reg_operands
== 1
6555 && i
.op
[first_reg_op
+ 1].regs
== 0);
6556 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
6557 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
6562 if (i
.tm
.opcode_modifier
.shortform
)
6564 if (i
.types
[0].bitfield
.sreg2
6565 || i
.types
[0].bitfield
.sreg3
)
6567 if (i
.tm
.base_opcode
== POP_SEG_SHORT
6568 && i
.op
[0].regs
->reg_num
== 1)
6570 as_bad (_("you can't `pop %scs'"), register_prefix
);
6573 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
6574 if ((i
.op
[0].regs
->reg_flags
& RegRex
) != 0)
6579 /* The register or float register operand is in operand
6583 if ((i
.types
[0].bitfield
.reg
&& i
.types
[0].bitfield
.tbyte
)
6584 || operand_type_check (i
.types
[0], reg
))
6588 /* Register goes in low 3 bits of opcode. */
6589 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
6590 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
6592 if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
6594 /* Warn about some common errors, but press on regardless.
6595 The first case can be generated by gcc (<= 2.8.1). */
6596 if (i
.operands
== 2)
6598 /* Reversed arguments on faddp, fsubp, etc. */
6599 as_warn (_("translating to `%s %s%s,%s%s'"), i
.tm
.name
,
6600 register_prefix
, i
.op
[!intel_syntax
].regs
->reg_name
,
6601 register_prefix
, i
.op
[intel_syntax
].regs
->reg_name
);
6605 /* Extraneous `l' suffix on fp insn. */
6606 as_warn (_("translating to `%s %s%s'"), i
.tm
.name
,
6607 register_prefix
, i
.op
[0].regs
->reg_name
);
6612 else if (i
.tm
.opcode_modifier
.modrm
)
6614 /* The opcode is completed (modulo i.tm.extension_opcode which
6615 must be put into the modrm byte). Now, we make the modrm and
6616 index base bytes based on all the info we've collected. */
6618 default_seg
= build_modrm_byte ();
6620 else if ((i
.tm
.base_opcode
& ~0x3) == MOV_AX_DISP32
)
6624 else if (i
.tm
.opcode_modifier
.isstring
)
6626 /* For the string instructions that allow a segment override
6627 on one of their operands, the default segment is ds. */
6631 if (i
.tm
.base_opcode
== 0x8d /* lea */
6634 as_warn (_("segment override on `%s' is ineffectual"), i
.tm
.name
);
6636 /* If a segment was explicitly specified, and the specified segment
6637 is not the default, use an opcode prefix to select it. If we
6638 never figured out what the default segment is, then default_seg
6639 will be zero at this point, and the specified segment prefix will
6641 if ((i
.seg
[0]) && (i
.seg
[0] != default_seg
))
6643 if (!add_prefix (i
.seg
[0]->seg_prefix
))
6649 static const seg_entry
*
6650 build_modrm_byte (void)
6652 const seg_entry
*default_seg
= 0;
6653 unsigned int source
, dest
;
6656 vex_3_sources
= i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
;
6659 unsigned int nds
, reg_slot
;
6662 dest
= i
.operands
- 1;
6665 /* There are 2 kinds of instructions:
6666 1. 5 operands: 4 register operands or 3 register operands
6667 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
6668 VexW0 or VexW1. The destination must be either XMM, YMM or
6670 2. 4 operands: 4 register operands or 3 register operands
6671 plus 1 memory operand, with VexXDS. */
6672 gas_assert ((i
.reg_operands
== 4
6673 || (i
.reg_operands
== 3 && i
.mem_operands
== 1))
6674 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
6675 && i
.tm
.opcode_modifier
.vexw
6676 && i
.tm
.operand_types
[dest
].bitfield
.regsimd
);
6678 /* If VexW1 is set, the first non-immediate operand is the source and
6679 the second non-immediate one is encoded in the immediate operand. */
6680 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
6682 source
= i
.imm_operands
;
6683 reg_slot
= i
.imm_operands
+ 1;
6687 source
= i
.imm_operands
+ 1;
6688 reg_slot
= i
.imm_operands
;
6691 if (i
.imm_operands
== 0)
6693 /* When there is no immediate operand, generate an 8bit
6694 immediate operand to encode the first operand. */
6695 exp
= &im_expressions
[i
.imm_operands
++];
6696 i
.op
[i
.operands
].imms
= exp
;
6697 i
.types
[i
.operands
] = imm8
;
6700 gas_assert (i
.tm
.operand_types
[reg_slot
].bitfield
.regsimd
);
6701 exp
->X_op
= O_constant
;
6702 exp
->X_add_number
= register_number (i
.op
[reg_slot
].regs
) << 4;
6703 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
6707 unsigned int imm_slot
;
6709 gas_assert (i
.imm_operands
== 1 && i
.types
[0].bitfield
.vec_imm4
);
6711 if (i
.tm
.opcode_modifier
.immext
)
6713 /* When ImmExt is set, the immediate byte is the last
6715 imm_slot
= i
.operands
- 1;
6723 /* Turn on Imm8 so that output_imm will generate it. */
6724 i
.types
[imm_slot
].bitfield
.imm8
= 1;
6727 gas_assert (i
.tm
.operand_types
[reg_slot
].bitfield
.regsimd
);
6728 i
.op
[imm_slot
].imms
->X_add_number
6729 |= register_number (i
.op
[reg_slot
].regs
) << 4;
6730 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
6733 gas_assert (i
.tm
.operand_types
[nds
].bitfield
.regsimd
);
6734 i
.vex
.register_specifier
= i
.op
[nds
].regs
;
6739 /* i.reg_operands MUST be the number of real register operands;
6740 implicit registers do not count. If there are 3 register
6741 operands, it must be a instruction with VexNDS. For a
6742 instruction with VexNDD, the destination register is encoded
6743 in VEX prefix. If there are 4 register operands, it must be
6744 a instruction with VEX prefix and 3 sources. */
6745 if (i
.mem_operands
== 0
6746 && ((i
.reg_operands
== 2
6747 && i
.tm
.opcode_modifier
.vexvvvv
<= VEXXDS
)
6748 || (i
.reg_operands
== 3
6749 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
6750 || (i
.reg_operands
== 4 && vex_3_sources
)))
6758 /* When there are 3 operands, one of them may be immediate,
6759 which may be the first or the last operand. Otherwise,
6760 the first operand must be shift count register (cl) or it
6761 is an instruction with VexNDS. */
6762 gas_assert (i
.imm_operands
== 1
6763 || (i
.imm_operands
== 0
6764 && (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
6765 || i
.types
[0].bitfield
.shiftcount
)));
6766 if (operand_type_check (i
.types
[0], imm
)
6767 || i
.types
[0].bitfield
.shiftcount
)
6773 /* When there are 4 operands, the first two must be 8bit
6774 immediate operands. The source operand will be the 3rd
6777 For instructions with VexNDS, if the first operand
6778 an imm8, the source operand is the 2nd one. If the last
6779 operand is imm8, the source operand is the first one. */
6780 gas_assert ((i
.imm_operands
== 2
6781 && i
.types
[0].bitfield
.imm8
6782 && i
.types
[1].bitfield
.imm8
)
6783 || (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
6784 && i
.imm_operands
== 1
6785 && (i
.types
[0].bitfield
.imm8
6786 || i
.types
[i
.operands
- 1].bitfield
.imm8
6788 if (i
.imm_operands
== 2)
6792 if (i
.types
[0].bitfield
.imm8
)
6799 if (is_evex_encoding (&i
.tm
))
6801 /* For EVEX instructions, when there are 5 operands, the
6802 first one must be immediate operand. If the second one
6803 is immediate operand, the source operand is the 3th
6804 one. If the last one is immediate operand, the source
6805 operand is the 2nd one. */
6806 gas_assert (i
.imm_operands
== 2
6807 && i
.tm
.opcode_modifier
.sae
6808 && operand_type_check (i
.types
[0], imm
));
6809 if (operand_type_check (i
.types
[1], imm
))
6811 else if (operand_type_check (i
.types
[4], imm
))
6825 /* RC/SAE operand could be between DEST and SRC. That happens
6826 when one operand is GPR and the other one is XMM/YMM/ZMM
6828 if (i
.rounding
&& i
.rounding
->operand
== (int) dest
)
6831 if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
6833 /* For instructions with VexNDS, the register-only source
6834 operand must be a 32/64bit integer, XMM, YMM, ZMM, or mask
6835 register. It is encoded in VEX prefix. We need to
6836 clear RegMem bit before calling operand_type_equal. */
6838 i386_operand_type op
;
6841 /* Check register-only source operand when two source
6842 operands are swapped. */
6843 if (!i
.tm
.operand_types
[source
].bitfield
.baseindex
6844 && i
.tm
.operand_types
[dest
].bitfield
.baseindex
)
6852 op
= i
.tm
.operand_types
[vvvv
];
6853 op
.bitfield
.regmem
= 0;
6854 if ((dest
+ 1) >= i
.operands
6855 || ((!op
.bitfield
.reg
6856 || (!op
.bitfield
.dword
&& !op
.bitfield
.qword
))
6857 && !op
.bitfield
.regsimd
6858 && !operand_type_equal (&op
, ®mask
)))
6860 i
.vex
.register_specifier
= i
.op
[vvvv
].regs
;
6866 /* One of the register operands will be encoded in the i.tm.reg
6867 field, the other in the combined i.tm.mode and i.tm.regmem
6868 fields. If no form of this instruction supports a memory
6869 destination operand, then we assume the source operand may
6870 sometimes be a memory operand and so we need to store the
6871 destination in the i.rm.reg field. */
6872 if (!i
.tm
.operand_types
[dest
].bitfield
.regmem
6873 && operand_type_check (i
.tm
.operand_types
[dest
], anymem
) == 0)
6875 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
6876 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
6877 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
6879 if ((i
.op
[dest
].regs
->reg_flags
& RegVRex
) != 0)
6881 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
6883 if ((i
.op
[source
].regs
->reg_flags
& RegVRex
) != 0)
6888 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
6889 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
6890 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
6892 if ((i
.op
[dest
].regs
->reg_flags
& RegVRex
) != 0)
6894 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
6896 if ((i
.op
[source
].regs
->reg_flags
& RegVRex
) != 0)
6899 if (flag_code
!= CODE_64BIT
&& (i
.rex
& REX_R
))
6901 if (!i
.types
[i
.tm
.operand_types
[0].bitfield
.regmem
].bitfield
.control
)
6904 add_prefix (LOCK_PREFIX_OPCODE
);
6908 { /* If it's not 2 reg operands... */
6913 unsigned int fake_zero_displacement
= 0;
6916 for (op
= 0; op
< i
.operands
; op
++)
6917 if (operand_type_check (i
.types
[op
], anymem
))
6919 gas_assert (op
< i
.operands
);
6921 if (i
.tm
.opcode_modifier
.vecsib
)
6923 if (i
.index_reg
->reg_num
== RegEiz
6924 || i
.index_reg
->reg_num
== RegRiz
)
6927 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6930 i
.sib
.base
= NO_BASE_REGISTER
;
6931 i
.sib
.scale
= i
.log2_scale_factor
;
6932 i
.types
[op
].bitfield
.disp8
= 0;
6933 i
.types
[op
].bitfield
.disp16
= 0;
6934 i
.types
[op
].bitfield
.disp64
= 0;
6935 if (flag_code
!= CODE_64BIT
|| i
.prefix
[ADDR_PREFIX
])
6937 /* Must be 32 bit */
6938 i
.types
[op
].bitfield
.disp32
= 1;
6939 i
.types
[op
].bitfield
.disp32s
= 0;
6943 i
.types
[op
].bitfield
.disp32
= 0;
6944 i
.types
[op
].bitfield
.disp32s
= 1;
6947 i
.sib
.index
= i
.index_reg
->reg_num
;
6948 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
6950 if ((i
.index_reg
->reg_flags
& RegVRex
) != 0)
6956 if (i
.base_reg
== 0)
6959 if (!i
.disp_operands
)
6960 fake_zero_displacement
= 1;
6961 if (i
.index_reg
== 0)
6963 i386_operand_type newdisp
;
6965 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6966 /* Operand is just <disp> */
6967 if (flag_code
== CODE_64BIT
)
6969 /* 64bit mode overwrites the 32bit absolute
6970 addressing by RIP relative addressing and
6971 absolute addressing is encoded by one of the
6972 redundant SIB forms. */
6973 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6974 i
.sib
.base
= NO_BASE_REGISTER
;
6975 i
.sib
.index
= NO_INDEX_REGISTER
;
6976 newdisp
= (!i
.prefix
[ADDR_PREFIX
] ? disp32s
: disp32
);
6978 else if ((flag_code
== CODE_16BIT
)
6979 ^ (i
.prefix
[ADDR_PREFIX
] != 0))
6981 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
6986 i
.rm
.regmem
= NO_BASE_REGISTER
;
6989 i
.types
[op
] = operand_type_and_not (i
.types
[op
], anydisp
);
6990 i
.types
[op
] = operand_type_or (i
.types
[op
], newdisp
);
6992 else if (!i
.tm
.opcode_modifier
.vecsib
)
6994 /* !i.base_reg && i.index_reg */
6995 if (i
.index_reg
->reg_num
== RegEiz
6996 || i
.index_reg
->reg_num
== RegRiz
)
6997 i
.sib
.index
= NO_INDEX_REGISTER
;
6999 i
.sib
.index
= i
.index_reg
->reg_num
;
7000 i
.sib
.base
= NO_BASE_REGISTER
;
7001 i
.sib
.scale
= i
.log2_scale_factor
;
7002 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
7003 i
.types
[op
].bitfield
.disp8
= 0;
7004 i
.types
[op
].bitfield
.disp16
= 0;
7005 i
.types
[op
].bitfield
.disp64
= 0;
7006 if (flag_code
!= CODE_64BIT
|| i
.prefix
[ADDR_PREFIX
])
7008 /* Must be 32 bit */
7009 i
.types
[op
].bitfield
.disp32
= 1;
7010 i
.types
[op
].bitfield
.disp32s
= 0;
7014 i
.types
[op
].bitfield
.disp32
= 0;
7015 i
.types
[op
].bitfield
.disp32s
= 1;
7017 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
7021 /* RIP addressing for 64bit mode. */
7022 else if (i
.base_reg
->reg_num
== RegRip
||
7023 i
.base_reg
->reg_num
== RegEip
)
7025 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
7026 i
.rm
.regmem
= NO_BASE_REGISTER
;
7027 i
.types
[op
].bitfield
.disp8
= 0;
7028 i
.types
[op
].bitfield
.disp16
= 0;
7029 i
.types
[op
].bitfield
.disp32
= 0;
7030 i
.types
[op
].bitfield
.disp32s
= 1;
7031 i
.types
[op
].bitfield
.disp64
= 0;
7032 i
.flags
[op
] |= Operand_PCrel
;
7033 if (! i
.disp_operands
)
7034 fake_zero_displacement
= 1;
7036 else if (i
.base_reg
->reg_type
.bitfield
.word
)
7038 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
7039 switch (i
.base_reg
->reg_num
)
7042 if (i
.index_reg
== 0)
7044 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
7045 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
7049 if (i
.index_reg
== 0)
7052 if (operand_type_check (i
.types
[op
], disp
) == 0)
7054 /* fake (%bp) into 0(%bp) */
7055 i
.types
[op
].bitfield
.disp8
= 1;
7056 fake_zero_displacement
= 1;
7059 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
7060 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
7062 default: /* (%si) -> 4 or (%di) -> 5 */
7063 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
7065 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
7067 else /* i.base_reg and 32/64 bit mode */
7069 if (flag_code
== CODE_64BIT
7070 && operand_type_check (i
.types
[op
], disp
))
7072 i
.types
[op
].bitfield
.disp16
= 0;
7073 i
.types
[op
].bitfield
.disp64
= 0;
7074 if (i
.prefix
[ADDR_PREFIX
] == 0)
7076 i
.types
[op
].bitfield
.disp32
= 0;
7077 i
.types
[op
].bitfield
.disp32s
= 1;
7081 i
.types
[op
].bitfield
.disp32
= 1;
7082 i
.types
[op
].bitfield
.disp32s
= 0;
7086 if (!i
.tm
.opcode_modifier
.vecsib
)
7087 i
.rm
.regmem
= i
.base_reg
->reg_num
;
7088 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
7090 i
.sib
.base
= i
.base_reg
->reg_num
;
7091 /* x86-64 ignores REX prefix bit here to avoid decoder
7093 if (!(i
.base_reg
->reg_flags
& RegRex
)
7094 && (i
.base_reg
->reg_num
== EBP_REG_NUM
7095 || i
.base_reg
->reg_num
== ESP_REG_NUM
))
7097 if (i
.base_reg
->reg_num
== 5 && i
.disp_operands
== 0)
7099 fake_zero_displacement
= 1;
7100 i
.types
[op
].bitfield
.disp8
= 1;
7102 i
.sib
.scale
= i
.log2_scale_factor
;
7103 if (i
.index_reg
== 0)
7105 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
7106 /* <disp>(%esp) becomes two byte modrm with no index
7107 register. We've already stored the code for esp
7108 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
7109 Any base register besides %esp will not use the
7110 extra modrm byte. */
7111 i
.sib
.index
= NO_INDEX_REGISTER
;
7113 else if (!i
.tm
.opcode_modifier
.vecsib
)
7115 if (i
.index_reg
->reg_num
== RegEiz
7116 || i
.index_reg
->reg_num
== RegRiz
)
7117 i
.sib
.index
= NO_INDEX_REGISTER
;
7119 i
.sib
.index
= i
.index_reg
->reg_num
;
7120 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
7121 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
7126 && (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
7127 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
))
7131 if (!fake_zero_displacement
7135 fake_zero_displacement
= 1;
7136 if (i
.disp_encoding
== disp_encoding_8bit
)
7137 i
.types
[op
].bitfield
.disp8
= 1;
7139 i
.types
[op
].bitfield
.disp32
= 1;
7141 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
7145 if (fake_zero_displacement
)
7147 /* Fakes a zero displacement assuming that i.types[op]
7148 holds the correct displacement size. */
7151 gas_assert (i
.op
[op
].disps
== 0);
7152 exp
= &disp_expressions
[i
.disp_operands
++];
7153 i
.op
[op
].disps
= exp
;
7154 exp
->X_op
= O_constant
;
7155 exp
->X_add_number
= 0;
7156 exp
->X_add_symbol
= (symbolS
*) 0;
7157 exp
->X_op_symbol
= (symbolS
*) 0;
7165 if (i
.tm
.opcode_modifier
.vexsources
== XOP2SOURCES
)
7167 if (operand_type_check (i
.types
[0], imm
))
7168 i
.vex
.register_specifier
= NULL
;
7171 /* VEX.vvvv encodes one of the sources when the first
7172 operand is not an immediate. */
7173 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
7174 i
.vex
.register_specifier
= i
.op
[0].regs
;
7176 i
.vex
.register_specifier
= i
.op
[1].regs
;
7179 /* Destination is a XMM register encoded in the ModRM.reg
7181 i
.rm
.reg
= i
.op
[2].regs
->reg_num
;
7182 if ((i
.op
[2].regs
->reg_flags
& RegRex
) != 0)
7185 /* ModRM.rm and VEX.B encodes the other source. */
7186 if (!i
.mem_operands
)
7190 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
7191 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
7193 i
.rm
.regmem
= i
.op
[0].regs
->reg_num
;
7195 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
7199 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXLWP
)
7201 i
.vex
.register_specifier
= i
.op
[2].regs
;
7202 if (!i
.mem_operands
)
7205 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
7206 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
7210 /* Fill in i.rm.reg or i.rm.regmem field with register operand
7211 (if any) based on i.tm.extension_opcode. Again, we must be
7212 careful to make sure that segment/control/debug/test/MMX
7213 registers are coded into the i.rm.reg field. */
7214 else if (i
.reg_operands
)
7217 unsigned int vex_reg
= ~0;
7219 for (op
= 0; op
< i
.operands
; op
++)
7220 if (i
.types
[op
].bitfield
.reg
7221 || i
.types
[op
].bitfield
.regmmx
7222 || i
.types
[op
].bitfield
.regsimd
7223 || i
.types
[op
].bitfield
.regbnd
7224 || i
.types
[op
].bitfield
.regmask
7225 || i
.types
[op
].bitfield
.sreg2
7226 || i
.types
[op
].bitfield
.sreg3
7227 || i
.types
[op
].bitfield
.control
7228 || i
.types
[op
].bitfield
.debug
7229 || i
.types
[op
].bitfield
.test
)
7234 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
7236 /* For instructions with VexNDS, the register-only
7237 source operand is encoded in VEX prefix. */
7238 gas_assert (mem
!= (unsigned int) ~0);
7243 gas_assert (op
< i
.operands
);
7247 /* Check register-only source operand when two source
7248 operands are swapped. */
7249 if (!i
.tm
.operand_types
[op
].bitfield
.baseindex
7250 && i
.tm
.operand_types
[op
+ 1].bitfield
.baseindex
)
7254 gas_assert (mem
== (vex_reg
+ 1)
7255 && op
< i
.operands
);
7260 gas_assert (vex_reg
< i
.operands
);
7264 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXNDD
)
7266 /* For instructions with VexNDD, the register destination
7267 is encoded in VEX prefix. */
7268 if (i
.mem_operands
== 0)
7270 /* There is no memory operand. */
7271 gas_assert ((op
+ 2) == i
.operands
);
7276 /* There are only 2 non-immediate operands. */
7277 gas_assert (op
< i
.imm_operands
+ 2
7278 && i
.operands
== i
.imm_operands
+ 2);
7279 vex_reg
= i
.imm_operands
+ 1;
7283 gas_assert (op
< i
.operands
);
7285 if (vex_reg
!= (unsigned int) ~0)
7287 i386_operand_type
*type
= &i
.tm
.operand_types
[vex_reg
];
7289 if ((!type
->bitfield
.reg
7290 || (!type
->bitfield
.dword
&& !type
->bitfield
.qword
))
7291 && !type
->bitfield
.regsimd
7292 && !operand_type_equal (type
, ®mask
))
7295 i
.vex
.register_specifier
= i
.op
[vex_reg
].regs
;
7298 /* Don't set OP operand twice. */
7301 /* If there is an extension opcode to put here, the
7302 register number must be put into the regmem field. */
7303 if (i
.tm
.extension_opcode
!= None
)
7305 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
7306 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
7308 if ((i
.op
[op
].regs
->reg_flags
& RegVRex
) != 0)
7313 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
7314 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
7316 if ((i
.op
[op
].regs
->reg_flags
& RegVRex
) != 0)
7321 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
7322 must set it to 3 to indicate this is a register operand
7323 in the regmem field. */
7324 if (!i
.mem_operands
)
7328 /* Fill in i.rm.reg field with extension opcode (if any). */
7329 if (i
.tm
.extension_opcode
!= None
)
7330 i
.rm
.reg
= i
.tm
.extension_opcode
;
7336 output_branch (void)
7342 relax_substateT subtype
;
7346 code16
= flag_code
== CODE_16BIT
? CODE16
: 0;
7347 size
= i
.disp_encoding
== disp_encoding_32bit
? BIG
: SMALL
;
7350 if (i
.prefix
[DATA_PREFIX
] != 0)
7356 /* Pentium4 branch hints. */
7357 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
7358 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
7363 if (i
.prefix
[REX_PREFIX
] != 0)
7369 /* BND prefixed jump. */
7370 if (i
.prefix
[BND_PREFIX
] != 0)
7372 FRAG_APPEND_1_CHAR (i
.prefix
[BND_PREFIX
]);
7376 if (i
.prefixes
!= 0 && !intel_syntax
)
7377 as_warn (_("skipping prefixes on this instruction"));
7379 /* It's always a symbol; End frag & setup for relax.
7380 Make sure there is enough room in this frag for the largest
7381 instruction we may generate in md_convert_frag. This is 2
7382 bytes for the opcode and room for the prefix and largest
7384 frag_grow (prefix
+ 2 + 4);
7385 /* Prefix and 1 opcode byte go in fr_fix. */
7386 p
= frag_more (prefix
+ 1);
7387 if (i
.prefix
[DATA_PREFIX
] != 0)
7388 *p
++ = DATA_PREFIX_OPCODE
;
7389 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
7390 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
7391 *p
++ = i
.prefix
[SEG_PREFIX
];
7392 if (i
.prefix
[REX_PREFIX
] != 0)
7393 *p
++ = i
.prefix
[REX_PREFIX
];
7394 *p
= i
.tm
.base_opcode
;
7396 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
7397 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, size
);
7398 else if (cpu_arch_flags
.bitfield
.cpui386
)
7399 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, size
);
7401 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, size
);
7404 sym
= i
.op
[0].disps
->X_add_symbol
;
7405 off
= i
.op
[0].disps
->X_add_number
;
7407 if (i
.op
[0].disps
->X_op
!= O_constant
7408 && i
.op
[0].disps
->X_op
!= O_symbol
)
7410 /* Handle complex expressions. */
7411 sym
= make_expr_symbol (i
.op
[0].disps
);
7415 /* 1 possible extra opcode + 4 byte displacement go in var part.
7416 Pass reloc in fr_var. */
7417 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
7420 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7421 /* Return TRUE iff PLT32 relocation should be used for branching to
7425 need_plt32_p (symbolS
*s
)
7427 /* PLT32 relocation is ELF only. */
7431 /* Since there is no need to prepare for PLT branch on x86-64, we
7432 can generate R_X86_64_PLT32, instead of R_X86_64_PC32, which can
7433 be used as a marker for 32-bit PC-relative branches. */
7437 /* Weak or undefined symbol need PLT32 relocation. */
7438 if (S_IS_WEAK (s
) || !S_IS_DEFINED (s
))
7441 /* Non-global symbol doesn't need PLT32 relocation. */
7442 if (! S_IS_EXTERNAL (s
))
7445 /* Other global symbols need PLT32 relocation. NB: Symbol with
7446 non-default visibilities are treated as normal global symbol
7447 so that PLT32 relocation can be used as a marker for 32-bit
7448 PC-relative branches. It is useful for linker relaxation. */
7459 bfd_reloc_code_real_type jump_reloc
= i
.reloc
[0];
7461 if (i
.tm
.opcode_modifier
.jumpbyte
)
7463 /* This is a loop or jecxz type instruction. */
7465 if (i
.prefix
[ADDR_PREFIX
] != 0)
7467 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
7470 /* Pentium4 branch hints. */
7471 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
7472 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
7474 FRAG_APPEND_1_CHAR (i
.prefix
[SEG_PREFIX
]);
7483 if (flag_code
== CODE_16BIT
)
7486 if (i
.prefix
[DATA_PREFIX
] != 0)
7488 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
7498 if (i
.prefix
[REX_PREFIX
] != 0)
7500 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
7504 /* BND prefixed jump. */
7505 if (i
.prefix
[BND_PREFIX
] != 0)
7507 FRAG_APPEND_1_CHAR (i
.prefix
[BND_PREFIX
]);
7511 if (i
.prefixes
!= 0 && !intel_syntax
)
7512 as_warn (_("skipping prefixes on this instruction"));
7514 p
= frag_more (i
.tm
.opcode_length
+ size
);
7515 switch (i
.tm
.opcode_length
)
7518 *p
++ = i
.tm
.base_opcode
>> 8;
7521 *p
++ = i
.tm
.base_opcode
;
7527 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7529 && jump_reloc
== NO_RELOC
7530 && need_plt32_p (i
.op
[0].disps
->X_add_symbol
))
7531 jump_reloc
= BFD_RELOC_X86_64_PLT32
;
7534 jump_reloc
= reloc (size
, 1, 1, jump_reloc
);
7536 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
7537 i
.op
[0].disps
, 1, jump_reloc
);
7539 /* All jumps handled here are signed, but don't use a signed limit
7540 check for 32 and 16 bit jumps as we want to allow wrap around at
7541 4G and 64k respectively. */
7543 fixP
->fx_signed
= 1;
7547 output_interseg_jump (void)
7555 if (flag_code
== CODE_16BIT
)
7559 if (i
.prefix
[DATA_PREFIX
] != 0)
7565 if (i
.prefix
[REX_PREFIX
] != 0)
7575 if (i
.prefixes
!= 0 && !intel_syntax
)
7576 as_warn (_("skipping prefixes on this instruction"));
7578 /* 1 opcode; 2 segment; offset */
7579 p
= frag_more (prefix
+ 1 + 2 + size
);
7581 if (i
.prefix
[DATA_PREFIX
] != 0)
7582 *p
++ = DATA_PREFIX_OPCODE
;
7584 if (i
.prefix
[REX_PREFIX
] != 0)
7585 *p
++ = i
.prefix
[REX_PREFIX
];
7587 *p
++ = i
.tm
.base_opcode
;
7588 if (i
.op
[1].imms
->X_op
== O_constant
)
7590 offsetT n
= i
.op
[1].imms
->X_add_number
;
7593 && !fits_in_unsigned_word (n
)
7594 && !fits_in_signed_word (n
))
7596 as_bad (_("16-bit jump out of range"));
7599 md_number_to_chars (p
, n
, size
);
7602 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
7603 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
7604 if (i
.op
[0].imms
->X_op
!= O_constant
)
7605 as_bad (_("can't handle non absolute segment in `%s'"),
7607 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
7613 fragS
*insn_start_frag
;
7614 offsetT insn_start_off
;
7616 /* Tie dwarf2 debug info to the address at the start of the insn.
7617 We can't do this after the insn has been output as the current
7618 frag may have been closed off. eg. by frag_var. */
7619 dwarf2_emit_insn (0);
7621 insn_start_frag
= frag_now
;
7622 insn_start_off
= frag_now_fix ();
7625 if (i
.tm
.opcode_modifier
.jump
)
7627 else if (i
.tm
.opcode_modifier
.jumpbyte
7628 || i
.tm
.opcode_modifier
.jumpdword
)
7630 else if (i
.tm
.opcode_modifier
.jumpintersegment
)
7631 output_interseg_jump ();
7634 /* Output normal instructions here. */
7638 unsigned int prefix
;
7641 && i
.tm
.base_opcode
== 0xfae
7643 && i
.imm_operands
== 1
7644 && (i
.op
[0].imms
->X_add_number
== 0xe8
7645 || i
.op
[0].imms
->X_add_number
== 0xf0
7646 || i
.op
[0].imms
->X_add_number
== 0xf8))
7648 /* Encode lfence, mfence, and sfence as
7649 f0 83 04 24 00 lock addl $0x0, (%{re}sp). */
7650 offsetT val
= 0x240483f0ULL
;
7652 md_number_to_chars (p
, val
, 5);
7656 /* Some processors fail on LOCK prefix. This options makes
7657 assembler ignore LOCK prefix and serves as a workaround. */
7658 if (omit_lock_prefix
)
7660 if (i
.tm
.base_opcode
== LOCK_PREFIX_OPCODE
)
7662 i
.prefix
[LOCK_PREFIX
] = 0;
7665 /* Since the VEX/EVEX prefix contains the implicit prefix, we
7666 don't need the explicit prefix. */
7667 if (!i
.tm
.opcode_modifier
.vex
&& !i
.tm
.opcode_modifier
.evex
)
7669 switch (i
.tm
.opcode_length
)
7672 if (i
.tm
.base_opcode
& 0xff000000)
7674 prefix
= (i
.tm
.base_opcode
>> 24) & 0xff;
7675 add_prefix (prefix
);
7679 if ((i
.tm
.base_opcode
& 0xff0000) != 0)
7681 prefix
= (i
.tm
.base_opcode
>> 16) & 0xff;
7682 if (!i
.tm
.cpu_flags
.bitfield
.cpupadlock
7683 || prefix
!= REPE_PREFIX_OPCODE
7684 || (i
.prefix
[REP_PREFIX
] != REPE_PREFIX_OPCODE
))
7685 add_prefix (prefix
);
7691 /* Check for pseudo prefixes. */
7692 as_bad_where (insn_start_frag
->fr_file
,
7693 insn_start_frag
->fr_line
,
7694 _("pseudo prefix without instruction"));
7700 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
7701 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
7702 R_X86_64_GOTTPOFF relocation so that linker can safely
7703 perform IE->LE optimization. */
7704 if (x86_elf_abi
== X86_64_X32_ABI
7706 && i
.reloc
[0] == BFD_RELOC_X86_64_GOTTPOFF
7707 && i
.prefix
[REX_PREFIX
] == 0)
7708 add_prefix (REX_OPCODE
);
7711 /* The prefix bytes. */
7712 for (j
= ARRAY_SIZE (i
.prefix
), q
= i
.prefix
; j
> 0; j
--, q
++)
7714 FRAG_APPEND_1_CHAR (*q
);
7718 for (j
= 0, q
= i
.prefix
; j
< ARRAY_SIZE (i
.prefix
); j
++, q
++)
7723 /* REX byte is encoded in VEX prefix. */
7727 FRAG_APPEND_1_CHAR (*q
);
7730 /* There should be no other prefixes for instructions
7735 /* For EVEX instructions i.vrex should become 0 after
7736 build_evex_prefix. For VEX instructions upper 16 registers
7737 aren't available, so VREX should be 0. */
7740 /* Now the VEX prefix. */
7741 p
= frag_more (i
.vex
.length
);
7742 for (j
= 0; j
< i
.vex
.length
; j
++)
7743 p
[j
] = i
.vex
.bytes
[j
];
7746 /* Now the opcode; be careful about word order here! */
7747 if (i
.tm
.opcode_length
== 1)
7749 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
7753 switch (i
.tm
.opcode_length
)
7757 *p
++ = (i
.tm
.base_opcode
>> 24) & 0xff;
7758 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
7762 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
7772 /* Put out high byte first: can't use md_number_to_chars! */
7773 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
7774 *p
= i
.tm
.base_opcode
& 0xff;
7777 /* Now the modrm byte and sib byte (if present). */
7778 if (i
.tm
.opcode_modifier
.modrm
)
7780 FRAG_APPEND_1_CHAR ((i
.rm
.regmem
<< 0
7783 /* If i.rm.regmem == ESP (4)
7784 && i.rm.mode != (Register mode)
7786 ==> need second modrm byte. */
7787 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
7789 && !(i
.base_reg
&& i
.base_reg
->reg_type
.bitfield
.word
))
7790 FRAG_APPEND_1_CHAR ((i
.sib
.base
<< 0
7792 | i
.sib
.scale
<< 6));
7795 if (i
.disp_operands
)
7796 output_disp (insn_start_frag
, insn_start_off
);
7799 output_imm (insn_start_frag
, insn_start_off
);
7805 pi ("" /*line*/, &i
);
7807 #endif /* DEBUG386 */
7810 /* Return the size of the displacement operand N. */
7813 disp_size (unsigned int n
)
7817 if (i
.types
[n
].bitfield
.disp64
)
7819 else if (i
.types
[n
].bitfield
.disp8
)
7821 else if (i
.types
[n
].bitfield
.disp16
)
7826 /* Return the size of the immediate operand N. */
7829 imm_size (unsigned int n
)
7832 if (i
.types
[n
].bitfield
.imm64
)
7834 else if (i
.types
[n
].bitfield
.imm8
|| i
.types
[n
].bitfield
.imm8s
)
7836 else if (i
.types
[n
].bitfield
.imm16
)
7842 output_disp (fragS
*insn_start_frag
, offsetT insn_start_off
)
7847 for (n
= 0; n
< i
.operands
; n
++)
7849 if (operand_type_check (i
.types
[n
], disp
))
7851 if (i
.op
[n
].disps
->X_op
== O_constant
)
7853 int size
= disp_size (n
);
7854 offsetT val
= i
.op
[n
].disps
->X_add_number
;
7856 val
= offset_in_range (val
>> i
.memshift
, size
);
7857 p
= frag_more (size
);
7858 md_number_to_chars (p
, val
, size
);
7862 enum bfd_reloc_code_real reloc_type
;
7863 int size
= disp_size (n
);
7864 int sign
= i
.types
[n
].bitfield
.disp32s
;
7865 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
7868 /* We can't have 8 bit displacement here. */
7869 gas_assert (!i
.types
[n
].bitfield
.disp8
);
7871 /* The PC relative address is computed relative
7872 to the instruction boundary, so in case immediate
7873 fields follows, we need to adjust the value. */
7874 if (pcrel
&& i
.imm_operands
)
7879 for (n1
= 0; n1
< i
.operands
; n1
++)
7880 if (operand_type_check (i
.types
[n1
], imm
))
7882 /* Only one immediate is allowed for PC
7883 relative address. */
7884 gas_assert (sz
== 0);
7886 i
.op
[n
].disps
->X_add_number
-= sz
;
7888 /* We should find the immediate. */
7889 gas_assert (sz
!= 0);
7892 p
= frag_more (size
);
7893 reloc_type
= reloc (size
, pcrel
, sign
, i
.reloc
[n
]);
7895 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
7896 && (((reloc_type
== BFD_RELOC_32
7897 || reloc_type
== BFD_RELOC_X86_64_32S
7898 || (reloc_type
== BFD_RELOC_64
7900 && (i
.op
[n
].disps
->X_op
== O_symbol
7901 || (i
.op
[n
].disps
->X_op
== O_add
7902 && ((symbol_get_value_expression
7903 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
7905 || reloc_type
== BFD_RELOC_32_PCREL
))
7909 if (insn_start_frag
== frag_now
)
7910 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
7915 add
= insn_start_frag
->fr_fix
- insn_start_off
;
7916 for (fr
= insn_start_frag
->fr_next
;
7917 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
7919 add
+= p
- frag_now
->fr_literal
;
7924 reloc_type
= BFD_RELOC_386_GOTPC
;
7925 i
.op
[n
].imms
->X_add_number
+= add
;
7927 else if (reloc_type
== BFD_RELOC_64
)
7928 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
7930 /* Don't do the adjustment for x86-64, as there
7931 the pcrel addressing is relative to the _next_
7932 insn, and that is taken care of in other code. */
7933 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
7935 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
7936 size
, i
.op
[n
].disps
, pcrel
,
7938 /* Check for "call/jmp *mem", "mov mem, %reg",
7939 "test %reg, mem" and "binop mem, %reg" where binop
7940 is one of adc, add, and, cmp, or, sbb, sub, xor
7941 instructions. Always generate R_386_GOT32X for
7942 "sym*GOT" operand in 32-bit mode. */
7943 if ((generate_relax_relocations
7946 && i
.rm
.regmem
== 5))
7948 || (i
.rm
.mode
== 0 && i
.rm
.regmem
== 5))
7949 && ((i
.operands
== 1
7950 && i
.tm
.base_opcode
== 0xff
7951 && (i
.rm
.reg
== 2 || i
.rm
.reg
== 4))
7953 && (i
.tm
.base_opcode
== 0x8b
7954 || i
.tm
.base_opcode
== 0x85
7955 || (i
.tm
.base_opcode
& 0xc7) == 0x03))))
7959 fixP
->fx_tcbit
= i
.rex
!= 0;
7961 && (i
.base_reg
->reg_num
== RegRip
7962 || i
.base_reg
->reg_num
== RegEip
))
7963 fixP
->fx_tcbit2
= 1;
7966 fixP
->fx_tcbit2
= 1;
7974 output_imm (fragS
*insn_start_frag
, offsetT insn_start_off
)
7979 for (n
= 0; n
< i
.operands
; n
++)
7981 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
7982 if (i
.rounding
&& (int) n
== i
.rounding
->operand
)
7985 if (operand_type_check (i
.types
[n
], imm
))
7987 if (i
.op
[n
].imms
->X_op
== O_constant
)
7989 int size
= imm_size (n
);
7992 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
7994 p
= frag_more (size
);
7995 md_number_to_chars (p
, val
, size
);
7999 /* Not absolute_section.
8000 Need a 32-bit fixup (don't support 8bit
8001 non-absolute imms). Try to support other
8003 enum bfd_reloc_code_real reloc_type
;
8004 int size
= imm_size (n
);
8007 if (i
.types
[n
].bitfield
.imm32s
8008 && (i
.suffix
== QWORD_MNEM_SUFFIX
8009 || (!i
.suffix
&& i
.tm
.opcode_modifier
.no_lsuf
)))
8014 p
= frag_more (size
);
8015 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
8017 /* This is tough to explain. We end up with this one if we
8018 * have operands that look like
8019 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
8020 * obtain the absolute address of the GOT, and it is strongly
8021 * preferable from a performance point of view to avoid using
8022 * a runtime relocation for this. The actual sequence of
8023 * instructions often look something like:
8028 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
8030 * The call and pop essentially return the absolute address
8031 * of the label .L66 and store it in %ebx. The linker itself
8032 * will ultimately change the first operand of the addl so
8033 * that %ebx points to the GOT, but to keep things simple, the
8034 * .o file must have this operand set so that it generates not
8035 * the absolute address of .L66, but the absolute address of
8036 * itself. This allows the linker itself simply treat a GOTPC
8037 * relocation as asking for a pcrel offset to the GOT to be
8038 * added in, and the addend of the relocation is stored in the
8039 * operand field for the instruction itself.
8041 * Our job here is to fix the operand so that it would add
8042 * the correct offset so that %ebx would point to itself. The
8043 * thing that is tricky is that .-.L66 will point to the
8044 * beginning of the instruction, so we need to further modify
8045 * the operand so that it will point to itself. There are
8046 * other cases where you have something like:
8048 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
8050 * and here no correction would be required. Internally in
8051 * the assembler we treat operands of this form as not being
8052 * pcrel since the '.' is explicitly mentioned, and I wonder
8053 * whether it would simplify matters to do it this way. Who
8054 * knows. In earlier versions of the PIC patches, the
8055 * pcrel_adjust field was used to store the correction, but
8056 * since the expression is not pcrel, I felt it would be
8057 * confusing to do it this way. */
8059 if ((reloc_type
== BFD_RELOC_32
8060 || reloc_type
== BFD_RELOC_X86_64_32S
8061 || reloc_type
== BFD_RELOC_64
)
8063 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
8064 && (i
.op
[n
].imms
->X_op
== O_symbol
8065 || (i
.op
[n
].imms
->X_op
== O_add
8066 && ((symbol_get_value_expression
8067 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
8072 if (insn_start_frag
== frag_now
)
8073 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
8078 add
= insn_start_frag
->fr_fix
- insn_start_off
;
8079 for (fr
= insn_start_frag
->fr_next
;
8080 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
8082 add
+= p
- frag_now
->fr_literal
;
8086 reloc_type
= BFD_RELOC_386_GOTPC
;
8088 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
8090 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
8091 i
.op
[n
].imms
->X_add_number
+= add
;
8093 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
8094 i
.op
[n
].imms
, 0, reloc_type
);
8100 /* x86_cons_fix_new is called via the expression parsing code when a
8101 reloc is needed. We use this hook to get the correct .got reloc. */
8102 static int cons_sign
= -1;
8105 x86_cons_fix_new (fragS
*frag
, unsigned int off
, unsigned int len
,
8106 expressionS
*exp
, bfd_reloc_code_real_type r
)
8108 r
= reloc (len
, 0, cons_sign
, r
);
8111 if (exp
->X_op
== O_secrel
)
8113 exp
->X_op
= O_symbol
;
8114 r
= BFD_RELOC_32_SECREL
;
8118 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
8121 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
8122 purpose of the `.dc.a' internal pseudo-op. */
8125 x86_address_bytes (void)
8127 if ((stdoutput
->arch_info
->mach
& bfd_mach_x64_32
))
8129 return stdoutput
->arch_info
->bits_per_address
/ 8;
8132 #if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
8134 # define lex_got(reloc, adjust, types) NULL
8136 /* Parse operands of the form
8137 <symbol>@GOTOFF+<nnn>
8138 and similar .plt or .got references.
8140 If we find one, set up the correct relocation in RELOC and copy the
8141 input string, minus the `@GOTOFF' into a malloc'd buffer for
8142 parsing by the calling routine. Return this buffer, and if ADJUST
8143 is non-null set it to the length of the string we removed from the
8144 input line. Otherwise return NULL. */
8146 lex_got (enum bfd_reloc_code_real
*rel
,
8148 i386_operand_type
*types
)
8150 /* Some of the relocations depend on the size of what field is to
8151 be relocated. But in our callers i386_immediate and i386_displacement
8152 we don't yet know the operand size (this will be set by insn
8153 matching). Hence we record the word32 relocation here,
8154 and adjust the reloc according to the real size in reloc(). */
8155 static const struct {
8158 const enum bfd_reloc_code_real rel
[2];
8159 const i386_operand_type types64
;
8161 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8162 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32
,
8164 OPERAND_TYPE_IMM32_64
},
8166 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real
,
8167 BFD_RELOC_X86_64_PLTOFF64
},
8168 OPERAND_TYPE_IMM64
},
8169 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32
,
8170 BFD_RELOC_X86_64_PLT32
},
8171 OPERAND_TYPE_IMM32_32S_DISP32
},
8172 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real
,
8173 BFD_RELOC_X86_64_GOTPLT64
},
8174 OPERAND_TYPE_IMM64_DISP64
},
8175 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF
,
8176 BFD_RELOC_X86_64_GOTOFF64
},
8177 OPERAND_TYPE_IMM64_DISP64
},
8178 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real
,
8179 BFD_RELOC_X86_64_GOTPCREL
},
8180 OPERAND_TYPE_IMM32_32S_DISP32
},
8181 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD
,
8182 BFD_RELOC_X86_64_TLSGD
},
8183 OPERAND_TYPE_IMM32_32S_DISP32
},
8184 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM
,
8185 _dummy_first_bfd_reloc_code_real
},
8186 OPERAND_TYPE_NONE
},
8187 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real
,
8188 BFD_RELOC_X86_64_TLSLD
},
8189 OPERAND_TYPE_IMM32_32S_DISP32
},
8190 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32
,
8191 BFD_RELOC_X86_64_GOTTPOFF
},
8192 OPERAND_TYPE_IMM32_32S_DISP32
},
8193 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32
,
8194 BFD_RELOC_X86_64_TPOFF32
},
8195 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
8196 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE
,
8197 _dummy_first_bfd_reloc_code_real
},
8198 OPERAND_TYPE_NONE
},
8199 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32
,
8200 BFD_RELOC_X86_64_DTPOFF32
},
8201 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
8202 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE
,
8203 _dummy_first_bfd_reloc_code_real
},
8204 OPERAND_TYPE_NONE
},
8205 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE
,
8206 _dummy_first_bfd_reloc_code_real
},
8207 OPERAND_TYPE_NONE
},
8208 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32
,
8209 BFD_RELOC_X86_64_GOT32
},
8210 OPERAND_TYPE_IMM32_32S_64_DISP32
},
8211 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC
,
8212 BFD_RELOC_X86_64_GOTPC32_TLSDESC
},
8213 OPERAND_TYPE_IMM32_32S_DISP32
},
8214 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL
,
8215 BFD_RELOC_X86_64_TLSDESC_CALL
},
8216 OPERAND_TYPE_IMM32_32S_DISP32
},
8221 #if defined (OBJ_MAYBE_ELF)
8226 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
8227 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
8230 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
8232 int len
= gotrel
[j
].len
;
8233 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
8235 if (gotrel
[j
].rel
[object_64bit
] != 0)
8238 char *tmpbuf
, *past_reloc
;
8240 *rel
= gotrel
[j
].rel
[object_64bit
];
8244 if (flag_code
!= CODE_64BIT
)
8246 types
->bitfield
.imm32
= 1;
8247 types
->bitfield
.disp32
= 1;
8250 *types
= gotrel
[j
].types64
;
8253 if (j
!= 0 && GOT_symbol
== NULL
)
8254 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
8256 /* The length of the first part of our input line. */
8257 first
= cp
- input_line_pointer
;
8259 /* The second part goes from after the reloc token until
8260 (and including) an end_of_line char or comma. */
8261 past_reloc
= cp
+ 1 + len
;
8263 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
8265 second
= cp
+ 1 - past_reloc
;
8267 /* Allocate and copy string. The trailing NUL shouldn't
8268 be necessary, but be safe. */
8269 tmpbuf
= XNEWVEC (char, first
+ second
+ 2);
8270 memcpy (tmpbuf
, input_line_pointer
, first
);
8271 if (second
!= 0 && *past_reloc
!= ' ')
8272 /* Replace the relocation token with ' ', so that
8273 errors like foo@GOTOFF1 will be detected. */
8274 tmpbuf
[first
++] = ' ';
8276 /* Increment length by 1 if the relocation token is
8281 memcpy (tmpbuf
+ first
, past_reloc
, second
);
8282 tmpbuf
[first
+ second
] = '\0';
8286 as_bad (_("@%s reloc is not supported with %d-bit output format"),
8287 gotrel
[j
].str
, 1 << (5 + object_64bit
));
8292 /* Might be a symbol version string. Don't as_bad here. */
8301 /* Parse operands of the form
8302 <symbol>@SECREL32+<nnn>
8304 If we find one, set up the correct relocation in RELOC and copy the
8305 input string, minus the `@SECREL32' into a malloc'd buffer for
8306 parsing by the calling routine. Return this buffer, and if ADJUST
8307 is non-null set it to the length of the string we removed from the
8308 input line. Otherwise return NULL.
8310 This function is copied from the ELF version above adjusted for PE targets. */
8313 lex_got (enum bfd_reloc_code_real
*rel ATTRIBUTE_UNUSED
,
8314 int *adjust ATTRIBUTE_UNUSED
,
8315 i386_operand_type
*types
)
8321 const enum bfd_reloc_code_real rel
[2];
8322 const i386_operand_type types64
;
8326 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL
,
8327 BFD_RELOC_32_SECREL
},
8328 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
8334 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
8335 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
8338 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
8340 int len
= gotrel
[j
].len
;
8342 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
8344 if (gotrel
[j
].rel
[object_64bit
] != 0)
8347 char *tmpbuf
, *past_reloc
;
8349 *rel
= gotrel
[j
].rel
[object_64bit
];
8355 if (flag_code
!= CODE_64BIT
)
8357 types
->bitfield
.imm32
= 1;
8358 types
->bitfield
.disp32
= 1;
8361 *types
= gotrel
[j
].types64
;
8364 /* The length of the first part of our input line. */
8365 first
= cp
- input_line_pointer
;
8367 /* The second part goes from after the reloc token until
8368 (and including) an end_of_line char or comma. */
8369 past_reloc
= cp
+ 1 + len
;
8371 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
8373 second
= cp
+ 1 - past_reloc
;
8375 /* Allocate and copy string. The trailing NUL shouldn't
8376 be necessary, but be safe. */
8377 tmpbuf
= XNEWVEC (char, first
+ second
+ 2);
8378 memcpy (tmpbuf
, input_line_pointer
, first
);
8379 if (second
!= 0 && *past_reloc
!= ' ')
8380 /* Replace the relocation token with ' ', so that
8381 errors like foo@SECLREL321 will be detected. */
8382 tmpbuf
[first
++] = ' ';
8383 memcpy (tmpbuf
+ first
, past_reloc
, second
);
8384 tmpbuf
[first
+ second
] = '\0';
8388 as_bad (_("@%s reloc is not supported with %d-bit output format"),
8389 gotrel
[j
].str
, 1 << (5 + object_64bit
));
8394 /* Might be a symbol version string. Don't as_bad here. */
8400 bfd_reloc_code_real_type
8401 x86_cons (expressionS
*exp
, int size
)
8403 bfd_reloc_code_real_type got_reloc
= NO_RELOC
;
8405 intel_syntax
= -intel_syntax
;
8408 if (size
== 4 || (object_64bit
&& size
== 8))
8410 /* Handle @GOTOFF and the like in an expression. */
8412 char *gotfree_input_line
;
8415 save
= input_line_pointer
;
8416 gotfree_input_line
= lex_got (&got_reloc
, &adjust
, NULL
);
8417 if (gotfree_input_line
)
8418 input_line_pointer
= gotfree_input_line
;
8422 if (gotfree_input_line
)
8424 /* expression () has merrily parsed up to the end of line,
8425 or a comma - in the wrong buffer. Transfer how far
8426 input_line_pointer has moved to the right buffer. */
8427 input_line_pointer
= (save
8428 + (input_line_pointer
- gotfree_input_line
)
8430 free (gotfree_input_line
);
8431 if (exp
->X_op
== O_constant
8432 || exp
->X_op
== O_absent
8433 || exp
->X_op
== O_illegal
8434 || exp
->X_op
== O_register
8435 || exp
->X_op
== O_big
)
8437 char c
= *input_line_pointer
;
8438 *input_line_pointer
= 0;
8439 as_bad (_("missing or invalid expression `%s'"), save
);
8440 *input_line_pointer
= c
;
8447 intel_syntax
= -intel_syntax
;
8450 i386_intel_simplify (exp
);
8456 signed_cons (int size
)
8458 if (flag_code
== CODE_64BIT
)
8466 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
8473 if (exp
.X_op
== O_symbol
)
8474 exp
.X_op
= O_secrel
;
8476 emit_expr (&exp
, 4);
8478 while (*input_line_pointer
++ == ',');
8480 input_line_pointer
--;
8481 demand_empty_rest_of_line ();
8485 /* Handle Vector operations. */
8488 check_VecOperations (char *op_string
, char *op_end
)
8490 const reg_entry
*mask
;
8495 && (op_end
== NULL
|| op_string
< op_end
))
8498 if (*op_string
== '{')
8502 /* Check broadcasts. */
8503 if (strncmp (op_string
, "1to", 3) == 0)
8508 goto duplicated_vec_op
;
8511 if (*op_string
== '8')
8513 else if (*op_string
== '4')
8515 else if (*op_string
== '2')
8517 else if (*op_string
== '1'
8518 && *(op_string
+1) == '6')
8525 as_bad (_("Unsupported broadcast: `%s'"), saved
);
8530 broadcast_op
.type
= bcst_type
;
8531 broadcast_op
.operand
= this_operand
;
8532 i
.broadcast
= &broadcast_op
;
8534 /* Check masking operation. */
8535 else if ((mask
= parse_register (op_string
, &end_op
)) != NULL
)
8537 /* k0 can't be used for write mask. */
8538 if (!mask
->reg_type
.bitfield
.regmask
|| mask
->reg_num
== 0)
8540 as_bad (_("`%s%s' can't be used for write mask"),
8541 register_prefix
, mask
->reg_name
);
8547 mask_op
.mask
= mask
;
8548 mask_op
.zeroing
= 0;
8549 mask_op
.operand
= this_operand
;
8555 goto duplicated_vec_op
;
8557 i
.mask
->mask
= mask
;
8559 /* Only "{z}" is allowed here. No need to check
8560 zeroing mask explicitly. */
8561 if (i
.mask
->operand
!= this_operand
)
8563 as_bad (_("invalid write mask `%s'"), saved
);
8570 /* Check zeroing-flag for masking operation. */
8571 else if (*op_string
== 'z')
8575 mask_op
.mask
= NULL
;
8576 mask_op
.zeroing
= 1;
8577 mask_op
.operand
= this_operand
;
8582 if (i
.mask
->zeroing
)
8585 as_bad (_("duplicated `%s'"), saved
);
8589 i
.mask
->zeroing
= 1;
8591 /* Only "{%k}" is allowed here. No need to check mask
8592 register explicitly. */
8593 if (i
.mask
->operand
!= this_operand
)
8595 as_bad (_("invalid zeroing-masking `%s'"),
8604 goto unknown_vec_op
;
8606 if (*op_string
!= '}')
8608 as_bad (_("missing `}' in `%s'"), saved
);
8613 /* Strip whitespace since the addition of pseudo prefixes
8614 changed how the scrubber treats '{'. */
8615 if (is_space_char (*op_string
))
8621 /* We don't know this one. */
8622 as_bad (_("unknown vector operation: `%s'"), saved
);
8626 if (i
.mask
&& i
.mask
->zeroing
&& !i
.mask
->mask
)
8628 as_bad (_("zeroing-masking only allowed with write mask"));
8636 i386_immediate (char *imm_start
)
8638 char *save_input_line_pointer
;
8639 char *gotfree_input_line
;
8642 i386_operand_type types
;
8644 operand_type_set (&types
, ~0);
8646 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
8648 as_bad (_("at most %d immediate operands are allowed"),
8649 MAX_IMMEDIATE_OPERANDS
);
8653 exp
= &im_expressions
[i
.imm_operands
++];
8654 i
.op
[this_operand
].imms
= exp
;
8656 if (is_space_char (*imm_start
))
8659 save_input_line_pointer
= input_line_pointer
;
8660 input_line_pointer
= imm_start
;
8662 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
8663 if (gotfree_input_line
)
8664 input_line_pointer
= gotfree_input_line
;
8666 exp_seg
= expression (exp
);
8670 /* Handle vector operations. */
8671 if (*input_line_pointer
== '{')
8673 input_line_pointer
= check_VecOperations (input_line_pointer
,
8675 if (input_line_pointer
== NULL
)
8679 if (*input_line_pointer
)
8680 as_bad (_("junk `%s' after expression"), input_line_pointer
);
8682 input_line_pointer
= save_input_line_pointer
;
8683 if (gotfree_input_line
)
8685 free (gotfree_input_line
);
8687 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
8688 exp
->X_op
= O_illegal
;
8691 return i386_finalize_immediate (exp_seg
, exp
, types
, imm_start
);
8695 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
8696 i386_operand_type types
, const char *imm_start
)
8698 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_illegal
|| exp
->X_op
== O_big
)
8701 as_bad (_("missing or invalid immediate expression `%s'"),
8705 else if (exp
->X_op
== O_constant
)
8707 /* Size it properly later. */
8708 i
.types
[this_operand
].bitfield
.imm64
= 1;
8709 /* If not 64bit, sign extend val. */
8710 if (flag_code
!= CODE_64BIT
8711 && (exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
8713 = (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
8715 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8716 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
8717 && exp_seg
!= absolute_section
8718 && exp_seg
!= text_section
8719 && exp_seg
!= data_section
8720 && exp_seg
!= bss_section
8721 && exp_seg
!= undefined_section
8722 && !bfd_is_com_section (exp_seg
))
8724 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
8728 else if (!intel_syntax
&& exp_seg
== reg_section
)
8731 as_bad (_("illegal immediate register operand %s"), imm_start
);
8736 /* This is an address. The size of the address will be
8737 determined later, depending on destination register,
8738 suffix, or the default for the section. */
8739 i
.types
[this_operand
].bitfield
.imm8
= 1;
8740 i
.types
[this_operand
].bitfield
.imm16
= 1;
8741 i
.types
[this_operand
].bitfield
.imm32
= 1;
8742 i
.types
[this_operand
].bitfield
.imm32s
= 1;
8743 i
.types
[this_operand
].bitfield
.imm64
= 1;
8744 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
8752 i386_scale (char *scale
)
8755 char *save
= input_line_pointer
;
8757 input_line_pointer
= scale
;
8758 val
= get_absolute_expression ();
8763 i
.log2_scale_factor
= 0;
8766 i
.log2_scale_factor
= 1;
8769 i
.log2_scale_factor
= 2;
8772 i
.log2_scale_factor
= 3;
8776 char sep
= *input_line_pointer
;
8778 *input_line_pointer
= '\0';
8779 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
8781 *input_line_pointer
= sep
;
8782 input_line_pointer
= save
;
8786 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
8788 as_warn (_("scale factor of %d without an index register"),
8789 1 << i
.log2_scale_factor
);
8790 i
.log2_scale_factor
= 0;
8792 scale
= input_line_pointer
;
8793 input_line_pointer
= save
;
8798 i386_displacement (char *disp_start
, char *disp_end
)
8802 char *save_input_line_pointer
;
8803 char *gotfree_input_line
;
8805 i386_operand_type bigdisp
, types
= anydisp
;
8808 if (i
.disp_operands
== MAX_MEMORY_OPERANDS
)
8810 as_bad (_("at most %d displacement operands are allowed"),
8811 MAX_MEMORY_OPERANDS
);
8815 operand_type_set (&bigdisp
, 0);
8816 if ((i
.types
[this_operand
].bitfield
.jumpabsolute
)
8817 || (!current_templates
->start
->opcode_modifier
.jump
8818 && !current_templates
->start
->opcode_modifier
.jumpdword
))
8820 bigdisp
.bitfield
.disp32
= 1;
8821 override
= (i
.prefix
[ADDR_PREFIX
] != 0);
8822 if (flag_code
== CODE_64BIT
)
8826 bigdisp
.bitfield
.disp32s
= 1;
8827 bigdisp
.bitfield
.disp64
= 1;
8830 else if ((flag_code
== CODE_16BIT
) ^ override
)
8832 bigdisp
.bitfield
.disp32
= 0;
8833 bigdisp
.bitfield
.disp16
= 1;
8838 /* For PC-relative branches, the width of the displacement
8839 is dependent upon data size, not address size. */
8840 override
= (i
.prefix
[DATA_PREFIX
] != 0);
8841 if (flag_code
== CODE_64BIT
)
8843 if (override
|| i
.suffix
== WORD_MNEM_SUFFIX
)
8844 bigdisp
.bitfield
.disp16
= 1;
8847 bigdisp
.bitfield
.disp32
= 1;
8848 bigdisp
.bitfield
.disp32s
= 1;
8854 override
= (i
.suffix
== (flag_code
!= CODE_16BIT
8856 : LONG_MNEM_SUFFIX
));
8857 bigdisp
.bitfield
.disp32
= 1;
8858 if ((flag_code
== CODE_16BIT
) ^ override
)
8860 bigdisp
.bitfield
.disp32
= 0;
8861 bigdisp
.bitfield
.disp16
= 1;
8865 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
8868 exp
= &disp_expressions
[i
.disp_operands
];
8869 i
.op
[this_operand
].disps
= exp
;
8871 save_input_line_pointer
= input_line_pointer
;
8872 input_line_pointer
= disp_start
;
8873 END_STRING_AND_SAVE (disp_end
);
8875 #ifndef GCC_ASM_O_HACK
8876 #define GCC_ASM_O_HACK 0
8879 END_STRING_AND_SAVE (disp_end
+ 1);
8880 if (i
.types
[this_operand
].bitfield
.baseIndex
8881 && displacement_string_end
[-1] == '+')
8883 /* This hack is to avoid a warning when using the "o"
8884 constraint within gcc asm statements.
8887 #define _set_tssldt_desc(n,addr,limit,type) \
8888 __asm__ __volatile__ ( \
8890 "movw %w1,2+%0\n\t" \
8892 "movb %b1,4+%0\n\t" \
8893 "movb %4,5+%0\n\t" \
8894 "movb $0,6+%0\n\t" \
8895 "movb %h1,7+%0\n\t" \
8897 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
8899 This works great except that the output assembler ends
8900 up looking a bit weird if it turns out that there is
8901 no offset. You end up producing code that looks like:
8914 So here we provide the missing zero. */
8916 *displacement_string_end
= '0';
8919 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
8920 if (gotfree_input_line
)
8921 input_line_pointer
= gotfree_input_line
;
8923 exp_seg
= expression (exp
);
8926 if (*input_line_pointer
)
8927 as_bad (_("junk `%s' after expression"), input_line_pointer
);
8929 RESTORE_END_STRING (disp_end
+ 1);
8931 input_line_pointer
= save_input_line_pointer
;
8932 if (gotfree_input_line
)
8934 free (gotfree_input_line
);
8936 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
8937 exp
->X_op
= O_illegal
;
8940 ret
= i386_finalize_displacement (exp_seg
, exp
, types
, disp_start
);
8942 RESTORE_END_STRING (disp_end
);
8948 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
8949 i386_operand_type types
, const char *disp_start
)
8951 i386_operand_type bigdisp
;
8954 /* We do this to make sure that the section symbol is in
8955 the symbol table. We will ultimately change the relocation
8956 to be relative to the beginning of the section. */
8957 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
8958 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
8959 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
8961 if (exp
->X_op
!= O_symbol
)
8964 if (S_IS_LOCAL (exp
->X_add_symbol
)
8965 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
8966 && S_GET_SEGMENT (exp
->X_add_symbol
) != expr_section
)
8967 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
8968 exp
->X_op
= O_subtract
;
8969 exp
->X_op_symbol
= GOT_symbol
;
8970 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
8971 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
8972 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
8973 i
.reloc
[this_operand
] = BFD_RELOC_64
;
8975 i
.reloc
[this_operand
] = BFD_RELOC_32
;
8978 else if (exp
->X_op
== O_absent
8979 || exp
->X_op
== O_illegal
8980 || exp
->X_op
== O_big
)
8983 as_bad (_("missing or invalid displacement expression `%s'"),
8988 else if (flag_code
== CODE_64BIT
8989 && !i
.prefix
[ADDR_PREFIX
]
8990 && exp
->X_op
== O_constant
)
8992 /* Since displacement is signed extended to 64bit, don't allow
8993 disp32 and turn off disp32s if they are out of range. */
8994 i
.types
[this_operand
].bitfield
.disp32
= 0;
8995 if (!fits_in_signed_long (exp
->X_add_number
))
8997 i
.types
[this_operand
].bitfield
.disp32s
= 0;
8998 if (i
.types
[this_operand
].bitfield
.baseindex
)
9000 as_bad (_("0x%lx out range of signed 32bit displacement"),
9001 (long) exp
->X_add_number
);
9007 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
9008 else if (exp
->X_op
!= O_constant
9009 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
9010 && exp_seg
!= absolute_section
9011 && exp_seg
!= text_section
9012 && exp_seg
!= data_section
9013 && exp_seg
!= bss_section
9014 && exp_seg
!= undefined_section
9015 && !bfd_is_com_section (exp_seg
))
9017 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
9022 /* Check if this is a displacement only operand. */
9023 bigdisp
= i
.types
[this_operand
];
9024 bigdisp
.bitfield
.disp8
= 0;
9025 bigdisp
.bitfield
.disp16
= 0;
9026 bigdisp
.bitfield
.disp32
= 0;
9027 bigdisp
.bitfield
.disp32s
= 0;
9028 bigdisp
.bitfield
.disp64
= 0;
9029 if (operand_type_all_zero (&bigdisp
))
9030 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
9036 /* Return the active addressing mode, taking address override and
9037 registers forming the address into consideration. Update the
9038 address override prefix if necessary. */
9040 static enum flag_code
9041 i386_addressing_mode (void)
9043 enum flag_code addr_mode
;
9045 if (i
.prefix
[ADDR_PREFIX
])
9046 addr_mode
= flag_code
== CODE_32BIT
? CODE_16BIT
: CODE_32BIT
;
9049 addr_mode
= flag_code
;
9051 #if INFER_ADDR_PREFIX
9052 if (i
.mem_operands
== 0)
9054 /* Infer address prefix from the first memory operand. */
9055 const reg_entry
*addr_reg
= i
.base_reg
;
9057 if (addr_reg
== NULL
)
9058 addr_reg
= i
.index_reg
;
9062 if (addr_reg
->reg_num
== RegEip
9063 || addr_reg
->reg_num
== RegEiz
9064 || addr_reg
->reg_type
.bitfield
.dword
)
9065 addr_mode
= CODE_32BIT
;
9066 else if (flag_code
!= CODE_64BIT
9067 && addr_reg
->reg_type
.bitfield
.word
)
9068 addr_mode
= CODE_16BIT
;
9070 if (addr_mode
!= flag_code
)
9072 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
9074 /* Change the size of any displacement too. At most one
9075 of Disp16 or Disp32 is set.
9076 FIXME. There doesn't seem to be any real need for
9077 separate Disp16 and Disp32 flags. The same goes for
9078 Imm16 and Imm32. Removing them would probably clean
9079 up the code quite a lot. */
9080 if (flag_code
!= CODE_64BIT
9081 && (i
.types
[this_operand
].bitfield
.disp16
9082 || i
.types
[this_operand
].bitfield
.disp32
))
9083 i
.types
[this_operand
]
9084 = operand_type_xor (i
.types
[this_operand
], disp16_32
);
9094 /* Make sure the memory operand we've been dealt is valid.
9095 Return 1 on success, 0 on a failure. */
9098 i386_index_check (const char *operand_string
)
9100 const char *kind
= "base/index";
9101 enum flag_code addr_mode
= i386_addressing_mode ();
9103 if (current_templates
->start
->opcode_modifier
.isstring
9104 && !current_templates
->start
->opcode_modifier
.immext
9105 && (current_templates
->end
[-1].opcode_modifier
.isstring
9108 /* Memory operands of string insns are special in that they only allow
9109 a single register (rDI, rSI, or rBX) as their memory address. */
9110 const reg_entry
*expected_reg
;
9111 static const char *di_si
[][2] =
9117 static const char *bx
[] = { "ebx", "bx", "rbx" };
9119 kind
= "string address";
9121 if (current_templates
->start
->opcode_modifier
.repprefixok
)
9123 i386_operand_type type
= current_templates
->end
[-1].operand_types
[0];
9125 if (!type
.bitfield
.baseindex
9126 || ((!i
.mem_operands
!= !intel_syntax
)
9127 && current_templates
->end
[-1].operand_types
[1]
9128 .bitfield
.baseindex
))
9129 type
= current_templates
->end
[-1].operand_types
[1];
9130 expected_reg
= hash_find (reg_hash
,
9131 di_si
[addr_mode
][type
.bitfield
.esseg
]);
9135 expected_reg
= hash_find (reg_hash
, bx
[addr_mode
]);
9137 if (i
.base_reg
!= expected_reg
9139 || operand_type_check (i
.types
[this_operand
], disp
))
9141 /* The second memory operand must have the same size as
9145 && !((addr_mode
== CODE_64BIT
9146 && i
.base_reg
->reg_type
.bitfield
.qword
)
9147 || (addr_mode
== CODE_32BIT
9148 ? i
.base_reg
->reg_type
.bitfield
.dword
9149 : i
.base_reg
->reg_type
.bitfield
.word
)))
9152 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
9154 intel_syntax
? '[' : '(',
9156 expected_reg
->reg_name
,
9157 intel_syntax
? ']' : ')');
9164 as_bad (_("`%s' is not a valid %s expression"),
9165 operand_string
, kind
);
9170 if (addr_mode
!= CODE_16BIT
)
9172 /* 32-bit/64-bit checks. */
9174 && (addr_mode
== CODE_64BIT
9175 ? !i
.base_reg
->reg_type
.bitfield
.qword
9176 : !i
.base_reg
->reg_type
.bitfield
.dword
)
9178 || (i
.base_reg
->reg_num
9179 != (addr_mode
== CODE_64BIT
? RegRip
: RegEip
))))
9181 && !i
.index_reg
->reg_type
.bitfield
.xmmword
9182 && !i
.index_reg
->reg_type
.bitfield
.ymmword
9183 && !i
.index_reg
->reg_type
.bitfield
.zmmword
9184 && ((addr_mode
== CODE_64BIT
9185 ? !(i
.index_reg
->reg_type
.bitfield
.qword
9186 || i
.index_reg
->reg_num
== RegRiz
)
9187 : !(i
.index_reg
->reg_type
.bitfield
.dword
9188 || i
.index_reg
->reg_num
== RegEiz
))
9189 || !i
.index_reg
->reg_type
.bitfield
.baseindex
)))
9192 /* bndmk, bndldx, and bndstx have special restrictions. */
9193 if (current_templates
->start
->base_opcode
== 0xf30f1b
9194 || (current_templates
->start
->base_opcode
& ~1) == 0x0f1a)
9196 /* They cannot use RIP-relative addressing. */
9197 if (i
.base_reg
&& i
.base_reg
->reg_num
== RegRip
)
9199 as_bad (_("`%s' cannot be used here"), operand_string
);
9203 /* bndldx and bndstx ignore their scale factor. */
9204 if (current_templates
->start
->base_opcode
!= 0xf30f1b
9205 && i
.log2_scale_factor
)
9206 as_warn (_("register scaling is being ignored here"));
9211 /* 16-bit checks. */
9213 && (!i
.base_reg
->reg_type
.bitfield
.word
9214 || !i
.base_reg
->reg_type
.bitfield
.baseindex
))
9216 && (!i
.index_reg
->reg_type
.bitfield
.word
9217 || !i
.index_reg
->reg_type
.bitfield
.baseindex
9219 && i
.base_reg
->reg_num
< 6
9220 && i
.index_reg
->reg_num
>= 6
9221 && i
.log2_scale_factor
== 0))))
9228 /* Handle vector immediates. */
9231 RC_SAE_immediate (const char *imm_start
)
9233 unsigned int match_found
, j
;
9234 const char *pstr
= imm_start
;
9242 for (j
= 0; j
< ARRAY_SIZE (RC_NamesTable
); j
++)
9244 if (!strncmp (pstr
, RC_NamesTable
[j
].name
, RC_NamesTable
[j
].len
))
9248 rc_op
.type
= RC_NamesTable
[j
].type
;
9249 rc_op
.operand
= this_operand
;
9250 i
.rounding
= &rc_op
;
9254 as_bad (_("duplicated `%s'"), imm_start
);
9257 pstr
+= RC_NamesTable
[j
].len
;
9267 as_bad (_("Missing '}': '%s'"), imm_start
);
9270 /* RC/SAE immediate string should contain nothing more. */;
9273 as_bad (_("Junk after '}': '%s'"), imm_start
);
9277 exp
= &im_expressions
[i
.imm_operands
++];
9278 i
.op
[this_operand
].imms
= exp
;
9280 exp
->X_op
= O_constant
;
9281 exp
->X_add_number
= 0;
9282 exp
->X_add_symbol
= (symbolS
*) 0;
9283 exp
->X_op_symbol
= (symbolS
*) 0;
9285 i
.types
[this_operand
].bitfield
.imm8
= 1;
9289 /* Only string instructions can have a second memory operand, so
9290 reduce current_templates to just those if it contains any. */
9292 maybe_adjust_templates (void)
9294 const insn_template
*t
;
9296 gas_assert (i
.mem_operands
== 1);
9298 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
9299 if (t
->opcode_modifier
.isstring
)
9302 if (t
< current_templates
->end
)
9304 static templates aux_templates
;
9305 bfd_boolean recheck
;
9307 aux_templates
.start
= t
;
9308 for (; t
< current_templates
->end
; ++t
)
9309 if (!t
->opcode_modifier
.isstring
)
9311 aux_templates
.end
= t
;
9313 /* Determine whether to re-check the first memory operand. */
9314 recheck
= (aux_templates
.start
!= current_templates
->start
9315 || t
!= current_templates
->end
);
9317 current_templates
= &aux_templates
;
9322 if (i
.memop1_string
!= NULL
9323 && i386_index_check (i
.memop1_string
) == 0)
9332 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
9336 i386_att_operand (char *operand_string
)
9340 char *op_string
= operand_string
;
9342 if (is_space_char (*op_string
))
9345 /* We check for an absolute prefix (differentiating,
9346 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
9347 if (*op_string
== ABSOLUTE_PREFIX
)
9350 if (is_space_char (*op_string
))
9352 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
9355 /* Check if operand is a register. */
9356 if ((r
= parse_register (op_string
, &end_op
)) != NULL
)
9358 i386_operand_type temp
;
9360 /* Check for a segment override by searching for ':' after a
9361 segment register. */
9363 if (is_space_char (*op_string
))
9365 if (*op_string
== ':'
9366 && (r
->reg_type
.bitfield
.sreg2
9367 || r
->reg_type
.bitfield
.sreg3
))
9372 i
.seg
[i
.mem_operands
] = &es
;
9375 i
.seg
[i
.mem_operands
] = &cs
;
9378 i
.seg
[i
.mem_operands
] = &ss
;
9381 i
.seg
[i
.mem_operands
] = &ds
;
9384 i
.seg
[i
.mem_operands
] = &fs
;
9387 i
.seg
[i
.mem_operands
] = &gs
;
9391 /* Skip the ':' and whitespace. */
9393 if (is_space_char (*op_string
))
9396 if (!is_digit_char (*op_string
)
9397 && !is_identifier_char (*op_string
)
9398 && *op_string
!= '('
9399 && *op_string
!= ABSOLUTE_PREFIX
)
9401 as_bad (_("bad memory operand `%s'"), op_string
);
9404 /* Handle case of %es:*foo. */
9405 if (*op_string
== ABSOLUTE_PREFIX
)
9408 if (is_space_char (*op_string
))
9410 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
9412 goto do_memory_reference
;
9415 /* Handle vector operations. */
9416 if (*op_string
== '{')
9418 op_string
= check_VecOperations (op_string
, NULL
);
9419 if (op_string
== NULL
)
9425 as_bad (_("junk `%s' after register"), op_string
);
9429 temp
.bitfield
.baseindex
= 0;
9430 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
9432 i
.types
[this_operand
].bitfield
.unspecified
= 0;
9433 i
.op
[this_operand
].regs
= r
;
9436 else if (*op_string
== REGISTER_PREFIX
)
9438 as_bad (_("bad register name `%s'"), op_string
);
9441 else if (*op_string
== IMMEDIATE_PREFIX
)
9444 if (i
.types
[this_operand
].bitfield
.jumpabsolute
)
9446 as_bad (_("immediate operand illegal with absolute jump"));
9449 if (!i386_immediate (op_string
))
9452 else if (RC_SAE_immediate (operand_string
))
9454 /* If it is a RC or SAE immediate, do nothing. */
9457 else if (is_digit_char (*op_string
)
9458 || is_identifier_char (*op_string
)
9459 || *op_string
== '"'
9460 || *op_string
== '(')
9462 /* This is a memory reference of some sort. */
9465 /* Start and end of displacement string expression (if found). */
9466 char *displacement_string_start
;
9467 char *displacement_string_end
;
9470 do_memory_reference
:
9471 if (i
.mem_operands
== 1 && !maybe_adjust_templates ())
9473 if ((i
.mem_operands
== 1
9474 && !current_templates
->start
->opcode_modifier
.isstring
)
9475 || i
.mem_operands
== 2)
9477 as_bad (_("too many memory references for `%s'"),
9478 current_templates
->start
->name
);
9482 /* Check for base index form. We detect the base index form by
9483 looking for an ')' at the end of the operand, searching
9484 for the '(' matching it, and finding a REGISTER_PREFIX or ','
9486 base_string
= op_string
+ strlen (op_string
);
9488 /* Handle vector operations. */
9489 vop_start
= strchr (op_string
, '{');
9490 if (vop_start
&& vop_start
< base_string
)
9492 if (check_VecOperations (vop_start
, base_string
) == NULL
)
9494 base_string
= vop_start
;
9498 if (is_space_char (*base_string
))
9501 /* If we only have a displacement, set-up for it to be parsed later. */
9502 displacement_string_start
= op_string
;
9503 displacement_string_end
= base_string
+ 1;
9505 if (*base_string
== ')')
9508 unsigned int parens_balanced
= 1;
9509 /* We've already checked that the number of left & right ()'s are
9510 equal, so this loop will not be infinite. */
9514 if (*base_string
== ')')
9516 if (*base_string
== '(')
9519 while (parens_balanced
);
9521 temp_string
= base_string
;
9523 /* Skip past '(' and whitespace. */
9525 if (is_space_char (*base_string
))
9528 if (*base_string
== ','
9529 || ((i
.base_reg
= parse_register (base_string
, &end_op
))
9532 displacement_string_end
= temp_string
;
9534 i
.types
[this_operand
].bitfield
.baseindex
= 1;
9538 base_string
= end_op
;
9539 if (is_space_char (*base_string
))
9543 /* There may be an index reg or scale factor here. */
9544 if (*base_string
== ',')
9547 if (is_space_char (*base_string
))
9550 if ((i
.index_reg
= parse_register (base_string
, &end_op
))
9553 base_string
= end_op
;
9554 if (is_space_char (*base_string
))
9556 if (*base_string
== ',')
9559 if (is_space_char (*base_string
))
9562 else if (*base_string
!= ')')
9564 as_bad (_("expecting `,' or `)' "
9565 "after index register in `%s'"),
9570 else if (*base_string
== REGISTER_PREFIX
)
9572 end_op
= strchr (base_string
, ',');
9575 as_bad (_("bad register name `%s'"), base_string
);
9579 /* Check for scale factor. */
9580 if (*base_string
!= ')')
9582 char *end_scale
= i386_scale (base_string
);
9587 base_string
= end_scale
;
9588 if (is_space_char (*base_string
))
9590 if (*base_string
!= ')')
9592 as_bad (_("expecting `)' "
9593 "after scale factor in `%s'"),
9598 else if (!i
.index_reg
)
9600 as_bad (_("expecting index register or scale factor "
9601 "after `,'; got '%c'"),
9606 else if (*base_string
!= ')')
9608 as_bad (_("expecting `,' or `)' "
9609 "after base register in `%s'"),
9614 else if (*base_string
== REGISTER_PREFIX
)
9616 end_op
= strchr (base_string
, ',');
9619 as_bad (_("bad register name `%s'"), base_string
);
9624 /* If there's an expression beginning the operand, parse it,
9625 assuming displacement_string_start and
9626 displacement_string_end are meaningful. */
9627 if (displacement_string_start
!= displacement_string_end
)
9629 if (!i386_displacement (displacement_string_start
,
9630 displacement_string_end
))
9634 /* Special case for (%dx) while doing input/output op. */
9636 && i
.base_reg
->reg_type
.bitfield
.inoutportreg
9638 && i
.log2_scale_factor
== 0
9639 && i
.seg
[i
.mem_operands
] == 0
9640 && !operand_type_check (i
.types
[this_operand
], disp
))
9642 i
.types
[this_operand
] = i
.base_reg
->reg_type
;
9646 if (i386_index_check (operand_string
) == 0)
9648 i
.types
[this_operand
].bitfield
.mem
= 1;
9649 if (i
.mem_operands
== 0)
9650 i
.memop1_string
= xstrdup (operand_string
);
9655 /* It's not a memory operand; argh! */
9656 as_bad (_("invalid char %s beginning operand %d `%s'"),
9657 output_invalid (*op_string
),
9662 return 1; /* Normal return. */
9665 /* Calculate the maximum variable size (i.e., excluding fr_fix)
9666 that an rs_machine_dependent frag may reach. */
9669 i386_frag_max_var (fragS
*frag
)
9671 /* The only relaxable frags are for jumps.
9672 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
9673 gas_assert (frag
->fr_type
== rs_machine_dependent
);
9674 return TYPE_FROM_RELAX_STATE (frag
->fr_subtype
) == UNCOND_JUMP
? 4 : 5;
9677 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9679 elf_symbol_resolved_in_segment_p (symbolS
*fr_symbol
, offsetT fr_var
)
9681 /* STT_GNU_IFUNC symbol must go through PLT. */
9682 if ((symbol_get_bfdsym (fr_symbol
)->flags
9683 & BSF_GNU_INDIRECT_FUNCTION
) != 0)
9686 if (!S_IS_EXTERNAL (fr_symbol
))
9687 /* Symbol may be weak or local. */
9688 return !S_IS_WEAK (fr_symbol
);
9690 /* Global symbols with non-default visibility can't be preempted. */
9691 if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol
)) != STV_DEFAULT
)
9694 if (fr_var
!= NO_RELOC
)
9695 switch ((enum bfd_reloc_code_real
) fr_var
)
9697 case BFD_RELOC_386_PLT32
:
9698 case BFD_RELOC_X86_64_PLT32
:
9699 /* Symbol with PLT relocation may be preempted. */
9705 /* Global symbols with default visibility in a shared library may be
9706 preempted by another definition. */
9711 /* md_estimate_size_before_relax()
9713 Called just before relax() for rs_machine_dependent frags. The x86
9714 assembler uses these frags to handle variable size jump
9717 Any symbol that is now undefined will not become defined.
9718 Return the correct fr_subtype in the frag.
9719 Return the initial "guess for variable size of frag" to caller.
9720 The guess is actually the growth beyond the fixed part. Whatever
9721 we do to grow the fixed or variable part contributes to our
9725 md_estimate_size_before_relax (fragS
*fragP
, segT segment
)
9727 /* We've already got fragP->fr_subtype right; all we have to do is
9728 check for un-relaxable symbols. On an ELF system, we can't relax
9729 an externally visible symbol, because it may be overridden by a
9731 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
9732 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9734 && !elf_symbol_resolved_in_segment_p (fragP
->fr_symbol
,
9737 #if defined (OBJ_COFF) && defined (TE_PE)
9738 || (OUTPUT_FLAVOR
== bfd_target_coff_flavour
9739 && S_IS_WEAK (fragP
->fr_symbol
))
9743 /* Symbol is undefined in this segment, or we need to keep a
9744 reloc so that weak symbols can be overridden. */
9745 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
9746 enum bfd_reloc_code_real reloc_type
;
9747 unsigned char *opcode
;
9750 if (fragP
->fr_var
!= NO_RELOC
)
9751 reloc_type
= (enum bfd_reloc_code_real
) fragP
->fr_var
;
9753 reloc_type
= BFD_RELOC_16_PCREL
;
9754 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9755 else if (need_plt32_p (fragP
->fr_symbol
))
9756 reloc_type
= BFD_RELOC_X86_64_PLT32
;
9759 reloc_type
= BFD_RELOC_32_PCREL
;
9761 old_fr_fix
= fragP
->fr_fix
;
9762 opcode
= (unsigned char *) fragP
->fr_opcode
;
9764 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
9767 /* Make jmp (0xeb) a (d)word displacement jump. */
9769 fragP
->fr_fix
+= size
;
9770 fix_new (fragP
, old_fr_fix
, size
,
9772 fragP
->fr_offset
, 1,
9778 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
9780 /* Negate the condition, and branch past an
9781 unconditional jump. */
9784 /* Insert an unconditional jump. */
9786 /* We added two extra opcode bytes, and have a two byte
9788 fragP
->fr_fix
+= 2 + 2;
9789 fix_new (fragP
, old_fr_fix
+ 2, 2,
9791 fragP
->fr_offset
, 1,
9798 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
9803 fixP
= fix_new (fragP
, old_fr_fix
, 1,
9805 fragP
->fr_offset
, 1,
9807 fixP
->fx_signed
= 1;
9811 /* This changes the byte-displacement jump 0x7N
9812 to the (d)word-displacement jump 0x0f,0x8N. */
9813 opcode
[1] = opcode
[0] + 0x10;
9814 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
9815 /* We've added an opcode byte. */
9816 fragP
->fr_fix
+= 1 + size
;
9817 fix_new (fragP
, old_fr_fix
+ 1, size
,
9819 fragP
->fr_offset
, 1,
9824 BAD_CASE (fragP
->fr_subtype
);
9828 return fragP
->fr_fix
- old_fr_fix
;
9831 /* Guess size depending on current relax state. Initially the relax
9832 state will correspond to a short jump and we return 1, because
9833 the variable part of the frag (the branch offset) is one byte
9834 long. However, we can relax a section more than once and in that
9835 case we must either set fr_subtype back to the unrelaxed state,
9836 or return the value for the appropriate branch. */
9837 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
9840 /* Called after relax() is finished.
9842 In: Address of frag.
9843 fr_type == rs_machine_dependent.
9844 fr_subtype is what the address relaxed to.
9846 Out: Any fixSs and constants are set up.
9847 Caller will turn frag into a ".space 0". */
9850 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec ATTRIBUTE_UNUSED
,
9853 unsigned char *opcode
;
9854 unsigned char *where_to_put_displacement
= NULL
;
9855 offsetT target_address
;
9856 offsetT opcode_address
;
9857 unsigned int extension
= 0;
9858 offsetT displacement_from_opcode_start
;
9860 opcode
= (unsigned char *) fragP
->fr_opcode
;
9862 /* Address we want to reach in file space. */
9863 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
9865 /* Address opcode resides at in file space. */
9866 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
9868 /* Displacement from opcode start to fill into instruction. */
9869 displacement_from_opcode_start
= target_address
- opcode_address
;
9871 if ((fragP
->fr_subtype
& BIG
) == 0)
9873 /* Don't have to change opcode. */
9874 extension
= 1; /* 1 opcode + 1 displacement */
9875 where_to_put_displacement
= &opcode
[1];
9879 if (no_cond_jump_promotion
9880 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
9881 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
9882 _("long jump required"));
9884 switch (fragP
->fr_subtype
)
9886 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
9887 extension
= 4; /* 1 opcode + 4 displacement */
9889 where_to_put_displacement
= &opcode
[1];
9892 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
9893 extension
= 2; /* 1 opcode + 2 displacement */
9895 where_to_put_displacement
= &opcode
[1];
9898 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
9899 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
9900 extension
= 5; /* 2 opcode + 4 displacement */
9901 opcode
[1] = opcode
[0] + 0x10;
9902 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
9903 where_to_put_displacement
= &opcode
[2];
9906 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
9907 extension
= 3; /* 2 opcode + 2 displacement */
9908 opcode
[1] = opcode
[0] + 0x10;
9909 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
9910 where_to_put_displacement
= &opcode
[2];
9913 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
9918 where_to_put_displacement
= &opcode
[3];
9922 BAD_CASE (fragP
->fr_subtype
);
9927 /* If size if less then four we are sure that the operand fits,
9928 but if it's 4, then it could be that the displacement is larger
9930 if (DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
) == 4
9932 && ((addressT
) (displacement_from_opcode_start
- extension
9933 + ((addressT
) 1 << 31))
9934 > (((addressT
) 2 << 31) - 1)))
9936 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
9937 _("jump target out of range"));
9938 /* Make us emit 0. */
9939 displacement_from_opcode_start
= extension
;
9941 /* Now put displacement after opcode. */
9942 md_number_to_chars ((char *) where_to_put_displacement
,
9943 (valueT
) (displacement_from_opcode_start
- extension
),
9944 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
9945 fragP
->fr_fix
+= extension
;
9948 /* Apply a fixup (fixP) to segment data, once it has been determined
9949 by our caller that we have all the info we need to fix it up.
9951 Parameter valP is the pointer to the value of the bits.
9953 On the 386, immediates, displacements, and data pointers are all in
9954 the same (little-endian) format, so we don't need to care about which
9958 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
9960 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
9961 valueT value
= *valP
;
9963 #if !defined (TE_Mach)
9966 switch (fixP
->fx_r_type
)
9972 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
9975 case BFD_RELOC_X86_64_32S
:
9976 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
9979 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
9982 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
9987 if (fixP
->fx_addsy
!= NULL
9988 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
9989 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
9990 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
9991 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
9992 && !use_rela_relocations
)
9994 /* This is a hack. There should be a better way to handle this.
9995 This covers for the fact that bfd_install_relocation will
9996 subtract the current location (for partial_inplace, PC relative
9997 relocations); see more below. */
10001 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
10004 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
10006 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10009 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
10011 if ((sym_seg
== seg
10012 || (symbol_section_p (fixP
->fx_addsy
)
10013 && sym_seg
!= absolute_section
))
10014 && !generic_force_reloc (fixP
))
10016 /* Yes, we add the values in twice. This is because
10017 bfd_install_relocation subtracts them out again. I think
10018 bfd_install_relocation is broken, but I don't dare change
10020 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
10024 #if defined (OBJ_COFF) && defined (TE_PE)
10025 /* For some reason, the PE format does not store a
10026 section address offset for a PC relative symbol. */
10027 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
10028 || S_IS_WEAK (fixP
->fx_addsy
))
10029 value
+= md_pcrel_from (fixP
);
10032 #if defined (OBJ_COFF) && defined (TE_PE)
10033 if (fixP
->fx_addsy
!= NULL
10034 && S_IS_WEAK (fixP
->fx_addsy
)
10035 /* PR 16858: Do not modify weak function references. */
10036 && ! fixP
->fx_pcrel
)
10038 #if !defined (TE_PEP)
10039 /* For x86 PE weak function symbols are neither PC-relative
10040 nor do they set S_IS_FUNCTION. So the only reliable way
10041 to detect them is to check the flags of their containing
10043 if (S_GET_SEGMENT (fixP
->fx_addsy
) != NULL
10044 && S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_CODE
)
10048 value
-= S_GET_VALUE (fixP
->fx_addsy
);
10052 /* Fix a few things - the dynamic linker expects certain values here,
10053 and we must not disappoint it. */
10054 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10055 if (IS_ELF
&& fixP
->fx_addsy
)
10056 switch (fixP
->fx_r_type
)
10058 case BFD_RELOC_386_PLT32
:
10059 case BFD_RELOC_X86_64_PLT32
:
10060 /* Make the jump instruction point to the address of the operand. At
10061 runtime we merely add the offset to the actual PLT entry. */
10065 case BFD_RELOC_386_TLS_GD
:
10066 case BFD_RELOC_386_TLS_LDM
:
10067 case BFD_RELOC_386_TLS_IE_32
:
10068 case BFD_RELOC_386_TLS_IE
:
10069 case BFD_RELOC_386_TLS_GOTIE
:
10070 case BFD_RELOC_386_TLS_GOTDESC
:
10071 case BFD_RELOC_X86_64_TLSGD
:
10072 case BFD_RELOC_X86_64_TLSLD
:
10073 case BFD_RELOC_X86_64_GOTTPOFF
:
10074 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
10075 value
= 0; /* Fully resolved at runtime. No addend. */
10077 case BFD_RELOC_386_TLS_LE
:
10078 case BFD_RELOC_386_TLS_LDO_32
:
10079 case BFD_RELOC_386_TLS_LE_32
:
10080 case BFD_RELOC_X86_64_DTPOFF32
:
10081 case BFD_RELOC_X86_64_DTPOFF64
:
10082 case BFD_RELOC_X86_64_TPOFF32
:
10083 case BFD_RELOC_X86_64_TPOFF64
:
10084 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
10087 case BFD_RELOC_386_TLS_DESC_CALL
:
10088 case BFD_RELOC_X86_64_TLSDESC_CALL
:
10089 value
= 0; /* Fully resolved at runtime. No addend. */
10090 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
10094 case BFD_RELOC_VTABLE_INHERIT
:
10095 case BFD_RELOC_VTABLE_ENTRY
:
10102 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
10104 #endif /* !defined (TE_Mach) */
10106 /* Are we finished with this relocation now? */
10107 if (fixP
->fx_addsy
== NULL
)
10109 #if defined (OBJ_COFF) && defined (TE_PE)
10110 else if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
10113 /* Remember value for tc_gen_reloc. */
10114 fixP
->fx_addnumber
= value
;
10115 /* Clear out the frag for now. */
10119 else if (use_rela_relocations
)
10121 fixP
->fx_no_overflow
= 1;
10122 /* Remember value for tc_gen_reloc. */
10123 fixP
->fx_addnumber
= value
;
10127 md_number_to_chars (p
, value
, fixP
->fx_size
);
10131 md_atof (int type
, char *litP
, int *sizeP
)
10133 /* This outputs the LITTLENUMs in REVERSE order;
10134 in accord with the bigendian 386. */
10135 return ieee_md_atof (type
, litP
, sizeP
, FALSE
);
10138 static char output_invalid_buf
[sizeof (unsigned char) * 2 + 6];
10141 output_invalid (int c
)
10144 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
10147 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
10148 "(0x%x)", (unsigned char) c
);
10149 return output_invalid_buf
;
10152 /* REG_STRING starts *before* REGISTER_PREFIX. */
10154 static const reg_entry
*
10155 parse_real_register (char *reg_string
, char **end_op
)
10157 char *s
= reg_string
;
10159 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
10160 const reg_entry
*r
;
10162 /* Skip possible REGISTER_PREFIX and possible whitespace. */
10163 if (*s
== REGISTER_PREFIX
)
10166 if (is_space_char (*s
))
10169 p
= reg_name_given
;
10170 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
10172 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
10173 return (const reg_entry
*) NULL
;
10177 /* For naked regs, make sure that we are not dealing with an identifier.
10178 This prevents confusing an identifier like `eax_var' with register
10180 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
10181 return (const reg_entry
*) NULL
;
10185 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
10187 /* Handle floating point regs, allowing spaces in the (i) part. */
10188 if (r
== i386_regtab
/* %st is first entry of table */)
10190 if (!cpu_arch_flags
.bitfield
.cpu8087
10191 && !cpu_arch_flags
.bitfield
.cpu287
10192 && !cpu_arch_flags
.bitfield
.cpu387
)
10193 return (const reg_entry
*) NULL
;
10195 if (is_space_char (*s
))
10200 if (is_space_char (*s
))
10202 if (*s
>= '0' && *s
<= '7')
10204 int fpr
= *s
- '0';
10206 if (is_space_char (*s
))
10211 r
= (const reg_entry
*) hash_find (reg_hash
, "st(0)");
10216 /* We have "%st(" then garbage. */
10217 return (const reg_entry
*) NULL
;
10221 if (r
== NULL
|| allow_pseudo_reg
)
10224 if (operand_type_all_zero (&r
->reg_type
))
10225 return (const reg_entry
*) NULL
;
10227 if ((r
->reg_type
.bitfield
.dword
10228 || r
->reg_type
.bitfield
.sreg3
10229 || r
->reg_type
.bitfield
.control
10230 || r
->reg_type
.bitfield
.debug
10231 || r
->reg_type
.bitfield
.test
)
10232 && !cpu_arch_flags
.bitfield
.cpui386
)
10233 return (const reg_entry
*) NULL
;
10235 if (r
->reg_type
.bitfield
.regmmx
&& !cpu_arch_flags
.bitfield
.cpummx
)
10236 return (const reg_entry
*) NULL
;
10238 if (!cpu_arch_flags
.bitfield
.cpuavx512f
)
10240 if (r
->reg_type
.bitfield
.zmmword
|| r
->reg_type
.bitfield
.regmask
)
10241 return (const reg_entry
*) NULL
;
10243 if (!cpu_arch_flags
.bitfield
.cpuavx
)
10245 if (r
->reg_type
.bitfield
.ymmword
)
10246 return (const reg_entry
*) NULL
;
10248 if (!cpu_arch_flags
.bitfield
.cpusse
&& r
->reg_type
.bitfield
.xmmword
)
10249 return (const reg_entry
*) NULL
;
10253 if (r
->reg_type
.bitfield
.regbnd
&& !cpu_arch_flags
.bitfield
.cpumpx
)
10254 return (const reg_entry
*) NULL
;
10256 /* Don't allow fake index register unless allow_index_reg isn't 0. */
10257 if (!allow_index_reg
10258 && (r
->reg_num
== RegEiz
|| r
->reg_num
== RegRiz
))
10259 return (const reg_entry
*) NULL
;
10261 /* Upper 16 vector registers are only available with VREX in 64bit
10262 mode, and require EVEX encoding. */
10263 if (r
->reg_flags
& RegVRex
)
10265 if (!cpu_arch_flags
.bitfield
.cpuvrex
10266 || flag_code
!= CODE_64BIT
)
10267 return (const reg_entry
*) NULL
;
10269 i
.vec_encoding
= vex_encoding_evex
;
10272 if (((r
->reg_flags
& (RegRex64
| RegRex
)) || r
->reg_type
.bitfield
.qword
)
10273 && (!cpu_arch_flags
.bitfield
.cpulm
|| !r
->reg_type
.bitfield
.control
)
10274 && flag_code
!= CODE_64BIT
)
10275 return (const reg_entry
*) NULL
;
10277 if (r
->reg_type
.bitfield
.sreg3
&& r
->reg_num
== RegFlat
&& !intel_syntax
)
10278 return (const reg_entry
*) NULL
;
10283 /* REG_STRING starts *before* REGISTER_PREFIX. */
10285 static const reg_entry
*
10286 parse_register (char *reg_string
, char **end_op
)
10288 const reg_entry
*r
;
10290 if (*reg_string
== REGISTER_PREFIX
|| allow_naked_reg
)
10291 r
= parse_real_register (reg_string
, end_op
);
10296 char *save
= input_line_pointer
;
10300 input_line_pointer
= reg_string
;
10301 c
= get_symbol_name (®_string
);
10302 symbolP
= symbol_find (reg_string
);
10303 if (symbolP
&& S_GET_SEGMENT (symbolP
) == reg_section
)
10305 const expressionS
*e
= symbol_get_value_expression (symbolP
);
10307 know (e
->X_op
== O_register
);
10308 know (e
->X_add_number
>= 0
10309 && (valueT
) e
->X_add_number
< i386_regtab_size
);
10310 r
= i386_regtab
+ e
->X_add_number
;
10311 if ((r
->reg_flags
& RegVRex
))
10312 i
.vec_encoding
= vex_encoding_evex
;
10313 *end_op
= input_line_pointer
;
10315 *input_line_pointer
= c
;
10316 input_line_pointer
= save
;
10322 i386_parse_name (char *name
, expressionS
*e
, char *nextcharP
)
10324 const reg_entry
*r
;
10325 char *end
= input_line_pointer
;
10328 r
= parse_register (name
, &input_line_pointer
);
10329 if (r
&& end
<= input_line_pointer
)
10331 *nextcharP
= *input_line_pointer
;
10332 *input_line_pointer
= 0;
10333 e
->X_op
= O_register
;
10334 e
->X_add_number
= r
- i386_regtab
;
10337 input_line_pointer
= end
;
10339 return intel_syntax
? i386_intel_parse_name (name
, e
) : 0;
10343 md_operand (expressionS
*e
)
10346 const reg_entry
*r
;
10348 switch (*input_line_pointer
)
10350 case REGISTER_PREFIX
:
10351 r
= parse_real_register (input_line_pointer
, &end
);
10354 e
->X_op
= O_register
;
10355 e
->X_add_number
= r
- i386_regtab
;
10356 input_line_pointer
= end
;
10361 gas_assert (intel_syntax
);
10362 end
= input_line_pointer
++;
10364 if (*input_line_pointer
== ']')
10366 ++input_line_pointer
;
10367 e
->X_op_symbol
= make_expr_symbol (e
);
10368 e
->X_add_symbol
= NULL
;
10369 e
->X_add_number
= 0;
10374 e
->X_op
= O_absent
;
10375 input_line_pointer
= end
;
10382 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10383 const char *md_shortopts
= "kVQ:sqnO::";
10385 const char *md_shortopts
= "qnO::";
10388 #define OPTION_32 (OPTION_MD_BASE + 0)
10389 #define OPTION_64 (OPTION_MD_BASE + 1)
10390 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
10391 #define OPTION_MARCH (OPTION_MD_BASE + 3)
10392 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
10393 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
10394 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
10395 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
10396 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
10397 #define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 9)
10398 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
10399 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
10400 #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
10401 #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
10402 #define OPTION_X32 (OPTION_MD_BASE + 14)
10403 #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
10404 #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
10405 #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
10406 #define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
10407 #define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
10408 #define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
10409 #define OPTION_MSHARED (OPTION_MD_BASE + 21)
10410 #define OPTION_MAMD64 (OPTION_MD_BASE + 22)
10411 #define OPTION_MINTEL64 (OPTION_MD_BASE + 23)
10412 #define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24)
10414 struct option md_longopts
[] =
10416 {"32", no_argument
, NULL
, OPTION_32
},
10417 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10418 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
10419 {"64", no_argument
, NULL
, OPTION_64
},
10421 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10422 {"x32", no_argument
, NULL
, OPTION_X32
},
10423 {"mshared", no_argument
, NULL
, OPTION_MSHARED
},
10425 {"divide", no_argument
, NULL
, OPTION_DIVIDE
},
10426 {"march", required_argument
, NULL
, OPTION_MARCH
},
10427 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
10428 {"mmnemonic", required_argument
, NULL
, OPTION_MMNEMONIC
},
10429 {"msyntax", required_argument
, NULL
, OPTION_MSYNTAX
},
10430 {"mindex-reg", no_argument
, NULL
, OPTION_MINDEX_REG
},
10431 {"mnaked-reg", no_argument
, NULL
, OPTION_MNAKED_REG
},
10432 {"msse2avx", no_argument
, NULL
, OPTION_MSSE2AVX
},
10433 {"msse-check", required_argument
, NULL
, OPTION_MSSE_CHECK
},
10434 {"moperand-check", required_argument
, NULL
, OPTION_MOPERAND_CHECK
},
10435 {"mavxscalar", required_argument
, NULL
, OPTION_MAVXSCALAR
},
10436 {"madd-bnd-prefix", no_argument
, NULL
, OPTION_MADD_BND_PREFIX
},
10437 {"mevexlig", required_argument
, NULL
, OPTION_MEVEXLIG
},
10438 {"mevexwig", required_argument
, NULL
, OPTION_MEVEXWIG
},
10439 # if defined (TE_PE) || defined (TE_PEP)
10440 {"mbig-obj", no_argument
, NULL
, OPTION_MBIG_OBJ
},
10442 {"momit-lock-prefix", required_argument
, NULL
, OPTION_MOMIT_LOCK_PREFIX
},
10443 {"mfence-as-lock-add", required_argument
, NULL
, OPTION_MFENCE_AS_LOCK_ADD
},
10444 {"mrelax-relocations", required_argument
, NULL
, OPTION_MRELAX_RELOCATIONS
},
10445 {"mevexrcig", required_argument
, NULL
, OPTION_MEVEXRCIG
},
10446 {"mamd64", no_argument
, NULL
, OPTION_MAMD64
},
10447 {"mintel64", no_argument
, NULL
, OPTION_MINTEL64
},
10448 {NULL
, no_argument
, NULL
, 0}
10450 size_t md_longopts_size
= sizeof (md_longopts
);
10453 md_parse_option (int c
, const char *arg
)
10456 char *arch
, *next
, *saved
;
10461 optimize_align_code
= 0;
10465 quiet_warnings
= 1;
10468 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10469 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
10470 should be emitted or not. FIXME: Not implemented. */
10474 /* -V: SVR4 argument to print version ID. */
10476 print_version_id ();
10479 /* -k: Ignore for FreeBSD compatibility. */
10484 /* -s: On i386 Solaris, this tells the native assembler to use
10485 .stab instead of .stab.excl. We always use .stab anyhow. */
10488 case OPTION_MSHARED
:
10492 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10493 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
10496 const char **list
, **l
;
10498 list
= bfd_target_list ();
10499 for (l
= list
; *l
!= NULL
; l
++)
10500 if (CONST_STRNEQ (*l
, "elf64-x86-64")
10501 || strcmp (*l
, "coff-x86-64") == 0
10502 || strcmp (*l
, "pe-x86-64") == 0
10503 || strcmp (*l
, "pei-x86-64") == 0
10504 || strcmp (*l
, "mach-o-x86-64") == 0)
10506 default_arch
= "x86_64";
10510 as_fatal (_("no compiled in support for x86_64"));
10516 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10520 const char **list
, **l
;
10522 list
= bfd_target_list ();
10523 for (l
= list
; *l
!= NULL
; l
++)
10524 if (CONST_STRNEQ (*l
, "elf32-x86-64"))
10526 default_arch
= "x86_64:32";
10530 as_fatal (_("no compiled in support for 32bit x86_64"));
10534 as_fatal (_("32bit x86_64 is only supported for ELF"));
10539 default_arch
= "i386";
10542 case OPTION_DIVIDE
:
10543 #ifdef SVR4_COMMENT_CHARS
10548 n
= XNEWVEC (char, strlen (i386_comment_chars
) + 1);
10550 for (s
= i386_comment_chars
; *s
!= '\0'; s
++)
10554 i386_comment_chars
= n
;
10560 saved
= xstrdup (arg
);
10562 /* Allow -march=+nosse. */
10568 as_fatal (_("invalid -march= option: `%s'"), arg
);
10569 next
= strchr (arch
, '+');
10572 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
10574 if (strcmp (arch
, cpu_arch
[j
].name
) == 0)
10577 if (! cpu_arch
[j
].flags
.bitfield
.cpui386
)
10580 cpu_arch_name
= cpu_arch
[j
].name
;
10581 cpu_sub_arch_name
= NULL
;
10582 cpu_arch_flags
= cpu_arch
[j
].flags
;
10583 cpu_arch_isa
= cpu_arch
[j
].type
;
10584 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
10585 if (!cpu_arch_tune_set
)
10587 cpu_arch_tune
= cpu_arch_isa
;
10588 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
10592 else if (*cpu_arch
[j
].name
== '.'
10593 && strcmp (arch
, cpu_arch
[j
].name
+ 1) == 0)
10595 /* ISA extension. */
10596 i386_cpu_flags flags
;
10598 flags
= cpu_flags_or (cpu_arch_flags
,
10599 cpu_arch
[j
].flags
);
10601 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
10603 if (cpu_sub_arch_name
)
10605 char *name
= cpu_sub_arch_name
;
10606 cpu_sub_arch_name
= concat (name
,
10608 (const char *) NULL
);
10612 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
10613 cpu_arch_flags
= flags
;
10614 cpu_arch_isa_flags
= flags
;
10618 = cpu_flags_or (cpu_arch_isa_flags
,
10619 cpu_arch
[j
].flags
);
10624 if (j
>= ARRAY_SIZE (cpu_arch
))
10626 /* Disable an ISA extension. */
10627 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
10628 if (strcmp (arch
, cpu_noarch
[j
].name
) == 0)
10630 i386_cpu_flags flags
;
10632 flags
= cpu_flags_and_not (cpu_arch_flags
,
10633 cpu_noarch
[j
].flags
);
10634 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
10636 if (cpu_sub_arch_name
)
10638 char *name
= cpu_sub_arch_name
;
10639 cpu_sub_arch_name
= concat (arch
,
10640 (const char *) NULL
);
10644 cpu_sub_arch_name
= xstrdup (arch
);
10645 cpu_arch_flags
= flags
;
10646 cpu_arch_isa_flags
= flags
;
10651 if (j
>= ARRAY_SIZE (cpu_noarch
))
10652 j
= ARRAY_SIZE (cpu_arch
);
10655 if (j
>= ARRAY_SIZE (cpu_arch
))
10656 as_fatal (_("invalid -march= option: `%s'"), arg
);
10660 while (next
!= NULL
);
10666 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
10667 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
10669 if (strcmp (arg
, cpu_arch
[j
].name
) == 0)
10671 cpu_arch_tune_set
= 1;
10672 cpu_arch_tune
= cpu_arch
[j
].type
;
10673 cpu_arch_tune_flags
= cpu_arch
[j
].flags
;
10677 if (j
>= ARRAY_SIZE (cpu_arch
))
10678 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
10681 case OPTION_MMNEMONIC
:
10682 if (strcasecmp (arg
, "att") == 0)
10683 intel_mnemonic
= 0;
10684 else if (strcasecmp (arg
, "intel") == 0)
10685 intel_mnemonic
= 1;
10687 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg
);
10690 case OPTION_MSYNTAX
:
10691 if (strcasecmp (arg
, "att") == 0)
10693 else if (strcasecmp (arg
, "intel") == 0)
10696 as_fatal (_("invalid -msyntax= option: `%s'"), arg
);
10699 case OPTION_MINDEX_REG
:
10700 allow_index_reg
= 1;
10703 case OPTION_MNAKED_REG
:
10704 allow_naked_reg
= 1;
10707 case OPTION_MSSE2AVX
:
10711 case OPTION_MSSE_CHECK
:
10712 if (strcasecmp (arg
, "error") == 0)
10713 sse_check
= check_error
;
10714 else if (strcasecmp (arg
, "warning") == 0)
10715 sse_check
= check_warning
;
10716 else if (strcasecmp (arg
, "none") == 0)
10717 sse_check
= check_none
;
10719 as_fatal (_("invalid -msse-check= option: `%s'"), arg
);
10722 case OPTION_MOPERAND_CHECK
:
10723 if (strcasecmp (arg
, "error") == 0)
10724 operand_check
= check_error
;
10725 else if (strcasecmp (arg
, "warning") == 0)
10726 operand_check
= check_warning
;
10727 else if (strcasecmp (arg
, "none") == 0)
10728 operand_check
= check_none
;
10730 as_fatal (_("invalid -moperand-check= option: `%s'"), arg
);
10733 case OPTION_MAVXSCALAR
:
10734 if (strcasecmp (arg
, "128") == 0)
10735 avxscalar
= vex128
;
10736 else if (strcasecmp (arg
, "256") == 0)
10737 avxscalar
= vex256
;
10739 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg
);
10742 case OPTION_MADD_BND_PREFIX
:
10743 add_bnd_prefix
= 1;
10746 case OPTION_MEVEXLIG
:
10747 if (strcmp (arg
, "128") == 0)
10748 evexlig
= evexl128
;
10749 else if (strcmp (arg
, "256") == 0)
10750 evexlig
= evexl256
;
10751 else if (strcmp (arg
, "512") == 0)
10752 evexlig
= evexl512
;
10754 as_fatal (_("invalid -mevexlig= option: `%s'"), arg
);
10757 case OPTION_MEVEXRCIG
:
10758 if (strcmp (arg
, "rne") == 0)
10760 else if (strcmp (arg
, "rd") == 0)
10762 else if (strcmp (arg
, "ru") == 0)
10764 else if (strcmp (arg
, "rz") == 0)
10767 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg
);
10770 case OPTION_MEVEXWIG
:
10771 if (strcmp (arg
, "0") == 0)
10773 else if (strcmp (arg
, "1") == 0)
10776 as_fatal (_("invalid -mevexwig= option: `%s'"), arg
);
10779 # if defined (TE_PE) || defined (TE_PEP)
10780 case OPTION_MBIG_OBJ
:
10785 case OPTION_MOMIT_LOCK_PREFIX
:
10786 if (strcasecmp (arg
, "yes") == 0)
10787 omit_lock_prefix
= 1;
10788 else if (strcasecmp (arg
, "no") == 0)
10789 omit_lock_prefix
= 0;
10791 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg
);
10794 case OPTION_MFENCE_AS_LOCK_ADD
:
10795 if (strcasecmp (arg
, "yes") == 0)
10797 else if (strcasecmp (arg
, "no") == 0)
10800 as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg
);
10803 case OPTION_MRELAX_RELOCATIONS
:
10804 if (strcasecmp (arg
, "yes") == 0)
10805 generate_relax_relocations
= 1;
10806 else if (strcasecmp (arg
, "no") == 0)
10807 generate_relax_relocations
= 0;
10809 as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg
);
10812 case OPTION_MAMD64
:
10816 case OPTION_MINTEL64
:
10824 /* Turn off -Os. */
10825 optimize_for_space
= 0;
10827 else if (*arg
== 's')
10829 optimize_for_space
= 1;
10830 /* Turn on all encoding optimizations. */
10835 optimize
= atoi (arg
);
10836 /* Turn off -Os. */
10837 optimize_for_space
= 0;
10847 #define MESSAGE_TEMPLATE \
10851 output_message (FILE *stream
, char *p
, char *message
, char *start
,
10852 int *left_p
, const char *name
, int len
)
10854 int size
= sizeof (MESSAGE_TEMPLATE
);
10855 int left
= *left_p
;
10857 /* Reserve 2 spaces for ", " or ",\0" */
10860 /* Check if there is any room. */
10868 p
= mempcpy (p
, name
, len
);
10872 /* Output the current message now and start a new one. */
10875 fprintf (stream
, "%s\n", message
);
10877 left
= size
- (start
- message
) - len
- 2;
10879 gas_assert (left
>= 0);
10881 p
= mempcpy (p
, name
, len
);
10889 show_arch (FILE *stream
, int ext
, int check
)
10891 static char message
[] = MESSAGE_TEMPLATE
;
10892 char *start
= message
+ 27;
10894 int size
= sizeof (MESSAGE_TEMPLATE
);
10901 left
= size
- (start
- message
);
10902 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
10904 /* Should it be skipped? */
10905 if (cpu_arch
[j
].skip
)
10908 name
= cpu_arch
[j
].name
;
10909 len
= cpu_arch
[j
].len
;
10912 /* It is an extension. Skip if we aren't asked to show it. */
10923 /* It is an processor. Skip if we show only extension. */
10926 else if (check
&& ! cpu_arch
[j
].flags
.bitfield
.cpui386
)
10928 /* It is an impossible processor - skip. */
10932 p
= output_message (stream
, p
, message
, start
, &left
, name
, len
);
10935 /* Display disabled extensions. */
10937 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
10939 name
= cpu_noarch
[j
].name
;
10940 len
= cpu_noarch
[j
].len
;
10941 p
= output_message (stream
, p
, message
, start
, &left
, name
,
10946 fprintf (stream
, "%s\n", message
);
10950 md_show_usage (FILE *stream
)
10952 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10953 fprintf (stream
, _("\
10955 -V print assembler version number\n\
10958 fprintf (stream
, _("\
10959 -n Do not optimize code alignment\n\
10960 -q quieten some warnings\n"));
10961 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10962 fprintf (stream
, _("\
10965 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10966 || defined (TE_PE) || defined (TE_PEP))
10967 fprintf (stream
, _("\
10968 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
10970 #ifdef SVR4_COMMENT_CHARS
10971 fprintf (stream
, _("\
10972 --divide do not treat `/' as a comment character\n"));
10974 fprintf (stream
, _("\
10975 --divide ignored\n"));
10977 fprintf (stream
, _("\
10978 -march=CPU[,+EXTENSION...]\n\
10979 generate code for CPU and EXTENSION, CPU is one of:\n"));
10980 show_arch (stream
, 0, 1);
10981 fprintf (stream
, _("\
10982 EXTENSION is combination of:\n"));
10983 show_arch (stream
, 1, 0);
10984 fprintf (stream
, _("\
10985 -mtune=CPU optimize for CPU, CPU is one of:\n"));
10986 show_arch (stream
, 0, 0);
10987 fprintf (stream
, _("\
10988 -msse2avx encode SSE instructions with VEX prefix\n"));
10989 fprintf (stream
, _("\
10990 -msse-check=[none|error|warning]\n\
10991 check SSE instructions\n"));
10992 fprintf (stream
, _("\
10993 -moperand-check=[none|error|warning]\n\
10994 check operand combinations for validity\n"));
10995 fprintf (stream
, _("\
10996 -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n\
10998 fprintf (stream
, _("\
10999 -mevexlig=[128|256|512] encode scalar EVEX instructions with specific vector\n\
11001 fprintf (stream
, _("\
11002 -mevexwig=[0|1] encode EVEX instructions with specific EVEX.W value\n\
11003 for EVEX.W bit ignored instructions\n"));
11004 fprintf (stream
, _("\
11005 -mevexrcig=[rne|rd|ru|rz]\n\
11006 encode EVEX instructions with specific EVEX.RC value\n\
11007 for SAE-only ignored instructions\n"));
11008 fprintf (stream
, _("\
11009 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
11010 fprintf (stream
, _("\
11011 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
11012 fprintf (stream
, _("\
11013 -mindex-reg support pseudo index registers\n"));
11014 fprintf (stream
, _("\
11015 -mnaked-reg don't require `%%' prefix for registers\n"));
11016 fprintf (stream
, _("\
11017 -madd-bnd-prefix add BND prefix for all valid branches\n"));
11018 fprintf (stream
, _("\
11019 -mshared disable branch optimization for shared code\n"));
11020 # if defined (TE_PE) || defined (TE_PEP)
11021 fprintf (stream
, _("\
11022 -mbig-obj generate big object files\n"));
11024 fprintf (stream
, _("\
11025 -momit-lock-prefix=[no|yes]\n\
11026 strip all lock prefixes\n"));
11027 fprintf (stream
, _("\
11028 -mfence-as-lock-add=[no|yes]\n\
11029 encode lfence, mfence and sfence as\n\
11030 lock addl $0x0, (%%{re}sp)\n"));
11031 fprintf (stream
, _("\
11032 -mrelax-relocations=[no|yes]\n\
11033 generate relax relocations\n"));
11034 fprintf (stream
, _("\
11035 -mamd64 accept only AMD64 ISA\n"));
11036 fprintf (stream
, _("\
11037 -mintel64 accept only Intel64 ISA\n"));
11040 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
11041 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
11042 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
11044 /* Pick the target format to use. */
11047 i386_target_format (void)
11049 if (!strncmp (default_arch
, "x86_64", 6))
11051 update_code_flag (CODE_64BIT
, 1);
11052 if (default_arch
[6] == '\0')
11053 x86_elf_abi
= X86_64_ABI
;
11055 x86_elf_abi
= X86_64_X32_ABI
;
11057 else if (!strcmp (default_arch
, "i386"))
11058 update_code_flag (CODE_32BIT
, 1);
11059 else if (!strcmp (default_arch
, "iamcu"))
11061 update_code_flag (CODE_32BIT
, 1);
11062 if (cpu_arch_isa
== PROCESSOR_UNKNOWN
)
11064 static const i386_cpu_flags iamcu_flags
= CPU_IAMCU_FLAGS
;
11065 cpu_arch_name
= "iamcu";
11066 cpu_sub_arch_name
= NULL
;
11067 cpu_arch_flags
= iamcu_flags
;
11068 cpu_arch_isa
= PROCESSOR_IAMCU
;
11069 cpu_arch_isa_flags
= iamcu_flags
;
11070 if (!cpu_arch_tune_set
)
11072 cpu_arch_tune
= cpu_arch_isa
;
11073 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
11076 else if (cpu_arch_isa
!= PROCESSOR_IAMCU
)
11077 as_fatal (_("Intel MCU doesn't support `%s' architecture"),
11081 as_fatal (_("unknown architecture"));
11083 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
11084 cpu_arch_isa_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
11085 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
11086 cpu_arch_tune_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
11088 switch (OUTPUT_FLAVOR
)
11090 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
11091 case bfd_target_aout_flavour
:
11092 return AOUT_TARGET_FORMAT
;
11094 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
11095 # if defined (TE_PE) || defined (TE_PEP)
11096 case bfd_target_coff_flavour
:
11097 if (flag_code
== CODE_64BIT
)
11098 return use_big_obj
? "pe-bigobj-x86-64" : "pe-x86-64";
11101 # elif defined (TE_GO32)
11102 case bfd_target_coff_flavour
:
11103 return "coff-go32";
11105 case bfd_target_coff_flavour
:
11106 return "coff-i386";
11109 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
11110 case bfd_target_elf_flavour
:
11112 const char *format
;
11114 switch (x86_elf_abi
)
11117 format
= ELF_TARGET_FORMAT
;
11120 use_rela_relocations
= 1;
11122 format
= ELF_TARGET_FORMAT64
;
11124 case X86_64_X32_ABI
:
11125 use_rela_relocations
= 1;
11127 disallow_64bit_reloc
= 1;
11128 format
= ELF_TARGET_FORMAT32
;
11131 if (cpu_arch_isa
== PROCESSOR_L1OM
)
11133 if (x86_elf_abi
!= X86_64_ABI
)
11134 as_fatal (_("Intel L1OM is 64bit only"));
11135 return ELF_TARGET_L1OM_FORMAT
;
11137 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
11139 if (x86_elf_abi
!= X86_64_ABI
)
11140 as_fatal (_("Intel K1OM is 64bit only"));
11141 return ELF_TARGET_K1OM_FORMAT
;
11143 else if (cpu_arch_isa
== PROCESSOR_IAMCU
)
11145 if (x86_elf_abi
!= I386_ABI
)
11146 as_fatal (_("Intel MCU is 32bit only"));
11147 return ELF_TARGET_IAMCU_FORMAT
;
11153 #if defined (OBJ_MACH_O)
11154 case bfd_target_mach_o_flavour
:
11155 if (flag_code
== CODE_64BIT
)
11157 use_rela_relocations
= 1;
11159 return "mach-o-x86-64";
11162 return "mach-o-i386";
11170 #endif /* OBJ_MAYBE_ more than one */
11173 md_undefined_symbol (char *name
)
11175 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
11176 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
11177 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
11178 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
11182 if (symbol_find (name
))
11183 as_bad (_("GOT already in symbol table"));
11184 GOT_symbol
= symbol_new (name
, undefined_section
,
11185 (valueT
) 0, &zero_address_frag
);
11192 /* Round up a section size to the appropriate boundary. */
11195 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
11197 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
11198 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
11200 /* For a.out, force the section size to be aligned. If we don't do
11201 this, BFD will align it for us, but it will not write out the
11202 final bytes of the section. This may be a bug in BFD, but it is
11203 easier to fix it here since that is how the other a.out targets
11207 align
= bfd_get_section_alignment (stdoutput
, segment
);
11208 size
= ((size
+ (1 << align
) - 1) & (-((valueT
) 1 << align
)));
11215 /* On the i386, PC-relative offsets are relative to the start of the
11216 next instruction. That is, the address of the offset, plus its
11217 size, since the offset is always the last part of the insn. */
11220 md_pcrel_from (fixS
*fixP
)
11222 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
11228 s_bss (int ignore ATTRIBUTE_UNUSED
)
11232 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11234 obj_elf_section_change_hook ();
11236 temp
= get_absolute_expression ();
11237 subseg_set (bss_section
, (subsegT
) temp
);
11238 demand_empty_rest_of_line ();
11244 i386_validate_fix (fixS
*fixp
)
11246 if (fixp
->fx_subsy
)
11248 if (fixp
->fx_subsy
== GOT_symbol
)
11250 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
11254 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11255 if (fixp
->fx_tcbit2
)
11256 fixp
->fx_r_type
= (fixp
->fx_tcbit
11257 ? BFD_RELOC_X86_64_REX_GOTPCRELX
11258 : BFD_RELOC_X86_64_GOTPCRELX
);
11261 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
11266 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
11268 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
11270 fixp
->fx_subsy
= 0;
11273 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11274 else if (!object_64bit
)
11276 if (fixp
->fx_r_type
== BFD_RELOC_386_GOT32
11277 && fixp
->fx_tcbit2
)
11278 fixp
->fx_r_type
= BFD_RELOC_386_GOT32X
;
11284 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
11287 bfd_reloc_code_real_type code
;
11289 switch (fixp
->fx_r_type
)
11291 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11292 case BFD_RELOC_SIZE32
:
11293 case BFD_RELOC_SIZE64
:
11294 if (S_IS_DEFINED (fixp
->fx_addsy
)
11295 && !S_IS_EXTERNAL (fixp
->fx_addsy
))
11297 /* Resolve size relocation against local symbol to size of
11298 the symbol plus addend. */
11299 valueT value
= S_GET_SIZE (fixp
->fx_addsy
) + fixp
->fx_offset
;
11300 if (fixp
->fx_r_type
== BFD_RELOC_SIZE32
11301 && !fits_in_unsigned_long (value
))
11302 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
11303 _("symbol size computation overflow"));
11304 fixp
->fx_addsy
= NULL
;
11305 fixp
->fx_subsy
= NULL
;
11306 md_apply_fix (fixp
, (valueT
*) &value
, NULL
);
11310 /* Fall through. */
11312 case BFD_RELOC_X86_64_PLT32
:
11313 case BFD_RELOC_X86_64_GOT32
:
11314 case BFD_RELOC_X86_64_GOTPCREL
:
11315 case BFD_RELOC_X86_64_GOTPCRELX
:
11316 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
11317 case BFD_RELOC_386_PLT32
:
11318 case BFD_RELOC_386_GOT32
:
11319 case BFD_RELOC_386_GOT32X
:
11320 case BFD_RELOC_386_GOTOFF
:
11321 case BFD_RELOC_386_GOTPC
:
11322 case BFD_RELOC_386_TLS_GD
:
11323 case BFD_RELOC_386_TLS_LDM
:
11324 case BFD_RELOC_386_TLS_LDO_32
:
11325 case BFD_RELOC_386_TLS_IE_32
:
11326 case BFD_RELOC_386_TLS_IE
:
11327 case BFD_RELOC_386_TLS_GOTIE
:
11328 case BFD_RELOC_386_TLS_LE_32
:
11329 case BFD_RELOC_386_TLS_LE
:
11330 case BFD_RELOC_386_TLS_GOTDESC
:
11331 case BFD_RELOC_386_TLS_DESC_CALL
:
11332 case BFD_RELOC_X86_64_TLSGD
:
11333 case BFD_RELOC_X86_64_TLSLD
:
11334 case BFD_RELOC_X86_64_DTPOFF32
:
11335 case BFD_RELOC_X86_64_DTPOFF64
:
11336 case BFD_RELOC_X86_64_GOTTPOFF
:
11337 case BFD_RELOC_X86_64_TPOFF32
:
11338 case BFD_RELOC_X86_64_TPOFF64
:
11339 case BFD_RELOC_X86_64_GOTOFF64
:
11340 case BFD_RELOC_X86_64_GOTPC32
:
11341 case BFD_RELOC_X86_64_GOT64
:
11342 case BFD_RELOC_X86_64_GOTPCREL64
:
11343 case BFD_RELOC_X86_64_GOTPC64
:
11344 case BFD_RELOC_X86_64_GOTPLT64
:
11345 case BFD_RELOC_X86_64_PLTOFF64
:
11346 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
11347 case BFD_RELOC_X86_64_TLSDESC_CALL
:
11348 case BFD_RELOC_RVA
:
11349 case BFD_RELOC_VTABLE_ENTRY
:
11350 case BFD_RELOC_VTABLE_INHERIT
:
11352 case BFD_RELOC_32_SECREL
:
11354 code
= fixp
->fx_r_type
;
11356 case BFD_RELOC_X86_64_32S
:
11357 if (!fixp
->fx_pcrel
)
11359 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
11360 code
= fixp
->fx_r_type
;
11363 /* Fall through. */
11365 if (fixp
->fx_pcrel
)
11367 switch (fixp
->fx_size
)
11370 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
11371 _("can not do %d byte pc-relative relocation"),
11373 code
= BFD_RELOC_32_PCREL
;
11375 case 1: code
= BFD_RELOC_8_PCREL
; break;
11376 case 2: code
= BFD_RELOC_16_PCREL
; break;
11377 case 4: code
= BFD_RELOC_32_PCREL
; break;
11379 case 8: code
= BFD_RELOC_64_PCREL
; break;
11385 switch (fixp
->fx_size
)
11388 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
11389 _("can not do %d byte relocation"),
11391 code
= BFD_RELOC_32
;
11393 case 1: code
= BFD_RELOC_8
; break;
11394 case 2: code
= BFD_RELOC_16
; break;
11395 case 4: code
= BFD_RELOC_32
; break;
11397 case 8: code
= BFD_RELOC_64
; break;
11404 if ((code
== BFD_RELOC_32
11405 || code
== BFD_RELOC_32_PCREL
11406 || code
== BFD_RELOC_X86_64_32S
)
11408 && fixp
->fx_addsy
== GOT_symbol
)
11411 code
= BFD_RELOC_386_GOTPC
;
11413 code
= BFD_RELOC_X86_64_GOTPC32
;
11415 if ((code
== BFD_RELOC_64
|| code
== BFD_RELOC_64_PCREL
)
11417 && fixp
->fx_addsy
== GOT_symbol
)
11419 code
= BFD_RELOC_X86_64_GOTPC64
;
11422 rel
= XNEW (arelent
);
11423 rel
->sym_ptr_ptr
= XNEW (asymbol
*);
11424 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
11426 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
11428 if (!use_rela_relocations
)
11430 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
11431 vtable entry to be used in the relocation's section offset. */
11432 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
11433 rel
->address
= fixp
->fx_offset
;
11434 #if defined (OBJ_COFF) && defined (TE_PE)
11435 else if (fixp
->fx_addsy
&& S_IS_WEAK (fixp
->fx_addsy
))
11436 rel
->addend
= fixp
->fx_addnumber
- (S_GET_VALUE (fixp
->fx_addsy
) * 2);
11441 /* Use the rela in 64bit mode. */
11444 if (disallow_64bit_reloc
)
11447 case BFD_RELOC_X86_64_DTPOFF64
:
11448 case BFD_RELOC_X86_64_TPOFF64
:
11449 case BFD_RELOC_64_PCREL
:
11450 case BFD_RELOC_X86_64_GOTOFF64
:
11451 case BFD_RELOC_X86_64_GOT64
:
11452 case BFD_RELOC_X86_64_GOTPCREL64
:
11453 case BFD_RELOC_X86_64_GOTPC64
:
11454 case BFD_RELOC_X86_64_GOTPLT64
:
11455 case BFD_RELOC_X86_64_PLTOFF64
:
11456 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
11457 _("cannot represent relocation type %s in x32 mode"),
11458 bfd_get_reloc_code_name (code
));
11464 if (!fixp
->fx_pcrel
)
11465 rel
->addend
= fixp
->fx_offset
;
11469 case BFD_RELOC_X86_64_PLT32
:
11470 case BFD_RELOC_X86_64_GOT32
:
11471 case BFD_RELOC_X86_64_GOTPCREL
:
11472 case BFD_RELOC_X86_64_GOTPCRELX
:
11473 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
11474 case BFD_RELOC_X86_64_TLSGD
:
11475 case BFD_RELOC_X86_64_TLSLD
:
11476 case BFD_RELOC_X86_64_GOTTPOFF
:
11477 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
11478 case BFD_RELOC_X86_64_TLSDESC_CALL
:
11479 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
11482 rel
->addend
= (section
->vma
11484 + fixp
->fx_addnumber
11485 + md_pcrel_from (fixp
));
11490 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
11491 if (rel
->howto
== NULL
)
11493 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
11494 _("cannot represent relocation type %s"),
11495 bfd_get_reloc_code_name (code
));
11496 /* Set howto to a garbage value so that we can keep going. */
11497 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
11498 gas_assert (rel
->howto
!= NULL
);
11504 #include "tc-i386-intel.c"
11507 tc_x86_parse_to_dw2regnum (expressionS
*exp
)
11509 int saved_naked_reg
;
11510 char saved_register_dot
;
11512 saved_naked_reg
= allow_naked_reg
;
11513 allow_naked_reg
= 1;
11514 saved_register_dot
= register_chars
['.'];
11515 register_chars
['.'] = '.';
11516 allow_pseudo_reg
= 1;
11517 expression_and_evaluate (exp
);
11518 allow_pseudo_reg
= 0;
11519 register_chars
['.'] = saved_register_dot
;
11520 allow_naked_reg
= saved_naked_reg
;
11522 if (exp
->X_op
== O_register
&& exp
->X_add_number
>= 0)
11524 if ((addressT
) exp
->X_add_number
< i386_regtab_size
)
11526 exp
->X_op
= O_constant
;
11527 exp
->X_add_number
= i386_regtab
[exp
->X_add_number
]
11528 .dw2_regnum
[flag_code
>> 1];
11531 exp
->X_op
= O_illegal
;
11536 tc_x86_frame_initial_instructions (void)
11538 static unsigned int sp_regno
[2];
11540 if (!sp_regno
[flag_code
>> 1])
11542 char *saved_input
= input_line_pointer
;
11543 char sp
[][4] = {"esp", "rsp"};
11546 input_line_pointer
= sp
[flag_code
>> 1];
11547 tc_x86_parse_to_dw2regnum (&exp
);
11548 gas_assert (exp
.X_op
== O_constant
);
11549 sp_regno
[flag_code
>> 1] = exp
.X_add_number
;
11550 input_line_pointer
= saved_input
;
11553 cfi_add_CFA_def_cfa (sp_regno
[flag_code
>> 1], -x86_cie_data_alignment
);
11554 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
11558 x86_dwarf2_addr_size (void)
11560 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
11561 if (x86_elf_abi
== X86_64_X32_ABI
)
11564 return bfd_arch_bits_per_address (stdoutput
) / 8;
11568 i386_elf_section_type (const char *str
, size_t len
)
11570 if (flag_code
== CODE_64BIT
11571 && len
== sizeof ("unwind") - 1
11572 && strncmp (str
, "unwind", 6) == 0)
11573 return SHT_X86_64_UNWIND
;
11580 i386_solaris_fix_up_eh_frame (segT sec
)
11582 if (flag_code
== CODE_64BIT
)
11583 elf_section_type (sec
) = SHT_X86_64_UNWIND
;
11589 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
11593 exp
.X_op
= O_secrel
;
11594 exp
.X_add_symbol
= symbol
;
11595 exp
.X_add_number
= 0;
11596 emit_expr (&exp
, size
);
11600 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11601 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
11604 x86_64_section_letter (int letter
, const char **ptr_msg
)
11606 if (flag_code
== CODE_64BIT
)
11609 return SHF_X86_64_LARGE
;
11611 *ptr_msg
= _("bad .section directive: want a,l,w,x,M,S,G,T in string");
11614 *ptr_msg
= _("bad .section directive: want a,w,x,M,S,G,T in string");
11619 x86_64_section_word (char *str
, size_t len
)
11621 if (len
== 5 && flag_code
== CODE_64BIT
&& CONST_STRNEQ (str
, "large"))
11622 return SHF_X86_64_LARGE
;
11628 handle_large_common (int small ATTRIBUTE_UNUSED
)
11630 if (flag_code
!= CODE_64BIT
)
11632 s_comm_internal (0, elf_common_parse
);
11633 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
11637 static segT lbss_section
;
11638 asection
*saved_com_section_ptr
= elf_com_section_ptr
;
11639 asection
*saved_bss_section
= bss_section
;
11641 if (lbss_section
== NULL
)
11643 flagword applicable
;
11644 segT seg
= now_seg
;
11645 subsegT subseg
= now_subseg
;
11647 /* The .lbss section is for local .largecomm symbols. */
11648 lbss_section
= subseg_new (".lbss", 0);
11649 applicable
= bfd_applicable_section_flags (stdoutput
);
11650 bfd_set_section_flags (stdoutput
, lbss_section
,
11651 applicable
& SEC_ALLOC
);
11652 seg_info (lbss_section
)->bss
= 1;
11654 subseg_set (seg
, subseg
);
11657 elf_com_section_ptr
= &_bfd_elf_large_com_section
;
11658 bss_section
= lbss_section
;
11660 s_comm_internal (0, elf_common_parse
);
11662 elf_com_section_ptr
= saved_com_section_ptr
;
11663 bss_section
= saved_bss_section
;
11666 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */