1 /* i386.c -- Assemble code for the Intel 80386
2 Copyright (C) 1989, 91, 92, 93, 94, 95, 96, 97, 98, 99, 2000, 2001
3 Free Software Foundation, Inc.
5 This file is part of GAS, the GNU Assembler.
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
22 /* Intel 80386 machine specific gas.
23 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
24 x86_64 support by Jan Hubicka (jh@suse.cz)
25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
32 #include "dwarf2dbg.h"
33 #include "opcode/i386.h"
35 #ifndef REGISTER_WARNINGS
36 #define REGISTER_WARNINGS 1
39 #ifndef INFER_ADDR_PREFIX
40 #define INFER_ADDR_PREFIX 1
43 #ifndef SCALE1_WHEN_NO_INDEX
44 /* Specifying a scale factor besides 1 when there is no index is
45 futile. eg. `mov (%ebx,2),%al' does exactly the same as
46 `mov (%ebx),%al'. To slavishly follow what the programmer
47 specified, set SCALE1_WHEN_NO_INDEX to 0. */
48 #define SCALE1_WHEN_NO_INDEX 1
54 static unsigned int mode_from_disp_size
PARAMS ((unsigned int));
55 static int fits_in_signed_byte
PARAMS ((offsetT
));
56 static int fits_in_unsigned_byte
PARAMS ((offsetT
));
57 static int fits_in_unsigned_word
PARAMS ((offsetT
));
58 static int fits_in_signed_word
PARAMS ((offsetT
));
59 static int fits_in_unsigned_long
PARAMS ((offsetT
));
60 static int fits_in_signed_long
PARAMS ((offsetT
));
61 static int smallest_imm_type
PARAMS ((offsetT
));
62 static offsetT offset_in_range
PARAMS ((offsetT
, int));
63 static int add_prefix
PARAMS ((unsigned int));
64 static void set_code_flag
PARAMS ((int));
65 static void set_16bit_gcc_code_flag
PARAMS ((int));
66 static void set_intel_syntax
PARAMS ((int));
67 static void set_cpu_arch
PARAMS ((int));
70 static bfd_reloc_code_real_type reloc
71 PARAMS ((int, int, int, bfd_reloc_code_real_type
));
75 #define DEFAULT_ARCH "i386"
77 static char *default_arch
= DEFAULT_ARCH
;
79 /* 'md_assemble ()' gathers together information and puts it into a
86 const reg_entry
*regs
;
91 /* TM holds the template for the insn were currently assembling. */
94 /* SUFFIX holds the instruction mnemonic suffix if given.
95 (e.g. 'l' for 'movl') */
98 /* OPERANDS gives the number of given operands. */
99 unsigned int operands
;
101 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
102 of given register, displacement, memory operands and immediate
104 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
106 /* TYPES [i] is the type (see above #defines) which tells us how to
107 use OP[i] for the corresponding operand. */
108 unsigned int types
[MAX_OPERANDS
];
110 /* Displacement expression, immediate expression, or register for each
112 union i386_op op
[MAX_OPERANDS
];
114 /* Flags for operands. */
115 unsigned int flags
[MAX_OPERANDS
];
116 #define Operand_PCrel 1
118 /* Relocation type for operand */
120 enum bfd_reloc_code_real disp_reloc
[MAX_OPERANDS
];
122 int disp_reloc
[MAX_OPERANDS
];
125 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
126 the base index byte below. */
127 const reg_entry
*base_reg
;
128 const reg_entry
*index_reg
;
129 unsigned int log2_scale_factor
;
131 /* SEG gives the seg_entries of this insn. They are zero unless
132 explicit segment overrides are given. */
133 const seg_entry
*seg
[2];
135 /* PREFIX holds all the given prefix opcodes (usually null).
136 PREFIXES is the number of prefix opcodes. */
137 unsigned int prefixes
;
138 unsigned char prefix
[MAX_PREFIXES
];
140 /* RM and SIB are the modrm byte and the sib byte where the
141 addressing modes of this insn are encoded. */
148 typedef struct _i386_insn i386_insn
;
150 /* List of chars besides those in app.c:symbol_chars that can start an
151 operand. Used to prevent the scrubber eating vital white-space. */
153 const char extra_symbol_chars
[] = "*%-(@";
155 const char extra_symbol_chars
[] = "*%-(";
158 /* This array holds the chars that always start a comment. If the
159 pre-processor is disabled, these aren't very useful. */
160 #if defined (TE_I386AIX) || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) && ! defined (TE_LINUX) && !defined(TE_FreeBSD))
161 /* Putting '/' here makes it impossible to use the divide operator.
162 However, we need it for compatibility with SVR4 systems. */
163 const char comment_chars
[] = "#/";
164 #define PREFIX_SEPARATOR '\\'
166 const char comment_chars
[] = "#";
167 #define PREFIX_SEPARATOR '/'
170 /* This array holds the chars that only start a comment at the beginning of
171 a line. If the line seems to have the form '# 123 filename'
172 .line and .file directives will appear in the pre-processed output.
173 Note that input_file.c hand checks for '#' at the beginning of the
174 first line of the input file. This is because the compiler outputs
175 #NO_APP at the beginning of its output.
176 Also note that comments started like this one will always work if
177 '/' isn't otherwise defined. */
178 #if defined (TE_I386AIX) || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) && ! defined (TE_LINUX) && !defined(TE_FreeBSD))
179 const char line_comment_chars
[] = "";
181 const char line_comment_chars
[] = "/";
184 const char line_separator_chars
[] = ";";
186 /* Chars that can be used to separate mant from exp in floating point
188 const char EXP_CHARS
[] = "eE";
190 /* Chars that mean this number is a floating point constant
193 const char FLT_CHARS
[] = "fFdDxX";
195 /* Tables for lexical analysis. */
196 static char mnemonic_chars
[256];
197 static char register_chars
[256];
198 static char operand_chars
[256];
199 static char identifier_chars
[256];
200 static char digit_chars
[256];
202 /* Lexical macros. */
203 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
204 #define is_operand_char(x) (operand_chars[(unsigned char) x])
205 #define is_register_char(x) (register_chars[(unsigned char) x])
206 #define is_space_char(x) ((x) == ' ')
207 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
208 #define is_digit_char(x) (digit_chars[(unsigned char) x])
210 /* All non-digit non-letter charcters that may occur in an operand. */
211 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
213 /* md_assemble() always leaves the strings it's passed unaltered. To
214 effect this we maintain a stack of saved characters that we've smashed
215 with '\0's (indicating end of strings for various sub-fields of the
216 assembler instruction). */
217 static char save_stack
[32];
218 static char *save_stack_p
;
219 #define END_STRING_AND_SAVE(s) \
220 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
221 #define RESTORE_END_STRING(s) \
222 do { *(s) = *--save_stack_p; } while (0)
224 /* The instruction we're assembling. */
227 /* Possible templates for current insn. */
228 static const templates
*current_templates
;
230 /* Per instruction expressionS buffers: 2 displacements & 2 immediate max. */
231 static expressionS disp_expressions
[2], im_expressions
[2];
233 /* Current operand we are working on. */
234 static int this_operand
;
236 /* We support four different modes. FLAG_CODE variable is used to distinguish
244 static enum flag_code flag_code
;
245 static int use_rela_relocations
= 0;
247 /* The names used to print error messages. */
248 static const char *flag_code_names
[] =
255 /* 1 for intel syntax,
257 static int intel_syntax
= 0;
259 /* 1 if register prefix % not required. */
260 static int allow_naked_reg
= 0;
262 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
263 leave, push, and pop instructions so that gcc has the same stack
264 frame as in 32 bit mode. */
265 static char stackop_size
= '\0';
267 /* Non-zero to quieten some warnings. */
268 static int quiet_warnings
= 0;
271 static const char *cpu_arch_name
= NULL
;
273 /* CPU feature flags. */
274 static unsigned int cpu_arch_flags
= CpuUnknownFlags
|CpuNo64
;
276 /* Interface to relax_segment.
277 There are 2 relax states for 386 jump insns: one for conditional &
278 one for unconditional jumps. This is because these two types of
279 jumps add different sizes to frags when we're figuring out what
280 sort of jump to choose to reach a given label. */
284 #define UNCOND_JUMP 2
288 #define SMALL16 (SMALL|CODE16)
290 #define BIG16 (BIG|CODE16)
294 #define INLINE __inline__
300 #define ENCODE_RELAX_STATE(type,size) \
301 ((relax_substateT) ((type<<2) | (size)))
302 #define SIZE_FROM_RELAX_STATE(s) \
303 ( (((s) & 0x3) == BIG ? 4 : (((s) & 0x3) == BIG16 ? 2 : 1)) )
305 /* This table is used by relax_frag to promote short jumps to long
306 ones where necessary. SMALL (short) jumps may be promoted to BIG
307 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
308 don't allow a short jump in a 32 bit code segment to be promoted to
309 a 16 bit offset jump because it's slower (requires data size
310 prefix), and doesn't work, unless the destination is in the bottom
311 64k of the code segment (The top 16 bits of eip are zeroed). */
313 const relax_typeS md_relax_table
[] =
316 1) most positive reach of this state,
317 2) most negative reach of this state,
318 3) how many bytes this mode will add to the size of the current frag
319 4) which index into the table to try if we can't fit into this one. */
325 {127 + 1, -128 + 1, 0, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
326 {127 + 1, -128 + 1, 0, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
327 /* dword conditionals adds 4 bytes to frag:
328 1 extra opcode byte, 3 extra displacement bytes. */
330 /* word conditionals add 2 bytes to frag:
331 1 extra opcode byte, 1 extra displacement byte. */
334 {127 + 1, -128 + 1, 0, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
335 {127 + 1, -128 + 1, 0, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
336 /* dword jmp adds 3 bytes to frag:
337 0 extra opcode bytes, 3 extra displacement bytes. */
339 /* word jmp adds 1 byte to frag:
340 0 extra opcode bytes, 1 extra displacement byte. */
345 static const arch_entry cpu_arch
[] = {
347 {"i186", Cpu086
|Cpu186
},
348 {"i286", Cpu086
|Cpu186
|Cpu286
},
349 {"i386", Cpu086
|Cpu186
|Cpu286
|Cpu386
},
350 {"i486", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
},
351 {"i586", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|CpuMMX
},
352 {"i686", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuMMX
|CpuSSE
},
353 {"pentium", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|CpuMMX
},
354 {"pentiumpro",Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuMMX
|CpuSSE
},
355 {"pentium4", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuP4
|CpuMMX
|CpuSSE
|CpuSSE2
},
356 {"k6", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|CpuK6
|CpuMMX
|Cpu3dnow
},
357 {"athlon", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuK6
|CpuAthlon
|CpuMMX
|Cpu3dnow
},
358 {"sledgehammer",Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuK6
|CpuAthlon
|CpuSledgehammer
|CpuMMX
|Cpu3dnow
|CpuSSE
|CpuSSE2
},
363 i386_align_code (fragP
, count
)
367 /* Various efficient no-op patterns for aligning code labels.
368 Note: Don't try to assemble the instructions in the comments.
369 0L and 0w are not legal. */
370 static const char f32_1
[] =
372 static const char f32_2
[] =
373 {0x89,0xf6}; /* movl %esi,%esi */
374 static const char f32_3
[] =
375 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
376 static const char f32_4
[] =
377 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
378 static const char f32_5
[] =
380 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
381 static const char f32_6
[] =
382 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
383 static const char f32_7
[] =
384 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
385 static const char f32_8
[] =
387 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
388 static const char f32_9
[] =
389 {0x89,0xf6, /* movl %esi,%esi */
390 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
391 static const char f32_10
[] =
392 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
393 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
394 static const char f32_11
[] =
395 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
396 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
397 static const char f32_12
[] =
398 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
399 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
400 static const char f32_13
[] =
401 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
402 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
403 static const char f32_14
[] =
404 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
405 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
406 static const char f32_15
[] =
407 {0xeb,0x0d,0x90,0x90,0x90,0x90,0x90, /* jmp .+15; lotsa nops */
408 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
409 static const char f16_3
[] =
410 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
411 static const char f16_4
[] =
412 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
413 static const char f16_5
[] =
415 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
416 static const char f16_6
[] =
417 {0x89,0xf6, /* mov %si,%si */
418 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
419 static const char f16_7
[] =
420 {0x8d,0x74,0x00, /* lea 0(%si),%si */
421 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
422 static const char f16_8
[] =
423 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
424 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
425 static const char *const f32_patt
[] = {
426 f32_1
, f32_2
, f32_3
, f32_4
, f32_5
, f32_6
, f32_7
, f32_8
,
427 f32_9
, f32_10
, f32_11
, f32_12
, f32_13
, f32_14
, f32_15
429 static const char *const f16_patt
[] = {
430 f32_1
, f32_2
, f16_3
, f16_4
, f16_5
, f16_6
, f16_7
, f16_8
,
431 f32_15
, f32_15
, f32_15
, f32_15
, f32_15
, f32_15
, f32_15
434 /* ??? We can't use these fillers for x86_64, since they often kills the
435 upper halves. Solve later. */
436 if (flag_code
== CODE_64BIT
)
439 if (count
> 0 && count
<= 15)
441 if (flag_code
== CODE_16BIT
)
443 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
444 f16_patt
[count
- 1], count
);
446 /* Adjust jump offset. */
447 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
450 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
451 f32_patt
[count
- 1], count
);
452 fragP
->fr_var
= count
;
456 static char *output_invalid
PARAMS ((int c
));
457 static int i386_operand
PARAMS ((char *operand_string
));
458 static int i386_intel_operand
PARAMS ((char *operand_string
, int got_a_float
));
459 static const reg_entry
*parse_register
PARAMS ((char *reg_string
,
463 static void s_bss
PARAMS ((int));
466 symbolS
*GOT_symbol
; /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
468 static INLINE
unsigned int
469 mode_from_disp_size (t
)
472 return (t
& Disp8
) ? 1 : (t
& (Disp16
| Disp32
| Disp32S
)) ? 2 : 0;
476 fits_in_signed_byte (num
)
479 return (num
>= -128) && (num
<= 127);
483 fits_in_unsigned_byte (num
)
486 return (num
& 0xff) == num
;
490 fits_in_unsigned_word (num
)
493 return (num
& 0xffff) == num
;
497 fits_in_signed_word (num
)
500 return (-32768 <= num
) && (num
<= 32767);
503 fits_in_signed_long (num
)
504 offsetT num ATTRIBUTE_UNUSED
;
509 return (!(((offsetT
) -1 << 31) & num
)
510 || (((offsetT
) -1 << 31) & num
) == ((offsetT
) -1 << 31));
512 } /* fits_in_signed_long() */
514 fits_in_unsigned_long (num
)
515 offsetT num ATTRIBUTE_UNUSED
;
520 return (num
& (((offsetT
) 2 << 31) - 1)) == num
;
522 } /* fits_in_unsigned_long() */
525 smallest_imm_type (num
)
528 if (cpu_arch_flags
!= (Cpu086
| Cpu186
| Cpu286
| Cpu386
| Cpu486
| CpuNo64
)
529 && !(cpu_arch_flags
& (CpuUnknown
)))
531 /* This code is disabled on the 486 because all the Imm1 forms
532 in the opcode table are slower on the i486. They're the
533 versions with the implicitly specified single-position
534 displacement, which has another syntax if you really want to
537 return Imm1
| Imm8
| Imm8S
| Imm16
| Imm32
| Imm32S
| Imm64
;
539 return (fits_in_signed_byte (num
)
540 ? (Imm8S
| Imm8
| Imm16
| Imm32
| Imm32S
| Imm64
)
541 : fits_in_unsigned_byte (num
)
542 ? (Imm8
| Imm16
| Imm32
| Imm32S
| Imm64
)
543 : (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
544 ? (Imm16
| Imm32
| Imm32S
| Imm64
)
545 : fits_in_signed_long (num
)
546 ? (Imm32
| Imm32S
| Imm64
)
547 : fits_in_unsigned_long (num
)
553 offset_in_range (val
, size
)
561 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
562 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
563 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
565 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
570 /* If BFD64, sign extend val. */
571 if (!use_rela_relocations
)
572 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
573 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
575 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
577 char buf1
[40], buf2
[40];
579 sprint_value (buf1
, val
);
580 sprint_value (buf2
, val
& mask
);
581 as_warn (_("%s shortened to %s"), buf1
, buf2
);
586 /* Returns 0 if attempting to add a prefix where one from the same
587 class already exists, 1 if non rep/repne added, 2 if rep/repne
596 if (prefix
>= 0x40 && prefix
< 0x50 && flag_code
== CODE_64BIT
)
604 case CS_PREFIX_OPCODE
:
605 case DS_PREFIX_OPCODE
:
606 case ES_PREFIX_OPCODE
:
607 case FS_PREFIX_OPCODE
:
608 case GS_PREFIX_OPCODE
:
609 case SS_PREFIX_OPCODE
:
613 case REPNE_PREFIX_OPCODE
:
614 case REPE_PREFIX_OPCODE
:
617 case LOCK_PREFIX_OPCODE
:
625 case ADDR_PREFIX_OPCODE
:
629 case DATA_PREFIX_OPCODE
:
636 as_bad (_("same type of prefix used twice"));
641 i
.prefix
[q
] = prefix
;
646 set_code_flag (value
)
650 cpu_arch_flags
&= ~(Cpu64
| CpuNo64
);
651 cpu_arch_flags
|= (flag_code
== CODE_64BIT
? Cpu64
: CpuNo64
);
652 if (value
== CODE_64BIT
&& !(cpu_arch_flags
& CpuSledgehammer
))
654 as_bad (_("64bit mode not supported on this CPU."));
656 if (value
== CODE_32BIT
&& !(cpu_arch_flags
& Cpu386
))
658 as_bad (_("32bit mode not supported on this CPU."));
664 set_16bit_gcc_code_flag (new_code_flag
)
667 flag_code
= new_code_flag
;
668 cpu_arch_flags
&= ~(Cpu64
| CpuNo64
);
669 cpu_arch_flags
|= (flag_code
== CODE_64BIT
? Cpu64
: CpuNo64
);
674 set_intel_syntax (syntax_flag
)
677 /* Find out if register prefixing is specified. */
678 int ask_naked_reg
= 0;
681 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
683 char *string
= input_line_pointer
;
684 int e
= get_symbol_end ();
686 if (strcmp (string
, "prefix") == 0)
688 else if (strcmp (string
, "noprefix") == 0)
691 as_bad (_("bad argument to syntax directive."));
692 *input_line_pointer
= e
;
694 demand_empty_rest_of_line ();
696 intel_syntax
= syntax_flag
;
698 if (ask_naked_reg
== 0)
701 allow_naked_reg
= (intel_syntax
702 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
704 /* Conservative default. */
709 allow_naked_reg
= (ask_naked_reg
< 0);
714 int dummy ATTRIBUTE_UNUSED
;
718 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
720 char *string
= input_line_pointer
;
721 int e
= get_symbol_end ();
724 for (i
= 0; cpu_arch
[i
].name
; i
++)
726 if (strcmp (string
, cpu_arch
[i
].name
) == 0)
728 cpu_arch_name
= cpu_arch
[i
].name
;
729 cpu_arch_flags
= cpu_arch
[i
].flags
| (flag_code
== CODE_64BIT
? Cpu64
: CpuNo64
);
733 if (!cpu_arch
[i
].name
)
734 as_bad (_("no such architecture: `%s'"), string
);
736 *input_line_pointer
= e
;
739 as_bad (_("missing cpu architecture"));
741 demand_empty_rest_of_line ();
744 const pseudo_typeS md_pseudo_table
[] =
746 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
747 {"align", s_align_bytes
, 0},
749 {"align", s_align_ptwo
, 0},
751 {"arch", set_cpu_arch
, 0},
755 {"ffloat", float_cons
, 'f'},
756 {"dfloat", float_cons
, 'd'},
757 {"tfloat", float_cons
, 'x'},
759 {"noopt", s_ignore
, 0},
760 {"optim", s_ignore
, 0},
761 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
762 {"code16", set_code_flag
, CODE_16BIT
},
763 {"code32", set_code_flag
, CODE_32BIT
},
764 {"code64", set_code_flag
, CODE_64BIT
},
765 {"intel_syntax", set_intel_syntax
, 1},
766 {"att_syntax", set_intel_syntax
, 0},
767 {"file", dwarf2_directive_file
, 0},
768 {"loc", dwarf2_directive_loc
, 0},
772 /* For interface with expression (). */
773 extern char *input_line_pointer
;
775 /* Hash table for instruction mnemonic lookup. */
776 static struct hash_control
*op_hash
;
778 /* Hash table for register lookup. */
779 static struct hash_control
*reg_hash
;
784 const char *hash_err
;
786 /* Initialize op_hash hash table. */
787 op_hash
= hash_new ();
790 register const template *optab
;
791 register templates
*core_optab
;
793 /* Setup for loop. */
795 core_optab
= (templates
*) xmalloc (sizeof (templates
));
796 core_optab
->start
= optab
;
801 if (optab
->name
== NULL
802 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
804 /* different name --> ship out current template list;
805 add to hash table; & begin anew. */
806 core_optab
->end
= optab
;
807 hash_err
= hash_insert (op_hash
,
812 as_fatal (_("Internal Error: Can't hash %s: %s"),
816 if (optab
->name
== NULL
)
818 core_optab
= (templates
*) xmalloc (sizeof (templates
));
819 core_optab
->start
= optab
;
824 /* Initialize reg_hash hash table. */
825 reg_hash
= hash_new ();
827 register const reg_entry
*regtab
;
829 for (regtab
= i386_regtab
;
830 regtab
< i386_regtab
+ sizeof (i386_regtab
) / sizeof (i386_regtab
[0]);
833 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (PTR
) regtab
);
835 as_fatal (_("Internal Error: Can't hash %s: %s"),
841 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
846 for (c
= 0; c
< 256; c
++)
851 mnemonic_chars
[c
] = c
;
852 register_chars
[c
] = c
;
853 operand_chars
[c
] = c
;
855 else if (islower (c
))
857 mnemonic_chars
[c
] = c
;
858 register_chars
[c
] = c
;
859 operand_chars
[c
] = c
;
861 else if (isupper (c
))
863 mnemonic_chars
[c
] = tolower (c
);
864 register_chars
[c
] = mnemonic_chars
[c
];
865 operand_chars
[c
] = c
;
868 if (isalpha (c
) || isdigit (c
))
869 identifier_chars
[c
] = c
;
872 identifier_chars
[c
] = c
;
873 operand_chars
[c
] = c
;
878 identifier_chars
['@'] = '@';
880 digit_chars
['-'] = '-';
881 identifier_chars
['_'] = '_';
882 identifier_chars
['.'] = '.';
884 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
885 operand_chars
[(unsigned char) *p
] = *p
;
888 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
889 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
891 record_alignment (text_section
, 2);
892 record_alignment (data_section
, 2);
893 record_alignment (bss_section
, 2);
899 i386_print_statistics (file
)
902 hash_print_statistics (file
, "i386 opcode", op_hash
);
903 hash_print_statistics (file
, "i386 register", reg_hash
);
908 /* Debugging routines for md_assemble. */
909 static void pi
PARAMS ((char *, i386_insn
*));
910 static void pte
PARAMS ((template *));
911 static void pt
PARAMS ((unsigned int));
912 static void pe
PARAMS ((expressionS
*));
913 static void ps
PARAMS ((symbolS
*));
922 fprintf (stdout
, "%s: template ", line
);
924 fprintf (stdout
, " address: base %s index %s scale %x\n",
925 x
->base_reg
? x
->base_reg
->reg_name
: "none",
926 x
->index_reg
? x
->index_reg
->reg_name
: "none",
927 x
->log2_scale_factor
);
928 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
929 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
930 fprintf (stdout
, " sib: base %x index %x scale %x\n",
931 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
932 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
933 x
->rex
.mode64
, x
->rex
.extX
, x
->rex
.extY
, x
->rex
.extZ
);
934 for (i
= 0; i
< x
->operands
; i
++)
936 fprintf (stdout
, " #%d: ", i
+ 1);
938 fprintf (stdout
, "\n");
940 & (Reg
| SReg2
| SReg3
| Control
| Debug
| Test
| RegMMX
| RegXMM
))
941 fprintf (stdout
, "%s\n", x
->op
[i
].regs
->reg_name
);
942 if (x
->types
[i
] & Imm
)
944 if (x
->types
[i
] & Disp
)
954 fprintf (stdout
, " %d operands ", t
->operands
);
955 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
956 if (t
->extension_opcode
!= None
)
957 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
958 if (t
->opcode_modifier
& D
)
959 fprintf (stdout
, "D");
960 if (t
->opcode_modifier
& W
)
961 fprintf (stdout
, "W");
962 fprintf (stdout
, "\n");
963 for (i
= 0; i
< t
->operands
; i
++)
965 fprintf (stdout
, " #%d type ", i
+ 1);
966 pt (t
->operand_types
[i
]);
967 fprintf (stdout
, "\n");
975 fprintf (stdout
, " operation %d\n", e
->X_op
);
976 fprintf (stdout
, " add_number %ld (%lx)\n",
977 (long) e
->X_add_number
, (long) e
->X_add_number
);
980 fprintf (stdout
, " add_symbol ");
981 ps (e
->X_add_symbol
);
982 fprintf (stdout
, "\n");
986 fprintf (stdout
, " op_symbol ");
988 fprintf (stdout
, "\n");
996 fprintf (stdout
, "%s type %s%s",
998 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
999 segment_name (S_GET_SEGMENT (s
)));
1021 { BaseIndex
, "BaseIndex" },
1025 { Disp32S
, "d32s" },
1027 { InOutPortReg
, "InOutPortReg" },
1028 { ShiftCount
, "ShiftCount" },
1029 { Control
, "control reg" },
1030 { Test
, "test reg" },
1031 { Debug
, "debug reg" },
1032 { FloatReg
, "FReg" },
1033 { FloatAcc
, "FAcc" },
1037 { JumpAbsolute
, "Jump Absolute" },
1048 register struct type_name
*ty
;
1050 for (ty
= type_names
; ty
->mask
; ty
++)
1052 fprintf (stdout
, "%s, ", ty
->tname
);
1056 #endif /* DEBUG386 */
1059 tc_i386_force_relocation (fixp
)
1062 #ifdef BFD_ASSEMBLER
1063 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
1064 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
1069 return fixp
->fx_r_type
== 7;
1073 #ifdef BFD_ASSEMBLER
1075 static bfd_reloc_code_real_type
1076 reloc (size
, pcrel
, sign
, other
)
1080 bfd_reloc_code_real_type other
;
1082 if (other
!= NO_RELOC
)
1088 as_bad(_("There are no unsigned pc-relative relocations"));
1091 case 1: return BFD_RELOC_8_PCREL
;
1092 case 2: return BFD_RELOC_16_PCREL
;
1093 case 4: return BFD_RELOC_32_PCREL
;
1095 as_bad (_("can not do %d byte pc-relative relocation"), size
);
1102 case 4: return BFD_RELOC_X86_64_32S
;
1107 case 1: return BFD_RELOC_8
;
1108 case 2: return BFD_RELOC_16
;
1109 case 4: return BFD_RELOC_32
;
1110 case 8: return BFD_RELOC_64
;
1112 as_bad (_("can not do %s %d byte relocation"),
1113 sign
? "signed" : "unsigned", size
);
1117 return BFD_RELOC_NONE
;
1120 /* Here we decide which fixups can be adjusted to make them relative to
1121 the beginning of the section instead of the symbol. Basically we need
1122 to make sure that the dynamic relocations are done correctly, so in
1123 some cases we force the original symbol to be used. */
1126 tc_i386_fix_adjustable (fixP
)
1129 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1130 /* Prevent all adjustments to global symbols, or else dynamic
1131 linking will not work correctly. */
1132 if (S_IS_EXTERNAL (fixP
->fx_addsy
)
1133 || S_IS_WEAK (fixP
->fx_addsy
))
1136 /* adjust_reloc_syms doesn't know about the GOT. */
1137 if (fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
1138 || fixP
->fx_r_type
== BFD_RELOC_386_PLT32
1139 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
1140 || fixP
->fx_r_type
== BFD_RELOC_X86_64_PLT32
1141 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
1142 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
1143 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
1148 #define reloc(SIZE,PCREL,SIGN,OTHER) 0
1149 #define BFD_RELOC_16 0
1150 #define BFD_RELOC_32 0
1151 #define BFD_RELOC_16_PCREL 0
1152 #define BFD_RELOC_32_PCREL 0
1153 #define BFD_RELOC_386_PLT32 0
1154 #define BFD_RELOC_386_GOT32 0
1155 #define BFD_RELOC_386_GOTOFF 0
1156 #define BFD_RELOC_X86_64_PLT32 0
1157 #define BFD_RELOC_X86_64_GOT32 0
1158 #define BFD_RELOC_X86_64_GOTPCREL 0
1161 static int intel_float_operand
PARAMS ((char *mnemonic
));
1164 intel_float_operand (mnemonic
)
1167 if (mnemonic
[0] == 'f' && mnemonic
[1] == 'i')
1170 if (mnemonic
[0] == 'f')
1176 /* This is the guts of the machine-dependent assembler. LINE points to a
1177 machine dependent instruction. This function is supposed to emit
1178 the frags/bytes it assembles to. */
1184 /* Points to template once we've found it. */
1187 /* Count the size of the instruction generated. */
1192 char mnemonic
[MAX_MNEM_SIZE
];
1194 /* Initialize globals. */
1195 memset (&i
, '\0', sizeof (i
));
1196 for (j
= 0; j
< MAX_OPERANDS
; j
++)
1197 i
.disp_reloc
[j
] = NO_RELOC
;
1198 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
1199 memset (im_expressions
, '\0', sizeof (im_expressions
));
1200 save_stack_p
= save_stack
;
1202 /* First parse an instruction mnemonic & call i386_operand for the operands.
1203 We assume that the scrubber has arranged it so that line[0] is the valid
1204 start of a (possibly prefixed) mnemonic. */
1207 char *token_start
= l
;
1210 /* Non-zero if we found a prefix only acceptable with string insns. */
1211 const char *expecting_string_instruction
= NULL
;
1216 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
1219 if (mnem_p
>= mnemonic
+ sizeof (mnemonic
))
1221 as_bad (_("no such instruction: `%s'"), token_start
);
1226 if (!is_space_char (*l
)
1227 && *l
!= END_OF_INSN
1228 && *l
!= PREFIX_SEPARATOR
)
1230 as_bad (_("invalid character %s in mnemonic"),
1231 output_invalid (*l
));
1234 if (token_start
== l
)
1236 if (*l
== PREFIX_SEPARATOR
)
1237 as_bad (_("expecting prefix; got nothing"));
1239 as_bad (_("expecting mnemonic; got nothing"));
1243 /* Look up instruction (or prefix) via hash table. */
1244 current_templates
= hash_find (op_hash
, mnemonic
);
1246 if (*l
!= END_OF_INSN
1247 && (! is_space_char (*l
) || l
[1] != END_OF_INSN
)
1248 && current_templates
1249 && (current_templates
->start
->opcode_modifier
& IsPrefix
))
1251 /* If we are in 16-bit mode, do not allow addr16 or data16.
1252 Similarly, in 32-bit mode, do not allow addr32 or data32. */
1253 if ((current_templates
->start
->opcode_modifier
& (Size16
| Size32
))
1254 && (((current_templates
->start
->opcode_modifier
& Size32
) != 0)
1255 ^ (flag_code
== CODE_16BIT
)))
1257 as_bad (_("redundant %s prefix"),
1258 current_templates
->start
->name
);
1261 /* Add prefix, checking for repeated prefixes. */
1262 switch (add_prefix (current_templates
->start
->base_opcode
))
1267 expecting_string_instruction
= current_templates
->start
->name
;
1270 /* Skip past PREFIX_SEPARATOR and reset token_start. */
1277 if (!current_templates
)
1279 /* See if we can get a match by trimming off a suffix. */
1282 case WORD_MNEM_SUFFIX
:
1283 case BYTE_MNEM_SUFFIX
:
1284 case QWORD_MNEM_SUFFIX
:
1285 i
.suffix
= mnem_p
[-1];
1287 current_templates
= hash_find (op_hash
, mnemonic
);
1289 case SHORT_MNEM_SUFFIX
:
1290 case LONG_MNEM_SUFFIX
:
1293 i
.suffix
= mnem_p
[-1];
1295 current_templates
= hash_find (op_hash
, mnemonic
);
1303 if (intel_float_operand (mnemonic
))
1304 i
.suffix
= SHORT_MNEM_SUFFIX
;
1306 i
.suffix
= LONG_MNEM_SUFFIX
;
1308 current_templates
= hash_find (op_hash
, mnemonic
);
1312 if (!current_templates
)
1314 as_bad (_("no such instruction: `%s'"), token_start
);
1319 /* Check if instruction is supported on specified architecture. */
1320 if (cpu_arch_flags
!= 0)
1322 if ((current_templates
->start
->cpu_flags
& ~(Cpu64
| CpuNo64
))
1323 & ~(cpu_arch_flags
& ~(Cpu64
| CpuNo64
)))
1325 as_warn (_("`%s' is not supported on `%s'"),
1326 current_templates
->start
->name
, cpu_arch_name
);
1328 else if ((Cpu386
& ~cpu_arch_flags
) && (flag_code
!= CODE_16BIT
))
1330 as_warn (_("use .code16 to ensure correct addressing mode"));
1334 /* Check for rep/repne without a string instruction. */
1335 if (expecting_string_instruction
1336 && !(current_templates
->start
->opcode_modifier
& IsString
))
1338 as_bad (_("expecting string instruction after `%s'"),
1339 expecting_string_instruction
);
1343 /* There may be operands to parse. */
1344 if (*l
!= END_OF_INSN
)
1346 /* 1 if operand is pending after ','. */
1347 unsigned int expecting_operand
= 0;
1349 /* Non-zero if operand parens not balanced. */
1350 unsigned int paren_not_balanced
;
1354 /* Skip optional white space before operand. */
1355 if (is_space_char (*l
))
1357 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
)
1359 as_bad (_("invalid character %s before operand %d"),
1360 output_invalid (*l
),
1364 token_start
= l
; /* after white space */
1365 paren_not_balanced
= 0;
1366 while (paren_not_balanced
|| *l
!= ',')
1368 if (*l
== END_OF_INSN
)
1370 if (paren_not_balanced
)
1373 as_bad (_("unbalanced parenthesis in operand %d."),
1376 as_bad (_("unbalanced brackets in operand %d."),
1381 break; /* we are done */
1383 else if (!is_operand_char (*l
) && !is_space_char (*l
))
1385 as_bad (_("invalid character %s in operand %d"),
1386 output_invalid (*l
),
1393 ++paren_not_balanced
;
1395 --paren_not_balanced
;
1400 ++paren_not_balanced
;
1402 --paren_not_balanced
;
1406 if (l
!= token_start
)
1407 { /* Yes, we've read in another operand. */
1408 unsigned int operand_ok
;
1409 this_operand
= i
.operands
++;
1410 if (i
.operands
> MAX_OPERANDS
)
1412 as_bad (_("spurious operands; (%d operands/instruction max)"),
1416 /* Now parse operand adding info to 'i' as we go along. */
1417 END_STRING_AND_SAVE (l
);
1421 i386_intel_operand (token_start
,
1422 intel_float_operand (mnemonic
));
1424 operand_ok
= i386_operand (token_start
);
1426 RESTORE_END_STRING (l
);
1432 if (expecting_operand
)
1434 expecting_operand_after_comma
:
1435 as_bad (_("expecting operand after ','; got nothing"));
1440 as_bad (_("expecting operand before ','; got nothing"));
1445 /* Now *l must be either ',' or END_OF_INSN. */
1448 if (*++l
== END_OF_INSN
)
1450 /* Just skip it, if it's \n complain. */
1451 goto expecting_operand_after_comma
;
1453 expecting_operand
= 1;
1456 while (*l
!= END_OF_INSN
);
1460 /* Now we've parsed the mnemonic into a set of templates, and have the
1463 Next, we find a template that matches the given insn,
1464 making sure the overlap of the given operands types is consistent
1465 with the template operand types. */
1467 #define MATCH(overlap, given, template) \
1468 ((overlap & ~JumpAbsolute) \
1469 && ((given) & (BaseIndex|JumpAbsolute)) == ((overlap) & (BaseIndex|JumpAbsolute)))
1471 /* If given types r0 and r1 are registers they must be of the same type
1472 unless the expected operand type register overlap is null.
1473 Note that Acc in a template matches every size of reg. */
1474 #define CONSISTENT_REGISTER_MATCH(m0, g0, t0, m1, g1, t1) \
1475 ( ((g0) & Reg) == 0 || ((g1) & Reg) == 0 || \
1476 ((g0) & Reg) == ((g1) & Reg) || \
1477 ((((m0) & Acc) ? Reg : (t0)) & (((m1) & Acc) ? Reg : (t1)) & Reg) == 0 )
1480 register unsigned int overlap0
, overlap1
;
1481 unsigned int overlap2
;
1482 unsigned int found_reverse_match
;
1485 /* All intel opcodes have reversed operands except for "bound" and
1486 "enter". We also don't reverse intersegment "jmp" and "call"
1487 instructions with 2 immediate operands so that the immediate segment
1488 precedes the offset, as it does when in AT&T mode. "enter" and the
1489 intersegment "jmp" and "call" instructions are the only ones that
1490 have two immediate operands. */
1491 if (intel_syntax
&& i
.operands
> 1
1492 && (strcmp (mnemonic
, "bound") != 0)
1493 && !((i
.types
[0] & Imm
) && (i
.types
[1] & Imm
)))
1495 union i386_op temp_op
;
1496 unsigned int temp_type
;
1497 #ifdef BFD_ASSEMBLER
1498 enum bfd_reloc_code_real temp_reloc
;
1505 if (i
.operands
== 2)
1510 else if (i
.operands
== 3)
1515 temp_type
= i
.types
[xchg2
];
1516 i
.types
[xchg2
] = i
.types
[xchg1
];
1517 i
.types
[xchg1
] = temp_type
;
1518 temp_op
= i
.op
[xchg2
];
1519 i
.op
[xchg2
] = i
.op
[xchg1
];
1520 i
.op
[xchg1
] = temp_op
;
1521 temp_reloc
= i
.disp_reloc
[xchg2
];
1522 i
.disp_reloc
[xchg2
] = i
.disp_reloc
[xchg1
];
1523 i
.disp_reloc
[xchg1
] = temp_reloc
;
1525 if (i
.mem_operands
== 2)
1527 const seg_entry
*temp_seg
;
1528 temp_seg
= i
.seg
[0];
1529 i
.seg
[0] = i
.seg
[1];
1530 i
.seg
[1] = temp_seg
;
1536 /* Try to ensure constant immediates are represented in the smallest
1538 char guess_suffix
= 0;
1542 guess_suffix
= i
.suffix
;
1543 else if (i
.reg_operands
)
1545 /* Figure out a suffix from the last register operand specified.
1546 We can't do this properly yet, ie. excluding InOutPortReg,
1547 but the following works for instructions with immediates.
1548 In any case, we can't set i.suffix yet. */
1549 for (op
= i
.operands
; --op
>= 0;)
1550 if (i
.types
[op
] & Reg
)
1552 if (i
.types
[op
] & Reg8
)
1553 guess_suffix
= BYTE_MNEM_SUFFIX
;
1554 else if (i
.types
[op
] & Reg16
)
1555 guess_suffix
= WORD_MNEM_SUFFIX
;
1556 else if (i
.types
[op
] & Reg32
)
1557 guess_suffix
= LONG_MNEM_SUFFIX
;
1558 else if (i
.types
[op
] & Reg64
)
1559 guess_suffix
= QWORD_MNEM_SUFFIX
;
1563 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
1564 guess_suffix
= WORD_MNEM_SUFFIX
;
1566 for (op
= i
.operands
; --op
>= 0;)
1567 if (i
.types
[op
] & Imm
)
1569 switch (i
.op
[op
].imms
->X_op
)
1572 /* If a suffix is given, this operand may be shortened. */
1573 switch (guess_suffix
)
1575 case LONG_MNEM_SUFFIX
:
1576 i
.types
[op
] |= Imm32
| Imm64
;
1578 case WORD_MNEM_SUFFIX
:
1579 i
.types
[op
] |= Imm16
| Imm32S
| Imm32
| Imm64
;
1581 case BYTE_MNEM_SUFFIX
:
1582 i
.types
[op
] |= Imm16
| Imm8
| Imm8S
| Imm32S
| Imm32
| Imm64
;
1586 /* If this operand is at most 16 bits, convert it to a
1587 signed 16 bit number before trying to see whether it will
1588 fit in an even smaller size. This allows a 16-bit operand
1589 such as $0xffe0 to be recognised as within Imm8S range. */
1590 if ((i
.types
[op
] & Imm16
)
1591 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
)0xffff) == 0)
1593 i
.op
[op
].imms
->X_add_number
=
1594 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
1596 if ((i
.types
[op
] & Imm32
)
1597 && (i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1)) == 0)
1599 i
.op
[op
].imms
->X_add_number
=
1600 (i
.op
[op
].imms
->X_add_number
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
1602 i
.types
[op
] |= smallest_imm_type (i
.op
[op
].imms
->X_add_number
);
1603 /* We must avoid matching of Imm32 templates when 64bit only immediate is available. */
1604 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
1605 i
.types
[op
] &= ~Imm32
;
1610 /* Symbols and expressions. */
1612 /* Convert symbolic operand to proper sizes for matching. */
1613 switch (guess_suffix
)
1615 case QWORD_MNEM_SUFFIX
:
1616 i
.types
[op
] = Imm64
| Imm32S
;
1618 case LONG_MNEM_SUFFIX
:
1619 i
.types
[op
] = Imm32
| Imm64
;
1621 case WORD_MNEM_SUFFIX
:
1622 i
.types
[op
] = Imm16
| Imm32
| Imm64
;
1625 case BYTE_MNEM_SUFFIX
:
1626 i
.types
[op
] = Imm8
| Imm8S
| Imm16
| Imm32S
| Imm32
;
1635 if (i
.disp_operands
)
1637 /* Try to use the smallest displacement type too. */
1640 for (op
= i
.operands
; --op
>= 0;)
1641 if ((i
.types
[op
] & Disp
)
1642 && i
.op
[op
].imms
->X_op
== O_constant
)
1644 offsetT disp
= i
.op
[op
].disps
->X_add_number
;
1646 if (i
.types
[op
] & Disp16
)
1648 /* We know this operand is at most 16 bits, so
1649 convert to a signed 16 bit number before trying
1650 to see whether it will fit in an even smaller
1653 disp
= (((disp
& 0xffff) ^ 0x8000) - 0x8000);
1655 else if (i
.types
[op
] & Disp32
)
1657 /* We know this operand is at most 32 bits, so convert to a
1658 signed 32 bit number before trying to see whether it will
1659 fit in an even smaller size. */
1660 disp
&= (((offsetT
) 2 << 31) - 1);
1661 disp
= (disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
1663 if (flag_code
== CODE_64BIT
)
1665 if (fits_in_signed_long (disp
))
1666 i
.types
[op
] |= Disp32S
;
1667 if (fits_in_unsigned_long (disp
))
1668 i
.types
[op
] |= Disp32
;
1670 if ((i
.types
[op
] & (Disp32
| Disp32S
| Disp16
))
1671 && fits_in_signed_byte (disp
))
1672 i
.types
[op
] |= Disp8
;
1679 found_reverse_match
= 0;
1680 suffix_check
= (i
.suffix
== BYTE_MNEM_SUFFIX
1682 : (i
.suffix
== WORD_MNEM_SUFFIX
1684 : (i
.suffix
== SHORT_MNEM_SUFFIX
1686 : (i
.suffix
== LONG_MNEM_SUFFIX
1688 : (i
.suffix
== QWORD_MNEM_SUFFIX
1690 : (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
? No_xSuf
: 0))))));
1692 for (t
= current_templates
->start
;
1693 t
< current_templates
->end
;
1696 /* Must have right number of operands. */
1697 if (i
.operands
!= t
->operands
)
1700 /* Check the suffix, except for some instructions in intel mode. */
1701 if ((t
->opcode_modifier
& suffix_check
)
1703 && (t
->opcode_modifier
& IgnoreSize
))
1705 && t
->base_opcode
== 0xd9
1706 && (t
->extension_opcode
== 5 /* 0xd9,5 "fldcw" */
1707 || t
->extension_opcode
== 7))) /* 0xd9,7 "f{n}stcw" */
1710 /* Do not verify operands when there are none. */
1711 else if (!t
->operands
)
1713 if (t
->cpu_flags
& ~cpu_arch_flags
)
1715 /* We've found a match; break out of loop. */
1719 overlap0
= i
.types
[0] & t
->operand_types
[0];
1720 switch (t
->operands
)
1723 if (!MATCH (overlap0
, i
.types
[0], t
->operand_types
[0]))
1728 overlap1
= i
.types
[1] & t
->operand_types
[1];
1729 if (!MATCH (overlap0
, i
.types
[0], t
->operand_types
[0])
1730 || !MATCH (overlap1
, i
.types
[1], t
->operand_types
[1])
1731 || !CONSISTENT_REGISTER_MATCH (overlap0
, i
.types
[0],
1732 t
->operand_types
[0],
1733 overlap1
, i
.types
[1],
1734 t
->operand_types
[1]))
1736 /* Check if other direction is valid ... */
1737 if ((t
->opcode_modifier
& (D
|FloatD
)) == 0)
1740 /* Try reversing direction of operands. */
1741 overlap0
= i
.types
[0] & t
->operand_types
[1];
1742 overlap1
= i
.types
[1] & t
->operand_types
[0];
1743 if (!MATCH (overlap0
, i
.types
[0], t
->operand_types
[1])
1744 || !MATCH (overlap1
, i
.types
[1], t
->operand_types
[0])
1745 || !CONSISTENT_REGISTER_MATCH (overlap0
, i
.types
[0],
1746 t
->operand_types
[1],
1747 overlap1
, i
.types
[1],
1748 t
->operand_types
[0]))
1750 /* Does not match either direction. */
1753 /* found_reverse_match holds which of D or FloatDR
1755 found_reverse_match
= t
->opcode_modifier
& (D
|FloatDR
);
1757 /* Found a forward 2 operand match here. */
1758 else if (t
->operands
== 3)
1760 /* Here we make use of the fact that there are no
1761 reverse match 3 operand instructions, and all 3
1762 operand instructions only need to be checked for
1763 register consistency between operands 2 and 3. */
1764 overlap2
= i
.types
[2] & t
->operand_types
[2];
1765 if (!MATCH (overlap2
, i
.types
[2], t
->operand_types
[2])
1766 || !CONSISTENT_REGISTER_MATCH (overlap1
, i
.types
[1],
1767 t
->operand_types
[1],
1768 overlap2
, i
.types
[2],
1769 t
->operand_types
[2]))
1773 /* Found either forward/reverse 2 or 3 operand match here:
1774 slip through to break. */
1776 if (t
->cpu_flags
& ~cpu_arch_flags
)
1778 found_reverse_match
= 0;
1781 /* We've found a match; break out of loop. */
1784 if (t
== current_templates
->end
)
1786 /* We found no match. */
1787 as_bad (_("suffix or operands invalid for `%s'"),
1788 current_templates
->start
->name
);
1792 if (!quiet_warnings
)
1795 && ((i
.types
[0] & JumpAbsolute
)
1796 != (t
->operand_types
[0] & JumpAbsolute
)))
1798 as_warn (_("indirect %s without `*'"), t
->name
);
1801 if ((t
->opcode_modifier
& (IsPrefix
|IgnoreSize
))
1802 == (IsPrefix
|IgnoreSize
))
1804 /* Warn them that a data or address size prefix doesn't
1805 affect assembly of the next line of code. */
1806 as_warn (_("stand-alone `%s' prefix"), t
->name
);
1810 /* Copy the template we found. */
1812 if (found_reverse_match
)
1814 /* If we found a reverse match we must alter the opcode
1815 direction bit. found_reverse_match holds bits to change
1816 (different for int & float insns). */
1818 i
.tm
.base_opcode
^= found_reverse_match
;
1820 i
.tm
.operand_types
[0] = t
->operand_types
[1];
1821 i
.tm
.operand_types
[1] = t
->operand_types
[0];
1824 /* Undo SYSV386_COMPAT brokenness when in Intel mode. See i386.h */
1827 && (i
.tm
.base_opcode
& 0xfffffde0) == 0xdce0)
1828 i
.tm
.base_opcode
^= FloatR
;
1830 if (i
.tm
.opcode_modifier
& FWait
)
1831 if (! add_prefix (FWAIT_OPCODE
))
1834 /* Check string instruction segment overrides. */
1835 if ((i
.tm
.opcode_modifier
& IsString
) != 0 && i
.mem_operands
!= 0)
1837 int mem_op
= (i
.types
[0] & AnyMem
) ? 0 : 1;
1838 if ((i
.tm
.operand_types
[mem_op
] & EsSeg
) != 0)
1840 if (i
.seg
[0] != NULL
&& i
.seg
[0] != &es
)
1842 as_bad (_("`%s' operand %d must use `%%es' segment"),
1847 /* There's only ever one segment override allowed per instruction.
1848 This instruction possibly has a legal segment override on the
1849 second operand, so copy the segment to where non-string
1850 instructions store it, allowing common code. */
1851 i
.seg
[0] = i
.seg
[1];
1853 else if ((i
.tm
.operand_types
[mem_op
+ 1] & EsSeg
) != 0)
1855 if (i
.seg
[1] != NULL
&& i
.seg
[1] != &es
)
1857 as_bad (_("`%s' operand %d must use `%%es' segment"),
1865 if (i
.reg_operands
&& flag_code
< CODE_64BIT
)
1868 for (op
= i
.operands
; --op
>= 0; )
1869 if ((i
.types
[op
] & Reg
)
1870 && (i
.op
[op
].regs
->reg_flags
& (RegRex64
|RegRex
)))
1872 as_bad (_("Extended register `%%%s' available only in 64bit mode."),
1873 i
.op
[op
].regs
->reg_name
);
1878 /* If matched instruction specifies an explicit instruction mnemonic
1880 if (i
.tm
.opcode_modifier
& (Size16
| Size32
| Size64
))
1882 if (i
.tm
.opcode_modifier
& Size16
)
1883 i
.suffix
= WORD_MNEM_SUFFIX
;
1884 else if (i
.tm
.opcode_modifier
& Size64
)
1885 i
.suffix
= QWORD_MNEM_SUFFIX
;
1887 i
.suffix
= LONG_MNEM_SUFFIX
;
1889 else if (i
.reg_operands
)
1891 /* If there's no instruction mnemonic suffix we try to invent one
1892 based on register operands. */
1895 /* We take i.suffix from the last register operand specified,
1896 Destination register type is more significant than source
1899 for (op
= i
.operands
; --op
>= 0;)
1900 if ((i
.types
[op
] & Reg
)
1901 && !(i
.tm
.operand_types
[op
] & InOutPortReg
))
1903 i
.suffix
= ((i
.types
[op
] & Reg8
) ? BYTE_MNEM_SUFFIX
:
1904 (i
.types
[op
] & Reg16
) ? WORD_MNEM_SUFFIX
:
1905 (i
.types
[op
] & Reg64
) ? QWORD_MNEM_SUFFIX
:
1910 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
1913 for (op
= i
.operands
; --op
>= 0;)
1915 /* If this is an eight bit register, it's OK. If it's
1916 the 16 or 32 bit version of an eight bit register,
1917 we will just use the low portion, and that's OK too. */
1918 if (i
.types
[op
] & Reg8
)
1921 /* movzx and movsx should not generate this warning. */
1923 && (i
.tm
.base_opcode
== 0xfb7
1924 || i
.tm
.base_opcode
== 0xfb6
1925 || i
.tm
.base_opcode
== 0x63
1926 || i
.tm
.base_opcode
== 0xfbe
1927 || i
.tm
.base_opcode
== 0xfbf))
1930 if ((i
.types
[op
] & WordReg
) && i
.op
[op
].regs
->reg_num
< 4
1932 /* Check that the template allows eight bit regs
1933 This kills insns such as `orb $1,%edx', which
1934 maybe should be allowed. */
1935 && (i
.tm
.operand_types
[op
] & (Reg8
|InOutPortReg
))
1939 /* Prohibit these changes in the 64bit mode, since
1940 the lowering is more complicated. */
1941 if (flag_code
== CODE_64BIT
1942 && (i
.tm
.operand_types
[op
] & InOutPortReg
) == 0)
1943 as_bad (_("Incorrect register `%%%s' used with`%c' suffix"),
1944 i
.op
[op
].regs
->reg_name
,
1946 #if REGISTER_WARNINGS
1948 && (i
.tm
.operand_types
[op
] & InOutPortReg
) == 0)
1949 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
1950 (i
.op
[op
].regs
- (i
.types
[op
] & Reg16
? 8 : 16))->reg_name
,
1951 i
.op
[op
].regs
->reg_name
,
1956 /* Any other register is bad. */
1957 if (i
.types
[op
] & (Reg
| RegMMX
| RegXMM
1959 | Control
| Debug
| Test
1960 | FloatReg
| FloatAcc
))
1962 as_bad (_("`%%%s' not allowed with `%s%c'"),
1963 i
.op
[op
].regs
->reg_name
,
1970 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
1974 for (op
= i
.operands
; --op
>= 0;)
1975 /* Reject eight bit registers, except where the template
1976 requires them. (eg. movzb) */
1977 if ((i
.types
[op
] & Reg8
) != 0
1978 && (i
.tm
.operand_types
[op
] & (Reg16
| Reg32
| Acc
)) != 0)
1980 as_bad (_("`%%%s' not allowed with `%s%c'"),
1981 i
.op
[op
].regs
->reg_name
,
1986 /* Warn if the e prefix on a general reg is missing. */
1987 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
1988 && (i
.types
[op
] & Reg16
) != 0
1989 && (i
.tm
.operand_types
[op
] & (Reg32
|Acc
)) != 0)
1991 /* Prohibit these changes in the 64bit mode, since
1992 the lowering is more complicated. */
1993 if (flag_code
== CODE_64BIT
)
1994 as_bad (_("Incorrect register `%%%s' used with`%c' suffix"),
1995 i
.op
[op
].regs
->reg_name
,
1997 #if REGISTER_WARNINGS
1999 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2000 (i
.op
[op
].regs
+ 8)->reg_name
,
2001 i
.op
[op
].regs
->reg_name
,
2005 /* Warn if the r prefix on a general reg is missing. */
2006 else if ((i
.types
[op
] & Reg64
) != 0
2007 && (i
.tm
.operand_types
[op
] & (Reg32
|Acc
)) != 0)
2009 as_bad (_("Incorrect register `%%%s' used with`%c' suffix"),
2010 i
.op
[op
].regs
->reg_name
,
2014 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
2018 for (op
= i
.operands
; --op
>= 0; )
2019 /* Reject eight bit registers, except where the template
2020 requires them. (eg. movzb) */
2021 if ((i
.types
[op
] & Reg8
) != 0
2022 && (i
.tm
.operand_types
[op
] & (Reg16
|Reg32
|Acc
)) != 0)
2024 as_bad (_("`%%%s' not allowed with `%s%c'"),
2025 i
.op
[op
].regs
->reg_name
,
2030 /* Warn if the e prefix on a general reg is missing. */
2031 else if (((i
.types
[op
] & Reg16
) != 0
2032 || (i
.types
[op
] & Reg32
) != 0)
2033 && (i
.tm
.operand_types
[op
] & (Reg32
|Acc
)) != 0)
2035 /* Prohibit these changes in the 64bit mode, since
2036 the lowering is more complicated. */
2037 as_bad (_("Incorrect register `%%%s' used with`%c' suffix"),
2038 i
.op
[op
].regs
->reg_name
,
2042 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
2045 for (op
= i
.operands
; --op
>= 0;)
2046 /* Reject eight bit registers, except where the template
2047 requires them. (eg. movzb) */
2048 if ((i
.types
[op
] & Reg8
) != 0
2049 && (i
.tm
.operand_types
[op
] & (Reg16
|Reg32
|Acc
)) != 0)
2051 as_bad (_("`%%%s' not allowed with `%s%c'"),
2052 i
.op
[op
].regs
->reg_name
,
2057 /* Warn if the e prefix on a general reg is present. */
2058 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
2059 && (i
.types
[op
] & Reg32
) != 0
2060 && (i
.tm
.operand_types
[op
] & (Reg16
|Acc
)) != 0)
2062 /* Prohibit these changes in the 64bit mode, since
2063 the lowering is more complicated. */
2064 if (flag_code
== CODE_64BIT
)
2065 as_bad (_("Incorrect register `%%%s' used with`%c' suffix"),
2066 i
.op
[op
].regs
->reg_name
,
2069 #if REGISTER_WARNINGS
2070 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2071 (i
.op
[op
].regs
- 8)->reg_name
,
2072 i
.op
[op
].regs
->reg_name
,
2077 else if (intel_syntax
&& (i
.tm
.opcode_modifier
& IgnoreSize
))
2078 /* Do nothing if the instruction is going to ignore the prefix. */
2083 else if ((i
.tm
.opcode_modifier
& DefaultSize
) && !i
.suffix
)
2085 i
.suffix
= stackop_size
;
2087 /* Make still unresolved immediate matches conform to size of immediate
2088 given in i.suffix. Note: overlap2 cannot be an immediate! */
2089 if ((overlap0
& (Imm8
| Imm8S
| Imm16
| Imm32
| Imm32S
))
2090 && overlap0
!= Imm8
&& overlap0
!= Imm8S
2091 && overlap0
!= Imm16
&& overlap0
!= Imm32S
2092 && overlap0
!= Imm32
&& overlap0
!= Imm64
)
2096 overlap0
&= (i
.suffix
== BYTE_MNEM_SUFFIX
? (Imm8
| Imm8S
) :
2097 (i
.suffix
== WORD_MNEM_SUFFIX
? Imm16
:
2098 (i
.suffix
== QWORD_MNEM_SUFFIX
? Imm64
| Imm32S
: Imm32
)));
2100 else if (overlap0
== (Imm16
| Imm32S
| Imm32
)
2101 || overlap0
== (Imm16
| Imm32
)
2102 || overlap0
== (Imm16
| Imm32S
))
2105 ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0)) ? Imm16
: Imm32S
;
2107 if (overlap0
!= Imm8
&& overlap0
!= Imm8S
2108 && overlap0
!= Imm16
&& overlap0
!= Imm32S
2109 && overlap0
!= Imm32
&& overlap0
!= Imm64
)
2111 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size"));
2115 if ((overlap1
& (Imm8
| Imm8S
| Imm16
| Imm32S
| Imm32
))
2116 && overlap1
!= Imm8
&& overlap1
!= Imm8S
2117 && overlap1
!= Imm16
&& overlap1
!= Imm32S
2118 && overlap1
!= Imm32
&& overlap1
!= Imm64
)
2122 overlap1
&= (i
.suffix
== BYTE_MNEM_SUFFIX
? (Imm8
| Imm8S
) :
2123 (i
.suffix
== WORD_MNEM_SUFFIX
? Imm16
:
2124 (i
.suffix
== QWORD_MNEM_SUFFIX
? Imm64
| Imm32S
: Imm32
)));
2126 else if (overlap1
== (Imm16
| Imm32
| Imm32S
)
2127 || overlap1
== (Imm16
| Imm32
)
2128 || overlap1
== (Imm16
| Imm32S
))
2131 ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0)) ? Imm16
: Imm32S
;
2133 if (overlap1
!= Imm8
&& overlap1
!= Imm8S
2134 && overlap1
!= Imm16
&& overlap1
!= Imm32S
2135 && overlap1
!= Imm32
&& overlap1
!= Imm64
)
2137 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size %x %c"),overlap1
, i
.suffix
);
2141 assert ((overlap2
& Imm
) == 0);
2143 i
.types
[0] = overlap0
;
2144 if (overlap0
& ImplicitRegister
)
2146 if (overlap0
& Imm1
)
2147 i
.imm_operands
= 0; /* kludge for shift insns. */
2149 i
.types
[1] = overlap1
;
2150 if (overlap1
& ImplicitRegister
)
2153 i
.types
[2] = overlap2
;
2154 if (overlap2
& ImplicitRegister
)
2157 /* Finalize opcode. First, we change the opcode based on the operand
2158 size given by i.suffix: We need not change things for byte insns. */
2160 if (!i
.suffix
&& (i
.tm
.opcode_modifier
& W
))
2162 as_bad (_("no instruction mnemonic suffix given and no register operands; can't size instruction"));
2166 /* For movzx and movsx, need to check the register type. */
2168 && (i
.tm
.base_opcode
== 0xfb6 || i
.tm
.base_opcode
== 0xfbe))
2169 if (i
.suffix
&& i
.suffix
== BYTE_MNEM_SUFFIX
)
2171 unsigned int prefix
= DATA_PREFIX_OPCODE
;
2173 if ((i
.op
[1].regs
->reg_type
& Reg16
) != 0)
2174 if (!add_prefix (prefix
))
2178 if (i
.suffix
&& i
.suffix
!= BYTE_MNEM_SUFFIX
)
2180 /* It's not a byte, select word/dword operation. */
2181 if (i
.tm
.opcode_modifier
& W
)
2183 if (i
.tm
.opcode_modifier
& ShortForm
)
2184 i
.tm
.base_opcode
|= 8;
2186 i
.tm
.base_opcode
|= 1;
2188 /* Now select between word & dword operations via the operand
2189 size prefix, except for instructions that will ignore this
2191 if (i
.suffix
!= QWORD_MNEM_SUFFIX
2192 && (i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
2193 && !(i
.tm
.opcode_modifier
& IgnoreSize
))
2195 unsigned int prefix
= DATA_PREFIX_OPCODE
;
2196 if (i
.tm
.opcode_modifier
& JumpByte
) /* jcxz, loop */
2197 prefix
= ADDR_PREFIX_OPCODE
;
2199 if (! add_prefix (prefix
))
2203 /* Set mode64 for an operand. */
2204 if (i
.suffix
== QWORD_MNEM_SUFFIX
2205 && !(i
.tm
.opcode_modifier
& NoRex64
))
2208 if (flag_code
< CODE_64BIT
)
2210 as_bad (_("64bit operations available only in 64bit modes."));
2215 /* Size floating point instruction. */
2216 if (i
.suffix
== LONG_MNEM_SUFFIX
)
2218 if (i
.tm
.opcode_modifier
& FloatMF
)
2219 i
.tm
.base_opcode
^= 4;
2223 if (i
.tm
.opcode_modifier
& ImmExt
)
2225 /* These AMD 3DNow! and Intel Katmai New Instructions have an
2226 opcode suffix which is coded in the same place as an 8-bit
2227 immediate field would be. Here we fake an 8-bit immediate
2228 operand from the opcode suffix stored in tm.extension_opcode. */
2232 assert (i
.imm_operands
== 0 && i
.operands
<= 2 && 2 < MAX_OPERANDS
);
2234 exp
= &im_expressions
[i
.imm_operands
++];
2235 i
.op
[i
.operands
].imms
= exp
;
2236 i
.types
[i
.operands
++] = Imm8
;
2237 exp
->X_op
= O_constant
;
2238 exp
->X_add_number
= i
.tm
.extension_opcode
;
2239 i
.tm
.extension_opcode
= None
;
2242 /* For insns with operands there are more diddles to do to the opcode. */
2245 /* Default segment register this instruction will use
2246 for memory accesses. 0 means unknown.
2247 This is only for optimizing out unnecessary segment overrides. */
2248 const seg_entry
*default_seg
= 0;
2250 /* The imul $imm, %reg instruction is converted into
2251 imul $imm, %reg, %reg, and the clr %reg instruction
2252 is converted into xor %reg, %reg. */
2253 if (i
.tm
.opcode_modifier
& regKludge
)
2255 unsigned int first_reg_op
= (i
.types
[0] & Reg
) ? 0 : 1;
2256 /* Pretend we saw the extra register operand. */
2257 assert (i
.op
[first_reg_op
+ 1].regs
== 0);
2258 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
2259 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
2263 if (i
.tm
.opcode_modifier
& ShortForm
)
2265 /* The register or float register operand is in operand 0 or 1. */
2266 unsigned int op
= (i
.types
[0] & (Reg
| FloatReg
)) ? 0 : 1;
2267 /* Register goes in low 3 bits of opcode. */
2268 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
2269 if (i
.op
[op
].regs
->reg_flags
& RegRex
)
2271 if (!quiet_warnings
&& (i
.tm
.opcode_modifier
& Ugh
) != 0)
2273 /* Warn about some common errors, but press on regardless.
2274 The first case can be generated by gcc (<= 2.8.1). */
2275 if (i
.operands
== 2)
2277 /* Reversed arguments on faddp, fsubp, etc. */
2278 as_warn (_("translating to `%s %%%s,%%%s'"), i
.tm
.name
,
2279 i
.op
[1].regs
->reg_name
,
2280 i
.op
[0].regs
->reg_name
);
2284 /* Extraneous `l' suffix on fp insn. */
2285 as_warn (_("translating to `%s %%%s'"), i
.tm
.name
,
2286 i
.op
[0].regs
->reg_name
);
2290 else if (i
.tm
.opcode_modifier
& Modrm
)
2292 /* The opcode is completed (modulo i.tm.extension_opcode which
2293 must be put into the modrm byte).
2294 Now, we make the modrm & index base bytes based on all the
2295 info we've collected. */
2297 /* i.reg_operands MUST be the number of real register operands;
2298 implicit registers do not count. */
2299 if (i
.reg_operands
== 2)
2301 unsigned int source
, dest
;
2302 source
= ((i
.types
[0]
2303 & (Reg
| RegMMX
| RegXMM
2305 | Control
| Debug
| Test
))
2310 /* One of the register operands will be encoded in the
2311 i.tm.reg field, the other in the combined i.tm.mode
2312 and i.tm.regmem fields. If no form of this
2313 instruction supports a memory destination operand,
2314 then we assume the source operand may sometimes be
2315 a memory operand and so we need to store the
2316 destination in the i.rm.reg field. */
2317 if ((i
.tm
.operand_types
[dest
] & AnyMem
) == 0)
2319 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
2320 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
2321 if (i
.op
[dest
].regs
->reg_flags
& RegRex
)
2323 if (i
.op
[source
].regs
->reg_flags
& RegRex
)
2328 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
2329 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
2330 if (i
.op
[dest
].regs
->reg_flags
& RegRex
)
2332 if (i
.op
[source
].regs
->reg_flags
& RegRex
)
2337 { /* If it's not 2 reg operands... */
2340 unsigned int fake_zero_displacement
= 0;
2341 unsigned int op
= ((i
.types
[0] & AnyMem
)
2343 : (i
.types
[1] & AnyMem
) ? 1 : 2);
2350 if (! i
.disp_operands
)
2351 fake_zero_displacement
= 1;
2354 /* Operand is just <disp> */
2355 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[ADDR_PREFIX
] != 0))
2357 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
2358 i
.types
[op
] &= ~Disp
;
2359 i
.types
[op
] |= Disp16
;
2361 else if (flag_code
!= CODE_64BIT
)
2363 i
.rm
.regmem
= NO_BASE_REGISTER
;
2364 i
.types
[op
] &= ~Disp
;
2365 i
.types
[op
] |= Disp32
;
2369 /* 64bit mode overwrites the 32bit absolute addressing
2370 by RIP relative addressing and absolute addressing
2371 is encoded by one of the redundant SIB forms. */
2373 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
2374 i
.sib
.base
= NO_BASE_REGISTER
;
2375 i
.sib
.index
= NO_INDEX_REGISTER
;
2376 i
.types
[op
] &= ~Disp
;
2377 i
.types
[op
] |= Disp32S
;
2380 else /* ! i.base_reg && i.index_reg */
2382 i
.sib
.index
= i
.index_reg
->reg_num
;
2383 i
.sib
.base
= NO_BASE_REGISTER
;
2384 i
.sib
.scale
= i
.log2_scale_factor
;
2385 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
2386 i
.types
[op
] &= ~Disp
;
2387 if (flag_code
!= CODE_64BIT
)
2388 i
.types
[op
] |= Disp32
; /* Must be 32 bit */
2390 i
.types
[op
] |= Disp32S
;
2391 if (i
.index_reg
->reg_flags
& RegRex
)
2395 /* RIP addressing for 64bit mode. */
2396 else if (i
.base_reg
->reg_type
== BaseIndex
)
2398 i
.rm
.regmem
= NO_BASE_REGISTER
;
2399 i
.types
[op
] &= ~Disp
;
2400 i
.types
[op
] |= Disp32S
;
2401 i
.flags
[op
] = Operand_PCrel
;
2403 else if (i
.base_reg
->reg_type
& Reg16
)
2405 switch (i
.base_reg
->reg_num
)
2410 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
2411 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
2418 if ((i
.types
[op
] & Disp
) == 0)
2420 /* fake (%bp) into 0(%bp) */
2421 i
.types
[op
] |= Disp8
;
2422 fake_zero_displacement
= 1;
2425 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
2426 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
2428 default: /* (%si) -> 4 or (%di) -> 5 */
2429 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
2431 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
2433 else /* i.base_reg and 32/64 bit mode */
2435 if (flag_code
== CODE_64BIT
2436 && (i
.types
[op
] & Disp
))
2438 if (i
.types
[op
] & Disp8
)
2439 i
.types
[op
] = Disp8
| Disp32S
;
2441 i
.types
[op
] = Disp32S
;
2443 i
.rm
.regmem
= i
.base_reg
->reg_num
;
2444 if (i
.base_reg
->reg_flags
& RegRex
)
2446 i
.sib
.base
= i
.base_reg
->reg_num
;
2447 /* x86-64 ignores REX prefix bit here to avoid
2448 decoder complications. */
2449 if ((i
.base_reg
->reg_num
& 7) == EBP_REG_NUM
)
2452 if (i
.disp_operands
== 0)
2454 fake_zero_displacement
= 1;
2455 i
.types
[op
] |= Disp8
;
2458 else if (i
.base_reg
->reg_num
== ESP_REG_NUM
)
2462 i
.sib
.scale
= i
.log2_scale_factor
;
2465 /* <disp>(%esp) becomes two byte modrm
2466 with no index register. We've already
2467 stored the code for esp in i.rm.regmem
2468 ie. ESCAPE_TO_TWO_BYTE_ADDRESSING. Any
2469 base register besides %esp will not use
2470 the extra modrm byte. */
2471 i
.sib
.index
= NO_INDEX_REGISTER
;
2472 #if ! SCALE1_WHEN_NO_INDEX
2473 /* Another case where we force the second
2475 if (i
.log2_scale_factor
)
2476 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
2481 i
.sib
.index
= i
.index_reg
->reg_num
;
2482 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
2483 if (i
.index_reg
->reg_flags
& RegRex
)
2486 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
2489 if (fake_zero_displacement
)
2491 /* Fakes a zero displacement assuming that i.types[op]
2492 holds the correct displacement size. */
2495 assert (i
.op
[op
].disps
== 0);
2496 exp
= &disp_expressions
[i
.disp_operands
++];
2497 i
.op
[op
].disps
= exp
;
2498 exp
->X_op
= O_constant
;
2499 exp
->X_add_number
= 0;
2500 exp
->X_add_symbol
= (symbolS
*) 0;
2501 exp
->X_op_symbol
= (symbolS
*) 0;
2505 /* Fill in i.rm.reg or i.rm.regmem field with register
2506 operand (if any) based on i.tm.extension_opcode.
2507 Again, we must be careful to make sure that
2508 segment/control/debug/test/MMX registers are coded
2509 into the i.rm.reg field. */
2514 & (Reg
| RegMMX
| RegXMM
2516 | Control
| Debug
| Test
))
2519 & (Reg
| RegMMX
| RegXMM
2521 | Control
| Debug
| Test
))
2524 /* If there is an extension opcode to put here, the
2525 register number must be put into the regmem field. */
2526 if (i
.tm
.extension_opcode
!= None
)
2528 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
2529 if (i
.op
[op
].regs
->reg_flags
& RegRex
)
2534 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
2535 if (i
.op
[op
].regs
->reg_flags
& RegRex
)
2539 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2
2540 we must set it to 3 to indicate this is a register
2541 operand in the regmem field. */
2542 if (!i
.mem_operands
)
2546 /* Fill in i.rm.reg field with extension opcode (if any). */
2547 if (i
.tm
.extension_opcode
!= None
)
2548 i
.rm
.reg
= i
.tm
.extension_opcode
;
2551 else if (i
.tm
.opcode_modifier
& (Seg2ShortForm
| Seg3ShortForm
))
2553 if (i
.tm
.base_opcode
== POP_SEG_SHORT
2554 && i
.op
[0].regs
->reg_num
== 1)
2556 as_bad (_("you can't `pop %%cs'"));
2559 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
2560 if (i
.op
[0].regs
->reg_flags
& RegRex
)
2563 else if ((i
.tm
.base_opcode
& ~(D
|W
)) == MOV_AX_DISP32
)
2567 else if ((i
.tm
.opcode_modifier
& IsString
) != 0)
2569 /* For the string instructions that allow a segment override
2570 on one of their operands, the default segment is ds. */
2574 /* If a segment was explicitly specified,
2575 and the specified segment is not the default,
2576 use an opcode prefix to select it.
2577 If we never figured out what the default segment is,
2578 then default_seg will be zero at this point,
2579 and the specified segment prefix will always be used. */
2580 if ((i
.seg
[0]) && (i
.seg
[0] != default_seg
))
2582 if (! add_prefix (i
.seg
[0]->seg_prefix
))
2586 else if (!quiet_warnings
&& (i
.tm
.opcode_modifier
& Ugh
) != 0)
2588 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
2589 as_warn (_("translating to `%sp'"), i
.tm
.name
);
2593 /* Handle conversion of 'int $3' --> special int3 insn. */
2594 if (i
.tm
.base_opcode
== INT_OPCODE
&& i
.op
[0].imms
->X_add_number
== 3)
2596 i
.tm
.base_opcode
= INT3_OPCODE
;
2600 if ((i
.tm
.opcode_modifier
& (Jump
| JumpByte
| JumpDword
))
2601 && i
.op
[0].disps
->X_op
== O_constant
)
2603 /* Convert "jmp constant" (and "call constant") to a jump (call) to
2604 the absolute address given by the constant. Since ix86 jumps and
2605 calls are pc relative, we need to generate a reloc. */
2606 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
2607 i
.op
[0].disps
->X_op
= O_symbol
;
2610 if (i
.tm
.opcode_modifier
& Rex64
)
2613 /* For 8bit registers we would need an empty rex prefix.
2614 Also in the case instruction is already having prefix,
2615 we need to convert old registers to new ones. */
2617 if (((i
.types
[0] & Reg8
) && (i
.op
[0].regs
->reg_flags
& RegRex64
))
2618 || ((i
.types
[1] & Reg8
) && (i
.op
[1].regs
->reg_flags
& RegRex64
))
2619 || ((i
.rex
.mode64
|| i
.rex
.extX
|| i
.rex
.extY
|| i
.rex
.extZ
|| i
.rex
.empty
)
2620 && ((i
.types
[0] & Reg8
) || (i
.types
[1] & Reg8
))))
2624 for (x
= 0; x
< 2; x
++)
2626 /* Look for 8bit operand that does use old registers. */
2627 if (i
.types
[x
] & Reg8
2628 && !(i
.op
[x
].regs
->reg_flags
& RegRex64
))
2630 /* In case it is "hi" register, give up. */
2631 if (i
.op
[x
].regs
->reg_num
> 3)
2632 as_bad (_("Can't encode registers '%%%s' in the instruction requiring REX prefix.\n"),
2633 i
.op
[x
].regs
->reg_name
);
2635 /* Otherwise it is equivalent to the extended register.
2636 Since the encoding don't change this is merely cosmetical
2637 cleanup for debug output. */
2639 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
2644 if (i
.rex
.mode64
|| i
.rex
.extX
|| i
.rex
.extY
|| i
.rex
.extZ
|| i
.rex
.empty
)
2646 | (i
.rex
.mode64
? 8 : 0)
2647 | (i
.rex
.extX
? 4 : 0)
2648 | (i
.rex
.extY
? 2 : 0)
2649 | (i
.rex
.extZ
? 1 : 0));
2651 /* We are ready to output the insn. */
2656 if (i
.tm
.opcode_modifier
& Jump
)
2663 if (flag_code
== CODE_16BIT
)
2667 if (i
.prefix
[DATA_PREFIX
])
2673 if (i
.prefix
[REX_PREFIX
])
2683 if (i
.prefixes
!= 0 && !intel_syntax
)
2684 as_warn (_("skipping prefixes on this instruction"));
2686 /* It's always a symbol; End frag & setup for relax.
2687 Make sure there is enough room in this frag for the largest
2688 instruction we may generate in md_convert_frag. This is 2
2689 bytes for the opcode and room for the prefix and largest
2691 frag_grow (prefix
+ 2 + size
);
2692 insn_size
+= prefix
+ 1;
2693 /* Prefix and 1 opcode byte go in fr_fix. */
2694 p
= frag_more (prefix
+ 1);
2695 if (i
.prefix
[DATA_PREFIX
])
2696 *p
++ = DATA_PREFIX_OPCODE
;
2697 if (i
.prefix
[REX_PREFIX
])
2698 *p
++ = i
.prefix
[REX_PREFIX
];
2699 *p
= i
.tm
.base_opcode
;
2700 /* 1 possible extra opcode + displacement go in var part.
2701 Pass reloc in fr_var. */
2702 frag_var (rs_machine_dependent
,
2705 ((unsigned char) *p
== JUMP_PC_RELATIVE
2706 ? ENCODE_RELAX_STATE (UNCOND_JUMP
, SMALL
) | code16
2707 : ENCODE_RELAX_STATE (COND_JUMP
, SMALL
) | code16
),
2708 i
.op
[0].disps
->X_add_symbol
,
2709 i
.op
[0].disps
->X_add_number
,
2712 else if (i
.tm
.opcode_modifier
& (JumpByte
| JumpDword
))
2716 if (i
.tm
.opcode_modifier
& JumpByte
)
2718 /* This is a loop or jecxz type instruction. */
2720 if (i
.prefix
[ADDR_PREFIX
])
2723 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
2732 if (flag_code
== CODE_16BIT
)
2735 if (i
.prefix
[DATA_PREFIX
])
2738 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
2748 if (i
.prefix
[REX_PREFIX
])
2750 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
2755 if (i
.prefixes
!= 0 && !intel_syntax
)
2756 as_warn (_("skipping prefixes on this instruction"));
2758 if (fits_in_unsigned_byte (i
.tm
.base_opcode
))
2760 insn_size
+= 1 + size
;
2761 p
= frag_more (1 + size
);
2765 /* Opcode can be at most two bytes. */
2766 insn_size
+= 2 + size
;
2767 p
= frag_more (2 + size
);
2768 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
2770 *p
++ = i
.tm
.base_opcode
& 0xff;
2772 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
2773 i
.op
[0].disps
, 1, reloc (size
, 1, 1, i
.disp_reloc
[0]));
2775 else if (i
.tm
.opcode_modifier
& JumpInterSegment
)
2782 if (flag_code
== CODE_16BIT
)
2786 if (i
.prefix
[DATA_PREFIX
])
2792 if (i
.prefix
[REX_PREFIX
])
2802 if (i
.prefixes
!= 0 && !intel_syntax
)
2803 as_warn (_("skipping prefixes on this instruction"));
2805 /* 1 opcode; 2 segment; offset */
2806 insn_size
+= prefix
+ 1 + 2 + size
;
2807 p
= frag_more (prefix
+ 1 + 2 + size
);
2809 if (i
.prefix
[DATA_PREFIX
])
2810 *p
++ = DATA_PREFIX_OPCODE
;
2812 if (i
.prefix
[REX_PREFIX
])
2813 *p
++ = i
.prefix
[REX_PREFIX
];
2815 *p
++ = i
.tm
.base_opcode
;
2816 if (i
.op
[1].imms
->X_op
== O_constant
)
2818 offsetT n
= i
.op
[1].imms
->X_add_number
;
2821 && !fits_in_unsigned_word (n
)
2822 && !fits_in_signed_word (n
))
2824 as_bad (_("16-bit jump out of range"));
2827 md_number_to_chars (p
, n
, size
);
2830 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
2831 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.disp_reloc
[0]));
2832 if (i
.op
[0].imms
->X_op
!= O_constant
)
2833 as_bad (_("can't handle non absolute segment in `%s'"),
2835 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
2839 /* Output normal instructions here. */
2842 /* All opcodes on i386 have eighter 1 or 2 bytes. We may use third
2843 byte for the SSE instructions to specify prefix they require. */
2844 if (i
.tm
.base_opcode
& 0xff0000)
2845 add_prefix ((i
.tm
.base_opcode
>> 16) & 0xff);
2847 /* The prefix bytes. */
2849 q
< i
.prefix
+ sizeof (i
.prefix
) / sizeof (i
.prefix
[0]);
2856 md_number_to_chars (p
, (valueT
) *q
, 1);
2860 /* Now the opcode; be careful about word order here! */
2861 if (fits_in_unsigned_byte (i
.tm
.base_opcode
))
2864 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
2870 /* Put out high byte first: can't use md_number_to_chars! */
2871 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
2872 *p
= i
.tm
.base_opcode
& 0xff;
2875 /* Now the modrm byte and sib byte (if present). */
2876 if (i
.tm
.opcode_modifier
& Modrm
)
2880 md_number_to_chars (p
,
2881 (valueT
) (i
.rm
.regmem
<< 0
2885 /* If i.rm.regmem == ESP (4)
2886 && i.rm.mode != (Register mode)
2888 ==> need second modrm byte. */
2889 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
2891 && !(i
.base_reg
&& (i
.base_reg
->reg_type
& Reg16
) != 0))
2895 md_number_to_chars (p
,
2896 (valueT
) (i
.sib
.base
<< 0
2898 | i
.sib
.scale
<< 6),
2903 if (i
.disp_operands
)
2905 register unsigned int n
;
2907 for (n
= 0; n
< i
.operands
; n
++)
2909 if (i
.types
[n
] & Disp
)
2911 if (i
.op
[n
].disps
->X_op
== O_constant
)
2917 if (i
.types
[n
] & (Disp8
| Disp16
| Disp64
))
2920 if (i
.types
[n
] & Disp8
)
2922 if (i
.types
[n
] & Disp64
)
2925 val
= offset_in_range (i
.op
[n
].disps
->X_add_number
,
2928 p
= frag_more (size
);
2929 md_number_to_chars (p
, val
, size
);
2935 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
2937 /* The PC relative address is computed relative
2938 to the instruction boundary, so in case immediate
2939 fields follows, we need to adjust the value. */
2940 if (pcrel
&& i
.imm_operands
)
2943 register unsigned int n1
;
2945 for (n1
= 0; n1
< i
.operands
; n1
++)
2946 if (i
.types
[n1
] & Imm
)
2948 if (i
.types
[n1
] & (Imm8
| Imm8S
| Imm16
| Imm64
))
2951 if (i
.types
[n1
] & (Imm8
| Imm8S
))
2953 if (i
.types
[n1
] & Imm64
)
2958 /* We should find the immediate. */
2959 if (n1
== i
.operands
)
2961 i
.op
[n
].disps
->X_add_number
-= imm_size
;
2964 if (i
.types
[n
] & Disp32S
)
2967 if (i
.types
[n
] & (Disp16
| Disp64
))
2970 if (i
.types
[n
] & Disp64
)
2975 p
= frag_more (size
);
2976 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
2977 i
.op
[n
].disps
, pcrel
,
2978 reloc (size
, pcrel
, sign
, i
.disp_reloc
[n
]));
2984 /* Output immediate. */
2987 register unsigned int n
;
2989 for (n
= 0; n
< i
.operands
; n
++)
2991 if (i
.types
[n
] & Imm
)
2993 if (i
.op
[n
].imms
->X_op
== O_constant
)
2999 if (i
.types
[n
] & (Imm8
| Imm8S
| Imm16
| Imm64
))
3002 if (i
.types
[n
] & (Imm8
| Imm8S
))
3004 else if (i
.types
[n
] & Imm64
)
3007 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
3010 p
= frag_more (size
);
3011 md_number_to_chars (p
, val
, size
);
3015 /* Not absolute_section.
3016 Need a 32-bit fixup (don't support 8bit
3017 non-absolute imms). Try to support other
3019 #ifdef BFD_ASSEMBLER
3020 enum bfd_reloc_code_real reloc_type
;
3027 if ((i
.types
[n
] & (Imm32S
))
3028 && i
.suffix
== QWORD_MNEM_SUFFIX
)
3030 if (i
.types
[n
] & (Imm8
| Imm8S
| Imm16
| Imm64
))
3033 if (i
.types
[n
] & (Imm8
| Imm8S
))
3035 if (i
.types
[n
] & Imm64
)
3040 p
= frag_more (size
);
3041 reloc_type
= reloc (size
, 0, sign
, i
.disp_reloc
[0]);
3042 #ifdef BFD_ASSEMBLER
3043 if (reloc_type
== BFD_RELOC_32
3045 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
3046 && (i
.op
[n
].imms
->X_op
== O_symbol
3047 || (i
.op
[n
].imms
->X_op
== O_add
3048 && ((symbol_get_value_expression
3049 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
3052 /* We don't support dynamic linking on x86-64 yet. */
3053 if (flag_code
== CODE_64BIT
)
3055 reloc_type
= BFD_RELOC_386_GOTPC
;
3056 i
.op
[n
].imms
->X_add_number
+= 3;
3059 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
3060 i
.op
[n
].imms
, 0, reloc_type
);
3067 dwarf2_emit_insn (insn_size
);
3074 #endif /* DEBUG386 */
3078 static int i386_immediate
PARAMS ((char *));
3081 i386_immediate (imm_start
)
3084 char *save_input_line_pointer
;
3088 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
3090 as_bad (_("only 1 or 2 immediate operands are allowed"));
3094 exp
= &im_expressions
[i
.imm_operands
++];
3095 i
.op
[this_operand
].imms
= exp
;
3097 if (is_space_char (*imm_start
))
3100 save_input_line_pointer
= input_line_pointer
;
3101 input_line_pointer
= imm_start
;
3105 /* We can have operands of the form
3106 <symbol>@GOTOFF+<nnn>
3107 Take the easy way out here and copy everything
3108 into a temporary buffer... */
3111 cp
= strchr (input_line_pointer
, '@');
3118 /* GOT relocations are not supported in 16 bit mode. */
3119 if (flag_code
== CODE_16BIT
)
3120 as_bad (_("GOT relocations not supported in 16 bit mode"));
3122 if (GOT_symbol
== NULL
)
3123 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
3125 if (strncmp (cp
+ 1, "PLT", 3) == 0)
3127 if (flag_code
== CODE_64BIT
)
3128 i
.disp_reloc
[this_operand
] = BFD_RELOC_X86_64_PLT32
;
3130 i
.disp_reloc
[this_operand
] = BFD_RELOC_386_PLT32
;
3133 else if (strncmp (cp
+ 1, "GOTOFF", 6) == 0)
3135 if (flag_code
== CODE_64BIT
)
3136 as_bad ("GOTOFF relocations are unsupported in 64bit mode.");
3137 i
.disp_reloc
[this_operand
] = BFD_RELOC_386_GOTOFF
;
3140 else if (strncmp (cp
+ 1, "GOTPCREL", 8) == 0)
3142 if (flag_code
== CODE_64BIT
)
3143 i
.disp_reloc
[this_operand
] = BFD_RELOC_X86_64_GOTPCREL
;
3145 as_bad ("GOTPCREL relocations are supported only in 64bit mode.");
3148 else if (strncmp (cp
+ 1, "GOT", 3) == 0)
3150 if (flag_code
== CODE_64BIT
)
3151 i
.disp_reloc
[this_operand
] = BFD_RELOC_X86_64_GOT32
;
3153 i
.disp_reloc
[this_operand
] = BFD_RELOC_386_GOT32
;
3157 as_bad (_("bad reloc specifier in expression"));
3159 /* Replace the relocation token with ' ', so that errors like
3160 foo@GOTOFF1 will be detected. */
3161 first
= cp
- input_line_pointer
;
3162 tmpbuf
= (char *) alloca (strlen (input_line_pointer
));
3163 memcpy (tmpbuf
, input_line_pointer
, first
);
3164 tmpbuf
[first
] = ' ';
3165 strcpy (tmpbuf
+ first
+ 1, cp
+ 1 + len
);
3166 input_line_pointer
= tmpbuf
;
3171 exp_seg
= expression (exp
);
3174 if (*input_line_pointer
)
3175 as_bad (_("ignoring junk `%s' after expression"), input_line_pointer
);
3177 input_line_pointer
= save_input_line_pointer
;
3179 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_big
)
3181 /* Missing or bad expr becomes absolute 0. */
3182 as_bad (_("missing or invalid immediate expression `%s' taken as 0"),
3184 exp
->X_op
= O_constant
;
3185 exp
->X_add_number
= 0;
3186 exp
->X_add_symbol
= (symbolS
*) 0;
3187 exp
->X_op_symbol
= (symbolS
*) 0;
3189 else if (exp
->X_op
== O_constant
)
3191 /* Size it properly later. */
3192 i
.types
[this_operand
] |= Imm64
;
3193 /* If BFD64, sign extend val. */
3194 if (!use_rela_relocations
)
3195 if ((exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
3196 exp
->X_add_number
= (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
3198 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3200 #ifdef BFD_ASSEMBLER
3201 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
3203 && exp_seg
!= text_section
3204 && exp_seg
!= data_section
3205 && exp_seg
!= bss_section
3206 && exp_seg
!= undefined_section
3207 #ifdef BFD_ASSEMBLER
3208 && !bfd_is_com_section (exp_seg
)
3212 #ifdef BFD_ASSEMBLER
3213 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
3215 as_bad (_("unimplemented segment type %d in operand"), exp_seg
);
3222 /* This is an address. The size of the address will be
3223 determined later, depending on destination register,
3224 suffix, or the default for the section. */
3225 i
.types
[this_operand
] |= Imm8
| Imm16
| Imm32
| Imm32S
| Imm64
;
3231 static int i386_scale
PARAMS ((char *));
3237 if (!isdigit (*scale
))
3244 i
.log2_scale_factor
= 0;
3247 i
.log2_scale_factor
= 1;
3250 i
.log2_scale_factor
= 2;
3253 i
.log2_scale_factor
= 3;
3257 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
3261 if (i
.log2_scale_factor
!= 0 && ! i
.index_reg
)
3263 as_warn (_("scale factor of %d without an index register"),
3264 1 << i
.log2_scale_factor
);
3265 #if SCALE1_WHEN_NO_INDEX
3266 i
.log2_scale_factor
= 0;
3272 static int i386_displacement
PARAMS ((char *, char *));
3275 i386_displacement (disp_start
, disp_end
)
3279 register expressionS
*exp
;
3281 char *save_input_line_pointer
;
3282 int bigdisp
= Disp32
;
3284 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[ADDR_PREFIX
] != 0))
3286 if (flag_code
== CODE_64BIT
)
3288 i
.types
[this_operand
] |= bigdisp
;
3290 exp
= &disp_expressions
[i
.disp_operands
];
3291 i
.op
[this_operand
].disps
= exp
;
3293 save_input_line_pointer
= input_line_pointer
;
3294 input_line_pointer
= disp_start
;
3295 END_STRING_AND_SAVE (disp_end
);
3297 #ifndef GCC_ASM_O_HACK
3298 #define GCC_ASM_O_HACK 0
3301 END_STRING_AND_SAVE (disp_end
+ 1);
3302 if ((i
.types
[this_operand
] & BaseIndex
) != 0
3303 && displacement_string_end
[-1] == '+')
3305 /* This hack is to avoid a warning when using the "o"
3306 constraint within gcc asm statements.
3309 #define _set_tssldt_desc(n,addr,limit,type) \
3310 __asm__ __volatile__ ( \
3312 "movw %w1,2+%0\n\t" \
3314 "movb %b1,4+%0\n\t" \
3315 "movb %4,5+%0\n\t" \
3316 "movb $0,6+%0\n\t" \
3317 "movb %h1,7+%0\n\t" \
3319 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
3321 This works great except that the output assembler ends
3322 up looking a bit weird if it turns out that there is
3323 no offset. You end up producing code that looks like:
3336 So here we provide the missing zero. */
3338 *displacement_string_end
= '0';
3343 /* We can have operands of the form
3344 <symbol>@GOTOFF+<nnn>
3345 Take the easy way out here and copy everything
3346 into a temporary buffer... */
3349 cp
= strchr (input_line_pointer
, '@');
3356 /* GOT relocations are not supported in 16 bit mode. */
3357 if (flag_code
== CODE_16BIT
)
3358 as_bad (_("GOT relocations not supported in 16 bit mode"));
3360 if (GOT_symbol
== NULL
)
3361 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
3363 if (strncmp (cp
+ 1, "PLT", 3) == 0)
3365 if (flag_code
== CODE_64BIT
)
3366 i
.disp_reloc
[this_operand
] = BFD_RELOC_X86_64_PLT32
;
3368 i
.disp_reloc
[this_operand
] = BFD_RELOC_386_PLT32
;
3371 else if (strncmp (cp
+ 1, "GOTOFF", 6) == 0)
3373 if (flag_code
== CODE_64BIT
)
3374 as_bad ("GOTOFF relocation is not supported in 64bit mode.");
3375 i
.disp_reloc
[this_operand
] = BFD_RELOC_386_GOTOFF
;
3378 else if (strncmp (cp
+ 1, "GOTPCREL", 8) == 0)
3380 if (flag_code
!= CODE_64BIT
)
3381 as_bad ("GOTPCREL relocation is supported only in 64bit mode.");
3382 i
.disp_reloc
[this_operand
] = BFD_RELOC_X86_64_GOTPCREL
;
3385 else if (strncmp (cp
+ 1, "GOT", 3) == 0)
3387 if (flag_code
== CODE_64BIT
)
3388 i
.disp_reloc
[this_operand
] = BFD_RELOC_X86_64_GOT32
;
3390 i
.disp_reloc
[this_operand
] = BFD_RELOC_386_GOT32
;
3394 as_bad (_("bad reloc specifier in expression"));
3396 /* Replace the relocation token with ' ', so that errors like
3397 foo@GOTOFF1 will be detected. */
3398 first
= cp
- input_line_pointer
;
3399 tmpbuf
= (char *) alloca (strlen (input_line_pointer
));
3400 memcpy (tmpbuf
, input_line_pointer
, first
);
3401 tmpbuf
[first
] = ' ';
3402 strcpy (tmpbuf
+ first
+ 1, cp
+ 1 + len
);
3403 input_line_pointer
= tmpbuf
;
3408 exp_seg
= expression (exp
);
3410 #ifdef BFD_ASSEMBLER
3411 /* We do this to make sure that the section symbol is in
3412 the symbol table. We will ultimately change the relocation
3413 to be relative to the beginning of the section. */
3414 if (i
.disp_reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
3415 || i
.disp_reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
3417 if (S_IS_LOCAL(exp
->X_add_symbol
)
3418 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
)
3419 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
3420 assert (exp
->X_op
== O_symbol
);
3421 exp
->X_op
= O_subtract
;
3422 exp
->X_op_symbol
= GOT_symbol
;
3423 i
.disp_reloc
[this_operand
] = BFD_RELOC_32
;
3428 if (*input_line_pointer
)
3429 as_bad (_("ignoring junk `%s' after expression"),
3430 input_line_pointer
);
3432 RESTORE_END_STRING (disp_end
+ 1);
3434 RESTORE_END_STRING (disp_end
);
3435 input_line_pointer
= save_input_line_pointer
;
3437 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_big
)
3439 /* Missing or bad expr becomes absolute 0. */
3440 as_bad (_("missing or invalid displacement expression `%s' taken as 0"),
3442 exp
->X_op
= O_constant
;
3443 exp
->X_add_number
= 0;
3444 exp
->X_add_symbol
= (symbolS
*) 0;
3445 exp
->X_op_symbol
= (symbolS
*) 0;
3448 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3449 if (exp
->X_op
!= O_constant
3450 #ifdef BFD_ASSEMBLER
3451 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
3453 && exp_seg
!= text_section
3454 && exp_seg
!= data_section
3455 && exp_seg
!= bss_section
3456 && exp_seg
!= undefined_section
)
3458 #ifdef BFD_ASSEMBLER
3459 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
3461 as_bad (_("unimplemented segment type %d in operand"), exp_seg
);
3466 else if (flag_code
== CODE_64BIT
)
3467 i
.types
[this_operand
] |= Disp32S
| Disp32
;
3471 static int i386_index_check
PARAMS((const char *));
3473 /* Make sure the memory operand we've been dealt is valid.
3474 Return 1 on success, 0 on a failure. */
3477 i386_index_check (operand_string
)
3478 const char *operand_string
;
3481 #if INFER_ADDR_PREFIX
3487 if (flag_code
== CODE_64BIT
)
3491 && ((i
.base_reg
->reg_type
& Reg64
) == 0)
3492 && (i
.base_reg
->reg_type
!= BaseIndex
3495 && ((i
.index_reg
->reg_type
& (Reg64
|BaseIndex
))
3496 != (Reg64
|BaseIndex
))))
3501 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[ADDR_PREFIX
] != 0))
3505 && ((i
.base_reg
->reg_type
& (Reg16
|BaseIndex
|RegRex
))
3506 != (Reg16
|BaseIndex
)))
3508 && (((i
.index_reg
->reg_type
& (Reg16
|BaseIndex
))
3509 != (Reg16
|BaseIndex
))
3511 && i
.base_reg
->reg_num
< 6
3512 && i
.index_reg
->reg_num
>= 6
3513 && i
.log2_scale_factor
== 0))))
3520 && (i
.base_reg
->reg_type
& (Reg32
| RegRex
)) != Reg32
)
3522 && ((i
.index_reg
->reg_type
& (Reg32
|BaseIndex
|RegRex
))
3523 != (Reg32
|BaseIndex
))))
3529 #if INFER_ADDR_PREFIX
3530 if (flag_code
!= CODE_64BIT
3531 && i
.prefix
[ADDR_PREFIX
] == 0 && stackop_size
!= '\0')
3533 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
3535 /* Change the size of any displacement too. At most one of
3536 Disp16 or Disp32 is set.
3537 FIXME. There doesn't seem to be any real need for separate
3538 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
3539 Removing them would probably clean up the code quite a lot. */
3540 if (i
.types
[this_operand
] & (Disp16
|Disp32
))
3541 i
.types
[this_operand
] ^= (Disp16
|Disp32
);
3546 as_bad (_("`%s' is not a valid base/index expression"),
3550 as_bad (_("`%s' is not a valid %s bit base/index expression"),
3552 flag_code_names
[flag_code
]);
3558 /* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero
3562 i386_operand (operand_string
)
3563 char *operand_string
;
3567 char *op_string
= operand_string
;
3569 if (is_space_char (*op_string
))
3572 /* We check for an absolute prefix (differentiating,
3573 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
3574 if (*op_string
== ABSOLUTE_PREFIX
)
3577 if (is_space_char (*op_string
))
3579 i
.types
[this_operand
] |= JumpAbsolute
;
3582 /* Check if operand is a register. */
3583 if ((*op_string
== REGISTER_PREFIX
|| allow_naked_reg
)
3584 && (r
= parse_register (op_string
, &end_op
)) != NULL
)
3586 /* Check for a segment override by searching for ':' after a
3587 segment register. */
3589 if (is_space_char (*op_string
))
3591 if (*op_string
== ':' && (r
->reg_type
& (SReg2
| SReg3
)))
3596 i
.seg
[i
.mem_operands
] = &es
;
3599 i
.seg
[i
.mem_operands
] = &cs
;
3602 i
.seg
[i
.mem_operands
] = &ss
;
3605 i
.seg
[i
.mem_operands
] = &ds
;
3608 i
.seg
[i
.mem_operands
] = &fs
;
3611 i
.seg
[i
.mem_operands
] = &gs
;
3615 /* Skip the ':' and whitespace. */
3617 if (is_space_char (*op_string
))
3620 if (!is_digit_char (*op_string
)
3621 && !is_identifier_char (*op_string
)
3622 && *op_string
!= '('
3623 && *op_string
!= ABSOLUTE_PREFIX
)
3625 as_bad (_("bad memory operand `%s'"), op_string
);
3628 /* Handle case of %es:*foo. */
3629 if (*op_string
== ABSOLUTE_PREFIX
)
3632 if (is_space_char (*op_string
))
3634 i
.types
[this_operand
] |= JumpAbsolute
;
3636 goto do_memory_reference
;
3640 as_bad (_("junk `%s' after register"), op_string
);
3643 i
.types
[this_operand
] |= r
->reg_type
& ~BaseIndex
;
3644 i
.op
[this_operand
].regs
= r
;
3647 else if (*op_string
== REGISTER_PREFIX
)
3649 as_bad (_("bad register name `%s'"), op_string
);
3652 else if (*op_string
== IMMEDIATE_PREFIX
)
3655 if (i
.types
[this_operand
] & JumpAbsolute
)
3657 as_bad (_("immediate operand illegal with absolute jump"));
3660 if (!i386_immediate (op_string
))
3663 else if (is_digit_char (*op_string
)
3664 || is_identifier_char (*op_string
)
3665 || *op_string
== '(' )
3667 /* This is a memory reference of some sort. */
3670 /* Start and end of displacement string expression (if found). */
3671 char *displacement_string_start
;
3672 char *displacement_string_end
;
3674 do_memory_reference
:
3675 if ((i
.mem_operands
== 1
3676 && (current_templates
->start
->opcode_modifier
& IsString
) == 0)
3677 || i
.mem_operands
== 2)
3679 as_bad (_("too many memory references for `%s'"),
3680 current_templates
->start
->name
);
3684 /* Check for base index form. We detect the base index form by
3685 looking for an ')' at the end of the operand, searching
3686 for the '(' matching it, and finding a REGISTER_PREFIX or ','
3688 base_string
= op_string
+ strlen (op_string
);
3691 if (is_space_char (*base_string
))
3694 /* If we only have a displacement, set-up for it to be parsed later. */
3695 displacement_string_start
= op_string
;
3696 displacement_string_end
= base_string
+ 1;
3698 if (*base_string
== ')')
3701 unsigned int parens_balanced
= 1;
3702 /* We've already checked that the number of left & right ()'s are
3703 equal, so this loop will not be infinite. */
3707 if (*base_string
== ')')
3709 if (*base_string
== '(')
3712 while (parens_balanced
);
3714 temp_string
= base_string
;
3716 /* Skip past '(' and whitespace. */
3718 if (is_space_char (*base_string
))
3721 if (*base_string
== ','
3722 || ((*base_string
== REGISTER_PREFIX
|| allow_naked_reg
)
3723 && (i
.base_reg
= parse_register (base_string
, &end_op
)) != NULL
))
3725 displacement_string_end
= temp_string
;
3727 i
.types
[this_operand
] |= BaseIndex
;
3731 base_string
= end_op
;
3732 if (is_space_char (*base_string
))
3736 /* There may be an index reg or scale factor here. */
3737 if (*base_string
== ',')
3740 if (is_space_char (*base_string
))
3743 if ((*base_string
== REGISTER_PREFIX
|| allow_naked_reg
)
3744 && (i
.index_reg
= parse_register (base_string
, &end_op
)) != NULL
)
3746 base_string
= end_op
;
3747 if (is_space_char (*base_string
))
3749 if (*base_string
== ',')
3752 if (is_space_char (*base_string
))
3755 else if (*base_string
!= ')' )
3757 as_bad (_("expecting `,' or `)' after index register in `%s'"),
3762 else if (*base_string
== REGISTER_PREFIX
)
3764 as_bad (_("bad register name `%s'"), base_string
);
3768 /* Check for scale factor. */
3769 if (isdigit ((unsigned char) *base_string
))
3771 if (!i386_scale (base_string
))
3775 if (is_space_char (*base_string
))
3777 if (*base_string
!= ')')
3779 as_bad (_("expecting `)' after scale factor in `%s'"),
3784 else if (!i
.index_reg
)
3786 as_bad (_("expecting index register or scale factor after `,'; got '%c'"),
3791 else if (*base_string
!= ')')
3793 as_bad (_("expecting `,' or `)' after base register in `%s'"),
3798 else if (*base_string
== REGISTER_PREFIX
)
3800 as_bad (_("bad register name `%s'"), base_string
);
3805 /* If there's an expression beginning the operand, parse it,
3806 assuming displacement_string_start and
3807 displacement_string_end are meaningful. */
3808 if (displacement_string_start
!= displacement_string_end
)
3810 if (!i386_displacement (displacement_string_start
,
3811 displacement_string_end
))
3815 /* Special case for (%dx) while doing input/output op. */
3817 && i
.base_reg
->reg_type
== (Reg16
| InOutPortReg
)
3819 && i
.log2_scale_factor
== 0
3820 && i
.seg
[i
.mem_operands
] == 0
3821 && (i
.types
[this_operand
] & Disp
) == 0)
3823 i
.types
[this_operand
] = InOutPortReg
;
3827 if (i386_index_check (operand_string
) == 0)
3833 /* It's not a memory operand; argh! */
3834 as_bad (_("invalid char %s beginning operand %d `%s'"),
3835 output_invalid (*op_string
),
3840 return 1; /* Normal return. */
3843 /* md_estimate_size_before_relax()
3845 Called just before relax() for rs_machine_dependent frags. The x86
3846 assembler uses these frags to handle variable size jump
3849 Any symbol that is now undefined will not become defined.
3850 Return the correct fr_subtype in the frag.
3851 Return the initial "guess for variable size of frag" to caller.
3852 The guess is actually the growth beyond the fixed part. Whatever
3853 we do to grow the fixed or variable part contributes to our
3857 md_estimate_size_before_relax (fragP
, segment
)
3858 register fragS
*fragP
;
3859 register segT segment
;
3861 /* We've already got fragP->fr_subtype right; all we have to do is
3862 check for un-relaxable symbols. On an ELF system, we can't relax
3863 an externally visible symbol, because it may be overridden by a
3865 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
3866 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3867 || S_IS_EXTERNAL (fragP
->fr_symbol
)
3868 || S_IS_WEAK (fragP
->fr_symbol
)
3872 /* Symbol is undefined in this segment, or we need to keep a
3873 reloc so that weak symbols can be overridden. */
3874 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
3875 #ifdef BFD_ASSEMBLER
3876 enum bfd_reloc_code_real reloc_type
;
3880 unsigned char *opcode
;
3883 if (fragP
->fr_var
!= NO_RELOC
)
3884 reloc_type
= fragP
->fr_var
;
3886 reloc_type
= BFD_RELOC_16_PCREL
;
3888 reloc_type
= BFD_RELOC_32_PCREL
;
3890 old_fr_fix
= fragP
->fr_fix
;
3891 opcode
= (unsigned char *) fragP
->fr_opcode
;
3895 case JUMP_PC_RELATIVE
:
3896 /* Make jmp (0xeb) a dword displacement jump. */
3898 fragP
->fr_fix
+= size
;
3899 fix_new (fragP
, old_fr_fix
, size
,
3901 fragP
->fr_offset
, 1,
3906 /* This changes the byte-displacement jump 0x7N
3907 to the dword-displacement jump 0x0f,0x8N. */
3908 opcode
[1] = opcode
[0] + 0x10;
3909 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
3910 /* We've added an opcode byte. */
3911 fragP
->fr_fix
+= 1 + size
;
3912 fix_new (fragP
, old_fr_fix
+ 1, size
,
3914 fragP
->fr_offset
, 1,
3919 return fragP
->fr_fix
- old_fr_fix
;
3921 /* Guess a short jump. */
3925 /* Called after relax() is finished.
3927 In: Address of frag.
3928 fr_type == rs_machine_dependent.
3929 fr_subtype is what the address relaxed to.
3931 Out: Any fixSs and constants are set up.
3932 Caller will turn frag into a ".space 0". */
3934 #ifndef BFD_ASSEMBLER
3936 md_convert_frag (headers
, sec
, fragP
)
3937 object_headers
*headers ATTRIBUTE_UNUSED
;
3938 segT sec ATTRIBUTE_UNUSED
;
3939 register fragS
*fragP
;
3942 md_convert_frag (abfd
, sec
, fragP
)
3943 bfd
*abfd ATTRIBUTE_UNUSED
;
3944 segT sec ATTRIBUTE_UNUSED
;
3945 register fragS
*fragP
;
3948 register unsigned char *opcode
;
3949 unsigned char *where_to_put_displacement
= NULL
;
3950 offsetT target_address
;
3951 offsetT opcode_address
;
3952 unsigned int extension
= 0;
3953 offsetT displacement_from_opcode_start
;
3955 opcode
= (unsigned char *) fragP
->fr_opcode
;
3957 /* Address we want to reach in file space. */
3958 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
3959 #ifdef BFD_ASSEMBLER
3960 /* Not needed otherwise? */
3961 target_address
+= symbol_get_frag (fragP
->fr_symbol
)->fr_address
;
3964 /* Address opcode resides at in file space. */
3965 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
3967 /* Displacement from opcode start to fill into instruction. */
3968 displacement_from_opcode_start
= target_address
- opcode_address
;
3970 switch (fragP
->fr_subtype
)
3972 case ENCODE_RELAX_STATE (COND_JUMP
, SMALL
):
3973 case ENCODE_RELAX_STATE (COND_JUMP
, SMALL16
):
3974 case ENCODE_RELAX_STATE (UNCOND_JUMP
, SMALL
):
3975 case ENCODE_RELAX_STATE (UNCOND_JUMP
, SMALL16
):
3976 /* Don't have to change opcode. */
3977 extension
= 1; /* 1 opcode + 1 displacement */
3978 where_to_put_displacement
= &opcode
[1];
3981 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
3982 extension
= 5; /* 2 opcode + 4 displacement */
3983 opcode
[1] = opcode
[0] + 0x10;
3984 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
3985 where_to_put_displacement
= &opcode
[2];
3988 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
3989 extension
= 4; /* 1 opcode + 4 displacement */
3991 where_to_put_displacement
= &opcode
[1];
3994 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
3995 extension
= 3; /* 2 opcode + 2 displacement */
3996 opcode
[1] = opcode
[0] + 0x10;
3997 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
3998 where_to_put_displacement
= &opcode
[2];
4001 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
4002 extension
= 2; /* 1 opcode + 2 displacement */
4004 where_to_put_displacement
= &opcode
[1];
4008 BAD_CASE (fragP
->fr_subtype
);
4011 /* Now put displacement after opcode. */
4012 md_number_to_chars ((char *) where_to_put_displacement
,
4013 (valueT
) (displacement_from_opcode_start
- extension
),
4014 SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
4015 fragP
->fr_fix
+= extension
;
4018 /* Size of byte displacement jmp. */
4019 int md_short_jump_size
= 2;
4021 /* Size of dword displacement jmp. */
4022 int md_long_jump_size
= 5;
4024 /* Size of relocation record. */
4025 const int md_reloc_size
= 8;
4028 md_create_short_jump (ptr
, from_addr
, to_addr
, frag
, to_symbol
)
4030 addressT from_addr
, to_addr
;
4031 fragS
*frag ATTRIBUTE_UNUSED
;
4032 symbolS
*to_symbol ATTRIBUTE_UNUSED
;
4036 offset
= to_addr
- (from_addr
+ 2);
4037 /* Opcode for byte-disp jump. */
4038 md_number_to_chars (ptr
, (valueT
) 0xeb, 1);
4039 md_number_to_chars (ptr
+ 1, (valueT
) offset
, 1);
4043 md_create_long_jump (ptr
, from_addr
, to_addr
, frag
, to_symbol
)
4045 addressT from_addr
, to_addr
;
4046 fragS
*frag ATTRIBUTE_UNUSED
;
4047 symbolS
*to_symbol ATTRIBUTE_UNUSED
;
4051 offset
= to_addr
- (from_addr
+ 5);
4052 md_number_to_chars (ptr
, (valueT
) 0xe9, 1);
4053 md_number_to_chars (ptr
+ 1, (valueT
) offset
, 4);
4056 /* Apply a fixup (fixS) to segment data, once it has been determined
4057 by our caller that we have all the info we need to fix it up.
4059 On the 386, immediates, displacements, and data pointers are all in
4060 the same (little-endian) format, so we don't need to care about which
4064 md_apply_fix3 (fixP
, valp
, seg
)
4065 /* The fix we're to put in. */
4068 /* Pointer to the value of the bits. */
4071 /* Segment fix is from. */
4072 segT seg ATTRIBUTE_UNUSED
;
4074 register char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
4075 valueT value
= *valp
;
4077 #if defined (BFD_ASSEMBLER) && !defined (TE_Mach)
4080 switch (fixP
->fx_r_type
)
4086 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
4089 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
4092 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
4097 /* This is a hack. There should be a better way to handle this.
4098 This covers for the fact that bfd_install_relocation will
4099 subtract the current location (for partial_inplace, PC relative
4100 relocations); see more below. */
4101 if ((fixP
->fx_r_type
== BFD_RELOC_32_PCREL
4102 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
4103 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
4107 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
4109 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
4112 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
4114 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4115 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
4117 segT fseg
= S_GET_SEGMENT (fixP
->fx_addsy
);
4120 || (symbol_section_p (fixP
->fx_addsy
)
4121 && fseg
!= absolute_section
))
4122 && ! S_IS_EXTERNAL (fixP
->fx_addsy
)
4123 && ! S_IS_WEAK (fixP
->fx_addsy
)
4124 && S_IS_DEFINED (fixP
->fx_addsy
)
4125 && ! S_IS_COMMON (fixP
->fx_addsy
))
4127 /* Yes, we add the values in twice. This is because
4128 bfd_perform_relocation subtracts them out again. I think
4129 bfd_perform_relocation is broken, but I don't dare change
4131 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
4135 #if defined (OBJ_COFF) && defined (TE_PE)
4136 /* For some reason, the PE format does not store a section
4137 address offset for a PC relative symbol. */
4138 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
4139 value
+= md_pcrel_from (fixP
);
4143 /* Fix a few things - the dynamic linker expects certain values here,
4144 and we must not dissappoint it. */
4145 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4146 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
4148 switch (fixP
->fx_r_type
)
4150 case BFD_RELOC_386_PLT32
:
4151 case BFD_RELOC_X86_64_PLT32
:
4152 /* Make the jump instruction point to the address of the operand. At
4153 runtime we merely add the offset to the actual PLT entry. */
4156 case BFD_RELOC_386_GOTPC
:
4158 /* This is tough to explain. We end up with this one if we have
4159 * operands that look like "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal
4160 * here is to obtain the absolute address of the GOT, and it is strongly
4161 * preferable from a performance point of view to avoid using a runtime
4162 * relocation for this. The actual sequence of instructions often look
4168 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
4170 * The call and pop essentially return the absolute address of
4171 * the label .L66 and store it in %ebx. The linker itself will
4172 * ultimately change the first operand of the addl so that %ebx points to
4173 * the GOT, but to keep things simple, the .o file must have this operand
4174 * set so that it generates not the absolute address of .L66, but the
4175 * absolute address of itself. This allows the linker itself simply
4176 * treat a GOTPC relocation as asking for a pcrel offset to the GOT to be
4177 * added in, and the addend of the relocation is stored in the operand
4178 * field for the instruction itself.
4180 * Our job here is to fix the operand so that it would add the correct
4181 * offset so that %ebx would point to itself. The thing that is tricky is
4182 * that .-.L66 will point to the beginning of the instruction, so we need
4183 * to further modify the operand so that it will point to itself.
4184 * There are other cases where you have something like:
4186 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
4188 * and here no correction would be required. Internally in the assembler
4189 * we treat operands of this form as not being pcrel since the '.' is
4190 * explicitly mentioned, and I wonder whether it would simplify matters
4191 * to do it this way. Who knows. In earlier versions of the PIC patches,
4192 * the pcrel_adjust field was used to store the correction, but since the
4193 * expression is not pcrel, I felt it would be confusing to do it this
4198 case BFD_RELOC_386_GOT32
:
4199 case BFD_RELOC_X86_64_GOT32
:
4200 value
= 0; /* Fully resolved at runtime. No addend. */
4202 case BFD_RELOC_386_GOTOFF
:
4203 case BFD_RELOC_X86_64_GOTPCREL
:
4206 case BFD_RELOC_VTABLE_INHERIT
:
4207 case BFD_RELOC_VTABLE_ENTRY
:
4214 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
4216 #endif /* defined (BFD_ASSEMBLER) && !defined (TE_Mach) */
4218 #ifndef BFD_ASSEMBLER
4219 md_number_to_chars (p
, value
, fixP
->fx_size
);
4221 /* Are we finished with this relocation now? */
4222 if (fixP
->fx_addsy
== 0 && fixP
->fx_pcrel
== 0)
4224 else if (use_rela_relocations
)
4226 fixP
->fx_no_overflow
= 1;
4229 md_number_to_chars (p
, value
, fixP
->fx_size
);
4235 #define MAX_LITTLENUMS 6
4237 /* Turn the string pointed to by litP into a floating point constant
4238 of type TYPE, and emit the appropriate bytes. The number of
4239 LITTLENUMS emitted is stored in *SIZEP. An error message is
4240 returned, or NULL on OK. */
4243 md_atof (type
, litP
, sizeP
)
4249 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4250 LITTLENUM_TYPE
*wordP
;
4272 return _("Bad call to md_atof ()");
4274 t
= atof_ieee (input_line_pointer
, type
, words
);
4276 input_line_pointer
= t
;
4278 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
4279 /* This loops outputs the LITTLENUMs in REVERSE order; in accord with
4280 the bigendian 386. */
4281 for (wordP
= words
+ prec
- 1; prec
--;)
4283 md_number_to_chars (litP
, (valueT
) (*wordP
--), sizeof (LITTLENUM_TYPE
));
4284 litP
+= sizeof (LITTLENUM_TYPE
);
4289 char output_invalid_buf
[8];
4296 sprintf (output_invalid_buf
, "'%c'", c
);
4298 sprintf (output_invalid_buf
, "(0x%x)", (unsigned) c
);
4299 return output_invalid_buf
;
4302 /* REG_STRING starts *before* REGISTER_PREFIX. */
4304 static const reg_entry
*
4305 parse_register (reg_string
, end_op
)
4309 char *s
= reg_string
;
4311 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
4314 /* Skip possible REGISTER_PREFIX and possible whitespace. */
4315 if (*s
== REGISTER_PREFIX
)
4318 if (is_space_char (*s
))
4322 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
4324 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
4325 return (const reg_entry
*) NULL
;
4329 /* For naked regs, make sure that we are not dealing with an identifier.
4330 This prevents confusing an identifier like `eax_var' with register
4332 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
4333 return (const reg_entry
*) NULL
;
4337 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
4339 /* Handle floating point regs, allowing spaces in the (i) part. */
4340 if (r
== i386_regtab
/* %st is first entry of table */)
4342 if (is_space_char (*s
))
4347 if (is_space_char (*s
))
4349 if (*s
>= '0' && *s
<= '7')
4351 r
= &i386_float_regtab
[*s
- '0'];
4353 if (is_space_char (*s
))
4361 /* We have "%st(" then garbage. */
4362 return (const reg_entry
*) NULL
;
4369 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4370 const char *md_shortopts
= "kVQ:sq";
4372 const char *md_shortopts
= "q";
4375 struct option md_longopts
[] = {
4376 #define OPTION_32 (OPTION_MD_BASE + 0)
4377 {"32", no_argument
, NULL
, OPTION_32
},
4378 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4379 #define OPTION_64 (OPTION_MD_BASE + 1)
4380 {"64", no_argument
, NULL
, OPTION_64
},
4382 {NULL
, no_argument
, NULL
, 0}
4384 size_t md_longopts_size
= sizeof (md_longopts
);
4387 md_parse_option (c
, arg
)
4389 char *arg ATTRIBUTE_UNUSED
;
4397 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4398 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
4399 should be emitted or not. FIXME: Not implemented. */
4403 /* -V: SVR4 argument to print version ID. */
4405 print_version_id ();
4408 /* -k: Ignore for FreeBSD compatibility. */
4413 /* -s: On i386 Solaris, this tells the native assembler to use
4414 .stab instead of .stab.excl. We always use .stab anyhow. */
4419 const char **list
, **l
;
4421 list
= bfd_target_list ();
4422 for (l
= list
; *l
!= NULL
; l
++)
4423 if (strcmp (*l
, "elf64-x86-64") == 0)
4425 default_arch
= "x86_64";
4429 as_fatal (_("No compiled in support for x86_64"));
4436 default_arch
= "i386";
4446 md_show_usage (stream
)
4449 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4450 fprintf (stream
, _("\
4452 -V print assembler version number\n\
4454 -q quieten some warnings\n\
4457 fprintf (stream
, _("\
4458 -q quieten some warnings\n"));
4462 #ifdef BFD_ASSEMBLER
4463 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
4464 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
4466 /* Pick the target format to use. */
4469 i386_target_format ()
4471 if (!strcmp (default_arch
, "x86_64"))
4472 set_code_flag (CODE_64BIT
);
4473 else if (!strcmp (default_arch
, "i386"))
4474 set_code_flag (CODE_32BIT
);
4476 as_fatal (_("Unknown architecture"));
4477 switch (OUTPUT_FLAVOR
)
4479 #ifdef OBJ_MAYBE_AOUT
4480 case bfd_target_aout_flavour
:
4481 return AOUT_TARGET_FORMAT
;
4483 #ifdef OBJ_MAYBE_COFF
4484 case bfd_target_coff_flavour
:
4487 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
4488 case bfd_target_elf_flavour
:
4490 if (flag_code
== CODE_64BIT
)
4491 use_rela_relocations
= 1;
4492 return flag_code
== CODE_64BIT
? "elf64-x86-64" : "elf32-i386";
4501 #endif /* OBJ_MAYBE_ more than one */
4502 #endif /* BFD_ASSEMBLER */
4505 md_undefined_symbol (name
)
4508 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
4509 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
4510 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
4511 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
4515 if (symbol_find (name
))
4516 as_bad (_("GOT already in symbol table"));
4517 GOT_symbol
= symbol_new (name
, undefined_section
,
4518 (valueT
) 0, &zero_address_frag
);
4525 /* Round up a section size to the appropriate boundary. */
4528 md_section_align (segment
, size
)
4529 segT segment ATTRIBUTE_UNUSED
;
4532 #ifdef BFD_ASSEMBLER
4533 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
4534 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
4536 /* For a.out, force the section size to be aligned. If we don't do
4537 this, BFD will align it for us, but it will not write out the
4538 final bytes of the section. This may be a bug in BFD, but it is
4539 easier to fix it here since that is how the other a.out targets
4543 align
= bfd_get_section_alignment (stdoutput
, segment
);
4544 size
= ((size
+ (1 << align
) - 1) & ((valueT
) -1 << align
));
4552 /* On the i386, PC-relative offsets are relative to the start of the
4553 next instruction. That is, the address of the offset, plus its
4554 size, since the offset is always the last part of the insn. */
4557 md_pcrel_from (fixP
)
4560 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
4567 int ignore ATTRIBUTE_UNUSED
;
4571 temp
= get_absolute_expression ();
4572 subseg_set (bss_section
, (subsegT
) temp
);
4573 demand_empty_rest_of_line ();
4578 #ifdef BFD_ASSEMBLER
4581 i386_validate_fix (fixp
)
4584 if (fixp
->fx_subsy
&& fixp
->fx_subsy
== GOT_symbol
)
4586 /* GOTOFF relocation are nonsense in 64bit mode. */
4587 if (flag_code
== CODE_64BIT
)
4589 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
4595 tc_gen_reloc (section
, fixp
)
4596 asection
*section ATTRIBUTE_UNUSED
;
4600 bfd_reloc_code_real_type code
;
4602 switch (fixp
->fx_r_type
)
4604 case BFD_RELOC_X86_64_PLT32
:
4605 case BFD_RELOC_X86_64_GOT32
:
4606 case BFD_RELOC_X86_64_GOTPCREL
:
4607 case BFD_RELOC_386_PLT32
:
4608 case BFD_RELOC_386_GOT32
:
4609 case BFD_RELOC_386_GOTOFF
:
4610 case BFD_RELOC_386_GOTPC
:
4611 case BFD_RELOC_X86_64_32S
:
4613 case BFD_RELOC_VTABLE_ENTRY
:
4614 case BFD_RELOC_VTABLE_INHERIT
:
4615 code
= fixp
->fx_r_type
;
4620 switch (fixp
->fx_size
)
4623 as_bad (_("can not do %d byte pc-relative relocation"),
4625 code
= BFD_RELOC_32_PCREL
;
4627 case 1: code
= BFD_RELOC_8_PCREL
; break;
4628 case 2: code
= BFD_RELOC_16_PCREL
; break;
4629 case 4: code
= BFD_RELOC_32_PCREL
; break;
4634 switch (fixp
->fx_size
)
4637 as_bad (_("can not do %d byte relocation"), fixp
->fx_size
);
4638 code
= BFD_RELOC_32
;
4640 case 1: code
= BFD_RELOC_8
; break;
4641 case 2: code
= BFD_RELOC_16
; break;
4642 case 4: code
= BFD_RELOC_32
; break;
4643 case 8: code
= BFD_RELOC_64
; break;
4649 if (code
== BFD_RELOC_32
4651 && fixp
->fx_addsy
== GOT_symbol
)
4653 /* We don't support GOTPC on 64bit targets. */
4654 if (flag_code
== CODE_64BIT
)
4656 code
= BFD_RELOC_386_GOTPC
;
4659 rel
= (arelent
*) xmalloc (sizeof (arelent
));
4660 rel
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
4661 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
4663 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
4664 if (!use_rela_relocations
)
4666 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
4667 vtable entry to be used in the relocation's section offset. */
4668 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
4669 rel
->address
= fixp
->fx_offset
;
4672 rel
->addend
= fixp
->fx_addnumber
;
4676 /* Use the rela in 64bit mode. */
4679 rel
->addend
= fixp
->fx_offset
;
4681 /* Ohhh, this is ugly. The problem is that if this is a local global
4682 symbol, the relocation will entirely be performed at link time, not
4683 at assembly time. bfd_perform_reloc doesn't know about this sort
4684 of thing, and as a result we need to fake it out here. */
4685 if ((S_IS_EXTERN (fixp
->fx_addsy
) || S_IS_WEAK (fixp
->fx_addsy
))
4686 && !S_IS_COMMON(fixp
->fx_addsy
))
4687 rel
->addend
-= symbol_get_bfdsym (fixp
->fx_addsy
)->value
;
4690 rel
->addend
-= fixp
->fx_size
;
4694 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
4695 if (rel
->howto
== NULL
)
4697 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
4698 _("cannot represent relocation type %s"),
4699 bfd_get_reloc_code_name (code
));
4700 /* Set howto to a garbage value so that we can keep going. */
4701 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
4702 assert (rel
->howto
!= NULL
);
4708 #else /* ! BFD_ASSEMBLER */
4710 #if (defined(OBJ_AOUT) | defined(OBJ_BOUT))
4712 tc_aout_fix_to_chars (where
, fixP
, segment_address_in_file
)
4715 relax_addressT segment_address_in_file
;
4717 /* In: length of relocation (or of address) in chars: 1, 2 or 4.
4718 Out: GNU LD relocation length code: 0, 1, or 2. */
4720 static const unsigned char nbytes_r_length
[] = { 42, 0, 1, 42, 2 };
4723 know (fixP
->fx_addsy
!= NULL
);
4725 md_number_to_chars (where
,
4726 (valueT
) (fixP
->fx_frag
->fr_address
4727 + fixP
->fx_where
- segment_address_in_file
),
4730 r_symbolnum
= (S_IS_DEFINED (fixP
->fx_addsy
)
4731 ? S_GET_TYPE (fixP
->fx_addsy
)
4732 : fixP
->fx_addsy
->sy_number
);
4734 where
[6] = (r_symbolnum
>> 16) & 0x0ff;
4735 where
[5] = (r_symbolnum
>> 8) & 0x0ff;
4736 where
[4] = r_symbolnum
& 0x0ff;
4737 where
[7] = ((((!S_IS_DEFINED (fixP
->fx_addsy
)) << 3) & 0x08)
4738 | ((nbytes_r_length
[fixP
->fx_size
] << 1) & 0x06)
4739 | (((fixP
->fx_pcrel
<< 0) & 0x01) & 0x0f));
4742 #endif /* OBJ_AOUT or OBJ_BOUT. */
4744 #if defined (I386COFF)
4747 tc_coff_fix2rtype (fixP
)
4750 if (fixP
->fx_r_type
== R_IMAGEBASE
)
4753 return (fixP
->fx_pcrel
?
4754 (fixP
->fx_size
== 1 ? R_PCRBYTE
:
4755 fixP
->fx_size
== 2 ? R_PCRWORD
:
4757 (fixP
->fx_size
== 1 ? R_RELBYTE
:
4758 fixP
->fx_size
== 2 ? R_RELWORD
:
4763 tc_coff_sizemachdep (frag
)
4767 return (frag
->fr_next
->fr_address
- frag
->fr_address
);
4772 #endif /* I386COFF */
4774 #endif /* ! BFD_ASSEMBLER */
4776 /* Parse operands using Intel syntax. This implements a recursive descent
4777 parser based on the BNF grammar published in Appendix B of the MASM 6.1
4780 FIXME: We do not recognize the full operand grammar defined in the MASM
4781 documentation. In particular, all the structure/union and
4782 high-level macro operands are missing.
4784 Uppercase words are terminals, lower case words are non-terminals.
4785 Objects surrounded by double brackets '[[' ']]' are optional. Vertical
4786 bars '|' denote choices. Most grammar productions are implemented in
4787 functions called 'intel_<production>'.
4789 Initial production is 'expr'.
4795 byteRegister AL | AH | BL | BH | CL | CH | DL | DH
4797 constant digits [[ radixOverride ]]
4799 dataType BYTE | WORD | DWORD | QWORD | XWORD
4832 gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX
4833 | BP | EBP | SP | ESP | DI | EDI | SI | ESI
4835 hexdigit a | b | c | d | e | f
4836 | A | B | C | D | E | F
4846 register specialRegister
4850 segmentRegister CS | DS | ES | FS | GS | SS
4852 specialRegister CR0 | CR2 | CR3
4853 | DR0 | DR1 | DR2 | DR3 | DR6 | DR7
4854 | TR3 | TR4 | TR5 | TR6 | TR7
4856 We simplify the grammar in obvious places (e.g., register parsing is
4857 done by calling parse_register) and eliminate immediate left recursion
4858 to implement a recursive-descent parser.
4898 /* Parsing structure for the intel syntax parser. Used to implement the
4899 semantic actions for the operand grammar. */
4900 struct intel_parser_s
4902 char *op_string
; /* The string being parsed. */
4903 int got_a_float
; /* Whether the operand is a float. */
4904 int op_modifier
; /* Operand modifier. */
4905 int is_mem
; /* 1 if operand is memory reference. */
4906 const reg_entry
*reg
; /* Last register reference found. */
4907 char *disp
; /* Displacement string being built. */
4910 static struct intel_parser_s intel_parser
;
4912 /* Token structure for parsing intel syntax. */
4915 int code
; /* Token code. */
4916 const reg_entry
*reg
; /* Register entry for register tokens. */
4917 char *str
; /* String representation. */
4920 static struct intel_token cur_token
, prev_token
;
4923 /* Token codes for the intel parser. Since T_SHORT is already used
4924 by COFF, undefine it first to prevent a warning. */
4939 /* Prototypes for intel parser functions. */
4940 static int intel_match_token
PARAMS ((int code
));
4941 static void intel_get_token
PARAMS ((void));
4942 static void intel_putback_token
PARAMS ((void));
4943 static int intel_expr
PARAMS ((void));
4944 static int intel_e05
PARAMS ((void));
4945 static int intel_e05_1
PARAMS ((void));
4946 static int intel_e06
PARAMS ((void));
4947 static int intel_e06_1
PARAMS ((void));
4948 static int intel_e09
PARAMS ((void));
4949 static int intel_e09_1
PARAMS ((void));
4950 static int intel_e10
PARAMS ((void));
4951 static int intel_e10_1
PARAMS ((void));
4952 static int intel_e11
PARAMS ((void));
4955 i386_intel_operand (operand_string
, got_a_float
)
4956 char *operand_string
;
4962 /* Initialize token holders. */
4963 cur_token
.code
= prev_token
.code
= T_NIL
;
4964 cur_token
.reg
= prev_token
.reg
= NULL
;
4965 cur_token
.str
= prev_token
.str
= NULL
;
4967 /* Initialize parser structure. */
4968 p
= intel_parser
.op_string
= (char *)malloc (strlen (operand_string
) + 1);
4971 strcpy (intel_parser
.op_string
, operand_string
);
4972 intel_parser
.got_a_float
= got_a_float
;
4973 intel_parser
.op_modifier
= -1;
4974 intel_parser
.is_mem
= 0;
4975 intel_parser
.reg
= NULL
;
4976 intel_parser
.disp
= (char *)malloc (strlen (operand_string
) + 1);
4977 if (intel_parser
.disp
== NULL
)
4979 intel_parser
.disp
[0] = '\0';
4981 /* Read the first token and start the parser. */
4983 ret
= intel_expr ();
4987 /* If we found a memory reference, hand it over to i386_displacement
4988 to fill in the rest of the operand fields. */
4989 if (intel_parser
.is_mem
)
4991 if ((i
.mem_operands
== 1
4992 && (current_templates
->start
->opcode_modifier
& IsString
) == 0)
4993 || i
.mem_operands
== 2)
4995 as_bad (_("too many memory references for '%s'"),
4996 current_templates
->start
->name
);
5001 char *s
= intel_parser
.disp
;
5004 /* Add the displacement expression. */
5006 ret
= i386_displacement (s
, s
+ strlen (s
))
5007 && i386_index_check (s
);
5011 /* Constant and OFFSET expressions are handled by i386_immediate. */
5012 else if (intel_parser
.op_modifier
== OFFSET_FLAT
5013 || intel_parser
.reg
== NULL
)
5014 ret
= i386_immediate (intel_parser
.disp
);
5018 free (intel_parser
.disp
);
5028 /* expr SHORT e05 */
5029 if (cur_token
.code
== T_SHORT
)
5031 intel_parser
.op_modifier
= SHORT
;
5032 intel_match_token (T_SHORT
);
5034 return (intel_e05 ());
5039 return intel_e05 ();
5049 return (intel_e06 () && intel_e05_1 ());
5055 /* e05' addOp e06 e05' */
5056 if (cur_token
.code
== '+' || cur_token
.code
== '-')
5058 strcat (intel_parser
.disp
, cur_token
.str
);
5059 intel_match_token (cur_token
.code
);
5061 return (intel_e06 () && intel_e05_1 ());
5076 return (intel_e09 () && intel_e06_1 ());
5082 /* e06' mulOp e09 e06' */
5083 if (cur_token
.code
== '*' || cur_token
.code
== '/')
5085 strcat (intel_parser
.disp
, cur_token
.str
);
5086 intel_match_token (cur_token
.code
);
5088 return (intel_e09 () && intel_e06_1 ());
5096 /* e09 OFFSET e10 e09'
5105 /* e09 OFFSET e10 e09' */
5106 if (cur_token
.code
== T_OFFSET
)
5108 intel_parser
.is_mem
= 0;
5109 intel_parser
.op_modifier
= OFFSET_FLAT
;
5110 intel_match_token (T_OFFSET
);
5112 return (intel_e10 () && intel_e09_1 ());
5117 return (intel_e10 () && intel_e09_1 ());
5123 /* e09' PTR e10 e09' */
5124 if (cur_token
.code
== T_PTR
)
5126 if (prev_token
.code
== T_BYTE
)
5127 i
.suffix
= BYTE_MNEM_SUFFIX
;
5129 else if (prev_token
.code
== T_WORD
)
5131 if (intel_parser
.got_a_float
== 2) /* "fi..." */
5132 i
.suffix
= SHORT_MNEM_SUFFIX
;
5134 i
.suffix
= WORD_MNEM_SUFFIX
;
5137 else if (prev_token
.code
== T_DWORD
)
5139 if (intel_parser
.got_a_float
== 1) /* "f..." */
5140 i
.suffix
= SHORT_MNEM_SUFFIX
;
5142 i
.suffix
= LONG_MNEM_SUFFIX
;
5145 else if (prev_token
.code
== T_QWORD
)
5147 if (intel_parser
.got_a_float
== 1) /* "f..." */
5148 i
.suffix
= LONG_MNEM_SUFFIX
;
5150 i
.suffix
= QWORD_MNEM_SUFFIX
;
5153 else if (prev_token
.code
== T_XWORD
)
5154 i
.suffix
= LONG_DOUBLE_MNEM_SUFFIX
;
5158 as_bad (_("Unknown operand modifier `%s'\n"), prev_token
.str
);
5162 intel_match_token (T_PTR
);
5164 return (intel_e10 () && intel_e09_1 ());
5167 /* e09 : e10 e09' */
5168 else if (cur_token
.code
== ':')
5170 /* Mark as a memory operand only if it's not already known to be an
5171 offset expression. */
5172 if (intel_parser
.op_modifier
!= OFFSET_FLAT
)
5173 intel_parser
.is_mem
= 1;
5175 return (intel_match_token (':') && intel_e10 () && intel_e09_1 ());
5190 return (intel_e11 () && intel_e10_1 ());
5196 /* e10' [ expr ] e10' */
5197 if (cur_token
.code
== '[')
5199 intel_match_token ('[');
5201 /* Mark as a memory operand only if it's not already known to be an
5202 offset expression. If it's an offset expression, we need to keep
5204 if (intel_parser
.op_modifier
!= OFFSET_FLAT
)
5205 intel_parser
.is_mem
= 1;
5207 strcat (intel_parser
.disp
, "[");
5209 /* Add a '+' to the displacement string if necessary. */
5210 if (*intel_parser
.disp
!= '\0'
5211 && *(intel_parser
.disp
+ strlen (intel_parser
.disp
) - 1) != '+')
5212 strcat (intel_parser
.disp
, "+");
5214 if (intel_expr () && intel_match_token (']'))
5216 /* Preserve brackets when the operand is an offset expression. */
5217 if (intel_parser
.op_modifier
== OFFSET_FLAT
)
5218 strcat (intel_parser
.disp
, "]");
5220 return intel_e10_1 ();
5247 if (cur_token
.code
== '(')
5249 intel_match_token ('(');
5250 strcat (intel_parser
.disp
, "(");
5252 if (intel_expr () && intel_match_token (')'))
5254 strcat (intel_parser
.disp
, ")");
5262 else if (cur_token
.code
== '[')
5264 intel_match_token ('[');
5266 /* Mark as a memory operand only if it's not already known to be an
5267 offset expression. If it's an offset expression, we need to keep
5269 if (intel_parser
.op_modifier
!= OFFSET_FLAT
)
5270 intel_parser
.is_mem
= 1;
5272 strcat (intel_parser
.disp
, "[");
5274 /* Operands for jump/call inside brackets denote absolute addresses. */
5275 if (current_templates
->start
->opcode_modifier
& Jump
5276 || current_templates
->start
->opcode_modifier
& JumpDword
5277 || current_templates
->start
->opcode_modifier
& JumpByte
5278 || current_templates
->start
->opcode_modifier
& JumpInterSegment
)
5279 i
.types
[this_operand
] |= JumpAbsolute
;
5281 /* Add a '+' to the displacement string if necessary. */
5282 if (*intel_parser
.disp
!= '\0'
5283 && *(intel_parser
.disp
+ strlen (intel_parser
.disp
) - 1) != '+')
5284 strcat (intel_parser
.disp
, "+");
5286 if (intel_expr () && intel_match_token (']'))
5288 /* Preserve brackets when the operand is an offset expression. */
5289 if (intel_parser
.op_modifier
== OFFSET_FLAT
)
5290 strcat (intel_parser
.disp
, "]");
5303 else if (cur_token
.code
== T_BYTE
5304 || cur_token
.code
== T_WORD
5305 || cur_token
.code
== T_DWORD
5306 || cur_token
.code
== T_QWORD
5307 || cur_token
.code
== T_XWORD
)
5309 intel_match_token (cur_token
.code
);
5316 else if (cur_token
.code
== '$' || cur_token
.code
== '.')
5318 strcat (intel_parser
.disp
, cur_token
.str
);
5319 intel_match_token (cur_token
.code
);
5321 /* Mark as a memory operand only if it's not already known to be an
5322 offset expression. */
5323 if (intel_parser
.op_modifier
!= OFFSET_FLAT
)
5324 intel_parser
.is_mem
= 1;
5330 else if (cur_token
.code
== T_REG
)
5332 const reg_entry
*reg
= intel_parser
.reg
= cur_token
.reg
;
5334 intel_match_token (T_REG
);
5336 /* Check for segment change. */
5337 if (cur_token
.code
== ':')
5339 if (reg
->reg_type
& (SReg2
| SReg3
))
5341 switch (reg
->reg_num
)
5344 i
.seg
[i
.mem_operands
] = &es
;
5347 i
.seg
[i
.mem_operands
] = &cs
;
5350 i
.seg
[i
.mem_operands
] = &ss
;
5353 i
.seg
[i
.mem_operands
] = &ds
;
5356 i
.seg
[i
.mem_operands
] = &fs
;
5359 i
.seg
[i
.mem_operands
] = &gs
;
5365 as_bad (_("`%s' is not a valid segment register"), reg
->reg_name
);
5370 /* Not a segment register. Check for register scaling. */
5371 else if (cur_token
.code
== '*')
5373 if (!intel_parser
.is_mem
)
5375 as_bad (_("Register scaling only allowed in memory operands."));
5379 /* What follows must be a valid scale. */
5380 if (intel_match_token ('*')
5381 && strchr ("01248", *cur_token
.str
))
5384 i
.types
[this_operand
] |= BaseIndex
;
5386 /* Set the scale after setting the register (otherwise,
5387 i386_scale will complain) */
5388 i386_scale (cur_token
.str
);
5389 intel_match_token (T_CONST
);
5393 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
5399 /* No scaling. If this is a memory operand, the register is either a
5400 base register (first occurrence) or an index register (second
5402 else if (intel_parser
.is_mem
&& !(reg
->reg_type
& (SReg2
| SReg3
)))
5404 if (i
.base_reg
&& i
.index_reg
)
5406 as_bad (_("Too many register references in memory operand.\n"));
5410 if (i
.base_reg
== NULL
)
5415 i
.types
[this_operand
] |= BaseIndex
;
5418 /* Offset modifier. Add the register to the displacement string to be
5419 parsed as an immediate expression after we're done. */
5420 else if (intel_parser
.op_modifier
== OFFSET_FLAT
)
5421 strcat (intel_parser
.disp
, reg
->reg_name
);
5423 /* It's neither base nor index nor offset. */
5426 i
.types
[this_operand
] |= reg
->reg_type
& ~BaseIndex
;
5427 i
.op
[this_operand
].regs
= reg
;
5431 /* Since registers are not part of the displacement string (except
5432 when we're parsing offset operands), we may need to remove any
5433 preceding '+' from the displacement string. */
5434 if (*intel_parser
.disp
!= '\0'
5435 && intel_parser
.op_modifier
!= OFFSET_FLAT
)
5437 char *s
= intel_parser
.disp
;
5438 s
+= strlen (s
) - 1;
5447 else if (cur_token
.code
== T_ID
)
5449 /* Add the identifier to the displacement string. */
5450 strcat (intel_parser
.disp
, cur_token
.str
);
5451 intel_match_token (T_ID
);
5453 /* The identifier represents a memory reference only if it's not
5454 preceded by an offset modifier. */
5455 if (intel_parser
.op_modifier
!= OFFSET_FLAT
)
5456 intel_parser
.is_mem
= 1;
5462 else if (cur_token
.code
== T_CONST
5463 || cur_token
.code
== '-'
5464 || cur_token
.code
== '+')
5468 /* Allow constants that start with `+' or `-'. */
5469 if (cur_token
.code
== '-' || cur_token
.code
== '+')
5471 strcat (intel_parser
.disp
, cur_token
.str
);
5472 intel_match_token (cur_token
.code
);
5473 if (cur_token
.code
!= T_CONST
)
5475 as_bad (_("Syntax error. Expecting a constant. Got `%s'.\n"),
5481 save_str
= (char *)malloc (strlen (cur_token
.str
) + 1);
5482 if (save_str
== NULL
)
5484 strcpy (save_str
, cur_token
.str
);
5486 /* Get the next token to check for register scaling. */
5487 intel_match_token (cur_token
.code
);
5489 /* Check if this constant is a scaling factor for an index register. */
5490 if (cur_token
.code
== '*')
5492 if (intel_match_token ('*') && cur_token
.code
== T_REG
)
5494 if (!intel_parser
.is_mem
)
5496 as_bad (_("Register scaling only allowed in memory operands."));
5500 /* The constant is followed by `* reg', so it must be
5502 if (strchr ("01248", *save_str
))
5504 i
.index_reg
= cur_token
.reg
;
5505 i
.types
[this_operand
] |= BaseIndex
;
5507 /* Set the scale after setting the register (otherwise,
5508 i386_scale will complain) */
5509 i386_scale (save_str
);
5510 intel_match_token (T_REG
);
5512 /* Since registers are not part of the displacement
5513 string, we may need to remove any preceding '+' from
5514 the displacement string. */
5515 if (*intel_parser
.disp
!= '\0')
5517 char *s
= intel_parser
.disp
;
5518 s
+= strlen (s
) - 1;
5531 /* The constant was not used for register scaling. Since we have
5532 already consumed the token following `*' we now need to put it
5533 back in the stream. */
5535 intel_putback_token ();
5538 /* Add the constant to the displacement string. */
5539 strcat (intel_parser
.disp
, save_str
);
5545 as_bad (_("Unrecognized token '%s'"), cur_token
.str
);
5549 /* Match the given token against cur_token. If they match, read the next
5550 token from the operand string. */
5552 intel_match_token (code
)
5555 if (cur_token
.code
== code
)
5562 as_bad (_("Unexpected token `%s'\n"), cur_token
.str
);
5567 /* Read a new token from intel_parser.op_string and store it in cur_token. */
5572 const reg_entry
*reg
;
5573 struct intel_token new_token
;
5575 new_token
.code
= T_NIL
;
5576 new_token
.reg
= NULL
;
5577 new_token
.str
= NULL
;
5579 /* Free the memory allocated to the previous token and move
5580 cur_token to prev_token. */
5582 free (prev_token
.str
);
5584 prev_token
= cur_token
;
5586 /* Skip whitespace. */
5587 while (is_space_char (*intel_parser
.op_string
))
5588 intel_parser
.op_string
++;
5590 /* Return an empty token if we find nothing else on the line. */
5591 if (*intel_parser
.op_string
== '\0')
5593 cur_token
= new_token
;
5597 /* The new token cannot be larger than the remainder of the operand
5599 new_token
.str
= (char *)malloc (strlen (intel_parser
.op_string
) + 1);
5600 if (new_token
.str
== NULL
)
5602 new_token
.str
[0] = '\0';
5604 if (strchr ("0123456789", *intel_parser
.op_string
))
5606 char *p
= new_token
.str
;
5607 char *q
= intel_parser
.op_string
;
5608 new_token
.code
= T_CONST
;
5610 /* Allow any kind of identifier char to encompass floating point and
5611 hexadecimal numbers. */
5612 while (is_identifier_char (*q
))
5616 /* Recognize special symbol names [0-9][bf]. */
5617 if (strlen (intel_parser
.op_string
) == 2
5618 && (intel_parser
.op_string
[1] == 'b'
5619 || intel_parser
.op_string
[1] == 'f'))
5620 new_token
.code
= T_ID
;
5623 else if (strchr ("+-/*:[]()", *intel_parser
.op_string
))
5625 new_token
.code
= *intel_parser
.op_string
;
5626 new_token
.str
[0] = *intel_parser
.op_string
;
5627 new_token
.str
[1] = '\0';
5630 else if ((*intel_parser
.op_string
== REGISTER_PREFIX
|| allow_naked_reg
)
5631 && ((reg
= parse_register (intel_parser
.op_string
, &end_op
)) != NULL
))
5633 new_token
.code
= T_REG
;
5634 new_token
.reg
= reg
;
5636 if (*intel_parser
.op_string
== REGISTER_PREFIX
)
5638 new_token
.str
[0] = REGISTER_PREFIX
;
5639 new_token
.str
[1] = '\0';
5642 strcat (new_token
.str
, reg
->reg_name
);
5645 else if (is_identifier_char (*intel_parser
.op_string
))
5647 char *p
= new_token
.str
;
5648 char *q
= intel_parser
.op_string
;
5650 /* A '.' or '$' followed by an identifier char is an identifier.
5651 Otherwise, it's operator '.' followed by an expression. */
5652 if ((*q
== '.' || *q
== '$') && !is_identifier_char (*(q
+ 1)))
5654 new_token
.code
= *q
;
5655 new_token
.str
[0] = *q
;
5656 new_token
.str
[1] = '\0';
5660 while (is_identifier_char (*q
) || *q
== '@')
5664 if (strcasecmp (new_token
.str
, "BYTE") == 0)
5665 new_token
.code
= T_BYTE
;
5667 else if (strcasecmp (new_token
.str
, "WORD") == 0)
5668 new_token
.code
= T_WORD
;
5670 else if (strcasecmp (new_token
.str
, "DWORD") == 0)
5671 new_token
.code
= T_DWORD
;
5673 else if (strcasecmp (new_token
.str
, "QWORD") == 0)
5674 new_token
.code
= T_QWORD
;
5676 else if (strcasecmp (new_token
.str
, "XWORD") == 0)
5677 new_token
.code
= T_XWORD
;
5679 else if (strcasecmp (new_token
.str
, "PTR") == 0)
5680 new_token
.code
= T_PTR
;
5682 else if (strcasecmp (new_token
.str
, "SHORT") == 0)
5683 new_token
.code
= T_SHORT
;
5685 else if (strcasecmp (new_token
.str
, "OFFSET") == 0)
5687 new_token
.code
= T_OFFSET
;
5689 /* ??? This is not mentioned in the MASM grammar but gcc
5690 makes use of it with -mintel-syntax. OFFSET may be
5691 followed by FLAT: */
5692 if (strncasecmp (q
, " FLAT:", 6) == 0)
5693 strcat (new_token
.str
, " FLAT:");
5696 /* ??? This is not mentioned in the MASM grammar. */
5697 else if (strcasecmp (new_token
.str
, "FLAT") == 0)
5698 new_token
.code
= T_OFFSET
;
5701 new_token
.code
= T_ID
;
5706 as_bad (_("Unrecognized token `%s'\n"), intel_parser
.op_string
);
5708 intel_parser
.op_string
+= strlen (new_token
.str
);
5709 cur_token
= new_token
;
5712 /* Put cur_token back into the token stream and make cur_token point to
5715 intel_putback_token ()
5717 intel_parser
.op_string
-= strlen (cur_token
.str
);
5718 free (cur_token
.str
);
5719 cur_token
= prev_token
;
5721 /* Forget prev_token. */
5722 prev_token
.code
= T_NIL
;
5723 prev_token
.reg
= NULL
;
5724 prev_token
.str
= NULL
;