1 /* i386.c -- Assemble code for the Intel 80386
2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005
4 Free Software Foundation, Inc.
6 This file is part of GAS, the GNU Assembler.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
23 /* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
25 x86_64 support by Jan Hubicka (jh@suse.cz)
26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
27 Bugs & suggestions are completely welcome. This is free software.
28 Please help us make it better. */
31 #include "safe-ctype.h"
33 #include "dwarf2dbg.h"
34 #include "dw2gencfi.h"
35 #include "opcode/i386.h"
36 #include "elf/x86-64.h"
38 #ifndef REGISTER_WARNINGS
39 #define REGISTER_WARNINGS 1
42 #ifndef INFER_ADDR_PREFIX
43 #define INFER_ADDR_PREFIX 1
46 #ifndef SCALE1_WHEN_NO_INDEX
47 /* Specifying a scale factor besides 1 when there is no index is
48 futile. eg. `mov (%ebx,2),%al' does exactly the same as
49 `mov (%ebx),%al'. To slavishly follow what the programmer
50 specified, set SCALE1_WHEN_NO_INDEX to 0. */
51 #define SCALE1_WHEN_NO_INDEX 1
55 #define DEFAULT_ARCH "i386"
60 #define INLINE __inline__
66 static INLINE
unsigned int mode_from_disp_size
PARAMS ((unsigned int));
67 static INLINE
int fits_in_signed_byte
PARAMS ((offsetT
));
68 static INLINE
int fits_in_unsigned_byte
PARAMS ((offsetT
));
69 static INLINE
int fits_in_unsigned_word
PARAMS ((offsetT
));
70 static INLINE
int fits_in_signed_word
PARAMS ((offsetT
));
71 static INLINE
int fits_in_unsigned_long
PARAMS ((offsetT
));
72 static INLINE
int fits_in_signed_long
PARAMS ((offsetT
));
73 static int smallest_imm_type
PARAMS ((offsetT
));
74 static offsetT offset_in_range
PARAMS ((offsetT
, int));
75 static int add_prefix
PARAMS ((unsigned int));
76 static void set_code_flag
PARAMS ((int));
77 static void set_16bit_gcc_code_flag
PARAMS ((int));
78 static void set_intel_syntax
PARAMS ((int));
79 static void set_cpu_arch
PARAMS ((int));
81 static void pe_directive_secrel
PARAMS ((int));
83 static char *output_invalid
PARAMS ((int c
));
84 static int i386_operand
PARAMS ((char *operand_string
));
85 static int i386_intel_operand
PARAMS ((char *operand_string
, int got_a_float
));
86 static const reg_entry
*parse_register
PARAMS ((char *reg_string
,
88 static char *parse_insn
PARAMS ((char *, char *));
89 static char *parse_operands
PARAMS ((char *, const char *));
90 static void swap_operands
PARAMS ((void));
91 static void optimize_imm
PARAMS ((void));
92 static void optimize_disp
PARAMS ((void));
93 static int match_template
PARAMS ((void));
94 static int check_string
PARAMS ((void));
95 static int process_suffix
PARAMS ((void));
96 static int check_byte_reg
PARAMS ((void));
97 static int check_long_reg
PARAMS ((void));
98 static int check_qword_reg
PARAMS ((void));
99 static int check_word_reg
PARAMS ((void));
100 static int finalize_imm
PARAMS ((void));
101 static int process_operands
PARAMS ((void));
102 static const seg_entry
*build_modrm_byte
PARAMS ((void));
103 static void output_insn
PARAMS ((void));
104 static void output_branch
PARAMS ((void));
105 static void output_jump
PARAMS ((void));
106 static void output_interseg_jump
PARAMS ((void));
107 static void output_imm
PARAMS ((fragS
*insn_start_frag
,
108 offsetT insn_start_off
));
109 static void output_disp
PARAMS ((fragS
*insn_start_frag
,
110 offsetT insn_start_off
));
112 static void s_bss
PARAMS ((int));
115 static const char *default_arch
= DEFAULT_ARCH
;
117 /* 'md_assemble ()' gathers together information and puts it into a
124 const reg_entry
*regs
;
129 /* TM holds the template for the insn were currently assembling. */
132 /* SUFFIX holds the instruction mnemonic suffix if given.
133 (e.g. 'l' for 'movl') */
136 /* OPERANDS gives the number of given operands. */
137 unsigned int operands
;
139 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
140 of given register, displacement, memory operands and immediate
142 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
144 /* TYPES [i] is the type (see above #defines) which tells us how to
145 use OP[i] for the corresponding operand. */
146 unsigned int types
[MAX_OPERANDS
];
148 /* Displacement expression, immediate expression, or register for each
150 union i386_op op
[MAX_OPERANDS
];
152 /* Flags for operands. */
153 unsigned int flags
[MAX_OPERANDS
];
154 #define Operand_PCrel 1
156 /* Relocation type for operand */
157 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
159 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
160 the base index byte below. */
161 const reg_entry
*base_reg
;
162 const reg_entry
*index_reg
;
163 unsigned int log2_scale_factor
;
165 /* SEG gives the seg_entries of this insn. They are zero unless
166 explicit segment overrides are given. */
167 const seg_entry
*seg
[2];
169 /* PREFIX holds all the given prefix opcodes (usually null).
170 PREFIXES is the number of prefix opcodes. */
171 unsigned int prefixes
;
172 unsigned char prefix
[MAX_PREFIXES
];
174 /* RM and SIB are the modrm byte and the sib byte where the
175 addressing modes of this insn are encoded. */
182 typedef struct _i386_insn i386_insn
;
184 /* List of chars besides those in app.c:symbol_chars that can start an
185 operand. Used to prevent the scrubber eating vital white-space. */
186 const char extra_symbol_chars
[] = "*%-(["
195 #if (defined (TE_I386AIX) \
196 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
197 && !defined (TE_LINUX) \
198 && !defined (TE_NETWARE) \
199 && !defined (TE_FreeBSD) \
200 && !defined (TE_NetBSD)))
201 /* This array holds the chars that always start a comment. If the
202 pre-processor is disabled, these aren't very useful. */
203 const char comment_chars
[] = "#/";
204 #define PREFIX_SEPARATOR '\\'
206 /* This array holds the chars that only start a comment at the beginning of
207 a line. If the line seems to have the form '# 123 filename'
208 .line and .file directives will appear in the pre-processed output.
209 Note that input_file.c hand checks for '#' at the beginning of the
210 first line of the input file. This is because the compiler outputs
211 #NO_APP at the beginning of its output.
212 Also note that comments started like this one will always work if
213 '/' isn't otherwise defined. */
214 const char line_comment_chars
[] = "#";
217 /* Putting '/' here makes it impossible to use the divide operator.
218 However, we need it for compatibility with SVR4 systems. */
219 const char comment_chars
[] = "#";
220 #define PREFIX_SEPARATOR '/'
222 const char line_comment_chars
[] = "/#";
225 const char line_separator_chars
[] = ";";
227 /* Chars that can be used to separate mant from exp in floating point
229 const char EXP_CHARS
[] = "eE";
231 /* Chars that mean this number is a floating point constant
234 const char FLT_CHARS
[] = "fFdDxX";
236 /* Tables for lexical analysis. */
237 static char mnemonic_chars
[256];
238 static char register_chars
[256];
239 static char operand_chars
[256];
240 static char identifier_chars
[256];
241 static char digit_chars
[256];
243 /* Lexical macros. */
244 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
245 #define is_operand_char(x) (operand_chars[(unsigned char) x])
246 #define is_register_char(x) (register_chars[(unsigned char) x])
247 #define is_space_char(x) ((x) == ' ')
248 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
249 #define is_digit_char(x) (digit_chars[(unsigned char) x])
251 /* All non-digit non-letter characters that may occur in an operand. */
252 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
254 /* md_assemble() always leaves the strings it's passed unaltered. To
255 effect this we maintain a stack of saved characters that we've smashed
256 with '\0's (indicating end of strings for various sub-fields of the
257 assembler instruction). */
258 static char save_stack
[32];
259 static char *save_stack_p
;
260 #define END_STRING_AND_SAVE(s) \
261 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
262 #define RESTORE_END_STRING(s) \
263 do { *(s) = *--save_stack_p; } while (0)
265 /* The instruction we're assembling. */
268 /* Possible templates for current insn. */
269 static const templates
*current_templates
;
271 /* Per instruction expressionS buffers: 2 displacements & 2 immediate max. */
272 static expressionS disp_expressions
[2], im_expressions
[2];
274 /* Current operand we are working on. */
275 static int this_operand
;
277 /* We support four different modes. FLAG_CODE variable is used to distinguish
284 #define NUM_FLAG_CODE ((int) CODE_64BIT + 1)
286 static enum flag_code flag_code
;
287 static int use_rela_relocations
= 0;
289 /* The names used to print error messages. */
290 static const char *flag_code_names
[] =
297 /* 1 for intel syntax,
299 static int intel_syntax
= 0;
301 /* 1 if register prefix % not required. */
302 static int allow_naked_reg
= 0;
304 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
305 leave, push, and pop instructions so that gcc has the same stack
306 frame as in 32 bit mode. */
307 static char stackop_size
= '\0';
308 static void handle_large_common (int small ATTRIBUTE_UNUSED
);
310 /* Non-zero to optimize code alignment. */
311 int optimize_align_code
= 1;
313 /* Non-zero to quieten some warnings. */
314 static int quiet_warnings
= 0;
317 static const char *cpu_arch_name
= NULL
;
318 static const char *cpu_sub_arch_name
= NULL
;
320 /* CPU feature flags. */
321 static unsigned int cpu_arch_flags
= CpuUnknownFlags
| CpuNo64
;
323 /* If set, conditional jumps are not automatically promoted to handle
324 larger than a byte offset. */
325 static unsigned int no_cond_jump_promotion
= 0;
327 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
328 static symbolS
*GOT_symbol
;
330 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
331 unsigned int x86_dwarf2_return_column
;
333 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
334 int x86_cie_data_alignment
;
336 /* Interface to relax_segment.
337 There are 3 major relax states for 386 jump insns because the
338 different types of jumps add different sizes to frags when we're
339 figuring out what sort of jump to choose to reach a given label. */
342 #define UNCOND_JUMP 0
344 #define COND_JUMP86 2
349 #define SMALL16 (SMALL | CODE16)
351 #define BIG16 (BIG | CODE16)
355 #define INLINE __inline__
361 #define ENCODE_RELAX_STATE(type, size) \
362 ((relax_substateT) (((type) << 2) | (size)))
363 #define TYPE_FROM_RELAX_STATE(s) \
365 #define DISP_SIZE_FROM_RELAX_STATE(s) \
366 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
368 /* This table is used by relax_frag to promote short jumps to long
369 ones where necessary. SMALL (short) jumps may be promoted to BIG
370 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
371 don't allow a short jump in a 32 bit code segment to be promoted to
372 a 16 bit offset jump because it's slower (requires data size
373 prefix), and doesn't work, unless the destination is in the bottom
374 64k of the code segment (The top 16 bits of eip are zeroed). */
376 const relax_typeS md_relax_table
[] =
379 1) most positive reach of this state,
380 2) most negative reach of this state,
381 3) how many bytes this mode will have in the variable part of the frag
382 4) which index into the table to try if we can't fit into this one. */
384 /* UNCOND_JUMP states. */
385 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
386 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
387 /* dword jmp adds 4 bytes to frag:
388 0 extra opcode bytes, 4 displacement bytes. */
390 /* word jmp adds 2 byte2 to frag:
391 0 extra opcode bytes, 2 displacement bytes. */
394 /* COND_JUMP states. */
395 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
396 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
397 /* dword conditionals adds 5 bytes to frag:
398 1 extra opcode byte, 4 displacement bytes. */
400 /* word conditionals add 3 bytes to frag:
401 1 extra opcode byte, 2 displacement bytes. */
404 /* COND_JUMP86 states. */
405 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
406 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
407 /* dword conditionals adds 5 bytes to frag:
408 1 extra opcode byte, 4 displacement bytes. */
410 /* word conditionals add 4 bytes to frag:
411 1 displacement byte and a 3 byte long branch insn. */
415 static const arch_entry cpu_arch
[] = {
417 {"i186", Cpu086
|Cpu186
},
418 {"i286", Cpu086
|Cpu186
|Cpu286
},
419 {"i386", Cpu086
|Cpu186
|Cpu286
|Cpu386
},
420 {"i486", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
},
421 {"i586", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
},
422 {"i686", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
},
423 {"pentium", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
},
424 {"pentiumpro",Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
},
425 {"pentiumii", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuMMX
},
426 {"pentiumiii",Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuMMX
|CpuMMX2
|CpuSSE
},
427 {"pentium4", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuP4
|CpuMMX
|CpuMMX2
|CpuSSE
|CpuSSE2
},
428 {"prescott", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuP4
|CpuMMX
|CpuMMX2
|CpuSSE
|CpuSSE2
|CpuPNI
},
429 {"k6", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|CpuK6
|CpuMMX
},
430 {"k6_2", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|CpuK6
|CpuMMX
|Cpu3dnow
},
431 {"athlon", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuK6
|CpuAthlon
|CpuMMX
|CpuMMX2
|Cpu3dnow
|Cpu3dnowA
},
432 {"sledgehammer",Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuK6
|CpuAthlon
|CpuSledgehammer
|CpuMMX
|CpuMMX2
|Cpu3dnow
|Cpu3dnowA
|CpuSSE
|CpuSSE2
},
433 {"opteron", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuK6
|CpuAthlon
|CpuSledgehammer
|CpuMMX
|CpuMMX2
|Cpu3dnow
|Cpu3dnowA
|CpuSSE
|CpuSSE2
},
435 {".sse", CpuMMX
|CpuMMX2
|CpuSSE
},
436 {".sse2", CpuMMX
|CpuMMX2
|CpuSSE
|CpuSSE2
},
437 {".sse3", CpuMMX
|CpuMMX2
|CpuSSE
|CpuSSE2
|CpuSSE3
},
438 {".3dnow", CpuMMX
|Cpu3dnow
},
439 {".3dnowa", CpuMMX
|CpuMMX2
|Cpu3dnow
|Cpu3dnowA
},
440 {".padlock", CpuPadLock
},
441 {".pacifica", CpuSVME
},
446 const pseudo_typeS md_pseudo_table
[] =
448 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
449 {"align", s_align_bytes
, 0},
451 {"align", s_align_ptwo
, 0},
453 {"arch", set_cpu_arch
, 0},
457 {"ffloat", float_cons
, 'f'},
458 {"dfloat", float_cons
, 'd'},
459 {"tfloat", float_cons
, 'x'},
461 {"noopt", s_ignore
, 0},
462 {"optim", s_ignore
, 0},
463 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
464 {"code16", set_code_flag
, CODE_16BIT
},
465 {"code32", set_code_flag
, CODE_32BIT
},
466 {"code64", set_code_flag
, CODE_64BIT
},
467 {"intel_syntax", set_intel_syntax
, 1},
468 {"att_syntax", set_intel_syntax
, 0},
469 {"file", (void (*) PARAMS ((int))) dwarf2_directive_file
, 0},
470 {"loc", dwarf2_directive_loc
, 0},
471 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
472 {"largecomm", handle_large_common
, 0},
475 {"secrel32", pe_directive_secrel
, 0},
480 /* For interface with expression (). */
481 extern char *input_line_pointer
;
483 /* Hash table for instruction mnemonic lookup. */
484 static struct hash_control
*op_hash
;
486 /* Hash table for register lookup. */
487 static struct hash_control
*reg_hash
;
490 i386_align_code (fragP
, count
)
494 /* Various efficient no-op patterns for aligning code labels.
495 Note: Don't try to assemble the instructions in the comments.
496 0L and 0w are not legal. */
497 static const char f32_1
[] =
499 static const char f32_2
[] =
500 {0x89,0xf6}; /* movl %esi,%esi */
501 static const char f32_3
[] =
502 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
503 static const char f32_4
[] =
504 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
505 static const char f32_5
[] =
507 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
508 static const char f32_6
[] =
509 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
510 static const char f32_7
[] =
511 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
512 static const char f32_8
[] =
514 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
515 static const char f32_9
[] =
516 {0x89,0xf6, /* movl %esi,%esi */
517 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
518 static const char f32_10
[] =
519 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
520 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
521 static const char f32_11
[] =
522 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
523 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
524 static const char f32_12
[] =
525 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
526 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
527 static const char f32_13
[] =
528 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
529 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
530 static const char f32_14
[] =
531 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
532 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
533 static const char f32_15
[] =
534 {0xeb,0x0d,0x90,0x90,0x90,0x90,0x90, /* jmp .+15; lotsa nops */
535 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
536 static const char f16_3
[] =
537 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
538 static const char f16_4
[] =
539 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
540 static const char f16_5
[] =
542 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
543 static const char f16_6
[] =
544 {0x89,0xf6, /* mov %si,%si */
545 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
546 static const char f16_7
[] =
547 {0x8d,0x74,0x00, /* lea 0(%si),%si */
548 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
549 static const char f16_8
[] =
550 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
551 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
552 static const char *const f32_patt
[] = {
553 f32_1
, f32_2
, f32_3
, f32_4
, f32_5
, f32_6
, f32_7
, f32_8
,
554 f32_9
, f32_10
, f32_11
, f32_12
, f32_13
, f32_14
, f32_15
556 static const char *const f16_patt
[] = {
557 f32_1
, f32_2
, f16_3
, f16_4
, f16_5
, f16_6
, f16_7
, f16_8
,
558 f32_15
, f32_15
, f32_15
, f32_15
, f32_15
, f32_15
, f32_15
561 if (count
<= 0 || count
> 15)
564 /* The recommended way to pad 64bit code is to use NOPs preceded by
565 maximally four 0x66 prefixes. Balance the size of nops. */
566 if (flag_code
== CODE_64BIT
)
569 int nnops
= (count
+ 3) / 4;
570 int len
= count
/ nnops
;
571 int remains
= count
- nnops
* len
;
574 for (i
= 0; i
< remains
; i
++)
576 memset (fragP
->fr_literal
+ fragP
->fr_fix
+ pos
, 0x66, len
);
577 fragP
->fr_literal
[fragP
->fr_fix
+ pos
+ len
] = 0x90;
580 for (; i
< nnops
; i
++)
582 memset (fragP
->fr_literal
+ fragP
->fr_fix
+ pos
, 0x66, len
- 1);
583 fragP
->fr_literal
[fragP
->fr_fix
+ pos
+ len
- 1] = 0x90;
588 if (flag_code
== CODE_16BIT
)
590 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
591 f16_patt
[count
- 1], count
);
593 /* Adjust jump offset. */
594 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
597 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
598 f32_patt
[count
- 1], count
);
599 fragP
->fr_var
= count
;
602 static INLINE
unsigned int
603 mode_from_disp_size (t
)
606 return (t
& Disp8
) ? 1 : (t
& (Disp16
| Disp32
| Disp32S
)) ? 2 : 0;
610 fits_in_signed_byte (num
)
613 return (num
>= -128) && (num
<= 127);
617 fits_in_unsigned_byte (num
)
620 return (num
& 0xff) == num
;
624 fits_in_unsigned_word (num
)
627 return (num
& 0xffff) == num
;
631 fits_in_signed_word (num
)
634 return (-32768 <= num
) && (num
<= 32767);
637 fits_in_signed_long (num
)
638 offsetT num ATTRIBUTE_UNUSED
;
643 return (!(((offsetT
) -1 << 31) & num
)
644 || (((offsetT
) -1 << 31) & num
) == ((offsetT
) -1 << 31));
646 } /* fits_in_signed_long() */
648 fits_in_unsigned_long (num
)
649 offsetT num ATTRIBUTE_UNUSED
;
654 return (num
& (((offsetT
) 2 << 31) - 1)) == num
;
656 } /* fits_in_unsigned_long() */
659 smallest_imm_type (num
)
662 if (cpu_arch_flags
!= (Cpu086
| Cpu186
| Cpu286
| Cpu386
| Cpu486
| CpuNo64
))
664 /* This code is disabled on the 486 because all the Imm1 forms
665 in the opcode table are slower on the i486. They're the
666 versions with the implicitly specified single-position
667 displacement, which has another syntax if you really want to
670 return Imm1
| Imm8
| Imm8S
| Imm16
| Imm32
| Imm32S
| Imm64
;
672 return (fits_in_signed_byte (num
)
673 ? (Imm8S
| Imm8
| Imm16
| Imm32
| Imm32S
| Imm64
)
674 : fits_in_unsigned_byte (num
)
675 ? (Imm8
| Imm16
| Imm32
| Imm32S
| Imm64
)
676 : (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
677 ? (Imm16
| Imm32
| Imm32S
| Imm64
)
678 : fits_in_signed_long (num
)
679 ? (Imm32
| Imm32S
| Imm64
)
680 : fits_in_unsigned_long (num
)
686 offset_in_range (val
, size
)
694 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
695 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
696 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
698 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
703 /* If BFD64, sign extend val. */
704 if (!use_rela_relocations
)
705 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
706 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
708 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
710 char buf1
[40], buf2
[40];
712 sprint_value (buf1
, val
);
713 sprint_value (buf2
, val
& mask
);
714 as_warn (_("%s shortened to %s"), buf1
, buf2
);
719 /* Returns 0 if attempting to add a prefix where one from the same
720 class already exists, 1 if non rep/repne added, 2 if rep/repne
729 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
730 && flag_code
== CODE_64BIT
)
738 case CS_PREFIX_OPCODE
:
739 case DS_PREFIX_OPCODE
:
740 case ES_PREFIX_OPCODE
:
741 case FS_PREFIX_OPCODE
:
742 case GS_PREFIX_OPCODE
:
743 case SS_PREFIX_OPCODE
:
747 case REPNE_PREFIX_OPCODE
:
748 case REPE_PREFIX_OPCODE
:
751 case LOCK_PREFIX_OPCODE
:
759 case ADDR_PREFIX_OPCODE
:
763 case DATA_PREFIX_OPCODE
:
768 if (i
.prefix
[q
] != 0)
770 as_bad (_("same type of prefix used twice"));
775 i
.prefix
[q
] = prefix
;
780 set_code_flag (value
)
784 cpu_arch_flags
&= ~(Cpu64
| CpuNo64
);
785 cpu_arch_flags
|= (flag_code
== CODE_64BIT
? Cpu64
: CpuNo64
);
786 if (value
== CODE_64BIT
&& !(cpu_arch_flags
& CpuSledgehammer
))
788 as_bad (_("64bit mode not supported on this CPU."));
790 if (value
== CODE_32BIT
&& !(cpu_arch_flags
& Cpu386
))
792 as_bad (_("32bit mode not supported on this CPU."));
798 set_16bit_gcc_code_flag (new_code_flag
)
801 flag_code
= new_code_flag
;
802 cpu_arch_flags
&= ~(Cpu64
| CpuNo64
);
803 cpu_arch_flags
|= (flag_code
== CODE_64BIT
? Cpu64
: CpuNo64
);
804 stackop_size
= LONG_MNEM_SUFFIX
;
808 set_intel_syntax (syntax_flag
)
811 /* Find out if register prefixing is specified. */
812 int ask_naked_reg
= 0;
815 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
817 char *string
= input_line_pointer
;
818 int e
= get_symbol_end ();
820 if (strcmp (string
, "prefix") == 0)
822 else if (strcmp (string
, "noprefix") == 0)
825 as_bad (_("bad argument to syntax directive."));
826 *input_line_pointer
= e
;
828 demand_empty_rest_of_line ();
830 intel_syntax
= syntax_flag
;
832 if (ask_naked_reg
== 0)
833 allow_naked_reg
= (intel_syntax
834 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
836 allow_naked_reg
= (ask_naked_reg
< 0);
838 identifier_chars
['%'] = intel_syntax
&& allow_naked_reg
? '%' : 0;
839 identifier_chars
['$'] = intel_syntax
? '$' : 0;
844 int dummy ATTRIBUTE_UNUSED
;
848 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
850 char *string
= input_line_pointer
;
851 int e
= get_symbol_end ();
854 for (i
= 0; cpu_arch
[i
].name
; i
++)
856 if (strcmp (string
, cpu_arch
[i
].name
) == 0)
860 cpu_arch_name
= cpu_arch
[i
].name
;
861 cpu_sub_arch_name
= NULL
;
862 cpu_arch_flags
= (cpu_arch
[i
].flags
863 | (flag_code
== CODE_64BIT
? Cpu64
: CpuNo64
));
866 if ((cpu_arch_flags
| cpu_arch
[i
].flags
) != cpu_arch_flags
)
868 cpu_sub_arch_name
= cpu_arch
[i
].name
;
869 cpu_arch_flags
|= cpu_arch
[i
].flags
;
871 *input_line_pointer
= e
;
872 demand_empty_rest_of_line ();
876 if (!cpu_arch
[i
].name
)
877 as_bad (_("no such architecture: `%s'"), string
);
879 *input_line_pointer
= e
;
882 as_bad (_("missing cpu architecture"));
884 no_cond_jump_promotion
= 0;
885 if (*input_line_pointer
== ','
886 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
888 char *string
= ++input_line_pointer
;
889 int e
= get_symbol_end ();
891 if (strcmp (string
, "nojumps") == 0)
892 no_cond_jump_promotion
= 1;
893 else if (strcmp (string
, "jumps") == 0)
896 as_bad (_("no such architecture modifier: `%s'"), string
);
898 *input_line_pointer
= e
;
901 demand_empty_rest_of_line ();
907 if (!strcmp (default_arch
, "x86_64"))
908 return bfd_mach_x86_64
;
909 else if (!strcmp (default_arch
, "i386"))
910 return bfd_mach_i386_i386
;
912 as_fatal (_("Unknown architecture"));
918 const char *hash_err
;
920 /* Initialize op_hash hash table. */
921 op_hash
= hash_new ();
924 const template *optab
;
925 templates
*core_optab
;
927 /* Setup for loop. */
929 core_optab
= (templates
*) xmalloc (sizeof (templates
));
930 core_optab
->start
= optab
;
935 if (optab
->name
== NULL
936 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
938 /* different name --> ship out current template list;
939 add to hash table; & begin anew. */
940 core_optab
->end
= optab
;
941 hash_err
= hash_insert (op_hash
,
946 as_fatal (_("Internal Error: Can't hash %s: %s"),
950 if (optab
->name
== NULL
)
952 core_optab
= (templates
*) xmalloc (sizeof (templates
));
953 core_optab
->start
= optab
;
958 /* Initialize reg_hash hash table. */
959 reg_hash
= hash_new ();
961 const reg_entry
*regtab
;
963 for (regtab
= i386_regtab
;
964 regtab
< i386_regtab
+ sizeof (i386_regtab
) / sizeof (i386_regtab
[0]);
967 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (PTR
) regtab
);
969 as_fatal (_("Internal Error: Can't hash %s: %s"),
975 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
980 for (c
= 0; c
< 256; c
++)
985 mnemonic_chars
[c
] = c
;
986 register_chars
[c
] = c
;
987 operand_chars
[c
] = c
;
989 else if (ISLOWER (c
))
991 mnemonic_chars
[c
] = c
;
992 register_chars
[c
] = c
;
993 operand_chars
[c
] = c
;
995 else if (ISUPPER (c
))
997 mnemonic_chars
[c
] = TOLOWER (c
);
998 register_chars
[c
] = mnemonic_chars
[c
];
999 operand_chars
[c
] = c
;
1002 if (ISALPHA (c
) || ISDIGIT (c
))
1003 identifier_chars
[c
] = c
;
1006 identifier_chars
[c
] = c
;
1007 operand_chars
[c
] = c
;
1012 identifier_chars
['@'] = '@';
1015 identifier_chars
['?'] = '?';
1016 operand_chars
['?'] = '?';
1018 digit_chars
['-'] = '-';
1019 mnemonic_chars
['-'] = '-';
1020 identifier_chars
['_'] = '_';
1021 identifier_chars
['.'] = '.';
1023 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
1024 operand_chars
[(unsigned char) *p
] = *p
;
1027 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1030 record_alignment (text_section
, 2);
1031 record_alignment (data_section
, 2);
1032 record_alignment (bss_section
, 2);
1036 if (flag_code
== CODE_64BIT
)
1038 x86_dwarf2_return_column
= 16;
1039 x86_cie_data_alignment
= -8;
1043 x86_dwarf2_return_column
= 8;
1044 x86_cie_data_alignment
= -4;
1049 i386_print_statistics (file
)
1052 hash_print_statistics (file
, "i386 opcode", op_hash
);
1053 hash_print_statistics (file
, "i386 register", reg_hash
);
1058 /* Debugging routines for md_assemble. */
1059 static void pi
PARAMS ((char *, i386_insn
*));
1060 static void pte
PARAMS ((template *));
1061 static void pt
PARAMS ((unsigned int));
1062 static void pe
PARAMS ((expressionS
*));
1063 static void ps
PARAMS ((symbolS
*));
1072 fprintf (stdout
, "%s: template ", line
);
1074 fprintf (stdout
, " address: base %s index %s scale %x\n",
1075 x
->base_reg
? x
->base_reg
->reg_name
: "none",
1076 x
->index_reg
? x
->index_reg
->reg_name
: "none",
1077 x
->log2_scale_factor
);
1078 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
1079 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
1080 fprintf (stdout
, " sib: base %x index %x scale %x\n",
1081 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
1082 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
1083 (x
->rex
& REX_MODE64
) != 0,
1084 (x
->rex
& REX_EXTX
) != 0,
1085 (x
->rex
& REX_EXTY
) != 0,
1086 (x
->rex
& REX_EXTZ
) != 0);
1087 for (i
= 0; i
< x
->operands
; i
++)
1089 fprintf (stdout
, " #%d: ", i
+ 1);
1091 fprintf (stdout
, "\n");
1093 & (Reg
| SReg2
| SReg3
| Control
| Debug
| Test
| RegMMX
| RegXMM
))
1094 fprintf (stdout
, "%s\n", x
->op
[i
].regs
->reg_name
);
1095 if (x
->types
[i
] & Imm
)
1097 if (x
->types
[i
] & Disp
)
1098 pe (x
->op
[i
].disps
);
1107 fprintf (stdout
, " %d operands ", t
->operands
);
1108 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
1109 if (t
->extension_opcode
!= None
)
1110 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
1111 if (t
->opcode_modifier
& D
)
1112 fprintf (stdout
, "D");
1113 if (t
->opcode_modifier
& W
)
1114 fprintf (stdout
, "W");
1115 fprintf (stdout
, "\n");
1116 for (i
= 0; i
< t
->operands
; i
++)
1118 fprintf (stdout
, " #%d type ", i
+ 1);
1119 pt (t
->operand_types
[i
]);
1120 fprintf (stdout
, "\n");
1128 fprintf (stdout
, " operation %d\n", e
->X_op
);
1129 fprintf (stdout
, " add_number %ld (%lx)\n",
1130 (long) e
->X_add_number
, (long) e
->X_add_number
);
1131 if (e
->X_add_symbol
)
1133 fprintf (stdout
, " add_symbol ");
1134 ps (e
->X_add_symbol
);
1135 fprintf (stdout
, "\n");
1139 fprintf (stdout
, " op_symbol ");
1140 ps (e
->X_op_symbol
);
1141 fprintf (stdout
, "\n");
1149 fprintf (stdout
, "%s type %s%s",
1151 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
1152 segment_name (S_GET_SEGMENT (s
)));
1161 static const type_names
[] =
1174 { BaseIndex
, "BaseIndex" },
1178 { Disp32S
, "d32s" },
1180 { InOutPortReg
, "InOutPortReg" },
1181 { ShiftCount
, "ShiftCount" },
1182 { Control
, "control reg" },
1183 { Test
, "test reg" },
1184 { Debug
, "debug reg" },
1185 { FloatReg
, "FReg" },
1186 { FloatAcc
, "FAcc" },
1190 { JumpAbsolute
, "Jump Absolute" },
1201 const struct type_name
*ty
;
1203 for (ty
= type_names
; ty
->mask
; ty
++)
1205 fprintf (stdout
, "%s, ", ty
->tname
);
1209 #endif /* DEBUG386 */
1211 static bfd_reloc_code_real_type
1212 reloc (unsigned int size
,
1215 bfd_reloc_code_real_type other
)
1217 if (other
!= NO_RELOC
)
1219 reloc_howto_type
*reloc
;
1224 case BFD_RELOC_X86_64_TPOFF32
:
1225 other
= BFD_RELOC_X86_64_TPOFF64
;
1227 case BFD_RELOC_X86_64_DTPOFF32
:
1228 other
= BFD_RELOC_X86_64_DTPOFF64
;
1233 reloc
= bfd_reloc_type_lookup (stdoutput
, other
);
1235 as_bad (_("unknown relocation (%u)"), other
);
1236 else if (size
!= bfd_get_reloc_size (reloc
))
1237 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
1238 bfd_get_reloc_size (reloc
),
1240 else if (pcrel
&& !reloc
->pc_relative
)
1241 as_bad (_("non-pc-relative relocation for pc-relative field"));
1242 else if ((reloc
->complain_on_overflow
== complain_overflow_signed
1244 || (reloc
->complain_on_overflow
== complain_overflow_unsigned
1246 as_bad (_("relocated field and relocation type differ in signedness"));
1255 as_bad (_("there are no unsigned pc-relative relocations"));
1258 case 1: return BFD_RELOC_8_PCREL
;
1259 case 2: return BFD_RELOC_16_PCREL
;
1260 case 4: return BFD_RELOC_32_PCREL
;
1261 case 8: return BFD_RELOC_64_PCREL
;
1263 as_bad (_("cannot do %u byte pc-relative relocation"), size
);
1270 case 4: return BFD_RELOC_X86_64_32S
;
1275 case 1: return BFD_RELOC_8
;
1276 case 2: return BFD_RELOC_16
;
1277 case 4: return BFD_RELOC_32
;
1278 case 8: return BFD_RELOC_64
;
1280 as_bad (_("cannot do %s %u byte relocation"),
1281 sign
> 0 ? "signed" : "unsigned", size
);
1285 return BFD_RELOC_NONE
;
1288 /* Here we decide which fixups can be adjusted to make them relative to
1289 the beginning of the section instead of the symbol. Basically we need
1290 to make sure that the dynamic relocations are done correctly, so in
1291 some cases we force the original symbol to be used. */
1294 tc_i386_fix_adjustable (fixP
)
1295 fixS
*fixP ATTRIBUTE_UNUSED
;
1297 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1301 /* Don't adjust pc-relative references to merge sections in 64-bit
1303 if (use_rela_relocations
1304 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
1308 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
1309 and changed later by validate_fix. */
1310 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
1311 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
1314 /* adjust_reloc_syms doesn't know about the GOT. */
1315 if (fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
1316 || fixP
->fx_r_type
== BFD_RELOC_386_PLT32
1317 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
1318 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
1319 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
1320 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
1321 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
1322 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
1323 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
1324 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
1325 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
1326 || fixP
->fx_r_type
== BFD_RELOC_X86_64_PLT32
1327 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
1328 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
1329 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
1330 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
1331 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
1332 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
1333 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
1334 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
1335 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
1336 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
1337 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
1338 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
1344 static int intel_float_operand
PARAMS ((const char *mnemonic
));
1347 intel_float_operand (mnemonic
)
1348 const char *mnemonic
;
1350 /* Note that the value returned is meaningful only for opcodes with (memory)
1351 operands, hence the code here is free to improperly handle opcodes that
1352 have no operands (for better performance and smaller code). */
1354 if (mnemonic
[0] != 'f')
1355 return 0; /* non-math */
1357 switch (mnemonic
[1])
1359 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
1360 the fs segment override prefix not currently handled because no
1361 call path can make opcodes without operands get here */
1363 return 2 /* integer op */;
1365 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
1366 return 3; /* fldcw/fldenv */
1369 if (mnemonic
[2] != 'o' /* fnop */)
1370 return 3; /* non-waiting control op */
1373 if (mnemonic
[2] == 's')
1374 return 3; /* frstor/frstpm */
1377 if (mnemonic
[2] == 'a')
1378 return 3; /* fsave */
1379 if (mnemonic
[2] == 't')
1381 switch (mnemonic
[3])
1383 case 'c': /* fstcw */
1384 case 'd': /* fstdw */
1385 case 'e': /* fstenv */
1386 case 's': /* fsts[gw] */
1392 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
1393 return 0; /* fxsave/fxrstor are not really math ops */
1400 /* This is the guts of the machine-dependent assembler. LINE points to a
1401 machine dependent instruction. This function is supposed to emit
1402 the frags/bytes it assembles to. */
1409 char mnemonic
[MAX_MNEM_SIZE
];
1411 /* Initialize globals. */
1412 memset (&i
, '\0', sizeof (i
));
1413 for (j
= 0; j
< MAX_OPERANDS
; j
++)
1414 i
.reloc
[j
] = NO_RELOC
;
1415 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
1416 memset (im_expressions
, '\0', sizeof (im_expressions
));
1417 save_stack_p
= save_stack
;
1419 /* First parse an instruction mnemonic & call i386_operand for the operands.
1420 We assume that the scrubber has arranged it so that line[0] is the valid
1421 start of a (possibly prefixed) mnemonic. */
1423 line
= parse_insn (line
, mnemonic
);
1427 line
= parse_operands (line
, mnemonic
);
1431 /* Now we've parsed the mnemonic into a set of templates, and have the
1432 operands at hand. */
1434 /* All intel opcodes have reversed operands except for "bound" and
1435 "enter". We also don't reverse intersegment "jmp" and "call"
1436 instructions with 2 immediate operands so that the immediate segment
1437 precedes the offset, as it does when in AT&T mode. "enter" and the
1438 intersegment "jmp" and "call" instructions are the only ones that
1439 have two immediate operands. */
1440 if (intel_syntax
&& i
.operands
> 1
1441 && (strcmp (mnemonic
, "bound") != 0)
1442 && (strcmp (mnemonic
, "invlpga") != 0)
1443 && !((i
.types
[0] & Imm
) && (i
.types
[1] & Imm
)))
1449 /* Don't optimize displacement for movabs since it only takes 64bit
1452 && (flag_code
!= CODE_64BIT
1453 || strcmp (mnemonic
, "movabs") != 0))
1456 /* Next, we find a template that matches the given insn,
1457 making sure the overlap of the given operands types is consistent
1458 with the template operand types. */
1460 if (!match_template ())
1465 /* Undo SYSV386_COMPAT brokenness when in Intel mode. See i386.h */
1467 && (i
.tm
.base_opcode
& 0xfffffde0) == 0xdce0)
1468 i
.tm
.base_opcode
^= FloatR
;
1470 /* Zap movzx and movsx suffix. The suffix may have been set from
1471 "word ptr" or "byte ptr" on the source operand, but we'll use
1472 the suffix later to choose the destination register. */
1473 if ((i
.tm
.base_opcode
& ~9) == 0x0fb6)
1475 if (i
.reg_operands
< 2
1477 && (~i
.tm
.opcode_modifier
1484 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
1490 if (i
.tm
.opcode_modifier
& FWait
)
1491 if (!add_prefix (FWAIT_OPCODE
))
1494 /* Check string instruction segment overrides. */
1495 if ((i
.tm
.opcode_modifier
& IsString
) != 0 && i
.mem_operands
!= 0)
1497 if (!check_string ())
1501 if (!process_suffix ())
1504 /* Make still unresolved immediate matches conform to size of immediate
1505 given in i.suffix. */
1506 if (!finalize_imm ())
1509 if (i
.types
[0] & Imm1
)
1510 i
.imm_operands
= 0; /* kludge for shift insns. */
1511 if (i
.types
[0] & ImplicitRegister
)
1513 if (i
.types
[1] & ImplicitRegister
)
1515 if (i
.types
[2] & ImplicitRegister
)
1518 if (i
.tm
.opcode_modifier
& ImmExt
)
1522 if ((i
.tm
.cpu_flags
& CpuPNI
) && i
.operands
> 0)
1524 /* These Intel Prescott New Instructions have the fixed
1525 operands with an opcode suffix which is coded in the same
1526 place as an 8-bit immediate field would be. Here we check
1527 those operands and remove them afterwards. */
1530 for (x
= 0; x
< i
.operands
; x
++)
1531 if (i
.op
[x
].regs
->reg_num
!= x
)
1532 as_bad (_("can't use register '%%%s' as operand %d in '%s'."),
1533 i
.op
[x
].regs
->reg_name
, x
+ 1, i
.tm
.name
);
1537 /* These AMD 3DNow! and Intel Katmai New Instructions have an
1538 opcode suffix which is coded in the same place as an 8-bit
1539 immediate field would be. Here we fake an 8-bit immediate
1540 operand from the opcode suffix stored in tm.extension_opcode. */
1542 assert (i
.imm_operands
== 0 && i
.operands
<= 2 && 2 < MAX_OPERANDS
);
1544 exp
= &im_expressions
[i
.imm_operands
++];
1545 i
.op
[i
.operands
].imms
= exp
;
1546 i
.types
[i
.operands
++] = Imm8
;
1547 exp
->X_op
= O_constant
;
1548 exp
->X_add_number
= i
.tm
.extension_opcode
;
1549 i
.tm
.extension_opcode
= None
;
1552 /* For insns with operands there are more diddles to do to the opcode. */
1555 if (!process_operands ())
1558 else if (!quiet_warnings
&& (i
.tm
.opcode_modifier
& Ugh
) != 0)
1560 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
1561 as_warn (_("translating to `%sp'"), i
.tm
.name
);
1564 /* Handle conversion of 'int $3' --> special int3 insn. */
1565 if (i
.tm
.base_opcode
== INT_OPCODE
&& i
.op
[0].imms
->X_add_number
== 3)
1567 i
.tm
.base_opcode
= INT3_OPCODE
;
1571 if ((i
.tm
.opcode_modifier
& (Jump
| JumpByte
| JumpDword
))
1572 && i
.op
[0].disps
->X_op
== O_constant
)
1574 /* Convert "jmp constant" (and "call constant") to a jump (call) to
1575 the absolute address given by the constant. Since ix86 jumps and
1576 calls are pc relative, we need to generate a reloc. */
1577 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
1578 i
.op
[0].disps
->X_op
= O_symbol
;
1581 if ((i
.tm
.opcode_modifier
& Rex64
) != 0)
1582 i
.rex
|= REX_MODE64
;
1584 /* For 8 bit registers we need an empty rex prefix. Also if the
1585 instruction already has a prefix, we need to convert old
1586 registers to new ones. */
1588 if (((i
.types
[0] & Reg8
) != 0
1589 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
1590 || ((i
.types
[1] & Reg8
) != 0
1591 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
1592 || (((i
.types
[0] & Reg8
) != 0 || (i
.types
[1] & Reg8
) != 0)
1597 i
.rex
|= REX_OPCODE
;
1598 for (x
= 0; x
< 2; x
++)
1600 /* Look for 8 bit operand that uses old registers. */
1601 if ((i
.types
[x
] & Reg8
) != 0
1602 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
1604 /* In case it is "hi" register, give up. */
1605 if (i
.op
[x
].regs
->reg_num
> 3)
1606 as_bad (_("can't encode register '%%%s' in an instruction requiring REX prefix."),
1607 i
.op
[x
].regs
->reg_name
);
1609 /* Otherwise it is equivalent to the extended register.
1610 Since the encoding doesn't change this is merely
1611 cosmetic cleanup for debug output. */
1613 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
1619 add_prefix (REX_OPCODE
| i
.rex
);
1621 /* We are ready to output the insn. */
1626 parse_insn (line
, mnemonic
)
1631 char *token_start
= l
;
1636 /* Non-zero if we found a prefix only acceptable with string insns. */
1637 const char *expecting_string_instruction
= NULL
;
1642 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
1645 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
1647 as_bad (_("no such instruction: `%s'"), token_start
);
1652 if (!is_space_char (*l
)
1653 && *l
!= END_OF_INSN
1655 || (*l
!= PREFIX_SEPARATOR
1658 as_bad (_("invalid character %s in mnemonic"),
1659 output_invalid (*l
));
1662 if (token_start
== l
)
1664 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
1665 as_bad (_("expecting prefix; got nothing"));
1667 as_bad (_("expecting mnemonic; got nothing"));
1671 /* Look up instruction (or prefix) via hash table. */
1672 current_templates
= hash_find (op_hash
, mnemonic
);
1674 if (*l
!= END_OF_INSN
1675 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
1676 && current_templates
1677 && (current_templates
->start
->opcode_modifier
& IsPrefix
))
1679 if (current_templates
->start
->cpu_flags
1680 & (flag_code
!= CODE_64BIT
? Cpu64
: CpuNo64
))
1682 as_bad ((flag_code
!= CODE_64BIT
1683 ? _("`%s' is only supported in 64-bit mode")
1684 : _("`%s' is not supported in 64-bit mode")),
1685 current_templates
->start
->name
);
1688 /* If we are in 16-bit mode, do not allow addr16 or data16.
1689 Similarly, in 32-bit mode, do not allow addr32 or data32. */
1690 if ((current_templates
->start
->opcode_modifier
& (Size16
| Size32
))
1691 && flag_code
!= CODE_64BIT
1692 && (((current_templates
->start
->opcode_modifier
& Size32
) != 0)
1693 ^ (flag_code
== CODE_16BIT
)))
1695 as_bad (_("redundant %s prefix"),
1696 current_templates
->start
->name
);
1699 /* Add prefix, checking for repeated prefixes. */
1700 switch (add_prefix (current_templates
->start
->base_opcode
))
1705 expecting_string_instruction
= current_templates
->start
->name
;
1708 /* Skip past PREFIX_SEPARATOR and reset token_start. */
1715 if (!current_templates
)
1717 /* See if we can get a match by trimming off a suffix. */
1720 case WORD_MNEM_SUFFIX
:
1721 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
1722 i
.suffix
= SHORT_MNEM_SUFFIX
;
1724 case BYTE_MNEM_SUFFIX
:
1725 case QWORD_MNEM_SUFFIX
:
1726 i
.suffix
= mnem_p
[-1];
1728 current_templates
= hash_find (op_hash
, mnemonic
);
1730 case SHORT_MNEM_SUFFIX
:
1731 case LONG_MNEM_SUFFIX
:
1734 i
.suffix
= mnem_p
[-1];
1736 current_templates
= hash_find (op_hash
, mnemonic
);
1744 if (intel_float_operand (mnemonic
) == 1)
1745 i
.suffix
= SHORT_MNEM_SUFFIX
;
1747 i
.suffix
= LONG_MNEM_SUFFIX
;
1749 current_templates
= hash_find (op_hash
, mnemonic
);
1753 if (!current_templates
)
1755 as_bad (_("no such instruction: `%s'"), token_start
);
1760 if (current_templates
->start
->opcode_modifier
& (Jump
| JumpByte
))
1762 /* Check for a branch hint. We allow ",pt" and ",pn" for
1763 predict taken and predict not taken respectively.
1764 I'm not sure that branch hints actually do anything on loop
1765 and jcxz insns (JumpByte) for current Pentium4 chips. They
1766 may work in the future and it doesn't hurt to accept them
1768 if (l
[0] == ',' && l
[1] == 'p')
1772 if (!add_prefix (DS_PREFIX_OPCODE
))
1776 else if (l
[2] == 'n')
1778 if (!add_prefix (CS_PREFIX_OPCODE
))
1784 /* Any other comma loses. */
1787 as_bad (_("invalid character %s in mnemonic"),
1788 output_invalid (*l
));
1792 /* Check if instruction is supported on specified architecture. */
1794 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
1796 if (!((t
->cpu_flags
& ~(Cpu64
| CpuNo64
))
1797 & ~(cpu_arch_flags
& ~(Cpu64
| CpuNo64
))))
1799 if (!(t
->cpu_flags
& (flag_code
== CODE_64BIT
? CpuNo64
: Cpu64
)))
1802 if (!(supported
& 2))
1804 as_bad (flag_code
== CODE_64BIT
1805 ? _("`%s' is not supported in 64-bit mode")
1806 : _("`%s' is only supported in 64-bit mode"),
1807 current_templates
->start
->name
);
1810 if (!(supported
& 1))
1812 as_warn (_("`%s' is not supported on `%s%s'"),
1813 current_templates
->start
->name
,
1815 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
1817 else if ((Cpu386
& ~cpu_arch_flags
) && (flag_code
!= CODE_16BIT
))
1819 as_warn (_("use .code16 to ensure correct addressing mode"));
1822 /* Check for rep/repne without a string instruction. */
1823 if (expecting_string_instruction
)
1825 static templates override
;
1827 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
1828 if (t
->opcode_modifier
& IsString
)
1830 if (t
>= current_templates
->end
)
1832 as_bad (_("expecting string instruction after `%s'"),
1833 expecting_string_instruction
);
1836 for (override
.start
= t
; t
< current_templates
->end
; ++t
)
1837 if (!(t
->opcode_modifier
& IsString
))
1840 current_templates
= &override
;
1847 parse_operands (l
, mnemonic
)
1849 const char *mnemonic
;
1853 /* 1 if operand is pending after ','. */
1854 unsigned int expecting_operand
= 0;
1856 /* Non-zero if operand parens not balanced. */
1857 unsigned int paren_not_balanced
;
1859 while (*l
!= END_OF_INSN
)
1861 /* Skip optional white space before operand. */
1862 if (is_space_char (*l
))
1864 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
)
1866 as_bad (_("invalid character %s before operand %d"),
1867 output_invalid (*l
),
1871 token_start
= l
; /* after white space */
1872 paren_not_balanced
= 0;
1873 while (paren_not_balanced
|| *l
!= ',')
1875 if (*l
== END_OF_INSN
)
1877 if (paren_not_balanced
)
1880 as_bad (_("unbalanced parenthesis in operand %d."),
1883 as_bad (_("unbalanced brackets in operand %d."),
1888 break; /* we are done */
1890 else if (!is_operand_char (*l
) && !is_space_char (*l
))
1892 as_bad (_("invalid character %s in operand %d"),
1893 output_invalid (*l
),
1900 ++paren_not_balanced
;
1902 --paren_not_balanced
;
1907 ++paren_not_balanced
;
1909 --paren_not_balanced
;
1913 if (l
!= token_start
)
1914 { /* Yes, we've read in another operand. */
1915 unsigned int operand_ok
;
1916 this_operand
= i
.operands
++;
1917 if (i
.operands
> MAX_OPERANDS
)
1919 as_bad (_("spurious operands; (%d operands/instruction max)"),
1923 /* Now parse operand adding info to 'i' as we go along. */
1924 END_STRING_AND_SAVE (l
);
1928 i386_intel_operand (token_start
,
1929 intel_float_operand (mnemonic
));
1931 operand_ok
= i386_operand (token_start
);
1933 RESTORE_END_STRING (l
);
1939 if (expecting_operand
)
1941 expecting_operand_after_comma
:
1942 as_bad (_("expecting operand after ','; got nothing"));
1947 as_bad (_("expecting operand before ','; got nothing"));
1952 /* Now *l must be either ',' or END_OF_INSN. */
1955 if (*++l
== END_OF_INSN
)
1957 /* Just skip it, if it's \n complain. */
1958 goto expecting_operand_after_comma
;
1960 expecting_operand
= 1;
1969 union i386_op temp_op
;
1970 unsigned int temp_type
;
1971 enum bfd_reloc_code_real temp_reloc
;
1975 if (i
.operands
== 2)
1980 else if (i
.operands
== 3)
1985 temp_type
= i
.types
[xchg2
];
1986 i
.types
[xchg2
] = i
.types
[xchg1
];
1987 i
.types
[xchg1
] = temp_type
;
1988 temp_op
= i
.op
[xchg2
];
1989 i
.op
[xchg2
] = i
.op
[xchg1
];
1990 i
.op
[xchg1
] = temp_op
;
1991 temp_reloc
= i
.reloc
[xchg2
];
1992 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
1993 i
.reloc
[xchg1
] = temp_reloc
;
1995 if (i
.mem_operands
== 2)
1997 const seg_entry
*temp_seg
;
1998 temp_seg
= i
.seg
[0];
1999 i
.seg
[0] = i
.seg
[1];
2000 i
.seg
[1] = temp_seg
;
2004 /* Try to ensure constant immediates are represented in the smallest
2009 char guess_suffix
= 0;
2013 guess_suffix
= i
.suffix
;
2014 else if (i
.reg_operands
)
2016 /* Figure out a suffix from the last register operand specified.
2017 We can't do this properly yet, ie. excluding InOutPortReg,
2018 but the following works for instructions with immediates.
2019 In any case, we can't set i.suffix yet. */
2020 for (op
= i
.operands
; --op
>= 0;)
2021 if (i
.types
[op
] & Reg
)
2023 if (i
.types
[op
] & Reg8
)
2024 guess_suffix
= BYTE_MNEM_SUFFIX
;
2025 else if (i
.types
[op
] & Reg16
)
2026 guess_suffix
= WORD_MNEM_SUFFIX
;
2027 else if (i
.types
[op
] & Reg32
)
2028 guess_suffix
= LONG_MNEM_SUFFIX
;
2029 else if (i
.types
[op
] & Reg64
)
2030 guess_suffix
= QWORD_MNEM_SUFFIX
;
2034 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
2035 guess_suffix
= WORD_MNEM_SUFFIX
;
2037 for (op
= i
.operands
; --op
>= 0;)
2038 if (i
.types
[op
] & Imm
)
2040 switch (i
.op
[op
].imms
->X_op
)
2043 /* If a suffix is given, this operand may be shortened. */
2044 switch (guess_suffix
)
2046 case LONG_MNEM_SUFFIX
:
2047 i
.types
[op
] |= Imm32
| Imm64
;
2049 case WORD_MNEM_SUFFIX
:
2050 i
.types
[op
] |= Imm16
| Imm32S
| Imm32
| Imm64
;
2052 case BYTE_MNEM_SUFFIX
:
2053 i
.types
[op
] |= Imm16
| Imm8
| Imm8S
| Imm32S
| Imm32
| Imm64
;
2057 /* If this operand is at most 16 bits, convert it
2058 to a signed 16 bit number before trying to see
2059 whether it will fit in an even smaller size.
2060 This allows a 16-bit operand such as $0xffe0 to
2061 be recognised as within Imm8S range. */
2062 if ((i
.types
[op
] & Imm16
)
2063 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
2065 i
.op
[op
].imms
->X_add_number
=
2066 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
2068 if ((i
.types
[op
] & Imm32
)
2069 && ((i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1))
2072 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
2073 ^ ((offsetT
) 1 << 31))
2074 - ((offsetT
) 1 << 31));
2076 i
.types
[op
] |= smallest_imm_type (i
.op
[op
].imms
->X_add_number
);
2078 /* We must avoid matching of Imm32 templates when 64bit
2079 only immediate is available. */
2080 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
2081 i
.types
[op
] &= ~Imm32
;
2088 /* Symbols and expressions. */
2090 /* Convert symbolic operand to proper sizes for matching. */
2091 switch (guess_suffix
)
2093 case QWORD_MNEM_SUFFIX
:
2094 i
.types
[op
] &= Imm64
| Imm32S
;
2096 case LONG_MNEM_SUFFIX
:
2097 i
.types
[op
] &= Imm32
;
2099 case WORD_MNEM_SUFFIX
:
2100 i
.types
[op
] &= Imm16
;
2102 case BYTE_MNEM_SUFFIX
:
2103 i
.types
[op
] &= Imm8
| Imm8S
;
2111 /* Try to use the smallest displacement type too. */
2117 for (op
= i
.operands
; --op
>= 0;)
2118 if (i
.types
[op
] & Disp
)
2120 if (i
.op
[op
].disps
->X_op
== O_constant
)
2122 offsetT disp
= i
.op
[op
].disps
->X_add_number
;
2124 if ((i
.types
[op
] & Disp16
)
2125 && (disp
& ~(offsetT
) 0xffff) == 0)
2127 /* If this operand is at most 16 bits, convert
2128 to a signed 16 bit number and don't use 64bit
2130 disp
= (((disp
& 0xffff) ^ 0x8000) - 0x8000);
2131 i
.types
[op
] &= ~Disp64
;
2133 if ((i
.types
[op
] & Disp32
)
2134 && (disp
& ~(((offsetT
) 2 << 31) - 1)) == 0)
2136 /* If this operand is at most 32 bits, convert
2137 to a signed 32 bit number and don't use 64bit
2139 disp
&= (((offsetT
) 2 << 31) - 1);
2140 disp
= (disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
2141 i
.types
[op
] &= ~Disp64
;
2143 if (!disp
&& (i
.types
[op
] & BaseIndex
))
2145 i
.types
[op
] &= ~Disp
;
2149 else if (flag_code
== CODE_64BIT
)
2151 if (fits_in_signed_long (disp
))
2153 i
.types
[op
] &= ~Disp64
;
2154 i
.types
[op
] |= Disp32S
;
2156 if (fits_in_unsigned_long (disp
))
2157 i
.types
[op
] |= Disp32
;
2159 if ((i
.types
[op
] & (Disp32
| Disp32S
| Disp16
))
2160 && fits_in_signed_byte (disp
))
2161 i
.types
[op
] |= Disp8
;
2164 /* We only support 64bit displacement on constants. */
2165 i
.types
[op
] &= ~Disp64
;
2172 /* Points to template once we've found it. */
2174 unsigned int overlap0
, overlap1
, overlap2
;
2175 unsigned int found_reverse_match
;
2178 #define MATCH(overlap, given, template) \
2179 ((overlap & ~JumpAbsolute) \
2180 && (((given) & (BaseIndex | JumpAbsolute)) \
2181 == ((overlap) & (BaseIndex | JumpAbsolute))))
2183 /* If given types r0 and r1 are registers they must be of the same type
2184 unless the expected operand type register overlap is null.
2185 Note that Acc in a template matches every size of reg. */
2186 #define CONSISTENT_REGISTER_MATCH(m0, g0, t0, m1, g1, t1) \
2187 (((g0) & Reg) == 0 || ((g1) & Reg) == 0 \
2188 || ((g0) & Reg) == ((g1) & Reg) \
2189 || ((((m0) & Acc) ? Reg : (t0)) & (((m1) & Acc) ? Reg : (t1)) & Reg) == 0 )
2194 found_reverse_match
= 0;
2195 suffix_check
= (i
.suffix
== BYTE_MNEM_SUFFIX
2197 : (i
.suffix
== WORD_MNEM_SUFFIX
2199 : (i
.suffix
== SHORT_MNEM_SUFFIX
2201 : (i
.suffix
== LONG_MNEM_SUFFIX
2203 : (i
.suffix
== QWORD_MNEM_SUFFIX
2205 : (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
2206 ? No_xSuf
: 0))))));
2208 t
= current_templates
->start
;
2209 if (i
.suffix
== QWORD_MNEM_SUFFIX
2210 && flag_code
!= CODE_64BIT
2212 ? !(t
->opcode_modifier
& IgnoreSize
)
2213 && !intel_float_operand (t
->name
)
2214 : intel_float_operand (t
->name
) != 2)
2215 && (!(t
->operand_types
[0] & (RegMMX
| RegXMM
))
2216 || !(t
->operand_types
[t
->operands
> 1] & (RegMMX
| RegXMM
)))
2217 && (t
->base_opcode
!= 0x0fc7
2218 || t
->extension_opcode
!= 1 /* cmpxchg8b */))
2219 t
= current_templates
->end
;
2220 for (; t
< current_templates
->end
; t
++)
2222 /* Must have right number of operands. */
2223 if (i
.operands
!= t
->operands
)
2226 /* Check the suffix, except for some instructions in intel mode. */
2227 if ((t
->opcode_modifier
& suffix_check
)
2229 && (t
->opcode_modifier
& IgnoreSize
)))
2232 /* Do not verify operands when there are none. */
2233 else if (!t
->operands
)
2235 if (t
->cpu_flags
& ~cpu_arch_flags
)
2237 /* We've found a match; break out of loop. */
2241 overlap0
= i
.types
[0] & t
->operand_types
[0];
2242 switch (t
->operands
)
2245 if (!MATCH (overlap0
, i
.types
[0], t
->operand_types
[0]))
2250 overlap1
= i
.types
[1] & t
->operand_types
[1];
2251 if (!MATCH (overlap0
, i
.types
[0], t
->operand_types
[0])
2252 || !MATCH (overlap1
, i
.types
[1], t
->operand_types
[1])
2253 || !CONSISTENT_REGISTER_MATCH (overlap0
, i
.types
[0],
2254 t
->operand_types
[0],
2255 overlap1
, i
.types
[1],
2256 t
->operand_types
[1]))
2258 /* Check if other direction is valid ... */
2259 if ((t
->opcode_modifier
& (D
| FloatD
)) == 0)
2262 /* Try reversing direction of operands. */
2263 overlap0
= i
.types
[0] & t
->operand_types
[1];
2264 overlap1
= i
.types
[1] & t
->operand_types
[0];
2265 if (!MATCH (overlap0
, i
.types
[0], t
->operand_types
[1])
2266 || !MATCH (overlap1
, i
.types
[1], t
->operand_types
[0])
2267 || !CONSISTENT_REGISTER_MATCH (overlap0
, i
.types
[0],
2268 t
->operand_types
[1],
2269 overlap1
, i
.types
[1],
2270 t
->operand_types
[0]))
2272 /* Does not match either direction. */
2275 /* found_reverse_match holds which of D or FloatDR
2277 found_reverse_match
= t
->opcode_modifier
& (D
| FloatDR
);
2279 /* Found a forward 2 operand match here. */
2280 else if (t
->operands
== 3)
2282 /* Here we make use of the fact that there are no
2283 reverse match 3 operand instructions, and all 3
2284 operand instructions only need to be checked for
2285 register consistency between operands 2 and 3. */
2286 overlap2
= i
.types
[2] & t
->operand_types
[2];
2287 if (!MATCH (overlap2
, i
.types
[2], t
->operand_types
[2])
2288 || !CONSISTENT_REGISTER_MATCH (overlap1
, i
.types
[1],
2289 t
->operand_types
[1],
2290 overlap2
, i
.types
[2],
2291 t
->operand_types
[2]))
2295 /* Found either forward/reverse 2 or 3 operand match here:
2296 slip through to break. */
2298 if (t
->cpu_flags
& ~cpu_arch_flags
)
2300 found_reverse_match
= 0;
2303 /* We've found a match; break out of loop. */
2307 if (t
== current_templates
->end
)
2309 /* We found no match. */
2310 as_bad (_("suffix or operands invalid for `%s'"),
2311 current_templates
->start
->name
);
2315 if (!quiet_warnings
)
2318 && ((i
.types
[0] & JumpAbsolute
)
2319 != (t
->operand_types
[0] & JumpAbsolute
)))
2321 as_warn (_("indirect %s without `*'"), t
->name
);
2324 if ((t
->opcode_modifier
& (IsPrefix
| IgnoreSize
))
2325 == (IsPrefix
| IgnoreSize
))
2327 /* Warn them that a data or address size prefix doesn't
2328 affect assembly of the next line of code. */
2329 as_warn (_("stand-alone `%s' prefix"), t
->name
);
2333 /* Copy the template we found. */
2335 if (found_reverse_match
)
2337 /* If we found a reverse match we must alter the opcode
2338 direction bit. found_reverse_match holds bits to change
2339 (different for int & float insns). */
2341 i
.tm
.base_opcode
^= found_reverse_match
;
2343 i
.tm
.operand_types
[0] = t
->operand_types
[1];
2344 i
.tm
.operand_types
[1] = t
->operand_types
[0];
2353 int mem_op
= (i
.types
[0] & AnyMem
) ? 0 : 1;
2354 if ((i
.tm
.operand_types
[mem_op
] & EsSeg
) != 0)
2356 if (i
.seg
[0] != NULL
&& i
.seg
[0] != &es
)
2358 as_bad (_("`%s' operand %d must use `%%es' segment"),
2363 /* There's only ever one segment override allowed per instruction.
2364 This instruction possibly has a legal segment override on the
2365 second operand, so copy the segment to where non-string
2366 instructions store it, allowing common code. */
2367 i
.seg
[0] = i
.seg
[1];
2369 else if ((i
.tm
.operand_types
[mem_op
+ 1] & EsSeg
) != 0)
2371 if (i
.seg
[1] != NULL
&& i
.seg
[1] != &es
)
2373 as_bad (_("`%s' operand %d must use `%%es' segment"),
2383 process_suffix (void)
2385 /* If matched instruction specifies an explicit instruction mnemonic
2387 if (i
.tm
.opcode_modifier
& (Size16
| Size32
| Size64
))
2389 if (i
.tm
.opcode_modifier
& Size16
)
2390 i
.suffix
= WORD_MNEM_SUFFIX
;
2391 else if (i
.tm
.opcode_modifier
& Size64
)
2392 i
.suffix
= QWORD_MNEM_SUFFIX
;
2394 i
.suffix
= LONG_MNEM_SUFFIX
;
2396 else if (i
.reg_operands
)
2398 /* If there's no instruction mnemonic suffix we try to invent one
2399 based on register operands. */
2402 /* We take i.suffix from the last register operand specified,
2403 Destination register type is more significant than source
2407 for (op
= i
.operands
; --op
>= 0;)
2408 if ((i
.types
[op
] & Reg
)
2409 && !(i
.tm
.operand_types
[op
] & InOutPortReg
))
2411 i
.suffix
= ((i
.types
[op
] & Reg8
) ? BYTE_MNEM_SUFFIX
:
2412 (i
.types
[op
] & Reg16
) ? WORD_MNEM_SUFFIX
:
2413 (i
.types
[op
] & Reg64
) ? QWORD_MNEM_SUFFIX
:
2418 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
2420 if (!check_byte_reg ())
2423 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
2425 if (!check_long_reg ())
2428 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
2430 if (!check_qword_reg ())
2433 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
2435 if (!check_word_reg ())
2438 else if (intel_syntax
&& (i
.tm
.opcode_modifier
& IgnoreSize
))
2439 /* Do nothing if the instruction is going to ignore the prefix. */
2444 else if ((i
.tm
.opcode_modifier
& DefaultSize
)
2446 /* exclude fldenv/frstor/fsave/fstenv */
2447 && (i
.tm
.opcode_modifier
& No_sSuf
))
2449 i
.suffix
= stackop_size
;
2451 else if (intel_syntax
2453 && ((i
.tm
.operand_types
[0] & JumpAbsolute
)
2454 || (i
.tm
.opcode_modifier
& (JumpByte
|JumpInterSegment
))
2455 || (i
.tm
.base_opcode
== 0x0f01 /* [ls][gi]dt */
2456 && i
.tm
.extension_opcode
<= 3)))
2461 if (!(i
.tm
.opcode_modifier
& No_qSuf
))
2463 i
.suffix
= QWORD_MNEM_SUFFIX
;
2467 if (!(i
.tm
.opcode_modifier
& No_lSuf
))
2468 i
.suffix
= LONG_MNEM_SUFFIX
;
2471 if (!(i
.tm
.opcode_modifier
& No_wSuf
))
2472 i
.suffix
= WORD_MNEM_SUFFIX
;
2481 if (i
.tm
.opcode_modifier
& W
)
2483 as_bad (_("no instruction mnemonic suffix given and no register operands; can't size instruction"));
2489 unsigned int suffixes
= ~i
.tm
.opcode_modifier
2497 if ((i
.tm
.opcode_modifier
& W
)
2498 || ((suffixes
& (suffixes
- 1))
2499 && !(i
.tm
.opcode_modifier
& (DefaultSize
| IgnoreSize
))))
2501 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
2507 /* Change the opcode based on the operand size given by i.suffix;
2508 We don't need to change things for byte insns. */
2510 if (i
.suffix
&& i
.suffix
!= BYTE_MNEM_SUFFIX
)
2512 /* It's not a byte, select word/dword operation. */
2513 if (i
.tm
.opcode_modifier
& W
)
2515 if (i
.tm
.opcode_modifier
& ShortForm
)
2516 i
.tm
.base_opcode
|= 8;
2518 i
.tm
.base_opcode
|= 1;
2521 /* Now select between word & dword operations via the operand
2522 size prefix, except for instructions that will ignore this
2524 if (i
.suffix
!= QWORD_MNEM_SUFFIX
2525 && i
.suffix
!= LONG_DOUBLE_MNEM_SUFFIX
2526 && !(i
.tm
.opcode_modifier
& (IgnoreSize
| FloatMF
))
2527 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
2528 || (flag_code
== CODE_64BIT
2529 && (i
.tm
.opcode_modifier
& JumpByte
))))
2531 unsigned int prefix
= DATA_PREFIX_OPCODE
;
2533 if (i
.tm
.opcode_modifier
& JumpByte
) /* jcxz, loop */
2534 prefix
= ADDR_PREFIX_OPCODE
;
2536 if (!add_prefix (prefix
))
2540 /* Set mode64 for an operand. */
2541 if (i
.suffix
== QWORD_MNEM_SUFFIX
2542 && flag_code
== CODE_64BIT
2543 && (i
.tm
.opcode_modifier
& NoRex64
) == 0)
2544 i
.rex
|= REX_MODE64
;
2546 /* Size floating point instruction. */
2547 if (i
.suffix
== LONG_MNEM_SUFFIX
)
2548 if (i
.tm
.opcode_modifier
& FloatMF
)
2549 i
.tm
.base_opcode
^= 4;
2556 check_byte_reg (void)
2560 for (op
= i
.operands
; --op
>= 0;)
2562 /* If this is an eight bit register, it's OK. If it's the 16 or
2563 32 bit version of an eight bit register, we will just use the
2564 low portion, and that's OK too. */
2565 if (i
.types
[op
] & Reg8
)
2568 /* movzx and movsx should not generate this warning. */
2570 && (i
.tm
.base_opcode
== 0xfb7
2571 || i
.tm
.base_opcode
== 0xfb6
2572 || i
.tm
.base_opcode
== 0x63
2573 || i
.tm
.base_opcode
== 0xfbe
2574 || i
.tm
.base_opcode
== 0xfbf))
2577 if ((i
.types
[op
] & WordReg
) && i
.op
[op
].regs
->reg_num
< 4)
2579 /* Prohibit these changes in the 64bit mode, since the
2580 lowering is more complicated. */
2581 if (flag_code
== CODE_64BIT
2582 && (i
.tm
.operand_types
[op
] & InOutPortReg
) == 0)
2584 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
2585 i
.op
[op
].regs
->reg_name
,
2589 #if REGISTER_WARNINGS
2591 && (i
.tm
.operand_types
[op
] & InOutPortReg
) == 0)
2592 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2593 (i
.op
[op
].regs
+ (i
.types
[op
] & Reg16
2594 ? REGNAM_AL
- REGNAM_AX
2595 : REGNAM_AL
- REGNAM_EAX
))->reg_name
,
2596 i
.op
[op
].regs
->reg_name
,
2601 /* Any other register is bad. */
2602 if (i
.types
[op
] & (Reg
| RegMMX
| RegXMM
2604 | Control
| Debug
| Test
2605 | FloatReg
| FloatAcc
))
2607 as_bad (_("`%%%s' not allowed with `%s%c'"),
2608 i
.op
[op
].regs
->reg_name
,
2622 for (op
= i
.operands
; --op
>= 0;)
2623 /* Reject eight bit registers, except where the template requires
2624 them. (eg. movzb) */
2625 if ((i
.types
[op
] & Reg8
) != 0
2626 && (i
.tm
.operand_types
[op
] & (Reg16
| Reg32
| Acc
)) != 0)
2628 as_bad (_("`%%%s' not allowed with `%s%c'"),
2629 i
.op
[op
].regs
->reg_name
,
2634 /* Warn if the e prefix on a general reg is missing. */
2635 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
2636 && (i
.types
[op
] & Reg16
) != 0
2637 && (i
.tm
.operand_types
[op
] & (Reg32
| Acc
)) != 0)
2639 /* Prohibit these changes in the 64bit mode, since the
2640 lowering is more complicated. */
2641 if (flag_code
== CODE_64BIT
)
2643 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
2644 i
.op
[op
].regs
->reg_name
,
2648 #if REGISTER_WARNINGS
2650 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2651 (i
.op
[op
].regs
+ REGNAM_EAX
- REGNAM_AX
)->reg_name
,
2652 i
.op
[op
].regs
->reg_name
,
2656 /* Warn if the r prefix on a general reg is missing. */
2657 else if ((i
.types
[op
] & Reg64
) != 0
2658 && (i
.tm
.operand_types
[op
] & (Reg32
| Acc
)) != 0)
2660 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
2661 i
.op
[op
].regs
->reg_name
,
2673 for (op
= i
.operands
; --op
>= 0; )
2674 /* Reject eight bit registers, except where the template requires
2675 them. (eg. movzb) */
2676 if ((i
.types
[op
] & Reg8
) != 0
2677 && (i
.tm
.operand_types
[op
] & (Reg16
| Reg32
| Acc
)) != 0)
2679 as_bad (_("`%%%s' not allowed with `%s%c'"),
2680 i
.op
[op
].regs
->reg_name
,
2685 /* Warn if the e prefix on a general reg is missing. */
2686 else if (((i
.types
[op
] & Reg16
) != 0
2687 || (i
.types
[op
] & Reg32
) != 0)
2688 && (i
.tm
.operand_types
[op
] & (Reg32
| Acc
)) != 0)
2690 /* Prohibit these changes in the 64bit mode, since the
2691 lowering is more complicated. */
2692 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
2693 i
.op
[op
].regs
->reg_name
,
2704 for (op
= i
.operands
; --op
>= 0;)
2705 /* Reject eight bit registers, except where the template requires
2706 them. (eg. movzb) */
2707 if ((i
.types
[op
] & Reg8
) != 0
2708 && (i
.tm
.operand_types
[op
] & (Reg16
| Reg32
| Acc
)) != 0)
2710 as_bad (_("`%%%s' not allowed with `%s%c'"),
2711 i
.op
[op
].regs
->reg_name
,
2716 /* Warn if the e prefix on a general reg is present. */
2717 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
2718 && (i
.types
[op
] & Reg32
) != 0
2719 && (i
.tm
.operand_types
[op
] & (Reg16
| Acc
)) != 0)
2721 /* Prohibit these changes in the 64bit mode, since the
2722 lowering is more complicated. */
2723 if (flag_code
== CODE_64BIT
)
2725 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
2726 i
.op
[op
].regs
->reg_name
,
2731 #if REGISTER_WARNINGS
2732 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2733 (i
.op
[op
].regs
+ REGNAM_AX
- REGNAM_EAX
)->reg_name
,
2734 i
.op
[op
].regs
->reg_name
,
2744 unsigned int overlap0
, overlap1
, overlap2
;
2746 overlap0
= i
.types
[0] & i
.tm
.operand_types
[0];
2747 if ((overlap0
& (Imm8
| Imm8S
| Imm16
| Imm32
| Imm32S
| Imm64
))
2748 && overlap0
!= Imm8
&& overlap0
!= Imm8S
2749 && overlap0
!= Imm16
&& overlap0
!= Imm32S
2750 && overlap0
!= Imm32
&& overlap0
!= Imm64
)
2754 overlap0
&= (i
.suffix
== BYTE_MNEM_SUFFIX
2756 : (i
.suffix
== WORD_MNEM_SUFFIX
2758 : (i
.suffix
== QWORD_MNEM_SUFFIX
2762 else if (overlap0
== (Imm16
| Imm32S
| Imm32
)
2763 || overlap0
== (Imm16
| Imm32
)
2764 || overlap0
== (Imm16
| Imm32S
))
2766 overlap0
= ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0)
2769 if (overlap0
!= Imm8
&& overlap0
!= Imm8S
2770 && overlap0
!= Imm16
&& overlap0
!= Imm32S
2771 && overlap0
!= Imm32
&& overlap0
!= Imm64
)
2773 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size"));
2777 i
.types
[0] = overlap0
;
2779 overlap1
= i
.types
[1] & i
.tm
.operand_types
[1];
2780 if ((overlap1
& (Imm8
| Imm8S
| Imm16
| Imm32S
| Imm32
| Imm64
))
2781 && overlap1
!= Imm8
&& overlap1
!= Imm8S
2782 && overlap1
!= Imm16
&& overlap1
!= Imm32S
2783 && overlap1
!= Imm32
&& overlap1
!= Imm64
)
2787 overlap1
&= (i
.suffix
== BYTE_MNEM_SUFFIX
2789 : (i
.suffix
== WORD_MNEM_SUFFIX
2791 : (i
.suffix
== QWORD_MNEM_SUFFIX
2795 else if (overlap1
== (Imm16
| Imm32
| Imm32S
)
2796 || overlap1
== (Imm16
| Imm32
)
2797 || overlap1
== (Imm16
| Imm32S
))
2799 overlap1
= ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0)
2802 if (overlap1
!= Imm8
&& overlap1
!= Imm8S
2803 && overlap1
!= Imm16
&& overlap1
!= Imm32S
2804 && overlap1
!= Imm32
&& overlap1
!= Imm64
)
2806 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size %x %c"),overlap1
, i
.suffix
);
2810 i
.types
[1] = overlap1
;
2812 overlap2
= i
.types
[2] & i
.tm
.operand_types
[2];
2813 assert ((overlap2
& Imm
) == 0);
2814 i
.types
[2] = overlap2
;
2822 /* Default segment register this instruction will use for memory
2823 accesses. 0 means unknown. This is only for optimizing out
2824 unnecessary segment overrides. */
2825 const seg_entry
*default_seg
= 0;
2827 /* The imul $imm, %reg instruction is converted into
2828 imul $imm, %reg, %reg, and the clr %reg instruction
2829 is converted into xor %reg, %reg. */
2830 if (i
.tm
.opcode_modifier
& regKludge
)
2832 unsigned int first_reg_op
= (i
.types
[0] & Reg
) ? 0 : 1;
2833 /* Pretend we saw the extra register operand. */
2834 assert (i
.op
[first_reg_op
+ 1].regs
== 0);
2835 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
2836 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
2840 if (i
.tm
.opcode_modifier
& ShortForm
)
2842 /* The register or float register operand is in operand 0 or 1. */
2843 unsigned int op
= (i
.types
[0] & (Reg
| FloatReg
)) ? 0 : 1;
2844 /* Register goes in low 3 bits of opcode. */
2845 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
2846 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
2848 if (!quiet_warnings
&& (i
.tm
.opcode_modifier
& Ugh
) != 0)
2850 /* Warn about some common errors, but press on regardless.
2851 The first case can be generated by gcc (<= 2.8.1). */
2852 if (i
.operands
== 2)
2854 /* Reversed arguments on faddp, fsubp, etc. */
2855 as_warn (_("translating to `%s %%%s,%%%s'"), i
.tm
.name
,
2856 i
.op
[1].regs
->reg_name
,
2857 i
.op
[0].regs
->reg_name
);
2861 /* Extraneous `l' suffix on fp insn. */
2862 as_warn (_("translating to `%s %%%s'"), i
.tm
.name
,
2863 i
.op
[0].regs
->reg_name
);
2867 else if (i
.tm
.opcode_modifier
& Modrm
)
2869 /* The opcode is completed (modulo i.tm.extension_opcode which
2870 must be put into the modrm byte). Now, we make the modrm and
2871 index base bytes based on all the info we've collected. */
2873 default_seg
= build_modrm_byte ();
2875 else if (i
.tm
.opcode_modifier
& (Seg2ShortForm
| Seg3ShortForm
))
2877 if (i
.tm
.base_opcode
== POP_SEG_SHORT
2878 && i
.op
[0].regs
->reg_num
== 1)
2880 as_bad (_("you can't `pop %%cs'"));
2883 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
2884 if ((i
.op
[0].regs
->reg_flags
& RegRex
) != 0)
2887 else if ((i
.tm
.base_opcode
& ~(D
| W
)) == MOV_AX_DISP32
)
2891 else if ((i
.tm
.opcode_modifier
& IsString
) != 0)
2893 /* For the string instructions that allow a segment override
2894 on one of their operands, the default segment is ds. */
2898 if ((i
.tm
.base_opcode
== 0x8d /* lea */
2899 || (i
.tm
.cpu_flags
& CpuSVME
))
2900 && i
.seg
[0] && !quiet_warnings
)
2901 as_warn (_("segment override on `%s' is ineffectual"), i
.tm
.name
);
2903 /* If a segment was explicitly specified, and the specified segment
2904 is not the default, use an opcode prefix to select it. If we
2905 never figured out what the default segment is, then default_seg
2906 will be zero at this point, and the specified segment prefix will
2908 if ((i
.seg
[0]) && (i
.seg
[0] != default_seg
))
2910 if (!add_prefix (i
.seg
[0]->seg_prefix
))
2916 static const seg_entry
*
2919 const seg_entry
*default_seg
= 0;
2921 /* i.reg_operands MUST be the number of real register operands;
2922 implicit registers do not count. */
2923 if (i
.reg_operands
== 2)
2925 unsigned int source
, dest
;
2926 source
= ((i
.types
[0]
2927 & (Reg
| RegMMX
| RegXMM
2929 | Control
| Debug
| Test
))
2934 /* One of the register operands will be encoded in the i.tm.reg
2935 field, the other in the combined i.tm.mode and i.tm.regmem
2936 fields. If no form of this instruction supports a memory
2937 destination operand, then we assume the source operand may
2938 sometimes be a memory operand and so we need to store the
2939 destination in the i.rm.reg field. */
2940 if ((i
.tm
.operand_types
[dest
] & AnyMem
) == 0)
2942 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
2943 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
2944 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
2946 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
2951 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
2952 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
2953 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
2955 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
2958 if (flag_code
!= CODE_64BIT
&& (i
.rex
& (REX_EXTX
| REX_EXTZ
)))
2960 if (!((i
.types
[0] | i
.types
[1]) & Control
))
2962 i
.rex
&= ~(REX_EXTX
| REX_EXTZ
);
2963 add_prefix (LOCK_PREFIX_OPCODE
);
2967 { /* If it's not 2 reg operands... */
2970 unsigned int fake_zero_displacement
= 0;
2971 unsigned int op
= ((i
.types
[0] & AnyMem
)
2973 : (i
.types
[1] & AnyMem
) ? 1 : 2);
2977 if (i
.base_reg
== 0)
2980 if (!i
.disp_operands
)
2981 fake_zero_displacement
= 1;
2982 if (i
.index_reg
== 0)
2984 /* Operand is just <disp> */
2985 if (flag_code
== CODE_64BIT
)
2987 /* 64bit mode overwrites the 32bit absolute
2988 addressing by RIP relative addressing and
2989 absolute addressing is encoded by one of the
2990 redundant SIB forms. */
2991 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
2992 i
.sib
.base
= NO_BASE_REGISTER
;
2993 i
.sib
.index
= NO_INDEX_REGISTER
;
2994 i
.types
[op
] = ((i
.prefix
[ADDR_PREFIX
] == 0) ? Disp32S
: Disp32
);
2996 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[ADDR_PREFIX
] != 0))
2998 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
2999 i
.types
[op
] = Disp16
;
3003 i
.rm
.regmem
= NO_BASE_REGISTER
;
3004 i
.types
[op
] = Disp32
;
3007 else /* !i.base_reg && i.index_reg */
3009 i
.sib
.index
= i
.index_reg
->reg_num
;
3010 i
.sib
.base
= NO_BASE_REGISTER
;
3011 i
.sib
.scale
= i
.log2_scale_factor
;
3012 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
3013 i
.types
[op
] &= ~Disp
;
3014 if (flag_code
!= CODE_64BIT
)
3015 i
.types
[op
] |= Disp32
; /* Must be 32 bit */
3017 i
.types
[op
] |= Disp32S
;
3018 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
3022 /* RIP addressing for 64bit mode. */
3023 else if (i
.base_reg
->reg_type
== BaseIndex
)
3025 i
.rm
.regmem
= NO_BASE_REGISTER
;
3026 i
.types
[op
] &= ~ Disp
;
3027 i
.types
[op
] |= Disp32S
;
3028 i
.flags
[op
] = Operand_PCrel
;
3029 if (! i
.disp_operands
)
3030 fake_zero_displacement
= 1;
3032 else if (i
.base_reg
->reg_type
& Reg16
)
3034 switch (i
.base_reg
->reg_num
)
3037 if (i
.index_reg
== 0)
3039 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
3040 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
3044 if (i
.index_reg
== 0)
3047 if ((i
.types
[op
] & Disp
) == 0)
3049 /* fake (%bp) into 0(%bp) */
3050 i
.types
[op
] |= Disp8
;
3051 fake_zero_displacement
= 1;
3054 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
3055 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
3057 default: /* (%si) -> 4 or (%di) -> 5 */
3058 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
3060 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
3062 else /* i.base_reg and 32/64 bit mode */
3064 if (flag_code
== CODE_64BIT
3065 && (i
.types
[op
] & Disp
))
3066 i
.types
[op
] = (i
.types
[op
] & Disp8
) | (i
.prefix
[ADDR_PREFIX
] == 0 ? Disp32S
: Disp32
);
3068 i
.rm
.regmem
= i
.base_reg
->reg_num
;
3069 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
3071 i
.sib
.base
= i
.base_reg
->reg_num
;
3072 /* x86-64 ignores REX prefix bit here to avoid decoder
3074 if ((i
.base_reg
->reg_num
& 7) == EBP_REG_NUM
)
3077 if (i
.disp_operands
== 0)
3079 fake_zero_displacement
= 1;
3080 i
.types
[op
] |= Disp8
;
3083 else if (i
.base_reg
->reg_num
== ESP_REG_NUM
)
3087 i
.sib
.scale
= i
.log2_scale_factor
;
3088 if (i
.index_reg
== 0)
3090 /* <disp>(%esp) becomes two byte modrm with no index
3091 register. We've already stored the code for esp
3092 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
3093 Any base register besides %esp will not use the
3094 extra modrm byte. */
3095 i
.sib
.index
= NO_INDEX_REGISTER
;
3096 #if !SCALE1_WHEN_NO_INDEX
3097 /* Another case where we force the second modrm byte. */
3098 if (i
.log2_scale_factor
)
3099 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
3104 i
.sib
.index
= i
.index_reg
->reg_num
;
3105 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
3106 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
3109 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
3112 if (fake_zero_displacement
)
3114 /* Fakes a zero displacement assuming that i.types[op]
3115 holds the correct displacement size. */
3118 assert (i
.op
[op
].disps
== 0);
3119 exp
= &disp_expressions
[i
.disp_operands
++];
3120 i
.op
[op
].disps
= exp
;
3121 exp
->X_op
= O_constant
;
3122 exp
->X_add_number
= 0;
3123 exp
->X_add_symbol
= (symbolS
*) 0;
3124 exp
->X_op_symbol
= (symbolS
*) 0;
3128 /* Fill in i.rm.reg or i.rm.regmem field with register operand
3129 (if any) based on i.tm.extension_opcode. Again, we must be
3130 careful to make sure that segment/control/debug/test/MMX
3131 registers are coded into the i.rm.reg field. */
3136 & (Reg
| RegMMX
| RegXMM
3138 | Control
| Debug
| Test
))
3141 & (Reg
| RegMMX
| RegXMM
3143 | Control
| Debug
| Test
))
3146 /* If there is an extension opcode to put here, the register
3147 number must be put into the regmem field. */
3148 if (i
.tm
.extension_opcode
!= None
)
3150 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
3151 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
3156 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
3157 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
3161 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
3162 must set it to 3 to indicate this is a register operand
3163 in the regmem field. */
3164 if (!i
.mem_operands
)
3168 /* Fill in i.rm.reg field with extension opcode (if any). */
3169 if (i
.tm
.extension_opcode
!= None
)
3170 i
.rm
.reg
= i
.tm
.extension_opcode
;
3181 relax_substateT subtype
;
3186 if (flag_code
== CODE_16BIT
)
3190 if (i
.prefix
[DATA_PREFIX
] != 0)
3196 /* Pentium4 branch hints. */
3197 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
3198 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
3203 if (i
.prefix
[REX_PREFIX
] != 0)
3209 if (i
.prefixes
!= 0 && !intel_syntax
)
3210 as_warn (_("skipping prefixes on this instruction"));
3212 /* It's always a symbol; End frag & setup for relax.
3213 Make sure there is enough room in this frag for the largest
3214 instruction we may generate in md_convert_frag. This is 2
3215 bytes for the opcode and room for the prefix and largest
3217 frag_grow (prefix
+ 2 + 4);
3218 /* Prefix and 1 opcode byte go in fr_fix. */
3219 p
= frag_more (prefix
+ 1);
3220 if (i
.prefix
[DATA_PREFIX
] != 0)
3221 *p
++ = DATA_PREFIX_OPCODE
;
3222 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
3223 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
3224 *p
++ = i
.prefix
[SEG_PREFIX
];
3225 if (i
.prefix
[REX_PREFIX
] != 0)
3226 *p
++ = i
.prefix
[REX_PREFIX
];
3227 *p
= i
.tm
.base_opcode
;
3229 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
3230 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, SMALL
);
3231 else if ((cpu_arch_flags
& Cpu386
) != 0)
3232 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, SMALL
);
3234 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, SMALL
);
3237 sym
= i
.op
[0].disps
->X_add_symbol
;
3238 off
= i
.op
[0].disps
->X_add_number
;
3240 if (i
.op
[0].disps
->X_op
!= O_constant
3241 && i
.op
[0].disps
->X_op
!= O_symbol
)
3243 /* Handle complex expressions. */
3244 sym
= make_expr_symbol (i
.op
[0].disps
);
3248 /* 1 possible extra opcode + 4 byte displacement go in var part.
3249 Pass reloc in fr_var. */
3250 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
3260 if (i
.tm
.opcode_modifier
& JumpByte
)
3262 /* This is a loop or jecxz type instruction. */
3264 if (i
.prefix
[ADDR_PREFIX
] != 0)
3266 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
3269 /* Pentium4 branch hints. */
3270 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
3271 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
3273 FRAG_APPEND_1_CHAR (i
.prefix
[SEG_PREFIX
]);
3282 if (flag_code
== CODE_16BIT
)
3285 if (i
.prefix
[DATA_PREFIX
] != 0)
3287 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
3297 if (i
.prefix
[REX_PREFIX
] != 0)
3299 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
3303 if (i
.prefixes
!= 0 && !intel_syntax
)
3304 as_warn (_("skipping prefixes on this instruction"));
3306 p
= frag_more (1 + size
);
3307 *p
++ = i
.tm
.base_opcode
;
3309 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
3310 i
.op
[0].disps
, 1, reloc (size
, 1, 1, i
.reloc
[0]));
3312 /* All jumps handled here are signed, but don't use a signed limit
3313 check for 32 and 16 bit jumps as we want to allow wrap around at
3314 4G and 64k respectively. */
3316 fixP
->fx_signed
= 1;
3320 output_interseg_jump ()
3328 if (flag_code
== CODE_16BIT
)
3332 if (i
.prefix
[DATA_PREFIX
] != 0)
3338 if (i
.prefix
[REX_PREFIX
] != 0)
3348 if (i
.prefixes
!= 0 && !intel_syntax
)
3349 as_warn (_("skipping prefixes on this instruction"));
3351 /* 1 opcode; 2 segment; offset */
3352 p
= frag_more (prefix
+ 1 + 2 + size
);
3354 if (i
.prefix
[DATA_PREFIX
] != 0)
3355 *p
++ = DATA_PREFIX_OPCODE
;
3357 if (i
.prefix
[REX_PREFIX
] != 0)
3358 *p
++ = i
.prefix
[REX_PREFIX
];
3360 *p
++ = i
.tm
.base_opcode
;
3361 if (i
.op
[1].imms
->X_op
== O_constant
)
3363 offsetT n
= i
.op
[1].imms
->X_add_number
;
3366 && !fits_in_unsigned_word (n
)
3367 && !fits_in_signed_word (n
))
3369 as_bad (_("16-bit jump out of range"));
3372 md_number_to_chars (p
, n
, size
);
3375 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
3376 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
3377 if (i
.op
[0].imms
->X_op
!= O_constant
)
3378 as_bad (_("can't handle non absolute segment in `%s'"),
3380 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
3386 fragS
*insn_start_frag
;
3387 offsetT insn_start_off
;
3389 /* Tie dwarf2 debug info to the address at the start of the insn.
3390 We can't do this after the insn has been output as the current
3391 frag may have been closed off. eg. by frag_var. */
3392 dwarf2_emit_insn (0);
3394 insn_start_frag
= frag_now
;
3395 insn_start_off
= frag_now_fix ();
3398 if (i
.tm
.opcode_modifier
& Jump
)
3400 else if (i
.tm
.opcode_modifier
& (JumpByte
| JumpDword
))
3402 else if (i
.tm
.opcode_modifier
& JumpInterSegment
)
3403 output_interseg_jump ();
3406 /* Output normal instructions here. */
3410 /* All opcodes on i386 have either 1 or 2 bytes. We may use one
3411 more higher byte to specify a prefix the instruction
3413 if ((i
.tm
.base_opcode
& 0xff0000) != 0)
3415 if ((i
.tm
.cpu_flags
& CpuPadLock
) != 0)
3417 unsigned int prefix
;
3418 prefix
= (i
.tm
.base_opcode
>> 16) & 0xff;
3420 if (prefix
!= REPE_PREFIX_OPCODE
3421 || i
.prefix
[LOCKREP_PREFIX
] != REPE_PREFIX_OPCODE
)
3422 add_prefix (prefix
);
3425 add_prefix ((i
.tm
.base_opcode
>> 16) & 0xff);
3428 /* The prefix bytes. */
3430 q
< i
.prefix
+ sizeof (i
.prefix
) / sizeof (i
.prefix
[0]);
3436 md_number_to_chars (p
, (valueT
) *q
, 1);
3440 /* Now the opcode; be careful about word order here! */
3441 if (fits_in_unsigned_byte (i
.tm
.base_opcode
))
3443 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
3449 /* Put out high byte first: can't use md_number_to_chars! */
3450 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
3451 *p
= i
.tm
.base_opcode
& 0xff;
3454 /* Now the modrm byte and sib byte (if present). */
3455 if (i
.tm
.opcode_modifier
& Modrm
)
3458 md_number_to_chars (p
,
3459 (valueT
) (i
.rm
.regmem
<< 0
3463 /* If i.rm.regmem == ESP (4)
3464 && i.rm.mode != (Register mode)
3466 ==> need second modrm byte. */
3467 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
3469 && !(i
.base_reg
&& (i
.base_reg
->reg_type
& Reg16
) != 0))
3472 md_number_to_chars (p
,
3473 (valueT
) (i
.sib
.base
<< 0
3475 | i
.sib
.scale
<< 6),
3480 if (i
.disp_operands
)
3481 output_disp (insn_start_frag
, insn_start_off
);
3484 output_imm (insn_start_frag
, insn_start_off
);
3492 #endif /* DEBUG386 */
3496 output_disp (insn_start_frag
, insn_start_off
)
3497 fragS
*insn_start_frag
;
3498 offsetT insn_start_off
;
3503 for (n
= 0; n
< i
.operands
; n
++)
3505 if (i
.types
[n
] & Disp
)
3507 if (i
.op
[n
].disps
->X_op
== O_constant
)
3513 if (i
.types
[n
] & (Disp8
| Disp16
| Disp64
))
3516 if (i
.types
[n
] & Disp8
)
3518 if (i
.types
[n
] & Disp64
)
3521 val
= offset_in_range (i
.op
[n
].disps
->X_add_number
,
3523 p
= frag_more (size
);
3524 md_number_to_chars (p
, val
, size
);
3528 enum bfd_reloc_code_real reloc_type
;
3531 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
3533 /* The PC relative address is computed relative
3534 to the instruction boundary, so in case immediate
3535 fields follows, we need to adjust the value. */
3536 if (pcrel
&& i
.imm_operands
)
3541 for (n1
= 0; n1
< i
.operands
; n1
++)
3542 if (i
.types
[n1
] & Imm
)
3544 if (i
.types
[n1
] & (Imm8
| Imm8S
| Imm16
| Imm64
))
3547 if (i
.types
[n1
] & (Imm8
| Imm8S
))
3549 if (i
.types
[n1
] & Imm64
)
3554 /* We should find the immediate. */
3555 if (n1
== i
.operands
)
3557 i
.op
[n
].disps
->X_add_number
-= imm_size
;
3560 if (i
.types
[n
] & Disp32S
)
3563 if (i
.types
[n
] & (Disp16
| Disp64
))
3566 if (i
.types
[n
] & Disp64
)
3570 p
= frag_more (size
);
3571 reloc_type
= reloc (size
, pcrel
, sign
, i
.reloc
[n
]);
3573 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
3574 && (((reloc_type
== BFD_RELOC_32
3575 || reloc_type
== BFD_RELOC_X86_64_32S
)
3576 && (i
.op
[n
].disps
->X_op
== O_symbol
3577 || (i
.op
[n
].disps
->X_op
== O_add
3578 && ((symbol_get_value_expression
3579 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
3581 || reloc_type
== BFD_RELOC_32_PCREL
))
3585 if (insn_start_frag
== frag_now
)
3586 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
3591 add
= insn_start_frag
->fr_fix
- insn_start_off
;
3592 for (fr
= insn_start_frag
->fr_next
;
3593 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
3595 add
+= p
- frag_now
->fr_literal
;
3598 if (flag_code
!= CODE_64BIT
)
3599 reloc_type
= BFD_RELOC_386_GOTPC
;
3601 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
3602 i
.op
[n
].disps
->X_add_number
+= add
;
3604 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
3605 i
.op
[n
].disps
, pcrel
, reloc_type
);
3612 output_imm (insn_start_frag
, insn_start_off
)
3613 fragS
*insn_start_frag
;
3614 offsetT insn_start_off
;
3619 for (n
= 0; n
< i
.operands
; n
++)
3621 if (i
.types
[n
] & Imm
)
3623 if (i
.op
[n
].imms
->X_op
== O_constant
)
3629 if (i
.types
[n
] & (Imm8
| Imm8S
| Imm16
| Imm64
))
3632 if (i
.types
[n
] & (Imm8
| Imm8S
))
3634 else if (i
.types
[n
] & Imm64
)
3637 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
3639 p
= frag_more (size
);
3640 md_number_to_chars (p
, val
, size
);
3644 /* Not absolute_section.
3645 Need a 32-bit fixup (don't support 8bit
3646 non-absolute imms). Try to support other
3648 enum bfd_reloc_code_real reloc_type
;
3652 if ((i
.types
[n
] & (Imm32S
))
3653 && (i
.suffix
== QWORD_MNEM_SUFFIX
3654 || (!i
.suffix
&& (i
.tm
.opcode_modifier
& No_lSuf
))))
3656 if (i
.types
[n
] & (Imm8
| Imm8S
| Imm16
| Imm64
))
3659 if (i
.types
[n
] & (Imm8
| Imm8S
))
3661 if (i
.types
[n
] & Imm64
)
3665 p
= frag_more (size
);
3666 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
3668 /* This is tough to explain. We end up with this one if we
3669 * have operands that look like
3670 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
3671 * obtain the absolute address of the GOT, and it is strongly
3672 * preferable from a performance point of view to avoid using
3673 * a runtime relocation for this. The actual sequence of
3674 * instructions often look something like:
3679 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
3681 * The call and pop essentially return the absolute address
3682 * of the label .L66 and store it in %ebx. The linker itself
3683 * will ultimately change the first operand of the addl so
3684 * that %ebx points to the GOT, but to keep things simple, the
3685 * .o file must have this operand set so that it generates not
3686 * the absolute address of .L66, but the absolute address of
3687 * itself. This allows the linker itself simply treat a GOTPC
3688 * relocation as asking for a pcrel offset to the GOT to be
3689 * added in, and the addend of the relocation is stored in the
3690 * operand field for the instruction itself.
3692 * Our job here is to fix the operand so that it would add
3693 * the correct offset so that %ebx would point to itself. The
3694 * thing that is tricky is that .-.L66 will point to the
3695 * beginning of the instruction, so we need to further modify
3696 * the operand so that it will point to itself. There are
3697 * other cases where you have something like:
3699 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
3701 * and here no correction would be required. Internally in
3702 * the assembler we treat operands of this form as not being
3703 * pcrel since the '.' is explicitly mentioned, and I wonder
3704 * whether it would simplify matters to do it this way. Who
3705 * knows. In earlier versions of the PIC patches, the
3706 * pcrel_adjust field was used to store the correction, but
3707 * since the expression is not pcrel, I felt it would be
3708 * confusing to do it this way. */
3710 if ((reloc_type
== BFD_RELOC_32
3711 || reloc_type
== BFD_RELOC_X86_64_32S
)
3713 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
3714 && (i
.op
[n
].imms
->X_op
== O_symbol
3715 || (i
.op
[n
].imms
->X_op
== O_add
3716 && ((symbol_get_value_expression
3717 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
3722 if (insn_start_frag
== frag_now
)
3723 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
3728 add
= insn_start_frag
->fr_fix
- insn_start_off
;
3729 for (fr
= insn_start_frag
->fr_next
;
3730 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
3732 add
+= p
- frag_now
->fr_literal
;
3735 if (flag_code
!= CODE_64BIT
)
3736 reloc_type
= BFD_RELOC_386_GOTPC
;
3738 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
3739 i
.op
[n
].imms
->X_add_number
+= add
;
3741 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
3742 i
.op
[n
].imms
, 0, reloc_type
);
3748 #if (!defined (OBJ_ELF) && !defined (OBJ_MAYBE_ELF)) || defined (LEX_AT)
3749 # define lex_got(reloc, adjust, types) NULL
3751 /* Parse operands of the form
3752 <symbol>@GOTOFF+<nnn>
3753 and similar .plt or .got references.
3755 If we find one, set up the correct relocation in RELOC and copy the
3756 input string, minus the `@GOTOFF' into a malloc'd buffer for
3757 parsing by the calling routine. Return this buffer, and if ADJUST
3758 is non-null set it to the length of the string we removed from the
3759 input line. Otherwise return NULL. */
3761 lex_got (enum bfd_reloc_code_real
*reloc
,
3763 unsigned int *types
)
3765 static const char * const mode_name
[NUM_FLAG_CODE
] = { "32", "16", "64" };
3766 static const struct {
3768 const enum bfd_reloc_code_real rel
[NUM_FLAG_CODE
];
3769 const unsigned int types64
;
3771 { "PLT", { BFD_RELOC_386_PLT32
, 0, BFD_RELOC_X86_64_PLT32
}, Imm32
|Imm32S
|Disp32
},
3772 { "GOTOFF", { BFD_RELOC_386_GOTOFF
, 0, BFD_RELOC_X86_64_GOTOFF64
}, Imm64
|Disp64
},
3773 { "GOTPCREL", { 0, 0, BFD_RELOC_X86_64_GOTPCREL
}, Imm32
|Imm32S
|Disp32
},
3774 { "TLSGD", { BFD_RELOC_386_TLS_GD
, 0, BFD_RELOC_X86_64_TLSGD
}, Imm32
|Imm32S
|Disp32
},
3775 { "TLSLDM", { BFD_RELOC_386_TLS_LDM
, 0, 0 }, 0 },
3776 { "TLSLD", { 0, 0, BFD_RELOC_X86_64_TLSLD
}, Imm32
|Imm32S
|Disp32
},
3777 { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32
, 0, BFD_RELOC_X86_64_GOTTPOFF
}, Imm32
|Imm32S
|Disp32
},
3778 { "TPOFF", { BFD_RELOC_386_TLS_LE_32
, 0, BFD_RELOC_X86_64_TPOFF32
}, Imm32
|Imm32S
|Imm64
|Disp32
|Disp64
},
3779 { "NTPOFF", { BFD_RELOC_386_TLS_LE
, 0, 0 }, 0 },
3780 { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32
, 0, BFD_RELOC_X86_64_DTPOFF32
}, Imm32
|Imm32S
|Imm64
|Disp32
|Disp64
},
3781 { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE
, 0, 0 }, 0 },
3782 { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE
, 0, 0 }, 0 },
3783 { "GOT", { BFD_RELOC_386_GOT32
, 0, BFD_RELOC_X86_64_GOT32
}, Imm32
|Imm32S
|Disp32
}
3791 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
3792 if (is_end_of_line
[(unsigned char) *cp
])
3795 for (j
= 0; j
< sizeof (gotrel
) / sizeof (gotrel
[0]); j
++)
3799 len
= strlen (gotrel
[j
].str
);
3800 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
3802 if (gotrel
[j
].rel
[(unsigned int) flag_code
] != 0)
3805 char *tmpbuf
, *past_reloc
;
3807 *reloc
= gotrel
[j
].rel
[(unsigned int) flag_code
];
3813 if (flag_code
!= CODE_64BIT
)
3814 *types
= Imm32
|Disp32
;
3816 *types
= gotrel
[j
].types64
;
3819 if (GOT_symbol
== NULL
)
3820 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
3822 /* Replace the relocation token with ' ', so that
3823 errors like foo@GOTOFF1 will be detected. */
3825 /* The length of the first part of our input line. */
3826 first
= cp
- input_line_pointer
;
3828 /* The second part goes from after the reloc token until
3829 (and including) an end_of_line char. Don't use strlen
3830 here as the end_of_line char may not be a NUL. */
3831 past_reloc
= cp
+ 1 + len
;
3832 for (cp
= past_reloc
; !is_end_of_line
[(unsigned char) *cp
++]; )
3834 second
= cp
- past_reloc
;
3836 /* Allocate and copy string. The trailing NUL shouldn't
3837 be necessary, but be safe. */
3838 tmpbuf
= xmalloc (first
+ second
+ 2);
3839 memcpy (tmpbuf
, input_line_pointer
, first
);
3840 tmpbuf
[first
] = ' ';
3841 memcpy (tmpbuf
+ first
+ 1, past_reloc
, second
);
3842 tmpbuf
[first
+ second
+ 1] = '\0';
3846 as_bad (_("@%s reloc is not supported in %s bit mode"),
3847 gotrel
[j
].str
, mode_name
[(unsigned int) flag_code
]);
3852 /* Might be a symbol version string. Don't as_bad here. */
3856 /* x86_cons_fix_new is called via the expression parsing code when a
3857 reloc is needed. We use this hook to get the correct .got reloc. */
3858 static enum bfd_reloc_code_real got_reloc
= NO_RELOC
;
3861 x86_cons_fix_new (frag
, off
, len
, exp
)
3867 enum bfd_reloc_code_real r
= reloc (len
, 0, -1, got_reloc
);
3868 got_reloc
= NO_RELOC
;
3869 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
3873 x86_cons (exp
, size
)
3877 if (size
== 4 || (flag_code
== CODE_64BIT
&& size
== 8))
3879 /* Handle @GOTOFF and the like in an expression. */
3881 char *gotfree_input_line
;
3884 save
= input_line_pointer
;
3885 gotfree_input_line
= lex_got (&got_reloc
, &adjust
, NULL
);
3886 if (gotfree_input_line
)
3887 input_line_pointer
= gotfree_input_line
;
3891 if (gotfree_input_line
)
3893 /* expression () has merrily parsed up to the end of line,
3894 or a comma - in the wrong buffer. Transfer how far
3895 input_line_pointer has moved to the right buffer. */
3896 input_line_pointer
= (save
3897 + (input_line_pointer
- gotfree_input_line
)
3899 free (gotfree_input_line
);
3910 x86_pe_cons_fix_new (frag
, off
, len
, exp
)
3916 enum bfd_reloc_code_real r
= reloc (len
, 0, -1, NO_RELOC
);
3918 if (exp
->X_op
== O_secrel
)
3920 exp
->X_op
= O_symbol
;
3921 r
= BFD_RELOC_32_SECREL
;
3924 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
3928 pe_directive_secrel (dummy
)
3929 int dummy ATTRIBUTE_UNUSED
;
3936 if (exp
.X_op
== O_symbol
)
3937 exp
.X_op
= O_secrel
;
3939 emit_expr (&exp
, 4);
3941 while (*input_line_pointer
++ == ',');
3943 input_line_pointer
--;
3944 demand_empty_rest_of_line ();
3949 static int i386_immediate
PARAMS ((char *));
3952 i386_immediate (imm_start
)
3955 char *save_input_line_pointer
;
3956 char *gotfree_input_line
;
3959 unsigned int types
= ~0U;
3961 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
3963 as_bad (_("only 1 or 2 immediate operands are allowed"));
3967 exp
= &im_expressions
[i
.imm_operands
++];
3968 i
.op
[this_operand
].imms
= exp
;
3970 if (is_space_char (*imm_start
))
3973 save_input_line_pointer
= input_line_pointer
;
3974 input_line_pointer
= imm_start
;
3976 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
3977 if (gotfree_input_line
)
3978 input_line_pointer
= gotfree_input_line
;
3980 exp_seg
= expression (exp
);
3983 if (*input_line_pointer
)
3984 as_bad (_("junk `%s' after expression"), input_line_pointer
);
3986 input_line_pointer
= save_input_line_pointer
;
3987 if (gotfree_input_line
)
3988 free (gotfree_input_line
);
3990 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_big
)
3992 /* Missing or bad expr becomes absolute 0. */
3993 as_bad (_("missing or invalid immediate expression `%s' taken as 0"),
3995 exp
->X_op
= O_constant
;
3996 exp
->X_add_number
= 0;
3997 exp
->X_add_symbol
= (symbolS
*) 0;
3998 exp
->X_op_symbol
= (symbolS
*) 0;
4000 else if (exp
->X_op
== O_constant
)
4002 /* Size it properly later. */
4003 i
.types
[this_operand
] |= Imm64
;
4004 /* If BFD64, sign extend val. */
4005 if (!use_rela_relocations
)
4006 if ((exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
4007 exp
->X_add_number
= (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
4009 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
4010 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
4011 && exp_seg
!= absolute_section
4012 && exp_seg
!= text_section
4013 && exp_seg
!= data_section
4014 && exp_seg
!= bss_section
4015 && exp_seg
!= undefined_section
4016 && !bfd_is_com_section (exp_seg
))
4018 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
4024 /* This is an address. The size of the address will be
4025 determined later, depending on destination register,
4026 suffix, or the default for the section. */
4027 i
.types
[this_operand
] |= Imm8
| Imm16
| Imm32
| Imm32S
| Imm64
;
4028 i
.types
[this_operand
] &= types
;
4034 static char *i386_scale
PARAMS ((char *));
4041 char *save
= input_line_pointer
;
4043 input_line_pointer
= scale
;
4044 val
= get_absolute_expression ();
4049 i
.log2_scale_factor
= 0;
4052 i
.log2_scale_factor
= 1;
4055 i
.log2_scale_factor
= 2;
4058 i
.log2_scale_factor
= 3;
4062 char sep
= *input_line_pointer
;
4064 *input_line_pointer
= '\0';
4065 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
4067 *input_line_pointer
= sep
;
4068 input_line_pointer
= save
;
4072 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
4074 as_warn (_("scale factor of %d without an index register"),
4075 1 << i
.log2_scale_factor
);
4076 #if SCALE1_WHEN_NO_INDEX
4077 i
.log2_scale_factor
= 0;
4080 scale
= input_line_pointer
;
4081 input_line_pointer
= save
;
4085 static int i386_displacement
PARAMS ((char *, char *));
4088 i386_displacement (disp_start
, disp_end
)
4094 char *save_input_line_pointer
;
4095 char *gotfree_input_line
;
4096 int bigdisp
= Disp32
;
4097 unsigned int types
= Disp
;
4099 if (flag_code
== CODE_64BIT
)
4101 if (i
.prefix
[ADDR_PREFIX
] == 0)
4102 bigdisp
= Disp64
| Disp32S
| Disp32
;
4104 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[ADDR_PREFIX
] != 0))
4106 i
.types
[this_operand
] |= bigdisp
;
4108 exp
= &disp_expressions
[i
.disp_operands
];
4109 i
.op
[this_operand
].disps
= exp
;
4111 save_input_line_pointer
= input_line_pointer
;
4112 input_line_pointer
= disp_start
;
4113 END_STRING_AND_SAVE (disp_end
);
4115 #ifndef GCC_ASM_O_HACK
4116 #define GCC_ASM_O_HACK 0
4119 END_STRING_AND_SAVE (disp_end
+ 1);
4120 if ((i
.types
[this_operand
] & BaseIndex
) != 0
4121 && displacement_string_end
[-1] == '+')
4123 /* This hack is to avoid a warning when using the "o"
4124 constraint within gcc asm statements.
4127 #define _set_tssldt_desc(n,addr,limit,type) \
4128 __asm__ __volatile__ ( \
4130 "movw %w1,2+%0\n\t" \
4132 "movb %b1,4+%0\n\t" \
4133 "movb %4,5+%0\n\t" \
4134 "movb $0,6+%0\n\t" \
4135 "movb %h1,7+%0\n\t" \
4137 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
4139 This works great except that the output assembler ends
4140 up looking a bit weird if it turns out that there is
4141 no offset. You end up producing code that looks like:
4154 So here we provide the missing zero. */
4156 *displacement_string_end
= '0';
4159 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
4160 if (gotfree_input_line
)
4161 input_line_pointer
= gotfree_input_line
;
4163 exp_seg
= expression (exp
);
4166 if (*input_line_pointer
)
4167 as_bad (_("junk `%s' after expression"), input_line_pointer
);
4169 RESTORE_END_STRING (disp_end
+ 1);
4171 RESTORE_END_STRING (disp_end
);
4172 input_line_pointer
= save_input_line_pointer
;
4173 if (gotfree_input_line
)
4174 free (gotfree_input_line
);
4176 /* We do this to make sure that the section symbol is in
4177 the symbol table. We will ultimately change the relocation
4178 to be relative to the beginning of the section. */
4179 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
4180 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
4181 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
4183 if (exp
->X_op
!= O_symbol
)
4185 as_bad (_("bad expression used with @%s"),
4186 (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
4192 if (S_IS_LOCAL (exp
->X_add_symbol
)
4193 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
)
4194 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
4195 exp
->X_op
= O_subtract
;
4196 exp
->X_op_symbol
= GOT_symbol
;
4197 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
4198 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
4199 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
4200 i
.reloc
[this_operand
] = BFD_RELOC_64
;
4202 i
.reloc
[this_operand
] = BFD_RELOC_32
;
4205 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_big
)
4207 /* Missing or bad expr becomes absolute 0. */
4208 as_bad (_("missing or invalid displacement expression `%s' taken as 0"),
4210 exp
->X_op
= O_constant
;
4211 exp
->X_add_number
= 0;
4212 exp
->X_add_symbol
= (symbolS
*) 0;
4213 exp
->X_op_symbol
= (symbolS
*) 0;
4216 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
4217 if (exp
->X_op
!= O_constant
4218 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
4219 && exp_seg
!= absolute_section
4220 && exp_seg
!= text_section
4221 && exp_seg
!= data_section
4222 && exp_seg
!= bss_section
4223 && exp_seg
!= undefined_section
4224 && !bfd_is_com_section (exp_seg
))
4226 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
4231 if (!(i
.types
[this_operand
] & ~Disp
))
4232 i
.types
[this_operand
] &= types
;
4237 static int i386_index_check
PARAMS ((const char *));
4239 /* Make sure the memory operand we've been dealt is valid.
4240 Return 1 on success, 0 on a failure. */
4243 i386_index_check (operand_string
)
4244 const char *operand_string
;
4247 #if INFER_ADDR_PREFIX
4253 if ((current_templates
->start
->cpu_flags
& CpuSVME
)
4254 && current_templates
->end
[-1].operand_types
[0] == AnyMem
)
4256 /* Memory operands of SVME insns are special in that they only allow
4257 rAX as their memory address and ignore any segment override. */
4260 /* SKINIT is even more restrictive: it always requires EAX. */
4261 if (strcmp (current_templates
->start
->name
, "skinit") == 0)
4263 else if (flag_code
== CODE_64BIT
)
4264 RegXX
= i
.prefix
[ADDR_PREFIX
] == 0 ? Reg64
: Reg32
;
4266 RegXX
= (flag_code
== CODE_16BIT
) ^ (i
.prefix
[ADDR_PREFIX
] != 0)
4270 || !(i
.base_reg
->reg_type
& Acc
)
4271 || !(i
.base_reg
->reg_type
& RegXX
)
4273 || (i
.types
[0] & Disp
))
4276 else if (flag_code
== CODE_64BIT
)
4278 unsigned RegXX
= (i
.prefix
[ADDR_PREFIX
] == 0 ? Reg64
: Reg32
);
4281 && ((i
.base_reg
->reg_type
& RegXX
) == 0)
4282 && (i
.base_reg
->reg_type
!= BaseIndex
4285 && ((i
.index_reg
->reg_type
& (RegXX
| BaseIndex
))
4286 != (RegXX
| BaseIndex
))))
4291 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[ADDR_PREFIX
] != 0))
4295 && ((i
.base_reg
->reg_type
& (Reg16
| BaseIndex
| RegRex
))
4296 != (Reg16
| BaseIndex
)))
4298 && (((i
.index_reg
->reg_type
& (Reg16
| BaseIndex
))
4299 != (Reg16
| BaseIndex
))
4301 && i
.base_reg
->reg_num
< 6
4302 && i
.index_reg
->reg_num
>= 6
4303 && i
.log2_scale_factor
== 0))))
4310 && (i
.base_reg
->reg_type
& (Reg32
| RegRex
)) != Reg32
)
4312 && ((i
.index_reg
->reg_type
& (Reg32
| BaseIndex
| RegRex
))
4313 != (Reg32
| BaseIndex
))))
4319 #if INFER_ADDR_PREFIX
4320 if (i
.prefix
[ADDR_PREFIX
] == 0)
4322 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
4324 /* Change the size of any displacement too. At most one of
4325 Disp16 or Disp32 is set.
4326 FIXME. There doesn't seem to be any real need for separate
4327 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
4328 Removing them would probably clean up the code quite a lot. */
4329 if (flag_code
!= CODE_64BIT
&& (i
.types
[this_operand
] & (Disp16
| Disp32
)))
4330 i
.types
[this_operand
] ^= (Disp16
| Disp32
);
4335 as_bad (_("`%s' is not a valid base/index expression"),
4339 as_bad (_("`%s' is not a valid %s bit base/index expression"),
4341 flag_code_names
[flag_code
]);
4346 /* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero
4350 i386_operand (operand_string
)
4351 char *operand_string
;
4355 char *op_string
= operand_string
;
4357 if (is_space_char (*op_string
))
4360 /* We check for an absolute prefix (differentiating,
4361 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
4362 if (*op_string
== ABSOLUTE_PREFIX
)
4365 if (is_space_char (*op_string
))
4367 i
.types
[this_operand
] |= JumpAbsolute
;
4370 /* Check if operand is a register. */
4371 if ((*op_string
== REGISTER_PREFIX
|| allow_naked_reg
)
4372 && (r
= parse_register (op_string
, &end_op
)) != NULL
)
4374 /* Check for a segment override by searching for ':' after a
4375 segment register. */
4377 if (is_space_char (*op_string
))
4379 if (*op_string
== ':' && (r
->reg_type
& (SReg2
| SReg3
)))
4384 i
.seg
[i
.mem_operands
] = &es
;
4387 i
.seg
[i
.mem_operands
] = &cs
;
4390 i
.seg
[i
.mem_operands
] = &ss
;
4393 i
.seg
[i
.mem_operands
] = &ds
;
4396 i
.seg
[i
.mem_operands
] = &fs
;
4399 i
.seg
[i
.mem_operands
] = &gs
;
4403 /* Skip the ':' and whitespace. */
4405 if (is_space_char (*op_string
))
4408 if (!is_digit_char (*op_string
)
4409 && !is_identifier_char (*op_string
)
4410 && *op_string
!= '('
4411 && *op_string
!= ABSOLUTE_PREFIX
)
4413 as_bad (_("bad memory operand `%s'"), op_string
);
4416 /* Handle case of %es:*foo. */
4417 if (*op_string
== ABSOLUTE_PREFIX
)
4420 if (is_space_char (*op_string
))
4422 i
.types
[this_operand
] |= JumpAbsolute
;
4424 goto do_memory_reference
;
4428 as_bad (_("junk `%s' after register"), op_string
);
4431 i
.types
[this_operand
] |= r
->reg_type
& ~BaseIndex
;
4432 i
.op
[this_operand
].regs
= r
;
4435 else if (*op_string
== REGISTER_PREFIX
)
4437 as_bad (_("bad register name `%s'"), op_string
);
4440 else if (*op_string
== IMMEDIATE_PREFIX
)
4443 if (i
.types
[this_operand
] & JumpAbsolute
)
4445 as_bad (_("immediate operand illegal with absolute jump"));
4448 if (!i386_immediate (op_string
))
4451 else if (is_digit_char (*op_string
)
4452 || is_identifier_char (*op_string
)
4453 || *op_string
== '(')
4455 /* This is a memory reference of some sort. */
4458 /* Start and end of displacement string expression (if found). */
4459 char *displacement_string_start
;
4460 char *displacement_string_end
;
4462 do_memory_reference
:
4463 if ((i
.mem_operands
== 1
4464 && (current_templates
->start
->opcode_modifier
& IsString
) == 0)
4465 || i
.mem_operands
== 2)
4467 as_bad (_("too many memory references for `%s'"),
4468 current_templates
->start
->name
);
4472 /* Check for base index form. We detect the base index form by
4473 looking for an ')' at the end of the operand, searching
4474 for the '(' matching it, and finding a REGISTER_PREFIX or ','
4476 base_string
= op_string
+ strlen (op_string
);
4479 if (is_space_char (*base_string
))
4482 /* If we only have a displacement, set-up for it to be parsed later. */
4483 displacement_string_start
= op_string
;
4484 displacement_string_end
= base_string
+ 1;
4486 if (*base_string
== ')')
4489 unsigned int parens_balanced
= 1;
4490 /* We've already checked that the number of left & right ()'s are
4491 equal, so this loop will not be infinite. */
4495 if (*base_string
== ')')
4497 if (*base_string
== '(')
4500 while (parens_balanced
);
4502 temp_string
= base_string
;
4504 /* Skip past '(' and whitespace. */
4506 if (is_space_char (*base_string
))
4509 if (*base_string
== ','
4510 || ((*base_string
== REGISTER_PREFIX
|| allow_naked_reg
)
4511 && (i
.base_reg
= parse_register (base_string
, &end_op
)) != NULL
))
4513 displacement_string_end
= temp_string
;
4515 i
.types
[this_operand
] |= BaseIndex
;
4519 base_string
= end_op
;
4520 if (is_space_char (*base_string
))
4524 /* There may be an index reg or scale factor here. */
4525 if (*base_string
== ',')
4528 if (is_space_char (*base_string
))
4531 if ((*base_string
== REGISTER_PREFIX
|| allow_naked_reg
)
4532 && (i
.index_reg
= parse_register (base_string
, &end_op
)) != NULL
)
4534 base_string
= end_op
;
4535 if (is_space_char (*base_string
))
4537 if (*base_string
== ',')
4540 if (is_space_char (*base_string
))
4543 else if (*base_string
!= ')')
4545 as_bad (_("expecting `,' or `)' after index register in `%s'"),
4550 else if (*base_string
== REGISTER_PREFIX
)
4552 as_bad (_("bad register name `%s'"), base_string
);
4556 /* Check for scale factor. */
4557 if (*base_string
!= ')')
4559 char *end_scale
= i386_scale (base_string
);
4564 base_string
= end_scale
;
4565 if (is_space_char (*base_string
))
4567 if (*base_string
!= ')')
4569 as_bad (_("expecting `)' after scale factor in `%s'"),
4574 else if (!i
.index_reg
)
4576 as_bad (_("expecting index register or scale factor after `,'; got '%c'"),
4581 else if (*base_string
!= ')')
4583 as_bad (_("expecting `,' or `)' after base register in `%s'"),
4588 else if (*base_string
== REGISTER_PREFIX
)
4590 as_bad (_("bad register name `%s'"), base_string
);
4595 /* If there's an expression beginning the operand, parse it,
4596 assuming displacement_string_start and
4597 displacement_string_end are meaningful. */
4598 if (displacement_string_start
!= displacement_string_end
)
4600 if (!i386_displacement (displacement_string_start
,
4601 displacement_string_end
))
4605 /* Special case for (%dx) while doing input/output op. */
4607 && i
.base_reg
->reg_type
== (Reg16
| InOutPortReg
)
4609 && i
.log2_scale_factor
== 0
4610 && i
.seg
[i
.mem_operands
] == 0
4611 && (i
.types
[this_operand
] & Disp
) == 0)
4613 i
.types
[this_operand
] = InOutPortReg
;
4617 if (i386_index_check (operand_string
) == 0)
4623 /* It's not a memory operand; argh! */
4624 as_bad (_("invalid char %s beginning operand %d `%s'"),
4625 output_invalid (*op_string
),
4630 return 1; /* Normal return. */
4633 /* md_estimate_size_before_relax()
4635 Called just before relax() for rs_machine_dependent frags. The x86
4636 assembler uses these frags to handle variable size jump
4639 Any symbol that is now undefined will not become defined.
4640 Return the correct fr_subtype in the frag.
4641 Return the initial "guess for variable size of frag" to caller.
4642 The guess is actually the growth beyond the fixed part. Whatever
4643 we do to grow the fixed or variable part contributes to our
4647 md_estimate_size_before_relax (fragP
, segment
)
4651 /* We've already got fragP->fr_subtype right; all we have to do is
4652 check for un-relaxable symbols. On an ELF system, we can't relax
4653 an externally visible symbol, because it may be overridden by a
4655 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
4656 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4658 && (S_IS_EXTERNAL (fragP
->fr_symbol
)
4659 || S_IS_WEAK (fragP
->fr_symbol
)))
4663 /* Symbol is undefined in this segment, or we need to keep a
4664 reloc so that weak symbols can be overridden. */
4665 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
4666 enum bfd_reloc_code_real reloc_type
;
4667 unsigned char *opcode
;
4670 if (fragP
->fr_var
!= NO_RELOC
)
4671 reloc_type
= fragP
->fr_var
;
4673 reloc_type
= BFD_RELOC_16_PCREL
;
4675 reloc_type
= BFD_RELOC_32_PCREL
;
4677 old_fr_fix
= fragP
->fr_fix
;
4678 opcode
= (unsigned char *) fragP
->fr_opcode
;
4680 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
4683 /* Make jmp (0xeb) a (d)word displacement jump. */
4685 fragP
->fr_fix
+= size
;
4686 fix_new (fragP
, old_fr_fix
, size
,
4688 fragP
->fr_offset
, 1,
4694 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
4696 /* Negate the condition, and branch past an
4697 unconditional jump. */
4700 /* Insert an unconditional jump. */
4702 /* We added two extra opcode bytes, and have a two byte
4704 fragP
->fr_fix
+= 2 + 2;
4705 fix_new (fragP
, old_fr_fix
+ 2, 2,
4707 fragP
->fr_offset
, 1,
4714 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
4719 fixP
= fix_new (fragP
, old_fr_fix
, 1,
4721 fragP
->fr_offset
, 1,
4723 fixP
->fx_signed
= 1;
4727 /* This changes the byte-displacement jump 0x7N
4728 to the (d)word-displacement jump 0x0f,0x8N. */
4729 opcode
[1] = opcode
[0] + 0x10;
4730 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
4731 /* We've added an opcode byte. */
4732 fragP
->fr_fix
+= 1 + size
;
4733 fix_new (fragP
, old_fr_fix
+ 1, size
,
4735 fragP
->fr_offset
, 1,
4740 BAD_CASE (fragP
->fr_subtype
);
4744 return fragP
->fr_fix
- old_fr_fix
;
4747 /* Guess size depending on current relax state. Initially the relax
4748 state will correspond to a short jump and we return 1, because
4749 the variable part of the frag (the branch offset) is one byte
4750 long. However, we can relax a section more than once and in that
4751 case we must either set fr_subtype back to the unrelaxed state,
4752 or return the value for the appropriate branch. */
4753 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
4756 /* Called after relax() is finished.
4758 In: Address of frag.
4759 fr_type == rs_machine_dependent.
4760 fr_subtype is what the address relaxed to.
4762 Out: Any fixSs and constants are set up.
4763 Caller will turn frag into a ".space 0". */
4766 md_convert_frag (abfd
, sec
, fragP
)
4767 bfd
*abfd ATTRIBUTE_UNUSED
;
4768 segT sec ATTRIBUTE_UNUSED
;
4771 unsigned char *opcode
;
4772 unsigned char *where_to_put_displacement
= NULL
;
4773 offsetT target_address
;
4774 offsetT opcode_address
;
4775 unsigned int extension
= 0;
4776 offsetT displacement_from_opcode_start
;
4778 opcode
= (unsigned char *) fragP
->fr_opcode
;
4780 /* Address we want to reach in file space. */
4781 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
4783 /* Address opcode resides at in file space. */
4784 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
4786 /* Displacement from opcode start to fill into instruction. */
4787 displacement_from_opcode_start
= target_address
- opcode_address
;
4789 if ((fragP
->fr_subtype
& BIG
) == 0)
4791 /* Don't have to change opcode. */
4792 extension
= 1; /* 1 opcode + 1 displacement */
4793 where_to_put_displacement
= &opcode
[1];
4797 if (no_cond_jump_promotion
4798 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
4799 as_warn_where (fragP
->fr_file
, fragP
->fr_line
, _("long jump required"));
4801 switch (fragP
->fr_subtype
)
4803 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
4804 extension
= 4; /* 1 opcode + 4 displacement */
4806 where_to_put_displacement
= &opcode
[1];
4809 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
4810 extension
= 2; /* 1 opcode + 2 displacement */
4812 where_to_put_displacement
= &opcode
[1];
4815 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
4816 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
4817 extension
= 5; /* 2 opcode + 4 displacement */
4818 opcode
[1] = opcode
[0] + 0x10;
4819 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
4820 where_to_put_displacement
= &opcode
[2];
4823 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
4824 extension
= 3; /* 2 opcode + 2 displacement */
4825 opcode
[1] = opcode
[0] + 0x10;
4826 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
4827 where_to_put_displacement
= &opcode
[2];
4830 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
4835 where_to_put_displacement
= &opcode
[3];
4839 BAD_CASE (fragP
->fr_subtype
);
4844 /* Now put displacement after opcode. */
4845 md_number_to_chars ((char *) where_to_put_displacement
,
4846 (valueT
) (displacement_from_opcode_start
- extension
),
4847 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
4848 fragP
->fr_fix
+= extension
;
4851 /* Size of byte displacement jmp. */
4852 int md_short_jump_size
= 2;
4854 /* Size of dword displacement jmp. */
4855 int md_long_jump_size
= 5;
4857 /* Size of relocation record. */
4858 const int md_reloc_size
= 8;
4861 md_create_short_jump (ptr
, from_addr
, to_addr
, frag
, to_symbol
)
4863 addressT from_addr
, to_addr
;
4864 fragS
*frag ATTRIBUTE_UNUSED
;
4865 symbolS
*to_symbol ATTRIBUTE_UNUSED
;
4869 offset
= to_addr
- (from_addr
+ 2);
4870 /* Opcode for byte-disp jump. */
4871 md_number_to_chars (ptr
, (valueT
) 0xeb, 1);
4872 md_number_to_chars (ptr
+ 1, (valueT
) offset
, 1);
4876 md_create_long_jump (ptr
, from_addr
, to_addr
, frag
, to_symbol
)
4878 addressT from_addr
, to_addr
;
4879 fragS
*frag ATTRIBUTE_UNUSED
;
4880 symbolS
*to_symbol ATTRIBUTE_UNUSED
;
4884 offset
= to_addr
- (from_addr
+ 5);
4885 md_number_to_chars (ptr
, (valueT
) 0xe9, 1);
4886 md_number_to_chars (ptr
+ 1, (valueT
) offset
, 4);
4889 /* Apply a fixup (fixS) to segment data, once it has been determined
4890 by our caller that we have all the info we need to fix it up.
4892 On the 386, immediates, displacements, and data pointers are all in
4893 the same (little-endian) format, so we don't need to care about which
4897 md_apply_fix (fixP
, valP
, seg
)
4898 /* The fix we're to put in. */
4900 /* Pointer to the value of the bits. */
4902 /* Segment fix is from. */
4903 segT seg ATTRIBUTE_UNUSED
;
4905 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
4906 valueT value
= *valP
;
4908 #if !defined (TE_Mach)
4911 switch (fixP
->fx_r_type
)
4917 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
4920 case BFD_RELOC_X86_64_32S
:
4921 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
4924 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
4927 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
4932 if (fixP
->fx_addsy
!= NULL
4933 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
4934 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
4935 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
4936 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
4937 && !use_rela_relocations
)
4939 /* This is a hack. There should be a better way to handle this.
4940 This covers for the fact that bfd_install_relocation will
4941 subtract the current location (for partial_inplace, PC relative
4942 relocations); see more below. */
4946 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
4949 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
4951 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4954 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
4957 || (symbol_section_p (fixP
->fx_addsy
)
4958 && sym_seg
!= absolute_section
))
4959 && !generic_force_reloc (fixP
))
4961 /* Yes, we add the values in twice. This is because
4962 bfd_install_relocation subtracts them out again. I think
4963 bfd_install_relocation is broken, but I don't dare change
4965 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
4969 #if defined (OBJ_COFF) && defined (TE_PE)
4970 /* For some reason, the PE format does not store a
4971 section address offset for a PC relative symbol. */
4972 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
4973 #if defined(BFD_ASSEMBLER) || defined(S_IS_WEAK)
4974 || S_IS_WEAK (fixP
->fx_addsy
)
4977 value
+= md_pcrel_from (fixP
);
4981 /* Fix a few things - the dynamic linker expects certain values here,
4982 and we must not disappoint it. */
4983 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4984 if (IS_ELF
&& fixP
->fx_addsy
)
4985 switch (fixP
->fx_r_type
)
4987 case BFD_RELOC_386_PLT32
:
4988 case BFD_RELOC_X86_64_PLT32
:
4989 /* Make the jump instruction point to the address of the operand. At
4990 runtime we merely add the offset to the actual PLT entry. */
4994 case BFD_RELOC_386_TLS_GD
:
4995 case BFD_RELOC_386_TLS_LDM
:
4996 case BFD_RELOC_386_TLS_IE_32
:
4997 case BFD_RELOC_386_TLS_IE
:
4998 case BFD_RELOC_386_TLS_GOTIE
:
4999 case BFD_RELOC_X86_64_TLSGD
:
5000 case BFD_RELOC_X86_64_TLSLD
:
5001 case BFD_RELOC_X86_64_GOTTPOFF
:
5002 value
= 0; /* Fully resolved at runtime. No addend. */
5004 case BFD_RELOC_386_TLS_LE
:
5005 case BFD_RELOC_386_TLS_LDO_32
:
5006 case BFD_RELOC_386_TLS_LE_32
:
5007 case BFD_RELOC_X86_64_DTPOFF32
:
5008 case BFD_RELOC_X86_64_DTPOFF64
:
5009 case BFD_RELOC_X86_64_TPOFF32
:
5010 case BFD_RELOC_X86_64_TPOFF64
:
5011 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
5014 case BFD_RELOC_386_GOT32
:
5015 case BFD_RELOC_X86_64_GOT32
:
5016 value
= 0; /* Fully resolved at runtime. No addend. */
5019 case BFD_RELOC_VTABLE_INHERIT
:
5020 case BFD_RELOC_VTABLE_ENTRY
:
5027 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
5029 #endif /* !defined (TE_Mach) */
5031 /* Are we finished with this relocation now? */
5032 if (fixP
->fx_addsy
== NULL
)
5034 else if (use_rela_relocations
)
5036 fixP
->fx_no_overflow
= 1;
5037 /* Remember value for tc_gen_reloc. */
5038 fixP
->fx_addnumber
= value
;
5042 md_number_to_chars (p
, value
, fixP
->fx_size
);
5045 #define MAX_LITTLENUMS 6
5047 /* Turn the string pointed to by litP into a floating point constant
5048 of type TYPE, and emit the appropriate bytes. The number of
5049 LITTLENUMS emitted is stored in *SIZEP. An error message is
5050 returned, or NULL on OK. */
5053 md_atof (type
, litP
, sizeP
)
5059 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
5060 LITTLENUM_TYPE
*wordP
;
5082 return _("Bad call to md_atof ()");
5084 t
= atof_ieee (input_line_pointer
, type
, words
);
5086 input_line_pointer
= t
;
5088 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
5089 /* This loops outputs the LITTLENUMs in REVERSE order; in accord with
5090 the bigendian 386. */
5091 for (wordP
= words
+ prec
- 1; prec
--;)
5093 md_number_to_chars (litP
, (valueT
) (*wordP
--), sizeof (LITTLENUM_TYPE
));
5094 litP
+= sizeof (LITTLENUM_TYPE
);
5099 static char output_invalid_buf
[8];
5106 sprintf (output_invalid_buf
, "'%c'", c
);
5108 sprintf (output_invalid_buf
, "(0x%x)", (unsigned) c
);
5109 return output_invalid_buf
;
5112 /* REG_STRING starts *before* REGISTER_PREFIX. */
5114 static const reg_entry
*
5115 parse_register (reg_string
, end_op
)
5119 char *s
= reg_string
;
5121 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
5124 /* Skip possible REGISTER_PREFIX and possible whitespace. */
5125 if (*s
== REGISTER_PREFIX
)
5128 if (is_space_char (*s
))
5132 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
5134 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
5135 return (const reg_entry
*) NULL
;
5139 /* For naked regs, make sure that we are not dealing with an identifier.
5140 This prevents confusing an identifier like `eax_var' with register
5142 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
5143 return (const reg_entry
*) NULL
;
5147 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
5149 /* Handle floating point regs, allowing spaces in the (i) part. */
5150 if (r
== i386_regtab
/* %st is first entry of table */)
5152 if (is_space_char (*s
))
5157 if (is_space_char (*s
))
5159 if (*s
>= '0' && *s
<= '7')
5161 r
= &i386_float_regtab
[*s
- '0'];
5163 if (is_space_char (*s
))
5171 /* We have "%st(" then garbage. */
5172 return (const reg_entry
*) NULL
;
5177 && ((r
->reg_flags
& (RegRex64
| RegRex
)) | (r
->reg_type
& Reg64
)) != 0
5178 && (r
->reg_type
!= Control
|| !(cpu_arch_flags
& CpuSledgehammer
))
5179 && flag_code
!= CODE_64BIT
)
5180 return (const reg_entry
*) NULL
;
5185 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5186 const char *md_shortopts
= "kVQ:sqn";
5188 const char *md_shortopts
= "qn";
5191 struct option md_longopts
[] = {
5192 #define OPTION_32 (OPTION_MD_BASE + 0)
5193 {"32", no_argument
, NULL
, OPTION_32
},
5194 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5195 #define OPTION_64 (OPTION_MD_BASE + 1)
5196 {"64", no_argument
, NULL
, OPTION_64
},
5198 {NULL
, no_argument
, NULL
, 0}
5200 size_t md_longopts_size
= sizeof (md_longopts
);
5203 md_parse_option (c
, arg
)
5205 char *arg ATTRIBUTE_UNUSED
;
5210 optimize_align_code
= 0;
5217 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5218 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
5219 should be emitted or not. FIXME: Not implemented. */
5223 /* -V: SVR4 argument to print version ID. */
5225 print_version_id ();
5228 /* -k: Ignore for FreeBSD compatibility. */
5233 /* -s: On i386 Solaris, this tells the native assembler to use
5234 .stab instead of .stab.excl. We always use .stab anyhow. */
5239 const char **list
, **l
;
5241 list
= bfd_target_list ();
5242 for (l
= list
; *l
!= NULL
; l
++)
5243 if (strcmp (*l
, "elf64-x86-64") == 0)
5245 default_arch
= "x86_64";
5249 as_fatal (_("No compiled in support for x86_64"));
5256 default_arch
= "i386";
5266 md_show_usage (stream
)
5269 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5270 fprintf (stream
, _("\
5272 -V print assembler version number\n\
5274 -n Do not optimize code alignment\n\
5275 -q quieten some warnings\n\
5278 fprintf (stream
, _("\
5279 -n Do not optimize code alignment\n\
5280 -q quieten some warnings\n"));
5284 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
5285 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
5287 /* Pick the target format to use. */
5290 i386_target_format ()
5292 if (!strcmp (default_arch
, "x86_64"))
5293 set_code_flag (CODE_64BIT
);
5294 else if (!strcmp (default_arch
, "i386"))
5295 set_code_flag (CODE_32BIT
);
5297 as_fatal (_("Unknown architecture"));
5298 switch (OUTPUT_FLAVOR
)
5300 #ifdef OBJ_MAYBE_AOUT
5301 case bfd_target_aout_flavour
:
5302 return AOUT_TARGET_FORMAT
;
5304 #ifdef OBJ_MAYBE_COFF
5305 case bfd_target_coff_flavour
:
5308 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
5309 case bfd_target_elf_flavour
:
5311 if (flag_code
== CODE_64BIT
)
5312 use_rela_relocations
= 1;
5313 return flag_code
== CODE_64BIT
? "elf64-x86-64" : ELF_TARGET_FORMAT
;
5322 #endif /* OBJ_MAYBE_ more than one */
5324 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
5325 void i386_elf_emit_arch_note ()
5327 if (IS_ELF
&& cpu_arch_name
!= NULL
)
5330 asection
*seg
= now_seg
;
5331 subsegT subseg
= now_subseg
;
5332 Elf_Internal_Note i_note
;
5333 Elf_External_Note e_note
;
5334 asection
*note_secp
;
5337 /* Create the .note section. */
5338 note_secp
= subseg_new (".note", 0);
5339 bfd_set_section_flags (stdoutput
,
5341 SEC_HAS_CONTENTS
| SEC_READONLY
);
5343 /* Process the arch string. */
5344 len
= strlen (cpu_arch_name
);
5346 i_note
.namesz
= len
+ 1;
5348 i_note
.type
= NT_ARCH
;
5349 p
= frag_more (sizeof (e_note
.namesz
));
5350 md_number_to_chars (p
, (valueT
) i_note
.namesz
, sizeof (e_note
.namesz
));
5351 p
= frag_more (sizeof (e_note
.descsz
));
5352 md_number_to_chars (p
, (valueT
) i_note
.descsz
, sizeof (e_note
.descsz
));
5353 p
= frag_more (sizeof (e_note
.type
));
5354 md_number_to_chars (p
, (valueT
) i_note
.type
, sizeof (e_note
.type
));
5355 p
= frag_more (len
+ 1);
5356 strcpy (p
, cpu_arch_name
);
5358 frag_align (2, 0, 0);
5360 subseg_set (seg
, subseg
);
5366 md_undefined_symbol (name
)
5369 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
5370 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
5371 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
5372 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
5376 if (symbol_find (name
))
5377 as_bad (_("GOT already in symbol table"));
5378 GOT_symbol
= symbol_new (name
, undefined_section
,
5379 (valueT
) 0, &zero_address_frag
);
5386 /* Round up a section size to the appropriate boundary. */
5389 md_section_align (segment
, size
)
5390 segT segment ATTRIBUTE_UNUSED
;
5393 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
5394 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
5396 /* For a.out, force the section size to be aligned. If we don't do
5397 this, BFD will align it for us, but it will not write out the
5398 final bytes of the section. This may be a bug in BFD, but it is
5399 easier to fix it here since that is how the other a.out targets
5403 align
= bfd_get_section_alignment (stdoutput
, segment
);
5404 size
= ((size
+ (1 << align
) - 1) & ((valueT
) -1 << align
));
5411 /* On the i386, PC-relative offsets are relative to the start of the
5412 next instruction. That is, the address of the offset, plus its
5413 size, since the offset is always the last part of the insn. */
5416 md_pcrel_from (fixP
)
5419 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
5426 int ignore ATTRIBUTE_UNUSED
;
5430 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5432 obj_elf_section_change_hook ();
5434 temp
= get_absolute_expression ();
5435 subseg_set (bss_section
, (subsegT
) temp
);
5436 demand_empty_rest_of_line ();
5442 i386_validate_fix (fixp
)
5445 if (fixp
->fx_subsy
&& fixp
->fx_subsy
== GOT_symbol
)
5447 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
5449 if (flag_code
!= CODE_64BIT
)
5451 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
5455 if (flag_code
!= CODE_64BIT
)
5456 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
5458 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
5465 tc_gen_reloc (section
, fixp
)
5466 asection
*section ATTRIBUTE_UNUSED
;
5470 bfd_reloc_code_real_type code
;
5472 switch (fixp
->fx_r_type
)
5474 case BFD_RELOC_X86_64_PLT32
:
5475 case BFD_RELOC_X86_64_GOT32
:
5476 case BFD_RELOC_X86_64_GOTPCREL
:
5477 case BFD_RELOC_386_PLT32
:
5478 case BFD_RELOC_386_GOT32
:
5479 case BFD_RELOC_386_GOTOFF
:
5480 case BFD_RELOC_386_GOTPC
:
5481 case BFD_RELOC_386_TLS_GD
:
5482 case BFD_RELOC_386_TLS_LDM
:
5483 case BFD_RELOC_386_TLS_LDO_32
:
5484 case BFD_RELOC_386_TLS_IE_32
:
5485 case BFD_RELOC_386_TLS_IE
:
5486 case BFD_RELOC_386_TLS_GOTIE
:
5487 case BFD_RELOC_386_TLS_LE_32
:
5488 case BFD_RELOC_386_TLS_LE
:
5489 case BFD_RELOC_X86_64_TLSGD
:
5490 case BFD_RELOC_X86_64_TLSLD
:
5491 case BFD_RELOC_X86_64_DTPOFF32
:
5492 case BFD_RELOC_X86_64_DTPOFF64
:
5493 case BFD_RELOC_X86_64_GOTTPOFF
:
5494 case BFD_RELOC_X86_64_TPOFF32
:
5495 case BFD_RELOC_X86_64_TPOFF64
:
5496 case BFD_RELOC_X86_64_GOTOFF64
:
5497 case BFD_RELOC_X86_64_GOTPC32
:
5499 case BFD_RELOC_VTABLE_ENTRY
:
5500 case BFD_RELOC_VTABLE_INHERIT
:
5502 case BFD_RELOC_32_SECREL
:
5504 code
= fixp
->fx_r_type
;
5506 case BFD_RELOC_X86_64_32S
:
5507 if (!fixp
->fx_pcrel
)
5509 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
5510 code
= fixp
->fx_r_type
;
5516 switch (fixp
->fx_size
)
5519 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
5520 _("can not do %d byte pc-relative relocation"),
5522 code
= BFD_RELOC_32_PCREL
;
5524 case 1: code
= BFD_RELOC_8_PCREL
; break;
5525 case 2: code
= BFD_RELOC_16_PCREL
; break;
5526 case 4: code
= BFD_RELOC_32_PCREL
; break;
5528 case 8: code
= BFD_RELOC_64_PCREL
; break;
5534 switch (fixp
->fx_size
)
5537 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
5538 _("can not do %d byte relocation"),
5540 code
= BFD_RELOC_32
;
5542 case 1: code
= BFD_RELOC_8
; break;
5543 case 2: code
= BFD_RELOC_16
; break;
5544 case 4: code
= BFD_RELOC_32
; break;
5546 case 8: code
= BFD_RELOC_64
; break;
5553 if ((code
== BFD_RELOC_32
|| code
== BFD_RELOC_32_PCREL
)
5555 && fixp
->fx_addsy
== GOT_symbol
)
5557 if (flag_code
!= CODE_64BIT
)
5558 code
= BFD_RELOC_386_GOTPC
;
5560 code
= BFD_RELOC_X86_64_GOTPC32
;
5563 rel
= (arelent
*) xmalloc (sizeof (arelent
));
5564 rel
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
5565 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
5567 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
5569 if (!use_rela_relocations
)
5571 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
5572 vtable entry to be used in the relocation's section offset. */
5573 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
5574 rel
->address
= fixp
->fx_offset
;
5578 /* Use the rela in 64bit mode. */
5581 if (!fixp
->fx_pcrel
)
5582 rel
->addend
= fixp
->fx_offset
;
5586 case BFD_RELOC_X86_64_PLT32
:
5587 case BFD_RELOC_X86_64_GOT32
:
5588 case BFD_RELOC_X86_64_GOTPCREL
:
5589 case BFD_RELOC_X86_64_TLSGD
:
5590 case BFD_RELOC_X86_64_TLSLD
:
5591 case BFD_RELOC_X86_64_GOTTPOFF
:
5592 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
5595 rel
->addend
= (section
->vma
5597 + fixp
->fx_addnumber
5598 + md_pcrel_from (fixp
));
5603 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
5604 if (rel
->howto
== NULL
)
5606 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
5607 _("cannot represent relocation type %s"),
5608 bfd_get_reloc_code_name (code
));
5609 /* Set howto to a garbage value so that we can keep going. */
5610 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
5611 assert (rel
->howto
!= NULL
);
5618 /* Parse operands using Intel syntax. This implements a recursive descent
5619 parser based on the BNF grammar published in Appendix B of the MASM 6.1
5622 FIXME: We do not recognize the full operand grammar defined in the MASM
5623 documentation. In particular, all the structure/union and
5624 high-level macro operands are missing.
5626 Uppercase words are terminals, lower case words are non-terminals.
5627 Objects surrounded by double brackets '[[' ']]' are optional. Vertical
5628 bars '|' denote choices. Most grammar productions are implemented in
5629 functions called 'intel_<production>'.
5631 Initial production is 'expr'.
5637 binOp & | AND | \| | OR | ^ | XOR
5639 byteRegister AL | AH | BL | BH | CL | CH | DL | DH
5641 constant digits [[ radixOverride ]]
5643 dataType BYTE | WORD | DWORD | FWORD | QWORD | TBYTE | OWORD | XMMWORD
5681 => expr expr cmpOp e04
5684 gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX
5685 | BP | EBP | SP | ESP | DI | EDI | SI | ESI
5687 hexdigit a | b | c | d | e | f
5688 | A | B | C | D | E | F
5694 mulOp * | / | % | MOD | << | SHL | >> | SHR
5698 register specialRegister
5702 segmentRegister CS | DS | ES | FS | GS | SS
5704 specialRegister CR0 | CR2 | CR3 | CR4
5705 | DR0 | DR1 | DR2 | DR3 | DR6 | DR7
5706 | TR3 | TR4 | TR5 | TR6 | TR7
5708 We simplify the grammar in obvious places (e.g., register parsing is
5709 done by calling parse_register) and eliminate immediate left recursion
5710 to implement a recursive-descent parser.
5714 expr' cmpOp e04 expr'
5765 /* Parsing structure for the intel syntax parser. Used to implement the
5766 semantic actions for the operand grammar. */
5767 struct intel_parser_s
5769 char *op_string
; /* The string being parsed. */
5770 int got_a_float
; /* Whether the operand is a float. */
5771 int op_modifier
; /* Operand modifier. */
5772 int is_mem
; /* 1 if operand is memory reference. */
5773 int in_offset
; /* >=1 if parsing operand of offset. */
5774 int in_bracket
; /* >=1 if parsing operand in brackets. */
5775 const reg_entry
*reg
; /* Last register reference found. */
5776 char *disp
; /* Displacement string being built. */
5777 char *next_operand
; /* Resume point when splitting operands. */
5780 static struct intel_parser_s intel_parser
;
5782 /* Token structure for parsing intel syntax. */
5785 int code
; /* Token code. */
5786 const reg_entry
*reg
; /* Register entry for register tokens. */
5787 char *str
; /* String representation. */
5790 static struct intel_token cur_token
, prev_token
;
5792 /* Token codes for the intel parser. Since T_SHORT is already used
5793 by COFF, undefine it first to prevent a warning. */
5812 /* Prototypes for intel parser functions. */
5813 static int intel_match_token
PARAMS ((int code
));
5814 static void intel_get_token
PARAMS ((void));
5815 static void intel_putback_token
PARAMS ((void));
5816 static int intel_expr
PARAMS ((void));
5817 static int intel_e04
PARAMS ((void));
5818 static int intel_e05
PARAMS ((void));
5819 static int intel_e06
PARAMS ((void));
5820 static int intel_e09
PARAMS ((void));
5821 static int intel_bracket_expr
PARAMS ((void));
5822 static int intel_e10
PARAMS ((void));
5823 static int intel_e11
PARAMS ((void));
5826 i386_intel_operand (operand_string
, got_a_float
)
5827 char *operand_string
;
5833 p
= intel_parser
.op_string
= xstrdup (operand_string
);
5834 intel_parser
.disp
= (char *) xmalloc (strlen (operand_string
) + 1);
5838 /* Initialize token holders. */
5839 cur_token
.code
= prev_token
.code
= T_NIL
;
5840 cur_token
.reg
= prev_token
.reg
= NULL
;
5841 cur_token
.str
= prev_token
.str
= NULL
;
5843 /* Initialize parser structure. */
5844 intel_parser
.got_a_float
= got_a_float
;
5845 intel_parser
.op_modifier
= 0;
5846 intel_parser
.is_mem
= 0;
5847 intel_parser
.in_offset
= 0;
5848 intel_parser
.in_bracket
= 0;
5849 intel_parser
.reg
= NULL
;
5850 intel_parser
.disp
[0] = '\0';
5851 intel_parser
.next_operand
= NULL
;
5853 /* Read the first token and start the parser. */
5855 ret
= intel_expr ();
5860 if (cur_token
.code
!= T_NIL
)
5862 as_bad (_("invalid operand for '%s' ('%s' unexpected)"),
5863 current_templates
->start
->name
, cur_token
.str
);
5866 /* If we found a memory reference, hand it over to i386_displacement
5867 to fill in the rest of the operand fields. */
5868 else if (intel_parser
.is_mem
)
5870 if ((i
.mem_operands
== 1
5871 && (current_templates
->start
->opcode_modifier
& IsString
) == 0)
5872 || i
.mem_operands
== 2)
5874 as_bad (_("too many memory references for '%s'"),
5875 current_templates
->start
->name
);
5880 char *s
= intel_parser
.disp
;
5883 if (!quiet_warnings
&& intel_parser
.is_mem
< 0)
5884 /* See the comments in intel_bracket_expr. */
5885 as_warn (_("Treating `%s' as memory reference"), operand_string
);
5887 /* Add the displacement expression. */
5889 ret
= i386_displacement (s
, s
+ strlen (s
));
5892 /* Swap base and index in 16-bit memory operands like
5893 [si+bx]. Since i386_index_check is also used in AT&T
5894 mode we have to do that here. */
5897 && (i
.base_reg
->reg_type
& Reg16
)
5898 && (i
.index_reg
->reg_type
& Reg16
)
5899 && i
.base_reg
->reg_num
>= 6
5900 && i
.index_reg
->reg_num
< 6)
5902 const reg_entry
*base
= i
.index_reg
;
5904 i
.index_reg
= i
.base_reg
;
5907 ret
= i386_index_check (operand_string
);
5912 /* Constant and OFFSET expressions are handled by i386_immediate. */
5913 else if ((intel_parser
.op_modifier
& (1 << T_OFFSET
))
5914 || intel_parser
.reg
== NULL
)
5915 ret
= i386_immediate (intel_parser
.disp
);
5917 if (intel_parser
.next_operand
&& this_operand
>= MAX_OPERANDS
- 1)
5919 if (!ret
|| !intel_parser
.next_operand
)
5921 intel_parser
.op_string
= intel_parser
.next_operand
;
5922 this_operand
= i
.operands
++;
5926 free (intel_parser
.disp
);
5931 #define NUM_ADDRESS_REGS (!!i.base_reg + !!i.index_reg)
5935 expr' cmpOp e04 expr'
5940 /* XXX Implement the comparison operators. */
5941 return intel_e04 ();
5958 if (nregs
>= 0 && NUM_ADDRESS_REGS
> nregs
)
5959 i
.base_reg
= i386_regtab
+ REGNAM_AL
; /* al is invalid as base */
5961 if (cur_token
.code
== '+')
5963 else if (cur_token
.code
== '-')
5964 nregs
= NUM_ADDRESS_REGS
;
5968 strcat (intel_parser
.disp
, cur_token
.str
);
5969 intel_match_token (cur_token
.code
);
5980 int nregs
= ~NUM_ADDRESS_REGS
;
5987 if (cur_token
.code
== '&' || cur_token
.code
== '|' || cur_token
.code
== '^')
5991 str
[0] = cur_token
.code
;
5993 strcat (intel_parser
.disp
, str
);
5998 intel_match_token (cur_token
.code
);
6003 if (nregs
>= 0 && NUM_ADDRESS_REGS
> nregs
)
6004 i
.base_reg
= i386_regtab
+ REGNAM_AL
+ 1; /* cl is invalid as base */
6015 int nregs
= ~NUM_ADDRESS_REGS
;
6022 if (cur_token
.code
== '*' || cur_token
.code
== '/' || cur_token
.code
== '%')
6026 str
[0] = cur_token
.code
;
6028 strcat (intel_parser
.disp
, str
);
6030 else if (cur_token
.code
== T_SHL
)
6031 strcat (intel_parser
.disp
, "<<");
6032 else if (cur_token
.code
== T_SHR
)
6033 strcat (intel_parser
.disp
, ">>");
6037 intel_match_token (cur_token
.code
);
6042 if (nregs
>= 0 && NUM_ADDRESS_REGS
> nregs
)
6043 i
.base_reg
= i386_regtab
+ REGNAM_AL
+ 2; /* dl is invalid as base */
6061 int nregs
= ~NUM_ADDRESS_REGS
;
6066 /* Don't consume constants here. */
6067 if (cur_token
.code
== '+' || cur_token
.code
== '-')
6069 /* Need to look one token ahead - if the next token
6070 is a constant, the current token is its sign. */
6073 intel_match_token (cur_token
.code
);
6074 next_code
= cur_token
.code
;
6075 intel_putback_token ();
6076 if (next_code
== T_CONST
)
6080 /* e09 OFFSET e09 */
6081 if (cur_token
.code
== T_OFFSET
)
6084 ++intel_parser
.in_offset
;
6088 else if (cur_token
.code
== T_SHORT
)
6089 intel_parser
.op_modifier
|= 1 << T_SHORT
;
6092 else if (cur_token
.code
== '+')
6093 strcat (intel_parser
.disp
, "+");
6098 else if (cur_token
.code
== '-' || cur_token
.code
== '~')
6104 str
[0] = cur_token
.code
;
6106 strcat (intel_parser
.disp
, str
);
6113 intel_match_token (cur_token
.code
);
6121 /* e09' PTR e10 e09' */
6122 if (cur_token
.code
== T_PTR
)
6126 if (prev_token
.code
== T_BYTE
)
6127 suffix
= BYTE_MNEM_SUFFIX
;
6129 else if (prev_token
.code
== T_WORD
)
6131 if (current_templates
->start
->name
[0] == 'l'
6132 && current_templates
->start
->name
[2] == 's'
6133 && current_templates
->start
->name
[3] == 0)
6134 suffix
= BYTE_MNEM_SUFFIX
; /* so it will cause an error */
6135 else if (intel_parser
.got_a_float
== 2) /* "fi..." */
6136 suffix
= SHORT_MNEM_SUFFIX
;
6138 suffix
= WORD_MNEM_SUFFIX
;
6141 else if (prev_token
.code
== T_DWORD
)
6143 if (current_templates
->start
->name
[0] == 'l'
6144 && current_templates
->start
->name
[2] == 's'
6145 && current_templates
->start
->name
[3] == 0)
6146 suffix
= WORD_MNEM_SUFFIX
;
6147 else if (flag_code
== CODE_16BIT
6148 && (current_templates
->start
->opcode_modifier
6149 & (Jump
|JumpDword
|JumpInterSegment
)))
6150 suffix
= LONG_DOUBLE_MNEM_SUFFIX
;
6151 else if (intel_parser
.got_a_float
== 1) /* "f..." */
6152 suffix
= SHORT_MNEM_SUFFIX
;
6154 suffix
= LONG_MNEM_SUFFIX
;
6157 else if (prev_token
.code
== T_FWORD
)
6159 if (current_templates
->start
->name
[0] == 'l'
6160 && current_templates
->start
->name
[2] == 's'
6161 && current_templates
->start
->name
[3] == 0)
6162 suffix
= LONG_MNEM_SUFFIX
;
6163 else if (!intel_parser
.got_a_float
)
6165 if (flag_code
== CODE_16BIT
)
6166 add_prefix (DATA_PREFIX_OPCODE
);
6167 suffix
= LONG_DOUBLE_MNEM_SUFFIX
;
6170 suffix
= BYTE_MNEM_SUFFIX
; /* so it will cause an error */
6173 else if (prev_token
.code
== T_QWORD
)
6175 if (intel_parser
.got_a_float
== 1) /* "f..." */
6176 suffix
= LONG_MNEM_SUFFIX
;
6178 suffix
= QWORD_MNEM_SUFFIX
;
6181 else if (prev_token
.code
== T_TBYTE
)
6183 if (intel_parser
.got_a_float
== 1)
6184 suffix
= LONG_DOUBLE_MNEM_SUFFIX
;
6186 suffix
= BYTE_MNEM_SUFFIX
; /* so it will cause an error */
6189 else if (prev_token
.code
== T_XMMWORD
)
6191 /* XXX ignored for now, but accepted since gcc uses it */
6197 as_bad (_("Unknown operand modifier `%s'"), prev_token
.str
);
6201 if (current_templates
->start
->base_opcode
== 0x8d /* lea */)
6205 else if (i
.suffix
!= suffix
)
6207 as_bad (_("Conflicting operand modifiers"));
6213 /* e09' : e10 e09' */
6214 else if (cur_token
.code
== ':')
6216 if (prev_token
.code
!= T_REG
)
6218 /* While {call,jmp} SSSS:OOOO is MASM syntax only when SSSS is a
6219 segment/group identifier (which we don't have), using comma
6220 as the operand separator there is even less consistent, since
6221 there all branches only have a single operand. */
6222 if (this_operand
!= 0
6223 || intel_parser
.in_offset
6224 || intel_parser
.in_bracket
6225 || (!(current_templates
->start
->opcode_modifier
6226 & (Jump
|JumpDword
|JumpInterSegment
))
6227 && !(current_templates
->start
->operand_types
[0]
6229 return intel_match_token (T_NIL
);
6230 /* Remember the start of the 2nd operand and terminate 1st
6232 XXX This isn't right, yet (when SSSS:OOOO is right operand of
6233 another expression), but it gets at least the simplest case
6234 (a plain number or symbol on the left side) right. */
6235 intel_parser
.next_operand
= intel_parser
.op_string
;
6236 *--intel_parser
.op_string
= '\0';
6237 return intel_match_token (':');
6245 intel_match_token (cur_token
.code
);
6251 --intel_parser
.in_offset
;
6254 if (NUM_ADDRESS_REGS
> nregs
)
6256 as_bad (_("Invalid operand to `OFFSET'"));
6259 intel_parser
.op_modifier
|= 1 << T_OFFSET
;
6262 if (nregs
>= 0 && NUM_ADDRESS_REGS
> nregs
)
6263 i
.base_reg
= i386_regtab
+ REGNAM_AL
+ 3; /* bl is invalid as base */
6268 intel_bracket_expr ()
6270 int was_offset
= intel_parser
.op_modifier
& (1 << T_OFFSET
);
6271 const char *start
= intel_parser
.op_string
;
6274 if (i
.op
[this_operand
].regs
)
6275 return intel_match_token (T_NIL
);
6277 intel_match_token ('[');
6279 /* Mark as a memory operand only if it's not already known to be an
6280 offset expression. If it's an offset expression, we need to keep
6282 if (!intel_parser
.in_offset
)
6284 ++intel_parser
.in_bracket
;
6285 /* Unfortunately gas always diverged from MASM in a respect that can't
6286 be easily fixed without risking to break code sequences likely to be
6287 encountered (the testsuite even check for this): MASM doesn't consider
6288 an expression inside brackets unconditionally as a memory reference.
6289 When that is e.g. a constant, an offset expression, or the sum of the
6290 two, this is still taken as a constant load. gas, however, always
6291 treated these as memory references. As a compromise, we'll try to make
6292 offset expressions inside brackets work the MASM way (since that's
6293 less likely to be found in real world code), but make constants alone
6294 continue to work the traditional gas way. In either case, issue a
6296 intel_parser
.op_modifier
&= ~was_offset
;
6299 strcat (intel_parser
.disp
, "[");
6301 /* Add a '+' to the displacement string if necessary. */
6302 if (*intel_parser
.disp
!= '\0'
6303 && *(intel_parser
.disp
+ strlen (intel_parser
.disp
) - 1) != '+')
6304 strcat (intel_parser
.disp
, "+");
6307 && (len
= intel_parser
.op_string
- start
- 1,
6308 intel_match_token (']')))
6310 /* Preserve brackets when the operand is an offset expression. */
6311 if (intel_parser
.in_offset
)
6312 strcat (intel_parser
.disp
, "]");
6315 --intel_parser
.in_bracket
;
6316 if (i
.base_reg
|| i
.index_reg
)
6317 intel_parser
.is_mem
= 1;
6318 if (!intel_parser
.is_mem
)
6320 if (!(intel_parser
.op_modifier
& (1 << T_OFFSET
)))
6321 /* Defer the warning until all of the operand was parsed. */
6322 intel_parser
.is_mem
= -1;
6323 else if (!quiet_warnings
)
6324 as_warn (_("`[%.*s]' taken to mean just `%.*s'"), len
, start
, len
, start
);
6327 intel_parser
.op_modifier
|= was_offset
;
6344 while (cur_token
.code
== '[')
6346 if (!intel_bracket_expr ())
6371 switch (cur_token
.code
)
6375 intel_match_token ('(');
6376 strcat (intel_parser
.disp
, "(");
6378 if (intel_expr () && intel_match_token (')'))
6380 strcat (intel_parser
.disp
, ")");
6387 /* Operands for jump/call inside brackets denote absolute addresses.
6388 XXX This shouldn't be needed anymore (or if it should rather live
6389 in intel_bracket_expr). */
6390 if (current_templates
->start
->opcode_modifier
6391 & (Jump
|JumpDword
|JumpByte
|JumpInterSegment
))
6392 i
.types
[this_operand
] |= JumpAbsolute
;
6394 return intel_bracket_expr ();
6399 strcat (intel_parser
.disp
, cur_token
.str
);
6400 intel_match_token (cur_token
.code
);
6402 /* Mark as a memory operand only if it's not already known to be an
6403 offset expression. */
6404 if (!intel_parser
.in_offset
)
6405 intel_parser
.is_mem
= 1;
6412 const reg_entry
*reg
= intel_parser
.reg
= cur_token
.reg
;
6414 intel_match_token (T_REG
);
6416 /* Check for segment change. */
6417 if (cur_token
.code
== ':')
6419 if (!(reg
->reg_type
& (SReg2
| SReg3
)))
6421 as_bad (_("`%s' is not a valid segment register"), reg
->reg_name
);
6424 else if (i
.seg
[i
.mem_operands
])
6425 as_warn (_("Extra segment override ignored"));
6428 if (!intel_parser
.in_offset
)
6429 intel_parser
.is_mem
= 1;
6430 switch (reg
->reg_num
)
6433 i
.seg
[i
.mem_operands
] = &es
;
6436 i
.seg
[i
.mem_operands
] = &cs
;
6439 i
.seg
[i
.mem_operands
] = &ss
;
6442 i
.seg
[i
.mem_operands
] = &ds
;
6445 i
.seg
[i
.mem_operands
] = &fs
;
6448 i
.seg
[i
.mem_operands
] = &gs
;
6454 /* Not a segment register. Check for register scaling. */
6455 else if (cur_token
.code
== '*')
6457 if (!intel_parser
.in_bracket
)
6459 as_bad (_("Register scaling only allowed in memory operands"));
6463 if (reg
->reg_type
& Reg16
) /* Disallow things like [si*1]. */
6464 reg
= i386_regtab
+ REGNAM_AX
+ 4; /* sp is invalid as index */
6465 else if (i
.index_reg
)
6466 reg
= i386_regtab
+ REGNAM_EAX
+ 4; /* esp is invalid as index */
6468 /* What follows must be a valid scale. */
6469 intel_match_token ('*');
6471 i
.types
[this_operand
] |= BaseIndex
;
6473 /* Set the scale after setting the register (otherwise,
6474 i386_scale will complain) */
6475 if (cur_token
.code
== '+' || cur_token
.code
== '-')
6477 char *str
, sign
= cur_token
.code
;
6478 intel_match_token (cur_token
.code
);
6479 if (cur_token
.code
!= T_CONST
)
6481 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
6485 str
= (char *) xmalloc (strlen (cur_token
.str
) + 2);
6486 strcpy (str
+ 1, cur_token
.str
);
6488 if (!i386_scale (str
))
6492 else if (!i386_scale (cur_token
.str
))
6494 intel_match_token (cur_token
.code
);
6497 /* No scaling. If this is a memory operand, the register is either a
6498 base register (first occurrence) or an index register (second
6500 else if (intel_parser
.in_bracket
&& !(reg
->reg_type
& (SReg2
| SReg3
)))
6505 else if (!i
.index_reg
)
6509 as_bad (_("Too many register references in memory operand"));
6513 i
.types
[this_operand
] |= BaseIndex
;
6516 /* Offset modifier. Add the register to the displacement string to be
6517 parsed as an immediate expression after we're done. */
6518 else if (intel_parser
.in_offset
)
6520 as_warn (_("Using register names in OFFSET expressions is deprecated"));
6521 strcat (intel_parser
.disp
, reg
->reg_name
);
6524 /* It's neither base nor index nor offset. */
6525 else if (!intel_parser
.is_mem
)
6527 i
.types
[this_operand
] |= reg
->reg_type
& ~BaseIndex
;
6528 i
.op
[this_operand
].regs
= reg
;
6533 as_bad (_("Invalid use of register"));
6537 /* Since registers are not part of the displacement string (except
6538 when we're parsing offset operands), we may need to remove any
6539 preceding '+' from the displacement string. */
6540 if (*intel_parser
.disp
!= '\0'
6541 && !intel_parser
.in_offset
)
6543 char *s
= intel_parser
.disp
;
6544 s
+= strlen (s
) - 1;
6567 intel_match_token (cur_token
.code
);
6569 if (cur_token
.code
== T_PTR
)
6572 /* It must have been an identifier. */
6573 intel_putback_token ();
6574 cur_token
.code
= T_ID
;
6580 if (!intel_parser
.in_offset
&& intel_parser
.is_mem
<= 0)
6584 /* The identifier represents a memory reference only if it's not
6585 preceded by an offset modifier and if it's not an equate. */
6586 symbolP
= symbol_find(cur_token
.str
);
6587 if (!symbolP
|| S_GET_SEGMENT(symbolP
) != absolute_section
)
6588 intel_parser
.is_mem
= 1;
6596 char *save_str
, sign
= 0;
6598 /* Allow constants that start with `+' or `-'. */
6599 if (cur_token
.code
== '-' || cur_token
.code
== '+')
6601 sign
= cur_token
.code
;
6602 intel_match_token (cur_token
.code
);
6603 if (cur_token
.code
!= T_CONST
)
6605 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
6611 save_str
= (char *) xmalloc (strlen (cur_token
.str
) + 2);
6612 strcpy (save_str
+ !!sign
, cur_token
.str
);
6616 /* Get the next token to check for register scaling. */
6617 intel_match_token (cur_token
.code
);
6619 /* Check if this constant is a scaling factor for an index register. */
6620 if (cur_token
.code
== '*')
6622 if (intel_match_token ('*') && cur_token
.code
== T_REG
)
6624 const reg_entry
*reg
= cur_token
.reg
;
6626 if (!intel_parser
.in_bracket
)
6628 as_bad (_("Register scaling only allowed in memory operands"));
6632 if (reg
->reg_type
& Reg16
) /* Disallow things like [1*si]. */
6633 reg
= i386_regtab
+ REGNAM_AX
+ 4; /* sp is invalid as index */
6634 else if (i
.index_reg
)
6635 reg
= i386_regtab
+ REGNAM_EAX
+ 4; /* esp is invalid as index */
6637 /* The constant is followed by `* reg', so it must be
6640 i
.types
[this_operand
] |= BaseIndex
;
6642 /* Set the scale after setting the register (otherwise,
6643 i386_scale will complain) */
6644 if (!i386_scale (save_str
))
6646 intel_match_token (T_REG
);
6648 /* Since registers are not part of the displacement
6649 string, we may need to remove any preceding '+' from
6650 the displacement string. */
6651 if (*intel_parser
.disp
!= '\0')
6653 char *s
= intel_parser
.disp
;
6654 s
+= strlen (s
) - 1;
6664 /* The constant was not used for register scaling. Since we have
6665 already consumed the token following `*' we now need to put it
6666 back in the stream. */
6667 intel_putback_token ();
6670 /* Add the constant to the displacement string. */
6671 strcat (intel_parser
.disp
, save_str
);
6678 as_bad (_("Unrecognized token '%s'"), cur_token
.str
);
6682 /* Match the given token against cur_token. If they match, read the next
6683 token from the operand string. */
6685 intel_match_token (code
)
6688 if (cur_token
.code
== code
)
6695 as_bad (_("Unexpected token `%s'"), cur_token
.str
);
6700 /* Read a new token from intel_parser.op_string and store it in cur_token. */
6705 const reg_entry
*reg
;
6706 struct intel_token new_token
;
6708 new_token
.code
= T_NIL
;
6709 new_token
.reg
= NULL
;
6710 new_token
.str
= NULL
;
6712 /* Free the memory allocated to the previous token and move
6713 cur_token to prev_token. */
6715 free (prev_token
.str
);
6717 prev_token
= cur_token
;
6719 /* Skip whitespace. */
6720 while (is_space_char (*intel_parser
.op_string
))
6721 intel_parser
.op_string
++;
6723 /* Return an empty token if we find nothing else on the line. */
6724 if (*intel_parser
.op_string
== '\0')
6726 cur_token
= new_token
;
6730 /* The new token cannot be larger than the remainder of the operand
6732 new_token
.str
= (char *) xmalloc (strlen (intel_parser
.op_string
) + 1);
6733 new_token
.str
[0] = '\0';
6735 if (strchr ("0123456789", *intel_parser
.op_string
))
6737 char *p
= new_token
.str
;
6738 char *q
= intel_parser
.op_string
;
6739 new_token
.code
= T_CONST
;
6741 /* Allow any kind of identifier char to encompass floating point and
6742 hexadecimal numbers. */
6743 while (is_identifier_char (*q
))
6747 /* Recognize special symbol names [0-9][bf]. */
6748 if (strlen (intel_parser
.op_string
) == 2
6749 && (intel_parser
.op_string
[1] == 'b'
6750 || intel_parser
.op_string
[1] == 'f'))
6751 new_token
.code
= T_ID
;
6754 else if ((*intel_parser
.op_string
== REGISTER_PREFIX
|| allow_naked_reg
)
6755 && ((reg
= parse_register (intel_parser
.op_string
, &end_op
)) != NULL
))
6757 new_token
.code
= T_REG
;
6758 new_token
.reg
= reg
;
6760 if (*intel_parser
.op_string
== REGISTER_PREFIX
)
6762 new_token
.str
[0] = REGISTER_PREFIX
;
6763 new_token
.str
[1] = '\0';
6766 strcat (new_token
.str
, reg
->reg_name
);
6769 else if (is_identifier_char (*intel_parser
.op_string
))
6771 char *p
= new_token
.str
;
6772 char *q
= intel_parser
.op_string
;
6774 /* A '.' or '$' followed by an identifier char is an identifier.
6775 Otherwise, it's operator '.' followed by an expression. */
6776 if ((*q
== '.' || *q
== '$') && !is_identifier_char (*(q
+ 1)))
6778 new_token
.code
= '.';
6779 new_token
.str
[0] = '.';
6780 new_token
.str
[1] = '\0';
6784 while (is_identifier_char (*q
) || *q
== '@')
6788 if (strcasecmp (new_token
.str
, "NOT") == 0)
6789 new_token
.code
= '~';
6791 else if (strcasecmp (new_token
.str
, "MOD") == 0)
6792 new_token
.code
= '%';
6794 else if (strcasecmp (new_token
.str
, "AND") == 0)
6795 new_token
.code
= '&';
6797 else if (strcasecmp (new_token
.str
, "OR") == 0)
6798 new_token
.code
= '|';
6800 else if (strcasecmp (new_token
.str
, "XOR") == 0)
6801 new_token
.code
= '^';
6803 else if (strcasecmp (new_token
.str
, "SHL") == 0)
6804 new_token
.code
= T_SHL
;
6806 else if (strcasecmp (new_token
.str
, "SHR") == 0)
6807 new_token
.code
= T_SHR
;
6809 else if (strcasecmp (new_token
.str
, "BYTE") == 0)
6810 new_token
.code
= T_BYTE
;
6812 else if (strcasecmp (new_token
.str
, "WORD") == 0)
6813 new_token
.code
= T_WORD
;
6815 else if (strcasecmp (new_token
.str
, "DWORD") == 0)
6816 new_token
.code
= T_DWORD
;
6818 else if (strcasecmp (new_token
.str
, "FWORD") == 0)
6819 new_token
.code
= T_FWORD
;
6821 else if (strcasecmp (new_token
.str
, "QWORD") == 0)
6822 new_token
.code
= T_QWORD
;
6824 else if (strcasecmp (new_token
.str
, "TBYTE") == 0
6825 /* XXX remove (gcc still uses it) */
6826 || strcasecmp (new_token
.str
, "XWORD") == 0)
6827 new_token
.code
= T_TBYTE
;
6829 else if (strcasecmp (new_token
.str
, "XMMWORD") == 0
6830 || strcasecmp (new_token
.str
, "OWORD") == 0)
6831 new_token
.code
= T_XMMWORD
;
6833 else if (strcasecmp (new_token
.str
, "PTR") == 0)
6834 new_token
.code
= T_PTR
;
6836 else if (strcasecmp (new_token
.str
, "SHORT") == 0)
6837 new_token
.code
= T_SHORT
;
6839 else if (strcasecmp (new_token
.str
, "OFFSET") == 0)
6841 new_token
.code
= T_OFFSET
;
6843 /* ??? This is not mentioned in the MASM grammar but gcc
6844 makes use of it with -mintel-syntax. OFFSET may be
6845 followed by FLAT: */
6846 if (strncasecmp (q
, " FLAT:", 6) == 0)
6847 strcat (new_token
.str
, " FLAT:");
6850 /* ??? This is not mentioned in the MASM grammar. */
6851 else if (strcasecmp (new_token
.str
, "FLAT") == 0)
6853 new_token
.code
= T_OFFSET
;
6855 strcat (new_token
.str
, ":");
6857 as_bad (_("`:' expected"));
6861 new_token
.code
= T_ID
;
6865 else if (strchr ("+-/*%|&^:[]()~", *intel_parser
.op_string
))
6867 new_token
.code
= *intel_parser
.op_string
;
6868 new_token
.str
[0] = *intel_parser
.op_string
;
6869 new_token
.str
[1] = '\0';
6872 else if (strchr ("<>", *intel_parser
.op_string
)
6873 && *intel_parser
.op_string
== *(intel_parser
.op_string
+ 1))
6875 new_token
.code
= *intel_parser
.op_string
== '<' ? T_SHL
: T_SHR
;
6876 new_token
.str
[0] = *intel_parser
.op_string
;
6877 new_token
.str
[1] = *intel_parser
.op_string
;
6878 new_token
.str
[2] = '\0';
6882 as_bad (_("Unrecognized token `%s'"), intel_parser
.op_string
);
6884 intel_parser
.op_string
+= strlen (new_token
.str
);
6885 cur_token
= new_token
;
6888 /* Put cur_token back into the token stream and make cur_token point to
6891 intel_putback_token ()
6893 if (cur_token
.code
!= T_NIL
)
6895 intel_parser
.op_string
-= strlen (cur_token
.str
);
6896 free (cur_token
.str
);
6898 cur_token
= prev_token
;
6900 /* Forget prev_token. */
6901 prev_token
.code
= T_NIL
;
6902 prev_token
.reg
= NULL
;
6903 prev_token
.str
= NULL
;
6907 tc_x86_regname_to_dw2regnum (const char *regname
)
6909 unsigned int regnum
;
6910 unsigned int regnames_count
;
6911 static const char *const regnames_32
[] =
6913 "eax", "ecx", "edx", "ebx",
6914 "esp", "ebp", "esi", "edi",
6915 "eip", "eflags", NULL
,
6916 "st0", "st1", "st2", "st3",
6917 "st4", "st5", "st6", "st7",
6919 "xmm0", "xmm1", "xmm2", "xmm3",
6920 "xmm4", "xmm5", "xmm6", "xmm7",
6921 "mm0", "mm1", "mm2", "mm3",
6922 "mm4", "mm5", "mm6", "mm7"
6924 static const char *const regnames_64
[] =
6926 "rax", "rdx", "rcx", "rbx",
6927 "rsi", "rdi", "rbp", "rsp",
6928 "r8", "r9", "r10", "r11",
6929 "r12", "r13", "r14", "r15",
6931 "xmm0", "xmm1", "xmm2", "xmm3",
6932 "xmm4", "xmm5", "xmm6", "xmm7",
6933 "xmm8", "xmm9", "xmm10", "xmm11",
6934 "xmm12", "xmm13", "xmm14", "xmm15",
6935 "st0", "st1", "st2", "st3",
6936 "st4", "st5", "st6", "st7",
6937 "mm0", "mm1", "mm2", "mm3",
6938 "mm4", "mm5", "mm6", "mm7"
6940 const char *const *regnames
;
6942 if (flag_code
== CODE_64BIT
)
6944 regnames
= regnames_64
;
6945 regnames_count
= ARRAY_SIZE (regnames_64
);
6949 regnames
= regnames_32
;
6950 regnames_count
= ARRAY_SIZE (regnames_32
);
6953 for (regnum
= 0; regnum
< regnames_count
; regnum
++)
6954 if (regnames
[regnum
] != NULL
6955 && strcmp (regname
, regnames
[regnum
]) == 0)
6962 tc_x86_frame_initial_instructions (void)
6964 static unsigned int sp_regno
;
6967 sp_regno
= tc_x86_regname_to_dw2regnum (flag_code
== CODE_64BIT
6970 cfi_add_CFA_def_cfa (sp_regno
, -x86_cie_data_alignment
);
6971 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
6975 i386_elf_section_type (const char *str
, size_t len
)
6977 if (flag_code
== CODE_64BIT
6978 && len
== sizeof ("unwind") - 1
6979 && strncmp (str
, "unwind", 6) == 0)
6980 return SHT_X86_64_UNWIND
;
6987 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
6991 expr
.X_op
= O_secrel
;
6992 expr
.X_add_symbol
= symbol
;
6993 expr
.X_add_number
= 0;
6994 emit_expr (&expr
, size
);
6998 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
6999 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
7002 x86_64_section_letter (int letter
, char **ptr_msg
)
7004 if (flag_code
== CODE_64BIT
)
7007 return SHF_X86_64_LARGE
;
7009 *ptr_msg
= _("Bad .section directive: want a,l,w,x,M,S,G,T in string");
7012 *ptr_msg
= _("Bad .section directive: want a,w,x,M,S,G,T in string");
7017 x86_64_section_word (char *str
, size_t len
)
7019 if (len
== 5 && flag_code
== CODE_64BIT
&& strncmp (str
, "large", 5) == 0)
7020 return SHF_X86_64_LARGE
;
7026 handle_large_common (int small ATTRIBUTE_UNUSED
)
7028 if (flag_code
!= CODE_64BIT
)
7030 s_comm_internal (0, elf_common_parse
);
7031 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
7035 static segT lbss_section
;
7036 asection
*saved_com_section_ptr
= elf_com_section_ptr
;
7037 asection
*saved_bss_section
= bss_section
;
7039 if (lbss_section
== NULL
)
7041 flagword applicable
;
7043 subsegT subseg
= now_subseg
;
7045 /* The .lbss section is for local .largecomm symbols. */
7046 lbss_section
= subseg_new (".lbss", 0);
7047 applicable
= bfd_applicable_section_flags (stdoutput
);
7048 bfd_set_section_flags (stdoutput
, lbss_section
,
7049 applicable
& SEC_ALLOC
);
7050 seg_info (lbss_section
)->bss
= 1;
7052 subseg_set (seg
, subseg
);
7055 elf_com_section_ptr
= &_bfd_elf_large_com_section
;
7056 bss_section
= lbss_section
;
7058 s_comm_internal (0, elf_common_parse
);
7060 elf_com_section_ptr
= saved_com_section_ptr
;
7061 bss_section
= saved_bss_section
;
7064 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */