1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright (C) 1989-2018 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 /* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
23 x86_64 support by Jan Hubicka (jh@suse.cz)
24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
29 #include "safe-ctype.h"
31 #include "dwarf2dbg.h"
32 #include "dw2gencfi.h"
33 #include "elf/x86-64.h"
34 #include "opcodes/i386-init.h"
36 #ifndef REGISTER_WARNINGS
37 #define REGISTER_WARNINGS 1
40 #ifndef INFER_ADDR_PREFIX
41 #define INFER_ADDR_PREFIX 1
45 #define DEFAULT_ARCH "i386"
50 #define INLINE __inline__
56 /* Prefixes will be emitted in the order defined below.
57 WAIT_PREFIX must be the first prefix since FWAIT is really is an
58 instruction, and so must come before any prefixes.
59 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
60 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
66 #define HLE_PREFIX REP_PREFIX
67 #define BND_PREFIX REP_PREFIX
69 #define REX_PREFIX 6 /* must come last. */
70 #define MAX_PREFIXES 7 /* max prefixes per opcode */
72 /* we define the syntax here (modulo base,index,scale syntax) */
73 #define REGISTER_PREFIX '%'
74 #define IMMEDIATE_PREFIX '$'
75 #define ABSOLUTE_PREFIX '*'
77 /* these are the instruction mnemonic suffixes in AT&T syntax or
78 memory operand size in Intel syntax. */
79 #define WORD_MNEM_SUFFIX 'w'
80 #define BYTE_MNEM_SUFFIX 'b'
81 #define SHORT_MNEM_SUFFIX 's'
82 #define LONG_MNEM_SUFFIX 'l'
83 #define QWORD_MNEM_SUFFIX 'q'
84 /* Intel Syntax. Use a non-ascii letter since since it never appears
86 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
88 #define END_OF_INSN '\0'
91 'templates' is for grouping together 'template' structures for opcodes
92 of the same name. This is only used for storing the insns in the grand
93 ole hash table of insns.
94 The templates themselves start at START and range up to (but not including)
99 const insn_template
*start
;
100 const insn_template
*end
;
104 /* 386 operand encoding bytes: see 386 book for details of this. */
107 unsigned int regmem
; /* codes register or memory operand */
108 unsigned int reg
; /* codes register operand (or extended opcode) */
109 unsigned int mode
; /* how to interpret regmem & reg */
113 /* x86-64 extension prefix. */
114 typedef int rex_byte
;
116 /* 386 opcode byte to code indirect addressing. */
125 /* x86 arch names, types and features */
128 const char *name
; /* arch name */
129 unsigned int len
; /* arch string length */
130 enum processor_type type
; /* arch type */
131 i386_cpu_flags flags
; /* cpu feature flags */
132 unsigned int skip
; /* show_arch should skip this. */
136 /* Used to turn off indicated flags. */
139 const char *name
; /* arch name */
140 unsigned int len
; /* arch string length */
141 i386_cpu_flags flags
; /* cpu feature flags */
145 static void update_code_flag (int, int);
146 static void set_code_flag (int);
147 static void set_16bit_gcc_code_flag (int);
148 static void set_intel_syntax (int);
149 static void set_intel_mnemonic (int);
150 static void set_allow_index_reg (int);
151 static void set_check (int);
152 static void set_cpu_arch (int);
154 static void pe_directive_secrel (int);
156 static void signed_cons (int);
157 static char *output_invalid (int c
);
158 static int i386_finalize_immediate (segT
, expressionS
*, i386_operand_type
,
160 static int i386_finalize_displacement (segT
, expressionS
*, i386_operand_type
,
162 static int i386_att_operand (char *);
163 static int i386_intel_operand (char *, int);
164 static int i386_intel_simplify (expressionS
*);
165 static int i386_intel_parse_name (const char *, expressionS
*);
166 static const reg_entry
*parse_register (char *, char **);
167 static char *parse_insn (char *, char *);
168 static char *parse_operands (char *, const char *);
169 static void swap_operands (void);
170 static void swap_2_operands (int, int);
171 static void optimize_imm (void);
172 static void optimize_disp (void);
173 static const insn_template
*match_template (char);
174 static int check_string (void);
175 static int process_suffix (void);
176 static int check_byte_reg (void);
177 static int check_long_reg (void);
178 static int check_qword_reg (void);
179 static int check_word_reg (void);
180 static int finalize_imm (void);
181 static int process_operands (void);
182 static const seg_entry
*build_modrm_byte (void);
183 static void output_insn (void);
184 static void output_imm (fragS
*, offsetT
);
185 static void output_disp (fragS
*, offsetT
);
187 static void s_bss (int);
189 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
190 static void handle_large_common (int small ATTRIBUTE_UNUSED
);
193 static const char *default_arch
= DEFAULT_ARCH
;
195 /* This struct describes rounding control and SAE in the instruction. */
209 static struct RC_Operation rc_op
;
211 /* The struct describes masking, applied to OPERAND in the instruction.
212 MASK is a pointer to the corresponding mask register. ZEROING tells
213 whether merging or zeroing mask is used. */
214 struct Mask_Operation
216 const reg_entry
*mask
;
217 unsigned int zeroing
;
218 /* The operand where this operation is associated. */
222 static struct Mask_Operation mask_op
;
224 /* The struct describes broadcasting, applied to OPERAND. FACTOR is
226 struct Broadcast_Operation
228 /* Type of broadcast: {1to2}, {1to4}, {1to8}, or {1to16}. */
231 /* Index of broadcasted operand. */
235 static struct Broadcast_Operation broadcast_op
;
240 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
241 unsigned char bytes
[4];
243 /* Destination or source register specifier. */
244 const reg_entry
*register_specifier
;
247 /* 'md_assemble ()' gathers together information and puts it into a
254 const reg_entry
*regs
;
259 operand_size_mismatch
,
260 operand_type_mismatch
,
261 register_type_mismatch
,
262 number_of_operands_mismatch
,
263 invalid_instruction_suffix
,
265 unsupported_with_intel_mnemonic
,
268 invalid_vsib_address
,
269 invalid_vector_register_set
,
270 unsupported_vector_index_register
,
271 unsupported_broadcast
,
272 broadcast_not_on_src_operand
,
275 mask_not_on_destination
,
278 rc_sae_operand_not_last_imm
,
279 invalid_register_operand
,
284 /* TM holds the template for the insn were currently assembling. */
287 /* SUFFIX holds the instruction size suffix for byte, word, dword
288 or qword, if given. */
291 /* OPERANDS gives the number of given operands. */
292 unsigned int operands
;
294 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
295 of given register, displacement, memory operands and immediate
297 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
299 /* TYPES [i] is the type (see above #defines) which tells us how to
300 use OP[i] for the corresponding operand. */
301 i386_operand_type types
[MAX_OPERANDS
];
303 /* Displacement expression, immediate expression, or register for each
305 union i386_op op
[MAX_OPERANDS
];
307 /* Flags for operands. */
308 unsigned int flags
[MAX_OPERANDS
];
309 #define Operand_PCrel 1
311 /* Relocation type for operand */
312 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
314 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
315 the base index byte below. */
316 const reg_entry
*base_reg
;
317 const reg_entry
*index_reg
;
318 unsigned int log2_scale_factor
;
320 /* SEG gives the seg_entries of this insn. They are zero unless
321 explicit segment overrides are given. */
322 const seg_entry
*seg
[2];
324 /* Copied first memory operand string, for re-checking. */
327 /* PREFIX holds all the given prefix opcodes (usually null).
328 PREFIXES is the number of prefix opcodes. */
329 unsigned int prefixes
;
330 unsigned char prefix
[MAX_PREFIXES
];
332 /* RM and SIB are the modrm byte and the sib byte where the
333 addressing modes of this insn are encoded. */
340 /* Masking attributes. */
341 struct Mask_Operation
*mask
;
343 /* Rounding control and SAE attributes. */
344 struct RC_Operation
*rounding
;
346 /* Broadcasting attributes. */
347 struct Broadcast_Operation
*broadcast
;
349 /* Compressed disp8*N attribute. */
350 unsigned int memshift
;
352 /* Prefer load or store in encoding. */
355 dir_encoding_default
= 0,
360 /* Prefer 8bit or 32bit displacement in encoding. */
363 disp_encoding_default
= 0,
368 /* Prefer the REX byte in encoding. */
369 bfd_boolean rex_encoding
;
371 /* Disable instruction size optimization. */
372 bfd_boolean no_optimize
;
374 /* How to encode vector instructions. */
377 vex_encoding_default
= 0,
384 const char *rep_prefix
;
387 const char *hle_prefix
;
389 /* Have BND prefix. */
390 const char *bnd_prefix
;
392 /* Have NOTRACK prefix. */
393 const char *notrack_prefix
;
396 enum i386_error error
;
399 typedef struct _i386_insn i386_insn
;
401 /* Link RC type with corresponding string, that'll be looked for in
410 static const struct RC_name RC_NamesTable
[] =
412 { rne
, STRING_COMMA_LEN ("rn-sae") },
413 { rd
, STRING_COMMA_LEN ("rd-sae") },
414 { ru
, STRING_COMMA_LEN ("ru-sae") },
415 { rz
, STRING_COMMA_LEN ("rz-sae") },
416 { saeonly
, STRING_COMMA_LEN ("sae") },
419 /* List of chars besides those in app.c:symbol_chars that can start an
420 operand. Used to prevent the scrubber eating vital white-space. */
421 const char extra_symbol_chars
[] = "*%-([{}"
430 #if (defined (TE_I386AIX) \
431 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
432 && !defined (TE_GNU) \
433 && !defined (TE_LINUX) \
434 && !defined (TE_NACL) \
435 && !defined (TE_FreeBSD) \
436 && !defined (TE_DragonFly) \
437 && !defined (TE_NetBSD)))
438 /* This array holds the chars that always start a comment. If the
439 pre-processor is disabled, these aren't very useful. The option
440 --divide will remove '/' from this list. */
441 const char *i386_comment_chars
= "#/";
442 #define SVR4_COMMENT_CHARS 1
443 #define PREFIX_SEPARATOR '\\'
446 const char *i386_comment_chars
= "#";
447 #define PREFIX_SEPARATOR '/'
450 /* This array holds the chars that only start a comment at the beginning of
451 a line. If the line seems to have the form '# 123 filename'
452 .line and .file directives will appear in the pre-processed output.
453 Note that input_file.c hand checks for '#' at the beginning of the
454 first line of the input file. This is because the compiler outputs
455 #NO_APP at the beginning of its output.
456 Also note that comments started like this one will always work if
457 '/' isn't otherwise defined. */
458 const char line_comment_chars
[] = "#/";
460 const char line_separator_chars
[] = ";";
462 /* Chars that can be used to separate mant from exp in floating point
464 const char EXP_CHARS
[] = "eE";
466 /* Chars that mean this number is a floating point constant
469 const char FLT_CHARS
[] = "fFdDxX";
471 /* Tables for lexical analysis. */
472 static char mnemonic_chars
[256];
473 static char register_chars
[256];
474 static char operand_chars
[256];
475 static char identifier_chars
[256];
476 static char digit_chars
[256];
478 /* Lexical macros. */
479 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
480 #define is_operand_char(x) (operand_chars[(unsigned char) x])
481 #define is_register_char(x) (register_chars[(unsigned char) x])
482 #define is_space_char(x) ((x) == ' ')
483 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
484 #define is_digit_char(x) (digit_chars[(unsigned char) x])
486 /* All non-digit non-letter characters that may occur in an operand. */
487 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
489 /* md_assemble() always leaves the strings it's passed unaltered. To
490 effect this we maintain a stack of saved characters that we've smashed
491 with '\0's (indicating end of strings for various sub-fields of the
492 assembler instruction). */
493 static char save_stack
[32];
494 static char *save_stack_p
;
495 #define END_STRING_AND_SAVE(s) \
496 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
497 #define RESTORE_END_STRING(s) \
498 do { *(s) = *--save_stack_p; } while (0)
500 /* The instruction we're assembling. */
503 /* Possible templates for current insn. */
504 static const templates
*current_templates
;
506 /* Per instruction expressionS buffers: max displacements & immediates. */
507 static expressionS disp_expressions
[MAX_MEMORY_OPERANDS
];
508 static expressionS im_expressions
[MAX_IMMEDIATE_OPERANDS
];
510 /* Current operand we are working on. */
511 static int this_operand
= -1;
513 /* We support four different modes. FLAG_CODE variable is used to distinguish
521 static enum flag_code flag_code
;
522 static unsigned int object_64bit
;
523 static unsigned int disallow_64bit_reloc
;
524 static int use_rela_relocations
= 0;
526 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
527 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
528 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
530 /* The ELF ABI to use. */
538 static enum x86_elf_abi x86_elf_abi
= I386_ABI
;
541 #if defined (TE_PE) || defined (TE_PEP)
542 /* Use big object file format. */
543 static int use_big_obj
= 0;
546 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
547 /* 1 if generating code for a shared library. */
548 static int shared
= 0;
551 /* 1 for intel syntax,
553 static int intel_syntax
= 0;
555 /* 1 for Intel64 ISA,
559 /* 1 for intel mnemonic,
560 0 if att mnemonic. */
561 static int intel_mnemonic
= !SYSV386_COMPAT
;
563 /* 1 if pseudo registers are permitted. */
564 static int allow_pseudo_reg
= 0;
566 /* 1 if register prefix % not required. */
567 static int allow_naked_reg
= 0;
569 /* 1 if the assembler should add BND prefix for all control-transferring
570 instructions supporting it, even if this prefix wasn't specified
572 static int add_bnd_prefix
= 0;
574 /* 1 if pseudo index register, eiz/riz, is allowed . */
575 static int allow_index_reg
= 0;
577 /* 1 if the assembler should ignore LOCK prefix, even if it was
578 specified explicitly. */
579 static int omit_lock_prefix
= 0;
581 /* 1 if the assembler should encode lfence, mfence, and sfence as
582 "lock addl $0, (%{re}sp)". */
583 static int avoid_fence
= 0;
585 /* 1 if the assembler should generate relax relocations. */
587 static int generate_relax_relocations
588 = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS
;
590 static enum check_kind
596 sse_check
, operand_check
= check_warning
;
599 1. Clear the REX_W bit with register operand if possible.
600 2. Above plus use 128bit vector instruction to clear the full vector
603 static int optimize
= 0;
606 1. Clear the REX_W bit with register operand if possible.
607 2. Above plus use 128bit vector instruction to clear the full vector
609 3. Above plus optimize "test{q,l,w} $imm8,%r{64,32,16}" to
612 static int optimize_for_space
= 0;
614 /* Register prefix used for error message. */
615 static const char *register_prefix
= "%";
617 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
618 leave, push, and pop instructions so that gcc has the same stack
619 frame as in 32 bit mode. */
620 static char stackop_size
= '\0';
622 /* Non-zero to optimize code alignment. */
623 int optimize_align_code
= 1;
625 /* Non-zero to quieten some warnings. */
626 static int quiet_warnings
= 0;
629 static const char *cpu_arch_name
= NULL
;
630 static char *cpu_sub_arch_name
= NULL
;
632 /* CPU feature flags. */
633 static i386_cpu_flags cpu_arch_flags
= CPU_UNKNOWN_FLAGS
;
635 /* If we have selected a cpu we are generating instructions for. */
636 static int cpu_arch_tune_set
= 0;
638 /* Cpu we are generating instructions for. */
639 enum processor_type cpu_arch_tune
= PROCESSOR_UNKNOWN
;
641 /* CPU feature flags of cpu we are generating instructions for. */
642 static i386_cpu_flags cpu_arch_tune_flags
;
644 /* CPU instruction set architecture used. */
645 enum processor_type cpu_arch_isa
= PROCESSOR_UNKNOWN
;
647 /* CPU feature flags of instruction set architecture used. */
648 i386_cpu_flags cpu_arch_isa_flags
;
650 /* If set, conditional jumps are not automatically promoted to handle
651 larger than a byte offset. */
652 static unsigned int no_cond_jump_promotion
= 0;
654 /* Encode SSE instructions with VEX prefix. */
655 static unsigned int sse2avx
;
657 /* Encode scalar AVX instructions with specific vector length. */
664 /* Encode scalar EVEX LIG instructions with specific vector length. */
672 /* Encode EVEX WIG instructions with specific evex.w. */
679 /* Value to encode in EVEX RC bits, for SAE-only instructions. */
680 static enum rc_type evexrcig
= rne
;
682 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
683 static symbolS
*GOT_symbol
;
685 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
686 unsigned int x86_dwarf2_return_column
;
688 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
689 int x86_cie_data_alignment
;
691 /* Interface to relax_segment.
692 There are 3 major relax states for 386 jump insns because the
693 different types of jumps add different sizes to frags when we're
694 figuring out what sort of jump to choose to reach a given label. */
697 #define UNCOND_JUMP 0
699 #define COND_JUMP86 2
704 #define SMALL16 (SMALL | CODE16)
706 #define BIG16 (BIG | CODE16)
710 #define INLINE __inline__
716 #define ENCODE_RELAX_STATE(type, size) \
717 ((relax_substateT) (((type) << 2) | (size)))
718 #define TYPE_FROM_RELAX_STATE(s) \
720 #define DISP_SIZE_FROM_RELAX_STATE(s) \
721 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
723 /* This table is used by relax_frag to promote short jumps to long
724 ones where necessary. SMALL (short) jumps may be promoted to BIG
725 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
726 don't allow a short jump in a 32 bit code segment to be promoted to
727 a 16 bit offset jump because it's slower (requires data size
728 prefix), and doesn't work, unless the destination is in the bottom
729 64k of the code segment (The top 16 bits of eip are zeroed). */
731 const relax_typeS md_relax_table
[] =
734 1) most positive reach of this state,
735 2) most negative reach of this state,
736 3) how many bytes this mode will have in the variable part of the frag
737 4) which index into the table to try if we can't fit into this one. */
739 /* UNCOND_JUMP states. */
740 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
741 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
742 /* dword jmp adds 4 bytes to frag:
743 0 extra opcode bytes, 4 displacement bytes. */
745 /* word jmp adds 2 byte2 to frag:
746 0 extra opcode bytes, 2 displacement bytes. */
749 /* COND_JUMP states. */
750 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
751 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
752 /* dword conditionals adds 5 bytes to frag:
753 1 extra opcode byte, 4 displacement bytes. */
755 /* word conditionals add 3 bytes to frag:
756 1 extra opcode byte, 2 displacement bytes. */
759 /* COND_JUMP86 states. */
760 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
761 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
762 /* dword conditionals adds 5 bytes to frag:
763 1 extra opcode byte, 4 displacement bytes. */
765 /* word conditionals add 4 bytes to frag:
766 1 displacement byte and a 3 byte long branch insn. */
770 static const arch_entry cpu_arch
[] =
772 /* Do not replace the first two entries - i386_target_format()
773 relies on them being there in this order. */
774 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32
,
775 CPU_GENERIC32_FLAGS
, 0 },
776 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64
,
777 CPU_GENERIC64_FLAGS
, 0 },
778 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN
,
780 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN
,
782 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN
,
784 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386
,
786 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486
,
788 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM
,
790 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO
,
792 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM
,
794 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO
,
795 CPU_PENTIUMPRO_FLAGS
, 0 },
796 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO
,
798 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO
,
800 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4
,
802 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA
,
804 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA
,
805 CPU_NOCONA_FLAGS
, 0 },
806 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE
,
808 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE
,
810 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2
,
811 CPU_CORE2_FLAGS
, 1 },
812 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2
,
813 CPU_CORE2_FLAGS
, 0 },
814 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7
,
815 CPU_COREI7_FLAGS
, 0 },
816 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM
,
818 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM
,
820 { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU
,
821 CPU_IAMCU_FLAGS
, 0 },
822 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6
,
824 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6
,
826 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON
,
827 CPU_ATHLON_FLAGS
, 0 },
828 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8
,
830 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8
,
832 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8
,
834 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10
,
835 CPU_AMDFAM10_FLAGS
, 0 },
836 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD
,
837 CPU_BDVER1_FLAGS
, 0 },
838 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD
,
839 CPU_BDVER2_FLAGS
, 0 },
840 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD
,
841 CPU_BDVER3_FLAGS
, 0 },
842 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD
,
843 CPU_BDVER4_FLAGS
, 0 },
844 { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER
,
845 CPU_ZNVER1_FLAGS
, 0 },
846 { STRING_COMMA_LEN ("znver2"), PROCESSOR_ZNVER
,
847 CPU_ZNVER2_FLAGS
, 0 },
848 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT
,
849 CPU_BTVER1_FLAGS
, 0 },
850 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT
,
851 CPU_BTVER2_FLAGS
, 0 },
852 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN
,
854 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN
,
856 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN
,
858 { STRING_COMMA_LEN (".687"), PROCESSOR_UNKNOWN
,
860 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN
,
862 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN
,
864 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN
,
866 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN
,
868 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN
,
869 CPU_SSSE3_FLAGS
, 0 },
870 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN
,
871 CPU_SSE4_1_FLAGS
, 0 },
872 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN
,
873 CPU_SSE4_2_FLAGS
, 0 },
874 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN
,
875 CPU_SSE4_2_FLAGS
, 0 },
876 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN
,
878 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN
,
880 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN
,
881 CPU_AVX512F_FLAGS
, 0 },
882 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN
,
883 CPU_AVX512CD_FLAGS
, 0 },
884 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN
,
885 CPU_AVX512ER_FLAGS
, 0 },
886 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN
,
887 CPU_AVX512PF_FLAGS
, 0 },
888 { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN
,
889 CPU_AVX512DQ_FLAGS
, 0 },
890 { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN
,
891 CPU_AVX512BW_FLAGS
, 0 },
892 { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN
,
893 CPU_AVX512VL_FLAGS
, 0 },
894 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN
,
896 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN
,
897 CPU_VMFUNC_FLAGS
, 0 },
898 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN
,
900 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN
,
901 CPU_XSAVE_FLAGS
, 0 },
902 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN
,
903 CPU_XSAVEOPT_FLAGS
, 0 },
904 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN
,
905 CPU_XSAVEC_FLAGS
, 0 },
906 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN
,
907 CPU_XSAVES_FLAGS
, 0 },
908 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN
,
910 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN
,
911 CPU_PCLMUL_FLAGS
, 0 },
912 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN
,
913 CPU_PCLMUL_FLAGS
, 1 },
914 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN
,
915 CPU_FSGSBASE_FLAGS
, 0 },
916 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN
,
917 CPU_RDRND_FLAGS
, 0 },
918 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN
,
920 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN
,
922 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN
,
924 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN
,
926 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN
,
928 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN
,
930 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN
,
931 CPU_MOVBE_FLAGS
, 0 },
932 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN
,
934 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN
,
936 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN
,
937 CPU_LZCNT_FLAGS
, 0 },
938 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN
,
940 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN
,
942 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN
,
943 CPU_INVPCID_FLAGS
, 0 },
944 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN
,
945 CPU_CLFLUSH_FLAGS
, 0 },
946 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN
,
948 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN
,
949 CPU_SYSCALL_FLAGS
, 0 },
950 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN
,
951 CPU_RDTSCP_FLAGS
, 0 },
952 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN
,
953 CPU_3DNOW_FLAGS
, 0 },
954 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN
,
955 CPU_3DNOWA_FLAGS
, 0 },
956 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN
,
957 CPU_PADLOCK_FLAGS
, 0 },
958 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN
,
960 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN
,
962 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN
,
963 CPU_SSE4A_FLAGS
, 0 },
964 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN
,
966 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN
,
968 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN
,
970 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN
,
972 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN
,
973 CPU_RDSEED_FLAGS
, 0 },
974 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN
,
975 CPU_PRFCHW_FLAGS
, 0 },
976 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN
,
978 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN
,
980 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN
,
982 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN
,
983 CPU_CLFLUSHOPT_FLAGS
, 0 },
984 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN
,
985 CPU_PREFETCHWT1_FLAGS
, 0 },
986 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN
,
988 { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN
,
990 { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN
,
991 CPU_AVX512IFMA_FLAGS
, 0 },
992 { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN
,
993 CPU_AVX512VBMI_FLAGS
, 0 },
994 { STRING_COMMA_LEN (".avx512_4fmaps"), PROCESSOR_UNKNOWN
,
995 CPU_AVX512_4FMAPS_FLAGS
, 0 },
996 { STRING_COMMA_LEN (".avx512_4vnniw"), PROCESSOR_UNKNOWN
,
997 CPU_AVX512_4VNNIW_FLAGS
, 0 },
998 { STRING_COMMA_LEN (".avx512_vpopcntdq"), PROCESSOR_UNKNOWN
,
999 CPU_AVX512_VPOPCNTDQ_FLAGS
, 0 },
1000 { STRING_COMMA_LEN (".avx512_vbmi2"), PROCESSOR_UNKNOWN
,
1001 CPU_AVX512_VBMI2_FLAGS
, 0 },
1002 { STRING_COMMA_LEN (".avx512_vnni"), PROCESSOR_UNKNOWN
,
1003 CPU_AVX512_VNNI_FLAGS
, 0 },
1004 { STRING_COMMA_LEN (".avx512_bitalg"), PROCESSOR_UNKNOWN
,
1005 CPU_AVX512_BITALG_FLAGS
, 0 },
1006 { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN
,
1007 CPU_CLZERO_FLAGS
, 0 },
1008 { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN
,
1009 CPU_MWAITX_FLAGS
, 0 },
1010 { STRING_COMMA_LEN (".ospke"), PROCESSOR_UNKNOWN
,
1011 CPU_OSPKE_FLAGS
, 0 },
1012 { STRING_COMMA_LEN (".rdpid"), PROCESSOR_UNKNOWN
,
1013 CPU_RDPID_FLAGS
, 0 },
1014 { STRING_COMMA_LEN (".ptwrite"), PROCESSOR_UNKNOWN
,
1015 CPU_PTWRITE_FLAGS
, 0 },
1016 { STRING_COMMA_LEN (".ibt"), PROCESSOR_UNKNOWN
,
1018 { STRING_COMMA_LEN (".shstk"), PROCESSOR_UNKNOWN
,
1019 CPU_SHSTK_FLAGS
, 0 },
1020 { STRING_COMMA_LEN (".gfni"), PROCESSOR_UNKNOWN
,
1021 CPU_GFNI_FLAGS
, 0 },
1022 { STRING_COMMA_LEN (".vaes"), PROCESSOR_UNKNOWN
,
1023 CPU_VAES_FLAGS
, 0 },
1024 { STRING_COMMA_LEN (".vpclmulqdq"), PROCESSOR_UNKNOWN
,
1025 CPU_VPCLMULQDQ_FLAGS
, 0 },
1026 { STRING_COMMA_LEN (".wbnoinvd"), PROCESSOR_UNKNOWN
,
1027 CPU_WBNOINVD_FLAGS
, 0 },
1028 { STRING_COMMA_LEN (".pconfig"), PROCESSOR_UNKNOWN
,
1029 CPU_PCONFIG_FLAGS
, 0 },
1030 { STRING_COMMA_LEN (".waitpkg"), PROCESSOR_UNKNOWN
,
1031 CPU_WAITPKG_FLAGS
, 0 },
1032 { STRING_COMMA_LEN (".cldemote"), PROCESSOR_UNKNOWN
,
1033 CPU_CLDEMOTE_FLAGS
, 0 },
1034 { STRING_COMMA_LEN (".movdiri"), PROCESSOR_UNKNOWN
,
1035 CPU_MOVDIRI_FLAGS
, 0 },
1036 { STRING_COMMA_LEN (".movdir64b"), PROCESSOR_UNKNOWN
,
1037 CPU_MOVDIR64B_FLAGS
, 0 },
1040 static const noarch_entry cpu_noarch
[] =
1042 { STRING_COMMA_LEN ("no87"), CPU_ANY_X87_FLAGS
},
1043 { STRING_COMMA_LEN ("no287"), CPU_ANY_287_FLAGS
},
1044 { STRING_COMMA_LEN ("no387"), CPU_ANY_387_FLAGS
},
1045 { STRING_COMMA_LEN ("no687"), CPU_ANY_687_FLAGS
},
1046 { STRING_COMMA_LEN ("nommx"), CPU_ANY_MMX_FLAGS
},
1047 { STRING_COMMA_LEN ("nosse"), CPU_ANY_SSE_FLAGS
},
1048 { STRING_COMMA_LEN ("nosse2"), CPU_ANY_SSE2_FLAGS
},
1049 { STRING_COMMA_LEN ("nosse3"), CPU_ANY_SSE3_FLAGS
},
1050 { STRING_COMMA_LEN ("nossse3"), CPU_ANY_SSSE3_FLAGS
},
1051 { STRING_COMMA_LEN ("nosse4.1"), CPU_ANY_SSE4_1_FLAGS
},
1052 { STRING_COMMA_LEN ("nosse4.2"), CPU_ANY_SSE4_2_FLAGS
},
1053 { STRING_COMMA_LEN ("nosse4"), CPU_ANY_SSE4_1_FLAGS
},
1054 { STRING_COMMA_LEN ("noavx"), CPU_ANY_AVX_FLAGS
},
1055 { STRING_COMMA_LEN ("noavx2"), CPU_ANY_AVX2_FLAGS
},
1056 { STRING_COMMA_LEN ("noavx512f"), CPU_ANY_AVX512F_FLAGS
},
1057 { STRING_COMMA_LEN ("noavx512cd"), CPU_ANY_AVX512CD_FLAGS
},
1058 { STRING_COMMA_LEN ("noavx512er"), CPU_ANY_AVX512ER_FLAGS
},
1059 { STRING_COMMA_LEN ("noavx512pf"), CPU_ANY_AVX512PF_FLAGS
},
1060 { STRING_COMMA_LEN ("noavx512dq"), CPU_ANY_AVX512DQ_FLAGS
},
1061 { STRING_COMMA_LEN ("noavx512bw"), CPU_ANY_AVX512BW_FLAGS
},
1062 { STRING_COMMA_LEN ("noavx512vl"), CPU_ANY_AVX512VL_FLAGS
},
1063 { STRING_COMMA_LEN ("noavx512ifma"), CPU_ANY_AVX512IFMA_FLAGS
},
1064 { STRING_COMMA_LEN ("noavx512vbmi"), CPU_ANY_AVX512VBMI_FLAGS
},
1065 { STRING_COMMA_LEN ("noavx512_4fmaps"), CPU_ANY_AVX512_4FMAPS_FLAGS
},
1066 { STRING_COMMA_LEN ("noavx512_4vnniw"), CPU_ANY_AVX512_4VNNIW_FLAGS
},
1067 { STRING_COMMA_LEN ("noavx512_vpopcntdq"), CPU_ANY_AVX512_VPOPCNTDQ_FLAGS
},
1068 { STRING_COMMA_LEN ("noavx512_vbmi2"), CPU_ANY_AVX512_VBMI2_FLAGS
},
1069 { STRING_COMMA_LEN ("noavx512_vnni"), CPU_ANY_AVX512_VNNI_FLAGS
},
1070 { STRING_COMMA_LEN ("noavx512_bitalg"), CPU_ANY_AVX512_BITALG_FLAGS
},
1071 { STRING_COMMA_LEN ("noibt"), CPU_ANY_IBT_FLAGS
},
1072 { STRING_COMMA_LEN ("noshstk"), CPU_ANY_SHSTK_FLAGS
},
1073 { STRING_COMMA_LEN ("nomovdiri"), CPU_ANY_MOVDIRI_FLAGS
},
1074 { STRING_COMMA_LEN ("nomovdir64b"), CPU_ANY_MOVDIR64B_FLAGS
},
1078 /* Like s_lcomm_internal in gas/read.c but the alignment string
1079 is allowed to be optional. */
1082 pe_lcomm_internal (int needs_align
, symbolS
*symbolP
, addressT size
)
1089 && *input_line_pointer
== ',')
1091 align
= parse_align (needs_align
- 1);
1093 if (align
== (addressT
) -1)
1108 bss_alloc (symbolP
, size
, align
);
1113 pe_lcomm (int needs_align
)
1115 s_comm_internal (needs_align
* 2, pe_lcomm_internal
);
1119 const pseudo_typeS md_pseudo_table
[] =
1121 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
1122 {"align", s_align_bytes
, 0},
1124 {"align", s_align_ptwo
, 0},
1126 {"arch", set_cpu_arch
, 0},
1130 {"lcomm", pe_lcomm
, 1},
1132 {"ffloat", float_cons
, 'f'},
1133 {"dfloat", float_cons
, 'd'},
1134 {"tfloat", float_cons
, 'x'},
1136 {"slong", signed_cons
, 4},
1137 {"noopt", s_ignore
, 0},
1138 {"optim", s_ignore
, 0},
1139 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
1140 {"code16", set_code_flag
, CODE_16BIT
},
1141 {"code32", set_code_flag
, CODE_32BIT
},
1143 {"code64", set_code_flag
, CODE_64BIT
},
1145 {"intel_syntax", set_intel_syntax
, 1},
1146 {"att_syntax", set_intel_syntax
, 0},
1147 {"intel_mnemonic", set_intel_mnemonic
, 1},
1148 {"att_mnemonic", set_intel_mnemonic
, 0},
1149 {"allow_index_reg", set_allow_index_reg
, 1},
1150 {"disallow_index_reg", set_allow_index_reg
, 0},
1151 {"sse_check", set_check
, 0},
1152 {"operand_check", set_check
, 1},
1153 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1154 {"largecomm", handle_large_common
, 0},
1156 {"file", dwarf2_directive_file
, 0},
1157 {"loc", dwarf2_directive_loc
, 0},
1158 {"loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0},
1161 {"secrel32", pe_directive_secrel
, 0},
1166 /* For interface with expression (). */
1167 extern char *input_line_pointer
;
1169 /* Hash table for instruction mnemonic lookup. */
1170 static struct hash_control
*op_hash
;
1172 /* Hash table for register lookup. */
1173 static struct hash_control
*reg_hash
;
1175 /* Various efficient no-op patterns for aligning code labels.
1176 Note: Don't try to assemble the instructions in the comments.
1177 0L and 0w are not legal. */
1178 static const unsigned char f32_1
[] =
1180 static const unsigned char f32_2
[] =
1181 {0x66,0x90}; /* xchg %ax,%ax */
1182 static const unsigned char f32_3
[] =
1183 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1184 static const unsigned char f32_4
[] =
1185 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1186 static const unsigned char f32_6
[] =
1187 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1188 static const unsigned char f32_7
[] =
1189 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1190 static const unsigned char f16_3
[] =
1191 {0x8d,0x74,0x00}; /* lea 0(%si),%si */
1192 static const unsigned char f16_4
[] =
1193 {0x8d,0xb4,0x00,0x00}; /* lea 0W(%si),%si */
1194 static const unsigned char jump_disp8
[] =
1195 {0xeb}; /* jmp disp8 */
1196 static const unsigned char jump32_disp32
[] =
1197 {0xe9}; /* jmp disp32 */
1198 static const unsigned char jump16_disp32
[] =
1199 {0x66,0xe9}; /* jmp disp32 */
1200 /* 32-bit NOPs patterns. */
1201 static const unsigned char *const f32_patt
[] = {
1202 f32_1
, f32_2
, f32_3
, f32_4
, NULL
, f32_6
, f32_7
1204 /* 16-bit NOPs patterns. */
1205 static const unsigned char *const f16_patt
[] = {
1206 f32_1
, f32_2
, f16_3
, f16_4
1208 /* nopl (%[re]ax) */
1209 static const unsigned char alt_3
[] =
1211 /* nopl 0(%[re]ax) */
1212 static const unsigned char alt_4
[] =
1213 {0x0f,0x1f,0x40,0x00};
1214 /* nopl 0(%[re]ax,%[re]ax,1) */
1215 static const unsigned char alt_5
[] =
1216 {0x0f,0x1f,0x44,0x00,0x00};
1217 /* nopw 0(%[re]ax,%[re]ax,1) */
1218 static const unsigned char alt_6
[] =
1219 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1220 /* nopl 0L(%[re]ax) */
1221 static const unsigned char alt_7
[] =
1222 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1223 /* nopl 0L(%[re]ax,%[re]ax,1) */
1224 static const unsigned char alt_8
[] =
1225 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1226 /* nopw 0L(%[re]ax,%[re]ax,1) */
1227 static const unsigned char alt_9
[] =
1228 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1229 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1230 static const unsigned char alt_10
[] =
1231 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1232 /* data16 nopw %cs:0L(%eax,%eax,1) */
1233 static const unsigned char alt_11
[] =
1234 {0x66,0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1235 /* 32-bit and 64-bit NOPs patterns. */
1236 static const unsigned char *const alt_patt
[] = {
1237 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
1238 alt_9
, alt_10
, alt_11
1241 /* Genenerate COUNT bytes of NOPs to WHERE from PATT with the maximum
1242 size of a single NOP instruction MAX_SINGLE_NOP_SIZE. */
1245 i386_output_nops (char *where
, const unsigned char *const *patt
,
1246 int count
, int max_single_nop_size
)
1249 /* Place the longer NOP first. */
1252 const unsigned char *nops
= patt
[max_single_nop_size
- 1];
1254 /* Use the smaller one if the requsted one isn't available. */
1257 max_single_nop_size
--;
1258 nops
= patt
[max_single_nop_size
- 1];
1261 last
= count
% max_single_nop_size
;
1264 for (offset
= 0; offset
< count
; offset
+= max_single_nop_size
)
1265 memcpy (where
+ offset
, nops
, max_single_nop_size
);
1269 nops
= patt
[last
- 1];
1272 /* Use the smaller one plus one-byte NOP if the needed one
1275 nops
= patt
[last
- 1];
1276 memcpy (where
+ offset
, nops
, last
);
1277 where
[offset
+ last
] = *patt
[0];
1280 memcpy (where
+ offset
, nops
, last
);
1285 fits_in_imm7 (offsetT num
)
1287 return (num
& 0x7f) == num
;
1291 fits_in_imm31 (offsetT num
)
1293 return (num
& 0x7fffffff) == num
;
1296 /* Genenerate COUNT bytes of NOPs to WHERE with the maximum size of a
1297 single NOP instruction LIMIT. */
1300 i386_generate_nops (fragS
*fragP
, char *where
, offsetT count
, int limit
)
1302 const unsigned char *const *patt
= NULL
;
1303 int max_single_nop_size
;
1304 /* Maximum number of NOPs before switching to jump over NOPs. */
1305 int max_number_of_nops
;
1307 switch (fragP
->fr_type
)
1316 /* We need to decide which NOP sequence to use for 32bit and
1317 64bit. When -mtune= is used:
1319 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1320 PROCESSOR_GENERIC32, f32_patt will be used.
1321 2. For the rest, alt_patt will be used.
1323 When -mtune= isn't used, alt_patt will be used if
1324 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
1327 When -march= or .arch is used, we can't use anything beyond
1328 cpu_arch_isa_flags. */
1330 if (flag_code
== CODE_16BIT
)
1333 max_single_nop_size
= sizeof (f16_patt
) / sizeof (f16_patt
[0]);
1334 /* Limit number of NOPs to 2 in 16-bit mode. */
1335 max_number_of_nops
= 2;
1339 if (fragP
->tc_frag_data
.isa
== PROCESSOR_UNKNOWN
)
1341 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1342 switch (cpu_arch_tune
)
1344 case PROCESSOR_UNKNOWN
:
1345 /* We use cpu_arch_isa_flags to check if we SHOULD
1346 optimize with nops. */
1347 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1352 case PROCESSOR_PENTIUM4
:
1353 case PROCESSOR_NOCONA
:
1354 case PROCESSOR_CORE
:
1355 case PROCESSOR_CORE2
:
1356 case PROCESSOR_COREI7
:
1357 case PROCESSOR_L1OM
:
1358 case PROCESSOR_K1OM
:
1359 case PROCESSOR_GENERIC64
:
1361 case PROCESSOR_ATHLON
:
1363 case PROCESSOR_AMDFAM10
:
1365 case PROCESSOR_ZNVER
:
1369 case PROCESSOR_I386
:
1370 case PROCESSOR_I486
:
1371 case PROCESSOR_PENTIUM
:
1372 case PROCESSOR_PENTIUMPRO
:
1373 case PROCESSOR_IAMCU
:
1374 case PROCESSOR_GENERIC32
:
1381 switch (fragP
->tc_frag_data
.tune
)
1383 case PROCESSOR_UNKNOWN
:
1384 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1385 PROCESSOR_UNKNOWN. */
1389 case PROCESSOR_I386
:
1390 case PROCESSOR_I486
:
1391 case PROCESSOR_PENTIUM
:
1392 case PROCESSOR_IAMCU
:
1394 case PROCESSOR_ATHLON
:
1396 case PROCESSOR_AMDFAM10
:
1398 case PROCESSOR_ZNVER
:
1400 case PROCESSOR_GENERIC32
:
1401 /* We use cpu_arch_isa_flags to check if we CAN optimize
1403 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1408 case PROCESSOR_PENTIUMPRO
:
1409 case PROCESSOR_PENTIUM4
:
1410 case PROCESSOR_NOCONA
:
1411 case PROCESSOR_CORE
:
1412 case PROCESSOR_CORE2
:
1413 case PROCESSOR_COREI7
:
1414 case PROCESSOR_L1OM
:
1415 case PROCESSOR_K1OM
:
1416 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1421 case PROCESSOR_GENERIC64
:
1427 if (patt
== f32_patt
)
1429 max_single_nop_size
= sizeof (f32_patt
) / sizeof (f32_patt
[0]);
1430 /* Limit number of NOPs to 2 for older processors. */
1431 max_number_of_nops
= 2;
1435 max_single_nop_size
= sizeof (alt_patt
) / sizeof (alt_patt
[0]);
1436 /* Limit number of NOPs to 7 for newer processors. */
1437 max_number_of_nops
= 7;
1442 limit
= max_single_nop_size
;
1444 if (fragP
->fr_type
== rs_fill_nop
)
1446 /* Output NOPs for .nop directive. */
1447 if (limit
> max_single_nop_size
)
1449 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
1450 _("invalid single nop size: %d "
1451 "(expect within [0, %d])"),
1452 limit
, max_single_nop_size
);
1457 fragP
->fr_var
= count
;
1459 if ((count
/ max_single_nop_size
) > max_number_of_nops
)
1461 /* Generate jump over NOPs. */
1462 offsetT disp
= count
- 2;
1463 if (fits_in_imm7 (disp
))
1465 /* Use "jmp disp8" if possible. */
1467 where
[0] = jump_disp8
[0];
1473 unsigned int size_of_jump
;
1475 if (flag_code
== CODE_16BIT
)
1477 where
[0] = jump16_disp32
[0];
1478 where
[1] = jump16_disp32
[1];
1483 where
[0] = jump32_disp32
[0];
1487 count
-= size_of_jump
+ 4;
1488 if (!fits_in_imm31 (count
))
1490 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
1491 _("jump over nop padding out of range"));
1495 md_number_to_chars (where
+ size_of_jump
, count
, 4);
1496 where
+= size_of_jump
+ 4;
1500 /* Generate multiple NOPs. */
1501 i386_output_nops (where
, patt
, count
, limit
);
1505 operand_type_all_zero (const union i386_operand_type
*x
)
1507 switch (ARRAY_SIZE(x
->array
))
1518 return !x
->array
[0];
1525 operand_type_set (union i386_operand_type
*x
, unsigned int v
)
1527 switch (ARRAY_SIZE(x
->array
))
1545 operand_type_equal (const union i386_operand_type
*x
,
1546 const union i386_operand_type
*y
)
1548 switch (ARRAY_SIZE(x
->array
))
1551 if (x
->array
[2] != y
->array
[2])
1555 if (x
->array
[1] != y
->array
[1])
1559 return x
->array
[0] == y
->array
[0];
1567 cpu_flags_all_zero (const union i386_cpu_flags
*x
)
1569 switch (ARRAY_SIZE(x
->array
))
1584 return !x
->array
[0];
1591 cpu_flags_equal (const union i386_cpu_flags
*x
,
1592 const union i386_cpu_flags
*y
)
1594 switch (ARRAY_SIZE(x
->array
))
1597 if (x
->array
[3] != y
->array
[3])
1601 if (x
->array
[2] != y
->array
[2])
1605 if (x
->array
[1] != y
->array
[1])
1609 return x
->array
[0] == y
->array
[0];
1617 cpu_flags_check_cpu64 (i386_cpu_flags f
)
1619 return !((flag_code
== CODE_64BIT
&& f
.bitfield
.cpuno64
)
1620 || (flag_code
!= CODE_64BIT
&& f
.bitfield
.cpu64
));
1623 static INLINE i386_cpu_flags
1624 cpu_flags_and (i386_cpu_flags x
, i386_cpu_flags y
)
1626 switch (ARRAY_SIZE (x
.array
))
1629 x
.array
[3] &= y
.array
[3];
1632 x
.array
[2] &= y
.array
[2];
1635 x
.array
[1] &= y
.array
[1];
1638 x
.array
[0] &= y
.array
[0];
1646 static INLINE i386_cpu_flags
1647 cpu_flags_or (i386_cpu_flags x
, i386_cpu_flags y
)
1649 switch (ARRAY_SIZE (x
.array
))
1652 x
.array
[3] |= y
.array
[3];
1655 x
.array
[2] |= y
.array
[2];
1658 x
.array
[1] |= y
.array
[1];
1661 x
.array
[0] |= y
.array
[0];
1669 static INLINE i386_cpu_flags
1670 cpu_flags_and_not (i386_cpu_flags x
, i386_cpu_flags y
)
1672 switch (ARRAY_SIZE (x
.array
))
1675 x
.array
[3] &= ~y
.array
[3];
1678 x
.array
[2] &= ~y
.array
[2];
1681 x
.array
[1] &= ~y
.array
[1];
1684 x
.array
[0] &= ~y
.array
[0];
1692 #define CPU_FLAGS_ARCH_MATCH 0x1
1693 #define CPU_FLAGS_64BIT_MATCH 0x2
1695 #define CPU_FLAGS_PERFECT_MATCH \
1696 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_64BIT_MATCH)
1698 /* Return CPU flags match bits. */
1701 cpu_flags_match (const insn_template
*t
)
1703 i386_cpu_flags x
= t
->cpu_flags
;
1704 int match
= cpu_flags_check_cpu64 (x
) ? CPU_FLAGS_64BIT_MATCH
: 0;
1706 x
.bitfield
.cpu64
= 0;
1707 x
.bitfield
.cpuno64
= 0;
1709 if (cpu_flags_all_zero (&x
))
1711 /* This instruction is available on all archs. */
1712 match
|= CPU_FLAGS_ARCH_MATCH
;
1716 /* This instruction is available only on some archs. */
1717 i386_cpu_flags cpu
= cpu_arch_flags
;
1719 /* AVX512VL is no standalone feature - match it and then strip it. */
1720 if (x
.bitfield
.cpuavx512vl
&& !cpu
.bitfield
.cpuavx512vl
)
1722 x
.bitfield
.cpuavx512vl
= 0;
1724 cpu
= cpu_flags_and (x
, cpu
);
1725 if (!cpu_flags_all_zero (&cpu
))
1727 if (x
.bitfield
.cpuavx
)
1729 /* We need to check a few extra flags with AVX. */
1730 if (cpu
.bitfield
.cpuavx
1731 && (!t
->opcode_modifier
.sse2avx
|| sse2avx
)
1732 && (!x
.bitfield
.cpuaes
|| cpu
.bitfield
.cpuaes
)
1733 && (!x
.bitfield
.cpugfni
|| cpu
.bitfield
.cpugfni
)
1734 && (!x
.bitfield
.cpupclmul
|| cpu
.bitfield
.cpupclmul
))
1735 match
|= CPU_FLAGS_ARCH_MATCH
;
1737 else if (x
.bitfield
.cpuavx512f
)
1739 /* We need to check a few extra flags with AVX512F. */
1740 if (cpu
.bitfield
.cpuavx512f
1741 && (!x
.bitfield
.cpugfni
|| cpu
.bitfield
.cpugfni
)
1742 && (!x
.bitfield
.cpuvaes
|| cpu
.bitfield
.cpuvaes
)
1743 && (!x
.bitfield
.cpuvpclmulqdq
|| cpu
.bitfield
.cpuvpclmulqdq
))
1744 match
|= CPU_FLAGS_ARCH_MATCH
;
1747 match
|= CPU_FLAGS_ARCH_MATCH
;
1753 static INLINE i386_operand_type
1754 operand_type_and (i386_operand_type x
, i386_operand_type y
)
1756 switch (ARRAY_SIZE (x
.array
))
1759 x
.array
[2] &= y
.array
[2];
1762 x
.array
[1] &= y
.array
[1];
1765 x
.array
[0] &= y
.array
[0];
1773 static INLINE i386_operand_type
1774 operand_type_and_not (i386_operand_type x
, i386_operand_type y
)
1776 switch (ARRAY_SIZE (x
.array
))
1779 x
.array
[2] &= ~y
.array
[2];
1782 x
.array
[1] &= ~y
.array
[1];
1785 x
.array
[0] &= ~y
.array
[0];
1793 static INLINE i386_operand_type
1794 operand_type_or (i386_operand_type x
, i386_operand_type y
)
1796 switch (ARRAY_SIZE (x
.array
))
1799 x
.array
[2] |= y
.array
[2];
1802 x
.array
[1] |= y
.array
[1];
1805 x
.array
[0] |= y
.array
[0];
1813 static INLINE i386_operand_type
1814 operand_type_xor (i386_operand_type x
, i386_operand_type y
)
1816 switch (ARRAY_SIZE (x
.array
))
1819 x
.array
[2] ^= y
.array
[2];
1822 x
.array
[1] ^= y
.array
[1];
1825 x
.array
[0] ^= y
.array
[0];
1833 static const i386_operand_type acc32
= OPERAND_TYPE_ACC32
;
1834 static const i386_operand_type acc64
= OPERAND_TYPE_ACC64
;
1835 static const i386_operand_type inoutportreg
1836 = OPERAND_TYPE_INOUTPORTREG
;
1837 static const i386_operand_type reg16_inoutportreg
1838 = OPERAND_TYPE_REG16_INOUTPORTREG
;
1839 static const i386_operand_type disp16
= OPERAND_TYPE_DISP16
;
1840 static const i386_operand_type disp32
= OPERAND_TYPE_DISP32
;
1841 static const i386_operand_type disp32s
= OPERAND_TYPE_DISP32S
;
1842 static const i386_operand_type disp16_32
= OPERAND_TYPE_DISP16_32
;
1843 static const i386_operand_type anydisp
1844 = OPERAND_TYPE_ANYDISP
;
1845 static const i386_operand_type regxmm
= OPERAND_TYPE_REGXMM
;
1846 static const i386_operand_type regmask
= OPERAND_TYPE_REGMASK
;
1847 static const i386_operand_type imm8
= OPERAND_TYPE_IMM8
;
1848 static const i386_operand_type imm8s
= OPERAND_TYPE_IMM8S
;
1849 static const i386_operand_type imm16
= OPERAND_TYPE_IMM16
;
1850 static const i386_operand_type imm32
= OPERAND_TYPE_IMM32
;
1851 static const i386_operand_type imm32s
= OPERAND_TYPE_IMM32S
;
1852 static const i386_operand_type imm64
= OPERAND_TYPE_IMM64
;
1853 static const i386_operand_type imm16_32
= OPERAND_TYPE_IMM16_32
;
1854 static const i386_operand_type imm16_32s
= OPERAND_TYPE_IMM16_32S
;
1855 static const i386_operand_type imm16_32_32s
= OPERAND_TYPE_IMM16_32_32S
;
1856 static const i386_operand_type vec_imm4
= OPERAND_TYPE_VEC_IMM4
;
1867 operand_type_check (i386_operand_type t
, enum operand_type c
)
1872 return t
.bitfield
.reg
;
1875 return (t
.bitfield
.imm8
1879 || t
.bitfield
.imm32s
1880 || t
.bitfield
.imm64
);
1883 return (t
.bitfield
.disp8
1884 || t
.bitfield
.disp16
1885 || t
.bitfield
.disp32
1886 || t
.bitfield
.disp32s
1887 || t
.bitfield
.disp64
);
1890 return (t
.bitfield
.disp8
1891 || t
.bitfield
.disp16
1892 || t
.bitfield
.disp32
1893 || t
.bitfield
.disp32s
1894 || t
.bitfield
.disp64
1895 || t
.bitfield
.baseindex
);
1904 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit/80bit on
1905 operand J for instruction template T. */
1908 match_reg_size (const insn_template
*t
, unsigned int j
)
1910 return !((i
.types
[j
].bitfield
.byte
1911 && !t
->operand_types
[j
].bitfield
.byte
)
1912 || (i
.types
[j
].bitfield
.word
1913 && !t
->operand_types
[j
].bitfield
.word
)
1914 || (i
.types
[j
].bitfield
.dword
1915 && !t
->operand_types
[j
].bitfield
.dword
)
1916 || (i
.types
[j
].bitfield
.qword
1917 && !t
->operand_types
[j
].bitfield
.qword
)
1918 || (i
.types
[j
].bitfield
.tbyte
1919 && !t
->operand_types
[j
].bitfield
.tbyte
));
1922 /* Return 1 if there is no conflict in SIMD register on
1923 operand J for instruction template T. */
1926 match_simd_size (const insn_template
*t
, unsigned int j
)
1928 return !((i
.types
[j
].bitfield
.xmmword
1929 && !t
->operand_types
[j
].bitfield
.xmmword
)
1930 || (i
.types
[j
].bitfield
.ymmword
1931 && !t
->operand_types
[j
].bitfield
.ymmword
)
1932 || (i
.types
[j
].bitfield
.zmmword
1933 && !t
->operand_types
[j
].bitfield
.zmmword
));
1936 /* Return 1 if there is no conflict in any size on operand J for
1937 instruction template T. */
1940 match_mem_size (const insn_template
*t
, unsigned int j
)
1942 return (match_reg_size (t
, j
)
1943 && !((i
.types
[j
].bitfield
.unspecified
1945 && !t
->operand_types
[j
].bitfield
.unspecified
)
1946 || (i
.types
[j
].bitfield
.fword
1947 && !t
->operand_types
[j
].bitfield
.fword
)
1948 /* For scalar opcode templates to allow register and memory
1949 operands at the same time, some special casing is needed
1950 here. Also for v{,p}broadcast*, {,v}pmov{s,z}*, and
1951 down-conversion vpmov*. */
1952 || ((t
->operand_types
[j
].bitfield
.regsimd
1953 && !t
->opcode_modifier
.broadcast
1954 && (t
->operand_types
[j
].bitfield
.byte
1955 || t
->operand_types
[j
].bitfield
.word
1956 || t
->operand_types
[j
].bitfield
.dword
1957 || t
->operand_types
[j
].bitfield
.qword
))
1958 ? (i
.types
[j
].bitfield
.xmmword
1959 || i
.types
[j
].bitfield
.ymmword
1960 || i
.types
[j
].bitfield
.zmmword
)
1961 : !match_simd_size(t
, j
))));
1964 /* Return 1 if there is no size conflict on any operands for
1965 instruction template T. */
1968 operand_size_match (const insn_template
*t
)
1973 /* Don't check jump instructions. */
1974 if (t
->opcode_modifier
.jump
1975 || t
->opcode_modifier
.jumpbyte
1976 || t
->opcode_modifier
.jumpdword
1977 || t
->opcode_modifier
.jumpintersegment
)
1980 /* Check memory and accumulator operand size. */
1981 for (j
= 0; j
< i
.operands
; j
++)
1983 if (!i
.types
[j
].bitfield
.reg
&& !i
.types
[j
].bitfield
.regsimd
1984 && t
->operand_types
[j
].bitfield
.anysize
)
1987 if (t
->operand_types
[j
].bitfield
.reg
1988 && !match_reg_size (t
, j
))
1994 if (t
->operand_types
[j
].bitfield
.regsimd
1995 && !match_simd_size (t
, j
))
2001 if (t
->operand_types
[j
].bitfield
.acc
2002 && (!match_reg_size (t
, j
) || !match_simd_size (t
, j
)))
2008 if (i
.types
[j
].bitfield
.mem
&& !match_mem_size (t
, j
))
2017 else if (!t
->opcode_modifier
.d
)
2020 i
.error
= operand_size_mismatch
;
2024 /* Check reverse. */
2025 gas_assert (i
.operands
== 2);
2028 for (j
= 0; j
< 2; j
++)
2030 if ((t
->operand_types
[j
].bitfield
.reg
2031 || t
->operand_types
[j
].bitfield
.acc
)
2032 && !match_reg_size (t
, j
? 0 : 1))
2035 if (i
.types
[j
].bitfield
.mem
2036 && !match_mem_size (t
, j
? 0 : 1))
2044 operand_type_match (i386_operand_type overlap
,
2045 i386_operand_type given
)
2047 i386_operand_type temp
= overlap
;
2049 temp
.bitfield
.jumpabsolute
= 0;
2050 temp
.bitfield
.unspecified
= 0;
2051 temp
.bitfield
.byte
= 0;
2052 temp
.bitfield
.word
= 0;
2053 temp
.bitfield
.dword
= 0;
2054 temp
.bitfield
.fword
= 0;
2055 temp
.bitfield
.qword
= 0;
2056 temp
.bitfield
.tbyte
= 0;
2057 temp
.bitfield
.xmmword
= 0;
2058 temp
.bitfield
.ymmword
= 0;
2059 temp
.bitfield
.zmmword
= 0;
2060 if (operand_type_all_zero (&temp
))
2063 if (given
.bitfield
.baseindex
== overlap
.bitfield
.baseindex
2064 && given
.bitfield
.jumpabsolute
== overlap
.bitfield
.jumpabsolute
)
2068 i
.error
= operand_type_mismatch
;
2072 /* If given types g0 and g1 are registers they must be of the same type
2073 unless the expected operand type register overlap is null.
2074 Memory operand size of certain SIMD instructions is also being checked
2078 operand_type_register_match (i386_operand_type g0
,
2079 i386_operand_type t0
,
2080 i386_operand_type g1
,
2081 i386_operand_type t1
)
2083 if (!g0
.bitfield
.reg
2084 && !g0
.bitfield
.regsimd
2085 && (!operand_type_check (g0
, anymem
)
2086 || g0
.bitfield
.unspecified
2087 || !t0
.bitfield
.regsimd
))
2090 if (!g1
.bitfield
.reg
2091 && !g1
.bitfield
.regsimd
2092 && (!operand_type_check (g1
, anymem
)
2093 || g1
.bitfield
.unspecified
2094 || !t1
.bitfield
.regsimd
))
2097 if (g0
.bitfield
.byte
== g1
.bitfield
.byte
2098 && g0
.bitfield
.word
== g1
.bitfield
.word
2099 && g0
.bitfield
.dword
== g1
.bitfield
.dword
2100 && g0
.bitfield
.qword
== g1
.bitfield
.qword
2101 && g0
.bitfield
.xmmword
== g1
.bitfield
.xmmword
2102 && g0
.bitfield
.ymmword
== g1
.bitfield
.ymmword
2103 && g0
.bitfield
.zmmword
== g1
.bitfield
.zmmword
)
2106 if (!(t0
.bitfield
.byte
& t1
.bitfield
.byte
)
2107 && !(t0
.bitfield
.word
& t1
.bitfield
.word
)
2108 && !(t0
.bitfield
.dword
& t1
.bitfield
.dword
)
2109 && !(t0
.bitfield
.qword
& t1
.bitfield
.qword
)
2110 && !(t0
.bitfield
.xmmword
& t1
.bitfield
.xmmword
)
2111 && !(t0
.bitfield
.ymmword
& t1
.bitfield
.ymmword
)
2112 && !(t0
.bitfield
.zmmword
& t1
.bitfield
.zmmword
))
2115 i
.error
= register_type_mismatch
;
2120 static INLINE
unsigned int
2121 register_number (const reg_entry
*r
)
2123 unsigned int nr
= r
->reg_num
;
2125 if (r
->reg_flags
& RegRex
)
2128 if (r
->reg_flags
& RegVRex
)
2134 static INLINE
unsigned int
2135 mode_from_disp_size (i386_operand_type t
)
2137 if (t
.bitfield
.disp8
)
2139 else if (t
.bitfield
.disp16
2140 || t
.bitfield
.disp32
2141 || t
.bitfield
.disp32s
)
2148 fits_in_signed_byte (addressT num
)
2150 return num
+ 0x80 <= 0xff;
2154 fits_in_unsigned_byte (addressT num
)
2160 fits_in_unsigned_word (addressT num
)
2162 return num
<= 0xffff;
2166 fits_in_signed_word (addressT num
)
2168 return num
+ 0x8000 <= 0xffff;
2172 fits_in_signed_long (addressT num ATTRIBUTE_UNUSED
)
2177 return num
+ 0x80000000 <= 0xffffffff;
2179 } /* fits_in_signed_long() */
2182 fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED
)
2187 return num
<= 0xffffffff;
2189 } /* fits_in_unsigned_long() */
2192 fits_in_disp8 (offsetT num
)
2194 int shift
= i
.memshift
;
2200 mask
= (1 << shift
) - 1;
2202 /* Return 0 if NUM isn't properly aligned. */
2206 /* Check if NUM will fit in 8bit after shift. */
2207 return fits_in_signed_byte (num
>> shift
);
2211 fits_in_imm4 (offsetT num
)
2213 return (num
& 0xf) == num
;
2216 static i386_operand_type
2217 smallest_imm_type (offsetT num
)
2219 i386_operand_type t
;
2221 operand_type_set (&t
, 0);
2222 t
.bitfield
.imm64
= 1;
2224 if (cpu_arch_tune
!= PROCESSOR_I486
&& num
== 1)
2226 /* This code is disabled on the 486 because all the Imm1 forms
2227 in the opcode table are slower on the i486. They're the
2228 versions with the implicitly specified single-position
2229 displacement, which has another syntax if you really want to
2231 t
.bitfield
.imm1
= 1;
2232 t
.bitfield
.imm8
= 1;
2233 t
.bitfield
.imm8s
= 1;
2234 t
.bitfield
.imm16
= 1;
2235 t
.bitfield
.imm32
= 1;
2236 t
.bitfield
.imm32s
= 1;
2238 else if (fits_in_signed_byte (num
))
2240 t
.bitfield
.imm8
= 1;
2241 t
.bitfield
.imm8s
= 1;
2242 t
.bitfield
.imm16
= 1;
2243 t
.bitfield
.imm32
= 1;
2244 t
.bitfield
.imm32s
= 1;
2246 else if (fits_in_unsigned_byte (num
))
2248 t
.bitfield
.imm8
= 1;
2249 t
.bitfield
.imm16
= 1;
2250 t
.bitfield
.imm32
= 1;
2251 t
.bitfield
.imm32s
= 1;
2253 else if (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
2255 t
.bitfield
.imm16
= 1;
2256 t
.bitfield
.imm32
= 1;
2257 t
.bitfield
.imm32s
= 1;
2259 else if (fits_in_signed_long (num
))
2261 t
.bitfield
.imm32
= 1;
2262 t
.bitfield
.imm32s
= 1;
2264 else if (fits_in_unsigned_long (num
))
2265 t
.bitfield
.imm32
= 1;
2271 offset_in_range (offsetT val
, int size
)
2277 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
2278 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
2279 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
2281 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
2287 /* If BFD64, sign extend val for 32bit address mode. */
2288 if (flag_code
!= CODE_64BIT
2289 || i
.prefix
[ADDR_PREFIX
])
2290 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
2291 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
2294 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
2296 char buf1
[40], buf2
[40];
2298 sprint_value (buf1
, val
);
2299 sprint_value (buf2
, val
& mask
);
2300 as_warn (_("%s shortened to %s"), buf1
, buf2
);
2315 a. PREFIX_EXIST if attempting to add a prefix where one from the
2316 same class already exists.
2317 b. PREFIX_LOCK if lock prefix is added.
2318 c. PREFIX_REP if rep/repne prefix is added.
2319 d. PREFIX_DS if ds prefix is added.
2320 e. PREFIX_OTHER if other prefix is added.
2323 static enum PREFIX_GROUP
2324 add_prefix (unsigned int prefix
)
2326 enum PREFIX_GROUP ret
= PREFIX_OTHER
;
2329 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
2330 && flag_code
== CODE_64BIT
)
2332 if ((i
.prefix
[REX_PREFIX
] & prefix
& REX_W
)
2333 || ((i
.prefix
[REX_PREFIX
] & (REX_R
| REX_X
| REX_B
))
2334 && (prefix
& (REX_R
| REX_X
| REX_B
))))
2345 case DS_PREFIX_OPCODE
:
2348 case CS_PREFIX_OPCODE
:
2349 case ES_PREFIX_OPCODE
:
2350 case FS_PREFIX_OPCODE
:
2351 case GS_PREFIX_OPCODE
:
2352 case SS_PREFIX_OPCODE
:
2356 case REPNE_PREFIX_OPCODE
:
2357 case REPE_PREFIX_OPCODE
:
2362 case LOCK_PREFIX_OPCODE
:
2371 case ADDR_PREFIX_OPCODE
:
2375 case DATA_PREFIX_OPCODE
:
2379 if (i
.prefix
[q
] != 0)
2387 i
.prefix
[q
] |= prefix
;
2390 as_bad (_("same type of prefix used twice"));
2396 update_code_flag (int value
, int check
)
2398 PRINTF_LIKE ((*as_error
));
2400 flag_code
= (enum flag_code
) value
;
2401 if (flag_code
== CODE_64BIT
)
2403 cpu_arch_flags
.bitfield
.cpu64
= 1;
2404 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2408 cpu_arch_flags
.bitfield
.cpu64
= 0;
2409 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2411 if (value
== CODE_64BIT
&& !cpu_arch_flags
.bitfield
.cpulm
)
2414 as_error
= as_fatal
;
2417 (*as_error
) (_("64bit mode not supported on `%s'."),
2418 cpu_arch_name
? cpu_arch_name
: default_arch
);
2420 if (value
== CODE_32BIT
&& !cpu_arch_flags
.bitfield
.cpui386
)
2423 as_error
= as_fatal
;
2426 (*as_error
) (_("32bit mode not supported on `%s'."),
2427 cpu_arch_name
? cpu_arch_name
: default_arch
);
2429 stackop_size
= '\0';
2433 set_code_flag (int value
)
2435 update_code_flag (value
, 0);
2439 set_16bit_gcc_code_flag (int new_code_flag
)
2441 flag_code
= (enum flag_code
) new_code_flag
;
2442 if (flag_code
!= CODE_16BIT
)
2444 cpu_arch_flags
.bitfield
.cpu64
= 0;
2445 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2446 stackop_size
= LONG_MNEM_SUFFIX
;
2450 set_intel_syntax (int syntax_flag
)
2452 /* Find out if register prefixing is specified. */
2453 int ask_naked_reg
= 0;
2456 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2459 int e
= get_symbol_name (&string
);
2461 if (strcmp (string
, "prefix") == 0)
2463 else if (strcmp (string
, "noprefix") == 0)
2466 as_bad (_("bad argument to syntax directive."));
2467 (void) restore_line_pointer (e
);
2469 demand_empty_rest_of_line ();
2471 intel_syntax
= syntax_flag
;
2473 if (ask_naked_reg
== 0)
2474 allow_naked_reg
= (intel_syntax
2475 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
2477 allow_naked_reg
= (ask_naked_reg
< 0);
2479 expr_set_rank (O_full_ptr
, syntax_flag
? 10 : 0);
2481 identifier_chars
['%'] = intel_syntax
&& allow_naked_reg
? '%' : 0;
2482 identifier_chars
['$'] = intel_syntax
? '$' : 0;
2483 register_prefix
= allow_naked_reg
? "" : "%";
2487 set_intel_mnemonic (int mnemonic_flag
)
2489 intel_mnemonic
= mnemonic_flag
;
2493 set_allow_index_reg (int flag
)
2495 allow_index_reg
= flag
;
2499 set_check (int what
)
2501 enum check_kind
*kind
;
2506 kind
= &operand_check
;
2517 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2520 int e
= get_symbol_name (&string
);
2522 if (strcmp (string
, "none") == 0)
2524 else if (strcmp (string
, "warning") == 0)
2525 *kind
= check_warning
;
2526 else if (strcmp (string
, "error") == 0)
2527 *kind
= check_error
;
2529 as_bad (_("bad argument to %s_check directive."), str
);
2530 (void) restore_line_pointer (e
);
2533 as_bad (_("missing argument for %s_check directive"), str
);
2535 demand_empty_rest_of_line ();
2539 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED
,
2540 i386_cpu_flags new_flag ATTRIBUTE_UNUSED
)
2542 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2543 static const char *arch
;
2545 /* Intel LIOM is only supported on ELF. */
2551 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2552 use default_arch. */
2553 arch
= cpu_arch_name
;
2555 arch
= default_arch
;
2558 /* If we are targeting Intel MCU, we must enable it. */
2559 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_IAMCU
2560 || new_flag
.bitfield
.cpuiamcu
)
2563 /* If we are targeting Intel L1OM, we must enable it. */
2564 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_L1OM
2565 || new_flag
.bitfield
.cpul1om
)
2568 /* If we are targeting Intel K1OM, we must enable it. */
2569 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_K1OM
2570 || new_flag
.bitfield
.cpuk1om
)
2573 as_bad (_("`%s' is not supported on `%s'"), name
, arch
);
2578 set_cpu_arch (int dummy ATTRIBUTE_UNUSED
)
2582 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2585 int e
= get_symbol_name (&string
);
2587 i386_cpu_flags flags
;
2589 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
2591 if (strcmp (string
, cpu_arch
[j
].name
) == 0)
2593 check_cpu_arch_compatible (string
, cpu_arch
[j
].flags
);
2597 cpu_arch_name
= cpu_arch
[j
].name
;
2598 cpu_sub_arch_name
= NULL
;
2599 cpu_arch_flags
= cpu_arch
[j
].flags
;
2600 if (flag_code
== CODE_64BIT
)
2602 cpu_arch_flags
.bitfield
.cpu64
= 1;
2603 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2607 cpu_arch_flags
.bitfield
.cpu64
= 0;
2608 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2610 cpu_arch_isa
= cpu_arch
[j
].type
;
2611 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
2612 if (!cpu_arch_tune_set
)
2614 cpu_arch_tune
= cpu_arch_isa
;
2615 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
2620 flags
= cpu_flags_or (cpu_arch_flags
,
2623 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2625 if (cpu_sub_arch_name
)
2627 char *name
= cpu_sub_arch_name
;
2628 cpu_sub_arch_name
= concat (name
,
2630 (const char *) NULL
);
2634 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
2635 cpu_arch_flags
= flags
;
2636 cpu_arch_isa_flags
= flags
;
2640 = cpu_flags_or (cpu_arch_isa_flags
,
2642 (void) restore_line_pointer (e
);
2643 demand_empty_rest_of_line ();
2648 if (*string
== '.' && j
>= ARRAY_SIZE (cpu_arch
))
2650 /* Disable an ISA extension. */
2651 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
2652 if (strcmp (string
+ 1, cpu_noarch
[j
].name
) == 0)
2654 flags
= cpu_flags_and_not (cpu_arch_flags
,
2655 cpu_noarch
[j
].flags
);
2656 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2658 if (cpu_sub_arch_name
)
2660 char *name
= cpu_sub_arch_name
;
2661 cpu_sub_arch_name
= concat (name
, string
,
2662 (const char *) NULL
);
2666 cpu_sub_arch_name
= xstrdup (string
);
2667 cpu_arch_flags
= flags
;
2668 cpu_arch_isa_flags
= flags
;
2670 (void) restore_line_pointer (e
);
2671 demand_empty_rest_of_line ();
2675 j
= ARRAY_SIZE (cpu_arch
);
2678 if (j
>= ARRAY_SIZE (cpu_arch
))
2679 as_bad (_("no such architecture: `%s'"), string
);
2681 *input_line_pointer
= e
;
2684 as_bad (_("missing cpu architecture"));
2686 no_cond_jump_promotion
= 0;
2687 if (*input_line_pointer
== ','
2688 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
2693 ++input_line_pointer
;
2694 e
= get_symbol_name (&string
);
2696 if (strcmp (string
, "nojumps") == 0)
2697 no_cond_jump_promotion
= 1;
2698 else if (strcmp (string
, "jumps") == 0)
2701 as_bad (_("no such architecture modifier: `%s'"), string
);
2703 (void) restore_line_pointer (e
);
2706 demand_empty_rest_of_line ();
2709 enum bfd_architecture
2712 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2714 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2715 || flag_code
!= CODE_64BIT
)
2716 as_fatal (_("Intel L1OM is 64bit ELF only"));
2717 return bfd_arch_l1om
;
2719 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2721 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2722 || flag_code
!= CODE_64BIT
)
2723 as_fatal (_("Intel K1OM is 64bit ELF only"));
2724 return bfd_arch_k1om
;
2726 else if (cpu_arch_isa
== PROCESSOR_IAMCU
)
2728 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2729 || flag_code
== CODE_64BIT
)
2730 as_fatal (_("Intel MCU is 32bit ELF only"));
2731 return bfd_arch_iamcu
;
2734 return bfd_arch_i386
;
2740 if (!strncmp (default_arch
, "x86_64", 6))
2742 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2744 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2745 || default_arch
[6] != '\0')
2746 as_fatal (_("Intel L1OM is 64bit ELF only"));
2747 return bfd_mach_l1om
;
2749 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2751 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2752 || default_arch
[6] != '\0')
2753 as_fatal (_("Intel K1OM is 64bit ELF only"));
2754 return bfd_mach_k1om
;
2756 else if (default_arch
[6] == '\0')
2757 return bfd_mach_x86_64
;
2759 return bfd_mach_x64_32
;
2761 else if (!strcmp (default_arch
, "i386")
2762 || !strcmp (default_arch
, "iamcu"))
2764 if (cpu_arch_isa
== PROCESSOR_IAMCU
)
2766 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
2767 as_fatal (_("Intel MCU is 32bit ELF only"));
2768 return bfd_mach_i386_iamcu
;
2771 return bfd_mach_i386_i386
;
2774 as_fatal (_("unknown architecture"));
2780 const char *hash_err
;
2782 /* Support pseudo prefixes like {disp32}. */
2783 lex_type
['{'] = LEX_BEGIN_NAME
;
2785 /* Initialize op_hash hash table. */
2786 op_hash
= hash_new ();
2789 const insn_template
*optab
;
2790 templates
*core_optab
;
2792 /* Setup for loop. */
2794 core_optab
= XNEW (templates
);
2795 core_optab
->start
= optab
;
2800 if (optab
->name
== NULL
2801 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
2803 /* different name --> ship out current template list;
2804 add to hash table; & begin anew. */
2805 core_optab
->end
= optab
;
2806 hash_err
= hash_insert (op_hash
,
2808 (void *) core_optab
);
2811 as_fatal (_("can't hash %s: %s"),
2815 if (optab
->name
== NULL
)
2817 core_optab
= XNEW (templates
);
2818 core_optab
->start
= optab
;
2823 /* Initialize reg_hash hash table. */
2824 reg_hash
= hash_new ();
2826 const reg_entry
*regtab
;
2827 unsigned int regtab_size
= i386_regtab_size
;
2829 for (regtab
= i386_regtab
; regtab_size
--; regtab
++)
2831 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (void *) regtab
);
2833 as_fatal (_("can't hash %s: %s"),
2839 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
2844 for (c
= 0; c
< 256; c
++)
2849 mnemonic_chars
[c
] = c
;
2850 register_chars
[c
] = c
;
2851 operand_chars
[c
] = c
;
2853 else if (ISLOWER (c
))
2855 mnemonic_chars
[c
] = c
;
2856 register_chars
[c
] = c
;
2857 operand_chars
[c
] = c
;
2859 else if (ISUPPER (c
))
2861 mnemonic_chars
[c
] = TOLOWER (c
);
2862 register_chars
[c
] = mnemonic_chars
[c
];
2863 operand_chars
[c
] = c
;
2865 else if (c
== '{' || c
== '}')
2867 mnemonic_chars
[c
] = c
;
2868 operand_chars
[c
] = c
;
2871 if (ISALPHA (c
) || ISDIGIT (c
))
2872 identifier_chars
[c
] = c
;
2875 identifier_chars
[c
] = c
;
2876 operand_chars
[c
] = c
;
2881 identifier_chars
['@'] = '@';
2884 identifier_chars
['?'] = '?';
2885 operand_chars
['?'] = '?';
2887 digit_chars
['-'] = '-';
2888 mnemonic_chars
['_'] = '_';
2889 mnemonic_chars
['-'] = '-';
2890 mnemonic_chars
['.'] = '.';
2891 identifier_chars
['_'] = '_';
2892 identifier_chars
['.'] = '.';
2894 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
2895 operand_chars
[(unsigned char) *p
] = *p
;
2898 if (flag_code
== CODE_64BIT
)
2900 #if defined (OBJ_COFF) && defined (TE_PE)
2901 x86_dwarf2_return_column
= (OUTPUT_FLAVOR
== bfd_target_coff_flavour
2904 x86_dwarf2_return_column
= 16;
2906 x86_cie_data_alignment
= -8;
2910 x86_dwarf2_return_column
= 8;
2911 x86_cie_data_alignment
= -4;
2916 i386_print_statistics (FILE *file
)
2918 hash_print_statistics (file
, "i386 opcode", op_hash
);
2919 hash_print_statistics (file
, "i386 register", reg_hash
);
2924 /* Debugging routines for md_assemble. */
2925 static void pte (insn_template
*);
2926 static void pt (i386_operand_type
);
2927 static void pe (expressionS
*);
2928 static void ps (symbolS
*);
2931 pi (char *line
, i386_insn
*x
)
2935 fprintf (stdout
, "%s: template ", line
);
2937 fprintf (stdout
, " address: base %s index %s scale %x\n",
2938 x
->base_reg
? x
->base_reg
->reg_name
: "none",
2939 x
->index_reg
? x
->index_reg
->reg_name
: "none",
2940 x
->log2_scale_factor
);
2941 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
2942 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
2943 fprintf (stdout
, " sib: base %x index %x scale %x\n",
2944 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
2945 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
2946 (x
->rex
& REX_W
) != 0,
2947 (x
->rex
& REX_R
) != 0,
2948 (x
->rex
& REX_X
) != 0,
2949 (x
->rex
& REX_B
) != 0);
2950 for (j
= 0; j
< x
->operands
; j
++)
2952 fprintf (stdout
, " #%d: ", j
+ 1);
2954 fprintf (stdout
, "\n");
2955 if (x
->types
[j
].bitfield
.reg
2956 || x
->types
[j
].bitfield
.regmmx
2957 || x
->types
[j
].bitfield
.regsimd
2958 || x
->types
[j
].bitfield
.sreg2
2959 || x
->types
[j
].bitfield
.sreg3
2960 || x
->types
[j
].bitfield
.control
2961 || x
->types
[j
].bitfield
.debug
2962 || x
->types
[j
].bitfield
.test
)
2963 fprintf (stdout
, "%s\n", x
->op
[j
].regs
->reg_name
);
2964 if (operand_type_check (x
->types
[j
], imm
))
2966 if (operand_type_check (x
->types
[j
], disp
))
2967 pe (x
->op
[j
].disps
);
2972 pte (insn_template
*t
)
2975 fprintf (stdout
, " %d operands ", t
->operands
);
2976 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
2977 if (t
->extension_opcode
!= None
)
2978 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
2979 if (t
->opcode_modifier
.d
)
2980 fprintf (stdout
, "D");
2981 if (t
->opcode_modifier
.w
)
2982 fprintf (stdout
, "W");
2983 fprintf (stdout
, "\n");
2984 for (j
= 0; j
< t
->operands
; j
++)
2986 fprintf (stdout
, " #%d type ", j
+ 1);
2987 pt (t
->operand_types
[j
]);
2988 fprintf (stdout
, "\n");
2995 fprintf (stdout
, " operation %d\n", e
->X_op
);
2996 fprintf (stdout
, " add_number %ld (%lx)\n",
2997 (long) e
->X_add_number
, (long) e
->X_add_number
);
2998 if (e
->X_add_symbol
)
3000 fprintf (stdout
, " add_symbol ");
3001 ps (e
->X_add_symbol
);
3002 fprintf (stdout
, "\n");
3006 fprintf (stdout
, " op_symbol ");
3007 ps (e
->X_op_symbol
);
3008 fprintf (stdout
, "\n");
3015 fprintf (stdout
, "%s type %s%s",
3017 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
3018 segment_name (S_GET_SEGMENT (s
)));
3021 static struct type_name
3023 i386_operand_type mask
;
3026 const type_names
[] =
3028 { OPERAND_TYPE_REG8
, "r8" },
3029 { OPERAND_TYPE_REG16
, "r16" },
3030 { OPERAND_TYPE_REG32
, "r32" },
3031 { OPERAND_TYPE_REG64
, "r64" },
3032 { OPERAND_TYPE_IMM8
, "i8" },
3033 { OPERAND_TYPE_IMM8
, "i8s" },
3034 { OPERAND_TYPE_IMM16
, "i16" },
3035 { OPERAND_TYPE_IMM32
, "i32" },
3036 { OPERAND_TYPE_IMM32S
, "i32s" },
3037 { OPERAND_TYPE_IMM64
, "i64" },
3038 { OPERAND_TYPE_IMM1
, "i1" },
3039 { OPERAND_TYPE_BASEINDEX
, "BaseIndex" },
3040 { OPERAND_TYPE_DISP8
, "d8" },
3041 { OPERAND_TYPE_DISP16
, "d16" },
3042 { OPERAND_TYPE_DISP32
, "d32" },
3043 { OPERAND_TYPE_DISP32S
, "d32s" },
3044 { OPERAND_TYPE_DISP64
, "d64" },
3045 { OPERAND_TYPE_INOUTPORTREG
, "InOutPortReg" },
3046 { OPERAND_TYPE_SHIFTCOUNT
, "ShiftCount" },
3047 { OPERAND_TYPE_CONTROL
, "control reg" },
3048 { OPERAND_TYPE_TEST
, "test reg" },
3049 { OPERAND_TYPE_DEBUG
, "debug reg" },
3050 { OPERAND_TYPE_FLOATREG
, "FReg" },
3051 { OPERAND_TYPE_FLOATACC
, "FAcc" },
3052 { OPERAND_TYPE_SREG2
, "SReg2" },
3053 { OPERAND_TYPE_SREG3
, "SReg3" },
3054 { OPERAND_TYPE_ACC
, "Acc" },
3055 { OPERAND_TYPE_JUMPABSOLUTE
, "Jump Absolute" },
3056 { OPERAND_TYPE_REGMMX
, "rMMX" },
3057 { OPERAND_TYPE_REGXMM
, "rXMM" },
3058 { OPERAND_TYPE_REGYMM
, "rYMM" },
3059 { OPERAND_TYPE_REGZMM
, "rZMM" },
3060 { OPERAND_TYPE_REGMASK
, "Mask reg" },
3061 { OPERAND_TYPE_ESSEG
, "es" },
3065 pt (i386_operand_type t
)
3068 i386_operand_type a
;
3070 for (j
= 0; j
< ARRAY_SIZE (type_names
); j
++)
3072 a
= operand_type_and (t
, type_names
[j
].mask
);
3073 if (!operand_type_all_zero (&a
))
3074 fprintf (stdout
, "%s, ", type_names
[j
].name
);
3079 #endif /* DEBUG386 */
3081 static bfd_reloc_code_real_type
3082 reloc (unsigned int size
,
3085 bfd_reloc_code_real_type other
)
3087 if (other
!= NO_RELOC
)
3089 reloc_howto_type
*rel
;
3094 case BFD_RELOC_X86_64_GOT32
:
3095 return BFD_RELOC_X86_64_GOT64
;
3097 case BFD_RELOC_X86_64_GOTPLT64
:
3098 return BFD_RELOC_X86_64_GOTPLT64
;
3100 case BFD_RELOC_X86_64_PLTOFF64
:
3101 return BFD_RELOC_X86_64_PLTOFF64
;
3103 case BFD_RELOC_X86_64_GOTPC32
:
3104 other
= BFD_RELOC_X86_64_GOTPC64
;
3106 case BFD_RELOC_X86_64_GOTPCREL
:
3107 other
= BFD_RELOC_X86_64_GOTPCREL64
;
3109 case BFD_RELOC_X86_64_TPOFF32
:
3110 other
= BFD_RELOC_X86_64_TPOFF64
;
3112 case BFD_RELOC_X86_64_DTPOFF32
:
3113 other
= BFD_RELOC_X86_64_DTPOFF64
;
3119 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3120 if (other
== BFD_RELOC_SIZE32
)
3123 other
= BFD_RELOC_SIZE64
;
3126 as_bad (_("there are no pc-relative size relocations"));
3132 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
3133 if (size
== 4 && (flag_code
!= CODE_64BIT
|| disallow_64bit_reloc
))
3136 rel
= bfd_reloc_type_lookup (stdoutput
, other
);
3138 as_bad (_("unknown relocation (%u)"), other
);
3139 else if (size
!= bfd_get_reloc_size (rel
))
3140 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
3141 bfd_get_reloc_size (rel
),
3143 else if (pcrel
&& !rel
->pc_relative
)
3144 as_bad (_("non-pc-relative relocation for pc-relative field"));
3145 else if ((rel
->complain_on_overflow
== complain_overflow_signed
3147 || (rel
->complain_on_overflow
== complain_overflow_unsigned
3149 as_bad (_("relocated field and relocation type differ in signedness"));
3158 as_bad (_("there are no unsigned pc-relative relocations"));
3161 case 1: return BFD_RELOC_8_PCREL
;
3162 case 2: return BFD_RELOC_16_PCREL
;
3163 case 4: return BFD_RELOC_32_PCREL
;
3164 case 8: return BFD_RELOC_64_PCREL
;
3166 as_bad (_("cannot do %u byte pc-relative relocation"), size
);
3173 case 4: return BFD_RELOC_X86_64_32S
;
3178 case 1: return BFD_RELOC_8
;
3179 case 2: return BFD_RELOC_16
;
3180 case 4: return BFD_RELOC_32
;
3181 case 8: return BFD_RELOC_64
;
3183 as_bad (_("cannot do %s %u byte relocation"),
3184 sign
> 0 ? "signed" : "unsigned", size
);
3190 /* Here we decide which fixups can be adjusted to make them relative to
3191 the beginning of the section instead of the symbol. Basically we need
3192 to make sure that the dynamic relocations are done correctly, so in
3193 some cases we force the original symbol to be used. */
3196 tc_i386_fix_adjustable (fixS
*fixP ATTRIBUTE_UNUSED
)
3198 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3202 /* Don't adjust pc-relative references to merge sections in 64-bit
3204 if (use_rela_relocations
3205 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
3209 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
3210 and changed later by validate_fix. */
3211 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
3212 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
3215 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
3216 for size relocations. */
3217 if (fixP
->fx_r_type
== BFD_RELOC_SIZE32
3218 || fixP
->fx_r_type
== BFD_RELOC_SIZE64
3219 || fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
3220 || fixP
->fx_r_type
== BFD_RELOC_386_PLT32
3221 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
3222 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32X
3223 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
3224 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
3225 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
3226 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
3227 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
3228 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
3229 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
3230 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
3231 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTDESC
3232 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_DESC_CALL
3233 || fixP
->fx_r_type
== BFD_RELOC_X86_64_PLT32
3234 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
3235 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
3236 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCRELX
3237 || fixP
->fx_r_type
== BFD_RELOC_X86_64_REX_GOTPCRELX
3238 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
3239 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
3240 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
3241 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
3242 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
3243 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
3244 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
3245 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
3246 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPC32_TLSDESC
3247 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSDESC_CALL
3248 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
3249 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
3256 intel_float_operand (const char *mnemonic
)
3258 /* Note that the value returned is meaningful only for opcodes with (memory)
3259 operands, hence the code here is free to improperly handle opcodes that
3260 have no operands (for better performance and smaller code). */
3262 if (mnemonic
[0] != 'f')
3263 return 0; /* non-math */
3265 switch (mnemonic
[1])
3267 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
3268 the fs segment override prefix not currently handled because no
3269 call path can make opcodes without operands get here */
3271 return 2 /* integer op */;
3273 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
3274 return 3; /* fldcw/fldenv */
3277 if (mnemonic
[2] != 'o' /* fnop */)
3278 return 3; /* non-waiting control op */
3281 if (mnemonic
[2] == 's')
3282 return 3; /* frstor/frstpm */
3285 if (mnemonic
[2] == 'a')
3286 return 3; /* fsave */
3287 if (mnemonic
[2] == 't')
3289 switch (mnemonic
[3])
3291 case 'c': /* fstcw */
3292 case 'd': /* fstdw */
3293 case 'e': /* fstenv */
3294 case 's': /* fsts[gw] */
3300 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
3301 return 0; /* fxsave/fxrstor are not really math ops */
3308 /* Build the VEX prefix. */
3311 build_vex_prefix (const insn_template
*t
)
3313 unsigned int register_specifier
;
3314 unsigned int implied_prefix
;
3315 unsigned int vector_length
;
3317 /* Check register specifier. */
3318 if (i
.vex
.register_specifier
)
3320 register_specifier
=
3321 ~register_number (i
.vex
.register_specifier
) & 0xf;
3322 gas_assert ((i
.vex
.register_specifier
->reg_flags
& RegVRex
) == 0);
3325 register_specifier
= 0xf;
3327 /* Use 2-byte VEX prefix by swapping destination and source
3329 if (i
.vec_encoding
!= vex_encoding_vex3
3330 && i
.dir_encoding
== dir_encoding_default
3331 && i
.operands
== i
.reg_operands
3332 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3333 && i
.tm
.opcode_modifier
.load
3336 unsigned int xchg
= i
.operands
- 1;
3337 union i386_op temp_op
;
3338 i386_operand_type temp_type
;
3340 temp_type
= i
.types
[xchg
];
3341 i
.types
[xchg
] = i
.types
[0];
3342 i
.types
[0] = temp_type
;
3343 temp_op
= i
.op
[xchg
];
3344 i
.op
[xchg
] = i
.op
[0];
3347 gas_assert (i
.rm
.mode
== 3);
3351 i
.rm
.regmem
= i
.rm
.reg
;
3354 /* Use the next insn. */
3358 if (i
.tm
.opcode_modifier
.vex
== VEXScalar
)
3359 vector_length
= avxscalar
;
3360 else if (i
.tm
.opcode_modifier
.vex
== VEX256
)
3367 for (op
= 0; op
< t
->operands
; ++op
)
3368 if (t
->operand_types
[op
].bitfield
.xmmword
3369 && t
->operand_types
[op
].bitfield
.ymmword
3370 && i
.types
[op
].bitfield
.ymmword
)
3377 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3382 case DATA_PREFIX_OPCODE
:
3385 case REPE_PREFIX_OPCODE
:
3388 case REPNE_PREFIX_OPCODE
:
3395 /* Use 2-byte VEX prefix if possible. */
3396 if (i
.vec_encoding
!= vex_encoding_vex3
3397 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3398 && i
.tm
.opcode_modifier
.vexw
!= VEXW1
3399 && (i
.rex
& (REX_W
| REX_X
| REX_B
)) == 0)
3401 /* 2-byte VEX prefix. */
3405 i
.vex
.bytes
[0] = 0xc5;
3407 /* Check the REX.R bit. */
3408 r
= (i
.rex
& REX_R
) ? 0 : 1;
3409 i
.vex
.bytes
[1] = (r
<< 7
3410 | register_specifier
<< 3
3411 | vector_length
<< 2
3416 /* 3-byte VEX prefix. */
3421 switch (i
.tm
.opcode_modifier
.vexopcode
)
3425 i
.vex
.bytes
[0] = 0xc4;
3429 i
.vex
.bytes
[0] = 0xc4;
3433 i
.vex
.bytes
[0] = 0xc4;
3437 i
.vex
.bytes
[0] = 0x8f;
3441 i
.vex
.bytes
[0] = 0x8f;
3445 i
.vex
.bytes
[0] = 0x8f;
3451 /* The high 3 bits of the second VEX byte are 1's compliment
3452 of RXB bits from REX. */
3453 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3455 /* Check the REX.W bit. */
3456 w
= (i
.rex
& REX_W
) ? 1 : 0;
3457 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
3460 i
.vex
.bytes
[2] = (w
<< 7
3461 | register_specifier
<< 3
3462 | vector_length
<< 2
3467 static INLINE bfd_boolean
3468 is_evex_encoding (const insn_template
*t
)
3470 return t
->opcode_modifier
.evex
3471 || t
->opcode_modifier
.broadcast
|| t
->opcode_modifier
.masking
3472 || t
->opcode_modifier
.staticrounding
|| t
->opcode_modifier
.sae
;
3475 /* Build the EVEX prefix. */
3478 build_evex_prefix (void)
3480 unsigned int register_specifier
;
3481 unsigned int implied_prefix
;
3483 rex_byte vrex_used
= 0;
3485 /* Check register specifier. */
3486 if (i
.vex
.register_specifier
)
3488 gas_assert ((i
.vrex
& REX_X
) == 0);
3490 register_specifier
= i
.vex
.register_specifier
->reg_num
;
3491 if ((i
.vex
.register_specifier
->reg_flags
& RegRex
))
3492 register_specifier
+= 8;
3493 /* The upper 16 registers are encoded in the fourth byte of the
3495 if (!(i
.vex
.register_specifier
->reg_flags
& RegVRex
))
3496 i
.vex
.bytes
[3] = 0x8;
3497 register_specifier
= ~register_specifier
& 0xf;
3501 register_specifier
= 0xf;
3503 /* Encode upper 16 vector index register in the fourth byte of
3505 if (!(i
.vrex
& REX_X
))
3506 i
.vex
.bytes
[3] = 0x8;
3511 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3516 case DATA_PREFIX_OPCODE
:
3519 case REPE_PREFIX_OPCODE
:
3522 case REPNE_PREFIX_OPCODE
:
3529 /* 4 byte EVEX prefix. */
3531 i
.vex
.bytes
[0] = 0x62;
3534 switch (i
.tm
.opcode_modifier
.vexopcode
)
3550 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3552 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3554 /* The fifth bit of the second EVEX byte is 1's compliment of the
3555 REX_R bit in VREX. */
3556 if (!(i
.vrex
& REX_R
))
3557 i
.vex
.bytes
[1] |= 0x10;
3561 if ((i
.reg_operands
+ i
.imm_operands
) == i
.operands
)
3563 /* When all operands are registers, the REX_X bit in REX is not
3564 used. We reuse it to encode the upper 16 registers, which is
3565 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3566 as 1's compliment. */
3567 if ((i
.vrex
& REX_B
))
3570 i
.vex
.bytes
[1] &= ~0x40;
3574 /* EVEX instructions shouldn't need the REX prefix. */
3575 i
.vrex
&= ~vrex_used
;
3576 gas_assert (i
.vrex
== 0);
3578 /* Check the REX.W bit. */
3579 w
= (i
.rex
& REX_W
) ? 1 : 0;
3580 if (i
.tm
.opcode_modifier
.vexw
)
3582 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
3585 /* If w is not set it means we are dealing with WIG instruction. */
3588 if (evexwig
== evexw1
)
3592 /* Encode the U bit. */
3593 implied_prefix
|= 0x4;
3595 /* The third byte of the EVEX prefix. */
3596 i
.vex
.bytes
[2] = (w
<< 7 | register_specifier
<< 3 | implied_prefix
);
3598 /* The fourth byte of the EVEX prefix. */
3599 /* The zeroing-masking bit. */
3600 if (i
.mask
&& i
.mask
->zeroing
)
3601 i
.vex
.bytes
[3] |= 0x80;
3603 /* Don't always set the broadcast bit if there is no RC. */
3606 /* Encode the vector length. */
3607 unsigned int vec_length
;
3609 if (!i
.tm
.opcode_modifier
.evex
3610 || i
.tm
.opcode_modifier
.evex
== EVEXDYN
)
3615 for (op
= 0; op
< i
.tm
.operands
; ++op
)
3616 if (i
.tm
.operand_types
[op
].bitfield
.xmmword
3617 + i
.tm
.operand_types
[op
].bitfield
.ymmword
3618 + i
.tm
.operand_types
[op
].bitfield
.zmmword
> 1)
3620 if (i
.types
[op
].bitfield
.zmmword
)
3621 i
.tm
.opcode_modifier
.evex
= EVEX512
;
3622 else if (i
.types
[op
].bitfield
.ymmword
)
3623 i
.tm
.opcode_modifier
.evex
= EVEX256
;
3624 else if (i
.types
[op
].bitfield
.xmmword
)
3625 i
.tm
.opcode_modifier
.evex
= EVEX128
;
3632 switch (i
.tm
.opcode_modifier
.evex
)
3634 case EVEXLIG
: /* LL' is ignored */
3635 vec_length
= evexlig
<< 5;
3638 vec_length
= 0 << 5;
3641 vec_length
= 1 << 5;
3644 vec_length
= 2 << 5;
3650 i
.vex
.bytes
[3] |= vec_length
;
3651 /* Encode the broadcast bit. */
3653 i
.vex
.bytes
[3] |= 0x10;
3657 if (i
.rounding
->type
!= saeonly
)
3658 i
.vex
.bytes
[3] |= 0x10 | (i
.rounding
->type
<< 5);
3660 i
.vex
.bytes
[3] |= 0x10 | (evexrcig
<< 5);
3663 if (i
.mask
&& i
.mask
->mask
)
3664 i
.vex
.bytes
[3] |= i
.mask
->mask
->reg_num
;
3668 process_immext (void)
3672 if ((i
.tm
.cpu_flags
.bitfield
.cpusse3
|| i
.tm
.cpu_flags
.bitfield
.cpusvme
)
3675 /* MONITOR/MWAIT as well as SVME instructions have fixed operands
3676 with an opcode suffix which is coded in the same place as an
3677 8-bit immediate field would be.
3678 Here we check those operands and remove them afterwards. */
3681 for (x
= 0; x
< i
.operands
; x
++)
3682 if (register_number (i
.op
[x
].regs
) != x
)
3683 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3684 register_prefix
, i
.op
[x
].regs
->reg_name
, x
+ 1,
3690 if (i
.tm
.cpu_flags
.bitfield
.cpumwaitx
&& i
.operands
> 0)
3692 /* MONITORX/MWAITX instructions have fixed operands with an opcode
3693 suffix which is coded in the same place as an 8-bit immediate
3695 Here we check those operands and remove them afterwards. */
3698 if (i
.operands
!= 3)
3701 for (x
= 0; x
< 2; x
++)
3702 if (register_number (i
.op
[x
].regs
) != x
)
3703 goto bad_register_operand
;
3705 /* Check for third operand for mwaitx/monitorx insn. */
3706 if (register_number (i
.op
[x
].regs
)
3707 != (x
+ (i
.tm
.extension_opcode
== 0xfb)))
3709 bad_register_operand
:
3710 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3711 register_prefix
, i
.op
[x
].regs
->reg_name
, x
+1,
3718 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
3719 which is coded in the same place as an 8-bit immediate field
3720 would be. Here we fake an 8-bit immediate operand from the
3721 opcode suffix stored in tm.extension_opcode.
3723 AVX instructions also use this encoding, for some of
3724 3 argument instructions. */
3726 gas_assert (i
.imm_operands
<= 1
3728 || ((i
.tm
.opcode_modifier
.vex
3729 || i
.tm
.opcode_modifier
.vexopcode
3730 || is_evex_encoding (&i
.tm
))
3731 && i
.operands
<= 4)));
3733 exp
= &im_expressions
[i
.imm_operands
++];
3734 i
.op
[i
.operands
].imms
= exp
;
3735 i
.types
[i
.operands
] = imm8
;
3737 exp
->X_op
= O_constant
;
3738 exp
->X_add_number
= i
.tm
.extension_opcode
;
3739 i
.tm
.extension_opcode
= None
;
3746 switch (i
.tm
.opcode_modifier
.hleprefixok
)
3751 as_bad (_("invalid instruction `%s' after `%s'"),
3752 i
.tm
.name
, i
.hle_prefix
);
3755 if (i
.prefix
[LOCK_PREFIX
])
3757 as_bad (_("missing `lock' with `%s'"), i
.hle_prefix
);
3761 case HLEPrefixRelease
:
3762 if (i
.prefix
[HLE_PREFIX
] != XRELEASE_PREFIX_OPCODE
)
3764 as_bad (_("instruction `%s' after `xacquire' not allowed"),
3768 if (i
.mem_operands
== 0
3769 || !operand_type_check (i
.types
[i
.operands
- 1], anymem
))
3771 as_bad (_("memory destination needed for instruction `%s'"
3772 " after `xrelease'"), i
.tm
.name
);
3779 /* Try the shortest encoding by shortening operand size. */
3782 optimize_encoding (void)
3786 if (optimize_for_space
3787 && i
.reg_operands
== 1
3788 && i
.imm_operands
== 1
3789 && !i
.types
[1].bitfield
.byte
3790 && i
.op
[0].imms
->X_op
== O_constant
3791 && fits_in_imm7 (i
.op
[0].imms
->X_add_number
)
3792 && ((i
.tm
.base_opcode
== 0xa8
3793 && i
.tm
.extension_opcode
== None
)
3794 || (i
.tm
.base_opcode
== 0xf6
3795 && i
.tm
.extension_opcode
== 0x0)))
3798 test $imm7, %r64/%r32/%r16 -> test $imm7, %r8
3800 unsigned int base_regnum
= i
.op
[1].regs
->reg_num
;
3801 if (flag_code
== CODE_64BIT
|| base_regnum
< 4)
3803 i
.types
[1].bitfield
.byte
= 1;
3804 /* Ignore the suffix. */
3806 if (base_regnum
>= 4
3807 && !(i
.op
[1].regs
->reg_flags
& RegRex
))
3809 /* Handle SP, BP, SI and DI registers. */
3810 if (i
.types
[1].bitfield
.word
)
3812 else if (i
.types
[1].bitfield
.dword
)
3820 else if (flag_code
== CODE_64BIT
3821 && ((i
.types
[1].bitfield
.qword
3822 && i
.reg_operands
== 1
3823 && i
.imm_operands
== 1
3824 && i
.op
[0].imms
->X_op
== O_constant
3825 && ((i
.tm
.base_opcode
== 0xb0
3826 && i
.tm
.extension_opcode
== None
3827 && fits_in_unsigned_long (i
.op
[0].imms
->X_add_number
))
3828 || (fits_in_imm31 (i
.op
[0].imms
->X_add_number
)
3829 && (((i
.tm
.base_opcode
== 0x24
3830 || i
.tm
.base_opcode
== 0xa8)
3831 && i
.tm
.extension_opcode
== None
)
3832 || (i
.tm
.base_opcode
== 0x80
3833 && i
.tm
.extension_opcode
== 0x4)
3834 || ((i
.tm
.base_opcode
== 0xf6
3835 || i
.tm
.base_opcode
== 0xc6)
3836 && i
.tm
.extension_opcode
== 0x0)))))
3837 || (i
.types
[0].bitfield
.qword
3838 && ((i
.reg_operands
== 2
3839 && i
.op
[0].regs
== i
.op
[1].regs
3840 && ((i
.tm
.base_opcode
== 0x30
3841 || i
.tm
.base_opcode
== 0x28)
3842 && i
.tm
.extension_opcode
== None
))
3843 || (i
.reg_operands
== 1
3845 && i
.tm
.base_opcode
== 0x30
3846 && i
.tm
.extension_opcode
== None
)))))
3849 andq $imm31, %r64 -> andl $imm31, %r32
3850 testq $imm31, %r64 -> testl $imm31, %r32
3851 xorq %r64, %r64 -> xorl %r32, %r32
3852 subq %r64, %r64 -> subl %r32, %r32
3853 movq $imm31, %r64 -> movl $imm31, %r32
3854 movq $imm32, %r64 -> movl $imm32, %r32
3856 i
.tm
.opcode_modifier
.norex64
= 1;
3857 if (i
.tm
.base_opcode
== 0xb0 || i
.tm
.base_opcode
== 0xc6)
3860 movq $imm31, %r64 -> movl $imm31, %r32
3861 movq $imm32, %r64 -> movl $imm32, %r32
3863 i
.tm
.operand_types
[0].bitfield
.imm32
= 1;
3864 i
.tm
.operand_types
[0].bitfield
.imm32s
= 0;
3865 i
.tm
.operand_types
[0].bitfield
.imm64
= 0;
3866 i
.types
[0].bitfield
.imm32
= 1;
3867 i
.types
[0].bitfield
.imm32s
= 0;
3868 i
.types
[0].bitfield
.imm64
= 0;
3869 i
.types
[1].bitfield
.dword
= 1;
3870 i
.types
[1].bitfield
.qword
= 0;
3871 if (i
.tm
.base_opcode
== 0xc6)
3874 movq $imm31, %r64 -> movl $imm31, %r32
3876 i
.tm
.base_opcode
= 0xb0;
3877 i
.tm
.extension_opcode
= None
;
3878 i
.tm
.opcode_modifier
.shortform
= 1;
3879 i
.tm
.opcode_modifier
.modrm
= 0;
3883 else if (optimize
> 1
3884 && i
.reg_operands
== 3
3885 && i
.op
[0].regs
== i
.op
[1].regs
3886 && !i
.types
[2].bitfield
.xmmword
3887 && (i
.tm
.opcode_modifier
.vex
3888 || ((!i
.mask
|| i
.mask
->zeroing
)
3890 && is_evex_encoding (&i
.tm
)
3891 && (i
.vec_encoding
!= vex_encoding_evex
3892 || i
.tm
.cpu_flags
.bitfield
.cpuavx512vl
3893 || cpu_arch_isa_flags
.bitfield
.cpuavx512vl
)))
3894 && ((i
.tm
.base_opcode
== 0x55
3895 || i
.tm
.base_opcode
== 0x6655
3896 || i
.tm
.base_opcode
== 0x66df
3897 || i
.tm
.base_opcode
== 0x57
3898 || i
.tm
.base_opcode
== 0x6657
3899 || i
.tm
.base_opcode
== 0x66ef
3900 || i
.tm
.base_opcode
== 0x66f8
3901 || i
.tm
.base_opcode
== 0x66f9
3902 || i
.tm
.base_opcode
== 0x66fa
3903 || i
.tm
.base_opcode
== 0x66fb)
3904 && i
.tm
.extension_opcode
== None
))
3907 VOP, one of vandnps, vandnpd, vxorps, vxorpd, vpsubb, vpsubd,
3909 EVEX VOP %zmmM, %zmmM, %zmmN
3910 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
3911 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3912 EVEX VOP %ymmM, %ymmM, %ymmN
3913 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
3914 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3915 VEX VOP %ymmM, %ymmM, %ymmN
3916 -> VEX VOP %xmmM, %xmmM, %xmmN
3917 VOP, one of vpandn and vpxor:
3918 VEX VOP %ymmM, %ymmM, %ymmN
3919 -> VEX VOP %xmmM, %xmmM, %xmmN
3920 VOP, one of vpandnd and vpandnq:
3921 EVEX VOP %zmmM, %zmmM, %zmmN
3922 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
3923 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3924 EVEX VOP %ymmM, %ymmM, %ymmN
3925 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
3926 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3927 VOP, one of vpxord and vpxorq:
3928 EVEX VOP %zmmM, %zmmM, %zmmN
3929 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
3930 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3931 EVEX VOP %ymmM, %ymmM, %ymmN
3932 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
3933 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3935 if (is_evex_encoding (&i
.tm
))
3937 if (i
.vec_encoding
== vex_encoding_evex
)
3938 i
.tm
.opcode_modifier
.evex
= EVEX128
;
3941 i
.tm
.opcode_modifier
.vex
= VEX128
;
3942 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
3943 i
.tm
.opcode_modifier
.evex
= 0;
3947 i
.tm
.opcode_modifier
.vex
= VEX128
;
3949 if (i
.tm
.opcode_modifier
.vex
)
3950 for (j
= 0; j
< 3; j
++)
3952 i
.types
[j
].bitfield
.xmmword
= 1;
3953 i
.types
[j
].bitfield
.ymmword
= 0;
3958 /* This is the guts of the machine-dependent assembler. LINE points to a
3959 machine dependent instruction. This function is supposed to emit
3960 the frags/bytes it assembles to. */
3963 md_assemble (char *line
)
3966 char mnemonic
[MAX_MNEM_SIZE
], mnem_suffix
;
3967 const insn_template
*t
;
3969 /* Initialize globals. */
3970 memset (&i
, '\0', sizeof (i
));
3971 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3972 i
.reloc
[j
] = NO_RELOC
;
3973 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
3974 memset (im_expressions
, '\0', sizeof (im_expressions
));
3975 save_stack_p
= save_stack
;
3977 /* First parse an instruction mnemonic & call i386_operand for the operands.
3978 We assume that the scrubber has arranged it so that line[0] is the valid
3979 start of a (possibly prefixed) mnemonic. */
3981 line
= parse_insn (line
, mnemonic
);
3984 mnem_suffix
= i
.suffix
;
3986 line
= parse_operands (line
, mnemonic
);
3988 xfree (i
.memop1_string
);
3989 i
.memop1_string
= NULL
;
3993 /* Now we've parsed the mnemonic into a set of templates, and have the
3994 operands at hand. */
3996 /* All intel opcodes have reversed operands except for "bound" and
3997 "enter". We also don't reverse intersegment "jmp" and "call"
3998 instructions with 2 immediate operands so that the immediate segment
3999 precedes the offset, as it does when in AT&T mode. */
4002 && (strcmp (mnemonic
, "bound") != 0)
4003 && (strcmp (mnemonic
, "invlpga") != 0)
4004 && !(operand_type_check (i
.types
[0], imm
)
4005 && operand_type_check (i
.types
[1], imm
)))
4008 /* The order of the immediates should be reversed
4009 for 2 immediates extrq and insertq instructions */
4010 if (i
.imm_operands
== 2
4011 && (strcmp (mnemonic
, "extrq") == 0
4012 || strcmp (mnemonic
, "insertq") == 0))
4013 swap_2_operands (0, 1);
4018 /* Don't optimize displacement for movabs since it only takes 64bit
4021 && i
.disp_encoding
!= disp_encoding_32bit
4022 && (flag_code
!= CODE_64BIT
4023 || strcmp (mnemonic
, "movabs") != 0))
4026 /* Next, we find a template that matches the given insn,
4027 making sure the overlap of the given operands types is consistent
4028 with the template operand types. */
4030 if (!(t
= match_template (mnem_suffix
)))
4033 if (sse_check
!= check_none
4034 && !i
.tm
.opcode_modifier
.noavx
4035 && !i
.tm
.cpu_flags
.bitfield
.cpuavx
4036 && (i
.tm
.cpu_flags
.bitfield
.cpusse
4037 || i
.tm
.cpu_flags
.bitfield
.cpusse2
4038 || i
.tm
.cpu_flags
.bitfield
.cpusse3
4039 || i
.tm
.cpu_flags
.bitfield
.cpussse3
4040 || i
.tm
.cpu_flags
.bitfield
.cpusse4_1
4041 || i
.tm
.cpu_flags
.bitfield
.cpusse4_2
4042 || i
.tm
.cpu_flags
.bitfield
.cpupclmul
4043 || i
.tm
.cpu_flags
.bitfield
.cpuaes
4044 || i
.tm
.cpu_flags
.bitfield
.cpugfni
))
4046 (sse_check
== check_warning
4048 : as_bad
) (_("SSE instruction `%s' is used"), i
.tm
.name
);
4051 /* Zap movzx and movsx suffix. The suffix has been set from
4052 "word ptr" or "byte ptr" on the source operand in Intel syntax
4053 or extracted from mnemonic in AT&T syntax. But we'll use
4054 the destination register to choose the suffix for encoding. */
4055 if ((i
.tm
.base_opcode
& ~9) == 0x0fb6)
4057 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
4058 there is no suffix, the default will be byte extension. */
4059 if (i
.reg_operands
!= 2
4062 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
4067 if (i
.tm
.opcode_modifier
.fwait
)
4068 if (!add_prefix (FWAIT_OPCODE
))
4071 /* Check if REP prefix is OK. */
4072 if (i
.rep_prefix
&& !i
.tm
.opcode_modifier
.repprefixok
)
4074 as_bad (_("invalid instruction `%s' after `%s'"),
4075 i
.tm
.name
, i
.rep_prefix
);
4079 /* Check for lock without a lockable instruction. Destination operand
4080 must be memory unless it is xchg (0x86). */
4081 if (i
.prefix
[LOCK_PREFIX
]
4082 && (!i
.tm
.opcode_modifier
.islockable
4083 || i
.mem_operands
== 0
4084 || (i
.tm
.base_opcode
!= 0x86
4085 && !operand_type_check (i
.types
[i
.operands
- 1], anymem
))))
4087 as_bad (_("expecting lockable instruction after `lock'"));
4091 /* Check if HLE prefix is OK. */
4092 if (i
.hle_prefix
&& !check_hle ())
4095 /* Check BND prefix. */
4096 if (i
.bnd_prefix
&& !i
.tm
.opcode_modifier
.bndprefixok
)
4097 as_bad (_("expecting valid branch instruction after `bnd'"));
4099 /* Check NOTRACK prefix. */
4100 if (i
.notrack_prefix
&& !i
.tm
.opcode_modifier
.notrackprefixok
)
4101 as_bad (_("expecting indirect branch instruction after `notrack'"));
4103 if (i
.tm
.cpu_flags
.bitfield
.cpumpx
)
4105 if (flag_code
== CODE_64BIT
&& i
.prefix
[ADDR_PREFIX
])
4106 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
4107 else if (flag_code
!= CODE_16BIT
4108 ? i
.prefix
[ADDR_PREFIX
]
4109 : i
.mem_operands
&& !i
.prefix
[ADDR_PREFIX
])
4110 as_bad (_("16-bit address isn't allowed in MPX instructions"));
4113 /* Insert BND prefix. */
4115 && i
.tm
.opcode_modifier
.bndprefixok
4116 && !i
.prefix
[BND_PREFIX
])
4117 add_prefix (BND_PREFIX_OPCODE
);
4119 /* Check string instruction segment overrides. */
4120 if (i
.tm
.opcode_modifier
.isstring
&& i
.mem_operands
!= 0)
4122 if (!check_string ())
4124 i
.disp_operands
= 0;
4127 if (optimize
&& !i
.no_optimize
&& i
.tm
.opcode_modifier
.optimize
)
4128 optimize_encoding ();
4130 if (!process_suffix ())
4133 /* Update operand types. */
4134 for (j
= 0; j
< i
.operands
; j
++)
4135 i
.types
[j
] = operand_type_and (i
.types
[j
], i
.tm
.operand_types
[j
]);
4137 /* Make still unresolved immediate matches conform to size of immediate
4138 given in i.suffix. */
4139 if (!finalize_imm ())
4142 if (i
.types
[0].bitfield
.imm1
)
4143 i
.imm_operands
= 0; /* kludge for shift insns. */
4145 /* We only need to check those implicit registers for instructions
4146 with 3 operands or less. */
4147 if (i
.operands
<= 3)
4148 for (j
= 0; j
< i
.operands
; j
++)
4149 if (i
.types
[j
].bitfield
.inoutportreg
4150 || i
.types
[j
].bitfield
.shiftcount
4151 || (i
.types
[j
].bitfield
.acc
&& !i
.types
[j
].bitfield
.xmmword
))
4154 /* ImmExt should be processed after SSE2AVX. */
4155 if (!i
.tm
.opcode_modifier
.sse2avx
4156 && i
.tm
.opcode_modifier
.immext
)
4159 /* For insns with operands there are more diddles to do to the opcode. */
4162 if (!process_operands ())
4165 else if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
4167 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
4168 as_warn (_("translating to `%sp'"), i
.tm
.name
);
4171 if (i
.tm
.opcode_modifier
.vex
|| i
.tm
.opcode_modifier
.vexopcode
4172 || is_evex_encoding (&i
.tm
))
4174 if (flag_code
== CODE_16BIT
)
4176 as_bad (_("instruction `%s' isn't supported in 16-bit mode."),
4181 if (i
.tm
.opcode_modifier
.vex
)
4182 build_vex_prefix (t
);
4184 build_evex_prefix ();
4187 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
4188 instructions may define INT_OPCODE as well, so avoid this corner
4189 case for those instructions that use MODRM. */
4190 if (i
.tm
.base_opcode
== INT_OPCODE
4191 && !i
.tm
.opcode_modifier
.modrm
4192 && i
.op
[0].imms
->X_add_number
== 3)
4194 i
.tm
.base_opcode
= INT3_OPCODE
;
4198 if ((i
.tm
.opcode_modifier
.jump
4199 || i
.tm
.opcode_modifier
.jumpbyte
4200 || i
.tm
.opcode_modifier
.jumpdword
)
4201 && i
.op
[0].disps
->X_op
== O_constant
)
4203 /* Convert "jmp constant" (and "call constant") to a jump (call) to
4204 the absolute address given by the constant. Since ix86 jumps and
4205 calls are pc relative, we need to generate a reloc. */
4206 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
4207 i
.op
[0].disps
->X_op
= O_symbol
;
4210 if (i
.tm
.opcode_modifier
.rex64
)
4213 /* For 8 bit registers we need an empty rex prefix. Also if the
4214 instruction already has a prefix, we need to convert old
4215 registers to new ones. */
4217 if ((i
.types
[0].bitfield
.reg
&& i
.types
[0].bitfield
.byte
4218 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
4219 || (i
.types
[1].bitfield
.reg
&& i
.types
[1].bitfield
.byte
4220 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
4221 || (((i
.types
[0].bitfield
.reg
&& i
.types
[0].bitfield
.byte
)
4222 || (i
.types
[1].bitfield
.reg
&& i
.types
[1].bitfield
.byte
))
4227 i
.rex
|= REX_OPCODE
;
4228 for (x
= 0; x
< 2; x
++)
4230 /* Look for 8 bit operand that uses old registers. */
4231 if (i
.types
[x
].bitfield
.reg
&& i
.types
[x
].bitfield
.byte
4232 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
4234 /* In case it is "hi" register, give up. */
4235 if (i
.op
[x
].regs
->reg_num
> 3)
4236 as_bad (_("can't encode register '%s%s' in an "
4237 "instruction requiring REX prefix."),
4238 register_prefix
, i
.op
[x
].regs
->reg_name
);
4240 /* Otherwise it is equivalent to the extended register.
4241 Since the encoding doesn't change this is merely
4242 cosmetic cleanup for debug output. */
4244 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
4249 if (i
.rex
== 0 && i
.rex_encoding
)
4251 /* Check if we can add a REX_OPCODE byte. Look for 8 bit operand
4252 that uses legacy register. If it is "hi" register, don't add
4253 the REX_OPCODE byte. */
4255 for (x
= 0; x
< 2; x
++)
4256 if (i
.types
[x
].bitfield
.reg
4257 && i
.types
[x
].bitfield
.byte
4258 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0
4259 && i
.op
[x
].regs
->reg_num
> 3)
4261 i
.rex_encoding
= FALSE
;
4270 add_prefix (REX_OPCODE
| i
.rex
);
4272 /* We are ready to output the insn. */
4277 parse_insn (char *line
, char *mnemonic
)
4280 char *token_start
= l
;
4283 const insn_template
*t
;
4289 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
4294 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
4296 as_bad (_("no such instruction: `%s'"), token_start
);
4301 if (!is_space_char (*l
)
4302 && *l
!= END_OF_INSN
4304 || (*l
!= PREFIX_SEPARATOR
4307 as_bad (_("invalid character %s in mnemonic"),
4308 output_invalid (*l
));
4311 if (token_start
== l
)
4313 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
4314 as_bad (_("expecting prefix; got nothing"));
4316 as_bad (_("expecting mnemonic; got nothing"));
4320 /* Look up instruction (or prefix) via hash table. */
4321 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
4323 if (*l
!= END_OF_INSN
4324 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
4325 && current_templates
4326 && current_templates
->start
->opcode_modifier
.isprefix
)
4328 if (!cpu_flags_check_cpu64 (current_templates
->start
->cpu_flags
))
4330 as_bad ((flag_code
!= CODE_64BIT
4331 ? _("`%s' is only supported in 64-bit mode")
4332 : _("`%s' is not supported in 64-bit mode")),
4333 current_templates
->start
->name
);
4336 /* If we are in 16-bit mode, do not allow addr16 or data16.
4337 Similarly, in 32-bit mode, do not allow addr32 or data32. */
4338 if ((current_templates
->start
->opcode_modifier
.size16
4339 || current_templates
->start
->opcode_modifier
.size32
)
4340 && flag_code
!= CODE_64BIT
4341 && (current_templates
->start
->opcode_modifier
.size32
4342 ^ (flag_code
== CODE_16BIT
)))
4344 as_bad (_("redundant %s prefix"),
4345 current_templates
->start
->name
);
4348 if (current_templates
->start
->opcode_length
== 0)
4350 /* Handle pseudo prefixes. */
4351 switch (current_templates
->start
->base_opcode
)
4355 i
.disp_encoding
= disp_encoding_8bit
;
4359 i
.disp_encoding
= disp_encoding_32bit
;
4363 i
.dir_encoding
= dir_encoding_load
;
4367 i
.dir_encoding
= dir_encoding_store
;
4371 i
.vec_encoding
= vex_encoding_vex2
;
4375 i
.vec_encoding
= vex_encoding_vex3
;
4379 i
.vec_encoding
= vex_encoding_evex
;
4383 i
.rex_encoding
= TRUE
;
4387 i
.no_optimize
= TRUE
;
4395 /* Add prefix, checking for repeated prefixes. */
4396 switch (add_prefix (current_templates
->start
->base_opcode
))
4401 if (current_templates
->start
->cpu_flags
.bitfield
.cpuibt
)
4402 i
.notrack_prefix
= current_templates
->start
->name
;
4405 if (current_templates
->start
->cpu_flags
.bitfield
.cpuhle
)
4406 i
.hle_prefix
= current_templates
->start
->name
;
4407 else if (current_templates
->start
->cpu_flags
.bitfield
.cpumpx
)
4408 i
.bnd_prefix
= current_templates
->start
->name
;
4410 i
.rep_prefix
= current_templates
->start
->name
;
4416 /* Skip past PREFIX_SEPARATOR and reset token_start. */
4423 if (!current_templates
)
4425 /* Check if we should swap operand or force 32bit displacement in
4427 if (mnem_p
- 2 == dot_p
&& dot_p
[1] == 's')
4428 i
.dir_encoding
= dir_encoding_store
;
4429 else if (mnem_p
- 3 == dot_p
4432 i
.disp_encoding
= disp_encoding_8bit
;
4433 else if (mnem_p
- 4 == dot_p
4437 i
.disp_encoding
= disp_encoding_32bit
;
4442 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
4445 if (!current_templates
)
4448 /* See if we can get a match by trimming off a suffix. */
4451 case WORD_MNEM_SUFFIX
:
4452 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
4453 i
.suffix
= SHORT_MNEM_SUFFIX
;
4456 case BYTE_MNEM_SUFFIX
:
4457 case QWORD_MNEM_SUFFIX
:
4458 i
.suffix
= mnem_p
[-1];
4460 current_templates
= (const templates
*) hash_find (op_hash
,
4463 case SHORT_MNEM_SUFFIX
:
4464 case LONG_MNEM_SUFFIX
:
4467 i
.suffix
= mnem_p
[-1];
4469 current_templates
= (const templates
*) hash_find (op_hash
,
4478 if (intel_float_operand (mnemonic
) == 1)
4479 i
.suffix
= SHORT_MNEM_SUFFIX
;
4481 i
.suffix
= LONG_MNEM_SUFFIX
;
4483 current_templates
= (const templates
*) hash_find (op_hash
,
4488 if (!current_templates
)
4490 as_bad (_("no such instruction: `%s'"), token_start
);
4495 if (current_templates
->start
->opcode_modifier
.jump
4496 || current_templates
->start
->opcode_modifier
.jumpbyte
)
4498 /* Check for a branch hint. We allow ",pt" and ",pn" for
4499 predict taken and predict not taken respectively.
4500 I'm not sure that branch hints actually do anything on loop
4501 and jcxz insns (JumpByte) for current Pentium4 chips. They
4502 may work in the future and it doesn't hurt to accept them
4504 if (l
[0] == ',' && l
[1] == 'p')
4508 if (!add_prefix (DS_PREFIX_OPCODE
))
4512 else if (l
[2] == 'n')
4514 if (!add_prefix (CS_PREFIX_OPCODE
))
4520 /* Any other comma loses. */
4523 as_bad (_("invalid character %s in mnemonic"),
4524 output_invalid (*l
));
4528 /* Check if instruction is supported on specified architecture. */
4530 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
4532 supported
|= cpu_flags_match (t
);
4533 if (supported
== CPU_FLAGS_PERFECT_MATCH
)
4535 if (!cpu_arch_flags
.bitfield
.cpui386
&& (flag_code
!= CODE_16BIT
))
4536 as_warn (_("use .code16 to ensure correct addressing mode"));
4542 if (!(supported
& CPU_FLAGS_64BIT_MATCH
))
4543 as_bad (flag_code
== CODE_64BIT
4544 ? _("`%s' is not supported in 64-bit mode")
4545 : _("`%s' is only supported in 64-bit mode"),
4546 current_templates
->start
->name
);
4548 as_bad (_("`%s' is not supported on `%s%s'"),
4549 current_templates
->start
->name
,
4550 cpu_arch_name
? cpu_arch_name
: default_arch
,
4551 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
4557 parse_operands (char *l
, const char *mnemonic
)
4561 /* 1 if operand is pending after ','. */
4562 unsigned int expecting_operand
= 0;
4564 /* Non-zero if operand parens not balanced. */
4565 unsigned int paren_not_balanced
;
4567 while (*l
!= END_OF_INSN
)
4569 /* Skip optional white space before operand. */
4570 if (is_space_char (*l
))
4572 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
&& *l
!= '"')
4574 as_bad (_("invalid character %s before operand %d"),
4575 output_invalid (*l
),
4579 token_start
= l
; /* After white space. */
4580 paren_not_balanced
= 0;
4581 while (paren_not_balanced
|| *l
!= ',')
4583 if (*l
== END_OF_INSN
)
4585 if (paren_not_balanced
)
4588 as_bad (_("unbalanced parenthesis in operand %d."),
4591 as_bad (_("unbalanced brackets in operand %d."),
4596 break; /* we are done */
4598 else if (!is_operand_char (*l
) && !is_space_char (*l
) && *l
!= '"')
4600 as_bad (_("invalid character %s in operand %d"),
4601 output_invalid (*l
),
4608 ++paren_not_balanced
;
4610 --paren_not_balanced
;
4615 ++paren_not_balanced
;
4617 --paren_not_balanced
;
4621 if (l
!= token_start
)
4622 { /* Yes, we've read in another operand. */
4623 unsigned int operand_ok
;
4624 this_operand
= i
.operands
++;
4625 if (i
.operands
> MAX_OPERANDS
)
4627 as_bad (_("spurious operands; (%d operands/instruction max)"),
4631 i
.types
[this_operand
].bitfield
.unspecified
= 1;
4632 /* Now parse operand adding info to 'i' as we go along. */
4633 END_STRING_AND_SAVE (l
);
4637 i386_intel_operand (token_start
,
4638 intel_float_operand (mnemonic
));
4640 operand_ok
= i386_att_operand (token_start
);
4642 RESTORE_END_STRING (l
);
4648 if (expecting_operand
)
4650 expecting_operand_after_comma
:
4651 as_bad (_("expecting operand after ','; got nothing"));
4656 as_bad (_("expecting operand before ','; got nothing"));
4661 /* Now *l must be either ',' or END_OF_INSN. */
4664 if (*++l
== END_OF_INSN
)
4666 /* Just skip it, if it's \n complain. */
4667 goto expecting_operand_after_comma
;
4669 expecting_operand
= 1;
4676 swap_2_operands (int xchg1
, int xchg2
)
4678 union i386_op temp_op
;
4679 i386_operand_type temp_type
;
4680 enum bfd_reloc_code_real temp_reloc
;
4682 temp_type
= i
.types
[xchg2
];
4683 i
.types
[xchg2
] = i
.types
[xchg1
];
4684 i
.types
[xchg1
] = temp_type
;
4685 temp_op
= i
.op
[xchg2
];
4686 i
.op
[xchg2
] = i
.op
[xchg1
];
4687 i
.op
[xchg1
] = temp_op
;
4688 temp_reloc
= i
.reloc
[xchg2
];
4689 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
4690 i
.reloc
[xchg1
] = temp_reloc
;
4694 if (i
.mask
->operand
== xchg1
)
4695 i
.mask
->operand
= xchg2
;
4696 else if (i
.mask
->operand
== xchg2
)
4697 i
.mask
->operand
= xchg1
;
4701 if (i
.broadcast
->operand
== xchg1
)
4702 i
.broadcast
->operand
= xchg2
;
4703 else if (i
.broadcast
->operand
== xchg2
)
4704 i
.broadcast
->operand
= xchg1
;
4708 if (i
.rounding
->operand
== xchg1
)
4709 i
.rounding
->operand
= xchg2
;
4710 else if (i
.rounding
->operand
== xchg2
)
4711 i
.rounding
->operand
= xchg1
;
4716 swap_operands (void)
4722 swap_2_operands (1, i
.operands
- 2);
4726 swap_2_operands (0, i
.operands
- 1);
4732 if (i
.mem_operands
== 2)
4734 const seg_entry
*temp_seg
;
4735 temp_seg
= i
.seg
[0];
4736 i
.seg
[0] = i
.seg
[1];
4737 i
.seg
[1] = temp_seg
;
4741 /* Try to ensure constant immediates are represented in the smallest
4746 char guess_suffix
= 0;
4750 guess_suffix
= i
.suffix
;
4751 else if (i
.reg_operands
)
4753 /* Figure out a suffix from the last register operand specified.
4754 We can't do this properly yet, ie. excluding InOutPortReg,
4755 but the following works for instructions with immediates.
4756 In any case, we can't set i.suffix yet. */
4757 for (op
= i
.operands
; --op
>= 0;)
4758 if (i
.types
[op
].bitfield
.reg
&& i
.types
[op
].bitfield
.byte
)
4760 guess_suffix
= BYTE_MNEM_SUFFIX
;
4763 else if (i
.types
[op
].bitfield
.reg
&& i
.types
[op
].bitfield
.word
)
4765 guess_suffix
= WORD_MNEM_SUFFIX
;
4768 else if (i
.types
[op
].bitfield
.reg
&& i
.types
[op
].bitfield
.dword
)
4770 guess_suffix
= LONG_MNEM_SUFFIX
;
4773 else if (i
.types
[op
].bitfield
.reg
&& i
.types
[op
].bitfield
.qword
)
4775 guess_suffix
= QWORD_MNEM_SUFFIX
;
4779 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
4780 guess_suffix
= WORD_MNEM_SUFFIX
;
4782 for (op
= i
.operands
; --op
>= 0;)
4783 if (operand_type_check (i
.types
[op
], imm
))
4785 switch (i
.op
[op
].imms
->X_op
)
4788 /* If a suffix is given, this operand may be shortened. */
4789 switch (guess_suffix
)
4791 case LONG_MNEM_SUFFIX
:
4792 i
.types
[op
].bitfield
.imm32
= 1;
4793 i
.types
[op
].bitfield
.imm64
= 1;
4795 case WORD_MNEM_SUFFIX
:
4796 i
.types
[op
].bitfield
.imm16
= 1;
4797 i
.types
[op
].bitfield
.imm32
= 1;
4798 i
.types
[op
].bitfield
.imm32s
= 1;
4799 i
.types
[op
].bitfield
.imm64
= 1;
4801 case BYTE_MNEM_SUFFIX
:
4802 i
.types
[op
].bitfield
.imm8
= 1;
4803 i
.types
[op
].bitfield
.imm8s
= 1;
4804 i
.types
[op
].bitfield
.imm16
= 1;
4805 i
.types
[op
].bitfield
.imm32
= 1;
4806 i
.types
[op
].bitfield
.imm32s
= 1;
4807 i
.types
[op
].bitfield
.imm64
= 1;
4811 /* If this operand is at most 16 bits, convert it
4812 to a signed 16 bit number before trying to see
4813 whether it will fit in an even smaller size.
4814 This allows a 16-bit operand such as $0xffe0 to
4815 be recognised as within Imm8S range. */
4816 if ((i
.types
[op
].bitfield
.imm16
)
4817 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
4819 i
.op
[op
].imms
->X_add_number
=
4820 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
4823 /* Store 32-bit immediate in 64-bit for 64-bit BFD. */
4824 if ((i
.types
[op
].bitfield
.imm32
)
4825 && ((i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1))
4828 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
4829 ^ ((offsetT
) 1 << 31))
4830 - ((offsetT
) 1 << 31));
4834 = operand_type_or (i
.types
[op
],
4835 smallest_imm_type (i
.op
[op
].imms
->X_add_number
));
4837 /* We must avoid matching of Imm32 templates when 64bit
4838 only immediate is available. */
4839 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
4840 i
.types
[op
].bitfield
.imm32
= 0;
4847 /* Symbols and expressions. */
4849 /* Convert symbolic operand to proper sizes for matching, but don't
4850 prevent matching a set of insns that only supports sizes other
4851 than those matching the insn suffix. */
4853 i386_operand_type mask
, allowed
;
4854 const insn_template
*t
;
4856 operand_type_set (&mask
, 0);
4857 operand_type_set (&allowed
, 0);
4859 for (t
= current_templates
->start
;
4860 t
< current_templates
->end
;
4862 allowed
= operand_type_or (allowed
,
4863 t
->operand_types
[op
]);
4864 switch (guess_suffix
)
4866 case QWORD_MNEM_SUFFIX
:
4867 mask
.bitfield
.imm64
= 1;
4868 mask
.bitfield
.imm32s
= 1;
4870 case LONG_MNEM_SUFFIX
:
4871 mask
.bitfield
.imm32
= 1;
4873 case WORD_MNEM_SUFFIX
:
4874 mask
.bitfield
.imm16
= 1;
4876 case BYTE_MNEM_SUFFIX
:
4877 mask
.bitfield
.imm8
= 1;
4882 allowed
= operand_type_and (mask
, allowed
);
4883 if (!operand_type_all_zero (&allowed
))
4884 i
.types
[op
] = operand_type_and (i
.types
[op
], mask
);
4891 /* Try to use the smallest displacement type too. */
4893 optimize_disp (void)
4897 for (op
= i
.operands
; --op
>= 0;)
4898 if (operand_type_check (i
.types
[op
], disp
))
4900 if (i
.op
[op
].disps
->X_op
== O_constant
)
4902 offsetT op_disp
= i
.op
[op
].disps
->X_add_number
;
4904 if (i
.types
[op
].bitfield
.disp16
4905 && (op_disp
& ~(offsetT
) 0xffff) == 0)
4907 /* If this operand is at most 16 bits, convert
4908 to a signed 16 bit number and don't use 64bit
4910 op_disp
= (((op_disp
& 0xffff) ^ 0x8000) - 0x8000);
4911 i
.types
[op
].bitfield
.disp64
= 0;
4914 /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */
4915 if (i
.types
[op
].bitfield
.disp32
4916 && (op_disp
& ~(((offsetT
) 2 << 31) - 1)) == 0)
4918 /* If this operand is at most 32 bits, convert
4919 to a signed 32 bit number and don't use 64bit
4921 op_disp
&= (((offsetT
) 2 << 31) - 1);
4922 op_disp
= (op_disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
4923 i
.types
[op
].bitfield
.disp64
= 0;
4926 if (!op_disp
&& i
.types
[op
].bitfield
.baseindex
)
4928 i
.types
[op
].bitfield
.disp8
= 0;
4929 i
.types
[op
].bitfield
.disp16
= 0;
4930 i
.types
[op
].bitfield
.disp32
= 0;
4931 i
.types
[op
].bitfield
.disp32s
= 0;
4932 i
.types
[op
].bitfield
.disp64
= 0;
4936 else if (flag_code
== CODE_64BIT
)
4938 if (fits_in_signed_long (op_disp
))
4940 i
.types
[op
].bitfield
.disp64
= 0;
4941 i
.types
[op
].bitfield
.disp32s
= 1;
4943 if (i
.prefix
[ADDR_PREFIX
]
4944 && fits_in_unsigned_long (op_disp
))
4945 i
.types
[op
].bitfield
.disp32
= 1;
4947 if ((i
.types
[op
].bitfield
.disp32
4948 || i
.types
[op
].bitfield
.disp32s
4949 || i
.types
[op
].bitfield
.disp16
)
4950 && fits_in_disp8 (op_disp
))
4951 i
.types
[op
].bitfield
.disp8
= 1;
4953 else if (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
4954 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
)
4956 fix_new_exp (frag_now
, frag_more (0) - frag_now
->fr_literal
, 0,
4957 i
.op
[op
].disps
, 0, i
.reloc
[op
]);
4958 i
.types
[op
].bitfield
.disp8
= 0;
4959 i
.types
[op
].bitfield
.disp16
= 0;
4960 i
.types
[op
].bitfield
.disp32
= 0;
4961 i
.types
[op
].bitfield
.disp32s
= 0;
4962 i
.types
[op
].bitfield
.disp64
= 0;
4965 /* We only support 64bit displacement on constants. */
4966 i
.types
[op
].bitfield
.disp64
= 0;
4970 /* Check if operands are valid for the instruction. */
4973 check_VecOperands (const insn_template
*t
)
4977 static const i386_cpu_flags avx512
= CPU_ANY_AVX512F_FLAGS
;
4979 /* Templates allowing for ZMMword as well as YMMword and/or XMMword for
4980 any one operand are implicity requiring AVX512VL support if the actual
4981 operand size is YMMword or XMMword. Since this function runs after
4982 template matching, there's no need to check for YMMword/XMMword in
4984 cpu
= cpu_flags_and (t
->cpu_flags
, avx512
);
4985 if (!cpu_flags_all_zero (&cpu
)
4986 && !t
->cpu_flags
.bitfield
.cpuavx512vl
4987 && !cpu_arch_flags
.bitfield
.cpuavx512vl
)
4989 for (op
= 0; op
< t
->operands
; ++op
)
4991 if (t
->operand_types
[op
].bitfield
.zmmword
4992 && (i
.types
[op
].bitfield
.ymmword
4993 || i
.types
[op
].bitfield
.xmmword
))
4995 i
.error
= unsupported
;
5001 /* Without VSIB byte, we can't have a vector register for index. */
5002 if (!t
->opcode_modifier
.vecsib
5004 && (i
.index_reg
->reg_type
.bitfield
.xmmword
5005 || i
.index_reg
->reg_type
.bitfield
.ymmword
5006 || i
.index_reg
->reg_type
.bitfield
.zmmword
))
5008 i
.error
= unsupported_vector_index_register
;
5012 /* Check if default mask is allowed. */
5013 if (t
->opcode_modifier
.nodefmask
5014 && (!i
.mask
|| i
.mask
->mask
->reg_num
== 0))
5016 i
.error
= no_default_mask
;
5020 /* For VSIB byte, we need a vector register for index, and all vector
5021 registers must be distinct. */
5022 if (t
->opcode_modifier
.vecsib
)
5025 || !((t
->opcode_modifier
.vecsib
== VecSIB128
5026 && i
.index_reg
->reg_type
.bitfield
.xmmword
)
5027 || (t
->opcode_modifier
.vecsib
== VecSIB256
5028 && i
.index_reg
->reg_type
.bitfield
.ymmword
)
5029 || (t
->opcode_modifier
.vecsib
== VecSIB512
5030 && i
.index_reg
->reg_type
.bitfield
.zmmword
)))
5032 i
.error
= invalid_vsib_address
;
5036 gas_assert (i
.reg_operands
== 2 || i
.mask
);
5037 if (i
.reg_operands
== 2 && !i
.mask
)
5039 gas_assert (i
.types
[0].bitfield
.regsimd
);
5040 gas_assert (i
.types
[0].bitfield
.xmmword
5041 || i
.types
[0].bitfield
.ymmword
);
5042 gas_assert (i
.types
[2].bitfield
.regsimd
);
5043 gas_assert (i
.types
[2].bitfield
.xmmword
5044 || i
.types
[2].bitfield
.ymmword
);
5045 if (operand_check
== check_none
)
5047 if (register_number (i
.op
[0].regs
)
5048 != register_number (i
.index_reg
)
5049 && register_number (i
.op
[2].regs
)
5050 != register_number (i
.index_reg
)
5051 && register_number (i
.op
[0].regs
)
5052 != register_number (i
.op
[2].regs
))
5054 if (operand_check
== check_error
)
5056 i
.error
= invalid_vector_register_set
;
5059 as_warn (_("mask, index, and destination registers should be distinct"));
5061 else if (i
.reg_operands
== 1 && i
.mask
)
5063 if (i
.types
[1].bitfield
.regsimd
5064 && (i
.types
[1].bitfield
.xmmword
5065 || i
.types
[1].bitfield
.ymmword
5066 || i
.types
[1].bitfield
.zmmword
)
5067 && (register_number (i
.op
[1].regs
)
5068 == register_number (i
.index_reg
)))
5070 if (operand_check
== check_error
)
5072 i
.error
= invalid_vector_register_set
;
5075 if (operand_check
!= check_none
)
5076 as_warn (_("index and destination registers should be distinct"));
5081 /* Check if broadcast is supported by the instruction and is applied
5082 to the memory operand. */
5085 i386_operand_type type
, overlap
;
5087 /* Check if specified broadcast is supported in this instruction,
5088 and it's applied to memory operand of DWORD or QWORD type. */
5089 op
= i
.broadcast
->operand
;
5090 if (!t
->opcode_modifier
.broadcast
5091 || !i
.types
[op
].bitfield
.mem
5092 || (!i
.types
[op
].bitfield
.unspecified
5093 && (t
->operand_types
[op
].bitfield
.dword
5094 ? !i
.types
[op
].bitfield
.dword
5095 : !i
.types
[op
].bitfield
.qword
)))
5098 i
.error
= unsupported_broadcast
;
5102 operand_type_set (&type
, 0);
5103 switch ((t
->operand_types
[op
].bitfield
.dword
? 4 : 8) * i
.broadcast
->type
)
5106 type
.bitfield
.qword
= 1;
5109 type
.bitfield
.xmmword
= 1;
5112 type
.bitfield
.ymmword
= 1;
5115 type
.bitfield
.zmmword
= 1;
5121 overlap
= operand_type_and (type
, t
->operand_types
[op
]);
5122 if (operand_type_all_zero (&overlap
))
5125 if (t
->opcode_modifier
.checkregsize
)
5129 type
.bitfield
.baseindex
= 1;
5130 for (j
= 0; j
< i
.operands
; ++j
)
5133 && !operand_type_register_match(i
.types
[j
],
5134 t
->operand_types
[j
],
5136 t
->operand_types
[op
]))
5141 /* If broadcast is supported in this instruction, we need to check if
5142 operand of one-element size isn't specified without broadcast. */
5143 else if (t
->opcode_modifier
.broadcast
&& i
.mem_operands
)
5145 /* Find memory operand. */
5146 for (op
= 0; op
< i
.operands
; op
++)
5147 if (operand_type_check (i
.types
[op
], anymem
))
5149 gas_assert (op
< i
.operands
);
5150 /* Check size of the memory operand. */
5151 if (t
->operand_types
[op
].bitfield
.dword
5152 ? i
.types
[op
].bitfield
.dword
5153 : i
.types
[op
].bitfield
.qword
)
5155 i
.error
= broadcast_needed
;
5160 op
= MAX_OPERANDS
- 1; /* Avoid uninitialized variable warning. */
5162 /* Check if requested masking is supported. */
5164 && (!t
->opcode_modifier
.masking
5166 && t
->opcode_modifier
.masking
== MERGING_MASKING
)))
5168 i
.error
= unsupported_masking
;
5172 /* Check if masking is applied to dest operand. */
5173 if (i
.mask
&& (i
.mask
->operand
!= (int) (i
.operands
- 1)))
5175 i
.error
= mask_not_on_destination
;
5182 if ((i
.rounding
->type
!= saeonly
5183 && !t
->opcode_modifier
.staticrounding
)
5184 || (i
.rounding
->type
== saeonly
5185 && (t
->opcode_modifier
.staticrounding
5186 || !t
->opcode_modifier
.sae
)))
5188 i
.error
= unsupported_rc_sae
;
5191 /* If the instruction has several immediate operands and one of
5192 them is rounding, the rounding operand should be the last
5193 immediate operand. */
5194 if (i
.imm_operands
> 1
5195 && i
.rounding
->operand
!= (int) (i
.imm_operands
- 1))
5197 i
.error
= rc_sae_operand_not_last_imm
;
5202 /* Check vector Disp8 operand. */
5203 if (t
->opcode_modifier
.disp8memshift
5204 && i
.disp_encoding
!= disp_encoding_32bit
)
5207 i
.memshift
= t
->operand_types
[op
].bitfield
.dword
? 2 : 3;
5209 i
.memshift
= t
->opcode_modifier
.disp8memshift
;
5211 for (op
= 0; op
< i
.operands
; op
++)
5212 if (operand_type_check (i
.types
[op
], disp
)
5213 && i
.op
[op
].disps
->X_op
== O_constant
)
5215 if (fits_in_disp8 (i
.op
[op
].disps
->X_add_number
))
5217 i
.types
[op
].bitfield
.disp8
= 1;
5220 i
.types
[op
].bitfield
.disp8
= 0;
5229 /* Check if operands are valid for the instruction. Update VEX
5233 VEX_check_operands (const insn_template
*t
)
5235 if (i
.vec_encoding
== vex_encoding_evex
)
5237 /* This instruction must be encoded with EVEX prefix. */
5238 if (!is_evex_encoding (t
))
5240 i
.error
= unsupported
;
5246 if (!t
->opcode_modifier
.vex
)
5248 /* This instruction template doesn't have VEX prefix. */
5249 if (i
.vec_encoding
!= vex_encoding_default
)
5251 i
.error
= unsupported
;
5257 /* Only check VEX_Imm4, which must be the first operand. */
5258 if (t
->operand_types
[0].bitfield
.vec_imm4
)
5260 if (i
.op
[0].imms
->X_op
!= O_constant
5261 || !fits_in_imm4 (i
.op
[0].imms
->X_add_number
))
5267 /* Turn off Imm8 so that update_imm won't complain. */
5268 i
.types
[0] = vec_imm4
;
5274 static const insn_template
*
5275 match_template (char mnem_suffix
)
5277 /* Points to template once we've found it. */
5278 const insn_template
*t
;
5279 i386_operand_type overlap0
, overlap1
, overlap2
, overlap3
;
5280 i386_operand_type overlap4
;
5281 unsigned int found_reverse_match
;
5282 i386_opcode_modifier suffix_check
, mnemsuf_check
;
5283 i386_operand_type operand_types
[MAX_OPERANDS
];
5284 int addr_prefix_disp
;
5286 unsigned int found_cpu_match
;
5287 unsigned int check_register
;
5288 enum i386_error specific_error
= 0;
5290 #if MAX_OPERANDS != 5
5291 # error "MAX_OPERANDS must be 5."
5294 found_reverse_match
= 0;
5295 addr_prefix_disp
= -1;
5297 memset (&suffix_check
, 0, sizeof (suffix_check
));
5298 if (intel_syntax
&& i
.broadcast
)
5300 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
5301 suffix_check
.no_bsuf
= 1;
5302 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
5303 suffix_check
.no_wsuf
= 1;
5304 else if (i
.suffix
== SHORT_MNEM_SUFFIX
)
5305 suffix_check
.no_ssuf
= 1;
5306 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
5307 suffix_check
.no_lsuf
= 1;
5308 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
5309 suffix_check
.no_qsuf
= 1;
5310 else if (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
)
5311 suffix_check
.no_ldsuf
= 1;
5313 memset (&mnemsuf_check
, 0, sizeof (mnemsuf_check
));
5316 switch (mnem_suffix
)
5318 case BYTE_MNEM_SUFFIX
: mnemsuf_check
.no_bsuf
= 1; break;
5319 case WORD_MNEM_SUFFIX
: mnemsuf_check
.no_wsuf
= 1; break;
5320 case SHORT_MNEM_SUFFIX
: mnemsuf_check
.no_ssuf
= 1; break;
5321 case LONG_MNEM_SUFFIX
: mnemsuf_check
.no_lsuf
= 1; break;
5322 case QWORD_MNEM_SUFFIX
: mnemsuf_check
.no_qsuf
= 1; break;
5326 /* Must have right number of operands. */
5327 i
.error
= number_of_operands_mismatch
;
5329 for (t
= current_templates
->start
; t
< current_templates
->end
; t
++)
5331 addr_prefix_disp
= -1;
5333 if (i
.operands
!= t
->operands
)
5336 /* Check processor support. */
5337 i
.error
= unsupported
;
5338 found_cpu_match
= (cpu_flags_match (t
)
5339 == CPU_FLAGS_PERFECT_MATCH
);
5340 if (!found_cpu_match
)
5343 /* Check AT&T mnemonic. */
5344 i
.error
= unsupported_with_intel_mnemonic
;
5345 if (intel_mnemonic
&& t
->opcode_modifier
.attmnemonic
)
5348 /* Check AT&T/Intel syntax and Intel64/AMD64 ISA. */
5349 i
.error
= unsupported_syntax
;
5350 if ((intel_syntax
&& t
->opcode_modifier
.attsyntax
)
5351 || (!intel_syntax
&& t
->opcode_modifier
.intelsyntax
)
5352 || (intel64
&& t
->opcode_modifier
.amd64
)
5353 || (!intel64
&& t
->opcode_modifier
.intel64
))
5356 /* Check the suffix, except for some instructions in intel mode. */
5357 i
.error
= invalid_instruction_suffix
;
5358 if ((!intel_syntax
|| !t
->opcode_modifier
.ignoresize
)
5359 && ((t
->opcode_modifier
.no_bsuf
&& suffix_check
.no_bsuf
)
5360 || (t
->opcode_modifier
.no_wsuf
&& suffix_check
.no_wsuf
)
5361 || (t
->opcode_modifier
.no_lsuf
&& suffix_check
.no_lsuf
)
5362 || (t
->opcode_modifier
.no_ssuf
&& suffix_check
.no_ssuf
)
5363 || (t
->opcode_modifier
.no_qsuf
&& suffix_check
.no_qsuf
)
5364 || (t
->opcode_modifier
.no_ldsuf
&& suffix_check
.no_ldsuf
)))
5366 /* In Intel mode all mnemonic suffixes must be explicitly allowed. */
5367 if ((t
->opcode_modifier
.no_bsuf
&& mnemsuf_check
.no_bsuf
)
5368 || (t
->opcode_modifier
.no_wsuf
&& mnemsuf_check
.no_wsuf
)
5369 || (t
->opcode_modifier
.no_lsuf
&& mnemsuf_check
.no_lsuf
)
5370 || (t
->opcode_modifier
.no_ssuf
&& mnemsuf_check
.no_ssuf
)
5371 || (t
->opcode_modifier
.no_qsuf
&& mnemsuf_check
.no_qsuf
)
5372 || (t
->opcode_modifier
.no_ldsuf
&& mnemsuf_check
.no_ldsuf
))
5375 if (!operand_size_match (t
))
5378 for (j
= 0; j
< MAX_OPERANDS
; j
++)
5379 operand_types
[j
] = t
->operand_types
[j
];
5381 /* In general, don't allow 64-bit operands in 32-bit mode. */
5382 if (i
.suffix
== QWORD_MNEM_SUFFIX
5383 && flag_code
!= CODE_64BIT
5385 ? (!t
->opcode_modifier
.ignoresize
5386 && !intel_float_operand (t
->name
))
5387 : intel_float_operand (t
->name
) != 2)
5388 && ((!operand_types
[0].bitfield
.regmmx
5389 && !operand_types
[0].bitfield
.regsimd
)
5390 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
5391 && !operand_types
[t
->operands
> 1].bitfield
.regsimd
))
5392 && (t
->base_opcode
!= 0x0fc7
5393 || t
->extension_opcode
!= 1 /* cmpxchg8b */))
5396 /* In general, don't allow 32-bit operands on pre-386. */
5397 else if (i
.suffix
== LONG_MNEM_SUFFIX
5398 && !cpu_arch_flags
.bitfield
.cpui386
5400 ? (!t
->opcode_modifier
.ignoresize
5401 && !intel_float_operand (t
->name
))
5402 : intel_float_operand (t
->name
) != 2)
5403 && ((!operand_types
[0].bitfield
.regmmx
5404 && !operand_types
[0].bitfield
.regsimd
)
5405 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
5406 && !operand_types
[t
->operands
> 1].bitfield
.regsimd
)))
5409 /* Do not verify operands when there are none. */
5413 /* We've found a match; break out of loop. */
5417 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
5418 into Disp32/Disp16/Disp32 operand. */
5419 if (i
.prefix
[ADDR_PREFIX
] != 0)
5421 /* There should be only one Disp operand. */
5425 for (j
= 0; j
< MAX_OPERANDS
; j
++)
5427 if (operand_types
[j
].bitfield
.disp16
)
5429 addr_prefix_disp
= j
;
5430 operand_types
[j
].bitfield
.disp32
= 1;
5431 operand_types
[j
].bitfield
.disp16
= 0;
5437 for (j
= 0; j
< MAX_OPERANDS
; j
++)
5439 if (operand_types
[j
].bitfield
.disp32
)
5441 addr_prefix_disp
= j
;
5442 operand_types
[j
].bitfield
.disp32
= 0;
5443 operand_types
[j
].bitfield
.disp16
= 1;
5449 for (j
= 0; j
< MAX_OPERANDS
; j
++)
5451 if (operand_types
[j
].bitfield
.disp64
)
5453 addr_prefix_disp
= j
;
5454 operand_types
[j
].bitfield
.disp64
= 0;
5455 operand_types
[j
].bitfield
.disp32
= 1;
5463 /* Force 0x8b encoding for "mov foo@GOT, %eax". */
5464 if (i
.reloc
[0] == BFD_RELOC_386_GOT32
&& t
->base_opcode
== 0xa0)
5467 /* We check register size if needed. */
5468 if (t
->opcode_modifier
.checkregsize
)
5470 check_register
= (1 << t
->operands
) - 1;
5472 check_register
&= ~(1 << i
.broadcast
->operand
);
5477 overlap0
= operand_type_and (i
.types
[0], operand_types
[0]);
5478 switch (t
->operands
)
5481 if (!operand_type_match (overlap0
, i
.types
[0]))
5485 /* xchg %eax, %eax is a special case. It is an alias for nop
5486 only in 32bit mode and we can use opcode 0x90. In 64bit
5487 mode, we can't use 0x90 for xchg %eax, %eax since it should
5488 zero-extend %eax to %rax. */
5489 if (flag_code
== CODE_64BIT
5490 && t
->base_opcode
== 0x90
5491 && operand_type_equal (&i
.types
[0], &acc32
)
5492 && operand_type_equal (&i
.types
[1], &acc32
))
5494 /* xrelease mov %eax, <disp> is another special case. It must not
5495 match the accumulator-only encoding of mov. */
5496 if (flag_code
!= CODE_64BIT
5498 && t
->base_opcode
== 0xa0
5499 && i
.types
[0].bitfield
.acc
5500 && operand_type_check (i
.types
[1], anymem
))
5502 /* If we want store form, we reverse direction of operands. */
5503 if (i
.dir_encoding
== dir_encoding_store
5504 && t
->opcode_modifier
.d
)
5509 /* If we want store form, we skip the current load. */
5510 if (i
.dir_encoding
== dir_encoding_store
5511 && i
.mem_operands
== 0
5512 && t
->opcode_modifier
.load
)
5517 overlap1
= operand_type_and (i
.types
[1], operand_types
[1]);
5518 if (!operand_type_match (overlap0
, i
.types
[0])
5519 || !operand_type_match (overlap1
, i
.types
[1])
5520 || ((check_register
& 3) == 3
5521 && !operand_type_register_match (i
.types
[0],
5526 /* Check if other direction is valid ... */
5527 if (!t
->opcode_modifier
.d
)
5531 /* Try reversing direction of operands. */
5532 overlap0
= operand_type_and (i
.types
[0], operand_types
[1]);
5533 overlap1
= operand_type_and (i
.types
[1], operand_types
[0]);
5534 if (!operand_type_match (overlap0
, i
.types
[0])
5535 || !operand_type_match (overlap1
, i
.types
[1])
5537 && !operand_type_register_match (i
.types
[0],
5542 /* Does not match either direction. */
5545 /* found_reverse_match holds which of D or FloatR
5547 if (!t
->opcode_modifier
.d
)
5548 found_reverse_match
= 0;
5549 else if (operand_types
[0].bitfield
.tbyte
)
5550 found_reverse_match
= Opcode_FloatD
;
5552 found_reverse_match
= Opcode_D
;
5553 if (t
->opcode_modifier
.floatr
)
5554 found_reverse_match
|= Opcode_FloatR
;
5558 /* Found a forward 2 operand match here. */
5559 switch (t
->operands
)
5562 overlap4
= operand_type_and (i
.types
[4],
5566 overlap3
= operand_type_and (i
.types
[3],
5570 overlap2
= operand_type_and (i
.types
[2],
5575 switch (t
->operands
)
5578 if (!operand_type_match (overlap4
, i
.types
[4])
5579 || !operand_type_register_match (i
.types
[3],
5586 if (!operand_type_match (overlap3
, i
.types
[3])
5587 || ((check_register
& 0xa) == 0xa
5588 && !operand_type_register_match (i
.types
[1],
5592 || ((check_register
& 0xc) == 0xc
5593 && !operand_type_register_match (i
.types
[2],
5600 /* Here we make use of the fact that there are no
5601 reverse match 3 operand instructions. */
5602 if (!operand_type_match (overlap2
, i
.types
[2])
5603 || ((check_register
& 5) == 5
5604 && !operand_type_register_match (i
.types
[0],
5608 || ((check_register
& 6) == 6
5609 && !operand_type_register_match (i
.types
[1],
5617 /* Found either forward/reverse 2, 3 or 4 operand match here:
5618 slip through to break. */
5620 if (!found_cpu_match
)
5622 found_reverse_match
= 0;
5626 /* Check if vector and VEX operands are valid. */
5627 if (check_VecOperands (t
) || VEX_check_operands (t
))
5629 specific_error
= i
.error
;
5633 /* We've found a match; break out of loop. */
5637 if (t
== current_templates
->end
)
5639 /* We found no match. */
5640 const char *err_msg
;
5641 switch (specific_error
? specific_error
: i
.error
)
5645 case operand_size_mismatch
:
5646 err_msg
= _("operand size mismatch");
5648 case operand_type_mismatch
:
5649 err_msg
= _("operand type mismatch");
5651 case register_type_mismatch
:
5652 err_msg
= _("register type mismatch");
5654 case number_of_operands_mismatch
:
5655 err_msg
= _("number of operands mismatch");
5657 case invalid_instruction_suffix
:
5658 err_msg
= _("invalid instruction suffix");
5661 err_msg
= _("constant doesn't fit in 4 bits");
5663 case unsupported_with_intel_mnemonic
:
5664 err_msg
= _("unsupported with Intel mnemonic");
5666 case unsupported_syntax
:
5667 err_msg
= _("unsupported syntax");
5670 as_bad (_("unsupported instruction `%s'"),
5671 current_templates
->start
->name
);
5673 case invalid_vsib_address
:
5674 err_msg
= _("invalid VSIB address");
5676 case invalid_vector_register_set
:
5677 err_msg
= _("mask, index, and destination registers must be distinct");
5679 case unsupported_vector_index_register
:
5680 err_msg
= _("unsupported vector index register");
5682 case unsupported_broadcast
:
5683 err_msg
= _("unsupported broadcast");
5685 case broadcast_not_on_src_operand
:
5686 err_msg
= _("broadcast not on source memory operand");
5688 case broadcast_needed
:
5689 err_msg
= _("broadcast is needed for operand of such type");
5691 case unsupported_masking
:
5692 err_msg
= _("unsupported masking");
5694 case mask_not_on_destination
:
5695 err_msg
= _("mask not on destination operand");
5697 case no_default_mask
:
5698 err_msg
= _("default mask isn't allowed");
5700 case unsupported_rc_sae
:
5701 err_msg
= _("unsupported static rounding/sae");
5703 case rc_sae_operand_not_last_imm
:
5705 err_msg
= _("RC/SAE operand must precede immediate operands");
5707 err_msg
= _("RC/SAE operand must follow immediate operands");
5709 case invalid_register_operand
:
5710 err_msg
= _("invalid register operand");
5713 as_bad (_("%s for `%s'"), err_msg
,
5714 current_templates
->start
->name
);
5718 if (!quiet_warnings
)
5721 && (i
.types
[0].bitfield
.jumpabsolute
5722 != operand_types
[0].bitfield
.jumpabsolute
))
5724 as_warn (_("indirect %s without `*'"), t
->name
);
5727 if (t
->opcode_modifier
.isprefix
5728 && t
->opcode_modifier
.ignoresize
)
5730 /* Warn them that a data or address size prefix doesn't
5731 affect assembly of the next line of code. */
5732 as_warn (_("stand-alone `%s' prefix"), t
->name
);
5736 /* Copy the template we found. */
5739 if (addr_prefix_disp
!= -1)
5740 i
.tm
.operand_types
[addr_prefix_disp
]
5741 = operand_types
[addr_prefix_disp
];
5743 if (found_reverse_match
)
5745 /* If we found a reverse match we must alter the opcode
5746 direction bit. found_reverse_match holds bits to change
5747 (different for int & float insns). */
5749 i
.tm
.base_opcode
^= found_reverse_match
;
5751 i
.tm
.operand_types
[0] = operand_types
[1];
5752 i
.tm
.operand_types
[1] = operand_types
[0];
5761 int mem_op
= operand_type_check (i
.types
[0], anymem
) ? 0 : 1;
5762 if (i
.tm
.operand_types
[mem_op
].bitfield
.esseg
)
5764 if (i
.seg
[0] != NULL
&& i
.seg
[0] != &es
)
5766 as_bad (_("`%s' operand %d must use `%ses' segment"),
5772 /* There's only ever one segment override allowed per instruction.
5773 This instruction possibly has a legal segment override on the
5774 second operand, so copy the segment to where non-string
5775 instructions store it, allowing common code. */
5776 i
.seg
[0] = i
.seg
[1];
5778 else if (i
.tm
.operand_types
[mem_op
+ 1].bitfield
.esseg
)
5780 if (i
.seg
[1] != NULL
&& i
.seg
[1] != &es
)
5782 as_bad (_("`%s' operand %d must use `%ses' segment"),
5793 process_suffix (void)
5795 /* If matched instruction specifies an explicit instruction mnemonic
5797 if (i
.tm
.opcode_modifier
.size16
)
5798 i
.suffix
= WORD_MNEM_SUFFIX
;
5799 else if (i
.tm
.opcode_modifier
.size32
)
5800 i
.suffix
= LONG_MNEM_SUFFIX
;
5801 else if (i
.tm
.opcode_modifier
.size64
)
5802 i
.suffix
= QWORD_MNEM_SUFFIX
;
5803 else if (i
.reg_operands
)
5805 /* If there's no instruction mnemonic suffix we try to invent one
5806 based on register operands. */
5809 /* We take i.suffix from the last register operand specified,
5810 Destination register type is more significant than source
5811 register type. crc32 in SSE4.2 prefers source register
5813 if (i
.tm
.base_opcode
== 0xf20f38f1)
5815 if (i
.types
[0].bitfield
.reg
&& i
.types
[0].bitfield
.word
)
5816 i
.suffix
= WORD_MNEM_SUFFIX
;
5817 else if (i
.types
[0].bitfield
.reg
&& i
.types
[0].bitfield
.dword
)
5818 i
.suffix
= LONG_MNEM_SUFFIX
;
5819 else if (i
.types
[0].bitfield
.reg
&& i
.types
[0].bitfield
.qword
)
5820 i
.suffix
= QWORD_MNEM_SUFFIX
;
5822 else if (i
.tm
.base_opcode
== 0xf20f38f0)
5824 if (i
.types
[0].bitfield
.reg
&& i
.types
[0].bitfield
.byte
)
5825 i
.suffix
= BYTE_MNEM_SUFFIX
;
5832 if (i
.tm
.base_opcode
== 0xf20f38f1
5833 || i
.tm
.base_opcode
== 0xf20f38f0)
5835 /* We have to know the operand size for crc32. */
5836 as_bad (_("ambiguous memory operand size for `%s`"),
5841 for (op
= i
.operands
; --op
>= 0;)
5842 if (!i
.tm
.operand_types
[op
].bitfield
.inoutportreg
5843 && !i
.tm
.operand_types
[op
].bitfield
.shiftcount
)
5845 if (!i
.types
[op
].bitfield
.reg
)
5847 if (i
.types
[op
].bitfield
.byte
)
5848 i
.suffix
= BYTE_MNEM_SUFFIX
;
5849 else if (i
.types
[op
].bitfield
.word
)
5850 i
.suffix
= WORD_MNEM_SUFFIX
;
5851 else if (i
.types
[op
].bitfield
.dword
)
5852 i
.suffix
= LONG_MNEM_SUFFIX
;
5853 else if (i
.types
[op
].bitfield
.qword
)
5854 i
.suffix
= QWORD_MNEM_SUFFIX
;
5861 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
5864 && i
.tm
.opcode_modifier
.ignoresize
5865 && i
.tm
.opcode_modifier
.no_bsuf
)
5867 else if (!check_byte_reg ())
5870 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
5873 && i
.tm
.opcode_modifier
.ignoresize
5874 && i
.tm
.opcode_modifier
.no_lsuf
5875 && !i
.tm
.opcode_modifier
.todword
5876 && !i
.tm
.opcode_modifier
.toqword
)
5878 else if (!check_long_reg ())
5881 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
5884 && i
.tm
.opcode_modifier
.ignoresize
5885 && i
.tm
.opcode_modifier
.no_qsuf
5886 && !i
.tm
.opcode_modifier
.todword
5887 && !i
.tm
.opcode_modifier
.toqword
)
5889 else if (!check_qword_reg ())
5892 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
5895 && i
.tm
.opcode_modifier
.ignoresize
5896 && i
.tm
.opcode_modifier
.no_wsuf
)
5898 else if (!check_word_reg ())
5901 else if (intel_syntax
&& i
.tm
.opcode_modifier
.ignoresize
)
5902 /* Do nothing if the instruction is going to ignore the prefix. */
5907 else if (i
.tm
.opcode_modifier
.defaultsize
5909 /* exclude fldenv/frstor/fsave/fstenv */
5910 && i
.tm
.opcode_modifier
.no_ssuf
)
5912 i
.suffix
= stackop_size
;
5914 else if (intel_syntax
5916 && (i
.tm
.operand_types
[0].bitfield
.jumpabsolute
5917 || i
.tm
.opcode_modifier
.jumpbyte
5918 || i
.tm
.opcode_modifier
.jumpintersegment
5919 || (i
.tm
.base_opcode
== 0x0f01 /* [ls][gi]dt */
5920 && i
.tm
.extension_opcode
<= 3)))
5925 if (!i
.tm
.opcode_modifier
.no_qsuf
)
5927 i
.suffix
= QWORD_MNEM_SUFFIX
;
5932 if (!i
.tm
.opcode_modifier
.no_lsuf
)
5933 i
.suffix
= LONG_MNEM_SUFFIX
;
5936 if (!i
.tm
.opcode_modifier
.no_wsuf
)
5937 i
.suffix
= WORD_MNEM_SUFFIX
;
5946 if (i
.tm
.opcode_modifier
.w
)
5948 as_bad (_("no instruction mnemonic suffix given and "
5949 "no register operands; can't size instruction"));
5955 unsigned int suffixes
;
5957 suffixes
= !i
.tm
.opcode_modifier
.no_bsuf
;
5958 if (!i
.tm
.opcode_modifier
.no_wsuf
)
5960 if (!i
.tm
.opcode_modifier
.no_lsuf
)
5962 if (!i
.tm
.opcode_modifier
.no_ldsuf
)
5964 if (!i
.tm
.opcode_modifier
.no_ssuf
)
5966 if (flag_code
== CODE_64BIT
&& !i
.tm
.opcode_modifier
.no_qsuf
)
5969 /* There are more than suffix matches. */
5970 if (i
.tm
.opcode_modifier
.w
5971 || ((suffixes
& (suffixes
- 1))
5972 && !i
.tm
.opcode_modifier
.defaultsize
5973 && !i
.tm
.opcode_modifier
.ignoresize
))
5975 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
5981 /* Change the opcode based on the operand size given by i.suffix. */
5984 /* Size floating point instruction. */
5985 case LONG_MNEM_SUFFIX
:
5986 if (i
.tm
.opcode_modifier
.floatmf
)
5988 i
.tm
.base_opcode
^= 4;
5992 case WORD_MNEM_SUFFIX
:
5993 case QWORD_MNEM_SUFFIX
:
5994 /* It's not a byte, select word/dword operation. */
5995 if (i
.tm
.opcode_modifier
.w
)
5997 if (i
.tm
.opcode_modifier
.shortform
)
5998 i
.tm
.base_opcode
|= 8;
6000 i
.tm
.base_opcode
|= 1;
6003 case SHORT_MNEM_SUFFIX
:
6004 /* Now select between word & dword operations via the operand
6005 size prefix, except for instructions that will ignore this
6007 if (i
.reg_operands
> 0
6008 && i
.types
[0].bitfield
.reg
6009 && i
.tm
.opcode_modifier
.addrprefixopreg
6010 && (i
.tm
.opcode_modifier
.immext
6011 || i
.operands
== 1))
6013 /* The address size override prefix changes the size of the
6015 if ((flag_code
== CODE_32BIT
6016 && i
.op
[0].regs
->reg_type
.bitfield
.word
)
6017 || (flag_code
!= CODE_32BIT
6018 && i
.op
[0].regs
->reg_type
.bitfield
.dword
))
6019 if (!add_prefix (ADDR_PREFIX_OPCODE
))
6022 else if (i
.suffix
!= QWORD_MNEM_SUFFIX
6023 && !i
.tm
.opcode_modifier
.ignoresize
6024 && !i
.tm
.opcode_modifier
.floatmf
6025 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
6026 || (flag_code
== CODE_64BIT
6027 && i
.tm
.opcode_modifier
.jumpbyte
)))
6029 unsigned int prefix
= DATA_PREFIX_OPCODE
;
6031 if (i
.tm
.opcode_modifier
.jumpbyte
) /* jcxz, loop */
6032 prefix
= ADDR_PREFIX_OPCODE
;
6034 if (!add_prefix (prefix
))
6038 /* Set mode64 for an operand. */
6039 if (i
.suffix
== QWORD_MNEM_SUFFIX
6040 && flag_code
== CODE_64BIT
6041 && !i
.tm
.opcode_modifier
.norex64
6042 /* Special case for xchg %rax,%rax. It is NOP and doesn't
6044 && ! (i
.operands
== 2
6045 && i
.tm
.base_opcode
== 0x90
6046 && i
.tm
.extension_opcode
== None
6047 && operand_type_equal (&i
.types
[0], &acc64
)
6048 && operand_type_equal (&i
.types
[1], &acc64
)))
6054 if (i
.reg_operands
!= 0
6056 && i
.tm
.opcode_modifier
.addrprefixopreg
6057 && !i
.tm
.opcode_modifier
.immext
)
6059 /* Check invalid register operand when the address size override
6060 prefix changes the size of register operands. */
6062 enum { need_word
, need_dword
, need_qword
} need
;
6064 if (flag_code
== CODE_32BIT
)
6065 need
= i
.prefix
[ADDR_PREFIX
] ? need_word
: need_dword
;
6068 if (i
.prefix
[ADDR_PREFIX
])
6071 need
= flag_code
== CODE_64BIT
? need_qword
: need_word
;
6074 for (op
= 0; op
< i
.operands
; op
++)
6075 if (i
.types
[op
].bitfield
.reg
6076 && ((need
== need_word
6077 && !i
.op
[op
].regs
->reg_type
.bitfield
.word
)
6078 || (need
== need_dword
6079 && !i
.op
[op
].regs
->reg_type
.bitfield
.dword
)
6080 || (need
== need_qword
6081 && !i
.op
[op
].regs
->reg_type
.bitfield
.qword
)))
6083 as_bad (_("invalid register operand size for `%s'"),
6093 check_byte_reg (void)
6097 for (op
= i
.operands
; --op
>= 0;)
6099 /* Skip non-register operands. */
6100 if (!i
.types
[op
].bitfield
.reg
)
6103 /* If this is an eight bit register, it's OK. If it's the 16 or
6104 32 bit version of an eight bit register, we will just use the
6105 low portion, and that's OK too. */
6106 if (i
.types
[op
].bitfield
.byte
)
6109 /* I/O port address operands are OK too. */
6110 if (i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
6113 /* crc32 doesn't generate this warning. */
6114 if (i
.tm
.base_opcode
== 0xf20f38f0)
6117 if ((i
.types
[op
].bitfield
.word
6118 || i
.types
[op
].bitfield
.dword
6119 || i
.types
[op
].bitfield
.qword
)
6120 && i
.op
[op
].regs
->reg_num
< 4
6121 /* Prohibit these changes in 64bit mode, since the lowering
6122 would be more complicated. */
6123 && flag_code
!= CODE_64BIT
)
6125 #if REGISTER_WARNINGS
6126 if (!quiet_warnings
)
6127 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6129 (i
.op
[op
].regs
+ (i
.types
[op
].bitfield
.word
6130 ? REGNAM_AL
- REGNAM_AX
6131 : REGNAM_AL
- REGNAM_EAX
))->reg_name
,
6133 i
.op
[op
].regs
->reg_name
,
6138 /* Any other register is bad. */
6139 if (i
.types
[op
].bitfield
.reg
6140 || i
.types
[op
].bitfield
.regmmx
6141 || i
.types
[op
].bitfield
.regsimd
6142 || i
.types
[op
].bitfield
.sreg2
6143 || i
.types
[op
].bitfield
.sreg3
6144 || i
.types
[op
].bitfield
.control
6145 || i
.types
[op
].bitfield
.debug
6146 || i
.types
[op
].bitfield
.test
)
6148 as_bad (_("`%s%s' not allowed with `%s%c'"),
6150 i
.op
[op
].regs
->reg_name
,
6160 check_long_reg (void)
6164 for (op
= i
.operands
; --op
>= 0;)
6165 /* Skip non-register operands. */
6166 if (!i
.types
[op
].bitfield
.reg
)
6168 /* Reject eight bit registers, except where the template requires
6169 them. (eg. movzb) */
6170 else if (i
.types
[op
].bitfield
.byte
6171 && (i
.tm
.operand_types
[op
].bitfield
.reg
6172 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6173 && (i
.tm
.operand_types
[op
].bitfield
.word
6174 || i
.tm
.operand_types
[op
].bitfield
.dword
))
6176 as_bad (_("`%s%s' not allowed with `%s%c'"),
6178 i
.op
[op
].regs
->reg_name
,
6183 /* Warn if the e prefix on a general reg is missing. */
6184 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
6185 && i
.types
[op
].bitfield
.word
6186 && (i
.tm
.operand_types
[op
].bitfield
.reg
6187 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6188 && i
.tm
.operand_types
[op
].bitfield
.dword
)
6190 /* Prohibit these changes in the 64bit mode, since the
6191 lowering is more complicated. */
6192 if (flag_code
== CODE_64BIT
)
6194 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6195 register_prefix
, i
.op
[op
].regs
->reg_name
,
6199 #if REGISTER_WARNINGS
6200 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6202 (i
.op
[op
].regs
+ REGNAM_EAX
- REGNAM_AX
)->reg_name
,
6203 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
6206 /* Warn if the r prefix on a general reg is present. */
6207 else if (i
.types
[op
].bitfield
.qword
6208 && (i
.tm
.operand_types
[op
].bitfield
.reg
6209 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6210 && i
.tm
.operand_types
[op
].bitfield
.dword
)
6213 && i
.tm
.opcode_modifier
.toqword
6214 && !i
.types
[0].bitfield
.regsimd
)
6216 /* Convert to QWORD. We want REX byte. */
6217 i
.suffix
= QWORD_MNEM_SUFFIX
;
6221 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6222 register_prefix
, i
.op
[op
].regs
->reg_name
,
6231 check_qword_reg (void)
6235 for (op
= i
.operands
; --op
>= 0; )
6236 /* Skip non-register operands. */
6237 if (!i
.types
[op
].bitfield
.reg
)
6239 /* Reject eight bit registers, except where the template requires
6240 them. (eg. movzb) */
6241 else if (i
.types
[op
].bitfield
.byte
6242 && (i
.tm
.operand_types
[op
].bitfield
.reg
6243 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6244 && (i
.tm
.operand_types
[op
].bitfield
.word
6245 || i
.tm
.operand_types
[op
].bitfield
.dword
))
6247 as_bad (_("`%s%s' not allowed with `%s%c'"),
6249 i
.op
[op
].regs
->reg_name
,
6254 /* Warn if the r prefix on a general reg is missing. */
6255 else if ((i
.types
[op
].bitfield
.word
6256 || i
.types
[op
].bitfield
.dword
)
6257 && (i
.tm
.operand_types
[op
].bitfield
.reg
6258 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6259 && i
.tm
.operand_types
[op
].bitfield
.qword
)
6261 /* Prohibit these changes in the 64bit mode, since the
6262 lowering is more complicated. */
6264 && i
.tm
.opcode_modifier
.todword
6265 && !i
.types
[0].bitfield
.regsimd
)
6267 /* Convert to DWORD. We don't want REX byte. */
6268 i
.suffix
= LONG_MNEM_SUFFIX
;
6272 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6273 register_prefix
, i
.op
[op
].regs
->reg_name
,
6282 check_word_reg (void)
6285 for (op
= i
.operands
; --op
>= 0;)
6286 /* Skip non-register operands. */
6287 if (!i
.types
[op
].bitfield
.reg
)
6289 /* Reject eight bit registers, except where the template requires
6290 them. (eg. movzb) */
6291 else if (i
.types
[op
].bitfield
.byte
6292 && (i
.tm
.operand_types
[op
].bitfield
.reg
6293 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6294 && (i
.tm
.operand_types
[op
].bitfield
.word
6295 || i
.tm
.operand_types
[op
].bitfield
.dword
))
6297 as_bad (_("`%s%s' not allowed with `%s%c'"),
6299 i
.op
[op
].regs
->reg_name
,
6304 /* Warn if the e or r prefix on a general reg is present. */
6305 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
6306 && (i
.types
[op
].bitfield
.dword
6307 || i
.types
[op
].bitfield
.qword
)
6308 && (i
.tm
.operand_types
[op
].bitfield
.reg
6309 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6310 && i
.tm
.operand_types
[op
].bitfield
.word
)
6312 /* Prohibit these changes in the 64bit mode, since the
6313 lowering is more complicated. */
6314 if (flag_code
== CODE_64BIT
)
6316 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6317 register_prefix
, i
.op
[op
].regs
->reg_name
,
6321 #if REGISTER_WARNINGS
6322 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6324 (i
.op
[op
].regs
+ REGNAM_AX
- REGNAM_EAX
)->reg_name
,
6325 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
6332 update_imm (unsigned int j
)
6334 i386_operand_type overlap
= i
.types
[j
];
6335 if ((overlap
.bitfield
.imm8
6336 || overlap
.bitfield
.imm8s
6337 || overlap
.bitfield
.imm16
6338 || overlap
.bitfield
.imm32
6339 || overlap
.bitfield
.imm32s
6340 || overlap
.bitfield
.imm64
)
6341 && !operand_type_equal (&overlap
, &imm8
)
6342 && !operand_type_equal (&overlap
, &imm8s
)
6343 && !operand_type_equal (&overlap
, &imm16
)
6344 && !operand_type_equal (&overlap
, &imm32
)
6345 && !operand_type_equal (&overlap
, &imm32s
)
6346 && !operand_type_equal (&overlap
, &imm64
))
6350 i386_operand_type temp
;
6352 operand_type_set (&temp
, 0);
6353 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
6355 temp
.bitfield
.imm8
= overlap
.bitfield
.imm8
;
6356 temp
.bitfield
.imm8s
= overlap
.bitfield
.imm8s
;
6358 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
6359 temp
.bitfield
.imm16
= overlap
.bitfield
.imm16
;
6360 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
6362 temp
.bitfield
.imm64
= overlap
.bitfield
.imm64
;
6363 temp
.bitfield
.imm32s
= overlap
.bitfield
.imm32s
;
6366 temp
.bitfield
.imm32
= overlap
.bitfield
.imm32
;
6369 else if (operand_type_equal (&overlap
, &imm16_32_32s
)
6370 || operand_type_equal (&overlap
, &imm16_32
)
6371 || operand_type_equal (&overlap
, &imm16_32s
))
6373 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
6378 if (!operand_type_equal (&overlap
, &imm8
)
6379 && !operand_type_equal (&overlap
, &imm8s
)
6380 && !operand_type_equal (&overlap
, &imm16
)
6381 && !operand_type_equal (&overlap
, &imm32
)
6382 && !operand_type_equal (&overlap
, &imm32s
)
6383 && !operand_type_equal (&overlap
, &imm64
))
6385 as_bad (_("no instruction mnemonic suffix given; "
6386 "can't determine immediate size"));
6390 i
.types
[j
] = overlap
;
6400 /* Update the first 2 immediate operands. */
6401 n
= i
.operands
> 2 ? 2 : i
.operands
;
6404 for (j
= 0; j
< n
; j
++)
6405 if (update_imm (j
) == 0)
6408 /* The 3rd operand can't be immediate operand. */
6409 gas_assert (operand_type_check (i
.types
[2], imm
) == 0);
6416 process_operands (void)
6418 /* Default segment register this instruction will use for memory
6419 accesses. 0 means unknown. This is only for optimizing out
6420 unnecessary segment overrides. */
6421 const seg_entry
*default_seg
= 0;
6423 if (i
.tm
.opcode_modifier
.sse2avx
&& i
.tm
.opcode_modifier
.vexvvvv
)
6425 unsigned int dupl
= i
.operands
;
6426 unsigned int dest
= dupl
- 1;
6429 /* The destination must be an xmm register. */
6430 gas_assert (i
.reg_operands
6431 && MAX_OPERANDS
> dupl
6432 && operand_type_equal (&i
.types
[dest
], ®xmm
));
6434 if (i
.tm
.operand_types
[0].bitfield
.acc
6435 && i
.tm
.operand_types
[0].bitfield
.xmmword
)
6437 if (i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
)
6439 /* Keep xmm0 for instructions with VEX prefix and 3
6441 i
.tm
.operand_types
[0].bitfield
.acc
= 0;
6442 i
.tm
.operand_types
[0].bitfield
.regsimd
= 1;
6447 /* We remove the first xmm0 and keep the number of
6448 operands unchanged, which in fact duplicates the
6450 for (j
= 1; j
< i
.operands
; j
++)
6452 i
.op
[j
- 1] = i
.op
[j
];
6453 i
.types
[j
- 1] = i
.types
[j
];
6454 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
6458 else if (i
.tm
.opcode_modifier
.implicit1stxmm0
)
6460 gas_assert ((MAX_OPERANDS
- 1) > dupl
6461 && (i
.tm
.opcode_modifier
.vexsources
6464 /* Add the implicit xmm0 for instructions with VEX prefix
6466 for (j
= i
.operands
; j
> 0; j
--)
6468 i
.op
[j
] = i
.op
[j
- 1];
6469 i
.types
[j
] = i
.types
[j
- 1];
6470 i
.tm
.operand_types
[j
] = i
.tm
.operand_types
[j
- 1];
6473 = (const reg_entry
*) hash_find (reg_hash
, "xmm0");
6474 i
.types
[0] = regxmm
;
6475 i
.tm
.operand_types
[0] = regxmm
;
6478 i
.reg_operands
+= 2;
6483 i
.op
[dupl
] = i
.op
[dest
];
6484 i
.types
[dupl
] = i
.types
[dest
];
6485 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
6494 i
.op
[dupl
] = i
.op
[dest
];
6495 i
.types
[dupl
] = i
.types
[dest
];
6496 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
6499 if (i
.tm
.opcode_modifier
.immext
)
6502 else if (i
.tm
.operand_types
[0].bitfield
.acc
6503 && i
.tm
.operand_types
[0].bitfield
.xmmword
)
6507 for (j
= 1; j
< i
.operands
; j
++)
6509 i
.op
[j
- 1] = i
.op
[j
];
6510 i
.types
[j
- 1] = i
.types
[j
];
6512 /* We need to adjust fields in i.tm since they are used by
6513 build_modrm_byte. */
6514 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
6521 else if (i
.tm
.opcode_modifier
.implicitquadgroup
)
6523 unsigned int regnum
, first_reg_in_group
, last_reg_in_group
;
6525 /* The second operand must be {x,y,z}mmN, where N is a multiple of 4. */
6526 gas_assert (i
.operands
>= 2 && i
.types
[1].bitfield
.regsimd
);
6527 regnum
= register_number (i
.op
[1].regs
);
6528 first_reg_in_group
= regnum
& ~3;
6529 last_reg_in_group
= first_reg_in_group
+ 3;
6530 if (regnum
!= first_reg_in_group
)
6531 as_warn (_("source register `%s%s' implicitly denotes"
6532 " `%s%.3s%u' to `%s%.3s%u' source group in `%s'"),
6533 register_prefix
, i
.op
[1].regs
->reg_name
,
6534 register_prefix
, i
.op
[1].regs
->reg_name
, first_reg_in_group
,
6535 register_prefix
, i
.op
[1].regs
->reg_name
, last_reg_in_group
,
6538 else if (i
.tm
.opcode_modifier
.regkludge
)
6540 /* The imul $imm, %reg instruction is converted into
6541 imul $imm, %reg, %reg, and the clr %reg instruction
6542 is converted into xor %reg, %reg. */
6544 unsigned int first_reg_op
;
6546 if (operand_type_check (i
.types
[0], reg
))
6550 /* Pretend we saw the extra register operand. */
6551 gas_assert (i
.reg_operands
== 1
6552 && i
.op
[first_reg_op
+ 1].regs
== 0);
6553 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
6554 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
6559 if (i
.tm
.opcode_modifier
.shortform
)
6561 if (i
.types
[0].bitfield
.sreg2
6562 || i
.types
[0].bitfield
.sreg3
)
6564 if (i
.tm
.base_opcode
== POP_SEG_SHORT
6565 && i
.op
[0].regs
->reg_num
== 1)
6567 as_bad (_("you can't `pop %scs'"), register_prefix
);
6570 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
6571 if ((i
.op
[0].regs
->reg_flags
& RegRex
) != 0)
6576 /* The register or float register operand is in operand
6580 if ((i
.types
[0].bitfield
.reg
&& i
.types
[0].bitfield
.tbyte
)
6581 || operand_type_check (i
.types
[0], reg
))
6585 /* Register goes in low 3 bits of opcode. */
6586 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
6587 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
6589 if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
6591 /* Warn about some common errors, but press on regardless.
6592 The first case can be generated by gcc (<= 2.8.1). */
6593 if (i
.operands
== 2)
6595 /* Reversed arguments on faddp, fsubp, etc. */
6596 as_warn (_("translating to `%s %s%s,%s%s'"), i
.tm
.name
,
6597 register_prefix
, i
.op
[!intel_syntax
].regs
->reg_name
,
6598 register_prefix
, i
.op
[intel_syntax
].regs
->reg_name
);
6602 /* Extraneous `l' suffix on fp insn. */
6603 as_warn (_("translating to `%s %s%s'"), i
.tm
.name
,
6604 register_prefix
, i
.op
[0].regs
->reg_name
);
6609 else if (i
.tm
.opcode_modifier
.modrm
)
6611 /* The opcode is completed (modulo i.tm.extension_opcode which
6612 must be put into the modrm byte). Now, we make the modrm and
6613 index base bytes based on all the info we've collected. */
6615 default_seg
= build_modrm_byte ();
6617 else if ((i
.tm
.base_opcode
& ~0x3) == MOV_AX_DISP32
)
6621 else if (i
.tm
.opcode_modifier
.isstring
)
6623 /* For the string instructions that allow a segment override
6624 on one of their operands, the default segment is ds. */
6628 if (i
.tm
.base_opcode
== 0x8d /* lea */
6631 as_warn (_("segment override on `%s' is ineffectual"), i
.tm
.name
);
6633 /* If a segment was explicitly specified, and the specified segment
6634 is not the default, use an opcode prefix to select it. If we
6635 never figured out what the default segment is, then default_seg
6636 will be zero at this point, and the specified segment prefix will
6638 if ((i
.seg
[0]) && (i
.seg
[0] != default_seg
))
6640 if (!add_prefix (i
.seg
[0]->seg_prefix
))
6646 static const seg_entry
*
6647 build_modrm_byte (void)
6649 const seg_entry
*default_seg
= 0;
6650 unsigned int source
, dest
;
6653 vex_3_sources
= i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
;
6656 unsigned int nds
, reg_slot
;
6659 dest
= i
.operands
- 1;
6662 /* There are 2 kinds of instructions:
6663 1. 5 operands: 4 register operands or 3 register operands
6664 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
6665 VexW0 or VexW1. The destination must be either XMM, YMM or
6667 2. 4 operands: 4 register operands or 3 register operands
6668 plus 1 memory operand, with VexXDS. */
6669 gas_assert ((i
.reg_operands
== 4
6670 || (i
.reg_operands
== 3 && i
.mem_operands
== 1))
6671 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
6672 && i
.tm
.opcode_modifier
.vexw
6673 && i
.tm
.operand_types
[dest
].bitfield
.regsimd
);
6675 /* If VexW1 is set, the first non-immediate operand is the source and
6676 the second non-immediate one is encoded in the immediate operand. */
6677 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
6679 source
= i
.imm_operands
;
6680 reg_slot
= i
.imm_operands
+ 1;
6684 source
= i
.imm_operands
+ 1;
6685 reg_slot
= i
.imm_operands
;
6688 if (i
.imm_operands
== 0)
6690 /* When there is no immediate operand, generate an 8bit
6691 immediate operand to encode the first operand. */
6692 exp
= &im_expressions
[i
.imm_operands
++];
6693 i
.op
[i
.operands
].imms
= exp
;
6694 i
.types
[i
.operands
] = imm8
;
6697 gas_assert (i
.tm
.operand_types
[reg_slot
].bitfield
.regsimd
);
6698 exp
->X_op
= O_constant
;
6699 exp
->X_add_number
= register_number (i
.op
[reg_slot
].regs
) << 4;
6700 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
6704 unsigned int imm_slot
;
6706 gas_assert (i
.imm_operands
== 1 && i
.types
[0].bitfield
.vec_imm4
);
6708 if (i
.tm
.opcode_modifier
.immext
)
6710 /* When ImmExt is set, the immediate byte is the last
6712 imm_slot
= i
.operands
- 1;
6720 /* Turn on Imm8 so that output_imm will generate it. */
6721 i
.types
[imm_slot
].bitfield
.imm8
= 1;
6724 gas_assert (i
.tm
.operand_types
[reg_slot
].bitfield
.regsimd
);
6725 i
.op
[imm_slot
].imms
->X_add_number
6726 |= register_number (i
.op
[reg_slot
].regs
) << 4;
6727 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
6730 gas_assert (i
.tm
.operand_types
[nds
].bitfield
.regsimd
);
6731 i
.vex
.register_specifier
= i
.op
[nds
].regs
;
6736 /* i.reg_operands MUST be the number of real register operands;
6737 implicit registers do not count. If there are 3 register
6738 operands, it must be a instruction with VexNDS. For a
6739 instruction with VexNDD, the destination register is encoded
6740 in VEX prefix. If there are 4 register operands, it must be
6741 a instruction with VEX prefix and 3 sources. */
6742 if (i
.mem_operands
== 0
6743 && ((i
.reg_operands
== 2
6744 && i
.tm
.opcode_modifier
.vexvvvv
<= VEXXDS
)
6745 || (i
.reg_operands
== 3
6746 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
6747 || (i
.reg_operands
== 4 && vex_3_sources
)))
6755 /* When there are 3 operands, one of them may be immediate,
6756 which may be the first or the last operand. Otherwise,
6757 the first operand must be shift count register (cl) or it
6758 is an instruction with VexNDS. */
6759 gas_assert (i
.imm_operands
== 1
6760 || (i
.imm_operands
== 0
6761 && (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
6762 || i
.types
[0].bitfield
.shiftcount
)));
6763 if (operand_type_check (i
.types
[0], imm
)
6764 || i
.types
[0].bitfield
.shiftcount
)
6770 /* When there are 4 operands, the first two must be 8bit
6771 immediate operands. The source operand will be the 3rd
6774 For instructions with VexNDS, if the first operand
6775 an imm8, the source operand is the 2nd one. If the last
6776 operand is imm8, the source operand is the first one. */
6777 gas_assert ((i
.imm_operands
== 2
6778 && i
.types
[0].bitfield
.imm8
6779 && i
.types
[1].bitfield
.imm8
)
6780 || (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
6781 && i
.imm_operands
== 1
6782 && (i
.types
[0].bitfield
.imm8
6783 || i
.types
[i
.operands
- 1].bitfield
.imm8
6785 if (i
.imm_operands
== 2)
6789 if (i
.types
[0].bitfield
.imm8
)
6796 if (is_evex_encoding (&i
.tm
))
6798 /* For EVEX instructions, when there are 5 operands, the
6799 first one must be immediate operand. If the second one
6800 is immediate operand, the source operand is the 3th
6801 one. If the last one is immediate operand, the source
6802 operand is the 2nd one. */
6803 gas_assert (i
.imm_operands
== 2
6804 && i
.tm
.opcode_modifier
.sae
6805 && operand_type_check (i
.types
[0], imm
));
6806 if (operand_type_check (i
.types
[1], imm
))
6808 else if (operand_type_check (i
.types
[4], imm
))
6822 /* RC/SAE operand could be between DEST and SRC. That happens
6823 when one operand is GPR and the other one is XMM/YMM/ZMM
6825 if (i
.rounding
&& i
.rounding
->operand
== (int) dest
)
6828 if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
6830 /* For instructions with VexNDS, the register-only source
6831 operand must be a 32/64bit integer, XMM, YMM, ZMM, or mask
6832 register. It is encoded in VEX prefix. We need to
6833 clear RegMem bit before calling operand_type_equal. */
6835 i386_operand_type op
;
6838 /* Check register-only source operand when two source
6839 operands are swapped. */
6840 if (!i
.tm
.operand_types
[source
].bitfield
.baseindex
6841 && i
.tm
.operand_types
[dest
].bitfield
.baseindex
)
6849 op
= i
.tm
.operand_types
[vvvv
];
6850 op
.bitfield
.regmem
= 0;
6851 if ((dest
+ 1) >= i
.operands
6852 || ((!op
.bitfield
.reg
6853 || (!op
.bitfield
.dword
&& !op
.bitfield
.qword
))
6854 && !op
.bitfield
.regsimd
6855 && !operand_type_equal (&op
, ®mask
)))
6857 i
.vex
.register_specifier
= i
.op
[vvvv
].regs
;
6863 /* One of the register operands will be encoded in the i.tm.reg
6864 field, the other in the combined i.tm.mode and i.tm.regmem
6865 fields. If no form of this instruction supports a memory
6866 destination operand, then we assume the source operand may
6867 sometimes be a memory operand and so we need to store the
6868 destination in the i.rm.reg field. */
6869 if (!i
.tm
.operand_types
[dest
].bitfield
.regmem
6870 && operand_type_check (i
.tm
.operand_types
[dest
], anymem
) == 0)
6872 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
6873 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
6874 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
6876 if ((i
.op
[dest
].regs
->reg_flags
& RegVRex
) != 0)
6878 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
6880 if ((i
.op
[source
].regs
->reg_flags
& RegVRex
) != 0)
6885 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
6886 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
6887 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
6889 if ((i
.op
[dest
].regs
->reg_flags
& RegVRex
) != 0)
6891 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
6893 if ((i
.op
[source
].regs
->reg_flags
& RegVRex
) != 0)
6896 if (flag_code
!= CODE_64BIT
&& (i
.rex
& REX_R
))
6898 if (!i
.types
[i
.tm
.operand_types
[0].bitfield
.regmem
].bitfield
.control
)
6901 add_prefix (LOCK_PREFIX_OPCODE
);
6905 { /* If it's not 2 reg operands... */
6910 unsigned int fake_zero_displacement
= 0;
6913 for (op
= 0; op
< i
.operands
; op
++)
6914 if (operand_type_check (i
.types
[op
], anymem
))
6916 gas_assert (op
< i
.operands
);
6918 if (i
.tm
.opcode_modifier
.vecsib
)
6920 if (i
.index_reg
->reg_num
== RegEiz
6921 || i
.index_reg
->reg_num
== RegRiz
)
6924 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6927 i
.sib
.base
= NO_BASE_REGISTER
;
6928 i
.sib
.scale
= i
.log2_scale_factor
;
6929 i
.types
[op
].bitfield
.disp8
= 0;
6930 i
.types
[op
].bitfield
.disp16
= 0;
6931 i
.types
[op
].bitfield
.disp64
= 0;
6932 if (flag_code
!= CODE_64BIT
|| i
.prefix
[ADDR_PREFIX
])
6934 /* Must be 32 bit */
6935 i
.types
[op
].bitfield
.disp32
= 1;
6936 i
.types
[op
].bitfield
.disp32s
= 0;
6940 i
.types
[op
].bitfield
.disp32
= 0;
6941 i
.types
[op
].bitfield
.disp32s
= 1;
6944 i
.sib
.index
= i
.index_reg
->reg_num
;
6945 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
6947 if ((i
.index_reg
->reg_flags
& RegVRex
) != 0)
6953 if (i
.base_reg
== 0)
6956 if (!i
.disp_operands
)
6957 fake_zero_displacement
= 1;
6958 if (i
.index_reg
== 0)
6960 i386_operand_type newdisp
;
6962 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6963 /* Operand is just <disp> */
6964 if (flag_code
== CODE_64BIT
)
6966 /* 64bit mode overwrites the 32bit absolute
6967 addressing by RIP relative addressing and
6968 absolute addressing is encoded by one of the
6969 redundant SIB forms. */
6970 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6971 i
.sib
.base
= NO_BASE_REGISTER
;
6972 i
.sib
.index
= NO_INDEX_REGISTER
;
6973 newdisp
= (!i
.prefix
[ADDR_PREFIX
] ? disp32s
: disp32
);
6975 else if ((flag_code
== CODE_16BIT
)
6976 ^ (i
.prefix
[ADDR_PREFIX
] != 0))
6978 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
6983 i
.rm
.regmem
= NO_BASE_REGISTER
;
6986 i
.types
[op
] = operand_type_and_not (i
.types
[op
], anydisp
);
6987 i
.types
[op
] = operand_type_or (i
.types
[op
], newdisp
);
6989 else if (!i
.tm
.opcode_modifier
.vecsib
)
6991 /* !i.base_reg && i.index_reg */
6992 if (i
.index_reg
->reg_num
== RegEiz
6993 || i
.index_reg
->reg_num
== RegRiz
)
6994 i
.sib
.index
= NO_INDEX_REGISTER
;
6996 i
.sib
.index
= i
.index_reg
->reg_num
;
6997 i
.sib
.base
= NO_BASE_REGISTER
;
6998 i
.sib
.scale
= i
.log2_scale_factor
;
6999 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
7000 i
.types
[op
].bitfield
.disp8
= 0;
7001 i
.types
[op
].bitfield
.disp16
= 0;
7002 i
.types
[op
].bitfield
.disp64
= 0;
7003 if (flag_code
!= CODE_64BIT
|| i
.prefix
[ADDR_PREFIX
])
7005 /* Must be 32 bit */
7006 i
.types
[op
].bitfield
.disp32
= 1;
7007 i
.types
[op
].bitfield
.disp32s
= 0;
7011 i
.types
[op
].bitfield
.disp32
= 0;
7012 i
.types
[op
].bitfield
.disp32s
= 1;
7014 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
7018 /* RIP addressing for 64bit mode. */
7019 else if (i
.base_reg
->reg_num
== RegRip
||
7020 i
.base_reg
->reg_num
== RegEip
)
7022 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
7023 i
.rm
.regmem
= NO_BASE_REGISTER
;
7024 i
.types
[op
].bitfield
.disp8
= 0;
7025 i
.types
[op
].bitfield
.disp16
= 0;
7026 i
.types
[op
].bitfield
.disp32
= 0;
7027 i
.types
[op
].bitfield
.disp32s
= 1;
7028 i
.types
[op
].bitfield
.disp64
= 0;
7029 i
.flags
[op
] |= Operand_PCrel
;
7030 if (! i
.disp_operands
)
7031 fake_zero_displacement
= 1;
7033 else if (i
.base_reg
->reg_type
.bitfield
.word
)
7035 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
7036 switch (i
.base_reg
->reg_num
)
7039 if (i
.index_reg
== 0)
7041 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
7042 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
7046 if (i
.index_reg
== 0)
7049 if (operand_type_check (i
.types
[op
], disp
) == 0)
7051 /* fake (%bp) into 0(%bp) */
7052 i
.types
[op
].bitfield
.disp8
= 1;
7053 fake_zero_displacement
= 1;
7056 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
7057 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
7059 default: /* (%si) -> 4 or (%di) -> 5 */
7060 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
7062 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
7064 else /* i.base_reg and 32/64 bit mode */
7066 if (flag_code
== CODE_64BIT
7067 && operand_type_check (i
.types
[op
], disp
))
7069 i
.types
[op
].bitfield
.disp16
= 0;
7070 i
.types
[op
].bitfield
.disp64
= 0;
7071 if (i
.prefix
[ADDR_PREFIX
] == 0)
7073 i
.types
[op
].bitfield
.disp32
= 0;
7074 i
.types
[op
].bitfield
.disp32s
= 1;
7078 i
.types
[op
].bitfield
.disp32
= 1;
7079 i
.types
[op
].bitfield
.disp32s
= 0;
7083 if (!i
.tm
.opcode_modifier
.vecsib
)
7084 i
.rm
.regmem
= i
.base_reg
->reg_num
;
7085 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
7087 i
.sib
.base
= i
.base_reg
->reg_num
;
7088 /* x86-64 ignores REX prefix bit here to avoid decoder
7090 if (!(i
.base_reg
->reg_flags
& RegRex
)
7091 && (i
.base_reg
->reg_num
== EBP_REG_NUM
7092 || i
.base_reg
->reg_num
== ESP_REG_NUM
))
7094 if (i
.base_reg
->reg_num
== 5 && i
.disp_operands
== 0)
7096 fake_zero_displacement
= 1;
7097 i
.types
[op
].bitfield
.disp8
= 1;
7099 i
.sib
.scale
= i
.log2_scale_factor
;
7100 if (i
.index_reg
== 0)
7102 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
7103 /* <disp>(%esp) becomes two byte modrm with no index
7104 register. We've already stored the code for esp
7105 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
7106 Any base register besides %esp will not use the
7107 extra modrm byte. */
7108 i
.sib
.index
= NO_INDEX_REGISTER
;
7110 else if (!i
.tm
.opcode_modifier
.vecsib
)
7112 if (i
.index_reg
->reg_num
== RegEiz
7113 || i
.index_reg
->reg_num
== RegRiz
)
7114 i
.sib
.index
= NO_INDEX_REGISTER
;
7116 i
.sib
.index
= i
.index_reg
->reg_num
;
7117 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
7118 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
7123 && (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
7124 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
))
7128 if (!fake_zero_displacement
7132 fake_zero_displacement
= 1;
7133 if (i
.disp_encoding
== disp_encoding_8bit
)
7134 i
.types
[op
].bitfield
.disp8
= 1;
7136 i
.types
[op
].bitfield
.disp32
= 1;
7138 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
7142 if (fake_zero_displacement
)
7144 /* Fakes a zero displacement assuming that i.types[op]
7145 holds the correct displacement size. */
7148 gas_assert (i
.op
[op
].disps
== 0);
7149 exp
= &disp_expressions
[i
.disp_operands
++];
7150 i
.op
[op
].disps
= exp
;
7151 exp
->X_op
= O_constant
;
7152 exp
->X_add_number
= 0;
7153 exp
->X_add_symbol
= (symbolS
*) 0;
7154 exp
->X_op_symbol
= (symbolS
*) 0;
7162 if (i
.tm
.opcode_modifier
.vexsources
== XOP2SOURCES
)
7164 if (operand_type_check (i
.types
[0], imm
))
7165 i
.vex
.register_specifier
= NULL
;
7168 /* VEX.vvvv encodes one of the sources when the first
7169 operand is not an immediate. */
7170 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
7171 i
.vex
.register_specifier
= i
.op
[0].regs
;
7173 i
.vex
.register_specifier
= i
.op
[1].regs
;
7176 /* Destination is a XMM register encoded in the ModRM.reg
7178 i
.rm
.reg
= i
.op
[2].regs
->reg_num
;
7179 if ((i
.op
[2].regs
->reg_flags
& RegRex
) != 0)
7182 /* ModRM.rm and VEX.B encodes the other source. */
7183 if (!i
.mem_operands
)
7187 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
7188 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
7190 i
.rm
.regmem
= i
.op
[0].regs
->reg_num
;
7192 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
7196 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXLWP
)
7198 i
.vex
.register_specifier
= i
.op
[2].regs
;
7199 if (!i
.mem_operands
)
7202 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
7203 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
7207 /* Fill in i.rm.reg or i.rm.regmem field with register operand
7208 (if any) based on i.tm.extension_opcode. Again, we must be
7209 careful to make sure that segment/control/debug/test/MMX
7210 registers are coded into the i.rm.reg field. */
7211 else if (i
.reg_operands
)
7214 unsigned int vex_reg
= ~0;
7216 for (op
= 0; op
< i
.operands
; op
++)
7217 if (i
.types
[op
].bitfield
.reg
7218 || i
.types
[op
].bitfield
.regmmx
7219 || i
.types
[op
].bitfield
.regsimd
7220 || i
.types
[op
].bitfield
.regbnd
7221 || i
.types
[op
].bitfield
.regmask
7222 || i
.types
[op
].bitfield
.sreg2
7223 || i
.types
[op
].bitfield
.sreg3
7224 || i
.types
[op
].bitfield
.control
7225 || i
.types
[op
].bitfield
.debug
7226 || i
.types
[op
].bitfield
.test
)
7231 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
7233 /* For instructions with VexNDS, the register-only
7234 source operand is encoded in VEX prefix. */
7235 gas_assert (mem
!= (unsigned int) ~0);
7240 gas_assert (op
< i
.operands
);
7244 /* Check register-only source operand when two source
7245 operands are swapped. */
7246 if (!i
.tm
.operand_types
[op
].bitfield
.baseindex
7247 && i
.tm
.operand_types
[op
+ 1].bitfield
.baseindex
)
7251 gas_assert (mem
== (vex_reg
+ 1)
7252 && op
< i
.operands
);
7257 gas_assert (vex_reg
< i
.operands
);
7261 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXNDD
)
7263 /* For instructions with VexNDD, the register destination
7264 is encoded in VEX prefix. */
7265 if (i
.mem_operands
== 0)
7267 /* There is no memory operand. */
7268 gas_assert ((op
+ 2) == i
.operands
);
7273 /* There are only 2 non-immediate operands. */
7274 gas_assert (op
< i
.imm_operands
+ 2
7275 && i
.operands
== i
.imm_operands
+ 2);
7276 vex_reg
= i
.imm_operands
+ 1;
7280 gas_assert (op
< i
.operands
);
7282 if (vex_reg
!= (unsigned int) ~0)
7284 i386_operand_type
*type
= &i
.tm
.operand_types
[vex_reg
];
7286 if ((!type
->bitfield
.reg
7287 || (!type
->bitfield
.dword
&& !type
->bitfield
.qword
))
7288 && !type
->bitfield
.regsimd
7289 && !operand_type_equal (type
, ®mask
))
7292 i
.vex
.register_specifier
= i
.op
[vex_reg
].regs
;
7295 /* Don't set OP operand twice. */
7298 /* If there is an extension opcode to put here, the
7299 register number must be put into the regmem field. */
7300 if (i
.tm
.extension_opcode
!= None
)
7302 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
7303 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
7305 if ((i
.op
[op
].regs
->reg_flags
& RegVRex
) != 0)
7310 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
7311 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
7313 if ((i
.op
[op
].regs
->reg_flags
& RegVRex
) != 0)
7318 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
7319 must set it to 3 to indicate this is a register operand
7320 in the regmem field. */
7321 if (!i
.mem_operands
)
7325 /* Fill in i.rm.reg field with extension opcode (if any). */
7326 if (i
.tm
.extension_opcode
!= None
)
7327 i
.rm
.reg
= i
.tm
.extension_opcode
;
7333 output_branch (void)
7339 relax_substateT subtype
;
7343 code16
= flag_code
== CODE_16BIT
? CODE16
: 0;
7344 size
= i
.disp_encoding
== disp_encoding_32bit
? BIG
: SMALL
;
7347 if (i
.prefix
[DATA_PREFIX
] != 0)
7353 /* Pentium4 branch hints. */
7354 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
7355 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
7360 if (i
.prefix
[REX_PREFIX
] != 0)
7366 /* BND prefixed jump. */
7367 if (i
.prefix
[BND_PREFIX
] != 0)
7369 FRAG_APPEND_1_CHAR (i
.prefix
[BND_PREFIX
]);
7373 if (i
.prefixes
!= 0 && !intel_syntax
)
7374 as_warn (_("skipping prefixes on this instruction"));
7376 /* It's always a symbol; End frag & setup for relax.
7377 Make sure there is enough room in this frag for the largest
7378 instruction we may generate in md_convert_frag. This is 2
7379 bytes for the opcode and room for the prefix and largest
7381 frag_grow (prefix
+ 2 + 4);
7382 /* Prefix and 1 opcode byte go in fr_fix. */
7383 p
= frag_more (prefix
+ 1);
7384 if (i
.prefix
[DATA_PREFIX
] != 0)
7385 *p
++ = DATA_PREFIX_OPCODE
;
7386 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
7387 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
7388 *p
++ = i
.prefix
[SEG_PREFIX
];
7389 if (i
.prefix
[REX_PREFIX
] != 0)
7390 *p
++ = i
.prefix
[REX_PREFIX
];
7391 *p
= i
.tm
.base_opcode
;
7393 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
7394 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, size
);
7395 else if (cpu_arch_flags
.bitfield
.cpui386
)
7396 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, size
);
7398 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, size
);
7401 sym
= i
.op
[0].disps
->X_add_symbol
;
7402 off
= i
.op
[0].disps
->X_add_number
;
7404 if (i
.op
[0].disps
->X_op
!= O_constant
7405 && i
.op
[0].disps
->X_op
!= O_symbol
)
7407 /* Handle complex expressions. */
7408 sym
= make_expr_symbol (i
.op
[0].disps
);
7412 /* 1 possible extra opcode + 4 byte displacement go in var part.
7413 Pass reloc in fr_var. */
7414 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
7417 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7418 /* Return TRUE iff PLT32 relocation should be used for branching to
7422 need_plt32_p (symbolS
*s
)
7424 /* PLT32 relocation is ELF only. */
7428 /* Since there is no need to prepare for PLT branch on x86-64, we
7429 can generate R_X86_64_PLT32, instead of R_X86_64_PC32, which can
7430 be used as a marker for 32-bit PC-relative branches. */
7434 /* Weak or undefined symbol need PLT32 relocation. */
7435 if (S_IS_WEAK (s
) || !S_IS_DEFINED (s
))
7438 /* Non-global symbol doesn't need PLT32 relocation. */
7439 if (! S_IS_EXTERNAL (s
))
7442 /* Other global symbols need PLT32 relocation. NB: Symbol with
7443 non-default visibilities are treated as normal global symbol
7444 so that PLT32 relocation can be used as a marker for 32-bit
7445 PC-relative branches. It is useful for linker relaxation. */
7456 bfd_reloc_code_real_type jump_reloc
= i
.reloc
[0];
7458 if (i
.tm
.opcode_modifier
.jumpbyte
)
7460 /* This is a loop or jecxz type instruction. */
7462 if (i
.prefix
[ADDR_PREFIX
] != 0)
7464 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
7467 /* Pentium4 branch hints. */
7468 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
7469 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
7471 FRAG_APPEND_1_CHAR (i
.prefix
[SEG_PREFIX
]);
7480 if (flag_code
== CODE_16BIT
)
7483 if (i
.prefix
[DATA_PREFIX
] != 0)
7485 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
7495 if (i
.prefix
[REX_PREFIX
] != 0)
7497 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
7501 /* BND prefixed jump. */
7502 if (i
.prefix
[BND_PREFIX
] != 0)
7504 FRAG_APPEND_1_CHAR (i
.prefix
[BND_PREFIX
]);
7508 if (i
.prefixes
!= 0 && !intel_syntax
)
7509 as_warn (_("skipping prefixes on this instruction"));
7511 p
= frag_more (i
.tm
.opcode_length
+ size
);
7512 switch (i
.tm
.opcode_length
)
7515 *p
++ = i
.tm
.base_opcode
>> 8;
7518 *p
++ = i
.tm
.base_opcode
;
7524 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7526 && jump_reloc
== NO_RELOC
7527 && need_plt32_p (i
.op
[0].disps
->X_add_symbol
))
7528 jump_reloc
= BFD_RELOC_X86_64_PLT32
;
7531 jump_reloc
= reloc (size
, 1, 1, jump_reloc
);
7533 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
7534 i
.op
[0].disps
, 1, jump_reloc
);
7536 /* All jumps handled here are signed, but don't use a signed limit
7537 check for 32 and 16 bit jumps as we want to allow wrap around at
7538 4G and 64k respectively. */
7540 fixP
->fx_signed
= 1;
7544 output_interseg_jump (void)
7552 if (flag_code
== CODE_16BIT
)
7556 if (i
.prefix
[DATA_PREFIX
] != 0)
7562 if (i
.prefix
[REX_PREFIX
] != 0)
7572 if (i
.prefixes
!= 0 && !intel_syntax
)
7573 as_warn (_("skipping prefixes on this instruction"));
7575 /* 1 opcode; 2 segment; offset */
7576 p
= frag_more (prefix
+ 1 + 2 + size
);
7578 if (i
.prefix
[DATA_PREFIX
] != 0)
7579 *p
++ = DATA_PREFIX_OPCODE
;
7581 if (i
.prefix
[REX_PREFIX
] != 0)
7582 *p
++ = i
.prefix
[REX_PREFIX
];
7584 *p
++ = i
.tm
.base_opcode
;
7585 if (i
.op
[1].imms
->X_op
== O_constant
)
7587 offsetT n
= i
.op
[1].imms
->X_add_number
;
7590 && !fits_in_unsigned_word (n
)
7591 && !fits_in_signed_word (n
))
7593 as_bad (_("16-bit jump out of range"));
7596 md_number_to_chars (p
, n
, size
);
7599 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
7600 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
7601 if (i
.op
[0].imms
->X_op
!= O_constant
)
7602 as_bad (_("can't handle non absolute segment in `%s'"),
7604 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
7610 fragS
*insn_start_frag
;
7611 offsetT insn_start_off
;
7613 /* Tie dwarf2 debug info to the address at the start of the insn.
7614 We can't do this after the insn has been output as the current
7615 frag may have been closed off. eg. by frag_var. */
7616 dwarf2_emit_insn (0);
7618 insn_start_frag
= frag_now
;
7619 insn_start_off
= frag_now_fix ();
7622 if (i
.tm
.opcode_modifier
.jump
)
7624 else if (i
.tm
.opcode_modifier
.jumpbyte
7625 || i
.tm
.opcode_modifier
.jumpdword
)
7627 else if (i
.tm
.opcode_modifier
.jumpintersegment
)
7628 output_interseg_jump ();
7631 /* Output normal instructions here. */
7635 unsigned int prefix
;
7638 && i
.tm
.base_opcode
== 0xfae
7640 && i
.imm_operands
== 1
7641 && (i
.op
[0].imms
->X_add_number
== 0xe8
7642 || i
.op
[0].imms
->X_add_number
== 0xf0
7643 || i
.op
[0].imms
->X_add_number
== 0xf8))
7645 /* Encode lfence, mfence, and sfence as
7646 f0 83 04 24 00 lock addl $0x0, (%{re}sp). */
7647 offsetT val
= 0x240483f0ULL
;
7649 md_number_to_chars (p
, val
, 5);
7653 /* Some processors fail on LOCK prefix. This options makes
7654 assembler ignore LOCK prefix and serves as a workaround. */
7655 if (omit_lock_prefix
)
7657 if (i
.tm
.base_opcode
== LOCK_PREFIX_OPCODE
)
7659 i
.prefix
[LOCK_PREFIX
] = 0;
7662 /* Since the VEX/EVEX prefix contains the implicit prefix, we
7663 don't need the explicit prefix. */
7664 if (!i
.tm
.opcode_modifier
.vex
&& !i
.tm
.opcode_modifier
.evex
)
7666 switch (i
.tm
.opcode_length
)
7669 if (i
.tm
.base_opcode
& 0xff000000)
7671 prefix
= (i
.tm
.base_opcode
>> 24) & 0xff;
7676 if ((i
.tm
.base_opcode
& 0xff0000) != 0)
7678 prefix
= (i
.tm
.base_opcode
>> 16) & 0xff;
7679 if (i
.tm
.cpu_flags
.bitfield
.cpupadlock
)
7682 if (prefix
!= REPE_PREFIX_OPCODE
7683 || (i
.prefix
[REP_PREFIX
]
7684 != REPE_PREFIX_OPCODE
))
7685 add_prefix (prefix
);
7688 add_prefix (prefix
);
7694 /* Check for pseudo prefixes. */
7695 as_bad_where (insn_start_frag
->fr_file
,
7696 insn_start_frag
->fr_line
,
7697 _("pseudo prefix without instruction"));
7703 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
7704 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
7705 R_X86_64_GOTTPOFF relocation so that linker can safely
7706 perform IE->LE optimization. */
7707 if (x86_elf_abi
== X86_64_X32_ABI
7709 && i
.reloc
[0] == BFD_RELOC_X86_64_GOTTPOFF
7710 && i
.prefix
[REX_PREFIX
] == 0)
7711 add_prefix (REX_OPCODE
);
7714 /* The prefix bytes. */
7715 for (j
= ARRAY_SIZE (i
.prefix
), q
= i
.prefix
; j
> 0; j
--, q
++)
7717 FRAG_APPEND_1_CHAR (*q
);
7721 for (j
= 0, q
= i
.prefix
; j
< ARRAY_SIZE (i
.prefix
); j
++, q
++)
7726 /* REX byte is encoded in VEX prefix. */
7730 FRAG_APPEND_1_CHAR (*q
);
7733 /* There should be no other prefixes for instructions
7738 /* For EVEX instructions i.vrex should become 0 after
7739 build_evex_prefix. For VEX instructions upper 16 registers
7740 aren't available, so VREX should be 0. */
7743 /* Now the VEX prefix. */
7744 p
= frag_more (i
.vex
.length
);
7745 for (j
= 0; j
< i
.vex
.length
; j
++)
7746 p
[j
] = i
.vex
.bytes
[j
];
7749 /* Now the opcode; be careful about word order here! */
7750 if (i
.tm
.opcode_length
== 1)
7752 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
7756 switch (i
.tm
.opcode_length
)
7760 *p
++ = (i
.tm
.base_opcode
>> 24) & 0xff;
7761 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
7765 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
7775 /* Put out high byte first: can't use md_number_to_chars! */
7776 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
7777 *p
= i
.tm
.base_opcode
& 0xff;
7780 /* Now the modrm byte and sib byte (if present). */
7781 if (i
.tm
.opcode_modifier
.modrm
)
7783 FRAG_APPEND_1_CHAR ((i
.rm
.regmem
<< 0
7786 /* If i.rm.regmem == ESP (4)
7787 && i.rm.mode != (Register mode)
7789 ==> need second modrm byte. */
7790 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
7792 && !(i
.base_reg
&& i
.base_reg
->reg_type
.bitfield
.word
))
7793 FRAG_APPEND_1_CHAR ((i
.sib
.base
<< 0
7795 | i
.sib
.scale
<< 6));
7798 if (i
.disp_operands
)
7799 output_disp (insn_start_frag
, insn_start_off
);
7802 output_imm (insn_start_frag
, insn_start_off
);
7808 pi ("" /*line*/, &i
);
7810 #endif /* DEBUG386 */
7813 /* Return the size of the displacement operand N. */
7816 disp_size (unsigned int n
)
7820 if (i
.types
[n
].bitfield
.disp64
)
7822 else if (i
.types
[n
].bitfield
.disp8
)
7824 else if (i
.types
[n
].bitfield
.disp16
)
7829 /* Return the size of the immediate operand N. */
7832 imm_size (unsigned int n
)
7835 if (i
.types
[n
].bitfield
.imm64
)
7837 else if (i
.types
[n
].bitfield
.imm8
|| i
.types
[n
].bitfield
.imm8s
)
7839 else if (i
.types
[n
].bitfield
.imm16
)
7845 output_disp (fragS
*insn_start_frag
, offsetT insn_start_off
)
7850 for (n
= 0; n
< i
.operands
; n
++)
7852 if (operand_type_check (i
.types
[n
], disp
))
7854 if (i
.op
[n
].disps
->X_op
== O_constant
)
7856 int size
= disp_size (n
);
7857 offsetT val
= i
.op
[n
].disps
->X_add_number
;
7859 val
= offset_in_range (val
>> i
.memshift
, size
);
7860 p
= frag_more (size
);
7861 md_number_to_chars (p
, val
, size
);
7865 enum bfd_reloc_code_real reloc_type
;
7866 int size
= disp_size (n
);
7867 int sign
= i
.types
[n
].bitfield
.disp32s
;
7868 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
7871 /* We can't have 8 bit displacement here. */
7872 gas_assert (!i
.types
[n
].bitfield
.disp8
);
7874 /* The PC relative address is computed relative
7875 to the instruction boundary, so in case immediate
7876 fields follows, we need to adjust the value. */
7877 if (pcrel
&& i
.imm_operands
)
7882 for (n1
= 0; n1
< i
.operands
; n1
++)
7883 if (operand_type_check (i
.types
[n1
], imm
))
7885 /* Only one immediate is allowed for PC
7886 relative address. */
7887 gas_assert (sz
== 0);
7889 i
.op
[n
].disps
->X_add_number
-= sz
;
7891 /* We should find the immediate. */
7892 gas_assert (sz
!= 0);
7895 p
= frag_more (size
);
7896 reloc_type
= reloc (size
, pcrel
, sign
, i
.reloc
[n
]);
7898 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
7899 && (((reloc_type
== BFD_RELOC_32
7900 || reloc_type
== BFD_RELOC_X86_64_32S
7901 || (reloc_type
== BFD_RELOC_64
7903 && (i
.op
[n
].disps
->X_op
== O_symbol
7904 || (i
.op
[n
].disps
->X_op
== O_add
7905 && ((symbol_get_value_expression
7906 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
7908 || reloc_type
== BFD_RELOC_32_PCREL
))
7912 if (insn_start_frag
== frag_now
)
7913 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
7918 add
= insn_start_frag
->fr_fix
- insn_start_off
;
7919 for (fr
= insn_start_frag
->fr_next
;
7920 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
7922 add
+= p
- frag_now
->fr_literal
;
7927 reloc_type
= BFD_RELOC_386_GOTPC
;
7928 i
.op
[n
].imms
->X_add_number
+= add
;
7930 else if (reloc_type
== BFD_RELOC_64
)
7931 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
7933 /* Don't do the adjustment for x86-64, as there
7934 the pcrel addressing is relative to the _next_
7935 insn, and that is taken care of in other code. */
7936 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
7938 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
7939 size
, i
.op
[n
].disps
, pcrel
,
7941 /* Check for "call/jmp *mem", "mov mem, %reg",
7942 "test %reg, mem" and "binop mem, %reg" where binop
7943 is one of adc, add, and, cmp, or, sbb, sub, xor
7944 instructions. Always generate R_386_GOT32X for
7945 "sym*GOT" operand in 32-bit mode. */
7946 if ((generate_relax_relocations
7949 && i
.rm
.regmem
== 5))
7951 || (i
.rm
.mode
== 0 && i
.rm
.regmem
== 5))
7952 && ((i
.operands
== 1
7953 && i
.tm
.base_opcode
== 0xff
7954 && (i
.rm
.reg
== 2 || i
.rm
.reg
== 4))
7956 && (i
.tm
.base_opcode
== 0x8b
7957 || i
.tm
.base_opcode
== 0x85
7958 || (i
.tm
.base_opcode
& 0xc7) == 0x03))))
7962 fixP
->fx_tcbit
= i
.rex
!= 0;
7964 && (i
.base_reg
->reg_num
== RegRip
7965 || i
.base_reg
->reg_num
== RegEip
))
7966 fixP
->fx_tcbit2
= 1;
7969 fixP
->fx_tcbit2
= 1;
7977 output_imm (fragS
*insn_start_frag
, offsetT insn_start_off
)
7982 for (n
= 0; n
< i
.operands
; n
++)
7984 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
7985 if (i
.rounding
&& (int) n
== i
.rounding
->operand
)
7988 if (operand_type_check (i
.types
[n
], imm
))
7990 if (i
.op
[n
].imms
->X_op
== O_constant
)
7992 int size
= imm_size (n
);
7995 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
7997 p
= frag_more (size
);
7998 md_number_to_chars (p
, val
, size
);
8002 /* Not absolute_section.
8003 Need a 32-bit fixup (don't support 8bit
8004 non-absolute imms). Try to support other
8006 enum bfd_reloc_code_real reloc_type
;
8007 int size
= imm_size (n
);
8010 if (i
.types
[n
].bitfield
.imm32s
8011 && (i
.suffix
== QWORD_MNEM_SUFFIX
8012 || (!i
.suffix
&& i
.tm
.opcode_modifier
.no_lsuf
)))
8017 p
= frag_more (size
);
8018 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
8020 /* This is tough to explain. We end up with this one if we
8021 * have operands that look like
8022 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
8023 * obtain the absolute address of the GOT, and it is strongly
8024 * preferable from a performance point of view to avoid using
8025 * a runtime relocation for this. The actual sequence of
8026 * instructions often look something like:
8031 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
8033 * The call and pop essentially return the absolute address
8034 * of the label .L66 and store it in %ebx. The linker itself
8035 * will ultimately change the first operand of the addl so
8036 * that %ebx points to the GOT, but to keep things simple, the
8037 * .o file must have this operand set so that it generates not
8038 * the absolute address of .L66, but the absolute address of
8039 * itself. This allows the linker itself simply treat a GOTPC
8040 * relocation as asking for a pcrel offset to the GOT to be
8041 * added in, and the addend of the relocation is stored in the
8042 * operand field for the instruction itself.
8044 * Our job here is to fix the operand so that it would add
8045 * the correct offset so that %ebx would point to itself. The
8046 * thing that is tricky is that .-.L66 will point to the
8047 * beginning of the instruction, so we need to further modify
8048 * the operand so that it will point to itself. There are
8049 * other cases where you have something like:
8051 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
8053 * and here no correction would be required. Internally in
8054 * the assembler we treat operands of this form as not being
8055 * pcrel since the '.' is explicitly mentioned, and I wonder
8056 * whether it would simplify matters to do it this way. Who
8057 * knows. In earlier versions of the PIC patches, the
8058 * pcrel_adjust field was used to store the correction, but
8059 * since the expression is not pcrel, I felt it would be
8060 * confusing to do it this way. */
8062 if ((reloc_type
== BFD_RELOC_32
8063 || reloc_type
== BFD_RELOC_X86_64_32S
8064 || reloc_type
== BFD_RELOC_64
)
8066 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
8067 && (i
.op
[n
].imms
->X_op
== O_symbol
8068 || (i
.op
[n
].imms
->X_op
== O_add
8069 && ((symbol_get_value_expression
8070 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
8075 if (insn_start_frag
== frag_now
)
8076 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
8081 add
= insn_start_frag
->fr_fix
- insn_start_off
;
8082 for (fr
= insn_start_frag
->fr_next
;
8083 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
8085 add
+= p
- frag_now
->fr_literal
;
8089 reloc_type
= BFD_RELOC_386_GOTPC
;
8091 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
8093 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
8094 i
.op
[n
].imms
->X_add_number
+= add
;
8096 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
8097 i
.op
[n
].imms
, 0, reloc_type
);
8103 /* x86_cons_fix_new is called via the expression parsing code when a
8104 reloc is needed. We use this hook to get the correct .got reloc. */
8105 static int cons_sign
= -1;
8108 x86_cons_fix_new (fragS
*frag
, unsigned int off
, unsigned int len
,
8109 expressionS
*exp
, bfd_reloc_code_real_type r
)
8111 r
= reloc (len
, 0, cons_sign
, r
);
8114 if (exp
->X_op
== O_secrel
)
8116 exp
->X_op
= O_symbol
;
8117 r
= BFD_RELOC_32_SECREL
;
8121 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
8124 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
8125 purpose of the `.dc.a' internal pseudo-op. */
8128 x86_address_bytes (void)
8130 if ((stdoutput
->arch_info
->mach
& bfd_mach_x64_32
))
8132 return stdoutput
->arch_info
->bits_per_address
/ 8;
8135 #if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
8137 # define lex_got(reloc, adjust, types) NULL
8139 /* Parse operands of the form
8140 <symbol>@GOTOFF+<nnn>
8141 and similar .plt or .got references.
8143 If we find one, set up the correct relocation in RELOC and copy the
8144 input string, minus the `@GOTOFF' into a malloc'd buffer for
8145 parsing by the calling routine. Return this buffer, and if ADJUST
8146 is non-null set it to the length of the string we removed from the
8147 input line. Otherwise return NULL. */
8149 lex_got (enum bfd_reloc_code_real
*rel
,
8151 i386_operand_type
*types
)
8153 /* Some of the relocations depend on the size of what field is to
8154 be relocated. But in our callers i386_immediate and i386_displacement
8155 we don't yet know the operand size (this will be set by insn
8156 matching). Hence we record the word32 relocation here,
8157 and adjust the reloc according to the real size in reloc(). */
8158 static const struct {
8161 const enum bfd_reloc_code_real rel
[2];
8162 const i386_operand_type types64
;
8164 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8165 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32
,
8167 OPERAND_TYPE_IMM32_64
},
8169 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real
,
8170 BFD_RELOC_X86_64_PLTOFF64
},
8171 OPERAND_TYPE_IMM64
},
8172 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32
,
8173 BFD_RELOC_X86_64_PLT32
},
8174 OPERAND_TYPE_IMM32_32S_DISP32
},
8175 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real
,
8176 BFD_RELOC_X86_64_GOTPLT64
},
8177 OPERAND_TYPE_IMM64_DISP64
},
8178 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF
,
8179 BFD_RELOC_X86_64_GOTOFF64
},
8180 OPERAND_TYPE_IMM64_DISP64
},
8181 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real
,
8182 BFD_RELOC_X86_64_GOTPCREL
},
8183 OPERAND_TYPE_IMM32_32S_DISP32
},
8184 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD
,
8185 BFD_RELOC_X86_64_TLSGD
},
8186 OPERAND_TYPE_IMM32_32S_DISP32
},
8187 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM
,
8188 _dummy_first_bfd_reloc_code_real
},
8189 OPERAND_TYPE_NONE
},
8190 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real
,
8191 BFD_RELOC_X86_64_TLSLD
},
8192 OPERAND_TYPE_IMM32_32S_DISP32
},
8193 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32
,
8194 BFD_RELOC_X86_64_GOTTPOFF
},
8195 OPERAND_TYPE_IMM32_32S_DISP32
},
8196 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32
,
8197 BFD_RELOC_X86_64_TPOFF32
},
8198 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
8199 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE
,
8200 _dummy_first_bfd_reloc_code_real
},
8201 OPERAND_TYPE_NONE
},
8202 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32
,
8203 BFD_RELOC_X86_64_DTPOFF32
},
8204 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
8205 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE
,
8206 _dummy_first_bfd_reloc_code_real
},
8207 OPERAND_TYPE_NONE
},
8208 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE
,
8209 _dummy_first_bfd_reloc_code_real
},
8210 OPERAND_TYPE_NONE
},
8211 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32
,
8212 BFD_RELOC_X86_64_GOT32
},
8213 OPERAND_TYPE_IMM32_32S_64_DISP32
},
8214 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC
,
8215 BFD_RELOC_X86_64_GOTPC32_TLSDESC
},
8216 OPERAND_TYPE_IMM32_32S_DISP32
},
8217 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL
,
8218 BFD_RELOC_X86_64_TLSDESC_CALL
},
8219 OPERAND_TYPE_IMM32_32S_DISP32
},
8224 #if defined (OBJ_MAYBE_ELF)
8229 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
8230 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
8233 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
8235 int len
= gotrel
[j
].len
;
8236 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
8238 if (gotrel
[j
].rel
[object_64bit
] != 0)
8241 char *tmpbuf
, *past_reloc
;
8243 *rel
= gotrel
[j
].rel
[object_64bit
];
8247 if (flag_code
!= CODE_64BIT
)
8249 types
->bitfield
.imm32
= 1;
8250 types
->bitfield
.disp32
= 1;
8253 *types
= gotrel
[j
].types64
;
8256 if (j
!= 0 && GOT_symbol
== NULL
)
8257 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
8259 /* The length of the first part of our input line. */
8260 first
= cp
- input_line_pointer
;
8262 /* The second part goes from after the reloc token until
8263 (and including) an end_of_line char or comma. */
8264 past_reloc
= cp
+ 1 + len
;
8266 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
8268 second
= cp
+ 1 - past_reloc
;
8270 /* Allocate and copy string. The trailing NUL shouldn't
8271 be necessary, but be safe. */
8272 tmpbuf
= XNEWVEC (char, first
+ second
+ 2);
8273 memcpy (tmpbuf
, input_line_pointer
, first
);
8274 if (second
!= 0 && *past_reloc
!= ' ')
8275 /* Replace the relocation token with ' ', so that
8276 errors like foo@GOTOFF1 will be detected. */
8277 tmpbuf
[first
++] = ' ';
8279 /* Increment length by 1 if the relocation token is
8284 memcpy (tmpbuf
+ first
, past_reloc
, second
);
8285 tmpbuf
[first
+ second
] = '\0';
8289 as_bad (_("@%s reloc is not supported with %d-bit output format"),
8290 gotrel
[j
].str
, 1 << (5 + object_64bit
));
8295 /* Might be a symbol version string. Don't as_bad here. */
8304 /* Parse operands of the form
8305 <symbol>@SECREL32+<nnn>
8307 If we find one, set up the correct relocation in RELOC and copy the
8308 input string, minus the `@SECREL32' into a malloc'd buffer for
8309 parsing by the calling routine. Return this buffer, and if ADJUST
8310 is non-null set it to the length of the string we removed from the
8311 input line. Otherwise return NULL.
8313 This function is copied from the ELF version above adjusted for PE targets. */
8316 lex_got (enum bfd_reloc_code_real
*rel ATTRIBUTE_UNUSED
,
8317 int *adjust ATTRIBUTE_UNUSED
,
8318 i386_operand_type
*types
)
8324 const enum bfd_reloc_code_real rel
[2];
8325 const i386_operand_type types64
;
8329 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL
,
8330 BFD_RELOC_32_SECREL
},
8331 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
8337 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
8338 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
8341 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
8343 int len
= gotrel
[j
].len
;
8345 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
8347 if (gotrel
[j
].rel
[object_64bit
] != 0)
8350 char *tmpbuf
, *past_reloc
;
8352 *rel
= gotrel
[j
].rel
[object_64bit
];
8358 if (flag_code
!= CODE_64BIT
)
8360 types
->bitfield
.imm32
= 1;
8361 types
->bitfield
.disp32
= 1;
8364 *types
= gotrel
[j
].types64
;
8367 /* The length of the first part of our input line. */
8368 first
= cp
- input_line_pointer
;
8370 /* The second part goes from after the reloc token until
8371 (and including) an end_of_line char or comma. */
8372 past_reloc
= cp
+ 1 + len
;
8374 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
8376 second
= cp
+ 1 - past_reloc
;
8378 /* Allocate and copy string. The trailing NUL shouldn't
8379 be necessary, but be safe. */
8380 tmpbuf
= XNEWVEC (char, first
+ second
+ 2);
8381 memcpy (tmpbuf
, input_line_pointer
, first
);
8382 if (second
!= 0 && *past_reloc
!= ' ')
8383 /* Replace the relocation token with ' ', so that
8384 errors like foo@SECLREL321 will be detected. */
8385 tmpbuf
[first
++] = ' ';
8386 memcpy (tmpbuf
+ first
, past_reloc
, second
);
8387 tmpbuf
[first
+ second
] = '\0';
8391 as_bad (_("@%s reloc is not supported with %d-bit output format"),
8392 gotrel
[j
].str
, 1 << (5 + object_64bit
));
8397 /* Might be a symbol version string. Don't as_bad here. */
8403 bfd_reloc_code_real_type
8404 x86_cons (expressionS
*exp
, int size
)
8406 bfd_reloc_code_real_type got_reloc
= NO_RELOC
;
8408 intel_syntax
= -intel_syntax
;
8411 if (size
== 4 || (object_64bit
&& size
== 8))
8413 /* Handle @GOTOFF and the like in an expression. */
8415 char *gotfree_input_line
;
8418 save
= input_line_pointer
;
8419 gotfree_input_line
= lex_got (&got_reloc
, &adjust
, NULL
);
8420 if (gotfree_input_line
)
8421 input_line_pointer
= gotfree_input_line
;
8425 if (gotfree_input_line
)
8427 /* expression () has merrily parsed up to the end of line,
8428 or a comma - in the wrong buffer. Transfer how far
8429 input_line_pointer has moved to the right buffer. */
8430 input_line_pointer
= (save
8431 + (input_line_pointer
- gotfree_input_line
)
8433 free (gotfree_input_line
);
8434 if (exp
->X_op
== O_constant
8435 || exp
->X_op
== O_absent
8436 || exp
->X_op
== O_illegal
8437 || exp
->X_op
== O_register
8438 || exp
->X_op
== O_big
)
8440 char c
= *input_line_pointer
;
8441 *input_line_pointer
= 0;
8442 as_bad (_("missing or invalid expression `%s'"), save
);
8443 *input_line_pointer
= c
;
8450 intel_syntax
= -intel_syntax
;
8453 i386_intel_simplify (exp
);
8459 signed_cons (int size
)
8461 if (flag_code
== CODE_64BIT
)
8469 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
8476 if (exp
.X_op
== O_symbol
)
8477 exp
.X_op
= O_secrel
;
8479 emit_expr (&exp
, 4);
8481 while (*input_line_pointer
++ == ',');
8483 input_line_pointer
--;
8484 demand_empty_rest_of_line ();
8488 /* Handle Vector operations. */
8491 check_VecOperations (char *op_string
, char *op_end
)
8493 const reg_entry
*mask
;
8498 && (op_end
== NULL
|| op_string
< op_end
))
8501 if (*op_string
== '{')
8505 /* Check broadcasts. */
8506 if (strncmp (op_string
, "1to", 3) == 0)
8511 goto duplicated_vec_op
;
8514 if (*op_string
== '8')
8516 else if (*op_string
== '4')
8518 else if (*op_string
== '2')
8520 else if (*op_string
== '1'
8521 && *(op_string
+1) == '6')
8528 as_bad (_("Unsupported broadcast: `%s'"), saved
);
8533 broadcast_op
.type
= bcst_type
;
8534 broadcast_op
.operand
= this_operand
;
8535 i
.broadcast
= &broadcast_op
;
8537 /* Check masking operation. */
8538 else if ((mask
= parse_register (op_string
, &end_op
)) != NULL
)
8540 /* k0 can't be used for write mask. */
8541 if (!mask
->reg_type
.bitfield
.regmask
|| mask
->reg_num
== 0)
8543 as_bad (_("`%s%s' can't be used for write mask"),
8544 register_prefix
, mask
->reg_name
);
8550 mask_op
.mask
= mask
;
8551 mask_op
.zeroing
= 0;
8552 mask_op
.operand
= this_operand
;
8558 goto duplicated_vec_op
;
8560 i
.mask
->mask
= mask
;
8562 /* Only "{z}" is allowed here. No need to check
8563 zeroing mask explicitly. */
8564 if (i
.mask
->operand
!= this_operand
)
8566 as_bad (_("invalid write mask `%s'"), saved
);
8573 /* Check zeroing-flag for masking operation. */
8574 else if (*op_string
== 'z')
8578 mask_op
.mask
= NULL
;
8579 mask_op
.zeroing
= 1;
8580 mask_op
.operand
= this_operand
;
8585 if (i
.mask
->zeroing
)
8588 as_bad (_("duplicated `%s'"), saved
);
8592 i
.mask
->zeroing
= 1;
8594 /* Only "{%k}" is allowed here. No need to check mask
8595 register explicitly. */
8596 if (i
.mask
->operand
!= this_operand
)
8598 as_bad (_("invalid zeroing-masking `%s'"),
8607 goto unknown_vec_op
;
8609 if (*op_string
!= '}')
8611 as_bad (_("missing `}' in `%s'"), saved
);
8616 /* Strip whitespace since the addition of pseudo prefixes
8617 changed how the scrubber treats '{'. */
8618 if (is_space_char (*op_string
))
8624 /* We don't know this one. */
8625 as_bad (_("unknown vector operation: `%s'"), saved
);
8629 if (i
.mask
&& i
.mask
->zeroing
&& !i
.mask
->mask
)
8631 as_bad (_("zeroing-masking only allowed with write mask"));
8639 i386_immediate (char *imm_start
)
8641 char *save_input_line_pointer
;
8642 char *gotfree_input_line
;
8645 i386_operand_type types
;
8647 operand_type_set (&types
, ~0);
8649 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
8651 as_bad (_("at most %d immediate operands are allowed"),
8652 MAX_IMMEDIATE_OPERANDS
);
8656 exp
= &im_expressions
[i
.imm_operands
++];
8657 i
.op
[this_operand
].imms
= exp
;
8659 if (is_space_char (*imm_start
))
8662 save_input_line_pointer
= input_line_pointer
;
8663 input_line_pointer
= imm_start
;
8665 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
8666 if (gotfree_input_line
)
8667 input_line_pointer
= gotfree_input_line
;
8669 exp_seg
= expression (exp
);
8673 /* Handle vector operations. */
8674 if (*input_line_pointer
== '{')
8676 input_line_pointer
= check_VecOperations (input_line_pointer
,
8678 if (input_line_pointer
== NULL
)
8682 if (*input_line_pointer
)
8683 as_bad (_("junk `%s' after expression"), input_line_pointer
);
8685 input_line_pointer
= save_input_line_pointer
;
8686 if (gotfree_input_line
)
8688 free (gotfree_input_line
);
8690 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
8691 exp
->X_op
= O_illegal
;
8694 return i386_finalize_immediate (exp_seg
, exp
, types
, imm_start
);
8698 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
8699 i386_operand_type types
, const char *imm_start
)
8701 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_illegal
|| exp
->X_op
== O_big
)
8704 as_bad (_("missing or invalid immediate expression `%s'"),
8708 else if (exp
->X_op
== O_constant
)
8710 /* Size it properly later. */
8711 i
.types
[this_operand
].bitfield
.imm64
= 1;
8712 /* If not 64bit, sign extend val. */
8713 if (flag_code
!= CODE_64BIT
8714 && (exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
8716 = (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
8718 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8719 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
8720 && exp_seg
!= absolute_section
8721 && exp_seg
!= text_section
8722 && exp_seg
!= data_section
8723 && exp_seg
!= bss_section
8724 && exp_seg
!= undefined_section
8725 && !bfd_is_com_section (exp_seg
))
8727 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
8731 else if (!intel_syntax
&& exp_seg
== reg_section
)
8734 as_bad (_("illegal immediate register operand %s"), imm_start
);
8739 /* This is an address. The size of the address will be
8740 determined later, depending on destination register,
8741 suffix, or the default for the section. */
8742 i
.types
[this_operand
].bitfield
.imm8
= 1;
8743 i
.types
[this_operand
].bitfield
.imm16
= 1;
8744 i
.types
[this_operand
].bitfield
.imm32
= 1;
8745 i
.types
[this_operand
].bitfield
.imm32s
= 1;
8746 i
.types
[this_operand
].bitfield
.imm64
= 1;
8747 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
8755 i386_scale (char *scale
)
8758 char *save
= input_line_pointer
;
8760 input_line_pointer
= scale
;
8761 val
= get_absolute_expression ();
8766 i
.log2_scale_factor
= 0;
8769 i
.log2_scale_factor
= 1;
8772 i
.log2_scale_factor
= 2;
8775 i
.log2_scale_factor
= 3;
8779 char sep
= *input_line_pointer
;
8781 *input_line_pointer
= '\0';
8782 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
8784 *input_line_pointer
= sep
;
8785 input_line_pointer
= save
;
8789 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
8791 as_warn (_("scale factor of %d without an index register"),
8792 1 << i
.log2_scale_factor
);
8793 i
.log2_scale_factor
= 0;
8795 scale
= input_line_pointer
;
8796 input_line_pointer
= save
;
8801 i386_displacement (char *disp_start
, char *disp_end
)
8805 char *save_input_line_pointer
;
8806 char *gotfree_input_line
;
8808 i386_operand_type bigdisp
, types
= anydisp
;
8811 if (i
.disp_operands
== MAX_MEMORY_OPERANDS
)
8813 as_bad (_("at most %d displacement operands are allowed"),
8814 MAX_MEMORY_OPERANDS
);
8818 operand_type_set (&bigdisp
, 0);
8819 if ((i
.types
[this_operand
].bitfield
.jumpabsolute
)
8820 || (!current_templates
->start
->opcode_modifier
.jump
8821 && !current_templates
->start
->opcode_modifier
.jumpdword
))
8823 bigdisp
.bitfield
.disp32
= 1;
8824 override
= (i
.prefix
[ADDR_PREFIX
] != 0);
8825 if (flag_code
== CODE_64BIT
)
8829 bigdisp
.bitfield
.disp32s
= 1;
8830 bigdisp
.bitfield
.disp64
= 1;
8833 else if ((flag_code
== CODE_16BIT
) ^ override
)
8835 bigdisp
.bitfield
.disp32
= 0;
8836 bigdisp
.bitfield
.disp16
= 1;
8841 /* For PC-relative branches, the width of the displacement
8842 is dependent upon data size, not address size. */
8843 override
= (i
.prefix
[DATA_PREFIX
] != 0);
8844 if (flag_code
== CODE_64BIT
)
8846 if (override
|| i
.suffix
== WORD_MNEM_SUFFIX
)
8847 bigdisp
.bitfield
.disp16
= 1;
8850 bigdisp
.bitfield
.disp32
= 1;
8851 bigdisp
.bitfield
.disp32s
= 1;
8857 override
= (i
.suffix
== (flag_code
!= CODE_16BIT
8859 : LONG_MNEM_SUFFIX
));
8860 bigdisp
.bitfield
.disp32
= 1;
8861 if ((flag_code
== CODE_16BIT
) ^ override
)
8863 bigdisp
.bitfield
.disp32
= 0;
8864 bigdisp
.bitfield
.disp16
= 1;
8868 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
8871 exp
= &disp_expressions
[i
.disp_operands
];
8872 i
.op
[this_operand
].disps
= exp
;
8874 save_input_line_pointer
= input_line_pointer
;
8875 input_line_pointer
= disp_start
;
8876 END_STRING_AND_SAVE (disp_end
);
8878 #ifndef GCC_ASM_O_HACK
8879 #define GCC_ASM_O_HACK 0
8882 END_STRING_AND_SAVE (disp_end
+ 1);
8883 if (i
.types
[this_operand
].bitfield
.baseIndex
8884 && displacement_string_end
[-1] == '+')
8886 /* This hack is to avoid a warning when using the "o"
8887 constraint within gcc asm statements.
8890 #define _set_tssldt_desc(n,addr,limit,type) \
8891 __asm__ __volatile__ ( \
8893 "movw %w1,2+%0\n\t" \
8895 "movb %b1,4+%0\n\t" \
8896 "movb %4,5+%0\n\t" \
8897 "movb $0,6+%0\n\t" \
8898 "movb %h1,7+%0\n\t" \
8900 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
8902 This works great except that the output assembler ends
8903 up looking a bit weird if it turns out that there is
8904 no offset. You end up producing code that looks like:
8917 So here we provide the missing zero. */
8919 *displacement_string_end
= '0';
8922 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
8923 if (gotfree_input_line
)
8924 input_line_pointer
= gotfree_input_line
;
8926 exp_seg
= expression (exp
);
8929 if (*input_line_pointer
)
8930 as_bad (_("junk `%s' after expression"), input_line_pointer
);
8932 RESTORE_END_STRING (disp_end
+ 1);
8934 input_line_pointer
= save_input_line_pointer
;
8935 if (gotfree_input_line
)
8937 free (gotfree_input_line
);
8939 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
8940 exp
->X_op
= O_illegal
;
8943 ret
= i386_finalize_displacement (exp_seg
, exp
, types
, disp_start
);
8945 RESTORE_END_STRING (disp_end
);
8951 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
8952 i386_operand_type types
, const char *disp_start
)
8954 i386_operand_type bigdisp
;
8957 /* We do this to make sure that the section symbol is in
8958 the symbol table. We will ultimately change the relocation
8959 to be relative to the beginning of the section. */
8960 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
8961 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
8962 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
8964 if (exp
->X_op
!= O_symbol
)
8967 if (S_IS_LOCAL (exp
->X_add_symbol
)
8968 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
8969 && S_GET_SEGMENT (exp
->X_add_symbol
) != expr_section
)
8970 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
8971 exp
->X_op
= O_subtract
;
8972 exp
->X_op_symbol
= GOT_symbol
;
8973 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
8974 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
8975 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
8976 i
.reloc
[this_operand
] = BFD_RELOC_64
;
8978 i
.reloc
[this_operand
] = BFD_RELOC_32
;
8981 else if (exp
->X_op
== O_absent
8982 || exp
->X_op
== O_illegal
8983 || exp
->X_op
== O_big
)
8986 as_bad (_("missing or invalid displacement expression `%s'"),
8991 else if (flag_code
== CODE_64BIT
8992 && !i
.prefix
[ADDR_PREFIX
]
8993 && exp
->X_op
== O_constant
)
8995 /* Since displacement is signed extended to 64bit, don't allow
8996 disp32 and turn off disp32s if they are out of range. */
8997 i
.types
[this_operand
].bitfield
.disp32
= 0;
8998 if (!fits_in_signed_long (exp
->X_add_number
))
9000 i
.types
[this_operand
].bitfield
.disp32s
= 0;
9001 if (i
.types
[this_operand
].bitfield
.baseindex
)
9003 as_bad (_("0x%lx out range of signed 32bit displacement"),
9004 (long) exp
->X_add_number
);
9010 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
9011 else if (exp
->X_op
!= O_constant
9012 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
9013 && exp_seg
!= absolute_section
9014 && exp_seg
!= text_section
9015 && exp_seg
!= data_section
9016 && exp_seg
!= bss_section
9017 && exp_seg
!= undefined_section
9018 && !bfd_is_com_section (exp_seg
))
9020 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
9025 /* Check if this is a displacement only operand. */
9026 bigdisp
= i
.types
[this_operand
];
9027 bigdisp
.bitfield
.disp8
= 0;
9028 bigdisp
.bitfield
.disp16
= 0;
9029 bigdisp
.bitfield
.disp32
= 0;
9030 bigdisp
.bitfield
.disp32s
= 0;
9031 bigdisp
.bitfield
.disp64
= 0;
9032 if (operand_type_all_zero (&bigdisp
))
9033 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
9039 /* Return the active addressing mode, taking address override and
9040 registers forming the address into consideration. Update the
9041 address override prefix if necessary. */
9043 static enum flag_code
9044 i386_addressing_mode (void)
9046 enum flag_code addr_mode
;
9048 if (i
.prefix
[ADDR_PREFIX
])
9049 addr_mode
= flag_code
== CODE_32BIT
? CODE_16BIT
: CODE_32BIT
;
9052 addr_mode
= flag_code
;
9054 #if INFER_ADDR_PREFIX
9055 if (i
.mem_operands
== 0)
9057 /* Infer address prefix from the first memory operand. */
9058 const reg_entry
*addr_reg
= i
.base_reg
;
9060 if (addr_reg
== NULL
)
9061 addr_reg
= i
.index_reg
;
9065 if (addr_reg
->reg_num
== RegEip
9066 || addr_reg
->reg_num
== RegEiz
9067 || addr_reg
->reg_type
.bitfield
.dword
)
9068 addr_mode
= CODE_32BIT
;
9069 else if (flag_code
!= CODE_64BIT
9070 && addr_reg
->reg_type
.bitfield
.word
)
9071 addr_mode
= CODE_16BIT
;
9073 if (addr_mode
!= flag_code
)
9075 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
9077 /* Change the size of any displacement too. At most one
9078 of Disp16 or Disp32 is set.
9079 FIXME. There doesn't seem to be any real need for
9080 separate Disp16 and Disp32 flags. The same goes for
9081 Imm16 and Imm32. Removing them would probably clean
9082 up the code quite a lot. */
9083 if (flag_code
!= CODE_64BIT
9084 && (i
.types
[this_operand
].bitfield
.disp16
9085 || i
.types
[this_operand
].bitfield
.disp32
))
9086 i
.types
[this_operand
]
9087 = operand_type_xor (i
.types
[this_operand
], disp16_32
);
9097 /* Make sure the memory operand we've been dealt is valid.
9098 Return 1 on success, 0 on a failure. */
9101 i386_index_check (const char *operand_string
)
9103 const char *kind
= "base/index";
9104 enum flag_code addr_mode
= i386_addressing_mode ();
9106 if (current_templates
->start
->opcode_modifier
.isstring
9107 && !current_templates
->start
->opcode_modifier
.immext
9108 && (current_templates
->end
[-1].opcode_modifier
.isstring
9111 /* Memory operands of string insns are special in that they only allow
9112 a single register (rDI, rSI, or rBX) as their memory address. */
9113 const reg_entry
*expected_reg
;
9114 static const char *di_si
[][2] =
9120 static const char *bx
[] = { "ebx", "bx", "rbx" };
9122 kind
= "string address";
9124 if (current_templates
->start
->opcode_modifier
.repprefixok
)
9126 i386_operand_type type
= current_templates
->end
[-1].operand_types
[0];
9128 if (!type
.bitfield
.baseindex
9129 || ((!i
.mem_operands
!= !intel_syntax
)
9130 && current_templates
->end
[-1].operand_types
[1]
9131 .bitfield
.baseindex
))
9132 type
= current_templates
->end
[-1].operand_types
[1];
9133 expected_reg
= hash_find (reg_hash
,
9134 di_si
[addr_mode
][type
.bitfield
.esseg
]);
9138 expected_reg
= hash_find (reg_hash
, bx
[addr_mode
]);
9140 if (i
.base_reg
!= expected_reg
9142 || operand_type_check (i
.types
[this_operand
], disp
))
9144 /* The second memory operand must have the same size as
9148 && !((addr_mode
== CODE_64BIT
9149 && i
.base_reg
->reg_type
.bitfield
.qword
)
9150 || (addr_mode
== CODE_32BIT
9151 ? i
.base_reg
->reg_type
.bitfield
.dword
9152 : i
.base_reg
->reg_type
.bitfield
.word
)))
9155 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
9157 intel_syntax
? '[' : '(',
9159 expected_reg
->reg_name
,
9160 intel_syntax
? ']' : ')');
9167 as_bad (_("`%s' is not a valid %s expression"),
9168 operand_string
, kind
);
9173 if (addr_mode
!= CODE_16BIT
)
9175 /* 32-bit/64-bit checks. */
9177 && (addr_mode
== CODE_64BIT
9178 ? !i
.base_reg
->reg_type
.bitfield
.qword
9179 : !i
.base_reg
->reg_type
.bitfield
.dword
)
9181 || (i
.base_reg
->reg_num
9182 != (addr_mode
== CODE_64BIT
? RegRip
: RegEip
))))
9184 && !i
.index_reg
->reg_type
.bitfield
.xmmword
9185 && !i
.index_reg
->reg_type
.bitfield
.ymmword
9186 && !i
.index_reg
->reg_type
.bitfield
.zmmword
9187 && ((addr_mode
== CODE_64BIT
9188 ? !(i
.index_reg
->reg_type
.bitfield
.qword
9189 || i
.index_reg
->reg_num
== RegRiz
)
9190 : !(i
.index_reg
->reg_type
.bitfield
.dword
9191 || i
.index_reg
->reg_num
== RegEiz
))
9192 || !i
.index_reg
->reg_type
.bitfield
.baseindex
)))
9195 /* bndmk, bndldx, and bndstx have special restrictions. */
9196 if (current_templates
->start
->base_opcode
== 0xf30f1b
9197 || (current_templates
->start
->base_opcode
& ~1) == 0x0f1a)
9199 /* They cannot use RIP-relative addressing. */
9200 if (i
.base_reg
&& i
.base_reg
->reg_num
== RegRip
)
9202 as_bad (_("`%s' cannot be used here"), operand_string
);
9206 /* bndldx and bndstx ignore their scale factor. */
9207 if (current_templates
->start
->base_opcode
!= 0xf30f1b
9208 && i
.log2_scale_factor
)
9209 as_warn (_("register scaling is being ignored here"));
9214 /* 16-bit checks. */
9216 && (!i
.base_reg
->reg_type
.bitfield
.word
9217 || !i
.base_reg
->reg_type
.bitfield
.baseindex
))
9219 && (!i
.index_reg
->reg_type
.bitfield
.word
9220 || !i
.index_reg
->reg_type
.bitfield
.baseindex
9222 && i
.base_reg
->reg_num
< 6
9223 && i
.index_reg
->reg_num
>= 6
9224 && i
.log2_scale_factor
== 0))))
9231 /* Handle vector immediates. */
9234 RC_SAE_immediate (const char *imm_start
)
9236 unsigned int match_found
, j
;
9237 const char *pstr
= imm_start
;
9245 for (j
= 0; j
< ARRAY_SIZE (RC_NamesTable
); j
++)
9247 if (!strncmp (pstr
, RC_NamesTable
[j
].name
, RC_NamesTable
[j
].len
))
9251 rc_op
.type
= RC_NamesTable
[j
].type
;
9252 rc_op
.operand
= this_operand
;
9253 i
.rounding
= &rc_op
;
9257 as_bad (_("duplicated `%s'"), imm_start
);
9260 pstr
+= RC_NamesTable
[j
].len
;
9270 as_bad (_("Missing '}': '%s'"), imm_start
);
9273 /* RC/SAE immediate string should contain nothing more. */;
9276 as_bad (_("Junk after '}': '%s'"), imm_start
);
9280 exp
= &im_expressions
[i
.imm_operands
++];
9281 i
.op
[this_operand
].imms
= exp
;
9283 exp
->X_op
= O_constant
;
9284 exp
->X_add_number
= 0;
9285 exp
->X_add_symbol
= (symbolS
*) 0;
9286 exp
->X_op_symbol
= (symbolS
*) 0;
9288 i
.types
[this_operand
].bitfield
.imm8
= 1;
9292 /* Only string instructions can have a second memory operand, so
9293 reduce current_templates to just those if it contains any. */
9295 maybe_adjust_templates (void)
9297 const insn_template
*t
;
9299 gas_assert (i
.mem_operands
== 1);
9301 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
9302 if (t
->opcode_modifier
.isstring
)
9305 if (t
< current_templates
->end
)
9307 static templates aux_templates
;
9308 bfd_boolean recheck
;
9310 aux_templates
.start
= t
;
9311 for (; t
< current_templates
->end
; ++t
)
9312 if (!t
->opcode_modifier
.isstring
)
9314 aux_templates
.end
= t
;
9316 /* Determine whether to re-check the first memory operand. */
9317 recheck
= (aux_templates
.start
!= current_templates
->start
9318 || t
!= current_templates
->end
);
9320 current_templates
= &aux_templates
;
9325 if (i
.memop1_string
!= NULL
9326 && i386_index_check (i
.memop1_string
) == 0)
9335 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
9339 i386_att_operand (char *operand_string
)
9343 char *op_string
= operand_string
;
9345 if (is_space_char (*op_string
))
9348 /* We check for an absolute prefix (differentiating,
9349 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
9350 if (*op_string
== ABSOLUTE_PREFIX
)
9353 if (is_space_char (*op_string
))
9355 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
9358 /* Check if operand is a register. */
9359 if ((r
= parse_register (op_string
, &end_op
)) != NULL
)
9361 i386_operand_type temp
;
9363 /* Check for a segment override by searching for ':' after a
9364 segment register. */
9366 if (is_space_char (*op_string
))
9368 if (*op_string
== ':'
9369 && (r
->reg_type
.bitfield
.sreg2
9370 || r
->reg_type
.bitfield
.sreg3
))
9375 i
.seg
[i
.mem_operands
] = &es
;
9378 i
.seg
[i
.mem_operands
] = &cs
;
9381 i
.seg
[i
.mem_operands
] = &ss
;
9384 i
.seg
[i
.mem_operands
] = &ds
;
9387 i
.seg
[i
.mem_operands
] = &fs
;
9390 i
.seg
[i
.mem_operands
] = &gs
;
9394 /* Skip the ':' and whitespace. */
9396 if (is_space_char (*op_string
))
9399 if (!is_digit_char (*op_string
)
9400 && !is_identifier_char (*op_string
)
9401 && *op_string
!= '('
9402 && *op_string
!= ABSOLUTE_PREFIX
)
9404 as_bad (_("bad memory operand `%s'"), op_string
);
9407 /* Handle case of %es:*foo. */
9408 if (*op_string
== ABSOLUTE_PREFIX
)
9411 if (is_space_char (*op_string
))
9413 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
9415 goto do_memory_reference
;
9418 /* Handle vector operations. */
9419 if (*op_string
== '{')
9421 op_string
= check_VecOperations (op_string
, NULL
);
9422 if (op_string
== NULL
)
9428 as_bad (_("junk `%s' after register"), op_string
);
9432 temp
.bitfield
.baseindex
= 0;
9433 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
9435 i
.types
[this_operand
].bitfield
.unspecified
= 0;
9436 i
.op
[this_operand
].regs
= r
;
9439 else if (*op_string
== REGISTER_PREFIX
)
9441 as_bad (_("bad register name `%s'"), op_string
);
9444 else if (*op_string
== IMMEDIATE_PREFIX
)
9447 if (i
.types
[this_operand
].bitfield
.jumpabsolute
)
9449 as_bad (_("immediate operand illegal with absolute jump"));
9452 if (!i386_immediate (op_string
))
9455 else if (RC_SAE_immediate (operand_string
))
9457 /* If it is a RC or SAE immediate, do nothing. */
9460 else if (is_digit_char (*op_string
)
9461 || is_identifier_char (*op_string
)
9462 || *op_string
== '"'
9463 || *op_string
== '(')
9465 /* This is a memory reference of some sort. */
9468 /* Start and end of displacement string expression (if found). */
9469 char *displacement_string_start
;
9470 char *displacement_string_end
;
9473 do_memory_reference
:
9474 if (i
.mem_operands
== 1 && !maybe_adjust_templates ())
9476 if ((i
.mem_operands
== 1
9477 && !current_templates
->start
->opcode_modifier
.isstring
)
9478 || i
.mem_operands
== 2)
9480 as_bad (_("too many memory references for `%s'"),
9481 current_templates
->start
->name
);
9485 /* Check for base index form. We detect the base index form by
9486 looking for an ')' at the end of the operand, searching
9487 for the '(' matching it, and finding a REGISTER_PREFIX or ','
9489 base_string
= op_string
+ strlen (op_string
);
9491 /* Handle vector operations. */
9492 vop_start
= strchr (op_string
, '{');
9493 if (vop_start
&& vop_start
< base_string
)
9495 if (check_VecOperations (vop_start
, base_string
) == NULL
)
9497 base_string
= vop_start
;
9501 if (is_space_char (*base_string
))
9504 /* If we only have a displacement, set-up for it to be parsed later. */
9505 displacement_string_start
= op_string
;
9506 displacement_string_end
= base_string
+ 1;
9508 if (*base_string
== ')')
9511 unsigned int parens_balanced
= 1;
9512 /* We've already checked that the number of left & right ()'s are
9513 equal, so this loop will not be infinite. */
9517 if (*base_string
== ')')
9519 if (*base_string
== '(')
9522 while (parens_balanced
);
9524 temp_string
= base_string
;
9526 /* Skip past '(' and whitespace. */
9528 if (is_space_char (*base_string
))
9531 if (*base_string
== ','
9532 || ((i
.base_reg
= parse_register (base_string
, &end_op
))
9535 displacement_string_end
= temp_string
;
9537 i
.types
[this_operand
].bitfield
.baseindex
= 1;
9541 base_string
= end_op
;
9542 if (is_space_char (*base_string
))
9546 /* There may be an index reg or scale factor here. */
9547 if (*base_string
== ',')
9550 if (is_space_char (*base_string
))
9553 if ((i
.index_reg
= parse_register (base_string
, &end_op
))
9556 base_string
= end_op
;
9557 if (is_space_char (*base_string
))
9559 if (*base_string
== ',')
9562 if (is_space_char (*base_string
))
9565 else if (*base_string
!= ')')
9567 as_bad (_("expecting `,' or `)' "
9568 "after index register in `%s'"),
9573 else if (*base_string
== REGISTER_PREFIX
)
9575 end_op
= strchr (base_string
, ',');
9578 as_bad (_("bad register name `%s'"), base_string
);
9582 /* Check for scale factor. */
9583 if (*base_string
!= ')')
9585 char *end_scale
= i386_scale (base_string
);
9590 base_string
= end_scale
;
9591 if (is_space_char (*base_string
))
9593 if (*base_string
!= ')')
9595 as_bad (_("expecting `)' "
9596 "after scale factor in `%s'"),
9601 else if (!i
.index_reg
)
9603 as_bad (_("expecting index register or scale factor "
9604 "after `,'; got '%c'"),
9609 else if (*base_string
!= ')')
9611 as_bad (_("expecting `,' or `)' "
9612 "after base register in `%s'"),
9617 else if (*base_string
== REGISTER_PREFIX
)
9619 end_op
= strchr (base_string
, ',');
9622 as_bad (_("bad register name `%s'"), base_string
);
9627 /* If there's an expression beginning the operand, parse it,
9628 assuming displacement_string_start and
9629 displacement_string_end are meaningful. */
9630 if (displacement_string_start
!= displacement_string_end
)
9632 if (!i386_displacement (displacement_string_start
,
9633 displacement_string_end
))
9637 /* Special case for (%dx) while doing input/output op. */
9639 && operand_type_equal (&i
.base_reg
->reg_type
,
9640 ®16_inoutportreg
)
9642 && i
.log2_scale_factor
== 0
9643 && i
.seg
[i
.mem_operands
] == 0
9644 && !operand_type_check (i
.types
[this_operand
], disp
))
9646 i
.types
[this_operand
] = inoutportreg
;
9650 if (i386_index_check (operand_string
) == 0)
9652 i
.types
[this_operand
].bitfield
.mem
= 1;
9653 if (i
.mem_operands
== 0)
9654 i
.memop1_string
= xstrdup (operand_string
);
9659 /* It's not a memory operand; argh! */
9660 as_bad (_("invalid char %s beginning operand %d `%s'"),
9661 output_invalid (*op_string
),
9666 return 1; /* Normal return. */
9669 /* Calculate the maximum variable size (i.e., excluding fr_fix)
9670 that an rs_machine_dependent frag may reach. */
9673 i386_frag_max_var (fragS
*frag
)
9675 /* The only relaxable frags are for jumps.
9676 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
9677 gas_assert (frag
->fr_type
== rs_machine_dependent
);
9678 return TYPE_FROM_RELAX_STATE (frag
->fr_subtype
) == UNCOND_JUMP
? 4 : 5;
9681 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9683 elf_symbol_resolved_in_segment_p (symbolS
*fr_symbol
, offsetT fr_var
)
9685 /* STT_GNU_IFUNC symbol must go through PLT. */
9686 if ((symbol_get_bfdsym (fr_symbol
)->flags
9687 & BSF_GNU_INDIRECT_FUNCTION
) != 0)
9690 if (!S_IS_EXTERNAL (fr_symbol
))
9691 /* Symbol may be weak or local. */
9692 return !S_IS_WEAK (fr_symbol
);
9694 /* Global symbols with non-default visibility can't be preempted. */
9695 if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol
)) != STV_DEFAULT
)
9698 if (fr_var
!= NO_RELOC
)
9699 switch ((enum bfd_reloc_code_real
) fr_var
)
9701 case BFD_RELOC_386_PLT32
:
9702 case BFD_RELOC_X86_64_PLT32
:
9703 /* Symbol with PLT relocation may be preempted. */
9709 /* Global symbols with default visibility in a shared library may be
9710 preempted by another definition. */
9715 /* md_estimate_size_before_relax()
9717 Called just before relax() for rs_machine_dependent frags. The x86
9718 assembler uses these frags to handle variable size jump
9721 Any symbol that is now undefined will not become defined.
9722 Return the correct fr_subtype in the frag.
9723 Return the initial "guess for variable size of frag" to caller.
9724 The guess is actually the growth beyond the fixed part. Whatever
9725 we do to grow the fixed or variable part contributes to our
9729 md_estimate_size_before_relax (fragS
*fragP
, segT segment
)
9731 /* We've already got fragP->fr_subtype right; all we have to do is
9732 check for un-relaxable symbols. On an ELF system, we can't relax
9733 an externally visible symbol, because it may be overridden by a
9735 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
9736 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9738 && !elf_symbol_resolved_in_segment_p (fragP
->fr_symbol
,
9741 #if defined (OBJ_COFF) && defined (TE_PE)
9742 || (OUTPUT_FLAVOR
== bfd_target_coff_flavour
9743 && S_IS_WEAK (fragP
->fr_symbol
))
9747 /* Symbol is undefined in this segment, or we need to keep a
9748 reloc so that weak symbols can be overridden. */
9749 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
9750 enum bfd_reloc_code_real reloc_type
;
9751 unsigned char *opcode
;
9754 if (fragP
->fr_var
!= NO_RELOC
)
9755 reloc_type
= (enum bfd_reloc_code_real
) fragP
->fr_var
;
9757 reloc_type
= BFD_RELOC_16_PCREL
;
9758 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9759 else if (need_plt32_p (fragP
->fr_symbol
))
9760 reloc_type
= BFD_RELOC_X86_64_PLT32
;
9763 reloc_type
= BFD_RELOC_32_PCREL
;
9765 old_fr_fix
= fragP
->fr_fix
;
9766 opcode
= (unsigned char *) fragP
->fr_opcode
;
9768 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
9771 /* Make jmp (0xeb) a (d)word displacement jump. */
9773 fragP
->fr_fix
+= size
;
9774 fix_new (fragP
, old_fr_fix
, size
,
9776 fragP
->fr_offset
, 1,
9782 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
9784 /* Negate the condition, and branch past an
9785 unconditional jump. */
9788 /* Insert an unconditional jump. */
9790 /* We added two extra opcode bytes, and have a two byte
9792 fragP
->fr_fix
+= 2 + 2;
9793 fix_new (fragP
, old_fr_fix
+ 2, 2,
9795 fragP
->fr_offset
, 1,
9802 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
9807 fixP
= fix_new (fragP
, old_fr_fix
, 1,
9809 fragP
->fr_offset
, 1,
9811 fixP
->fx_signed
= 1;
9815 /* This changes the byte-displacement jump 0x7N
9816 to the (d)word-displacement jump 0x0f,0x8N. */
9817 opcode
[1] = opcode
[0] + 0x10;
9818 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
9819 /* We've added an opcode byte. */
9820 fragP
->fr_fix
+= 1 + size
;
9821 fix_new (fragP
, old_fr_fix
+ 1, size
,
9823 fragP
->fr_offset
, 1,
9828 BAD_CASE (fragP
->fr_subtype
);
9832 return fragP
->fr_fix
- old_fr_fix
;
9835 /* Guess size depending on current relax state. Initially the relax
9836 state will correspond to a short jump and we return 1, because
9837 the variable part of the frag (the branch offset) is one byte
9838 long. However, we can relax a section more than once and in that
9839 case we must either set fr_subtype back to the unrelaxed state,
9840 or return the value for the appropriate branch. */
9841 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
9844 /* Called after relax() is finished.
9846 In: Address of frag.
9847 fr_type == rs_machine_dependent.
9848 fr_subtype is what the address relaxed to.
9850 Out: Any fixSs and constants are set up.
9851 Caller will turn frag into a ".space 0". */
9854 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec ATTRIBUTE_UNUSED
,
9857 unsigned char *opcode
;
9858 unsigned char *where_to_put_displacement
= NULL
;
9859 offsetT target_address
;
9860 offsetT opcode_address
;
9861 unsigned int extension
= 0;
9862 offsetT displacement_from_opcode_start
;
9864 opcode
= (unsigned char *) fragP
->fr_opcode
;
9866 /* Address we want to reach in file space. */
9867 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
9869 /* Address opcode resides at in file space. */
9870 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
9872 /* Displacement from opcode start to fill into instruction. */
9873 displacement_from_opcode_start
= target_address
- opcode_address
;
9875 if ((fragP
->fr_subtype
& BIG
) == 0)
9877 /* Don't have to change opcode. */
9878 extension
= 1; /* 1 opcode + 1 displacement */
9879 where_to_put_displacement
= &opcode
[1];
9883 if (no_cond_jump_promotion
9884 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
9885 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
9886 _("long jump required"));
9888 switch (fragP
->fr_subtype
)
9890 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
9891 extension
= 4; /* 1 opcode + 4 displacement */
9893 where_to_put_displacement
= &opcode
[1];
9896 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
9897 extension
= 2; /* 1 opcode + 2 displacement */
9899 where_to_put_displacement
= &opcode
[1];
9902 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
9903 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
9904 extension
= 5; /* 2 opcode + 4 displacement */
9905 opcode
[1] = opcode
[0] + 0x10;
9906 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
9907 where_to_put_displacement
= &opcode
[2];
9910 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
9911 extension
= 3; /* 2 opcode + 2 displacement */
9912 opcode
[1] = opcode
[0] + 0x10;
9913 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
9914 where_to_put_displacement
= &opcode
[2];
9917 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
9922 where_to_put_displacement
= &opcode
[3];
9926 BAD_CASE (fragP
->fr_subtype
);
9931 /* If size if less then four we are sure that the operand fits,
9932 but if it's 4, then it could be that the displacement is larger
9934 if (DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
) == 4
9936 && ((addressT
) (displacement_from_opcode_start
- extension
9937 + ((addressT
) 1 << 31))
9938 > (((addressT
) 2 << 31) - 1)))
9940 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
9941 _("jump target out of range"));
9942 /* Make us emit 0. */
9943 displacement_from_opcode_start
= extension
;
9945 /* Now put displacement after opcode. */
9946 md_number_to_chars ((char *) where_to_put_displacement
,
9947 (valueT
) (displacement_from_opcode_start
- extension
),
9948 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
9949 fragP
->fr_fix
+= extension
;
9952 /* Apply a fixup (fixP) to segment data, once it has been determined
9953 by our caller that we have all the info we need to fix it up.
9955 Parameter valP is the pointer to the value of the bits.
9957 On the 386, immediates, displacements, and data pointers are all in
9958 the same (little-endian) format, so we don't need to care about which
9962 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
9964 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
9965 valueT value
= *valP
;
9967 #if !defined (TE_Mach)
9970 switch (fixP
->fx_r_type
)
9976 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
9979 case BFD_RELOC_X86_64_32S
:
9980 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
9983 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
9986 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
9991 if (fixP
->fx_addsy
!= NULL
9992 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
9993 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
9994 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
9995 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
9996 && !use_rela_relocations
)
9998 /* This is a hack. There should be a better way to handle this.
9999 This covers for the fact that bfd_install_relocation will
10000 subtract the current location (for partial_inplace, PC relative
10001 relocations); see more below. */
10005 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
10008 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
10010 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10013 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
10015 if ((sym_seg
== seg
10016 || (symbol_section_p (fixP
->fx_addsy
)
10017 && sym_seg
!= absolute_section
))
10018 && !generic_force_reloc (fixP
))
10020 /* Yes, we add the values in twice. This is because
10021 bfd_install_relocation subtracts them out again. I think
10022 bfd_install_relocation is broken, but I don't dare change
10024 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
10028 #if defined (OBJ_COFF) && defined (TE_PE)
10029 /* For some reason, the PE format does not store a
10030 section address offset for a PC relative symbol. */
10031 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
10032 || S_IS_WEAK (fixP
->fx_addsy
))
10033 value
+= md_pcrel_from (fixP
);
10036 #if defined (OBJ_COFF) && defined (TE_PE)
10037 if (fixP
->fx_addsy
!= NULL
10038 && S_IS_WEAK (fixP
->fx_addsy
)
10039 /* PR 16858: Do not modify weak function references. */
10040 && ! fixP
->fx_pcrel
)
10042 #if !defined (TE_PEP)
10043 /* For x86 PE weak function symbols are neither PC-relative
10044 nor do they set S_IS_FUNCTION. So the only reliable way
10045 to detect them is to check the flags of their containing
10047 if (S_GET_SEGMENT (fixP
->fx_addsy
) != NULL
10048 && S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_CODE
)
10052 value
-= S_GET_VALUE (fixP
->fx_addsy
);
10056 /* Fix a few things - the dynamic linker expects certain values here,
10057 and we must not disappoint it. */
10058 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10059 if (IS_ELF
&& fixP
->fx_addsy
)
10060 switch (fixP
->fx_r_type
)
10062 case BFD_RELOC_386_PLT32
:
10063 case BFD_RELOC_X86_64_PLT32
:
10064 /* Make the jump instruction point to the address of the operand. At
10065 runtime we merely add the offset to the actual PLT entry. */
10069 case BFD_RELOC_386_TLS_GD
:
10070 case BFD_RELOC_386_TLS_LDM
:
10071 case BFD_RELOC_386_TLS_IE_32
:
10072 case BFD_RELOC_386_TLS_IE
:
10073 case BFD_RELOC_386_TLS_GOTIE
:
10074 case BFD_RELOC_386_TLS_GOTDESC
:
10075 case BFD_RELOC_X86_64_TLSGD
:
10076 case BFD_RELOC_X86_64_TLSLD
:
10077 case BFD_RELOC_X86_64_GOTTPOFF
:
10078 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
10079 value
= 0; /* Fully resolved at runtime. No addend. */
10081 case BFD_RELOC_386_TLS_LE
:
10082 case BFD_RELOC_386_TLS_LDO_32
:
10083 case BFD_RELOC_386_TLS_LE_32
:
10084 case BFD_RELOC_X86_64_DTPOFF32
:
10085 case BFD_RELOC_X86_64_DTPOFF64
:
10086 case BFD_RELOC_X86_64_TPOFF32
:
10087 case BFD_RELOC_X86_64_TPOFF64
:
10088 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
10091 case BFD_RELOC_386_TLS_DESC_CALL
:
10092 case BFD_RELOC_X86_64_TLSDESC_CALL
:
10093 value
= 0; /* Fully resolved at runtime. No addend. */
10094 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
10098 case BFD_RELOC_VTABLE_INHERIT
:
10099 case BFD_RELOC_VTABLE_ENTRY
:
10106 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
10108 #endif /* !defined (TE_Mach) */
10110 /* Are we finished with this relocation now? */
10111 if (fixP
->fx_addsy
== NULL
)
10113 #if defined (OBJ_COFF) && defined (TE_PE)
10114 else if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
10117 /* Remember value for tc_gen_reloc. */
10118 fixP
->fx_addnumber
= value
;
10119 /* Clear out the frag for now. */
10123 else if (use_rela_relocations
)
10125 fixP
->fx_no_overflow
= 1;
10126 /* Remember value for tc_gen_reloc. */
10127 fixP
->fx_addnumber
= value
;
10131 md_number_to_chars (p
, value
, fixP
->fx_size
);
10135 md_atof (int type
, char *litP
, int *sizeP
)
10137 /* This outputs the LITTLENUMs in REVERSE order;
10138 in accord with the bigendian 386. */
10139 return ieee_md_atof (type
, litP
, sizeP
, FALSE
);
10142 static char output_invalid_buf
[sizeof (unsigned char) * 2 + 6];
10145 output_invalid (int c
)
10148 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
10151 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
10152 "(0x%x)", (unsigned char) c
);
10153 return output_invalid_buf
;
10156 /* REG_STRING starts *before* REGISTER_PREFIX. */
10158 static const reg_entry
*
10159 parse_real_register (char *reg_string
, char **end_op
)
10161 char *s
= reg_string
;
10163 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
10164 const reg_entry
*r
;
10166 /* Skip possible REGISTER_PREFIX and possible whitespace. */
10167 if (*s
== REGISTER_PREFIX
)
10170 if (is_space_char (*s
))
10173 p
= reg_name_given
;
10174 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
10176 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
10177 return (const reg_entry
*) NULL
;
10181 /* For naked regs, make sure that we are not dealing with an identifier.
10182 This prevents confusing an identifier like `eax_var' with register
10184 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
10185 return (const reg_entry
*) NULL
;
10189 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
10191 /* Handle floating point regs, allowing spaces in the (i) part. */
10192 if (r
== i386_regtab
/* %st is first entry of table */)
10194 if (!cpu_arch_flags
.bitfield
.cpu8087
10195 && !cpu_arch_flags
.bitfield
.cpu287
10196 && !cpu_arch_flags
.bitfield
.cpu387
)
10197 return (const reg_entry
*) NULL
;
10199 if (is_space_char (*s
))
10204 if (is_space_char (*s
))
10206 if (*s
>= '0' && *s
<= '7')
10208 int fpr
= *s
- '0';
10210 if (is_space_char (*s
))
10215 r
= (const reg_entry
*) hash_find (reg_hash
, "st(0)");
10220 /* We have "%st(" then garbage. */
10221 return (const reg_entry
*) NULL
;
10225 if (r
== NULL
|| allow_pseudo_reg
)
10228 if (operand_type_all_zero (&r
->reg_type
))
10229 return (const reg_entry
*) NULL
;
10231 if ((r
->reg_type
.bitfield
.dword
10232 || r
->reg_type
.bitfield
.sreg3
10233 || r
->reg_type
.bitfield
.control
10234 || r
->reg_type
.bitfield
.debug
10235 || r
->reg_type
.bitfield
.test
)
10236 && !cpu_arch_flags
.bitfield
.cpui386
)
10237 return (const reg_entry
*) NULL
;
10239 if (r
->reg_type
.bitfield
.regmmx
&& !cpu_arch_flags
.bitfield
.cpummx
)
10240 return (const reg_entry
*) NULL
;
10242 if (!cpu_arch_flags
.bitfield
.cpuavx512f
)
10244 if (r
->reg_type
.bitfield
.zmmword
|| r
->reg_type
.bitfield
.regmask
)
10245 return (const reg_entry
*) NULL
;
10247 if (!cpu_arch_flags
.bitfield
.cpuavx
)
10249 if (r
->reg_type
.bitfield
.ymmword
)
10250 return (const reg_entry
*) NULL
;
10252 if (!cpu_arch_flags
.bitfield
.cpusse
&& r
->reg_type
.bitfield
.xmmword
)
10253 return (const reg_entry
*) NULL
;
10257 if (r
->reg_type
.bitfield
.regbnd
&& !cpu_arch_flags
.bitfield
.cpumpx
)
10258 return (const reg_entry
*) NULL
;
10260 /* Don't allow fake index register unless allow_index_reg isn't 0. */
10261 if (!allow_index_reg
10262 && (r
->reg_num
== RegEiz
|| r
->reg_num
== RegRiz
))
10263 return (const reg_entry
*) NULL
;
10265 /* Upper 16 vector registers are only available with VREX in 64bit
10266 mode, and require EVEX encoding. */
10267 if (r
->reg_flags
& RegVRex
)
10269 if (!cpu_arch_flags
.bitfield
.cpuvrex
10270 || flag_code
!= CODE_64BIT
)
10271 return (const reg_entry
*) NULL
;
10273 i
.vec_encoding
= vex_encoding_evex
;
10276 if (((r
->reg_flags
& (RegRex64
| RegRex
)) || r
->reg_type
.bitfield
.qword
)
10277 && (!cpu_arch_flags
.bitfield
.cpulm
|| !r
->reg_type
.bitfield
.control
)
10278 && flag_code
!= CODE_64BIT
)
10279 return (const reg_entry
*) NULL
;
10281 if (r
->reg_type
.bitfield
.sreg3
&& r
->reg_num
== RegFlat
&& !intel_syntax
)
10282 return (const reg_entry
*) NULL
;
10287 /* REG_STRING starts *before* REGISTER_PREFIX. */
10289 static const reg_entry
*
10290 parse_register (char *reg_string
, char **end_op
)
10292 const reg_entry
*r
;
10294 if (*reg_string
== REGISTER_PREFIX
|| allow_naked_reg
)
10295 r
= parse_real_register (reg_string
, end_op
);
10300 char *save
= input_line_pointer
;
10304 input_line_pointer
= reg_string
;
10305 c
= get_symbol_name (®_string
);
10306 symbolP
= symbol_find (reg_string
);
10307 if (symbolP
&& S_GET_SEGMENT (symbolP
) == reg_section
)
10309 const expressionS
*e
= symbol_get_value_expression (symbolP
);
10311 know (e
->X_op
== O_register
);
10312 know (e
->X_add_number
>= 0
10313 && (valueT
) e
->X_add_number
< i386_regtab_size
);
10314 r
= i386_regtab
+ e
->X_add_number
;
10315 if ((r
->reg_flags
& RegVRex
))
10316 i
.vec_encoding
= vex_encoding_evex
;
10317 *end_op
= input_line_pointer
;
10319 *input_line_pointer
= c
;
10320 input_line_pointer
= save
;
10326 i386_parse_name (char *name
, expressionS
*e
, char *nextcharP
)
10328 const reg_entry
*r
;
10329 char *end
= input_line_pointer
;
10332 r
= parse_register (name
, &input_line_pointer
);
10333 if (r
&& end
<= input_line_pointer
)
10335 *nextcharP
= *input_line_pointer
;
10336 *input_line_pointer
= 0;
10337 e
->X_op
= O_register
;
10338 e
->X_add_number
= r
- i386_regtab
;
10341 input_line_pointer
= end
;
10343 return intel_syntax
? i386_intel_parse_name (name
, e
) : 0;
10347 md_operand (expressionS
*e
)
10350 const reg_entry
*r
;
10352 switch (*input_line_pointer
)
10354 case REGISTER_PREFIX
:
10355 r
= parse_real_register (input_line_pointer
, &end
);
10358 e
->X_op
= O_register
;
10359 e
->X_add_number
= r
- i386_regtab
;
10360 input_line_pointer
= end
;
10365 gas_assert (intel_syntax
);
10366 end
= input_line_pointer
++;
10368 if (*input_line_pointer
== ']')
10370 ++input_line_pointer
;
10371 e
->X_op_symbol
= make_expr_symbol (e
);
10372 e
->X_add_symbol
= NULL
;
10373 e
->X_add_number
= 0;
10378 e
->X_op
= O_absent
;
10379 input_line_pointer
= end
;
10386 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10387 const char *md_shortopts
= "kVQ:sqnO::";
10389 const char *md_shortopts
= "qnO::";
10392 #define OPTION_32 (OPTION_MD_BASE + 0)
10393 #define OPTION_64 (OPTION_MD_BASE + 1)
10394 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
10395 #define OPTION_MARCH (OPTION_MD_BASE + 3)
10396 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
10397 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
10398 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
10399 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
10400 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
10401 #define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 9)
10402 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
10403 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
10404 #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
10405 #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
10406 #define OPTION_X32 (OPTION_MD_BASE + 14)
10407 #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
10408 #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
10409 #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
10410 #define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
10411 #define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
10412 #define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
10413 #define OPTION_MSHARED (OPTION_MD_BASE + 21)
10414 #define OPTION_MAMD64 (OPTION_MD_BASE + 22)
10415 #define OPTION_MINTEL64 (OPTION_MD_BASE + 23)
10416 #define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24)
10418 struct option md_longopts
[] =
10420 {"32", no_argument
, NULL
, OPTION_32
},
10421 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10422 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
10423 {"64", no_argument
, NULL
, OPTION_64
},
10425 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10426 {"x32", no_argument
, NULL
, OPTION_X32
},
10427 {"mshared", no_argument
, NULL
, OPTION_MSHARED
},
10429 {"divide", no_argument
, NULL
, OPTION_DIVIDE
},
10430 {"march", required_argument
, NULL
, OPTION_MARCH
},
10431 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
10432 {"mmnemonic", required_argument
, NULL
, OPTION_MMNEMONIC
},
10433 {"msyntax", required_argument
, NULL
, OPTION_MSYNTAX
},
10434 {"mindex-reg", no_argument
, NULL
, OPTION_MINDEX_REG
},
10435 {"mnaked-reg", no_argument
, NULL
, OPTION_MNAKED_REG
},
10436 {"msse2avx", no_argument
, NULL
, OPTION_MSSE2AVX
},
10437 {"msse-check", required_argument
, NULL
, OPTION_MSSE_CHECK
},
10438 {"moperand-check", required_argument
, NULL
, OPTION_MOPERAND_CHECK
},
10439 {"mavxscalar", required_argument
, NULL
, OPTION_MAVXSCALAR
},
10440 {"madd-bnd-prefix", no_argument
, NULL
, OPTION_MADD_BND_PREFIX
},
10441 {"mevexlig", required_argument
, NULL
, OPTION_MEVEXLIG
},
10442 {"mevexwig", required_argument
, NULL
, OPTION_MEVEXWIG
},
10443 # if defined (TE_PE) || defined (TE_PEP)
10444 {"mbig-obj", no_argument
, NULL
, OPTION_MBIG_OBJ
},
10446 {"momit-lock-prefix", required_argument
, NULL
, OPTION_MOMIT_LOCK_PREFIX
},
10447 {"mfence-as-lock-add", required_argument
, NULL
, OPTION_MFENCE_AS_LOCK_ADD
},
10448 {"mrelax-relocations", required_argument
, NULL
, OPTION_MRELAX_RELOCATIONS
},
10449 {"mevexrcig", required_argument
, NULL
, OPTION_MEVEXRCIG
},
10450 {"mamd64", no_argument
, NULL
, OPTION_MAMD64
},
10451 {"mintel64", no_argument
, NULL
, OPTION_MINTEL64
},
10452 {NULL
, no_argument
, NULL
, 0}
10454 size_t md_longopts_size
= sizeof (md_longopts
);
10457 md_parse_option (int c
, const char *arg
)
10460 char *arch
, *next
, *saved
;
10465 optimize_align_code
= 0;
10469 quiet_warnings
= 1;
10472 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10473 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
10474 should be emitted or not. FIXME: Not implemented. */
10478 /* -V: SVR4 argument to print version ID. */
10480 print_version_id ();
10483 /* -k: Ignore for FreeBSD compatibility. */
10488 /* -s: On i386 Solaris, this tells the native assembler to use
10489 .stab instead of .stab.excl. We always use .stab anyhow. */
10492 case OPTION_MSHARED
:
10496 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10497 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
10500 const char **list
, **l
;
10502 list
= bfd_target_list ();
10503 for (l
= list
; *l
!= NULL
; l
++)
10504 if (CONST_STRNEQ (*l
, "elf64-x86-64")
10505 || strcmp (*l
, "coff-x86-64") == 0
10506 || strcmp (*l
, "pe-x86-64") == 0
10507 || strcmp (*l
, "pei-x86-64") == 0
10508 || strcmp (*l
, "mach-o-x86-64") == 0)
10510 default_arch
= "x86_64";
10514 as_fatal (_("no compiled in support for x86_64"));
10520 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10524 const char **list
, **l
;
10526 list
= bfd_target_list ();
10527 for (l
= list
; *l
!= NULL
; l
++)
10528 if (CONST_STRNEQ (*l
, "elf32-x86-64"))
10530 default_arch
= "x86_64:32";
10534 as_fatal (_("no compiled in support for 32bit x86_64"));
10538 as_fatal (_("32bit x86_64 is only supported for ELF"));
10543 default_arch
= "i386";
10546 case OPTION_DIVIDE
:
10547 #ifdef SVR4_COMMENT_CHARS
10552 n
= XNEWVEC (char, strlen (i386_comment_chars
) + 1);
10554 for (s
= i386_comment_chars
; *s
!= '\0'; s
++)
10558 i386_comment_chars
= n
;
10564 saved
= xstrdup (arg
);
10566 /* Allow -march=+nosse. */
10572 as_fatal (_("invalid -march= option: `%s'"), arg
);
10573 next
= strchr (arch
, '+');
10576 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
10578 if (strcmp (arch
, cpu_arch
[j
].name
) == 0)
10581 if (! cpu_arch
[j
].flags
.bitfield
.cpui386
)
10584 cpu_arch_name
= cpu_arch
[j
].name
;
10585 cpu_sub_arch_name
= NULL
;
10586 cpu_arch_flags
= cpu_arch
[j
].flags
;
10587 cpu_arch_isa
= cpu_arch
[j
].type
;
10588 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
10589 if (!cpu_arch_tune_set
)
10591 cpu_arch_tune
= cpu_arch_isa
;
10592 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
10596 else if (*cpu_arch
[j
].name
== '.'
10597 && strcmp (arch
, cpu_arch
[j
].name
+ 1) == 0)
10599 /* ISA extension. */
10600 i386_cpu_flags flags
;
10602 flags
= cpu_flags_or (cpu_arch_flags
,
10603 cpu_arch
[j
].flags
);
10605 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
10607 if (cpu_sub_arch_name
)
10609 char *name
= cpu_sub_arch_name
;
10610 cpu_sub_arch_name
= concat (name
,
10612 (const char *) NULL
);
10616 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
10617 cpu_arch_flags
= flags
;
10618 cpu_arch_isa_flags
= flags
;
10622 = cpu_flags_or (cpu_arch_isa_flags
,
10623 cpu_arch
[j
].flags
);
10628 if (j
>= ARRAY_SIZE (cpu_arch
))
10630 /* Disable an ISA extension. */
10631 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
10632 if (strcmp (arch
, cpu_noarch
[j
].name
) == 0)
10634 i386_cpu_flags flags
;
10636 flags
= cpu_flags_and_not (cpu_arch_flags
,
10637 cpu_noarch
[j
].flags
);
10638 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
10640 if (cpu_sub_arch_name
)
10642 char *name
= cpu_sub_arch_name
;
10643 cpu_sub_arch_name
= concat (arch
,
10644 (const char *) NULL
);
10648 cpu_sub_arch_name
= xstrdup (arch
);
10649 cpu_arch_flags
= flags
;
10650 cpu_arch_isa_flags
= flags
;
10655 if (j
>= ARRAY_SIZE (cpu_noarch
))
10656 j
= ARRAY_SIZE (cpu_arch
);
10659 if (j
>= ARRAY_SIZE (cpu_arch
))
10660 as_fatal (_("invalid -march= option: `%s'"), arg
);
10664 while (next
!= NULL
);
10670 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
10671 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
10673 if (strcmp (arg
, cpu_arch
[j
].name
) == 0)
10675 cpu_arch_tune_set
= 1;
10676 cpu_arch_tune
= cpu_arch
[j
].type
;
10677 cpu_arch_tune_flags
= cpu_arch
[j
].flags
;
10681 if (j
>= ARRAY_SIZE (cpu_arch
))
10682 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
10685 case OPTION_MMNEMONIC
:
10686 if (strcasecmp (arg
, "att") == 0)
10687 intel_mnemonic
= 0;
10688 else if (strcasecmp (arg
, "intel") == 0)
10689 intel_mnemonic
= 1;
10691 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg
);
10694 case OPTION_MSYNTAX
:
10695 if (strcasecmp (arg
, "att") == 0)
10697 else if (strcasecmp (arg
, "intel") == 0)
10700 as_fatal (_("invalid -msyntax= option: `%s'"), arg
);
10703 case OPTION_MINDEX_REG
:
10704 allow_index_reg
= 1;
10707 case OPTION_MNAKED_REG
:
10708 allow_naked_reg
= 1;
10711 case OPTION_MSSE2AVX
:
10715 case OPTION_MSSE_CHECK
:
10716 if (strcasecmp (arg
, "error") == 0)
10717 sse_check
= check_error
;
10718 else if (strcasecmp (arg
, "warning") == 0)
10719 sse_check
= check_warning
;
10720 else if (strcasecmp (arg
, "none") == 0)
10721 sse_check
= check_none
;
10723 as_fatal (_("invalid -msse-check= option: `%s'"), arg
);
10726 case OPTION_MOPERAND_CHECK
:
10727 if (strcasecmp (arg
, "error") == 0)
10728 operand_check
= check_error
;
10729 else if (strcasecmp (arg
, "warning") == 0)
10730 operand_check
= check_warning
;
10731 else if (strcasecmp (arg
, "none") == 0)
10732 operand_check
= check_none
;
10734 as_fatal (_("invalid -moperand-check= option: `%s'"), arg
);
10737 case OPTION_MAVXSCALAR
:
10738 if (strcasecmp (arg
, "128") == 0)
10739 avxscalar
= vex128
;
10740 else if (strcasecmp (arg
, "256") == 0)
10741 avxscalar
= vex256
;
10743 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg
);
10746 case OPTION_MADD_BND_PREFIX
:
10747 add_bnd_prefix
= 1;
10750 case OPTION_MEVEXLIG
:
10751 if (strcmp (arg
, "128") == 0)
10752 evexlig
= evexl128
;
10753 else if (strcmp (arg
, "256") == 0)
10754 evexlig
= evexl256
;
10755 else if (strcmp (arg
, "512") == 0)
10756 evexlig
= evexl512
;
10758 as_fatal (_("invalid -mevexlig= option: `%s'"), arg
);
10761 case OPTION_MEVEXRCIG
:
10762 if (strcmp (arg
, "rne") == 0)
10764 else if (strcmp (arg
, "rd") == 0)
10766 else if (strcmp (arg
, "ru") == 0)
10768 else if (strcmp (arg
, "rz") == 0)
10771 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg
);
10774 case OPTION_MEVEXWIG
:
10775 if (strcmp (arg
, "0") == 0)
10777 else if (strcmp (arg
, "1") == 0)
10780 as_fatal (_("invalid -mevexwig= option: `%s'"), arg
);
10783 # if defined (TE_PE) || defined (TE_PEP)
10784 case OPTION_MBIG_OBJ
:
10789 case OPTION_MOMIT_LOCK_PREFIX
:
10790 if (strcasecmp (arg
, "yes") == 0)
10791 omit_lock_prefix
= 1;
10792 else if (strcasecmp (arg
, "no") == 0)
10793 omit_lock_prefix
= 0;
10795 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg
);
10798 case OPTION_MFENCE_AS_LOCK_ADD
:
10799 if (strcasecmp (arg
, "yes") == 0)
10801 else if (strcasecmp (arg
, "no") == 0)
10804 as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg
);
10807 case OPTION_MRELAX_RELOCATIONS
:
10808 if (strcasecmp (arg
, "yes") == 0)
10809 generate_relax_relocations
= 1;
10810 else if (strcasecmp (arg
, "no") == 0)
10811 generate_relax_relocations
= 0;
10813 as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg
);
10816 case OPTION_MAMD64
:
10820 case OPTION_MINTEL64
:
10828 /* Turn off -Os. */
10829 optimize_for_space
= 0;
10831 else if (*arg
== 's')
10833 optimize_for_space
= 1;
10834 /* Turn on all encoding optimizations. */
10839 optimize
= atoi (arg
);
10840 /* Turn off -Os. */
10841 optimize_for_space
= 0;
10851 #define MESSAGE_TEMPLATE \
10855 output_message (FILE *stream
, char *p
, char *message
, char *start
,
10856 int *left_p
, const char *name
, int len
)
10858 int size
= sizeof (MESSAGE_TEMPLATE
);
10859 int left
= *left_p
;
10861 /* Reserve 2 spaces for ", " or ",\0" */
10864 /* Check if there is any room. */
10872 p
= mempcpy (p
, name
, len
);
10876 /* Output the current message now and start a new one. */
10879 fprintf (stream
, "%s\n", message
);
10881 left
= size
- (start
- message
) - len
- 2;
10883 gas_assert (left
>= 0);
10885 p
= mempcpy (p
, name
, len
);
10893 show_arch (FILE *stream
, int ext
, int check
)
10895 static char message
[] = MESSAGE_TEMPLATE
;
10896 char *start
= message
+ 27;
10898 int size
= sizeof (MESSAGE_TEMPLATE
);
10905 left
= size
- (start
- message
);
10906 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
10908 /* Should it be skipped? */
10909 if (cpu_arch
[j
].skip
)
10912 name
= cpu_arch
[j
].name
;
10913 len
= cpu_arch
[j
].len
;
10916 /* It is an extension. Skip if we aren't asked to show it. */
10927 /* It is an processor. Skip if we show only extension. */
10930 else if (check
&& ! cpu_arch
[j
].flags
.bitfield
.cpui386
)
10932 /* It is an impossible processor - skip. */
10936 p
= output_message (stream
, p
, message
, start
, &left
, name
, len
);
10939 /* Display disabled extensions. */
10941 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
10943 name
= cpu_noarch
[j
].name
;
10944 len
= cpu_noarch
[j
].len
;
10945 p
= output_message (stream
, p
, message
, start
, &left
, name
,
10950 fprintf (stream
, "%s\n", message
);
10954 md_show_usage (FILE *stream
)
10956 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10957 fprintf (stream
, _("\
10959 -V print assembler version number\n\
10962 fprintf (stream
, _("\
10963 -n Do not optimize code alignment\n\
10964 -q quieten some warnings\n"));
10965 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10966 fprintf (stream
, _("\
10969 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10970 || defined (TE_PE) || defined (TE_PEP))
10971 fprintf (stream
, _("\
10972 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
10974 #ifdef SVR4_COMMENT_CHARS
10975 fprintf (stream
, _("\
10976 --divide do not treat `/' as a comment character\n"));
10978 fprintf (stream
, _("\
10979 --divide ignored\n"));
10981 fprintf (stream
, _("\
10982 -march=CPU[,+EXTENSION...]\n\
10983 generate code for CPU and EXTENSION, CPU is one of:\n"));
10984 show_arch (stream
, 0, 1);
10985 fprintf (stream
, _("\
10986 EXTENSION is combination of:\n"));
10987 show_arch (stream
, 1, 0);
10988 fprintf (stream
, _("\
10989 -mtune=CPU optimize for CPU, CPU is one of:\n"));
10990 show_arch (stream
, 0, 0);
10991 fprintf (stream
, _("\
10992 -msse2avx encode SSE instructions with VEX prefix\n"));
10993 fprintf (stream
, _("\
10994 -msse-check=[none|error|warning]\n\
10995 check SSE instructions\n"));
10996 fprintf (stream
, _("\
10997 -moperand-check=[none|error|warning]\n\
10998 check operand combinations for validity\n"));
10999 fprintf (stream
, _("\
11000 -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n\
11002 fprintf (stream
, _("\
11003 -mevexlig=[128|256|512] encode scalar EVEX instructions with specific vector\n\
11005 fprintf (stream
, _("\
11006 -mevexwig=[0|1] encode EVEX instructions with specific EVEX.W value\n\
11007 for EVEX.W bit ignored instructions\n"));
11008 fprintf (stream
, _("\
11009 -mevexrcig=[rne|rd|ru|rz]\n\
11010 encode EVEX instructions with specific EVEX.RC value\n\
11011 for SAE-only ignored instructions\n"));
11012 fprintf (stream
, _("\
11013 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
11014 fprintf (stream
, _("\
11015 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
11016 fprintf (stream
, _("\
11017 -mindex-reg support pseudo index registers\n"));
11018 fprintf (stream
, _("\
11019 -mnaked-reg don't require `%%' prefix for registers\n"));
11020 fprintf (stream
, _("\
11021 -madd-bnd-prefix add BND prefix for all valid branches\n"));
11022 fprintf (stream
, _("\
11023 -mshared disable branch optimization for shared code\n"));
11024 # if defined (TE_PE) || defined (TE_PEP)
11025 fprintf (stream
, _("\
11026 -mbig-obj generate big object files\n"));
11028 fprintf (stream
, _("\
11029 -momit-lock-prefix=[no|yes]\n\
11030 strip all lock prefixes\n"));
11031 fprintf (stream
, _("\
11032 -mfence-as-lock-add=[no|yes]\n\
11033 encode lfence, mfence and sfence as\n\
11034 lock addl $0x0, (%%{re}sp)\n"));
11035 fprintf (stream
, _("\
11036 -mrelax-relocations=[no|yes]\n\
11037 generate relax relocations\n"));
11038 fprintf (stream
, _("\
11039 -mamd64 accept only AMD64 ISA\n"));
11040 fprintf (stream
, _("\
11041 -mintel64 accept only Intel64 ISA\n"));
11044 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
11045 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
11046 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
11048 /* Pick the target format to use. */
11051 i386_target_format (void)
11053 if (!strncmp (default_arch
, "x86_64", 6))
11055 update_code_flag (CODE_64BIT
, 1);
11056 if (default_arch
[6] == '\0')
11057 x86_elf_abi
= X86_64_ABI
;
11059 x86_elf_abi
= X86_64_X32_ABI
;
11061 else if (!strcmp (default_arch
, "i386"))
11062 update_code_flag (CODE_32BIT
, 1);
11063 else if (!strcmp (default_arch
, "iamcu"))
11065 update_code_flag (CODE_32BIT
, 1);
11066 if (cpu_arch_isa
== PROCESSOR_UNKNOWN
)
11068 static const i386_cpu_flags iamcu_flags
= CPU_IAMCU_FLAGS
;
11069 cpu_arch_name
= "iamcu";
11070 cpu_sub_arch_name
= NULL
;
11071 cpu_arch_flags
= iamcu_flags
;
11072 cpu_arch_isa
= PROCESSOR_IAMCU
;
11073 cpu_arch_isa_flags
= iamcu_flags
;
11074 if (!cpu_arch_tune_set
)
11076 cpu_arch_tune
= cpu_arch_isa
;
11077 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
11080 else if (cpu_arch_isa
!= PROCESSOR_IAMCU
)
11081 as_fatal (_("Intel MCU doesn't support `%s' architecture"),
11085 as_fatal (_("unknown architecture"));
11087 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
11088 cpu_arch_isa_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
11089 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
11090 cpu_arch_tune_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
11092 switch (OUTPUT_FLAVOR
)
11094 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
11095 case bfd_target_aout_flavour
:
11096 return AOUT_TARGET_FORMAT
;
11098 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
11099 # if defined (TE_PE) || defined (TE_PEP)
11100 case bfd_target_coff_flavour
:
11101 if (flag_code
== CODE_64BIT
)
11102 return use_big_obj
? "pe-bigobj-x86-64" : "pe-x86-64";
11105 # elif defined (TE_GO32)
11106 case bfd_target_coff_flavour
:
11107 return "coff-go32";
11109 case bfd_target_coff_flavour
:
11110 return "coff-i386";
11113 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
11114 case bfd_target_elf_flavour
:
11116 const char *format
;
11118 switch (x86_elf_abi
)
11121 format
= ELF_TARGET_FORMAT
;
11124 use_rela_relocations
= 1;
11126 format
= ELF_TARGET_FORMAT64
;
11128 case X86_64_X32_ABI
:
11129 use_rela_relocations
= 1;
11131 disallow_64bit_reloc
= 1;
11132 format
= ELF_TARGET_FORMAT32
;
11135 if (cpu_arch_isa
== PROCESSOR_L1OM
)
11137 if (x86_elf_abi
!= X86_64_ABI
)
11138 as_fatal (_("Intel L1OM is 64bit only"));
11139 return ELF_TARGET_L1OM_FORMAT
;
11141 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
11143 if (x86_elf_abi
!= X86_64_ABI
)
11144 as_fatal (_("Intel K1OM is 64bit only"));
11145 return ELF_TARGET_K1OM_FORMAT
;
11147 else if (cpu_arch_isa
== PROCESSOR_IAMCU
)
11149 if (x86_elf_abi
!= I386_ABI
)
11150 as_fatal (_("Intel MCU is 32bit only"));
11151 return ELF_TARGET_IAMCU_FORMAT
;
11157 #if defined (OBJ_MACH_O)
11158 case bfd_target_mach_o_flavour
:
11159 if (flag_code
== CODE_64BIT
)
11161 use_rela_relocations
= 1;
11163 return "mach-o-x86-64";
11166 return "mach-o-i386";
11174 #endif /* OBJ_MAYBE_ more than one */
11177 md_undefined_symbol (char *name
)
11179 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
11180 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
11181 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
11182 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
11186 if (symbol_find (name
))
11187 as_bad (_("GOT already in symbol table"));
11188 GOT_symbol
= symbol_new (name
, undefined_section
,
11189 (valueT
) 0, &zero_address_frag
);
11196 /* Round up a section size to the appropriate boundary. */
11199 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
11201 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
11202 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
11204 /* For a.out, force the section size to be aligned. If we don't do
11205 this, BFD will align it for us, but it will not write out the
11206 final bytes of the section. This may be a bug in BFD, but it is
11207 easier to fix it here since that is how the other a.out targets
11211 align
= bfd_get_section_alignment (stdoutput
, segment
);
11212 size
= ((size
+ (1 << align
) - 1) & (-((valueT
) 1 << align
)));
11219 /* On the i386, PC-relative offsets are relative to the start of the
11220 next instruction. That is, the address of the offset, plus its
11221 size, since the offset is always the last part of the insn. */
11224 md_pcrel_from (fixS
*fixP
)
11226 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
11232 s_bss (int ignore ATTRIBUTE_UNUSED
)
11236 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11238 obj_elf_section_change_hook ();
11240 temp
= get_absolute_expression ();
11241 subseg_set (bss_section
, (subsegT
) temp
);
11242 demand_empty_rest_of_line ();
11248 i386_validate_fix (fixS
*fixp
)
11250 if (fixp
->fx_subsy
)
11252 if (fixp
->fx_subsy
== GOT_symbol
)
11254 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
11258 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11259 if (fixp
->fx_tcbit2
)
11260 fixp
->fx_r_type
= (fixp
->fx_tcbit
11261 ? BFD_RELOC_X86_64_REX_GOTPCRELX
11262 : BFD_RELOC_X86_64_GOTPCRELX
);
11265 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
11270 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
11272 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
11274 fixp
->fx_subsy
= 0;
11277 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11278 else if (!object_64bit
)
11280 if (fixp
->fx_r_type
== BFD_RELOC_386_GOT32
11281 && fixp
->fx_tcbit2
)
11282 fixp
->fx_r_type
= BFD_RELOC_386_GOT32X
;
11288 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
11291 bfd_reloc_code_real_type code
;
11293 switch (fixp
->fx_r_type
)
11295 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11296 case BFD_RELOC_SIZE32
:
11297 case BFD_RELOC_SIZE64
:
11298 if (S_IS_DEFINED (fixp
->fx_addsy
)
11299 && !S_IS_EXTERNAL (fixp
->fx_addsy
))
11301 /* Resolve size relocation against local symbol to size of
11302 the symbol plus addend. */
11303 valueT value
= S_GET_SIZE (fixp
->fx_addsy
) + fixp
->fx_offset
;
11304 if (fixp
->fx_r_type
== BFD_RELOC_SIZE32
11305 && !fits_in_unsigned_long (value
))
11306 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
11307 _("symbol size computation overflow"));
11308 fixp
->fx_addsy
= NULL
;
11309 fixp
->fx_subsy
= NULL
;
11310 md_apply_fix (fixp
, (valueT
*) &value
, NULL
);
11314 /* Fall through. */
11316 case BFD_RELOC_X86_64_PLT32
:
11317 case BFD_RELOC_X86_64_GOT32
:
11318 case BFD_RELOC_X86_64_GOTPCREL
:
11319 case BFD_RELOC_X86_64_GOTPCRELX
:
11320 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
11321 case BFD_RELOC_386_PLT32
:
11322 case BFD_RELOC_386_GOT32
:
11323 case BFD_RELOC_386_GOT32X
:
11324 case BFD_RELOC_386_GOTOFF
:
11325 case BFD_RELOC_386_GOTPC
:
11326 case BFD_RELOC_386_TLS_GD
:
11327 case BFD_RELOC_386_TLS_LDM
:
11328 case BFD_RELOC_386_TLS_LDO_32
:
11329 case BFD_RELOC_386_TLS_IE_32
:
11330 case BFD_RELOC_386_TLS_IE
:
11331 case BFD_RELOC_386_TLS_GOTIE
:
11332 case BFD_RELOC_386_TLS_LE_32
:
11333 case BFD_RELOC_386_TLS_LE
:
11334 case BFD_RELOC_386_TLS_GOTDESC
:
11335 case BFD_RELOC_386_TLS_DESC_CALL
:
11336 case BFD_RELOC_X86_64_TLSGD
:
11337 case BFD_RELOC_X86_64_TLSLD
:
11338 case BFD_RELOC_X86_64_DTPOFF32
:
11339 case BFD_RELOC_X86_64_DTPOFF64
:
11340 case BFD_RELOC_X86_64_GOTTPOFF
:
11341 case BFD_RELOC_X86_64_TPOFF32
:
11342 case BFD_RELOC_X86_64_TPOFF64
:
11343 case BFD_RELOC_X86_64_GOTOFF64
:
11344 case BFD_RELOC_X86_64_GOTPC32
:
11345 case BFD_RELOC_X86_64_GOT64
:
11346 case BFD_RELOC_X86_64_GOTPCREL64
:
11347 case BFD_RELOC_X86_64_GOTPC64
:
11348 case BFD_RELOC_X86_64_GOTPLT64
:
11349 case BFD_RELOC_X86_64_PLTOFF64
:
11350 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
11351 case BFD_RELOC_X86_64_TLSDESC_CALL
:
11352 case BFD_RELOC_RVA
:
11353 case BFD_RELOC_VTABLE_ENTRY
:
11354 case BFD_RELOC_VTABLE_INHERIT
:
11356 case BFD_RELOC_32_SECREL
:
11358 code
= fixp
->fx_r_type
;
11360 case BFD_RELOC_X86_64_32S
:
11361 if (!fixp
->fx_pcrel
)
11363 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
11364 code
= fixp
->fx_r_type
;
11367 /* Fall through. */
11369 if (fixp
->fx_pcrel
)
11371 switch (fixp
->fx_size
)
11374 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
11375 _("can not do %d byte pc-relative relocation"),
11377 code
= BFD_RELOC_32_PCREL
;
11379 case 1: code
= BFD_RELOC_8_PCREL
; break;
11380 case 2: code
= BFD_RELOC_16_PCREL
; break;
11381 case 4: code
= BFD_RELOC_32_PCREL
; break;
11383 case 8: code
= BFD_RELOC_64_PCREL
; break;
11389 switch (fixp
->fx_size
)
11392 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
11393 _("can not do %d byte relocation"),
11395 code
= BFD_RELOC_32
;
11397 case 1: code
= BFD_RELOC_8
; break;
11398 case 2: code
= BFD_RELOC_16
; break;
11399 case 4: code
= BFD_RELOC_32
; break;
11401 case 8: code
= BFD_RELOC_64
; break;
11408 if ((code
== BFD_RELOC_32
11409 || code
== BFD_RELOC_32_PCREL
11410 || code
== BFD_RELOC_X86_64_32S
)
11412 && fixp
->fx_addsy
== GOT_symbol
)
11415 code
= BFD_RELOC_386_GOTPC
;
11417 code
= BFD_RELOC_X86_64_GOTPC32
;
11419 if ((code
== BFD_RELOC_64
|| code
== BFD_RELOC_64_PCREL
)
11421 && fixp
->fx_addsy
== GOT_symbol
)
11423 code
= BFD_RELOC_X86_64_GOTPC64
;
11426 rel
= XNEW (arelent
);
11427 rel
->sym_ptr_ptr
= XNEW (asymbol
*);
11428 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
11430 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
11432 if (!use_rela_relocations
)
11434 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
11435 vtable entry to be used in the relocation's section offset. */
11436 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
11437 rel
->address
= fixp
->fx_offset
;
11438 #if defined (OBJ_COFF) && defined (TE_PE)
11439 else if (fixp
->fx_addsy
&& S_IS_WEAK (fixp
->fx_addsy
))
11440 rel
->addend
= fixp
->fx_addnumber
- (S_GET_VALUE (fixp
->fx_addsy
) * 2);
11445 /* Use the rela in 64bit mode. */
11448 if (disallow_64bit_reloc
)
11451 case BFD_RELOC_X86_64_DTPOFF64
:
11452 case BFD_RELOC_X86_64_TPOFF64
:
11453 case BFD_RELOC_64_PCREL
:
11454 case BFD_RELOC_X86_64_GOTOFF64
:
11455 case BFD_RELOC_X86_64_GOT64
:
11456 case BFD_RELOC_X86_64_GOTPCREL64
:
11457 case BFD_RELOC_X86_64_GOTPC64
:
11458 case BFD_RELOC_X86_64_GOTPLT64
:
11459 case BFD_RELOC_X86_64_PLTOFF64
:
11460 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
11461 _("cannot represent relocation type %s in x32 mode"),
11462 bfd_get_reloc_code_name (code
));
11468 if (!fixp
->fx_pcrel
)
11469 rel
->addend
= fixp
->fx_offset
;
11473 case BFD_RELOC_X86_64_PLT32
:
11474 case BFD_RELOC_X86_64_GOT32
:
11475 case BFD_RELOC_X86_64_GOTPCREL
:
11476 case BFD_RELOC_X86_64_GOTPCRELX
:
11477 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
11478 case BFD_RELOC_X86_64_TLSGD
:
11479 case BFD_RELOC_X86_64_TLSLD
:
11480 case BFD_RELOC_X86_64_GOTTPOFF
:
11481 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
11482 case BFD_RELOC_X86_64_TLSDESC_CALL
:
11483 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
11486 rel
->addend
= (section
->vma
11488 + fixp
->fx_addnumber
11489 + md_pcrel_from (fixp
));
11494 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
11495 if (rel
->howto
== NULL
)
11497 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
11498 _("cannot represent relocation type %s"),
11499 bfd_get_reloc_code_name (code
));
11500 /* Set howto to a garbage value so that we can keep going. */
11501 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
11502 gas_assert (rel
->howto
!= NULL
);
11508 #include "tc-i386-intel.c"
11511 tc_x86_parse_to_dw2regnum (expressionS
*exp
)
11513 int saved_naked_reg
;
11514 char saved_register_dot
;
11516 saved_naked_reg
= allow_naked_reg
;
11517 allow_naked_reg
= 1;
11518 saved_register_dot
= register_chars
['.'];
11519 register_chars
['.'] = '.';
11520 allow_pseudo_reg
= 1;
11521 expression_and_evaluate (exp
);
11522 allow_pseudo_reg
= 0;
11523 register_chars
['.'] = saved_register_dot
;
11524 allow_naked_reg
= saved_naked_reg
;
11526 if (exp
->X_op
== O_register
&& exp
->X_add_number
>= 0)
11528 if ((addressT
) exp
->X_add_number
< i386_regtab_size
)
11530 exp
->X_op
= O_constant
;
11531 exp
->X_add_number
= i386_regtab
[exp
->X_add_number
]
11532 .dw2_regnum
[flag_code
>> 1];
11535 exp
->X_op
= O_illegal
;
11540 tc_x86_frame_initial_instructions (void)
11542 static unsigned int sp_regno
[2];
11544 if (!sp_regno
[flag_code
>> 1])
11546 char *saved_input
= input_line_pointer
;
11547 char sp
[][4] = {"esp", "rsp"};
11550 input_line_pointer
= sp
[flag_code
>> 1];
11551 tc_x86_parse_to_dw2regnum (&exp
);
11552 gas_assert (exp
.X_op
== O_constant
);
11553 sp_regno
[flag_code
>> 1] = exp
.X_add_number
;
11554 input_line_pointer
= saved_input
;
11557 cfi_add_CFA_def_cfa (sp_regno
[flag_code
>> 1], -x86_cie_data_alignment
);
11558 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
11562 x86_dwarf2_addr_size (void)
11564 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
11565 if (x86_elf_abi
== X86_64_X32_ABI
)
11568 return bfd_arch_bits_per_address (stdoutput
) / 8;
11572 i386_elf_section_type (const char *str
, size_t len
)
11574 if (flag_code
== CODE_64BIT
11575 && len
== sizeof ("unwind") - 1
11576 && strncmp (str
, "unwind", 6) == 0)
11577 return SHT_X86_64_UNWIND
;
11584 i386_solaris_fix_up_eh_frame (segT sec
)
11586 if (flag_code
== CODE_64BIT
)
11587 elf_section_type (sec
) = SHT_X86_64_UNWIND
;
11593 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
11597 exp
.X_op
= O_secrel
;
11598 exp
.X_add_symbol
= symbol
;
11599 exp
.X_add_number
= 0;
11600 emit_expr (&exp
, size
);
11604 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11605 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
11608 x86_64_section_letter (int letter
, const char **ptr_msg
)
11610 if (flag_code
== CODE_64BIT
)
11613 return SHF_X86_64_LARGE
;
11615 *ptr_msg
= _("bad .section directive: want a,l,w,x,M,S,G,T in string");
11618 *ptr_msg
= _("bad .section directive: want a,w,x,M,S,G,T in string");
11623 x86_64_section_word (char *str
, size_t len
)
11625 if (len
== 5 && flag_code
== CODE_64BIT
&& CONST_STRNEQ (str
, "large"))
11626 return SHF_X86_64_LARGE
;
11632 handle_large_common (int small ATTRIBUTE_UNUSED
)
11634 if (flag_code
!= CODE_64BIT
)
11636 s_comm_internal (0, elf_common_parse
);
11637 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
11641 static segT lbss_section
;
11642 asection
*saved_com_section_ptr
= elf_com_section_ptr
;
11643 asection
*saved_bss_section
= bss_section
;
11645 if (lbss_section
== NULL
)
11647 flagword applicable
;
11648 segT seg
= now_seg
;
11649 subsegT subseg
= now_subseg
;
11651 /* The .lbss section is for local .largecomm symbols. */
11652 lbss_section
= subseg_new (".lbss", 0);
11653 applicable
= bfd_applicable_section_flags (stdoutput
);
11654 bfd_set_section_flags (stdoutput
, lbss_section
,
11655 applicable
& SEC_ALLOC
);
11656 seg_info (lbss_section
)->bss
= 1;
11658 subseg_set (seg
, subseg
);
11661 elf_com_section_ptr
= &_bfd_elf_large_com_section
;
11662 bss_section
= lbss_section
;
11664 s_comm_internal (0, elf_common_parse
);
11666 elf_com_section_ptr
= saved_com_section_ptr
;
11667 bss_section
= saved_bss_section
;
11670 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */