1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright (C) 1989-2016 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 /* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
23 x86_64 support by Jan Hubicka (jh@suse.cz)
24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
29 #include "safe-ctype.h"
31 #include "dwarf2dbg.h"
32 #include "dw2gencfi.h"
33 #include "elf/x86-64.h"
34 #include "opcodes/i386-init.h"
36 #ifndef REGISTER_WARNINGS
37 #define REGISTER_WARNINGS 1
40 #ifndef INFER_ADDR_PREFIX
41 #define INFER_ADDR_PREFIX 1
45 #define DEFAULT_ARCH "i386"
50 #define INLINE __inline__
56 /* Prefixes will be emitted in the order defined below.
57 WAIT_PREFIX must be the first prefix since FWAIT is really is an
58 instruction, and so must come before any prefixes.
59 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
60 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
66 #define HLE_PREFIX REP_PREFIX
67 #define BND_PREFIX REP_PREFIX
69 #define REX_PREFIX 6 /* must come last. */
70 #define MAX_PREFIXES 7 /* max prefixes per opcode */
72 /* we define the syntax here (modulo base,index,scale syntax) */
73 #define REGISTER_PREFIX '%'
74 #define IMMEDIATE_PREFIX '$'
75 #define ABSOLUTE_PREFIX '*'
77 /* these are the instruction mnemonic suffixes in AT&T syntax or
78 memory operand size in Intel syntax. */
79 #define WORD_MNEM_SUFFIX 'w'
80 #define BYTE_MNEM_SUFFIX 'b'
81 #define SHORT_MNEM_SUFFIX 's'
82 #define LONG_MNEM_SUFFIX 'l'
83 #define QWORD_MNEM_SUFFIX 'q'
84 #define XMMWORD_MNEM_SUFFIX 'x'
85 #define YMMWORD_MNEM_SUFFIX 'y'
86 #define ZMMWORD_MNEM_SUFFIX 'z'
87 /* Intel Syntax. Use a non-ascii letter since since it never appears
89 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
91 #define END_OF_INSN '\0'
94 'templates' is for grouping together 'template' structures for opcodes
95 of the same name. This is only used for storing the insns in the grand
96 ole hash table of insns.
97 The templates themselves start at START and range up to (but not including)
102 const insn_template
*start
;
103 const insn_template
*end
;
107 /* 386 operand encoding bytes: see 386 book for details of this. */
110 unsigned int regmem
; /* codes register or memory operand */
111 unsigned int reg
; /* codes register operand (or extended opcode) */
112 unsigned int mode
; /* how to interpret regmem & reg */
116 /* x86-64 extension prefix. */
117 typedef int rex_byte
;
119 /* 386 opcode byte to code indirect addressing. */
128 /* x86 arch names, types and features */
131 const char *name
; /* arch name */
132 unsigned int len
; /* arch string length */
133 enum processor_type type
; /* arch type */
134 i386_cpu_flags flags
; /* cpu feature flags */
135 unsigned int skip
; /* show_arch should skip this. */
139 /* Used to turn off indicated flags. */
142 const char *name
; /* arch name */
143 unsigned int len
; /* arch string length */
144 i386_cpu_flags flags
; /* cpu feature flags */
148 static void update_code_flag (int, int);
149 static void set_code_flag (int);
150 static void set_16bit_gcc_code_flag (int);
151 static void set_intel_syntax (int);
152 static void set_intel_mnemonic (int);
153 static void set_allow_index_reg (int);
154 static void set_check (int);
155 static void set_cpu_arch (int);
157 static void pe_directive_secrel (int);
159 static void signed_cons (int);
160 static char *output_invalid (int c
);
161 static int i386_finalize_immediate (segT
, expressionS
*, i386_operand_type
,
163 static int i386_finalize_displacement (segT
, expressionS
*, i386_operand_type
,
165 static int i386_att_operand (char *);
166 static int i386_intel_operand (char *, int);
167 static int i386_intel_simplify (expressionS
*);
168 static int i386_intel_parse_name (const char *, expressionS
*);
169 static const reg_entry
*parse_register (char *, char **);
170 static char *parse_insn (char *, char *);
171 static char *parse_operands (char *, const char *);
172 static void swap_operands (void);
173 static void swap_2_operands (int, int);
174 static void optimize_imm (void);
175 static void optimize_disp (void);
176 static const insn_template
*match_template (char);
177 static int check_string (void);
178 static int process_suffix (void);
179 static int check_byte_reg (void);
180 static int check_long_reg (void);
181 static int check_qword_reg (void);
182 static int check_word_reg (void);
183 static int finalize_imm (void);
184 static int process_operands (void);
185 static const seg_entry
*build_modrm_byte (void);
186 static void output_insn (void);
187 static void output_imm (fragS
*, offsetT
);
188 static void output_disp (fragS
*, offsetT
);
190 static void s_bss (int);
192 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
193 static void handle_large_common (int small ATTRIBUTE_UNUSED
);
196 static const char *default_arch
= DEFAULT_ARCH
;
198 /* This struct describes rounding control and SAE in the instruction. */
212 static struct RC_Operation rc_op
;
214 /* The struct describes masking, applied to OPERAND in the instruction.
215 MASK is a pointer to the corresponding mask register. ZEROING tells
216 whether merging or zeroing mask is used. */
217 struct Mask_Operation
219 const reg_entry
*mask
;
220 unsigned int zeroing
;
221 /* The operand where this operation is associated. */
225 static struct Mask_Operation mask_op
;
227 /* The struct describes broadcasting, applied to OPERAND. FACTOR is
229 struct Broadcast_Operation
231 /* Type of broadcast: no broadcast, {1to8}, or {1to16}. */
234 /* Index of broadcasted operand. */
238 static struct Broadcast_Operation broadcast_op
;
243 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
244 unsigned char bytes
[4];
246 /* Destination or source register specifier. */
247 const reg_entry
*register_specifier
;
250 /* 'md_assemble ()' gathers together information and puts it into a
257 const reg_entry
*regs
;
262 operand_size_mismatch
,
263 operand_type_mismatch
,
264 register_type_mismatch
,
265 number_of_operands_mismatch
,
266 invalid_instruction_suffix
,
269 unsupported_with_intel_mnemonic
,
272 invalid_vsib_address
,
273 invalid_vector_register_set
,
274 unsupported_vector_index_register
,
275 unsupported_broadcast
,
276 broadcast_not_on_src_operand
,
279 mask_not_on_destination
,
282 rc_sae_operand_not_last_imm
,
283 invalid_register_operand
,
289 /* TM holds the template for the insn were currently assembling. */
292 /* SUFFIX holds the instruction size suffix for byte, word, dword
293 or qword, if given. */
296 /* OPERANDS gives the number of given operands. */
297 unsigned int operands
;
299 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
300 of given register, displacement, memory operands and immediate
302 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
304 /* TYPES [i] is the type (see above #defines) which tells us how to
305 use OP[i] for the corresponding operand. */
306 i386_operand_type types
[MAX_OPERANDS
];
308 /* Displacement expression, immediate expression, or register for each
310 union i386_op op
[MAX_OPERANDS
];
312 /* Flags for operands. */
313 unsigned int flags
[MAX_OPERANDS
];
314 #define Operand_PCrel 1
316 /* Relocation type for operand */
317 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
319 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
320 the base index byte below. */
321 const reg_entry
*base_reg
;
322 const reg_entry
*index_reg
;
323 unsigned int log2_scale_factor
;
325 /* SEG gives the seg_entries of this insn. They are zero unless
326 explicit segment overrides are given. */
327 const seg_entry
*seg
[2];
329 /* Copied first memory operand string, for re-checking. */
332 /* PREFIX holds all the given prefix opcodes (usually null).
333 PREFIXES is the number of prefix opcodes. */
334 unsigned int prefixes
;
335 unsigned char prefix
[MAX_PREFIXES
];
337 /* RM and SIB are the modrm byte and the sib byte where the
338 addressing modes of this insn are encoded. */
345 /* Masking attributes. */
346 struct Mask_Operation
*mask
;
348 /* Rounding control and SAE attributes. */
349 struct RC_Operation
*rounding
;
351 /* Broadcasting attributes. */
352 struct Broadcast_Operation
*broadcast
;
354 /* Compressed disp8*N attribute. */
355 unsigned int memshift
;
357 /* Swap operand in encoding. */
358 unsigned int swap_operand
;
360 /* Prefer 8bit or 32bit displacement in encoding. */
363 disp_encoding_default
= 0,
369 const char *rep_prefix
;
372 const char *hle_prefix
;
374 /* Have BND prefix. */
375 const char *bnd_prefix
;
377 /* Need VREX to support upper 16 registers. */
381 enum i386_error error
;
384 typedef struct _i386_insn i386_insn
;
386 /* Link RC type with corresponding string, that'll be looked for in
395 static const struct RC_name RC_NamesTable
[] =
397 { rne
, STRING_COMMA_LEN ("rn-sae") },
398 { rd
, STRING_COMMA_LEN ("rd-sae") },
399 { ru
, STRING_COMMA_LEN ("ru-sae") },
400 { rz
, STRING_COMMA_LEN ("rz-sae") },
401 { saeonly
, STRING_COMMA_LEN ("sae") },
404 /* List of chars besides those in app.c:symbol_chars that can start an
405 operand. Used to prevent the scrubber eating vital white-space. */
406 const char extra_symbol_chars
[] = "*%-([{"
415 #if (defined (TE_I386AIX) \
416 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
417 && !defined (TE_GNU) \
418 && !defined (TE_LINUX) \
419 && !defined (TE_NACL) \
420 && !defined (TE_NETWARE) \
421 && !defined (TE_FreeBSD) \
422 && !defined (TE_DragonFly) \
423 && !defined (TE_NetBSD)))
424 /* This array holds the chars that always start a comment. If the
425 pre-processor is disabled, these aren't very useful. The option
426 --divide will remove '/' from this list. */
427 const char *i386_comment_chars
= "#/";
428 #define SVR4_COMMENT_CHARS 1
429 #define PREFIX_SEPARATOR '\\'
432 const char *i386_comment_chars
= "#";
433 #define PREFIX_SEPARATOR '/'
436 /* This array holds the chars that only start a comment at the beginning of
437 a line. If the line seems to have the form '# 123 filename'
438 .line and .file directives will appear in the pre-processed output.
439 Note that input_file.c hand checks for '#' at the beginning of the
440 first line of the input file. This is because the compiler outputs
441 #NO_APP at the beginning of its output.
442 Also note that comments started like this one will always work if
443 '/' isn't otherwise defined. */
444 const char line_comment_chars
[] = "#/";
446 const char line_separator_chars
[] = ";";
448 /* Chars that can be used to separate mant from exp in floating point
450 const char EXP_CHARS
[] = "eE";
452 /* Chars that mean this number is a floating point constant
455 const char FLT_CHARS
[] = "fFdDxX";
457 /* Tables for lexical analysis. */
458 static char mnemonic_chars
[256];
459 static char register_chars
[256];
460 static char operand_chars
[256];
461 static char identifier_chars
[256];
462 static char digit_chars
[256];
464 /* Lexical macros. */
465 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
466 #define is_operand_char(x) (operand_chars[(unsigned char) x])
467 #define is_register_char(x) (register_chars[(unsigned char) x])
468 #define is_space_char(x) ((x) == ' ')
469 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
470 #define is_digit_char(x) (digit_chars[(unsigned char) x])
472 /* All non-digit non-letter characters that may occur in an operand. */
473 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
475 /* md_assemble() always leaves the strings it's passed unaltered. To
476 effect this we maintain a stack of saved characters that we've smashed
477 with '\0's (indicating end of strings for various sub-fields of the
478 assembler instruction). */
479 static char save_stack
[32];
480 static char *save_stack_p
;
481 #define END_STRING_AND_SAVE(s) \
482 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
483 #define RESTORE_END_STRING(s) \
484 do { *(s) = *--save_stack_p; } while (0)
486 /* The instruction we're assembling. */
489 /* Possible templates for current insn. */
490 static const templates
*current_templates
;
492 /* Per instruction expressionS buffers: max displacements & immediates. */
493 static expressionS disp_expressions
[MAX_MEMORY_OPERANDS
];
494 static expressionS im_expressions
[MAX_IMMEDIATE_OPERANDS
];
496 /* Current operand we are working on. */
497 static int this_operand
= -1;
499 /* We support four different modes. FLAG_CODE variable is used to distinguish
507 static enum flag_code flag_code
;
508 static unsigned int object_64bit
;
509 static unsigned int disallow_64bit_reloc
;
510 static int use_rela_relocations
= 0;
512 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
513 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
514 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
516 /* The ELF ABI to use. */
524 static enum x86_elf_abi x86_elf_abi
= I386_ABI
;
527 #if defined (TE_PE) || defined (TE_PEP)
528 /* Use big object file format. */
529 static int use_big_obj
= 0;
532 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
533 /* 1 if generating code for a shared library. */
534 static int shared
= 0;
537 /* 1 for intel syntax,
539 static int intel_syntax
= 0;
541 /* 1 for Intel64 ISA,
545 /* 1 for intel mnemonic,
546 0 if att mnemonic. */
547 static int intel_mnemonic
= !SYSV386_COMPAT
;
549 /* 1 if support old (<= 2.8.1) versions of gcc. */
550 static int old_gcc
= OLDGCC_COMPAT
;
552 /* 1 if pseudo registers are permitted. */
553 static int allow_pseudo_reg
= 0;
555 /* 1 if register prefix % not required. */
556 static int allow_naked_reg
= 0;
558 /* 1 if the assembler should add BND prefix for all control-tranferring
559 instructions supporting it, even if this prefix wasn't specified
561 static int add_bnd_prefix
= 0;
563 /* 1 if pseudo index register, eiz/riz, is allowed . */
564 static int allow_index_reg
= 0;
566 /* 1 if the assembler should ignore LOCK prefix, even if it was
567 specified explicitly. */
568 static int omit_lock_prefix
= 0;
570 /* 1 if the assembler should encode lfence, mfence, and sfence as
571 "lock addl $0, (%{re}sp)". */
572 static int avoid_fence
= 0;
574 /* 1 if the assembler should generate relax relocations. */
576 static int generate_relax_relocations
577 = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS
;
579 static enum check_kind
585 sse_check
, operand_check
= check_warning
;
587 /* Register prefix used for error message. */
588 static const char *register_prefix
= "%";
590 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
591 leave, push, and pop instructions so that gcc has the same stack
592 frame as in 32 bit mode. */
593 static char stackop_size
= '\0';
595 /* Non-zero to optimize code alignment. */
596 int optimize_align_code
= 1;
598 /* Non-zero to quieten some warnings. */
599 static int quiet_warnings
= 0;
602 static const char *cpu_arch_name
= NULL
;
603 static char *cpu_sub_arch_name
= NULL
;
605 /* CPU feature flags. */
606 static i386_cpu_flags cpu_arch_flags
= CPU_UNKNOWN_FLAGS
;
608 /* If we have selected a cpu we are generating instructions for. */
609 static int cpu_arch_tune_set
= 0;
611 /* Cpu we are generating instructions for. */
612 enum processor_type cpu_arch_tune
= PROCESSOR_UNKNOWN
;
614 /* CPU feature flags of cpu we are generating instructions for. */
615 static i386_cpu_flags cpu_arch_tune_flags
;
617 /* CPU instruction set architecture used. */
618 enum processor_type cpu_arch_isa
= PROCESSOR_UNKNOWN
;
620 /* CPU feature flags of instruction set architecture used. */
621 i386_cpu_flags cpu_arch_isa_flags
;
623 /* If set, conditional jumps are not automatically promoted to handle
624 larger than a byte offset. */
625 static unsigned int no_cond_jump_promotion
= 0;
627 /* Encode SSE instructions with VEX prefix. */
628 static unsigned int sse2avx
;
630 /* Encode scalar AVX instructions with specific vector length. */
637 /* Encode scalar EVEX LIG instructions with specific vector length. */
645 /* Encode EVEX WIG instructions with specific evex.w. */
652 /* Value to encode in EVEX RC bits, for SAE-only instructions. */
653 static enum rc_type evexrcig
= rne
;
655 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
656 static symbolS
*GOT_symbol
;
658 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
659 unsigned int x86_dwarf2_return_column
;
661 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
662 int x86_cie_data_alignment
;
664 /* Interface to relax_segment.
665 There are 3 major relax states for 386 jump insns because the
666 different types of jumps add different sizes to frags when we're
667 figuring out what sort of jump to choose to reach a given label. */
670 #define UNCOND_JUMP 0
672 #define COND_JUMP86 2
677 #define SMALL16 (SMALL | CODE16)
679 #define BIG16 (BIG | CODE16)
683 #define INLINE __inline__
689 #define ENCODE_RELAX_STATE(type, size) \
690 ((relax_substateT) (((type) << 2) | (size)))
691 #define TYPE_FROM_RELAX_STATE(s) \
693 #define DISP_SIZE_FROM_RELAX_STATE(s) \
694 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
696 /* This table is used by relax_frag to promote short jumps to long
697 ones where necessary. SMALL (short) jumps may be promoted to BIG
698 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
699 don't allow a short jump in a 32 bit code segment to be promoted to
700 a 16 bit offset jump because it's slower (requires data size
701 prefix), and doesn't work, unless the destination is in the bottom
702 64k of the code segment (The top 16 bits of eip are zeroed). */
704 const relax_typeS md_relax_table
[] =
707 1) most positive reach of this state,
708 2) most negative reach of this state,
709 3) how many bytes this mode will have in the variable part of the frag
710 4) which index into the table to try if we can't fit into this one. */
712 /* UNCOND_JUMP states. */
713 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
714 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
715 /* dword jmp adds 4 bytes to frag:
716 0 extra opcode bytes, 4 displacement bytes. */
718 /* word jmp adds 2 byte2 to frag:
719 0 extra opcode bytes, 2 displacement bytes. */
722 /* COND_JUMP states. */
723 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
724 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
725 /* dword conditionals adds 5 bytes to frag:
726 1 extra opcode byte, 4 displacement bytes. */
728 /* word conditionals add 3 bytes to frag:
729 1 extra opcode byte, 2 displacement bytes. */
732 /* COND_JUMP86 states. */
733 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
734 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
735 /* dword conditionals adds 5 bytes to frag:
736 1 extra opcode byte, 4 displacement bytes. */
738 /* word conditionals add 4 bytes to frag:
739 1 displacement byte and a 3 byte long branch insn. */
743 static const arch_entry cpu_arch
[] =
745 /* Do not replace the first two entries - i386_target_format()
746 relies on them being there in this order. */
747 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32
,
748 CPU_GENERIC32_FLAGS
, 0 },
749 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64
,
750 CPU_GENERIC64_FLAGS
, 0 },
751 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN
,
753 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN
,
755 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN
,
757 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386
,
759 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486
,
761 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM
,
763 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO
,
765 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM
,
767 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO
,
768 CPU_PENTIUMPRO_FLAGS
, 0 },
769 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO
,
771 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO
,
773 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4
,
775 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA
,
777 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA
,
778 CPU_NOCONA_FLAGS
, 0 },
779 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE
,
781 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE
,
783 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2
,
784 CPU_CORE2_FLAGS
, 1 },
785 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2
,
786 CPU_CORE2_FLAGS
, 0 },
787 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7
,
788 CPU_COREI7_FLAGS
, 0 },
789 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM
,
791 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM
,
793 { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU
,
794 CPU_IAMCU_FLAGS
, 0 },
795 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6
,
797 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6
,
799 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON
,
800 CPU_ATHLON_FLAGS
, 0 },
801 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8
,
803 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8
,
805 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8
,
807 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10
,
808 CPU_AMDFAM10_FLAGS
, 0 },
809 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD
,
810 CPU_BDVER1_FLAGS
, 0 },
811 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD
,
812 CPU_BDVER2_FLAGS
, 0 },
813 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD
,
814 CPU_BDVER3_FLAGS
, 0 },
815 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD
,
816 CPU_BDVER4_FLAGS
, 0 },
817 { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER
,
818 CPU_ZNVER1_FLAGS
, 0 },
819 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT
,
820 CPU_BTVER1_FLAGS
, 0 },
821 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT
,
822 CPU_BTVER2_FLAGS
, 0 },
823 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN
,
825 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN
,
827 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN
,
829 { STRING_COMMA_LEN (".687"), PROCESSOR_UNKNOWN
,
831 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN
,
833 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN
,
835 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN
,
837 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN
,
839 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN
,
840 CPU_SSSE3_FLAGS
, 0 },
841 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN
,
842 CPU_SSE4_1_FLAGS
, 0 },
843 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN
,
844 CPU_SSE4_2_FLAGS
, 0 },
845 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN
,
846 CPU_SSE4_2_FLAGS
, 0 },
847 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN
,
849 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN
,
851 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN
,
852 CPU_AVX512F_FLAGS
, 0 },
853 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN
,
854 CPU_AVX512CD_FLAGS
, 0 },
855 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN
,
856 CPU_AVX512ER_FLAGS
, 0 },
857 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN
,
858 CPU_AVX512PF_FLAGS
, 0 },
859 { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN
,
860 CPU_AVX512DQ_FLAGS
, 0 },
861 { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN
,
862 CPU_AVX512BW_FLAGS
, 0 },
863 { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN
,
864 CPU_AVX512VL_FLAGS
, 0 },
865 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN
,
867 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN
,
868 CPU_VMFUNC_FLAGS
, 0 },
869 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN
,
871 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN
,
872 CPU_XSAVE_FLAGS
, 0 },
873 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN
,
874 CPU_XSAVEOPT_FLAGS
, 0 },
875 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN
,
876 CPU_XSAVEC_FLAGS
, 0 },
877 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN
,
878 CPU_XSAVES_FLAGS
, 0 },
879 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN
,
881 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN
,
882 CPU_PCLMUL_FLAGS
, 0 },
883 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN
,
884 CPU_PCLMUL_FLAGS
, 1 },
885 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN
,
886 CPU_FSGSBASE_FLAGS
, 0 },
887 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN
,
888 CPU_RDRND_FLAGS
, 0 },
889 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN
,
891 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN
,
893 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN
,
895 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN
,
897 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN
,
899 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN
,
901 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN
,
902 CPU_MOVBE_FLAGS
, 0 },
903 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN
,
905 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN
,
907 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN
,
908 CPU_LZCNT_FLAGS
, 0 },
909 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN
,
911 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN
,
913 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN
,
914 CPU_INVPCID_FLAGS
, 0 },
915 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN
,
916 CPU_CLFLUSH_FLAGS
, 0 },
917 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN
,
919 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN
,
920 CPU_SYSCALL_FLAGS
, 0 },
921 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN
,
922 CPU_RDTSCP_FLAGS
, 0 },
923 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN
,
924 CPU_3DNOW_FLAGS
, 0 },
925 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN
,
926 CPU_3DNOWA_FLAGS
, 0 },
927 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN
,
928 CPU_PADLOCK_FLAGS
, 0 },
929 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN
,
931 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN
,
933 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN
,
934 CPU_SSE4A_FLAGS
, 0 },
935 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN
,
937 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN
,
939 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN
,
941 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN
,
943 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN
,
944 CPU_RDSEED_FLAGS
, 0 },
945 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN
,
946 CPU_PRFCHW_FLAGS
, 0 },
947 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN
,
949 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN
,
951 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN
,
953 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN
,
954 CPU_CLFLUSHOPT_FLAGS
, 0 },
955 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN
,
956 CPU_PREFETCHWT1_FLAGS
, 0 },
957 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN
,
959 { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN
,
961 { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN
,
962 CPU_AVX512IFMA_FLAGS
, 0 },
963 { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN
,
964 CPU_AVX512VBMI_FLAGS
, 0 },
965 { STRING_COMMA_LEN (".avx512_4fmaps"), PROCESSOR_UNKNOWN
,
966 CPU_AVX512_4FMAPS_FLAGS
, 0 },
967 { STRING_COMMA_LEN (".avx512_4vnniw"), PROCESSOR_UNKNOWN
,
968 CPU_AVX512_4VNNIW_FLAGS
, 0 },
969 { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN
,
970 CPU_CLZERO_FLAGS
, 0 },
971 { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN
,
972 CPU_MWAITX_FLAGS
, 0 },
973 { STRING_COMMA_LEN (".ospke"), PROCESSOR_UNKNOWN
,
974 CPU_OSPKE_FLAGS
, 0 },
975 { STRING_COMMA_LEN (".rdpid"), PROCESSOR_UNKNOWN
,
976 CPU_RDPID_FLAGS
, 0 },
977 { STRING_COMMA_LEN (".ptwrite"), PROCESSOR_UNKNOWN
,
978 CPU_PTWRITE_FLAGS
, 0 },
981 static const noarch_entry cpu_noarch
[] =
983 { STRING_COMMA_LEN ("no87"), CPU_ANY_X87_FLAGS
},
984 { STRING_COMMA_LEN ("no287"), CPU_ANY_287_FLAGS
},
985 { STRING_COMMA_LEN ("no387"), CPU_ANY_387_FLAGS
},
986 { STRING_COMMA_LEN ("no687"), CPU_ANY_687_FLAGS
},
987 { STRING_COMMA_LEN ("nommx"), CPU_ANY_MMX_FLAGS
},
988 { STRING_COMMA_LEN ("nosse"), CPU_ANY_SSE_FLAGS
},
989 { STRING_COMMA_LEN ("nosse2"), CPU_ANY_SSE2_FLAGS
},
990 { STRING_COMMA_LEN ("nosse3"), CPU_ANY_SSE3_FLAGS
},
991 { STRING_COMMA_LEN ("nossse3"), CPU_ANY_SSSE3_FLAGS
},
992 { STRING_COMMA_LEN ("nosse4.1"), CPU_ANY_SSE4_1_FLAGS
},
993 { STRING_COMMA_LEN ("nosse4.2"), CPU_ANY_SSE4_2_FLAGS
},
994 { STRING_COMMA_LEN ("nosse4"), CPU_ANY_SSE4_1_FLAGS
},
995 { STRING_COMMA_LEN ("noavx"), CPU_ANY_AVX_FLAGS
},
996 { STRING_COMMA_LEN ("noavx2"), CPU_ANY_AVX2_FLAGS
},
997 { STRING_COMMA_LEN ("noavx512f"), CPU_ANY_AVX512F_FLAGS
},
998 { STRING_COMMA_LEN ("noavx512cd"), CPU_ANY_AVX512CD_FLAGS
},
999 { STRING_COMMA_LEN ("noavx512er"), CPU_ANY_AVX512ER_FLAGS
},
1000 { STRING_COMMA_LEN ("noavx512pf"), CPU_ANY_AVX512PF_FLAGS
},
1001 { STRING_COMMA_LEN ("noavx512dq"), CPU_ANY_AVX512DQ_FLAGS
},
1002 { STRING_COMMA_LEN ("noavx512bw"), CPU_ANY_AVX512BW_FLAGS
},
1003 { STRING_COMMA_LEN ("noavx512vl"), CPU_ANY_AVX512VL_FLAGS
},
1004 { STRING_COMMA_LEN ("noavx512ifma"), CPU_ANY_AVX512IFMA_FLAGS
},
1005 { STRING_COMMA_LEN ("noavx512vbmi"), CPU_ANY_AVX512VBMI_FLAGS
},
1006 { STRING_COMMA_LEN ("noavx512_4fmaps"), CPU_ANY_AVX512_4FMAPS_FLAGS
},
1007 { STRING_COMMA_LEN ("noavx512_4vnniw"), CPU_ANY_AVX512_4VNNIW_FLAGS
},
1011 /* Like s_lcomm_internal in gas/read.c but the alignment string
1012 is allowed to be optional. */
1015 pe_lcomm_internal (int needs_align
, symbolS
*symbolP
, addressT size
)
1022 && *input_line_pointer
== ',')
1024 align
= parse_align (needs_align
- 1);
1026 if (align
== (addressT
) -1)
1041 bss_alloc (symbolP
, size
, align
);
1046 pe_lcomm (int needs_align
)
1048 s_comm_internal (needs_align
* 2, pe_lcomm_internal
);
1052 const pseudo_typeS md_pseudo_table
[] =
1054 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
1055 {"align", s_align_bytes
, 0},
1057 {"align", s_align_ptwo
, 0},
1059 {"arch", set_cpu_arch
, 0},
1063 {"lcomm", pe_lcomm
, 1},
1065 {"ffloat", float_cons
, 'f'},
1066 {"dfloat", float_cons
, 'd'},
1067 {"tfloat", float_cons
, 'x'},
1069 {"slong", signed_cons
, 4},
1070 {"noopt", s_ignore
, 0},
1071 {"optim", s_ignore
, 0},
1072 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
1073 {"code16", set_code_flag
, CODE_16BIT
},
1074 {"code32", set_code_flag
, CODE_32BIT
},
1075 {"code64", set_code_flag
, CODE_64BIT
},
1076 {"intel_syntax", set_intel_syntax
, 1},
1077 {"att_syntax", set_intel_syntax
, 0},
1078 {"intel_mnemonic", set_intel_mnemonic
, 1},
1079 {"att_mnemonic", set_intel_mnemonic
, 0},
1080 {"allow_index_reg", set_allow_index_reg
, 1},
1081 {"disallow_index_reg", set_allow_index_reg
, 0},
1082 {"sse_check", set_check
, 0},
1083 {"operand_check", set_check
, 1},
1084 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1085 {"largecomm", handle_large_common
, 0},
1087 {"file", (void (*) (int)) dwarf2_directive_file
, 0},
1088 {"loc", dwarf2_directive_loc
, 0},
1089 {"loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0},
1092 {"secrel32", pe_directive_secrel
, 0},
1097 /* For interface with expression (). */
1098 extern char *input_line_pointer
;
1100 /* Hash table for instruction mnemonic lookup. */
1101 static struct hash_control
*op_hash
;
1103 /* Hash table for register lookup. */
1104 static struct hash_control
*reg_hash
;
1107 i386_align_code (fragS
*fragP
, int count
)
1109 /* Various efficient no-op patterns for aligning code labels.
1110 Note: Don't try to assemble the instructions in the comments.
1111 0L and 0w are not legal. */
1112 static const unsigned char f32_1
[] =
1114 static const unsigned char f32_2
[] =
1115 {0x66,0x90}; /* xchg %ax,%ax */
1116 static const unsigned char f32_3
[] =
1117 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1118 static const unsigned char f32_4
[] =
1119 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1120 static const unsigned char f32_5
[] =
1122 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1123 static const unsigned char f32_6
[] =
1124 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1125 static const unsigned char f32_7
[] =
1126 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1127 static const unsigned char f32_8
[] =
1129 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1130 static const unsigned char f32_9
[] =
1131 {0x89,0xf6, /* movl %esi,%esi */
1132 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1133 static const unsigned char f32_10
[] =
1134 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
1135 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1136 static const unsigned char f32_11
[] =
1137 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
1138 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1139 static const unsigned char f32_12
[] =
1140 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1141 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
1142 static const unsigned char f32_13
[] =
1143 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1144 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1145 static const unsigned char f32_14
[] =
1146 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
1147 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1148 static const unsigned char f16_3
[] =
1149 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
1150 static const unsigned char f16_4
[] =
1151 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
1152 static const unsigned char f16_5
[] =
1154 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
1155 static const unsigned char f16_6
[] =
1156 {0x89,0xf6, /* mov %si,%si */
1157 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1158 static const unsigned char f16_7
[] =
1159 {0x8d,0x74,0x00, /* lea 0(%si),%si */
1160 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1161 static const unsigned char f16_8
[] =
1162 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
1163 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1164 static const unsigned char jump_31
[] =
1165 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
1166 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1167 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1168 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
1169 static const unsigned char *const f32_patt
[] = {
1170 f32_1
, f32_2
, f32_3
, f32_4
, f32_5
, f32_6
, f32_7
, f32_8
,
1171 f32_9
, f32_10
, f32_11
, f32_12
, f32_13
, f32_14
1173 static const unsigned char *const f16_patt
[] = {
1174 f32_1
, f32_2
, f16_3
, f16_4
, f16_5
, f16_6
, f16_7
, f16_8
1176 /* nopl (%[re]ax) */
1177 static const unsigned char alt_3
[] =
1179 /* nopl 0(%[re]ax) */
1180 static const unsigned char alt_4
[] =
1181 {0x0f,0x1f,0x40,0x00};
1182 /* nopl 0(%[re]ax,%[re]ax,1) */
1183 static const unsigned char alt_5
[] =
1184 {0x0f,0x1f,0x44,0x00,0x00};
1185 /* nopw 0(%[re]ax,%[re]ax,1) */
1186 static const unsigned char alt_6
[] =
1187 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1188 /* nopl 0L(%[re]ax) */
1189 static const unsigned char alt_7
[] =
1190 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1191 /* nopl 0L(%[re]ax,%[re]ax,1) */
1192 static const unsigned char alt_8
[] =
1193 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1194 /* nopw 0L(%[re]ax,%[re]ax,1) */
1195 static const unsigned char alt_9
[] =
1196 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1197 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1198 static const unsigned char alt_10
[] =
1199 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1200 static const unsigned char *const alt_patt
[] = {
1201 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
1205 /* Only align for at least a positive non-zero boundary. */
1206 if (count
<= 0 || count
> MAX_MEM_FOR_RS_ALIGN_CODE
)
1209 /* We need to decide which NOP sequence to use for 32bit and
1210 64bit. When -mtune= is used:
1212 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1213 PROCESSOR_GENERIC32, f32_patt will be used.
1214 2. For the rest, alt_patt will be used.
1216 When -mtune= isn't used, alt_patt will be used if
1217 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
1220 When -march= or .arch is used, we can't use anything beyond
1221 cpu_arch_isa_flags. */
1223 if (flag_code
== CODE_16BIT
)
1227 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1229 /* Adjust jump offset. */
1230 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
1233 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1234 f16_patt
[count
- 1], count
);
1238 const unsigned char *const *patt
= NULL
;
1240 if (fragP
->tc_frag_data
.isa
== PROCESSOR_UNKNOWN
)
1242 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1243 switch (cpu_arch_tune
)
1245 case PROCESSOR_UNKNOWN
:
1246 /* We use cpu_arch_isa_flags to check if we SHOULD
1247 optimize with nops. */
1248 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1253 case PROCESSOR_PENTIUM4
:
1254 case PROCESSOR_NOCONA
:
1255 case PROCESSOR_CORE
:
1256 case PROCESSOR_CORE2
:
1257 case PROCESSOR_COREI7
:
1258 case PROCESSOR_L1OM
:
1259 case PROCESSOR_K1OM
:
1260 case PROCESSOR_GENERIC64
:
1262 case PROCESSOR_ATHLON
:
1264 case PROCESSOR_AMDFAM10
:
1266 case PROCESSOR_ZNVER
:
1270 case PROCESSOR_I386
:
1271 case PROCESSOR_I486
:
1272 case PROCESSOR_PENTIUM
:
1273 case PROCESSOR_PENTIUMPRO
:
1274 case PROCESSOR_IAMCU
:
1275 case PROCESSOR_GENERIC32
:
1282 switch (fragP
->tc_frag_data
.tune
)
1284 case PROCESSOR_UNKNOWN
:
1285 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1286 PROCESSOR_UNKNOWN. */
1290 case PROCESSOR_I386
:
1291 case PROCESSOR_I486
:
1292 case PROCESSOR_PENTIUM
:
1293 case PROCESSOR_IAMCU
:
1295 case PROCESSOR_ATHLON
:
1297 case PROCESSOR_AMDFAM10
:
1299 case PROCESSOR_ZNVER
:
1301 case PROCESSOR_GENERIC32
:
1302 /* We use cpu_arch_isa_flags to check if we CAN optimize
1304 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1309 case PROCESSOR_PENTIUMPRO
:
1310 case PROCESSOR_PENTIUM4
:
1311 case PROCESSOR_NOCONA
:
1312 case PROCESSOR_CORE
:
1313 case PROCESSOR_CORE2
:
1314 case PROCESSOR_COREI7
:
1315 case PROCESSOR_L1OM
:
1316 case PROCESSOR_K1OM
:
1317 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1322 case PROCESSOR_GENERIC64
:
1328 if (patt
== f32_patt
)
1330 /* If the padding is less than 15 bytes, we use the normal
1331 ones. Otherwise, we use a jump instruction and adjust
1335 /* For 64bit, the limit is 3 bytes. */
1336 if (flag_code
== CODE_64BIT
1337 && fragP
->tc_frag_data
.isa_flags
.bitfield
.cpulm
)
1342 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1343 patt
[count
- 1], count
);
1346 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1348 /* Adjust jump offset. */
1349 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
1354 /* Maximum length of an instruction is 10 byte. If the
1355 padding is greater than 10 bytes and we don't use jump,
1356 we have to break it into smaller pieces. */
1357 int padding
= count
;
1358 while (padding
> 10)
1361 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
+ padding
,
1366 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1367 patt
[padding
- 1], padding
);
1370 fragP
->fr_var
= count
;
1374 operand_type_all_zero (const union i386_operand_type
*x
)
1376 switch (ARRAY_SIZE(x
->array
))
1387 return !x
->array
[0];
1394 operand_type_set (union i386_operand_type
*x
, unsigned int v
)
1396 switch (ARRAY_SIZE(x
->array
))
1414 operand_type_equal (const union i386_operand_type
*x
,
1415 const union i386_operand_type
*y
)
1417 switch (ARRAY_SIZE(x
->array
))
1420 if (x
->array
[2] != y
->array
[2])
1424 if (x
->array
[1] != y
->array
[1])
1428 return x
->array
[0] == y
->array
[0];
1436 cpu_flags_all_zero (const union i386_cpu_flags
*x
)
1438 switch (ARRAY_SIZE(x
->array
))
1449 return !x
->array
[0];
1456 cpu_flags_equal (const union i386_cpu_flags
*x
,
1457 const union i386_cpu_flags
*y
)
1459 switch (ARRAY_SIZE(x
->array
))
1462 if (x
->array
[2] != y
->array
[2])
1466 if (x
->array
[1] != y
->array
[1])
1470 return x
->array
[0] == y
->array
[0];
1478 cpu_flags_check_cpu64 (i386_cpu_flags f
)
1480 return !((flag_code
== CODE_64BIT
&& f
.bitfield
.cpuno64
)
1481 || (flag_code
!= CODE_64BIT
&& f
.bitfield
.cpu64
));
1484 static INLINE i386_cpu_flags
1485 cpu_flags_and (i386_cpu_flags x
, i386_cpu_flags y
)
1487 switch (ARRAY_SIZE (x
.array
))
1490 x
.array
[2] &= y
.array
[2];
1493 x
.array
[1] &= y
.array
[1];
1496 x
.array
[0] &= y
.array
[0];
1504 static INLINE i386_cpu_flags
1505 cpu_flags_or (i386_cpu_flags x
, i386_cpu_flags y
)
1507 switch (ARRAY_SIZE (x
.array
))
1510 x
.array
[2] |= y
.array
[2];
1513 x
.array
[1] |= y
.array
[1];
1516 x
.array
[0] |= y
.array
[0];
1524 static INLINE i386_cpu_flags
1525 cpu_flags_and_not (i386_cpu_flags x
, i386_cpu_flags y
)
1527 switch (ARRAY_SIZE (x
.array
))
1530 x
.array
[2] &= ~y
.array
[2];
1533 x
.array
[1] &= ~y
.array
[1];
1536 x
.array
[0] &= ~y
.array
[0];
1544 #define CPU_FLAGS_ARCH_MATCH 0x1
1545 #define CPU_FLAGS_64BIT_MATCH 0x2
1546 #define CPU_FLAGS_AES_MATCH 0x4
1547 #define CPU_FLAGS_PCLMUL_MATCH 0x8
1548 #define CPU_FLAGS_AVX_MATCH 0x10
1550 #define CPU_FLAGS_32BIT_MATCH \
1551 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH \
1552 | CPU_FLAGS_PCLMUL_MATCH | CPU_FLAGS_AVX_MATCH)
1553 #define CPU_FLAGS_PERFECT_MATCH \
1554 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)
1556 /* Return CPU flags match bits. */
1559 cpu_flags_match (const insn_template
*t
)
1561 i386_cpu_flags x
= t
->cpu_flags
;
1562 int match
= cpu_flags_check_cpu64 (x
) ? CPU_FLAGS_64BIT_MATCH
: 0;
1564 x
.bitfield
.cpu64
= 0;
1565 x
.bitfield
.cpuno64
= 0;
1567 if (cpu_flags_all_zero (&x
))
1569 /* This instruction is available on all archs. */
1570 match
|= CPU_FLAGS_32BIT_MATCH
;
1574 /* This instruction is available only on some archs. */
1575 i386_cpu_flags cpu
= cpu_arch_flags
;
1577 cpu
= cpu_flags_and (x
, cpu
);
1578 if (!cpu_flags_all_zero (&cpu
))
1580 if (x
.bitfield
.cpuavx
)
1582 /* We only need to check AES/PCLMUL/SSE2AVX with AVX. */
1583 if (cpu
.bitfield
.cpuavx
)
1585 /* Check SSE2AVX. */
1586 if (!t
->opcode_modifier
.sse2avx
|| sse2avx
)
1588 match
|= (CPU_FLAGS_ARCH_MATCH
1589 | CPU_FLAGS_AVX_MATCH
);
1591 if (!x
.bitfield
.cpuaes
|| cpu
.bitfield
.cpuaes
)
1592 match
|= CPU_FLAGS_AES_MATCH
;
1594 if (!x
.bitfield
.cpupclmul
1595 || cpu
.bitfield
.cpupclmul
)
1596 match
|= CPU_FLAGS_PCLMUL_MATCH
;
1600 match
|= CPU_FLAGS_ARCH_MATCH
;
1602 else if (x
.bitfield
.cpuavx512vl
)
1604 /* Match AVX512VL. */
1605 if (cpu
.bitfield
.cpuavx512vl
)
1607 /* Need another match. */
1608 cpu
.bitfield
.cpuavx512vl
= 0;
1609 if (!cpu_flags_all_zero (&cpu
))
1610 match
|= CPU_FLAGS_32BIT_MATCH
;
1612 match
|= CPU_FLAGS_ARCH_MATCH
;
1615 match
|= CPU_FLAGS_ARCH_MATCH
;
1618 match
|= CPU_FLAGS_32BIT_MATCH
;
1624 static INLINE i386_operand_type
1625 operand_type_and (i386_operand_type x
, i386_operand_type y
)
1627 switch (ARRAY_SIZE (x
.array
))
1630 x
.array
[2] &= y
.array
[2];
1633 x
.array
[1] &= y
.array
[1];
1636 x
.array
[0] &= y
.array
[0];
1644 static INLINE i386_operand_type
1645 operand_type_or (i386_operand_type x
, i386_operand_type y
)
1647 switch (ARRAY_SIZE (x
.array
))
1650 x
.array
[2] |= y
.array
[2];
1653 x
.array
[1] |= y
.array
[1];
1656 x
.array
[0] |= y
.array
[0];
1664 static INLINE i386_operand_type
1665 operand_type_xor (i386_operand_type x
, i386_operand_type y
)
1667 switch (ARRAY_SIZE (x
.array
))
1670 x
.array
[2] ^= y
.array
[2];
1673 x
.array
[1] ^= y
.array
[1];
1676 x
.array
[0] ^= y
.array
[0];
1684 static const i386_operand_type acc32
= OPERAND_TYPE_ACC32
;
1685 static const i386_operand_type acc64
= OPERAND_TYPE_ACC64
;
1686 static const i386_operand_type control
= OPERAND_TYPE_CONTROL
;
1687 static const i386_operand_type inoutportreg
1688 = OPERAND_TYPE_INOUTPORTREG
;
1689 static const i386_operand_type reg16_inoutportreg
1690 = OPERAND_TYPE_REG16_INOUTPORTREG
;
1691 static const i386_operand_type disp16
= OPERAND_TYPE_DISP16
;
1692 static const i386_operand_type disp32
= OPERAND_TYPE_DISP32
;
1693 static const i386_operand_type disp32s
= OPERAND_TYPE_DISP32S
;
1694 static const i386_operand_type disp16_32
= OPERAND_TYPE_DISP16_32
;
1695 static const i386_operand_type anydisp
1696 = OPERAND_TYPE_ANYDISP
;
1697 static const i386_operand_type regxmm
= OPERAND_TYPE_REGXMM
;
1698 static const i386_operand_type regymm
= OPERAND_TYPE_REGYMM
;
1699 static const i386_operand_type regzmm
= OPERAND_TYPE_REGZMM
;
1700 static const i386_operand_type regmask
= OPERAND_TYPE_REGMASK
;
1701 static const i386_operand_type imm8
= OPERAND_TYPE_IMM8
;
1702 static const i386_operand_type imm8s
= OPERAND_TYPE_IMM8S
;
1703 static const i386_operand_type imm16
= OPERAND_TYPE_IMM16
;
1704 static const i386_operand_type imm32
= OPERAND_TYPE_IMM32
;
1705 static const i386_operand_type imm32s
= OPERAND_TYPE_IMM32S
;
1706 static const i386_operand_type imm64
= OPERAND_TYPE_IMM64
;
1707 static const i386_operand_type imm16_32
= OPERAND_TYPE_IMM16_32
;
1708 static const i386_operand_type imm16_32s
= OPERAND_TYPE_IMM16_32S
;
1709 static const i386_operand_type imm16_32_32s
= OPERAND_TYPE_IMM16_32_32S
;
1710 static const i386_operand_type vec_imm4
= OPERAND_TYPE_VEC_IMM4
;
1721 operand_type_check (i386_operand_type t
, enum operand_type c
)
1726 return (t
.bitfield
.reg8
1729 || t
.bitfield
.reg64
);
1732 return (t
.bitfield
.imm8
1736 || t
.bitfield
.imm32s
1737 || t
.bitfield
.imm64
);
1740 return (t
.bitfield
.disp8
1741 || t
.bitfield
.disp16
1742 || t
.bitfield
.disp32
1743 || t
.bitfield
.disp32s
1744 || t
.bitfield
.disp64
);
1747 return (t
.bitfield
.disp8
1748 || t
.bitfield
.disp16
1749 || t
.bitfield
.disp32
1750 || t
.bitfield
.disp32s
1751 || t
.bitfield
.disp64
1752 || t
.bitfield
.baseindex
);
1761 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1762 operand J for instruction template T. */
1765 match_reg_size (const insn_template
*t
, unsigned int j
)
1767 return !((i
.types
[j
].bitfield
.byte
1768 && !t
->operand_types
[j
].bitfield
.byte
)
1769 || (i
.types
[j
].bitfield
.word
1770 && !t
->operand_types
[j
].bitfield
.word
)
1771 || (i
.types
[j
].bitfield
.dword
1772 && !t
->operand_types
[j
].bitfield
.dword
)
1773 || (i
.types
[j
].bitfield
.qword
1774 && !t
->operand_types
[j
].bitfield
.qword
));
1777 /* Return 1 if there is no conflict in any size on operand J for
1778 instruction template T. */
1781 match_mem_size (const insn_template
*t
, unsigned int j
)
1783 return (match_reg_size (t
, j
)
1784 && !((i
.types
[j
].bitfield
.unspecified
1786 && !t
->operand_types
[j
].bitfield
.unspecified
)
1787 || (i
.types
[j
].bitfield
.fword
1788 && !t
->operand_types
[j
].bitfield
.fword
)
1789 || (i
.types
[j
].bitfield
.tbyte
1790 && !t
->operand_types
[j
].bitfield
.tbyte
)
1791 || (i
.types
[j
].bitfield
.xmmword
1792 && !t
->operand_types
[j
].bitfield
.xmmword
)
1793 || (i
.types
[j
].bitfield
.ymmword
1794 && !t
->operand_types
[j
].bitfield
.ymmword
)
1795 || (i
.types
[j
].bitfield
.zmmword
1796 && !t
->operand_types
[j
].bitfield
.zmmword
)));
1799 /* Return 1 if there is no size conflict on any operands for
1800 instruction template T. */
1803 operand_size_match (const insn_template
*t
)
1808 /* Don't check jump instructions. */
1809 if (t
->opcode_modifier
.jump
1810 || t
->opcode_modifier
.jumpbyte
1811 || t
->opcode_modifier
.jumpdword
1812 || t
->opcode_modifier
.jumpintersegment
)
1815 /* Check memory and accumulator operand size. */
1816 for (j
= 0; j
< i
.operands
; j
++)
1818 if (t
->operand_types
[j
].bitfield
.anysize
)
1821 if (t
->operand_types
[j
].bitfield
.acc
&& !match_reg_size (t
, j
))
1827 if (i
.types
[j
].bitfield
.mem
&& !match_mem_size (t
, j
))
1836 else if (!t
->opcode_modifier
.d
&& !t
->opcode_modifier
.floatd
)
1839 i
.error
= operand_size_mismatch
;
1843 /* Check reverse. */
1844 gas_assert (i
.operands
== 2);
1847 for (j
= 0; j
< 2; j
++)
1849 if (t
->operand_types
[j
].bitfield
.acc
1850 && !match_reg_size (t
, j
? 0 : 1))
1853 if (i
.types
[j
].bitfield
.mem
1854 && !match_mem_size (t
, j
? 0 : 1))
1862 operand_type_match (i386_operand_type overlap
,
1863 i386_operand_type given
)
1865 i386_operand_type temp
= overlap
;
1867 temp
.bitfield
.jumpabsolute
= 0;
1868 temp
.bitfield
.unspecified
= 0;
1869 temp
.bitfield
.byte
= 0;
1870 temp
.bitfield
.word
= 0;
1871 temp
.bitfield
.dword
= 0;
1872 temp
.bitfield
.fword
= 0;
1873 temp
.bitfield
.qword
= 0;
1874 temp
.bitfield
.tbyte
= 0;
1875 temp
.bitfield
.xmmword
= 0;
1876 temp
.bitfield
.ymmword
= 0;
1877 temp
.bitfield
.zmmword
= 0;
1878 if (operand_type_all_zero (&temp
))
1881 if (given
.bitfield
.baseindex
== overlap
.bitfield
.baseindex
1882 && given
.bitfield
.jumpabsolute
== overlap
.bitfield
.jumpabsolute
)
1886 i
.error
= operand_type_mismatch
;
1890 /* If given types g0 and g1 are registers they must be of the same type
1891 unless the expected operand type register overlap is null.
1892 Note that Acc in a template matches every size of reg. */
1895 operand_type_register_match (i386_operand_type m0
,
1896 i386_operand_type g0
,
1897 i386_operand_type t0
,
1898 i386_operand_type m1
,
1899 i386_operand_type g1
,
1900 i386_operand_type t1
)
1902 if (!operand_type_check (g0
, reg
))
1905 if (!operand_type_check (g1
, reg
))
1908 if (g0
.bitfield
.reg8
== g1
.bitfield
.reg8
1909 && g0
.bitfield
.reg16
== g1
.bitfield
.reg16
1910 && g0
.bitfield
.reg32
== g1
.bitfield
.reg32
1911 && g0
.bitfield
.reg64
== g1
.bitfield
.reg64
)
1914 if (m0
.bitfield
.acc
)
1916 t0
.bitfield
.reg8
= 1;
1917 t0
.bitfield
.reg16
= 1;
1918 t0
.bitfield
.reg32
= 1;
1919 t0
.bitfield
.reg64
= 1;
1922 if (m1
.bitfield
.acc
)
1924 t1
.bitfield
.reg8
= 1;
1925 t1
.bitfield
.reg16
= 1;
1926 t1
.bitfield
.reg32
= 1;
1927 t1
.bitfield
.reg64
= 1;
1930 if (!(t0
.bitfield
.reg8
& t1
.bitfield
.reg8
)
1931 && !(t0
.bitfield
.reg16
& t1
.bitfield
.reg16
)
1932 && !(t0
.bitfield
.reg32
& t1
.bitfield
.reg32
)
1933 && !(t0
.bitfield
.reg64
& t1
.bitfield
.reg64
))
1936 i
.error
= register_type_mismatch
;
1941 static INLINE
unsigned int
1942 register_number (const reg_entry
*r
)
1944 unsigned int nr
= r
->reg_num
;
1946 if (r
->reg_flags
& RegRex
)
1949 if (r
->reg_flags
& RegVRex
)
1955 static INLINE
unsigned int
1956 mode_from_disp_size (i386_operand_type t
)
1958 if (t
.bitfield
.disp8
|| t
.bitfield
.vec_disp8
)
1960 else if (t
.bitfield
.disp16
1961 || t
.bitfield
.disp32
1962 || t
.bitfield
.disp32s
)
1969 fits_in_signed_byte (addressT num
)
1971 return num
+ 0x80 <= 0xff;
1975 fits_in_unsigned_byte (addressT num
)
1981 fits_in_unsigned_word (addressT num
)
1983 return num
<= 0xffff;
1987 fits_in_signed_word (addressT num
)
1989 return num
+ 0x8000 <= 0xffff;
1993 fits_in_signed_long (addressT num ATTRIBUTE_UNUSED
)
1998 return num
+ 0x80000000 <= 0xffffffff;
2000 } /* fits_in_signed_long() */
2003 fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED
)
2008 return num
<= 0xffffffff;
2010 } /* fits_in_unsigned_long() */
2013 fits_in_vec_disp8 (offsetT num
)
2015 int shift
= i
.memshift
;
2021 mask
= (1 << shift
) - 1;
2023 /* Return 0 if NUM isn't properly aligned. */
2027 /* Check if NUM will fit in 8bit after shift. */
2028 return fits_in_signed_byte (num
>> shift
);
2032 fits_in_imm4 (offsetT num
)
2034 return (num
& 0xf) == num
;
2037 static i386_operand_type
2038 smallest_imm_type (offsetT num
)
2040 i386_operand_type t
;
2042 operand_type_set (&t
, 0);
2043 t
.bitfield
.imm64
= 1;
2045 if (cpu_arch_tune
!= PROCESSOR_I486
&& num
== 1)
2047 /* This code is disabled on the 486 because all the Imm1 forms
2048 in the opcode table are slower on the i486. They're the
2049 versions with the implicitly specified single-position
2050 displacement, which has another syntax if you really want to
2052 t
.bitfield
.imm1
= 1;
2053 t
.bitfield
.imm8
= 1;
2054 t
.bitfield
.imm8s
= 1;
2055 t
.bitfield
.imm16
= 1;
2056 t
.bitfield
.imm32
= 1;
2057 t
.bitfield
.imm32s
= 1;
2059 else if (fits_in_signed_byte (num
))
2061 t
.bitfield
.imm8
= 1;
2062 t
.bitfield
.imm8s
= 1;
2063 t
.bitfield
.imm16
= 1;
2064 t
.bitfield
.imm32
= 1;
2065 t
.bitfield
.imm32s
= 1;
2067 else if (fits_in_unsigned_byte (num
))
2069 t
.bitfield
.imm8
= 1;
2070 t
.bitfield
.imm16
= 1;
2071 t
.bitfield
.imm32
= 1;
2072 t
.bitfield
.imm32s
= 1;
2074 else if (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
2076 t
.bitfield
.imm16
= 1;
2077 t
.bitfield
.imm32
= 1;
2078 t
.bitfield
.imm32s
= 1;
2080 else if (fits_in_signed_long (num
))
2082 t
.bitfield
.imm32
= 1;
2083 t
.bitfield
.imm32s
= 1;
2085 else if (fits_in_unsigned_long (num
))
2086 t
.bitfield
.imm32
= 1;
2092 offset_in_range (offsetT val
, int size
)
2098 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
2099 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
2100 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
2102 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
2108 /* If BFD64, sign extend val for 32bit address mode. */
2109 if (flag_code
!= CODE_64BIT
2110 || i
.prefix
[ADDR_PREFIX
])
2111 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
2112 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
2115 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
2117 char buf1
[40], buf2
[40];
2119 sprint_value (buf1
, val
);
2120 sprint_value (buf2
, val
& mask
);
2121 as_warn (_("%s shortened to %s"), buf1
, buf2
);
2135 a. PREFIX_EXIST if attempting to add a prefix where one from the
2136 same class already exists.
2137 b. PREFIX_LOCK if lock prefix is added.
2138 c. PREFIX_REP if rep/repne prefix is added.
2139 d. PREFIX_OTHER if other prefix is added.
2142 static enum PREFIX_GROUP
2143 add_prefix (unsigned int prefix
)
2145 enum PREFIX_GROUP ret
= PREFIX_OTHER
;
2148 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
2149 && flag_code
== CODE_64BIT
)
2151 if ((i
.prefix
[REX_PREFIX
] & prefix
& REX_W
)
2152 || ((i
.prefix
[REX_PREFIX
] & (REX_R
| REX_X
| REX_B
))
2153 && (prefix
& (REX_R
| REX_X
| REX_B
))))
2164 case CS_PREFIX_OPCODE
:
2165 case DS_PREFIX_OPCODE
:
2166 case ES_PREFIX_OPCODE
:
2167 case FS_PREFIX_OPCODE
:
2168 case GS_PREFIX_OPCODE
:
2169 case SS_PREFIX_OPCODE
:
2173 case REPNE_PREFIX_OPCODE
:
2174 case REPE_PREFIX_OPCODE
:
2179 case LOCK_PREFIX_OPCODE
:
2188 case ADDR_PREFIX_OPCODE
:
2192 case DATA_PREFIX_OPCODE
:
2196 if (i
.prefix
[q
] != 0)
2204 i
.prefix
[q
] |= prefix
;
2207 as_bad (_("same type of prefix used twice"));
2213 update_code_flag (int value
, int check
)
2215 PRINTF_LIKE ((*as_error
));
2217 flag_code
= (enum flag_code
) value
;
2218 if (flag_code
== CODE_64BIT
)
2220 cpu_arch_flags
.bitfield
.cpu64
= 1;
2221 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2225 cpu_arch_flags
.bitfield
.cpu64
= 0;
2226 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2228 if (value
== CODE_64BIT
&& !cpu_arch_flags
.bitfield
.cpulm
)
2231 as_error
= as_fatal
;
2234 (*as_error
) (_("64bit mode not supported on `%s'."),
2235 cpu_arch_name
? cpu_arch_name
: default_arch
);
2237 if (value
== CODE_32BIT
&& !cpu_arch_flags
.bitfield
.cpui386
)
2240 as_error
= as_fatal
;
2243 (*as_error
) (_("32bit mode not supported on `%s'."),
2244 cpu_arch_name
? cpu_arch_name
: default_arch
);
2246 stackop_size
= '\0';
2250 set_code_flag (int value
)
2252 update_code_flag (value
, 0);
2256 set_16bit_gcc_code_flag (int new_code_flag
)
2258 flag_code
= (enum flag_code
) new_code_flag
;
2259 if (flag_code
!= CODE_16BIT
)
2261 cpu_arch_flags
.bitfield
.cpu64
= 0;
2262 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2263 stackop_size
= LONG_MNEM_SUFFIX
;
2267 set_intel_syntax (int syntax_flag
)
2269 /* Find out if register prefixing is specified. */
2270 int ask_naked_reg
= 0;
2273 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2276 int e
= get_symbol_name (&string
);
2278 if (strcmp (string
, "prefix") == 0)
2280 else if (strcmp (string
, "noprefix") == 0)
2283 as_bad (_("bad argument to syntax directive."));
2284 (void) restore_line_pointer (e
);
2286 demand_empty_rest_of_line ();
2288 intel_syntax
= syntax_flag
;
2290 if (ask_naked_reg
== 0)
2291 allow_naked_reg
= (intel_syntax
2292 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
2294 allow_naked_reg
= (ask_naked_reg
< 0);
2296 expr_set_rank (O_full_ptr
, syntax_flag
? 10 : 0);
2298 identifier_chars
['%'] = intel_syntax
&& allow_naked_reg
? '%' : 0;
2299 identifier_chars
['$'] = intel_syntax
? '$' : 0;
2300 register_prefix
= allow_naked_reg
? "" : "%";
2304 set_intel_mnemonic (int mnemonic_flag
)
2306 intel_mnemonic
= mnemonic_flag
;
2310 set_allow_index_reg (int flag
)
2312 allow_index_reg
= flag
;
2316 set_check (int what
)
2318 enum check_kind
*kind
;
2323 kind
= &operand_check
;
2334 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2337 int e
= get_symbol_name (&string
);
2339 if (strcmp (string
, "none") == 0)
2341 else if (strcmp (string
, "warning") == 0)
2342 *kind
= check_warning
;
2343 else if (strcmp (string
, "error") == 0)
2344 *kind
= check_error
;
2346 as_bad (_("bad argument to %s_check directive."), str
);
2347 (void) restore_line_pointer (e
);
2350 as_bad (_("missing argument for %s_check directive"), str
);
2352 demand_empty_rest_of_line ();
2356 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED
,
2357 i386_cpu_flags new_flag ATTRIBUTE_UNUSED
)
2359 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2360 static const char *arch
;
2362 /* Intel LIOM is only supported on ELF. */
2368 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2369 use default_arch. */
2370 arch
= cpu_arch_name
;
2372 arch
= default_arch
;
2375 /* If we are targeting Intel MCU, we must enable it. */
2376 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_IAMCU
2377 || new_flag
.bitfield
.cpuiamcu
)
2380 /* If we are targeting Intel L1OM, we must enable it. */
2381 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_L1OM
2382 || new_flag
.bitfield
.cpul1om
)
2385 /* If we are targeting Intel K1OM, we must enable it. */
2386 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_K1OM
2387 || new_flag
.bitfield
.cpuk1om
)
2390 as_bad (_("`%s' is not supported on `%s'"), name
, arch
);
2395 set_cpu_arch (int dummy ATTRIBUTE_UNUSED
)
2399 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2402 int e
= get_symbol_name (&string
);
2404 i386_cpu_flags flags
;
2406 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
2408 if (strcmp (string
, cpu_arch
[j
].name
) == 0)
2410 check_cpu_arch_compatible (string
, cpu_arch
[j
].flags
);
2414 cpu_arch_name
= cpu_arch
[j
].name
;
2415 cpu_sub_arch_name
= NULL
;
2416 cpu_arch_flags
= cpu_arch
[j
].flags
;
2417 if (flag_code
== CODE_64BIT
)
2419 cpu_arch_flags
.bitfield
.cpu64
= 1;
2420 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2424 cpu_arch_flags
.bitfield
.cpu64
= 0;
2425 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2427 cpu_arch_isa
= cpu_arch
[j
].type
;
2428 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
2429 if (!cpu_arch_tune_set
)
2431 cpu_arch_tune
= cpu_arch_isa
;
2432 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
2437 flags
= cpu_flags_or (cpu_arch_flags
,
2440 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2442 if (cpu_sub_arch_name
)
2444 char *name
= cpu_sub_arch_name
;
2445 cpu_sub_arch_name
= concat (name
,
2447 (const char *) NULL
);
2451 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
2452 cpu_arch_flags
= flags
;
2453 cpu_arch_isa_flags
= flags
;
2455 (void) restore_line_pointer (e
);
2456 demand_empty_rest_of_line ();
2461 if (*string
== '.' && j
>= ARRAY_SIZE (cpu_arch
))
2463 /* Disable an ISA entension. */
2464 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
2465 if (strcmp (string
+ 1, cpu_noarch
[j
].name
) == 0)
2467 flags
= cpu_flags_and_not (cpu_arch_flags
,
2468 cpu_noarch
[j
].flags
);
2469 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2471 if (cpu_sub_arch_name
)
2473 char *name
= cpu_sub_arch_name
;
2474 cpu_sub_arch_name
= concat (name
, string
,
2475 (const char *) NULL
);
2479 cpu_sub_arch_name
= xstrdup (string
);
2480 cpu_arch_flags
= flags
;
2481 cpu_arch_isa_flags
= flags
;
2483 (void) restore_line_pointer (e
);
2484 demand_empty_rest_of_line ();
2488 j
= ARRAY_SIZE (cpu_arch
);
2491 if (j
>= ARRAY_SIZE (cpu_arch
))
2492 as_bad (_("no such architecture: `%s'"), string
);
2494 *input_line_pointer
= e
;
2497 as_bad (_("missing cpu architecture"));
2499 no_cond_jump_promotion
= 0;
2500 if (*input_line_pointer
== ','
2501 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
2506 ++input_line_pointer
;
2507 e
= get_symbol_name (&string
);
2509 if (strcmp (string
, "nojumps") == 0)
2510 no_cond_jump_promotion
= 1;
2511 else if (strcmp (string
, "jumps") == 0)
2514 as_bad (_("no such architecture modifier: `%s'"), string
);
2516 (void) restore_line_pointer (e
);
2519 demand_empty_rest_of_line ();
2522 enum bfd_architecture
2525 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2527 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2528 || flag_code
!= CODE_64BIT
)
2529 as_fatal (_("Intel L1OM is 64bit ELF only"));
2530 return bfd_arch_l1om
;
2532 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2534 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2535 || flag_code
!= CODE_64BIT
)
2536 as_fatal (_("Intel K1OM is 64bit ELF only"));
2537 return bfd_arch_k1om
;
2539 else if (cpu_arch_isa
== PROCESSOR_IAMCU
)
2541 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2542 || flag_code
== CODE_64BIT
)
2543 as_fatal (_("Intel MCU is 32bit ELF only"));
2544 return bfd_arch_iamcu
;
2547 return bfd_arch_i386
;
2553 if (!strncmp (default_arch
, "x86_64", 6))
2555 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2557 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2558 || default_arch
[6] != '\0')
2559 as_fatal (_("Intel L1OM is 64bit ELF only"));
2560 return bfd_mach_l1om
;
2562 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2564 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2565 || default_arch
[6] != '\0')
2566 as_fatal (_("Intel K1OM is 64bit ELF only"));
2567 return bfd_mach_k1om
;
2569 else if (default_arch
[6] == '\0')
2570 return bfd_mach_x86_64
;
2572 return bfd_mach_x64_32
;
2574 else if (!strcmp (default_arch
, "i386")
2575 || !strcmp (default_arch
, "iamcu"))
2577 if (cpu_arch_isa
== PROCESSOR_IAMCU
)
2579 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
2580 as_fatal (_("Intel MCU is 32bit ELF only"));
2581 return bfd_mach_i386_iamcu
;
2584 return bfd_mach_i386_i386
;
2587 as_fatal (_("unknown architecture"));
2593 const char *hash_err
;
2595 /* Initialize op_hash hash table. */
2596 op_hash
= hash_new ();
2599 const insn_template
*optab
;
2600 templates
*core_optab
;
2602 /* Setup for loop. */
2604 core_optab
= XNEW (templates
);
2605 core_optab
->start
= optab
;
2610 if (optab
->name
== NULL
2611 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
2613 /* different name --> ship out current template list;
2614 add to hash table; & begin anew. */
2615 core_optab
->end
= optab
;
2616 hash_err
= hash_insert (op_hash
,
2618 (void *) core_optab
);
2621 as_fatal (_("can't hash %s: %s"),
2625 if (optab
->name
== NULL
)
2627 core_optab
= XNEW (templates
);
2628 core_optab
->start
= optab
;
2633 /* Initialize reg_hash hash table. */
2634 reg_hash
= hash_new ();
2636 const reg_entry
*regtab
;
2637 unsigned int regtab_size
= i386_regtab_size
;
2639 for (regtab
= i386_regtab
; regtab_size
--; regtab
++)
2641 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (void *) regtab
);
2643 as_fatal (_("can't hash %s: %s"),
2649 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
2654 for (c
= 0; c
< 256; c
++)
2659 mnemonic_chars
[c
] = c
;
2660 register_chars
[c
] = c
;
2661 operand_chars
[c
] = c
;
2663 else if (ISLOWER (c
))
2665 mnemonic_chars
[c
] = c
;
2666 register_chars
[c
] = c
;
2667 operand_chars
[c
] = c
;
2669 else if (ISUPPER (c
))
2671 mnemonic_chars
[c
] = TOLOWER (c
);
2672 register_chars
[c
] = mnemonic_chars
[c
];
2673 operand_chars
[c
] = c
;
2675 else if (c
== '{' || c
== '}')
2676 operand_chars
[c
] = c
;
2678 if (ISALPHA (c
) || ISDIGIT (c
))
2679 identifier_chars
[c
] = c
;
2682 identifier_chars
[c
] = c
;
2683 operand_chars
[c
] = c
;
2688 identifier_chars
['@'] = '@';
2691 identifier_chars
['?'] = '?';
2692 operand_chars
['?'] = '?';
2694 digit_chars
['-'] = '-';
2695 mnemonic_chars
['_'] = '_';
2696 mnemonic_chars
['-'] = '-';
2697 mnemonic_chars
['.'] = '.';
2698 identifier_chars
['_'] = '_';
2699 identifier_chars
['.'] = '.';
2701 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
2702 operand_chars
[(unsigned char) *p
] = *p
;
2705 if (flag_code
== CODE_64BIT
)
2707 #if defined (OBJ_COFF) && defined (TE_PE)
2708 x86_dwarf2_return_column
= (OUTPUT_FLAVOR
== bfd_target_coff_flavour
2711 x86_dwarf2_return_column
= 16;
2713 x86_cie_data_alignment
= -8;
2717 x86_dwarf2_return_column
= 8;
2718 x86_cie_data_alignment
= -4;
2723 i386_print_statistics (FILE *file
)
2725 hash_print_statistics (file
, "i386 opcode", op_hash
);
2726 hash_print_statistics (file
, "i386 register", reg_hash
);
2731 /* Debugging routines for md_assemble. */
2732 static void pte (insn_template
*);
2733 static void pt (i386_operand_type
);
2734 static void pe (expressionS
*);
2735 static void ps (symbolS
*);
2738 pi (char *line
, i386_insn
*x
)
2742 fprintf (stdout
, "%s: template ", line
);
2744 fprintf (stdout
, " address: base %s index %s scale %x\n",
2745 x
->base_reg
? x
->base_reg
->reg_name
: "none",
2746 x
->index_reg
? x
->index_reg
->reg_name
: "none",
2747 x
->log2_scale_factor
);
2748 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
2749 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
2750 fprintf (stdout
, " sib: base %x index %x scale %x\n",
2751 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
2752 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
2753 (x
->rex
& REX_W
) != 0,
2754 (x
->rex
& REX_R
) != 0,
2755 (x
->rex
& REX_X
) != 0,
2756 (x
->rex
& REX_B
) != 0);
2757 for (j
= 0; j
< x
->operands
; j
++)
2759 fprintf (stdout
, " #%d: ", j
+ 1);
2761 fprintf (stdout
, "\n");
2762 if (x
->types
[j
].bitfield
.reg8
2763 || x
->types
[j
].bitfield
.reg16
2764 || x
->types
[j
].bitfield
.reg32
2765 || x
->types
[j
].bitfield
.reg64
2766 || x
->types
[j
].bitfield
.regmmx
2767 || x
->types
[j
].bitfield
.regxmm
2768 || x
->types
[j
].bitfield
.regymm
2769 || x
->types
[j
].bitfield
.regzmm
2770 || x
->types
[j
].bitfield
.sreg2
2771 || x
->types
[j
].bitfield
.sreg3
2772 || x
->types
[j
].bitfield
.control
2773 || x
->types
[j
].bitfield
.debug
2774 || x
->types
[j
].bitfield
.test
)
2775 fprintf (stdout
, "%s\n", x
->op
[j
].regs
->reg_name
);
2776 if (operand_type_check (x
->types
[j
], imm
))
2778 if (operand_type_check (x
->types
[j
], disp
))
2779 pe (x
->op
[j
].disps
);
2784 pte (insn_template
*t
)
2787 fprintf (stdout
, " %d operands ", t
->operands
);
2788 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
2789 if (t
->extension_opcode
!= None
)
2790 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
2791 if (t
->opcode_modifier
.d
)
2792 fprintf (stdout
, "D");
2793 if (t
->opcode_modifier
.w
)
2794 fprintf (stdout
, "W");
2795 fprintf (stdout
, "\n");
2796 for (j
= 0; j
< t
->operands
; j
++)
2798 fprintf (stdout
, " #%d type ", j
+ 1);
2799 pt (t
->operand_types
[j
]);
2800 fprintf (stdout
, "\n");
2807 fprintf (stdout
, " operation %d\n", e
->X_op
);
2808 fprintf (stdout
, " add_number %ld (%lx)\n",
2809 (long) e
->X_add_number
, (long) e
->X_add_number
);
2810 if (e
->X_add_symbol
)
2812 fprintf (stdout
, " add_symbol ");
2813 ps (e
->X_add_symbol
);
2814 fprintf (stdout
, "\n");
2818 fprintf (stdout
, " op_symbol ");
2819 ps (e
->X_op_symbol
);
2820 fprintf (stdout
, "\n");
2827 fprintf (stdout
, "%s type %s%s",
2829 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
2830 segment_name (S_GET_SEGMENT (s
)));
2833 static struct type_name
2835 i386_operand_type mask
;
2838 const type_names
[] =
2840 { OPERAND_TYPE_REG8
, "r8" },
2841 { OPERAND_TYPE_REG16
, "r16" },
2842 { OPERAND_TYPE_REG32
, "r32" },
2843 { OPERAND_TYPE_REG64
, "r64" },
2844 { OPERAND_TYPE_IMM8
, "i8" },
2845 { OPERAND_TYPE_IMM8
, "i8s" },
2846 { OPERAND_TYPE_IMM16
, "i16" },
2847 { OPERAND_TYPE_IMM32
, "i32" },
2848 { OPERAND_TYPE_IMM32S
, "i32s" },
2849 { OPERAND_TYPE_IMM64
, "i64" },
2850 { OPERAND_TYPE_IMM1
, "i1" },
2851 { OPERAND_TYPE_BASEINDEX
, "BaseIndex" },
2852 { OPERAND_TYPE_DISP8
, "d8" },
2853 { OPERAND_TYPE_DISP16
, "d16" },
2854 { OPERAND_TYPE_DISP32
, "d32" },
2855 { OPERAND_TYPE_DISP32S
, "d32s" },
2856 { OPERAND_TYPE_DISP64
, "d64" },
2857 { OPERAND_TYPE_VEC_DISP8
, "Vector d8" },
2858 { OPERAND_TYPE_INOUTPORTREG
, "InOutPortReg" },
2859 { OPERAND_TYPE_SHIFTCOUNT
, "ShiftCount" },
2860 { OPERAND_TYPE_CONTROL
, "control reg" },
2861 { OPERAND_TYPE_TEST
, "test reg" },
2862 { OPERAND_TYPE_DEBUG
, "debug reg" },
2863 { OPERAND_TYPE_FLOATREG
, "FReg" },
2864 { OPERAND_TYPE_FLOATACC
, "FAcc" },
2865 { OPERAND_TYPE_SREG2
, "SReg2" },
2866 { OPERAND_TYPE_SREG3
, "SReg3" },
2867 { OPERAND_TYPE_ACC
, "Acc" },
2868 { OPERAND_TYPE_JUMPABSOLUTE
, "Jump Absolute" },
2869 { OPERAND_TYPE_REGMMX
, "rMMX" },
2870 { OPERAND_TYPE_REGXMM
, "rXMM" },
2871 { OPERAND_TYPE_REGYMM
, "rYMM" },
2872 { OPERAND_TYPE_REGZMM
, "rZMM" },
2873 { OPERAND_TYPE_REGMASK
, "Mask reg" },
2874 { OPERAND_TYPE_ESSEG
, "es" },
2878 pt (i386_operand_type t
)
2881 i386_operand_type a
;
2883 for (j
= 0; j
< ARRAY_SIZE (type_names
); j
++)
2885 a
= operand_type_and (t
, type_names
[j
].mask
);
2886 if (!operand_type_all_zero (&a
))
2887 fprintf (stdout
, "%s, ", type_names
[j
].name
);
2892 #endif /* DEBUG386 */
2894 static bfd_reloc_code_real_type
2895 reloc (unsigned int size
,
2898 bfd_reloc_code_real_type other
)
2900 if (other
!= NO_RELOC
)
2902 reloc_howto_type
*rel
;
2907 case BFD_RELOC_X86_64_GOT32
:
2908 return BFD_RELOC_X86_64_GOT64
;
2910 case BFD_RELOC_X86_64_GOTPLT64
:
2911 return BFD_RELOC_X86_64_GOTPLT64
;
2913 case BFD_RELOC_X86_64_PLTOFF64
:
2914 return BFD_RELOC_X86_64_PLTOFF64
;
2916 case BFD_RELOC_X86_64_GOTPC32
:
2917 other
= BFD_RELOC_X86_64_GOTPC64
;
2919 case BFD_RELOC_X86_64_GOTPCREL
:
2920 other
= BFD_RELOC_X86_64_GOTPCREL64
;
2922 case BFD_RELOC_X86_64_TPOFF32
:
2923 other
= BFD_RELOC_X86_64_TPOFF64
;
2925 case BFD_RELOC_X86_64_DTPOFF32
:
2926 other
= BFD_RELOC_X86_64_DTPOFF64
;
2932 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2933 if (other
== BFD_RELOC_SIZE32
)
2936 other
= BFD_RELOC_SIZE64
;
2939 as_bad (_("there are no pc-relative size relocations"));
2945 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
2946 if (size
== 4 && (flag_code
!= CODE_64BIT
|| disallow_64bit_reloc
))
2949 rel
= bfd_reloc_type_lookup (stdoutput
, other
);
2951 as_bad (_("unknown relocation (%u)"), other
);
2952 else if (size
!= bfd_get_reloc_size (rel
))
2953 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
2954 bfd_get_reloc_size (rel
),
2956 else if (pcrel
&& !rel
->pc_relative
)
2957 as_bad (_("non-pc-relative relocation for pc-relative field"));
2958 else if ((rel
->complain_on_overflow
== complain_overflow_signed
2960 || (rel
->complain_on_overflow
== complain_overflow_unsigned
2962 as_bad (_("relocated field and relocation type differ in signedness"));
2971 as_bad (_("there are no unsigned pc-relative relocations"));
2974 case 1: return BFD_RELOC_8_PCREL
;
2975 case 2: return BFD_RELOC_16_PCREL
;
2976 case 4: return BFD_RELOC_32_PCREL
;
2977 case 8: return BFD_RELOC_64_PCREL
;
2979 as_bad (_("cannot do %u byte pc-relative relocation"), size
);
2986 case 4: return BFD_RELOC_X86_64_32S
;
2991 case 1: return BFD_RELOC_8
;
2992 case 2: return BFD_RELOC_16
;
2993 case 4: return BFD_RELOC_32
;
2994 case 8: return BFD_RELOC_64
;
2996 as_bad (_("cannot do %s %u byte relocation"),
2997 sign
> 0 ? "signed" : "unsigned", size
);
3003 /* Here we decide which fixups can be adjusted to make them relative to
3004 the beginning of the section instead of the symbol. Basically we need
3005 to make sure that the dynamic relocations are done correctly, so in
3006 some cases we force the original symbol to be used. */
3009 tc_i386_fix_adjustable (fixS
*fixP ATTRIBUTE_UNUSED
)
3011 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3015 /* Don't adjust pc-relative references to merge sections in 64-bit
3017 if (use_rela_relocations
3018 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
3022 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
3023 and changed later by validate_fix. */
3024 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
3025 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
3028 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
3029 for size relocations. */
3030 if (fixP
->fx_r_type
== BFD_RELOC_SIZE32
3031 || fixP
->fx_r_type
== BFD_RELOC_SIZE64
3032 || fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
3033 || fixP
->fx_r_type
== BFD_RELOC_386_PLT32
3034 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
3035 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32X
3036 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
3037 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
3038 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
3039 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
3040 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
3041 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
3042 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
3043 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
3044 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTDESC
3045 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_DESC_CALL
3046 || fixP
->fx_r_type
== BFD_RELOC_X86_64_PLT32
3047 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
3048 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
3049 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCRELX
3050 || fixP
->fx_r_type
== BFD_RELOC_X86_64_REX_GOTPCRELX
3051 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
3052 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
3053 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
3054 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
3055 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
3056 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
3057 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
3058 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
3059 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPC32_TLSDESC
3060 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSDESC_CALL
3061 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
3062 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
3069 intel_float_operand (const char *mnemonic
)
3071 /* Note that the value returned is meaningful only for opcodes with (memory)
3072 operands, hence the code here is free to improperly handle opcodes that
3073 have no operands (for better performance and smaller code). */
3075 if (mnemonic
[0] != 'f')
3076 return 0; /* non-math */
3078 switch (mnemonic
[1])
3080 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
3081 the fs segment override prefix not currently handled because no
3082 call path can make opcodes without operands get here */
3084 return 2 /* integer op */;
3086 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
3087 return 3; /* fldcw/fldenv */
3090 if (mnemonic
[2] != 'o' /* fnop */)
3091 return 3; /* non-waiting control op */
3094 if (mnemonic
[2] == 's')
3095 return 3; /* frstor/frstpm */
3098 if (mnemonic
[2] == 'a')
3099 return 3; /* fsave */
3100 if (mnemonic
[2] == 't')
3102 switch (mnemonic
[3])
3104 case 'c': /* fstcw */
3105 case 'd': /* fstdw */
3106 case 'e': /* fstenv */
3107 case 's': /* fsts[gw] */
3113 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
3114 return 0; /* fxsave/fxrstor are not really math ops */
3121 /* Build the VEX prefix. */
3124 build_vex_prefix (const insn_template
*t
)
3126 unsigned int register_specifier
;
3127 unsigned int implied_prefix
;
3128 unsigned int vector_length
;
3130 /* Check register specifier. */
3131 if (i
.vex
.register_specifier
)
3133 register_specifier
=
3134 ~register_number (i
.vex
.register_specifier
) & 0xf;
3135 gas_assert ((i
.vex
.register_specifier
->reg_flags
& RegVRex
) == 0);
3138 register_specifier
= 0xf;
3140 /* Use 2-byte VEX prefix by swappping destination and source
3143 && i
.operands
== i
.reg_operands
3144 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3145 && i
.tm
.opcode_modifier
.s
3148 unsigned int xchg
= i
.operands
- 1;
3149 union i386_op temp_op
;
3150 i386_operand_type temp_type
;
3152 temp_type
= i
.types
[xchg
];
3153 i
.types
[xchg
] = i
.types
[0];
3154 i
.types
[0] = temp_type
;
3155 temp_op
= i
.op
[xchg
];
3156 i
.op
[xchg
] = i
.op
[0];
3159 gas_assert (i
.rm
.mode
== 3);
3163 i
.rm
.regmem
= i
.rm
.reg
;
3166 /* Use the next insn. */
3170 if (i
.tm
.opcode_modifier
.vex
== VEXScalar
)
3171 vector_length
= avxscalar
;
3173 vector_length
= i
.tm
.opcode_modifier
.vex
== VEX256
? 1 : 0;
3175 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3180 case DATA_PREFIX_OPCODE
:
3183 case REPE_PREFIX_OPCODE
:
3186 case REPNE_PREFIX_OPCODE
:
3193 /* Use 2-byte VEX prefix if possible. */
3194 if (i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3195 && i
.tm
.opcode_modifier
.vexw
!= VEXW1
3196 && (i
.rex
& (REX_W
| REX_X
| REX_B
)) == 0)
3198 /* 2-byte VEX prefix. */
3202 i
.vex
.bytes
[0] = 0xc5;
3204 /* Check the REX.R bit. */
3205 r
= (i
.rex
& REX_R
) ? 0 : 1;
3206 i
.vex
.bytes
[1] = (r
<< 7
3207 | register_specifier
<< 3
3208 | vector_length
<< 2
3213 /* 3-byte VEX prefix. */
3218 switch (i
.tm
.opcode_modifier
.vexopcode
)
3222 i
.vex
.bytes
[0] = 0xc4;
3226 i
.vex
.bytes
[0] = 0xc4;
3230 i
.vex
.bytes
[0] = 0xc4;
3234 i
.vex
.bytes
[0] = 0x8f;
3238 i
.vex
.bytes
[0] = 0x8f;
3242 i
.vex
.bytes
[0] = 0x8f;
3248 /* The high 3 bits of the second VEX byte are 1's compliment
3249 of RXB bits from REX. */
3250 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3252 /* Check the REX.W bit. */
3253 w
= (i
.rex
& REX_W
) ? 1 : 0;
3254 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
3257 i
.vex
.bytes
[2] = (w
<< 7
3258 | register_specifier
<< 3
3259 | vector_length
<< 2
3264 /* Build the EVEX prefix. */
3267 build_evex_prefix (void)
3269 unsigned int register_specifier
;
3270 unsigned int implied_prefix
;
3272 rex_byte vrex_used
= 0;
3274 /* Check register specifier. */
3275 if (i
.vex
.register_specifier
)
3277 gas_assert ((i
.vrex
& REX_X
) == 0);
3279 register_specifier
= i
.vex
.register_specifier
->reg_num
;
3280 if ((i
.vex
.register_specifier
->reg_flags
& RegRex
))
3281 register_specifier
+= 8;
3282 /* The upper 16 registers are encoded in the fourth byte of the
3284 if (!(i
.vex
.register_specifier
->reg_flags
& RegVRex
))
3285 i
.vex
.bytes
[3] = 0x8;
3286 register_specifier
= ~register_specifier
& 0xf;
3290 register_specifier
= 0xf;
3292 /* Encode upper 16 vector index register in the fourth byte of
3294 if (!(i
.vrex
& REX_X
))
3295 i
.vex
.bytes
[3] = 0x8;
3300 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3305 case DATA_PREFIX_OPCODE
:
3308 case REPE_PREFIX_OPCODE
:
3311 case REPNE_PREFIX_OPCODE
:
3318 /* 4 byte EVEX prefix. */
3320 i
.vex
.bytes
[0] = 0x62;
3323 switch (i
.tm
.opcode_modifier
.vexopcode
)
3339 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3341 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3343 /* The fifth bit of the second EVEX byte is 1's compliment of the
3344 REX_R bit in VREX. */
3345 if (!(i
.vrex
& REX_R
))
3346 i
.vex
.bytes
[1] |= 0x10;
3350 if ((i
.reg_operands
+ i
.imm_operands
) == i
.operands
)
3352 /* When all operands are registers, the REX_X bit in REX is not
3353 used. We reuse it to encode the upper 16 registers, which is
3354 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3355 as 1's compliment. */
3356 if ((i
.vrex
& REX_B
))
3359 i
.vex
.bytes
[1] &= ~0x40;
3363 /* EVEX instructions shouldn't need the REX prefix. */
3364 i
.vrex
&= ~vrex_used
;
3365 gas_assert (i
.vrex
== 0);
3367 /* Check the REX.W bit. */
3368 w
= (i
.rex
& REX_W
) ? 1 : 0;
3369 if (i
.tm
.opcode_modifier
.vexw
)
3371 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
3374 /* If w is not set it means we are dealing with WIG instruction. */
3377 if (evexwig
== evexw1
)
3381 /* Encode the U bit. */
3382 implied_prefix
|= 0x4;
3384 /* The third byte of the EVEX prefix. */
3385 i
.vex
.bytes
[2] = (w
<< 7 | register_specifier
<< 3 | implied_prefix
);
3387 /* The fourth byte of the EVEX prefix. */
3388 /* The zeroing-masking bit. */
3389 if (i
.mask
&& i
.mask
->zeroing
)
3390 i
.vex
.bytes
[3] |= 0x80;
3392 /* Don't always set the broadcast bit if there is no RC. */
3395 /* Encode the vector length. */
3396 unsigned int vec_length
;
3398 switch (i
.tm
.opcode_modifier
.evex
)
3400 case EVEXLIG
: /* LL' is ignored */
3401 vec_length
= evexlig
<< 5;
3404 vec_length
= 0 << 5;
3407 vec_length
= 1 << 5;
3410 vec_length
= 2 << 5;
3416 i
.vex
.bytes
[3] |= vec_length
;
3417 /* Encode the broadcast bit. */
3419 i
.vex
.bytes
[3] |= 0x10;
3423 if (i
.rounding
->type
!= saeonly
)
3424 i
.vex
.bytes
[3] |= 0x10 | (i
.rounding
->type
<< 5);
3426 i
.vex
.bytes
[3] |= 0x10 | (evexrcig
<< 5);
3429 if (i
.mask
&& i
.mask
->mask
)
3430 i
.vex
.bytes
[3] |= i
.mask
->mask
->reg_num
;
3434 process_immext (void)
3438 if ((i
.tm
.cpu_flags
.bitfield
.cpusse3
|| i
.tm
.cpu_flags
.bitfield
.cpusvme
)
3441 /* MONITOR/MWAIT as well as SVME instructions have fixed operands
3442 with an opcode suffix which is coded in the same place as an
3443 8-bit immediate field would be.
3444 Here we check those operands and remove them afterwards. */
3447 for (x
= 0; x
< i
.operands
; x
++)
3448 if (register_number (i
.op
[x
].regs
) != x
)
3449 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3450 register_prefix
, i
.op
[x
].regs
->reg_name
, x
+ 1,
3456 if (i
.tm
.cpu_flags
.bitfield
.cpumwaitx
&& i
.operands
> 0)
3458 /* MONITORX/MWAITX instructions have fixed operands with an opcode
3459 suffix which is coded in the same place as an 8-bit immediate
3461 Here we check those operands and remove them afterwards. */
3464 if (i
.operands
!= 3)
3467 for (x
= 0; x
< 2; x
++)
3468 if (register_number (i
.op
[x
].regs
) != x
)
3469 goto bad_register_operand
;
3471 /* Check for third operand for mwaitx/monitorx insn. */
3472 if (register_number (i
.op
[x
].regs
)
3473 != (x
+ (i
.tm
.extension_opcode
== 0xfb)))
3475 bad_register_operand
:
3476 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3477 register_prefix
, i
.op
[x
].regs
->reg_name
, x
+1,
3484 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
3485 which is coded in the same place as an 8-bit immediate field
3486 would be. Here we fake an 8-bit immediate operand from the
3487 opcode suffix stored in tm.extension_opcode.
3489 AVX instructions also use this encoding, for some of
3490 3 argument instructions. */
3492 gas_assert (i
.imm_operands
<= 1
3494 || ((i
.tm
.opcode_modifier
.vex
3495 || i
.tm
.opcode_modifier
.evex
)
3496 && i
.operands
<= 4)));
3498 exp
= &im_expressions
[i
.imm_operands
++];
3499 i
.op
[i
.operands
].imms
= exp
;
3500 i
.types
[i
.operands
] = imm8
;
3502 exp
->X_op
= O_constant
;
3503 exp
->X_add_number
= i
.tm
.extension_opcode
;
3504 i
.tm
.extension_opcode
= None
;
3511 switch (i
.tm
.opcode_modifier
.hleprefixok
)
3516 as_bad (_("invalid instruction `%s' after `%s'"),
3517 i
.tm
.name
, i
.hle_prefix
);
3520 if (i
.prefix
[LOCK_PREFIX
])
3522 as_bad (_("missing `lock' with `%s'"), i
.hle_prefix
);
3526 case HLEPrefixRelease
:
3527 if (i
.prefix
[HLE_PREFIX
] != XRELEASE_PREFIX_OPCODE
)
3529 as_bad (_("instruction `%s' after `xacquire' not allowed"),
3533 if (i
.mem_operands
== 0
3534 || !operand_type_check (i
.types
[i
.operands
- 1], anymem
))
3536 as_bad (_("memory destination needed for instruction `%s'"
3537 " after `xrelease'"), i
.tm
.name
);
3544 /* This is the guts of the machine-dependent assembler. LINE points to a
3545 machine dependent instruction. This function is supposed to emit
3546 the frags/bytes it assembles to. */
3549 md_assemble (char *line
)
3552 char mnemonic
[MAX_MNEM_SIZE
], mnem_suffix
;
3553 const insn_template
*t
;
3555 /* Initialize globals. */
3556 memset (&i
, '\0', sizeof (i
));
3557 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3558 i
.reloc
[j
] = NO_RELOC
;
3559 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
3560 memset (im_expressions
, '\0', sizeof (im_expressions
));
3561 save_stack_p
= save_stack
;
3563 /* First parse an instruction mnemonic & call i386_operand for the operands.
3564 We assume that the scrubber has arranged it so that line[0] is the valid
3565 start of a (possibly prefixed) mnemonic. */
3567 line
= parse_insn (line
, mnemonic
);
3570 mnem_suffix
= i
.suffix
;
3572 line
= parse_operands (line
, mnemonic
);
3574 xfree (i
.memop1_string
);
3575 i
.memop1_string
= NULL
;
3579 /* Now we've parsed the mnemonic into a set of templates, and have the
3580 operands at hand. */
3582 /* All intel opcodes have reversed operands except for "bound" and
3583 "enter". We also don't reverse intersegment "jmp" and "call"
3584 instructions with 2 immediate operands so that the immediate segment
3585 precedes the offset, as it does when in AT&T mode. */
3588 && (strcmp (mnemonic
, "bound") != 0)
3589 && (strcmp (mnemonic
, "invlpga") != 0)
3590 && !(operand_type_check (i
.types
[0], imm
)
3591 && operand_type_check (i
.types
[1], imm
)))
3594 /* The order of the immediates should be reversed
3595 for 2 immediates extrq and insertq instructions */
3596 if (i
.imm_operands
== 2
3597 && (strcmp (mnemonic
, "extrq") == 0
3598 || strcmp (mnemonic
, "insertq") == 0))
3599 swap_2_operands (0, 1);
3604 /* Don't optimize displacement for movabs since it only takes 64bit
3607 && i
.disp_encoding
!= disp_encoding_32bit
3608 && (flag_code
!= CODE_64BIT
3609 || strcmp (mnemonic
, "movabs") != 0))
3612 /* Next, we find a template that matches the given insn,
3613 making sure the overlap of the given operands types is consistent
3614 with the template operand types. */
3616 if (!(t
= match_template (mnem_suffix
)))
3619 if (sse_check
!= check_none
3620 && !i
.tm
.opcode_modifier
.noavx
3621 && (i
.tm
.cpu_flags
.bitfield
.cpusse
3622 || i
.tm
.cpu_flags
.bitfield
.cpusse2
3623 || i
.tm
.cpu_flags
.bitfield
.cpusse3
3624 || i
.tm
.cpu_flags
.bitfield
.cpussse3
3625 || i
.tm
.cpu_flags
.bitfield
.cpusse4_1
3626 || i
.tm
.cpu_flags
.bitfield
.cpusse4_2
))
3628 (sse_check
== check_warning
3630 : as_bad
) (_("SSE instruction `%s' is used"), i
.tm
.name
);
3633 /* Zap movzx and movsx suffix. The suffix has been set from
3634 "word ptr" or "byte ptr" on the source operand in Intel syntax
3635 or extracted from mnemonic in AT&T syntax. But we'll use
3636 the destination register to choose the suffix for encoding. */
3637 if ((i
.tm
.base_opcode
& ~9) == 0x0fb6)
3639 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
3640 there is no suffix, the default will be byte extension. */
3641 if (i
.reg_operands
!= 2
3644 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
3649 if (i
.tm
.opcode_modifier
.fwait
)
3650 if (!add_prefix (FWAIT_OPCODE
))
3653 /* Check if REP prefix is OK. */
3654 if (i
.rep_prefix
&& !i
.tm
.opcode_modifier
.repprefixok
)
3656 as_bad (_("invalid instruction `%s' after `%s'"),
3657 i
.tm
.name
, i
.rep_prefix
);
3661 /* Check for lock without a lockable instruction. Destination operand
3662 must be memory unless it is xchg (0x86). */
3663 if (i
.prefix
[LOCK_PREFIX
]
3664 && (!i
.tm
.opcode_modifier
.islockable
3665 || i
.mem_operands
== 0
3666 || (i
.tm
.base_opcode
!= 0x86
3667 && !operand_type_check (i
.types
[i
.operands
- 1], anymem
))))
3669 as_bad (_("expecting lockable instruction after `lock'"));
3673 /* Check if HLE prefix is OK. */
3674 if (i
.hle_prefix
&& !check_hle ())
3677 /* Check BND prefix. */
3678 if (i
.bnd_prefix
&& !i
.tm
.opcode_modifier
.bndprefixok
)
3679 as_bad (_("expecting valid branch instruction after `bnd'"));
3681 if (i
.tm
.cpu_flags
.bitfield
.cpumpx
)
3683 if (flag_code
== CODE_64BIT
&& i
.prefix
[ADDR_PREFIX
])
3684 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
3685 else if (flag_code
!= CODE_16BIT
3686 ? i
.prefix
[ADDR_PREFIX
]
3687 : i
.mem_operands
&& !i
.prefix
[ADDR_PREFIX
])
3688 as_bad (_("16-bit address isn't allowed in MPX instructions"));
3691 /* Insert BND prefix. */
3693 && i
.tm
.opcode_modifier
.bndprefixok
3694 && !i
.prefix
[BND_PREFIX
])
3695 add_prefix (BND_PREFIX_OPCODE
);
3697 /* Check string instruction segment overrides. */
3698 if (i
.tm
.opcode_modifier
.isstring
&& i
.mem_operands
!= 0)
3700 if (!check_string ())
3702 i
.disp_operands
= 0;
3705 if (!process_suffix ())
3708 /* Update operand types. */
3709 for (j
= 0; j
< i
.operands
; j
++)
3710 i
.types
[j
] = operand_type_and (i
.types
[j
], i
.tm
.operand_types
[j
]);
3712 /* Make still unresolved immediate matches conform to size of immediate
3713 given in i.suffix. */
3714 if (!finalize_imm ())
3717 if (i
.types
[0].bitfield
.imm1
)
3718 i
.imm_operands
= 0; /* kludge for shift insns. */
3720 /* We only need to check those implicit registers for instructions
3721 with 3 operands or less. */
3722 if (i
.operands
<= 3)
3723 for (j
= 0; j
< i
.operands
; j
++)
3724 if (i
.types
[j
].bitfield
.inoutportreg
3725 || i
.types
[j
].bitfield
.shiftcount
3726 || i
.types
[j
].bitfield
.acc
3727 || i
.types
[j
].bitfield
.floatacc
)
3730 /* ImmExt should be processed after SSE2AVX. */
3731 if (!i
.tm
.opcode_modifier
.sse2avx
3732 && i
.tm
.opcode_modifier
.immext
)
3735 /* For insns with operands there are more diddles to do to the opcode. */
3738 if (!process_operands ())
3741 else if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
3743 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
3744 as_warn (_("translating to `%sp'"), i
.tm
.name
);
3747 if (i
.tm
.opcode_modifier
.vex
|| i
.tm
.opcode_modifier
.evex
)
3749 if (flag_code
== CODE_16BIT
)
3751 as_bad (_("instruction `%s' isn't supported in 16-bit mode."),
3756 if (i
.tm
.opcode_modifier
.vex
)
3757 build_vex_prefix (t
);
3759 build_evex_prefix ();
3762 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
3763 instructions may define INT_OPCODE as well, so avoid this corner
3764 case for those instructions that use MODRM. */
3765 if (i
.tm
.base_opcode
== INT_OPCODE
3766 && !i
.tm
.opcode_modifier
.modrm
3767 && i
.op
[0].imms
->X_add_number
== 3)
3769 i
.tm
.base_opcode
= INT3_OPCODE
;
3773 if ((i
.tm
.opcode_modifier
.jump
3774 || i
.tm
.opcode_modifier
.jumpbyte
3775 || i
.tm
.opcode_modifier
.jumpdword
)
3776 && i
.op
[0].disps
->X_op
== O_constant
)
3778 /* Convert "jmp constant" (and "call constant") to a jump (call) to
3779 the absolute address given by the constant. Since ix86 jumps and
3780 calls are pc relative, we need to generate a reloc. */
3781 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
3782 i
.op
[0].disps
->X_op
= O_symbol
;
3785 if (i
.tm
.opcode_modifier
.rex64
)
3788 /* For 8 bit registers we need an empty rex prefix. Also if the
3789 instruction already has a prefix, we need to convert old
3790 registers to new ones. */
3792 if ((i
.types
[0].bitfield
.reg8
3793 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
3794 || (i
.types
[1].bitfield
.reg8
3795 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
3796 || ((i
.types
[0].bitfield
.reg8
3797 || i
.types
[1].bitfield
.reg8
)
3802 i
.rex
|= REX_OPCODE
;
3803 for (x
= 0; x
< 2; x
++)
3805 /* Look for 8 bit operand that uses old registers. */
3806 if (i
.types
[x
].bitfield
.reg8
3807 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
3809 /* In case it is "hi" register, give up. */
3810 if (i
.op
[x
].regs
->reg_num
> 3)
3811 as_bad (_("can't encode register '%s%s' in an "
3812 "instruction requiring REX prefix."),
3813 register_prefix
, i
.op
[x
].regs
->reg_name
);
3815 /* Otherwise it is equivalent to the extended register.
3816 Since the encoding doesn't change this is merely
3817 cosmetic cleanup for debug output. */
3819 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
3825 add_prefix (REX_OPCODE
| i
.rex
);
3827 /* We are ready to output the insn. */
3832 parse_insn (char *line
, char *mnemonic
)
3835 char *token_start
= l
;
3838 const insn_template
*t
;
3844 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
3849 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
3851 as_bad (_("no such instruction: `%s'"), token_start
);
3856 if (!is_space_char (*l
)
3857 && *l
!= END_OF_INSN
3859 || (*l
!= PREFIX_SEPARATOR
3862 as_bad (_("invalid character %s in mnemonic"),
3863 output_invalid (*l
));
3866 if (token_start
== l
)
3868 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
3869 as_bad (_("expecting prefix; got nothing"));
3871 as_bad (_("expecting mnemonic; got nothing"));
3875 /* Look up instruction (or prefix) via hash table. */
3876 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
3878 if (*l
!= END_OF_INSN
3879 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
3880 && current_templates
3881 && current_templates
->start
->opcode_modifier
.isprefix
)
3883 if (!cpu_flags_check_cpu64 (current_templates
->start
->cpu_flags
))
3885 as_bad ((flag_code
!= CODE_64BIT
3886 ? _("`%s' is only supported in 64-bit mode")
3887 : _("`%s' is not supported in 64-bit mode")),
3888 current_templates
->start
->name
);
3891 /* If we are in 16-bit mode, do not allow addr16 or data16.
3892 Similarly, in 32-bit mode, do not allow addr32 or data32. */
3893 if ((current_templates
->start
->opcode_modifier
.size16
3894 || current_templates
->start
->opcode_modifier
.size32
)
3895 && flag_code
!= CODE_64BIT
3896 && (current_templates
->start
->opcode_modifier
.size32
3897 ^ (flag_code
== CODE_16BIT
)))
3899 as_bad (_("redundant %s prefix"),
3900 current_templates
->start
->name
);
3903 /* Add prefix, checking for repeated prefixes. */
3904 switch (add_prefix (current_templates
->start
->base_opcode
))
3909 if (current_templates
->start
->cpu_flags
.bitfield
.cpuhle
)
3910 i
.hle_prefix
= current_templates
->start
->name
;
3911 else if (current_templates
->start
->cpu_flags
.bitfield
.cpumpx
)
3912 i
.bnd_prefix
= current_templates
->start
->name
;
3914 i
.rep_prefix
= current_templates
->start
->name
;
3919 /* Skip past PREFIX_SEPARATOR and reset token_start. */
3926 if (!current_templates
)
3928 /* Check if we should swap operand or force 32bit displacement in
3930 if (mnem_p
- 2 == dot_p
&& dot_p
[1] == 's')
3932 else if (mnem_p
- 3 == dot_p
3935 i
.disp_encoding
= disp_encoding_8bit
;
3936 else if (mnem_p
- 4 == dot_p
3940 i
.disp_encoding
= disp_encoding_32bit
;
3945 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
3948 if (!current_templates
)
3951 /* See if we can get a match by trimming off a suffix. */
3954 case WORD_MNEM_SUFFIX
:
3955 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
3956 i
.suffix
= SHORT_MNEM_SUFFIX
;
3959 case BYTE_MNEM_SUFFIX
:
3960 case QWORD_MNEM_SUFFIX
:
3961 i
.suffix
= mnem_p
[-1];
3963 current_templates
= (const templates
*) hash_find (op_hash
,
3966 case SHORT_MNEM_SUFFIX
:
3967 case LONG_MNEM_SUFFIX
:
3970 i
.suffix
= mnem_p
[-1];
3972 current_templates
= (const templates
*) hash_find (op_hash
,
3981 if (intel_float_operand (mnemonic
) == 1)
3982 i
.suffix
= SHORT_MNEM_SUFFIX
;
3984 i
.suffix
= LONG_MNEM_SUFFIX
;
3986 current_templates
= (const templates
*) hash_find (op_hash
,
3991 if (!current_templates
)
3993 as_bad (_("no such instruction: `%s'"), token_start
);
3998 if (current_templates
->start
->opcode_modifier
.jump
3999 || current_templates
->start
->opcode_modifier
.jumpbyte
)
4001 /* Check for a branch hint. We allow ",pt" and ",pn" for
4002 predict taken and predict not taken respectively.
4003 I'm not sure that branch hints actually do anything on loop
4004 and jcxz insns (JumpByte) for current Pentium4 chips. They
4005 may work in the future and it doesn't hurt to accept them
4007 if (l
[0] == ',' && l
[1] == 'p')
4011 if (!add_prefix (DS_PREFIX_OPCODE
))
4015 else if (l
[2] == 'n')
4017 if (!add_prefix (CS_PREFIX_OPCODE
))
4023 /* Any other comma loses. */
4026 as_bad (_("invalid character %s in mnemonic"),
4027 output_invalid (*l
));
4031 /* Check if instruction is supported on specified architecture. */
4033 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
4035 supported
|= cpu_flags_match (t
);
4036 if (supported
== CPU_FLAGS_PERFECT_MATCH
)
4040 if (!(supported
& CPU_FLAGS_64BIT_MATCH
))
4042 as_bad (flag_code
== CODE_64BIT
4043 ? _("`%s' is not supported in 64-bit mode")
4044 : _("`%s' is only supported in 64-bit mode"),
4045 current_templates
->start
->name
);
4048 if (supported
!= CPU_FLAGS_PERFECT_MATCH
)
4050 as_bad (_("`%s' is not supported on `%s%s'"),
4051 current_templates
->start
->name
,
4052 cpu_arch_name
? cpu_arch_name
: default_arch
,
4053 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
4058 if (!cpu_arch_flags
.bitfield
.cpui386
4059 && (flag_code
!= CODE_16BIT
))
4061 as_warn (_("use .code16 to ensure correct addressing mode"));
4068 parse_operands (char *l
, const char *mnemonic
)
4072 /* 1 if operand is pending after ','. */
4073 unsigned int expecting_operand
= 0;
4075 /* Non-zero if operand parens not balanced. */
4076 unsigned int paren_not_balanced
;
4078 while (*l
!= END_OF_INSN
)
4080 /* Skip optional white space before operand. */
4081 if (is_space_char (*l
))
4083 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
&& *l
!= '"')
4085 as_bad (_("invalid character %s before operand %d"),
4086 output_invalid (*l
),
4090 token_start
= l
; /* After white space. */
4091 paren_not_balanced
= 0;
4092 while (paren_not_balanced
|| *l
!= ',')
4094 if (*l
== END_OF_INSN
)
4096 if (paren_not_balanced
)
4099 as_bad (_("unbalanced parenthesis in operand %d."),
4102 as_bad (_("unbalanced brackets in operand %d."),
4107 break; /* we are done */
4109 else if (!is_operand_char (*l
) && !is_space_char (*l
) && *l
!= '"')
4111 as_bad (_("invalid character %s in operand %d"),
4112 output_invalid (*l
),
4119 ++paren_not_balanced
;
4121 --paren_not_balanced
;
4126 ++paren_not_balanced
;
4128 --paren_not_balanced
;
4132 if (l
!= token_start
)
4133 { /* Yes, we've read in another operand. */
4134 unsigned int operand_ok
;
4135 this_operand
= i
.operands
++;
4136 i
.types
[this_operand
].bitfield
.unspecified
= 1;
4137 if (i
.operands
> MAX_OPERANDS
)
4139 as_bad (_("spurious operands; (%d operands/instruction max)"),
4143 /* Now parse operand adding info to 'i' as we go along. */
4144 END_STRING_AND_SAVE (l
);
4148 i386_intel_operand (token_start
,
4149 intel_float_operand (mnemonic
));
4151 operand_ok
= i386_att_operand (token_start
);
4153 RESTORE_END_STRING (l
);
4159 if (expecting_operand
)
4161 expecting_operand_after_comma
:
4162 as_bad (_("expecting operand after ','; got nothing"));
4167 as_bad (_("expecting operand before ','; got nothing"));
4172 /* Now *l must be either ',' or END_OF_INSN. */
4175 if (*++l
== END_OF_INSN
)
4177 /* Just skip it, if it's \n complain. */
4178 goto expecting_operand_after_comma
;
4180 expecting_operand
= 1;
4187 swap_2_operands (int xchg1
, int xchg2
)
4189 union i386_op temp_op
;
4190 i386_operand_type temp_type
;
4191 enum bfd_reloc_code_real temp_reloc
;
4193 temp_type
= i
.types
[xchg2
];
4194 i
.types
[xchg2
] = i
.types
[xchg1
];
4195 i
.types
[xchg1
] = temp_type
;
4196 temp_op
= i
.op
[xchg2
];
4197 i
.op
[xchg2
] = i
.op
[xchg1
];
4198 i
.op
[xchg1
] = temp_op
;
4199 temp_reloc
= i
.reloc
[xchg2
];
4200 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
4201 i
.reloc
[xchg1
] = temp_reloc
;
4205 if (i
.mask
->operand
== xchg1
)
4206 i
.mask
->operand
= xchg2
;
4207 else if (i
.mask
->operand
== xchg2
)
4208 i
.mask
->operand
= xchg1
;
4212 if (i
.broadcast
->operand
== xchg1
)
4213 i
.broadcast
->operand
= xchg2
;
4214 else if (i
.broadcast
->operand
== xchg2
)
4215 i
.broadcast
->operand
= xchg1
;
4219 if (i
.rounding
->operand
== xchg1
)
4220 i
.rounding
->operand
= xchg2
;
4221 else if (i
.rounding
->operand
== xchg2
)
4222 i
.rounding
->operand
= xchg1
;
4227 swap_operands (void)
4233 swap_2_operands (1, i
.operands
- 2);
4237 swap_2_operands (0, i
.operands
- 1);
4243 if (i
.mem_operands
== 2)
4245 const seg_entry
*temp_seg
;
4246 temp_seg
= i
.seg
[0];
4247 i
.seg
[0] = i
.seg
[1];
4248 i
.seg
[1] = temp_seg
;
4252 /* Try to ensure constant immediates are represented in the smallest
4257 char guess_suffix
= 0;
4261 guess_suffix
= i
.suffix
;
4262 else if (i
.reg_operands
)
4264 /* Figure out a suffix from the last register operand specified.
4265 We can't do this properly yet, ie. excluding InOutPortReg,
4266 but the following works for instructions with immediates.
4267 In any case, we can't set i.suffix yet. */
4268 for (op
= i
.operands
; --op
>= 0;)
4269 if (i
.types
[op
].bitfield
.reg8
)
4271 guess_suffix
= BYTE_MNEM_SUFFIX
;
4274 else if (i
.types
[op
].bitfield
.reg16
)
4276 guess_suffix
= WORD_MNEM_SUFFIX
;
4279 else if (i
.types
[op
].bitfield
.reg32
)
4281 guess_suffix
= LONG_MNEM_SUFFIX
;
4284 else if (i
.types
[op
].bitfield
.reg64
)
4286 guess_suffix
= QWORD_MNEM_SUFFIX
;
4290 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
4291 guess_suffix
= WORD_MNEM_SUFFIX
;
4293 for (op
= i
.operands
; --op
>= 0;)
4294 if (operand_type_check (i
.types
[op
], imm
))
4296 switch (i
.op
[op
].imms
->X_op
)
4299 /* If a suffix is given, this operand may be shortened. */
4300 switch (guess_suffix
)
4302 case LONG_MNEM_SUFFIX
:
4303 i
.types
[op
].bitfield
.imm32
= 1;
4304 i
.types
[op
].bitfield
.imm64
= 1;
4306 case WORD_MNEM_SUFFIX
:
4307 i
.types
[op
].bitfield
.imm16
= 1;
4308 i
.types
[op
].bitfield
.imm32
= 1;
4309 i
.types
[op
].bitfield
.imm32s
= 1;
4310 i
.types
[op
].bitfield
.imm64
= 1;
4312 case BYTE_MNEM_SUFFIX
:
4313 i
.types
[op
].bitfield
.imm8
= 1;
4314 i
.types
[op
].bitfield
.imm8s
= 1;
4315 i
.types
[op
].bitfield
.imm16
= 1;
4316 i
.types
[op
].bitfield
.imm32
= 1;
4317 i
.types
[op
].bitfield
.imm32s
= 1;
4318 i
.types
[op
].bitfield
.imm64
= 1;
4322 /* If this operand is at most 16 bits, convert it
4323 to a signed 16 bit number before trying to see
4324 whether it will fit in an even smaller size.
4325 This allows a 16-bit operand such as $0xffe0 to
4326 be recognised as within Imm8S range. */
4327 if ((i
.types
[op
].bitfield
.imm16
)
4328 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
4330 i
.op
[op
].imms
->X_add_number
=
4331 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
4334 /* Store 32-bit immediate in 64-bit for 64-bit BFD. */
4335 if ((i
.types
[op
].bitfield
.imm32
)
4336 && ((i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1))
4339 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
4340 ^ ((offsetT
) 1 << 31))
4341 - ((offsetT
) 1 << 31));
4345 = operand_type_or (i
.types
[op
],
4346 smallest_imm_type (i
.op
[op
].imms
->X_add_number
));
4348 /* We must avoid matching of Imm32 templates when 64bit
4349 only immediate is available. */
4350 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
4351 i
.types
[op
].bitfield
.imm32
= 0;
4358 /* Symbols and expressions. */
4360 /* Convert symbolic operand to proper sizes for matching, but don't
4361 prevent matching a set of insns that only supports sizes other
4362 than those matching the insn suffix. */
4364 i386_operand_type mask
, allowed
;
4365 const insn_template
*t
;
4367 operand_type_set (&mask
, 0);
4368 operand_type_set (&allowed
, 0);
4370 for (t
= current_templates
->start
;
4371 t
< current_templates
->end
;
4373 allowed
= operand_type_or (allowed
,
4374 t
->operand_types
[op
]);
4375 switch (guess_suffix
)
4377 case QWORD_MNEM_SUFFIX
:
4378 mask
.bitfield
.imm64
= 1;
4379 mask
.bitfield
.imm32s
= 1;
4381 case LONG_MNEM_SUFFIX
:
4382 mask
.bitfield
.imm32
= 1;
4384 case WORD_MNEM_SUFFIX
:
4385 mask
.bitfield
.imm16
= 1;
4387 case BYTE_MNEM_SUFFIX
:
4388 mask
.bitfield
.imm8
= 1;
4393 allowed
= operand_type_and (mask
, allowed
);
4394 if (!operand_type_all_zero (&allowed
))
4395 i
.types
[op
] = operand_type_and (i
.types
[op
], mask
);
4402 /* Try to use the smallest displacement type too. */
4404 optimize_disp (void)
4408 for (op
= i
.operands
; --op
>= 0;)
4409 if (operand_type_check (i
.types
[op
], disp
))
4411 if (i
.op
[op
].disps
->X_op
== O_constant
)
4413 offsetT op_disp
= i
.op
[op
].disps
->X_add_number
;
4415 if (i
.types
[op
].bitfield
.disp16
4416 && (op_disp
& ~(offsetT
) 0xffff) == 0)
4418 /* If this operand is at most 16 bits, convert
4419 to a signed 16 bit number and don't use 64bit
4421 op_disp
= (((op_disp
& 0xffff) ^ 0x8000) - 0x8000);
4422 i
.types
[op
].bitfield
.disp64
= 0;
4425 /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */
4426 if (i
.types
[op
].bitfield
.disp32
4427 && (op_disp
& ~(((offsetT
) 2 << 31) - 1)) == 0)
4429 /* If this operand is at most 32 bits, convert
4430 to a signed 32 bit number and don't use 64bit
4432 op_disp
&= (((offsetT
) 2 << 31) - 1);
4433 op_disp
= (op_disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
4434 i
.types
[op
].bitfield
.disp64
= 0;
4437 if (!op_disp
&& i
.types
[op
].bitfield
.baseindex
)
4439 i
.types
[op
].bitfield
.disp8
= 0;
4440 i
.types
[op
].bitfield
.disp16
= 0;
4441 i
.types
[op
].bitfield
.disp32
= 0;
4442 i
.types
[op
].bitfield
.disp32s
= 0;
4443 i
.types
[op
].bitfield
.disp64
= 0;
4447 else if (flag_code
== CODE_64BIT
)
4449 if (fits_in_signed_long (op_disp
))
4451 i
.types
[op
].bitfield
.disp64
= 0;
4452 i
.types
[op
].bitfield
.disp32s
= 1;
4454 if (i
.prefix
[ADDR_PREFIX
]
4455 && fits_in_unsigned_long (op_disp
))
4456 i
.types
[op
].bitfield
.disp32
= 1;
4458 if ((i
.types
[op
].bitfield
.disp32
4459 || i
.types
[op
].bitfield
.disp32s
4460 || i
.types
[op
].bitfield
.disp16
)
4461 && fits_in_signed_byte (op_disp
))
4462 i
.types
[op
].bitfield
.disp8
= 1;
4464 else if (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
4465 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
)
4467 fix_new_exp (frag_now
, frag_more (0) - frag_now
->fr_literal
, 0,
4468 i
.op
[op
].disps
, 0, i
.reloc
[op
]);
4469 i
.types
[op
].bitfield
.disp8
= 0;
4470 i
.types
[op
].bitfield
.disp16
= 0;
4471 i
.types
[op
].bitfield
.disp32
= 0;
4472 i
.types
[op
].bitfield
.disp32s
= 0;
4473 i
.types
[op
].bitfield
.disp64
= 0;
4476 /* We only support 64bit displacement on constants. */
4477 i
.types
[op
].bitfield
.disp64
= 0;
4481 /* Check if operands are valid for the instruction. */
4484 check_VecOperands (const insn_template
*t
)
4488 /* Without VSIB byte, we can't have a vector register for index. */
4489 if (!t
->opcode_modifier
.vecsib
4491 && (i
.index_reg
->reg_type
.bitfield
.regxmm
4492 || i
.index_reg
->reg_type
.bitfield
.regymm
4493 || i
.index_reg
->reg_type
.bitfield
.regzmm
))
4495 i
.error
= unsupported_vector_index_register
;
4499 /* Check if default mask is allowed. */
4500 if (t
->opcode_modifier
.nodefmask
4501 && (!i
.mask
|| i
.mask
->mask
->reg_num
== 0))
4503 i
.error
= no_default_mask
;
4507 /* For VSIB byte, we need a vector register for index, and all vector
4508 registers must be distinct. */
4509 if (t
->opcode_modifier
.vecsib
)
4512 || !((t
->opcode_modifier
.vecsib
== VecSIB128
4513 && i
.index_reg
->reg_type
.bitfield
.regxmm
)
4514 || (t
->opcode_modifier
.vecsib
== VecSIB256
4515 && i
.index_reg
->reg_type
.bitfield
.regymm
)
4516 || (t
->opcode_modifier
.vecsib
== VecSIB512
4517 && i
.index_reg
->reg_type
.bitfield
.regzmm
)))
4519 i
.error
= invalid_vsib_address
;
4523 gas_assert (i
.reg_operands
== 2 || i
.mask
);
4524 if (i
.reg_operands
== 2 && !i
.mask
)
4526 gas_assert (i
.types
[0].bitfield
.regxmm
4527 || i
.types
[0].bitfield
.regymm
);
4528 gas_assert (i
.types
[2].bitfield
.regxmm
4529 || i
.types
[2].bitfield
.regymm
);
4530 if (operand_check
== check_none
)
4532 if (register_number (i
.op
[0].regs
)
4533 != register_number (i
.index_reg
)
4534 && register_number (i
.op
[2].regs
)
4535 != register_number (i
.index_reg
)
4536 && register_number (i
.op
[0].regs
)
4537 != register_number (i
.op
[2].regs
))
4539 if (operand_check
== check_error
)
4541 i
.error
= invalid_vector_register_set
;
4544 as_warn (_("mask, index, and destination registers should be distinct"));
4546 else if (i
.reg_operands
== 1 && i
.mask
)
4548 if ((i
.types
[1].bitfield
.regymm
4549 || i
.types
[1].bitfield
.regzmm
)
4550 && (register_number (i
.op
[1].regs
)
4551 == register_number (i
.index_reg
)))
4553 if (operand_check
== check_error
)
4555 i
.error
= invalid_vector_register_set
;
4558 if (operand_check
!= check_none
)
4559 as_warn (_("index and destination registers should be distinct"));
4564 /* Check if broadcast is supported by the instruction and is applied
4565 to the memory operand. */
4568 int broadcasted_opnd_size
;
4570 /* Check if specified broadcast is supported in this instruction,
4571 and it's applied to memory operand of DWORD or QWORD type,
4572 depending on VecESize. */
4573 if (i
.broadcast
->type
!= t
->opcode_modifier
.broadcast
4574 || !i
.types
[i
.broadcast
->operand
].bitfield
.mem
4575 || (t
->opcode_modifier
.vecesize
== 0
4576 && !i
.types
[i
.broadcast
->operand
].bitfield
.dword
4577 && !i
.types
[i
.broadcast
->operand
].bitfield
.unspecified
)
4578 || (t
->opcode_modifier
.vecesize
== 1
4579 && !i
.types
[i
.broadcast
->operand
].bitfield
.qword
4580 && !i
.types
[i
.broadcast
->operand
].bitfield
.unspecified
))
4583 broadcasted_opnd_size
= t
->opcode_modifier
.vecesize
? 64 : 32;
4584 if (i
.broadcast
->type
== BROADCAST_1TO16
)
4585 broadcasted_opnd_size
<<= 4; /* Broadcast 1to16. */
4586 else if (i
.broadcast
->type
== BROADCAST_1TO8
)
4587 broadcasted_opnd_size
<<= 3; /* Broadcast 1to8. */
4588 else if (i
.broadcast
->type
== BROADCAST_1TO4
)
4589 broadcasted_opnd_size
<<= 2; /* Broadcast 1to4. */
4590 else if (i
.broadcast
->type
== BROADCAST_1TO2
)
4591 broadcasted_opnd_size
<<= 1; /* Broadcast 1to2. */
4595 if ((broadcasted_opnd_size
== 256
4596 && !t
->operand_types
[i
.broadcast
->operand
].bitfield
.ymmword
)
4597 || (broadcasted_opnd_size
== 512
4598 && !t
->operand_types
[i
.broadcast
->operand
].bitfield
.zmmword
))
4601 i
.error
= unsupported_broadcast
;
4605 /* If broadcast is supported in this instruction, we need to check if
4606 operand of one-element size isn't specified without broadcast. */
4607 else if (t
->opcode_modifier
.broadcast
&& i
.mem_operands
)
4609 /* Find memory operand. */
4610 for (op
= 0; op
< i
.operands
; op
++)
4611 if (operand_type_check (i
.types
[op
], anymem
))
4613 gas_assert (op
< i
.operands
);
4614 /* Check size of the memory operand. */
4615 if ((t
->opcode_modifier
.vecesize
== 0
4616 && i
.types
[op
].bitfield
.dword
)
4617 || (t
->opcode_modifier
.vecesize
== 1
4618 && i
.types
[op
].bitfield
.qword
))
4620 i
.error
= broadcast_needed
;
4625 /* Check if requested masking is supported. */
4627 && (!t
->opcode_modifier
.masking
4629 && t
->opcode_modifier
.masking
== MERGING_MASKING
)))
4631 i
.error
= unsupported_masking
;
4635 /* Check if masking is applied to dest operand. */
4636 if (i
.mask
&& (i
.mask
->operand
!= (int) (i
.operands
- 1)))
4638 i
.error
= mask_not_on_destination
;
4645 if ((i
.rounding
->type
!= saeonly
4646 && !t
->opcode_modifier
.staticrounding
)
4647 || (i
.rounding
->type
== saeonly
4648 && (t
->opcode_modifier
.staticrounding
4649 || !t
->opcode_modifier
.sae
)))
4651 i
.error
= unsupported_rc_sae
;
4654 /* If the instruction has several immediate operands and one of
4655 them is rounding, the rounding operand should be the last
4656 immediate operand. */
4657 if (i
.imm_operands
> 1
4658 && i
.rounding
->operand
!= (int) (i
.imm_operands
- 1))
4660 i
.error
= rc_sae_operand_not_last_imm
;
4665 /* Check vector Disp8 operand. */
4666 if (t
->opcode_modifier
.disp8memshift
)
4669 i
.memshift
= t
->opcode_modifier
.vecesize
? 3 : 2;
4671 i
.memshift
= t
->opcode_modifier
.disp8memshift
;
4673 for (op
= 0; op
< i
.operands
; op
++)
4674 if (operand_type_check (i
.types
[op
], disp
)
4675 && i
.op
[op
].disps
->X_op
== O_constant
)
4677 offsetT value
= i
.op
[op
].disps
->X_add_number
;
4679 = (i
.disp_encoding
!= disp_encoding_32bit
4680 && fits_in_vec_disp8 (value
));
4681 if (t
->operand_types
[op
].bitfield
.vec_disp8
)
4684 i
.types
[op
].bitfield
.vec_disp8
= 1;
4687 /* Vector insn can only have Vec_Disp8/Disp32 in
4688 32/64bit modes, and Vec_Disp8/Disp16 in 16bit
4690 i
.types
[op
].bitfield
.disp8
= 0;
4691 if (flag_code
!= CODE_16BIT
)
4692 i
.types
[op
].bitfield
.disp16
= 0;
4695 else if (flag_code
!= CODE_16BIT
)
4697 /* One form of this instruction supports vector Disp8.
4698 Try vector Disp8 if we need to use Disp32. */
4699 if (vec_disp8_ok
&& !fits_in_signed_byte (value
))
4701 i
.error
= try_vector_disp8
;
4713 /* Check if operands are valid for the instruction. Update VEX
4717 VEX_check_operands (const insn_template
*t
)
4719 /* VREX is only valid with EVEX prefix. */
4720 if (i
.need_vrex
&& !t
->opcode_modifier
.evex
)
4722 i
.error
= invalid_register_operand
;
4726 if (!t
->opcode_modifier
.vex
)
4729 /* Only check VEX_Imm4, which must be the first operand. */
4730 if (t
->operand_types
[0].bitfield
.vec_imm4
)
4732 if (i
.op
[0].imms
->X_op
!= O_constant
4733 || !fits_in_imm4 (i
.op
[0].imms
->X_add_number
))
4739 /* Turn off Imm8 so that update_imm won't complain. */
4740 i
.types
[0] = vec_imm4
;
4746 static const insn_template
*
4747 match_template (char mnem_suffix
)
4749 /* Points to template once we've found it. */
4750 const insn_template
*t
;
4751 i386_operand_type overlap0
, overlap1
, overlap2
, overlap3
;
4752 i386_operand_type overlap4
;
4753 unsigned int found_reverse_match
;
4754 i386_opcode_modifier suffix_check
, mnemsuf_check
;
4755 i386_operand_type operand_types
[MAX_OPERANDS
];
4756 int addr_prefix_disp
;
4758 unsigned int found_cpu_match
;
4759 unsigned int check_register
;
4760 enum i386_error specific_error
= 0;
4762 #if MAX_OPERANDS != 5
4763 # error "MAX_OPERANDS must be 5."
4766 found_reverse_match
= 0;
4767 addr_prefix_disp
= -1;
4769 memset (&suffix_check
, 0, sizeof (suffix_check
));
4770 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
4771 suffix_check
.no_bsuf
= 1;
4772 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
4773 suffix_check
.no_wsuf
= 1;
4774 else if (i
.suffix
== SHORT_MNEM_SUFFIX
)
4775 suffix_check
.no_ssuf
= 1;
4776 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
4777 suffix_check
.no_lsuf
= 1;
4778 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
4779 suffix_check
.no_qsuf
= 1;
4780 else if (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
)
4781 suffix_check
.no_ldsuf
= 1;
4783 memset (&mnemsuf_check
, 0, sizeof (mnemsuf_check
));
4786 switch (mnem_suffix
)
4788 case BYTE_MNEM_SUFFIX
: mnemsuf_check
.no_bsuf
= 1; break;
4789 case WORD_MNEM_SUFFIX
: mnemsuf_check
.no_wsuf
= 1; break;
4790 case SHORT_MNEM_SUFFIX
: mnemsuf_check
.no_ssuf
= 1; break;
4791 case LONG_MNEM_SUFFIX
: mnemsuf_check
.no_lsuf
= 1; break;
4792 case QWORD_MNEM_SUFFIX
: mnemsuf_check
.no_qsuf
= 1; break;
4796 /* Must have right number of operands. */
4797 i
.error
= number_of_operands_mismatch
;
4799 for (t
= current_templates
->start
; t
< current_templates
->end
; t
++)
4801 addr_prefix_disp
= -1;
4803 if (i
.operands
!= t
->operands
)
4806 /* Check processor support. */
4807 i
.error
= unsupported
;
4808 found_cpu_match
= (cpu_flags_match (t
)
4809 == CPU_FLAGS_PERFECT_MATCH
);
4810 if (!found_cpu_match
)
4813 /* Check old gcc support. */
4814 i
.error
= old_gcc_only
;
4815 if (!old_gcc
&& t
->opcode_modifier
.oldgcc
)
4818 /* Check AT&T mnemonic. */
4819 i
.error
= unsupported_with_intel_mnemonic
;
4820 if (intel_mnemonic
&& t
->opcode_modifier
.attmnemonic
)
4823 /* Check AT&T/Intel syntax and Intel64/AMD64 ISA. */
4824 i
.error
= unsupported_syntax
;
4825 if ((intel_syntax
&& t
->opcode_modifier
.attsyntax
)
4826 || (!intel_syntax
&& t
->opcode_modifier
.intelsyntax
)
4827 || (intel64
&& t
->opcode_modifier
.amd64
)
4828 || (!intel64
&& t
->opcode_modifier
.intel64
))
4831 /* Check the suffix, except for some instructions in intel mode. */
4832 i
.error
= invalid_instruction_suffix
;
4833 if ((!intel_syntax
|| !t
->opcode_modifier
.ignoresize
)
4834 && ((t
->opcode_modifier
.no_bsuf
&& suffix_check
.no_bsuf
)
4835 || (t
->opcode_modifier
.no_wsuf
&& suffix_check
.no_wsuf
)
4836 || (t
->opcode_modifier
.no_lsuf
&& suffix_check
.no_lsuf
)
4837 || (t
->opcode_modifier
.no_ssuf
&& suffix_check
.no_ssuf
)
4838 || (t
->opcode_modifier
.no_qsuf
&& suffix_check
.no_qsuf
)
4839 || (t
->opcode_modifier
.no_ldsuf
&& suffix_check
.no_ldsuf
)))
4841 /* In Intel mode all mnemonic suffixes must be explicitly allowed. */
4842 if ((t
->opcode_modifier
.no_bsuf
&& mnemsuf_check
.no_bsuf
)
4843 || (t
->opcode_modifier
.no_wsuf
&& mnemsuf_check
.no_wsuf
)
4844 || (t
->opcode_modifier
.no_lsuf
&& mnemsuf_check
.no_lsuf
)
4845 || (t
->opcode_modifier
.no_ssuf
&& mnemsuf_check
.no_ssuf
)
4846 || (t
->opcode_modifier
.no_qsuf
&& mnemsuf_check
.no_qsuf
)
4847 || (t
->opcode_modifier
.no_ldsuf
&& mnemsuf_check
.no_ldsuf
))
4850 if (!operand_size_match (t
))
4853 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4854 operand_types
[j
] = t
->operand_types
[j
];
4856 /* In general, don't allow 64-bit operands in 32-bit mode. */
4857 if (i
.suffix
== QWORD_MNEM_SUFFIX
4858 && flag_code
!= CODE_64BIT
4860 ? (!t
->opcode_modifier
.ignoresize
4861 && !intel_float_operand (t
->name
))
4862 : intel_float_operand (t
->name
) != 2)
4863 && ((!operand_types
[0].bitfield
.regmmx
4864 && !operand_types
[0].bitfield
.regxmm
4865 && !operand_types
[0].bitfield
.regymm
4866 && !operand_types
[0].bitfield
.regzmm
)
4867 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
4868 && operand_types
[t
->operands
> 1].bitfield
.regxmm
4869 && operand_types
[t
->operands
> 1].bitfield
.regymm
4870 && operand_types
[t
->operands
> 1].bitfield
.regzmm
))
4871 && (t
->base_opcode
!= 0x0fc7
4872 || t
->extension_opcode
!= 1 /* cmpxchg8b */))
4875 /* In general, don't allow 32-bit operands on pre-386. */
4876 else if (i
.suffix
== LONG_MNEM_SUFFIX
4877 && !cpu_arch_flags
.bitfield
.cpui386
4879 ? (!t
->opcode_modifier
.ignoresize
4880 && !intel_float_operand (t
->name
))
4881 : intel_float_operand (t
->name
) != 2)
4882 && ((!operand_types
[0].bitfield
.regmmx
4883 && !operand_types
[0].bitfield
.regxmm
)
4884 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
4885 && operand_types
[t
->operands
> 1].bitfield
.regxmm
)))
4888 /* Do not verify operands when there are none. */
4892 /* We've found a match; break out of loop. */
4896 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
4897 into Disp32/Disp16/Disp32 operand. */
4898 if (i
.prefix
[ADDR_PREFIX
] != 0)
4900 /* There should be only one Disp operand. */
4904 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4906 if (operand_types
[j
].bitfield
.disp16
)
4908 addr_prefix_disp
= j
;
4909 operand_types
[j
].bitfield
.disp32
= 1;
4910 operand_types
[j
].bitfield
.disp16
= 0;
4916 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4918 if (operand_types
[j
].bitfield
.disp32
)
4920 addr_prefix_disp
= j
;
4921 operand_types
[j
].bitfield
.disp32
= 0;
4922 operand_types
[j
].bitfield
.disp16
= 1;
4928 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4930 if (operand_types
[j
].bitfield
.disp64
)
4932 addr_prefix_disp
= j
;
4933 operand_types
[j
].bitfield
.disp64
= 0;
4934 operand_types
[j
].bitfield
.disp32
= 1;
4942 /* Force 0x8b encoding for "mov foo@GOT, %eax". */
4943 if (i
.reloc
[0] == BFD_RELOC_386_GOT32
&& t
->base_opcode
== 0xa0)
4946 /* We check register size if needed. */
4947 check_register
= t
->opcode_modifier
.checkregsize
;
4948 overlap0
= operand_type_and (i
.types
[0], operand_types
[0]);
4949 switch (t
->operands
)
4952 if (!operand_type_match (overlap0
, i
.types
[0]))
4956 /* xchg %eax, %eax is a special case. It is an aliase for nop
4957 only in 32bit mode and we can use opcode 0x90. In 64bit
4958 mode, we can't use 0x90 for xchg %eax, %eax since it should
4959 zero-extend %eax to %rax. */
4960 if (flag_code
== CODE_64BIT
4961 && t
->base_opcode
== 0x90
4962 && operand_type_equal (&i
.types
[0], &acc32
)
4963 && operand_type_equal (&i
.types
[1], &acc32
))
4967 /* If we swap operand in encoding, we either match
4968 the next one or reverse direction of operands. */
4969 if (t
->opcode_modifier
.s
)
4971 else if (t
->opcode_modifier
.d
)
4977 /* If we swap operand in encoding, we match the next one. */
4978 if (i
.swap_operand
&& t
->opcode_modifier
.s
)
4983 overlap1
= operand_type_and (i
.types
[1], operand_types
[1]);
4984 if (!operand_type_match (overlap0
, i
.types
[0])
4985 || !operand_type_match (overlap1
, i
.types
[1])
4987 && !operand_type_register_match (overlap0
, i
.types
[0],
4989 overlap1
, i
.types
[1],
4992 /* Check if other direction is valid ... */
4993 if (!t
->opcode_modifier
.d
&& !t
->opcode_modifier
.floatd
)
4997 /* Try reversing direction of operands. */
4998 overlap0
= operand_type_and (i
.types
[0], operand_types
[1]);
4999 overlap1
= operand_type_and (i
.types
[1], operand_types
[0]);
5000 if (!operand_type_match (overlap0
, i
.types
[0])
5001 || !operand_type_match (overlap1
, i
.types
[1])
5003 && !operand_type_register_match (overlap0
,
5010 /* Does not match either direction. */
5013 /* found_reverse_match holds which of D or FloatDR
5015 if (t
->opcode_modifier
.d
)
5016 found_reverse_match
= Opcode_D
;
5017 else if (t
->opcode_modifier
.floatd
)
5018 found_reverse_match
= Opcode_FloatD
;
5020 found_reverse_match
= 0;
5021 if (t
->opcode_modifier
.floatr
)
5022 found_reverse_match
|= Opcode_FloatR
;
5026 /* Found a forward 2 operand match here. */
5027 switch (t
->operands
)
5030 overlap4
= operand_type_and (i
.types
[4],
5034 overlap3
= operand_type_and (i
.types
[3],
5038 overlap2
= operand_type_and (i
.types
[2],
5043 switch (t
->operands
)
5046 if (!operand_type_match (overlap4
, i
.types
[4])
5047 || !operand_type_register_match (overlap3
,
5056 if (!operand_type_match (overlap3
, i
.types
[3])
5058 && !operand_type_register_match (overlap2
,
5067 /* Here we make use of the fact that there are no
5068 reverse match 3 operand instructions, and all 3
5069 operand instructions only need to be checked for
5070 register consistency between operands 2 and 3. */
5071 if (!operand_type_match (overlap2
, i
.types
[2])
5073 && !operand_type_register_match (overlap1
,
5083 /* Found either forward/reverse 2, 3 or 4 operand match here:
5084 slip through to break. */
5086 if (!found_cpu_match
)
5088 found_reverse_match
= 0;
5092 /* Check if vector and VEX operands are valid. */
5093 if (check_VecOperands (t
) || VEX_check_operands (t
))
5095 specific_error
= i
.error
;
5099 /* We've found a match; break out of loop. */
5103 if (t
== current_templates
->end
)
5105 /* We found no match. */
5106 const char *err_msg
;
5107 switch (specific_error
? specific_error
: i
.error
)
5111 case operand_size_mismatch
:
5112 err_msg
= _("operand size mismatch");
5114 case operand_type_mismatch
:
5115 err_msg
= _("operand type mismatch");
5117 case register_type_mismatch
:
5118 err_msg
= _("register type mismatch");
5120 case number_of_operands_mismatch
:
5121 err_msg
= _("number of operands mismatch");
5123 case invalid_instruction_suffix
:
5124 err_msg
= _("invalid instruction suffix");
5127 err_msg
= _("constant doesn't fit in 4 bits");
5130 err_msg
= _("only supported with old gcc");
5132 case unsupported_with_intel_mnemonic
:
5133 err_msg
= _("unsupported with Intel mnemonic");
5135 case unsupported_syntax
:
5136 err_msg
= _("unsupported syntax");
5139 as_bad (_("unsupported instruction `%s'"),
5140 current_templates
->start
->name
);
5142 case invalid_vsib_address
:
5143 err_msg
= _("invalid VSIB address");
5145 case invalid_vector_register_set
:
5146 err_msg
= _("mask, index, and destination registers must be distinct");
5148 case unsupported_vector_index_register
:
5149 err_msg
= _("unsupported vector index register");
5151 case unsupported_broadcast
:
5152 err_msg
= _("unsupported broadcast");
5154 case broadcast_not_on_src_operand
:
5155 err_msg
= _("broadcast not on source memory operand");
5157 case broadcast_needed
:
5158 err_msg
= _("broadcast is needed for operand of such type");
5160 case unsupported_masking
:
5161 err_msg
= _("unsupported masking");
5163 case mask_not_on_destination
:
5164 err_msg
= _("mask not on destination operand");
5166 case no_default_mask
:
5167 err_msg
= _("default mask isn't allowed");
5169 case unsupported_rc_sae
:
5170 err_msg
= _("unsupported static rounding/sae");
5172 case rc_sae_operand_not_last_imm
:
5174 err_msg
= _("RC/SAE operand must precede immediate operands");
5176 err_msg
= _("RC/SAE operand must follow immediate operands");
5178 case invalid_register_operand
:
5179 err_msg
= _("invalid register operand");
5182 as_bad (_("%s for `%s'"), err_msg
,
5183 current_templates
->start
->name
);
5187 if (!quiet_warnings
)
5190 && (i
.types
[0].bitfield
.jumpabsolute
5191 != operand_types
[0].bitfield
.jumpabsolute
))
5193 as_warn (_("indirect %s without `*'"), t
->name
);
5196 if (t
->opcode_modifier
.isprefix
5197 && t
->opcode_modifier
.ignoresize
)
5199 /* Warn them that a data or address size prefix doesn't
5200 affect assembly of the next line of code. */
5201 as_warn (_("stand-alone `%s' prefix"), t
->name
);
5205 /* Copy the template we found. */
5208 if (addr_prefix_disp
!= -1)
5209 i
.tm
.operand_types
[addr_prefix_disp
]
5210 = operand_types
[addr_prefix_disp
];
5212 if (found_reverse_match
)
5214 /* If we found a reverse match we must alter the opcode
5215 direction bit. found_reverse_match holds bits to change
5216 (different for int & float insns). */
5218 i
.tm
.base_opcode
^= found_reverse_match
;
5220 i
.tm
.operand_types
[0] = operand_types
[1];
5221 i
.tm
.operand_types
[1] = operand_types
[0];
5230 int mem_op
= operand_type_check (i
.types
[0], anymem
) ? 0 : 1;
5231 if (i
.tm
.operand_types
[mem_op
].bitfield
.esseg
)
5233 if (i
.seg
[0] != NULL
&& i
.seg
[0] != &es
)
5235 as_bad (_("`%s' operand %d must use `%ses' segment"),
5241 /* There's only ever one segment override allowed per instruction.
5242 This instruction possibly has a legal segment override on the
5243 second operand, so copy the segment to where non-string
5244 instructions store it, allowing common code. */
5245 i
.seg
[0] = i
.seg
[1];
5247 else if (i
.tm
.operand_types
[mem_op
+ 1].bitfield
.esseg
)
5249 if (i
.seg
[1] != NULL
&& i
.seg
[1] != &es
)
5251 as_bad (_("`%s' operand %d must use `%ses' segment"),
5262 process_suffix (void)
5264 /* If matched instruction specifies an explicit instruction mnemonic
5266 if (i
.tm
.opcode_modifier
.size16
)
5267 i
.suffix
= WORD_MNEM_SUFFIX
;
5268 else if (i
.tm
.opcode_modifier
.size32
)
5269 i
.suffix
= LONG_MNEM_SUFFIX
;
5270 else if (i
.tm
.opcode_modifier
.size64
)
5271 i
.suffix
= QWORD_MNEM_SUFFIX
;
5272 else if (i
.reg_operands
)
5274 /* If there's no instruction mnemonic suffix we try to invent one
5275 based on register operands. */
5278 /* We take i.suffix from the last register operand specified,
5279 Destination register type is more significant than source
5280 register type. crc32 in SSE4.2 prefers source register
5282 if (i
.tm
.base_opcode
== 0xf20f38f1)
5284 if (i
.types
[0].bitfield
.reg16
)
5285 i
.suffix
= WORD_MNEM_SUFFIX
;
5286 else if (i
.types
[0].bitfield
.reg32
)
5287 i
.suffix
= LONG_MNEM_SUFFIX
;
5288 else if (i
.types
[0].bitfield
.reg64
)
5289 i
.suffix
= QWORD_MNEM_SUFFIX
;
5291 else if (i
.tm
.base_opcode
== 0xf20f38f0)
5293 if (i
.types
[0].bitfield
.reg8
)
5294 i
.suffix
= BYTE_MNEM_SUFFIX
;
5301 if (i
.tm
.base_opcode
== 0xf20f38f1
5302 || i
.tm
.base_opcode
== 0xf20f38f0)
5304 /* We have to know the operand size for crc32. */
5305 as_bad (_("ambiguous memory operand size for `%s`"),
5310 for (op
= i
.operands
; --op
>= 0;)
5311 if (!i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
5313 if (i
.types
[op
].bitfield
.reg8
)
5315 i
.suffix
= BYTE_MNEM_SUFFIX
;
5318 else if (i
.types
[op
].bitfield
.reg16
)
5320 i
.suffix
= WORD_MNEM_SUFFIX
;
5323 else if (i
.types
[op
].bitfield
.reg32
)
5325 i
.suffix
= LONG_MNEM_SUFFIX
;
5328 else if (i
.types
[op
].bitfield
.reg64
)
5330 i
.suffix
= QWORD_MNEM_SUFFIX
;
5336 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
5339 && i
.tm
.opcode_modifier
.ignoresize
5340 && i
.tm
.opcode_modifier
.no_bsuf
)
5342 else if (!check_byte_reg ())
5345 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
5348 && i
.tm
.opcode_modifier
.ignoresize
5349 && i
.tm
.opcode_modifier
.no_lsuf
)
5351 else if (!check_long_reg ())
5354 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
5357 && i
.tm
.opcode_modifier
.ignoresize
5358 && i
.tm
.opcode_modifier
.no_qsuf
)
5360 else if (!check_qword_reg ())
5363 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
5366 && i
.tm
.opcode_modifier
.ignoresize
5367 && i
.tm
.opcode_modifier
.no_wsuf
)
5369 else if (!check_word_reg ())
5372 else if (i
.suffix
== XMMWORD_MNEM_SUFFIX
5373 || i
.suffix
== YMMWORD_MNEM_SUFFIX
5374 || i
.suffix
== ZMMWORD_MNEM_SUFFIX
)
5376 /* Skip if the instruction has x/y/z suffix. match_template
5377 should check if it is a valid suffix. */
5379 else if (intel_syntax
&& i
.tm
.opcode_modifier
.ignoresize
)
5380 /* Do nothing if the instruction is going to ignore the prefix. */
5385 else if (i
.tm
.opcode_modifier
.defaultsize
5387 /* exclude fldenv/frstor/fsave/fstenv */
5388 && i
.tm
.opcode_modifier
.no_ssuf
)
5390 i
.suffix
= stackop_size
;
5392 else if (intel_syntax
5394 && (i
.tm
.operand_types
[0].bitfield
.jumpabsolute
5395 || i
.tm
.opcode_modifier
.jumpbyte
5396 || i
.tm
.opcode_modifier
.jumpintersegment
5397 || (i
.tm
.base_opcode
== 0x0f01 /* [ls][gi]dt */
5398 && i
.tm
.extension_opcode
<= 3)))
5403 if (!i
.tm
.opcode_modifier
.no_qsuf
)
5405 i
.suffix
= QWORD_MNEM_SUFFIX
;
5410 if (!i
.tm
.opcode_modifier
.no_lsuf
)
5411 i
.suffix
= LONG_MNEM_SUFFIX
;
5414 if (!i
.tm
.opcode_modifier
.no_wsuf
)
5415 i
.suffix
= WORD_MNEM_SUFFIX
;
5424 if (i
.tm
.opcode_modifier
.w
)
5426 as_bad (_("no instruction mnemonic suffix given and "
5427 "no register operands; can't size instruction"));
5433 unsigned int suffixes
;
5435 suffixes
= !i
.tm
.opcode_modifier
.no_bsuf
;
5436 if (!i
.tm
.opcode_modifier
.no_wsuf
)
5438 if (!i
.tm
.opcode_modifier
.no_lsuf
)
5440 if (!i
.tm
.opcode_modifier
.no_ldsuf
)
5442 if (!i
.tm
.opcode_modifier
.no_ssuf
)
5444 if (!i
.tm
.opcode_modifier
.no_qsuf
)
5447 /* There are more than suffix matches. */
5448 if (i
.tm
.opcode_modifier
.w
5449 || ((suffixes
& (suffixes
- 1))
5450 && !i
.tm
.opcode_modifier
.defaultsize
5451 && !i
.tm
.opcode_modifier
.ignoresize
))
5453 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
5459 /* Change the opcode based on the operand size given by i.suffix;
5460 We don't need to change things for byte insns. */
5463 && i
.suffix
!= BYTE_MNEM_SUFFIX
5464 && i
.suffix
!= XMMWORD_MNEM_SUFFIX
5465 && i
.suffix
!= YMMWORD_MNEM_SUFFIX
5466 && i
.suffix
!= ZMMWORD_MNEM_SUFFIX
)
5468 /* It's not a byte, select word/dword operation. */
5469 if (i
.tm
.opcode_modifier
.w
)
5471 if (i
.tm
.opcode_modifier
.shortform
)
5472 i
.tm
.base_opcode
|= 8;
5474 i
.tm
.base_opcode
|= 1;
5477 /* Now select between word & dword operations via the operand
5478 size prefix, except for instructions that will ignore this
5480 if (i
.tm
.opcode_modifier
.addrprefixop0
)
5482 /* The address size override prefix changes the size of the
5484 if ((flag_code
== CODE_32BIT
5485 && i
.op
->regs
[0].reg_type
.bitfield
.reg16
)
5486 || (flag_code
!= CODE_32BIT
5487 && i
.op
->regs
[0].reg_type
.bitfield
.reg32
))
5488 if (!add_prefix (ADDR_PREFIX_OPCODE
))
5491 else if (i
.suffix
!= QWORD_MNEM_SUFFIX
5492 && i
.suffix
!= LONG_DOUBLE_MNEM_SUFFIX
5493 && !i
.tm
.opcode_modifier
.ignoresize
5494 && !i
.tm
.opcode_modifier
.floatmf
5495 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
5496 || (flag_code
== CODE_64BIT
5497 && i
.tm
.opcode_modifier
.jumpbyte
)))
5499 unsigned int prefix
= DATA_PREFIX_OPCODE
;
5501 if (i
.tm
.opcode_modifier
.jumpbyte
) /* jcxz, loop */
5502 prefix
= ADDR_PREFIX_OPCODE
;
5504 if (!add_prefix (prefix
))
5508 /* Set mode64 for an operand. */
5509 if (i
.suffix
== QWORD_MNEM_SUFFIX
5510 && flag_code
== CODE_64BIT
5511 && !i
.tm
.opcode_modifier
.norex64
)
5513 /* Special case for xchg %rax,%rax. It is NOP and doesn't
5514 need rex64. cmpxchg8b is also a special case. */
5515 if (! (i
.operands
== 2
5516 && i
.tm
.base_opcode
== 0x90
5517 && i
.tm
.extension_opcode
== None
5518 && operand_type_equal (&i
.types
[0], &acc64
)
5519 && operand_type_equal (&i
.types
[1], &acc64
))
5520 && ! (i
.operands
== 1
5521 && i
.tm
.base_opcode
== 0xfc7
5522 && i
.tm
.extension_opcode
== 1
5523 && !operand_type_check (i
.types
[0], reg
)
5524 && operand_type_check (i
.types
[0], anymem
)))
5528 /* Size floating point instruction. */
5529 if (i
.suffix
== LONG_MNEM_SUFFIX
)
5530 if (i
.tm
.opcode_modifier
.floatmf
)
5531 i
.tm
.base_opcode
^= 4;
5538 check_byte_reg (void)
5542 for (op
= i
.operands
; --op
>= 0;)
5544 /* If this is an eight bit register, it's OK. If it's the 16 or
5545 32 bit version of an eight bit register, we will just use the
5546 low portion, and that's OK too. */
5547 if (i
.types
[op
].bitfield
.reg8
)
5550 /* I/O port address operands are OK too. */
5551 if (i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
5554 /* crc32 doesn't generate this warning. */
5555 if (i
.tm
.base_opcode
== 0xf20f38f0)
5558 if ((i
.types
[op
].bitfield
.reg16
5559 || i
.types
[op
].bitfield
.reg32
5560 || i
.types
[op
].bitfield
.reg64
)
5561 && i
.op
[op
].regs
->reg_num
< 4
5562 /* Prohibit these changes in 64bit mode, since the lowering
5563 would be more complicated. */
5564 && flag_code
!= CODE_64BIT
)
5566 #if REGISTER_WARNINGS
5567 if (!quiet_warnings
)
5568 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5570 (i
.op
[op
].regs
+ (i
.types
[op
].bitfield
.reg16
5571 ? REGNAM_AL
- REGNAM_AX
5572 : REGNAM_AL
- REGNAM_EAX
))->reg_name
,
5574 i
.op
[op
].regs
->reg_name
,
5579 /* Any other register is bad. */
5580 if (i
.types
[op
].bitfield
.reg16
5581 || i
.types
[op
].bitfield
.reg32
5582 || i
.types
[op
].bitfield
.reg64
5583 || i
.types
[op
].bitfield
.regmmx
5584 || i
.types
[op
].bitfield
.regxmm
5585 || i
.types
[op
].bitfield
.regymm
5586 || i
.types
[op
].bitfield
.regzmm
5587 || i
.types
[op
].bitfield
.sreg2
5588 || i
.types
[op
].bitfield
.sreg3
5589 || i
.types
[op
].bitfield
.control
5590 || i
.types
[op
].bitfield
.debug
5591 || i
.types
[op
].bitfield
.test
5592 || i
.types
[op
].bitfield
.floatreg
5593 || i
.types
[op
].bitfield
.floatacc
)
5595 as_bad (_("`%s%s' not allowed with `%s%c'"),
5597 i
.op
[op
].regs
->reg_name
,
5607 check_long_reg (void)
5611 for (op
= i
.operands
; --op
>= 0;)
5612 /* Reject eight bit registers, except where the template requires
5613 them. (eg. movzb) */
5614 if (i
.types
[op
].bitfield
.reg8
5615 && (i
.tm
.operand_types
[op
].bitfield
.reg16
5616 || i
.tm
.operand_types
[op
].bitfield
.reg32
5617 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5619 as_bad (_("`%s%s' not allowed with `%s%c'"),
5621 i
.op
[op
].regs
->reg_name
,
5626 /* Warn if the e prefix on a general reg is missing. */
5627 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
5628 && i
.types
[op
].bitfield
.reg16
5629 && (i
.tm
.operand_types
[op
].bitfield
.reg32
5630 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5632 /* Prohibit these changes in the 64bit mode, since the
5633 lowering is more complicated. */
5634 if (flag_code
== CODE_64BIT
)
5636 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5637 register_prefix
, i
.op
[op
].regs
->reg_name
,
5641 #if REGISTER_WARNINGS
5642 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5644 (i
.op
[op
].regs
+ REGNAM_EAX
- REGNAM_AX
)->reg_name
,
5645 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
5648 /* Warn if the r prefix on a general reg is present. */
5649 else if (i
.types
[op
].bitfield
.reg64
5650 && (i
.tm
.operand_types
[op
].bitfield
.reg32
5651 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5654 && i
.tm
.opcode_modifier
.toqword
5655 && !i
.types
[0].bitfield
.regxmm
)
5657 /* Convert to QWORD. We want REX byte. */
5658 i
.suffix
= QWORD_MNEM_SUFFIX
;
5662 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5663 register_prefix
, i
.op
[op
].regs
->reg_name
,
5672 check_qword_reg (void)
5676 for (op
= i
.operands
; --op
>= 0; )
5677 /* Reject eight bit registers, except where the template requires
5678 them. (eg. movzb) */
5679 if (i
.types
[op
].bitfield
.reg8
5680 && (i
.tm
.operand_types
[op
].bitfield
.reg16
5681 || i
.tm
.operand_types
[op
].bitfield
.reg32
5682 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5684 as_bad (_("`%s%s' not allowed with `%s%c'"),
5686 i
.op
[op
].regs
->reg_name
,
5691 /* Warn if the r prefix on a general reg is missing. */
5692 else if ((i
.types
[op
].bitfield
.reg16
5693 || i
.types
[op
].bitfield
.reg32
)
5694 && (i
.tm
.operand_types
[op
].bitfield
.reg64
5695 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5697 /* Prohibit these changes in the 64bit mode, since the
5698 lowering is more complicated. */
5700 && i
.tm
.opcode_modifier
.todword
5701 && !i
.types
[0].bitfield
.regxmm
)
5703 /* Convert to DWORD. We don't want REX byte. */
5704 i
.suffix
= LONG_MNEM_SUFFIX
;
5708 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5709 register_prefix
, i
.op
[op
].regs
->reg_name
,
5718 check_word_reg (void)
5721 for (op
= i
.operands
; --op
>= 0;)
5722 /* Reject eight bit registers, except where the template requires
5723 them. (eg. movzb) */
5724 if (i
.types
[op
].bitfield
.reg8
5725 && (i
.tm
.operand_types
[op
].bitfield
.reg16
5726 || i
.tm
.operand_types
[op
].bitfield
.reg32
5727 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5729 as_bad (_("`%s%s' not allowed with `%s%c'"),
5731 i
.op
[op
].regs
->reg_name
,
5736 /* Warn if the e or r prefix on a general reg is present. */
5737 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
5738 && (i
.types
[op
].bitfield
.reg32
5739 || i
.types
[op
].bitfield
.reg64
)
5740 && (i
.tm
.operand_types
[op
].bitfield
.reg16
5741 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5743 /* Prohibit these changes in the 64bit mode, since the
5744 lowering is more complicated. */
5745 if (flag_code
== CODE_64BIT
)
5747 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5748 register_prefix
, i
.op
[op
].regs
->reg_name
,
5752 #if REGISTER_WARNINGS
5753 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5755 (i
.op
[op
].regs
+ REGNAM_AX
- REGNAM_EAX
)->reg_name
,
5756 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
5763 update_imm (unsigned int j
)
5765 i386_operand_type overlap
= i
.types
[j
];
5766 if ((overlap
.bitfield
.imm8
5767 || overlap
.bitfield
.imm8s
5768 || overlap
.bitfield
.imm16
5769 || overlap
.bitfield
.imm32
5770 || overlap
.bitfield
.imm32s
5771 || overlap
.bitfield
.imm64
)
5772 && !operand_type_equal (&overlap
, &imm8
)
5773 && !operand_type_equal (&overlap
, &imm8s
)
5774 && !operand_type_equal (&overlap
, &imm16
)
5775 && !operand_type_equal (&overlap
, &imm32
)
5776 && !operand_type_equal (&overlap
, &imm32s
)
5777 && !operand_type_equal (&overlap
, &imm64
))
5781 i386_operand_type temp
;
5783 operand_type_set (&temp
, 0);
5784 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
5786 temp
.bitfield
.imm8
= overlap
.bitfield
.imm8
;
5787 temp
.bitfield
.imm8s
= overlap
.bitfield
.imm8s
;
5789 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
5790 temp
.bitfield
.imm16
= overlap
.bitfield
.imm16
;
5791 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
5793 temp
.bitfield
.imm64
= overlap
.bitfield
.imm64
;
5794 temp
.bitfield
.imm32s
= overlap
.bitfield
.imm32s
;
5797 temp
.bitfield
.imm32
= overlap
.bitfield
.imm32
;
5800 else if (operand_type_equal (&overlap
, &imm16_32_32s
)
5801 || operand_type_equal (&overlap
, &imm16_32
)
5802 || operand_type_equal (&overlap
, &imm16_32s
))
5804 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
5809 if (!operand_type_equal (&overlap
, &imm8
)
5810 && !operand_type_equal (&overlap
, &imm8s
)
5811 && !operand_type_equal (&overlap
, &imm16
)
5812 && !operand_type_equal (&overlap
, &imm32
)
5813 && !operand_type_equal (&overlap
, &imm32s
)
5814 && !operand_type_equal (&overlap
, &imm64
))
5816 as_bad (_("no instruction mnemonic suffix given; "
5817 "can't determine immediate size"));
5821 i
.types
[j
] = overlap
;
5831 /* Update the first 2 immediate operands. */
5832 n
= i
.operands
> 2 ? 2 : i
.operands
;
5835 for (j
= 0; j
< n
; j
++)
5836 if (update_imm (j
) == 0)
5839 /* The 3rd operand can't be immediate operand. */
5840 gas_assert (operand_type_check (i
.types
[2], imm
) == 0);
5847 bad_implicit_operand (int xmm
)
5849 const char *ireg
= xmm
? "xmm0" : "ymm0";
5852 as_bad (_("the last operand of `%s' must be `%s%s'"),
5853 i
.tm
.name
, register_prefix
, ireg
);
5855 as_bad (_("the first operand of `%s' must be `%s%s'"),
5856 i
.tm
.name
, register_prefix
, ireg
);
5861 process_operands (void)
5863 /* Default segment register this instruction will use for memory
5864 accesses. 0 means unknown. This is only for optimizing out
5865 unnecessary segment overrides. */
5866 const seg_entry
*default_seg
= 0;
5868 if (i
.tm
.opcode_modifier
.sse2avx
&& i
.tm
.opcode_modifier
.vexvvvv
)
5870 unsigned int dupl
= i
.operands
;
5871 unsigned int dest
= dupl
- 1;
5874 /* The destination must be an xmm register. */
5875 gas_assert (i
.reg_operands
5876 && MAX_OPERANDS
> dupl
5877 && operand_type_equal (&i
.types
[dest
], ®xmm
));
5879 if (i
.tm
.opcode_modifier
.firstxmm0
)
5881 /* The first operand is implicit and must be xmm0. */
5882 gas_assert (operand_type_equal (&i
.types
[0], ®xmm
));
5883 if (register_number (i
.op
[0].regs
) != 0)
5884 return bad_implicit_operand (1);
5886 if (i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
)
5888 /* Keep xmm0 for instructions with VEX prefix and 3
5894 /* We remove the first xmm0 and keep the number of
5895 operands unchanged, which in fact duplicates the
5897 for (j
= 1; j
< i
.operands
; j
++)
5899 i
.op
[j
- 1] = i
.op
[j
];
5900 i
.types
[j
- 1] = i
.types
[j
];
5901 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
5905 else if (i
.tm
.opcode_modifier
.implicit1stxmm0
)
5907 gas_assert ((MAX_OPERANDS
- 1) > dupl
5908 && (i
.tm
.opcode_modifier
.vexsources
5911 /* Add the implicit xmm0 for instructions with VEX prefix
5913 for (j
= i
.operands
; j
> 0; j
--)
5915 i
.op
[j
] = i
.op
[j
- 1];
5916 i
.types
[j
] = i
.types
[j
- 1];
5917 i
.tm
.operand_types
[j
] = i
.tm
.operand_types
[j
- 1];
5920 = (const reg_entry
*) hash_find (reg_hash
, "xmm0");
5921 i
.types
[0] = regxmm
;
5922 i
.tm
.operand_types
[0] = regxmm
;
5925 i
.reg_operands
+= 2;
5930 i
.op
[dupl
] = i
.op
[dest
];
5931 i
.types
[dupl
] = i
.types
[dest
];
5932 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
5941 i
.op
[dupl
] = i
.op
[dest
];
5942 i
.types
[dupl
] = i
.types
[dest
];
5943 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
5946 if (i
.tm
.opcode_modifier
.immext
)
5949 else if (i
.tm
.opcode_modifier
.firstxmm0
)
5953 /* The first operand is implicit and must be xmm0/ymm0/zmm0. */
5954 gas_assert (i
.reg_operands
5955 && (operand_type_equal (&i
.types
[0], ®xmm
)
5956 || operand_type_equal (&i
.types
[0], ®ymm
)
5957 || operand_type_equal (&i
.types
[0], ®zmm
)));
5958 if (register_number (i
.op
[0].regs
) != 0)
5959 return bad_implicit_operand (i
.types
[0].bitfield
.regxmm
);
5961 for (j
= 1; j
< i
.operands
; j
++)
5963 i
.op
[j
- 1] = i
.op
[j
];
5964 i
.types
[j
- 1] = i
.types
[j
];
5966 /* We need to adjust fields in i.tm since they are used by
5967 build_modrm_byte. */
5968 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
5975 else if (i
.tm
.opcode_modifier
.implicitquadgroup
)
5977 /* The second operand must be {x,y,z}mmN, where N is a multiple of 4. */
5978 gas_assert (i
.operands
>= 2
5979 && (operand_type_equal (&i
.types
[1], ®xmm
)
5980 || operand_type_equal (&i
.types
[1], ®ymm
)
5981 || operand_type_equal (&i
.types
[1], ®zmm
)));
5982 unsigned int regnum
= register_number (i
.op
[1].regs
);
5983 unsigned int first_reg_in_group
= regnum
& ~3;
5984 unsigned int last_reg_in_group
= first_reg_in_group
+ 3;
5985 if (regnum
!= first_reg_in_group
) {
5986 as_warn (_("the second source register `%s%s' implicitly denotes"
5987 " `%s%.3s%d' to `%s%.3s%d' source group in `%s'"),
5988 register_prefix
, i
.op
[1].regs
->reg_name
,
5989 register_prefix
, i
.op
[1].regs
->reg_name
, first_reg_in_group
,
5990 register_prefix
, i
.op
[1].regs
->reg_name
, last_reg_in_group
,
5994 else if (i
.tm
.opcode_modifier
.regkludge
)
5996 /* The imul $imm, %reg instruction is converted into
5997 imul $imm, %reg, %reg, and the clr %reg instruction
5998 is converted into xor %reg, %reg. */
6000 unsigned int first_reg_op
;
6002 if (operand_type_check (i
.types
[0], reg
))
6006 /* Pretend we saw the extra register operand. */
6007 gas_assert (i
.reg_operands
== 1
6008 && i
.op
[first_reg_op
+ 1].regs
== 0);
6009 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
6010 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
6015 if (i
.tm
.opcode_modifier
.shortform
)
6017 if (i
.types
[0].bitfield
.sreg2
6018 || i
.types
[0].bitfield
.sreg3
)
6020 if (i
.tm
.base_opcode
== POP_SEG_SHORT
6021 && i
.op
[0].regs
->reg_num
== 1)
6023 as_bad (_("you can't `pop %scs'"), register_prefix
);
6026 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
6027 if ((i
.op
[0].regs
->reg_flags
& RegRex
) != 0)
6032 /* The register or float register operand is in operand
6036 if (i
.types
[0].bitfield
.floatreg
6037 || operand_type_check (i
.types
[0], reg
))
6041 /* Register goes in low 3 bits of opcode. */
6042 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
6043 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
6045 if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
6047 /* Warn about some common errors, but press on regardless.
6048 The first case can be generated by gcc (<= 2.8.1). */
6049 if (i
.operands
== 2)
6051 /* Reversed arguments on faddp, fsubp, etc. */
6052 as_warn (_("translating to `%s %s%s,%s%s'"), i
.tm
.name
,
6053 register_prefix
, i
.op
[!intel_syntax
].regs
->reg_name
,
6054 register_prefix
, i
.op
[intel_syntax
].regs
->reg_name
);
6058 /* Extraneous `l' suffix on fp insn. */
6059 as_warn (_("translating to `%s %s%s'"), i
.tm
.name
,
6060 register_prefix
, i
.op
[0].regs
->reg_name
);
6065 else if (i
.tm
.opcode_modifier
.modrm
)
6067 /* The opcode is completed (modulo i.tm.extension_opcode which
6068 must be put into the modrm byte). Now, we make the modrm and
6069 index base bytes based on all the info we've collected. */
6071 default_seg
= build_modrm_byte ();
6073 else if ((i
.tm
.base_opcode
& ~0x3) == MOV_AX_DISP32
)
6077 else if (i
.tm
.opcode_modifier
.isstring
)
6079 /* For the string instructions that allow a segment override
6080 on one of their operands, the default segment is ds. */
6084 if (i
.tm
.base_opcode
== 0x8d /* lea */
6087 as_warn (_("segment override on `%s' is ineffectual"), i
.tm
.name
);
6089 /* If a segment was explicitly specified, and the specified segment
6090 is not the default, use an opcode prefix to select it. If we
6091 never figured out what the default segment is, then default_seg
6092 will be zero at this point, and the specified segment prefix will
6094 if ((i
.seg
[0]) && (i
.seg
[0] != default_seg
))
6096 if (!add_prefix (i
.seg
[0]->seg_prefix
))
6102 static const seg_entry
*
6103 build_modrm_byte (void)
6105 const seg_entry
*default_seg
= 0;
6106 unsigned int source
, dest
;
6109 /* The first operand of instructions with VEX prefix and 3 sources
6110 must be VEX_Imm4. */
6111 vex_3_sources
= i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
;
6114 unsigned int nds
, reg_slot
;
6117 if (i
.tm
.opcode_modifier
.veximmext
6118 && i
.tm
.opcode_modifier
.immext
)
6120 dest
= i
.operands
- 2;
6121 gas_assert (dest
== 3);
6124 dest
= i
.operands
- 1;
6127 /* There are 2 kinds of instructions:
6128 1. 5 operands: 4 register operands or 3 register operands
6129 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
6130 VexW0 or VexW1. The destination must be either XMM, YMM or
6132 2. 4 operands: 4 register operands or 3 register operands
6133 plus 1 memory operand, VexXDS, and VexImmExt */
6134 gas_assert ((i
.reg_operands
== 4
6135 || (i
.reg_operands
== 3 && i
.mem_operands
== 1))
6136 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
6137 && (i
.tm
.opcode_modifier
.veximmext
6138 || (i
.imm_operands
== 1
6139 && i
.types
[0].bitfield
.vec_imm4
6140 && (i
.tm
.opcode_modifier
.vexw
== VEXW0
6141 || i
.tm
.opcode_modifier
.vexw
== VEXW1
)
6142 && (operand_type_equal (&i
.tm
.operand_types
[dest
], ®xmm
)
6143 || operand_type_equal (&i
.tm
.operand_types
[dest
], ®ymm
)
6144 || operand_type_equal (&i
.tm
.operand_types
[dest
], ®zmm
)))));
6146 if (i
.imm_operands
== 0)
6148 /* When there is no immediate operand, generate an 8bit
6149 immediate operand to encode the first operand. */
6150 exp
= &im_expressions
[i
.imm_operands
++];
6151 i
.op
[i
.operands
].imms
= exp
;
6152 i
.types
[i
.operands
] = imm8
;
6154 /* If VexW1 is set, the first operand is the source and
6155 the second operand is encoded in the immediate operand. */
6156 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
6167 /* FMA swaps REG and NDS. */
6168 if (i
.tm
.cpu_flags
.bitfield
.cpufma
)
6176 gas_assert (operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6178 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6180 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6182 exp
->X_op
= O_constant
;
6183 exp
->X_add_number
= register_number (i
.op
[reg_slot
].regs
) << 4;
6184 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
6188 unsigned int imm_slot
;
6190 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
6192 /* If VexW0 is set, the third operand is the source and
6193 the second operand is encoded in the immediate
6200 /* VexW1 is set, the second operand is the source and
6201 the third operand is encoded in the immediate
6207 if (i
.tm
.opcode_modifier
.immext
)
6209 /* When ImmExt is set, the immdiate byte is the last
6211 imm_slot
= i
.operands
- 1;
6219 /* Turn on Imm8 so that output_imm will generate it. */
6220 i
.types
[imm_slot
].bitfield
.imm8
= 1;
6223 gas_assert (operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6225 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6227 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6229 i
.op
[imm_slot
].imms
->X_add_number
6230 |= register_number (i
.op
[reg_slot
].regs
) << 4;
6231 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
6234 gas_assert (operand_type_equal (&i
.tm
.operand_types
[nds
], ®xmm
)
6235 || operand_type_equal (&i
.tm
.operand_types
[nds
],
6237 || operand_type_equal (&i
.tm
.operand_types
[nds
],
6239 i
.vex
.register_specifier
= i
.op
[nds
].regs
;
6244 /* i.reg_operands MUST be the number of real register operands;
6245 implicit registers do not count. If there are 3 register
6246 operands, it must be a instruction with VexNDS. For a
6247 instruction with VexNDD, the destination register is encoded
6248 in VEX prefix. If there are 4 register operands, it must be
6249 a instruction with VEX prefix and 3 sources. */
6250 if (i
.mem_operands
== 0
6251 && ((i
.reg_operands
== 2
6252 && i
.tm
.opcode_modifier
.vexvvvv
<= VEXXDS
)
6253 || (i
.reg_operands
== 3
6254 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
6255 || (i
.reg_operands
== 4 && vex_3_sources
)))
6263 /* When there are 3 operands, one of them may be immediate,
6264 which may be the first or the last operand. Otherwise,
6265 the first operand must be shift count register (cl) or it
6266 is an instruction with VexNDS. */
6267 gas_assert (i
.imm_operands
== 1
6268 || (i
.imm_operands
== 0
6269 && (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
6270 || i
.types
[0].bitfield
.shiftcount
)));
6271 if (operand_type_check (i
.types
[0], imm
)
6272 || i
.types
[0].bitfield
.shiftcount
)
6278 /* When there are 4 operands, the first two must be 8bit
6279 immediate operands. The source operand will be the 3rd
6282 For instructions with VexNDS, if the first operand
6283 an imm8, the source operand is the 2nd one. If the last
6284 operand is imm8, the source operand is the first one. */
6285 gas_assert ((i
.imm_operands
== 2
6286 && i
.types
[0].bitfield
.imm8
6287 && i
.types
[1].bitfield
.imm8
)
6288 || (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
6289 && i
.imm_operands
== 1
6290 && (i
.types
[0].bitfield
.imm8
6291 || i
.types
[i
.operands
- 1].bitfield
.imm8
6293 if (i
.imm_operands
== 2)
6297 if (i
.types
[0].bitfield
.imm8
)
6304 if (i
.tm
.opcode_modifier
.evex
)
6306 /* For EVEX instructions, when there are 5 operands, the
6307 first one must be immediate operand. If the second one
6308 is immediate operand, the source operand is the 3th
6309 one. If the last one is immediate operand, the source
6310 operand is the 2nd one. */
6311 gas_assert (i
.imm_operands
== 2
6312 && i
.tm
.opcode_modifier
.sae
6313 && operand_type_check (i
.types
[0], imm
));
6314 if (operand_type_check (i
.types
[1], imm
))
6316 else if (operand_type_check (i
.types
[4], imm
))
6330 /* RC/SAE operand could be between DEST and SRC. That happens
6331 when one operand is GPR and the other one is XMM/YMM/ZMM
6333 if (i
.rounding
&& i
.rounding
->operand
== (int) dest
)
6336 if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
6338 /* For instructions with VexNDS, the register-only source
6339 operand must be 32/64bit integer, XMM, YMM or ZMM
6340 register. It is encoded in VEX prefix. We need to
6341 clear RegMem bit before calling operand_type_equal. */
6343 i386_operand_type op
;
6346 /* Check register-only source operand when two source
6347 operands are swapped. */
6348 if (!i
.tm
.operand_types
[source
].bitfield
.baseindex
6349 && i
.tm
.operand_types
[dest
].bitfield
.baseindex
)
6357 op
= i
.tm
.operand_types
[vvvv
];
6358 op
.bitfield
.regmem
= 0;
6359 if ((dest
+ 1) >= i
.operands
6360 || (!op
.bitfield
.reg32
6361 && op
.bitfield
.reg64
6362 && !operand_type_equal (&op
, ®xmm
)
6363 && !operand_type_equal (&op
, ®ymm
)
6364 && !operand_type_equal (&op
, ®zmm
)
6365 && !operand_type_equal (&op
, ®mask
)))
6367 i
.vex
.register_specifier
= i
.op
[vvvv
].regs
;
6373 /* One of the register operands will be encoded in the i.tm.reg
6374 field, the other in the combined i.tm.mode and i.tm.regmem
6375 fields. If no form of this instruction supports a memory
6376 destination operand, then we assume the source operand may
6377 sometimes be a memory operand and so we need to store the
6378 destination in the i.rm.reg field. */
6379 if (!i
.tm
.operand_types
[dest
].bitfield
.regmem
6380 && operand_type_check (i
.tm
.operand_types
[dest
], anymem
) == 0)
6382 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
6383 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
6384 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
6386 if ((i
.op
[dest
].regs
->reg_flags
& RegVRex
) != 0)
6388 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
6390 if ((i
.op
[source
].regs
->reg_flags
& RegVRex
) != 0)
6395 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
6396 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
6397 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
6399 if ((i
.op
[dest
].regs
->reg_flags
& RegVRex
) != 0)
6401 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
6403 if ((i
.op
[source
].regs
->reg_flags
& RegVRex
) != 0)
6406 if (flag_code
!= CODE_64BIT
&& (i
.rex
& (REX_R
| REX_B
)))
6408 if (!i
.types
[0].bitfield
.control
6409 && !i
.types
[1].bitfield
.control
)
6411 i
.rex
&= ~(REX_R
| REX_B
);
6412 add_prefix (LOCK_PREFIX_OPCODE
);
6416 { /* If it's not 2 reg operands... */
6421 unsigned int fake_zero_displacement
= 0;
6424 for (op
= 0; op
< i
.operands
; op
++)
6425 if (operand_type_check (i
.types
[op
], anymem
))
6427 gas_assert (op
< i
.operands
);
6429 if (i
.tm
.opcode_modifier
.vecsib
)
6431 if (i
.index_reg
->reg_num
== RegEiz
6432 || i
.index_reg
->reg_num
== RegRiz
)
6435 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6438 i
.sib
.base
= NO_BASE_REGISTER
;
6439 i
.sib
.scale
= i
.log2_scale_factor
;
6440 /* No Vec_Disp8 if there is no base. */
6441 i
.types
[op
].bitfield
.vec_disp8
= 0;
6442 i
.types
[op
].bitfield
.disp8
= 0;
6443 i
.types
[op
].bitfield
.disp16
= 0;
6444 i
.types
[op
].bitfield
.disp64
= 0;
6445 if (flag_code
!= CODE_64BIT
)
6447 /* Must be 32 bit */
6448 i
.types
[op
].bitfield
.disp32
= 1;
6449 i
.types
[op
].bitfield
.disp32s
= 0;
6453 i
.types
[op
].bitfield
.disp32
= 0;
6454 i
.types
[op
].bitfield
.disp32s
= 1;
6457 i
.sib
.index
= i
.index_reg
->reg_num
;
6458 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
6460 if ((i
.index_reg
->reg_flags
& RegVRex
) != 0)
6466 if (i
.base_reg
== 0)
6469 if (!i
.disp_operands
)
6471 fake_zero_displacement
= 1;
6472 /* Instructions with VSIB byte need 32bit displacement
6473 if there is no base register. */
6474 if (i
.tm
.opcode_modifier
.vecsib
)
6475 i
.types
[op
].bitfield
.disp32
= 1;
6477 if (i
.index_reg
== 0)
6479 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6480 /* Operand is just <disp> */
6481 if (flag_code
== CODE_64BIT
)
6483 /* 64bit mode overwrites the 32bit absolute
6484 addressing by RIP relative addressing and
6485 absolute addressing is encoded by one of the
6486 redundant SIB forms. */
6487 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6488 i
.sib
.base
= NO_BASE_REGISTER
;
6489 i
.sib
.index
= NO_INDEX_REGISTER
;
6490 i
.types
[op
] = ((i
.prefix
[ADDR_PREFIX
] == 0)
6491 ? disp32s
: disp32
);
6493 else if ((flag_code
== CODE_16BIT
)
6494 ^ (i
.prefix
[ADDR_PREFIX
] != 0))
6496 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
6497 i
.types
[op
] = disp16
;
6501 i
.rm
.regmem
= NO_BASE_REGISTER
;
6502 i
.types
[op
] = disp32
;
6505 else if (!i
.tm
.opcode_modifier
.vecsib
)
6507 /* !i.base_reg && i.index_reg */
6508 if (i
.index_reg
->reg_num
== RegEiz
6509 || i
.index_reg
->reg_num
== RegRiz
)
6510 i
.sib
.index
= NO_INDEX_REGISTER
;
6512 i
.sib
.index
= i
.index_reg
->reg_num
;
6513 i
.sib
.base
= NO_BASE_REGISTER
;
6514 i
.sib
.scale
= i
.log2_scale_factor
;
6515 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6516 /* No Vec_Disp8 if there is no base. */
6517 i
.types
[op
].bitfield
.vec_disp8
= 0;
6518 i
.types
[op
].bitfield
.disp8
= 0;
6519 i
.types
[op
].bitfield
.disp16
= 0;
6520 i
.types
[op
].bitfield
.disp64
= 0;
6521 if (flag_code
!= CODE_64BIT
)
6523 /* Must be 32 bit */
6524 i
.types
[op
].bitfield
.disp32
= 1;
6525 i
.types
[op
].bitfield
.disp32s
= 0;
6529 i
.types
[op
].bitfield
.disp32
= 0;
6530 i
.types
[op
].bitfield
.disp32s
= 1;
6532 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
6536 /* RIP addressing for 64bit mode. */
6537 else if (i
.base_reg
->reg_num
== RegRip
||
6538 i
.base_reg
->reg_num
== RegEip
)
6540 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6541 i
.rm
.regmem
= NO_BASE_REGISTER
;
6542 i
.types
[op
].bitfield
.disp8
= 0;
6543 i
.types
[op
].bitfield
.disp16
= 0;
6544 i
.types
[op
].bitfield
.disp32
= 0;
6545 i
.types
[op
].bitfield
.disp32s
= 1;
6546 i
.types
[op
].bitfield
.disp64
= 0;
6547 i
.types
[op
].bitfield
.vec_disp8
= 0;
6548 i
.flags
[op
] |= Operand_PCrel
;
6549 if (! i
.disp_operands
)
6550 fake_zero_displacement
= 1;
6552 else if (i
.base_reg
->reg_type
.bitfield
.reg16
)
6554 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6555 switch (i
.base_reg
->reg_num
)
6558 if (i
.index_reg
== 0)
6560 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
6561 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
6565 if (i
.index_reg
== 0)
6568 if (operand_type_check (i
.types
[op
], disp
) == 0)
6570 /* fake (%bp) into 0(%bp) */
6571 if (i
.tm
.operand_types
[op
].bitfield
.vec_disp8
)
6572 i
.types
[op
].bitfield
.vec_disp8
= 1;
6574 i
.types
[op
].bitfield
.disp8
= 1;
6575 fake_zero_displacement
= 1;
6578 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
6579 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
6581 default: /* (%si) -> 4 or (%di) -> 5 */
6582 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
6584 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
6586 else /* i.base_reg and 32/64 bit mode */
6588 if (flag_code
== CODE_64BIT
6589 && operand_type_check (i
.types
[op
], disp
))
6591 i386_operand_type temp
;
6592 operand_type_set (&temp
, 0);
6593 temp
.bitfield
.disp8
= i
.types
[op
].bitfield
.disp8
;
6594 temp
.bitfield
.vec_disp8
6595 = i
.types
[op
].bitfield
.vec_disp8
;
6597 if (i
.prefix
[ADDR_PREFIX
] == 0)
6598 i
.types
[op
].bitfield
.disp32s
= 1;
6600 i
.types
[op
].bitfield
.disp32
= 1;
6603 if (!i
.tm
.opcode_modifier
.vecsib
)
6604 i
.rm
.regmem
= i
.base_reg
->reg_num
;
6605 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
6607 i
.sib
.base
= i
.base_reg
->reg_num
;
6608 /* x86-64 ignores REX prefix bit here to avoid decoder
6610 if (!(i
.base_reg
->reg_flags
& RegRex
)
6611 && (i
.base_reg
->reg_num
== EBP_REG_NUM
6612 || i
.base_reg
->reg_num
== ESP_REG_NUM
))
6614 if (i
.base_reg
->reg_num
== 5 && i
.disp_operands
== 0)
6616 fake_zero_displacement
= 1;
6617 if (i
.tm
.operand_types
[op
].bitfield
.vec_disp8
)
6618 i
.types
[op
].bitfield
.vec_disp8
= 1;
6620 i
.types
[op
].bitfield
.disp8
= 1;
6622 i
.sib
.scale
= i
.log2_scale_factor
;
6623 if (i
.index_reg
== 0)
6625 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6626 /* <disp>(%esp) becomes two byte modrm with no index
6627 register. We've already stored the code for esp
6628 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
6629 Any base register besides %esp will not use the
6630 extra modrm byte. */
6631 i
.sib
.index
= NO_INDEX_REGISTER
;
6633 else if (!i
.tm
.opcode_modifier
.vecsib
)
6635 if (i
.index_reg
->reg_num
== RegEiz
6636 || i
.index_reg
->reg_num
== RegRiz
)
6637 i
.sib
.index
= NO_INDEX_REGISTER
;
6639 i
.sib
.index
= i
.index_reg
->reg_num
;
6640 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6641 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
6646 && (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
6647 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
))
6651 if (!fake_zero_displacement
6655 fake_zero_displacement
= 1;
6656 if (i
.disp_encoding
== disp_encoding_8bit
)
6657 i
.types
[op
].bitfield
.disp8
= 1;
6659 i
.types
[op
].bitfield
.disp32
= 1;
6661 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
6665 if (fake_zero_displacement
)
6667 /* Fakes a zero displacement assuming that i.types[op]
6668 holds the correct displacement size. */
6671 gas_assert (i
.op
[op
].disps
== 0);
6672 exp
= &disp_expressions
[i
.disp_operands
++];
6673 i
.op
[op
].disps
= exp
;
6674 exp
->X_op
= O_constant
;
6675 exp
->X_add_number
= 0;
6676 exp
->X_add_symbol
= (symbolS
*) 0;
6677 exp
->X_op_symbol
= (symbolS
*) 0;
6685 if (i
.tm
.opcode_modifier
.vexsources
== XOP2SOURCES
)
6687 if (operand_type_check (i
.types
[0], imm
))
6688 i
.vex
.register_specifier
= NULL
;
6691 /* VEX.vvvv encodes one of the sources when the first
6692 operand is not an immediate. */
6693 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
6694 i
.vex
.register_specifier
= i
.op
[0].regs
;
6696 i
.vex
.register_specifier
= i
.op
[1].regs
;
6699 /* Destination is a XMM register encoded in the ModRM.reg
6701 i
.rm
.reg
= i
.op
[2].regs
->reg_num
;
6702 if ((i
.op
[2].regs
->reg_flags
& RegRex
) != 0)
6705 /* ModRM.rm and VEX.B encodes the other source. */
6706 if (!i
.mem_operands
)
6710 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
6711 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
6713 i
.rm
.regmem
= i
.op
[0].regs
->reg_num
;
6715 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
6719 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXLWP
)
6721 i
.vex
.register_specifier
= i
.op
[2].regs
;
6722 if (!i
.mem_operands
)
6725 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
6726 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
6730 /* Fill in i.rm.reg or i.rm.regmem field with register operand
6731 (if any) based on i.tm.extension_opcode. Again, we must be
6732 careful to make sure that segment/control/debug/test/MMX
6733 registers are coded into the i.rm.reg field. */
6734 else if (i
.reg_operands
)
6737 unsigned int vex_reg
= ~0;
6739 for (op
= 0; op
< i
.operands
; op
++)
6740 if (i
.types
[op
].bitfield
.reg8
6741 || i
.types
[op
].bitfield
.reg16
6742 || i
.types
[op
].bitfield
.reg32
6743 || i
.types
[op
].bitfield
.reg64
6744 || i
.types
[op
].bitfield
.regmmx
6745 || i
.types
[op
].bitfield
.regxmm
6746 || i
.types
[op
].bitfield
.regymm
6747 || i
.types
[op
].bitfield
.regbnd
6748 || i
.types
[op
].bitfield
.regzmm
6749 || i
.types
[op
].bitfield
.regmask
6750 || i
.types
[op
].bitfield
.sreg2
6751 || i
.types
[op
].bitfield
.sreg3
6752 || i
.types
[op
].bitfield
.control
6753 || i
.types
[op
].bitfield
.debug
6754 || i
.types
[op
].bitfield
.test
)
6759 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
6761 /* For instructions with VexNDS, the register-only
6762 source operand is encoded in VEX prefix. */
6763 gas_assert (mem
!= (unsigned int) ~0);
6768 gas_assert (op
< i
.operands
);
6772 /* Check register-only source operand when two source
6773 operands are swapped. */
6774 if (!i
.tm
.operand_types
[op
].bitfield
.baseindex
6775 && i
.tm
.operand_types
[op
+ 1].bitfield
.baseindex
)
6779 gas_assert (mem
== (vex_reg
+ 1)
6780 && op
< i
.operands
);
6785 gas_assert (vex_reg
< i
.operands
);
6789 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXNDD
)
6791 /* For instructions with VexNDD, the register destination
6792 is encoded in VEX prefix. */
6793 if (i
.mem_operands
== 0)
6795 /* There is no memory operand. */
6796 gas_assert ((op
+ 2) == i
.operands
);
6801 /* There are only 2 operands. */
6802 gas_assert (op
< 2 && i
.operands
== 2);
6807 gas_assert (op
< i
.operands
);
6809 if (vex_reg
!= (unsigned int) ~0)
6811 i386_operand_type
*type
= &i
.tm
.operand_types
[vex_reg
];
6813 if (type
->bitfield
.reg32
!= 1
6814 && type
->bitfield
.reg64
!= 1
6815 && !operand_type_equal (type
, ®xmm
)
6816 && !operand_type_equal (type
, ®ymm
)
6817 && !operand_type_equal (type
, ®zmm
)
6818 && !operand_type_equal (type
, ®mask
))
6821 i
.vex
.register_specifier
= i
.op
[vex_reg
].regs
;
6824 /* Don't set OP operand twice. */
6827 /* If there is an extension opcode to put here, the
6828 register number must be put into the regmem field. */
6829 if (i
.tm
.extension_opcode
!= None
)
6831 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
6832 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
6834 if ((i
.op
[op
].regs
->reg_flags
& RegVRex
) != 0)
6839 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
6840 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
6842 if ((i
.op
[op
].regs
->reg_flags
& RegVRex
) != 0)
6847 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
6848 must set it to 3 to indicate this is a register operand
6849 in the regmem field. */
6850 if (!i
.mem_operands
)
6854 /* Fill in i.rm.reg field with extension opcode (if any). */
6855 if (i
.tm
.extension_opcode
!= None
)
6856 i
.rm
.reg
= i
.tm
.extension_opcode
;
6862 output_branch (void)
6868 relax_substateT subtype
;
6872 code16
= flag_code
== CODE_16BIT
? CODE16
: 0;
6873 size
= i
.disp_encoding
== disp_encoding_32bit
? BIG
: SMALL
;
6876 if (i
.prefix
[DATA_PREFIX
] != 0)
6882 /* Pentium4 branch hints. */
6883 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
6884 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
6889 if (i
.prefix
[REX_PREFIX
] != 0)
6895 /* BND prefixed jump. */
6896 if (i
.prefix
[BND_PREFIX
] != 0)
6898 FRAG_APPEND_1_CHAR (i
.prefix
[BND_PREFIX
]);
6902 if (i
.prefixes
!= 0 && !intel_syntax
)
6903 as_warn (_("skipping prefixes on this instruction"));
6905 /* It's always a symbol; End frag & setup for relax.
6906 Make sure there is enough room in this frag for the largest
6907 instruction we may generate in md_convert_frag. This is 2
6908 bytes for the opcode and room for the prefix and largest
6910 frag_grow (prefix
+ 2 + 4);
6911 /* Prefix and 1 opcode byte go in fr_fix. */
6912 p
= frag_more (prefix
+ 1);
6913 if (i
.prefix
[DATA_PREFIX
] != 0)
6914 *p
++ = DATA_PREFIX_OPCODE
;
6915 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
6916 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
6917 *p
++ = i
.prefix
[SEG_PREFIX
];
6918 if (i
.prefix
[REX_PREFIX
] != 0)
6919 *p
++ = i
.prefix
[REX_PREFIX
];
6920 *p
= i
.tm
.base_opcode
;
6922 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
6923 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, size
);
6924 else if (cpu_arch_flags
.bitfield
.cpui386
)
6925 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, size
);
6927 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, size
);
6930 sym
= i
.op
[0].disps
->X_add_symbol
;
6931 off
= i
.op
[0].disps
->X_add_number
;
6933 if (i
.op
[0].disps
->X_op
!= O_constant
6934 && i
.op
[0].disps
->X_op
!= O_symbol
)
6936 /* Handle complex expressions. */
6937 sym
= make_expr_symbol (i
.op
[0].disps
);
6941 /* 1 possible extra opcode + 4 byte displacement go in var part.
6942 Pass reloc in fr_var. */
6943 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
6953 if (i
.tm
.opcode_modifier
.jumpbyte
)
6955 /* This is a loop or jecxz type instruction. */
6957 if (i
.prefix
[ADDR_PREFIX
] != 0)
6959 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
6962 /* Pentium4 branch hints. */
6963 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
6964 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
6966 FRAG_APPEND_1_CHAR (i
.prefix
[SEG_PREFIX
]);
6975 if (flag_code
== CODE_16BIT
)
6978 if (i
.prefix
[DATA_PREFIX
] != 0)
6980 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
6990 if (i
.prefix
[REX_PREFIX
] != 0)
6992 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
6996 /* BND prefixed jump. */
6997 if (i
.prefix
[BND_PREFIX
] != 0)
6999 FRAG_APPEND_1_CHAR (i
.prefix
[BND_PREFIX
]);
7003 if (i
.prefixes
!= 0 && !intel_syntax
)
7004 as_warn (_("skipping prefixes on this instruction"));
7006 p
= frag_more (i
.tm
.opcode_length
+ size
);
7007 switch (i
.tm
.opcode_length
)
7010 *p
++ = i
.tm
.base_opcode
>> 8;
7013 *p
++ = i
.tm
.base_opcode
;
7019 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
7020 i
.op
[0].disps
, 1, reloc (size
, 1, 1, i
.reloc
[0]));
7022 /* All jumps handled here are signed, but don't use a signed limit
7023 check for 32 and 16 bit jumps as we want to allow wrap around at
7024 4G and 64k respectively. */
7026 fixP
->fx_signed
= 1;
7030 output_interseg_jump (void)
7038 if (flag_code
== CODE_16BIT
)
7042 if (i
.prefix
[DATA_PREFIX
] != 0)
7048 if (i
.prefix
[REX_PREFIX
] != 0)
7058 if (i
.prefixes
!= 0 && !intel_syntax
)
7059 as_warn (_("skipping prefixes on this instruction"));
7061 /* 1 opcode; 2 segment; offset */
7062 p
= frag_more (prefix
+ 1 + 2 + size
);
7064 if (i
.prefix
[DATA_PREFIX
] != 0)
7065 *p
++ = DATA_PREFIX_OPCODE
;
7067 if (i
.prefix
[REX_PREFIX
] != 0)
7068 *p
++ = i
.prefix
[REX_PREFIX
];
7070 *p
++ = i
.tm
.base_opcode
;
7071 if (i
.op
[1].imms
->X_op
== O_constant
)
7073 offsetT n
= i
.op
[1].imms
->X_add_number
;
7076 && !fits_in_unsigned_word (n
)
7077 && !fits_in_signed_word (n
))
7079 as_bad (_("16-bit jump out of range"));
7082 md_number_to_chars (p
, n
, size
);
7085 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
7086 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
7087 if (i
.op
[0].imms
->X_op
!= O_constant
)
7088 as_bad (_("can't handle non absolute segment in `%s'"),
7090 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
7096 fragS
*insn_start_frag
;
7097 offsetT insn_start_off
;
7099 /* Tie dwarf2 debug info to the address at the start of the insn.
7100 We can't do this after the insn has been output as the current
7101 frag may have been closed off. eg. by frag_var. */
7102 dwarf2_emit_insn (0);
7104 insn_start_frag
= frag_now
;
7105 insn_start_off
= frag_now_fix ();
7108 if (i
.tm
.opcode_modifier
.jump
)
7110 else if (i
.tm
.opcode_modifier
.jumpbyte
7111 || i
.tm
.opcode_modifier
.jumpdword
)
7113 else if (i
.tm
.opcode_modifier
.jumpintersegment
)
7114 output_interseg_jump ();
7117 /* Output normal instructions here. */
7121 unsigned int prefix
;
7124 && i
.tm
.base_opcode
== 0xfae
7126 && i
.imm_operands
== 1
7127 && (i
.op
[0].imms
->X_add_number
== 0xe8
7128 || i
.op
[0].imms
->X_add_number
== 0xf0
7129 || i
.op
[0].imms
->X_add_number
== 0xf8))
7131 /* Encode lfence, mfence, and sfence as
7132 f0 83 04 24 00 lock addl $0x0, (%{re}sp). */
7133 offsetT val
= 0x240483f0ULL
;
7135 md_number_to_chars (p
, val
, 5);
7139 /* Some processors fail on LOCK prefix. This options makes
7140 assembler ignore LOCK prefix and serves as a workaround. */
7141 if (omit_lock_prefix
)
7143 if (i
.tm
.base_opcode
== LOCK_PREFIX_OPCODE
)
7145 i
.prefix
[LOCK_PREFIX
] = 0;
7148 /* Since the VEX/EVEX prefix contains the implicit prefix, we
7149 don't need the explicit prefix. */
7150 if (!i
.tm
.opcode_modifier
.vex
&& !i
.tm
.opcode_modifier
.evex
)
7152 switch (i
.tm
.opcode_length
)
7155 if (i
.tm
.base_opcode
& 0xff000000)
7157 prefix
= (i
.tm
.base_opcode
>> 24) & 0xff;
7162 if ((i
.tm
.base_opcode
& 0xff0000) != 0)
7164 prefix
= (i
.tm
.base_opcode
>> 16) & 0xff;
7165 if (i
.tm
.cpu_flags
.bitfield
.cpupadlock
)
7168 if (prefix
!= REPE_PREFIX_OPCODE
7169 || (i
.prefix
[REP_PREFIX
]
7170 != REPE_PREFIX_OPCODE
))
7171 add_prefix (prefix
);
7174 add_prefix (prefix
);
7183 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
7184 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
7185 R_X86_64_GOTTPOFF relocation so that linker can safely
7186 perform IE->LE optimization. */
7187 if (x86_elf_abi
== X86_64_X32_ABI
7189 && i
.reloc
[0] == BFD_RELOC_X86_64_GOTTPOFF
7190 && i
.prefix
[REX_PREFIX
] == 0)
7191 add_prefix (REX_OPCODE
);
7194 /* The prefix bytes. */
7195 for (j
= ARRAY_SIZE (i
.prefix
), q
= i
.prefix
; j
> 0; j
--, q
++)
7197 FRAG_APPEND_1_CHAR (*q
);
7201 for (j
= 0, q
= i
.prefix
; j
< ARRAY_SIZE (i
.prefix
); j
++, q
++)
7206 /* REX byte is encoded in VEX prefix. */
7210 FRAG_APPEND_1_CHAR (*q
);
7213 /* There should be no other prefixes for instructions
7218 /* For EVEX instructions i.vrex should become 0 after
7219 build_evex_prefix. For VEX instructions upper 16 registers
7220 aren't available, so VREX should be 0. */
7223 /* Now the VEX prefix. */
7224 p
= frag_more (i
.vex
.length
);
7225 for (j
= 0; j
< i
.vex
.length
; j
++)
7226 p
[j
] = i
.vex
.bytes
[j
];
7229 /* Now the opcode; be careful about word order here! */
7230 if (i
.tm
.opcode_length
== 1)
7232 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
7236 switch (i
.tm
.opcode_length
)
7240 *p
++ = (i
.tm
.base_opcode
>> 24) & 0xff;
7241 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
7245 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
7255 /* Put out high byte first: can't use md_number_to_chars! */
7256 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
7257 *p
= i
.tm
.base_opcode
& 0xff;
7260 /* Now the modrm byte and sib byte (if present). */
7261 if (i
.tm
.opcode_modifier
.modrm
)
7263 FRAG_APPEND_1_CHAR ((i
.rm
.regmem
<< 0
7266 /* If i.rm.regmem == ESP (4)
7267 && i.rm.mode != (Register mode)
7269 ==> need second modrm byte. */
7270 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
7272 && !(i
.base_reg
&& i
.base_reg
->reg_type
.bitfield
.reg16
))
7273 FRAG_APPEND_1_CHAR ((i
.sib
.base
<< 0
7275 | i
.sib
.scale
<< 6));
7278 if (i
.disp_operands
)
7279 output_disp (insn_start_frag
, insn_start_off
);
7282 output_imm (insn_start_frag
, insn_start_off
);
7288 pi ("" /*line*/, &i
);
7290 #endif /* DEBUG386 */
7293 /* Return the size of the displacement operand N. */
7296 disp_size (unsigned int n
)
7300 /* Vec_Disp8 has to be 8bit. */
7301 if (i
.types
[n
].bitfield
.vec_disp8
)
7303 else if (i
.types
[n
].bitfield
.disp64
)
7305 else if (i
.types
[n
].bitfield
.disp8
)
7307 else if (i
.types
[n
].bitfield
.disp16
)
7312 /* Return the size of the immediate operand N. */
7315 imm_size (unsigned int n
)
7318 if (i
.types
[n
].bitfield
.imm64
)
7320 else if (i
.types
[n
].bitfield
.imm8
|| i
.types
[n
].bitfield
.imm8s
)
7322 else if (i
.types
[n
].bitfield
.imm16
)
7328 output_disp (fragS
*insn_start_frag
, offsetT insn_start_off
)
7333 for (n
= 0; n
< i
.operands
; n
++)
7335 if (i
.types
[n
].bitfield
.vec_disp8
7336 || operand_type_check (i
.types
[n
], disp
))
7338 if (i
.op
[n
].disps
->X_op
== O_constant
)
7340 int size
= disp_size (n
);
7341 offsetT val
= i
.op
[n
].disps
->X_add_number
;
7343 if (i
.types
[n
].bitfield
.vec_disp8
)
7345 val
= offset_in_range (val
, size
);
7346 p
= frag_more (size
);
7347 md_number_to_chars (p
, val
, size
);
7351 enum bfd_reloc_code_real reloc_type
;
7352 int size
= disp_size (n
);
7353 int sign
= i
.types
[n
].bitfield
.disp32s
;
7354 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
7357 /* We can't have 8 bit displacement here. */
7358 gas_assert (!i
.types
[n
].bitfield
.disp8
);
7360 /* The PC relative address is computed relative
7361 to the instruction boundary, so in case immediate
7362 fields follows, we need to adjust the value. */
7363 if (pcrel
&& i
.imm_operands
)
7368 for (n1
= 0; n1
< i
.operands
; n1
++)
7369 if (operand_type_check (i
.types
[n1
], imm
))
7371 /* Only one immediate is allowed for PC
7372 relative address. */
7373 gas_assert (sz
== 0);
7375 i
.op
[n
].disps
->X_add_number
-= sz
;
7377 /* We should find the immediate. */
7378 gas_assert (sz
!= 0);
7381 p
= frag_more (size
);
7382 reloc_type
= reloc (size
, pcrel
, sign
, i
.reloc
[n
]);
7384 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
7385 && (((reloc_type
== BFD_RELOC_32
7386 || reloc_type
== BFD_RELOC_X86_64_32S
7387 || (reloc_type
== BFD_RELOC_64
7389 && (i
.op
[n
].disps
->X_op
== O_symbol
7390 || (i
.op
[n
].disps
->X_op
== O_add
7391 && ((symbol_get_value_expression
7392 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
7394 || reloc_type
== BFD_RELOC_32_PCREL
))
7398 if (insn_start_frag
== frag_now
)
7399 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
7404 add
= insn_start_frag
->fr_fix
- insn_start_off
;
7405 for (fr
= insn_start_frag
->fr_next
;
7406 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
7408 add
+= p
- frag_now
->fr_literal
;
7413 reloc_type
= BFD_RELOC_386_GOTPC
;
7414 i
.op
[n
].imms
->X_add_number
+= add
;
7416 else if (reloc_type
== BFD_RELOC_64
)
7417 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
7419 /* Don't do the adjustment for x86-64, as there
7420 the pcrel addressing is relative to the _next_
7421 insn, and that is taken care of in other code. */
7422 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
7424 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
7425 size
, i
.op
[n
].disps
, pcrel
,
7427 /* Check for "call/jmp *mem", "mov mem, %reg",
7428 "test %reg, mem" and "binop mem, %reg" where binop
7429 is one of adc, add, and, cmp, or, sbb, sub, xor
7430 instructions. Always generate R_386_GOT32X for
7431 "sym*GOT" operand in 32-bit mode. */
7432 if ((generate_relax_relocations
7435 && i
.rm
.regmem
== 5))
7437 || (i
.rm
.mode
== 0 && i
.rm
.regmem
== 5))
7438 && ((i
.operands
== 1
7439 && i
.tm
.base_opcode
== 0xff
7440 && (i
.rm
.reg
== 2 || i
.rm
.reg
== 4))
7442 && (i
.tm
.base_opcode
== 0x8b
7443 || i
.tm
.base_opcode
== 0x85
7444 || (i
.tm
.base_opcode
& 0xc7) == 0x03))))
7448 fixP
->fx_tcbit
= i
.rex
!= 0;
7450 && (i
.base_reg
->reg_num
== RegRip
7451 || i
.base_reg
->reg_num
== RegEip
))
7452 fixP
->fx_tcbit2
= 1;
7455 fixP
->fx_tcbit2
= 1;
7463 output_imm (fragS
*insn_start_frag
, offsetT insn_start_off
)
7468 for (n
= 0; n
< i
.operands
; n
++)
7470 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
7471 if (i
.rounding
&& (int) n
== i
.rounding
->operand
)
7474 if (operand_type_check (i
.types
[n
], imm
))
7476 if (i
.op
[n
].imms
->X_op
== O_constant
)
7478 int size
= imm_size (n
);
7481 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
7483 p
= frag_more (size
);
7484 md_number_to_chars (p
, val
, size
);
7488 /* Not absolute_section.
7489 Need a 32-bit fixup (don't support 8bit
7490 non-absolute imms). Try to support other
7492 enum bfd_reloc_code_real reloc_type
;
7493 int size
= imm_size (n
);
7496 if (i
.types
[n
].bitfield
.imm32s
7497 && (i
.suffix
== QWORD_MNEM_SUFFIX
7498 || (!i
.suffix
&& i
.tm
.opcode_modifier
.no_lsuf
)))
7503 p
= frag_more (size
);
7504 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
7506 /* This is tough to explain. We end up with this one if we
7507 * have operands that look like
7508 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
7509 * obtain the absolute address of the GOT, and it is strongly
7510 * preferable from a performance point of view to avoid using
7511 * a runtime relocation for this. The actual sequence of
7512 * instructions often look something like:
7517 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
7519 * The call and pop essentially return the absolute address
7520 * of the label .L66 and store it in %ebx. The linker itself
7521 * will ultimately change the first operand of the addl so
7522 * that %ebx points to the GOT, but to keep things simple, the
7523 * .o file must have this operand set so that it generates not
7524 * the absolute address of .L66, but the absolute address of
7525 * itself. This allows the linker itself simply treat a GOTPC
7526 * relocation as asking for a pcrel offset to the GOT to be
7527 * added in, and the addend of the relocation is stored in the
7528 * operand field for the instruction itself.
7530 * Our job here is to fix the operand so that it would add
7531 * the correct offset so that %ebx would point to itself. The
7532 * thing that is tricky is that .-.L66 will point to the
7533 * beginning of the instruction, so we need to further modify
7534 * the operand so that it will point to itself. There are
7535 * other cases where you have something like:
7537 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
7539 * and here no correction would be required. Internally in
7540 * the assembler we treat operands of this form as not being
7541 * pcrel since the '.' is explicitly mentioned, and I wonder
7542 * whether it would simplify matters to do it this way. Who
7543 * knows. In earlier versions of the PIC patches, the
7544 * pcrel_adjust field was used to store the correction, but
7545 * since the expression is not pcrel, I felt it would be
7546 * confusing to do it this way. */
7548 if ((reloc_type
== BFD_RELOC_32
7549 || reloc_type
== BFD_RELOC_X86_64_32S
7550 || reloc_type
== BFD_RELOC_64
)
7552 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
7553 && (i
.op
[n
].imms
->X_op
== O_symbol
7554 || (i
.op
[n
].imms
->X_op
== O_add
7555 && ((symbol_get_value_expression
7556 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
7561 if (insn_start_frag
== frag_now
)
7562 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
7567 add
= insn_start_frag
->fr_fix
- insn_start_off
;
7568 for (fr
= insn_start_frag
->fr_next
;
7569 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
7571 add
+= p
- frag_now
->fr_literal
;
7575 reloc_type
= BFD_RELOC_386_GOTPC
;
7577 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
7579 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
7580 i
.op
[n
].imms
->X_add_number
+= add
;
7582 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
7583 i
.op
[n
].imms
, 0, reloc_type
);
7589 /* x86_cons_fix_new is called via the expression parsing code when a
7590 reloc is needed. We use this hook to get the correct .got reloc. */
7591 static int cons_sign
= -1;
7594 x86_cons_fix_new (fragS
*frag
, unsigned int off
, unsigned int len
,
7595 expressionS
*exp
, bfd_reloc_code_real_type r
)
7597 r
= reloc (len
, 0, cons_sign
, r
);
7600 if (exp
->X_op
== O_secrel
)
7602 exp
->X_op
= O_symbol
;
7603 r
= BFD_RELOC_32_SECREL
;
7607 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
7610 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
7611 purpose of the `.dc.a' internal pseudo-op. */
7614 x86_address_bytes (void)
7616 if ((stdoutput
->arch_info
->mach
& bfd_mach_x64_32
))
7618 return stdoutput
->arch_info
->bits_per_address
/ 8;
7621 #if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
7623 # define lex_got(reloc, adjust, types) NULL
7625 /* Parse operands of the form
7626 <symbol>@GOTOFF+<nnn>
7627 and similar .plt or .got references.
7629 If we find one, set up the correct relocation in RELOC and copy the
7630 input string, minus the `@GOTOFF' into a malloc'd buffer for
7631 parsing by the calling routine. Return this buffer, and if ADJUST
7632 is non-null set it to the length of the string we removed from the
7633 input line. Otherwise return NULL. */
7635 lex_got (enum bfd_reloc_code_real
*rel
,
7637 i386_operand_type
*types
)
7639 /* Some of the relocations depend on the size of what field is to
7640 be relocated. But in our callers i386_immediate and i386_displacement
7641 we don't yet know the operand size (this will be set by insn
7642 matching). Hence we record the word32 relocation here,
7643 and adjust the reloc according to the real size in reloc(). */
7644 static const struct {
7647 const enum bfd_reloc_code_real rel
[2];
7648 const i386_operand_type types64
;
7650 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7651 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32
,
7653 OPERAND_TYPE_IMM32_64
},
7655 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real
,
7656 BFD_RELOC_X86_64_PLTOFF64
},
7657 OPERAND_TYPE_IMM64
},
7658 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32
,
7659 BFD_RELOC_X86_64_PLT32
},
7660 OPERAND_TYPE_IMM32_32S_DISP32
},
7661 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real
,
7662 BFD_RELOC_X86_64_GOTPLT64
},
7663 OPERAND_TYPE_IMM64_DISP64
},
7664 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF
,
7665 BFD_RELOC_X86_64_GOTOFF64
},
7666 OPERAND_TYPE_IMM64_DISP64
},
7667 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real
,
7668 BFD_RELOC_X86_64_GOTPCREL
},
7669 OPERAND_TYPE_IMM32_32S_DISP32
},
7670 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD
,
7671 BFD_RELOC_X86_64_TLSGD
},
7672 OPERAND_TYPE_IMM32_32S_DISP32
},
7673 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM
,
7674 _dummy_first_bfd_reloc_code_real
},
7675 OPERAND_TYPE_NONE
},
7676 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real
,
7677 BFD_RELOC_X86_64_TLSLD
},
7678 OPERAND_TYPE_IMM32_32S_DISP32
},
7679 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32
,
7680 BFD_RELOC_X86_64_GOTTPOFF
},
7681 OPERAND_TYPE_IMM32_32S_DISP32
},
7682 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32
,
7683 BFD_RELOC_X86_64_TPOFF32
},
7684 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
7685 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE
,
7686 _dummy_first_bfd_reloc_code_real
},
7687 OPERAND_TYPE_NONE
},
7688 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32
,
7689 BFD_RELOC_X86_64_DTPOFF32
},
7690 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
7691 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE
,
7692 _dummy_first_bfd_reloc_code_real
},
7693 OPERAND_TYPE_NONE
},
7694 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE
,
7695 _dummy_first_bfd_reloc_code_real
},
7696 OPERAND_TYPE_NONE
},
7697 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32
,
7698 BFD_RELOC_X86_64_GOT32
},
7699 OPERAND_TYPE_IMM32_32S_64_DISP32
},
7700 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC
,
7701 BFD_RELOC_X86_64_GOTPC32_TLSDESC
},
7702 OPERAND_TYPE_IMM32_32S_DISP32
},
7703 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL
,
7704 BFD_RELOC_X86_64_TLSDESC_CALL
},
7705 OPERAND_TYPE_IMM32_32S_DISP32
},
7710 #if defined (OBJ_MAYBE_ELF)
7715 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
7716 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
7719 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
7721 int len
= gotrel
[j
].len
;
7722 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
7724 if (gotrel
[j
].rel
[object_64bit
] != 0)
7727 char *tmpbuf
, *past_reloc
;
7729 *rel
= gotrel
[j
].rel
[object_64bit
];
7733 if (flag_code
!= CODE_64BIT
)
7735 types
->bitfield
.imm32
= 1;
7736 types
->bitfield
.disp32
= 1;
7739 *types
= gotrel
[j
].types64
;
7742 if (j
!= 0 && GOT_symbol
== NULL
)
7743 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
7745 /* The length of the first part of our input line. */
7746 first
= cp
- input_line_pointer
;
7748 /* The second part goes from after the reloc token until
7749 (and including) an end_of_line char or comma. */
7750 past_reloc
= cp
+ 1 + len
;
7752 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
7754 second
= cp
+ 1 - past_reloc
;
7756 /* Allocate and copy string. The trailing NUL shouldn't
7757 be necessary, but be safe. */
7758 tmpbuf
= XNEWVEC (char, first
+ second
+ 2);
7759 memcpy (tmpbuf
, input_line_pointer
, first
);
7760 if (second
!= 0 && *past_reloc
!= ' ')
7761 /* Replace the relocation token with ' ', so that
7762 errors like foo@GOTOFF1 will be detected. */
7763 tmpbuf
[first
++] = ' ';
7765 /* Increment length by 1 if the relocation token is
7770 memcpy (tmpbuf
+ first
, past_reloc
, second
);
7771 tmpbuf
[first
+ second
] = '\0';
7775 as_bad (_("@%s reloc is not supported with %d-bit output format"),
7776 gotrel
[j
].str
, 1 << (5 + object_64bit
));
7781 /* Might be a symbol version string. Don't as_bad here. */
7790 /* Parse operands of the form
7791 <symbol>@SECREL32+<nnn>
7793 If we find one, set up the correct relocation in RELOC and copy the
7794 input string, minus the `@SECREL32' into a malloc'd buffer for
7795 parsing by the calling routine. Return this buffer, and if ADJUST
7796 is non-null set it to the length of the string we removed from the
7797 input line. Otherwise return NULL.
7799 This function is copied from the ELF version above adjusted for PE targets. */
7802 lex_got (enum bfd_reloc_code_real
*rel ATTRIBUTE_UNUSED
,
7803 int *adjust ATTRIBUTE_UNUSED
,
7804 i386_operand_type
*types
)
7810 const enum bfd_reloc_code_real rel
[2];
7811 const i386_operand_type types64
;
7815 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL
,
7816 BFD_RELOC_32_SECREL
},
7817 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
7823 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
7824 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
7827 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
7829 int len
= gotrel
[j
].len
;
7831 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
7833 if (gotrel
[j
].rel
[object_64bit
] != 0)
7836 char *tmpbuf
, *past_reloc
;
7838 *rel
= gotrel
[j
].rel
[object_64bit
];
7844 if (flag_code
!= CODE_64BIT
)
7846 types
->bitfield
.imm32
= 1;
7847 types
->bitfield
.disp32
= 1;
7850 *types
= gotrel
[j
].types64
;
7853 /* The length of the first part of our input line. */
7854 first
= cp
- input_line_pointer
;
7856 /* The second part goes from after the reloc token until
7857 (and including) an end_of_line char or comma. */
7858 past_reloc
= cp
+ 1 + len
;
7860 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
7862 second
= cp
+ 1 - past_reloc
;
7864 /* Allocate and copy string. The trailing NUL shouldn't
7865 be necessary, but be safe. */
7866 tmpbuf
= XNEWVEC (char, first
+ second
+ 2);
7867 memcpy (tmpbuf
, input_line_pointer
, first
);
7868 if (second
!= 0 && *past_reloc
!= ' ')
7869 /* Replace the relocation token with ' ', so that
7870 errors like foo@SECLREL321 will be detected. */
7871 tmpbuf
[first
++] = ' ';
7872 memcpy (tmpbuf
+ first
, past_reloc
, second
);
7873 tmpbuf
[first
+ second
] = '\0';
7877 as_bad (_("@%s reloc is not supported with %d-bit output format"),
7878 gotrel
[j
].str
, 1 << (5 + object_64bit
));
7883 /* Might be a symbol version string. Don't as_bad here. */
7889 bfd_reloc_code_real_type
7890 x86_cons (expressionS
*exp
, int size
)
7892 bfd_reloc_code_real_type got_reloc
= NO_RELOC
;
7894 intel_syntax
= -intel_syntax
;
7897 if (size
== 4 || (object_64bit
&& size
== 8))
7899 /* Handle @GOTOFF and the like in an expression. */
7901 char *gotfree_input_line
;
7904 save
= input_line_pointer
;
7905 gotfree_input_line
= lex_got (&got_reloc
, &adjust
, NULL
);
7906 if (gotfree_input_line
)
7907 input_line_pointer
= gotfree_input_line
;
7911 if (gotfree_input_line
)
7913 /* expression () has merrily parsed up to the end of line,
7914 or a comma - in the wrong buffer. Transfer how far
7915 input_line_pointer has moved to the right buffer. */
7916 input_line_pointer
= (save
7917 + (input_line_pointer
- gotfree_input_line
)
7919 free (gotfree_input_line
);
7920 if (exp
->X_op
== O_constant
7921 || exp
->X_op
== O_absent
7922 || exp
->X_op
== O_illegal
7923 || exp
->X_op
== O_register
7924 || exp
->X_op
== O_big
)
7926 char c
= *input_line_pointer
;
7927 *input_line_pointer
= 0;
7928 as_bad (_("missing or invalid expression `%s'"), save
);
7929 *input_line_pointer
= c
;
7936 intel_syntax
= -intel_syntax
;
7939 i386_intel_simplify (exp
);
7945 signed_cons (int size
)
7947 if (flag_code
== CODE_64BIT
)
7955 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
7962 if (exp
.X_op
== O_symbol
)
7963 exp
.X_op
= O_secrel
;
7965 emit_expr (&exp
, 4);
7967 while (*input_line_pointer
++ == ',');
7969 input_line_pointer
--;
7970 demand_empty_rest_of_line ();
7974 /* Handle Vector operations. */
7977 check_VecOperations (char *op_string
, char *op_end
)
7979 const reg_entry
*mask
;
7984 && (op_end
== NULL
|| op_string
< op_end
))
7987 if (*op_string
== '{')
7991 /* Check broadcasts. */
7992 if (strncmp (op_string
, "1to", 3) == 0)
7997 goto duplicated_vec_op
;
8000 if (*op_string
== '8')
8001 bcst_type
= BROADCAST_1TO8
;
8002 else if (*op_string
== '4')
8003 bcst_type
= BROADCAST_1TO4
;
8004 else if (*op_string
== '2')
8005 bcst_type
= BROADCAST_1TO2
;
8006 else if (*op_string
== '1'
8007 && *(op_string
+1) == '6')
8009 bcst_type
= BROADCAST_1TO16
;
8014 as_bad (_("Unsupported broadcast: `%s'"), saved
);
8019 broadcast_op
.type
= bcst_type
;
8020 broadcast_op
.operand
= this_operand
;
8021 i
.broadcast
= &broadcast_op
;
8023 /* Check masking operation. */
8024 else if ((mask
= parse_register (op_string
, &end_op
)) != NULL
)
8026 /* k0 can't be used for write mask. */
8027 if (mask
->reg_num
== 0)
8029 as_bad (_("`%s' can't be used for write mask"),
8036 mask_op
.mask
= mask
;
8037 mask_op
.zeroing
= 0;
8038 mask_op
.operand
= this_operand
;
8044 goto duplicated_vec_op
;
8046 i
.mask
->mask
= mask
;
8048 /* Only "{z}" is allowed here. No need to check
8049 zeroing mask explicitly. */
8050 if (i
.mask
->operand
!= this_operand
)
8052 as_bad (_("invalid write mask `%s'"), saved
);
8059 /* Check zeroing-flag for masking operation. */
8060 else if (*op_string
== 'z')
8064 mask_op
.mask
= NULL
;
8065 mask_op
.zeroing
= 1;
8066 mask_op
.operand
= this_operand
;
8071 if (i
.mask
->zeroing
)
8074 as_bad (_("duplicated `%s'"), saved
);
8078 i
.mask
->zeroing
= 1;
8080 /* Only "{%k}" is allowed here. No need to check mask
8081 register explicitly. */
8082 if (i
.mask
->operand
!= this_operand
)
8084 as_bad (_("invalid zeroing-masking `%s'"),
8093 goto unknown_vec_op
;
8095 if (*op_string
!= '}')
8097 as_bad (_("missing `}' in `%s'"), saved
);
8104 /* We don't know this one. */
8105 as_bad (_("unknown vector operation: `%s'"), saved
);
8113 i386_immediate (char *imm_start
)
8115 char *save_input_line_pointer
;
8116 char *gotfree_input_line
;
8119 i386_operand_type types
;
8121 operand_type_set (&types
, ~0);
8123 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
8125 as_bad (_("at most %d immediate operands are allowed"),
8126 MAX_IMMEDIATE_OPERANDS
);
8130 exp
= &im_expressions
[i
.imm_operands
++];
8131 i
.op
[this_operand
].imms
= exp
;
8133 if (is_space_char (*imm_start
))
8136 save_input_line_pointer
= input_line_pointer
;
8137 input_line_pointer
= imm_start
;
8139 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
8140 if (gotfree_input_line
)
8141 input_line_pointer
= gotfree_input_line
;
8143 exp_seg
= expression (exp
);
8147 /* Handle vector operations. */
8148 if (*input_line_pointer
== '{')
8150 input_line_pointer
= check_VecOperations (input_line_pointer
,
8152 if (input_line_pointer
== NULL
)
8156 if (*input_line_pointer
)
8157 as_bad (_("junk `%s' after expression"), input_line_pointer
);
8159 input_line_pointer
= save_input_line_pointer
;
8160 if (gotfree_input_line
)
8162 free (gotfree_input_line
);
8164 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
8165 exp
->X_op
= O_illegal
;
8168 return i386_finalize_immediate (exp_seg
, exp
, types
, imm_start
);
8172 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
8173 i386_operand_type types
, const char *imm_start
)
8175 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_illegal
|| exp
->X_op
== O_big
)
8178 as_bad (_("missing or invalid immediate expression `%s'"),
8182 else if (exp
->X_op
== O_constant
)
8184 /* Size it properly later. */
8185 i
.types
[this_operand
].bitfield
.imm64
= 1;
8186 /* If not 64bit, sign extend val. */
8187 if (flag_code
!= CODE_64BIT
8188 && (exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
8190 = (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
8192 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8193 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
8194 && exp_seg
!= absolute_section
8195 && exp_seg
!= text_section
8196 && exp_seg
!= data_section
8197 && exp_seg
!= bss_section
8198 && exp_seg
!= undefined_section
8199 && !bfd_is_com_section (exp_seg
))
8201 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
8205 else if (!intel_syntax
&& exp_seg
== reg_section
)
8208 as_bad (_("illegal immediate register operand %s"), imm_start
);
8213 /* This is an address. The size of the address will be
8214 determined later, depending on destination register,
8215 suffix, or the default for the section. */
8216 i
.types
[this_operand
].bitfield
.imm8
= 1;
8217 i
.types
[this_operand
].bitfield
.imm16
= 1;
8218 i
.types
[this_operand
].bitfield
.imm32
= 1;
8219 i
.types
[this_operand
].bitfield
.imm32s
= 1;
8220 i
.types
[this_operand
].bitfield
.imm64
= 1;
8221 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
8229 i386_scale (char *scale
)
8232 char *save
= input_line_pointer
;
8234 input_line_pointer
= scale
;
8235 val
= get_absolute_expression ();
8240 i
.log2_scale_factor
= 0;
8243 i
.log2_scale_factor
= 1;
8246 i
.log2_scale_factor
= 2;
8249 i
.log2_scale_factor
= 3;
8253 char sep
= *input_line_pointer
;
8255 *input_line_pointer
= '\0';
8256 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
8258 *input_line_pointer
= sep
;
8259 input_line_pointer
= save
;
8263 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
8265 as_warn (_("scale factor of %d without an index register"),
8266 1 << i
.log2_scale_factor
);
8267 i
.log2_scale_factor
= 0;
8269 scale
= input_line_pointer
;
8270 input_line_pointer
= save
;
8275 i386_displacement (char *disp_start
, char *disp_end
)
8279 char *save_input_line_pointer
;
8280 char *gotfree_input_line
;
8282 i386_operand_type bigdisp
, types
= anydisp
;
8285 if (i
.disp_operands
== MAX_MEMORY_OPERANDS
)
8287 as_bad (_("at most %d displacement operands are allowed"),
8288 MAX_MEMORY_OPERANDS
);
8292 operand_type_set (&bigdisp
, 0);
8293 if ((i
.types
[this_operand
].bitfield
.jumpabsolute
)
8294 || (!current_templates
->start
->opcode_modifier
.jump
8295 && !current_templates
->start
->opcode_modifier
.jumpdword
))
8297 bigdisp
.bitfield
.disp32
= 1;
8298 override
= (i
.prefix
[ADDR_PREFIX
] != 0);
8299 if (flag_code
== CODE_64BIT
)
8303 bigdisp
.bitfield
.disp32s
= 1;
8304 bigdisp
.bitfield
.disp64
= 1;
8307 else if ((flag_code
== CODE_16BIT
) ^ override
)
8309 bigdisp
.bitfield
.disp32
= 0;
8310 bigdisp
.bitfield
.disp16
= 1;
8315 /* For PC-relative branches, the width of the displacement
8316 is dependent upon data size, not address size. */
8317 override
= (i
.prefix
[DATA_PREFIX
] != 0);
8318 if (flag_code
== CODE_64BIT
)
8320 if (override
|| i
.suffix
== WORD_MNEM_SUFFIX
)
8321 bigdisp
.bitfield
.disp16
= 1;
8324 bigdisp
.bitfield
.disp32
= 1;
8325 bigdisp
.bitfield
.disp32s
= 1;
8331 override
= (i
.suffix
== (flag_code
!= CODE_16BIT
8333 : LONG_MNEM_SUFFIX
));
8334 bigdisp
.bitfield
.disp32
= 1;
8335 if ((flag_code
== CODE_16BIT
) ^ override
)
8337 bigdisp
.bitfield
.disp32
= 0;
8338 bigdisp
.bitfield
.disp16
= 1;
8342 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
8345 exp
= &disp_expressions
[i
.disp_operands
];
8346 i
.op
[this_operand
].disps
= exp
;
8348 save_input_line_pointer
= input_line_pointer
;
8349 input_line_pointer
= disp_start
;
8350 END_STRING_AND_SAVE (disp_end
);
8352 #ifndef GCC_ASM_O_HACK
8353 #define GCC_ASM_O_HACK 0
8356 END_STRING_AND_SAVE (disp_end
+ 1);
8357 if (i
.types
[this_operand
].bitfield
.baseIndex
8358 && displacement_string_end
[-1] == '+')
8360 /* This hack is to avoid a warning when using the "o"
8361 constraint within gcc asm statements.
8364 #define _set_tssldt_desc(n,addr,limit,type) \
8365 __asm__ __volatile__ ( \
8367 "movw %w1,2+%0\n\t" \
8369 "movb %b1,4+%0\n\t" \
8370 "movb %4,5+%0\n\t" \
8371 "movb $0,6+%0\n\t" \
8372 "movb %h1,7+%0\n\t" \
8374 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
8376 This works great except that the output assembler ends
8377 up looking a bit weird if it turns out that there is
8378 no offset. You end up producing code that looks like:
8391 So here we provide the missing zero. */
8393 *displacement_string_end
= '0';
8396 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
8397 if (gotfree_input_line
)
8398 input_line_pointer
= gotfree_input_line
;
8400 exp_seg
= expression (exp
);
8403 if (*input_line_pointer
)
8404 as_bad (_("junk `%s' after expression"), input_line_pointer
);
8406 RESTORE_END_STRING (disp_end
+ 1);
8408 input_line_pointer
= save_input_line_pointer
;
8409 if (gotfree_input_line
)
8411 free (gotfree_input_line
);
8413 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
8414 exp
->X_op
= O_illegal
;
8417 ret
= i386_finalize_displacement (exp_seg
, exp
, types
, disp_start
);
8419 RESTORE_END_STRING (disp_end
);
8425 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
8426 i386_operand_type types
, const char *disp_start
)
8428 i386_operand_type bigdisp
;
8431 /* We do this to make sure that the section symbol is in
8432 the symbol table. We will ultimately change the relocation
8433 to be relative to the beginning of the section. */
8434 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
8435 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
8436 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
8438 if (exp
->X_op
!= O_symbol
)
8441 if (S_IS_LOCAL (exp
->X_add_symbol
)
8442 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
8443 && S_GET_SEGMENT (exp
->X_add_symbol
) != expr_section
)
8444 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
8445 exp
->X_op
= O_subtract
;
8446 exp
->X_op_symbol
= GOT_symbol
;
8447 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
8448 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
8449 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
8450 i
.reloc
[this_operand
] = BFD_RELOC_64
;
8452 i
.reloc
[this_operand
] = BFD_RELOC_32
;
8455 else if (exp
->X_op
== O_absent
8456 || exp
->X_op
== O_illegal
8457 || exp
->X_op
== O_big
)
8460 as_bad (_("missing or invalid displacement expression `%s'"),
8465 else if (flag_code
== CODE_64BIT
8466 && !i
.prefix
[ADDR_PREFIX
]
8467 && exp
->X_op
== O_constant
)
8469 /* Since displacement is signed extended to 64bit, don't allow
8470 disp32 and turn off disp32s if they are out of range. */
8471 i
.types
[this_operand
].bitfield
.disp32
= 0;
8472 if (!fits_in_signed_long (exp
->X_add_number
))
8474 i
.types
[this_operand
].bitfield
.disp32s
= 0;
8475 if (i
.types
[this_operand
].bitfield
.baseindex
)
8477 as_bad (_("0x%lx out range of signed 32bit displacement"),
8478 (long) exp
->X_add_number
);
8484 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8485 else if (exp
->X_op
!= O_constant
8486 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
8487 && exp_seg
!= absolute_section
8488 && exp_seg
!= text_section
8489 && exp_seg
!= data_section
8490 && exp_seg
!= bss_section
8491 && exp_seg
!= undefined_section
8492 && !bfd_is_com_section (exp_seg
))
8494 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
8499 /* Check if this is a displacement only operand. */
8500 bigdisp
= i
.types
[this_operand
];
8501 bigdisp
.bitfield
.disp8
= 0;
8502 bigdisp
.bitfield
.disp16
= 0;
8503 bigdisp
.bitfield
.disp32
= 0;
8504 bigdisp
.bitfield
.disp32s
= 0;
8505 bigdisp
.bitfield
.disp64
= 0;
8506 if (operand_type_all_zero (&bigdisp
))
8507 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
8513 /* Make sure the memory operand we've been dealt is valid.
8514 Return 1 on success, 0 on a failure. */
8517 i386_index_check (const char *operand_string
)
8519 const char *kind
= "base/index";
8520 enum flag_code addr_mode
;
8522 if (i
.prefix
[ADDR_PREFIX
])
8523 addr_mode
= flag_code
== CODE_32BIT
? CODE_16BIT
: CODE_32BIT
;
8526 addr_mode
= flag_code
;
8528 #if INFER_ADDR_PREFIX
8529 if (i
.mem_operands
== 0)
8531 /* Infer address prefix from the first memory operand. */
8532 const reg_entry
*addr_reg
= i
.base_reg
;
8534 if (addr_reg
== NULL
)
8535 addr_reg
= i
.index_reg
;
8539 if (addr_reg
->reg_num
== RegEip
8540 || addr_reg
->reg_num
== RegEiz
8541 || addr_reg
->reg_type
.bitfield
.reg32
)
8542 addr_mode
= CODE_32BIT
;
8543 else if (flag_code
!= CODE_64BIT
8544 && addr_reg
->reg_type
.bitfield
.reg16
)
8545 addr_mode
= CODE_16BIT
;
8547 if (addr_mode
!= flag_code
)
8549 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
8551 /* Change the size of any displacement too. At most one
8552 of Disp16 or Disp32 is set.
8553 FIXME. There doesn't seem to be any real need for
8554 separate Disp16 and Disp32 flags. The same goes for
8555 Imm16 and Imm32. Removing them would probably clean
8556 up the code quite a lot. */
8557 if (flag_code
!= CODE_64BIT
8558 && (i
.types
[this_operand
].bitfield
.disp16
8559 || i
.types
[this_operand
].bitfield
.disp32
))
8560 i
.types
[this_operand
]
8561 = operand_type_xor (i
.types
[this_operand
], disp16_32
);
8568 if (current_templates
->start
->opcode_modifier
.isstring
8569 && !current_templates
->start
->opcode_modifier
.immext
8570 && (current_templates
->end
[-1].opcode_modifier
.isstring
8573 /* Memory operands of string insns are special in that they only allow
8574 a single register (rDI, rSI, or rBX) as their memory address. */
8575 const reg_entry
*expected_reg
;
8576 static const char *di_si
[][2] =
8582 static const char *bx
[] = { "ebx", "bx", "rbx" };
8584 kind
= "string address";
8586 if (current_templates
->start
->opcode_modifier
.repprefixok
)
8588 i386_operand_type type
= current_templates
->end
[-1].operand_types
[0];
8590 if (!type
.bitfield
.baseindex
8591 || ((!i
.mem_operands
!= !intel_syntax
)
8592 && current_templates
->end
[-1].operand_types
[1]
8593 .bitfield
.baseindex
))
8594 type
= current_templates
->end
[-1].operand_types
[1];
8595 expected_reg
= hash_find (reg_hash
,
8596 di_si
[addr_mode
][type
.bitfield
.esseg
]);
8600 expected_reg
= hash_find (reg_hash
, bx
[addr_mode
]);
8602 if (i
.base_reg
!= expected_reg
8604 || operand_type_check (i
.types
[this_operand
], disp
))
8606 /* The second memory operand must have the same size as
8610 && !((addr_mode
== CODE_64BIT
8611 && i
.base_reg
->reg_type
.bitfield
.reg64
)
8612 || (addr_mode
== CODE_32BIT
8613 ? i
.base_reg
->reg_type
.bitfield
.reg32
8614 : i
.base_reg
->reg_type
.bitfield
.reg16
)))
8617 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
8619 intel_syntax
? '[' : '(',
8621 expected_reg
->reg_name
,
8622 intel_syntax
? ']' : ')');
8629 as_bad (_("`%s' is not a valid %s expression"),
8630 operand_string
, kind
);
8635 if (addr_mode
!= CODE_16BIT
)
8637 /* 32-bit/64-bit checks. */
8639 && (addr_mode
== CODE_64BIT
8640 ? !i
.base_reg
->reg_type
.bitfield
.reg64
8641 : !i
.base_reg
->reg_type
.bitfield
.reg32
)
8643 || (i
.base_reg
->reg_num
8644 != (addr_mode
== CODE_64BIT
? RegRip
: RegEip
))))
8646 && !i
.index_reg
->reg_type
.bitfield
.regxmm
8647 && !i
.index_reg
->reg_type
.bitfield
.regymm
8648 && !i
.index_reg
->reg_type
.bitfield
.regzmm
8649 && ((addr_mode
== CODE_64BIT
8650 ? !(i
.index_reg
->reg_type
.bitfield
.reg64
8651 || i
.index_reg
->reg_num
== RegRiz
)
8652 : !(i
.index_reg
->reg_type
.bitfield
.reg32
8653 || i
.index_reg
->reg_num
== RegEiz
))
8654 || !i
.index_reg
->reg_type
.bitfield
.baseindex
)))
8657 /* bndmk, bndldx, and bndstx have special restrictions. */
8658 if (current_templates
->start
->base_opcode
== 0xf30f1b
8659 || (current_templates
->start
->base_opcode
& ~1) == 0x0f1a)
8661 /* They cannot use RIP-relative addressing. */
8662 if (i
.base_reg
&& i
.base_reg
->reg_num
== RegRip
)
8664 as_bad (_("`%s' cannot be used here"), operand_string
);
8668 /* bndldx and bndstx ignore their scale factor. */
8669 if (current_templates
->start
->base_opcode
!= 0xf30f1b
8670 && i
.log2_scale_factor
)
8671 as_warn (_("register scaling is being ignored here"));
8676 /* 16-bit checks. */
8678 && (!i
.base_reg
->reg_type
.bitfield
.reg16
8679 || !i
.base_reg
->reg_type
.bitfield
.baseindex
))
8681 && (!i
.index_reg
->reg_type
.bitfield
.reg16
8682 || !i
.index_reg
->reg_type
.bitfield
.baseindex
8684 && i
.base_reg
->reg_num
< 6
8685 && i
.index_reg
->reg_num
>= 6
8686 && i
.log2_scale_factor
== 0))))
8693 /* Handle vector immediates. */
8696 RC_SAE_immediate (const char *imm_start
)
8698 unsigned int match_found
, j
;
8699 const char *pstr
= imm_start
;
8707 for (j
= 0; j
< ARRAY_SIZE (RC_NamesTable
); j
++)
8709 if (!strncmp (pstr
, RC_NamesTable
[j
].name
, RC_NamesTable
[j
].len
))
8713 rc_op
.type
= RC_NamesTable
[j
].type
;
8714 rc_op
.operand
= this_operand
;
8715 i
.rounding
= &rc_op
;
8719 as_bad (_("duplicated `%s'"), imm_start
);
8722 pstr
+= RC_NamesTable
[j
].len
;
8732 as_bad (_("Missing '}': '%s'"), imm_start
);
8735 /* RC/SAE immediate string should contain nothing more. */;
8738 as_bad (_("Junk after '}': '%s'"), imm_start
);
8742 exp
= &im_expressions
[i
.imm_operands
++];
8743 i
.op
[this_operand
].imms
= exp
;
8745 exp
->X_op
= O_constant
;
8746 exp
->X_add_number
= 0;
8747 exp
->X_add_symbol
= (symbolS
*) 0;
8748 exp
->X_op_symbol
= (symbolS
*) 0;
8750 i
.types
[this_operand
].bitfield
.imm8
= 1;
8754 /* Only string instructions can have a second memory operand, so
8755 reduce current_templates to just those if it contains any. */
8757 maybe_adjust_templates (void)
8759 const insn_template
*t
;
8761 gas_assert (i
.mem_operands
== 1);
8763 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
8764 if (t
->opcode_modifier
.isstring
)
8767 if (t
< current_templates
->end
)
8769 static templates aux_templates
;
8770 bfd_boolean recheck
;
8772 aux_templates
.start
= t
;
8773 for (; t
< current_templates
->end
; ++t
)
8774 if (!t
->opcode_modifier
.isstring
)
8776 aux_templates
.end
= t
;
8778 /* Determine whether to re-check the first memory operand. */
8779 recheck
= (aux_templates
.start
!= current_templates
->start
8780 || t
!= current_templates
->end
);
8782 current_templates
= &aux_templates
;
8787 if (i
.memop1_string
!= NULL
8788 && i386_index_check (i
.memop1_string
) == 0)
8797 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
8801 i386_att_operand (char *operand_string
)
8805 char *op_string
= operand_string
;
8807 if (is_space_char (*op_string
))
8810 /* We check for an absolute prefix (differentiating,
8811 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
8812 if (*op_string
== ABSOLUTE_PREFIX
)
8815 if (is_space_char (*op_string
))
8817 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
8820 /* Check if operand is a register. */
8821 if ((r
= parse_register (op_string
, &end_op
)) != NULL
)
8823 i386_operand_type temp
;
8825 /* Check for a segment override by searching for ':' after a
8826 segment register. */
8828 if (is_space_char (*op_string
))
8830 if (*op_string
== ':'
8831 && (r
->reg_type
.bitfield
.sreg2
8832 || r
->reg_type
.bitfield
.sreg3
))
8837 i
.seg
[i
.mem_operands
] = &es
;
8840 i
.seg
[i
.mem_operands
] = &cs
;
8843 i
.seg
[i
.mem_operands
] = &ss
;
8846 i
.seg
[i
.mem_operands
] = &ds
;
8849 i
.seg
[i
.mem_operands
] = &fs
;
8852 i
.seg
[i
.mem_operands
] = &gs
;
8856 /* Skip the ':' and whitespace. */
8858 if (is_space_char (*op_string
))
8861 if (!is_digit_char (*op_string
)
8862 && !is_identifier_char (*op_string
)
8863 && *op_string
!= '('
8864 && *op_string
!= ABSOLUTE_PREFIX
)
8866 as_bad (_("bad memory operand `%s'"), op_string
);
8869 /* Handle case of %es:*foo. */
8870 if (*op_string
== ABSOLUTE_PREFIX
)
8873 if (is_space_char (*op_string
))
8875 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
8877 goto do_memory_reference
;
8880 /* Handle vector operations. */
8881 if (*op_string
== '{')
8883 op_string
= check_VecOperations (op_string
, NULL
);
8884 if (op_string
== NULL
)
8890 as_bad (_("junk `%s' after register"), op_string
);
8894 temp
.bitfield
.baseindex
= 0;
8895 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
8897 i
.types
[this_operand
].bitfield
.unspecified
= 0;
8898 i
.op
[this_operand
].regs
= r
;
8901 else if (*op_string
== REGISTER_PREFIX
)
8903 as_bad (_("bad register name `%s'"), op_string
);
8906 else if (*op_string
== IMMEDIATE_PREFIX
)
8909 if (i
.types
[this_operand
].bitfield
.jumpabsolute
)
8911 as_bad (_("immediate operand illegal with absolute jump"));
8914 if (!i386_immediate (op_string
))
8917 else if (RC_SAE_immediate (operand_string
))
8919 /* If it is a RC or SAE immediate, do nothing. */
8922 else if (is_digit_char (*op_string
)
8923 || is_identifier_char (*op_string
)
8924 || *op_string
== '"'
8925 || *op_string
== '(')
8927 /* This is a memory reference of some sort. */
8930 /* Start and end of displacement string expression (if found). */
8931 char *displacement_string_start
;
8932 char *displacement_string_end
;
8935 do_memory_reference
:
8936 if (i
.mem_operands
== 1 && !maybe_adjust_templates ())
8938 if ((i
.mem_operands
== 1
8939 && !current_templates
->start
->opcode_modifier
.isstring
)
8940 || i
.mem_operands
== 2)
8942 as_bad (_("too many memory references for `%s'"),
8943 current_templates
->start
->name
);
8947 /* Check for base index form. We detect the base index form by
8948 looking for an ')' at the end of the operand, searching
8949 for the '(' matching it, and finding a REGISTER_PREFIX or ','
8951 base_string
= op_string
+ strlen (op_string
);
8953 /* Handle vector operations. */
8954 vop_start
= strchr (op_string
, '{');
8955 if (vop_start
&& vop_start
< base_string
)
8957 if (check_VecOperations (vop_start
, base_string
) == NULL
)
8959 base_string
= vop_start
;
8963 if (is_space_char (*base_string
))
8966 /* If we only have a displacement, set-up for it to be parsed later. */
8967 displacement_string_start
= op_string
;
8968 displacement_string_end
= base_string
+ 1;
8970 if (*base_string
== ')')
8973 unsigned int parens_balanced
= 1;
8974 /* We've already checked that the number of left & right ()'s are
8975 equal, so this loop will not be infinite. */
8979 if (*base_string
== ')')
8981 if (*base_string
== '(')
8984 while (parens_balanced
);
8986 temp_string
= base_string
;
8988 /* Skip past '(' and whitespace. */
8990 if (is_space_char (*base_string
))
8993 if (*base_string
== ','
8994 || ((i
.base_reg
= parse_register (base_string
, &end_op
))
8997 displacement_string_end
= temp_string
;
8999 i
.types
[this_operand
].bitfield
.baseindex
= 1;
9003 base_string
= end_op
;
9004 if (is_space_char (*base_string
))
9008 /* There may be an index reg or scale factor here. */
9009 if (*base_string
== ',')
9012 if (is_space_char (*base_string
))
9015 if ((i
.index_reg
= parse_register (base_string
, &end_op
))
9018 base_string
= end_op
;
9019 if (is_space_char (*base_string
))
9021 if (*base_string
== ',')
9024 if (is_space_char (*base_string
))
9027 else if (*base_string
!= ')')
9029 as_bad (_("expecting `,' or `)' "
9030 "after index register in `%s'"),
9035 else if (*base_string
== REGISTER_PREFIX
)
9037 end_op
= strchr (base_string
, ',');
9040 as_bad (_("bad register name `%s'"), base_string
);
9044 /* Check for scale factor. */
9045 if (*base_string
!= ')')
9047 char *end_scale
= i386_scale (base_string
);
9052 base_string
= end_scale
;
9053 if (is_space_char (*base_string
))
9055 if (*base_string
!= ')')
9057 as_bad (_("expecting `)' "
9058 "after scale factor in `%s'"),
9063 else if (!i
.index_reg
)
9065 as_bad (_("expecting index register or scale factor "
9066 "after `,'; got '%c'"),
9071 else if (*base_string
!= ')')
9073 as_bad (_("expecting `,' or `)' "
9074 "after base register in `%s'"),
9079 else if (*base_string
== REGISTER_PREFIX
)
9081 end_op
= strchr (base_string
, ',');
9084 as_bad (_("bad register name `%s'"), base_string
);
9089 /* If there's an expression beginning the operand, parse it,
9090 assuming displacement_string_start and
9091 displacement_string_end are meaningful. */
9092 if (displacement_string_start
!= displacement_string_end
)
9094 if (!i386_displacement (displacement_string_start
,
9095 displacement_string_end
))
9099 /* Special case for (%dx) while doing input/output op. */
9101 && operand_type_equal (&i
.base_reg
->reg_type
,
9102 ®16_inoutportreg
)
9104 && i
.log2_scale_factor
== 0
9105 && i
.seg
[i
.mem_operands
] == 0
9106 && !operand_type_check (i
.types
[this_operand
], disp
))
9108 i
.types
[this_operand
] = inoutportreg
;
9112 if (i386_index_check (operand_string
) == 0)
9114 i
.types
[this_operand
].bitfield
.mem
= 1;
9115 if (i
.mem_operands
== 0)
9116 i
.memop1_string
= xstrdup (operand_string
);
9121 /* It's not a memory operand; argh! */
9122 as_bad (_("invalid char %s beginning operand %d `%s'"),
9123 output_invalid (*op_string
),
9128 return 1; /* Normal return. */
9131 /* Calculate the maximum variable size (i.e., excluding fr_fix)
9132 that an rs_machine_dependent frag may reach. */
9135 i386_frag_max_var (fragS
*frag
)
9137 /* The only relaxable frags are for jumps.
9138 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
9139 gas_assert (frag
->fr_type
== rs_machine_dependent
);
9140 return TYPE_FROM_RELAX_STATE (frag
->fr_subtype
) == UNCOND_JUMP
? 4 : 5;
9143 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9145 elf_symbol_resolved_in_segment_p (symbolS
*fr_symbol
, offsetT fr_var
)
9147 /* STT_GNU_IFUNC symbol must go through PLT. */
9148 if ((symbol_get_bfdsym (fr_symbol
)->flags
9149 & BSF_GNU_INDIRECT_FUNCTION
) != 0)
9152 if (!S_IS_EXTERNAL (fr_symbol
))
9153 /* Symbol may be weak or local. */
9154 return !S_IS_WEAK (fr_symbol
);
9156 /* Global symbols with non-default visibility can't be preempted. */
9157 if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol
)) != STV_DEFAULT
)
9160 if (fr_var
!= NO_RELOC
)
9161 switch ((enum bfd_reloc_code_real
) fr_var
)
9163 case BFD_RELOC_386_PLT32
:
9164 case BFD_RELOC_X86_64_PLT32
:
9165 /* Symbol with PLT relocatin may be preempted. */
9171 /* Global symbols with default visibility in a shared library may be
9172 preempted by another definition. */
9177 /* md_estimate_size_before_relax()
9179 Called just before relax() for rs_machine_dependent frags. The x86
9180 assembler uses these frags to handle variable size jump
9183 Any symbol that is now undefined will not become defined.
9184 Return the correct fr_subtype in the frag.
9185 Return the initial "guess for variable size of frag" to caller.
9186 The guess is actually the growth beyond the fixed part. Whatever
9187 we do to grow the fixed or variable part contributes to our
9191 md_estimate_size_before_relax (fragS
*fragP
, segT segment
)
9193 /* We've already got fragP->fr_subtype right; all we have to do is
9194 check for un-relaxable symbols. On an ELF system, we can't relax
9195 an externally visible symbol, because it may be overridden by a
9197 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
9198 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9200 && !elf_symbol_resolved_in_segment_p (fragP
->fr_symbol
,
9203 #if defined (OBJ_COFF) && defined (TE_PE)
9204 || (OUTPUT_FLAVOR
== bfd_target_coff_flavour
9205 && S_IS_WEAK (fragP
->fr_symbol
))
9209 /* Symbol is undefined in this segment, or we need to keep a
9210 reloc so that weak symbols can be overridden. */
9211 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
9212 enum bfd_reloc_code_real reloc_type
;
9213 unsigned char *opcode
;
9216 if (fragP
->fr_var
!= NO_RELOC
)
9217 reloc_type
= (enum bfd_reloc_code_real
) fragP
->fr_var
;
9219 reloc_type
= BFD_RELOC_16_PCREL
;
9221 reloc_type
= BFD_RELOC_32_PCREL
;
9223 old_fr_fix
= fragP
->fr_fix
;
9224 opcode
= (unsigned char *) fragP
->fr_opcode
;
9226 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
9229 /* Make jmp (0xeb) a (d)word displacement jump. */
9231 fragP
->fr_fix
+= size
;
9232 fix_new (fragP
, old_fr_fix
, size
,
9234 fragP
->fr_offset
, 1,
9240 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
9242 /* Negate the condition, and branch past an
9243 unconditional jump. */
9246 /* Insert an unconditional jump. */
9248 /* We added two extra opcode bytes, and have a two byte
9250 fragP
->fr_fix
+= 2 + 2;
9251 fix_new (fragP
, old_fr_fix
+ 2, 2,
9253 fragP
->fr_offset
, 1,
9260 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
9265 fixP
= fix_new (fragP
, old_fr_fix
, 1,
9267 fragP
->fr_offset
, 1,
9269 fixP
->fx_signed
= 1;
9273 /* This changes the byte-displacement jump 0x7N
9274 to the (d)word-displacement jump 0x0f,0x8N. */
9275 opcode
[1] = opcode
[0] + 0x10;
9276 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
9277 /* We've added an opcode byte. */
9278 fragP
->fr_fix
+= 1 + size
;
9279 fix_new (fragP
, old_fr_fix
+ 1, size
,
9281 fragP
->fr_offset
, 1,
9286 BAD_CASE (fragP
->fr_subtype
);
9290 return fragP
->fr_fix
- old_fr_fix
;
9293 /* Guess size depending on current relax state. Initially the relax
9294 state will correspond to a short jump and we return 1, because
9295 the variable part of the frag (the branch offset) is one byte
9296 long. However, we can relax a section more than once and in that
9297 case we must either set fr_subtype back to the unrelaxed state,
9298 or return the value for the appropriate branch. */
9299 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
9302 /* Called after relax() is finished.
9304 In: Address of frag.
9305 fr_type == rs_machine_dependent.
9306 fr_subtype is what the address relaxed to.
9308 Out: Any fixSs and constants are set up.
9309 Caller will turn frag into a ".space 0". */
9312 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec ATTRIBUTE_UNUSED
,
9315 unsigned char *opcode
;
9316 unsigned char *where_to_put_displacement
= NULL
;
9317 offsetT target_address
;
9318 offsetT opcode_address
;
9319 unsigned int extension
= 0;
9320 offsetT displacement_from_opcode_start
;
9322 opcode
= (unsigned char *) fragP
->fr_opcode
;
9324 /* Address we want to reach in file space. */
9325 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
9327 /* Address opcode resides at in file space. */
9328 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
9330 /* Displacement from opcode start to fill into instruction. */
9331 displacement_from_opcode_start
= target_address
- opcode_address
;
9333 if ((fragP
->fr_subtype
& BIG
) == 0)
9335 /* Don't have to change opcode. */
9336 extension
= 1; /* 1 opcode + 1 displacement */
9337 where_to_put_displacement
= &opcode
[1];
9341 if (no_cond_jump_promotion
9342 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
9343 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
9344 _("long jump required"));
9346 switch (fragP
->fr_subtype
)
9348 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
9349 extension
= 4; /* 1 opcode + 4 displacement */
9351 where_to_put_displacement
= &opcode
[1];
9354 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
9355 extension
= 2; /* 1 opcode + 2 displacement */
9357 where_to_put_displacement
= &opcode
[1];
9360 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
9361 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
9362 extension
= 5; /* 2 opcode + 4 displacement */
9363 opcode
[1] = opcode
[0] + 0x10;
9364 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
9365 where_to_put_displacement
= &opcode
[2];
9368 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
9369 extension
= 3; /* 2 opcode + 2 displacement */
9370 opcode
[1] = opcode
[0] + 0x10;
9371 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
9372 where_to_put_displacement
= &opcode
[2];
9375 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
9380 where_to_put_displacement
= &opcode
[3];
9384 BAD_CASE (fragP
->fr_subtype
);
9389 /* If size if less then four we are sure that the operand fits,
9390 but if it's 4, then it could be that the displacement is larger
9392 if (DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
) == 4
9394 && ((addressT
) (displacement_from_opcode_start
- extension
9395 + ((addressT
) 1 << 31))
9396 > (((addressT
) 2 << 31) - 1)))
9398 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
9399 _("jump target out of range"));
9400 /* Make us emit 0. */
9401 displacement_from_opcode_start
= extension
;
9403 /* Now put displacement after opcode. */
9404 md_number_to_chars ((char *) where_to_put_displacement
,
9405 (valueT
) (displacement_from_opcode_start
- extension
),
9406 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
9407 fragP
->fr_fix
+= extension
;
9410 /* Apply a fixup (fixP) to segment data, once it has been determined
9411 by our caller that we have all the info we need to fix it up.
9413 Parameter valP is the pointer to the value of the bits.
9415 On the 386, immediates, displacements, and data pointers are all in
9416 the same (little-endian) format, so we don't need to care about which
9420 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
9422 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
9423 valueT value
= *valP
;
9425 #if !defined (TE_Mach)
9428 switch (fixP
->fx_r_type
)
9434 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
9437 case BFD_RELOC_X86_64_32S
:
9438 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
9441 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
9444 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
9449 if (fixP
->fx_addsy
!= NULL
9450 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
9451 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
9452 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
9453 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
9454 && !use_rela_relocations
)
9456 /* This is a hack. There should be a better way to handle this.
9457 This covers for the fact that bfd_install_relocation will
9458 subtract the current location (for partial_inplace, PC relative
9459 relocations); see more below. */
9463 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
9466 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
9468 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9471 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
9474 || (symbol_section_p (fixP
->fx_addsy
)
9475 && sym_seg
!= absolute_section
))
9476 && !generic_force_reloc (fixP
))
9478 /* Yes, we add the values in twice. This is because
9479 bfd_install_relocation subtracts them out again. I think
9480 bfd_install_relocation is broken, but I don't dare change
9482 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
9486 #if defined (OBJ_COFF) && defined (TE_PE)
9487 /* For some reason, the PE format does not store a
9488 section address offset for a PC relative symbol. */
9489 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
9490 || S_IS_WEAK (fixP
->fx_addsy
))
9491 value
+= md_pcrel_from (fixP
);
9494 #if defined (OBJ_COFF) && defined (TE_PE)
9495 if (fixP
->fx_addsy
!= NULL
9496 && S_IS_WEAK (fixP
->fx_addsy
)
9497 /* PR 16858: Do not modify weak function references. */
9498 && ! fixP
->fx_pcrel
)
9500 #if !defined (TE_PEP)
9501 /* For x86 PE weak function symbols are neither PC-relative
9502 nor do they set S_IS_FUNCTION. So the only reliable way
9503 to detect them is to check the flags of their containing
9505 if (S_GET_SEGMENT (fixP
->fx_addsy
) != NULL
9506 && S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_CODE
)
9510 value
-= S_GET_VALUE (fixP
->fx_addsy
);
9514 /* Fix a few things - the dynamic linker expects certain values here,
9515 and we must not disappoint it. */
9516 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9517 if (IS_ELF
&& fixP
->fx_addsy
)
9518 switch (fixP
->fx_r_type
)
9520 case BFD_RELOC_386_PLT32
:
9521 case BFD_RELOC_X86_64_PLT32
:
9522 /* Make the jump instruction point to the address of the operand. At
9523 runtime we merely add the offset to the actual PLT entry. */
9527 case BFD_RELOC_386_TLS_GD
:
9528 case BFD_RELOC_386_TLS_LDM
:
9529 case BFD_RELOC_386_TLS_IE_32
:
9530 case BFD_RELOC_386_TLS_IE
:
9531 case BFD_RELOC_386_TLS_GOTIE
:
9532 case BFD_RELOC_386_TLS_GOTDESC
:
9533 case BFD_RELOC_X86_64_TLSGD
:
9534 case BFD_RELOC_X86_64_TLSLD
:
9535 case BFD_RELOC_X86_64_GOTTPOFF
:
9536 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
9537 value
= 0; /* Fully resolved at runtime. No addend. */
9539 case BFD_RELOC_386_TLS_LE
:
9540 case BFD_RELOC_386_TLS_LDO_32
:
9541 case BFD_RELOC_386_TLS_LE_32
:
9542 case BFD_RELOC_X86_64_DTPOFF32
:
9543 case BFD_RELOC_X86_64_DTPOFF64
:
9544 case BFD_RELOC_X86_64_TPOFF32
:
9545 case BFD_RELOC_X86_64_TPOFF64
:
9546 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
9549 case BFD_RELOC_386_TLS_DESC_CALL
:
9550 case BFD_RELOC_X86_64_TLSDESC_CALL
:
9551 value
= 0; /* Fully resolved at runtime. No addend. */
9552 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
9556 case BFD_RELOC_VTABLE_INHERIT
:
9557 case BFD_RELOC_VTABLE_ENTRY
:
9564 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
9566 #endif /* !defined (TE_Mach) */
9568 /* Are we finished with this relocation now? */
9569 if (fixP
->fx_addsy
== NULL
)
9571 #if defined (OBJ_COFF) && defined (TE_PE)
9572 else if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
9575 /* Remember value for tc_gen_reloc. */
9576 fixP
->fx_addnumber
= value
;
9577 /* Clear out the frag for now. */
9581 else if (use_rela_relocations
)
9583 fixP
->fx_no_overflow
= 1;
9584 /* Remember value for tc_gen_reloc. */
9585 fixP
->fx_addnumber
= value
;
9589 md_number_to_chars (p
, value
, fixP
->fx_size
);
9593 md_atof (int type
, char *litP
, int *sizeP
)
9595 /* This outputs the LITTLENUMs in REVERSE order;
9596 in accord with the bigendian 386. */
9597 return ieee_md_atof (type
, litP
, sizeP
, FALSE
);
9600 static char output_invalid_buf
[sizeof (unsigned char) * 2 + 6];
9603 output_invalid (int c
)
9606 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
9609 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
9610 "(0x%x)", (unsigned char) c
);
9611 return output_invalid_buf
;
9614 /* REG_STRING starts *before* REGISTER_PREFIX. */
9616 static const reg_entry
*
9617 parse_real_register (char *reg_string
, char **end_op
)
9619 char *s
= reg_string
;
9621 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
9624 /* Skip possible REGISTER_PREFIX and possible whitespace. */
9625 if (*s
== REGISTER_PREFIX
)
9628 if (is_space_char (*s
))
9632 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
9634 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
9635 return (const reg_entry
*) NULL
;
9639 /* For naked regs, make sure that we are not dealing with an identifier.
9640 This prevents confusing an identifier like `eax_var' with register
9642 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
9643 return (const reg_entry
*) NULL
;
9647 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
9649 /* Handle floating point regs, allowing spaces in the (i) part. */
9650 if (r
== i386_regtab
/* %st is first entry of table */)
9652 if (is_space_char (*s
))
9657 if (is_space_char (*s
))
9659 if (*s
>= '0' && *s
<= '7')
9663 if (is_space_char (*s
))
9668 r
= (const reg_entry
*) hash_find (reg_hash
, "st(0)");
9673 /* We have "%st(" then garbage. */
9674 return (const reg_entry
*) NULL
;
9678 if (r
== NULL
|| allow_pseudo_reg
)
9681 if (operand_type_all_zero (&r
->reg_type
))
9682 return (const reg_entry
*) NULL
;
9684 if ((r
->reg_type
.bitfield
.reg32
9685 || r
->reg_type
.bitfield
.sreg3
9686 || r
->reg_type
.bitfield
.control
9687 || r
->reg_type
.bitfield
.debug
9688 || r
->reg_type
.bitfield
.test
)
9689 && !cpu_arch_flags
.bitfield
.cpui386
)
9690 return (const reg_entry
*) NULL
;
9692 if (r
->reg_type
.bitfield
.floatreg
9693 && !cpu_arch_flags
.bitfield
.cpu8087
9694 && !cpu_arch_flags
.bitfield
.cpu287
9695 && !cpu_arch_flags
.bitfield
.cpu387
)
9696 return (const reg_entry
*) NULL
;
9698 if (r
->reg_type
.bitfield
.regmmx
&& !cpu_arch_flags
.bitfield
.cpuregmmx
)
9699 return (const reg_entry
*) NULL
;
9701 if (r
->reg_type
.bitfield
.regxmm
&& !cpu_arch_flags
.bitfield
.cpuregxmm
)
9702 return (const reg_entry
*) NULL
;
9704 if (r
->reg_type
.bitfield
.regymm
&& !cpu_arch_flags
.bitfield
.cpuregymm
)
9705 return (const reg_entry
*) NULL
;
9707 if (r
->reg_type
.bitfield
.regzmm
&& !cpu_arch_flags
.bitfield
.cpuregzmm
)
9708 return (const reg_entry
*) NULL
;
9710 if (r
->reg_type
.bitfield
.regmask
9711 && !cpu_arch_flags
.bitfield
.cpuregmask
)
9712 return (const reg_entry
*) NULL
;
9714 /* Don't allow fake index register unless allow_index_reg isn't 0. */
9715 if (!allow_index_reg
9716 && (r
->reg_num
== RegEiz
|| r
->reg_num
== RegRiz
))
9717 return (const reg_entry
*) NULL
;
9719 /* Upper 16 vector register is only available with VREX in 64bit
9721 if ((r
->reg_flags
& RegVRex
))
9723 if (!cpu_arch_flags
.bitfield
.cpuvrex
9724 || flag_code
!= CODE_64BIT
)
9725 return (const reg_entry
*) NULL
;
9730 if (((r
->reg_flags
& (RegRex64
| RegRex
))
9731 || r
->reg_type
.bitfield
.reg64
)
9732 && (!cpu_arch_flags
.bitfield
.cpulm
9733 || !operand_type_equal (&r
->reg_type
, &control
))
9734 && flag_code
!= CODE_64BIT
)
9735 return (const reg_entry
*) NULL
;
9737 if (r
->reg_type
.bitfield
.sreg3
&& r
->reg_num
== RegFlat
&& !intel_syntax
)
9738 return (const reg_entry
*) NULL
;
9743 /* REG_STRING starts *before* REGISTER_PREFIX. */
9745 static const reg_entry
*
9746 parse_register (char *reg_string
, char **end_op
)
9750 if (*reg_string
== REGISTER_PREFIX
|| allow_naked_reg
)
9751 r
= parse_real_register (reg_string
, end_op
);
9756 char *save
= input_line_pointer
;
9760 input_line_pointer
= reg_string
;
9761 c
= get_symbol_name (®_string
);
9762 symbolP
= symbol_find (reg_string
);
9763 if (symbolP
&& S_GET_SEGMENT (symbolP
) == reg_section
)
9765 const expressionS
*e
= symbol_get_value_expression (symbolP
);
9767 know (e
->X_op
== O_register
);
9768 know (e
->X_add_number
>= 0
9769 && (valueT
) e
->X_add_number
< i386_regtab_size
);
9770 r
= i386_regtab
+ e
->X_add_number
;
9771 if ((r
->reg_flags
& RegVRex
))
9773 *end_op
= input_line_pointer
;
9775 *input_line_pointer
= c
;
9776 input_line_pointer
= save
;
9782 i386_parse_name (char *name
, expressionS
*e
, char *nextcharP
)
9785 char *end
= input_line_pointer
;
9788 r
= parse_register (name
, &input_line_pointer
);
9789 if (r
&& end
<= input_line_pointer
)
9791 *nextcharP
= *input_line_pointer
;
9792 *input_line_pointer
= 0;
9793 e
->X_op
= O_register
;
9794 e
->X_add_number
= r
- i386_regtab
;
9797 input_line_pointer
= end
;
9799 return intel_syntax
? i386_intel_parse_name (name
, e
) : 0;
9803 md_operand (expressionS
*e
)
9808 switch (*input_line_pointer
)
9810 case REGISTER_PREFIX
:
9811 r
= parse_real_register (input_line_pointer
, &end
);
9814 e
->X_op
= O_register
;
9815 e
->X_add_number
= r
- i386_regtab
;
9816 input_line_pointer
= end
;
9821 gas_assert (intel_syntax
);
9822 end
= input_line_pointer
++;
9824 if (*input_line_pointer
== ']')
9826 ++input_line_pointer
;
9827 e
->X_op_symbol
= make_expr_symbol (e
);
9828 e
->X_add_symbol
= NULL
;
9829 e
->X_add_number
= 0;
9835 input_line_pointer
= end
;
9842 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9843 const char *md_shortopts
= "kVQ:sqn";
9845 const char *md_shortopts
= "qn";
9848 #define OPTION_32 (OPTION_MD_BASE + 0)
9849 #define OPTION_64 (OPTION_MD_BASE + 1)
9850 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
9851 #define OPTION_MARCH (OPTION_MD_BASE + 3)
9852 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
9853 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
9854 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
9855 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
9856 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
9857 #define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
9858 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
9859 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
9860 #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
9861 #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
9862 #define OPTION_X32 (OPTION_MD_BASE + 14)
9863 #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
9864 #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
9865 #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
9866 #define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
9867 #define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
9868 #define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
9869 #define OPTION_MSHARED (OPTION_MD_BASE + 21)
9870 #define OPTION_MAMD64 (OPTION_MD_BASE + 22)
9871 #define OPTION_MINTEL64 (OPTION_MD_BASE + 23)
9872 #define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24)
9873 #define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 25)
9875 struct option md_longopts
[] =
9877 {"32", no_argument
, NULL
, OPTION_32
},
9878 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
9879 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
9880 {"64", no_argument
, NULL
, OPTION_64
},
9882 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9883 {"x32", no_argument
, NULL
, OPTION_X32
},
9884 {"mshared", no_argument
, NULL
, OPTION_MSHARED
},
9886 {"divide", no_argument
, NULL
, OPTION_DIVIDE
},
9887 {"march", required_argument
, NULL
, OPTION_MARCH
},
9888 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
9889 {"mmnemonic", required_argument
, NULL
, OPTION_MMNEMONIC
},
9890 {"msyntax", required_argument
, NULL
, OPTION_MSYNTAX
},
9891 {"mindex-reg", no_argument
, NULL
, OPTION_MINDEX_REG
},
9892 {"mnaked-reg", no_argument
, NULL
, OPTION_MNAKED_REG
},
9893 {"mold-gcc", no_argument
, NULL
, OPTION_MOLD_GCC
},
9894 {"msse2avx", no_argument
, NULL
, OPTION_MSSE2AVX
},
9895 {"msse-check", required_argument
, NULL
, OPTION_MSSE_CHECK
},
9896 {"moperand-check", required_argument
, NULL
, OPTION_MOPERAND_CHECK
},
9897 {"mavxscalar", required_argument
, NULL
, OPTION_MAVXSCALAR
},
9898 {"madd-bnd-prefix", no_argument
, NULL
, OPTION_MADD_BND_PREFIX
},
9899 {"mevexlig", required_argument
, NULL
, OPTION_MEVEXLIG
},
9900 {"mevexwig", required_argument
, NULL
, OPTION_MEVEXWIG
},
9901 # if defined (TE_PE) || defined (TE_PEP)
9902 {"mbig-obj", no_argument
, NULL
, OPTION_MBIG_OBJ
},
9904 {"momit-lock-prefix", required_argument
, NULL
, OPTION_MOMIT_LOCK_PREFIX
},
9905 {"mfence-as-lock-add", required_argument
, NULL
, OPTION_MFENCE_AS_LOCK_ADD
},
9906 {"mrelax-relocations", required_argument
, NULL
, OPTION_MRELAX_RELOCATIONS
},
9907 {"mevexrcig", required_argument
, NULL
, OPTION_MEVEXRCIG
},
9908 {"mamd64", no_argument
, NULL
, OPTION_MAMD64
},
9909 {"mintel64", no_argument
, NULL
, OPTION_MINTEL64
},
9910 {NULL
, no_argument
, NULL
, 0}
9912 size_t md_longopts_size
= sizeof (md_longopts
);
9915 md_parse_option (int c
, const char *arg
)
9918 char *arch
, *next
, *saved
;
9923 optimize_align_code
= 0;
9930 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9931 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
9932 should be emitted or not. FIXME: Not implemented. */
9936 /* -V: SVR4 argument to print version ID. */
9938 print_version_id ();
9941 /* -k: Ignore for FreeBSD compatibility. */
9946 /* -s: On i386 Solaris, this tells the native assembler to use
9947 .stab instead of .stab.excl. We always use .stab anyhow. */
9950 case OPTION_MSHARED
:
9954 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
9955 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
9958 const char **list
, **l
;
9960 list
= bfd_target_list ();
9961 for (l
= list
; *l
!= NULL
; l
++)
9962 if (CONST_STRNEQ (*l
, "elf64-x86-64")
9963 || strcmp (*l
, "coff-x86-64") == 0
9964 || strcmp (*l
, "pe-x86-64") == 0
9965 || strcmp (*l
, "pei-x86-64") == 0
9966 || strcmp (*l
, "mach-o-x86-64") == 0)
9968 default_arch
= "x86_64";
9972 as_fatal (_("no compiled in support for x86_64"));
9978 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9982 const char **list
, **l
;
9984 list
= bfd_target_list ();
9985 for (l
= list
; *l
!= NULL
; l
++)
9986 if (CONST_STRNEQ (*l
, "elf32-x86-64"))
9988 default_arch
= "x86_64:32";
9992 as_fatal (_("no compiled in support for 32bit x86_64"));
9996 as_fatal (_("32bit x86_64 is only supported for ELF"));
10001 default_arch
= "i386";
10004 case OPTION_DIVIDE
:
10005 #ifdef SVR4_COMMENT_CHARS
10010 n
= XNEWVEC (char, strlen (i386_comment_chars
) + 1);
10012 for (s
= i386_comment_chars
; *s
!= '\0'; s
++)
10016 i386_comment_chars
= n
;
10022 saved
= xstrdup (arg
);
10024 /* Allow -march=+nosse. */
10030 as_fatal (_("invalid -march= option: `%s'"), arg
);
10031 next
= strchr (arch
, '+');
10034 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
10036 if (strcmp (arch
, cpu_arch
[j
].name
) == 0)
10039 if (! cpu_arch
[j
].flags
.bitfield
.cpui386
)
10042 cpu_arch_name
= cpu_arch
[j
].name
;
10043 cpu_sub_arch_name
= NULL
;
10044 cpu_arch_flags
= cpu_arch
[j
].flags
;
10045 cpu_arch_isa
= cpu_arch
[j
].type
;
10046 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
10047 if (!cpu_arch_tune_set
)
10049 cpu_arch_tune
= cpu_arch_isa
;
10050 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
10054 else if (*cpu_arch
[j
].name
== '.'
10055 && strcmp (arch
, cpu_arch
[j
].name
+ 1) == 0)
10057 /* ISA entension. */
10058 i386_cpu_flags flags
;
10060 flags
= cpu_flags_or (cpu_arch_flags
,
10061 cpu_arch
[j
].flags
);
10063 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
10065 if (cpu_sub_arch_name
)
10067 char *name
= cpu_sub_arch_name
;
10068 cpu_sub_arch_name
= concat (name
,
10070 (const char *) NULL
);
10074 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
10075 cpu_arch_flags
= flags
;
10076 cpu_arch_isa_flags
= flags
;
10082 if (j
>= ARRAY_SIZE (cpu_arch
))
10084 /* Disable an ISA entension. */
10085 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
10086 if (strcmp (arch
, cpu_noarch
[j
].name
) == 0)
10088 i386_cpu_flags flags
;
10090 flags
= cpu_flags_and_not (cpu_arch_flags
,
10091 cpu_noarch
[j
].flags
);
10092 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
10094 if (cpu_sub_arch_name
)
10096 char *name
= cpu_sub_arch_name
;
10097 cpu_sub_arch_name
= concat (arch
,
10098 (const char *) NULL
);
10102 cpu_sub_arch_name
= xstrdup (arch
);
10103 cpu_arch_flags
= flags
;
10104 cpu_arch_isa_flags
= flags
;
10109 if (j
>= ARRAY_SIZE (cpu_noarch
))
10110 j
= ARRAY_SIZE (cpu_arch
);
10113 if (j
>= ARRAY_SIZE (cpu_arch
))
10114 as_fatal (_("invalid -march= option: `%s'"), arg
);
10118 while (next
!= NULL
);
10124 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
10125 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
10127 if (strcmp (arg
, cpu_arch
[j
].name
) == 0)
10129 cpu_arch_tune_set
= 1;
10130 cpu_arch_tune
= cpu_arch
[j
].type
;
10131 cpu_arch_tune_flags
= cpu_arch
[j
].flags
;
10135 if (j
>= ARRAY_SIZE (cpu_arch
))
10136 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
10139 case OPTION_MMNEMONIC
:
10140 if (strcasecmp (arg
, "att") == 0)
10141 intel_mnemonic
= 0;
10142 else if (strcasecmp (arg
, "intel") == 0)
10143 intel_mnemonic
= 1;
10145 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg
);
10148 case OPTION_MSYNTAX
:
10149 if (strcasecmp (arg
, "att") == 0)
10151 else if (strcasecmp (arg
, "intel") == 0)
10154 as_fatal (_("invalid -msyntax= option: `%s'"), arg
);
10157 case OPTION_MINDEX_REG
:
10158 allow_index_reg
= 1;
10161 case OPTION_MNAKED_REG
:
10162 allow_naked_reg
= 1;
10165 case OPTION_MOLD_GCC
:
10169 case OPTION_MSSE2AVX
:
10173 case OPTION_MSSE_CHECK
:
10174 if (strcasecmp (arg
, "error") == 0)
10175 sse_check
= check_error
;
10176 else if (strcasecmp (arg
, "warning") == 0)
10177 sse_check
= check_warning
;
10178 else if (strcasecmp (arg
, "none") == 0)
10179 sse_check
= check_none
;
10181 as_fatal (_("invalid -msse-check= option: `%s'"), arg
);
10184 case OPTION_MOPERAND_CHECK
:
10185 if (strcasecmp (arg
, "error") == 0)
10186 operand_check
= check_error
;
10187 else if (strcasecmp (arg
, "warning") == 0)
10188 operand_check
= check_warning
;
10189 else if (strcasecmp (arg
, "none") == 0)
10190 operand_check
= check_none
;
10192 as_fatal (_("invalid -moperand-check= option: `%s'"), arg
);
10195 case OPTION_MAVXSCALAR
:
10196 if (strcasecmp (arg
, "128") == 0)
10197 avxscalar
= vex128
;
10198 else if (strcasecmp (arg
, "256") == 0)
10199 avxscalar
= vex256
;
10201 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg
);
10204 case OPTION_MADD_BND_PREFIX
:
10205 add_bnd_prefix
= 1;
10208 case OPTION_MEVEXLIG
:
10209 if (strcmp (arg
, "128") == 0)
10210 evexlig
= evexl128
;
10211 else if (strcmp (arg
, "256") == 0)
10212 evexlig
= evexl256
;
10213 else if (strcmp (arg
, "512") == 0)
10214 evexlig
= evexl512
;
10216 as_fatal (_("invalid -mevexlig= option: `%s'"), arg
);
10219 case OPTION_MEVEXRCIG
:
10220 if (strcmp (arg
, "rne") == 0)
10222 else if (strcmp (arg
, "rd") == 0)
10224 else if (strcmp (arg
, "ru") == 0)
10226 else if (strcmp (arg
, "rz") == 0)
10229 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg
);
10232 case OPTION_MEVEXWIG
:
10233 if (strcmp (arg
, "0") == 0)
10235 else if (strcmp (arg
, "1") == 0)
10238 as_fatal (_("invalid -mevexwig= option: `%s'"), arg
);
10241 # if defined (TE_PE) || defined (TE_PEP)
10242 case OPTION_MBIG_OBJ
:
10247 case OPTION_MOMIT_LOCK_PREFIX
:
10248 if (strcasecmp (arg
, "yes") == 0)
10249 omit_lock_prefix
= 1;
10250 else if (strcasecmp (arg
, "no") == 0)
10251 omit_lock_prefix
= 0;
10253 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg
);
10256 case OPTION_MFENCE_AS_LOCK_ADD
:
10257 if (strcasecmp (arg
, "yes") == 0)
10259 else if (strcasecmp (arg
, "no") == 0)
10262 as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg
);
10265 case OPTION_MRELAX_RELOCATIONS
:
10266 if (strcasecmp (arg
, "yes") == 0)
10267 generate_relax_relocations
= 1;
10268 else if (strcasecmp (arg
, "no") == 0)
10269 generate_relax_relocations
= 0;
10271 as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg
);
10274 case OPTION_MAMD64
:
10278 case OPTION_MINTEL64
:
10288 #define MESSAGE_TEMPLATE \
10292 output_message (FILE *stream
, char *p
, char *message
, char *start
,
10293 int *left_p
, const char *name
, int len
)
10295 int size
= sizeof (MESSAGE_TEMPLATE
);
10296 int left
= *left_p
;
10298 /* Reserve 2 spaces for ", " or ",\0" */
10301 /* Check if there is any room. */
10309 p
= mempcpy (p
, name
, len
);
10313 /* Output the current message now and start a new one. */
10316 fprintf (stream
, "%s\n", message
);
10318 left
= size
- (start
- message
) - len
- 2;
10320 gas_assert (left
>= 0);
10322 p
= mempcpy (p
, name
, len
);
10330 show_arch (FILE *stream
, int ext
, int check
)
10332 static char message
[] = MESSAGE_TEMPLATE
;
10333 char *start
= message
+ 27;
10335 int size
= sizeof (MESSAGE_TEMPLATE
);
10342 left
= size
- (start
- message
);
10343 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
10345 /* Should it be skipped? */
10346 if (cpu_arch
[j
].skip
)
10349 name
= cpu_arch
[j
].name
;
10350 len
= cpu_arch
[j
].len
;
10353 /* It is an extension. Skip if we aren't asked to show it. */
10364 /* It is an processor. Skip if we show only extension. */
10367 else if (check
&& ! cpu_arch
[j
].flags
.bitfield
.cpui386
)
10369 /* It is an impossible processor - skip. */
10373 p
= output_message (stream
, p
, message
, start
, &left
, name
, len
);
10376 /* Display disabled extensions. */
10378 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
10380 name
= cpu_noarch
[j
].name
;
10381 len
= cpu_noarch
[j
].len
;
10382 p
= output_message (stream
, p
, message
, start
, &left
, name
,
10387 fprintf (stream
, "%s\n", message
);
10391 md_show_usage (FILE *stream
)
10393 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10394 fprintf (stream
, _("\
10396 -V print assembler version number\n\
10399 fprintf (stream
, _("\
10400 -n Do not optimize code alignment\n\
10401 -q quieten some warnings\n"));
10402 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10403 fprintf (stream
, _("\
10406 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10407 || defined (TE_PE) || defined (TE_PEP))
10408 fprintf (stream
, _("\
10409 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
10411 #ifdef SVR4_COMMENT_CHARS
10412 fprintf (stream
, _("\
10413 --divide do not treat `/' as a comment character\n"));
10415 fprintf (stream
, _("\
10416 --divide ignored\n"));
10418 fprintf (stream
, _("\
10419 -march=CPU[,+EXTENSION...]\n\
10420 generate code for CPU and EXTENSION, CPU is one of:\n"));
10421 show_arch (stream
, 0, 1);
10422 fprintf (stream
, _("\
10423 EXTENSION is combination of:\n"));
10424 show_arch (stream
, 1, 0);
10425 fprintf (stream
, _("\
10426 -mtune=CPU optimize for CPU, CPU is one of:\n"));
10427 show_arch (stream
, 0, 0);
10428 fprintf (stream
, _("\
10429 -msse2avx encode SSE instructions with VEX prefix\n"));
10430 fprintf (stream
, _("\
10431 -msse-check=[none|error|warning]\n\
10432 check SSE instructions\n"));
10433 fprintf (stream
, _("\
10434 -moperand-check=[none|error|warning]\n\
10435 check operand combinations for validity\n"));
10436 fprintf (stream
, _("\
10437 -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n\
10439 fprintf (stream
, _("\
10440 -mevexlig=[128|256|512] encode scalar EVEX instructions with specific vector\n\
10442 fprintf (stream
, _("\
10443 -mevexwig=[0|1] encode EVEX instructions with specific EVEX.W value\n\
10444 for EVEX.W bit ignored instructions\n"));
10445 fprintf (stream
, _("\
10446 -mevexrcig=[rne|rd|ru|rz]\n\
10447 encode EVEX instructions with specific EVEX.RC value\n\
10448 for SAE-only ignored instructions\n"));
10449 fprintf (stream
, _("\
10450 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
10451 fprintf (stream
, _("\
10452 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
10453 fprintf (stream
, _("\
10454 -mindex-reg support pseudo index registers\n"));
10455 fprintf (stream
, _("\
10456 -mnaked-reg don't require `%%' prefix for registers\n"));
10457 fprintf (stream
, _("\
10458 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
10459 fprintf (stream
, _("\
10460 -madd-bnd-prefix add BND prefix for all valid branches\n"));
10461 fprintf (stream
, _("\
10462 -mshared disable branch optimization for shared code\n"));
10463 # if defined (TE_PE) || defined (TE_PEP)
10464 fprintf (stream
, _("\
10465 -mbig-obj generate big object files\n"));
10467 fprintf (stream
, _("\
10468 -momit-lock-prefix=[no|yes]\n\
10469 strip all lock prefixes\n"));
10470 fprintf (stream
, _("\
10471 -mfence-as-lock-add=[no|yes]\n\
10472 encode lfence, mfence and sfence as\n\
10473 lock addl $0x0, (%%{re}sp)\n"));
10474 fprintf (stream
, _("\
10475 -mrelax-relocations=[no|yes]\n\
10476 generate relax relocations\n"));
10477 fprintf (stream
, _("\
10478 -mamd64 accept only AMD64 ISA\n"));
10479 fprintf (stream
, _("\
10480 -mintel64 accept only Intel64 ISA\n"));
10483 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
10484 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10485 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
10487 /* Pick the target format to use. */
10490 i386_target_format (void)
10492 if (!strncmp (default_arch
, "x86_64", 6))
10494 update_code_flag (CODE_64BIT
, 1);
10495 if (default_arch
[6] == '\0')
10496 x86_elf_abi
= X86_64_ABI
;
10498 x86_elf_abi
= X86_64_X32_ABI
;
10500 else if (!strcmp (default_arch
, "i386"))
10501 update_code_flag (CODE_32BIT
, 1);
10502 else if (!strcmp (default_arch
, "iamcu"))
10504 update_code_flag (CODE_32BIT
, 1);
10505 if (cpu_arch_isa
== PROCESSOR_UNKNOWN
)
10507 static const i386_cpu_flags iamcu_flags
= CPU_IAMCU_FLAGS
;
10508 cpu_arch_name
= "iamcu";
10509 cpu_sub_arch_name
= NULL
;
10510 cpu_arch_flags
= iamcu_flags
;
10511 cpu_arch_isa
= PROCESSOR_IAMCU
;
10512 cpu_arch_isa_flags
= iamcu_flags
;
10513 if (!cpu_arch_tune_set
)
10515 cpu_arch_tune
= cpu_arch_isa
;
10516 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
10519 else if (cpu_arch_isa
!= PROCESSOR_IAMCU
)
10520 as_fatal (_("Intel MCU doesn't support `%s' architecture"),
10524 as_fatal (_("unknown architecture"));
10526 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
10527 cpu_arch_isa_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
10528 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
10529 cpu_arch_tune_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
10531 switch (OUTPUT_FLAVOR
)
10533 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
10534 case bfd_target_aout_flavour
:
10535 return AOUT_TARGET_FORMAT
;
10537 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
10538 # if defined (TE_PE) || defined (TE_PEP)
10539 case bfd_target_coff_flavour
:
10540 if (flag_code
== CODE_64BIT
)
10541 return use_big_obj
? "pe-bigobj-x86-64" : "pe-x86-64";
10544 # elif defined (TE_GO32)
10545 case bfd_target_coff_flavour
:
10546 return "coff-go32";
10548 case bfd_target_coff_flavour
:
10549 return "coff-i386";
10552 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
10553 case bfd_target_elf_flavour
:
10555 const char *format
;
10557 switch (x86_elf_abi
)
10560 format
= ELF_TARGET_FORMAT
;
10563 use_rela_relocations
= 1;
10565 format
= ELF_TARGET_FORMAT64
;
10567 case X86_64_X32_ABI
:
10568 use_rela_relocations
= 1;
10570 disallow_64bit_reloc
= 1;
10571 format
= ELF_TARGET_FORMAT32
;
10574 if (cpu_arch_isa
== PROCESSOR_L1OM
)
10576 if (x86_elf_abi
!= X86_64_ABI
)
10577 as_fatal (_("Intel L1OM is 64bit only"));
10578 return ELF_TARGET_L1OM_FORMAT
;
10580 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
10582 if (x86_elf_abi
!= X86_64_ABI
)
10583 as_fatal (_("Intel K1OM is 64bit only"));
10584 return ELF_TARGET_K1OM_FORMAT
;
10586 else if (cpu_arch_isa
== PROCESSOR_IAMCU
)
10588 if (x86_elf_abi
!= I386_ABI
)
10589 as_fatal (_("Intel MCU is 32bit only"));
10590 return ELF_TARGET_IAMCU_FORMAT
;
10596 #if defined (OBJ_MACH_O)
10597 case bfd_target_mach_o_flavour
:
10598 if (flag_code
== CODE_64BIT
)
10600 use_rela_relocations
= 1;
10602 return "mach-o-x86-64";
10605 return "mach-o-i386";
10613 #endif /* OBJ_MAYBE_ more than one */
10616 md_undefined_symbol (char *name
)
10618 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
10619 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
10620 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
10621 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
10625 if (symbol_find (name
))
10626 as_bad (_("GOT already in symbol table"));
10627 GOT_symbol
= symbol_new (name
, undefined_section
,
10628 (valueT
) 0, &zero_address_frag
);
10635 /* Round up a section size to the appropriate boundary. */
10638 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
10640 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
10641 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
10643 /* For a.out, force the section size to be aligned. If we don't do
10644 this, BFD will align it for us, but it will not write out the
10645 final bytes of the section. This may be a bug in BFD, but it is
10646 easier to fix it here since that is how the other a.out targets
10650 align
= bfd_get_section_alignment (stdoutput
, segment
);
10651 size
= ((size
+ (1 << align
) - 1) & (-((valueT
) 1 << align
)));
10658 /* On the i386, PC-relative offsets are relative to the start of the
10659 next instruction. That is, the address of the offset, plus its
10660 size, since the offset is always the last part of the insn. */
10663 md_pcrel_from (fixS
*fixP
)
10665 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
10671 s_bss (int ignore ATTRIBUTE_UNUSED
)
10675 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10677 obj_elf_section_change_hook ();
10679 temp
= get_absolute_expression ();
10680 subseg_set (bss_section
, (subsegT
) temp
);
10681 demand_empty_rest_of_line ();
10687 i386_validate_fix (fixS
*fixp
)
10689 if (fixp
->fx_subsy
)
10691 if (fixp
->fx_subsy
== GOT_symbol
)
10693 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
10697 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10698 if (fixp
->fx_tcbit2
)
10699 fixp
->fx_r_type
= (fixp
->fx_tcbit
10700 ? BFD_RELOC_X86_64_REX_GOTPCRELX
10701 : BFD_RELOC_X86_64_GOTPCRELX
);
10704 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
10709 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
10711 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
10713 fixp
->fx_subsy
= 0;
10716 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10717 else if (!object_64bit
)
10719 if (fixp
->fx_r_type
== BFD_RELOC_386_GOT32
10720 && fixp
->fx_tcbit2
)
10721 fixp
->fx_r_type
= BFD_RELOC_386_GOT32X
;
10727 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
10730 bfd_reloc_code_real_type code
;
10732 switch (fixp
->fx_r_type
)
10734 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10735 case BFD_RELOC_SIZE32
:
10736 case BFD_RELOC_SIZE64
:
10737 if (S_IS_DEFINED (fixp
->fx_addsy
)
10738 && !S_IS_EXTERNAL (fixp
->fx_addsy
))
10740 /* Resolve size relocation against local symbol to size of
10741 the symbol plus addend. */
10742 valueT value
= S_GET_SIZE (fixp
->fx_addsy
) + fixp
->fx_offset
;
10743 if (fixp
->fx_r_type
== BFD_RELOC_SIZE32
10744 && !fits_in_unsigned_long (value
))
10745 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10746 _("symbol size computation overflow"));
10747 fixp
->fx_addsy
= NULL
;
10748 fixp
->fx_subsy
= NULL
;
10749 md_apply_fix (fixp
, (valueT
*) &value
, NULL
);
10753 /* Fall through. */
10755 case BFD_RELOC_X86_64_PLT32
:
10756 case BFD_RELOC_X86_64_GOT32
:
10757 case BFD_RELOC_X86_64_GOTPCREL
:
10758 case BFD_RELOC_X86_64_GOTPCRELX
:
10759 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
10760 case BFD_RELOC_386_PLT32
:
10761 case BFD_RELOC_386_GOT32
:
10762 case BFD_RELOC_386_GOT32X
:
10763 case BFD_RELOC_386_GOTOFF
:
10764 case BFD_RELOC_386_GOTPC
:
10765 case BFD_RELOC_386_TLS_GD
:
10766 case BFD_RELOC_386_TLS_LDM
:
10767 case BFD_RELOC_386_TLS_LDO_32
:
10768 case BFD_RELOC_386_TLS_IE_32
:
10769 case BFD_RELOC_386_TLS_IE
:
10770 case BFD_RELOC_386_TLS_GOTIE
:
10771 case BFD_RELOC_386_TLS_LE_32
:
10772 case BFD_RELOC_386_TLS_LE
:
10773 case BFD_RELOC_386_TLS_GOTDESC
:
10774 case BFD_RELOC_386_TLS_DESC_CALL
:
10775 case BFD_RELOC_X86_64_TLSGD
:
10776 case BFD_RELOC_X86_64_TLSLD
:
10777 case BFD_RELOC_X86_64_DTPOFF32
:
10778 case BFD_RELOC_X86_64_DTPOFF64
:
10779 case BFD_RELOC_X86_64_GOTTPOFF
:
10780 case BFD_RELOC_X86_64_TPOFF32
:
10781 case BFD_RELOC_X86_64_TPOFF64
:
10782 case BFD_RELOC_X86_64_GOTOFF64
:
10783 case BFD_RELOC_X86_64_GOTPC32
:
10784 case BFD_RELOC_X86_64_GOT64
:
10785 case BFD_RELOC_X86_64_GOTPCREL64
:
10786 case BFD_RELOC_X86_64_GOTPC64
:
10787 case BFD_RELOC_X86_64_GOTPLT64
:
10788 case BFD_RELOC_X86_64_PLTOFF64
:
10789 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
10790 case BFD_RELOC_X86_64_TLSDESC_CALL
:
10791 case BFD_RELOC_RVA
:
10792 case BFD_RELOC_VTABLE_ENTRY
:
10793 case BFD_RELOC_VTABLE_INHERIT
:
10795 case BFD_RELOC_32_SECREL
:
10797 code
= fixp
->fx_r_type
;
10799 case BFD_RELOC_X86_64_32S
:
10800 if (!fixp
->fx_pcrel
)
10802 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
10803 code
= fixp
->fx_r_type
;
10806 /* Fall through. */
10808 if (fixp
->fx_pcrel
)
10810 switch (fixp
->fx_size
)
10813 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10814 _("can not do %d byte pc-relative relocation"),
10816 code
= BFD_RELOC_32_PCREL
;
10818 case 1: code
= BFD_RELOC_8_PCREL
; break;
10819 case 2: code
= BFD_RELOC_16_PCREL
; break;
10820 case 4: code
= BFD_RELOC_32_PCREL
; break;
10822 case 8: code
= BFD_RELOC_64_PCREL
; break;
10828 switch (fixp
->fx_size
)
10831 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10832 _("can not do %d byte relocation"),
10834 code
= BFD_RELOC_32
;
10836 case 1: code
= BFD_RELOC_8
; break;
10837 case 2: code
= BFD_RELOC_16
; break;
10838 case 4: code
= BFD_RELOC_32
; break;
10840 case 8: code
= BFD_RELOC_64
; break;
10847 if ((code
== BFD_RELOC_32
10848 || code
== BFD_RELOC_32_PCREL
10849 || code
== BFD_RELOC_X86_64_32S
)
10851 && fixp
->fx_addsy
== GOT_symbol
)
10854 code
= BFD_RELOC_386_GOTPC
;
10856 code
= BFD_RELOC_X86_64_GOTPC32
;
10858 if ((code
== BFD_RELOC_64
|| code
== BFD_RELOC_64_PCREL
)
10860 && fixp
->fx_addsy
== GOT_symbol
)
10862 code
= BFD_RELOC_X86_64_GOTPC64
;
10865 rel
= XNEW (arelent
);
10866 rel
->sym_ptr_ptr
= XNEW (asymbol
*);
10867 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
10869 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
10871 if (!use_rela_relocations
)
10873 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
10874 vtable entry to be used in the relocation's section offset. */
10875 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
10876 rel
->address
= fixp
->fx_offset
;
10877 #if defined (OBJ_COFF) && defined (TE_PE)
10878 else if (fixp
->fx_addsy
&& S_IS_WEAK (fixp
->fx_addsy
))
10879 rel
->addend
= fixp
->fx_addnumber
- (S_GET_VALUE (fixp
->fx_addsy
) * 2);
10884 /* Use the rela in 64bit mode. */
10887 if (disallow_64bit_reloc
)
10890 case BFD_RELOC_X86_64_DTPOFF64
:
10891 case BFD_RELOC_X86_64_TPOFF64
:
10892 case BFD_RELOC_64_PCREL
:
10893 case BFD_RELOC_X86_64_GOTOFF64
:
10894 case BFD_RELOC_X86_64_GOT64
:
10895 case BFD_RELOC_X86_64_GOTPCREL64
:
10896 case BFD_RELOC_X86_64_GOTPC64
:
10897 case BFD_RELOC_X86_64_GOTPLT64
:
10898 case BFD_RELOC_X86_64_PLTOFF64
:
10899 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10900 _("cannot represent relocation type %s in x32 mode"),
10901 bfd_get_reloc_code_name (code
));
10907 if (!fixp
->fx_pcrel
)
10908 rel
->addend
= fixp
->fx_offset
;
10912 case BFD_RELOC_X86_64_PLT32
:
10913 case BFD_RELOC_X86_64_GOT32
:
10914 case BFD_RELOC_X86_64_GOTPCREL
:
10915 case BFD_RELOC_X86_64_GOTPCRELX
:
10916 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
10917 case BFD_RELOC_X86_64_TLSGD
:
10918 case BFD_RELOC_X86_64_TLSLD
:
10919 case BFD_RELOC_X86_64_GOTTPOFF
:
10920 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
10921 case BFD_RELOC_X86_64_TLSDESC_CALL
:
10922 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
10925 rel
->addend
= (section
->vma
10927 + fixp
->fx_addnumber
10928 + md_pcrel_from (fixp
));
10933 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
10934 if (rel
->howto
== NULL
)
10936 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10937 _("cannot represent relocation type %s"),
10938 bfd_get_reloc_code_name (code
));
10939 /* Set howto to a garbage value so that we can keep going. */
10940 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
10941 gas_assert (rel
->howto
!= NULL
);
10947 #include "tc-i386-intel.c"
10950 tc_x86_parse_to_dw2regnum (expressionS
*exp
)
10952 int saved_naked_reg
;
10953 char saved_register_dot
;
10955 saved_naked_reg
= allow_naked_reg
;
10956 allow_naked_reg
= 1;
10957 saved_register_dot
= register_chars
['.'];
10958 register_chars
['.'] = '.';
10959 allow_pseudo_reg
= 1;
10960 expression_and_evaluate (exp
);
10961 allow_pseudo_reg
= 0;
10962 register_chars
['.'] = saved_register_dot
;
10963 allow_naked_reg
= saved_naked_reg
;
10965 if (exp
->X_op
== O_register
&& exp
->X_add_number
>= 0)
10967 if ((addressT
) exp
->X_add_number
< i386_regtab_size
)
10969 exp
->X_op
= O_constant
;
10970 exp
->X_add_number
= i386_regtab
[exp
->X_add_number
]
10971 .dw2_regnum
[flag_code
>> 1];
10974 exp
->X_op
= O_illegal
;
10979 tc_x86_frame_initial_instructions (void)
10981 static unsigned int sp_regno
[2];
10983 if (!sp_regno
[flag_code
>> 1])
10985 char *saved_input
= input_line_pointer
;
10986 char sp
[][4] = {"esp", "rsp"};
10989 input_line_pointer
= sp
[flag_code
>> 1];
10990 tc_x86_parse_to_dw2regnum (&exp
);
10991 gas_assert (exp
.X_op
== O_constant
);
10992 sp_regno
[flag_code
>> 1] = exp
.X_add_number
;
10993 input_line_pointer
= saved_input
;
10996 cfi_add_CFA_def_cfa (sp_regno
[flag_code
>> 1], -x86_cie_data_alignment
);
10997 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
11001 x86_dwarf2_addr_size (void)
11003 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
11004 if (x86_elf_abi
== X86_64_X32_ABI
)
11007 return bfd_arch_bits_per_address (stdoutput
) / 8;
11011 i386_elf_section_type (const char *str
, size_t len
)
11013 if (flag_code
== CODE_64BIT
11014 && len
== sizeof ("unwind") - 1
11015 && strncmp (str
, "unwind", 6) == 0)
11016 return SHT_X86_64_UNWIND
;
11023 i386_solaris_fix_up_eh_frame (segT sec
)
11025 if (flag_code
== CODE_64BIT
)
11026 elf_section_type (sec
) = SHT_X86_64_UNWIND
;
11032 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
11036 exp
.X_op
= O_secrel
;
11037 exp
.X_add_symbol
= symbol
;
11038 exp
.X_add_number
= 0;
11039 emit_expr (&exp
, size
);
11043 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11044 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
11047 x86_64_section_letter (int letter
, const char **ptr_msg
)
11049 if (flag_code
== CODE_64BIT
)
11052 return SHF_X86_64_LARGE
;
11054 *ptr_msg
= _("bad .section directive: want a,l,w,x,M,S,G,T in string");
11057 *ptr_msg
= _("bad .section directive: want a,w,x,M,S,G,T in string");
11062 x86_64_section_word (char *str
, size_t len
)
11064 if (len
== 5 && flag_code
== CODE_64BIT
&& CONST_STRNEQ (str
, "large"))
11065 return SHF_X86_64_LARGE
;
11071 handle_large_common (int small ATTRIBUTE_UNUSED
)
11073 if (flag_code
!= CODE_64BIT
)
11075 s_comm_internal (0, elf_common_parse
);
11076 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
11080 static segT lbss_section
;
11081 asection
*saved_com_section_ptr
= elf_com_section_ptr
;
11082 asection
*saved_bss_section
= bss_section
;
11084 if (lbss_section
== NULL
)
11086 flagword applicable
;
11087 segT seg
= now_seg
;
11088 subsegT subseg
= now_subseg
;
11090 /* The .lbss section is for local .largecomm symbols. */
11091 lbss_section
= subseg_new (".lbss", 0);
11092 applicable
= bfd_applicable_section_flags (stdoutput
);
11093 bfd_set_section_flags (stdoutput
, lbss_section
,
11094 applicable
& SEC_ALLOC
);
11095 seg_info (lbss_section
)->bss
= 1;
11097 subseg_set (seg
, subseg
);
11100 elf_com_section_ptr
= &_bfd_elf_large_com_section
;
11101 bss_section
= lbss_section
;
11103 s_comm_internal (0, elf_common_parse
);
11105 elf_com_section_ptr
= saved_com_section_ptr
;
11106 bss_section
= saved_bss_section
;
11109 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */