1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright (C) 1989-2020 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 /* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
23 x86_64 support by Jan Hubicka (jh@suse.cz)
24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
29 #include "safe-ctype.h"
31 #include "dwarf2dbg.h"
32 #include "dw2gencfi.h"
33 #include "elf/x86-64.h"
34 #include "opcodes/i386-init.h"
39 #ifdef HAVE_SYS_PARAM_H
40 #include <sys/param.h>
43 #define INT_MAX (int) (((unsigned) (-1)) >> 1)
47 #ifndef INFER_ADDR_PREFIX
48 #define INFER_ADDR_PREFIX 1
52 #define DEFAULT_ARCH "i386"
57 #define INLINE __inline__
63 /* Prefixes will be emitted in the order defined below.
64 WAIT_PREFIX must be the first prefix since FWAIT is really is an
65 instruction, and so must come before any prefixes.
66 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
67 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
73 #define HLE_PREFIX REP_PREFIX
74 #define BND_PREFIX REP_PREFIX
76 #define REX_PREFIX 6 /* must come last. */
77 #define MAX_PREFIXES 7 /* max prefixes per opcode */
79 /* we define the syntax here (modulo base,index,scale syntax) */
80 #define REGISTER_PREFIX '%'
81 #define IMMEDIATE_PREFIX '$'
82 #define ABSOLUTE_PREFIX '*'
84 /* these are the instruction mnemonic suffixes in AT&T syntax or
85 memory operand size in Intel syntax. */
86 #define WORD_MNEM_SUFFIX 'w'
87 #define BYTE_MNEM_SUFFIX 'b'
88 #define SHORT_MNEM_SUFFIX 's'
89 #define LONG_MNEM_SUFFIX 'l'
90 #define QWORD_MNEM_SUFFIX 'q'
91 /* Intel Syntax. Use a non-ascii letter since since it never appears
93 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
95 #define END_OF_INSN '\0'
97 /* This matches the C -> StaticRounding alias in the opcode table. */
98 #define commutative staticrounding
101 'templates' is for grouping together 'template' structures for opcodes
102 of the same name. This is only used for storing the insns in the grand
103 ole hash table of insns.
104 The templates themselves start at START and range up to (but not including)
109 const insn_template
*start
;
110 const insn_template
*end
;
114 /* 386 operand encoding bytes: see 386 book for details of this. */
117 unsigned int regmem
; /* codes register or memory operand */
118 unsigned int reg
; /* codes register operand (or extended opcode) */
119 unsigned int mode
; /* how to interpret regmem & reg */
123 /* x86-64 extension prefix. */
124 typedef int rex_byte
;
126 /* 386 opcode byte to code indirect addressing. */
135 /* x86 arch names, types and features */
138 const char *name
; /* arch name */
139 unsigned int len
; /* arch string length */
140 enum processor_type type
; /* arch type */
141 i386_cpu_flags flags
; /* cpu feature flags */
142 unsigned int skip
; /* show_arch should skip this. */
146 /* Used to turn off indicated flags. */
149 const char *name
; /* arch name */
150 unsigned int len
; /* arch string length */
151 i386_cpu_flags flags
; /* cpu feature flags */
155 static void update_code_flag (int, int);
156 static void set_code_flag (int);
157 static void set_16bit_gcc_code_flag (int);
158 static void set_intel_syntax (int);
159 static void set_intel_mnemonic (int);
160 static void set_allow_index_reg (int);
161 static void set_check (int);
162 static void set_cpu_arch (int);
164 static void pe_directive_secrel (int);
166 static void signed_cons (int);
167 static char *output_invalid (int c
);
168 static int i386_finalize_immediate (segT
, expressionS
*, i386_operand_type
,
170 static int i386_finalize_displacement (segT
, expressionS
*, i386_operand_type
,
172 static int i386_att_operand (char *);
173 static int i386_intel_operand (char *, int);
174 static int i386_intel_simplify (expressionS
*);
175 static int i386_intel_parse_name (const char *, expressionS
*);
176 static const reg_entry
*parse_register (char *, char **);
177 static char *parse_insn (char *, char *);
178 static char *parse_operands (char *, const char *);
179 static void swap_operands (void);
180 static void swap_2_operands (int, int);
181 static enum flag_code
i386_addressing_mode (void);
182 static void optimize_imm (void);
183 static void optimize_disp (void);
184 static const insn_template
*match_template (char);
185 static int check_string (void);
186 static int process_suffix (void);
187 static int check_byte_reg (void);
188 static int check_long_reg (void);
189 static int check_qword_reg (void);
190 static int check_word_reg (void);
191 static int finalize_imm (void);
192 static int process_operands (void);
193 static const seg_entry
*build_modrm_byte (void);
194 static void output_insn (void);
195 static void output_imm (fragS
*, offsetT
);
196 static void output_disp (fragS
*, offsetT
);
198 static void s_bss (int);
200 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
201 static void handle_large_common (int small ATTRIBUTE_UNUSED
);
203 /* GNU_PROPERTY_X86_ISA_1_USED. */
204 static unsigned int x86_isa_1_used
;
205 /* GNU_PROPERTY_X86_FEATURE_2_USED. */
206 static unsigned int x86_feature_2_used
;
207 /* Generate x86 used ISA and feature properties. */
208 static unsigned int x86_used_note
= DEFAULT_X86_USED_NOTE
;
211 static const char *default_arch
= DEFAULT_ARCH
;
213 /* This struct describes rounding control and SAE in the instruction. */
227 static struct RC_Operation rc_op
;
229 /* The struct describes masking, applied to OPERAND in the instruction.
230 MASK is a pointer to the corresponding mask register. ZEROING tells
231 whether merging or zeroing mask is used. */
232 struct Mask_Operation
234 const reg_entry
*mask
;
235 unsigned int zeroing
;
236 /* The operand where this operation is associated. */
240 static struct Mask_Operation mask_op
;
242 /* The struct describes broadcasting, applied to OPERAND. FACTOR is
244 struct Broadcast_Operation
246 /* Type of broadcast: {1to2}, {1to4}, {1to8}, or {1to16}. */
249 /* Index of broadcasted operand. */
252 /* Number of bytes to broadcast. */
256 static struct Broadcast_Operation broadcast_op
;
261 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
262 unsigned char bytes
[4];
264 /* Destination or source register specifier. */
265 const reg_entry
*register_specifier
;
268 /* 'md_assemble ()' gathers together information and puts it into a
275 const reg_entry
*regs
;
280 operand_size_mismatch
,
281 operand_type_mismatch
,
282 register_type_mismatch
,
283 number_of_operands_mismatch
,
284 invalid_instruction_suffix
,
286 unsupported_with_intel_mnemonic
,
289 invalid_vsib_address
,
290 invalid_vector_register_set
,
291 unsupported_vector_index_register
,
292 unsupported_broadcast
,
295 mask_not_on_destination
,
298 rc_sae_operand_not_last_imm
,
299 invalid_register_operand
,
304 /* TM holds the template for the insn were currently assembling. */
307 /* SUFFIX holds the instruction size suffix for byte, word, dword
308 or qword, if given. */
311 /* OPERANDS gives the number of given operands. */
312 unsigned int operands
;
314 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
315 of given register, displacement, memory operands and immediate
317 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
319 /* TYPES [i] is the type (see above #defines) which tells us how to
320 use OP[i] for the corresponding operand. */
321 i386_operand_type types
[MAX_OPERANDS
];
323 /* Displacement expression, immediate expression, or register for each
325 union i386_op op
[MAX_OPERANDS
];
327 /* Flags for operands. */
328 unsigned int flags
[MAX_OPERANDS
];
329 #define Operand_PCrel 1
330 #define Operand_Mem 2
332 /* Relocation type for operand */
333 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
335 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
336 the base index byte below. */
337 const reg_entry
*base_reg
;
338 const reg_entry
*index_reg
;
339 unsigned int log2_scale_factor
;
341 /* SEG gives the seg_entries of this insn. They are zero unless
342 explicit segment overrides are given. */
343 const seg_entry
*seg
[2];
345 /* Copied first memory operand string, for re-checking. */
348 /* PREFIX holds all the given prefix opcodes (usually null).
349 PREFIXES is the number of prefix opcodes. */
350 unsigned int prefixes
;
351 unsigned char prefix
[MAX_PREFIXES
];
353 /* Register is in low 3 bits of opcode. */
354 bfd_boolean short_form
;
356 /* The operand to a branch insn indicates an absolute branch. */
357 bfd_boolean jumpabsolute
;
359 /* Has MMX register operands. */
360 bfd_boolean has_regmmx
;
362 /* Has XMM register operands. */
363 bfd_boolean has_regxmm
;
365 /* Has YMM register operands. */
366 bfd_boolean has_regymm
;
368 /* Has ZMM register operands. */
369 bfd_boolean has_regzmm
;
371 /* Has GOTPC or TLS relocation. */
372 bfd_boolean has_gotpc_tls_reloc
;
374 /* RM and SIB are the modrm byte and the sib byte where the
375 addressing modes of this insn are encoded. */
382 /* Masking attributes. */
383 struct Mask_Operation
*mask
;
385 /* Rounding control and SAE attributes. */
386 struct RC_Operation
*rounding
;
388 /* Broadcasting attributes. */
389 struct Broadcast_Operation
*broadcast
;
391 /* Compressed disp8*N attribute. */
392 unsigned int memshift
;
394 /* Prefer load or store in encoding. */
397 dir_encoding_default
= 0,
403 /* Prefer 8bit or 32bit displacement in encoding. */
406 disp_encoding_default
= 0,
411 /* Prefer the REX byte in encoding. */
412 bfd_boolean rex_encoding
;
414 /* Disable instruction size optimization. */
415 bfd_boolean no_optimize
;
417 /* How to encode vector instructions. */
420 vex_encoding_default
= 0,
427 const char *rep_prefix
;
430 const char *hle_prefix
;
432 /* Have BND prefix. */
433 const char *bnd_prefix
;
435 /* Have NOTRACK prefix. */
436 const char *notrack_prefix
;
439 enum i386_error error
;
442 typedef struct _i386_insn i386_insn
;
444 /* Link RC type with corresponding string, that'll be looked for in
453 static const struct RC_name RC_NamesTable
[] =
455 { rne
, STRING_COMMA_LEN ("rn-sae") },
456 { rd
, STRING_COMMA_LEN ("rd-sae") },
457 { ru
, STRING_COMMA_LEN ("ru-sae") },
458 { rz
, STRING_COMMA_LEN ("rz-sae") },
459 { saeonly
, STRING_COMMA_LEN ("sae") },
462 /* List of chars besides those in app.c:symbol_chars that can start an
463 operand. Used to prevent the scrubber eating vital white-space. */
464 const char extra_symbol_chars
[] = "*%-([{}"
473 #if (defined (TE_I386AIX) \
474 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
475 && !defined (TE_GNU) \
476 && !defined (TE_LINUX) \
477 && !defined (TE_NACL) \
478 && !defined (TE_FreeBSD) \
479 && !defined (TE_DragonFly) \
480 && !defined (TE_NetBSD)))
481 /* This array holds the chars that always start a comment. If the
482 pre-processor is disabled, these aren't very useful. The option
483 --divide will remove '/' from this list. */
484 const char *i386_comment_chars
= "#/";
485 #define SVR4_COMMENT_CHARS 1
486 #define PREFIX_SEPARATOR '\\'
489 const char *i386_comment_chars
= "#";
490 #define PREFIX_SEPARATOR '/'
493 /* This array holds the chars that only start a comment at the beginning of
494 a line. If the line seems to have the form '# 123 filename'
495 .line and .file directives will appear in the pre-processed output.
496 Note that input_file.c hand checks for '#' at the beginning of the
497 first line of the input file. This is because the compiler outputs
498 #NO_APP at the beginning of its output.
499 Also note that comments started like this one will always work if
500 '/' isn't otherwise defined. */
501 const char line_comment_chars
[] = "#/";
503 const char line_separator_chars
[] = ";";
505 /* Chars that can be used to separate mant from exp in floating point
507 const char EXP_CHARS
[] = "eE";
509 /* Chars that mean this number is a floating point constant
512 const char FLT_CHARS
[] = "fFdDxX";
514 /* Tables for lexical analysis. */
515 static char mnemonic_chars
[256];
516 static char register_chars
[256];
517 static char operand_chars
[256];
518 static char identifier_chars
[256];
519 static char digit_chars
[256];
521 /* Lexical macros. */
522 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
523 #define is_operand_char(x) (operand_chars[(unsigned char) x])
524 #define is_register_char(x) (register_chars[(unsigned char) x])
525 #define is_space_char(x) ((x) == ' ')
526 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
527 #define is_digit_char(x) (digit_chars[(unsigned char) x])
529 /* All non-digit non-letter characters that may occur in an operand. */
530 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
532 /* md_assemble() always leaves the strings it's passed unaltered. To
533 effect this we maintain a stack of saved characters that we've smashed
534 with '\0's (indicating end of strings for various sub-fields of the
535 assembler instruction). */
536 static char save_stack
[32];
537 static char *save_stack_p
;
538 #define END_STRING_AND_SAVE(s) \
539 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
540 #define RESTORE_END_STRING(s) \
541 do { *(s) = *--save_stack_p; } while (0)
543 /* The instruction we're assembling. */
546 /* Possible templates for current insn. */
547 static const templates
*current_templates
;
549 /* Per instruction expressionS buffers: max displacements & immediates. */
550 static expressionS disp_expressions
[MAX_MEMORY_OPERANDS
];
551 static expressionS im_expressions
[MAX_IMMEDIATE_OPERANDS
];
553 /* Current operand we are working on. */
554 static int this_operand
= -1;
556 /* We support four different modes. FLAG_CODE variable is used to distinguish
564 static enum flag_code flag_code
;
565 static unsigned int object_64bit
;
566 static unsigned int disallow_64bit_reloc
;
567 static int use_rela_relocations
= 0;
568 /* __tls_get_addr/___tls_get_addr symbol for TLS. */
569 static const char *tls_get_addr
;
571 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
572 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
573 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
575 /* The ELF ABI to use. */
583 static enum x86_elf_abi x86_elf_abi
= I386_ABI
;
586 #if defined (TE_PE) || defined (TE_PEP)
587 /* Use big object file format. */
588 static int use_big_obj
= 0;
591 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
592 /* 1 if generating code for a shared library. */
593 static int shared
= 0;
596 /* 1 for intel syntax,
598 static int intel_syntax
= 0;
600 static enum x86_64_isa
602 amd64
= 1, /* AMD64 ISA. */
603 intel64
/* Intel64 ISA. */
606 /* 1 for intel mnemonic,
607 0 if att mnemonic. */
608 static int intel_mnemonic
= !SYSV386_COMPAT
;
610 /* 1 if pseudo registers are permitted. */
611 static int allow_pseudo_reg
= 0;
613 /* 1 if register prefix % not required. */
614 static int allow_naked_reg
= 0;
616 /* 1 if the assembler should add BND prefix for all control-transferring
617 instructions supporting it, even if this prefix wasn't specified
619 static int add_bnd_prefix
= 0;
621 /* 1 if pseudo index register, eiz/riz, is allowed . */
622 static int allow_index_reg
= 0;
624 /* 1 if the assembler should ignore LOCK prefix, even if it was
625 specified explicitly. */
626 static int omit_lock_prefix
= 0;
628 /* 1 if the assembler should encode lfence, mfence, and sfence as
629 "lock addl $0, (%{re}sp)". */
630 static int avoid_fence
= 0;
632 /* Type of the previous instruction. */
647 /* 1 if the assembler should generate relax relocations. */
649 static int generate_relax_relocations
650 = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS
;
652 static enum check_kind
658 sse_check
, operand_check
= check_warning
;
660 /* Non-zero if branches should be aligned within power of 2 boundary. */
661 static int align_branch_power
= 0;
663 /* Types of branches to align. */
664 enum align_branch_kind
666 align_branch_none
= 0,
667 align_branch_jcc
= 1,
668 align_branch_fused
= 2,
669 align_branch_jmp
= 3,
670 align_branch_call
= 4,
671 align_branch_indirect
= 5,
675 /* Type bits of branches to align. */
676 enum align_branch_bit
678 align_branch_jcc_bit
= 1 << align_branch_jcc
,
679 align_branch_fused_bit
= 1 << align_branch_fused
,
680 align_branch_jmp_bit
= 1 << align_branch_jmp
,
681 align_branch_call_bit
= 1 << align_branch_call
,
682 align_branch_indirect_bit
= 1 << align_branch_indirect
,
683 align_branch_ret_bit
= 1 << align_branch_ret
686 static unsigned int align_branch
= (align_branch_jcc_bit
687 | align_branch_fused_bit
688 | align_branch_jmp_bit
);
690 /* Types of condition jump used by macro-fusion. */
693 mf_jcc_jo
= 0, /* base opcode 0x70 */
694 mf_jcc_jc
, /* base opcode 0x72 */
695 mf_jcc_je
, /* base opcode 0x74 */
696 mf_jcc_jna
, /* base opcode 0x76 */
697 mf_jcc_js
, /* base opcode 0x78 */
698 mf_jcc_jp
, /* base opcode 0x7a */
699 mf_jcc_jl
, /* base opcode 0x7c */
700 mf_jcc_jle
, /* base opcode 0x7e */
703 /* Types of compare flag-modifying insntructions used by macro-fusion. */
706 mf_cmp_test_and
, /* test/cmp */
707 mf_cmp_alu_cmp
, /* add/sub/cmp */
708 mf_cmp_incdec
/* inc/dec */
711 /* The maximum padding size for fused jcc. CMP like instruction can
712 be 9 bytes and jcc can be 6 bytes. Leave room just in case for
714 #define MAX_FUSED_JCC_PADDING_SIZE 20
716 /* The maximum number of prefixes added for an instruction. */
717 static unsigned int align_branch_prefix_size
= 5;
720 1. Clear the REX_W bit with register operand if possible.
721 2. Above plus use 128bit vector instruction to clear the full vector
724 static int optimize
= 0;
727 1. Clear the REX_W bit with register operand if possible.
728 2. Above plus use 128bit vector instruction to clear the full vector
730 3. Above plus optimize "test{q,l,w} $imm8,%r{64,32,16}" to
733 static int optimize_for_space
= 0;
735 /* Register prefix used for error message. */
736 static const char *register_prefix
= "%";
738 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
739 leave, push, and pop instructions so that gcc has the same stack
740 frame as in 32 bit mode. */
741 static char stackop_size
= '\0';
743 /* Non-zero to optimize code alignment. */
744 int optimize_align_code
= 1;
746 /* Non-zero to quieten some warnings. */
747 static int quiet_warnings
= 0;
750 static const char *cpu_arch_name
= NULL
;
751 static char *cpu_sub_arch_name
= NULL
;
753 /* CPU feature flags. */
754 static i386_cpu_flags cpu_arch_flags
= CPU_UNKNOWN_FLAGS
;
756 /* If we have selected a cpu we are generating instructions for. */
757 static int cpu_arch_tune_set
= 0;
759 /* Cpu we are generating instructions for. */
760 enum processor_type cpu_arch_tune
= PROCESSOR_UNKNOWN
;
762 /* CPU feature flags of cpu we are generating instructions for. */
763 static i386_cpu_flags cpu_arch_tune_flags
;
765 /* CPU instruction set architecture used. */
766 enum processor_type cpu_arch_isa
= PROCESSOR_UNKNOWN
;
768 /* CPU feature flags of instruction set architecture used. */
769 i386_cpu_flags cpu_arch_isa_flags
;
771 /* If set, conditional jumps are not automatically promoted to handle
772 larger than a byte offset. */
773 static unsigned int no_cond_jump_promotion
= 0;
775 /* Encode SSE instructions with VEX prefix. */
776 static unsigned int sse2avx
;
778 /* Encode scalar AVX instructions with specific vector length. */
785 /* Encode VEX WIG instructions with specific vex.w. */
792 /* Encode scalar EVEX LIG instructions with specific vector length. */
800 /* Encode EVEX WIG instructions with specific evex.w. */
807 /* Value to encode in EVEX RC bits, for SAE-only instructions. */
808 static enum rc_type evexrcig
= rne
;
810 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
811 static symbolS
*GOT_symbol
;
813 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
814 unsigned int x86_dwarf2_return_column
;
816 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
817 int x86_cie_data_alignment
;
819 /* Interface to relax_segment.
820 There are 3 major relax states for 386 jump insns because the
821 different types of jumps add different sizes to frags when we're
822 figuring out what sort of jump to choose to reach a given label.
824 BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING are used to align
825 branches which are handled by md_estimate_size_before_relax() and
826 i386_generic_table_relax_frag(). */
829 #define UNCOND_JUMP 0
831 #define COND_JUMP86 2
832 #define BRANCH_PADDING 3
833 #define BRANCH_PREFIX 4
834 #define FUSED_JCC_PADDING 5
839 #define SMALL16 (SMALL | CODE16)
841 #define BIG16 (BIG | CODE16)
845 #define INLINE __inline__
851 #define ENCODE_RELAX_STATE(type, size) \
852 ((relax_substateT) (((type) << 2) | (size)))
853 #define TYPE_FROM_RELAX_STATE(s) \
855 #define DISP_SIZE_FROM_RELAX_STATE(s) \
856 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
858 /* This table is used by relax_frag to promote short jumps to long
859 ones where necessary. SMALL (short) jumps may be promoted to BIG
860 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
861 don't allow a short jump in a 32 bit code segment to be promoted to
862 a 16 bit offset jump because it's slower (requires data size
863 prefix), and doesn't work, unless the destination is in the bottom
864 64k of the code segment (The top 16 bits of eip are zeroed). */
866 const relax_typeS md_relax_table
[] =
869 1) most positive reach of this state,
870 2) most negative reach of this state,
871 3) how many bytes this mode will have in the variable part of the frag
872 4) which index into the table to try if we can't fit into this one. */
874 /* UNCOND_JUMP states. */
875 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
876 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
877 /* dword jmp adds 4 bytes to frag:
878 0 extra opcode bytes, 4 displacement bytes. */
880 /* word jmp adds 2 byte2 to frag:
881 0 extra opcode bytes, 2 displacement bytes. */
884 /* COND_JUMP states. */
885 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
886 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
887 /* dword conditionals adds 5 bytes to frag:
888 1 extra opcode byte, 4 displacement bytes. */
890 /* word conditionals add 3 bytes to frag:
891 1 extra opcode byte, 2 displacement bytes. */
894 /* COND_JUMP86 states. */
895 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
896 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
897 /* dword conditionals adds 5 bytes to frag:
898 1 extra opcode byte, 4 displacement bytes. */
900 /* word conditionals add 4 bytes to frag:
901 1 displacement byte and a 3 byte long branch insn. */
905 static const arch_entry cpu_arch
[] =
907 /* Do not replace the first two entries - i386_target_format()
908 relies on them being there in this order. */
909 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32
,
910 CPU_GENERIC32_FLAGS
, 0 },
911 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64
,
912 CPU_GENERIC64_FLAGS
, 0 },
913 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN
,
915 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN
,
917 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN
,
919 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386
,
921 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486
,
923 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM
,
925 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO
,
927 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM
,
929 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO
,
930 CPU_PENTIUMPRO_FLAGS
, 0 },
931 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO
,
933 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO
,
935 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4
,
937 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA
,
939 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA
,
940 CPU_NOCONA_FLAGS
, 0 },
941 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE
,
943 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE
,
945 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2
,
946 CPU_CORE2_FLAGS
, 1 },
947 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2
,
948 CPU_CORE2_FLAGS
, 0 },
949 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7
,
950 CPU_COREI7_FLAGS
, 0 },
951 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM
,
953 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM
,
955 { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU
,
956 CPU_IAMCU_FLAGS
, 0 },
957 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6
,
959 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6
,
961 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON
,
962 CPU_ATHLON_FLAGS
, 0 },
963 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8
,
965 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8
,
967 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8
,
969 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10
,
970 CPU_AMDFAM10_FLAGS
, 0 },
971 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD
,
972 CPU_BDVER1_FLAGS
, 0 },
973 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD
,
974 CPU_BDVER2_FLAGS
, 0 },
975 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD
,
976 CPU_BDVER3_FLAGS
, 0 },
977 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD
,
978 CPU_BDVER4_FLAGS
, 0 },
979 { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER
,
980 CPU_ZNVER1_FLAGS
, 0 },
981 { STRING_COMMA_LEN ("znver2"), PROCESSOR_ZNVER
,
982 CPU_ZNVER2_FLAGS
, 0 },
983 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT
,
984 CPU_BTVER1_FLAGS
, 0 },
985 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT
,
986 CPU_BTVER2_FLAGS
, 0 },
987 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN
,
989 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN
,
991 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN
,
993 { STRING_COMMA_LEN (".687"), PROCESSOR_UNKNOWN
,
995 { STRING_COMMA_LEN (".cmov"), PROCESSOR_UNKNOWN
,
997 { STRING_COMMA_LEN (".fxsr"), PROCESSOR_UNKNOWN
,
999 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN
,
1001 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN
,
1003 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN
,
1004 CPU_SSE2_FLAGS
, 0 },
1005 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN
,
1006 CPU_SSE3_FLAGS
, 0 },
1007 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN
,
1008 CPU_SSE4A_FLAGS
, 0 },
1009 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN
,
1010 CPU_SSSE3_FLAGS
, 0 },
1011 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN
,
1012 CPU_SSE4_1_FLAGS
, 0 },
1013 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN
,
1014 CPU_SSE4_2_FLAGS
, 0 },
1015 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN
,
1016 CPU_SSE4_2_FLAGS
, 0 },
1017 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN
,
1019 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN
,
1020 CPU_AVX2_FLAGS
, 0 },
1021 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN
,
1022 CPU_AVX512F_FLAGS
, 0 },
1023 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN
,
1024 CPU_AVX512CD_FLAGS
, 0 },
1025 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN
,
1026 CPU_AVX512ER_FLAGS
, 0 },
1027 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN
,
1028 CPU_AVX512PF_FLAGS
, 0 },
1029 { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN
,
1030 CPU_AVX512DQ_FLAGS
, 0 },
1031 { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN
,
1032 CPU_AVX512BW_FLAGS
, 0 },
1033 { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN
,
1034 CPU_AVX512VL_FLAGS
, 0 },
1035 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN
,
1037 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN
,
1038 CPU_VMFUNC_FLAGS
, 0 },
1039 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN
,
1041 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN
,
1042 CPU_XSAVE_FLAGS
, 0 },
1043 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN
,
1044 CPU_XSAVEOPT_FLAGS
, 0 },
1045 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN
,
1046 CPU_XSAVEC_FLAGS
, 0 },
1047 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN
,
1048 CPU_XSAVES_FLAGS
, 0 },
1049 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN
,
1051 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN
,
1052 CPU_PCLMUL_FLAGS
, 0 },
1053 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN
,
1054 CPU_PCLMUL_FLAGS
, 1 },
1055 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN
,
1056 CPU_FSGSBASE_FLAGS
, 0 },
1057 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN
,
1058 CPU_RDRND_FLAGS
, 0 },
1059 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN
,
1060 CPU_F16C_FLAGS
, 0 },
1061 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN
,
1062 CPU_BMI2_FLAGS
, 0 },
1063 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN
,
1065 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN
,
1066 CPU_FMA4_FLAGS
, 0 },
1067 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN
,
1069 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN
,
1071 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN
,
1072 CPU_MOVBE_FLAGS
, 0 },
1073 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN
,
1074 CPU_CX16_FLAGS
, 0 },
1075 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN
,
1077 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN
,
1078 CPU_LZCNT_FLAGS
, 0 },
1079 { STRING_COMMA_LEN (".popcnt"), PROCESSOR_UNKNOWN
,
1080 CPU_POPCNT_FLAGS
, 0 },
1081 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN
,
1083 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN
,
1085 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN
,
1086 CPU_INVPCID_FLAGS
, 0 },
1087 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN
,
1088 CPU_CLFLUSH_FLAGS
, 0 },
1089 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN
,
1091 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN
,
1092 CPU_SYSCALL_FLAGS
, 0 },
1093 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN
,
1094 CPU_RDTSCP_FLAGS
, 0 },
1095 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN
,
1096 CPU_3DNOW_FLAGS
, 0 },
1097 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN
,
1098 CPU_3DNOWA_FLAGS
, 0 },
1099 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN
,
1100 CPU_PADLOCK_FLAGS
, 0 },
1101 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN
,
1102 CPU_SVME_FLAGS
, 1 },
1103 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN
,
1104 CPU_SVME_FLAGS
, 0 },
1105 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN
,
1106 CPU_SSE4A_FLAGS
, 0 },
1107 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN
,
1109 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN
,
1111 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN
,
1113 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN
,
1115 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN
,
1116 CPU_RDSEED_FLAGS
, 0 },
1117 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN
,
1118 CPU_PRFCHW_FLAGS
, 0 },
1119 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN
,
1120 CPU_SMAP_FLAGS
, 0 },
1121 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN
,
1123 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN
,
1125 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN
,
1126 CPU_CLFLUSHOPT_FLAGS
, 0 },
1127 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN
,
1128 CPU_PREFETCHWT1_FLAGS
, 0 },
1129 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN
,
1131 { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN
,
1132 CPU_CLWB_FLAGS
, 0 },
1133 { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN
,
1134 CPU_AVX512IFMA_FLAGS
, 0 },
1135 { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN
,
1136 CPU_AVX512VBMI_FLAGS
, 0 },
1137 { STRING_COMMA_LEN (".avx512_4fmaps"), PROCESSOR_UNKNOWN
,
1138 CPU_AVX512_4FMAPS_FLAGS
, 0 },
1139 { STRING_COMMA_LEN (".avx512_4vnniw"), PROCESSOR_UNKNOWN
,
1140 CPU_AVX512_4VNNIW_FLAGS
, 0 },
1141 { STRING_COMMA_LEN (".avx512_vpopcntdq"), PROCESSOR_UNKNOWN
,
1142 CPU_AVX512_VPOPCNTDQ_FLAGS
, 0 },
1143 { STRING_COMMA_LEN (".avx512_vbmi2"), PROCESSOR_UNKNOWN
,
1144 CPU_AVX512_VBMI2_FLAGS
, 0 },
1145 { STRING_COMMA_LEN (".avx512_vnni"), PROCESSOR_UNKNOWN
,
1146 CPU_AVX512_VNNI_FLAGS
, 0 },
1147 { STRING_COMMA_LEN (".avx512_bitalg"), PROCESSOR_UNKNOWN
,
1148 CPU_AVX512_BITALG_FLAGS
, 0 },
1149 { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN
,
1150 CPU_CLZERO_FLAGS
, 0 },
1151 { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN
,
1152 CPU_MWAITX_FLAGS
, 0 },
1153 { STRING_COMMA_LEN (".ospke"), PROCESSOR_UNKNOWN
,
1154 CPU_OSPKE_FLAGS
, 0 },
1155 { STRING_COMMA_LEN (".rdpid"), PROCESSOR_UNKNOWN
,
1156 CPU_RDPID_FLAGS
, 0 },
1157 { STRING_COMMA_LEN (".ptwrite"), PROCESSOR_UNKNOWN
,
1158 CPU_PTWRITE_FLAGS
, 0 },
1159 { STRING_COMMA_LEN (".ibt"), PROCESSOR_UNKNOWN
,
1161 { STRING_COMMA_LEN (".shstk"), PROCESSOR_UNKNOWN
,
1162 CPU_SHSTK_FLAGS
, 0 },
1163 { STRING_COMMA_LEN (".gfni"), PROCESSOR_UNKNOWN
,
1164 CPU_GFNI_FLAGS
, 0 },
1165 { STRING_COMMA_LEN (".vaes"), PROCESSOR_UNKNOWN
,
1166 CPU_VAES_FLAGS
, 0 },
1167 { STRING_COMMA_LEN (".vpclmulqdq"), PROCESSOR_UNKNOWN
,
1168 CPU_VPCLMULQDQ_FLAGS
, 0 },
1169 { STRING_COMMA_LEN (".wbnoinvd"), PROCESSOR_UNKNOWN
,
1170 CPU_WBNOINVD_FLAGS
, 0 },
1171 { STRING_COMMA_LEN (".pconfig"), PROCESSOR_UNKNOWN
,
1172 CPU_PCONFIG_FLAGS
, 0 },
1173 { STRING_COMMA_LEN (".waitpkg"), PROCESSOR_UNKNOWN
,
1174 CPU_WAITPKG_FLAGS
, 0 },
1175 { STRING_COMMA_LEN (".cldemote"), PROCESSOR_UNKNOWN
,
1176 CPU_CLDEMOTE_FLAGS
, 0 },
1177 { STRING_COMMA_LEN (".movdiri"), PROCESSOR_UNKNOWN
,
1178 CPU_MOVDIRI_FLAGS
, 0 },
1179 { STRING_COMMA_LEN (".movdir64b"), PROCESSOR_UNKNOWN
,
1180 CPU_MOVDIR64B_FLAGS
, 0 },
1181 { STRING_COMMA_LEN (".avx512_bf16"), PROCESSOR_UNKNOWN
,
1182 CPU_AVX512_BF16_FLAGS
, 0 },
1183 { STRING_COMMA_LEN (".avx512_vp2intersect"), PROCESSOR_UNKNOWN
,
1184 CPU_AVX512_VP2INTERSECT_FLAGS
, 0 },
1185 { STRING_COMMA_LEN (".enqcmd"), PROCESSOR_UNKNOWN
,
1186 CPU_ENQCMD_FLAGS
, 0 },
1187 { STRING_COMMA_LEN (".rdpru"), PROCESSOR_UNKNOWN
,
1188 CPU_RDPRU_FLAGS
, 0 },
1189 { STRING_COMMA_LEN (".mcommit"), PROCESSOR_UNKNOWN
,
1190 CPU_MCOMMIT_FLAGS
, 0 },
1191 { STRING_COMMA_LEN (".sev_es"), PROCESSOR_UNKNOWN
,
1192 CPU_SEV_ES_FLAGS
, 0 },
1195 static const noarch_entry cpu_noarch
[] =
1197 { STRING_COMMA_LEN ("no87"), CPU_ANY_X87_FLAGS
},
1198 { STRING_COMMA_LEN ("no287"), CPU_ANY_287_FLAGS
},
1199 { STRING_COMMA_LEN ("no387"), CPU_ANY_387_FLAGS
},
1200 { STRING_COMMA_LEN ("no687"), CPU_ANY_687_FLAGS
},
1201 { STRING_COMMA_LEN ("nocmov"), CPU_ANY_CMOV_FLAGS
},
1202 { STRING_COMMA_LEN ("nofxsr"), CPU_ANY_FXSR_FLAGS
},
1203 { STRING_COMMA_LEN ("nommx"), CPU_ANY_MMX_FLAGS
},
1204 { STRING_COMMA_LEN ("nosse"), CPU_ANY_SSE_FLAGS
},
1205 { STRING_COMMA_LEN ("nosse2"), CPU_ANY_SSE2_FLAGS
},
1206 { STRING_COMMA_LEN ("nosse3"), CPU_ANY_SSE3_FLAGS
},
1207 { STRING_COMMA_LEN ("nosse4a"), CPU_ANY_SSE4A_FLAGS
},
1208 { STRING_COMMA_LEN ("nossse3"), CPU_ANY_SSSE3_FLAGS
},
1209 { STRING_COMMA_LEN ("nosse4.1"), CPU_ANY_SSE4_1_FLAGS
},
1210 { STRING_COMMA_LEN ("nosse4.2"), CPU_ANY_SSE4_2_FLAGS
},
1211 { STRING_COMMA_LEN ("nosse4"), CPU_ANY_SSE4_1_FLAGS
},
1212 { STRING_COMMA_LEN ("noavx"), CPU_ANY_AVX_FLAGS
},
1213 { STRING_COMMA_LEN ("noavx2"), CPU_ANY_AVX2_FLAGS
},
1214 { STRING_COMMA_LEN ("noavx512f"), CPU_ANY_AVX512F_FLAGS
},
1215 { STRING_COMMA_LEN ("noavx512cd"), CPU_ANY_AVX512CD_FLAGS
},
1216 { STRING_COMMA_LEN ("noavx512er"), CPU_ANY_AVX512ER_FLAGS
},
1217 { STRING_COMMA_LEN ("noavx512pf"), CPU_ANY_AVX512PF_FLAGS
},
1218 { STRING_COMMA_LEN ("noavx512dq"), CPU_ANY_AVX512DQ_FLAGS
},
1219 { STRING_COMMA_LEN ("noavx512bw"), CPU_ANY_AVX512BW_FLAGS
},
1220 { STRING_COMMA_LEN ("noavx512vl"), CPU_ANY_AVX512VL_FLAGS
},
1221 { STRING_COMMA_LEN ("noavx512ifma"), CPU_ANY_AVX512IFMA_FLAGS
},
1222 { STRING_COMMA_LEN ("noavx512vbmi"), CPU_ANY_AVX512VBMI_FLAGS
},
1223 { STRING_COMMA_LEN ("noavx512_4fmaps"), CPU_ANY_AVX512_4FMAPS_FLAGS
},
1224 { STRING_COMMA_LEN ("noavx512_4vnniw"), CPU_ANY_AVX512_4VNNIW_FLAGS
},
1225 { STRING_COMMA_LEN ("noavx512_vpopcntdq"), CPU_ANY_AVX512_VPOPCNTDQ_FLAGS
},
1226 { STRING_COMMA_LEN ("noavx512_vbmi2"), CPU_ANY_AVX512_VBMI2_FLAGS
},
1227 { STRING_COMMA_LEN ("noavx512_vnni"), CPU_ANY_AVX512_VNNI_FLAGS
},
1228 { STRING_COMMA_LEN ("noavx512_bitalg"), CPU_ANY_AVX512_BITALG_FLAGS
},
1229 { STRING_COMMA_LEN ("noibt"), CPU_ANY_IBT_FLAGS
},
1230 { STRING_COMMA_LEN ("noshstk"), CPU_ANY_SHSTK_FLAGS
},
1231 { STRING_COMMA_LEN ("nomovdiri"), CPU_ANY_MOVDIRI_FLAGS
},
1232 { STRING_COMMA_LEN ("nomovdir64b"), CPU_ANY_MOVDIR64B_FLAGS
},
1233 { STRING_COMMA_LEN ("noavx512_bf16"), CPU_ANY_AVX512_BF16_FLAGS
},
1234 { STRING_COMMA_LEN ("noavx512_vp2intersect"), CPU_ANY_SHSTK_FLAGS
},
1235 { STRING_COMMA_LEN ("noenqcmd"), CPU_ANY_ENQCMD_FLAGS
},
1239 /* Like s_lcomm_internal in gas/read.c but the alignment string
1240 is allowed to be optional. */
1243 pe_lcomm_internal (int needs_align
, symbolS
*symbolP
, addressT size
)
1250 && *input_line_pointer
== ',')
1252 align
= parse_align (needs_align
- 1);
1254 if (align
== (addressT
) -1)
1269 bss_alloc (symbolP
, size
, align
);
1274 pe_lcomm (int needs_align
)
1276 s_comm_internal (needs_align
* 2, pe_lcomm_internal
);
1280 const pseudo_typeS md_pseudo_table
[] =
1282 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
1283 {"align", s_align_bytes
, 0},
1285 {"align", s_align_ptwo
, 0},
1287 {"arch", set_cpu_arch
, 0},
1291 {"lcomm", pe_lcomm
, 1},
1293 {"ffloat", float_cons
, 'f'},
1294 {"dfloat", float_cons
, 'd'},
1295 {"tfloat", float_cons
, 'x'},
1297 {"slong", signed_cons
, 4},
1298 {"noopt", s_ignore
, 0},
1299 {"optim", s_ignore
, 0},
1300 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
1301 {"code16", set_code_flag
, CODE_16BIT
},
1302 {"code32", set_code_flag
, CODE_32BIT
},
1304 {"code64", set_code_flag
, CODE_64BIT
},
1306 {"intel_syntax", set_intel_syntax
, 1},
1307 {"att_syntax", set_intel_syntax
, 0},
1308 {"intel_mnemonic", set_intel_mnemonic
, 1},
1309 {"att_mnemonic", set_intel_mnemonic
, 0},
1310 {"allow_index_reg", set_allow_index_reg
, 1},
1311 {"disallow_index_reg", set_allow_index_reg
, 0},
1312 {"sse_check", set_check
, 0},
1313 {"operand_check", set_check
, 1},
1314 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1315 {"largecomm", handle_large_common
, 0},
1317 {"file", dwarf2_directive_file
, 0},
1318 {"loc", dwarf2_directive_loc
, 0},
1319 {"loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0},
1322 {"secrel32", pe_directive_secrel
, 0},
1327 /* For interface with expression (). */
1328 extern char *input_line_pointer
;
1330 /* Hash table for instruction mnemonic lookup. */
1331 static struct hash_control
*op_hash
;
1333 /* Hash table for register lookup. */
1334 static struct hash_control
*reg_hash
;
1336 /* Various efficient no-op patterns for aligning code labels.
1337 Note: Don't try to assemble the instructions in the comments.
1338 0L and 0w are not legal. */
1339 static const unsigned char f32_1
[] =
1341 static const unsigned char f32_2
[] =
1342 {0x66,0x90}; /* xchg %ax,%ax */
1343 static const unsigned char f32_3
[] =
1344 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1345 static const unsigned char f32_4
[] =
1346 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1347 static const unsigned char f32_6
[] =
1348 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1349 static const unsigned char f32_7
[] =
1350 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1351 static const unsigned char f16_3
[] =
1352 {0x8d,0x74,0x00}; /* lea 0(%si),%si */
1353 static const unsigned char f16_4
[] =
1354 {0x8d,0xb4,0x00,0x00}; /* lea 0W(%si),%si */
1355 static const unsigned char jump_disp8
[] =
1356 {0xeb}; /* jmp disp8 */
1357 static const unsigned char jump32_disp32
[] =
1358 {0xe9}; /* jmp disp32 */
1359 static const unsigned char jump16_disp32
[] =
1360 {0x66,0xe9}; /* jmp disp32 */
1361 /* 32-bit NOPs patterns. */
1362 static const unsigned char *const f32_patt
[] = {
1363 f32_1
, f32_2
, f32_3
, f32_4
, NULL
, f32_6
, f32_7
1365 /* 16-bit NOPs patterns. */
1366 static const unsigned char *const f16_patt
[] = {
1367 f32_1
, f32_2
, f16_3
, f16_4
1369 /* nopl (%[re]ax) */
1370 static const unsigned char alt_3
[] =
1372 /* nopl 0(%[re]ax) */
1373 static const unsigned char alt_4
[] =
1374 {0x0f,0x1f,0x40,0x00};
1375 /* nopl 0(%[re]ax,%[re]ax,1) */
1376 static const unsigned char alt_5
[] =
1377 {0x0f,0x1f,0x44,0x00,0x00};
1378 /* nopw 0(%[re]ax,%[re]ax,1) */
1379 static const unsigned char alt_6
[] =
1380 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1381 /* nopl 0L(%[re]ax) */
1382 static const unsigned char alt_7
[] =
1383 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1384 /* nopl 0L(%[re]ax,%[re]ax,1) */
1385 static const unsigned char alt_8
[] =
1386 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1387 /* nopw 0L(%[re]ax,%[re]ax,1) */
1388 static const unsigned char alt_9
[] =
1389 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1390 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1391 static const unsigned char alt_10
[] =
1392 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1393 /* data16 nopw %cs:0L(%eax,%eax,1) */
1394 static const unsigned char alt_11
[] =
1395 {0x66,0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1396 /* 32-bit and 64-bit NOPs patterns. */
1397 static const unsigned char *const alt_patt
[] = {
1398 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
1399 alt_9
, alt_10
, alt_11
1402 /* Genenerate COUNT bytes of NOPs to WHERE from PATT with the maximum
1403 size of a single NOP instruction MAX_SINGLE_NOP_SIZE. */
1406 i386_output_nops (char *where
, const unsigned char *const *patt
,
1407 int count
, int max_single_nop_size
)
1410 /* Place the longer NOP first. */
1413 const unsigned char *nops
;
1415 if (max_single_nop_size
< 1)
1417 as_fatal (_("i386_output_nops called to generate nops of at most %d bytes!"),
1418 max_single_nop_size
);
1422 nops
= patt
[max_single_nop_size
- 1];
1424 /* Use the smaller one if the requsted one isn't available. */
1427 max_single_nop_size
--;
1428 nops
= patt
[max_single_nop_size
- 1];
1431 last
= count
% max_single_nop_size
;
1434 for (offset
= 0; offset
< count
; offset
+= max_single_nop_size
)
1435 memcpy (where
+ offset
, nops
, max_single_nop_size
);
1439 nops
= patt
[last
- 1];
1442 /* Use the smaller one plus one-byte NOP if the needed one
1445 nops
= patt
[last
- 1];
1446 memcpy (where
+ offset
, nops
, last
);
1447 where
[offset
+ last
] = *patt
[0];
1450 memcpy (where
+ offset
, nops
, last
);
1455 fits_in_imm7 (offsetT num
)
1457 return (num
& 0x7f) == num
;
1461 fits_in_imm31 (offsetT num
)
1463 return (num
& 0x7fffffff) == num
;
1466 /* Genenerate COUNT bytes of NOPs to WHERE with the maximum size of a
1467 single NOP instruction LIMIT. */
1470 i386_generate_nops (fragS
*fragP
, char *where
, offsetT count
, int limit
)
1472 const unsigned char *const *patt
= NULL
;
1473 int max_single_nop_size
;
1474 /* Maximum number of NOPs before switching to jump over NOPs. */
1475 int max_number_of_nops
;
1477 switch (fragP
->fr_type
)
1482 case rs_machine_dependent
:
1483 /* Allow NOP padding for jumps and calls. */
1484 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
1485 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
)
1492 /* We need to decide which NOP sequence to use for 32bit and
1493 64bit. When -mtune= is used:
1495 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1496 PROCESSOR_GENERIC32, f32_patt will be used.
1497 2. For the rest, alt_patt will be used.
1499 When -mtune= isn't used, alt_patt will be used if
1500 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
1503 When -march= or .arch is used, we can't use anything beyond
1504 cpu_arch_isa_flags. */
1506 if (flag_code
== CODE_16BIT
)
1509 max_single_nop_size
= sizeof (f16_patt
) / sizeof (f16_patt
[0]);
1510 /* Limit number of NOPs to 2 in 16-bit mode. */
1511 max_number_of_nops
= 2;
1515 if (fragP
->tc_frag_data
.isa
== PROCESSOR_UNKNOWN
)
1517 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1518 switch (cpu_arch_tune
)
1520 case PROCESSOR_UNKNOWN
:
1521 /* We use cpu_arch_isa_flags to check if we SHOULD
1522 optimize with nops. */
1523 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1528 case PROCESSOR_PENTIUM4
:
1529 case PROCESSOR_NOCONA
:
1530 case PROCESSOR_CORE
:
1531 case PROCESSOR_CORE2
:
1532 case PROCESSOR_COREI7
:
1533 case PROCESSOR_L1OM
:
1534 case PROCESSOR_K1OM
:
1535 case PROCESSOR_GENERIC64
:
1537 case PROCESSOR_ATHLON
:
1539 case PROCESSOR_AMDFAM10
:
1541 case PROCESSOR_ZNVER
:
1545 case PROCESSOR_I386
:
1546 case PROCESSOR_I486
:
1547 case PROCESSOR_PENTIUM
:
1548 case PROCESSOR_PENTIUMPRO
:
1549 case PROCESSOR_IAMCU
:
1550 case PROCESSOR_GENERIC32
:
1557 switch (fragP
->tc_frag_data
.tune
)
1559 case PROCESSOR_UNKNOWN
:
1560 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1561 PROCESSOR_UNKNOWN. */
1565 case PROCESSOR_I386
:
1566 case PROCESSOR_I486
:
1567 case PROCESSOR_PENTIUM
:
1568 case PROCESSOR_IAMCU
:
1570 case PROCESSOR_ATHLON
:
1572 case PROCESSOR_AMDFAM10
:
1574 case PROCESSOR_ZNVER
:
1576 case PROCESSOR_GENERIC32
:
1577 /* We use cpu_arch_isa_flags to check if we CAN optimize
1579 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1584 case PROCESSOR_PENTIUMPRO
:
1585 case PROCESSOR_PENTIUM4
:
1586 case PROCESSOR_NOCONA
:
1587 case PROCESSOR_CORE
:
1588 case PROCESSOR_CORE2
:
1589 case PROCESSOR_COREI7
:
1590 case PROCESSOR_L1OM
:
1591 case PROCESSOR_K1OM
:
1592 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1597 case PROCESSOR_GENERIC64
:
1603 if (patt
== f32_patt
)
1605 max_single_nop_size
= sizeof (f32_patt
) / sizeof (f32_patt
[0]);
1606 /* Limit number of NOPs to 2 for older processors. */
1607 max_number_of_nops
= 2;
1611 max_single_nop_size
= sizeof (alt_patt
) / sizeof (alt_patt
[0]);
1612 /* Limit number of NOPs to 7 for newer processors. */
1613 max_number_of_nops
= 7;
1618 limit
= max_single_nop_size
;
1620 if (fragP
->fr_type
== rs_fill_nop
)
1622 /* Output NOPs for .nop directive. */
1623 if (limit
> max_single_nop_size
)
1625 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
1626 _("invalid single nop size: %d "
1627 "(expect within [0, %d])"),
1628 limit
, max_single_nop_size
);
1632 else if (fragP
->fr_type
!= rs_machine_dependent
)
1633 fragP
->fr_var
= count
;
1635 if ((count
/ max_single_nop_size
) > max_number_of_nops
)
1637 /* Generate jump over NOPs. */
1638 offsetT disp
= count
- 2;
1639 if (fits_in_imm7 (disp
))
1641 /* Use "jmp disp8" if possible. */
1643 where
[0] = jump_disp8
[0];
1649 unsigned int size_of_jump
;
1651 if (flag_code
== CODE_16BIT
)
1653 where
[0] = jump16_disp32
[0];
1654 where
[1] = jump16_disp32
[1];
1659 where
[0] = jump32_disp32
[0];
1663 count
-= size_of_jump
+ 4;
1664 if (!fits_in_imm31 (count
))
1666 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
1667 _("jump over nop padding out of range"));
1671 md_number_to_chars (where
+ size_of_jump
, count
, 4);
1672 where
+= size_of_jump
+ 4;
1676 /* Generate multiple NOPs. */
1677 i386_output_nops (where
, patt
, count
, limit
);
1681 operand_type_all_zero (const union i386_operand_type
*x
)
1683 switch (ARRAY_SIZE(x
->array
))
1694 return !x
->array
[0];
1701 operand_type_set (union i386_operand_type
*x
, unsigned int v
)
1703 switch (ARRAY_SIZE(x
->array
))
1719 x
->bitfield
.class = ClassNone
;
1720 x
->bitfield
.instance
= InstanceNone
;
1724 operand_type_equal (const union i386_operand_type
*x
,
1725 const union i386_operand_type
*y
)
1727 switch (ARRAY_SIZE(x
->array
))
1730 if (x
->array
[2] != y
->array
[2])
1734 if (x
->array
[1] != y
->array
[1])
1738 return x
->array
[0] == y
->array
[0];
1746 cpu_flags_all_zero (const union i386_cpu_flags
*x
)
1748 switch (ARRAY_SIZE(x
->array
))
1763 return !x
->array
[0];
1770 cpu_flags_equal (const union i386_cpu_flags
*x
,
1771 const union i386_cpu_flags
*y
)
1773 switch (ARRAY_SIZE(x
->array
))
1776 if (x
->array
[3] != y
->array
[3])
1780 if (x
->array
[2] != y
->array
[2])
1784 if (x
->array
[1] != y
->array
[1])
1788 return x
->array
[0] == y
->array
[0];
1796 cpu_flags_check_cpu64 (i386_cpu_flags f
)
1798 return !((flag_code
== CODE_64BIT
&& f
.bitfield
.cpuno64
)
1799 || (flag_code
!= CODE_64BIT
&& f
.bitfield
.cpu64
));
1802 static INLINE i386_cpu_flags
1803 cpu_flags_and (i386_cpu_flags x
, i386_cpu_flags y
)
1805 switch (ARRAY_SIZE (x
.array
))
1808 x
.array
[3] &= y
.array
[3];
1811 x
.array
[2] &= y
.array
[2];
1814 x
.array
[1] &= y
.array
[1];
1817 x
.array
[0] &= y
.array
[0];
1825 static INLINE i386_cpu_flags
1826 cpu_flags_or (i386_cpu_flags x
, i386_cpu_flags y
)
1828 switch (ARRAY_SIZE (x
.array
))
1831 x
.array
[3] |= y
.array
[3];
1834 x
.array
[2] |= y
.array
[2];
1837 x
.array
[1] |= y
.array
[1];
1840 x
.array
[0] |= y
.array
[0];
1848 static INLINE i386_cpu_flags
1849 cpu_flags_and_not (i386_cpu_flags x
, i386_cpu_flags y
)
1851 switch (ARRAY_SIZE (x
.array
))
1854 x
.array
[3] &= ~y
.array
[3];
1857 x
.array
[2] &= ~y
.array
[2];
1860 x
.array
[1] &= ~y
.array
[1];
1863 x
.array
[0] &= ~y
.array
[0];
1871 static const i386_cpu_flags avx512
= CPU_ANY_AVX512F_FLAGS
;
1873 #define CPU_FLAGS_ARCH_MATCH 0x1
1874 #define CPU_FLAGS_64BIT_MATCH 0x2
1876 #define CPU_FLAGS_PERFECT_MATCH \
1877 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_64BIT_MATCH)
1879 /* Return CPU flags match bits. */
1882 cpu_flags_match (const insn_template
*t
)
1884 i386_cpu_flags x
= t
->cpu_flags
;
1885 int match
= cpu_flags_check_cpu64 (x
) ? CPU_FLAGS_64BIT_MATCH
: 0;
1887 x
.bitfield
.cpu64
= 0;
1888 x
.bitfield
.cpuno64
= 0;
1890 if (cpu_flags_all_zero (&x
))
1892 /* This instruction is available on all archs. */
1893 match
|= CPU_FLAGS_ARCH_MATCH
;
1897 /* This instruction is available only on some archs. */
1898 i386_cpu_flags cpu
= cpu_arch_flags
;
1900 /* AVX512VL is no standalone feature - match it and then strip it. */
1901 if (x
.bitfield
.cpuavx512vl
&& !cpu
.bitfield
.cpuavx512vl
)
1903 x
.bitfield
.cpuavx512vl
= 0;
1905 cpu
= cpu_flags_and (x
, cpu
);
1906 if (!cpu_flags_all_zero (&cpu
))
1908 if (x
.bitfield
.cpuavx
)
1910 /* We need to check a few extra flags with AVX. */
1911 if (cpu
.bitfield
.cpuavx
1912 && (!t
->opcode_modifier
.sse2avx
|| sse2avx
)
1913 && (!x
.bitfield
.cpuaes
|| cpu
.bitfield
.cpuaes
)
1914 && (!x
.bitfield
.cpugfni
|| cpu
.bitfield
.cpugfni
)
1915 && (!x
.bitfield
.cpupclmul
|| cpu
.bitfield
.cpupclmul
))
1916 match
|= CPU_FLAGS_ARCH_MATCH
;
1918 else if (x
.bitfield
.cpuavx512f
)
1920 /* We need to check a few extra flags with AVX512F. */
1921 if (cpu
.bitfield
.cpuavx512f
1922 && (!x
.bitfield
.cpugfni
|| cpu
.bitfield
.cpugfni
)
1923 && (!x
.bitfield
.cpuvaes
|| cpu
.bitfield
.cpuvaes
)
1924 && (!x
.bitfield
.cpuvpclmulqdq
|| cpu
.bitfield
.cpuvpclmulqdq
))
1925 match
|= CPU_FLAGS_ARCH_MATCH
;
1928 match
|= CPU_FLAGS_ARCH_MATCH
;
1934 static INLINE i386_operand_type
1935 operand_type_and (i386_operand_type x
, i386_operand_type y
)
1937 if (x
.bitfield
.class != y
.bitfield
.class)
1938 x
.bitfield
.class = ClassNone
;
1939 if (x
.bitfield
.instance
!= y
.bitfield
.instance
)
1940 x
.bitfield
.instance
= InstanceNone
;
1942 switch (ARRAY_SIZE (x
.array
))
1945 x
.array
[2] &= y
.array
[2];
1948 x
.array
[1] &= y
.array
[1];
1951 x
.array
[0] &= y
.array
[0];
1959 static INLINE i386_operand_type
1960 operand_type_and_not (i386_operand_type x
, i386_operand_type y
)
1962 gas_assert (y
.bitfield
.class == ClassNone
);
1963 gas_assert (y
.bitfield
.instance
== InstanceNone
);
1965 switch (ARRAY_SIZE (x
.array
))
1968 x
.array
[2] &= ~y
.array
[2];
1971 x
.array
[1] &= ~y
.array
[1];
1974 x
.array
[0] &= ~y
.array
[0];
1982 static INLINE i386_operand_type
1983 operand_type_or (i386_operand_type x
, i386_operand_type y
)
1985 gas_assert (x
.bitfield
.class == ClassNone
||
1986 y
.bitfield
.class == ClassNone
||
1987 x
.bitfield
.class == y
.bitfield
.class);
1988 gas_assert (x
.bitfield
.instance
== InstanceNone
||
1989 y
.bitfield
.instance
== InstanceNone
||
1990 x
.bitfield
.instance
== y
.bitfield
.instance
);
1992 switch (ARRAY_SIZE (x
.array
))
1995 x
.array
[2] |= y
.array
[2];
1998 x
.array
[1] |= y
.array
[1];
2001 x
.array
[0] |= y
.array
[0];
2009 static INLINE i386_operand_type
2010 operand_type_xor (i386_operand_type x
, i386_operand_type y
)
2012 gas_assert (y
.bitfield
.class == ClassNone
);
2013 gas_assert (y
.bitfield
.instance
== InstanceNone
);
2015 switch (ARRAY_SIZE (x
.array
))
2018 x
.array
[2] ^= y
.array
[2];
2021 x
.array
[1] ^= y
.array
[1];
2024 x
.array
[0] ^= y
.array
[0];
2032 static const i386_operand_type disp16
= OPERAND_TYPE_DISP16
;
2033 static const i386_operand_type disp32
= OPERAND_TYPE_DISP32
;
2034 static const i386_operand_type disp32s
= OPERAND_TYPE_DISP32S
;
2035 static const i386_operand_type disp16_32
= OPERAND_TYPE_DISP16_32
;
2036 static const i386_operand_type anydisp
= OPERAND_TYPE_ANYDISP
;
2037 static const i386_operand_type anyimm
= OPERAND_TYPE_ANYIMM
;
2038 static const i386_operand_type regxmm
= OPERAND_TYPE_REGXMM
;
2039 static const i386_operand_type regmask
= OPERAND_TYPE_REGMASK
;
2040 static const i386_operand_type imm8
= OPERAND_TYPE_IMM8
;
2041 static const i386_operand_type imm8s
= OPERAND_TYPE_IMM8S
;
2042 static const i386_operand_type imm16
= OPERAND_TYPE_IMM16
;
2043 static const i386_operand_type imm32
= OPERAND_TYPE_IMM32
;
2044 static const i386_operand_type imm32s
= OPERAND_TYPE_IMM32S
;
2045 static const i386_operand_type imm64
= OPERAND_TYPE_IMM64
;
2046 static const i386_operand_type imm16_32
= OPERAND_TYPE_IMM16_32
;
2047 static const i386_operand_type imm16_32s
= OPERAND_TYPE_IMM16_32S
;
2048 static const i386_operand_type imm16_32_32s
= OPERAND_TYPE_IMM16_32_32S
;
2059 operand_type_check (i386_operand_type t
, enum operand_type c
)
2064 return t
.bitfield
.class == Reg
;
2067 return (t
.bitfield
.imm8
2071 || t
.bitfield
.imm32s
2072 || t
.bitfield
.imm64
);
2075 return (t
.bitfield
.disp8
2076 || t
.bitfield
.disp16
2077 || t
.bitfield
.disp32
2078 || t
.bitfield
.disp32s
2079 || t
.bitfield
.disp64
);
2082 return (t
.bitfield
.disp8
2083 || t
.bitfield
.disp16
2084 || t
.bitfield
.disp32
2085 || t
.bitfield
.disp32s
2086 || t
.bitfield
.disp64
2087 || t
.bitfield
.baseindex
);
2096 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit/80bit size
2097 between operand GIVEN and opeand WANTED for instruction template T. */
2100 match_operand_size (const insn_template
*t
, unsigned int wanted
,
2103 return !((i
.types
[given
].bitfield
.byte
2104 && !t
->operand_types
[wanted
].bitfield
.byte
)
2105 || (i
.types
[given
].bitfield
.word
2106 && !t
->operand_types
[wanted
].bitfield
.word
)
2107 || (i
.types
[given
].bitfield
.dword
2108 && !t
->operand_types
[wanted
].bitfield
.dword
)
2109 || (i
.types
[given
].bitfield
.qword
2110 && !t
->operand_types
[wanted
].bitfield
.qword
)
2111 || (i
.types
[given
].bitfield
.tbyte
2112 && !t
->operand_types
[wanted
].bitfield
.tbyte
));
2115 /* Return 1 if there is no conflict in SIMD register between operand
2116 GIVEN and opeand WANTED for instruction template T. */
2119 match_simd_size (const insn_template
*t
, unsigned int wanted
,
2122 return !((i
.types
[given
].bitfield
.xmmword
2123 && !t
->operand_types
[wanted
].bitfield
.xmmword
)
2124 || (i
.types
[given
].bitfield
.ymmword
2125 && !t
->operand_types
[wanted
].bitfield
.ymmword
)
2126 || (i
.types
[given
].bitfield
.zmmword
2127 && !t
->operand_types
[wanted
].bitfield
.zmmword
));
2130 /* Return 1 if there is no conflict in any size between operand GIVEN
2131 and opeand WANTED for instruction template T. */
2134 match_mem_size (const insn_template
*t
, unsigned int wanted
,
2137 return (match_operand_size (t
, wanted
, given
)
2138 && !((i
.types
[given
].bitfield
.unspecified
2140 && !t
->operand_types
[wanted
].bitfield
.unspecified
)
2141 || (i
.types
[given
].bitfield
.fword
2142 && !t
->operand_types
[wanted
].bitfield
.fword
)
2143 /* For scalar opcode templates to allow register and memory
2144 operands at the same time, some special casing is needed
2145 here. Also for v{,p}broadcast*, {,v}pmov{s,z}*, and
2146 down-conversion vpmov*. */
2147 || ((t
->operand_types
[wanted
].bitfield
.class == RegSIMD
2148 && !t
->opcode_modifier
.broadcast
2149 && (t
->operand_types
[wanted
].bitfield
.byte
2150 || t
->operand_types
[wanted
].bitfield
.word
2151 || t
->operand_types
[wanted
].bitfield
.dword
2152 || t
->operand_types
[wanted
].bitfield
.qword
))
2153 ? (i
.types
[given
].bitfield
.xmmword
2154 || i
.types
[given
].bitfield
.ymmword
2155 || i
.types
[given
].bitfield
.zmmword
)
2156 : !match_simd_size(t
, wanted
, given
))));
2159 /* Return value has MATCH_STRAIGHT set if there is no size conflict on any
2160 operands for instruction template T, and it has MATCH_REVERSE set if there
2161 is no size conflict on any operands for the template with operands reversed
2162 (and the template allows for reversing in the first place). */
2164 #define MATCH_STRAIGHT 1
2165 #define MATCH_REVERSE 2
2167 static INLINE
unsigned int
2168 operand_size_match (const insn_template
*t
)
2170 unsigned int j
, match
= MATCH_STRAIGHT
;
2172 /* Don't check non-absolute jump instructions. */
2173 if (t
->opcode_modifier
.jump
2174 && t
->opcode_modifier
.jump
!= JUMP_ABSOLUTE
)
2177 /* Check memory and accumulator operand size. */
2178 for (j
= 0; j
< i
.operands
; j
++)
2180 if (i
.types
[j
].bitfield
.class != Reg
2181 && i
.types
[j
].bitfield
.class != RegSIMD
2182 && t
->opcode_modifier
.anysize
)
2185 if (t
->operand_types
[j
].bitfield
.class == Reg
2186 && !match_operand_size (t
, j
, j
))
2192 if (t
->operand_types
[j
].bitfield
.class == RegSIMD
2193 && !match_simd_size (t
, j
, j
))
2199 if (t
->operand_types
[j
].bitfield
.instance
== Accum
2200 && (!match_operand_size (t
, j
, j
) || !match_simd_size (t
, j
, j
)))
2206 if ((i
.flags
[j
] & Operand_Mem
) && !match_mem_size (t
, j
, j
))
2213 if (!t
->opcode_modifier
.d
)
2217 i
.error
= operand_size_mismatch
;
2221 /* Check reverse. */
2222 gas_assert (i
.operands
>= 2 && i
.operands
<= 3);
2224 for (j
= 0; j
< i
.operands
; j
++)
2226 unsigned int given
= i
.operands
- j
- 1;
2228 if (t
->operand_types
[j
].bitfield
.class == Reg
2229 && !match_operand_size (t
, j
, given
))
2232 if (t
->operand_types
[j
].bitfield
.class == RegSIMD
2233 && !match_simd_size (t
, j
, given
))
2236 if (t
->operand_types
[j
].bitfield
.instance
== Accum
2237 && (!match_operand_size (t
, j
, given
)
2238 || !match_simd_size (t
, j
, given
)))
2241 if ((i
.flags
[given
] & Operand_Mem
) && !match_mem_size (t
, j
, given
))
2245 return match
| MATCH_REVERSE
;
2249 operand_type_match (i386_operand_type overlap
,
2250 i386_operand_type given
)
2252 i386_operand_type temp
= overlap
;
2254 temp
.bitfield
.unspecified
= 0;
2255 temp
.bitfield
.byte
= 0;
2256 temp
.bitfield
.word
= 0;
2257 temp
.bitfield
.dword
= 0;
2258 temp
.bitfield
.fword
= 0;
2259 temp
.bitfield
.qword
= 0;
2260 temp
.bitfield
.tbyte
= 0;
2261 temp
.bitfield
.xmmword
= 0;
2262 temp
.bitfield
.ymmword
= 0;
2263 temp
.bitfield
.zmmword
= 0;
2264 if (operand_type_all_zero (&temp
))
2267 if (given
.bitfield
.baseindex
== overlap
.bitfield
.baseindex
)
2271 i
.error
= operand_type_mismatch
;
2275 /* If given types g0 and g1 are registers they must be of the same type
2276 unless the expected operand type register overlap is null.
2277 Some Intel syntax memory operand size checking also happens here. */
2280 operand_type_register_match (i386_operand_type g0
,
2281 i386_operand_type t0
,
2282 i386_operand_type g1
,
2283 i386_operand_type t1
)
2285 if (g0
.bitfield
.class != Reg
2286 && g0
.bitfield
.class != RegSIMD
2287 && (!operand_type_check (g0
, anymem
)
2288 || g0
.bitfield
.unspecified
2289 || (t0
.bitfield
.class != Reg
2290 && t0
.bitfield
.class != RegSIMD
)))
2293 if (g1
.bitfield
.class != Reg
2294 && g1
.bitfield
.class != RegSIMD
2295 && (!operand_type_check (g1
, anymem
)
2296 || g1
.bitfield
.unspecified
2297 || (t1
.bitfield
.class != Reg
2298 && t1
.bitfield
.class != RegSIMD
)))
2301 if (g0
.bitfield
.byte
== g1
.bitfield
.byte
2302 && g0
.bitfield
.word
== g1
.bitfield
.word
2303 && g0
.bitfield
.dword
== g1
.bitfield
.dword
2304 && g0
.bitfield
.qword
== g1
.bitfield
.qword
2305 && g0
.bitfield
.xmmword
== g1
.bitfield
.xmmword
2306 && g0
.bitfield
.ymmword
== g1
.bitfield
.ymmword
2307 && g0
.bitfield
.zmmword
== g1
.bitfield
.zmmword
)
2310 if (!(t0
.bitfield
.byte
& t1
.bitfield
.byte
)
2311 && !(t0
.bitfield
.word
& t1
.bitfield
.word
)
2312 && !(t0
.bitfield
.dword
& t1
.bitfield
.dword
)
2313 && !(t0
.bitfield
.qword
& t1
.bitfield
.qword
)
2314 && !(t0
.bitfield
.xmmword
& t1
.bitfield
.xmmword
)
2315 && !(t0
.bitfield
.ymmword
& t1
.bitfield
.ymmword
)
2316 && !(t0
.bitfield
.zmmword
& t1
.bitfield
.zmmword
))
2319 i
.error
= register_type_mismatch
;
2324 static INLINE
unsigned int
2325 register_number (const reg_entry
*r
)
2327 unsigned int nr
= r
->reg_num
;
2329 if (r
->reg_flags
& RegRex
)
2332 if (r
->reg_flags
& RegVRex
)
2338 static INLINE
unsigned int
2339 mode_from_disp_size (i386_operand_type t
)
2341 if (t
.bitfield
.disp8
)
2343 else if (t
.bitfield
.disp16
2344 || t
.bitfield
.disp32
2345 || t
.bitfield
.disp32s
)
2352 fits_in_signed_byte (addressT num
)
2354 return num
+ 0x80 <= 0xff;
2358 fits_in_unsigned_byte (addressT num
)
2364 fits_in_unsigned_word (addressT num
)
2366 return num
<= 0xffff;
2370 fits_in_signed_word (addressT num
)
2372 return num
+ 0x8000 <= 0xffff;
2376 fits_in_signed_long (addressT num ATTRIBUTE_UNUSED
)
2381 return num
+ 0x80000000 <= 0xffffffff;
2383 } /* fits_in_signed_long() */
2386 fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED
)
2391 return num
<= 0xffffffff;
2393 } /* fits_in_unsigned_long() */
2396 fits_in_disp8 (offsetT num
)
2398 int shift
= i
.memshift
;
2404 mask
= (1 << shift
) - 1;
2406 /* Return 0 if NUM isn't properly aligned. */
2410 /* Check if NUM will fit in 8bit after shift. */
2411 return fits_in_signed_byte (num
>> shift
);
2415 fits_in_imm4 (offsetT num
)
2417 return (num
& 0xf) == num
;
2420 static i386_operand_type
2421 smallest_imm_type (offsetT num
)
2423 i386_operand_type t
;
2425 operand_type_set (&t
, 0);
2426 t
.bitfield
.imm64
= 1;
2428 if (cpu_arch_tune
!= PROCESSOR_I486
&& num
== 1)
2430 /* This code is disabled on the 486 because all the Imm1 forms
2431 in the opcode table are slower on the i486. They're the
2432 versions with the implicitly specified single-position
2433 displacement, which has another syntax if you really want to
2435 t
.bitfield
.imm1
= 1;
2436 t
.bitfield
.imm8
= 1;
2437 t
.bitfield
.imm8s
= 1;
2438 t
.bitfield
.imm16
= 1;
2439 t
.bitfield
.imm32
= 1;
2440 t
.bitfield
.imm32s
= 1;
2442 else if (fits_in_signed_byte (num
))
2444 t
.bitfield
.imm8
= 1;
2445 t
.bitfield
.imm8s
= 1;
2446 t
.bitfield
.imm16
= 1;
2447 t
.bitfield
.imm32
= 1;
2448 t
.bitfield
.imm32s
= 1;
2450 else if (fits_in_unsigned_byte (num
))
2452 t
.bitfield
.imm8
= 1;
2453 t
.bitfield
.imm16
= 1;
2454 t
.bitfield
.imm32
= 1;
2455 t
.bitfield
.imm32s
= 1;
2457 else if (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
2459 t
.bitfield
.imm16
= 1;
2460 t
.bitfield
.imm32
= 1;
2461 t
.bitfield
.imm32s
= 1;
2463 else if (fits_in_signed_long (num
))
2465 t
.bitfield
.imm32
= 1;
2466 t
.bitfield
.imm32s
= 1;
2468 else if (fits_in_unsigned_long (num
))
2469 t
.bitfield
.imm32
= 1;
2475 offset_in_range (offsetT val
, int size
)
2481 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
2482 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
2483 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
2485 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
2491 /* If BFD64, sign extend val for 32bit address mode. */
2492 if (flag_code
!= CODE_64BIT
2493 || i
.prefix
[ADDR_PREFIX
])
2494 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
2495 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
2498 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
2500 char buf1
[40], buf2
[40];
2502 sprint_value (buf1
, val
);
2503 sprint_value (buf2
, val
& mask
);
2504 as_warn (_("%s shortened to %s"), buf1
, buf2
);
2519 a. PREFIX_EXIST if attempting to add a prefix where one from the
2520 same class already exists.
2521 b. PREFIX_LOCK if lock prefix is added.
2522 c. PREFIX_REP if rep/repne prefix is added.
2523 d. PREFIX_DS if ds prefix is added.
2524 e. PREFIX_OTHER if other prefix is added.
2527 static enum PREFIX_GROUP
2528 add_prefix (unsigned int prefix
)
2530 enum PREFIX_GROUP ret
= PREFIX_OTHER
;
2533 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
2534 && flag_code
== CODE_64BIT
)
2536 if ((i
.prefix
[REX_PREFIX
] & prefix
& REX_W
)
2537 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_R
)
2538 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_X
)
2539 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_B
))
2550 case DS_PREFIX_OPCODE
:
2553 case CS_PREFIX_OPCODE
:
2554 case ES_PREFIX_OPCODE
:
2555 case FS_PREFIX_OPCODE
:
2556 case GS_PREFIX_OPCODE
:
2557 case SS_PREFIX_OPCODE
:
2561 case REPNE_PREFIX_OPCODE
:
2562 case REPE_PREFIX_OPCODE
:
2567 case LOCK_PREFIX_OPCODE
:
2576 case ADDR_PREFIX_OPCODE
:
2580 case DATA_PREFIX_OPCODE
:
2584 if (i
.prefix
[q
] != 0)
2592 i
.prefix
[q
] |= prefix
;
2595 as_bad (_("same type of prefix used twice"));
2601 update_code_flag (int value
, int check
)
2603 PRINTF_LIKE ((*as_error
));
2605 flag_code
= (enum flag_code
) value
;
2606 if (flag_code
== CODE_64BIT
)
2608 cpu_arch_flags
.bitfield
.cpu64
= 1;
2609 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2613 cpu_arch_flags
.bitfield
.cpu64
= 0;
2614 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2616 if (value
== CODE_64BIT
&& !cpu_arch_flags
.bitfield
.cpulm
)
2619 as_error
= as_fatal
;
2622 (*as_error
) (_("64bit mode not supported on `%s'."),
2623 cpu_arch_name
? cpu_arch_name
: default_arch
);
2625 if (value
== CODE_32BIT
&& !cpu_arch_flags
.bitfield
.cpui386
)
2628 as_error
= as_fatal
;
2631 (*as_error
) (_("32bit mode not supported on `%s'."),
2632 cpu_arch_name
? cpu_arch_name
: default_arch
);
2634 stackop_size
= '\0';
2638 set_code_flag (int value
)
2640 update_code_flag (value
, 0);
2644 set_16bit_gcc_code_flag (int new_code_flag
)
2646 flag_code
= (enum flag_code
) new_code_flag
;
2647 if (flag_code
!= CODE_16BIT
)
2649 cpu_arch_flags
.bitfield
.cpu64
= 0;
2650 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2651 stackop_size
= LONG_MNEM_SUFFIX
;
2655 set_intel_syntax (int syntax_flag
)
2657 /* Find out if register prefixing is specified. */
2658 int ask_naked_reg
= 0;
2661 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2664 int e
= get_symbol_name (&string
);
2666 if (strcmp (string
, "prefix") == 0)
2668 else if (strcmp (string
, "noprefix") == 0)
2671 as_bad (_("bad argument to syntax directive."));
2672 (void) restore_line_pointer (e
);
2674 demand_empty_rest_of_line ();
2676 intel_syntax
= syntax_flag
;
2678 if (ask_naked_reg
== 0)
2679 allow_naked_reg
= (intel_syntax
2680 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
2682 allow_naked_reg
= (ask_naked_reg
< 0);
2684 expr_set_rank (O_full_ptr
, syntax_flag
? 10 : 0);
2686 identifier_chars
['%'] = intel_syntax
&& allow_naked_reg
? '%' : 0;
2687 identifier_chars
['$'] = intel_syntax
? '$' : 0;
2688 register_prefix
= allow_naked_reg
? "" : "%";
2692 set_intel_mnemonic (int mnemonic_flag
)
2694 intel_mnemonic
= mnemonic_flag
;
2698 set_allow_index_reg (int flag
)
2700 allow_index_reg
= flag
;
2704 set_check (int what
)
2706 enum check_kind
*kind
;
2711 kind
= &operand_check
;
2722 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2725 int e
= get_symbol_name (&string
);
2727 if (strcmp (string
, "none") == 0)
2729 else if (strcmp (string
, "warning") == 0)
2730 *kind
= check_warning
;
2731 else if (strcmp (string
, "error") == 0)
2732 *kind
= check_error
;
2734 as_bad (_("bad argument to %s_check directive."), str
);
2735 (void) restore_line_pointer (e
);
2738 as_bad (_("missing argument for %s_check directive"), str
);
2740 demand_empty_rest_of_line ();
2744 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED
,
2745 i386_cpu_flags new_flag ATTRIBUTE_UNUSED
)
2747 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2748 static const char *arch
;
2750 /* Intel LIOM is only supported on ELF. */
2756 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2757 use default_arch. */
2758 arch
= cpu_arch_name
;
2760 arch
= default_arch
;
2763 /* If we are targeting Intel MCU, we must enable it. */
2764 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_IAMCU
2765 || new_flag
.bitfield
.cpuiamcu
)
2768 /* If we are targeting Intel L1OM, we must enable it. */
2769 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_L1OM
2770 || new_flag
.bitfield
.cpul1om
)
2773 /* If we are targeting Intel K1OM, we must enable it. */
2774 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_K1OM
2775 || new_flag
.bitfield
.cpuk1om
)
2778 as_bad (_("`%s' is not supported on `%s'"), name
, arch
);
2783 set_cpu_arch (int dummy ATTRIBUTE_UNUSED
)
2787 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2790 int e
= get_symbol_name (&string
);
2792 i386_cpu_flags flags
;
2794 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
2796 if (strcmp (string
, cpu_arch
[j
].name
) == 0)
2798 check_cpu_arch_compatible (string
, cpu_arch
[j
].flags
);
2802 cpu_arch_name
= cpu_arch
[j
].name
;
2803 cpu_sub_arch_name
= NULL
;
2804 cpu_arch_flags
= cpu_arch
[j
].flags
;
2805 if (flag_code
== CODE_64BIT
)
2807 cpu_arch_flags
.bitfield
.cpu64
= 1;
2808 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2812 cpu_arch_flags
.bitfield
.cpu64
= 0;
2813 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2815 cpu_arch_isa
= cpu_arch
[j
].type
;
2816 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
2817 if (!cpu_arch_tune_set
)
2819 cpu_arch_tune
= cpu_arch_isa
;
2820 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
2825 flags
= cpu_flags_or (cpu_arch_flags
,
2828 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2830 if (cpu_sub_arch_name
)
2832 char *name
= cpu_sub_arch_name
;
2833 cpu_sub_arch_name
= concat (name
,
2835 (const char *) NULL
);
2839 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
2840 cpu_arch_flags
= flags
;
2841 cpu_arch_isa_flags
= flags
;
2845 = cpu_flags_or (cpu_arch_isa_flags
,
2847 (void) restore_line_pointer (e
);
2848 demand_empty_rest_of_line ();
2853 if (*string
== '.' && j
>= ARRAY_SIZE (cpu_arch
))
2855 /* Disable an ISA extension. */
2856 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
2857 if (strcmp (string
+ 1, cpu_noarch
[j
].name
) == 0)
2859 flags
= cpu_flags_and_not (cpu_arch_flags
,
2860 cpu_noarch
[j
].flags
);
2861 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2863 if (cpu_sub_arch_name
)
2865 char *name
= cpu_sub_arch_name
;
2866 cpu_sub_arch_name
= concat (name
, string
,
2867 (const char *) NULL
);
2871 cpu_sub_arch_name
= xstrdup (string
);
2872 cpu_arch_flags
= flags
;
2873 cpu_arch_isa_flags
= flags
;
2875 (void) restore_line_pointer (e
);
2876 demand_empty_rest_of_line ();
2880 j
= ARRAY_SIZE (cpu_arch
);
2883 if (j
>= ARRAY_SIZE (cpu_arch
))
2884 as_bad (_("no such architecture: `%s'"), string
);
2886 *input_line_pointer
= e
;
2889 as_bad (_("missing cpu architecture"));
2891 no_cond_jump_promotion
= 0;
2892 if (*input_line_pointer
== ','
2893 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
2898 ++input_line_pointer
;
2899 e
= get_symbol_name (&string
);
2901 if (strcmp (string
, "nojumps") == 0)
2902 no_cond_jump_promotion
= 1;
2903 else if (strcmp (string
, "jumps") == 0)
2906 as_bad (_("no such architecture modifier: `%s'"), string
);
2908 (void) restore_line_pointer (e
);
2911 demand_empty_rest_of_line ();
2914 enum bfd_architecture
2917 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2919 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2920 || flag_code
!= CODE_64BIT
)
2921 as_fatal (_("Intel L1OM is 64bit ELF only"));
2922 return bfd_arch_l1om
;
2924 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2926 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2927 || flag_code
!= CODE_64BIT
)
2928 as_fatal (_("Intel K1OM is 64bit ELF only"));
2929 return bfd_arch_k1om
;
2931 else if (cpu_arch_isa
== PROCESSOR_IAMCU
)
2933 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2934 || flag_code
== CODE_64BIT
)
2935 as_fatal (_("Intel MCU is 32bit ELF only"));
2936 return bfd_arch_iamcu
;
2939 return bfd_arch_i386
;
2945 if (!strncmp (default_arch
, "x86_64", 6))
2947 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2949 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2950 || default_arch
[6] != '\0')
2951 as_fatal (_("Intel L1OM is 64bit ELF only"));
2952 return bfd_mach_l1om
;
2954 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2956 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2957 || default_arch
[6] != '\0')
2958 as_fatal (_("Intel K1OM is 64bit ELF only"));
2959 return bfd_mach_k1om
;
2961 else if (default_arch
[6] == '\0')
2962 return bfd_mach_x86_64
;
2964 return bfd_mach_x64_32
;
2966 else if (!strcmp (default_arch
, "i386")
2967 || !strcmp (default_arch
, "iamcu"))
2969 if (cpu_arch_isa
== PROCESSOR_IAMCU
)
2971 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
2972 as_fatal (_("Intel MCU is 32bit ELF only"));
2973 return bfd_mach_i386_iamcu
;
2976 return bfd_mach_i386_i386
;
2979 as_fatal (_("unknown architecture"));
2985 const char *hash_err
;
2987 /* Support pseudo prefixes like {disp32}. */
2988 lex_type
['{'] = LEX_BEGIN_NAME
;
2990 /* Initialize op_hash hash table. */
2991 op_hash
= hash_new ();
2994 const insn_template
*optab
;
2995 templates
*core_optab
;
2997 /* Setup for loop. */
2999 core_optab
= XNEW (templates
);
3000 core_optab
->start
= optab
;
3005 if (optab
->name
== NULL
3006 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
3008 /* different name --> ship out current template list;
3009 add to hash table; & begin anew. */
3010 core_optab
->end
= optab
;
3011 hash_err
= hash_insert (op_hash
,
3013 (void *) core_optab
);
3016 as_fatal (_("can't hash %s: %s"),
3020 if (optab
->name
== NULL
)
3022 core_optab
= XNEW (templates
);
3023 core_optab
->start
= optab
;
3028 /* Initialize reg_hash hash table. */
3029 reg_hash
= hash_new ();
3031 const reg_entry
*regtab
;
3032 unsigned int regtab_size
= i386_regtab_size
;
3034 for (regtab
= i386_regtab
; regtab_size
--; regtab
++)
3036 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (void *) regtab
);
3038 as_fatal (_("can't hash %s: %s"),
3044 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
3049 for (c
= 0; c
< 256; c
++)
3054 mnemonic_chars
[c
] = c
;
3055 register_chars
[c
] = c
;
3056 operand_chars
[c
] = c
;
3058 else if (ISLOWER (c
))
3060 mnemonic_chars
[c
] = c
;
3061 register_chars
[c
] = c
;
3062 operand_chars
[c
] = c
;
3064 else if (ISUPPER (c
))
3066 mnemonic_chars
[c
] = TOLOWER (c
);
3067 register_chars
[c
] = mnemonic_chars
[c
];
3068 operand_chars
[c
] = c
;
3070 else if (c
== '{' || c
== '}')
3072 mnemonic_chars
[c
] = c
;
3073 operand_chars
[c
] = c
;
3076 if (ISALPHA (c
) || ISDIGIT (c
))
3077 identifier_chars
[c
] = c
;
3080 identifier_chars
[c
] = c
;
3081 operand_chars
[c
] = c
;
3086 identifier_chars
['@'] = '@';
3089 identifier_chars
['?'] = '?';
3090 operand_chars
['?'] = '?';
3092 digit_chars
['-'] = '-';
3093 mnemonic_chars
['_'] = '_';
3094 mnemonic_chars
['-'] = '-';
3095 mnemonic_chars
['.'] = '.';
3096 identifier_chars
['_'] = '_';
3097 identifier_chars
['.'] = '.';
3099 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
3100 operand_chars
[(unsigned char) *p
] = *p
;
3103 if (flag_code
== CODE_64BIT
)
3105 #if defined (OBJ_COFF) && defined (TE_PE)
3106 x86_dwarf2_return_column
= (OUTPUT_FLAVOR
== bfd_target_coff_flavour
3109 x86_dwarf2_return_column
= 16;
3111 x86_cie_data_alignment
= -8;
3115 x86_dwarf2_return_column
= 8;
3116 x86_cie_data_alignment
= -4;
3119 /* NB: FUSED_JCC_PADDING frag must have sufficient room so that it
3120 can be turned into BRANCH_PREFIX frag. */
3121 if (align_branch_prefix_size
> MAX_FUSED_JCC_PADDING_SIZE
)
3126 i386_print_statistics (FILE *file
)
3128 hash_print_statistics (file
, "i386 opcode", op_hash
);
3129 hash_print_statistics (file
, "i386 register", reg_hash
);
3134 /* Debugging routines for md_assemble. */
3135 static void pte (insn_template
*);
3136 static void pt (i386_operand_type
);
3137 static void pe (expressionS
*);
3138 static void ps (symbolS
*);
3141 pi (const char *line
, i386_insn
*x
)
3145 fprintf (stdout
, "%s: template ", line
);
3147 fprintf (stdout
, " address: base %s index %s scale %x\n",
3148 x
->base_reg
? x
->base_reg
->reg_name
: "none",
3149 x
->index_reg
? x
->index_reg
->reg_name
: "none",
3150 x
->log2_scale_factor
);
3151 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
3152 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
3153 fprintf (stdout
, " sib: base %x index %x scale %x\n",
3154 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
3155 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
3156 (x
->rex
& REX_W
) != 0,
3157 (x
->rex
& REX_R
) != 0,
3158 (x
->rex
& REX_X
) != 0,
3159 (x
->rex
& REX_B
) != 0);
3160 for (j
= 0; j
< x
->operands
; j
++)
3162 fprintf (stdout
, " #%d: ", j
+ 1);
3164 fprintf (stdout
, "\n");
3165 if (x
->types
[j
].bitfield
.class == Reg
3166 || x
->types
[j
].bitfield
.class == RegMMX
3167 || x
->types
[j
].bitfield
.class == RegSIMD
3168 || x
->types
[j
].bitfield
.class == SReg
3169 || x
->types
[j
].bitfield
.class == RegCR
3170 || x
->types
[j
].bitfield
.class == RegDR
3171 || x
->types
[j
].bitfield
.class == RegTR
)
3172 fprintf (stdout
, "%s\n", x
->op
[j
].regs
->reg_name
);
3173 if (operand_type_check (x
->types
[j
], imm
))
3175 if (operand_type_check (x
->types
[j
], disp
))
3176 pe (x
->op
[j
].disps
);
3181 pte (insn_template
*t
)
3184 fprintf (stdout
, " %d operands ", t
->operands
);
3185 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
3186 if (t
->extension_opcode
!= None
)
3187 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
3188 if (t
->opcode_modifier
.d
)
3189 fprintf (stdout
, "D");
3190 if (t
->opcode_modifier
.w
)
3191 fprintf (stdout
, "W");
3192 fprintf (stdout
, "\n");
3193 for (j
= 0; j
< t
->operands
; j
++)
3195 fprintf (stdout
, " #%d type ", j
+ 1);
3196 pt (t
->operand_types
[j
]);
3197 fprintf (stdout
, "\n");
3204 fprintf (stdout
, " operation %d\n", e
->X_op
);
3205 fprintf (stdout
, " add_number %ld (%lx)\n",
3206 (long) e
->X_add_number
, (long) e
->X_add_number
);
3207 if (e
->X_add_symbol
)
3209 fprintf (stdout
, " add_symbol ");
3210 ps (e
->X_add_symbol
);
3211 fprintf (stdout
, "\n");
3215 fprintf (stdout
, " op_symbol ");
3216 ps (e
->X_op_symbol
);
3217 fprintf (stdout
, "\n");
3224 fprintf (stdout
, "%s type %s%s",
3226 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
3227 segment_name (S_GET_SEGMENT (s
)));
3230 static struct type_name
3232 i386_operand_type mask
;
3235 const type_names
[] =
3237 { OPERAND_TYPE_REG8
, "r8" },
3238 { OPERAND_TYPE_REG16
, "r16" },
3239 { OPERAND_TYPE_REG32
, "r32" },
3240 { OPERAND_TYPE_REG64
, "r64" },
3241 { OPERAND_TYPE_ACC8
, "acc8" },
3242 { OPERAND_TYPE_ACC16
, "acc16" },
3243 { OPERAND_TYPE_ACC32
, "acc32" },
3244 { OPERAND_TYPE_ACC64
, "acc64" },
3245 { OPERAND_TYPE_IMM8
, "i8" },
3246 { OPERAND_TYPE_IMM8
, "i8s" },
3247 { OPERAND_TYPE_IMM16
, "i16" },
3248 { OPERAND_TYPE_IMM32
, "i32" },
3249 { OPERAND_TYPE_IMM32S
, "i32s" },
3250 { OPERAND_TYPE_IMM64
, "i64" },
3251 { OPERAND_TYPE_IMM1
, "i1" },
3252 { OPERAND_TYPE_BASEINDEX
, "BaseIndex" },
3253 { OPERAND_TYPE_DISP8
, "d8" },
3254 { OPERAND_TYPE_DISP16
, "d16" },
3255 { OPERAND_TYPE_DISP32
, "d32" },
3256 { OPERAND_TYPE_DISP32S
, "d32s" },
3257 { OPERAND_TYPE_DISP64
, "d64" },
3258 { OPERAND_TYPE_INOUTPORTREG
, "InOutPortReg" },
3259 { OPERAND_TYPE_SHIFTCOUNT
, "ShiftCount" },
3260 { OPERAND_TYPE_CONTROL
, "control reg" },
3261 { OPERAND_TYPE_TEST
, "test reg" },
3262 { OPERAND_TYPE_DEBUG
, "debug reg" },
3263 { OPERAND_TYPE_FLOATREG
, "FReg" },
3264 { OPERAND_TYPE_FLOATACC
, "FAcc" },
3265 { OPERAND_TYPE_SREG
, "SReg" },
3266 { OPERAND_TYPE_REGMMX
, "rMMX" },
3267 { OPERAND_TYPE_REGXMM
, "rXMM" },
3268 { OPERAND_TYPE_REGYMM
, "rYMM" },
3269 { OPERAND_TYPE_REGZMM
, "rZMM" },
3270 { OPERAND_TYPE_REGMASK
, "Mask reg" },
3274 pt (i386_operand_type t
)
3277 i386_operand_type a
;
3279 for (j
= 0; j
< ARRAY_SIZE (type_names
); j
++)
3281 a
= operand_type_and (t
, type_names
[j
].mask
);
3282 if (operand_type_equal (&a
, &type_names
[j
].mask
))
3283 fprintf (stdout
, "%s, ", type_names
[j
].name
);
3288 #endif /* DEBUG386 */
3290 static bfd_reloc_code_real_type
3291 reloc (unsigned int size
,
3294 bfd_reloc_code_real_type other
)
3296 if (other
!= NO_RELOC
)
3298 reloc_howto_type
*rel
;
3303 case BFD_RELOC_X86_64_GOT32
:
3304 return BFD_RELOC_X86_64_GOT64
;
3306 case BFD_RELOC_X86_64_GOTPLT64
:
3307 return BFD_RELOC_X86_64_GOTPLT64
;
3309 case BFD_RELOC_X86_64_PLTOFF64
:
3310 return BFD_RELOC_X86_64_PLTOFF64
;
3312 case BFD_RELOC_X86_64_GOTPC32
:
3313 other
= BFD_RELOC_X86_64_GOTPC64
;
3315 case BFD_RELOC_X86_64_GOTPCREL
:
3316 other
= BFD_RELOC_X86_64_GOTPCREL64
;
3318 case BFD_RELOC_X86_64_TPOFF32
:
3319 other
= BFD_RELOC_X86_64_TPOFF64
;
3321 case BFD_RELOC_X86_64_DTPOFF32
:
3322 other
= BFD_RELOC_X86_64_DTPOFF64
;
3328 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3329 if (other
== BFD_RELOC_SIZE32
)
3332 other
= BFD_RELOC_SIZE64
;
3335 as_bad (_("there are no pc-relative size relocations"));
3341 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
3342 if (size
== 4 && (flag_code
!= CODE_64BIT
|| disallow_64bit_reloc
))
3345 rel
= bfd_reloc_type_lookup (stdoutput
, other
);
3347 as_bad (_("unknown relocation (%u)"), other
);
3348 else if (size
!= bfd_get_reloc_size (rel
))
3349 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
3350 bfd_get_reloc_size (rel
),
3352 else if (pcrel
&& !rel
->pc_relative
)
3353 as_bad (_("non-pc-relative relocation for pc-relative field"));
3354 else if ((rel
->complain_on_overflow
== complain_overflow_signed
3356 || (rel
->complain_on_overflow
== complain_overflow_unsigned
3358 as_bad (_("relocated field and relocation type differ in signedness"));
3367 as_bad (_("there are no unsigned pc-relative relocations"));
3370 case 1: return BFD_RELOC_8_PCREL
;
3371 case 2: return BFD_RELOC_16_PCREL
;
3372 case 4: return BFD_RELOC_32_PCREL
;
3373 case 8: return BFD_RELOC_64_PCREL
;
3375 as_bad (_("cannot do %u byte pc-relative relocation"), size
);
3382 case 4: return BFD_RELOC_X86_64_32S
;
3387 case 1: return BFD_RELOC_8
;
3388 case 2: return BFD_RELOC_16
;
3389 case 4: return BFD_RELOC_32
;
3390 case 8: return BFD_RELOC_64
;
3392 as_bad (_("cannot do %s %u byte relocation"),
3393 sign
> 0 ? "signed" : "unsigned", size
);
3399 /* Here we decide which fixups can be adjusted to make them relative to
3400 the beginning of the section instead of the symbol. Basically we need
3401 to make sure that the dynamic relocations are done correctly, so in
3402 some cases we force the original symbol to be used. */
3405 tc_i386_fix_adjustable (fixS
*fixP ATTRIBUTE_UNUSED
)
3407 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3411 /* Don't adjust pc-relative references to merge sections in 64-bit
3413 if (use_rela_relocations
3414 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
3418 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
3419 and changed later by validate_fix. */
3420 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
3421 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
3424 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
3425 for size relocations. */
3426 if (fixP
->fx_r_type
== BFD_RELOC_SIZE32
3427 || fixP
->fx_r_type
== BFD_RELOC_SIZE64
3428 || fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
3429 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
3430 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32X
3431 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
3432 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
3433 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
3434 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
3435 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
3436 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
3437 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
3438 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
3439 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTDESC
3440 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_DESC_CALL
3441 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
3442 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
3443 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCRELX
3444 || fixP
->fx_r_type
== BFD_RELOC_X86_64_REX_GOTPCRELX
3445 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
3446 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
3447 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
3448 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
3449 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
3450 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
3451 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
3452 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
3453 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPC32_TLSDESC
3454 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSDESC_CALL
3455 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
3456 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
3463 intel_float_operand (const char *mnemonic
)
3465 /* Note that the value returned is meaningful only for opcodes with (memory)
3466 operands, hence the code here is free to improperly handle opcodes that
3467 have no operands (for better performance and smaller code). */
3469 if (mnemonic
[0] != 'f')
3470 return 0; /* non-math */
3472 switch (mnemonic
[1])
3474 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
3475 the fs segment override prefix not currently handled because no
3476 call path can make opcodes without operands get here */
3478 return 2 /* integer op */;
3480 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
3481 return 3; /* fldcw/fldenv */
3484 if (mnemonic
[2] != 'o' /* fnop */)
3485 return 3; /* non-waiting control op */
3488 if (mnemonic
[2] == 's')
3489 return 3; /* frstor/frstpm */
3492 if (mnemonic
[2] == 'a')
3493 return 3; /* fsave */
3494 if (mnemonic
[2] == 't')
3496 switch (mnemonic
[3])
3498 case 'c': /* fstcw */
3499 case 'd': /* fstdw */
3500 case 'e': /* fstenv */
3501 case 's': /* fsts[gw] */
3507 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
3508 return 0; /* fxsave/fxrstor are not really math ops */
3515 /* Build the VEX prefix. */
3518 build_vex_prefix (const insn_template
*t
)
3520 unsigned int register_specifier
;
3521 unsigned int implied_prefix
;
3522 unsigned int vector_length
;
3525 /* Check register specifier. */
3526 if (i
.vex
.register_specifier
)
3528 register_specifier
=
3529 ~register_number (i
.vex
.register_specifier
) & 0xf;
3530 gas_assert ((i
.vex
.register_specifier
->reg_flags
& RegVRex
) == 0);
3533 register_specifier
= 0xf;
3535 /* Use 2-byte VEX prefix by swapping destination and source operand
3536 if there are more than 1 register operand. */
3537 if (i
.reg_operands
> 1
3538 && i
.vec_encoding
!= vex_encoding_vex3
3539 && i
.dir_encoding
== dir_encoding_default
3540 && i
.operands
== i
.reg_operands
3541 && operand_type_equal (&i
.types
[0], &i
.types
[i
.operands
- 1])
3542 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3543 && (i
.tm
.opcode_modifier
.load
|| i
.tm
.opcode_modifier
.d
)
3546 unsigned int xchg
= i
.operands
- 1;
3547 union i386_op temp_op
;
3548 i386_operand_type temp_type
;
3550 temp_type
= i
.types
[xchg
];
3551 i
.types
[xchg
] = i
.types
[0];
3552 i
.types
[0] = temp_type
;
3553 temp_op
= i
.op
[xchg
];
3554 i
.op
[xchg
] = i
.op
[0];
3557 gas_assert (i
.rm
.mode
== 3);
3561 i
.rm
.regmem
= i
.rm
.reg
;
3564 if (i
.tm
.opcode_modifier
.d
)
3565 i
.tm
.base_opcode
^= (i
.tm
.base_opcode
& 0xee) != 0x6e
3566 ? Opcode_SIMD_FloatD
: Opcode_SIMD_IntD
;
3567 else /* Use the next insn. */
3571 /* Use 2-byte VEX prefix by swapping commutative source operands if there
3572 are no memory operands and at least 3 register ones. */
3573 if (i
.reg_operands
>= 3
3574 && i
.vec_encoding
!= vex_encoding_vex3
3575 && i
.reg_operands
== i
.operands
- i
.imm_operands
3576 && i
.tm
.opcode_modifier
.vex
3577 && i
.tm
.opcode_modifier
.commutative
3578 && (i
.tm
.opcode_modifier
.sse2avx
|| optimize
> 1)
3580 && i
.vex
.register_specifier
3581 && !(i
.vex
.register_specifier
->reg_flags
& RegRex
))
3583 unsigned int xchg
= i
.operands
- i
.reg_operands
;
3584 union i386_op temp_op
;
3585 i386_operand_type temp_type
;
3587 gas_assert (i
.tm
.opcode_modifier
.vexopcode
== VEX0F
);
3588 gas_assert (!i
.tm
.opcode_modifier
.sae
);
3589 gas_assert (operand_type_equal (&i
.types
[i
.operands
- 2],
3590 &i
.types
[i
.operands
- 3]));
3591 gas_assert (i
.rm
.mode
== 3);
3593 temp_type
= i
.types
[xchg
];
3594 i
.types
[xchg
] = i
.types
[xchg
+ 1];
3595 i
.types
[xchg
+ 1] = temp_type
;
3596 temp_op
= i
.op
[xchg
];
3597 i
.op
[xchg
] = i
.op
[xchg
+ 1];
3598 i
.op
[xchg
+ 1] = temp_op
;
3601 xchg
= i
.rm
.regmem
| 8;
3602 i
.rm
.regmem
= ~register_specifier
& 0xf;
3603 gas_assert (!(i
.rm
.regmem
& 8));
3604 i
.vex
.register_specifier
+= xchg
- i
.rm
.regmem
;
3605 register_specifier
= ~xchg
& 0xf;
3608 if (i
.tm
.opcode_modifier
.vex
== VEXScalar
)
3609 vector_length
= avxscalar
;
3610 else if (i
.tm
.opcode_modifier
.vex
== VEX256
)
3616 /* Determine vector length from the last multi-length vector
3619 for (op
= t
->operands
; op
--;)
3620 if (t
->operand_types
[op
].bitfield
.xmmword
3621 && t
->operand_types
[op
].bitfield
.ymmword
3622 && i
.types
[op
].bitfield
.ymmword
)
3629 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3634 case DATA_PREFIX_OPCODE
:
3637 case REPE_PREFIX_OPCODE
:
3640 case REPNE_PREFIX_OPCODE
:
3647 /* Check the REX.W bit and VEXW. */
3648 if (i
.tm
.opcode_modifier
.vexw
== VEXWIG
)
3649 w
= (vexwig
== vexw1
|| (i
.rex
& REX_W
)) ? 1 : 0;
3650 else if (i
.tm
.opcode_modifier
.vexw
)
3651 w
= i
.tm
.opcode_modifier
.vexw
== VEXW1
? 1 : 0;
3653 w
= (flag_code
== CODE_64BIT
? i
.rex
& REX_W
: vexwig
== vexw1
) ? 1 : 0;
3655 /* Use 2-byte VEX prefix if possible. */
3657 && i
.vec_encoding
!= vex_encoding_vex3
3658 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3659 && (i
.rex
& (REX_W
| REX_X
| REX_B
)) == 0)
3661 /* 2-byte VEX prefix. */
3665 i
.vex
.bytes
[0] = 0xc5;
3667 /* Check the REX.R bit. */
3668 r
= (i
.rex
& REX_R
) ? 0 : 1;
3669 i
.vex
.bytes
[1] = (r
<< 7
3670 | register_specifier
<< 3
3671 | vector_length
<< 2
3676 /* 3-byte VEX prefix. */
3681 switch (i
.tm
.opcode_modifier
.vexopcode
)
3685 i
.vex
.bytes
[0] = 0xc4;
3689 i
.vex
.bytes
[0] = 0xc4;
3693 i
.vex
.bytes
[0] = 0xc4;
3697 i
.vex
.bytes
[0] = 0x8f;
3701 i
.vex
.bytes
[0] = 0x8f;
3705 i
.vex
.bytes
[0] = 0x8f;
3711 /* The high 3 bits of the second VEX byte are 1's compliment
3712 of RXB bits from REX. */
3713 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3715 i
.vex
.bytes
[2] = (w
<< 7
3716 | register_specifier
<< 3
3717 | vector_length
<< 2
3722 static INLINE bfd_boolean
3723 is_evex_encoding (const insn_template
*t
)
3725 return t
->opcode_modifier
.evex
|| t
->opcode_modifier
.disp8memshift
3726 || t
->opcode_modifier
.broadcast
|| t
->opcode_modifier
.masking
3727 || t
->opcode_modifier
.sae
;
3730 static INLINE bfd_boolean
3731 is_any_vex_encoding (const insn_template
*t
)
3733 return t
->opcode_modifier
.vex
|| t
->opcode_modifier
.vexopcode
3734 || is_evex_encoding (t
);
3737 /* Build the EVEX prefix. */
3740 build_evex_prefix (void)
3742 unsigned int register_specifier
;
3743 unsigned int implied_prefix
;
3745 rex_byte vrex_used
= 0;
3747 /* Check register specifier. */
3748 if (i
.vex
.register_specifier
)
3750 gas_assert ((i
.vrex
& REX_X
) == 0);
3752 register_specifier
= i
.vex
.register_specifier
->reg_num
;
3753 if ((i
.vex
.register_specifier
->reg_flags
& RegRex
))
3754 register_specifier
+= 8;
3755 /* The upper 16 registers are encoded in the fourth byte of the
3757 if (!(i
.vex
.register_specifier
->reg_flags
& RegVRex
))
3758 i
.vex
.bytes
[3] = 0x8;
3759 register_specifier
= ~register_specifier
& 0xf;
3763 register_specifier
= 0xf;
3765 /* Encode upper 16 vector index register in the fourth byte of
3767 if (!(i
.vrex
& REX_X
))
3768 i
.vex
.bytes
[3] = 0x8;
3773 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3778 case DATA_PREFIX_OPCODE
:
3781 case REPE_PREFIX_OPCODE
:
3784 case REPNE_PREFIX_OPCODE
:
3791 /* 4 byte EVEX prefix. */
3793 i
.vex
.bytes
[0] = 0x62;
3796 switch (i
.tm
.opcode_modifier
.vexopcode
)
3812 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3814 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3816 /* The fifth bit of the second EVEX byte is 1's compliment of the
3817 REX_R bit in VREX. */
3818 if (!(i
.vrex
& REX_R
))
3819 i
.vex
.bytes
[1] |= 0x10;
3823 if ((i
.reg_operands
+ i
.imm_operands
) == i
.operands
)
3825 /* When all operands are registers, the REX_X bit in REX is not
3826 used. We reuse it to encode the upper 16 registers, which is
3827 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3828 as 1's compliment. */
3829 if ((i
.vrex
& REX_B
))
3832 i
.vex
.bytes
[1] &= ~0x40;
3836 /* EVEX instructions shouldn't need the REX prefix. */
3837 i
.vrex
&= ~vrex_used
;
3838 gas_assert (i
.vrex
== 0);
3840 /* Check the REX.W bit and VEXW. */
3841 if (i
.tm
.opcode_modifier
.vexw
== VEXWIG
)
3842 w
= (evexwig
== evexw1
|| (i
.rex
& REX_W
)) ? 1 : 0;
3843 else if (i
.tm
.opcode_modifier
.vexw
)
3844 w
= i
.tm
.opcode_modifier
.vexw
== VEXW1
? 1 : 0;
3846 w
= (flag_code
== CODE_64BIT
? i
.rex
& REX_W
: evexwig
== evexw1
) ? 1 : 0;
3848 /* Encode the U bit. */
3849 implied_prefix
|= 0x4;
3851 /* The third byte of the EVEX prefix. */
3852 i
.vex
.bytes
[2] = (w
<< 7 | register_specifier
<< 3 | implied_prefix
);
3854 /* The fourth byte of the EVEX prefix. */
3855 /* The zeroing-masking bit. */
3856 if (i
.mask
&& i
.mask
->zeroing
)
3857 i
.vex
.bytes
[3] |= 0x80;
3859 /* Don't always set the broadcast bit if there is no RC. */
3862 /* Encode the vector length. */
3863 unsigned int vec_length
;
3865 if (!i
.tm
.opcode_modifier
.evex
3866 || i
.tm
.opcode_modifier
.evex
== EVEXDYN
)
3870 /* Determine vector length from the last multi-length vector
3873 for (op
= i
.operands
; op
--;)
3874 if (i
.tm
.operand_types
[op
].bitfield
.xmmword
3875 + i
.tm
.operand_types
[op
].bitfield
.ymmword
3876 + i
.tm
.operand_types
[op
].bitfield
.zmmword
> 1)
3878 if (i
.types
[op
].bitfield
.zmmword
)
3880 i
.tm
.opcode_modifier
.evex
= EVEX512
;
3883 else if (i
.types
[op
].bitfield
.ymmword
)
3885 i
.tm
.opcode_modifier
.evex
= EVEX256
;
3888 else if (i
.types
[op
].bitfield
.xmmword
)
3890 i
.tm
.opcode_modifier
.evex
= EVEX128
;
3893 else if (i
.broadcast
&& (int) op
== i
.broadcast
->operand
)
3895 switch (i
.broadcast
->bytes
)
3898 i
.tm
.opcode_modifier
.evex
= EVEX512
;
3901 i
.tm
.opcode_modifier
.evex
= EVEX256
;
3904 i
.tm
.opcode_modifier
.evex
= EVEX128
;
3913 if (op
>= MAX_OPERANDS
)
3917 switch (i
.tm
.opcode_modifier
.evex
)
3919 case EVEXLIG
: /* LL' is ignored */
3920 vec_length
= evexlig
<< 5;
3923 vec_length
= 0 << 5;
3926 vec_length
= 1 << 5;
3929 vec_length
= 2 << 5;
3935 i
.vex
.bytes
[3] |= vec_length
;
3936 /* Encode the broadcast bit. */
3938 i
.vex
.bytes
[3] |= 0x10;
3942 if (i
.rounding
->type
!= saeonly
)
3943 i
.vex
.bytes
[3] |= 0x10 | (i
.rounding
->type
<< 5);
3945 i
.vex
.bytes
[3] |= 0x10 | (evexrcig
<< 5);
3948 if (i
.mask
&& i
.mask
->mask
)
3949 i
.vex
.bytes
[3] |= i
.mask
->mask
->reg_num
;
3953 process_immext (void)
3957 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
3958 which is coded in the same place as an 8-bit immediate field
3959 would be. Here we fake an 8-bit immediate operand from the
3960 opcode suffix stored in tm.extension_opcode.
3962 AVX instructions also use this encoding, for some of
3963 3 argument instructions. */
3965 gas_assert (i
.imm_operands
<= 1
3967 || (is_any_vex_encoding (&i
.tm
)
3968 && i
.operands
<= 4)));
3970 exp
= &im_expressions
[i
.imm_operands
++];
3971 i
.op
[i
.operands
].imms
= exp
;
3972 i
.types
[i
.operands
] = imm8
;
3974 exp
->X_op
= O_constant
;
3975 exp
->X_add_number
= i
.tm
.extension_opcode
;
3976 i
.tm
.extension_opcode
= None
;
3983 switch (i
.tm
.opcode_modifier
.hleprefixok
)
3988 as_bad (_("invalid instruction `%s' after `%s'"),
3989 i
.tm
.name
, i
.hle_prefix
);
3992 if (i
.prefix
[LOCK_PREFIX
])
3994 as_bad (_("missing `lock' with `%s'"), i
.hle_prefix
);
3998 case HLEPrefixRelease
:
3999 if (i
.prefix
[HLE_PREFIX
] != XRELEASE_PREFIX_OPCODE
)
4001 as_bad (_("instruction `%s' after `xacquire' not allowed"),
4005 if (i
.mem_operands
== 0 || !(i
.flags
[i
.operands
- 1] & Operand_Mem
))
4007 as_bad (_("memory destination needed for instruction `%s'"
4008 " after `xrelease'"), i
.tm
.name
);
4015 /* Try the shortest encoding by shortening operand size. */
4018 optimize_encoding (void)
4022 if (optimize_for_space
4023 && !is_any_vex_encoding (&i
.tm
)
4024 && i
.reg_operands
== 1
4025 && i
.imm_operands
== 1
4026 && !i
.types
[1].bitfield
.byte
4027 && i
.op
[0].imms
->X_op
== O_constant
4028 && fits_in_imm7 (i
.op
[0].imms
->X_add_number
)
4029 && (i
.tm
.base_opcode
== 0xa8
4030 || (i
.tm
.base_opcode
== 0xf6
4031 && i
.tm
.extension_opcode
== 0x0)))
4034 test $imm7, %r64/%r32/%r16 -> test $imm7, %r8
4036 unsigned int base_regnum
= i
.op
[1].regs
->reg_num
;
4037 if (flag_code
== CODE_64BIT
|| base_regnum
< 4)
4039 i
.types
[1].bitfield
.byte
= 1;
4040 /* Ignore the suffix. */
4042 /* Convert to byte registers. */
4043 if (i
.types
[1].bitfield
.word
)
4045 else if (i
.types
[1].bitfield
.dword
)
4049 if (!(i
.op
[1].regs
->reg_flags
& RegRex
) && base_regnum
< 4)
4054 else if (flag_code
== CODE_64BIT
4055 && !is_any_vex_encoding (&i
.tm
)
4056 && ((i
.types
[1].bitfield
.qword
4057 && i
.reg_operands
== 1
4058 && i
.imm_operands
== 1
4059 && i
.op
[0].imms
->X_op
== O_constant
4060 && ((i
.tm
.base_opcode
== 0xb8
4061 && i
.tm
.extension_opcode
== None
4062 && fits_in_unsigned_long (i
.op
[0].imms
->X_add_number
))
4063 || (fits_in_imm31 (i
.op
[0].imms
->X_add_number
)
4064 && ((i
.tm
.base_opcode
== 0x24
4065 || i
.tm
.base_opcode
== 0xa8)
4066 || (i
.tm
.base_opcode
== 0x80
4067 && i
.tm
.extension_opcode
== 0x4)
4068 || ((i
.tm
.base_opcode
== 0xf6
4069 || (i
.tm
.base_opcode
| 1) == 0xc7)
4070 && i
.tm
.extension_opcode
== 0x0)))
4071 || (fits_in_imm7 (i
.op
[0].imms
->X_add_number
)
4072 && i
.tm
.base_opcode
== 0x83
4073 && i
.tm
.extension_opcode
== 0x4)))
4074 || (i
.types
[0].bitfield
.qword
4075 && ((i
.reg_operands
== 2
4076 && i
.op
[0].regs
== i
.op
[1].regs
4077 && (i
.tm
.base_opcode
== 0x30
4078 || i
.tm
.base_opcode
== 0x28))
4079 || (i
.reg_operands
== 1
4081 && i
.tm
.base_opcode
== 0x30)))))
4084 andq $imm31, %r64 -> andl $imm31, %r32
4085 andq $imm7, %r64 -> andl $imm7, %r32
4086 testq $imm31, %r64 -> testl $imm31, %r32
4087 xorq %r64, %r64 -> xorl %r32, %r32
4088 subq %r64, %r64 -> subl %r32, %r32
4089 movq $imm31, %r64 -> movl $imm31, %r32
4090 movq $imm32, %r64 -> movl $imm32, %r32
4092 i
.tm
.opcode_modifier
.norex64
= 1;
4093 if (i
.tm
.base_opcode
== 0xb8 || (i
.tm
.base_opcode
| 1) == 0xc7)
4096 movq $imm31, %r64 -> movl $imm31, %r32
4097 movq $imm32, %r64 -> movl $imm32, %r32
4099 i
.tm
.operand_types
[0].bitfield
.imm32
= 1;
4100 i
.tm
.operand_types
[0].bitfield
.imm32s
= 0;
4101 i
.tm
.operand_types
[0].bitfield
.imm64
= 0;
4102 i
.types
[0].bitfield
.imm32
= 1;
4103 i
.types
[0].bitfield
.imm32s
= 0;
4104 i
.types
[0].bitfield
.imm64
= 0;
4105 i
.types
[1].bitfield
.dword
= 1;
4106 i
.types
[1].bitfield
.qword
= 0;
4107 if ((i
.tm
.base_opcode
| 1) == 0xc7)
4110 movq $imm31, %r64 -> movl $imm31, %r32
4112 i
.tm
.base_opcode
= 0xb8;
4113 i
.tm
.extension_opcode
= None
;
4114 i
.tm
.opcode_modifier
.w
= 0;
4115 i
.tm
.opcode_modifier
.modrm
= 0;
4119 else if (optimize
> 1
4120 && !optimize_for_space
4121 && !is_any_vex_encoding (&i
.tm
)
4122 && i
.reg_operands
== 2
4123 && i
.op
[0].regs
== i
.op
[1].regs
4124 && ((i
.tm
.base_opcode
& ~(Opcode_D
| 1)) == 0x8
4125 || (i
.tm
.base_opcode
& ~(Opcode_D
| 1)) == 0x20)
4126 && (flag_code
!= CODE_64BIT
|| !i
.types
[0].bitfield
.dword
))
4129 andb %rN, %rN -> testb %rN, %rN
4130 andw %rN, %rN -> testw %rN, %rN
4131 andq %rN, %rN -> testq %rN, %rN
4132 orb %rN, %rN -> testb %rN, %rN
4133 orw %rN, %rN -> testw %rN, %rN
4134 orq %rN, %rN -> testq %rN, %rN
4136 and outside of 64-bit mode
4138 andl %rN, %rN -> testl %rN, %rN
4139 orl %rN, %rN -> testl %rN, %rN
4141 i
.tm
.base_opcode
= 0x84 | (i
.tm
.base_opcode
& 1);
4143 else if (i
.reg_operands
== 3
4144 && i
.op
[0].regs
== i
.op
[1].regs
4145 && !i
.types
[2].bitfield
.xmmword
4146 && (i
.tm
.opcode_modifier
.vex
4147 || ((!i
.mask
|| i
.mask
->zeroing
)
4149 && is_evex_encoding (&i
.tm
)
4150 && (i
.vec_encoding
!= vex_encoding_evex
4151 || cpu_arch_isa_flags
.bitfield
.cpuavx512vl
4152 || i
.tm
.cpu_flags
.bitfield
.cpuavx512vl
4153 || (i
.tm
.operand_types
[2].bitfield
.zmmword
4154 && i
.types
[2].bitfield
.ymmword
))))
4155 && ((i
.tm
.base_opcode
== 0x55
4156 || i
.tm
.base_opcode
== 0x6655
4157 || i
.tm
.base_opcode
== 0x66df
4158 || i
.tm
.base_opcode
== 0x57
4159 || i
.tm
.base_opcode
== 0x6657
4160 || i
.tm
.base_opcode
== 0x66ef
4161 || i
.tm
.base_opcode
== 0x66f8
4162 || i
.tm
.base_opcode
== 0x66f9
4163 || i
.tm
.base_opcode
== 0x66fa
4164 || i
.tm
.base_opcode
== 0x66fb
4165 || i
.tm
.base_opcode
== 0x42
4166 || i
.tm
.base_opcode
== 0x6642
4167 || i
.tm
.base_opcode
== 0x47
4168 || i
.tm
.base_opcode
== 0x6647)
4169 && i
.tm
.extension_opcode
== None
))
4172 VOP, one of vandnps, vandnpd, vxorps, vxorpd, vpsubb, vpsubd,
4174 EVEX VOP %zmmM, %zmmM, %zmmN
4175 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
4176 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4177 EVEX VOP %ymmM, %ymmM, %ymmN
4178 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
4179 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4180 VEX VOP %ymmM, %ymmM, %ymmN
4181 -> VEX VOP %xmmM, %xmmM, %xmmN
4182 VOP, one of vpandn and vpxor:
4183 VEX VOP %ymmM, %ymmM, %ymmN
4184 -> VEX VOP %xmmM, %xmmM, %xmmN
4185 VOP, one of vpandnd and vpandnq:
4186 EVEX VOP %zmmM, %zmmM, %zmmN
4187 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
4188 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4189 EVEX VOP %ymmM, %ymmM, %ymmN
4190 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
4191 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4192 VOP, one of vpxord and vpxorq:
4193 EVEX VOP %zmmM, %zmmM, %zmmN
4194 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
4195 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4196 EVEX VOP %ymmM, %ymmM, %ymmN
4197 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
4198 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4199 VOP, one of kxord and kxorq:
4200 VEX VOP %kM, %kM, %kN
4201 -> VEX kxorw %kM, %kM, %kN
4202 VOP, one of kandnd and kandnq:
4203 VEX VOP %kM, %kM, %kN
4204 -> VEX kandnw %kM, %kM, %kN
4206 if (is_evex_encoding (&i
.tm
))
4208 if (i
.vec_encoding
!= vex_encoding_evex
)
4210 i
.tm
.opcode_modifier
.vex
= VEX128
;
4211 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4212 i
.tm
.opcode_modifier
.evex
= 0;
4214 else if (optimize
> 1)
4215 i
.tm
.opcode_modifier
.evex
= EVEX128
;
4219 else if (i
.tm
.operand_types
[0].bitfield
.class == RegMask
)
4221 i
.tm
.base_opcode
&= 0xff;
4222 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4225 i
.tm
.opcode_modifier
.vex
= VEX128
;
4227 if (i
.tm
.opcode_modifier
.vex
)
4228 for (j
= 0; j
< 3; j
++)
4230 i
.types
[j
].bitfield
.xmmword
= 1;
4231 i
.types
[j
].bitfield
.ymmword
= 0;
4234 else if (i
.vec_encoding
!= vex_encoding_evex
4235 && !i
.types
[0].bitfield
.zmmword
4236 && !i
.types
[1].bitfield
.zmmword
4239 && is_evex_encoding (&i
.tm
)
4240 && ((i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0x666f
4241 || (i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0xf36f
4242 || (i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0xf26f
4243 || (i
.tm
.base_opcode
& ~4) == 0x66db
4244 || (i
.tm
.base_opcode
& ~4) == 0x66eb)
4245 && i
.tm
.extension_opcode
== None
)
4248 VOP, one of vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16,
4249 vmovdqu32 and vmovdqu64:
4250 EVEX VOP %xmmM, %xmmN
4251 -> VEX vmovdqa|vmovdqu %xmmM, %xmmN (M and N < 16)
4252 EVEX VOP %ymmM, %ymmN
4253 -> VEX vmovdqa|vmovdqu %ymmM, %ymmN (M and N < 16)
4255 -> VEX vmovdqa|vmovdqu %xmmM, mem (M < 16)
4257 -> VEX vmovdqa|vmovdqu %ymmM, mem (M < 16)
4259 -> VEX mvmovdqa|vmovdquem, %xmmN (N < 16)
4261 -> VEX vmovdqa|vmovdqu mem, %ymmN (N < 16)
4262 VOP, one of vpand, vpandn, vpor, vpxor:
4263 EVEX VOP{d,q} %xmmL, %xmmM, %xmmN
4264 -> VEX VOP %xmmL, %xmmM, %xmmN (L, M, and N < 16)
4265 EVEX VOP{d,q} %ymmL, %ymmM, %ymmN
4266 -> VEX VOP %ymmL, %ymmM, %ymmN (L, M, and N < 16)
4267 EVEX VOP{d,q} mem, %xmmM, %xmmN
4268 -> VEX VOP mem, %xmmM, %xmmN (M and N < 16)
4269 EVEX VOP{d,q} mem, %ymmM, %ymmN
4270 -> VEX VOP mem, %ymmM, %ymmN (M and N < 16)
4272 for (j
= 0; j
< i
.operands
; j
++)
4273 if (operand_type_check (i
.types
[j
], disp
)
4274 && i
.op
[j
].disps
->X_op
== O_constant
)
4276 /* Since the VEX prefix has 2 or 3 bytes, the EVEX prefix
4277 has 4 bytes, EVEX Disp8 has 1 byte and VEX Disp32 has 4
4278 bytes, we choose EVEX Disp8 over VEX Disp32. */
4279 int evex_disp8
, vex_disp8
;
4280 unsigned int memshift
= i
.memshift
;
4281 offsetT n
= i
.op
[j
].disps
->X_add_number
;
4283 evex_disp8
= fits_in_disp8 (n
);
4285 vex_disp8
= fits_in_disp8 (n
);
4286 if (evex_disp8
!= vex_disp8
)
4288 i
.memshift
= memshift
;
4292 i
.types
[j
].bitfield
.disp8
= vex_disp8
;
4295 if ((i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0xf26f)
4296 i
.tm
.base_opcode
^= 0xf36f ^ 0xf26f;
4297 i
.tm
.opcode_modifier
.vex
4298 = i
.types
[0].bitfield
.ymmword
? VEX256
: VEX128
;
4299 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4300 /* VPAND, VPOR, and VPXOR are commutative. */
4301 if (i
.reg_operands
== 3 && i
.tm
.base_opcode
!= 0x66df)
4302 i
.tm
.opcode_modifier
.commutative
= 1;
4303 i
.tm
.opcode_modifier
.evex
= 0;
4304 i
.tm
.opcode_modifier
.masking
= 0;
4305 i
.tm
.opcode_modifier
.broadcast
= 0;
4306 i
.tm
.opcode_modifier
.disp8memshift
= 0;
4309 i
.types
[j
].bitfield
.disp8
4310 = fits_in_disp8 (i
.op
[j
].disps
->X_add_number
);
4314 /* This is the guts of the machine-dependent assembler. LINE points to a
4315 machine dependent instruction. This function is supposed to emit
4316 the frags/bytes it assembles to. */
4319 md_assemble (char *line
)
4322 char mnemonic
[MAX_MNEM_SIZE
], mnem_suffix
;
4323 const insn_template
*t
;
4325 /* Initialize globals. */
4326 memset (&i
, '\0', sizeof (i
));
4327 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4328 i
.reloc
[j
] = NO_RELOC
;
4329 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
4330 memset (im_expressions
, '\0', sizeof (im_expressions
));
4331 save_stack_p
= save_stack
;
4333 /* First parse an instruction mnemonic & call i386_operand for the operands.
4334 We assume that the scrubber has arranged it so that line[0] is the valid
4335 start of a (possibly prefixed) mnemonic. */
4337 line
= parse_insn (line
, mnemonic
);
4340 mnem_suffix
= i
.suffix
;
4342 line
= parse_operands (line
, mnemonic
);
4344 xfree (i
.memop1_string
);
4345 i
.memop1_string
= NULL
;
4349 /* Now we've parsed the mnemonic into a set of templates, and have the
4350 operands at hand. */
4352 /* All Intel opcodes have reversed operands except for "bound", "enter",
4353 "monitor*", "mwait*", "tpause", and "umwait". We also don't reverse
4354 intersegment "jmp" and "call" instructions with 2 immediate operands so
4355 that the immediate segment precedes the offset, as it does when in AT&T
4359 && (strcmp (mnemonic
, "bound") != 0)
4360 && (strcmp (mnemonic
, "invlpga") != 0)
4361 && (strncmp (mnemonic
, "monitor", 7) != 0)
4362 && (strncmp (mnemonic
, "mwait", 5) != 0)
4363 && (strcmp (mnemonic
, "tpause") != 0)
4364 && (strcmp (mnemonic
, "umwait") != 0)
4365 && !(operand_type_check (i
.types
[0], imm
)
4366 && operand_type_check (i
.types
[1], imm
)))
4369 /* The order of the immediates should be reversed
4370 for 2 immediates extrq and insertq instructions */
4371 if (i
.imm_operands
== 2
4372 && (strcmp (mnemonic
, "extrq") == 0
4373 || strcmp (mnemonic
, "insertq") == 0))
4374 swap_2_operands (0, 1);
4379 /* Don't optimize displacement for movabs since it only takes 64bit
4382 && i
.disp_encoding
!= disp_encoding_32bit
4383 && (flag_code
!= CODE_64BIT
4384 || strcmp (mnemonic
, "movabs") != 0))
4387 /* Next, we find a template that matches the given insn,
4388 making sure the overlap of the given operands types is consistent
4389 with the template operand types. */
4391 if (!(t
= match_template (mnem_suffix
)))
4394 if (sse_check
!= check_none
4395 && !i
.tm
.opcode_modifier
.noavx
4396 && !i
.tm
.cpu_flags
.bitfield
.cpuavx
4397 && !i
.tm
.cpu_flags
.bitfield
.cpuavx512f
4398 && (i
.tm
.cpu_flags
.bitfield
.cpusse
4399 || i
.tm
.cpu_flags
.bitfield
.cpusse2
4400 || i
.tm
.cpu_flags
.bitfield
.cpusse3
4401 || i
.tm
.cpu_flags
.bitfield
.cpussse3
4402 || i
.tm
.cpu_flags
.bitfield
.cpusse4_1
4403 || i
.tm
.cpu_flags
.bitfield
.cpusse4_2
4404 || i
.tm
.cpu_flags
.bitfield
.cpusse4a
4405 || i
.tm
.cpu_flags
.bitfield
.cpupclmul
4406 || i
.tm
.cpu_flags
.bitfield
.cpuaes
4407 || i
.tm
.cpu_flags
.bitfield
.cpusha
4408 || i
.tm
.cpu_flags
.bitfield
.cpugfni
))
4410 (sse_check
== check_warning
4412 : as_bad
) (_("SSE instruction `%s' is used"), i
.tm
.name
);
4415 if (i
.tm
.opcode_modifier
.fwait
)
4416 if (!add_prefix (FWAIT_OPCODE
))
4419 /* Check if REP prefix is OK. */
4420 if (i
.rep_prefix
&& !i
.tm
.opcode_modifier
.repprefixok
)
4422 as_bad (_("invalid instruction `%s' after `%s'"),
4423 i
.tm
.name
, i
.rep_prefix
);
4427 /* Check for lock without a lockable instruction. Destination operand
4428 must be memory unless it is xchg (0x86). */
4429 if (i
.prefix
[LOCK_PREFIX
]
4430 && (!i
.tm
.opcode_modifier
.islockable
4431 || i
.mem_operands
== 0
4432 || (i
.tm
.base_opcode
!= 0x86
4433 && !(i
.flags
[i
.operands
- 1] & Operand_Mem
))))
4435 as_bad (_("expecting lockable instruction after `lock'"));
4439 /* Check for data size prefix on VEX/XOP/EVEX encoded insns. */
4440 if (i
.prefix
[DATA_PREFIX
] && is_any_vex_encoding (&i
.tm
))
4442 as_bad (_("data size prefix invalid with `%s'"), i
.tm
.name
);
4446 /* Check if HLE prefix is OK. */
4447 if (i
.hle_prefix
&& !check_hle ())
4450 /* Check BND prefix. */
4451 if (i
.bnd_prefix
&& !i
.tm
.opcode_modifier
.bndprefixok
)
4452 as_bad (_("expecting valid branch instruction after `bnd'"));
4454 /* Check NOTRACK prefix. */
4455 if (i
.notrack_prefix
&& !i
.tm
.opcode_modifier
.notrackprefixok
)
4456 as_bad (_("expecting indirect branch instruction after `notrack'"));
4458 if (i
.tm
.cpu_flags
.bitfield
.cpumpx
)
4460 if (flag_code
== CODE_64BIT
&& i
.prefix
[ADDR_PREFIX
])
4461 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
4462 else if (flag_code
!= CODE_16BIT
4463 ? i
.prefix
[ADDR_PREFIX
]
4464 : i
.mem_operands
&& !i
.prefix
[ADDR_PREFIX
])
4465 as_bad (_("16-bit address isn't allowed in MPX instructions"));
4468 /* Insert BND prefix. */
4469 if (add_bnd_prefix
&& i
.tm
.opcode_modifier
.bndprefixok
)
4471 if (!i
.prefix
[BND_PREFIX
])
4472 add_prefix (BND_PREFIX_OPCODE
);
4473 else if (i
.prefix
[BND_PREFIX
] != BND_PREFIX_OPCODE
)
4475 as_warn (_("replacing `rep'/`repe' prefix by `bnd'"));
4476 i
.prefix
[BND_PREFIX
] = BND_PREFIX_OPCODE
;
4480 /* Check string instruction segment overrides. */
4481 if (i
.tm
.opcode_modifier
.isstring
>= IS_STRING_ES_OP0
)
4483 gas_assert (i
.mem_operands
);
4484 if (!check_string ())
4486 i
.disp_operands
= 0;
4489 if (optimize
&& !i
.no_optimize
&& i
.tm
.opcode_modifier
.optimize
)
4490 optimize_encoding ();
4492 if (!process_suffix ())
4495 /* Update operand types. */
4496 for (j
= 0; j
< i
.operands
; j
++)
4497 i
.types
[j
] = operand_type_and (i
.types
[j
], i
.tm
.operand_types
[j
]);
4499 /* Make still unresolved immediate matches conform to size of immediate
4500 given in i.suffix. */
4501 if (!finalize_imm ())
4504 if (i
.types
[0].bitfield
.imm1
)
4505 i
.imm_operands
= 0; /* kludge for shift insns. */
4507 /* We only need to check those implicit registers for instructions
4508 with 3 operands or less. */
4509 if (i
.operands
<= 3)
4510 for (j
= 0; j
< i
.operands
; j
++)
4511 if (i
.types
[j
].bitfield
.instance
!= InstanceNone
4512 && !i
.types
[j
].bitfield
.xmmword
)
4515 /* ImmExt should be processed after SSE2AVX. */
4516 if (!i
.tm
.opcode_modifier
.sse2avx
4517 && i
.tm
.opcode_modifier
.immext
)
4520 /* For insns with operands there are more diddles to do to the opcode. */
4523 if (!process_operands ())
4526 else if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
4528 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
4529 as_warn (_("translating to `%sp'"), i
.tm
.name
);
4532 if (is_any_vex_encoding (&i
.tm
))
4534 if (!cpu_arch_flags
.bitfield
.cpui286
)
4536 as_bad (_("instruction `%s' isn't supported outside of protected mode."),
4541 if (i
.tm
.opcode_modifier
.vex
)
4542 build_vex_prefix (t
);
4544 build_evex_prefix ();
4547 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
4548 instructions may define INT_OPCODE as well, so avoid this corner
4549 case for those instructions that use MODRM. */
4550 if (i
.tm
.base_opcode
== INT_OPCODE
4551 && !i
.tm
.opcode_modifier
.modrm
4552 && i
.op
[0].imms
->X_add_number
== 3)
4554 i
.tm
.base_opcode
= INT3_OPCODE
;
4558 if ((i
.tm
.opcode_modifier
.jump
== JUMP
4559 || i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
4560 || i
.tm
.opcode_modifier
.jump
== JUMP_DWORD
)
4561 && i
.op
[0].disps
->X_op
== O_constant
)
4563 /* Convert "jmp constant" (and "call constant") to a jump (call) to
4564 the absolute address given by the constant. Since ix86 jumps and
4565 calls are pc relative, we need to generate a reloc. */
4566 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
4567 i
.op
[0].disps
->X_op
= O_symbol
;
4570 /* For 8 bit registers we need an empty rex prefix. Also if the
4571 instruction already has a prefix, we need to convert old
4572 registers to new ones. */
4574 if ((i
.types
[0].bitfield
.class == Reg
&& i
.types
[0].bitfield
.byte
4575 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
4576 || (i
.types
[1].bitfield
.class == Reg
&& i
.types
[1].bitfield
.byte
4577 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
4578 || (((i
.types
[0].bitfield
.class == Reg
&& i
.types
[0].bitfield
.byte
)
4579 || (i
.types
[1].bitfield
.class == Reg
&& i
.types
[1].bitfield
.byte
))
4584 i
.rex
|= REX_OPCODE
;
4585 for (x
= 0; x
< 2; x
++)
4587 /* Look for 8 bit operand that uses old registers. */
4588 if (i
.types
[x
].bitfield
.class == Reg
&& i
.types
[x
].bitfield
.byte
4589 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
4591 gas_assert (!(i
.op
[x
].regs
->reg_flags
& RegRex
));
4592 /* In case it is "hi" register, give up. */
4593 if (i
.op
[x
].regs
->reg_num
> 3)
4594 as_bad (_("can't encode register '%s%s' in an "
4595 "instruction requiring REX prefix."),
4596 register_prefix
, i
.op
[x
].regs
->reg_name
);
4598 /* Otherwise it is equivalent to the extended register.
4599 Since the encoding doesn't change this is merely
4600 cosmetic cleanup for debug output. */
4602 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
4607 if (i
.rex
== 0 && i
.rex_encoding
)
4609 /* Check if we can add a REX_OPCODE byte. Look for 8 bit operand
4610 that uses legacy register. If it is "hi" register, don't add
4611 the REX_OPCODE byte. */
4613 for (x
= 0; x
< 2; x
++)
4614 if (i
.types
[x
].bitfield
.class == Reg
4615 && i
.types
[x
].bitfield
.byte
4616 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0
4617 && i
.op
[x
].regs
->reg_num
> 3)
4619 gas_assert (!(i
.op
[x
].regs
->reg_flags
& RegRex
));
4620 i
.rex_encoding
= FALSE
;
4629 add_prefix (REX_OPCODE
| i
.rex
);
4631 /* We are ready to output the insn. */
4634 last_insn
.seg
= now_seg
;
4636 if (i
.tm
.opcode_modifier
.isprefix
)
4638 last_insn
.kind
= last_insn_prefix
;
4639 last_insn
.name
= i
.tm
.name
;
4640 last_insn
.file
= as_where (&last_insn
.line
);
4643 last_insn
.kind
= last_insn_other
;
4647 parse_insn (char *line
, char *mnemonic
)
4650 char *token_start
= l
;
4653 const insn_template
*t
;
4659 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
4664 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
4666 as_bad (_("no such instruction: `%s'"), token_start
);
4671 if (!is_space_char (*l
)
4672 && *l
!= END_OF_INSN
4674 || (*l
!= PREFIX_SEPARATOR
4677 as_bad (_("invalid character %s in mnemonic"),
4678 output_invalid (*l
));
4681 if (token_start
== l
)
4683 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
4684 as_bad (_("expecting prefix; got nothing"));
4686 as_bad (_("expecting mnemonic; got nothing"));
4690 /* Look up instruction (or prefix) via hash table. */
4691 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
4693 if (*l
!= END_OF_INSN
4694 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
4695 && current_templates
4696 && current_templates
->start
->opcode_modifier
.isprefix
)
4698 if (!cpu_flags_check_cpu64 (current_templates
->start
->cpu_flags
))
4700 as_bad ((flag_code
!= CODE_64BIT
4701 ? _("`%s' is only supported in 64-bit mode")
4702 : _("`%s' is not supported in 64-bit mode")),
4703 current_templates
->start
->name
);
4706 /* If we are in 16-bit mode, do not allow addr16 or data16.
4707 Similarly, in 32-bit mode, do not allow addr32 or data32. */
4708 if ((current_templates
->start
->opcode_modifier
.size
== SIZE16
4709 || current_templates
->start
->opcode_modifier
.size
== SIZE32
)
4710 && flag_code
!= CODE_64BIT
4711 && ((current_templates
->start
->opcode_modifier
.size
== SIZE32
)
4712 ^ (flag_code
== CODE_16BIT
)))
4714 as_bad (_("redundant %s prefix"),
4715 current_templates
->start
->name
);
4718 if (current_templates
->start
->opcode_length
== 0)
4720 /* Handle pseudo prefixes. */
4721 switch (current_templates
->start
->base_opcode
)
4725 i
.disp_encoding
= disp_encoding_8bit
;
4729 i
.disp_encoding
= disp_encoding_32bit
;
4733 i
.dir_encoding
= dir_encoding_load
;
4737 i
.dir_encoding
= dir_encoding_store
;
4741 i
.vec_encoding
= vex_encoding_vex
;
4745 i
.vec_encoding
= vex_encoding_vex3
;
4749 i
.vec_encoding
= vex_encoding_evex
;
4753 i
.rex_encoding
= TRUE
;
4757 i
.no_optimize
= TRUE
;
4765 /* Add prefix, checking for repeated prefixes. */
4766 switch (add_prefix (current_templates
->start
->base_opcode
))
4771 if (current_templates
->start
->cpu_flags
.bitfield
.cpuibt
)
4772 i
.notrack_prefix
= current_templates
->start
->name
;
4775 if (current_templates
->start
->cpu_flags
.bitfield
.cpuhle
)
4776 i
.hle_prefix
= current_templates
->start
->name
;
4777 else if (current_templates
->start
->cpu_flags
.bitfield
.cpumpx
)
4778 i
.bnd_prefix
= current_templates
->start
->name
;
4780 i
.rep_prefix
= current_templates
->start
->name
;
4786 /* Skip past PREFIX_SEPARATOR and reset token_start. */
4793 if (!current_templates
)
4795 /* Deprecated functionality (new code should use pseudo-prefixes instead):
4796 Check if we should swap operand or force 32bit displacement in
4798 if (mnem_p
- 2 == dot_p
&& dot_p
[1] == 's')
4799 i
.dir_encoding
= dir_encoding_swap
;
4800 else if (mnem_p
- 3 == dot_p
4803 i
.disp_encoding
= disp_encoding_8bit
;
4804 else if (mnem_p
- 4 == dot_p
4808 i
.disp_encoding
= disp_encoding_32bit
;
4813 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
4816 if (!current_templates
)
4819 if (mnem_p
> mnemonic
)
4821 /* See if we can get a match by trimming off a suffix. */
4824 case WORD_MNEM_SUFFIX
:
4825 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
4826 i
.suffix
= SHORT_MNEM_SUFFIX
;
4829 case BYTE_MNEM_SUFFIX
:
4830 case QWORD_MNEM_SUFFIX
:
4831 i
.suffix
= mnem_p
[-1];
4833 current_templates
= (const templates
*) hash_find (op_hash
,
4836 case SHORT_MNEM_SUFFIX
:
4837 case LONG_MNEM_SUFFIX
:
4840 i
.suffix
= mnem_p
[-1];
4842 current_templates
= (const templates
*) hash_find (op_hash
,
4851 if (intel_float_operand (mnemonic
) == 1)
4852 i
.suffix
= SHORT_MNEM_SUFFIX
;
4854 i
.suffix
= LONG_MNEM_SUFFIX
;
4856 current_templates
= (const templates
*) hash_find (op_hash
,
4863 if (!current_templates
)
4865 as_bad (_("no such instruction: `%s'"), token_start
);
4870 if (current_templates
->start
->opcode_modifier
.jump
== JUMP
4871 || current_templates
->start
->opcode_modifier
.jump
== JUMP_BYTE
)
4873 /* Check for a branch hint. We allow ",pt" and ",pn" for
4874 predict taken and predict not taken respectively.
4875 I'm not sure that branch hints actually do anything on loop
4876 and jcxz insns (JumpByte) for current Pentium4 chips. They
4877 may work in the future and it doesn't hurt to accept them
4879 if (l
[0] == ',' && l
[1] == 'p')
4883 if (!add_prefix (DS_PREFIX_OPCODE
))
4887 else if (l
[2] == 'n')
4889 if (!add_prefix (CS_PREFIX_OPCODE
))
4895 /* Any other comma loses. */
4898 as_bad (_("invalid character %s in mnemonic"),
4899 output_invalid (*l
));
4903 /* Check if instruction is supported on specified architecture. */
4905 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
4907 supported
|= cpu_flags_match (t
);
4908 if (supported
== CPU_FLAGS_PERFECT_MATCH
)
4910 if (!cpu_arch_flags
.bitfield
.cpui386
&& (flag_code
!= CODE_16BIT
))
4911 as_warn (_("use .code16 to ensure correct addressing mode"));
4917 if (!(supported
& CPU_FLAGS_64BIT_MATCH
))
4918 as_bad (flag_code
== CODE_64BIT
4919 ? _("`%s' is not supported in 64-bit mode")
4920 : _("`%s' is only supported in 64-bit mode"),
4921 current_templates
->start
->name
);
4923 as_bad (_("`%s' is not supported on `%s%s'"),
4924 current_templates
->start
->name
,
4925 cpu_arch_name
? cpu_arch_name
: default_arch
,
4926 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
4932 parse_operands (char *l
, const char *mnemonic
)
4936 /* 1 if operand is pending after ','. */
4937 unsigned int expecting_operand
= 0;
4939 /* Non-zero if operand parens not balanced. */
4940 unsigned int paren_not_balanced
;
4942 while (*l
!= END_OF_INSN
)
4944 /* Skip optional white space before operand. */
4945 if (is_space_char (*l
))
4947 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
&& *l
!= '"')
4949 as_bad (_("invalid character %s before operand %d"),
4950 output_invalid (*l
),
4954 token_start
= l
; /* After white space. */
4955 paren_not_balanced
= 0;
4956 while (paren_not_balanced
|| *l
!= ',')
4958 if (*l
== END_OF_INSN
)
4960 if (paren_not_balanced
)
4963 as_bad (_("unbalanced parenthesis in operand %d."),
4966 as_bad (_("unbalanced brackets in operand %d."),
4971 break; /* we are done */
4973 else if (!is_operand_char (*l
) && !is_space_char (*l
) && *l
!= '"')
4975 as_bad (_("invalid character %s in operand %d"),
4976 output_invalid (*l
),
4983 ++paren_not_balanced
;
4985 --paren_not_balanced
;
4990 ++paren_not_balanced
;
4992 --paren_not_balanced
;
4996 if (l
!= token_start
)
4997 { /* Yes, we've read in another operand. */
4998 unsigned int operand_ok
;
4999 this_operand
= i
.operands
++;
5000 if (i
.operands
> MAX_OPERANDS
)
5002 as_bad (_("spurious operands; (%d operands/instruction max)"),
5006 i
.types
[this_operand
].bitfield
.unspecified
= 1;
5007 /* Now parse operand adding info to 'i' as we go along. */
5008 END_STRING_AND_SAVE (l
);
5010 if (i
.mem_operands
> 1)
5012 as_bad (_("too many memory references for `%s'"),
5019 i386_intel_operand (token_start
,
5020 intel_float_operand (mnemonic
));
5022 operand_ok
= i386_att_operand (token_start
);
5024 RESTORE_END_STRING (l
);
5030 if (expecting_operand
)
5032 expecting_operand_after_comma
:
5033 as_bad (_("expecting operand after ','; got nothing"));
5038 as_bad (_("expecting operand before ','; got nothing"));
5043 /* Now *l must be either ',' or END_OF_INSN. */
5046 if (*++l
== END_OF_INSN
)
5048 /* Just skip it, if it's \n complain. */
5049 goto expecting_operand_after_comma
;
5051 expecting_operand
= 1;
5058 swap_2_operands (int xchg1
, int xchg2
)
5060 union i386_op temp_op
;
5061 i386_operand_type temp_type
;
5062 unsigned int temp_flags
;
5063 enum bfd_reloc_code_real temp_reloc
;
5065 temp_type
= i
.types
[xchg2
];
5066 i
.types
[xchg2
] = i
.types
[xchg1
];
5067 i
.types
[xchg1
] = temp_type
;
5069 temp_flags
= i
.flags
[xchg2
];
5070 i
.flags
[xchg2
] = i
.flags
[xchg1
];
5071 i
.flags
[xchg1
] = temp_flags
;
5073 temp_op
= i
.op
[xchg2
];
5074 i
.op
[xchg2
] = i
.op
[xchg1
];
5075 i
.op
[xchg1
] = temp_op
;
5077 temp_reloc
= i
.reloc
[xchg2
];
5078 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
5079 i
.reloc
[xchg1
] = temp_reloc
;
5083 if (i
.mask
->operand
== xchg1
)
5084 i
.mask
->operand
= xchg2
;
5085 else if (i
.mask
->operand
== xchg2
)
5086 i
.mask
->operand
= xchg1
;
5090 if (i
.broadcast
->operand
== xchg1
)
5091 i
.broadcast
->operand
= xchg2
;
5092 else if (i
.broadcast
->operand
== xchg2
)
5093 i
.broadcast
->operand
= xchg1
;
5097 if (i
.rounding
->operand
== xchg1
)
5098 i
.rounding
->operand
= xchg2
;
5099 else if (i
.rounding
->operand
== xchg2
)
5100 i
.rounding
->operand
= xchg1
;
5105 swap_operands (void)
5111 swap_2_operands (1, i
.operands
- 2);
5115 swap_2_operands (0, i
.operands
- 1);
5121 if (i
.mem_operands
== 2)
5123 const seg_entry
*temp_seg
;
5124 temp_seg
= i
.seg
[0];
5125 i
.seg
[0] = i
.seg
[1];
5126 i
.seg
[1] = temp_seg
;
5130 /* Try to ensure constant immediates are represented in the smallest
5135 char guess_suffix
= 0;
5139 guess_suffix
= i
.suffix
;
5140 else if (i
.reg_operands
)
5142 /* Figure out a suffix from the last register operand specified.
5143 We can't do this properly yet, i.e. excluding special register
5144 instances, but the following works for instructions with
5145 immediates. In any case, we can't set i.suffix yet. */
5146 for (op
= i
.operands
; --op
>= 0;)
5147 if (i
.types
[op
].bitfield
.class != Reg
)
5149 else if (i
.types
[op
].bitfield
.byte
)
5151 guess_suffix
= BYTE_MNEM_SUFFIX
;
5154 else if (i
.types
[op
].bitfield
.word
)
5156 guess_suffix
= WORD_MNEM_SUFFIX
;
5159 else if (i
.types
[op
].bitfield
.dword
)
5161 guess_suffix
= LONG_MNEM_SUFFIX
;
5164 else if (i
.types
[op
].bitfield
.qword
)
5166 guess_suffix
= QWORD_MNEM_SUFFIX
;
5170 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
5171 guess_suffix
= WORD_MNEM_SUFFIX
;
5173 for (op
= i
.operands
; --op
>= 0;)
5174 if (operand_type_check (i
.types
[op
], imm
))
5176 switch (i
.op
[op
].imms
->X_op
)
5179 /* If a suffix is given, this operand may be shortened. */
5180 switch (guess_suffix
)
5182 case LONG_MNEM_SUFFIX
:
5183 i
.types
[op
].bitfield
.imm32
= 1;
5184 i
.types
[op
].bitfield
.imm64
= 1;
5186 case WORD_MNEM_SUFFIX
:
5187 i
.types
[op
].bitfield
.imm16
= 1;
5188 i
.types
[op
].bitfield
.imm32
= 1;
5189 i
.types
[op
].bitfield
.imm32s
= 1;
5190 i
.types
[op
].bitfield
.imm64
= 1;
5192 case BYTE_MNEM_SUFFIX
:
5193 i
.types
[op
].bitfield
.imm8
= 1;
5194 i
.types
[op
].bitfield
.imm8s
= 1;
5195 i
.types
[op
].bitfield
.imm16
= 1;
5196 i
.types
[op
].bitfield
.imm32
= 1;
5197 i
.types
[op
].bitfield
.imm32s
= 1;
5198 i
.types
[op
].bitfield
.imm64
= 1;
5202 /* If this operand is at most 16 bits, convert it
5203 to a signed 16 bit number before trying to see
5204 whether it will fit in an even smaller size.
5205 This allows a 16-bit operand such as $0xffe0 to
5206 be recognised as within Imm8S range. */
5207 if ((i
.types
[op
].bitfield
.imm16
)
5208 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
5210 i
.op
[op
].imms
->X_add_number
=
5211 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
5214 /* Store 32-bit immediate in 64-bit for 64-bit BFD. */
5215 if ((i
.types
[op
].bitfield
.imm32
)
5216 && ((i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1))
5219 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
5220 ^ ((offsetT
) 1 << 31))
5221 - ((offsetT
) 1 << 31));
5225 = operand_type_or (i
.types
[op
],
5226 smallest_imm_type (i
.op
[op
].imms
->X_add_number
));
5228 /* We must avoid matching of Imm32 templates when 64bit
5229 only immediate is available. */
5230 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
5231 i
.types
[op
].bitfield
.imm32
= 0;
5238 /* Symbols and expressions. */
5240 /* Convert symbolic operand to proper sizes for matching, but don't
5241 prevent matching a set of insns that only supports sizes other
5242 than those matching the insn suffix. */
5244 i386_operand_type mask
, allowed
;
5245 const insn_template
*t
;
5247 operand_type_set (&mask
, 0);
5248 operand_type_set (&allowed
, 0);
5250 for (t
= current_templates
->start
;
5251 t
< current_templates
->end
;
5254 allowed
= operand_type_or (allowed
, t
->operand_types
[op
]);
5255 allowed
= operand_type_and (allowed
, anyimm
);
5257 switch (guess_suffix
)
5259 case QWORD_MNEM_SUFFIX
:
5260 mask
.bitfield
.imm64
= 1;
5261 mask
.bitfield
.imm32s
= 1;
5263 case LONG_MNEM_SUFFIX
:
5264 mask
.bitfield
.imm32
= 1;
5266 case WORD_MNEM_SUFFIX
:
5267 mask
.bitfield
.imm16
= 1;
5269 case BYTE_MNEM_SUFFIX
:
5270 mask
.bitfield
.imm8
= 1;
5275 allowed
= operand_type_and (mask
, allowed
);
5276 if (!operand_type_all_zero (&allowed
))
5277 i
.types
[op
] = operand_type_and (i
.types
[op
], mask
);
5284 /* Try to use the smallest displacement type too. */
5286 optimize_disp (void)
5290 for (op
= i
.operands
; --op
>= 0;)
5291 if (operand_type_check (i
.types
[op
], disp
))
5293 if (i
.op
[op
].disps
->X_op
== O_constant
)
5295 offsetT op_disp
= i
.op
[op
].disps
->X_add_number
;
5297 if (i
.types
[op
].bitfield
.disp16
5298 && (op_disp
& ~(offsetT
) 0xffff) == 0)
5300 /* If this operand is at most 16 bits, convert
5301 to a signed 16 bit number and don't use 64bit
5303 op_disp
= (((op_disp
& 0xffff) ^ 0x8000) - 0x8000);
5304 i
.types
[op
].bitfield
.disp64
= 0;
5307 /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */
5308 if (i
.types
[op
].bitfield
.disp32
5309 && (op_disp
& ~(((offsetT
) 2 << 31) - 1)) == 0)
5311 /* If this operand is at most 32 bits, convert
5312 to a signed 32 bit number and don't use 64bit
5314 op_disp
&= (((offsetT
) 2 << 31) - 1);
5315 op_disp
= (op_disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
5316 i
.types
[op
].bitfield
.disp64
= 0;
5319 if (!op_disp
&& i
.types
[op
].bitfield
.baseindex
)
5321 i
.types
[op
].bitfield
.disp8
= 0;
5322 i
.types
[op
].bitfield
.disp16
= 0;
5323 i
.types
[op
].bitfield
.disp32
= 0;
5324 i
.types
[op
].bitfield
.disp32s
= 0;
5325 i
.types
[op
].bitfield
.disp64
= 0;
5329 else if (flag_code
== CODE_64BIT
)
5331 if (fits_in_signed_long (op_disp
))
5333 i
.types
[op
].bitfield
.disp64
= 0;
5334 i
.types
[op
].bitfield
.disp32s
= 1;
5336 if (i
.prefix
[ADDR_PREFIX
]
5337 && fits_in_unsigned_long (op_disp
))
5338 i
.types
[op
].bitfield
.disp32
= 1;
5340 if ((i
.types
[op
].bitfield
.disp32
5341 || i
.types
[op
].bitfield
.disp32s
5342 || i
.types
[op
].bitfield
.disp16
)
5343 && fits_in_disp8 (op_disp
))
5344 i
.types
[op
].bitfield
.disp8
= 1;
5346 else if (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
5347 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
)
5349 fix_new_exp (frag_now
, frag_more (0) - frag_now
->fr_literal
, 0,
5350 i
.op
[op
].disps
, 0, i
.reloc
[op
]);
5351 i
.types
[op
].bitfield
.disp8
= 0;
5352 i
.types
[op
].bitfield
.disp16
= 0;
5353 i
.types
[op
].bitfield
.disp32
= 0;
5354 i
.types
[op
].bitfield
.disp32s
= 0;
5355 i
.types
[op
].bitfield
.disp64
= 0;
5358 /* We only support 64bit displacement on constants. */
5359 i
.types
[op
].bitfield
.disp64
= 0;
5363 /* Return 1 if there is a match in broadcast bytes between operand
5364 GIVEN and instruction template T. */
5367 match_broadcast_size (const insn_template
*t
, unsigned int given
)
5369 return ((t
->opcode_modifier
.broadcast
== BYTE_BROADCAST
5370 && i
.types
[given
].bitfield
.byte
)
5371 || (t
->opcode_modifier
.broadcast
== WORD_BROADCAST
5372 && i
.types
[given
].bitfield
.word
)
5373 || (t
->opcode_modifier
.broadcast
== DWORD_BROADCAST
5374 && i
.types
[given
].bitfield
.dword
)
5375 || (t
->opcode_modifier
.broadcast
== QWORD_BROADCAST
5376 && i
.types
[given
].bitfield
.qword
));
5379 /* Check if operands are valid for the instruction. */
5382 check_VecOperands (const insn_template
*t
)
5387 /* Templates allowing for ZMMword as well as YMMword and/or XMMword for
5388 any one operand are implicity requiring AVX512VL support if the actual
5389 operand size is YMMword or XMMword. Since this function runs after
5390 template matching, there's no need to check for YMMword/XMMword in
5392 cpu
= cpu_flags_and (t
->cpu_flags
, avx512
);
5393 if (!cpu_flags_all_zero (&cpu
)
5394 && !t
->cpu_flags
.bitfield
.cpuavx512vl
5395 && !cpu_arch_flags
.bitfield
.cpuavx512vl
)
5397 for (op
= 0; op
< t
->operands
; ++op
)
5399 if (t
->operand_types
[op
].bitfield
.zmmword
5400 && (i
.types
[op
].bitfield
.ymmword
5401 || i
.types
[op
].bitfield
.xmmword
))
5403 i
.error
= unsupported
;
5409 /* Without VSIB byte, we can't have a vector register for index. */
5410 if (!t
->opcode_modifier
.vecsib
5412 && (i
.index_reg
->reg_type
.bitfield
.xmmword
5413 || i
.index_reg
->reg_type
.bitfield
.ymmword
5414 || i
.index_reg
->reg_type
.bitfield
.zmmword
))
5416 i
.error
= unsupported_vector_index_register
;
5420 /* Check if default mask is allowed. */
5421 if (t
->opcode_modifier
.nodefmask
5422 && (!i
.mask
|| i
.mask
->mask
->reg_num
== 0))
5424 i
.error
= no_default_mask
;
5428 /* For VSIB byte, we need a vector register for index, and all vector
5429 registers must be distinct. */
5430 if (t
->opcode_modifier
.vecsib
)
5433 || !((t
->opcode_modifier
.vecsib
== VecSIB128
5434 && i
.index_reg
->reg_type
.bitfield
.xmmword
)
5435 || (t
->opcode_modifier
.vecsib
== VecSIB256
5436 && i
.index_reg
->reg_type
.bitfield
.ymmword
)
5437 || (t
->opcode_modifier
.vecsib
== VecSIB512
5438 && i
.index_reg
->reg_type
.bitfield
.zmmword
)))
5440 i
.error
= invalid_vsib_address
;
5444 gas_assert (i
.reg_operands
== 2 || i
.mask
);
5445 if (i
.reg_operands
== 2 && !i
.mask
)
5447 gas_assert (i
.types
[0].bitfield
.class == RegSIMD
);
5448 gas_assert (i
.types
[0].bitfield
.xmmword
5449 || i
.types
[0].bitfield
.ymmword
);
5450 gas_assert (i
.types
[2].bitfield
.class == RegSIMD
);
5451 gas_assert (i
.types
[2].bitfield
.xmmword
5452 || i
.types
[2].bitfield
.ymmword
);
5453 if (operand_check
== check_none
)
5455 if (register_number (i
.op
[0].regs
)
5456 != register_number (i
.index_reg
)
5457 && register_number (i
.op
[2].regs
)
5458 != register_number (i
.index_reg
)
5459 && register_number (i
.op
[0].regs
)
5460 != register_number (i
.op
[2].regs
))
5462 if (operand_check
== check_error
)
5464 i
.error
= invalid_vector_register_set
;
5467 as_warn (_("mask, index, and destination registers should be distinct"));
5469 else if (i
.reg_operands
== 1 && i
.mask
)
5471 if (i
.types
[1].bitfield
.class == RegSIMD
5472 && (i
.types
[1].bitfield
.xmmword
5473 || i
.types
[1].bitfield
.ymmword
5474 || i
.types
[1].bitfield
.zmmword
)
5475 && (register_number (i
.op
[1].regs
)
5476 == register_number (i
.index_reg
)))
5478 if (operand_check
== check_error
)
5480 i
.error
= invalid_vector_register_set
;
5483 if (operand_check
!= check_none
)
5484 as_warn (_("index and destination registers should be distinct"));
5489 /* Check if broadcast is supported by the instruction and is applied
5490 to the memory operand. */
5493 i386_operand_type type
, overlap
;
5495 /* Check if specified broadcast is supported in this instruction,
5496 and its broadcast bytes match the memory operand. */
5497 op
= i
.broadcast
->operand
;
5498 if (!t
->opcode_modifier
.broadcast
5499 || !(i
.flags
[op
] & Operand_Mem
)
5500 || (!i
.types
[op
].bitfield
.unspecified
5501 && !match_broadcast_size (t
, op
)))
5504 i
.error
= unsupported_broadcast
;
5508 i
.broadcast
->bytes
= ((1 << (t
->opcode_modifier
.broadcast
- 1))
5509 * i
.broadcast
->type
);
5510 operand_type_set (&type
, 0);
5511 switch (i
.broadcast
->bytes
)
5514 type
.bitfield
.word
= 1;
5517 type
.bitfield
.dword
= 1;
5520 type
.bitfield
.qword
= 1;
5523 type
.bitfield
.xmmword
= 1;
5526 type
.bitfield
.ymmword
= 1;
5529 type
.bitfield
.zmmword
= 1;
5535 overlap
= operand_type_and (type
, t
->operand_types
[op
]);
5536 if (operand_type_all_zero (&overlap
))
5539 if (t
->opcode_modifier
.checkregsize
)
5543 type
.bitfield
.baseindex
= 1;
5544 for (j
= 0; j
< i
.operands
; ++j
)
5547 && !operand_type_register_match(i
.types
[j
],
5548 t
->operand_types
[j
],
5550 t
->operand_types
[op
]))
5555 /* If broadcast is supported in this instruction, we need to check if
5556 operand of one-element size isn't specified without broadcast. */
5557 else if (t
->opcode_modifier
.broadcast
&& i
.mem_operands
)
5559 /* Find memory operand. */
5560 for (op
= 0; op
< i
.operands
; op
++)
5561 if (i
.flags
[op
] & Operand_Mem
)
5563 gas_assert (op
< i
.operands
);
5564 /* Check size of the memory operand. */
5565 if (match_broadcast_size (t
, op
))
5567 i
.error
= broadcast_needed
;
5572 op
= MAX_OPERANDS
- 1; /* Avoid uninitialized variable warning. */
5574 /* Check if requested masking is supported. */
5577 switch (t
->opcode_modifier
.masking
)
5581 case MERGING_MASKING
:
5582 if (i
.mask
->zeroing
)
5585 i
.error
= unsupported_masking
;
5589 case DYNAMIC_MASKING
:
5590 /* Memory destinations allow only merging masking. */
5591 if (i
.mask
->zeroing
&& i
.mem_operands
)
5593 /* Find memory operand. */
5594 for (op
= 0; op
< i
.operands
; op
++)
5595 if (i
.flags
[op
] & Operand_Mem
)
5597 gas_assert (op
< i
.operands
);
5598 if (op
== i
.operands
- 1)
5600 i
.error
= unsupported_masking
;
5610 /* Check if masking is applied to dest operand. */
5611 if (i
.mask
&& (i
.mask
->operand
!= (int) (i
.operands
- 1)))
5613 i
.error
= mask_not_on_destination
;
5620 if (!t
->opcode_modifier
.sae
5621 || (i
.rounding
->type
!= saeonly
&& !t
->opcode_modifier
.staticrounding
))
5623 i
.error
= unsupported_rc_sae
;
5626 /* If the instruction has several immediate operands and one of
5627 them is rounding, the rounding operand should be the last
5628 immediate operand. */
5629 if (i
.imm_operands
> 1
5630 && i
.rounding
->operand
!= (int) (i
.imm_operands
- 1))
5632 i
.error
= rc_sae_operand_not_last_imm
;
5637 /* Check vector Disp8 operand. */
5638 if (t
->opcode_modifier
.disp8memshift
5639 && i
.disp_encoding
!= disp_encoding_32bit
)
5642 i
.memshift
= t
->opcode_modifier
.broadcast
- 1;
5643 else if (t
->opcode_modifier
.disp8memshift
!= DISP8_SHIFT_VL
)
5644 i
.memshift
= t
->opcode_modifier
.disp8memshift
;
5647 const i386_operand_type
*type
= NULL
;
5650 for (op
= 0; op
< i
.operands
; op
++)
5651 if (i
.flags
[op
] & Operand_Mem
)
5653 if (t
->opcode_modifier
.evex
== EVEXLIG
)
5654 i
.memshift
= 2 + (i
.suffix
== QWORD_MNEM_SUFFIX
);
5655 else if (t
->operand_types
[op
].bitfield
.xmmword
5656 + t
->operand_types
[op
].bitfield
.ymmword
5657 + t
->operand_types
[op
].bitfield
.zmmword
<= 1)
5658 type
= &t
->operand_types
[op
];
5659 else if (!i
.types
[op
].bitfield
.unspecified
)
5660 type
= &i
.types
[op
];
5662 else if (i
.types
[op
].bitfield
.class == RegSIMD
5663 && t
->opcode_modifier
.evex
!= EVEXLIG
)
5665 if (i
.types
[op
].bitfield
.zmmword
)
5667 else if (i
.types
[op
].bitfield
.ymmword
&& i
.memshift
< 5)
5669 else if (i
.types
[op
].bitfield
.xmmword
&& i
.memshift
< 4)
5675 if (type
->bitfield
.zmmword
)
5677 else if (type
->bitfield
.ymmword
)
5679 else if (type
->bitfield
.xmmword
)
5683 /* For the check in fits_in_disp8(). */
5684 if (i
.memshift
== 0)
5688 for (op
= 0; op
< i
.operands
; op
++)
5689 if (operand_type_check (i
.types
[op
], disp
)
5690 && i
.op
[op
].disps
->X_op
== O_constant
)
5692 if (fits_in_disp8 (i
.op
[op
].disps
->X_add_number
))
5694 i
.types
[op
].bitfield
.disp8
= 1;
5697 i
.types
[op
].bitfield
.disp8
= 0;
5706 /* Check if operands are valid for the instruction. Update VEX
5710 VEX_check_operands (const insn_template
*t
)
5712 if (i
.vec_encoding
== vex_encoding_evex
)
5714 /* This instruction must be encoded with EVEX prefix. */
5715 if (!is_evex_encoding (t
))
5717 i
.error
= unsupported
;
5723 if (!t
->opcode_modifier
.vex
)
5725 /* This instruction template doesn't have VEX prefix. */
5726 if (i
.vec_encoding
!= vex_encoding_default
)
5728 i
.error
= unsupported
;
5734 /* Check the special Imm4 cases; must be the first operand. */
5735 if (t
->cpu_flags
.bitfield
.cpuxop
&& t
->operands
== 5)
5737 if (i
.op
[0].imms
->X_op
!= O_constant
5738 || !fits_in_imm4 (i
.op
[0].imms
->X_add_number
))
5744 /* Turn off Imm<N> so that update_imm won't complain. */
5745 operand_type_set (&i
.types
[0], 0);
5751 static const insn_template
*
5752 match_template (char mnem_suffix
)
5754 /* Points to template once we've found it. */
5755 const insn_template
*t
;
5756 i386_operand_type overlap0
, overlap1
, overlap2
, overlap3
;
5757 i386_operand_type overlap4
;
5758 unsigned int found_reverse_match
;
5759 i386_opcode_modifier suffix_check
;
5760 i386_operand_type operand_types
[MAX_OPERANDS
];
5761 int addr_prefix_disp
;
5762 unsigned int j
, size_match
, check_register
;
5763 enum i386_error specific_error
= 0;
5765 #if MAX_OPERANDS != 5
5766 # error "MAX_OPERANDS must be 5."
5769 found_reverse_match
= 0;
5770 addr_prefix_disp
= -1;
5772 /* Prepare for mnemonic suffix check. */
5773 memset (&suffix_check
, 0, sizeof (suffix_check
));
5774 switch (mnem_suffix
)
5776 case BYTE_MNEM_SUFFIX
:
5777 suffix_check
.no_bsuf
= 1;
5779 case WORD_MNEM_SUFFIX
:
5780 suffix_check
.no_wsuf
= 1;
5782 case SHORT_MNEM_SUFFIX
:
5783 suffix_check
.no_ssuf
= 1;
5785 case LONG_MNEM_SUFFIX
:
5786 suffix_check
.no_lsuf
= 1;
5788 case QWORD_MNEM_SUFFIX
:
5789 suffix_check
.no_qsuf
= 1;
5792 /* NB: In Intel syntax, normally we can check for memory operand
5793 size when there is no mnemonic suffix. But jmp and call have
5794 2 different encodings with Dword memory operand size, one with
5795 No_ldSuf and the other without. i.suffix is set to
5796 LONG_DOUBLE_MNEM_SUFFIX to skip the one with No_ldSuf. */
5797 if (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
)
5798 suffix_check
.no_ldsuf
= 1;
5801 /* Must have right number of operands. */
5802 i
.error
= number_of_operands_mismatch
;
5804 for (t
= current_templates
->start
; t
< current_templates
->end
; t
++)
5806 addr_prefix_disp
= -1;
5807 found_reverse_match
= 0;
5809 if (i
.operands
!= t
->operands
)
5812 /* Check processor support. */
5813 i
.error
= unsupported
;
5814 if (cpu_flags_match (t
) != CPU_FLAGS_PERFECT_MATCH
)
5817 /* Check AT&T mnemonic. */
5818 i
.error
= unsupported_with_intel_mnemonic
;
5819 if (intel_mnemonic
&& t
->opcode_modifier
.attmnemonic
)
5822 /* Check AT&T/Intel syntax. */
5823 i
.error
= unsupported_syntax
;
5824 if ((intel_syntax
&& t
->opcode_modifier
.attsyntax
)
5825 || (!intel_syntax
&& t
->opcode_modifier
.intelsyntax
))
5828 /* Check Intel64/AMD64 ISA. */
5832 /* Default: Don't accept Intel64. */
5833 if (t
->opcode_modifier
.isa64
== INTEL64
)
5837 /* -mamd64: Don't accept Intel64 and Intel64 only. */
5838 if (t
->opcode_modifier
.isa64
>= INTEL64
)
5842 /* -mintel64: Don't accept AMD64. */
5843 if (t
->opcode_modifier
.isa64
== AMD64
&& flag_code
== CODE_64BIT
)
5848 /* Check the suffix. */
5849 i
.error
= invalid_instruction_suffix
;
5850 if ((t
->opcode_modifier
.no_bsuf
&& suffix_check
.no_bsuf
)
5851 || (t
->opcode_modifier
.no_wsuf
&& suffix_check
.no_wsuf
)
5852 || (t
->opcode_modifier
.no_lsuf
&& suffix_check
.no_lsuf
)
5853 || (t
->opcode_modifier
.no_ssuf
&& suffix_check
.no_ssuf
)
5854 || (t
->opcode_modifier
.no_qsuf
&& suffix_check
.no_qsuf
)
5855 || (t
->opcode_modifier
.no_ldsuf
&& suffix_check
.no_ldsuf
))
5858 size_match
= operand_size_match (t
);
5862 /* This is intentionally not
5864 if (i.jumpabsolute != (t->opcode_modifier.jump == JUMP_ABSOLUTE))
5866 as the case of a missing * on the operand is accepted (perhaps with
5867 a warning, issued further down). */
5868 if (i
.jumpabsolute
&& t
->opcode_modifier
.jump
!= JUMP_ABSOLUTE
)
5870 i
.error
= operand_type_mismatch
;
5874 for (j
= 0; j
< MAX_OPERANDS
; j
++)
5875 operand_types
[j
] = t
->operand_types
[j
];
5877 /* In general, don't allow 64-bit operands in 32-bit mode. */
5878 if (i
.suffix
== QWORD_MNEM_SUFFIX
5879 && flag_code
!= CODE_64BIT
5881 ? (t
->opcode_modifier
.mnemonicsize
!= IGNORESIZE
5882 && !t
->opcode_modifier
.broadcast
5883 && !intel_float_operand (t
->name
))
5884 : intel_float_operand (t
->name
) != 2)
5885 && ((operand_types
[0].bitfield
.class != RegMMX
5886 && operand_types
[0].bitfield
.class != RegSIMD
)
5887 || (operand_types
[t
->operands
> 1].bitfield
.class != RegMMX
5888 && operand_types
[t
->operands
> 1].bitfield
.class != RegSIMD
))
5889 && (t
->base_opcode
!= 0x0fc7
5890 || t
->extension_opcode
!= 1 /* cmpxchg8b */))
5893 /* In general, don't allow 32-bit operands on pre-386. */
5894 else if (i
.suffix
== LONG_MNEM_SUFFIX
5895 && !cpu_arch_flags
.bitfield
.cpui386
5897 ? (t
->opcode_modifier
.mnemonicsize
!= IGNORESIZE
5898 && !intel_float_operand (t
->name
))
5899 : intel_float_operand (t
->name
) != 2)
5900 && ((operand_types
[0].bitfield
.class != RegMMX
5901 && operand_types
[0].bitfield
.class != RegSIMD
)
5902 || (operand_types
[t
->operands
> 1].bitfield
.class != RegMMX
5903 && operand_types
[t
->operands
> 1].bitfield
.class
5907 /* Do not verify operands when there are none. */
5911 /* We've found a match; break out of loop. */
5915 if (!t
->opcode_modifier
.jump
5916 || t
->opcode_modifier
.jump
== JUMP_ABSOLUTE
)
5918 /* There should be only one Disp operand. */
5919 for (j
= 0; j
< MAX_OPERANDS
; j
++)
5920 if (operand_type_check (operand_types
[j
], disp
))
5922 if (j
< MAX_OPERANDS
)
5924 bfd_boolean override
= (i
.prefix
[ADDR_PREFIX
] != 0);
5926 addr_prefix_disp
= j
;
5928 /* Address size prefix will turn Disp64/Disp32S/Disp32/Disp16
5929 operand into Disp32/Disp32/Disp16/Disp32 operand. */
5933 override
= !override
;
5936 if (operand_types
[j
].bitfield
.disp32
5937 && operand_types
[j
].bitfield
.disp16
)
5939 operand_types
[j
].bitfield
.disp16
= override
;
5940 operand_types
[j
].bitfield
.disp32
= !override
;
5942 operand_types
[j
].bitfield
.disp32s
= 0;
5943 operand_types
[j
].bitfield
.disp64
= 0;
5947 if (operand_types
[j
].bitfield
.disp32s
5948 || operand_types
[j
].bitfield
.disp64
)
5950 operand_types
[j
].bitfield
.disp64
&= !override
;
5951 operand_types
[j
].bitfield
.disp32s
&= !override
;
5952 operand_types
[j
].bitfield
.disp32
= override
;
5954 operand_types
[j
].bitfield
.disp16
= 0;
5960 /* Force 0x8b encoding for "mov foo@GOT, %eax". */
5961 if (i
.reloc
[0] == BFD_RELOC_386_GOT32
&& t
->base_opcode
== 0xa0)
5964 /* We check register size if needed. */
5965 if (t
->opcode_modifier
.checkregsize
)
5967 check_register
= (1 << t
->operands
) - 1;
5969 check_register
&= ~(1 << i
.broadcast
->operand
);
5974 overlap0
= operand_type_and (i
.types
[0], operand_types
[0]);
5975 switch (t
->operands
)
5978 if (!operand_type_match (overlap0
, i
.types
[0]))
5982 /* xchg %eax, %eax is a special case. It is an alias for nop
5983 only in 32bit mode and we can use opcode 0x90. In 64bit
5984 mode, we can't use 0x90 for xchg %eax, %eax since it should
5985 zero-extend %eax to %rax. */
5986 if (flag_code
== CODE_64BIT
5987 && t
->base_opcode
== 0x90
5988 && i
.types
[0].bitfield
.instance
== Accum
5989 && i
.types
[0].bitfield
.dword
5990 && i
.types
[1].bitfield
.instance
== Accum
5991 && i
.types
[1].bitfield
.dword
)
5993 /* xrelease mov %eax, <disp> is another special case. It must not
5994 match the accumulator-only encoding of mov. */
5995 if (flag_code
!= CODE_64BIT
5997 && t
->base_opcode
== 0xa0
5998 && i
.types
[0].bitfield
.instance
== Accum
5999 && (i
.flags
[1] & Operand_Mem
))
6004 if (!(size_match
& MATCH_STRAIGHT
))
6006 /* Reverse direction of operands if swapping is possible in the first
6007 place (operands need to be symmetric) and
6008 - the load form is requested, and the template is a store form,
6009 - the store form is requested, and the template is a load form,
6010 - the non-default (swapped) form is requested. */
6011 overlap1
= operand_type_and (operand_types
[0], operand_types
[1]);
6012 if (t
->opcode_modifier
.d
&& i
.reg_operands
== i
.operands
6013 && !operand_type_all_zero (&overlap1
))
6014 switch (i
.dir_encoding
)
6016 case dir_encoding_load
:
6017 if (operand_type_check (operand_types
[i
.operands
- 1], anymem
)
6018 || t
->opcode_modifier
.regmem
)
6022 case dir_encoding_store
:
6023 if (!operand_type_check (operand_types
[i
.operands
- 1], anymem
)
6024 && !t
->opcode_modifier
.regmem
)
6028 case dir_encoding_swap
:
6031 case dir_encoding_default
:
6034 /* If we want store form, we skip the current load. */
6035 if ((i
.dir_encoding
== dir_encoding_store
6036 || i
.dir_encoding
== dir_encoding_swap
)
6037 && i
.mem_operands
== 0
6038 && t
->opcode_modifier
.load
)
6043 overlap1
= operand_type_and (i
.types
[1], operand_types
[1]);
6044 if (!operand_type_match (overlap0
, i
.types
[0])
6045 || !operand_type_match (overlap1
, i
.types
[1])
6046 || ((check_register
& 3) == 3
6047 && !operand_type_register_match (i
.types
[0],
6052 /* Check if other direction is valid ... */
6053 if (!t
->opcode_modifier
.d
)
6057 if (!(size_match
& MATCH_REVERSE
))
6059 /* Try reversing direction of operands. */
6060 overlap0
= operand_type_and (i
.types
[0], operand_types
[i
.operands
- 1]);
6061 overlap1
= operand_type_and (i
.types
[i
.operands
- 1], operand_types
[0]);
6062 if (!operand_type_match (overlap0
, i
.types
[0])
6063 || !operand_type_match (overlap1
, i
.types
[i
.operands
- 1])
6065 && !operand_type_register_match (i
.types
[0],
6066 operand_types
[i
.operands
- 1],
6067 i
.types
[i
.operands
- 1],
6070 /* Does not match either direction. */
6073 /* found_reverse_match holds which of D or FloatR
6075 if (!t
->opcode_modifier
.d
)
6076 found_reverse_match
= 0;
6077 else if (operand_types
[0].bitfield
.tbyte
)
6078 found_reverse_match
= Opcode_FloatD
;
6079 else if (operand_types
[0].bitfield
.xmmword
6080 || operand_types
[i
.operands
- 1].bitfield
.xmmword
6081 || operand_types
[0].bitfield
.class == RegMMX
6082 || operand_types
[i
.operands
- 1].bitfield
.class == RegMMX
6083 || is_any_vex_encoding(t
))
6084 found_reverse_match
= (t
->base_opcode
& 0xee) != 0x6e
6085 ? Opcode_SIMD_FloatD
: Opcode_SIMD_IntD
;
6087 found_reverse_match
= Opcode_D
;
6088 if (t
->opcode_modifier
.floatr
)
6089 found_reverse_match
|= Opcode_FloatR
;
6093 /* Found a forward 2 operand match here. */
6094 switch (t
->operands
)
6097 overlap4
= operand_type_and (i
.types
[4],
6101 overlap3
= operand_type_and (i
.types
[3],
6105 overlap2
= operand_type_and (i
.types
[2],
6110 switch (t
->operands
)
6113 if (!operand_type_match (overlap4
, i
.types
[4])
6114 || !operand_type_register_match (i
.types
[3],
6121 if (!operand_type_match (overlap3
, i
.types
[3])
6122 || ((check_register
& 0xa) == 0xa
6123 && !operand_type_register_match (i
.types
[1],
6127 || ((check_register
& 0xc) == 0xc
6128 && !operand_type_register_match (i
.types
[2],
6135 /* Here we make use of the fact that there are no
6136 reverse match 3 operand instructions. */
6137 if (!operand_type_match (overlap2
, i
.types
[2])
6138 || ((check_register
& 5) == 5
6139 && !operand_type_register_match (i
.types
[0],
6143 || ((check_register
& 6) == 6
6144 && !operand_type_register_match (i
.types
[1],
6152 /* Found either forward/reverse 2, 3 or 4 operand match here:
6153 slip through to break. */
6156 /* Check if vector and VEX operands are valid. */
6157 if (check_VecOperands (t
) || VEX_check_operands (t
))
6159 specific_error
= i
.error
;
6163 /* We've found a match; break out of loop. */
6167 if (t
== current_templates
->end
)
6169 /* We found no match. */
6170 const char *err_msg
;
6171 switch (specific_error
? specific_error
: i
.error
)
6175 case operand_size_mismatch
:
6176 err_msg
= _("operand size mismatch");
6178 case operand_type_mismatch
:
6179 err_msg
= _("operand type mismatch");
6181 case register_type_mismatch
:
6182 err_msg
= _("register type mismatch");
6184 case number_of_operands_mismatch
:
6185 err_msg
= _("number of operands mismatch");
6187 case invalid_instruction_suffix
:
6188 err_msg
= _("invalid instruction suffix");
6191 err_msg
= _("constant doesn't fit in 4 bits");
6193 case unsupported_with_intel_mnemonic
:
6194 err_msg
= _("unsupported with Intel mnemonic");
6196 case unsupported_syntax
:
6197 err_msg
= _("unsupported syntax");
6200 as_bad (_("unsupported instruction `%s'"),
6201 current_templates
->start
->name
);
6203 case invalid_vsib_address
:
6204 err_msg
= _("invalid VSIB address");
6206 case invalid_vector_register_set
:
6207 err_msg
= _("mask, index, and destination registers must be distinct");
6209 case unsupported_vector_index_register
:
6210 err_msg
= _("unsupported vector index register");
6212 case unsupported_broadcast
:
6213 err_msg
= _("unsupported broadcast");
6215 case broadcast_needed
:
6216 err_msg
= _("broadcast is needed for operand of such type");
6218 case unsupported_masking
:
6219 err_msg
= _("unsupported masking");
6221 case mask_not_on_destination
:
6222 err_msg
= _("mask not on destination operand");
6224 case no_default_mask
:
6225 err_msg
= _("default mask isn't allowed");
6227 case unsupported_rc_sae
:
6228 err_msg
= _("unsupported static rounding/sae");
6230 case rc_sae_operand_not_last_imm
:
6232 err_msg
= _("RC/SAE operand must precede immediate operands");
6234 err_msg
= _("RC/SAE operand must follow immediate operands");
6236 case invalid_register_operand
:
6237 err_msg
= _("invalid register operand");
6240 as_bad (_("%s for `%s'"), err_msg
,
6241 current_templates
->start
->name
);
6245 if (!quiet_warnings
)
6248 && (i
.jumpabsolute
!= (t
->opcode_modifier
.jump
== JUMP_ABSOLUTE
)))
6249 as_warn (_("indirect %s without `*'"), t
->name
);
6251 if (t
->opcode_modifier
.isprefix
6252 && t
->opcode_modifier
.mnemonicsize
== IGNORESIZE
)
6254 /* Warn them that a data or address size prefix doesn't
6255 affect assembly of the next line of code. */
6256 as_warn (_("stand-alone `%s' prefix"), t
->name
);
6260 /* Copy the template we found. */
6263 if (addr_prefix_disp
!= -1)
6264 i
.tm
.operand_types
[addr_prefix_disp
]
6265 = operand_types
[addr_prefix_disp
];
6267 if (found_reverse_match
)
6269 /* If we found a reverse match we must alter the opcode direction
6270 bit and clear/flip the regmem modifier one. found_reverse_match
6271 holds bits to change (different for int & float insns). */
6273 i
.tm
.base_opcode
^= found_reverse_match
;
6275 i
.tm
.operand_types
[0] = operand_types
[i
.operands
- 1];
6276 i
.tm
.operand_types
[i
.operands
- 1] = operand_types
[0];
6278 /* Certain SIMD insns have their load forms specified in the opcode
6279 table, and hence we need to _set_ RegMem instead of clearing it.
6280 We need to avoid setting the bit though on insns like KMOVW. */
6281 i
.tm
.opcode_modifier
.regmem
6282 = i
.tm
.opcode_modifier
.modrm
&& i
.tm
.opcode_modifier
.d
6283 && i
.tm
.operands
> 2U - i
.tm
.opcode_modifier
.sse2avx
6284 && !i
.tm
.opcode_modifier
.regmem
;
6293 unsigned int es_op
= i
.tm
.opcode_modifier
.isstring
- IS_STRING_ES_OP0
;
6294 unsigned int op
= i
.tm
.operand_types
[0].bitfield
.baseindex
? es_op
: 0;
6296 if (i
.seg
[op
] != NULL
&& i
.seg
[op
] != &es
)
6298 as_bad (_("`%s' operand %u must use `%ses' segment"),
6300 intel_syntax
? i
.tm
.operands
- es_op
: es_op
+ 1,
6305 /* There's only ever one segment override allowed per instruction.
6306 This instruction possibly has a legal segment override on the
6307 second operand, so copy the segment to where non-string
6308 instructions store it, allowing common code. */
6309 i
.seg
[op
] = i
.seg
[1];
6315 process_suffix (void)
6317 /* If matched instruction specifies an explicit instruction mnemonic
6319 if (i
.tm
.opcode_modifier
.size
== SIZE16
)
6320 i
.suffix
= WORD_MNEM_SUFFIX
;
6321 else if (i
.tm
.opcode_modifier
.size
== SIZE32
)
6322 i
.suffix
= LONG_MNEM_SUFFIX
;
6323 else if (i
.tm
.opcode_modifier
.size
== SIZE64
)
6324 i
.suffix
= QWORD_MNEM_SUFFIX
;
6325 else if (i
.reg_operands
6326 && (i
.operands
> 1 || i
.types
[0].bitfield
.class == Reg
)
6327 && !i
.tm
.opcode_modifier
.addrprefixopreg
)
6329 unsigned int numop
= i
.operands
;
6331 /* movsx/movzx want only their source operand considered here, for the
6332 ambiguity checking below. The suffix will be replaced afterwards
6333 to represent the destination (register). */
6334 if (((i
.tm
.base_opcode
| 8) == 0xfbe && i
.tm
.opcode_modifier
.w
)
6335 || (i
.tm
.base_opcode
== 0x63 && i
.tm
.cpu_flags
.bitfield
.cpu64
))
6338 /* crc32 needs REX.W set regardless of suffix / source operand size. */
6339 if (i
.tm
.base_opcode
== 0xf20f38f0
6340 && i
.tm
.operand_types
[1].bitfield
.qword
)
6343 /* If there's no instruction mnemonic suffix we try to invent one
6344 based on GPR operands. */
6347 /* We take i.suffix from the last register operand specified,
6348 Destination register type is more significant than source
6349 register type. crc32 in SSE4.2 prefers source register
6351 unsigned int op
= i
.tm
.base_opcode
!= 0xf20f38f0 ? i
.operands
: 1;
6354 if (i
.tm
.operand_types
[op
].bitfield
.instance
== InstanceNone
6355 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
6357 if (i
.types
[op
].bitfield
.class != Reg
)
6359 if (i
.types
[op
].bitfield
.byte
)
6360 i
.suffix
= BYTE_MNEM_SUFFIX
;
6361 else if (i
.types
[op
].bitfield
.word
)
6362 i
.suffix
= WORD_MNEM_SUFFIX
;
6363 else if (i
.types
[op
].bitfield
.dword
)
6364 i
.suffix
= LONG_MNEM_SUFFIX
;
6365 else if (i
.types
[op
].bitfield
.qword
)
6366 i
.suffix
= QWORD_MNEM_SUFFIX
;
6372 /* As an exception, movsx/movzx silently default to a byte source
6374 if ((i
.tm
.base_opcode
| 8) == 0xfbe && i
.tm
.opcode_modifier
.w
6375 && !i
.suffix
&& !intel_syntax
)
6376 i
.suffix
= BYTE_MNEM_SUFFIX
;
6378 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
6381 && i
.tm
.opcode_modifier
.mnemonicsize
== IGNORESIZE
6382 && i
.tm
.opcode_modifier
.no_bsuf
)
6384 else if (!check_byte_reg ())
6387 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
6390 && i
.tm
.opcode_modifier
.mnemonicsize
== IGNORESIZE
6391 && i
.tm
.opcode_modifier
.no_lsuf
6392 && !i
.tm
.opcode_modifier
.todword
6393 && !i
.tm
.opcode_modifier
.toqword
)
6395 else if (!check_long_reg ())
6398 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
6401 && i
.tm
.opcode_modifier
.mnemonicsize
== IGNORESIZE
6402 && i
.tm
.opcode_modifier
.no_qsuf
6403 && !i
.tm
.opcode_modifier
.todword
6404 && !i
.tm
.opcode_modifier
.toqword
)
6406 else if (!check_qword_reg ())
6409 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
6412 && i
.tm
.opcode_modifier
.mnemonicsize
== IGNORESIZE
6413 && i
.tm
.opcode_modifier
.no_wsuf
)
6415 else if (!check_word_reg ())
6418 else if (intel_syntax
6419 && i
.tm
.opcode_modifier
.mnemonicsize
== IGNORESIZE
)
6420 /* Do nothing if the instruction is going to ignore the prefix. */
6425 /* Undo the movsx/movzx change done above. */
6428 else if (i
.tm
.opcode_modifier
.mnemonicsize
== DEFAULTSIZE
6431 i
.suffix
= stackop_size
;
6432 if (stackop_size
== LONG_MNEM_SUFFIX
)
6434 /* stackop_size is set to LONG_MNEM_SUFFIX for the
6435 .code16gcc directive to support 16-bit mode with
6436 32-bit address. For IRET without a suffix, generate
6437 16-bit IRET (opcode 0xcf) to return from an interrupt
6439 if (i
.tm
.base_opcode
== 0xcf)
6441 i
.suffix
= WORD_MNEM_SUFFIX
;
6442 as_warn (_("generating 16-bit `iret' for .code16gcc directive"));
6444 /* Warn about changed behavior for segment register push/pop. */
6445 else if ((i
.tm
.base_opcode
| 1) == 0x07)
6446 as_warn (_("generating 32-bit `%s', unlike earlier gas versions"),
6451 && (i
.tm
.opcode_modifier
.jump
== JUMP_ABSOLUTE
6452 || i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
6453 || i
.tm
.opcode_modifier
.jump
== JUMP_INTERSEGMENT
6454 || (i
.tm
.base_opcode
== 0x0f01 /* [ls][gi]dt */
6455 && i
.tm
.extension_opcode
<= 3)))
6460 if (!i
.tm
.opcode_modifier
.no_qsuf
)
6462 i
.suffix
= QWORD_MNEM_SUFFIX
;
6467 if (!i
.tm
.opcode_modifier
.no_lsuf
)
6468 i
.suffix
= LONG_MNEM_SUFFIX
;
6471 if (!i
.tm
.opcode_modifier
.no_wsuf
)
6472 i
.suffix
= WORD_MNEM_SUFFIX
;
6478 && (i
.tm
.opcode_modifier
.mnemonicsize
!= DEFAULTSIZE
6479 /* Also cover lret/retf/iret in 64-bit mode. */
6480 || (flag_code
== CODE_64BIT
6481 && !i
.tm
.opcode_modifier
.no_lsuf
6482 && !i
.tm
.opcode_modifier
.no_qsuf
))
6483 && i
.tm
.opcode_modifier
.mnemonicsize
!= IGNORESIZE
6484 /* Accept FLDENV et al without suffix. */
6485 && (i
.tm
.opcode_modifier
.no_ssuf
|| i
.tm
.opcode_modifier
.floatmf
))
6487 unsigned int suffixes
, evex
= 0;
6489 suffixes
= !i
.tm
.opcode_modifier
.no_bsuf
;
6490 if (!i
.tm
.opcode_modifier
.no_wsuf
)
6492 if (!i
.tm
.opcode_modifier
.no_lsuf
)
6494 if (!i
.tm
.opcode_modifier
.no_ldsuf
)
6496 if (!i
.tm
.opcode_modifier
.no_ssuf
)
6498 if (flag_code
== CODE_64BIT
&& !i
.tm
.opcode_modifier
.no_qsuf
)
6501 /* For [XYZ]MMWORD operands inspect operand sizes. While generally
6502 also suitable for AT&T syntax mode, it was requested that this be
6503 restricted to just Intel syntax. */
6504 if (intel_syntax
&& is_any_vex_encoding (&i
.tm
) && !i
.broadcast
)
6508 for (op
= 0; op
< i
.tm
.operands
; ++op
)
6510 if (is_evex_encoding (&i
.tm
)
6511 && !cpu_arch_flags
.bitfield
.cpuavx512vl
)
6513 if (i
.tm
.operand_types
[op
].bitfield
.ymmword
)
6514 i
.tm
.operand_types
[op
].bitfield
.xmmword
= 0;
6515 if (i
.tm
.operand_types
[op
].bitfield
.zmmword
)
6516 i
.tm
.operand_types
[op
].bitfield
.ymmword
= 0;
6517 if (!i
.tm
.opcode_modifier
.evex
6518 || i
.tm
.opcode_modifier
.evex
== EVEXDYN
)
6519 i
.tm
.opcode_modifier
.evex
= EVEX512
;
6522 if (i
.tm
.operand_types
[op
].bitfield
.xmmword
6523 + i
.tm
.operand_types
[op
].bitfield
.ymmword
6524 + i
.tm
.operand_types
[op
].bitfield
.zmmword
< 2)
6527 /* Any properly sized operand disambiguates the insn. */
6528 if (i
.types
[op
].bitfield
.xmmword
6529 || i
.types
[op
].bitfield
.ymmword
6530 || i
.types
[op
].bitfield
.zmmword
)
6532 suffixes
&= ~(7 << 6);
6537 if ((i
.flags
[op
] & Operand_Mem
)
6538 && i
.tm
.operand_types
[op
].bitfield
.unspecified
)
6540 if (i
.tm
.operand_types
[op
].bitfield
.xmmword
)
6542 if (i
.tm
.operand_types
[op
].bitfield
.ymmword
)
6544 if (i
.tm
.operand_types
[op
].bitfield
.zmmword
)
6546 if (is_evex_encoding (&i
.tm
))
6552 /* Are multiple suffixes / operand sizes allowed? */
6553 if (suffixes
& (suffixes
- 1))
6556 && (i
.tm
.opcode_modifier
.mnemonicsize
!= DEFAULTSIZE
6557 || operand_check
== check_error
))
6559 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
6562 if (operand_check
== check_error
)
6564 as_bad (_("no instruction mnemonic suffix given and "
6565 "no register operands; can't size `%s'"), i
.tm
.name
);
6568 if (operand_check
== check_warning
)
6569 as_warn (_("%s; using default for `%s'"),
6571 ? _("ambiguous operand size")
6572 : _("no instruction mnemonic suffix given and "
6573 "no register operands"),
6576 if (i
.tm
.opcode_modifier
.floatmf
)
6577 i
.suffix
= SHORT_MNEM_SUFFIX
;
6578 else if ((i
.tm
.base_opcode
| 8) == 0xfbe
6579 || (i
.tm
.base_opcode
== 0x63
6580 && i
.tm
.cpu_flags
.bitfield
.cpu64
))
6581 /* handled below */;
6583 i
.tm
.opcode_modifier
.evex
= evex
;
6584 else if (flag_code
== CODE_16BIT
)
6585 i
.suffix
= WORD_MNEM_SUFFIX
;
6586 else if (!i
.tm
.opcode_modifier
.no_lsuf
)
6587 i
.suffix
= LONG_MNEM_SUFFIX
;
6589 i
.suffix
= QWORD_MNEM_SUFFIX
;
6593 if ((i
.tm
.base_opcode
| 8) == 0xfbe
6594 || (i
.tm
.base_opcode
== 0x63 && i
.tm
.cpu_flags
.bitfield
.cpu64
))
6596 /* In Intel syntax, movsx/movzx must have a "suffix" (checked above).
6597 In AT&T syntax, if there is no suffix (warned about above), the default
6598 will be byte extension. */
6599 if (i
.tm
.opcode_modifier
.w
&& i
.suffix
&& i
.suffix
!= BYTE_MNEM_SUFFIX
)
6600 i
.tm
.base_opcode
|= 1;
6602 /* For further processing, the suffix should represent the destination
6603 (register). This is already the case when one was used with
6604 mov[sz][bw]*, but we need to replace it for mov[sz]x, or if there was
6605 no suffix to begin with. */
6606 if (i
.tm
.opcode_modifier
.w
|| i
.tm
.base_opcode
== 0x63 || !i
.suffix
)
6608 if (i
.types
[1].bitfield
.word
)
6609 i
.suffix
= WORD_MNEM_SUFFIX
;
6610 else if (i
.types
[1].bitfield
.qword
)
6611 i
.suffix
= QWORD_MNEM_SUFFIX
;
6613 i
.suffix
= LONG_MNEM_SUFFIX
;
6615 i
.tm
.opcode_modifier
.w
= 0;
6619 if (!i
.tm
.opcode_modifier
.modrm
&& i
.reg_operands
&& i
.tm
.operands
< 3)
6620 i
.short_form
= (i
.tm
.operand_types
[0].bitfield
.class == Reg
)
6621 != (i
.tm
.operand_types
[1].bitfield
.class == Reg
);
6623 /* Change the opcode based on the operand size given by i.suffix. */
6626 /* Size floating point instruction. */
6627 case LONG_MNEM_SUFFIX
:
6628 if (i
.tm
.opcode_modifier
.floatmf
)
6630 i
.tm
.base_opcode
^= 4;
6634 case WORD_MNEM_SUFFIX
:
6635 case QWORD_MNEM_SUFFIX
:
6636 /* It's not a byte, select word/dword operation. */
6637 if (i
.tm
.opcode_modifier
.w
)
6640 i
.tm
.base_opcode
|= 8;
6642 i
.tm
.base_opcode
|= 1;
6645 case SHORT_MNEM_SUFFIX
:
6646 /* Now select between word & dword operations via the operand
6647 size prefix, except for instructions that will ignore this
6649 if (i
.suffix
!= QWORD_MNEM_SUFFIX
6650 && i
.tm
.opcode_modifier
.mnemonicsize
!= IGNORESIZE
6651 && !i
.tm
.opcode_modifier
.floatmf
6652 && !is_any_vex_encoding (&i
.tm
)
6653 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
6654 || (flag_code
== CODE_64BIT
6655 && i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
)))
6657 unsigned int prefix
= DATA_PREFIX_OPCODE
;
6659 if (i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
) /* jcxz, loop */
6660 prefix
= ADDR_PREFIX_OPCODE
;
6662 if (!add_prefix (prefix
))
6666 /* Set mode64 for an operand. */
6667 if (i
.suffix
== QWORD_MNEM_SUFFIX
6668 && flag_code
== CODE_64BIT
6669 && !i
.tm
.opcode_modifier
.norex64
6670 && !i
.tm
.opcode_modifier
.vexw
6671 /* Special case for xchg %rax,%rax. It is NOP and doesn't
6673 && ! (i
.operands
== 2
6674 && i
.tm
.base_opcode
== 0x90
6675 && i
.tm
.extension_opcode
== None
6676 && i
.types
[0].bitfield
.instance
== Accum
6677 && i
.types
[0].bitfield
.qword
6678 && i
.types
[1].bitfield
.instance
== Accum
6679 && i
.types
[1].bitfield
.qword
))
6685 if (i
.tm
.opcode_modifier
.addrprefixopreg
)
6687 gas_assert (!i
.suffix
);
6688 gas_assert (i
.reg_operands
);
6690 if (i
.tm
.operand_types
[0].bitfield
.instance
== Accum
6693 /* The address size override prefix changes the size of the
6695 if (flag_code
== CODE_64BIT
6696 && i
.op
[0].regs
->reg_type
.bitfield
.word
)
6698 as_bad (_("16-bit addressing unavailable for `%s'"),
6703 if ((flag_code
== CODE_32BIT
6704 ? i
.op
[0].regs
->reg_type
.bitfield
.word
6705 : i
.op
[0].regs
->reg_type
.bitfield
.dword
)
6706 && !add_prefix (ADDR_PREFIX_OPCODE
))
6711 /* Check invalid register operand when the address size override
6712 prefix changes the size of register operands. */
6714 enum { need_word
, need_dword
, need_qword
} need
;
6716 if (flag_code
== CODE_32BIT
)
6717 need
= i
.prefix
[ADDR_PREFIX
] ? need_word
: need_dword
;
6718 else if (i
.prefix
[ADDR_PREFIX
])
6721 need
= flag_code
== CODE_64BIT
? need_qword
: need_word
;
6723 for (op
= 0; op
< i
.operands
; op
++)
6725 if (i
.types
[op
].bitfield
.class != Reg
)
6731 if (i
.op
[op
].regs
->reg_type
.bitfield
.word
)
6735 if (i
.op
[op
].regs
->reg_type
.bitfield
.dword
)
6739 if (i
.op
[op
].regs
->reg_type
.bitfield
.qword
)
6744 as_bad (_("invalid register operand size for `%s'"),
6755 check_byte_reg (void)
6759 for (op
= i
.operands
; --op
>= 0;)
6761 /* Skip non-register operands. */
6762 if (i
.types
[op
].bitfield
.class != Reg
)
6765 /* If this is an eight bit register, it's OK. If it's the 16 or
6766 32 bit version of an eight bit register, we will just use the
6767 low portion, and that's OK too. */
6768 if (i
.types
[op
].bitfield
.byte
)
6771 /* I/O port address operands are OK too. */
6772 if (i
.tm
.operand_types
[op
].bitfield
.instance
== RegD
6773 && i
.tm
.operand_types
[op
].bitfield
.word
)
6776 /* crc32 only wants its source operand checked here. */
6777 if (i
.tm
.base_opcode
== 0xf20f38f0 && op
)
6780 /* Any other register is bad. */
6781 if (i
.types
[op
].bitfield
.class == Reg
6782 || i
.types
[op
].bitfield
.class == RegMMX
6783 || i
.types
[op
].bitfield
.class == RegSIMD
6784 || i
.types
[op
].bitfield
.class == SReg
6785 || i
.types
[op
].bitfield
.class == RegCR
6786 || i
.types
[op
].bitfield
.class == RegDR
6787 || i
.types
[op
].bitfield
.class == RegTR
)
6789 as_bad (_("`%s%s' not allowed with `%s%c'"),
6791 i
.op
[op
].regs
->reg_name
,
6801 check_long_reg (void)
6805 for (op
= i
.operands
; --op
>= 0;)
6806 /* Skip non-register operands. */
6807 if (i
.types
[op
].bitfield
.class != Reg
)
6809 /* Reject eight bit registers, except where the template requires
6810 them. (eg. movzb) */
6811 else if (i
.types
[op
].bitfield
.byte
6812 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
6813 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
6814 && (i
.tm
.operand_types
[op
].bitfield
.word
6815 || i
.tm
.operand_types
[op
].bitfield
.dword
))
6817 as_bad (_("`%s%s' not allowed with `%s%c'"),
6819 i
.op
[op
].regs
->reg_name
,
6824 /* Error if the e prefix on a general reg is missing. */
6825 else if (i
.types
[op
].bitfield
.word
6826 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
6827 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
6828 && i
.tm
.operand_types
[op
].bitfield
.dword
)
6830 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6831 register_prefix
, i
.op
[op
].regs
->reg_name
,
6835 /* Warn if the r prefix on a general reg is present. */
6836 else if (i
.types
[op
].bitfield
.qword
6837 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
6838 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
6839 && i
.tm
.operand_types
[op
].bitfield
.dword
)
6842 && i
.tm
.opcode_modifier
.toqword
6843 && i
.types
[0].bitfield
.class != RegSIMD
)
6845 /* Convert to QWORD. We want REX byte. */
6846 i
.suffix
= QWORD_MNEM_SUFFIX
;
6850 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6851 register_prefix
, i
.op
[op
].regs
->reg_name
,
6860 check_qword_reg (void)
6864 for (op
= i
.operands
; --op
>= 0; )
6865 /* Skip non-register operands. */
6866 if (i
.types
[op
].bitfield
.class != Reg
)
6868 /* Reject eight bit registers, except where the template requires
6869 them. (eg. movzb) */
6870 else if (i
.types
[op
].bitfield
.byte
6871 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
6872 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
6873 && (i
.tm
.operand_types
[op
].bitfield
.word
6874 || i
.tm
.operand_types
[op
].bitfield
.dword
))
6876 as_bad (_("`%s%s' not allowed with `%s%c'"),
6878 i
.op
[op
].regs
->reg_name
,
6883 /* Warn if the r prefix on a general reg is missing. */
6884 else if ((i
.types
[op
].bitfield
.word
6885 || i
.types
[op
].bitfield
.dword
)
6886 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
6887 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
6888 && i
.tm
.operand_types
[op
].bitfield
.qword
)
6890 /* Prohibit these changes in the 64bit mode, since the
6891 lowering is more complicated. */
6893 && i
.tm
.opcode_modifier
.todword
6894 && i
.types
[0].bitfield
.class != RegSIMD
)
6896 /* Convert to DWORD. We don't want REX byte. */
6897 i
.suffix
= LONG_MNEM_SUFFIX
;
6901 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6902 register_prefix
, i
.op
[op
].regs
->reg_name
,
6911 check_word_reg (void)
6914 for (op
= i
.operands
; --op
>= 0;)
6915 /* Skip non-register operands. */
6916 if (i
.types
[op
].bitfield
.class != Reg
)
6918 /* Reject eight bit registers, except where the template requires
6919 them. (eg. movzb) */
6920 else if (i
.types
[op
].bitfield
.byte
6921 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
6922 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
6923 && (i
.tm
.operand_types
[op
].bitfield
.word
6924 || i
.tm
.operand_types
[op
].bitfield
.dword
))
6926 as_bad (_("`%s%s' not allowed with `%s%c'"),
6928 i
.op
[op
].regs
->reg_name
,
6933 /* Error if the e or r prefix on a general reg is present. */
6934 else if ((i
.types
[op
].bitfield
.dword
6935 || i
.types
[op
].bitfield
.qword
)
6936 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
6937 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
6938 && i
.tm
.operand_types
[op
].bitfield
.word
)
6940 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6941 register_prefix
, i
.op
[op
].regs
->reg_name
,
6949 update_imm (unsigned int j
)
6951 i386_operand_type overlap
= i
.types
[j
];
6952 if ((overlap
.bitfield
.imm8
6953 || overlap
.bitfield
.imm8s
6954 || overlap
.bitfield
.imm16
6955 || overlap
.bitfield
.imm32
6956 || overlap
.bitfield
.imm32s
6957 || overlap
.bitfield
.imm64
)
6958 && !operand_type_equal (&overlap
, &imm8
)
6959 && !operand_type_equal (&overlap
, &imm8s
)
6960 && !operand_type_equal (&overlap
, &imm16
)
6961 && !operand_type_equal (&overlap
, &imm32
)
6962 && !operand_type_equal (&overlap
, &imm32s
)
6963 && !operand_type_equal (&overlap
, &imm64
))
6967 i386_operand_type temp
;
6969 operand_type_set (&temp
, 0);
6970 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
6972 temp
.bitfield
.imm8
= overlap
.bitfield
.imm8
;
6973 temp
.bitfield
.imm8s
= overlap
.bitfield
.imm8s
;
6975 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
6976 temp
.bitfield
.imm16
= overlap
.bitfield
.imm16
;
6977 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
6979 temp
.bitfield
.imm64
= overlap
.bitfield
.imm64
;
6980 temp
.bitfield
.imm32s
= overlap
.bitfield
.imm32s
;
6983 temp
.bitfield
.imm32
= overlap
.bitfield
.imm32
;
6986 else if (operand_type_equal (&overlap
, &imm16_32_32s
)
6987 || operand_type_equal (&overlap
, &imm16_32
)
6988 || operand_type_equal (&overlap
, &imm16_32s
))
6990 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
6995 if (!operand_type_equal (&overlap
, &imm8
)
6996 && !operand_type_equal (&overlap
, &imm8s
)
6997 && !operand_type_equal (&overlap
, &imm16
)
6998 && !operand_type_equal (&overlap
, &imm32
)
6999 && !operand_type_equal (&overlap
, &imm32s
)
7000 && !operand_type_equal (&overlap
, &imm64
))
7002 as_bad (_("no instruction mnemonic suffix given; "
7003 "can't determine immediate size"));
7007 i
.types
[j
] = overlap
;
7017 /* Update the first 2 immediate operands. */
7018 n
= i
.operands
> 2 ? 2 : i
.operands
;
7021 for (j
= 0; j
< n
; j
++)
7022 if (update_imm (j
) == 0)
7025 /* The 3rd operand can't be immediate operand. */
7026 gas_assert (operand_type_check (i
.types
[2], imm
) == 0);
7033 process_operands (void)
7035 /* Default segment register this instruction will use for memory
7036 accesses. 0 means unknown. This is only for optimizing out
7037 unnecessary segment overrides. */
7038 const seg_entry
*default_seg
= 0;
7040 if (i
.tm
.opcode_modifier
.sse2avx
&& i
.tm
.opcode_modifier
.vexvvvv
)
7042 unsigned int dupl
= i
.operands
;
7043 unsigned int dest
= dupl
- 1;
7046 /* The destination must be an xmm register. */
7047 gas_assert (i
.reg_operands
7048 && MAX_OPERANDS
> dupl
7049 && operand_type_equal (&i
.types
[dest
], ®xmm
));
7051 if (i
.tm
.operand_types
[0].bitfield
.instance
== Accum
7052 && i
.tm
.operand_types
[0].bitfield
.xmmword
)
7054 if (i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
)
7056 /* Keep xmm0 for instructions with VEX prefix and 3
7058 i
.tm
.operand_types
[0].bitfield
.instance
= InstanceNone
;
7059 i
.tm
.operand_types
[0].bitfield
.class = RegSIMD
;
7064 /* We remove the first xmm0 and keep the number of
7065 operands unchanged, which in fact duplicates the
7067 for (j
= 1; j
< i
.operands
; j
++)
7069 i
.op
[j
- 1] = i
.op
[j
];
7070 i
.types
[j
- 1] = i
.types
[j
];
7071 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
7072 i
.flags
[j
- 1] = i
.flags
[j
];
7076 else if (i
.tm
.opcode_modifier
.implicit1stxmm0
)
7078 gas_assert ((MAX_OPERANDS
- 1) > dupl
7079 && (i
.tm
.opcode_modifier
.vexsources
7082 /* Add the implicit xmm0 for instructions with VEX prefix
7084 for (j
= i
.operands
; j
> 0; j
--)
7086 i
.op
[j
] = i
.op
[j
- 1];
7087 i
.types
[j
] = i
.types
[j
- 1];
7088 i
.tm
.operand_types
[j
] = i
.tm
.operand_types
[j
- 1];
7089 i
.flags
[j
] = i
.flags
[j
- 1];
7092 = (const reg_entry
*) hash_find (reg_hash
, "xmm0");
7093 i
.types
[0] = regxmm
;
7094 i
.tm
.operand_types
[0] = regxmm
;
7097 i
.reg_operands
+= 2;
7102 i
.op
[dupl
] = i
.op
[dest
];
7103 i
.types
[dupl
] = i
.types
[dest
];
7104 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
7105 i
.flags
[dupl
] = i
.flags
[dest
];
7114 i
.op
[dupl
] = i
.op
[dest
];
7115 i
.types
[dupl
] = i
.types
[dest
];
7116 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
7117 i
.flags
[dupl
] = i
.flags
[dest
];
7120 if (i
.tm
.opcode_modifier
.immext
)
7123 else if (i
.tm
.operand_types
[0].bitfield
.instance
== Accum
7124 && i
.tm
.operand_types
[0].bitfield
.xmmword
)
7128 for (j
= 1; j
< i
.operands
; j
++)
7130 i
.op
[j
- 1] = i
.op
[j
];
7131 i
.types
[j
- 1] = i
.types
[j
];
7133 /* We need to adjust fields in i.tm since they are used by
7134 build_modrm_byte. */
7135 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
7137 i
.flags
[j
- 1] = i
.flags
[j
];
7144 else if (i
.tm
.opcode_modifier
.implicitquadgroup
)
7146 unsigned int regnum
, first_reg_in_group
, last_reg_in_group
;
7148 /* The second operand must be {x,y,z}mmN, where N is a multiple of 4. */
7149 gas_assert (i
.operands
>= 2 && i
.types
[1].bitfield
.class == RegSIMD
);
7150 regnum
= register_number (i
.op
[1].regs
);
7151 first_reg_in_group
= regnum
& ~3;
7152 last_reg_in_group
= first_reg_in_group
+ 3;
7153 if (regnum
!= first_reg_in_group
)
7154 as_warn (_("source register `%s%s' implicitly denotes"
7155 " `%s%.3s%u' to `%s%.3s%u' source group in `%s'"),
7156 register_prefix
, i
.op
[1].regs
->reg_name
,
7157 register_prefix
, i
.op
[1].regs
->reg_name
, first_reg_in_group
,
7158 register_prefix
, i
.op
[1].regs
->reg_name
, last_reg_in_group
,
7161 else if (i
.tm
.opcode_modifier
.regkludge
)
7163 /* The imul $imm, %reg instruction is converted into
7164 imul $imm, %reg, %reg, and the clr %reg instruction
7165 is converted into xor %reg, %reg. */
7167 unsigned int first_reg_op
;
7169 if (operand_type_check (i
.types
[0], reg
))
7173 /* Pretend we saw the extra register operand. */
7174 gas_assert (i
.reg_operands
== 1
7175 && i
.op
[first_reg_op
+ 1].regs
== 0);
7176 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
7177 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
7182 if (i
.tm
.opcode_modifier
.modrm
)
7184 /* The opcode is completed (modulo i.tm.extension_opcode which
7185 must be put into the modrm byte). Now, we make the modrm and
7186 index base bytes based on all the info we've collected. */
7188 default_seg
= build_modrm_byte ();
7190 else if (i
.types
[0].bitfield
.class == SReg
)
7192 if (flag_code
!= CODE_64BIT
7193 ? i
.tm
.base_opcode
== POP_SEG_SHORT
7194 && i
.op
[0].regs
->reg_num
== 1
7195 : (i
.tm
.base_opcode
| 1) == POP_SEG386_SHORT
7196 && i
.op
[0].regs
->reg_num
< 4)
7198 as_bad (_("you can't `%s %s%s'"),
7199 i
.tm
.name
, register_prefix
, i
.op
[0].regs
->reg_name
);
7202 if ( i
.op
[0].regs
->reg_num
> 3 && i
.tm
.opcode_length
== 1 )
7204 i
.tm
.base_opcode
^= POP_SEG_SHORT
^ POP_SEG386_SHORT
;
7205 i
.tm
.opcode_length
= 2;
7207 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
7209 else if ((i
.tm
.base_opcode
& ~0x3) == MOV_AX_DISP32
)
7213 else if (i
.tm
.opcode_modifier
.isstring
)
7215 /* For the string instructions that allow a segment override
7216 on one of their operands, the default segment is ds. */
7219 else if (i
.short_form
)
7221 /* The register or float register operand is in operand
7223 unsigned int op
= i
.tm
.operand_types
[0].bitfield
.class != Reg
;
7225 /* Register goes in low 3 bits of opcode. */
7226 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
7227 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
7229 if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
7231 /* Warn about some common errors, but press on regardless.
7232 The first case can be generated by gcc (<= 2.8.1). */
7233 if (i
.operands
== 2)
7235 /* Reversed arguments on faddp, fsubp, etc. */
7236 as_warn (_("translating to `%s %s%s,%s%s'"), i
.tm
.name
,
7237 register_prefix
, i
.op
[!intel_syntax
].regs
->reg_name
,
7238 register_prefix
, i
.op
[intel_syntax
].regs
->reg_name
);
7242 /* Extraneous `l' suffix on fp insn. */
7243 as_warn (_("translating to `%s %s%s'"), i
.tm
.name
,
7244 register_prefix
, i
.op
[0].regs
->reg_name
);
7249 if ((i
.seg
[0] || i
.prefix
[SEG_PREFIX
])
7250 && i
.tm
.base_opcode
== 0x8d /* lea */
7251 && !is_any_vex_encoding(&i
.tm
))
7253 if (!quiet_warnings
)
7254 as_warn (_("segment override on `%s' is ineffectual"), i
.tm
.name
);
7258 i
.prefix
[SEG_PREFIX
] = 0;
7262 /* If a segment was explicitly specified, and the specified segment
7263 is neither the default nor the one already recorded from a prefix,
7264 use an opcode prefix to select it. If we never figured out what
7265 the default segment is, then default_seg will be zero at this
7266 point, and the specified segment prefix will always be used. */
7268 && i
.seg
[0] != default_seg
7269 && i
.seg
[0]->seg_prefix
!= i
.prefix
[SEG_PREFIX
])
7271 if (!add_prefix (i
.seg
[0]->seg_prefix
))
7277 static const seg_entry
*
7278 build_modrm_byte (void)
7280 const seg_entry
*default_seg
= 0;
7281 unsigned int source
, dest
;
7284 vex_3_sources
= i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
;
7287 unsigned int nds
, reg_slot
;
7290 dest
= i
.operands
- 1;
7293 /* There are 2 kinds of instructions:
7294 1. 5 operands: 4 register operands or 3 register operands
7295 plus 1 memory operand plus one Imm4 operand, VexXDS, and
7296 VexW0 or VexW1. The destination must be either XMM, YMM or
7298 2. 4 operands: 4 register operands or 3 register operands
7299 plus 1 memory operand, with VexXDS. */
7300 gas_assert ((i
.reg_operands
== 4
7301 || (i
.reg_operands
== 3 && i
.mem_operands
== 1))
7302 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
7303 && i
.tm
.opcode_modifier
.vexw
7304 && i
.tm
.operand_types
[dest
].bitfield
.class == RegSIMD
);
7306 /* If VexW1 is set, the first non-immediate operand is the source and
7307 the second non-immediate one is encoded in the immediate operand. */
7308 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
7310 source
= i
.imm_operands
;
7311 reg_slot
= i
.imm_operands
+ 1;
7315 source
= i
.imm_operands
+ 1;
7316 reg_slot
= i
.imm_operands
;
7319 if (i
.imm_operands
== 0)
7321 /* When there is no immediate operand, generate an 8bit
7322 immediate operand to encode the first operand. */
7323 exp
= &im_expressions
[i
.imm_operands
++];
7324 i
.op
[i
.operands
].imms
= exp
;
7325 i
.types
[i
.operands
] = imm8
;
7328 gas_assert (i
.tm
.operand_types
[reg_slot
].bitfield
.class == RegSIMD
);
7329 exp
->X_op
= O_constant
;
7330 exp
->X_add_number
= register_number (i
.op
[reg_slot
].regs
) << 4;
7331 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
7335 gas_assert (i
.imm_operands
== 1);
7336 gas_assert (fits_in_imm4 (i
.op
[0].imms
->X_add_number
));
7337 gas_assert (!i
.tm
.opcode_modifier
.immext
);
7339 /* Turn on Imm8 again so that output_imm will generate it. */
7340 i
.types
[0].bitfield
.imm8
= 1;
7342 gas_assert (i
.tm
.operand_types
[reg_slot
].bitfield
.class == RegSIMD
);
7343 i
.op
[0].imms
->X_add_number
7344 |= register_number (i
.op
[reg_slot
].regs
) << 4;
7345 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
7348 gas_assert (i
.tm
.operand_types
[nds
].bitfield
.class == RegSIMD
);
7349 i
.vex
.register_specifier
= i
.op
[nds
].regs
;
7354 /* i.reg_operands MUST be the number of real register operands;
7355 implicit registers do not count. If there are 3 register
7356 operands, it must be a instruction with VexNDS. For a
7357 instruction with VexNDD, the destination register is encoded
7358 in VEX prefix. If there are 4 register operands, it must be
7359 a instruction with VEX prefix and 3 sources. */
7360 if (i
.mem_operands
== 0
7361 && ((i
.reg_operands
== 2
7362 && i
.tm
.opcode_modifier
.vexvvvv
<= VEXXDS
)
7363 || (i
.reg_operands
== 3
7364 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
7365 || (i
.reg_operands
== 4 && vex_3_sources
)))
7373 /* When there are 3 operands, one of them may be immediate,
7374 which may be the first or the last operand. Otherwise,
7375 the first operand must be shift count register (cl) or it
7376 is an instruction with VexNDS. */
7377 gas_assert (i
.imm_operands
== 1
7378 || (i
.imm_operands
== 0
7379 && (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
7380 || (i
.types
[0].bitfield
.instance
== RegC
7381 && i
.types
[0].bitfield
.byte
))));
7382 if (operand_type_check (i
.types
[0], imm
)
7383 || (i
.types
[0].bitfield
.instance
== RegC
7384 && i
.types
[0].bitfield
.byte
))
7390 /* When there are 4 operands, the first two must be 8bit
7391 immediate operands. The source operand will be the 3rd
7394 For instructions with VexNDS, if the first operand
7395 an imm8, the source operand is the 2nd one. If the last
7396 operand is imm8, the source operand is the first one. */
7397 gas_assert ((i
.imm_operands
== 2
7398 && i
.types
[0].bitfield
.imm8
7399 && i
.types
[1].bitfield
.imm8
)
7400 || (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
7401 && i
.imm_operands
== 1
7402 && (i
.types
[0].bitfield
.imm8
7403 || i
.types
[i
.operands
- 1].bitfield
.imm8
7405 if (i
.imm_operands
== 2)
7409 if (i
.types
[0].bitfield
.imm8
)
7416 if (is_evex_encoding (&i
.tm
))
7418 /* For EVEX instructions, when there are 5 operands, the
7419 first one must be immediate operand. If the second one
7420 is immediate operand, the source operand is the 3th
7421 one. If the last one is immediate operand, the source
7422 operand is the 2nd one. */
7423 gas_assert (i
.imm_operands
== 2
7424 && i
.tm
.opcode_modifier
.sae
7425 && operand_type_check (i
.types
[0], imm
));
7426 if (operand_type_check (i
.types
[1], imm
))
7428 else if (operand_type_check (i
.types
[4], imm
))
7442 /* RC/SAE operand could be between DEST and SRC. That happens
7443 when one operand is GPR and the other one is XMM/YMM/ZMM
7445 if (i
.rounding
&& i
.rounding
->operand
== (int) dest
)
7448 if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
7450 /* For instructions with VexNDS, the register-only source
7451 operand must be a 32/64bit integer, XMM, YMM, ZMM, or mask
7452 register. It is encoded in VEX prefix. */
7454 i386_operand_type op
;
7457 /* Check register-only source operand when two source
7458 operands are swapped. */
7459 if (!i
.tm
.operand_types
[source
].bitfield
.baseindex
7460 && i
.tm
.operand_types
[dest
].bitfield
.baseindex
)
7468 op
= i
.tm
.operand_types
[vvvv
];
7469 if ((dest
+ 1) >= i
.operands
7470 || ((op
.bitfield
.class != Reg
7471 || (!op
.bitfield
.dword
&& !op
.bitfield
.qword
))
7472 && op
.bitfield
.class != RegSIMD
7473 && !operand_type_equal (&op
, ®mask
)))
7475 i
.vex
.register_specifier
= i
.op
[vvvv
].regs
;
7481 /* One of the register operands will be encoded in the i.rm.reg
7482 field, the other in the combined i.rm.mode and i.rm.regmem
7483 fields. If no form of this instruction supports a memory
7484 destination operand, then we assume the source operand may
7485 sometimes be a memory operand and so we need to store the
7486 destination in the i.rm.reg field. */
7487 if (!i
.tm
.opcode_modifier
.regmem
7488 && operand_type_check (i
.tm
.operand_types
[dest
], anymem
) == 0)
7490 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
7491 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
7492 if (i
.op
[dest
].regs
->reg_type
.bitfield
.class == RegMMX
7493 || i
.op
[source
].regs
->reg_type
.bitfield
.class == RegMMX
)
7494 i
.has_regmmx
= TRUE
;
7495 else if (i
.op
[dest
].regs
->reg_type
.bitfield
.class == RegSIMD
7496 || i
.op
[source
].regs
->reg_type
.bitfield
.class == RegSIMD
)
7498 if (i
.types
[dest
].bitfield
.zmmword
7499 || i
.types
[source
].bitfield
.zmmword
)
7500 i
.has_regzmm
= TRUE
;
7501 else if (i
.types
[dest
].bitfield
.ymmword
7502 || i
.types
[source
].bitfield
.ymmword
)
7503 i
.has_regymm
= TRUE
;
7505 i
.has_regxmm
= TRUE
;
7507 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
7509 if ((i
.op
[dest
].regs
->reg_flags
& RegVRex
) != 0)
7511 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
7513 if ((i
.op
[source
].regs
->reg_flags
& RegVRex
) != 0)
7518 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
7519 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
7520 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
7522 if ((i
.op
[dest
].regs
->reg_flags
& RegVRex
) != 0)
7524 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
7526 if ((i
.op
[source
].regs
->reg_flags
& RegVRex
) != 0)
7529 if (flag_code
!= CODE_64BIT
&& (i
.rex
& REX_R
))
7531 if (i
.types
[!i
.tm
.opcode_modifier
.regmem
].bitfield
.class != RegCR
)
7534 add_prefix (LOCK_PREFIX_OPCODE
);
7538 { /* If it's not 2 reg operands... */
7543 unsigned int fake_zero_displacement
= 0;
7546 for (op
= 0; op
< i
.operands
; op
++)
7547 if (i
.flags
[op
] & Operand_Mem
)
7549 gas_assert (op
< i
.operands
);
7551 if (i
.tm
.opcode_modifier
.vecsib
)
7553 if (i
.index_reg
->reg_num
== RegIZ
)
7556 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
7559 i
.sib
.base
= NO_BASE_REGISTER
;
7560 i
.sib
.scale
= i
.log2_scale_factor
;
7561 i
.types
[op
].bitfield
.disp8
= 0;
7562 i
.types
[op
].bitfield
.disp16
= 0;
7563 i
.types
[op
].bitfield
.disp64
= 0;
7564 if (flag_code
!= CODE_64BIT
|| i
.prefix
[ADDR_PREFIX
])
7566 /* Must be 32 bit */
7567 i
.types
[op
].bitfield
.disp32
= 1;
7568 i
.types
[op
].bitfield
.disp32s
= 0;
7572 i
.types
[op
].bitfield
.disp32
= 0;
7573 i
.types
[op
].bitfield
.disp32s
= 1;
7576 i
.sib
.index
= i
.index_reg
->reg_num
;
7577 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
7579 if ((i
.index_reg
->reg_flags
& RegVRex
) != 0)
7585 if (i
.base_reg
== 0)
7588 if (!i
.disp_operands
)
7589 fake_zero_displacement
= 1;
7590 if (i
.index_reg
== 0)
7592 i386_operand_type newdisp
;
7594 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
7595 /* Operand is just <disp> */
7596 if (flag_code
== CODE_64BIT
)
7598 /* 64bit mode overwrites the 32bit absolute
7599 addressing by RIP relative addressing and
7600 absolute addressing is encoded by one of the
7601 redundant SIB forms. */
7602 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
7603 i
.sib
.base
= NO_BASE_REGISTER
;
7604 i
.sib
.index
= NO_INDEX_REGISTER
;
7605 newdisp
= (!i
.prefix
[ADDR_PREFIX
] ? disp32s
: disp32
);
7607 else if ((flag_code
== CODE_16BIT
)
7608 ^ (i
.prefix
[ADDR_PREFIX
] != 0))
7610 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
7615 i
.rm
.regmem
= NO_BASE_REGISTER
;
7618 i
.types
[op
] = operand_type_and_not (i
.types
[op
], anydisp
);
7619 i
.types
[op
] = operand_type_or (i
.types
[op
], newdisp
);
7621 else if (!i
.tm
.opcode_modifier
.vecsib
)
7623 /* !i.base_reg && i.index_reg */
7624 if (i
.index_reg
->reg_num
== RegIZ
)
7625 i
.sib
.index
= NO_INDEX_REGISTER
;
7627 i
.sib
.index
= i
.index_reg
->reg_num
;
7628 i
.sib
.base
= NO_BASE_REGISTER
;
7629 i
.sib
.scale
= i
.log2_scale_factor
;
7630 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
7631 i
.types
[op
].bitfield
.disp8
= 0;
7632 i
.types
[op
].bitfield
.disp16
= 0;
7633 i
.types
[op
].bitfield
.disp64
= 0;
7634 if (flag_code
!= CODE_64BIT
|| i
.prefix
[ADDR_PREFIX
])
7636 /* Must be 32 bit */
7637 i
.types
[op
].bitfield
.disp32
= 1;
7638 i
.types
[op
].bitfield
.disp32s
= 0;
7642 i
.types
[op
].bitfield
.disp32
= 0;
7643 i
.types
[op
].bitfield
.disp32s
= 1;
7645 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
7649 /* RIP addressing for 64bit mode. */
7650 else if (i
.base_reg
->reg_num
== RegIP
)
7652 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
7653 i
.rm
.regmem
= NO_BASE_REGISTER
;
7654 i
.types
[op
].bitfield
.disp8
= 0;
7655 i
.types
[op
].bitfield
.disp16
= 0;
7656 i
.types
[op
].bitfield
.disp32
= 0;
7657 i
.types
[op
].bitfield
.disp32s
= 1;
7658 i
.types
[op
].bitfield
.disp64
= 0;
7659 i
.flags
[op
] |= Operand_PCrel
;
7660 if (! i
.disp_operands
)
7661 fake_zero_displacement
= 1;
7663 else if (i
.base_reg
->reg_type
.bitfield
.word
)
7665 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
7666 switch (i
.base_reg
->reg_num
)
7669 if (i
.index_reg
== 0)
7671 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
7672 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
7676 if (i
.index_reg
== 0)
7679 if (operand_type_check (i
.types
[op
], disp
) == 0)
7681 /* fake (%bp) into 0(%bp) */
7682 i
.types
[op
].bitfield
.disp8
= 1;
7683 fake_zero_displacement
= 1;
7686 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
7687 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
7689 default: /* (%si) -> 4 or (%di) -> 5 */
7690 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
7692 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
7694 else /* i.base_reg and 32/64 bit mode */
7696 if (flag_code
== CODE_64BIT
7697 && operand_type_check (i
.types
[op
], disp
))
7699 i
.types
[op
].bitfield
.disp16
= 0;
7700 i
.types
[op
].bitfield
.disp64
= 0;
7701 if (i
.prefix
[ADDR_PREFIX
] == 0)
7703 i
.types
[op
].bitfield
.disp32
= 0;
7704 i
.types
[op
].bitfield
.disp32s
= 1;
7708 i
.types
[op
].bitfield
.disp32
= 1;
7709 i
.types
[op
].bitfield
.disp32s
= 0;
7713 if (!i
.tm
.opcode_modifier
.vecsib
)
7714 i
.rm
.regmem
= i
.base_reg
->reg_num
;
7715 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
7717 i
.sib
.base
= i
.base_reg
->reg_num
;
7718 /* x86-64 ignores REX prefix bit here to avoid decoder
7720 if (!(i
.base_reg
->reg_flags
& RegRex
)
7721 && (i
.base_reg
->reg_num
== EBP_REG_NUM
7722 || i
.base_reg
->reg_num
== ESP_REG_NUM
))
7724 if (i
.base_reg
->reg_num
== 5 && i
.disp_operands
== 0)
7726 fake_zero_displacement
= 1;
7727 i
.types
[op
].bitfield
.disp8
= 1;
7729 i
.sib
.scale
= i
.log2_scale_factor
;
7730 if (i
.index_reg
== 0)
7732 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
7733 /* <disp>(%esp) becomes two byte modrm with no index
7734 register. We've already stored the code for esp
7735 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
7736 Any base register besides %esp will not use the
7737 extra modrm byte. */
7738 i
.sib
.index
= NO_INDEX_REGISTER
;
7740 else if (!i
.tm
.opcode_modifier
.vecsib
)
7742 if (i
.index_reg
->reg_num
== RegIZ
)
7743 i
.sib
.index
= NO_INDEX_REGISTER
;
7745 i
.sib
.index
= i
.index_reg
->reg_num
;
7746 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
7747 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
7752 && (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
7753 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
))
7757 if (!fake_zero_displacement
7761 fake_zero_displacement
= 1;
7762 if (i
.disp_encoding
== disp_encoding_8bit
)
7763 i
.types
[op
].bitfield
.disp8
= 1;
7765 i
.types
[op
].bitfield
.disp32
= 1;
7767 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
7771 if (fake_zero_displacement
)
7773 /* Fakes a zero displacement assuming that i.types[op]
7774 holds the correct displacement size. */
7777 gas_assert (i
.op
[op
].disps
== 0);
7778 exp
= &disp_expressions
[i
.disp_operands
++];
7779 i
.op
[op
].disps
= exp
;
7780 exp
->X_op
= O_constant
;
7781 exp
->X_add_number
= 0;
7782 exp
->X_add_symbol
= (symbolS
*) 0;
7783 exp
->X_op_symbol
= (symbolS
*) 0;
7791 if (i
.tm
.opcode_modifier
.vexsources
== XOP2SOURCES
)
7793 if (operand_type_check (i
.types
[0], imm
))
7794 i
.vex
.register_specifier
= NULL
;
7797 /* VEX.vvvv encodes one of the sources when the first
7798 operand is not an immediate. */
7799 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
7800 i
.vex
.register_specifier
= i
.op
[0].regs
;
7802 i
.vex
.register_specifier
= i
.op
[1].regs
;
7805 /* Destination is a XMM register encoded in the ModRM.reg
7807 i
.rm
.reg
= i
.op
[2].regs
->reg_num
;
7808 if ((i
.op
[2].regs
->reg_flags
& RegRex
) != 0)
7811 /* ModRM.rm and VEX.B encodes the other source. */
7812 if (!i
.mem_operands
)
7816 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
7817 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
7819 i
.rm
.regmem
= i
.op
[0].regs
->reg_num
;
7821 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
7825 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXLWP
)
7827 i
.vex
.register_specifier
= i
.op
[2].regs
;
7828 if (!i
.mem_operands
)
7831 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
7832 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
7836 /* Fill in i.rm.reg or i.rm.regmem field with register operand
7837 (if any) based on i.tm.extension_opcode. Again, we must be
7838 careful to make sure that segment/control/debug/test/MMX
7839 registers are coded into the i.rm.reg field. */
7840 else if (i
.reg_operands
)
7843 unsigned int vex_reg
= ~0;
7845 for (op
= 0; op
< i
.operands
; op
++)
7847 if (i
.types
[op
].bitfield
.class == Reg
7848 || i
.types
[op
].bitfield
.class == RegBND
7849 || i
.types
[op
].bitfield
.class == RegMask
7850 || i
.types
[op
].bitfield
.class == SReg
7851 || i
.types
[op
].bitfield
.class == RegCR
7852 || i
.types
[op
].bitfield
.class == RegDR
7853 || i
.types
[op
].bitfield
.class == RegTR
)
7855 if (i
.types
[op
].bitfield
.class == RegSIMD
)
7857 if (i
.types
[op
].bitfield
.zmmword
)
7858 i
.has_regzmm
= TRUE
;
7859 else if (i
.types
[op
].bitfield
.ymmword
)
7860 i
.has_regymm
= TRUE
;
7862 i
.has_regxmm
= TRUE
;
7865 if (i
.types
[op
].bitfield
.class == RegMMX
)
7867 i
.has_regmmx
= TRUE
;
7874 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
7876 /* For instructions with VexNDS, the register-only
7877 source operand is encoded in VEX prefix. */
7878 gas_assert (mem
!= (unsigned int) ~0);
7883 gas_assert (op
< i
.operands
);
7887 /* Check register-only source operand when two source
7888 operands are swapped. */
7889 if (!i
.tm
.operand_types
[op
].bitfield
.baseindex
7890 && i
.tm
.operand_types
[op
+ 1].bitfield
.baseindex
)
7894 gas_assert (mem
== (vex_reg
+ 1)
7895 && op
< i
.operands
);
7900 gas_assert (vex_reg
< i
.operands
);
7904 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXNDD
)
7906 /* For instructions with VexNDD, the register destination
7907 is encoded in VEX prefix. */
7908 if (i
.mem_operands
== 0)
7910 /* There is no memory operand. */
7911 gas_assert ((op
+ 2) == i
.operands
);
7916 /* There are only 2 non-immediate operands. */
7917 gas_assert (op
< i
.imm_operands
+ 2
7918 && i
.operands
== i
.imm_operands
+ 2);
7919 vex_reg
= i
.imm_operands
+ 1;
7923 gas_assert (op
< i
.operands
);
7925 if (vex_reg
!= (unsigned int) ~0)
7927 i386_operand_type
*type
= &i
.tm
.operand_types
[vex_reg
];
7929 if ((type
->bitfield
.class != Reg
7930 || (!type
->bitfield
.dword
&& !type
->bitfield
.qword
))
7931 && type
->bitfield
.class != RegSIMD
7932 && !operand_type_equal (type
, ®mask
))
7935 i
.vex
.register_specifier
= i
.op
[vex_reg
].regs
;
7938 /* Don't set OP operand twice. */
7941 /* If there is an extension opcode to put here, the
7942 register number must be put into the regmem field. */
7943 if (i
.tm
.extension_opcode
!= None
)
7945 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
7946 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
7948 if ((i
.op
[op
].regs
->reg_flags
& RegVRex
) != 0)
7953 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
7954 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
7956 if ((i
.op
[op
].regs
->reg_flags
& RegVRex
) != 0)
7961 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
7962 must set it to 3 to indicate this is a register operand
7963 in the regmem field. */
7964 if (!i
.mem_operands
)
7968 /* Fill in i.rm.reg field with extension opcode (if any). */
7969 if (i
.tm
.extension_opcode
!= None
)
7970 i
.rm
.reg
= i
.tm
.extension_opcode
;
7976 flip_code16 (unsigned int code16
)
7978 gas_assert (i
.tm
.operands
== 1);
7980 return !(i
.prefix
[REX_PREFIX
] & REX_W
)
7981 && (code16
? i
.tm
.operand_types
[0].bitfield
.disp32
7982 || i
.tm
.operand_types
[0].bitfield
.disp32s
7983 : i
.tm
.operand_types
[0].bitfield
.disp16
)
7988 output_branch (void)
7994 relax_substateT subtype
;
7998 code16
= flag_code
== CODE_16BIT
? CODE16
: 0;
7999 size
= i
.disp_encoding
== disp_encoding_32bit
? BIG
: SMALL
;
8002 if (i
.prefix
[DATA_PREFIX
] != 0)
8006 code16
^= flip_code16(code16
);
8008 /* Pentium4 branch hints. */
8009 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
8010 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
8015 if (i
.prefix
[REX_PREFIX
] != 0)
8021 /* BND prefixed jump. */
8022 if (i
.prefix
[BND_PREFIX
] != 0)
8028 if (i
.prefixes
!= 0)
8029 as_warn (_("skipping prefixes on `%s'"), i
.tm
.name
);
8031 /* It's always a symbol; End frag & setup for relax.
8032 Make sure there is enough room in this frag for the largest
8033 instruction we may generate in md_convert_frag. This is 2
8034 bytes for the opcode and room for the prefix and largest
8036 frag_grow (prefix
+ 2 + 4);
8037 /* Prefix and 1 opcode byte go in fr_fix. */
8038 p
= frag_more (prefix
+ 1);
8039 if (i
.prefix
[DATA_PREFIX
] != 0)
8040 *p
++ = DATA_PREFIX_OPCODE
;
8041 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
8042 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
8043 *p
++ = i
.prefix
[SEG_PREFIX
];
8044 if (i
.prefix
[BND_PREFIX
] != 0)
8045 *p
++ = BND_PREFIX_OPCODE
;
8046 if (i
.prefix
[REX_PREFIX
] != 0)
8047 *p
++ = i
.prefix
[REX_PREFIX
];
8048 *p
= i
.tm
.base_opcode
;
8050 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
8051 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, size
);
8052 else if (cpu_arch_flags
.bitfield
.cpui386
)
8053 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, size
);
8055 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, size
);
8058 sym
= i
.op
[0].disps
->X_add_symbol
;
8059 off
= i
.op
[0].disps
->X_add_number
;
8061 if (i
.op
[0].disps
->X_op
!= O_constant
8062 && i
.op
[0].disps
->X_op
!= O_symbol
)
8064 /* Handle complex expressions. */
8065 sym
= make_expr_symbol (i
.op
[0].disps
);
8069 /* 1 possible extra opcode + 4 byte displacement go in var part.
8070 Pass reloc in fr_var. */
8071 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
8074 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8075 /* Return TRUE iff PLT32 relocation should be used for branching to
8079 need_plt32_p (symbolS
*s
)
8081 /* PLT32 relocation is ELF only. */
8086 /* Don't emit PLT32 relocation on Solaris: neither native linker nor
8087 krtld support it. */
8091 /* Since there is no need to prepare for PLT branch on x86-64, we
8092 can generate R_X86_64_PLT32, instead of R_X86_64_PC32, which can
8093 be used as a marker for 32-bit PC-relative branches. */
8097 /* Weak or undefined symbol need PLT32 relocation. */
8098 if (S_IS_WEAK (s
) || !S_IS_DEFINED (s
))
8101 /* Non-global symbol doesn't need PLT32 relocation. */
8102 if (! S_IS_EXTERNAL (s
))
8105 /* Other global symbols need PLT32 relocation. NB: Symbol with
8106 non-default visibilities are treated as normal global symbol
8107 so that PLT32 relocation can be used as a marker for 32-bit
8108 PC-relative branches. It is useful for linker relaxation. */
8119 bfd_reloc_code_real_type jump_reloc
= i
.reloc
[0];
8121 if (i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
)
8123 /* This is a loop or jecxz type instruction. */
8125 if (i
.prefix
[ADDR_PREFIX
] != 0)
8127 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
8130 /* Pentium4 branch hints. */
8131 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
8132 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
8134 FRAG_APPEND_1_CHAR (i
.prefix
[SEG_PREFIX
]);
8143 if (flag_code
== CODE_16BIT
)
8146 if (i
.prefix
[DATA_PREFIX
] != 0)
8148 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
8150 code16
^= flip_code16(code16
);
8158 /* BND prefixed jump. */
8159 if (i
.prefix
[BND_PREFIX
] != 0)
8161 FRAG_APPEND_1_CHAR (i
.prefix
[BND_PREFIX
]);
8165 if (i
.prefix
[REX_PREFIX
] != 0)
8167 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
8171 if (i
.prefixes
!= 0)
8172 as_warn (_("skipping prefixes on `%s'"), i
.tm
.name
);
8174 p
= frag_more (i
.tm
.opcode_length
+ size
);
8175 switch (i
.tm
.opcode_length
)
8178 *p
++ = i
.tm
.base_opcode
>> 8;
8181 *p
++ = i
.tm
.base_opcode
;
8187 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8189 && jump_reloc
== NO_RELOC
8190 && need_plt32_p (i
.op
[0].disps
->X_add_symbol
))
8191 jump_reloc
= BFD_RELOC_X86_64_PLT32
;
8194 jump_reloc
= reloc (size
, 1, 1, jump_reloc
);
8196 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
8197 i
.op
[0].disps
, 1, jump_reloc
);
8199 /* All jumps handled here are signed, but don't use a signed limit
8200 check for 32 and 16 bit jumps as we want to allow wrap around at
8201 4G and 64k respectively. */
8203 fixP
->fx_signed
= 1;
8207 output_interseg_jump (void)
8215 if (flag_code
== CODE_16BIT
)
8219 if (i
.prefix
[DATA_PREFIX
] != 0)
8226 gas_assert (!i
.prefix
[REX_PREFIX
]);
8232 if (i
.prefixes
!= 0)
8233 as_warn (_("skipping prefixes on `%s'"), i
.tm
.name
);
8235 /* 1 opcode; 2 segment; offset */
8236 p
= frag_more (prefix
+ 1 + 2 + size
);
8238 if (i
.prefix
[DATA_PREFIX
] != 0)
8239 *p
++ = DATA_PREFIX_OPCODE
;
8241 if (i
.prefix
[REX_PREFIX
] != 0)
8242 *p
++ = i
.prefix
[REX_PREFIX
];
8244 *p
++ = i
.tm
.base_opcode
;
8245 if (i
.op
[1].imms
->X_op
== O_constant
)
8247 offsetT n
= i
.op
[1].imms
->X_add_number
;
8250 && !fits_in_unsigned_word (n
)
8251 && !fits_in_signed_word (n
))
8253 as_bad (_("16-bit jump out of range"));
8256 md_number_to_chars (p
, n
, size
);
8259 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
8260 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
8261 if (i
.op
[0].imms
->X_op
!= O_constant
)
8262 as_bad (_("can't handle non absolute segment in `%s'"),
8264 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
8267 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8272 asection
*seg
= now_seg
;
8273 subsegT subseg
= now_subseg
;
8275 unsigned int alignment
, align_size_1
;
8276 unsigned int isa_1_descsz
, feature_2_descsz
, descsz
;
8277 unsigned int isa_1_descsz_raw
, feature_2_descsz_raw
;
8278 unsigned int padding
;
8280 if (!IS_ELF
|| !x86_used_note
)
8283 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_X86
;
8285 /* The .note.gnu.property section layout:
8287 Field Length Contents
8290 n_descsz 4 The note descriptor size
8291 n_type 4 NT_GNU_PROPERTY_TYPE_0
8293 n_desc n_descsz The program property array
8297 /* Create the .note.gnu.property section. */
8298 sec
= subseg_new (NOTE_GNU_PROPERTY_SECTION_NAME
, 0);
8299 bfd_set_section_flags (sec
,
8306 if (get_elf_backend_data (stdoutput
)->s
->elfclass
== ELFCLASS64
)
8317 bfd_set_section_alignment (sec
, alignment
);
8318 elf_section_type (sec
) = SHT_NOTE
;
8320 /* GNU_PROPERTY_X86_ISA_1_USED: 4-byte type + 4-byte data size
8322 isa_1_descsz_raw
= 4 + 4 + 4;
8323 /* Align GNU_PROPERTY_X86_ISA_1_USED. */
8324 isa_1_descsz
= (isa_1_descsz_raw
+ align_size_1
) & ~align_size_1
;
8326 feature_2_descsz_raw
= isa_1_descsz
;
8327 /* GNU_PROPERTY_X86_FEATURE_2_USED: 4-byte type + 4-byte data size
8329 feature_2_descsz_raw
+= 4 + 4 + 4;
8330 /* Align GNU_PROPERTY_X86_FEATURE_2_USED. */
8331 feature_2_descsz
= ((feature_2_descsz_raw
+ align_size_1
)
8334 descsz
= feature_2_descsz
;
8335 /* Section size: n_namsz + n_descsz + n_type + n_name + n_descsz. */
8336 p
= frag_more (4 + 4 + 4 + 4 + descsz
);
8338 /* Write n_namsz. */
8339 md_number_to_chars (p
, (valueT
) 4, 4);
8341 /* Write n_descsz. */
8342 md_number_to_chars (p
+ 4, (valueT
) descsz
, 4);
8345 md_number_to_chars (p
+ 4 * 2, (valueT
) NT_GNU_PROPERTY_TYPE_0
, 4);
8348 memcpy (p
+ 4 * 3, "GNU", 4);
8350 /* Write 4-byte type. */
8351 md_number_to_chars (p
+ 4 * 4,
8352 (valueT
) GNU_PROPERTY_X86_ISA_1_USED
, 4);
8354 /* Write 4-byte data size. */
8355 md_number_to_chars (p
+ 4 * 5, (valueT
) 4, 4);
8357 /* Write 4-byte data. */
8358 md_number_to_chars (p
+ 4 * 6, (valueT
) x86_isa_1_used
, 4);
8360 /* Zero out paddings. */
8361 padding
= isa_1_descsz
- isa_1_descsz_raw
;
8363 memset (p
+ 4 * 7, 0, padding
);
8365 /* Write 4-byte type. */
8366 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 4,
8367 (valueT
) GNU_PROPERTY_X86_FEATURE_2_USED
, 4);
8369 /* Write 4-byte data size. */
8370 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 5, (valueT
) 4, 4);
8372 /* Write 4-byte data. */
8373 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 6,
8374 (valueT
) x86_feature_2_used
, 4);
8376 /* Zero out paddings. */
8377 padding
= feature_2_descsz
- feature_2_descsz_raw
;
8379 memset (p
+ isa_1_descsz
+ 4 * 7, 0, padding
);
8381 /* We probably can't restore the current segment, for there likely
8384 subseg_set (seg
, subseg
);
8389 encoding_length (const fragS
*start_frag
, offsetT start_off
,
8390 const char *frag_now_ptr
)
8392 unsigned int len
= 0;
8394 if (start_frag
!= frag_now
)
8396 const fragS
*fr
= start_frag
;
8401 } while (fr
&& fr
!= frag_now
);
8404 return len
- start_off
+ (frag_now_ptr
- frag_now
->fr_literal
);
8407 /* Return 1 for test, and, cmp, add, sub, inc and dec which may
8408 be macro-fused with conditional jumps.
8409 NB: If TEST/AND/CMP/ADD/SUB/INC/DEC is of RIP relative address,
8410 or is one of the following format:
8423 maybe_fused_with_jcc_p (enum mf_cmp_kind
* mf_cmp_p
)
8425 /* No RIP address. */
8426 if (i
.base_reg
&& i
.base_reg
->reg_num
== RegIP
)
8429 /* No VEX/EVEX encoding. */
8430 if (is_any_vex_encoding (&i
.tm
))
8433 /* add, sub without add/sub m, imm. */
8434 if (i
.tm
.base_opcode
<= 5
8435 || (i
.tm
.base_opcode
>= 0x28 && i
.tm
.base_opcode
<= 0x2d)
8436 || ((i
.tm
.base_opcode
| 3) == 0x83
8437 && (i
.tm
.extension_opcode
== 0x5
8438 || i
.tm
.extension_opcode
== 0x0)))
8440 *mf_cmp_p
= mf_cmp_alu_cmp
;
8441 return !(i
.mem_operands
&& i
.imm_operands
);
8444 /* and without and m, imm. */
8445 if ((i
.tm
.base_opcode
>= 0x20 && i
.tm
.base_opcode
<= 0x25)
8446 || ((i
.tm
.base_opcode
| 3) == 0x83
8447 && i
.tm
.extension_opcode
== 0x4))
8449 *mf_cmp_p
= mf_cmp_test_and
;
8450 return !(i
.mem_operands
&& i
.imm_operands
);
8453 /* test without test m imm. */
8454 if ((i
.tm
.base_opcode
| 1) == 0x85
8455 || (i
.tm
.base_opcode
| 1) == 0xa9
8456 || ((i
.tm
.base_opcode
| 1) == 0xf7
8457 && i
.tm
.extension_opcode
== 0))
8459 *mf_cmp_p
= mf_cmp_test_and
;
8460 return !(i
.mem_operands
&& i
.imm_operands
);
8463 /* cmp without cmp m, imm. */
8464 if ((i
.tm
.base_opcode
>= 0x38 && i
.tm
.base_opcode
<= 0x3d)
8465 || ((i
.tm
.base_opcode
| 3) == 0x83
8466 && (i
.tm
.extension_opcode
== 0x7)))
8468 *mf_cmp_p
= mf_cmp_alu_cmp
;
8469 return !(i
.mem_operands
&& i
.imm_operands
);
8472 /* inc, dec without inc/dec m. */
8473 if ((i
.tm
.cpu_flags
.bitfield
.cpuno64
8474 && (i
.tm
.base_opcode
| 0xf) == 0x4f)
8475 || ((i
.tm
.base_opcode
| 1) == 0xff
8476 && i
.tm
.extension_opcode
<= 0x1))
8478 *mf_cmp_p
= mf_cmp_incdec
;
8479 return !i
.mem_operands
;
8485 /* Return 1 if a FUSED_JCC_PADDING frag should be generated. */
8488 add_fused_jcc_padding_frag_p (enum mf_cmp_kind
* mf_cmp_p
)
8490 /* NB: Don't work with COND_JUMP86 without i386. */
8491 if (!align_branch_power
8492 || now_seg
== absolute_section
8493 || !cpu_arch_flags
.bitfield
.cpui386
8494 || !(align_branch
& align_branch_fused_bit
))
8497 if (maybe_fused_with_jcc_p (mf_cmp_p
))
8499 if (last_insn
.kind
== last_insn_other
8500 || last_insn
.seg
!= now_seg
)
8503 as_warn_where (last_insn
.file
, last_insn
.line
,
8504 _("`%s` skips -malign-branch-boundary on `%s`"),
8505 last_insn
.name
, i
.tm
.name
);
8511 /* Return 1 if a BRANCH_PREFIX frag should be generated. */
8514 add_branch_prefix_frag_p (void)
8516 /* NB: Don't work with COND_JUMP86 without i386. Don't add prefix
8517 to PadLock instructions since they include prefixes in opcode. */
8518 if (!align_branch_power
8519 || !align_branch_prefix_size
8520 || now_seg
== absolute_section
8521 || i
.tm
.cpu_flags
.bitfield
.cpupadlock
8522 || !cpu_arch_flags
.bitfield
.cpui386
)
8525 /* Don't add prefix if it is a prefix or there is no operand in case
8526 that segment prefix is special. */
8527 if (!i
.operands
|| i
.tm
.opcode_modifier
.isprefix
)
8530 if (last_insn
.kind
== last_insn_other
8531 || last_insn
.seg
!= now_seg
)
8535 as_warn_where (last_insn
.file
, last_insn
.line
,
8536 _("`%s` skips -malign-branch-boundary on `%s`"),
8537 last_insn
.name
, i
.tm
.name
);
8542 /* Return 1 if a BRANCH_PADDING frag should be generated. */
8545 add_branch_padding_frag_p (enum align_branch_kind
*branch_p
,
8546 enum mf_jcc_kind
*mf_jcc_p
)
8550 /* NB: Don't work with COND_JUMP86 without i386. */
8551 if (!align_branch_power
8552 || now_seg
== absolute_section
8553 || !cpu_arch_flags
.bitfield
.cpui386
)
8558 /* Check for jcc and direct jmp. */
8559 if (i
.tm
.opcode_modifier
.jump
== JUMP
)
8561 if (i
.tm
.base_opcode
== JUMP_PC_RELATIVE
)
8563 *branch_p
= align_branch_jmp
;
8564 add_padding
= align_branch
& align_branch_jmp_bit
;
8568 /* Because J<cc> and JN<cc> share same group in macro-fusible table,
8569 igore the lowest bit. */
8570 *mf_jcc_p
= (i
.tm
.base_opcode
& 0x0e) >> 1;
8571 *branch_p
= align_branch_jcc
;
8572 if ((align_branch
& align_branch_jcc_bit
))
8576 else if (is_any_vex_encoding (&i
.tm
))
8578 else if ((i
.tm
.base_opcode
| 1) == 0xc3)
8581 *branch_p
= align_branch_ret
;
8582 if ((align_branch
& align_branch_ret_bit
))
8587 /* Check for indirect jmp, direct and indirect calls. */
8588 if (i
.tm
.base_opcode
== 0xe8)
8591 *branch_p
= align_branch_call
;
8592 if ((align_branch
& align_branch_call_bit
))
8595 else if (i
.tm
.base_opcode
== 0xff
8596 && (i
.tm
.extension_opcode
== 2
8597 || i
.tm
.extension_opcode
== 4))
8599 /* Indirect call and jmp. */
8600 *branch_p
= align_branch_indirect
;
8601 if ((align_branch
& align_branch_indirect_bit
))
8608 && (i
.op
[0].disps
->X_op
== O_symbol
8609 || (i
.op
[0].disps
->X_op
== O_subtract
8610 && i
.op
[0].disps
->X_op_symbol
== GOT_symbol
)))
8612 symbolS
*s
= i
.op
[0].disps
->X_add_symbol
;
8613 /* No padding to call to global or undefined tls_get_addr. */
8614 if ((S_IS_EXTERNAL (s
) || !S_IS_DEFINED (s
))
8615 && strcmp (S_GET_NAME (s
), tls_get_addr
) == 0)
8621 && last_insn
.kind
!= last_insn_other
8622 && last_insn
.seg
== now_seg
)
8625 as_warn_where (last_insn
.file
, last_insn
.line
,
8626 _("`%s` skips -malign-branch-boundary on `%s`"),
8627 last_insn
.name
, i
.tm
.name
);
8637 fragS
*insn_start_frag
;
8638 offsetT insn_start_off
;
8639 fragS
*fragP
= NULL
;
8640 enum align_branch_kind branch
= align_branch_none
;
8641 /* The initializer is arbitrary just to avoid uninitialized error.
8642 it's actually either assigned in add_branch_padding_frag_p
8643 or never be used. */
8644 enum mf_jcc_kind mf_jcc
= mf_jcc_jo
;
8646 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8647 if (IS_ELF
&& x86_used_note
)
8649 if (i
.tm
.cpu_flags
.bitfield
.cpucmov
)
8650 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_CMOV
;
8651 if (i
.tm
.cpu_flags
.bitfield
.cpusse
)
8652 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE
;
8653 if (i
.tm
.cpu_flags
.bitfield
.cpusse2
)
8654 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE2
;
8655 if (i
.tm
.cpu_flags
.bitfield
.cpusse3
)
8656 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE3
;
8657 if (i
.tm
.cpu_flags
.bitfield
.cpussse3
)
8658 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSSE3
;
8659 if (i
.tm
.cpu_flags
.bitfield
.cpusse4_1
)
8660 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE4_1
;
8661 if (i
.tm
.cpu_flags
.bitfield
.cpusse4_2
)
8662 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE4_2
;
8663 if (i
.tm
.cpu_flags
.bitfield
.cpuavx
)
8664 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX
;
8665 if (i
.tm
.cpu_flags
.bitfield
.cpuavx2
)
8666 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX2
;
8667 if (i
.tm
.cpu_flags
.bitfield
.cpufma
)
8668 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_FMA
;
8669 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512f
)
8670 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512F
;
8671 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512cd
)
8672 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512CD
;
8673 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512er
)
8674 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512ER
;
8675 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512pf
)
8676 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512PF
;
8677 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512vl
)
8678 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512VL
;
8679 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512dq
)
8680 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512DQ
;
8681 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512bw
)
8682 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512BW
;
8683 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_4fmaps
)
8684 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_4FMAPS
;
8685 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_4vnniw
)
8686 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_4VNNIW
;
8687 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_bitalg
)
8688 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_BITALG
;
8689 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512ifma
)
8690 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_IFMA
;
8691 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512vbmi
)
8692 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_VBMI
;
8693 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_vbmi2
)
8694 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_VBMI2
;
8695 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_vnni
)
8696 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_VNNI
;
8697 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_bf16
)
8698 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_BF16
;
8700 if (i
.tm
.cpu_flags
.bitfield
.cpu8087
8701 || i
.tm
.cpu_flags
.bitfield
.cpu287
8702 || i
.tm
.cpu_flags
.bitfield
.cpu387
8703 || i
.tm
.cpu_flags
.bitfield
.cpu687
8704 || i
.tm
.cpu_flags
.bitfield
.cpufisttp
)
8705 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_X87
;
8707 || i
.tm
.base_opcode
== 0xf77 /* emms */
8708 || i
.tm
.base_opcode
== 0xf0e /* femms */
8709 || i
.tm
.base_opcode
== 0xf2a /* cvtpi2ps */
8710 || i
.tm
.base_opcode
== 0x660f2a /* cvtpi2pd */)
8711 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_MMX
;
8713 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XMM
;
8715 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_YMM
;
8717 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_ZMM
;
8718 if (i
.tm
.cpu_flags
.bitfield
.cpufxsr
)
8719 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_FXSR
;
8720 if (i
.tm
.cpu_flags
.bitfield
.cpuxsave
)
8721 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVE
;
8722 if (i
.tm
.cpu_flags
.bitfield
.cpuxsaveopt
)
8723 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVEOPT
;
8724 if (i
.tm
.cpu_flags
.bitfield
.cpuxsavec
)
8725 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVEC
;
8729 /* Tie dwarf2 debug info to the address at the start of the insn.
8730 We can't do this after the insn has been output as the current
8731 frag may have been closed off. eg. by frag_var. */
8732 dwarf2_emit_insn (0);
8734 insn_start_frag
= frag_now
;
8735 insn_start_off
= frag_now_fix ();
8737 if (add_branch_padding_frag_p (&branch
, &mf_jcc
))
8740 /* Branch can be 8 bytes. Leave some room for prefixes. */
8741 unsigned int max_branch_padding_size
= 14;
8743 /* Align section to boundary. */
8744 record_alignment (now_seg
, align_branch_power
);
8746 /* Make room for padding. */
8747 frag_grow (max_branch_padding_size
);
8749 /* Start of the padding. */
8754 frag_var (rs_machine_dependent
, max_branch_padding_size
, 0,
8755 ENCODE_RELAX_STATE (BRANCH_PADDING
, 0),
8758 fragP
->tc_frag_data
.mf_type
= mf_jcc
;
8759 fragP
->tc_frag_data
.branch_type
= branch
;
8760 fragP
->tc_frag_data
.max_bytes
= max_branch_padding_size
;
8764 if (i
.tm
.opcode_modifier
.jump
== JUMP
)
8766 else if (i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
8767 || i
.tm
.opcode_modifier
.jump
== JUMP_DWORD
)
8769 else if (i
.tm
.opcode_modifier
.jump
== JUMP_INTERSEGMENT
)
8770 output_interseg_jump ();
8773 /* Output normal instructions here. */
8777 unsigned int prefix
;
8778 enum mf_cmp_kind mf_cmp
;
8781 && (i
.tm
.base_opcode
== 0xfaee8
8782 || i
.tm
.base_opcode
== 0xfaef0
8783 || i
.tm
.base_opcode
== 0xfaef8))
8785 /* Encode lfence, mfence, and sfence as
8786 f0 83 04 24 00 lock addl $0x0, (%{re}sp). */
8787 offsetT val
= 0x240483f0ULL
;
8789 md_number_to_chars (p
, val
, 5);
8793 /* Some processors fail on LOCK prefix. This options makes
8794 assembler ignore LOCK prefix and serves as a workaround. */
8795 if (omit_lock_prefix
)
8797 if (i
.tm
.base_opcode
== LOCK_PREFIX_OPCODE
)
8799 i
.prefix
[LOCK_PREFIX
] = 0;
8803 /* Skip if this is a branch. */
8805 else if (add_fused_jcc_padding_frag_p (&mf_cmp
))
8807 /* Make room for padding. */
8808 frag_grow (MAX_FUSED_JCC_PADDING_SIZE
);
8813 frag_var (rs_machine_dependent
, MAX_FUSED_JCC_PADDING_SIZE
, 0,
8814 ENCODE_RELAX_STATE (FUSED_JCC_PADDING
, 0),
8817 fragP
->tc_frag_data
.mf_type
= mf_cmp
;
8818 fragP
->tc_frag_data
.branch_type
= align_branch_fused
;
8819 fragP
->tc_frag_data
.max_bytes
= MAX_FUSED_JCC_PADDING_SIZE
;
8821 else if (add_branch_prefix_frag_p ())
8823 unsigned int max_prefix_size
= align_branch_prefix_size
;
8825 /* Make room for padding. */
8826 frag_grow (max_prefix_size
);
8831 frag_var (rs_machine_dependent
, max_prefix_size
, 0,
8832 ENCODE_RELAX_STATE (BRANCH_PREFIX
, 0),
8835 fragP
->tc_frag_data
.max_bytes
= max_prefix_size
;
8838 /* Since the VEX/EVEX prefix contains the implicit prefix, we
8839 don't need the explicit prefix. */
8840 if (!i
.tm
.opcode_modifier
.vex
&& !i
.tm
.opcode_modifier
.evex
)
8842 switch (i
.tm
.opcode_length
)
8845 if (i
.tm
.base_opcode
& 0xff000000)
8847 prefix
= (i
.tm
.base_opcode
>> 24) & 0xff;
8848 if (!i
.tm
.cpu_flags
.bitfield
.cpupadlock
8849 || prefix
!= REPE_PREFIX_OPCODE
8850 || (i
.prefix
[REP_PREFIX
] != REPE_PREFIX_OPCODE
))
8851 add_prefix (prefix
);
8855 if ((i
.tm
.base_opcode
& 0xff0000) != 0)
8857 prefix
= (i
.tm
.base_opcode
>> 16) & 0xff;
8858 add_prefix (prefix
);
8864 /* Check for pseudo prefixes. */
8865 as_bad_where (insn_start_frag
->fr_file
,
8866 insn_start_frag
->fr_line
,
8867 _("pseudo prefix without instruction"));
8873 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
8874 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
8875 R_X86_64_GOTTPOFF relocation so that linker can safely
8876 perform IE->LE optimization. A dummy REX_OPCODE prefix
8877 is also needed for lea with R_X86_64_GOTPC32_TLSDESC
8878 relocation for GDesc -> IE/LE optimization. */
8879 if (x86_elf_abi
== X86_64_X32_ABI
8881 && (i
.reloc
[0] == BFD_RELOC_X86_64_GOTTPOFF
8882 || i
.reloc
[0] == BFD_RELOC_X86_64_GOTPC32_TLSDESC
)
8883 && i
.prefix
[REX_PREFIX
] == 0)
8884 add_prefix (REX_OPCODE
);
8887 /* The prefix bytes. */
8888 for (j
= ARRAY_SIZE (i
.prefix
), q
= i
.prefix
; j
> 0; j
--, q
++)
8890 FRAG_APPEND_1_CHAR (*q
);
8894 for (j
= 0, q
= i
.prefix
; j
< ARRAY_SIZE (i
.prefix
); j
++, q
++)
8899 /* REX byte is encoded in VEX prefix. */
8903 FRAG_APPEND_1_CHAR (*q
);
8906 /* There should be no other prefixes for instructions
8911 /* For EVEX instructions i.vrex should become 0 after
8912 build_evex_prefix. For VEX instructions upper 16 registers
8913 aren't available, so VREX should be 0. */
8916 /* Now the VEX prefix. */
8917 p
= frag_more (i
.vex
.length
);
8918 for (j
= 0; j
< i
.vex
.length
; j
++)
8919 p
[j
] = i
.vex
.bytes
[j
];
8922 /* Now the opcode; be careful about word order here! */
8923 if (i
.tm
.opcode_length
== 1)
8925 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
8929 switch (i
.tm
.opcode_length
)
8933 *p
++ = (i
.tm
.base_opcode
>> 24) & 0xff;
8934 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
8938 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
8948 /* Put out high byte first: can't use md_number_to_chars! */
8949 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
8950 *p
= i
.tm
.base_opcode
& 0xff;
8953 /* Now the modrm byte and sib byte (if present). */
8954 if (i
.tm
.opcode_modifier
.modrm
)
8956 FRAG_APPEND_1_CHAR ((i
.rm
.regmem
<< 0
8959 /* If i.rm.regmem == ESP (4)
8960 && i.rm.mode != (Register mode)
8962 ==> need second modrm byte. */
8963 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
8965 && !(i
.base_reg
&& i
.base_reg
->reg_type
.bitfield
.word
))
8966 FRAG_APPEND_1_CHAR ((i
.sib
.base
<< 0
8968 | i
.sib
.scale
<< 6));
8971 if (i
.disp_operands
)
8972 output_disp (insn_start_frag
, insn_start_off
);
8975 output_imm (insn_start_frag
, insn_start_off
);
8978 * frag_now_fix () returning plain abs_section_offset when we're in the
8979 * absolute section, and abs_section_offset not getting updated as data
8980 * gets added to the frag breaks the logic below.
8982 if (now_seg
!= absolute_section
)
8984 j
= encoding_length (insn_start_frag
, insn_start_off
, frag_more (0));
8986 as_warn (_("instruction length of %u bytes exceeds the limit of 15"),
8990 /* NB: Don't add prefix with GOTPC relocation since
8991 output_disp() above depends on the fixed encoding
8992 length. Can't add prefix with TLS relocation since
8993 it breaks TLS linker optimization. */
8994 unsigned int max
= i
.has_gotpc_tls_reloc
? 0 : 15 - j
;
8995 /* Prefix count on the current instruction. */
8996 unsigned int count
= i
.vex
.length
;
8998 for (k
= 0; k
< ARRAY_SIZE (i
.prefix
); k
++)
8999 /* REX byte is encoded in VEX/EVEX prefix. */
9000 if (i
.prefix
[k
] && (k
!= REX_PREFIX
|| !i
.vex
.length
))
9003 /* Count prefixes for extended opcode maps. */
9005 switch (i
.tm
.opcode_length
)
9008 if (((i
.tm
.base_opcode
>> 16) & 0xff) == 0xf)
9011 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
9023 if (((i
.tm
.base_opcode
>> 8) & 0xff) == 0xf)
9032 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
)
9035 /* Set the maximum prefix size in BRANCH_PREFIX
9037 if (fragP
->tc_frag_data
.max_bytes
> max
)
9038 fragP
->tc_frag_data
.max_bytes
= max
;
9039 if (fragP
->tc_frag_data
.max_bytes
> count
)
9040 fragP
->tc_frag_data
.max_bytes
-= count
;
9042 fragP
->tc_frag_data
.max_bytes
= 0;
9046 /* Remember the maximum prefix size in FUSED_JCC_PADDING
9048 unsigned int max_prefix_size
;
9049 if (align_branch_prefix_size
> max
)
9050 max_prefix_size
= max
;
9052 max_prefix_size
= align_branch_prefix_size
;
9053 if (max_prefix_size
> count
)
9054 fragP
->tc_frag_data
.max_prefix_length
9055 = max_prefix_size
- count
;
9058 /* Use existing segment prefix if possible. Use CS
9059 segment prefix in 64-bit mode. In 32-bit mode, use SS
9060 segment prefix with ESP/EBP base register and use DS
9061 segment prefix without ESP/EBP base register. */
9062 if (i
.prefix
[SEG_PREFIX
])
9063 fragP
->tc_frag_data
.default_prefix
= i
.prefix
[SEG_PREFIX
];
9064 else if (flag_code
== CODE_64BIT
)
9065 fragP
->tc_frag_data
.default_prefix
= CS_PREFIX_OPCODE
;
9067 && (i
.base_reg
->reg_num
== 4
9068 || i
.base_reg
->reg_num
== 5))
9069 fragP
->tc_frag_data
.default_prefix
= SS_PREFIX_OPCODE
;
9071 fragP
->tc_frag_data
.default_prefix
= DS_PREFIX_OPCODE
;
9076 /* NB: Don't work with COND_JUMP86 without i386. */
9077 if (align_branch_power
9078 && now_seg
!= absolute_section
9079 && cpu_arch_flags
.bitfield
.cpui386
)
9081 /* Terminate each frag so that we can add prefix and check for
9083 frag_wane (frag_now
);
9090 pi ("" /*line*/, &i
);
9092 #endif /* DEBUG386 */
9095 /* Return the size of the displacement operand N. */
9098 disp_size (unsigned int n
)
9102 if (i
.types
[n
].bitfield
.disp64
)
9104 else if (i
.types
[n
].bitfield
.disp8
)
9106 else if (i
.types
[n
].bitfield
.disp16
)
9111 /* Return the size of the immediate operand N. */
9114 imm_size (unsigned int n
)
9117 if (i
.types
[n
].bitfield
.imm64
)
9119 else if (i
.types
[n
].bitfield
.imm8
|| i
.types
[n
].bitfield
.imm8s
)
9121 else if (i
.types
[n
].bitfield
.imm16
)
9127 output_disp (fragS
*insn_start_frag
, offsetT insn_start_off
)
9132 for (n
= 0; n
< i
.operands
; n
++)
9134 if (operand_type_check (i
.types
[n
], disp
))
9136 if (i
.op
[n
].disps
->X_op
== O_constant
)
9138 int size
= disp_size (n
);
9139 offsetT val
= i
.op
[n
].disps
->X_add_number
;
9141 val
= offset_in_range (val
>> (size
== 1 ? i
.memshift
: 0),
9143 p
= frag_more (size
);
9144 md_number_to_chars (p
, val
, size
);
9148 enum bfd_reloc_code_real reloc_type
;
9149 int size
= disp_size (n
);
9150 int sign
= i
.types
[n
].bitfield
.disp32s
;
9151 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
9154 /* We can't have 8 bit displacement here. */
9155 gas_assert (!i
.types
[n
].bitfield
.disp8
);
9157 /* The PC relative address is computed relative
9158 to the instruction boundary, so in case immediate
9159 fields follows, we need to adjust the value. */
9160 if (pcrel
&& i
.imm_operands
)
9165 for (n1
= 0; n1
< i
.operands
; n1
++)
9166 if (operand_type_check (i
.types
[n1
], imm
))
9168 /* Only one immediate is allowed for PC
9169 relative address. */
9170 gas_assert (sz
== 0);
9172 i
.op
[n
].disps
->X_add_number
-= sz
;
9174 /* We should find the immediate. */
9175 gas_assert (sz
!= 0);
9178 p
= frag_more (size
);
9179 reloc_type
= reloc (size
, pcrel
, sign
, i
.reloc
[n
]);
9181 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
9182 && (((reloc_type
== BFD_RELOC_32
9183 || reloc_type
== BFD_RELOC_X86_64_32S
9184 || (reloc_type
== BFD_RELOC_64
9186 && (i
.op
[n
].disps
->X_op
== O_symbol
9187 || (i
.op
[n
].disps
->X_op
== O_add
9188 && ((symbol_get_value_expression
9189 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
9191 || reloc_type
== BFD_RELOC_32_PCREL
))
9195 reloc_type
= BFD_RELOC_386_GOTPC
;
9196 i
.has_gotpc_tls_reloc
= TRUE
;
9197 i
.op
[n
].imms
->X_add_number
+=
9198 encoding_length (insn_start_frag
, insn_start_off
, p
);
9200 else if (reloc_type
== BFD_RELOC_64
)
9201 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
9203 /* Don't do the adjustment for x86-64, as there
9204 the pcrel addressing is relative to the _next_
9205 insn, and that is taken care of in other code. */
9206 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
9208 else if (align_branch_power
)
9212 case BFD_RELOC_386_TLS_GD
:
9213 case BFD_RELOC_386_TLS_LDM
:
9214 case BFD_RELOC_386_TLS_IE
:
9215 case BFD_RELOC_386_TLS_IE_32
:
9216 case BFD_RELOC_386_TLS_GOTIE
:
9217 case BFD_RELOC_386_TLS_GOTDESC
:
9218 case BFD_RELOC_386_TLS_DESC_CALL
:
9219 case BFD_RELOC_X86_64_TLSGD
:
9220 case BFD_RELOC_X86_64_TLSLD
:
9221 case BFD_RELOC_X86_64_GOTTPOFF
:
9222 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
9223 case BFD_RELOC_X86_64_TLSDESC_CALL
:
9224 i
.has_gotpc_tls_reloc
= TRUE
;
9229 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
9230 size
, i
.op
[n
].disps
, pcrel
,
9232 /* Check for "call/jmp *mem", "mov mem, %reg",
9233 "test %reg, mem" and "binop mem, %reg" where binop
9234 is one of adc, add, and, cmp, or, sbb, sub, xor
9235 instructions without data prefix. Always generate
9236 R_386_GOT32X for "sym*GOT" operand in 32-bit mode. */
9237 if (i
.prefix
[DATA_PREFIX
] == 0
9238 && (generate_relax_relocations
9241 && i
.rm
.regmem
== 5))
9243 || (i
.rm
.mode
== 0 && i
.rm
.regmem
== 5))
9244 && !is_any_vex_encoding(&i
.tm
)
9245 && ((i
.operands
== 1
9246 && i
.tm
.base_opcode
== 0xff
9247 && (i
.rm
.reg
== 2 || i
.rm
.reg
== 4))
9249 && (i
.tm
.base_opcode
== 0x8b
9250 || i
.tm
.base_opcode
== 0x85
9251 || (i
.tm
.base_opcode
& ~0x38) == 0x03))))
9255 fixP
->fx_tcbit
= i
.rex
!= 0;
9257 && (i
.base_reg
->reg_num
== RegIP
))
9258 fixP
->fx_tcbit2
= 1;
9261 fixP
->fx_tcbit2
= 1;
9269 output_imm (fragS
*insn_start_frag
, offsetT insn_start_off
)
9274 for (n
= 0; n
< i
.operands
; n
++)
9276 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
9277 if (i
.rounding
&& (int) n
== i
.rounding
->operand
)
9280 if (operand_type_check (i
.types
[n
], imm
))
9282 if (i
.op
[n
].imms
->X_op
== O_constant
)
9284 int size
= imm_size (n
);
9287 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
9289 p
= frag_more (size
);
9290 md_number_to_chars (p
, val
, size
);
9294 /* Not absolute_section.
9295 Need a 32-bit fixup (don't support 8bit
9296 non-absolute imms). Try to support other
9298 enum bfd_reloc_code_real reloc_type
;
9299 int size
= imm_size (n
);
9302 if (i
.types
[n
].bitfield
.imm32s
9303 && (i
.suffix
== QWORD_MNEM_SUFFIX
9304 || (!i
.suffix
&& i
.tm
.opcode_modifier
.no_lsuf
)))
9309 p
= frag_more (size
);
9310 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
9312 /* This is tough to explain. We end up with this one if we
9313 * have operands that look like
9314 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
9315 * obtain the absolute address of the GOT, and it is strongly
9316 * preferable from a performance point of view to avoid using
9317 * a runtime relocation for this. The actual sequence of
9318 * instructions often look something like:
9323 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
9325 * The call and pop essentially return the absolute address
9326 * of the label .L66 and store it in %ebx. The linker itself
9327 * will ultimately change the first operand of the addl so
9328 * that %ebx points to the GOT, but to keep things simple, the
9329 * .o file must have this operand set so that it generates not
9330 * the absolute address of .L66, but the absolute address of
9331 * itself. This allows the linker itself simply treat a GOTPC
9332 * relocation as asking for a pcrel offset to the GOT to be
9333 * added in, and the addend of the relocation is stored in the
9334 * operand field for the instruction itself.
9336 * Our job here is to fix the operand so that it would add
9337 * the correct offset so that %ebx would point to itself. The
9338 * thing that is tricky is that .-.L66 will point to the
9339 * beginning of the instruction, so we need to further modify
9340 * the operand so that it will point to itself. There are
9341 * other cases where you have something like:
9343 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
9345 * and here no correction would be required. Internally in
9346 * the assembler we treat operands of this form as not being
9347 * pcrel since the '.' is explicitly mentioned, and I wonder
9348 * whether it would simplify matters to do it this way. Who
9349 * knows. In earlier versions of the PIC patches, the
9350 * pcrel_adjust field was used to store the correction, but
9351 * since the expression is not pcrel, I felt it would be
9352 * confusing to do it this way. */
9354 if ((reloc_type
== BFD_RELOC_32
9355 || reloc_type
== BFD_RELOC_X86_64_32S
9356 || reloc_type
== BFD_RELOC_64
)
9358 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
9359 && (i
.op
[n
].imms
->X_op
== O_symbol
9360 || (i
.op
[n
].imms
->X_op
== O_add
9361 && ((symbol_get_value_expression
9362 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
9366 reloc_type
= BFD_RELOC_386_GOTPC
;
9368 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
9370 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
9371 i
.has_gotpc_tls_reloc
= TRUE
;
9372 i
.op
[n
].imms
->X_add_number
+=
9373 encoding_length (insn_start_frag
, insn_start_off
, p
);
9375 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
9376 i
.op
[n
].imms
, 0, reloc_type
);
9382 /* x86_cons_fix_new is called via the expression parsing code when a
9383 reloc is needed. We use this hook to get the correct .got reloc. */
9384 static int cons_sign
= -1;
9387 x86_cons_fix_new (fragS
*frag
, unsigned int off
, unsigned int len
,
9388 expressionS
*exp
, bfd_reloc_code_real_type r
)
9390 r
= reloc (len
, 0, cons_sign
, r
);
9393 if (exp
->X_op
== O_secrel
)
9395 exp
->X_op
= O_symbol
;
9396 r
= BFD_RELOC_32_SECREL
;
9400 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
9403 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
9404 purpose of the `.dc.a' internal pseudo-op. */
9407 x86_address_bytes (void)
9409 if ((stdoutput
->arch_info
->mach
& bfd_mach_x64_32
))
9411 return stdoutput
->arch_info
->bits_per_address
/ 8;
9414 #if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
9416 # define lex_got(reloc, adjust, types) NULL
9418 /* Parse operands of the form
9419 <symbol>@GOTOFF+<nnn>
9420 and similar .plt or .got references.
9422 If we find one, set up the correct relocation in RELOC and copy the
9423 input string, minus the `@GOTOFF' into a malloc'd buffer for
9424 parsing by the calling routine. Return this buffer, and if ADJUST
9425 is non-null set it to the length of the string we removed from the
9426 input line. Otherwise return NULL. */
9428 lex_got (enum bfd_reloc_code_real
*rel
,
9430 i386_operand_type
*types
)
9432 /* Some of the relocations depend on the size of what field is to
9433 be relocated. But in our callers i386_immediate and i386_displacement
9434 we don't yet know the operand size (this will be set by insn
9435 matching). Hence we record the word32 relocation here,
9436 and adjust the reloc according to the real size in reloc(). */
9437 static const struct {
9440 const enum bfd_reloc_code_real rel
[2];
9441 const i386_operand_type types64
;
9443 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9444 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32
,
9446 OPERAND_TYPE_IMM32_64
},
9448 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real
,
9449 BFD_RELOC_X86_64_PLTOFF64
},
9450 OPERAND_TYPE_IMM64
},
9451 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32
,
9452 BFD_RELOC_X86_64_PLT32
},
9453 OPERAND_TYPE_IMM32_32S_DISP32
},
9454 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real
,
9455 BFD_RELOC_X86_64_GOTPLT64
},
9456 OPERAND_TYPE_IMM64_DISP64
},
9457 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF
,
9458 BFD_RELOC_X86_64_GOTOFF64
},
9459 OPERAND_TYPE_IMM64_DISP64
},
9460 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real
,
9461 BFD_RELOC_X86_64_GOTPCREL
},
9462 OPERAND_TYPE_IMM32_32S_DISP32
},
9463 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD
,
9464 BFD_RELOC_X86_64_TLSGD
},
9465 OPERAND_TYPE_IMM32_32S_DISP32
},
9466 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM
,
9467 _dummy_first_bfd_reloc_code_real
},
9468 OPERAND_TYPE_NONE
},
9469 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real
,
9470 BFD_RELOC_X86_64_TLSLD
},
9471 OPERAND_TYPE_IMM32_32S_DISP32
},
9472 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32
,
9473 BFD_RELOC_X86_64_GOTTPOFF
},
9474 OPERAND_TYPE_IMM32_32S_DISP32
},
9475 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32
,
9476 BFD_RELOC_X86_64_TPOFF32
},
9477 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
9478 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE
,
9479 _dummy_first_bfd_reloc_code_real
},
9480 OPERAND_TYPE_NONE
},
9481 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32
,
9482 BFD_RELOC_X86_64_DTPOFF32
},
9483 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
9484 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE
,
9485 _dummy_first_bfd_reloc_code_real
},
9486 OPERAND_TYPE_NONE
},
9487 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE
,
9488 _dummy_first_bfd_reloc_code_real
},
9489 OPERAND_TYPE_NONE
},
9490 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32
,
9491 BFD_RELOC_X86_64_GOT32
},
9492 OPERAND_TYPE_IMM32_32S_64_DISP32
},
9493 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC
,
9494 BFD_RELOC_X86_64_GOTPC32_TLSDESC
},
9495 OPERAND_TYPE_IMM32_32S_DISP32
},
9496 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL
,
9497 BFD_RELOC_X86_64_TLSDESC_CALL
},
9498 OPERAND_TYPE_IMM32_32S_DISP32
},
9503 #if defined (OBJ_MAYBE_ELF)
9508 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
9509 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
9512 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
9514 int len
= gotrel
[j
].len
;
9515 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
9517 if (gotrel
[j
].rel
[object_64bit
] != 0)
9520 char *tmpbuf
, *past_reloc
;
9522 *rel
= gotrel
[j
].rel
[object_64bit
];
9526 if (flag_code
!= CODE_64BIT
)
9528 types
->bitfield
.imm32
= 1;
9529 types
->bitfield
.disp32
= 1;
9532 *types
= gotrel
[j
].types64
;
9535 if (j
!= 0 && GOT_symbol
== NULL
)
9536 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
9538 /* The length of the first part of our input line. */
9539 first
= cp
- input_line_pointer
;
9541 /* The second part goes from after the reloc token until
9542 (and including) an end_of_line char or comma. */
9543 past_reloc
= cp
+ 1 + len
;
9545 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
9547 second
= cp
+ 1 - past_reloc
;
9549 /* Allocate and copy string. The trailing NUL shouldn't
9550 be necessary, but be safe. */
9551 tmpbuf
= XNEWVEC (char, first
+ second
+ 2);
9552 memcpy (tmpbuf
, input_line_pointer
, first
);
9553 if (second
!= 0 && *past_reloc
!= ' ')
9554 /* Replace the relocation token with ' ', so that
9555 errors like foo@GOTOFF1 will be detected. */
9556 tmpbuf
[first
++] = ' ';
9558 /* Increment length by 1 if the relocation token is
9563 memcpy (tmpbuf
+ first
, past_reloc
, second
);
9564 tmpbuf
[first
+ second
] = '\0';
9568 as_bad (_("@%s reloc is not supported with %d-bit output format"),
9569 gotrel
[j
].str
, 1 << (5 + object_64bit
));
9574 /* Might be a symbol version string. Don't as_bad here. */
9583 /* Parse operands of the form
9584 <symbol>@SECREL32+<nnn>
9586 If we find one, set up the correct relocation in RELOC and copy the
9587 input string, minus the `@SECREL32' into a malloc'd buffer for
9588 parsing by the calling routine. Return this buffer, and if ADJUST
9589 is non-null set it to the length of the string we removed from the
9590 input line. Otherwise return NULL.
9592 This function is copied from the ELF version above adjusted for PE targets. */
9595 lex_got (enum bfd_reloc_code_real
*rel ATTRIBUTE_UNUSED
,
9596 int *adjust ATTRIBUTE_UNUSED
,
9597 i386_operand_type
*types
)
9603 const enum bfd_reloc_code_real rel
[2];
9604 const i386_operand_type types64
;
9608 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL
,
9609 BFD_RELOC_32_SECREL
},
9610 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
9616 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
9617 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
9620 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
9622 int len
= gotrel
[j
].len
;
9624 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
9626 if (gotrel
[j
].rel
[object_64bit
] != 0)
9629 char *tmpbuf
, *past_reloc
;
9631 *rel
= gotrel
[j
].rel
[object_64bit
];
9637 if (flag_code
!= CODE_64BIT
)
9639 types
->bitfield
.imm32
= 1;
9640 types
->bitfield
.disp32
= 1;
9643 *types
= gotrel
[j
].types64
;
9646 /* The length of the first part of our input line. */
9647 first
= cp
- input_line_pointer
;
9649 /* The second part goes from after the reloc token until
9650 (and including) an end_of_line char or comma. */
9651 past_reloc
= cp
+ 1 + len
;
9653 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
9655 second
= cp
+ 1 - past_reloc
;
9657 /* Allocate and copy string. The trailing NUL shouldn't
9658 be necessary, but be safe. */
9659 tmpbuf
= XNEWVEC (char, first
+ second
+ 2);
9660 memcpy (tmpbuf
, input_line_pointer
, first
);
9661 if (second
!= 0 && *past_reloc
!= ' ')
9662 /* Replace the relocation token with ' ', so that
9663 errors like foo@SECLREL321 will be detected. */
9664 tmpbuf
[first
++] = ' ';
9665 memcpy (tmpbuf
+ first
, past_reloc
, second
);
9666 tmpbuf
[first
+ second
] = '\0';
9670 as_bad (_("@%s reloc is not supported with %d-bit output format"),
9671 gotrel
[j
].str
, 1 << (5 + object_64bit
));
9676 /* Might be a symbol version string. Don't as_bad here. */
9682 bfd_reloc_code_real_type
9683 x86_cons (expressionS
*exp
, int size
)
9685 bfd_reloc_code_real_type got_reloc
= NO_RELOC
;
9687 intel_syntax
= -intel_syntax
;
9690 if (size
== 4 || (object_64bit
&& size
== 8))
9692 /* Handle @GOTOFF and the like in an expression. */
9694 char *gotfree_input_line
;
9697 save
= input_line_pointer
;
9698 gotfree_input_line
= lex_got (&got_reloc
, &adjust
, NULL
);
9699 if (gotfree_input_line
)
9700 input_line_pointer
= gotfree_input_line
;
9704 if (gotfree_input_line
)
9706 /* expression () has merrily parsed up to the end of line,
9707 or a comma - in the wrong buffer. Transfer how far
9708 input_line_pointer has moved to the right buffer. */
9709 input_line_pointer
= (save
9710 + (input_line_pointer
- gotfree_input_line
)
9712 free (gotfree_input_line
);
9713 if (exp
->X_op
== O_constant
9714 || exp
->X_op
== O_absent
9715 || exp
->X_op
== O_illegal
9716 || exp
->X_op
== O_register
9717 || exp
->X_op
== O_big
)
9719 char c
= *input_line_pointer
;
9720 *input_line_pointer
= 0;
9721 as_bad (_("missing or invalid expression `%s'"), save
);
9722 *input_line_pointer
= c
;
9724 else if ((got_reloc
== BFD_RELOC_386_PLT32
9725 || got_reloc
== BFD_RELOC_X86_64_PLT32
)
9726 && exp
->X_op
!= O_symbol
)
9728 char c
= *input_line_pointer
;
9729 *input_line_pointer
= 0;
9730 as_bad (_("invalid PLT expression `%s'"), save
);
9731 *input_line_pointer
= c
;
9738 intel_syntax
= -intel_syntax
;
9741 i386_intel_simplify (exp
);
9747 signed_cons (int size
)
9749 if (flag_code
== CODE_64BIT
)
9757 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
9764 if (exp
.X_op
== O_symbol
)
9765 exp
.X_op
= O_secrel
;
9767 emit_expr (&exp
, 4);
9769 while (*input_line_pointer
++ == ',');
9771 input_line_pointer
--;
9772 demand_empty_rest_of_line ();
9776 /* Handle Vector operations. */
9779 check_VecOperations (char *op_string
, char *op_end
)
9781 const reg_entry
*mask
;
9786 && (op_end
== NULL
|| op_string
< op_end
))
9789 if (*op_string
== '{')
9793 /* Check broadcasts. */
9794 if (strncmp (op_string
, "1to", 3) == 0)
9799 goto duplicated_vec_op
;
9802 if (*op_string
== '8')
9804 else if (*op_string
== '4')
9806 else if (*op_string
== '2')
9808 else if (*op_string
== '1'
9809 && *(op_string
+1) == '6')
9816 as_bad (_("Unsupported broadcast: `%s'"), saved
);
9821 broadcast_op
.type
= bcst_type
;
9822 broadcast_op
.operand
= this_operand
;
9823 broadcast_op
.bytes
= 0;
9824 i
.broadcast
= &broadcast_op
;
9826 /* Check masking operation. */
9827 else if ((mask
= parse_register (op_string
, &end_op
)) != NULL
)
9829 /* k0 can't be used for write mask. */
9830 if (mask
->reg_type
.bitfield
.class != RegMask
|| !mask
->reg_num
)
9832 as_bad (_("`%s%s' can't be used for write mask"),
9833 register_prefix
, mask
->reg_name
);
9839 mask_op
.mask
= mask
;
9840 mask_op
.zeroing
= 0;
9841 mask_op
.operand
= this_operand
;
9847 goto duplicated_vec_op
;
9849 i
.mask
->mask
= mask
;
9851 /* Only "{z}" is allowed here. No need to check
9852 zeroing mask explicitly. */
9853 if (i
.mask
->operand
!= this_operand
)
9855 as_bad (_("invalid write mask `%s'"), saved
);
9862 /* Check zeroing-flag for masking operation. */
9863 else if (*op_string
== 'z')
9867 mask_op
.mask
= NULL
;
9868 mask_op
.zeroing
= 1;
9869 mask_op
.operand
= this_operand
;
9874 if (i
.mask
->zeroing
)
9877 as_bad (_("duplicated `%s'"), saved
);
9881 i
.mask
->zeroing
= 1;
9883 /* Only "{%k}" is allowed here. No need to check mask
9884 register explicitly. */
9885 if (i
.mask
->operand
!= this_operand
)
9887 as_bad (_("invalid zeroing-masking `%s'"),
9896 goto unknown_vec_op
;
9898 if (*op_string
!= '}')
9900 as_bad (_("missing `}' in `%s'"), saved
);
9905 /* Strip whitespace since the addition of pseudo prefixes
9906 changed how the scrubber treats '{'. */
9907 if (is_space_char (*op_string
))
9913 /* We don't know this one. */
9914 as_bad (_("unknown vector operation: `%s'"), saved
);
9918 if (i
.mask
&& i
.mask
->zeroing
&& !i
.mask
->mask
)
9920 as_bad (_("zeroing-masking only allowed with write mask"));
9928 i386_immediate (char *imm_start
)
9930 char *save_input_line_pointer
;
9931 char *gotfree_input_line
;
9934 i386_operand_type types
;
9936 operand_type_set (&types
, ~0);
9938 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
9940 as_bad (_("at most %d immediate operands are allowed"),
9941 MAX_IMMEDIATE_OPERANDS
);
9945 exp
= &im_expressions
[i
.imm_operands
++];
9946 i
.op
[this_operand
].imms
= exp
;
9948 if (is_space_char (*imm_start
))
9951 save_input_line_pointer
= input_line_pointer
;
9952 input_line_pointer
= imm_start
;
9954 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
9955 if (gotfree_input_line
)
9956 input_line_pointer
= gotfree_input_line
;
9958 exp_seg
= expression (exp
);
9962 /* Handle vector operations. */
9963 if (*input_line_pointer
== '{')
9965 input_line_pointer
= check_VecOperations (input_line_pointer
,
9967 if (input_line_pointer
== NULL
)
9971 if (*input_line_pointer
)
9972 as_bad (_("junk `%s' after expression"), input_line_pointer
);
9974 input_line_pointer
= save_input_line_pointer
;
9975 if (gotfree_input_line
)
9977 free (gotfree_input_line
);
9979 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
9980 exp
->X_op
= O_illegal
;
9983 return i386_finalize_immediate (exp_seg
, exp
, types
, imm_start
);
9987 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
9988 i386_operand_type types
, const char *imm_start
)
9990 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_illegal
|| exp
->X_op
== O_big
)
9993 as_bad (_("missing or invalid immediate expression `%s'"),
9997 else if (exp
->X_op
== O_constant
)
9999 /* Size it properly later. */
10000 i
.types
[this_operand
].bitfield
.imm64
= 1;
10001 /* If not 64bit, sign extend val. */
10002 if (flag_code
!= CODE_64BIT
10003 && (exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
10005 = (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
10007 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
10008 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
10009 && exp_seg
!= absolute_section
10010 && exp_seg
!= text_section
10011 && exp_seg
!= data_section
10012 && exp_seg
!= bss_section
10013 && exp_seg
!= undefined_section
10014 && !bfd_is_com_section (exp_seg
))
10016 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
10020 else if (!intel_syntax
&& exp_seg
== reg_section
)
10023 as_bad (_("illegal immediate register operand %s"), imm_start
);
10028 /* This is an address. The size of the address will be
10029 determined later, depending on destination register,
10030 suffix, or the default for the section. */
10031 i
.types
[this_operand
].bitfield
.imm8
= 1;
10032 i
.types
[this_operand
].bitfield
.imm16
= 1;
10033 i
.types
[this_operand
].bitfield
.imm32
= 1;
10034 i
.types
[this_operand
].bitfield
.imm32s
= 1;
10035 i
.types
[this_operand
].bitfield
.imm64
= 1;
10036 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
10044 i386_scale (char *scale
)
10047 char *save
= input_line_pointer
;
10049 input_line_pointer
= scale
;
10050 val
= get_absolute_expression ();
10055 i
.log2_scale_factor
= 0;
10058 i
.log2_scale_factor
= 1;
10061 i
.log2_scale_factor
= 2;
10064 i
.log2_scale_factor
= 3;
10068 char sep
= *input_line_pointer
;
10070 *input_line_pointer
= '\0';
10071 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
10073 *input_line_pointer
= sep
;
10074 input_line_pointer
= save
;
10078 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
10080 as_warn (_("scale factor of %d without an index register"),
10081 1 << i
.log2_scale_factor
);
10082 i
.log2_scale_factor
= 0;
10084 scale
= input_line_pointer
;
10085 input_line_pointer
= save
;
10090 i386_displacement (char *disp_start
, char *disp_end
)
10094 char *save_input_line_pointer
;
10095 char *gotfree_input_line
;
10097 i386_operand_type bigdisp
, types
= anydisp
;
10100 if (i
.disp_operands
== MAX_MEMORY_OPERANDS
)
10102 as_bad (_("at most %d displacement operands are allowed"),
10103 MAX_MEMORY_OPERANDS
);
10107 operand_type_set (&bigdisp
, 0);
10109 || i
.types
[this_operand
].bitfield
.baseindex
10110 || (current_templates
->start
->opcode_modifier
.jump
!= JUMP
10111 && current_templates
->start
->opcode_modifier
.jump
!= JUMP_DWORD
))
10113 i386_addressing_mode ();
10114 override
= (i
.prefix
[ADDR_PREFIX
] != 0);
10115 if (flag_code
== CODE_64BIT
)
10119 bigdisp
.bitfield
.disp32s
= 1;
10120 bigdisp
.bitfield
.disp64
= 1;
10123 bigdisp
.bitfield
.disp32
= 1;
10125 else if ((flag_code
== CODE_16BIT
) ^ override
)
10126 bigdisp
.bitfield
.disp16
= 1;
10128 bigdisp
.bitfield
.disp32
= 1;
10132 /* For PC-relative branches, the width of the displacement may be
10133 dependent upon data size, but is never dependent upon address size.
10134 Also make sure to not unintentionally match against a non-PC-relative
10135 branch template. */
10136 static templates aux_templates
;
10137 const insn_template
*t
= current_templates
->start
;
10138 bfd_boolean has_intel64
= FALSE
;
10140 aux_templates
.start
= t
;
10141 while (++t
< current_templates
->end
)
10143 if (t
->opcode_modifier
.jump
10144 != current_templates
->start
->opcode_modifier
.jump
)
10146 if ((t
->opcode_modifier
.isa64
>= INTEL64
))
10147 has_intel64
= TRUE
;
10149 if (t
< current_templates
->end
)
10151 aux_templates
.end
= t
;
10152 current_templates
= &aux_templates
;
10155 override
= (i
.prefix
[DATA_PREFIX
] != 0);
10156 if (flag_code
== CODE_64BIT
)
10158 if ((override
|| i
.suffix
== WORD_MNEM_SUFFIX
)
10159 && (!intel64
|| !has_intel64
))
10160 bigdisp
.bitfield
.disp16
= 1;
10162 bigdisp
.bitfield
.disp32s
= 1;
10167 override
= (i
.suffix
== (flag_code
!= CODE_16BIT
10169 : LONG_MNEM_SUFFIX
));
10170 bigdisp
.bitfield
.disp32
= 1;
10171 if ((flag_code
== CODE_16BIT
) ^ override
)
10173 bigdisp
.bitfield
.disp32
= 0;
10174 bigdisp
.bitfield
.disp16
= 1;
10178 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
10181 exp
= &disp_expressions
[i
.disp_operands
];
10182 i
.op
[this_operand
].disps
= exp
;
10184 save_input_line_pointer
= input_line_pointer
;
10185 input_line_pointer
= disp_start
;
10186 END_STRING_AND_SAVE (disp_end
);
10188 #ifndef GCC_ASM_O_HACK
10189 #define GCC_ASM_O_HACK 0
10192 END_STRING_AND_SAVE (disp_end
+ 1);
10193 if (i
.types
[this_operand
].bitfield
.baseIndex
10194 && displacement_string_end
[-1] == '+')
10196 /* This hack is to avoid a warning when using the "o"
10197 constraint within gcc asm statements.
10200 #define _set_tssldt_desc(n,addr,limit,type) \
10201 __asm__ __volatile__ ( \
10202 "movw %w2,%0\n\t" \
10203 "movw %w1,2+%0\n\t" \
10204 "rorl $16,%1\n\t" \
10205 "movb %b1,4+%0\n\t" \
10206 "movb %4,5+%0\n\t" \
10207 "movb $0,6+%0\n\t" \
10208 "movb %h1,7+%0\n\t" \
10210 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
10212 This works great except that the output assembler ends
10213 up looking a bit weird if it turns out that there is
10214 no offset. You end up producing code that looks like:
10227 So here we provide the missing zero. */
10229 *displacement_string_end
= '0';
10232 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
10233 if (gotfree_input_line
)
10234 input_line_pointer
= gotfree_input_line
;
10236 exp_seg
= expression (exp
);
10238 SKIP_WHITESPACE ();
10239 if (*input_line_pointer
)
10240 as_bad (_("junk `%s' after expression"), input_line_pointer
);
10242 RESTORE_END_STRING (disp_end
+ 1);
10244 input_line_pointer
= save_input_line_pointer
;
10245 if (gotfree_input_line
)
10247 free (gotfree_input_line
);
10249 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
10250 exp
->X_op
= O_illegal
;
10253 ret
= i386_finalize_displacement (exp_seg
, exp
, types
, disp_start
);
10255 RESTORE_END_STRING (disp_end
);
10261 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
10262 i386_operand_type types
, const char *disp_start
)
10264 i386_operand_type bigdisp
;
10267 /* We do this to make sure that the section symbol is in
10268 the symbol table. We will ultimately change the relocation
10269 to be relative to the beginning of the section. */
10270 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
10271 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
10272 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
10274 if (exp
->X_op
!= O_symbol
)
10277 if (S_IS_LOCAL (exp
->X_add_symbol
)
10278 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
10279 && S_GET_SEGMENT (exp
->X_add_symbol
) != expr_section
)
10280 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
10281 exp
->X_op
= O_subtract
;
10282 exp
->X_op_symbol
= GOT_symbol
;
10283 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
10284 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
10285 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
10286 i
.reloc
[this_operand
] = BFD_RELOC_64
;
10288 i
.reloc
[this_operand
] = BFD_RELOC_32
;
10291 else if (exp
->X_op
== O_absent
10292 || exp
->X_op
== O_illegal
10293 || exp
->X_op
== O_big
)
10296 as_bad (_("missing or invalid displacement expression `%s'"),
10301 else if (flag_code
== CODE_64BIT
10302 && !i
.prefix
[ADDR_PREFIX
]
10303 && exp
->X_op
== O_constant
)
10305 /* Since displacement is signed extended to 64bit, don't allow
10306 disp32 and turn off disp32s if they are out of range. */
10307 i
.types
[this_operand
].bitfield
.disp32
= 0;
10308 if (!fits_in_signed_long (exp
->X_add_number
))
10310 i
.types
[this_operand
].bitfield
.disp32s
= 0;
10311 if (i
.types
[this_operand
].bitfield
.baseindex
)
10313 as_bad (_("0x%lx out range of signed 32bit displacement"),
10314 (long) exp
->X_add_number
);
10320 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
10321 else if (exp
->X_op
!= O_constant
10322 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
10323 && exp_seg
!= absolute_section
10324 && exp_seg
!= text_section
10325 && exp_seg
!= data_section
10326 && exp_seg
!= bss_section
10327 && exp_seg
!= undefined_section
10328 && !bfd_is_com_section (exp_seg
))
10330 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
10335 if (current_templates
->start
->opcode_modifier
.jump
== JUMP_BYTE
10336 /* Constants get taken care of by optimize_disp(). */
10337 && exp
->X_op
!= O_constant
)
10338 i
.types
[this_operand
].bitfield
.disp8
= 1;
10340 /* Check if this is a displacement only operand. */
10341 bigdisp
= i
.types
[this_operand
];
10342 bigdisp
.bitfield
.disp8
= 0;
10343 bigdisp
.bitfield
.disp16
= 0;
10344 bigdisp
.bitfield
.disp32
= 0;
10345 bigdisp
.bitfield
.disp32s
= 0;
10346 bigdisp
.bitfield
.disp64
= 0;
10347 if (operand_type_all_zero (&bigdisp
))
10348 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
10354 /* Return the active addressing mode, taking address override and
10355 registers forming the address into consideration. Update the
10356 address override prefix if necessary. */
10358 static enum flag_code
10359 i386_addressing_mode (void)
10361 enum flag_code addr_mode
;
10363 if (i
.prefix
[ADDR_PREFIX
])
10364 addr_mode
= flag_code
== CODE_32BIT
? CODE_16BIT
: CODE_32BIT
;
10365 else if (flag_code
== CODE_16BIT
10366 && current_templates
->start
->cpu_flags
.bitfield
.cpumpx
10367 /* Avoid replacing the "16-bit addressing not allowed" diagnostic
10368 from md_assemble() by "is not a valid base/index expression"
10369 when there is a base and/or index. */
10370 && !i
.types
[this_operand
].bitfield
.baseindex
)
10372 /* MPX insn memory operands with neither base nor index must be forced
10373 to use 32-bit addressing in 16-bit mode. */
10374 addr_mode
= CODE_32BIT
;
10375 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
10377 gas_assert (!i
.types
[this_operand
].bitfield
.disp16
);
10378 gas_assert (!i
.types
[this_operand
].bitfield
.disp32
);
10382 addr_mode
= flag_code
;
10384 #if INFER_ADDR_PREFIX
10385 if (i
.mem_operands
== 0)
10387 /* Infer address prefix from the first memory operand. */
10388 const reg_entry
*addr_reg
= i
.base_reg
;
10390 if (addr_reg
== NULL
)
10391 addr_reg
= i
.index_reg
;
10395 if (addr_reg
->reg_type
.bitfield
.dword
)
10396 addr_mode
= CODE_32BIT
;
10397 else if (flag_code
!= CODE_64BIT
10398 && addr_reg
->reg_type
.bitfield
.word
)
10399 addr_mode
= CODE_16BIT
;
10401 if (addr_mode
!= flag_code
)
10403 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
10405 /* Change the size of any displacement too. At most one
10406 of Disp16 or Disp32 is set.
10407 FIXME. There doesn't seem to be any real need for
10408 separate Disp16 and Disp32 flags. The same goes for
10409 Imm16 and Imm32. Removing them would probably clean
10410 up the code quite a lot. */
10411 if (flag_code
!= CODE_64BIT
10412 && (i
.types
[this_operand
].bitfield
.disp16
10413 || i
.types
[this_operand
].bitfield
.disp32
))
10414 i
.types
[this_operand
]
10415 = operand_type_xor (i
.types
[this_operand
], disp16_32
);
10425 /* Make sure the memory operand we've been dealt is valid.
10426 Return 1 on success, 0 on a failure. */
10429 i386_index_check (const char *operand_string
)
10431 const char *kind
= "base/index";
10432 enum flag_code addr_mode
= i386_addressing_mode ();
10434 if (current_templates
->start
->opcode_modifier
.isstring
10435 && !current_templates
->start
->cpu_flags
.bitfield
.cpupadlock
10436 && (current_templates
->end
[-1].opcode_modifier
.isstring
10437 || i
.mem_operands
))
10439 /* Memory operands of string insns are special in that they only allow
10440 a single register (rDI, rSI, or rBX) as their memory address. */
10441 const reg_entry
*expected_reg
;
10442 static const char *di_si
[][2] =
10448 static const char *bx
[] = { "ebx", "bx", "rbx" };
10450 kind
= "string address";
10452 if (current_templates
->start
->opcode_modifier
.repprefixok
)
10454 int es_op
= current_templates
->end
[-1].opcode_modifier
.isstring
10455 - IS_STRING_ES_OP0
;
10458 if (!current_templates
->end
[-1].operand_types
[0].bitfield
.baseindex
10459 || ((!i
.mem_operands
!= !intel_syntax
)
10460 && current_templates
->end
[-1].operand_types
[1]
10461 .bitfield
.baseindex
))
10463 expected_reg
= hash_find (reg_hash
, di_si
[addr_mode
][op
== es_op
]);
10466 expected_reg
= hash_find (reg_hash
, bx
[addr_mode
]);
10468 if (i
.base_reg
!= expected_reg
10470 || operand_type_check (i
.types
[this_operand
], disp
))
10472 /* The second memory operand must have the same size as
10476 && !((addr_mode
== CODE_64BIT
10477 && i
.base_reg
->reg_type
.bitfield
.qword
)
10478 || (addr_mode
== CODE_32BIT
10479 ? i
.base_reg
->reg_type
.bitfield
.dword
10480 : i
.base_reg
->reg_type
.bitfield
.word
)))
10483 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
10485 intel_syntax
? '[' : '(',
10487 expected_reg
->reg_name
,
10488 intel_syntax
? ']' : ')');
10495 as_bad (_("`%s' is not a valid %s expression"),
10496 operand_string
, kind
);
10501 if (addr_mode
!= CODE_16BIT
)
10503 /* 32-bit/64-bit checks. */
10505 && ((addr_mode
== CODE_64BIT
10506 ? !i
.base_reg
->reg_type
.bitfield
.qword
10507 : !i
.base_reg
->reg_type
.bitfield
.dword
)
10508 || (i
.index_reg
&& i
.base_reg
->reg_num
== RegIP
)
10509 || i
.base_reg
->reg_num
== RegIZ
))
10511 && !i
.index_reg
->reg_type
.bitfield
.xmmword
10512 && !i
.index_reg
->reg_type
.bitfield
.ymmword
10513 && !i
.index_reg
->reg_type
.bitfield
.zmmword
10514 && ((addr_mode
== CODE_64BIT
10515 ? !i
.index_reg
->reg_type
.bitfield
.qword
10516 : !i
.index_reg
->reg_type
.bitfield
.dword
)
10517 || !i
.index_reg
->reg_type
.bitfield
.baseindex
)))
10520 /* bndmk, bndldx, and bndstx have special restrictions. */
10521 if (current_templates
->start
->base_opcode
== 0xf30f1b
10522 || (current_templates
->start
->base_opcode
& ~1) == 0x0f1a)
10524 /* They cannot use RIP-relative addressing. */
10525 if (i
.base_reg
&& i
.base_reg
->reg_num
== RegIP
)
10527 as_bad (_("`%s' cannot be used here"), operand_string
);
10531 /* bndldx and bndstx ignore their scale factor. */
10532 if (current_templates
->start
->base_opcode
!= 0xf30f1b
10533 && i
.log2_scale_factor
)
10534 as_warn (_("register scaling is being ignored here"));
10539 /* 16-bit checks. */
10541 && (!i
.base_reg
->reg_type
.bitfield
.word
10542 || !i
.base_reg
->reg_type
.bitfield
.baseindex
))
10544 && (!i
.index_reg
->reg_type
.bitfield
.word
10545 || !i
.index_reg
->reg_type
.bitfield
.baseindex
10547 && i
.base_reg
->reg_num
< 6
10548 && i
.index_reg
->reg_num
>= 6
10549 && i
.log2_scale_factor
== 0))))
10556 /* Handle vector immediates. */
10559 RC_SAE_immediate (const char *imm_start
)
10561 unsigned int match_found
, j
;
10562 const char *pstr
= imm_start
;
10570 for (j
= 0; j
< ARRAY_SIZE (RC_NamesTable
); j
++)
10572 if (!strncmp (pstr
, RC_NamesTable
[j
].name
, RC_NamesTable
[j
].len
))
10576 rc_op
.type
= RC_NamesTable
[j
].type
;
10577 rc_op
.operand
= this_operand
;
10578 i
.rounding
= &rc_op
;
10582 as_bad (_("duplicated `%s'"), imm_start
);
10585 pstr
+= RC_NamesTable
[j
].len
;
10593 if (*pstr
++ != '}')
10595 as_bad (_("Missing '}': '%s'"), imm_start
);
10598 /* RC/SAE immediate string should contain nothing more. */;
10601 as_bad (_("Junk after '}': '%s'"), imm_start
);
10605 exp
= &im_expressions
[i
.imm_operands
++];
10606 i
.op
[this_operand
].imms
= exp
;
10608 exp
->X_op
= O_constant
;
10609 exp
->X_add_number
= 0;
10610 exp
->X_add_symbol
= (symbolS
*) 0;
10611 exp
->X_op_symbol
= (symbolS
*) 0;
10613 i
.types
[this_operand
].bitfield
.imm8
= 1;
10617 /* Only string instructions can have a second memory operand, so
10618 reduce current_templates to just those if it contains any. */
10620 maybe_adjust_templates (void)
10622 const insn_template
*t
;
10624 gas_assert (i
.mem_operands
== 1);
10626 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
10627 if (t
->opcode_modifier
.isstring
)
10630 if (t
< current_templates
->end
)
10632 static templates aux_templates
;
10633 bfd_boolean recheck
;
10635 aux_templates
.start
= t
;
10636 for (; t
< current_templates
->end
; ++t
)
10637 if (!t
->opcode_modifier
.isstring
)
10639 aux_templates
.end
= t
;
10641 /* Determine whether to re-check the first memory operand. */
10642 recheck
= (aux_templates
.start
!= current_templates
->start
10643 || t
!= current_templates
->end
);
10645 current_templates
= &aux_templates
;
10649 i
.mem_operands
= 0;
10650 if (i
.memop1_string
!= NULL
10651 && i386_index_check (i
.memop1_string
) == 0)
10653 i
.mem_operands
= 1;
10660 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
10664 i386_att_operand (char *operand_string
)
10666 const reg_entry
*r
;
10668 char *op_string
= operand_string
;
10670 if (is_space_char (*op_string
))
10673 /* We check for an absolute prefix (differentiating,
10674 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
10675 if (*op_string
== ABSOLUTE_PREFIX
)
10678 if (is_space_char (*op_string
))
10680 i
.jumpabsolute
= TRUE
;
10683 /* Check if operand is a register. */
10684 if ((r
= parse_register (op_string
, &end_op
)) != NULL
)
10686 i386_operand_type temp
;
10688 /* Check for a segment override by searching for ':' after a
10689 segment register. */
10690 op_string
= end_op
;
10691 if (is_space_char (*op_string
))
10693 if (*op_string
== ':' && r
->reg_type
.bitfield
.class == SReg
)
10695 switch (r
->reg_num
)
10698 i
.seg
[i
.mem_operands
] = &es
;
10701 i
.seg
[i
.mem_operands
] = &cs
;
10704 i
.seg
[i
.mem_operands
] = &ss
;
10707 i
.seg
[i
.mem_operands
] = &ds
;
10710 i
.seg
[i
.mem_operands
] = &fs
;
10713 i
.seg
[i
.mem_operands
] = &gs
;
10717 /* Skip the ':' and whitespace. */
10719 if (is_space_char (*op_string
))
10722 if (!is_digit_char (*op_string
)
10723 && !is_identifier_char (*op_string
)
10724 && *op_string
!= '('
10725 && *op_string
!= ABSOLUTE_PREFIX
)
10727 as_bad (_("bad memory operand `%s'"), op_string
);
10730 /* Handle case of %es:*foo. */
10731 if (*op_string
== ABSOLUTE_PREFIX
)
10734 if (is_space_char (*op_string
))
10736 i
.jumpabsolute
= TRUE
;
10738 goto do_memory_reference
;
10741 /* Handle vector operations. */
10742 if (*op_string
== '{')
10744 op_string
= check_VecOperations (op_string
, NULL
);
10745 if (op_string
== NULL
)
10751 as_bad (_("junk `%s' after register"), op_string
);
10754 temp
= r
->reg_type
;
10755 temp
.bitfield
.baseindex
= 0;
10756 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
10758 i
.types
[this_operand
].bitfield
.unspecified
= 0;
10759 i
.op
[this_operand
].regs
= r
;
10762 else if (*op_string
== REGISTER_PREFIX
)
10764 as_bad (_("bad register name `%s'"), op_string
);
10767 else if (*op_string
== IMMEDIATE_PREFIX
)
10770 if (i
.jumpabsolute
)
10772 as_bad (_("immediate operand illegal with absolute jump"));
10775 if (!i386_immediate (op_string
))
10778 else if (RC_SAE_immediate (operand_string
))
10780 /* If it is a RC or SAE immediate, do nothing. */
10783 else if (is_digit_char (*op_string
)
10784 || is_identifier_char (*op_string
)
10785 || *op_string
== '"'
10786 || *op_string
== '(')
10788 /* This is a memory reference of some sort. */
10791 /* Start and end of displacement string expression (if found). */
10792 char *displacement_string_start
;
10793 char *displacement_string_end
;
10796 do_memory_reference
:
10797 if (i
.mem_operands
== 1 && !maybe_adjust_templates ())
10799 if ((i
.mem_operands
== 1
10800 && !current_templates
->start
->opcode_modifier
.isstring
)
10801 || i
.mem_operands
== 2)
10803 as_bad (_("too many memory references for `%s'"),
10804 current_templates
->start
->name
);
10808 /* Check for base index form. We detect the base index form by
10809 looking for an ')' at the end of the operand, searching
10810 for the '(' matching it, and finding a REGISTER_PREFIX or ','
10812 base_string
= op_string
+ strlen (op_string
);
10814 /* Handle vector operations. */
10815 vop_start
= strchr (op_string
, '{');
10816 if (vop_start
&& vop_start
< base_string
)
10818 if (check_VecOperations (vop_start
, base_string
) == NULL
)
10820 base_string
= vop_start
;
10824 if (is_space_char (*base_string
))
10827 /* If we only have a displacement, set-up for it to be parsed later. */
10828 displacement_string_start
= op_string
;
10829 displacement_string_end
= base_string
+ 1;
10831 if (*base_string
== ')')
10834 unsigned int parens_balanced
= 1;
10835 /* We've already checked that the number of left & right ()'s are
10836 equal, so this loop will not be infinite. */
10840 if (*base_string
== ')')
10842 if (*base_string
== '(')
10845 while (parens_balanced
);
10847 temp_string
= base_string
;
10849 /* Skip past '(' and whitespace. */
10851 if (is_space_char (*base_string
))
10854 if (*base_string
== ','
10855 || ((i
.base_reg
= parse_register (base_string
, &end_op
))
10858 displacement_string_end
= temp_string
;
10860 i
.types
[this_operand
].bitfield
.baseindex
= 1;
10864 base_string
= end_op
;
10865 if (is_space_char (*base_string
))
10869 /* There may be an index reg or scale factor here. */
10870 if (*base_string
== ',')
10873 if (is_space_char (*base_string
))
10876 if ((i
.index_reg
= parse_register (base_string
, &end_op
))
10879 base_string
= end_op
;
10880 if (is_space_char (*base_string
))
10882 if (*base_string
== ',')
10885 if (is_space_char (*base_string
))
10888 else if (*base_string
!= ')')
10890 as_bad (_("expecting `,' or `)' "
10891 "after index register in `%s'"),
10896 else if (*base_string
== REGISTER_PREFIX
)
10898 end_op
= strchr (base_string
, ',');
10901 as_bad (_("bad register name `%s'"), base_string
);
10905 /* Check for scale factor. */
10906 if (*base_string
!= ')')
10908 char *end_scale
= i386_scale (base_string
);
10913 base_string
= end_scale
;
10914 if (is_space_char (*base_string
))
10916 if (*base_string
!= ')')
10918 as_bad (_("expecting `)' "
10919 "after scale factor in `%s'"),
10924 else if (!i
.index_reg
)
10926 as_bad (_("expecting index register or scale factor "
10927 "after `,'; got '%c'"),
10932 else if (*base_string
!= ')')
10934 as_bad (_("expecting `,' or `)' "
10935 "after base register in `%s'"),
10940 else if (*base_string
== REGISTER_PREFIX
)
10942 end_op
= strchr (base_string
, ',');
10945 as_bad (_("bad register name `%s'"), base_string
);
10950 /* If there's an expression beginning the operand, parse it,
10951 assuming displacement_string_start and
10952 displacement_string_end are meaningful. */
10953 if (displacement_string_start
!= displacement_string_end
)
10955 if (!i386_displacement (displacement_string_start
,
10956 displacement_string_end
))
10960 /* Special case for (%dx) while doing input/output op. */
10962 && i
.base_reg
->reg_type
.bitfield
.instance
== RegD
10963 && i
.base_reg
->reg_type
.bitfield
.word
10964 && i
.index_reg
== 0
10965 && i
.log2_scale_factor
== 0
10966 && i
.seg
[i
.mem_operands
] == 0
10967 && !operand_type_check (i
.types
[this_operand
], disp
))
10969 i
.types
[this_operand
] = i
.base_reg
->reg_type
;
10973 if (i386_index_check (operand_string
) == 0)
10975 i
.flags
[this_operand
] |= Operand_Mem
;
10976 if (i
.mem_operands
== 0)
10977 i
.memop1_string
= xstrdup (operand_string
);
10982 /* It's not a memory operand; argh! */
10983 as_bad (_("invalid char %s beginning operand %d `%s'"),
10984 output_invalid (*op_string
),
10989 return 1; /* Normal return. */
10992 /* Calculate the maximum variable size (i.e., excluding fr_fix)
10993 that an rs_machine_dependent frag may reach. */
10996 i386_frag_max_var (fragS
*frag
)
10998 /* The only relaxable frags are for jumps.
10999 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
11000 gas_assert (frag
->fr_type
== rs_machine_dependent
);
11001 return TYPE_FROM_RELAX_STATE (frag
->fr_subtype
) == UNCOND_JUMP
? 4 : 5;
11004 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11006 elf_symbol_resolved_in_segment_p (symbolS
*fr_symbol
, offsetT fr_var
)
11008 /* STT_GNU_IFUNC symbol must go through PLT. */
11009 if ((symbol_get_bfdsym (fr_symbol
)->flags
11010 & BSF_GNU_INDIRECT_FUNCTION
) != 0)
11013 if (!S_IS_EXTERNAL (fr_symbol
))
11014 /* Symbol may be weak or local. */
11015 return !S_IS_WEAK (fr_symbol
);
11017 /* Global symbols with non-default visibility can't be preempted. */
11018 if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol
)) != STV_DEFAULT
)
11021 if (fr_var
!= NO_RELOC
)
11022 switch ((enum bfd_reloc_code_real
) fr_var
)
11024 case BFD_RELOC_386_PLT32
:
11025 case BFD_RELOC_X86_64_PLT32
:
11026 /* Symbol with PLT relocation may be preempted. */
11032 /* Global symbols with default visibility in a shared library may be
11033 preempted by another definition. */
11038 /* Table 3-2. Macro-Fusible Instructions in Haswell Microarchitecture
11039 Note also work for Skylake and Cascadelake.
11040 ---------------------------------------------------------------------
11041 | JCC | ADD/SUB/CMP | INC/DEC | TEST/AND |
11042 | ------ | ----------- | ------- | -------- |
11044 | Jno | N | N | Y |
11045 | Jc/Jb | Y | N | Y |
11046 | Jae/Jnb | Y | N | Y |
11047 | Je/Jz | Y | Y | Y |
11048 | Jne/Jnz | Y | Y | Y |
11049 | Jna/Jbe | Y | N | Y |
11050 | Ja/Jnbe | Y | N | Y |
11052 | Jns | N | N | Y |
11053 | Jp/Jpe | N | N | Y |
11054 | Jnp/Jpo | N | N | Y |
11055 | Jl/Jnge | Y | Y | Y |
11056 | Jge/Jnl | Y | Y | Y |
11057 | Jle/Jng | Y | Y | Y |
11058 | Jg/Jnle | Y | Y | Y |
11059 --------------------------------------------------------------------- */
11061 i386_macro_fusible_p (enum mf_cmp_kind mf_cmp
, enum mf_jcc_kind mf_jcc
)
11063 if (mf_cmp
== mf_cmp_alu_cmp
)
11064 return ((mf_jcc
>= mf_jcc_jc
&& mf_jcc
<= mf_jcc_jna
)
11065 || mf_jcc
== mf_jcc_jl
|| mf_jcc
== mf_jcc_jle
);
11066 if (mf_cmp
== mf_cmp_incdec
)
11067 return (mf_jcc
== mf_jcc_je
|| mf_jcc
== mf_jcc_jl
11068 || mf_jcc
== mf_jcc_jle
);
11069 if (mf_cmp
== mf_cmp_test_and
)
11074 /* Return the next non-empty frag. */
11077 i386_next_non_empty_frag (fragS
*fragP
)
11079 /* There may be a frag with a ".fill 0" when there is no room in
11080 the current frag for frag_grow in output_insn. */
11081 for (fragP
= fragP
->fr_next
;
11083 && fragP
->fr_type
== rs_fill
11084 && fragP
->fr_fix
== 0);
11085 fragP
= fragP
->fr_next
)
11090 /* Return the next jcc frag after BRANCH_PADDING. */
11093 i386_next_fusible_jcc_frag (fragS
*maybe_cmp_fragP
, fragS
*pad_fragP
)
11095 fragS
*branch_fragP
;
11099 if (pad_fragP
->fr_type
== rs_machine_dependent
11100 && (TYPE_FROM_RELAX_STATE (pad_fragP
->fr_subtype
)
11101 == BRANCH_PADDING
))
11103 branch_fragP
= i386_next_non_empty_frag (pad_fragP
);
11104 if (branch_fragP
->fr_type
!= rs_machine_dependent
)
11106 if (TYPE_FROM_RELAX_STATE (branch_fragP
->fr_subtype
) == COND_JUMP
11107 && i386_macro_fusible_p (maybe_cmp_fragP
->tc_frag_data
.mf_type
,
11108 pad_fragP
->tc_frag_data
.mf_type
))
11109 return branch_fragP
;
11115 /* Classify BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING frags. */
11118 i386_classify_machine_dependent_frag (fragS
*fragP
)
11122 fragS
*branch_fragP
;
11124 unsigned int max_prefix_length
;
11126 if (fragP
->tc_frag_data
.classified
)
11129 /* First scan for BRANCH_PADDING and FUSED_JCC_PADDING. Convert
11130 FUSED_JCC_PADDING and merge BRANCH_PADDING. */
11131 for (next_fragP
= fragP
;
11132 next_fragP
!= NULL
;
11133 next_fragP
= next_fragP
->fr_next
)
11135 next_fragP
->tc_frag_data
.classified
= 1;
11136 if (next_fragP
->fr_type
== rs_machine_dependent
)
11137 switch (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
))
11139 case BRANCH_PADDING
:
11140 /* The BRANCH_PADDING frag must be followed by a branch
11142 branch_fragP
= i386_next_non_empty_frag (next_fragP
);
11143 next_fragP
->tc_frag_data
.u
.branch_fragP
= branch_fragP
;
11145 case FUSED_JCC_PADDING
:
11146 /* Check if this is a fused jcc:
11148 CMP like instruction
11152 cmp_fragP
= i386_next_non_empty_frag (next_fragP
);
11153 pad_fragP
= i386_next_non_empty_frag (cmp_fragP
);
11154 branch_fragP
= i386_next_fusible_jcc_frag (next_fragP
, pad_fragP
);
11157 /* The BRANCH_PADDING frag is merged with the
11158 FUSED_JCC_PADDING frag. */
11159 next_fragP
->tc_frag_data
.u
.branch_fragP
= branch_fragP
;
11160 /* CMP like instruction size. */
11161 next_fragP
->tc_frag_data
.cmp_size
= cmp_fragP
->fr_fix
;
11162 frag_wane (pad_fragP
);
11163 /* Skip to branch_fragP. */
11164 next_fragP
= branch_fragP
;
11166 else if (next_fragP
->tc_frag_data
.max_prefix_length
)
11168 /* Turn FUSED_JCC_PADDING into BRANCH_PREFIX if it isn't
11170 next_fragP
->fr_subtype
11171 = ENCODE_RELAX_STATE (BRANCH_PREFIX
, 0);
11172 next_fragP
->tc_frag_data
.max_bytes
11173 = next_fragP
->tc_frag_data
.max_prefix_length
;
11174 /* This will be updated in the BRANCH_PREFIX scan. */
11175 next_fragP
->tc_frag_data
.max_prefix_length
= 0;
11178 frag_wane (next_fragP
);
11183 /* Stop if there is no BRANCH_PREFIX. */
11184 if (!align_branch_prefix_size
)
11187 /* Scan for BRANCH_PREFIX. */
11188 for (; fragP
!= NULL
; fragP
= fragP
->fr_next
)
11190 if (fragP
->fr_type
!= rs_machine_dependent
11191 || (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
)
11195 /* Count all BRANCH_PREFIX frags before BRANCH_PADDING and
11196 COND_JUMP_PREFIX. */
11197 max_prefix_length
= 0;
11198 for (next_fragP
= fragP
;
11199 next_fragP
!= NULL
;
11200 next_fragP
= next_fragP
->fr_next
)
11202 if (next_fragP
->fr_type
== rs_fill
)
11203 /* Skip rs_fill frags. */
11205 else if (next_fragP
->fr_type
!= rs_machine_dependent
)
11206 /* Stop for all other frags. */
11209 /* rs_machine_dependent frags. */
11210 if (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
11213 /* Count BRANCH_PREFIX frags. */
11214 if (max_prefix_length
>= MAX_FUSED_JCC_PADDING_SIZE
)
11216 max_prefix_length
= MAX_FUSED_JCC_PADDING_SIZE
;
11217 frag_wane (next_fragP
);
11221 += next_fragP
->tc_frag_data
.max_bytes
;
11223 else if ((TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
11225 || (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
11226 == FUSED_JCC_PADDING
))
11228 /* Stop at BRANCH_PADDING and FUSED_JCC_PADDING. */
11229 fragP
->tc_frag_data
.u
.padding_fragP
= next_fragP
;
11233 /* Stop for other rs_machine_dependent frags. */
11237 fragP
->tc_frag_data
.max_prefix_length
= max_prefix_length
;
11239 /* Skip to the next frag. */
11240 fragP
= next_fragP
;
11244 /* Compute padding size for
11247 CMP like instruction
11249 COND_JUMP/UNCOND_JUMP
11254 COND_JUMP/UNCOND_JUMP
11258 i386_branch_padding_size (fragS
*fragP
, offsetT address
)
11260 unsigned int offset
, size
, padding_size
;
11261 fragS
*branch_fragP
= fragP
->tc_frag_data
.u
.branch_fragP
;
11263 /* The start address of the BRANCH_PADDING or FUSED_JCC_PADDING frag. */
11265 address
= fragP
->fr_address
;
11266 address
+= fragP
->fr_fix
;
11268 /* CMP like instrunction size. */
11269 size
= fragP
->tc_frag_data
.cmp_size
;
11271 /* The base size of the branch frag. */
11272 size
+= branch_fragP
->fr_fix
;
11274 /* Add opcode and displacement bytes for the rs_machine_dependent
11276 if (branch_fragP
->fr_type
== rs_machine_dependent
)
11277 size
+= md_relax_table
[branch_fragP
->fr_subtype
].rlx_length
;
11279 /* Check if branch is within boundary and doesn't end at the last
11281 offset
= address
& ((1U << align_branch_power
) - 1);
11282 if ((offset
+ size
) >= (1U << align_branch_power
))
11283 /* Padding needed to avoid crossing boundary. */
11284 padding_size
= (1U << align_branch_power
) - offset
;
11286 /* No padding needed. */
11289 /* The return value may be saved in tc_frag_data.length which is
11291 if (!fits_in_unsigned_byte (padding_size
))
11294 return padding_size
;
11297 /* i386_generic_table_relax_frag()
11299 Handle BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING frags to
11300 grow/shrink padding to align branch frags. Hand others to
11304 i386_generic_table_relax_frag (segT segment
, fragS
*fragP
, long stretch
)
11306 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
11307 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
)
11309 long padding_size
= i386_branch_padding_size (fragP
, 0);
11310 long grow
= padding_size
- fragP
->tc_frag_data
.length
;
11312 /* When the BRANCH_PREFIX frag is used, the computed address
11313 must match the actual address and there should be no padding. */
11314 if (fragP
->tc_frag_data
.padding_address
11315 && (fragP
->tc_frag_data
.padding_address
!= fragP
->fr_address
11319 /* Update the padding size. */
11321 fragP
->tc_frag_data
.length
= padding_size
;
11325 else if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
)
11327 fragS
*padding_fragP
, *next_fragP
;
11328 long padding_size
, left_size
, last_size
;
11330 padding_fragP
= fragP
->tc_frag_data
.u
.padding_fragP
;
11331 if (!padding_fragP
)
11332 /* Use the padding set by the leading BRANCH_PREFIX frag. */
11333 return (fragP
->tc_frag_data
.length
11334 - fragP
->tc_frag_data
.last_length
);
11336 /* Compute the relative address of the padding frag in the very
11337 first time where the BRANCH_PREFIX frag sizes are zero. */
11338 if (!fragP
->tc_frag_data
.padding_address
)
11339 fragP
->tc_frag_data
.padding_address
11340 = padding_fragP
->fr_address
- (fragP
->fr_address
- stretch
);
11342 /* First update the last length from the previous interation. */
11343 left_size
= fragP
->tc_frag_data
.prefix_length
;
11344 for (next_fragP
= fragP
;
11345 next_fragP
!= padding_fragP
;
11346 next_fragP
= next_fragP
->fr_next
)
11347 if (next_fragP
->fr_type
== rs_machine_dependent
11348 && (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
11353 int max
= next_fragP
->tc_frag_data
.max_bytes
;
11357 if (max
> left_size
)
11362 next_fragP
->tc_frag_data
.last_length
= size
;
11366 next_fragP
->tc_frag_data
.last_length
= 0;
11369 /* Check the padding size for the padding frag. */
11370 padding_size
= i386_branch_padding_size
11371 (padding_fragP
, (fragP
->fr_address
11372 + fragP
->tc_frag_data
.padding_address
));
11374 last_size
= fragP
->tc_frag_data
.prefix_length
;
11375 /* Check if there is change from the last interation. */
11376 if (padding_size
== last_size
)
11378 /* Update the expected address of the padding frag. */
11379 padding_fragP
->tc_frag_data
.padding_address
11380 = (fragP
->fr_address
+ padding_size
11381 + fragP
->tc_frag_data
.padding_address
);
11385 if (padding_size
> fragP
->tc_frag_data
.max_prefix_length
)
11387 /* No padding if there is no sufficient room. Clear the
11388 expected address of the padding frag. */
11389 padding_fragP
->tc_frag_data
.padding_address
= 0;
11393 /* Store the expected address of the padding frag. */
11394 padding_fragP
->tc_frag_data
.padding_address
11395 = (fragP
->fr_address
+ padding_size
11396 + fragP
->tc_frag_data
.padding_address
);
11398 fragP
->tc_frag_data
.prefix_length
= padding_size
;
11400 /* Update the length for the current interation. */
11401 left_size
= padding_size
;
11402 for (next_fragP
= fragP
;
11403 next_fragP
!= padding_fragP
;
11404 next_fragP
= next_fragP
->fr_next
)
11405 if (next_fragP
->fr_type
== rs_machine_dependent
11406 && (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
11411 int max
= next_fragP
->tc_frag_data
.max_bytes
;
11415 if (max
> left_size
)
11420 next_fragP
->tc_frag_data
.length
= size
;
11424 next_fragP
->tc_frag_data
.length
= 0;
11427 return (fragP
->tc_frag_data
.length
11428 - fragP
->tc_frag_data
.last_length
);
11430 return relax_frag (segment
, fragP
, stretch
);
11433 /* md_estimate_size_before_relax()
11435 Called just before relax() for rs_machine_dependent frags. The x86
11436 assembler uses these frags to handle variable size jump
11439 Any symbol that is now undefined will not become defined.
11440 Return the correct fr_subtype in the frag.
11441 Return the initial "guess for variable size of frag" to caller.
11442 The guess is actually the growth beyond the fixed part. Whatever
11443 we do to grow the fixed or variable part contributes to our
11447 md_estimate_size_before_relax (fragS
*fragP
, segT segment
)
11449 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
11450 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
11451 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
)
11453 i386_classify_machine_dependent_frag (fragP
);
11454 return fragP
->tc_frag_data
.length
;
11457 /* We've already got fragP->fr_subtype right; all we have to do is
11458 check for un-relaxable symbols. On an ELF system, we can't relax
11459 an externally visible symbol, because it may be overridden by a
11461 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
11462 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11464 && !elf_symbol_resolved_in_segment_p (fragP
->fr_symbol
,
11467 #if defined (OBJ_COFF) && defined (TE_PE)
11468 || (OUTPUT_FLAVOR
== bfd_target_coff_flavour
11469 && S_IS_WEAK (fragP
->fr_symbol
))
11473 /* Symbol is undefined in this segment, or we need to keep a
11474 reloc so that weak symbols can be overridden. */
11475 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
11476 enum bfd_reloc_code_real reloc_type
;
11477 unsigned char *opcode
;
11480 if (fragP
->fr_var
!= NO_RELOC
)
11481 reloc_type
= (enum bfd_reloc_code_real
) fragP
->fr_var
;
11482 else if (size
== 2)
11483 reloc_type
= BFD_RELOC_16_PCREL
;
11484 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11485 else if (need_plt32_p (fragP
->fr_symbol
))
11486 reloc_type
= BFD_RELOC_X86_64_PLT32
;
11489 reloc_type
= BFD_RELOC_32_PCREL
;
11491 old_fr_fix
= fragP
->fr_fix
;
11492 opcode
= (unsigned char *) fragP
->fr_opcode
;
11494 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
11497 /* Make jmp (0xeb) a (d)word displacement jump. */
11499 fragP
->fr_fix
+= size
;
11500 fix_new (fragP
, old_fr_fix
, size
,
11502 fragP
->fr_offset
, 1,
11508 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
11510 /* Negate the condition, and branch past an
11511 unconditional jump. */
11514 /* Insert an unconditional jump. */
11516 /* We added two extra opcode bytes, and have a two byte
11518 fragP
->fr_fix
+= 2 + 2;
11519 fix_new (fragP
, old_fr_fix
+ 2, 2,
11521 fragP
->fr_offset
, 1,
11525 /* Fall through. */
11528 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
11532 fragP
->fr_fix
+= 1;
11533 fixP
= fix_new (fragP
, old_fr_fix
, 1,
11535 fragP
->fr_offset
, 1,
11536 BFD_RELOC_8_PCREL
);
11537 fixP
->fx_signed
= 1;
11541 /* This changes the byte-displacement jump 0x7N
11542 to the (d)word-displacement jump 0x0f,0x8N. */
11543 opcode
[1] = opcode
[0] + 0x10;
11544 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
11545 /* We've added an opcode byte. */
11546 fragP
->fr_fix
+= 1 + size
;
11547 fix_new (fragP
, old_fr_fix
+ 1, size
,
11549 fragP
->fr_offset
, 1,
11554 BAD_CASE (fragP
->fr_subtype
);
11558 return fragP
->fr_fix
- old_fr_fix
;
11561 /* Guess size depending on current relax state. Initially the relax
11562 state will correspond to a short jump and we return 1, because
11563 the variable part of the frag (the branch offset) is one byte
11564 long. However, we can relax a section more than once and in that
11565 case we must either set fr_subtype back to the unrelaxed state,
11566 or return the value for the appropriate branch. */
11567 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
11570 /* Called after relax() is finished.
11572 In: Address of frag.
11573 fr_type == rs_machine_dependent.
11574 fr_subtype is what the address relaxed to.
11576 Out: Any fixSs and constants are set up.
11577 Caller will turn frag into a ".space 0". */
11580 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec ATTRIBUTE_UNUSED
,
11583 unsigned char *opcode
;
11584 unsigned char *where_to_put_displacement
= NULL
;
11585 offsetT target_address
;
11586 offsetT opcode_address
;
11587 unsigned int extension
= 0;
11588 offsetT displacement_from_opcode_start
;
11590 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
11591 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
11592 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
)
11594 /* Generate nop padding. */
11595 unsigned int size
= fragP
->tc_frag_data
.length
;
11598 if (size
> fragP
->tc_frag_data
.max_bytes
)
11604 const char *branch
= "branch";
11605 const char *prefix
= "";
11606 fragS
*padding_fragP
;
11607 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
)
11610 padding_fragP
= fragP
->tc_frag_data
.u
.padding_fragP
;
11611 switch (fragP
->tc_frag_data
.default_prefix
)
11616 case CS_PREFIX_OPCODE
:
11619 case DS_PREFIX_OPCODE
:
11622 case ES_PREFIX_OPCODE
:
11625 case FS_PREFIX_OPCODE
:
11628 case GS_PREFIX_OPCODE
:
11631 case SS_PREFIX_OPCODE
:
11636 msg
= _("%s:%u: add %d%s at 0x%llx to align "
11637 "%s within %d-byte boundary\n");
11639 msg
= _("%s:%u: add additional %d%s at 0x%llx to "
11640 "align %s within %d-byte boundary\n");
11644 padding_fragP
= fragP
;
11645 msg
= _("%s:%u: add %d%s-byte nop at 0x%llx to align "
11646 "%s within %d-byte boundary\n");
11650 switch (padding_fragP
->tc_frag_data
.branch_type
)
11652 case align_branch_jcc
:
11655 case align_branch_fused
:
11656 branch
= "fused jcc";
11658 case align_branch_jmp
:
11661 case align_branch_call
:
11664 case align_branch_indirect
:
11665 branch
= "indiret branch";
11667 case align_branch_ret
:
11674 fprintf (stdout
, msg
,
11675 fragP
->fr_file
, fragP
->fr_line
, size
, prefix
,
11676 (long long) fragP
->fr_address
, branch
,
11677 1 << align_branch_power
);
11679 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
)
11680 memset (fragP
->fr_opcode
,
11681 fragP
->tc_frag_data
.default_prefix
, size
);
11683 i386_generate_nops (fragP
, (char *) fragP
->fr_opcode
,
11685 fragP
->fr_fix
+= size
;
11690 opcode
= (unsigned char *) fragP
->fr_opcode
;
11692 /* Address we want to reach in file space. */
11693 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
11695 /* Address opcode resides at in file space. */
11696 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
11698 /* Displacement from opcode start to fill into instruction. */
11699 displacement_from_opcode_start
= target_address
- opcode_address
;
11701 if ((fragP
->fr_subtype
& BIG
) == 0)
11703 /* Don't have to change opcode. */
11704 extension
= 1; /* 1 opcode + 1 displacement */
11705 where_to_put_displacement
= &opcode
[1];
11709 if (no_cond_jump_promotion
11710 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
11711 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
11712 _("long jump required"));
11714 switch (fragP
->fr_subtype
)
11716 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
11717 extension
= 4; /* 1 opcode + 4 displacement */
11719 where_to_put_displacement
= &opcode
[1];
11722 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
11723 extension
= 2; /* 1 opcode + 2 displacement */
11725 where_to_put_displacement
= &opcode
[1];
11728 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
11729 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
11730 extension
= 5; /* 2 opcode + 4 displacement */
11731 opcode
[1] = opcode
[0] + 0x10;
11732 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
11733 where_to_put_displacement
= &opcode
[2];
11736 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
11737 extension
= 3; /* 2 opcode + 2 displacement */
11738 opcode
[1] = opcode
[0] + 0x10;
11739 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
11740 where_to_put_displacement
= &opcode
[2];
11743 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
11748 where_to_put_displacement
= &opcode
[3];
11752 BAD_CASE (fragP
->fr_subtype
);
11757 /* If size if less then four we are sure that the operand fits,
11758 but if it's 4, then it could be that the displacement is larger
11760 if (DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
) == 4
11762 && ((addressT
) (displacement_from_opcode_start
- extension
11763 + ((addressT
) 1 << 31))
11764 > (((addressT
) 2 << 31) - 1)))
11766 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
11767 _("jump target out of range"));
11768 /* Make us emit 0. */
11769 displacement_from_opcode_start
= extension
;
11771 /* Now put displacement after opcode. */
11772 md_number_to_chars ((char *) where_to_put_displacement
,
11773 (valueT
) (displacement_from_opcode_start
- extension
),
11774 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
11775 fragP
->fr_fix
+= extension
;
11778 /* Apply a fixup (fixP) to segment data, once it has been determined
11779 by our caller that we have all the info we need to fix it up.
11781 Parameter valP is the pointer to the value of the bits.
11783 On the 386, immediates, displacements, and data pointers are all in
11784 the same (little-endian) format, so we don't need to care about which
11785 we are handling. */
11788 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
11790 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
11791 valueT value
= *valP
;
11793 #if !defined (TE_Mach)
11794 if (fixP
->fx_pcrel
)
11796 switch (fixP
->fx_r_type
)
11802 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
11805 case BFD_RELOC_X86_64_32S
:
11806 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
11809 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
11812 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
11817 if (fixP
->fx_addsy
!= NULL
11818 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
11819 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
11820 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
11821 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
11822 && !use_rela_relocations
)
11824 /* This is a hack. There should be a better way to handle this.
11825 This covers for the fact that bfd_install_relocation will
11826 subtract the current location (for partial_inplace, PC relative
11827 relocations); see more below. */
11831 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
11834 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
11836 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11839 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
11841 if ((sym_seg
== seg
11842 || (symbol_section_p (fixP
->fx_addsy
)
11843 && sym_seg
!= absolute_section
))
11844 && !generic_force_reloc (fixP
))
11846 /* Yes, we add the values in twice. This is because
11847 bfd_install_relocation subtracts them out again. I think
11848 bfd_install_relocation is broken, but I don't dare change
11850 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
11854 #if defined (OBJ_COFF) && defined (TE_PE)
11855 /* For some reason, the PE format does not store a
11856 section address offset for a PC relative symbol. */
11857 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
11858 || S_IS_WEAK (fixP
->fx_addsy
))
11859 value
+= md_pcrel_from (fixP
);
11862 #if defined (OBJ_COFF) && defined (TE_PE)
11863 if (fixP
->fx_addsy
!= NULL
11864 && S_IS_WEAK (fixP
->fx_addsy
)
11865 /* PR 16858: Do not modify weak function references. */
11866 && ! fixP
->fx_pcrel
)
11868 #if !defined (TE_PEP)
11869 /* For x86 PE weak function symbols are neither PC-relative
11870 nor do they set S_IS_FUNCTION. So the only reliable way
11871 to detect them is to check the flags of their containing
11873 if (S_GET_SEGMENT (fixP
->fx_addsy
) != NULL
11874 && S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_CODE
)
11878 value
-= S_GET_VALUE (fixP
->fx_addsy
);
11882 /* Fix a few things - the dynamic linker expects certain values here,
11883 and we must not disappoint it. */
11884 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11885 if (IS_ELF
&& fixP
->fx_addsy
)
11886 switch (fixP
->fx_r_type
)
11888 case BFD_RELOC_386_PLT32
:
11889 case BFD_RELOC_X86_64_PLT32
:
11890 /* Make the jump instruction point to the address of the operand.
11891 At runtime we merely add the offset to the actual PLT entry.
11892 NB: Subtract the offset size only for jump instructions. */
11893 if (fixP
->fx_pcrel
)
11897 case BFD_RELOC_386_TLS_GD
:
11898 case BFD_RELOC_386_TLS_LDM
:
11899 case BFD_RELOC_386_TLS_IE_32
:
11900 case BFD_RELOC_386_TLS_IE
:
11901 case BFD_RELOC_386_TLS_GOTIE
:
11902 case BFD_RELOC_386_TLS_GOTDESC
:
11903 case BFD_RELOC_X86_64_TLSGD
:
11904 case BFD_RELOC_X86_64_TLSLD
:
11905 case BFD_RELOC_X86_64_GOTTPOFF
:
11906 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
11907 value
= 0; /* Fully resolved at runtime. No addend. */
11909 case BFD_RELOC_386_TLS_LE
:
11910 case BFD_RELOC_386_TLS_LDO_32
:
11911 case BFD_RELOC_386_TLS_LE_32
:
11912 case BFD_RELOC_X86_64_DTPOFF32
:
11913 case BFD_RELOC_X86_64_DTPOFF64
:
11914 case BFD_RELOC_X86_64_TPOFF32
:
11915 case BFD_RELOC_X86_64_TPOFF64
:
11916 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
11919 case BFD_RELOC_386_TLS_DESC_CALL
:
11920 case BFD_RELOC_X86_64_TLSDESC_CALL
:
11921 value
= 0; /* Fully resolved at runtime. No addend. */
11922 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
11926 case BFD_RELOC_VTABLE_INHERIT
:
11927 case BFD_RELOC_VTABLE_ENTRY
:
11934 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
11936 #endif /* !defined (TE_Mach) */
11938 /* Are we finished with this relocation now? */
11939 if (fixP
->fx_addsy
== NULL
)
11941 #if defined (OBJ_COFF) && defined (TE_PE)
11942 else if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
11945 /* Remember value for tc_gen_reloc. */
11946 fixP
->fx_addnumber
= value
;
11947 /* Clear out the frag for now. */
11951 else if (use_rela_relocations
)
11953 fixP
->fx_no_overflow
= 1;
11954 /* Remember value for tc_gen_reloc. */
11955 fixP
->fx_addnumber
= value
;
11959 md_number_to_chars (p
, value
, fixP
->fx_size
);
11963 md_atof (int type
, char *litP
, int *sizeP
)
11965 /* This outputs the LITTLENUMs in REVERSE order;
11966 in accord with the bigendian 386. */
11967 return ieee_md_atof (type
, litP
, sizeP
, FALSE
);
11970 static char output_invalid_buf
[sizeof (unsigned char) * 2 + 6];
11973 output_invalid (int c
)
11976 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
11979 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
11980 "(0x%x)", (unsigned char) c
);
11981 return output_invalid_buf
;
11984 /* REG_STRING starts *before* REGISTER_PREFIX. */
11986 static const reg_entry
*
11987 parse_real_register (char *reg_string
, char **end_op
)
11989 char *s
= reg_string
;
11991 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
11992 const reg_entry
*r
;
11994 /* Skip possible REGISTER_PREFIX and possible whitespace. */
11995 if (*s
== REGISTER_PREFIX
)
11998 if (is_space_char (*s
))
12001 p
= reg_name_given
;
12002 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
12004 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
12005 return (const reg_entry
*) NULL
;
12009 /* For naked regs, make sure that we are not dealing with an identifier.
12010 This prevents confusing an identifier like `eax_var' with register
12012 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
12013 return (const reg_entry
*) NULL
;
12017 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
12019 /* Handle floating point regs, allowing spaces in the (i) part. */
12020 if (r
== i386_regtab
/* %st is first entry of table */)
12022 if (!cpu_arch_flags
.bitfield
.cpu8087
12023 && !cpu_arch_flags
.bitfield
.cpu287
12024 && !cpu_arch_flags
.bitfield
.cpu387
)
12025 return (const reg_entry
*) NULL
;
12027 if (is_space_char (*s
))
12032 if (is_space_char (*s
))
12034 if (*s
>= '0' && *s
<= '7')
12036 int fpr
= *s
- '0';
12038 if (is_space_char (*s
))
12043 r
= (const reg_entry
*) hash_find (reg_hash
, "st(0)");
12048 /* We have "%st(" then garbage. */
12049 return (const reg_entry
*) NULL
;
12053 if (r
== NULL
|| allow_pseudo_reg
)
12056 if (operand_type_all_zero (&r
->reg_type
))
12057 return (const reg_entry
*) NULL
;
12059 if ((r
->reg_type
.bitfield
.dword
12060 || (r
->reg_type
.bitfield
.class == SReg
&& r
->reg_num
> 3)
12061 || r
->reg_type
.bitfield
.class == RegCR
12062 || r
->reg_type
.bitfield
.class == RegDR
12063 || r
->reg_type
.bitfield
.class == RegTR
)
12064 && !cpu_arch_flags
.bitfield
.cpui386
)
12065 return (const reg_entry
*) NULL
;
12067 if (r
->reg_type
.bitfield
.class == RegMMX
&& !cpu_arch_flags
.bitfield
.cpummx
)
12068 return (const reg_entry
*) NULL
;
12070 if (!cpu_arch_flags
.bitfield
.cpuavx512f
)
12072 if (r
->reg_type
.bitfield
.zmmword
12073 || r
->reg_type
.bitfield
.class == RegMask
)
12074 return (const reg_entry
*) NULL
;
12076 if (!cpu_arch_flags
.bitfield
.cpuavx
)
12078 if (r
->reg_type
.bitfield
.ymmword
)
12079 return (const reg_entry
*) NULL
;
12081 if (!cpu_arch_flags
.bitfield
.cpusse
&& r
->reg_type
.bitfield
.xmmword
)
12082 return (const reg_entry
*) NULL
;
12086 if (r
->reg_type
.bitfield
.class == RegBND
&& !cpu_arch_flags
.bitfield
.cpumpx
)
12087 return (const reg_entry
*) NULL
;
12089 /* Don't allow fake index register unless allow_index_reg isn't 0. */
12090 if (!allow_index_reg
&& r
->reg_num
== RegIZ
)
12091 return (const reg_entry
*) NULL
;
12093 /* Upper 16 vector registers are only available with VREX in 64bit
12094 mode, and require EVEX encoding. */
12095 if (r
->reg_flags
& RegVRex
)
12097 if (!cpu_arch_flags
.bitfield
.cpuavx512f
12098 || flag_code
!= CODE_64BIT
)
12099 return (const reg_entry
*) NULL
;
12101 i
.vec_encoding
= vex_encoding_evex
;
12104 if (((r
->reg_flags
& (RegRex64
| RegRex
)) || r
->reg_type
.bitfield
.qword
)
12105 && (!cpu_arch_flags
.bitfield
.cpulm
|| r
->reg_type
.bitfield
.class != RegCR
)
12106 && flag_code
!= CODE_64BIT
)
12107 return (const reg_entry
*) NULL
;
12109 if (r
->reg_type
.bitfield
.class == SReg
&& r
->reg_num
== RegFlat
12111 return (const reg_entry
*) NULL
;
12116 /* REG_STRING starts *before* REGISTER_PREFIX. */
12118 static const reg_entry
*
12119 parse_register (char *reg_string
, char **end_op
)
12121 const reg_entry
*r
;
12123 if (*reg_string
== REGISTER_PREFIX
|| allow_naked_reg
)
12124 r
= parse_real_register (reg_string
, end_op
);
12129 char *save
= input_line_pointer
;
12133 input_line_pointer
= reg_string
;
12134 c
= get_symbol_name (®_string
);
12135 symbolP
= symbol_find (reg_string
);
12136 if (symbolP
&& S_GET_SEGMENT (symbolP
) == reg_section
)
12138 const expressionS
*e
= symbol_get_value_expression (symbolP
);
12140 know (e
->X_op
== O_register
);
12141 know (e
->X_add_number
>= 0
12142 && (valueT
) e
->X_add_number
< i386_regtab_size
);
12143 r
= i386_regtab
+ e
->X_add_number
;
12144 if ((r
->reg_flags
& RegVRex
))
12145 i
.vec_encoding
= vex_encoding_evex
;
12146 *end_op
= input_line_pointer
;
12148 *input_line_pointer
= c
;
12149 input_line_pointer
= save
;
12155 i386_parse_name (char *name
, expressionS
*e
, char *nextcharP
)
12157 const reg_entry
*r
;
12158 char *end
= input_line_pointer
;
12161 r
= parse_register (name
, &input_line_pointer
);
12162 if (r
&& end
<= input_line_pointer
)
12164 *nextcharP
= *input_line_pointer
;
12165 *input_line_pointer
= 0;
12166 e
->X_op
= O_register
;
12167 e
->X_add_number
= r
- i386_regtab
;
12170 input_line_pointer
= end
;
12172 return intel_syntax
? i386_intel_parse_name (name
, e
) : 0;
12176 md_operand (expressionS
*e
)
12179 const reg_entry
*r
;
12181 switch (*input_line_pointer
)
12183 case REGISTER_PREFIX
:
12184 r
= parse_real_register (input_line_pointer
, &end
);
12187 e
->X_op
= O_register
;
12188 e
->X_add_number
= r
- i386_regtab
;
12189 input_line_pointer
= end
;
12194 gas_assert (intel_syntax
);
12195 end
= input_line_pointer
++;
12197 if (*input_line_pointer
== ']')
12199 ++input_line_pointer
;
12200 e
->X_op_symbol
= make_expr_symbol (e
);
12201 e
->X_add_symbol
= NULL
;
12202 e
->X_add_number
= 0;
12207 e
->X_op
= O_absent
;
12208 input_line_pointer
= end
;
12215 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12216 const char *md_shortopts
= "kVQ:sqnO::";
12218 const char *md_shortopts
= "qnO::";
12221 #define OPTION_32 (OPTION_MD_BASE + 0)
12222 #define OPTION_64 (OPTION_MD_BASE + 1)
12223 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
12224 #define OPTION_MARCH (OPTION_MD_BASE + 3)
12225 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
12226 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
12227 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
12228 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
12229 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
12230 #define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 9)
12231 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
12232 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
12233 #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
12234 #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
12235 #define OPTION_X32 (OPTION_MD_BASE + 14)
12236 #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
12237 #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
12238 #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
12239 #define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
12240 #define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
12241 #define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
12242 #define OPTION_MSHARED (OPTION_MD_BASE + 21)
12243 #define OPTION_MAMD64 (OPTION_MD_BASE + 22)
12244 #define OPTION_MINTEL64 (OPTION_MD_BASE + 23)
12245 #define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24)
12246 #define OPTION_X86_USED_NOTE (OPTION_MD_BASE + 25)
12247 #define OPTION_MVEXWIG (OPTION_MD_BASE + 26)
12248 #define OPTION_MALIGN_BRANCH_BOUNDARY (OPTION_MD_BASE + 27)
12249 #define OPTION_MALIGN_BRANCH_PREFIX_SIZE (OPTION_MD_BASE + 28)
12250 #define OPTION_MALIGN_BRANCH (OPTION_MD_BASE + 29)
12251 #define OPTION_MBRANCHES_WITH_32B_BOUNDARIES (OPTION_MD_BASE + 30)
12253 struct option md_longopts
[] =
12255 {"32", no_argument
, NULL
, OPTION_32
},
12256 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
12257 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
12258 {"64", no_argument
, NULL
, OPTION_64
},
12260 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12261 {"x32", no_argument
, NULL
, OPTION_X32
},
12262 {"mshared", no_argument
, NULL
, OPTION_MSHARED
},
12263 {"mx86-used-note", required_argument
, NULL
, OPTION_X86_USED_NOTE
},
12265 {"divide", no_argument
, NULL
, OPTION_DIVIDE
},
12266 {"march", required_argument
, NULL
, OPTION_MARCH
},
12267 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
12268 {"mmnemonic", required_argument
, NULL
, OPTION_MMNEMONIC
},
12269 {"msyntax", required_argument
, NULL
, OPTION_MSYNTAX
},
12270 {"mindex-reg", no_argument
, NULL
, OPTION_MINDEX_REG
},
12271 {"mnaked-reg", no_argument
, NULL
, OPTION_MNAKED_REG
},
12272 {"msse2avx", no_argument
, NULL
, OPTION_MSSE2AVX
},
12273 {"msse-check", required_argument
, NULL
, OPTION_MSSE_CHECK
},
12274 {"moperand-check", required_argument
, NULL
, OPTION_MOPERAND_CHECK
},
12275 {"mavxscalar", required_argument
, NULL
, OPTION_MAVXSCALAR
},
12276 {"mvexwig", required_argument
, NULL
, OPTION_MVEXWIG
},
12277 {"madd-bnd-prefix", no_argument
, NULL
, OPTION_MADD_BND_PREFIX
},
12278 {"mevexlig", required_argument
, NULL
, OPTION_MEVEXLIG
},
12279 {"mevexwig", required_argument
, NULL
, OPTION_MEVEXWIG
},
12280 # if defined (TE_PE) || defined (TE_PEP)
12281 {"mbig-obj", no_argument
, NULL
, OPTION_MBIG_OBJ
},
12283 {"momit-lock-prefix", required_argument
, NULL
, OPTION_MOMIT_LOCK_PREFIX
},
12284 {"mfence-as-lock-add", required_argument
, NULL
, OPTION_MFENCE_AS_LOCK_ADD
},
12285 {"mrelax-relocations", required_argument
, NULL
, OPTION_MRELAX_RELOCATIONS
},
12286 {"mevexrcig", required_argument
, NULL
, OPTION_MEVEXRCIG
},
12287 {"malign-branch-boundary", required_argument
, NULL
, OPTION_MALIGN_BRANCH_BOUNDARY
},
12288 {"malign-branch-prefix-size", required_argument
, NULL
, OPTION_MALIGN_BRANCH_PREFIX_SIZE
},
12289 {"malign-branch", required_argument
, NULL
, OPTION_MALIGN_BRANCH
},
12290 {"mbranches-within-32B-boundaries", no_argument
, NULL
, OPTION_MBRANCHES_WITH_32B_BOUNDARIES
},
12291 {"mamd64", no_argument
, NULL
, OPTION_MAMD64
},
12292 {"mintel64", no_argument
, NULL
, OPTION_MINTEL64
},
12293 {NULL
, no_argument
, NULL
, 0}
12295 size_t md_longopts_size
= sizeof (md_longopts
);
12298 md_parse_option (int c
, const char *arg
)
12301 char *arch
, *next
, *saved
, *type
;
12306 optimize_align_code
= 0;
12310 quiet_warnings
= 1;
12313 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12314 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
12315 should be emitted or not. FIXME: Not implemented. */
12317 if ((arg
[0] != 'y' && arg
[0] != 'n') || arg
[1])
12321 /* -V: SVR4 argument to print version ID. */
12323 print_version_id ();
12326 /* -k: Ignore for FreeBSD compatibility. */
12331 /* -s: On i386 Solaris, this tells the native assembler to use
12332 .stab instead of .stab.excl. We always use .stab anyhow. */
12335 case OPTION_MSHARED
:
12339 case OPTION_X86_USED_NOTE
:
12340 if (strcasecmp (arg
, "yes") == 0)
12342 else if (strcasecmp (arg
, "no") == 0)
12345 as_fatal (_("invalid -mx86-used-note= option: `%s'"), arg
);
12350 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
12351 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
12354 const char **list
, **l
;
12356 list
= bfd_target_list ();
12357 for (l
= list
; *l
!= NULL
; l
++)
12358 if (CONST_STRNEQ (*l
, "elf64-x86-64")
12359 || strcmp (*l
, "coff-x86-64") == 0
12360 || strcmp (*l
, "pe-x86-64") == 0
12361 || strcmp (*l
, "pei-x86-64") == 0
12362 || strcmp (*l
, "mach-o-x86-64") == 0)
12364 default_arch
= "x86_64";
12368 as_fatal (_("no compiled in support for x86_64"));
12374 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12378 const char **list
, **l
;
12380 list
= bfd_target_list ();
12381 for (l
= list
; *l
!= NULL
; l
++)
12382 if (CONST_STRNEQ (*l
, "elf32-x86-64"))
12384 default_arch
= "x86_64:32";
12388 as_fatal (_("no compiled in support for 32bit x86_64"));
12392 as_fatal (_("32bit x86_64 is only supported for ELF"));
12397 default_arch
= "i386";
12400 case OPTION_DIVIDE
:
12401 #ifdef SVR4_COMMENT_CHARS
12406 n
= XNEWVEC (char, strlen (i386_comment_chars
) + 1);
12408 for (s
= i386_comment_chars
; *s
!= '\0'; s
++)
12412 i386_comment_chars
= n
;
12418 saved
= xstrdup (arg
);
12420 /* Allow -march=+nosse. */
12426 as_fatal (_("invalid -march= option: `%s'"), arg
);
12427 next
= strchr (arch
, '+');
12430 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
12432 if (strcmp (arch
, cpu_arch
[j
].name
) == 0)
12435 if (! cpu_arch
[j
].flags
.bitfield
.cpui386
)
12438 cpu_arch_name
= cpu_arch
[j
].name
;
12439 cpu_sub_arch_name
= NULL
;
12440 cpu_arch_flags
= cpu_arch
[j
].flags
;
12441 cpu_arch_isa
= cpu_arch
[j
].type
;
12442 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
12443 if (!cpu_arch_tune_set
)
12445 cpu_arch_tune
= cpu_arch_isa
;
12446 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
12450 else if (*cpu_arch
[j
].name
== '.'
12451 && strcmp (arch
, cpu_arch
[j
].name
+ 1) == 0)
12453 /* ISA extension. */
12454 i386_cpu_flags flags
;
12456 flags
= cpu_flags_or (cpu_arch_flags
,
12457 cpu_arch
[j
].flags
);
12459 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
12461 if (cpu_sub_arch_name
)
12463 char *name
= cpu_sub_arch_name
;
12464 cpu_sub_arch_name
= concat (name
,
12466 (const char *) NULL
);
12470 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
12471 cpu_arch_flags
= flags
;
12472 cpu_arch_isa_flags
= flags
;
12476 = cpu_flags_or (cpu_arch_isa_flags
,
12477 cpu_arch
[j
].flags
);
12482 if (j
>= ARRAY_SIZE (cpu_arch
))
12484 /* Disable an ISA extension. */
12485 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
12486 if (strcmp (arch
, cpu_noarch
[j
].name
) == 0)
12488 i386_cpu_flags flags
;
12490 flags
= cpu_flags_and_not (cpu_arch_flags
,
12491 cpu_noarch
[j
].flags
);
12492 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
12494 if (cpu_sub_arch_name
)
12496 char *name
= cpu_sub_arch_name
;
12497 cpu_sub_arch_name
= concat (arch
,
12498 (const char *) NULL
);
12502 cpu_sub_arch_name
= xstrdup (arch
);
12503 cpu_arch_flags
= flags
;
12504 cpu_arch_isa_flags
= flags
;
12509 if (j
>= ARRAY_SIZE (cpu_noarch
))
12510 j
= ARRAY_SIZE (cpu_arch
);
12513 if (j
>= ARRAY_SIZE (cpu_arch
))
12514 as_fatal (_("invalid -march= option: `%s'"), arg
);
12518 while (next
!= NULL
);
12524 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
12525 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
12527 if (strcmp (arg
, cpu_arch
[j
].name
) == 0)
12529 cpu_arch_tune_set
= 1;
12530 cpu_arch_tune
= cpu_arch
[j
].type
;
12531 cpu_arch_tune_flags
= cpu_arch
[j
].flags
;
12535 if (j
>= ARRAY_SIZE (cpu_arch
))
12536 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
12539 case OPTION_MMNEMONIC
:
12540 if (strcasecmp (arg
, "att") == 0)
12541 intel_mnemonic
= 0;
12542 else if (strcasecmp (arg
, "intel") == 0)
12543 intel_mnemonic
= 1;
12545 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg
);
12548 case OPTION_MSYNTAX
:
12549 if (strcasecmp (arg
, "att") == 0)
12551 else if (strcasecmp (arg
, "intel") == 0)
12554 as_fatal (_("invalid -msyntax= option: `%s'"), arg
);
12557 case OPTION_MINDEX_REG
:
12558 allow_index_reg
= 1;
12561 case OPTION_MNAKED_REG
:
12562 allow_naked_reg
= 1;
12565 case OPTION_MSSE2AVX
:
12569 case OPTION_MSSE_CHECK
:
12570 if (strcasecmp (arg
, "error") == 0)
12571 sse_check
= check_error
;
12572 else if (strcasecmp (arg
, "warning") == 0)
12573 sse_check
= check_warning
;
12574 else if (strcasecmp (arg
, "none") == 0)
12575 sse_check
= check_none
;
12577 as_fatal (_("invalid -msse-check= option: `%s'"), arg
);
12580 case OPTION_MOPERAND_CHECK
:
12581 if (strcasecmp (arg
, "error") == 0)
12582 operand_check
= check_error
;
12583 else if (strcasecmp (arg
, "warning") == 0)
12584 operand_check
= check_warning
;
12585 else if (strcasecmp (arg
, "none") == 0)
12586 operand_check
= check_none
;
12588 as_fatal (_("invalid -moperand-check= option: `%s'"), arg
);
12591 case OPTION_MAVXSCALAR
:
12592 if (strcasecmp (arg
, "128") == 0)
12593 avxscalar
= vex128
;
12594 else if (strcasecmp (arg
, "256") == 0)
12595 avxscalar
= vex256
;
12597 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg
);
12600 case OPTION_MVEXWIG
:
12601 if (strcmp (arg
, "0") == 0)
12603 else if (strcmp (arg
, "1") == 0)
12606 as_fatal (_("invalid -mvexwig= option: `%s'"), arg
);
12609 case OPTION_MADD_BND_PREFIX
:
12610 add_bnd_prefix
= 1;
12613 case OPTION_MEVEXLIG
:
12614 if (strcmp (arg
, "128") == 0)
12615 evexlig
= evexl128
;
12616 else if (strcmp (arg
, "256") == 0)
12617 evexlig
= evexl256
;
12618 else if (strcmp (arg
, "512") == 0)
12619 evexlig
= evexl512
;
12621 as_fatal (_("invalid -mevexlig= option: `%s'"), arg
);
12624 case OPTION_MEVEXRCIG
:
12625 if (strcmp (arg
, "rne") == 0)
12627 else if (strcmp (arg
, "rd") == 0)
12629 else if (strcmp (arg
, "ru") == 0)
12631 else if (strcmp (arg
, "rz") == 0)
12634 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg
);
12637 case OPTION_MEVEXWIG
:
12638 if (strcmp (arg
, "0") == 0)
12640 else if (strcmp (arg
, "1") == 0)
12643 as_fatal (_("invalid -mevexwig= option: `%s'"), arg
);
12646 # if defined (TE_PE) || defined (TE_PEP)
12647 case OPTION_MBIG_OBJ
:
12652 case OPTION_MOMIT_LOCK_PREFIX
:
12653 if (strcasecmp (arg
, "yes") == 0)
12654 omit_lock_prefix
= 1;
12655 else if (strcasecmp (arg
, "no") == 0)
12656 omit_lock_prefix
= 0;
12658 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg
);
12661 case OPTION_MFENCE_AS_LOCK_ADD
:
12662 if (strcasecmp (arg
, "yes") == 0)
12664 else if (strcasecmp (arg
, "no") == 0)
12667 as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg
);
12670 case OPTION_MRELAX_RELOCATIONS
:
12671 if (strcasecmp (arg
, "yes") == 0)
12672 generate_relax_relocations
= 1;
12673 else if (strcasecmp (arg
, "no") == 0)
12674 generate_relax_relocations
= 0;
12676 as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg
);
12679 case OPTION_MALIGN_BRANCH_BOUNDARY
:
12682 long int align
= strtoul (arg
, &end
, 0);
12687 align_branch_power
= 0;
12690 else if (align
>= 16)
12693 for (align_power
= 0;
12695 align
>>= 1, align_power
++)
12697 /* Limit alignment power to 31. */
12698 if (align
== 1 && align_power
< 32)
12700 align_branch_power
= align_power
;
12705 as_fatal (_("invalid -malign-branch-boundary= value: %s"), arg
);
12709 case OPTION_MALIGN_BRANCH_PREFIX_SIZE
:
12712 int align
= strtoul (arg
, &end
, 0);
12713 /* Some processors only support 5 prefixes. */
12714 if (*end
== '\0' && align
>= 0 && align
< 6)
12716 align_branch_prefix_size
= align
;
12719 as_fatal (_("invalid -malign-branch-prefix-size= value: %s"),
12724 case OPTION_MALIGN_BRANCH
:
12726 saved
= xstrdup (arg
);
12730 next
= strchr (type
, '+');
12733 if (strcasecmp (type
, "jcc") == 0)
12734 align_branch
|= align_branch_jcc_bit
;
12735 else if (strcasecmp (type
, "fused") == 0)
12736 align_branch
|= align_branch_fused_bit
;
12737 else if (strcasecmp (type
, "jmp") == 0)
12738 align_branch
|= align_branch_jmp_bit
;
12739 else if (strcasecmp (type
, "call") == 0)
12740 align_branch
|= align_branch_call_bit
;
12741 else if (strcasecmp (type
, "ret") == 0)
12742 align_branch
|= align_branch_ret_bit
;
12743 else if (strcasecmp (type
, "indirect") == 0)
12744 align_branch
|= align_branch_indirect_bit
;
12746 as_fatal (_("invalid -malign-branch= option: `%s'"), arg
);
12749 while (next
!= NULL
);
12753 case OPTION_MBRANCHES_WITH_32B_BOUNDARIES
:
12754 align_branch_power
= 5;
12755 align_branch_prefix_size
= 5;
12756 align_branch
= (align_branch_jcc_bit
12757 | align_branch_fused_bit
12758 | align_branch_jmp_bit
);
12761 case OPTION_MAMD64
:
12765 case OPTION_MINTEL64
:
12773 /* Turn off -Os. */
12774 optimize_for_space
= 0;
12776 else if (*arg
== 's')
12778 optimize_for_space
= 1;
12779 /* Turn on all encoding optimizations. */
12780 optimize
= INT_MAX
;
12784 optimize
= atoi (arg
);
12785 /* Turn off -Os. */
12786 optimize_for_space
= 0;
12796 #define MESSAGE_TEMPLATE \
12800 output_message (FILE *stream
, char *p
, char *message
, char *start
,
12801 int *left_p
, const char *name
, int len
)
12803 int size
= sizeof (MESSAGE_TEMPLATE
);
12804 int left
= *left_p
;
12806 /* Reserve 2 spaces for ", " or ",\0" */
12809 /* Check if there is any room. */
12817 p
= mempcpy (p
, name
, len
);
12821 /* Output the current message now and start a new one. */
12824 fprintf (stream
, "%s\n", message
);
12826 left
= size
- (start
- message
) - len
- 2;
12828 gas_assert (left
>= 0);
12830 p
= mempcpy (p
, name
, len
);
12838 show_arch (FILE *stream
, int ext
, int check
)
12840 static char message
[] = MESSAGE_TEMPLATE
;
12841 char *start
= message
+ 27;
12843 int size
= sizeof (MESSAGE_TEMPLATE
);
12850 left
= size
- (start
- message
);
12851 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
12853 /* Should it be skipped? */
12854 if (cpu_arch
[j
].skip
)
12857 name
= cpu_arch
[j
].name
;
12858 len
= cpu_arch
[j
].len
;
12861 /* It is an extension. Skip if we aren't asked to show it. */
12872 /* It is an processor. Skip if we show only extension. */
12875 else if (check
&& ! cpu_arch
[j
].flags
.bitfield
.cpui386
)
12877 /* It is an impossible processor - skip. */
12881 p
= output_message (stream
, p
, message
, start
, &left
, name
, len
);
12884 /* Display disabled extensions. */
12886 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
12888 name
= cpu_noarch
[j
].name
;
12889 len
= cpu_noarch
[j
].len
;
12890 p
= output_message (stream
, p
, message
, start
, &left
, name
,
12895 fprintf (stream
, "%s\n", message
);
12899 md_show_usage (FILE *stream
)
12901 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12902 fprintf (stream
, _("\
12903 -Qy, -Qn ignored\n\
12904 -V print assembler version number\n\
12907 fprintf (stream
, _("\
12908 -n Do not optimize code alignment\n\
12909 -q quieten some warnings\n"));
12910 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12911 fprintf (stream
, _("\
12914 #if defined BFD64 && (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
12915 || defined (TE_PE) || defined (TE_PEP))
12916 fprintf (stream
, _("\
12917 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
12919 #ifdef SVR4_COMMENT_CHARS
12920 fprintf (stream
, _("\
12921 --divide do not treat `/' as a comment character\n"));
12923 fprintf (stream
, _("\
12924 --divide ignored\n"));
12926 fprintf (stream
, _("\
12927 -march=CPU[,+EXTENSION...]\n\
12928 generate code for CPU and EXTENSION, CPU is one of:\n"));
12929 show_arch (stream
, 0, 1);
12930 fprintf (stream
, _("\
12931 EXTENSION is combination of:\n"));
12932 show_arch (stream
, 1, 0);
12933 fprintf (stream
, _("\
12934 -mtune=CPU optimize for CPU, CPU is one of:\n"));
12935 show_arch (stream
, 0, 0);
12936 fprintf (stream
, _("\
12937 -msse2avx encode SSE instructions with VEX prefix\n"));
12938 fprintf (stream
, _("\
12939 -msse-check=[none|error|warning] (default: warning)\n\
12940 check SSE instructions\n"));
12941 fprintf (stream
, _("\
12942 -moperand-check=[none|error|warning] (default: warning)\n\
12943 check operand combinations for validity\n"));
12944 fprintf (stream
, _("\
12945 -mavxscalar=[128|256] (default: 128)\n\
12946 encode scalar AVX instructions with specific vector\n\
12948 fprintf (stream
, _("\
12949 -mvexwig=[0|1] (default: 0)\n\
12950 encode VEX instructions with specific VEX.W value\n\
12951 for VEX.W bit ignored instructions\n"));
12952 fprintf (stream
, _("\
12953 -mevexlig=[128|256|512] (default: 128)\n\
12954 encode scalar EVEX instructions with specific vector\n\
12956 fprintf (stream
, _("\
12957 -mevexwig=[0|1] (default: 0)\n\
12958 encode EVEX instructions with specific EVEX.W value\n\
12959 for EVEX.W bit ignored instructions\n"));
12960 fprintf (stream
, _("\
12961 -mevexrcig=[rne|rd|ru|rz] (default: rne)\n\
12962 encode EVEX instructions with specific EVEX.RC value\n\
12963 for SAE-only ignored instructions\n"));
12964 fprintf (stream
, _("\
12965 -mmnemonic=[att|intel] "));
12966 if (SYSV386_COMPAT
)
12967 fprintf (stream
, _("(default: att)\n"));
12969 fprintf (stream
, _("(default: intel)\n"));
12970 fprintf (stream
, _("\
12971 use AT&T/Intel mnemonic\n"));
12972 fprintf (stream
, _("\
12973 -msyntax=[att|intel] (default: att)\n\
12974 use AT&T/Intel syntax\n"));
12975 fprintf (stream
, _("\
12976 -mindex-reg support pseudo index registers\n"));
12977 fprintf (stream
, _("\
12978 -mnaked-reg don't require `%%' prefix for registers\n"));
12979 fprintf (stream
, _("\
12980 -madd-bnd-prefix add BND prefix for all valid branches\n"));
12981 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12982 fprintf (stream
, _("\
12983 -mshared disable branch optimization for shared code\n"));
12984 fprintf (stream
, _("\
12985 -mx86-used-note=[no|yes] "));
12986 if (DEFAULT_X86_USED_NOTE
)
12987 fprintf (stream
, _("(default: yes)\n"));
12989 fprintf (stream
, _("(default: no)\n"));
12990 fprintf (stream
, _("\
12991 generate x86 used ISA and feature properties\n"));
12993 #if defined (TE_PE) || defined (TE_PEP)
12994 fprintf (stream
, _("\
12995 -mbig-obj generate big object files\n"));
12997 fprintf (stream
, _("\
12998 -momit-lock-prefix=[no|yes] (default: no)\n\
12999 strip all lock prefixes\n"));
13000 fprintf (stream
, _("\
13001 -mfence-as-lock-add=[no|yes] (default: no)\n\
13002 encode lfence, mfence and sfence as\n\
13003 lock addl $0x0, (%%{re}sp)\n"));
13004 fprintf (stream
, _("\
13005 -mrelax-relocations=[no|yes] "));
13006 if (DEFAULT_GENERATE_X86_RELAX_RELOCATIONS
)
13007 fprintf (stream
, _("(default: yes)\n"));
13009 fprintf (stream
, _("(default: no)\n"));
13010 fprintf (stream
, _("\
13011 generate relax relocations\n"));
13012 fprintf (stream
, _("\
13013 -malign-branch-boundary=NUM (default: 0)\n\
13014 align branches within NUM byte boundary\n"));
13015 fprintf (stream
, _("\
13016 -malign-branch=TYPE[+TYPE...] (default: jcc+fused+jmp)\n\
13017 TYPE is combination of jcc, fused, jmp, call, ret,\n\
13019 specify types of branches to align\n"));
13020 fprintf (stream
, _("\
13021 -malign-branch-prefix-size=NUM (default: 5)\n\
13022 align branches with NUM prefixes per instruction\n"));
13023 fprintf (stream
, _("\
13024 -mbranches-within-32B-boundaries\n\
13025 align branches within 32 byte boundary\n"));
13026 fprintf (stream
, _("\
13027 -mamd64 accept only AMD64 ISA [default]\n"));
13028 fprintf (stream
, _("\
13029 -mintel64 accept only Intel64 ISA\n"));
13032 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
13033 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
13034 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
13036 /* Pick the target format to use. */
13039 i386_target_format (void)
13041 if (!strncmp (default_arch
, "x86_64", 6))
13043 update_code_flag (CODE_64BIT
, 1);
13044 if (default_arch
[6] == '\0')
13045 x86_elf_abi
= X86_64_ABI
;
13047 x86_elf_abi
= X86_64_X32_ABI
;
13049 else if (!strcmp (default_arch
, "i386"))
13050 update_code_flag (CODE_32BIT
, 1);
13051 else if (!strcmp (default_arch
, "iamcu"))
13053 update_code_flag (CODE_32BIT
, 1);
13054 if (cpu_arch_isa
== PROCESSOR_UNKNOWN
)
13056 static const i386_cpu_flags iamcu_flags
= CPU_IAMCU_FLAGS
;
13057 cpu_arch_name
= "iamcu";
13058 cpu_sub_arch_name
= NULL
;
13059 cpu_arch_flags
= iamcu_flags
;
13060 cpu_arch_isa
= PROCESSOR_IAMCU
;
13061 cpu_arch_isa_flags
= iamcu_flags
;
13062 if (!cpu_arch_tune_set
)
13064 cpu_arch_tune
= cpu_arch_isa
;
13065 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
13068 else if (cpu_arch_isa
!= PROCESSOR_IAMCU
)
13069 as_fatal (_("Intel MCU doesn't support `%s' architecture"),
13073 as_fatal (_("unknown architecture"));
13075 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
13076 cpu_arch_isa_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
13077 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
13078 cpu_arch_tune_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
13080 switch (OUTPUT_FLAVOR
)
13082 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
13083 case bfd_target_aout_flavour
:
13084 return AOUT_TARGET_FORMAT
;
13086 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
13087 # if defined (TE_PE) || defined (TE_PEP)
13088 case bfd_target_coff_flavour
:
13089 if (flag_code
== CODE_64BIT
)
13090 return use_big_obj
? "pe-bigobj-x86-64" : "pe-x86-64";
13093 # elif defined (TE_GO32)
13094 case bfd_target_coff_flavour
:
13095 return "coff-go32";
13097 case bfd_target_coff_flavour
:
13098 return "coff-i386";
13101 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
13102 case bfd_target_elf_flavour
:
13104 const char *format
;
13106 switch (x86_elf_abi
)
13109 format
= ELF_TARGET_FORMAT
;
13111 tls_get_addr
= "___tls_get_addr";
13115 use_rela_relocations
= 1;
13118 tls_get_addr
= "__tls_get_addr";
13120 format
= ELF_TARGET_FORMAT64
;
13122 case X86_64_X32_ABI
:
13123 use_rela_relocations
= 1;
13126 tls_get_addr
= "__tls_get_addr";
13128 disallow_64bit_reloc
= 1;
13129 format
= ELF_TARGET_FORMAT32
;
13132 if (cpu_arch_isa
== PROCESSOR_L1OM
)
13134 if (x86_elf_abi
!= X86_64_ABI
)
13135 as_fatal (_("Intel L1OM is 64bit only"));
13136 return ELF_TARGET_L1OM_FORMAT
;
13138 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
13140 if (x86_elf_abi
!= X86_64_ABI
)
13141 as_fatal (_("Intel K1OM is 64bit only"));
13142 return ELF_TARGET_K1OM_FORMAT
;
13144 else if (cpu_arch_isa
== PROCESSOR_IAMCU
)
13146 if (x86_elf_abi
!= I386_ABI
)
13147 as_fatal (_("Intel MCU is 32bit only"));
13148 return ELF_TARGET_IAMCU_FORMAT
;
13154 #if defined (OBJ_MACH_O)
13155 case bfd_target_mach_o_flavour
:
13156 if (flag_code
== CODE_64BIT
)
13158 use_rela_relocations
= 1;
13160 return "mach-o-x86-64";
13163 return "mach-o-i386";
13171 #endif /* OBJ_MAYBE_ more than one */
13174 md_undefined_symbol (char *name
)
13176 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
13177 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
13178 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
13179 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
13183 if (symbol_find (name
))
13184 as_bad (_("GOT already in symbol table"));
13185 GOT_symbol
= symbol_new (name
, undefined_section
,
13186 (valueT
) 0, &zero_address_frag
);
13193 /* Round up a section size to the appropriate boundary. */
13196 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
13198 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
13199 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
13201 /* For a.out, force the section size to be aligned. If we don't do
13202 this, BFD will align it for us, but it will not write out the
13203 final bytes of the section. This may be a bug in BFD, but it is
13204 easier to fix it here since that is how the other a.out targets
13208 align
= bfd_section_alignment (segment
);
13209 size
= ((size
+ (1 << align
) - 1) & (-((valueT
) 1 << align
)));
13216 /* On the i386, PC-relative offsets are relative to the start of the
13217 next instruction. That is, the address of the offset, plus its
13218 size, since the offset is always the last part of the insn. */
13221 md_pcrel_from (fixS
*fixP
)
13223 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
13229 s_bss (int ignore ATTRIBUTE_UNUSED
)
13233 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13235 obj_elf_section_change_hook ();
13237 temp
= get_absolute_expression ();
13238 subseg_set (bss_section
, (subsegT
) temp
);
13239 demand_empty_rest_of_line ();
13244 /* Remember constant directive. */
13247 i386_cons_align (int ignore ATTRIBUTE_UNUSED
)
13249 if (last_insn
.kind
!= last_insn_directive
13250 && (bfd_section_flags (now_seg
) & SEC_CODE
))
13252 last_insn
.seg
= now_seg
;
13253 last_insn
.kind
= last_insn_directive
;
13254 last_insn
.name
= "constant directive";
13255 last_insn
.file
= as_where (&last_insn
.line
);
13260 i386_validate_fix (fixS
*fixp
)
13262 if (fixp
->fx_subsy
)
13264 if (fixp
->fx_subsy
== GOT_symbol
)
13266 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
13270 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13271 if (fixp
->fx_tcbit2
)
13272 fixp
->fx_r_type
= (fixp
->fx_tcbit
13273 ? BFD_RELOC_X86_64_REX_GOTPCRELX
13274 : BFD_RELOC_X86_64_GOTPCRELX
);
13277 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
13282 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
13284 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
13286 fixp
->fx_subsy
= 0;
13289 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13290 else if (!object_64bit
)
13292 if (fixp
->fx_r_type
== BFD_RELOC_386_GOT32
13293 && fixp
->fx_tcbit2
)
13294 fixp
->fx_r_type
= BFD_RELOC_386_GOT32X
;
13300 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
13303 bfd_reloc_code_real_type code
;
13305 switch (fixp
->fx_r_type
)
13307 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13308 case BFD_RELOC_SIZE32
:
13309 case BFD_RELOC_SIZE64
:
13310 if (S_IS_DEFINED (fixp
->fx_addsy
)
13311 && !S_IS_EXTERNAL (fixp
->fx_addsy
))
13313 /* Resolve size relocation against local symbol to size of
13314 the symbol plus addend. */
13315 valueT value
= S_GET_SIZE (fixp
->fx_addsy
) + fixp
->fx_offset
;
13316 if (fixp
->fx_r_type
== BFD_RELOC_SIZE32
13317 && !fits_in_unsigned_long (value
))
13318 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
13319 _("symbol size computation overflow"));
13320 fixp
->fx_addsy
= NULL
;
13321 fixp
->fx_subsy
= NULL
;
13322 md_apply_fix (fixp
, (valueT
*) &value
, NULL
);
13326 /* Fall through. */
13328 case BFD_RELOC_X86_64_PLT32
:
13329 case BFD_RELOC_X86_64_GOT32
:
13330 case BFD_RELOC_X86_64_GOTPCREL
:
13331 case BFD_RELOC_X86_64_GOTPCRELX
:
13332 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
13333 case BFD_RELOC_386_PLT32
:
13334 case BFD_RELOC_386_GOT32
:
13335 case BFD_RELOC_386_GOT32X
:
13336 case BFD_RELOC_386_GOTOFF
:
13337 case BFD_RELOC_386_GOTPC
:
13338 case BFD_RELOC_386_TLS_GD
:
13339 case BFD_RELOC_386_TLS_LDM
:
13340 case BFD_RELOC_386_TLS_LDO_32
:
13341 case BFD_RELOC_386_TLS_IE_32
:
13342 case BFD_RELOC_386_TLS_IE
:
13343 case BFD_RELOC_386_TLS_GOTIE
:
13344 case BFD_RELOC_386_TLS_LE_32
:
13345 case BFD_RELOC_386_TLS_LE
:
13346 case BFD_RELOC_386_TLS_GOTDESC
:
13347 case BFD_RELOC_386_TLS_DESC_CALL
:
13348 case BFD_RELOC_X86_64_TLSGD
:
13349 case BFD_RELOC_X86_64_TLSLD
:
13350 case BFD_RELOC_X86_64_DTPOFF32
:
13351 case BFD_RELOC_X86_64_DTPOFF64
:
13352 case BFD_RELOC_X86_64_GOTTPOFF
:
13353 case BFD_RELOC_X86_64_TPOFF32
:
13354 case BFD_RELOC_X86_64_TPOFF64
:
13355 case BFD_RELOC_X86_64_GOTOFF64
:
13356 case BFD_RELOC_X86_64_GOTPC32
:
13357 case BFD_RELOC_X86_64_GOT64
:
13358 case BFD_RELOC_X86_64_GOTPCREL64
:
13359 case BFD_RELOC_X86_64_GOTPC64
:
13360 case BFD_RELOC_X86_64_GOTPLT64
:
13361 case BFD_RELOC_X86_64_PLTOFF64
:
13362 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
13363 case BFD_RELOC_X86_64_TLSDESC_CALL
:
13364 case BFD_RELOC_RVA
:
13365 case BFD_RELOC_VTABLE_ENTRY
:
13366 case BFD_RELOC_VTABLE_INHERIT
:
13368 case BFD_RELOC_32_SECREL
:
13370 code
= fixp
->fx_r_type
;
13372 case BFD_RELOC_X86_64_32S
:
13373 if (!fixp
->fx_pcrel
)
13375 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
13376 code
= fixp
->fx_r_type
;
13379 /* Fall through. */
13381 if (fixp
->fx_pcrel
)
13383 switch (fixp
->fx_size
)
13386 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
13387 _("can not do %d byte pc-relative relocation"),
13389 code
= BFD_RELOC_32_PCREL
;
13391 case 1: code
= BFD_RELOC_8_PCREL
; break;
13392 case 2: code
= BFD_RELOC_16_PCREL
; break;
13393 case 4: code
= BFD_RELOC_32_PCREL
; break;
13395 case 8: code
= BFD_RELOC_64_PCREL
; break;
13401 switch (fixp
->fx_size
)
13404 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
13405 _("can not do %d byte relocation"),
13407 code
= BFD_RELOC_32
;
13409 case 1: code
= BFD_RELOC_8
; break;
13410 case 2: code
= BFD_RELOC_16
; break;
13411 case 4: code
= BFD_RELOC_32
; break;
13413 case 8: code
= BFD_RELOC_64
; break;
13420 if ((code
== BFD_RELOC_32
13421 || code
== BFD_RELOC_32_PCREL
13422 || code
== BFD_RELOC_X86_64_32S
)
13424 && fixp
->fx_addsy
== GOT_symbol
)
13427 code
= BFD_RELOC_386_GOTPC
;
13429 code
= BFD_RELOC_X86_64_GOTPC32
;
13431 if ((code
== BFD_RELOC_64
|| code
== BFD_RELOC_64_PCREL
)
13433 && fixp
->fx_addsy
== GOT_symbol
)
13435 code
= BFD_RELOC_X86_64_GOTPC64
;
13438 rel
= XNEW (arelent
);
13439 rel
->sym_ptr_ptr
= XNEW (asymbol
*);
13440 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
13442 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
13444 if (!use_rela_relocations
)
13446 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
13447 vtable entry to be used in the relocation's section offset. */
13448 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
13449 rel
->address
= fixp
->fx_offset
;
13450 #if defined (OBJ_COFF) && defined (TE_PE)
13451 else if (fixp
->fx_addsy
&& S_IS_WEAK (fixp
->fx_addsy
))
13452 rel
->addend
= fixp
->fx_addnumber
- (S_GET_VALUE (fixp
->fx_addsy
) * 2);
13457 /* Use the rela in 64bit mode. */
13460 if (disallow_64bit_reloc
)
13463 case BFD_RELOC_X86_64_DTPOFF64
:
13464 case BFD_RELOC_X86_64_TPOFF64
:
13465 case BFD_RELOC_64_PCREL
:
13466 case BFD_RELOC_X86_64_GOTOFF64
:
13467 case BFD_RELOC_X86_64_GOT64
:
13468 case BFD_RELOC_X86_64_GOTPCREL64
:
13469 case BFD_RELOC_X86_64_GOTPC64
:
13470 case BFD_RELOC_X86_64_GOTPLT64
:
13471 case BFD_RELOC_X86_64_PLTOFF64
:
13472 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
13473 _("cannot represent relocation type %s in x32 mode"),
13474 bfd_get_reloc_code_name (code
));
13480 if (!fixp
->fx_pcrel
)
13481 rel
->addend
= fixp
->fx_offset
;
13485 case BFD_RELOC_X86_64_PLT32
:
13486 case BFD_RELOC_X86_64_GOT32
:
13487 case BFD_RELOC_X86_64_GOTPCREL
:
13488 case BFD_RELOC_X86_64_GOTPCRELX
:
13489 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
13490 case BFD_RELOC_X86_64_TLSGD
:
13491 case BFD_RELOC_X86_64_TLSLD
:
13492 case BFD_RELOC_X86_64_GOTTPOFF
:
13493 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
13494 case BFD_RELOC_X86_64_TLSDESC_CALL
:
13495 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
13498 rel
->addend
= (section
->vma
13500 + fixp
->fx_addnumber
13501 + md_pcrel_from (fixp
));
13506 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
13507 if (rel
->howto
== NULL
)
13509 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
13510 _("cannot represent relocation type %s"),
13511 bfd_get_reloc_code_name (code
));
13512 /* Set howto to a garbage value so that we can keep going. */
13513 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
13514 gas_assert (rel
->howto
!= NULL
);
13520 #include "tc-i386-intel.c"
13523 tc_x86_parse_to_dw2regnum (expressionS
*exp
)
13525 int saved_naked_reg
;
13526 char saved_register_dot
;
13528 saved_naked_reg
= allow_naked_reg
;
13529 allow_naked_reg
= 1;
13530 saved_register_dot
= register_chars
['.'];
13531 register_chars
['.'] = '.';
13532 allow_pseudo_reg
= 1;
13533 expression_and_evaluate (exp
);
13534 allow_pseudo_reg
= 0;
13535 register_chars
['.'] = saved_register_dot
;
13536 allow_naked_reg
= saved_naked_reg
;
13538 if (exp
->X_op
== O_register
&& exp
->X_add_number
>= 0)
13540 if ((addressT
) exp
->X_add_number
< i386_regtab_size
)
13542 exp
->X_op
= O_constant
;
13543 exp
->X_add_number
= i386_regtab
[exp
->X_add_number
]
13544 .dw2_regnum
[flag_code
>> 1];
13547 exp
->X_op
= O_illegal
;
13552 tc_x86_frame_initial_instructions (void)
13554 static unsigned int sp_regno
[2];
13556 if (!sp_regno
[flag_code
>> 1])
13558 char *saved_input
= input_line_pointer
;
13559 char sp
[][4] = {"esp", "rsp"};
13562 input_line_pointer
= sp
[flag_code
>> 1];
13563 tc_x86_parse_to_dw2regnum (&exp
);
13564 gas_assert (exp
.X_op
== O_constant
);
13565 sp_regno
[flag_code
>> 1] = exp
.X_add_number
;
13566 input_line_pointer
= saved_input
;
13569 cfi_add_CFA_def_cfa (sp_regno
[flag_code
>> 1], -x86_cie_data_alignment
);
13570 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
13574 x86_dwarf2_addr_size (void)
13576 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
13577 if (x86_elf_abi
== X86_64_X32_ABI
)
13580 return bfd_arch_bits_per_address (stdoutput
) / 8;
13584 i386_elf_section_type (const char *str
, size_t len
)
13586 if (flag_code
== CODE_64BIT
13587 && len
== sizeof ("unwind") - 1
13588 && strncmp (str
, "unwind", 6) == 0)
13589 return SHT_X86_64_UNWIND
;
13596 i386_solaris_fix_up_eh_frame (segT sec
)
13598 if (flag_code
== CODE_64BIT
)
13599 elf_section_type (sec
) = SHT_X86_64_UNWIND
;
13605 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
13609 exp
.X_op
= O_secrel
;
13610 exp
.X_add_symbol
= symbol
;
13611 exp
.X_add_number
= 0;
13612 emit_expr (&exp
, size
);
13616 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13617 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
13620 x86_64_section_letter (int letter
, const char **ptr_msg
)
13622 if (flag_code
== CODE_64BIT
)
13625 return SHF_X86_64_LARGE
;
13627 *ptr_msg
= _("bad .section directive: want a,l,w,x,M,S,G,T in string");
13630 *ptr_msg
= _("bad .section directive: want a,w,x,M,S,G,T in string");
13635 x86_64_section_word (char *str
, size_t len
)
13637 if (len
== 5 && flag_code
== CODE_64BIT
&& CONST_STRNEQ (str
, "large"))
13638 return SHF_X86_64_LARGE
;
13644 handle_large_common (int small ATTRIBUTE_UNUSED
)
13646 if (flag_code
!= CODE_64BIT
)
13648 s_comm_internal (0, elf_common_parse
);
13649 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
13653 static segT lbss_section
;
13654 asection
*saved_com_section_ptr
= elf_com_section_ptr
;
13655 asection
*saved_bss_section
= bss_section
;
13657 if (lbss_section
== NULL
)
13659 flagword applicable
;
13660 segT seg
= now_seg
;
13661 subsegT subseg
= now_subseg
;
13663 /* The .lbss section is for local .largecomm symbols. */
13664 lbss_section
= subseg_new (".lbss", 0);
13665 applicable
= bfd_applicable_section_flags (stdoutput
);
13666 bfd_set_section_flags (lbss_section
, applicable
& SEC_ALLOC
);
13667 seg_info (lbss_section
)->bss
= 1;
13669 subseg_set (seg
, subseg
);
13672 elf_com_section_ptr
= &_bfd_elf_large_com_section
;
13673 bss_section
= lbss_section
;
13675 s_comm_internal (0, elf_common_parse
);
13677 elf_com_section_ptr
= saved_com_section_ptr
;
13678 bss_section
= saved_bss_section
;
13681 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */