1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright (C) 1989-2017 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 /* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
23 x86_64 support by Jan Hubicka (jh@suse.cz)
24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
29 #include "safe-ctype.h"
31 #include "dwarf2dbg.h"
32 #include "dw2gencfi.h"
33 #include "elf/x86-64.h"
34 #include "opcodes/i386-init.h"
36 #ifndef REGISTER_WARNINGS
37 #define REGISTER_WARNINGS 1
40 #ifndef INFER_ADDR_PREFIX
41 #define INFER_ADDR_PREFIX 1
45 #define DEFAULT_ARCH "i386"
50 #define INLINE __inline__
56 /* Prefixes will be emitted in the order defined below.
57 WAIT_PREFIX must be the first prefix since FWAIT is really is an
58 instruction, and so must come before any prefixes.
59 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
60 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
66 #define HLE_PREFIX REP_PREFIX
67 #define BND_PREFIX REP_PREFIX
69 #define REX_PREFIX 6 /* must come last. */
70 #define MAX_PREFIXES 7 /* max prefixes per opcode */
72 /* we define the syntax here (modulo base,index,scale syntax) */
73 #define REGISTER_PREFIX '%'
74 #define IMMEDIATE_PREFIX '$'
75 #define ABSOLUTE_PREFIX '*'
77 /* these are the instruction mnemonic suffixes in AT&T syntax or
78 memory operand size in Intel syntax. */
79 #define WORD_MNEM_SUFFIX 'w'
80 #define BYTE_MNEM_SUFFIX 'b'
81 #define SHORT_MNEM_SUFFIX 's'
82 #define LONG_MNEM_SUFFIX 'l'
83 #define QWORD_MNEM_SUFFIX 'q'
84 #define XMMWORD_MNEM_SUFFIX 'x'
85 #define YMMWORD_MNEM_SUFFIX 'y'
86 #define ZMMWORD_MNEM_SUFFIX 'z'
87 /* Intel Syntax. Use a non-ascii letter since since it never appears
89 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
91 #define END_OF_INSN '\0'
94 'templates' is for grouping together 'template' structures for opcodes
95 of the same name. This is only used for storing the insns in the grand
96 ole hash table of insns.
97 The templates themselves start at START and range up to (but not including)
102 const insn_template
*start
;
103 const insn_template
*end
;
107 /* 386 operand encoding bytes: see 386 book for details of this. */
110 unsigned int regmem
; /* codes register or memory operand */
111 unsigned int reg
; /* codes register operand (or extended opcode) */
112 unsigned int mode
; /* how to interpret regmem & reg */
116 /* x86-64 extension prefix. */
117 typedef int rex_byte
;
119 /* 386 opcode byte to code indirect addressing. */
128 /* x86 arch names, types and features */
131 const char *name
; /* arch name */
132 unsigned int len
; /* arch string length */
133 enum processor_type type
; /* arch type */
134 i386_cpu_flags flags
; /* cpu feature flags */
135 unsigned int skip
; /* show_arch should skip this. */
139 /* Used to turn off indicated flags. */
142 const char *name
; /* arch name */
143 unsigned int len
; /* arch string length */
144 i386_cpu_flags flags
; /* cpu feature flags */
148 static void update_code_flag (int, int);
149 static void set_code_flag (int);
150 static void set_16bit_gcc_code_flag (int);
151 static void set_intel_syntax (int);
152 static void set_intel_mnemonic (int);
153 static void set_allow_index_reg (int);
154 static void set_check (int);
155 static void set_cpu_arch (int);
157 static void pe_directive_secrel (int);
159 static void signed_cons (int);
160 static char *output_invalid (int c
);
161 static int i386_finalize_immediate (segT
, expressionS
*, i386_operand_type
,
163 static int i386_finalize_displacement (segT
, expressionS
*, i386_operand_type
,
165 static int i386_att_operand (char *);
166 static int i386_intel_operand (char *, int);
167 static int i386_intel_simplify (expressionS
*);
168 static int i386_intel_parse_name (const char *, expressionS
*);
169 static const reg_entry
*parse_register (char *, char **);
170 static char *parse_insn (char *, char *);
171 static char *parse_operands (char *, const char *);
172 static void swap_operands (void);
173 static void swap_2_operands (int, int);
174 static void optimize_imm (void);
175 static void optimize_disp (void);
176 static const insn_template
*match_template (char);
177 static int check_string (void);
178 static int process_suffix (void);
179 static int check_byte_reg (void);
180 static int check_long_reg (void);
181 static int check_qword_reg (void);
182 static int check_word_reg (void);
183 static int finalize_imm (void);
184 static int process_operands (void);
185 static const seg_entry
*build_modrm_byte (void);
186 static void output_insn (void);
187 static void output_imm (fragS
*, offsetT
);
188 static void output_disp (fragS
*, offsetT
);
190 static void s_bss (int);
192 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
193 static void handle_large_common (int small ATTRIBUTE_UNUSED
);
196 static const char *default_arch
= DEFAULT_ARCH
;
198 /* This struct describes rounding control and SAE in the instruction. */
212 static struct RC_Operation rc_op
;
214 /* The struct describes masking, applied to OPERAND in the instruction.
215 MASK is a pointer to the corresponding mask register. ZEROING tells
216 whether merging or zeroing mask is used. */
217 struct Mask_Operation
219 const reg_entry
*mask
;
220 unsigned int zeroing
;
221 /* The operand where this operation is associated. */
225 static struct Mask_Operation mask_op
;
227 /* The struct describes broadcasting, applied to OPERAND. FACTOR is
229 struct Broadcast_Operation
231 /* Type of broadcast: no broadcast, {1to8}, or {1to16}. */
234 /* Index of broadcasted operand. */
238 static struct Broadcast_Operation broadcast_op
;
243 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
244 unsigned char bytes
[4];
246 /* Destination or source register specifier. */
247 const reg_entry
*register_specifier
;
250 /* 'md_assemble ()' gathers together information and puts it into a
257 const reg_entry
*regs
;
262 operand_size_mismatch
,
263 operand_type_mismatch
,
264 register_type_mismatch
,
265 number_of_operands_mismatch
,
266 invalid_instruction_suffix
,
269 unsupported_with_intel_mnemonic
,
272 invalid_vsib_address
,
273 invalid_vector_register_set
,
274 unsupported_vector_index_register
,
275 unsupported_broadcast
,
276 broadcast_not_on_src_operand
,
279 mask_not_on_destination
,
282 rc_sae_operand_not_last_imm
,
283 invalid_register_operand
,
289 /* TM holds the template for the insn were currently assembling. */
292 /* SUFFIX holds the instruction size suffix for byte, word, dword
293 or qword, if given. */
296 /* OPERANDS gives the number of given operands. */
297 unsigned int operands
;
299 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
300 of given register, displacement, memory operands and immediate
302 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
304 /* TYPES [i] is the type (see above #defines) which tells us how to
305 use OP[i] for the corresponding operand. */
306 i386_operand_type types
[MAX_OPERANDS
];
308 /* Displacement expression, immediate expression, or register for each
310 union i386_op op
[MAX_OPERANDS
];
312 /* Flags for operands. */
313 unsigned int flags
[MAX_OPERANDS
];
314 #define Operand_PCrel 1
316 /* Relocation type for operand */
317 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
319 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
320 the base index byte below. */
321 const reg_entry
*base_reg
;
322 const reg_entry
*index_reg
;
323 unsigned int log2_scale_factor
;
325 /* SEG gives the seg_entries of this insn. They are zero unless
326 explicit segment overrides are given. */
327 const seg_entry
*seg
[2];
329 /* Copied first memory operand string, for re-checking. */
332 /* PREFIX holds all the given prefix opcodes (usually null).
333 PREFIXES is the number of prefix opcodes. */
334 unsigned int prefixes
;
335 unsigned char prefix
[MAX_PREFIXES
];
337 /* RM and SIB are the modrm byte and the sib byte where the
338 addressing modes of this insn are encoded. */
345 /* Masking attributes. */
346 struct Mask_Operation
*mask
;
348 /* Rounding control and SAE attributes. */
349 struct RC_Operation
*rounding
;
351 /* Broadcasting attributes. */
352 struct Broadcast_Operation
*broadcast
;
354 /* Compressed disp8*N attribute. */
355 unsigned int memshift
;
357 /* Prefer load or store in encoding. */
360 dir_encoding_default
= 0,
365 /* Prefer 8bit or 32bit displacement in encoding. */
368 disp_encoding_default
= 0,
373 /* How to encode vector instructions. */
376 vex_encoding_default
= 0,
383 const char *rep_prefix
;
386 const char *hle_prefix
;
388 /* Have BND prefix. */
389 const char *bnd_prefix
;
391 /* Have NOTRACK prefix. */
392 const char *notrack_prefix
;
395 enum i386_error error
;
398 typedef struct _i386_insn i386_insn
;
400 /* Link RC type with corresponding string, that'll be looked for in
409 static const struct RC_name RC_NamesTable
[] =
411 { rne
, STRING_COMMA_LEN ("rn-sae") },
412 { rd
, STRING_COMMA_LEN ("rd-sae") },
413 { ru
, STRING_COMMA_LEN ("ru-sae") },
414 { rz
, STRING_COMMA_LEN ("rz-sae") },
415 { saeonly
, STRING_COMMA_LEN ("sae") },
418 /* List of chars besides those in app.c:symbol_chars that can start an
419 operand. Used to prevent the scrubber eating vital white-space. */
420 const char extra_symbol_chars
[] = "*%-([{}"
429 #if (defined (TE_I386AIX) \
430 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
431 && !defined (TE_GNU) \
432 && !defined (TE_LINUX) \
433 && !defined (TE_NACL) \
434 && !defined (TE_NETWARE) \
435 && !defined (TE_FreeBSD) \
436 && !defined (TE_DragonFly) \
437 && !defined (TE_NetBSD)))
438 /* This array holds the chars that always start a comment. If the
439 pre-processor is disabled, these aren't very useful. The option
440 --divide will remove '/' from this list. */
441 const char *i386_comment_chars
= "#/";
442 #define SVR4_COMMENT_CHARS 1
443 #define PREFIX_SEPARATOR '\\'
446 const char *i386_comment_chars
= "#";
447 #define PREFIX_SEPARATOR '/'
450 /* This array holds the chars that only start a comment at the beginning of
451 a line. If the line seems to have the form '# 123 filename'
452 .line and .file directives will appear in the pre-processed output.
453 Note that input_file.c hand checks for '#' at the beginning of the
454 first line of the input file. This is because the compiler outputs
455 #NO_APP at the beginning of its output.
456 Also note that comments started like this one will always work if
457 '/' isn't otherwise defined. */
458 const char line_comment_chars
[] = "#/";
460 const char line_separator_chars
[] = ";";
462 /* Chars that can be used to separate mant from exp in floating point
464 const char EXP_CHARS
[] = "eE";
466 /* Chars that mean this number is a floating point constant
469 const char FLT_CHARS
[] = "fFdDxX";
471 /* Tables for lexical analysis. */
472 static char mnemonic_chars
[256];
473 static char register_chars
[256];
474 static char operand_chars
[256];
475 static char identifier_chars
[256];
476 static char digit_chars
[256];
478 /* Lexical macros. */
479 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
480 #define is_operand_char(x) (operand_chars[(unsigned char) x])
481 #define is_register_char(x) (register_chars[(unsigned char) x])
482 #define is_space_char(x) ((x) == ' ')
483 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
484 #define is_digit_char(x) (digit_chars[(unsigned char) x])
486 /* All non-digit non-letter characters that may occur in an operand. */
487 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
489 /* md_assemble() always leaves the strings it's passed unaltered. To
490 effect this we maintain a stack of saved characters that we've smashed
491 with '\0's (indicating end of strings for various sub-fields of the
492 assembler instruction). */
493 static char save_stack
[32];
494 static char *save_stack_p
;
495 #define END_STRING_AND_SAVE(s) \
496 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
497 #define RESTORE_END_STRING(s) \
498 do { *(s) = *--save_stack_p; } while (0)
500 /* The instruction we're assembling. */
503 /* Possible templates for current insn. */
504 static const templates
*current_templates
;
506 /* Per instruction expressionS buffers: max displacements & immediates. */
507 static expressionS disp_expressions
[MAX_MEMORY_OPERANDS
];
508 static expressionS im_expressions
[MAX_IMMEDIATE_OPERANDS
];
510 /* Current operand we are working on. */
511 static int this_operand
= -1;
513 /* We support four different modes. FLAG_CODE variable is used to distinguish
521 static enum flag_code flag_code
;
522 static unsigned int object_64bit
;
523 static unsigned int disallow_64bit_reloc
;
524 static int use_rela_relocations
= 0;
526 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
527 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
528 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
530 /* The ELF ABI to use. */
538 static enum x86_elf_abi x86_elf_abi
= I386_ABI
;
541 #if defined (TE_PE) || defined (TE_PEP)
542 /* Use big object file format. */
543 static int use_big_obj
= 0;
546 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
547 /* 1 if generating code for a shared library. */
548 static int shared
= 0;
551 /* 1 for intel syntax,
553 static int intel_syntax
= 0;
555 /* 1 for Intel64 ISA,
559 /* 1 for intel mnemonic,
560 0 if att mnemonic. */
561 static int intel_mnemonic
= !SYSV386_COMPAT
;
563 /* 1 if support old (<= 2.8.1) versions of gcc. */
564 static int old_gcc
= OLDGCC_COMPAT
;
566 /* 1 if pseudo registers are permitted. */
567 static int allow_pseudo_reg
= 0;
569 /* 1 if register prefix % not required. */
570 static int allow_naked_reg
= 0;
572 /* 1 if the assembler should add BND prefix for all control-transferring
573 instructions supporting it, even if this prefix wasn't specified
575 static int add_bnd_prefix
= 0;
577 /* 1 if pseudo index register, eiz/riz, is allowed . */
578 static int allow_index_reg
= 0;
580 /* 1 if the assembler should ignore LOCK prefix, even if it was
581 specified explicitly. */
582 static int omit_lock_prefix
= 0;
584 /* 1 if the assembler should encode lfence, mfence, and sfence as
585 "lock addl $0, (%{re}sp)". */
586 static int avoid_fence
= 0;
588 /* 1 if the assembler should generate relax relocations. */
590 static int generate_relax_relocations
591 = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS
;
593 static enum check_kind
599 sse_check
, operand_check
= check_warning
;
601 /* Register prefix used for error message. */
602 static const char *register_prefix
= "%";
604 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
605 leave, push, and pop instructions so that gcc has the same stack
606 frame as in 32 bit mode. */
607 static char stackop_size
= '\0';
609 /* Non-zero to optimize code alignment. */
610 int optimize_align_code
= 1;
612 /* Non-zero to quieten some warnings. */
613 static int quiet_warnings
= 0;
616 static const char *cpu_arch_name
= NULL
;
617 static char *cpu_sub_arch_name
= NULL
;
619 /* CPU feature flags. */
620 static i386_cpu_flags cpu_arch_flags
= CPU_UNKNOWN_FLAGS
;
622 /* If we have selected a cpu we are generating instructions for. */
623 static int cpu_arch_tune_set
= 0;
625 /* Cpu we are generating instructions for. */
626 enum processor_type cpu_arch_tune
= PROCESSOR_UNKNOWN
;
628 /* CPU feature flags of cpu we are generating instructions for. */
629 static i386_cpu_flags cpu_arch_tune_flags
;
631 /* CPU instruction set architecture used. */
632 enum processor_type cpu_arch_isa
= PROCESSOR_UNKNOWN
;
634 /* CPU feature flags of instruction set architecture used. */
635 i386_cpu_flags cpu_arch_isa_flags
;
637 /* If set, conditional jumps are not automatically promoted to handle
638 larger than a byte offset. */
639 static unsigned int no_cond_jump_promotion
= 0;
641 /* Encode SSE instructions with VEX prefix. */
642 static unsigned int sse2avx
;
644 /* Encode scalar AVX instructions with specific vector length. */
651 /* Encode scalar EVEX LIG instructions with specific vector length. */
659 /* Encode EVEX WIG instructions with specific evex.w. */
666 /* Value to encode in EVEX RC bits, for SAE-only instructions. */
667 static enum rc_type evexrcig
= rne
;
669 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
670 static symbolS
*GOT_symbol
;
672 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
673 unsigned int x86_dwarf2_return_column
;
675 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
676 int x86_cie_data_alignment
;
678 /* Interface to relax_segment.
679 There are 3 major relax states for 386 jump insns because the
680 different types of jumps add different sizes to frags when we're
681 figuring out what sort of jump to choose to reach a given label. */
684 #define UNCOND_JUMP 0
686 #define COND_JUMP86 2
691 #define SMALL16 (SMALL | CODE16)
693 #define BIG16 (BIG | CODE16)
697 #define INLINE __inline__
703 #define ENCODE_RELAX_STATE(type, size) \
704 ((relax_substateT) (((type) << 2) | (size)))
705 #define TYPE_FROM_RELAX_STATE(s) \
707 #define DISP_SIZE_FROM_RELAX_STATE(s) \
708 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
710 /* This table is used by relax_frag to promote short jumps to long
711 ones where necessary. SMALL (short) jumps may be promoted to BIG
712 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
713 don't allow a short jump in a 32 bit code segment to be promoted to
714 a 16 bit offset jump because it's slower (requires data size
715 prefix), and doesn't work, unless the destination is in the bottom
716 64k of the code segment (The top 16 bits of eip are zeroed). */
718 const relax_typeS md_relax_table
[] =
721 1) most positive reach of this state,
722 2) most negative reach of this state,
723 3) how many bytes this mode will have in the variable part of the frag
724 4) which index into the table to try if we can't fit into this one. */
726 /* UNCOND_JUMP states. */
727 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
728 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
729 /* dword jmp adds 4 bytes to frag:
730 0 extra opcode bytes, 4 displacement bytes. */
732 /* word jmp adds 2 byte2 to frag:
733 0 extra opcode bytes, 2 displacement bytes. */
736 /* COND_JUMP states. */
737 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
738 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
739 /* dword conditionals adds 5 bytes to frag:
740 1 extra opcode byte, 4 displacement bytes. */
742 /* word conditionals add 3 bytes to frag:
743 1 extra opcode byte, 2 displacement bytes. */
746 /* COND_JUMP86 states. */
747 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
748 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
749 /* dword conditionals adds 5 bytes to frag:
750 1 extra opcode byte, 4 displacement bytes. */
752 /* word conditionals add 4 bytes to frag:
753 1 displacement byte and a 3 byte long branch insn. */
757 static const arch_entry cpu_arch
[] =
759 /* Do not replace the first two entries - i386_target_format()
760 relies on them being there in this order. */
761 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32
,
762 CPU_GENERIC32_FLAGS
, 0 },
763 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64
,
764 CPU_GENERIC64_FLAGS
, 0 },
765 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN
,
767 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN
,
769 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN
,
771 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386
,
773 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486
,
775 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM
,
777 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO
,
779 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM
,
781 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO
,
782 CPU_PENTIUMPRO_FLAGS
, 0 },
783 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO
,
785 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO
,
787 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4
,
789 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA
,
791 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA
,
792 CPU_NOCONA_FLAGS
, 0 },
793 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE
,
795 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE
,
797 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2
,
798 CPU_CORE2_FLAGS
, 1 },
799 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2
,
800 CPU_CORE2_FLAGS
, 0 },
801 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7
,
802 CPU_COREI7_FLAGS
, 0 },
803 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM
,
805 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM
,
807 { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU
,
808 CPU_IAMCU_FLAGS
, 0 },
809 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6
,
811 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6
,
813 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON
,
814 CPU_ATHLON_FLAGS
, 0 },
815 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8
,
817 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8
,
819 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8
,
821 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10
,
822 CPU_AMDFAM10_FLAGS
, 0 },
823 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD
,
824 CPU_BDVER1_FLAGS
, 0 },
825 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD
,
826 CPU_BDVER2_FLAGS
, 0 },
827 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD
,
828 CPU_BDVER3_FLAGS
, 0 },
829 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD
,
830 CPU_BDVER4_FLAGS
, 0 },
831 { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER
,
832 CPU_ZNVER1_FLAGS
, 0 },
833 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT
,
834 CPU_BTVER1_FLAGS
, 0 },
835 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT
,
836 CPU_BTVER2_FLAGS
, 0 },
837 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN
,
839 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN
,
841 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN
,
843 { STRING_COMMA_LEN (".687"), PROCESSOR_UNKNOWN
,
845 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN
,
847 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN
,
849 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN
,
851 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN
,
853 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN
,
854 CPU_SSSE3_FLAGS
, 0 },
855 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN
,
856 CPU_SSE4_1_FLAGS
, 0 },
857 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN
,
858 CPU_SSE4_2_FLAGS
, 0 },
859 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN
,
860 CPU_SSE4_2_FLAGS
, 0 },
861 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN
,
863 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN
,
865 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN
,
866 CPU_AVX512F_FLAGS
, 0 },
867 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN
,
868 CPU_AVX512CD_FLAGS
, 0 },
869 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN
,
870 CPU_AVX512ER_FLAGS
, 0 },
871 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN
,
872 CPU_AVX512PF_FLAGS
, 0 },
873 { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN
,
874 CPU_AVX512DQ_FLAGS
, 0 },
875 { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN
,
876 CPU_AVX512BW_FLAGS
, 0 },
877 { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN
,
878 CPU_AVX512VL_FLAGS
, 0 },
879 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN
,
881 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN
,
882 CPU_VMFUNC_FLAGS
, 0 },
883 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN
,
885 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN
,
886 CPU_XSAVE_FLAGS
, 0 },
887 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN
,
888 CPU_XSAVEOPT_FLAGS
, 0 },
889 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN
,
890 CPU_XSAVEC_FLAGS
, 0 },
891 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN
,
892 CPU_XSAVES_FLAGS
, 0 },
893 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN
,
895 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN
,
896 CPU_PCLMUL_FLAGS
, 0 },
897 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN
,
898 CPU_PCLMUL_FLAGS
, 1 },
899 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN
,
900 CPU_FSGSBASE_FLAGS
, 0 },
901 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN
,
902 CPU_RDRND_FLAGS
, 0 },
903 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN
,
905 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN
,
907 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN
,
909 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN
,
911 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN
,
913 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN
,
915 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN
,
916 CPU_MOVBE_FLAGS
, 0 },
917 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN
,
919 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN
,
921 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN
,
922 CPU_LZCNT_FLAGS
, 0 },
923 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN
,
925 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN
,
927 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN
,
928 CPU_INVPCID_FLAGS
, 0 },
929 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN
,
930 CPU_CLFLUSH_FLAGS
, 0 },
931 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN
,
933 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN
,
934 CPU_SYSCALL_FLAGS
, 0 },
935 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN
,
936 CPU_RDTSCP_FLAGS
, 0 },
937 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN
,
938 CPU_3DNOW_FLAGS
, 0 },
939 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN
,
940 CPU_3DNOWA_FLAGS
, 0 },
941 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN
,
942 CPU_PADLOCK_FLAGS
, 0 },
943 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN
,
945 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN
,
947 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN
,
948 CPU_SSE4A_FLAGS
, 0 },
949 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN
,
951 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN
,
953 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN
,
955 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN
,
957 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN
,
958 CPU_RDSEED_FLAGS
, 0 },
959 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN
,
960 CPU_PRFCHW_FLAGS
, 0 },
961 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN
,
963 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN
,
965 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN
,
967 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN
,
968 CPU_CLFLUSHOPT_FLAGS
, 0 },
969 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN
,
970 CPU_PREFETCHWT1_FLAGS
, 0 },
971 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN
,
973 { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN
,
975 { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN
,
976 CPU_AVX512IFMA_FLAGS
, 0 },
977 { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN
,
978 CPU_AVX512VBMI_FLAGS
, 0 },
979 { STRING_COMMA_LEN (".avx512_4fmaps"), PROCESSOR_UNKNOWN
,
980 CPU_AVX512_4FMAPS_FLAGS
, 0 },
981 { STRING_COMMA_LEN (".avx512_4vnniw"), PROCESSOR_UNKNOWN
,
982 CPU_AVX512_4VNNIW_FLAGS
, 0 },
983 { STRING_COMMA_LEN (".avx512_vpopcntdq"), PROCESSOR_UNKNOWN
,
984 CPU_AVX512_VPOPCNTDQ_FLAGS
, 0 },
985 { STRING_COMMA_LEN (".avx512_vbmi2"), PROCESSOR_UNKNOWN
,
986 CPU_AVX512_VBMI2_FLAGS
, 0 },
987 { STRING_COMMA_LEN (".avx512_vnni"), PROCESSOR_UNKNOWN
,
988 CPU_AVX512_VNNI_FLAGS
, 0 },
989 { STRING_COMMA_LEN (".avx512_bitalg"), PROCESSOR_UNKNOWN
,
990 CPU_AVX512_BITALG_FLAGS
, 0 },
991 { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN
,
992 CPU_CLZERO_FLAGS
, 0 },
993 { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN
,
994 CPU_MWAITX_FLAGS
, 0 },
995 { STRING_COMMA_LEN (".ospke"), PROCESSOR_UNKNOWN
,
996 CPU_OSPKE_FLAGS
, 0 },
997 { STRING_COMMA_LEN (".rdpid"), PROCESSOR_UNKNOWN
,
998 CPU_RDPID_FLAGS
, 0 },
999 { STRING_COMMA_LEN (".ptwrite"), PROCESSOR_UNKNOWN
,
1000 CPU_PTWRITE_FLAGS
, 0 },
1001 { STRING_COMMA_LEN (".cet"), PROCESSOR_UNKNOWN
,
1003 { STRING_COMMA_LEN (".gfni"), PROCESSOR_UNKNOWN
,
1004 CPU_GFNI_FLAGS
, 0 },
1005 { STRING_COMMA_LEN (".vaes"), PROCESSOR_UNKNOWN
,
1006 CPU_VAES_FLAGS
, 0 },
1007 { STRING_COMMA_LEN (".vpclmulqdq"), PROCESSOR_UNKNOWN
,
1008 CPU_VPCLMULQDQ_FLAGS
, 0 },
1011 static const noarch_entry cpu_noarch
[] =
1013 { STRING_COMMA_LEN ("no87"), CPU_ANY_X87_FLAGS
},
1014 { STRING_COMMA_LEN ("no287"), CPU_ANY_287_FLAGS
},
1015 { STRING_COMMA_LEN ("no387"), CPU_ANY_387_FLAGS
},
1016 { STRING_COMMA_LEN ("no687"), CPU_ANY_687_FLAGS
},
1017 { STRING_COMMA_LEN ("nommx"), CPU_ANY_MMX_FLAGS
},
1018 { STRING_COMMA_LEN ("nosse"), CPU_ANY_SSE_FLAGS
},
1019 { STRING_COMMA_LEN ("nosse2"), CPU_ANY_SSE2_FLAGS
},
1020 { STRING_COMMA_LEN ("nosse3"), CPU_ANY_SSE3_FLAGS
},
1021 { STRING_COMMA_LEN ("nossse3"), CPU_ANY_SSSE3_FLAGS
},
1022 { STRING_COMMA_LEN ("nosse4.1"), CPU_ANY_SSE4_1_FLAGS
},
1023 { STRING_COMMA_LEN ("nosse4.2"), CPU_ANY_SSE4_2_FLAGS
},
1024 { STRING_COMMA_LEN ("nosse4"), CPU_ANY_SSE4_1_FLAGS
},
1025 { STRING_COMMA_LEN ("noavx"), CPU_ANY_AVX_FLAGS
},
1026 { STRING_COMMA_LEN ("noavx2"), CPU_ANY_AVX2_FLAGS
},
1027 { STRING_COMMA_LEN ("noavx512f"), CPU_ANY_AVX512F_FLAGS
},
1028 { STRING_COMMA_LEN ("noavx512cd"), CPU_ANY_AVX512CD_FLAGS
},
1029 { STRING_COMMA_LEN ("noavx512er"), CPU_ANY_AVX512ER_FLAGS
},
1030 { STRING_COMMA_LEN ("noavx512pf"), CPU_ANY_AVX512PF_FLAGS
},
1031 { STRING_COMMA_LEN ("noavx512dq"), CPU_ANY_AVX512DQ_FLAGS
},
1032 { STRING_COMMA_LEN ("noavx512bw"), CPU_ANY_AVX512BW_FLAGS
},
1033 { STRING_COMMA_LEN ("noavx512vl"), CPU_ANY_AVX512VL_FLAGS
},
1034 { STRING_COMMA_LEN ("noavx512ifma"), CPU_ANY_AVX512IFMA_FLAGS
},
1035 { STRING_COMMA_LEN ("noavx512vbmi"), CPU_ANY_AVX512VBMI_FLAGS
},
1036 { STRING_COMMA_LEN ("noavx512_4fmaps"), CPU_ANY_AVX512_4FMAPS_FLAGS
},
1037 { STRING_COMMA_LEN ("noavx512_4vnniw"), CPU_ANY_AVX512_4VNNIW_FLAGS
},
1038 { STRING_COMMA_LEN ("noavx512_vpopcntdq"), CPU_ANY_AVX512_VPOPCNTDQ_FLAGS
},
1039 { STRING_COMMA_LEN ("noavx512_vbmi2"), CPU_ANY_AVX512_VBMI2_FLAGS
},
1040 { STRING_COMMA_LEN ("noavx512_vnni"), CPU_ANY_AVX512_VNNI_FLAGS
},
1041 { STRING_COMMA_LEN ("noavx512_bitalg"), CPU_ANY_AVX512_BITALG_FLAGS
},
1045 /* Like s_lcomm_internal in gas/read.c but the alignment string
1046 is allowed to be optional. */
1049 pe_lcomm_internal (int needs_align
, symbolS
*symbolP
, addressT size
)
1056 && *input_line_pointer
== ',')
1058 align
= parse_align (needs_align
- 1);
1060 if (align
== (addressT
) -1)
1075 bss_alloc (symbolP
, size
, align
);
1080 pe_lcomm (int needs_align
)
1082 s_comm_internal (needs_align
* 2, pe_lcomm_internal
);
1086 const pseudo_typeS md_pseudo_table
[] =
1088 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
1089 {"align", s_align_bytes
, 0},
1091 {"align", s_align_ptwo
, 0},
1093 {"arch", set_cpu_arch
, 0},
1097 {"lcomm", pe_lcomm
, 1},
1099 {"ffloat", float_cons
, 'f'},
1100 {"dfloat", float_cons
, 'd'},
1101 {"tfloat", float_cons
, 'x'},
1103 {"slong", signed_cons
, 4},
1104 {"noopt", s_ignore
, 0},
1105 {"optim", s_ignore
, 0},
1106 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
1107 {"code16", set_code_flag
, CODE_16BIT
},
1108 {"code32", set_code_flag
, CODE_32BIT
},
1110 {"code64", set_code_flag
, CODE_64BIT
},
1112 {"intel_syntax", set_intel_syntax
, 1},
1113 {"att_syntax", set_intel_syntax
, 0},
1114 {"intel_mnemonic", set_intel_mnemonic
, 1},
1115 {"att_mnemonic", set_intel_mnemonic
, 0},
1116 {"allow_index_reg", set_allow_index_reg
, 1},
1117 {"disallow_index_reg", set_allow_index_reg
, 0},
1118 {"sse_check", set_check
, 0},
1119 {"operand_check", set_check
, 1},
1120 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1121 {"largecomm", handle_large_common
, 0},
1123 {"file", (void (*) (int)) dwarf2_directive_file
, 0},
1124 {"loc", dwarf2_directive_loc
, 0},
1125 {"loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0},
1128 {"secrel32", pe_directive_secrel
, 0},
1133 /* For interface with expression (). */
1134 extern char *input_line_pointer
;
1136 /* Hash table for instruction mnemonic lookup. */
1137 static struct hash_control
*op_hash
;
1139 /* Hash table for register lookup. */
1140 static struct hash_control
*reg_hash
;
1143 i386_align_code (fragS
*fragP
, int count
)
1145 /* Various efficient no-op patterns for aligning code labels.
1146 Note: Don't try to assemble the instructions in the comments.
1147 0L and 0w are not legal. */
1148 static const unsigned char f32_1
[] =
1150 static const unsigned char f32_2
[] =
1151 {0x66,0x90}; /* xchg %ax,%ax */
1152 static const unsigned char f32_3
[] =
1153 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1154 static const unsigned char f32_4
[] =
1155 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1156 static const unsigned char f32_5
[] =
1158 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1159 static const unsigned char f32_6
[] =
1160 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1161 static const unsigned char f32_7
[] =
1162 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1163 static const unsigned char f32_8
[] =
1165 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1166 static const unsigned char f32_9
[] =
1167 {0x89,0xf6, /* movl %esi,%esi */
1168 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1169 static const unsigned char f32_10
[] =
1170 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
1171 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1172 static const unsigned char f32_11
[] =
1173 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
1174 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1175 static const unsigned char f32_12
[] =
1176 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1177 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
1178 static const unsigned char f32_13
[] =
1179 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1180 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1181 static const unsigned char f32_14
[] =
1182 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
1183 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1184 static const unsigned char f16_3
[] =
1185 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
1186 static const unsigned char f16_4
[] =
1187 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
1188 static const unsigned char f16_5
[] =
1190 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
1191 static const unsigned char f16_6
[] =
1192 {0x89,0xf6, /* mov %si,%si */
1193 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1194 static const unsigned char f16_7
[] =
1195 {0x8d,0x74,0x00, /* lea 0(%si),%si */
1196 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1197 static const unsigned char f16_8
[] =
1198 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
1199 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1200 static const unsigned char jump_31
[] =
1201 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
1202 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1203 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1204 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
1205 static const unsigned char *const f32_patt
[] = {
1206 f32_1
, f32_2
, f32_3
, f32_4
, f32_5
, f32_6
, f32_7
, f32_8
,
1207 f32_9
, f32_10
, f32_11
, f32_12
, f32_13
, f32_14
1209 static const unsigned char *const f16_patt
[] = {
1210 f32_1
, f32_2
, f16_3
, f16_4
, f16_5
, f16_6
, f16_7
, f16_8
1212 /* nopl (%[re]ax) */
1213 static const unsigned char alt_3
[] =
1215 /* nopl 0(%[re]ax) */
1216 static const unsigned char alt_4
[] =
1217 {0x0f,0x1f,0x40,0x00};
1218 /* nopl 0(%[re]ax,%[re]ax,1) */
1219 static const unsigned char alt_5
[] =
1220 {0x0f,0x1f,0x44,0x00,0x00};
1221 /* nopw 0(%[re]ax,%[re]ax,1) */
1222 static const unsigned char alt_6
[] =
1223 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1224 /* nopl 0L(%[re]ax) */
1225 static const unsigned char alt_7
[] =
1226 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1227 /* nopl 0L(%[re]ax,%[re]ax,1) */
1228 static const unsigned char alt_8
[] =
1229 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1230 /* nopw 0L(%[re]ax,%[re]ax,1) */
1231 static const unsigned char alt_9
[] =
1232 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1233 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1234 static const unsigned char alt_10
[] =
1235 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1236 static const unsigned char *const alt_patt
[] = {
1237 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
1241 /* Only align for at least a positive non-zero boundary. */
1242 if (count
<= 0 || count
> MAX_MEM_FOR_RS_ALIGN_CODE
)
1245 /* We need to decide which NOP sequence to use for 32bit and
1246 64bit. When -mtune= is used:
1248 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1249 PROCESSOR_GENERIC32, f32_patt will be used.
1250 2. For the rest, alt_patt will be used.
1252 When -mtune= isn't used, alt_patt will be used if
1253 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
1256 When -march= or .arch is used, we can't use anything beyond
1257 cpu_arch_isa_flags. */
1259 if (flag_code
== CODE_16BIT
)
1263 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1265 /* Adjust jump offset. */
1266 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
1269 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1270 f16_patt
[count
- 1], count
);
1274 const unsigned char *const *patt
= NULL
;
1276 if (fragP
->tc_frag_data
.isa
== PROCESSOR_UNKNOWN
)
1278 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1279 switch (cpu_arch_tune
)
1281 case PROCESSOR_UNKNOWN
:
1282 /* We use cpu_arch_isa_flags to check if we SHOULD
1283 optimize with nops. */
1284 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1289 case PROCESSOR_PENTIUM4
:
1290 case PROCESSOR_NOCONA
:
1291 case PROCESSOR_CORE
:
1292 case PROCESSOR_CORE2
:
1293 case PROCESSOR_COREI7
:
1294 case PROCESSOR_L1OM
:
1295 case PROCESSOR_K1OM
:
1296 case PROCESSOR_GENERIC64
:
1298 case PROCESSOR_ATHLON
:
1300 case PROCESSOR_AMDFAM10
:
1302 case PROCESSOR_ZNVER
:
1306 case PROCESSOR_I386
:
1307 case PROCESSOR_I486
:
1308 case PROCESSOR_PENTIUM
:
1309 case PROCESSOR_PENTIUMPRO
:
1310 case PROCESSOR_IAMCU
:
1311 case PROCESSOR_GENERIC32
:
1318 switch (fragP
->tc_frag_data
.tune
)
1320 case PROCESSOR_UNKNOWN
:
1321 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1322 PROCESSOR_UNKNOWN. */
1326 case PROCESSOR_I386
:
1327 case PROCESSOR_I486
:
1328 case PROCESSOR_PENTIUM
:
1329 case PROCESSOR_IAMCU
:
1331 case PROCESSOR_ATHLON
:
1333 case PROCESSOR_AMDFAM10
:
1335 case PROCESSOR_ZNVER
:
1337 case PROCESSOR_GENERIC32
:
1338 /* We use cpu_arch_isa_flags to check if we CAN optimize
1340 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1345 case PROCESSOR_PENTIUMPRO
:
1346 case PROCESSOR_PENTIUM4
:
1347 case PROCESSOR_NOCONA
:
1348 case PROCESSOR_CORE
:
1349 case PROCESSOR_CORE2
:
1350 case PROCESSOR_COREI7
:
1351 case PROCESSOR_L1OM
:
1352 case PROCESSOR_K1OM
:
1353 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1358 case PROCESSOR_GENERIC64
:
1364 if (patt
== f32_patt
)
1366 /* If the padding is less than 15 bytes, we use the normal
1367 ones. Otherwise, we use a jump instruction and adjust
1371 /* For 64bit, the limit is 3 bytes. */
1372 if (flag_code
== CODE_64BIT
1373 && fragP
->tc_frag_data
.isa_flags
.bitfield
.cpulm
)
1378 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1379 patt
[count
- 1], count
);
1382 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1384 /* Adjust jump offset. */
1385 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
1390 /* Maximum length of an instruction is 10 byte. If the
1391 padding is greater than 10 bytes and we don't use jump,
1392 we have to break it into smaller pieces. */
1393 int padding
= count
;
1394 while (padding
> 10)
1397 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
+ padding
,
1402 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1403 patt
[padding
- 1], padding
);
1406 fragP
->fr_var
= count
;
1410 operand_type_all_zero (const union i386_operand_type
*x
)
1412 switch (ARRAY_SIZE(x
->array
))
1423 return !x
->array
[0];
1430 operand_type_set (union i386_operand_type
*x
, unsigned int v
)
1432 switch (ARRAY_SIZE(x
->array
))
1450 operand_type_equal (const union i386_operand_type
*x
,
1451 const union i386_operand_type
*y
)
1453 switch (ARRAY_SIZE(x
->array
))
1456 if (x
->array
[2] != y
->array
[2])
1460 if (x
->array
[1] != y
->array
[1])
1464 return x
->array
[0] == y
->array
[0];
1472 cpu_flags_all_zero (const union i386_cpu_flags
*x
)
1474 switch (ARRAY_SIZE(x
->array
))
1489 return !x
->array
[0];
1496 cpu_flags_equal (const union i386_cpu_flags
*x
,
1497 const union i386_cpu_flags
*y
)
1499 switch (ARRAY_SIZE(x
->array
))
1502 if (x
->array
[3] != y
->array
[3])
1506 if (x
->array
[2] != y
->array
[2])
1510 if (x
->array
[1] != y
->array
[1])
1514 return x
->array
[0] == y
->array
[0];
1522 cpu_flags_check_cpu64 (i386_cpu_flags f
)
1524 return !((flag_code
== CODE_64BIT
&& f
.bitfield
.cpuno64
)
1525 || (flag_code
!= CODE_64BIT
&& f
.bitfield
.cpu64
));
1528 static INLINE i386_cpu_flags
1529 cpu_flags_and (i386_cpu_flags x
, i386_cpu_flags y
)
1531 switch (ARRAY_SIZE (x
.array
))
1534 x
.array
[3] &= y
.array
[3];
1537 x
.array
[2] &= y
.array
[2];
1540 x
.array
[1] &= y
.array
[1];
1543 x
.array
[0] &= y
.array
[0];
1551 static INLINE i386_cpu_flags
1552 cpu_flags_or (i386_cpu_flags x
, i386_cpu_flags y
)
1554 switch (ARRAY_SIZE (x
.array
))
1557 x
.array
[3] |= y
.array
[3];
1560 x
.array
[2] |= y
.array
[2];
1563 x
.array
[1] |= y
.array
[1];
1566 x
.array
[0] |= y
.array
[0];
1574 static INLINE i386_cpu_flags
1575 cpu_flags_and_not (i386_cpu_flags x
, i386_cpu_flags y
)
1577 switch (ARRAY_SIZE (x
.array
))
1580 x
.array
[3] &= ~y
.array
[3];
1583 x
.array
[2] &= ~y
.array
[2];
1586 x
.array
[1] &= ~y
.array
[1];
1589 x
.array
[0] &= ~y
.array
[0];
1597 #define CPU_FLAGS_ARCH_MATCH 0x1
1598 #define CPU_FLAGS_64BIT_MATCH 0x2
1599 #define CPU_FLAGS_AES_MATCH 0x4
1600 #define CPU_FLAGS_PCLMUL_MATCH 0x8
1601 #define CPU_FLAGS_AVX_MATCH 0x10
1603 #define CPU_FLAGS_32BIT_MATCH \
1604 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH \
1605 | CPU_FLAGS_PCLMUL_MATCH | CPU_FLAGS_AVX_MATCH)
1606 #define CPU_FLAGS_PERFECT_MATCH \
1607 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)
1609 /* Return CPU flags match bits. */
1612 cpu_flags_match (const insn_template
*t
)
1614 i386_cpu_flags x
= t
->cpu_flags
;
1615 int match
= cpu_flags_check_cpu64 (x
) ? CPU_FLAGS_64BIT_MATCH
: 0;
1617 x
.bitfield
.cpu64
= 0;
1618 x
.bitfield
.cpuno64
= 0;
1620 if (cpu_flags_all_zero (&x
))
1622 /* This instruction is available on all archs. */
1623 match
|= CPU_FLAGS_32BIT_MATCH
;
1627 /* This instruction is available only on some archs. */
1628 i386_cpu_flags cpu
= cpu_arch_flags
;
1630 cpu
= cpu_flags_and (x
, cpu
);
1631 if (!cpu_flags_all_zero (&cpu
))
1633 if (x
.bitfield
.cpuavx
)
1635 /* We only need to check AES/PCLMUL/SSE2AVX with AVX. */
1636 if (cpu
.bitfield
.cpuavx
)
1638 /* Check SSE2AVX. */
1639 if (!t
->opcode_modifier
.sse2avx
|| sse2avx
)
1641 match
|= (CPU_FLAGS_ARCH_MATCH
1642 | CPU_FLAGS_AVX_MATCH
);
1644 if (!x
.bitfield
.cpuaes
|| cpu
.bitfield
.cpuaes
)
1645 match
|= CPU_FLAGS_AES_MATCH
;
1647 if (!x
.bitfield
.cpupclmul
1648 || cpu
.bitfield
.cpupclmul
)
1649 match
|= CPU_FLAGS_PCLMUL_MATCH
;
1653 match
|= CPU_FLAGS_ARCH_MATCH
;
1655 else if (x
.bitfield
.cpuavx512vl
)
1657 /* Match AVX512VL. */
1658 if (cpu
.bitfield
.cpuavx512vl
)
1660 /* Need another match. */
1661 cpu
.bitfield
.cpuavx512vl
= 0;
1662 if (!cpu_flags_all_zero (&cpu
))
1663 match
|= CPU_FLAGS_32BIT_MATCH
;
1665 match
|= CPU_FLAGS_ARCH_MATCH
;
1668 match
|= CPU_FLAGS_ARCH_MATCH
;
1671 match
|= CPU_FLAGS_32BIT_MATCH
;
1677 static INLINE i386_operand_type
1678 operand_type_and (i386_operand_type x
, i386_operand_type y
)
1680 switch (ARRAY_SIZE (x
.array
))
1683 x
.array
[2] &= y
.array
[2];
1686 x
.array
[1] &= y
.array
[1];
1689 x
.array
[0] &= y
.array
[0];
1697 static INLINE i386_operand_type
1698 operand_type_or (i386_operand_type x
, i386_operand_type y
)
1700 switch (ARRAY_SIZE (x
.array
))
1703 x
.array
[2] |= y
.array
[2];
1706 x
.array
[1] |= y
.array
[1];
1709 x
.array
[0] |= y
.array
[0];
1717 static INLINE i386_operand_type
1718 operand_type_xor (i386_operand_type x
, i386_operand_type y
)
1720 switch (ARRAY_SIZE (x
.array
))
1723 x
.array
[2] ^= y
.array
[2];
1726 x
.array
[1] ^= y
.array
[1];
1729 x
.array
[0] ^= y
.array
[0];
1737 static const i386_operand_type acc32
= OPERAND_TYPE_ACC32
;
1738 static const i386_operand_type acc64
= OPERAND_TYPE_ACC64
;
1739 static const i386_operand_type control
= OPERAND_TYPE_CONTROL
;
1740 static const i386_operand_type inoutportreg
1741 = OPERAND_TYPE_INOUTPORTREG
;
1742 static const i386_operand_type reg16_inoutportreg
1743 = OPERAND_TYPE_REG16_INOUTPORTREG
;
1744 static const i386_operand_type disp16
= OPERAND_TYPE_DISP16
;
1745 static const i386_operand_type disp32
= OPERAND_TYPE_DISP32
;
1746 static const i386_operand_type disp32s
= OPERAND_TYPE_DISP32S
;
1747 static const i386_operand_type disp16_32
= OPERAND_TYPE_DISP16_32
;
1748 static const i386_operand_type anydisp
1749 = OPERAND_TYPE_ANYDISP
;
1750 static const i386_operand_type regxmm
= OPERAND_TYPE_REGXMM
;
1751 static const i386_operand_type regymm
= OPERAND_TYPE_REGYMM
;
1752 static const i386_operand_type regzmm
= OPERAND_TYPE_REGZMM
;
1753 static const i386_operand_type regmask
= OPERAND_TYPE_REGMASK
;
1754 static const i386_operand_type imm8
= OPERAND_TYPE_IMM8
;
1755 static const i386_operand_type imm8s
= OPERAND_TYPE_IMM8S
;
1756 static const i386_operand_type imm16
= OPERAND_TYPE_IMM16
;
1757 static const i386_operand_type imm32
= OPERAND_TYPE_IMM32
;
1758 static const i386_operand_type imm32s
= OPERAND_TYPE_IMM32S
;
1759 static const i386_operand_type imm64
= OPERAND_TYPE_IMM64
;
1760 static const i386_operand_type imm16_32
= OPERAND_TYPE_IMM16_32
;
1761 static const i386_operand_type imm16_32s
= OPERAND_TYPE_IMM16_32S
;
1762 static const i386_operand_type imm16_32_32s
= OPERAND_TYPE_IMM16_32_32S
;
1763 static const i386_operand_type vec_imm4
= OPERAND_TYPE_VEC_IMM4
;
1774 operand_type_check (i386_operand_type t
, enum operand_type c
)
1779 return (t
.bitfield
.reg8
1782 || t
.bitfield
.reg64
);
1785 return (t
.bitfield
.imm8
1789 || t
.bitfield
.imm32s
1790 || t
.bitfield
.imm64
);
1793 return (t
.bitfield
.disp8
1794 || t
.bitfield
.disp16
1795 || t
.bitfield
.disp32
1796 || t
.bitfield
.disp32s
1797 || t
.bitfield
.disp64
);
1800 return (t
.bitfield
.disp8
1801 || t
.bitfield
.disp16
1802 || t
.bitfield
.disp32
1803 || t
.bitfield
.disp32s
1804 || t
.bitfield
.disp64
1805 || t
.bitfield
.baseindex
);
1814 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1815 operand J for instruction template T. */
1818 match_reg_size (const insn_template
*t
, unsigned int j
)
1820 return !((i
.types
[j
].bitfield
.byte
1821 && !t
->operand_types
[j
].bitfield
.byte
)
1822 || (i
.types
[j
].bitfield
.word
1823 && !t
->operand_types
[j
].bitfield
.word
)
1824 || (i
.types
[j
].bitfield
.dword
1825 && !t
->operand_types
[j
].bitfield
.dword
)
1826 || (i
.types
[j
].bitfield
.qword
1827 && !t
->operand_types
[j
].bitfield
.qword
));
1830 /* Return 1 if there is no conflict in any size on operand J for
1831 instruction template T. */
1834 match_mem_size (const insn_template
*t
, unsigned int j
)
1836 return (match_reg_size (t
, j
)
1837 && !((i
.types
[j
].bitfield
.unspecified
1839 && !t
->operand_types
[j
].bitfield
.unspecified
)
1840 || (i
.types
[j
].bitfield
.fword
1841 && !t
->operand_types
[j
].bitfield
.fword
)
1842 || (i
.types
[j
].bitfield
.tbyte
1843 && !t
->operand_types
[j
].bitfield
.tbyte
)
1844 || (i
.types
[j
].bitfield
.xmmword
1845 && !t
->operand_types
[j
].bitfield
.xmmword
)
1846 || (i
.types
[j
].bitfield
.ymmword
1847 && !t
->operand_types
[j
].bitfield
.ymmword
)
1848 || (i
.types
[j
].bitfield
.zmmword
1849 && !t
->operand_types
[j
].bitfield
.zmmword
)));
1852 /* Return 1 if there is no size conflict on any operands for
1853 instruction template T. */
1856 operand_size_match (const insn_template
*t
)
1861 /* Don't check jump instructions. */
1862 if (t
->opcode_modifier
.jump
1863 || t
->opcode_modifier
.jumpbyte
1864 || t
->opcode_modifier
.jumpdword
1865 || t
->opcode_modifier
.jumpintersegment
)
1868 /* Check memory and accumulator operand size. */
1869 for (j
= 0; j
< i
.operands
; j
++)
1871 if (t
->operand_types
[j
].bitfield
.anysize
)
1874 if (t
->operand_types
[j
].bitfield
.acc
&& !match_reg_size (t
, j
))
1880 if (i
.types
[j
].bitfield
.mem
&& !match_mem_size (t
, j
))
1889 else if (!t
->opcode_modifier
.d
&& !t
->opcode_modifier
.floatd
)
1892 i
.error
= operand_size_mismatch
;
1896 /* Check reverse. */
1897 gas_assert (i
.operands
== 2);
1900 for (j
= 0; j
< 2; j
++)
1902 if (t
->operand_types
[j
].bitfield
.acc
1903 && !match_reg_size (t
, j
? 0 : 1))
1906 if (i
.types
[j
].bitfield
.mem
1907 && !match_mem_size (t
, j
? 0 : 1))
1915 operand_type_match (i386_operand_type overlap
,
1916 i386_operand_type given
)
1918 i386_operand_type temp
= overlap
;
1920 temp
.bitfield
.jumpabsolute
= 0;
1921 temp
.bitfield
.unspecified
= 0;
1922 temp
.bitfield
.byte
= 0;
1923 temp
.bitfield
.word
= 0;
1924 temp
.bitfield
.dword
= 0;
1925 temp
.bitfield
.fword
= 0;
1926 temp
.bitfield
.qword
= 0;
1927 temp
.bitfield
.tbyte
= 0;
1928 temp
.bitfield
.xmmword
= 0;
1929 temp
.bitfield
.ymmword
= 0;
1930 temp
.bitfield
.zmmword
= 0;
1931 if (operand_type_all_zero (&temp
))
1934 if (given
.bitfield
.baseindex
== overlap
.bitfield
.baseindex
1935 && given
.bitfield
.jumpabsolute
== overlap
.bitfield
.jumpabsolute
)
1939 i
.error
= operand_type_mismatch
;
1943 /* If given types g0 and g1 are registers they must be of the same type
1944 unless the expected operand type register overlap is null.
1945 Note that Acc in a template matches every size of reg. */
1948 operand_type_register_match (i386_operand_type m0
,
1949 i386_operand_type g0
,
1950 i386_operand_type t0
,
1951 i386_operand_type m1
,
1952 i386_operand_type g1
,
1953 i386_operand_type t1
)
1955 if (!operand_type_check (g0
, reg
))
1958 if (!operand_type_check (g1
, reg
))
1961 if (g0
.bitfield
.reg8
== g1
.bitfield
.reg8
1962 && g0
.bitfield
.reg16
== g1
.bitfield
.reg16
1963 && g0
.bitfield
.reg32
== g1
.bitfield
.reg32
1964 && g0
.bitfield
.reg64
== g1
.bitfield
.reg64
)
1967 if (m0
.bitfield
.acc
)
1969 t0
.bitfield
.reg8
= 1;
1970 t0
.bitfield
.reg16
= 1;
1971 t0
.bitfield
.reg32
= 1;
1972 t0
.bitfield
.reg64
= 1;
1975 if (m1
.bitfield
.acc
)
1977 t1
.bitfield
.reg8
= 1;
1978 t1
.bitfield
.reg16
= 1;
1979 t1
.bitfield
.reg32
= 1;
1980 t1
.bitfield
.reg64
= 1;
1983 if (!(t0
.bitfield
.reg8
& t1
.bitfield
.reg8
)
1984 && !(t0
.bitfield
.reg16
& t1
.bitfield
.reg16
)
1985 && !(t0
.bitfield
.reg32
& t1
.bitfield
.reg32
)
1986 && !(t0
.bitfield
.reg64
& t1
.bitfield
.reg64
))
1989 i
.error
= register_type_mismatch
;
1994 static INLINE
unsigned int
1995 register_number (const reg_entry
*r
)
1997 unsigned int nr
= r
->reg_num
;
1999 if (r
->reg_flags
& RegRex
)
2002 if (r
->reg_flags
& RegVRex
)
2008 static INLINE
unsigned int
2009 mode_from_disp_size (i386_operand_type t
)
2011 if (t
.bitfield
.disp8
|| t
.bitfield
.vec_disp8
)
2013 else if (t
.bitfield
.disp16
2014 || t
.bitfield
.disp32
2015 || t
.bitfield
.disp32s
)
2022 fits_in_signed_byte (addressT num
)
2024 return num
+ 0x80 <= 0xff;
2028 fits_in_unsigned_byte (addressT num
)
2034 fits_in_unsigned_word (addressT num
)
2036 return num
<= 0xffff;
2040 fits_in_signed_word (addressT num
)
2042 return num
+ 0x8000 <= 0xffff;
2046 fits_in_signed_long (addressT num ATTRIBUTE_UNUSED
)
2051 return num
+ 0x80000000 <= 0xffffffff;
2053 } /* fits_in_signed_long() */
2056 fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED
)
2061 return num
<= 0xffffffff;
2063 } /* fits_in_unsigned_long() */
2066 fits_in_vec_disp8 (offsetT num
)
2068 int shift
= i
.memshift
;
2074 mask
= (1 << shift
) - 1;
2076 /* Return 0 if NUM isn't properly aligned. */
2080 /* Check if NUM will fit in 8bit after shift. */
2081 return fits_in_signed_byte (num
>> shift
);
2085 fits_in_imm4 (offsetT num
)
2087 return (num
& 0xf) == num
;
2090 static i386_operand_type
2091 smallest_imm_type (offsetT num
)
2093 i386_operand_type t
;
2095 operand_type_set (&t
, 0);
2096 t
.bitfield
.imm64
= 1;
2098 if (cpu_arch_tune
!= PROCESSOR_I486
&& num
== 1)
2100 /* This code is disabled on the 486 because all the Imm1 forms
2101 in the opcode table are slower on the i486. They're the
2102 versions with the implicitly specified single-position
2103 displacement, which has another syntax if you really want to
2105 t
.bitfield
.imm1
= 1;
2106 t
.bitfield
.imm8
= 1;
2107 t
.bitfield
.imm8s
= 1;
2108 t
.bitfield
.imm16
= 1;
2109 t
.bitfield
.imm32
= 1;
2110 t
.bitfield
.imm32s
= 1;
2112 else if (fits_in_signed_byte (num
))
2114 t
.bitfield
.imm8
= 1;
2115 t
.bitfield
.imm8s
= 1;
2116 t
.bitfield
.imm16
= 1;
2117 t
.bitfield
.imm32
= 1;
2118 t
.bitfield
.imm32s
= 1;
2120 else if (fits_in_unsigned_byte (num
))
2122 t
.bitfield
.imm8
= 1;
2123 t
.bitfield
.imm16
= 1;
2124 t
.bitfield
.imm32
= 1;
2125 t
.bitfield
.imm32s
= 1;
2127 else if (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
2129 t
.bitfield
.imm16
= 1;
2130 t
.bitfield
.imm32
= 1;
2131 t
.bitfield
.imm32s
= 1;
2133 else if (fits_in_signed_long (num
))
2135 t
.bitfield
.imm32
= 1;
2136 t
.bitfield
.imm32s
= 1;
2138 else if (fits_in_unsigned_long (num
))
2139 t
.bitfield
.imm32
= 1;
2145 offset_in_range (offsetT val
, int size
)
2151 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
2152 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
2153 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
2155 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
2161 /* If BFD64, sign extend val for 32bit address mode. */
2162 if (flag_code
!= CODE_64BIT
2163 || i
.prefix
[ADDR_PREFIX
])
2164 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
2165 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
2168 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
2170 char buf1
[40], buf2
[40];
2172 sprint_value (buf1
, val
);
2173 sprint_value (buf2
, val
& mask
);
2174 as_warn (_("%s shortened to %s"), buf1
, buf2
);
2189 a. PREFIX_EXIST if attempting to add a prefix where one from the
2190 same class already exists.
2191 b. PREFIX_LOCK if lock prefix is added.
2192 c. PREFIX_REP if rep/repne prefix is added.
2193 d. PREFIX_DS if ds prefix is added.
2194 e. PREFIX_OTHER if other prefix is added.
2197 static enum PREFIX_GROUP
2198 add_prefix (unsigned int prefix
)
2200 enum PREFIX_GROUP ret
= PREFIX_OTHER
;
2203 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
2204 && flag_code
== CODE_64BIT
)
2206 if ((i
.prefix
[REX_PREFIX
] & prefix
& REX_W
)
2207 || ((i
.prefix
[REX_PREFIX
] & (REX_R
| REX_X
| REX_B
))
2208 && (prefix
& (REX_R
| REX_X
| REX_B
))))
2219 case DS_PREFIX_OPCODE
:
2222 case CS_PREFIX_OPCODE
:
2223 case ES_PREFIX_OPCODE
:
2224 case FS_PREFIX_OPCODE
:
2225 case GS_PREFIX_OPCODE
:
2226 case SS_PREFIX_OPCODE
:
2230 case REPNE_PREFIX_OPCODE
:
2231 case REPE_PREFIX_OPCODE
:
2236 case LOCK_PREFIX_OPCODE
:
2245 case ADDR_PREFIX_OPCODE
:
2249 case DATA_PREFIX_OPCODE
:
2253 if (i
.prefix
[q
] != 0)
2261 i
.prefix
[q
] |= prefix
;
2264 as_bad (_("same type of prefix used twice"));
2270 update_code_flag (int value
, int check
)
2272 PRINTF_LIKE ((*as_error
));
2274 flag_code
= (enum flag_code
) value
;
2275 if (flag_code
== CODE_64BIT
)
2277 cpu_arch_flags
.bitfield
.cpu64
= 1;
2278 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2282 cpu_arch_flags
.bitfield
.cpu64
= 0;
2283 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2285 if (value
== CODE_64BIT
&& !cpu_arch_flags
.bitfield
.cpulm
)
2288 as_error
= as_fatal
;
2291 (*as_error
) (_("64bit mode not supported on `%s'."),
2292 cpu_arch_name
? cpu_arch_name
: default_arch
);
2294 if (value
== CODE_32BIT
&& !cpu_arch_flags
.bitfield
.cpui386
)
2297 as_error
= as_fatal
;
2300 (*as_error
) (_("32bit mode not supported on `%s'."),
2301 cpu_arch_name
? cpu_arch_name
: default_arch
);
2303 stackop_size
= '\0';
2307 set_code_flag (int value
)
2309 update_code_flag (value
, 0);
2313 set_16bit_gcc_code_flag (int new_code_flag
)
2315 flag_code
= (enum flag_code
) new_code_flag
;
2316 if (flag_code
!= CODE_16BIT
)
2318 cpu_arch_flags
.bitfield
.cpu64
= 0;
2319 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2320 stackop_size
= LONG_MNEM_SUFFIX
;
2324 set_intel_syntax (int syntax_flag
)
2326 /* Find out if register prefixing is specified. */
2327 int ask_naked_reg
= 0;
2330 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2333 int e
= get_symbol_name (&string
);
2335 if (strcmp (string
, "prefix") == 0)
2337 else if (strcmp (string
, "noprefix") == 0)
2340 as_bad (_("bad argument to syntax directive."));
2341 (void) restore_line_pointer (e
);
2343 demand_empty_rest_of_line ();
2345 intel_syntax
= syntax_flag
;
2347 if (ask_naked_reg
== 0)
2348 allow_naked_reg
= (intel_syntax
2349 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
2351 allow_naked_reg
= (ask_naked_reg
< 0);
2353 expr_set_rank (O_full_ptr
, syntax_flag
? 10 : 0);
2355 identifier_chars
['%'] = intel_syntax
&& allow_naked_reg
? '%' : 0;
2356 identifier_chars
['$'] = intel_syntax
? '$' : 0;
2357 register_prefix
= allow_naked_reg
? "" : "%";
2361 set_intel_mnemonic (int mnemonic_flag
)
2363 intel_mnemonic
= mnemonic_flag
;
2367 set_allow_index_reg (int flag
)
2369 allow_index_reg
= flag
;
2373 set_check (int what
)
2375 enum check_kind
*kind
;
2380 kind
= &operand_check
;
2391 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2394 int e
= get_symbol_name (&string
);
2396 if (strcmp (string
, "none") == 0)
2398 else if (strcmp (string
, "warning") == 0)
2399 *kind
= check_warning
;
2400 else if (strcmp (string
, "error") == 0)
2401 *kind
= check_error
;
2403 as_bad (_("bad argument to %s_check directive."), str
);
2404 (void) restore_line_pointer (e
);
2407 as_bad (_("missing argument for %s_check directive"), str
);
2409 demand_empty_rest_of_line ();
2413 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED
,
2414 i386_cpu_flags new_flag ATTRIBUTE_UNUSED
)
2416 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2417 static const char *arch
;
2419 /* Intel LIOM is only supported on ELF. */
2425 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2426 use default_arch. */
2427 arch
= cpu_arch_name
;
2429 arch
= default_arch
;
2432 /* If we are targeting Intel MCU, we must enable it. */
2433 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_IAMCU
2434 || new_flag
.bitfield
.cpuiamcu
)
2437 /* If we are targeting Intel L1OM, we must enable it. */
2438 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_L1OM
2439 || new_flag
.bitfield
.cpul1om
)
2442 /* If we are targeting Intel K1OM, we must enable it. */
2443 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_K1OM
2444 || new_flag
.bitfield
.cpuk1om
)
2447 as_bad (_("`%s' is not supported on `%s'"), name
, arch
);
2452 set_cpu_arch (int dummy ATTRIBUTE_UNUSED
)
2456 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2459 int e
= get_symbol_name (&string
);
2461 i386_cpu_flags flags
;
2463 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
2465 if (strcmp (string
, cpu_arch
[j
].name
) == 0)
2467 check_cpu_arch_compatible (string
, cpu_arch
[j
].flags
);
2471 cpu_arch_name
= cpu_arch
[j
].name
;
2472 cpu_sub_arch_name
= NULL
;
2473 cpu_arch_flags
= cpu_arch
[j
].flags
;
2474 if (flag_code
== CODE_64BIT
)
2476 cpu_arch_flags
.bitfield
.cpu64
= 1;
2477 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2481 cpu_arch_flags
.bitfield
.cpu64
= 0;
2482 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2484 cpu_arch_isa
= cpu_arch
[j
].type
;
2485 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
2486 if (!cpu_arch_tune_set
)
2488 cpu_arch_tune
= cpu_arch_isa
;
2489 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
2494 flags
= cpu_flags_or (cpu_arch_flags
,
2497 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2499 if (cpu_sub_arch_name
)
2501 char *name
= cpu_sub_arch_name
;
2502 cpu_sub_arch_name
= concat (name
,
2504 (const char *) NULL
);
2508 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
2509 cpu_arch_flags
= flags
;
2510 cpu_arch_isa_flags
= flags
;
2512 (void) restore_line_pointer (e
);
2513 demand_empty_rest_of_line ();
2518 if (*string
== '.' && j
>= ARRAY_SIZE (cpu_arch
))
2520 /* Disable an ISA extension. */
2521 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
2522 if (strcmp (string
+ 1, cpu_noarch
[j
].name
) == 0)
2524 flags
= cpu_flags_and_not (cpu_arch_flags
,
2525 cpu_noarch
[j
].flags
);
2526 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2528 if (cpu_sub_arch_name
)
2530 char *name
= cpu_sub_arch_name
;
2531 cpu_sub_arch_name
= concat (name
, string
,
2532 (const char *) NULL
);
2536 cpu_sub_arch_name
= xstrdup (string
);
2537 cpu_arch_flags
= flags
;
2538 cpu_arch_isa_flags
= flags
;
2540 (void) restore_line_pointer (e
);
2541 demand_empty_rest_of_line ();
2545 j
= ARRAY_SIZE (cpu_arch
);
2548 if (j
>= ARRAY_SIZE (cpu_arch
))
2549 as_bad (_("no such architecture: `%s'"), string
);
2551 *input_line_pointer
= e
;
2554 as_bad (_("missing cpu architecture"));
2556 no_cond_jump_promotion
= 0;
2557 if (*input_line_pointer
== ','
2558 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
2563 ++input_line_pointer
;
2564 e
= get_symbol_name (&string
);
2566 if (strcmp (string
, "nojumps") == 0)
2567 no_cond_jump_promotion
= 1;
2568 else if (strcmp (string
, "jumps") == 0)
2571 as_bad (_("no such architecture modifier: `%s'"), string
);
2573 (void) restore_line_pointer (e
);
2576 demand_empty_rest_of_line ();
2579 enum bfd_architecture
2582 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2584 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2585 || flag_code
!= CODE_64BIT
)
2586 as_fatal (_("Intel L1OM is 64bit ELF only"));
2587 return bfd_arch_l1om
;
2589 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2591 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2592 || flag_code
!= CODE_64BIT
)
2593 as_fatal (_("Intel K1OM is 64bit ELF only"));
2594 return bfd_arch_k1om
;
2596 else if (cpu_arch_isa
== PROCESSOR_IAMCU
)
2598 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2599 || flag_code
== CODE_64BIT
)
2600 as_fatal (_("Intel MCU is 32bit ELF only"));
2601 return bfd_arch_iamcu
;
2604 return bfd_arch_i386
;
2610 if (!strncmp (default_arch
, "x86_64", 6))
2612 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2614 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2615 || default_arch
[6] != '\0')
2616 as_fatal (_("Intel L1OM is 64bit ELF only"));
2617 return bfd_mach_l1om
;
2619 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2621 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2622 || default_arch
[6] != '\0')
2623 as_fatal (_("Intel K1OM is 64bit ELF only"));
2624 return bfd_mach_k1om
;
2626 else if (default_arch
[6] == '\0')
2627 return bfd_mach_x86_64
;
2629 return bfd_mach_x64_32
;
2631 else if (!strcmp (default_arch
, "i386")
2632 || !strcmp (default_arch
, "iamcu"))
2634 if (cpu_arch_isa
== PROCESSOR_IAMCU
)
2636 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
2637 as_fatal (_("Intel MCU is 32bit ELF only"));
2638 return bfd_mach_i386_iamcu
;
2641 return bfd_mach_i386_i386
;
2644 as_fatal (_("unknown architecture"));
2650 const char *hash_err
;
2652 /* Support pseudo prefixes like {disp32}. */
2653 lex_type
['{'] = LEX_BEGIN_NAME
;
2655 /* Initialize op_hash hash table. */
2656 op_hash
= hash_new ();
2659 const insn_template
*optab
;
2660 templates
*core_optab
;
2662 /* Setup for loop. */
2664 core_optab
= XNEW (templates
);
2665 core_optab
->start
= optab
;
2670 if (optab
->name
== NULL
2671 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
2673 /* different name --> ship out current template list;
2674 add to hash table; & begin anew. */
2675 core_optab
->end
= optab
;
2676 hash_err
= hash_insert (op_hash
,
2678 (void *) core_optab
);
2681 as_fatal (_("can't hash %s: %s"),
2685 if (optab
->name
== NULL
)
2687 core_optab
= XNEW (templates
);
2688 core_optab
->start
= optab
;
2693 /* Initialize reg_hash hash table. */
2694 reg_hash
= hash_new ();
2696 const reg_entry
*regtab
;
2697 unsigned int regtab_size
= i386_regtab_size
;
2699 for (regtab
= i386_regtab
; regtab_size
--; regtab
++)
2701 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (void *) regtab
);
2703 as_fatal (_("can't hash %s: %s"),
2709 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
2714 for (c
= 0; c
< 256; c
++)
2719 mnemonic_chars
[c
] = c
;
2720 register_chars
[c
] = c
;
2721 operand_chars
[c
] = c
;
2723 else if (ISLOWER (c
))
2725 mnemonic_chars
[c
] = c
;
2726 register_chars
[c
] = c
;
2727 operand_chars
[c
] = c
;
2729 else if (ISUPPER (c
))
2731 mnemonic_chars
[c
] = TOLOWER (c
);
2732 register_chars
[c
] = mnemonic_chars
[c
];
2733 operand_chars
[c
] = c
;
2735 else if (c
== '{' || c
== '}')
2737 mnemonic_chars
[c
] = c
;
2738 operand_chars
[c
] = c
;
2741 if (ISALPHA (c
) || ISDIGIT (c
))
2742 identifier_chars
[c
] = c
;
2745 identifier_chars
[c
] = c
;
2746 operand_chars
[c
] = c
;
2751 identifier_chars
['@'] = '@';
2754 identifier_chars
['?'] = '?';
2755 operand_chars
['?'] = '?';
2757 digit_chars
['-'] = '-';
2758 mnemonic_chars
['_'] = '_';
2759 mnemonic_chars
['-'] = '-';
2760 mnemonic_chars
['.'] = '.';
2761 identifier_chars
['_'] = '_';
2762 identifier_chars
['.'] = '.';
2764 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
2765 operand_chars
[(unsigned char) *p
] = *p
;
2768 if (flag_code
== CODE_64BIT
)
2770 #if defined (OBJ_COFF) && defined (TE_PE)
2771 x86_dwarf2_return_column
= (OUTPUT_FLAVOR
== bfd_target_coff_flavour
2774 x86_dwarf2_return_column
= 16;
2776 x86_cie_data_alignment
= -8;
2780 x86_dwarf2_return_column
= 8;
2781 x86_cie_data_alignment
= -4;
2786 i386_print_statistics (FILE *file
)
2788 hash_print_statistics (file
, "i386 opcode", op_hash
);
2789 hash_print_statistics (file
, "i386 register", reg_hash
);
2794 /* Debugging routines for md_assemble. */
2795 static void pte (insn_template
*);
2796 static void pt (i386_operand_type
);
2797 static void pe (expressionS
*);
2798 static void ps (symbolS
*);
2801 pi (char *line
, i386_insn
*x
)
2805 fprintf (stdout
, "%s: template ", line
);
2807 fprintf (stdout
, " address: base %s index %s scale %x\n",
2808 x
->base_reg
? x
->base_reg
->reg_name
: "none",
2809 x
->index_reg
? x
->index_reg
->reg_name
: "none",
2810 x
->log2_scale_factor
);
2811 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
2812 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
2813 fprintf (stdout
, " sib: base %x index %x scale %x\n",
2814 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
2815 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
2816 (x
->rex
& REX_W
) != 0,
2817 (x
->rex
& REX_R
) != 0,
2818 (x
->rex
& REX_X
) != 0,
2819 (x
->rex
& REX_B
) != 0);
2820 for (j
= 0; j
< x
->operands
; j
++)
2822 fprintf (stdout
, " #%d: ", j
+ 1);
2824 fprintf (stdout
, "\n");
2825 if (x
->types
[j
].bitfield
.reg8
2826 || x
->types
[j
].bitfield
.reg16
2827 || x
->types
[j
].bitfield
.reg32
2828 || x
->types
[j
].bitfield
.reg64
2829 || x
->types
[j
].bitfield
.regmmx
2830 || x
->types
[j
].bitfield
.regxmm
2831 || x
->types
[j
].bitfield
.regymm
2832 || x
->types
[j
].bitfield
.regzmm
2833 || x
->types
[j
].bitfield
.sreg2
2834 || x
->types
[j
].bitfield
.sreg3
2835 || x
->types
[j
].bitfield
.control
2836 || x
->types
[j
].bitfield
.debug
2837 || x
->types
[j
].bitfield
.test
)
2838 fprintf (stdout
, "%s\n", x
->op
[j
].regs
->reg_name
);
2839 if (operand_type_check (x
->types
[j
], imm
))
2841 if (operand_type_check (x
->types
[j
], disp
))
2842 pe (x
->op
[j
].disps
);
2847 pte (insn_template
*t
)
2850 fprintf (stdout
, " %d operands ", t
->operands
);
2851 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
2852 if (t
->extension_opcode
!= None
)
2853 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
2854 if (t
->opcode_modifier
.d
)
2855 fprintf (stdout
, "D");
2856 if (t
->opcode_modifier
.w
)
2857 fprintf (stdout
, "W");
2858 fprintf (stdout
, "\n");
2859 for (j
= 0; j
< t
->operands
; j
++)
2861 fprintf (stdout
, " #%d type ", j
+ 1);
2862 pt (t
->operand_types
[j
]);
2863 fprintf (stdout
, "\n");
2870 fprintf (stdout
, " operation %d\n", e
->X_op
);
2871 fprintf (stdout
, " add_number %ld (%lx)\n",
2872 (long) e
->X_add_number
, (long) e
->X_add_number
);
2873 if (e
->X_add_symbol
)
2875 fprintf (stdout
, " add_symbol ");
2876 ps (e
->X_add_symbol
);
2877 fprintf (stdout
, "\n");
2881 fprintf (stdout
, " op_symbol ");
2882 ps (e
->X_op_symbol
);
2883 fprintf (stdout
, "\n");
2890 fprintf (stdout
, "%s type %s%s",
2892 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
2893 segment_name (S_GET_SEGMENT (s
)));
2896 static struct type_name
2898 i386_operand_type mask
;
2901 const type_names
[] =
2903 { OPERAND_TYPE_REG8
, "r8" },
2904 { OPERAND_TYPE_REG16
, "r16" },
2905 { OPERAND_TYPE_REG32
, "r32" },
2906 { OPERAND_TYPE_REG64
, "r64" },
2907 { OPERAND_TYPE_IMM8
, "i8" },
2908 { OPERAND_TYPE_IMM8
, "i8s" },
2909 { OPERAND_TYPE_IMM16
, "i16" },
2910 { OPERAND_TYPE_IMM32
, "i32" },
2911 { OPERAND_TYPE_IMM32S
, "i32s" },
2912 { OPERAND_TYPE_IMM64
, "i64" },
2913 { OPERAND_TYPE_IMM1
, "i1" },
2914 { OPERAND_TYPE_BASEINDEX
, "BaseIndex" },
2915 { OPERAND_TYPE_DISP8
, "d8" },
2916 { OPERAND_TYPE_DISP16
, "d16" },
2917 { OPERAND_TYPE_DISP32
, "d32" },
2918 { OPERAND_TYPE_DISP32S
, "d32s" },
2919 { OPERAND_TYPE_DISP64
, "d64" },
2920 { OPERAND_TYPE_VEC_DISP8
, "Vector d8" },
2921 { OPERAND_TYPE_INOUTPORTREG
, "InOutPortReg" },
2922 { OPERAND_TYPE_SHIFTCOUNT
, "ShiftCount" },
2923 { OPERAND_TYPE_CONTROL
, "control reg" },
2924 { OPERAND_TYPE_TEST
, "test reg" },
2925 { OPERAND_TYPE_DEBUG
, "debug reg" },
2926 { OPERAND_TYPE_FLOATREG
, "FReg" },
2927 { OPERAND_TYPE_FLOATACC
, "FAcc" },
2928 { OPERAND_TYPE_SREG2
, "SReg2" },
2929 { OPERAND_TYPE_SREG3
, "SReg3" },
2930 { OPERAND_TYPE_ACC
, "Acc" },
2931 { OPERAND_TYPE_JUMPABSOLUTE
, "Jump Absolute" },
2932 { OPERAND_TYPE_REGMMX
, "rMMX" },
2933 { OPERAND_TYPE_REGXMM
, "rXMM" },
2934 { OPERAND_TYPE_REGYMM
, "rYMM" },
2935 { OPERAND_TYPE_REGZMM
, "rZMM" },
2936 { OPERAND_TYPE_REGMASK
, "Mask reg" },
2937 { OPERAND_TYPE_ESSEG
, "es" },
2941 pt (i386_operand_type t
)
2944 i386_operand_type a
;
2946 for (j
= 0; j
< ARRAY_SIZE (type_names
); j
++)
2948 a
= operand_type_and (t
, type_names
[j
].mask
);
2949 if (!operand_type_all_zero (&a
))
2950 fprintf (stdout
, "%s, ", type_names
[j
].name
);
2955 #endif /* DEBUG386 */
2957 static bfd_reloc_code_real_type
2958 reloc (unsigned int size
,
2961 bfd_reloc_code_real_type other
)
2963 if (other
!= NO_RELOC
)
2965 reloc_howto_type
*rel
;
2970 case BFD_RELOC_X86_64_GOT32
:
2971 return BFD_RELOC_X86_64_GOT64
;
2973 case BFD_RELOC_X86_64_GOTPLT64
:
2974 return BFD_RELOC_X86_64_GOTPLT64
;
2976 case BFD_RELOC_X86_64_PLTOFF64
:
2977 return BFD_RELOC_X86_64_PLTOFF64
;
2979 case BFD_RELOC_X86_64_GOTPC32
:
2980 other
= BFD_RELOC_X86_64_GOTPC64
;
2982 case BFD_RELOC_X86_64_GOTPCREL
:
2983 other
= BFD_RELOC_X86_64_GOTPCREL64
;
2985 case BFD_RELOC_X86_64_TPOFF32
:
2986 other
= BFD_RELOC_X86_64_TPOFF64
;
2988 case BFD_RELOC_X86_64_DTPOFF32
:
2989 other
= BFD_RELOC_X86_64_DTPOFF64
;
2995 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2996 if (other
== BFD_RELOC_SIZE32
)
2999 other
= BFD_RELOC_SIZE64
;
3002 as_bad (_("there are no pc-relative size relocations"));
3008 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
3009 if (size
== 4 && (flag_code
!= CODE_64BIT
|| disallow_64bit_reloc
))
3012 rel
= bfd_reloc_type_lookup (stdoutput
, other
);
3014 as_bad (_("unknown relocation (%u)"), other
);
3015 else if (size
!= bfd_get_reloc_size (rel
))
3016 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
3017 bfd_get_reloc_size (rel
),
3019 else if (pcrel
&& !rel
->pc_relative
)
3020 as_bad (_("non-pc-relative relocation for pc-relative field"));
3021 else if ((rel
->complain_on_overflow
== complain_overflow_signed
3023 || (rel
->complain_on_overflow
== complain_overflow_unsigned
3025 as_bad (_("relocated field and relocation type differ in signedness"));
3034 as_bad (_("there are no unsigned pc-relative relocations"));
3037 case 1: return BFD_RELOC_8_PCREL
;
3038 case 2: return BFD_RELOC_16_PCREL
;
3039 case 4: return BFD_RELOC_32_PCREL
;
3040 case 8: return BFD_RELOC_64_PCREL
;
3042 as_bad (_("cannot do %u byte pc-relative relocation"), size
);
3049 case 4: return BFD_RELOC_X86_64_32S
;
3054 case 1: return BFD_RELOC_8
;
3055 case 2: return BFD_RELOC_16
;
3056 case 4: return BFD_RELOC_32
;
3057 case 8: return BFD_RELOC_64
;
3059 as_bad (_("cannot do %s %u byte relocation"),
3060 sign
> 0 ? "signed" : "unsigned", size
);
3066 /* Here we decide which fixups can be adjusted to make them relative to
3067 the beginning of the section instead of the symbol. Basically we need
3068 to make sure that the dynamic relocations are done correctly, so in
3069 some cases we force the original symbol to be used. */
3072 tc_i386_fix_adjustable (fixS
*fixP ATTRIBUTE_UNUSED
)
3074 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3078 /* Don't adjust pc-relative references to merge sections in 64-bit
3080 if (use_rela_relocations
3081 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
3085 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
3086 and changed later by validate_fix. */
3087 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
3088 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
3091 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
3092 for size relocations. */
3093 if (fixP
->fx_r_type
== BFD_RELOC_SIZE32
3094 || fixP
->fx_r_type
== BFD_RELOC_SIZE64
3095 || fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
3096 || fixP
->fx_r_type
== BFD_RELOC_386_PLT32
3097 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
3098 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32X
3099 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
3100 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
3101 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
3102 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
3103 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
3104 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
3105 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
3106 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
3107 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTDESC
3108 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_DESC_CALL
3109 || fixP
->fx_r_type
== BFD_RELOC_X86_64_PLT32
3110 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
3111 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
3112 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCRELX
3113 || fixP
->fx_r_type
== BFD_RELOC_X86_64_REX_GOTPCRELX
3114 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
3115 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
3116 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
3117 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
3118 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
3119 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
3120 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
3121 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
3122 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPC32_TLSDESC
3123 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSDESC_CALL
3124 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
3125 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
3132 intel_float_operand (const char *mnemonic
)
3134 /* Note that the value returned is meaningful only for opcodes with (memory)
3135 operands, hence the code here is free to improperly handle opcodes that
3136 have no operands (for better performance and smaller code). */
3138 if (mnemonic
[0] != 'f')
3139 return 0; /* non-math */
3141 switch (mnemonic
[1])
3143 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
3144 the fs segment override prefix not currently handled because no
3145 call path can make opcodes without operands get here */
3147 return 2 /* integer op */;
3149 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
3150 return 3; /* fldcw/fldenv */
3153 if (mnemonic
[2] != 'o' /* fnop */)
3154 return 3; /* non-waiting control op */
3157 if (mnemonic
[2] == 's')
3158 return 3; /* frstor/frstpm */
3161 if (mnemonic
[2] == 'a')
3162 return 3; /* fsave */
3163 if (mnemonic
[2] == 't')
3165 switch (mnemonic
[3])
3167 case 'c': /* fstcw */
3168 case 'd': /* fstdw */
3169 case 'e': /* fstenv */
3170 case 's': /* fsts[gw] */
3176 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
3177 return 0; /* fxsave/fxrstor are not really math ops */
3184 /* Build the VEX prefix. */
3187 build_vex_prefix (const insn_template
*t
)
3189 unsigned int register_specifier
;
3190 unsigned int implied_prefix
;
3191 unsigned int vector_length
;
3193 /* Check register specifier. */
3194 if (i
.vex
.register_specifier
)
3196 register_specifier
=
3197 ~register_number (i
.vex
.register_specifier
) & 0xf;
3198 gas_assert ((i
.vex
.register_specifier
->reg_flags
& RegVRex
) == 0);
3201 register_specifier
= 0xf;
3203 /* Use 2-byte VEX prefix by swapping destination and source
3205 if (i
.vec_encoding
!= vex_encoding_vex3
3206 && i
.dir_encoding
== dir_encoding_default
3207 && i
.operands
== i
.reg_operands
3208 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3209 && i
.tm
.opcode_modifier
.load
3212 unsigned int xchg
= i
.operands
- 1;
3213 union i386_op temp_op
;
3214 i386_operand_type temp_type
;
3216 temp_type
= i
.types
[xchg
];
3217 i
.types
[xchg
] = i
.types
[0];
3218 i
.types
[0] = temp_type
;
3219 temp_op
= i
.op
[xchg
];
3220 i
.op
[xchg
] = i
.op
[0];
3223 gas_assert (i
.rm
.mode
== 3);
3227 i
.rm
.regmem
= i
.rm
.reg
;
3230 /* Use the next insn. */
3234 if (i
.tm
.opcode_modifier
.vex
== VEXScalar
)
3235 vector_length
= avxscalar
;
3237 vector_length
= i
.tm
.opcode_modifier
.vex
== VEX256
? 1 : 0;
3239 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3244 case DATA_PREFIX_OPCODE
:
3247 case REPE_PREFIX_OPCODE
:
3250 case REPNE_PREFIX_OPCODE
:
3257 /* Use 2-byte VEX prefix if possible. */
3258 if (i
.vec_encoding
!= vex_encoding_vex3
3259 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3260 && i
.tm
.opcode_modifier
.vexw
!= VEXW1
3261 && (i
.rex
& (REX_W
| REX_X
| REX_B
)) == 0)
3263 /* 2-byte VEX prefix. */
3267 i
.vex
.bytes
[0] = 0xc5;
3269 /* Check the REX.R bit. */
3270 r
= (i
.rex
& REX_R
) ? 0 : 1;
3271 i
.vex
.bytes
[1] = (r
<< 7
3272 | register_specifier
<< 3
3273 | vector_length
<< 2
3278 /* 3-byte VEX prefix. */
3283 switch (i
.tm
.opcode_modifier
.vexopcode
)
3287 i
.vex
.bytes
[0] = 0xc4;
3291 i
.vex
.bytes
[0] = 0xc4;
3295 i
.vex
.bytes
[0] = 0xc4;
3299 i
.vex
.bytes
[0] = 0x8f;
3303 i
.vex
.bytes
[0] = 0x8f;
3307 i
.vex
.bytes
[0] = 0x8f;
3313 /* The high 3 bits of the second VEX byte are 1's compliment
3314 of RXB bits from REX. */
3315 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3317 /* Check the REX.W bit. */
3318 w
= (i
.rex
& REX_W
) ? 1 : 0;
3319 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
3322 i
.vex
.bytes
[2] = (w
<< 7
3323 | register_specifier
<< 3
3324 | vector_length
<< 2
3329 /* Build the EVEX prefix. */
3332 build_evex_prefix (void)
3334 unsigned int register_specifier
;
3335 unsigned int implied_prefix
;
3337 rex_byte vrex_used
= 0;
3339 /* Check register specifier. */
3340 if (i
.vex
.register_specifier
)
3342 gas_assert ((i
.vrex
& REX_X
) == 0);
3344 register_specifier
= i
.vex
.register_specifier
->reg_num
;
3345 if ((i
.vex
.register_specifier
->reg_flags
& RegRex
))
3346 register_specifier
+= 8;
3347 /* The upper 16 registers are encoded in the fourth byte of the
3349 if (!(i
.vex
.register_specifier
->reg_flags
& RegVRex
))
3350 i
.vex
.bytes
[3] = 0x8;
3351 register_specifier
= ~register_specifier
& 0xf;
3355 register_specifier
= 0xf;
3357 /* Encode upper 16 vector index register in the fourth byte of
3359 if (!(i
.vrex
& REX_X
))
3360 i
.vex
.bytes
[3] = 0x8;
3365 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3370 case DATA_PREFIX_OPCODE
:
3373 case REPE_PREFIX_OPCODE
:
3376 case REPNE_PREFIX_OPCODE
:
3383 /* 4 byte EVEX prefix. */
3385 i
.vex
.bytes
[0] = 0x62;
3388 switch (i
.tm
.opcode_modifier
.vexopcode
)
3404 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3406 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3408 /* The fifth bit of the second EVEX byte is 1's compliment of the
3409 REX_R bit in VREX. */
3410 if (!(i
.vrex
& REX_R
))
3411 i
.vex
.bytes
[1] |= 0x10;
3415 if ((i
.reg_operands
+ i
.imm_operands
) == i
.operands
)
3417 /* When all operands are registers, the REX_X bit in REX is not
3418 used. We reuse it to encode the upper 16 registers, which is
3419 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3420 as 1's compliment. */
3421 if ((i
.vrex
& REX_B
))
3424 i
.vex
.bytes
[1] &= ~0x40;
3428 /* EVEX instructions shouldn't need the REX prefix. */
3429 i
.vrex
&= ~vrex_used
;
3430 gas_assert (i
.vrex
== 0);
3432 /* Check the REX.W bit. */
3433 w
= (i
.rex
& REX_W
) ? 1 : 0;
3434 if (i
.tm
.opcode_modifier
.vexw
)
3436 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
3439 /* If w is not set it means we are dealing with WIG instruction. */
3442 if (evexwig
== evexw1
)
3446 /* Encode the U bit. */
3447 implied_prefix
|= 0x4;
3449 /* The third byte of the EVEX prefix. */
3450 i
.vex
.bytes
[2] = (w
<< 7 | register_specifier
<< 3 | implied_prefix
);
3452 /* The fourth byte of the EVEX prefix. */
3453 /* The zeroing-masking bit. */
3454 if (i
.mask
&& i
.mask
->zeroing
)
3455 i
.vex
.bytes
[3] |= 0x80;
3457 /* Don't always set the broadcast bit if there is no RC. */
3460 /* Encode the vector length. */
3461 unsigned int vec_length
;
3463 switch (i
.tm
.opcode_modifier
.evex
)
3465 case EVEXLIG
: /* LL' is ignored */
3466 vec_length
= evexlig
<< 5;
3469 vec_length
= 0 << 5;
3472 vec_length
= 1 << 5;
3475 vec_length
= 2 << 5;
3481 i
.vex
.bytes
[3] |= vec_length
;
3482 /* Encode the broadcast bit. */
3484 i
.vex
.bytes
[3] |= 0x10;
3488 if (i
.rounding
->type
!= saeonly
)
3489 i
.vex
.bytes
[3] |= 0x10 | (i
.rounding
->type
<< 5);
3491 i
.vex
.bytes
[3] |= 0x10 | (evexrcig
<< 5);
3494 if (i
.mask
&& i
.mask
->mask
)
3495 i
.vex
.bytes
[3] |= i
.mask
->mask
->reg_num
;
3499 process_immext (void)
3503 if ((i
.tm
.cpu_flags
.bitfield
.cpusse3
|| i
.tm
.cpu_flags
.bitfield
.cpusvme
)
3506 /* MONITOR/MWAIT as well as SVME instructions have fixed operands
3507 with an opcode suffix which is coded in the same place as an
3508 8-bit immediate field would be.
3509 Here we check those operands and remove them afterwards. */
3512 for (x
= 0; x
< i
.operands
; x
++)
3513 if (register_number (i
.op
[x
].regs
) != x
)
3514 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3515 register_prefix
, i
.op
[x
].regs
->reg_name
, x
+ 1,
3521 if (i
.tm
.cpu_flags
.bitfield
.cpumwaitx
&& i
.operands
> 0)
3523 /* MONITORX/MWAITX instructions have fixed operands with an opcode
3524 suffix which is coded in the same place as an 8-bit immediate
3526 Here we check those operands and remove them afterwards. */
3529 if (i
.operands
!= 3)
3532 for (x
= 0; x
< 2; x
++)
3533 if (register_number (i
.op
[x
].regs
) != x
)
3534 goto bad_register_operand
;
3536 /* Check for third operand for mwaitx/monitorx insn. */
3537 if (register_number (i
.op
[x
].regs
)
3538 != (x
+ (i
.tm
.extension_opcode
== 0xfb)))
3540 bad_register_operand
:
3541 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3542 register_prefix
, i
.op
[x
].regs
->reg_name
, x
+1,
3549 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
3550 which is coded in the same place as an 8-bit immediate field
3551 would be. Here we fake an 8-bit immediate operand from the
3552 opcode suffix stored in tm.extension_opcode.
3554 AVX instructions also use this encoding, for some of
3555 3 argument instructions. */
3557 gas_assert (i
.imm_operands
<= 1
3559 || ((i
.tm
.opcode_modifier
.vex
3560 || i
.tm
.opcode_modifier
.evex
)
3561 && i
.operands
<= 4)));
3563 exp
= &im_expressions
[i
.imm_operands
++];
3564 i
.op
[i
.operands
].imms
= exp
;
3565 i
.types
[i
.operands
] = imm8
;
3567 exp
->X_op
= O_constant
;
3568 exp
->X_add_number
= i
.tm
.extension_opcode
;
3569 i
.tm
.extension_opcode
= None
;
3576 switch (i
.tm
.opcode_modifier
.hleprefixok
)
3581 as_bad (_("invalid instruction `%s' after `%s'"),
3582 i
.tm
.name
, i
.hle_prefix
);
3585 if (i
.prefix
[LOCK_PREFIX
])
3587 as_bad (_("missing `lock' with `%s'"), i
.hle_prefix
);
3591 case HLEPrefixRelease
:
3592 if (i
.prefix
[HLE_PREFIX
] != XRELEASE_PREFIX_OPCODE
)
3594 as_bad (_("instruction `%s' after `xacquire' not allowed"),
3598 if (i
.mem_operands
== 0
3599 || !operand_type_check (i
.types
[i
.operands
- 1], anymem
))
3601 as_bad (_("memory destination needed for instruction `%s'"
3602 " after `xrelease'"), i
.tm
.name
);
3609 /* This is the guts of the machine-dependent assembler. LINE points to a
3610 machine dependent instruction. This function is supposed to emit
3611 the frags/bytes it assembles to. */
3614 md_assemble (char *line
)
3617 char mnemonic
[MAX_MNEM_SIZE
], mnem_suffix
;
3618 const insn_template
*t
;
3620 /* Initialize globals. */
3621 memset (&i
, '\0', sizeof (i
));
3622 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3623 i
.reloc
[j
] = NO_RELOC
;
3624 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
3625 memset (im_expressions
, '\0', sizeof (im_expressions
));
3626 save_stack_p
= save_stack
;
3628 /* First parse an instruction mnemonic & call i386_operand for the operands.
3629 We assume that the scrubber has arranged it so that line[0] is the valid
3630 start of a (possibly prefixed) mnemonic. */
3632 line
= parse_insn (line
, mnemonic
);
3635 mnem_suffix
= i
.suffix
;
3637 line
= parse_operands (line
, mnemonic
);
3639 xfree (i
.memop1_string
);
3640 i
.memop1_string
= NULL
;
3644 /* Now we've parsed the mnemonic into a set of templates, and have the
3645 operands at hand. */
3647 /* All intel opcodes have reversed operands except for "bound" and
3648 "enter". We also don't reverse intersegment "jmp" and "call"
3649 instructions with 2 immediate operands so that the immediate segment
3650 precedes the offset, as it does when in AT&T mode. */
3653 && (strcmp (mnemonic
, "bound") != 0)
3654 && (strcmp (mnemonic
, "invlpga") != 0)
3655 && !(operand_type_check (i
.types
[0], imm
)
3656 && operand_type_check (i
.types
[1], imm
)))
3659 /* The order of the immediates should be reversed
3660 for 2 immediates extrq and insertq instructions */
3661 if (i
.imm_operands
== 2
3662 && (strcmp (mnemonic
, "extrq") == 0
3663 || strcmp (mnemonic
, "insertq") == 0))
3664 swap_2_operands (0, 1);
3669 /* Don't optimize displacement for movabs since it only takes 64bit
3672 && i
.disp_encoding
!= disp_encoding_32bit
3673 && (flag_code
!= CODE_64BIT
3674 || strcmp (mnemonic
, "movabs") != 0))
3677 /* Next, we find a template that matches the given insn,
3678 making sure the overlap of the given operands types is consistent
3679 with the template operand types. */
3681 if (!(t
= match_template (mnem_suffix
)))
3684 if (sse_check
!= check_none
3685 && !i
.tm
.opcode_modifier
.noavx
3686 && (i
.tm
.cpu_flags
.bitfield
.cpusse
3687 || i
.tm
.cpu_flags
.bitfield
.cpusse2
3688 || i
.tm
.cpu_flags
.bitfield
.cpusse3
3689 || i
.tm
.cpu_flags
.bitfield
.cpussse3
3690 || i
.tm
.cpu_flags
.bitfield
.cpusse4_1
3691 || i
.tm
.cpu_flags
.bitfield
.cpusse4_2
))
3693 (sse_check
== check_warning
3695 : as_bad
) (_("SSE instruction `%s' is used"), i
.tm
.name
);
3698 /* Zap movzx and movsx suffix. The suffix has been set from
3699 "word ptr" or "byte ptr" on the source operand in Intel syntax
3700 or extracted from mnemonic in AT&T syntax. But we'll use
3701 the destination register to choose the suffix for encoding. */
3702 if ((i
.tm
.base_opcode
& ~9) == 0x0fb6)
3704 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
3705 there is no suffix, the default will be byte extension. */
3706 if (i
.reg_operands
!= 2
3709 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
3714 if (i
.tm
.opcode_modifier
.fwait
)
3715 if (!add_prefix (FWAIT_OPCODE
))
3718 /* Check if REP prefix is OK. */
3719 if (i
.rep_prefix
&& !i
.tm
.opcode_modifier
.repprefixok
)
3721 as_bad (_("invalid instruction `%s' after `%s'"),
3722 i
.tm
.name
, i
.rep_prefix
);
3726 /* Check for lock without a lockable instruction. Destination operand
3727 must be memory unless it is xchg (0x86). */
3728 if (i
.prefix
[LOCK_PREFIX
]
3729 && (!i
.tm
.opcode_modifier
.islockable
3730 || i
.mem_operands
== 0
3731 || (i
.tm
.base_opcode
!= 0x86
3732 && !operand_type_check (i
.types
[i
.operands
- 1], anymem
))))
3734 as_bad (_("expecting lockable instruction after `lock'"));
3738 /* Check if HLE prefix is OK. */
3739 if (i
.hle_prefix
&& !check_hle ())
3742 /* Check BND prefix. */
3743 if (i
.bnd_prefix
&& !i
.tm
.opcode_modifier
.bndprefixok
)
3744 as_bad (_("expecting valid branch instruction after `bnd'"));
3746 /* Check NOTRACK prefix. */
3747 if (i
.notrack_prefix
&& !i
.tm
.opcode_modifier
.notrackprefixok
)
3748 as_bad (_("expecting indirect branch instruction after `notrack'"));
3750 if (i
.tm
.cpu_flags
.bitfield
.cpumpx
)
3752 if (flag_code
== CODE_64BIT
&& i
.prefix
[ADDR_PREFIX
])
3753 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
3754 else if (flag_code
!= CODE_16BIT
3755 ? i
.prefix
[ADDR_PREFIX
]
3756 : i
.mem_operands
&& !i
.prefix
[ADDR_PREFIX
])
3757 as_bad (_("16-bit address isn't allowed in MPX instructions"));
3760 /* Insert BND prefix. */
3762 && i
.tm
.opcode_modifier
.bndprefixok
3763 && !i
.prefix
[BND_PREFIX
])
3764 add_prefix (BND_PREFIX_OPCODE
);
3766 /* Check string instruction segment overrides. */
3767 if (i
.tm
.opcode_modifier
.isstring
&& i
.mem_operands
!= 0)
3769 if (!check_string ())
3771 i
.disp_operands
= 0;
3774 if (!process_suffix ())
3777 /* Update operand types. */
3778 for (j
= 0; j
< i
.operands
; j
++)
3779 i
.types
[j
] = operand_type_and (i
.types
[j
], i
.tm
.operand_types
[j
]);
3781 /* Make still unresolved immediate matches conform to size of immediate
3782 given in i.suffix. */
3783 if (!finalize_imm ())
3786 if (i
.types
[0].bitfield
.imm1
)
3787 i
.imm_operands
= 0; /* kludge for shift insns. */
3789 /* We only need to check those implicit registers for instructions
3790 with 3 operands or less. */
3791 if (i
.operands
<= 3)
3792 for (j
= 0; j
< i
.operands
; j
++)
3793 if (i
.types
[j
].bitfield
.inoutportreg
3794 || i
.types
[j
].bitfield
.shiftcount
3795 || i
.types
[j
].bitfield
.acc
3796 || i
.types
[j
].bitfield
.floatacc
)
3799 /* ImmExt should be processed after SSE2AVX. */
3800 if (!i
.tm
.opcode_modifier
.sse2avx
3801 && i
.tm
.opcode_modifier
.immext
)
3804 /* For insns with operands there are more diddles to do to the opcode. */
3807 if (!process_operands ())
3810 else if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
3812 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
3813 as_warn (_("translating to `%sp'"), i
.tm
.name
);
3816 if (i
.tm
.opcode_modifier
.vex
|| i
.tm
.opcode_modifier
.evex
)
3818 if (flag_code
== CODE_16BIT
)
3820 as_bad (_("instruction `%s' isn't supported in 16-bit mode."),
3825 if (i
.tm
.opcode_modifier
.vex
)
3826 build_vex_prefix (t
);
3828 build_evex_prefix ();
3831 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
3832 instructions may define INT_OPCODE as well, so avoid this corner
3833 case for those instructions that use MODRM. */
3834 if (i
.tm
.base_opcode
== INT_OPCODE
3835 && !i
.tm
.opcode_modifier
.modrm
3836 && i
.op
[0].imms
->X_add_number
== 3)
3838 i
.tm
.base_opcode
= INT3_OPCODE
;
3842 if ((i
.tm
.opcode_modifier
.jump
3843 || i
.tm
.opcode_modifier
.jumpbyte
3844 || i
.tm
.opcode_modifier
.jumpdword
)
3845 && i
.op
[0].disps
->X_op
== O_constant
)
3847 /* Convert "jmp constant" (and "call constant") to a jump (call) to
3848 the absolute address given by the constant. Since ix86 jumps and
3849 calls are pc relative, we need to generate a reloc. */
3850 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
3851 i
.op
[0].disps
->X_op
= O_symbol
;
3854 if (i
.tm
.opcode_modifier
.rex64
)
3857 /* For 8 bit registers we need an empty rex prefix. Also if the
3858 instruction already has a prefix, we need to convert old
3859 registers to new ones. */
3861 if ((i
.types
[0].bitfield
.reg8
3862 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
3863 || (i
.types
[1].bitfield
.reg8
3864 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
3865 || ((i
.types
[0].bitfield
.reg8
3866 || i
.types
[1].bitfield
.reg8
)
3871 i
.rex
|= REX_OPCODE
;
3872 for (x
= 0; x
< 2; x
++)
3874 /* Look for 8 bit operand that uses old registers. */
3875 if (i
.types
[x
].bitfield
.reg8
3876 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
3878 /* In case it is "hi" register, give up. */
3879 if (i
.op
[x
].regs
->reg_num
> 3)
3880 as_bad (_("can't encode register '%s%s' in an "
3881 "instruction requiring REX prefix."),
3882 register_prefix
, i
.op
[x
].regs
->reg_name
);
3884 /* Otherwise it is equivalent to the extended register.
3885 Since the encoding doesn't change this is merely
3886 cosmetic cleanup for debug output. */
3888 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
3894 add_prefix (REX_OPCODE
| i
.rex
);
3896 /* We are ready to output the insn. */
3901 parse_insn (char *line
, char *mnemonic
)
3904 char *token_start
= l
;
3907 const insn_template
*t
;
3913 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
3918 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
3920 as_bad (_("no such instruction: `%s'"), token_start
);
3925 if (!is_space_char (*l
)
3926 && *l
!= END_OF_INSN
3928 || (*l
!= PREFIX_SEPARATOR
3931 as_bad (_("invalid character %s in mnemonic"),
3932 output_invalid (*l
));
3935 if (token_start
== l
)
3937 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
3938 as_bad (_("expecting prefix; got nothing"));
3940 as_bad (_("expecting mnemonic; got nothing"));
3944 /* Look up instruction (or prefix) via hash table. */
3945 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
3947 if (*l
!= END_OF_INSN
3948 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
3949 && current_templates
3950 && current_templates
->start
->opcode_modifier
.isprefix
)
3952 if (!cpu_flags_check_cpu64 (current_templates
->start
->cpu_flags
))
3954 as_bad ((flag_code
!= CODE_64BIT
3955 ? _("`%s' is only supported in 64-bit mode")
3956 : _("`%s' is not supported in 64-bit mode")),
3957 current_templates
->start
->name
);
3960 /* If we are in 16-bit mode, do not allow addr16 or data16.
3961 Similarly, in 32-bit mode, do not allow addr32 or data32. */
3962 if ((current_templates
->start
->opcode_modifier
.size16
3963 || current_templates
->start
->opcode_modifier
.size32
)
3964 && flag_code
!= CODE_64BIT
3965 && (current_templates
->start
->opcode_modifier
.size32
3966 ^ (flag_code
== CODE_16BIT
)))
3968 as_bad (_("redundant %s prefix"),
3969 current_templates
->start
->name
);
3972 if (current_templates
->start
->opcode_length
== 0)
3974 /* Handle pseudo prefixes. */
3975 switch (current_templates
->start
->base_opcode
)
3979 i
.disp_encoding
= disp_encoding_8bit
;
3983 i
.disp_encoding
= disp_encoding_32bit
;
3987 i
.dir_encoding
= dir_encoding_load
;
3991 i
.dir_encoding
= dir_encoding_store
;
3995 i
.vec_encoding
= vex_encoding_vex2
;
3999 i
.vec_encoding
= vex_encoding_vex3
;
4003 i
.vec_encoding
= vex_encoding_evex
;
4011 /* Add prefix, checking for repeated prefixes. */
4012 switch (add_prefix (current_templates
->start
->base_opcode
))
4017 if (current_templates
->start
->cpu_flags
.bitfield
.cpucet
)
4018 i
.notrack_prefix
= current_templates
->start
->name
;
4021 if (current_templates
->start
->cpu_flags
.bitfield
.cpuhle
)
4022 i
.hle_prefix
= current_templates
->start
->name
;
4023 else if (current_templates
->start
->cpu_flags
.bitfield
.cpumpx
)
4024 i
.bnd_prefix
= current_templates
->start
->name
;
4026 i
.rep_prefix
= current_templates
->start
->name
;
4032 /* Skip past PREFIX_SEPARATOR and reset token_start. */
4039 if (!current_templates
)
4041 /* Check if we should swap operand or force 32bit displacement in
4043 if (mnem_p
- 2 == dot_p
&& dot_p
[1] == 's')
4044 i
.dir_encoding
= dir_encoding_store
;
4045 else if (mnem_p
- 3 == dot_p
4048 i
.disp_encoding
= disp_encoding_8bit
;
4049 else if (mnem_p
- 4 == dot_p
4053 i
.disp_encoding
= disp_encoding_32bit
;
4058 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
4061 if (!current_templates
)
4064 /* See if we can get a match by trimming off a suffix. */
4067 case WORD_MNEM_SUFFIX
:
4068 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
4069 i
.suffix
= SHORT_MNEM_SUFFIX
;
4072 case BYTE_MNEM_SUFFIX
:
4073 case QWORD_MNEM_SUFFIX
:
4074 i
.suffix
= mnem_p
[-1];
4076 current_templates
= (const templates
*) hash_find (op_hash
,
4079 case SHORT_MNEM_SUFFIX
:
4080 case LONG_MNEM_SUFFIX
:
4083 i
.suffix
= mnem_p
[-1];
4085 current_templates
= (const templates
*) hash_find (op_hash
,
4094 if (intel_float_operand (mnemonic
) == 1)
4095 i
.suffix
= SHORT_MNEM_SUFFIX
;
4097 i
.suffix
= LONG_MNEM_SUFFIX
;
4099 current_templates
= (const templates
*) hash_find (op_hash
,
4104 if (!current_templates
)
4106 as_bad (_("no such instruction: `%s'"), token_start
);
4111 if (current_templates
->start
->opcode_modifier
.jump
4112 || current_templates
->start
->opcode_modifier
.jumpbyte
)
4114 /* Check for a branch hint. We allow ",pt" and ",pn" for
4115 predict taken and predict not taken respectively.
4116 I'm not sure that branch hints actually do anything on loop
4117 and jcxz insns (JumpByte) for current Pentium4 chips. They
4118 may work in the future and it doesn't hurt to accept them
4120 if (l
[0] == ',' && l
[1] == 'p')
4124 if (!add_prefix (DS_PREFIX_OPCODE
))
4128 else if (l
[2] == 'n')
4130 if (!add_prefix (CS_PREFIX_OPCODE
))
4136 /* Any other comma loses. */
4139 as_bad (_("invalid character %s in mnemonic"),
4140 output_invalid (*l
));
4144 /* Check if instruction is supported on specified architecture. */
4146 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
4148 supported
|= cpu_flags_match (t
);
4149 if (supported
== CPU_FLAGS_PERFECT_MATCH
)
4153 if (!(supported
& CPU_FLAGS_64BIT_MATCH
))
4155 as_bad (flag_code
== CODE_64BIT
4156 ? _("`%s' is not supported in 64-bit mode")
4157 : _("`%s' is only supported in 64-bit mode"),
4158 current_templates
->start
->name
);
4161 if (supported
!= CPU_FLAGS_PERFECT_MATCH
)
4163 as_bad (_("`%s' is not supported on `%s%s'"),
4164 current_templates
->start
->name
,
4165 cpu_arch_name
? cpu_arch_name
: default_arch
,
4166 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
4171 if (!cpu_arch_flags
.bitfield
.cpui386
4172 && (flag_code
!= CODE_16BIT
))
4174 as_warn (_("use .code16 to ensure correct addressing mode"));
4181 parse_operands (char *l
, const char *mnemonic
)
4185 /* 1 if operand is pending after ','. */
4186 unsigned int expecting_operand
= 0;
4188 /* Non-zero if operand parens not balanced. */
4189 unsigned int paren_not_balanced
;
4191 while (*l
!= END_OF_INSN
)
4193 /* Skip optional white space before operand. */
4194 if (is_space_char (*l
))
4196 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
&& *l
!= '"')
4198 as_bad (_("invalid character %s before operand %d"),
4199 output_invalid (*l
),
4203 token_start
= l
; /* After white space. */
4204 paren_not_balanced
= 0;
4205 while (paren_not_balanced
|| *l
!= ',')
4207 if (*l
== END_OF_INSN
)
4209 if (paren_not_balanced
)
4212 as_bad (_("unbalanced parenthesis in operand %d."),
4215 as_bad (_("unbalanced brackets in operand %d."),
4220 break; /* we are done */
4222 else if (!is_operand_char (*l
) && !is_space_char (*l
) && *l
!= '"')
4224 as_bad (_("invalid character %s in operand %d"),
4225 output_invalid (*l
),
4232 ++paren_not_balanced
;
4234 --paren_not_balanced
;
4239 ++paren_not_balanced
;
4241 --paren_not_balanced
;
4245 if (l
!= token_start
)
4246 { /* Yes, we've read in another operand. */
4247 unsigned int operand_ok
;
4248 this_operand
= i
.operands
++;
4249 if (i
.operands
> MAX_OPERANDS
)
4251 as_bad (_("spurious operands; (%d operands/instruction max)"),
4255 i
.types
[this_operand
].bitfield
.unspecified
= 1;
4256 /* Now parse operand adding info to 'i' as we go along. */
4257 END_STRING_AND_SAVE (l
);
4261 i386_intel_operand (token_start
,
4262 intel_float_operand (mnemonic
));
4264 operand_ok
= i386_att_operand (token_start
);
4266 RESTORE_END_STRING (l
);
4272 if (expecting_operand
)
4274 expecting_operand_after_comma
:
4275 as_bad (_("expecting operand after ','; got nothing"));
4280 as_bad (_("expecting operand before ','; got nothing"));
4285 /* Now *l must be either ',' or END_OF_INSN. */
4288 if (*++l
== END_OF_INSN
)
4290 /* Just skip it, if it's \n complain. */
4291 goto expecting_operand_after_comma
;
4293 expecting_operand
= 1;
4300 swap_2_operands (int xchg1
, int xchg2
)
4302 union i386_op temp_op
;
4303 i386_operand_type temp_type
;
4304 enum bfd_reloc_code_real temp_reloc
;
4306 temp_type
= i
.types
[xchg2
];
4307 i
.types
[xchg2
] = i
.types
[xchg1
];
4308 i
.types
[xchg1
] = temp_type
;
4309 temp_op
= i
.op
[xchg2
];
4310 i
.op
[xchg2
] = i
.op
[xchg1
];
4311 i
.op
[xchg1
] = temp_op
;
4312 temp_reloc
= i
.reloc
[xchg2
];
4313 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
4314 i
.reloc
[xchg1
] = temp_reloc
;
4318 if (i
.mask
->operand
== xchg1
)
4319 i
.mask
->operand
= xchg2
;
4320 else if (i
.mask
->operand
== xchg2
)
4321 i
.mask
->operand
= xchg1
;
4325 if (i
.broadcast
->operand
== xchg1
)
4326 i
.broadcast
->operand
= xchg2
;
4327 else if (i
.broadcast
->operand
== xchg2
)
4328 i
.broadcast
->operand
= xchg1
;
4332 if (i
.rounding
->operand
== xchg1
)
4333 i
.rounding
->operand
= xchg2
;
4334 else if (i
.rounding
->operand
== xchg2
)
4335 i
.rounding
->operand
= xchg1
;
4340 swap_operands (void)
4346 swap_2_operands (1, i
.operands
- 2);
4350 swap_2_operands (0, i
.operands
- 1);
4356 if (i
.mem_operands
== 2)
4358 const seg_entry
*temp_seg
;
4359 temp_seg
= i
.seg
[0];
4360 i
.seg
[0] = i
.seg
[1];
4361 i
.seg
[1] = temp_seg
;
4365 /* Try to ensure constant immediates are represented in the smallest
4370 char guess_suffix
= 0;
4374 guess_suffix
= i
.suffix
;
4375 else if (i
.reg_operands
)
4377 /* Figure out a suffix from the last register operand specified.
4378 We can't do this properly yet, ie. excluding InOutPortReg,
4379 but the following works for instructions with immediates.
4380 In any case, we can't set i.suffix yet. */
4381 for (op
= i
.operands
; --op
>= 0;)
4382 if (i
.types
[op
].bitfield
.reg8
)
4384 guess_suffix
= BYTE_MNEM_SUFFIX
;
4387 else if (i
.types
[op
].bitfield
.reg16
)
4389 guess_suffix
= WORD_MNEM_SUFFIX
;
4392 else if (i
.types
[op
].bitfield
.reg32
)
4394 guess_suffix
= LONG_MNEM_SUFFIX
;
4397 else if (i
.types
[op
].bitfield
.reg64
)
4399 guess_suffix
= QWORD_MNEM_SUFFIX
;
4403 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
4404 guess_suffix
= WORD_MNEM_SUFFIX
;
4406 for (op
= i
.operands
; --op
>= 0;)
4407 if (operand_type_check (i
.types
[op
], imm
))
4409 switch (i
.op
[op
].imms
->X_op
)
4412 /* If a suffix is given, this operand may be shortened. */
4413 switch (guess_suffix
)
4415 case LONG_MNEM_SUFFIX
:
4416 i
.types
[op
].bitfield
.imm32
= 1;
4417 i
.types
[op
].bitfield
.imm64
= 1;
4419 case WORD_MNEM_SUFFIX
:
4420 i
.types
[op
].bitfield
.imm16
= 1;
4421 i
.types
[op
].bitfield
.imm32
= 1;
4422 i
.types
[op
].bitfield
.imm32s
= 1;
4423 i
.types
[op
].bitfield
.imm64
= 1;
4425 case BYTE_MNEM_SUFFIX
:
4426 i
.types
[op
].bitfield
.imm8
= 1;
4427 i
.types
[op
].bitfield
.imm8s
= 1;
4428 i
.types
[op
].bitfield
.imm16
= 1;
4429 i
.types
[op
].bitfield
.imm32
= 1;
4430 i
.types
[op
].bitfield
.imm32s
= 1;
4431 i
.types
[op
].bitfield
.imm64
= 1;
4435 /* If this operand is at most 16 bits, convert it
4436 to a signed 16 bit number before trying to see
4437 whether it will fit in an even smaller size.
4438 This allows a 16-bit operand such as $0xffe0 to
4439 be recognised as within Imm8S range. */
4440 if ((i
.types
[op
].bitfield
.imm16
)
4441 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
4443 i
.op
[op
].imms
->X_add_number
=
4444 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
4447 /* Store 32-bit immediate in 64-bit for 64-bit BFD. */
4448 if ((i
.types
[op
].bitfield
.imm32
)
4449 && ((i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1))
4452 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
4453 ^ ((offsetT
) 1 << 31))
4454 - ((offsetT
) 1 << 31));
4458 = operand_type_or (i
.types
[op
],
4459 smallest_imm_type (i
.op
[op
].imms
->X_add_number
));
4461 /* We must avoid matching of Imm32 templates when 64bit
4462 only immediate is available. */
4463 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
4464 i
.types
[op
].bitfield
.imm32
= 0;
4471 /* Symbols and expressions. */
4473 /* Convert symbolic operand to proper sizes for matching, but don't
4474 prevent matching a set of insns that only supports sizes other
4475 than those matching the insn suffix. */
4477 i386_operand_type mask
, allowed
;
4478 const insn_template
*t
;
4480 operand_type_set (&mask
, 0);
4481 operand_type_set (&allowed
, 0);
4483 for (t
= current_templates
->start
;
4484 t
< current_templates
->end
;
4486 allowed
= operand_type_or (allowed
,
4487 t
->operand_types
[op
]);
4488 switch (guess_suffix
)
4490 case QWORD_MNEM_SUFFIX
:
4491 mask
.bitfield
.imm64
= 1;
4492 mask
.bitfield
.imm32s
= 1;
4494 case LONG_MNEM_SUFFIX
:
4495 mask
.bitfield
.imm32
= 1;
4497 case WORD_MNEM_SUFFIX
:
4498 mask
.bitfield
.imm16
= 1;
4500 case BYTE_MNEM_SUFFIX
:
4501 mask
.bitfield
.imm8
= 1;
4506 allowed
= operand_type_and (mask
, allowed
);
4507 if (!operand_type_all_zero (&allowed
))
4508 i
.types
[op
] = operand_type_and (i
.types
[op
], mask
);
4515 /* Try to use the smallest displacement type too. */
4517 optimize_disp (void)
4521 for (op
= i
.operands
; --op
>= 0;)
4522 if (operand_type_check (i
.types
[op
], disp
))
4524 if (i
.op
[op
].disps
->X_op
== O_constant
)
4526 offsetT op_disp
= i
.op
[op
].disps
->X_add_number
;
4528 if (i
.types
[op
].bitfield
.disp16
4529 && (op_disp
& ~(offsetT
) 0xffff) == 0)
4531 /* If this operand is at most 16 bits, convert
4532 to a signed 16 bit number and don't use 64bit
4534 op_disp
= (((op_disp
& 0xffff) ^ 0x8000) - 0x8000);
4535 i
.types
[op
].bitfield
.disp64
= 0;
4538 /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */
4539 if (i
.types
[op
].bitfield
.disp32
4540 && (op_disp
& ~(((offsetT
) 2 << 31) - 1)) == 0)
4542 /* If this operand is at most 32 bits, convert
4543 to a signed 32 bit number and don't use 64bit
4545 op_disp
&= (((offsetT
) 2 << 31) - 1);
4546 op_disp
= (op_disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
4547 i
.types
[op
].bitfield
.disp64
= 0;
4550 if (!op_disp
&& i
.types
[op
].bitfield
.baseindex
)
4552 i
.types
[op
].bitfield
.disp8
= 0;
4553 i
.types
[op
].bitfield
.disp16
= 0;
4554 i
.types
[op
].bitfield
.disp32
= 0;
4555 i
.types
[op
].bitfield
.disp32s
= 0;
4556 i
.types
[op
].bitfield
.disp64
= 0;
4560 else if (flag_code
== CODE_64BIT
)
4562 if (fits_in_signed_long (op_disp
))
4564 i
.types
[op
].bitfield
.disp64
= 0;
4565 i
.types
[op
].bitfield
.disp32s
= 1;
4567 if (i
.prefix
[ADDR_PREFIX
]
4568 && fits_in_unsigned_long (op_disp
))
4569 i
.types
[op
].bitfield
.disp32
= 1;
4571 if ((i
.types
[op
].bitfield
.disp32
4572 || i
.types
[op
].bitfield
.disp32s
4573 || i
.types
[op
].bitfield
.disp16
)
4574 && fits_in_signed_byte (op_disp
))
4575 i
.types
[op
].bitfield
.disp8
= 1;
4577 else if (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
4578 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
)
4580 fix_new_exp (frag_now
, frag_more (0) - frag_now
->fr_literal
, 0,
4581 i
.op
[op
].disps
, 0, i
.reloc
[op
]);
4582 i
.types
[op
].bitfield
.disp8
= 0;
4583 i
.types
[op
].bitfield
.disp16
= 0;
4584 i
.types
[op
].bitfield
.disp32
= 0;
4585 i
.types
[op
].bitfield
.disp32s
= 0;
4586 i
.types
[op
].bitfield
.disp64
= 0;
4589 /* We only support 64bit displacement on constants. */
4590 i
.types
[op
].bitfield
.disp64
= 0;
4594 /* Check if operands are valid for the instruction. */
4597 check_VecOperands (const insn_template
*t
)
4601 /* Without VSIB byte, we can't have a vector register for index. */
4602 if (!t
->opcode_modifier
.vecsib
4604 && (i
.index_reg
->reg_type
.bitfield
.regxmm
4605 || i
.index_reg
->reg_type
.bitfield
.regymm
4606 || i
.index_reg
->reg_type
.bitfield
.regzmm
))
4608 i
.error
= unsupported_vector_index_register
;
4612 /* Check if default mask is allowed. */
4613 if (t
->opcode_modifier
.nodefmask
4614 && (!i
.mask
|| i
.mask
->mask
->reg_num
== 0))
4616 i
.error
= no_default_mask
;
4620 /* For VSIB byte, we need a vector register for index, and all vector
4621 registers must be distinct. */
4622 if (t
->opcode_modifier
.vecsib
)
4625 || !((t
->opcode_modifier
.vecsib
== VecSIB128
4626 && i
.index_reg
->reg_type
.bitfield
.regxmm
)
4627 || (t
->opcode_modifier
.vecsib
== VecSIB256
4628 && i
.index_reg
->reg_type
.bitfield
.regymm
)
4629 || (t
->opcode_modifier
.vecsib
== VecSIB512
4630 && i
.index_reg
->reg_type
.bitfield
.regzmm
)))
4632 i
.error
= invalid_vsib_address
;
4636 gas_assert (i
.reg_operands
== 2 || i
.mask
);
4637 if (i
.reg_operands
== 2 && !i
.mask
)
4639 gas_assert (i
.types
[0].bitfield
.regxmm
4640 || i
.types
[0].bitfield
.regymm
);
4641 gas_assert (i
.types
[2].bitfield
.regxmm
4642 || i
.types
[2].bitfield
.regymm
);
4643 if (operand_check
== check_none
)
4645 if (register_number (i
.op
[0].regs
)
4646 != register_number (i
.index_reg
)
4647 && register_number (i
.op
[2].regs
)
4648 != register_number (i
.index_reg
)
4649 && register_number (i
.op
[0].regs
)
4650 != register_number (i
.op
[2].regs
))
4652 if (operand_check
== check_error
)
4654 i
.error
= invalid_vector_register_set
;
4657 as_warn (_("mask, index, and destination registers should be distinct"));
4659 else if (i
.reg_operands
== 1 && i
.mask
)
4661 if ((i
.types
[1].bitfield
.regxmm
4662 || i
.types
[1].bitfield
.regymm
4663 || i
.types
[1].bitfield
.regzmm
)
4664 && (register_number (i
.op
[1].regs
)
4665 == register_number (i
.index_reg
)))
4667 if (operand_check
== check_error
)
4669 i
.error
= invalid_vector_register_set
;
4672 if (operand_check
!= check_none
)
4673 as_warn (_("index and destination registers should be distinct"));
4678 /* Check if broadcast is supported by the instruction and is applied
4679 to the memory operand. */
4682 int broadcasted_opnd_size
;
4684 /* Check if specified broadcast is supported in this instruction,
4685 and it's applied to memory operand of DWORD or QWORD type,
4686 depending on VecESize. */
4687 if (i
.broadcast
->type
!= t
->opcode_modifier
.broadcast
4688 || !i
.types
[i
.broadcast
->operand
].bitfield
.mem
4689 || (t
->opcode_modifier
.vecesize
== 0
4690 && !i
.types
[i
.broadcast
->operand
].bitfield
.dword
4691 && !i
.types
[i
.broadcast
->operand
].bitfield
.unspecified
)
4692 || (t
->opcode_modifier
.vecesize
== 1
4693 && !i
.types
[i
.broadcast
->operand
].bitfield
.qword
4694 && !i
.types
[i
.broadcast
->operand
].bitfield
.unspecified
))
4697 broadcasted_opnd_size
= t
->opcode_modifier
.vecesize
? 64 : 32;
4698 if (i
.broadcast
->type
== BROADCAST_1TO16
)
4699 broadcasted_opnd_size
<<= 4; /* Broadcast 1to16. */
4700 else if (i
.broadcast
->type
== BROADCAST_1TO8
)
4701 broadcasted_opnd_size
<<= 3; /* Broadcast 1to8. */
4702 else if (i
.broadcast
->type
== BROADCAST_1TO4
)
4703 broadcasted_opnd_size
<<= 2; /* Broadcast 1to4. */
4704 else if (i
.broadcast
->type
== BROADCAST_1TO2
)
4705 broadcasted_opnd_size
<<= 1; /* Broadcast 1to2. */
4709 if ((broadcasted_opnd_size
== 256
4710 && !t
->operand_types
[i
.broadcast
->operand
].bitfield
.ymmword
)
4711 || (broadcasted_opnd_size
== 512
4712 && !t
->operand_types
[i
.broadcast
->operand
].bitfield
.zmmword
))
4715 i
.error
= unsupported_broadcast
;
4719 /* If broadcast is supported in this instruction, we need to check if
4720 operand of one-element size isn't specified without broadcast. */
4721 else if (t
->opcode_modifier
.broadcast
&& i
.mem_operands
)
4723 /* Find memory operand. */
4724 for (op
= 0; op
< i
.operands
; op
++)
4725 if (operand_type_check (i
.types
[op
], anymem
))
4727 gas_assert (op
< i
.operands
);
4728 /* Check size of the memory operand. */
4729 if ((t
->opcode_modifier
.vecesize
== 0
4730 && i
.types
[op
].bitfield
.dword
)
4731 || (t
->opcode_modifier
.vecesize
== 1
4732 && i
.types
[op
].bitfield
.qword
))
4734 i
.error
= broadcast_needed
;
4739 /* Check if requested masking is supported. */
4741 && (!t
->opcode_modifier
.masking
4743 && t
->opcode_modifier
.masking
== MERGING_MASKING
)))
4745 i
.error
= unsupported_masking
;
4749 /* Check if masking is applied to dest operand. */
4750 if (i
.mask
&& (i
.mask
->operand
!= (int) (i
.operands
- 1)))
4752 i
.error
= mask_not_on_destination
;
4759 if ((i
.rounding
->type
!= saeonly
4760 && !t
->opcode_modifier
.staticrounding
)
4761 || (i
.rounding
->type
== saeonly
4762 && (t
->opcode_modifier
.staticrounding
4763 || !t
->opcode_modifier
.sae
)))
4765 i
.error
= unsupported_rc_sae
;
4768 /* If the instruction has several immediate operands and one of
4769 them is rounding, the rounding operand should be the last
4770 immediate operand. */
4771 if (i
.imm_operands
> 1
4772 && i
.rounding
->operand
!= (int) (i
.imm_operands
- 1))
4774 i
.error
= rc_sae_operand_not_last_imm
;
4779 /* Check vector Disp8 operand. */
4780 if (t
->opcode_modifier
.disp8memshift
)
4783 i
.memshift
= t
->opcode_modifier
.vecesize
? 3 : 2;
4785 i
.memshift
= t
->opcode_modifier
.disp8memshift
;
4787 for (op
= 0; op
< i
.operands
; op
++)
4788 if (operand_type_check (i
.types
[op
], disp
)
4789 && i
.op
[op
].disps
->X_op
== O_constant
)
4791 offsetT value
= i
.op
[op
].disps
->X_add_number
;
4793 = (i
.disp_encoding
!= disp_encoding_32bit
4794 && fits_in_vec_disp8 (value
));
4795 if (t
->operand_types
[op
].bitfield
.vec_disp8
)
4798 i
.types
[op
].bitfield
.vec_disp8
= 1;
4801 /* Vector insn can only have Vec_Disp8/Disp32 in
4802 32/64bit modes, and Vec_Disp8/Disp16 in 16bit
4804 i
.types
[op
].bitfield
.disp8
= 0;
4805 if (flag_code
!= CODE_16BIT
)
4806 i
.types
[op
].bitfield
.disp16
= 0;
4809 else if (flag_code
!= CODE_16BIT
)
4811 /* One form of this instruction supports vector Disp8.
4812 Try vector Disp8 if we need to use Disp32. */
4813 if (vec_disp8_ok
&& !fits_in_signed_byte (value
))
4815 i
.error
= try_vector_disp8
;
4827 /* Check if operands are valid for the instruction. Update VEX
4831 VEX_check_operands (const insn_template
*t
)
4833 if (i
.vec_encoding
== vex_encoding_evex
)
4835 /* This instruction must be encoded with EVEX prefix. */
4836 if (!t
->opcode_modifier
.evex
)
4838 i
.error
= unsupported
;
4844 if (!t
->opcode_modifier
.vex
)
4846 /* This instruction template doesn't have VEX prefix. */
4847 if (i
.vec_encoding
!= vex_encoding_default
)
4849 i
.error
= unsupported
;
4855 /* Only check VEX_Imm4, which must be the first operand. */
4856 if (t
->operand_types
[0].bitfield
.vec_imm4
)
4858 if (i
.op
[0].imms
->X_op
!= O_constant
4859 || !fits_in_imm4 (i
.op
[0].imms
->X_add_number
))
4865 /* Turn off Imm8 so that update_imm won't complain. */
4866 i
.types
[0] = vec_imm4
;
4872 static const insn_template
*
4873 match_template (char mnem_suffix
)
4875 /* Points to template once we've found it. */
4876 const insn_template
*t
;
4877 i386_operand_type overlap0
, overlap1
, overlap2
, overlap3
;
4878 i386_operand_type overlap4
;
4879 unsigned int found_reverse_match
;
4880 i386_opcode_modifier suffix_check
, mnemsuf_check
;
4881 i386_operand_type operand_types
[MAX_OPERANDS
];
4882 int addr_prefix_disp
;
4884 unsigned int found_cpu_match
;
4885 unsigned int check_register
;
4886 enum i386_error specific_error
= 0;
4888 #if MAX_OPERANDS != 5
4889 # error "MAX_OPERANDS must be 5."
4892 found_reverse_match
= 0;
4893 addr_prefix_disp
= -1;
4895 memset (&suffix_check
, 0, sizeof (suffix_check
));
4896 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
4897 suffix_check
.no_bsuf
= 1;
4898 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
4899 suffix_check
.no_wsuf
= 1;
4900 else if (i
.suffix
== SHORT_MNEM_SUFFIX
)
4901 suffix_check
.no_ssuf
= 1;
4902 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
4903 suffix_check
.no_lsuf
= 1;
4904 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
4905 suffix_check
.no_qsuf
= 1;
4906 else if (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
)
4907 suffix_check
.no_ldsuf
= 1;
4909 memset (&mnemsuf_check
, 0, sizeof (mnemsuf_check
));
4912 switch (mnem_suffix
)
4914 case BYTE_MNEM_SUFFIX
: mnemsuf_check
.no_bsuf
= 1; break;
4915 case WORD_MNEM_SUFFIX
: mnemsuf_check
.no_wsuf
= 1; break;
4916 case SHORT_MNEM_SUFFIX
: mnemsuf_check
.no_ssuf
= 1; break;
4917 case LONG_MNEM_SUFFIX
: mnemsuf_check
.no_lsuf
= 1; break;
4918 case QWORD_MNEM_SUFFIX
: mnemsuf_check
.no_qsuf
= 1; break;
4922 /* Must have right number of operands. */
4923 i
.error
= number_of_operands_mismatch
;
4925 for (t
= current_templates
->start
; t
< current_templates
->end
; t
++)
4927 addr_prefix_disp
= -1;
4929 if (i
.operands
!= t
->operands
)
4932 /* Check processor support. */
4933 i
.error
= unsupported
;
4934 found_cpu_match
= (cpu_flags_match (t
)
4935 == CPU_FLAGS_PERFECT_MATCH
);
4936 if (!found_cpu_match
)
4939 /* Check old gcc support. */
4940 i
.error
= old_gcc_only
;
4941 if (!old_gcc
&& t
->opcode_modifier
.oldgcc
)
4944 /* Check AT&T mnemonic. */
4945 i
.error
= unsupported_with_intel_mnemonic
;
4946 if (intel_mnemonic
&& t
->opcode_modifier
.attmnemonic
)
4949 /* Check AT&T/Intel syntax and Intel64/AMD64 ISA. */
4950 i
.error
= unsupported_syntax
;
4951 if ((intel_syntax
&& t
->opcode_modifier
.attsyntax
)
4952 || (!intel_syntax
&& t
->opcode_modifier
.intelsyntax
)
4953 || (intel64
&& t
->opcode_modifier
.amd64
)
4954 || (!intel64
&& t
->opcode_modifier
.intel64
))
4957 /* Check the suffix, except for some instructions in intel mode. */
4958 i
.error
= invalid_instruction_suffix
;
4959 if ((!intel_syntax
|| !t
->opcode_modifier
.ignoresize
)
4960 && ((t
->opcode_modifier
.no_bsuf
&& suffix_check
.no_bsuf
)
4961 || (t
->opcode_modifier
.no_wsuf
&& suffix_check
.no_wsuf
)
4962 || (t
->opcode_modifier
.no_lsuf
&& suffix_check
.no_lsuf
)
4963 || (t
->opcode_modifier
.no_ssuf
&& suffix_check
.no_ssuf
)
4964 || (t
->opcode_modifier
.no_qsuf
&& suffix_check
.no_qsuf
)
4965 || (t
->opcode_modifier
.no_ldsuf
&& suffix_check
.no_ldsuf
)))
4967 /* In Intel mode all mnemonic suffixes must be explicitly allowed. */
4968 if ((t
->opcode_modifier
.no_bsuf
&& mnemsuf_check
.no_bsuf
)
4969 || (t
->opcode_modifier
.no_wsuf
&& mnemsuf_check
.no_wsuf
)
4970 || (t
->opcode_modifier
.no_lsuf
&& mnemsuf_check
.no_lsuf
)
4971 || (t
->opcode_modifier
.no_ssuf
&& mnemsuf_check
.no_ssuf
)
4972 || (t
->opcode_modifier
.no_qsuf
&& mnemsuf_check
.no_qsuf
)
4973 || (t
->opcode_modifier
.no_ldsuf
&& mnemsuf_check
.no_ldsuf
))
4976 if (!operand_size_match (t
))
4979 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4980 operand_types
[j
] = t
->operand_types
[j
];
4982 /* In general, don't allow 64-bit operands in 32-bit mode. */
4983 if (i
.suffix
== QWORD_MNEM_SUFFIX
4984 && flag_code
!= CODE_64BIT
4986 ? (!t
->opcode_modifier
.ignoresize
4987 && !intel_float_operand (t
->name
))
4988 : intel_float_operand (t
->name
) != 2)
4989 && ((!operand_types
[0].bitfield
.regmmx
4990 && !operand_types
[0].bitfield
.regxmm
4991 && !operand_types
[0].bitfield
.regymm
4992 && !operand_types
[0].bitfield
.regzmm
)
4993 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
4994 && operand_types
[t
->operands
> 1].bitfield
.regxmm
4995 && operand_types
[t
->operands
> 1].bitfield
.regymm
4996 && operand_types
[t
->operands
> 1].bitfield
.regzmm
))
4997 && (t
->base_opcode
!= 0x0fc7
4998 || t
->extension_opcode
!= 1 /* cmpxchg8b */))
5001 /* In general, don't allow 32-bit operands on pre-386. */
5002 else if (i
.suffix
== LONG_MNEM_SUFFIX
5003 && !cpu_arch_flags
.bitfield
.cpui386
5005 ? (!t
->opcode_modifier
.ignoresize
5006 && !intel_float_operand (t
->name
))
5007 : intel_float_operand (t
->name
) != 2)
5008 && ((!operand_types
[0].bitfield
.regmmx
5009 && !operand_types
[0].bitfield
.regxmm
)
5010 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
5011 && operand_types
[t
->operands
> 1].bitfield
.regxmm
)))
5014 /* Do not verify operands when there are none. */
5018 /* We've found a match; break out of loop. */
5022 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
5023 into Disp32/Disp16/Disp32 operand. */
5024 if (i
.prefix
[ADDR_PREFIX
] != 0)
5026 /* There should be only one Disp operand. */
5030 for (j
= 0; j
< MAX_OPERANDS
; j
++)
5032 if (operand_types
[j
].bitfield
.disp16
)
5034 addr_prefix_disp
= j
;
5035 operand_types
[j
].bitfield
.disp32
= 1;
5036 operand_types
[j
].bitfield
.disp16
= 0;
5042 for (j
= 0; j
< MAX_OPERANDS
; j
++)
5044 if (operand_types
[j
].bitfield
.disp32
)
5046 addr_prefix_disp
= j
;
5047 operand_types
[j
].bitfield
.disp32
= 0;
5048 operand_types
[j
].bitfield
.disp16
= 1;
5054 for (j
= 0; j
< MAX_OPERANDS
; j
++)
5056 if (operand_types
[j
].bitfield
.disp64
)
5058 addr_prefix_disp
= j
;
5059 operand_types
[j
].bitfield
.disp64
= 0;
5060 operand_types
[j
].bitfield
.disp32
= 1;
5068 /* Force 0x8b encoding for "mov foo@GOT, %eax". */
5069 if (i
.reloc
[0] == BFD_RELOC_386_GOT32
&& t
->base_opcode
== 0xa0)
5072 /* We check register size if needed. */
5073 check_register
= t
->opcode_modifier
.checkregsize
;
5074 overlap0
= operand_type_and (i
.types
[0], operand_types
[0]);
5075 switch (t
->operands
)
5078 if (!operand_type_match (overlap0
, i
.types
[0]))
5082 /* xchg %eax, %eax is a special case. It is an alias for nop
5083 only in 32bit mode and we can use opcode 0x90. In 64bit
5084 mode, we can't use 0x90 for xchg %eax, %eax since it should
5085 zero-extend %eax to %rax. */
5086 if (flag_code
== CODE_64BIT
5087 && t
->base_opcode
== 0x90
5088 && operand_type_equal (&i
.types
[0], &acc32
)
5089 && operand_type_equal (&i
.types
[1], &acc32
))
5091 /* If we want store form, we reverse direction of operands. */
5092 if (i
.dir_encoding
== dir_encoding_store
5093 && t
->opcode_modifier
.d
)
5098 /* If we want store form, we skip the current load. */
5099 if (i
.dir_encoding
== dir_encoding_store
5100 && i
.mem_operands
== 0
5101 && t
->opcode_modifier
.load
)
5106 overlap1
= operand_type_and (i
.types
[1], operand_types
[1]);
5107 if (!operand_type_match (overlap0
, i
.types
[0])
5108 || !operand_type_match (overlap1
, i
.types
[1])
5110 && !operand_type_register_match (overlap0
, i
.types
[0],
5112 overlap1
, i
.types
[1],
5115 /* Check if other direction is valid ... */
5116 if (!t
->opcode_modifier
.d
&& !t
->opcode_modifier
.floatd
)
5120 /* Try reversing direction of operands. */
5121 overlap0
= operand_type_and (i
.types
[0], operand_types
[1]);
5122 overlap1
= operand_type_and (i
.types
[1], operand_types
[0]);
5123 if (!operand_type_match (overlap0
, i
.types
[0])
5124 || !operand_type_match (overlap1
, i
.types
[1])
5126 && !operand_type_register_match (overlap0
,
5133 /* Does not match either direction. */
5136 /* found_reverse_match holds which of D or FloatDR
5138 if (t
->opcode_modifier
.d
)
5139 found_reverse_match
= Opcode_D
;
5140 else if (t
->opcode_modifier
.floatd
)
5141 found_reverse_match
= Opcode_FloatD
;
5143 found_reverse_match
= 0;
5144 if (t
->opcode_modifier
.floatr
)
5145 found_reverse_match
|= Opcode_FloatR
;
5149 /* Found a forward 2 operand match here. */
5150 switch (t
->operands
)
5153 overlap4
= operand_type_and (i
.types
[4],
5157 overlap3
= operand_type_and (i
.types
[3],
5161 overlap2
= operand_type_and (i
.types
[2],
5166 switch (t
->operands
)
5169 if (!operand_type_match (overlap4
, i
.types
[4])
5170 || !operand_type_register_match (overlap3
,
5179 if (!operand_type_match (overlap3
, i
.types
[3])
5181 && !operand_type_register_match (overlap2
,
5190 /* Here we make use of the fact that there are no
5191 reverse match 3 operand instructions, and all 3
5192 operand instructions only need to be checked for
5193 register consistency between operands 2 and 3. */
5194 if (!operand_type_match (overlap2
, i
.types
[2])
5196 && !operand_type_register_match (overlap1
,
5206 /* Found either forward/reverse 2, 3 or 4 operand match here:
5207 slip through to break. */
5209 if (!found_cpu_match
)
5211 found_reverse_match
= 0;
5215 /* Check if vector and VEX operands are valid. */
5216 if (check_VecOperands (t
) || VEX_check_operands (t
))
5218 specific_error
= i
.error
;
5222 /* We've found a match; break out of loop. */
5226 if (t
== current_templates
->end
)
5228 /* We found no match. */
5229 const char *err_msg
;
5230 switch (specific_error
? specific_error
: i
.error
)
5234 case operand_size_mismatch
:
5235 err_msg
= _("operand size mismatch");
5237 case operand_type_mismatch
:
5238 err_msg
= _("operand type mismatch");
5240 case register_type_mismatch
:
5241 err_msg
= _("register type mismatch");
5243 case number_of_operands_mismatch
:
5244 err_msg
= _("number of operands mismatch");
5246 case invalid_instruction_suffix
:
5247 err_msg
= _("invalid instruction suffix");
5250 err_msg
= _("constant doesn't fit in 4 bits");
5253 err_msg
= _("only supported with old gcc");
5255 case unsupported_with_intel_mnemonic
:
5256 err_msg
= _("unsupported with Intel mnemonic");
5258 case unsupported_syntax
:
5259 err_msg
= _("unsupported syntax");
5262 as_bad (_("unsupported instruction `%s'"),
5263 current_templates
->start
->name
);
5265 case invalid_vsib_address
:
5266 err_msg
= _("invalid VSIB address");
5268 case invalid_vector_register_set
:
5269 err_msg
= _("mask, index, and destination registers must be distinct");
5271 case unsupported_vector_index_register
:
5272 err_msg
= _("unsupported vector index register");
5274 case unsupported_broadcast
:
5275 err_msg
= _("unsupported broadcast");
5277 case broadcast_not_on_src_operand
:
5278 err_msg
= _("broadcast not on source memory operand");
5280 case broadcast_needed
:
5281 err_msg
= _("broadcast is needed for operand of such type");
5283 case unsupported_masking
:
5284 err_msg
= _("unsupported masking");
5286 case mask_not_on_destination
:
5287 err_msg
= _("mask not on destination operand");
5289 case no_default_mask
:
5290 err_msg
= _("default mask isn't allowed");
5292 case unsupported_rc_sae
:
5293 err_msg
= _("unsupported static rounding/sae");
5295 case rc_sae_operand_not_last_imm
:
5297 err_msg
= _("RC/SAE operand must precede immediate operands");
5299 err_msg
= _("RC/SAE operand must follow immediate operands");
5301 case invalid_register_operand
:
5302 err_msg
= _("invalid register operand");
5305 as_bad (_("%s for `%s'"), err_msg
,
5306 current_templates
->start
->name
);
5310 if (!quiet_warnings
)
5313 && (i
.types
[0].bitfield
.jumpabsolute
5314 != operand_types
[0].bitfield
.jumpabsolute
))
5316 as_warn (_("indirect %s without `*'"), t
->name
);
5319 if (t
->opcode_modifier
.isprefix
5320 && t
->opcode_modifier
.ignoresize
)
5322 /* Warn them that a data or address size prefix doesn't
5323 affect assembly of the next line of code. */
5324 as_warn (_("stand-alone `%s' prefix"), t
->name
);
5328 /* Copy the template we found. */
5331 if (addr_prefix_disp
!= -1)
5332 i
.tm
.operand_types
[addr_prefix_disp
]
5333 = operand_types
[addr_prefix_disp
];
5335 if (found_reverse_match
)
5337 /* If we found a reverse match we must alter the opcode
5338 direction bit. found_reverse_match holds bits to change
5339 (different for int & float insns). */
5341 i
.tm
.base_opcode
^= found_reverse_match
;
5343 i
.tm
.operand_types
[0] = operand_types
[1];
5344 i
.tm
.operand_types
[1] = operand_types
[0];
5353 int mem_op
= operand_type_check (i
.types
[0], anymem
) ? 0 : 1;
5354 if (i
.tm
.operand_types
[mem_op
].bitfield
.esseg
)
5356 if (i
.seg
[0] != NULL
&& i
.seg
[0] != &es
)
5358 as_bad (_("`%s' operand %d must use `%ses' segment"),
5364 /* There's only ever one segment override allowed per instruction.
5365 This instruction possibly has a legal segment override on the
5366 second operand, so copy the segment to where non-string
5367 instructions store it, allowing common code. */
5368 i
.seg
[0] = i
.seg
[1];
5370 else if (i
.tm
.operand_types
[mem_op
+ 1].bitfield
.esseg
)
5372 if (i
.seg
[1] != NULL
&& i
.seg
[1] != &es
)
5374 as_bad (_("`%s' operand %d must use `%ses' segment"),
5385 process_suffix (void)
5387 /* If matched instruction specifies an explicit instruction mnemonic
5389 if (i
.tm
.opcode_modifier
.size16
)
5390 i
.suffix
= WORD_MNEM_SUFFIX
;
5391 else if (i
.tm
.opcode_modifier
.size32
)
5392 i
.suffix
= LONG_MNEM_SUFFIX
;
5393 else if (i
.tm
.opcode_modifier
.size64
)
5394 i
.suffix
= QWORD_MNEM_SUFFIX
;
5395 else if (i
.reg_operands
)
5397 /* If there's no instruction mnemonic suffix we try to invent one
5398 based on register operands. */
5401 /* We take i.suffix from the last register operand specified,
5402 Destination register type is more significant than source
5403 register type. crc32 in SSE4.2 prefers source register
5405 if (i
.tm
.base_opcode
== 0xf20f38f1)
5407 if (i
.types
[0].bitfield
.reg16
)
5408 i
.suffix
= WORD_MNEM_SUFFIX
;
5409 else if (i
.types
[0].bitfield
.reg32
)
5410 i
.suffix
= LONG_MNEM_SUFFIX
;
5411 else if (i
.types
[0].bitfield
.reg64
)
5412 i
.suffix
= QWORD_MNEM_SUFFIX
;
5414 else if (i
.tm
.base_opcode
== 0xf20f38f0)
5416 if (i
.types
[0].bitfield
.reg8
)
5417 i
.suffix
= BYTE_MNEM_SUFFIX
;
5424 if (i
.tm
.base_opcode
== 0xf20f38f1
5425 || i
.tm
.base_opcode
== 0xf20f38f0)
5427 /* We have to know the operand size for crc32. */
5428 as_bad (_("ambiguous memory operand size for `%s`"),
5433 for (op
= i
.operands
; --op
>= 0;)
5434 if (!i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
5436 if (i
.types
[op
].bitfield
.reg8
)
5438 i
.suffix
= BYTE_MNEM_SUFFIX
;
5441 else if (i
.types
[op
].bitfield
.reg16
)
5443 i
.suffix
= WORD_MNEM_SUFFIX
;
5446 else if (i
.types
[op
].bitfield
.reg32
)
5448 i
.suffix
= LONG_MNEM_SUFFIX
;
5451 else if (i
.types
[op
].bitfield
.reg64
)
5453 i
.suffix
= QWORD_MNEM_SUFFIX
;
5459 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
5462 && i
.tm
.opcode_modifier
.ignoresize
5463 && i
.tm
.opcode_modifier
.no_bsuf
)
5465 else if (!check_byte_reg ())
5468 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
5471 && i
.tm
.opcode_modifier
.ignoresize
5472 && i
.tm
.opcode_modifier
.no_lsuf
)
5474 else if (!check_long_reg ())
5477 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
5480 && i
.tm
.opcode_modifier
.ignoresize
5481 && i
.tm
.opcode_modifier
.no_qsuf
)
5483 else if (!check_qword_reg ())
5486 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
5489 && i
.tm
.opcode_modifier
.ignoresize
5490 && i
.tm
.opcode_modifier
.no_wsuf
)
5492 else if (!check_word_reg ())
5495 else if (i
.suffix
== XMMWORD_MNEM_SUFFIX
5496 || i
.suffix
== YMMWORD_MNEM_SUFFIX
5497 || i
.suffix
== ZMMWORD_MNEM_SUFFIX
)
5499 /* Skip if the instruction has x/y/z suffix. match_template
5500 should check if it is a valid suffix. */
5502 else if (intel_syntax
&& i
.tm
.opcode_modifier
.ignoresize
)
5503 /* Do nothing if the instruction is going to ignore the prefix. */
5508 else if (i
.tm
.opcode_modifier
.defaultsize
5510 /* exclude fldenv/frstor/fsave/fstenv */
5511 && i
.tm
.opcode_modifier
.no_ssuf
)
5513 i
.suffix
= stackop_size
;
5515 else if (intel_syntax
5517 && (i
.tm
.operand_types
[0].bitfield
.jumpabsolute
5518 || i
.tm
.opcode_modifier
.jumpbyte
5519 || i
.tm
.opcode_modifier
.jumpintersegment
5520 || (i
.tm
.base_opcode
== 0x0f01 /* [ls][gi]dt */
5521 && i
.tm
.extension_opcode
<= 3)))
5526 if (!i
.tm
.opcode_modifier
.no_qsuf
)
5528 i
.suffix
= QWORD_MNEM_SUFFIX
;
5533 if (!i
.tm
.opcode_modifier
.no_lsuf
)
5534 i
.suffix
= LONG_MNEM_SUFFIX
;
5537 if (!i
.tm
.opcode_modifier
.no_wsuf
)
5538 i
.suffix
= WORD_MNEM_SUFFIX
;
5547 if (i
.tm
.opcode_modifier
.w
)
5549 as_bad (_("no instruction mnemonic suffix given and "
5550 "no register operands; can't size instruction"));
5556 unsigned int suffixes
;
5558 suffixes
= !i
.tm
.opcode_modifier
.no_bsuf
;
5559 if (!i
.tm
.opcode_modifier
.no_wsuf
)
5561 if (!i
.tm
.opcode_modifier
.no_lsuf
)
5563 if (!i
.tm
.opcode_modifier
.no_ldsuf
)
5565 if (!i
.tm
.opcode_modifier
.no_ssuf
)
5567 if (!i
.tm
.opcode_modifier
.no_qsuf
)
5570 /* There are more than suffix matches. */
5571 if (i
.tm
.opcode_modifier
.w
5572 || ((suffixes
& (suffixes
- 1))
5573 && !i
.tm
.opcode_modifier
.defaultsize
5574 && !i
.tm
.opcode_modifier
.ignoresize
))
5576 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
5582 /* Change the opcode based on the operand size given by i.suffix;
5583 We don't need to change things for byte insns. */
5586 && i
.suffix
!= BYTE_MNEM_SUFFIX
5587 && i
.suffix
!= XMMWORD_MNEM_SUFFIX
5588 && i
.suffix
!= YMMWORD_MNEM_SUFFIX
5589 && i
.suffix
!= ZMMWORD_MNEM_SUFFIX
)
5591 /* It's not a byte, select word/dword operation. */
5592 if (i
.tm
.opcode_modifier
.w
)
5594 if (i
.tm
.opcode_modifier
.shortform
)
5595 i
.tm
.base_opcode
|= 8;
5597 i
.tm
.base_opcode
|= 1;
5600 /* Now select between word & dword operations via the operand
5601 size prefix, except for instructions that will ignore this
5603 if (i
.tm
.opcode_modifier
.addrprefixop0
)
5605 /* The address size override prefix changes the size of the
5607 if ((flag_code
== CODE_32BIT
5608 && i
.op
->regs
[0].reg_type
.bitfield
.reg16
)
5609 || (flag_code
!= CODE_32BIT
5610 && i
.op
->regs
[0].reg_type
.bitfield
.reg32
))
5611 if (!add_prefix (ADDR_PREFIX_OPCODE
))
5614 else if (i
.suffix
!= QWORD_MNEM_SUFFIX
5615 && i
.suffix
!= LONG_DOUBLE_MNEM_SUFFIX
5616 && !i
.tm
.opcode_modifier
.ignoresize
5617 && !i
.tm
.opcode_modifier
.floatmf
5618 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
5619 || (flag_code
== CODE_64BIT
5620 && i
.tm
.opcode_modifier
.jumpbyte
)))
5622 unsigned int prefix
= DATA_PREFIX_OPCODE
;
5624 if (i
.tm
.opcode_modifier
.jumpbyte
) /* jcxz, loop */
5625 prefix
= ADDR_PREFIX_OPCODE
;
5627 if (!add_prefix (prefix
))
5631 /* Set mode64 for an operand. */
5632 if (i
.suffix
== QWORD_MNEM_SUFFIX
5633 && flag_code
== CODE_64BIT
5634 && !i
.tm
.opcode_modifier
.norex64
)
5636 /* Special case for xchg %rax,%rax. It is NOP and doesn't
5637 need rex64. cmpxchg8b is also a special case. */
5638 if (! (i
.operands
== 2
5639 && i
.tm
.base_opcode
== 0x90
5640 && i
.tm
.extension_opcode
== None
5641 && operand_type_equal (&i
.types
[0], &acc64
)
5642 && operand_type_equal (&i
.types
[1], &acc64
))
5643 && ! (i
.operands
== 1
5644 && i
.tm
.base_opcode
== 0xfc7
5645 && i
.tm
.extension_opcode
== 1
5646 && !operand_type_check (i
.types
[0], reg
)
5647 && operand_type_check (i
.types
[0], anymem
)))
5651 /* Size floating point instruction. */
5652 if (i
.suffix
== LONG_MNEM_SUFFIX
)
5653 if (i
.tm
.opcode_modifier
.floatmf
)
5654 i
.tm
.base_opcode
^= 4;
5661 check_byte_reg (void)
5665 for (op
= i
.operands
; --op
>= 0;)
5667 /* If this is an eight bit register, it's OK. If it's the 16 or
5668 32 bit version of an eight bit register, we will just use the
5669 low portion, and that's OK too. */
5670 if (i
.types
[op
].bitfield
.reg8
)
5673 /* I/O port address operands are OK too. */
5674 if (i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
5677 /* crc32 doesn't generate this warning. */
5678 if (i
.tm
.base_opcode
== 0xf20f38f0)
5681 if ((i
.types
[op
].bitfield
.reg16
5682 || i
.types
[op
].bitfield
.reg32
5683 || i
.types
[op
].bitfield
.reg64
)
5684 && i
.op
[op
].regs
->reg_num
< 4
5685 /* Prohibit these changes in 64bit mode, since the lowering
5686 would be more complicated. */
5687 && flag_code
!= CODE_64BIT
)
5689 #if REGISTER_WARNINGS
5690 if (!quiet_warnings
)
5691 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5693 (i
.op
[op
].regs
+ (i
.types
[op
].bitfield
.reg16
5694 ? REGNAM_AL
- REGNAM_AX
5695 : REGNAM_AL
- REGNAM_EAX
))->reg_name
,
5697 i
.op
[op
].regs
->reg_name
,
5702 /* Any other register is bad. */
5703 if (i
.types
[op
].bitfield
.reg16
5704 || i
.types
[op
].bitfield
.reg32
5705 || i
.types
[op
].bitfield
.reg64
5706 || i
.types
[op
].bitfield
.regmmx
5707 || i
.types
[op
].bitfield
.regxmm
5708 || i
.types
[op
].bitfield
.regymm
5709 || i
.types
[op
].bitfield
.regzmm
5710 || i
.types
[op
].bitfield
.sreg2
5711 || i
.types
[op
].bitfield
.sreg3
5712 || i
.types
[op
].bitfield
.control
5713 || i
.types
[op
].bitfield
.debug
5714 || i
.types
[op
].bitfield
.test
5715 || i
.types
[op
].bitfield
.floatreg
5716 || i
.types
[op
].bitfield
.floatacc
)
5718 as_bad (_("`%s%s' not allowed with `%s%c'"),
5720 i
.op
[op
].regs
->reg_name
,
5730 check_long_reg (void)
5734 for (op
= i
.operands
; --op
>= 0;)
5735 /* Reject eight bit registers, except where the template requires
5736 them. (eg. movzb) */
5737 if (i
.types
[op
].bitfield
.reg8
5738 && (i
.tm
.operand_types
[op
].bitfield
.reg16
5739 || i
.tm
.operand_types
[op
].bitfield
.reg32
5740 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5742 as_bad (_("`%s%s' not allowed with `%s%c'"),
5744 i
.op
[op
].regs
->reg_name
,
5749 /* Warn if the e prefix on a general reg is missing. */
5750 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
5751 && i
.types
[op
].bitfield
.reg16
5752 && (i
.tm
.operand_types
[op
].bitfield
.reg32
5753 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5755 /* Prohibit these changes in the 64bit mode, since the
5756 lowering is more complicated. */
5757 if (flag_code
== CODE_64BIT
)
5759 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5760 register_prefix
, i
.op
[op
].regs
->reg_name
,
5764 #if REGISTER_WARNINGS
5765 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5767 (i
.op
[op
].regs
+ REGNAM_EAX
- REGNAM_AX
)->reg_name
,
5768 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
5771 /* Warn if the r prefix on a general reg is present. */
5772 else if (i
.types
[op
].bitfield
.reg64
5773 && (i
.tm
.operand_types
[op
].bitfield
.reg32
5774 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5777 && i
.tm
.opcode_modifier
.toqword
5778 && !i
.types
[0].bitfield
.regxmm
)
5780 /* Convert to QWORD. We want REX byte. */
5781 i
.suffix
= QWORD_MNEM_SUFFIX
;
5785 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5786 register_prefix
, i
.op
[op
].regs
->reg_name
,
5795 check_qword_reg (void)
5799 for (op
= i
.operands
; --op
>= 0; )
5800 /* Reject eight bit registers, except where the template requires
5801 them. (eg. movzb) */
5802 if (i
.types
[op
].bitfield
.reg8
5803 && (i
.tm
.operand_types
[op
].bitfield
.reg16
5804 || i
.tm
.operand_types
[op
].bitfield
.reg32
5805 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5807 as_bad (_("`%s%s' not allowed with `%s%c'"),
5809 i
.op
[op
].regs
->reg_name
,
5814 /* Warn if the r prefix on a general reg is missing. */
5815 else if ((i
.types
[op
].bitfield
.reg16
5816 || i
.types
[op
].bitfield
.reg32
)
5817 && (i
.tm
.operand_types
[op
].bitfield
.reg64
5818 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5820 /* Prohibit these changes in the 64bit mode, since the
5821 lowering is more complicated. */
5823 && i
.tm
.opcode_modifier
.todword
5824 && !i
.types
[0].bitfield
.regxmm
)
5826 /* Convert to DWORD. We don't want REX byte. */
5827 i
.suffix
= LONG_MNEM_SUFFIX
;
5831 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5832 register_prefix
, i
.op
[op
].regs
->reg_name
,
5841 check_word_reg (void)
5844 for (op
= i
.operands
; --op
>= 0;)
5845 /* Reject eight bit registers, except where the template requires
5846 them. (eg. movzb) */
5847 if (i
.types
[op
].bitfield
.reg8
5848 && (i
.tm
.operand_types
[op
].bitfield
.reg16
5849 || i
.tm
.operand_types
[op
].bitfield
.reg32
5850 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5852 as_bad (_("`%s%s' not allowed with `%s%c'"),
5854 i
.op
[op
].regs
->reg_name
,
5859 /* Warn if the e or r prefix on a general reg is present. */
5860 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
5861 && (i
.types
[op
].bitfield
.reg32
5862 || i
.types
[op
].bitfield
.reg64
)
5863 && (i
.tm
.operand_types
[op
].bitfield
.reg16
5864 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5866 /* Prohibit these changes in the 64bit mode, since the
5867 lowering is more complicated. */
5868 if (flag_code
== CODE_64BIT
)
5870 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5871 register_prefix
, i
.op
[op
].regs
->reg_name
,
5875 #if REGISTER_WARNINGS
5876 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5878 (i
.op
[op
].regs
+ REGNAM_AX
- REGNAM_EAX
)->reg_name
,
5879 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
5886 update_imm (unsigned int j
)
5888 i386_operand_type overlap
= i
.types
[j
];
5889 if ((overlap
.bitfield
.imm8
5890 || overlap
.bitfield
.imm8s
5891 || overlap
.bitfield
.imm16
5892 || overlap
.bitfield
.imm32
5893 || overlap
.bitfield
.imm32s
5894 || overlap
.bitfield
.imm64
)
5895 && !operand_type_equal (&overlap
, &imm8
)
5896 && !operand_type_equal (&overlap
, &imm8s
)
5897 && !operand_type_equal (&overlap
, &imm16
)
5898 && !operand_type_equal (&overlap
, &imm32
)
5899 && !operand_type_equal (&overlap
, &imm32s
)
5900 && !operand_type_equal (&overlap
, &imm64
))
5904 i386_operand_type temp
;
5906 operand_type_set (&temp
, 0);
5907 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
5909 temp
.bitfield
.imm8
= overlap
.bitfield
.imm8
;
5910 temp
.bitfield
.imm8s
= overlap
.bitfield
.imm8s
;
5912 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
5913 temp
.bitfield
.imm16
= overlap
.bitfield
.imm16
;
5914 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
5916 temp
.bitfield
.imm64
= overlap
.bitfield
.imm64
;
5917 temp
.bitfield
.imm32s
= overlap
.bitfield
.imm32s
;
5920 temp
.bitfield
.imm32
= overlap
.bitfield
.imm32
;
5923 else if (operand_type_equal (&overlap
, &imm16_32_32s
)
5924 || operand_type_equal (&overlap
, &imm16_32
)
5925 || operand_type_equal (&overlap
, &imm16_32s
))
5927 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
5932 if (!operand_type_equal (&overlap
, &imm8
)
5933 && !operand_type_equal (&overlap
, &imm8s
)
5934 && !operand_type_equal (&overlap
, &imm16
)
5935 && !operand_type_equal (&overlap
, &imm32
)
5936 && !operand_type_equal (&overlap
, &imm32s
)
5937 && !operand_type_equal (&overlap
, &imm64
))
5939 as_bad (_("no instruction mnemonic suffix given; "
5940 "can't determine immediate size"));
5944 i
.types
[j
] = overlap
;
5954 /* Update the first 2 immediate operands. */
5955 n
= i
.operands
> 2 ? 2 : i
.operands
;
5958 for (j
= 0; j
< n
; j
++)
5959 if (update_imm (j
) == 0)
5962 /* The 3rd operand can't be immediate operand. */
5963 gas_assert (operand_type_check (i
.types
[2], imm
) == 0);
5970 bad_implicit_operand (int xmm
)
5972 const char *ireg
= xmm
? "xmm0" : "ymm0";
5975 as_bad (_("the last operand of `%s' must be `%s%s'"),
5976 i
.tm
.name
, register_prefix
, ireg
);
5978 as_bad (_("the first operand of `%s' must be `%s%s'"),
5979 i
.tm
.name
, register_prefix
, ireg
);
5984 process_operands (void)
5986 /* Default segment register this instruction will use for memory
5987 accesses. 0 means unknown. This is only for optimizing out
5988 unnecessary segment overrides. */
5989 const seg_entry
*default_seg
= 0;
5991 if (i
.tm
.opcode_modifier
.sse2avx
&& i
.tm
.opcode_modifier
.vexvvvv
)
5993 unsigned int dupl
= i
.operands
;
5994 unsigned int dest
= dupl
- 1;
5997 /* The destination must be an xmm register. */
5998 gas_assert (i
.reg_operands
5999 && MAX_OPERANDS
> dupl
6000 && operand_type_equal (&i
.types
[dest
], ®xmm
));
6002 if (i
.tm
.opcode_modifier
.firstxmm0
)
6004 /* The first operand is implicit and must be xmm0. */
6005 gas_assert (operand_type_equal (&i
.types
[0], ®xmm
));
6006 if (register_number (i
.op
[0].regs
) != 0)
6007 return bad_implicit_operand (1);
6009 if (i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
)
6011 /* Keep xmm0 for instructions with VEX prefix and 3
6017 /* We remove the first xmm0 and keep the number of
6018 operands unchanged, which in fact duplicates the
6020 for (j
= 1; j
< i
.operands
; j
++)
6022 i
.op
[j
- 1] = i
.op
[j
];
6023 i
.types
[j
- 1] = i
.types
[j
];
6024 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
6028 else if (i
.tm
.opcode_modifier
.implicit1stxmm0
)
6030 gas_assert ((MAX_OPERANDS
- 1) > dupl
6031 && (i
.tm
.opcode_modifier
.vexsources
6034 /* Add the implicit xmm0 for instructions with VEX prefix
6036 for (j
= i
.operands
; j
> 0; j
--)
6038 i
.op
[j
] = i
.op
[j
- 1];
6039 i
.types
[j
] = i
.types
[j
- 1];
6040 i
.tm
.operand_types
[j
] = i
.tm
.operand_types
[j
- 1];
6043 = (const reg_entry
*) hash_find (reg_hash
, "xmm0");
6044 i
.types
[0] = regxmm
;
6045 i
.tm
.operand_types
[0] = regxmm
;
6048 i
.reg_operands
+= 2;
6053 i
.op
[dupl
] = i
.op
[dest
];
6054 i
.types
[dupl
] = i
.types
[dest
];
6055 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
6064 i
.op
[dupl
] = i
.op
[dest
];
6065 i
.types
[dupl
] = i
.types
[dest
];
6066 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
6069 if (i
.tm
.opcode_modifier
.immext
)
6072 else if (i
.tm
.opcode_modifier
.firstxmm0
)
6076 /* The first operand is implicit and must be xmm0/ymm0/zmm0. */
6077 gas_assert (i
.reg_operands
6078 && (operand_type_equal (&i
.types
[0], ®xmm
)
6079 || operand_type_equal (&i
.types
[0], ®ymm
)
6080 || operand_type_equal (&i
.types
[0], ®zmm
)));
6081 if (register_number (i
.op
[0].regs
) != 0)
6082 return bad_implicit_operand (i
.types
[0].bitfield
.regxmm
);
6084 for (j
= 1; j
< i
.operands
; j
++)
6086 i
.op
[j
- 1] = i
.op
[j
];
6087 i
.types
[j
- 1] = i
.types
[j
];
6089 /* We need to adjust fields in i.tm since they are used by
6090 build_modrm_byte. */
6091 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
6098 else if (i
.tm
.opcode_modifier
.implicitquadgroup
)
6100 /* The second operand must be {x,y,z}mmN, where N is a multiple of 4. */
6101 gas_assert (i
.operands
>= 2
6102 && (operand_type_equal (&i
.types
[1], ®xmm
)
6103 || operand_type_equal (&i
.types
[1], ®ymm
)
6104 || operand_type_equal (&i
.types
[1], ®zmm
)));
6105 unsigned int regnum
= register_number (i
.op
[1].regs
);
6106 unsigned int first_reg_in_group
= regnum
& ~3;
6107 unsigned int last_reg_in_group
= first_reg_in_group
+ 3;
6108 if (regnum
!= first_reg_in_group
) {
6109 as_warn (_("the second source register `%s%s' implicitly denotes"
6110 " `%s%.3s%d' to `%s%.3s%d' source group in `%s'"),
6111 register_prefix
, i
.op
[1].regs
->reg_name
,
6112 register_prefix
, i
.op
[1].regs
->reg_name
, first_reg_in_group
,
6113 register_prefix
, i
.op
[1].regs
->reg_name
, last_reg_in_group
,
6117 else if (i
.tm
.opcode_modifier
.regkludge
)
6119 /* The imul $imm, %reg instruction is converted into
6120 imul $imm, %reg, %reg, and the clr %reg instruction
6121 is converted into xor %reg, %reg. */
6123 unsigned int first_reg_op
;
6125 if (operand_type_check (i
.types
[0], reg
))
6129 /* Pretend we saw the extra register operand. */
6130 gas_assert (i
.reg_operands
== 1
6131 && i
.op
[first_reg_op
+ 1].regs
== 0);
6132 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
6133 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
6138 if (i
.tm
.opcode_modifier
.shortform
)
6140 if (i
.types
[0].bitfield
.sreg2
6141 || i
.types
[0].bitfield
.sreg3
)
6143 if (i
.tm
.base_opcode
== POP_SEG_SHORT
6144 && i
.op
[0].regs
->reg_num
== 1)
6146 as_bad (_("you can't `pop %scs'"), register_prefix
);
6149 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
6150 if ((i
.op
[0].regs
->reg_flags
& RegRex
) != 0)
6155 /* The register or float register operand is in operand
6159 if (i
.types
[0].bitfield
.floatreg
6160 || operand_type_check (i
.types
[0], reg
))
6164 /* Register goes in low 3 bits of opcode. */
6165 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
6166 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
6168 if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
6170 /* Warn about some common errors, but press on regardless.
6171 The first case can be generated by gcc (<= 2.8.1). */
6172 if (i
.operands
== 2)
6174 /* Reversed arguments on faddp, fsubp, etc. */
6175 as_warn (_("translating to `%s %s%s,%s%s'"), i
.tm
.name
,
6176 register_prefix
, i
.op
[!intel_syntax
].regs
->reg_name
,
6177 register_prefix
, i
.op
[intel_syntax
].regs
->reg_name
);
6181 /* Extraneous `l' suffix on fp insn. */
6182 as_warn (_("translating to `%s %s%s'"), i
.tm
.name
,
6183 register_prefix
, i
.op
[0].regs
->reg_name
);
6188 else if (i
.tm
.opcode_modifier
.modrm
)
6190 /* The opcode is completed (modulo i.tm.extension_opcode which
6191 must be put into the modrm byte). Now, we make the modrm and
6192 index base bytes based on all the info we've collected. */
6194 default_seg
= build_modrm_byte ();
6196 else if ((i
.tm
.base_opcode
& ~0x3) == MOV_AX_DISP32
)
6200 else if (i
.tm
.opcode_modifier
.isstring
)
6202 /* For the string instructions that allow a segment override
6203 on one of their operands, the default segment is ds. */
6207 if (i
.tm
.base_opcode
== 0x8d /* lea */
6210 as_warn (_("segment override on `%s' is ineffectual"), i
.tm
.name
);
6212 /* If a segment was explicitly specified, and the specified segment
6213 is not the default, use an opcode prefix to select it. If we
6214 never figured out what the default segment is, then default_seg
6215 will be zero at this point, and the specified segment prefix will
6217 if ((i
.seg
[0]) && (i
.seg
[0] != default_seg
))
6219 if (!add_prefix (i
.seg
[0]->seg_prefix
))
6225 static const seg_entry
*
6226 build_modrm_byte (void)
6228 const seg_entry
*default_seg
= 0;
6229 unsigned int source
, dest
;
6232 /* The first operand of instructions with VEX prefix and 3 sources
6233 must be VEX_Imm4. */
6234 vex_3_sources
= i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
;
6237 unsigned int nds
, reg_slot
;
6240 if (i
.tm
.opcode_modifier
.veximmext
6241 && i
.tm
.opcode_modifier
.immext
)
6243 dest
= i
.operands
- 2;
6244 gas_assert (dest
== 3);
6247 dest
= i
.operands
- 1;
6250 /* There are 2 kinds of instructions:
6251 1. 5 operands: 4 register operands or 3 register operands
6252 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
6253 VexW0 or VexW1. The destination must be either XMM, YMM or
6255 2. 4 operands: 4 register operands or 3 register operands
6256 plus 1 memory operand, VexXDS, and VexImmExt */
6257 gas_assert ((i
.reg_operands
== 4
6258 || (i
.reg_operands
== 3 && i
.mem_operands
== 1))
6259 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
6260 && (i
.tm
.opcode_modifier
.veximmext
6261 || (i
.imm_operands
== 1
6262 && i
.types
[0].bitfield
.vec_imm4
6263 && (i
.tm
.opcode_modifier
.vexw
== VEXW0
6264 || i
.tm
.opcode_modifier
.vexw
== VEXW1
)
6265 && (operand_type_equal (&i
.tm
.operand_types
[dest
], ®xmm
)
6266 || operand_type_equal (&i
.tm
.operand_types
[dest
], ®ymm
)
6267 || operand_type_equal (&i
.tm
.operand_types
[dest
], ®zmm
)))));
6269 if (i
.imm_operands
== 0)
6271 /* When there is no immediate operand, generate an 8bit
6272 immediate operand to encode the first operand. */
6273 exp
= &im_expressions
[i
.imm_operands
++];
6274 i
.op
[i
.operands
].imms
= exp
;
6275 i
.types
[i
.operands
] = imm8
;
6277 /* If VexW1 is set, the first operand is the source and
6278 the second operand is encoded in the immediate operand. */
6279 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
6290 /* FMA swaps REG and NDS. */
6291 if (i
.tm
.cpu_flags
.bitfield
.cpufma
)
6299 gas_assert (operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6301 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6303 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6305 exp
->X_op
= O_constant
;
6306 exp
->X_add_number
= register_number (i
.op
[reg_slot
].regs
) << 4;
6307 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
6311 unsigned int imm_slot
;
6313 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
6315 /* If VexW0 is set, the third operand is the source and
6316 the second operand is encoded in the immediate
6323 /* VexW1 is set, the second operand is the source and
6324 the third operand is encoded in the immediate
6330 if (i
.tm
.opcode_modifier
.immext
)
6332 /* When ImmExt is set, the immediate byte is the last
6334 imm_slot
= i
.operands
- 1;
6342 /* Turn on Imm8 so that output_imm will generate it. */
6343 i
.types
[imm_slot
].bitfield
.imm8
= 1;
6346 gas_assert (operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6348 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6350 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6352 i
.op
[imm_slot
].imms
->X_add_number
6353 |= register_number (i
.op
[reg_slot
].regs
) << 4;
6354 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
6357 gas_assert (operand_type_equal (&i
.tm
.operand_types
[nds
], ®xmm
)
6358 || operand_type_equal (&i
.tm
.operand_types
[nds
],
6360 || operand_type_equal (&i
.tm
.operand_types
[nds
],
6362 i
.vex
.register_specifier
= i
.op
[nds
].regs
;
6367 /* i.reg_operands MUST be the number of real register operands;
6368 implicit registers do not count. If there are 3 register
6369 operands, it must be a instruction with VexNDS. For a
6370 instruction with VexNDD, the destination register is encoded
6371 in VEX prefix. If there are 4 register operands, it must be
6372 a instruction with VEX prefix and 3 sources. */
6373 if (i
.mem_operands
== 0
6374 && ((i
.reg_operands
== 2
6375 && i
.tm
.opcode_modifier
.vexvvvv
<= VEXXDS
)
6376 || (i
.reg_operands
== 3
6377 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
6378 || (i
.reg_operands
== 4 && vex_3_sources
)))
6386 /* When there are 3 operands, one of them may be immediate,
6387 which may be the first or the last operand. Otherwise,
6388 the first operand must be shift count register (cl) or it
6389 is an instruction with VexNDS. */
6390 gas_assert (i
.imm_operands
== 1
6391 || (i
.imm_operands
== 0
6392 && (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
6393 || i
.types
[0].bitfield
.shiftcount
)));
6394 if (operand_type_check (i
.types
[0], imm
)
6395 || i
.types
[0].bitfield
.shiftcount
)
6401 /* When there are 4 operands, the first two must be 8bit
6402 immediate operands. The source operand will be the 3rd
6405 For instructions with VexNDS, if the first operand
6406 an imm8, the source operand is the 2nd one. If the last
6407 operand is imm8, the source operand is the first one. */
6408 gas_assert ((i
.imm_operands
== 2
6409 && i
.types
[0].bitfield
.imm8
6410 && i
.types
[1].bitfield
.imm8
)
6411 || (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
6412 && i
.imm_operands
== 1
6413 && (i
.types
[0].bitfield
.imm8
6414 || i
.types
[i
.operands
- 1].bitfield
.imm8
6416 if (i
.imm_operands
== 2)
6420 if (i
.types
[0].bitfield
.imm8
)
6427 if (i
.tm
.opcode_modifier
.evex
)
6429 /* For EVEX instructions, when there are 5 operands, the
6430 first one must be immediate operand. If the second one
6431 is immediate operand, the source operand is the 3th
6432 one. If the last one is immediate operand, the source
6433 operand is the 2nd one. */
6434 gas_assert (i
.imm_operands
== 2
6435 && i
.tm
.opcode_modifier
.sae
6436 && operand_type_check (i
.types
[0], imm
));
6437 if (operand_type_check (i
.types
[1], imm
))
6439 else if (operand_type_check (i
.types
[4], imm
))
6453 /* RC/SAE operand could be between DEST and SRC. That happens
6454 when one operand is GPR and the other one is XMM/YMM/ZMM
6456 if (i
.rounding
&& i
.rounding
->operand
== (int) dest
)
6459 if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
6461 /* For instructions with VexNDS, the register-only source
6462 operand must be 32/64bit integer, XMM, YMM or ZMM
6463 register. It is encoded in VEX prefix. We need to
6464 clear RegMem bit before calling operand_type_equal. */
6466 i386_operand_type op
;
6469 /* Check register-only source operand when two source
6470 operands are swapped. */
6471 if (!i
.tm
.operand_types
[source
].bitfield
.baseindex
6472 && i
.tm
.operand_types
[dest
].bitfield
.baseindex
)
6480 op
= i
.tm
.operand_types
[vvvv
];
6481 op
.bitfield
.regmem
= 0;
6482 if ((dest
+ 1) >= i
.operands
6483 || (!op
.bitfield
.reg32
6484 && op
.bitfield
.reg64
6485 && !operand_type_equal (&op
, ®xmm
)
6486 && !operand_type_equal (&op
, ®ymm
)
6487 && !operand_type_equal (&op
, ®zmm
)
6488 && !operand_type_equal (&op
, ®mask
)))
6490 i
.vex
.register_specifier
= i
.op
[vvvv
].regs
;
6496 /* One of the register operands will be encoded in the i.tm.reg
6497 field, the other in the combined i.tm.mode and i.tm.regmem
6498 fields. If no form of this instruction supports a memory
6499 destination operand, then we assume the source operand may
6500 sometimes be a memory operand and so we need to store the
6501 destination in the i.rm.reg field. */
6502 if (!i
.tm
.operand_types
[dest
].bitfield
.regmem
6503 && operand_type_check (i
.tm
.operand_types
[dest
], anymem
) == 0)
6505 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
6506 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
6507 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
6509 if ((i
.op
[dest
].regs
->reg_flags
& RegVRex
) != 0)
6511 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
6513 if ((i
.op
[source
].regs
->reg_flags
& RegVRex
) != 0)
6518 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
6519 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
6520 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
6522 if ((i
.op
[dest
].regs
->reg_flags
& RegVRex
) != 0)
6524 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
6526 if ((i
.op
[source
].regs
->reg_flags
& RegVRex
) != 0)
6529 if (flag_code
!= CODE_64BIT
&& (i
.rex
& (REX_R
| REX_B
)))
6531 if (!i
.types
[0].bitfield
.control
6532 && !i
.types
[1].bitfield
.control
)
6534 i
.rex
&= ~(REX_R
| REX_B
);
6535 add_prefix (LOCK_PREFIX_OPCODE
);
6539 { /* If it's not 2 reg operands... */
6544 unsigned int fake_zero_displacement
= 0;
6547 for (op
= 0; op
< i
.operands
; op
++)
6548 if (operand_type_check (i
.types
[op
], anymem
))
6550 gas_assert (op
< i
.operands
);
6552 if (i
.tm
.opcode_modifier
.vecsib
)
6554 if (i
.index_reg
->reg_num
== RegEiz
6555 || i
.index_reg
->reg_num
== RegRiz
)
6558 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6561 i
.sib
.base
= NO_BASE_REGISTER
;
6562 i
.sib
.scale
= i
.log2_scale_factor
;
6563 /* No Vec_Disp8 if there is no base. */
6564 i
.types
[op
].bitfield
.vec_disp8
= 0;
6565 i
.types
[op
].bitfield
.disp8
= 0;
6566 i
.types
[op
].bitfield
.disp16
= 0;
6567 i
.types
[op
].bitfield
.disp64
= 0;
6568 if (flag_code
!= CODE_64BIT
)
6570 /* Must be 32 bit */
6571 i
.types
[op
].bitfield
.disp32
= 1;
6572 i
.types
[op
].bitfield
.disp32s
= 0;
6576 i
.types
[op
].bitfield
.disp32
= 0;
6577 i
.types
[op
].bitfield
.disp32s
= 1;
6580 i
.sib
.index
= i
.index_reg
->reg_num
;
6581 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
6583 if ((i
.index_reg
->reg_flags
& RegVRex
) != 0)
6589 if (i
.base_reg
== 0)
6592 if (!i
.disp_operands
)
6594 fake_zero_displacement
= 1;
6595 /* Instructions with VSIB byte need 32bit displacement
6596 if there is no base register. */
6597 if (i
.tm
.opcode_modifier
.vecsib
)
6598 i
.types
[op
].bitfield
.disp32
= 1;
6600 if (i
.index_reg
== 0)
6602 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6603 /* Operand is just <disp> */
6604 if (flag_code
== CODE_64BIT
)
6606 /* 64bit mode overwrites the 32bit absolute
6607 addressing by RIP relative addressing and
6608 absolute addressing is encoded by one of the
6609 redundant SIB forms. */
6610 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6611 i
.sib
.base
= NO_BASE_REGISTER
;
6612 i
.sib
.index
= NO_INDEX_REGISTER
;
6613 i
.types
[op
] = ((i
.prefix
[ADDR_PREFIX
] == 0)
6614 ? disp32s
: disp32
);
6616 else if ((flag_code
== CODE_16BIT
)
6617 ^ (i
.prefix
[ADDR_PREFIX
] != 0))
6619 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
6620 i
.types
[op
] = disp16
;
6624 i
.rm
.regmem
= NO_BASE_REGISTER
;
6625 i
.types
[op
] = disp32
;
6628 else if (!i
.tm
.opcode_modifier
.vecsib
)
6630 /* !i.base_reg && i.index_reg */
6631 if (i
.index_reg
->reg_num
== RegEiz
6632 || i
.index_reg
->reg_num
== RegRiz
)
6633 i
.sib
.index
= NO_INDEX_REGISTER
;
6635 i
.sib
.index
= i
.index_reg
->reg_num
;
6636 i
.sib
.base
= NO_BASE_REGISTER
;
6637 i
.sib
.scale
= i
.log2_scale_factor
;
6638 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6639 /* No Vec_Disp8 if there is no base. */
6640 i
.types
[op
].bitfield
.vec_disp8
= 0;
6641 i
.types
[op
].bitfield
.disp8
= 0;
6642 i
.types
[op
].bitfield
.disp16
= 0;
6643 i
.types
[op
].bitfield
.disp64
= 0;
6644 if (flag_code
!= CODE_64BIT
)
6646 /* Must be 32 bit */
6647 i
.types
[op
].bitfield
.disp32
= 1;
6648 i
.types
[op
].bitfield
.disp32s
= 0;
6652 i
.types
[op
].bitfield
.disp32
= 0;
6653 i
.types
[op
].bitfield
.disp32s
= 1;
6655 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
6659 /* RIP addressing for 64bit mode. */
6660 else if (i
.base_reg
->reg_num
== RegRip
||
6661 i
.base_reg
->reg_num
== RegEip
)
6663 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6664 i
.rm
.regmem
= NO_BASE_REGISTER
;
6665 i
.types
[op
].bitfield
.disp8
= 0;
6666 i
.types
[op
].bitfield
.disp16
= 0;
6667 i
.types
[op
].bitfield
.disp32
= 0;
6668 i
.types
[op
].bitfield
.disp32s
= 1;
6669 i
.types
[op
].bitfield
.disp64
= 0;
6670 i
.types
[op
].bitfield
.vec_disp8
= 0;
6671 i
.flags
[op
] |= Operand_PCrel
;
6672 if (! i
.disp_operands
)
6673 fake_zero_displacement
= 1;
6675 else if (i
.base_reg
->reg_type
.bitfield
.reg16
)
6677 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6678 switch (i
.base_reg
->reg_num
)
6681 if (i
.index_reg
== 0)
6683 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
6684 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
6688 if (i
.index_reg
== 0)
6691 if (operand_type_check (i
.types
[op
], disp
) == 0)
6693 /* fake (%bp) into 0(%bp) */
6694 if (i
.tm
.operand_types
[op
].bitfield
.vec_disp8
)
6695 i
.types
[op
].bitfield
.vec_disp8
= 1;
6697 i
.types
[op
].bitfield
.disp8
= 1;
6698 fake_zero_displacement
= 1;
6701 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
6702 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
6704 default: /* (%si) -> 4 or (%di) -> 5 */
6705 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
6707 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
6709 else /* i.base_reg and 32/64 bit mode */
6711 if (flag_code
== CODE_64BIT
6712 && operand_type_check (i
.types
[op
], disp
))
6714 i386_operand_type temp
;
6715 operand_type_set (&temp
, 0);
6716 temp
.bitfield
.disp8
= i
.types
[op
].bitfield
.disp8
;
6717 temp
.bitfield
.vec_disp8
6718 = i
.types
[op
].bitfield
.vec_disp8
;
6720 if (i
.prefix
[ADDR_PREFIX
] == 0)
6721 i
.types
[op
].bitfield
.disp32s
= 1;
6723 i
.types
[op
].bitfield
.disp32
= 1;
6726 if (!i
.tm
.opcode_modifier
.vecsib
)
6727 i
.rm
.regmem
= i
.base_reg
->reg_num
;
6728 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
6730 i
.sib
.base
= i
.base_reg
->reg_num
;
6731 /* x86-64 ignores REX prefix bit here to avoid decoder
6733 if (!(i
.base_reg
->reg_flags
& RegRex
)
6734 && (i
.base_reg
->reg_num
== EBP_REG_NUM
6735 || i
.base_reg
->reg_num
== ESP_REG_NUM
))
6737 if (i
.base_reg
->reg_num
== 5 && i
.disp_operands
== 0)
6739 fake_zero_displacement
= 1;
6740 if (i
.tm
.operand_types
[op
].bitfield
.vec_disp8
)
6741 i
.types
[op
].bitfield
.vec_disp8
= 1;
6743 i
.types
[op
].bitfield
.disp8
= 1;
6745 i
.sib
.scale
= i
.log2_scale_factor
;
6746 if (i
.index_reg
== 0)
6748 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6749 /* <disp>(%esp) becomes two byte modrm with no index
6750 register. We've already stored the code for esp
6751 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
6752 Any base register besides %esp will not use the
6753 extra modrm byte. */
6754 i
.sib
.index
= NO_INDEX_REGISTER
;
6756 else if (!i
.tm
.opcode_modifier
.vecsib
)
6758 if (i
.index_reg
->reg_num
== RegEiz
6759 || i
.index_reg
->reg_num
== RegRiz
)
6760 i
.sib
.index
= NO_INDEX_REGISTER
;
6762 i
.sib
.index
= i
.index_reg
->reg_num
;
6763 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6764 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
6769 && (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
6770 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
))
6774 if (!fake_zero_displacement
6778 fake_zero_displacement
= 1;
6779 if (i
.disp_encoding
== disp_encoding_8bit
)
6780 i
.types
[op
].bitfield
.disp8
= 1;
6782 i
.types
[op
].bitfield
.disp32
= 1;
6784 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
6788 if (fake_zero_displacement
)
6790 /* Fakes a zero displacement assuming that i.types[op]
6791 holds the correct displacement size. */
6794 gas_assert (i
.op
[op
].disps
== 0);
6795 exp
= &disp_expressions
[i
.disp_operands
++];
6796 i
.op
[op
].disps
= exp
;
6797 exp
->X_op
= O_constant
;
6798 exp
->X_add_number
= 0;
6799 exp
->X_add_symbol
= (symbolS
*) 0;
6800 exp
->X_op_symbol
= (symbolS
*) 0;
6808 if (i
.tm
.opcode_modifier
.vexsources
== XOP2SOURCES
)
6810 if (operand_type_check (i
.types
[0], imm
))
6811 i
.vex
.register_specifier
= NULL
;
6814 /* VEX.vvvv encodes one of the sources when the first
6815 operand is not an immediate. */
6816 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
6817 i
.vex
.register_specifier
= i
.op
[0].regs
;
6819 i
.vex
.register_specifier
= i
.op
[1].regs
;
6822 /* Destination is a XMM register encoded in the ModRM.reg
6824 i
.rm
.reg
= i
.op
[2].regs
->reg_num
;
6825 if ((i
.op
[2].regs
->reg_flags
& RegRex
) != 0)
6828 /* ModRM.rm and VEX.B encodes the other source. */
6829 if (!i
.mem_operands
)
6833 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
6834 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
6836 i
.rm
.regmem
= i
.op
[0].regs
->reg_num
;
6838 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
6842 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXLWP
)
6844 i
.vex
.register_specifier
= i
.op
[2].regs
;
6845 if (!i
.mem_operands
)
6848 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
6849 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
6853 /* Fill in i.rm.reg or i.rm.regmem field with register operand
6854 (if any) based on i.tm.extension_opcode. Again, we must be
6855 careful to make sure that segment/control/debug/test/MMX
6856 registers are coded into the i.rm.reg field. */
6857 else if (i
.reg_operands
)
6860 unsigned int vex_reg
= ~0;
6862 for (op
= 0; op
< i
.operands
; op
++)
6863 if (i
.types
[op
].bitfield
.reg8
6864 || i
.types
[op
].bitfield
.reg16
6865 || i
.types
[op
].bitfield
.reg32
6866 || i
.types
[op
].bitfield
.reg64
6867 || i
.types
[op
].bitfield
.regmmx
6868 || i
.types
[op
].bitfield
.regxmm
6869 || i
.types
[op
].bitfield
.regymm
6870 || i
.types
[op
].bitfield
.regbnd
6871 || i
.types
[op
].bitfield
.regzmm
6872 || i
.types
[op
].bitfield
.regmask
6873 || i
.types
[op
].bitfield
.sreg2
6874 || i
.types
[op
].bitfield
.sreg3
6875 || i
.types
[op
].bitfield
.control
6876 || i
.types
[op
].bitfield
.debug
6877 || i
.types
[op
].bitfield
.test
)
6882 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
6884 /* For instructions with VexNDS, the register-only
6885 source operand is encoded in VEX prefix. */
6886 gas_assert (mem
!= (unsigned int) ~0);
6891 gas_assert (op
< i
.operands
);
6895 /* Check register-only source operand when two source
6896 operands are swapped. */
6897 if (!i
.tm
.operand_types
[op
].bitfield
.baseindex
6898 && i
.tm
.operand_types
[op
+ 1].bitfield
.baseindex
)
6902 gas_assert (mem
== (vex_reg
+ 1)
6903 && op
< i
.operands
);
6908 gas_assert (vex_reg
< i
.operands
);
6912 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXNDD
)
6914 /* For instructions with VexNDD, the register destination
6915 is encoded in VEX prefix. */
6916 if (i
.mem_operands
== 0)
6918 /* There is no memory operand. */
6919 gas_assert ((op
+ 2) == i
.operands
);
6924 /* There are only 2 operands. */
6925 gas_assert (op
< 2 && i
.operands
== 2);
6930 gas_assert (op
< i
.operands
);
6932 if (vex_reg
!= (unsigned int) ~0)
6934 i386_operand_type
*type
= &i
.tm
.operand_types
[vex_reg
];
6936 if (type
->bitfield
.reg32
!= 1
6937 && type
->bitfield
.reg64
!= 1
6938 && !operand_type_equal (type
, ®xmm
)
6939 && !operand_type_equal (type
, ®ymm
)
6940 && !operand_type_equal (type
, ®zmm
)
6941 && !operand_type_equal (type
, ®mask
))
6944 i
.vex
.register_specifier
= i
.op
[vex_reg
].regs
;
6947 /* Don't set OP operand twice. */
6950 /* If there is an extension opcode to put here, the
6951 register number must be put into the regmem field. */
6952 if (i
.tm
.extension_opcode
!= None
)
6954 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
6955 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
6957 if ((i
.op
[op
].regs
->reg_flags
& RegVRex
) != 0)
6962 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
6963 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
6965 if ((i
.op
[op
].regs
->reg_flags
& RegVRex
) != 0)
6970 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
6971 must set it to 3 to indicate this is a register operand
6972 in the regmem field. */
6973 if (!i
.mem_operands
)
6977 /* Fill in i.rm.reg field with extension opcode (if any). */
6978 if (i
.tm
.extension_opcode
!= None
)
6979 i
.rm
.reg
= i
.tm
.extension_opcode
;
6985 output_branch (void)
6991 relax_substateT subtype
;
6995 code16
= flag_code
== CODE_16BIT
? CODE16
: 0;
6996 size
= i
.disp_encoding
== disp_encoding_32bit
? BIG
: SMALL
;
6999 if (i
.prefix
[DATA_PREFIX
] != 0)
7005 /* Pentium4 branch hints. */
7006 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
7007 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
7012 if (i
.prefix
[REX_PREFIX
] != 0)
7018 /* BND prefixed jump. */
7019 if (i
.prefix
[BND_PREFIX
] != 0)
7021 FRAG_APPEND_1_CHAR (i
.prefix
[BND_PREFIX
]);
7025 if (i
.prefixes
!= 0 && !intel_syntax
)
7026 as_warn (_("skipping prefixes on this instruction"));
7028 /* It's always a symbol; End frag & setup for relax.
7029 Make sure there is enough room in this frag for the largest
7030 instruction we may generate in md_convert_frag. This is 2
7031 bytes for the opcode and room for the prefix and largest
7033 frag_grow (prefix
+ 2 + 4);
7034 /* Prefix and 1 opcode byte go in fr_fix. */
7035 p
= frag_more (prefix
+ 1);
7036 if (i
.prefix
[DATA_PREFIX
] != 0)
7037 *p
++ = DATA_PREFIX_OPCODE
;
7038 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
7039 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
7040 *p
++ = i
.prefix
[SEG_PREFIX
];
7041 if (i
.prefix
[REX_PREFIX
] != 0)
7042 *p
++ = i
.prefix
[REX_PREFIX
];
7043 *p
= i
.tm
.base_opcode
;
7045 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
7046 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, size
);
7047 else if (cpu_arch_flags
.bitfield
.cpui386
)
7048 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, size
);
7050 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, size
);
7053 sym
= i
.op
[0].disps
->X_add_symbol
;
7054 off
= i
.op
[0].disps
->X_add_number
;
7056 if (i
.op
[0].disps
->X_op
!= O_constant
7057 && i
.op
[0].disps
->X_op
!= O_symbol
)
7059 /* Handle complex expressions. */
7060 sym
= make_expr_symbol (i
.op
[0].disps
);
7064 /* 1 possible extra opcode + 4 byte displacement go in var part.
7065 Pass reloc in fr_var. */
7066 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
7076 if (i
.tm
.opcode_modifier
.jumpbyte
)
7078 /* This is a loop or jecxz type instruction. */
7080 if (i
.prefix
[ADDR_PREFIX
] != 0)
7082 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
7085 /* Pentium4 branch hints. */
7086 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
7087 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
7089 FRAG_APPEND_1_CHAR (i
.prefix
[SEG_PREFIX
]);
7098 if (flag_code
== CODE_16BIT
)
7101 if (i
.prefix
[DATA_PREFIX
] != 0)
7103 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
7113 if (i
.prefix
[REX_PREFIX
] != 0)
7115 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
7119 /* BND prefixed jump. */
7120 if (i
.prefix
[BND_PREFIX
] != 0)
7122 FRAG_APPEND_1_CHAR (i
.prefix
[BND_PREFIX
]);
7126 if (i
.prefixes
!= 0 && !intel_syntax
)
7127 as_warn (_("skipping prefixes on this instruction"));
7129 p
= frag_more (i
.tm
.opcode_length
+ size
);
7130 switch (i
.tm
.opcode_length
)
7133 *p
++ = i
.tm
.base_opcode
>> 8;
7136 *p
++ = i
.tm
.base_opcode
;
7142 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
7143 i
.op
[0].disps
, 1, reloc (size
, 1, 1, i
.reloc
[0]));
7145 /* All jumps handled here are signed, but don't use a signed limit
7146 check for 32 and 16 bit jumps as we want to allow wrap around at
7147 4G and 64k respectively. */
7149 fixP
->fx_signed
= 1;
7153 output_interseg_jump (void)
7161 if (flag_code
== CODE_16BIT
)
7165 if (i
.prefix
[DATA_PREFIX
] != 0)
7171 if (i
.prefix
[REX_PREFIX
] != 0)
7181 if (i
.prefixes
!= 0 && !intel_syntax
)
7182 as_warn (_("skipping prefixes on this instruction"));
7184 /* 1 opcode; 2 segment; offset */
7185 p
= frag_more (prefix
+ 1 + 2 + size
);
7187 if (i
.prefix
[DATA_PREFIX
] != 0)
7188 *p
++ = DATA_PREFIX_OPCODE
;
7190 if (i
.prefix
[REX_PREFIX
] != 0)
7191 *p
++ = i
.prefix
[REX_PREFIX
];
7193 *p
++ = i
.tm
.base_opcode
;
7194 if (i
.op
[1].imms
->X_op
== O_constant
)
7196 offsetT n
= i
.op
[1].imms
->X_add_number
;
7199 && !fits_in_unsigned_word (n
)
7200 && !fits_in_signed_word (n
))
7202 as_bad (_("16-bit jump out of range"));
7205 md_number_to_chars (p
, n
, size
);
7208 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
7209 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
7210 if (i
.op
[0].imms
->X_op
!= O_constant
)
7211 as_bad (_("can't handle non absolute segment in `%s'"),
7213 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
7219 fragS
*insn_start_frag
;
7220 offsetT insn_start_off
;
7222 /* Tie dwarf2 debug info to the address at the start of the insn.
7223 We can't do this after the insn has been output as the current
7224 frag may have been closed off. eg. by frag_var. */
7225 dwarf2_emit_insn (0);
7227 insn_start_frag
= frag_now
;
7228 insn_start_off
= frag_now_fix ();
7231 if (i
.tm
.opcode_modifier
.jump
)
7233 else if (i
.tm
.opcode_modifier
.jumpbyte
7234 || i
.tm
.opcode_modifier
.jumpdword
)
7236 else if (i
.tm
.opcode_modifier
.jumpintersegment
)
7237 output_interseg_jump ();
7240 /* Output normal instructions here. */
7244 unsigned int prefix
;
7247 && i
.tm
.base_opcode
== 0xfae
7249 && i
.imm_operands
== 1
7250 && (i
.op
[0].imms
->X_add_number
== 0xe8
7251 || i
.op
[0].imms
->X_add_number
== 0xf0
7252 || i
.op
[0].imms
->X_add_number
== 0xf8))
7254 /* Encode lfence, mfence, and sfence as
7255 f0 83 04 24 00 lock addl $0x0, (%{re}sp). */
7256 offsetT val
= 0x240483f0ULL
;
7258 md_number_to_chars (p
, val
, 5);
7262 /* Some processors fail on LOCK prefix. This options makes
7263 assembler ignore LOCK prefix and serves as a workaround. */
7264 if (omit_lock_prefix
)
7266 if (i
.tm
.base_opcode
== LOCK_PREFIX_OPCODE
)
7268 i
.prefix
[LOCK_PREFIX
] = 0;
7271 /* Since the VEX/EVEX prefix contains the implicit prefix, we
7272 don't need the explicit prefix. */
7273 if (!i
.tm
.opcode_modifier
.vex
&& !i
.tm
.opcode_modifier
.evex
)
7275 switch (i
.tm
.opcode_length
)
7278 if (i
.tm
.base_opcode
& 0xff000000)
7280 prefix
= (i
.tm
.base_opcode
>> 24) & 0xff;
7285 if ((i
.tm
.base_opcode
& 0xff0000) != 0)
7287 prefix
= (i
.tm
.base_opcode
>> 16) & 0xff;
7288 if (i
.tm
.cpu_flags
.bitfield
.cpupadlock
)
7291 if (prefix
!= REPE_PREFIX_OPCODE
7292 || (i
.prefix
[REP_PREFIX
]
7293 != REPE_PREFIX_OPCODE
))
7294 add_prefix (prefix
);
7297 add_prefix (prefix
);
7306 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
7307 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
7308 R_X86_64_GOTTPOFF relocation so that linker can safely
7309 perform IE->LE optimization. */
7310 if (x86_elf_abi
== X86_64_X32_ABI
7312 && i
.reloc
[0] == BFD_RELOC_X86_64_GOTTPOFF
7313 && i
.prefix
[REX_PREFIX
] == 0)
7314 add_prefix (REX_OPCODE
);
7317 /* The prefix bytes. */
7318 for (j
= ARRAY_SIZE (i
.prefix
), q
= i
.prefix
; j
> 0; j
--, q
++)
7320 FRAG_APPEND_1_CHAR (*q
);
7324 for (j
= 0, q
= i
.prefix
; j
< ARRAY_SIZE (i
.prefix
); j
++, q
++)
7329 /* REX byte is encoded in VEX prefix. */
7333 FRAG_APPEND_1_CHAR (*q
);
7336 /* There should be no other prefixes for instructions
7341 /* For EVEX instructions i.vrex should become 0 after
7342 build_evex_prefix. For VEX instructions upper 16 registers
7343 aren't available, so VREX should be 0. */
7346 /* Now the VEX prefix. */
7347 p
= frag_more (i
.vex
.length
);
7348 for (j
= 0; j
< i
.vex
.length
; j
++)
7349 p
[j
] = i
.vex
.bytes
[j
];
7352 /* Now the opcode; be careful about word order here! */
7353 if (i
.tm
.opcode_length
== 1)
7355 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
7359 switch (i
.tm
.opcode_length
)
7363 *p
++ = (i
.tm
.base_opcode
>> 24) & 0xff;
7364 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
7368 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
7378 /* Put out high byte first: can't use md_number_to_chars! */
7379 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
7380 *p
= i
.tm
.base_opcode
& 0xff;
7383 /* Now the modrm byte and sib byte (if present). */
7384 if (i
.tm
.opcode_modifier
.modrm
)
7386 FRAG_APPEND_1_CHAR ((i
.rm
.regmem
<< 0
7389 /* If i.rm.regmem == ESP (4)
7390 && i.rm.mode != (Register mode)
7392 ==> need second modrm byte. */
7393 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
7395 && !(i
.base_reg
&& i
.base_reg
->reg_type
.bitfield
.reg16
))
7396 FRAG_APPEND_1_CHAR ((i
.sib
.base
<< 0
7398 | i
.sib
.scale
<< 6));
7401 if (i
.disp_operands
)
7402 output_disp (insn_start_frag
, insn_start_off
);
7405 output_imm (insn_start_frag
, insn_start_off
);
7411 pi ("" /*line*/, &i
);
7413 #endif /* DEBUG386 */
7416 /* Return the size of the displacement operand N. */
7419 disp_size (unsigned int n
)
7423 /* Vec_Disp8 has to be 8bit. */
7424 if (i
.types
[n
].bitfield
.vec_disp8
)
7426 else if (i
.types
[n
].bitfield
.disp64
)
7428 else if (i
.types
[n
].bitfield
.disp8
)
7430 else if (i
.types
[n
].bitfield
.disp16
)
7435 /* Return the size of the immediate operand N. */
7438 imm_size (unsigned int n
)
7441 if (i
.types
[n
].bitfield
.imm64
)
7443 else if (i
.types
[n
].bitfield
.imm8
|| i
.types
[n
].bitfield
.imm8s
)
7445 else if (i
.types
[n
].bitfield
.imm16
)
7451 output_disp (fragS
*insn_start_frag
, offsetT insn_start_off
)
7456 for (n
= 0; n
< i
.operands
; n
++)
7458 if (i
.types
[n
].bitfield
.vec_disp8
7459 || operand_type_check (i
.types
[n
], disp
))
7461 if (i
.op
[n
].disps
->X_op
== O_constant
)
7463 int size
= disp_size (n
);
7464 offsetT val
= i
.op
[n
].disps
->X_add_number
;
7466 if (i
.types
[n
].bitfield
.vec_disp8
)
7468 val
= offset_in_range (val
, size
);
7469 p
= frag_more (size
);
7470 md_number_to_chars (p
, val
, size
);
7474 enum bfd_reloc_code_real reloc_type
;
7475 int size
= disp_size (n
);
7476 int sign
= i
.types
[n
].bitfield
.disp32s
;
7477 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
7480 /* We can't have 8 bit displacement here. */
7481 gas_assert (!i
.types
[n
].bitfield
.disp8
);
7483 /* The PC relative address is computed relative
7484 to the instruction boundary, so in case immediate
7485 fields follows, we need to adjust the value. */
7486 if (pcrel
&& i
.imm_operands
)
7491 for (n1
= 0; n1
< i
.operands
; n1
++)
7492 if (operand_type_check (i
.types
[n1
], imm
))
7494 /* Only one immediate is allowed for PC
7495 relative address. */
7496 gas_assert (sz
== 0);
7498 i
.op
[n
].disps
->X_add_number
-= sz
;
7500 /* We should find the immediate. */
7501 gas_assert (sz
!= 0);
7504 p
= frag_more (size
);
7505 reloc_type
= reloc (size
, pcrel
, sign
, i
.reloc
[n
]);
7507 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
7508 && (((reloc_type
== BFD_RELOC_32
7509 || reloc_type
== BFD_RELOC_X86_64_32S
7510 || (reloc_type
== BFD_RELOC_64
7512 && (i
.op
[n
].disps
->X_op
== O_symbol
7513 || (i
.op
[n
].disps
->X_op
== O_add
7514 && ((symbol_get_value_expression
7515 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
7517 || reloc_type
== BFD_RELOC_32_PCREL
))
7521 if (insn_start_frag
== frag_now
)
7522 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
7527 add
= insn_start_frag
->fr_fix
- insn_start_off
;
7528 for (fr
= insn_start_frag
->fr_next
;
7529 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
7531 add
+= p
- frag_now
->fr_literal
;
7536 reloc_type
= BFD_RELOC_386_GOTPC
;
7537 i
.op
[n
].imms
->X_add_number
+= add
;
7539 else if (reloc_type
== BFD_RELOC_64
)
7540 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
7542 /* Don't do the adjustment for x86-64, as there
7543 the pcrel addressing is relative to the _next_
7544 insn, and that is taken care of in other code. */
7545 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
7547 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
7548 size
, i
.op
[n
].disps
, pcrel
,
7550 /* Check for "call/jmp *mem", "mov mem, %reg",
7551 "test %reg, mem" and "binop mem, %reg" where binop
7552 is one of adc, add, and, cmp, or, sbb, sub, xor
7553 instructions. Always generate R_386_GOT32X for
7554 "sym*GOT" operand in 32-bit mode. */
7555 if ((generate_relax_relocations
7558 && i
.rm
.regmem
== 5))
7560 || (i
.rm
.mode
== 0 && i
.rm
.regmem
== 5))
7561 && ((i
.operands
== 1
7562 && i
.tm
.base_opcode
== 0xff
7563 && (i
.rm
.reg
== 2 || i
.rm
.reg
== 4))
7565 && (i
.tm
.base_opcode
== 0x8b
7566 || i
.tm
.base_opcode
== 0x85
7567 || (i
.tm
.base_opcode
& 0xc7) == 0x03))))
7571 fixP
->fx_tcbit
= i
.rex
!= 0;
7573 && (i
.base_reg
->reg_num
== RegRip
7574 || i
.base_reg
->reg_num
== RegEip
))
7575 fixP
->fx_tcbit2
= 1;
7578 fixP
->fx_tcbit2
= 1;
7586 output_imm (fragS
*insn_start_frag
, offsetT insn_start_off
)
7591 for (n
= 0; n
< i
.operands
; n
++)
7593 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
7594 if (i
.rounding
&& (int) n
== i
.rounding
->operand
)
7597 if (operand_type_check (i
.types
[n
], imm
))
7599 if (i
.op
[n
].imms
->X_op
== O_constant
)
7601 int size
= imm_size (n
);
7604 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
7606 p
= frag_more (size
);
7607 md_number_to_chars (p
, val
, size
);
7611 /* Not absolute_section.
7612 Need a 32-bit fixup (don't support 8bit
7613 non-absolute imms). Try to support other
7615 enum bfd_reloc_code_real reloc_type
;
7616 int size
= imm_size (n
);
7619 if (i
.types
[n
].bitfield
.imm32s
7620 && (i
.suffix
== QWORD_MNEM_SUFFIX
7621 || (!i
.suffix
&& i
.tm
.opcode_modifier
.no_lsuf
)))
7626 p
= frag_more (size
);
7627 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
7629 /* This is tough to explain. We end up with this one if we
7630 * have operands that look like
7631 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
7632 * obtain the absolute address of the GOT, and it is strongly
7633 * preferable from a performance point of view to avoid using
7634 * a runtime relocation for this. The actual sequence of
7635 * instructions often look something like:
7640 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
7642 * The call and pop essentially return the absolute address
7643 * of the label .L66 and store it in %ebx. The linker itself
7644 * will ultimately change the first operand of the addl so
7645 * that %ebx points to the GOT, but to keep things simple, the
7646 * .o file must have this operand set so that it generates not
7647 * the absolute address of .L66, but the absolute address of
7648 * itself. This allows the linker itself simply treat a GOTPC
7649 * relocation as asking for a pcrel offset to the GOT to be
7650 * added in, and the addend of the relocation is stored in the
7651 * operand field for the instruction itself.
7653 * Our job here is to fix the operand so that it would add
7654 * the correct offset so that %ebx would point to itself. The
7655 * thing that is tricky is that .-.L66 will point to the
7656 * beginning of the instruction, so we need to further modify
7657 * the operand so that it will point to itself. There are
7658 * other cases where you have something like:
7660 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
7662 * and here no correction would be required. Internally in
7663 * the assembler we treat operands of this form as not being
7664 * pcrel since the '.' is explicitly mentioned, and I wonder
7665 * whether it would simplify matters to do it this way. Who
7666 * knows. In earlier versions of the PIC patches, the
7667 * pcrel_adjust field was used to store the correction, but
7668 * since the expression is not pcrel, I felt it would be
7669 * confusing to do it this way. */
7671 if ((reloc_type
== BFD_RELOC_32
7672 || reloc_type
== BFD_RELOC_X86_64_32S
7673 || reloc_type
== BFD_RELOC_64
)
7675 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
7676 && (i
.op
[n
].imms
->X_op
== O_symbol
7677 || (i
.op
[n
].imms
->X_op
== O_add
7678 && ((symbol_get_value_expression
7679 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
7684 if (insn_start_frag
== frag_now
)
7685 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
7690 add
= insn_start_frag
->fr_fix
- insn_start_off
;
7691 for (fr
= insn_start_frag
->fr_next
;
7692 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
7694 add
+= p
- frag_now
->fr_literal
;
7698 reloc_type
= BFD_RELOC_386_GOTPC
;
7700 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
7702 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
7703 i
.op
[n
].imms
->X_add_number
+= add
;
7705 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
7706 i
.op
[n
].imms
, 0, reloc_type
);
7712 /* x86_cons_fix_new is called via the expression parsing code when a
7713 reloc is needed. We use this hook to get the correct .got reloc. */
7714 static int cons_sign
= -1;
7717 x86_cons_fix_new (fragS
*frag
, unsigned int off
, unsigned int len
,
7718 expressionS
*exp
, bfd_reloc_code_real_type r
)
7720 r
= reloc (len
, 0, cons_sign
, r
);
7723 if (exp
->X_op
== O_secrel
)
7725 exp
->X_op
= O_symbol
;
7726 r
= BFD_RELOC_32_SECREL
;
7730 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
7733 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
7734 purpose of the `.dc.a' internal pseudo-op. */
7737 x86_address_bytes (void)
7739 if ((stdoutput
->arch_info
->mach
& bfd_mach_x64_32
))
7741 return stdoutput
->arch_info
->bits_per_address
/ 8;
7744 #if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
7746 # define lex_got(reloc, adjust, types) NULL
7748 /* Parse operands of the form
7749 <symbol>@GOTOFF+<nnn>
7750 and similar .plt or .got references.
7752 If we find one, set up the correct relocation in RELOC and copy the
7753 input string, minus the `@GOTOFF' into a malloc'd buffer for
7754 parsing by the calling routine. Return this buffer, and if ADJUST
7755 is non-null set it to the length of the string we removed from the
7756 input line. Otherwise return NULL. */
7758 lex_got (enum bfd_reloc_code_real
*rel
,
7760 i386_operand_type
*types
)
7762 /* Some of the relocations depend on the size of what field is to
7763 be relocated. But in our callers i386_immediate and i386_displacement
7764 we don't yet know the operand size (this will be set by insn
7765 matching). Hence we record the word32 relocation here,
7766 and adjust the reloc according to the real size in reloc(). */
7767 static const struct {
7770 const enum bfd_reloc_code_real rel
[2];
7771 const i386_operand_type types64
;
7773 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7774 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32
,
7776 OPERAND_TYPE_IMM32_64
},
7778 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real
,
7779 BFD_RELOC_X86_64_PLTOFF64
},
7780 OPERAND_TYPE_IMM64
},
7781 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32
,
7782 BFD_RELOC_X86_64_PLT32
},
7783 OPERAND_TYPE_IMM32_32S_DISP32
},
7784 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real
,
7785 BFD_RELOC_X86_64_GOTPLT64
},
7786 OPERAND_TYPE_IMM64_DISP64
},
7787 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF
,
7788 BFD_RELOC_X86_64_GOTOFF64
},
7789 OPERAND_TYPE_IMM64_DISP64
},
7790 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real
,
7791 BFD_RELOC_X86_64_GOTPCREL
},
7792 OPERAND_TYPE_IMM32_32S_DISP32
},
7793 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD
,
7794 BFD_RELOC_X86_64_TLSGD
},
7795 OPERAND_TYPE_IMM32_32S_DISP32
},
7796 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM
,
7797 _dummy_first_bfd_reloc_code_real
},
7798 OPERAND_TYPE_NONE
},
7799 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real
,
7800 BFD_RELOC_X86_64_TLSLD
},
7801 OPERAND_TYPE_IMM32_32S_DISP32
},
7802 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32
,
7803 BFD_RELOC_X86_64_GOTTPOFF
},
7804 OPERAND_TYPE_IMM32_32S_DISP32
},
7805 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32
,
7806 BFD_RELOC_X86_64_TPOFF32
},
7807 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
7808 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE
,
7809 _dummy_first_bfd_reloc_code_real
},
7810 OPERAND_TYPE_NONE
},
7811 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32
,
7812 BFD_RELOC_X86_64_DTPOFF32
},
7813 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
7814 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE
,
7815 _dummy_first_bfd_reloc_code_real
},
7816 OPERAND_TYPE_NONE
},
7817 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE
,
7818 _dummy_first_bfd_reloc_code_real
},
7819 OPERAND_TYPE_NONE
},
7820 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32
,
7821 BFD_RELOC_X86_64_GOT32
},
7822 OPERAND_TYPE_IMM32_32S_64_DISP32
},
7823 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC
,
7824 BFD_RELOC_X86_64_GOTPC32_TLSDESC
},
7825 OPERAND_TYPE_IMM32_32S_DISP32
},
7826 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL
,
7827 BFD_RELOC_X86_64_TLSDESC_CALL
},
7828 OPERAND_TYPE_IMM32_32S_DISP32
},
7833 #if defined (OBJ_MAYBE_ELF)
7838 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
7839 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
7842 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
7844 int len
= gotrel
[j
].len
;
7845 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
7847 if (gotrel
[j
].rel
[object_64bit
] != 0)
7850 char *tmpbuf
, *past_reloc
;
7852 *rel
= gotrel
[j
].rel
[object_64bit
];
7856 if (flag_code
!= CODE_64BIT
)
7858 types
->bitfield
.imm32
= 1;
7859 types
->bitfield
.disp32
= 1;
7862 *types
= gotrel
[j
].types64
;
7865 if (j
!= 0 && GOT_symbol
== NULL
)
7866 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
7868 /* The length of the first part of our input line. */
7869 first
= cp
- input_line_pointer
;
7871 /* The second part goes from after the reloc token until
7872 (and including) an end_of_line char or comma. */
7873 past_reloc
= cp
+ 1 + len
;
7875 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
7877 second
= cp
+ 1 - past_reloc
;
7879 /* Allocate and copy string. The trailing NUL shouldn't
7880 be necessary, but be safe. */
7881 tmpbuf
= XNEWVEC (char, first
+ second
+ 2);
7882 memcpy (tmpbuf
, input_line_pointer
, first
);
7883 if (second
!= 0 && *past_reloc
!= ' ')
7884 /* Replace the relocation token with ' ', so that
7885 errors like foo@GOTOFF1 will be detected. */
7886 tmpbuf
[first
++] = ' ';
7888 /* Increment length by 1 if the relocation token is
7893 memcpy (tmpbuf
+ first
, past_reloc
, second
);
7894 tmpbuf
[first
+ second
] = '\0';
7898 as_bad (_("@%s reloc is not supported with %d-bit output format"),
7899 gotrel
[j
].str
, 1 << (5 + object_64bit
));
7904 /* Might be a symbol version string. Don't as_bad here. */
7913 /* Parse operands of the form
7914 <symbol>@SECREL32+<nnn>
7916 If we find one, set up the correct relocation in RELOC and copy the
7917 input string, minus the `@SECREL32' into a malloc'd buffer for
7918 parsing by the calling routine. Return this buffer, and if ADJUST
7919 is non-null set it to the length of the string we removed from the
7920 input line. Otherwise return NULL.
7922 This function is copied from the ELF version above adjusted for PE targets. */
7925 lex_got (enum bfd_reloc_code_real
*rel ATTRIBUTE_UNUSED
,
7926 int *adjust ATTRIBUTE_UNUSED
,
7927 i386_operand_type
*types
)
7933 const enum bfd_reloc_code_real rel
[2];
7934 const i386_operand_type types64
;
7938 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL
,
7939 BFD_RELOC_32_SECREL
},
7940 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
7946 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
7947 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
7950 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
7952 int len
= gotrel
[j
].len
;
7954 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
7956 if (gotrel
[j
].rel
[object_64bit
] != 0)
7959 char *tmpbuf
, *past_reloc
;
7961 *rel
= gotrel
[j
].rel
[object_64bit
];
7967 if (flag_code
!= CODE_64BIT
)
7969 types
->bitfield
.imm32
= 1;
7970 types
->bitfield
.disp32
= 1;
7973 *types
= gotrel
[j
].types64
;
7976 /* The length of the first part of our input line. */
7977 first
= cp
- input_line_pointer
;
7979 /* The second part goes from after the reloc token until
7980 (and including) an end_of_line char or comma. */
7981 past_reloc
= cp
+ 1 + len
;
7983 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
7985 second
= cp
+ 1 - past_reloc
;
7987 /* Allocate and copy string. The trailing NUL shouldn't
7988 be necessary, but be safe. */
7989 tmpbuf
= XNEWVEC (char, first
+ second
+ 2);
7990 memcpy (tmpbuf
, input_line_pointer
, first
);
7991 if (second
!= 0 && *past_reloc
!= ' ')
7992 /* Replace the relocation token with ' ', so that
7993 errors like foo@SECLREL321 will be detected. */
7994 tmpbuf
[first
++] = ' ';
7995 memcpy (tmpbuf
+ first
, past_reloc
, second
);
7996 tmpbuf
[first
+ second
] = '\0';
8000 as_bad (_("@%s reloc is not supported with %d-bit output format"),
8001 gotrel
[j
].str
, 1 << (5 + object_64bit
));
8006 /* Might be a symbol version string. Don't as_bad here. */
8012 bfd_reloc_code_real_type
8013 x86_cons (expressionS
*exp
, int size
)
8015 bfd_reloc_code_real_type got_reloc
= NO_RELOC
;
8017 intel_syntax
= -intel_syntax
;
8020 if (size
== 4 || (object_64bit
&& size
== 8))
8022 /* Handle @GOTOFF and the like in an expression. */
8024 char *gotfree_input_line
;
8027 save
= input_line_pointer
;
8028 gotfree_input_line
= lex_got (&got_reloc
, &adjust
, NULL
);
8029 if (gotfree_input_line
)
8030 input_line_pointer
= gotfree_input_line
;
8034 if (gotfree_input_line
)
8036 /* expression () has merrily parsed up to the end of line,
8037 or a comma - in the wrong buffer. Transfer how far
8038 input_line_pointer has moved to the right buffer. */
8039 input_line_pointer
= (save
8040 + (input_line_pointer
- gotfree_input_line
)
8042 free (gotfree_input_line
);
8043 if (exp
->X_op
== O_constant
8044 || exp
->X_op
== O_absent
8045 || exp
->X_op
== O_illegal
8046 || exp
->X_op
== O_register
8047 || exp
->X_op
== O_big
)
8049 char c
= *input_line_pointer
;
8050 *input_line_pointer
= 0;
8051 as_bad (_("missing or invalid expression `%s'"), save
);
8052 *input_line_pointer
= c
;
8059 intel_syntax
= -intel_syntax
;
8062 i386_intel_simplify (exp
);
8068 signed_cons (int size
)
8070 if (flag_code
== CODE_64BIT
)
8078 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
8085 if (exp
.X_op
== O_symbol
)
8086 exp
.X_op
= O_secrel
;
8088 emit_expr (&exp
, 4);
8090 while (*input_line_pointer
++ == ',');
8092 input_line_pointer
--;
8093 demand_empty_rest_of_line ();
8097 /* Handle Vector operations. */
8100 check_VecOperations (char *op_string
, char *op_end
)
8102 const reg_entry
*mask
;
8107 && (op_end
== NULL
|| op_string
< op_end
))
8110 if (*op_string
== '{')
8114 /* Check broadcasts. */
8115 if (strncmp (op_string
, "1to", 3) == 0)
8120 goto duplicated_vec_op
;
8123 if (*op_string
== '8')
8124 bcst_type
= BROADCAST_1TO8
;
8125 else if (*op_string
== '4')
8126 bcst_type
= BROADCAST_1TO4
;
8127 else if (*op_string
== '2')
8128 bcst_type
= BROADCAST_1TO2
;
8129 else if (*op_string
== '1'
8130 && *(op_string
+1) == '6')
8132 bcst_type
= BROADCAST_1TO16
;
8137 as_bad (_("Unsupported broadcast: `%s'"), saved
);
8142 broadcast_op
.type
= bcst_type
;
8143 broadcast_op
.operand
= this_operand
;
8144 i
.broadcast
= &broadcast_op
;
8146 /* Check masking operation. */
8147 else if ((mask
= parse_register (op_string
, &end_op
)) != NULL
)
8149 /* k0 can't be used for write mask. */
8150 if (mask
->reg_num
== 0)
8152 as_bad (_("`%s' can't be used for write mask"),
8159 mask_op
.mask
= mask
;
8160 mask_op
.zeroing
= 0;
8161 mask_op
.operand
= this_operand
;
8167 goto duplicated_vec_op
;
8169 i
.mask
->mask
= mask
;
8171 /* Only "{z}" is allowed here. No need to check
8172 zeroing mask explicitly. */
8173 if (i
.mask
->operand
!= this_operand
)
8175 as_bad (_("invalid write mask `%s'"), saved
);
8182 /* Check zeroing-flag for masking operation. */
8183 else if (*op_string
== 'z')
8187 mask_op
.mask
= NULL
;
8188 mask_op
.zeroing
= 1;
8189 mask_op
.operand
= this_operand
;
8194 if (i
.mask
->zeroing
)
8197 as_bad (_("duplicated `%s'"), saved
);
8201 i
.mask
->zeroing
= 1;
8203 /* Only "{%k}" is allowed here. No need to check mask
8204 register explicitly. */
8205 if (i
.mask
->operand
!= this_operand
)
8207 as_bad (_("invalid zeroing-masking `%s'"),
8216 goto unknown_vec_op
;
8218 if (*op_string
!= '}')
8220 as_bad (_("missing `}' in `%s'"), saved
);
8227 /* We don't know this one. */
8228 as_bad (_("unknown vector operation: `%s'"), saved
);
8236 i386_immediate (char *imm_start
)
8238 char *save_input_line_pointer
;
8239 char *gotfree_input_line
;
8242 i386_operand_type types
;
8244 operand_type_set (&types
, ~0);
8246 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
8248 as_bad (_("at most %d immediate operands are allowed"),
8249 MAX_IMMEDIATE_OPERANDS
);
8253 exp
= &im_expressions
[i
.imm_operands
++];
8254 i
.op
[this_operand
].imms
= exp
;
8256 if (is_space_char (*imm_start
))
8259 save_input_line_pointer
= input_line_pointer
;
8260 input_line_pointer
= imm_start
;
8262 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
8263 if (gotfree_input_line
)
8264 input_line_pointer
= gotfree_input_line
;
8266 exp_seg
= expression (exp
);
8270 /* Handle vector operations. */
8271 if (*input_line_pointer
== '{')
8273 input_line_pointer
= check_VecOperations (input_line_pointer
,
8275 if (input_line_pointer
== NULL
)
8279 if (*input_line_pointer
)
8280 as_bad (_("junk `%s' after expression"), input_line_pointer
);
8282 input_line_pointer
= save_input_line_pointer
;
8283 if (gotfree_input_line
)
8285 free (gotfree_input_line
);
8287 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
8288 exp
->X_op
= O_illegal
;
8291 return i386_finalize_immediate (exp_seg
, exp
, types
, imm_start
);
8295 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
8296 i386_operand_type types
, const char *imm_start
)
8298 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_illegal
|| exp
->X_op
== O_big
)
8301 as_bad (_("missing or invalid immediate expression `%s'"),
8305 else if (exp
->X_op
== O_constant
)
8307 /* Size it properly later. */
8308 i
.types
[this_operand
].bitfield
.imm64
= 1;
8309 /* If not 64bit, sign extend val. */
8310 if (flag_code
!= CODE_64BIT
8311 && (exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
8313 = (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
8315 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8316 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
8317 && exp_seg
!= absolute_section
8318 && exp_seg
!= text_section
8319 && exp_seg
!= data_section
8320 && exp_seg
!= bss_section
8321 && exp_seg
!= undefined_section
8322 && !bfd_is_com_section (exp_seg
))
8324 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
8328 else if (!intel_syntax
&& exp_seg
== reg_section
)
8331 as_bad (_("illegal immediate register operand %s"), imm_start
);
8336 /* This is an address. The size of the address will be
8337 determined later, depending on destination register,
8338 suffix, or the default for the section. */
8339 i
.types
[this_operand
].bitfield
.imm8
= 1;
8340 i
.types
[this_operand
].bitfield
.imm16
= 1;
8341 i
.types
[this_operand
].bitfield
.imm32
= 1;
8342 i
.types
[this_operand
].bitfield
.imm32s
= 1;
8343 i
.types
[this_operand
].bitfield
.imm64
= 1;
8344 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
8352 i386_scale (char *scale
)
8355 char *save
= input_line_pointer
;
8357 input_line_pointer
= scale
;
8358 val
= get_absolute_expression ();
8363 i
.log2_scale_factor
= 0;
8366 i
.log2_scale_factor
= 1;
8369 i
.log2_scale_factor
= 2;
8372 i
.log2_scale_factor
= 3;
8376 char sep
= *input_line_pointer
;
8378 *input_line_pointer
= '\0';
8379 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
8381 *input_line_pointer
= sep
;
8382 input_line_pointer
= save
;
8386 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
8388 as_warn (_("scale factor of %d without an index register"),
8389 1 << i
.log2_scale_factor
);
8390 i
.log2_scale_factor
= 0;
8392 scale
= input_line_pointer
;
8393 input_line_pointer
= save
;
8398 i386_displacement (char *disp_start
, char *disp_end
)
8402 char *save_input_line_pointer
;
8403 char *gotfree_input_line
;
8405 i386_operand_type bigdisp
, types
= anydisp
;
8408 if (i
.disp_operands
== MAX_MEMORY_OPERANDS
)
8410 as_bad (_("at most %d displacement operands are allowed"),
8411 MAX_MEMORY_OPERANDS
);
8415 operand_type_set (&bigdisp
, 0);
8416 if ((i
.types
[this_operand
].bitfield
.jumpabsolute
)
8417 || (!current_templates
->start
->opcode_modifier
.jump
8418 && !current_templates
->start
->opcode_modifier
.jumpdword
))
8420 bigdisp
.bitfield
.disp32
= 1;
8421 override
= (i
.prefix
[ADDR_PREFIX
] != 0);
8422 if (flag_code
== CODE_64BIT
)
8426 bigdisp
.bitfield
.disp32s
= 1;
8427 bigdisp
.bitfield
.disp64
= 1;
8430 else if ((flag_code
== CODE_16BIT
) ^ override
)
8432 bigdisp
.bitfield
.disp32
= 0;
8433 bigdisp
.bitfield
.disp16
= 1;
8438 /* For PC-relative branches, the width of the displacement
8439 is dependent upon data size, not address size. */
8440 override
= (i
.prefix
[DATA_PREFIX
] != 0);
8441 if (flag_code
== CODE_64BIT
)
8443 if (override
|| i
.suffix
== WORD_MNEM_SUFFIX
)
8444 bigdisp
.bitfield
.disp16
= 1;
8447 bigdisp
.bitfield
.disp32
= 1;
8448 bigdisp
.bitfield
.disp32s
= 1;
8454 override
= (i
.suffix
== (flag_code
!= CODE_16BIT
8456 : LONG_MNEM_SUFFIX
));
8457 bigdisp
.bitfield
.disp32
= 1;
8458 if ((flag_code
== CODE_16BIT
) ^ override
)
8460 bigdisp
.bitfield
.disp32
= 0;
8461 bigdisp
.bitfield
.disp16
= 1;
8465 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
8468 exp
= &disp_expressions
[i
.disp_operands
];
8469 i
.op
[this_operand
].disps
= exp
;
8471 save_input_line_pointer
= input_line_pointer
;
8472 input_line_pointer
= disp_start
;
8473 END_STRING_AND_SAVE (disp_end
);
8475 #ifndef GCC_ASM_O_HACK
8476 #define GCC_ASM_O_HACK 0
8479 END_STRING_AND_SAVE (disp_end
+ 1);
8480 if (i
.types
[this_operand
].bitfield
.baseIndex
8481 && displacement_string_end
[-1] == '+')
8483 /* This hack is to avoid a warning when using the "o"
8484 constraint within gcc asm statements.
8487 #define _set_tssldt_desc(n,addr,limit,type) \
8488 __asm__ __volatile__ ( \
8490 "movw %w1,2+%0\n\t" \
8492 "movb %b1,4+%0\n\t" \
8493 "movb %4,5+%0\n\t" \
8494 "movb $0,6+%0\n\t" \
8495 "movb %h1,7+%0\n\t" \
8497 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
8499 This works great except that the output assembler ends
8500 up looking a bit weird if it turns out that there is
8501 no offset. You end up producing code that looks like:
8514 So here we provide the missing zero. */
8516 *displacement_string_end
= '0';
8519 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
8520 if (gotfree_input_line
)
8521 input_line_pointer
= gotfree_input_line
;
8523 exp_seg
= expression (exp
);
8526 if (*input_line_pointer
)
8527 as_bad (_("junk `%s' after expression"), input_line_pointer
);
8529 RESTORE_END_STRING (disp_end
+ 1);
8531 input_line_pointer
= save_input_line_pointer
;
8532 if (gotfree_input_line
)
8534 free (gotfree_input_line
);
8536 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
8537 exp
->X_op
= O_illegal
;
8540 ret
= i386_finalize_displacement (exp_seg
, exp
, types
, disp_start
);
8542 RESTORE_END_STRING (disp_end
);
8548 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
8549 i386_operand_type types
, const char *disp_start
)
8551 i386_operand_type bigdisp
;
8554 /* We do this to make sure that the section symbol is in
8555 the symbol table. We will ultimately change the relocation
8556 to be relative to the beginning of the section. */
8557 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
8558 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
8559 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
8561 if (exp
->X_op
!= O_symbol
)
8564 if (S_IS_LOCAL (exp
->X_add_symbol
)
8565 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
8566 && S_GET_SEGMENT (exp
->X_add_symbol
) != expr_section
)
8567 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
8568 exp
->X_op
= O_subtract
;
8569 exp
->X_op_symbol
= GOT_symbol
;
8570 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
8571 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
8572 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
8573 i
.reloc
[this_operand
] = BFD_RELOC_64
;
8575 i
.reloc
[this_operand
] = BFD_RELOC_32
;
8578 else if (exp
->X_op
== O_absent
8579 || exp
->X_op
== O_illegal
8580 || exp
->X_op
== O_big
)
8583 as_bad (_("missing or invalid displacement expression `%s'"),
8588 else if (flag_code
== CODE_64BIT
8589 && !i
.prefix
[ADDR_PREFIX
]
8590 && exp
->X_op
== O_constant
)
8592 /* Since displacement is signed extended to 64bit, don't allow
8593 disp32 and turn off disp32s if they are out of range. */
8594 i
.types
[this_operand
].bitfield
.disp32
= 0;
8595 if (!fits_in_signed_long (exp
->X_add_number
))
8597 i
.types
[this_operand
].bitfield
.disp32s
= 0;
8598 if (i
.types
[this_operand
].bitfield
.baseindex
)
8600 as_bad (_("0x%lx out range of signed 32bit displacement"),
8601 (long) exp
->X_add_number
);
8607 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8608 else if (exp
->X_op
!= O_constant
8609 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
8610 && exp_seg
!= absolute_section
8611 && exp_seg
!= text_section
8612 && exp_seg
!= data_section
8613 && exp_seg
!= bss_section
8614 && exp_seg
!= undefined_section
8615 && !bfd_is_com_section (exp_seg
))
8617 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
8622 /* Check if this is a displacement only operand. */
8623 bigdisp
= i
.types
[this_operand
];
8624 bigdisp
.bitfield
.disp8
= 0;
8625 bigdisp
.bitfield
.disp16
= 0;
8626 bigdisp
.bitfield
.disp32
= 0;
8627 bigdisp
.bitfield
.disp32s
= 0;
8628 bigdisp
.bitfield
.disp64
= 0;
8629 if (operand_type_all_zero (&bigdisp
))
8630 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
8636 /* Make sure the memory operand we've been dealt is valid.
8637 Return 1 on success, 0 on a failure. */
8640 i386_index_check (const char *operand_string
)
8642 const char *kind
= "base/index";
8643 enum flag_code addr_mode
;
8645 if (i
.prefix
[ADDR_PREFIX
])
8646 addr_mode
= flag_code
== CODE_32BIT
? CODE_16BIT
: CODE_32BIT
;
8649 addr_mode
= flag_code
;
8651 #if INFER_ADDR_PREFIX
8652 if (i
.mem_operands
== 0)
8654 /* Infer address prefix from the first memory operand. */
8655 const reg_entry
*addr_reg
= i
.base_reg
;
8657 if (addr_reg
== NULL
)
8658 addr_reg
= i
.index_reg
;
8662 if (addr_reg
->reg_num
== RegEip
8663 || addr_reg
->reg_num
== RegEiz
8664 || addr_reg
->reg_type
.bitfield
.reg32
)
8665 addr_mode
= CODE_32BIT
;
8666 else if (flag_code
!= CODE_64BIT
8667 && addr_reg
->reg_type
.bitfield
.reg16
)
8668 addr_mode
= CODE_16BIT
;
8670 if (addr_mode
!= flag_code
)
8672 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
8674 /* Change the size of any displacement too. At most one
8675 of Disp16 or Disp32 is set.
8676 FIXME. There doesn't seem to be any real need for
8677 separate Disp16 and Disp32 flags. The same goes for
8678 Imm16 and Imm32. Removing them would probably clean
8679 up the code quite a lot. */
8680 if (flag_code
!= CODE_64BIT
8681 && (i
.types
[this_operand
].bitfield
.disp16
8682 || i
.types
[this_operand
].bitfield
.disp32
))
8683 i
.types
[this_operand
]
8684 = operand_type_xor (i
.types
[this_operand
], disp16_32
);
8691 if (current_templates
->start
->opcode_modifier
.isstring
8692 && !current_templates
->start
->opcode_modifier
.immext
8693 && (current_templates
->end
[-1].opcode_modifier
.isstring
8696 /* Memory operands of string insns are special in that they only allow
8697 a single register (rDI, rSI, or rBX) as their memory address. */
8698 const reg_entry
*expected_reg
;
8699 static const char *di_si
[][2] =
8705 static const char *bx
[] = { "ebx", "bx", "rbx" };
8707 kind
= "string address";
8709 if (current_templates
->start
->opcode_modifier
.repprefixok
)
8711 i386_operand_type type
= current_templates
->end
[-1].operand_types
[0];
8713 if (!type
.bitfield
.baseindex
8714 || ((!i
.mem_operands
!= !intel_syntax
)
8715 && current_templates
->end
[-1].operand_types
[1]
8716 .bitfield
.baseindex
))
8717 type
= current_templates
->end
[-1].operand_types
[1];
8718 expected_reg
= hash_find (reg_hash
,
8719 di_si
[addr_mode
][type
.bitfield
.esseg
]);
8723 expected_reg
= hash_find (reg_hash
, bx
[addr_mode
]);
8725 if (i
.base_reg
!= expected_reg
8727 || operand_type_check (i
.types
[this_operand
], disp
))
8729 /* The second memory operand must have the same size as
8733 && !((addr_mode
== CODE_64BIT
8734 && i
.base_reg
->reg_type
.bitfield
.reg64
)
8735 || (addr_mode
== CODE_32BIT
8736 ? i
.base_reg
->reg_type
.bitfield
.reg32
8737 : i
.base_reg
->reg_type
.bitfield
.reg16
)))
8740 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
8742 intel_syntax
? '[' : '(',
8744 expected_reg
->reg_name
,
8745 intel_syntax
? ']' : ')');
8752 as_bad (_("`%s' is not a valid %s expression"),
8753 operand_string
, kind
);
8758 if (addr_mode
!= CODE_16BIT
)
8760 /* 32-bit/64-bit checks. */
8762 && (addr_mode
== CODE_64BIT
8763 ? !i
.base_reg
->reg_type
.bitfield
.reg64
8764 : !i
.base_reg
->reg_type
.bitfield
.reg32
)
8766 || (i
.base_reg
->reg_num
8767 != (addr_mode
== CODE_64BIT
? RegRip
: RegEip
))))
8769 && !i
.index_reg
->reg_type
.bitfield
.regxmm
8770 && !i
.index_reg
->reg_type
.bitfield
.regymm
8771 && !i
.index_reg
->reg_type
.bitfield
.regzmm
8772 && ((addr_mode
== CODE_64BIT
8773 ? !(i
.index_reg
->reg_type
.bitfield
.reg64
8774 || i
.index_reg
->reg_num
== RegRiz
)
8775 : !(i
.index_reg
->reg_type
.bitfield
.reg32
8776 || i
.index_reg
->reg_num
== RegEiz
))
8777 || !i
.index_reg
->reg_type
.bitfield
.baseindex
)))
8780 /* bndmk, bndldx, and bndstx have special restrictions. */
8781 if (current_templates
->start
->base_opcode
== 0xf30f1b
8782 || (current_templates
->start
->base_opcode
& ~1) == 0x0f1a)
8784 /* They cannot use RIP-relative addressing. */
8785 if (i
.base_reg
&& i
.base_reg
->reg_num
== RegRip
)
8787 as_bad (_("`%s' cannot be used here"), operand_string
);
8791 /* bndldx and bndstx ignore their scale factor. */
8792 if (current_templates
->start
->base_opcode
!= 0xf30f1b
8793 && i
.log2_scale_factor
)
8794 as_warn (_("register scaling is being ignored here"));
8799 /* 16-bit checks. */
8801 && (!i
.base_reg
->reg_type
.bitfield
.reg16
8802 || !i
.base_reg
->reg_type
.bitfield
.baseindex
))
8804 && (!i
.index_reg
->reg_type
.bitfield
.reg16
8805 || !i
.index_reg
->reg_type
.bitfield
.baseindex
8807 && i
.base_reg
->reg_num
< 6
8808 && i
.index_reg
->reg_num
>= 6
8809 && i
.log2_scale_factor
== 0))))
8816 /* Handle vector immediates. */
8819 RC_SAE_immediate (const char *imm_start
)
8821 unsigned int match_found
, j
;
8822 const char *pstr
= imm_start
;
8830 for (j
= 0; j
< ARRAY_SIZE (RC_NamesTable
); j
++)
8832 if (!strncmp (pstr
, RC_NamesTable
[j
].name
, RC_NamesTable
[j
].len
))
8836 rc_op
.type
= RC_NamesTable
[j
].type
;
8837 rc_op
.operand
= this_operand
;
8838 i
.rounding
= &rc_op
;
8842 as_bad (_("duplicated `%s'"), imm_start
);
8845 pstr
+= RC_NamesTable
[j
].len
;
8855 as_bad (_("Missing '}': '%s'"), imm_start
);
8858 /* RC/SAE immediate string should contain nothing more. */;
8861 as_bad (_("Junk after '}': '%s'"), imm_start
);
8865 exp
= &im_expressions
[i
.imm_operands
++];
8866 i
.op
[this_operand
].imms
= exp
;
8868 exp
->X_op
= O_constant
;
8869 exp
->X_add_number
= 0;
8870 exp
->X_add_symbol
= (symbolS
*) 0;
8871 exp
->X_op_symbol
= (symbolS
*) 0;
8873 i
.types
[this_operand
].bitfield
.imm8
= 1;
8877 /* Only string instructions can have a second memory operand, so
8878 reduce current_templates to just those if it contains any. */
8880 maybe_adjust_templates (void)
8882 const insn_template
*t
;
8884 gas_assert (i
.mem_operands
== 1);
8886 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
8887 if (t
->opcode_modifier
.isstring
)
8890 if (t
< current_templates
->end
)
8892 static templates aux_templates
;
8893 bfd_boolean recheck
;
8895 aux_templates
.start
= t
;
8896 for (; t
< current_templates
->end
; ++t
)
8897 if (!t
->opcode_modifier
.isstring
)
8899 aux_templates
.end
= t
;
8901 /* Determine whether to re-check the first memory operand. */
8902 recheck
= (aux_templates
.start
!= current_templates
->start
8903 || t
!= current_templates
->end
);
8905 current_templates
= &aux_templates
;
8910 if (i
.memop1_string
!= NULL
8911 && i386_index_check (i
.memop1_string
) == 0)
8920 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
8924 i386_att_operand (char *operand_string
)
8928 char *op_string
= operand_string
;
8930 if (is_space_char (*op_string
))
8933 /* We check for an absolute prefix (differentiating,
8934 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
8935 if (*op_string
== ABSOLUTE_PREFIX
)
8938 if (is_space_char (*op_string
))
8940 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
8943 /* Check if operand is a register. */
8944 if ((r
= parse_register (op_string
, &end_op
)) != NULL
)
8946 i386_operand_type temp
;
8948 /* Check for a segment override by searching for ':' after a
8949 segment register. */
8951 if (is_space_char (*op_string
))
8953 if (*op_string
== ':'
8954 && (r
->reg_type
.bitfield
.sreg2
8955 || r
->reg_type
.bitfield
.sreg3
))
8960 i
.seg
[i
.mem_operands
] = &es
;
8963 i
.seg
[i
.mem_operands
] = &cs
;
8966 i
.seg
[i
.mem_operands
] = &ss
;
8969 i
.seg
[i
.mem_operands
] = &ds
;
8972 i
.seg
[i
.mem_operands
] = &fs
;
8975 i
.seg
[i
.mem_operands
] = &gs
;
8979 /* Skip the ':' and whitespace. */
8981 if (is_space_char (*op_string
))
8984 if (!is_digit_char (*op_string
)
8985 && !is_identifier_char (*op_string
)
8986 && *op_string
!= '('
8987 && *op_string
!= ABSOLUTE_PREFIX
)
8989 as_bad (_("bad memory operand `%s'"), op_string
);
8992 /* Handle case of %es:*foo. */
8993 if (*op_string
== ABSOLUTE_PREFIX
)
8996 if (is_space_char (*op_string
))
8998 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
9000 goto do_memory_reference
;
9003 /* Handle vector operations. */
9004 if (*op_string
== '{')
9006 op_string
= check_VecOperations (op_string
, NULL
);
9007 if (op_string
== NULL
)
9013 as_bad (_("junk `%s' after register"), op_string
);
9017 temp
.bitfield
.baseindex
= 0;
9018 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
9020 i
.types
[this_operand
].bitfield
.unspecified
= 0;
9021 i
.op
[this_operand
].regs
= r
;
9024 else if (*op_string
== REGISTER_PREFIX
)
9026 as_bad (_("bad register name `%s'"), op_string
);
9029 else if (*op_string
== IMMEDIATE_PREFIX
)
9032 if (i
.types
[this_operand
].bitfield
.jumpabsolute
)
9034 as_bad (_("immediate operand illegal with absolute jump"));
9037 if (!i386_immediate (op_string
))
9040 else if (RC_SAE_immediate (operand_string
))
9042 /* If it is a RC or SAE immediate, do nothing. */
9045 else if (is_digit_char (*op_string
)
9046 || is_identifier_char (*op_string
)
9047 || *op_string
== '"'
9048 || *op_string
== '(')
9050 /* This is a memory reference of some sort. */
9053 /* Start and end of displacement string expression (if found). */
9054 char *displacement_string_start
;
9055 char *displacement_string_end
;
9058 do_memory_reference
:
9059 if (i
.mem_operands
== 1 && !maybe_adjust_templates ())
9061 if ((i
.mem_operands
== 1
9062 && !current_templates
->start
->opcode_modifier
.isstring
)
9063 || i
.mem_operands
== 2)
9065 as_bad (_("too many memory references for `%s'"),
9066 current_templates
->start
->name
);
9070 /* Check for base index form. We detect the base index form by
9071 looking for an ')' at the end of the operand, searching
9072 for the '(' matching it, and finding a REGISTER_PREFIX or ','
9074 base_string
= op_string
+ strlen (op_string
);
9076 /* Handle vector operations. */
9077 vop_start
= strchr (op_string
, '{');
9078 if (vop_start
&& vop_start
< base_string
)
9080 if (check_VecOperations (vop_start
, base_string
) == NULL
)
9082 base_string
= vop_start
;
9086 if (is_space_char (*base_string
))
9089 /* If we only have a displacement, set-up for it to be parsed later. */
9090 displacement_string_start
= op_string
;
9091 displacement_string_end
= base_string
+ 1;
9093 if (*base_string
== ')')
9096 unsigned int parens_balanced
= 1;
9097 /* We've already checked that the number of left & right ()'s are
9098 equal, so this loop will not be infinite. */
9102 if (*base_string
== ')')
9104 if (*base_string
== '(')
9107 while (parens_balanced
);
9109 temp_string
= base_string
;
9111 /* Skip past '(' and whitespace. */
9113 if (is_space_char (*base_string
))
9116 if (*base_string
== ','
9117 || ((i
.base_reg
= parse_register (base_string
, &end_op
))
9120 displacement_string_end
= temp_string
;
9122 i
.types
[this_operand
].bitfield
.baseindex
= 1;
9126 base_string
= end_op
;
9127 if (is_space_char (*base_string
))
9131 /* There may be an index reg or scale factor here. */
9132 if (*base_string
== ',')
9135 if (is_space_char (*base_string
))
9138 if ((i
.index_reg
= parse_register (base_string
, &end_op
))
9141 base_string
= end_op
;
9142 if (is_space_char (*base_string
))
9144 if (*base_string
== ',')
9147 if (is_space_char (*base_string
))
9150 else if (*base_string
!= ')')
9152 as_bad (_("expecting `,' or `)' "
9153 "after index register in `%s'"),
9158 else if (*base_string
== REGISTER_PREFIX
)
9160 end_op
= strchr (base_string
, ',');
9163 as_bad (_("bad register name `%s'"), base_string
);
9167 /* Check for scale factor. */
9168 if (*base_string
!= ')')
9170 char *end_scale
= i386_scale (base_string
);
9175 base_string
= end_scale
;
9176 if (is_space_char (*base_string
))
9178 if (*base_string
!= ')')
9180 as_bad (_("expecting `)' "
9181 "after scale factor in `%s'"),
9186 else if (!i
.index_reg
)
9188 as_bad (_("expecting index register or scale factor "
9189 "after `,'; got '%c'"),
9194 else if (*base_string
!= ')')
9196 as_bad (_("expecting `,' or `)' "
9197 "after base register in `%s'"),
9202 else if (*base_string
== REGISTER_PREFIX
)
9204 end_op
= strchr (base_string
, ',');
9207 as_bad (_("bad register name `%s'"), base_string
);
9212 /* If there's an expression beginning the operand, parse it,
9213 assuming displacement_string_start and
9214 displacement_string_end are meaningful. */
9215 if (displacement_string_start
!= displacement_string_end
)
9217 if (!i386_displacement (displacement_string_start
,
9218 displacement_string_end
))
9222 /* Special case for (%dx) while doing input/output op. */
9224 && operand_type_equal (&i
.base_reg
->reg_type
,
9225 ®16_inoutportreg
)
9227 && i
.log2_scale_factor
== 0
9228 && i
.seg
[i
.mem_operands
] == 0
9229 && !operand_type_check (i
.types
[this_operand
], disp
))
9231 i
.types
[this_operand
] = inoutportreg
;
9235 if (i386_index_check (operand_string
) == 0)
9237 i
.types
[this_operand
].bitfield
.mem
= 1;
9238 if (i
.mem_operands
== 0)
9239 i
.memop1_string
= xstrdup (operand_string
);
9244 /* It's not a memory operand; argh! */
9245 as_bad (_("invalid char %s beginning operand %d `%s'"),
9246 output_invalid (*op_string
),
9251 return 1; /* Normal return. */
9254 /* Calculate the maximum variable size (i.e., excluding fr_fix)
9255 that an rs_machine_dependent frag may reach. */
9258 i386_frag_max_var (fragS
*frag
)
9260 /* The only relaxable frags are for jumps.
9261 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
9262 gas_assert (frag
->fr_type
== rs_machine_dependent
);
9263 return TYPE_FROM_RELAX_STATE (frag
->fr_subtype
) == UNCOND_JUMP
? 4 : 5;
9266 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9268 elf_symbol_resolved_in_segment_p (symbolS
*fr_symbol
, offsetT fr_var
)
9270 /* STT_GNU_IFUNC symbol must go through PLT. */
9271 if ((symbol_get_bfdsym (fr_symbol
)->flags
9272 & BSF_GNU_INDIRECT_FUNCTION
) != 0)
9275 if (!S_IS_EXTERNAL (fr_symbol
))
9276 /* Symbol may be weak or local. */
9277 return !S_IS_WEAK (fr_symbol
);
9279 /* Global symbols with non-default visibility can't be preempted. */
9280 if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol
)) != STV_DEFAULT
)
9283 if (fr_var
!= NO_RELOC
)
9284 switch ((enum bfd_reloc_code_real
) fr_var
)
9286 case BFD_RELOC_386_PLT32
:
9287 case BFD_RELOC_X86_64_PLT32
:
9288 /* Symbol with PLT relocation may be preempted. */
9294 /* Global symbols with default visibility in a shared library may be
9295 preempted by another definition. */
9300 /* md_estimate_size_before_relax()
9302 Called just before relax() for rs_machine_dependent frags. The x86
9303 assembler uses these frags to handle variable size jump
9306 Any symbol that is now undefined will not become defined.
9307 Return the correct fr_subtype in the frag.
9308 Return the initial "guess for variable size of frag" to caller.
9309 The guess is actually the growth beyond the fixed part. Whatever
9310 we do to grow the fixed or variable part contributes to our
9314 md_estimate_size_before_relax (fragS
*fragP
, segT segment
)
9316 /* We've already got fragP->fr_subtype right; all we have to do is
9317 check for un-relaxable symbols. On an ELF system, we can't relax
9318 an externally visible symbol, because it may be overridden by a
9320 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
9321 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9323 && !elf_symbol_resolved_in_segment_p (fragP
->fr_symbol
,
9326 #if defined (OBJ_COFF) && defined (TE_PE)
9327 || (OUTPUT_FLAVOR
== bfd_target_coff_flavour
9328 && S_IS_WEAK (fragP
->fr_symbol
))
9332 /* Symbol is undefined in this segment, or we need to keep a
9333 reloc so that weak symbols can be overridden. */
9334 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
9335 enum bfd_reloc_code_real reloc_type
;
9336 unsigned char *opcode
;
9339 if (fragP
->fr_var
!= NO_RELOC
)
9340 reloc_type
= (enum bfd_reloc_code_real
) fragP
->fr_var
;
9342 reloc_type
= BFD_RELOC_16_PCREL
;
9344 reloc_type
= BFD_RELOC_32_PCREL
;
9346 old_fr_fix
= fragP
->fr_fix
;
9347 opcode
= (unsigned char *) fragP
->fr_opcode
;
9349 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
9352 /* Make jmp (0xeb) a (d)word displacement jump. */
9354 fragP
->fr_fix
+= size
;
9355 fix_new (fragP
, old_fr_fix
, size
,
9357 fragP
->fr_offset
, 1,
9363 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
9365 /* Negate the condition, and branch past an
9366 unconditional jump. */
9369 /* Insert an unconditional jump. */
9371 /* We added two extra opcode bytes, and have a two byte
9373 fragP
->fr_fix
+= 2 + 2;
9374 fix_new (fragP
, old_fr_fix
+ 2, 2,
9376 fragP
->fr_offset
, 1,
9383 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
9388 fixP
= fix_new (fragP
, old_fr_fix
, 1,
9390 fragP
->fr_offset
, 1,
9392 fixP
->fx_signed
= 1;
9396 /* This changes the byte-displacement jump 0x7N
9397 to the (d)word-displacement jump 0x0f,0x8N. */
9398 opcode
[1] = opcode
[0] + 0x10;
9399 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
9400 /* We've added an opcode byte. */
9401 fragP
->fr_fix
+= 1 + size
;
9402 fix_new (fragP
, old_fr_fix
+ 1, size
,
9404 fragP
->fr_offset
, 1,
9409 BAD_CASE (fragP
->fr_subtype
);
9413 return fragP
->fr_fix
- old_fr_fix
;
9416 /* Guess size depending on current relax state. Initially the relax
9417 state will correspond to a short jump and we return 1, because
9418 the variable part of the frag (the branch offset) is one byte
9419 long. However, we can relax a section more than once and in that
9420 case we must either set fr_subtype back to the unrelaxed state,
9421 or return the value for the appropriate branch. */
9422 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
9425 /* Called after relax() is finished.
9427 In: Address of frag.
9428 fr_type == rs_machine_dependent.
9429 fr_subtype is what the address relaxed to.
9431 Out: Any fixSs and constants are set up.
9432 Caller will turn frag into a ".space 0". */
9435 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec ATTRIBUTE_UNUSED
,
9438 unsigned char *opcode
;
9439 unsigned char *where_to_put_displacement
= NULL
;
9440 offsetT target_address
;
9441 offsetT opcode_address
;
9442 unsigned int extension
= 0;
9443 offsetT displacement_from_opcode_start
;
9445 opcode
= (unsigned char *) fragP
->fr_opcode
;
9447 /* Address we want to reach in file space. */
9448 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
9450 /* Address opcode resides at in file space. */
9451 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
9453 /* Displacement from opcode start to fill into instruction. */
9454 displacement_from_opcode_start
= target_address
- opcode_address
;
9456 if ((fragP
->fr_subtype
& BIG
) == 0)
9458 /* Don't have to change opcode. */
9459 extension
= 1; /* 1 opcode + 1 displacement */
9460 where_to_put_displacement
= &opcode
[1];
9464 if (no_cond_jump_promotion
9465 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
9466 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
9467 _("long jump required"));
9469 switch (fragP
->fr_subtype
)
9471 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
9472 extension
= 4; /* 1 opcode + 4 displacement */
9474 where_to_put_displacement
= &opcode
[1];
9477 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
9478 extension
= 2; /* 1 opcode + 2 displacement */
9480 where_to_put_displacement
= &opcode
[1];
9483 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
9484 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
9485 extension
= 5; /* 2 opcode + 4 displacement */
9486 opcode
[1] = opcode
[0] + 0x10;
9487 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
9488 where_to_put_displacement
= &opcode
[2];
9491 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
9492 extension
= 3; /* 2 opcode + 2 displacement */
9493 opcode
[1] = opcode
[0] + 0x10;
9494 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
9495 where_to_put_displacement
= &opcode
[2];
9498 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
9503 where_to_put_displacement
= &opcode
[3];
9507 BAD_CASE (fragP
->fr_subtype
);
9512 /* If size if less then four we are sure that the operand fits,
9513 but if it's 4, then it could be that the displacement is larger
9515 if (DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
) == 4
9517 && ((addressT
) (displacement_from_opcode_start
- extension
9518 + ((addressT
) 1 << 31))
9519 > (((addressT
) 2 << 31) - 1)))
9521 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
9522 _("jump target out of range"));
9523 /* Make us emit 0. */
9524 displacement_from_opcode_start
= extension
;
9526 /* Now put displacement after opcode. */
9527 md_number_to_chars ((char *) where_to_put_displacement
,
9528 (valueT
) (displacement_from_opcode_start
- extension
),
9529 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
9530 fragP
->fr_fix
+= extension
;
9533 /* Apply a fixup (fixP) to segment data, once it has been determined
9534 by our caller that we have all the info we need to fix it up.
9536 Parameter valP is the pointer to the value of the bits.
9538 On the 386, immediates, displacements, and data pointers are all in
9539 the same (little-endian) format, so we don't need to care about which
9543 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
9545 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
9546 valueT value
= *valP
;
9548 #if !defined (TE_Mach)
9551 switch (fixP
->fx_r_type
)
9557 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
9560 case BFD_RELOC_X86_64_32S
:
9561 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
9564 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
9567 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
9572 if (fixP
->fx_addsy
!= NULL
9573 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
9574 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
9575 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
9576 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
9577 && !use_rela_relocations
)
9579 /* This is a hack. There should be a better way to handle this.
9580 This covers for the fact that bfd_install_relocation will
9581 subtract the current location (for partial_inplace, PC relative
9582 relocations); see more below. */
9586 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
9589 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
9591 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9594 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
9597 || (symbol_section_p (fixP
->fx_addsy
)
9598 && sym_seg
!= absolute_section
))
9599 && !generic_force_reloc (fixP
))
9601 /* Yes, we add the values in twice. This is because
9602 bfd_install_relocation subtracts them out again. I think
9603 bfd_install_relocation is broken, but I don't dare change
9605 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
9609 #if defined (OBJ_COFF) && defined (TE_PE)
9610 /* For some reason, the PE format does not store a
9611 section address offset for a PC relative symbol. */
9612 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
9613 || S_IS_WEAK (fixP
->fx_addsy
))
9614 value
+= md_pcrel_from (fixP
);
9617 #if defined (OBJ_COFF) && defined (TE_PE)
9618 if (fixP
->fx_addsy
!= NULL
9619 && S_IS_WEAK (fixP
->fx_addsy
)
9620 /* PR 16858: Do not modify weak function references. */
9621 && ! fixP
->fx_pcrel
)
9623 #if !defined (TE_PEP)
9624 /* For x86 PE weak function symbols are neither PC-relative
9625 nor do they set S_IS_FUNCTION. So the only reliable way
9626 to detect them is to check the flags of their containing
9628 if (S_GET_SEGMENT (fixP
->fx_addsy
) != NULL
9629 && S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_CODE
)
9633 value
-= S_GET_VALUE (fixP
->fx_addsy
);
9637 /* Fix a few things - the dynamic linker expects certain values here,
9638 and we must not disappoint it. */
9639 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9640 if (IS_ELF
&& fixP
->fx_addsy
)
9641 switch (fixP
->fx_r_type
)
9643 case BFD_RELOC_386_PLT32
:
9644 case BFD_RELOC_X86_64_PLT32
:
9645 /* Make the jump instruction point to the address of the operand. At
9646 runtime we merely add the offset to the actual PLT entry. */
9650 case BFD_RELOC_386_TLS_GD
:
9651 case BFD_RELOC_386_TLS_LDM
:
9652 case BFD_RELOC_386_TLS_IE_32
:
9653 case BFD_RELOC_386_TLS_IE
:
9654 case BFD_RELOC_386_TLS_GOTIE
:
9655 case BFD_RELOC_386_TLS_GOTDESC
:
9656 case BFD_RELOC_X86_64_TLSGD
:
9657 case BFD_RELOC_X86_64_TLSLD
:
9658 case BFD_RELOC_X86_64_GOTTPOFF
:
9659 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
9660 value
= 0; /* Fully resolved at runtime. No addend. */
9662 case BFD_RELOC_386_TLS_LE
:
9663 case BFD_RELOC_386_TLS_LDO_32
:
9664 case BFD_RELOC_386_TLS_LE_32
:
9665 case BFD_RELOC_X86_64_DTPOFF32
:
9666 case BFD_RELOC_X86_64_DTPOFF64
:
9667 case BFD_RELOC_X86_64_TPOFF32
:
9668 case BFD_RELOC_X86_64_TPOFF64
:
9669 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
9672 case BFD_RELOC_386_TLS_DESC_CALL
:
9673 case BFD_RELOC_X86_64_TLSDESC_CALL
:
9674 value
= 0; /* Fully resolved at runtime. No addend. */
9675 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
9679 case BFD_RELOC_VTABLE_INHERIT
:
9680 case BFD_RELOC_VTABLE_ENTRY
:
9687 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
9689 #endif /* !defined (TE_Mach) */
9691 /* Are we finished with this relocation now? */
9692 if (fixP
->fx_addsy
== NULL
)
9694 #if defined (OBJ_COFF) && defined (TE_PE)
9695 else if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
9698 /* Remember value for tc_gen_reloc. */
9699 fixP
->fx_addnumber
= value
;
9700 /* Clear out the frag for now. */
9704 else if (use_rela_relocations
)
9706 fixP
->fx_no_overflow
= 1;
9707 /* Remember value for tc_gen_reloc. */
9708 fixP
->fx_addnumber
= value
;
9712 md_number_to_chars (p
, value
, fixP
->fx_size
);
9716 md_atof (int type
, char *litP
, int *sizeP
)
9718 /* This outputs the LITTLENUMs in REVERSE order;
9719 in accord with the bigendian 386. */
9720 return ieee_md_atof (type
, litP
, sizeP
, FALSE
);
9723 static char output_invalid_buf
[sizeof (unsigned char) * 2 + 6];
9726 output_invalid (int c
)
9729 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
9732 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
9733 "(0x%x)", (unsigned char) c
);
9734 return output_invalid_buf
;
9737 /* REG_STRING starts *before* REGISTER_PREFIX. */
9739 static const reg_entry
*
9740 parse_real_register (char *reg_string
, char **end_op
)
9742 char *s
= reg_string
;
9744 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
9747 /* Skip possible REGISTER_PREFIX and possible whitespace. */
9748 if (*s
== REGISTER_PREFIX
)
9751 if (is_space_char (*s
))
9755 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
9757 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
9758 return (const reg_entry
*) NULL
;
9762 /* For naked regs, make sure that we are not dealing with an identifier.
9763 This prevents confusing an identifier like `eax_var' with register
9765 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
9766 return (const reg_entry
*) NULL
;
9770 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
9772 /* Handle floating point regs, allowing spaces in the (i) part. */
9773 if (r
== i386_regtab
/* %st is first entry of table */)
9775 if (is_space_char (*s
))
9780 if (is_space_char (*s
))
9782 if (*s
>= '0' && *s
<= '7')
9786 if (is_space_char (*s
))
9791 r
= (const reg_entry
*) hash_find (reg_hash
, "st(0)");
9796 /* We have "%st(" then garbage. */
9797 return (const reg_entry
*) NULL
;
9801 if (r
== NULL
|| allow_pseudo_reg
)
9804 if (operand_type_all_zero (&r
->reg_type
))
9805 return (const reg_entry
*) NULL
;
9807 if ((r
->reg_type
.bitfield
.reg32
9808 || r
->reg_type
.bitfield
.sreg3
9809 || r
->reg_type
.bitfield
.control
9810 || r
->reg_type
.bitfield
.debug
9811 || r
->reg_type
.bitfield
.test
)
9812 && !cpu_arch_flags
.bitfield
.cpui386
)
9813 return (const reg_entry
*) NULL
;
9815 if (r
->reg_type
.bitfield
.floatreg
9816 && !cpu_arch_flags
.bitfield
.cpu8087
9817 && !cpu_arch_flags
.bitfield
.cpu287
9818 && !cpu_arch_flags
.bitfield
.cpu387
)
9819 return (const reg_entry
*) NULL
;
9821 if (r
->reg_type
.bitfield
.regmmx
&& !cpu_arch_flags
.bitfield
.cpuregmmx
)
9822 return (const reg_entry
*) NULL
;
9824 if (r
->reg_type
.bitfield
.regxmm
&& !cpu_arch_flags
.bitfield
.cpuregxmm
)
9825 return (const reg_entry
*) NULL
;
9827 if (r
->reg_type
.bitfield
.regymm
&& !cpu_arch_flags
.bitfield
.cpuregymm
)
9828 return (const reg_entry
*) NULL
;
9830 if (r
->reg_type
.bitfield
.regzmm
&& !cpu_arch_flags
.bitfield
.cpuregzmm
)
9831 return (const reg_entry
*) NULL
;
9833 if (r
->reg_type
.bitfield
.regmask
9834 && !cpu_arch_flags
.bitfield
.cpuregmask
)
9835 return (const reg_entry
*) NULL
;
9837 /* Don't allow fake index register unless allow_index_reg isn't 0. */
9838 if (!allow_index_reg
9839 && (r
->reg_num
== RegEiz
|| r
->reg_num
== RegRiz
))
9840 return (const reg_entry
*) NULL
;
9842 /* Upper 16 vector register is only available with VREX in 64bit
9844 if ((r
->reg_flags
& RegVRex
))
9846 if (i
.vec_encoding
== vex_encoding_default
)
9847 i
.vec_encoding
= vex_encoding_evex
;
9849 if (!cpu_arch_flags
.bitfield
.cpuvrex
9850 || i
.vec_encoding
!= vex_encoding_evex
9851 || flag_code
!= CODE_64BIT
)
9852 return (const reg_entry
*) NULL
;
9855 if (((r
->reg_flags
& (RegRex64
| RegRex
))
9856 || r
->reg_type
.bitfield
.reg64
)
9857 && (!cpu_arch_flags
.bitfield
.cpulm
9858 || !operand_type_equal (&r
->reg_type
, &control
))
9859 && flag_code
!= CODE_64BIT
)
9860 return (const reg_entry
*) NULL
;
9862 if (r
->reg_type
.bitfield
.sreg3
&& r
->reg_num
== RegFlat
&& !intel_syntax
)
9863 return (const reg_entry
*) NULL
;
9868 /* REG_STRING starts *before* REGISTER_PREFIX. */
9870 static const reg_entry
*
9871 parse_register (char *reg_string
, char **end_op
)
9875 if (*reg_string
== REGISTER_PREFIX
|| allow_naked_reg
)
9876 r
= parse_real_register (reg_string
, end_op
);
9881 char *save
= input_line_pointer
;
9885 input_line_pointer
= reg_string
;
9886 c
= get_symbol_name (®_string
);
9887 symbolP
= symbol_find (reg_string
);
9888 if (symbolP
&& S_GET_SEGMENT (symbolP
) == reg_section
)
9890 const expressionS
*e
= symbol_get_value_expression (symbolP
);
9892 know (e
->X_op
== O_register
);
9893 know (e
->X_add_number
>= 0
9894 && (valueT
) e
->X_add_number
< i386_regtab_size
);
9895 r
= i386_regtab
+ e
->X_add_number
;
9896 if ((r
->reg_flags
& RegVRex
))
9897 i
.vec_encoding
= vex_encoding_evex
;
9898 *end_op
= input_line_pointer
;
9900 *input_line_pointer
= c
;
9901 input_line_pointer
= save
;
9907 i386_parse_name (char *name
, expressionS
*e
, char *nextcharP
)
9910 char *end
= input_line_pointer
;
9913 r
= parse_register (name
, &input_line_pointer
);
9914 if (r
&& end
<= input_line_pointer
)
9916 *nextcharP
= *input_line_pointer
;
9917 *input_line_pointer
= 0;
9918 e
->X_op
= O_register
;
9919 e
->X_add_number
= r
- i386_regtab
;
9922 input_line_pointer
= end
;
9924 return intel_syntax
? i386_intel_parse_name (name
, e
) : 0;
9928 md_operand (expressionS
*e
)
9933 switch (*input_line_pointer
)
9935 case REGISTER_PREFIX
:
9936 r
= parse_real_register (input_line_pointer
, &end
);
9939 e
->X_op
= O_register
;
9940 e
->X_add_number
= r
- i386_regtab
;
9941 input_line_pointer
= end
;
9946 gas_assert (intel_syntax
);
9947 end
= input_line_pointer
++;
9949 if (*input_line_pointer
== ']')
9951 ++input_line_pointer
;
9952 e
->X_op_symbol
= make_expr_symbol (e
);
9953 e
->X_add_symbol
= NULL
;
9954 e
->X_add_number
= 0;
9960 input_line_pointer
= end
;
9967 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9968 const char *md_shortopts
= "kVQ:sqn";
9970 const char *md_shortopts
= "qn";
9973 #define OPTION_32 (OPTION_MD_BASE + 0)
9974 #define OPTION_64 (OPTION_MD_BASE + 1)
9975 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
9976 #define OPTION_MARCH (OPTION_MD_BASE + 3)
9977 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
9978 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
9979 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
9980 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
9981 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
9982 #define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
9983 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
9984 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
9985 #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
9986 #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
9987 #define OPTION_X32 (OPTION_MD_BASE + 14)
9988 #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
9989 #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
9990 #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
9991 #define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
9992 #define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
9993 #define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
9994 #define OPTION_MSHARED (OPTION_MD_BASE + 21)
9995 #define OPTION_MAMD64 (OPTION_MD_BASE + 22)
9996 #define OPTION_MINTEL64 (OPTION_MD_BASE + 23)
9997 #define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24)
9998 #define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 25)
10000 struct option md_longopts
[] =
10002 {"32", no_argument
, NULL
, OPTION_32
},
10003 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10004 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
10005 {"64", no_argument
, NULL
, OPTION_64
},
10007 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10008 {"x32", no_argument
, NULL
, OPTION_X32
},
10009 {"mshared", no_argument
, NULL
, OPTION_MSHARED
},
10011 {"divide", no_argument
, NULL
, OPTION_DIVIDE
},
10012 {"march", required_argument
, NULL
, OPTION_MARCH
},
10013 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
10014 {"mmnemonic", required_argument
, NULL
, OPTION_MMNEMONIC
},
10015 {"msyntax", required_argument
, NULL
, OPTION_MSYNTAX
},
10016 {"mindex-reg", no_argument
, NULL
, OPTION_MINDEX_REG
},
10017 {"mnaked-reg", no_argument
, NULL
, OPTION_MNAKED_REG
},
10018 {"mold-gcc", no_argument
, NULL
, OPTION_MOLD_GCC
},
10019 {"msse2avx", no_argument
, NULL
, OPTION_MSSE2AVX
},
10020 {"msse-check", required_argument
, NULL
, OPTION_MSSE_CHECK
},
10021 {"moperand-check", required_argument
, NULL
, OPTION_MOPERAND_CHECK
},
10022 {"mavxscalar", required_argument
, NULL
, OPTION_MAVXSCALAR
},
10023 {"madd-bnd-prefix", no_argument
, NULL
, OPTION_MADD_BND_PREFIX
},
10024 {"mevexlig", required_argument
, NULL
, OPTION_MEVEXLIG
},
10025 {"mevexwig", required_argument
, NULL
, OPTION_MEVEXWIG
},
10026 # if defined (TE_PE) || defined (TE_PEP)
10027 {"mbig-obj", no_argument
, NULL
, OPTION_MBIG_OBJ
},
10029 {"momit-lock-prefix", required_argument
, NULL
, OPTION_MOMIT_LOCK_PREFIX
},
10030 {"mfence-as-lock-add", required_argument
, NULL
, OPTION_MFENCE_AS_LOCK_ADD
},
10031 {"mrelax-relocations", required_argument
, NULL
, OPTION_MRELAX_RELOCATIONS
},
10032 {"mevexrcig", required_argument
, NULL
, OPTION_MEVEXRCIG
},
10033 {"mamd64", no_argument
, NULL
, OPTION_MAMD64
},
10034 {"mintel64", no_argument
, NULL
, OPTION_MINTEL64
},
10035 {NULL
, no_argument
, NULL
, 0}
10037 size_t md_longopts_size
= sizeof (md_longopts
);
10040 md_parse_option (int c
, const char *arg
)
10043 char *arch
, *next
, *saved
;
10048 optimize_align_code
= 0;
10052 quiet_warnings
= 1;
10055 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10056 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
10057 should be emitted or not. FIXME: Not implemented. */
10061 /* -V: SVR4 argument to print version ID. */
10063 print_version_id ();
10066 /* -k: Ignore for FreeBSD compatibility. */
10071 /* -s: On i386 Solaris, this tells the native assembler to use
10072 .stab instead of .stab.excl. We always use .stab anyhow. */
10075 case OPTION_MSHARED
:
10079 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10080 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
10083 const char **list
, **l
;
10085 list
= bfd_target_list ();
10086 for (l
= list
; *l
!= NULL
; l
++)
10087 if (CONST_STRNEQ (*l
, "elf64-x86-64")
10088 || strcmp (*l
, "coff-x86-64") == 0
10089 || strcmp (*l
, "pe-x86-64") == 0
10090 || strcmp (*l
, "pei-x86-64") == 0
10091 || strcmp (*l
, "mach-o-x86-64") == 0)
10093 default_arch
= "x86_64";
10097 as_fatal (_("no compiled in support for x86_64"));
10103 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10107 const char **list
, **l
;
10109 list
= bfd_target_list ();
10110 for (l
= list
; *l
!= NULL
; l
++)
10111 if (CONST_STRNEQ (*l
, "elf32-x86-64"))
10113 default_arch
= "x86_64:32";
10117 as_fatal (_("no compiled in support for 32bit x86_64"));
10121 as_fatal (_("32bit x86_64 is only supported for ELF"));
10126 default_arch
= "i386";
10129 case OPTION_DIVIDE
:
10130 #ifdef SVR4_COMMENT_CHARS
10135 n
= XNEWVEC (char, strlen (i386_comment_chars
) + 1);
10137 for (s
= i386_comment_chars
; *s
!= '\0'; s
++)
10141 i386_comment_chars
= n
;
10147 saved
= xstrdup (arg
);
10149 /* Allow -march=+nosse. */
10155 as_fatal (_("invalid -march= option: `%s'"), arg
);
10156 next
= strchr (arch
, '+');
10159 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
10161 if (strcmp (arch
, cpu_arch
[j
].name
) == 0)
10164 if (! cpu_arch
[j
].flags
.bitfield
.cpui386
)
10167 cpu_arch_name
= cpu_arch
[j
].name
;
10168 cpu_sub_arch_name
= NULL
;
10169 cpu_arch_flags
= cpu_arch
[j
].flags
;
10170 cpu_arch_isa
= cpu_arch
[j
].type
;
10171 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
10172 if (!cpu_arch_tune_set
)
10174 cpu_arch_tune
= cpu_arch_isa
;
10175 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
10179 else if (*cpu_arch
[j
].name
== '.'
10180 && strcmp (arch
, cpu_arch
[j
].name
+ 1) == 0)
10182 /* ISA extension. */
10183 i386_cpu_flags flags
;
10185 flags
= cpu_flags_or (cpu_arch_flags
,
10186 cpu_arch
[j
].flags
);
10188 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
10190 if (cpu_sub_arch_name
)
10192 char *name
= cpu_sub_arch_name
;
10193 cpu_sub_arch_name
= concat (name
,
10195 (const char *) NULL
);
10199 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
10200 cpu_arch_flags
= flags
;
10201 cpu_arch_isa_flags
= flags
;
10207 if (j
>= ARRAY_SIZE (cpu_arch
))
10209 /* Disable an ISA extension. */
10210 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
10211 if (strcmp (arch
, cpu_noarch
[j
].name
) == 0)
10213 i386_cpu_flags flags
;
10215 flags
= cpu_flags_and_not (cpu_arch_flags
,
10216 cpu_noarch
[j
].flags
);
10217 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
10219 if (cpu_sub_arch_name
)
10221 char *name
= cpu_sub_arch_name
;
10222 cpu_sub_arch_name
= concat (arch
,
10223 (const char *) NULL
);
10227 cpu_sub_arch_name
= xstrdup (arch
);
10228 cpu_arch_flags
= flags
;
10229 cpu_arch_isa_flags
= flags
;
10234 if (j
>= ARRAY_SIZE (cpu_noarch
))
10235 j
= ARRAY_SIZE (cpu_arch
);
10238 if (j
>= ARRAY_SIZE (cpu_arch
))
10239 as_fatal (_("invalid -march= option: `%s'"), arg
);
10243 while (next
!= NULL
);
10249 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
10250 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
10252 if (strcmp (arg
, cpu_arch
[j
].name
) == 0)
10254 cpu_arch_tune_set
= 1;
10255 cpu_arch_tune
= cpu_arch
[j
].type
;
10256 cpu_arch_tune_flags
= cpu_arch
[j
].flags
;
10260 if (j
>= ARRAY_SIZE (cpu_arch
))
10261 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
10264 case OPTION_MMNEMONIC
:
10265 if (strcasecmp (arg
, "att") == 0)
10266 intel_mnemonic
= 0;
10267 else if (strcasecmp (arg
, "intel") == 0)
10268 intel_mnemonic
= 1;
10270 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg
);
10273 case OPTION_MSYNTAX
:
10274 if (strcasecmp (arg
, "att") == 0)
10276 else if (strcasecmp (arg
, "intel") == 0)
10279 as_fatal (_("invalid -msyntax= option: `%s'"), arg
);
10282 case OPTION_MINDEX_REG
:
10283 allow_index_reg
= 1;
10286 case OPTION_MNAKED_REG
:
10287 allow_naked_reg
= 1;
10290 case OPTION_MOLD_GCC
:
10294 case OPTION_MSSE2AVX
:
10298 case OPTION_MSSE_CHECK
:
10299 if (strcasecmp (arg
, "error") == 0)
10300 sse_check
= check_error
;
10301 else if (strcasecmp (arg
, "warning") == 0)
10302 sse_check
= check_warning
;
10303 else if (strcasecmp (arg
, "none") == 0)
10304 sse_check
= check_none
;
10306 as_fatal (_("invalid -msse-check= option: `%s'"), arg
);
10309 case OPTION_MOPERAND_CHECK
:
10310 if (strcasecmp (arg
, "error") == 0)
10311 operand_check
= check_error
;
10312 else if (strcasecmp (arg
, "warning") == 0)
10313 operand_check
= check_warning
;
10314 else if (strcasecmp (arg
, "none") == 0)
10315 operand_check
= check_none
;
10317 as_fatal (_("invalid -moperand-check= option: `%s'"), arg
);
10320 case OPTION_MAVXSCALAR
:
10321 if (strcasecmp (arg
, "128") == 0)
10322 avxscalar
= vex128
;
10323 else if (strcasecmp (arg
, "256") == 0)
10324 avxscalar
= vex256
;
10326 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg
);
10329 case OPTION_MADD_BND_PREFIX
:
10330 add_bnd_prefix
= 1;
10333 case OPTION_MEVEXLIG
:
10334 if (strcmp (arg
, "128") == 0)
10335 evexlig
= evexl128
;
10336 else if (strcmp (arg
, "256") == 0)
10337 evexlig
= evexl256
;
10338 else if (strcmp (arg
, "512") == 0)
10339 evexlig
= evexl512
;
10341 as_fatal (_("invalid -mevexlig= option: `%s'"), arg
);
10344 case OPTION_MEVEXRCIG
:
10345 if (strcmp (arg
, "rne") == 0)
10347 else if (strcmp (arg
, "rd") == 0)
10349 else if (strcmp (arg
, "ru") == 0)
10351 else if (strcmp (arg
, "rz") == 0)
10354 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg
);
10357 case OPTION_MEVEXWIG
:
10358 if (strcmp (arg
, "0") == 0)
10360 else if (strcmp (arg
, "1") == 0)
10363 as_fatal (_("invalid -mevexwig= option: `%s'"), arg
);
10366 # if defined (TE_PE) || defined (TE_PEP)
10367 case OPTION_MBIG_OBJ
:
10372 case OPTION_MOMIT_LOCK_PREFIX
:
10373 if (strcasecmp (arg
, "yes") == 0)
10374 omit_lock_prefix
= 1;
10375 else if (strcasecmp (arg
, "no") == 0)
10376 omit_lock_prefix
= 0;
10378 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg
);
10381 case OPTION_MFENCE_AS_LOCK_ADD
:
10382 if (strcasecmp (arg
, "yes") == 0)
10384 else if (strcasecmp (arg
, "no") == 0)
10387 as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg
);
10390 case OPTION_MRELAX_RELOCATIONS
:
10391 if (strcasecmp (arg
, "yes") == 0)
10392 generate_relax_relocations
= 1;
10393 else if (strcasecmp (arg
, "no") == 0)
10394 generate_relax_relocations
= 0;
10396 as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg
);
10399 case OPTION_MAMD64
:
10403 case OPTION_MINTEL64
:
10413 #define MESSAGE_TEMPLATE \
10417 output_message (FILE *stream
, char *p
, char *message
, char *start
,
10418 int *left_p
, const char *name
, int len
)
10420 int size
= sizeof (MESSAGE_TEMPLATE
);
10421 int left
= *left_p
;
10423 /* Reserve 2 spaces for ", " or ",\0" */
10426 /* Check if there is any room. */
10434 p
= mempcpy (p
, name
, len
);
10438 /* Output the current message now and start a new one. */
10441 fprintf (stream
, "%s\n", message
);
10443 left
= size
- (start
- message
) - len
- 2;
10445 gas_assert (left
>= 0);
10447 p
= mempcpy (p
, name
, len
);
10455 show_arch (FILE *stream
, int ext
, int check
)
10457 static char message
[] = MESSAGE_TEMPLATE
;
10458 char *start
= message
+ 27;
10460 int size
= sizeof (MESSAGE_TEMPLATE
);
10467 left
= size
- (start
- message
);
10468 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
10470 /* Should it be skipped? */
10471 if (cpu_arch
[j
].skip
)
10474 name
= cpu_arch
[j
].name
;
10475 len
= cpu_arch
[j
].len
;
10478 /* It is an extension. Skip if we aren't asked to show it. */
10489 /* It is an processor. Skip if we show only extension. */
10492 else if (check
&& ! cpu_arch
[j
].flags
.bitfield
.cpui386
)
10494 /* It is an impossible processor - skip. */
10498 p
= output_message (stream
, p
, message
, start
, &left
, name
, len
);
10501 /* Display disabled extensions. */
10503 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
10505 name
= cpu_noarch
[j
].name
;
10506 len
= cpu_noarch
[j
].len
;
10507 p
= output_message (stream
, p
, message
, start
, &left
, name
,
10512 fprintf (stream
, "%s\n", message
);
10516 md_show_usage (FILE *stream
)
10518 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10519 fprintf (stream
, _("\
10521 -V print assembler version number\n\
10524 fprintf (stream
, _("\
10525 -n Do not optimize code alignment\n\
10526 -q quieten some warnings\n"));
10527 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10528 fprintf (stream
, _("\
10531 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10532 || defined (TE_PE) || defined (TE_PEP))
10533 fprintf (stream
, _("\
10534 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
10536 #ifdef SVR4_COMMENT_CHARS
10537 fprintf (stream
, _("\
10538 --divide do not treat `/' as a comment character\n"));
10540 fprintf (stream
, _("\
10541 --divide ignored\n"));
10543 fprintf (stream
, _("\
10544 -march=CPU[,+EXTENSION...]\n\
10545 generate code for CPU and EXTENSION, CPU is one of:\n"));
10546 show_arch (stream
, 0, 1);
10547 fprintf (stream
, _("\
10548 EXTENSION is combination of:\n"));
10549 show_arch (stream
, 1, 0);
10550 fprintf (stream
, _("\
10551 -mtune=CPU optimize for CPU, CPU is one of:\n"));
10552 show_arch (stream
, 0, 0);
10553 fprintf (stream
, _("\
10554 -msse2avx encode SSE instructions with VEX prefix\n"));
10555 fprintf (stream
, _("\
10556 -msse-check=[none|error|warning]\n\
10557 check SSE instructions\n"));
10558 fprintf (stream
, _("\
10559 -moperand-check=[none|error|warning]\n\
10560 check operand combinations for validity\n"));
10561 fprintf (stream
, _("\
10562 -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n\
10564 fprintf (stream
, _("\
10565 -mevexlig=[128|256|512] encode scalar EVEX instructions with specific vector\n\
10567 fprintf (stream
, _("\
10568 -mevexwig=[0|1] encode EVEX instructions with specific EVEX.W value\n\
10569 for EVEX.W bit ignored instructions\n"));
10570 fprintf (stream
, _("\
10571 -mevexrcig=[rne|rd|ru|rz]\n\
10572 encode EVEX instructions with specific EVEX.RC value\n\
10573 for SAE-only ignored instructions\n"));
10574 fprintf (stream
, _("\
10575 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
10576 fprintf (stream
, _("\
10577 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
10578 fprintf (stream
, _("\
10579 -mindex-reg support pseudo index registers\n"));
10580 fprintf (stream
, _("\
10581 -mnaked-reg don't require `%%' prefix for registers\n"));
10582 fprintf (stream
, _("\
10583 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
10584 fprintf (stream
, _("\
10585 -madd-bnd-prefix add BND prefix for all valid branches\n"));
10586 fprintf (stream
, _("\
10587 -mshared disable branch optimization for shared code\n"));
10588 # if defined (TE_PE) || defined (TE_PEP)
10589 fprintf (stream
, _("\
10590 -mbig-obj generate big object files\n"));
10592 fprintf (stream
, _("\
10593 -momit-lock-prefix=[no|yes]\n\
10594 strip all lock prefixes\n"));
10595 fprintf (stream
, _("\
10596 -mfence-as-lock-add=[no|yes]\n\
10597 encode lfence, mfence and sfence as\n\
10598 lock addl $0x0, (%%{re}sp)\n"));
10599 fprintf (stream
, _("\
10600 -mrelax-relocations=[no|yes]\n\
10601 generate relax relocations\n"));
10602 fprintf (stream
, _("\
10603 -mamd64 accept only AMD64 ISA\n"));
10604 fprintf (stream
, _("\
10605 -mintel64 accept only Intel64 ISA\n"));
10608 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
10609 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10610 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
10612 /* Pick the target format to use. */
10615 i386_target_format (void)
10617 if (!strncmp (default_arch
, "x86_64", 6))
10619 update_code_flag (CODE_64BIT
, 1);
10620 if (default_arch
[6] == '\0')
10621 x86_elf_abi
= X86_64_ABI
;
10623 x86_elf_abi
= X86_64_X32_ABI
;
10625 else if (!strcmp (default_arch
, "i386"))
10626 update_code_flag (CODE_32BIT
, 1);
10627 else if (!strcmp (default_arch
, "iamcu"))
10629 update_code_flag (CODE_32BIT
, 1);
10630 if (cpu_arch_isa
== PROCESSOR_UNKNOWN
)
10632 static const i386_cpu_flags iamcu_flags
= CPU_IAMCU_FLAGS
;
10633 cpu_arch_name
= "iamcu";
10634 cpu_sub_arch_name
= NULL
;
10635 cpu_arch_flags
= iamcu_flags
;
10636 cpu_arch_isa
= PROCESSOR_IAMCU
;
10637 cpu_arch_isa_flags
= iamcu_flags
;
10638 if (!cpu_arch_tune_set
)
10640 cpu_arch_tune
= cpu_arch_isa
;
10641 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
10644 else if (cpu_arch_isa
!= PROCESSOR_IAMCU
)
10645 as_fatal (_("Intel MCU doesn't support `%s' architecture"),
10649 as_fatal (_("unknown architecture"));
10651 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
10652 cpu_arch_isa_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
10653 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
10654 cpu_arch_tune_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
10656 switch (OUTPUT_FLAVOR
)
10658 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
10659 case bfd_target_aout_flavour
:
10660 return AOUT_TARGET_FORMAT
;
10662 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
10663 # if defined (TE_PE) || defined (TE_PEP)
10664 case bfd_target_coff_flavour
:
10665 if (flag_code
== CODE_64BIT
)
10666 return use_big_obj
? "pe-bigobj-x86-64" : "pe-x86-64";
10669 # elif defined (TE_GO32)
10670 case bfd_target_coff_flavour
:
10671 return "coff-go32";
10673 case bfd_target_coff_flavour
:
10674 return "coff-i386";
10677 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
10678 case bfd_target_elf_flavour
:
10680 const char *format
;
10682 switch (x86_elf_abi
)
10685 format
= ELF_TARGET_FORMAT
;
10688 use_rela_relocations
= 1;
10690 format
= ELF_TARGET_FORMAT64
;
10692 case X86_64_X32_ABI
:
10693 use_rela_relocations
= 1;
10695 disallow_64bit_reloc
= 1;
10696 format
= ELF_TARGET_FORMAT32
;
10699 if (cpu_arch_isa
== PROCESSOR_L1OM
)
10701 if (x86_elf_abi
!= X86_64_ABI
)
10702 as_fatal (_("Intel L1OM is 64bit only"));
10703 return ELF_TARGET_L1OM_FORMAT
;
10705 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
10707 if (x86_elf_abi
!= X86_64_ABI
)
10708 as_fatal (_("Intel K1OM is 64bit only"));
10709 return ELF_TARGET_K1OM_FORMAT
;
10711 else if (cpu_arch_isa
== PROCESSOR_IAMCU
)
10713 if (x86_elf_abi
!= I386_ABI
)
10714 as_fatal (_("Intel MCU is 32bit only"));
10715 return ELF_TARGET_IAMCU_FORMAT
;
10721 #if defined (OBJ_MACH_O)
10722 case bfd_target_mach_o_flavour
:
10723 if (flag_code
== CODE_64BIT
)
10725 use_rela_relocations
= 1;
10727 return "mach-o-x86-64";
10730 return "mach-o-i386";
10738 #endif /* OBJ_MAYBE_ more than one */
10741 md_undefined_symbol (char *name
)
10743 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
10744 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
10745 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
10746 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
10750 if (symbol_find (name
))
10751 as_bad (_("GOT already in symbol table"));
10752 GOT_symbol
= symbol_new (name
, undefined_section
,
10753 (valueT
) 0, &zero_address_frag
);
10760 /* Round up a section size to the appropriate boundary. */
10763 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
10765 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
10766 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
10768 /* For a.out, force the section size to be aligned. If we don't do
10769 this, BFD will align it for us, but it will not write out the
10770 final bytes of the section. This may be a bug in BFD, but it is
10771 easier to fix it here since that is how the other a.out targets
10775 align
= bfd_get_section_alignment (stdoutput
, segment
);
10776 size
= ((size
+ (1 << align
) - 1) & (-((valueT
) 1 << align
)));
10783 /* On the i386, PC-relative offsets are relative to the start of the
10784 next instruction. That is, the address of the offset, plus its
10785 size, since the offset is always the last part of the insn. */
10788 md_pcrel_from (fixS
*fixP
)
10790 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
10796 s_bss (int ignore ATTRIBUTE_UNUSED
)
10800 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10802 obj_elf_section_change_hook ();
10804 temp
= get_absolute_expression ();
10805 subseg_set (bss_section
, (subsegT
) temp
);
10806 demand_empty_rest_of_line ();
10812 i386_validate_fix (fixS
*fixp
)
10814 if (fixp
->fx_subsy
)
10816 if (fixp
->fx_subsy
== GOT_symbol
)
10818 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
10822 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10823 if (fixp
->fx_tcbit2
)
10824 fixp
->fx_r_type
= (fixp
->fx_tcbit
10825 ? BFD_RELOC_X86_64_REX_GOTPCRELX
10826 : BFD_RELOC_X86_64_GOTPCRELX
);
10829 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
10834 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
10836 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
10838 fixp
->fx_subsy
= 0;
10841 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10842 else if (!object_64bit
)
10844 if (fixp
->fx_r_type
== BFD_RELOC_386_GOT32
10845 && fixp
->fx_tcbit2
)
10846 fixp
->fx_r_type
= BFD_RELOC_386_GOT32X
;
10852 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
10855 bfd_reloc_code_real_type code
;
10857 switch (fixp
->fx_r_type
)
10859 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10860 case BFD_RELOC_SIZE32
:
10861 case BFD_RELOC_SIZE64
:
10862 if (S_IS_DEFINED (fixp
->fx_addsy
)
10863 && !S_IS_EXTERNAL (fixp
->fx_addsy
))
10865 /* Resolve size relocation against local symbol to size of
10866 the symbol plus addend. */
10867 valueT value
= S_GET_SIZE (fixp
->fx_addsy
) + fixp
->fx_offset
;
10868 if (fixp
->fx_r_type
== BFD_RELOC_SIZE32
10869 && !fits_in_unsigned_long (value
))
10870 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10871 _("symbol size computation overflow"));
10872 fixp
->fx_addsy
= NULL
;
10873 fixp
->fx_subsy
= NULL
;
10874 md_apply_fix (fixp
, (valueT
*) &value
, NULL
);
10878 /* Fall through. */
10880 case BFD_RELOC_X86_64_PLT32
:
10881 case BFD_RELOC_X86_64_GOT32
:
10882 case BFD_RELOC_X86_64_GOTPCREL
:
10883 case BFD_RELOC_X86_64_GOTPCRELX
:
10884 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
10885 case BFD_RELOC_386_PLT32
:
10886 case BFD_RELOC_386_GOT32
:
10887 case BFD_RELOC_386_GOT32X
:
10888 case BFD_RELOC_386_GOTOFF
:
10889 case BFD_RELOC_386_GOTPC
:
10890 case BFD_RELOC_386_TLS_GD
:
10891 case BFD_RELOC_386_TLS_LDM
:
10892 case BFD_RELOC_386_TLS_LDO_32
:
10893 case BFD_RELOC_386_TLS_IE_32
:
10894 case BFD_RELOC_386_TLS_IE
:
10895 case BFD_RELOC_386_TLS_GOTIE
:
10896 case BFD_RELOC_386_TLS_LE_32
:
10897 case BFD_RELOC_386_TLS_LE
:
10898 case BFD_RELOC_386_TLS_GOTDESC
:
10899 case BFD_RELOC_386_TLS_DESC_CALL
:
10900 case BFD_RELOC_X86_64_TLSGD
:
10901 case BFD_RELOC_X86_64_TLSLD
:
10902 case BFD_RELOC_X86_64_DTPOFF32
:
10903 case BFD_RELOC_X86_64_DTPOFF64
:
10904 case BFD_RELOC_X86_64_GOTTPOFF
:
10905 case BFD_RELOC_X86_64_TPOFF32
:
10906 case BFD_RELOC_X86_64_TPOFF64
:
10907 case BFD_RELOC_X86_64_GOTOFF64
:
10908 case BFD_RELOC_X86_64_GOTPC32
:
10909 case BFD_RELOC_X86_64_GOT64
:
10910 case BFD_RELOC_X86_64_GOTPCREL64
:
10911 case BFD_RELOC_X86_64_GOTPC64
:
10912 case BFD_RELOC_X86_64_GOTPLT64
:
10913 case BFD_RELOC_X86_64_PLTOFF64
:
10914 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
10915 case BFD_RELOC_X86_64_TLSDESC_CALL
:
10916 case BFD_RELOC_RVA
:
10917 case BFD_RELOC_VTABLE_ENTRY
:
10918 case BFD_RELOC_VTABLE_INHERIT
:
10920 case BFD_RELOC_32_SECREL
:
10922 code
= fixp
->fx_r_type
;
10924 case BFD_RELOC_X86_64_32S
:
10925 if (!fixp
->fx_pcrel
)
10927 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
10928 code
= fixp
->fx_r_type
;
10931 /* Fall through. */
10933 if (fixp
->fx_pcrel
)
10935 switch (fixp
->fx_size
)
10938 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10939 _("can not do %d byte pc-relative relocation"),
10941 code
= BFD_RELOC_32_PCREL
;
10943 case 1: code
= BFD_RELOC_8_PCREL
; break;
10944 case 2: code
= BFD_RELOC_16_PCREL
; break;
10945 case 4: code
= BFD_RELOC_32_PCREL
; break;
10947 case 8: code
= BFD_RELOC_64_PCREL
; break;
10953 switch (fixp
->fx_size
)
10956 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10957 _("can not do %d byte relocation"),
10959 code
= BFD_RELOC_32
;
10961 case 1: code
= BFD_RELOC_8
; break;
10962 case 2: code
= BFD_RELOC_16
; break;
10963 case 4: code
= BFD_RELOC_32
; break;
10965 case 8: code
= BFD_RELOC_64
; break;
10972 if ((code
== BFD_RELOC_32
10973 || code
== BFD_RELOC_32_PCREL
10974 || code
== BFD_RELOC_X86_64_32S
)
10976 && fixp
->fx_addsy
== GOT_symbol
)
10979 code
= BFD_RELOC_386_GOTPC
;
10981 code
= BFD_RELOC_X86_64_GOTPC32
;
10983 if ((code
== BFD_RELOC_64
|| code
== BFD_RELOC_64_PCREL
)
10985 && fixp
->fx_addsy
== GOT_symbol
)
10987 code
= BFD_RELOC_X86_64_GOTPC64
;
10990 rel
= XNEW (arelent
);
10991 rel
->sym_ptr_ptr
= XNEW (asymbol
*);
10992 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
10994 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
10996 if (!use_rela_relocations
)
10998 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
10999 vtable entry to be used in the relocation's section offset. */
11000 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
11001 rel
->address
= fixp
->fx_offset
;
11002 #if defined (OBJ_COFF) && defined (TE_PE)
11003 else if (fixp
->fx_addsy
&& S_IS_WEAK (fixp
->fx_addsy
))
11004 rel
->addend
= fixp
->fx_addnumber
- (S_GET_VALUE (fixp
->fx_addsy
) * 2);
11009 /* Use the rela in 64bit mode. */
11012 if (disallow_64bit_reloc
)
11015 case BFD_RELOC_X86_64_DTPOFF64
:
11016 case BFD_RELOC_X86_64_TPOFF64
:
11017 case BFD_RELOC_64_PCREL
:
11018 case BFD_RELOC_X86_64_GOTOFF64
:
11019 case BFD_RELOC_X86_64_GOT64
:
11020 case BFD_RELOC_X86_64_GOTPCREL64
:
11021 case BFD_RELOC_X86_64_GOTPC64
:
11022 case BFD_RELOC_X86_64_GOTPLT64
:
11023 case BFD_RELOC_X86_64_PLTOFF64
:
11024 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
11025 _("cannot represent relocation type %s in x32 mode"),
11026 bfd_get_reloc_code_name (code
));
11032 if (!fixp
->fx_pcrel
)
11033 rel
->addend
= fixp
->fx_offset
;
11037 case BFD_RELOC_X86_64_PLT32
:
11038 case BFD_RELOC_X86_64_GOT32
:
11039 case BFD_RELOC_X86_64_GOTPCREL
:
11040 case BFD_RELOC_X86_64_GOTPCRELX
:
11041 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
11042 case BFD_RELOC_X86_64_TLSGD
:
11043 case BFD_RELOC_X86_64_TLSLD
:
11044 case BFD_RELOC_X86_64_GOTTPOFF
:
11045 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
11046 case BFD_RELOC_X86_64_TLSDESC_CALL
:
11047 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
11050 rel
->addend
= (section
->vma
11052 + fixp
->fx_addnumber
11053 + md_pcrel_from (fixp
));
11058 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
11059 if (rel
->howto
== NULL
)
11061 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
11062 _("cannot represent relocation type %s"),
11063 bfd_get_reloc_code_name (code
));
11064 /* Set howto to a garbage value so that we can keep going. */
11065 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
11066 gas_assert (rel
->howto
!= NULL
);
11072 #include "tc-i386-intel.c"
11075 tc_x86_parse_to_dw2regnum (expressionS
*exp
)
11077 int saved_naked_reg
;
11078 char saved_register_dot
;
11080 saved_naked_reg
= allow_naked_reg
;
11081 allow_naked_reg
= 1;
11082 saved_register_dot
= register_chars
['.'];
11083 register_chars
['.'] = '.';
11084 allow_pseudo_reg
= 1;
11085 expression_and_evaluate (exp
);
11086 allow_pseudo_reg
= 0;
11087 register_chars
['.'] = saved_register_dot
;
11088 allow_naked_reg
= saved_naked_reg
;
11090 if (exp
->X_op
== O_register
&& exp
->X_add_number
>= 0)
11092 if ((addressT
) exp
->X_add_number
< i386_regtab_size
)
11094 exp
->X_op
= O_constant
;
11095 exp
->X_add_number
= i386_regtab
[exp
->X_add_number
]
11096 .dw2_regnum
[flag_code
>> 1];
11099 exp
->X_op
= O_illegal
;
11104 tc_x86_frame_initial_instructions (void)
11106 static unsigned int sp_regno
[2];
11108 if (!sp_regno
[flag_code
>> 1])
11110 char *saved_input
= input_line_pointer
;
11111 char sp
[][4] = {"esp", "rsp"};
11114 input_line_pointer
= sp
[flag_code
>> 1];
11115 tc_x86_parse_to_dw2regnum (&exp
);
11116 gas_assert (exp
.X_op
== O_constant
);
11117 sp_regno
[flag_code
>> 1] = exp
.X_add_number
;
11118 input_line_pointer
= saved_input
;
11121 cfi_add_CFA_def_cfa (sp_regno
[flag_code
>> 1], -x86_cie_data_alignment
);
11122 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
11126 x86_dwarf2_addr_size (void)
11128 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
11129 if (x86_elf_abi
== X86_64_X32_ABI
)
11132 return bfd_arch_bits_per_address (stdoutput
) / 8;
11136 i386_elf_section_type (const char *str
, size_t len
)
11138 if (flag_code
== CODE_64BIT
11139 && len
== sizeof ("unwind") - 1
11140 && strncmp (str
, "unwind", 6) == 0)
11141 return SHT_X86_64_UNWIND
;
11148 i386_solaris_fix_up_eh_frame (segT sec
)
11150 if (flag_code
== CODE_64BIT
)
11151 elf_section_type (sec
) = SHT_X86_64_UNWIND
;
11157 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
11161 exp
.X_op
= O_secrel
;
11162 exp
.X_add_symbol
= symbol
;
11163 exp
.X_add_number
= 0;
11164 emit_expr (&exp
, size
);
11168 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11169 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
11172 x86_64_section_letter (int letter
, const char **ptr_msg
)
11174 if (flag_code
== CODE_64BIT
)
11177 return SHF_X86_64_LARGE
;
11179 *ptr_msg
= _("bad .section directive: want a,l,w,x,M,S,G,T in string");
11182 *ptr_msg
= _("bad .section directive: want a,w,x,M,S,G,T in string");
11187 x86_64_section_word (char *str
, size_t len
)
11189 if (len
== 5 && flag_code
== CODE_64BIT
&& CONST_STRNEQ (str
, "large"))
11190 return SHF_X86_64_LARGE
;
11196 handle_large_common (int small ATTRIBUTE_UNUSED
)
11198 if (flag_code
!= CODE_64BIT
)
11200 s_comm_internal (0, elf_common_parse
);
11201 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
11205 static segT lbss_section
;
11206 asection
*saved_com_section_ptr
= elf_com_section_ptr
;
11207 asection
*saved_bss_section
= bss_section
;
11209 if (lbss_section
== NULL
)
11211 flagword applicable
;
11212 segT seg
= now_seg
;
11213 subsegT subseg
= now_subseg
;
11215 /* The .lbss section is for local .largecomm symbols. */
11216 lbss_section
= subseg_new (".lbss", 0);
11217 applicable
= bfd_applicable_section_flags (stdoutput
);
11218 bfd_set_section_flags (stdoutput
, lbss_section
,
11219 applicable
& SEC_ALLOC
);
11220 seg_info (lbss_section
)->bss
= 1;
11222 subseg_set (seg
, subseg
);
11225 elf_com_section_ptr
= &_bfd_elf_large_com_section
;
11226 bss_section
= lbss_section
;
11228 s_comm_internal (0, elf_common_parse
);
11230 elf_com_section_ptr
= saved_com_section_ptr
;
11231 bss_section
= saved_bss_section
;
11234 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */