1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright (C) 1989-2017 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 /* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
23 x86_64 support by Jan Hubicka (jh@suse.cz)
24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
29 #include "safe-ctype.h"
31 #include "dwarf2dbg.h"
32 #include "dw2gencfi.h"
33 #include "elf/x86-64.h"
34 #include "opcodes/i386-init.h"
36 #ifndef REGISTER_WARNINGS
37 #define REGISTER_WARNINGS 1
40 #ifndef INFER_ADDR_PREFIX
41 #define INFER_ADDR_PREFIX 1
45 #define DEFAULT_ARCH "i386"
50 #define INLINE __inline__
56 /* Prefixes will be emitted in the order defined below.
57 WAIT_PREFIX must be the first prefix since FWAIT is really is an
58 instruction, and so must come before any prefixes.
59 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
60 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
66 #define HLE_PREFIX REP_PREFIX
67 #define BND_PREFIX REP_PREFIX
69 #define REX_PREFIX 6 /* must come last. */
70 #define MAX_PREFIXES 7 /* max prefixes per opcode */
72 /* we define the syntax here (modulo base,index,scale syntax) */
73 #define REGISTER_PREFIX '%'
74 #define IMMEDIATE_PREFIX '$'
75 #define ABSOLUTE_PREFIX '*'
77 /* these are the instruction mnemonic suffixes in AT&T syntax or
78 memory operand size in Intel syntax. */
79 #define WORD_MNEM_SUFFIX 'w'
80 #define BYTE_MNEM_SUFFIX 'b'
81 #define SHORT_MNEM_SUFFIX 's'
82 #define LONG_MNEM_SUFFIX 'l'
83 #define QWORD_MNEM_SUFFIX 'q'
84 #define XMMWORD_MNEM_SUFFIX 'x'
85 #define YMMWORD_MNEM_SUFFIX 'y'
86 #define ZMMWORD_MNEM_SUFFIX 'z'
87 /* Intel Syntax. Use a non-ascii letter since since it never appears
89 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
91 #define END_OF_INSN '\0'
94 'templates' is for grouping together 'template' structures for opcodes
95 of the same name. This is only used for storing the insns in the grand
96 ole hash table of insns.
97 The templates themselves start at START and range up to (but not including)
102 const insn_template
*start
;
103 const insn_template
*end
;
107 /* 386 operand encoding bytes: see 386 book for details of this. */
110 unsigned int regmem
; /* codes register or memory operand */
111 unsigned int reg
; /* codes register operand (or extended opcode) */
112 unsigned int mode
; /* how to interpret regmem & reg */
116 /* x86-64 extension prefix. */
117 typedef int rex_byte
;
119 /* 386 opcode byte to code indirect addressing. */
128 /* x86 arch names, types and features */
131 const char *name
; /* arch name */
132 unsigned int len
; /* arch string length */
133 enum processor_type type
; /* arch type */
134 i386_cpu_flags flags
; /* cpu feature flags */
135 unsigned int skip
; /* show_arch should skip this. */
139 /* Used to turn off indicated flags. */
142 const char *name
; /* arch name */
143 unsigned int len
; /* arch string length */
144 i386_cpu_flags flags
; /* cpu feature flags */
148 static void update_code_flag (int, int);
149 static void set_code_flag (int);
150 static void set_16bit_gcc_code_flag (int);
151 static void set_intel_syntax (int);
152 static void set_intel_mnemonic (int);
153 static void set_allow_index_reg (int);
154 static void set_check (int);
155 static void set_cpu_arch (int);
157 static void pe_directive_secrel (int);
159 static void signed_cons (int);
160 static char *output_invalid (int c
);
161 static int i386_finalize_immediate (segT
, expressionS
*, i386_operand_type
,
163 static int i386_finalize_displacement (segT
, expressionS
*, i386_operand_type
,
165 static int i386_att_operand (char *);
166 static int i386_intel_operand (char *, int);
167 static int i386_intel_simplify (expressionS
*);
168 static int i386_intel_parse_name (const char *, expressionS
*);
169 static const reg_entry
*parse_register (char *, char **);
170 static char *parse_insn (char *, char *);
171 static char *parse_operands (char *, const char *);
172 static void swap_operands (void);
173 static void swap_2_operands (int, int);
174 static void optimize_imm (void);
175 static void optimize_disp (void);
176 static const insn_template
*match_template (char);
177 static int check_string (void);
178 static int process_suffix (void);
179 static int check_byte_reg (void);
180 static int check_long_reg (void);
181 static int check_qword_reg (void);
182 static int check_word_reg (void);
183 static int finalize_imm (void);
184 static int process_operands (void);
185 static const seg_entry
*build_modrm_byte (void);
186 static void output_insn (void);
187 static void output_imm (fragS
*, offsetT
);
188 static void output_disp (fragS
*, offsetT
);
190 static void s_bss (int);
192 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
193 static void handle_large_common (int small ATTRIBUTE_UNUSED
);
196 static const char *default_arch
= DEFAULT_ARCH
;
198 /* This struct describes rounding control and SAE in the instruction. */
212 static struct RC_Operation rc_op
;
214 /* The struct describes masking, applied to OPERAND in the instruction.
215 MASK is a pointer to the corresponding mask register. ZEROING tells
216 whether merging or zeroing mask is used. */
217 struct Mask_Operation
219 const reg_entry
*mask
;
220 unsigned int zeroing
;
221 /* The operand where this operation is associated. */
225 static struct Mask_Operation mask_op
;
227 /* The struct describes broadcasting, applied to OPERAND. FACTOR is
229 struct Broadcast_Operation
231 /* Type of broadcast: no broadcast, {1to8}, or {1to16}. */
234 /* Index of broadcasted operand. */
238 static struct Broadcast_Operation broadcast_op
;
243 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
244 unsigned char bytes
[4];
246 /* Destination or source register specifier. */
247 const reg_entry
*register_specifier
;
250 /* 'md_assemble ()' gathers together information and puts it into a
257 const reg_entry
*regs
;
262 operand_size_mismatch
,
263 operand_type_mismatch
,
264 register_type_mismatch
,
265 number_of_operands_mismatch
,
266 invalid_instruction_suffix
,
269 unsupported_with_intel_mnemonic
,
272 invalid_vsib_address
,
273 invalid_vector_register_set
,
274 unsupported_vector_index_register
,
275 unsupported_broadcast
,
276 broadcast_not_on_src_operand
,
279 mask_not_on_destination
,
282 rc_sae_operand_not_last_imm
,
283 invalid_register_operand
,
289 /* TM holds the template for the insn were currently assembling. */
292 /* SUFFIX holds the instruction size suffix for byte, word, dword
293 or qword, if given. */
296 /* OPERANDS gives the number of given operands. */
297 unsigned int operands
;
299 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
300 of given register, displacement, memory operands and immediate
302 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
304 /* TYPES [i] is the type (see above #defines) which tells us how to
305 use OP[i] for the corresponding operand. */
306 i386_operand_type types
[MAX_OPERANDS
];
308 /* Displacement expression, immediate expression, or register for each
310 union i386_op op
[MAX_OPERANDS
];
312 /* Flags for operands. */
313 unsigned int flags
[MAX_OPERANDS
];
314 #define Operand_PCrel 1
316 /* Relocation type for operand */
317 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
319 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
320 the base index byte below. */
321 const reg_entry
*base_reg
;
322 const reg_entry
*index_reg
;
323 unsigned int log2_scale_factor
;
325 /* SEG gives the seg_entries of this insn. They are zero unless
326 explicit segment overrides are given. */
327 const seg_entry
*seg
[2];
329 /* Copied first memory operand string, for re-checking. */
332 /* PREFIX holds all the given prefix opcodes (usually null).
333 PREFIXES is the number of prefix opcodes. */
334 unsigned int prefixes
;
335 unsigned char prefix
[MAX_PREFIXES
];
337 /* RM and SIB are the modrm byte and the sib byte where the
338 addressing modes of this insn are encoded. */
345 /* Masking attributes. */
346 struct Mask_Operation
*mask
;
348 /* Rounding control and SAE attributes. */
349 struct RC_Operation
*rounding
;
351 /* Broadcasting attributes. */
352 struct Broadcast_Operation
*broadcast
;
354 /* Compressed disp8*N attribute. */
355 unsigned int memshift
;
357 /* Swap operand in encoding. */
358 unsigned int swap_operand
;
360 /* Prefer 8bit or 32bit displacement in encoding. */
363 disp_encoding_default
= 0,
369 const char *rep_prefix
;
372 const char *hle_prefix
;
374 /* Have BND prefix. */
375 const char *bnd_prefix
;
377 /* Need VREX to support upper 16 registers. */
381 enum i386_error error
;
384 typedef struct _i386_insn i386_insn
;
386 /* Link RC type with corresponding string, that'll be looked for in
395 static const struct RC_name RC_NamesTable
[] =
397 { rne
, STRING_COMMA_LEN ("rn-sae") },
398 { rd
, STRING_COMMA_LEN ("rd-sae") },
399 { ru
, STRING_COMMA_LEN ("ru-sae") },
400 { rz
, STRING_COMMA_LEN ("rz-sae") },
401 { saeonly
, STRING_COMMA_LEN ("sae") },
404 /* List of chars besides those in app.c:symbol_chars that can start an
405 operand. Used to prevent the scrubber eating vital white-space. */
406 const char extra_symbol_chars
[] = "*%-([{"
415 #if (defined (TE_I386AIX) \
416 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
417 && !defined (TE_GNU) \
418 && !defined (TE_LINUX) \
419 && !defined (TE_NACL) \
420 && !defined (TE_NETWARE) \
421 && !defined (TE_FreeBSD) \
422 && !defined (TE_DragonFly) \
423 && !defined (TE_NetBSD)))
424 /* This array holds the chars that always start a comment. If the
425 pre-processor is disabled, these aren't very useful. The option
426 --divide will remove '/' from this list. */
427 const char *i386_comment_chars
= "#/";
428 #define SVR4_COMMENT_CHARS 1
429 #define PREFIX_SEPARATOR '\\'
432 const char *i386_comment_chars
= "#";
433 #define PREFIX_SEPARATOR '/'
436 /* This array holds the chars that only start a comment at the beginning of
437 a line. If the line seems to have the form '# 123 filename'
438 .line and .file directives will appear in the pre-processed output.
439 Note that input_file.c hand checks for '#' at the beginning of the
440 first line of the input file. This is because the compiler outputs
441 #NO_APP at the beginning of its output.
442 Also note that comments started like this one will always work if
443 '/' isn't otherwise defined. */
444 const char line_comment_chars
[] = "#/";
446 const char line_separator_chars
[] = ";";
448 /* Chars that can be used to separate mant from exp in floating point
450 const char EXP_CHARS
[] = "eE";
452 /* Chars that mean this number is a floating point constant
455 const char FLT_CHARS
[] = "fFdDxX";
457 /* Tables for lexical analysis. */
458 static char mnemonic_chars
[256];
459 static char register_chars
[256];
460 static char operand_chars
[256];
461 static char identifier_chars
[256];
462 static char digit_chars
[256];
464 /* Lexical macros. */
465 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
466 #define is_operand_char(x) (operand_chars[(unsigned char) x])
467 #define is_register_char(x) (register_chars[(unsigned char) x])
468 #define is_space_char(x) ((x) == ' ')
469 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
470 #define is_digit_char(x) (digit_chars[(unsigned char) x])
472 /* All non-digit non-letter characters that may occur in an operand. */
473 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
475 /* md_assemble() always leaves the strings it's passed unaltered. To
476 effect this we maintain a stack of saved characters that we've smashed
477 with '\0's (indicating end of strings for various sub-fields of the
478 assembler instruction). */
479 static char save_stack
[32];
480 static char *save_stack_p
;
481 #define END_STRING_AND_SAVE(s) \
482 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
483 #define RESTORE_END_STRING(s) \
484 do { *(s) = *--save_stack_p; } while (0)
486 /* The instruction we're assembling. */
489 /* Possible templates for current insn. */
490 static const templates
*current_templates
;
492 /* Per instruction expressionS buffers: max displacements & immediates. */
493 static expressionS disp_expressions
[MAX_MEMORY_OPERANDS
];
494 static expressionS im_expressions
[MAX_IMMEDIATE_OPERANDS
];
496 /* Current operand we are working on. */
497 static int this_operand
= -1;
499 /* We support four different modes. FLAG_CODE variable is used to distinguish
507 static enum flag_code flag_code
;
508 static unsigned int object_64bit
;
509 static unsigned int disallow_64bit_reloc
;
510 static int use_rela_relocations
= 0;
512 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
513 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
514 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
516 /* The ELF ABI to use. */
524 static enum x86_elf_abi x86_elf_abi
= I386_ABI
;
527 #if defined (TE_PE) || defined (TE_PEP)
528 /* Use big object file format. */
529 static int use_big_obj
= 0;
532 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
533 /* 1 if generating code for a shared library. */
534 static int shared
= 0;
537 /* 1 for intel syntax,
539 static int intel_syntax
= 0;
541 /* 1 for Intel64 ISA,
545 /* 1 for intel mnemonic,
546 0 if att mnemonic. */
547 static int intel_mnemonic
= !SYSV386_COMPAT
;
549 /* 1 if support old (<= 2.8.1) versions of gcc. */
550 static int old_gcc
= OLDGCC_COMPAT
;
552 /* 1 if pseudo registers are permitted. */
553 static int allow_pseudo_reg
= 0;
555 /* 1 if register prefix % not required. */
556 static int allow_naked_reg
= 0;
558 /* 1 if the assembler should add BND prefix for all control-transferring
559 instructions supporting it, even if this prefix wasn't specified
561 static int add_bnd_prefix
= 0;
563 /* 1 if pseudo index register, eiz/riz, is allowed . */
564 static int allow_index_reg
= 0;
566 /* 1 if the assembler should ignore LOCK prefix, even if it was
567 specified explicitly. */
568 static int omit_lock_prefix
= 0;
570 /* 1 if the assembler should encode lfence, mfence, and sfence as
571 "lock addl $0, (%{re}sp)". */
572 static int avoid_fence
= 0;
574 /* 1 if the assembler should generate relax relocations. */
576 static int generate_relax_relocations
577 = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS
;
579 static enum check_kind
585 sse_check
, operand_check
= check_warning
;
587 /* Register prefix used for error message. */
588 static const char *register_prefix
= "%";
590 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
591 leave, push, and pop instructions so that gcc has the same stack
592 frame as in 32 bit mode. */
593 static char stackop_size
= '\0';
595 /* Non-zero to optimize code alignment. */
596 int optimize_align_code
= 1;
598 /* Non-zero to quieten some warnings. */
599 static int quiet_warnings
= 0;
602 static const char *cpu_arch_name
= NULL
;
603 static char *cpu_sub_arch_name
= NULL
;
605 /* CPU feature flags. */
606 static i386_cpu_flags cpu_arch_flags
= CPU_UNKNOWN_FLAGS
;
608 /* If we have selected a cpu we are generating instructions for. */
609 static int cpu_arch_tune_set
= 0;
611 /* Cpu we are generating instructions for. */
612 enum processor_type cpu_arch_tune
= PROCESSOR_UNKNOWN
;
614 /* CPU feature flags of cpu we are generating instructions for. */
615 static i386_cpu_flags cpu_arch_tune_flags
;
617 /* CPU instruction set architecture used. */
618 enum processor_type cpu_arch_isa
= PROCESSOR_UNKNOWN
;
620 /* CPU feature flags of instruction set architecture used. */
621 i386_cpu_flags cpu_arch_isa_flags
;
623 /* If set, conditional jumps are not automatically promoted to handle
624 larger than a byte offset. */
625 static unsigned int no_cond_jump_promotion
= 0;
627 /* Encode SSE instructions with VEX prefix. */
628 static unsigned int sse2avx
;
630 /* Encode scalar AVX instructions with specific vector length. */
637 /* Encode scalar EVEX LIG instructions with specific vector length. */
645 /* Encode EVEX WIG instructions with specific evex.w. */
652 /* Value to encode in EVEX RC bits, for SAE-only instructions. */
653 static enum rc_type evexrcig
= rne
;
655 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
656 static symbolS
*GOT_symbol
;
658 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
659 unsigned int x86_dwarf2_return_column
;
661 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
662 int x86_cie_data_alignment
;
664 /* Interface to relax_segment.
665 There are 3 major relax states for 386 jump insns because the
666 different types of jumps add different sizes to frags when we're
667 figuring out what sort of jump to choose to reach a given label. */
670 #define UNCOND_JUMP 0
672 #define COND_JUMP86 2
677 #define SMALL16 (SMALL | CODE16)
679 #define BIG16 (BIG | CODE16)
683 #define INLINE __inline__
689 #define ENCODE_RELAX_STATE(type, size) \
690 ((relax_substateT) (((type) << 2) | (size)))
691 #define TYPE_FROM_RELAX_STATE(s) \
693 #define DISP_SIZE_FROM_RELAX_STATE(s) \
694 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
696 /* This table is used by relax_frag to promote short jumps to long
697 ones where necessary. SMALL (short) jumps may be promoted to BIG
698 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
699 don't allow a short jump in a 32 bit code segment to be promoted to
700 a 16 bit offset jump because it's slower (requires data size
701 prefix), and doesn't work, unless the destination is in the bottom
702 64k of the code segment (The top 16 bits of eip are zeroed). */
704 const relax_typeS md_relax_table
[] =
707 1) most positive reach of this state,
708 2) most negative reach of this state,
709 3) how many bytes this mode will have in the variable part of the frag
710 4) which index into the table to try if we can't fit into this one. */
712 /* UNCOND_JUMP states. */
713 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
714 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
715 /* dword jmp adds 4 bytes to frag:
716 0 extra opcode bytes, 4 displacement bytes. */
718 /* word jmp adds 2 byte2 to frag:
719 0 extra opcode bytes, 2 displacement bytes. */
722 /* COND_JUMP states. */
723 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
724 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
725 /* dword conditionals adds 5 bytes to frag:
726 1 extra opcode byte, 4 displacement bytes. */
728 /* word conditionals add 3 bytes to frag:
729 1 extra opcode byte, 2 displacement bytes. */
732 /* COND_JUMP86 states. */
733 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
734 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
735 /* dword conditionals adds 5 bytes to frag:
736 1 extra opcode byte, 4 displacement bytes. */
738 /* word conditionals add 4 bytes to frag:
739 1 displacement byte and a 3 byte long branch insn. */
743 static const arch_entry cpu_arch
[] =
745 /* Do not replace the first two entries - i386_target_format()
746 relies on them being there in this order. */
747 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32
,
748 CPU_GENERIC32_FLAGS
, 0 },
749 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64
,
750 CPU_GENERIC64_FLAGS
, 0 },
751 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN
,
753 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN
,
755 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN
,
757 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386
,
759 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486
,
761 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM
,
763 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO
,
765 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM
,
767 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO
,
768 CPU_PENTIUMPRO_FLAGS
, 0 },
769 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO
,
771 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO
,
773 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4
,
775 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA
,
777 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA
,
778 CPU_NOCONA_FLAGS
, 0 },
779 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE
,
781 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE
,
783 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2
,
784 CPU_CORE2_FLAGS
, 1 },
785 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2
,
786 CPU_CORE2_FLAGS
, 0 },
787 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7
,
788 CPU_COREI7_FLAGS
, 0 },
789 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM
,
791 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM
,
793 { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU
,
794 CPU_IAMCU_FLAGS
, 0 },
795 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6
,
797 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6
,
799 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON
,
800 CPU_ATHLON_FLAGS
, 0 },
801 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8
,
803 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8
,
805 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8
,
807 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10
,
808 CPU_AMDFAM10_FLAGS
, 0 },
809 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD
,
810 CPU_BDVER1_FLAGS
, 0 },
811 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD
,
812 CPU_BDVER2_FLAGS
, 0 },
813 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD
,
814 CPU_BDVER3_FLAGS
, 0 },
815 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD
,
816 CPU_BDVER4_FLAGS
, 0 },
817 { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER
,
818 CPU_ZNVER1_FLAGS
, 0 },
819 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT
,
820 CPU_BTVER1_FLAGS
, 0 },
821 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT
,
822 CPU_BTVER2_FLAGS
, 0 },
823 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN
,
825 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN
,
827 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN
,
829 { STRING_COMMA_LEN (".687"), PROCESSOR_UNKNOWN
,
831 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN
,
833 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN
,
835 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN
,
837 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN
,
839 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN
,
840 CPU_SSSE3_FLAGS
, 0 },
841 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN
,
842 CPU_SSE4_1_FLAGS
, 0 },
843 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN
,
844 CPU_SSE4_2_FLAGS
, 0 },
845 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN
,
846 CPU_SSE4_2_FLAGS
, 0 },
847 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN
,
849 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN
,
851 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN
,
852 CPU_AVX512F_FLAGS
, 0 },
853 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN
,
854 CPU_AVX512CD_FLAGS
, 0 },
855 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN
,
856 CPU_AVX512ER_FLAGS
, 0 },
857 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN
,
858 CPU_AVX512PF_FLAGS
, 0 },
859 { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN
,
860 CPU_AVX512DQ_FLAGS
, 0 },
861 { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN
,
862 CPU_AVX512BW_FLAGS
, 0 },
863 { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN
,
864 CPU_AVX512VL_FLAGS
, 0 },
865 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN
,
867 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN
,
868 CPU_VMFUNC_FLAGS
, 0 },
869 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN
,
871 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN
,
872 CPU_XSAVE_FLAGS
, 0 },
873 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN
,
874 CPU_XSAVEOPT_FLAGS
, 0 },
875 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN
,
876 CPU_XSAVEC_FLAGS
, 0 },
877 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN
,
878 CPU_XSAVES_FLAGS
, 0 },
879 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN
,
881 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN
,
882 CPU_PCLMUL_FLAGS
, 0 },
883 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN
,
884 CPU_PCLMUL_FLAGS
, 1 },
885 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN
,
886 CPU_FSGSBASE_FLAGS
, 0 },
887 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN
,
888 CPU_RDRND_FLAGS
, 0 },
889 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN
,
891 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN
,
893 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN
,
895 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN
,
897 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN
,
899 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN
,
901 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN
,
902 CPU_MOVBE_FLAGS
, 0 },
903 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN
,
905 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN
,
907 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN
,
908 CPU_LZCNT_FLAGS
, 0 },
909 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN
,
911 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN
,
913 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN
,
914 CPU_INVPCID_FLAGS
, 0 },
915 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN
,
916 CPU_CLFLUSH_FLAGS
, 0 },
917 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN
,
919 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN
,
920 CPU_SYSCALL_FLAGS
, 0 },
921 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN
,
922 CPU_RDTSCP_FLAGS
, 0 },
923 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN
,
924 CPU_3DNOW_FLAGS
, 0 },
925 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN
,
926 CPU_3DNOWA_FLAGS
, 0 },
927 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN
,
928 CPU_PADLOCK_FLAGS
, 0 },
929 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN
,
931 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN
,
933 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN
,
934 CPU_SSE4A_FLAGS
, 0 },
935 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN
,
937 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN
,
939 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN
,
941 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN
,
943 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN
,
944 CPU_RDSEED_FLAGS
, 0 },
945 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN
,
946 CPU_PRFCHW_FLAGS
, 0 },
947 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN
,
949 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN
,
951 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN
,
953 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN
,
954 CPU_CLFLUSHOPT_FLAGS
, 0 },
955 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN
,
956 CPU_PREFETCHWT1_FLAGS
, 0 },
957 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN
,
959 { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN
,
961 { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN
,
962 CPU_AVX512IFMA_FLAGS
, 0 },
963 { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN
,
964 CPU_AVX512VBMI_FLAGS
, 0 },
965 { STRING_COMMA_LEN (".avx512_4fmaps"), PROCESSOR_UNKNOWN
,
966 CPU_AVX512_4FMAPS_FLAGS
, 0 },
967 { STRING_COMMA_LEN (".avx512_4vnniw"), PROCESSOR_UNKNOWN
,
968 CPU_AVX512_4VNNIW_FLAGS
, 0 },
969 { STRING_COMMA_LEN (".avx512_vpopcntdq"), PROCESSOR_UNKNOWN
,
970 CPU_AVX512_VPOPCNTDQ_FLAGS
, 0 },
971 { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN
,
972 CPU_CLZERO_FLAGS
, 0 },
973 { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN
,
974 CPU_MWAITX_FLAGS
, 0 },
975 { STRING_COMMA_LEN (".ospke"), PROCESSOR_UNKNOWN
,
976 CPU_OSPKE_FLAGS
, 0 },
977 { STRING_COMMA_LEN (".rdpid"), PROCESSOR_UNKNOWN
,
978 CPU_RDPID_FLAGS
, 0 },
979 { STRING_COMMA_LEN (".ptwrite"), PROCESSOR_UNKNOWN
,
980 CPU_PTWRITE_FLAGS
, 0 },
981 { STRING_COMMA_LEN (".cet"), PROCESSOR_UNKNOWN
,
985 static const noarch_entry cpu_noarch
[] =
987 { STRING_COMMA_LEN ("no87"), CPU_ANY_X87_FLAGS
},
988 { STRING_COMMA_LEN ("no287"), CPU_ANY_287_FLAGS
},
989 { STRING_COMMA_LEN ("no387"), CPU_ANY_387_FLAGS
},
990 { STRING_COMMA_LEN ("no687"), CPU_ANY_687_FLAGS
},
991 { STRING_COMMA_LEN ("nommx"), CPU_ANY_MMX_FLAGS
},
992 { STRING_COMMA_LEN ("nosse"), CPU_ANY_SSE_FLAGS
},
993 { STRING_COMMA_LEN ("nosse2"), CPU_ANY_SSE2_FLAGS
},
994 { STRING_COMMA_LEN ("nosse3"), CPU_ANY_SSE3_FLAGS
},
995 { STRING_COMMA_LEN ("nossse3"), CPU_ANY_SSSE3_FLAGS
},
996 { STRING_COMMA_LEN ("nosse4.1"), CPU_ANY_SSE4_1_FLAGS
},
997 { STRING_COMMA_LEN ("nosse4.2"), CPU_ANY_SSE4_2_FLAGS
},
998 { STRING_COMMA_LEN ("nosse4"), CPU_ANY_SSE4_1_FLAGS
},
999 { STRING_COMMA_LEN ("noavx"), CPU_ANY_AVX_FLAGS
},
1000 { STRING_COMMA_LEN ("noavx2"), CPU_ANY_AVX2_FLAGS
},
1001 { STRING_COMMA_LEN ("noavx512f"), CPU_ANY_AVX512F_FLAGS
},
1002 { STRING_COMMA_LEN ("noavx512cd"), CPU_ANY_AVX512CD_FLAGS
},
1003 { STRING_COMMA_LEN ("noavx512er"), CPU_ANY_AVX512ER_FLAGS
},
1004 { STRING_COMMA_LEN ("noavx512pf"), CPU_ANY_AVX512PF_FLAGS
},
1005 { STRING_COMMA_LEN ("noavx512dq"), CPU_ANY_AVX512DQ_FLAGS
},
1006 { STRING_COMMA_LEN ("noavx512bw"), CPU_ANY_AVX512BW_FLAGS
},
1007 { STRING_COMMA_LEN ("noavx512vl"), CPU_ANY_AVX512VL_FLAGS
},
1008 { STRING_COMMA_LEN ("noavx512ifma"), CPU_ANY_AVX512IFMA_FLAGS
},
1009 { STRING_COMMA_LEN ("noavx512vbmi"), CPU_ANY_AVX512VBMI_FLAGS
},
1010 { STRING_COMMA_LEN ("noavx512_4fmaps"), CPU_ANY_AVX512_4FMAPS_FLAGS
},
1011 { STRING_COMMA_LEN ("noavx512_4vnniw"), CPU_ANY_AVX512_4VNNIW_FLAGS
},
1012 { STRING_COMMA_LEN ("noavx512_vpopcntdq"), CPU_ANY_AVX512_VPOPCNTDQ_FLAGS
},
1016 /* Like s_lcomm_internal in gas/read.c but the alignment string
1017 is allowed to be optional. */
1020 pe_lcomm_internal (int needs_align
, symbolS
*symbolP
, addressT size
)
1027 && *input_line_pointer
== ',')
1029 align
= parse_align (needs_align
- 1);
1031 if (align
== (addressT
) -1)
1046 bss_alloc (symbolP
, size
, align
);
1051 pe_lcomm (int needs_align
)
1053 s_comm_internal (needs_align
* 2, pe_lcomm_internal
);
1057 const pseudo_typeS md_pseudo_table
[] =
1059 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
1060 {"align", s_align_bytes
, 0},
1062 {"align", s_align_ptwo
, 0},
1064 {"arch", set_cpu_arch
, 0},
1068 {"lcomm", pe_lcomm
, 1},
1070 {"ffloat", float_cons
, 'f'},
1071 {"dfloat", float_cons
, 'd'},
1072 {"tfloat", float_cons
, 'x'},
1074 {"slong", signed_cons
, 4},
1075 {"noopt", s_ignore
, 0},
1076 {"optim", s_ignore
, 0},
1077 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
1078 {"code16", set_code_flag
, CODE_16BIT
},
1079 {"code32", set_code_flag
, CODE_32BIT
},
1080 {"code64", set_code_flag
, CODE_64BIT
},
1081 {"intel_syntax", set_intel_syntax
, 1},
1082 {"att_syntax", set_intel_syntax
, 0},
1083 {"intel_mnemonic", set_intel_mnemonic
, 1},
1084 {"att_mnemonic", set_intel_mnemonic
, 0},
1085 {"allow_index_reg", set_allow_index_reg
, 1},
1086 {"disallow_index_reg", set_allow_index_reg
, 0},
1087 {"sse_check", set_check
, 0},
1088 {"operand_check", set_check
, 1},
1089 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1090 {"largecomm", handle_large_common
, 0},
1092 {"file", (void (*) (int)) dwarf2_directive_file
, 0},
1093 {"loc", dwarf2_directive_loc
, 0},
1094 {"loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0},
1097 {"secrel32", pe_directive_secrel
, 0},
1102 /* For interface with expression (). */
1103 extern char *input_line_pointer
;
1105 /* Hash table for instruction mnemonic lookup. */
1106 static struct hash_control
*op_hash
;
1108 /* Hash table for register lookup. */
1109 static struct hash_control
*reg_hash
;
1112 i386_align_code (fragS
*fragP
, int count
)
1114 /* Various efficient no-op patterns for aligning code labels.
1115 Note: Don't try to assemble the instructions in the comments.
1116 0L and 0w are not legal. */
1117 static const unsigned char f32_1
[] =
1119 static const unsigned char f32_2
[] =
1120 {0x66,0x90}; /* xchg %ax,%ax */
1121 static const unsigned char f32_3
[] =
1122 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1123 static const unsigned char f32_4
[] =
1124 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1125 static const unsigned char f32_5
[] =
1127 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1128 static const unsigned char f32_6
[] =
1129 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1130 static const unsigned char f32_7
[] =
1131 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1132 static const unsigned char f32_8
[] =
1134 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1135 static const unsigned char f32_9
[] =
1136 {0x89,0xf6, /* movl %esi,%esi */
1137 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1138 static const unsigned char f32_10
[] =
1139 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
1140 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1141 static const unsigned char f32_11
[] =
1142 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
1143 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1144 static const unsigned char f32_12
[] =
1145 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1146 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
1147 static const unsigned char f32_13
[] =
1148 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1149 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1150 static const unsigned char f32_14
[] =
1151 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
1152 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1153 static const unsigned char f16_3
[] =
1154 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
1155 static const unsigned char f16_4
[] =
1156 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
1157 static const unsigned char f16_5
[] =
1159 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
1160 static const unsigned char f16_6
[] =
1161 {0x89,0xf6, /* mov %si,%si */
1162 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1163 static const unsigned char f16_7
[] =
1164 {0x8d,0x74,0x00, /* lea 0(%si),%si */
1165 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1166 static const unsigned char f16_8
[] =
1167 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
1168 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1169 static const unsigned char jump_31
[] =
1170 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
1171 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1172 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1173 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
1174 static const unsigned char *const f32_patt
[] = {
1175 f32_1
, f32_2
, f32_3
, f32_4
, f32_5
, f32_6
, f32_7
, f32_8
,
1176 f32_9
, f32_10
, f32_11
, f32_12
, f32_13
, f32_14
1178 static const unsigned char *const f16_patt
[] = {
1179 f32_1
, f32_2
, f16_3
, f16_4
, f16_5
, f16_6
, f16_7
, f16_8
1181 /* nopl (%[re]ax) */
1182 static const unsigned char alt_3
[] =
1184 /* nopl 0(%[re]ax) */
1185 static const unsigned char alt_4
[] =
1186 {0x0f,0x1f,0x40,0x00};
1187 /* nopl 0(%[re]ax,%[re]ax,1) */
1188 static const unsigned char alt_5
[] =
1189 {0x0f,0x1f,0x44,0x00,0x00};
1190 /* nopw 0(%[re]ax,%[re]ax,1) */
1191 static const unsigned char alt_6
[] =
1192 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1193 /* nopl 0L(%[re]ax) */
1194 static const unsigned char alt_7
[] =
1195 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1196 /* nopl 0L(%[re]ax,%[re]ax,1) */
1197 static const unsigned char alt_8
[] =
1198 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1199 /* nopw 0L(%[re]ax,%[re]ax,1) */
1200 static const unsigned char alt_9
[] =
1201 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1202 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1203 static const unsigned char alt_10
[] =
1204 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1205 static const unsigned char *const alt_patt
[] = {
1206 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
1210 /* Only align for at least a positive non-zero boundary. */
1211 if (count
<= 0 || count
> MAX_MEM_FOR_RS_ALIGN_CODE
)
1214 /* We need to decide which NOP sequence to use for 32bit and
1215 64bit. When -mtune= is used:
1217 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1218 PROCESSOR_GENERIC32, f32_patt will be used.
1219 2. For the rest, alt_patt will be used.
1221 When -mtune= isn't used, alt_patt will be used if
1222 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
1225 When -march= or .arch is used, we can't use anything beyond
1226 cpu_arch_isa_flags. */
1228 if (flag_code
== CODE_16BIT
)
1232 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1234 /* Adjust jump offset. */
1235 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
1238 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1239 f16_patt
[count
- 1], count
);
1243 const unsigned char *const *patt
= NULL
;
1245 if (fragP
->tc_frag_data
.isa
== PROCESSOR_UNKNOWN
)
1247 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1248 switch (cpu_arch_tune
)
1250 case PROCESSOR_UNKNOWN
:
1251 /* We use cpu_arch_isa_flags to check if we SHOULD
1252 optimize with nops. */
1253 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1258 case PROCESSOR_PENTIUM4
:
1259 case PROCESSOR_NOCONA
:
1260 case PROCESSOR_CORE
:
1261 case PROCESSOR_CORE2
:
1262 case PROCESSOR_COREI7
:
1263 case PROCESSOR_L1OM
:
1264 case PROCESSOR_K1OM
:
1265 case PROCESSOR_GENERIC64
:
1267 case PROCESSOR_ATHLON
:
1269 case PROCESSOR_AMDFAM10
:
1271 case PROCESSOR_ZNVER
:
1275 case PROCESSOR_I386
:
1276 case PROCESSOR_I486
:
1277 case PROCESSOR_PENTIUM
:
1278 case PROCESSOR_PENTIUMPRO
:
1279 case PROCESSOR_IAMCU
:
1280 case PROCESSOR_GENERIC32
:
1287 switch (fragP
->tc_frag_data
.tune
)
1289 case PROCESSOR_UNKNOWN
:
1290 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1291 PROCESSOR_UNKNOWN. */
1295 case PROCESSOR_I386
:
1296 case PROCESSOR_I486
:
1297 case PROCESSOR_PENTIUM
:
1298 case PROCESSOR_IAMCU
:
1300 case PROCESSOR_ATHLON
:
1302 case PROCESSOR_AMDFAM10
:
1304 case PROCESSOR_ZNVER
:
1306 case PROCESSOR_GENERIC32
:
1307 /* We use cpu_arch_isa_flags to check if we CAN optimize
1309 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1314 case PROCESSOR_PENTIUMPRO
:
1315 case PROCESSOR_PENTIUM4
:
1316 case PROCESSOR_NOCONA
:
1317 case PROCESSOR_CORE
:
1318 case PROCESSOR_CORE2
:
1319 case PROCESSOR_COREI7
:
1320 case PROCESSOR_L1OM
:
1321 case PROCESSOR_K1OM
:
1322 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1327 case PROCESSOR_GENERIC64
:
1333 if (patt
== f32_patt
)
1335 /* If the padding is less than 15 bytes, we use the normal
1336 ones. Otherwise, we use a jump instruction and adjust
1340 /* For 64bit, the limit is 3 bytes. */
1341 if (flag_code
== CODE_64BIT
1342 && fragP
->tc_frag_data
.isa_flags
.bitfield
.cpulm
)
1347 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1348 patt
[count
- 1], count
);
1351 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1353 /* Adjust jump offset. */
1354 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
1359 /* Maximum length of an instruction is 10 byte. If the
1360 padding is greater than 10 bytes and we don't use jump,
1361 we have to break it into smaller pieces. */
1362 int padding
= count
;
1363 while (padding
> 10)
1366 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
+ padding
,
1371 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1372 patt
[padding
- 1], padding
);
1375 fragP
->fr_var
= count
;
1379 operand_type_all_zero (const union i386_operand_type
*x
)
1381 switch (ARRAY_SIZE(x
->array
))
1392 return !x
->array
[0];
1399 operand_type_set (union i386_operand_type
*x
, unsigned int v
)
1401 switch (ARRAY_SIZE(x
->array
))
1419 operand_type_equal (const union i386_operand_type
*x
,
1420 const union i386_operand_type
*y
)
1422 switch (ARRAY_SIZE(x
->array
))
1425 if (x
->array
[2] != y
->array
[2])
1429 if (x
->array
[1] != y
->array
[1])
1433 return x
->array
[0] == y
->array
[0];
1441 cpu_flags_all_zero (const union i386_cpu_flags
*x
)
1443 switch (ARRAY_SIZE(x
->array
))
1454 return !x
->array
[0];
1461 cpu_flags_equal (const union i386_cpu_flags
*x
,
1462 const union i386_cpu_flags
*y
)
1464 switch (ARRAY_SIZE(x
->array
))
1467 if (x
->array
[2] != y
->array
[2])
1471 if (x
->array
[1] != y
->array
[1])
1475 return x
->array
[0] == y
->array
[0];
1483 cpu_flags_check_cpu64 (i386_cpu_flags f
)
1485 return !((flag_code
== CODE_64BIT
&& f
.bitfield
.cpuno64
)
1486 || (flag_code
!= CODE_64BIT
&& f
.bitfield
.cpu64
));
1489 static INLINE i386_cpu_flags
1490 cpu_flags_and (i386_cpu_flags x
, i386_cpu_flags y
)
1492 switch (ARRAY_SIZE (x
.array
))
1495 x
.array
[2] &= y
.array
[2];
1498 x
.array
[1] &= y
.array
[1];
1501 x
.array
[0] &= y
.array
[0];
1509 static INLINE i386_cpu_flags
1510 cpu_flags_or (i386_cpu_flags x
, i386_cpu_flags y
)
1512 switch (ARRAY_SIZE (x
.array
))
1515 x
.array
[2] |= y
.array
[2];
1518 x
.array
[1] |= y
.array
[1];
1521 x
.array
[0] |= y
.array
[0];
1529 static INLINE i386_cpu_flags
1530 cpu_flags_and_not (i386_cpu_flags x
, i386_cpu_flags y
)
1532 switch (ARRAY_SIZE (x
.array
))
1535 x
.array
[2] &= ~y
.array
[2];
1538 x
.array
[1] &= ~y
.array
[1];
1541 x
.array
[0] &= ~y
.array
[0];
1549 #define CPU_FLAGS_ARCH_MATCH 0x1
1550 #define CPU_FLAGS_64BIT_MATCH 0x2
1551 #define CPU_FLAGS_AES_MATCH 0x4
1552 #define CPU_FLAGS_PCLMUL_MATCH 0x8
1553 #define CPU_FLAGS_AVX_MATCH 0x10
1555 #define CPU_FLAGS_32BIT_MATCH \
1556 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH \
1557 | CPU_FLAGS_PCLMUL_MATCH | CPU_FLAGS_AVX_MATCH)
1558 #define CPU_FLAGS_PERFECT_MATCH \
1559 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)
1561 /* Return CPU flags match bits. */
1564 cpu_flags_match (const insn_template
*t
)
1566 i386_cpu_flags x
= t
->cpu_flags
;
1567 int match
= cpu_flags_check_cpu64 (x
) ? CPU_FLAGS_64BIT_MATCH
: 0;
1569 x
.bitfield
.cpu64
= 0;
1570 x
.bitfield
.cpuno64
= 0;
1572 if (cpu_flags_all_zero (&x
))
1574 /* This instruction is available on all archs. */
1575 match
|= CPU_FLAGS_32BIT_MATCH
;
1579 /* This instruction is available only on some archs. */
1580 i386_cpu_flags cpu
= cpu_arch_flags
;
1582 cpu
= cpu_flags_and (x
, cpu
);
1583 if (!cpu_flags_all_zero (&cpu
))
1585 if (x
.bitfield
.cpuavx
)
1587 /* We only need to check AES/PCLMUL/SSE2AVX with AVX. */
1588 if (cpu
.bitfield
.cpuavx
)
1590 /* Check SSE2AVX. */
1591 if (!t
->opcode_modifier
.sse2avx
|| sse2avx
)
1593 match
|= (CPU_FLAGS_ARCH_MATCH
1594 | CPU_FLAGS_AVX_MATCH
);
1596 if (!x
.bitfield
.cpuaes
|| cpu
.bitfield
.cpuaes
)
1597 match
|= CPU_FLAGS_AES_MATCH
;
1599 if (!x
.bitfield
.cpupclmul
1600 || cpu
.bitfield
.cpupclmul
)
1601 match
|= CPU_FLAGS_PCLMUL_MATCH
;
1605 match
|= CPU_FLAGS_ARCH_MATCH
;
1607 else if (x
.bitfield
.cpuavx512vl
)
1609 /* Match AVX512VL. */
1610 if (cpu
.bitfield
.cpuavx512vl
)
1612 /* Need another match. */
1613 cpu
.bitfield
.cpuavx512vl
= 0;
1614 if (!cpu_flags_all_zero (&cpu
))
1615 match
|= CPU_FLAGS_32BIT_MATCH
;
1617 match
|= CPU_FLAGS_ARCH_MATCH
;
1620 match
|= CPU_FLAGS_ARCH_MATCH
;
1623 match
|= CPU_FLAGS_32BIT_MATCH
;
1629 static INLINE i386_operand_type
1630 operand_type_and (i386_operand_type x
, i386_operand_type y
)
1632 switch (ARRAY_SIZE (x
.array
))
1635 x
.array
[2] &= y
.array
[2];
1638 x
.array
[1] &= y
.array
[1];
1641 x
.array
[0] &= y
.array
[0];
1649 static INLINE i386_operand_type
1650 operand_type_or (i386_operand_type x
, i386_operand_type y
)
1652 switch (ARRAY_SIZE (x
.array
))
1655 x
.array
[2] |= y
.array
[2];
1658 x
.array
[1] |= y
.array
[1];
1661 x
.array
[0] |= y
.array
[0];
1669 static INLINE i386_operand_type
1670 operand_type_xor (i386_operand_type x
, i386_operand_type y
)
1672 switch (ARRAY_SIZE (x
.array
))
1675 x
.array
[2] ^= y
.array
[2];
1678 x
.array
[1] ^= y
.array
[1];
1681 x
.array
[0] ^= y
.array
[0];
1689 static const i386_operand_type acc32
= OPERAND_TYPE_ACC32
;
1690 static const i386_operand_type acc64
= OPERAND_TYPE_ACC64
;
1691 static const i386_operand_type control
= OPERAND_TYPE_CONTROL
;
1692 static const i386_operand_type inoutportreg
1693 = OPERAND_TYPE_INOUTPORTREG
;
1694 static const i386_operand_type reg16_inoutportreg
1695 = OPERAND_TYPE_REG16_INOUTPORTREG
;
1696 static const i386_operand_type disp16
= OPERAND_TYPE_DISP16
;
1697 static const i386_operand_type disp32
= OPERAND_TYPE_DISP32
;
1698 static const i386_operand_type disp32s
= OPERAND_TYPE_DISP32S
;
1699 static const i386_operand_type disp16_32
= OPERAND_TYPE_DISP16_32
;
1700 static const i386_operand_type anydisp
1701 = OPERAND_TYPE_ANYDISP
;
1702 static const i386_operand_type regxmm
= OPERAND_TYPE_REGXMM
;
1703 static const i386_operand_type regymm
= OPERAND_TYPE_REGYMM
;
1704 static const i386_operand_type regzmm
= OPERAND_TYPE_REGZMM
;
1705 static const i386_operand_type regmask
= OPERAND_TYPE_REGMASK
;
1706 static const i386_operand_type imm8
= OPERAND_TYPE_IMM8
;
1707 static const i386_operand_type imm8s
= OPERAND_TYPE_IMM8S
;
1708 static const i386_operand_type imm16
= OPERAND_TYPE_IMM16
;
1709 static const i386_operand_type imm32
= OPERAND_TYPE_IMM32
;
1710 static const i386_operand_type imm32s
= OPERAND_TYPE_IMM32S
;
1711 static const i386_operand_type imm64
= OPERAND_TYPE_IMM64
;
1712 static const i386_operand_type imm16_32
= OPERAND_TYPE_IMM16_32
;
1713 static const i386_operand_type imm16_32s
= OPERAND_TYPE_IMM16_32S
;
1714 static const i386_operand_type imm16_32_32s
= OPERAND_TYPE_IMM16_32_32S
;
1715 static const i386_operand_type vec_imm4
= OPERAND_TYPE_VEC_IMM4
;
1726 operand_type_check (i386_operand_type t
, enum operand_type c
)
1731 return (t
.bitfield
.reg8
1734 || t
.bitfield
.reg64
);
1737 return (t
.bitfield
.imm8
1741 || t
.bitfield
.imm32s
1742 || t
.bitfield
.imm64
);
1745 return (t
.bitfield
.disp8
1746 || t
.bitfield
.disp16
1747 || t
.bitfield
.disp32
1748 || t
.bitfield
.disp32s
1749 || t
.bitfield
.disp64
);
1752 return (t
.bitfield
.disp8
1753 || t
.bitfield
.disp16
1754 || t
.bitfield
.disp32
1755 || t
.bitfield
.disp32s
1756 || t
.bitfield
.disp64
1757 || t
.bitfield
.baseindex
);
1766 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1767 operand J for instruction template T. */
1770 match_reg_size (const insn_template
*t
, unsigned int j
)
1772 return !((i
.types
[j
].bitfield
.byte
1773 && !t
->operand_types
[j
].bitfield
.byte
)
1774 || (i
.types
[j
].bitfield
.word
1775 && !t
->operand_types
[j
].bitfield
.word
)
1776 || (i
.types
[j
].bitfield
.dword
1777 && !t
->operand_types
[j
].bitfield
.dword
)
1778 || (i
.types
[j
].bitfield
.qword
1779 && !t
->operand_types
[j
].bitfield
.qword
));
1782 /* Return 1 if there is no conflict in any size on operand J for
1783 instruction template T. */
1786 match_mem_size (const insn_template
*t
, unsigned int j
)
1788 return (match_reg_size (t
, j
)
1789 && !((i
.types
[j
].bitfield
.unspecified
1791 && !t
->operand_types
[j
].bitfield
.unspecified
)
1792 || (i
.types
[j
].bitfield
.fword
1793 && !t
->operand_types
[j
].bitfield
.fword
)
1794 || (i
.types
[j
].bitfield
.tbyte
1795 && !t
->operand_types
[j
].bitfield
.tbyte
)
1796 || (i
.types
[j
].bitfield
.xmmword
1797 && !t
->operand_types
[j
].bitfield
.xmmword
)
1798 || (i
.types
[j
].bitfield
.ymmword
1799 && !t
->operand_types
[j
].bitfield
.ymmword
)
1800 || (i
.types
[j
].bitfield
.zmmword
1801 && !t
->operand_types
[j
].bitfield
.zmmword
)));
1804 /* Return 1 if there is no size conflict on any operands for
1805 instruction template T. */
1808 operand_size_match (const insn_template
*t
)
1813 /* Don't check jump instructions. */
1814 if (t
->opcode_modifier
.jump
1815 || t
->opcode_modifier
.jumpbyte
1816 || t
->opcode_modifier
.jumpdword
1817 || t
->opcode_modifier
.jumpintersegment
)
1820 /* Check memory and accumulator operand size. */
1821 for (j
= 0; j
< i
.operands
; j
++)
1823 if (t
->operand_types
[j
].bitfield
.anysize
)
1826 if (t
->operand_types
[j
].bitfield
.acc
&& !match_reg_size (t
, j
))
1832 if (i
.types
[j
].bitfield
.mem
&& !match_mem_size (t
, j
))
1841 else if (!t
->opcode_modifier
.d
&& !t
->opcode_modifier
.floatd
)
1844 i
.error
= operand_size_mismatch
;
1848 /* Check reverse. */
1849 gas_assert (i
.operands
== 2);
1852 for (j
= 0; j
< 2; j
++)
1854 if (t
->operand_types
[j
].bitfield
.acc
1855 && !match_reg_size (t
, j
? 0 : 1))
1858 if (i
.types
[j
].bitfield
.mem
1859 && !match_mem_size (t
, j
? 0 : 1))
1867 operand_type_match (i386_operand_type overlap
,
1868 i386_operand_type given
)
1870 i386_operand_type temp
= overlap
;
1872 temp
.bitfield
.jumpabsolute
= 0;
1873 temp
.bitfield
.unspecified
= 0;
1874 temp
.bitfield
.byte
= 0;
1875 temp
.bitfield
.word
= 0;
1876 temp
.bitfield
.dword
= 0;
1877 temp
.bitfield
.fword
= 0;
1878 temp
.bitfield
.qword
= 0;
1879 temp
.bitfield
.tbyte
= 0;
1880 temp
.bitfield
.xmmword
= 0;
1881 temp
.bitfield
.ymmword
= 0;
1882 temp
.bitfield
.zmmword
= 0;
1883 if (operand_type_all_zero (&temp
))
1886 if (given
.bitfield
.baseindex
== overlap
.bitfield
.baseindex
1887 && given
.bitfield
.jumpabsolute
== overlap
.bitfield
.jumpabsolute
)
1891 i
.error
= operand_type_mismatch
;
1895 /* If given types g0 and g1 are registers they must be of the same type
1896 unless the expected operand type register overlap is null.
1897 Note that Acc in a template matches every size of reg. */
1900 operand_type_register_match (i386_operand_type m0
,
1901 i386_operand_type g0
,
1902 i386_operand_type t0
,
1903 i386_operand_type m1
,
1904 i386_operand_type g1
,
1905 i386_operand_type t1
)
1907 if (!operand_type_check (g0
, reg
))
1910 if (!operand_type_check (g1
, reg
))
1913 if (g0
.bitfield
.reg8
== g1
.bitfield
.reg8
1914 && g0
.bitfield
.reg16
== g1
.bitfield
.reg16
1915 && g0
.bitfield
.reg32
== g1
.bitfield
.reg32
1916 && g0
.bitfield
.reg64
== g1
.bitfield
.reg64
)
1919 if (m0
.bitfield
.acc
)
1921 t0
.bitfield
.reg8
= 1;
1922 t0
.bitfield
.reg16
= 1;
1923 t0
.bitfield
.reg32
= 1;
1924 t0
.bitfield
.reg64
= 1;
1927 if (m1
.bitfield
.acc
)
1929 t1
.bitfield
.reg8
= 1;
1930 t1
.bitfield
.reg16
= 1;
1931 t1
.bitfield
.reg32
= 1;
1932 t1
.bitfield
.reg64
= 1;
1935 if (!(t0
.bitfield
.reg8
& t1
.bitfield
.reg8
)
1936 && !(t0
.bitfield
.reg16
& t1
.bitfield
.reg16
)
1937 && !(t0
.bitfield
.reg32
& t1
.bitfield
.reg32
)
1938 && !(t0
.bitfield
.reg64
& t1
.bitfield
.reg64
))
1941 i
.error
= register_type_mismatch
;
1946 static INLINE
unsigned int
1947 register_number (const reg_entry
*r
)
1949 unsigned int nr
= r
->reg_num
;
1951 if (r
->reg_flags
& RegRex
)
1954 if (r
->reg_flags
& RegVRex
)
1960 static INLINE
unsigned int
1961 mode_from_disp_size (i386_operand_type t
)
1963 if (t
.bitfield
.disp8
|| t
.bitfield
.vec_disp8
)
1965 else if (t
.bitfield
.disp16
1966 || t
.bitfield
.disp32
1967 || t
.bitfield
.disp32s
)
1974 fits_in_signed_byte (addressT num
)
1976 return num
+ 0x80 <= 0xff;
1980 fits_in_unsigned_byte (addressT num
)
1986 fits_in_unsigned_word (addressT num
)
1988 return num
<= 0xffff;
1992 fits_in_signed_word (addressT num
)
1994 return num
+ 0x8000 <= 0xffff;
1998 fits_in_signed_long (addressT num ATTRIBUTE_UNUSED
)
2003 return num
+ 0x80000000 <= 0xffffffff;
2005 } /* fits_in_signed_long() */
2008 fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED
)
2013 return num
<= 0xffffffff;
2015 } /* fits_in_unsigned_long() */
2018 fits_in_vec_disp8 (offsetT num
)
2020 int shift
= i
.memshift
;
2026 mask
= (1 << shift
) - 1;
2028 /* Return 0 if NUM isn't properly aligned. */
2032 /* Check if NUM will fit in 8bit after shift. */
2033 return fits_in_signed_byte (num
>> shift
);
2037 fits_in_imm4 (offsetT num
)
2039 return (num
& 0xf) == num
;
2042 static i386_operand_type
2043 smallest_imm_type (offsetT num
)
2045 i386_operand_type t
;
2047 operand_type_set (&t
, 0);
2048 t
.bitfield
.imm64
= 1;
2050 if (cpu_arch_tune
!= PROCESSOR_I486
&& num
== 1)
2052 /* This code is disabled on the 486 because all the Imm1 forms
2053 in the opcode table are slower on the i486. They're the
2054 versions with the implicitly specified single-position
2055 displacement, which has another syntax if you really want to
2057 t
.bitfield
.imm1
= 1;
2058 t
.bitfield
.imm8
= 1;
2059 t
.bitfield
.imm8s
= 1;
2060 t
.bitfield
.imm16
= 1;
2061 t
.bitfield
.imm32
= 1;
2062 t
.bitfield
.imm32s
= 1;
2064 else if (fits_in_signed_byte (num
))
2066 t
.bitfield
.imm8
= 1;
2067 t
.bitfield
.imm8s
= 1;
2068 t
.bitfield
.imm16
= 1;
2069 t
.bitfield
.imm32
= 1;
2070 t
.bitfield
.imm32s
= 1;
2072 else if (fits_in_unsigned_byte (num
))
2074 t
.bitfield
.imm8
= 1;
2075 t
.bitfield
.imm16
= 1;
2076 t
.bitfield
.imm32
= 1;
2077 t
.bitfield
.imm32s
= 1;
2079 else if (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
2081 t
.bitfield
.imm16
= 1;
2082 t
.bitfield
.imm32
= 1;
2083 t
.bitfield
.imm32s
= 1;
2085 else if (fits_in_signed_long (num
))
2087 t
.bitfield
.imm32
= 1;
2088 t
.bitfield
.imm32s
= 1;
2090 else if (fits_in_unsigned_long (num
))
2091 t
.bitfield
.imm32
= 1;
2097 offset_in_range (offsetT val
, int size
)
2103 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
2104 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
2105 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
2107 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
2113 /* If BFD64, sign extend val for 32bit address mode. */
2114 if (flag_code
!= CODE_64BIT
2115 || i
.prefix
[ADDR_PREFIX
])
2116 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
2117 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
2120 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
2122 char buf1
[40], buf2
[40];
2124 sprint_value (buf1
, val
);
2125 sprint_value (buf2
, val
& mask
);
2126 as_warn (_("%s shortened to %s"), buf1
, buf2
);
2140 a. PREFIX_EXIST if attempting to add a prefix where one from the
2141 same class already exists.
2142 b. PREFIX_LOCK if lock prefix is added.
2143 c. PREFIX_REP if rep/repne prefix is added.
2144 d. PREFIX_OTHER if other prefix is added.
2147 static enum PREFIX_GROUP
2148 add_prefix (unsigned int prefix
)
2150 enum PREFIX_GROUP ret
= PREFIX_OTHER
;
2153 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
2154 && flag_code
== CODE_64BIT
)
2156 if ((i
.prefix
[REX_PREFIX
] & prefix
& REX_W
)
2157 || ((i
.prefix
[REX_PREFIX
] & (REX_R
| REX_X
| REX_B
))
2158 && (prefix
& (REX_R
| REX_X
| REX_B
))))
2169 case CS_PREFIX_OPCODE
:
2170 case DS_PREFIX_OPCODE
:
2171 case ES_PREFIX_OPCODE
:
2172 case FS_PREFIX_OPCODE
:
2173 case GS_PREFIX_OPCODE
:
2174 case SS_PREFIX_OPCODE
:
2178 case REPNE_PREFIX_OPCODE
:
2179 case REPE_PREFIX_OPCODE
:
2184 case LOCK_PREFIX_OPCODE
:
2193 case ADDR_PREFIX_OPCODE
:
2197 case DATA_PREFIX_OPCODE
:
2201 if (i
.prefix
[q
] != 0)
2209 i
.prefix
[q
] |= prefix
;
2212 as_bad (_("same type of prefix used twice"));
2218 update_code_flag (int value
, int check
)
2220 PRINTF_LIKE ((*as_error
));
2222 flag_code
= (enum flag_code
) value
;
2223 if (flag_code
== CODE_64BIT
)
2225 cpu_arch_flags
.bitfield
.cpu64
= 1;
2226 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2230 cpu_arch_flags
.bitfield
.cpu64
= 0;
2231 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2233 if (value
== CODE_64BIT
&& !cpu_arch_flags
.bitfield
.cpulm
)
2236 as_error
= as_fatal
;
2239 (*as_error
) (_("64bit mode not supported on `%s'."),
2240 cpu_arch_name
? cpu_arch_name
: default_arch
);
2242 if (value
== CODE_32BIT
&& !cpu_arch_flags
.bitfield
.cpui386
)
2245 as_error
= as_fatal
;
2248 (*as_error
) (_("32bit mode not supported on `%s'."),
2249 cpu_arch_name
? cpu_arch_name
: default_arch
);
2251 stackop_size
= '\0';
2255 set_code_flag (int value
)
2257 update_code_flag (value
, 0);
2261 set_16bit_gcc_code_flag (int new_code_flag
)
2263 flag_code
= (enum flag_code
) new_code_flag
;
2264 if (flag_code
!= CODE_16BIT
)
2266 cpu_arch_flags
.bitfield
.cpu64
= 0;
2267 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2268 stackop_size
= LONG_MNEM_SUFFIX
;
2272 set_intel_syntax (int syntax_flag
)
2274 /* Find out if register prefixing is specified. */
2275 int ask_naked_reg
= 0;
2278 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2281 int e
= get_symbol_name (&string
);
2283 if (strcmp (string
, "prefix") == 0)
2285 else if (strcmp (string
, "noprefix") == 0)
2288 as_bad (_("bad argument to syntax directive."));
2289 (void) restore_line_pointer (e
);
2291 demand_empty_rest_of_line ();
2293 intel_syntax
= syntax_flag
;
2295 if (ask_naked_reg
== 0)
2296 allow_naked_reg
= (intel_syntax
2297 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
2299 allow_naked_reg
= (ask_naked_reg
< 0);
2301 expr_set_rank (O_full_ptr
, syntax_flag
? 10 : 0);
2303 identifier_chars
['%'] = intel_syntax
&& allow_naked_reg
? '%' : 0;
2304 identifier_chars
['$'] = intel_syntax
? '$' : 0;
2305 register_prefix
= allow_naked_reg
? "" : "%";
2309 set_intel_mnemonic (int mnemonic_flag
)
2311 intel_mnemonic
= mnemonic_flag
;
2315 set_allow_index_reg (int flag
)
2317 allow_index_reg
= flag
;
2321 set_check (int what
)
2323 enum check_kind
*kind
;
2328 kind
= &operand_check
;
2339 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2342 int e
= get_symbol_name (&string
);
2344 if (strcmp (string
, "none") == 0)
2346 else if (strcmp (string
, "warning") == 0)
2347 *kind
= check_warning
;
2348 else if (strcmp (string
, "error") == 0)
2349 *kind
= check_error
;
2351 as_bad (_("bad argument to %s_check directive."), str
);
2352 (void) restore_line_pointer (e
);
2355 as_bad (_("missing argument for %s_check directive"), str
);
2357 demand_empty_rest_of_line ();
2361 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED
,
2362 i386_cpu_flags new_flag ATTRIBUTE_UNUSED
)
2364 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2365 static const char *arch
;
2367 /* Intel LIOM is only supported on ELF. */
2373 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2374 use default_arch. */
2375 arch
= cpu_arch_name
;
2377 arch
= default_arch
;
2380 /* If we are targeting Intel MCU, we must enable it. */
2381 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_IAMCU
2382 || new_flag
.bitfield
.cpuiamcu
)
2385 /* If we are targeting Intel L1OM, we must enable it. */
2386 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_L1OM
2387 || new_flag
.bitfield
.cpul1om
)
2390 /* If we are targeting Intel K1OM, we must enable it. */
2391 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_K1OM
2392 || new_flag
.bitfield
.cpuk1om
)
2395 as_bad (_("`%s' is not supported on `%s'"), name
, arch
);
2400 set_cpu_arch (int dummy ATTRIBUTE_UNUSED
)
2404 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2407 int e
= get_symbol_name (&string
);
2409 i386_cpu_flags flags
;
2411 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
2413 if (strcmp (string
, cpu_arch
[j
].name
) == 0)
2415 check_cpu_arch_compatible (string
, cpu_arch
[j
].flags
);
2419 cpu_arch_name
= cpu_arch
[j
].name
;
2420 cpu_sub_arch_name
= NULL
;
2421 cpu_arch_flags
= cpu_arch
[j
].flags
;
2422 if (flag_code
== CODE_64BIT
)
2424 cpu_arch_flags
.bitfield
.cpu64
= 1;
2425 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2429 cpu_arch_flags
.bitfield
.cpu64
= 0;
2430 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2432 cpu_arch_isa
= cpu_arch
[j
].type
;
2433 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
2434 if (!cpu_arch_tune_set
)
2436 cpu_arch_tune
= cpu_arch_isa
;
2437 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
2442 flags
= cpu_flags_or (cpu_arch_flags
,
2445 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2447 if (cpu_sub_arch_name
)
2449 char *name
= cpu_sub_arch_name
;
2450 cpu_sub_arch_name
= concat (name
,
2452 (const char *) NULL
);
2456 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
2457 cpu_arch_flags
= flags
;
2458 cpu_arch_isa_flags
= flags
;
2460 (void) restore_line_pointer (e
);
2461 demand_empty_rest_of_line ();
2466 if (*string
== '.' && j
>= ARRAY_SIZE (cpu_arch
))
2468 /* Disable an ISA extension. */
2469 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
2470 if (strcmp (string
+ 1, cpu_noarch
[j
].name
) == 0)
2472 flags
= cpu_flags_and_not (cpu_arch_flags
,
2473 cpu_noarch
[j
].flags
);
2474 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2476 if (cpu_sub_arch_name
)
2478 char *name
= cpu_sub_arch_name
;
2479 cpu_sub_arch_name
= concat (name
, string
,
2480 (const char *) NULL
);
2484 cpu_sub_arch_name
= xstrdup (string
);
2485 cpu_arch_flags
= flags
;
2486 cpu_arch_isa_flags
= flags
;
2488 (void) restore_line_pointer (e
);
2489 demand_empty_rest_of_line ();
2493 j
= ARRAY_SIZE (cpu_arch
);
2496 if (j
>= ARRAY_SIZE (cpu_arch
))
2497 as_bad (_("no such architecture: `%s'"), string
);
2499 *input_line_pointer
= e
;
2502 as_bad (_("missing cpu architecture"));
2504 no_cond_jump_promotion
= 0;
2505 if (*input_line_pointer
== ','
2506 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
2511 ++input_line_pointer
;
2512 e
= get_symbol_name (&string
);
2514 if (strcmp (string
, "nojumps") == 0)
2515 no_cond_jump_promotion
= 1;
2516 else if (strcmp (string
, "jumps") == 0)
2519 as_bad (_("no such architecture modifier: `%s'"), string
);
2521 (void) restore_line_pointer (e
);
2524 demand_empty_rest_of_line ();
2527 enum bfd_architecture
2530 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2532 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2533 || flag_code
!= CODE_64BIT
)
2534 as_fatal (_("Intel L1OM is 64bit ELF only"));
2535 return bfd_arch_l1om
;
2537 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2539 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2540 || flag_code
!= CODE_64BIT
)
2541 as_fatal (_("Intel K1OM is 64bit ELF only"));
2542 return bfd_arch_k1om
;
2544 else if (cpu_arch_isa
== PROCESSOR_IAMCU
)
2546 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2547 || flag_code
== CODE_64BIT
)
2548 as_fatal (_("Intel MCU is 32bit ELF only"));
2549 return bfd_arch_iamcu
;
2552 return bfd_arch_i386
;
2558 if (!strncmp (default_arch
, "x86_64", 6))
2560 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2562 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2563 || default_arch
[6] != '\0')
2564 as_fatal (_("Intel L1OM is 64bit ELF only"));
2565 return bfd_mach_l1om
;
2567 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2569 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2570 || default_arch
[6] != '\0')
2571 as_fatal (_("Intel K1OM is 64bit ELF only"));
2572 return bfd_mach_k1om
;
2574 else if (default_arch
[6] == '\0')
2575 return bfd_mach_x86_64
;
2577 return bfd_mach_x64_32
;
2579 else if (!strcmp (default_arch
, "i386")
2580 || !strcmp (default_arch
, "iamcu"))
2582 if (cpu_arch_isa
== PROCESSOR_IAMCU
)
2584 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
2585 as_fatal (_("Intel MCU is 32bit ELF only"));
2586 return bfd_mach_i386_iamcu
;
2589 return bfd_mach_i386_i386
;
2592 as_fatal (_("unknown architecture"));
2598 const char *hash_err
;
2600 /* Initialize op_hash hash table. */
2601 op_hash
= hash_new ();
2604 const insn_template
*optab
;
2605 templates
*core_optab
;
2607 /* Setup for loop. */
2609 core_optab
= XNEW (templates
);
2610 core_optab
->start
= optab
;
2615 if (optab
->name
== NULL
2616 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
2618 /* different name --> ship out current template list;
2619 add to hash table; & begin anew. */
2620 core_optab
->end
= optab
;
2621 hash_err
= hash_insert (op_hash
,
2623 (void *) core_optab
);
2626 as_fatal (_("can't hash %s: %s"),
2630 if (optab
->name
== NULL
)
2632 core_optab
= XNEW (templates
);
2633 core_optab
->start
= optab
;
2638 /* Initialize reg_hash hash table. */
2639 reg_hash
= hash_new ();
2641 const reg_entry
*regtab
;
2642 unsigned int regtab_size
= i386_regtab_size
;
2644 for (regtab
= i386_regtab
; regtab_size
--; regtab
++)
2646 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (void *) regtab
);
2648 as_fatal (_("can't hash %s: %s"),
2654 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
2659 for (c
= 0; c
< 256; c
++)
2664 mnemonic_chars
[c
] = c
;
2665 register_chars
[c
] = c
;
2666 operand_chars
[c
] = c
;
2668 else if (ISLOWER (c
))
2670 mnemonic_chars
[c
] = c
;
2671 register_chars
[c
] = c
;
2672 operand_chars
[c
] = c
;
2674 else if (ISUPPER (c
))
2676 mnemonic_chars
[c
] = TOLOWER (c
);
2677 register_chars
[c
] = mnemonic_chars
[c
];
2678 operand_chars
[c
] = c
;
2680 else if (c
== '{' || c
== '}')
2681 operand_chars
[c
] = c
;
2683 if (ISALPHA (c
) || ISDIGIT (c
))
2684 identifier_chars
[c
] = c
;
2687 identifier_chars
[c
] = c
;
2688 operand_chars
[c
] = c
;
2693 identifier_chars
['@'] = '@';
2696 identifier_chars
['?'] = '?';
2697 operand_chars
['?'] = '?';
2699 digit_chars
['-'] = '-';
2700 mnemonic_chars
['_'] = '_';
2701 mnemonic_chars
['-'] = '-';
2702 mnemonic_chars
['.'] = '.';
2703 identifier_chars
['_'] = '_';
2704 identifier_chars
['.'] = '.';
2706 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
2707 operand_chars
[(unsigned char) *p
] = *p
;
2710 if (flag_code
== CODE_64BIT
)
2712 #if defined (OBJ_COFF) && defined (TE_PE)
2713 x86_dwarf2_return_column
= (OUTPUT_FLAVOR
== bfd_target_coff_flavour
2716 x86_dwarf2_return_column
= 16;
2718 x86_cie_data_alignment
= -8;
2722 x86_dwarf2_return_column
= 8;
2723 x86_cie_data_alignment
= -4;
2728 i386_print_statistics (FILE *file
)
2730 hash_print_statistics (file
, "i386 opcode", op_hash
);
2731 hash_print_statistics (file
, "i386 register", reg_hash
);
2736 /* Debugging routines for md_assemble. */
2737 static void pte (insn_template
*);
2738 static void pt (i386_operand_type
);
2739 static void pe (expressionS
*);
2740 static void ps (symbolS
*);
2743 pi (char *line
, i386_insn
*x
)
2747 fprintf (stdout
, "%s: template ", line
);
2749 fprintf (stdout
, " address: base %s index %s scale %x\n",
2750 x
->base_reg
? x
->base_reg
->reg_name
: "none",
2751 x
->index_reg
? x
->index_reg
->reg_name
: "none",
2752 x
->log2_scale_factor
);
2753 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
2754 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
2755 fprintf (stdout
, " sib: base %x index %x scale %x\n",
2756 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
2757 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
2758 (x
->rex
& REX_W
) != 0,
2759 (x
->rex
& REX_R
) != 0,
2760 (x
->rex
& REX_X
) != 0,
2761 (x
->rex
& REX_B
) != 0);
2762 for (j
= 0; j
< x
->operands
; j
++)
2764 fprintf (stdout
, " #%d: ", j
+ 1);
2766 fprintf (stdout
, "\n");
2767 if (x
->types
[j
].bitfield
.reg8
2768 || x
->types
[j
].bitfield
.reg16
2769 || x
->types
[j
].bitfield
.reg32
2770 || x
->types
[j
].bitfield
.reg64
2771 || x
->types
[j
].bitfield
.regmmx
2772 || x
->types
[j
].bitfield
.regxmm
2773 || x
->types
[j
].bitfield
.regymm
2774 || x
->types
[j
].bitfield
.regzmm
2775 || x
->types
[j
].bitfield
.sreg2
2776 || x
->types
[j
].bitfield
.sreg3
2777 || x
->types
[j
].bitfield
.control
2778 || x
->types
[j
].bitfield
.debug
2779 || x
->types
[j
].bitfield
.test
)
2780 fprintf (stdout
, "%s\n", x
->op
[j
].regs
->reg_name
);
2781 if (operand_type_check (x
->types
[j
], imm
))
2783 if (operand_type_check (x
->types
[j
], disp
))
2784 pe (x
->op
[j
].disps
);
2789 pte (insn_template
*t
)
2792 fprintf (stdout
, " %d operands ", t
->operands
);
2793 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
2794 if (t
->extension_opcode
!= None
)
2795 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
2796 if (t
->opcode_modifier
.d
)
2797 fprintf (stdout
, "D");
2798 if (t
->opcode_modifier
.w
)
2799 fprintf (stdout
, "W");
2800 fprintf (stdout
, "\n");
2801 for (j
= 0; j
< t
->operands
; j
++)
2803 fprintf (stdout
, " #%d type ", j
+ 1);
2804 pt (t
->operand_types
[j
]);
2805 fprintf (stdout
, "\n");
2812 fprintf (stdout
, " operation %d\n", e
->X_op
);
2813 fprintf (stdout
, " add_number %ld (%lx)\n",
2814 (long) e
->X_add_number
, (long) e
->X_add_number
);
2815 if (e
->X_add_symbol
)
2817 fprintf (stdout
, " add_symbol ");
2818 ps (e
->X_add_symbol
);
2819 fprintf (stdout
, "\n");
2823 fprintf (stdout
, " op_symbol ");
2824 ps (e
->X_op_symbol
);
2825 fprintf (stdout
, "\n");
2832 fprintf (stdout
, "%s type %s%s",
2834 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
2835 segment_name (S_GET_SEGMENT (s
)));
2838 static struct type_name
2840 i386_operand_type mask
;
2843 const type_names
[] =
2845 { OPERAND_TYPE_REG8
, "r8" },
2846 { OPERAND_TYPE_REG16
, "r16" },
2847 { OPERAND_TYPE_REG32
, "r32" },
2848 { OPERAND_TYPE_REG64
, "r64" },
2849 { OPERAND_TYPE_IMM8
, "i8" },
2850 { OPERAND_TYPE_IMM8
, "i8s" },
2851 { OPERAND_TYPE_IMM16
, "i16" },
2852 { OPERAND_TYPE_IMM32
, "i32" },
2853 { OPERAND_TYPE_IMM32S
, "i32s" },
2854 { OPERAND_TYPE_IMM64
, "i64" },
2855 { OPERAND_TYPE_IMM1
, "i1" },
2856 { OPERAND_TYPE_BASEINDEX
, "BaseIndex" },
2857 { OPERAND_TYPE_DISP8
, "d8" },
2858 { OPERAND_TYPE_DISP16
, "d16" },
2859 { OPERAND_TYPE_DISP32
, "d32" },
2860 { OPERAND_TYPE_DISP32S
, "d32s" },
2861 { OPERAND_TYPE_DISP64
, "d64" },
2862 { OPERAND_TYPE_VEC_DISP8
, "Vector d8" },
2863 { OPERAND_TYPE_INOUTPORTREG
, "InOutPortReg" },
2864 { OPERAND_TYPE_SHIFTCOUNT
, "ShiftCount" },
2865 { OPERAND_TYPE_CONTROL
, "control reg" },
2866 { OPERAND_TYPE_TEST
, "test reg" },
2867 { OPERAND_TYPE_DEBUG
, "debug reg" },
2868 { OPERAND_TYPE_FLOATREG
, "FReg" },
2869 { OPERAND_TYPE_FLOATACC
, "FAcc" },
2870 { OPERAND_TYPE_SREG2
, "SReg2" },
2871 { OPERAND_TYPE_SREG3
, "SReg3" },
2872 { OPERAND_TYPE_ACC
, "Acc" },
2873 { OPERAND_TYPE_JUMPABSOLUTE
, "Jump Absolute" },
2874 { OPERAND_TYPE_REGMMX
, "rMMX" },
2875 { OPERAND_TYPE_REGXMM
, "rXMM" },
2876 { OPERAND_TYPE_REGYMM
, "rYMM" },
2877 { OPERAND_TYPE_REGZMM
, "rZMM" },
2878 { OPERAND_TYPE_REGMASK
, "Mask reg" },
2879 { OPERAND_TYPE_ESSEG
, "es" },
2883 pt (i386_operand_type t
)
2886 i386_operand_type a
;
2888 for (j
= 0; j
< ARRAY_SIZE (type_names
); j
++)
2890 a
= operand_type_and (t
, type_names
[j
].mask
);
2891 if (!operand_type_all_zero (&a
))
2892 fprintf (stdout
, "%s, ", type_names
[j
].name
);
2897 #endif /* DEBUG386 */
2899 static bfd_reloc_code_real_type
2900 reloc (unsigned int size
,
2903 bfd_reloc_code_real_type other
)
2905 if (other
!= NO_RELOC
)
2907 reloc_howto_type
*rel
;
2912 case BFD_RELOC_X86_64_GOT32
:
2913 return BFD_RELOC_X86_64_GOT64
;
2915 case BFD_RELOC_X86_64_GOTPLT64
:
2916 return BFD_RELOC_X86_64_GOTPLT64
;
2918 case BFD_RELOC_X86_64_PLTOFF64
:
2919 return BFD_RELOC_X86_64_PLTOFF64
;
2921 case BFD_RELOC_X86_64_GOTPC32
:
2922 other
= BFD_RELOC_X86_64_GOTPC64
;
2924 case BFD_RELOC_X86_64_GOTPCREL
:
2925 other
= BFD_RELOC_X86_64_GOTPCREL64
;
2927 case BFD_RELOC_X86_64_TPOFF32
:
2928 other
= BFD_RELOC_X86_64_TPOFF64
;
2930 case BFD_RELOC_X86_64_DTPOFF32
:
2931 other
= BFD_RELOC_X86_64_DTPOFF64
;
2937 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2938 if (other
== BFD_RELOC_SIZE32
)
2941 other
= BFD_RELOC_SIZE64
;
2944 as_bad (_("there are no pc-relative size relocations"));
2950 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
2951 if (size
== 4 && (flag_code
!= CODE_64BIT
|| disallow_64bit_reloc
))
2954 rel
= bfd_reloc_type_lookup (stdoutput
, other
);
2956 as_bad (_("unknown relocation (%u)"), other
);
2957 else if (size
!= bfd_get_reloc_size (rel
))
2958 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
2959 bfd_get_reloc_size (rel
),
2961 else if (pcrel
&& !rel
->pc_relative
)
2962 as_bad (_("non-pc-relative relocation for pc-relative field"));
2963 else if ((rel
->complain_on_overflow
== complain_overflow_signed
2965 || (rel
->complain_on_overflow
== complain_overflow_unsigned
2967 as_bad (_("relocated field and relocation type differ in signedness"));
2976 as_bad (_("there are no unsigned pc-relative relocations"));
2979 case 1: return BFD_RELOC_8_PCREL
;
2980 case 2: return BFD_RELOC_16_PCREL
;
2981 case 4: return BFD_RELOC_32_PCREL
;
2982 case 8: return BFD_RELOC_64_PCREL
;
2984 as_bad (_("cannot do %u byte pc-relative relocation"), size
);
2991 case 4: return BFD_RELOC_X86_64_32S
;
2996 case 1: return BFD_RELOC_8
;
2997 case 2: return BFD_RELOC_16
;
2998 case 4: return BFD_RELOC_32
;
2999 case 8: return BFD_RELOC_64
;
3001 as_bad (_("cannot do %s %u byte relocation"),
3002 sign
> 0 ? "signed" : "unsigned", size
);
3008 /* Here we decide which fixups can be adjusted to make them relative to
3009 the beginning of the section instead of the symbol. Basically we need
3010 to make sure that the dynamic relocations are done correctly, so in
3011 some cases we force the original symbol to be used. */
3014 tc_i386_fix_adjustable (fixS
*fixP ATTRIBUTE_UNUSED
)
3016 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3020 /* Don't adjust pc-relative references to merge sections in 64-bit
3022 if (use_rela_relocations
3023 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
3027 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
3028 and changed later by validate_fix. */
3029 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
3030 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
3033 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
3034 for size relocations. */
3035 if (fixP
->fx_r_type
== BFD_RELOC_SIZE32
3036 || fixP
->fx_r_type
== BFD_RELOC_SIZE64
3037 || fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
3038 || fixP
->fx_r_type
== BFD_RELOC_386_PLT32
3039 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
3040 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32X
3041 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
3042 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
3043 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
3044 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
3045 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
3046 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
3047 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
3048 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
3049 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTDESC
3050 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_DESC_CALL
3051 || fixP
->fx_r_type
== BFD_RELOC_X86_64_PLT32
3052 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
3053 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
3054 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCRELX
3055 || fixP
->fx_r_type
== BFD_RELOC_X86_64_REX_GOTPCRELX
3056 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
3057 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
3058 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
3059 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
3060 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
3061 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
3062 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
3063 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
3064 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPC32_TLSDESC
3065 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSDESC_CALL
3066 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
3067 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
3074 intel_float_operand (const char *mnemonic
)
3076 /* Note that the value returned is meaningful only for opcodes with (memory)
3077 operands, hence the code here is free to improperly handle opcodes that
3078 have no operands (for better performance and smaller code). */
3080 if (mnemonic
[0] != 'f')
3081 return 0; /* non-math */
3083 switch (mnemonic
[1])
3085 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
3086 the fs segment override prefix not currently handled because no
3087 call path can make opcodes without operands get here */
3089 return 2 /* integer op */;
3091 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
3092 return 3; /* fldcw/fldenv */
3095 if (mnemonic
[2] != 'o' /* fnop */)
3096 return 3; /* non-waiting control op */
3099 if (mnemonic
[2] == 's')
3100 return 3; /* frstor/frstpm */
3103 if (mnemonic
[2] == 'a')
3104 return 3; /* fsave */
3105 if (mnemonic
[2] == 't')
3107 switch (mnemonic
[3])
3109 case 'c': /* fstcw */
3110 case 'd': /* fstdw */
3111 case 'e': /* fstenv */
3112 case 's': /* fsts[gw] */
3118 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
3119 return 0; /* fxsave/fxrstor are not really math ops */
3126 /* Build the VEX prefix. */
3129 build_vex_prefix (const insn_template
*t
)
3131 unsigned int register_specifier
;
3132 unsigned int implied_prefix
;
3133 unsigned int vector_length
;
3135 /* Check register specifier. */
3136 if (i
.vex
.register_specifier
)
3138 register_specifier
=
3139 ~register_number (i
.vex
.register_specifier
) & 0xf;
3140 gas_assert ((i
.vex
.register_specifier
->reg_flags
& RegVRex
) == 0);
3143 register_specifier
= 0xf;
3145 /* Use 2-byte VEX prefix by swapping destination and source
3148 && i
.operands
== i
.reg_operands
3149 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3150 && i
.tm
.opcode_modifier
.s
3153 unsigned int xchg
= i
.operands
- 1;
3154 union i386_op temp_op
;
3155 i386_operand_type temp_type
;
3157 temp_type
= i
.types
[xchg
];
3158 i
.types
[xchg
] = i
.types
[0];
3159 i
.types
[0] = temp_type
;
3160 temp_op
= i
.op
[xchg
];
3161 i
.op
[xchg
] = i
.op
[0];
3164 gas_assert (i
.rm
.mode
== 3);
3168 i
.rm
.regmem
= i
.rm
.reg
;
3171 /* Use the next insn. */
3175 if (i
.tm
.opcode_modifier
.vex
== VEXScalar
)
3176 vector_length
= avxscalar
;
3178 vector_length
= i
.tm
.opcode_modifier
.vex
== VEX256
? 1 : 0;
3180 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3185 case DATA_PREFIX_OPCODE
:
3188 case REPE_PREFIX_OPCODE
:
3191 case REPNE_PREFIX_OPCODE
:
3198 /* Use 2-byte VEX prefix if possible. */
3199 if (i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3200 && i
.tm
.opcode_modifier
.vexw
!= VEXW1
3201 && (i
.rex
& (REX_W
| REX_X
| REX_B
)) == 0)
3203 /* 2-byte VEX prefix. */
3207 i
.vex
.bytes
[0] = 0xc5;
3209 /* Check the REX.R bit. */
3210 r
= (i
.rex
& REX_R
) ? 0 : 1;
3211 i
.vex
.bytes
[1] = (r
<< 7
3212 | register_specifier
<< 3
3213 | vector_length
<< 2
3218 /* 3-byte VEX prefix. */
3223 switch (i
.tm
.opcode_modifier
.vexopcode
)
3227 i
.vex
.bytes
[0] = 0xc4;
3231 i
.vex
.bytes
[0] = 0xc4;
3235 i
.vex
.bytes
[0] = 0xc4;
3239 i
.vex
.bytes
[0] = 0x8f;
3243 i
.vex
.bytes
[0] = 0x8f;
3247 i
.vex
.bytes
[0] = 0x8f;
3253 /* The high 3 bits of the second VEX byte are 1's compliment
3254 of RXB bits from REX. */
3255 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3257 /* Check the REX.W bit. */
3258 w
= (i
.rex
& REX_W
) ? 1 : 0;
3259 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
3262 i
.vex
.bytes
[2] = (w
<< 7
3263 | register_specifier
<< 3
3264 | vector_length
<< 2
3269 /* Build the EVEX prefix. */
3272 build_evex_prefix (void)
3274 unsigned int register_specifier
;
3275 unsigned int implied_prefix
;
3277 rex_byte vrex_used
= 0;
3279 /* Check register specifier. */
3280 if (i
.vex
.register_specifier
)
3282 gas_assert ((i
.vrex
& REX_X
) == 0);
3284 register_specifier
= i
.vex
.register_specifier
->reg_num
;
3285 if ((i
.vex
.register_specifier
->reg_flags
& RegRex
))
3286 register_specifier
+= 8;
3287 /* The upper 16 registers are encoded in the fourth byte of the
3289 if (!(i
.vex
.register_specifier
->reg_flags
& RegVRex
))
3290 i
.vex
.bytes
[3] = 0x8;
3291 register_specifier
= ~register_specifier
& 0xf;
3295 register_specifier
= 0xf;
3297 /* Encode upper 16 vector index register in the fourth byte of
3299 if (!(i
.vrex
& REX_X
))
3300 i
.vex
.bytes
[3] = 0x8;
3305 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3310 case DATA_PREFIX_OPCODE
:
3313 case REPE_PREFIX_OPCODE
:
3316 case REPNE_PREFIX_OPCODE
:
3323 /* 4 byte EVEX prefix. */
3325 i
.vex
.bytes
[0] = 0x62;
3328 switch (i
.tm
.opcode_modifier
.vexopcode
)
3344 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3346 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3348 /* The fifth bit of the second EVEX byte is 1's compliment of the
3349 REX_R bit in VREX. */
3350 if (!(i
.vrex
& REX_R
))
3351 i
.vex
.bytes
[1] |= 0x10;
3355 if ((i
.reg_operands
+ i
.imm_operands
) == i
.operands
)
3357 /* When all operands are registers, the REX_X bit in REX is not
3358 used. We reuse it to encode the upper 16 registers, which is
3359 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3360 as 1's compliment. */
3361 if ((i
.vrex
& REX_B
))
3364 i
.vex
.bytes
[1] &= ~0x40;
3368 /* EVEX instructions shouldn't need the REX prefix. */
3369 i
.vrex
&= ~vrex_used
;
3370 gas_assert (i
.vrex
== 0);
3372 /* Check the REX.W bit. */
3373 w
= (i
.rex
& REX_W
) ? 1 : 0;
3374 if (i
.tm
.opcode_modifier
.vexw
)
3376 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
3379 /* If w is not set it means we are dealing with WIG instruction. */
3382 if (evexwig
== evexw1
)
3386 /* Encode the U bit. */
3387 implied_prefix
|= 0x4;
3389 /* The third byte of the EVEX prefix. */
3390 i
.vex
.bytes
[2] = (w
<< 7 | register_specifier
<< 3 | implied_prefix
);
3392 /* The fourth byte of the EVEX prefix. */
3393 /* The zeroing-masking bit. */
3394 if (i
.mask
&& i
.mask
->zeroing
)
3395 i
.vex
.bytes
[3] |= 0x80;
3397 /* Don't always set the broadcast bit if there is no RC. */
3400 /* Encode the vector length. */
3401 unsigned int vec_length
;
3403 switch (i
.tm
.opcode_modifier
.evex
)
3405 case EVEXLIG
: /* LL' is ignored */
3406 vec_length
= evexlig
<< 5;
3409 vec_length
= 0 << 5;
3412 vec_length
= 1 << 5;
3415 vec_length
= 2 << 5;
3421 i
.vex
.bytes
[3] |= vec_length
;
3422 /* Encode the broadcast bit. */
3424 i
.vex
.bytes
[3] |= 0x10;
3428 if (i
.rounding
->type
!= saeonly
)
3429 i
.vex
.bytes
[3] |= 0x10 | (i
.rounding
->type
<< 5);
3431 i
.vex
.bytes
[3] |= 0x10 | (evexrcig
<< 5);
3434 if (i
.mask
&& i
.mask
->mask
)
3435 i
.vex
.bytes
[3] |= i
.mask
->mask
->reg_num
;
3439 process_immext (void)
3443 if ((i
.tm
.cpu_flags
.bitfield
.cpusse3
|| i
.tm
.cpu_flags
.bitfield
.cpusvme
)
3446 /* MONITOR/MWAIT as well as SVME instructions have fixed operands
3447 with an opcode suffix which is coded in the same place as an
3448 8-bit immediate field would be.
3449 Here we check those operands and remove them afterwards. */
3452 for (x
= 0; x
< i
.operands
; x
++)
3453 if (register_number (i
.op
[x
].regs
) != x
)
3454 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3455 register_prefix
, i
.op
[x
].regs
->reg_name
, x
+ 1,
3461 if (i
.tm
.cpu_flags
.bitfield
.cpumwaitx
&& i
.operands
> 0)
3463 /* MONITORX/MWAITX instructions have fixed operands with an opcode
3464 suffix which is coded in the same place as an 8-bit immediate
3466 Here we check those operands and remove them afterwards. */
3469 if (i
.operands
!= 3)
3472 for (x
= 0; x
< 2; x
++)
3473 if (register_number (i
.op
[x
].regs
) != x
)
3474 goto bad_register_operand
;
3476 /* Check for third operand for mwaitx/monitorx insn. */
3477 if (register_number (i
.op
[x
].regs
)
3478 != (x
+ (i
.tm
.extension_opcode
== 0xfb)))
3480 bad_register_operand
:
3481 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3482 register_prefix
, i
.op
[x
].regs
->reg_name
, x
+1,
3489 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
3490 which is coded in the same place as an 8-bit immediate field
3491 would be. Here we fake an 8-bit immediate operand from the
3492 opcode suffix stored in tm.extension_opcode.
3494 AVX instructions also use this encoding, for some of
3495 3 argument instructions. */
3497 gas_assert (i
.imm_operands
<= 1
3499 || ((i
.tm
.opcode_modifier
.vex
3500 || i
.tm
.opcode_modifier
.evex
)
3501 && i
.operands
<= 4)));
3503 exp
= &im_expressions
[i
.imm_operands
++];
3504 i
.op
[i
.operands
].imms
= exp
;
3505 i
.types
[i
.operands
] = imm8
;
3507 exp
->X_op
= O_constant
;
3508 exp
->X_add_number
= i
.tm
.extension_opcode
;
3509 i
.tm
.extension_opcode
= None
;
3516 switch (i
.tm
.opcode_modifier
.hleprefixok
)
3521 as_bad (_("invalid instruction `%s' after `%s'"),
3522 i
.tm
.name
, i
.hle_prefix
);
3525 if (i
.prefix
[LOCK_PREFIX
])
3527 as_bad (_("missing `lock' with `%s'"), i
.hle_prefix
);
3531 case HLEPrefixRelease
:
3532 if (i
.prefix
[HLE_PREFIX
] != XRELEASE_PREFIX_OPCODE
)
3534 as_bad (_("instruction `%s' after `xacquire' not allowed"),
3538 if (i
.mem_operands
== 0
3539 || !operand_type_check (i
.types
[i
.operands
- 1], anymem
))
3541 as_bad (_("memory destination needed for instruction `%s'"
3542 " after `xrelease'"), i
.tm
.name
);
3549 /* This is the guts of the machine-dependent assembler. LINE points to a
3550 machine dependent instruction. This function is supposed to emit
3551 the frags/bytes it assembles to. */
3554 md_assemble (char *line
)
3557 char mnemonic
[MAX_MNEM_SIZE
], mnem_suffix
;
3558 const insn_template
*t
;
3560 /* Initialize globals. */
3561 memset (&i
, '\0', sizeof (i
));
3562 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3563 i
.reloc
[j
] = NO_RELOC
;
3564 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
3565 memset (im_expressions
, '\0', sizeof (im_expressions
));
3566 save_stack_p
= save_stack
;
3568 /* First parse an instruction mnemonic & call i386_operand for the operands.
3569 We assume that the scrubber has arranged it so that line[0] is the valid
3570 start of a (possibly prefixed) mnemonic. */
3572 line
= parse_insn (line
, mnemonic
);
3575 mnem_suffix
= i
.suffix
;
3577 line
= parse_operands (line
, mnemonic
);
3579 xfree (i
.memop1_string
);
3580 i
.memop1_string
= NULL
;
3584 /* Now we've parsed the mnemonic into a set of templates, and have the
3585 operands at hand. */
3587 /* All intel opcodes have reversed operands except for "bound" and
3588 "enter". We also don't reverse intersegment "jmp" and "call"
3589 instructions with 2 immediate operands so that the immediate segment
3590 precedes the offset, as it does when in AT&T mode. */
3593 && (strcmp (mnemonic
, "bound") != 0)
3594 && (strcmp (mnemonic
, "invlpga") != 0)
3595 && !(operand_type_check (i
.types
[0], imm
)
3596 && operand_type_check (i
.types
[1], imm
)))
3599 /* The order of the immediates should be reversed
3600 for 2 immediates extrq and insertq instructions */
3601 if (i
.imm_operands
== 2
3602 && (strcmp (mnemonic
, "extrq") == 0
3603 || strcmp (mnemonic
, "insertq") == 0))
3604 swap_2_operands (0, 1);
3609 /* Don't optimize displacement for movabs since it only takes 64bit
3612 && i
.disp_encoding
!= disp_encoding_32bit
3613 && (flag_code
!= CODE_64BIT
3614 || strcmp (mnemonic
, "movabs") != 0))
3617 /* Next, we find a template that matches the given insn,
3618 making sure the overlap of the given operands types is consistent
3619 with the template operand types. */
3621 if (!(t
= match_template (mnem_suffix
)))
3624 if (sse_check
!= check_none
3625 && !i
.tm
.opcode_modifier
.noavx
3626 && (i
.tm
.cpu_flags
.bitfield
.cpusse
3627 || i
.tm
.cpu_flags
.bitfield
.cpusse2
3628 || i
.tm
.cpu_flags
.bitfield
.cpusse3
3629 || i
.tm
.cpu_flags
.bitfield
.cpussse3
3630 || i
.tm
.cpu_flags
.bitfield
.cpusse4_1
3631 || i
.tm
.cpu_flags
.bitfield
.cpusse4_2
))
3633 (sse_check
== check_warning
3635 : as_bad
) (_("SSE instruction `%s' is used"), i
.tm
.name
);
3638 /* Zap movzx and movsx suffix. The suffix has been set from
3639 "word ptr" or "byte ptr" on the source operand in Intel syntax
3640 or extracted from mnemonic in AT&T syntax. But we'll use
3641 the destination register to choose the suffix for encoding. */
3642 if ((i
.tm
.base_opcode
& ~9) == 0x0fb6)
3644 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
3645 there is no suffix, the default will be byte extension. */
3646 if (i
.reg_operands
!= 2
3649 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
3654 if (i
.tm
.opcode_modifier
.fwait
)
3655 if (!add_prefix (FWAIT_OPCODE
))
3658 /* Check if REP prefix is OK. */
3659 if (i
.rep_prefix
&& !i
.tm
.opcode_modifier
.repprefixok
)
3661 as_bad (_("invalid instruction `%s' after `%s'"),
3662 i
.tm
.name
, i
.rep_prefix
);
3666 /* Check for lock without a lockable instruction. Destination operand
3667 must be memory unless it is xchg (0x86). */
3668 if (i
.prefix
[LOCK_PREFIX
]
3669 && (!i
.tm
.opcode_modifier
.islockable
3670 || i
.mem_operands
== 0
3671 || (i
.tm
.base_opcode
!= 0x86
3672 && !operand_type_check (i
.types
[i
.operands
- 1], anymem
))))
3674 as_bad (_("expecting lockable instruction after `lock'"));
3678 /* Check if HLE prefix is OK. */
3679 if (i
.hle_prefix
&& !check_hle ())
3682 /* Check BND prefix. */
3683 if (i
.bnd_prefix
&& !i
.tm
.opcode_modifier
.bndprefixok
)
3684 as_bad (_("expecting valid branch instruction after `bnd'"));
3686 if (i
.tm
.cpu_flags
.bitfield
.cpumpx
)
3688 if (flag_code
== CODE_64BIT
&& i
.prefix
[ADDR_PREFIX
])
3689 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
3690 else if (flag_code
!= CODE_16BIT
3691 ? i
.prefix
[ADDR_PREFIX
]
3692 : i
.mem_operands
&& !i
.prefix
[ADDR_PREFIX
])
3693 as_bad (_("16-bit address isn't allowed in MPX instructions"));
3696 /* Insert BND prefix. */
3698 && i
.tm
.opcode_modifier
.bndprefixok
3699 && !i
.prefix
[BND_PREFIX
])
3700 add_prefix (BND_PREFIX_OPCODE
);
3702 /* Check string instruction segment overrides. */
3703 if (i
.tm
.opcode_modifier
.isstring
&& i
.mem_operands
!= 0)
3705 if (!check_string ())
3707 i
.disp_operands
= 0;
3710 if (!process_suffix ())
3713 /* Update operand types. */
3714 for (j
= 0; j
< i
.operands
; j
++)
3715 i
.types
[j
] = operand_type_and (i
.types
[j
], i
.tm
.operand_types
[j
]);
3717 /* Make still unresolved immediate matches conform to size of immediate
3718 given in i.suffix. */
3719 if (!finalize_imm ())
3722 if (i
.types
[0].bitfield
.imm1
)
3723 i
.imm_operands
= 0; /* kludge for shift insns. */
3725 /* We only need to check those implicit registers for instructions
3726 with 3 operands or less. */
3727 if (i
.operands
<= 3)
3728 for (j
= 0; j
< i
.operands
; j
++)
3729 if (i
.types
[j
].bitfield
.inoutportreg
3730 || i
.types
[j
].bitfield
.shiftcount
3731 || i
.types
[j
].bitfield
.acc
3732 || i
.types
[j
].bitfield
.floatacc
)
3735 /* ImmExt should be processed after SSE2AVX. */
3736 if (!i
.tm
.opcode_modifier
.sse2avx
3737 && i
.tm
.opcode_modifier
.immext
)
3740 /* For insns with operands there are more diddles to do to the opcode. */
3743 if (!process_operands ())
3746 else if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
3748 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
3749 as_warn (_("translating to `%sp'"), i
.tm
.name
);
3752 if (i
.tm
.opcode_modifier
.vex
|| i
.tm
.opcode_modifier
.evex
)
3754 if (flag_code
== CODE_16BIT
)
3756 as_bad (_("instruction `%s' isn't supported in 16-bit mode."),
3761 if (i
.tm
.opcode_modifier
.vex
)
3762 build_vex_prefix (t
);
3764 build_evex_prefix ();
3767 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
3768 instructions may define INT_OPCODE as well, so avoid this corner
3769 case for those instructions that use MODRM. */
3770 if (i
.tm
.base_opcode
== INT_OPCODE
3771 && !i
.tm
.opcode_modifier
.modrm
3772 && i
.op
[0].imms
->X_add_number
== 3)
3774 i
.tm
.base_opcode
= INT3_OPCODE
;
3778 if ((i
.tm
.opcode_modifier
.jump
3779 || i
.tm
.opcode_modifier
.jumpbyte
3780 || i
.tm
.opcode_modifier
.jumpdword
)
3781 && i
.op
[0].disps
->X_op
== O_constant
)
3783 /* Convert "jmp constant" (and "call constant") to a jump (call) to
3784 the absolute address given by the constant. Since ix86 jumps and
3785 calls are pc relative, we need to generate a reloc. */
3786 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
3787 i
.op
[0].disps
->X_op
= O_symbol
;
3790 if (i
.tm
.opcode_modifier
.rex64
)
3793 /* For 8 bit registers we need an empty rex prefix. Also if the
3794 instruction already has a prefix, we need to convert old
3795 registers to new ones. */
3797 if ((i
.types
[0].bitfield
.reg8
3798 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
3799 || (i
.types
[1].bitfield
.reg8
3800 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
3801 || ((i
.types
[0].bitfield
.reg8
3802 || i
.types
[1].bitfield
.reg8
)
3807 i
.rex
|= REX_OPCODE
;
3808 for (x
= 0; x
< 2; x
++)
3810 /* Look for 8 bit operand that uses old registers. */
3811 if (i
.types
[x
].bitfield
.reg8
3812 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
3814 /* In case it is "hi" register, give up. */
3815 if (i
.op
[x
].regs
->reg_num
> 3)
3816 as_bad (_("can't encode register '%s%s' in an "
3817 "instruction requiring REX prefix."),
3818 register_prefix
, i
.op
[x
].regs
->reg_name
);
3820 /* Otherwise it is equivalent to the extended register.
3821 Since the encoding doesn't change this is merely
3822 cosmetic cleanup for debug output. */
3824 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
3830 add_prefix (REX_OPCODE
| i
.rex
);
3832 /* We are ready to output the insn. */
3837 parse_insn (char *line
, char *mnemonic
)
3840 char *token_start
= l
;
3843 const insn_template
*t
;
3849 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
3854 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
3856 as_bad (_("no such instruction: `%s'"), token_start
);
3861 if (!is_space_char (*l
)
3862 && *l
!= END_OF_INSN
3864 || (*l
!= PREFIX_SEPARATOR
3867 as_bad (_("invalid character %s in mnemonic"),
3868 output_invalid (*l
));
3871 if (token_start
== l
)
3873 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
3874 as_bad (_("expecting prefix; got nothing"));
3876 as_bad (_("expecting mnemonic; got nothing"));
3880 /* Look up instruction (or prefix) via hash table. */
3881 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
3883 if (*l
!= END_OF_INSN
3884 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
3885 && current_templates
3886 && current_templates
->start
->opcode_modifier
.isprefix
)
3888 if (!cpu_flags_check_cpu64 (current_templates
->start
->cpu_flags
))
3890 as_bad ((flag_code
!= CODE_64BIT
3891 ? _("`%s' is only supported in 64-bit mode")
3892 : _("`%s' is not supported in 64-bit mode")),
3893 current_templates
->start
->name
);
3896 /* If we are in 16-bit mode, do not allow addr16 or data16.
3897 Similarly, in 32-bit mode, do not allow addr32 or data32. */
3898 if ((current_templates
->start
->opcode_modifier
.size16
3899 || current_templates
->start
->opcode_modifier
.size32
)
3900 && flag_code
!= CODE_64BIT
3901 && (current_templates
->start
->opcode_modifier
.size32
3902 ^ (flag_code
== CODE_16BIT
)))
3904 as_bad (_("redundant %s prefix"),
3905 current_templates
->start
->name
);
3908 /* Add prefix, checking for repeated prefixes. */
3909 switch (add_prefix (current_templates
->start
->base_opcode
))
3914 if (current_templates
->start
->cpu_flags
.bitfield
.cpuhle
)
3915 i
.hle_prefix
= current_templates
->start
->name
;
3916 else if (current_templates
->start
->cpu_flags
.bitfield
.cpumpx
)
3917 i
.bnd_prefix
= current_templates
->start
->name
;
3919 i
.rep_prefix
= current_templates
->start
->name
;
3924 /* Skip past PREFIX_SEPARATOR and reset token_start. */
3931 if (!current_templates
)
3933 /* Check if we should swap operand or force 32bit displacement in
3935 if (mnem_p
- 2 == dot_p
&& dot_p
[1] == 's')
3937 else if (mnem_p
- 3 == dot_p
3940 i
.disp_encoding
= disp_encoding_8bit
;
3941 else if (mnem_p
- 4 == dot_p
3945 i
.disp_encoding
= disp_encoding_32bit
;
3950 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
3953 if (!current_templates
)
3956 /* See if we can get a match by trimming off a suffix. */
3959 case WORD_MNEM_SUFFIX
:
3960 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
3961 i
.suffix
= SHORT_MNEM_SUFFIX
;
3964 case BYTE_MNEM_SUFFIX
:
3965 case QWORD_MNEM_SUFFIX
:
3966 i
.suffix
= mnem_p
[-1];
3968 current_templates
= (const templates
*) hash_find (op_hash
,
3971 case SHORT_MNEM_SUFFIX
:
3972 case LONG_MNEM_SUFFIX
:
3975 i
.suffix
= mnem_p
[-1];
3977 current_templates
= (const templates
*) hash_find (op_hash
,
3986 if (intel_float_operand (mnemonic
) == 1)
3987 i
.suffix
= SHORT_MNEM_SUFFIX
;
3989 i
.suffix
= LONG_MNEM_SUFFIX
;
3991 current_templates
= (const templates
*) hash_find (op_hash
,
3996 if (!current_templates
)
3998 as_bad (_("no such instruction: `%s'"), token_start
);
4003 if (current_templates
->start
->opcode_modifier
.jump
4004 || current_templates
->start
->opcode_modifier
.jumpbyte
)
4006 /* Check for a branch hint. We allow ",pt" and ",pn" for
4007 predict taken and predict not taken respectively.
4008 I'm not sure that branch hints actually do anything on loop
4009 and jcxz insns (JumpByte) for current Pentium4 chips. They
4010 may work in the future and it doesn't hurt to accept them
4012 if (l
[0] == ',' && l
[1] == 'p')
4016 if (!add_prefix (DS_PREFIX_OPCODE
))
4020 else if (l
[2] == 'n')
4022 if (!add_prefix (CS_PREFIX_OPCODE
))
4028 /* Any other comma loses. */
4031 as_bad (_("invalid character %s in mnemonic"),
4032 output_invalid (*l
));
4036 /* Check if instruction is supported on specified architecture. */
4038 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
4040 supported
|= cpu_flags_match (t
);
4041 if (supported
== CPU_FLAGS_PERFECT_MATCH
)
4045 if (!(supported
& CPU_FLAGS_64BIT_MATCH
))
4047 as_bad (flag_code
== CODE_64BIT
4048 ? _("`%s' is not supported in 64-bit mode")
4049 : _("`%s' is only supported in 64-bit mode"),
4050 current_templates
->start
->name
);
4053 if (supported
!= CPU_FLAGS_PERFECT_MATCH
)
4055 as_bad (_("`%s' is not supported on `%s%s'"),
4056 current_templates
->start
->name
,
4057 cpu_arch_name
? cpu_arch_name
: default_arch
,
4058 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
4063 if (!cpu_arch_flags
.bitfield
.cpui386
4064 && (flag_code
!= CODE_16BIT
))
4066 as_warn (_("use .code16 to ensure correct addressing mode"));
4073 parse_operands (char *l
, const char *mnemonic
)
4077 /* 1 if operand is pending after ','. */
4078 unsigned int expecting_operand
= 0;
4080 /* Non-zero if operand parens not balanced. */
4081 unsigned int paren_not_balanced
;
4083 while (*l
!= END_OF_INSN
)
4085 /* Skip optional white space before operand. */
4086 if (is_space_char (*l
))
4088 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
&& *l
!= '"')
4090 as_bad (_("invalid character %s before operand %d"),
4091 output_invalid (*l
),
4095 token_start
= l
; /* After white space. */
4096 paren_not_balanced
= 0;
4097 while (paren_not_balanced
|| *l
!= ',')
4099 if (*l
== END_OF_INSN
)
4101 if (paren_not_balanced
)
4104 as_bad (_("unbalanced parenthesis in operand %d."),
4107 as_bad (_("unbalanced brackets in operand %d."),
4112 break; /* we are done */
4114 else if (!is_operand_char (*l
) && !is_space_char (*l
) && *l
!= '"')
4116 as_bad (_("invalid character %s in operand %d"),
4117 output_invalid (*l
),
4124 ++paren_not_balanced
;
4126 --paren_not_balanced
;
4131 ++paren_not_balanced
;
4133 --paren_not_balanced
;
4137 if (l
!= token_start
)
4138 { /* Yes, we've read in another operand. */
4139 unsigned int operand_ok
;
4140 this_operand
= i
.operands
++;
4141 if (i
.operands
> MAX_OPERANDS
)
4143 as_bad (_("spurious operands; (%d operands/instruction max)"),
4147 i
.types
[this_operand
].bitfield
.unspecified
= 1;
4148 /* Now parse operand adding info to 'i' as we go along. */
4149 END_STRING_AND_SAVE (l
);
4153 i386_intel_operand (token_start
,
4154 intel_float_operand (mnemonic
));
4156 operand_ok
= i386_att_operand (token_start
);
4158 RESTORE_END_STRING (l
);
4164 if (expecting_operand
)
4166 expecting_operand_after_comma
:
4167 as_bad (_("expecting operand after ','; got nothing"));
4172 as_bad (_("expecting operand before ','; got nothing"));
4177 /* Now *l must be either ',' or END_OF_INSN. */
4180 if (*++l
== END_OF_INSN
)
4182 /* Just skip it, if it's \n complain. */
4183 goto expecting_operand_after_comma
;
4185 expecting_operand
= 1;
4192 swap_2_operands (int xchg1
, int xchg2
)
4194 union i386_op temp_op
;
4195 i386_operand_type temp_type
;
4196 enum bfd_reloc_code_real temp_reloc
;
4198 temp_type
= i
.types
[xchg2
];
4199 i
.types
[xchg2
] = i
.types
[xchg1
];
4200 i
.types
[xchg1
] = temp_type
;
4201 temp_op
= i
.op
[xchg2
];
4202 i
.op
[xchg2
] = i
.op
[xchg1
];
4203 i
.op
[xchg1
] = temp_op
;
4204 temp_reloc
= i
.reloc
[xchg2
];
4205 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
4206 i
.reloc
[xchg1
] = temp_reloc
;
4210 if (i
.mask
->operand
== xchg1
)
4211 i
.mask
->operand
= xchg2
;
4212 else if (i
.mask
->operand
== xchg2
)
4213 i
.mask
->operand
= xchg1
;
4217 if (i
.broadcast
->operand
== xchg1
)
4218 i
.broadcast
->operand
= xchg2
;
4219 else if (i
.broadcast
->operand
== xchg2
)
4220 i
.broadcast
->operand
= xchg1
;
4224 if (i
.rounding
->operand
== xchg1
)
4225 i
.rounding
->operand
= xchg2
;
4226 else if (i
.rounding
->operand
== xchg2
)
4227 i
.rounding
->operand
= xchg1
;
4232 swap_operands (void)
4238 swap_2_operands (1, i
.operands
- 2);
4242 swap_2_operands (0, i
.operands
- 1);
4248 if (i
.mem_operands
== 2)
4250 const seg_entry
*temp_seg
;
4251 temp_seg
= i
.seg
[0];
4252 i
.seg
[0] = i
.seg
[1];
4253 i
.seg
[1] = temp_seg
;
4257 /* Try to ensure constant immediates are represented in the smallest
4262 char guess_suffix
= 0;
4266 guess_suffix
= i
.suffix
;
4267 else if (i
.reg_operands
)
4269 /* Figure out a suffix from the last register operand specified.
4270 We can't do this properly yet, ie. excluding InOutPortReg,
4271 but the following works for instructions with immediates.
4272 In any case, we can't set i.suffix yet. */
4273 for (op
= i
.operands
; --op
>= 0;)
4274 if (i
.types
[op
].bitfield
.reg8
)
4276 guess_suffix
= BYTE_MNEM_SUFFIX
;
4279 else if (i
.types
[op
].bitfield
.reg16
)
4281 guess_suffix
= WORD_MNEM_SUFFIX
;
4284 else if (i
.types
[op
].bitfield
.reg32
)
4286 guess_suffix
= LONG_MNEM_SUFFIX
;
4289 else if (i
.types
[op
].bitfield
.reg64
)
4291 guess_suffix
= QWORD_MNEM_SUFFIX
;
4295 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
4296 guess_suffix
= WORD_MNEM_SUFFIX
;
4298 for (op
= i
.operands
; --op
>= 0;)
4299 if (operand_type_check (i
.types
[op
], imm
))
4301 switch (i
.op
[op
].imms
->X_op
)
4304 /* If a suffix is given, this operand may be shortened. */
4305 switch (guess_suffix
)
4307 case LONG_MNEM_SUFFIX
:
4308 i
.types
[op
].bitfield
.imm32
= 1;
4309 i
.types
[op
].bitfield
.imm64
= 1;
4311 case WORD_MNEM_SUFFIX
:
4312 i
.types
[op
].bitfield
.imm16
= 1;
4313 i
.types
[op
].bitfield
.imm32
= 1;
4314 i
.types
[op
].bitfield
.imm32s
= 1;
4315 i
.types
[op
].bitfield
.imm64
= 1;
4317 case BYTE_MNEM_SUFFIX
:
4318 i
.types
[op
].bitfield
.imm8
= 1;
4319 i
.types
[op
].bitfield
.imm8s
= 1;
4320 i
.types
[op
].bitfield
.imm16
= 1;
4321 i
.types
[op
].bitfield
.imm32
= 1;
4322 i
.types
[op
].bitfield
.imm32s
= 1;
4323 i
.types
[op
].bitfield
.imm64
= 1;
4327 /* If this operand is at most 16 bits, convert it
4328 to a signed 16 bit number before trying to see
4329 whether it will fit in an even smaller size.
4330 This allows a 16-bit operand such as $0xffe0 to
4331 be recognised as within Imm8S range. */
4332 if ((i
.types
[op
].bitfield
.imm16
)
4333 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
4335 i
.op
[op
].imms
->X_add_number
=
4336 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
4339 /* Store 32-bit immediate in 64-bit for 64-bit BFD. */
4340 if ((i
.types
[op
].bitfield
.imm32
)
4341 && ((i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1))
4344 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
4345 ^ ((offsetT
) 1 << 31))
4346 - ((offsetT
) 1 << 31));
4350 = operand_type_or (i
.types
[op
],
4351 smallest_imm_type (i
.op
[op
].imms
->X_add_number
));
4353 /* We must avoid matching of Imm32 templates when 64bit
4354 only immediate is available. */
4355 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
4356 i
.types
[op
].bitfield
.imm32
= 0;
4363 /* Symbols and expressions. */
4365 /* Convert symbolic operand to proper sizes for matching, but don't
4366 prevent matching a set of insns that only supports sizes other
4367 than those matching the insn suffix. */
4369 i386_operand_type mask
, allowed
;
4370 const insn_template
*t
;
4372 operand_type_set (&mask
, 0);
4373 operand_type_set (&allowed
, 0);
4375 for (t
= current_templates
->start
;
4376 t
< current_templates
->end
;
4378 allowed
= operand_type_or (allowed
,
4379 t
->operand_types
[op
]);
4380 switch (guess_suffix
)
4382 case QWORD_MNEM_SUFFIX
:
4383 mask
.bitfield
.imm64
= 1;
4384 mask
.bitfield
.imm32s
= 1;
4386 case LONG_MNEM_SUFFIX
:
4387 mask
.bitfield
.imm32
= 1;
4389 case WORD_MNEM_SUFFIX
:
4390 mask
.bitfield
.imm16
= 1;
4392 case BYTE_MNEM_SUFFIX
:
4393 mask
.bitfield
.imm8
= 1;
4398 allowed
= operand_type_and (mask
, allowed
);
4399 if (!operand_type_all_zero (&allowed
))
4400 i
.types
[op
] = operand_type_and (i
.types
[op
], mask
);
4407 /* Try to use the smallest displacement type too. */
4409 optimize_disp (void)
4413 for (op
= i
.operands
; --op
>= 0;)
4414 if (operand_type_check (i
.types
[op
], disp
))
4416 if (i
.op
[op
].disps
->X_op
== O_constant
)
4418 offsetT op_disp
= i
.op
[op
].disps
->X_add_number
;
4420 if (i
.types
[op
].bitfield
.disp16
4421 && (op_disp
& ~(offsetT
) 0xffff) == 0)
4423 /* If this operand is at most 16 bits, convert
4424 to a signed 16 bit number and don't use 64bit
4426 op_disp
= (((op_disp
& 0xffff) ^ 0x8000) - 0x8000);
4427 i
.types
[op
].bitfield
.disp64
= 0;
4430 /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */
4431 if (i
.types
[op
].bitfield
.disp32
4432 && (op_disp
& ~(((offsetT
) 2 << 31) - 1)) == 0)
4434 /* If this operand is at most 32 bits, convert
4435 to a signed 32 bit number and don't use 64bit
4437 op_disp
&= (((offsetT
) 2 << 31) - 1);
4438 op_disp
= (op_disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
4439 i
.types
[op
].bitfield
.disp64
= 0;
4442 if (!op_disp
&& i
.types
[op
].bitfield
.baseindex
)
4444 i
.types
[op
].bitfield
.disp8
= 0;
4445 i
.types
[op
].bitfield
.disp16
= 0;
4446 i
.types
[op
].bitfield
.disp32
= 0;
4447 i
.types
[op
].bitfield
.disp32s
= 0;
4448 i
.types
[op
].bitfield
.disp64
= 0;
4452 else if (flag_code
== CODE_64BIT
)
4454 if (fits_in_signed_long (op_disp
))
4456 i
.types
[op
].bitfield
.disp64
= 0;
4457 i
.types
[op
].bitfield
.disp32s
= 1;
4459 if (i
.prefix
[ADDR_PREFIX
]
4460 && fits_in_unsigned_long (op_disp
))
4461 i
.types
[op
].bitfield
.disp32
= 1;
4463 if ((i
.types
[op
].bitfield
.disp32
4464 || i
.types
[op
].bitfield
.disp32s
4465 || i
.types
[op
].bitfield
.disp16
)
4466 && fits_in_signed_byte (op_disp
))
4467 i
.types
[op
].bitfield
.disp8
= 1;
4469 else if (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
4470 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
)
4472 fix_new_exp (frag_now
, frag_more (0) - frag_now
->fr_literal
, 0,
4473 i
.op
[op
].disps
, 0, i
.reloc
[op
]);
4474 i
.types
[op
].bitfield
.disp8
= 0;
4475 i
.types
[op
].bitfield
.disp16
= 0;
4476 i
.types
[op
].bitfield
.disp32
= 0;
4477 i
.types
[op
].bitfield
.disp32s
= 0;
4478 i
.types
[op
].bitfield
.disp64
= 0;
4481 /* We only support 64bit displacement on constants. */
4482 i
.types
[op
].bitfield
.disp64
= 0;
4486 /* Check if operands are valid for the instruction. */
4489 check_VecOperands (const insn_template
*t
)
4493 /* Without VSIB byte, we can't have a vector register for index. */
4494 if (!t
->opcode_modifier
.vecsib
4496 && (i
.index_reg
->reg_type
.bitfield
.regxmm
4497 || i
.index_reg
->reg_type
.bitfield
.regymm
4498 || i
.index_reg
->reg_type
.bitfield
.regzmm
))
4500 i
.error
= unsupported_vector_index_register
;
4504 /* Check if default mask is allowed. */
4505 if (t
->opcode_modifier
.nodefmask
4506 && (!i
.mask
|| i
.mask
->mask
->reg_num
== 0))
4508 i
.error
= no_default_mask
;
4512 /* For VSIB byte, we need a vector register for index, and all vector
4513 registers must be distinct. */
4514 if (t
->opcode_modifier
.vecsib
)
4517 || !((t
->opcode_modifier
.vecsib
== VecSIB128
4518 && i
.index_reg
->reg_type
.bitfield
.regxmm
)
4519 || (t
->opcode_modifier
.vecsib
== VecSIB256
4520 && i
.index_reg
->reg_type
.bitfield
.regymm
)
4521 || (t
->opcode_modifier
.vecsib
== VecSIB512
4522 && i
.index_reg
->reg_type
.bitfield
.regzmm
)))
4524 i
.error
= invalid_vsib_address
;
4528 gas_assert (i
.reg_operands
== 2 || i
.mask
);
4529 if (i
.reg_operands
== 2 && !i
.mask
)
4531 gas_assert (i
.types
[0].bitfield
.regxmm
4532 || i
.types
[0].bitfield
.regymm
);
4533 gas_assert (i
.types
[2].bitfield
.regxmm
4534 || i
.types
[2].bitfield
.regymm
);
4535 if (operand_check
== check_none
)
4537 if (register_number (i
.op
[0].regs
)
4538 != register_number (i
.index_reg
)
4539 && register_number (i
.op
[2].regs
)
4540 != register_number (i
.index_reg
)
4541 && register_number (i
.op
[0].regs
)
4542 != register_number (i
.op
[2].regs
))
4544 if (operand_check
== check_error
)
4546 i
.error
= invalid_vector_register_set
;
4549 as_warn (_("mask, index, and destination registers should be distinct"));
4551 else if (i
.reg_operands
== 1 && i
.mask
)
4553 if ((i
.types
[1].bitfield
.regymm
4554 || i
.types
[1].bitfield
.regzmm
)
4555 && (register_number (i
.op
[1].regs
)
4556 == register_number (i
.index_reg
)))
4558 if (operand_check
== check_error
)
4560 i
.error
= invalid_vector_register_set
;
4563 if (operand_check
!= check_none
)
4564 as_warn (_("index and destination registers should be distinct"));
4569 /* Check if broadcast is supported by the instruction and is applied
4570 to the memory operand. */
4573 int broadcasted_opnd_size
;
4575 /* Check if specified broadcast is supported in this instruction,
4576 and it's applied to memory operand of DWORD or QWORD type,
4577 depending on VecESize. */
4578 if (i
.broadcast
->type
!= t
->opcode_modifier
.broadcast
4579 || !i
.types
[i
.broadcast
->operand
].bitfield
.mem
4580 || (t
->opcode_modifier
.vecesize
== 0
4581 && !i
.types
[i
.broadcast
->operand
].bitfield
.dword
4582 && !i
.types
[i
.broadcast
->operand
].bitfield
.unspecified
)
4583 || (t
->opcode_modifier
.vecesize
== 1
4584 && !i
.types
[i
.broadcast
->operand
].bitfield
.qword
4585 && !i
.types
[i
.broadcast
->operand
].bitfield
.unspecified
))
4588 broadcasted_opnd_size
= t
->opcode_modifier
.vecesize
? 64 : 32;
4589 if (i
.broadcast
->type
== BROADCAST_1TO16
)
4590 broadcasted_opnd_size
<<= 4; /* Broadcast 1to16. */
4591 else if (i
.broadcast
->type
== BROADCAST_1TO8
)
4592 broadcasted_opnd_size
<<= 3; /* Broadcast 1to8. */
4593 else if (i
.broadcast
->type
== BROADCAST_1TO4
)
4594 broadcasted_opnd_size
<<= 2; /* Broadcast 1to4. */
4595 else if (i
.broadcast
->type
== BROADCAST_1TO2
)
4596 broadcasted_opnd_size
<<= 1; /* Broadcast 1to2. */
4600 if ((broadcasted_opnd_size
== 256
4601 && !t
->operand_types
[i
.broadcast
->operand
].bitfield
.ymmword
)
4602 || (broadcasted_opnd_size
== 512
4603 && !t
->operand_types
[i
.broadcast
->operand
].bitfield
.zmmword
))
4606 i
.error
= unsupported_broadcast
;
4610 /* If broadcast is supported in this instruction, we need to check if
4611 operand of one-element size isn't specified without broadcast. */
4612 else if (t
->opcode_modifier
.broadcast
&& i
.mem_operands
)
4614 /* Find memory operand. */
4615 for (op
= 0; op
< i
.operands
; op
++)
4616 if (operand_type_check (i
.types
[op
], anymem
))
4618 gas_assert (op
< i
.operands
);
4619 /* Check size of the memory operand. */
4620 if ((t
->opcode_modifier
.vecesize
== 0
4621 && i
.types
[op
].bitfield
.dword
)
4622 || (t
->opcode_modifier
.vecesize
== 1
4623 && i
.types
[op
].bitfield
.qword
))
4625 i
.error
= broadcast_needed
;
4630 /* Check if requested masking is supported. */
4632 && (!t
->opcode_modifier
.masking
4634 && t
->opcode_modifier
.masking
== MERGING_MASKING
)))
4636 i
.error
= unsupported_masking
;
4640 /* Check if masking is applied to dest operand. */
4641 if (i
.mask
&& (i
.mask
->operand
!= (int) (i
.operands
- 1)))
4643 i
.error
= mask_not_on_destination
;
4650 if ((i
.rounding
->type
!= saeonly
4651 && !t
->opcode_modifier
.staticrounding
)
4652 || (i
.rounding
->type
== saeonly
4653 && (t
->opcode_modifier
.staticrounding
4654 || !t
->opcode_modifier
.sae
)))
4656 i
.error
= unsupported_rc_sae
;
4659 /* If the instruction has several immediate operands and one of
4660 them is rounding, the rounding operand should be the last
4661 immediate operand. */
4662 if (i
.imm_operands
> 1
4663 && i
.rounding
->operand
!= (int) (i
.imm_operands
- 1))
4665 i
.error
= rc_sae_operand_not_last_imm
;
4670 /* Check vector Disp8 operand. */
4671 if (t
->opcode_modifier
.disp8memshift
)
4674 i
.memshift
= t
->opcode_modifier
.vecesize
? 3 : 2;
4676 i
.memshift
= t
->opcode_modifier
.disp8memshift
;
4678 for (op
= 0; op
< i
.operands
; op
++)
4679 if (operand_type_check (i
.types
[op
], disp
)
4680 && i
.op
[op
].disps
->X_op
== O_constant
)
4682 offsetT value
= i
.op
[op
].disps
->X_add_number
;
4684 = (i
.disp_encoding
!= disp_encoding_32bit
4685 && fits_in_vec_disp8 (value
));
4686 if (t
->operand_types
[op
].bitfield
.vec_disp8
)
4689 i
.types
[op
].bitfield
.vec_disp8
= 1;
4692 /* Vector insn can only have Vec_Disp8/Disp32 in
4693 32/64bit modes, and Vec_Disp8/Disp16 in 16bit
4695 i
.types
[op
].bitfield
.disp8
= 0;
4696 if (flag_code
!= CODE_16BIT
)
4697 i
.types
[op
].bitfield
.disp16
= 0;
4700 else if (flag_code
!= CODE_16BIT
)
4702 /* One form of this instruction supports vector Disp8.
4703 Try vector Disp8 if we need to use Disp32. */
4704 if (vec_disp8_ok
&& !fits_in_signed_byte (value
))
4706 i
.error
= try_vector_disp8
;
4718 /* Check if operands are valid for the instruction. Update VEX
4722 VEX_check_operands (const insn_template
*t
)
4724 /* VREX is only valid with EVEX prefix. */
4725 if (i
.need_vrex
&& !t
->opcode_modifier
.evex
)
4727 i
.error
= invalid_register_operand
;
4731 if (!t
->opcode_modifier
.vex
)
4734 /* Only check VEX_Imm4, which must be the first operand. */
4735 if (t
->operand_types
[0].bitfield
.vec_imm4
)
4737 if (i
.op
[0].imms
->X_op
!= O_constant
4738 || !fits_in_imm4 (i
.op
[0].imms
->X_add_number
))
4744 /* Turn off Imm8 so that update_imm won't complain. */
4745 i
.types
[0] = vec_imm4
;
4751 static const insn_template
*
4752 match_template (char mnem_suffix
)
4754 /* Points to template once we've found it. */
4755 const insn_template
*t
;
4756 i386_operand_type overlap0
, overlap1
, overlap2
, overlap3
;
4757 i386_operand_type overlap4
;
4758 unsigned int found_reverse_match
;
4759 i386_opcode_modifier suffix_check
, mnemsuf_check
;
4760 i386_operand_type operand_types
[MAX_OPERANDS
];
4761 int addr_prefix_disp
;
4763 unsigned int found_cpu_match
;
4764 unsigned int check_register
;
4765 enum i386_error specific_error
= 0;
4767 #if MAX_OPERANDS != 5
4768 # error "MAX_OPERANDS must be 5."
4771 found_reverse_match
= 0;
4772 addr_prefix_disp
= -1;
4774 memset (&suffix_check
, 0, sizeof (suffix_check
));
4775 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
4776 suffix_check
.no_bsuf
= 1;
4777 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
4778 suffix_check
.no_wsuf
= 1;
4779 else if (i
.suffix
== SHORT_MNEM_SUFFIX
)
4780 suffix_check
.no_ssuf
= 1;
4781 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
4782 suffix_check
.no_lsuf
= 1;
4783 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
4784 suffix_check
.no_qsuf
= 1;
4785 else if (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
)
4786 suffix_check
.no_ldsuf
= 1;
4788 memset (&mnemsuf_check
, 0, sizeof (mnemsuf_check
));
4791 switch (mnem_suffix
)
4793 case BYTE_MNEM_SUFFIX
: mnemsuf_check
.no_bsuf
= 1; break;
4794 case WORD_MNEM_SUFFIX
: mnemsuf_check
.no_wsuf
= 1; break;
4795 case SHORT_MNEM_SUFFIX
: mnemsuf_check
.no_ssuf
= 1; break;
4796 case LONG_MNEM_SUFFIX
: mnemsuf_check
.no_lsuf
= 1; break;
4797 case QWORD_MNEM_SUFFIX
: mnemsuf_check
.no_qsuf
= 1; break;
4801 /* Must have right number of operands. */
4802 i
.error
= number_of_operands_mismatch
;
4804 for (t
= current_templates
->start
; t
< current_templates
->end
; t
++)
4806 addr_prefix_disp
= -1;
4808 if (i
.operands
!= t
->operands
)
4811 /* Check processor support. */
4812 i
.error
= unsupported
;
4813 found_cpu_match
= (cpu_flags_match (t
)
4814 == CPU_FLAGS_PERFECT_MATCH
);
4815 if (!found_cpu_match
)
4818 /* Check old gcc support. */
4819 i
.error
= old_gcc_only
;
4820 if (!old_gcc
&& t
->opcode_modifier
.oldgcc
)
4823 /* Check AT&T mnemonic. */
4824 i
.error
= unsupported_with_intel_mnemonic
;
4825 if (intel_mnemonic
&& t
->opcode_modifier
.attmnemonic
)
4828 /* Check AT&T/Intel syntax and Intel64/AMD64 ISA. */
4829 i
.error
= unsupported_syntax
;
4830 if ((intel_syntax
&& t
->opcode_modifier
.attsyntax
)
4831 || (!intel_syntax
&& t
->opcode_modifier
.intelsyntax
)
4832 || (intel64
&& t
->opcode_modifier
.amd64
)
4833 || (!intel64
&& t
->opcode_modifier
.intel64
))
4836 /* Check the suffix, except for some instructions in intel mode. */
4837 i
.error
= invalid_instruction_suffix
;
4838 if ((!intel_syntax
|| !t
->opcode_modifier
.ignoresize
)
4839 && ((t
->opcode_modifier
.no_bsuf
&& suffix_check
.no_bsuf
)
4840 || (t
->opcode_modifier
.no_wsuf
&& suffix_check
.no_wsuf
)
4841 || (t
->opcode_modifier
.no_lsuf
&& suffix_check
.no_lsuf
)
4842 || (t
->opcode_modifier
.no_ssuf
&& suffix_check
.no_ssuf
)
4843 || (t
->opcode_modifier
.no_qsuf
&& suffix_check
.no_qsuf
)
4844 || (t
->opcode_modifier
.no_ldsuf
&& suffix_check
.no_ldsuf
)))
4846 /* In Intel mode all mnemonic suffixes must be explicitly allowed. */
4847 if ((t
->opcode_modifier
.no_bsuf
&& mnemsuf_check
.no_bsuf
)
4848 || (t
->opcode_modifier
.no_wsuf
&& mnemsuf_check
.no_wsuf
)
4849 || (t
->opcode_modifier
.no_lsuf
&& mnemsuf_check
.no_lsuf
)
4850 || (t
->opcode_modifier
.no_ssuf
&& mnemsuf_check
.no_ssuf
)
4851 || (t
->opcode_modifier
.no_qsuf
&& mnemsuf_check
.no_qsuf
)
4852 || (t
->opcode_modifier
.no_ldsuf
&& mnemsuf_check
.no_ldsuf
))
4855 if (!operand_size_match (t
))
4858 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4859 operand_types
[j
] = t
->operand_types
[j
];
4861 /* In general, don't allow 64-bit operands in 32-bit mode. */
4862 if (i
.suffix
== QWORD_MNEM_SUFFIX
4863 && flag_code
!= CODE_64BIT
4865 ? (!t
->opcode_modifier
.ignoresize
4866 && !intel_float_operand (t
->name
))
4867 : intel_float_operand (t
->name
) != 2)
4868 && ((!operand_types
[0].bitfield
.regmmx
4869 && !operand_types
[0].bitfield
.regxmm
4870 && !operand_types
[0].bitfield
.regymm
4871 && !operand_types
[0].bitfield
.regzmm
)
4872 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
4873 && operand_types
[t
->operands
> 1].bitfield
.regxmm
4874 && operand_types
[t
->operands
> 1].bitfield
.regymm
4875 && operand_types
[t
->operands
> 1].bitfield
.regzmm
))
4876 && (t
->base_opcode
!= 0x0fc7
4877 || t
->extension_opcode
!= 1 /* cmpxchg8b */))
4880 /* In general, don't allow 32-bit operands on pre-386. */
4881 else if (i
.suffix
== LONG_MNEM_SUFFIX
4882 && !cpu_arch_flags
.bitfield
.cpui386
4884 ? (!t
->opcode_modifier
.ignoresize
4885 && !intel_float_operand (t
->name
))
4886 : intel_float_operand (t
->name
) != 2)
4887 && ((!operand_types
[0].bitfield
.regmmx
4888 && !operand_types
[0].bitfield
.regxmm
)
4889 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
4890 && operand_types
[t
->operands
> 1].bitfield
.regxmm
)))
4893 /* Do not verify operands when there are none. */
4897 /* We've found a match; break out of loop. */
4901 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
4902 into Disp32/Disp16/Disp32 operand. */
4903 if (i
.prefix
[ADDR_PREFIX
] != 0)
4905 /* There should be only one Disp operand. */
4909 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4911 if (operand_types
[j
].bitfield
.disp16
)
4913 addr_prefix_disp
= j
;
4914 operand_types
[j
].bitfield
.disp32
= 1;
4915 operand_types
[j
].bitfield
.disp16
= 0;
4921 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4923 if (operand_types
[j
].bitfield
.disp32
)
4925 addr_prefix_disp
= j
;
4926 operand_types
[j
].bitfield
.disp32
= 0;
4927 operand_types
[j
].bitfield
.disp16
= 1;
4933 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4935 if (operand_types
[j
].bitfield
.disp64
)
4937 addr_prefix_disp
= j
;
4938 operand_types
[j
].bitfield
.disp64
= 0;
4939 operand_types
[j
].bitfield
.disp32
= 1;
4947 /* Force 0x8b encoding for "mov foo@GOT, %eax". */
4948 if (i
.reloc
[0] == BFD_RELOC_386_GOT32
&& t
->base_opcode
== 0xa0)
4951 /* We check register size if needed. */
4952 check_register
= t
->opcode_modifier
.checkregsize
;
4953 overlap0
= operand_type_and (i
.types
[0], operand_types
[0]);
4954 switch (t
->operands
)
4957 if (!operand_type_match (overlap0
, i
.types
[0]))
4961 /* xchg %eax, %eax is a special case. It is an alias for nop
4962 only in 32bit mode and we can use opcode 0x90. In 64bit
4963 mode, we can't use 0x90 for xchg %eax, %eax since it should
4964 zero-extend %eax to %rax. */
4965 if (flag_code
== CODE_64BIT
4966 && t
->base_opcode
== 0x90
4967 && operand_type_equal (&i
.types
[0], &acc32
)
4968 && operand_type_equal (&i
.types
[1], &acc32
))
4972 /* If we swap operand in encoding, we either match
4973 the next one or reverse direction of operands. */
4974 if (t
->opcode_modifier
.s
)
4976 else if (t
->opcode_modifier
.d
)
4982 /* If we swap operand in encoding, we match the next one. */
4983 if (i
.swap_operand
&& t
->opcode_modifier
.s
)
4988 overlap1
= operand_type_and (i
.types
[1], operand_types
[1]);
4989 if (!operand_type_match (overlap0
, i
.types
[0])
4990 || !operand_type_match (overlap1
, i
.types
[1])
4992 && !operand_type_register_match (overlap0
, i
.types
[0],
4994 overlap1
, i
.types
[1],
4997 /* Check if other direction is valid ... */
4998 if (!t
->opcode_modifier
.d
&& !t
->opcode_modifier
.floatd
)
5002 /* Try reversing direction of operands. */
5003 overlap0
= operand_type_and (i
.types
[0], operand_types
[1]);
5004 overlap1
= operand_type_and (i
.types
[1], operand_types
[0]);
5005 if (!operand_type_match (overlap0
, i
.types
[0])
5006 || !operand_type_match (overlap1
, i
.types
[1])
5008 && !operand_type_register_match (overlap0
,
5015 /* Does not match either direction. */
5018 /* found_reverse_match holds which of D or FloatDR
5020 if (t
->opcode_modifier
.d
)
5021 found_reverse_match
= Opcode_D
;
5022 else if (t
->opcode_modifier
.floatd
)
5023 found_reverse_match
= Opcode_FloatD
;
5025 found_reverse_match
= 0;
5026 if (t
->opcode_modifier
.floatr
)
5027 found_reverse_match
|= Opcode_FloatR
;
5031 /* Found a forward 2 operand match here. */
5032 switch (t
->operands
)
5035 overlap4
= operand_type_and (i
.types
[4],
5039 overlap3
= operand_type_and (i
.types
[3],
5043 overlap2
= operand_type_and (i
.types
[2],
5048 switch (t
->operands
)
5051 if (!operand_type_match (overlap4
, i
.types
[4])
5052 || !operand_type_register_match (overlap3
,
5061 if (!operand_type_match (overlap3
, i
.types
[3])
5063 && !operand_type_register_match (overlap2
,
5072 /* Here we make use of the fact that there are no
5073 reverse match 3 operand instructions, and all 3
5074 operand instructions only need to be checked for
5075 register consistency between operands 2 and 3. */
5076 if (!operand_type_match (overlap2
, i
.types
[2])
5078 && !operand_type_register_match (overlap1
,
5088 /* Found either forward/reverse 2, 3 or 4 operand match here:
5089 slip through to break. */
5091 if (!found_cpu_match
)
5093 found_reverse_match
= 0;
5097 /* Check if vector and VEX operands are valid. */
5098 if (check_VecOperands (t
) || VEX_check_operands (t
))
5100 specific_error
= i
.error
;
5104 /* We've found a match; break out of loop. */
5108 if (t
== current_templates
->end
)
5110 /* We found no match. */
5111 const char *err_msg
;
5112 switch (specific_error
? specific_error
: i
.error
)
5116 case operand_size_mismatch
:
5117 err_msg
= _("operand size mismatch");
5119 case operand_type_mismatch
:
5120 err_msg
= _("operand type mismatch");
5122 case register_type_mismatch
:
5123 err_msg
= _("register type mismatch");
5125 case number_of_operands_mismatch
:
5126 err_msg
= _("number of operands mismatch");
5128 case invalid_instruction_suffix
:
5129 err_msg
= _("invalid instruction suffix");
5132 err_msg
= _("constant doesn't fit in 4 bits");
5135 err_msg
= _("only supported with old gcc");
5137 case unsupported_with_intel_mnemonic
:
5138 err_msg
= _("unsupported with Intel mnemonic");
5140 case unsupported_syntax
:
5141 err_msg
= _("unsupported syntax");
5144 as_bad (_("unsupported instruction `%s'"),
5145 current_templates
->start
->name
);
5147 case invalid_vsib_address
:
5148 err_msg
= _("invalid VSIB address");
5150 case invalid_vector_register_set
:
5151 err_msg
= _("mask, index, and destination registers must be distinct");
5153 case unsupported_vector_index_register
:
5154 err_msg
= _("unsupported vector index register");
5156 case unsupported_broadcast
:
5157 err_msg
= _("unsupported broadcast");
5159 case broadcast_not_on_src_operand
:
5160 err_msg
= _("broadcast not on source memory operand");
5162 case broadcast_needed
:
5163 err_msg
= _("broadcast is needed for operand of such type");
5165 case unsupported_masking
:
5166 err_msg
= _("unsupported masking");
5168 case mask_not_on_destination
:
5169 err_msg
= _("mask not on destination operand");
5171 case no_default_mask
:
5172 err_msg
= _("default mask isn't allowed");
5174 case unsupported_rc_sae
:
5175 err_msg
= _("unsupported static rounding/sae");
5177 case rc_sae_operand_not_last_imm
:
5179 err_msg
= _("RC/SAE operand must precede immediate operands");
5181 err_msg
= _("RC/SAE operand must follow immediate operands");
5183 case invalid_register_operand
:
5184 err_msg
= _("invalid register operand");
5187 as_bad (_("%s for `%s'"), err_msg
,
5188 current_templates
->start
->name
);
5192 if (!quiet_warnings
)
5195 && (i
.types
[0].bitfield
.jumpabsolute
5196 != operand_types
[0].bitfield
.jumpabsolute
))
5198 as_warn (_("indirect %s without `*'"), t
->name
);
5201 if (t
->opcode_modifier
.isprefix
5202 && t
->opcode_modifier
.ignoresize
)
5204 /* Warn them that a data or address size prefix doesn't
5205 affect assembly of the next line of code. */
5206 as_warn (_("stand-alone `%s' prefix"), t
->name
);
5210 /* Copy the template we found. */
5213 if (addr_prefix_disp
!= -1)
5214 i
.tm
.operand_types
[addr_prefix_disp
]
5215 = operand_types
[addr_prefix_disp
];
5217 if (found_reverse_match
)
5219 /* If we found a reverse match we must alter the opcode
5220 direction bit. found_reverse_match holds bits to change
5221 (different for int & float insns). */
5223 i
.tm
.base_opcode
^= found_reverse_match
;
5225 i
.tm
.operand_types
[0] = operand_types
[1];
5226 i
.tm
.operand_types
[1] = operand_types
[0];
5235 int mem_op
= operand_type_check (i
.types
[0], anymem
) ? 0 : 1;
5236 if (i
.tm
.operand_types
[mem_op
].bitfield
.esseg
)
5238 if (i
.seg
[0] != NULL
&& i
.seg
[0] != &es
)
5240 as_bad (_("`%s' operand %d must use `%ses' segment"),
5246 /* There's only ever one segment override allowed per instruction.
5247 This instruction possibly has a legal segment override on the
5248 second operand, so copy the segment to where non-string
5249 instructions store it, allowing common code. */
5250 i
.seg
[0] = i
.seg
[1];
5252 else if (i
.tm
.operand_types
[mem_op
+ 1].bitfield
.esseg
)
5254 if (i
.seg
[1] != NULL
&& i
.seg
[1] != &es
)
5256 as_bad (_("`%s' operand %d must use `%ses' segment"),
5267 process_suffix (void)
5269 /* If matched instruction specifies an explicit instruction mnemonic
5271 if (i
.tm
.opcode_modifier
.size16
)
5272 i
.suffix
= WORD_MNEM_SUFFIX
;
5273 else if (i
.tm
.opcode_modifier
.size32
)
5274 i
.suffix
= LONG_MNEM_SUFFIX
;
5275 else if (i
.tm
.opcode_modifier
.size64
)
5276 i
.suffix
= QWORD_MNEM_SUFFIX
;
5277 else if (i
.reg_operands
)
5279 /* If there's no instruction mnemonic suffix we try to invent one
5280 based on register operands. */
5283 /* We take i.suffix from the last register operand specified,
5284 Destination register type is more significant than source
5285 register type. crc32 in SSE4.2 prefers source register
5287 if (i
.tm
.base_opcode
== 0xf20f38f1)
5289 if (i
.types
[0].bitfield
.reg16
)
5290 i
.suffix
= WORD_MNEM_SUFFIX
;
5291 else if (i
.types
[0].bitfield
.reg32
)
5292 i
.suffix
= LONG_MNEM_SUFFIX
;
5293 else if (i
.types
[0].bitfield
.reg64
)
5294 i
.suffix
= QWORD_MNEM_SUFFIX
;
5296 else if (i
.tm
.base_opcode
== 0xf20f38f0)
5298 if (i
.types
[0].bitfield
.reg8
)
5299 i
.suffix
= BYTE_MNEM_SUFFIX
;
5306 if (i
.tm
.base_opcode
== 0xf20f38f1
5307 || i
.tm
.base_opcode
== 0xf20f38f0)
5309 /* We have to know the operand size for crc32. */
5310 as_bad (_("ambiguous memory operand size for `%s`"),
5315 for (op
= i
.operands
; --op
>= 0;)
5316 if (!i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
5318 if (i
.types
[op
].bitfield
.reg8
)
5320 i
.suffix
= BYTE_MNEM_SUFFIX
;
5323 else if (i
.types
[op
].bitfield
.reg16
)
5325 i
.suffix
= WORD_MNEM_SUFFIX
;
5328 else if (i
.types
[op
].bitfield
.reg32
)
5330 i
.suffix
= LONG_MNEM_SUFFIX
;
5333 else if (i
.types
[op
].bitfield
.reg64
)
5335 i
.suffix
= QWORD_MNEM_SUFFIX
;
5341 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
5344 && i
.tm
.opcode_modifier
.ignoresize
5345 && i
.tm
.opcode_modifier
.no_bsuf
)
5347 else if (!check_byte_reg ())
5350 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
5353 && i
.tm
.opcode_modifier
.ignoresize
5354 && i
.tm
.opcode_modifier
.no_lsuf
)
5356 else if (!check_long_reg ())
5359 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
5362 && i
.tm
.opcode_modifier
.ignoresize
5363 && i
.tm
.opcode_modifier
.no_qsuf
)
5365 else if (!check_qword_reg ())
5368 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
5371 && i
.tm
.opcode_modifier
.ignoresize
5372 && i
.tm
.opcode_modifier
.no_wsuf
)
5374 else if (!check_word_reg ())
5377 else if (i
.suffix
== XMMWORD_MNEM_SUFFIX
5378 || i
.suffix
== YMMWORD_MNEM_SUFFIX
5379 || i
.suffix
== ZMMWORD_MNEM_SUFFIX
)
5381 /* Skip if the instruction has x/y/z suffix. match_template
5382 should check if it is a valid suffix. */
5384 else if (intel_syntax
&& i
.tm
.opcode_modifier
.ignoresize
)
5385 /* Do nothing if the instruction is going to ignore the prefix. */
5390 else if (i
.tm
.opcode_modifier
.defaultsize
5392 /* exclude fldenv/frstor/fsave/fstenv */
5393 && i
.tm
.opcode_modifier
.no_ssuf
)
5395 i
.suffix
= stackop_size
;
5397 else if (intel_syntax
5399 && (i
.tm
.operand_types
[0].bitfield
.jumpabsolute
5400 || i
.tm
.opcode_modifier
.jumpbyte
5401 || i
.tm
.opcode_modifier
.jumpintersegment
5402 || (i
.tm
.base_opcode
== 0x0f01 /* [ls][gi]dt */
5403 && i
.tm
.extension_opcode
<= 3)))
5408 if (!i
.tm
.opcode_modifier
.no_qsuf
)
5410 i
.suffix
= QWORD_MNEM_SUFFIX
;
5415 if (!i
.tm
.opcode_modifier
.no_lsuf
)
5416 i
.suffix
= LONG_MNEM_SUFFIX
;
5419 if (!i
.tm
.opcode_modifier
.no_wsuf
)
5420 i
.suffix
= WORD_MNEM_SUFFIX
;
5429 if (i
.tm
.opcode_modifier
.w
)
5431 as_bad (_("no instruction mnemonic suffix given and "
5432 "no register operands; can't size instruction"));
5438 unsigned int suffixes
;
5440 suffixes
= !i
.tm
.opcode_modifier
.no_bsuf
;
5441 if (!i
.tm
.opcode_modifier
.no_wsuf
)
5443 if (!i
.tm
.opcode_modifier
.no_lsuf
)
5445 if (!i
.tm
.opcode_modifier
.no_ldsuf
)
5447 if (!i
.tm
.opcode_modifier
.no_ssuf
)
5449 if (!i
.tm
.opcode_modifier
.no_qsuf
)
5452 /* There are more than suffix matches. */
5453 if (i
.tm
.opcode_modifier
.w
5454 || ((suffixes
& (suffixes
- 1))
5455 && !i
.tm
.opcode_modifier
.defaultsize
5456 && !i
.tm
.opcode_modifier
.ignoresize
))
5458 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
5464 /* Change the opcode based on the operand size given by i.suffix;
5465 We don't need to change things for byte insns. */
5468 && i
.suffix
!= BYTE_MNEM_SUFFIX
5469 && i
.suffix
!= XMMWORD_MNEM_SUFFIX
5470 && i
.suffix
!= YMMWORD_MNEM_SUFFIX
5471 && i
.suffix
!= ZMMWORD_MNEM_SUFFIX
)
5473 /* It's not a byte, select word/dword operation. */
5474 if (i
.tm
.opcode_modifier
.w
)
5476 if (i
.tm
.opcode_modifier
.shortform
)
5477 i
.tm
.base_opcode
|= 8;
5479 i
.tm
.base_opcode
|= 1;
5482 /* Now select between word & dword operations via the operand
5483 size prefix, except for instructions that will ignore this
5485 if (i
.tm
.opcode_modifier
.addrprefixop0
)
5487 /* The address size override prefix changes the size of the
5489 if ((flag_code
== CODE_32BIT
5490 && i
.op
->regs
[0].reg_type
.bitfield
.reg16
)
5491 || (flag_code
!= CODE_32BIT
5492 && i
.op
->regs
[0].reg_type
.bitfield
.reg32
))
5493 if (!add_prefix (ADDR_PREFIX_OPCODE
))
5496 else if (i
.suffix
!= QWORD_MNEM_SUFFIX
5497 && i
.suffix
!= LONG_DOUBLE_MNEM_SUFFIX
5498 && !i
.tm
.opcode_modifier
.ignoresize
5499 && !i
.tm
.opcode_modifier
.floatmf
5500 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
5501 || (flag_code
== CODE_64BIT
5502 && i
.tm
.opcode_modifier
.jumpbyte
)))
5504 unsigned int prefix
= DATA_PREFIX_OPCODE
;
5506 if (i
.tm
.opcode_modifier
.jumpbyte
) /* jcxz, loop */
5507 prefix
= ADDR_PREFIX_OPCODE
;
5509 if (!add_prefix (prefix
))
5513 /* Set mode64 for an operand. */
5514 if (i
.suffix
== QWORD_MNEM_SUFFIX
5515 && flag_code
== CODE_64BIT
5516 && !i
.tm
.opcode_modifier
.norex64
)
5518 /* Special case for xchg %rax,%rax. It is NOP and doesn't
5519 need rex64. cmpxchg8b is also a special case. */
5520 if (! (i
.operands
== 2
5521 && i
.tm
.base_opcode
== 0x90
5522 && i
.tm
.extension_opcode
== None
5523 && operand_type_equal (&i
.types
[0], &acc64
)
5524 && operand_type_equal (&i
.types
[1], &acc64
))
5525 && ! (i
.operands
== 1
5526 && i
.tm
.base_opcode
== 0xfc7
5527 && i
.tm
.extension_opcode
== 1
5528 && !operand_type_check (i
.types
[0], reg
)
5529 && operand_type_check (i
.types
[0], anymem
)))
5533 /* Size floating point instruction. */
5534 if (i
.suffix
== LONG_MNEM_SUFFIX
)
5535 if (i
.tm
.opcode_modifier
.floatmf
)
5536 i
.tm
.base_opcode
^= 4;
5543 check_byte_reg (void)
5547 for (op
= i
.operands
; --op
>= 0;)
5549 /* If this is an eight bit register, it's OK. If it's the 16 or
5550 32 bit version of an eight bit register, we will just use the
5551 low portion, and that's OK too. */
5552 if (i
.types
[op
].bitfield
.reg8
)
5555 /* I/O port address operands are OK too. */
5556 if (i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
5559 /* crc32 doesn't generate this warning. */
5560 if (i
.tm
.base_opcode
== 0xf20f38f0)
5563 if ((i
.types
[op
].bitfield
.reg16
5564 || i
.types
[op
].bitfield
.reg32
5565 || i
.types
[op
].bitfield
.reg64
)
5566 && i
.op
[op
].regs
->reg_num
< 4
5567 /* Prohibit these changes in 64bit mode, since the lowering
5568 would be more complicated. */
5569 && flag_code
!= CODE_64BIT
)
5571 #if REGISTER_WARNINGS
5572 if (!quiet_warnings
)
5573 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5575 (i
.op
[op
].regs
+ (i
.types
[op
].bitfield
.reg16
5576 ? REGNAM_AL
- REGNAM_AX
5577 : REGNAM_AL
- REGNAM_EAX
))->reg_name
,
5579 i
.op
[op
].regs
->reg_name
,
5584 /* Any other register is bad. */
5585 if (i
.types
[op
].bitfield
.reg16
5586 || i
.types
[op
].bitfield
.reg32
5587 || i
.types
[op
].bitfield
.reg64
5588 || i
.types
[op
].bitfield
.regmmx
5589 || i
.types
[op
].bitfield
.regxmm
5590 || i
.types
[op
].bitfield
.regymm
5591 || i
.types
[op
].bitfield
.regzmm
5592 || i
.types
[op
].bitfield
.sreg2
5593 || i
.types
[op
].bitfield
.sreg3
5594 || i
.types
[op
].bitfield
.control
5595 || i
.types
[op
].bitfield
.debug
5596 || i
.types
[op
].bitfield
.test
5597 || i
.types
[op
].bitfield
.floatreg
5598 || i
.types
[op
].bitfield
.floatacc
)
5600 as_bad (_("`%s%s' not allowed with `%s%c'"),
5602 i
.op
[op
].regs
->reg_name
,
5612 check_long_reg (void)
5616 for (op
= i
.operands
; --op
>= 0;)
5617 /* Reject eight bit registers, except where the template requires
5618 them. (eg. movzb) */
5619 if (i
.types
[op
].bitfield
.reg8
5620 && (i
.tm
.operand_types
[op
].bitfield
.reg16
5621 || i
.tm
.operand_types
[op
].bitfield
.reg32
5622 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5624 as_bad (_("`%s%s' not allowed with `%s%c'"),
5626 i
.op
[op
].regs
->reg_name
,
5631 /* Warn if the e prefix on a general reg is missing. */
5632 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
5633 && i
.types
[op
].bitfield
.reg16
5634 && (i
.tm
.operand_types
[op
].bitfield
.reg32
5635 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5637 /* Prohibit these changes in the 64bit mode, since the
5638 lowering is more complicated. */
5639 if (flag_code
== CODE_64BIT
)
5641 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5642 register_prefix
, i
.op
[op
].regs
->reg_name
,
5646 #if REGISTER_WARNINGS
5647 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5649 (i
.op
[op
].regs
+ REGNAM_EAX
- REGNAM_AX
)->reg_name
,
5650 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
5653 /* Warn if the r prefix on a general reg is present. */
5654 else if (i
.types
[op
].bitfield
.reg64
5655 && (i
.tm
.operand_types
[op
].bitfield
.reg32
5656 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5659 && i
.tm
.opcode_modifier
.toqword
5660 && !i
.types
[0].bitfield
.regxmm
)
5662 /* Convert to QWORD. We want REX byte. */
5663 i
.suffix
= QWORD_MNEM_SUFFIX
;
5667 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5668 register_prefix
, i
.op
[op
].regs
->reg_name
,
5677 check_qword_reg (void)
5681 for (op
= i
.operands
; --op
>= 0; )
5682 /* Reject eight bit registers, except where the template requires
5683 them. (eg. movzb) */
5684 if (i
.types
[op
].bitfield
.reg8
5685 && (i
.tm
.operand_types
[op
].bitfield
.reg16
5686 || i
.tm
.operand_types
[op
].bitfield
.reg32
5687 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5689 as_bad (_("`%s%s' not allowed with `%s%c'"),
5691 i
.op
[op
].regs
->reg_name
,
5696 /* Warn if the r prefix on a general reg is missing. */
5697 else if ((i
.types
[op
].bitfield
.reg16
5698 || i
.types
[op
].bitfield
.reg32
)
5699 && (i
.tm
.operand_types
[op
].bitfield
.reg64
5700 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5702 /* Prohibit these changes in the 64bit mode, since the
5703 lowering is more complicated. */
5705 && i
.tm
.opcode_modifier
.todword
5706 && !i
.types
[0].bitfield
.regxmm
)
5708 /* Convert to DWORD. We don't want REX byte. */
5709 i
.suffix
= LONG_MNEM_SUFFIX
;
5713 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5714 register_prefix
, i
.op
[op
].regs
->reg_name
,
5723 check_word_reg (void)
5726 for (op
= i
.operands
; --op
>= 0;)
5727 /* Reject eight bit registers, except where the template requires
5728 them. (eg. movzb) */
5729 if (i
.types
[op
].bitfield
.reg8
5730 && (i
.tm
.operand_types
[op
].bitfield
.reg16
5731 || i
.tm
.operand_types
[op
].bitfield
.reg32
5732 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5734 as_bad (_("`%s%s' not allowed with `%s%c'"),
5736 i
.op
[op
].regs
->reg_name
,
5741 /* Warn if the e or r prefix on a general reg is present. */
5742 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
5743 && (i
.types
[op
].bitfield
.reg32
5744 || i
.types
[op
].bitfield
.reg64
)
5745 && (i
.tm
.operand_types
[op
].bitfield
.reg16
5746 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5748 /* Prohibit these changes in the 64bit mode, since the
5749 lowering is more complicated. */
5750 if (flag_code
== CODE_64BIT
)
5752 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5753 register_prefix
, i
.op
[op
].regs
->reg_name
,
5757 #if REGISTER_WARNINGS
5758 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5760 (i
.op
[op
].regs
+ REGNAM_AX
- REGNAM_EAX
)->reg_name
,
5761 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
5768 update_imm (unsigned int j
)
5770 i386_operand_type overlap
= i
.types
[j
];
5771 if ((overlap
.bitfield
.imm8
5772 || overlap
.bitfield
.imm8s
5773 || overlap
.bitfield
.imm16
5774 || overlap
.bitfield
.imm32
5775 || overlap
.bitfield
.imm32s
5776 || overlap
.bitfield
.imm64
)
5777 && !operand_type_equal (&overlap
, &imm8
)
5778 && !operand_type_equal (&overlap
, &imm8s
)
5779 && !operand_type_equal (&overlap
, &imm16
)
5780 && !operand_type_equal (&overlap
, &imm32
)
5781 && !operand_type_equal (&overlap
, &imm32s
)
5782 && !operand_type_equal (&overlap
, &imm64
))
5786 i386_operand_type temp
;
5788 operand_type_set (&temp
, 0);
5789 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
5791 temp
.bitfield
.imm8
= overlap
.bitfield
.imm8
;
5792 temp
.bitfield
.imm8s
= overlap
.bitfield
.imm8s
;
5794 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
5795 temp
.bitfield
.imm16
= overlap
.bitfield
.imm16
;
5796 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
5798 temp
.bitfield
.imm64
= overlap
.bitfield
.imm64
;
5799 temp
.bitfield
.imm32s
= overlap
.bitfield
.imm32s
;
5802 temp
.bitfield
.imm32
= overlap
.bitfield
.imm32
;
5805 else if (operand_type_equal (&overlap
, &imm16_32_32s
)
5806 || operand_type_equal (&overlap
, &imm16_32
)
5807 || operand_type_equal (&overlap
, &imm16_32s
))
5809 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
5814 if (!operand_type_equal (&overlap
, &imm8
)
5815 && !operand_type_equal (&overlap
, &imm8s
)
5816 && !operand_type_equal (&overlap
, &imm16
)
5817 && !operand_type_equal (&overlap
, &imm32
)
5818 && !operand_type_equal (&overlap
, &imm32s
)
5819 && !operand_type_equal (&overlap
, &imm64
))
5821 as_bad (_("no instruction mnemonic suffix given; "
5822 "can't determine immediate size"));
5826 i
.types
[j
] = overlap
;
5836 /* Update the first 2 immediate operands. */
5837 n
= i
.operands
> 2 ? 2 : i
.operands
;
5840 for (j
= 0; j
< n
; j
++)
5841 if (update_imm (j
) == 0)
5844 /* The 3rd operand can't be immediate operand. */
5845 gas_assert (operand_type_check (i
.types
[2], imm
) == 0);
5852 bad_implicit_operand (int xmm
)
5854 const char *ireg
= xmm
? "xmm0" : "ymm0";
5857 as_bad (_("the last operand of `%s' must be `%s%s'"),
5858 i
.tm
.name
, register_prefix
, ireg
);
5860 as_bad (_("the first operand of `%s' must be `%s%s'"),
5861 i
.tm
.name
, register_prefix
, ireg
);
5866 process_operands (void)
5868 /* Default segment register this instruction will use for memory
5869 accesses. 0 means unknown. This is only for optimizing out
5870 unnecessary segment overrides. */
5871 const seg_entry
*default_seg
= 0;
5873 if (i
.tm
.opcode_modifier
.sse2avx
&& i
.tm
.opcode_modifier
.vexvvvv
)
5875 unsigned int dupl
= i
.operands
;
5876 unsigned int dest
= dupl
- 1;
5879 /* The destination must be an xmm register. */
5880 gas_assert (i
.reg_operands
5881 && MAX_OPERANDS
> dupl
5882 && operand_type_equal (&i
.types
[dest
], ®xmm
));
5884 if (i
.tm
.opcode_modifier
.firstxmm0
)
5886 /* The first operand is implicit and must be xmm0. */
5887 gas_assert (operand_type_equal (&i
.types
[0], ®xmm
));
5888 if (register_number (i
.op
[0].regs
) != 0)
5889 return bad_implicit_operand (1);
5891 if (i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
)
5893 /* Keep xmm0 for instructions with VEX prefix and 3
5899 /* We remove the first xmm0 and keep the number of
5900 operands unchanged, which in fact duplicates the
5902 for (j
= 1; j
< i
.operands
; j
++)
5904 i
.op
[j
- 1] = i
.op
[j
];
5905 i
.types
[j
- 1] = i
.types
[j
];
5906 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
5910 else if (i
.tm
.opcode_modifier
.implicit1stxmm0
)
5912 gas_assert ((MAX_OPERANDS
- 1) > dupl
5913 && (i
.tm
.opcode_modifier
.vexsources
5916 /* Add the implicit xmm0 for instructions with VEX prefix
5918 for (j
= i
.operands
; j
> 0; j
--)
5920 i
.op
[j
] = i
.op
[j
- 1];
5921 i
.types
[j
] = i
.types
[j
- 1];
5922 i
.tm
.operand_types
[j
] = i
.tm
.operand_types
[j
- 1];
5925 = (const reg_entry
*) hash_find (reg_hash
, "xmm0");
5926 i
.types
[0] = regxmm
;
5927 i
.tm
.operand_types
[0] = regxmm
;
5930 i
.reg_operands
+= 2;
5935 i
.op
[dupl
] = i
.op
[dest
];
5936 i
.types
[dupl
] = i
.types
[dest
];
5937 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
5946 i
.op
[dupl
] = i
.op
[dest
];
5947 i
.types
[dupl
] = i
.types
[dest
];
5948 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
5951 if (i
.tm
.opcode_modifier
.immext
)
5954 else if (i
.tm
.opcode_modifier
.firstxmm0
)
5958 /* The first operand is implicit and must be xmm0/ymm0/zmm0. */
5959 gas_assert (i
.reg_operands
5960 && (operand_type_equal (&i
.types
[0], ®xmm
)
5961 || operand_type_equal (&i
.types
[0], ®ymm
)
5962 || operand_type_equal (&i
.types
[0], ®zmm
)));
5963 if (register_number (i
.op
[0].regs
) != 0)
5964 return bad_implicit_operand (i
.types
[0].bitfield
.regxmm
);
5966 for (j
= 1; j
< i
.operands
; j
++)
5968 i
.op
[j
- 1] = i
.op
[j
];
5969 i
.types
[j
- 1] = i
.types
[j
];
5971 /* We need to adjust fields in i.tm since they are used by
5972 build_modrm_byte. */
5973 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
5980 else if (i
.tm
.opcode_modifier
.implicitquadgroup
)
5982 /* The second operand must be {x,y,z}mmN, where N is a multiple of 4. */
5983 gas_assert (i
.operands
>= 2
5984 && (operand_type_equal (&i
.types
[1], ®xmm
)
5985 || operand_type_equal (&i
.types
[1], ®ymm
)
5986 || operand_type_equal (&i
.types
[1], ®zmm
)));
5987 unsigned int regnum
= register_number (i
.op
[1].regs
);
5988 unsigned int first_reg_in_group
= regnum
& ~3;
5989 unsigned int last_reg_in_group
= first_reg_in_group
+ 3;
5990 if (regnum
!= first_reg_in_group
) {
5991 as_warn (_("the second source register `%s%s' implicitly denotes"
5992 " `%s%.3s%d' to `%s%.3s%d' source group in `%s'"),
5993 register_prefix
, i
.op
[1].regs
->reg_name
,
5994 register_prefix
, i
.op
[1].regs
->reg_name
, first_reg_in_group
,
5995 register_prefix
, i
.op
[1].regs
->reg_name
, last_reg_in_group
,
5999 else if (i
.tm
.opcode_modifier
.regkludge
)
6001 /* The imul $imm, %reg instruction is converted into
6002 imul $imm, %reg, %reg, and the clr %reg instruction
6003 is converted into xor %reg, %reg. */
6005 unsigned int first_reg_op
;
6007 if (operand_type_check (i
.types
[0], reg
))
6011 /* Pretend we saw the extra register operand. */
6012 gas_assert (i
.reg_operands
== 1
6013 && i
.op
[first_reg_op
+ 1].regs
== 0);
6014 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
6015 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
6020 if (i
.tm
.opcode_modifier
.shortform
)
6022 if (i
.types
[0].bitfield
.sreg2
6023 || i
.types
[0].bitfield
.sreg3
)
6025 if (i
.tm
.base_opcode
== POP_SEG_SHORT
6026 && i
.op
[0].regs
->reg_num
== 1)
6028 as_bad (_("you can't `pop %scs'"), register_prefix
);
6031 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
6032 if ((i
.op
[0].regs
->reg_flags
& RegRex
) != 0)
6037 /* The register or float register operand is in operand
6041 if (i
.types
[0].bitfield
.floatreg
6042 || operand_type_check (i
.types
[0], reg
))
6046 /* Register goes in low 3 bits of opcode. */
6047 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
6048 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
6050 if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
6052 /* Warn about some common errors, but press on regardless.
6053 The first case can be generated by gcc (<= 2.8.1). */
6054 if (i
.operands
== 2)
6056 /* Reversed arguments on faddp, fsubp, etc. */
6057 as_warn (_("translating to `%s %s%s,%s%s'"), i
.tm
.name
,
6058 register_prefix
, i
.op
[!intel_syntax
].regs
->reg_name
,
6059 register_prefix
, i
.op
[intel_syntax
].regs
->reg_name
);
6063 /* Extraneous `l' suffix on fp insn. */
6064 as_warn (_("translating to `%s %s%s'"), i
.tm
.name
,
6065 register_prefix
, i
.op
[0].regs
->reg_name
);
6070 else if (i
.tm
.opcode_modifier
.modrm
)
6072 /* The opcode is completed (modulo i.tm.extension_opcode which
6073 must be put into the modrm byte). Now, we make the modrm and
6074 index base bytes based on all the info we've collected. */
6076 default_seg
= build_modrm_byte ();
6078 else if ((i
.tm
.base_opcode
& ~0x3) == MOV_AX_DISP32
)
6082 else if (i
.tm
.opcode_modifier
.isstring
)
6084 /* For the string instructions that allow a segment override
6085 on one of their operands, the default segment is ds. */
6089 if (i
.tm
.base_opcode
== 0x8d /* lea */
6092 as_warn (_("segment override on `%s' is ineffectual"), i
.tm
.name
);
6094 /* If a segment was explicitly specified, and the specified segment
6095 is not the default, use an opcode prefix to select it. If we
6096 never figured out what the default segment is, then default_seg
6097 will be zero at this point, and the specified segment prefix will
6099 if ((i
.seg
[0]) && (i
.seg
[0] != default_seg
))
6101 if (!add_prefix (i
.seg
[0]->seg_prefix
))
6107 static const seg_entry
*
6108 build_modrm_byte (void)
6110 const seg_entry
*default_seg
= 0;
6111 unsigned int source
, dest
;
6114 /* The first operand of instructions with VEX prefix and 3 sources
6115 must be VEX_Imm4. */
6116 vex_3_sources
= i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
;
6119 unsigned int nds
, reg_slot
;
6122 if (i
.tm
.opcode_modifier
.veximmext
6123 && i
.tm
.opcode_modifier
.immext
)
6125 dest
= i
.operands
- 2;
6126 gas_assert (dest
== 3);
6129 dest
= i
.operands
- 1;
6132 /* There are 2 kinds of instructions:
6133 1. 5 operands: 4 register operands or 3 register operands
6134 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
6135 VexW0 or VexW1. The destination must be either XMM, YMM or
6137 2. 4 operands: 4 register operands or 3 register operands
6138 plus 1 memory operand, VexXDS, and VexImmExt */
6139 gas_assert ((i
.reg_operands
== 4
6140 || (i
.reg_operands
== 3 && i
.mem_operands
== 1))
6141 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
6142 && (i
.tm
.opcode_modifier
.veximmext
6143 || (i
.imm_operands
== 1
6144 && i
.types
[0].bitfield
.vec_imm4
6145 && (i
.tm
.opcode_modifier
.vexw
== VEXW0
6146 || i
.tm
.opcode_modifier
.vexw
== VEXW1
)
6147 && (operand_type_equal (&i
.tm
.operand_types
[dest
], ®xmm
)
6148 || operand_type_equal (&i
.tm
.operand_types
[dest
], ®ymm
)
6149 || operand_type_equal (&i
.tm
.operand_types
[dest
], ®zmm
)))));
6151 if (i
.imm_operands
== 0)
6153 /* When there is no immediate operand, generate an 8bit
6154 immediate operand to encode the first operand. */
6155 exp
= &im_expressions
[i
.imm_operands
++];
6156 i
.op
[i
.operands
].imms
= exp
;
6157 i
.types
[i
.operands
] = imm8
;
6159 /* If VexW1 is set, the first operand is the source and
6160 the second operand is encoded in the immediate operand. */
6161 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
6172 /* FMA swaps REG and NDS. */
6173 if (i
.tm
.cpu_flags
.bitfield
.cpufma
)
6181 gas_assert (operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6183 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6185 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6187 exp
->X_op
= O_constant
;
6188 exp
->X_add_number
= register_number (i
.op
[reg_slot
].regs
) << 4;
6189 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
6193 unsigned int imm_slot
;
6195 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
6197 /* If VexW0 is set, the third operand is the source and
6198 the second operand is encoded in the immediate
6205 /* VexW1 is set, the second operand is the source and
6206 the third operand is encoded in the immediate
6212 if (i
.tm
.opcode_modifier
.immext
)
6214 /* When ImmExt is set, the immediate byte is the last
6216 imm_slot
= i
.operands
- 1;
6224 /* Turn on Imm8 so that output_imm will generate it. */
6225 i
.types
[imm_slot
].bitfield
.imm8
= 1;
6228 gas_assert (operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6230 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6232 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6234 i
.op
[imm_slot
].imms
->X_add_number
6235 |= register_number (i
.op
[reg_slot
].regs
) << 4;
6236 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
6239 gas_assert (operand_type_equal (&i
.tm
.operand_types
[nds
], ®xmm
)
6240 || operand_type_equal (&i
.tm
.operand_types
[nds
],
6242 || operand_type_equal (&i
.tm
.operand_types
[nds
],
6244 i
.vex
.register_specifier
= i
.op
[nds
].regs
;
6249 /* i.reg_operands MUST be the number of real register operands;
6250 implicit registers do not count. If there are 3 register
6251 operands, it must be a instruction with VexNDS. For a
6252 instruction with VexNDD, the destination register is encoded
6253 in VEX prefix. If there are 4 register operands, it must be
6254 a instruction with VEX prefix and 3 sources. */
6255 if (i
.mem_operands
== 0
6256 && ((i
.reg_operands
== 2
6257 && i
.tm
.opcode_modifier
.vexvvvv
<= VEXXDS
)
6258 || (i
.reg_operands
== 3
6259 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
6260 || (i
.reg_operands
== 4 && vex_3_sources
)))
6268 /* When there are 3 operands, one of them may be immediate,
6269 which may be the first or the last operand. Otherwise,
6270 the first operand must be shift count register (cl) or it
6271 is an instruction with VexNDS. */
6272 gas_assert (i
.imm_operands
== 1
6273 || (i
.imm_operands
== 0
6274 && (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
6275 || i
.types
[0].bitfield
.shiftcount
)));
6276 if (operand_type_check (i
.types
[0], imm
)
6277 || i
.types
[0].bitfield
.shiftcount
)
6283 /* When there are 4 operands, the first two must be 8bit
6284 immediate operands. The source operand will be the 3rd
6287 For instructions with VexNDS, if the first operand
6288 an imm8, the source operand is the 2nd one. If the last
6289 operand is imm8, the source operand is the first one. */
6290 gas_assert ((i
.imm_operands
== 2
6291 && i
.types
[0].bitfield
.imm8
6292 && i
.types
[1].bitfield
.imm8
)
6293 || (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
6294 && i
.imm_operands
== 1
6295 && (i
.types
[0].bitfield
.imm8
6296 || i
.types
[i
.operands
- 1].bitfield
.imm8
6298 if (i
.imm_operands
== 2)
6302 if (i
.types
[0].bitfield
.imm8
)
6309 if (i
.tm
.opcode_modifier
.evex
)
6311 /* For EVEX instructions, when there are 5 operands, the
6312 first one must be immediate operand. If the second one
6313 is immediate operand, the source operand is the 3th
6314 one. If the last one is immediate operand, the source
6315 operand is the 2nd one. */
6316 gas_assert (i
.imm_operands
== 2
6317 && i
.tm
.opcode_modifier
.sae
6318 && operand_type_check (i
.types
[0], imm
));
6319 if (operand_type_check (i
.types
[1], imm
))
6321 else if (operand_type_check (i
.types
[4], imm
))
6335 /* RC/SAE operand could be between DEST and SRC. That happens
6336 when one operand is GPR and the other one is XMM/YMM/ZMM
6338 if (i
.rounding
&& i
.rounding
->operand
== (int) dest
)
6341 if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
6343 /* For instructions with VexNDS, the register-only source
6344 operand must be 32/64bit integer, XMM, YMM or ZMM
6345 register. It is encoded in VEX prefix. We need to
6346 clear RegMem bit before calling operand_type_equal. */
6348 i386_operand_type op
;
6351 /* Check register-only source operand when two source
6352 operands are swapped. */
6353 if (!i
.tm
.operand_types
[source
].bitfield
.baseindex
6354 && i
.tm
.operand_types
[dest
].bitfield
.baseindex
)
6362 op
= i
.tm
.operand_types
[vvvv
];
6363 op
.bitfield
.regmem
= 0;
6364 if ((dest
+ 1) >= i
.operands
6365 || (!op
.bitfield
.reg32
6366 && op
.bitfield
.reg64
6367 && !operand_type_equal (&op
, ®xmm
)
6368 && !operand_type_equal (&op
, ®ymm
)
6369 && !operand_type_equal (&op
, ®zmm
)
6370 && !operand_type_equal (&op
, ®mask
)))
6372 i
.vex
.register_specifier
= i
.op
[vvvv
].regs
;
6378 /* One of the register operands will be encoded in the i.tm.reg
6379 field, the other in the combined i.tm.mode and i.tm.regmem
6380 fields. If no form of this instruction supports a memory
6381 destination operand, then we assume the source operand may
6382 sometimes be a memory operand and so we need to store the
6383 destination in the i.rm.reg field. */
6384 if (!i
.tm
.operand_types
[dest
].bitfield
.regmem
6385 && operand_type_check (i
.tm
.operand_types
[dest
], anymem
) == 0)
6387 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
6388 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
6389 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
6391 if ((i
.op
[dest
].regs
->reg_flags
& RegVRex
) != 0)
6393 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
6395 if ((i
.op
[source
].regs
->reg_flags
& RegVRex
) != 0)
6400 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
6401 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
6402 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
6404 if ((i
.op
[dest
].regs
->reg_flags
& RegVRex
) != 0)
6406 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
6408 if ((i
.op
[source
].regs
->reg_flags
& RegVRex
) != 0)
6411 if (flag_code
!= CODE_64BIT
&& (i
.rex
& (REX_R
| REX_B
)))
6413 if (!i
.types
[0].bitfield
.control
6414 && !i
.types
[1].bitfield
.control
)
6416 i
.rex
&= ~(REX_R
| REX_B
);
6417 add_prefix (LOCK_PREFIX_OPCODE
);
6421 { /* If it's not 2 reg operands... */
6426 unsigned int fake_zero_displacement
= 0;
6429 for (op
= 0; op
< i
.operands
; op
++)
6430 if (operand_type_check (i
.types
[op
], anymem
))
6432 gas_assert (op
< i
.operands
);
6434 if (i
.tm
.opcode_modifier
.vecsib
)
6436 if (i
.index_reg
->reg_num
== RegEiz
6437 || i
.index_reg
->reg_num
== RegRiz
)
6440 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6443 i
.sib
.base
= NO_BASE_REGISTER
;
6444 i
.sib
.scale
= i
.log2_scale_factor
;
6445 /* No Vec_Disp8 if there is no base. */
6446 i
.types
[op
].bitfield
.vec_disp8
= 0;
6447 i
.types
[op
].bitfield
.disp8
= 0;
6448 i
.types
[op
].bitfield
.disp16
= 0;
6449 i
.types
[op
].bitfield
.disp64
= 0;
6450 if (flag_code
!= CODE_64BIT
)
6452 /* Must be 32 bit */
6453 i
.types
[op
].bitfield
.disp32
= 1;
6454 i
.types
[op
].bitfield
.disp32s
= 0;
6458 i
.types
[op
].bitfield
.disp32
= 0;
6459 i
.types
[op
].bitfield
.disp32s
= 1;
6462 i
.sib
.index
= i
.index_reg
->reg_num
;
6463 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
6465 if ((i
.index_reg
->reg_flags
& RegVRex
) != 0)
6471 if (i
.base_reg
== 0)
6474 if (!i
.disp_operands
)
6476 fake_zero_displacement
= 1;
6477 /* Instructions with VSIB byte need 32bit displacement
6478 if there is no base register. */
6479 if (i
.tm
.opcode_modifier
.vecsib
)
6480 i
.types
[op
].bitfield
.disp32
= 1;
6482 if (i
.index_reg
== 0)
6484 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6485 /* Operand is just <disp> */
6486 if (flag_code
== CODE_64BIT
)
6488 /* 64bit mode overwrites the 32bit absolute
6489 addressing by RIP relative addressing and
6490 absolute addressing is encoded by one of the
6491 redundant SIB forms. */
6492 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6493 i
.sib
.base
= NO_BASE_REGISTER
;
6494 i
.sib
.index
= NO_INDEX_REGISTER
;
6495 i
.types
[op
] = ((i
.prefix
[ADDR_PREFIX
] == 0)
6496 ? disp32s
: disp32
);
6498 else if ((flag_code
== CODE_16BIT
)
6499 ^ (i
.prefix
[ADDR_PREFIX
] != 0))
6501 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
6502 i
.types
[op
] = disp16
;
6506 i
.rm
.regmem
= NO_BASE_REGISTER
;
6507 i
.types
[op
] = disp32
;
6510 else if (!i
.tm
.opcode_modifier
.vecsib
)
6512 /* !i.base_reg && i.index_reg */
6513 if (i
.index_reg
->reg_num
== RegEiz
6514 || i
.index_reg
->reg_num
== RegRiz
)
6515 i
.sib
.index
= NO_INDEX_REGISTER
;
6517 i
.sib
.index
= i
.index_reg
->reg_num
;
6518 i
.sib
.base
= NO_BASE_REGISTER
;
6519 i
.sib
.scale
= i
.log2_scale_factor
;
6520 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6521 /* No Vec_Disp8 if there is no base. */
6522 i
.types
[op
].bitfield
.vec_disp8
= 0;
6523 i
.types
[op
].bitfield
.disp8
= 0;
6524 i
.types
[op
].bitfield
.disp16
= 0;
6525 i
.types
[op
].bitfield
.disp64
= 0;
6526 if (flag_code
!= CODE_64BIT
)
6528 /* Must be 32 bit */
6529 i
.types
[op
].bitfield
.disp32
= 1;
6530 i
.types
[op
].bitfield
.disp32s
= 0;
6534 i
.types
[op
].bitfield
.disp32
= 0;
6535 i
.types
[op
].bitfield
.disp32s
= 1;
6537 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
6541 /* RIP addressing for 64bit mode. */
6542 else if (i
.base_reg
->reg_num
== RegRip
||
6543 i
.base_reg
->reg_num
== RegEip
)
6545 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6546 i
.rm
.regmem
= NO_BASE_REGISTER
;
6547 i
.types
[op
].bitfield
.disp8
= 0;
6548 i
.types
[op
].bitfield
.disp16
= 0;
6549 i
.types
[op
].bitfield
.disp32
= 0;
6550 i
.types
[op
].bitfield
.disp32s
= 1;
6551 i
.types
[op
].bitfield
.disp64
= 0;
6552 i
.types
[op
].bitfield
.vec_disp8
= 0;
6553 i
.flags
[op
] |= Operand_PCrel
;
6554 if (! i
.disp_operands
)
6555 fake_zero_displacement
= 1;
6557 else if (i
.base_reg
->reg_type
.bitfield
.reg16
)
6559 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6560 switch (i
.base_reg
->reg_num
)
6563 if (i
.index_reg
== 0)
6565 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
6566 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
6570 if (i
.index_reg
== 0)
6573 if (operand_type_check (i
.types
[op
], disp
) == 0)
6575 /* fake (%bp) into 0(%bp) */
6576 if (i
.tm
.operand_types
[op
].bitfield
.vec_disp8
)
6577 i
.types
[op
].bitfield
.vec_disp8
= 1;
6579 i
.types
[op
].bitfield
.disp8
= 1;
6580 fake_zero_displacement
= 1;
6583 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
6584 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
6586 default: /* (%si) -> 4 or (%di) -> 5 */
6587 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
6589 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
6591 else /* i.base_reg and 32/64 bit mode */
6593 if (flag_code
== CODE_64BIT
6594 && operand_type_check (i
.types
[op
], disp
))
6596 i386_operand_type temp
;
6597 operand_type_set (&temp
, 0);
6598 temp
.bitfield
.disp8
= i
.types
[op
].bitfield
.disp8
;
6599 temp
.bitfield
.vec_disp8
6600 = i
.types
[op
].bitfield
.vec_disp8
;
6602 if (i
.prefix
[ADDR_PREFIX
] == 0)
6603 i
.types
[op
].bitfield
.disp32s
= 1;
6605 i
.types
[op
].bitfield
.disp32
= 1;
6608 if (!i
.tm
.opcode_modifier
.vecsib
)
6609 i
.rm
.regmem
= i
.base_reg
->reg_num
;
6610 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
6612 i
.sib
.base
= i
.base_reg
->reg_num
;
6613 /* x86-64 ignores REX prefix bit here to avoid decoder
6615 if (!(i
.base_reg
->reg_flags
& RegRex
)
6616 && (i
.base_reg
->reg_num
== EBP_REG_NUM
6617 || i
.base_reg
->reg_num
== ESP_REG_NUM
))
6619 if (i
.base_reg
->reg_num
== 5 && i
.disp_operands
== 0)
6621 fake_zero_displacement
= 1;
6622 if (i
.tm
.operand_types
[op
].bitfield
.vec_disp8
)
6623 i
.types
[op
].bitfield
.vec_disp8
= 1;
6625 i
.types
[op
].bitfield
.disp8
= 1;
6627 i
.sib
.scale
= i
.log2_scale_factor
;
6628 if (i
.index_reg
== 0)
6630 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6631 /* <disp>(%esp) becomes two byte modrm with no index
6632 register. We've already stored the code for esp
6633 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
6634 Any base register besides %esp will not use the
6635 extra modrm byte. */
6636 i
.sib
.index
= NO_INDEX_REGISTER
;
6638 else if (!i
.tm
.opcode_modifier
.vecsib
)
6640 if (i
.index_reg
->reg_num
== RegEiz
6641 || i
.index_reg
->reg_num
== RegRiz
)
6642 i
.sib
.index
= NO_INDEX_REGISTER
;
6644 i
.sib
.index
= i
.index_reg
->reg_num
;
6645 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6646 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
6651 && (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
6652 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
))
6656 if (!fake_zero_displacement
6660 fake_zero_displacement
= 1;
6661 if (i
.disp_encoding
== disp_encoding_8bit
)
6662 i
.types
[op
].bitfield
.disp8
= 1;
6664 i
.types
[op
].bitfield
.disp32
= 1;
6666 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
6670 if (fake_zero_displacement
)
6672 /* Fakes a zero displacement assuming that i.types[op]
6673 holds the correct displacement size. */
6676 gas_assert (i
.op
[op
].disps
== 0);
6677 exp
= &disp_expressions
[i
.disp_operands
++];
6678 i
.op
[op
].disps
= exp
;
6679 exp
->X_op
= O_constant
;
6680 exp
->X_add_number
= 0;
6681 exp
->X_add_symbol
= (symbolS
*) 0;
6682 exp
->X_op_symbol
= (symbolS
*) 0;
6690 if (i
.tm
.opcode_modifier
.vexsources
== XOP2SOURCES
)
6692 if (operand_type_check (i
.types
[0], imm
))
6693 i
.vex
.register_specifier
= NULL
;
6696 /* VEX.vvvv encodes one of the sources when the first
6697 operand is not an immediate. */
6698 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
6699 i
.vex
.register_specifier
= i
.op
[0].regs
;
6701 i
.vex
.register_specifier
= i
.op
[1].regs
;
6704 /* Destination is a XMM register encoded in the ModRM.reg
6706 i
.rm
.reg
= i
.op
[2].regs
->reg_num
;
6707 if ((i
.op
[2].regs
->reg_flags
& RegRex
) != 0)
6710 /* ModRM.rm and VEX.B encodes the other source. */
6711 if (!i
.mem_operands
)
6715 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
6716 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
6718 i
.rm
.regmem
= i
.op
[0].regs
->reg_num
;
6720 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
6724 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXLWP
)
6726 i
.vex
.register_specifier
= i
.op
[2].regs
;
6727 if (!i
.mem_operands
)
6730 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
6731 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
6735 /* Fill in i.rm.reg or i.rm.regmem field with register operand
6736 (if any) based on i.tm.extension_opcode. Again, we must be
6737 careful to make sure that segment/control/debug/test/MMX
6738 registers are coded into the i.rm.reg field. */
6739 else if (i
.reg_operands
)
6742 unsigned int vex_reg
= ~0;
6744 for (op
= 0; op
< i
.operands
; op
++)
6745 if (i
.types
[op
].bitfield
.reg8
6746 || i
.types
[op
].bitfield
.reg16
6747 || i
.types
[op
].bitfield
.reg32
6748 || i
.types
[op
].bitfield
.reg64
6749 || i
.types
[op
].bitfield
.regmmx
6750 || i
.types
[op
].bitfield
.regxmm
6751 || i
.types
[op
].bitfield
.regymm
6752 || i
.types
[op
].bitfield
.regbnd
6753 || i
.types
[op
].bitfield
.regzmm
6754 || i
.types
[op
].bitfield
.regmask
6755 || i
.types
[op
].bitfield
.sreg2
6756 || i
.types
[op
].bitfield
.sreg3
6757 || i
.types
[op
].bitfield
.control
6758 || i
.types
[op
].bitfield
.debug
6759 || i
.types
[op
].bitfield
.test
)
6764 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
6766 /* For instructions with VexNDS, the register-only
6767 source operand is encoded in VEX prefix. */
6768 gas_assert (mem
!= (unsigned int) ~0);
6773 gas_assert (op
< i
.operands
);
6777 /* Check register-only source operand when two source
6778 operands are swapped. */
6779 if (!i
.tm
.operand_types
[op
].bitfield
.baseindex
6780 && i
.tm
.operand_types
[op
+ 1].bitfield
.baseindex
)
6784 gas_assert (mem
== (vex_reg
+ 1)
6785 && op
< i
.operands
);
6790 gas_assert (vex_reg
< i
.operands
);
6794 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXNDD
)
6796 /* For instructions with VexNDD, the register destination
6797 is encoded in VEX prefix. */
6798 if (i
.mem_operands
== 0)
6800 /* There is no memory operand. */
6801 gas_assert ((op
+ 2) == i
.operands
);
6806 /* There are only 2 operands. */
6807 gas_assert (op
< 2 && i
.operands
== 2);
6812 gas_assert (op
< i
.operands
);
6814 if (vex_reg
!= (unsigned int) ~0)
6816 i386_operand_type
*type
= &i
.tm
.operand_types
[vex_reg
];
6818 if (type
->bitfield
.reg32
!= 1
6819 && type
->bitfield
.reg64
!= 1
6820 && !operand_type_equal (type
, ®xmm
)
6821 && !operand_type_equal (type
, ®ymm
)
6822 && !operand_type_equal (type
, ®zmm
)
6823 && !operand_type_equal (type
, ®mask
))
6826 i
.vex
.register_specifier
= i
.op
[vex_reg
].regs
;
6829 /* Don't set OP operand twice. */
6832 /* If there is an extension opcode to put here, the
6833 register number must be put into the regmem field. */
6834 if (i
.tm
.extension_opcode
!= None
)
6836 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
6837 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
6839 if ((i
.op
[op
].regs
->reg_flags
& RegVRex
) != 0)
6844 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
6845 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
6847 if ((i
.op
[op
].regs
->reg_flags
& RegVRex
) != 0)
6852 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
6853 must set it to 3 to indicate this is a register operand
6854 in the regmem field. */
6855 if (!i
.mem_operands
)
6859 /* Fill in i.rm.reg field with extension opcode (if any). */
6860 if (i
.tm
.extension_opcode
!= None
)
6861 i
.rm
.reg
= i
.tm
.extension_opcode
;
6867 output_branch (void)
6873 relax_substateT subtype
;
6877 code16
= flag_code
== CODE_16BIT
? CODE16
: 0;
6878 size
= i
.disp_encoding
== disp_encoding_32bit
? BIG
: SMALL
;
6881 if (i
.prefix
[DATA_PREFIX
] != 0)
6887 /* Pentium4 branch hints. */
6888 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
6889 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
6894 if (i
.prefix
[REX_PREFIX
] != 0)
6900 /* BND prefixed jump. */
6901 if (i
.prefix
[BND_PREFIX
] != 0)
6903 FRAG_APPEND_1_CHAR (i
.prefix
[BND_PREFIX
]);
6907 if (i
.prefixes
!= 0 && !intel_syntax
)
6908 as_warn (_("skipping prefixes on this instruction"));
6910 /* It's always a symbol; End frag & setup for relax.
6911 Make sure there is enough room in this frag for the largest
6912 instruction we may generate in md_convert_frag. This is 2
6913 bytes for the opcode and room for the prefix and largest
6915 frag_grow (prefix
+ 2 + 4);
6916 /* Prefix and 1 opcode byte go in fr_fix. */
6917 p
= frag_more (prefix
+ 1);
6918 if (i
.prefix
[DATA_PREFIX
] != 0)
6919 *p
++ = DATA_PREFIX_OPCODE
;
6920 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
6921 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
6922 *p
++ = i
.prefix
[SEG_PREFIX
];
6923 if (i
.prefix
[REX_PREFIX
] != 0)
6924 *p
++ = i
.prefix
[REX_PREFIX
];
6925 *p
= i
.tm
.base_opcode
;
6927 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
6928 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, size
);
6929 else if (cpu_arch_flags
.bitfield
.cpui386
)
6930 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, size
);
6932 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, size
);
6935 sym
= i
.op
[0].disps
->X_add_symbol
;
6936 off
= i
.op
[0].disps
->X_add_number
;
6938 if (i
.op
[0].disps
->X_op
!= O_constant
6939 && i
.op
[0].disps
->X_op
!= O_symbol
)
6941 /* Handle complex expressions. */
6942 sym
= make_expr_symbol (i
.op
[0].disps
);
6946 /* 1 possible extra opcode + 4 byte displacement go in var part.
6947 Pass reloc in fr_var. */
6948 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
6958 if (i
.tm
.opcode_modifier
.jumpbyte
)
6960 /* This is a loop or jecxz type instruction. */
6962 if (i
.prefix
[ADDR_PREFIX
] != 0)
6964 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
6967 /* Pentium4 branch hints. */
6968 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
6969 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
6971 FRAG_APPEND_1_CHAR (i
.prefix
[SEG_PREFIX
]);
6980 if (flag_code
== CODE_16BIT
)
6983 if (i
.prefix
[DATA_PREFIX
] != 0)
6985 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
6995 if (i
.prefix
[REX_PREFIX
] != 0)
6997 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
7001 /* BND prefixed jump. */
7002 if (i
.prefix
[BND_PREFIX
] != 0)
7004 FRAG_APPEND_1_CHAR (i
.prefix
[BND_PREFIX
]);
7008 if (i
.prefixes
!= 0 && !intel_syntax
)
7009 as_warn (_("skipping prefixes on this instruction"));
7011 p
= frag_more (i
.tm
.opcode_length
+ size
);
7012 switch (i
.tm
.opcode_length
)
7015 *p
++ = i
.tm
.base_opcode
>> 8;
7018 *p
++ = i
.tm
.base_opcode
;
7024 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
7025 i
.op
[0].disps
, 1, reloc (size
, 1, 1, i
.reloc
[0]));
7027 /* All jumps handled here are signed, but don't use a signed limit
7028 check for 32 and 16 bit jumps as we want to allow wrap around at
7029 4G and 64k respectively. */
7031 fixP
->fx_signed
= 1;
7035 output_interseg_jump (void)
7043 if (flag_code
== CODE_16BIT
)
7047 if (i
.prefix
[DATA_PREFIX
] != 0)
7053 if (i
.prefix
[REX_PREFIX
] != 0)
7063 if (i
.prefixes
!= 0 && !intel_syntax
)
7064 as_warn (_("skipping prefixes on this instruction"));
7066 /* 1 opcode; 2 segment; offset */
7067 p
= frag_more (prefix
+ 1 + 2 + size
);
7069 if (i
.prefix
[DATA_PREFIX
] != 0)
7070 *p
++ = DATA_PREFIX_OPCODE
;
7072 if (i
.prefix
[REX_PREFIX
] != 0)
7073 *p
++ = i
.prefix
[REX_PREFIX
];
7075 *p
++ = i
.tm
.base_opcode
;
7076 if (i
.op
[1].imms
->X_op
== O_constant
)
7078 offsetT n
= i
.op
[1].imms
->X_add_number
;
7081 && !fits_in_unsigned_word (n
)
7082 && !fits_in_signed_word (n
))
7084 as_bad (_("16-bit jump out of range"));
7087 md_number_to_chars (p
, n
, size
);
7090 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
7091 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
7092 if (i
.op
[0].imms
->X_op
!= O_constant
)
7093 as_bad (_("can't handle non absolute segment in `%s'"),
7095 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
7101 fragS
*insn_start_frag
;
7102 offsetT insn_start_off
;
7104 /* Tie dwarf2 debug info to the address at the start of the insn.
7105 We can't do this after the insn has been output as the current
7106 frag may have been closed off. eg. by frag_var. */
7107 dwarf2_emit_insn (0);
7109 insn_start_frag
= frag_now
;
7110 insn_start_off
= frag_now_fix ();
7113 if (i
.tm
.opcode_modifier
.jump
)
7115 else if (i
.tm
.opcode_modifier
.jumpbyte
7116 || i
.tm
.opcode_modifier
.jumpdword
)
7118 else if (i
.tm
.opcode_modifier
.jumpintersegment
)
7119 output_interseg_jump ();
7122 /* Output normal instructions here. */
7126 unsigned int prefix
;
7129 && i
.tm
.base_opcode
== 0xfae
7131 && i
.imm_operands
== 1
7132 && (i
.op
[0].imms
->X_add_number
== 0xe8
7133 || i
.op
[0].imms
->X_add_number
== 0xf0
7134 || i
.op
[0].imms
->X_add_number
== 0xf8))
7136 /* Encode lfence, mfence, and sfence as
7137 f0 83 04 24 00 lock addl $0x0, (%{re}sp). */
7138 offsetT val
= 0x240483f0ULL
;
7140 md_number_to_chars (p
, val
, 5);
7144 /* Some processors fail on LOCK prefix. This options makes
7145 assembler ignore LOCK prefix and serves as a workaround. */
7146 if (omit_lock_prefix
)
7148 if (i
.tm
.base_opcode
== LOCK_PREFIX_OPCODE
)
7150 i
.prefix
[LOCK_PREFIX
] = 0;
7153 /* Since the VEX/EVEX prefix contains the implicit prefix, we
7154 don't need the explicit prefix. */
7155 if (!i
.tm
.opcode_modifier
.vex
&& !i
.tm
.opcode_modifier
.evex
)
7157 switch (i
.tm
.opcode_length
)
7160 if (i
.tm
.base_opcode
& 0xff000000)
7162 prefix
= (i
.tm
.base_opcode
>> 24) & 0xff;
7167 if ((i
.tm
.base_opcode
& 0xff0000) != 0)
7169 prefix
= (i
.tm
.base_opcode
>> 16) & 0xff;
7170 if (i
.tm
.cpu_flags
.bitfield
.cpupadlock
)
7173 if (prefix
!= REPE_PREFIX_OPCODE
7174 || (i
.prefix
[REP_PREFIX
]
7175 != REPE_PREFIX_OPCODE
))
7176 add_prefix (prefix
);
7179 add_prefix (prefix
);
7188 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
7189 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
7190 R_X86_64_GOTTPOFF relocation so that linker can safely
7191 perform IE->LE optimization. */
7192 if (x86_elf_abi
== X86_64_X32_ABI
7194 && i
.reloc
[0] == BFD_RELOC_X86_64_GOTTPOFF
7195 && i
.prefix
[REX_PREFIX
] == 0)
7196 add_prefix (REX_OPCODE
);
7199 /* The prefix bytes. */
7200 for (j
= ARRAY_SIZE (i
.prefix
), q
= i
.prefix
; j
> 0; j
--, q
++)
7202 FRAG_APPEND_1_CHAR (*q
);
7206 for (j
= 0, q
= i
.prefix
; j
< ARRAY_SIZE (i
.prefix
); j
++, q
++)
7211 /* REX byte is encoded in VEX prefix. */
7215 FRAG_APPEND_1_CHAR (*q
);
7218 /* There should be no other prefixes for instructions
7223 /* For EVEX instructions i.vrex should become 0 after
7224 build_evex_prefix. For VEX instructions upper 16 registers
7225 aren't available, so VREX should be 0. */
7228 /* Now the VEX prefix. */
7229 p
= frag_more (i
.vex
.length
);
7230 for (j
= 0; j
< i
.vex
.length
; j
++)
7231 p
[j
] = i
.vex
.bytes
[j
];
7234 /* Now the opcode; be careful about word order here! */
7235 if (i
.tm
.opcode_length
== 1)
7237 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
7241 switch (i
.tm
.opcode_length
)
7245 *p
++ = (i
.tm
.base_opcode
>> 24) & 0xff;
7246 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
7250 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
7260 /* Put out high byte first: can't use md_number_to_chars! */
7261 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
7262 *p
= i
.tm
.base_opcode
& 0xff;
7265 /* Now the modrm byte and sib byte (if present). */
7266 if (i
.tm
.opcode_modifier
.modrm
)
7268 FRAG_APPEND_1_CHAR ((i
.rm
.regmem
<< 0
7271 /* If i.rm.regmem == ESP (4)
7272 && i.rm.mode != (Register mode)
7274 ==> need second modrm byte. */
7275 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
7277 && !(i
.base_reg
&& i
.base_reg
->reg_type
.bitfield
.reg16
))
7278 FRAG_APPEND_1_CHAR ((i
.sib
.base
<< 0
7280 | i
.sib
.scale
<< 6));
7283 if (i
.disp_operands
)
7284 output_disp (insn_start_frag
, insn_start_off
);
7287 output_imm (insn_start_frag
, insn_start_off
);
7293 pi ("" /*line*/, &i
);
7295 #endif /* DEBUG386 */
7298 /* Return the size of the displacement operand N. */
7301 disp_size (unsigned int n
)
7305 /* Vec_Disp8 has to be 8bit. */
7306 if (i
.types
[n
].bitfield
.vec_disp8
)
7308 else if (i
.types
[n
].bitfield
.disp64
)
7310 else if (i
.types
[n
].bitfield
.disp8
)
7312 else if (i
.types
[n
].bitfield
.disp16
)
7317 /* Return the size of the immediate operand N. */
7320 imm_size (unsigned int n
)
7323 if (i
.types
[n
].bitfield
.imm64
)
7325 else if (i
.types
[n
].bitfield
.imm8
|| i
.types
[n
].bitfield
.imm8s
)
7327 else if (i
.types
[n
].bitfield
.imm16
)
7333 output_disp (fragS
*insn_start_frag
, offsetT insn_start_off
)
7338 for (n
= 0; n
< i
.operands
; n
++)
7340 if (i
.types
[n
].bitfield
.vec_disp8
7341 || operand_type_check (i
.types
[n
], disp
))
7343 if (i
.op
[n
].disps
->X_op
== O_constant
)
7345 int size
= disp_size (n
);
7346 offsetT val
= i
.op
[n
].disps
->X_add_number
;
7348 if (i
.types
[n
].bitfield
.vec_disp8
)
7350 val
= offset_in_range (val
, size
);
7351 p
= frag_more (size
);
7352 md_number_to_chars (p
, val
, size
);
7356 enum bfd_reloc_code_real reloc_type
;
7357 int size
= disp_size (n
);
7358 int sign
= i
.types
[n
].bitfield
.disp32s
;
7359 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
7362 /* We can't have 8 bit displacement here. */
7363 gas_assert (!i
.types
[n
].bitfield
.disp8
);
7365 /* The PC relative address is computed relative
7366 to the instruction boundary, so in case immediate
7367 fields follows, we need to adjust the value. */
7368 if (pcrel
&& i
.imm_operands
)
7373 for (n1
= 0; n1
< i
.operands
; n1
++)
7374 if (operand_type_check (i
.types
[n1
], imm
))
7376 /* Only one immediate is allowed for PC
7377 relative address. */
7378 gas_assert (sz
== 0);
7380 i
.op
[n
].disps
->X_add_number
-= sz
;
7382 /* We should find the immediate. */
7383 gas_assert (sz
!= 0);
7386 p
= frag_more (size
);
7387 reloc_type
= reloc (size
, pcrel
, sign
, i
.reloc
[n
]);
7389 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
7390 && (((reloc_type
== BFD_RELOC_32
7391 || reloc_type
== BFD_RELOC_X86_64_32S
7392 || (reloc_type
== BFD_RELOC_64
7394 && (i
.op
[n
].disps
->X_op
== O_symbol
7395 || (i
.op
[n
].disps
->X_op
== O_add
7396 && ((symbol_get_value_expression
7397 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
7399 || reloc_type
== BFD_RELOC_32_PCREL
))
7403 if (insn_start_frag
== frag_now
)
7404 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
7409 add
= insn_start_frag
->fr_fix
- insn_start_off
;
7410 for (fr
= insn_start_frag
->fr_next
;
7411 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
7413 add
+= p
- frag_now
->fr_literal
;
7418 reloc_type
= BFD_RELOC_386_GOTPC
;
7419 i
.op
[n
].imms
->X_add_number
+= add
;
7421 else if (reloc_type
== BFD_RELOC_64
)
7422 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
7424 /* Don't do the adjustment for x86-64, as there
7425 the pcrel addressing is relative to the _next_
7426 insn, and that is taken care of in other code. */
7427 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
7429 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
7430 size
, i
.op
[n
].disps
, pcrel
,
7432 /* Check for "call/jmp *mem", "mov mem, %reg",
7433 "test %reg, mem" and "binop mem, %reg" where binop
7434 is one of adc, add, and, cmp, or, sbb, sub, xor
7435 instructions. Always generate R_386_GOT32X for
7436 "sym*GOT" operand in 32-bit mode. */
7437 if ((generate_relax_relocations
7440 && i
.rm
.regmem
== 5))
7442 || (i
.rm
.mode
== 0 && i
.rm
.regmem
== 5))
7443 && ((i
.operands
== 1
7444 && i
.tm
.base_opcode
== 0xff
7445 && (i
.rm
.reg
== 2 || i
.rm
.reg
== 4))
7447 && (i
.tm
.base_opcode
== 0x8b
7448 || i
.tm
.base_opcode
== 0x85
7449 || (i
.tm
.base_opcode
& 0xc7) == 0x03))))
7453 fixP
->fx_tcbit
= i
.rex
!= 0;
7455 && (i
.base_reg
->reg_num
== RegRip
7456 || i
.base_reg
->reg_num
== RegEip
))
7457 fixP
->fx_tcbit2
= 1;
7460 fixP
->fx_tcbit2
= 1;
7468 output_imm (fragS
*insn_start_frag
, offsetT insn_start_off
)
7473 for (n
= 0; n
< i
.operands
; n
++)
7475 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
7476 if (i
.rounding
&& (int) n
== i
.rounding
->operand
)
7479 if (operand_type_check (i
.types
[n
], imm
))
7481 if (i
.op
[n
].imms
->X_op
== O_constant
)
7483 int size
= imm_size (n
);
7486 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
7488 p
= frag_more (size
);
7489 md_number_to_chars (p
, val
, size
);
7493 /* Not absolute_section.
7494 Need a 32-bit fixup (don't support 8bit
7495 non-absolute imms). Try to support other
7497 enum bfd_reloc_code_real reloc_type
;
7498 int size
= imm_size (n
);
7501 if (i
.types
[n
].bitfield
.imm32s
7502 && (i
.suffix
== QWORD_MNEM_SUFFIX
7503 || (!i
.suffix
&& i
.tm
.opcode_modifier
.no_lsuf
)))
7508 p
= frag_more (size
);
7509 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
7511 /* This is tough to explain. We end up with this one if we
7512 * have operands that look like
7513 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
7514 * obtain the absolute address of the GOT, and it is strongly
7515 * preferable from a performance point of view to avoid using
7516 * a runtime relocation for this. The actual sequence of
7517 * instructions often look something like:
7522 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
7524 * The call and pop essentially return the absolute address
7525 * of the label .L66 and store it in %ebx. The linker itself
7526 * will ultimately change the first operand of the addl so
7527 * that %ebx points to the GOT, but to keep things simple, the
7528 * .o file must have this operand set so that it generates not
7529 * the absolute address of .L66, but the absolute address of
7530 * itself. This allows the linker itself simply treat a GOTPC
7531 * relocation as asking for a pcrel offset to the GOT to be
7532 * added in, and the addend of the relocation is stored in the
7533 * operand field for the instruction itself.
7535 * Our job here is to fix the operand so that it would add
7536 * the correct offset so that %ebx would point to itself. The
7537 * thing that is tricky is that .-.L66 will point to the
7538 * beginning of the instruction, so we need to further modify
7539 * the operand so that it will point to itself. There are
7540 * other cases where you have something like:
7542 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
7544 * and here no correction would be required. Internally in
7545 * the assembler we treat operands of this form as not being
7546 * pcrel since the '.' is explicitly mentioned, and I wonder
7547 * whether it would simplify matters to do it this way. Who
7548 * knows. In earlier versions of the PIC patches, the
7549 * pcrel_adjust field was used to store the correction, but
7550 * since the expression is not pcrel, I felt it would be
7551 * confusing to do it this way. */
7553 if ((reloc_type
== BFD_RELOC_32
7554 || reloc_type
== BFD_RELOC_X86_64_32S
7555 || reloc_type
== BFD_RELOC_64
)
7557 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
7558 && (i
.op
[n
].imms
->X_op
== O_symbol
7559 || (i
.op
[n
].imms
->X_op
== O_add
7560 && ((symbol_get_value_expression
7561 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
7566 if (insn_start_frag
== frag_now
)
7567 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
7572 add
= insn_start_frag
->fr_fix
- insn_start_off
;
7573 for (fr
= insn_start_frag
->fr_next
;
7574 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
7576 add
+= p
- frag_now
->fr_literal
;
7580 reloc_type
= BFD_RELOC_386_GOTPC
;
7582 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
7584 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
7585 i
.op
[n
].imms
->X_add_number
+= add
;
7587 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
7588 i
.op
[n
].imms
, 0, reloc_type
);
7594 /* x86_cons_fix_new is called via the expression parsing code when a
7595 reloc is needed. We use this hook to get the correct .got reloc. */
7596 static int cons_sign
= -1;
7599 x86_cons_fix_new (fragS
*frag
, unsigned int off
, unsigned int len
,
7600 expressionS
*exp
, bfd_reloc_code_real_type r
)
7602 r
= reloc (len
, 0, cons_sign
, r
);
7605 if (exp
->X_op
== O_secrel
)
7607 exp
->X_op
= O_symbol
;
7608 r
= BFD_RELOC_32_SECREL
;
7612 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
7615 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
7616 purpose of the `.dc.a' internal pseudo-op. */
7619 x86_address_bytes (void)
7621 if ((stdoutput
->arch_info
->mach
& bfd_mach_x64_32
))
7623 return stdoutput
->arch_info
->bits_per_address
/ 8;
7626 #if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
7628 # define lex_got(reloc, adjust, types) NULL
7630 /* Parse operands of the form
7631 <symbol>@GOTOFF+<nnn>
7632 and similar .plt or .got references.
7634 If we find one, set up the correct relocation in RELOC and copy the
7635 input string, minus the `@GOTOFF' into a malloc'd buffer for
7636 parsing by the calling routine. Return this buffer, and if ADJUST
7637 is non-null set it to the length of the string we removed from the
7638 input line. Otherwise return NULL. */
7640 lex_got (enum bfd_reloc_code_real
*rel
,
7642 i386_operand_type
*types
)
7644 /* Some of the relocations depend on the size of what field is to
7645 be relocated. But in our callers i386_immediate and i386_displacement
7646 we don't yet know the operand size (this will be set by insn
7647 matching). Hence we record the word32 relocation here,
7648 and adjust the reloc according to the real size in reloc(). */
7649 static const struct {
7652 const enum bfd_reloc_code_real rel
[2];
7653 const i386_operand_type types64
;
7655 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7656 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32
,
7658 OPERAND_TYPE_IMM32_64
},
7660 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real
,
7661 BFD_RELOC_X86_64_PLTOFF64
},
7662 OPERAND_TYPE_IMM64
},
7663 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32
,
7664 BFD_RELOC_X86_64_PLT32
},
7665 OPERAND_TYPE_IMM32_32S_DISP32
},
7666 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real
,
7667 BFD_RELOC_X86_64_GOTPLT64
},
7668 OPERAND_TYPE_IMM64_DISP64
},
7669 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF
,
7670 BFD_RELOC_X86_64_GOTOFF64
},
7671 OPERAND_TYPE_IMM64_DISP64
},
7672 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real
,
7673 BFD_RELOC_X86_64_GOTPCREL
},
7674 OPERAND_TYPE_IMM32_32S_DISP32
},
7675 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD
,
7676 BFD_RELOC_X86_64_TLSGD
},
7677 OPERAND_TYPE_IMM32_32S_DISP32
},
7678 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM
,
7679 _dummy_first_bfd_reloc_code_real
},
7680 OPERAND_TYPE_NONE
},
7681 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real
,
7682 BFD_RELOC_X86_64_TLSLD
},
7683 OPERAND_TYPE_IMM32_32S_DISP32
},
7684 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32
,
7685 BFD_RELOC_X86_64_GOTTPOFF
},
7686 OPERAND_TYPE_IMM32_32S_DISP32
},
7687 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32
,
7688 BFD_RELOC_X86_64_TPOFF32
},
7689 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
7690 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE
,
7691 _dummy_first_bfd_reloc_code_real
},
7692 OPERAND_TYPE_NONE
},
7693 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32
,
7694 BFD_RELOC_X86_64_DTPOFF32
},
7695 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
7696 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE
,
7697 _dummy_first_bfd_reloc_code_real
},
7698 OPERAND_TYPE_NONE
},
7699 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE
,
7700 _dummy_first_bfd_reloc_code_real
},
7701 OPERAND_TYPE_NONE
},
7702 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32
,
7703 BFD_RELOC_X86_64_GOT32
},
7704 OPERAND_TYPE_IMM32_32S_64_DISP32
},
7705 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC
,
7706 BFD_RELOC_X86_64_GOTPC32_TLSDESC
},
7707 OPERAND_TYPE_IMM32_32S_DISP32
},
7708 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL
,
7709 BFD_RELOC_X86_64_TLSDESC_CALL
},
7710 OPERAND_TYPE_IMM32_32S_DISP32
},
7715 #if defined (OBJ_MAYBE_ELF)
7720 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
7721 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
7724 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
7726 int len
= gotrel
[j
].len
;
7727 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
7729 if (gotrel
[j
].rel
[object_64bit
] != 0)
7732 char *tmpbuf
, *past_reloc
;
7734 *rel
= gotrel
[j
].rel
[object_64bit
];
7738 if (flag_code
!= CODE_64BIT
)
7740 types
->bitfield
.imm32
= 1;
7741 types
->bitfield
.disp32
= 1;
7744 *types
= gotrel
[j
].types64
;
7747 if (j
!= 0 && GOT_symbol
== NULL
)
7748 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
7750 /* The length of the first part of our input line. */
7751 first
= cp
- input_line_pointer
;
7753 /* The second part goes from after the reloc token until
7754 (and including) an end_of_line char or comma. */
7755 past_reloc
= cp
+ 1 + len
;
7757 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
7759 second
= cp
+ 1 - past_reloc
;
7761 /* Allocate and copy string. The trailing NUL shouldn't
7762 be necessary, but be safe. */
7763 tmpbuf
= XNEWVEC (char, first
+ second
+ 2);
7764 memcpy (tmpbuf
, input_line_pointer
, first
);
7765 if (second
!= 0 && *past_reloc
!= ' ')
7766 /* Replace the relocation token with ' ', so that
7767 errors like foo@GOTOFF1 will be detected. */
7768 tmpbuf
[first
++] = ' ';
7770 /* Increment length by 1 if the relocation token is
7775 memcpy (tmpbuf
+ first
, past_reloc
, second
);
7776 tmpbuf
[first
+ second
] = '\0';
7780 as_bad (_("@%s reloc is not supported with %d-bit output format"),
7781 gotrel
[j
].str
, 1 << (5 + object_64bit
));
7786 /* Might be a symbol version string. Don't as_bad here. */
7795 /* Parse operands of the form
7796 <symbol>@SECREL32+<nnn>
7798 If we find one, set up the correct relocation in RELOC and copy the
7799 input string, minus the `@SECREL32' into a malloc'd buffer for
7800 parsing by the calling routine. Return this buffer, and if ADJUST
7801 is non-null set it to the length of the string we removed from the
7802 input line. Otherwise return NULL.
7804 This function is copied from the ELF version above adjusted for PE targets. */
7807 lex_got (enum bfd_reloc_code_real
*rel ATTRIBUTE_UNUSED
,
7808 int *adjust ATTRIBUTE_UNUSED
,
7809 i386_operand_type
*types
)
7815 const enum bfd_reloc_code_real rel
[2];
7816 const i386_operand_type types64
;
7820 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL
,
7821 BFD_RELOC_32_SECREL
},
7822 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
7828 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
7829 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
7832 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
7834 int len
= gotrel
[j
].len
;
7836 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
7838 if (gotrel
[j
].rel
[object_64bit
] != 0)
7841 char *tmpbuf
, *past_reloc
;
7843 *rel
= gotrel
[j
].rel
[object_64bit
];
7849 if (flag_code
!= CODE_64BIT
)
7851 types
->bitfield
.imm32
= 1;
7852 types
->bitfield
.disp32
= 1;
7855 *types
= gotrel
[j
].types64
;
7858 /* The length of the first part of our input line. */
7859 first
= cp
- input_line_pointer
;
7861 /* The second part goes from after the reloc token until
7862 (and including) an end_of_line char or comma. */
7863 past_reloc
= cp
+ 1 + len
;
7865 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
7867 second
= cp
+ 1 - past_reloc
;
7869 /* Allocate and copy string. The trailing NUL shouldn't
7870 be necessary, but be safe. */
7871 tmpbuf
= XNEWVEC (char, first
+ second
+ 2);
7872 memcpy (tmpbuf
, input_line_pointer
, first
);
7873 if (second
!= 0 && *past_reloc
!= ' ')
7874 /* Replace the relocation token with ' ', so that
7875 errors like foo@SECLREL321 will be detected. */
7876 tmpbuf
[first
++] = ' ';
7877 memcpy (tmpbuf
+ first
, past_reloc
, second
);
7878 tmpbuf
[first
+ second
] = '\0';
7882 as_bad (_("@%s reloc is not supported with %d-bit output format"),
7883 gotrel
[j
].str
, 1 << (5 + object_64bit
));
7888 /* Might be a symbol version string. Don't as_bad here. */
7894 bfd_reloc_code_real_type
7895 x86_cons (expressionS
*exp
, int size
)
7897 bfd_reloc_code_real_type got_reloc
= NO_RELOC
;
7899 intel_syntax
= -intel_syntax
;
7902 if (size
== 4 || (object_64bit
&& size
== 8))
7904 /* Handle @GOTOFF and the like in an expression. */
7906 char *gotfree_input_line
;
7909 save
= input_line_pointer
;
7910 gotfree_input_line
= lex_got (&got_reloc
, &adjust
, NULL
);
7911 if (gotfree_input_line
)
7912 input_line_pointer
= gotfree_input_line
;
7916 if (gotfree_input_line
)
7918 /* expression () has merrily parsed up to the end of line,
7919 or a comma - in the wrong buffer. Transfer how far
7920 input_line_pointer has moved to the right buffer. */
7921 input_line_pointer
= (save
7922 + (input_line_pointer
- gotfree_input_line
)
7924 free (gotfree_input_line
);
7925 if (exp
->X_op
== O_constant
7926 || exp
->X_op
== O_absent
7927 || exp
->X_op
== O_illegal
7928 || exp
->X_op
== O_register
7929 || exp
->X_op
== O_big
)
7931 char c
= *input_line_pointer
;
7932 *input_line_pointer
= 0;
7933 as_bad (_("missing or invalid expression `%s'"), save
);
7934 *input_line_pointer
= c
;
7941 intel_syntax
= -intel_syntax
;
7944 i386_intel_simplify (exp
);
7950 signed_cons (int size
)
7952 if (flag_code
== CODE_64BIT
)
7960 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
7967 if (exp
.X_op
== O_symbol
)
7968 exp
.X_op
= O_secrel
;
7970 emit_expr (&exp
, 4);
7972 while (*input_line_pointer
++ == ',');
7974 input_line_pointer
--;
7975 demand_empty_rest_of_line ();
7979 /* Handle Vector operations. */
7982 check_VecOperations (char *op_string
, char *op_end
)
7984 const reg_entry
*mask
;
7989 && (op_end
== NULL
|| op_string
< op_end
))
7992 if (*op_string
== '{')
7996 /* Check broadcasts. */
7997 if (strncmp (op_string
, "1to", 3) == 0)
8002 goto duplicated_vec_op
;
8005 if (*op_string
== '8')
8006 bcst_type
= BROADCAST_1TO8
;
8007 else if (*op_string
== '4')
8008 bcst_type
= BROADCAST_1TO4
;
8009 else if (*op_string
== '2')
8010 bcst_type
= BROADCAST_1TO2
;
8011 else if (*op_string
== '1'
8012 && *(op_string
+1) == '6')
8014 bcst_type
= BROADCAST_1TO16
;
8019 as_bad (_("Unsupported broadcast: `%s'"), saved
);
8024 broadcast_op
.type
= bcst_type
;
8025 broadcast_op
.operand
= this_operand
;
8026 i
.broadcast
= &broadcast_op
;
8028 /* Check masking operation. */
8029 else if ((mask
= parse_register (op_string
, &end_op
)) != NULL
)
8031 /* k0 can't be used for write mask. */
8032 if (mask
->reg_num
== 0)
8034 as_bad (_("`%s' can't be used for write mask"),
8041 mask_op
.mask
= mask
;
8042 mask_op
.zeroing
= 0;
8043 mask_op
.operand
= this_operand
;
8049 goto duplicated_vec_op
;
8051 i
.mask
->mask
= mask
;
8053 /* Only "{z}" is allowed here. No need to check
8054 zeroing mask explicitly. */
8055 if (i
.mask
->operand
!= this_operand
)
8057 as_bad (_("invalid write mask `%s'"), saved
);
8064 /* Check zeroing-flag for masking operation. */
8065 else if (*op_string
== 'z')
8069 mask_op
.mask
= NULL
;
8070 mask_op
.zeroing
= 1;
8071 mask_op
.operand
= this_operand
;
8076 if (i
.mask
->zeroing
)
8079 as_bad (_("duplicated `%s'"), saved
);
8083 i
.mask
->zeroing
= 1;
8085 /* Only "{%k}" is allowed here. No need to check mask
8086 register explicitly. */
8087 if (i
.mask
->operand
!= this_operand
)
8089 as_bad (_("invalid zeroing-masking `%s'"),
8098 goto unknown_vec_op
;
8100 if (*op_string
!= '}')
8102 as_bad (_("missing `}' in `%s'"), saved
);
8109 /* We don't know this one. */
8110 as_bad (_("unknown vector operation: `%s'"), saved
);
8118 i386_immediate (char *imm_start
)
8120 char *save_input_line_pointer
;
8121 char *gotfree_input_line
;
8124 i386_operand_type types
;
8126 operand_type_set (&types
, ~0);
8128 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
8130 as_bad (_("at most %d immediate operands are allowed"),
8131 MAX_IMMEDIATE_OPERANDS
);
8135 exp
= &im_expressions
[i
.imm_operands
++];
8136 i
.op
[this_operand
].imms
= exp
;
8138 if (is_space_char (*imm_start
))
8141 save_input_line_pointer
= input_line_pointer
;
8142 input_line_pointer
= imm_start
;
8144 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
8145 if (gotfree_input_line
)
8146 input_line_pointer
= gotfree_input_line
;
8148 exp_seg
= expression (exp
);
8152 /* Handle vector operations. */
8153 if (*input_line_pointer
== '{')
8155 input_line_pointer
= check_VecOperations (input_line_pointer
,
8157 if (input_line_pointer
== NULL
)
8161 if (*input_line_pointer
)
8162 as_bad (_("junk `%s' after expression"), input_line_pointer
);
8164 input_line_pointer
= save_input_line_pointer
;
8165 if (gotfree_input_line
)
8167 free (gotfree_input_line
);
8169 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
8170 exp
->X_op
= O_illegal
;
8173 return i386_finalize_immediate (exp_seg
, exp
, types
, imm_start
);
8177 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
8178 i386_operand_type types
, const char *imm_start
)
8180 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_illegal
|| exp
->X_op
== O_big
)
8183 as_bad (_("missing or invalid immediate expression `%s'"),
8187 else if (exp
->X_op
== O_constant
)
8189 /* Size it properly later. */
8190 i
.types
[this_operand
].bitfield
.imm64
= 1;
8191 /* If not 64bit, sign extend val. */
8192 if (flag_code
!= CODE_64BIT
8193 && (exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
8195 = (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
8197 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8198 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
8199 && exp_seg
!= absolute_section
8200 && exp_seg
!= text_section
8201 && exp_seg
!= data_section
8202 && exp_seg
!= bss_section
8203 && exp_seg
!= undefined_section
8204 && !bfd_is_com_section (exp_seg
))
8206 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
8210 else if (!intel_syntax
&& exp_seg
== reg_section
)
8213 as_bad (_("illegal immediate register operand %s"), imm_start
);
8218 /* This is an address. The size of the address will be
8219 determined later, depending on destination register,
8220 suffix, or the default for the section. */
8221 i
.types
[this_operand
].bitfield
.imm8
= 1;
8222 i
.types
[this_operand
].bitfield
.imm16
= 1;
8223 i
.types
[this_operand
].bitfield
.imm32
= 1;
8224 i
.types
[this_operand
].bitfield
.imm32s
= 1;
8225 i
.types
[this_operand
].bitfield
.imm64
= 1;
8226 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
8234 i386_scale (char *scale
)
8237 char *save
= input_line_pointer
;
8239 input_line_pointer
= scale
;
8240 val
= get_absolute_expression ();
8245 i
.log2_scale_factor
= 0;
8248 i
.log2_scale_factor
= 1;
8251 i
.log2_scale_factor
= 2;
8254 i
.log2_scale_factor
= 3;
8258 char sep
= *input_line_pointer
;
8260 *input_line_pointer
= '\0';
8261 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
8263 *input_line_pointer
= sep
;
8264 input_line_pointer
= save
;
8268 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
8270 as_warn (_("scale factor of %d without an index register"),
8271 1 << i
.log2_scale_factor
);
8272 i
.log2_scale_factor
= 0;
8274 scale
= input_line_pointer
;
8275 input_line_pointer
= save
;
8280 i386_displacement (char *disp_start
, char *disp_end
)
8284 char *save_input_line_pointer
;
8285 char *gotfree_input_line
;
8287 i386_operand_type bigdisp
, types
= anydisp
;
8290 if (i
.disp_operands
== MAX_MEMORY_OPERANDS
)
8292 as_bad (_("at most %d displacement operands are allowed"),
8293 MAX_MEMORY_OPERANDS
);
8297 operand_type_set (&bigdisp
, 0);
8298 if ((i
.types
[this_operand
].bitfield
.jumpabsolute
)
8299 || (!current_templates
->start
->opcode_modifier
.jump
8300 && !current_templates
->start
->opcode_modifier
.jumpdword
))
8302 bigdisp
.bitfield
.disp32
= 1;
8303 override
= (i
.prefix
[ADDR_PREFIX
] != 0);
8304 if (flag_code
== CODE_64BIT
)
8308 bigdisp
.bitfield
.disp32s
= 1;
8309 bigdisp
.bitfield
.disp64
= 1;
8312 else if ((flag_code
== CODE_16BIT
) ^ override
)
8314 bigdisp
.bitfield
.disp32
= 0;
8315 bigdisp
.bitfield
.disp16
= 1;
8320 /* For PC-relative branches, the width of the displacement
8321 is dependent upon data size, not address size. */
8322 override
= (i
.prefix
[DATA_PREFIX
] != 0);
8323 if (flag_code
== CODE_64BIT
)
8325 if (override
|| i
.suffix
== WORD_MNEM_SUFFIX
)
8326 bigdisp
.bitfield
.disp16
= 1;
8329 bigdisp
.bitfield
.disp32
= 1;
8330 bigdisp
.bitfield
.disp32s
= 1;
8336 override
= (i
.suffix
== (flag_code
!= CODE_16BIT
8338 : LONG_MNEM_SUFFIX
));
8339 bigdisp
.bitfield
.disp32
= 1;
8340 if ((flag_code
== CODE_16BIT
) ^ override
)
8342 bigdisp
.bitfield
.disp32
= 0;
8343 bigdisp
.bitfield
.disp16
= 1;
8347 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
8350 exp
= &disp_expressions
[i
.disp_operands
];
8351 i
.op
[this_operand
].disps
= exp
;
8353 save_input_line_pointer
= input_line_pointer
;
8354 input_line_pointer
= disp_start
;
8355 END_STRING_AND_SAVE (disp_end
);
8357 #ifndef GCC_ASM_O_HACK
8358 #define GCC_ASM_O_HACK 0
8361 END_STRING_AND_SAVE (disp_end
+ 1);
8362 if (i
.types
[this_operand
].bitfield
.baseIndex
8363 && displacement_string_end
[-1] == '+')
8365 /* This hack is to avoid a warning when using the "o"
8366 constraint within gcc asm statements.
8369 #define _set_tssldt_desc(n,addr,limit,type) \
8370 __asm__ __volatile__ ( \
8372 "movw %w1,2+%0\n\t" \
8374 "movb %b1,4+%0\n\t" \
8375 "movb %4,5+%0\n\t" \
8376 "movb $0,6+%0\n\t" \
8377 "movb %h1,7+%0\n\t" \
8379 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
8381 This works great except that the output assembler ends
8382 up looking a bit weird if it turns out that there is
8383 no offset. You end up producing code that looks like:
8396 So here we provide the missing zero. */
8398 *displacement_string_end
= '0';
8401 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
8402 if (gotfree_input_line
)
8403 input_line_pointer
= gotfree_input_line
;
8405 exp_seg
= expression (exp
);
8408 if (*input_line_pointer
)
8409 as_bad (_("junk `%s' after expression"), input_line_pointer
);
8411 RESTORE_END_STRING (disp_end
+ 1);
8413 input_line_pointer
= save_input_line_pointer
;
8414 if (gotfree_input_line
)
8416 free (gotfree_input_line
);
8418 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
8419 exp
->X_op
= O_illegal
;
8422 ret
= i386_finalize_displacement (exp_seg
, exp
, types
, disp_start
);
8424 RESTORE_END_STRING (disp_end
);
8430 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
8431 i386_operand_type types
, const char *disp_start
)
8433 i386_operand_type bigdisp
;
8436 /* We do this to make sure that the section symbol is in
8437 the symbol table. We will ultimately change the relocation
8438 to be relative to the beginning of the section. */
8439 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
8440 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
8441 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
8443 if (exp
->X_op
!= O_symbol
)
8446 if (S_IS_LOCAL (exp
->X_add_symbol
)
8447 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
8448 && S_GET_SEGMENT (exp
->X_add_symbol
) != expr_section
)
8449 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
8450 exp
->X_op
= O_subtract
;
8451 exp
->X_op_symbol
= GOT_symbol
;
8452 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
8453 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
8454 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
8455 i
.reloc
[this_operand
] = BFD_RELOC_64
;
8457 i
.reloc
[this_operand
] = BFD_RELOC_32
;
8460 else if (exp
->X_op
== O_absent
8461 || exp
->X_op
== O_illegal
8462 || exp
->X_op
== O_big
)
8465 as_bad (_("missing or invalid displacement expression `%s'"),
8470 else if (flag_code
== CODE_64BIT
8471 && !i
.prefix
[ADDR_PREFIX
]
8472 && exp
->X_op
== O_constant
)
8474 /* Since displacement is signed extended to 64bit, don't allow
8475 disp32 and turn off disp32s if they are out of range. */
8476 i
.types
[this_operand
].bitfield
.disp32
= 0;
8477 if (!fits_in_signed_long (exp
->X_add_number
))
8479 i
.types
[this_operand
].bitfield
.disp32s
= 0;
8480 if (i
.types
[this_operand
].bitfield
.baseindex
)
8482 as_bad (_("0x%lx out range of signed 32bit displacement"),
8483 (long) exp
->X_add_number
);
8489 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8490 else if (exp
->X_op
!= O_constant
8491 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
8492 && exp_seg
!= absolute_section
8493 && exp_seg
!= text_section
8494 && exp_seg
!= data_section
8495 && exp_seg
!= bss_section
8496 && exp_seg
!= undefined_section
8497 && !bfd_is_com_section (exp_seg
))
8499 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
8504 /* Check if this is a displacement only operand. */
8505 bigdisp
= i
.types
[this_operand
];
8506 bigdisp
.bitfield
.disp8
= 0;
8507 bigdisp
.bitfield
.disp16
= 0;
8508 bigdisp
.bitfield
.disp32
= 0;
8509 bigdisp
.bitfield
.disp32s
= 0;
8510 bigdisp
.bitfield
.disp64
= 0;
8511 if (operand_type_all_zero (&bigdisp
))
8512 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
8518 /* Make sure the memory operand we've been dealt is valid.
8519 Return 1 on success, 0 on a failure. */
8522 i386_index_check (const char *operand_string
)
8524 const char *kind
= "base/index";
8525 enum flag_code addr_mode
;
8527 if (i
.prefix
[ADDR_PREFIX
])
8528 addr_mode
= flag_code
== CODE_32BIT
? CODE_16BIT
: CODE_32BIT
;
8531 addr_mode
= flag_code
;
8533 #if INFER_ADDR_PREFIX
8534 if (i
.mem_operands
== 0)
8536 /* Infer address prefix from the first memory operand. */
8537 const reg_entry
*addr_reg
= i
.base_reg
;
8539 if (addr_reg
== NULL
)
8540 addr_reg
= i
.index_reg
;
8544 if (addr_reg
->reg_num
== RegEip
8545 || addr_reg
->reg_num
== RegEiz
8546 || addr_reg
->reg_type
.bitfield
.reg32
)
8547 addr_mode
= CODE_32BIT
;
8548 else if (flag_code
!= CODE_64BIT
8549 && addr_reg
->reg_type
.bitfield
.reg16
)
8550 addr_mode
= CODE_16BIT
;
8552 if (addr_mode
!= flag_code
)
8554 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
8556 /* Change the size of any displacement too. At most one
8557 of Disp16 or Disp32 is set.
8558 FIXME. There doesn't seem to be any real need for
8559 separate Disp16 and Disp32 flags. The same goes for
8560 Imm16 and Imm32. Removing them would probably clean
8561 up the code quite a lot. */
8562 if (flag_code
!= CODE_64BIT
8563 && (i
.types
[this_operand
].bitfield
.disp16
8564 || i
.types
[this_operand
].bitfield
.disp32
))
8565 i
.types
[this_operand
]
8566 = operand_type_xor (i
.types
[this_operand
], disp16_32
);
8573 if (current_templates
->start
->opcode_modifier
.isstring
8574 && !current_templates
->start
->opcode_modifier
.immext
8575 && (current_templates
->end
[-1].opcode_modifier
.isstring
8578 /* Memory operands of string insns are special in that they only allow
8579 a single register (rDI, rSI, or rBX) as their memory address. */
8580 const reg_entry
*expected_reg
;
8581 static const char *di_si
[][2] =
8587 static const char *bx
[] = { "ebx", "bx", "rbx" };
8589 kind
= "string address";
8591 if (current_templates
->start
->opcode_modifier
.repprefixok
)
8593 i386_operand_type type
= current_templates
->end
[-1].operand_types
[0];
8595 if (!type
.bitfield
.baseindex
8596 || ((!i
.mem_operands
!= !intel_syntax
)
8597 && current_templates
->end
[-1].operand_types
[1]
8598 .bitfield
.baseindex
))
8599 type
= current_templates
->end
[-1].operand_types
[1];
8600 expected_reg
= hash_find (reg_hash
,
8601 di_si
[addr_mode
][type
.bitfield
.esseg
]);
8605 expected_reg
= hash_find (reg_hash
, bx
[addr_mode
]);
8607 if (i
.base_reg
!= expected_reg
8609 || operand_type_check (i
.types
[this_operand
], disp
))
8611 /* The second memory operand must have the same size as
8615 && !((addr_mode
== CODE_64BIT
8616 && i
.base_reg
->reg_type
.bitfield
.reg64
)
8617 || (addr_mode
== CODE_32BIT
8618 ? i
.base_reg
->reg_type
.bitfield
.reg32
8619 : i
.base_reg
->reg_type
.bitfield
.reg16
)))
8622 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
8624 intel_syntax
? '[' : '(',
8626 expected_reg
->reg_name
,
8627 intel_syntax
? ']' : ')');
8634 as_bad (_("`%s' is not a valid %s expression"),
8635 operand_string
, kind
);
8640 if (addr_mode
!= CODE_16BIT
)
8642 /* 32-bit/64-bit checks. */
8644 && (addr_mode
== CODE_64BIT
8645 ? !i
.base_reg
->reg_type
.bitfield
.reg64
8646 : !i
.base_reg
->reg_type
.bitfield
.reg32
)
8648 || (i
.base_reg
->reg_num
8649 != (addr_mode
== CODE_64BIT
? RegRip
: RegEip
))))
8651 && !i
.index_reg
->reg_type
.bitfield
.regxmm
8652 && !i
.index_reg
->reg_type
.bitfield
.regymm
8653 && !i
.index_reg
->reg_type
.bitfield
.regzmm
8654 && ((addr_mode
== CODE_64BIT
8655 ? !(i
.index_reg
->reg_type
.bitfield
.reg64
8656 || i
.index_reg
->reg_num
== RegRiz
)
8657 : !(i
.index_reg
->reg_type
.bitfield
.reg32
8658 || i
.index_reg
->reg_num
== RegEiz
))
8659 || !i
.index_reg
->reg_type
.bitfield
.baseindex
)))
8662 /* bndmk, bndldx, and bndstx have special restrictions. */
8663 if (current_templates
->start
->base_opcode
== 0xf30f1b
8664 || (current_templates
->start
->base_opcode
& ~1) == 0x0f1a)
8666 /* They cannot use RIP-relative addressing. */
8667 if (i
.base_reg
&& i
.base_reg
->reg_num
== RegRip
)
8669 as_bad (_("`%s' cannot be used here"), operand_string
);
8673 /* bndldx and bndstx ignore their scale factor. */
8674 if (current_templates
->start
->base_opcode
!= 0xf30f1b
8675 && i
.log2_scale_factor
)
8676 as_warn (_("register scaling is being ignored here"));
8681 /* 16-bit checks. */
8683 && (!i
.base_reg
->reg_type
.bitfield
.reg16
8684 || !i
.base_reg
->reg_type
.bitfield
.baseindex
))
8686 && (!i
.index_reg
->reg_type
.bitfield
.reg16
8687 || !i
.index_reg
->reg_type
.bitfield
.baseindex
8689 && i
.base_reg
->reg_num
< 6
8690 && i
.index_reg
->reg_num
>= 6
8691 && i
.log2_scale_factor
== 0))))
8698 /* Handle vector immediates. */
8701 RC_SAE_immediate (const char *imm_start
)
8703 unsigned int match_found
, j
;
8704 const char *pstr
= imm_start
;
8712 for (j
= 0; j
< ARRAY_SIZE (RC_NamesTable
); j
++)
8714 if (!strncmp (pstr
, RC_NamesTable
[j
].name
, RC_NamesTable
[j
].len
))
8718 rc_op
.type
= RC_NamesTable
[j
].type
;
8719 rc_op
.operand
= this_operand
;
8720 i
.rounding
= &rc_op
;
8724 as_bad (_("duplicated `%s'"), imm_start
);
8727 pstr
+= RC_NamesTable
[j
].len
;
8737 as_bad (_("Missing '}': '%s'"), imm_start
);
8740 /* RC/SAE immediate string should contain nothing more. */;
8743 as_bad (_("Junk after '}': '%s'"), imm_start
);
8747 exp
= &im_expressions
[i
.imm_operands
++];
8748 i
.op
[this_operand
].imms
= exp
;
8750 exp
->X_op
= O_constant
;
8751 exp
->X_add_number
= 0;
8752 exp
->X_add_symbol
= (symbolS
*) 0;
8753 exp
->X_op_symbol
= (symbolS
*) 0;
8755 i
.types
[this_operand
].bitfield
.imm8
= 1;
8759 /* Only string instructions can have a second memory operand, so
8760 reduce current_templates to just those if it contains any. */
8762 maybe_adjust_templates (void)
8764 const insn_template
*t
;
8766 gas_assert (i
.mem_operands
== 1);
8768 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
8769 if (t
->opcode_modifier
.isstring
)
8772 if (t
< current_templates
->end
)
8774 static templates aux_templates
;
8775 bfd_boolean recheck
;
8777 aux_templates
.start
= t
;
8778 for (; t
< current_templates
->end
; ++t
)
8779 if (!t
->opcode_modifier
.isstring
)
8781 aux_templates
.end
= t
;
8783 /* Determine whether to re-check the first memory operand. */
8784 recheck
= (aux_templates
.start
!= current_templates
->start
8785 || t
!= current_templates
->end
);
8787 current_templates
= &aux_templates
;
8792 if (i
.memop1_string
!= NULL
8793 && i386_index_check (i
.memop1_string
) == 0)
8802 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
8806 i386_att_operand (char *operand_string
)
8810 char *op_string
= operand_string
;
8812 if (is_space_char (*op_string
))
8815 /* We check for an absolute prefix (differentiating,
8816 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
8817 if (*op_string
== ABSOLUTE_PREFIX
)
8820 if (is_space_char (*op_string
))
8822 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
8825 /* Check if operand is a register. */
8826 if ((r
= parse_register (op_string
, &end_op
)) != NULL
)
8828 i386_operand_type temp
;
8830 /* Check for a segment override by searching for ':' after a
8831 segment register. */
8833 if (is_space_char (*op_string
))
8835 if (*op_string
== ':'
8836 && (r
->reg_type
.bitfield
.sreg2
8837 || r
->reg_type
.bitfield
.sreg3
))
8842 i
.seg
[i
.mem_operands
] = &es
;
8845 i
.seg
[i
.mem_operands
] = &cs
;
8848 i
.seg
[i
.mem_operands
] = &ss
;
8851 i
.seg
[i
.mem_operands
] = &ds
;
8854 i
.seg
[i
.mem_operands
] = &fs
;
8857 i
.seg
[i
.mem_operands
] = &gs
;
8861 /* Skip the ':' and whitespace. */
8863 if (is_space_char (*op_string
))
8866 if (!is_digit_char (*op_string
)
8867 && !is_identifier_char (*op_string
)
8868 && *op_string
!= '('
8869 && *op_string
!= ABSOLUTE_PREFIX
)
8871 as_bad (_("bad memory operand `%s'"), op_string
);
8874 /* Handle case of %es:*foo. */
8875 if (*op_string
== ABSOLUTE_PREFIX
)
8878 if (is_space_char (*op_string
))
8880 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
8882 goto do_memory_reference
;
8885 /* Handle vector operations. */
8886 if (*op_string
== '{')
8888 op_string
= check_VecOperations (op_string
, NULL
);
8889 if (op_string
== NULL
)
8895 as_bad (_("junk `%s' after register"), op_string
);
8899 temp
.bitfield
.baseindex
= 0;
8900 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
8902 i
.types
[this_operand
].bitfield
.unspecified
= 0;
8903 i
.op
[this_operand
].regs
= r
;
8906 else if (*op_string
== REGISTER_PREFIX
)
8908 as_bad (_("bad register name `%s'"), op_string
);
8911 else if (*op_string
== IMMEDIATE_PREFIX
)
8914 if (i
.types
[this_operand
].bitfield
.jumpabsolute
)
8916 as_bad (_("immediate operand illegal with absolute jump"));
8919 if (!i386_immediate (op_string
))
8922 else if (RC_SAE_immediate (operand_string
))
8924 /* If it is a RC or SAE immediate, do nothing. */
8927 else if (is_digit_char (*op_string
)
8928 || is_identifier_char (*op_string
)
8929 || *op_string
== '"'
8930 || *op_string
== '(')
8932 /* This is a memory reference of some sort. */
8935 /* Start and end of displacement string expression (if found). */
8936 char *displacement_string_start
;
8937 char *displacement_string_end
;
8940 do_memory_reference
:
8941 if (i
.mem_operands
== 1 && !maybe_adjust_templates ())
8943 if ((i
.mem_operands
== 1
8944 && !current_templates
->start
->opcode_modifier
.isstring
)
8945 || i
.mem_operands
== 2)
8947 as_bad (_("too many memory references for `%s'"),
8948 current_templates
->start
->name
);
8952 /* Check for base index form. We detect the base index form by
8953 looking for an ')' at the end of the operand, searching
8954 for the '(' matching it, and finding a REGISTER_PREFIX or ','
8956 base_string
= op_string
+ strlen (op_string
);
8958 /* Handle vector operations. */
8959 vop_start
= strchr (op_string
, '{');
8960 if (vop_start
&& vop_start
< base_string
)
8962 if (check_VecOperations (vop_start
, base_string
) == NULL
)
8964 base_string
= vop_start
;
8968 if (is_space_char (*base_string
))
8971 /* If we only have a displacement, set-up for it to be parsed later. */
8972 displacement_string_start
= op_string
;
8973 displacement_string_end
= base_string
+ 1;
8975 if (*base_string
== ')')
8978 unsigned int parens_balanced
= 1;
8979 /* We've already checked that the number of left & right ()'s are
8980 equal, so this loop will not be infinite. */
8984 if (*base_string
== ')')
8986 if (*base_string
== '(')
8989 while (parens_balanced
);
8991 temp_string
= base_string
;
8993 /* Skip past '(' and whitespace. */
8995 if (is_space_char (*base_string
))
8998 if (*base_string
== ','
8999 || ((i
.base_reg
= parse_register (base_string
, &end_op
))
9002 displacement_string_end
= temp_string
;
9004 i
.types
[this_operand
].bitfield
.baseindex
= 1;
9008 base_string
= end_op
;
9009 if (is_space_char (*base_string
))
9013 /* There may be an index reg or scale factor here. */
9014 if (*base_string
== ',')
9017 if (is_space_char (*base_string
))
9020 if ((i
.index_reg
= parse_register (base_string
, &end_op
))
9023 base_string
= end_op
;
9024 if (is_space_char (*base_string
))
9026 if (*base_string
== ',')
9029 if (is_space_char (*base_string
))
9032 else if (*base_string
!= ')')
9034 as_bad (_("expecting `,' or `)' "
9035 "after index register in `%s'"),
9040 else if (*base_string
== REGISTER_PREFIX
)
9042 end_op
= strchr (base_string
, ',');
9045 as_bad (_("bad register name `%s'"), base_string
);
9049 /* Check for scale factor. */
9050 if (*base_string
!= ')')
9052 char *end_scale
= i386_scale (base_string
);
9057 base_string
= end_scale
;
9058 if (is_space_char (*base_string
))
9060 if (*base_string
!= ')')
9062 as_bad (_("expecting `)' "
9063 "after scale factor in `%s'"),
9068 else if (!i
.index_reg
)
9070 as_bad (_("expecting index register or scale factor "
9071 "after `,'; got '%c'"),
9076 else if (*base_string
!= ')')
9078 as_bad (_("expecting `,' or `)' "
9079 "after base register in `%s'"),
9084 else if (*base_string
== REGISTER_PREFIX
)
9086 end_op
= strchr (base_string
, ',');
9089 as_bad (_("bad register name `%s'"), base_string
);
9094 /* If there's an expression beginning the operand, parse it,
9095 assuming displacement_string_start and
9096 displacement_string_end are meaningful. */
9097 if (displacement_string_start
!= displacement_string_end
)
9099 if (!i386_displacement (displacement_string_start
,
9100 displacement_string_end
))
9104 /* Special case for (%dx) while doing input/output op. */
9106 && operand_type_equal (&i
.base_reg
->reg_type
,
9107 ®16_inoutportreg
)
9109 && i
.log2_scale_factor
== 0
9110 && i
.seg
[i
.mem_operands
] == 0
9111 && !operand_type_check (i
.types
[this_operand
], disp
))
9113 i
.types
[this_operand
] = inoutportreg
;
9117 if (i386_index_check (operand_string
) == 0)
9119 i
.types
[this_operand
].bitfield
.mem
= 1;
9120 if (i
.mem_operands
== 0)
9121 i
.memop1_string
= xstrdup (operand_string
);
9126 /* It's not a memory operand; argh! */
9127 as_bad (_("invalid char %s beginning operand %d `%s'"),
9128 output_invalid (*op_string
),
9133 return 1; /* Normal return. */
9136 /* Calculate the maximum variable size (i.e., excluding fr_fix)
9137 that an rs_machine_dependent frag may reach. */
9140 i386_frag_max_var (fragS
*frag
)
9142 /* The only relaxable frags are for jumps.
9143 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
9144 gas_assert (frag
->fr_type
== rs_machine_dependent
);
9145 return TYPE_FROM_RELAX_STATE (frag
->fr_subtype
) == UNCOND_JUMP
? 4 : 5;
9148 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9150 elf_symbol_resolved_in_segment_p (symbolS
*fr_symbol
, offsetT fr_var
)
9152 /* STT_GNU_IFUNC symbol must go through PLT. */
9153 if ((symbol_get_bfdsym (fr_symbol
)->flags
9154 & BSF_GNU_INDIRECT_FUNCTION
) != 0)
9157 if (!S_IS_EXTERNAL (fr_symbol
))
9158 /* Symbol may be weak or local. */
9159 return !S_IS_WEAK (fr_symbol
);
9161 /* Global symbols with non-default visibility can't be preempted. */
9162 if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol
)) != STV_DEFAULT
)
9165 if (fr_var
!= NO_RELOC
)
9166 switch ((enum bfd_reloc_code_real
) fr_var
)
9168 case BFD_RELOC_386_PLT32
:
9169 case BFD_RELOC_X86_64_PLT32
:
9170 /* Symbol with PLT relocation may be preempted. */
9176 /* Global symbols with default visibility in a shared library may be
9177 preempted by another definition. */
9182 /* md_estimate_size_before_relax()
9184 Called just before relax() for rs_machine_dependent frags. The x86
9185 assembler uses these frags to handle variable size jump
9188 Any symbol that is now undefined will not become defined.
9189 Return the correct fr_subtype in the frag.
9190 Return the initial "guess for variable size of frag" to caller.
9191 The guess is actually the growth beyond the fixed part. Whatever
9192 we do to grow the fixed or variable part contributes to our
9196 md_estimate_size_before_relax (fragS
*fragP
, segT segment
)
9198 /* We've already got fragP->fr_subtype right; all we have to do is
9199 check for un-relaxable symbols. On an ELF system, we can't relax
9200 an externally visible symbol, because it may be overridden by a
9202 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
9203 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9205 && !elf_symbol_resolved_in_segment_p (fragP
->fr_symbol
,
9208 #if defined (OBJ_COFF) && defined (TE_PE)
9209 || (OUTPUT_FLAVOR
== bfd_target_coff_flavour
9210 && S_IS_WEAK (fragP
->fr_symbol
))
9214 /* Symbol is undefined in this segment, or we need to keep a
9215 reloc so that weak symbols can be overridden. */
9216 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
9217 enum bfd_reloc_code_real reloc_type
;
9218 unsigned char *opcode
;
9221 if (fragP
->fr_var
!= NO_RELOC
)
9222 reloc_type
= (enum bfd_reloc_code_real
) fragP
->fr_var
;
9224 reloc_type
= BFD_RELOC_16_PCREL
;
9226 reloc_type
= BFD_RELOC_32_PCREL
;
9228 old_fr_fix
= fragP
->fr_fix
;
9229 opcode
= (unsigned char *) fragP
->fr_opcode
;
9231 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
9234 /* Make jmp (0xeb) a (d)word displacement jump. */
9236 fragP
->fr_fix
+= size
;
9237 fix_new (fragP
, old_fr_fix
, size
,
9239 fragP
->fr_offset
, 1,
9245 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
9247 /* Negate the condition, and branch past an
9248 unconditional jump. */
9251 /* Insert an unconditional jump. */
9253 /* We added two extra opcode bytes, and have a two byte
9255 fragP
->fr_fix
+= 2 + 2;
9256 fix_new (fragP
, old_fr_fix
+ 2, 2,
9258 fragP
->fr_offset
, 1,
9265 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
9270 fixP
= fix_new (fragP
, old_fr_fix
, 1,
9272 fragP
->fr_offset
, 1,
9274 fixP
->fx_signed
= 1;
9278 /* This changes the byte-displacement jump 0x7N
9279 to the (d)word-displacement jump 0x0f,0x8N. */
9280 opcode
[1] = opcode
[0] + 0x10;
9281 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
9282 /* We've added an opcode byte. */
9283 fragP
->fr_fix
+= 1 + size
;
9284 fix_new (fragP
, old_fr_fix
+ 1, size
,
9286 fragP
->fr_offset
, 1,
9291 BAD_CASE (fragP
->fr_subtype
);
9295 return fragP
->fr_fix
- old_fr_fix
;
9298 /* Guess size depending on current relax state. Initially the relax
9299 state will correspond to a short jump and we return 1, because
9300 the variable part of the frag (the branch offset) is one byte
9301 long. However, we can relax a section more than once and in that
9302 case we must either set fr_subtype back to the unrelaxed state,
9303 or return the value for the appropriate branch. */
9304 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
9307 /* Called after relax() is finished.
9309 In: Address of frag.
9310 fr_type == rs_machine_dependent.
9311 fr_subtype is what the address relaxed to.
9313 Out: Any fixSs and constants are set up.
9314 Caller will turn frag into a ".space 0". */
9317 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec ATTRIBUTE_UNUSED
,
9320 unsigned char *opcode
;
9321 unsigned char *where_to_put_displacement
= NULL
;
9322 offsetT target_address
;
9323 offsetT opcode_address
;
9324 unsigned int extension
= 0;
9325 offsetT displacement_from_opcode_start
;
9327 opcode
= (unsigned char *) fragP
->fr_opcode
;
9329 /* Address we want to reach in file space. */
9330 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
9332 /* Address opcode resides at in file space. */
9333 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
9335 /* Displacement from opcode start to fill into instruction. */
9336 displacement_from_opcode_start
= target_address
- opcode_address
;
9338 if ((fragP
->fr_subtype
& BIG
) == 0)
9340 /* Don't have to change opcode. */
9341 extension
= 1; /* 1 opcode + 1 displacement */
9342 where_to_put_displacement
= &opcode
[1];
9346 if (no_cond_jump_promotion
9347 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
9348 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
9349 _("long jump required"));
9351 switch (fragP
->fr_subtype
)
9353 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
9354 extension
= 4; /* 1 opcode + 4 displacement */
9356 where_to_put_displacement
= &opcode
[1];
9359 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
9360 extension
= 2; /* 1 opcode + 2 displacement */
9362 where_to_put_displacement
= &opcode
[1];
9365 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
9366 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
9367 extension
= 5; /* 2 opcode + 4 displacement */
9368 opcode
[1] = opcode
[0] + 0x10;
9369 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
9370 where_to_put_displacement
= &opcode
[2];
9373 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
9374 extension
= 3; /* 2 opcode + 2 displacement */
9375 opcode
[1] = opcode
[0] + 0x10;
9376 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
9377 where_to_put_displacement
= &opcode
[2];
9380 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
9385 where_to_put_displacement
= &opcode
[3];
9389 BAD_CASE (fragP
->fr_subtype
);
9394 /* If size if less then four we are sure that the operand fits,
9395 but if it's 4, then it could be that the displacement is larger
9397 if (DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
) == 4
9399 && ((addressT
) (displacement_from_opcode_start
- extension
9400 + ((addressT
) 1 << 31))
9401 > (((addressT
) 2 << 31) - 1)))
9403 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
9404 _("jump target out of range"));
9405 /* Make us emit 0. */
9406 displacement_from_opcode_start
= extension
;
9408 /* Now put displacement after opcode. */
9409 md_number_to_chars ((char *) where_to_put_displacement
,
9410 (valueT
) (displacement_from_opcode_start
- extension
),
9411 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
9412 fragP
->fr_fix
+= extension
;
9415 /* Apply a fixup (fixP) to segment data, once it has been determined
9416 by our caller that we have all the info we need to fix it up.
9418 Parameter valP is the pointer to the value of the bits.
9420 On the 386, immediates, displacements, and data pointers are all in
9421 the same (little-endian) format, so we don't need to care about which
9425 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
9427 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
9428 valueT value
= *valP
;
9430 #if !defined (TE_Mach)
9433 switch (fixP
->fx_r_type
)
9439 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
9442 case BFD_RELOC_X86_64_32S
:
9443 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
9446 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
9449 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
9454 if (fixP
->fx_addsy
!= NULL
9455 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
9456 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
9457 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
9458 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
9459 && !use_rela_relocations
)
9461 /* This is a hack. There should be a better way to handle this.
9462 This covers for the fact that bfd_install_relocation will
9463 subtract the current location (for partial_inplace, PC relative
9464 relocations); see more below. */
9468 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
9471 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
9473 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9476 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
9479 || (symbol_section_p (fixP
->fx_addsy
)
9480 && sym_seg
!= absolute_section
))
9481 && !generic_force_reloc (fixP
))
9483 /* Yes, we add the values in twice. This is because
9484 bfd_install_relocation subtracts them out again. I think
9485 bfd_install_relocation is broken, but I don't dare change
9487 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
9491 #if defined (OBJ_COFF) && defined (TE_PE)
9492 /* For some reason, the PE format does not store a
9493 section address offset for a PC relative symbol. */
9494 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
9495 || S_IS_WEAK (fixP
->fx_addsy
))
9496 value
+= md_pcrel_from (fixP
);
9499 #if defined (OBJ_COFF) && defined (TE_PE)
9500 if (fixP
->fx_addsy
!= NULL
9501 && S_IS_WEAK (fixP
->fx_addsy
)
9502 /* PR 16858: Do not modify weak function references. */
9503 && ! fixP
->fx_pcrel
)
9505 #if !defined (TE_PEP)
9506 /* For x86 PE weak function symbols are neither PC-relative
9507 nor do they set S_IS_FUNCTION. So the only reliable way
9508 to detect them is to check the flags of their containing
9510 if (S_GET_SEGMENT (fixP
->fx_addsy
) != NULL
9511 && S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_CODE
)
9515 value
-= S_GET_VALUE (fixP
->fx_addsy
);
9519 /* Fix a few things - the dynamic linker expects certain values here,
9520 and we must not disappoint it. */
9521 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9522 if (IS_ELF
&& fixP
->fx_addsy
)
9523 switch (fixP
->fx_r_type
)
9525 case BFD_RELOC_386_PLT32
:
9526 case BFD_RELOC_X86_64_PLT32
:
9527 /* Make the jump instruction point to the address of the operand. At
9528 runtime we merely add the offset to the actual PLT entry. */
9532 case BFD_RELOC_386_TLS_GD
:
9533 case BFD_RELOC_386_TLS_LDM
:
9534 case BFD_RELOC_386_TLS_IE_32
:
9535 case BFD_RELOC_386_TLS_IE
:
9536 case BFD_RELOC_386_TLS_GOTIE
:
9537 case BFD_RELOC_386_TLS_GOTDESC
:
9538 case BFD_RELOC_X86_64_TLSGD
:
9539 case BFD_RELOC_X86_64_TLSLD
:
9540 case BFD_RELOC_X86_64_GOTTPOFF
:
9541 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
9542 value
= 0; /* Fully resolved at runtime. No addend. */
9544 case BFD_RELOC_386_TLS_LE
:
9545 case BFD_RELOC_386_TLS_LDO_32
:
9546 case BFD_RELOC_386_TLS_LE_32
:
9547 case BFD_RELOC_X86_64_DTPOFF32
:
9548 case BFD_RELOC_X86_64_DTPOFF64
:
9549 case BFD_RELOC_X86_64_TPOFF32
:
9550 case BFD_RELOC_X86_64_TPOFF64
:
9551 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
9554 case BFD_RELOC_386_TLS_DESC_CALL
:
9555 case BFD_RELOC_X86_64_TLSDESC_CALL
:
9556 value
= 0; /* Fully resolved at runtime. No addend. */
9557 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
9561 case BFD_RELOC_VTABLE_INHERIT
:
9562 case BFD_RELOC_VTABLE_ENTRY
:
9569 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
9571 #endif /* !defined (TE_Mach) */
9573 /* Are we finished with this relocation now? */
9574 if (fixP
->fx_addsy
== NULL
)
9576 #if defined (OBJ_COFF) && defined (TE_PE)
9577 else if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
9580 /* Remember value for tc_gen_reloc. */
9581 fixP
->fx_addnumber
= value
;
9582 /* Clear out the frag for now. */
9586 else if (use_rela_relocations
)
9588 fixP
->fx_no_overflow
= 1;
9589 /* Remember value for tc_gen_reloc. */
9590 fixP
->fx_addnumber
= value
;
9594 md_number_to_chars (p
, value
, fixP
->fx_size
);
9598 md_atof (int type
, char *litP
, int *sizeP
)
9600 /* This outputs the LITTLENUMs in REVERSE order;
9601 in accord with the bigendian 386. */
9602 return ieee_md_atof (type
, litP
, sizeP
, FALSE
);
9605 static char output_invalid_buf
[sizeof (unsigned char) * 2 + 6];
9608 output_invalid (int c
)
9611 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
9614 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
9615 "(0x%x)", (unsigned char) c
);
9616 return output_invalid_buf
;
9619 /* REG_STRING starts *before* REGISTER_PREFIX. */
9621 static const reg_entry
*
9622 parse_real_register (char *reg_string
, char **end_op
)
9624 char *s
= reg_string
;
9626 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
9629 /* Skip possible REGISTER_PREFIX and possible whitespace. */
9630 if (*s
== REGISTER_PREFIX
)
9633 if (is_space_char (*s
))
9637 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
9639 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
9640 return (const reg_entry
*) NULL
;
9644 /* For naked regs, make sure that we are not dealing with an identifier.
9645 This prevents confusing an identifier like `eax_var' with register
9647 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
9648 return (const reg_entry
*) NULL
;
9652 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
9654 /* Handle floating point regs, allowing spaces in the (i) part. */
9655 if (r
== i386_regtab
/* %st is first entry of table */)
9657 if (is_space_char (*s
))
9662 if (is_space_char (*s
))
9664 if (*s
>= '0' && *s
<= '7')
9668 if (is_space_char (*s
))
9673 r
= (const reg_entry
*) hash_find (reg_hash
, "st(0)");
9678 /* We have "%st(" then garbage. */
9679 return (const reg_entry
*) NULL
;
9683 if (r
== NULL
|| allow_pseudo_reg
)
9686 if (operand_type_all_zero (&r
->reg_type
))
9687 return (const reg_entry
*) NULL
;
9689 if ((r
->reg_type
.bitfield
.reg32
9690 || r
->reg_type
.bitfield
.sreg3
9691 || r
->reg_type
.bitfield
.control
9692 || r
->reg_type
.bitfield
.debug
9693 || r
->reg_type
.bitfield
.test
)
9694 && !cpu_arch_flags
.bitfield
.cpui386
)
9695 return (const reg_entry
*) NULL
;
9697 if (r
->reg_type
.bitfield
.floatreg
9698 && !cpu_arch_flags
.bitfield
.cpu8087
9699 && !cpu_arch_flags
.bitfield
.cpu287
9700 && !cpu_arch_flags
.bitfield
.cpu387
)
9701 return (const reg_entry
*) NULL
;
9703 if (r
->reg_type
.bitfield
.regmmx
&& !cpu_arch_flags
.bitfield
.cpuregmmx
)
9704 return (const reg_entry
*) NULL
;
9706 if (r
->reg_type
.bitfield
.regxmm
&& !cpu_arch_flags
.bitfield
.cpuregxmm
)
9707 return (const reg_entry
*) NULL
;
9709 if (r
->reg_type
.bitfield
.regymm
&& !cpu_arch_flags
.bitfield
.cpuregymm
)
9710 return (const reg_entry
*) NULL
;
9712 if (r
->reg_type
.bitfield
.regzmm
&& !cpu_arch_flags
.bitfield
.cpuregzmm
)
9713 return (const reg_entry
*) NULL
;
9715 if (r
->reg_type
.bitfield
.regmask
9716 && !cpu_arch_flags
.bitfield
.cpuregmask
)
9717 return (const reg_entry
*) NULL
;
9719 /* Don't allow fake index register unless allow_index_reg isn't 0. */
9720 if (!allow_index_reg
9721 && (r
->reg_num
== RegEiz
|| r
->reg_num
== RegRiz
))
9722 return (const reg_entry
*) NULL
;
9724 /* Upper 16 vector register is only available with VREX in 64bit
9726 if ((r
->reg_flags
& RegVRex
))
9728 if (!cpu_arch_flags
.bitfield
.cpuvrex
9729 || flag_code
!= CODE_64BIT
)
9730 return (const reg_entry
*) NULL
;
9735 if (((r
->reg_flags
& (RegRex64
| RegRex
))
9736 || r
->reg_type
.bitfield
.reg64
)
9737 && (!cpu_arch_flags
.bitfield
.cpulm
9738 || !operand_type_equal (&r
->reg_type
, &control
))
9739 && flag_code
!= CODE_64BIT
)
9740 return (const reg_entry
*) NULL
;
9742 if (r
->reg_type
.bitfield
.sreg3
&& r
->reg_num
== RegFlat
&& !intel_syntax
)
9743 return (const reg_entry
*) NULL
;
9748 /* REG_STRING starts *before* REGISTER_PREFIX. */
9750 static const reg_entry
*
9751 parse_register (char *reg_string
, char **end_op
)
9755 if (*reg_string
== REGISTER_PREFIX
|| allow_naked_reg
)
9756 r
= parse_real_register (reg_string
, end_op
);
9761 char *save
= input_line_pointer
;
9765 input_line_pointer
= reg_string
;
9766 c
= get_symbol_name (®_string
);
9767 symbolP
= symbol_find (reg_string
);
9768 if (symbolP
&& S_GET_SEGMENT (symbolP
) == reg_section
)
9770 const expressionS
*e
= symbol_get_value_expression (symbolP
);
9772 know (e
->X_op
== O_register
);
9773 know (e
->X_add_number
>= 0
9774 && (valueT
) e
->X_add_number
< i386_regtab_size
);
9775 r
= i386_regtab
+ e
->X_add_number
;
9776 if ((r
->reg_flags
& RegVRex
))
9778 *end_op
= input_line_pointer
;
9780 *input_line_pointer
= c
;
9781 input_line_pointer
= save
;
9787 i386_parse_name (char *name
, expressionS
*e
, char *nextcharP
)
9790 char *end
= input_line_pointer
;
9793 r
= parse_register (name
, &input_line_pointer
);
9794 if (r
&& end
<= input_line_pointer
)
9796 *nextcharP
= *input_line_pointer
;
9797 *input_line_pointer
= 0;
9798 e
->X_op
= O_register
;
9799 e
->X_add_number
= r
- i386_regtab
;
9802 input_line_pointer
= end
;
9804 return intel_syntax
? i386_intel_parse_name (name
, e
) : 0;
9808 md_operand (expressionS
*e
)
9813 switch (*input_line_pointer
)
9815 case REGISTER_PREFIX
:
9816 r
= parse_real_register (input_line_pointer
, &end
);
9819 e
->X_op
= O_register
;
9820 e
->X_add_number
= r
- i386_regtab
;
9821 input_line_pointer
= end
;
9826 gas_assert (intel_syntax
);
9827 end
= input_line_pointer
++;
9829 if (*input_line_pointer
== ']')
9831 ++input_line_pointer
;
9832 e
->X_op_symbol
= make_expr_symbol (e
);
9833 e
->X_add_symbol
= NULL
;
9834 e
->X_add_number
= 0;
9840 input_line_pointer
= end
;
9847 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9848 const char *md_shortopts
= "kVQ:sqn";
9850 const char *md_shortopts
= "qn";
9853 #define OPTION_32 (OPTION_MD_BASE + 0)
9854 #define OPTION_64 (OPTION_MD_BASE + 1)
9855 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
9856 #define OPTION_MARCH (OPTION_MD_BASE + 3)
9857 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
9858 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
9859 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
9860 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
9861 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
9862 #define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
9863 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
9864 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
9865 #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
9866 #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
9867 #define OPTION_X32 (OPTION_MD_BASE + 14)
9868 #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
9869 #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
9870 #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
9871 #define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
9872 #define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
9873 #define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
9874 #define OPTION_MSHARED (OPTION_MD_BASE + 21)
9875 #define OPTION_MAMD64 (OPTION_MD_BASE + 22)
9876 #define OPTION_MINTEL64 (OPTION_MD_BASE + 23)
9877 #define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24)
9878 #define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 25)
9880 struct option md_longopts
[] =
9882 {"32", no_argument
, NULL
, OPTION_32
},
9883 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
9884 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
9885 {"64", no_argument
, NULL
, OPTION_64
},
9887 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9888 {"x32", no_argument
, NULL
, OPTION_X32
},
9889 {"mshared", no_argument
, NULL
, OPTION_MSHARED
},
9891 {"divide", no_argument
, NULL
, OPTION_DIVIDE
},
9892 {"march", required_argument
, NULL
, OPTION_MARCH
},
9893 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
9894 {"mmnemonic", required_argument
, NULL
, OPTION_MMNEMONIC
},
9895 {"msyntax", required_argument
, NULL
, OPTION_MSYNTAX
},
9896 {"mindex-reg", no_argument
, NULL
, OPTION_MINDEX_REG
},
9897 {"mnaked-reg", no_argument
, NULL
, OPTION_MNAKED_REG
},
9898 {"mold-gcc", no_argument
, NULL
, OPTION_MOLD_GCC
},
9899 {"msse2avx", no_argument
, NULL
, OPTION_MSSE2AVX
},
9900 {"msse-check", required_argument
, NULL
, OPTION_MSSE_CHECK
},
9901 {"moperand-check", required_argument
, NULL
, OPTION_MOPERAND_CHECK
},
9902 {"mavxscalar", required_argument
, NULL
, OPTION_MAVXSCALAR
},
9903 {"madd-bnd-prefix", no_argument
, NULL
, OPTION_MADD_BND_PREFIX
},
9904 {"mevexlig", required_argument
, NULL
, OPTION_MEVEXLIG
},
9905 {"mevexwig", required_argument
, NULL
, OPTION_MEVEXWIG
},
9906 # if defined (TE_PE) || defined (TE_PEP)
9907 {"mbig-obj", no_argument
, NULL
, OPTION_MBIG_OBJ
},
9909 {"momit-lock-prefix", required_argument
, NULL
, OPTION_MOMIT_LOCK_PREFIX
},
9910 {"mfence-as-lock-add", required_argument
, NULL
, OPTION_MFENCE_AS_LOCK_ADD
},
9911 {"mrelax-relocations", required_argument
, NULL
, OPTION_MRELAX_RELOCATIONS
},
9912 {"mevexrcig", required_argument
, NULL
, OPTION_MEVEXRCIG
},
9913 {"mamd64", no_argument
, NULL
, OPTION_MAMD64
},
9914 {"mintel64", no_argument
, NULL
, OPTION_MINTEL64
},
9915 {NULL
, no_argument
, NULL
, 0}
9917 size_t md_longopts_size
= sizeof (md_longopts
);
9920 md_parse_option (int c
, const char *arg
)
9923 char *arch
, *next
, *saved
;
9928 optimize_align_code
= 0;
9935 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9936 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
9937 should be emitted or not. FIXME: Not implemented. */
9941 /* -V: SVR4 argument to print version ID. */
9943 print_version_id ();
9946 /* -k: Ignore for FreeBSD compatibility. */
9951 /* -s: On i386 Solaris, this tells the native assembler to use
9952 .stab instead of .stab.excl. We always use .stab anyhow. */
9955 case OPTION_MSHARED
:
9959 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
9960 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
9963 const char **list
, **l
;
9965 list
= bfd_target_list ();
9966 for (l
= list
; *l
!= NULL
; l
++)
9967 if (CONST_STRNEQ (*l
, "elf64-x86-64")
9968 || strcmp (*l
, "coff-x86-64") == 0
9969 || strcmp (*l
, "pe-x86-64") == 0
9970 || strcmp (*l
, "pei-x86-64") == 0
9971 || strcmp (*l
, "mach-o-x86-64") == 0)
9973 default_arch
= "x86_64";
9977 as_fatal (_("no compiled in support for x86_64"));
9983 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9987 const char **list
, **l
;
9989 list
= bfd_target_list ();
9990 for (l
= list
; *l
!= NULL
; l
++)
9991 if (CONST_STRNEQ (*l
, "elf32-x86-64"))
9993 default_arch
= "x86_64:32";
9997 as_fatal (_("no compiled in support for 32bit x86_64"));
10001 as_fatal (_("32bit x86_64 is only supported for ELF"));
10006 default_arch
= "i386";
10009 case OPTION_DIVIDE
:
10010 #ifdef SVR4_COMMENT_CHARS
10015 n
= XNEWVEC (char, strlen (i386_comment_chars
) + 1);
10017 for (s
= i386_comment_chars
; *s
!= '\0'; s
++)
10021 i386_comment_chars
= n
;
10027 saved
= xstrdup (arg
);
10029 /* Allow -march=+nosse. */
10035 as_fatal (_("invalid -march= option: `%s'"), arg
);
10036 next
= strchr (arch
, '+');
10039 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
10041 if (strcmp (arch
, cpu_arch
[j
].name
) == 0)
10044 if (! cpu_arch
[j
].flags
.bitfield
.cpui386
)
10047 cpu_arch_name
= cpu_arch
[j
].name
;
10048 cpu_sub_arch_name
= NULL
;
10049 cpu_arch_flags
= cpu_arch
[j
].flags
;
10050 cpu_arch_isa
= cpu_arch
[j
].type
;
10051 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
10052 if (!cpu_arch_tune_set
)
10054 cpu_arch_tune
= cpu_arch_isa
;
10055 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
10059 else if (*cpu_arch
[j
].name
== '.'
10060 && strcmp (arch
, cpu_arch
[j
].name
+ 1) == 0)
10062 /* ISA extension. */
10063 i386_cpu_flags flags
;
10065 flags
= cpu_flags_or (cpu_arch_flags
,
10066 cpu_arch
[j
].flags
);
10068 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
10070 if (cpu_sub_arch_name
)
10072 char *name
= cpu_sub_arch_name
;
10073 cpu_sub_arch_name
= concat (name
,
10075 (const char *) NULL
);
10079 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
10080 cpu_arch_flags
= flags
;
10081 cpu_arch_isa_flags
= flags
;
10087 if (j
>= ARRAY_SIZE (cpu_arch
))
10089 /* Disable an ISA extension. */
10090 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
10091 if (strcmp (arch
, cpu_noarch
[j
].name
) == 0)
10093 i386_cpu_flags flags
;
10095 flags
= cpu_flags_and_not (cpu_arch_flags
,
10096 cpu_noarch
[j
].flags
);
10097 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
10099 if (cpu_sub_arch_name
)
10101 char *name
= cpu_sub_arch_name
;
10102 cpu_sub_arch_name
= concat (arch
,
10103 (const char *) NULL
);
10107 cpu_sub_arch_name
= xstrdup (arch
);
10108 cpu_arch_flags
= flags
;
10109 cpu_arch_isa_flags
= flags
;
10114 if (j
>= ARRAY_SIZE (cpu_noarch
))
10115 j
= ARRAY_SIZE (cpu_arch
);
10118 if (j
>= ARRAY_SIZE (cpu_arch
))
10119 as_fatal (_("invalid -march= option: `%s'"), arg
);
10123 while (next
!= NULL
);
10129 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
10130 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
10132 if (strcmp (arg
, cpu_arch
[j
].name
) == 0)
10134 cpu_arch_tune_set
= 1;
10135 cpu_arch_tune
= cpu_arch
[j
].type
;
10136 cpu_arch_tune_flags
= cpu_arch
[j
].flags
;
10140 if (j
>= ARRAY_SIZE (cpu_arch
))
10141 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
10144 case OPTION_MMNEMONIC
:
10145 if (strcasecmp (arg
, "att") == 0)
10146 intel_mnemonic
= 0;
10147 else if (strcasecmp (arg
, "intel") == 0)
10148 intel_mnemonic
= 1;
10150 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg
);
10153 case OPTION_MSYNTAX
:
10154 if (strcasecmp (arg
, "att") == 0)
10156 else if (strcasecmp (arg
, "intel") == 0)
10159 as_fatal (_("invalid -msyntax= option: `%s'"), arg
);
10162 case OPTION_MINDEX_REG
:
10163 allow_index_reg
= 1;
10166 case OPTION_MNAKED_REG
:
10167 allow_naked_reg
= 1;
10170 case OPTION_MOLD_GCC
:
10174 case OPTION_MSSE2AVX
:
10178 case OPTION_MSSE_CHECK
:
10179 if (strcasecmp (arg
, "error") == 0)
10180 sse_check
= check_error
;
10181 else if (strcasecmp (arg
, "warning") == 0)
10182 sse_check
= check_warning
;
10183 else if (strcasecmp (arg
, "none") == 0)
10184 sse_check
= check_none
;
10186 as_fatal (_("invalid -msse-check= option: `%s'"), arg
);
10189 case OPTION_MOPERAND_CHECK
:
10190 if (strcasecmp (arg
, "error") == 0)
10191 operand_check
= check_error
;
10192 else if (strcasecmp (arg
, "warning") == 0)
10193 operand_check
= check_warning
;
10194 else if (strcasecmp (arg
, "none") == 0)
10195 operand_check
= check_none
;
10197 as_fatal (_("invalid -moperand-check= option: `%s'"), arg
);
10200 case OPTION_MAVXSCALAR
:
10201 if (strcasecmp (arg
, "128") == 0)
10202 avxscalar
= vex128
;
10203 else if (strcasecmp (arg
, "256") == 0)
10204 avxscalar
= vex256
;
10206 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg
);
10209 case OPTION_MADD_BND_PREFIX
:
10210 add_bnd_prefix
= 1;
10213 case OPTION_MEVEXLIG
:
10214 if (strcmp (arg
, "128") == 0)
10215 evexlig
= evexl128
;
10216 else if (strcmp (arg
, "256") == 0)
10217 evexlig
= evexl256
;
10218 else if (strcmp (arg
, "512") == 0)
10219 evexlig
= evexl512
;
10221 as_fatal (_("invalid -mevexlig= option: `%s'"), arg
);
10224 case OPTION_MEVEXRCIG
:
10225 if (strcmp (arg
, "rne") == 0)
10227 else if (strcmp (arg
, "rd") == 0)
10229 else if (strcmp (arg
, "ru") == 0)
10231 else if (strcmp (arg
, "rz") == 0)
10234 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg
);
10237 case OPTION_MEVEXWIG
:
10238 if (strcmp (arg
, "0") == 0)
10240 else if (strcmp (arg
, "1") == 0)
10243 as_fatal (_("invalid -mevexwig= option: `%s'"), arg
);
10246 # if defined (TE_PE) || defined (TE_PEP)
10247 case OPTION_MBIG_OBJ
:
10252 case OPTION_MOMIT_LOCK_PREFIX
:
10253 if (strcasecmp (arg
, "yes") == 0)
10254 omit_lock_prefix
= 1;
10255 else if (strcasecmp (arg
, "no") == 0)
10256 omit_lock_prefix
= 0;
10258 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg
);
10261 case OPTION_MFENCE_AS_LOCK_ADD
:
10262 if (strcasecmp (arg
, "yes") == 0)
10264 else if (strcasecmp (arg
, "no") == 0)
10267 as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg
);
10270 case OPTION_MRELAX_RELOCATIONS
:
10271 if (strcasecmp (arg
, "yes") == 0)
10272 generate_relax_relocations
= 1;
10273 else if (strcasecmp (arg
, "no") == 0)
10274 generate_relax_relocations
= 0;
10276 as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg
);
10279 case OPTION_MAMD64
:
10283 case OPTION_MINTEL64
:
10293 #define MESSAGE_TEMPLATE \
10297 output_message (FILE *stream
, char *p
, char *message
, char *start
,
10298 int *left_p
, const char *name
, int len
)
10300 int size
= sizeof (MESSAGE_TEMPLATE
);
10301 int left
= *left_p
;
10303 /* Reserve 2 spaces for ", " or ",\0" */
10306 /* Check if there is any room. */
10314 p
= mempcpy (p
, name
, len
);
10318 /* Output the current message now and start a new one. */
10321 fprintf (stream
, "%s\n", message
);
10323 left
= size
- (start
- message
) - len
- 2;
10325 gas_assert (left
>= 0);
10327 p
= mempcpy (p
, name
, len
);
10335 show_arch (FILE *stream
, int ext
, int check
)
10337 static char message
[] = MESSAGE_TEMPLATE
;
10338 char *start
= message
+ 27;
10340 int size
= sizeof (MESSAGE_TEMPLATE
);
10347 left
= size
- (start
- message
);
10348 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
10350 /* Should it be skipped? */
10351 if (cpu_arch
[j
].skip
)
10354 name
= cpu_arch
[j
].name
;
10355 len
= cpu_arch
[j
].len
;
10358 /* It is an extension. Skip if we aren't asked to show it. */
10369 /* It is an processor. Skip if we show only extension. */
10372 else if (check
&& ! cpu_arch
[j
].flags
.bitfield
.cpui386
)
10374 /* It is an impossible processor - skip. */
10378 p
= output_message (stream
, p
, message
, start
, &left
, name
, len
);
10381 /* Display disabled extensions. */
10383 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
10385 name
= cpu_noarch
[j
].name
;
10386 len
= cpu_noarch
[j
].len
;
10387 p
= output_message (stream
, p
, message
, start
, &left
, name
,
10392 fprintf (stream
, "%s\n", message
);
10396 md_show_usage (FILE *stream
)
10398 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10399 fprintf (stream
, _("\
10401 -V print assembler version number\n\
10404 fprintf (stream
, _("\
10405 -n Do not optimize code alignment\n\
10406 -q quieten some warnings\n"));
10407 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10408 fprintf (stream
, _("\
10411 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10412 || defined (TE_PE) || defined (TE_PEP))
10413 fprintf (stream
, _("\
10414 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
10416 #ifdef SVR4_COMMENT_CHARS
10417 fprintf (stream
, _("\
10418 --divide do not treat `/' as a comment character\n"));
10420 fprintf (stream
, _("\
10421 --divide ignored\n"));
10423 fprintf (stream
, _("\
10424 -march=CPU[,+EXTENSION...]\n\
10425 generate code for CPU and EXTENSION, CPU is one of:\n"));
10426 show_arch (stream
, 0, 1);
10427 fprintf (stream
, _("\
10428 EXTENSION is combination of:\n"));
10429 show_arch (stream
, 1, 0);
10430 fprintf (stream
, _("\
10431 -mtune=CPU optimize for CPU, CPU is one of:\n"));
10432 show_arch (stream
, 0, 0);
10433 fprintf (stream
, _("\
10434 -msse2avx encode SSE instructions with VEX prefix\n"));
10435 fprintf (stream
, _("\
10436 -msse-check=[none|error|warning]\n\
10437 check SSE instructions\n"));
10438 fprintf (stream
, _("\
10439 -moperand-check=[none|error|warning]\n\
10440 check operand combinations for validity\n"));
10441 fprintf (stream
, _("\
10442 -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n\
10444 fprintf (stream
, _("\
10445 -mevexlig=[128|256|512] encode scalar EVEX instructions with specific vector\n\
10447 fprintf (stream
, _("\
10448 -mevexwig=[0|1] encode EVEX instructions with specific EVEX.W value\n\
10449 for EVEX.W bit ignored instructions\n"));
10450 fprintf (stream
, _("\
10451 -mevexrcig=[rne|rd|ru|rz]\n\
10452 encode EVEX instructions with specific EVEX.RC value\n\
10453 for SAE-only ignored instructions\n"));
10454 fprintf (stream
, _("\
10455 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
10456 fprintf (stream
, _("\
10457 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
10458 fprintf (stream
, _("\
10459 -mindex-reg support pseudo index registers\n"));
10460 fprintf (stream
, _("\
10461 -mnaked-reg don't require `%%' prefix for registers\n"));
10462 fprintf (stream
, _("\
10463 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
10464 fprintf (stream
, _("\
10465 -madd-bnd-prefix add BND prefix for all valid branches\n"));
10466 fprintf (stream
, _("\
10467 -mshared disable branch optimization for shared code\n"));
10468 # if defined (TE_PE) || defined (TE_PEP)
10469 fprintf (stream
, _("\
10470 -mbig-obj generate big object files\n"));
10472 fprintf (stream
, _("\
10473 -momit-lock-prefix=[no|yes]\n\
10474 strip all lock prefixes\n"));
10475 fprintf (stream
, _("\
10476 -mfence-as-lock-add=[no|yes]\n\
10477 encode lfence, mfence and sfence as\n\
10478 lock addl $0x0, (%%{re}sp)\n"));
10479 fprintf (stream
, _("\
10480 -mrelax-relocations=[no|yes]\n\
10481 generate relax relocations\n"));
10482 fprintf (stream
, _("\
10483 -mamd64 accept only AMD64 ISA\n"));
10484 fprintf (stream
, _("\
10485 -mintel64 accept only Intel64 ISA\n"));
10488 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
10489 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10490 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
10492 /* Pick the target format to use. */
10495 i386_target_format (void)
10497 if (!strncmp (default_arch
, "x86_64", 6))
10499 update_code_flag (CODE_64BIT
, 1);
10500 if (default_arch
[6] == '\0')
10501 x86_elf_abi
= X86_64_ABI
;
10503 x86_elf_abi
= X86_64_X32_ABI
;
10505 else if (!strcmp (default_arch
, "i386"))
10506 update_code_flag (CODE_32BIT
, 1);
10507 else if (!strcmp (default_arch
, "iamcu"))
10509 update_code_flag (CODE_32BIT
, 1);
10510 if (cpu_arch_isa
== PROCESSOR_UNKNOWN
)
10512 static const i386_cpu_flags iamcu_flags
= CPU_IAMCU_FLAGS
;
10513 cpu_arch_name
= "iamcu";
10514 cpu_sub_arch_name
= NULL
;
10515 cpu_arch_flags
= iamcu_flags
;
10516 cpu_arch_isa
= PROCESSOR_IAMCU
;
10517 cpu_arch_isa_flags
= iamcu_flags
;
10518 if (!cpu_arch_tune_set
)
10520 cpu_arch_tune
= cpu_arch_isa
;
10521 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
10524 else if (cpu_arch_isa
!= PROCESSOR_IAMCU
)
10525 as_fatal (_("Intel MCU doesn't support `%s' architecture"),
10529 as_fatal (_("unknown architecture"));
10531 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
10532 cpu_arch_isa_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
10533 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
10534 cpu_arch_tune_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
10536 switch (OUTPUT_FLAVOR
)
10538 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
10539 case bfd_target_aout_flavour
:
10540 return AOUT_TARGET_FORMAT
;
10542 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
10543 # if defined (TE_PE) || defined (TE_PEP)
10544 case bfd_target_coff_flavour
:
10545 if (flag_code
== CODE_64BIT
)
10546 return use_big_obj
? "pe-bigobj-x86-64" : "pe-x86-64";
10549 # elif defined (TE_GO32)
10550 case bfd_target_coff_flavour
:
10551 return "coff-go32";
10553 case bfd_target_coff_flavour
:
10554 return "coff-i386";
10557 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
10558 case bfd_target_elf_flavour
:
10560 const char *format
;
10562 switch (x86_elf_abi
)
10565 format
= ELF_TARGET_FORMAT
;
10568 use_rela_relocations
= 1;
10570 format
= ELF_TARGET_FORMAT64
;
10572 case X86_64_X32_ABI
:
10573 use_rela_relocations
= 1;
10575 disallow_64bit_reloc
= 1;
10576 format
= ELF_TARGET_FORMAT32
;
10579 if (cpu_arch_isa
== PROCESSOR_L1OM
)
10581 if (x86_elf_abi
!= X86_64_ABI
)
10582 as_fatal (_("Intel L1OM is 64bit only"));
10583 return ELF_TARGET_L1OM_FORMAT
;
10585 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
10587 if (x86_elf_abi
!= X86_64_ABI
)
10588 as_fatal (_("Intel K1OM is 64bit only"));
10589 return ELF_TARGET_K1OM_FORMAT
;
10591 else if (cpu_arch_isa
== PROCESSOR_IAMCU
)
10593 if (x86_elf_abi
!= I386_ABI
)
10594 as_fatal (_("Intel MCU is 32bit only"));
10595 return ELF_TARGET_IAMCU_FORMAT
;
10601 #if defined (OBJ_MACH_O)
10602 case bfd_target_mach_o_flavour
:
10603 if (flag_code
== CODE_64BIT
)
10605 use_rela_relocations
= 1;
10607 return "mach-o-x86-64";
10610 return "mach-o-i386";
10618 #endif /* OBJ_MAYBE_ more than one */
10621 md_undefined_symbol (char *name
)
10623 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
10624 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
10625 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
10626 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
10630 if (symbol_find (name
))
10631 as_bad (_("GOT already in symbol table"));
10632 GOT_symbol
= symbol_new (name
, undefined_section
,
10633 (valueT
) 0, &zero_address_frag
);
10640 /* Round up a section size to the appropriate boundary. */
10643 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
10645 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
10646 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
10648 /* For a.out, force the section size to be aligned. If we don't do
10649 this, BFD will align it for us, but it will not write out the
10650 final bytes of the section. This may be a bug in BFD, but it is
10651 easier to fix it here since that is how the other a.out targets
10655 align
= bfd_get_section_alignment (stdoutput
, segment
);
10656 size
= ((size
+ (1 << align
) - 1) & (-((valueT
) 1 << align
)));
10663 /* On the i386, PC-relative offsets are relative to the start of the
10664 next instruction. That is, the address of the offset, plus its
10665 size, since the offset is always the last part of the insn. */
10668 md_pcrel_from (fixS
*fixP
)
10670 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
10676 s_bss (int ignore ATTRIBUTE_UNUSED
)
10680 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10682 obj_elf_section_change_hook ();
10684 temp
= get_absolute_expression ();
10685 subseg_set (bss_section
, (subsegT
) temp
);
10686 demand_empty_rest_of_line ();
10692 i386_validate_fix (fixS
*fixp
)
10694 if (fixp
->fx_subsy
)
10696 if (fixp
->fx_subsy
== GOT_symbol
)
10698 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
10702 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10703 if (fixp
->fx_tcbit2
)
10704 fixp
->fx_r_type
= (fixp
->fx_tcbit
10705 ? BFD_RELOC_X86_64_REX_GOTPCRELX
10706 : BFD_RELOC_X86_64_GOTPCRELX
);
10709 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
10714 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
10716 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
10718 fixp
->fx_subsy
= 0;
10721 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10722 else if (!object_64bit
)
10724 if (fixp
->fx_r_type
== BFD_RELOC_386_GOT32
10725 && fixp
->fx_tcbit2
)
10726 fixp
->fx_r_type
= BFD_RELOC_386_GOT32X
;
10732 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
10735 bfd_reloc_code_real_type code
;
10737 switch (fixp
->fx_r_type
)
10739 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10740 case BFD_RELOC_SIZE32
:
10741 case BFD_RELOC_SIZE64
:
10742 if (S_IS_DEFINED (fixp
->fx_addsy
)
10743 && !S_IS_EXTERNAL (fixp
->fx_addsy
))
10745 /* Resolve size relocation against local symbol to size of
10746 the symbol plus addend. */
10747 valueT value
= S_GET_SIZE (fixp
->fx_addsy
) + fixp
->fx_offset
;
10748 if (fixp
->fx_r_type
== BFD_RELOC_SIZE32
10749 && !fits_in_unsigned_long (value
))
10750 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10751 _("symbol size computation overflow"));
10752 fixp
->fx_addsy
= NULL
;
10753 fixp
->fx_subsy
= NULL
;
10754 md_apply_fix (fixp
, (valueT
*) &value
, NULL
);
10758 /* Fall through. */
10760 case BFD_RELOC_X86_64_PLT32
:
10761 case BFD_RELOC_X86_64_GOT32
:
10762 case BFD_RELOC_X86_64_GOTPCREL
:
10763 case BFD_RELOC_X86_64_GOTPCRELX
:
10764 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
10765 case BFD_RELOC_386_PLT32
:
10766 case BFD_RELOC_386_GOT32
:
10767 case BFD_RELOC_386_GOT32X
:
10768 case BFD_RELOC_386_GOTOFF
:
10769 case BFD_RELOC_386_GOTPC
:
10770 case BFD_RELOC_386_TLS_GD
:
10771 case BFD_RELOC_386_TLS_LDM
:
10772 case BFD_RELOC_386_TLS_LDO_32
:
10773 case BFD_RELOC_386_TLS_IE_32
:
10774 case BFD_RELOC_386_TLS_IE
:
10775 case BFD_RELOC_386_TLS_GOTIE
:
10776 case BFD_RELOC_386_TLS_LE_32
:
10777 case BFD_RELOC_386_TLS_LE
:
10778 case BFD_RELOC_386_TLS_GOTDESC
:
10779 case BFD_RELOC_386_TLS_DESC_CALL
:
10780 case BFD_RELOC_X86_64_TLSGD
:
10781 case BFD_RELOC_X86_64_TLSLD
:
10782 case BFD_RELOC_X86_64_DTPOFF32
:
10783 case BFD_RELOC_X86_64_DTPOFF64
:
10784 case BFD_RELOC_X86_64_GOTTPOFF
:
10785 case BFD_RELOC_X86_64_TPOFF32
:
10786 case BFD_RELOC_X86_64_TPOFF64
:
10787 case BFD_RELOC_X86_64_GOTOFF64
:
10788 case BFD_RELOC_X86_64_GOTPC32
:
10789 case BFD_RELOC_X86_64_GOT64
:
10790 case BFD_RELOC_X86_64_GOTPCREL64
:
10791 case BFD_RELOC_X86_64_GOTPC64
:
10792 case BFD_RELOC_X86_64_GOTPLT64
:
10793 case BFD_RELOC_X86_64_PLTOFF64
:
10794 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
10795 case BFD_RELOC_X86_64_TLSDESC_CALL
:
10796 case BFD_RELOC_RVA
:
10797 case BFD_RELOC_VTABLE_ENTRY
:
10798 case BFD_RELOC_VTABLE_INHERIT
:
10800 case BFD_RELOC_32_SECREL
:
10802 code
= fixp
->fx_r_type
;
10804 case BFD_RELOC_X86_64_32S
:
10805 if (!fixp
->fx_pcrel
)
10807 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
10808 code
= fixp
->fx_r_type
;
10811 /* Fall through. */
10813 if (fixp
->fx_pcrel
)
10815 switch (fixp
->fx_size
)
10818 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10819 _("can not do %d byte pc-relative relocation"),
10821 code
= BFD_RELOC_32_PCREL
;
10823 case 1: code
= BFD_RELOC_8_PCREL
; break;
10824 case 2: code
= BFD_RELOC_16_PCREL
; break;
10825 case 4: code
= BFD_RELOC_32_PCREL
; break;
10827 case 8: code
= BFD_RELOC_64_PCREL
; break;
10833 switch (fixp
->fx_size
)
10836 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10837 _("can not do %d byte relocation"),
10839 code
= BFD_RELOC_32
;
10841 case 1: code
= BFD_RELOC_8
; break;
10842 case 2: code
= BFD_RELOC_16
; break;
10843 case 4: code
= BFD_RELOC_32
; break;
10845 case 8: code
= BFD_RELOC_64
; break;
10852 if ((code
== BFD_RELOC_32
10853 || code
== BFD_RELOC_32_PCREL
10854 || code
== BFD_RELOC_X86_64_32S
)
10856 && fixp
->fx_addsy
== GOT_symbol
)
10859 code
= BFD_RELOC_386_GOTPC
;
10861 code
= BFD_RELOC_X86_64_GOTPC32
;
10863 if ((code
== BFD_RELOC_64
|| code
== BFD_RELOC_64_PCREL
)
10865 && fixp
->fx_addsy
== GOT_symbol
)
10867 code
= BFD_RELOC_X86_64_GOTPC64
;
10870 rel
= XNEW (arelent
);
10871 rel
->sym_ptr_ptr
= XNEW (asymbol
*);
10872 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
10874 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
10876 if (!use_rela_relocations
)
10878 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
10879 vtable entry to be used in the relocation's section offset. */
10880 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
10881 rel
->address
= fixp
->fx_offset
;
10882 #if defined (OBJ_COFF) && defined (TE_PE)
10883 else if (fixp
->fx_addsy
&& S_IS_WEAK (fixp
->fx_addsy
))
10884 rel
->addend
= fixp
->fx_addnumber
- (S_GET_VALUE (fixp
->fx_addsy
) * 2);
10889 /* Use the rela in 64bit mode. */
10892 if (disallow_64bit_reloc
)
10895 case BFD_RELOC_X86_64_DTPOFF64
:
10896 case BFD_RELOC_X86_64_TPOFF64
:
10897 case BFD_RELOC_64_PCREL
:
10898 case BFD_RELOC_X86_64_GOTOFF64
:
10899 case BFD_RELOC_X86_64_GOT64
:
10900 case BFD_RELOC_X86_64_GOTPCREL64
:
10901 case BFD_RELOC_X86_64_GOTPC64
:
10902 case BFD_RELOC_X86_64_GOTPLT64
:
10903 case BFD_RELOC_X86_64_PLTOFF64
:
10904 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10905 _("cannot represent relocation type %s in x32 mode"),
10906 bfd_get_reloc_code_name (code
));
10912 if (!fixp
->fx_pcrel
)
10913 rel
->addend
= fixp
->fx_offset
;
10917 case BFD_RELOC_X86_64_PLT32
:
10918 case BFD_RELOC_X86_64_GOT32
:
10919 case BFD_RELOC_X86_64_GOTPCREL
:
10920 case BFD_RELOC_X86_64_GOTPCRELX
:
10921 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
10922 case BFD_RELOC_X86_64_TLSGD
:
10923 case BFD_RELOC_X86_64_TLSLD
:
10924 case BFD_RELOC_X86_64_GOTTPOFF
:
10925 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
10926 case BFD_RELOC_X86_64_TLSDESC_CALL
:
10927 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
10930 rel
->addend
= (section
->vma
10932 + fixp
->fx_addnumber
10933 + md_pcrel_from (fixp
));
10938 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
10939 if (rel
->howto
== NULL
)
10941 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10942 _("cannot represent relocation type %s"),
10943 bfd_get_reloc_code_name (code
));
10944 /* Set howto to a garbage value so that we can keep going. */
10945 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
10946 gas_assert (rel
->howto
!= NULL
);
10952 #include "tc-i386-intel.c"
10955 tc_x86_parse_to_dw2regnum (expressionS
*exp
)
10957 int saved_naked_reg
;
10958 char saved_register_dot
;
10960 saved_naked_reg
= allow_naked_reg
;
10961 allow_naked_reg
= 1;
10962 saved_register_dot
= register_chars
['.'];
10963 register_chars
['.'] = '.';
10964 allow_pseudo_reg
= 1;
10965 expression_and_evaluate (exp
);
10966 allow_pseudo_reg
= 0;
10967 register_chars
['.'] = saved_register_dot
;
10968 allow_naked_reg
= saved_naked_reg
;
10970 if (exp
->X_op
== O_register
&& exp
->X_add_number
>= 0)
10972 if ((addressT
) exp
->X_add_number
< i386_regtab_size
)
10974 exp
->X_op
= O_constant
;
10975 exp
->X_add_number
= i386_regtab
[exp
->X_add_number
]
10976 .dw2_regnum
[flag_code
>> 1];
10979 exp
->X_op
= O_illegal
;
10984 tc_x86_frame_initial_instructions (void)
10986 static unsigned int sp_regno
[2];
10988 if (!sp_regno
[flag_code
>> 1])
10990 char *saved_input
= input_line_pointer
;
10991 char sp
[][4] = {"esp", "rsp"};
10994 input_line_pointer
= sp
[flag_code
>> 1];
10995 tc_x86_parse_to_dw2regnum (&exp
);
10996 gas_assert (exp
.X_op
== O_constant
);
10997 sp_regno
[flag_code
>> 1] = exp
.X_add_number
;
10998 input_line_pointer
= saved_input
;
11001 cfi_add_CFA_def_cfa (sp_regno
[flag_code
>> 1], -x86_cie_data_alignment
);
11002 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
11006 x86_dwarf2_addr_size (void)
11008 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
11009 if (x86_elf_abi
== X86_64_X32_ABI
)
11012 return bfd_arch_bits_per_address (stdoutput
) / 8;
11016 i386_elf_section_type (const char *str
, size_t len
)
11018 if (flag_code
== CODE_64BIT
11019 && len
== sizeof ("unwind") - 1
11020 && strncmp (str
, "unwind", 6) == 0)
11021 return SHT_X86_64_UNWIND
;
11028 i386_solaris_fix_up_eh_frame (segT sec
)
11030 if (flag_code
== CODE_64BIT
)
11031 elf_section_type (sec
) = SHT_X86_64_UNWIND
;
11037 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
11041 exp
.X_op
= O_secrel
;
11042 exp
.X_add_symbol
= symbol
;
11043 exp
.X_add_number
= 0;
11044 emit_expr (&exp
, size
);
11048 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11049 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
11052 x86_64_section_letter (int letter
, const char **ptr_msg
)
11054 if (flag_code
== CODE_64BIT
)
11057 return SHF_X86_64_LARGE
;
11059 *ptr_msg
= _("bad .section directive: want a,l,w,x,M,S,G,T in string");
11062 *ptr_msg
= _("bad .section directive: want a,w,x,M,S,G,T in string");
11067 x86_64_section_word (char *str
, size_t len
)
11069 if (len
== 5 && flag_code
== CODE_64BIT
&& CONST_STRNEQ (str
, "large"))
11070 return SHF_X86_64_LARGE
;
11076 handle_large_common (int small ATTRIBUTE_UNUSED
)
11078 if (flag_code
!= CODE_64BIT
)
11080 s_comm_internal (0, elf_common_parse
);
11081 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
11085 static segT lbss_section
;
11086 asection
*saved_com_section_ptr
= elf_com_section_ptr
;
11087 asection
*saved_bss_section
= bss_section
;
11089 if (lbss_section
== NULL
)
11091 flagword applicable
;
11092 segT seg
= now_seg
;
11093 subsegT subseg
= now_subseg
;
11095 /* The .lbss section is for local .largecomm symbols. */
11096 lbss_section
= subseg_new (".lbss", 0);
11097 applicable
= bfd_applicable_section_flags (stdoutput
);
11098 bfd_set_section_flags (stdoutput
, lbss_section
,
11099 applicable
& SEC_ALLOC
);
11100 seg_info (lbss_section
)->bss
= 1;
11102 subseg_set (seg
, subseg
);
11105 elf_com_section_ptr
= &_bfd_elf_large_com_section
;
11106 bss_section
= lbss_section
;
11108 s_comm_internal (0, elf_common_parse
);
11110 elf_com_section_ptr
= saved_com_section_ptr
;
11111 bss_section
= saved_bss_section
;
11114 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */