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Add .nop assembler directive
[deliverable/binutils-gdb.git] / gas / config / tc-i386.c
1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright (C) 1989-2018 Free Software Foundation, Inc.
3
4 This file is part of GAS, the GNU Assembler.
5
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
9 any later version.
10
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
19 02110-1301, USA. */
20
21 /* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
23 x86_64 support by Jan Hubicka (jh@suse.cz)
24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
27
28 #include "as.h"
29 #include "safe-ctype.h"
30 #include "subsegs.h"
31 #include "dwarf2dbg.h"
32 #include "dw2gencfi.h"
33 #include "elf/x86-64.h"
34 #include "opcodes/i386-init.h"
35
36 #ifndef REGISTER_WARNINGS
37 #define REGISTER_WARNINGS 1
38 #endif
39
40 #ifndef INFER_ADDR_PREFIX
41 #define INFER_ADDR_PREFIX 1
42 #endif
43
44 #ifndef DEFAULT_ARCH
45 #define DEFAULT_ARCH "i386"
46 #endif
47
48 #ifndef INLINE
49 #if __GNUC__ >= 2
50 #define INLINE __inline__
51 #else
52 #define INLINE
53 #endif
54 #endif
55
56 /* Prefixes will be emitted in the order defined below.
57 WAIT_PREFIX must be the first prefix since FWAIT is really is an
58 instruction, and so must come before any prefixes.
59 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
60 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
61 #define WAIT_PREFIX 0
62 #define SEG_PREFIX 1
63 #define ADDR_PREFIX 2
64 #define DATA_PREFIX 3
65 #define REP_PREFIX 4
66 #define HLE_PREFIX REP_PREFIX
67 #define BND_PREFIX REP_PREFIX
68 #define LOCK_PREFIX 5
69 #define REX_PREFIX 6 /* must come last. */
70 #define MAX_PREFIXES 7 /* max prefixes per opcode */
71
72 /* we define the syntax here (modulo base,index,scale syntax) */
73 #define REGISTER_PREFIX '%'
74 #define IMMEDIATE_PREFIX '$'
75 #define ABSOLUTE_PREFIX '*'
76
77 /* these are the instruction mnemonic suffixes in AT&T syntax or
78 memory operand size in Intel syntax. */
79 #define WORD_MNEM_SUFFIX 'w'
80 #define BYTE_MNEM_SUFFIX 'b'
81 #define SHORT_MNEM_SUFFIX 's'
82 #define LONG_MNEM_SUFFIX 'l'
83 #define QWORD_MNEM_SUFFIX 'q'
84 #define XMMWORD_MNEM_SUFFIX 'x'
85 #define YMMWORD_MNEM_SUFFIX 'y'
86 #define ZMMWORD_MNEM_SUFFIX 'z'
87 /* Intel Syntax. Use a non-ascii letter since since it never appears
88 in instructions. */
89 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
90
91 #define END_OF_INSN '\0'
92
93 /*
94 'templates' is for grouping together 'template' structures for opcodes
95 of the same name. This is only used for storing the insns in the grand
96 ole hash table of insns.
97 The templates themselves start at START and range up to (but not including)
98 END.
99 */
100 typedef struct
101 {
102 const insn_template *start;
103 const insn_template *end;
104 }
105 templates;
106
107 /* 386 operand encoding bytes: see 386 book for details of this. */
108 typedef struct
109 {
110 unsigned int regmem; /* codes register or memory operand */
111 unsigned int reg; /* codes register operand (or extended opcode) */
112 unsigned int mode; /* how to interpret regmem & reg */
113 }
114 modrm_byte;
115
116 /* x86-64 extension prefix. */
117 typedef int rex_byte;
118
119 /* 386 opcode byte to code indirect addressing. */
120 typedef struct
121 {
122 unsigned base;
123 unsigned index;
124 unsigned scale;
125 }
126 sib_byte;
127
128 /* x86 arch names, types and features */
129 typedef struct
130 {
131 const char *name; /* arch name */
132 unsigned int len; /* arch string length */
133 enum processor_type type; /* arch type */
134 i386_cpu_flags flags; /* cpu feature flags */
135 unsigned int skip; /* show_arch should skip this. */
136 }
137 arch_entry;
138
139 /* Used to turn off indicated flags. */
140 typedef struct
141 {
142 const char *name; /* arch name */
143 unsigned int len; /* arch string length */
144 i386_cpu_flags flags; /* cpu feature flags */
145 }
146 noarch_entry;
147
148 static void update_code_flag (int, int);
149 static void set_code_flag (int);
150 static void set_16bit_gcc_code_flag (int);
151 static void set_intel_syntax (int);
152 static void set_intel_mnemonic (int);
153 static void set_allow_index_reg (int);
154 static void set_check (int);
155 static void set_cpu_arch (int);
156 #ifdef TE_PE
157 static void pe_directive_secrel (int);
158 #endif
159 static void signed_cons (int);
160 static char *output_invalid (int c);
161 static int i386_finalize_immediate (segT, expressionS *, i386_operand_type,
162 const char *);
163 static int i386_finalize_displacement (segT, expressionS *, i386_operand_type,
164 const char *);
165 static int i386_att_operand (char *);
166 static int i386_intel_operand (char *, int);
167 static int i386_intel_simplify (expressionS *);
168 static int i386_intel_parse_name (const char *, expressionS *);
169 static const reg_entry *parse_register (char *, char **);
170 static char *parse_insn (char *, char *);
171 static char *parse_operands (char *, const char *);
172 static void swap_operands (void);
173 static void swap_2_operands (int, int);
174 static void optimize_imm (void);
175 static void optimize_disp (void);
176 static const insn_template *match_template (char);
177 static int check_string (void);
178 static int process_suffix (void);
179 static int check_byte_reg (void);
180 static int check_long_reg (void);
181 static int check_qword_reg (void);
182 static int check_word_reg (void);
183 static int finalize_imm (void);
184 static int process_operands (void);
185 static const seg_entry *build_modrm_byte (void);
186 static void output_insn (void);
187 static void output_imm (fragS *, offsetT);
188 static void output_disp (fragS *, offsetT);
189 #ifndef I386COFF
190 static void s_bss (int);
191 #endif
192 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
193 static void handle_large_common (int small ATTRIBUTE_UNUSED);
194 #endif
195
196 static const char *default_arch = DEFAULT_ARCH;
197
198 /* This struct describes rounding control and SAE in the instruction. */
199 struct RC_Operation
200 {
201 enum rc_type
202 {
203 rne = 0,
204 rd,
205 ru,
206 rz,
207 saeonly
208 } type;
209 int operand;
210 };
211
212 static struct RC_Operation rc_op;
213
214 /* The struct describes masking, applied to OPERAND in the instruction.
215 MASK is a pointer to the corresponding mask register. ZEROING tells
216 whether merging or zeroing mask is used. */
217 struct Mask_Operation
218 {
219 const reg_entry *mask;
220 unsigned int zeroing;
221 /* The operand where this operation is associated. */
222 int operand;
223 };
224
225 static struct Mask_Operation mask_op;
226
227 /* The struct describes broadcasting, applied to OPERAND. FACTOR is
228 broadcast factor. */
229 struct Broadcast_Operation
230 {
231 /* Type of broadcast: no broadcast, {1to8}, or {1to16}. */
232 int type;
233
234 /* Index of broadcasted operand. */
235 int operand;
236 };
237
238 static struct Broadcast_Operation broadcast_op;
239
240 /* VEX prefix. */
241 typedef struct
242 {
243 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
244 unsigned char bytes[4];
245 unsigned int length;
246 /* Destination or source register specifier. */
247 const reg_entry *register_specifier;
248 } vex_prefix;
249
250 /* 'md_assemble ()' gathers together information and puts it into a
251 i386_insn. */
252
253 union i386_op
254 {
255 expressionS *disps;
256 expressionS *imms;
257 const reg_entry *regs;
258 };
259
260 enum i386_error
261 {
262 operand_size_mismatch,
263 operand_type_mismatch,
264 register_type_mismatch,
265 number_of_operands_mismatch,
266 invalid_instruction_suffix,
267 bad_imm4,
268 old_gcc_only,
269 unsupported_with_intel_mnemonic,
270 unsupported_syntax,
271 unsupported,
272 invalid_vsib_address,
273 invalid_vector_register_set,
274 unsupported_vector_index_register,
275 unsupported_broadcast,
276 broadcast_not_on_src_operand,
277 broadcast_needed,
278 unsupported_masking,
279 mask_not_on_destination,
280 no_default_mask,
281 unsupported_rc_sae,
282 rc_sae_operand_not_last_imm,
283 invalid_register_operand,
284 };
285
286 struct _i386_insn
287 {
288 /* TM holds the template for the insn were currently assembling. */
289 insn_template tm;
290
291 /* SUFFIX holds the instruction size suffix for byte, word, dword
292 or qword, if given. */
293 char suffix;
294
295 /* OPERANDS gives the number of given operands. */
296 unsigned int operands;
297
298 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
299 of given register, displacement, memory operands and immediate
300 operands. */
301 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
302
303 /* TYPES [i] is the type (see above #defines) which tells us how to
304 use OP[i] for the corresponding operand. */
305 i386_operand_type types[MAX_OPERANDS];
306
307 /* Displacement expression, immediate expression, or register for each
308 operand. */
309 union i386_op op[MAX_OPERANDS];
310
311 /* Flags for operands. */
312 unsigned int flags[MAX_OPERANDS];
313 #define Operand_PCrel 1
314
315 /* Relocation type for operand */
316 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
317
318 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
319 the base index byte below. */
320 const reg_entry *base_reg;
321 const reg_entry *index_reg;
322 unsigned int log2_scale_factor;
323
324 /* SEG gives the seg_entries of this insn. They are zero unless
325 explicit segment overrides are given. */
326 const seg_entry *seg[2];
327
328 /* Copied first memory operand string, for re-checking. */
329 char *memop1_string;
330
331 /* PREFIX holds all the given prefix opcodes (usually null).
332 PREFIXES is the number of prefix opcodes. */
333 unsigned int prefixes;
334 unsigned char prefix[MAX_PREFIXES];
335
336 /* RM and SIB are the modrm byte and the sib byte where the
337 addressing modes of this insn are encoded. */
338 modrm_byte rm;
339 rex_byte rex;
340 rex_byte vrex;
341 sib_byte sib;
342 vex_prefix vex;
343
344 /* Masking attributes. */
345 struct Mask_Operation *mask;
346
347 /* Rounding control and SAE attributes. */
348 struct RC_Operation *rounding;
349
350 /* Broadcasting attributes. */
351 struct Broadcast_Operation *broadcast;
352
353 /* Compressed disp8*N attribute. */
354 unsigned int memshift;
355
356 /* Prefer load or store in encoding. */
357 enum
358 {
359 dir_encoding_default = 0,
360 dir_encoding_load,
361 dir_encoding_store
362 } dir_encoding;
363
364 /* Prefer 8bit or 32bit displacement in encoding. */
365 enum
366 {
367 disp_encoding_default = 0,
368 disp_encoding_8bit,
369 disp_encoding_32bit
370 } disp_encoding;
371
372 /* How to encode vector instructions. */
373 enum
374 {
375 vex_encoding_default = 0,
376 vex_encoding_vex2,
377 vex_encoding_vex3,
378 vex_encoding_evex
379 } vec_encoding;
380
381 /* REP prefix. */
382 const char *rep_prefix;
383
384 /* HLE prefix. */
385 const char *hle_prefix;
386
387 /* Have BND prefix. */
388 const char *bnd_prefix;
389
390 /* Have NOTRACK prefix. */
391 const char *notrack_prefix;
392
393 /* Error message. */
394 enum i386_error error;
395 };
396
397 typedef struct _i386_insn i386_insn;
398
399 /* Link RC type with corresponding string, that'll be looked for in
400 asm. */
401 struct RC_name
402 {
403 enum rc_type type;
404 const char *name;
405 unsigned int len;
406 };
407
408 static const struct RC_name RC_NamesTable[] =
409 {
410 { rne, STRING_COMMA_LEN ("rn-sae") },
411 { rd, STRING_COMMA_LEN ("rd-sae") },
412 { ru, STRING_COMMA_LEN ("ru-sae") },
413 { rz, STRING_COMMA_LEN ("rz-sae") },
414 { saeonly, STRING_COMMA_LEN ("sae") },
415 };
416
417 /* List of chars besides those in app.c:symbol_chars that can start an
418 operand. Used to prevent the scrubber eating vital white-space. */
419 const char extra_symbol_chars[] = "*%-([{}"
420 #ifdef LEX_AT
421 "@"
422 #endif
423 #ifdef LEX_QM
424 "?"
425 #endif
426 ;
427
428 #if (defined (TE_I386AIX) \
429 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
430 && !defined (TE_GNU) \
431 && !defined (TE_LINUX) \
432 && !defined (TE_NACL) \
433 && !defined (TE_NETWARE) \
434 && !defined (TE_FreeBSD) \
435 && !defined (TE_DragonFly) \
436 && !defined (TE_NetBSD)))
437 /* This array holds the chars that always start a comment. If the
438 pre-processor is disabled, these aren't very useful. The option
439 --divide will remove '/' from this list. */
440 const char *i386_comment_chars = "#/";
441 #define SVR4_COMMENT_CHARS 1
442 #define PREFIX_SEPARATOR '\\'
443
444 #else
445 const char *i386_comment_chars = "#";
446 #define PREFIX_SEPARATOR '/'
447 #endif
448
449 /* This array holds the chars that only start a comment at the beginning of
450 a line. If the line seems to have the form '# 123 filename'
451 .line and .file directives will appear in the pre-processed output.
452 Note that input_file.c hand checks for '#' at the beginning of the
453 first line of the input file. This is because the compiler outputs
454 #NO_APP at the beginning of its output.
455 Also note that comments started like this one will always work if
456 '/' isn't otherwise defined. */
457 const char line_comment_chars[] = "#/";
458
459 const char line_separator_chars[] = ";";
460
461 /* Chars that can be used to separate mant from exp in floating point
462 nums. */
463 const char EXP_CHARS[] = "eE";
464
465 /* Chars that mean this number is a floating point constant
466 As in 0f12.456
467 or 0d1.2345e12. */
468 const char FLT_CHARS[] = "fFdDxX";
469
470 /* Tables for lexical analysis. */
471 static char mnemonic_chars[256];
472 static char register_chars[256];
473 static char operand_chars[256];
474 static char identifier_chars[256];
475 static char digit_chars[256];
476
477 /* Lexical macros. */
478 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
479 #define is_operand_char(x) (operand_chars[(unsigned char) x])
480 #define is_register_char(x) (register_chars[(unsigned char) x])
481 #define is_space_char(x) ((x) == ' ')
482 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
483 #define is_digit_char(x) (digit_chars[(unsigned char) x])
484
485 /* All non-digit non-letter characters that may occur in an operand. */
486 static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
487
488 /* md_assemble() always leaves the strings it's passed unaltered. To
489 effect this we maintain a stack of saved characters that we've smashed
490 with '\0's (indicating end of strings for various sub-fields of the
491 assembler instruction). */
492 static char save_stack[32];
493 static char *save_stack_p;
494 #define END_STRING_AND_SAVE(s) \
495 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
496 #define RESTORE_END_STRING(s) \
497 do { *(s) = *--save_stack_p; } while (0)
498
499 /* The instruction we're assembling. */
500 static i386_insn i;
501
502 /* Possible templates for current insn. */
503 static const templates *current_templates;
504
505 /* Per instruction expressionS buffers: max displacements & immediates. */
506 static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
507 static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
508
509 /* Current operand we are working on. */
510 static int this_operand = -1;
511
512 /* We support four different modes. FLAG_CODE variable is used to distinguish
513 these. */
514
515 enum flag_code {
516 CODE_32BIT,
517 CODE_16BIT,
518 CODE_64BIT };
519
520 static enum flag_code flag_code;
521 static unsigned int object_64bit;
522 static unsigned int disallow_64bit_reloc;
523 static int use_rela_relocations = 0;
524
525 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
526 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
527 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
528
529 /* The ELF ABI to use. */
530 enum x86_elf_abi
531 {
532 I386_ABI,
533 X86_64_ABI,
534 X86_64_X32_ABI
535 };
536
537 static enum x86_elf_abi x86_elf_abi = I386_ABI;
538 #endif
539
540 #if defined (TE_PE) || defined (TE_PEP)
541 /* Use big object file format. */
542 static int use_big_obj = 0;
543 #endif
544
545 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
546 /* 1 if generating code for a shared library. */
547 static int shared = 0;
548 #endif
549
550 /* 1 for intel syntax,
551 0 if att syntax. */
552 static int intel_syntax = 0;
553
554 /* 1 for Intel64 ISA,
555 0 if AMD64 ISA. */
556 static int intel64;
557
558 /* 1 for intel mnemonic,
559 0 if att mnemonic. */
560 static int intel_mnemonic = !SYSV386_COMPAT;
561
562 /* 1 if support old (<= 2.8.1) versions of gcc. */
563 static int old_gcc = OLDGCC_COMPAT;
564
565 /* 1 if pseudo registers are permitted. */
566 static int allow_pseudo_reg = 0;
567
568 /* 1 if register prefix % not required. */
569 static int allow_naked_reg = 0;
570
571 /* 1 if the assembler should add BND prefix for all control-transferring
572 instructions supporting it, even if this prefix wasn't specified
573 explicitly. */
574 static int add_bnd_prefix = 0;
575
576 /* 1 if pseudo index register, eiz/riz, is allowed . */
577 static int allow_index_reg = 0;
578
579 /* 1 if the assembler should ignore LOCK prefix, even if it was
580 specified explicitly. */
581 static int omit_lock_prefix = 0;
582
583 /* 1 if the assembler should encode lfence, mfence, and sfence as
584 "lock addl $0, (%{re}sp)". */
585 static int avoid_fence = 0;
586
587 /* 1 if the assembler should generate relax relocations. */
588
589 static int generate_relax_relocations
590 = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS;
591
592 static enum check_kind
593 {
594 check_none = 0,
595 check_warning,
596 check_error
597 }
598 sse_check, operand_check = check_warning;
599
600 /* Register prefix used for error message. */
601 static const char *register_prefix = "%";
602
603 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
604 leave, push, and pop instructions so that gcc has the same stack
605 frame as in 32 bit mode. */
606 static char stackop_size = '\0';
607
608 /* Non-zero to optimize code alignment. */
609 int optimize_align_code = 1;
610
611 /* Non-zero to quieten some warnings. */
612 static int quiet_warnings = 0;
613
614 /* CPU name. */
615 static const char *cpu_arch_name = NULL;
616 static char *cpu_sub_arch_name = NULL;
617
618 /* CPU feature flags. */
619 static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS;
620
621 /* If we have selected a cpu we are generating instructions for. */
622 static int cpu_arch_tune_set = 0;
623
624 /* Cpu we are generating instructions for. */
625 enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
626
627 /* CPU feature flags of cpu we are generating instructions for. */
628 static i386_cpu_flags cpu_arch_tune_flags;
629
630 /* CPU instruction set architecture used. */
631 enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
632
633 /* CPU feature flags of instruction set architecture used. */
634 i386_cpu_flags cpu_arch_isa_flags;
635
636 /* If set, conditional jumps are not automatically promoted to handle
637 larger than a byte offset. */
638 static unsigned int no_cond_jump_promotion = 0;
639
640 /* Encode SSE instructions with VEX prefix. */
641 static unsigned int sse2avx;
642
643 /* Encode scalar AVX instructions with specific vector length. */
644 static enum
645 {
646 vex128 = 0,
647 vex256
648 } avxscalar;
649
650 /* Encode scalar EVEX LIG instructions with specific vector length. */
651 static enum
652 {
653 evexl128 = 0,
654 evexl256,
655 evexl512
656 } evexlig;
657
658 /* Encode EVEX WIG instructions with specific evex.w. */
659 static enum
660 {
661 evexw0 = 0,
662 evexw1
663 } evexwig;
664
665 /* Value to encode in EVEX RC bits, for SAE-only instructions. */
666 static enum rc_type evexrcig = rne;
667
668 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
669 static symbolS *GOT_symbol;
670
671 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
672 unsigned int x86_dwarf2_return_column;
673
674 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
675 int x86_cie_data_alignment;
676
677 /* Interface to relax_segment.
678 There are 3 major relax states for 386 jump insns because the
679 different types of jumps add different sizes to frags when we're
680 figuring out what sort of jump to choose to reach a given label. */
681
682 /* Types. */
683 #define UNCOND_JUMP 0
684 #define COND_JUMP 1
685 #define COND_JUMP86 2
686
687 /* Sizes. */
688 #define CODE16 1
689 #define SMALL 0
690 #define SMALL16 (SMALL | CODE16)
691 #define BIG 2
692 #define BIG16 (BIG | CODE16)
693
694 #ifndef INLINE
695 #ifdef __GNUC__
696 #define INLINE __inline__
697 #else
698 #define INLINE
699 #endif
700 #endif
701
702 #define ENCODE_RELAX_STATE(type, size) \
703 ((relax_substateT) (((type) << 2) | (size)))
704 #define TYPE_FROM_RELAX_STATE(s) \
705 ((s) >> 2)
706 #define DISP_SIZE_FROM_RELAX_STATE(s) \
707 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
708
709 /* This table is used by relax_frag to promote short jumps to long
710 ones where necessary. SMALL (short) jumps may be promoted to BIG
711 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
712 don't allow a short jump in a 32 bit code segment to be promoted to
713 a 16 bit offset jump because it's slower (requires data size
714 prefix), and doesn't work, unless the destination is in the bottom
715 64k of the code segment (The top 16 bits of eip are zeroed). */
716
717 const relax_typeS md_relax_table[] =
718 {
719 /* The fields are:
720 1) most positive reach of this state,
721 2) most negative reach of this state,
722 3) how many bytes this mode will have in the variable part of the frag
723 4) which index into the table to try if we can't fit into this one. */
724
725 /* UNCOND_JUMP states. */
726 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
727 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
728 /* dword jmp adds 4 bytes to frag:
729 0 extra opcode bytes, 4 displacement bytes. */
730 {0, 0, 4, 0},
731 /* word jmp adds 2 byte2 to frag:
732 0 extra opcode bytes, 2 displacement bytes. */
733 {0, 0, 2, 0},
734
735 /* COND_JUMP states. */
736 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
737 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
738 /* dword conditionals adds 5 bytes to frag:
739 1 extra opcode byte, 4 displacement bytes. */
740 {0, 0, 5, 0},
741 /* word conditionals add 3 bytes to frag:
742 1 extra opcode byte, 2 displacement bytes. */
743 {0, 0, 3, 0},
744
745 /* COND_JUMP86 states. */
746 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
747 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
748 /* dword conditionals adds 5 bytes to frag:
749 1 extra opcode byte, 4 displacement bytes. */
750 {0, 0, 5, 0},
751 /* word conditionals add 4 bytes to frag:
752 1 displacement byte and a 3 byte long branch insn. */
753 {0, 0, 4, 0}
754 };
755
756 static const arch_entry cpu_arch[] =
757 {
758 /* Do not replace the first two entries - i386_target_format()
759 relies on them being there in this order. */
760 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32,
761 CPU_GENERIC32_FLAGS, 0 },
762 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64,
763 CPU_GENERIC64_FLAGS, 0 },
764 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN,
765 CPU_NONE_FLAGS, 0 },
766 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN,
767 CPU_I186_FLAGS, 0 },
768 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN,
769 CPU_I286_FLAGS, 0 },
770 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386,
771 CPU_I386_FLAGS, 0 },
772 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486,
773 CPU_I486_FLAGS, 0 },
774 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM,
775 CPU_I586_FLAGS, 0 },
776 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO,
777 CPU_I686_FLAGS, 0 },
778 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM,
779 CPU_I586_FLAGS, 0 },
780 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO,
781 CPU_PENTIUMPRO_FLAGS, 0 },
782 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO,
783 CPU_P2_FLAGS, 0 },
784 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO,
785 CPU_P3_FLAGS, 0 },
786 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4,
787 CPU_P4_FLAGS, 0 },
788 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA,
789 CPU_CORE_FLAGS, 0 },
790 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA,
791 CPU_NOCONA_FLAGS, 0 },
792 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE,
793 CPU_CORE_FLAGS, 1 },
794 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE,
795 CPU_CORE_FLAGS, 0 },
796 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2,
797 CPU_CORE2_FLAGS, 1 },
798 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2,
799 CPU_CORE2_FLAGS, 0 },
800 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7,
801 CPU_COREI7_FLAGS, 0 },
802 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM,
803 CPU_L1OM_FLAGS, 0 },
804 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM,
805 CPU_K1OM_FLAGS, 0 },
806 { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU,
807 CPU_IAMCU_FLAGS, 0 },
808 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6,
809 CPU_K6_FLAGS, 0 },
810 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6,
811 CPU_K6_2_FLAGS, 0 },
812 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON,
813 CPU_ATHLON_FLAGS, 0 },
814 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8,
815 CPU_K8_FLAGS, 1 },
816 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8,
817 CPU_K8_FLAGS, 0 },
818 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8,
819 CPU_K8_FLAGS, 0 },
820 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10,
821 CPU_AMDFAM10_FLAGS, 0 },
822 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD,
823 CPU_BDVER1_FLAGS, 0 },
824 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD,
825 CPU_BDVER2_FLAGS, 0 },
826 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD,
827 CPU_BDVER3_FLAGS, 0 },
828 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD,
829 CPU_BDVER4_FLAGS, 0 },
830 { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER,
831 CPU_ZNVER1_FLAGS, 0 },
832 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT,
833 CPU_BTVER1_FLAGS, 0 },
834 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT,
835 CPU_BTVER2_FLAGS, 0 },
836 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN,
837 CPU_8087_FLAGS, 0 },
838 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN,
839 CPU_287_FLAGS, 0 },
840 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN,
841 CPU_387_FLAGS, 0 },
842 { STRING_COMMA_LEN (".687"), PROCESSOR_UNKNOWN,
843 CPU_687_FLAGS, 0 },
844 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN,
845 CPU_MMX_FLAGS, 0 },
846 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN,
847 CPU_SSE_FLAGS, 0 },
848 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN,
849 CPU_SSE2_FLAGS, 0 },
850 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN,
851 CPU_SSE3_FLAGS, 0 },
852 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN,
853 CPU_SSSE3_FLAGS, 0 },
854 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN,
855 CPU_SSE4_1_FLAGS, 0 },
856 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN,
857 CPU_SSE4_2_FLAGS, 0 },
858 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN,
859 CPU_SSE4_2_FLAGS, 0 },
860 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN,
861 CPU_AVX_FLAGS, 0 },
862 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN,
863 CPU_AVX2_FLAGS, 0 },
864 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN,
865 CPU_AVX512F_FLAGS, 0 },
866 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN,
867 CPU_AVX512CD_FLAGS, 0 },
868 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN,
869 CPU_AVX512ER_FLAGS, 0 },
870 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN,
871 CPU_AVX512PF_FLAGS, 0 },
872 { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN,
873 CPU_AVX512DQ_FLAGS, 0 },
874 { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN,
875 CPU_AVX512BW_FLAGS, 0 },
876 { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN,
877 CPU_AVX512VL_FLAGS, 0 },
878 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN,
879 CPU_VMX_FLAGS, 0 },
880 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN,
881 CPU_VMFUNC_FLAGS, 0 },
882 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN,
883 CPU_SMX_FLAGS, 0 },
884 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN,
885 CPU_XSAVE_FLAGS, 0 },
886 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN,
887 CPU_XSAVEOPT_FLAGS, 0 },
888 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN,
889 CPU_XSAVEC_FLAGS, 0 },
890 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN,
891 CPU_XSAVES_FLAGS, 0 },
892 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN,
893 CPU_AES_FLAGS, 0 },
894 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN,
895 CPU_PCLMUL_FLAGS, 0 },
896 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN,
897 CPU_PCLMUL_FLAGS, 1 },
898 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN,
899 CPU_FSGSBASE_FLAGS, 0 },
900 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN,
901 CPU_RDRND_FLAGS, 0 },
902 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN,
903 CPU_F16C_FLAGS, 0 },
904 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN,
905 CPU_BMI2_FLAGS, 0 },
906 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN,
907 CPU_FMA_FLAGS, 0 },
908 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN,
909 CPU_FMA4_FLAGS, 0 },
910 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN,
911 CPU_XOP_FLAGS, 0 },
912 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN,
913 CPU_LWP_FLAGS, 0 },
914 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN,
915 CPU_MOVBE_FLAGS, 0 },
916 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN,
917 CPU_CX16_FLAGS, 0 },
918 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN,
919 CPU_EPT_FLAGS, 0 },
920 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN,
921 CPU_LZCNT_FLAGS, 0 },
922 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN,
923 CPU_HLE_FLAGS, 0 },
924 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN,
925 CPU_RTM_FLAGS, 0 },
926 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN,
927 CPU_INVPCID_FLAGS, 0 },
928 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN,
929 CPU_CLFLUSH_FLAGS, 0 },
930 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN,
931 CPU_NOP_FLAGS, 0 },
932 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN,
933 CPU_SYSCALL_FLAGS, 0 },
934 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN,
935 CPU_RDTSCP_FLAGS, 0 },
936 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN,
937 CPU_3DNOW_FLAGS, 0 },
938 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN,
939 CPU_3DNOWA_FLAGS, 0 },
940 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN,
941 CPU_PADLOCK_FLAGS, 0 },
942 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN,
943 CPU_SVME_FLAGS, 1 },
944 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN,
945 CPU_SVME_FLAGS, 0 },
946 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN,
947 CPU_SSE4A_FLAGS, 0 },
948 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN,
949 CPU_ABM_FLAGS, 0 },
950 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN,
951 CPU_BMI_FLAGS, 0 },
952 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN,
953 CPU_TBM_FLAGS, 0 },
954 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN,
955 CPU_ADX_FLAGS, 0 },
956 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN,
957 CPU_RDSEED_FLAGS, 0 },
958 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN,
959 CPU_PRFCHW_FLAGS, 0 },
960 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN,
961 CPU_SMAP_FLAGS, 0 },
962 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN,
963 CPU_MPX_FLAGS, 0 },
964 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN,
965 CPU_SHA_FLAGS, 0 },
966 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN,
967 CPU_CLFLUSHOPT_FLAGS, 0 },
968 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN,
969 CPU_PREFETCHWT1_FLAGS, 0 },
970 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN,
971 CPU_SE1_FLAGS, 0 },
972 { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN,
973 CPU_CLWB_FLAGS, 0 },
974 { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN,
975 CPU_AVX512IFMA_FLAGS, 0 },
976 { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN,
977 CPU_AVX512VBMI_FLAGS, 0 },
978 { STRING_COMMA_LEN (".avx512_4fmaps"), PROCESSOR_UNKNOWN,
979 CPU_AVX512_4FMAPS_FLAGS, 0 },
980 { STRING_COMMA_LEN (".avx512_4vnniw"), PROCESSOR_UNKNOWN,
981 CPU_AVX512_4VNNIW_FLAGS, 0 },
982 { STRING_COMMA_LEN (".avx512_vpopcntdq"), PROCESSOR_UNKNOWN,
983 CPU_AVX512_VPOPCNTDQ_FLAGS, 0 },
984 { STRING_COMMA_LEN (".avx512_vbmi2"), PROCESSOR_UNKNOWN,
985 CPU_AVX512_VBMI2_FLAGS, 0 },
986 { STRING_COMMA_LEN (".avx512_vnni"), PROCESSOR_UNKNOWN,
987 CPU_AVX512_VNNI_FLAGS, 0 },
988 { STRING_COMMA_LEN (".avx512_bitalg"), PROCESSOR_UNKNOWN,
989 CPU_AVX512_BITALG_FLAGS, 0 },
990 { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN,
991 CPU_CLZERO_FLAGS, 0 },
992 { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN,
993 CPU_MWAITX_FLAGS, 0 },
994 { STRING_COMMA_LEN (".ospke"), PROCESSOR_UNKNOWN,
995 CPU_OSPKE_FLAGS, 0 },
996 { STRING_COMMA_LEN (".rdpid"), PROCESSOR_UNKNOWN,
997 CPU_RDPID_FLAGS, 0 },
998 { STRING_COMMA_LEN (".ptwrite"), PROCESSOR_UNKNOWN,
999 CPU_PTWRITE_FLAGS, 0 },
1000 { STRING_COMMA_LEN (".ibt"), PROCESSOR_UNKNOWN,
1001 CPU_IBT_FLAGS, 0 },
1002 { STRING_COMMA_LEN (".shstk"), PROCESSOR_UNKNOWN,
1003 CPU_SHSTK_FLAGS, 0 },
1004 { STRING_COMMA_LEN (".gfni"), PROCESSOR_UNKNOWN,
1005 CPU_GFNI_FLAGS, 0 },
1006 { STRING_COMMA_LEN (".vaes"), PROCESSOR_UNKNOWN,
1007 CPU_VAES_FLAGS, 0 },
1008 { STRING_COMMA_LEN (".vpclmulqdq"), PROCESSOR_UNKNOWN,
1009 CPU_VPCLMULQDQ_FLAGS, 0 },
1010 { STRING_COMMA_LEN (".wbnoinvd"), PROCESSOR_UNKNOWN,
1011 CPU_WBNOINVD_FLAGS, 0 },
1012 { STRING_COMMA_LEN (".pconfig"), PROCESSOR_UNKNOWN,
1013 CPU_PCONFIG_FLAGS, 0 },
1014 };
1015
1016 static const noarch_entry cpu_noarch[] =
1017 {
1018 { STRING_COMMA_LEN ("no87"), CPU_ANY_X87_FLAGS },
1019 { STRING_COMMA_LEN ("no287"), CPU_ANY_287_FLAGS },
1020 { STRING_COMMA_LEN ("no387"), CPU_ANY_387_FLAGS },
1021 { STRING_COMMA_LEN ("no687"), CPU_ANY_687_FLAGS },
1022 { STRING_COMMA_LEN ("nommx"), CPU_ANY_MMX_FLAGS },
1023 { STRING_COMMA_LEN ("nosse"), CPU_ANY_SSE_FLAGS },
1024 { STRING_COMMA_LEN ("nosse2"), CPU_ANY_SSE2_FLAGS },
1025 { STRING_COMMA_LEN ("nosse3"), CPU_ANY_SSE3_FLAGS },
1026 { STRING_COMMA_LEN ("nossse3"), CPU_ANY_SSSE3_FLAGS },
1027 { STRING_COMMA_LEN ("nosse4.1"), CPU_ANY_SSE4_1_FLAGS },
1028 { STRING_COMMA_LEN ("nosse4.2"), CPU_ANY_SSE4_2_FLAGS },
1029 { STRING_COMMA_LEN ("nosse4"), CPU_ANY_SSE4_1_FLAGS },
1030 { STRING_COMMA_LEN ("noavx"), CPU_ANY_AVX_FLAGS },
1031 { STRING_COMMA_LEN ("noavx2"), CPU_ANY_AVX2_FLAGS },
1032 { STRING_COMMA_LEN ("noavx512f"), CPU_ANY_AVX512F_FLAGS },
1033 { STRING_COMMA_LEN ("noavx512cd"), CPU_ANY_AVX512CD_FLAGS },
1034 { STRING_COMMA_LEN ("noavx512er"), CPU_ANY_AVX512ER_FLAGS },
1035 { STRING_COMMA_LEN ("noavx512pf"), CPU_ANY_AVX512PF_FLAGS },
1036 { STRING_COMMA_LEN ("noavx512dq"), CPU_ANY_AVX512DQ_FLAGS },
1037 { STRING_COMMA_LEN ("noavx512bw"), CPU_ANY_AVX512BW_FLAGS },
1038 { STRING_COMMA_LEN ("noavx512vl"), CPU_ANY_AVX512VL_FLAGS },
1039 { STRING_COMMA_LEN ("noavx512ifma"), CPU_ANY_AVX512IFMA_FLAGS },
1040 { STRING_COMMA_LEN ("noavx512vbmi"), CPU_ANY_AVX512VBMI_FLAGS },
1041 { STRING_COMMA_LEN ("noavx512_4fmaps"), CPU_ANY_AVX512_4FMAPS_FLAGS },
1042 { STRING_COMMA_LEN ("noavx512_4vnniw"), CPU_ANY_AVX512_4VNNIW_FLAGS },
1043 { STRING_COMMA_LEN ("noavx512_vpopcntdq"), CPU_ANY_AVX512_VPOPCNTDQ_FLAGS },
1044 { STRING_COMMA_LEN ("noavx512_vbmi2"), CPU_ANY_AVX512_VBMI2_FLAGS },
1045 { STRING_COMMA_LEN ("noavx512_vnni"), CPU_ANY_AVX512_VNNI_FLAGS },
1046 { STRING_COMMA_LEN ("noavx512_bitalg"), CPU_ANY_AVX512_BITALG_FLAGS },
1047 { STRING_COMMA_LEN ("noibt"), CPU_ANY_IBT_FLAGS },
1048 { STRING_COMMA_LEN ("noshstk"), CPU_ANY_SHSTK_FLAGS },
1049 };
1050
1051 #ifdef I386COFF
1052 /* Like s_lcomm_internal in gas/read.c but the alignment string
1053 is allowed to be optional. */
1054
1055 static symbolS *
1056 pe_lcomm_internal (int needs_align, symbolS *symbolP, addressT size)
1057 {
1058 addressT align = 0;
1059
1060 SKIP_WHITESPACE ();
1061
1062 if (needs_align
1063 && *input_line_pointer == ',')
1064 {
1065 align = parse_align (needs_align - 1);
1066
1067 if (align == (addressT) -1)
1068 return NULL;
1069 }
1070 else
1071 {
1072 if (size >= 8)
1073 align = 3;
1074 else if (size >= 4)
1075 align = 2;
1076 else if (size >= 2)
1077 align = 1;
1078 else
1079 align = 0;
1080 }
1081
1082 bss_alloc (symbolP, size, align);
1083 return symbolP;
1084 }
1085
1086 static void
1087 pe_lcomm (int needs_align)
1088 {
1089 s_comm_internal (needs_align * 2, pe_lcomm_internal);
1090 }
1091 #endif
1092
1093 const pseudo_typeS md_pseudo_table[] =
1094 {
1095 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
1096 {"align", s_align_bytes, 0},
1097 #else
1098 {"align", s_align_ptwo, 0},
1099 #endif
1100 {"arch", set_cpu_arch, 0},
1101 #ifndef I386COFF
1102 {"bss", s_bss, 0},
1103 #else
1104 {"lcomm", pe_lcomm, 1},
1105 #endif
1106 {"ffloat", float_cons, 'f'},
1107 {"dfloat", float_cons, 'd'},
1108 {"tfloat", float_cons, 'x'},
1109 {"value", cons, 2},
1110 {"slong", signed_cons, 4},
1111 {"noopt", s_ignore, 0},
1112 {"optim", s_ignore, 0},
1113 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
1114 {"code16", set_code_flag, CODE_16BIT},
1115 {"code32", set_code_flag, CODE_32BIT},
1116 #ifdef BFD64
1117 {"code64", set_code_flag, CODE_64BIT},
1118 #endif
1119 {"intel_syntax", set_intel_syntax, 1},
1120 {"att_syntax", set_intel_syntax, 0},
1121 {"intel_mnemonic", set_intel_mnemonic, 1},
1122 {"att_mnemonic", set_intel_mnemonic, 0},
1123 {"allow_index_reg", set_allow_index_reg, 1},
1124 {"disallow_index_reg", set_allow_index_reg, 0},
1125 {"sse_check", set_check, 0},
1126 {"operand_check", set_check, 1},
1127 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1128 {"largecomm", handle_large_common, 0},
1129 #else
1130 {"file", dwarf2_directive_file, 0},
1131 {"loc", dwarf2_directive_loc, 0},
1132 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
1133 #endif
1134 #ifdef TE_PE
1135 {"secrel32", pe_directive_secrel, 0},
1136 #endif
1137 {0, 0, 0}
1138 };
1139
1140 /* For interface with expression (). */
1141 extern char *input_line_pointer;
1142
1143 /* Hash table for instruction mnemonic lookup. */
1144 static struct hash_control *op_hash;
1145
1146 /* Hash table for register lookup. */
1147 static struct hash_control *reg_hash;
1148 \f
1149 /* Various efficient no-op patterns for aligning code labels.
1150 Note: Don't try to assemble the instructions in the comments.
1151 0L and 0w are not legal. */
1152 static const unsigned char f32_1[] =
1153 {0x90}; /* nop */
1154 static const unsigned char f32_2[] =
1155 {0x66,0x90}; /* xchg %ax,%ax */
1156 static const unsigned char f32_3[] =
1157 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1158 static const unsigned char f32_4[] =
1159 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1160 static const unsigned char f32_5[] =
1161 {0x90, /* nop */
1162 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1163 static const unsigned char f32_6[] =
1164 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1165 static const unsigned char f32_7[] =
1166 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1167 static const unsigned char f32_8[] =
1168 {0x90, /* nop */
1169 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1170 static const unsigned char f32_9[] =
1171 {0x89,0xf6, /* movl %esi,%esi */
1172 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1173 static const unsigned char f32_10[] =
1174 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
1175 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1176 static const unsigned char f32_11[] =
1177 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
1178 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1179 static const unsigned char f32_12[] =
1180 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1181 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
1182 static const unsigned char f32_13[] =
1183 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1184 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1185 static const unsigned char f32_14[] =
1186 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
1187 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1188 static const unsigned char f16_3[] =
1189 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
1190 static const unsigned char f16_4[] =
1191 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
1192 static const unsigned char f16_5[] =
1193 {0x90, /* nop */
1194 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
1195 static const unsigned char f16_6[] =
1196 {0x89,0xf6, /* mov %si,%si */
1197 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1198 static const unsigned char f16_7[] =
1199 {0x8d,0x74,0x00, /* lea 0(%si),%si */
1200 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1201 static const unsigned char f16_8[] =
1202 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
1203 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1204 static const unsigned char jump_31[] =
1205 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
1206 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1207 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1208 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
1209 /* 32-bit NOPs patterns. */
1210 static const unsigned char *const f32_patt[] = {
1211 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
1212 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14
1213 };
1214 /* 16-bit NOPs patterns. */
1215 static const unsigned char *const f16_patt[] = {
1216 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8
1217 };
1218 /* nopl (%[re]ax) */
1219 static const unsigned char alt_3[] =
1220 {0x0f,0x1f,0x00};
1221 /* nopl 0(%[re]ax) */
1222 static const unsigned char alt_4[] =
1223 {0x0f,0x1f,0x40,0x00};
1224 /* nopl 0(%[re]ax,%[re]ax,1) */
1225 static const unsigned char alt_5[] =
1226 {0x0f,0x1f,0x44,0x00,0x00};
1227 /* nopw 0(%[re]ax,%[re]ax,1) */
1228 static const unsigned char alt_6[] =
1229 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1230 /* nopl 0L(%[re]ax) */
1231 static const unsigned char alt_7[] =
1232 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1233 /* nopl 0L(%[re]ax,%[re]ax,1) */
1234 static const unsigned char alt_8[] =
1235 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1236 /* nopw 0L(%[re]ax,%[re]ax,1) */
1237 static const unsigned char alt_9[] =
1238 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1239 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1240 static const unsigned char alt_10[] =
1241 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1242 /* 32-bit and 64-bit NOPs patterns. */
1243 static const unsigned char *const alt_patt[] = {
1244 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
1245 alt_9, alt_10
1246 };
1247 /* 64-bit only: nopw %cs:0L(%eax,%eax,1) */
1248 static const unsigned char alt64_11[] =
1249 {0x67,0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1250 /* 64-bit NOPs patterns. */
1251 static const unsigned char *const alt64_patt[] = {
1252 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
1253 alt_9, alt_10, alt64_11
1254 };
1255
1256 /* Genenerate COUNT bytes of NOPs to WHERE from PATT with the maximum
1257 size of a single NOP instruction MAX_SINGLE_NOP_SIZE. */
1258
1259 static void
1260 i386_output_nops (char *where, const unsigned char *const *patt,
1261 int count, int max_single_nop_size)
1262
1263 {
1264 while (count > max_single_nop_size)
1265 {
1266 count -= max_single_nop_size;
1267 memcpy (where + count, patt[max_single_nop_size - 1],
1268 max_single_nop_size);
1269 }
1270
1271 if (count)
1272 memcpy (where, patt[count - 1], count);
1273 }
1274
1275
1276 /* Genenerate COUNT bytes of NOPs to WHERE with the maximum size of a
1277 single NOP instruction LIMIT. */
1278
1279 void
1280 i386_generate_nops (fragS *f, char *where, offsetT count, int limit)
1281 {
1282 /* Output NOPs for .nop directive. */
1283 int max_single_nop_size;
1284 const unsigned char *const *patt;
1285
1286 if (flag_code == CODE_16BIT)
1287 {
1288 patt = f16_patt;
1289 max_single_nop_size = sizeof (f16_patt) / sizeof (f16_patt[0]);
1290 }
1291 else if (flag_code == CODE_64BIT)
1292 {
1293 patt = alt64_patt;
1294 max_single_nop_size = sizeof (alt64_patt) / sizeof (alt64_patt[0]);
1295 }
1296 else
1297 {
1298 patt = alt_patt;
1299 max_single_nop_size = sizeof (alt_patt) / sizeof (alt_patt[0]);
1300 }
1301 if (limit == 0)
1302 limit = max_single_nop_size;
1303 else if (limit > max_single_nop_size)
1304 {
1305 as_bad_where (f->fr_file, f->fr_line,
1306 _("invalide single nop size: %d (expect within [0, %d])"),
1307 limit, max_single_nop_size);
1308 return;
1309 }
1310
1311 i386_output_nops (where, patt, count, limit);
1312 }
1313
1314 void
1315 i386_align_code (fragS *fragP, int count)
1316 {
1317 /* Only align for at least a positive non-zero boundary. */
1318 if (count <= 0 || count > MAX_MEM_FOR_RS_ALIGN_CODE)
1319 return;
1320
1321 /* We need to decide which NOP sequence to use for 32bit and
1322 64bit. When -mtune= is used:
1323
1324 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1325 PROCESSOR_GENERIC32, f32_patt will be used.
1326 2. For the rest, alt_patt will be used.
1327
1328 When -mtune= isn't used, alt_patt will be used if
1329 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
1330 be used.
1331
1332 When -march= or .arch is used, we can't use anything beyond
1333 cpu_arch_isa_flags. */
1334
1335 if (flag_code == CODE_16BIT)
1336 {
1337 if (count > 8)
1338 {
1339 memcpy (fragP->fr_literal + fragP->fr_fix,
1340 jump_31, count);
1341 /* Adjust jump offset. */
1342 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
1343 }
1344 else
1345 memcpy (fragP->fr_literal + fragP->fr_fix,
1346 f16_patt[count - 1], count);
1347 }
1348 else
1349 {
1350 const unsigned char *const *patt = NULL;
1351
1352 if (fragP->tc_frag_data.isa == PROCESSOR_UNKNOWN)
1353 {
1354 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1355 switch (cpu_arch_tune)
1356 {
1357 case PROCESSOR_UNKNOWN:
1358 /* We use cpu_arch_isa_flags to check if we SHOULD
1359 optimize with nops. */
1360 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
1361 patt = alt_patt;
1362 else
1363 patt = f32_patt;
1364 break;
1365 case PROCESSOR_PENTIUM4:
1366 case PROCESSOR_NOCONA:
1367 case PROCESSOR_CORE:
1368 case PROCESSOR_CORE2:
1369 case PROCESSOR_COREI7:
1370 case PROCESSOR_L1OM:
1371 case PROCESSOR_K1OM:
1372 case PROCESSOR_GENERIC64:
1373 case PROCESSOR_K6:
1374 case PROCESSOR_ATHLON:
1375 case PROCESSOR_K8:
1376 case PROCESSOR_AMDFAM10:
1377 case PROCESSOR_BD:
1378 case PROCESSOR_ZNVER:
1379 case PROCESSOR_BT:
1380 patt = alt_patt;
1381 break;
1382 case PROCESSOR_I386:
1383 case PROCESSOR_I486:
1384 case PROCESSOR_PENTIUM:
1385 case PROCESSOR_PENTIUMPRO:
1386 case PROCESSOR_IAMCU:
1387 case PROCESSOR_GENERIC32:
1388 patt = f32_patt;
1389 break;
1390 }
1391 }
1392 else
1393 {
1394 switch (fragP->tc_frag_data.tune)
1395 {
1396 case PROCESSOR_UNKNOWN:
1397 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1398 PROCESSOR_UNKNOWN. */
1399 abort ();
1400 break;
1401
1402 case PROCESSOR_I386:
1403 case PROCESSOR_I486:
1404 case PROCESSOR_PENTIUM:
1405 case PROCESSOR_IAMCU:
1406 case PROCESSOR_K6:
1407 case PROCESSOR_ATHLON:
1408 case PROCESSOR_K8:
1409 case PROCESSOR_AMDFAM10:
1410 case PROCESSOR_BD:
1411 case PROCESSOR_ZNVER:
1412 case PROCESSOR_BT:
1413 case PROCESSOR_GENERIC32:
1414 /* We use cpu_arch_isa_flags to check if we CAN optimize
1415 with nops. */
1416 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
1417 patt = alt_patt;
1418 else
1419 patt = f32_patt;
1420 break;
1421 case PROCESSOR_PENTIUMPRO:
1422 case PROCESSOR_PENTIUM4:
1423 case PROCESSOR_NOCONA:
1424 case PROCESSOR_CORE:
1425 case PROCESSOR_CORE2:
1426 case PROCESSOR_COREI7:
1427 case PROCESSOR_L1OM:
1428 case PROCESSOR_K1OM:
1429 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
1430 patt = alt_patt;
1431 else
1432 patt = f32_patt;
1433 break;
1434 case PROCESSOR_GENERIC64:
1435 patt = alt_patt;
1436 break;
1437 }
1438 }
1439
1440 if (patt == f32_patt)
1441 {
1442 /* If the padding is less than 15 bytes, we use the normal
1443 ones. Otherwise, we use a jump instruction and adjust
1444 its offset. */
1445 int limit;
1446
1447 /* For 64bit, the limit is 3 bytes. */
1448 if (flag_code == CODE_64BIT
1449 && fragP->tc_frag_data.isa_flags.bitfield.cpulm)
1450 limit = 3;
1451 else
1452 limit = 15;
1453 if (count < limit)
1454 memcpy (fragP->fr_literal + fragP->fr_fix,
1455 patt[count - 1], count);
1456 else
1457 {
1458 memcpy (fragP->fr_literal + fragP->fr_fix,
1459 jump_31, count);
1460 /* Adjust jump offset. */
1461 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
1462 }
1463 }
1464 else
1465 {
1466 /* Maximum length of an instruction is 10 byte. If the
1467 padding is greater than 10 bytes and we don't use jump,
1468 we have to break it into smaller pieces. */
1469 i386_output_nops (fragP->fr_literal + fragP->fr_fix,
1470 patt, count, 10);
1471 }
1472 }
1473 fragP->fr_var = count;
1474 }
1475
1476 static INLINE int
1477 operand_type_all_zero (const union i386_operand_type *x)
1478 {
1479 switch (ARRAY_SIZE(x->array))
1480 {
1481 case 3:
1482 if (x->array[2])
1483 return 0;
1484 /* Fall through. */
1485 case 2:
1486 if (x->array[1])
1487 return 0;
1488 /* Fall through. */
1489 case 1:
1490 return !x->array[0];
1491 default:
1492 abort ();
1493 }
1494 }
1495
1496 static INLINE void
1497 operand_type_set (union i386_operand_type *x, unsigned int v)
1498 {
1499 switch (ARRAY_SIZE(x->array))
1500 {
1501 case 3:
1502 x->array[2] = v;
1503 /* Fall through. */
1504 case 2:
1505 x->array[1] = v;
1506 /* Fall through. */
1507 case 1:
1508 x->array[0] = v;
1509 /* Fall through. */
1510 break;
1511 default:
1512 abort ();
1513 }
1514 }
1515
1516 static INLINE int
1517 operand_type_equal (const union i386_operand_type *x,
1518 const union i386_operand_type *y)
1519 {
1520 switch (ARRAY_SIZE(x->array))
1521 {
1522 case 3:
1523 if (x->array[2] != y->array[2])
1524 return 0;
1525 /* Fall through. */
1526 case 2:
1527 if (x->array[1] != y->array[1])
1528 return 0;
1529 /* Fall through. */
1530 case 1:
1531 return x->array[0] == y->array[0];
1532 break;
1533 default:
1534 abort ();
1535 }
1536 }
1537
1538 static INLINE int
1539 cpu_flags_all_zero (const union i386_cpu_flags *x)
1540 {
1541 switch (ARRAY_SIZE(x->array))
1542 {
1543 case 4:
1544 if (x->array[3])
1545 return 0;
1546 /* Fall through. */
1547 case 3:
1548 if (x->array[2])
1549 return 0;
1550 /* Fall through. */
1551 case 2:
1552 if (x->array[1])
1553 return 0;
1554 /* Fall through. */
1555 case 1:
1556 return !x->array[0];
1557 default:
1558 abort ();
1559 }
1560 }
1561
1562 static INLINE int
1563 cpu_flags_equal (const union i386_cpu_flags *x,
1564 const union i386_cpu_flags *y)
1565 {
1566 switch (ARRAY_SIZE(x->array))
1567 {
1568 case 4:
1569 if (x->array[3] != y->array[3])
1570 return 0;
1571 /* Fall through. */
1572 case 3:
1573 if (x->array[2] != y->array[2])
1574 return 0;
1575 /* Fall through. */
1576 case 2:
1577 if (x->array[1] != y->array[1])
1578 return 0;
1579 /* Fall through. */
1580 case 1:
1581 return x->array[0] == y->array[0];
1582 break;
1583 default:
1584 abort ();
1585 }
1586 }
1587
1588 static INLINE int
1589 cpu_flags_check_cpu64 (i386_cpu_flags f)
1590 {
1591 return !((flag_code == CODE_64BIT && f.bitfield.cpuno64)
1592 || (flag_code != CODE_64BIT && f.bitfield.cpu64));
1593 }
1594
1595 static INLINE i386_cpu_flags
1596 cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y)
1597 {
1598 switch (ARRAY_SIZE (x.array))
1599 {
1600 case 4:
1601 x.array [3] &= y.array [3];
1602 /* Fall through. */
1603 case 3:
1604 x.array [2] &= y.array [2];
1605 /* Fall through. */
1606 case 2:
1607 x.array [1] &= y.array [1];
1608 /* Fall through. */
1609 case 1:
1610 x.array [0] &= y.array [0];
1611 break;
1612 default:
1613 abort ();
1614 }
1615 return x;
1616 }
1617
1618 static INLINE i386_cpu_flags
1619 cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y)
1620 {
1621 switch (ARRAY_SIZE (x.array))
1622 {
1623 case 4:
1624 x.array [3] |= y.array [3];
1625 /* Fall through. */
1626 case 3:
1627 x.array [2] |= y.array [2];
1628 /* Fall through. */
1629 case 2:
1630 x.array [1] |= y.array [1];
1631 /* Fall through. */
1632 case 1:
1633 x.array [0] |= y.array [0];
1634 break;
1635 default:
1636 abort ();
1637 }
1638 return x;
1639 }
1640
1641 static INLINE i386_cpu_flags
1642 cpu_flags_and_not (i386_cpu_flags x, i386_cpu_flags y)
1643 {
1644 switch (ARRAY_SIZE (x.array))
1645 {
1646 case 4:
1647 x.array [3] &= ~y.array [3];
1648 /* Fall through. */
1649 case 3:
1650 x.array [2] &= ~y.array [2];
1651 /* Fall through. */
1652 case 2:
1653 x.array [1] &= ~y.array [1];
1654 /* Fall through. */
1655 case 1:
1656 x.array [0] &= ~y.array [0];
1657 break;
1658 default:
1659 abort ();
1660 }
1661 return x;
1662 }
1663
1664 #define CPU_FLAGS_ARCH_MATCH 0x1
1665 #define CPU_FLAGS_64BIT_MATCH 0x2
1666 #define CPU_FLAGS_AES_MATCH 0x4
1667 #define CPU_FLAGS_PCLMUL_MATCH 0x8
1668 #define CPU_FLAGS_AVX_MATCH 0x10
1669
1670 #define CPU_FLAGS_32BIT_MATCH \
1671 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH \
1672 | CPU_FLAGS_PCLMUL_MATCH | CPU_FLAGS_AVX_MATCH)
1673 #define CPU_FLAGS_PERFECT_MATCH \
1674 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)
1675
1676 /* Return CPU flags match bits. */
1677
1678 static int
1679 cpu_flags_match (const insn_template *t)
1680 {
1681 i386_cpu_flags x = t->cpu_flags;
1682 int match = cpu_flags_check_cpu64 (x) ? CPU_FLAGS_64BIT_MATCH : 0;
1683
1684 x.bitfield.cpu64 = 0;
1685 x.bitfield.cpuno64 = 0;
1686
1687 if (cpu_flags_all_zero (&x))
1688 {
1689 /* This instruction is available on all archs. */
1690 match |= CPU_FLAGS_32BIT_MATCH;
1691 }
1692 else
1693 {
1694 /* This instruction is available only on some archs. */
1695 i386_cpu_flags cpu = cpu_arch_flags;
1696
1697 cpu = cpu_flags_and (x, cpu);
1698 if (!cpu_flags_all_zero (&cpu))
1699 {
1700 if (x.bitfield.cpuavx)
1701 {
1702 /* We only need to check AES/PCLMUL/SSE2AVX with AVX. */
1703 if (cpu.bitfield.cpuavx)
1704 {
1705 /* Check SSE2AVX. */
1706 if (!t->opcode_modifier.sse2avx|| sse2avx)
1707 {
1708 match |= (CPU_FLAGS_ARCH_MATCH
1709 | CPU_FLAGS_AVX_MATCH);
1710 /* Check AES. */
1711 if (!x.bitfield.cpuaes || cpu.bitfield.cpuaes)
1712 match |= CPU_FLAGS_AES_MATCH;
1713 /* Check PCLMUL. */
1714 if (!x.bitfield.cpupclmul
1715 || cpu.bitfield.cpupclmul)
1716 match |= CPU_FLAGS_PCLMUL_MATCH;
1717 }
1718 }
1719 else
1720 match |= CPU_FLAGS_ARCH_MATCH;
1721 }
1722 else if (x.bitfield.cpuavx512vl)
1723 {
1724 /* Match AVX512VL. */
1725 if (cpu.bitfield.cpuavx512vl)
1726 {
1727 /* Need another match. */
1728 cpu.bitfield.cpuavx512vl = 0;
1729 if (!cpu_flags_all_zero (&cpu))
1730 match |= CPU_FLAGS_32BIT_MATCH;
1731 else
1732 match |= CPU_FLAGS_ARCH_MATCH;
1733 }
1734 else
1735 match |= CPU_FLAGS_ARCH_MATCH;
1736 }
1737 else
1738 match |= CPU_FLAGS_32BIT_MATCH;
1739 }
1740 }
1741 return match;
1742 }
1743
1744 static INLINE i386_operand_type
1745 operand_type_and (i386_operand_type x, i386_operand_type y)
1746 {
1747 switch (ARRAY_SIZE (x.array))
1748 {
1749 case 3:
1750 x.array [2] &= y.array [2];
1751 /* Fall through. */
1752 case 2:
1753 x.array [1] &= y.array [1];
1754 /* Fall through. */
1755 case 1:
1756 x.array [0] &= y.array [0];
1757 break;
1758 default:
1759 abort ();
1760 }
1761 return x;
1762 }
1763
1764 static INLINE i386_operand_type
1765 operand_type_or (i386_operand_type x, i386_operand_type y)
1766 {
1767 switch (ARRAY_SIZE (x.array))
1768 {
1769 case 3:
1770 x.array [2] |= y.array [2];
1771 /* Fall through. */
1772 case 2:
1773 x.array [1] |= y.array [1];
1774 /* Fall through. */
1775 case 1:
1776 x.array [0] |= y.array [0];
1777 break;
1778 default:
1779 abort ();
1780 }
1781 return x;
1782 }
1783
1784 static INLINE i386_operand_type
1785 operand_type_xor (i386_operand_type x, i386_operand_type y)
1786 {
1787 switch (ARRAY_SIZE (x.array))
1788 {
1789 case 3:
1790 x.array [2] ^= y.array [2];
1791 /* Fall through. */
1792 case 2:
1793 x.array [1] ^= y.array [1];
1794 /* Fall through. */
1795 case 1:
1796 x.array [0] ^= y.array [0];
1797 break;
1798 default:
1799 abort ();
1800 }
1801 return x;
1802 }
1803
1804 static const i386_operand_type acc32 = OPERAND_TYPE_ACC32;
1805 static const i386_operand_type acc64 = OPERAND_TYPE_ACC64;
1806 static const i386_operand_type control = OPERAND_TYPE_CONTROL;
1807 static const i386_operand_type inoutportreg
1808 = OPERAND_TYPE_INOUTPORTREG;
1809 static const i386_operand_type reg16_inoutportreg
1810 = OPERAND_TYPE_REG16_INOUTPORTREG;
1811 static const i386_operand_type disp16 = OPERAND_TYPE_DISP16;
1812 static const i386_operand_type disp32 = OPERAND_TYPE_DISP32;
1813 static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S;
1814 static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32;
1815 static const i386_operand_type anydisp
1816 = OPERAND_TYPE_ANYDISP;
1817 static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM;
1818 static const i386_operand_type regmask = OPERAND_TYPE_REGMASK;
1819 static const i386_operand_type imm8 = OPERAND_TYPE_IMM8;
1820 static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S;
1821 static const i386_operand_type imm16 = OPERAND_TYPE_IMM16;
1822 static const i386_operand_type imm32 = OPERAND_TYPE_IMM32;
1823 static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S;
1824 static const i386_operand_type imm64 = OPERAND_TYPE_IMM64;
1825 static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32;
1826 static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S;
1827 static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S;
1828 static const i386_operand_type vec_imm4 = OPERAND_TYPE_VEC_IMM4;
1829
1830 enum operand_type
1831 {
1832 reg,
1833 imm,
1834 disp,
1835 anymem
1836 };
1837
1838 static INLINE int
1839 operand_type_check (i386_operand_type t, enum operand_type c)
1840 {
1841 switch (c)
1842 {
1843 case reg:
1844 return t.bitfield.reg;
1845
1846 case imm:
1847 return (t.bitfield.imm8
1848 || t.bitfield.imm8s
1849 || t.bitfield.imm16
1850 || t.bitfield.imm32
1851 || t.bitfield.imm32s
1852 || t.bitfield.imm64);
1853
1854 case disp:
1855 return (t.bitfield.disp8
1856 || t.bitfield.disp16
1857 || t.bitfield.disp32
1858 || t.bitfield.disp32s
1859 || t.bitfield.disp64);
1860
1861 case anymem:
1862 return (t.bitfield.disp8
1863 || t.bitfield.disp16
1864 || t.bitfield.disp32
1865 || t.bitfield.disp32s
1866 || t.bitfield.disp64
1867 || t.bitfield.baseindex);
1868
1869 default:
1870 abort ();
1871 }
1872
1873 return 0;
1874 }
1875
1876 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit/80bit on
1877 operand J for instruction template T. */
1878
1879 static INLINE int
1880 match_reg_size (const insn_template *t, unsigned int j)
1881 {
1882 return !((i.types[j].bitfield.byte
1883 && !t->operand_types[j].bitfield.byte)
1884 || (i.types[j].bitfield.word
1885 && !t->operand_types[j].bitfield.word)
1886 || (i.types[j].bitfield.dword
1887 && !t->operand_types[j].bitfield.dword)
1888 || (i.types[j].bitfield.qword
1889 && !t->operand_types[j].bitfield.qword)
1890 || (i.types[j].bitfield.tbyte
1891 && !t->operand_types[j].bitfield.tbyte));
1892 }
1893
1894 /* Return 1 if there is no conflict in SIMD register on
1895 operand J for instruction template T. */
1896
1897 static INLINE int
1898 match_simd_size (const insn_template *t, unsigned int j)
1899 {
1900 return !((i.types[j].bitfield.xmmword
1901 && !t->operand_types[j].bitfield.xmmword)
1902 || (i.types[j].bitfield.ymmword
1903 && !t->operand_types[j].bitfield.ymmword)
1904 || (i.types[j].bitfield.zmmword
1905 && !t->operand_types[j].bitfield.zmmword));
1906 }
1907
1908 /* Return 1 if there is no conflict in any size on operand J for
1909 instruction template T. */
1910
1911 static INLINE int
1912 match_mem_size (const insn_template *t, unsigned int j)
1913 {
1914 return (match_reg_size (t, j)
1915 && !((i.types[j].bitfield.unspecified
1916 && !i.broadcast
1917 && !t->operand_types[j].bitfield.unspecified)
1918 || (i.types[j].bitfield.fword
1919 && !t->operand_types[j].bitfield.fword)
1920 /* For scalar opcode templates to allow register and memory
1921 operands at the same time, some special casing is needed
1922 here. */
1923 || ((t->operand_types[j].bitfield.regsimd
1924 && !t->opcode_modifier.broadcast
1925 && (t->operand_types[j].bitfield.dword
1926 || t->operand_types[j].bitfield.qword))
1927 ? (i.types[j].bitfield.xmmword
1928 || i.types[j].bitfield.ymmword
1929 || i.types[j].bitfield.zmmword)
1930 : !match_simd_size(t, j))));
1931 }
1932
1933 /* Return 1 if there is no size conflict on any operands for
1934 instruction template T. */
1935
1936 static INLINE int
1937 operand_size_match (const insn_template *t)
1938 {
1939 unsigned int j;
1940 int match = 1;
1941
1942 /* Don't check jump instructions. */
1943 if (t->opcode_modifier.jump
1944 || t->opcode_modifier.jumpbyte
1945 || t->opcode_modifier.jumpdword
1946 || t->opcode_modifier.jumpintersegment)
1947 return match;
1948
1949 /* Check memory and accumulator operand size. */
1950 for (j = 0; j < i.operands; j++)
1951 {
1952 if (!i.types[j].bitfield.reg && !i.types[j].bitfield.regsimd
1953 && t->operand_types[j].bitfield.anysize)
1954 continue;
1955
1956 if (t->operand_types[j].bitfield.reg
1957 && !match_reg_size (t, j))
1958 {
1959 match = 0;
1960 break;
1961 }
1962
1963 if (t->operand_types[j].bitfield.regsimd
1964 && !match_simd_size (t, j))
1965 {
1966 match = 0;
1967 break;
1968 }
1969
1970 if (t->operand_types[j].bitfield.acc
1971 && (!match_reg_size (t, j) || !match_simd_size (t, j)))
1972 {
1973 match = 0;
1974 break;
1975 }
1976
1977 if (i.types[j].bitfield.mem && !match_mem_size (t, j))
1978 {
1979 match = 0;
1980 break;
1981 }
1982 }
1983
1984 if (match)
1985 return match;
1986 else if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
1987 {
1988 mismatch:
1989 i.error = operand_size_mismatch;
1990 return 0;
1991 }
1992
1993 /* Check reverse. */
1994 gas_assert (i.operands == 2);
1995
1996 match = 1;
1997 for (j = 0; j < 2; j++)
1998 {
1999 if ((t->operand_types[j].bitfield.reg
2000 || t->operand_types[j].bitfield.acc)
2001 && !match_reg_size (t, j ? 0 : 1))
2002 goto mismatch;
2003
2004 if (i.types[j].bitfield.mem
2005 && !match_mem_size (t, j ? 0 : 1))
2006 goto mismatch;
2007 }
2008
2009 return match;
2010 }
2011
2012 static INLINE int
2013 operand_type_match (i386_operand_type overlap,
2014 i386_operand_type given)
2015 {
2016 i386_operand_type temp = overlap;
2017
2018 temp.bitfield.jumpabsolute = 0;
2019 temp.bitfield.unspecified = 0;
2020 temp.bitfield.byte = 0;
2021 temp.bitfield.word = 0;
2022 temp.bitfield.dword = 0;
2023 temp.bitfield.fword = 0;
2024 temp.bitfield.qword = 0;
2025 temp.bitfield.tbyte = 0;
2026 temp.bitfield.xmmword = 0;
2027 temp.bitfield.ymmword = 0;
2028 temp.bitfield.zmmword = 0;
2029 if (operand_type_all_zero (&temp))
2030 goto mismatch;
2031
2032 if (given.bitfield.baseindex == overlap.bitfield.baseindex
2033 && given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute)
2034 return 1;
2035
2036 mismatch:
2037 i.error = operand_type_mismatch;
2038 return 0;
2039 }
2040
2041 /* If given types g0 and g1 are registers they must be of the same type
2042 unless the expected operand type register overlap is null.
2043 Memory operand size of certain SIMD instructions is also being checked
2044 here. */
2045
2046 static INLINE int
2047 operand_type_register_match (i386_operand_type g0,
2048 i386_operand_type t0,
2049 i386_operand_type g1,
2050 i386_operand_type t1)
2051 {
2052 if (!g0.bitfield.reg
2053 && !g0.bitfield.regsimd
2054 && (!operand_type_check (g0, anymem)
2055 || g0.bitfield.unspecified
2056 || !t0.bitfield.regsimd))
2057 return 1;
2058
2059 if (!g1.bitfield.reg
2060 && !g1.bitfield.regsimd
2061 && (!operand_type_check (g1, anymem)
2062 || g1.bitfield.unspecified
2063 || !t1.bitfield.regsimd))
2064 return 1;
2065
2066 if (g0.bitfield.byte == g1.bitfield.byte
2067 && g0.bitfield.word == g1.bitfield.word
2068 && g0.bitfield.dword == g1.bitfield.dword
2069 && g0.bitfield.qword == g1.bitfield.qword
2070 && g0.bitfield.xmmword == g1.bitfield.xmmword
2071 && g0.bitfield.ymmword == g1.bitfield.ymmword
2072 && g0.bitfield.zmmword == g1.bitfield.zmmword)
2073 return 1;
2074
2075 if (!(t0.bitfield.byte & t1.bitfield.byte)
2076 && !(t0.bitfield.word & t1.bitfield.word)
2077 && !(t0.bitfield.dword & t1.bitfield.dword)
2078 && !(t0.bitfield.qword & t1.bitfield.qword)
2079 && !(t0.bitfield.xmmword & t1.bitfield.xmmword)
2080 && !(t0.bitfield.ymmword & t1.bitfield.ymmword)
2081 && !(t0.bitfield.zmmword & t1.bitfield.zmmword))
2082 return 1;
2083
2084 i.error = register_type_mismatch;
2085
2086 return 0;
2087 }
2088
2089 static INLINE unsigned int
2090 register_number (const reg_entry *r)
2091 {
2092 unsigned int nr = r->reg_num;
2093
2094 if (r->reg_flags & RegRex)
2095 nr += 8;
2096
2097 if (r->reg_flags & RegVRex)
2098 nr += 16;
2099
2100 return nr;
2101 }
2102
2103 static INLINE unsigned int
2104 mode_from_disp_size (i386_operand_type t)
2105 {
2106 if (t.bitfield.disp8)
2107 return 1;
2108 else if (t.bitfield.disp16
2109 || t.bitfield.disp32
2110 || t.bitfield.disp32s)
2111 return 2;
2112 else
2113 return 0;
2114 }
2115
2116 static INLINE int
2117 fits_in_signed_byte (addressT num)
2118 {
2119 return num + 0x80 <= 0xff;
2120 }
2121
2122 static INLINE int
2123 fits_in_unsigned_byte (addressT num)
2124 {
2125 return num <= 0xff;
2126 }
2127
2128 static INLINE int
2129 fits_in_unsigned_word (addressT num)
2130 {
2131 return num <= 0xffff;
2132 }
2133
2134 static INLINE int
2135 fits_in_signed_word (addressT num)
2136 {
2137 return num + 0x8000 <= 0xffff;
2138 }
2139
2140 static INLINE int
2141 fits_in_signed_long (addressT num ATTRIBUTE_UNUSED)
2142 {
2143 #ifndef BFD64
2144 return 1;
2145 #else
2146 return num + 0x80000000 <= 0xffffffff;
2147 #endif
2148 } /* fits_in_signed_long() */
2149
2150 static INLINE int
2151 fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED)
2152 {
2153 #ifndef BFD64
2154 return 1;
2155 #else
2156 return num <= 0xffffffff;
2157 #endif
2158 } /* fits_in_unsigned_long() */
2159
2160 static INLINE int
2161 fits_in_disp8 (offsetT num)
2162 {
2163 int shift = i.memshift;
2164 unsigned int mask;
2165
2166 if (shift == -1)
2167 abort ();
2168
2169 mask = (1 << shift) - 1;
2170
2171 /* Return 0 if NUM isn't properly aligned. */
2172 if ((num & mask))
2173 return 0;
2174
2175 /* Check if NUM will fit in 8bit after shift. */
2176 return fits_in_signed_byte (num >> shift);
2177 }
2178
2179 static INLINE int
2180 fits_in_imm4 (offsetT num)
2181 {
2182 return (num & 0xf) == num;
2183 }
2184
2185 static i386_operand_type
2186 smallest_imm_type (offsetT num)
2187 {
2188 i386_operand_type t;
2189
2190 operand_type_set (&t, 0);
2191 t.bitfield.imm64 = 1;
2192
2193 if (cpu_arch_tune != PROCESSOR_I486 && num == 1)
2194 {
2195 /* This code is disabled on the 486 because all the Imm1 forms
2196 in the opcode table are slower on the i486. They're the
2197 versions with the implicitly specified single-position
2198 displacement, which has another syntax if you really want to
2199 use that form. */
2200 t.bitfield.imm1 = 1;
2201 t.bitfield.imm8 = 1;
2202 t.bitfield.imm8s = 1;
2203 t.bitfield.imm16 = 1;
2204 t.bitfield.imm32 = 1;
2205 t.bitfield.imm32s = 1;
2206 }
2207 else if (fits_in_signed_byte (num))
2208 {
2209 t.bitfield.imm8 = 1;
2210 t.bitfield.imm8s = 1;
2211 t.bitfield.imm16 = 1;
2212 t.bitfield.imm32 = 1;
2213 t.bitfield.imm32s = 1;
2214 }
2215 else if (fits_in_unsigned_byte (num))
2216 {
2217 t.bitfield.imm8 = 1;
2218 t.bitfield.imm16 = 1;
2219 t.bitfield.imm32 = 1;
2220 t.bitfield.imm32s = 1;
2221 }
2222 else if (fits_in_signed_word (num) || fits_in_unsigned_word (num))
2223 {
2224 t.bitfield.imm16 = 1;
2225 t.bitfield.imm32 = 1;
2226 t.bitfield.imm32s = 1;
2227 }
2228 else if (fits_in_signed_long (num))
2229 {
2230 t.bitfield.imm32 = 1;
2231 t.bitfield.imm32s = 1;
2232 }
2233 else if (fits_in_unsigned_long (num))
2234 t.bitfield.imm32 = 1;
2235
2236 return t;
2237 }
2238
2239 static offsetT
2240 offset_in_range (offsetT val, int size)
2241 {
2242 addressT mask;
2243
2244 switch (size)
2245 {
2246 case 1: mask = ((addressT) 1 << 8) - 1; break;
2247 case 2: mask = ((addressT) 1 << 16) - 1; break;
2248 case 4: mask = ((addressT) 2 << 31) - 1; break;
2249 #ifdef BFD64
2250 case 8: mask = ((addressT) 2 << 63) - 1; break;
2251 #endif
2252 default: abort ();
2253 }
2254
2255 #ifdef BFD64
2256 /* If BFD64, sign extend val for 32bit address mode. */
2257 if (flag_code != CODE_64BIT
2258 || i.prefix[ADDR_PREFIX])
2259 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
2260 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
2261 #endif
2262
2263 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
2264 {
2265 char buf1[40], buf2[40];
2266
2267 sprint_value (buf1, val);
2268 sprint_value (buf2, val & mask);
2269 as_warn (_("%s shortened to %s"), buf1, buf2);
2270 }
2271 return val & mask;
2272 }
2273
2274 enum PREFIX_GROUP
2275 {
2276 PREFIX_EXIST = 0,
2277 PREFIX_LOCK,
2278 PREFIX_REP,
2279 PREFIX_DS,
2280 PREFIX_OTHER
2281 };
2282
2283 /* Returns
2284 a. PREFIX_EXIST if attempting to add a prefix where one from the
2285 same class already exists.
2286 b. PREFIX_LOCK if lock prefix is added.
2287 c. PREFIX_REP if rep/repne prefix is added.
2288 d. PREFIX_DS if ds prefix is added.
2289 e. PREFIX_OTHER if other prefix is added.
2290 */
2291
2292 static enum PREFIX_GROUP
2293 add_prefix (unsigned int prefix)
2294 {
2295 enum PREFIX_GROUP ret = PREFIX_OTHER;
2296 unsigned int q;
2297
2298 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
2299 && flag_code == CODE_64BIT)
2300 {
2301 if ((i.prefix[REX_PREFIX] & prefix & REX_W)
2302 || ((i.prefix[REX_PREFIX] & (REX_R | REX_X | REX_B))
2303 && (prefix & (REX_R | REX_X | REX_B))))
2304 ret = PREFIX_EXIST;
2305 q = REX_PREFIX;
2306 }
2307 else
2308 {
2309 switch (prefix)
2310 {
2311 default:
2312 abort ();
2313
2314 case DS_PREFIX_OPCODE:
2315 ret = PREFIX_DS;
2316 /* Fall through. */
2317 case CS_PREFIX_OPCODE:
2318 case ES_PREFIX_OPCODE:
2319 case FS_PREFIX_OPCODE:
2320 case GS_PREFIX_OPCODE:
2321 case SS_PREFIX_OPCODE:
2322 q = SEG_PREFIX;
2323 break;
2324
2325 case REPNE_PREFIX_OPCODE:
2326 case REPE_PREFIX_OPCODE:
2327 q = REP_PREFIX;
2328 ret = PREFIX_REP;
2329 break;
2330
2331 case LOCK_PREFIX_OPCODE:
2332 q = LOCK_PREFIX;
2333 ret = PREFIX_LOCK;
2334 break;
2335
2336 case FWAIT_OPCODE:
2337 q = WAIT_PREFIX;
2338 break;
2339
2340 case ADDR_PREFIX_OPCODE:
2341 q = ADDR_PREFIX;
2342 break;
2343
2344 case DATA_PREFIX_OPCODE:
2345 q = DATA_PREFIX;
2346 break;
2347 }
2348 if (i.prefix[q] != 0)
2349 ret = PREFIX_EXIST;
2350 }
2351
2352 if (ret)
2353 {
2354 if (!i.prefix[q])
2355 ++i.prefixes;
2356 i.prefix[q] |= prefix;
2357 }
2358 else
2359 as_bad (_("same type of prefix used twice"));
2360
2361 return ret;
2362 }
2363
2364 static void
2365 update_code_flag (int value, int check)
2366 {
2367 PRINTF_LIKE ((*as_error));
2368
2369 flag_code = (enum flag_code) value;
2370 if (flag_code == CODE_64BIT)
2371 {
2372 cpu_arch_flags.bitfield.cpu64 = 1;
2373 cpu_arch_flags.bitfield.cpuno64 = 0;
2374 }
2375 else
2376 {
2377 cpu_arch_flags.bitfield.cpu64 = 0;
2378 cpu_arch_flags.bitfield.cpuno64 = 1;
2379 }
2380 if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm )
2381 {
2382 if (check)
2383 as_error = as_fatal;
2384 else
2385 as_error = as_bad;
2386 (*as_error) (_("64bit mode not supported on `%s'."),
2387 cpu_arch_name ? cpu_arch_name : default_arch);
2388 }
2389 if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386)
2390 {
2391 if (check)
2392 as_error = as_fatal;
2393 else
2394 as_error = as_bad;
2395 (*as_error) (_("32bit mode not supported on `%s'."),
2396 cpu_arch_name ? cpu_arch_name : default_arch);
2397 }
2398 stackop_size = '\0';
2399 }
2400
2401 static void
2402 set_code_flag (int value)
2403 {
2404 update_code_flag (value, 0);
2405 }
2406
2407 static void
2408 set_16bit_gcc_code_flag (int new_code_flag)
2409 {
2410 flag_code = (enum flag_code) new_code_flag;
2411 if (flag_code != CODE_16BIT)
2412 abort ();
2413 cpu_arch_flags.bitfield.cpu64 = 0;
2414 cpu_arch_flags.bitfield.cpuno64 = 1;
2415 stackop_size = LONG_MNEM_SUFFIX;
2416 }
2417
2418 static void
2419 set_intel_syntax (int syntax_flag)
2420 {
2421 /* Find out if register prefixing is specified. */
2422 int ask_naked_reg = 0;
2423
2424 SKIP_WHITESPACE ();
2425 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2426 {
2427 char *string;
2428 int e = get_symbol_name (&string);
2429
2430 if (strcmp (string, "prefix") == 0)
2431 ask_naked_reg = 1;
2432 else if (strcmp (string, "noprefix") == 0)
2433 ask_naked_reg = -1;
2434 else
2435 as_bad (_("bad argument to syntax directive."));
2436 (void) restore_line_pointer (e);
2437 }
2438 demand_empty_rest_of_line ();
2439
2440 intel_syntax = syntax_flag;
2441
2442 if (ask_naked_reg == 0)
2443 allow_naked_reg = (intel_syntax
2444 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
2445 else
2446 allow_naked_reg = (ask_naked_reg < 0);
2447
2448 expr_set_rank (O_full_ptr, syntax_flag ? 10 : 0);
2449
2450 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
2451 identifier_chars['$'] = intel_syntax ? '$' : 0;
2452 register_prefix = allow_naked_reg ? "" : "%";
2453 }
2454
2455 static void
2456 set_intel_mnemonic (int mnemonic_flag)
2457 {
2458 intel_mnemonic = mnemonic_flag;
2459 }
2460
2461 static void
2462 set_allow_index_reg (int flag)
2463 {
2464 allow_index_reg = flag;
2465 }
2466
2467 static void
2468 set_check (int what)
2469 {
2470 enum check_kind *kind;
2471 const char *str;
2472
2473 if (what)
2474 {
2475 kind = &operand_check;
2476 str = "operand";
2477 }
2478 else
2479 {
2480 kind = &sse_check;
2481 str = "sse";
2482 }
2483
2484 SKIP_WHITESPACE ();
2485
2486 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2487 {
2488 char *string;
2489 int e = get_symbol_name (&string);
2490
2491 if (strcmp (string, "none") == 0)
2492 *kind = check_none;
2493 else if (strcmp (string, "warning") == 0)
2494 *kind = check_warning;
2495 else if (strcmp (string, "error") == 0)
2496 *kind = check_error;
2497 else
2498 as_bad (_("bad argument to %s_check directive."), str);
2499 (void) restore_line_pointer (e);
2500 }
2501 else
2502 as_bad (_("missing argument for %s_check directive"), str);
2503
2504 demand_empty_rest_of_line ();
2505 }
2506
2507 static void
2508 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED,
2509 i386_cpu_flags new_flag ATTRIBUTE_UNUSED)
2510 {
2511 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2512 static const char *arch;
2513
2514 /* Intel LIOM is only supported on ELF. */
2515 if (!IS_ELF)
2516 return;
2517
2518 if (!arch)
2519 {
2520 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2521 use default_arch. */
2522 arch = cpu_arch_name;
2523 if (!arch)
2524 arch = default_arch;
2525 }
2526
2527 /* If we are targeting Intel MCU, we must enable it. */
2528 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_IAMCU
2529 || new_flag.bitfield.cpuiamcu)
2530 return;
2531
2532 /* If we are targeting Intel L1OM, we must enable it. */
2533 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_L1OM
2534 || new_flag.bitfield.cpul1om)
2535 return;
2536
2537 /* If we are targeting Intel K1OM, we must enable it. */
2538 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_K1OM
2539 || new_flag.bitfield.cpuk1om)
2540 return;
2541
2542 as_bad (_("`%s' is not supported on `%s'"), name, arch);
2543 #endif
2544 }
2545
2546 static void
2547 set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
2548 {
2549 SKIP_WHITESPACE ();
2550
2551 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2552 {
2553 char *string;
2554 int e = get_symbol_name (&string);
2555 unsigned int j;
2556 i386_cpu_flags flags;
2557
2558 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
2559 {
2560 if (strcmp (string, cpu_arch[j].name) == 0)
2561 {
2562 check_cpu_arch_compatible (string, cpu_arch[j].flags);
2563
2564 if (*string != '.')
2565 {
2566 cpu_arch_name = cpu_arch[j].name;
2567 cpu_sub_arch_name = NULL;
2568 cpu_arch_flags = cpu_arch[j].flags;
2569 if (flag_code == CODE_64BIT)
2570 {
2571 cpu_arch_flags.bitfield.cpu64 = 1;
2572 cpu_arch_flags.bitfield.cpuno64 = 0;
2573 }
2574 else
2575 {
2576 cpu_arch_flags.bitfield.cpu64 = 0;
2577 cpu_arch_flags.bitfield.cpuno64 = 1;
2578 }
2579 cpu_arch_isa = cpu_arch[j].type;
2580 cpu_arch_isa_flags = cpu_arch[j].flags;
2581 if (!cpu_arch_tune_set)
2582 {
2583 cpu_arch_tune = cpu_arch_isa;
2584 cpu_arch_tune_flags = cpu_arch_isa_flags;
2585 }
2586 break;
2587 }
2588
2589 flags = cpu_flags_or (cpu_arch_flags,
2590 cpu_arch[j].flags);
2591
2592 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
2593 {
2594 if (cpu_sub_arch_name)
2595 {
2596 char *name = cpu_sub_arch_name;
2597 cpu_sub_arch_name = concat (name,
2598 cpu_arch[j].name,
2599 (const char *) NULL);
2600 free (name);
2601 }
2602 else
2603 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
2604 cpu_arch_flags = flags;
2605 cpu_arch_isa_flags = flags;
2606 }
2607 (void) restore_line_pointer (e);
2608 demand_empty_rest_of_line ();
2609 return;
2610 }
2611 }
2612
2613 if (*string == '.' && j >= ARRAY_SIZE (cpu_arch))
2614 {
2615 /* Disable an ISA extension. */
2616 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
2617 if (strcmp (string + 1, cpu_noarch [j].name) == 0)
2618 {
2619 flags = cpu_flags_and_not (cpu_arch_flags,
2620 cpu_noarch[j].flags);
2621 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
2622 {
2623 if (cpu_sub_arch_name)
2624 {
2625 char *name = cpu_sub_arch_name;
2626 cpu_sub_arch_name = concat (name, string,
2627 (const char *) NULL);
2628 free (name);
2629 }
2630 else
2631 cpu_sub_arch_name = xstrdup (string);
2632 cpu_arch_flags = flags;
2633 cpu_arch_isa_flags = flags;
2634 }
2635 (void) restore_line_pointer (e);
2636 demand_empty_rest_of_line ();
2637 return;
2638 }
2639
2640 j = ARRAY_SIZE (cpu_arch);
2641 }
2642
2643 if (j >= ARRAY_SIZE (cpu_arch))
2644 as_bad (_("no such architecture: `%s'"), string);
2645
2646 *input_line_pointer = e;
2647 }
2648 else
2649 as_bad (_("missing cpu architecture"));
2650
2651 no_cond_jump_promotion = 0;
2652 if (*input_line_pointer == ','
2653 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
2654 {
2655 char *string;
2656 char e;
2657
2658 ++input_line_pointer;
2659 e = get_symbol_name (&string);
2660
2661 if (strcmp (string, "nojumps") == 0)
2662 no_cond_jump_promotion = 1;
2663 else if (strcmp (string, "jumps") == 0)
2664 ;
2665 else
2666 as_bad (_("no such architecture modifier: `%s'"), string);
2667
2668 (void) restore_line_pointer (e);
2669 }
2670
2671 demand_empty_rest_of_line ();
2672 }
2673
2674 enum bfd_architecture
2675 i386_arch (void)
2676 {
2677 if (cpu_arch_isa == PROCESSOR_L1OM)
2678 {
2679 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2680 || flag_code != CODE_64BIT)
2681 as_fatal (_("Intel L1OM is 64bit ELF only"));
2682 return bfd_arch_l1om;
2683 }
2684 else if (cpu_arch_isa == PROCESSOR_K1OM)
2685 {
2686 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2687 || flag_code != CODE_64BIT)
2688 as_fatal (_("Intel K1OM is 64bit ELF only"));
2689 return bfd_arch_k1om;
2690 }
2691 else if (cpu_arch_isa == PROCESSOR_IAMCU)
2692 {
2693 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2694 || flag_code == CODE_64BIT)
2695 as_fatal (_("Intel MCU is 32bit ELF only"));
2696 return bfd_arch_iamcu;
2697 }
2698 else
2699 return bfd_arch_i386;
2700 }
2701
2702 unsigned long
2703 i386_mach (void)
2704 {
2705 if (!strncmp (default_arch, "x86_64", 6))
2706 {
2707 if (cpu_arch_isa == PROCESSOR_L1OM)
2708 {
2709 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2710 || default_arch[6] != '\0')
2711 as_fatal (_("Intel L1OM is 64bit ELF only"));
2712 return bfd_mach_l1om;
2713 }
2714 else if (cpu_arch_isa == PROCESSOR_K1OM)
2715 {
2716 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2717 || default_arch[6] != '\0')
2718 as_fatal (_("Intel K1OM is 64bit ELF only"));
2719 return bfd_mach_k1om;
2720 }
2721 else if (default_arch[6] == '\0')
2722 return bfd_mach_x86_64;
2723 else
2724 return bfd_mach_x64_32;
2725 }
2726 else if (!strcmp (default_arch, "i386")
2727 || !strcmp (default_arch, "iamcu"))
2728 {
2729 if (cpu_arch_isa == PROCESSOR_IAMCU)
2730 {
2731 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
2732 as_fatal (_("Intel MCU is 32bit ELF only"));
2733 return bfd_mach_i386_iamcu;
2734 }
2735 else
2736 return bfd_mach_i386_i386;
2737 }
2738 else
2739 as_fatal (_("unknown architecture"));
2740 }
2741 \f
2742 void
2743 md_begin (void)
2744 {
2745 const char *hash_err;
2746
2747 /* Support pseudo prefixes like {disp32}. */
2748 lex_type ['{'] = LEX_BEGIN_NAME;
2749
2750 /* Initialize op_hash hash table. */
2751 op_hash = hash_new ();
2752
2753 {
2754 const insn_template *optab;
2755 templates *core_optab;
2756
2757 /* Setup for loop. */
2758 optab = i386_optab;
2759 core_optab = XNEW (templates);
2760 core_optab->start = optab;
2761
2762 while (1)
2763 {
2764 ++optab;
2765 if (optab->name == NULL
2766 || strcmp (optab->name, (optab - 1)->name) != 0)
2767 {
2768 /* different name --> ship out current template list;
2769 add to hash table; & begin anew. */
2770 core_optab->end = optab;
2771 hash_err = hash_insert (op_hash,
2772 (optab - 1)->name,
2773 (void *) core_optab);
2774 if (hash_err)
2775 {
2776 as_fatal (_("can't hash %s: %s"),
2777 (optab - 1)->name,
2778 hash_err);
2779 }
2780 if (optab->name == NULL)
2781 break;
2782 core_optab = XNEW (templates);
2783 core_optab->start = optab;
2784 }
2785 }
2786 }
2787
2788 /* Initialize reg_hash hash table. */
2789 reg_hash = hash_new ();
2790 {
2791 const reg_entry *regtab;
2792 unsigned int regtab_size = i386_regtab_size;
2793
2794 for (regtab = i386_regtab; regtab_size--; regtab++)
2795 {
2796 hash_err = hash_insert (reg_hash, regtab->reg_name, (void *) regtab);
2797 if (hash_err)
2798 as_fatal (_("can't hash %s: %s"),
2799 regtab->reg_name,
2800 hash_err);
2801 }
2802 }
2803
2804 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
2805 {
2806 int c;
2807 char *p;
2808
2809 for (c = 0; c < 256; c++)
2810 {
2811 if (ISDIGIT (c))
2812 {
2813 digit_chars[c] = c;
2814 mnemonic_chars[c] = c;
2815 register_chars[c] = c;
2816 operand_chars[c] = c;
2817 }
2818 else if (ISLOWER (c))
2819 {
2820 mnemonic_chars[c] = c;
2821 register_chars[c] = c;
2822 operand_chars[c] = c;
2823 }
2824 else if (ISUPPER (c))
2825 {
2826 mnemonic_chars[c] = TOLOWER (c);
2827 register_chars[c] = mnemonic_chars[c];
2828 operand_chars[c] = c;
2829 }
2830 else if (c == '{' || c == '}')
2831 {
2832 mnemonic_chars[c] = c;
2833 operand_chars[c] = c;
2834 }
2835
2836 if (ISALPHA (c) || ISDIGIT (c))
2837 identifier_chars[c] = c;
2838 else if (c >= 128)
2839 {
2840 identifier_chars[c] = c;
2841 operand_chars[c] = c;
2842 }
2843 }
2844
2845 #ifdef LEX_AT
2846 identifier_chars['@'] = '@';
2847 #endif
2848 #ifdef LEX_QM
2849 identifier_chars['?'] = '?';
2850 operand_chars['?'] = '?';
2851 #endif
2852 digit_chars['-'] = '-';
2853 mnemonic_chars['_'] = '_';
2854 mnemonic_chars['-'] = '-';
2855 mnemonic_chars['.'] = '.';
2856 identifier_chars['_'] = '_';
2857 identifier_chars['.'] = '.';
2858
2859 for (p = operand_special_chars; *p != '\0'; p++)
2860 operand_chars[(unsigned char) *p] = *p;
2861 }
2862
2863 if (flag_code == CODE_64BIT)
2864 {
2865 #if defined (OBJ_COFF) && defined (TE_PE)
2866 x86_dwarf2_return_column = (OUTPUT_FLAVOR == bfd_target_coff_flavour
2867 ? 32 : 16);
2868 #else
2869 x86_dwarf2_return_column = 16;
2870 #endif
2871 x86_cie_data_alignment = -8;
2872 }
2873 else
2874 {
2875 x86_dwarf2_return_column = 8;
2876 x86_cie_data_alignment = -4;
2877 }
2878 }
2879
2880 void
2881 i386_print_statistics (FILE *file)
2882 {
2883 hash_print_statistics (file, "i386 opcode", op_hash);
2884 hash_print_statistics (file, "i386 register", reg_hash);
2885 }
2886 \f
2887 #ifdef DEBUG386
2888
2889 /* Debugging routines for md_assemble. */
2890 static void pte (insn_template *);
2891 static void pt (i386_operand_type);
2892 static void pe (expressionS *);
2893 static void ps (symbolS *);
2894
2895 static void
2896 pi (char *line, i386_insn *x)
2897 {
2898 unsigned int j;
2899
2900 fprintf (stdout, "%s: template ", line);
2901 pte (&x->tm);
2902 fprintf (stdout, " address: base %s index %s scale %x\n",
2903 x->base_reg ? x->base_reg->reg_name : "none",
2904 x->index_reg ? x->index_reg->reg_name : "none",
2905 x->log2_scale_factor);
2906 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
2907 x->rm.mode, x->rm.reg, x->rm.regmem);
2908 fprintf (stdout, " sib: base %x index %x scale %x\n",
2909 x->sib.base, x->sib.index, x->sib.scale);
2910 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
2911 (x->rex & REX_W) != 0,
2912 (x->rex & REX_R) != 0,
2913 (x->rex & REX_X) != 0,
2914 (x->rex & REX_B) != 0);
2915 for (j = 0; j < x->operands; j++)
2916 {
2917 fprintf (stdout, " #%d: ", j + 1);
2918 pt (x->types[j]);
2919 fprintf (stdout, "\n");
2920 if (x->types[j].bitfield.reg
2921 || x->types[j].bitfield.regmmx
2922 || x->types[j].bitfield.regsimd
2923 || x->types[j].bitfield.sreg2
2924 || x->types[j].bitfield.sreg3
2925 || x->types[j].bitfield.control
2926 || x->types[j].bitfield.debug
2927 || x->types[j].bitfield.test)
2928 fprintf (stdout, "%s\n", x->op[j].regs->reg_name);
2929 if (operand_type_check (x->types[j], imm))
2930 pe (x->op[j].imms);
2931 if (operand_type_check (x->types[j], disp))
2932 pe (x->op[j].disps);
2933 }
2934 }
2935
2936 static void
2937 pte (insn_template *t)
2938 {
2939 unsigned int j;
2940 fprintf (stdout, " %d operands ", t->operands);
2941 fprintf (stdout, "opcode %x ", t->base_opcode);
2942 if (t->extension_opcode != None)
2943 fprintf (stdout, "ext %x ", t->extension_opcode);
2944 if (t->opcode_modifier.d)
2945 fprintf (stdout, "D");
2946 if (t->opcode_modifier.w)
2947 fprintf (stdout, "W");
2948 fprintf (stdout, "\n");
2949 for (j = 0; j < t->operands; j++)
2950 {
2951 fprintf (stdout, " #%d type ", j + 1);
2952 pt (t->operand_types[j]);
2953 fprintf (stdout, "\n");
2954 }
2955 }
2956
2957 static void
2958 pe (expressionS *e)
2959 {
2960 fprintf (stdout, " operation %d\n", e->X_op);
2961 fprintf (stdout, " add_number %ld (%lx)\n",
2962 (long) e->X_add_number, (long) e->X_add_number);
2963 if (e->X_add_symbol)
2964 {
2965 fprintf (stdout, " add_symbol ");
2966 ps (e->X_add_symbol);
2967 fprintf (stdout, "\n");
2968 }
2969 if (e->X_op_symbol)
2970 {
2971 fprintf (stdout, " op_symbol ");
2972 ps (e->X_op_symbol);
2973 fprintf (stdout, "\n");
2974 }
2975 }
2976
2977 static void
2978 ps (symbolS *s)
2979 {
2980 fprintf (stdout, "%s type %s%s",
2981 S_GET_NAME (s),
2982 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
2983 segment_name (S_GET_SEGMENT (s)));
2984 }
2985
2986 static struct type_name
2987 {
2988 i386_operand_type mask;
2989 const char *name;
2990 }
2991 const type_names[] =
2992 {
2993 { OPERAND_TYPE_REG8, "r8" },
2994 { OPERAND_TYPE_REG16, "r16" },
2995 { OPERAND_TYPE_REG32, "r32" },
2996 { OPERAND_TYPE_REG64, "r64" },
2997 { OPERAND_TYPE_IMM8, "i8" },
2998 { OPERAND_TYPE_IMM8, "i8s" },
2999 { OPERAND_TYPE_IMM16, "i16" },
3000 { OPERAND_TYPE_IMM32, "i32" },
3001 { OPERAND_TYPE_IMM32S, "i32s" },
3002 { OPERAND_TYPE_IMM64, "i64" },
3003 { OPERAND_TYPE_IMM1, "i1" },
3004 { OPERAND_TYPE_BASEINDEX, "BaseIndex" },
3005 { OPERAND_TYPE_DISP8, "d8" },
3006 { OPERAND_TYPE_DISP16, "d16" },
3007 { OPERAND_TYPE_DISP32, "d32" },
3008 { OPERAND_TYPE_DISP32S, "d32s" },
3009 { OPERAND_TYPE_DISP64, "d64" },
3010 { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" },
3011 { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" },
3012 { OPERAND_TYPE_CONTROL, "control reg" },
3013 { OPERAND_TYPE_TEST, "test reg" },
3014 { OPERAND_TYPE_DEBUG, "debug reg" },
3015 { OPERAND_TYPE_FLOATREG, "FReg" },
3016 { OPERAND_TYPE_FLOATACC, "FAcc" },
3017 { OPERAND_TYPE_SREG2, "SReg2" },
3018 { OPERAND_TYPE_SREG3, "SReg3" },
3019 { OPERAND_TYPE_ACC, "Acc" },
3020 { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" },
3021 { OPERAND_TYPE_REGMMX, "rMMX" },
3022 { OPERAND_TYPE_REGXMM, "rXMM" },
3023 { OPERAND_TYPE_REGYMM, "rYMM" },
3024 { OPERAND_TYPE_REGZMM, "rZMM" },
3025 { OPERAND_TYPE_REGMASK, "Mask reg" },
3026 { OPERAND_TYPE_ESSEG, "es" },
3027 };
3028
3029 static void
3030 pt (i386_operand_type t)
3031 {
3032 unsigned int j;
3033 i386_operand_type a;
3034
3035 for (j = 0; j < ARRAY_SIZE (type_names); j++)
3036 {
3037 a = operand_type_and (t, type_names[j].mask);
3038 if (!operand_type_all_zero (&a))
3039 fprintf (stdout, "%s, ", type_names[j].name);
3040 }
3041 fflush (stdout);
3042 }
3043
3044 #endif /* DEBUG386 */
3045 \f
3046 static bfd_reloc_code_real_type
3047 reloc (unsigned int size,
3048 int pcrel,
3049 int sign,
3050 bfd_reloc_code_real_type other)
3051 {
3052 if (other != NO_RELOC)
3053 {
3054 reloc_howto_type *rel;
3055
3056 if (size == 8)
3057 switch (other)
3058 {
3059 case BFD_RELOC_X86_64_GOT32:
3060 return BFD_RELOC_X86_64_GOT64;
3061 break;
3062 case BFD_RELOC_X86_64_GOTPLT64:
3063 return BFD_RELOC_X86_64_GOTPLT64;
3064 break;
3065 case BFD_RELOC_X86_64_PLTOFF64:
3066 return BFD_RELOC_X86_64_PLTOFF64;
3067 break;
3068 case BFD_RELOC_X86_64_GOTPC32:
3069 other = BFD_RELOC_X86_64_GOTPC64;
3070 break;
3071 case BFD_RELOC_X86_64_GOTPCREL:
3072 other = BFD_RELOC_X86_64_GOTPCREL64;
3073 break;
3074 case BFD_RELOC_X86_64_TPOFF32:
3075 other = BFD_RELOC_X86_64_TPOFF64;
3076 break;
3077 case BFD_RELOC_X86_64_DTPOFF32:
3078 other = BFD_RELOC_X86_64_DTPOFF64;
3079 break;
3080 default:
3081 break;
3082 }
3083
3084 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3085 if (other == BFD_RELOC_SIZE32)
3086 {
3087 if (size == 8)
3088 other = BFD_RELOC_SIZE64;
3089 if (pcrel)
3090 {
3091 as_bad (_("there are no pc-relative size relocations"));
3092 return NO_RELOC;
3093 }
3094 }
3095 #endif
3096
3097 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
3098 if (size == 4 && (flag_code != CODE_64BIT || disallow_64bit_reloc))
3099 sign = -1;
3100
3101 rel = bfd_reloc_type_lookup (stdoutput, other);
3102 if (!rel)
3103 as_bad (_("unknown relocation (%u)"), other);
3104 else if (size != bfd_get_reloc_size (rel))
3105 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
3106 bfd_get_reloc_size (rel),
3107 size);
3108 else if (pcrel && !rel->pc_relative)
3109 as_bad (_("non-pc-relative relocation for pc-relative field"));
3110 else if ((rel->complain_on_overflow == complain_overflow_signed
3111 && !sign)
3112 || (rel->complain_on_overflow == complain_overflow_unsigned
3113 && sign > 0))
3114 as_bad (_("relocated field and relocation type differ in signedness"));
3115 else
3116 return other;
3117 return NO_RELOC;
3118 }
3119
3120 if (pcrel)
3121 {
3122 if (!sign)
3123 as_bad (_("there are no unsigned pc-relative relocations"));
3124 switch (size)
3125 {
3126 case 1: return BFD_RELOC_8_PCREL;
3127 case 2: return BFD_RELOC_16_PCREL;
3128 case 4: return BFD_RELOC_32_PCREL;
3129 case 8: return BFD_RELOC_64_PCREL;
3130 }
3131 as_bad (_("cannot do %u byte pc-relative relocation"), size);
3132 }
3133 else
3134 {
3135 if (sign > 0)
3136 switch (size)
3137 {
3138 case 4: return BFD_RELOC_X86_64_32S;
3139 }
3140 else
3141 switch (size)
3142 {
3143 case 1: return BFD_RELOC_8;
3144 case 2: return BFD_RELOC_16;
3145 case 4: return BFD_RELOC_32;
3146 case 8: return BFD_RELOC_64;
3147 }
3148 as_bad (_("cannot do %s %u byte relocation"),
3149 sign > 0 ? "signed" : "unsigned", size);
3150 }
3151
3152 return NO_RELOC;
3153 }
3154
3155 /* Here we decide which fixups can be adjusted to make them relative to
3156 the beginning of the section instead of the symbol. Basically we need
3157 to make sure that the dynamic relocations are done correctly, so in
3158 some cases we force the original symbol to be used. */
3159
3160 int
3161 tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED)
3162 {
3163 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3164 if (!IS_ELF)
3165 return 1;
3166
3167 /* Don't adjust pc-relative references to merge sections in 64-bit
3168 mode. */
3169 if (use_rela_relocations
3170 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
3171 && fixP->fx_pcrel)
3172 return 0;
3173
3174 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
3175 and changed later by validate_fix. */
3176 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
3177 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
3178 return 0;
3179
3180 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
3181 for size relocations. */
3182 if (fixP->fx_r_type == BFD_RELOC_SIZE32
3183 || fixP->fx_r_type == BFD_RELOC_SIZE64
3184 || fixP->fx_r_type == BFD_RELOC_386_GOTOFF
3185 || fixP->fx_r_type == BFD_RELOC_386_PLT32
3186 || fixP->fx_r_type == BFD_RELOC_386_GOT32
3187 || fixP->fx_r_type == BFD_RELOC_386_GOT32X
3188 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
3189 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
3190 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
3191 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
3192 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
3193 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
3194 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
3195 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
3196 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
3197 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
3198 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
3199 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
3200 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
3201 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCRELX
3202 || fixP->fx_r_type == BFD_RELOC_X86_64_REX_GOTPCRELX
3203 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
3204 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
3205 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
3206 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
3207 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
3208 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
3209 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
3210 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
3211 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
3212 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
3213 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
3214 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
3215 return 0;
3216 #endif
3217 return 1;
3218 }
3219
3220 static int
3221 intel_float_operand (const char *mnemonic)
3222 {
3223 /* Note that the value returned is meaningful only for opcodes with (memory)
3224 operands, hence the code here is free to improperly handle opcodes that
3225 have no operands (for better performance and smaller code). */
3226
3227 if (mnemonic[0] != 'f')
3228 return 0; /* non-math */
3229
3230 switch (mnemonic[1])
3231 {
3232 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
3233 the fs segment override prefix not currently handled because no
3234 call path can make opcodes without operands get here */
3235 case 'i':
3236 return 2 /* integer op */;
3237 case 'l':
3238 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
3239 return 3; /* fldcw/fldenv */
3240 break;
3241 case 'n':
3242 if (mnemonic[2] != 'o' /* fnop */)
3243 return 3; /* non-waiting control op */
3244 break;
3245 case 'r':
3246 if (mnemonic[2] == 's')
3247 return 3; /* frstor/frstpm */
3248 break;
3249 case 's':
3250 if (mnemonic[2] == 'a')
3251 return 3; /* fsave */
3252 if (mnemonic[2] == 't')
3253 {
3254 switch (mnemonic[3])
3255 {
3256 case 'c': /* fstcw */
3257 case 'd': /* fstdw */
3258 case 'e': /* fstenv */
3259 case 's': /* fsts[gw] */
3260 return 3;
3261 }
3262 }
3263 break;
3264 case 'x':
3265 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
3266 return 0; /* fxsave/fxrstor are not really math ops */
3267 break;
3268 }
3269
3270 return 1;
3271 }
3272
3273 /* Build the VEX prefix. */
3274
3275 static void
3276 build_vex_prefix (const insn_template *t)
3277 {
3278 unsigned int register_specifier;
3279 unsigned int implied_prefix;
3280 unsigned int vector_length;
3281
3282 /* Check register specifier. */
3283 if (i.vex.register_specifier)
3284 {
3285 register_specifier =
3286 ~register_number (i.vex.register_specifier) & 0xf;
3287 gas_assert ((i.vex.register_specifier->reg_flags & RegVRex) == 0);
3288 }
3289 else
3290 register_specifier = 0xf;
3291
3292 /* Use 2-byte VEX prefix by swapping destination and source
3293 operand. */
3294 if (i.vec_encoding != vex_encoding_vex3
3295 && i.dir_encoding == dir_encoding_default
3296 && i.operands == i.reg_operands
3297 && i.tm.opcode_modifier.vexopcode == VEX0F
3298 && i.tm.opcode_modifier.load
3299 && i.rex == REX_B)
3300 {
3301 unsigned int xchg = i.operands - 1;
3302 union i386_op temp_op;
3303 i386_operand_type temp_type;
3304
3305 temp_type = i.types[xchg];
3306 i.types[xchg] = i.types[0];
3307 i.types[0] = temp_type;
3308 temp_op = i.op[xchg];
3309 i.op[xchg] = i.op[0];
3310 i.op[0] = temp_op;
3311
3312 gas_assert (i.rm.mode == 3);
3313
3314 i.rex = REX_R;
3315 xchg = i.rm.regmem;
3316 i.rm.regmem = i.rm.reg;
3317 i.rm.reg = xchg;
3318
3319 /* Use the next insn. */
3320 i.tm = t[1];
3321 }
3322
3323 if (i.tm.opcode_modifier.vex == VEXScalar)
3324 vector_length = avxscalar;
3325 else if (i.tm.opcode_modifier.vex == VEX256)
3326 vector_length = 1;
3327 else
3328 {
3329 unsigned int op;
3330
3331 vector_length = 0;
3332 for (op = 0; op < t->operands; ++op)
3333 if (t->operand_types[op].bitfield.xmmword
3334 && t->operand_types[op].bitfield.ymmword
3335 && i.types[op].bitfield.ymmword)
3336 {
3337 vector_length = 1;
3338 break;
3339 }
3340 }
3341
3342 switch ((i.tm.base_opcode >> 8) & 0xff)
3343 {
3344 case 0:
3345 implied_prefix = 0;
3346 break;
3347 case DATA_PREFIX_OPCODE:
3348 implied_prefix = 1;
3349 break;
3350 case REPE_PREFIX_OPCODE:
3351 implied_prefix = 2;
3352 break;
3353 case REPNE_PREFIX_OPCODE:
3354 implied_prefix = 3;
3355 break;
3356 default:
3357 abort ();
3358 }
3359
3360 /* Use 2-byte VEX prefix if possible. */
3361 if (i.vec_encoding != vex_encoding_vex3
3362 && i.tm.opcode_modifier.vexopcode == VEX0F
3363 && i.tm.opcode_modifier.vexw != VEXW1
3364 && (i.rex & (REX_W | REX_X | REX_B)) == 0)
3365 {
3366 /* 2-byte VEX prefix. */
3367 unsigned int r;
3368
3369 i.vex.length = 2;
3370 i.vex.bytes[0] = 0xc5;
3371
3372 /* Check the REX.R bit. */
3373 r = (i.rex & REX_R) ? 0 : 1;
3374 i.vex.bytes[1] = (r << 7
3375 | register_specifier << 3
3376 | vector_length << 2
3377 | implied_prefix);
3378 }
3379 else
3380 {
3381 /* 3-byte VEX prefix. */
3382 unsigned int m, w;
3383
3384 i.vex.length = 3;
3385
3386 switch (i.tm.opcode_modifier.vexopcode)
3387 {
3388 case VEX0F:
3389 m = 0x1;
3390 i.vex.bytes[0] = 0xc4;
3391 break;
3392 case VEX0F38:
3393 m = 0x2;
3394 i.vex.bytes[0] = 0xc4;
3395 break;
3396 case VEX0F3A:
3397 m = 0x3;
3398 i.vex.bytes[0] = 0xc4;
3399 break;
3400 case XOP08:
3401 m = 0x8;
3402 i.vex.bytes[0] = 0x8f;
3403 break;
3404 case XOP09:
3405 m = 0x9;
3406 i.vex.bytes[0] = 0x8f;
3407 break;
3408 case XOP0A:
3409 m = 0xa;
3410 i.vex.bytes[0] = 0x8f;
3411 break;
3412 default:
3413 abort ();
3414 }
3415
3416 /* The high 3 bits of the second VEX byte are 1's compliment
3417 of RXB bits from REX. */
3418 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
3419
3420 /* Check the REX.W bit. */
3421 w = (i.rex & REX_W) ? 1 : 0;
3422 if (i.tm.opcode_modifier.vexw == VEXW1)
3423 w = 1;
3424
3425 i.vex.bytes[2] = (w << 7
3426 | register_specifier << 3
3427 | vector_length << 2
3428 | implied_prefix);
3429 }
3430 }
3431
3432 /* Build the EVEX prefix. */
3433
3434 static void
3435 build_evex_prefix (void)
3436 {
3437 unsigned int register_specifier;
3438 unsigned int implied_prefix;
3439 unsigned int m, w;
3440 rex_byte vrex_used = 0;
3441
3442 /* Check register specifier. */
3443 if (i.vex.register_specifier)
3444 {
3445 gas_assert ((i.vrex & REX_X) == 0);
3446
3447 register_specifier = i.vex.register_specifier->reg_num;
3448 if ((i.vex.register_specifier->reg_flags & RegRex))
3449 register_specifier += 8;
3450 /* The upper 16 registers are encoded in the fourth byte of the
3451 EVEX prefix. */
3452 if (!(i.vex.register_specifier->reg_flags & RegVRex))
3453 i.vex.bytes[3] = 0x8;
3454 register_specifier = ~register_specifier & 0xf;
3455 }
3456 else
3457 {
3458 register_specifier = 0xf;
3459
3460 /* Encode upper 16 vector index register in the fourth byte of
3461 the EVEX prefix. */
3462 if (!(i.vrex & REX_X))
3463 i.vex.bytes[3] = 0x8;
3464 else
3465 vrex_used |= REX_X;
3466 }
3467
3468 switch ((i.tm.base_opcode >> 8) & 0xff)
3469 {
3470 case 0:
3471 implied_prefix = 0;
3472 break;
3473 case DATA_PREFIX_OPCODE:
3474 implied_prefix = 1;
3475 break;
3476 case REPE_PREFIX_OPCODE:
3477 implied_prefix = 2;
3478 break;
3479 case REPNE_PREFIX_OPCODE:
3480 implied_prefix = 3;
3481 break;
3482 default:
3483 abort ();
3484 }
3485
3486 /* 4 byte EVEX prefix. */
3487 i.vex.length = 4;
3488 i.vex.bytes[0] = 0x62;
3489
3490 /* mmmm bits. */
3491 switch (i.tm.opcode_modifier.vexopcode)
3492 {
3493 case VEX0F:
3494 m = 1;
3495 break;
3496 case VEX0F38:
3497 m = 2;
3498 break;
3499 case VEX0F3A:
3500 m = 3;
3501 break;
3502 default:
3503 abort ();
3504 break;
3505 }
3506
3507 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3508 bits from REX. */
3509 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
3510
3511 /* The fifth bit of the second EVEX byte is 1's compliment of the
3512 REX_R bit in VREX. */
3513 if (!(i.vrex & REX_R))
3514 i.vex.bytes[1] |= 0x10;
3515 else
3516 vrex_used |= REX_R;
3517
3518 if ((i.reg_operands + i.imm_operands) == i.operands)
3519 {
3520 /* When all operands are registers, the REX_X bit in REX is not
3521 used. We reuse it to encode the upper 16 registers, which is
3522 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3523 as 1's compliment. */
3524 if ((i.vrex & REX_B))
3525 {
3526 vrex_used |= REX_B;
3527 i.vex.bytes[1] &= ~0x40;
3528 }
3529 }
3530
3531 /* EVEX instructions shouldn't need the REX prefix. */
3532 i.vrex &= ~vrex_used;
3533 gas_assert (i.vrex == 0);
3534
3535 /* Check the REX.W bit. */
3536 w = (i.rex & REX_W) ? 1 : 0;
3537 if (i.tm.opcode_modifier.vexw)
3538 {
3539 if (i.tm.opcode_modifier.vexw == VEXW1)
3540 w = 1;
3541 }
3542 /* If w is not set it means we are dealing with WIG instruction. */
3543 else if (!w)
3544 {
3545 if (evexwig == evexw1)
3546 w = 1;
3547 }
3548
3549 /* Encode the U bit. */
3550 implied_prefix |= 0x4;
3551
3552 /* The third byte of the EVEX prefix. */
3553 i.vex.bytes[2] = (w << 7 | register_specifier << 3 | implied_prefix);
3554
3555 /* The fourth byte of the EVEX prefix. */
3556 /* The zeroing-masking bit. */
3557 if (i.mask && i.mask->zeroing)
3558 i.vex.bytes[3] |= 0x80;
3559
3560 /* Don't always set the broadcast bit if there is no RC. */
3561 if (!i.rounding)
3562 {
3563 /* Encode the vector length. */
3564 unsigned int vec_length;
3565
3566 switch (i.tm.opcode_modifier.evex)
3567 {
3568 case EVEXLIG: /* LL' is ignored */
3569 vec_length = evexlig << 5;
3570 break;
3571 case EVEX128:
3572 vec_length = 0 << 5;
3573 break;
3574 case EVEX256:
3575 vec_length = 1 << 5;
3576 break;
3577 case EVEX512:
3578 vec_length = 2 << 5;
3579 break;
3580 default:
3581 abort ();
3582 break;
3583 }
3584 i.vex.bytes[3] |= vec_length;
3585 /* Encode the broadcast bit. */
3586 if (i.broadcast)
3587 i.vex.bytes[3] |= 0x10;
3588 }
3589 else
3590 {
3591 if (i.rounding->type != saeonly)
3592 i.vex.bytes[3] |= 0x10 | (i.rounding->type << 5);
3593 else
3594 i.vex.bytes[3] |= 0x10 | (evexrcig << 5);
3595 }
3596
3597 if (i.mask && i.mask->mask)
3598 i.vex.bytes[3] |= i.mask->mask->reg_num;
3599 }
3600
3601 static void
3602 process_immext (void)
3603 {
3604 expressionS *exp;
3605
3606 if ((i.tm.cpu_flags.bitfield.cpusse3 || i.tm.cpu_flags.bitfield.cpusvme)
3607 && i.operands > 0)
3608 {
3609 /* MONITOR/MWAIT as well as SVME instructions have fixed operands
3610 with an opcode suffix which is coded in the same place as an
3611 8-bit immediate field would be.
3612 Here we check those operands and remove them afterwards. */
3613 unsigned int x;
3614
3615 for (x = 0; x < i.operands; x++)
3616 if (register_number (i.op[x].regs) != x)
3617 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3618 register_prefix, i.op[x].regs->reg_name, x + 1,
3619 i.tm.name);
3620
3621 i.operands = 0;
3622 }
3623
3624 if (i.tm.cpu_flags.bitfield.cpumwaitx && i.operands > 0)
3625 {
3626 /* MONITORX/MWAITX instructions have fixed operands with an opcode
3627 suffix which is coded in the same place as an 8-bit immediate
3628 field would be.
3629 Here we check those operands and remove them afterwards. */
3630 unsigned int x;
3631
3632 if (i.operands != 3)
3633 abort();
3634
3635 for (x = 0; x < 2; x++)
3636 if (register_number (i.op[x].regs) != x)
3637 goto bad_register_operand;
3638
3639 /* Check for third operand for mwaitx/monitorx insn. */
3640 if (register_number (i.op[x].regs)
3641 != (x + (i.tm.extension_opcode == 0xfb)))
3642 {
3643 bad_register_operand:
3644 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3645 register_prefix, i.op[x].regs->reg_name, x+1,
3646 i.tm.name);
3647 }
3648
3649 i.operands = 0;
3650 }
3651
3652 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
3653 which is coded in the same place as an 8-bit immediate field
3654 would be. Here we fake an 8-bit immediate operand from the
3655 opcode suffix stored in tm.extension_opcode.
3656
3657 AVX instructions also use this encoding, for some of
3658 3 argument instructions. */
3659
3660 gas_assert (i.imm_operands <= 1
3661 && (i.operands <= 2
3662 || ((i.tm.opcode_modifier.vex
3663 || i.tm.opcode_modifier.evex)
3664 && i.operands <= 4)));
3665
3666 exp = &im_expressions[i.imm_operands++];
3667 i.op[i.operands].imms = exp;
3668 i.types[i.operands] = imm8;
3669 i.operands++;
3670 exp->X_op = O_constant;
3671 exp->X_add_number = i.tm.extension_opcode;
3672 i.tm.extension_opcode = None;
3673 }
3674
3675
3676 static int
3677 check_hle (void)
3678 {
3679 switch (i.tm.opcode_modifier.hleprefixok)
3680 {
3681 default:
3682 abort ();
3683 case HLEPrefixNone:
3684 as_bad (_("invalid instruction `%s' after `%s'"),
3685 i.tm.name, i.hle_prefix);
3686 return 0;
3687 case HLEPrefixLock:
3688 if (i.prefix[LOCK_PREFIX])
3689 return 1;
3690 as_bad (_("missing `lock' with `%s'"), i.hle_prefix);
3691 return 0;
3692 case HLEPrefixAny:
3693 return 1;
3694 case HLEPrefixRelease:
3695 if (i.prefix[HLE_PREFIX] != XRELEASE_PREFIX_OPCODE)
3696 {
3697 as_bad (_("instruction `%s' after `xacquire' not allowed"),
3698 i.tm.name);
3699 return 0;
3700 }
3701 if (i.mem_operands == 0
3702 || !operand_type_check (i.types[i.operands - 1], anymem))
3703 {
3704 as_bad (_("memory destination needed for instruction `%s'"
3705 " after `xrelease'"), i.tm.name);
3706 return 0;
3707 }
3708 return 1;
3709 }
3710 }
3711
3712 /* This is the guts of the machine-dependent assembler. LINE points to a
3713 machine dependent instruction. This function is supposed to emit
3714 the frags/bytes it assembles to. */
3715
3716 void
3717 md_assemble (char *line)
3718 {
3719 unsigned int j;
3720 char mnemonic[MAX_MNEM_SIZE], mnem_suffix;
3721 const insn_template *t;
3722
3723 /* Initialize globals. */
3724 memset (&i, '\0', sizeof (i));
3725 for (j = 0; j < MAX_OPERANDS; j++)
3726 i.reloc[j] = NO_RELOC;
3727 memset (disp_expressions, '\0', sizeof (disp_expressions));
3728 memset (im_expressions, '\0', sizeof (im_expressions));
3729 save_stack_p = save_stack;
3730
3731 /* First parse an instruction mnemonic & call i386_operand for the operands.
3732 We assume that the scrubber has arranged it so that line[0] is the valid
3733 start of a (possibly prefixed) mnemonic. */
3734
3735 line = parse_insn (line, mnemonic);
3736 if (line == NULL)
3737 return;
3738 mnem_suffix = i.suffix;
3739
3740 line = parse_operands (line, mnemonic);
3741 this_operand = -1;
3742 xfree (i.memop1_string);
3743 i.memop1_string = NULL;
3744 if (line == NULL)
3745 return;
3746
3747 /* Now we've parsed the mnemonic into a set of templates, and have the
3748 operands at hand. */
3749
3750 /* All intel opcodes have reversed operands except for "bound" and
3751 "enter". We also don't reverse intersegment "jmp" and "call"
3752 instructions with 2 immediate operands so that the immediate segment
3753 precedes the offset, as it does when in AT&T mode. */
3754 if (intel_syntax
3755 && i.operands > 1
3756 && (strcmp (mnemonic, "bound") != 0)
3757 && (strcmp (mnemonic, "invlpga") != 0)
3758 && !(operand_type_check (i.types[0], imm)
3759 && operand_type_check (i.types[1], imm)))
3760 swap_operands ();
3761
3762 /* The order of the immediates should be reversed
3763 for 2 immediates extrq and insertq instructions */
3764 if (i.imm_operands == 2
3765 && (strcmp (mnemonic, "extrq") == 0
3766 || strcmp (mnemonic, "insertq") == 0))
3767 swap_2_operands (0, 1);
3768
3769 if (i.imm_operands)
3770 optimize_imm ();
3771
3772 /* Don't optimize displacement for movabs since it only takes 64bit
3773 displacement. */
3774 if (i.disp_operands
3775 && i.disp_encoding != disp_encoding_32bit
3776 && (flag_code != CODE_64BIT
3777 || strcmp (mnemonic, "movabs") != 0))
3778 optimize_disp ();
3779
3780 /* Next, we find a template that matches the given insn,
3781 making sure the overlap of the given operands types is consistent
3782 with the template operand types. */
3783
3784 if (!(t = match_template (mnem_suffix)))
3785 return;
3786
3787 if (sse_check != check_none
3788 && !i.tm.opcode_modifier.noavx
3789 && (i.tm.cpu_flags.bitfield.cpusse
3790 || i.tm.cpu_flags.bitfield.cpusse2
3791 || i.tm.cpu_flags.bitfield.cpusse3
3792 || i.tm.cpu_flags.bitfield.cpussse3
3793 || i.tm.cpu_flags.bitfield.cpusse4_1
3794 || i.tm.cpu_flags.bitfield.cpusse4_2))
3795 {
3796 (sse_check == check_warning
3797 ? as_warn
3798 : as_bad) (_("SSE instruction `%s' is used"), i.tm.name);
3799 }
3800
3801 /* Zap movzx and movsx suffix. The suffix has been set from
3802 "word ptr" or "byte ptr" on the source operand in Intel syntax
3803 or extracted from mnemonic in AT&T syntax. But we'll use
3804 the destination register to choose the suffix for encoding. */
3805 if ((i.tm.base_opcode & ~9) == 0x0fb6)
3806 {
3807 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
3808 there is no suffix, the default will be byte extension. */
3809 if (i.reg_operands != 2
3810 && !i.suffix
3811 && intel_syntax)
3812 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
3813
3814 i.suffix = 0;
3815 }
3816
3817 if (i.tm.opcode_modifier.fwait)
3818 if (!add_prefix (FWAIT_OPCODE))
3819 return;
3820
3821 /* Check if REP prefix is OK. */
3822 if (i.rep_prefix && !i.tm.opcode_modifier.repprefixok)
3823 {
3824 as_bad (_("invalid instruction `%s' after `%s'"),
3825 i.tm.name, i.rep_prefix);
3826 return;
3827 }
3828
3829 /* Check for lock without a lockable instruction. Destination operand
3830 must be memory unless it is xchg (0x86). */
3831 if (i.prefix[LOCK_PREFIX]
3832 && (!i.tm.opcode_modifier.islockable
3833 || i.mem_operands == 0
3834 || (i.tm.base_opcode != 0x86
3835 && !operand_type_check (i.types[i.operands - 1], anymem))))
3836 {
3837 as_bad (_("expecting lockable instruction after `lock'"));
3838 return;
3839 }
3840
3841 /* Check if HLE prefix is OK. */
3842 if (i.hle_prefix && !check_hle ())
3843 return;
3844
3845 /* Check BND prefix. */
3846 if (i.bnd_prefix && !i.tm.opcode_modifier.bndprefixok)
3847 as_bad (_("expecting valid branch instruction after `bnd'"));
3848
3849 /* Check NOTRACK prefix. */
3850 if (i.notrack_prefix && !i.tm.opcode_modifier.notrackprefixok)
3851 as_bad (_("expecting indirect branch instruction after `notrack'"));
3852
3853 if (i.tm.cpu_flags.bitfield.cpumpx)
3854 {
3855 if (flag_code == CODE_64BIT && i.prefix[ADDR_PREFIX])
3856 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
3857 else if (flag_code != CODE_16BIT
3858 ? i.prefix[ADDR_PREFIX]
3859 : i.mem_operands && !i.prefix[ADDR_PREFIX])
3860 as_bad (_("16-bit address isn't allowed in MPX instructions"));
3861 }
3862
3863 /* Insert BND prefix. */
3864 if (add_bnd_prefix
3865 && i.tm.opcode_modifier.bndprefixok
3866 && !i.prefix[BND_PREFIX])
3867 add_prefix (BND_PREFIX_OPCODE);
3868
3869 /* Check string instruction segment overrides. */
3870 if (i.tm.opcode_modifier.isstring && i.mem_operands != 0)
3871 {
3872 if (!check_string ())
3873 return;
3874 i.disp_operands = 0;
3875 }
3876
3877 if (!process_suffix ())
3878 return;
3879
3880 /* Update operand types. */
3881 for (j = 0; j < i.operands; j++)
3882 i.types[j] = operand_type_and (i.types[j], i.tm.operand_types[j]);
3883
3884 /* Make still unresolved immediate matches conform to size of immediate
3885 given in i.suffix. */
3886 if (!finalize_imm ())
3887 return;
3888
3889 if (i.types[0].bitfield.imm1)
3890 i.imm_operands = 0; /* kludge for shift insns. */
3891
3892 /* We only need to check those implicit registers for instructions
3893 with 3 operands or less. */
3894 if (i.operands <= 3)
3895 for (j = 0; j < i.operands; j++)
3896 if (i.types[j].bitfield.inoutportreg
3897 || i.types[j].bitfield.shiftcount
3898 || (i.types[j].bitfield.acc && !i.types[j].bitfield.xmmword))
3899 i.reg_operands--;
3900
3901 /* ImmExt should be processed after SSE2AVX. */
3902 if (!i.tm.opcode_modifier.sse2avx
3903 && i.tm.opcode_modifier.immext)
3904 process_immext ();
3905
3906 /* For insns with operands there are more diddles to do to the opcode. */
3907 if (i.operands)
3908 {
3909 if (!process_operands ())
3910 return;
3911 }
3912 else if (!quiet_warnings && i.tm.opcode_modifier.ugh)
3913 {
3914 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
3915 as_warn (_("translating to `%sp'"), i.tm.name);
3916 }
3917
3918 if (i.tm.opcode_modifier.vex || i.tm.opcode_modifier.evex)
3919 {
3920 if (flag_code == CODE_16BIT)
3921 {
3922 as_bad (_("instruction `%s' isn't supported in 16-bit mode."),
3923 i.tm.name);
3924 return;
3925 }
3926
3927 if (i.tm.opcode_modifier.vex)
3928 build_vex_prefix (t);
3929 else
3930 build_evex_prefix ();
3931 }
3932
3933 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
3934 instructions may define INT_OPCODE as well, so avoid this corner
3935 case for those instructions that use MODRM. */
3936 if (i.tm.base_opcode == INT_OPCODE
3937 && !i.tm.opcode_modifier.modrm
3938 && i.op[0].imms->X_add_number == 3)
3939 {
3940 i.tm.base_opcode = INT3_OPCODE;
3941 i.imm_operands = 0;
3942 }
3943
3944 if ((i.tm.opcode_modifier.jump
3945 || i.tm.opcode_modifier.jumpbyte
3946 || i.tm.opcode_modifier.jumpdword)
3947 && i.op[0].disps->X_op == O_constant)
3948 {
3949 /* Convert "jmp constant" (and "call constant") to a jump (call) to
3950 the absolute address given by the constant. Since ix86 jumps and
3951 calls are pc relative, we need to generate a reloc. */
3952 i.op[0].disps->X_add_symbol = &abs_symbol;
3953 i.op[0].disps->X_op = O_symbol;
3954 }
3955
3956 if (i.tm.opcode_modifier.rex64)
3957 i.rex |= REX_W;
3958
3959 /* For 8 bit registers we need an empty rex prefix. Also if the
3960 instruction already has a prefix, we need to convert old
3961 registers to new ones. */
3962
3963 if ((i.types[0].bitfield.reg && i.types[0].bitfield.byte
3964 && (i.op[0].regs->reg_flags & RegRex64) != 0)
3965 || (i.types[1].bitfield.reg && i.types[1].bitfield.byte
3966 && (i.op[1].regs->reg_flags & RegRex64) != 0)
3967 || (((i.types[0].bitfield.reg && i.types[0].bitfield.byte)
3968 || (i.types[1].bitfield.reg && i.types[1].bitfield.byte))
3969 && i.rex != 0))
3970 {
3971 int x;
3972
3973 i.rex |= REX_OPCODE;
3974 for (x = 0; x < 2; x++)
3975 {
3976 /* Look for 8 bit operand that uses old registers. */
3977 if (i.types[x].bitfield.reg && i.types[x].bitfield.byte
3978 && (i.op[x].regs->reg_flags & RegRex64) == 0)
3979 {
3980 /* In case it is "hi" register, give up. */
3981 if (i.op[x].regs->reg_num > 3)
3982 as_bad (_("can't encode register '%s%s' in an "
3983 "instruction requiring REX prefix."),
3984 register_prefix, i.op[x].regs->reg_name);
3985
3986 /* Otherwise it is equivalent to the extended register.
3987 Since the encoding doesn't change this is merely
3988 cosmetic cleanup for debug output. */
3989
3990 i.op[x].regs = i.op[x].regs + 8;
3991 }
3992 }
3993 }
3994
3995 if (i.rex != 0)
3996 add_prefix (REX_OPCODE | i.rex);
3997
3998 /* We are ready to output the insn. */
3999 output_insn ();
4000 }
4001
4002 static char *
4003 parse_insn (char *line, char *mnemonic)
4004 {
4005 char *l = line;
4006 char *token_start = l;
4007 char *mnem_p;
4008 int supported;
4009 const insn_template *t;
4010 char *dot_p = NULL;
4011
4012 while (1)
4013 {
4014 mnem_p = mnemonic;
4015 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
4016 {
4017 if (*mnem_p == '.')
4018 dot_p = mnem_p;
4019 mnem_p++;
4020 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
4021 {
4022 as_bad (_("no such instruction: `%s'"), token_start);
4023 return NULL;
4024 }
4025 l++;
4026 }
4027 if (!is_space_char (*l)
4028 && *l != END_OF_INSN
4029 && (intel_syntax
4030 || (*l != PREFIX_SEPARATOR
4031 && *l != ',')))
4032 {
4033 as_bad (_("invalid character %s in mnemonic"),
4034 output_invalid (*l));
4035 return NULL;
4036 }
4037 if (token_start == l)
4038 {
4039 if (!intel_syntax && *l == PREFIX_SEPARATOR)
4040 as_bad (_("expecting prefix; got nothing"));
4041 else
4042 as_bad (_("expecting mnemonic; got nothing"));
4043 return NULL;
4044 }
4045
4046 /* Look up instruction (or prefix) via hash table. */
4047 current_templates = (const templates *) hash_find (op_hash, mnemonic);
4048
4049 if (*l != END_OF_INSN
4050 && (!is_space_char (*l) || l[1] != END_OF_INSN)
4051 && current_templates
4052 && current_templates->start->opcode_modifier.isprefix)
4053 {
4054 if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags))
4055 {
4056 as_bad ((flag_code != CODE_64BIT
4057 ? _("`%s' is only supported in 64-bit mode")
4058 : _("`%s' is not supported in 64-bit mode")),
4059 current_templates->start->name);
4060 return NULL;
4061 }
4062 /* If we are in 16-bit mode, do not allow addr16 or data16.
4063 Similarly, in 32-bit mode, do not allow addr32 or data32. */
4064 if ((current_templates->start->opcode_modifier.size16
4065 || current_templates->start->opcode_modifier.size32)
4066 && flag_code != CODE_64BIT
4067 && (current_templates->start->opcode_modifier.size32
4068 ^ (flag_code == CODE_16BIT)))
4069 {
4070 as_bad (_("redundant %s prefix"),
4071 current_templates->start->name);
4072 return NULL;
4073 }
4074 if (current_templates->start->opcode_length == 0)
4075 {
4076 /* Handle pseudo prefixes. */
4077 switch (current_templates->start->base_opcode)
4078 {
4079 case 0x0:
4080 /* {disp8} */
4081 i.disp_encoding = disp_encoding_8bit;
4082 break;
4083 case 0x1:
4084 /* {disp32} */
4085 i.disp_encoding = disp_encoding_32bit;
4086 break;
4087 case 0x2:
4088 /* {load} */
4089 i.dir_encoding = dir_encoding_load;
4090 break;
4091 case 0x3:
4092 /* {store} */
4093 i.dir_encoding = dir_encoding_store;
4094 break;
4095 case 0x4:
4096 /* {vex2} */
4097 i.vec_encoding = vex_encoding_vex2;
4098 break;
4099 case 0x5:
4100 /* {vex3} */
4101 i.vec_encoding = vex_encoding_vex3;
4102 break;
4103 case 0x6:
4104 /* {evex} */
4105 i.vec_encoding = vex_encoding_evex;
4106 break;
4107 default:
4108 abort ();
4109 }
4110 }
4111 else
4112 {
4113 /* Add prefix, checking for repeated prefixes. */
4114 switch (add_prefix (current_templates->start->base_opcode))
4115 {
4116 case PREFIX_EXIST:
4117 return NULL;
4118 case PREFIX_DS:
4119 if (current_templates->start->cpu_flags.bitfield.cpuibt)
4120 i.notrack_prefix = current_templates->start->name;
4121 break;
4122 case PREFIX_REP:
4123 if (current_templates->start->cpu_flags.bitfield.cpuhle)
4124 i.hle_prefix = current_templates->start->name;
4125 else if (current_templates->start->cpu_flags.bitfield.cpumpx)
4126 i.bnd_prefix = current_templates->start->name;
4127 else
4128 i.rep_prefix = current_templates->start->name;
4129 break;
4130 default:
4131 break;
4132 }
4133 }
4134 /* Skip past PREFIX_SEPARATOR and reset token_start. */
4135 token_start = ++l;
4136 }
4137 else
4138 break;
4139 }
4140
4141 if (!current_templates)
4142 {
4143 /* Check if we should swap operand or force 32bit displacement in
4144 encoding. */
4145 if (mnem_p - 2 == dot_p && dot_p[1] == 's')
4146 i.dir_encoding = dir_encoding_store;
4147 else if (mnem_p - 3 == dot_p
4148 && dot_p[1] == 'd'
4149 && dot_p[2] == '8')
4150 i.disp_encoding = disp_encoding_8bit;
4151 else if (mnem_p - 4 == dot_p
4152 && dot_p[1] == 'd'
4153 && dot_p[2] == '3'
4154 && dot_p[3] == '2')
4155 i.disp_encoding = disp_encoding_32bit;
4156 else
4157 goto check_suffix;
4158 mnem_p = dot_p;
4159 *dot_p = '\0';
4160 current_templates = (const templates *) hash_find (op_hash, mnemonic);
4161 }
4162
4163 if (!current_templates)
4164 {
4165 check_suffix:
4166 /* See if we can get a match by trimming off a suffix. */
4167 switch (mnem_p[-1])
4168 {
4169 case WORD_MNEM_SUFFIX:
4170 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
4171 i.suffix = SHORT_MNEM_SUFFIX;
4172 else
4173 /* Fall through. */
4174 case BYTE_MNEM_SUFFIX:
4175 case QWORD_MNEM_SUFFIX:
4176 i.suffix = mnem_p[-1];
4177 mnem_p[-1] = '\0';
4178 current_templates = (const templates *) hash_find (op_hash,
4179 mnemonic);
4180 break;
4181 case SHORT_MNEM_SUFFIX:
4182 case LONG_MNEM_SUFFIX:
4183 if (!intel_syntax)
4184 {
4185 i.suffix = mnem_p[-1];
4186 mnem_p[-1] = '\0';
4187 current_templates = (const templates *) hash_find (op_hash,
4188 mnemonic);
4189 }
4190 break;
4191
4192 /* Intel Syntax. */
4193 case 'd':
4194 if (intel_syntax)
4195 {
4196 if (intel_float_operand (mnemonic) == 1)
4197 i.suffix = SHORT_MNEM_SUFFIX;
4198 else
4199 i.suffix = LONG_MNEM_SUFFIX;
4200 mnem_p[-1] = '\0';
4201 current_templates = (const templates *) hash_find (op_hash,
4202 mnemonic);
4203 }
4204 break;
4205 }
4206 if (!current_templates)
4207 {
4208 as_bad (_("no such instruction: `%s'"), token_start);
4209 return NULL;
4210 }
4211 }
4212
4213 if (current_templates->start->opcode_modifier.jump
4214 || current_templates->start->opcode_modifier.jumpbyte)
4215 {
4216 /* Check for a branch hint. We allow ",pt" and ",pn" for
4217 predict taken and predict not taken respectively.
4218 I'm not sure that branch hints actually do anything on loop
4219 and jcxz insns (JumpByte) for current Pentium4 chips. They
4220 may work in the future and it doesn't hurt to accept them
4221 now. */
4222 if (l[0] == ',' && l[1] == 'p')
4223 {
4224 if (l[2] == 't')
4225 {
4226 if (!add_prefix (DS_PREFIX_OPCODE))
4227 return NULL;
4228 l += 3;
4229 }
4230 else if (l[2] == 'n')
4231 {
4232 if (!add_prefix (CS_PREFIX_OPCODE))
4233 return NULL;
4234 l += 3;
4235 }
4236 }
4237 }
4238 /* Any other comma loses. */
4239 if (*l == ',')
4240 {
4241 as_bad (_("invalid character %s in mnemonic"),
4242 output_invalid (*l));
4243 return NULL;
4244 }
4245
4246 /* Check if instruction is supported on specified architecture. */
4247 supported = 0;
4248 for (t = current_templates->start; t < current_templates->end; ++t)
4249 {
4250 supported |= cpu_flags_match (t);
4251 if (supported == CPU_FLAGS_PERFECT_MATCH)
4252 goto skip;
4253 }
4254
4255 if (!(supported & CPU_FLAGS_64BIT_MATCH))
4256 {
4257 as_bad (flag_code == CODE_64BIT
4258 ? _("`%s' is not supported in 64-bit mode")
4259 : _("`%s' is only supported in 64-bit mode"),
4260 current_templates->start->name);
4261 return NULL;
4262 }
4263 if (supported != CPU_FLAGS_PERFECT_MATCH)
4264 {
4265 as_bad (_("`%s' is not supported on `%s%s'"),
4266 current_templates->start->name,
4267 cpu_arch_name ? cpu_arch_name : default_arch,
4268 cpu_sub_arch_name ? cpu_sub_arch_name : "");
4269 return NULL;
4270 }
4271
4272 skip:
4273 if (!cpu_arch_flags.bitfield.cpui386
4274 && (flag_code != CODE_16BIT))
4275 {
4276 as_warn (_("use .code16 to ensure correct addressing mode"));
4277 }
4278
4279 return l;
4280 }
4281
4282 static char *
4283 parse_operands (char *l, const char *mnemonic)
4284 {
4285 char *token_start;
4286
4287 /* 1 if operand is pending after ','. */
4288 unsigned int expecting_operand = 0;
4289
4290 /* Non-zero if operand parens not balanced. */
4291 unsigned int paren_not_balanced;
4292
4293 while (*l != END_OF_INSN)
4294 {
4295 /* Skip optional white space before operand. */
4296 if (is_space_char (*l))
4297 ++l;
4298 if (!is_operand_char (*l) && *l != END_OF_INSN && *l != '"')
4299 {
4300 as_bad (_("invalid character %s before operand %d"),
4301 output_invalid (*l),
4302 i.operands + 1);
4303 return NULL;
4304 }
4305 token_start = l; /* After white space. */
4306 paren_not_balanced = 0;
4307 while (paren_not_balanced || *l != ',')
4308 {
4309 if (*l == END_OF_INSN)
4310 {
4311 if (paren_not_balanced)
4312 {
4313 if (!intel_syntax)
4314 as_bad (_("unbalanced parenthesis in operand %d."),
4315 i.operands + 1);
4316 else
4317 as_bad (_("unbalanced brackets in operand %d."),
4318 i.operands + 1);
4319 return NULL;
4320 }
4321 else
4322 break; /* we are done */
4323 }
4324 else if (!is_operand_char (*l) && !is_space_char (*l) && *l != '"')
4325 {
4326 as_bad (_("invalid character %s in operand %d"),
4327 output_invalid (*l),
4328 i.operands + 1);
4329 return NULL;
4330 }
4331 if (!intel_syntax)
4332 {
4333 if (*l == '(')
4334 ++paren_not_balanced;
4335 if (*l == ')')
4336 --paren_not_balanced;
4337 }
4338 else
4339 {
4340 if (*l == '[')
4341 ++paren_not_balanced;
4342 if (*l == ']')
4343 --paren_not_balanced;
4344 }
4345 l++;
4346 }
4347 if (l != token_start)
4348 { /* Yes, we've read in another operand. */
4349 unsigned int operand_ok;
4350 this_operand = i.operands++;
4351 if (i.operands > MAX_OPERANDS)
4352 {
4353 as_bad (_("spurious operands; (%d operands/instruction max)"),
4354 MAX_OPERANDS);
4355 return NULL;
4356 }
4357 i.types[this_operand].bitfield.unspecified = 1;
4358 /* Now parse operand adding info to 'i' as we go along. */
4359 END_STRING_AND_SAVE (l);
4360
4361 if (intel_syntax)
4362 operand_ok =
4363 i386_intel_operand (token_start,
4364 intel_float_operand (mnemonic));
4365 else
4366 operand_ok = i386_att_operand (token_start);
4367
4368 RESTORE_END_STRING (l);
4369 if (!operand_ok)
4370 return NULL;
4371 }
4372 else
4373 {
4374 if (expecting_operand)
4375 {
4376 expecting_operand_after_comma:
4377 as_bad (_("expecting operand after ','; got nothing"));
4378 return NULL;
4379 }
4380 if (*l == ',')
4381 {
4382 as_bad (_("expecting operand before ','; got nothing"));
4383 return NULL;
4384 }
4385 }
4386
4387 /* Now *l must be either ',' or END_OF_INSN. */
4388 if (*l == ',')
4389 {
4390 if (*++l == END_OF_INSN)
4391 {
4392 /* Just skip it, if it's \n complain. */
4393 goto expecting_operand_after_comma;
4394 }
4395 expecting_operand = 1;
4396 }
4397 }
4398 return l;
4399 }
4400
4401 static void
4402 swap_2_operands (int xchg1, int xchg2)
4403 {
4404 union i386_op temp_op;
4405 i386_operand_type temp_type;
4406 enum bfd_reloc_code_real temp_reloc;
4407
4408 temp_type = i.types[xchg2];
4409 i.types[xchg2] = i.types[xchg1];
4410 i.types[xchg1] = temp_type;
4411 temp_op = i.op[xchg2];
4412 i.op[xchg2] = i.op[xchg1];
4413 i.op[xchg1] = temp_op;
4414 temp_reloc = i.reloc[xchg2];
4415 i.reloc[xchg2] = i.reloc[xchg1];
4416 i.reloc[xchg1] = temp_reloc;
4417
4418 if (i.mask)
4419 {
4420 if (i.mask->operand == xchg1)
4421 i.mask->operand = xchg2;
4422 else if (i.mask->operand == xchg2)
4423 i.mask->operand = xchg1;
4424 }
4425 if (i.broadcast)
4426 {
4427 if (i.broadcast->operand == xchg1)
4428 i.broadcast->operand = xchg2;
4429 else if (i.broadcast->operand == xchg2)
4430 i.broadcast->operand = xchg1;
4431 }
4432 if (i.rounding)
4433 {
4434 if (i.rounding->operand == xchg1)
4435 i.rounding->operand = xchg2;
4436 else if (i.rounding->operand == xchg2)
4437 i.rounding->operand = xchg1;
4438 }
4439 }
4440
4441 static void
4442 swap_operands (void)
4443 {
4444 switch (i.operands)
4445 {
4446 case 5:
4447 case 4:
4448 swap_2_operands (1, i.operands - 2);
4449 /* Fall through. */
4450 case 3:
4451 case 2:
4452 swap_2_operands (0, i.operands - 1);
4453 break;
4454 default:
4455 abort ();
4456 }
4457
4458 if (i.mem_operands == 2)
4459 {
4460 const seg_entry *temp_seg;
4461 temp_seg = i.seg[0];
4462 i.seg[0] = i.seg[1];
4463 i.seg[1] = temp_seg;
4464 }
4465 }
4466
4467 /* Try to ensure constant immediates are represented in the smallest
4468 opcode possible. */
4469 static void
4470 optimize_imm (void)
4471 {
4472 char guess_suffix = 0;
4473 int op;
4474
4475 if (i.suffix)
4476 guess_suffix = i.suffix;
4477 else if (i.reg_operands)
4478 {
4479 /* Figure out a suffix from the last register operand specified.
4480 We can't do this properly yet, ie. excluding InOutPortReg,
4481 but the following works for instructions with immediates.
4482 In any case, we can't set i.suffix yet. */
4483 for (op = i.operands; --op >= 0;)
4484 if (i.types[op].bitfield.reg && i.types[op].bitfield.byte)
4485 {
4486 guess_suffix = BYTE_MNEM_SUFFIX;
4487 break;
4488 }
4489 else if (i.types[op].bitfield.reg && i.types[op].bitfield.word)
4490 {
4491 guess_suffix = WORD_MNEM_SUFFIX;
4492 break;
4493 }
4494 else if (i.types[op].bitfield.reg && i.types[op].bitfield.dword)
4495 {
4496 guess_suffix = LONG_MNEM_SUFFIX;
4497 break;
4498 }
4499 else if (i.types[op].bitfield.reg && i.types[op].bitfield.qword)
4500 {
4501 guess_suffix = QWORD_MNEM_SUFFIX;
4502 break;
4503 }
4504 }
4505 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
4506 guess_suffix = WORD_MNEM_SUFFIX;
4507
4508 for (op = i.operands; --op >= 0;)
4509 if (operand_type_check (i.types[op], imm))
4510 {
4511 switch (i.op[op].imms->X_op)
4512 {
4513 case O_constant:
4514 /* If a suffix is given, this operand may be shortened. */
4515 switch (guess_suffix)
4516 {
4517 case LONG_MNEM_SUFFIX:
4518 i.types[op].bitfield.imm32 = 1;
4519 i.types[op].bitfield.imm64 = 1;
4520 break;
4521 case WORD_MNEM_SUFFIX:
4522 i.types[op].bitfield.imm16 = 1;
4523 i.types[op].bitfield.imm32 = 1;
4524 i.types[op].bitfield.imm32s = 1;
4525 i.types[op].bitfield.imm64 = 1;
4526 break;
4527 case BYTE_MNEM_SUFFIX:
4528 i.types[op].bitfield.imm8 = 1;
4529 i.types[op].bitfield.imm8s = 1;
4530 i.types[op].bitfield.imm16 = 1;
4531 i.types[op].bitfield.imm32 = 1;
4532 i.types[op].bitfield.imm32s = 1;
4533 i.types[op].bitfield.imm64 = 1;
4534 break;
4535 }
4536
4537 /* If this operand is at most 16 bits, convert it
4538 to a signed 16 bit number before trying to see
4539 whether it will fit in an even smaller size.
4540 This allows a 16-bit operand such as $0xffe0 to
4541 be recognised as within Imm8S range. */
4542 if ((i.types[op].bitfield.imm16)
4543 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
4544 {
4545 i.op[op].imms->X_add_number =
4546 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
4547 }
4548 #ifdef BFD64
4549 /* Store 32-bit immediate in 64-bit for 64-bit BFD. */
4550 if ((i.types[op].bitfield.imm32)
4551 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
4552 == 0))
4553 {
4554 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
4555 ^ ((offsetT) 1 << 31))
4556 - ((offsetT) 1 << 31));
4557 }
4558 #endif
4559 i.types[op]
4560 = operand_type_or (i.types[op],
4561 smallest_imm_type (i.op[op].imms->X_add_number));
4562
4563 /* We must avoid matching of Imm32 templates when 64bit
4564 only immediate is available. */
4565 if (guess_suffix == QWORD_MNEM_SUFFIX)
4566 i.types[op].bitfield.imm32 = 0;
4567 break;
4568
4569 case O_absent:
4570 case O_register:
4571 abort ();
4572
4573 /* Symbols and expressions. */
4574 default:
4575 /* Convert symbolic operand to proper sizes for matching, but don't
4576 prevent matching a set of insns that only supports sizes other
4577 than those matching the insn suffix. */
4578 {
4579 i386_operand_type mask, allowed;
4580 const insn_template *t;
4581
4582 operand_type_set (&mask, 0);
4583 operand_type_set (&allowed, 0);
4584
4585 for (t = current_templates->start;
4586 t < current_templates->end;
4587 ++t)
4588 allowed = operand_type_or (allowed,
4589 t->operand_types[op]);
4590 switch (guess_suffix)
4591 {
4592 case QWORD_MNEM_SUFFIX:
4593 mask.bitfield.imm64 = 1;
4594 mask.bitfield.imm32s = 1;
4595 break;
4596 case LONG_MNEM_SUFFIX:
4597 mask.bitfield.imm32 = 1;
4598 break;
4599 case WORD_MNEM_SUFFIX:
4600 mask.bitfield.imm16 = 1;
4601 break;
4602 case BYTE_MNEM_SUFFIX:
4603 mask.bitfield.imm8 = 1;
4604 break;
4605 default:
4606 break;
4607 }
4608 allowed = operand_type_and (mask, allowed);
4609 if (!operand_type_all_zero (&allowed))
4610 i.types[op] = operand_type_and (i.types[op], mask);
4611 }
4612 break;
4613 }
4614 }
4615 }
4616
4617 /* Try to use the smallest displacement type too. */
4618 static void
4619 optimize_disp (void)
4620 {
4621 int op;
4622
4623 for (op = i.operands; --op >= 0;)
4624 if (operand_type_check (i.types[op], disp))
4625 {
4626 if (i.op[op].disps->X_op == O_constant)
4627 {
4628 offsetT op_disp = i.op[op].disps->X_add_number;
4629
4630 if (i.types[op].bitfield.disp16
4631 && (op_disp & ~(offsetT) 0xffff) == 0)
4632 {
4633 /* If this operand is at most 16 bits, convert
4634 to a signed 16 bit number and don't use 64bit
4635 displacement. */
4636 op_disp = (((op_disp & 0xffff) ^ 0x8000) - 0x8000);
4637 i.types[op].bitfield.disp64 = 0;
4638 }
4639 #ifdef BFD64
4640 /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */
4641 if (i.types[op].bitfield.disp32
4642 && (op_disp & ~(((offsetT) 2 << 31) - 1)) == 0)
4643 {
4644 /* If this operand is at most 32 bits, convert
4645 to a signed 32 bit number and don't use 64bit
4646 displacement. */
4647 op_disp &= (((offsetT) 2 << 31) - 1);
4648 op_disp = (op_disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
4649 i.types[op].bitfield.disp64 = 0;
4650 }
4651 #endif
4652 if (!op_disp && i.types[op].bitfield.baseindex)
4653 {
4654 i.types[op].bitfield.disp8 = 0;
4655 i.types[op].bitfield.disp16 = 0;
4656 i.types[op].bitfield.disp32 = 0;
4657 i.types[op].bitfield.disp32s = 0;
4658 i.types[op].bitfield.disp64 = 0;
4659 i.op[op].disps = 0;
4660 i.disp_operands--;
4661 }
4662 else if (flag_code == CODE_64BIT)
4663 {
4664 if (fits_in_signed_long (op_disp))
4665 {
4666 i.types[op].bitfield.disp64 = 0;
4667 i.types[op].bitfield.disp32s = 1;
4668 }
4669 if (i.prefix[ADDR_PREFIX]
4670 && fits_in_unsigned_long (op_disp))
4671 i.types[op].bitfield.disp32 = 1;
4672 }
4673 if ((i.types[op].bitfield.disp32
4674 || i.types[op].bitfield.disp32s
4675 || i.types[op].bitfield.disp16)
4676 && fits_in_disp8 (op_disp))
4677 i.types[op].bitfield.disp8 = 1;
4678 }
4679 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
4680 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
4681 {
4682 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
4683 i.op[op].disps, 0, i.reloc[op]);
4684 i.types[op].bitfield.disp8 = 0;
4685 i.types[op].bitfield.disp16 = 0;
4686 i.types[op].bitfield.disp32 = 0;
4687 i.types[op].bitfield.disp32s = 0;
4688 i.types[op].bitfield.disp64 = 0;
4689 }
4690 else
4691 /* We only support 64bit displacement on constants. */
4692 i.types[op].bitfield.disp64 = 0;
4693 }
4694 }
4695
4696 /* Check if operands are valid for the instruction. */
4697
4698 static int
4699 check_VecOperands (const insn_template *t)
4700 {
4701 unsigned int op;
4702
4703 /* Without VSIB byte, we can't have a vector register for index. */
4704 if (!t->opcode_modifier.vecsib
4705 && i.index_reg
4706 && (i.index_reg->reg_type.bitfield.xmmword
4707 || i.index_reg->reg_type.bitfield.ymmword
4708 || i.index_reg->reg_type.bitfield.zmmword))
4709 {
4710 i.error = unsupported_vector_index_register;
4711 return 1;
4712 }
4713
4714 /* Check if default mask is allowed. */
4715 if (t->opcode_modifier.nodefmask
4716 && (!i.mask || i.mask->mask->reg_num == 0))
4717 {
4718 i.error = no_default_mask;
4719 return 1;
4720 }
4721
4722 /* For VSIB byte, we need a vector register for index, and all vector
4723 registers must be distinct. */
4724 if (t->opcode_modifier.vecsib)
4725 {
4726 if (!i.index_reg
4727 || !((t->opcode_modifier.vecsib == VecSIB128
4728 && i.index_reg->reg_type.bitfield.xmmword)
4729 || (t->opcode_modifier.vecsib == VecSIB256
4730 && i.index_reg->reg_type.bitfield.ymmword)
4731 || (t->opcode_modifier.vecsib == VecSIB512
4732 && i.index_reg->reg_type.bitfield.zmmword)))
4733 {
4734 i.error = invalid_vsib_address;
4735 return 1;
4736 }
4737
4738 gas_assert (i.reg_operands == 2 || i.mask);
4739 if (i.reg_operands == 2 && !i.mask)
4740 {
4741 gas_assert (i.types[0].bitfield.regsimd);
4742 gas_assert (i.types[0].bitfield.xmmword
4743 || i.types[0].bitfield.ymmword);
4744 gas_assert (i.types[2].bitfield.regsimd);
4745 gas_assert (i.types[2].bitfield.xmmword
4746 || i.types[2].bitfield.ymmword);
4747 if (operand_check == check_none)
4748 return 0;
4749 if (register_number (i.op[0].regs)
4750 != register_number (i.index_reg)
4751 && register_number (i.op[2].regs)
4752 != register_number (i.index_reg)
4753 && register_number (i.op[0].regs)
4754 != register_number (i.op[2].regs))
4755 return 0;
4756 if (operand_check == check_error)
4757 {
4758 i.error = invalid_vector_register_set;
4759 return 1;
4760 }
4761 as_warn (_("mask, index, and destination registers should be distinct"));
4762 }
4763 else if (i.reg_operands == 1 && i.mask)
4764 {
4765 if (i.types[1].bitfield.regsimd
4766 && (i.types[1].bitfield.xmmword
4767 || i.types[1].bitfield.ymmword
4768 || i.types[1].bitfield.zmmword)
4769 && (register_number (i.op[1].regs)
4770 == register_number (i.index_reg)))
4771 {
4772 if (operand_check == check_error)
4773 {
4774 i.error = invalid_vector_register_set;
4775 return 1;
4776 }
4777 if (operand_check != check_none)
4778 as_warn (_("index and destination registers should be distinct"));
4779 }
4780 }
4781 }
4782
4783 /* Check if broadcast is supported by the instruction and is applied
4784 to the memory operand. */
4785 if (i.broadcast)
4786 {
4787 int broadcasted_opnd_size;
4788
4789 /* Check if specified broadcast is supported in this instruction,
4790 and it's applied to memory operand of DWORD or QWORD type,
4791 depending on VecESize. */
4792 if (i.broadcast->type != t->opcode_modifier.broadcast
4793 || !i.types[i.broadcast->operand].bitfield.mem
4794 || (t->opcode_modifier.vecesize == 0
4795 && !i.types[i.broadcast->operand].bitfield.dword
4796 && !i.types[i.broadcast->operand].bitfield.unspecified)
4797 || (t->opcode_modifier.vecesize == 1
4798 && !i.types[i.broadcast->operand].bitfield.qword
4799 && !i.types[i.broadcast->operand].bitfield.unspecified))
4800 goto bad_broadcast;
4801
4802 broadcasted_opnd_size = t->opcode_modifier.vecesize ? 64 : 32;
4803 if (i.broadcast->type == BROADCAST_1TO16)
4804 broadcasted_opnd_size <<= 4; /* Broadcast 1to16. */
4805 else if (i.broadcast->type == BROADCAST_1TO8)
4806 broadcasted_opnd_size <<= 3; /* Broadcast 1to8. */
4807 else if (i.broadcast->type == BROADCAST_1TO4)
4808 broadcasted_opnd_size <<= 2; /* Broadcast 1to4. */
4809 else if (i.broadcast->type == BROADCAST_1TO2)
4810 broadcasted_opnd_size <<= 1; /* Broadcast 1to2. */
4811 else
4812 goto bad_broadcast;
4813
4814 if ((broadcasted_opnd_size == 256
4815 && !t->operand_types[i.broadcast->operand].bitfield.ymmword)
4816 || (broadcasted_opnd_size == 512
4817 && !t->operand_types[i.broadcast->operand].bitfield.zmmword))
4818 {
4819 bad_broadcast:
4820 i.error = unsupported_broadcast;
4821 return 1;
4822 }
4823 }
4824 /* If broadcast is supported in this instruction, we need to check if
4825 operand of one-element size isn't specified without broadcast. */
4826 else if (t->opcode_modifier.broadcast && i.mem_operands)
4827 {
4828 /* Find memory operand. */
4829 for (op = 0; op < i.operands; op++)
4830 if (operand_type_check (i.types[op], anymem))
4831 break;
4832 gas_assert (op < i.operands);
4833 /* Check size of the memory operand. */
4834 if ((t->opcode_modifier.vecesize == 0
4835 && i.types[op].bitfield.dword)
4836 || (t->opcode_modifier.vecesize == 1
4837 && i.types[op].bitfield.qword))
4838 {
4839 i.error = broadcast_needed;
4840 return 1;
4841 }
4842 }
4843
4844 /* Check if requested masking is supported. */
4845 if (i.mask
4846 && (!t->opcode_modifier.masking
4847 || (i.mask->zeroing
4848 && t->opcode_modifier.masking == MERGING_MASKING)))
4849 {
4850 i.error = unsupported_masking;
4851 return 1;
4852 }
4853
4854 /* Check if masking is applied to dest operand. */
4855 if (i.mask && (i.mask->operand != (int) (i.operands - 1)))
4856 {
4857 i.error = mask_not_on_destination;
4858 return 1;
4859 }
4860
4861 /* Check RC/SAE. */
4862 if (i.rounding)
4863 {
4864 if ((i.rounding->type != saeonly
4865 && !t->opcode_modifier.staticrounding)
4866 || (i.rounding->type == saeonly
4867 && (t->opcode_modifier.staticrounding
4868 || !t->opcode_modifier.sae)))
4869 {
4870 i.error = unsupported_rc_sae;
4871 return 1;
4872 }
4873 /* If the instruction has several immediate operands and one of
4874 them is rounding, the rounding operand should be the last
4875 immediate operand. */
4876 if (i.imm_operands > 1
4877 && i.rounding->operand != (int) (i.imm_operands - 1))
4878 {
4879 i.error = rc_sae_operand_not_last_imm;
4880 return 1;
4881 }
4882 }
4883
4884 /* Check vector Disp8 operand. */
4885 if (t->opcode_modifier.disp8memshift
4886 && i.disp_encoding != disp_encoding_32bit)
4887 {
4888 if (i.broadcast)
4889 i.memshift = t->opcode_modifier.vecesize ? 3 : 2;
4890 else
4891 i.memshift = t->opcode_modifier.disp8memshift;
4892
4893 for (op = 0; op < i.operands; op++)
4894 if (operand_type_check (i.types[op], disp)
4895 && i.op[op].disps->X_op == O_constant)
4896 {
4897 if (fits_in_disp8 (i.op[op].disps->X_add_number))
4898 {
4899 i.types[op].bitfield.disp8 = 1;
4900 return 0;
4901 }
4902 i.types[op].bitfield.disp8 = 0;
4903 }
4904 }
4905
4906 i.memshift = 0;
4907
4908 return 0;
4909 }
4910
4911 /* Check if operands are valid for the instruction. Update VEX
4912 operand types. */
4913
4914 static int
4915 VEX_check_operands (const insn_template *t)
4916 {
4917 if (i.vec_encoding == vex_encoding_evex)
4918 {
4919 /* This instruction must be encoded with EVEX prefix. */
4920 if (!t->opcode_modifier.evex)
4921 {
4922 i.error = unsupported;
4923 return 1;
4924 }
4925 return 0;
4926 }
4927
4928 if (!t->opcode_modifier.vex)
4929 {
4930 /* This instruction template doesn't have VEX prefix. */
4931 if (i.vec_encoding != vex_encoding_default)
4932 {
4933 i.error = unsupported;
4934 return 1;
4935 }
4936 return 0;
4937 }
4938
4939 /* Only check VEX_Imm4, which must be the first operand. */
4940 if (t->operand_types[0].bitfield.vec_imm4)
4941 {
4942 if (i.op[0].imms->X_op != O_constant
4943 || !fits_in_imm4 (i.op[0].imms->X_add_number))
4944 {
4945 i.error = bad_imm4;
4946 return 1;
4947 }
4948
4949 /* Turn off Imm8 so that update_imm won't complain. */
4950 i.types[0] = vec_imm4;
4951 }
4952
4953 return 0;
4954 }
4955
4956 static const insn_template *
4957 match_template (char mnem_suffix)
4958 {
4959 /* Points to template once we've found it. */
4960 const insn_template *t;
4961 i386_operand_type overlap0, overlap1, overlap2, overlap3;
4962 i386_operand_type overlap4;
4963 unsigned int found_reverse_match;
4964 i386_opcode_modifier suffix_check, mnemsuf_check;
4965 i386_operand_type operand_types [MAX_OPERANDS];
4966 int addr_prefix_disp;
4967 unsigned int j;
4968 unsigned int found_cpu_match;
4969 unsigned int check_register;
4970 enum i386_error specific_error = 0;
4971
4972 #if MAX_OPERANDS != 5
4973 # error "MAX_OPERANDS must be 5."
4974 #endif
4975
4976 found_reverse_match = 0;
4977 addr_prefix_disp = -1;
4978
4979 memset (&suffix_check, 0, sizeof (suffix_check));
4980 if (i.suffix == BYTE_MNEM_SUFFIX)
4981 suffix_check.no_bsuf = 1;
4982 else if (i.suffix == WORD_MNEM_SUFFIX)
4983 suffix_check.no_wsuf = 1;
4984 else if (i.suffix == SHORT_MNEM_SUFFIX)
4985 suffix_check.no_ssuf = 1;
4986 else if (i.suffix == LONG_MNEM_SUFFIX)
4987 suffix_check.no_lsuf = 1;
4988 else if (i.suffix == QWORD_MNEM_SUFFIX)
4989 suffix_check.no_qsuf = 1;
4990 else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX)
4991 suffix_check.no_ldsuf = 1;
4992
4993 memset (&mnemsuf_check, 0, sizeof (mnemsuf_check));
4994 if (intel_syntax)
4995 {
4996 switch (mnem_suffix)
4997 {
4998 case BYTE_MNEM_SUFFIX: mnemsuf_check.no_bsuf = 1; break;
4999 case WORD_MNEM_SUFFIX: mnemsuf_check.no_wsuf = 1; break;
5000 case SHORT_MNEM_SUFFIX: mnemsuf_check.no_ssuf = 1; break;
5001 case LONG_MNEM_SUFFIX: mnemsuf_check.no_lsuf = 1; break;
5002 case QWORD_MNEM_SUFFIX: mnemsuf_check.no_qsuf = 1; break;
5003 }
5004 }
5005
5006 /* Must have right number of operands. */
5007 i.error = number_of_operands_mismatch;
5008
5009 for (t = current_templates->start; t < current_templates->end; t++)
5010 {
5011 addr_prefix_disp = -1;
5012
5013 if (i.operands != t->operands)
5014 continue;
5015
5016 /* Check processor support. */
5017 i.error = unsupported;
5018 found_cpu_match = (cpu_flags_match (t)
5019 == CPU_FLAGS_PERFECT_MATCH);
5020 if (!found_cpu_match)
5021 continue;
5022
5023 /* Check old gcc support. */
5024 i.error = old_gcc_only;
5025 if (!old_gcc && t->opcode_modifier.oldgcc)
5026 continue;
5027
5028 /* Check AT&T mnemonic. */
5029 i.error = unsupported_with_intel_mnemonic;
5030 if (intel_mnemonic && t->opcode_modifier.attmnemonic)
5031 continue;
5032
5033 /* Check AT&T/Intel syntax and Intel64/AMD64 ISA. */
5034 i.error = unsupported_syntax;
5035 if ((intel_syntax && t->opcode_modifier.attsyntax)
5036 || (!intel_syntax && t->opcode_modifier.intelsyntax)
5037 || (intel64 && t->opcode_modifier.amd64)
5038 || (!intel64 && t->opcode_modifier.intel64))
5039 continue;
5040
5041 /* Check the suffix, except for some instructions in intel mode. */
5042 i.error = invalid_instruction_suffix;
5043 if ((!intel_syntax || !t->opcode_modifier.ignoresize)
5044 && ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf)
5045 || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf)
5046 || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf)
5047 || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf)
5048 || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf)
5049 || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf)))
5050 continue;
5051 /* In Intel mode all mnemonic suffixes must be explicitly allowed. */
5052 if ((t->opcode_modifier.no_bsuf && mnemsuf_check.no_bsuf)
5053 || (t->opcode_modifier.no_wsuf && mnemsuf_check.no_wsuf)
5054 || (t->opcode_modifier.no_lsuf && mnemsuf_check.no_lsuf)
5055 || (t->opcode_modifier.no_ssuf && mnemsuf_check.no_ssuf)
5056 || (t->opcode_modifier.no_qsuf && mnemsuf_check.no_qsuf)
5057 || (t->opcode_modifier.no_ldsuf && mnemsuf_check.no_ldsuf))
5058 continue;
5059
5060 if (!operand_size_match (t))
5061 continue;
5062
5063 for (j = 0; j < MAX_OPERANDS; j++)
5064 operand_types[j] = t->operand_types[j];
5065
5066 /* In general, don't allow 64-bit operands in 32-bit mode. */
5067 if (i.suffix == QWORD_MNEM_SUFFIX
5068 && flag_code != CODE_64BIT
5069 && (intel_syntax
5070 ? (!t->opcode_modifier.ignoresize
5071 && !intel_float_operand (t->name))
5072 : intel_float_operand (t->name) != 2)
5073 && ((!operand_types[0].bitfield.regmmx
5074 && !operand_types[0].bitfield.regsimd)
5075 || (!operand_types[t->operands > 1].bitfield.regmmx
5076 && !operand_types[t->operands > 1].bitfield.regsimd))
5077 && (t->base_opcode != 0x0fc7
5078 || t->extension_opcode != 1 /* cmpxchg8b */))
5079 continue;
5080
5081 /* In general, don't allow 32-bit operands on pre-386. */
5082 else if (i.suffix == LONG_MNEM_SUFFIX
5083 && !cpu_arch_flags.bitfield.cpui386
5084 && (intel_syntax
5085 ? (!t->opcode_modifier.ignoresize
5086 && !intel_float_operand (t->name))
5087 : intel_float_operand (t->name) != 2)
5088 && ((!operand_types[0].bitfield.regmmx
5089 && !operand_types[0].bitfield.regsimd)
5090 || (!operand_types[t->operands > 1].bitfield.regmmx
5091 && !operand_types[t->operands > 1].bitfield.regsimd)))
5092 continue;
5093
5094 /* Do not verify operands when there are none. */
5095 else
5096 {
5097 if (!t->operands)
5098 /* We've found a match; break out of loop. */
5099 break;
5100 }
5101
5102 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
5103 into Disp32/Disp16/Disp32 operand. */
5104 if (i.prefix[ADDR_PREFIX] != 0)
5105 {
5106 /* There should be only one Disp operand. */
5107 switch (flag_code)
5108 {
5109 case CODE_16BIT:
5110 for (j = 0; j < MAX_OPERANDS; j++)
5111 {
5112 if (operand_types[j].bitfield.disp16)
5113 {
5114 addr_prefix_disp = j;
5115 operand_types[j].bitfield.disp32 = 1;
5116 operand_types[j].bitfield.disp16 = 0;
5117 break;
5118 }
5119 }
5120 break;
5121 case CODE_32BIT:
5122 for (j = 0; j < MAX_OPERANDS; j++)
5123 {
5124 if (operand_types[j].bitfield.disp32)
5125 {
5126 addr_prefix_disp = j;
5127 operand_types[j].bitfield.disp32 = 0;
5128 operand_types[j].bitfield.disp16 = 1;
5129 break;
5130 }
5131 }
5132 break;
5133 case CODE_64BIT:
5134 for (j = 0; j < MAX_OPERANDS; j++)
5135 {
5136 if (operand_types[j].bitfield.disp64)
5137 {
5138 addr_prefix_disp = j;
5139 operand_types[j].bitfield.disp64 = 0;
5140 operand_types[j].bitfield.disp32 = 1;
5141 break;
5142 }
5143 }
5144 break;
5145 }
5146 }
5147
5148 /* Force 0x8b encoding for "mov foo@GOT, %eax". */
5149 if (i.reloc[0] == BFD_RELOC_386_GOT32 && t->base_opcode == 0xa0)
5150 continue;
5151
5152 /* We check register size if needed. */
5153 check_register = t->opcode_modifier.checkregsize;
5154 overlap0 = operand_type_and (i.types[0], operand_types[0]);
5155 switch (t->operands)
5156 {
5157 case 1:
5158 if (!operand_type_match (overlap0, i.types[0]))
5159 continue;
5160 break;
5161 case 2:
5162 /* xchg %eax, %eax is a special case. It is an alias for nop
5163 only in 32bit mode and we can use opcode 0x90. In 64bit
5164 mode, we can't use 0x90 for xchg %eax, %eax since it should
5165 zero-extend %eax to %rax. */
5166 if (flag_code == CODE_64BIT
5167 && t->base_opcode == 0x90
5168 && operand_type_equal (&i.types [0], &acc32)
5169 && operand_type_equal (&i.types [1], &acc32))
5170 continue;
5171 /* If we want store form, we reverse direction of operands. */
5172 if (i.dir_encoding == dir_encoding_store
5173 && t->opcode_modifier.d)
5174 goto check_reverse;
5175 /* Fall through. */
5176
5177 case 3:
5178 /* If we want store form, we skip the current load. */
5179 if (i.dir_encoding == dir_encoding_store
5180 && i.mem_operands == 0
5181 && t->opcode_modifier.load)
5182 continue;
5183 /* Fall through. */
5184 case 4:
5185 case 5:
5186 overlap1 = operand_type_and (i.types[1], operand_types[1]);
5187 if (!operand_type_match (overlap0, i.types[0])
5188 || !operand_type_match (overlap1, i.types[1])
5189 || (check_register
5190 && !operand_type_register_match (i.types[0],
5191 operand_types[0],
5192 i.types[1],
5193 operand_types[1])))
5194 {
5195 /* Check if other direction is valid ... */
5196 if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
5197 continue;
5198
5199 check_reverse:
5200 /* Try reversing direction of operands. */
5201 overlap0 = operand_type_and (i.types[0], operand_types[1]);
5202 overlap1 = operand_type_and (i.types[1], operand_types[0]);
5203 if (!operand_type_match (overlap0, i.types[0])
5204 || !operand_type_match (overlap1, i.types[1])
5205 || (check_register
5206 && !operand_type_register_match (i.types[0],
5207 operand_types[1],
5208 i.types[1],
5209 operand_types[0])))
5210 {
5211 /* Does not match either direction. */
5212 continue;
5213 }
5214 /* found_reverse_match holds which of D or FloatDR
5215 we've found. */
5216 if (t->opcode_modifier.d)
5217 found_reverse_match = Opcode_D;
5218 else if (t->opcode_modifier.floatd)
5219 found_reverse_match = Opcode_FloatD;
5220 else
5221 found_reverse_match = 0;
5222 if (t->opcode_modifier.floatr)
5223 found_reverse_match |= Opcode_FloatR;
5224 }
5225 else
5226 {
5227 /* Found a forward 2 operand match here. */
5228 switch (t->operands)
5229 {
5230 case 5:
5231 overlap4 = operand_type_and (i.types[4],
5232 operand_types[4]);
5233 /* Fall through. */
5234 case 4:
5235 overlap3 = operand_type_and (i.types[3],
5236 operand_types[3]);
5237 /* Fall through. */
5238 case 3:
5239 overlap2 = operand_type_and (i.types[2],
5240 operand_types[2]);
5241 break;
5242 }
5243
5244 switch (t->operands)
5245 {
5246 case 5:
5247 if (!operand_type_match (overlap4, i.types[4])
5248 || !operand_type_register_match (i.types[3],
5249 operand_types[3],
5250 i.types[4],
5251 operand_types[4]))
5252 continue;
5253 /* Fall through. */
5254 case 4:
5255 if (!operand_type_match (overlap3, i.types[3])
5256 || (check_register
5257 && !operand_type_register_match (i.types[2],
5258 operand_types[2],
5259 i.types[3],
5260 operand_types[3])))
5261 continue;
5262 /* Fall through. */
5263 case 3:
5264 /* Here we make use of the fact that there are no
5265 reverse match 3 operand instructions, and all 3
5266 operand instructions only need to be checked for
5267 register consistency between operands 2 and 3. */
5268 if (!operand_type_match (overlap2, i.types[2])
5269 || (check_register
5270 && !operand_type_register_match (i.types[1],
5271 operand_types[1],
5272 i.types[2],
5273 operand_types[2])))
5274 continue;
5275 break;
5276 }
5277 }
5278 /* Found either forward/reverse 2, 3 or 4 operand match here:
5279 slip through to break. */
5280 }
5281 if (!found_cpu_match)
5282 {
5283 found_reverse_match = 0;
5284 continue;
5285 }
5286
5287 /* Check if vector and VEX operands are valid. */
5288 if (check_VecOperands (t) || VEX_check_operands (t))
5289 {
5290 specific_error = i.error;
5291 continue;
5292 }
5293
5294 /* We've found a match; break out of loop. */
5295 break;
5296 }
5297
5298 if (t == current_templates->end)
5299 {
5300 /* We found no match. */
5301 const char *err_msg;
5302 switch (specific_error ? specific_error : i.error)
5303 {
5304 default:
5305 abort ();
5306 case operand_size_mismatch:
5307 err_msg = _("operand size mismatch");
5308 break;
5309 case operand_type_mismatch:
5310 err_msg = _("operand type mismatch");
5311 break;
5312 case register_type_mismatch:
5313 err_msg = _("register type mismatch");
5314 break;
5315 case number_of_operands_mismatch:
5316 err_msg = _("number of operands mismatch");
5317 break;
5318 case invalid_instruction_suffix:
5319 err_msg = _("invalid instruction suffix");
5320 break;
5321 case bad_imm4:
5322 err_msg = _("constant doesn't fit in 4 bits");
5323 break;
5324 case old_gcc_only:
5325 err_msg = _("only supported with old gcc");
5326 break;
5327 case unsupported_with_intel_mnemonic:
5328 err_msg = _("unsupported with Intel mnemonic");
5329 break;
5330 case unsupported_syntax:
5331 err_msg = _("unsupported syntax");
5332 break;
5333 case unsupported:
5334 as_bad (_("unsupported instruction `%s'"),
5335 current_templates->start->name);
5336 return NULL;
5337 case invalid_vsib_address:
5338 err_msg = _("invalid VSIB address");
5339 break;
5340 case invalid_vector_register_set:
5341 err_msg = _("mask, index, and destination registers must be distinct");
5342 break;
5343 case unsupported_vector_index_register:
5344 err_msg = _("unsupported vector index register");
5345 break;
5346 case unsupported_broadcast:
5347 err_msg = _("unsupported broadcast");
5348 break;
5349 case broadcast_not_on_src_operand:
5350 err_msg = _("broadcast not on source memory operand");
5351 break;
5352 case broadcast_needed:
5353 err_msg = _("broadcast is needed for operand of such type");
5354 break;
5355 case unsupported_masking:
5356 err_msg = _("unsupported masking");
5357 break;
5358 case mask_not_on_destination:
5359 err_msg = _("mask not on destination operand");
5360 break;
5361 case no_default_mask:
5362 err_msg = _("default mask isn't allowed");
5363 break;
5364 case unsupported_rc_sae:
5365 err_msg = _("unsupported static rounding/sae");
5366 break;
5367 case rc_sae_operand_not_last_imm:
5368 if (intel_syntax)
5369 err_msg = _("RC/SAE operand must precede immediate operands");
5370 else
5371 err_msg = _("RC/SAE operand must follow immediate operands");
5372 break;
5373 case invalid_register_operand:
5374 err_msg = _("invalid register operand");
5375 break;
5376 }
5377 as_bad (_("%s for `%s'"), err_msg,
5378 current_templates->start->name);
5379 return NULL;
5380 }
5381
5382 if (!quiet_warnings)
5383 {
5384 if (!intel_syntax
5385 && (i.types[0].bitfield.jumpabsolute
5386 != operand_types[0].bitfield.jumpabsolute))
5387 {
5388 as_warn (_("indirect %s without `*'"), t->name);
5389 }
5390
5391 if (t->opcode_modifier.isprefix
5392 && t->opcode_modifier.ignoresize)
5393 {
5394 /* Warn them that a data or address size prefix doesn't
5395 affect assembly of the next line of code. */
5396 as_warn (_("stand-alone `%s' prefix"), t->name);
5397 }
5398 }
5399
5400 /* Copy the template we found. */
5401 i.tm = *t;
5402
5403 if (addr_prefix_disp != -1)
5404 i.tm.operand_types[addr_prefix_disp]
5405 = operand_types[addr_prefix_disp];
5406
5407 if (found_reverse_match)
5408 {
5409 /* If we found a reverse match we must alter the opcode
5410 direction bit. found_reverse_match holds bits to change
5411 (different for int & float insns). */
5412
5413 i.tm.base_opcode ^= found_reverse_match;
5414
5415 i.tm.operand_types[0] = operand_types[1];
5416 i.tm.operand_types[1] = operand_types[0];
5417 }
5418
5419 return t;
5420 }
5421
5422 static int
5423 check_string (void)
5424 {
5425 int mem_op = operand_type_check (i.types[0], anymem) ? 0 : 1;
5426 if (i.tm.operand_types[mem_op].bitfield.esseg)
5427 {
5428 if (i.seg[0] != NULL && i.seg[0] != &es)
5429 {
5430 as_bad (_("`%s' operand %d must use `%ses' segment"),
5431 i.tm.name,
5432 mem_op + 1,
5433 register_prefix);
5434 return 0;
5435 }
5436 /* There's only ever one segment override allowed per instruction.
5437 This instruction possibly has a legal segment override on the
5438 second operand, so copy the segment to where non-string
5439 instructions store it, allowing common code. */
5440 i.seg[0] = i.seg[1];
5441 }
5442 else if (i.tm.operand_types[mem_op + 1].bitfield.esseg)
5443 {
5444 if (i.seg[1] != NULL && i.seg[1] != &es)
5445 {
5446 as_bad (_("`%s' operand %d must use `%ses' segment"),
5447 i.tm.name,
5448 mem_op + 2,
5449 register_prefix);
5450 return 0;
5451 }
5452 }
5453 return 1;
5454 }
5455
5456 static int
5457 process_suffix (void)
5458 {
5459 /* If matched instruction specifies an explicit instruction mnemonic
5460 suffix, use it. */
5461 if (i.tm.opcode_modifier.size16)
5462 i.suffix = WORD_MNEM_SUFFIX;
5463 else if (i.tm.opcode_modifier.size32)
5464 i.suffix = LONG_MNEM_SUFFIX;
5465 else if (i.tm.opcode_modifier.size64)
5466 i.suffix = QWORD_MNEM_SUFFIX;
5467 else if (i.reg_operands)
5468 {
5469 /* If there's no instruction mnemonic suffix we try to invent one
5470 based on register operands. */
5471 if (!i.suffix)
5472 {
5473 /* We take i.suffix from the last register operand specified,
5474 Destination register type is more significant than source
5475 register type. crc32 in SSE4.2 prefers source register
5476 type. */
5477 if (i.tm.base_opcode == 0xf20f38f1)
5478 {
5479 if (i.types[0].bitfield.reg && i.types[0].bitfield.word)
5480 i.suffix = WORD_MNEM_SUFFIX;
5481 else if (i.types[0].bitfield.reg && i.types[0].bitfield.dword)
5482 i.suffix = LONG_MNEM_SUFFIX;
5483 else if (i.types[0].bitfield.reg && i.types[0].bitfield.qword)
5484 i.suffix = QWORD_MNEM_SUFFIX;
5485 }
5486 else if (i.tm.base_opcode == 0xf20f38f0)
5487 {
5488 if (i.types[0].bitfield.reg && i.types[0].bitfield.byte)
5489 i.suffix = BYTE_MNEM_SUFFIX;
5490 }
5491
5492 if (!i.suffix)
5493 {
5494 int op;
5495
5496 if (i.tm.base_opcode == 0xf20f38f1
5497 || i.tm.base_opcode == 0xf20f38f0)
5498 {
5499 /* We have to know the operand size for crc32. */
5500 as_bad (_("ambiguous memory operand size for `%s`"),
5501 i.tm.name);
5502 return 0;
5503 }
5504
5505 for (op = i.operands; --op >= 0;)
5506 if (!i.tm.operand_types[op].bitfield.inoutportreg
5507 && !i.tm.operand_types[op].bitfield.shiftcount)
5508 {
5509 if (i.types[op].bitfield.reg && i.types[op].bitfield.byte)
5510 {
5511 i.suffix = BYTE_MNEM_SUFFIX;
5512 break;
5513 }
5514 if (i.types[op].bitfield.reg && i.types[op].bitfield.word)
5515 {
5516 i.suffix = WORD_MNEM_SUFFIX;
5517 break;
5518 }
5519 if (i.types[op].bitfield.reg && i.types[op].bitfield.dword)
5520 {
5521 i.suffix = LONG_MNEM_SUFFIX;
5522 break;
5523 }
5524 if (i.types[op].bitfield.reg && i.types[op].bitfield.qword)
5525 {
5526 i.suffix = QWORD_MNEM_SUFFIX;
5527 break;
5528 }
5529 }
5530 }
5531 }
5532 else if (i.suffix == BYTE_MNEM_SUFFIX)
5533 {
5534 if (intel_syntax
5535 && i.tm.opcode_modifier.ignoresize
5536 && i.tm.opcode_modifier.no_bsuf)
5537 i.suffix = 0;
5538 else if (!check_byte_reg ())
5539 return 0;
5540 }
5541 else if (i.suffix == LONG_MNEM_SUFFIX)
5542 {
5543 if (intel_syntax
5544 && i.tm.opcode_modifier.ignoresize
5545 && i.tm.opcode_modifier.no_lsuf)
5546 i.suffix = 0;
5547 else if (!check_long_reg ())
5548 return 0;
5549 }
5550 else if (i.suffix == QWORD_MNEM_SUFFIX)
5551 {
5552 if (intel_syntax
5553 && i.tm.opcode_modifier.ignoresize
5554 && i.tm.opcode_modifier.no_qsuf)
5555 i.suffix = 0;
5556 else if (!check_qword_reg ())
5557 return 0;
5558 }
5559 else if (i.suffix == WORD_MNEM_SUFFIX)
5560 {
5561 if (intel_syntax
5562 && i.tm.opcode_modifier.ignoresize
5563 && i.tm.opcode_modifier.no_wsuf)
5564 i.suffix = 0;
5565 else if (!check_word_reg ())
5566 return 0;
5567 }
5568 else if (i.suffix == XMMWORD_MNEM_SUFFIX
5569 || i.suffix == YMMWORD_MNEM_SUFFIX
5570 || i.suffix == ZMMWORD_MNEM_SUFFIX)
5571 {
5572 /* Skip if the instruction has x/y/z suffix. match_template
5573 should check if it is a valid suffix. */
5574 }
5575 else if (intel_syntax && i.tm.opcode_modifier.ignoresize)
5576 /* Do nothing if the instruction is going to ignore the prefix. */
5577 ;
5578 else
5579 abort ();
5580 }
5581 else if (i.tm.opcode_modifier.defaultsize
5582 && !i.suffix
5583 /* exclude fldenv/frstor/fsave/fstenv */
5584 && i.tm.opcode_modifier.no_ssuf)
5585 {
5586 i.suffix = stackop_size;
5587 }
5588 else if (intel_syntax
5589 && !i.suffix
5590 && (i.tm.operand_types[0].bitfield.jumpabsolute
5591 || i.tm.opcode_modifier.jumpbyte
5592 || i.tm.opcode_modifier.jumpintersegment
5593 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
5594 && i.tm.extension_opcode <= 3)))
5595 {
5596 switch (flag_code)
5597 {
5598 case CODE_64BIT:
5599 if (!i.tm.opcode_modifier.no_qsuf)
5600 {
5601 i.suffix = QWORD_MNEM_SUFFIX;
5602 break;
5603 }
5604 /* Fall through. */
5605 case CODE_32BIT:
5606 if (!i.tm.opcode_modifier.no_lsuf)
5607 i.suffix = LONG_MNEM_SUFFIX;
5608 break;
5609 case CODE_16BIT:
5610 if (!i.tm.opcode_modifier.no_wsuf)
5611 i.suffix = WORD_MNEM_SUFFIX;
5612 break;
5613 }
5614 }
5615
5616 if (!i.suffix)
5617 {
5618 if (!intel_syntax)
5619 {
5620 if (i.tm.opcode_modifier.w)
5621 {
5622 as_bad (_("no instruction mnemonic suffix given and "
5623 "no register operands; can't size instruction"));
5624 return 0;
5625 }
5626 }
5627 else
5628 {
5629 unsigned int suffixes;
5630
5631 suffixes = !i.tm.opcode_modifier.no_bsuf;
5632 if (!i.tm.opcode_modifier.no_wsuf)
5633 suffixes |= 1 << 1;
5634 if (!i.tm.opcode_modifier.no_lsuf)
5635 suffixes |= 1 << 2;
5636 if (!i.tm.opcode_modifier.no_ldsuf)
5637 suffixes |= 1 << 3;
5638 if (!i.tm.opcode_modifier.no_ssuf)
5639 suffixes |= 1 << 4;
5640 if (flag_code == CODE_64BIT && !i.tm.opcode_modifier.no_qsuf)
5641 suffixes |= 1 << 5;
5642
5643 /* There are more than suffix matches. */
5644 if (i.tm.opcode_modifier.w
5645 || ((suffixes & (suffixes - 1))
5646 && !i.tm.opcode_modifier.defaultsize
5647 && !i.tm.opcode_modifier.ignoresize))
5648 {
5649 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
5650 return 0;
5651 }
5652 }
5653 }
5654
5655 /* Change the opcode based on the operand size given by i.suffix;
5656 We don't need to change things for byte insns. */
5657
5658 if (i.suffix
5659 && i.suffix != BYTE_MNEM_SUFFIX
5660 && i.suffix != XMMWORD_MNEM_SUFFIX
5661 && i.suffix != YMMWORD_MNEM_SUFFIX
5662 && i.suffix != ZMMWORD_MNEM_SUFFIX)
5663 {
5664 /* It's not a byte, select word/dword operation. */
5665 if (i.tm.opcode_modifier.w)
5666 {
5667 if (i.tm.opcode_modifier.shortform)
5668 i.tm.base_opcode |= 8;
5669 else
5670 i.tm.base_opcode |= 1;
5671 }
5672
5673 /* Now select between word & dword operations via the operand
5674 size prefix, except for instructions that will ignore this
5675 prefix anyway. */
5676 if (i.tm.opcode_modifier.addrprefixop0)
5677 {
5678 /* The address size override prefix changes the size of the
5679 first operand. */
5680 if ((flag_code == CODE_32BIT
5681 && i.op->regs[0].reg_type.bitfield.word)
5682 || (flag_code != CODE_32BIT
5683 && i.op->regs[0].reg_type.bitfield.dword))
5684 if (!add_prefix (ADDR_PREFIX_OPCODE))
5685 return 0;
5686 }
5687 else if (i.suffix != QWORD_MNEM_SUFFIX
5688 && i.suffix != LONG_DOUBLE_MNEM_SUFFIX
5689 && !i.tm.opcode_modifier.ignoresize
5690 && !i.tm.opcode_modifier.floatmf
5691 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
5692 || (flag_code == CODE_64BIT
5693 && i.tm.opcode_modifier.jumpbyte)))
5694 {
5695 unsigned int prefix = DATA_PREFIX_OPCODE;
5696
5697 if (i.tm.opcode_modifier.jumpbyte) /* jcxz, loop */
5698 prefix = ADDR_PREFIX_OPCODE;
5699
5700 if (!add_prefix (prefix))
5701 return 0;
5702 }
5703
5704 /* Set mode64 for an operand. */
5705 if (i.suffix == QWORD_MNEM_SUFFIX
5706 && flag_code == CODE_64BIT
5707 && !i.tm.opcode_modifier.norex64)
5708 {
5709 /* Special case for xchg %rax,%rax. It is NOP and doesn't
5710 need rex64. cmpxchg8b is also a special case. */
5711 if (! (i.operands == 2
5712 && i.tm.base_opcode == 0x90
5713 && i.tm.extension_opcode == None
5714 && operand_type_equal (&i.types [0], &acc64)
5715 && operand_type_equal (&i.types [1], &acc64))
5716 && ! (i.operands == 1
5717 && i.tm.base_opcode == 0xfc7
5718 && i.tm.extension_opcode == 1
5719 && !operand_type_check (i.types [0], reg)
5720 && operand_type_check (i.types [0], anymem)))
5721 i.rex |= REX_W;
5722 }
5723
5724 /* Size floating point instruction. */
5725 if (i.suffix == LONG_MNEM_SUFFIX)
5726 if (i.tm.opcode_modifier.floatmf)
5727 i.tm.base_opcode ^= 4;
5728 }
5729
5730 return 1;
5731 }
5732
5733 static int
5734 check_byte_reg (void)
5735 {
5736 int op;
5737
5738 for (op = i.operands; --op >= 0;)
5739 {
5740 /* Skip non-register operands. */
5741 if (!i.types[op].bitfield.reg)
5742 continue;
5743
5744 /* If this is an eight bit register, it's OK. If it's the 16 or
5745 32 bit version of an eight bit register, we will just use the
5746 low portion, and that's OK too. */
5747 if (i.types[op].bitfield.byte)
5748 continue;
5749
5750 /* I/O port address operands are OK too. */
5751 if (i.tm.operand_types[op].bitfield.inoutportreg)
5752 continue;
5753
5754 /* crc32 doesn't generate this warning. */
5755 if (i.tm.base_opcode == 0xf20f38f0)
5756 continue;
5757
5758 if ((i.types[op].bitfield.word
5759 || i.types[op].bitfield.dword
5760 || i.types[op].bitfield.qword)
5761 && i.op[op].regs->reg_num < 4
5762 /* Prohibit these changes in 64bit mode, since the lowering
5763 would be more complicated. */
5764 && flag_code != CODE_64BIT)
5765 {
5766 #if REGISTER_WARNINGS
5767 if (!quiet_warnings)
5768 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5769 register_prefix,
5770 (i.op[op].regs + (i.types[op].bitfield.word
5771 ? REGNAM_AL - REGNAM_AX
5772 : REGNAM_AL - REGNAM_EAX))->reg_name,
5773 register_prefix,
5774 i.op[op].regs->reg_name,
5775 i.suffix);
5776 #endif
5777 continue;
5778 }
5779 /* Any other register is bad. */
5780 if (i.types[op].bitfield.reg
5781 || i.types[op].bitfield.regmmx
5782 || i.types[op].bitfield.regsimd
5783 || i.types[op].bitfield.sreg2
5784 || i.types[op].bitfield.sreg3
5785 || i.types[op].bitfield.control
5786 || i.types[op].bitfield.debug
5787 || i.types[op].bitfield.test)
5788 {
5789 as_bad (_("`%s%s' not allowed with `%s%c'"),
5790 register_prefix,
5791 i.op[op].regs->reg_name,
5792 i.tm.name,
5793 i.suffix);
5794 return 0;
5795 }
5796 }
5797 return 1;
5798 }
5799
5800 static int
5801 check_long_reg (void)
5802 {
5803 int op;
5804
5805 for (op = i.operands; --op >= 0;)
5806 /* Skip non-register operands. */
5807 if (!i.types[op].bitfield.reg)
5808 continue;
5809 /* Reject eight bit registers, except where the template requires
5810 them. (eg. movzb) */
5811 else if (i.types[op].bitfield.byte
5812 && (i.tm.operand_types[op].bitfield.reg
5813 || i.tm.operand_types[op].bitfield.acc)
5814 && (i.tm.operand_types[op].bitfield.word
5815 || i.tm.operand_types[op].bitfield.dword))
5816 {
5817 as_bad (_("`%s%s' not allowed with `%s%c'"),
5818 register_prefix,
5819 i.op[op].regs->reg_name,
5820 i.tm.name,
5821 i.suffix);
5822 return 0;
5823 }
5824 /* Warn if the e prefix on a general reg is missing. */
5825 else if ((!quiet_warnings || flag_code == CODE_64BIT)
5826 && i.types[op].bitfield.word
5827 && (i.tm.operand_types[op].bitfield.reg
5828 || i.tm.operand_types[op].bitfield.acc)
5829 && i.tm.operand_types[op].bitfield.dword)
5830 {
5831 /* Prohibit these changes in the 64bit mode, since the
5832 lowering is more complicated. */
5833 if (flag_code == CODE_64BIT)
5834 {
5835 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5836 register_prefix, i.op[op].regs->reg_name,
5837 i.suffix);
5838 return 0;
5839 }
5840 #if REGISTER_WARNINGS
5841 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5842 register_prefix,
5843 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
5844 register_prefix, i.op[op].regs->reg_name, i.suffix);
5845 #endif
5846 }
5847 /* Warn if the r prefix on a general reg is present. */
5848 else if (i.types[op].bitfield.qword
5849 && (i.tm.operand_types[op].bitfield.reg
5850 || i.tm.operand_types[op].bitfield.acc)
5851 && i.tm.operand_types[op].bitfield.dword)
5852 {
5853 if (intel_syntax
5854 && i.tm.opcode_modifier.toqword
5855 && !i.types[0].bitfield.regsimd)
5856 {
5857 /* Convert to QWORD. We want REX byte. */
5858 i.suffix = QWORD_MNEM_SUFFIX;
5859 }
5860 else
5861 {
5862 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5863 register_prefix, i.op[op].regs->reg_name,
5864 i.suffix);
5865 return 0;
5866 }
5867 }
5868 return 1;
5869 }
5870
5871 static int
5872 check_qword_reg (void)
5873 {
5874 int op;
5875
5876 for (op = i.operands; --op >= 0; )
5877 /* Skip non-register operands. */
5878 if (!i.types[op].bitfield.reg)
5879 continue;
5880 /* Reject eight bit registers, except where the template requires
5881 them. (eg. movzb) */
5882 else if (i.types[op].bitfield.byte
5883 && (i.tm.operand_types[op].bitfield.reg
5884 || i.tm.operand_types[op].bitfield.acc)
5885 && (i.tm.operand_types[op].bitfield.word
5886 || i.tm.operand_types[op].bitfield.dword))
5887 {
5888 as_bad (_("`%s%s' not allowed with `%s%c'"),
5889 register_prefix,
5890 i.op[op].regs->reg_name,
5891 i.tm.name,
5892 i.suffix);
5893 return 0;
5894 }
5895 /* Warn if the r prefix on a general reg is missing. */
5896 else if ((i.types[op].bitfield.word
5897 || i.types[op].bitfield.dword)
5898 && (i.tm.operand_types[op].bitfield.reg
5899 || i.tm.operand_types[op].bitfield.acc)
5900 && i.tm.operand_types[op].bitfield.qword)
5901 {
5902 /* Prohibit these changes in the 64bit mode, since the
5903 lowering is more complicated. */
5904 if (intel_syntax
5905 && i.tm.opcode_modifier.todword
5906 && !i.types[0].bitfield.regsimd)
5907 {
5908 /* Convert to DWORD. We don't want REX byte. */
5909 i.suffix = LONG_MNEM_SUFFIX;
5910 }
5911 else
5912 {
5913 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5914 register_prefix, i.op[op].regs->reg_name,
5915 i.suffix);
5916 return 0;
5917 }
5918 }
5919 return 1;
5920 }
5921
5922 static int
5923 check_word_reg (void)
5924 {
5925 int op;
5926 for (op = i.operands; --op >= 0;)
5927 /* Skip non-register operands. */
5928 if (!i.types[op].bitfield.reg)
5929 continue;
5930 /* Reject eight bit registers, except where the template requires
5931 them. (eg. movzb) */
5932 else if (i.types[op].bitfield.byte
5933 && (i.tm.operand_types[op].bitfield.reg
5934 || i.tm.operand_types[op].bitfield.acc)
5935 && (i.tm.operand_types[op].bitfield.word
5936 || i.tm.operand_types[op].bitfield.dword))
5937 {
5938 as_bad (_("`%s%s' not allowed with `%s%c'"),
5939 register_prefix,
5940 i.op[op].regs->reg_name,
5941 i.tm.name,
5942 i.suffix);
5943 return 0;
5944 }
5945 /* Warn if the e or r prefix on a general reg is present. */
5946 else if ((!quiet_warnings || flag_code == CODE_64BIT)
5947 && (i.types[op].bitfield.dword
5948 || i.types[op].bitfield.qword)
5949 && (i.tm.operand_types[op].bitfield.reg
5950 || i.tm.operand_types[op].bitfield.acc)
5951 && i.tm.operand_types[op].bitfield.word)
5952 {
5953 /* Prohibit these changes in the 64bit mode, since the
5954 lowering is more complicated. */
5955 if (flag_code == CODE_64BIT)
5956 {
5957 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5958 register_prefix, i.op[op].regs->reg_name,
5959 i.suffix);
5960 return 0;
5961 }
5962 #if REGISTER_WARNINGS
5963 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5964 register_prefix,
5965 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
5966 register_prefix, i.op[op].regs->reg_name, i.suffix);
5967 #endif
5968 }
5969 return 1;
5970 }
5971
5972 static int
5973 update_imm (unsigned int j)
5974 {
5975 i386_operand_type overlap = i.types[j];
5976 if ((overlap.bitfield.imm8
5977 || overlap.bitfield.imm8s
5978 || overlap.bitfield.imm16
5979 || overlap.bitfield.imm32
5980 || overlap.bitfield.imm32s
5981 || overlap.bitfield.imm64)
5982 && !operand_type_equal (&overlap, &imm8)
5983 && !operand_type_equal (&overlap, &imm8s)
5984 && !operand_type_equal (&overlap, &imm16)
5985 && !operand_type_equal (&overlap, &imm32)
5986 && !operand_type_equal (&overlap, &imm32s)
5987 && !operand_type_equal (&overlap, &imm64))
5988 {
5989 if (i.suffix)
5990 {
5991 i386_operand_type temp;
5992
5993 operand_type_set (&temp, 0);
5994 if (i.suffix == BYTE_MNEM_SUFFIX)
5995 {
5996 temp.bitfield.imm8 = overlap.bitfield.imm8;
5997 temp.bitfield.imm8s = overlap.bitfield.imm8s;
5998 }
5999 else if (i.suffix == WORD_MNEM_SUFFIX)
6000 temp.bitfield.imm16 = overlap.bitfield.imm16;
6001 else if (i.suffix == QWORD_MNEM_SUFFIX)
6002 {
6003 temp.bitfield.imm64 = overlap.bitfield.imm64;
6004 temp.bitfield.imm32s = overlap.bitfield.imm32s;
6005 }
6006 else
6007 temp.bitfield.imm32 = overlap.bitfield.imm32;
6008 overlap = temp;
6009 }
6010 else if (operand_type_equal (&overlap, &imm16_32_32s)
6011 || operand_type_equal (&overlap, &imm16_32)
6012 || operand_type_equal (&overlap, &imm16_32s))
6013 {
6014 if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
6015 overlap = imm16;
6016 else
6017 overlap = imm32s;
6018 }
6019 if (!operand_type_equal (&overlap, &imm8)
6020 && !operand_type_equal (&overlap, &imm8s)
6021 && !operand_type_equal (&overlap, &imm16)
6022 && !operand_type_equal (&overlap, &imm32)
6023 && !operand_type_equal (&overlap, &imm32s)
6024 && !operand_type_equal (&overlap, &imm64))
6025 {
6026 as_bad (_("no instruction mnemonic suffix given; "
6027 "can't determine immediate size"));
6028 return 0;
6029 }
6030 }
6031 i.types[j] = overlap;
6032
6033 return 1;
6034 }
6035
6036 static int
6037 finalize_imm (void)
6038 {
6039 unsigned int j, n;
6040
6041 /* Update the first 2 immediate operands. */
6042 n = i.operands > 2 ? 2 : i.operands;
6043 if (n)
6044 {
6045 for (j = 0; j < n; j++)
6046 if (update_imm (j) == 0)
6047 return 0;
6048
6049 /* The 3rd operand can't be immediate operand. */
6050 gas_assert (operand_type_check (i.types[2], imm) == 0);
6051 }
6052
6053 return 1;
6054 }
6055
6056 static int
6057 process_operands (void)
6058 {
6059 /* Default segment register this instruction will use for memory
6060 accesses. 0 means unknown. This is only for optimizing out
6061 unnecessary segment overrides. */
6062 const seg_entry *default_seg = 0;
6063
6064 if (i.tm.opcode_modifier.sse2avx && i.tm.opcode_modifier.vexvvvv)
6065 {
6066 unsigned int dupl = i.operands;
6067 unsigned int dest = dupl - 1;
6068 unsigned int j;
6069
6070 /* The destination must be an xmm register. */
6071 gas_assert (i.reg_operands
6072 && MAX_OPERANDS > dupl
6073 && operand_type_equal (&i.types[dest], &regxmm));
6074
6075 if (i.tm.operand_types[0].bitfield.acc
6076 && i.tm.operand_types[0].bitfield.xmmword)
6077 {
6078 if (i.tm.opcode_modifier.vexsources == VEX3SOURCES)
6079 {
6080 /* Keep xmm0 for instructions with VEX prefix and 3
6081 sources. */
6082 i.tm.operand_types[0].bitfield.acc = 0;
6083 i.tm.operand_types[0].bitfield.regsimd = 1;
6084 goto duplicate;
6085 }
6086 else
6087 {
6088 /* We remove the first xmm0 and keep the number of
6089 operands unchanged, which in fact duplicates the
6090 destination. */
6091 for (j = 1; j < i.operands; j++)
6092 {
6093 i.op[j - 1] = i.op[j];
6094 i.types[j - 1] = i.types[j];
6095 i.tm.operand_types[j - 1] = i.tm.operand_types[j];
6096 }
6097 }
6098 }
6099 else if (i.tm.opcode_modifier.implicit1stxmm0)
6100 {
6101 gas_assert ((MAX_OPERANDS - 1) > dupl
6102 && (i.tm.opcode_modifier.vexsources
6103 == VEX3SOURCES));
6104
6105 /* Add the implicit xmm0 for instructions with VEX prefix
6106 and 3 sources. */
6107 for (j = i.operands; j > 0; j--)
6108 {
6109 i.op[j] = i.op[j - 1];
6110 i.types[j] = i.types[j - 1];
6111 i.tm.operand_types[j] = i.tm.operand_types[j - 1];
6112 }
6113 i.op[0].regs
6114 = (const reg_entry *) hash_find (reg_hash, "xmm0");
6115 i.types[0] = regxmm;
6116 i.tm.operand_types[0] = regxmm;
6117
6118 i.operands += 2;
6119 i.reg_operands += 2;
6120 i.tm.operands += 2;
6121
6122 dupl++;
6123 dest++;
6124 i.op[dupl] = i.op[dest];
6125 i.types[dupl] = i.types[dest];
6126 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
6127 }
6128 else
6129 {
6130 duplicate:
6131 i.operands++;
6132 i.reg_operands++;
6133 i.tm.operands++;
6134
6135 i.op[dupl] = i.op[dest];
6136 i.types[dupl] = i.types[dest];
6137 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
6138 }
6139
6140 if (i.tm.opcode_modifier.immext)
6141 process_immext ();
6142 }
6143 else if (i.tm.operand_types[0].bitfield.acc
6144 && i.tm.operand_types[0].bitfield.xmmword)
6145 {
6146 unsigned int j;
6147
6148 for (j = 1; j < i.operands; j++)
6149 {
6150 i.op[j - 1] = i.op[j];
6151 i.types[j - 1] = i.types[j];
6152
6153 /* We need to adjust fields in i.tm since they are used by
6154 build_modrm_byte. */
6155 i.tm.operand_types [j - 1] = i.tm.operand_types [j];
6156 }
6157
6158 i.operands--;
6159 i.reg_operands--;
6160 i.tm.operands--;
6161 }
6162 else if (i.tm.opcode_modifier.implicitquadgroup)
6163 {
6164 /* The second operand must be {x,y,z}mmN, where N is a multiple of 4. */
6165 gas_assert (i.operands >= 2 && i.types[1].bitfield.regsimd);
6166 unsigned int regnum = register_number (i.op[1].regs);
6167 unsigned int first_reg_in_group = regnum & ~3;
6168 unsigned int last_reg_in_group = first_reg_in_group + 3;
6169 if (regnum != first_reg_in_group) {
6170 as_warn (_("the second source register `%s%s' implicitly denotes"
6171 " `%s%.3s%d' to `%s%.3s%d' source group in `%s'"),
6172 register_prefix, i.op[1].regs->reg_name,
6173 register_prefix, i.op[1].regs->reg_name, first_reg_in_group,
6174 register_prefix, i.op[1].regs->reg_name, last_reg_in_group,
6175 i.tm.name);
6176 }
6177 }
6178 else if (i.tm.opcode_modifier.regkludge)
6179 {
6180 /* The imul $imm, %reg instruction is converted into
6181 imul $imm, %reg, %reg, and the clr %reg instruction
6182 is converted into xor %reg, %reg. */
6183
6184 unsigned int first_reg_op;
6185
6186 if (operand_type_check (i.types[0], reg))
6187 first_reg_op = 0;
6188 else
6189 first_reg_op = 1;
6190 /* Pretend we saw the extra register operand. */
6191 gas_assert (i.reg_operands == 1
6192 && i.op[first_reg_op + 1].regs == 0);
6193 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
6194 i.types[first_reg_op + 1] = i.types[first_reg_op];
6195 i.operands++;
6196 i.reg_operands++;
6197 }
6198
6199 if (i.tm.opcode_modifier.shortform)
6200 {
6201 if (i.types[0].bitfield.sreg2
6202 || i.types[0].bitfield.sreg3)
6203 {
6204 if (i.tm.base_opcode == POP_SEG_SHORT
6205 && i.op[0].regs->reg_num == 1)
6206 {
6207 as_bad (_("you can't `pop %scs'"), register_prefix);
6208 return 0;
6209 }
6210 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
6211 if ((i.op[0].regs->reg_flags & RegRex) != 0)
6212 i.rex |= REX_B;
6213 }
6214 else
6215 {
6216 /* The register or float register operand is in operand
6217 0 or 1. */
6218 unsigned int op;
6219
6220 if ((i.types[0].bitfield.reg && i.types[0].bitfield.tbyte)
6221 || operand_type_check (i.types[0], reg))
6222 op = 0;
6223 else
6224 op = 1;
6225 /* Register goes in low 3 bits of opcode. */
6226 i.tm.base_opcode |= i.op[op].regs->reg_num;
6227 if ((i.op[op].regs->reg_flags & RegRex) != 0)
6228 i.rex |= REX_B;
6229 if (!quiet_warnings && i.tm.opcode_modifier.ugh)
6230 {
6231 /* Warn about some common errors, but press on regardless.
6232 The first case can be generated by gcc (<= 2.8.1). */
6233 if (i.operands == 2)
6234 {
6235 /* Reversed arguments on faddp, fsubp, etc. */
6236 as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name,
6237 register_prefix, i.op[!intel_syntax].regs->reg_name,
6238 register_prefix, i.op[intel_syntax].regs->reg_name);
6239 }
6240 else
6241 {
6242 /* Extraneous `l' suffix on fp insn. */
6243 as_warn (_("translating to `%s %s%s'"), i.tm.name,
6244 register_prefix, i.op[0].regs->reg_name);
6245 }
6246 }
6247 }
6248 }
6249 else if (i.tm.opcode_modifier.modrm)
6250 {
6251 /* The opcode is completed (modulo i.tm.extension_opcode which
6252 must be put into the modrm byte). Now, we make the modrm and
6253 index base bytes based on all the info we've collected. */
6254
6255 default_seg = build_modrm_byte ();
6256 }
6257 else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32)
6258 {
6259 default_seg = &ds;
6260 }
6261 else if (i.tm.opcode_modifier.isstring)
6262 {
6263 /* For the string instructions that allow a segment override
6264 on one of their operands, the default segment is ds. */
6265 default_seg = &ds;
6266 }
6267
6268 if (i.tm.base_opcode == 0x8d /* lea */
6269 && i.seg[0]
6270 && !quiet_warnings)
6271 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
6272
6273 /* If a segment was explicitly specified, and the specified segment
6274 is not the default, use an opcode prefix to select it. If we
6275 never figured out what the default segment is, then default_seg
6276 will be zero at this point, and the specified segment prefix will
6277 always be used. */
6278 if ((i.seg[0]) && (i.seg[0] != default_seg))
6279 {
6280 if (!add_prefix (i.seg[0]->seg_prefix))
6281 return 0;
6282 }
6283 return 1;
6284 }
6285
6286 static const seg_entry *
6287 build_modrm_byte (void)
6288 {
6289 const seg_entry *default_seg = 0;
6290 unsigned int source, dest;
6291 int vex_3_sources;
6292
6293 /* The first operand of instructions with VEX prefix and 3 sources
6294 must be VEX_Imm4. */
6295 vex_3_sources = i.tm.opcode_modifier.vexsources == VEX3SOURCES;
6296 if (vex_3_sources)
6297 {
6298 unsigned int nds, reg_slot;
6299 expressionS *exp;
6300
6301 if (i.tm.opcode_modifier.veximmext
6302 && i.tm.opcode_modifier.immext)
6303 {
6304 dest = i.operands - 2;
6305 gas_assert (dest == 3);
6306 }
6307 else
6308 dest = i.operands - 1;
6309 nds = dest - 1;
6310
6311 /* There are 2 kinds of instructions:
6312 1. 5 operands: 4 register operands or 3 register operands
6313 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
6314 VexW0 or VexW1. The destination must be either XMM, YMM or
6315 ZMM register.
6316 2. 4 operands: 4 register operands or 3 register operands
6317 plus 1 memory operand, VexXDS, and VexImmExt */
6318 gas_assert ((i.reg_operands == 4
6319 || (i.reg_operands == 3 && i.mem_operands == 1))
6320 && i.tm.opcode_modifier.vexvvvv == VEXXDS
6321 && (i.tm.opcode_modifier.veximmext
6322 || (i.imm_operands == 1
6323 && i.types[0].bitfield.vec_imm4
6324 && (i.tm.opcode_modifier.vexw == VEXW0
6325 || i.tm.opcode_modifier.vexw == VEXW1)
6326 && i.tm.operand_types[dest].bitfield.regsimd)));
6327
6328 if (i.imm_operands == 0)
6329 {
6330 /* When there is no immediate operand, generate an 8bit
6331 immediate operand to encode the first operand. */
6332 exp = &im_expressions[i.imm_operands++];
6333 i.op[i.operands].imms = exp;
6334 i.types[i.operands] = imm8;
6335 i.operands++;
6336 /* If VexW1 is set, the first operand is the source and
6337 the second operand is encoded in the immediate operand. */
6338 if (i.tm.opcode_modifier.vexw == VEXW1)
6339 {
6340 source = 0;
6341 reg_slot = 1;
6342 }
6343 else
6344 {
6345 source = 1;
6346 reg_slot = 0;
6347 }
6348
6349 /* FMA swaps REG and NDS. */
6350 if (i.tm.cpu_flags.bitfield.cpufma)
6351 {
6352 unsigned int tmp;
6353 tmp = reg_slot;
6354 reg_slot = nds;
6355 nds = tmp;
6356 }
6357
6358 gas_assert (i.tm.operand_types[reg_slot].bitfield.regsimd);
6359 exp->X_op = O_constant;
6360 exp->X_add_number = register_number (i.op[reg_slot].regs) << 4;
6361 gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
6362 }
6363 else
6364 {
6365 unsigned int imm_slot;
6366
6367 if (i.tm.opcode_modifier.vexw == VEXW0)
6368 {
6369 /* If VexW0 is set, the third operand is the source and
6370 the second operand is encoded in the immediate
6371 operand. */
6372 source = 2;
6373 reg_slot = 1;
6374 }
6375 else
6376 {
6377 /* VexW1 is set, the second operand is the source and
6378 the third operand is encoded in the immediate
6379 operand. */
6380 source = 1;
6381 reg_slot = 2;
6382 }
6383
6384 if (i.tm.opcode_modifier.immext)
6385 {
6386 /* When ImmExt is set, the immediate byte is the last
6387 operand. */
6388 imm_slot = i.operands - 1;
6389 source--;
6390 reg_slot--;
6391 }
6392 else
6393 {
6394 imm_slot = 0;
6395
6396 /* Turn on Imm8 so that output_imm will generate it. */
6397 i.types[imm_slot].bitfield.imm8 = 1;
6398 }
6399
6400 gas_assert (i.tm.operand_types[reg_slot].bitfield.regsimd);
6401 i.op[imm_slot].imms->X_add_number
6402 |= register_number (i.op[reg_slot].regs) << 4;
6403 gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
6404 }
6405
6406 gas_assert (i.tm.operand_types[nds].bitfield.regsimd);
6407 i.vex.register_specifier = i.op[nds].regs;
6408 }
6409 else
6410 source = dest = 0;
6411
6412 /* i.reg_operands MUST be the number of real register operands;
6413 implicit registers do not count. If there are 3 register
6414 operands, it must be a instruction with VexNDS. For a
6415 instruction with VexNDD, the destination register is encoded
6416 in VEX prefix. If there are 4 register operands, it must be
6417 a instruction with VEX prefix and 3 sources. */
6418 if (i.mem_operands == 0
6419 && ((i.reg_operands == 2
6420 && i.tm.opcode_modifier.vexvvvv <= VEXXDS)
6421 || (i.reg_operands == 3
6422 && i.tm.opcode_modifier.vexvvvv == VEXXDS)
6423 || (i.reg_operands == 4 && vex_3_sources)))
6424 {
6425 switch (i.operands)
6426 {
6427 case 2:
6428 source = 0;
6429 break;
6430 case 3:
6431 /* When there are 3 operands, one of them may be immediate,
6432 which may be the first or the last operand. Otherwise,
6433 the first operand must be shift count register (cl) or it
6434 is an instruction with VexNDS. */
6435 gas_assert (i.imm_operands == 1
6436 || (i.imm_operands == 0
6437 && (i.tm.opcode_modifier.vexvvvv == VEXXDS
6438 || i.types[0].bitfield.shiftcount)));
6439 if (operand_type_check (i.types[0], imm)
6440 || i.types[0].bitfield.shiftcount)
6441 source = 1;
6442 else
6443 source = 0;
6444 break;
6445 case 4:
6446 /* When there are 4 operands, the first two must be 8bit
6447 immediate operands. The source operand will be the 3rd
6448 one.
6449
6450 For instructions with VexNDS, if the first operand
6451 an imm8, the source operand is the 2nd one. If the last
6452 operand is imm8, the source operand is the first one. */
6453 gas_assert ((i.imm_operands == 2
6454 && i.types[0].bitfield.imm8
6455 && i.types[1].bitfield.imm8)
6456 || (i.tm.opcode_modifier.vexvvvv == VEXXDS
6457 && i.imm_operands == 1
6458 && (i.types[0].bitfield.imm8
6459 || i.types[i.operands - 1].bitfield.imm8
6460 || i.rounding)));
6461 if (i.imm_operands == 2)
6462 source = 2;
6463 else
6464 {
6465 if (i.types[0].bitfield.imm8)
6466 source = 1;
6467 else
6468 source = 0;
6469 }
6470 break;
6471 case 5:
6472 if (i.tm.opcode_modifier.evex)
6473 {
6474 /* For EVEX instructions, when there are 5 operands, the
6475 first one must be immediate operand. If the second one
6476 is immediate operand, the source operand is the 3th
6477 one. If the last one is immediate operand, the source
6478 operand is the 2nd one. */
6479 gas_assert (i.imm_operands == 2
6480 && i.tm.opcode_modifier.sae
6481 && operand_type_check (i.types[0], imm));
6482 if (operand_type_check (i.types[1], imm))
6483 source = 2;
6484 else if (operand_type_check (i.types[4], imm))
6485 source = 1;
6486 else
6487 abort ();
6488 }
6489 break;
6490 default:
6491 abort ();
6492 }
6493
6494 if (!vex_3_sources)
6495 {
6496 dest = source + 1;
6497
6498 /* RC/SAE operand could be between DEST and SRC. That happens
6499 when one operand is GPR and the other one is XMM/YMM/ZMM
6500 register. */
6501 if (i.rounding && i.rounding->operand == (int) dest)
6502 dest++;
6503
6504 if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
6505 {
6506 /* For instructions with VexNDS, the register-only source
6507 operand must be a 32/64bit integer, XMM, YMM, ZMM, or mask
6508 register. It is encoded in VEX prefix. We need to
6509 clear RegMem bit before calling operand_type_equal. */
6510
6511 i386_operand_type op;
6512 unsigned int vvvv;
6513
6514 /* Check register-only source operand when two source
6515 operands are swapped. */
6516 if (!i.tm.operand_types[source].bitfield.baseindex
6517 && i.tm.operand_types[dest].bitfield.baseindex)
6518 {
6519 vvvv = source;
6520 source = dest;
6521 }
6522 else
6523 vvvv = dest;
6524
6525 op = i.tm.operand_types[vvvv];
6526 op.bitfield.regmem = 0;
6527 if ((dest + 1) >= i.operands
6528 || ((!op.bitfield.reg
6529 || (!op.bitfield.dword && !op.bitfield.qword))
6530 && !op.bitfield.regsimd
6531 && !operand_type_equal (&op, &regmask)))
6532 abort ();
6533 i.vex.register_specifier = i.op[vvvv].regs;
6534 dest++;
6535 }
6536 }
6537
6538 i.rm.mode = 3;
6539 /* One of the register operands will be encoded in the i.tm.reg
6540 field, the other in the combined i.tm.mode and i.tm.regmem
6541 fields. If no form of this instruction supports a memory
6542 destination operand, then we assume the source operand may
6543 sometimes be a memory operand and so we need to store the
6544 destination in the i.rm.reg field. */
6545 if (!i.tm.operand_types[dest].bitfield.regmem
6546 && operand_type_check (i.tm.operand_types[dest], anymem) == 0)
6547 {
6548 i.rm.reg = i.op[dest].regs->reg_num;
6549 i.rm.regmem = i.op[source].regs->reg_num;
6550 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
6551 i.rex |= REX_R;
6552 if ((i.op[dest].regs->reg_flags & RegVRex) != 0)
6553 i.vrex |= REX_R;
6554 if ((i.op[source].regs->reg_flags & RegRex) != 0)
6555 i.rex |= REX_B;
6556 if ((i.op[source].regs->reg_flags & RegVRex) != 0)
6557 i.vrex |= REX_B;
6558 }
6559 else
6560 {
6561 i.rm.reg = i.op[source].regs->reg_num;
6562 i.rm.regmem = i.op[dest].regs->reg_num;
6563 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
6564 i.rex |= REX_B;
6565 if ((i.op[dest].regs->reg_flags & RegVRex) != 0)
6566 i.vrex |= REX_B;
6567 if ((i.op[source].regs->reg_flags & RegRex) != 0)
6568 i.rex |= REX_R;
6569 if ((i.op[source].regs->reg_flags & RegVRex) != 0)
6570 i.vrex |= REX_R;
6571 }
6572 if (flag_code != CODE_64BIT && (i.rex & (REX_R | REX_B)))
6573 {
6574 if (!i.types[0].bitfield.control
6575 && !i.types[1].bitfield.control)
6576 abort ();
6577 i.rex &= ~(REX_R | REX_B);
6578 add_prefix (LOCK_PREFIX_OPCODE);
6579 }
6580 }
6581 else
6582 { /* If it's not 2 reg operands... */
6583 unsigned int mem;
6584
6585 if (i.mem_operands)
6586 {
6587 unsigned int fake_zero_displacement = 0;
6588 unsigned int op;
6589
6590 for (op = 0; op < i.operands; op++)
6591 if (operand_type_check (i.types[op], anymem))
6592 break;
6593 gas_assert (op < i.operands);
6594
6595 if (i.tm.opcode_modifier.vecsib)
6596 {
6597 if (i.index_reg->reg_num == RegEiz
6598 || i.index_reg->reg_num == RegRiz)
6599 abort ();
6600
6601 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6602 if (!i.base_reg)
6603 {
6604 i.sib.base = NO_BASE_REGISTER;
6605 i.sib.scale = i.log2_scale_factor;
6606 i.types[op].bitfield.disp8 = 0;
6607 i.types[op].bitfield.disp16 = 0;
6608 i.types[op].bitfield.disp64 = 0;
6609 if (flag_code != CODE_64BIT || i.prefix[ADDR_PREFIX])
6610 {
6611 /* Must be 32 bit */
6612 i.types[op].bitfield.disp32 = 1;
6613 i.types[op].bitfield.disp32s = 0;
6614 }
6615 else
6616 {
6617 i.types[op].bitfield.disp32 = 0;
6618 i.types[op].bitfield.disp32s = 1;
6619 }
6620 }
6621 i.sib.index = i.index_reg->reg_num;
6622 if ((i.index_reg->reg_flags & RegRex) != 0)
6623 i.rex |= REX_X;
6624 if ((i.index_reg->reg_flags & RegVRex) != 0)
6625 i.vrex |= REX_X;
6626 }
6627
6628 default_seg = &ds;
6629
6630 if (i.base_reg == 0)
6631 {
6632 i.rm.mode = 0;
6633 if (!i.disp_operands)
6634 fake_zero_displacement = 1;
6635 if (i.index_reg == 0)
6636 {
6637 gas_assert (!i.tm.opcode_modifier.vecsib);
6638 /* Operand is just <disp> */
6639 if (flag_code == CODE_64BIT)
6640 {
6641 /* 64bit mode overwrites the 32bit absolute
6642 addressing by RIP relative addressing and
6643 absolute addressing is encoded by one of the
6644 redundant SIB forms. */
6645 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6646 i.sib.base = NO_BASE_REGISTER;
6647 i.sib.index = NO_INDEX_REGISTER;
6648 i.types[op] = ((i.prefix[ADDR_PREFIX] == 0)
6649 ? disp32s : disp32);
6650 }
6651 else if ((flag_code == CODE_16BIT)
6652 ^ (i.prefix[ADDR_PREFIX] != 0))
6653 {
6654 i.rm.regmem = NO_BASE_REGISTER_16;
6655 i.types[op] = disp16;
6656 }
6657 else
6658 {
6659 i.rm.regmem = NO_BASE_REGISTER;
6660 i.types[op] = disp32;
6661 }
6662 }
6663 else if (!i.tm.opcode_modifier.vecsib)
6664 {
6665 /* !i.base_reg && i.index_reg */
6666 if (i.index_reg->reg_num == RegEiz
6667 || i.index_reg->reg_num == RegRiz)
6668 i.sib.index = NO_INDEX_REGISTER;
6669 else
6670 i.sib.index = i.index_reg->reg_num;
6671 i.sib.base = NO_BASE_REGISTER;
6672 i.sib.scale = i.log2_scale_factor;
6673 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6674 i.types[op].bitfield.disp8 = 0;
6675 i.types[op].bitfield.disp16 = 0;
6676 i.types[op].bitfield.disp64 = 0;
6677 if (flag_code != CODE_64BIT || i.prefix[ADDR_PREFIX])
6678 {
6679 /* Must be 32 bit */
6680 i.types[op].bitfield.disp32 = 1;
6681 i.types[op].bitfield.disp32s = 0;
6682 }
6683 else
6684 {
6685 i.types[op].bitfield.disp32 = 0;
6686 i.types[op].bitfield.disp32s = 1;
6687 }
6688 if ((i.index_reg->reg_flags & RegRex) != 0)
6689 i.rex |= REX_X;
6690 }
6691 }
6692 /* RIP addressing for 64bit mode. */
6693 else if (i.base_reg->reg_num == RegRip ||
6694 i.base_reg->reg_num == RegEip)
6695 {
6696 gas_assert (!i.tm.opcode_modifier.vecsib);
6697 i.rm.regmem = NO_BASE_REGISTER;
6698 i.types[op].bitfield.disp8 = 0;
6699 i.types[op].bitfield.disp16 = 0;
6700 i.types[op].bitfield.disp32 = 0;
6701 i.types[op].bitfield.disp32s = 1;
6702 i.types[op].bitfield.disp64 = 0;
6703 i.flags[op] |= Operand_PCrel;
6704 if (! i.disp_operands)
6705 fake_zero_displacement = 1;
6706 }
6707 else if (i.base_reg->reg_type.bitfield.word)
6708 {
6709 gas_assert (!i.tm.opcode_modifier.vecsib);
6710 switch (i.base_reg->reg_num)
6711 {
6712 case 3: /* (%bx) */
6713 if (i.index_reg == 0)
6714 i.rm.regmem = 7;
6715 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
6716 i.rm.regmem = i.index_reg->reg_num - 6;
6717 break;
6718 case 5: /* (%bp) */
6719 default_seg = &ss;
6720 if (i.index_reg == 0)
6721 {
6722 i.rm.regmem = 6;
6723 if (operand_type_check (i.types[op], disp) == 0)
6724 {
6725 /* fake (%bp) into 0(%bp) */
6726 i.types[op].bitfield.disp8 = 1;
6727 fake_zero_displacement = 1;
6728 }
6729 }
6730 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
6731 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
6732 break;
6733 default: /* (%si) -> 4 or (%di) -> 5 */
6734 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
6735 }
6736 i.rm.mode = mode_from_disp_size (i.types[op]);
6737 }
6738 else /* i.base_reg and 32/64 bit mode */
6739 {
6740 if (flag_code == CODE_64BIT
6741 && operand_type_check (i.types[op], disp))
6742 {
6743 i386_operand_type temp;
6744 operand_type_set (&temp, 0);
6745 temp.bitfield.disp8 = i.types[op].bitfield.disp8;
6746 i.types[op] = temp;
6747 if (i.prefix[ADDR_PREFIX] == 0)
6748 i.types[op].bitfield.disp32s = 1;
6749 else
6750 i.types[op].bitfield.disp32 = 1;
6751 }
6752
6753 if (!i.tm.opcode_modifier.vecsib)
6754 i.rm.regmem = i.base_reg->reg_num;
6755 if ((i.base_reg->reg_flags & RegRex) != 0)
6756 i.rex |= REX_B;
6757 i.sib.base = i.base_reg->reg_num;
6758 /* x86-64 ignores REX prefix bit here to avoid decoder
6759 complications. */
6760 if (!(i.base_reg->reg_flags & RegRex)
6761 && (i.base_reg->reg_num == EBP_REG_NUM
6762 || i.base_reg->reg_num == ESP_REG_NUM))
6763 default_seg = &ss;
6764 if (i.base_reg->reg_num == 5 && i.disp_operands == 0)
6765 {
6766 fake_zero_displacement = 1;
6767 i.types[op].bitfield.disp8 = 1;
6768 }
6769 i.sib.scale = i.log2_scale_factor;
6770 if (i.index_reg == 0)
6771 {
6772 gas_assert (!i.tm.opcode_modifier.vecsib);
6773 /* <disp>(%esp) becomes two byte modrm with no index
6774 register. We've already stored the code for esp
6775 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
6776 Any base register besides %esp will not use the
6777 extra modrm byte. */
6778 i.sib.index = NO_INDEX_REGISTER;
6779 }
6780 else if (!i.tm.opcode_modifier.vecsib)
6781 {
6782 if (i.index_reg->reg_num == RegEiz
6783 || i.index_reg->reg_num == RegRiz)
6784 i.sib.index = NO_INDEX_REGISTER;
6785 else
6786 i.sib.index = i.index_reg->reg_num;
6787 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6788 if ((i.index_reg->reg_flags & RegRex) != 0)
6789 i.rex |= REX_X;
6790 }
6791
6792 if (i.disp_operands
6793 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
6794 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
6795 i.rm.mode = 0;
6796 else
6797 {
6798 if (!fake_zero_displacement
6799 && !i.disp_operands
6800 && i.disp_encoding)
6801 {
6802 fake_zero_displacement = 1;
6803 if (i.disp_encoding == disp_encoding_8bit)
6804 i.types[op].bitfield.disp8 = 1;
6805 else
6806 i.types[op].bitfield.disp32 = 1;
6807 }
6808 i.rm.mode = mode_from_disp_size (i.types[op]);
6809 }
6810 }
6811
6812 if (fake_zero_displacement)
6813 {
6814 /* Fakes a zero displacement assuming that i.types[op]
6815 holds the correct displacement size. */
6816 expressionS *exp;
6817
6818 gas_assert (i.op[op].disps == 0);
6819 exp = &disp_expressions[i.disp_operands++];
6820 i.op[op].disps = exp;
6821 exp->X_op = O_constant;
6822 exp->X_add_number = 0;
6823 exp->X_add_symbol = (symbolS *) 0;
6824 exp->X_op_symbol = (symbolS *) 0;
6825 }
6826
6827 mem = op;
6828 }
6829 else
6830 mem = ~0;
6831
6832 if (i.tm.opcode_modifier.vexsources == XOP2SOURCES)
6833 {
6834 if (operand_type_check (i.types[0], imm))
6835 i.vex.register_specifier = NULL;
6836 else
6837 {
6838 /* VEX.vvvv encodes one of the sources when the first
6839 operand is not an immediate. */
6840 if (i.tm.opcode_modifier.vexw == VEXW0)
6841 i.vex.register_specifier = i.op[0].regs;
6842 else
6843 i.vex.register_specifier = i.op[1].regs;
6844 }
6845
6846 /* Destination is a XMM register encoded in the ModRM.reg
6847 and VEX.R bit. */
6848 i.rm.reg = i.op[2].regs->reg_num;
6849 if ((i.op[2].regs->reg_flags & RegRex) != 0)
6850 i.rex |= REX_R;
6851
6852 /* ModRM.rm and VEX.B encodes the other source. */
6853 if (!i.mem_operands)
6854 {
6855 i.rm.mode = 3;
6856
6857 if (i.tm.opcode_modifier.vexw == VEXW0)
6858 i.rm.regmem = i.op[1].regs->reg_num;
6859 else
6860 i.rm.regmem = i.op[0].regs->reg_num;
6861
6862 if ((i.op[1].regs->reg_flags & RegRex) != 0)
6863 i.rex |= REX_B;
6864 }
6865 }
6866 else if (i.tm.opcode_modifier.vexvvvv == VEXLWP)
6867 {
6868 i.vex.register_specifier = i.op[2].regs;
6869 if (!i.mem_operands)
6870 {
6871 i.rm.mode = 3;
6872 i.rm.regmem = i.op[1].regs->reg_num;
6873 if ((i.op[1].regs->reg_flags & RegRex) != 0)
6874 i.rex |= REX_B;
6875 }
6876 }
6877 /* Fill in i.rm.reg or i.rm.regmem field with register operand
6878 (if any) based on i.tm.extension_opcode. Again, we must be
6879 careful to make sure that segment/control/debug/test/MMX
6880 registers are coded into the i.rm.reg field. */
6881 else if (i.reg_operands)
6882 {
6883 unsigned int op;
6884 unsigned int vex_reg = ~0;
6885
6886 for (op = 0; op < i.operands; op++)
6887 if (i.types[op].bitfield.reg
6888 || i.types[op].bitfield.regmmx
6889 || i.types[op].bitfield.regsimd
6890 || i.types[op].bitfield.regbnd
6891 || i.types[op].bitfield.regmask
6892 || i.types[op].bitfield.sreg2
6893 || i.types[op].bitfield.sreg3
6894 || i.types[op].bitfield.control
6895 || i.types[op].bitfield.debug
6896 || i.types[op].bitfield.test)
6897 break;
6898
6899 if (vex_3_sources)
6900 op = dest;
6901 else if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
6902 {
6903 /* For instructions with VexNDS, the register-only
6904 source operand is encoded in VEX prefix. */
6905 gas_assert (mem != (unsigned int) ~0);
6906
6907 if (op > mem)
6908 {
6909 vex_reg = op++;
6910 gas_assert (op < i.operands);
6911 }
6912 else
6913 {
6914 /* Check register-only source operand when two source
6915 operands are swapped. */
6916 if (!i.tm.operand_types[op].bitfield.baseindex
6917 && i.tm.operand_types[op + 1].bitfield.baseindex)
6918 {
6919 vex_reg = op;
6920 op += 2;
6921 gas_assert (mem == (vex_reg + 1)
6922 && op < i.operands);
6923 }
6924 else
6925 {
6926 vex_reg = op + 1;
6927 gas_assert (vex_reg < i.operands);
6928 }
6929 }
6930 }
6931 else if (i.tm.opcode_modifier.vexvvvv == VEXNDD)
6932 {
6933 /* For instructions with VexNDD, the register destination
6934 is encoded in VEX prefix. */
6935 if (i.mem_operands == 0)
6936 {
6937 /* There is no memory operand. */
6938 gas_assert ((op + 2) == i.operands);
6939 vex_reg = op + 1;
6940 }
6941 else
6942 {
6943 /* There are only 2 operands. */
6944 gas_assert (op < 2 && i.operands == 2);
6945 vex_reg = 1;
6946 }
6947 }
6948 else
6949 gas_assert (op < i.operands);
6950
6951 if (vex_reg != (unsigned int) ~0)
6952 {
6953 i386_operand_type *type = &i.tm.operand_types[vex_reg];
6954
6955 if ((!type->bitfield.reg
6956 || (!type->bitfield.dword && !type->bitfield.qword))
6957 && !type->bitfield.regsimd
6958 && !operand_type_equal (type, &regmask))
6959 abort ();
6960
6961 i.vex.register_specifier = i.op[vex_reg].regs;
6962 }
6963
6964 /* Don't set OP operand twice. */
6965 if (vex_reg != op)
6966 {
6967 /* If there is an extension opcode to put here, the
6968 register number must be put into the regmem field. */
6969 if (i.tm.extension_opcode != None)
6970 {
6971 i.rm.regmem = i.op[op].regs->reg_num;
6972 if ((i.op[op].regs->reg_flags & RegRex) != 0)
6973 i.rex |= REX_B;
6974 if ((i.op[op].regs->reg_flags & RegVRex) != 0)
6975 i.vrex |= REX_B;
6976 }
6977 else
6978 {
6979 i.rm.reg = i.op[op].regs->reg_num;
6980 if ((i.op[op].regs->reg_flags & RegRex) != 0)
6981 i.rex |= REX_R;
6982 if ((i.op[op].regs->reg_flags & RegVRex) != 0)
6983 i.vrex |= REX_R;
6984 }
6985 }
6986
6987 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
6988 must set it to 3 to indicate this is a register operand
6989 in the regmem field. */
6990 if (!i.mem_operands)
6991 i.rm.mode = 3;
6992 }
6993
6994 /* Fill in i.rm.reg field with extension opcode (if any). */
6995 if (i.tm.extension_opcode != None)
6996 i.rm.reg = i.tm.extension_opcode;
6997 }
6998 return default_seg;
6999 }
7000
7001 static void
7002 output_branch (void)
7003 {
7004 char *p;
7005 int size;
7006 int code16;
7007 int prefix;
7008 relax_substateT subtype;
7009 symbolS *sym;
7010 offsetT off;
7011
7012 code16 = flag_code == CODE_16BIT ? CODE16 : 0;
7013 size = i.disp_encoding == disp_encoding_32bit ? BIG : SMALL;
7014
7015 prefix = 0;
7016 if (i.prefix[DATA_PREFIX] != 0)
7017 {
7018 prefix = 1;
7019 i.prefixes -= 1;
7020 code16 ^= CODE16;
7021 }
7022 /* Pentium4 branch hints. */
7023 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
7024 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
7025 {
7026 prefix++;
7027 i.prefixes--;
7028 }
7029 if (i.prefix[REX_PREFIX] != 0)
7030 {
7031 prefix++;
7032 i.prefixes--;
7033 }
7034
7035 /* BND prefixed jump. */
7036 if (i.prefix[BND_PREFIX] != 0)
7037 {
7038 FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]);
7039 i.prefixes -= 1;
7040 }
7041
7042 if (i.prefixes != 0 && !intel_syntax)
7043 as_warn (_("skipping prefixes on this instruction"));
7044
7045 /* It's always a symbol; End frag & setup for relax.
7046 Make sure there is enough room in this frag for the largest
7047 instruction we may generate in md_convert_frag. This is 2
7048 bytes for the opcode and room for the prefix and largest
7049 displacement. */
7050 frag_grow (prefix + 2 + 4);
7051 /* Prefix and 1 opcode byte go in fr_fix. */
7052 p = frag_more (prefix + 1);
7053 if (i.prefix[DATA_PREFIX] != 0)
7054 *p++ = DATA_PREFIX_OPCODE;
7055 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
7056 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
7057 *p++ = i.prefix[SEG_PREFIX];
7058 if (i.prefix[REX_PREFIX] != 0)
7059 *p++ = i.prefix[REX_PREFIX];
7060 *p = i.tm.base_opcode;
7061
7062 if ((unsigned char) *p == JUMP_PC_RELATIVE)
7063 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, size);
7064 else if (cpu_arch_flags.bitfield.cpui386)
7065 subtype = ENCODE_RELAX_STATE (COND_JUMP, size);
7066 else
7067 subtype = ENCODE_RELAX_STATE (COND_JUMP86, size);
7068 subtype |= code16;
7069
7070 sym = i.op[0].disps->X_add_symbol;
7071 off = i.op[0].disps->X_add_number;
7072
7073 if (i.op[0].disps->X_op != O_constant
7074 && i.op[0].disps->X_op != O_symbol)
7075 {
7076 /* Handle complex expressions. */
7077 sym = make_expr_symbol (i.op[0].disps);
7078 off = 0;
7079 }
7080
7081 /* 1 possible extra opcode + 4 byte displacement go in var part.
7082 Pass reloc in fr_var. */
7083 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
7084 }
7085
7086 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7087 /* Return TRUE iff PLT32 relocation should be used for branching to
7088 symbol S. */
7089
7090 static bfd_boolean
7091 need_plt32_p (symbolS *s)
7092 {
7093 /* PLT32 relocation is ELF only. */
7094 if (!IS_ELF)
7095 return FALSE;
7096
7097 /* Since there is no need to prepare for PLT branch on x86-64, we
7098 can generate R_X86_64_PLT32, instead of R_X86_64_PC32, which can
7099 be used as a marker for 32-bit PC-relative branches. */
7100 if (!object_64bit)
7101 return FALSE;
7102
7103 /* Weak or undefined symbol need PLT32 relocation. */
7104 if (S_IS_WEAK (s) || !S_IS_DEFINED (s))
7105 return TRUE;
7106
7107 /* Non-global symbol doesn't need PLT32 relocation. */
7108 if (! S_IS_EXTERNAL (s))
7109 return FALSE;
7110
7111 /* Other global symbols need PLT32 relocation. NB: Symbol with
7112 non-default visibilities are treated as normal global symbol
7113 so that PLT32 relocation can be used as a marker for 32-bit
7114 PC-relative branches. It is useful for linker relaxation. */
7115 return TRUE;
7116 }
7117 #endif
7118
7119 static void
7120 output_jump (void)
7121 {
7122 char *p;
7123 int size;
7124 fixS *fixP;
7125 bfd_reloc_code_real_type jump_reloc = i.reloc[0];
7126
7127 if (i.tm.opcode_modifier.jumpbyte)
7128 {
7129 /* This is a loop or jecxz type instruction. */
7130 size = 1;
7131 if (i.prefix[ADDR_PREFIX] != 0)
7132 {
7133 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
7134 i.prefixes -= 1;
7135 }
7136 /* Pentium4 branch hints. */
7137 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
7138 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
7139 {
7140 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
7141 i.prefixes--;
7142 }
7143 }
7144 else
7145 {
7146 int code16;
7147
7148 code16 = 0;
7149 if (flag_code == CODE_16BIT)
7150 code16 = CODE16;
7151
7152 if (i.prefix[DATA_PREFIX] != 0)
7153 {
7154 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
7155 i.prefixes -= 1;
7156 code16 ^= CODE16;
7157 }
7158
7159 size = 4;
7160 if (code16)
7161 size = 2;
7162 }
7163
7164 if (i.prefix[REX_PREFIX] != 0)
7165 {
7166 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
7167 i.prefixes -= 1;
7168 }
7169
7170 /* BND prefixed jump. */
7171 if (i.prefix[BND_PREFIX] != 0)
7172 {
7173 FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]);
7174 i.prefixes -= 1;
7175 }
7176
7177 if (i.prefixes != 0 && !intel_syntax)
7178 as_warn (_("skipping prefixes on this instruction"));
7179
7180 p = frag_more (i.tm.opcode_length + size);
7181 switch (i.tm.opcode_length)
7182 {
7183 case 2:
7184 *p++ = i.tm.base_opcode >> 8;
7185 /* Fall through. */
7186 case 1:
7187 *p++ = i.tm.base_opcode;
7188 break;
7189 default:
7190 abort ();
7191 }
7192
7193 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7194 if (size == 4
7195 && jump_reloc == NO_RELOC
7196 && need_plt32_p (i.op[0].disps->X_add_symbol))
7197 jump_reloc = BFD_RELOC_X86_64_PLT32;
7198 #endif
7199
7200 jump_reloc = reloc (size, 1, 1, jump_reloc);
7201
7202 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
7203 i.op[0].disps, 1, jump_reloc);
7204
7205 /* All jumps handled here are signed, but don't use a signed limit
7206 check for 32 and 16 bit jumps as we want to allow wrap around at
7207 4G and 64k respectively. */
7208 if (size == 1)
7209 fixP->fx_signed = 1;
7210 }
7211
7212 static void
7213 output_interseg_jump (void)
7214 {
7215 char *p;
7216 int size;
7217 int prefix;
7218 int code16;
7219
7220 code16 = 0;
7221 if (flag_code == CODE_16BIT)
7222 code16 = CODE16;
7223
7224 prefix = 0;
7225 if (i.prefix[DATA_PREFIX] != 0)
7226 {
7227 prefix = 1;
7228 i.prefixes -= 1;
7229 code16 ^= CODE16;
7230 }
7231 if (i.prefix[REX_PREFIX] != 0)
7232 {
7233 prefix++;
7234 i.prefixes -= 1;
7235 }
7236
7237 size = 4;
7238 if (code16)
7239 size = 2;
7240
7241 if (i.prefixes != 0 && !intel_syntax)
7242 as_warn (_("skipping prefixes on this instruction"));
7243
7244 /* 1 opcode; 2 segment; offset */
7245 p = frag_more (prefix + 1 + 2 + size);
7246
7247 if (i.prefix[DATA_PREFIX] != 0)
7248 *p++ = DATA_PREFIX_OPCODE;
7249
7250 if (i.prefix[REX_PREFIX] != 0)
7251 *p++ = i.prefix[REX_PREFIX];
7252
7253 *p++ = i.tm.base_opcode;
7254 if (i.op[1].imms->X_op == O_constant)
7255 {
7256 offsetT n = i.op[1].imms->X_add_number;
7257
7258 if (size == 2
7259 && !fits_in_unsigned_word (n)
7260 && !fits_in_signed_word (n))
7261 {
7262 as_bad (_("16-bit jump out of range"));
7263 return;
7264 }
7265 md_number_to_chars (p, n, size);
7266 }
7267 else
7268 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
7269 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
7270 if (i.op[0].imms->X_op != O_constant)
7271 as_bad (_("can't handle non absolute segment in `%s'"),
7272 i.tm.name);
7273 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
7274 }
7275
7276 static void
7277 output_insn (void)
7278 {
7279 fragS *insn_start_frag;
7280 offsetT insn_start_off;
7281
7282 /* Tie dwarf2 debug info to the address at the start of the insn.
7283 We can't do this after the insn has been output as the current
7284 frag may have been closed off. eg. by frag_var. */
7285 dwarf2_emit_insn (0);
7286
7287 insn_start_frag = frag_now;
7288 insn_start_off = frag_now_fix ();
7289
7290 /* Output jumps. */
7291 if (i.tm.opcode_modifier.jump)
7292 output_branch ();
7293 else if (i.tm.opcode_modifier.jumpbyte
7294 || i.tm.opcode_modifier.jumpdword)
7295 output_jump ();
7296 else if (i.tm.opcode_modifier.jumpintersegment)
7297 output_interseg_jump ();
7298 else
7299 {
7300 /* Output normal instructions here. */
7301 char *p;
7302 unsigned char *q;
7303 unsigned int j;
7304 unsigned int prefix;
7305
7306 if (avoid_fence
7307 && i.tm.base_opcode == 0xfae
7308 && i.operands == 1
7309 && i.imm_operands == 1
7310 && (i.op[0].imms->X_add_number == 0xe8
7311 || i.op[0].imms->X_add_number == 0xf0
7312 || i.op[0].imms->X_add_number == 0xf8))
7313 {
7314 /* Encode lfence, mfence, and sfence as
7315 f0 83 04 24 00 lock addl $0x0, (%{re}sp). */
7316 offsetT val = 0x240483f0ULL;
7317 p = frag_more (5);
7318 md_number_to_chars (p, val, 5);
7319 return;
7320 }
7321
7322 /* Some processors fail on LOCK prefix. This options makes
7323 assembler ignore LOCK prefix and serves as a workaround. */
7324 if (omit_lock_prefix)
7325 {
7326 if (i.tm.base_opcode == LOCK_PREFIX_OPCODE)
7327 return;
7328 i.prefix[LOCK_PREFIX] = 0;
7329 }
7330
7331 /* Since the VEX/EVEX prefix contains the implicit prefix, we
7332 don't need the explicit prefix. */
7333 if (!i.tm.opcode_modifier.vex && !i.tm.opcode_modifier.evex)
7334 {
7335 switch (i.tm.opcode_length)
7336 {
7337 case 3:
7338 if (i.tm.base_opcode & 0xff000000)
7339 {
7340 prefix = (i.tm.base_opcode >> 24) & 0xff;
7341 goto check_prefix;
7342 }
7343 break;
7344 case 2:
7345 if ((i.tm.base_opcode & 0xff0000) != 0)
7346 {
7347 prefix = (i.tm.base_opcode >> 16) & 0xff;
7348 if (i.tm.cpu_flags.bitfield.cpupadlock)
7349 {
7350 check_prefix:
7351 if (prefix != REPE_PREFIX_OPCODE
7352 || (i.prefix[REP_PREFIX]
7353 != REPE_PREFIX_OPCODE))
7354 add_prefix (prefix);
7355 }
7356 else
7357 add_prefix (prefix);
7358 }
7359 break;
7360 case 1:
7361 break;
7362 case 0:
7363 /* Check for pseudo prefixes. */
7364 as_bad_where (insn_start_frag->fr_file,
7365 insn_start_frag->fr_line,
7366 _("pseudo prefix without instruction"));
7367 return;
7368 default:
7369 abort ();
7370 }
7371
7372 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
7373 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
7374 R_X86_64_GOTTPOFF relocation so that linker can safely
7375 perform IE->LE optimization. */
7376 if (x86_elf_abi == X86_64_X32_ABI
7377 && i.operands == 2
7378 && i.reloc[0] == BFD_RELOC_X86_64_GOTTPOFF
7379 && i.prefix[REX_PREFIX] == 0)
7380 add_prefix (REX_OPCODE);
7381 #endif
7382
7383 /* The prefix bytes. */
7384 for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++)
7385 if (*q)
7386 FRAG_APPEND_1_CHAR (*q);
7387 }
7388 else
7389 {
7390 for (j = 0, q = i.prefix; j < ARRAY_SIZE (i.prefix); j++, q++)
7391 if (*q)
7392 switch (j)
7393 {
7394 case REX_PREFIX:
7395 /* REX byte is encoded in VEX prefix. */
7396 break;
7397 case SEG_PREFIX:
7398 case ADDR_PREFIX:
7399 FRAG_APPEND_1_CHAR (*q);
7400 break;
7401 default:
7402 /* There should be no other prefixes for instructions
7403 with VEX prefix. */
7404 abort ();
7405 }
7406
7407 /* For EVEX instructions i.vrex should become 0 after
7408 build_evex_prefix. For VEX instructions upper 16 registers
7409 aren't available, so VREX should be 0. */
7410 if (i.vrex)
7411 abort ();
7412 /* Now the VEX prefix. */
7413 p = frag_more (i.vex.length);
7414 for (j = 0; j < i.vex.length; j++)
7415 p[j] = i.vex.bytes[j];
7416 }
7417
7418 /* Now the opcode; be careful about word order here! */
7419 if (i.tm.opcode_length == 1)
7420 {
7421 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
7422 }
7423 else
7424 {
7425 switch (i.tm.opcode_length)
7426 {
7427 case 4:
7428 p = frag_more (4);
7429 *p++ = (i.tm.base_opcode >> 24) & 0xff;
7430 *p++ = (i.tm.base_opcode >> 16) & 0xff;
7431 break;
7432 case 3:
7433 p = frag_more (3);
7434 *p++ = (i.tm.base_opcode >> 16) & 0xff;
7435 break;
7436 case 2:
7437 p = frag_more (2);
7438 break;
7439 default:
7440 abort ();
7441 break;
7442 }
7443
7444 /* Put out high byte first: can't use md_number_to_chars! */
7445 *p++ = (i.tm.base_opcode >> 8) & 0xff;
7446 *p = i.tm.base_opcode & 0xff;
7447 }
7448
7449 /* Now the modrm byte and sib byte (if present). */
7450 if (i.tm.opcode_modifier.modrm)
7451 {
7452 FRAG_APPEND_1_CHAR ((i.rm.regmem << 0
7453 | i.rm.reg << 3
7454 | i.rm.mode << 6));
7455 /* If i.rm.regmem == ESP (4)
7456 && i.rm.mode != (Register mode)
7457 && not 16 bit
7458 ==> need second modrm byte. */
7459 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
7460 && i.rm.mode != 3
7461 && !(i.base_reg && i.base_reg->reg_type.bitfield.word))
7462 FRAG_APPEND_1_CHAR ((i.sib.base << 0
7463 | i.sib.index << 3
7464 | i.sib.scale << 6));
7465 }
7466
7467 if (i.disp_operands)
7468 output_disp (insn_start_frag, insn_start_off);
7469
7470 if (i.imm_operands)
7471 output_imm (insn_start_frag, insn_start_off);
7472 }
7473
7474 #ifdef DEBUG386
7475 if (flag_debug)
7476 {
7477 pi ("" /*line*/, &i);
7478 }
7479 #endif /* DEBUG386 */
7480 }
7481
7482 /* Return the size of the displacement operand N. */
7483
7484 static int
7485 disp_size (unsigned int n)
7486 {
7487 int size = 4;
7488
7489 if (i.types[n].bitfield.disp64)
7490 size = 8;
7491 else if (i.types[n].bitfield.disp8)
7492 size = 1;
7493 else if (i.types[n].bitfield.disp16)
7494 size = 2;
7495 return size;
7496 }
7497
7498 /* Return the size of the immediate operand N. */
7499
7500 static int
7501 imm_size (unsigned int n)
7502 {
7503 int size = 4;
7504 if (i.types[n].bitfield.imm64)
7505 size = 8;
7506 else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s)
7507 size = 1;
7508 else if (i.types[n].bitfield.imm16)
7509 size = 2;
7510 return size;
7511 }
7512
7513 static void
7514 output_disp (fragS *insn_start_frag, offsetT insn_start_off)
7515 {
7516 char *p;
7517 unsigned int n;
7518
7519 for (n = 0; n < i.operands; n++)
7520 {
7521 if (operand_type_check (i.types[n], disp))
7522 {
7523 if (i.op[n].disps->X_op == O_constant)
7524 {
7525 int size = disp_size (n);
7526 offsetT val = i.op[n].disps->X_add_number;
7527
7528 val = offset_in_range (val >> i.memshift, size);
7529 p = frag_more (size);
7530 md_number_to_chars (p, val, size);
7531 }
7532 else
7533 {
7534 enum bfd_reloc_code_real reloc_type;
7535 int size = disp_size (n);
7536 int sign = i.types[n].bitfield.disp32s;
7537 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
7538 fixS *fixP;
7539
7540 /* We can't have 8 bit displacement here. */
7541 gas_assert (!i.types[n].bitfield.disp8);
7542
7543 /* The PC relative address is computed relative
7544 to the instruction boundary, so in case immediate
7545 fields follows, we need to adjust the value. */
7546 if (pcrel && i.imm_operands)
7547 {
7548 unsigned int n1;
7549 int sz = 0;
7550
7551 for (n1 = 0; n1 < i.operands; n1++)
7552 if (operand_type_check (i.types[n1], imm))
7553 {
7554 /* Only one immediate is allowed for PC
7555 relative address. */
7556 gas_assert (sz == 0);
7557 sz = imm_size (n1);
7558 i.op[n].disps->X_add_number -= sz;
7559 }
7560 /* We should find the immediate. */
7561 gas_assert (sz != 0);
7562 }
7563
7564 p = frag_more (size);
7565 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
7566 if (GOT_symbol
7567 && GOT_symbol == i.op[n].disps->X_add_symbol
7568 && (((reloc_type == BFD_RELOC_32
7569 || reloc_type == BFD_RELOC_X86_64_32S
7570 || (reloc_type == BFD_RELOC_64
7571 && object_64bit))
7572 && (i.op[n].disps->X_op == O_symbol
7573 || (i.op[n].disps->X_op == O_add
7574 && ((symbol_get_value_expression
7575 (i.op[n].disps->X_op_symbol)->X_op)
7576 == O_subtract))))
7577 || reloc_type == BFD_RELOC_32_PCREL))
7578 {
7579 offsetT add;
7580
7581 if (insn_start_frag == frag_now)
7582 add = (p - frag_now->fr_literal) - insn_start_off;
7583 else
7584 {
7585 fragS *fr;
7586
7587 add = insn_start_frag->fr_fix - insn_start_off;
7588 for (fr = insn_start_frag->fr_next;
7589 fr && fr != frag_now; fr = fr->fr_next)
7590 add += fr->fr_fix;
7591 add += p - frag_now->fr_literal;
7592 }
7593
7594 if (!object_64bit)
7595 {
7596 reloc_type = BFD_RELOC_386_GOTPC;
7597 i.op[n].imms->X_add_number += add;
7598 }
7599 else if (reloc_type == BFD_RELOC_64)
7600 reloc_type = BFD_RELOC_X86_64_GOTPC64;
7601 else
7602 /* Don't do the adjustment for x86-64, as there
7603 the pcrel addressing is relative to the _next_
7604 insn, and that is taken care of in other code. */
7605 reloc_type = BFD_RELOC_X86_64_GOTPC32;
7606 }
7607 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal,
7608 size, i.op[n].disps, pcrel,
7609 reloc_type);
7610 /* Check for "call/jmp *mem", "mov mem, %reg",
7611 "test %reg, mem" and "binop mem, %reg" where binop
7612 is one of adc, add, and, cmp, or, sbb, sub, xor
7613 instructions. Always generate R_386_GOT32X for
7614 "sym*GOT" operand in 32-bit mode. */
7615 if ((generate_relax_relocations
7616 || (!object_64bit
7617 && i.rm.mode == 0
7618 && i.rm.regmem == 5))
7619 && (i.rm.mode == 2
7620 || (i.rm.mode == 0 && i.rm.regmem == 5))
7621 && ((i.operands == 1
7622 && i.tm.base_opcode == 0xff
7623 && (i.rm.reg == 2 || i.rm.reg == 4))
7624 || (i.operands == 2
7625 && (i.tm.base_opcode == 0x8b
7626 || i.tm.base_opcode == 0x85
7627 || (i.tm.base_opcode & 0xc7) == 0x03))))
7628 {
7629 if (object_64bit)
7630 {
7631 fixP->fx_tcbit = i.rex != 0;
7632 if (i.base_reg
7633 && (i.base_reg->reg_num == RegRip
7634 || i.base_reg->reg_num == RegEip))
7635 fixP->fx_tcbit2 = 1;
7636 }
7637 else
7638 fixP->fx_tcbit2 = 1;
7639 }
7640 }
7641 }
7642 }
7643 }
7644
7645 static void
7646 output_imm (fragS *insn_start_frag, offsetT insn_start_off)
7647 {
7648 char *p;
7649 unsigned int n;
7650
7651 for (n = 0; n < i.operands; n++)
7652 {
7653 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
7654 if (i.rounding && (int) n == i.rounding->operand)
7655 continue;
7656
7657 if (operand_type_check (i.types[n], imm))
7658 {
7659 if (i.op[n].imms->X_op == O_constant)
7660 {
7661 int size = imm_size (n);
7662 offsetT val;
7663
7664 val = offset_in_range (i.op[n].imms->X_add_number,
7665 size);
7666 p = frag_more (size);
7667 md_number_to_chars (p, val, size);
7668 }
7669 else
7670 {
7671 /* Not absolute_section.
7672 Need a 32-bit fixup (don't support 8bit
7673 non-absolute imms). Try to support other
7674 sizes ... */
7675 enum bfd_reloc_code_real reloc_type;
7676 int size = imm_size (n);
7677 int sign;
7678
7679 if (i.types[n].bitfield.imm32s
7680 && (i.suffix == QWORD_MNEM_SUFFIX
7681 || (!i.suffix && i.tm.opcode_modifier.no_lsuf)))
7682 sign = 1;
7683 else
7684 sign = 0;
7685
7686 p = frag_more (size);
7687 reloc_type = reloc (size, 0, sign, i.reloc[n]);
7688
7689 /* This is tough to explain. We end up with this one if we
7690 * have operands that look like
7691 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
7692 * obtain the absolute address of the GOT, and it is strongly
7693 * preferable from a performance point of view to avoid using
7694 * a runtime relocation for this. The actual sequence of
7695 * instructions often look something like:
7696 *
7697 * call .L66
7698 * .L66:
7699 * popl %ebx
7700 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
7701 *
7702 * The call and pop essentially return the absolute address
7703 * of the label .L66 and store it in %ebx. The linker itself
7704 * will ultimately change the first operand of the addl so
7705 * that %ebx points to the GOT, but to keep things simple, the
7706 * .o file must have this operand set so that it generates not
7707 * the absolute address of .L66, but the absolute address of
7708 * itself. This allows the linker itself simply treat a GOTPC
7709 * relocation as asking for a pcrel offset to the GOT to be
7710 * added in, and the addend of the relocation is stored in the
7711 * operand field for the instruction itself.
7712 *
7713 * Our job here is to fix the operand so that it would add
7714 * the correct offset so that %ebx would point to itself. The
7715 * thing that is tricky is that .-.L66 will point to the
7716 * beginning of the instruction, so we need to further modify
7717 * the operand so that it will point to itself. There are
7718 * other cases where you have something like:
7719 *
7720 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
7721 *
7722 * and here no correction would be required. Internally in
7723 * the assembler we treat operands of this form as not being
7724 * pcrel since the '.' is explicitly mentioned, and I wonder
7725 * whether it would simplify matters to do it this way. Who
7726 * knows. In earlier versions of the PIC patches, the
7727 * pcrel_adjust field was used to store the correction, but
7728 * since the expression is not pcrel, I felt it would be
7729 * confusing to do it this way. */
7730
7731 if ((reloc_type == BFD_RELOC_32
7732 || reloc_type == BFD_RELOC_X86_64_32S
7733 || reloc_type == BFD_RELOC_64)
7734 && GOT_symbol
7735 && GOT_symbol == i.op[n].imms->X_add_symbol
7736 && (i.op[n].imms->X_op == O_symbol
7737 || (i.op[n].imms->X_op == O_add
7738 && ((symbol_get_value_expression
7739 (i.op[n].imms->X_op_symbol)->X_op)
7740 == O_subtract))))
7741 {
7742 offsetT add;
7743
7744 if (insn_start_frag == frag_now)
7745 add = (p - frag_now->fr_literal) - insn_start_off;
7746 else
7747 {
7748 fragS *fr;
7749
7750 add = insn_start_frag->fr_fix - insn_start_off;
7751 for (fr = insn_start_frag->fr_next;
7752 fr && fr != frag_now; fr = fr->fr_next)
7753 add += fr->fr_fix;
7754 add += p - frag_now->fr_literal;
7755 }
7756
7757 if (!object_64bit)
7758 reloc_type = BFD_RELOC_386_GOTPC;
7759 else if (size == 4)
7760 reloc_type = BFD_RELOC_X86_64_GOTPC32;
7761 else if (size == 8)
7762 reloc_type = BFD_RELOC_X86_64_GOTPC64;
7763 i.op[n].imms->X_add_number += add;
7764 }
7765 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
7766 i.op[n].imms, 0, reloc_type);
7767 }
7768 }
7769 }
7770 }
7771 \f
7772 /* x86_cons_fix_new is called via the expression parsing code when a
7773 reloc is needed. We use this hook to get the correct .got reloc. */
7774 static int cons_sign = -1;
7775
7776 void
7777 x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len,
7778 expressionS *exp, bfd_reloc_code_real_type r)
7779 {
7780 r = reloc (len, 0, cons_sign, r);
7781
7782 #ifdef TE_PE
7783 if (exp->X_op == O_secrel)
7784 {
7785 exp->X_op = O_symbol;
7786 r = BFD_RELOC_32_SECREL;
7787 }
7788 #endif
7789
7790 fix_new_exp (frag, off, len, exp, 0, r);
7791 }
7792
7793 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
7794 purpose of the `.dc.a' internal pseudo-op. */
7795
7796 int
7797 x86_address_bytes (void)
7798 {
7799 if ((stdoutput->arch_info->mach & bfd_mach_x64_32))
7800 return 4;
7801 return stdoutput->arch_info->bits_per_address / 8;
7802 }
7803
7804 #if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
7805 || defined (LEX_AT)
7806 # define lex_got(reloc, adjust, types) NULL
7807 #else
7808 /* Parse operands of the form
7809 <symbol>@GOTOFF+<nnn>
7810 and similar .plt or .got references.
7811
7812 If we find one, set up the correct relocation in RELOC and copy the
7813 input string, minus the `@GOTOFF' into a malloc'd buffer for
7814 parsing by the calling routine. Return this buffer, and if ADJUST
7815 is non-null set it to the length of the string we removed from the
7816 input line. Otherwise return NULL. */
7817 static char *
7818 lex_got (enum bfd_reloc_code_real *rel,
7819 int *adjust,
7820 i386_operand_type *types)
7821 {
7822 /* Some of the relocations depend on the size of what field is to
7823 be relocated. But in our callers i386_immediate and i386_displacement
7824 we don't yet know the operand size (this will be set by insn
7825 matching). Hence we record the word32 relocation here,
7826 and adjust the reloc according to the real size in reloc(). */
7827 static const struct {
7828 const char *str;
7829 int len;
7830 const enum bfd_reloc_code_real rel[2];
7831 const i386_operand_type types64;
7832 } gotrel[] = {
7833 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7834 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32,
7835 BFD_RELOC_SIZE32 },
7836 OPERAND_TYPE_IMM32_64 },
7837 #endif
7838 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real,
7839 BFD_RELOC_X86_64_PLTOFF64 },
7840 OPERAND_TYPE_IMM64 },
7841 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32,
7842 BFD_RELOC_X86_64_PLT32 },
7843 OPERAND_TYPE_IMM32_32S_DISP32 },
7844 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real,
7845 BFD_RELOC_X86_64_GOTPLT64 },
7846 OPERAND_TYPE_IMM64_DISP64 },
7847 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF,
7848 BFD_RELOC_X86_64_GOTOFF64 },
7849 OPERAND_TYPE_IMM64_DISP64 },
7850 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real,
7851 BFD_RELOC_X86_64_GOTPCREL },
7852 OPERAND_TYPE_IMM32_32S_DISP32 },
7853 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD,
7854 BFD_RELOC_X86_64_TLSGD },
7855 OPERAND_TYPE_IMM32_32S_DISP32 },
7856 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM,
7857 _dummy_first_bfd_reloc_code_real },
7858 OPERAND_TYPE_NONE },
7859 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real,
7860 BFD_RELOC_X86_64_TLSLD },
7861 OPERAND_TYPE_IMM32_32S_DISP32 },
7862 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32,
7863 BFD_RELOC_X86_64_GOTTPOFF },
7864 OPERAND_TYPE_IMM32_32S_DISP32 },
7865 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32,
7866 BFD_RELOC_X86_64_TPOFF32 },
7867 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
7868 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE,
7869 _dummy_first_bfd_reloc_code_real },
7870 OPERAND_TYPE_NONE },
7871 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32,
7872 BFD_RELOC_X86_64_DTPOFF32 },
7873 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
7874 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE,
7875 _dummy_first_bfd_reloc_code_real },
7876 OPERAND_TYPE_NONE },
7877 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE,
7878 _dummy_first_bfd_reloc_code_real },
7879 OPERAND_TYPE_NONE },
7880 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32,
7881 BFD_RELOC_X86_64_GOT32 },
7882 OPERAND_TYPE_IMM32_32S_64_DISP32 },
7883 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC,
7884 BFD_RELOC_X86_64_GOTPC32_TLSDESC },
7885 OPERAND_TYPE_IMM32_32S_DISP32 },
7886 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL,
7887 BFD_RELOC_X86_64_TLSDESC_CALL },
7888 OPERAND_TYPE_IMM32_32S_DISP32 },
7889 };
7890 char *cp;
7891 unsigned int j;
7892
7893 #if defined (OBJ_MAYBE_ELF)
7894 if (!IS_ELF)
7895 return NULL;
7896 #endif
7897
7898 for (cp = input_line_pointer; *cp != '@'; cp++)
7899 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
7900 return NULL;
7901
7902 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
7903 {
7904 int len = gotrel[j].len;
7905 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
7906 {
7907 if (gotrel[j].rel[object_64bit] != 0)
7908 {
7909 int first, second;
7910 char *tmpbuf, *past_reloc;
7911
7912 *rel = gotrel[j].rel[object_64bit];
7913
7914 if (types)
7915 {
7916 if (flag_code != CODE_64BIT)
7917 {
7918 types->bitfield.imm32 = 1;
7919 types->bitfield.disp32 = 1;
7920 }
7921 else
7922 *types = gotrel[j].types64;
7923 }
7924
7925 if (j != 0 && GOT_symbol == NULL)
7926 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
7927
7928 /* The length of the first part of our input line. */
7929 first = cp - input_line_pointer;
7930
7931 /* The second part goes from after the reloc token until
7932 (and including) an end_of_line char or comma. */
7933 past_reloc = cp + 1 + len;
7934 cp = past_reloc;
7935 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
7936 ++cp;
7937 second = cp + 1 - past_reloc;
7938
7939 /* Allocate and copy string. The trailing NUL shouldn't
7940 be necessary, but be safe. */
7941 tmpbuf = XNEWVEC (char, first + second + 2);
7942 memcpy (tmpbuf, input_line_pointer, first);
7943 if (second != 0 && *past_reloc != ' ')
7944 /* Replace the relocation token with ' ', so that
7945 errors like foo@GOTOFF1 will be detected. */
7946 tmpbuf[first++] = ' ';
7947 else
7948 /* Increment length by 1 if the relocation token is
7949 removed. */
7950 len++;
7951 if (adjust)
7952 *adjust = len;
7953 memcpy (tmpbuf + first, past_reloc, second);
7954 tmpbuf[first + second] = '\0';
7955 return tmpbuf;
7956 }
7957
7958 as_bad (_("@%s reloc is not supported with %d-bit output format"),
7959 gotrel[j].str, 1 << (5 + object_64bit));
7960 return NULL;
7961 }
7962 }
7963
7964 /* Might be a symbol version string. Don't as_bad here. */
7965 return NULL;
7966 }
7967 #endif
7968
7969 #ifdef TE_PE
7970 #ifdef lex_got
7971 #undef lex_got
7972 #endif
7973 /* Parse operands of the form
7974 <symbol>@SECREL32+<nnn>
7975
7976 If we find one, set up the correct relocation in RELOC and copy the
7977 input string, minus the `@SECREL32' into a malloc'd buffer for
7978 parsing by the calling routine. Return this buffer, and if ADJUST
7979 is non-null set it to the length of the string we removed from the
7980 input line. Otherwise return NULL.
7981
7982 This function is copied from the ELF version above adjusted for PE targets. */
7983
7984 static char *
7985 lex_got (enum bfd_reloc_code_real *rel ATTRIBUTE_UNUSED,
7986 int *adjust ATTRIBUTE_UNUSED,
7987 i386_operand_type *types)
7988 {
7989 static const struct
7990 {
7991 const char *str;
7992 int len;
7993 const enum bfd_reloc_code_real rel[2];
7994 const i386_operand_type types64;
7995 }
7996 gotrel[] =
7997 {
7998 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL,
7999 BFD_RELOC_32_SECREL },
8000 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
8001 };
8002
8003 char *cp;
8004 unsigned j;
8005
8006 for (cp = input_line_pointer; *cp != '@'; cp++)
8007 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
8008 return NULL;
8009
8010 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
8011 {
8012 int len = gotrel[j].len;
8013
8014 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
8015 {
8016 if (gotrel[j].rel[object_64bit] != 0)
8017 {
8018 int first, second;
8019 char *tmpbuf, *past_reloc;
8020
8021 *rel = gotrel[j].rel[object_64bit];
8022 if (adjust)
8023 *adjust = len;
8024
8025 if (types)
8026 {
8027 if (flag_code != CODE_64BIT)
8028 {
8029 types->bitfield.imm32 = 1;
8030 types->bitfield.disp32 = 1;
8031 }
8032 else
8033 *types = gotrel[j].types64;
8034 }
8035
8036 /* The length of the first part of our input line. */
8037 first = cp - input_line_pointer;
8038
8039 /* The second part goes from after the reloc token until
8040 (and including) an end_of_line char or comma. */
8041 past_reloc = cp + 1 + len;
8042 cp = past_reloc;
8043 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
8044 ++cp;
8045 second = cp + 1 - past_reloc;
8046
8047 /* Allocate and copy string. The trailing NUL shouldn't
8048 be necessary, but be safe. */
8049 tmpbuf = XNEWVEC (char, first + second + 2);
8050 memcpy (tmpbuf, input_line_pointer, first);
8051 if (second != 0 && *past_reloc != ' ')
8052 /* Replace the relocation token with ' ', so that
8053 errors like foo@SECLREL321 will be detected. */
8054 tmpbuf[first++] = ' ';
8055 memcpy (tmpbuf + first, past_reloc, second);
8056 tmpbuf[first + second] = '\0';
8057 return tmpbuf;
8058 }
8059
8060 as_bad (_("@%s reloc is not supported with %d-bit output format"),
8061 gotrel[j].str, 1 << (5 + object_64bit));
8062 return NULL;
8063 }
8064 }
8065
8066 /* Might be a symbol version string. Don't as_bad here. */
8067 return NULL;
8068 }
8069
8070 #endif /* TE_PE */
8071
8072 bfd_reloc_code_real_type
8073 x86_cons (expressionS *exp, int size)
8074 {
8075 bfd_reloc_code_real_type got_reloc = NO_RELOC;
8076
8077 intel_syntax = -intel_syntax;
8078
8079 exp->X_md = 0;
8080 if (size == 4 || (object_64bit && size == 8))
8081 {
8082 /* Handle @GOTOFF and the like in an expression. */
8083 char *save;
8084 char *gotfree_input_line;
8085 int adjust = 0;
8086
8087 save = input_line_pointer;
8088 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
8089 if (gotfree_input_line)
8090 input_line_pointer = gotfree_input_line;
8091
8092 expression (exp);
8093
8094 if (gotfree_input_line)
8095 {
8096 /* expression () has merrily parsed up to the end of line,
8097 or a comma - in the wrong buffer. Transfer how far
8098 input_line_pointer has moved to the right buffer. */
8099 input_line_pointer = (save
8100 + (input_line_pointer - gotfree_input_line)
8101 + adjust);
8102 free (gotfree_input_line);
8103 if (exp->X_op == O_constant
8104 || exp->X_op == O_absent
8105 || exp->X_op == O_illegal
8106 || exp->X_op == O_register
8107 || exp->X_op == O_big)
8108 {
8109 char c = *input_line_pointer;
8110 *input_line_pointer = 0;
8111 as_bad (_("missing or invalid expression `%s'"), save);
8112 *input_line_pointer = c;
8113 }
8114 }
8115 }
8116 else
8117 expression (exp);
8118
8119 intel_syntax = -intel_syntax;
8120
8121 if (intel_syntax)
8122 i386_intel_simplify (exp);
8123
8124 return got_reloc;
8125 }
8126
8127 static void
8128 signed_cons (int size)
8129 {
8130 if (flag_code == CODE_64BIT)
8131 cons_sign = 1;
8132 cons (size);
8133 cons_sign = -1;
8134 }
8135
8136 #ifdef TE_PE
8137 static void
8138 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED)
8139 {
8140 expressionS exp;
8141
8142 do
8143 {
8144 expression (&exp);
8145 if (exp.X_op == O_symbol)
8146 exp.X_op = O_secrel;
8147
8148 emit_expr (&exp, 4);
8149 }
8150 while (*input_line_pointer++ == ',');
8151
8152 input_line_pointer--;
8153 demand_empty_rest_of_line ();
8154 }
8155 #endif
8156
8157 /* Handle Vector operations. */
8158
8159 static char *
8160 check_VecOperations (char *op_string, char *op_end)
8161 {
8162 const reg_entry *mask;
8163 const char *saved;
8164 char *end_op;
8165
8166 while (*op_string
8167 && (op_end == NULL || op_string < op_end))
8168 {
8169 saved = op_string;
8170 if (*op_string == '{')
8171 {
8172 op_string++;
8173
8174 /* Check broadcasts. */
8175 if (strncmp (op_string, "1to", 3) == 0)
8176 {
8177 int bcst_type;
8178
8179 if (i.broadcast)
8180 goto duplicated_vec_op;
8181
8182 op_string += 3;
8183 if (*op_string == '8')
8184 bcst_type = BROADCAST_1TO8;
8185 else if (*op_string == '4')
8186 bcst_type = BROADCAST_1TO4;
8187 else if (*op_string == '2')
8188 bcst_type = BROADCAST_1TO2;
8189 else if (*op_string == '1'
8190 && *(op_string+1) == '6')
8191 {
8192 bcst_type = BROADCAST_1TO16;
8193 op_string++;
8194 }
8195 else
8196 {
8197 as_bad (_("Unsupported broadcast: `%s'"), saved);
8198 return NULL;
8199 }
8200 op_string++;
8201
8202 broadcast_op.type = bcst_type;
8203 broadcast_op.operand = this_operand;
8204 i.broadcast = &broadcast_op;
8205 }
8206 /* Check masking operation. */
8207 else if ((mask = parse_register (op_string, &end_op)) != NULL)
8208 {
8209 /* k0 can't be used for write mask. */
8210 if (!mask->reg_type.bitfield.regmask || mask->reg_num == 0)
8211 {
8212 as_bad (_("`%s%s' can't be used for write mask"),
8213 register_prefix, mask->reg_name);
8214 return NULL;
8215 }
8216
8217 if (!i.mask)
8218 {
8219 mask_op.mask = mask;
8220 mask_op.zeroing = 0;
8221 mask_op.operand = this_operand;
8222 i.mask = &mask_op;
8223 }
8224 else
8225 {
8226 if (i.mask->mask)
8227 goto duplicated_vec_op;
8228
8229 i.mask->mask = mask;
8230
8231 /* Only "{z}" is allowed here. No need to check
8232 zeroing mask explicitly. */
8233 if (i.mask->operand != this_operand)
8234 {
8235 as_bad (_("invalid write mask `%s'"), saved);
8236 return NULL;
8237 }
8238 }
8239
8240 op_string = end_op;
8241 }
8242 /* Check zeroing-flag for masking operation. */
8243 else if (*op_string == 'z')
8244 {
8245 if (!i.mask)
8246 {
8247 mask_op.mask = NULL;
8248 mask_op.zeroing = 1;
8249 mask_op.operand = this_operand;
8250 i.mask = &mask_op;
8251 }
8252 else
8253 {
8254 if (i.mask->zeroing)
8255 {
8256 duplicated_vec_op:
8257 as_bad (_("duplicated `%s'"), saved);
8258 return NULL;
8259 }
8260
8261 i.mask->zeroing = 1;
8262
8263 /* Only "{%k}" is allowed here. No need to check mask
8264 register explicitly. */
8265 if (i.mask->operand != this_operand)
8266 {
8267 as_bad (_("invalid zeroing-masking `%s'"),
8268 saved);
8269 return NULL;
8270 }
8271 }
8272
8273 op_string++;
8274 }
8275 else
8276 goto unknown_vec_op;
8277
8278 if (*op_string != '}')
8279 {
8280 as_bad (_("missing `}' in `%s'"), saved);
8281 return NULL;
8282 }
8283 op_string++;
8284 continue;
8285 }
8286 unknown_vec_op:
8287 /* We don't know this one. */
8288 as_bad (_("unknown vector operation: `%s'"), saved);
8289 return NULL;
8290 }
8291
8292 if (i.mask && i.mask->zeroing && !i.mask->mask)
8293 {
8294 as_bad (_("zeroing-masking only allowed with write mask"));
8295 return NULL;
8296 }
8297
8298 return op_string;
8299 }
8300
8301 static int
8302 i386_immediate (char *imm_start)
8303 {
8304 char *save_input_line_pointer;
8305 char *gotfree_input_line;
8306 segT exp_seg = 0;
8307 expressionS *exp;
8308 i386_operand_type types;
8309
8310 operand_type_set (&types, ~0);
8311
8312 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
8313 {
8314 as_bad (_("at most %d immediate operands are allowed"),
8315 MAX_IMMEDIATE_OPERANDS);
8316 return 0;
8317 }
8318
8319 exp = &im_expressions[i.imm_operands++];
8320 i.op[this_operand].imms = exp;
8321
8322 if (is_space_char (*imm_start))
8323 ++imm_start;
8324
8325 save_input_line_pointer = input_line_pointer;
8326 input_line_pointer = imm_start;
8327
8328 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
8329 if (gotfree_input_line)
8330 input_line_pointer = gotfree_input_line;
8331
8332 exp_seg = expression (exp);
8333
8334 SKIP_WHITESPACE ();
8335
8336 /* Handle vector operations. */
8337 if (*input_line_pointer == '{')
8338 {
8339 input_line_pointer = check_VecOperations (input_line_pointer,
8340 NULL);
8341 if (input_line_pointer == NULL)
8342 return 0;
8343 }
8344
8345 if (*input_line_pointer)
8346 as_bad (_("junk `%s' after expression"), input_line_pointer);
8347
8348 input_line_pointer = save_input_line_pointer;
8349 if (gotfree_input_line)
8350 {
8351 free (gotfree_input_line);
8352
8353 if (exp->X_op == O_constant || exp->X_op == O_register)
8354 exp->X_op = O_illegal;
8355 }
8356
8357 return i386_finalize_immediate (exp_seg, exp, types, imm_start);
8358 }
8359
8360 static int
8361 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
8362 i386_operand_type types, const char *imm_start)
8363 {
8364 if (exp->X_op == O_absent || exp->X_op == O_illegal || exp->X_op == O_big)
8365 {
8366 if (imm_start)
8367 as_bad (_("missing or invalid immediate expression `%s'"),
8368 imm_start);
8369 return 0;
8370 }
8371 else if (exp->X_op == O_constant)
8372 {
8373 /* Size it properly later. */
8374 i.types[this_operand].bitfield.imm64 = 1;
8375 /* If not 64bit, sign extend val. */
8376 if (flag_code != CODE_64BIT
8377 && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
8378 exp->X_add_number
8379 = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
8380 }
8381 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8382 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
8383 && exp_seg != absolute_section
8384 && exp_seg != text_section
8385 && exp_seg != data_section
8386 && exp_seg != bss_section
8387 && exp_seg != undefined_section
8388 && !bfd_is_com_section (exp_seg))
8389 {
8390 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
8391 return 0;
8392 }
8393 #endif
8394 else if (!intel_syntax && exp_seg == reg_section)
8395 {
8396 if (imm_start)
8397 as_bad (_("illegal immediate register operand %s"), imm_start);
8398 return 0;
8399 }
8400 else
8401 {
8402 /* This is an address. The size of the address will be
8403 determined later, depending on destination register,
8404 suffix, or the default for the section. */
8405 i.types[this_operand].bitfield.imm8 = 1;
8406 i.types[this_operand].bitfield.imm16 = 1;
8407 i.types[this_operand].bitfield.imm32 = 1;
8408 i.types[this_operand].bitfield.imm32s = 1;
8409 i.types[this_operand].bitfield.imm64 = 1;
8410 i.types[this_operand] = operand_type_and (i.types[this_operand],
8411 types);
8412 }
8413
8414 return 1;
8415 }
8416
8417 static char *
8418 i386_scale (char *scale)
8419 {
8420 offsetT val;
8421 char *save = input_line_pointer;
8422
8423 input_line_pointer = scale;
8424 val = get_absolute_expression ();
8425
8426 switch (val)
8427 {
8428 case 1:
8429 i.log2_scale_factor = 0;
8430 break;
8431 case 2:
8432 i.log2_scale_factor = 1;
8433 break;
8434 case 4:
8435 i.log2_scale_factor = 2;
8436 break;
8437 case 8:
8438 i.log2_scale_factor = 3;
8439 break;
8440 default:
8441 {
8442 char sep = *input_line_pointer;
8443
8444 *input_line_pointer = '\0';
8445 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
8446 scale);
8447 *input_line_pointer = sep;
8448 input_line_pointer = save;
8449 return NULL;
8450 }
8451 }
8452 if (i.log2_scale_factor != 0 && i.index_reg == 0)
8453 {
8454 as_warn (_("scale factor of %d without an index register"),
8455 1 << i.log2_scale_factor);
8456 i.log2_scale_factor = 0;
8457 }
8458 scale = input_line_pointer;
8459 input_line_pointer = save;
8460 return scale;
8461 }
8462
8463 static int
8464 i386_displacement (char *disp_start, char *disp_end)
8465 {
8466 expressionS *exp;
8467 segT exp_seg = 0;
8468 char *save_input_line_pointer;
8469 char *gotfree_input_line;
8470 int override;
8471 i386_operand_type bigdisp, types = anydisp;
8472 int ret;
8473
8474 if (i.disp_operands == MAX_MEMORY_OPERANDS)
8475 {
8476 as_bad (_("at most %d displacement operands are allowed"),
8477 MAX_MEMORY_OPERANDS);
8478 return 0;
8479 }
8480
8481 operand_type_set (&bigdisp, 0);
8482 if ((i.types[this_operand].bitfield.jumpabsolute)
8483 || (!current_templates->start->opcode_modifier.jump
8484 && !current_templates->start->opcode_modifier.jumpdword))
8485 {
8486 bigdisp.bitfield.disp32 = 1;
8487 override = (i.prefix[ADDR_PREFIX] != 0);
8488 if (flag_code == CODE_64BIT)
8489 {
8490 if (!override)
8491 {
8492 bigdisp.bitfield.disp32s = 1;
8493 bigdisp.bitfield.disp64 = 1;
8494 }
8495 }
8496 else if ((flag_code == CODE_16BIT) ^ override)
8497 {
8498 bigdisp.bitfield.disp32 = 0;
8499 bigdisp.bitfield.disp16 = 1;
8500 }
8501 }
8502 else
8503 {
8504 /* For PC-relative branches, the width of the displacement
8505 is dependent upon data size, not address size. */
8506 override = (i.prefix[DATA_PREFIX] != 0);
8507 if (flag_code == CODE_64BIT)
8508 {
8509 if (override || i.suffix == WORD_MNEM_SUFFIX)
8510 bigdisp.bitfield.disp16 = 1;
8511 else
8512 {
8513 bigdisp.bitfield.disp32 = 1;
8514 bigdisp.bitfield.disp32s = 1;
8515 }
8516 }
8517 else
8518 {
8519 if (!override)
8520 override = (i.suffix == (flag_code != CODE_16BIT
8521 ? WORD_MNEM_SUFFIX
8522 : LONG_MNEM_SUFFIX));
8523 bigdisp.bitfield.disp32 = 1;
8524 if ((flag_code == CODE_16BIT) ^ override)
8525 {
8526 bigdisp.bitfield.disp32 = 0;
8527 bigdisp.bitfield.disp16 = 1;
8528 }
8529 }
8530 }
8531 i.types[this_operand] = operand_type_or (i.types[this_operand],
8532 bigdisp);
8533
8534 exp = &disp_expressions[i.disp_operands];
8535 i.op[this_operand].disps = exp;
8536 i.disp_operands++;
8537 save_input_line_pointer = input_line_pointer;
8538 input_line_pointer = disp_start;
8539 END_STRING_AND_SAVE (disp_end);
8540
8541 #ifndef GCC_ASM_O_HACK
8542 #define GCC_ASM_O_HACK 0
8543 #endif
8544 #if GCC_ASM_O_HACK
8545 END_STRING_AND_SAVE (disp_end + 1);
8546 if (i.types[this_operand].bitfield.baseIndex
8547 && displacement_string_end[-1] == '+')
8548 {
8549 /* This hack is to avoid a warning when using the "o"
8550 constraint within gcc asm statements.
8551 For instance:
8552
8553 #define _set_tssldt_desc(n,addr,limit,type) \
8554 __asm__ __volatile__ ( \
8555 "movw %w2,%0\n\t" \
8556 "movw %w1,2+%0\n\t" \
8557 "rorl $16,%1\n\t" \
8558 "movb %b1,4+%0\n\t" \
8559 "movb %4,5+%0\n\t" \
8560 "movb $0,6+%0\n\t" \
8561 "movb %h1,7+%0\n\t" \
8562 "rorl $16,%1" \
8563 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
8564
8565 This works great except that the output assembler ends
8566 up looking a bit weird if it turns out that there is
8567 no offset. You end up producing code that looks like:
8568
8569 #APP
8570 movw $235,(%eax)
8571 movw %dx,2+(%eax)
8572 rorl $16,%edx
8573 movb %dl,4+(%eax)
8574 movb $137,5+(%eax)
8575 movb $0,6+(%eax)
8576 movb %dh,7+(%eax)
8577 rorl $16,%edx
8578 #NO_APP
8579
8580 So here we provide the missing zero. */
8581
8582 *displacement_string_end = '0';
8583 }
8584 #endif
8585 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
8586 if (gotfree_input_line)
8587 input_line_pointer = gotfree_input_line;
8588
8589 exp_seg = expression (exp);
8590
8591 SKIP_WHITESPACE ();
8592 if (*input_line_pointer)
8593 as_bad (_("junk `%s' after expression"), input_line_pointer);
8594 #if GCC_ASM_O_HACK
8595 RESTORE_END_STRING (disp_end + 1);
8596 #endif
8597 input_line_pointer = save_input_line_pointer;
8598 if (gotfree_input_line)
8599 {
8600 free (gotfree_input_line);
8601
8602 if (exp->X_op == O_constant || exp->X_op == O_register)
8603 exp->X_op = O_illegal;
8604 }
8605
8606 ret = i386_finalize_displacement (exp_seg, exp, types, disp_start);
8607
8608 RESTORE_END_STRING (disp_end);
8609
8610 return ret;
8611 }
8612
8613 static int
8614 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
8615 i386_operand_type types, const char *disp_start)
8616 {
8617 i386_operand_type bigdisp;
8618 int ret = 1;
8619
8620 /* We do this to make sure that the section symbol is in
8621 the symbol table. We will ultimately change the relocation
8622 to be relative to the beginning of the section. */
8623 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
8624 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
8625 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
8626 {
8627 if (exp->X_op != O_symbol)
8628 goto inv_disp;
8629
8630 if (S_IS_LOCAL (exp->X_add_symbol)
8631 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section
8632 && S_GET_SEGMENT (exp->X_add_symbol) != expr_section)
8633 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
8634 exp->X_op = O_subtract;
8635 exp->X_op_symbol = GOT_symbol;
8636 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
8637 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
8638 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
8639 i.reloc[this_operand] = BFD_RELOC_64;
8640 else
8641 i.reloc[this_operand] = BFD_RELOC_32;
8642 }
8643
8644 else if (exp->X_op == O_absent
8645 || exp->X_op == O_illegal
8646 || exp->X_op == O_big)
8647 {
8648 inv_disp:
8649 as_bad (_("missing or invalid displacement expression `%s'"),
8650 disp_start);
8651 ret = 0;
8652 }
8653
8654 else if (flag_code == CODE_64BIT
8655 && !i.prefix[ADDR_PREFIX]
8656 && exp->X_op == O_constant)
8657 {
8658 /* Since displacement is signed extended to 64bit, don't allow
8659 disp32 and turn off disp32s if they are out of range. */
8660 i.types[this_operand].bitfield.disp32 = 0;
8661 if (!fits_in_signed_long (exp->X_add_number))
8662 {
8663 i.types[this_operand].bitfield.disp32s = 0;
8664 if (i.types[this_operand].bitfield.baseindex)
8665 {
8666 as_bad (_("0x%lx out range of signed 32bit displacement"),
8667 (long) exp->X_add_number);
8668 ret = 0;
8669 }
8670 }
8671 }
8672
8673 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8674 else if (exp->X_op != O_constant
8675 && OUTPUT_FLAVOR == bfd_target_aout_flavour
8676 && exp_seg != absolute_section
8677 && exp_seg != text_section
8678 && exp_seg != data_section
8679 && exp_seg != bss_section
8680 && exp_seg != undefined_section
8681 && !bfd_is_com_section (exp_seg))
8682 {
8683 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
8684 ret = 0;
8685 }
8686 #endif
8687
8688 /* Check if this is a displacement only operand. */
8689 bigdisp = i.types[this_operand];
8690 bigdisp.bitfield.disp8 = 0;
8691 bigdisp.bitfield.disp16 = 0;
8692 bigdisp.bitfield.disp32 = 0;
8693 bigdisp.bitfield.disp32s = 0;
8694 bigdisp.bitfield.disp64 = 0;
8695 if (operand_type_all_zero (&bigdisp))
8696 i.types[this_operand] = operand_type_and (i.types[this_operand],
8697 types);
8698
8699 return ret;
8700 }
8701
8702 /* Return the active addressing mode, taking address override and
8703 registers forming the address into consideration. Update the
8704 address override prefix if necessary. */
8705
8706 static enum flag_code
8707 i386_addressing_mode (void)
8708 {
8709 enum flag_code addr_mode;
8710
8711 if (i.prefix[ADDR_PREFIX])
8712 addr_mode = flag_code == CODE_32BIT ? CODE_16BIT : CODE_32BIT;
8713 else
8714 {
8715 addr_mode = flag_code;
8716
8717 #if INFER_ADDR_PREFIX
8718 if (i.mem_operands == 0)
8719 {
8720 /* Infer address prefix from the first memory operand. */
8721 const reg_entry *addr_reg = i.base_reg;
8722
8723 if (addr_reg == NULL)
8724 addr_reg = i.index_reg;
8725
8726 if (addr_reg)
8727 {
8728 if (addr_reg->reg_num == RegEip
8729 || addr_reg->reg_num == RegEiz
8730 || addr_reg->reg_type.bitfield.dword)
8731 addr_mode = CODE_32BIT;
8732 else if (flag_code != CODE_64BIT
8733 && addr_reg->reg_type.bitfield.word)
8734 addr_mode = CODE_16BIT;
8735
8736 if (addr_mode != flag_code)
8737 {
8738 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
8739 i.prefixes += 1;
8740 /* Change the size of any displacement too. At most one
8741 of Disp16 or Disp32 is set.
8742 FIXME. There doesn't seem to be any real need for
8743 separate Disp16 and Disp32 flags. The same goes for
8744 Imm16 and Imm32. Removing them would probably clean
8745 up the code quite a lot. */
8746 if (flag_code != CODE_64BIT
8747 && (i.types[this_operand].bitfield.disp16
8748 || i.types[this_operand].bitfield.disp32))
8749 i.types[this_operand]
8750 = operand_type_xor (i.types[this_operand], disp16_32);
8751 }
8752 }
8753 }
8754 #endif
8755 }
8756
8757 return addr_mode;
8758 }
8759
8760 /* Make sure the memory operand we've been dealt is valid.
8761 Return 1 on success, 0 on a failure. */
8762
8763 static int
8764 i386_index_check (const char *operand_string)
8765 {
8766 const char *kind = "base/index";
8767 enum flag_code addr_mode = i386_addressing_mode ();
8768
8769 if (current_templates->start->opcode_modifier.isstring
8770 && !current_templates->start->opcode_modifier.immext
8771 && (current_templates->end[-1].opcode_modifier.isstring
8772 || i.mem_operands))
8773 {
8774 /* Memory operands of string insns are special in that they only allow
8775 a single register (rDI, rSI, or rBX) as their memory address. */
8776 const reg_entry *expected_reg;
8777 static const char *di_si[][2] =
8778 {
8779 { "esi", "edi" },
8780 { "si", "di" },
8781 { "rsi", "rdi" }
8782 };
8783 static const char *bx[] = { "ebx", "bx", "rbx" };
8784
8785 kind = "string address";
8786
8787 if (current_templates->start->opcode_modifier.repprefixok)
8788 {
8789 i386_operand_type type = current_templates->end[-1].operand_types[0];
8790
8791 if (!type.bitfield.baseindex
8792 || ((!i.mem_operands != !intel_syntax)
8793 && current_templates->end[-1].operand_types[1]
8794 .bitfield.baseindex))
8795 type = current_templates->end[-1].operand_types[1];
8796 expected_reg = hash_find (reg_hash,
8797 di_si[addr_mode][type.bitfield.esseg]);
8798
8799 }
8800 else
8801 expected_reg = hash_find (reg_hash, bx[addr_mode]);
8802
8803 if (i.base_reg != expected_reg
8804 || i.index_reg
8805 || operand_type_check (i.types[this_operand], disp))
8806 {
8807 /* The second memory operand must have the same size as
8808 the first one. */
8809 if (i.mem_operands
8810 && i.base_reg
8811 && !((addr_mode == CODE_64BIT
8812 && i.base_reg->reg_type.bitfield.qword)
8813 || (addr_mode == CODE_32BIT
8814 ? i.base_reg->reg_type.bitfield.dword
8815 : i.base_reg->reg_type.bitfield.word)))
8816 goto bad_address;
8817
8818 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
8819 operand_string,
8820 intel_syntax ? '[' : '(',
8821 register_prefix,
8822 expected_reg->reg_name,
8823 intel_syntax ? ']' : ')');
8824 return 1;
8825 }
8826 else
8827 return 1;
8828
8829 bad_address:
8830 as_bad (_("`%s' is not a valid %s expression"),
8831 operand_string, kind);
8832 return 0;
8833 }
8834 else
8835 {
8836 if (addr_mode != CODE_16BIT)
8837 {
8838 /* 32-bit/64-bit checks. */
8839 if ((i.base_reg
8840 && (addr_mode == CODE_64BIT
8841 ? !i.base_reg->reg_type.bitfield.qword
8842 : !i.base_reg->reg_type.bitfield.dword)
8843 && (i.index_reg
8844 || (i.base_reg->reg_num
8845 != (addr_mode == CODE_64BIT ? RegRip : RegEip))))
8846 || (i.index_reg
8847 && !i.index_reg->reg_type.bitfield.xmmword
8848 && !i.index_reg->reg_type.bitfield.ymmword
8849 && !i.index_reg->reg_type.bitfield.zmmword
8850 && ((addr_mode == CODE_64BIT
8851 ? !(i.index_reg->reg_type.bitfield.qword
8852 || i.index_reg->reg_num == RegRiz)
8853 : !(i.index_reg->reg_type.bitfield.dword
8854 || i.index_reg->reg_num == RegEiz))
8855 || !i.index_reg->reg_type.bitfield.baseindex)))
8856 goto bad_address;
8857
8858 /* bndmk, bndldx, and bndstx have special restrictions. */
8859 if (current_templates->start->base_opcode == 0xf30f1b
8860 || (current_templates->start->base_opcode & ~1) == 0x0f1a)
8861 {
8862 /* They cannot use RIP-relative addressing. */
8863 if (i.base_reg && i.base_reg->reg_num == RegRip)
8864 {
8865 as_bad (_("`%s' cannot be used here"), operand_string);
8866 return 0;
8867 }
8868
8869 /* bndldx and bndstx ignore their scale factor. */
8870 if (current_templates->start->base_opcode != 0xf30f1b
8871 && i.log2_scale_factor)
8872 as_warn (_("register scaling is being ignored here"));
8873 }
8874 }
8875 else
8876 {
8877 /* 16-bit checks. */
8878 if ((i.base_reg
8879 && (!i.base_reg->reg_type.bitfield.word
8880 || !i.base_reg->reg_type.bitfield.baseindex))
8881 || (i.index_reg
8882 && (!i.index_reg->reg_type.bitfield.word
8883 || !i.index_reg->reg_type.bitfield.baseindex
8884 || !(i.base_reg
8885 && i.base_reg->reg_num < 6
8886 && i.index_reg->reg_num >= 6
8887 && i.log2_scale_factor == 0))))
8888 goto bad_address;
8889 }
8890 }
8891 return 1;
8892 }
8893
8894 /* Handle vector immediates. */
8895
8896 static int
8897 RC_SAE_immediate (const char *imm_start)
8898 {
8899 unsigned int match_found, j;
8900 const char *pstr = imm_start;
8901 expressionS *exp;
8902
8903 if (*pstr != '{')
8904 return 0;
8905
8906 pstr++;
8907 match_found = 0;
8908 for (j = 0; j < ARRAY_SIZE (RC_NamesTable); j++)
8909 {
8910 if (!strncmp (pstr, RC_NamesTable[j].name, RC_NamesTable[j].len))
8911 {
8912 if (!i.rounding)
8913 {
8914 rc_op.type = RC_NamesTable[j].type;
8915 rc_op.operand = this_operand;
8916 i.rounding = &rc_op;
8917 }
8918 else
8919 {
8920 as_bad (_("duplicated `%s'"), imm_start);
8921 return 0;
8922 }
8923 pstr += RC_NamesTable[j].len;
8924 match_found = 1;
8925 break;
8926 }
8927 }
8928 if (!match_found)
8929 return 0;
8930
8931 if (*pstr++ != '}')
8932 {
8933 as_bad (_("Missing '}': '%s'"), imm_start);
8934 return 0;
8935 }
8936 /* RC/SAE immediate string should contain nothing more. */;
8937 if (*pstr != 0)
8938 {
8939 as_bad (_("Junk after '}': '%s'"), imm_start);
8940 return 0;
8941 }
8942
8943 exp = &im_expressions[i.imm_operands++];
8944 i.op[this_operand].imms = exp;
8945
8946 exp->X_op = O_constant;
8947 exp->X_add_number = 0;
8948 exp->X_add_symbol = (symbolS *) 0;
8949 exp->X_op_symbol = (symbolS *) 0;
8950
8951 i.types[this_operand].bitfield.imm8 = 1;
8952 return 1;
8953 }
8954
8955 /* Only string instructions can have a second memory operand, so
8956 reduce current_templates to just those if it contains any. */
8957 static int
8958 maybe_adjust_templates (void)
8959 {
8960 const insn_template *t;
8961
8962 gas_assert (i.mem_operands == 1);
8963
8964 for (t = current_templates->start; t < current_templates->end; ++t)
8965 if (t->opcode_modifier.isstring)
8966 break;
8967
8968 if (t < current_templates->end)
8969 {
8970 static templates aux_templates;
8971 bfd_boolean recheck;
8972
8973 aux_templates.start = t;
8974 for (; t < current_templates->end; ++t)
8975 if (!t->opcode_modifier.isstring)
8976 break;
8977 aux_templates.end = t;
8978
8979 /* Determine whether to re-check the first memory operand. */
8980 recheck = (aux_templates.start != current_templates->start
8981 || t != current_templates->end);
8982
8983 current_templates = &aux_templates;
8984
8985 if (recheck)
8986 {
8987 i.mem_operands = 0;
8988 if (i.memop1_string != NULL
8989 && i386_index_check (i.memop1_string) == 0)
8990 return 0;
8991 i.mem_operands = 1;
8992 }
8993 }
8994
8995 return 1;
8996 }
8997
8998 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
8999 on error. */
9000
9001 static int
9002 i386_att_operand (char *operand_string)
9003 {
9004 const reg_entry *r;
9005 char *end_op;
9006 char *op_string = operand_string;
9007
9008 if (is_space_char (*op_string))
9009 ++op_string;
9010
9011 /* We check for an absolute prefix (differentiating,
9012 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
9013 if (*op_string == ABSOLUTE_PREFIX)
9014 {
9015 ++op_string;
9016 if (is_space_char (*op_string))
9017 ++op_string;
9018 i.types[this_operand].bitfield.jumpabsolute = 1;
9019 }
9020
9021 /* Check if operand is a register. */
9022 if ((r = parse_register (op_string, &end_op)) != NULL)
9023 {
9024 i386_operand_type temp;
9025
9026 /* Check for a segment override by searching for ':' after a
9027 segment register. */
9028 op_string = end_op;
9029 if (is_space_char (*op_string))
9030 ++op_string;
9031 if (*op_string == ':'
9032 && (r->reg_type.bitfield.sreg2
9033 || r->reg_type.bitfield.sreg3))
9034 {
9035 switch (r->reg_num)
9036 {
9037 case 0:
9038 i.seg[i.mem_operands] = &es;
9039 break;
9040 case 1:
9041 i.seg[i.mem_operands] = &cs;
9042 break;
9043 case 2:
9044 i.seg[i.mem_operands] = &ss;
9045 break;
9046 case 3:
9047 i.seg[i.mem_operands] = &ds;
9048 break;
9049 case 4:
9050 i.seg[i.mem_operands] = &fs;
9051 break;
9052 case 5:
9053 i.seg[i.mem_operands] = &gs;
9054 break;
9055 }
9056
9057 /* Skip the ':' and whitespace. */
9058 ++op_string;
9059 if (is_space_char (*op_string))
9060 ++op_string;
9061
9062 if (!is_digit_char (*op_string)
9063 && !is_identifier_char (*op_string)
9064 && *op_string != '('
9065 && *op_string != ABSOLUTE_PREFIX)
9066 {
9067 as_bad (_("bad memory operand `%s'"), op_string);
9068 return 0;
9069 }
9070 /* Handle case of %es:*foo. */
9071 if (*op_string == ABSOLUTE_PREFIX)
9072 {
9073 ++op_string;
9074 if (is_space_char (*op_string))
9075 ++op_string;
9076 i.types[this_operand].bitfield.jumpabsolute = 1;
9077 }
9078 goto do_memory_reference;
9079 }
9080
9081 /* Handle vector operations. */
9082 if (*op_string == '{')
9083 {
9084 op_string = check_VecOperations (op_string, NULL);
9085 if (op_string == NULL)
9086 return 0;
9087 }
9088
9089 if (*op_string)
9090 {
9091 as_bad (_("junk `%s' after register"), op_string);
9092 return 0;
9093 }
9094 temp = r->reg_type;
9095 temp.bitfield.baseindex = 0;
9096 i.types[this_operand] = operand_type_or (i.types[this_operand],
9097 temp);
9098 i.types[this_operand].bitfield.unspecified = 0;
9099 i.op[this_operand].regs = r;
9100 i.reg_operands++;
9101 }
9102 else if (*op_string == REGISTER_PREFIX)
9103 {
9104 as_bad (_("bad register name `%s'"), op_string);
9105 return 0;
9106 }
9107 else if (*op_string == IMMEDIATE_PREFIX)
9108 {
9109 ++op_string;
9110 if (i.types[this_operand].bitfield.jumpabsolute)
9111 {
9112 as_bad (_("immediate operand illegal with absolute jump"));
9113 return 0;
9114 }
9115 if (!i386_immediate (op_string))
9116 return 0;
9117 }
9118 else if (RC_SAE_immediate (operand_string))
9119 {
9120 /* If it is a RC or SAE immediate, do nothing. */
9121 ;
9122 }
9123 else if (is_digit_char (*op_string)
9124 || is_identifier_char (*op_string)
9125 || *op_string == '"'
9126 || *op_string == '(')
9127 {
9128 /* This is a memory reference of some sort. */
9129 char *base_string;
9130
9131 /* Start and end of displacement string expression (if found). */
9132 char *displacement_string_start;
9133 char *displacement_string_end;
9134 char *vop_start;
9135
9136 do_memory_reference:
9137 if (i.mem_operands == 1 && !maybe_adjust_templates ())
9138 return 0;
9139 if ((i.mem_operands == 1
9140 && !current_templates->start->opcode_modifier.isstring)
9141 || i.mem_operands == 2)
9142 {
9143 as_bad (_("too many memory references for `%s'"),
9144 current_templates->start->name);
9145 return 0;
9146 }
9147
9148 /* Check for base index form. We detect the base index form by
9149 looking for an ')' at the end of the operand, searching
9150 for the '(' matching it, and finding a REGISTER_PREFIX or ','
9151 after the '('. */
9152 base_string = op_string + strlen (op_string);
9153
9154 /* Handle vector operations. */
9155 vop_start = strchr (op_string, '{');
9156 if (vop_start && vop_start < base_string)
9157 {
9158 if (check_VecOperations (vop_start, base_string) == NULL)
9159 return 0;
9160 base_string = vop_start;
9161 }
9162
9163 --base_string;
9164 if (is_space_char (*base_string))
9165 --base_string;
9166
9167 /* If we only have a displacement, set-up for it to be parsed later. */
9168 displacement_string_start = op_string;
9169 displacement_string_end = base_string + 1;
9170
9171 if (*base_string == ')')
9172 {
9173 char *temp_string;
9174 unsigned int parens_balanced = 1;
9175 /* We've already checked that the number of left & right ()'s are
9176 equal, so this loop will not be infinite. */
9177 do
9178 {
9179 base_string--;
9180 if (*base_string == ')')
9181 parens_balanced++;
9182 if (*base_string == '(')
9183 parens_balanced--;
9184 }
9185 while (parens_balanced);
9186
9187 temp_string = base_string;
9188
9189 /* Skip past '(' and whitespace. */
9190 ++base_string;
9191 if (is_space_char (*base_string))
9192 ++base_string;
9193
9194 if (*base_string == ','
9195 || ((i.base_reg = parse_register (base_string, &end_op))
9196 != NULL))
9197 {
9198 displacement_string_end = temp_string;
9199
9200 i.types[this_operand].bitfield.baseindex = 1;
9201
9202 if (i.base_reg)
9203 {
9204 base_string = end_op;
9205 if (is_space_char (*base_string))
9206 ++base_string;
9207 }
9208
9209 /* There may be an index reg or scale factor here. */
9210 if (*base_string == ',')
9211 {
9212 ++base_string;
9213 if (is_space_char (*base_string))
9214 ++base_string;
9215
9216 if ((i.index_reg = parse_register (base_string, &end_op))
9217 != NULL)
9218 {
9219 base_string = end_op;
9220 if (is_space_char (*base_string))
9221 ++base_string;
9222 if (*base_string == ',')
9223 {
9224 ++base_string;
9225 if (is_space_char (*base_string))
9226 ++base_string;
9227 }
9228 else if (*base_string != ')')
9229 {
9230 as_bad (_("expecting `,' or `)' "
9231 "after index register in `%s'"),
9232 operand_string);
9233 return 0;
9234 }
9235 }
9236 else if (*base_string == REGISTER_PREFIX)
9237 {
9238 end_op = strchr (base_string, ',');
9239 if (end_op)
9240 *end_op = '\0';
9241 as_bad (_("bad register name `%s'"), base_string);
9242 return 0;
9243 }
9244
9245 /* Check for scale factor. */
9246 if (*base_string != ')')
9247 {
9248 char *end_scale = i386_scale (base_string);
9249
9250 if (!end_scale)
9251 return 0;
9252
9253 base_string = end_scale;
9254 if (is_space_char (*base_string))
9255 ++base_string;
9256 if (*base_string != ')')
9257 {
9258 as_bad (_("expecting `)' "
9259 "after scale factor in `%s'"),
9260 operand_string);
9261 return 0;
9262 }
9263 }
9264 else if (!i.index_reg)
9265 {
9266 as_bad (_("expecting index register or scale factor "
9267 "after `,'; got '%c'"),
9268 *base_string);
9269 return 0;
9270 }
9271 }
9272 else if (*base_string != ')')
9273 {
9274 as_bad (_("expecting `,' or `)' "
9275 "after base register in `%s'"),
9276 operand_string);
9277 return 0;
9278 }
9279 }
9280 else if (*base_string == REGISTER_PREFIX)
9281 {
9282 end_op = strchr (base_string, ',');
9283 if (end_op)
9284 *end_op = '\0';
9285 as_bad (_("bad register name `%s'"), base_string);
9286 return 0;
9287 }
9288 }
9289
9290 /* If there's an expression beginning the operand, parse it,
9291 assuming displacement_string_start and
9292 displacement_string_end are meaningful. */
9293 if (displacement_string_start != displacement_string_end)
9294 {
9295 if (!i386_displacement (displacement_string_start,
9296 displacement_string_end))
9297 return 0;
9298 }
9299
9300 /* Special case for (%dx) while doing input/output op. */
9301 if (i.base_reg
9302 && operand_type_equal (&i.base_reg->reg_type,
9303 &reg16_inoutportreg)
9304 && i.index_reg == 0
9305 && i.log2_scale_factor == 0
9306 && i.seg[i.mem_operands] == 0
9307 && !operand_type_check (i.types[this_operand], disp))
9308 {
9309 i.types[this_operand] = inoutportreg;
9310 return 1;
9311 }
9312
9313 if (i386_index_check (operand_string) == 0)
9314 return 0;
9315 i.types[this_operand].bitfield.mem = 1;
9316 if (i.mem_operands == 0)
9317 i.memop1_string = xstrdup (operand_string);
9318 i.mem_operands++;
9319 }
9320 else
9321 {
9322 /* It's not a memory operand; argh! */
9323 as_bad (_("invalid char %s beginning operand %d `%s'"),
9324 output_invalid (*op_string),
9325 this_operand + 1,
9326 op_string);
9327 return 0;
9328 }
9329 return 1; /* Normal return. */
9330 }
9331 \f
9332 /* Calculate the maximum variable size (i.e., excluding fr_fix)
9333 that an rs_machine_dependent frag may reach. */
9334
9335 unsigned int
9336 i386_frag_max_var (fragS *frag)
9337 {
9338 /* The only relaxable frags are for jumps.
9339 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
9340 gas_assert (frag->fr_type == rs_machine_dependent);
9341 return TYPE_FROM_RELAX_STATE (frag->fr_subtype) == UNCOND_JUMP ? 4 : 5;
9342 }
9343
9344 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9345 static int
9346 elf_symbol_resolved_in_segment_p (symbolS *fr_symbol, offsetT fr_var)
9347 {
9348 /* STT_GNU_IFUNC symbol must go through PLT. */
9349 if ((symbol_get_bfdsym (fr_symbol)->flags
9350 & BSF_GNU_INDIRECT_FUNCTION) != 0)
9351 return 0;
9352
9353 if (!S_IS_EXTERNAL (fr_symbol))
9354 /* Symbol may be weak or local. */
9355 return !S_IS_WEAK (fr_symbol);
9356
9357 /* Global symbols with non-default visibility can't be preempted. */
9358 if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol)) != STV_DEFAULT)
9359 return 1;
9360
9361 if (fr_var != NO_RELOC)
9362 switch ((enum bfd_reloc_code_real) fr_var)
9363 {
9364 case BFD_RELOC_386_PLT32:
9365 case BFD_RELOC_X86_64_PLT32:
9366 /* Symbol with PLT relocation may be preempted. */
9367 return 0;
9368 default:
9369 abort ();
9370 }
9371
9372 /* Global symbols with default visibility in a shared library may be
9373 preempted by another definition. */
9374 return !shared;
9375 }
9376 #endif
9377
9378 /* md_estimate_size_before_relax()
9379
9380 Called just before relax() for rs_machine_dependent frags. The x86
9381 assembler uses these frags to handle variable size jump
9382 instructions.
9383
9384 Any symbol that is now undefined will not become defined.
9385 Return the correct fr_subtype in the frag.
9386 Return the initial "guess for variable size of frag" to caller.
9387 The guess is actually the growth beyond the fixed part. Whatever
9388 we do to grow the fixed or variable part contributes to our
9389 returned value. */
9390
9391 int
9392 md_estimate_size_before_relax (fragS *fragP, segT segment)
9393 {
9394 /* We've already got fragP->fr_subtype right; all we have to do is
9395 check for un-relaxable symbols. On an ELF system, we can't relax
9396 an externally visible symbol, because it may be overridden by a
9397 shared library. */
9398 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
9399 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9400 || (IS_ELF
9401 && !elf_symbol_resolved_in_segment_p (fragP->fr_symbol,
9402 fragP->fr_var))
9403 #endif
9404 #if defined (OBJ_COFF) && defined (TE_PE)
9405 || (OUTPUT_FLAVOR == bfd_target_coff_flavour
9406 && S_IS_WEAK (fragP->fr_symbol))
9407 #endif
9408 )
9409 {
9410 /* Symbol is undefined in this segment, or we need to keep a
9411 reloc so that weak symbols can be overridden. */
9412 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
9413 enum bfd_reloc_code_real reloc_type;
9414 unsigned char *opcode;
9415 int old_fr_fix;
9416
9417 if (fragP->fr_var != NO_RELOC)
9418 reloc_type = (enum bfd_reloc_code_real) fragP->fr_var;
9419 else if (size == 2)
9420 reloc_type = BFD_RELOC_16_PCREL;
9421 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9422 else if (need_plt32_p (fragP->fr_symbol))
9423 reloc_type = BFD_RELOC_X86_64_PLT32;
9424 #endif
9425 else
9426 reloc_type = BFD_RELOC_32_PCREL;
9427
9428 old_fr_fix = fragP->fr_fix;
9429 opcode = (unsigned char *) fragP->fr_opcode;
9430
9431 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
9432 {
9433 case UNCOND_JUMP:
9434 /* Make jmp (0xeb) a (d)word displacement jump. */
9435 opcode[0] = 0xe9;
9436 fragP->fr_fix += size;
9437 fix_new (fragP, old_fr_fix, size,
9438 fragP->fr_symbol,
9439 fragP->fr_offset, 1,
9440 reloc_type);
9441 break;
9442
9443 case COND_JUMP86:
9444 if (size == 2
9445 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
9446 {
9447 /* Negate the condition, and branch past an
9448 unconditional jump. */
9449 opcode[0] ^= 1;
9450 opcode[1] = 3;
9451 /* Insert an unconditional jump. */
9452 opcode[2] = 0xe9;
9453 /* We added two extra opcode bytes, and have a two byte
9454 offset. */
9455 fragP->fr_fix += 2 + 2;
9456 fix_new (fragP, old_fr_fix + 2, 2,
9457 fragP->fr_symbol,
9458 fragP->fr_offset, 1,
9459 reloc_type);
9460 break;
9461 }
9462 /* Fall through. */
9463
9464 case COND_JUMP:
9465 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
9466 {
9467 fixS *fixP;
9468
9469 fragP->fr_fix += 1;
9470 fixP = fix_new (fragP, old_fr_fix, 1,
9471 fragP->fr_symbol,
9472 fragP->fr_offset, 1,
9473 BFD_RELOC_8_PCREL);
9474 fixP->fx_signed = 1;
9475 break;
9476 }
9477
9478 /* This changes the byte-displacement jump 0x7N
9479 to the (d)word-displacement jump 0x0f,0x8N. */
9480 opcode[1] = opcode[0] + 0x10;
9481 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
9482 /* We've added an opcode byte. */
9483 fragP->fr_fix += 1 + size;
9484 fix_new (fragP, old_fr_fix + 1, size,
9485 fragP->fr_symbol,
9486 fragP->fr_offset, 1,
9487 reloc_type);
9488 break;
9489
9490 default:
9491 BAD_CASE (fragP->fr_subtype);
9492 break;
9493 }
9494 frag_wane (fragP);
9495 return fragP->fr_fix - old_fr_fix;
9496 }
9497
9498 /* Guess size depending on current relax state. Initially the relax
9499 state will correspond to a short jump and we return 1, because
9500 the variable part of the frag (the branch offset) is one byte
9501 long. However, we can relax a section more than once and in that
9502 case we must either set fr_subtype back to the unrelaxed state,
9503 or return the value for the appropriate branch. */
9504 return md_relax_table[fragP->fr_subtype].rlx_length;
9505 }
9506
9507 /* Called after relax() is finished.
9508
9509 In: Address of frag.
9510 fr_type == rs_machine_dependent.
9511 fr_subtype is what the address relaxed to.
9512
9513 Out: Any fixSs and constants are set up.
9514 Caller will turn frag into a ".space 0". */
9515
9516 void
9517 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT sec ATTRIBUTE_UNUSED,
9518 fragS *fragP)
9519 {
9520 unsigned char *opcode;
9521 unsigned char *where_to_put_displacement = NULL;
9522 offsetT target_address;
9523 offsetT opcode_address;
9524 unsigned int extension = 0;
9525 offsetT displacement_from_opcode_start;
9526
9527 opcode = (unsigned char *) fragP->fr_opcode;
9528
9529 /* Address we want to reach in file space. */
9530 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
9531
9532 /* Address opcode resides at in file space. */
9533 opcode_address = fragP->fr_address + fragP->fr_fix;
9534
9535 /* Displacement from opcode start to fill into instruction. */
9536 displacement_from_opcode_start = target_address - opcode_address;
9537
9538 if ((fragP->fr_subtype & BIG) == 0)
9539 {
9540 /* Don't have to change opcode. */
9541 extension = 1; /* 1 opcode + 1 displacement */
9542 where_to_put_displacement = &opcode[1];
9543 }
9544 else
9545 {
9546 if (no_cond_jump_promotion
9547 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
9548 as_warn_where (fragP->fr_file, fragP->fr_line,
9549 _("long jump required"));
9550
9551 switch (fragP->fr_subtype)
9552 {
9553 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
9554 extension = 4; /* 1 opcode + 4 displacement */
9555 opcode[0] = 0xe9;
9556 where_to_put_displacement = &opcode[1];
9557 break;
9558
9559 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
9560 extension = 2; /* 1 opcode + 2 displacement */
9561 opcode[0] = 0xe9;
9562 where_to_put_displacement = &opcode[1];
9563 break;
9564
9565 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
9566 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
9567 extension = 5; /* 2 opcode + 4 displacement */
9568 opcode[1] = opcode[0] + 0x10;
9569 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
9570 where_to_put_displacement = &opcode[2];
9571 break;
9572
9573 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
9574 extension = 3; /* 2 opcode + 2 displacement */
9575 opcode[1] = opcode[0] + 0x10;
9576 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
9577 where_to_put_displacement = &opcode[2];
9578 break;
9579
9580 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
9581 extension = 4;
9582 opcode[0] ^= 1;
9583 opcode[1] = 3;
9584 opcode[2] = 0xe9;
9585 where_to_put_displacement = &opcode[3];
9586 break;
9587
9588 default:
9589 BAD_CASE (fragP->fr_subtype);
9590 break;
9591 }
9592 }
9593
9594 /* If size if less then four we are sure that the operand fits,
9595 but if it's 4, then it could be that the displacement is larger
9596 then -/+ 2GB. */
9597 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
9598 && object_64bit
9599 && ((addressT) (displacement_from_opcode_start - extension
9600 + ((addressT) 1 << 31))
9601 > (((addressT) 2 << 31) - 1)))
9602 {
9603 as_bad_where (fragP->fr_file, fragP->fr_line,
9604 _("jump target out of range"));
9605 /* Make us emit 0. */
9606 displacement_from_opcode_start = extension;
9607 }
9608 /* Now put displacement after opcode. */
9609 md_number_to_chars ((char *) where_to_put_displacement,
9610 (valueT) (displacement_from_opcode_start - extension),
9611 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
9612 fragP->fr_fix += extension;
9613 }
9614 \f
9615 /* Apply a fixup (fixP) to segment data, once it has been determined
9616 by our caller that we have all the info we need to fix it up.
9617
9618 Parameter valP is the pointer to the value of the bits.
9619
9620 On the 386, immediates, displacements, and data pointers are all in
9621 the same (little-endian) format, so we don't need to care about which
9622 we are handling. */
9623
9624 void
9625 md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
9626 {
9627 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
9628 valueT value = *valP;
9629
9630 #if !defined (TE_Mach)
9631 if (fixP->fx_pcrel)
9632 {
9633 switch (fixP->fx_r_type)
9634 {
9635 default:
9636 break;
9637
9638 case BFD_RELOC_64:
9639 fixP->fx_r_type = BFD_RELOC_64_PCREL;
9640 break;
9641 case BFD_RELOC_32:
9642 case BFD_RELOC_X86_64_32S:
9643 fixP->fx_r_type = BFD_RELOC_32_PCREL;
9644 break;
9645 case BFD_RELOC_16:
9646 fixP->fx_r_type = BFD_RELOC_16_PCREL;
9647 break;
9648 case BFD_RELOC_8:
9649 fixP->fx_r_type = BFD_RELOC_8_PCREL;
9650 break;
9651 }
9652 }
9653
9654 if (fixP->fx_addsy != NULL
9655 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
9656 || fixP->fx_r_type == BFD_RELOC_64_PCREL
9657 || fixP->fx_r_type == BFD_RELOC_16_PCREL
9658 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
9659 && !use_rela_relocations)
9660 {
9661 /* This is a hack. There should be a better way to handle this.
9662 This covers for the fact that bfd_install_relocation will
9663 subtract the current location (for partial_inplace, PC relative
9664 relocations); see more below. */
9665 #ifndef OBJ_AOUT
9666 if (IS_ELF
9667 #ifdef TE_PE
9668 || OUTPUT_FLAVOR == bfd_target_coff_flavour
9669 #endif
9670 )
9671 value += fixP->fx_where + fixP->fx_frag->fr_address;
9672 #endif
9673 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9674 if (IS_ELF)
9675 {
9676 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
9677
9678 if ((sym_seg == seg
9679 || (symbol_section_p (fixP->fx_addsy)
9680 && sym_seg != absolute_section))
9681 && !generic_force_reloc (fixP))
9682 {
9683 /* Yes, we add the values in twice. This is because
9684 bfd_install_relocation subtracts them out again. I think
9685 bfd_install_relocation is broken, but I don't dare change
9686 it. FIXME. */
9687 value += fixP->fx_where + fixP->fx_frag->fr_address;
9688 }
9689 }
9690 #endif
9691 #if defined (OBJ_COFF) && defined (TE_PE)
9692 /* For some reason, the PE format does not store a
9693 section address offset for a PC relative symbol. */
9694 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
9695 || S_IS_WEAK (fixP->fx_addsy))
9696 value += md_pcrel_from (fixP);
9697 #endif
9698 }
9699 #if defined (OBJ_COFF) && defined (TE_PE)
9700 if (fixP->fx_addsy != NULL
9701 && S_IS_WEAK (fixP->fx_addsy)
9702 /* PR 16858: Do not modify weak function references. */
9703 && ! fixP->fx_pcrel)
9704 {
9705 #if !defined (TE_PEP)
9706 /* For x86 PE weak function symbols are neither PC-relative
9707 nor do they set S_IS_FUNCTION. So the only reliable way
9708 to detect them is to check the flags of their containing
9709 section. */
9710 if (S_GET_SEGMENT (fixP->fx_addsy) != NULL
9711 && S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_CODE)
9712 ;
9713 else
9714 #endif
9715 value -= S_GET_VALUE (fixP->fx_addsy);
9716 }
9717 #endif
9718
9719 /* Fix a few things - the dynamic linker expects certain values here,
9720 and we must not disappoint it. */
9721 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9722 if (IS_ELF && fixP->fx_addsy)
9723 switch (fixP->fx_r_type)
9724 {
9725 case BFD_RELOC_386_PLT32:
9726 case BFD_RELOC_X86_64_PLT32:
9727 /* Make the jump instruction point to the address of the operand. At
9728 runtime we merely add the offset to the actual PLT entry. */
9729 value = -4;
9730 break;
9731
9732 case BFD_RELOC_386_TLS_GD:
9733 case BFD_RELOC_386_TLS_LDM:
9734 case BFD_RELOC_386_TLS_IE_32:
9735 case BFD_RELOC_386_TLS_IE:
9736 case BFD_RELOC_386_TLS_GOTIE:
9737 case BFD_RELOC_386_TLS_GOTDESC:
9738 case BFD_RELOC_X86_64_TLSGD:
9739 case BFD_RELOC_X86_64_TLSLD:
9740 case BFD_RELOC_X86_64_GOTTPOFF:
9741 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
9742 value = 0; /* Fully resolved at runtime. No addend. */
9743 /* Fallthrough */
9744 case BFD_RELOC_386_TLS_LE:
9745 case BFD_RELOC_386_TLS_LDO_32:
9746 case BFD_RELOC_386_TLS_LE_32:
9747 case BFD_RELOC_X86_64_DTPOFF32:
9748 case BFD_RELOC_X86_64_DTPOFF64:
9749 case BFD_RELOC_X86_64_TPOFF32:
9750 case BFD_RELOC_X86_64_TPOFF64:
9751 S_SET_THREAD_LOCAL (fixP->fx_addsy);
9752 break;
9753
9754 case BFD_RELOC_386_TLS_DESC_CALL:
9755 case BFD_RELOC_X86_64_TLSDESC_CALL:
9756 value = 0; /* Fully resolved at runtime. No addend. */
9757 S_SET_THREAD_LOCAL (fixP->fx_addsy);
9758 fixP->fx_done = 0;
9759 return;
9760
9761 case BFD_RELOC_VTABLE_INHERIT:
9762 case BFD_RELOC_VTABLE_ENTRY:
9763 fixP->fx_done = 0;
9764 return;
9765
9766 default:
9767 break;
9768 }
9769 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
9770 *valP = value;
9771 #endif /* !defined (TE_Mach) */
9772
9773 /* Are we finished with this relocation now? */
9774 if (fixP->fx_addsy == NULL)
9775 fixP->fx_done = 1;
9776 #if defined (OBJ_COFF) && defined (TE_PE)
9777 else if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy))
9778 {
9779 fixP->fx_done = 0;
9780 /* Remember value for tc_gen_reloc. */
9781 fixP->fx_addnumber = value;
9782 /* Clear out the frag for now. */
9783 value = 0;
9784 }
9785 #endif
9786 else if (use_rela_relocations)
9787 {
9788 fixP->fx_no_overflow = 1;
9789 /* Remember value for tc_gen_reloc. */
9790 fixP->fx_addnumber = value;
9791 value = 0;
9792 }
9793
9794 md_number_to_chars (p, value, fixP->fx_size);
9795 }
9796 \f
9797 const char *
9798 md_atof (int type, char *litP, int *sizeP)
9799 {
9800 /* This outputs the LITTLENUMs in REVERSE order;
9801 in accord with the bigendian 386. */
9802 return ieee_md_atof (type, litP, sizeP, FALSE);
9803 }
9804 \f
9805 static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
9806
9807 static char *
9808 output_invalid (int c)
9809 {
9810 if (ISPRINT (c))
9811 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
9812 "'%c'", c);
9813 else
9814 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
9815 "(0x%x)", (unsigned char) c);
9816 return output_invalid_buf;
9817 }
9818
9819 /* REG_STRING starts *before* REGISTER_PREFIX. */
9820
9821 static const reg_entry *
9822 parse_real_register (char *reg_string, char **end_op)
9823 {
9824 char *s = reg_string;
9825 char *p;
9826 char reg_name_given[MAX_REG_NAME_SIZE + 1];
9827 const reg_entry *r;
9828
9829 /* Skip possible REGISTER_PREFIX and possible whitespace. */
9830 if (*s == REGISTER_PREFIX)
9831 ++s;
9832
9833 if (is_space_char (*s))
9834 ++s;
9835
9836 p = reg_name_given;
9837 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
9838 {
9839 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
9840 return (const reg_entry *) NULL;
9841 s++;
9842 }
9843
9844 /* For naked regs, make sure that we are not dealing with an identifier.
9845 This prevents confusing an identifier like `eax_var' with register
9846 `eax'. */
9847 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
9848 return (const reg_entry *) NULL;
9849
9850 *end_op = s;
9851
9852 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
9853
9854 /* Handle floating point regs, allowing spaces in the (i) part. */
9855 if (r == i386_regtab /* %st is first entry of table */)
9856 {
9857 if (is_space_char (*s))
9858 ++s;
9859 if (*s == '(')
9860 {
9861 ++s;
9862 if (is_space_char (*s))
9863 ++s;
9864 if (*s >= '0' && *s <= '7')
9865 {
9866 int fpr = *s - '0';
9867 ++s;
9868 if (is_space_char (*s))
9869 ++s;
9870 if (*s == ')')
9871 {
9872 *end_op = s + 1;
9873 r = (const reg_entry *) hash_find (reg_hash, "st(0)");
9874 know (r);
9875 return r + fpr;
9876 }
9877 }
9878 /* We have "%st(" then garbage. */
9879 return (const reg_entry *) NULL;
9880 }
9881 }
9882
9883 if (r == NULL || allow_pseudo_reg)
9884 return r;
9885
9886 if (operand_type_all_zero (&r->reg_type))
9887 return (const reg_entry *) NULL;
9888
9889 if ((r->reg_type.bitfield.dword
9890 || r->reg_type.bitfield.sreg3
9891 || r->reg_type.bitfield.control
9892 || r->reg_type.bitfield.debug
9893 || r->reg_type.bitfield.test)
9894 && !cpu_arch_flags.bitfield.cpui386)
9895 return (const reg_entry *) NULL;
9896
9897 if (r->reg_type.bitfield.tbyte
9898 && !cpu_arch_flags.bitfield.cpu8087
9899 && !cpu_arch_flags.bitfield.cpu287
9900 && !cpu_arch_flags.bitfield.cpu387)
9901 return (const reg_entry *) NULL;
9902
9903 if (r->reg_type.bitfield.regmmx && !cpu_arch_flags.bitfield.cpuregmmx)
9904 return (const reg_entry *) NULL;
9905
9906 if (r->reg_type.bitfield.xmmword && !cpu_arch_flags.bitfield.cpuregxmm)
9907 return (const reg_entry *) NULL;
9908
9909 if (r->reg_type.bitfield.ymmword && !cpu_arch_flags.bitfield.cpuregymm)
9910 return (const reg_entry *) NULL;
9911
9912 if (r->reg_type.bitfield.zmmword && !cpu_arch_flags.bitfield.cpuregzmm)
9913 return (const reg_entry *) NULL;
9914
9915 if (r->reg_type.bitfield.regmask
9916 && !cpu_arch_flags.bitfield.cpuregmask)
9917 return (const reg_entry *) NULL;
9918
9919 /* Don't allow fake index register unless allow_index_reg isn't 0. */
9920 if (!allow_index_reg
9921 && (r->reg_num == RegEiz || r->reg_num == RegRiz))
9922 return (const reg_entry *) NULL;
9923
9924 /* Upper 16 vector register is only available with VREX in 64bit
9925 mode. */
9926 if ((r->reg_flags & RegVRex))
9927 {
9928 if (i.vec_encoding == vex_encoding_default)
9929 i.vec_encoding = vex_encoding_evex;
9930
9931 if (!cpu_arch_flags.bitfield.cpuvrex
9932 || i.vec_encoding != vex_encoding_evex
9933 || flag_code != CODE_64BIT)
9934 return (const reg_entry *) NULL;
9935 }
9936
9937 if (((r->reg_flags & (RegRex64 | RegRex))
9938 || r->reg_type.bitfield.qword)
9939 && (!cpu_arch_flags.bitfield.cpulm
9940 || !operand_type_equal (&r->reg_type, &control))
9941 && flag_code != CODE_64BIT)
9942 return (const reg_entry *) NULL;
9943
9944 if (r->reg_type.bitfield.sreg3 && r->reg_num == RegFlat && !intel_syntax)
9945 return (const reg_entry *) NULL;
9946
9947 return r;
9948 }
9949
9950 /* REG_STRING starts *before* REGISTER_PREFIX. */
9951
9952 static const reg_entry *
9953 parse_register (char *reg_string, char **end_op)
9954 {
9955 const reg_entry *r;
9956
9957 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
9958 r = parse_real_register (reg_string, end_op);
9959 else
9960 r = NULL;
9961 if (!r)
9962 {
9963 char *save = input_line_pointer;
9964 char c;
9965 symbolS *symbolP;
9966
9967 input_line_pointer = reg_string;
9968 c = get_symbol_name (&reg_string);
9969 symbolP = symbol_find (reg_string);
9970 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
9971 {
9972 const expressionS *e = symbol_get_value_expression (symbolP);
9973
9974 know (e->X_op == O_register);
9975 know (e->X_add_number >= 0
9976 && (valueT) e->X_add_number < i386_regtab_size);
9977 r = i386_regtab + e->X_add_number;
9978 if ((r->reg_flags & RegVRex))
9979 i.vec_encoding = vex_encoding_evex;
9980 *end_op = input_line_pointer;
9981 }
9982 *input_line_pointer = c;
9983 input_line_pointer = save;
9984 }
9985 return r;
9986 }
9987
9988 int
9989 i386_parse_name (char *name, expressionS *e, char *nextcharP)
9990 {
9991 const reg_entry *r;
9992 char *end = input_line_pointer;
9993
9994 *end = *nextcharP;
9995 r = parse_register (name, &input_line_pointer);
9996 if (r && end <= input_line_pointer)
9997 {
9998 *nextcharP = *input_line_pointer;
9999 *input_line_pointer = 0;
10000 e->X_op = O_register;
10001 e->X_add_number = r - i386_regtab;
10002 return 1;
10003 }
10004 input_line_pointer = end;
10005 *end = 0;
10006 return intel_syntax ? i386_intel_parse_name (name, e) : 0;
10007 }
10008
10009 void
10010 md_operand (expressionS *e)
10011 {
10012 char *end;
10013 const reg_entry *r;
10014
10015 switch (*input_line_pointer)
10016 {
10017 case REGISTER_PREFIX:
10018 r = parse_real_register (input_line_pointer, &end);
10019 if (r)
10020 {
10021 e->X_op = O_register;
10022 e->X_add_number = r - i386_regtab;
10023 input_line_pointer = end;
10024 }
10025 break;
10026
10027 case '[':
10028 gas_assert (intel_syntax);
10029 end = input_line_pointer++;
10030 expression (e);
10031 if (*input_line_pointer == ']')
10032 {
10033 ++input_line_pointer;
10034 e->X_op_symbol = make_expr_symbol (e);
10035 e->X_add_symbol = NULL;
10036 e->X_add_number = 0;
10037 e->X_op = O_index;
10038 }
10039 else
10040 {
10041 e->X_op = O_absent;
10042 input_line_pointer = end;
10043 }
10044 break;
10045 }
10046 }
10047
10048 \f
10049 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10050 const char *md_shortopts = "kVQ:sqn";
10051 #else
10052 const char *md_shortopts = "qn";
10053 #endif
10054
10055 #define OPTION_32 (OPTION_MD_BASE + 0)
10056 #define OPTION_64 (OPTION_MD_BASE + 1)
10057 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
10058 #define OPTION_MARCH (OPTION_MD_BASE + 3)
10059 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
10060 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
10061 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
10062 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
10063 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
10064 #define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
10065 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
10066 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
10067 #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
10068 #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
10069 #define OPTION_X32 (OPTION_MD_BASE + 14)
10070 #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
10071 #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
10072 #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
10073 #define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
10074 #define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
10075 #define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
10076 #define OPTION_MSHARED (OPTION_MD_BASE + 21)
10077 #define OPTION_MAMD64 (OPTION_MD_BASE + 22)
10078 #define OPTION_MINTEL64 (OPTION_MD_BASE + 23)
10079 #define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24)
10080 #define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 25)
10081
10082 struct option md_longopts[] =
10083 {
10084 {"32", no_argument, NULL, OPTION_32},
10085 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10086 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
10087 {"64", no_argument, NULL, OPTION_64},
10088 #endif
10089 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10090 {"x32", no_argument, NULL, OPTION_X32},
10091 {"mshared", no_argument, NULL, OPTION_MSHARED},
10092 #endif
10093 {"divide", no_argument, NULL, OPTION_DIVIDE},
10094 {"march", required_argument, NULL, OPTION_MARCH},
10095 {"mtune", required_argument, NULL, OPTION_MTUNE},
10096 {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC},
10097 {"msyntax", required_argument, NULL, OPTION_MSYNTAX},
10098 {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG},
10099 {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG},
10100 {"mold-gcc", no_argument, NULL, OPTION_MOLD_GCC},
10101 {"msse2avx", no_argument, NULL, OPTION_MSSE2AVX},
10102 {"msse-check", required_argument, NULL, OPTION_MSSE_CHECK},
10103 {"moperand-check", required_argument, NULL, OPTION_MOPERAND_CHECK},
10104 {"mavxscalar", required_argument, NULL, OPTION_MAVXSCALAR},
10105 {"madd-bnd-prefix", no_argument, NULL, OPTION_MADD_BND_PREFIX},
10106 {"mevexlig", required_argument, NULL, OPTION_MEVEXLIG},
10107 {"mevexwig", required_argument, NULL, OPTION_MEVEXWIG},
10108 # if defined (TE_PE) || defined (TE_PEP)
10109 {"mbig-obj", no_argument, NULL, OPTION_MBIG_OBJ},
10110 #endif
10111 {"momit-lock-prefix", required_argument, NULL, OPTION_MOMIT_LOCK_PREFIX},
10112 {"mfence-as-lock-add", required_argument, NULL, OPTION_MFENCE_AS_LOCK_ADD},
10113 {"mrelax-relocations", required_argument, NULL, OPTION_MRELAX_RELOCATIONS},
10114 {"mevexrcig", required_argument, NULL, OPTION_MEVEXRCIG},
10115 {"mamd64", no_argument, NULL, OPTION_MAMD64},
10116 {"mintel64", no_argument, NULL, OPTION_MINTEL64},
10117 {NULL, no_argument, NULL, 0}
10118 };
10119 size_t md_longopts_size = sizeof (md_longopts);
10120
10121 int
10122 md_parse_option (int c, const char *arg)
10123 {
10124 unsigned int j;
10125 char *arch, *next, *saved;
10126
10127 switch (c)
10128 {
10129 case 'n':
10130 optimize_align_code = 0;
10131 break;
10132
10133 case 'q':
10134 quiet_warnings = 1;
10135 break;
10136
10137 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10138 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
10139 should be emitted or not. FIXME: Not implemented. */
10140 case 'Q':
10141 break;
10142
10143 /* -V: SVR4 argument to print version ID. */
10144 case 'V':
10145 print_version_id ();
10146 break;
10147
10148 /* -k: Ignore for FreeBSD compatibility. */
10149 case 'k':
10150 break;
10151
10152 case 's':
10153 /* -s: On i386 Solaris, this tells the native assembler to use
10154 .stab instead of .stab.excl. We always use .stab anyhow. */
10155 break;
10156
10157 case OPTION_MSHARED:
10158 shared = 1;
10159 break;
10160 #endif
10161 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10162 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
10163 case OPTION_64:
10164 {
10165 const char **list, **l;
10166
10167 list = bfd_target_list ();
10168 for (l = list; *l != NULL; l++)
10169 if (CONST_STRNEQ (*l, "elf64-x86-64")
10170 || strcmp (*l, "coff-x86-64") == 0
10171 || strcmp (*l, "pe-x86-64") == 0
10172 || strcmp (*l, "pei-x86-64") == 0
10173 || strcmp (*l, "mach-o-x86-64") == 0)
10174 {
10175 default_arch = "x86_64";
10176 break;
10177 }
10178 if (*l == NULL)
10179 as_fatal (_("no compiled in support for x86_64"));
10180 free (list);
10181 }
10182 break;
10183 #endif
10184
10185 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10186 case OPTION_X32:
10187 if (IS_ELF)
10188 {
10189 const char **list, **l;
10190
10191 list = bfd_target_list ();
10192 for (l = list; *l != NULL; l++)
10193 if (CONST_STRNEQ (*l, "elf32-x86-64"))
10194 {
10195 default_arch = "x86_64:32";
10196 break;
10197 }
10198 if (*l == NULL)
10199 as_fatal (_("no compiled in support for 32bit x86_64"));
10200 free (list);
10201 }
10202 else
10203 as_fatal (_("32bit x86_64 is only supported for ELF"));
10204 break;
10205 #endif
10206
10207 case OPTION_32:
10208 default_arch = "i386";
10209 break;
10210
10211 case OPTION_DIVIDE:
10212 #ifdef SVR4_COMMENT_CHARS
10213 {
10214 char *n, *t;
10215 const char *s;
10216
10217 n = XNEWVEC (char, strlen (i386_comment_chars) + 1);
10218 t = n;
10219 for (s = i386_comment_chars; *s != '\0'; s++)
10220 if (*s != '/')
10221 *t++ = *s;
10222 *t = '\0';
10223 i386_comment_chars = n;
10224 }
10225 #endif
10226 break;
10227
10228 case OPTION_MARCH:
10229 saved = xstrdup (arg);
10230 arch = saved;
10231 /* Allow -march=+nosse. */
10232 if (*arch == '+')
10233 arch++;
10234 do
10235 {
10236 if (*arch == '.')
10237 as_fatal (_("invalid -march= option: `%s'"), arg);
10238 next = strchr (arch, '+');
10239 if (next)
10240 *next++ = '\0';
10241 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
10242 {
10243 if (strcmp (arch, cpu_arch [j].name) == 0)
10244 {
10245 /* Processor. */
10246 if (! cpu_arch[j].flags.bitfield.cpui386)
10247 continue;
10248
10249 cpu_arch_name = cpu_arch[j].name;
10250 cpu_sub_arch_name = NULL;
10251 cpu_arch_flags = cpu_arch[j].flags;
10252 cpu_arch_isa = cpu_arch[j].type;
10253 cpu_arch_isa_flags = cpu_arch[j].flags;
10254 if (!cpu_arch_tune_set)
10255 {
10256 cpu_arch_tune = cpu_arch_isa;
10257 cpu_arch_tune_flags = cpu_arch_isa_flags;
10258 }
10259 break;
10260 }
10261 else if (*cpu_arch [j].name == '.'
10262 && strcmp (arch, cpu_arch [j].name + 1) == 0)
10263 {
10264 /* ISA extension. */
10265 i386_cpu_flags flags;
10266
10267 flags = cpu_flags_or (cpu_arch_flags,
10268 cpu_arch[j].flags);
10269
10270 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
10271 {
10272 if (cpu_sub_arch_name)
10273 {
10274 char *name = cpu_sub_arch_name;
10275 cpu_sub_arch_name = concat (name,
10276 cpu_arch[j].name,
10277 (const char *) NULL);
10278 free (name);
10279 }
10280 else
10281 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
10282 cpu_arch_flags = flags;
10283 cpu_arch_isa_flags = flags;
10284 }
10285 break;
10286 }
10287 }
10288
10289 if (j >= ARRAY_SIZE (cpu_arch))
10290 {
10291 /* Disable an ISA extension. */
10292 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
10293 if (strcmp (arch, cpu_noarch [j].name) == 0)
10294 {
10295 i386_cpu_flags flags;
10296
10297 flags = cpu_flags_and_not (cpu_arch_flags,
10298 cpu_noarch[j].flags);
10299 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
10300 {
10301 if (cpu_sub_arch_name)
10302 {
10303 char *name = cpu_sub_arch_name;
10304 cpu_sub_arch_name = concat (arch,
10305 (const char *) NULL);
10306 free (name);
10307 }
10308 else
10309 cpu_sub_arch_name = xstrdup (arch);
10310 cpu_arch_flags = flags;
10311 cpu_arch_isa_flags = flags;
10312 }
10313 break;
10314 }
10315
10316 if (j >= ARRAY_SIZE (cpu_noarch))
10317 j = ARRAY_SIZE (cpu_arch);
10318 }
10319
10320 if (j >= ARRAY_SIZE (cpu_arch))
10321 as_fatal (_("invalid -march= option: `%s'"), arg);
10322
10323 arch = next;
10324 }
10325 while (next != NULL);
10326 free (saved);
10327 break;
10328
10329 case OPTION_MTUNE:
10330 if (*arg == '.')
10331 as_fatal (_("invalid -mtune= option: `%s'"), arg);
10332 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
10333 {
10334 if (strcmp (arg, cpu_arch [j].name) == 0)
10335 {
10336 cpu_arch_tune_set = 1;
10337 cpu_arch_tune = cpu_arch [j].type;
10338 cpu_arch_tune_flags = cpu_arch[j].flags;
10339 break;
10340 }
10341 }
10342 if (j >= ARRAY_SIZE (cpu_arch))
10343 as_fatal (_("invalid -mtune= option: `%s'"), arg);
10344 break;
10345
10346 case OPTION_MMNEMONIC:
10347 if (strcasecmp (arg, "att") == 0)
10348 intel_mnemonic = 0;
10349 else if (strcasecmp (arg, "intel") == 0)
10350 intel_mnemonic = 1;
10351 else
10352 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg);
10353 break;
10354
10355 case OPTION_MSYNTAX:
10356 if (strcasecmp (arg, "att") == 0)
10357 intel_syntax = 0;
10358 else if (strcasecmp (arg, "intel") == 0)
10359 intel_syntax = 1;
10360 else
10361 as_fatal (_("invalid -msyntax= option: `%s'"), arg);
10362 break;
10363
10364 case OPTION_MINDEX_REG:
10365 allow_index_reg = 1;
10366 break;
10367
10368 case OPTION_MNAKED_REG:
10369 allow_naked_reg = 1;
10370 break;
10371
10372 case OPTION_MOLD_GCC:
10373 old_gcc = 1;
10374 break;
10375
10376 case OPTION_MSSE2AVX:
10377 sse2avx = 1;
10378 break;
10379
10380 case OPTION_MSSE_CHECK:
10381 if (strcasecmp (arg, "error") == 0)
10382 sse_check = check_error;
10383 else if (strcasecmp (arg, "warning") == 0)
10384 sse_check = check_warning;
10385 else if (strcasecmp (arg, "none") == 0)
10386 sse_check = check_none;
10387 else
10388 as_fatal (_("invalid -msse-check= option: `%s'"), arg);
10389 break;
10390
10391 case OPTION_MOPERAND_CHECK:
10392 if (strcasecmp (arg, "error") == 0)
10393 operand_check = check_error;
10394 else if (strcasecmp (arg, "warning") == 0)
10395 operand_check = check_warning;
10396 else if (strcasecmp (arg, "none") == 0)
10397 operand_check = check_none;
10398 else
10399 as_fatal (_("invalid -moperand-check= option: `%s'"), arg);
10400 break;
10401
10402 case OPTION_MAVXSCALAR:
10403 if (strcasecmp (arg, "128") == 0)
10404 avxscalar = vex128;
10405 else if (strcasecmp (arg, "256") == 0)
10406 avxscalar = vex256;
10407 else
10408 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg);
10409 break;
10410
10411 case OPTION_MADD_BND_PREFIX:
10412 add_bnd_prefix = 1;
10413 break;
10414
10415 case OPTION_MEVEXLIG:
10416 if (strcmp (arg, "128") == 0)
10417 evexlig = evexl128;
10418 else if (strcmp (arg, "256") == 0)
10419 evexlig = evexl256;
10420 else if (strcmp (arg, "512") == 0)
10421 evexlig = evexl512;
10422 else
10423 as_fatal (_("invalid -mevexlig= option: `%s'"), arg);
10424 break;
10425
10426 case OPTION_MEVEXRCIG:
10427 if (strcmp (arg, "rne") == 0)
10428 evexrcig = rne;
10429 else if (strcmp (arg, "rd") == 0)
10430 evexrcig = rd;
10431 else if (strcmp (arg, "ru") == 0)
10432 evexrcig = ru;
10433 else if (strcmp (arg, "rz") == 0)
10434 evexrcig = rz;
10435 else
10436 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg);
10437 break;
10438
10439 case OPTION_MEVEXWIG:
10440 if (strcmp (arg, "0") == 0)
10441 evexwig = evexw0;
10442 else if (strcmp (arg, "1") == 0)
10443 evexwig = evexw1;
10444 else
10445 as_fatal (_("invalid -mevexwig= option: `%s'"), arg);
10446 break;
10447
10448 # if defined (TE_PE) || defined (TE_PEP)
10449 case OPTION_MBIG_OBJ:
10450 use_big_obj = 1;
10451 break;
10452 #endif
10453
10454 case OPTION_MOMIT_LOCK_PREFIX:
10455 if (strcasecmp (arg, "yes") == 0)
10456 omit_lock_prefix = 1;
10457 else if (strcasecmp (arg, "no") == 0)
10458 omit_lock_prefix = 0;
10459 else
10460 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg);
10461 break;
10462
10463 case OPTION_MFENCE_AS_LOCK_ADD:
10464 if (strcasecmp (arg, "yes") == 0)
10465 avoid_fence = 1;
10466 else if (strcasecmp (arg, "no") == 0)
10467 avoid_fence = 0;
10468 else
10469 as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg);
10470 break;
10471
10472 case OPTION_MRELAX_RELOCATIONS:
10473 if (strcasecmp (arg, "yes") == 0)
10474 generate_relax_relocations = 1;
10475 else if (strcasecmp (arg, "no") == 0)
10476 generate_relax_relocations = 0;
10477 else
10478 as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg);
10479 break;
10480
10481 case OPTION_MAMD64:
10482 intel64 = 0;
10483 break;
10484
10485 case OPTION_MINTEL64:
10486 intel64 = 1;
10487 break;
10488
10489 default:
10490 return 0;
10491 }
10492 return 1;
10493 }
10494
10495 #define MESSAGE_TEMPLATE \
10496 " "
10497
10498 static char *
10499 output_message (FILE *stream, char *p, char *message, char *start,
10500 int *left_p, const char *name, int len)
10501 {
10502 int size = sizeof (MESSAGE_TEMPLATE);
10503 int left = *left_p;
10504
10505 /* Reserve 2 spaces for ", " or ",\0" */
10506 left -= len + 2;
10507
10508 /* Check if there is any room. */
10509 if (left >= 0)
10510 {
10511 if (p != start)
10512 {
10513 *p++ = ',';
10514 *p++ = ' ';
10515 }
10516 p = mempcpy (p, name, len);
10517 }
10518 else
10519 {
10520 /* Output the current message now and start a new one. */
10521 *p++ = ',';
10522 *p = '\0';
10523 fprintf (stream, "%s\n", message);
10524 p = start;
10525 left = size - (start - message) - len - 2;
10526
10527 gas_assert (left >= 0);
10528
10529 p = mempcpy (p, name, len);
10530 }
10531
10532 *left_p = left;
10533 return p;
10534 }
10535
10536 static void
10537 show_arch (FILE *stream, int ext, int check)
10538 {
10539 static char message[] = MESSAGE_TEMPLATE;
10540 char *start = message + 27;
10541 char *p;
10542 int size = sizeof (MESSAGE_TEMPLATE);
10543 int left;
10544 const char *name;
10545 int len;
10546 unsigned int j;
10547
10548 p = start;
10549 left = size - (start - message);
10550 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
10551 {
10552 /* Should it be skipped? */
10553 if (cpu_arch [j].skip)
10554 continue;
10555
10556 name = cpu_arch [j].name;
10557 len = cpu_arch [j].len;
10558 if (*name == '.')
10559 {
10560 /* It is an extension. Skip if we aren't asked to show it. */
10561 if (ext)
10562 {
10563 name++;
10564 len--;
10565 }
10566 else
10567 continue;
10568 }
10569 else if (ext)
10570 {
10571 /* It is an processor. Skip if we show only extension. */
10572 continue;
10573 }
10574 else if (check && ! cpu_arch[j].flags.bitfield.cpui386)
10575 {
10576 /* It is an impossible processor - skip. */
10577 continue;
10578 }
10579
10580 p = output_message (stream, p, message, start, &left, name, len);
10581 }
10582
10583 /* Display disabled extensions. */
10584 if (ext)
10585 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
10586 {
10587 name = cpu_noarch [j].name;
10588 len = cpu_noarch [j].len;
10589 p = output_message (stream, p, message, start, &left, name,
10590 len);
10591 }
10592
10593 *p = '\0';
10594 fprintf (stream, "%s\n", message);
10595 }
10596
10597 void
10598 md_show_usage (FILE *stream)
10599 {
10600 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10601 fprintf (stream, _("\
10602 -Q ignored\n\
10603 -V print assembler version number\n\
10604 -k ignored\n"));
10605 #endif
10606 fprintf (stream, _("\
10607 -n Do not optimize code alignment\n\
10608 -q quieten some warnings\n"));
10609 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10610 fprintf (stream, _("\
10611 -s ignored\n"));
10612 #endif
10613 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10614 || defined (TE_PE) || defined (TE_PEP))
10615 fprintf (stream, _("\
10616 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
10617 #endif
10618 #ifdef SVR4_COMMENT_CHARS
10619 fprintf (stream, _("\
10620 --divide do not treat `/' as a comment character\n"));
10621 #else
10622 fprintf (stream, _("\
10623 --divide ignored\n"));
10624 #endif
10625 fprintf (stream, _("\
10626 -march=CPU[,+EXTENSION...]\n\
10627 generate code for CPU and EXTENSION, CPU is one of:\n"));
10628 show_arch (stream, 0, 1);
10629 fprintf (stream, _("\
10630 EXTENSION is combination of:\n"));
10631 show_arch (stream, 1, 0);
10632 fprintf (stream, _("\
10633 -mtune=CPU optimize for CPU, CPU is one of:\n"));
10634 show_arch (stream, 0, 0);
10635 fprintf (stream, _("\
10636 -msse2avx encode SSE instructions with VEX prefix\n"));
10637 fprintf (stream, _("\
10638 -msse-check=[none|error|warning]\n\
10639 check SSE instructions\n"));
10640 fprintf (stream, _("\
10641 -moperand-check=[none|error|warning]\n\
10642 check operand combinations for validity\n"));
10643 fprintf (stream, _("\
10644 -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n\
10645 length\n"));
10646 fprintf (stream, _("\
10647 -mevexlig=[128|256|512] encode scalar EVEX instructions with specific vector\n\
10648 length\n"));
10649 fprintf (stream, _("\
10650 -mevexwig=[0|1] encode EVEX instructions with specific EVEX.W value\n\
10651 for EVEX.W bit ignored instructions\n"));
10652 fprintf (stream, _("\
10653 -mevexrcig=[rne|rd|ru|rz]\n\
10654 encode EVEX instructions with specific EVEX.RC value\n\
10655 for SAE-only ignored instructions\n"));
10656 fprintf (stream, _("\
10657 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
10658 fprintf (stream, _("\
10659 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
10660 fprintf (stream, _("\
10661 -mindex-reg support pseudo index registers\n"));
10662 fprintf (stream, _("\
10663 -mnaked-reg don't require `%%' prefix for registers\n"));
10664 fprintf (stream, _("\
10665 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
10666 fprintf (stream, _("\
10667 -madd-bnd-prefix add BND prefix for all valid branches\n"));
10668 fprintf (stream, _("\
10669 -mshared disable branch optimization for shared code\n"));
10670 # if defined (TE_PE) || defined (TE_PEP)
10671 fprintf (stream, _("\
10672 -mbig-obj generate big object files\n"));
10673 #endif
10674 fprintf (stream, _("\
10675 -momit-lock-prefix=[no|yes]\n\
10676 strip all lock prefixes\n"));
10677 fprintf (stream, _("\
10678 -mfence-as-lock-add=[no|yes]\n\
10679 encode lfence, mfence and sfence as\n\
10680 lock addl $0x0, (%%{re}sp)\n"));
10681 fprintf (stream, _("\
10682 -mrelax-relocations=[no|yes]\n\
10683 generate relax relocations\n"));
10684 fprintf (stream, _("\
10685 -mamd64 accept only AMD64 ISA\n"));
10686 fprintf (stream, _("\
10687 -mintel64 accept only Intel64 ISA\n"));
10688 }
10689
10690 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
10691 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10692 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
10693
10694 /* Pick the target format to use. */
10695
10696 const char *
10697 i386_target_format (void)
10698 {
10699 if (!strncmp (default_arch, "x86_64", 6))
10700 {
10701 update_code_flag (CODE_64BIT, 1);
10702 if (default_arch[6] == '\0')
10703 x86_elf_abi = X86_64_ABI;
10704 else
10705 x86_elf_abi = X86_64_X32_ABI;
10706 }
10707 else if (!strcmp (default_arch, "i386"))
10708 update_code_flag (CODE_32BIT, 1);
10709 else if (!strcmp (default_arch, "iamcu"))
10710 {
10711 update_code_flag (CODE_32BIT, 1);
10712 if (cpu_arch_isa == PROCESSOR_UNKNOWN)
10713 {
10714 static const i386_cpu_flags iamcu_flags = CPU_IAMCU_FLAGS;
10715 cpu_arch_name = "iamcu";
10716 cpu_sub_arch_name = NULL;
10717 cpu_arch_flags = iamcu_flags;
10718 cpu_arch_isa = PROCESSOR_IAMCU;
10719 cpu_arch_isa_flags = iamcu_flags;
10720 if (!cpu_arch_tune_set)
10721 {
10722 cpu_arch_tune = cpu_arch_isa;
10723 cpu_arch_tune_flags = cpu_arch_isa_flags;
10724 }
10725 }
10726 else if (cpu_arch_isa != PROCESSOR_IAMCU)
10727 as_fatal (_("Intel MCU doesn't support `%s' architecture"),
10728 cpu_arch_name);
10729 }
10730 else
10731 as_fatal (_("unknown architecture"));
10732
10733 if (cpu_flags_all_zero (&cpu_arch_isa_flags))
10734 cpu_arch_isa_flags = cpu_arch[flag_code == CODE_64BIT].flags;
10735 if (cpu_flags_all_zero (&cpu_arch_tune_flags))
10736 cpu_arch_tune_flags = cpu_arch[flag_code == CODE_64BIT].flags;
10737
10738 switch (OUTPUT_FLAVOR)
10739 {
10740 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
10741 case bfd_target_aout_flavour:
10742 return AOUT_TARGET_FORMAT;
10743 #endif
10744 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
10745 # if defined (TE_PE) || defined (TE_PEP)
10746 case bfd_target_coff_flavour:
10747 if (flag_code == CODE_64BIT)
10748 return use_big_obj ? "pe-bigobj-x86-64" : "pe-x86-64";
10749 else
10750 return "pe-i386";
10751 # elif defined (TE_GO32)
10752 case bfd_target_coff_flavour:
10753 return "coff-go32";
10754 # else
10755 case bfd_target_coff_flavour:
10756 return "coff-i386";
10757 # endif
10758 #endif
10759 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
10760 case bfd_target_elf_flavour:
10761 {
10762 const char *format;
10763
10764 switch (x86_elf_abi)
10765 {
10766 default:
10767 format = ELF_TARGET_FORMAT;
10768 break;
10769 case X86_64_ABI:
10770 use_rela_relocations = 1;
10771 object_64bit = 1;
10772 format = ELF_TARGET_FORMAT64;
10773 break;
10774 case X86_64_X32_ABI:
10775 use_rela_relocations = 1;
10776 object_64bit = 1;
10777 disallow_64bit_reloc = 1;
10778 format = ELF_TARGET_FORMAT32;
10779 break;
10780 }
10781 if (cpu_arch_isa == PROCESSOR_L1OM)
10782 {
10783 if (x86_elf_abi != X86_64_ABI)
10784 as_fatal (_("Intel L1OM is 64bit only"));
10785 return ELF_TARGET_L1OM_FORMAT;
10786 }
10787 else if (cpu_arch_isa == PROCESSOR_K1OM)
10788 {
10789 if (x86_elf_abi != X86_64_ABI)
10790 as_fatal (_("Intel K1OM is 64bit only"));
10791 return ELF_TARGET_K1OM_FORMAT;
10792 }
10793 else if (cpu_arch_isa == PROCESSOR_IAMCU)
10794 {
10795 if (x86_elf_abi != I386_ABI)
10796 as_fatal (_("Intel MCU is 32bit only"));
10797 return ELF_TARGET_IAMCU_FORMAT;
10798 }
10799 else
10800 return format;
10801 }
10802 #endif
10803 #if defined (OBJ_MACH_O)
10804 case bfd_target_mach_o_flavour:
10805 if (flag_code == CODE_64BIT)
10806 {
10807 use_rela_relocations = 1;
10808 object_64bit = 1;
10809 return "mach-o-x86-64";
10810 }
10811 else
10812 return "mach-o-i386";
10813 #endif
10814 default:
10815 abort ();
10816 return NULL;
10817 }
10818 }
10819
10820 #endif /* OBJ_MAYBE_ more than one */
10821 \f
10822 symbolS *
10823 md_undefined_symbol (char *name)
10824 {
10825 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
10826 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
10827 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
10828 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
10829 {
10830 if (!GOT_symbol)
10831 {
10832 if (symbol_find (name))
10833 as_bad (_("GOT already in symbol table"));
10834 GOT_symbol = symbol_new (name, undefined_section,
10835 (valueT) 0, &zero_address_frag);
10836 };
10837 return GOT_symbol;
10838 }
10839 return 0;
10840 }
10841
10842 /* Round up a section size to the appropriate boundary. */
10843
10844 valueT
10845 md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size)
10846 {
10847 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
10848 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
10849 {
10850 /* For a.out, force the section size to be aligned. If we don't do
10851 this, BFD will align it for us, but it will not write out the
10852 final bytes of the section. This may be a bug in BFD, but it is
10853 easier to fix it here since that is how the other a.out targets
10854 work. */
10855 int align;
10856
10857 align = bfd_get_section_alignment (stdoutput, segment);
10858 size = ((size + (1 << align) - 1) & (-((valueT) 1 << align)));
10859 }
10860 #endif
10861
10862 return size;
10863 }
10864
10865 /* On the i386, PC-relative offsets are relative to the start of the
10866 next instruction. That is, the address of the offset, plus its
10867 size, since the offset is always the last part of the insn. */
10868
10869 long
10870 md_pcrel_from (fixS *fixP)
10871 {
10872 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
10873 }
10874
10875 #ifndef I386COFF
10876
10877 static void
10878 s_bss (int ignore ATTRIBUTE_UNUSED)
10879 {
10880 int temp;
10881
10882 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10883 if (IS_ELF)
10884 obj_elf_section_change_hook ();
10885 #endif
10886 temp = get_absolute_expression ();
10887 subseg_set (bss_section, (subsegT) temp);
10888 demand_empty_rest_of_line ();
10889 }
10890
10891 #endif
10892
10893 void
10894 i386_validate_fix (fixS *fixp)
10895 {
10896 if (fixp->fx_subsy)
10897 {
10898 if (fixp->fx_subsy == GOT_symbol)
10899 {
10900 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
10901 {
10902 if (!object_64bit)
10903 abort ();
10904 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10905 if (fixp->fx_tcbit2)
10906 fixp->fx_r_type = (fixp->fx_tcbit
10907 ? BFD_RELOC_X86_64_REX_GOTPCRELX
10908 : BFD_RELOC_X86_64_GOTPCRELX);
10909 else
10910 #endif
10911 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
10912 }
10913 else
10914 {
10915 if (!object_64bit)
10916 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
10917 else
10918 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
10919 }
10920 fixp->fx_subsy = 0;
10921 }
10922 }
10923 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10924 else if (!object_64bit)
10925 {
10926 if (fixp->fx_r_type == BFD_RELOC_386_GOT32
10927 && fixp->fx_tcbit2)
10928 fixp->fx_r_type = BFD_RELOC_386_GOT32X;
10929 }
10930 #endif
10931 }
10932
10933 arelent *
10934 tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
10935 {
10936 arelent *rel;
10937 bfd_reloc_code_real_type code;
10938
10939 switch (fixp->fx_r_type)
10940 {
10941 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10942 case BFD_RELOC_SIZE32:
10943 case BFD_RELOC_SIZE64:
10944 if (S_IS_DEFINED (fixp->fx_addsy)
10945 && !S_IS_EXTERNAL (fixp->fx_addsy))
10946 {
10947 /* Resolve size relocation against local symbol to size of
10948 the symbol plus addend. */
10949 valueT value = S_GET_SIZE (fixp->fx_addsy) + fixp->fx_offset;
10950 if (fixp->fx_r_type == BFD_RELOC_SIZE32
10951 && !fits_in_unsigned_long (value))
10952 as_bad_where (fixp->fx_file, fixp->fx_line,
10953 _("symbol size computation overflow"));
10954 fixp->fx_addsy = NULL;
10955 fixp->fx_subsy = NULL;
10956 md_apply_fix (fixp, (valueT *) &value, NULL);
10957 return NULL;
10958 }
10959 #endif
10960 /* Fall through. */
10961
10962 case BFD_RELOC_X86_64_PLT32:
10963 case BFD_RELOC_X86_64_GOT32:
10964 case BFD_RELOC_X86_64_GOTPCREL:
10965 case BFD_RELOC_X86_64_GOTPCRELX:
10966 case BFD_RELOC_X86_64_REX_GOTPCRELX:
10967 case BFD_RELOC_386_PLT32:
10968 case BFD_RELOC_386_GOT32:
10969 case BFD_RELOC_386_GOT32X:
10970 case BFD_RELOC_386_GOTOFF:
10971 case BFD_RELOC_386_GOTPC:
10972 case BFD_RELOC_386_TLS_GD:
10973 case BFD_RELOC_386_TLS_LDM:
10974 case BFD_RELOC_386_TLS_LDO_32:
10975 case BFD_RELOC_386_TLS_IE_32:
10976 case BFD_RELOC_386_TLS_IE:
10977 case BFD_RELOC_386_TLS_GOTIE:
10978 case BFD_RELOC_386_TLS_LE_32:
10979 case BFD_RELOC_386_TLS_LE:
10980 case BFD_RELOC_386_TLS_GOTDESC:
10981 case BFD_RELOC_386_TLS_DESC_CALL:
10982 case BFD_RELOC_X86_64_TLSGD:
10983 case BFD_RELOC_X86_64_TLSLD:
10984 case BFD_RELOC_X86_64_DTPOFF32:
10985 case BFD_RELOC_X86_64_DTPOFF64:
10986 case BFD_RELOC_X86_64_GOTTPOFF:
10987 case BFD_RELOC_X86_64_TPOFF32:
10988 case BFD_RELOC_X86_64_TPOFF64:
10989 case BFD_RELOC_X86_64_GOTOFF64:
10990 case BFD_RELOC_X86_64_GOTPC32:
10991 case BFD_RELOC_X86_64_GOT64:
10992 case BFD_RELOC_X86_64_GOTPCREL64:
10993 case BFD_RELOC_X86_64_GOTPC64:
10994 case BFD_RELOC_X86_64_GOTPLT64:
10995 case BFD_RELOC_X86_64_PLTOFF64:
10996 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
10997 case BFD_RELOC_X86_64_TLSDESC_CALL:
10998 case BFD_RELOC_RVA:
10999 case BFD_RELOC_VTABLE_ENTRY:
11000 case BFD_RELOC_VTABLE_INHERIT:
11001 #ifdef TE_PE
11002 case BFD_RELOC_32_SECREL:
11003 #endif
11004 code = fixp->fx_r_type;
11005 break;
11006 case BFD_RELOC_X86_64_32S:
11007 if (!fixp->fx_pcrel)
11008 {
11009 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
11010 code = fixp->fx_r_type;
11011 break;
11012 }
11013 /* Fall through. */
11014 default:
11015 if (fixp->fx_pcrel)
11016 {
11017 switch (fixp->fx_size)
11018 {
11019 default:
11020 as_bad_where (fixp->fx_file, fixp->fx_line,
11021 _("can not do %d byte pc-relative relocation"),
11022 fixp->fx_size);
11023 code = BFD_RELOC_32_PCREL;
11024 break;
11025 case 1: code = BFD_RELOC_8_PCREL; break;
11026 case 2: code = BFD_RELOC_16_PCREL; break;
11027 case 4: code = BFD_RELOC_32_PCREL; break;
11028 #ifdef BFD64
11029 case 8: code = BFD_RELOC_64_PCREL; break;
11030 #endif
11031 }
11032 }
11033 else
11034 {
11035 switch (fixp->fx_size)
11036 {
11037 default:
11038 as_bad_where (fixp->fx_file, fixp->fx_line,
11039 _("can not do %d byte relocation"),
11040 fixp->fx_size);
11041 code = BFD_RELOC_32;
11042 break;
11043 case 1: code = BFD_RELOC_8; break;
11044 case 2: code = BFD_RELOC_16; break;
11045 case 4: code = BFD_RELOC_32; break;
11046 #ifdef BFD64
11047 case 8: code = BFD_RELOC_64; break;
11048 #endif
11049 }
11050 }
11051 break;
11052 }
11053
11054 if ((code == BFD_RELOC_32
11055 || code == BFD_RELOC_32_PCREL
11056 || code == BFD_RELOC_X86_64_32S)
11057 && GOT_symbol
11058 && fixp->fx_addsy == GOT_symbol)
11059 {
11060 if (!object_64bit)
11061 code = BFD_RELOC_386_GOTPC;
11062 else
11063 code = BFD_RELOC_X86_64_GOTPC32;
11064 }
11065 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
11066 && GOT_symbol
11067 && fixp->fx_addsy == GOT_symbol)
11068 {
11069 code = BFD_RELOC_X86_64_GOTPC64;
11070 }
11071
11072 rel = XNEW (arelent);
11073 rel->sym_ptr_ptr = XNEW (asymbol *);
11074 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
11075
11076 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
11077
11078 if (!use_rela_relocations)
11079 {
11080 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
11081 vtable entry to be used in the relocation's section offset. */
11082 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
11083 rel->address = fixp->fx_offset;
11084 #if defined (OBJ_COFF) && defined (TE_PE)
11085 else if (fixp->fx_addsy && S_IS_WEAK (fixp->fx_addsy))
11086 rel->addend = fixp->fx_addnumber - (S_GET_VALUE (fixp->fx_addsy) * 2);
11087 else
11088 #endif
11089 rel->addend = 0;
11090 }
11091 /* Use the rela in 64bit mode. */
11092 else
11093 {
11094 if (disallow_64bit_reloc)
11095 switch (code)
11096 {
11097 case BFD_RELOC_X86_64_DTPOFF64:
11098 case BFD_RELOC_X86_64_TPOFF64:
11099 case BFD_RELOC_64_PCREL:
11100 case BFD_RELOC_X86_64_GOTOFF64:
11101 case BFD_RELOC_X86_64_GOT64:
11102 case BFD_RELOC_X86_64_GOTPCREL64:
11103 case BFD_RELOC_X86_64_GOTPC64:
11104 case BFD_RELOC_X86_64_GOTPLT64:
11105 case BFD_RELOC_X86_64_PLTOFF64:
11106 as_bad_where (fixp->fx_file, fixp->fx_line,
11107 _("cannot represent relocation type %s in x32 mode"),
11108 bfd_get_reloc_code_name (code));
11109 break;
11110 default:
11111 break;
11112 }
11113
11114 if (!fixp->fx_pcrel)
11115 rel->addend = fixp->fx_offset;
11116 else
11117 switch (code)
11118 {
11119 case BFD_RELOC_X86_64_PLT32:
11120 case BFD_RELOC_X86_64_GOT32:
11121 case BFD_RELOC_X86_64_GOTPCREL:
11122 case BFD_RELOC_X86_64_GOTPCRELX:
11123 case BFD_RELOC_X86_64_REX_GOTPCRELX:
11124 case BFD_RELOC_X86_64_TLSGD:
11125 case BFD_RELOC_X86_64_TLSLD:
11126 case BFD_RELOC_X86_64_GOTTPOFF:
11127 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
11128 case BFD_RELOC_X86_64_TLSDESC_CALL:
11129 rel->addend = fixp->fx_offset - fixp->fx_size;
11130 break;
11131 default:
11132 rel->addend = (section->vma
11133 - fixp->fx_size
11134 + fixp->fx_addnumber
11135 + md_pcrel_from (fixp));
11136 break;
11137 }
11138 }
11139
11140 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
11141 if (rel->howto == NULL)
11142 {
11143 as_bad_where (fixp->fx_file, fixp->fx_line,
11144 _("cannot represent relocation type %s"),
11145 bfd_get_reloc_code_name (code));
11146 /* Set howto to a garbage value so that we can keep going. */
11147 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
11148 gas_assert (rel->howto != NULL);
11149 }
11150
11151 return rel;
11152 }
11153
11154 #include "tc-i386-intel.c"
11155
11156 void
11157 tc_x86_parse_to_dw2regnum (expressionS *exp)
11158 {
11159 int saved_naked_reg;
11160 char saved_register_dot;
11161
11162 saved_naked_reg = allow_naked_reg;
11163 allow_naked_reg = 1;
11164 saved_register_dot = register_chars['.'];
11165 register_chars['.'] = '.';
11166 allow_pseudo_reg = 1;
11167 expression_and_evaluate (exp);
11168 allow_pseudo_reg = 0;
11169 register_chars['.'] = saved_register_dot;
11170 allow_naked_reg = saved_naked_reg;
11171
11172 if (exp->X_op == O_register && exp->X_add_number >= 0)
11173 {
11174 if ((addressT) exp->X_add_number < i386_regtab_size)
11175 {
11176 exp->X_op = O_constant;
11177 exp->X_add_number = i386_regtab[exp->X_add_number]
11178 .dw2_regnum[flag_code >> 1];
11179 }
11180 else
11181 exp->X_op = O_illegal;
11182 }
11183 }
11184
11185 void
11186 tc_x86_frame_initial_instructions (void)
11187 {
11188 static unsigned int sp_regno[2];
11189
11190 if (!sp_regno[flag_code >> 1])
11191 {
11192 char *saved_input = input_line_pointer;
11193 char sp[][4] = {"esp", "rsp"};
11194 expressionS exp;
11195
11196 input_line_pointer = sp[flag_code >> 1];
11197 tc_x86_parse_to_dw2regnum (&exp);
11198 gas_assert (exp.X_op == O_constant);
11199 sp_regno[flag_code >> 1] = exp.X_add_number;
11200 input_line_pointer = saved_input;
11201 }
11202
11203 cfi_add_CFA_def_cfa (sp_regno[flag_code >> 1], -x86_cie_data_alignment);
11204 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
11205 }
11206
11207 int
11208 x86_dwarf2_addr_size (void)
11209 {
11210 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
11211 if (x86_elf_abi == X86_64_X32_ABI)
11212 return 4;
11213 #endif
11214 return bfd_arch_bits_per_address (stdoutput) / 8;
11215 }
11216
11217 int
11218 i386_elf_section_type (const char *str, size_t len)
11219 {
11220 if (flag_code == CODE_64BIT
11221 && len == sizeof ("unwind") - 1
11222 && strncmp (str, "unwind", 6) == 0)
11223 return SHT_X86_64_UNWIND;
11224
11225 return -1;
11226 }
11227
11228 #ifdef TE_SOLARIS
11229 void
11230 i386_solaris_fix_up_eh_frame (segT sec)
11231 {
11232 if (flag_code == CODE_64BIT)
11233 elf_section_type (sec) = SHT_X86_64_UNWIND;
11234 }
11235 #endif
11236
11237 #ifdef TE_PE
11238 void
11239 tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
11240 {
11241 expressionS exp;
11242
11243 exp.X_op = O_secrel;
11244 exp.X_add_symbol = symbol;
11245 exp.X_add_number = 0;
11246 emit_expr (&exp, size);
11247 }
11248 #endif
11249
11250 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11251 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
11252
11253 bfd_vma
11254 x86_64_section_letter (int letter, const char **ptr_msg)
11255 {
11256 if (flag_code == CODE_64BIT)
11257 {
11258 if (letter == 'l')
11259 return SHF_X86_64_LARGE;
11260
11261 *ptr_msg = _("bad .section directive: want a,l,w,x,M,S,G,T in string");
11262 }
11263 else
11264 *ptr_msg = _("bad .section directive: want a,w,x,M,S,G,T in string");
11265 return -1;
11266 }
11267
11268 bfd_vma
11269 x86_64_section_word (char *str, size_t len)
11270 {
11271 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
11272 return SHF_X86_64_LARGE;
11273
11274 return -1;
11275 }
11276
11277 static void
11278 handle_large_common (int small ATTRIBUTE_UNUSED)
11279 {
11280 if (flag_code != CODE_64BIT)
11281 {
11282 s_comm_internal (0, elf_common_parse);
11283 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
11284 }
11285 else
11286 {
11287 static segT lbss_section;
11288 asection *saved_com_section_ptr = elf_com_section_ptr;
11289 asection *saved_bss_section = bss_section;
11290
11291 if (lbss_section == NULL)
11292 {
11293 flagword applicable;
11294 segT seg = now_seg;
11295 subsegT subseg = now_subseg;
11296
11297 /* The .lbss section is for local .largecomm symbols. */
11298 lbss_section = subseg_new (".lbss", 0);
11299 applicable = bfd_applicable_section_flags (stdoutput);
11300 bfd_set_section_flags (stdoutput, lbss_section,
11301 applicable & SEC_ALLOC);
11302 seg_info (lbss_section)->bss = 1;
11303
11304 subseg_set (seg, subseg);
11305 }
11306
11307 elf_com_section_ptr = &_bfd_elf_large_com_section;
11308 bss_section = lbss_section;
11309
11310 s_comm_internal (0, elf_common_parse);
11311
11312 elf_com_section_ptr = saved_com_section_ptr;
11313 bss_section = saved_bss_section;
11314 }
11315 }
11316 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
GDB Binutils - Deliverables
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