1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
4 Free Software Foundation, Inc.
6 This file is part of GAS, the GNU Assembler.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
23 /* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
25 x86_64 support by Jan Hubicka (jh@suse.cz)
26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
27 Bugs & suggestions are completely welcome. This is free software.
28 Please help us make it better. */
31 #include "safe-ctype.h"
33 #include "dwarf2dbg.h"
34 #include "dw2gencfi.h"
35 #include "elf/x86-64.h"
36 #include "opcodes/i386-init.h"
38 #ifndef REGISTER_WARNINGS
39 #define REGISTER_WARNINGS 1
42 #ifndef INFER_ADDR_PREFIX
43 #define INFER_ADDR_PREFIX 1
47 #define DEFAULT_ARCH "i386"
52 #define INLINE __inline__
58 /* Prefixes will be emitted in the order defined below.
59 WAIT_PREFIX must be the first prefix since FWAIT is really is an
60 instruction, and so must come before any prefixes.
61 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
62 REP_PREFIX, LOCK_PREFIX. */
69 #define REX_PREFIX 6 /* must come last. */
70 #define MAX_PREFIXES 7 /* max prefixes per opcode */
72 /* we define the syntax here (modulo base,index,scale syntax) */
73 #define REGISTER_PREFIX '%'
74 #define IMMEDIATE_PREFIX '$'
75 #define ABSOLUTE_PREFIX '*'
77 /* these are the instruction mnemonic suffixes in AT&T syntax or
78 memory operand size in Intel syntax. */
79 #define WORD_MNEM_SUFFIX 'w'
80 #define BYTE_MNEM_SUFFIX 'b'
81 #define SHORT_MNEM_SUFFIX 's'
82 #define LONG_MNEM_SUFFIX 'l'
83 #define QWORD_MNEM_SUFFIX 'q'
84 #define XMMWORD_MNEM_SUFFIX 'x'
85 #define YMMWORD_MNEM_SUFFIX 'y'
86 /* Intel Syntax. Use a non-ascii letter since since it never appears
88 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
90 #define END_OF_INSN '\0'
93 'templates' is for grouping together 'template' structures for opcodes
94 of the same name. This is only used for storing the insns in the grand
95 ole hash table of insns.
96 The templates themselves start at START and range up to (but not including)
101 const insn_template
*start
;
102 const insn_template
*end
;
106 /* 386 operand encoding bytes: see 386 book for details of this. */
109 unsigned int regmem
; /* codes register or memory operand */
110 unsigned int reg
; /* codes register operand (or extended opcode) */
111 unsigned int mode
; /* how to interpret regmem & reg */
115 /* x86-64 extension prefix. */
116 typedef int rex_byte
;
118 /* 386 opcode byte to code indirect addressing. */
127 /* x86 arch names, types and features */
130 const char *name
; /* arch name */
131 unsigned int len
; /* arch string length */
132 enum processor_type type
; /* arch type */
133 i386_cpu_flags flags
; /* cpu feature flags */
134 unsigned int skip
; /* show_arch should skip this. */
138 static void set_code_flag (int);
139 static void set_16bit_gcc_code_flag (int);
140 static void set_intel_syntax (int);
141 static void set_intel_mnemonic (int);
142 static void set_allow_index_reg (int);
143 static void set_sse_check (int);
144 static void set_cpu_arch (int);
146 static void pe_directive_secrel (int);
148 static void signed_cons (int);
149 static char *output_invalid (int c
);
150 static int i386_finalize_immediate (segT
, expressionS
*, i386_operand_type
,
152 static int i386_finalize_displacement (segT
, expressionS
*, i386_operand_type
,
154 static int i386_att_operand (char *);
155 static int i386_intel_operand (char *, int);
156 static int i386_intel_simplify (expressionS
*);
157 static int i386_intel_parse_name (const char *, expressionS
*);
158 static const reg_entry
*parse_register (char *, char **);
159 static char *parse_insn (char *, char *);
160 static char *parse_operands (char *, const char *);
161 static void swap_operands (void);
162 static void swap_2_operands (int, int);
163 static void optimize_imm (void);
164 static void optimize_disp (void);
165 static const insn_template
*match_template (void);
166 static int check_string (void);
167 static int process_suffix (void);
168 static int check_byte_reg (void);
169 static int check_long_reg (void);
170 static int check_qword_reg (void);
171 static int check_word_reg (void);
172 static int finalize_imm (void);
173 static int process_operands (void);
174 static const seg_entry
*build_modrm_byte (void);
175 static void output_insn (void);
176 static void output_imm (fragS
*, offsetT
);
177 static void output_disp (fragS
*, offsetT
);
179 static void s_bss (int);
181 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
182 static void handle_large_common (int small ATTRIBUTE_UNUSED
);
185 static const char *default_arch
= DEFAULT_ARCH
;
190 /* VEX prefix is either 2 byte or 3 byte. */
191 unsigned char bytes
[3];
193 /* Destination or source register specifier. */
194 const reg_entry
*register_specifier
;
197 /* 'md_assemble ()' gathers together information and puts it into a
204 const reg_entry
*regs
;
209 /* TM holds the template for the insn were currently assembling. */
212 /* SUFFIX holds the instruction size suffix for byte, word, dword
213 or qword, if given. */
216 /* OPERANDS gives the number of given operands. */
217 unsigned int operands
;
219 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
220 of given register, displacement, memory operands and immediate
222 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
224 /* TYPES [i] is the type (see above #defines) which tells us how to
225 use OP[i] for the corresponding operand. */
226 i386_operand_type types
[MAX_OPERANDS
];
228 /* Displacement expression, immediate expression, or register for each
230 union i386_op op
[MAX_OPERANDS
];
232 /* Flags for operands. */
233 unsigned int flags
[MAX_OPERANDS
];
234 #define Operand_PCrel 1
236 /* Relocation type for operand */
237 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
239 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
240 the base index byte below. */
241 const reg_entry
*base_reg
;
242 const reg_entry
*index_reg
;
243 unsigned int log2_scale_factor
;
245 /* SEG gives the seg_entries of this insn. They are zero unless
246 explicit segment overrides are given. */
247 const seg_entry
*seg
[2];
249 /* PREFIX holds all the given prefix opcodes (usually null).
250 PREFIXES is the number of prefix opcodes. */
251 unsigned int prefixes
;
252 unsigned char prefix
[MAX_PREFIXES
];
254 /* RM and SIB are the modrm byte and the sib byte where the
255 addressing modes of this insn are encoded. */
261 /* Swap operand in encoding. */
262 unsigned int swap_operand
;
265 typedef struct _i386_insn i386_insn
;
267 /* List of chars besides those in app.c:symbol_chars that can start an
268 operand. Used to prevent the scrubber eating vital white-space. */
269 const char extra_symbol_chars
[] = "*%-(["
278 #if (defined (TE_I386AIX) \
279 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
280 && !defined (TE_GNU) \
281 && !defined (TE_LINUX) \
282 && !defined (TE_NETWARE) \
283 && !defined (TE_FreeBSD) \
284 && !defined (TE_NetBSD)))
285 /* This array holds the chars that always start a comment. If the
286 pre-processor is disabled, these aren't very useful. The option
287 --divide will remove '/' from this list. */
288 const char *i386_comment_chars
= "#/";
289 #define SVR4_COMMENT_CHARS 1
290 #define PREFIX_SEPARATOR '\\'
293 const char *i386_comment_chars
= "#";
294 #define PREFIX_SEPARATOR '/'
297 /* This array holds the chars that only start a comment at the beginning of
298 a line. If the line seems to have the form '# 123 filename'
299 .line and .file directives will appear in the pre-processed output.
300 Note that input_file.c hand checks for '#' at the beginning of the
301 first line of the input file. This is because the compiler outputs
302 #NO_APP at the beginning of its output.
303 Also note that comments started like this one will always work if
304 '/' isn't otherwise defined. */
305 const char line_comment_chars
[] = "#/";
307 const char line_separator_chars
[] = ";";
309 /* Chars that can be used to separate mant from exp in floating point
311 const char EXP_CHARS
[] = "eE";
313 /* Chars that mean this number is a floating point constant
316 const char FLT_CHARS
[] = "fFdDxX";
318 /* Tables for lexical analysis. */
319 static char mnemonic_chars
[256];
320 static char register_chars
[256];
321 static char operand_chars
[256];
322 static char identifier_chars
[256];
323 static char digit_chars
[256];
325 /* Lexical macros. */
326 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
327 #define is_operand_char(x) (operand_chars[(unsigned char) x])
328 #define is_register_char(x) (register_chars[(unsigned char) x])
329 #define is_space_char(x) ((x) == ' ')
330 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
331 #define is_digit_char(x) (digit_chars[(unsigned char) x])
333 /* All non-digit non-letter characters that may occur in an operand. */
334 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
336 /* md_assemble() always leaves the strings it's passed unaltered. To
337 effect this we maintain a stack of saved characters that we've smashed
338 with '\0's (indicating end of strings for various sub-fields of the
339 assembler instruction). */
340 static char save_stack
[32];
341 static char *save_stack_p
;
342 #define END_STRING_AND_SAVE(s) \
343 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
344 #define RESTORE_END_STRING(s) \
345 do { *(s) = *--save_stack_p; } while (0)
347 /* The instruction we're assembling. */
350 /* Possible templates for current insn. */
351 static const templates
*current_templates
;
353 /* Per instruction expressionS buffers: max displacements & immediates. */
354 static expressionS disp_expressions
[MAX_MEMORY_OPERANDS
];
355 static expressionS im_expressions
[MAX_IMMEDIATE_OPERANDS
];
357 /* Current operand we are working on. */
358 static int this_operand
= -1;
360 /* We support four different modes. FLAG_CODE variable is used to distinguish
368 static enum flag_code flag_code
;
369 static unsigned int object_64bit
;
370 static int use_rela_relocations
= 0;
372 /* The names used to print error messages. */
373 static const char *flag_code_names
[] =
380 /* 1 for intel syntax,
382 static int intel_syntax
= 0;
384 /* 1 for intel mnemonic,
385 0 if att mnemonic. */
386 static int intel_mnemonic
= !SYSV386_COMPAT
;
388 /* 1 if support old (<= 2.8.1) versions of gcc. */
389 static int old_gcc
= OLDGCC_COMPAT
;
391 /* 1 if pseudo registers are permitted. */
392 static int allow_pseudo_reg
= 0;
394 /* 1 if register prefix % not required. */
395 static int allow_naked_reg
= 0;
397 /* 1 if pseudo index register, eiz/riz, is allowed . */
398 static int allow_index_reg
= 0;
408 /* Register prefix used for error message. */
409 static const char *register_prefix
= "%";
411 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
412 leave, push, and pop instructions so that gcc has the same stack
413 frame as in 32 bit mode. */
414 static char stackop_size
= '\0';
416 /* Non-zero to optimize code alignment. */
417 int optimize_align_code
= 1;
419 /* Non-zero to quieten some warnings. */
420 static int quiet_warnings
= 0;
423 static const char *cpu_arch_name
= NULL
;
424 static char *cpu_sub_arch_name
= NULL
;
426 /* CPU feature flags. */
427 static i386_cpu_flags cpu_arch_flags
= CPU_UNKNOWN_FLAGS
;
429 /* If we have selected a cpu we are generating instructions for. */
430 static int cpu_arch_tune_set
= 0;
432 /* Cpu we are generating instructions for. */
433 enum processor_type cpu_arch_tune
= PROCESSOR_UNKNOWN
;
435 /* CPU feature flags of cpu we are generating instructions for. */
436 static i386_cpu_flags cpu_arch_tune_flags
;
438 /* CPU instruction set architecture used. */
439 enum processor_type cpu_arch_isa
= PROCESSOR_UNKNOWN
;
441 /* CPU feature flags of instruction set architecture used. */
442 i386_cpu_flags cpu_arch_isa_flags
;
444 /* If set, conditional jumps are not automatically promoted to handle
445 larger than a byte offset. */
446 static unsigned int no_cond_jump_promotion
= 0;
448 /* Encode SSE instructions with VEX prefix. */
449 static unsigned int sse2avx
;
451 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
452 static symbolS
*GOT_symbol
;
454 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
455 unsigned int x86_dwarf2_return_column
;
457 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
458 int x86_cie_data_alignment
;
460 /* Interface to relax_segment.
461 There are 3 major relax states for 386 jump insns because the
462 different types of jumps add different sizes to frags when we're
463 figuring out what sort of jump to choose to reach a given label. */
466 #define UNCOND_JUMP 0
468 #define COND_JUMP86 2
473 #define SMALL16 (SMALL | CODE16)
475 #define BIG16 (BIG | CODE16)
479 #define INLINE __inline__
485 #define ENCODE_RELAX_STATE(type, size) \
486 ((relax_substateT) (((type) << 2) | (size)))
487 #define TYPE_FROM_RELAX_STATE(s) \
489 #define DISP_SIZE_FROM_RELAX_STATE(s) \
490 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
492 /* This table is used by relax_frag to promote short jumps to long
493 ones where necessary. SMALL (short) jumps may be promoted to BIG
494 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
495 don't allow a short jump in a 32 bit code segment to be promoted to
496 a 16 bit offset jump because it's slower (requires data size
497 prefix), and doesn't work, unless the destination is in the bottom
498 64k of the code segment (The top 16 bits of eip are zeroed). */
500 const relax_typeS md_relax_table
[] =
503 1) most positive reach of this state,
504 2) most negative reach of this state,
505 3) how many bytes this mode will have in the variable part of the frag
506 4) which index into the table to try if we can't fit into this one. */
508 /* UNCOND_JUMP states. */
509 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
510 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
511 /* dword jmp adds 4 bytes to frag:
512 0 extra opcode bytes, 4 displacement bytes. */
514 /* word jmp adds 2 byte2 to frag:
515 0 extra opcode bytes, 2 displacement bytes. */
518 /* COND_JUMP states. */
519 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
520 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
521 /* dword conditionals adds 5 bytes to frag:
522 1 extra opcode byte, 4 displacement bytes. */
524 /* word conditionals add 3 bytes to frag:
525 1 extra opcode byte, 2 displacement bytes. */
528 /* COND_JUMP86 states. */
529 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
530 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
531 /* dword conditionals adds 5 bytes to frag:
532 1 extra opcode byte, 4 displacement bytes. */
534 /* word conditionals add 4 bytes to frag:
535 1 displacement byte and a 3 byte long branch insn. */
539 static const arch_entry cpu_arch
[] =
541 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32
,
542 CPU_GENERIC32_FLAGS
, 0 },
543 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64
,
544 CPU_GENERIC64_FLAGS
, 0 },
545 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN
,
547 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN
,
549 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN
,
551 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386
,
553 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486
,
555 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM
,
557 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO
,
559 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM
,
561 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO
,
563 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO
,
565 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO
,
567 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4
,
569 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA
,
571 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA
,
572 CPU_NOCONA_FLAGS
, 0 },
573 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE
,
575 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE
,
577 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2
,
578 CPU_CORE2_FLAGS
, 1 },
579 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2
,
580 CPU_CORE2_FLAGS
, 0 },
581 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7
,
582 CPU_COREI7_FLAGS
, 0 },
583 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM
,
585 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6
,
587 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6
,
589 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON
,
590 CPU_ATHLON_FLAGS
, 0 },
591 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8
,
593 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8
,
595 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8
,
597 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10
,
598 CPU_AMDFAM10_FLAGS
, 0 },
599 { STRING_COMMA_LEN ("amdfam15"), PROCESSOR_AMDFAM15
,
600 CPU_AMDFAM15_FLAGS
, 0 },
601 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN
,
603 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN
,
605 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN
,
607 { STRING_COMMA_LEN (".no87"), PROCESSOR_UNKNOWN
,
608 CPU_ANY87_FLAGS
, 0 },
609 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN
,
611 { STRING_COMMA_LEN (".nommx"), PROCESSOR_UNKNOWN
,
612 CPU_3DNOWA_FLAGS
, 0 },
613 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN
,
615 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN
,
617 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN
,
619 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN
,
620 CPU_SSSE3_FLAGS
, 0 },
621 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN
,
622 CPU_SSE4_1_FLAGS
, 0 },
623 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN
,
624 CPU_SSE4_2_FLAGS
, 0 },
625 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN
,
626 CPU_SSE4_2_FLAGS
, 0 },
627 { STRING_COMMA_LEN (".nosse"), PROCESSOR_UNKNOWN
,
628 CPU_ANY_SSE_FLAGS
, 0 },
629 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN
,
631 { STRING_COMMA_LEN (".noavx"), PROCESSOR_UNKNOWN
,
632 CPU_ANY_AVX_FLAGS
, 0 },
633 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN
,
635 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN
,
637 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN
,
638 CPU_XSAVE_FLAGS
, 0 },
639 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN
,
641 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN
,
642 CPU_PCLMUL_FLAGS
, 0 },
643 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN
,
644 CPU_PCLMUL_FLAGS
, 1 },
645 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN
,
647 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN
,
649 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN
,
651 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN
,
653 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN
,
654 CPU_MOVBE_FLAGS
, 0 },
655 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN
,
657 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN
,
658 CPU_CLFLUSH_FLAGS
, 0 },
659 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN
,
660 CPU_SYSCALL_FLAGS
, 0 },
661 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN
,
662 CPU_RDTSCP_FLAGS
, 0 },
663 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN
,
664 CPU_3DNOW_FLAGS
, 0 },
665 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN
,
666 CPU_3DNOWA_FLAGS
, 0 },
667 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN
,
668 CPU_PADLOCK_FLAGS
, 0 },
669 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN
,
671 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN
,
673 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN
,
674 CPU_SSE4A_FLAGS
, 0 },
675 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN
,
680 /* Like s_lcomm_internal in gas/read.c but the alignment string
681 is allowed to be optional. */
684 pe_lcomm_internal (int needs_align
, symbolS
*symbolP
, addressT size
)
691 && *input_line_pointer
== ',')
693 align
= parse_align (needs_align
- 1);
695 if (align
== (addressT
) -1)
710 bss_alloc (symbolP
, size
, align
);
715 pe_lcomm (int needs_align
)
717 s_comm_internal (needs_align
* 2, pe_lcomm_internal
);
721 const pseudo_typeS md_pseudo_table
[] =
723 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
724 {"align", s_align_bytes
, 0},
726 {"align", s_align_ptwo
, 0},
728 {"arch", set_cpu_arch
, 0},
732 {"lcomm", pe_lcomm
, 1},
734 {"ffloat", float_cons
, 'f'},
735 {"dfloat", float_cons
, 'd'},
736 {"tfloat", float_cons
, 'x'},
738 {"slong", signed_cons
, 4},
739 {"noopt", s_ignore
, 0},
740 {"optim", s_ignore
, 0},
741 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
742 {"code16", set_code_flag
, CODE_16BIT
},
743 {"code32", set_code_flag
, CODE_32BIT
},
744 {"code64", set_code_flag
, CODE_64BIT
},
745 {"intel_syntax", set_intel_syntax
, 1},
746 {"att_syntax", set_intel_syntax
, 0},
747 {"intel_mnemonic", set_intel_mnemonic
, 1},
748 {"att_mnemonic", set_intel_mnemonic
, 0},
749 {"allow_index_reg", set_allow_index_reg
, 1},
750 {"disallow_index_reg", set_allow_index_reg
, 0},
751 {"sse_check", set_sse_check
, 0},
752 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
753 {"largecomm", handle_large_common
, 0},
755 {"file", (void (*) (int)) dwarf2_directive_file
, 0},
756 {"loc", dwarf2_directive_loc
, 0},
757 {"loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0},
760 {"secrel32", pe_directive_secrel
, 0},
765 /* For interface with expression (). */
766 extern char *input_line_pointer
;
768 /* Hash table for instruction mnemonic lookup. */
769 static struct hash_control
*op_hash
;
771 /* Hash table for register lookup. */
772 static struct hash_control
*reg_hash
;
775 i386_align_code (fragS
*fragP
, int count
)
777 /* Various efficient no-op patterns for aligning code labels.
778 Note: Don't try to assemble the instructions in the comments.
779 0L and 0w are not legal. */
780 static const char f32_1
[] =
782 static const char f32_2
[] =
783 {0x66,0x90}; /* xchg %ax,%ax */
784 static const char f32_3
[] =
785 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
786 static const char f32_4
[] =
787 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
788 static const char f32_5
[] =
790 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
791 static const char f32_6
[] =
792 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
793 static const char f32_7
[] =
794 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
795 static const char f32_8
[] =
797 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
798 static const char f32_9
[] =
799 {0x89,0xf6, /* movl %esi,%esi */
800 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
801 static const char f32_10
[] =
802 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
803 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
804 static const char f32_11
[] =
805 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
806 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
807 static const char f32_12
[] =
808 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
809 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
810 static const char f32_13
[] =
811 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
812 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
813 static const char f32_14
[] =
814 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
815 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
816 static const char f16_3
[] =
817 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
818 static const char f16_4
[] =
819 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
820 static const char f16_5
[] =
822 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
823 static const char f16_6
[] =
824 {0x89,0xf6, /* mov %si,%si */
825 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
826 static const char f16_7
[] =
827 {0x8d,0x74,0x00, /* lea 0(%si),%si */
828 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
829 static const char f16_8
[] =
830 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
831 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
832 static const char jump_31
[] =
833 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
834 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
835 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
836 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
837 static const char *const f32_patt
[] = {
838 f32_1
, f32_2
, f32_3
, f32_4
, f32_5
, f32_6
, f32_7
, f32_8
,
839 f32_9
, f32_10
, f32_11
, f32_12
, f32_13
, f32_14
841 static const char *const f16_patt
[] = {
842 f32_1
, f32_2
, f16_3
, f16_4
, f16_5
, f16_6
, f16_7
, f16_8
845 static const char alt_3
[] =
847 /* nopl 0(%[re]ax) */
848 static const char alt_4
[] =
849 {0x0f,0x1f,0x40,0x00};
850 /* nopl 0(%[re]ax,%[re]ax,1) */
851 static const char alt_5
[] =
852 {0x0f,0x1f,0x44,0x00,0x00};
853 /* nopw 0(%[re]ax,%[re]ax,1) */
854 static const char alt_6
[] =
855 {0x66,0x0f,0x1f,0x44,0x00,0x00};
856 /* nopl 0L(%[re]ax) */
857 static const char alt_7
[] =
858 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
859 /* nopl 0L(%[re]ax,%[re]ax,1) */
860 static const char alt_8
[] =
861 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
862 /* nopw 0L(%[re]ax,%[re]ax,1) */
863 static const char alt_9
[] =
864 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
865 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
866 static const char alt_10
[] =
867 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
869 nopw %cs:0L(%[re]ax,%[re]ax,1) */
870 static const char alt_long_11
[] =
872 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
875 nopw %cs:0L(%[re]ax,%[re]ax,1) */
876 static const char alt_long_12
[] =
879 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
883 nopw %cs:0L(%[re]ax,%[re]ax,1) */
884 static const char alt_long_13
[] =
888 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
893 nopw %cs:0L(%[re]ax,%[re]ax,1) */
894 static const char alt_long_14
[] =
899 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
905 nopw %cs:0L(%[re]ax,%[re]ax,1) */
906 static const char alt_long_15
[] =
912 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
913 /* nopl 0(%[re]ax,%[re]ax,1)
914 nopw 0(%[re]ax,%[re]ax,1) */
915 static const char alt_short_11
[] =
916 {0x0f,0x1f,0x44,0x00,0x00,
917 0x66,0x0f,0x1f,0x44,0x00,0x00};
918 /* nopw 0(%[re]ax,%[re]ax,1)
919 nopw 0(%[re]ax,%[re]ax,1) */
920 static const char alt_short_12
[] =
921 {0x66,0x0f,0x1f,0x44,0x00,0x00,
922 0x66,0x0f,0x1f,0x44,0x00,0x00};
923 /* nopw 0(%[re]ax,%[re]ax,1)
925 static const char alt_short_13
[] =
926 {0x66,0x0f,0x1f,0x44,0x00,0x00,
927 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
930 static const char alt_short_14
[] =
931 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
932 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
934 nopl 0L(%[re]ax,%[re]ax,1) */
935 static const char alt_short_15
[] =
936 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
937 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
938 static const char *const alt_short_patt
[] = {
939 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
940 alt_9
, alt_10
, alt_short_11
, alt_short_12
, alt_short_13
,
941 alt_short_14
, alt_short_15
943 static const char *const alt_long_patt
[] = {
944 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
945 alt_9
, alt_10
, alt_long_11
, alt_long_12
, alt_long_13
,
946 alt_long_14
, alt_long_15
949 /* Only align for at least a positive non-zero boundary. */
950 if (count
<= 0 || count
> MAX_MEM_FOR_RS_ALIGN_CODE
)
953 /* We need to decide which NOP sequence to use for 32bit and
954 64bit. When -mtune= is used:
956 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
957 PROCESSOR_GENERIC32, f32_patt will be used.
958 2. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
959 PROCESSOR_CORE, PROCESSOR_CORE2, PROCESSOR_COREI7, and
960 PROCESSOR_GENERIC64, alt_long_patt will be used.
961 3. For PROCESSOR_ATHLON, PROCESSOR_K6, PROCESSOR_K8 and
962 PROCESSOR_AMDFAM10, and PROCESSOR_AMDFAM15, alt_short_patt
965 When -mtune= isn't used, alt_long_patt will be used if
966 cpu_arch_isa_flags has Cpu686. Otherwise, f32_patt will
969 When -march= or .arch is used, we can't use anything beyond
970 cpu_arch_isa_flags. */
972 if (flag_code
== CODE_16BIT
)
976 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
978 /* Adjust jump offset. */
979 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
982 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
983 f16_patt
[count
- 1], count
);
987 const char *const *patt
= NULL
;
989 if (fragP
->tc_frag_data
.isa
== PROCESSOR_UNKNOWN
)
991 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
992 switch (cpu_arch_tune
)
994 case PROCESSOR_UNKNOWN
:
995 /* We use cpu_arch_isa_flags to check if we SHOULD
996 optimize for Cpu686. */
997 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpui686
)
998 patt
= alt_long_patt
;
1002 case PROCESSOR_PENTIUMPRO
:
1003 case PROCESSOR_PENTIUM4
:
1004 case PROCESSOR_NOCONA
:
1005 case PROCESSOR_CORE
:
1006 case PROCESSOR_CORE2
:
1007 case PROCESSOR_COREI7
:
1008 case PROCESSOR_L1OM
:
1009 case PROCESSOR_GENERIC64
:
1010 patt
= alt_long_patt
;
1013 case PROCESSOR_ATHLON
:
1015 case PROCESSOR_AMDFAM10
:
1016 case PROCESSOR_AMDFAM15
:
1017 patt
= alt_short_patt
;
1019 case PROCESSOR_I386
:
1020 case PROCESSOR_I486
:
1021 case PROCESSOR_PENTIUM
:
1022 case PROCESSOR_GENERIC32
:
1029 switch (fragP
->tc_frag_data
.tune
)
1031 case PROCESSOR_UNKNOWN
:
1032 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1033 PROCESSOR_UNKNOWN. */
1037 case PROCESSOR_I386
:
1038 case PROCESSOR_I486
:
1039 case PROCESSOR_PENTIUM
:
1041 case PROCESSOR_ATHLON
:
1043 case PROCESSOR_AMDFAM10
:
1044 case PROCESSOR_AMDFAM15
:
1045 case PROCESSOR_GENERIC32
:
1046 /* We use cpu_arch_isa_flags to check if we CAN optimize
1048 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpui686
)
1049 patt
= alt_short_patt
;
1053 case PROCESSOR_PENTIUMPRO
:
1054 case PROCESSOR_PENTIUM4
:
1055 case PROCESSOR_NOCONA
:
1056 case PROCESSOR_CORE
:
1057 case PROCESSOR_CORE2
:
1058 case PROCESSOR_COREI7
:
1059 case PROCESSOR_L1OM
:
1060 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpui686
)
1061 patt
= alt_long_patt
;
1065 case PROCESSOR_GENERIC64
:
1066 patt
= alt_long_patt
;
1071 if (patt
== f32_patt
)
1073 /* If the padding is less than 15 bytes, we use the normal
1074 ones. Otherwise, we use a jump instruction and adjust
1078 /* For 64bit, the limit is 3 bytes. */
1079 if (flag_code
== CODE_64BIT
1080 && fragP
->tc_frag_data
.isa_flags
.bitfield
.cpulm
)
1085 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1086 patt
[count
- 1], count
);
1089 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1091 /* Adjust jump offset. */
1092 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
1097 /* Maximum length of an instruction is 15 byte. If the
1098 padding is greater than 15 bytes and we don't use jump,
1099 we have to break it into smaller pieces. */
1100 int padding
= count
;
1101 while (padding
> 15)
1104 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
+ padding
,
1109 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1110 patt
[padding
- 1], padding
);
1113 fragP
->fr_var
= count
;
1117 operand_type_all_zero (const union i386_operand_type
*x
)
1119 switch (ARRAY_SIZE(x
->array
))
1128 return !x
->array
[0];
1135 operand_type_set (union i386_operand_type
*x
, unsigned int v
)
1137 switch (ARRAY_SIZE(x
->array
))
1152 operand_type_equal (const union i386_operand_type
*x
,
1153 const union i386_operand_type
*y
)
1155 switch (ARRAY_SIZE(x
->array
))
1158 if (x
->array
[2] != y
->array
[2])
1161 if (x
->array
[1] != y
->array
[1])
1164 return x
->array
[0] == y
->array
[0];
1172 cpu_flags_all_zero (const union i386_cpu_flags
*x
)
1174 switch (ARRAY_SIZE(x
->array
))
1183 return !x
->array
[0];
1190 cpu_flags_set (union i386_cpu_flags
*x
, unsigned int v
)
1192 switch (ARRAY_SIZE(x
->array
))
1207 cpu_flags_equal (const union i386_cpu_flags
*x
,
1208 const union i386_cpu_flags
*y
)
1210 switch (ARRAY_SIZE(x
->array
))
1213 if (x
->array
[2] != y
->array
[2])
1216 if (x
->array
[1] != y
->array
[1])
1219 return x
->array
[0] == y
->array
[0];
1227 cpu_flags_check_cpu64 (i386_cpu_flags f
)
1229 return !((flag_code
== CODE_64BIT
&& f
.bitfield
.cpuno64
)
1230 || (flag_code
!= CODE_64BIT
&& f
.bitfield
.cpu64
));
1233 static INLINE i386_cpu_flags
1234 cpu_flags_and (i386_cpu_flags x
, i386_cpu_flags y
)
1236 switch (ARRAY_SIZE (x
.array
))
1239 x
.array
[2] &= y
.array
[2];
1241 x
.array
[1] &= y
.array
[1];
1243 x
.array
[0] &= y
.array
[0];
1251 static INLINE i386_cpu_flags
1252 cpu_flags_or (i386_cpu_flags x
, i386_cpu_flags y
)
1254 switch (ARRAY_SIZE (x
.array
))
1257 x
.array
[2] |= y
.array
[2];
1259 x
.array
[1] |= y
.array
[1];
1261 x
.array
[0] |= y
.array
[0];
1269 static INLINE i386_cpu_flags
1270 cpu_flags_and_not (i386_cpu_flags x
, i386_cpu_flags y
)
1272 switch (ARRAY_SIZE (x
.array
))
1275 x
.array
[2] &= ~y
.array
[2];
1277 x
.array
[1] &= ~y
.array
[1];
1279 x
.array
[0] &= ~y
.array
[0];
1287 #define CPU_FLAGS_ARCH_MATCH 0x1
1288 #define CPU_FLAGS_64BIT_MATCH 0x2
1289 #define CPU_FLAGS_AES_MATCH 0x4
1290 #define CPU_FLAGS_PCLMUL_MATCH 0x8
1291 #define CPU_FLAGS_AVX_MATCH 0x10
1293 #define CPU_FLAGS_32BIT_MATCH \
1294 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH \
1295 | CPU_FLAGS_PCLMUL_MATCH | CPU_FLAGS_AVX_MATCH)
1296 #define CPU_FLAGS_PERFECT_MATCH \
1297 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)
1299 /* Return CPU flags match bits. */
1302 cpu_flags_match (const insn_template
*t
)
1304 i386_cpu_flags x
= t
->cpu_flags
;
1305 int match
= cpu_flags_check_cpu64 (x
) ? CPU_FLAGS_64BIT_MATCH
: 0;
1307 x
.bitfield
.cpu64
= 0;
1308 x
.bitfield
.cpuno64
= 0;
1310 if (cpu_flags_all_zero (&x
))
1312 /* This instruction is available on all archs. */
1313 match
|= CPU_FLAGS_32BIT_MATCH
;
1317 /* This instruction is available only on some archs. */
1318 i386_cpu_flags cpu
= cpu_arch_flags
;
1320 cpu
.bitfield
.cpu64
= 0;
1321 cpu
.bitfield
.cpuno64
= 0;
1322 cpu
= cpu_flags_and (x
, cpu
);
1323 if (!cpu_flags_all_zero (&cpu
))
1325 if (x
.bitfield
.cpuavx
)
1327 /* We only need to check AES/PCLMUL/SSE2AVX with AVX. */
1328 if (cpu
.bitfield
.cpuavx
)
1330 /* Check SSE2AVX. */
1331 if (!t
->opcode_modifier
.sse2avx
|| sse2avx
)
1333 match
|= (CPU_FLAGS_ARCH_MATCH
1334 | CPU_FLAGS_AVX_MATCH
);
1336 if (!x
.bitfield
.cpuaes
|| cpu
.bitfield
.cpuaes
)
1337 match
|= CPU_FLAGS_AES_MATCH
;
1339 if (!x
.bitfield
.cpupclmul
1340 || cpu
.bitfield
.cpupclmul
)
1341 match
|= CPU_FLAGS_PCLMUL_MATCH
;
1345 match
|= CPU_FLAGS_ARCH_MATCH
;
1348 match
|= CPU_FLAGS_32BIT_MATCH
;
1354 static INLINE i386_operand_type
1355 operand_type_and (i386_operand_type x
, i386_operand_type y
)
1357 switch (ARRAY_SIZE (x
.array
))
1360 x
.array
[2] &= y
.array
[2];
1362 x
.array
[1] &= y
.array
[1];
1364 x
.array
[0] &= y
.array
[0];
1372 static INLINE i386_operand_type
1373 operand_type_or (i386_operand_type x
, i386_operand_type y
)
1375 switch (ARRAY_SIZE (x
.array
))
1378 x
.array
[2] |= y
.array
[2];
1380 x
.array
[1] |= y
.array
[1];
1382 x
.array
[0] |= y
.array
[0];
1390 static INLINE i386_operand_type
1391 operand_type_xor (i386_operand_type x
, i386_operand_type y
)
1393 switch (ARRAY_SIZE (x
.array
))
1396 x
.array
[2] ^= y
.array
[2];
1398 x
.array
[1] ^= y
.array
[1];
1400 x
.array
[0] ^= y
.array
[0];
1408 static const i386_operand_type acc32
= OPERAND_TYPE_ACC32
;
1409 static const i386_operand_type acc64
= OPERAND_TYPE_ACC64
;
1410 static const i386_operand_type control
= OPERAND_TYPE_CONTROL
;
1411 static const i386_operand_type inoutportreg
1412 = OPERAND_TYPE_INOUTPORTREG
;
1413 static const i386_operand_type reg16_inoutportreg
1414 = OPERAND_TYPE_REG16_INOUTPORTREG
;
1415 static const i386_operand_type disp16
= OPERAND_TYPE_DISP16
;
1416 static const i386_operand_type disp32
= OPERAND_TYPE_DISP32
;
1417 static const i386_operand_type disp32s
= OPERAND_TYPE_DISP32S
;
1418 static const i386_operand_type disp16_32
= OPERAND_TYPE_DISP16_32
;
1419 static const i386_operand_type anydisp
1420 = OPERAND_TYPE_ANYDISP
;
1421 static const i386_operand_type regxmm
= OPERAND_TYPE_REGXMM
;
1422 static const i386_operand_type regymm
= OPERAND_TYPE_REGYMM
;
1423 static const i386_operand_type imm8
= OPERAND_TYPE_IMM8
;
1424 static const i386_operand_type imm8s
= OPERAND_TYPE_IMM8S
;
1425 static const i386_operand_type imm16
= OPERAND_TYPE_IMM16
;
1426 static const i386_operand_type imm32
= OPERAND_TYPE_IMM32
;
1427 static const i386_operand_type imm32s
= OPERAND_TYPE_IMM32S
;
1428 static const i386_operand_type imm64
= OPERAND_TYPE_IMM64
;
1429 static const i386_operand_type imm16_32
= OPERAND_TYPE_IMM16_32
;
1430 static const i386_operand_type imm16_32s
= OPERAND_TYPE_IMM16_32S
;
1431 static const i386_operand_type imm16_32_32s
= OPERAND_TYPE_IMM16_32_32S
;
1442 operand_type_check (i386_operand_type t
, enum operand_type c
)
1447 return (t
.bitfield
.reg8
1450 || t
.bitfield
.reg64
);
1453 return (t
.bitfield
.imm8
1457 || t
.bitfield
.imm32s
1458 || t
.bitfield
.imm64
);
1461 return (t
.bitfield
.disp8
1462 || t
.bitfield
.disp16
1463 || t
.bitfield
.disp32
1464 || t
.bitfield
.disp32s
1465 || t
.bitfield
.disp64
);
1468 return (t
.bitfield
.disp8
1469 || t
.bitfield
.disp16
1470 || t
.bitfield
.disp32
1471 || t
.bitfield
.disp32s
1472 || t
.bitfield
.disp64
1473 || t
.bitfield
.baseindex
);
1482 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1483 operand J for instruction template T. */
1486 match_reg_size (const insn_template
*t
, unsigned int j
)
1488 return !((i
.types
[j
].bitfield
.byte
1489 && !t
->operand_types
[j
].bitfield
.byte
)
1490 || (i
.types
[j
].bitfield
.word
1491 && !t
->operand_types
[j
].bitfield
.word
)
1492 || (i
.types
[j
].bitfield
.dword
1493 && !t
->operand_types
[j
].bitfield
.dword
)
1494 || (i
.types
[j
].bitfield
.qword
1495 && !t
->operand_types
[j
].bitfield
.qword
));
1498 /* Return 1 if there is no conflict in any size on operand J for
1499 instruction template T. */
1502 match_mem_size (const insn_template
*t
, unsigned int j
)
1504 return (match_reg_size (t
, j
)
1505 && !((i
.types
[j
].bitfield
.unspecified
1506 && !t
->operand_types
[j
].bitfield
.unspecified
)
1507 || (i
.types
[j
].bitfield
.fword
1508 && !t
->operand_types
[j
].bitfield
.fword
)
1509 || (i
.types
[j
].bitfield
.tbyte
1510 && !t
->operand_types
[j
].bitfield
.tbyte
)
1511 || (i
.types
[j
].bitfield
.xmmword
1512 && !t
->operand_types
[j
].bitfield
.xmmword
)
1513 || (i
.types
[j
].bitfield
.ymmword
1514 && !t
->operand_types
[j
].bitfield
.ymmword
)));
1517 /* Return 1 if there is no size conflict on any operands for
1518 instruction template T. */
1521 operand_size_match (const insn_template
*t
)
1526 /* Don't check jump instructions. */
1527 if (t
->opcode_modifier
.jump
1528 || t
->opcode_modifier
.jumpbyte
1529 || t
->opcode_modifier
.jumpdword
1530 || t
->opcode_modifier
.jumpintersegment
)
1533 /* Check memory and accumulator operand size. */
1534 for (j
= 0; j
< i
.operands
; j
++)
1536 if (t
->operand_types
[j
].bitfield
.anysize
)
1539 if (t
->operand_types
[j
].bitfield
.acc
&& !match_reg_size (t
, j
))
1545 if (i
.types
[j
].bitfield
.mem
&& !match_mem_size (t
, j
))
1553 || (!t
->opcode_modifier
.d
&& !t
->opcode_modifier
.floatd
))
1556 /* Check reverse. */
1557 gas_assert (i
.operands
== 2);
1560 for (j
= 0; j
< 2; j
++)
1562 if (t
->operand_types
[j
].bitfield
.acc
1563 && !match_reg_size (t
, j
? 0 : 1))
1569 if (i
.types
[j
].bitfield
.mem
1570 && !match_mem_size (t
, j
? 0 : 1))
1581 operand_type_match (i386_operand_type overlap
,
1582 i386_operand_type given
)
1584 i386_operand_type temp
= overlap
;
1586 temp
.bitfield
.jumpabsolute
= 0;
1587 temp
.bitfield
.unspecified
= 0;
1588 temp
.bitfield
.byte
= 0;
1589 temp
.bitfield
.word
= 0;
1590 temp
.bitfield
.dword
= 0;
1591 temp
.bitfield
.fword
= 0;
1592 temp
.bitfield
.qword
= 0;
1593 temp
.bitfield
.tbyte
= 0;
1594 temp
.bitfield
.xmmword
= 0;
1595 temp
.bitfield
.ymmword
= 0;
1596 if (operand_type_all_zero (&temp
))
1599 return (given
.bitfield
.baseindex
== overlap
.bitfield
.baseindex
1600 && given
.bitfield
.jumpabsolute
== overlap
.bitfield
.jumpabsolute
);
1603 /* If given types g0 and g1 are registers they must be of the same type
1604 unless the expected operand type register overlap is null.
1605 Note that Acc in a template matches every size of reg. */
1608 operand_type_register_match (i386_operand_type m0
,
1609 i386_operand_type g0
,
1610 i386_operand_type t0
,
1611 i386_operand_type m1
,
1612 i386_operand_type g1
,
1613 i386_operand_type t1
)
1615 if (!operand_type_check (g0
, reg
))
1618 if (!operand_type_check (g1
, reg
))
1621 if (g0
.bitfield
.reg8
== g1
.bitfield
.reg8
1622 && g0
.bitfield
.reg16
== g1
.bitfield
.reg16
1623 && g0
.bitfield
.reg32
== g1
.bitfield
.reg32
1624 && g0
.bitfield
.reg64
== g1
.bitfield
.reg64
)
1627 if (m0
.bitfield
.acc
)
1629 t0
.bitfield
.reg8
= 1;
1630 t0
.bitfield
.reg16
= 1;
1631 t0
.bitfield
.reg32
= 1;
1632 t0
.bitfield
.reg64
= 1;
1635 if (m1
.bitfield
.acc
)
1637 t1
.bitfield
.reg8
= 1;
1638 t1
.bitfield
.reg16
= 1;
1639 t1
.bitfield
.reg32
= 1;
1640 t1
.bitfield
.reg64
= 1;
1643 return (!(t0
.bitfield
.reg8
& t1
.bitfield
.reg8
)
1644 && !(t0
.bitfield
.reg16
& t1
.bitfield
.reg16
)
1645 && !(t0
.bitfield
.reg32
& t1
.bitfield
.reg32
)
1646 && !(t0
.bitfield
.reg64
& t1
.bitfield
.reg64
));
1649 static INLINE
unsigned int
1650 mode_from_disp_size (i386_operand_type t
)
1652 if (t
.bitfield
.disp8
)
1654 else if (t
.bitfield
.disp16
1655 || t
.bitfield
.disp32
1656 || t
.bitfield
.disp32s
)
1663 fits_in_signed_byte (offsetT num
)
1665 return (num
>= -128) && (num
<= 127);
1669 fits_in_unsigned_byte (offsetT num
)
1671 return (num
& 0xff) == num
;
1675 fits_in_unsigned_word (offsetT num
)
1677 return (num
& 0xffff) == num
;
1681 fits_in_signed_word (offsetT num
)
1683 return (-32768 <= num
) && (num
<= 32767);
1687 fits_in_signed_long (offsetT num ATTRIBUTE_UNUSED
)
1692 return (!(((offsetT
) -1 << 31) & num
)
1693 || (((offsetT
) -1 << 31) & num
) == ((offsetT
) -1 << 31));
1695 } /* fits_in_signed_long() */
1698 fits_in_unsigned_long (offsetT num ATTRIBUTE_UNUSED
)
1703 return (num
& (((offsetT
) 2 << 31) - 1)) == num
;
1705 } /* fits_in_unsigned_long() */
1707 static i386_operand_type
1708 smallest_imm_type (offsetT num
)
1710 i386_operand_type t
;
1712 operand_type_set (&t
, 0);
1713 t
.bitfield
.imm64
= 1;
1715 if (cpu_arch_tune
!= PROCESSOR_I486
&& num
== 1)
1717 /* This code is disabled on the 486 because all the Imm1 forms
1718 in the opcode table are slower on the i486. They're the
1719 versions with the implicitly specified single-position
1720 displacement, which has another syntax if you really want to
1722 t
.bitfield
.imm1
= 1;
1723 t
.bitfield
.imm8
= 1;
1724 t
.bitfield
.imm8s
= 1;
1725 t
.bitfield
.imm16
= 1;
1726 t
.bitfield
.imm32
= 1;
1727 t
.bitfield
.imm32s
= 1;
1729 else if (fits_in_signed_byte (num
))
1731 t
.bitfield
.imm8
= 1;
1732 t
.bitfield
.imm8s
= 1;
1733 t
.bitfield
.imm16
= 1;
1734 t
.bitfield
.imm32
= 1;
1735 t
.bitfield
.imm32s
= 1;
1737 else if (fits_in_unsigned_byte (num
))
1739 t
.bitfield
.imm8
= 1;
1740 t
.bitfield
.imm16
= 1;
1741 t
.bitfield
.imm32
= 1;
1742 t
.bitfield
.imm32s
= 1;
1744 else if (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
1746 t
.bitfield
.imm16
= 1;
1747 t
.bitfield
.imm32
= 1;
1748 t
.bitfield
.imm32s
= 1;
1750 else if (fits_in_signed_long (num
))
1752 t
.bitfield
.imm32
= 1;
1753 t
.bitfield
.imm32s
= 1;
1755 else if (fits_in_unsigned_long (num
))
1756 t
.bitfield
.imm32
= 1;
1762 offset_in_range (offsetT val
, int size
)
1768 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
1769 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
1770 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
1772 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
1778 /* If BFD64, sign extend val for 32bit address mode. */
1779 if (flag_code
!= CODE_64BIT
1780 || i
.prefix
[ADDR_PREFIX
])
1781 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
1782 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
1785 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
1787 char buf1
[40], buf2
[40];
1789 sprint_value (buf1
, val
);
1790 sprint_value (buf2
, val
& mask
);
1791 as_warn (_("%s shortened to %s"), buf1
, buf2
);
1805 a. PREFIX_EXIST if attempting to add a prefix where one from the
1806 same class already exists.
1807 b. PREFIX_LOCK if lock prefix is added.
1808 c. PREFIX_REP if rep/repne prefix is added.
1809 d. PREFIX_OTHER if other prefix is added.
1812 static enum PREFIX_GROUP
1813 add_prefix (unsigned int prefix
)
1815 enum PREFIX_GROUP ret
= PREFIX_OTHER
;
1818 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
1819 && flag_code
== CODE_64BIT
)
1821 if ((i
.prefix
[REX_PREFIX
] & prefix
& REX_W
)
1822 || ((i
.prefix
[REX_PREFIX
] & (REX_R
| REX_X
| REX_B
))
1823 && (prefix
& (REX_R
| REX_X
| REX_B
))))
1834 case CS_PREFIX_OPCODE
:
1835 case DS_PREFIX_OPCODE
:
1836 case ES_PREFIX_OPCODE
:
1837 case FS_PREFIX_OPCODE
:
1838 case GS_PREFIX_OPCODE
:
1839 case SS_PREFIX_OPCODE
:
1843 case REPNE_PREFIX_OPCODE
:
1844 case REPE_PREFIX_OPCODE
:
1849 case LOCK_PREFIX_OPCODE
:
1858 case ADDR_PREFIX_OPCODE
:
1862 case DATA_PREFIX_OPCODE
:
1866 if (i
.prefix
[q
] != 0)
1874 i
.prefix
[q
] |= prefix
;
1877 as_bad (_("same type of prefix used twice"));
1883 set_code_flag (int value
)
1885 flag_code
= (enum flag_code
) value
;
1886 if (flag_code
== CODE_64BIT
)
1888 cpu_arch_flags
.bitfield
.cpu64
= 1;
1889 cpu_arch_flags
.bitfield
.cpuno64
= 0;
1893 cpu_arch_flags
.bitfield
.cpu64
= 0;
1894 cpu_arch_flags
.bitfield
.cpuno64
= 1;
1896 if (value
== CODE_64BIT
&& !cpu_arch_flags
.bitfield
.cpulm
)
1898 as_bad (_("64bit mode not supported on this CPU."));
1900 if (value
== CODE_32BIT
&& !cpu_arch_flags
.bitfield
.cpui386
)
1902 as_bad (_("32bit mode not supported on this CPU."));
1904 stackop_size
= '\0';
1908 set_16bit_gcc_code_flag (int new_code_flag
)
1910 flag_code
= (enum flag_code
) new_code_flag
;
1911 if (flag_code
!= CODE_16BIT
)
1913 cpu_arch_flags
.bitfield
.cpu64
= 0;
1914 cpu_arch_flags
.bitfield
.cpuno64
= 1;
1915 stackop_size
= LONG_MNEM_SUFFIX
;
1919 set_intel_syntax (int syntax_flag
)
1921 /* Find out if register prefixing is specified. */
1922 int ask_naked_reg
= 0;
1925 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
1927 char *string
= input_line_pointer
;
1928 int e
= get_symbol_end ();
1930 if (strcmp (string
, "prefix") == 0)
1932 else if (strcmp (string
, "noprefix") == 0)
1935 as_bad (_("bad argument to syntax directive."));
1936 *input_line_pointer
= e
;
1938 demand_empty_rest_of_line ();
1940 intel_syntax
= syntax_flag
;
1942 if (ask_naked_reg
== 0)
1943 allow_naked_reg
= (intel_syntax
1944 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
1946 allow_naked_reg
= (ask_naked_reg
< 0);
1948 expr_set_rank (O_full_ptr
, syntax_flag
? 10 : 0);
1950 identifier_chars
['%'] = intel_syntax
&& allow_naked_reg
? '%' : 0;
1951 identifier_chars
['$'] = intel_syntax
? '$' : 0;
1952 register_prefix
= allow_naked_reg
? "" : "%";
1956 set_intel_mnemonic (int mnemonic_flag
)
1958 intel_mnemonic
= mnemonic_flag
;
1962 set_allow_index_reg (int flag
)
1964 allow_index_reg
= flag
;
1968 set_sse_check (int dummy ATTRIBUTE_UNUSED
)
1972 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
1974 char *string
= input_line_pointer
;
1975 int e
= get_symbol_end ();
1977 if (strcmp (string
, "none") == 0)
1978 sse_check
= sse_check_none
;
1979 else if (strcmp (string
, "warning") == 0)
1980 sse_check
= sse_check_warning
;
1981 else if (strcmp (string
, "error") == 0)
1982 sse_check
= sse_check_error
;
1984 as_bad (_("bad argument to sse_check directive."));
1985 *input_line_pointer
= e
;
1988 as_bad (_("missing argument for sse_check directive"));
1990 demand_empty_rest_of_line ();
1994 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED
,
1995 i386_cpu_flags new_flag ATTRIBUTE_UNUSED
)
1997 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1998 static const char *arch
;
2000 /* Intel LIOM is only supported on ELF. */
2006 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2007 use default_arch. */
2008 arch
= cpu_arch_name
;
2010 arch
= default_arch
;
2013 /* If we are targeting Intel L1OM, we must enable it. */
2014 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_L1OM
2015 || new_flag
.bitfield
.cpul1om
)
2018 as_bad (_("`%s' is not supported on `%s'"), name
, arch
);
2023 set_cpu_arch (int dummy ATTRIBUTE_UNUSED
)
2027 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2029 char *string
= input_line_pointer
;
2030 int e
= get_symbol_end ();
2032 i386_cpu_flags flags
;
2034 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
2036 if (strcmp (string
, cpu_arch
[j
].name
) == 0)
2038 check_cpu_arch_compatible (string
, cpu_arch
[j
].flags
);
2042 cpu_arch_name
= cpu_arch
[j
].name
;
2043 cpu_sub_arch_name
= NULL
;
2044 cpu_arch_flags
= cpu_arch
[j
].flags
;
2045 if (flag_code
== CODE_64BIT
)
2047 cpu_arch_flags
.bitfield
.cpu64
= 1;
2048 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2052 cpu_arch_flags
.bitfield
.cpu64
= 0;
2053 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2055 cpu_arch_isa
= cpu_arch
[j
].type
;
2056 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
2057 if (!cpu_arch_tune_set
)
2059 cpu_arch_tune
= cpu_arch_isa
;
2060 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
2065 if (strncmp (string
+ 1, "no", 2))
2066 flags
= cpu_flags_or (cpu_arch_flags
,
2069 flags
= cpu_flags_and_not (cpu_arch_flags
,
2071 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2073 if (cpu_sub_arch_name
)
2075 char *name
= cpu_sub_arch_name
;
2076 cpu_sub_arch_name
= concat (name
,
2078 (const char *) NULL
);
2082 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
2083 cpu_arch_flags
= flags
;
2085 *input_line_pointer
= e
;
2086 demand_empty_rest_of_line ();
2090 if (j
>= ARRAY_SIZE (cpu_arch
))
2091 as_bad (_("no such architecture: `%s'"), string
);
2093 *input_line_pointer
= e
;
2096 as_bad (_("missing cpu architecture"));
2098 no_cond_jump_promotion
= 0;
2099 if (*input_line_pointer
== ','
2100 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
2102 char *string
= ++input_line_pointer
;
2103 int e
= get_symbol_end ();
2105 if (strcmp (string
, "nojumps") == 0)
2106 no_cond_jump_promotion
= 1;
2107 else if (strcmp (string
, "jumps") == 0)
2110 as_bad (_("no such architecture modifier: `%s'"), string
);
2112 *input_line_pointer
= e
;
2115 demand_empty_rest_of_line ();
2118 enum bfd_architecture
2121 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2123 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2124 || flag_code
!= CODE_64BIT
)
2125 as_fatal (_("Intel L1OM is 64bit ELF only"));
2126 return bfd_arch_l1om
;
2129 return bfd_arch_i386
;
2135 if (!strcmp (default_arch
, "x86_64"))
2137 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2139 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
2140 as_fatal (_("Intel L1OM is 64bit ELF only"));
2141 return bfd_mach_l1om
;
2144 return bfd_mach_x86_64
;
2146 else if (!strcmp (default_arch
, "i386"))
2147 return bfd_mach_i386_i386
;
2149 as_fatal (_("Unknown architecture"));
2155 const char *hash_err
;
2157 /* Initialize op_hash hash table. */
2158 op_hash
= hash_new ();
2161 const insn_template
*optab
;
2162 templates
*core_optab
;
2164 /* Setup for loop. */
2166 core_optab
= (templates
*) xmalloc (sizeof (templates
));
2167 core_optab
->start
= optab
;
2172 if (optab
->name
== NULL
2173 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
2175 /* different name --> ship out current template list;
2176 add to hash table; & begin anew. */
2177 core_optab
->end
= optab
;
2178 hash_err
= hash_insert (op_hash
,
2180 (void *) core_optab
);
2183 as_fatal (_("Internal Error: Can't hash %s: %s"),
2187 if (optab
->name
== NULL
)
2189 core_optab
= (templates
*) xmalloc (sizeof (templates
));
2190 core_optab
->start
= optab
;
2195 /* Initialize reg_hash hash table. */
2196 reg_hash
= hash_new ();
2198 const reg_entry
*regtab
;
2199 unsigned int regtab_size
= i386_regtab_size
;
2201 for (regtab
= i386_regtab
; regtab_size
--; regtab
++)
2203 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (void *) regtab
);
2205 as_fatal (_("Internal Error: Can't hash %s: %s"),
2211 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
2216 for (c
= 0; c
< 256; c
++)
2221 mnemonic_chars
[c
] = c
;
2222 register_chars
[c
] = c
;
2223 operand_chars
[c
] = c
;
2225 else if (ISLOWER (c
))
2227 mnemonic_chars
[c
] = c
;
2228 register_chars
[c
] = c
;
2229 operand_chars
[c
] = c
;
2231 else if (ISUPPER (c
))
2233 mnemonic_chars
[c
] = TOLOWER (c
);
2234 register_chars
[c
] = mnemonic_chars
[c
];
2235 operand_chars
[c
] = c
;
2238 if (ISALPHA (c
) || ISDIGIT (c
))
2239 identifier_chars
[c
] = c
;
2242 identifier_chars
[c
] = c
;
2243 operand_chars
[c
] = c
;
2248 identifier_chars
['@'] = '@';
2251 identifier_chars
['?'] = '?';
2252 operand_chars
['?'] = '?';
2254 digit_chars
['-'] = '-';
2255 mnemonic_chars
['_'] = '_';
2256 mnemonic_chars
['-'] = '-';
2257 mnemonic_chars
['.'] = '.';
2258 identifier_chars
['_'] = '_';
2259 identifier_chars
['.'] = '.';
2261 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
2262 operand_chars
[(unsigned char) *p
] = *p
;
2265 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2268 record_alignment (text_section
, 2);
2269 record_alignment (data_section
, 2);
2270 record_alignment (bss_section
, 2);
2274 if (flag_code
== CODE_64BIT
)
2276 x86_dwarf2_return_column
= 16;
2277 x86_cie_data_alignment
= -8;
2281 x86_dwarf2_return_column
= 8;
2282 x86_cie_data_alignment
= -4;
2287 i386_print_statistics (FILE *file
)
2289 hash_print_statistics (file
, "i386 opcode", op_hash
);
2290 hash_print_statistics (file
, "i386 register", reg_hash
);
2295 /* Debugging routines for md_assemble. */
2296 static void pte (insn_template
*);
2297 static void pt (i386_operand_type
);
2298 static void pe (expressionS
*);
2299 static void ps (symbolS
*);
2302 pi (char *line
, i386_insn
*x
)
2306 fprintf (stdout
, "%s: template ", line
);
2308 fprintf (stdout
, " address: base %s index %s scale %x\n",
2309 x
->base_reg
? x
->base_reg
->reg_name
: "none",
2310 x
->index_reg
? x
->index_reg
->reg_name
: "none",
2311 x
->log2_scale_factor
);
2312 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
2313 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
2314 fprintf (stdout
, " sib: base %x index %x scale %x\n",
2315 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
2316 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
2317 (x
->rex
& REX_W
) != 0,
2318 (x
->rex
& REX_R
) != 0,
2319 (x
->rex
& REX_X
) != 0,
2320 (x
->rex
& REX_B
) != 0);
2321 for (i
= 0; i
< x
->operands
; i
++)
2323 fprintf (stdout
, " #%d: ", i
+ 1);
2325 fprintf (stdout
, "\n");
2326 if (x
->types
[i
].bitfield
.reg8
2327 || x
->types
[i
].bitfield
.reg16
2328 || x
->types
[i
].bitfield
.reg32
2329 || x
->types
[i
].bitfield
.reg64
2330 || x
->types
[i
].bitfield
.regmmx
2331 || x
->types
[i
].bitfield
.regxmm
2332 || x
->types
[i
].bitfield
.regymm
2333 || x
->types
[i
].bitfield
.sreg2
2334 || x
->types
[i
].bitfield
.sreg3
2335 || x
->types
[i
].bitfield
.control
2336 || x
->types
[i
].bitfield
.debug
2337 || x
->types
[i
].bitfield
.test
)
2338 fprintf (stdout
, "%s\n", x
->op
[i
].regs
->reg_name
);
2339 if (operand_type_check (x
->types
[i
], imm
))
2341 if (operand_type_check (x
->types
[i
], disp
))
2342 pe (x
->op
[i
].disps
);
2347 pte (insn_template
*t
)
2350 fprintf (stdout
, " %d operands ", t
->operands
);
2351 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
2352 if (t
->extension_opcode
!= None
)
2353 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
2354 if (t
->opcode_modifier
.d
)
2355 fprintf (stdout
, "D");
2356 if (t
->opcode_modifier
.w
)
2357 fprintf (stdout
, "W");
2358 fprintf (stdout
, "\n");
2359 for (i
= 0; i
< t
->operands
; i
++)
2361 fprintf (stdout
, " #%d type ", i
+ 1);
2362 pt (t
->operand_types
[i
]);
2363 fprintf (stdout
, "\n");
2370 fprintf (stdout
, " operation %d\n", e
->X_op
);
2371 fprintf (stdout
, " add_number %ld (%lx)\n",
2372 (long) e
->X_add_number
, (long) e
->X_add_number
);
2373 if (e
->X_add_symbol
)
2375 fprintf (stdout
, " add_symbol ");
2376 ps (e
->X_add_symbol
);
2377 fprintf (stdout
, "\n");
2381 fprintf (stdout
, " op_symbol ");
2382 ps (e
->X_op_symbol
);
2383 fprintf (stdout
, "\n");
2390 fprintf (stdout
, "%s type %s%s",
2392 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
2393 segment_name (S_GET_SEGMENT (s
)));
2396 static struct type_name
2398 i386_operand_type mask
;
2401 const type_names
[] =
2403 { OPERAND_TYPE_REG8
, "r8" },
2404 { OPERAND_TYPE_REG16
, "r16" },
2405 { OPERAND_TYPE_REG32
, "r32" },
2406 { OPERAND_TYPE_REG64
, "r64" },
2407 { OPERAND_TYPE_IMM8
, "i8" },
2408 { OPERAND_TYPE_IMM8
, "i8s" },
2409 { OPERAND_TYPE_IMM16
, "i16" },
2410 { OPERAND_TYPE_IMM32
, "i32" },
2411 { OPERAND_TYPE_IMM32S
, "i32s" },
2412 { OPERAND_TYPE_IMM64
, "i64" },
2413 { OPERAND_TYPE_IMM1
, "i1" },
2414 { OPERAND_TYPE_BASEINDEX
, "BaseIndex" },
2415 { OPERAND_TYPE_DISP8
, "d8" },
2416 { OPERAND_TYPE_DISP16
, "d16" },
2417 { OPERAND_TYPE_DISP32
, "d32" },
2418 { OPERAND_TYPE_DISP32S
, "d32s" },
2419 { OPERAND_TYPE_DISP64
, "d64" },
2420 { OPERAND_TYPE_INOUTPORTREG
, "InOutPortReg" },
2421 { OPERAND_TYPE_SHIFTCOUNT
, "ShiftCount" },
2422 { OPERAND_TYPE_CONTROL
, "control reg" },
2423 { OPERAND_TYPE_TEST
, "test reg" },
2424 { OPERAND_TYPE_DEBUG
, "debug reg" },
2425 { OPERAND_TYPE_FLOATREG
, "FReg" },
2426 { OPERAND_TYPE_FLOATACC
, "FAcc" },
2427 { OPERAND_TYPE_SREG2
, "SReg2" },
2428 { OPERAND_TYPE_SREG3
, "SReg3" },
2429 { OPERAND_TYPE_ACC
, "Acc" },
2430 { OPERAND_TYPE_JUMPABSOLUTE
, "Jump Absolute" },
2431 { OPERAND_TYPE_REGMMX
, "rMMX" },
2432 { OPERAND_TYPE_REGXMM
, "rXMM" },
2433 { OPERAND_TYPE_REGYMM
, "rYMM" },
2434 { OPERAND_TYPE_ESSEG
, "es" },
2438 pt (i386_operand_type t
)
2441 i386_operand_type a
;
2443 for (j
= 0; j
< ARRAY_SIZE (type_names
); j
++)
2445 a
= operand_type_and (t
, type_names
[j
].mask
);
2446 if (!operand_type_all_zero (&a
))
2447 fprintf (stdout
, "%s, ", type_names
[j
].name
);
2452 #endif /* DEBUG386 */
2454 static bfd_reloc_code_real_type
2455 reloc (unsigned int size
,
2458 bfd_reloc_code_real_type other
)
2460 if (other
!= NO_RELOC
)
2462 reloc_howto_type
*rel
;
2467 case BFD_RELOC_X86_64_GOT32
:
2468 return BFD_RELOC_X86_64_GOT64
;
2470 case BFD_RELOC_X86_64_PLTOFF64
:
2471 return BFD_RELOC_X86_64_PLTOFF64
;
2473 case BFD_RELOC_X86_64_GOTPC32
:
2474 other
= BFD_RELOC_X86_64_GOTPC64
;
2476 case BFD_RELOC_X86_64_GOTPCREL
:
2477 other
= BFD_RELOC_X86_64_GOTPCREL64
;
2479 case BFD_RELOC_X86_64_TPOFF32
:
2480 other
= BFD_RELOC_X86_64_TPOFF64
;
2482 case BFD_RELOC_X86_64_DTPOFF32
:
2483 other
= BFD_RELOC_X86_64_DTPOFF64
;
2489 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
2490 if (size
== 4 && flag_code
!= CODE_64BIT
)
2493 rel
= bfd_reloc_type_lookup (stdoutput
, other
);
2495 as_bad (_("unknown relocation (%u)"), other
);
2496 else if (size
!= bfd_get_reloc_size (rel
))
2497 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
2498 bfd_get_reloc_size (rel
),
2500 else if (pcrel
&& !rel
->pc_relative
)
2501 as_bad (_("non-pc-relative relocation for pc-relative field"));
2502 else if ((rel
->complain_on_overflow
== complain_overflow_signed
2504 || (rel
->complain_on_overflow
== complain_overflow_unsigned
2506 as_bad (_("relocated field and relocation type differ in signedness"));
2515 as_bad (_("there are no unsigned pc-relative relocations"));
2518 case 1: return BFD_RELOC_8_PCREL
;
2519 case 2: return BFD_RELOC_16_PCREL
;
2520 case 4: return BFD_RELOC_32_PCREL
;
2521 case 8: return BFD_RELOC_64_PCREL
;
2523 as_bad (_("cannot do %u byte pc-relative relocation"), size
);
2530 case 4: return BFD_RELOC_X86_64_32S
;
2535 case 1: return BFD_RELOC_8
;
2536 case 2: return BFD_RELOC_16
;
2537 case 4: return BFD_RELOC_32
;
2538 case 8: return BFD_RELOC_64
;
2540 as_bad (_("cannot do %s %u byte relocation"),
2541 sign
> 0 ? "signed" : "unsigned", size
);
2547 /* Here we decide which fixups can be adjusted to make them relative to
2548 the beginning of the section instead of the symbol. Basically we need
2549 to make sure that the dynamic relocations are done correctly, so in
2550 some cases we force the original symbol to be used. */
2553 tc_i386_fix_adjustable (fixS
*fixP ATTRIBUTE_UNUSED
)
2555 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2559 /* Don't adjust pc-relative references to merge sections in 64-bit
2561 if (use_rela_relocations
2562 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
2566 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
2567 and changed later by validate_fix. */
2568 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
2569 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
2572 /* adjust_reloc_syms doesn't know about the GOT. */
2573 if (fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
2574 || fixP
->fx_r_type
== BFD_RELOC_386_PLT32
2575 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
2576 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
2577 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
2578 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
2579 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
2580 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
2581 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
2582 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
2583 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
2584 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTDESC
2585 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_DESC_CALL
2586 || fixP
->fx_r_type
== BFD_RELOC_X86_64_PLT32
2587 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
2588 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
2589 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
2590 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
2591 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
2592 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
2593 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
2594 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
2595 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
2596 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
2597 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPC32_TLSDESC
2598 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSDESC_CALL
2599 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
2600 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
2607 intel_float_operand (const char *mnemonic
)
2609 /* Note that the value returned is meaningful only for opcodes with (memory)
2610 operands, hence the code here is free to improperly handle opcodes that
2611 have no operands (for better performance and smaller code). */
2613 if (mnemonic
[0] != 'f')
2614 return 0; /* non-math */
2616 switch (mnemonic
[1])
2618 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
2619 the fs segment override prefix not currently handled because no
2620 call path can make opcodes without operands get here */
2622 return 2 /* integer op */;
2624 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
2625 return 3; /* fldcw/fldenv */
2628 if (mnemonic
[2] != 'o' /* fnop */)
2629 return 3; /* non-waiting control op */
2632 if (mnemonic
[2] == 's')
2633 return 3; /* frstor/frstpm */
2636 if (mnemonic
[2] == 'a')
2637 return 3; /* fsave */
2638 if (mnemonic
[2] == 't')
2640 switch (mnemonic
[3])
2642 case 'c': /* fstcw */
2643 case 'd': /* fstdw */
2644 case 'e': /* fstenv */
2645 case 's': /* fsts[gw] */
2651 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
2652 return 0; /* fxsave/fxrstor are not really math ops */
2659 /* Build the VEX prefix. */
2662 build_vex_prefix (const insn_template
*t
)
2664 unsigned int register_specifier
;
2665 unsigned int implied_prefix
;
2666 unsigned int vector_length
;
2668 /* Check register specifier. */
2669 if (i
.vex
.register_specifier
)
2671 register_specifier
= i
.vex
.register_specifier
->reg_num
;
2672 if ((i
.vex
.register_specifier
->reg_flags
& RegRex
))
2673 register_specifier
+= 8;
2674 register_specifier
= ~register_specifier
& 0xf;
2677 register_specifier
= 0xf;
2679 /* Use 2-byte VEX prefix by swappping destination and source
2682 && i
.operands
== i
.reg_operands
2683 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
2684 && i
.tm
.opcode_modifier
.s
2687 unsigned int xchg
= i
.operands
- 1;
2688 union i386_op temp_op
;
2689 i386_operand_type temp_type
;
2691 temp_type
= i
.types
[xchg
];
2692 i
.types
[xchg
] = i
.types
[0];
2693 i
.types
[0] = temp_type
;
2694 temp_op
= i
.op
[xchg
];
2695 i
.op
[xchg
] = i
.op
[0];
2698 gas_assert (i
.rm
.mode
== 3);
2702 i
.rm
.regmem
= i
.rm
.reg
;
2705 /* Use the next insn. */
2709 vector_length
= i
.tm
.opcode_modifier
.vex
== VEX256
? 1 : 0;
2711 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
2716 case DATA_PREFIX_OPCODE
:
2719 case REPE_PREFIX_OPCODE
:
2722 case REPNE_PREFIX_OPCODE
:
2729 /* Use 2-byte VEX prefix if possible. */
2730 if (i
.tm
.opcode_modifier
.vexopcode
== VEX0F
2731 && (i
.rex
& (REX_W
| REX_X
| REX_B
)) == 0)
2733 /* 2-byte VEX prefix. */
2737 i
.vex
.bytes
[0] = 0xc5;
2739 /* Check the REX.R bit. */
2740 r
= (i
.rex
& REX_R
) ? 0 : 1;
2741 i
.vex
.bytes
[1] = (r
<< 7
2742 | register_specifier
<< 3
2743 | vector_length
<< 2
2748 /* 3-byte VEX prefix. */
2752 i
.vex
.bytes
[0] = 0xc4;
2754 switch (i
.tm
.opcode_modifier
.vexopcode
)
2767 i
.vex
.bytes
[0] = 0x8f;
2771 i
.vex
.bytes
[0] = 0x8f;
2775 i
.vex
.bytes
[0] = 0x8f;
2781 /* The high 3 bits of the second VEX byte are 1's compliment
2782 of RXB bits from REX. */
2783 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
2785 /* Check the REX.W bit. */
2786 w
= (i
.rex
& REX_W
) ? 1 : 0;
2787 if (i
.tm
.opcode_modifier
.vexw
)
2792 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
2796 i
.vex
.bytes
[2] = (w
<< 7
2797 | register_specifier
<< 3
2798 | vector_length
<< 2
2804 process_immext (void)
2808 if (i
.tm
.cpu_flags
.bitfield
.cpusse3
&& i
.operands
> 0)
2810 /* SSE3 Instructions have the fixed operands with an opcode
2811 suffix which is coded in the same place as an 8-bit immediate
2812 field would be. Here we check those operands and remove them
2816 for (x
= 0; x
< i
.operands
; x
++)
2817 if (i
.op
[x
].regs
->reg_num
!= x
)
2818 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
2819 register_prefix
, i
.op
[x
].regs
->reg_name
, x
+ 1,
2825 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
2826 which is coded in the same place as an 8-bit immediate field
2827 would be. Here we fake an 8-bit immediate operand from the
2828 opcode suffix stored in tm.extension_opcode.
2830 AVX instructions also use this encoding, for some of
2831 3 argument instructions. */
2833 gas_assert (i
.imm_operands
== 0
2835 || (i
.tm
.opcode_modifier
.vex
2836 && i
.operands
<= 4)));
2838 exp
= &im_expressions
[i
.imm_operands
++];
2839 i
.op
[i
.operands
].imms
= exp
;
2840 i
.types
[i
.operands
] = imm8
;
2842 exp
->X_op
= O_constant
;
2843 exp
->X_add_number
= i
.tm
.extension_opcode
;
2844 i
.tm
.extension_opcode
= None
;
2847 /* This is the guts of the machine-dependent assembler. LINE points to a
2848 machine dependent instruction. This function is supposed to emit
2849 the frags/bytes it assembles to. */
2852 md_assemble (char *line
)
2855 char mnemonic
[MAX_MNEM_SIZE
];
2856 const insn_template
*t
;
2858 /* Initialize globals. */
2859 memset (&i
, '\0', sizeof (i
));
2860 for (j
= 0; j
< MAX_OPERANDS
; j
++)
2861 i
.reloc
[j
] = NO_RELOC
;
2862 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
2863 memset (im_expressions
, '\0', sizeof (im_expressions
));
2864 save_stack_p
= save_stack
;
2866 /* First parse an instruction mnemonic & call i386_operand for the operands.
2867 We assume that the scrubber has arranged it so that line[0] is the valid
2868 start of a (possibly prefixed) mnemonic. */
2870 line
= parse_insn (line
, mnemonic
);
2874 line
= parse_operands (line
, mnemonic
);
2879 /* Now we've parsed the mnemonic into a set of templates, and have the
2880 operands at hand. */
2882 /* All intel opcodes have reversed operands except for "bound" and
2883 "enter". We also don't reverse intersegment "jmp" and "call"
2884 instructions with 2 immediate operands so that the immediate segment
2885 precedes the offset, as it does when in AT&T mode. */
2888 && (strcmp (mnemonic
, "bound") != 0)
2889 && (strcmp (mnemonic
, "invlpga") != 0)
2890 && !(operand_type_check (i
.types
[0], imm
)
2891 && operand_type_check (i
.types
[1], imm
)))
2894 /* The order of the immediates should be reversed
2895 for 2 immediates extrq and insertq instructions */
2896 if (i
.imm_operands
== 2
2897 && (strcmp (mnemonic
, "extrq") == 0
2898 || strcmp (mnemonic
, "insertq") == 0))
2899 swap_2_operands (0, 1);
2904 /* Don't optimize displacement for movabs since it only takes 64bit
2907 && (flag_code
!= CODE_64BIT
2908 || strcmp (mnemonic
, "movabs") != 0))
2911 /* Next, we find a template that matches the given insn,
2912 making sure the overlap of the given operands types is consistent
2913 with the template operand types. */
2915 if (!(t
= match_template ()))
2918 if (sse_check
!= sse_check_none
2919 && !i
.tm
.opcode_modifier
.noavx
2920 && (i
.tm
.cpu_flags
.bitfield
.cpusse
2921 || i
.tm
.cpu_flags
.bitfield
.cpusse2
2922 || i
.tm
.cpu_flags
.bitfield
.cpusse3
2923 || i
.tm
.cpu_flags
.bitfield
.cpussse3
2924 || i
.tm
.cpu_flags
.bitfield
.cpusse4_1
2925 || i
.tm
.cpu_flags
.bitfield
.cpusse4_2
))
2927 (sse_check
== sse_check_warning
2929 : as_bad
) (_("SSE instruction `%s' is used"), i
.tm
.name
);
2932 /* Zap movzx and movsx suffix. The suffix has been set from
2933 "word ptr" or "byte ptr" on the source operand in Intel syntax
2934 or extracted from mnemonic in AT&T syntax. But we'll use
2935 the destination register to choose the suffix for encoding. */
2936 if ((i
.tm
.base_opcode
& ~9) == 0x0fb6)
2938 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
2939 there is no suffix, the default will be byte extension. */
2940 if (i
.reg_operands
!= 2
2943 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
2948 if (i
.tm
.opcode_modifier
.fwait
)
2949 if (!add_prefix (FWAIT_OPCODE
))
2952 /* Check for lock without a lockable instruction. Destination operand
2953 must be memory unless it is xchg (0x86). */
2954 if (i
.prefix
[LOCK_PREFIX
]
2955 && (!i
.tm
.opcode_modifier
.islockable
2956 || i
.mem_operands
== 0
2957 || (i
.tm
.base_opcode
!= 0x86
2958 && !operand_type_check (i
.types
[i
.operands
- 1], anymem
))))
2960 as_bad (_("expecting lockable instruction after `lock'"));
2964 /* Check string instruction segment overrides. */
2965 if (i
.tm
.opcode_modifier
.isstring
&& i
.mem_operands
!= 0)
2967 if (!check_string ())
2969 i
.disp_operands
= 0;
2972 if (!process_suffix ())
2975 /* Update operand types. */
2976 for (j
= 0; j
< i
.operands
; j
++)
2977 i
.types
[j
] = operand_type_and (i
.types
[j
], i
.tm
.operand_types
[j
]);
2979 /* Make still unresolved immediate matches conform to size of immediate
2980 given in i.suffix. */
2981 if (!finalize_imm ())
2984 if (i
.types
[0].bitfield
.imm1
)
2985 i
.imm_operands
= 0; /* kludge for shift insns. */
2987 /* We only need to check those implicit registers for instructions
2988 with 3 operands or less. */
2989 if (i
.operands
<= 3)
2990 for (j
= 0; j
< i
.operands
; j
++)
2991 if (i
.types
[j
].bitfield
.inoutportreg
2992 || i
.types
[j
].bitfield
.shiftcount
2993 || i
.types
[j
].bitfield
.acc
2994 || i
.types
[j
].bitfield
.floatacc
)
2997 /* ImmExt should be processed after SSE2AVX. */
2998 if (!i
.tm
.opcode_modifier
.sse2avx
2999 && i
.tm
.opcode_modifier
.immext
)
3002 /* For insns with operands there are more diddles to do to the opcode. */
3005 if (!process_operands ())
3008 else if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
3010 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
3011 as_warn (_("translating to `%sp'"), i
.tm
.name
);
3014 if (i
.tm
.opcode_modifier
.vex
)
3015 build_vex_prefix (t
);
3017 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
3018 instructions may define INT_OPCODE as well, so avoid this corner
3019 case for those instructions that use MODRM. */
3020 if (i
.tm
.base_opcode
== INT_OPCODE
3021 && i
.op
[0].imms
->X_add_number
== 3
3022 && !i
.tm
.opcode_modifier
.modrm
)
3024 i
.tm
.base_opcode
= INT3_OPCODE
;
3028 if ((i
.tm
.opcode_modifier
.jump
3029 || i
.tm
.opcode_modifier
.jumpbyte
3030 || i
.tm
.opcode_modifier
.jumpdword
)
3031 && i
.op
[0].disps
->X_op
== O_constant
)
3033 /* Convert "jmp constant" (and "call constant") to a jump (call) to
3034 the absolute address given by the constant. Since ix86 jumps and
3035 calls are pc relative, we need to generate a reloc. */
3036 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
3037 i
.op
[0].disps
->X_op
= O_symbol
;
3040 if (i
.tm
.opcode_modifier
.rex64
)
3043 /* For 8 bit registers we need an empty rex prefix. Also if the
3044 instruction already has a prefix, we need to convert old
3045 registers to new ones. */
3047 if ((i
.types
[0].bitfield
.reg8
3048 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
3049 || (i
.types
[1].bitfield
.reg8
3050 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
3051 || ((i
.types
[0].bitfield
.reg8
3052 || i
.types
[1].bitfield
.reg8
)
3057 i
.rex
|= REX_OPCODE
;
3058 for (x
= 0; x
< 2; x
++)
3060 /* Look for 8 bit operand that uses old registers. */
3061 if (i
.types
[x
].bitfield
.reg8
3062 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
3064 /* In case it is "hi" register, give up. */
3065 if (i
.op
[x
].regs
->reg_num
> 3)
3066 as_bad (_("can't encode register '%s%s' in an "
3067 "instruction requiring REX prefix."),
3068 register_prefix
, i
.op
[x
].regs
->reg_name
);
3070 /* Otherwise it is equivalent to the extended register.
3071 Since the encoding doesn't change this is merely
3072 cosmetic cleanup for debug output. */
3074 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
3080 add_prefix (REX_OPCODE
| i
.rex
);
3082 /* We are ready to output the insn. */
3087 parse_insn (char *line
, char *mnemonic
)
3090 char *token_start
= l
;
3093 const insn_template
*t
;
3096 /* Non-zero if we found a prefix only acceptable with string insns. */
3097 const char *expecting_string_instruction
= NULL
;
3102 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
3107 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
3109 as_bad (_("no such instruction: `%s'"), token_start
);
3114 if (!is_space_char (*l
)
3115 && *l
!= END_OF_INSN
3117 || (*l
!= PREFIX_SEPARATOR
3120 as_bad (_("invalid character %s in mnemonic"),
3121 output_invalid (*l
));
3124 if (token_start
== l
)
3126 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
3127 as_bad (_("expecting prefix; got nothing"));
3129 as_bad (_("expecting mnemonic; got nothing"));
3133 /* Look up instruction (or prefix) via hash table. */
3134 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
3136 if (*l
!= END_OF_INSN
3137 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
3138 && current_templates
3139 && current_templates
->start
->opcode_modifier
.isprefix
)
3141 if (!cpu_flags_check_cpu64 (current_templates
->start
->cpu_flags
))
3143 as_bad ((flag_code
!= CODE_64BIT
3144 ? _("`%s' is only supported in 64-bit mode")
3145 : _("`%s' is not supported in 64-bit mode")),
3146 current_templates
->start
->name
);
3149 /* If we are in 16-bit mode, do not allow addr16 or data16.
3150 Similarly, in 32-bit mode, do not allow addr32 or data32. */
3151 if ((current_templates
->start
->opcode_modifier
.size16
3152 || current_templates
->start
->opcode_modifier
.size32
)
3153 && flag_code
!= CODE_64BIT
3154 && (current_templates
->start
->opcode_modifier
.size32
3155 ^ (flag_code
== CODE_16BIT
)))
3157 as_bad (_("redundant %s prefix"),
3158 current_templates
->start
->name
);
3161 /* Add prefix, checking for repeated prefixes. */
3162 switch (add_prefix (current_templates
->start
->base_opcode
))
3167 expecting_string_instruction
= current_templates
->start
->name
;
3172 /* Skip past PREFIX_SEPARATOR and reset token_start. */
3179 if (!current_templates
)
3181 /* Check if we should swap operand in encoding. */
3182 if (mnem_p
- 2 == dot_p
&& dot_p
[1] == 's')
3188 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
3191 if (!current_templates
)
3194 /* See if we can get a match by trimming off a suffix. */
3197 case WORD_MNEM_SUFFIX
:
3198 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
3199 i
.suffix
= SHORT_MNEM_SUFFIX
;
3201 case BYTE_MNEM_SUFFIX
:
3202 case QWORD_MNEM_SUFFIX
:
3203 i
.suffix
= mnem_p
[-1];
3205 current_templates
= (const templates
*) hash_find (op_hash
,
3208 case SHORT_MNEM_SUFFIX
:
3209 case LONG_MNEM_SUFFIX
:
3212 i
.suffix
= mnem_p
[-1];
3214 current_templates
= (const templates
*) hash_find (op_hash
,
3223 if (intel_float_operand (mnemonic
) == 1)
3224 i
.suffix
= SHORT_MNEM_SUFFIX
;
3226 i
.suffix
= LONG_MNEM_SUFFIX
;
3228 current_templates
= (const templates
*) hash_find (op_hash
,
3233 if (!current_templates
)
3235 as_bad (_("no such instruction: `%s'"), token_start
);
3240 if (current_templates
->start
->opcode_modifier
.jump
3241 || current_templates
->start
->opcode_modifier
.jumpbyte
)
3243 /* Check for a branch hint. We allow ",pt" and ",pn" for
3244 predict taken and predict not taken respectively.
3245 I'm not sure that branch hints actually do anything on loop
3246 and jcxz insns (JumpByte) for current Pentium4 chips. They
3247 may work in the future and it doesn't hurt to accept them
3249 if (l
[0] == ',' && l
[1] == 'p')
3253 if (!add_prefix (DS_PREFIX_OPCODE
))
3257 else if (l
[2] == 'n')
3259 if (!add_prefix (CS_PREFIX_OPCODE
))
3265 /* Any other comma loses. */
3268 as_bad (_("invalid character %s in mnemonic"),
3269 output_invalid (*l
));
3273 /* Check if instruction is supported on specified architecture. */
3275 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
3277 supported
|= cpu_flags_match (t
);
3278 if (supported
== CPU_FLAGS_PERFECT_MATCH
)
3282 if (!(supported
& CPU_FLAGS_64BIT_MATCH
))
3284 as_bad (flag_code
== CODE_64BIT
3285 ? _("`%s' is not supported in 64-bit mode")
3286 : _("`%s' is only supported in 64-bit mode"),
3287 current_templates
->start
->name
);
3290 if (supported
!= CPU_FLAGS_PERFECT_MATCH
)
3292 as_bad (_("`%s' is not supported on `%s%s'"),
3293 current_templates
->start
->name
,
3294 cpu_arch_name
? cpu_arch_name
: default_arch
,
3295 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
3300 if (!cpu_arch_flags
.bitfield
.cpui386
3301 && (flag_code
!= CODE_16BIT
))
3303 as_warn (_("use .code16 to ensure correct addressing mode"));
3306 /* Check for rep/repne without a string instruction. */
3307 if (expecting_string_instruction
)
3309 static templates override
;
3311 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
3312 if (t
->opcode_modifier
.isstring
)
3314 if (t
>= current_templates
->end
)
3316 as_bad (_("expecting string instruction after `%s'"),
3317 expecting_string_instruction
);
3320 for (override
.start
= t
; t
< current_templates
->end
; ++t
)
3321 if (!t
->opcode_modifier
.isstring
)
3324 current_templates
= &override
;
3331 parse_operands (char *l
, const char *mnemonic
)
3335 /* 1 if operand is pending after ','. */
3336 unsigned int expecting_operand
= 0;
3338 /* Non-zero if operand parens not balanced. */
3339 unsigned int paren_not_balanced
;
3341 while (*l
!= END_OF_INSN
)
3343 /* Skip optional white space before operand. */
3344 if (is_space_char (*l
))
3346 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
)
3348 as_bad (_("invalid character %s before operand %d"),
3349 output_invalid (*l
),
3353 token_start
= l
; /* after white space */
3354 paren_not_balanced
= 0;
3355 while (paren_not_balanced
|| *l
!= ',')
3357 if (*l
== END_OF_INSN
)
3359 if (paren_not_balanced
)
3362 as_bad (_("unbalanced parenthesis in operand %d."),
3365 as_bad (_("unbalanced brackets in operand %d."),
3370 break; /* we are done */
3372 else if (!is_operand_char (*l
) && !is_space_char (*l
))
3374 as_bad (_("invalid character %s in operand %d"),
3375 output_invalid (*l
),
3382 ++paren_not_balanced
;
3384 --paren_not_balanced
;
3389 ++paren_not_balanced
;
3391 --paren_not_balanced
;
3395 if (l
!= token_start
)
3396 { /* Yes, we've read in another operand. */
3397 unsigned int operand_ok
;
3398 this_operand
= i
.operands
++;
3399 i
.types
[this_operand
].bitfield
.unspecified
= 1;
3400 if (i
.operands
> MAX_OPERANDS
)
3402 as_bad (_("spurious operands; (%d operands/instruction max)"),
3406 /* Now parse operand adding info to 'i' as we go along. */
3407 END_STRING_AND_SAVE (l
);
3411 i386_intel_operand (token_start
,
3412 intel_float_operand (mnemonic
));
3414 operand_ok
= i386_att_operand (token_start
);
3416 RESTORE_END_STRING (l
);
3422 if (expecting_operand
)
3424 expecting_operand_after_comma
:
3425 as_bad (_("expecting operand after ','; got nothing"));
3430 as_bad (_("expecting operand before ','; got nothing"));
3435 /* Now *l must be either ',' or END_OF_INSN. */
3438 if (*++l
== END_OF_INSN
)
3440 /* Just skip it, if it's \n complain. */
3441 goto expecting_operand_after_comma
;
3443 expecting_operand
= 1;
3450 swap_2_operands (int xchg1
, int xchg2
)
3452 union i386_op temp_op
;
3453 i386_operand_type temp_type
;
3454 enum bfd_reloc_code_real temp_reloc
;
3456 temp_type
= i
.types
[xchg2
];
3457 i
.types
[xchg2
] = i
.types
[xchg1
];
3458 i
.types
[xchg1
] = temp_type
;
3459 temp_op
= i
.op
[xchg2
];
3460 i
.op
[xchg2
] = i
.op
[xchg1
];
3461 i
.op
[xchg1
] = temp_op
;
3462 temp_reloc
= i
.reloc
[xchg2
];
3463 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
3464 i
.reloc
[xchg1
] = temp_reloc
;
3468 swap_operands (void)
3474 swap_2_operands (1, i
.operands
- 2);
3477 swap_2_operands (0, i
.operands
- 1);
3483 if (i
.mem_operands
== 2)
3485 const seg_entry
*temp_seg
;
3486 temp_seg
= i
.seg
[0];
3487 i
.seg
[0] = i
.seg
[1];
3488 i
.seg
[1] = temp_seg
;
3492 /* Try to ensure constant immediates are represented in the smallest
3497 char guess_suffix
= 0;
3501 guess_suffix
= i
.suffix
;
3502 else if (i
.reg_operands
)
3504 /* Figure out a suffix from the last register operand specified.
3505 We can't do this properly yet, ie. excluding InOutPortReg,
3506 but the following works for instructions with immediates.
3507 In any case, we can't set i.suffix yet. */
3508 for (op
= i
.operands
; --op
>= 0;)
3509 if (i
.types
[op
].bitfield
.reg8
)
3511 guess_suffix
= BYTE_MNEM_SUFFIX
;
3514 else if (i
.types
[op
].bitfield
.reg16
)
3516 guess_suffix
= WORD_MNEM_SUFFIX
;
3519 else if (i
.types
[op
].bitfield
.reg32
)
3521 guess_suffix
= LONG_MNEM_SUFFIX
;
3524 else if (i
.types
[op
].bitfield
.reg64
)
3526 guess_suffix
= QWORD_MNEM_SUFFIX
;
3530 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
3531 guess_suffix
= WORD_MNEM_SUFFIX
;
3533 for (op
= i
.operands
; --op
>= 0;)
3534 if (operand_type_check (i
.types
[op
], imm
))
3536 switch (i
.op
[op
].imms
->X_op
)
3539 /* If a suffix is given, this operand may be shortened. */
3540 switch (guess_suffix
)
3542 case LONG_MNEM_SUFFIX
:
3543 i
.types
[op
].bitfield
.imm32
= 1;
3544 i
.types
[op
].bitfield
.imm64
= 1;
3546 case WORD_MNEM_SUFFIX
:
3547 i
.types
[op
].bitfield
.imm16
= 1;
3548 i
.types
[op
].bitfield
.imm32
= 1;
3549 i
.types
[op
].bitfield
.imm32s
= 1;
3550 i
.types
[op
].bitfield
.imm64
= 1;
3552 case BYTE_MNEM_SUFFIX
:
3553 i
.types
[op
].bitfield
.imm8
= 1;
3554 i
.types
[op
].bitfield
.imm8s
= 1;
3555 i
.types
[op
].bitfield
.imm16
= 1;
3556 i
.types
[op
].bitfield
.imm32
= 1;
3557 i
.types
[op
].bitfield
.imm32s
= 1;
3558 i
.types
[op
].bitfield
.imm64
= 1;
3562 /* If this operand is at most 16 bits, convert it
3563 to a signed 16 bit number before trying to see
3564 whether it will fit in an even smaller size.
3565 This allows a 16-bit operand such as $0xffe0 to
3566 be recognised as within Imm8S range. */
3567 if ((i
.types
[op
].bitfield
.imm16
)
3568 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
3570 i
.op
[op
].imms
->X_add_number
=
3571 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
3573 if ((i
.types
[op
].bitfield
.imm32
)
3574 && ((i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1))
3577 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
3578 ^ ((offsetT
) 1 << 31))
3579 - ((offsetT
) 1 << 31));
3582 = operand_type_or (i
.types
[op
],
3583 smallest_imm_type (i
.op
[op
].imms
->X_add_number
));
3585 /* We must avoid matching of Imm32 templates when 64bit
3586 only immediate is available. */
3587 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
3588 i
.types
[op
].bitfield
.imm32
= 0;
3595 /* Symbols and expressions. */
3597 /* Convert symbolic operand to proper sizes for matching, but don't
3598 prevent matching a set of insns that only supports sizes other
3599 than those matching the insn suffix. */
3601 i386_operand_type mask
, allowed
;
3602 const insn_template
*t
;
3604 operand_type_set (&mask
, 0);
3605 operand_type_set (&allowed
, 0);
3607 for (t
= current_templates
->start
;
3608 t
< current_templates
->end
;
3610 allowed
= operand_type_or (allowed
,
3611 t
->operand_types
[op
]);
3612 switch (guess_suffix
)
3614 case QWORD_MNEM_SUFFIX
:
3615 mask
.bitfield
.imm64
= 1;
3616 mask
.bitfield
.imm32s
= 1;
3618 case LONG_MNEM_SUFFIX
:
3619 mask
.bitfield
.imm32
= 1;
3621 case WORD_MNEM_SUFFIX
:
3622 mask
.bitfield
.imm16
= 1;
3624 case BYTE_MNEM_SUFFIX
:
3625 mask
.bitfield
.imm8
= 1;
3630 allowed
= operand_type_and (mask
, allowed
);
3631 if (!operand_type_all_zero (&allowed
))
3632 i
.types
[op
] = operand_type_and (i
.types
[op
], mask
);
3639 /* Try to use the smallest displacement type too. */
3641 optimize_disp (void)
3645 for (op
= i
.operands
; --op
>= 0;)
3646 if (operand_type_check (i
.types
[op
], disp
))
3648 if (i
.op
[op
].disps
->X_op
== O_constant
)
3650 offsetT op_disp
= i
.op
[op
].disps
->X_add_number
;
3652 if (i
.types
[op
].bitfield
.disp16
3653 && (op_disp
& ~(offsetT
) 0xffff) == 0)
3655 /* If this operand is at most 16 bits, convert
3656 to a signed 16 bit number and don't use 64bit
3658 op_disp
= (((op_disp
& 0xffff) ^ 0x8000) - 0x8000);
3659 i
.types
[op
].bitfield
.disp64
= 0;
3661 if (i
.types
[op
].bitfield
.disp32
3662 && (op_disp
& ~(((offsetT
) 2 << 31) - 1)) == 0)
3664 /* If this operand is at most 32 bits, convert
3665 to a signed 32 bit number and don't use 64bit
3667 op_disp
&= (((offsetT
) 2 << 31) - 1);
3668 op_disp
= (op_disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
3669 i
.types
[op
].bitfield
.disp64
= 0;
3671 if (!op_disp
&& i
.types
[op
].bitfield
.baseindex
)
3673 i
.types
[op
].bitfield
.disp8
= 0;
3674 i
.types
[op
].bitfield
.disp16
= 0;
3675 i
.types
[op
].bitfield
.disp32
= 0;
3676 i
.types
[op
].bitfield
.disp32s
= 0;
3677 i
.types
[op
].bitfield
.disp64
= 0;
3681 else if (flag_code
== CODE_64BIT
)
3683 if (fits_in_signed_long (op_disp
))
3685 i
.types
[op
].bitfield
.disp64
= 0;
3686 i
.types
[op
].bitfield
.disp32s
= 1;
3688 if (i
.prefix
[ADDR_PREFIX
]
3689 && fits_in_unsigned_long (op_disp
))
3690 i
.types
[op
].bitfield
.disp32
= 1;
3692 if ((i
.types
[op
].bitfield
.disp32
3693 || i
.types
[op
].bitfield
.disp32s
3694 || i
.types
[op
].bitfield
.disp16
)
3695 && fits_in_signed_byte (op_disp
))
3696 i
.types
[op
].bitfield
.disp8
= 1;
3698 else if (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
3699 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
)
3701 fix_new_exp (frag_now
, frag_more (0) - frag_now
->fr_literal
, 0,
3702 i
.op
[op
].disps
, 0, i
.reloc
[op
]);
3703 i
.types
[op
].bitfield
.disp8
= 0;
3704 i
.types
[op
].bitfield
.disp16
= 0;
3705 i
.types
[op
].bitfield
.disp32
= 0;
3706 i
.types
[op
].bitfield
.disp32s
= 0;
3707 i
.types
[op
].bitfield
.disp64
= 0;
3710 /* We only support 64bit displacement on constants. */
3711 i
.types
[op
].bitfield
.disp64
= 0;
3715 static const insn_template
*
3716 match_template (void)
3718 /* Points to template once we've found it. */
3719 const insn_template
*t
;
3720 i386_operand_type overlap0
, overlap1
, overlap2
, overlap3
;
3721 i386_operand_type overlap4
;
3722 unsigned int found_reverse_match
;
3723 i386_opcode_modifier suffix_check
;
3724 i386_operand_type operand_types
[MAX_OPERANDS
];
3725 int addr_prefix_disp
;
3727 unsigned int found_cpu_match
;
3728 unsigned int check_register
;
3730 #if MAX_OPERANDS != 5
3731 # error "MAX_OPERANDS must be 5."
3734 found_reverse_match
= 0;
3735 addr_prefix_disp
= -1;
3737 memset (&suffix_check
, 0, sizeof (suffix_check
));
3738 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
3739 suffix_check
.no_bsuf
= 1;
3740 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
3741 suffix_check
.no_wsuf
= 1;
3742 else if (i
.suffix
== SHORT_MNEM_SUFFIX
)
3743 suffix_check
.no_ssuf
= 1;
3744 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
3745 suffix_check
.no_lsuf
= 1;
3746 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
3747 suffix_check
.no_qsuf
= 1;
3748 else if (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
)
3749 suffix_check
.no_ldsuf
= 1;
3751 for (t
= current_templates
->start
; t
< current_templates
->end
; t
++)
3753 addr_prefix_disp
= -1;
3755 /* Must have right number of operands. */
3756 if (i
.operands
!= t
->operands
)
3759 /* Check processor support. */
3760 found_cpu_match
= (cpu_flags_match (t
)
3761 == CPU_FLAGS_PERFECT_MATCH
);
3762 if (!found_cpu_match
)
3765 /* Check old gcc support. */
3766 if (!old_gcc
&& t
->opcode_modifier
.oldgcc
)
3769 /* Check AT&T mnemonic. */
3770 if (intel_mnemonic
&& t
->opcode_modifier
.attmnemonic
)
3773 /* Check AT&T syntax Intel syntax. */
3774 if ((intel_syntax
&& t
->opcode_modifier
.attsyntax
)
3775 || (!intel_syntax
&& t
->opcode_modifier
.intelsyntax
))
3778 /* Check the suffix, except for some instructions in intel mode. */
3779 if ((!intel_syntax
|| !t
->opcode_modifier
.ignoresize
)
3780 && ((t
->opcode_modifier
.no_bsuf
&& suffix_check
.no_bsuf
)
3781 || (t
->opcode_modifier
.no_wsuf
&& suffix_check
.no_wsuf
)
3782 || (t
->opcode_modifier
.no_lsuf
&& suffix_check
.no_lsuf
)
3783 || (t
->opcode_modifier
.no_ssuf
&& suffix_check
.no_ssuf
)
3784 || (t
->opcode_modifier
.no_qsuf
&& suffix_check
.no_qsuf
)
3785 || (t
->opcode_modifier
.no_ldsuf
&& suffix_check
.no_ldsuf
)))
3788 if (!operand_size_match (t
))
3791 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3792 operand_types
[j
] = t
->operand_types
[j
];
3794 /* In general, don't allow 64-bit operands in 32-bit mode. */
3795 if (i
.suffix
== QWORD_MNEM_SUFFIX
3796 && flag_code
!= CODE_64BIT
3798 ? (!t
->opcode_modifier
.ignoresize
3799 && !intel_float_operand (t
->name
))
3800 : intel_float_operand (t
->name
) != 2)
3801 && ((!operand_types
[0].bitfield
.regmmx
3802 && !operand_types
[0].bitfield
.regxmm
3803 && !operand_types
[0].bitfield
.regymm
)
3804 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
3805 && !!operand_types
[t
->operands
> 1].bitfield
.regxmm
3806 && !!operand_types
[t
->operands
> 1].bitfield
.regymm
))
3807 && (t
->base_opcode
!= 0x0fc7
3808 || t
->extension_opcode
!= 1 /* cmpxchg8b */))
3811 /* In general, don't allow 32-bit operands on pre-386. */
3812 else if (i
.suffix
== LONG_MNEM_SUFFIX
3813 && !cpu_arch_flags
.bitfield
.cpui386
3815 ? (!t
->opcode_modifier
.ignoresize
3816 && !intel_float_operand (t
->name
))
3817 : intel_float_operand (t
->name
) != 2)
3818 && ((!operand_types
[0].bitfield
.regmmx
3819 && !operand_types
[0].bitfield
.regxmm
)
3820 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
3821 && !!operand_types
[t
->operands
> 1].bitfield
.regxmm
)))
3824 /* Do not verify operands when there are none. */
3828 /* We've found a match; break out of loop. */
3832 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
3833 into Disp32/Disp16/Disp32 operand. */
3834 if (i
.prefix
[ADDR_PREFIX
] != 0)
3836 /* There should be only one Disp operand. */
3840 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3842 if (operand_types
[j
].bitfield
.disp16
)
3844 addr_prefix_disp
= j
;
3845 operand_types
[j
].bitfield
.disp32
= 1;
3846 operand_types
[j
].bitfield
.disp16
= 0;
3852 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3854 if (operand_types
[j
].bitfield
.disp32
)
3856 addr_prefix_disp
= j
;
3857 operand_types
[j
].bitfield
.disp32
= 0;
3858 operand_types
[j
].bitfield
.disp16
= 1;
3864 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3866 if (operand_types
[j
].bitfield
.disp64
)
3868 addr_prefix_disp
= j
;
3869 operand_types
[j
].bitfield
.disp64
= 0;
3870 operand_types
[j
].bitfield
.disp32
= 1;
3878 /* We check register size only if size of operands can be
3879 encoded the canonical way. */
3880 check_register
= t
->opcode_modifier
.w
;
3881 overlap0
= operand_type_and (i
.types
[0], operand_types
[0]);
3882 switch (t
->operands
)
3885 if (!operand_type_match (overlap0
, i
.types
[0]))
3889 /* xchg %eax, %eax is a special case. It is an aliase for nop
3890 only in 32bit mode and we can use opcode 0x90. In 64bit
3891 mode, we can't use 0x90 for xchg %eax, %eax since it should
3892 zero-extend %eax to %rax. */
3893 if (flag_code
== CODE_64BIT
3894 && t
->base_opcode
== 0x90
3895 && operand_type_equal (&i
.types
[0], &acc32
)
3896 && operand_type_equal (&i
.types
[1], &acc32
))
3900 /* If we swap operand in encoding, we either match
3901 the next one or reverse direction of operands. */
3902 if (t
->opcode_modifier
.s
)
3904 else if (t
->opcode_modifier
.d
)
3909 /* If we swap operand in encoding, we match the next one. */
3910 if (i
.swap_operand
&& t
->opcode_modifier
.s
)
3914 overlap1
= operand_type_and (i
.types
[1], operand_types
[1]);
3915 if (!operand_type_match (overlap0
, i
.types
[0])
3916 || !operand_type_match (overlap1
, i
.types
[1])
3918 && !operand_type_register_match (overlap0
, i
.types
[0],
3920 overlap1
, i
.types
[1],
3923 /* Check if other direction is valid ... */
3924 if (!t
->opcode_modifier
.d
&& !t
->opcode_modifier
.floatd
)
3928 /* Try reversing direction of operands. */
3929 overlap0
= operand_type_and (i
.types
[0], operand_types
[1]);
3930 overlap1
= operand_type_and (i
.types
[1], operand_types
[0]);
3931 if (!operand_type_match (overlap0
, i
.types
[0])
3932 || !operand_type_match (overlap1
, i
.types
[1])
3934 && !operand_type_register_match (overlap0
,
3941 /* Does not match either direction. */
3944 /* found_reverse_match holds which of D or FloatDR
3946 if (t
->opcode_modifier
.d
)
3947 found_reverse_match
= Opcode_D
;
3948 else if (t
->opcode_modifier
.floatd
)
3949 found_reverse_match
= Opcode_FloatD
;
3951 found_reverse_match
= 0;
3952 if (t
->opcode_modifier
.floatr
)
3953 found_reverse_match
|= Opcode_FloatR
;
3957 /* Found a forward 2 operand match here. */
3958 switch (t
->operands
)
3961 overlap4
= operand_type_and (i
.types
[4],
3964 overlap3
= operand_type_and (i
.types
[3],
3967 overlap2
= operand_type_and (i
.types
[2],
3972 switch (t
->operands
)
3975 if (!operand_type_match (overlap4
, i
.types
[4])
3976 || !operand_type_register_match (overlap3
,
3984 if (!operand_type_match (overlap3
, i
.types
[3])
3986 && !operand_type_register_match (overlap2
,
3994 /* Here we make use of the fact that there are no
3995 reverse match 3 operand instructions, and all 3
3996 operand instructions only need to be checked for
3997 register consistency between operands 2 and 3. */
3998 if (!operand_type_match (overlap2
, i
.types
[2])
4000 && !operand_type_register_match (overlap1
,
4010 /* Found either forward/reverse 2, 3 or 4 operand match here:
4011 slip through to break. */
4013 if (!found_cpu_match
)
4015 found_reverse_match
= 0;
4019 /* We've found a match; break out of loop. */
4023 if (t
== current_templates
->end
)
4025 /* We found no match. */
4027 as_bad (_("ambiguous operand size or operands invalid for `%s'"),
4028 current_templates
->start
->name
);
4030 as_bad (_("suffix or operands invalid for `%s'"),
4031 current_templates
->start
->name
);
4035 if (!quiet_warnings
)
4038 && (i
.types
[0].bitfield
.jumpabsolute
4039 != operand_types
[0].bitfield
.jumpabsolute
))
4041 as_warn (_("indirect %s without `*'"), t
->name
);
4044 if (t
->opcode_modifier
.isprefix
4045 && t
->opcode_modifier
.ignoresize
)
4047 /* Warn them that a data or address size prefix doesn't
4048 affect assembly of the next line of code. */
4049 as_warn (_("stand-alone `%s' prefix"), t
->name
);
4053 /* Copy the template we found. */
4056 if (addr_prefix_disp
!= -1)
4057 i
.tm
.operand_types
[addr_prefix_disp
]
4058 = operand_types
[addr_prefix_disp
];
4060 if (found_reverse_match
)
4062 /* If we found a reverse match we must alter the opcode
4063 direction bit. found_reverse_match holds bits to change
4064 (different for int & float insns). */
4066 i
.tm
.base_opcode
^= found_reverse_match
;
4068 i
.tm
.operand_types
[0] = operand_types
[1];
4069 i
.tm
.operand_types
[1] = operand_types
[0];
4078 int mem_op
= operand_type_check (i
.types
[0], anymem
) ? 0 : 1;
4079 if (i
.tm
.operand_types
[mem_op
].bitfield
.esseg
)
4081 if (i
.seg
[0] != NULL
&& i
.seg
[0] != &es
)
4083 as_bad (_("`%s' operand %d must use `%ses' segment"),
4089 /* There's only ever one segment override allowed per instruction.
4090 This instruction possibly has a legal segment override on the
4091 second operand, so copy the segment to where non-string
4092 instructions store it, allowing common code. */
4093 i
.seg
[0] = i
.seg
[1];
4095 else if (i
.tm
.operand_types
[mem_op
+ 1].bitfield
.esseg
)
4097 if (i
.seg
[1] != NULL
&& i
.seg
[1] != &es
)
4099 as_bad (_("`%s' operand %d must use `%ses' segment"),
4110 process_suffix (void)
4112 /* If matched instruction specifies an explicit instruction mnemonic
4114 if (i
.tm
.opcode_modifier
.size16
)
4115 i
.suffix
= WORD_MNEM_SUFFIX
;
4116 else if (i
.tm
.opcode_modifier
.size32
)
4117 i
.suffix
= LONG_MNEM_SUFFIX
;
4118 else if (i
.tm
.opcode_modifier
.size64
)
4119 i
.suffix
= QWORD_MNEM_SUFFIX
;
4120 else if (i
.reg_operands
)
4122 /* If there's no instruction mnemonic suffix we try to invent one
4123 based on register operands. */
4126 /* We take i.suffix from the last register operand specified,
4127 Destination register type is more significant than source
4128 register type. crc32 in SSE4.2 prefers source register
4130 if (i
.tm
.base_opcode
== 0xf20f38f1)
4132 if (i
.types
[0].bitfield
.reg16
)
4133 i
.suffix
= WORD_MNEM_SUFFIX
;
4134 else if (i
.types
[0].bitfield
.reg32
)
4135 i
.suffix
= LONG_MNEM_SUFFIX
;
4136 else if (i
.types
[0].bitfield
.reg64
)
4137 i
.suffix
= QWORD_MNEM_SUFFIX
;
4139 else if (i
.tm
.base_opcode
== 0xf20f38f0)
4141 if (i
.types
[0].bitfield
.reg8
)
4142 i
.suffix
= BYTE_MNEM_SUFFIX
;
4149 if (i
.tm
.base_opcode
== 0xf20f38f1
4150 || i
.tm
.base_opcode
== 0xf20f38f0)
4152 /* We have to know the operand size for crc32. */
4153 as_bad (_("ambiguous memory operand size for `%s`"),
4158 for (op
= i
.operands
; --op
>= 0;)
4159 if (!i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
4161 if (i
.types
[op
].bitfield
.reg8
)
4163 i
.suffix
= BYTE_MNEM_SUFFIX
;
4166 else if (i
.types
[op
].bitfield
.reg16
)
4168 i
.suffix
= WORD_MNEM_SUFFIX
;
4171 else if (i
.types
[op
].bitfield
.reg32
)
4173 i
.suffix
= LONG_MNEM_SUFFIX
;
4176 else if (i
.types
[op
].bitfield
.reg64
)
4178 i
.suffix
= QWORD_MNEM_SUFFIX
;
4184 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
4187 && i
.tm
.opcode_modifier
.ignoresize
4188 && i
.tm
.opcode_modifier
.no_bsuf
)
4190 else if (!check_byte_reg ())
4193 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
4196 && i
.tm
.opcode_modifier
.ignoresize
4197 && i
.tm
.opcode_modifier
.no_lsuf
)
4199 else if (!check_long_reg ())
4202 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
4205 && i
.tm
.opcode_modifier
.ignoresize
4206 && i
.tm
.opcode_modifier
.no_qsuf
)
4208 else if (!check_qword_reg ())
4211 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
4214 && i
.tm
.opcode_modifier
.ignoresize
4215 && i
.tm
.opcode_modifier
.no_wsuf
)
4217 else if (!check_word_reg ())
4220 else if (i
.suffix
== XMMWORD_MNEM_SUFFIX
4221 || i
.suffix
== YMMWORD_MNEM_SUFFIX
)
4223 /* Skip if the instruction has x/y suffix. match_template
4224 should check if it is a valid suffix. */
4226 else if (intel_syntax
&& i
.tm
.opcode_modifier
.ignoresize
)
4227 /* Do nothing if the instruction is going to ignore the prefix. */
4232 else if (i
.tm
.opcode_modifier
.defaultsize
4234 /* exclude fldenv/frstor/fsave/fstenv */
4235 && i
.tm
.opcode_modifier
.no_ssuf
)
4237 i
.suffix
= stackop_size
;
4239 else if (intel_syntax
4241 && (i
.tm
.operand_types
[0].bitfield
.jumpabsolute
4242 || i
.tm
.opcode_modifier
.jumpbyte
4243 || i
.tm
.opcode_modifier
.jumpintersegment
4244 || (i
.tm
.base_opcode
== 0x0f01 /* [ls][gi]dt */
4245 && i
.tm
.extension_opcode
<= 3)))
4250 if (!i
.tm
.opcode_modifier
.no_qsuf
)
4252 i
.suffix
= QWORD_MNEM_SUFFIX
;
4256 if (!i
.tm
.opcode_modifier
.no_lsuf
)
4257 i
.suffix
= LONG_MNEM_SUFFIX
;
4260 if (!i
.tm
.opcode_modifier
.no_wsuf
)
4261 i
.suffix
= WORD_MNEM_SUFFIX
;
4270 if (i
.tm
.opcode_modifier
.w
)
4272 as_bad (_("no instruction mnemonic suffix given and "
4273 "no register operands; can't size instruction"));
4279 unsigned int suffixes
;
4281 suffixes
= !i
.tm
.opcode_modifier
.no_bsuf
;
4282 if (!i
.tm
.opcode_modifier
.no_wsuf
)
4284 if (!i
.tm
.opcode_modifier
.no_lsuf
)
4286 if (!i
.tm
.opcode_modifier
.no_ldsuf
)
4288 if (!i
.tm
.opcode_modifier
.no_ssuf
)
4290 if (!i
.tm
.opcode_modifier
.no_qsuf
)
4293 /* There are more than suffix matches. */
4294 if (i
.tm
.opcode_modifier
.w
4295 || ((suffixes
& (suffixes
- 1))
4296 && !i
.tm
.opcode_modifier
.defaultsize
4297 && !i
.tm
.opcode_modifier
.ignoresize
))
4299 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
4305 /* Change the opcode based on the operand size given by i.suffix;
4306 We don't need to change things for byte insns. */
4309 && i
.suffix
!= BYTE_MNEM_SUFFIX
4310 && i
.suffix
!= XMMWORD_MNEM_SUFFIX
4311 && i
.suffix
!= YMMWORD_MNEM_SUFFIX
)
4313 /* It's not a byte, select word/dword operation. */
4314 if (i
.tm
.opcode_modifier
.w
)
4316 if (i
.tm
.opcode_modifier
.shortform
)
4317 i
.tm
.base_opcode
|= 8;
4319 i
.tm
.base_opcode
|= 1;
4322 /* Now select between word & dword operations via the operand
4323 size prefix, except for instructions that will ignore this
4325 if (i
.tm
.opcode_modifier
.addrprefixop0
)
4327 /* The address size override prefix changes the size of the
4329 if ((flag_code
== CODE_32BIT
4330 && i
.op
->regs
[0].reg_type
.bitfield
.reg16
)
4331 || (flag_code
!= CODE_32BIT
4332 && i
.op
->regs
[0].reg_type
.bitfield
.reg32
))
4333 if (!add_prefix (ADDR_PREFIX_OPCODE
))
4336 else if (i
.suffix
!= QWORD_MNEM_SUFFIX
4337 && i
.suffix
!= LONG_DOUBLE_MNEM_SUFFIX
4338 && !i
.tm
.opcode_modifier
.ignoresize
4339 && !i
.tm
.opcode_modifier
.floatmf
4340 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
4341 || (flag_code
== CODE_64BIT
4342 && i
.tm
.opcode_modifier
.jumpbyte
)))
4344 unsigned int prefix
= DATA_PREFIX_OPCODE
;
4346 if (i
.tm
.opcode_modifier
.jumpbyte
) /* jcxz, loop */
4347 prefix
= ADDR_PREFIX_OPCODE
;
4349 if (!add_prefix (prefix
))
4353 /* Set mode64 for an operand. */
4354 if (i
.suffix
== QWORD_MNEM_SUFFIX
4355 && flag_code
== CODE_64BIT
4356 && !i
.tm
.opcode_modifier
.norex64
)
4358 /* Special case for xchg %rax,%rax. It is NOP and doesn't
4359 need rex64. cmpxchg8b is also a special case. */
4360 if (! (i
.operands
== 2
4361 && i
.tm
.base_opcode
== 0x90
4362 && i
.tm
.extension_opcode
== None
4363 && operand_type_equal (&i
.types
[0], &acc64
)
4364 && operand_type_equal (&i
.types
[1], &acc64
))
4365 && ! (i
.operands
== 1
4366 && i
.tm
.base_opcode
== 0xfc7
4367 && i
.tm
.extension_opcode
== 1
4368 && !operand_type_check (i
.types
[0], reg
)
4369 && operand_type_check (i
.types
[0], anymem
)))
4373 /* Size floating point instruction. */
4374 if (i
.suffix
== LONG_MNEM_SUFFIX
)
4375 if (i
.tm
.opcode_modifier
.floatmf
)
4376 i
.tm
.base_opcode
^= 4;
4383 check_byte_reg (void)
4387 for (op
= i
.operands
; --op
>= 0;)
4389 /* If this is an eight bit register, it's OK. If it's the 16 or
4390 32 bit version of an eight bit register, we will just use the
4391 low portion, and that's OK too. */
4392 if (i
.types
[op
].bitfield
.reg8
)
4395 /* crc32 doesn't generate this warning. */
4396 if (i
.tm
.base_opcode
== 0xf20f38f0)
4399 if ((i
.types
[op
].bitfield
.reg16
4400 || i
.types
[op
].bitfield
.reg32
4401 || i
.types
[op
].bitfield
.reg64
)
4402 && i
.op
[op
].regs
->reg_num
< 4)
4404 /* Prohibit these changes in the 64bit mode, since the
4405 lowering is more complicated. */
4406 if (flag_code
== CODE_64BIT
4407 && !i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
4409 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4410 register_prefix
, i
.op
[op
].regs
->reg_name
,
4414 #if REGISTER_WARNINGS
4416 && !i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
4417 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4419 (i
.op
[op
].regs
+ (i
.types
[op
].bitfield
.reg16
4420 ? REGNAM_AL
- REGNAM_AX
4421 : REGNAM_AL
- REGNAM_EAX
))->reg_name
,
4423 i
.op
[op
].regs
->reg_name
,
4428 /* Any other register is bad. */
4429 if (i
.types
[op
].bitfield
.reg16
4430 || i
.types
[op
].bitfield
.reg32
4431 || i
.types
[op
].bitfield
.reg64
4432 || i
.types
[op
].bitfield
.regmmx
4433 || i
.types
[op
].bitfield
.regxmm
4434 || i
.types
[op
].bitfield
.regymm
4435 || i
.types
[op
].bitfield
.sreg2
4436 || i
.types
[op
].bitfield
.sreg3
4437 || i
.types
[op
].bitfield
.control
4438 || i
.types
[op
].bitfield
.debug
4439 || i
.types
[op
].bitfield
.test
4440 || i
.types
[op
].bitfield
.floatreg
4441 || i
.types
[op
].bitfield
.floatacc
)
4443 as_bad (_("`%s%s' not allowed with `%s%c'"),
4445 i
.op
[op
].regs
->reg_name
,
4455 check_long_reg (void)
4459 for (op
= i
.operands
; --op
>= 0;)
4460 /* Reject eight bit registers, except where the template requires
4461 them. (eg. movzb) */
4462 if (i
.types
[op
].bitfield
.reg8
4463 && (i
.tm
.operand_types
[op
].bitfield
.reg16
4464 || i
.tm
.operand_types
[op
].bitfield
.reg32
4465 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4467 as_bad (_("`%s%s' not allowed with `%s%c'"),
4469 i
.op
[op
].regs
->reg_name
,
4474 /* Warn if the e prefix on a general reg is missing. */
4475 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
4476 && i
.types
[op
].bitfield
.reg16
4477 && (i
.tm
.operand_types
[op
].bitfield
.reg32
4478 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4480 /* Prohibit these changes in the 64bit mode, since the
4481 lowering is more complicated. */
4482 if (flag_code
== CODE_64BIT
)
4484 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4485 register_prefix
, i
.op
[op
].regs
->reg_name
,
4489 #if REGISTER_WARNINGS
4491 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4493 (i
.op
[op
].regs
+ REGNAM_EAX
- REGNAM_AX
)->reg_name
,
4495 i
.op
[op
].regs
->reg_name
,
4499 /* Warn if the r prefix on a general reg is missing. */
4500 else if (i
.types
[op
].bitfield
.reg64
4501 && (i
.tm
.operand_types
[op
].bitfield
.reg32
4502 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4505 && i
.tm
.opcode_modifier
.toqword
4506 && !i
.types
[0].bitfield
.regxmm
)
4508 /* Convert to QWORD. We want REX byte. */
4509 i
.suffix
= QWORD_MNEM_SUFFIX
;
4513 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4514 register_prefix
, i
.op
[op
].regs
->reg_name
,
4523 check_qword_reg (void)
4527 for (op
= i
.operands
; --op
>= 0; )
4528 /* Reject eight bit registers, except where the template requires
4529 them. (eg. movzb) */
4530 if (i
.types
[op
].bitfield
.reg8
4531 && (i
.tm
.operand_types
[op
].bitfield
.reg16
4532 || i
.tm
.operand_types
[op
].bitfield
.reg32
4533 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4535 as_bad (_("`%s%s' not allowed with `%s%c'"),
4537 i
.op
[op
].regs
->reg_name
,
4542 /* Warn if the e prefix on a general reg is missing. */
4543 else if ((i
.types
[op
].bitfield
.reg16
4544 || i
.types
[op
].bitfield
.reg32
)
4545 && (i
.tm
.operand_types
[op
].bitfield
.reg32
4546 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4548 /* Prohibit these changes in the 64bit mode, since the
4549 lowering is more complicated. */
4551 && i
.tm
.opcode_modifier
.todword
4552 && !i
.types
[0].bitfield
.regxmm
)
4554 /* Convert to DWORD. We don't want REX byte. */
4555 i
.suffix
= LONG_MNEM_SUFFIX
;
4559 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4560 register_prefix
, i
.op
[op
].regs
->reg_name
,
4569 check_word_reg (void)
4572 for (op
= i
.operands
; --op
>= 0;)
4573 /* Reject eight bit registers, except where the template requires
4574 them. (eg. movzb) */
4575 if (i
.types
[op
].bitfield
.reg8
4576 && (i
.tm
.operand_types
[op
].bitfield
.reg16
4577 || i
.tm
.operand_types
[op
].bitfield
.reg32
4578 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4580 as_bad (_("`%s%s' not allowed with `%s%c'"),
4582 i
.op
[op
].regs
->reg_name
,
4587 /* Warn if the e prefix on a general reg is present. */
4588 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
4589 && i
.types
[op
].bitfield
.reg32
4590 && (i
.tm
.operand_types
[op
].bitfield
.reg16
4591 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4593 /* Prohibit these changes in the 64bit mode, since the
4594 lowering is more complicated. */
4595 if (flag_code
== CODE_64BIT
)
4597 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4598 register_prefix
, i
.op
[op
].regs
->reg_name
,
4603 #if REGISTER_WARNINGS
4604 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4606 (i
.op
[op
].regs
+ REGNAM_AX
- REGNAM_EAX
)->reg_name
,
4608 i
.op
[op
].regs
->reg_name
,
4616 update_imm (unsigned int j
)
4618 i386_operand_type overlap
= i
.types
[j
];
4619 if ((overlap
.bitfield
.imm8
4620 || overlap
.bitfield
.imm8s
4621 || overlap
.bitfield
.imm16
4622 || overlap
.bitfield
.imm32
4623 || overlap
.bitfield
.imm32s
4624 || overlap
.bitfield
.imm64
)
4625 && !operand_type_equal (&overlap
, &imm8
)
4626 && !operand_type_equal (&overlap
, &imm8s
)
4627 && !operand_type_equal (&overlap
, &imm16
)
4628 && !operand_type_equal (&overlap
, &imm32
)
4629 && !operand_type_equal (&overlap
, &imm32s
)
4630 && !operand_type_equal (&overlap
, &imm64
))
4634 i386_operand_type temp
;
4636 operand_type_set (&temp
, 0);
4637 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
4639 temp
.bitfield
.imm8
= overlap
.bitfield
.imm8
;
4640 temp
.bitfield
.imm8s
= overlap
.bitfield
.imm8s
;
4642 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
4643 temp
.bitfield
.imm16
= overlap
.bitfield
.imm16
;
4644 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
4646 temp
.bitfield
.imm64
= overlap
.bitfield
.imm64
;
4647 temp
.bitfield
.imm32s
= overlap
.bitfield
.imm32s
;
4650 temp
.bitfield
.imm32
= overlap
.bitfield
.imm32
;
4653 else if (operand_type_equal (&overlap
, &imm16_32_32s
)
4654 || operand_type_equal (&overlap
, &imm16_32
)
4655 || operand_type_equal (&overlap
, &imm16_32s
))
4657 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
4662 if (!operand_type_equal (&overlap
, &imm8
)
4663 && !operand_type_equal (&overlap
, &imm8s
)
4664 && !operand_type_equal (&overlap
, &imm16
)
4665 && !operand_type_equal (&overlap
, &imm32
)
4666 && !operand_type_equal (&overlap
, &imm32s
)
4667 && !operand_type_equal (&overlap
, &imm64
))
4669 as_bad (_("no instruction mnemonic suffix given; "
4670 "can't determine immediate size"));
4674 i
.types
[j
] = overlap
;
4684 /* Update the first 2 immediate operands. */
4685 n
= i
.operands
> 2 ? 2 : i
.operands
;
4688 for (j
= 0; j
< n
; j
++)
4689 if (update_imm (j
) == 0)
4692 /* The 3rd operand can't be immediate operand. */
4693 gas_assert (operand_type_check (i
.types
[2], imm
) == 0);
4700 bad_implicit_operand (int xmm
)
4702 const char *ireg
= xmm
? "xmm0" : "ymm0";
4705 as_bad (_("the last operand of `%s' must be `%s%s'"),
4706 i
.tm
.name
, register_prefix
, ireg
);
4708 as_bad (_("the first operand of `%s' must be `%s%s'"),
4709 i
.tm
.name
, register_prefix
, ireg
);
4714 process_operands (void)
4716 /* Default segment register this instruction will use for memory
4717 accesses. 0 means unknown. This is only for optimizing out
4718 unnecessary segment overrides. */
4719 const seg_entry
*default_seg
= 0;
4721 if (i
.tm
.opcode_modifier
.sse2avx
&& i
.tm
.opcode_modifier
.vexvvvv
)
4723 unsigned int dupl
= i
.operands
;
4724 unsigned int dest
= dupl
- 1;
4727 /* The destination must be an xmm register. */
4728 gas_assert (i
.reg_operands
4729 && MAX_OPERANDS
> dupl
4730 && operand_type_equal (&i
.types
[dest
], ®xmm
));
4732 if (i
.tm
.opcode_modifier
.firstxmm0
)
4734 /* The first operand is implicit and must be xmm0. */
4735 gas_assert (operand_type_equal (&i
.types
[0], ®xmm
));
4736 if (i
.op
[0].regs
->reg_num
!= 0)
4737 return bad_implicit_operand (1);
4739 if (i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
)
4741 /* Keep xmm0 for instructions with VEX prefix and 3
4747 /* We remove the first xmm0 and keep the number of
4748 operands unchanged, which in fact duplicates the
4750 for (j
= 1; j
< i
.operands
; j
++)
4752 i
.op
[j
- 1] = i
.op
[j
];
4753 i
.types
[j
- 1] = i
.types
[j
];
4754 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
4758 else if (i
.tm
.opcode_modifier
.implicit1stxmm0
)
4760 gas_assert ((MAX_OPERANDS
- 1) > dupl
4761 && (i
.tm
.opcode_modifier
.vexsources
4764 /* Add the implicit xmm0 for instructions with VEX prefix
4766 for (j
= i
.operands
; j
> 0; j
--)
4768 i
.op
[j
] = i
.op
[j
- 1];
4769 i
.types
[j
] = i
.types
[j
- 1];
4770 i
.tm
.operand_types
[j
] = i
.tm
.operand_types
[j
- 1];
4773 = (const reg_entry
*) hash_find (reg_hash
, "xmm0");
4774 i
.types
[0] = regxmm
;
4775 i
.tm
.operand_types
[0] = regxmm
;
4778 i
.reg_operands
+= 2;
4783 i
.op
[dupl
] = i
.op
[dest
];
4784 i
.types
[dupl
] = i
.types
[dest
];
4785 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
4794 i
.op
[dupl
] = i
.op
[dest
];
4795 i
.types
[dupl
] = i
.types
[dest
];
4796 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
4799 if (i
.tm
.opcode_modifier
.immext
)
4802 else if (i
.tm
.opcode_modifier
.firstxmm0
)
4806 /* The first operand is implicit and must be xmm0/ymm0. */
4807 gas_assert (i
.reg_operands
4808 && (operand_type_equal (&i
.types
[0], ®xmm
)
4809 || operand_type_equal (&i
.types
[0], ®ymm
)));
4810 if (i
.op
[0].regs
->reg_num
!= 0)
4811 return bad_implicit_operand (i
.types
[0].bitfield
.regxmm
);
4813 for (j
= 1; j
< i
.operands
; j
++)
4815 i
.op
[j
- 1] = i
.op
[j
];
4816 i
.types
[j
- 1] = i
.types
[j
];
4818 /* We need to adjust fields in i.tm since they are used by
4819 build_modrm_byte. */
4820 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
4827 else if (i
.tm
.opcode_modifier
.regkludge
)
4829 /* The imul $imm, %reg instruction is converted into
4830 imul $imm, %reg, %reg, and the clr %reg instruction
4831 is converted into xor %reg, %reg. */
4833 unsigned int first_reg_op
;
4835 if (operand_type_check (i
.types
[0], reg
))
4839 /* Pretend we saw the extra register operand. */
4840 gas_assert (i
.reg_operands
== 1
4841 && i
.op
[first_reg_op
+ 1].regs
== 0);
4842 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
4843 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
4848 if (i
.tm
.opcode_modifier
.shortform
)
4850 if (i
.types
[0].bitfield
.sreg2
4851 || i
.types
[0].bitfield
.sreg3
)
4853 if (i
.tm
.base_opcode
== POP_SEG_SHORT
4854 && i
.op
[0].regs
->reg_num
== 1)
4856 as_bad (_("you can't `pop %scs'"), register_prefix
);
4859 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
4860 if ((i
.op
[0].regs
->reg_flags
& RegRex
) != 0)
4865 /* The register or float register operand is in operand
4869 if (i
.types
[0].bitfield
.floatreg
4870 || operand_type_check (i
.types
[0], reg
))
4874 /* Register goes in low 3 bits of opcode. */
4875 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
4876 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
4878 if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
4880 /* Warn about some common errors, but press on regardless.
4881 The first case can be generated by gcc (<= 2.8.1). */
4882 if (i
.operands
== 2)
4884 /* Reversed arguments on faddp, fsubp, etc. */
4885 as_warn (_("translating to `%s %s%s,%s%s'"), i
.tm
.name
,
4886 register_prefix
, i
.op
[!intel_syntax
].regs
->reg_name
,
4887 register_prefix
, i
.op
[intel_syntax
].regs
->reg_name
);
4891 /* Extraneous `l' suffix on fp insn. */
4892 as_warn (_("translating to `%s %s%s'"), i
.tm
.name
,
4893 register_prefix
, i
.op
[0].regs
->reg_name
);
4898 else if (i
.tm
.opcode_modifier
.modrm
)
4900 /* The opcode is completed (modulo i.tm.extension_opcode which
4901 must be put into the modrm byte). Now, we make the modrm and
4902 index base bytes based on all the info we've collected. */
4904 default_seg
= build_modrm_byte ();
4906 else if ((i
.tm
.base_opcode
& ~0x3) == MOV_AX_DISP32
)
4910 else if (i
.tm
.opcode_modifier
.isstring
)
4912 /* For the string instructions that allow a segment override
4913 on one of their operands, the default segment is ds. */
4917 if (i
.tm
.base_opcode
== 0x8d /* lea */
4920 as_warn (_("segment override on `%s' is ineffectual"), i
.tm
.name
);
4922 /* If a segment was explicitly specified, and the specified segment
4923 is not the default, use an opcode prefix to select it. If we
4924 never figured out what the default segment is, then default_seg
4925 will be zero at this point, and the specified segment prefix will
4927 if ((i
.seg
[0]) && (i
.seg
[0] != default_seg
))
4929 if (!add_prefix (i
.seg
[0]->seg_prefix
))
4935 static const seg_entry
*
4936 build_modrm_byte (void)
4938 const seg_entry
*default_seg
= 0;
4939 unsigned int source
, dest
;
4942 /* The first operand of instructions with VEX prefix and 3 sources
4943 must be VEX_Imm4. */
4944 vex_3_sources
= i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
;
4947 unsigned int nds
, reg_slot
;
4950 if (i
.tm
.opcode_modifier
.veximmext
4951 && i
.tm
.opcode_modifier
.immext
)
4953 dest
= i
.operands
- 2;
4954 gas_assert (dest
== 3);
4957 dest
= i
.operands
- 1;
4960 /* This instruction must have 4 register operands
4961 or 3 register operands plus 1 memory operand.
4962 It must have VexNDS and VexImmExt. */
4963 gas_assert ((i
.reg_operands
== 4
4964 || (i
.reg_operands
== 3 && i
.mem_operands
== 1))
4965 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
4966 && i
.tm
.opcode_modifier
.veximmext
4967 && (operand_type_equal (&i
.tm
.operand_types
[dest
], ®xmm
)
4968 || operand_type_equal (&i
.tm
.operand_types
[dest
], ®ymm
)));
4970 /* Generate an 8bit immediate operand to encode the register
4972 exp
= &im_expressions
[i
.imm_operands
++];
4973 i
.op
[i
.operands
].imms
= exp
;
4974 i
.types
[i
.operands
] = imm8
;
4976 /* If VexW1 is set, the first operand is the source and
4977 the second operand is encoded in the immediate operand. */
4978 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
4988 gas_assert ((operand_type_equal (&i
.tm
.operand_types
[reg_slot
], ®xmm
)
4989 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
4991 && (operand_type_equal (&i
.tm
.operand_types
[nds
], ®xmm
)
4992 || operand_type_equal (&i
.tm
.operand_types
[nds
],
4994 exp
->X_op
= O_constant
;
4996 = ((i
.op
[reg_slot
].regs
->reg_num
4997 + ((i
.op
[reg_slot
].regs
->reg_flags
& RegRex
) ? 8 : 0)) << 4);
4998 i
.vex
.register_specifier
= i
.op
[nds
].regs
;
5003 /* i.reg_operands MUST be the number of real register operands;
5004 implicit registers do not count. If there are 3 register
5005 operands, it must be a instruction with VexNDS. For a
5006 instruction with VexNDD, the destination register is encoded
5007 in VEX prefix. If there are 4 register operands, it must be
5008 a instruction with VEX prefix and 3 sources. */
5009 if (i
.mem_operands
== 0
5010 && ((i
.reg_operands
== 2
5011 && i
.tm
.opcode_modifier
.vexvvvv
<= VEXXDS
)
5012 || (i
.reg_operands
== 3
5013 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
5014 || (i
.reg_operands
== 4 && vex_3_sources
)))
5022 /* When there are 3 operands, one of them may be immediate,
5023 which may be the first or the last operand. Otherwise,
5024 the first operand must be shift count register (cl) or it
5025 is an instruction with VexNDS. */
5026 gas_assert (i
.imm_operands
== 1
5027 || (i
.imm_operands
== 0
5028 && (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
5029 || i
.types
[0].bitfield
.shiftcount
)));
5030 if (operand_type_check (i
.types
[0], imm
)
5031 || i
.types
[0].bitfield
.shiftcount
)
5037 /* When there are 4 operands, the first two must be 8bit
5038 immediate operands. The source operand will be the 3rd
5041 For instructions with VexNDS, if the first operand
5042 an imm8, the source operand is the 2nd one. If the last
5043 operand is imm8, the source operand is the first one. */
5044 gas_assert ((i
.imm_operands
== 2
5045 && i
.types
[0].bitfield
.imm8
5046 && i
.types
[1].bitfield
.imm8
)
5047 || (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
5048 && i
.imm_operands
== 1
5049 && (i
.types
[0].bitfield
.imm8
5050 || i
.types
[i
.operands
- 1].bitfield
.imm8
)));
5051 if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
5053 if (i
.types
[0].bitfield
.imm8
)
5071 if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
5073 /* For instructions with VexNDS, the register-only
5074 source operand must be XMM or YMM register. It is
5075 encoded in VEX prefix. We need to clear RegMem bit
5076 before calling operand_type_equal. */
5077 i386_operand_type op
= i
.tm
.operand_types
[dest
];
5078 op
.bitfield
.regmem
= 0;
5079 if ((dest
+ 1) >= i
.operands
5080 || (!operand_type_equal (&op
, ®xmm
)
5081 && !operand_type_equal (&op
, ®ymm
)))
5083 i
.vex
.register_specifier
= i
.op
[dest
].regs
;
5089 /* One of the register operands will be encoded in the i.tm.reg
5090 field, the other in the combined i.tm.mode and i.tm.regmem
5091 fields. If no form of this instruction supports a memory
5092 destination operand, then we assume the source operand may
5093 sometimes be a memory operand and so we need to store the
5094 destination in the i.rm.reg field. */
5095 if (!i
.tm
.operand_types
[dest
].bitfield
.regmem
5096 && operand_type_check (i
.tm
.operand_types
[dest
], anymem
) == 0)
5098 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
5099 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
5100 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
5102 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
5107 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
5108 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
5109 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
5111 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
5114 if (flag_code
!= CODE_64BIT
&& (i
.rex
& (REX_R
| REX_B
)))
5116 if (!i
.types
[0].bitfield
.control
5117 && !i
.types
[1].bitfield
.control
)
5119 i
.rex
&= ~(REX_R
| REX_B
);
5120 add_prefix (LOCK_PREFIX_OPCODE
);
5124 { /* If it's not 2 reg operands... */
5129 unsigned int fake_zero_displacement
= 0;
5132 for (op
= 0; op
< i
.operands
; op
++)
5133 if (operand_type_check (i
.types
[op
], anymem
))
5135 gas_assert (op
< i
.operands
);
5139 if (i
.base_reg
== 0)
5142 if (!i
.disp_operands
)
5143 fake_zero_displacement
= 1;
5144 if (i
.index_reg
== 0)
5146 /* Operand is just <disp> */
5147 if (flag_code
== CODE_64BIT
)
5149 /* 64bit mode overwrites the 32bit absolute
5150 addressing by RIP relative addressing and
5151 absolute addressing is encoded by one of the
5152 redundant SIB forms. */
5153 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
5154 i
.sib
.base
= NO_BASE_REGISTER
;
5155 i
.sib
.index
= NO_INDEX_REGISTER
;
5156 i
.types
[op
] = ((i
.prefix
[ADDR_PREFIX
] == 0)
5157 ? disp32s
: disp32
);
5159 else if ((flag_code
== CODE_16BIT
)
5160 ^ (i
.prefix
[ADDR_PREFIX
] != 0))
5162 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
5163 i
.types
[op
] = disp16
;
5167 i
.rm
.regmem
= NO_BASE_REGISTER
;
5168 i
.types
[op
] = disp32
;
5171 else /* !i.base_reg && i.index_reg */
5173 if (i
.index_reg
->reg_num
== RegEiz
5174 || i
.index_reg
->reg_num
== RegRiz
)
5175 i
.sib
.index
= NO_INDEX_REGISTER
;
5177 i
.sib
.index
= i
.index_reg
->reg_num
;
5178 i
.sib
.base
= NO_BASE_REGISTER
;
5179 i
.sib
.scale
= i
.log2_scale_factor
;
5180 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
5181 i
.types
[op
].bitfield
.disp8
= 0;
5182 i
.types
[op
].bitfield
.disp16
= 0;
5183 i
.types
[op
].bitfield
.disp64
= 0;
5184 if (flag_code
!= CODE_64BIT
)
5186 /* Must be 32 bit */
5187 i
.types
[op
].bitfield
.disp32
= 1;
5188 i
.types
[op
].bitfield
.disp32s
= 0;
5192 i
.types
[op
].bitfield
.disp32
= 0;
5193 i
.types
[op
].bitfield
.disp32s
= 1;
5195 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
5199 /* RIP addressing for 64bit mode. */
5200 else if (i
.base_reg
->reg_num
== RegRip
||
5201 i
.base_reg
->reg_num
== RegEip
)
5203 i
.rm
.regmem
= NO_BASE_REGISTER
;
5204 i
.types
[op
].bitfield
.disp8
= 0;
5205 i
.types
[op
].bitfield
.disp16
= 0;
5206 i
.types
[op
].bitfield
.disp32
= 0;
5207 i
.types
[op
].bitfield
.disp32s
= 1;
5208 i
.types
[op
].bitfield
.disp64
= 0;
5209 i
.flags
[op
] |= Operand_PCrel
;
5210 if (! i
.disp_operands
)
5211 fake_zero_displacement
= 1;
5213 else if (i
.base_reg
->reg_type
.bitfield
.reg16
)
5215 switch (i
.base_reg
->reg_num
)
5218 if (i
.index_reg
== 0)
5220 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
5221 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
5225 if (i
.index_reg
== 0)
5228 if (operand_type_check (i
.types
[op
], disp
) == 0)
5230 /* fake (%bp) into 0(%bp) */
5231 i
.types
[op
].bitfield
.disp8
= 1;
5232 fake_zero_displacement
= 1;
5235 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
5236 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
5238 default: /* (%si) -> 4 or (%di) -> 5 */
5239 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
5241 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
5243 else /* i.base_reg and 32/64 bit mode */
5245 if (flag_code
== CODE_64BIT
5246 && operand_type_check (i
.types
[op
], disp
))
5248 i386_operand_type temp
;
5249 operand_type_set (&temp
, 0);
5250 temp
.bitfield
.disp8
= i
.types
[op
].bitfield
.disp8
;
5252 if (i
.prefix
[ADDR_PREFIX
] == 0)
5253 i
.types
[op
].bitfield
.disp32s
= 1;
5255 i
.types
[op
].bitfield
.disp32
= 1;
5258 i
.rm
.regmem
= i
.base_reg
->reg_num
;
5259 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
5261 i
.sib
.base
= i
.base_reg
->reg_num
;
5262 /* x86-64 ignores REX prefix bit here to avoid decoder
5264 if ((i
.base_reg
->reg_num
& 7) == EBP_REG_NUM
)
5267 if (i
.disp_operands
== 0)
5269 fake_zero_displacement
= 1;
5270 i
.types
[op
].bitfield
.disp8
= 1;
5273 else if (i
.base_reg
->reg_num
== ESP_REG_NUM
)
5277 i
.sib
.scale
= i
.log2_scale_factor
;
5278 if (i
.index_reg
== 0)
5280 /* <disp>(%esp) becomes two byte modrm with no index
5281 register. We've already stored the code for esp
5282 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
5283 Any base register besides %esp will not use the
5284 extra modrm byte. */
5285 i
.sib
.index
= NO_INDEX_REGISTER
;
5289 if (i
.index_reg
->reg_num
== RegEiz
5290 || i
.index_reg
->reg_num
== RegRiz
)
5291 i
.sib
.index
= NO_INDEX_REGISTER
;
5293 i
.sib
.index
= i
.index_reg
->reg_num
;
5294 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
5295 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
5300 && (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
5301 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
))
5304 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
5307 if (fake_zero_displacement
)
5309 /* Fakes a zero displacement assuming that i.types[op]
5310 holds the correct displacement size. */
5313 gas_assert (i
.op
[op
].disps
== 0);
5314 exp
= &disp_expressions
[i
.disp_operands
++];
5315 i
.op
[op
].disps
= exp
;
5316 exp
->X_op
= O_constant
;
5317 exp
->X_add_number
= 0;
5318 exp
->X_add_symbol
= (symbolS
*) 0;
5319 exp
->X_op_symbol
= (symbolS
*) 0;
5327 if (i
.tm
.opcode_modifier
.vexsources
== XOP2SOURCES
)
5329 if (operand_type_check (i
.types
[0], imm
))
5330 i
.vex
.register_specifier
= NULL
;
5333 /* VEX.vvvv encodes one of the sources when the first
5334 operand is not an immediate. */
5335 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
5336 i
.vex
.register_specifier
= i
.op
[0].regs
;
5338 i
.vex
.register_specifier
= i
.op
[1].regs
;
5341 /* Destination is a XMM register encoded in the ModRM.reg
5343 i
.rm
.reg
= i
.op
[2].regs
->reg_num
;
5344 if ((i
.op
[2].regs
->reg_flags
& RegRex
) != 0)
5347 /* ModRM.rm and VEX.B encodes the other source. */
5348 if (!i
.mem_operands
)
5352 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
5353 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
5355 i
.rm
.regmem
= i
.op
[0].regs
->reg_num
;
5357 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
5361 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXLWP
)
5363 i
.vex
.register_specifier
= i
.op
[2].regs
;
5364 if (!i
.mem_operands
)
5367 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
5368 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
5372 /* Fill in i.rm.reg or i.rm.regmem field with register operand
5373 (if any) based on i.tm.extension_opcode. Again, we must be
5374 careful to make sure that segment/control/debug/test/MMX
5375 registers are coded into the i.rm.reg field. */
5376 else if (i
.reg_operands
)
5379 unsigned int vex_reg
= ~0;
5381 for (op
= 0; op
< i
.operands
; op
++)
5382 if (i
.types
[op
].bitfield
.reg8
5383 || i
.types
[op
].bitfield
.reg16
5384 || i
.types
[op
].bitfield
.reg32
5385 || i
.types
[op
].bitfield
.reg64
5386 || i
.types
[op
].bitfield
.regmmx
5387 || i
.types
[op
].bitfield
.regxmm
5388 || i
.types
[op
].bitfield
.regymm
5389 || i
.types
[op
].bitfield
.sreg2
5390 || i
.types
[op
].bitfield
.sreg3
5391 || i
.types
[op
].bitfield
.control
5392 || i
.types
[op
].bitfield
.debug
5393 || i
.types
[op
].bitfield
.test
)
5398 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
5400 /* For instructions with VexNDS, the register-only
5401 source operand is encoded in VEX prefix. */
5402 gas_assert (mem
!= (unsigned int) ~0);
5407 gas_assert (op
< i
.operands
);
5412 gas_assert (vex_reg
< i
.operands
);
5415 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXNDD
)
5417 /* For instructions with VexNDD, there should be
5418 no memory operand and the register destination
5419 is encoded in VEX prefix. */
5420 gas_assert (i
.mem_operands
== 0
5421 && (op
+ 2) == i
.operands
);
5425 gas_assert (op
< i
.operands
);
5427 if (vex_reg
!= (unsigned int) ~0)
5429 gas_assert (i
.reg_operands
== 2);
5431 if (!operand_type_equal (&i
.tm
.operand_types
[vex_reg
],
5433 && !operand_type_equal (&i
.tm
.operand_types
[vex_reg
],
5437 i
.vex
.register_specifier
= i
.op
[vex_reg
].regs
;
5440 /* Don't set OP operand twice. */
5443 /* If there is an extension opcode to put here, the
5444 register number must be put into the regmem field. */
5445 if (i
.tm
.extension_opcode
!= None
)
5447 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
5448 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
5453 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
5454 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
5459 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
5460 must set it to 3 to indicate this is a register operand
5461 in the regmem field. */
5462 if (!i
.mem_operands
)
5466 /* Fill in i.rm.reg field with extension opcode (if any). */
5467 if (i
.tm
.extension_opcode
!= None
)
5468 i
.rm
.reg
= i
.tm
.extension_opcode
;
5474 output_branch (void)
5479 relax_substateT subtype
;
5484 if (flag_code
== CODE_16BIT
)
5488 if (i
.prefix
[DATA_PREFIX
] != 0)
5494 /* Pentium4 branch hints. */
5495 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
5496 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
5501 if (i
.prefix
[REX_PREFIX
] != 0)
5507 if (i
.prefixes
!= 0 && !intel_syntax
)
5508 as_warn (_("skipping prefixes on this instruction"));
5510 /* It's always a symbol; End frag & setup for relax.
5511 Make sure there is enough room in this frag for the largest
5512 instruction we may generate in md_convert_frag. This is 2
5513 bytes for the opcode and room for the prefix and largest
5515 frag_grow (prefix
+ 2 + 4);
5516 /* Prefix and 1 opcode byte go in fr_fix. */
5517 p
= frag_more (prefix
+ 1);
5518 if (i
.prefix
[DATA_PREFIX
] != 0)
5519 *p
++ = DATA_PREFIX_OPCODE
;
5520 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
5521 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
5522 *p
++ = i
.prefix
[SEG_PREFIX
];
5523 if (i
.prefix
[REX_PREFIX
] != 0)
5524 *p
++ = i
.prefix
[REX_PREFIX
];
5525 *p
= i
.tm
.base_opcode
;
5527 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
5528 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, SMALL
);
5529 else if (cpu_arch_flags
.bitfield
.cpui386
)
5530 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, SMALL
);
5532 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, SMALL
);
5535 sym
= i
.op
[0].disps
->X_add_symbol
;
5536 off
= i
.op
[0].disps
->X_add_number
;
5538 if (i
.op
[0].disps
->X_op
!= O_constant
5539 && i
.op
[0].disps
->X_op
!= O_symbol
)
5541 /* Handle complex expressions. */
5542 sym
= make_expr_symbol (i
.op
[0].disps
);
5546 /* 1 possible extra opcode + 4 byte displacement go in var part.
5547 Pass reloc in fr_var. */
5548 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
5558 if (i
.tm
.opcode_modifier
.jumpbyte
)
5560 /* This is a loop or jecxz type instruction. */
5562 if (i
.prefix
[ADDR_PREFIX
] != 0)
5564 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
5567 /* Pentium4 branch hints. */
5568 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
5569 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
5571 FRAG_APPEND_1_CHAR (i
.prefix
[SEG_PREFIX
]);
5580 if (flag_code
== CODE_16BIT
)
5583 if (i
.prefix
[DATA_PREFIX
] != 0)
5585 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
5595 if (i
.prefix
[REX_PREFIX
] != 0)
5597 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
5601 if (i
.prefixes
!= 0 && !intel_syntax
)
5602 as_warn (_("skipping prefixes on this instruction"));
5604 p
= frag_more (1 + size
);
5605 *p
++ = i
.tm
.base_opcode
;
5607 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
5608 i
.op
[0].disps
, 1, reloc (size
, 1, 1, i
.reloc
[0]));
5610 /* All jumps handled here are signed, but don't use a signed limit
5611 check for 32 and 16 bit jumps as we want to allow wrap around at
5612 4G and 64k respectively. */
5614 fixP
->fx_signed
= 1;
5618 output_interseg_jump (void)
5626 if (flag_code
== CODE_16BIT
)
5630 if (i
.prefix
[DATA_PREFIX
] != 0)
5636 if (i
.prefix
[REX_PREFIX
] != 0)
5646 if (i
.prefixes
!= 0 && !intel_syntax
)
5647 as_warn (_("skipping prefixes on this instruction"));
5649 /* 1 opcode; 2 segment; offset */
5650 p
= frag_more (prefix
+ 1 + 2 + size
);
5652 if (i
.prefix
[DATA_PREFIX
] != 0)
5653 *p
++ = DATA_PREFIX_OPCODE
;
5655 if (i
.prefix
[REX_PREFIX
] != 0)
5656 *p
++ = i
.prefix
[REX_PREFIX
];
5658 *p
++ = i
.tm
.base_opcode
;
5659 if (i
.op
[1].imms
->X_op
== O_constant
)
5661 offsetT n
= i
.op
[1].imms
->X_add_number
;
5664 && !fits_in_unsigned_word (n
)
5665 && !fits_in_signed_word (n
))
5667 as_bad (_("16-bit jump out of range"));
5670 md_number_to_chars (p
, n
, size
);
5673 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
5674 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
5675 if (i
.op
[0].imms
->X_op
!= O_constant
)
5676 as_bad (_("can't handle non absolute segment in `%s'"),
5678 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
5684 fragS
*insn_start_frag
;
5685 offsetT insn_start_off
;
5687 /* Tie dwarf2 debug info to the address at the start of the insn.
5688 We can't do this after the insn has been output as the current
5689 frag may have been closed off. eg. by frag_var. */
5690 dwarf2_emit_insn (0);
5692 insn_start_frag
= frag_now
;
5693 insn_start_off
= frag_now_fix ();
5696 if (i
.tm
.opcode_modifier
.jump
)
5698 else if (i
.tm
.opcode_modifier
.jumpbyte
5699 || i
.tm
.opcode_modifier
.jumpdword
)
5701 else if (i
.tm
.opcode_modifier
.jumpintersegment
)
5702 output_interseg_jump ();
5705 /* Output normal instructions here. */
5709 unsigned int prefix
;
5711 /* Since the VEX prefix contains the implicit prefix, we don't
5712 need the explicit prefix. */
5713 if (!i
.tm
.opcode_modifier
.vex
)
5715 switch (i
.tm
.opcode_length
)
5718 if (i
.tm
.base_opcode
& 0xff000000)
5720 prefix
= (i
.tm
.base_opcode
>> 24) & 0xff;
5725 if ((i
.tm
.base_opcode
& 0xff0000) != 0)
5727 prefix
= (i
.tm
.base_opcode
>> 16) & 0xff;
5728 if (i
.tm
.cpu_flags
.bitfield
.cpupadlock
)
5731 if (prefix
!= REPE_PREFIX_OPCODE
5732 || (i
.prefix
[REP_PREFIX
]
5733 != REPE_PREFIX_OPCODE
))
5734 add_prefix (prefix
);
5737 add_prefix (prefix
);
5746 /* The prefix bytes. */
5747 for (j
= ARRAY_SIZE (i
.prefix
), q
= i
.prefix
; j
> 0; j
--, q
++)
5749 FRAG_APPEND_1_CHAR (*q
);
5752 if (i
.tm
.opcode_modifier
.vex
)
5754 for (j
= 0, q
= i
.prefix
; j
< ARRAY_SIZE (i
.prefix
); j
++, q
++)
5759 /* REX byte is encoded in VEX prefix. */
5763 FRAG_APPEND_1_CHAR (*q
);
5766 /* There should be no other prefixes for instructions
5771 /* Now the VEX prefix. */
5772 p
= frag_more (i
.vex
.length
);
5773 for (j
= 0; j
< i
.vex
.length
; j
++)
5774 p
[j
] = i
.vex
.bytes
[j
];
5777 /* Now the opcode; be careful about word order here! */
5778 if (i
.tm
.opcode_length
== 1)
5780 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
5784 switch (i
.tm
.opcode_length
)
5788 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
5798 /* Put out high byte first: can't use md_number_to_chars! */
5799 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
5800 *p
= i
.tm
.base_opcode
& 0xff;
5803 /* Now the modrm byte and sib byte (if present). */
5804 if (i
.tm
.opcode_modifier
.modrm
)
5806 FRAG_APPEND_1_CHAR ((i
.rm
.regmem
<< 0
5809 /* If i.rm.regmem == ESP (4)
5810 && i.rm.mode != (Register mode)
5812 ==> need second modrm byte. */
5813 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
5815 && !(i
.base_reg
&& i
.base_reg
->reg_type
.bitfield
.reg16
))
5816 FRAG_APPEND_1_CHAR ((i
.sib
.base
<< 0
5818 | i
.sib
.scale
<< 6));
5821 if (i
.disp_operands
)
5822 output_disp (insn_start_frag
, insn_start_off
);
5825 output_imm (insn_start_frag
, insn_start_off
);
5831 pi ("" /*line*/, &i
);
5833 #endif /* DEBUG386 */
5836 /* Return the size of the displacement operand N. */
5839 disp_size (unsigned int n
)
5842 if (i
.types
[n
].bitfield
.disp64
)
5844 else if (i
.types
[n
].bitfield
.disp8
)
5846 else if (i
.types
[n
].bitfield
.disp16
)
5851 /* Return the size of the immediate operand N. */
5854 imm_size (unsigned int n
)
5857 if (i
.types
[n
].bitfield
.imm64
)
5859 else if (i
.types
[n
].bitfield
.imm8
|| i
.types
[n
].bitfield
.imm8s
)
5861 else if (i
.types
[n
].bitfield
.imm16
)
5867 output_disp (fragS
*insn_start_frag
, offsetT insn_start_off
)
5872 for (n
= 0; n
< i
.operands
; n
++)
5874 if (operand_type_check (i
.types
[n
], disp
))
5876 if (i
.op
[n
].disps
->X_op
== O_constant
)
5878 int size
= disp_size (n
);
5881 val
= offset_in_range (i
.op
[n
].disps
->X_add_number
,
5883 p
= frag_more (size
);
5884 md_number_to_chars (p
, val
, size
);
5888 enum bfd_reloc_code_real reloc_type
;
5889 int size
= disp_size (n
);
5890 int sign
= i
.types
[n
].bitfield
.disp32s
;
5891 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
5893 /* We can't have 8 bit displacement here. */
5894 gas_assert (!i
.types
[n
].bitfield
.disp8
);
5896 /* The PC relative address is computed relative
5897 to the instruction boundary, so in case immediate
5898 fields follows, we need to adjust the value. */
5899 if (pcrel
&& i
.imm_operands
)
5904 for (n1
= 0; n1
< i
.operands
; n1
++)
5905 if (operand_type_check (i
.types
[n1
], imm
))
5907 /* Only one immediate is allowed for PC
5908 relative address. */
5909 gas_assert (sz
== 0);
5911 i
.op
[n
].disps
->X_add_number
-= sz
;
5913 /* We should find the immediate. */
5914 gas_assert (sz
!= 0);
5917 p
= frag_more (size
);
5918 reloc_type
= reloc (size
, pcrel
, sign
, i
.reloc
[n
]);
5920 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
5921 && (((reloc_type
== BFD_RELOC_32
5922 || reloc_type
== BFD_RELOC_X86_64_32S
5923 || (reloc_type
== BFD_RELOC_64
5925 && (i
.op
[n
].disps
->X_op
== O_symbol
5926 || (i
.op
[n
].disps
->X_op
== O_add
5927 && ((symbol_get_value_expression
5928 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
5930 || reloc_type
== BFD_RELOC_32_PCREL
))
5934 if (insn_start_frag
== frag_now
)
5935 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
5940 add
= insn_start_frag
->fr_fix
- insn_start_off
;
5941 for (fr
= insn_start_frag
->fr_next
;
5942 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
5944 add
+= p
- frag_now
->fr_literal
;
5949 reloc_type
= BFD_RELOC_386_GOTPC
;
5950 i
.op
[n
].imms
->X_add_number
+= add
;
5952 else if (reloc_type
== BFD_RELOC_64
)
5953 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
5955 /* Don't do the adjustment for x86-64, as there
5956 the pcrel addressing is relative to the _next_
5957 insn, and that is taken care of in other code. */
5958 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
5960 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
5961 i
.op
[n
].disps
, pcrel
, reloc_type
);
5968 output_imm (fragS
*insn_start_frag
, offsetT insn_start_off
)
5973 for (n
= 0; n
< i
.operands
; n
++)
5975 if (operand_type_check (i
.types
[n
], imm
))
5977 if (i
.op
[n
].imms
->X_op
== O_constant
)
5979 int size
= imm_size (n
);
5982 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
5984 p
= frag_more (size
);
5985 md_number_to_chars (p
, val
, size
);
5989 /* Not absolute_section.
5990 Need a 32-bit fixup (don't support 8bit
5991 non-absolute imms). Try to support other
5993 enum bfd_reloc_code_real reloc_type
;
5994 int size
= imm_size (n
);
5997 if (i
.types
[n
].bitfield
.imm32s
5998 && (i
.suffix
== QWORD_MNEM_SUFFIX
5999 || (!i
.suffix
&& i
.tm
.opcode_modifier
.no_lsuf
)))
6004 p
= frag_more (size
);
6005 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
6007 /* This is tough to explain. We end up with this one if we
6008 * have operands that look like
6009 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
6010 * obtain the absolute address of the GOT, and it is strongly
6011 * preferable from a performance point of view to avoid using
6012 * a runtime relocation for this. The actual sequence of
6013 * instructions often look something like:
6018 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
6020 * The call and pop essentially return the absolute address
6021 * of the label .L66 and store it in %ebx. The linker itself
6022 * will ultimately change the first operand of the addl so
6023 * that %ebx points to the GOT, but to keep things simple, the
6024 * .o file must have this operand set so that it generates not
6025 * the absolute address of .L66, but the absolute address of
6026 * itself. This allows the linker itself simply treat a GOTPC
6027 * relocation as asking for a pcrel offset to the GOT to be
6028 * added in, and the addend of the relocation is stored in the
6029 * operand field for the instruction itself.
6031 * Our job here is to fix the operand so that it would add
6032 * the correct offset so that %ebx would point to itself. The
6033 * thing that is tricky is that .-.L66 will point to the
6034 * beginning of the instruction, so we need to further modify
6035 * the operand so that it will point to itself. There are
6036 * other cases where you have something like:
6038 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
6040 * and here no correction would be required. Internally in
6041 * the assembler we treat operands of this form as not being
6042 * pcrel since the '.' is explicitly mentioned, and I wonder
6043 * whether it would simplify matters to do it this way. Who
6044 * knows. In earlier versions of the PIC patches, the
6045 * pcrel_adjust field was used to store the correction, but
6046 * since the expression is not pcrel, I felt it would be
6047 * confusing to do it this way. */
6049 if ((reloc_type
== BFD_RELOC_32
6050 || reloc_type
== BFD_RELOC_X86_64_32S
6051 || reloc_type
== BFD_RELOC_64
)
6053 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
6054 && (i
.op
[n
].imms
->X_op
== O_symbol
6055 || (i
.op
[n
].imms
->X_op
== O_add
6056 && ((symbol_get_value_expression
6057 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
6062 if (insn_start_frag
== frag_now
)
6063 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
6068 add
= insn_start_frag
->fr_fix
- insn_start_off
;
6069 for (fr
= insn_start_frag
->fr_next
;
6070 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
6072 add
+= p
- frag_now
->fr_literal
;
6076 reloc_type
= BFD_RELOC_386_GOTPC
;
6078 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
6080 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
6081 i
.op
[n
].imms
->X_add_number
+= add
;
6083 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
6084 i
.op
[n
].imms
, 0, reloc_type
);
6090 /* x86_cons_fix_new is called via the expression parsing code when a
6091 reloc is needed. We use this hook to get the correct .got reloc. */
6092 static enum bfd_reloc_code_real got_reloc
= NO_RELOC
;
6093 static int cons_sign
= -1;
6096 x86_cons_fix_new (fragS
*frag
, unsigned int off
, unsigned int len
,
6099 enum bfd_reloc_code_real r
= reloc (len
, 0, cons_sign
, got_reloc
);
6101 got_reloc
= NO_RELOC
;
6104 if (exp
->X_op
== O_secrel
)
6106 exp
->X_op
= O_symbol
;
6107 r
= BFD_RELOC_32_SECREL
;
6111 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
6114 #if (!defined (OBJ_ELF) && !defined (OBJ_MAYBE_ELF)) || defined (LEX_AT)
6115 # define lex_got(reloc, adjust, types) NULL
6117 /* Parse operands of the form
6118 <symbol>@GOTOFF+<nnn>
6119 and similar .plt or .got references.
6121 If we find one, set up the correct relocation in RELOC and copy the
6122 input string, minus the `@GOTOFF' into a malloc'd buffer for
6123 parsing by the calling routine. Return this buffer, and if ADJUST
6124 is non-null set it to the length of the string we removed from the
6125 input line. Otherwise return NULL. */
6127 lex_got (enum bfd_reloc_code_real
*rel
,
6129 i386_operand_type
*types
)
6131 /* Some of the relocations depend on the size of what field is to
6132 be relocated. But in our callers i386_immediate and i386_displacement
6133 we don't yet know the operand size (this will be set by insn
6134 matching). Hence we record the word32 relocation here,
6135 and adjust the reloc according to the real size in reloc(). */
6136 static const struct {
6138 const enum bfd_reloc_code_real rel
[2];
6139 const i386_operand_type types64
;
6141 { "PLTOFF", { _dummy_first_bfd_reloc_code_real
,
6142 BFD_RELOC_X86_64_PLTOFF64
},
6143 OPERAND_TYPE_IMM64
},
6144 { "PLT", { BFD_RELOC_386_PLT32
,
6145 BFD_RELOC_X86_64_PLT32
},
6146 OPERAND_TYPE_IMM32_32S_DISP32
},
6147 { "GOTPLT", { _dummy_first_bfd_reloc_code_real
,
6148 BFD_RELOC_X86_64_GOTPLT64
},
6149 OPERAND_TYPE_IMM64_DISP64
},
6150 { "GOTOFF", { BFD_RELOC_386_GOTOFF
,
6151 BFD_RELOC_X86_64_GOTOFF64
},
6152 OPERAND_TYPE_IMM64_DISP64
},
6153 { "GOTPCREL", { _dummy_first_bfd_reloc_code_real
,
6154 BFD_RELOC_X86_64_GOTPCREL
},
6155 OPERAND_TYPE_IMM32_32S_DISP32
},
6156 { "TLSGD", { BFD_RELOC_386_TLS_GD
,
6157 BFD_RELOC_X86_64_TLSGD
},
6158 OPERAND_TYPE_IMM32_32S_DISP32
},
6159 { "TLSLDM", { BFD_RELOC_386_TLS_LDM
,
6160 _dummy_first_bfd_reloc_code_real
},
6161 OPERAND_TYPE_NONE
},
6162 { "TLSLD", { _dummy_first_bfd_reloc_code_real
,
6163 BFD_RELOC_X86_64_TLSLD
},
6164 OPERAND_TYPE_IMM32_32S_DISP32
},
6165 { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32
,
6166 BFD_RELOC_X86_64_GOTTPOFF
},
6167 OPERAND_TYPE_IMM32_32S_DISP32
},
6168 { "TPOFF", { BFD_RELOC_386_TLS_LE_32
,
6169 BFD_RELOC_X86_64_TPOFF32
},
6170 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
6171 { "NTPOFF", { BFD_RELOC_386_TLS_LE
,
6172 _dummy_first_bfd_reloc_code_real
},
6173 OPERAND_TYPE_NONE
},
6174 { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32
,
6175 BFD_RELOC_X86_64_DTPOFF32
},
6177 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
6178 { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE
,
6179 _dummy_first_bfd_reloc_code_real
},
6180 OPERAND_TYPE_NONE
},
6181 { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE
,
6182 _dummy_first_bfd_reloc_code_real
},
6183 OPERAND_TYPE_NONE
},
6184 { "GOT", { BFD_RELOC_386_GOT32
,
6185 BFD_RELOC_X86_64_GOT32
},
6186 OPERAND_TYPE_IMM32_32S_64_DISP32
},
6187 { "TLSDESC", { BFD_RELOC_386_TLS_GOTDESC
,
6188 BFD_RELOC_X86_64_GOTPC32_TLSDESC
},
6189 OPERAND_TYPE_IMM32_32S_DISP32
},
6190 { "TLSCALL", { BFD_RELOC_386_TLS_DESC_CALL
,
6191 BFD_RELOC_X86_64_TLSDESC_CALL
},
6192 OPERAND_TYPE_IMM32_32S_DISP32
},
6200 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
6201 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
6204 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
6208 len
= strlen (gotrel
[j
].str
);
6209 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
6211 if (gotrel
[j
].rel
[object_64bit
] != 0)
6214 char *tmpbuf
, *past_reloc
;
6216 *rel
= gotrel
[j
].rel
[object_64bit
];
6222 if (flag_code
!= CODE_64BIT
)
6224 types
->bitfield
.imm32
= 1;
6225 types
->bitfield
.disp32
= 1;
6228 *types
= gotrel
[j
].types64
;
6231 if (GOT_symbol
== NULL
)
6232 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
6234 /* The length of the first part of our input line. */
6235 first
= cp
- input_line_pointer
;
6237 /* The second part goes from after the reloc token until
6238 (and including) an end_of_line char or comma. */
6239 past_reloc
= cp
+ 1 + len
;
6241 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
6243 second
= cp
+ 1 - past_reloc
;
6245 /* Allocate and copy string. The trailing NUL shouldn't
6246 be necessary, but be safe. */
6247 tmpbuf
= (char *) xmalloc (first
+ second
+ 2);
6248 memcpy (tmpbuf
, input_line_pointer
, first
);
6249 if (second
!= 0 && *past_reloc
!= ' ')
6250 /* Replace the relocation token with ' ', so that
6251 errors like foo@GOTOFF1 will be detected. */
6252 tmpbuf
[first
++] = ' ';
6253 memcpy (tmpbuf
+ first
, past_reloc
, second
);
6254 tmpbuf
[first
+ second
] = '\0';
6258 as_bad (_("@%s reloc is not supported with %d-bit output format"),
6259 gotrel
[j
].str
, 1 << (5 + object_64bit
));
6264 /* Might be a symbol version string. Don't as_bad here. */
6269 x86_cons (expressionS
*exp
, int size
)
6271 intel_syntax
= -intel_syntax
;
6273 if (size
== 4 || (object_64bit
&& size
== 8))
6275 /* Handle @GOTOFF and the like in an expression. */
6277 char *gotfree_input_line
;
6280 save
= input_line_pointer
;
6281 gotfree_input_line
= lex_got (&got_reloc
, &adjust
, NULL
);
6282 if (gotfree_input_line
)
6283 input_line_pointer
= gotfree_input_line
;
6287 if (gotfree_input_line
)
6289 /* expression () has merrily parsed up to the end of line,
6290 or a comma - in the wrong buffer. Transfer how far
6291 input_line_pointer has moved to the right buffer. */
6292 input_line_pointer
= (save
6293 + (input_line_pointer
- gotfree_input_line
)
6295 free (gotfree_input_line
);
6296 if (exp
->X_op
== O_constant
6297 || exp
->X_op
== O_absent
6298 || exp
->X_op
== O_illegal
6299 || exp
->X_op
== O_register
6300 || exp
->X_op
== O_big
)
6302 char c
= *input_line_pointer
;
6303 *input_line_pointer
= 0;
6304 as_bad (_("missing or invalid expression `%s'"), save
);
6305 *input_line_pointer
= c
;
6312 intel_syntax
= -intel_syntax
;
6315 i386_intel_simplify (exp
);
6320 signed_cons (int size
)
6322 if (flag_code
== CODE_64BIT
)
6330 pe_directive_secrel (dummy
)
6331 int dummy ATTRIBUTE_UNUSED
;
6338 if (exp
.X_op
== O_symbol
)
6339 exp
.X_op
= O_secrel
;
6341 emit_expr (&exp
, 4);
6343 while (*input_line_pointer
++ == ',');
6345 input_line_pointer
--;
6346 demand_empty_rest_of_line ();
6351 i386_immediate (char *imm_start
)
6353 char *save_input_line_pointer
;
6354 char *gotfree_input_line
;
6357 i386_operand_type types
;
6359 operand_type_set (&types
, ~0);
6361 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
6363 as_bad (_("at most %d immediate operands are allowed"),
6364 MAX_IMMEDIATE_OPERANDS
);
6368 exp
= &im_expressions
[i
.imm_operands
++];
6369 i
.op
[this_operand
].imms
= exp
;
6371 if (is_space_char (*imm_start
))
6374 save_input_line_pointer
= input_line_pointer
;
6375 input_line_pointer
= imm_start
;
6377 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
6378 if (gotfree_input_line
)
6379 input_line_pointer
= gotfree_input_line
;
6381 exp_seg
= expression (exp
);
6384 if (*input_line_pointer
)
6385 as_bad (_("junk `%s' after expression"), input_line_pointer
);
6387 input_line_pointer
= save_input_line_pointer
;
6388 if (gotfree_input_line
)
6390 free (gotfree_input_line
);
6392 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
6393 exp
->X_op
= O_illegal
;
6396 return i386_finalize_immediate (exp_seg
, exp
, types
, imm_start
);
6400 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
6401 i386_operand_type types
, const char *imm_start
)
6403 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_illegal
|| exp
->X_op
== O_big
)
6406 as_bad (_("missing or invalid immediate expression `%s'"),
6410 else if (exp
->X_op
== O_constant
)
6412 /* Size it properly later. */
6413 i
.types
[this_operand
].bitfield
.imm64
= 1;
6414 /* If BFD64, sign extend val. */
6415 if (!use_rela_relocations
6416 && (exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
6418 = (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
6420 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
6421 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
6422 && exp_seg
!= absolute_section
6423 && exp_seg
!= text_section
6424 && exp_seg
!= data_section
6425 && exp_seg
!= bss_section
6426 && exp_seg
!= undefined_section
6427 && !bfd_is_com_section (exp_seg
))
6429 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
6433 else if (!intel_syntax
&& exp
->X_op
== O_register
)
6436 as_bad (_("illegal immediate register operand %s"), imm_start
);
6441 /* This is an address. The size of the address will be
6442 determined later, depending on destination register,
6443 suffix, or the default for the section. */
6444 i
.types
[this_operand
].bitfield
.imm8
= 1;
6445 i
.types
[this_operand
].bitfield
.imm16
= 1;
6446 i
.types
[this_operand
].bitfield
.imm32
= 1;
6447 i
.types
[this_operand
].bitfield
.imm32s
= 1;
6448 i
.types
[this_operand
].bitfield
.imm64
= 1;
6449 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
6457 i386_scale (char *scale
)
6460 char *save
= input_line_pointer
;
6462 input_line_pointer
= scale
;
6463 val
= get_absolute_expression ();
6468 i
.log2_scale_factor
= 0;
6471 i
.log2_scale_factor
= 1;
6474 i
.log2_scale_factor
= 2;
6477 i
.log2_scale_factor
= 3;
6481 char sep
= *input_line_pointer
;
6483 *input_line_pointer
= '\0';
6484 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
6486 *input_line_pointer
= sep
;
6487 input_line_pointer
= save
;
6491 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
6493 as_warn (_("scale factor of %d without an index register"),
6494 1 << i
.log2_scale_factor
);
6495 i
.log2_scale_factor
= 0;
6497 scale
= input_line_pointer
;
6498 input_line_pointer
= save
;
6503 i386_displacement (char *disp_start
, char *disp_end
)
6507 char *save_input_line_pointer
;
6508 char *gotfree_input_line
;
6510 i386_operand_type bigdisp
, types
= anydisp
;
6513 if (i
.disp_operands
== MAX_MEMORY_OPERANDS
)
6515 as_bad (_("at most %d displacement operands are allowed"),
6516 MAX_MEMORY_OPERANDS
);
6520 operand_type_set (&bigdisp
, 0);
6521 if ((i
.types
[this_operand
].bitfield
.jumpabsolute
)
6522 || (!current_templates
->start
->opcode_modifier
.jump
6523 && !current_templates
->start
->opcode_modifier
.jumpdword
))
6525 bigdisp
.bitfield
.disp32
= 1;
6526 override
= (i
.prefix
[ADDR_PREFIX
] != 0);
6527 if (flag_code
== CODE_64BIT
)
6531 bigdisp
.bitfield
.disp32s
= 1;
6532 bigdisp
.bitfield
.disp64
= 1;
6535 else if ((flag_code
== CODE_16BIT
) ^ override
)
6537 bigdisp
.bitfield
.disp32
= 0;
6538 bigdisp
.bitfield
.disp16
= 1;
6543 /* For PC-relative branches, the width of the displacement
6544 is dependent upon data size, not address size. */
6545 override
= (i
.prefix
[DATA_PREFIX
] != 0);
6546 if (flag_code
== CODE_64BIT
)
6548 if (override
|| i
.suffix
== WORD_MNEM_SUFFIX
)
6549 bigdisp
.bitfield
.disp16
= 1;
6552 bigdisp
.bitfield
.disp32
= 1;
6553 bigdisp
.bitfield
.disp32s
= 1;
6559 override
= (i
.suffix
== (flag_code
!= CODE_16BIT
6561 : LONG_MNEM_SUFFIX
));
6562 bigdisp
.bitfield
.disp32
= 1;
6563 if ((flag_code
== CODE_16BIT
) ^ override
)
6565 bigdisp
.bitfield
.disp32
= 0;
6566 bigdisp
.bitfield
.disp16
= 1;
6570 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
6573 exp
= &disp_expressions
[i
.disp_operands
];
6574 i
.op
[this_operand
].disps
= exp
;
6576 save_input_line_pointer
= input_line_pointer
;
6577 input_line_pointer
= disp_start
;
6578 END_STRING_AND_SAVE (disp_end
);
6580 #ifndef GCC_ASM_O_HACK
6581 #define GCC_ASM_O_HACK 0
6584 END_STRING_AND_SAVE (disp_end
+ 1);
6585 if (i
.types
[this_operand
].bitfield
.baseIndex
6586 && displacement_string_end
[-1] == '+')
6588 /* This hack is to avoid a warning when using the "o"
6589 constraint within gcc asm statements.
6592 #define _set_tssldt_desc(n,addr,limit,type) \
6593 __asm__ __volatile__ ( \
6595 "movw %w1,2+%0\n\t" \
6597 "movb %b1,4+%0\n\t" \
6598 "movb %4,5+%0\n\t" \
6599 "movb $0,6+%0\n\t" \
6600 "movb %h1,7+%0\n\t" \
6602 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
6604 This works great except that the output assembler ends
6605 up looking a bit weird if it turns out that there is
6606 no offset. You end up producing code that looks like:
6619 So here we provide the missing zero. */
6621 *displacement_string_end
= '0';
6624 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
6625 if (gotfree_input_line
)
6626 input_line_pointer
= gotfree_input_line
;
6628 exp_seg
= expression (exp
);
6631 if (*input_line_pointer
)
6632 as_bad (_("junk `%s' after expression"), input_line_pointer
);
6634 RESTORE_END_STRING (disp_end
+ 1);
6636 input_line_pointer
= save_input_line_pointer
;
6637 if (gotfree_input_line
)
6639 free (gotfree_input_line
);
6641 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
6642 exp
->X_op
= O_illegal
;
6645 ret
= i386_finalize_displacement (exp_seg
, exp
, types
, disp_start
);
6647 RESTORE_END_STRING (disp_end
);
6653 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
6654 i386_operand_type types
, const char *disp_start
)
6656 i386_operand_type bigdisp
;
6659 /* We do this to make sure that the section symbol is in
6660 the symbol table. We will ultimately change the relocation
6661 to be relative to the beginning of the section. */
6662 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
6663 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
6664 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
6666 if (exp
->X_op
!= O_symbol
)
6669 if (S_IS_LOCAL (exp
->X_add_symbol
)
6670 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
)
6671 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
6672 exp
->X_op
= O_subtract
;
6673 exp
->X_op_symbol
= GOT_symbol
;
6674 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
6675 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
6676 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
6677 i
.reloc
[this_operand
] = BFD_RELOC_64
;
6679 i
.reloc
[this_operand
] = BFD_RELOC_32
;
6682 else if (exp
->X_op
== O_absent
6683 || exp
->X_op
== O_illegal
6684 || exp
->X_op
== O_big
)
6687 as_bad (_("missing or invalid displacement expression `%s'"),
6692 else if (flag_code
== CODE_64BIT
6693 && !i
.prefix
[ADDR_PREFIX
]
6694 && exp
->X_op
== O_constant
)
6696 /* Since displacement is signed extended to 64bit, don't allow
6697 disp32 and turn off disp32s if they are out of range. */
6698 i
.types
[this_operand
].bitfield
.disp32
= 0;
6699 if (!fits_in_signed_long (exp
->X_add_number
))
6701 i
.types
[this_operand
].bitfield
.disp32s
= 0;
6702 if (i
.types
[this_operand
].bitfield
.baseindex
)
6704 as_bad (_("0x%lx out range of signed 32bit displacement"),
6705 (long) exp
->X_add_number
);
6711 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
6712 else if (exp
->X_op
!= O_constant
6713 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
6714 && exp_seg
!= absolute_section
6715 && exp_seg
!= text_section
6716 && exp_seg
!= data_section
6717 && exp_seg
!= bss_section
6718 && exp_seg
!= undefined_section
6719 && !bfd_is_com_section (exp_seg
))
6721 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
6726 /* Check if this is a displacement only operand. */
6727 bigdisp
= i
.types
[this_operand
];
6728 bigdisp
.bitfield
.disp8
= 0;
6729 bigdisp
.bitfield
.disp16
= 0;
6730 bigdisp
.bitfield
.disp32
= 0;
6731 bigdisp
.bitfield
.disp32s
= 0;
6732 bigdisp
.bitfield
.disp64
= 0;
6733 if (operand_type_all_zero (&bigdisp
))
6734 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
6740 /* Make sure the memory operand we've been dealt is valid.
6741 Return 1 on success, 0 on a failure. */
6744 i386_index_check (const char *operand_string
)
6747 const char *kind
= "base/index";
6748 #if INFER_ADDR_PREFIX
6754 if (current_templates
->start
->opcode_modifier
.isstring
6755 && !current_templates
->start
->opcode_modifier
.immext
6756 && (current_templates
->end
[-1].opcode_modifier
.isstring
6759 /* Memory operands of string insns are special in that they only allow
6760 a single register (rDI, rSI, or rBX) as their memory address. */
6761 unsigned int expected
;
6763 kind
= "string address";
6765 if (current_templates
->start
->opcode_modifier
.w
)
6767 i386_operand_type type
= current_templates
->end
[-1].operand_types
[0];
6769 if (!type
.bitfield
.baseindex
6770 || ((!i
.mem_operands
!= !intel_syntax
)
6771 && current_templates
->end
[-1].operand_types
[1]
6772 .bitfield
.baseindex
))
6773 type
= current_templates
->end
[-1].operand_types
[1];
6774 expected
= type
.bitfield
.esseg
? 7 /* rDI */ : 6 /* rSI */;
6777 expected
= 3 /* rBX */;
6779 if (!i
.base_reg
|| i
.index_reg
6780 || operand_type_check (i
.types
[this_operand
], disp
))
6782 else if (!(flag_code
== CODE_64BIT
6783 ? i
.prefix
[ADDR_PREFIX
]
6784 ? i
.base_reg
->reg_type
.bitfield
.reg32
6785 : i
.base_reg
->reg_type
.bitfield
.reg64
6786 : (flag_code
== CODE_16BIT
) ^ !i
.prefix
[ADDR_PREFIX
]
6787 ? i
.base_reg
->reg_type
.bitfield
.reg32
6788 : i
.base_reg
->reg_type
.bitfield
.reg16
))
6790 else if (i
.base_reg
->reg_num
!= expected
)
6797 for (j
= 0; j
< i386_regtab_size
; ++j
)
6798 if ((flag_code
== CODE_64BIT
6799 ? i
.prefix
[ADDR_PREFIX
]
6800 ? i386_regtab
[j
].reg_type
.bitfield
.reg32
6801 : i386_regtab
[j
].reg_type
.bitfield
.reg64
6802 : (flag_code
== CODE_16BIT
) ^ !i
.prefix
[ADDR_PREFIX
]
6803 ? i386_regtab
[j
].reg_type
.bitfield
.reg32
6804 : i386_regtab
[j
].reg_type
.bitfield
.reg16
)
6805 && i386_regtab
[j
].reg_num
== expected
)
6807 gas_assert (j
< i386_regtab_size
);
6808 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
6810 intel_syntax
? '[' : '(',
6812 i386_regtab
[j
].reg_name
,
6813 intel_syntax
? ']' : ')');
6817 else if (flag_code
== CODE_64BIT
)
6820 && ((i
.prefix
[ADDR_PREFIX
] == 0
6821 && !i
.base_reg
->reg_type
.bitfield
.reg64
)
6822 || (i
.prefix
[ADDR_PREFIX
]
6823 && !i
.base_reg
->reg_type
.bitfield
.reg32
))
6825 || i
.base_reg
->reg_num
!=
6826 (i
.prefix
[ADDR_PREFIX
] == 0 ? RegRip
: RegEip
)))
6828 && (!i
.index_reg
->reg_type
.bitfield
.baseindex
6829 || (i
.prefix
[ADDR_PREFIX
] == 0
6830 && i
.index_reg
->reg_num
!= RegRiz
6831 && !i
.index_reg
->reg_type
.bitfield
.reg64
6833 || (i
.prefix
[ADDR_PREFIX
]
6834 && i
.index_reg
->reg_num
!= RegEiz
6835 && !i
.index_reg
->reg_type
.bitfield
.reg32
))))
6840 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[ADDR_PREFIX
] != 0))
6844 && (!i
.base_reg
->reg_type
.bitfield
.reg16
6845 || !i
.base_reg
->reg_type
.bitfield
.baseindex
))
6847 && (!i
.index_reg
->reg_type
.bitfield
.reg16
6848 || !i
.index_reg
->reg_type
.bitfield
.baseindex
6850 && i
.base_reg
->reg_num
< 6
6851 && i
.index_reg
->reg_num
>= 6
6852 && i
.log2_scale_factor
== 0))))
6859 && !i
.base_reg
->reg_type
.bitfield
.reg32
)
6861 && ((!i
.index_reg
->reg_type
.bitfield
.reg32
6862 && i
.index_reg
->reg_num
!= RegEiz
)
6863 || !i
.index_reg
->reg_type
.bitfield
.baseindex
)))
6869 #if INFER_ADDR_PREFIX
6870 if (!i
.mem_operands
&& !i
.prefix
[ADDR_PREFIX
])
6872 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
6874 /* Change the size of any displacement too. At most one of
6875 Disp16 or Disp32 is set.
6876 FIXME. There doesn't seem to be any real need for separate
6877 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
6878 Removing them would probably clean up the code quite a lot. */
6879 if (flag_code
!= CODE_64BIT
6880 && (i
.types
[this_operand
].bitfield
.disp16
6881 || i
.types
[this_operand
].bitfield
.disp32
))
6882 i
.types
[this_operand
]
6883 = operand_type_xor (i
.types
[this_operand
], disp16_32
);
6888 as_bad (_("`%s' is not a valid %s expression"),
6893 as_bad (_("`%s' is not a valid %s-bit %s expression"),
6895 flag_code_names
[i
.prefix
[ADDR_PREFIX
]
6896 ? flag_code
== CODE_32BIT
6905 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
6909 i386_att_operand (char *operand_string
)
6913 char *op_string
= operand_string
;
6915 if (is_space_char (*op_string
))
6918 /* We check for an absolute prefix (differentiating,
6919 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
6920 if (*op_string
== ABSOLUTE_PREFIX
)
6923 if (is_space_char (*op_string
))
6925 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
6928 /* Check if operand is a register. */
6929 if ((r
= parse_register (op_string
, &end_op
)) != NULL
)
6931 i386_operand_type temp
;
6933 /* Check for a segment override by searching for ':' after a
6934 segment register. */
6936 if (is_space_char (*op_string
))
6938 if (*op_string
== ':'
6939 && (r
->reg_type
.bitfield
.sreg2
6940 || r
->reg_type
.bitfield
.sreg3
))
6945 i
.seg
[i
.mem_operands
] = &es
;
6948 i
.seg
[i
.mem_operands
] = &cs
;
6951 i
.seg
[i
.mem_operands
] = &ss
;
6954 i
.seg
[i
.mem_operands
] = &ds
;
6957 i
.seg
[i
.mem_operands
] = &fs
;
6960 i
.seg
[i
.mem_operands
] = &gs
;
6964 /* Skip the ':' and whitespace. */
6966 if (is_space_char (*op_string
))
6969 if (!is_digit_char (*op_string
)
6970 && !is_identifier_char (*op_string
)
6971 && *op_string
!= '('
6972 && *op_string
!= ABSOLUTE_PREFIX
)
6974 as_bad (_("bad memory operand `%s'"), op_string
);
6977 /* Handle case of %es:*foo. */
6978 if (*op_string
== ABSOLUTE_PREFIX
)
6981 if (is_space_char (*op_string
))
6983 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
6985 goto do_memory_reference
;
6989 as_bad (_("junk `%s' after register"), op_string
);
6993 temp
.bitfield
.baseindex
= 0;
6994 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
6996 i
.types
[this_operand
].bitfield
.unspecified
= 0;
6997 i
.op
[this_operand
].regs
= r
;
7000 else if (*op_string
== REGISTER_PREFIX
)
7002 as_bad (_("bad register name `%s'"), op_string
);
7005 else if (*op_string
== IMMEDIATE_PREFIX
)
7008 if (i
.types
[this_operand
].bitfield
.jumpabsolute
)
7010 as_bad (_("immediate operand illegal with absolute jump"));
7013 if (!i386_immediate (op_string
))
7016 else if (is_digit_char (*op_string
)
7017 || is_identifier_char (*op_string
)
7018 || *op_string
== '(')
7020 /* This is a memory reference of some sort. */
7023 /* Start and end of displacement string expression (if found). */
7024 char *displacement_string_start
;
7025 char *displacement_string_end
;
7027 do_memory_reference
:
7028 if ((i
.mem_operands
== 1
7029 && !current_templates
->start
->opcode_modifier
.isstring
)
7030 || i
.mem_operands
== 2)
7032 as_bad (_("too many memory references for `%s'"),
7033 current_templates
->start
->name
);
7037 /* Check for base index form. We detect the base index form by
7038 looking for an ')' at the end of the operand, searching
7039 for the '(' matching it, and finding a REGISTER_PREFIX or ','
7041 base_string
= op_string
+ strlen (op_string
);
7044 if (is_space_char (*base_string
))
7047 /* If we only have a displacement, set-up for it to be parsed later. */
7048 displacement_string_start
= op_string
;
7049 displacement_string_end
= base_string
+ 1;
7051 if (*base_string
== ')')
7054 unsigned int parens_balanced
= 1;
7055 /* We've already checked that the number of left & right ()'s are
7056 equal, so this loop will not be infinite. */
7060 if (*base_string
== ')')
7062 if (*base_string
== '(')
7065 while (parens_balanced
);
7067 temp_string
= base_string
;
7069 /* Skip past '(' and whitespace. */
7071 if (is_space_char (*base_string
))
7074 if (*base_string
== ','
7075 || ((i
.base_reg
= parse_register (base_string
, &end_op
))
7078 displacement_string_end
= temp_string
;
7080 i
.types
[this_operand
].bitfield
.baseindex
= 1;
7084 base_string
= end_op
;
7085 if (is_space_char (*base_string
))
7089 /* There may be an index reg or scale factor here. */
7090 if (*base_string
== ',')
7093 if (is_space_char (*base_string
))
7096 if ((i
.index_reg
= parse_register (base_string
, &end_op
))
7099 base_string
= end_op
;
7100 if (is_space_char (*base_string
))
7102 if (*base_string
== ',')
7105 if (is_space_char (*base_string
))
7108 else if (*base_string
!= ')')
7110 as_bad (_("expecting `,' or `)' "
7111 "after index register in `%s'"),
7116 else if (*base_string
== REGISTER_PREFIX
)
7118 as_bad (_("bad register name `%s'"), base_string
);
7122 /* Check for scale factor. */
7123 if (*base_string
!= ')')
7125 char *end_scale
= i386_scale (base_string
);
7130 base_string
= end_scale
;
7131 if (is_space_char (*base_string
))
7133 if (*base_string
!= ')')
7135 as_bad (_("expecting `)' "
7136 "after scale factor in `%s'"),
7141 else if (!i
.index_reg
)
7143 as_bad (_("expecting index register or scale factor "
7144 "after `,'; got '%c'"),
7149 else if (*base_string
!= ')')
7151 as_bad (_("expecting `,' or `)' "
7152 "after base register in `%s'"),
7157 else if (*base_string
== REGISTER_PREFIX
)
7159 as_bad (_("bad register name `%s'"), base_string
);
7164 /* If there's an expression beginning the operand, parse it,
7165 assuming displacement_string_start and
7166 displacement_string_end are meaningful. */
7167 if (displacement_string_start
!= displacement_string_end
)
7169 if (!i386_displacement (displacement_string_start
,
7170 displacement_string_end
))
7174 /* Special case for (%dx) while doing input/output op. */
7176 && operand_type_equal (&i
.base_reg
->reg_type
,
7177 ®16_inoutportreg
)
7179 && i
.log2_scale_factor
== 0
7180 && i
.seg
[i
.mem_operands
] == 0
7181 && !operand_type_check (i
.types
[this_operand
], disp
))
7183 i
.types
[this_operand
] = inoutportreg
;
7187 if (i386_index_check (operand_string
) == 0)
7189 i
.types
[this_operand
].bitfield
.mem
= 1;
7194 /* It's not a memory operand; argh! */
7195 as_bad (_("invalid char %s beginning operand %d `%s'"),
7196 output_invalid (*op_string
),
7201 return 1; /* Normal return. */
7204 /* md_estimate_size_before_relax()
7206 Called just before relax() for rs_machine_dependent frags. The x86
7207 assembler uses these frags to handle variable size jump
7210 Any symbol that is now undefined will not become defined.
7211 Return the correct fr_subtype in the frag.
7212 Return the initial "guess for variable size of frag" to caller.
7213 The guess is actually the growth beyond the fixed part. Whatever
7214 we do to grow the fixed or variable part contributes to our
7218 md_estimate_size_before_relax (fragP
, segment
)
7222 /* We've already got fragP->fr_subtype right; all we have to do is
7223 check for un-relaxable symbols. On an ELF system, we can't relax
7224 an externally visible symbol, because it may be overridden by a
7226 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
7227 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7229 && (S_IS_EXTERNAL (fragP
->fr_symbol
)
7230 || S_IS_WEAK (fragP
->fr_symbol
)
7231 || ((symbol_get_bfdsym (fragP
->fr_symbol
)->flags
7232 & BSF_GNU_INDIRECT_FUNCTION
))))
7234 #if defined (OBJ_COFF) && defined (TE_PE)
7235 || (OUTPUT_FLAVOR
== bfd_target_coff_flavour
7236 && S_IS_WEAK (fragP
->fr_symbol
))
7240 /* Symbol is undefined in this segment, or we need to keep a
7241 reloc so that weak symbols can be overridden. */
7242 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
7243 enum bfd_reloc_code_real reloc_type
;
7244 unsigned char *opcode
;
7247 if (fragP
->fr_var
!= NO_RELOC
)
7248 reloc_type
= (enum bfd_reloc_code_real
) fragP
->fr_var
;
7250 reloc_type
= BFD_RELOC_16_PCREL
;
7252 reloc_type
= BFD_RELOC_32_PCREL
;
7254 old_fr_fix
= fragP
->fr_fix
;
7255 opcode
= (unsigned char *) fragP
->fr_opcode
;
7257 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
7260 /* Make jmp (0xeb) a (d)word displacement jump. */
7262 fragP
->fr_fix
+= size
;
7263 fix_new (fragP
, old_fr_fix
, size
,
7265 fragP
->fr_offset
, 1,
7271 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
7273 /* Negate the condition, and branch past an
7274 unconditional jump. */
7277 /* Insert an unconditional jump. */
7279 /* We added two extra opcode bytes, and have a two byte
7281 fragP
->fr_fix
+= 2 + 2;
7282 fix_new (fragP
, old_fr_fix
+ 2, 2,
7284 fragP
->fr_offset
, 1,
7291 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
7296 fixP
= fix_new (fragP
, old_fr_fix
, 1,
7298 fragP
->fr_offset
, 1,
7300 fixP
->fx_signed
= 1;
7304 /* This changes the byte-displacement jump 0x7N
7305 to the (d)word-displacement jump 0x0f,0x8N. */
7306 opcode
[1] = opcode
[0] + 0x10;
7307 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
7308 /* We've added an opcode byte. */
7309 fragP
->fr_fix
+= 1 + size
;
7310 fix_new (fragP
, old_fr_fix
+ 1, size
,
7312 fragP
->fr_offset
, 1,
7317 BAD_CASE (fragP
->fr_subtype
);
7321 return fragP
->fr_fix
- old_fr_fix
;
7324 /* Guess size depending on current relax state. Initially the relax
7325 state will correspond to a short jump and we return 1, because
7326 the variable part of the frag (the branch offset) is one byte
7327 long. However, we can relax a section more than once and in that
7328 case we must either set fr_subtype back to the unrelaxed state,
7329 or return the value for the appropriate branch. */
7330 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
7333 /* Called after relax() is finished.
7335 In: Address of frag.
7336 fr_type == rs_machine_dependent.
7337 fr_subtype is what the address relaxed to.
7339 Out: Any fixSs and constants are set up.
7340 Caller will turn frag into a ".space 0". */
7343 md_convert_frag (abfd
, sec
, fragP
)
7344 bfd
*abfd ATTRIBUTE_UNUSED
;
7345 segT sec ATTRIBUTE_UNUSED
;
7348 unsigned char *opcode
;
7349 unsigned char *where_to_put_displacement
= NULL
;
7350 offsetT target_address
;
7351 offsetT opcode_address
;
7352 unsigned int extension
= 0;
7353 offsetT displacement_from_opcode_start
;
7355 opcode
= (unsigned char *) fragP
->fr_opcode
;
7357 /* Address we want to reach in file space. */
7358 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
7360 /* Address opcode resides at in file space. */
7361 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
7363 /* Displacement from opcode start to fill into instruction. */
7364 displacement_from_opcode_start
= target_address
- opcode_address
;
7366 if ((fragP
->fr_subtype
& BIG
) == 0)
7368 /* Don't have to change opcode. */
7369 extension
= 1; /* 1 opcode + 1 displacement */
7370 where_to_put_displacement
= &opcode
[1];
7374 if (no_cond_jump_promotion
7375 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
7376 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
7377 _("long jump required"));
7379 switch (fragP
->fr_subtype
)
7381 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
7382 extension
= 4; /* 1 opcode + 4 displacement */
7384 where_to_put_displacement
= &opcode
[1];
7387 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
7388 extension
= 2; /* 1 opcode + 2 displacement */
7390 where_to_put_displacement
= &opcode
[1];
7393 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
7394 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
7395 extension
= 5; /* 2 opcode + 4 displacement */
7396 opcode
[1] = opcode
[0] + 0x10;
7397 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
7398 where_to_put_displacement
= &opcode
[2];
7401 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
7402 extension
= 3; /* 2 opcode + 2 displacement */
7403 opcode
[1] = opcode
[0] + 0x10;
7404 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
7405 where_to_put_displacement
= &opcode
[2];
7408 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
7413 where_to_put_displacement
= &opcode
[3];
7417 BAD_CASE (fragP
->fr_subtype
);
7422 /* If size if less then four we are sure that the operand fits,
7423 but if it's 4, then it could be that the displacement is larger
7425 if (DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
) == 4
7427 && ((addressT
) (displacement_from_opcode_start
- extension
7428 + ((addressT
) 1 << 31))
7429 > (((addressT
) 2 << 31) - 1)))
7431 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
7432 _("jump target out of range"));
7433 /* Make us emit 0. */
7434 displacement_from_opcode_start
= extension
;
7436 /* Now put displacement after opcode. */
7437 md_number_to_chars ((char *) where_to_put_displacement
,
7438 (valueT
) (displacement_from_opcode_start
- extension
),
7439 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
7440 fragP
->fr_fix
+= extension
;
7443 /* Apply a fixup (fixS) to segment data, once it has been determined
7444 by our caller that we have all the info we need to fix it up.
7446 On the 386, immediates, displacements, and data pointers are all in
7447 the same (little-endian) format, so we don't need to care about which
7451 md_apply_fix (fixP
, valP
, seg
)
7452 /* The fix we're to put in. */
7454 /* Pointer to the value of the bits. */
7456 /* Segment fix is from. */
7457 segT seg ATTRIBUTE_UNUSED
;
7459 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
7460 valueT value
= *valP
;
7462 #if !defined (TE_Mach)
7465 switch (fixP
->fx_r_type
)
7471 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
7474 case BFD_RELOC_X86_64_32S
:
7475 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
7478 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
7481 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
7486 if (fixP
->fx_addsy
!= NULL
7487 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
7488 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
7489 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
7490 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
7491 && !use_rela_relocations
)
7493 /* This is a hack. There should be a better way to handle this.
7494 This covers for the fact that bfd_install_relocation will
7495 subtract the current location (for partial_inplace, PC relative
7496 relocations); see more below. */
7500 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
7503 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
7505 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7508 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
7511 || (symbol_section_p (fixP
->fx_addsy
)
7512 && sym_seg
!= absolute_section
))
7513 && !generic_force_reloc (fixP
))
7515 /* Yes, we add the values in twice. This is because
7516 bfd_install_relocation subtracts them out again. I think
7517 bfd_install_relocation is broken, but I don't dare change
7519 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
7523 #if defined (OBJ_COFF) && defined (TE_PE)
7524 /* For some reason, the PE format does not store a
7525 section address offset for a PC relative symbol. */
7526 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
7527 || S_IS_WEAK (fixP
->fx_addsy
))
7528 value
+= md_pcrel_from (fixP
);
7531 #if defined (OBJ_COFF) && defined (TE_PE)
7532 if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
7534 value
-= S_GET_VALUE (fixP
->fx_addsy
);
7538 /* Fix a few things - the dynamic linker expects certain values here,
7539 and we must not disappoint it. */
7540 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7541 if (IS_ELF
&& fixP
->fx_addsy
)
7542 switch (fixP
->fx_r_type
)
7544 case BFD_RELOC_386_PLT32
:
7545 case BFD_RELOC_X86_64_PLT32
:
7546 /* Make the jump instruction point to the address of the operand. At
7547 runtime we merely add the offset to the actual PLT entry. */
7551 case BFD_RELOC_386_TLS_GD
:
7552 case BFD_RELOC_386_TLS_LDM
:
7553 case BFD_RELOC_386_TLS_IE_32
:
7554 case BFD_RELOC_386_TLS_IE
:
7555 case BFD_RELOC_386_TLS_GOTIE
:
7556 case BFD_RELOC_386_TLS_GOTDESC
:
7557 case BFD_RELOC_X86_64_TLSGD
:
7558 case BFD_RELOC_X86_64_TLSLD
:
7559 case BFD_RELOC_X86_64_GOTTPOFF
:
7560 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
7561 value
= 0; /* Fully resolved at runtime. No addend. */
7563 case BFD_RELOC_386_TLS_LE
:
7564 case BFD_RELOC_386_TLS_LDO_32
:
7565 case BFD_RELOC_386_TLS_LE_32
:
7566 case BFD_RELOC_X86_64_DTPOFF32
:
7567 case BFD_RELOC_X86_64_DTPOFF64
:
7568 case BFD_RELOC_X86_64_TPOFF32
:
7569 case BFD_RELOC_X86_64_TPOFF64
:
7570 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
7573 case BFD_RELOC_386_TLS_DESC_CALL
:
7574 case BFD_RELOC_X86_64_TLSDESC_CALL
:
7575 value
= 0; /* Fully resolved at runtime. No addend. */
7576 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
7580 case BFD_RELOC_386_GOT32
:
7581 case BFD_RELOC_X86_64_GOT32
:
7582 value
= 0; /* Fully resolved at runtime. No addend. */
7585 case BFD_RELOC_VTABLE_INHERIT
:
7586 case BFD_RELOC_VTABLE_ENTRY
:
7593 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
7595 #endif /* !defined (TE_Mach) */
7597 /* Are we finished with this relocation now? */
7598 if (fixP
->fx_addsy
== NULL
)
7600 #if defined (OBJ_COFF) && defined (TE_PE)
7601 else if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
7604 /* Remember value for tc_gen_reloc. */
7605 fixP
->fx_addnumber
= value
;
7606 /* Clear out the frag for now. */
7610 else if (use_rela_relocations
)
7612 fixP
->fx_no_overflow
= 1;
7613 /* Remember value for tc_gen_reloc. */
7614 fixP
->fx_addnumber
= value
;
7618 md_number_to_chars (p
, value
, fixP
->fx_size
);
7622 md_atof (int type
, char *litP
, int *sizeP
)
7624 /* This outputs the LITTLENUMs in REVERSE order;
7625 in accord with the bigendian 386. */
7626 return ieee_md_atof (type
, litP
, sizeP
, FALSE
);
7629 static char output_invalid_buf
[sizeof (unsigned char) * 2 + 6];
7632 output_invalid (int c
)
7635 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
7638 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
7639 "(0x%x)", (unsigned char) c
);
7640 return output_invalid_buf
;
7643 /* REG_STRING starts *before* REGISTER_PREFIX. */
7645 static const reg_entry
*
7646 parse_real_register (char *reg_string
, char **end_op
)
7648 char *s
= reg_string
;
7650 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
7653 /* Skip possible REGISTER_PREFIX and possible whitespace. */
7654 if (*s
== REGISTER_PREFIX
)
7657 if (is_space_char (*s
))
7661 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
7663 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
7664 return (const reg_entry
*) NULL
;
7668 /* For naked regs, make sure that we are not dealing with an identifier.
7669 This prevents confusing an identifier like `eax_var' with register
7671 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
7672 return (const reg_entry
*) NULL
;
7676 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
7678 /* Handle floating point regs, allowing spaces in the (i) part. */
7679 if (r
== i386_regtab
/* %st is first entry of table */)
7681 if (is_space_char (*s
))
7686 if (is_space_char (*s
))
7688 if (*s
>= '0' && *s
<= '7')
7692 if (is_space_char (*s
))
7697 r
= (const reg_entry
*) hash_find (reg_hash
, "st(0)");
7702 /* We have "%st(" then garbage. */
7703 return (const reg_entry
*) NULL
;
7707 if (r
== NULL
|| allow_pseudo_reg
)
7710 if (operand_type_all_zero (&r
->reg_type
))
7711 return (const reg_entry
*) NULL
;
7713 if ((r
->reg_type
.bitfield
.reg32
7714 || r
->reg_type
.bitfield
.sreg3
7715 || r
->reg_type
.bitfield
.control
7716 || r
->reg_type
.bitfield
.debug
7717 || r
->reg_type
.bitfield
.test
)
7718 && !cpu_arch_flags
.bitfield
.cpui386
)
7719 return (const reg_entry
*) NULL
;
7721 if (r
->reg_type
.bitfield
.floatreg
7722 && !cpu_arch_flags
.bitfield
.cpu8087
7723 && !cpu_arch_flags
.bitfield
.cpu287
7724 && !cpu_arch_flags
.bitfield
.cpu387
)
7725 return (const reg_entry
*) NULL
;
7727 if (r
->reg_type
.bitfield
.regmmx
&& !cpu_arch_flags
.bitfield
.cpummx
)
7728 return (const reg_entry
*) NULL
;
7730 if (r
->reg_type
.bitfield
.regxmm
&& !cpu_arch_flags
.bitfield
.cpusse
)
7731 return (const reg_entry
*) NULL
;
7733 if (r
->reg_type
.bitfield
.regymm
&& !cpu_arch_flags
.bitfield
.cpuavx
)
7734 return (const reg_entry
*) NULL
;
7736 /* Don't allow fake index register unless allow_index_reg isn't 0. */
7737 if (!allow_index_reg
7738 && (r
->reg_num
== RegEiz
|| r
->reg_num
== RegRiz
))
7739 return (const reg_entry
*) NULL
;
7741 if (((r
->reg_flags
& (RegRex64
| RegRex
))
7742 || r
->reg_type
.bitfield
.reg64
)
7743 && (!cpu_arch_flags
.bitfield
.cpulm
7744 || !operand_type_equal (&r
->reg_type
, &control
))
7745 && flag_code
!= CODE_64BIT
)
7746 return (const reg_entry
*) NULL
;
7748 if (r
->reg_type
.bitfield
.sreg3
&& r
->reg_num
== RegFlat
&& !intel_syntax
)
7749 return (const reg_entry
*) NULL
;
7754 /* REG_STRING starts *before* REGISTER_PREFIX. */
7756 static const reg_entry
*
7757 parse_register (char *reg_string
, char **end_op
)
7761 if (*reg_string
== REGISTER_PREFIX
|| allow_naked_reg
)
7762 r
= parse_real_register (reg_string
, end_op
);
7767 char *save
= input_line_pointer
;
7771 input_line_pointer
= reg_string
;
7772 c
= get_symbol_end ();
7773 symbolP
= symbol_find (reg_string
);
7774 if (symbolP
&& S_GET_SEGMENT (symbolP
) == reg_section
)
7776 const expressionS
*e
= symbol_get_value_expression (symbolP
);
7778 know (e
->X_op
== O_register
);
7779 know (e
->X_add_number
>= 0
7780 && (valueT
) e
->X_add_number
< i386_regtab_size
);
7781 r
= i386_regtab
+ e
->X_add_number
;
7782 *end_op
= input_line_pointer
;
7784 *input_line_pointer
= c
;
7785 input_line_pointer
= save
;
7791 i386_parse_name (char *name
, expressionS
*e
, char *nextcharP
)
7794 char *end
= input_line_pointer
;
7797 r
= parse_register (name
, &input_line_pointer
);
7798 if (r
&& end
<= input_line_pointer
)
7800 *nextcharP
= *input_line_pointer
;
7801 *input_line_pointer
= 0;
7802 e
->X_op
= O_register
;
7803 e
->X_add_number
= r
- i386_regtab
;
7806 input_line_pointer
= end
;
7808 return intel_syntax
? i386_intel_parse_name (name
, e
) : 0;
7812 md_operand (expressionS
*e
)
7817 switch (*input_line_pointer
)
7819 case REGISTER_PREFIX
:
7820 r
= parse_real_register (input_line_pointer
, &end
);
7823 e
->X_op
= O_register
;
7824 e
->X_add_number
= r
- i386_regtab
;
7825 input_line_pointer
= end
;
7830 gas_assert (intel_syntax
);
7831 end
= input_line_pointer
++;
7833 if (*input_line_pointer
== ']')
7835 ++input_line_pointer
;
7836 e
->X_op_symbol
= make_expr_symbol (e
);
7837 e
->X_add_symbol
= NULL
;
7838 e
->X_add_number
= 0;
7844 input_line_pointer
= end
;
7851 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7852 const char *md_shortopts
= "kVQ:sqn";
7854 const char *md_shortopts
= "qn";
7857 #define OPTION_32 (OPTION_MD_BASE + 0)
7858 #define OPTION_64 (OPTION_MD_BASE + 1)
7859 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
7860 #define OPTION_MARCH (OPTION_MD_BASE + 3)
7861 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
7862 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
7863 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
7864 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
7865 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
7866 #define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
7867 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
7868 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
7870 struct option md_longopts
[] =
7872 {"32", no_argument
, NULL
, OPTION_32
},
7873 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
7874 || defined (TE_PE) || defined (TE_PEP))
7875 {"64", no_argument
, NULL
, OPTION_64
},
7877 {"divide", no_argument
, NULL
, OPTION_DIVIDE
},
7878 {"march", required_argument
, NULL
, OPTION_MARCH
},
7879 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
7880 {"mmnemonic", required_argument
, NULL
, OPTION_MMNEMONIC
},
7881 {"msyntax", required_argument
, NULL
, OPTION_MSYNTAX
},
7882 {"mindex-reg", no_argument
, NULL
, OPTION_MINDEX_REG
},
7883 {"mnaked-reg", no_argument
, NULL
, OPTION_MNAKED_REG
},
7884 {"mold-gcc", no_argument
, NULL
, OPTION_MOLD_GCC
},
7885 {"msse2avx", no_argument
, NULL
, OPTION_MSSE2AVX
},
7886 {"msse-check", required_argument
, NULL
, OPTION_MSSE_CHECK
},
7887 {NULL
, no_argument
, NULL
, 0}
7889 size_t md_longopts_size
= sizeof (md_longopts
);
7892 md_parse_option (int c
, char *arg
)
7900 optimize_align_code
= 0;
7907 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7908 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
7909 should be emitted or not. FIXME: Not implemented. */
7913 /* -V: SVR4 argument to print version ID. */
7915 print_version_id ();
7918 /* -k: Ignore for FreeBSD compatibility. */
7923 /* -s: On i386 Solaris, this tells the native assembler to use
7924 .stab instead of .stab.excl. We always use .stab anyhow. */
7927 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
7928 || defined (TE_PE) || defined (TE_PEP))
7931 const char **list
, **l
;
7933 list
= bfd_target_list ();
7934 for (l
= list
; *l
!= NULL
; l
++)
7935 if (CONST_STRNEQ (*l
, "elf64-x86-64")
7936 || strcmp (*l
, "coff-x86-64") == 0
7937 || strcmp (*l
, "pe-x86-64") == 0
7938 || strcmp (*l
, "pei-x86-64") == 0)
7940 default_arch
= "x86_64";
7944 as_fatal (_("No compiled in support for x86_64"));
7951 default_arch
= "i386";
7955 #ifdef SVR4_COMMENT_CHARS
7960 n
= (char *) xmalloc (strlen (i386_comment_chars
) + 1);
7962 for (s
= i386_comment_chars
; *s
!= '\0'; s
++)
7966 i386_comment_chars
= n
;
7972 arch
= xstrdup (arg
);
7976 as_fatal (_("Invalid -march= option: `%s'"), arg
);
7977 next
= strchr (arch
, '+');
7980 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
7982 if (strcmp (arch
, cpu_arch
[j
].name
) == 0)
7985 cpu_arch_name
= cpu_arch
[j
].name
;
7986 cpu_sub_arch_name
= NULL
;
7987 cpu_arch_flags
= cpu_arch
[j
].flags
;
7988 cpu_arch_isa
= cpu_arch
[j
].type
;
7989 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
7990 if (!cpu_arch_tune_set
)
7992 cpu_arch_tune
= cpu_arch_isa
;
7993 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
7997 else if (*cpu_arch
[j
].name
== '.'
7998 && strcmp (arch
, cpu_arch
[j
].name
+ 1) == 0)
8000 /* ISA entension. */
8001 i386_cpu_flags flags
;
8003 if (strncmp (arch
, "no", 2))
8004 flags
= cpu_flags_or (cpu_arch_flags
,
8007 flags
= cpu_flags_and_not (cpu_arch_flags
,
8009 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
8011 if (cpu_sub_arch_name
)
8013 char *name
= cpu_sub_arch_name
;
8014 cpu_sub_arch_name
= concat (name
,
8016 (const char *) NULL
);
8020 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
8021 cpu_arch_flags
= flags
;
8027 if (j
>= ARRAY_SIZE (cpu_arch
))
8028 as_fatal (_("Invalid -march= option: `%s'"), arg
);
8032 while (next
!= NULL
);
8037 as_fatal (_("Invalid -mtune= option: `%s'"), arg
);
8038 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
8040 if (strcmp (arg
, cpu_arch
[j
].name
) == 0)
8042 cpu_arch_tune_set
= 1;
8043 cpu_arch_tune
= cpu_arch
[j
].type
;
8044 cpu_arch_tune_flags
= cpu_arch
[j
].flags
;
8048 if (j
>= ARRAY_SIZE (cpu_arch
))
8049 as_fatal (_("Invalid -mtune= option: `%s'"), arg
);
8052 case OPTION_MMNEMONIC
:
8053 if (strcasecmp (arg
, "att") == 0)
8055 else if (strcasecmp (arg
, "intel") == 0)
8058 as_fatal (_("Invalid -mmnemonic= option: `%s'"), arg
);
8061 case OPTION_MSYNTAX
:
8062 if (strcasecmp (arg
, "att") == 0)
8064 else if (strcasecmp (arg
, "intel") == 0)
8067 as_fatal (_("Invalid -msyntax= option: `%s'"), arg
);
8070 case OPTION_MINDEX_REG
:
8071 allow_index_reg
= 1;
8074 case OPTION_MNAKED_REG
:
8075 allow_naked_reg
= 1;
8078 case OPTION_MOLD_GCC
:
8082 case OPTION_MSSE2AVX
:
8086 case OPTION_MSSE_CHECK
:
8087 if (strcasecmp (arg
, "error") == 0)
8088 sse_check
= sse_check_error
;
8089 else if (strcasecmp (arg
, "warning") == 0)
8090 sse_check
= sse_check_warning
;
8091 else if (strcasecmp (arg
, "none") == 0)
8092 sse_check
= sse_check_none
;
8094 as_fatal (_("Invalid -msse-check= option: `%s'"), arg
);
8103 #define MESSAGE_TEMPLATE \
8107 show_arch (FILE *stream
, int ext
)
8109 static char message
[] = MESSAGE_TEMPLATE
;
8110 char *start
= message
+ 27;
8112 int size
= sizeof (MESSAGE_TEMPLATE
);
8119 left
= size
- (start
- message
);
8120 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
8122 /* Should it be skipped? */
8123 if (cpu_arch
[j
].skip
)
8126 name
= cpu_arch
[j
].name
;
8127 len
= cpu_arch
[j
].len
;
8130 /* It is an extension. Skip if we aren't asked to show it. */
8141 /* It is an processor. Skip if we show only extension. */
8145 /* Reserve 2 spaces for ", " or ",\0" */
8148 /* Check if there is any room. */
8156 p
= mempcpy (p
, name
, len
);
8160 /* Output the current message now and start a new one. */
8163 fprintf (stream
, "%s\n", message
);
8165 left
= size
- (start
- message
) - len
- 2;
8167 gas_assert (left
>= 0);
8169 p
= mempcpy (p
, name
, len
);
8174 fprintf (stream
, "%s\n", message
);
8178 md_show_usage (FILE *stream
)
8180 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8181 fprintf (stream
, _("\
8183 -V print assembler version number\n\
8186 fprintf (stream
, _("\
8187 -n Do not optimize code alignment\n\
8188 -q quieten some warnings\n"));
8189 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8190 fprintf (stream
, _("\
8193 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
8194 || defined (TE_PE) || defined (TE_PEP))
8195 fprintf (stream
, _("\
8196 --32/--64 generate 32bit/64bit code\n"));
8198 #ifdef SVR4_COMMENT_CHARS
8199 fprintf (stream
, _("\
8200 --divide do not treat `/' as a comment character\n"));
8202 fprintf (stream
, _("\
8203 --divide ignored\n"));
8205 fprintf (stream
, _("\
8206 -march=CPU[,+EXTENSION...]\n\
8207 generate code for CPU and EXTENSION, CPU is one of:\n"));
8208 show_arch (stream
, 0);
8209 fprintf (stream
, _("\
8210 EXTENSION is combination of:\n"));
8211 show_arch (stream
, 1);
8212 fprintf (stream
, _("\
8213 -mtune=CPU optimize for CPU, CPU is one of:\n"));
8214 show_arch (stream
, 0);
8215 fprintf (stream
, _("\
8216 -msse2avx encode SSE instructions with VEX prefix\n"));
8217 fprintf (stream
, _("\
8218 -msse-check=[none|error|warning]\n\
8219 check SSE instructions\n"));
8220 fprintf (stream
, _("\
8221 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
8222 fprintf (stream
, _("\
8223 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
8224 fprintf (stream
, _("\
8225 -mindex-reg support pseudo index registers\n"));
8226 fprintf (stream
, _("\
8227 -mnaked-reg don't require `%%' prefix for registers\n"));
8228 fprintf (stream
, _("\
8229 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
8232 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
8233 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
8234 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
8236 /* Pick the target format to use. */
8239 i386_target_format (void)
8241 if (!strcmp (default_arch
, "x86_64"))
8243 set_code_flag (CODE_64BIT
);
8244 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
8246 cpu_arch_isa_flags
.bitfield
.cpui186
= 1;
8247 cpu_arch_isa_flags
.bitfield
.cpui286
= 1;
8248 cpu_arch_isa_flags
.bitfield
.cpui386
= 1;
8249 cpu_arch_isa_flags
.bitfield
.cpui486
= 1;
8250 cpu_arch_isa_flags
.bitfield
.cpui586
= 1;
8251 cpu_arch_isa_flags
.bitfield
.cpui686
= 1;
8252 cpu_arch_isa_flags
.bitfield
.cpuclflush
= 1;
8253 cpu_arch_isa_flags
.bitfield
.cpummx
= 1;
8254 cpu_arch_isa_flags
.bitfield
.cpusse
= 1;
8255 cpu_arch_isa_flags
.bitfield
.cpusse2
= 1;
8256 cpu_arch_isa_flags
.bitfield
.cpulm
= 1;
8258 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
8260 cpu_arch_tune_flags
.bitfield
.cpui186
= 1;
8261 cpu_arch_tune_flags
.bitfield
.cpui286
= 1;
8262 cpu_arch_tune_flags
.bitfield
.cpui386
= 1;
8263 cpu_arch_tune_flags
.bitfield
.cpui486
= 1;
8264 cpu_arch_tune_flags
.bitfield
.cpui586
= 1;
8265 cpu_arch_tune_flags
.bitfield
.cpui686
= 1;
8266 cpu_arch_tune_flags
.bitfield
.cpuclflush
= 1;
8267 cpu_arch_tune_flags
.bitfield
.cpummx
= 1;
8268 cpu_arch_tune_flags
.bitfield
.cpusse
= 1;
8269 cpu_arch_tune_flags
.bitfield
.cpusse2
= 1;
8272 else if (!strcmp (default_arch
, "i386"))
8274 set_code_flag (CODE_32BIT
);
8275 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
8277 cpu_arch_isa_flags
.bitfield
.cpui186
= 1;
8278 cpu_arch_isa_flags
.bitfield
.cpui286
= 1;
8279 cpu_arch_isa_flags
.bitfield
.cpui386
= 1;
8281 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
8283 cpu_arch_tune_flags
.bitfield
.cpui186
= 1;
8284 cpu_arch_tune_flags
.bitfield
.cpui286
= 1;
8285 cpu_arch_tune_flags
.bitfield
.cpui386
= 1;
8289 as_fatal (_("Unknown architecture"));
8290 switch (OUTPUT_FLAVOR
)
8292 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
8293 case bfd_target_aout_flavour
:
8294 return AOUT_TARGET_FORMAT
;
8296 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
8297 # if defined (TE_PE) || defined (TE_PEP)
8298 case bfd_target_coff_flavour
:
8299 return flag_code
== CODE_64BIT
? "pe-x86-64" : "pe-i386";
8300 # elif defined (TE_GO32)
8301 case bfd_target_coff_flavour
:
8304 case bfd_target_coff_flavour
:
8308 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
8309 case bfd_target_elf_flavour
:
8311 if (flag_code
== CODE_64BIT
)
8314 use_rela_relocations
= 1;
8316 if (cpu_arch_isa
== PROCESSOR_L1OM
)
8318 if (flag_code
!= CODE_64BIT
)
8319 as_fatal (_("Intel L1OM is 64bit only"));
8320 return ELF_TARGET_L1OM_FORMAT
;
8323 return (flag_code
== CODE_64BIT
8324 ? ELF_TARGET_FORMAT64
: ELF_TARGET_FORMAT
);
8327 #if defined (OBJ_MACH_O)
8328 case bfd_target_mach_o_flavour
:
8329 return flag_code
== CODE_64BIT
? "mach-o-x86-64" : "mach-o-i386";
8337 #endif /* OBJ_MAYBE_ more than one */
8339 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
8341 i386_elf_emit_arch_note (void)
8343 if (IS_ELF
&& cpu_arch_name
!= NULL
)
8346 asection
*seg
= now_seg
;
8347 subsegT subseg
= now_subseg
;
8348 Elf_Internal_Note i_note
;
8349 Elf_External_Note e_note
;
8350 asection
*note_secp
;
8353 /* Create the .note section. */
8354 note_secp
= subseg_new (".note", 0);
8355 bfd_set_section_flags (stdoutput
,
8357 SEC_HAS_CONTENTS
| SEC_READONLY
);
8359 /* Process the arch string. */
8360 len
= strlen (cpu_arch_name
);
8362 i_note
.namesz
= len
+ 1;
8364 i_note
.type
= NT_ARCH
;
8365 p
= frag_more (sizeof (e_note
.namesz
));
8366 md_number_to_chars (p
, (valueT
) i_note
.namesz
, sizeof (e_note
.namesz
));
8367 p
= frag_more (sizeof (e_note
.descsz
));
8368 md_number_to_chars (p
, (valueT
) i_note
.descsz
, sizeof (e_note
.descsz
));
8369 p
= frag_more (sizeof (e_note
.type
));
8370 md_number_to_chars (p
, (valueT
) i_note
.type
, sizeof (e_note
.type
));
8371 p
= frag_more (len
+ 1);
8372 strcpy (p
, cpu_arch_name
);
8374 frag_align (2, 0, 0);
8376 subseg_set (seg
, subseg
);
8382 md_undefined_symbol (name
)
8385 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
8386 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
8387 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
8388 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
8392 if (symbol_find (name
))
8393 as_bad (_("GOT already in symbol table"));
8394 GOT_symbol
= symbol_new (name
, undefined_section
,
8395 (valueT
) 0, &zero_address_frag
);
8402 /* Round up a section size to the appropriate boundary. */
8405 md_section_align (segment
, size
)
8406 segT segment ATTRIBUTE_UNUSED
;
8409 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8410 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
8412 /* For a.out, force the section size to be aligned. If we don't do
8413 this, BFD will align it for us, but it will not write out the
8414 final bytes of the section. This may be a bug in BFD, but it is
8415 easier to fix it here since that is how the other a.out targets
8419 align
= bfd_get_section_alignment (stdoutput
, segment
);
8420 size
= ((size
+ (1 << align
) - 1) & ((valueT
) -1 << align
));
8427 /* On the i386, PC-relative offsets are relative to the start of the
8428 next instruction. That is, the address of the offset, plus its
8429 size, since the offset is always the last part of the insn. */
8432 md_pcrel_from (fixS
*fixP
)
8434 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
8440 s_bss (int ignore ATTRIBUTE_UNUSED
)
8444 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8446 obj_elf_section_change_hook ();
8448 temp
= get_absolute_expression ();
8449 subseg_set (bss_section
, (subsegT
) temp
);
8450 demand_empty_rest_of_line ();
8456 i386_validate_fix (fixS
*fixp
)
8458 if (fixp
->fx_subsy
&& fixp
->fx_subsy
== GOT_symbol
)
8460 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
8464 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
8469 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
8471 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
8478 tc_gen_reloc (section
, fixp
)
8479 asection
*section ATTRIBUTE_UNUSED
;
8483 bfd_reloc_code_real_type code
;
8485 switch (fixp
->fx_r_type
)
8487 case BFD_RELOC_X86_64_PLT32
:
8488 case BFD_RELOC_X86_64_GOT32
:
8489 case BFD_RELOC_X86_64_GOTPCREL
:
8490 case BFD_RELOC_386_PLT32
:
8491 case BFD_RELOC_386_GOT32
:
8492 case BFD_RELOC_386_GOTOFF
:
8493 case BFD_RELOC_386_GOTPC
:
8494 case BFD_RELOC_386_TLS_GD
:
8495 case BFD_RELOC_386_TLS_LDM
:
8496 case BFD_RELOC_386_TLS_LDO_32
:
8497 case BFD_RELOC_386_TLS_IE_32
:
8498 case BFD_RELOC_386_TLS_IE
:
8499 case BFD_RELOC_386_TLS_GOTIE
:
8500 case BFD_RELOC_386_TLS_LE_32
:
8501 case BFD_RELOC_386_TLS_LE
:
8502 case BFD_RELOC_386_TLS_GOTDESC
:
8503 case BFD_RELOC_386_TLS_DESC_CALL
:
8504 case BFD_RELOC_X86_64_TLSGD
:
8505 case BFD_RELOC_X86_64_TLSLD
:
8506 case BFD_RELOC_X86_64_DTPOFF32
:
8507 case BFD_RELOC_X86_64_DTPOFF64
:
8508 case BFD_RELOC_X86_64_GOTTPOFF
:
8509 case BFD_RELOC_X86_64_TPOFF32
:
8510 case BFD_RELOC_X86_64_TPOFF64
:
8511 case BFD_RELOC_X86_64_GOTOFF64
:
8512 case BFD_RELOC_X86_64_GOTPC32
:
8513 case BFD_RELOC_X86_64_GOT64
:
8514 case BFD_RELOC_X86_64_GOTPCREL64
:
8515 case BFD_RELOC_X86_64_GOTPC64
:
8516 case BFD_RELOC_X86_64_GOTPLT64
:
8517 case BFD_RELOC_X86_64_PLTOFF64
:
8518 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
8519 case BFD_RELOC_X86_64_TLSDESC_CALL
:
8521 case BFD_RELOC_VTABLE_ENTRY
:
8522 case BFD_RELOC_VTABLE_INHERIT
:
8524 case BFD_RELOC_32_SECREL
:
8526 code
= fixp
->fx_r_type
;
8528 case BFD_RELOC_X86_64_32S
:
8529 if (!fixp
->fx_pcrel
)
8531 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
8532 code
= fixp
->fx_r_type
;
8538 switch (fixp
->fx_size
)
8541 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
8542 _("can not do %d byte pc-relative relocation"),
8544 code
= BFD_RELOC_32_PCREL
;
8546 case 1: code
= BFD_RELOC_8_PCREL
; break;
8547 case 2: code
= BFD_RELOC_16_PCREL
; break;
8548 case 4: code
= BFD_RELOC_32_PCREL
; break;
8550 case 8: code
= BFD_RELOC_64_PCREL
; break;
8556 switch (fixp
->fx_size
)
8559 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
8560 _("can not do %d byte relocation"),
8562 code
= BFD_RELOC_32
;
8564 case 1: code
= BFD_RELOC_8
; break;
8565 case 2: code
= BFD_RELOC_16
; break;
8566 case 4: code
= BFD_RELOC_32
; break;
8568 case 8: code
= BFD_RELOC_64
; break;
8575 if ((code
== BFD_RELOC_32
8576 || code
== BFD_RELOC_32_PCREL
8577 || code
== BFD_RELOC_X86_64_32S
)
8579 && fixp
->fx_addsy
== GOT_symbol
)
8582 code
= BFD_RELOC_386_GOTPC
;
8584 code
= BFD_RELOC_X86_64_GOTPC32
;
8586 if ((code
== BFD_RELOC_64
|| code
== BFD_RELOC_64_PCREL
)
8588 && fixp
->fx_addsy
== GOT_symbol
)
8590 code
= BFD_RELOC_X86_64_GOTPC64
;
8593 rel
= (arelent
*) xmalloc (sizeof (arelent
));
8594 rel
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
8595 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
8597 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
8599 if (!use_rela_relocations
)
8601 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
8602 vtable entry to be used in the relocation's section offset. */
8603 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
8604 rel
->address
= fixp
->fx_offset
;
8605 #if defined (OBJ_COFF) && defined (TE_PE)
8606 else if (fixp
->fx_addsy
&& S_IS_WEAK (fixp
->fx_addsy
))
8607 rel
->addend
= fixp
->fx_addnumber
- (S_GET_VALUE (fixp
->fx_addsy
) * 2);
8612 /* Use the rela in 64bit mode. */
8615 if (!fixp
->fx_pcrel
)
8616 rel
->addend
= fixp
->fx_offset
;
8620 case BFD_RELOC_X86_64_PLT32
:
8621 case BFD_RELOC_X86_64_GOT32
:
8622 case BFD_RELOC_X86_64_GOTPCREL
:
8623 case BFD_RELOC_X86_64_TLSGD
:
8624 case BFD_RELOC_X86_64_TLSLD
:
8625 case BFD_RELOC_X86_64_GOTTPOFF
:
8626 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
8627 case BFD_RELOC_X86_64_TLSDESC_CALL
:
8628 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
8631 rel
->addend
= (section
->vma
8633 + fixp
->fx_addnumber
8634 + md_pcrel_from (fixp
));
8639 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
8640 if (rel
->howto
== NULL
)
8642 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
8643 _("cannot represent relocation type %s"),
8644 bfd_get_reloc_code_name (code
));
8645 /* Set howto to a garbage value so that we can keep going. */
8646 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
8647 gas_assert (rel
->howto
!= NULL
);
8653 #include "tc-i386-intel.c"
8656 tc_x86_parse_to_dw2regnum (expressionS
*exp
)
8658 int saved_naked_reg
;
8659 char saved_register_dot
;
8661 saved_naked_reg
= allow_naked_reg
;
8662 allow_naked_reg
= 1;
8663 saved_register_dot
= register_chars
['.'];
8664 register_chars
['.'] = '.';
8665 allow_pseudo_reg
= 1;
8666 expression_and_evaluate (exp
);
8667 allow_pseudo_reg
= 0;
8668 register_chars
['.'] = saved_register_dot
;
8669 allow_naked_reg
= saved_naked_reg
;
8671 if (exp
->X_op
== O_register
&& exp
->X_add_number
>= 0)
8673 if ((addressT
) exp
->X_add_number
< i386_regtab_size
)
8675 exp
->X_op
= O_constant
;
8676 exp
->X_add_number
= i386_regtab
[exp
->X_add_number
]
8677 .dw2_regnum
[flag_code
>> 1];
8680 exp
->X_op
= O_illegal
;
8685 tc_x86_frame_initial_instructions (void)
8687 static unsigned int sp_regno
[2];
8689 if (!sp_regno
[flag_code
>> 1])
8691 char *saved_input
= input_line_pointer
;
8692 char sp
[][4] = {"esp", "rsp"};
8695 input_line_pointer
= sp
[flag_code
>> 1];
8696 tc_x86_parse_to_dw2regnum (&exp
);
8697 gas_assert (exp
.X_op
== O_constant
);
8698 sp_regno
[flag_code
>> 1] = exp
.X_add_number
;
8699 input_line_pointer
= saved_input
;
8702 cfi_add_CFA_def_cfa (sp_regno
[flag_code
>> 1], -x86_cie_data_alignment
);
8703 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
8707 i386_elf_section_type (const char *str
, size_t len
)
8709 if (flag_code
== CODE_64BIT
8710 && len
== sizeof ("unwind") - 1
8711 && strncmp (str
, "unwind", 6) == 0)
8712 return SHT_X86_64_UNWIND
;
8719 i386_solaris_fix_up_eh_frame (segT sec
)
8721 if (flag_code
== CODE_64BIT
)
8722 elf_section_type (sec
) = SHT_X86_64_UNWIND
;
8728 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
8732 exp
.X_op
= O_secrel
;
8733 exp
.X_add_symbol
= symbol
;
8734 exp
.X_add_number
= 0;
8735 emit_expr (&exp
, size
);
8739 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8740 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
8743 x86_64_section_letter (int letter
, char **ptr_msg
)
8745 if (flag_code
== CODE_64BIT
)
8748 return SHF_X86_64_LARGE
;
8750 *ptr_msg
= _("Bad .section directive: want a,l,w,x,M,S,G,T in string");
8753 *ptr_msg
= _("Bad .section directive: want a,w,x,M,S,G,T in string");
8758 x86_64_section_word (char *str
, size_t len
)
8760 if (len
== 5 && flag_code
== CODE_64BIT
&& CONST_STRNEQ (str
, "large"))
8761 return SHF_X86_64_LARGE
;
8767 handle_large_common (int small ATTRIBUTE_UNUSED
)
8769 if (flag_code
!= CODE_64BIT
)
8771 s_comm_internal (0, elf_common_parse
);
8772 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
8776 static segT lbss_section
;
8777 asection
*saved_com_section_ptr
= elf_com_section_ptr
;
8778 asection
*saved_bss_section
= bss_section
;
8780 if (lbss_section
== NULL
)
8782 flagword applicable
;
8784 subsegT subseg
= now_subseg
;
8786 /* The .lbss section is for local .largecomm symbols. */
8787 lbss_section
= subseg_new (".lbss", 0);
8788 applicable
= bfd_applicable_section_flags (stdoutput
);
8789 bfd_set_section_flags (stdoutput
, lbss_section
,
8790 applicable
& SEC_ALLOC
);
8791 seg_info (lbss_section
)->bss
= 1;
8793 subseg_set (seg
, subseg
);
8796 elf_com_section_ptr
= &_bfd_elf_large_com_section
;
8797 bss_section
= lbss_section
;
8799 s_comm_internal (0, elf_common_parse
);
8801 elf_com_section_ptr
= saved_com_section_ptr
;
8802 bss_section
= saved_bss_section
;
8805 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */