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x86: Encode EVEX instructions with VEX128 if possible
[deliverable/binutils-gdb.git] / gas / config / tc-i386.c
1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright (C) 1989-2018 Free Software Foundation, Inc.
3
4 This file is part of GAS, the GNU Assembler.
5
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
9 any later version.
10
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
19 02110-1301, USA. */
20
21 /* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
23 x86_64 support by Jan Hubicka (jh@suse.cz)
24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
27
28 #include "as.h"
29 #include "safe-ctype.h"
30 #include "subsegs.h"
31 #include "dwarf2dbg.h"
32 #include "dw2gencfi.h"
33 #include "elf/x86-64.h"
34 #include "opcodes/i386-init.h"
35
36 #ifndef REGISTER_WARNINGS
37 #define REGISTER_WARNINGS 1
38 #endif
39
40 #ifndef INFER_ADDR_PREFIX
41 #define INFER_ADDR_PREFIX 1
42 #endif
43
44 #ifndef DEFAULT_ARCH
45 #define DEFAULT_ARCH "i386"
46 #endif
47
48 #ifndef INLINE
49 #if __GNUC__ >= 2
50 #define INLINE __inline__
51 #else
52 #define INLINE
53 #endif
54 #endif
55
56 /* Prefixes will be emitted in the order defined below.
57 WAIT_PREFIX must be the first prefix since FWAIT is really is an
58 instruction, and so must come before any prefixes.
59 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
60 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
61 #define WAIT_PREFIX 0
62 #define SEG_PREFIX 1
63 #define ADDR_PREFIX 2
64 #define DATA_PREFIX 3
65 #define REP_PREFIX 4
66 #define HLE_PREFIX REP_PREFIX
67 #define BND_PREFIX REP_PREFIX
68 #define LOCK_PREFIX 5
69 #define REX_PREFIX 6 /* must come last. */
70 #define MAX_PREFIXES 7 /* max prefixes per opcode */
71
72 /* we define the syntax here (modulo base,index,scale syntax) */
73 #define REGISTER_PREFIX '%'
74 #define IMMEDIATE_PREFIX '$'
75 #define ABSOLUTE_PREFIX '*'
76
77 /* these are the instruction mnemonic suffixes in AT&T syntax or
78 memory operand size in Intel syntax. */
79 #define WORD_MNEM_SUFFIX 'w'
80 #define BYTE_MNEM_SUFFIX 'b'
81 #define SHORT_MNEM_SUFFIX 's'
82 #define LONG_MNEM_SUFFIX 'l'
83 #define QWORD_MNEM_SUFFIX 'q'
84 /* Intel Syntax. Use a non-ascii letter since since it never appears
85 in instructions. */
86 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
87
88 #define END_OF_INSN '\0'
89
90 /*
91 'templates' is for grouping together 'template' structures for opcodes
92 of the same name. This is only used for storing the insns in the grand
93 ole hash table of insns.
94 The templates themselves start at START and range up to (but not including)
95 END.
96 */
97 typedef struct
98 {
99 const insn_template *start;
100 const insn_template *end;
101 }
102 templates;
103
104 /* 386 operand encoding bytes: see 386 book for details of this. */
105 typedef struct
106 {
107 unsigned int regmem; /* codes register or memory operand */
108 unsigned int reg; /* codes register operand (or extended opcode) */
109 unsigned int mode; /* how to interpret regmem & reg */
110 }
111 modrm_byte;
112
113 /* x86-64 extension prefix. */
114 typedef int rex_byte;
115
116 /* 386 opcode byte to code indirect addressing. */
117 typedef struct
118 {
119 unsigned base;
120 unsigned index;
121 unsigned scale;
122 }
123 sib_byte;
124
125 /* x86 arch names, types and features */
126 typedef struct
127 {
128 const char *name; /* arch name */
129 unsigned int len; /* arch string length */
130 enum processor_type type; /* arch type */
131 i386_cpu_flags flags; /* cpu feature flags */
132 unsigned int skip; /* show_arch should skip this. */
133 }
134 arch_entry;
135
136 /* Used to turn off indicated flags. */
137 typedef struct
138 {
139 const char *name; /* arch name */
140 unsigned int len; /* arch string length */
141 i386_cpu_flags flags; /* cpu feature flags */
142 }
143 noarch_entry;
144
145 static void update_code_flag (int, int);
146 static void set_code_flag (int);
147 static void set_16bit_gcc_code_flag (int);
148 static void set_intel_syntax (int);
149 static void set_intel_mnemonic (int);
150 static void set_allow_index_reg (int);
151 static void set_check (int);
152 static void set_cpu_arch (int);
153 #ifdef TE_PE
154 static void pe_directive_secrel (int);
155 #endif
156 static void signed_cons (int);
157 static char *output_invalid (int c);
158 static int i386_finalize_immediate (segT, expressionS *, i386_operand_type,
159 const char *);
160 static int i386_finalize_displacement (segT, expressionS *, i386_operand_type,
161 const char *);
162 static int i386_att_operand (char *);
163 static int i386_intel_operand (char *, int);
164 static int i386_intel_simplify (expressionS *);
165 static int i386_intel_parse_name (const char *, expressionS *);
166 static const reg_entry *parse_register (char *, char **);
167 static char *parse_insn (char *, char *);
168 static char *parse_operands (char *, const char *);
169 static void swap_operands (void);
170 static void swap_2_operands (int, int);
171 static void optimize_imm (void);
172 static void optimize_disp (void);
173 static const insn_template *match_template (char);
174 static int check_string (void);
175 static int process_suffix (void);
176 static int check_byte_reg (void);
177 static int check_long_reg (void);
178 static int check_qword_reg (void);
179 static int check_word_reg (void);
180 static int finalize_imm (void);
181 static int process_operands (void);
182 static const seg_entry *build_modrm_byte (void);
183 static void output_insn (void);
184 static void output_imm (fragS *, offsetT);
185 static void output_disp (fragS *, offsetT);
186 #ifndef I386COFF
187 static void s_bss (int);
188 #endif
189 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
190 static void handle_large_common (int small ATTRIBUTE_UNUSED);
191 #endif
192
193 static const char *default_arch = DEFAULT_ARCH;
194
195 /* This struct describes rounding control and SAE in the instruction. */
196 struct RC_Operation
197 {
198 enum rc_type
199 {
200 rne = 0,
201 rd,
202 ru,
203 rz,
204 saeonly
205 } type;
206 int operand;
207 };
208
209 static struct RC_Operation rc_op;
210
211 /* The struct describes masking, applied to OPERAND in the instruction.
212 MASK is a pointer to the corresponding mask register. ZEROING tells
213 whether merging or zeroing mask is used. */
214 struct Mask_Operation
215 {
216 const reg_entry *mask;
217 unsigned int zeroing;
218 /* The operand where this operation is associated. */
219 int operand;
220 };
221
222 static struct Mask_Operation mask_op;
223
224 /* The struct describes broadcasting, applied to OPERAND. FACTOR is
225 broadcast factor. */
226 struct Broadcast_Operation
227 {
228 /* Type of broadcast: no broadcast, {1to8}, or {1to16}. */
229 int type;
230
231 /* Index of broadcasted operand. */
232 int operand;
233 };
234
235 static struct Broadcast_Operation broadcast_op;
236
237 /* VEX prefix. */
238 typedef struct
239 {
240 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
241 unsigned char bytes[4];
242 unsigned int length;
243 /* Destination or source register specifier. */
244 const reg_entry *register_specifier;
245 } vex_prefix;
246
247 /* 'md_assemble ()' gathers together information and puts it into a
248 i386_insn. */
249
250 union i386_op
251 {
252 expressionS *disps;
253 expressionS *imms;
254 const reg_entry *regs;
255 };
256
257 enum i386_error
258 {
259 operand_size_mismatch,
260 operand_type_mismatch,
261 register_type_mismatch,
262 number_of_operands_mismatch,
263 invalid_instruction_suffix,
264 bad_imm4,
265 unsupported_with_intel_mnemonic,
266 unsupported_syntax,
267 unsupported,
268 invalid_vsib_address,
269 invalid_vector_register_set,
270 unsupported_vector_index_register,
271 unsupported_broadcast,
272 broadcast_not_on_src_operand,
273 broadcast_needed,
274 unsupported_masking,
275 mask_not_on_destination,
276 no_default_mask,
277 unsupported_rc_sae,
278 rc_sae_operand_not_last_imm,
279 invalid_register_operand,
280 };
281
282 struct _i386_insn
283 {
284 /* TM holds the template for the insn were currently assembling. */
285 insn_template tm;
286
287 /* SUFFIX holds the instruction size suffix for byte, word, dword
288 or qword, if given. */
289 char suffix;
290
291 /* OPERANDS gives the number of given operands. */
292 unsigned int operands;
293
294 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
295 of given register, displacement, memory operands and immediate
296 operands. */
297 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
298
299 /* TYPES [i] is the type (see above #defines) which tells us how to
300 use OP[i] for the corresponding operand. */
301 i386_operand_type types[MAX_OPERANDS];
302
303 /* Displacement expression, immediate expression, or register for each
304 operand. */
305 union i386_op op[MAX_OPERANDS];
306
307 /* Flags for operands. */
308 unsigned int flags[MAX_OPERANDS];
309 #define Operand_PCrel 1
310
311 /* Relocation type for operand */
312 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
313
314 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
315 the base index byte below. */
316 const reg_entry *base_reg;
317 const reg_entry *index_reg;
318 unsigned int log2_scale_factor;
319
320 /* SEG gives the seg_entries of this insn. They are zero unless
321 explicit segment overrides are given. */
322 const seg_entry *seg[2];
323
324 /* Copied first memory operand string, for re-checking. */
325 char *memop1_string;
326
327 /* PREFIX holds all the given prefix opcodes (usually null).
328 PREFIXES is the number of prefix opcodes. */
329 unsigned int prefixes;
330 unsigned char prefix[MAX_PREFIXES];
331
332 /* RM and SIB are the modrm byte and the sib byte where the
333 addressing modes of this insn are encoded. */
334 modrm_byte rm;
335 rex_byte rex;
336 rex_byte vrex;
337 sib_byte sib;
338 vex_prefix vex;
339
340 /* Masking attributes. */
341 struct Mask_Operation *mask;
342
343 /* Rounding control and SAE attributes. */
344 struct RC_Operation *rounding;
345
346 /* Broadcasting attributes. */
347 struct Broadcast_Operation *broadcast;
348
349 /* Compressed disp8*N attribute. */
350 unsigned int memshift;
351
352 /* Prefer load or store in encoding. */
353 enum
354 {
355 dir_encoding_default = 0,
356 dir_encoding_load,
357 dir_encoding_store
358 } dir_encoding;
359
360 /* Prefer 8bit or 32bit displacement in encoding. */
361 enum
362 {
363 disp_encoding_default = 0,
364 disp_encoding_8bit,
365 disp_encoding_32bit
366 } disp_encoding;
367
368 /* Prefer the REX byte in encoding. */
369 bfd_boolean rex_encoding;
370
371 /* Disable instruction size optimization. */
372 bfd_boolean no_optimize;
373
374 /* How to encode vector instructions. */
375 enum
376 {
377 vex_encoding_default = 0,
378 vex_encoding_vex2,
379 vex_encoding_vex3,
380 vex_encoding_evex
381 } vec_encoding;
382
383 /* REP prefix. */
384 const char *rep_prefix;
385
386 /* HLE prefix. */
387 const char *hle_prefix;
388
389 /* Have BND prefix. */
390 const char *bnd_prefix;
391
392 /* Have NOTRACK prefix. */
393 const char *notrack_prefix;
394
395 /* Error message. */
396 enum i386_error error;
397 };
398
399 typedef struct _i386_insn i386_insn;
400
401 /* Link RC type with corresponding string, that'll be looked for in
402 asm. */
403 struct RC_name
404 {
405 enum rc_type type;
406 const char *name;
407 unsigned int len;
408 };
409
410 static const struct RC_name RC_NamesTable[] =
411 {
412 { rne, STRING_COMMA_LEN ("rn-sae") },
413 { rd, STRING_COMMA_LEN ("rd-sae") },
414 { ru, STRING_COMMA_LEN ("ru-sae") },
415 { rz, STRING_COMMA_LEN ("rz-sae") },
416 { saeonly, STRING_COMMA_LEN ("sae") },
417 };
418
419 /* List of chars besides those in app.c:symbol_chars that can start an
420 operand. Used to prevent the scrubber eating vital white-space. */
421 const char extra_symbol_chars[] = "*%-([{}"
422 #ifdef LEX_AT
423 "@"
424 #endif
425 #ifdef LEX_QM
426 "?"
427 #endif
428 ;
429
430 #if (defined (TE_I386AIX) \
431 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
432 && !defined (TE_GNU) \
433 && !defined (TE_LINUX) \
434 && !defined (TE_NACL) \
435 && !defined (TE_NETWARE) \
436 && !defined (TE_FreeBSD) \
437 && !defined (TE_DragonFly) \
438 && !defined (TE_NetBSD)))
439 /* This array holds the chars that always start a comment. If the
440 pre-processor is disabled, these aren't very useful. The option
441 --divide will remove '/' from this list. */
442 const char *i386_comment_chars = "#/";
443 #define SVR4_COMMENT_CHARS 1
444 #define PREFIX_SEPARATOR '\\'
445
446 #else
447 const char *i386_comment_chars = "#";
448 #define PREFIX_SEPARATOR '/'
449 #endif
450
451 /* This array holds the chars that only start a comment at the beginning of
452 a line. If the line seems to have the form '# 123 filename'
453 .line and .file directives will appear in the pre-processed output.
454 Note that input_file.c hand checks for '#' at the beginning of the
455 first line of the input file. This is because the compiler outputs
456 #NO_APP at the beginning of its output.
457 Also note that comments started like this one will always work if
458 '/' isn't otherwise defined. */
459 const char line_comment_chars[] = "#/";
460
461 const char line_separator_chars[] = ";";
462
463 /* Chars that can be used to separate mant from exp in floating point
464 nums. */
465 const char EXP_CHARS[] = "eE";
466
467 /* Chars that mean this number is a floating point constant
468 As in 0f12.456
469 or 0d1.2345e12. */
470 const char FLT_CHARS[] = "fFdDxX";
471
472 /* Tables for lexical analysis. */
473 static char mnemonic_chars[256];
474 static char register_chars[256];
475 static char operand_chars[256];
476 static char identifier_chars[256];
477 static char digit_chars[256];
478
479 /* Lexical macros. */
480 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
481 #define is_operand_char(x) (operand_chars[(unsigned char) x])
482 #define is_register_char(x) (register_chars[(unsigned char) x])
483 #define is_space_char(x) ((x) == ' ')
484 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
485 #define is_digit_char(x) (digit_chars[(unsigned char) x])
486
487 /* All non-digit non-letter characters that may occur in an operand. */
488 static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
489
490 /* md_assemble() always leaves the strings it's passed unaltered. To
491 effect this we maintain a stack of saved characters that we've smashed
492 with '\0's (indicating end of strings for various sub-fields of the
493 assembler instruction). */
494 static char save_stack[32];
495 static char *save_stack_p;
496 #define END_STRING_AND_SAVE(s) \
497 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
498 #define RESTORE_END_STRING(s) \
499 do { *(s) = *--save_stack_p; } while (0)
500
501 /* The instruction we're assembling. */
502 static i386_insn i;
503
504 /* Possible templates for current insn. */
505 static const templates *current_templates;
506
507 /* Per instruction expressionS buffers: max displacements & immediates. */
508 static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
509 static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
510
511 /* Current operand we are working on. */
512 static int this_operand = -1;
513
514 /* We support four different modes. FLAG_CODE variable is used to distinguish
515 these. */
516
517 enum flag_code {
518 CODE_32BIT,
519 CODE_16BIT,
520 CODE_64BIT };
521
522 static enum flag_code flag_code;
523 static unsigned int object_64bit;
524 static unsigned int disallow_64bit_reloc;
525 static int use_rela_relocations = 0;
526
527 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
528 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
529 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
530
531 /* The ELF ABI to use. */
532 enum x86_elf_abi
533 {
534 I386_ABI,
535 X86_64_ABI,
536 X86_64_X32_ABI
537 };
538
539 static enum x86_elf_abi x86_elf_abi = I386_ABI;
540 #endif
541
542 #if defined (TE_PE) || defined (TE_PEP)
543 /* Use big object file format. */
544 static int use_big_obj = 0;
545 #endif
546
547 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
548 /* 1 if generating code for a shared library. */
549 static int shared = 0;
550 #endif
551
552 /* 1 for intel syntax,
553 0 if att syntax. */
554 static int intel_syntax = 0;
555
556 /* 1 for Intel64 ISA,
557 0 if AMD64 ISA. */
558 static int intel64;
559
560 /* 1 for intel mnemonic,
561 0 if att mnemonic. */
562 static int intel_mnemonic = !SYSV386_COMPAT;
563
564 /* 1 if pseudo registers are permitted. */
565 static int allow_pseudo_reg = 0;
566
567 /* 1 if register prefix % not required. */
568 static int allow_naked_reg = 0;
569
570 /* 1 if the assembler should add BND prefix for all control-transferring
571 instructions supporting it, even if this prefix wasn't specified
572 explicitly. */
573 static int add_bnd_prefix = 0;
574
575 /* 1 if pseudo index register, eiz/riz, is allowed . */
576 static int allow_index_reg = 0;
577
578 /* 1 if the assembler should ignore LOCK prefix, even if it was
579 specified explicitly. */
580 static int omit_lock_prefix = 0;
581
582 /* 1 if the assembler should encode lfence, mfence, and sfence as
583 "lock addl $0, (%{re}sp)". */
584 static int avoid_fence = 0;
585
586 /* 1 if the assembler should generate relax relocations. */
587
588 static int generate_relax_relocations
589 = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS;
590
591 static enum check_kind
592 {
593 check_none = 0,
594 check_warning,
595 check_error
596 }
597 sse_check, operand_check = check_warning;
598
599 /* Optimization:
600 1. Clear the REX_W bit with register operand if possible.
601 2. Above plus use 128bit vector instruction to clear the full vector
602 register.
603 */
604 static int optimize = 0;
605
606 /* Optimization:
607 1. Clear the REX_W bit with register operand if possible.
608 2. Above plus use 128bit vector instruction to clear the full vector
609 register.
610 3. Above plus optimize "test{q,l,w} $imm8,%r{64,32,16}" to
611 "testb $imm7,%r8".
612 */
613 static int optimize_for_space = 0;
614
615 /* Register prefix used for error message. */
616 static const char *register_prefix = "%";
617
618 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
619 leave, push, and pop instructions so that gcc has the same stack
620 frame as in 32 bit mode. */
621 static char stackop_size = '\0';
622
623 /* Non-zero to optimize code alignment. */
624 int optimize_align_code = 1;
625
626 /* Non-zero to quieten some warnings. */
627 static int quiet_warnings = 0;
628
629 /* CPU name. */
630 static const char *cpu_arch_name = NULL;
631 static char *cpu_sub_arch_name = NULL;
632
633 /* CPU feature flags. */
634 static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS;
635
636 /* If we have selected a cpu we are generating instructions for. */
637 static int cpu_arch_tune_set = 0;
638
639 /* Cpu we are generating instructions for. */
640 enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
641
642 /* CPU feature flags of cpu we are generating instructions for. */
643 static i386_cpu_flags cpu_arch_tune_flags;
644
645 /* CPU instruction set architecture used. */
646 enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
647
648 /* CPU feature flags of instruction set architecture used. */
649 i386_cpu_flags cpu_arch_isa_flags;
650
651 /* If set, conditional jumps are not automatically promoted to handle
652 larger than a byte offset. */
653 static unsigned int no_cond_jump_promotion = 0;
654
655 /* Encode SSE instructions with VEX prefix. */
656 static unsigned int sse2avx;
657
658 /* Encode scalar AVX instructions with specific vector length. */
659 static enum
660 {
661 vex128 = 0,
662 vex256
663 } avxscalar;
664
665 /* Encode scalar EVEX LIG instructions with specific vector length. */
666 static enum
667 {
668 evexl128 = 0,
669 evexl256,
670 evexl512
671 } evexlig;
672
673 /* Encode EVEX WIG instructions with specific evex.w. */
674 static enum
675 {
676 evexw0 = 0,
677 evexw1
678 } evexwig;
679
680 /* Value to encode in EVEX RC bits, for SAE-only instructions. */
681 static enum rc_type evexrcig = rne;
682
683 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
684 static symbolS *GOT_symbol;
685
686 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
687 unsigned int x86_dwarf2_return_column;
688
689 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
690 int x86_cie_data_alignment;
691
692 /* Interface to relax_segment.
693 There are 3 major relax states for 386 jump insns because the
694 different types of jumps add different sizes to frags when we're
695 figuring out what sort of jump to choose to reach a given label. */
696
697 /* Types. */
698 #define UNCOND_JUMP 0
699 #define COND_JUMP 1
700 #define COND_JUMP86 2
701
702 /* Sizes. */
703 #define CODE16 1
704 #define SMALL 0
705 #define SMALL16 (SMALL | CODE16)
706 #define BIG 2
707 #define BIG16 (BIG | CODE16)
708
709 #ifndef INLINE
710 #ifdef __GNUC__
711 #define INLINE __inline__
712 #else
713 #define INLINE
714 #endif
715 #endif
716
717 #define ENCODE_RELAX_STATE(type, size) \
718 ((relax_substateT) (((type) << 2) | (size)))
719 #define TYPE_FROM_RELAX_STATE(s) \
720 ((s) >> 2)
721 #define DISP_SIZE_FROM_RELAX_STATE(s) \
722 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
723
724 /* This table is used by relax_frag to promote short jumps to long
725 ones where necessary. SMALL (short) jumps may be promoted to BIG
726 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
727 don't allow a short jump in a 32 bit code segment to be promoted to
728 a 16 bit offset jump because it's slower (requires data size
729 prefix), and doesn't work, unless the destination is in the bottom
730 64k of the code segment (The top 16 bits of eip are zeroed). */
731
732 const relax_typeS md_relax_table[] =
733 {
734 /* The fields are:
735 1) most positive reach of this state,
736 2) most negative reach of this state,
737 3) how many bytes this mode will have in the variable part of the frag
738 4) which index into the table to try if we can't fit into this one. */
739
740 /* UNCOND_JUMP states. */
741 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
742 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
743 /* dword jmp adds 4 bytes to frag:
744 0 extra opcode bytes, 4 displacement bytes. */
745 {0, 0, 4, 0},
746 /* word jmp adds 2 byte2 to frag:
747 0 extra opcode bytes, 2 displacement bytes. */
748 {0, 0, 2, 0},
749
750 /* COND_JUMP states. */
751 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
752 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
753 /* dword conditionals adds 5 bytes to frag:
754 1 extra opcode byte, 4 displacement bytes. */
755 {0, 0, 5, 0},
756 /* word conditionals add 3 bytes to frag:
757 1 extra opcode byte, 2 displacement bytes. */
758 {0, 0, 3, 0},
759
760 /* COND_JUMP86 states. */
761 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
762 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
763 /* dword conditionals adds 5 bytes to frag:
764 1 extra opcode byte, 4 displacement bytes. */
765 {0, 0, 5, 0},
766 /* word conditionals add 4 bytes to frag:
767 1 displacement byte and a 3 byte long branch insn. */
768 {0, 0, 4, 0}
769 };
770
771 static const arch_entry cpu_arch[] =
772 {
773 /* Do not replace the first two entries - i386_target_format()
774 relies on them being there in this order. */
775 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32,
776 CPU_GENERIC32_FLAGS, 0 },
777 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64,
778 CPU_GENERIC64_FLAGS, 0 },
779 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN,
780 CPU_NONE_FLAGS, 0 },
781 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN,
782 CPU_I186_FLAGS, 0 },
783 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN,
784 CPU_I286_FLAGS, 0 },
785 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386,
786 CPU_I386_FLAGS, 0 },
787 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486,
788 CPU_I486_FLAGS, 0 },
789 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM,
790 CPU_I586_FLAGS, 0 },
791 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO,
792 CPU_I686_FLAGS, 0 },
793 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM,
794 CPU_I586_FLAGS, 0 },
795 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO,
796 CPU_PENTIUMPRO_FLAGS, 0 },
797 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO,
798 CPU_P2_FLAGS, 0 },
799 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO,
800 CPU_P3_FLAGS, 0 },
801 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4,
802 CPU_P4_FLAGS, 0 },
803 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA,
804 CPU_CORE_FLAGS, 0 },
805 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA,
806 CPU_NOCONA_FLAGS, 0 },
807 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE,
808 CPU_CORE_FLAGS, 1 },
809 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE,
810 CPU_CORE_FLAGS, 0 },
811 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2,
812 CPU_CORE2_FLAGS, 1 },
813 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2,
814 CPU_CORE2_FLAGS, 0 },
815 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7,
816 CPU_COREI7_FLAGS, 0 },
817 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM,
818 CPU_L1OM_FLAGS, 0 },
819 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM,
820 CPU_K1OM_FLAGS, 0 },
821 { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU,
822 CPU_IAMCU_FLAGS, 0 },
823 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6,
824 CPU_K6_FLAGS, 0 },
825 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6,
826 CPU_K6_2_FLAGS, 0 },
827 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON,
828 CPU_ATHLON_FLAGS, 0 },
829 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8,
830 CPU_K8_FLAGS, 1 },
831 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8,
832 CPU_K8_FLAGS, 0 },
833 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8,
834 CPU_K8_FLAGS, 0 },
835 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10,
836 CPU_AMDFAM10_FLAGS, 0 },
837 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD,
838 CPU_BDVER1_FLAGS, 0 },
839 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD,
840 CPU_BDVER2_FLAGS, 0 },
841 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD,
842 CPU_BDVER3_FLAGS, 0 },
843 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD,
844 CPU_BDVER4_FLAGS, 0 },
845 { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER,
846 CPU_ZNVER1_FLAGS, 0 },
847 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT,
848 CPU_BTVER1_FLAGS, 0 },
849 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT,
850 CPU_BTVER2_FLAGS, 0 },
851 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN,
852 CPU_8087_FLAGS, 0 },
853 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN,
854 CPU_287_FLAGS, 0 },
855 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN,
856 CPU_387_FLAGS, 0 },
857 { STRING_COMMA_LEN (".687"), PROCESSOR_UNKNOWN,
858 CPU_687_FLAGS, 0 },
859 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN,
860 CPU_MMX_FLAGS, 0 },
861 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN,
862 CPU_SSE_FLAGS, 0 },
863 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN,
864 CPU_SSE2_FLAGS, 0 },
865 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN,
866 CPU_SSE3_FLAGS, 0 },
867 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN,
868 CPU_SSSE3_FLAGS, 0 },
869 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN,
870 CPU_SSE4_1_FLAGS, 0 },
871 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN,
872 CPU_SSE4_2_FLAGS, 0 },
873 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN,
874 CPU_SSE4_2_FLAGS, 0 },
875 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN,
876 CPU_AVX_FLAGS, 0 },
877 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN,
878 CPU_AVX2_FLAGS, 0 },
879 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN,
880 CPU_AVX512F_FLAGS, 0 },
881 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN,
882 CPU_AVX512CD_FLAGS, 0 },
883 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN,
884 CPU_AVX512ER_FLAGS, 0 },
885 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN,
886 CPU_AVX512PF_FLAGS, 0 },
887 { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN,
888 CPU_AVX512DQ_FLAGS, 0 },
889 { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN,
890 CPU_AVX512BW_FLAGS, 0 },
891 { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN,
892 CPU_AVX512VL_FLAGS, 0 },
893 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN,
894 CPU_VMX_FLAGS, 0 },
895 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN,
896 CPU_VMFUNC_FLAGS, 0 },
897 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN,
898 CPU_SMX_FLAGS, 0 },
899 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN,
900 CPU_XSAVE_FLAGS, 0 },
901 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN,
902 CPU_XSAVEOPT_FLAGS, 0 },
903 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN,
904 CPU_XSAVEC_FLAGS, 0 },
905 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN,
906 CPU_XSAVES_FLAGS, 0 },
907 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN,
908 CPU_AES_FLAGS, 0 },
909 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN,
910 CPU_PCLMUL_FLAGS, 0 },
911 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN,
912 CPU_PCLMUL_FLAGS, 1 },
913 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN,
914 CPU_FSGSBASE_FLAGS, 0 },
915 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN,
916 CPU_RDRND_FLAGS, 0 },
917 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN,
918 CPU_F16C_FLAGS, 0 },
919 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN,
920 CPU_BMI2_FLAGS, 0 },
921 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN,
922 CPU_FMA_FLAGS, 0 },
923 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN,
924 CPU_FMA4_FLAGS, 0 },
925 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN,
926 CPU_XOP_FLAGS, 0 },
927 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN,
928 CPU_LWP_FLAGS, 0 },
929 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN,
930 CPU_MOVBE_FLAGS, 0 },
931 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN,
932 CPU_CX16_FLAGS, 0 },
933 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN,
934 CPU_EPT_FLAGS, 0 },
935 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN,
936 CPU_LZCNT_FLAGS, 0 },
937 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN,
938 CPU_HLE_FLAGS, 0 },
939 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN,
940 CPU_RTM_FLAGS, 0 },
941 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN,
942 CPU_INVPCID_FLAGS, 0 },
943 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN,
944 CPU_CLFLUSH_FLAGS, 0 },
945 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN,
946 CPU_NOP_FLAGS, 0 },
947 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN,
948 CPU_SYSCALL_FLAGS, 0 },
949 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN,
950 CPU_RDTSCP_FLAGS, 0 },
951 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN,
952 CPU_3DNOW_FLAGS, 0 },
953 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN,
954 CPU_3DNOWA_FLAGS, 0 },
955 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN,
956 CPU_PADLOCK_FLAGS, 0 },
957 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN,
958 CPU_SVME_FLAGS, 1 },
959 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN,
960 CPU_SVME_FLAGS, 0 },
961 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN,
962 CPU_SSE4A_FLAGS, 0 },
963 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN,
964 CPU_ABM_FLAGS, 0 },
965 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN,
966 CPU_BMI_FLAGS, 0 },
967 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN,
968 CPU_TBM_FLAGS, 0 },
969 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN,
970 CPU_ADX_FLAGS, 0 },
971 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN,
972 CPU_RDSEED_FLAGS, 0 },
973 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN,
974 CPU_PRFCHW_FLAGS, 0 },
975 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN,
976 CPU_SMAP_FLAGS, 0 },
977 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN,
978 CPU_MPX_FLAGS, 0 },
979 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN,
980 CPU_SHA_FLAGS, 0 },
981 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN,
982 CPU_CLFLUSHOPT_FLAGS, 0 },
983 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN,
984 CPU_PREFETCHWT1_FLAGS, 0 },
985 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN,
986 CPU_SE1_FLAGS, 0 },
987 { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN,
988 CPU_CLWB_FLAGS, 0 },
989 { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN,
990 CPU_AVX512IFMA_FLAGS, 0 },
991 { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN,
992 CPU_AVX512VBMI_FLAGS, 0 },
993 { STRING_COMMA_LEN (".avx512_4fmaps"), PROCESSOR_UNKNOWN,
994 CPU_AVX512_4FMAPS_FLAGS, 0 },
995 { STRING_COMMA_LEN (".avx512_4vnniw"), PROCESSOR_UNKNOWN,
996 CPU_AVX512_4VNNIW_FLAGS, 0 },
997 { STRING_COMMA_LEN (".avx512_vpopcntdq"), PROCESSOR_UNKNOWN,
998 CPU_AVX512_VPOPCNTDQ_FLAGS, 0 },
999 { STRING_COMMA_LEN (".avx512_vbmi2"), PROCESSOR_UNKNOWN,
1000 CPU_AVX512_VBMI2_FLAGS, 0 },
1001 { STRING_COMMA_LEN (".avx512_vnni"), PROCESSOR_UNKNOWN,
1002 CPU_AVX512_VNNI_FLAGS, 0 },
1003 { STRING_COMMA_LEN (".avx512_bitalg"), PROCESSOR_UNKNOWN,
1004 CPU_AVX512_BITALG_FLAGS, 0 },
1005 { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN,
1006 CPU_CLZERO_FLAGS, 0 },
1007 { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN,
1008 CPU_MWAITX_FLAGS, 0 },
1009 { STRING_COMMA_LEN (".ospke"), PROCESSOR_UNKNOWN,
1010 CPU_OSPKE_FLAGS, 0 },
1011 { STRING_COMMA_LEN (".rdpid"), PROCESSOR_UNKNOWN,
1012 CPU_RDPID_FLAGS, 0 },
1013 { STRING_COMMA_LEN (".ptwrite"), PROCESSOR_UNKNOWN,
1014 CPU_PTWRITE_FLAGS, 0 },
1015 { STRING_COMMA_LEN (".ibt"), PROCESSOR_UNKNOWN,
1016 CPU_IBT_FLAGS, 0 },
1017 { STRING_COMMA_LEN (".shstk"), PROCESSOR_UNKNOWN,
1018 CPU_SHSTK_FLAGS, 0 },
1019 { STRING_COMMA_LEN (".gfni"), PROCESSOR_UNKNOWN,
1020 CPU_GFNI_FLAGS, 0 },
1021 { STRING_COMMA_LEN (".vaes"), PROCESSOR_UNKNOWN,
1022 CPU_VAES_FLAGS, 0 },
1023 { STRING_COMMA_LEN (".vpclmulqdq"), PROCESSOR_UNKNOWN,
1024 CPU_VPCLMULQDQ_FLAGS, 0 },
1025 { STRING_COMMA_LEN (".wbnoinvd"), PROCESSOR_UNKNOWN,
1026 CPU_WBNOINVD_FLAGS, 0 },
1027 { STRING_COMMA_LEN (".pconfig"), PROCESSOR_UNKNOWN,
1028 CPU_PCONFIG_FLAGS, 0 },
1029 };
1030
1031 static const noarch_entry cpu_noarch[] =
1032 {
1033 { STRING_COMMA_LEN ("no87"), CPU_ANY_X87_FLAGS },
1034 { STRING_COMMA_LEN ("no287"), CPU_ANY_287_FLAGS },
1035 { STRING_COMMA_LEN ("no387"), CPU_ANY_387_FLAGS },
1036 { STRING_COMMA_LEN ("no687"), CPU_ANY_687_FLAGS },
1037 { STRING_COMMA_LEN ("nommx"), CPU_ANY_MMX_FLAGS },
1038 { STRING_COMMA_LEN ("nosse"), CPU_ANY_SSE_FLAGS },
1039 { STRING_COMMA_LEN ("nosse2"), CPU_ANY_SSE2_FLAGS },
1040 { STRING_COMMA_LEN ("nosse3"), CPU_ANY_SSE3_FLAGS },
1041 { STRING_COMMA_LEN ("nossse3"), CPU_ANY_SSSE3_FLAGS },
1042 { STRING_COMMA_LEN ("nosse4.1"), CPU_ANY_SSE4_1_FLAGS },
1043 { STRING_COMMA_LEN ("nosse4.2"), CPU_ANY_SSE4_2_FLAGS },
1044 { STRING_COMMA_LEN ("nosse4"), CPU_ANY_SSE4_1_FLAGS },
1045 { STRING_COMMA_LEN ("noavx"), CPU_ANY_AVX_FLAGS },
1046 { STRING_COMMA_LEN ("noavx2"), CPU_ANY_AVX2_FLAGS },
1047 { STRING_COMMA_LEN ("noavx512f"), CPU_ANY_AVX512F_FLAGS },
1048 { STRING_COMMA_LEN ("noavx512cd"), CPU_ANY_AVX512CD_FLAGS },
1049 { STRING_COMMA_LEN ("noavx512er"), CPU_ANY_AVX512ER_FLAGS },
1050 { STRING_COMMA_LEN ("noavx512pf"), CPU_ANY_AVX512PF_FLAGS },
1051 { STRING_COMMA_LEN ("noavx512dq"), CPU_ANY_AVX512DQ_FLAGS },
1052 { STRING_COMMA_LEN ("noavx512bw"), CPU_ANY_AVX512BW_FLAGS },
1053 { STRING_COMMA_LEN ("noavx512vl"), CPU_ANY_AVX512VL_FLAGS },
1054 { STRING_COMMA_LEN ("noavx512ifma"), CPU_ANY_AVX512IFMA_FLAGS },
1055 { STRING_COMMA_LEN ("noavx512vbmi"), CPU_ANY_AVX512VBMI_FLAGS },
1056 { STRING_COMMA_LEN ("noavx512_4fmaps"), CPU_ANY_AVX512_4FMAPS_FLAGS },
1057 { STRING_COMMA_LEN ("noavx512_4vnniw"), CPU_ANY_AVX512_4VNNIW_FLAGS },
1058 { STRING_COMMA_LEN ("noavx512_vpopcntdq"), CPU_ANY_AVX512_VPOPCNTDQ_FLAGS },
1059 { STRING_COMMA_LEN ("noavx512_vbmi2"), CPU_ANY_AVX512_VBMI2_FLAGS },
1060 { STRING_COMMA_LEN ("noavx512_vnni"), CPU_ANY_AVX512_VNNI_FLAGS },
1061 { STRING_COMMA_LEN ("noavx512_bitalg"), CPU_ANY_AVX512_BITALG_FLAGS },
1062 { STRING_COMMA_LEN ("noibt"), CPU_ANY_IBT_FLAGS },
1063 { STRING_COMMA_LEN ("noshstk"), CPU_ANY_SHSTK_FLAGS },
1064 };
1065
1066 #ifdef I386COFF
1067 /* Like s_lcomm_internal in gas/read.c but the alignment string
1068 is allowed to be optional. */
1069
1070 static symbolS *
1071 pe_lcomm_internal (int needs_align, symbolS *symbolP, addressT size)
1072 {
1073 addressT align = 0;
1074
1075 SKIP_WHITESPACE ();
1076
1077 if (needs_align
1078 && *input_line_pointer == ',')
1079 {
1080 align = parse_align (needs_align - 1);
1081
1082 if (align == (addressT) -1)
1083 return NULL;
1084 }
1085 else
1086 {
1087 if (size >= 8)
1088 align = 3;
1089 else if (size >= 4)
1090 align = 2;
1091 else if (size >= 2)
1092 align = 1;
1093 else
1094 align = 0;
1095 }
1096
1097 bss_alloc (symbolP, size, align);
1098 return symbolP;
1099 }
1100
1101 static void
1102 pe_lcomm (int needs_align)
1103 {
1104 s_comm_internal (needs_align * 2, pe_lcomm_internal);
1105 }
1106 #endif
1107
1108 const pseudo_typeS md_pseudo_table[] =
1109 {
1110 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
1111 {"align", s_align_bytes, 0},
1112 #else
1113 {"align", s_align_ptwo, 0},
1114 #endif
1115 {"arch", set_cpu_arch, 0},
1116 #ifndef I386COFF
1117 {"bss", s_bss, 0},
1118 #else
1119 {"lcomm", pe_lcomm, 1},
1120 #endif
1121 {"ffloat", float_cons, 'f'},
1122 {"dfloat", float_cons, 'd'},
1123 {"tfloat", float_cons, 'x'},
1124 {"value", cons, 2},
1125 {"slong", signed_cons, 4},
1126 {"noopt", s_ignore, 0},
1127 {"optim", s_ignore, 0},
1128 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
1129 {"code16", set_code_flag, CODE_16BIT},
1130 {"code32", set_code_flag, CODE_32BIT},
1131 #ifdef BFD64
1132 {"code64", set_code_flag, CODE_64BIT},
1133 #endif
1134 {"intel_syntax", set_intel_syntax, 1},
1135 {"att_syntax", set_intel_syntax, 0},
1136 {"intel_mnemonic", set_intel_mnemonic, 1},
1137 {"att_mnemonic", set_intel_mnemonic, 0},
1138 {"allow_index_reg", set_allow_index_reg, 1},
1139 {"disallow_index_reg", set_allow_index_reg, 0},
1140 {"sse_check", set_check, 0},
1141 {"operand_check", set_check, 1},
1142 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1143 {"largecomm", handle_large_common, 0},
1144 #else
1145 {"file", dwarf2_directive_file, 0},
1146 {"loc", dwarf2_directive_loc, 0},
1147 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
1148 #endif
1149 #ifdef TE_PE
1150 {"secrel32", pe_directive_secrel, 0},
1151 #endif
1152 {0, 0, 0}
1153 };
1154
1155 /* For interface with expression (). */
1156 extern char *input_line_pointer;
1157
1158 /* Hash table for instruction mnemonic lookup. */
1159 static struct hash_control *op_hash;
1160
1161 /* Hash table for register lookup. */
1162 static struct hash_control *reg_hash;
1163 \f
1164 /* Various efficient no-op patterns for aligning code labels.
1165 Note: Don't try to assemble the instructions in the comments.
1166 0L and 0w are not legal. */
1167 static const unsigned char f32_1[] =
1168 {0x90}; /* nop */
1169 static const unsigned char f32_2[] =
1170 {0x66,0x90}; /* xchg %ax,%ax */
1171 static const unsigned char f32_3[] =
1172 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1173 static const unsigned char f32_4[] =
1174 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1175 static const unsigned char f32_6[] =
1176 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1177 static const unsigned char f32_7[] =
1178 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1179 static const unsigned char f16_3[] =
1180 {0x8d,0x74,0x00}; /* lea 0(%si),%si */
1181 static const unsigned char f16_4[] =
1182 {0x8d,0xb4,0x00,0x00}; /* lea 0W(%si),%si */
1183 static const unsigned char jump_disp8[] =
1184 {0xeb}; /* jmp disp8 */
1185 static const unsigned char jump32_disp32[] =
1186 {0xe9}; /* jmp disp32 */
1187 static const unsigned char jump16_disp32[] =
1188 {0x66,0xe9}; /* jmp disp32 */
1189 /* 32-bit NOPs patterns. */
1190 static const unsigned char *const f32_patt[] = {
1191 f32_1, f32_2, f32_3, f32_4, NULL, f32_6, f32_7
1192 };
1193 /* 16-bit NOPs patterns. */
1194 static const unsigned char *const f16_patt[] = {
1195 f32_1, f32_2, f16_3, f16_4
1196 };
1197 /* nopl (%[re]ax) */
1198 static const unsigned char alt_3[] =
1199 {0x0f,0x1f,0x00};
1200 /* nopl 0(%[re]ax) */
1201 static const unsigned char alt_4[] =
1202 {0x0f,0x1f,0x40,0x00};
1203 /* nopl 0(%[re]ax,%[re]ax,1) */
1204 static const unsigned char alt_5[] =
1205 {0x0f,0x1f,0x44,0x00,0x00};
1206 /* nopw 0(%[re]ax,%[re]ax,1) */
1207 static const unsigned char alt_6[] =
1208 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1209 /* nopl 0L(%[re]ax) */
1210 static const unsigned char alt_7[] =
1211 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1212 /* nopl 0L(%[re]ax,%[re]ax,1) */
1213 static const unsigned char alt_8[] =
1214 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1215 /* nopw 0L(%[re]ax,%[re]ax,1) */
1216 static const unsigned char alt_9[] =
1217 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1218 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1219 static const unsigned char alt_10[] =
1220 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1221 /* data16 nopw %cs:0L(%eax,%eax,1) */
1222 static const unsigned char alt_11[] =
1223 {0x66,0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1224 /* 32-bit and 64-bit NOPs patterns. */
1225 static const unsigned char *const alt_patt[] = {
1226 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
1227 alt_9, alt_10, alt_11
1228 };
1229
1230 /* Genenerate COUNT bytes of NOPs to WHERE from PATT with the maximum
1231 size of a single NOP instruction MAX_SINGLE_NOP_SIZE. */
1232
1233 static void
1234 i386_output_nops (char *where, const unsigned char *const *patt,
1235 int count, int max_single_nop_size)
1236
1237 {
1238 /* Place the longer NOP first. */
1239 int last;
1240 int offset;
1241 const unsigned char *nops = patt[max_single_nop_size - 1];
1242
1243 /* Use the smaller one if the requsted one isn't available. */
1244 if (nops == NULL)
1245 {
1246 max_single_nop_size--;
1247 nops = patt[max_single_nop_size - 1];
1248 }
1249
1250 last = count % max_single_nop_size;
1251
1252 count -= last;
1253 for (offset = 0; offset < count; offset += max_single_nop_size)
1254 memcpy (where + offset, nops, max_single_nop_size);
1255
1256 if (last)
1257 {
1258 nops = patt[last - 1];
1259 if (nops == NULL)
1260 {
1261 /* Use the smaller one plus one-byte NOP if the needed one
1262 isn't available. */
1263 last--;
1264 nops = patt[last - 1];
1265 memcpy (where + offset, nops, last);
1266 where[offset + last] = *patt[0];
1267 }
1268 else
1269 memcpy (where + offset, nops, last);
1270 }
1271 }
1272
1273 static INLINE int
1274 fits_in_imm7 (offsetT num)
1275 {
1276 return (num & 0x7f) == num;
1277 }
1278
1279 static INLINE int
1280 fits_in_imm31 (offsetT num)
1281 {
1282 return (num & 0x7fffffff) == num;
1283 }
1284
1285 /* Genenerate COUNT bytes of NOPs to WHERE with the maximum size of a
1286 single NOP instruction LIMIT. */
1287
1288 void
1289 i386_generate_nops (fragS *fragP, char *where, offsetT count, int limit)
1290 {
1291 const unsigned char *const *patt = NULL;
1292 int max_single_nop_size;
1293 /* Maximum number of NOPs before switching to jump over NOPs. */
1294 int max_number_of_nops;
1295
1296 switch (fragP->fr_type)
1297 {
1298 case rs_fill_nop:
1299 case rs_align_code:
1300 break;
1301 default:
1302 return;
1303 }
1304
1305 /* We need to decide which NOP sequence to use for 32bit and
1306 64bit. When -mtune= is used:
1307
1308 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1309 PROCESSOR_GENERIC32, f32_patt will be used.
1310 2. For the rest, alt_patt will be used.
1311
1312 When -mtune= isn't used, alt_patt will be used if
1313 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
1314 be used.
1315
1316 When -march= or .arch is used, we can't use anything beyond
1317 cpu_arch_isa_flags. */
1318
1319 if (flag_code == CODE_16BIT)
1320 {
1321 patt = f16_patt;
1322 max_single_nop_size = sizeof (f16_patt) / sizeof (f16_patt[0]);
1323 /* Limit number of NOPs to 2 in 16-bit mode. */
1324 max_number_of_nops = 2;
1325 }
1326 else
1327 {
1328 if (fragP->tc_frag_data.isa == PROCESSOR_UNKNOWN)
1329 {
1330 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1331 switch (cpu_arch_tune)
1332 {
1333 case PROCESSOR_UNKNOWN:
1334 /* We use cpu_arch_isa_flags to check if we SHOULD
1335 optimize with nops. */
1336 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
1337 patt = alt_patt;
1338 else
1339 patt = f32_patt;
1340 break;
1341 case PROCESSOR_PENTIUM4:
1342 case PROCESSOR_NOCONA:
1343 case PROCESSOR_CORE:
1344 case PROCESSOR_CORE2:
1345 case PROCESSOR_COREI7:
1346 case PROCESSOR_L1OM:
1347 case PROCESSOR_K1OM:
1348 case PROCESSOR_GENERIC64:
1349 case PROCESSOR_K6:
1350 case PROCESSOR_ATHLON:
1351 case PROCESSOR_K8:
1352 case PROCESSOR_AMDFAM10:
1353 case PROCESSOR_BD:
1354 case PROCESSOR_ZNVER:
1355 case PROCESSOR_BT:
1356 patt = alt_patt;
1357 break;
1358 case PROCESSOR_I386:
1359 case PROCESSOR_I486:
1360 case PROCESSOR_PENTIUM:
1361 case PROCESSOR_PENTIUMPRO:
1362 case PROCESSOR_IAMCU:
1363 case PROCESSOR_GENERIC32:
1364 patt = f32_patt;
1365 break;
1366 }
1367 }
1368 else
1369 {
1370 switch (fragP->tc_frag_data.tune)
1371 {
1372 case PROCESSOR_UNKNOWN:
1373 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1374 PROCESSOR_UNKNOWN. */
1375 abort ();
1376 break;
1377
1378 case PROCESSOR_I386:
1379 case PROCESSOR_I486:
1380 case PROCESSOR_PENTIUM:
1381 case PROCESSOR_IAMCU:
1382 case PROCESSOR_K6:
1383 case PROCESSOR_ATHLON:
1384 case PROCESSOR_K8:
1385 case PROCESSOR_AMDFAM10:
1386 case PROCESSOR_BD:
1387 case PROCESSOR_ZNVER:
1388 case PROCESSOR_BT:
1389 case PROCESSOR_GENERIC32:
1390 /* We use cpu_arch_isa_flags to check if we CAN optimize
1391 with nops. */
1392 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
1393 patt = alt_patt;
1394 else
1395 patt = f32_patt;
1396 break;
1397 case PROCESSOR_PENTIUMPRO:
1398 case PROCESSOR_PENTIUM4:
1399 case PROCESSOR_NOCONA:
1400 case PROCESSOR_CORE:
1401 case PROCESSOR_CORE2:
1402 case PROCESSOR_COREI7:
1403 case PROCESSOR_L1OM:
1404 case PROCESSOR_K1OM:
1405 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
1406 patt = alt_patt;
1407 else
1408 patt = f32_patt;
1409 break;
1410 case PROCESSOR_GENERIC64:
1411 patt = alt_patt;
1412 break;
1413 }
1414 }
1415
1416 if (patt == f32_patt)
1417 {
1418 max_single_nop_size = sizeof (f32_patt) / sizeof (f32_patt[0]);
1419 /* Limit number of NOPs to 2 for older processors. */
1420 max_number_of_nops = 2;
1421 }
1422 else
1423 {
1424 max_single_nop_size = sizeof (alt_patt) / sizeof (alt_patt[0]);
1425 /* Limit number of NOPs to 7 for newer processors. */
1426 max_number_of_nops = 7;
1427 }
1428 }
1429
1430 if (limit == 0)
1431 limit = max_single_nop_size;
1432
1433 if (fragP->fr_type == rs_fill_nop)
1434 {
1435 /* Output NOPs for .nop directive. */
1436 if (limit > max_single_nop_size)
1437 {
1438 as_bad_where (fragP->fr_file, fragP->fr_line,
1439 _("invalid single nop size: %d "
1440 "(expect within [0, %d])"),
1441 limit, max_single_nop_size);
1442 return;
1443 }
1444 }
1445 else
1446 fragP->fr_var = count;
1447
1448 if ((count / max_single_nop_size) > max_number_of_nops)
1449 {
1450 /* Generate jump over NOPs. */
1451 offsetT disp = count - 2;
1452 if (fits_in_imm7 (disp))
1453 {
1454 /* Use "jmp disp8" if possible. */
1455 count = disp;
1456 where[0] = jump_disp8[0];
1457 where[1] = count;
1458 where += 2;
1459 }
1460 else
1461 {
1462 unsigned int size_of_jump;
1463
1464 if (flag_code == CODE_16BIT)
1465 {
1466 where[0] = jump16_disp32[0];
1467 where[1] = jump16_disp32[1];
1468 size_of_jump = 2;
1469 }
1470 else
1471 {
1472 where[0] = jump32_disp32[0];
1473 size_of_jump = 1;
1474 }
1475
1476 count -= size_of_jump + 4;
1477 if (!fits_in_imm31 (count))
1478 {
1479 as_bad_where (fragP->fr_file, fragP->fr_line,
1480 _("jump over nop padding out of range"));
1481 return;
1482 }
1483
1484 md_number_to_chars (where + size_of_jump, count, 4);
1485 where += size_of_jump + 4;
1486 }
1487 }
1488
1489 /* Generate multiple NOPs. */
1490 i386_output_nops (where, patt, count, limit);
1491 }
1492
1493 static INLINE int
1494 operand_type_all_zero (const union i386_operand_type *x)
1495 {
1496 switch (ARRAY_SIZE(x->array))
1497 {
1498 case 3:
1499 if (x->array[2])
1500 return 0;
1501 /* Fall through. */
1502 case 2:
1503 if (x->array[1])
1504 return 0;
1505 /* Fall through. */
1506 case 1:
1507 return !x->array[0];
1508 default:
1509 abort ();
1510 }
1511 }
1512
1513 static INLINE void
1514 operand_type_set (union i386_operand_type *x, unsigned int v)
1515 {
1516 switch (ARRAY_SIZE(x->array))
1517 {
1518 case 3:
1519 x->array[2] = v;
1520 /* Fall through. */
1521 case 2:
1522 x->array[1] = v;
1523 /* Fall through. */
1524 case 1:
1525 x->array[0] = v;
1526 /* Fall through. */
1527 break;
1528 default:
1529 abort ();
1530 }
1531 }
1532
1533 static INLINE int
1534 operand_type_equal (const union i386_operand_type *x,
1535 const union i386_operand_type *y)
1536 {
1537 switch (ARRAY_SIZE(x->array))
1538 {
1539 case 3:
1540 if (x->array[2] != y->array[2])
1541 return 0;
1542 /* Fall through. */
1543 case 2:
1544 if (x->array[1] != y->array[1])
1545 return 0;
1546 /* Fall through. */
1547 case 1:
1548 return x->array[0] == y->array[0];
1549 break;
1550 default:
1551 abort ();
1552 }
1553 }
1554
1555 static INLINE int
1556 cpu_flags_all_zero (const union i386_cpu_flags *x)
1557 {
1558 switch (ARRAY_SIZE(x->array))
1559 {
1560 case 4:
1561 if (x->array[3])
1562 return 0;
1563 /* Fall through. */
1564 case 3:
1565 if (x->array[2])
1566 return 0;
1567 /* Fall through. */
1568 case 2:
1569 if (x->array[1])
1570 return 0;
1571 /* Fall through. */
1572 case 1:
1573 return !x->array[0];
1574 default:
1575 abort ();
1576 }
1577 }
1578
1579 static INLINE int
1580 cpu_flags_equal (const union i386_cpu_flags *x,
1581 const union i386_cpu_flags *y)
1582 {
1583 switch (ARRAY_SIZE(x->array))
1584 {
1585 case 4:
1586 if (x->array[3] != y->array[3])
1587 return 0;
1588 /* Fall through. */
1589 case 3:
1590 if (x->array[2] != y->array[2])
1591 return 0;
1592 /* Fall through. */
1593 case 2:
1594 if (x->array[1] != y->array[1])
1595 return 0;
1596 /* Fall through. */
1597 case 1:
1598 return x->array[0] == y->array[0];
1599 break;
1600 default:
1601 abort ();
1602 }
1603 }
1604
1605 static INLINE int
1606 cpu_flags_check_cpu64 (i386_cpu_flags f)
1607 {
1608 return !((flag_code == CODE_64BIT && f.bitfield.cpuno64)
1609 || (flag_code != CODE_64BIT && f.bitfield.cpu64));
1610 }
1611
1612 static INLINE i386_cpu_flags
1613 cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y)
1614 {
1615 switch (ARRAY_SIZE (x.array))
1616 {
1617 case 4:
1618 x.array [3] &= y.array [3];
1619 /* Fall through. */
1620 case 3:
1621 x.array [2] &= y.array [2];
1622 /* Fall through. */
1623 case 2:
1624 x.array [1] &= y.array [1];
1625 /* Fall through. */
1626 case 1:
1627 x.array [0] &= y.array [0];
1628 break;
1629 default:
1630 abort ();
1631 }
1632 return x;
1633 }
1634
1635 static INLINE i386_cpu_flags
1636 cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y)
1637 {
1638 switch (ARRAY_SIZE (x.array))
1639 {
1640 case 4:
1641 x.array [3] |= y.array [3];
1642 /* Fall through. */
1643 case 3:
1644 x.array [2] |= y.array [2];
1645 /* Fall through. */
1646 case 2:
1647 x.array [1] |= y.array [1];
1648 /* Fall through. */
1649 case 1:
1650 x.array [0] |= y.array [0];
1651 break;
1652 default:
1653 abort ();
1654 }
1655 return x;
1656 }
1657
1658 static INLINE i386_cpu_flags
1659 cpu_flags_and_not (i386_cpu_flags x, i386_cpu_flags y)
1660 {
1661 switch (ARRAY_SIZE (x.array))
1662 {
1663 case 4:
1664 x.array [3] &= ~y.array [3];
1665 /* Fall through. */
1666 case 3:
1667 x.array [2] &= ~y.array [2];
1668 /* Fall through. */
1669 case 2:
1670 x.array [1] &= ~y.array [1];
1671 /* Fall through. */
1672 case 1:
1673 x.array [0] &= ~y.array [0];
1674 break;
1675 default:
1676 abort ();
1677 }
1678 return x;
1679 }
1680
1681 #define CPU_FLAGS_ARCH_MATCH 0x1
1682 #define CPU_FLAGS_64BIT_MATCH 0x2
1683
1684 #define CPU_FLAGS_PERFECT_MATCH \
1685 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_64BIT_MATCH)
1686
1687 /* Return CPU flags match bits. */
1688
1689 static int
1690 cpu_flags_match (const insn_template *t)
1691 {
1692 i386_cpu_flags x = t->cpu_flags;
1693 int match = cpu_flags_check_cpu64 (x) ? CPU_FLAGS_64BIT_MATCH : 0;
1694
1695 x.bitfield.cpu64 = 0;
1696 x.bitfield.cpuno64 = 0;
1697
1698 if (cpu_flags_all_zero (&x))
1699 {
1700 /* This instruction is available on all archs. */
1701 match |= CPU_FLAGS_ARCH_MATCH;
1702 }
1703 else
1704 {
1705 /* This instruction is available only on some archs. */
1706 i386_cpu_flags cpu = cpu_arch_flags;
1707
1708 /* AVX512VL is no standalone feature - match it and then strip it. */
1709 if (x.bitfield.cpuavx512vl && !cpu.bitfield.cpuavx512vl)
1710 return match;
1711 x.bitfield.cpuavx512vl = 0;
1712
1713 cpu = cpu_flags_and (x, cpu);
1714 if (!cpu_flags_all_zero (&cpu))
1715 {
1716 if (x.bitfield.cpuavx)
1717 {
1718 /* We need to check a few extra flags with AVX. */
1719 if (cpu.bitfield.cpuavx
1720 && (!t->opcode_modifier.sse2avx || sse2avx)
1721 && (!x.bitfield.cpuaes || cpu.bitfield.cpuaes)
1722 && (!x.bitfield.cpugfni || cpu.bitfield.cpugfni)
1723 && (!x.bitfield.cpupclmul || cpu.bitfield.cpupclmul))
1724 match |= CPU_FLAGS_ARCH_MATCH;
1725 }
1726 else if (x.bitfield.cpuavx512f)
1727 {
1728 /* We need to check a few extra flags with AVX512F. */
1729 if (cpu.bitfield.cpuavx512f
1730 && (!x.bitfield.cpugfni || cpu.bitfield.cpugfni)
1731 && (!x.bitfield.cpuvaes || cpu.bitfield.cpuvaes)
1732 && (!x.bitfield.cpuvpclmulqdq || cpu.bitfield.cpuvpclmulqdq))
1733 match |= CPU_FLAGS_ARCH_MATCH;
1734 }
1735 else
1736 match |= CPU_FLAGS_ARCH_MATCH;
1737 }
1738 }
1739 return match;
1740 }
1741
1742 static INLINE i386_operand_type
1743 operand_type_and (i386_operand_type x, i386_operand_type y)
1744 {
1745 switch (ARRAY_SIZE (x.array))
1746 {
1747 case 3:
1748 x.array [2] &= y.array [2];
1749 /* Fall through. */
1750 case 2:
1751 x.array [1] &= y.array [1];
1752 /* Fall through. */
1753 case 1:
1754 x.array [0] &= y.array [0];
1755 break;
1756 default:
1757 abort ();
1758 }
1759 return x;
1760 }
1761
1762 static INLINE i386_operand_type
1763 operand_type_and_not (i386_operand_type x, i386_operand_type y)
1764 {
1765 switch (ARRAY_SIZE (x.array))
1766 {
1767 case 3:
1768 x.array [2] &= ~y.array [2];
1769 /* Fall through. */
1770 case 2:
1771 x.array [1] &= ~y.array [1];
1772 /* Fall through. */
1773 case 1:
1774 x.array [0] &= ~y.array [0];
1775 break;
1776 default:
1777 abort ();
1778 }
1779 return x;
1780 }
1781
1782 static INLINE i386_operand_type
1783 operand_type_or (i386_operand_type x, i386_operand_type y)
1784 {
1785 switch (ARRAY_SIZE (x.array))
1786 {
1787 case 3:
1788 x.array [2] |= y.array [2];
1789 /* Fall through. */
1790 case 2:
1791 x.array [1] |= y.array [1];
1792 /* Fall through. */
1793 case 1:
1794 x.array [0] |= y.array [0];
1795 break;
1796 default:
1797 abort ();
1798 }
1799 return x;
1800 }
1801
1802 static INLINE i386_operand_type
1803 operand_type_xor (i386_operand_type x, i386_operand_type y)
1804 {
1805 switch (ARRAY_SIZE (x.array))
1806 {
1807 case 3:
1808 x.array [2] ^= y.array [2];
1809 /* Fall through. */
1810 case 2:
1811 x.array [1] ^= y.array [1];
1812 /* Fall through. */
1813 case 1:
1814 x.array [0] ^= y.array [0];
1815 break;
1816 default:
1817 abort ();
1818 }
1819 return x;
1820 }
1821
1822 static const i386_operand_type acc32 = OPERAND_TYPE_ACC32;
1823 static const i386_operand_type acc64 = OPERAND_TYPE_ACC64;
1824 static const i386_operand_type control = OPERAND_TYPE_CONTROL;
1825 static const i386_operand_type inoutportreg
1826 = OPERAND_TYPE_INOUTPORTREG;
1827 static const i386_operand_type reg16_inoutportreg
1828 = OPERAND_TYPE_REG16_INOUTPORTREG;
1829 static const i386_operand_type disp16 = OPERAND_TYPE_DISP16;
1830 static const i386_operand_type disp32 = OPERAND_TYPE_DISP32;
1831 static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S;
1832 static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32;
1833 static const i386_operand_type anydisp
1834 = OPERAND_TYPE_ANYDISP;
1835 static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM;
1836 static const i386_operand_type regmask = OPERAND_TYPE_REGMASK;
1837 static const i386_operand_type imm8 = OPERAND_TYPE_IMM8;
1838 static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S;
1839 static const i386_operand_type imm16 = OPERAND_TYPE_IMM16;
1840 static const i386_operand_type imm32 = OPERAND_TYPE_IMM32;
1841 static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S;
1842 static const i386_operand_type imm64 = OPERAND_TYPE_IMM64;
1843 static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32;
1844 static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S;
1845 static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S;
1846 static const i386_operand_type vec_imm4 = OPERAND_TYPE_VEC_IMM4;
1847
1848 enum operand_type
1849 {
1850 reg,
1851 imm,
1852 disp,
1853 anymem
1854 };
1855
1856 static INLINE int
1857 operand_type_check (i386_operand_type t, enum operand_type c)
1858 {
1859 switch (c)
1860 {
1861 case reg:
1862 return t.bitfield.reg;
1863
1864 case imm:
1865 return (t.bitfield.imm8
1866 || t.bitfield.imm8s
1867 || t.bitfield.imm16
1868 || t.bitfield.imm32
1869 || t.bitfield.imm32s
1870 || t.bitfield.imm64);
1871
1872 case disp:
1873 return (t.bitfield.disp8
1874 || t.bitfield.disp16
1875 || t.bitfield.disp32
1876 || t.bitfield.disp32s
1877 || t.bitfield.disp64);
1878
1879 case anymem:
1880 return (t.bitfield.disp8
1881 || t.bitfield.disp16
1882 || t.bitfield.disp32
1883 || t.bitfield.disp32s
1884 || t.bitfield.disp64
1885 || t.bitfield.baseindex);
1886
1887 default:
1888 abort ();
1889 }
1890
1891 return 0;
1892 }
1893
1894 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit/80bit on
1895 operand J for instruction template T. */
1896
1897 static INLINE int
1898 match_reg_size (const insn_template *t, unsigned int j)
1899 {
1900 return !((i.types[j].bitfield.byte
1901 && !t->operand_types[j].bitfield.byte)
1902 || (i.types[j].bitfield.word
1903 && !t->operand_types[j].bitfield.word)
1904 || (i.types[j].bitfield.dword
1905 && !t->operand_types[j].bitfield.dword)
1906 || (i.types[j].bitfield.qword
1907 && !t->operand_types[j].bitfield.qword)
1908 || (i.types[j].bitfield.tbyte
1909 && !t->operand_types[j].bitfield.tbyte));
1910 }
1911
1912 /* Return 1 if there is no conflict in SIMD register on
1913 operand J for instruction template T. */
1914
1915 static INLINE int
1916 match_simd_size (const insn_template *t, unsigned int j)
1917 {
1918 return !((i.types[j].bitfield.xmmword
1919 && !t->operand_types[j].bitfield.xmmword)
1920 || (i.types[j].bitfield.ymmword
1921 && !t->operand_types[j].bitfield.ymmword)
1922 || (i.types[j].bitfield.zmmword
1923 && !t->operand_types[j].bitfield.zmmword));
1924 }
1925
1926 /* Return 1 if there is no conflict in any size on operand J for
1927 instruction template T. */
1928
1929 static INLINE int
1930 match_mem_size (const insn_template *t, unsigned int j)
1931 {
1932 return (match_reg_size (t, j)
1933 && !((i.types[j].bitfield.unspecified
1934 && !i.broadcast
1935 && !t->operand_types[j].bitfield.unspecified)
1936 || (i.types[j].bitfield.fword
1937 && !t->operand_types[j].bitfield.fword)
1938 /* For scalar opcode templates to allow register and memory
1939 operands at the same time, some special casing is needed
1940 here. */
1941 || ((t->operand_types[j].bitfield.regsimd
1942 && !t->opcode_modifier.broadcast
1943 && (t->operand_types[j].bitfield.dword
1944 || t->operand_types[j].bitfield.qword))
1945 ? (i.types[j].bitfield.xmmword
1946 || i.types[j].bitfield.ymmword
1947 || i.types[j].bitfield.zmmword)
1948 : !match_simd_size(t, j))));
1949 }
1950
1951 /* Return 1 if there is no size conflict on any operands for
1952 instruction template T. */
1953
1954 static INLINE int
1955 operand_size_match (const insn_template *t)
1956 {
1957 unsigned int j;
1958 int match = 1;
1959
1960 /* Don't check jump instructions. */
1961 if (t->opcode_modifier.jump
1962 || t->opcode_modifier.jumpbyte
1963 || t->opcode_modifier.jumpdword
1964 || t->opcode_modifier.jumpintersegment)
1965 return match;
1966
1967 /* Check memory and accumulator operand size. */
1968 for (j = 0; j < i.operands; j++)
1969 {
1970 if (!i.types[j].bitfield.reg && !i.types[j].bitfield.regsimd
1971 && t->operand_types[j].bitfield.anysize)
1972 continue;
1973
1974 if (t->operand_types[j].bitfield.reg
1975 && !match_reg_size (t, j))
1976 {
1977 match = 0;
1978 break;
1979 }
1980
1981 if (t->operand_types[j].bitfield.regsimd
1982 && !match_simd_size (t, j))
1983 {
1984 match = 0;
1985 break;
1986 }
1987
1988 if (t->operand_types[j].bitfield.acc
1989 && (!match_reg_size (t, j) || !match_simd_size (t, j)))
1990 {
1991 match = 0;
1992 break;
1993 }
1994
1995 if (i.types[j].bitfield.mem && !match_mem_size (t, j))
1996 {
1997 match = 0;
1998 break;
1999 }
2000 }
2001
2002 if (match)
2003 return match;
2004 else if (!t->opcode_modifier.d)
2005 {
2006 mismatch:
2007 i.error = operand_size_mismatch;
2008 return 0;
2009 }
2010
2011 /* Check reverse. */
2012 gas_assert (i.operands == 2);
2013
2014 match = 1;
2015 for (j = 0; j < 2; j++)
2016 {
2017 if ((t->operand_types[j].bitfield.reg
2018 || t->operand_types[j].bitfield.acc)
2019 && !match_reg_size (t, j ? 0 : 1))
2020 goto mismatch;
2021
2022 if (i.types[j].bitfield.mem
2023 && !match_mem_size (t, j ? 0 : 1))
2024 goto mismatch;
2025 }
2026
2027 return match;
2028 }
2029
2030 static INLINE int
2031 operand_type_match (i386_operand_type overlap,
2032 i386_operand_type given)
2033 {
2034 i386_operand_type temp = overlap;
2035
2036 temp.bitfield.jumpabsolute = 0;
2037 temp.bitfield.unspecified = 0;
2038 temp.bitfield.byte = 0;
2039 temp.bitfield.word = 0;
2040 temp.bitfield.dword = 0;
2041 temp.bitfield.fword = 0;
2042 temp.bitfield.qword = 0;
2043 temp.bitfield.tbyte = 0;
2044 temp.bitfield.xmmword = 0;
2045 temp.bitfield.ymmword = 0;
2046 temp.bitfield.zmmword = 0;
2047 if (operand_type_all_zero (&temp))
2048 goto mismatch;
2049
2050 if (given.bitfield.baseindex == overlap.bitfield.baseindex
2051 && given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute)
2052 return 1;
2053
2054 mismatch:
2055 i.error = operand_type_mismatch;
2056 return 0;
2057 }
2058
2059 /* If given types g0 and g1 are registers they must be of the same type
2060 unless the expected operand type register overlap is null.
2061 Memory operand size of certain SIMD instructions is also being checked
2062 here. */
2063
2064 static INLINE int
2065 operand_type_register_match (i386_operand_type g0,
2066 i386_operand_type t0,
2067 i386_operand_type g1,
2068 i386_operand_type t1)
2069 {
2070 if (!g0.bitfield.reg
2071 && !g0.bitfield.regsimd
2072 && (!operand_type_check (g0, anymem)
2073 || g0.bitfield.unspecified
2074 || !t0.bitfield.regsimd))
2075 return 1;
2076
2077 if (!g1.bitfield.reg
2078 && !g1.bitfield.regsimd
2079 && (!operand_type_check (g1, anymem)
2080 || g1.bitfield.unspecified
2081 || !t1.bitfield.regsimd))
2082 return 1;
2083
2084 if (g0.bitfield.byte == g1.bitfield.byte
2085 && g0.bitfield.word == g1.bitfield.word
2086 && g0.bitfield.dword == g1.bitfield.dword
2087 && g0.bitfield.qword == g1.bitfield.qword
2088 && g0.bitfield.xmmword == g1.bitfield.xmmword
2089 && g0.bitfield.ymmword == g1.bitfield.ymmword
2090 && g0.bitfield.zmmword == g1.bitfield.zmmword)
2091 return 1;
2092
2093 if (!(t0.bitfield.byte & t1.bitfield.byte)
2094 && !(t0.bitfield.word & t1.bitfield.word)
2095 && !(t0.bitfield.dword & t1.bitfield.dword)
2096 && !(t0.bitfield.qword & t1.bitfield.qword)
2097 && !(t0.bitfield.xmmword & t1.bitfield.xmmword)
2098 && !(t0.bitfield.ymmword & t1.bitfield.ymmword)
2099 && !(t0.bitfield.zmmword & t1.bitfield.zmmword))
2100 return 1;
2101
2102 i.error = register_type_mismatch;
2103
2104 return 0;
2105 }
2106
2107 static INLINE unsigned int
2108 register_number (const reg_entry *r)
2109 {
2110 unsigned int nr = r->reg_num;
2111
2112 if (r->reg_flags & RegRex)
2113 nr += 8;
2114
2115 if (r->reg_flags & RegVRex)
2116 nr += 16;
2117
2118 return nr;
2119 }
2120
2121 static INLINE unsigned int
2122 mode_from_disp_size (i386_operand_type t)
2123 {
2124 if (t.bitfield.disp8)
2125 return 1;
2126 else if (t.bitfield.disp16
2127 || t.bitfield.disp32
2128 || t.bitfield.disp32s)
2129 return 2;
2130 else
2131 return 0;
2132 }
2133
2134 static INLINE int
2135 fits_in_signed_byte (addressT num)
2136 {
2137 return num + 0x80 <= 0xff;
2138 }
2139
2140 static INLINE int
2141 fits_in_unsigned_byte (addressT num)
2142 {
2143 return num <= 0xff;
2144 }
2145
2146 static INLINE int
2147 fits_in_unsigned_word (addressT num)
2148 {
2149 return num <= 0xffff;
2150 }
2151
2152 static INLINE int
2153 fits_in_signed_word (addressT num)
2154 {
2155 return num + 0x8000 <= 0xffff;
2156 }
2157
2158 static INLINE int
2159 fits_in_signed_long (addressT num ATTRIBUTE_UNUSED)
2160 {
2161 #ifndef BFD64
2162 return 1;
2163 #else
2164 return num + 0x80000000 <= 0xffffffff;
2165 #endif
2166 } /* fits_in_signed_long() */
2167
2168 static INLINE int
2169 fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED)
2170 {
2171 #ifndef BFD64
2172 return 1;
2173 #else
2174 return num <= 0xffffffff;
2175 #endif
2176 } /* fits_in_unsigned_long() */
2177
2178 static INLINE int
2179 fits_in_disp8 (offsetT num)
2180 {
2181 int shift = i.memshift;
2182 unsigned int mask;
2183
2184 if (shift == -1)
2185 abort ();
2186
2187 mask = (1 << shift) - 1;
2188
2189 /* Return 0 if NUM isn't properly aligned. */
2190 if ((num & mask))
2191 return 0;
2192
2193 /* Check if NUM will fit in 8bit after shift. */
2194 return fits_in_signed_byte (num >> shift);
2195 }
2196
2197 static INLINE int
2198 fits_in_imm4 (offsetT num)
2199 {
2200 return (num & 0xf) == num;
2201 }
2202
2203 static i386_operand_type
2204 smallest_imm_type (offsetT num)
2205 {
2206 i386_operand_type t;
2207
2208 operand_type_set (&t, 0);
2209 t.bitfield.imm64 = 1;
2210
2211 if (cpu_arch_tune != PROCESSOR_I486 && num == 1)
2212 {
2213 /* This code is disabled on the 486 because all the Imm1 forms
2214 in the opcode table are slower on the i486. They're the
2215 versions with the implicitly specified single-position
2216 displacement, which has another syntax if you really want to
2217 use that form. */
2218 t.bitfield.imm1 = 1;
2219 t.bitfield.imm8 = 1;
2220 t.bitfield.imm8s = 1;
2221 t.bitfield.imm16 = 1;
2222 t.bitfield.imm32 = 1;
2223 t.bitfield.imm32s = 1;
2224 }
2225 else if (fits_in_signed_byte (num))
2226 {
2227 t.bitfield.imm8 = 1;
2228 t.bitfield.imm8s = 1;
2229 t.bitfield.imm16 = 1;
2230 t.bitfield.imm32 = 1;
2231 t.bitfield.imm32s = 1;
2232 }
2233 else if (fits_in_unsigned_byte (num))
2234 {
2235 t.bitfield.imm8 = 1;
2236 t.bitfield.imm16 = 1;
2237 t.bitfield.imm32 = 1;
2238 t.bitfield.imm32s = 1;
2239 }
2240 else if (fits_in_signed_word (num) || fits_in_unsigned_word (num))
2241 {
2242 t.bitfield.imm16 = 1;
2243 t.bitfield.imm32 = 1;
2244 t.bitfield.imm32s = 1;
2245 }
2246 else if (fits_in_signed_long (num))
2247 {
2248 t.bitfield.imm32 = 1;
2249 t.bitfield.imm32s = 1;
2250 }
2251 else if (fits_in_unsigned_long (num))
2252 t.bitfield.imm32 = 1;
2253
2254 return t;
2255 }
2256
2257 static offsetT
2258 offset_in_range (offsetT val, int size)
2259 {
2260 addressT mask;
2261
2262 switch (size)
2263 {
2264 case 1: mask = ((addressT) 1 << 8) - 1; break;
2265 case 2: mask = ((addressT) 1 << 16) - 1; break;
2266 case 4: mask = ((addressT) 2 << 31) - 1; break;
2267 #ifdef BFD64
2268 case 8: mask = ((addressT) 2 << 63) - 1; break;
2269 #endif
2270 default: abort ();
2271 }
2272
2273 #ifdef BFD64
2274 /* If BFD64, sign extend val for 32bit address mode. */
2275 if (flag_code != CODE_64BIT
2276 || i.prefix[ADDR_PREFIX])
2277 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
2278 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
2279 #endif
2280
2281 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
2282 {
2283 char buf1[40], buf2[40];
2284
2285 sprint_value (buf1, val);
2286 sprint_value (buf2, val & mask);
2287 as_warn (_("%s shortened to %s"), buf1, buf2);
2288 }
2289 return val & mask;
2290 }
2291
2292 enum PREFIX_GROUP
2293 {
2294 PREFIX_EXIST = 0,
2295 PREFIX_LOCK,
2296 PREFIX_REP,
2297 PREFIX_DS,
2298 PREFIX_OTHER
2299 };
2300
2301 /* Returns
2302 a. PREFIX_EXIST if attempting to add a prefix where one from the
2303 same class already exists.
2304 b. PREFIX_LOCK if lock prefix is added.
2305 c. PREFIX_REP if rep/repne prefix is added.
2306 d. PREFIX_DS if ds prefix is added.
2307 e. PREFIX_OTHER if other prefix is added.
2308 */
2309
2310 static enum PREFIX_GROUP
2311 add_prefix (unsigned int prefix)
2312 {
2313 enum PREFIX_GROUP ret = PREFIX_OTHER;
2314 unsigned int q;
2315
2316 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
2317 && flag_code == CODE_64BIT)
2318 {
2319 if ((i.prefix[REX_PREFIX] & prefix & REX_W)
2320 || ((i.prefix[REX_PREFIX] & (REX_R | REX_X | REX_B))
2321 && (prefix & (REX_R | REX_X | REX_B))))
2322 ret = PREFIX_EXIST;
2323 q = REX_PREFIX;
2324 }
2325 else
2326 {
2327 switch (prefix)
2328 {
2329 default:
2330 abort ();
2331
2332 case DS_PREFIX_OPCODE:
2333 ret = PREFIX_DS;
2334 /* Fall through. */
2335 case CS_PREFIX_OPCODE:
2336 case ES_PREFIX_OPCODE:
2337 case FS_PREFIX_OPCODE:
2338 case GS_PREFIX_OPCODE:
2339 case SS_PREFIX_OPCODE:
2340 q = SEG_PREFIX;
2341 break;
2342
2343 case REPNE_PREFIX_OPCODE:
2344 case REPE_PREFIX_OPCODE:
2345 q = REP_PREFIX;
2346 ret = PREFIX_REP;
2347 break;
2348
2349 case LOCK_PREFIX_OPCODE:
2350 q = LOCK_PREFIX;
2351 ret = PREFIX_LOCK;
2352 break;
2353
2354 case FWAIT_OPCODE:
2355 q = WAIT_PREFIX;
2356 break;
2357
2358 case ADDR_PREFIX_OPCODE:
2359 q = ADDR_PREFIX;
2360 break;
2361
2362 case DATA_PREFIX_OPCODE:
2363 q = DATA_PREFIX;
2364 break;
2365 }
2366 if (i.prefix[q] != 0)
2367 ret = PREFIX_EXIST;
2368 }
2369
2370 if (ret)
2371 {
2372 if (!i.prefix[q])
2373 ++i.prefixes;
2374 i.prefix[q] |= prefix;
2375 }
2376 else
2377 as_bad (_("same type of prefix used twice"));
2378
2379 return ret;
2380 }
2381
2382 static void
2383 update_code_flag (int value, int check)
2384 {
2385 PRINTF_LIKE ((*as_error));
2386
2387 flag_code = (enum flag_code) value;
2388 if (flag_code == CODE_64BIT)
2389 {
2390 cpu_arch_flags.bitfield.cpu64 = 1;
2391 cpu_arch_flags.bitfield.cpuno64 = 0;
2392 }
2393 else
2394 {
2395 cpu_arch_flags.bitfield.cpu64 = 0;
2396 cpu_arch_flags.bitfield.cpuno64 = 1;
2397 }
2398 if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm )
2399 {
2400 if (check)
2401 as_error = as_fatal;
2402 else
2403 as_error = as_bad;
2404 (*as_error) (_("64bit mode not supported on `%s'."),
2405 cpu_arch_name ? cpu_arch_name : default_arch);
2406 }
2407 if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386)
2408 {
2409 if (check)
2410 as_error = as_fatal;
2411 else
2412 as_error = as_bad;
2413 (*as_error) (_("32bit mode not supported on `%s'."),
2414 cpu_arch_name ? cpu_arch_name : default_arch);
2415 }
2416 stackop_size = '\0';
2417 }
2418
2419 static void
2420 set_code_flag (int value)
2421 {
2422 update_code_flag (value, 0);
2423 }
2424
2425 static void
2426 set_16bit_gcc_code_flag (int new_code_flag)
2427 {
2428 flag_code = (enum flag_code) new_code_flag;
2429 if (flag_code != CODE_16BIT)
2430 abort ();
2431 cpu_arch_flags.bitfield.cpu64 = 0;
2432 cpu_arch_flags.bitfield.cpuno64 = 1;
2433 stackop_size = LONG_MNEM_SUFFIX;
2434 }
2435
2436 static void
2437 set_intel_syntax (int syntax_flag)
2438 {
2439 /* Find out if register prefixing is specified. */
2440 int ask_naked_reg = 0;
2441
2442 SKIP_WHITESPACE ();
2443 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2444 {
2445 char *string;
2446 int e = get_symbol_name (&string);
2447
2448 if (strcmp (string, "prefix") == 0)
2449 ask_naked_reg = 1;
2450 else if (strcmp (string, "noprefix") == 0)
2451 ask_naked_reg = -1;
2452 else
2453 as_bad (_("bad argument to syntax directive."));
2454 (void) restore_line_pointer (e);
2455 }
2456 demand_empty_rest_of_line ();
2457
2458 intel_syntax = syntax_flag;
2459
2460 if (ask_naked_reg == 0)
2461 allow_naked_reg = (intel_syntax
2462 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
2463 else
2464 allow_naked_reg = (ask_naked_reg < 0);
2465
2466 expr_set_rank (O_full_ptr, syntax_flag ? 10 : 0);
2467
2468 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
2469 identifier_chars['$'] = intel_syntax ? '$' : 0;
2470 register_prefix = allow_naked_reg ? "" : "%";
2471 }
2472
2473 static void
2474 set_intel_mnemonic (int mnemonic_flag)
2475 {
2476 intel_mnemonic = mnemonic_flag;
2477 }
2478
2479 static void
2480 set_allow_index_reg (int flag)
2481 {
2482 allow_index_reg = flag;
2483 }
2484
2485 static void
2486 set_check (int what)
2487 {
2488 enum check_kind *kind;
2489 const char *str;
2490
2491 if (what)
2492 {
2493 kind = &operand_check;
2494 str = "operand";
2495 }
2496 else
2497 {
2498 kind = &sse_check;
2499 str = "sse";
2500 }
2501
2502 SKIP_WHITESPACE ();
2503
2504 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2505 {
2506 char *string;
2507 int e = get_symbol_name (&string);
2508
2509 if (strcmp (string, "none") == 0)
2510 *kind = check_none;
2511 else if (strcmp (string, "warning") == 0)
2512 *kind = check_warning;
2513 else if (strcmp (string, "error") == 0)
2514 *kind = check_error;
2515 else
2516 as_bad (_("bad argument to %s_check directive."), str);
2517 (void) restore_line_pointer (e);
2518 }
2519 else
2520 as_bad (_("missing argument for %s_check directive"), str);
2521
2522 demand_empty_rest_of_line ();
2523 }
2524
2525 static void
2526 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED,
2527 i386_cpu_flags new_flag ATTRIBUTE_UNUSED)
2528 {
2529 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2530 static const char *arch;
2531
2532 /* Intel LIOM is only supported on ELF. */
2533 if (!IS_ELF)
2534 return;
2535
2536 if (!arch)
2537 {
2538 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2539 use default_arch. */
2540 arch = cpu_arch_name;
2541 if (!arch)
2542 arch = default_arch;
2543 }
2544
2545 /* If we are targeting Intel MCU, we must enable it. */
2546 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_IAMCU
2547 || new_flag.bitfield.cpuiamcu)
2548 return;
2549
2550 /* If we are targeting Intel L1OM, we must enable it. */
2551 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_L1OM
2552 || new_flag.bitfield.cpul1om)
2553 return;
2554
2555 /* If we are targeting Intel K1OM, we must enable it. */
2556 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_K1OM
2557 || new_flag.bitfield.cpuk1om)
2558 return;
2559
2560 as_bad (_("`%s' is not supported on `%s'"), name, arch);
2561 #endif
2562 }
2563
2564 static void
2565 set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
2566 {
2567 SKIP_WHITESPACE ();
2568
2569 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2570 {
2571 char *string;
2572 int e = get_symbol_name (&string);
2573 unsigned int j;
2574 i386_cpu_flags flags;
2575
2576 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
2577 {
2578 if (strcmp (string, cpu_arch[j].name) == 0)
2579 {
2580 check_cpu_arch_compatible (string, cpu_arch[j].flags);
2581
2582 if (*string != '.')
2583 {
2584 cpu_arch_name = cpu_arch[j].name;
2585 cpu_sub_arch_name = NULL;
2586 cpu_arch_flags = cpu_arch[j].flags;
2587 if (flag_code == CODE_64BIT)
2588 {
2589 cpu_arch_flags.bitfield.cpu64 = 1;
2590 cpu_arch_flags.bitfield.cpuno64 = 0;
2591 }
2592 else
2593 {
2594 cpu_arch_flags.bitfield.cpu64 = 0;
2595 cpu_arch_flags.bitfield.cpuno64 = 1;
2596 }
2597 cpu_arch_isa = cpu_arch[j].type;
2598 cpu_arch_isa_flags = cpu_arch[j].flags;
2599 if (!cpu_arch_tune_set)
2600 {
2601 cpu_arch_tune = cpu_arch_isa;
2602 cpu_arch_tune_flags = cpu_arch_isa_flags;
2603 }
2604 break;
2605 }
2606
2607 flags = cpu_flags_or (cpu_arch_flags,
2608 cpu_arch[j].flags);
2609
2610 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
2611 {
2612 if (cpu_sub_arch_name)
2613 {
2614 char *name = cpu_sub_arch_name;
2615 cpu_sub_arch_name = concat (name,
2616 cpu_arch[j].name,
2617 (const char *) NULL);
2618 free (name);
2619 }
2620 else
2621 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
2622 cpu_arch_flags = flags;
2623 cpu_arch_isa_flags = flags;
2624 }
2625 else
2626 cpu_arch_isa_flags
2627 = cpu_flags_or (cpu_arch_isa_flags,
2628 cpu_arch[j].flags);
2629 (void) restore_line_pointer (e);
2630 demand_empty_rest_of_line ();
2631 return;
2632 }
2633 }
2634
2635 if (*string == '.' && j >= ARRAY_SIZE (cpu_arch))
2636 {
2637 /* Disable an ISA extension. */
2638 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
2639 if (strcmp (string + 1, cpu_noarch [j].name) == 0)
2640 {
2641 flags = cpu_flags_and_not (cpu_arch_flags,
2642 cpu_noarch[j].flags);
2643 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
2644 {
2645 if (cpu_sub_arch_name)
2646 {
2647 char *name = cpu_sub_arch_name;
2648 cpu_sub_arch_name = concat (name, string,
2649 (const char *) NULL);
2650 free (name);
2651 }
2652 else
2653 cpu_sub_arch_name = xstrdup (string);
2654 cpu_arch_flags = flags;
2655 cpu_arch_isa_flags = flags;
2656 }
2657 (void) restore_line_pointer (e);
2658 demand_empty_rest_of_line ();
2659 return;
2660 }
2661
2662 j = ARRAY_SIZE (cpu_arch);
2663 }
2664
2665 if (j >= ARRAY_SIZE (cpu_arch))
2666 as_bad (_("no such architecture: `%s'"), string);
2667
2668 *input_line_pointer = e;
2669 }
2670 else
2671 as_bad (_("missing cpu architecture"));
2672
2673 no_cond_jump_promotion = 0;
2674 if (*input_line_pointer == ','
2675 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
2676 {
2677 char *string;
2678 char e;
2679
2680 ++input_line_pointer;
2681 e = get_symbol_name (&string);
2682
2683 if (strcmp (string, "nojumps") == 0)
2684 no_cond_jump_promotion = 1;
2685 else if (strcmp (string, "jumps") == 0)
2686 ;
2687 else
2688 as_bad (_("no such architecture modifier: `%s'"), string);
2689
2690 (void) restore_line_pointer (e);
2691 }
2692
2693 demand_empty_rest_of_line ();
2694 }
2695
2696 enum bfd_architecture
2697 i386_arch (void)
2698 {
2699 if (cpu_arch_isa == PROCESSOR_L1OM)
2700 {
2701 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2702 || flag_code != CODE_64BIT)
2703 as_fatal (_("Intel L1OM is 64bit ELF only"));
2704 return bfd_arch_l1om;
2705 }
2706 else if (cpu_arch_isa == PROCESSOR_K1OM)
2707 {
2708 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2709 || flag_code != CODE_64BIT)
2710 as_fatal (_("Intel K1OM is 64bit ELF only"));
2711 return bfd_arch_k1om;
2712 }
2713 else if (cpu_arch_isa == PROCESSOR_IAMCU)
2714 {
2715 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2716 || flag_code == CODE_64BIT)
2717 as_fatal (_("Intel MCU is 32bit ELF only"));
2718 return bfd_arch_iamcu;
2719 }
2720 else
2721 return bfd_arch_i386;
2722 }
2723
2724 unsigned long
2725 i386_mach (void)
2726 {
2727 if (!strncmp (default_arch, "x86_64", 6))
2728 {
2729 if (cpu_arch_isa == PROCESSOR_L1OM)
2730 {
2731 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2732 || default_arch[6] != '\0')
2733 as_fatal (_("Intel L1OM is 64bit ELF only"));
2734 return bfd_mach_l1om;
2735 }
2736 else if (cpu_arch_isa == PROCESSOR_K1OM)
2737 {
2738 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2739 || default_arch[6] != '\0')
2740 as_fatal (_("Intel K1OM is 64bit ELF only"));
2741 return bfd_mach_k1om;
2742 }
2743 else if (default_arch[6] == '\0')
2744 return bfd_mach_x86_64;
2745 else
2746 return bfd_mach_x64_32;
2747 }
2748 else if (!strcmp (default_arch, "i386")
2749 || !strcmp (default_arch, "iamcu"))
2750 {
2751 if (cpu_arch_isa == PROCESSOR_IAMCU)
2752 {
2753 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
2754 as_fatal (_("Intel MCU is 32bit ELF only"));
2755 return bfd_mach_i386_iamcu;
2756 }
2757 else
2758 return bfd_mach_i386_i386;
2759 }
2760 else
2761 as_fatal (_("unknown architecture"));
2762 }
2763 \f
2764 void
2765 md_begin (void)
2766 {
2767 const char *hash_err;
2768
2769 /* Support pseudo prefixes like {disp32}. */
2770 lex_type ['{'] = LEX_BEGIN_NAME;
2771
2772 /* Initialize op_hash hash table. */
2773 op_hash = hash_new ();
2774
2775 {
2776 const insn_template *optab;
2777 templates *core_optab;
2778
2779 /* Setup for loop. */
2780 optab = i386_optab;
2781 core_optab = XNEW (templates);
2782 core_optab->start = optab;
2783
2784 while (1)
2785 {
2786 ++optab;
2787 if (optab->name == NULL
2788 || strcmp (optab->name, (optab - 1)->name) != 0)
2789 {
2790 /* different name --> ship out current template list;
2791 add to hash table; & begin anew. */
2792 core_optab->end = optab;
2793 hash_err = hash_insert (op_hash,
2794 (optab - 1)->name,
2795 (void *) core_optab);
2796 if (hash_err)
2797 {
2798 as_fatal (_("can't hash %s: %s"),
2799 (optab - 1)->name,
2800 hash_err);
2801 }
2802 if (optab->name == NULL)
2803 break;
2804 core_optab = XNEW (templates);
2805 core_optab->start = optab;
2806 }
2807 }
2808 }
2809
2810 /* Initialize reg_hash hash table. */
2811 reg_hash = hash_new ();
2812 {
2813 const reg_entry *regtab;
2814 unsigned int regtab_size = i386_regtab_size;
2815
2816 for (regtab = i386_regtab; regtab_size--; regtab++)
2817 {
2818 hash_err = hash_insert (reg_hash, regtab->reg_name, (void *) regtab);
2819 if (hash_err)
2820 as_fatal (_("can't hash %s: %s"),
2821 regtab->reg_name,
2822 hash_err);
2823 }
2824 }
2825
2826 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
2827 {
2828 int c;
2829 char *p;
2830
2831 for (c = 0; c < 256; c++)
2832 {
2833 if (ISDIGIT (c))
2834 {
2835 digit_chars[c] = c;
2836 mnemonic_chars[c] = c;
2837 register_chars[c] = c;
2838 operand_chars[c] = c;
2839 }
2840 else if (ISLOWER (c))
2841 {
2842 mnemonic_chars[c] = c;
2843 register_chars[c] = c;
2844 operand_chars[c] = c;
2845 }
2846 else if (ISUPPER (c))
2847 {
2848 mnemonic_chars[c] = TOLOWER (c);
2849 register_chars[c] = mnemonic_chars[c];
2850 operand_chars[c] = c;
2851 }
2852 else if (c == '{' || c == '}')
2853 {
2854 mnemonic_chars[c] = c;
2855 operand_chars[c] = c;
2856 }
2857
2858 if (ISALPHA (c) || ISDIGIT (c))
2859 identifier_chars[c] = c;
2860 else if (c >= 128)
2861 {
2862 identifier_chars[c] = c;
2863 operand_chars[c] = c;
2864 }
2865 }
2866
2867 #ifdef LEX_AT
2868 identifier_chars['@'] = '@';
2869 #endif
2870 #ifdef LEX_QM
2871 identifier_chars['?'] = '?';
2872 operand_chars['?'] = '?';
2873 #endif
2874 digit_chars['-'] = '-';
2875 mnemonic_chars['_'] = '_';
2876 mnemonic_chars['-'] = '-';
2877 mnemonic_chars['.'] = '.';
2878 identifier_chars['_'] = '_';
2879 identifier_chars['.'] = '.';
2880
2881 for (p = operand_special_chars; *p != '\0'; p++)
2882 operand_chars[(unsigned char) *p] = *p;
2883 }
2884
2885 if (flag_code == CODE_64BIT)
2886 {
2887 #if defined (OBJ_COFF) && defined (TE_PE)
2888 x86_dwarf2_return_column = (OUTPUT_FLAVOR == bfd_target_coff_flavour
2889 ? 32 : 16);
2890 #else
2891 x86_dwarf2_return_column = 16;
2892 #endif
2893 x86_cie_data_alignment = -8;
2894 }
2895 else
2896 {
2897 x86_dwarf2_return_column = 8;
2898 x86_cie_data_alignment = -4;
2899 }
2900 }
2901
2902 void
2903 i386_print_statistics (FILE *file)
2904 {
2905 hash_print_statistics (file, "i386 opcode", op_hash);
2906 hash_print_statistics (file, "i386 register", reg_hash);
2907 }
2908 \f
2909 #ifdef DEBUG386
2910
2911 /* Debugging routines for md_assemble. */
2912 static void pte (insn_template *);
2913 static void pt (i386_operand_type);
2914 static void pe (expressionS *);
2915 static void ps (symbolS *);
2916
2917 static void
2918 pi (char *line, i386_insn *x)
2919 {
2920 unsigned int j;
2921
2922 fprintf (stdout, "%s: template ", line);
2923 pte (&x->tm);
2924 fprintf (stdout, " address: base %s index %s scale %x\n",
2925 x->base_reg ? x->base_reg->reg_name : "none",
2926 x->index_reg ? x->index_reg->reg_name : "none",
2927 x->log2_scale_factor);
2928 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
2929 x->rm.mode, x->rm.reg, x->rm.regmem);
2930 fprintf (stdout, " sib: base %x index %x scale %x\n",
2931 x->sib.base, x->sib.index, x->sib.scale);
2932 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
2933 (x->rex & REX_W) != 0,
2934 (x->rex & REX_R) != 0,
2935 (x->rex & REX_X) != 0,
2936 (x->rex & REX_B) != 0);
2937 for (j = 0; j < x->operands; j++)
2938 {
2939 fprintf (stdout, " #%d: ", j + 1);
2940 pt (x->types[j]);
2941 fprintf (stdout, "\n");
2942 if (x->types[j].bitfield.reg
2943 || x->types[j].bitfield.regmmx
2944 || x->types[j].bitfield.regsimd
2945 || x->types[j].bitfield.sreg2
2946 || x->types[j].bitfield.sreg3
2947 || x->types[j].bitfield.control
2948 || x->types[j].bitfield.debug
2949 || x->types[j].bitfield.test)
2950 fprintf (stdout, "%s\n", x->op[j].regs->reg_name);
2951 if (operand_type_check (x->types[j], imm))
2952 pe (x->op[j].imms);
2953 if (operand_type_check (x->types[j], disp))
2954 pe (x->op[j].disps);
2955 }
2956 }
2957
2958 static void
2959 pte (insn_template *t)
2960 {
2961 unsigned int j;
2962 fprintf (stdout, " %d operands ", t->operands);
2963 fprintf (stdout, "opcode %x ", t->base_opcode);
2964 if (t->extension_opcode != None)
2965 fprintf (stdout, "ext %x ", t->extension_opcode);
2966 if (t->opcode_modifier.d)
2967 fprintf (stdout, "D");
2968 if (t->opcode_modifier.w)
2969 fprintf (stdout, "W");
2970 fprintf (stdout, "\n");
2971 for (j = 0; j < t->operands; j++)
2972 {
2973 fprintf (stdout, " #%d type ", j + 1);
2974 pt (t->operand_types[j]);
2975 fprintf (stdout, "\n");
2976 }
2977 }
2978
2979 static void
2980 pe (expressionS *e)
2981 {
2982 fprintf (stdout, " operation %d\n", e->X_op);
2983 fprintf (stdout, " add_number %ld (%lx)\n",
2984 (long) e->X_add_number, (long) e->X_add_number);
2985 if (e->X_add_symbol)
2986 {
2987 fprintf (stdout, " add_symbol ");
2988 ps (e->X_add_symbol);
2989 fprintf (stdout, "\n");
2990 }
2991 if (e->X_op_symbol)
2992 {
2993 fprintf (stdout, " op_symbol ");
2994 ps (e->X_op_symbol);
2995 fprintf (stdout, "\n");
2996 }
2997 }
2998
2999 static void
3000 ps (symbolS *s)
3001 {
3002 fprintf (stdout, "%s type %s%s",
3003 S_GET_NAME (s),
3004 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
3005 segment_name (S_GET_SEGMENT (s)));
3006 }
3007
3008 static struct type_name
3009 {
3010 i386_operand_type mask;
3011 const char *name;
3012 }
3013 const type_names[] =
3014 {
3015 { OPERAND_TYPE_REG8, "r8" },
3016 { OPERAND_TYPE_REG16, "r16" },
3017 { OPERAND_TYPE_REG32, "r32" },
3018 { OPERAND_TYPE_REG64, "r64" },
3019 { OPERAND_TYPE_IMM8, "i8" },
3020 { OPERAND_TYPE_IMM8, "i8s" },
3021 { OPERAND_TYPE_IMM16, "i16" },
3022 { OPERAND_TYPE_IMM32, "i32" },
3023 { OPERAND_TYPE_IMM32S, "i32s" },
3024 { OPERAND_TYPE_IMM64, "i64" },
3025 { OPERAND_TYPE_IMM1, "i1" },
3026 { OPERAND_TYPE_BASEINDEX, "BaseIndex" },
3027 { OPERAND_TYPE_DISP8, "d8" },
3028 { OPERAND_TYPE_DISP16, "d16" },
3029 { OPERAND_TYPE_DISP32, "d32" },
3030 { OPERAND_TYPE_DISP32S, "d32s" },
3031 { OPERAND_TYPE_DISP64, "d64" },
3032 { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" },
3033 { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" },
3034 { OPERAND_TYPE_CONTROL, "control reg" },
3035 { OPERAND_TYPE_TEST, "test reg" },
3036 { OPERAND_TYPE_DEBUG, "debug reg" },
3037 { OPERAND_TYPE_FLOATREG, "FReg" },
3038 { OPERAND_TYPE_FLOATACC, "FAcc" },
3039 { OPERAND_TYPE_SREG2, "SReg2" },
3040 { OPERAND_TYPE_SREG3, "SReg3" },
3041 { OPERAND_TYPE_ACC, "Acc" },
3042 { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" },
3043 { OPERAND_TYPE_REGMMX, "rMMX" },
3044 { OPERAND_TYPE_REGXMM, "rXMM" },
3045 { OPERAND_TYPE_REGYMM, "rYMM" },
3046 { OPERAND_TYPE_REGZMM, "rZMM" },
3047 { OPERAND_TYPE_REGMASK, "Mask reg" },
3048 { OPERAND_TYPE_ESSEG, "es" },
3049 };
3050
3051 static void
3052 pt (i386_operand_type t)
3053 {
3054 unsigned int j;
3055 i386_operand_type a;
3056
3057 for (j = 0; j < ARRAY_SIZE (type_names); j++)
3058 {
3059 a = operand_type_and (t, type_names[j].mask);
3060 if (!operand_type_all_zero (&a))
3061 fprintf (stdout, "%s, ", type_names[j].name);
3062 }
3063 fflush (stdout);
3064 }
3065
3066 #endif /* DEBUG386 */
3067 \f
3068 static bfd_reloc_code_real_type
3069 reloc (unsigned int size,
3070 int pcrel,
3071 int sign,
3072 bfd_reloc_code_real_type other)
3073 {
3074 if (other != NO_RELOC)
3075 {
3076 reloc_howto_type *rel;
3077
3078 if (size == 8)
3079 switch (other)
3080 {
3081 case BFD_RELOC_X86_64_GOT32:
3082 return BFD_RELOC_X86_64_GOT64;
3083 break;
3084 case BFD_RELOC_X86_64_GOTPLT64:
3085 return BFD_RELOC_X86_64_GOTPLT64;
3086 break;
3087 case BFD_RELOC_X86_64_PLTOFF64:
3088 return BFD_RELOC_X86_64_PLTOFF64;
3089 break;
3090 case BFD_RELOC_X86_64_GOTPC32:
3091 other = BFD_RELOC_X86_64_GOTPC64;
3092 break;
3093 case BFD_RELOC_X86_64_GOTPCREL:
3094 other = BFD_RELOC_X86_64_GOTPCREL64;
3095 break;
3096 case BFD_RELOC_X86_64_TPOFF32:
3097 other = BFD_RELOC_X86_64_TPOFF64;
3098 break;
3099 case BFD_RELOC_X86_64_DTPOFF32:
3100 other = BFD_RELOC_X86_64_DTPOFF64;
3101 break;
3102 default:
3103 break;
3104 }
3105
3106 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3107 if (other == BFD_RELOC_SIZE32)
3108 {
3109 if (size == 8)
3110 other = BFD_RELOC_SIZE64;
3111 if (pcrel)
3112 {
3113 as_bad (_("there are no pc-relative size relocations"));
3114 return NO_RELOC;
3115 }
3116 }
3117 #endif
3118
3119 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
3120 if (size == 4 && (flag_code != CODE_64BIT || disallow_64bit_reloc))
3121 sign = -1;
3122
3123 rel = bfd_reloc_type_lookup (stdoutput, other);
3124 if (!rel)
3125 as_bad (_("unknown relocation (%u)"), other);
3126 else if (size != bfd_get_reloc_size (rel))
3127 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
3128 bfd_get_reloc_size (rel),
3129 size);
3130 else if (pcrel && !rel->pc_relative)
3131 as_bad (_("non-pc-relative relocation for pc-relative field"));
3132 else if ((rel->complain_on_overflow == complain_overflow_signed
3133 && !sign)
3134 || (rel->complain_on_overflow == complain_overflow_unsigned
3135 && sign > 0))
3136 as_bad (_("relocated field and relocation type differ in signedness"));
3137 else
3138 return other;
3139 return NO_RELOC;
3140 }
3141
3142 if (pcrel)
3143 {
3144 if (!sign)
3145 as_bad (_("there are no unsigned pc-relative relocations"));
3146 switch (size)
3147 {
3148 case 1: return BFD_RELOC_8_PCREL;
3149 case 2: return BFD_RELOC_16_PCREL;
3150 case 4: return BFD_RELOC_32_PCREL;
3151 case 8: return BFD_RELOC_64_PCREL;
3152 }
3153 as_bad (_("cannot do %u byte pc-relative relocation"), size);
3154 }
3155 else
3156 {
3157 if (sign > 0)
3158 switch (size)
3159 {
3160 case 4: return BFD_RELOC_X86_64_32S;
3161 }
3162 else
3163 switch (size)
3164 {
3165 case 1: return BFD_RELOC_8;
3166 case 2: return BFD_RELOC_16;
3167 case 4: return BFD_RELOC_32;
3168 case 8: return BFD_RELOC_64;
3169 }
3170 as_bad (_("cannot do %s %u byte relocation"),
3171 sign > 0 ? "signed" : "unsigned", size);
3172 }
3173
3174 return NO_RELOC;
3175 }
3176
3177 /* Here we decide which fixups can be adjusted to make them relative to
3178 the beginning of the section instead of the symbol. Basically we need
3179 to make sure that the dynamic relocations are done correctly, so in
3180 some cases we force the original symbol to be used. */
3181
3182 int
3183 tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED)
3184 {
3185 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3186 if (!IS_ELF)
3187 return 1;
3188
3189 /* Don't adjust pc-relative references to merge sections in 64-bit
3190 mode. */
3191 if (use_rela_relocations
3192 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
3193 && fixP->fx_pcrel)
3194 return 0;
3195
3196 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
3197 and changed later by validate_fix. */
3198 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
3199 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
3200 return 0;
3201
3202 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
3203 for size relocations. */
3204 if (fixP->fx_r_type == BFD_RELOC_SIZE32
3205 || fixP->fx_r_type == BFD_RELOC_SIZE64
3206 || fixP->fx_r_type == BFD_RELOC_386_GOTOFF
3207 || fixP->fx_r_type == BFD_RELOC_386_PLT32
3208 || fixP->fx_r_type == BFD_RELOC_386_GOT32
3209 || fixP->fx_r_type == BFD_RELOC_386_GOT32X
3210 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
3211 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
3212 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
3213 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
3214 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
3215 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
3216 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
3217 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
3218 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
3219 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
3220 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
3221 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
3222 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
3223 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCRELX
3224 || fixP->fx_r_type == BFD_RELOC_X86_64_REX_GOTPCRELX
3225 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
3226 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
3227 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
3228 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
3229 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
3230 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
3231 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
3232 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
3233 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
3234 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
3235 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
3236 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
3237 return 0;
3238 #endif
3239 return 1;
3240 }
3241
3242 static int
3243 intel_float_operand (const char *mnemonic)
3244 {
3245 /* Note that the value returned is meaningful only for opcodes with (memory)
3246 operands, hence the code here is free to improperly handle opcodes that
3247 have no operands (for better performance and smaller code). */
3248
3249 if (mnemonic[0] != 'f')
3250 return 0; /* non-math */
3251
3252 switch (mnemonic[1])
3253 {
3254 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
3255 the fs segment override prefix not currently handled because no
3256 call path can make opcodes without operands get here */
3257 case 'i':
3258 return 2 /* integer op */;
3259 case 'l':
3260 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
3261 return 3; /* fldcw/fldenv */
3262 break;
3263 case 'n':
3264 if (mnemonic[2] != 'o' /* fnop */)
3265 return 3; /* non-waiting control op */
3266 break;
3267 case 'r':
3268 if (mnemonic[2] == 's')
3269 return 3; /* frstor/frstpm */
3270 break;
3271 case 's':
3272 if (mnemonic[2] == 'a')
3273 return 3; /* fsave */
3274 if (mnemonic[2] == 't')
3275 {
3276 switch (mnemonic[3])
3277 {
3278 case 'c': /* fstcw */
3279 case 'd': /* fstdw */
3280 case 'e': /* fstenv */
3281 case 's': /* fsts[gw] */
3282 return 3;
3283 }
3284 }
3285 break;
3286 case 'x':
3287 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
3288 return 0; /* fxsave/fxrstor are not really math ops */
3289 break;
3290 }
3291
3292 return 1;
3293 }
3294
3295 /* Build the VEX prefix. */
3296
3297 static void
3298 build_vex_prefix (const insn_template *t)
3299 {
3300 unsigned int register_specifier;
3301 unsigned int implied_prefix;
3302 unsigned int vector_length;
3303
3304 /* Check register specifier. */
3305 if (i.vex.register_specifier)
3306 {
3307 register_specifier =
3308 ~register_number (i.vex.register_specifier) & 0xf;
3309 gas_assert ((i.vex.register_specifier->reg_flags & RegVRex) == 0);
3310 }
3311 else
3312 register_specifier = 0xf;
3313
3314 /* Use 2-byte VEX prefix by swapping destination and source
3315 operand. */
3316 if (i.vec_encoding != vex_encoding_vex3
3317 && i.dir_encoding == dir_encoding_default
3318 && i.operands == i.reg_operands
3319 && i.tm.opcode_modifier.vexopcode == VEX0F
3320 && i.tm.opcode_modifier.load
3321 && i.rex == REX_B)
3322 {
3323 unsigned int xchg = i.operands - 1;
3324 union i386_op temp_op;
3325 i386_operand_type temp_type;
3326
3327 temp_type = i.types[xchg];
3328 i.types[xchg] = i.types[0];
3329 i.types[0] = temp_type;
3330 temp_op = i.op[xchg];
3331 i.op[xchg] = i.op[0];
3332 i.op[0] = temp_op;
3333
3334 gas_assert (i.rm.mode == 3);
3335
3336 i.rex = REX_R;
3337 xchg = i.rm.regmem;
3338 i.rm.regmem = i.rm.reg;
3339 i.rm.reg = xchg;
3340
3341 /* Use the next insn. */
3342 i.tm = t[1];
3343 }
3344
3345 if (i.tm.opcode_modifier.vex == VEXScalar)
3346 vector_length = avxscalar;
3347 else if (i.tm.opcode_modifier.vex == VEX256)
3348 vector_length = 1;
3349 else
3350 {
3351 unsigned int op;
3352
3353 vector_length = 0;
3354 for (op = 0; op < t->operands; ++op)
3355 if (t->operand_types[op].bitfield.xmmword
3356 && t->operand_types[op].bitfield.ymmword
3357 && i.types[op].bitfield.ymmword)
3358 {
3359 vector_length = 1;
3360 break;
3361 }
3362 }
3363
3364 switch ((i.tm.base_opcode >> 8) & 0xff)
3365 {
3366 case 0:
3367 implied_prefix = 0;
3368 break;
3369 case DATA_PREFIX_OPCODE:
3370 implied_prefix = 1;
3371 break;
3372 case REPE_PREFIX_OPCODE:
3373 implied_prefix = 2;
3374 break;
3375 case REPNE_PREFIX_OPCODE:
3376 implied_prefix = 3;
3377 break;
3378 default:
3379 abort ();
3380 }
3381
3382 /* Use 2-byte VEX prefix if possible. */
3383 if (i.vec_encoding != vex_encoding_vex3
3384 && i.tm.opcode_modifier.vexopcode == VEX0F
3385 && i.tm.opcode_modifier.vexw != VEXW1
3386 && (i.rex & (REX_W | REX_X | REX_B)) == 0)
3387 {
3388 /* 2-byte VEX prefix. */
3389 unsigned int r;
3390
3391 i.vex.length = 2;
3392 i.vex.bytes[0] = 0xc5;
3393
3394 /* Check the REX.R bit. */
3395 r = (i.rex & REX_R) ? 0 : 1;
3396 i.vex.bytes[1] = (r << 7
3397 | register_specifier << 3
3398 | vector_length << 2
3399 | implied_prefix);
3400 }
3401 else
3402 {
3403 /* 3-byte VEX prefix. */
3404 unsigned int m, w;
3405
3406 i.vex.length = 3;
3407
3408 switch (i.tm.opcode_modifier.vexopcode)
3409 {
3410 case VEX0F:
3411 m = 0x1;
3412 i.vex.bytes[0] = 0xc4;
3413 break;
3414 case VEX0F38:
3415 m = 0x2;
3416 i.vex.bytes[0] = 0xc4;
3417 break;
3418 case VEX0F3A:
3419 m = 0x3;
3420 i.vex.bytes[0] = 0xc4;
3421 break;
3422 case XOP08:
3423 m = 0x8;
3424 i.vex.bytes[0] = 0x8f;
3425 break;
3426 case XOP09:
3427 m = 0x9;
3428 i.vex.bytes[0] = 0x8f;
3429 break;
3430 case XOP0A:
3431 m = 0xa;
3432 i.vex.bytes[0] = 0x8f;
3433 break;
3434 default:
3435 abort ();
3436 }
3437
3438 /* The high 3 bits of the second VEX byte are 1's compliment
3439 of RXB bits from REX. */
3440 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
3441
3442 /* Check the REX.W bit. */
3443 w = (i.rex & REX_W) ? 1 : 0;
3444 if (i.tm.opcode_modifier.vexw == VEXW1)
3445 w = 1;
3446
3447 i.vex.bytes[2] = (w << 7
3448 | register_specifier << 3
3449 | vector_length << 2
3450 | implied_prefix);
3451 }
3452 }
3453
3454 static INLINE bfd_boolean
3455 is_evex_encoding (const insn_template *t)
3456 {
3457 return t->opcode_modifier.evex
3458 || t->opcode_modifier.broadcast || t->opcode_modifier.masking
3459 || t->opcode_modifier.staticrounding || t->opcode_modifier.sae;
3460 }
3461
3462 /* Build the EVEX prefix. */
3463
3464 static void
3465 build_evex_prefix (void)
3466 {
3467 unsigned int register_specifier;
3468 unsigned int implied_prefix;
3469 unsigned int m, w;
3470 rex_byte vrex_used = 0;
3471
3472 /* Check register specifier. */
3473 if (i.vex.register_specifier)
3474 {
3475 gas_assert ((i.vrex & REX_X) == 0);
3476
3477 register_specifier = i.vex.register_specifier->reg_num;
3478 if ((i.vex.register_specifier->reg_flags & RegRex))
3479 register_specifier += 8;
3480 /* The upper 16 registers are encoded in the fourth byte of the
3481 EVEX prefix. */
3482 if (!(i.vex.register_specifier->reg_flags & RegVRex))
3483 i.vex.bytes[3] = 0x8;
3484 register_specifier = ~register_specifier & 0xf;
3485 }
3486 else
3487 {
3488 register_specifier = 0xf;
3489
3490 /* Encode upper 16 vector index register in the fourth byte of
3491 the EVEX prefix. */
3492 if (!(i.vrex & REX_X))
3493 i.vex.bytes[3] = 0x8;
3494 else
3495 vrex_used |= REX_X;
3496 }
3497
3498 switch ((i.tm.base_opcode >> 8) & 0xff)
3499 {
3500 case 0:
3501 implied_prefix = 0;
3502 break;
3503 case DATA_PREFIX_OPCODE:
3504 implied_prefix = 1;
3505 break;
3506 case REPE_PREFIX_OPCODE:
3507 implied_prefix = 2;
3508 break;
3509 case REPNE_PREFIX_OPCODE:
3510 implied_prefix = 3;
3511 break;
3512 default:
3513 abort ();
3514 }
3515
3516 /* 4 byte EVEX prefix. */
3517 i.vex.length = 4;
3518 i.vex.bytes[0] = 0x62;
3519
3520 /* mmmm bits. */
3521 switch (i.tm.opcode_modifier.vexopcode)
3522 {
3523 case VEX0F:
3524 m = 1;
3525 break;
3526 case VEX0F38:
3527 m = 2;
3528 break;
3529 case VEX0F3A:
3530 m = 3;
3531 break;
3532 default:
3533 abort ();
3534 break;
3535 }
3536
3537 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3538 bits from REX. */
3539 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
3540
3541 /* The fifth bit of the second EVEX byte is 1's compliment of the
3542 REX_R bit in VREX. */
3543 if (!(i.vrex & REX_R))
3544 i.vex.bytes[1] |= 0x10;
3545 else
3546 vrex_used |= REX_R;
3547
3548 if ((i.reg_operands + i.imm_operands) == i.operands)
3549 {
3550 /* When all operands are registers, the REX_X bit in REX is not
3551 used. We reuse it to encode the upper 16 registers, which is
3552 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3553 as 1's compliment. */
3554 if ((i.vrex & REX_B))
3555 {
3556 vrex_used |= REX_B;
3557 i.vex.bytes[1] &= ~0x40;
3558 }
3559 }
3560
3561 /* EVEX instructions shouldn't need the REX prefix. */
3562 i.vrex &= ~vrex_used;
3563 gas_assert (i.vrex == 0);
3564
3565 /* Check the REX.W bit. */
3566 w = (i.rex & REX_W) ? 1 : 0;
3567 if (i.tm.opcode_modifier.vexw)
3568 {
3569 if (i.tm.opcode_modifier.vexw == VEXW1)
3570 w = 1;
3571 }
3572 /* If w is not set it means we are dealing with WIG instruction. */
3573 else if (!w)
3574 {
3575 if (evexwig == evexw1)
3576 w = 1;
3577 }
3578
3579 /* Encode the U bit. */
3580 implied_prefix |= 0x4;
3581
3582 /* The third byte of the EVEX prefix. */
3583 i.vex.bytes[2] = (w << 7 | register_specifier << 3 | implied_prefix);
3584
3585 /* The fourth byte of the EVEX prefix. */
3586 /* The zeroing-masking bit. */
3587 if (i.mask && i.mask->zeroing)
3588 i.vex.bytes[3] |= 0x80;
3589
3590 /* Don't always set the broadcast bit if there is no RC. */
3591 if (!i.rounding)
3592 {
3593 /* Encode the vector length. */
3594 unsigned int vec_length;
3595
3596 if (!i.tm.opcode_modifier.evex
3597 || i.tm.opcode_modifier.evex == EVEXDYN)
3598 {
3599 unsigned int op;
3600
3601 vec_length = 0;
3602 for (op = 0; op < i.tm.operands; ++op)
3603 if (i.tm.operand_types[op].bitfield.xmmword
3604 + i.tm.operand_types[op].bitfield.ymmword
3605 + i.tm.operand_types[op].bitfield.zmmword > 1)
3606 {
3607 if (i.types[op].bitfield.zmmword)
3608 i.tm.opcode_modifier.evex = EVEX512;
3609 else if (i.types[op].bitfield.ymmword)
3610 i.tm.opcode_modifier.evex = EVEX256;
3611 else if (i.types[op].bitfield.xmmword)
3612 i.tm.opcode_modifier.evex = EVEX128;
3613 else
3614 continue;
3615 break;
3616 }
3617 }
3618
3619 switch (i.tm.opcode_modifier.evex)
3620 {
3621 case EVEXLIG: /* LL' is ignored */
3622 vec_length = evexlig << 5;
3623 break;
3624 case EVEX128:
3625 vec_length = 0 << 5;
3626 break;
3627 case EVEX256:
3628 vec_length = 1 << 5;
3629 break;
3630 case EVEX512:
3631 vec_length = 2 << 5;
3632 break;
3633 default:
3634 abort ();
3635 break;
3636 }
3637 i.vex.bytes[3] |= vec_length;
3638 /* Encode the broadcast bit. */
3639 if (i.broadcast)
3640 i.vex.bytes[3] |= 0x10;
3641 }
3642 else
3643 {
3644 if (i.rounding->type != saeonly)
3645 i.vex.bytes[3] |= 0x10 | (i.rounding->type << 5);
3646 else
3647 i.vex.bytes[3] |= 0x10 | (evexrcig << 5);
3648 }
3649
3650 if (i.mask && i.mask->mask)
3651 i.vex.bytes[3] |= i.mask->mask->reg_num;
3652 }
3653
3654 static void
3655 process_immext (void)
3656 {
3657 expressionS *exp;
3658
3659 if ((i.tm.cpu_flags.bitfield.cpusse3 || i.tm.cpu_flags.bitfield.cpusvme)
3660 && i.operands > 0)
3661 {
3662 /* MONITOR/MWAIT as well as SVME instructions have fixed operands
3663 with an opcode suffix which is coded in the same place as an
3664 8-bit immediate field would be.
3665 Here we check those operands and remove them afterwards. */
3666 unsigned int x;
3667
3668 for (x = 0; x < i.operands; x++)
3669 if (register_number (i.op[x].regs) != x)
3670 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3671 register_prefix, i.op[x].regs->reg_name, x + 1,
3672 i.tm.name);
3673
3674 i.operands = 0;
3675 }
3676
3677 if (i.tm.cpu_flags.bitfield.cpumwaitx && i.operands > 0)
3678 {
3679 /* MONITORX/MWAITX instructions have fixed operands with an opcode
3680 suffix which is coded in the same place as an 8-bit immediate
3681 field would be.
3682 Here we check those operands and remove them afterwards. */
3683 unsigned int x;
3684
3685 if (i.operands != 3)
3686 abort();
3687
3688 for (x = 0; x < 2; x++)
3689 if (register_number (i.op[x].regs) != x)
3690 goto bad_register_operand;
3691
3692 /* Check for third operand for mwaitx/monitorx insn. */
3693 if (register_number (i.op[x].regs)
3694 != (x + (i.tm.extension_opcode == 0xfb)))
3695 {
3696 bad_register_operand:
3697 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3698 register_prefix, i.op[x].regs->reg_name, x+1,
3699 i.tm.name);
3700 }
3701
3702 i.operands = 0;
3703 }
3704
3705 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
3706 which is coded in the same place as an 8-bit immediate field
3707 would be. Here we fake an 8-bit immediate operand from the
3708 opcode suffix stored in tm.extension_opcode.
3709
3710 AVX instructions also use this encoding, for some of
3711 3 argument instructions. */
3712
3713 gas_assert (i.imm_operands <= 1
3714 && (i.operands <= 2
3715 || ((i.tm.opcode_modifier.vex
3716 || i.tm.opcode_modifier.vexopcode
3717 || is_evex_encoding (&i.tm))
3718 && i.operands <= 4)));
3719
3720 exp = &im_expressions[i.imm_operands++];
3721 i.op[i.operands].imms = exp;
3722 i.types[i.operands] = imm8;
3723 i.operands++;
3724 exp->X_op = O_constant;
3725 exp->X_add_number = i.tm.extension_opcode;
3726 i.tm.extension_opcode = None;
3727 }
3728
3729
3730 static int
3731 check_hle (void)
3732 {
3733 switch (i.tm.opcode_modifier.hleprefixok)
3734 {
3735 default:
3736 abort ();
3737 case HLEPrefixNone:
3738 as_bad (_("invalid instruction `%s' after `%s'"),
3739 i.tm.name, i.hle_prefix);
3740 return 0;
3741 case HLEPrefixLock:
3742 if (i.prefix[LOCK_PREFIX])
3743 return 1;
3744 as_bad (_("missing `lock' with `%s'"), i.hle_prefix);
3745 return 0;
3746 case HLEPrefixAny:
3747 return 1;
3748 case HLEPrefixRelease:
3749 if (i.prefix[HLE_PREFIX] != XRELEASE_PREFIX_OPCODE)
3750 {
3751 as_bad (_("instruction `%s' after `xacquire' not allowed"),
3752 i.tm.name);
3753 return 0;
3754 }
3755 if (i.mem_operands == 0
3756 || !operand_type_check (i.types[i.operands - 1], anymem))
3757 {
3758 as_bad (_("memory destination needed for instruction `%s'"
3759 " after `xrelease'"), i.tm.name);
3760 return 0;
3761 }
3762 return 1;
3763 }
3764 }
3765
3766 /* Try the shortest encoding by shortening operand size. */
3767
3768 static void
3769 optimize_encoding (void)
3770 {
3771 int j;
3772
3773 if (optimize_for_space
3774 && i.reg_operands == 1
3775 && i.imm_operands == 1
3776 && !i.types[1].bitfield.byte
3777 && i.op[0].imms->X_op == O_constant
3778 && fits_in_imm7 (i.op[0].imms->X_add_number)
3779 && ((i.tm.base_opcode == 0xa8
3780 && i.tm.extension_opcode == None)
3781 || (i.tm.base_opcode == 0xf6
3782 && i.tm.extension_opcode == 0x0)))
3783 {
3784 /* Optimize: -Os:
3785 test $imm7, %r64/%r32/%r16 -> test $imm7, %r8
3786 */
3787 unsigned int base_regnum = i.op[1].regs->reg_num;
3788 if (flag_code == CODE_64BIT || base_regnum < 4)
3789 {
3790 i.types[1].bitfield.byte = 1;
3791 /* Ignore the suffix. */
3792 i.suffix = 0;
3793 if (base_regnum >= 4
3794 && !(i.op[1].regs->reg_flags & RegRex))
3795 {
3796 /* Handle SP, BP, SI and DI registers. */
3797 if (i.types[1].bitfield.word)
3798 j = 16;
3799 else if (i.types[1].bitfield.dword)
3800 j = 32;
3801 else
3802 j = 48;
3803 i.op[1].regs -= j;
3804 }
3805 }
3806 }
3807 else if (flag_code == CODE_64BIT
3808 && ((i.types[1].bitfield.qword
3809 && i.reg_operands == 1
3810 && i.imm_operands == 1
3811 && i.op[0].imms->X_op == O_constant
3812 && ((i.tm.base_opcode == 0xb0
3813 && i.tm.extension_opcode == None
3814 && fits_in_unsigned_long (i.op[0].imms->X_add_number))
3815 || (fits_in_imm31 (i.op[0].imms->X_add_number)
3816 && (((i.tm.base_opcode == 0x24
3817 || i.tm.base_opcode == 0xa8)
3818 && i.tm.extension_opcode == None)
3819 || (i.tm.base_opcode == 0x80
3820 && i.tm.extension_opcode == 0x4)
3821 || ((i.tm.base_opcode == 0xf6
3822 || i.tm.base_opcode == 0xc6)
3823 && i.tm.extension_opcode == 0x0)))))
3824 || (i.types[0].bitfield.qword
3825 && ((i.reg_operands == 2
3826 && i.op[0].regs == i.op[1].regs
3827 && ((i.tm.base_opcode == 0x30
3828 || i.tm.base_opcode == 0x28)
3829 && i.tm.extension_opcode == None))
3830 || (i.reg_operands == 1
3831 && i.operands == 1
3832 && i.tm.base_opcode == 0x30
3833 && i.tm.extension_opcode == None)))))
3834 {
3835 /* Optimize: -O:
3836 andq $imm31, %r64 -> andl $imm31, %r32
3837 testq $imm31, %r64 -> testl $imm31, %r32
3838 xorq %r64, %r64 -> xorl %r32, %r32
3839 subq %r64, %r64 -> subl %r32, %r32
3840 movq $imm31, %r64 -> movl $imm31, %r32
3841 movq $imm32, %r64 -> movl $imm32, %r32
3842 */
3843 i.tm.opcode_modifier.norex64 = 1;
3844 if (i.tm.base_opcode == 0xb0 || i.tm.base_opcode == 0xc6)
3845 {
3846 /* Handle
3847 movq $imm31, %r64 -> movl $imm31, %r32
3848 movq $imm32, %r64 -> movl $imm32, %r32
3849 */
3850 i.tm.operand_types[0].bitfield.imm32 = 1;
3851 i.tm.operand_types[0].bitfield.imm32s = 0;
3852 i.tm.operand_types[0].bitfield.imm64 = 0;
3853 i.types[0].bitfield.imm32 = 1;
3854 i.types[0].bitfield.imm32s = 0;
3855 i.types[0].bitfield.imm64 = 0;
3856 i.types[1].bitfield.dword = 1;
3857 i.types[1].bitfield.qword = 0;
3858 if (i.tm.base_opcode == 0xc6)
3859 {
3860 /* Handle
3861 movq $imm31, %r64 -> movl $imm31, %r32
3862 */
3863 i.tm.base_opcode = 0xb0;
3864 i.tm.extension_opcode = None;
3865 i.tm.opcode_modifier.shortform = 1;
3866 i.tm.opcode_modifier.modrm = 0;
3867 }
3868 }
3869 }
3870 else if (optimize > 1
3871 && i.reg_operands == 3
3872 && i.op[0].regs == i.op[1].regs
3873 && !i.types[2].bitfield.xmmword
3874 && (i.tm.opcode_modifier.vex
3875 || (!i.mask
3876 && !i.rounding
3877 && is_evex_encoding (&i.tm)
3878 && (i.vec_encoding != vex_encoding_evex
3879 || i.tm.cpu_flags.bitfield.cpuavx512vl
3880 || cpu_arch_isa_flags.bitfield.cpuavx512vl)))
3881 && ((i.tm.base_opcode == 0x55
3882 || i.tm.base_opcode == 0x6655
3883 || i.tm.base_opcode == 0x66df
3884 || i.tm.base_opcode == 0x57
3885 || i.tm.base_opcode == 0x6657
3886 || i.tm.base_opcode == 0x66ef
3887 || i.tm.base_opcode == 0x66f8
3888 || i.tm.base_opcode == 0x66f9
3889 || i.tm.base_opcode == 0x66fa
3890 || i.tm.base_opcode == 0x66fb)
3891 && i.tm.extension_opcode == None))
3892 {
3893 /* Optimize: -O2:
3894 VOP, one of vandnps, vandnpd, vxorps, vxorpd, vpsubb, vpsubd,
3895 vpsubq and vpsubw:
3896 EVEX VOP %zmmM, %zmmM, %zmmN
3897 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
3898 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3899 EVEX VOP %ymmM, %ymmM, %ymmN
3900 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
3901 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3902 VEX VOP %ymmM, %ymmM, %ymmN
3903 -> VEX VOP %xmmM, %xmmM, %xmmN
3904 VOP, one of vpandn and vpxor:
3905 VEX VOP %ymmM, %ymmM, %ymmN
3906 -> VEX VOP %xmmM, %xmmM, %xmmN
3907 VOP, one of vpandnd and vpandnq:
3908 EVEX VOP %zmmM, %zmmM, %zmmN
3909 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
3910 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3911 EVEX VOP %ymmM, %ymmM, %ymmN
3912 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
3913 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3914 VOP, one of vpxord and vpxorq:
3915 EVEX VOP %zmmM, %zmmM, %zmmN
3916 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
3917 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3918 EVEX VOP %ymmM, %ymmM, %ymmN
3919 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
3920 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3921 */
3922 if (is_evex_encoding (&i.tm))
3923 {
3924 if (i.vec_encoding == vex_encoding_evex)
3925 i.tm.opcode_modifier.evex = EVEX128;
3926 else
3927 {
3928 i.tm.opcode_modifier.vex = VEX128;
3929 i.tm.opcode_modifier.vexw = VEXW0;
3930 i.tm.opcode_modifier.evex = 0;
3931 }
3932 }
3933 else
3934 i.tm.opcode_modifier.vex = VEX128;
3935
3936 if (i.tm.opcode_modifier.vex)
3937 for (j = 0; j < 3; j++)
3938 {
3939 i.types[j].bitfield.xmmword = 1;
3940 i.types[j].bitfield.ymmword = 0;
3941 }
3942 }
3943 }
3944
3945 /* This is the guts of the machine-dependent assembler. LINE points to a
3946 machine dependent instruction. This function is supposed to emit
3947 the frags/bytes it assembles to. */
3948
3949 void
3950 md_assemble (char *line)
3951 {
3952 unsigned int j;
3953 char mnemonic[MAX_MNEM_SIZE], mnem_suffix;
3954 const insn_template *t;
3955
3956 /* Initialize globals. */
3957 memset (&i, '\0', sizeof (i));
3958 for (j = 0; j < MAX_OPERANDS; j++)
3959 i.reloc[j] = NO_RELOC;
3960 memset (disp_expressions, '\0', sizeof (disp_expressions));
3961 memset (im_expressions, '\0', sizeof (im_expressions));
3962 save_stack_p = save_stack;
3963
3964 /* First parse an instruction mnemonic & call i386_operand for the operands.
3965 We assume that the scrubber has arranged it so that line[0] is the valid
3966 start of a (possibly prefixed) mnemonic. */
3967
3968 line = parse_insn (line, mnemonic);
3969 if (line == NULL)
3970 return;
3971 mnem_suffix = i.suffix;
3972
3973 line = parse_operands (line, mnemonic);
3974 this_operand = -1;
3975 xfree (i.memop1_string);
3976 i.memop1_string = NULL;
3977 if (line == NULL)
3978 return;
3979
3980 /* Now we've parsed the mnemonic into a set of templates, and have the
3981 operands at hand. */
3982
3983 /* All intel opcodes have reversed operands except for "bound" and
3984 "enter". We also don't reverse intersegment "jmp" and "call"
3985 instructions with 2 immediate operands so that the immediate segment
3986 precedes the offset, as it does when in AT&T mode. */
3987 if (intel_syntax
3988 && i.operands > 1
3989 && (strcmp (mnemonic, "bound") != 0)
3990 && (strcmp (mnemonic, "invlpga") != 0)
3991 && !(operand_type_check (i.types[0], imm)
3992 && operand_type_check (i.types[1], imm)))
3993 swap_operands ();
3994
3995 /* The order of the immediates should be reversed
3996 for 2 immediates extrq and insertq instructions */
3997 if (i.imm_operands == 2
3998 && (strcmp (mnemonic, "extrq") == 0
3999 || strcmp (mnemonic, "insertq") == 0))
4000 swap_2_operands (0, 1);
4001
4002 if (i.imm_operands)
4003 optimize_imm ();
4004
4005 /* Don't optimize displacement for movabs since it only takes 64bit
4006 displacement. */
4007 if (i.disp_operands
4008 && i.disp_encoding != disp_encoding_32bit
4009 && (flag_code != CODE_64BIT
4010 || strcmp (mnemonic, "movabs") != 0))
4011 optimize_disp ();
4012
4013 /* Next, we find a template that matches the given insn,
4014 making sure the overlap of the given operands types is consistent
4015 with the template operand types. */
4016
4017 if (!(t = match_template (mnem_suffix)))
4018 return;
4019
4020 if (sse_check != check_none
4021 && !i.tm.opcode_modifier.noavx
4022 && !i.tm.cpu_flags.bitfield.cpuavx
4023 && (i.tm.cpu_flags.bitfield.cpusse
4024 || i.tm.cpu_flags.bitfield.cpusse2
4025 || i.tm.cpu_flags.bitfield.cpusse3
4026 || i.tm.cpu_flags.bitfield.cpussse3
4027 || i.tm.cpu_flags.bitfield.cpusse4_1
4028 || i.tm.cpu_flags.bitfield.cpusse4_2
4029 || i.tm.cpu_flags.bitfield.cpupclmul
4030 || i.tm.cpu_flags.bitfield.cpuaes
4031 || i.tm.cpu_flags.bitfield.cpugfni))
4032 {
4033 (sse_check == check_warning
4034 ? as_warn
4035 : as_bad) (_("SSE instruction `%s' is used"), i.tm.name);
4036 }
4037
4038 /* Zap movzx and movsx suffix. The suffix has been set from
4039 "word ptr" or "byte ptr" on the source operand in Intel syntax
4040 or extracted from mnemonic in AT&T syntax. But we'll use
4041 the destination register to choose the suffix for encoding. */
4042 if ((i.tm.base_opcode & ~9) == 0x0fb6)
4043 {
4044 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
4045 there is no suffix, the default will be byte extension. */
4046 if (i.reg_operands != 2
4047 && !i.suffix
4048 && intel_syntax)
4049 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
4050
4051 i.suffix = 0;
4052 }
4053
4054 if (i.tm.opcode_modifier.fwait)
4055 if (!add_prefix (FWAIT_OPCODE))
4056 return;
4057
4058 /* Check if REP prefix is OK. */
4059 if (i.rep_prefix && !i.tm.opcode_modifier.repprefixok)
4060 {
4061 as_bad (_("invalid instruction `%s' after `%s'"),
4062 i.tm.name, i.rep_prefix);
4063 return;
4064 }
4065
4066 /* Check for lock without a lockable instruction. Destination operand
4067 must be memory unless it is xchg (0x86). */
4068 if (i.prefix[LOCK_PREFIX]
4069 && (!i.tm.opcode_modifier.islockable
4070 || i.mem_operands == 0
4071 || (i.tm.base_opcode != 0x86
4072 && !operand_type_check (i.types[i.operands - 1], anymem))))
4073 {
4074 as_bad (_("expecting lockable instruction after `lock'"));
4075 return;
4076 }
4077
4078 /* Check if HLE prefix is OK. */
4079 if (i.hle_prefix && !check_hle ())
4080 return;
4081
4082 /* Check BND prefix. */
4083 if (i.bnd_prefix && !i.tm.opcode_modifier.bndprefixok)
4084 as_bad (_("expecting valid branch instruction after `bnd'"));
4085
4086 /* Check NOTRACK prefix. */
4087 if (i.notrack_prefix && !i.tm.opcode_modifier.notrackprefixok)
4088 as_bad (_("expecting indirect branch instruction after `notrack'"));
4089
4090 if (i.tm.cpu_flags.bitfield.cpumpx)
4091 {
4092 if (flag_code == CODE_64BIT && i.prefix[ADDR_PREFIX])
4093 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
4094 else if (flag_code != CODE_16BIT
4095 ? i.prefix[ADDR_PREFIX]
4096 : i.mem_operands && !i.prefix[ADDR_PREFIX])
4097 as_bad (_("16-bit address isn't allowed in MPX instructions"));
4098 }
4099
4100 /* Insert BND prefix. */
4101 if (add_bnd_prefix
4102 && i.tm.opcode_modifier.bndprefixok
4103 && !i.prefix[BND_PREFIX])
4104 add_prefix (BND_PREFIX_OPCODE);
4105
4106 /* Check string instruction segment overrides. */
4107 if (i.tm.opcode_modifier.isstring && i.mem_operands != 0)
4108 {
4109 if (!check_string ())
4110 return;
4111 i.disp_operands = 0;
4112 }
4113
4114 if (optimize && !i.no_optimize && i.tm.opcode_modifier.optimize)
4115 optimize_encoding ();
4116
4117 if (!process_suffix ())
4118 return;
4119
4120 /* Update operand types. */
4121 for (j = 0; j < i.operands; j++)
4122 i.types[j] = operand_type_and (i.types[j], i.tm.operand_types[j]);
4123
4124 /* Make still unresolved immediate matches conform to size of immediate
4125 given in i.suffix. */
4126 if (!finalize_imm ())
4127 return;
4128
4129 if (i.types[0].bitfield.imm1)
4130 i.imm_operands = 0; /* kludge for shift insns. */
4131
4132 /* We only need to check those implicit registers for instructions
4133 with 3 operands or less. */
4134 if (i.operands <= 3)
4135 for (j = 0; j < i.operands; j++)
4136 if (i.types[j].bitfield.inoutportreg
4137 || i.types[j].bitfield.shiftcount
4138 || (i.types[j].bitfield.acc && !i.types[j].bitfield.xmmword))
4139 i.reg_operands--;
4140
4141 /* ImmExt should be processed after SSE2AVX. */
4142 if (!i.tm.opcode_modifier.sse2avx
4143 && i.tm.opcode_modifier.immext)
4144 process_immext ();
4145
4146 /* For insns with operands there are more diddles to do to the opcode. */
4147 if (i.operands)
4148 {
4149 if (!process_operands ())
4150 return;
4151 }
4152 else if (!quiet_warnings && i.tm.opcode_modifier.ugh)
4153 {
4154 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
4155 as_warn (_("translating to `%sp'"), i.tm.name);
4156 }
4157
4158 if (i.tm.opcode_modifier.vex || i.tm.opcode_modifier.vexopcode
4159 || is_evex_encoding (&i.tm))
4160 {
4161 if (flag_code == CODE_16BIT)
4162 {
4163 as_bad (_("instruction `%s' isn't supported in 16-bit mode."),
4164 i.tm.name);
4165 return;
4166 }
4167
4168 if (i.tm.opcode_modifier.vex)
4169 build_vex_prefix (t);
4170 else
4171 build_evex_prefix ();
4172 }
4173
4174 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
4175 instructions may define INT_OPCODE as well, so avoid this corner
4176 case for those instructions that use MODRM. */
4177 if (i.tm.base_opcode == INT_OPCODE
4178 && !i.tm.opcode_modifier.modrm
4179 && i.op[0].imms->X_add_number == 3)
4180 {
4181 i.tm.base_opcode = INT3_OPCODE;
4182 i.imm_operands = 0;
4183 }
4184
4185 if ((i.tm.opcode_modifier.jump
4186 || i.tm.opcode_modifier.jumpbyte
4187 || i.tm.opcode_modifier.jumpdword)
4188 && i.op[0].disps->X_op == O_constant)
4189 {
4190 /* Convert "jmp constant" (and "call constant") to a jump (call) to
4191 the absolute address given by the constant. Since ix86 jumps and
4192 calls are pc relative, we need to generate a reloc. */
4193 i.op[0].disps->X_add_symbol = &abs_symbol;
4194 i.op[0].disps->X_op = O_symbol;
4195 }
4196
4197 if (i.tm.opcode_modifier.rex64)
4198 i.rex |= REX_W;
4199
4200 /* For 8 bit registers we need an empty rex prefix. Also if the
4201 instruction already has a prefix, we need to convert old
4202 registers to new ones. */
4203
4204 if ((i.types[0].bitfield.reg && i.types[0].bitfield.byte
4205 && (i.op[0].regs->reg_flags & RegRex64) != 0)
4206 || (i.types[1].bitfield.reg && i.types[1].bitfield.byte
4207 && (i.op[1].regs->reg_flags & RegRex64) != 0)
4208 || (((i.types[0].bitfield.reg && i.types[0].bitfield.byte)
4209 || (i.types[1].bitfield.reg && i.types[1].bitfield.byte))
4210 && i.rex != 0))
4211 {
4212 int x;
4213
4214 i.rex |= REX_OPCODE;
4215 for (x = 0; x < 2; x++)
4216 {
4217 /* Look for 8 bit operand that uses old registers. */
4218 if (i.types[x].bitfield.reg && i.types[x].bitfield.byte
4219 && (i.op[x].regs->reg_flags & RegRex64) == 0)
4220 {
4221 /* In case it is "hi" register, give up. */
4222 if (i.op[x].regs->reg_num > 3)
4223 as_bad (_("can't encode register '%s%s' in an "
4224 "instruction requiring REX prefix."),
4225 register_prefix, i.op[x].regs->reg_name);
4226
4227 /* Otherwise it is equivalent to the extended register.
4228 Since the encoding doesn't change this is merely
4229 cosmetic cleanup for debug output. */
4230
4231 i.op[x].regs = i.op[x].regs + 8;
4232 }
4233 }
4234 }
4235
4236 if (i.rex == 0 && i.rex_encoding)
4237 {
4238 /* Check if we can add a REX_OPCODE byte. Look for 8 bit operand
4239 that uses legacy register. If it is "hi" register, don't add
4240 the REX_OPCODE byte. */
4241 int x;
4242 for (x = 0; x < 2; x++)
4243 if (i.types[x].bitfield.reg
4244 && i.types[x].bitfield.byte
4245 && (i.op[x].regs->reg_flags & RegRex64) == 0
4246 && i.op[x].regs->reg_num > 3)
4247 {
4248 i.rex_encoding = FALSE;
4249 break;
4250 }
4251
4252 if (i.rex_encoding)
4253 i.rex = REX_OPCODE;
4254 }
4255
4256 if (i.rex != 0)
4257 add_prefix (REX_OPCODE | i.rex);
4258
4259 /* We are ready to output the insn. */
4260 output_insn ();
4261 }
4262
4263 static char *
4264 parse_insn (char *line, char *mnemonic)
4265 {
4266 char *l = line;
4267 char *token_start = l;
4268 char *mnem_p;
4269 int supported;
4270 const insn_template *t;
4271 char *dot_p = NULL;
4272
4273 while (1)
4274 {
4275 mnem_p = mnemonic;
4276 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
4277 {
4278 if (*mnem_p == '.')
4279 dot_p = mnem_p;
4280 mnem_p++;
4281 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
4282 {
4283 as_bad (_("no such instruction: `%s'"), token_start);
4284 return NULL;
4285 }
4286 l++;
4287 }
4288 if (!is_space_char (*l)
4289 && *l != END_OF_INSN
4290 && (intel_syntax
4291 || (*l != PREFIX_SEPARATOR
4292 && *l != ',')))
4293 {
4294 as_bad (_("invalid character %s in mnemonic"),
4295 output_invalid (*l));
4296 return NULL;
4297 }
4298 if (token_start == l)
4299 {
4300 if (!intel_syntax && *l == PREFIX_SEPARATOR)
4301 as_bad (_("expecting prefix; got nothing"));
4302 else
4303 as_bad (_("expecting mnemonic; got nothing"));
4304 return NULL;
4305 }
4306
4307 /* Look up instruction (or prefix) via hash table. */
4308 current_templates = (const templates *) hash_find (op_hash, mnemonic);
4309
4310 if (*l != END_OF_INSN
4311 && (!is_space_char (*l) || l[1] != END_OF_INSN)
4312 && current_templates
4313 && current_templates->start->opcode_modifier.isprefix)
4314 {
4315 if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags))
4316 {
4317 as_bad ((flag_code != CODE_64BIT
4318 ? _("`%s' is only supported in 64-bit mode")
4319 : _("`%s' is not supported in 64-bit mode")),
4320 current_templates->start->name);
4321 return NULL;
4322 }
4323 /* If we are in 16-bit mode, do not allow addr16 or data16.
4324 Similarly, in 32-bit mode, do not allow addr32 or data32. */
4325 if ((current_templates->start->opcode_modifier.size16
4326 || current_templates->start->opcode_modifier.size32)
4327 && flag_code != CODE_64BIT
4328 && (current_templates->start->opcode_modifier.size32
4329 ^ (flag_code == CODE_16BIT)))
4330 {
4331 as_bad (_("redundant %s prefix"),
4332 current_templates->start->name);
4333 return NULL;
4334 }
4335 if (current_templates->start->opcode_length == 0)
4336 {
4337 /* Handle pseudo prefixes. */
4338 switch (current_templates->start->base_opcode)
4339 {
4340 case 0x0:
4341 /* {disp8} */
4342 i.disp_encoding = disp_encoding_8bit;
4343 break;
4344 case 0x1:
4345 /* {disp32} */
4346 i.disp_encoding = disp_encoding_32bit;
4347 break;
4348 case 0x2:
4349 /* {load} */
4350 i.dir_encoding = dir_encoding_load;
4351 break;
4352 case 0x3:
4353 /* {store} */
4354 i.dir_encoding = dir_encoding_store;
4355 break;
4356 case 0x4:
4357 /* {vex2} */
4358 i.vec_encoding = vex_encoding_vex2;
4359 break;
4360 case 0x5:
4361 /* {vex3} */
4362 i.vec_encoding = vex_encoding_vex3;
4363 break;
4364 case 0x6:
4365 /* {evex} */
4366 i.vec_encoding = vex_encoding_evex;
4367 break;
4368 case 0x7:
4369 /* {rex} */
4370 i.rex_encoding = TRUE;
4371 break;
4372 case 0x8:
4373 /* {nooptimize} */
4374 i.no_optimize = TRUE;
4375 break;
4376 default:
4377 abort ();
4378 }
4379 }
4380 else
4381 {
4382 /* Add prefix, checking for repeated prefixes. */
4383 switch (add_prefix (current_templates->start->base_opcode))
4384 {
4385 case PREFIX_EXIST:
4386 return NULL;
4387 case PREFIX_DS:
4388 if (current_templates->start->cpu_flags.bitfield.cpuibt)
4389 i.notrack_prefix = current_templates->start->name;
4390 break;
4391 case PREFIX_REP:
4392 if (current_templates->start->cpu_flags.bitfield.cpuhle)
4393 i.hle_prefix = current_templates->start->name;
4394 else if (current_templates->start->cpu_flags.bitfield.cpumpx)
4395 i.bnd_prefix = current_templates->start->name;
4396 else
4397 i.rep_prefix = current_templates->start->name;
4398 break;
4399 default:
4400 break;
4401 }
4402 }
4403 /* Skip past PREFIX_SEPARATOR and reset token_start. */
4404 token_start = ++l;
4405 }
4406 else
4407 break;
4408 }
4409
4410 if (!current_templates)
4411 {
4412 /* Check if we should swap operand or force 32bit displacement in
4413 encoding. */
4414 if (mnem_p - 2 == dot_p && dot_p[1] == 's')
4415 i.dir_encoding = dir_encoding_store;
4416 else if (mnem_p - 3 == dot_p
4417 && dot_p[1] == 'd'
4418 && dot_p[2] == '8')
4419 i.disp_encoding = disp_encoding_8bit;
4420 else if (mnem_p - 4 == dot_p
4421 && dot_p[1] == 'd'
4422 && dot_p[2] == '3'
4423 && dot_p[3] == '2')
4424 i.disp_encoding = disp_encoding_32bit;
4425 else
4426 goto check_suffix;
4427 mnem_p = dot_p;
4428 *dot_p = '\0';
4429 current_templates = (const templates *) hash_find (op_hash, mnemonic);
4430 }
4431
4432 if (!current_templates)
4433 {
4434 check_suffix:
4435 /* See if we can get a match by trimming off a suffix. */
4436 switch (mnem_p[-1])
4437 {
4438 case WORD_MNEM_SUFFIX:
4439 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
4440 i.suffix = SHORT_MNEM_SUFFIX;
4441 else
4442 /* Fall through. */
4443 case BYTE_MNEM_SUFFIX:
4444 case QWORD_MNEM_SUFFIX:
4445 i.suffix = mnem_p[-1];
4446 mnem_p[-1] = '\0';
4447 current_templates = (const templates *) hash_find (op_hash,
4448 mnemonic);
4449 break;
4450 case SHORT_MNEM_SUFFIX:
4451 case LONG_MNEM_SUFFIX:
4452 if (!intel_syntax)
4453 {
4454 i.suffix = mnem_p[-1];
4455 mnem_p[-1] = '\0';
4456 current_templates = (const templates *) hash_find (op_hash,
4457 mnemonic);
4458 }
4459 break;
4460
4461 /* Intel Syntax. */
4462 case 'd':
4463 if (intel_syntax)
4464 {
4465 if (intel_float_operand (mnemonic) == 1)
4466 i.suffix = SHORT_MNEM_SUFFIX;
4467 else
4468 i.suffix = LONG_MNEM_SUFFIX;
4469 mnem_p[-1] = '\0';
4470 current_templates = (const templates *) hash_find (op_hash,
4471 mnemonic);
4472 }
4473 break;
4474 }
4475 if (!current_templates)
4476 {
4477 as_bad (_("no such instruction: `%s'"), token_start);
4478 return NULL;
4479 }
4480 }
4481
4482 if (current_templates->start->opcode_modifier.jump
4483 || current_templates->start->opcode_modifier.jumpbyte)
4484 {
4485 /* Check for a branch hint. We allow ",pt" and ",pn" for
4486 predict taken and predict not taken respectively.
4487 I'm not sure that branch hints actually do anything on loop
4488 and jcxz insns (JumpByte) for current Pentium4 chips. They
4489 may work in the future and it doesn't hurt to accept them
4490 now. */
4491 if (l[0] == ',' && l[1] == 'p')
4492 {
4493 if (l[2] == 't')
4494 {
4495 if (!add_prefix (DS_PREFIX_OPCODE))
4496 return NULL;
4497 l += 3;
4498 }
4499 else if (l[2] == 'n')
4500 {
4501 if (!add_prefix (CS_PREFIX_OPCODE))
4502 return NULL;
4503 l += 3;
4504 }
4505 }
4506 }
4507 /* Any other comma loses. */
4508 if (*l == ',')
4509 {
4510 as_bad (_("invalid character %s in mnemonic"),
4511 output_invalid (*l));
4512 return NULL;
4513 }
4514
4515 /* Check if instruction is supported on specified architecture. */
4516 supported = 0;
4517 for (t = current_templates->start; t < current_templates->end; ++t)
4518 {
4519 supported |= cpu_flags_match (t);
4520 if (supported == CPU_FLAGS_PERFECT_MATCH)
4521 {
4522 if (!cpu_arch_flags.bitfield.cpui386 && (flag_code != CODE_16BIT))
4523 as_warn (_("use .code16 to ensure correct addressing mode"));
4524
4525 return l;
4526 }
4527 }
4528
4529 if (!(supported & CPU_FLAGS_64BIT_MATCH))
4530 as_bad (flag_code == CODE_64BIT
4531 ? _("`%s' is not supported in 64-bit mode")
4532 : _("`%s' is only supported in 64-bit mode"),
4533 current_templates->start->name);
4534 else
4535 as_bad (_("`%s' is not supported on `%s%s'"),
4536 current_templates->start->name,
4537 cpu_arch_name ? cpu_arch_name : default_arch,
4538 cpu_sub_arch_name ? cpu_sub_arch_name : "");
4539
4540 return NULL;
4541 }
4542
4543 static char *
4544 parse_operands (char *l, const char *mnemonic)
4545 {
4546 char *token_start;
4547
4548 /* 1 if operand is pending after ','. */
4549 unsigned int expecting_operand = 0;
4550
4551 /* Non-zero if operand parens not balanced. */
4552 unsigned int paren_not_balanced;
4553
4554 while (*l != END_OF_INSN)
4555 {
4556 /* Skip optional white space before operand. */
4557 if (is_space_char (*l))
4558 ++l;
4559 if (!is_operand_char (*l) && *l != END_OF_INSN && *l != '"')
4560 {
4561 as_bad (_("invalid character %s before operand %d"),
4562 output_invalid (*l),
4563 i.operands + 1);
4564 return NULL;
4565 }
4566 token_start = l; /* After white space. */
4567 paren_not_balanced = 0;
4568 while (paren_not_balanced || *l != ',')
4569 {
4570 if (*l == END_OF_INSN)
4571 {
4572 if (paren_not_balanced)
4573 {
4574 if (!intel_syntax)
4575 as_bad (_("unbalanced parenthesis in operand %d."),
4576 i.operands + 1);
4577 else
4578 as_bad (_("unbalanced brackets in operand %d."),
4579 i.operands + 1);
4580 return NULL;
4581 }
4582 else
4583 break; /* we are done */
4584 }
4585 else if (!is_operand_char (*l) && !is_space_char (*l) && *l != '"')
4586 {
4587 as_bad (_("invalid character %s in operand %d"),
4588 output_invalid (*l),
4589 i.operands + 1);
4590 return NULL;
4591 }
4592 if (!intel_syntax)
4593 {
4594 if (*l == '(')
4595 ++paren_not_balanced;
4596 if (*l == ')')
4597 --paren_not_balanced;
4598 }
4599 else
4600 {
4601 if (*l == '[')
4602 ++paren_not_balanced;
4603 if (*l == ']')
4604 --paren_not_balanced;
4605 }
4606 l++;
4607 }
4608 if (l != token_start)
4609 { /* Yes, we've read in another operand. */
4610 unsigned int operand_ok;
4611 this_operand = i.operands++;
4612 if (i.operands > MAX_OPERANDS)
4613 {
4614 as_bad (_("spurious operands; (%d operands/instruction max)"),
4615 MAX_OPERANDS);
4616 return NULL;
4617 }
4618 i.types[this_operand].bitfield.unspecified = 1;
4619 /* Now parse operand adding info to 'i' as we go along. */
4620 END_STRING_AND_SAVE (l);
4621
4622 if (intel_syntax)
4623 operand_ok =
4624 i386_intel_operand (token_start,
4625 intel_float_operand (mnemonic));
4626 else
4627 operand_ok = i386_att_operand (token_start);
4628
4629 RESTORE_END_STRING (l);
4630 if (!operand_ok)
4631 return NULL;
4632 }
4633 else
4634 {
4635 if (expecting_operand)
4636 {
4637 expecting_operand_after_comma:
4638 as_bad (_("expecting operand after ','; got nothing"));
4639 return NULL;
4640 }
4641 if (*l == ',')
4642 {
4643 as_bad (_("expecting operand before ','; got nothing"));
4644 return NULL;
4645 }
4646 }
4647
4648 /* Now *l must be either ',' or END_OF_INSN. */
4649 if (*l == ',')
4650 {
4651 if (*++l == END_OF_INSN)
4652 {
4653 /* Just skip it, if it's \n complain. */
4654 goto expecting_operand_after_comma;
4655 }
4656 expecting_operand = 1;
4657 }
4658 }
4659 return l;
4660 }
4661
4662 static void
4663 swap_2_operands (int xchg1, int xchg2)
4664 {
4665 union i386_op temp_op;
4666 i386_operand_type temp_type;
4667 enum bfd_reloc_code_real temp_reloc;
4668
4669 temp_type = i.types[xchg2];
4670 i.types[xchg2] = i.types[xchg1];
4671 i.types[xchg1] = temp_type;
4672 temp_op = i.op[xchg2];
4673 i.op[xchg2] = i.op[xchg1];
4674 i.op[xchg1] = temp_op;
4675 temp_reloc = i.reloc[xchg2];
4676 i.reloc[xchg2] = i.reloc[xchg1];
4677 i.reloc[xchg1] = temp_reloc;
4678
4679 if (i.mask)
4680 {
4681 if (i.mask->operand == xchg1)
4682 i.mask->operand = xchg2;
4683 else if (i.mask->operand == xchg2)
4684 i.mask->operand = xchg1;
4685 }
4686 if (i.broadcast)
4687 {
4688 if (i.broadcast->operand == xchg1)
4689 i.broadcast->operand = xchg2;
4690 else if (i.broadcast->operand == xchg2)
4691 i.broadcast->operand = xchg1;
4692 }
4693 if (i.rounding)
4694 {
4695 if (i.rounding->operand == xchg1)
4696 i.rounding->operand = xchg2;
4697 else if (i.rounding->operand == xchg2)
4698 i.rounding->operand = xchg1;
4699 }
4700 }
4701
4702 static void
4703 swap_operands (void)
4704 {
4705 switch (i.operands)
4706 {
4707 case 5:
4708 case 4:
4709 swap_2_operands (1, i.operands - 2);
4710 /* Fall through. */
4711 case 3:
4712 case 2:
4713 swap_2_operands (0, i.operands - 1);
4714 break;
4715 default:
4716 abort ();
4717 }
4718
4719 if (i.mem_operands == 2)
4720 {
4721 const seg_entry *temp_seg;
4722 temp_seg = i.seg[0];
4723 i.seg[0] = i.seg[1];
4724 i.seg[1] = temp_seg;
4725 }
4726 }
4727
4728 /* Try to ensure constant immediates are represented in the smallest
4729 opcode possible. */
4730 static void
4731 optimize_imm (void)
4732 {
4733 char guess_suffix = 0;
4734 int op;
4735
4736 if (i.suffix)
4737 guess_suffix = i.suffix;
4738 else if (i.reg_operands)
4739 {
4740 /* Figure out a suffix from the last register operand specified.
4741 We can't do this properly yet, ie. excluding InOutPortReg,
4742 but the following works for instructions with immediates.
4743 In any case, we can't set i.suffix yet. */
4744 for (op = i.operands; --op >= 0;)
4745 if (i.types[op].bitfield.reg && i.types[op].bitfield.byte)
4746 {
4747 guess_suffix = BYTE_MNEM_SUFFIX;
4748 break;
4749 }
4750 else if (i.types[op].bitfield.reg && i.types[op].bitfield.word)
4751 {
4752 guess_suffix = WORD_MNEM_SUFFIX;
4753 break;
4754 }
4755 else if (i.types[op].bitfield.reg && i.types[op].bitfield.dword)
4756 {
4757 guess_suffix = LONG_MNEM_SUFFIX;
4758 break;
4759 }
4760 else if (i.types[op].bitfield.reg && i.types[op].bitfield.qword)
4761 {
4762 guess_suffix = QWORD_MNEM_SUFFIX;
4763 break;
4764 }
4765 }
4766 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
4767 guess_suffix = WORD_MNEM_SUFFIX;
4768
4769 for (op = i.operands; --op >= 0;)
4770 if (operand_type_check (i.types[op], imm))
4771 {
4772 switch (i.op[op].imms->X_op)
4773 {
4774 case O_constant:
4775 /* If a suffix is given, this operand may be shortened. */
4776 switch (guess_suffix)
4777 {
4778 case LONG_MNEM_SUFFIX:
4779 i.types[op].bitfield.imm32 = 1;
4780 i.types[op].bitfield.imm64 = 1;
4781 break;
4782 case WORD_MNEM_SUFFIX:
4783 i.types[op].bitfield.imm16 = 1;
4784 i.types[op].bitfield.imm32 = 1;
4785 i.types[op].bitfield.imm32s = 1;
4786 i.types[op].bitfield.imm64 = 1;
4787 break;
4788 case BYTE_MNEM_SUFFIX:
4789 i.types[op].bitfield.imm8 = 1;
4790 i.types[op].bitfield.imm8s = 1;
4791 i.types[op].bitfield.imm16 = 1;
4792 i.types[op].bitfield.imm32 = 1;
4793 i.types[op].bitfield.imm32s = 1;
4794 i.types[op].bitfield.imm64 = 1;
4795 break;
4796 }
4797
4798 /* If this operand is at most 16 bits, convert it
4799 to a signed 16 bit number before trying to see
4800 whether it will fit in an even smaller size.
4801 This allows a 16-bit operand such as $0xffe0 to
4802 be recognised as within Imm8S range. */
4803 if ((i.types[op].bitfield.imm16)
4804 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
4805 {
4806 i.op[op].imms->X_add_number =
4807 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
4808 }
4809 #ifdef BFD64
4810 /* Store 32-bit immediate in 64-bit for 64-bit BFD. */
4811 if ((i.types[op].bitfield.imm32)
4812 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
4813 == 0))
4814 {
4815 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
4816 ^ ((offsetT) 1 << 31))
4817 - ((offsetT) 1 << 31));
4818 }
4819 #endif
4820 i.types[op]
4821 = operand_type_or (i.types[op],
4822 smallest_imm_type (i.op[op].imms->X_add_number));
4823
4824 /* We must avoid matching of Imm32 templates when 64bit
4825 only immediate is available. */
4826 if (guess_suffix == QWORD_MNEM_SUFFIX)
4827 i.types[op].bitfield.imm32 = 0;
4828 break;
4829
4830 case O_absent:
4831 case O_register:
4832 abort ();
4833
4834 /* Symbols and expressions. */
4835 default:
4836 /* Convert symbolic operand to proper sizes for matching, but don't
4837 prevent matching a set of insns that only supports sizes other
4838 than those matching the insn suffix. */
4839 {
4840 i386_operand_type mask, allowed;
4841 const insn_template *t;
4842
4843 operand_type_set (&mask, 0);
4844 operand_type_set (&allowed, 0);
4845
4846 for (t = current_templates->start;
4847 t < current_templates->end;
4848 ++t)
4849 allowed = operand_type_or (allowed,
4850 t->operand_types[op]);
4851 switch (guess_suffix)
4852 {
4853 case QWORD_MNEM_SUFFIX:
4854 mask.bitfield.imm64 = 1;
4855 mask.bitfield.imm32s = 1;
4856 break;
4857 case LONG_MNEM_SUFFIX:
4858 mask.bitfield.imm32 = 1;
4859 break;
4860 case WORD_MNEM_SUFFIX:
4861 mask.bitfield.imm16 = 1;
4862 break;
4863 case BYTE_MNEM_SUFFIX:
4864 mask.bitfield.imm8 = 1;
4865 break;
4866 default:
4867 break;
4868 }
4869 allowed = operand_type_and (mask, allowed);
4870 if (!operand_type_all_zero (&allowed))
4871 i.types[op] = operand_type_and (i.types[op], mask);
4872 }
4873 break;
4874 }
4875 }
4876 }
4877
4878 /* Try to use the smallest displacement type too. */
4879 static void
4880 optimize_disp (void)
4881 {
4882 int op;
4883
4884 for (op = i.operands; --op >= 0;)
4885 if (operand_type_check (i.types[op], disp))
4886 {
4887 if (i.op[op].disps->X_op == O_constant)
4888 {
4889 offsetT op_disp = i.op[op].disps->X_add_number;
4890
4891 if (i.types[op].bitfield.disp16
4892 && (op_disp & ~(offsetT) 0xffff) == 0)
4893 {
4894 /* If this operand is at most 16 bits, convert
4895 to a signed 16 bit number and don't use 64bit
4896 displacement. */
4897 op_disp = (((op_disp & 0xffff) ^ 0x8000) - 0x8000);
4898 i.types[op].bitfield.disp64 = 0;
4899 }
4900 #ifdef BFD64
4901 /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */
4902 if (i.types[op].bitfield.disp32
4903 && (op_disp & ~(((offsetT) 2 << 31) - 1)) == 0)
4904 {
4905 /* If this operand is at most 32 bits, convert
4906 to a signed 32 bit number and don't use 64bit
4907 displacement. */
4908 op_disp &= (((offsetT) 2 << 31) - 1);
4909 op_disp = (op_disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
4910 i.types[op].bitfield.disp64 = 0;
4911 }
4912 #endif
4913 if (!op_disp && i.types[op].bitfield.baseindex)
4914 {
4915 i.types[op].bitfield.disp8 = 0;
4916 i.types[op].bitfield.disp16 = 0;
4917 i.types[op].bitfield.disp32 = 0;
4918 i.types[op].bitfield.disp32s = 0;
4919 i.types[op].bitfield.disp64 = 0;
4920 i.op[op].disps = 0;
4921 i.disp_operands--;
4922 }
4923 else if (flag_code == CODE_64BIT)
4924 {
4925 if (fits_in_signed_long (op_disp))
4926 {
4927 i.types[op].bitfield.disp64 = 0;
4928 i.types[op].bitfield.disp32s = 1;
4929 }
4930 if (i.prefix[ADDR_PREFIX]
4931 && fits_in_unsigned_long (op_disp))
4932 i.types[op].bitfield.disp32 = 1;
4933 }
4934 if ((i.types[op].bitfield.disp32
4935 || i.types[op].bitfield.disp32s
4936 || i.types[op].bitfield.disp16)
4937 && fits_in_disp8 (op_disp))
4938 i.types[op].bitfield.disp8 = 1;
4939 }
4940 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
4941 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
4942 {
4943 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
4944 i.op[op].disps, 0, i.reloc[op]);
4945 i.types[op].bitfield.disp8 = 0;
4946 i.types[op].bitfield.disp16 = 0;
4947 i.types[op].bitfield.disp32 = 0;
4948 i.types[op].bitfield.disp32s = 0;
4949 i.types[op].bitfield.disp64 = 0;
4950 }
4951 else
4952 /* We only support 64bit displacement on constants. */
4953 i.types[op].bitfield.disp64 = 0;
4954 }
4955 }
4956
4957 /* Check if operands are valid for the instruction. */
4958
4959 static int
4960 check_VecOperands (const insn_template *t)
4961 {
4962 unsigned int op;
4963
4964 /* Without VSIB byte, we can't have a vector register for index. */
4965 if (!t->opcode_modifier.vecsib
4966 && i.index_reg
4967 && (i.index_reg->reg_type.bitfield.xmmword
4968 || i.index_reg->reg_type.bitfield.ymmword
4969 || i.index_reg->reg_type.bitfield.zmmword))
4970 {
4971 i.error = unsupported_vector_index_register;
4972 return 1;
4973 }
4974
4975 /* Check if default mask is allowed. */
4976 if (t->opcode_modifier.nodefmask
4977 && (!i.mask || i.mask->mask->reg_num == 0))
4978 {
4979 i.error = no_default_mask;
4980 return 1;
4981 }
4982
4983 /* For VSIB byte, we need a vector register for index, and all vector
4984 registers must be distinct. */
4985 if (t->opcode_modifier.vecsib)
4986 {
4987 if (!i.index_reg
4988 || !((t->opcode_modifier.vecsib == VecSIB128
4989 && i.index_reg->reg_type.bitfield.xmmword)
4990 || (t->opcode_modifier.vecsib == VecSIB256
4991 && i.index_reg->reg_type.bitfield.ymmword)
4992 || (t->opcode_modifier.vecsib == VecSIB512
4993 && i.index_reg->reg_type.bitfield.zmmword)))
4994 {
4995 i.error = invalid_vsib_address;
4996 return 1;
4997 }
4998
4999 gas_assert (i.reg_operands == 2 || i.mask);
5000 if (i.reg_operands == 2 && !i.mask)
5001 {
5002 gas_assert (i.types[0].bitfield.regsimd);
5003 gas_assert (i.types[0].bitfield.xmmword
5004 || i.types[0].bitfield.ymmword);
5005 gas_assert (i.types[2].bitfield.regsimd);
5006 gas_assert (i.types[2].bitfield.xmmword
5007 || i.types[2].bitfield.ymmword);
5008 if (operand_check == check_none)
5009 return 0;
5010 if (register_number (i.op[0].regs)
5011 != register_number (i.index_reg)
5012 && register_number (i.op[2].regs)
5013 != register_number (i.index_reg)
5014 && register_number (i.op[0].regs)
5015 != register_number (i.op[2].regs))
5016 return 0;
5017 if (operand_check == check_error)
5018 {
5019 i.error = invalid_vector_register_set;
5020 return 1;
5021 }
5022 as_warn (_("mask, index, and destination registers should be distinct"));
5023 }
5024 else if (i.reg_operands == 1 && i.mask)
5025 {
5026 if (i.types[1].bitfield.regsimd
5027 && (i.types[1].bitfield.xmmword
5028 || i.types[1].bitfield.ymmword
5029 || i.types[1].bitfield.zmmword)
5030 && (register_number (i.op[1].regs)
5031 == register_number (i.index_reg)))
5032 {
5033 if (operand_check == check_error)
5034 {
5035 i.error = invalid_vector_register_set;
5036 return 1;
5037 }
5038 if (operand_check != check_none)
5039 as_warn (_("index and destination registers should be distinct"));
5040 }
5041 }
5042 }
5043
5044 /* Check if broadcast is supported by the instruction and is applied
5045 to the memory operand. */
5046 if (i.broadcast)
5047 {
5048 int broadcasted_opnd_size;
5049
5050 /* Check if specified broadcast is supported in this instruction,
5051 and it's applied to memory operand of DWORD or QWORD type,
5052 depending on VecESize. */
5053 if (i.broadcast->type != t->opcode_modifier.broadcast
5054 || !i.types[i.broadcast->operand].bitfield.mem
5055 || (t->opcode_modifier.vecesize == 0
5056 && !i.types[i.broadcast->operand].bitfield.dword
5057 && !i.types[i.broadcast->operand].bitfield.unspecified)
5058 || (t->opcode_modifier.vecesize == 1
5059 && !i.types[i.broadcast->operand].bitfield.qword
5060 && !i.types[i.broadcast->operand].bitfield.unspecified))
5061 goto bad_broadcast;
5062
5063 broadcasted_opnd_size = t->opcode_modifier.vecesize ? 64 : 32;
5064 if (i.broadcast->type == BROADCAST_1TO16)
5065 broadcasted_opnd_size <<= 4; /* Broadcast 1to16. */
5066 else if (i.broadcast->type == BROADCAST_1TO8)
5067 broadcasted_opnd_size <<= 3; /* Broadcast 1to8. */
5068 else if (i.broadcast->type == BROADCAST_1TO4)
5069 broadcasted_opnd_size <<= 2; /* Broadcast 1to4. */
5070 else if (i.broadcast->type == BROADCAST_1TO2)
5071 broadcasted_opnd_size <<= 1; /* Broadcast 1to2. */
5072 else
5073 goto bad_broadcast;
5074
5075 if ((broadcasted_opnd_size == 256
5076 && !t->operand_types[i.broadcast->operand].bitfield.ymmword)
5077 || (broadcasted_opnd_size == 512
5078 && !t->operand_types[i.broadcast->operand].bitfield.zmmword))
5079 {
5080 bad_broadcast:
5081 i.error = unsupported_broadcast;
5082 return 1;
5083 }
5084 }
5085 /* If broadcast is supported in this instruction, we need to check if
5086 operand of one-element size isn't specified without broadcast. */
5087 else if (t->opcode_modifier.broadcast && i.mem_operands)
5088 {
5089 /* Find memory operand. */
5090 for (op = 0; op < i.operands; op++)
5091 if (operand_type_check (i.types[op], anymem))
5092 break;
5093 gas_assert (op < i.operands);
5094 /* Check size of the memory operand. */
5095 if ((t->opcode_modifier.vecesize == 0
5096 && i.types[op].bitfield.dword)
5097 || (t->opcode_modifier.vecesize == 1
5098 && i.types[op].bitfield.qword))
5099 {
5100 i.error = broadcast_needed;
5101 return 1;
5102 }
5103 }
5104
5105 /* Check if requested masking is supported. */
5106 if (i.mask
5107 && (!t->opcode_modifier.masking
5108 || (i.mask->zeroing
5109 && t->opcode_modifier.masking == MERGING_MASKING)))
5110 {
5111 i.error = unsupported_masking;
5112 return 1;
5113 }
5114
5115 /* Check if masking is applied to dest operand. */
5116 if (i.mask && (i.mask->operand != (int) (i.operands - 1)))
5117 {
5118 i.error = mask_not_on_destination;
5119 return 1;
5120 }
5121
5122 /* Check RC/SAE. */
5123 if (i.rounding)
5124 {
5125 if ((i.rounding->type != saeonly
5126 && !t->opcode_modifier.staticrounding)
5127 || (i.rounding->type == saeonly
5128 && (t->opcode_modifier.staticrounding
5129 || !t->opcode_modifier.sae)))
5130 {
5131 i.error = unsupported_rc_sae;
5132 return 1;
5133 }
5134 /* If the instruction has several immediate operands and one of
5135 them is rounding, the rounding operand should be the last
5136 immediate operand. */
5137 if (i.imm_operands > 1
5138 && i.rounding->operand != (int) (i.imm_operands - 1))
5139 {
5140 i.error = rc_sae_operand_not_last_imm;
5141 return 1;
5142 }
5143 }
5144
5145 /* Check vector Disp8 operand. */
5146 if (t->opcode_modifier.disp8memshift
5147 && i.disp_encoding != disp_encoding_32bit)
5148 {
5149 if (i.broadcast)
5150 i.memshift = t->opcode_modifier.vecesize ? 3 : 2;
5151 else
5152 i.memshift = t->opcode_modifier.disp8memshift;
5153
5154 for (op = 0; op < i.operands; op++)
5155 if (operand_type_check (i.types[op], disp)
5156 && i.op[op].disps->X_op == O_constant)
5157 {
5158 if (fits_in_disp8 (i.op[op].disps->X_add_number))
5159 {
5160 i.types[op].bitfield.disp8 = 1;
5161 return 0;
5162 }
5163 i.types[op].bitfield.disp8 = 0;
5164 }
5165 }
5166
5167 i.memshift = 0;
5168
5169 return 0;
5170 }
5171
5172 /* Check if operands are valid for the instruction. Update VEX
5173 operand types. */
5174
5175 static int
5176 VEX_check_operands (const insn_template *t)
5177 {
5178 if (i.vec_encoding == vex_encoding_evex)
5179 {
5180 /* This instruction must be encoded with EVEX prefix. */
5181 if (!is_evex_encoding (t))
5182 {
5183 i.error = unsupported;
5184 return 1;
5185 }
5186 return 0;
5187 }
5188
5189 if (!t->opcode_modifier.vex)
5190 {
5191 /* This instruction template doesn't have VEX prefix. */
5192 if (i.vec_encoding != vex_encoding_default)
5193 {
5194 i.error = unsupported;
5195 return 1;
5196 }
5197 return 0;
5198 }
5199
5200 /* Only check VEX_Imm4, which must be the first operand. */
5201 if (t->operand_types[0].bitfield.vec_imm4)
5202 {
5203 if (i.op[0].imms->X_op != O_constant
5204 || !fits_in_imm4 (i.op[0].imms->X_add_number))
5205 {
5206 i.error = bad_imm4;
5207 return 1;
5208 }
5209
5210 /* Turn off Imm8 so that update_imm won't complain. */
5211 i.types[0] = vec_imm4;
5212 }
5213
5214 return 0;
5215 }
5216
5217 static const insn_template *
5218 match_template (char mnem_suffix)
5219 {
5220 /* Points to template once we've found it. */
5221 const insn_template *t;
5222 i386_operand_type overlap0, overlap1, overlap2, overlap3;
5223 i386_operand_type overlap4;
5224 unsigned int found_reverse_match;
5225 i386_opcode_modifier suffix_check, mnemsuf_check;
5226 i386_operand_type operand_types [MAX_OPERANDS];
5227 int addr_prefix_disp;
5228 unsigned int j;
5229 unsigned int found_cpu_match;
5230 unsigned int check_register;
5231 enum i386_error specific_error = 0;
5232
5233 #if MAX_OPERANDS != 5
5234 # error "MAX_OPERANDS must be 5."
5235 #endif
5236
5237 found_reverse_match = 0;
5238 addr_prefix_disp = -1;
5239
5240 memset (&suffix_check, 0, sizeof (suffix_check));
5241 if (i.suffix == BYTE_MNEM_SUFFIX)
5242 suffix_check.no_bsuf = 1;
5243 else if (i.suffix == WORD_MNEM_SUFFIX)
5244 suffix_check.no_wsuf = 1;
5245 else if (i.suffix == SHORT_MNEM_SUFFIX)
5246 suffix_check.no_ssuf = 1;
5247 else if (i.suffix == LONG_MNEM_SUFFIX)
5248 suffix_check.no_lsuf = 1;
5249 else if (i.suffix == QWORD_MNEM_SUFFIX)
5250 suffix_check.no_qsuf = 1;
5251 else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX)
5252 suffix_check.no_ldsuf = 1;
5253
5254 memset (&mnemsuf_check, 0, sizeof (mnemsuf_check));
5255 if (intel_syntax)
5256 {
5257 switch (mnem_suffix)
5258 {
5259 case BYTE_MNEM_SUFFIX: mnemsuf_check.no_bsuf = 1; break;
5260 case WORD_MNEM_SUFFIX: mnemsuf_check.no_wsuf = 1; break;
5261 case SHORT_MNEM_SUFFIX: mnemsuf_check.no_ssuf = 1; break;
5262 case LONG_MNEM_SUFFIX: mnemsuf_check.no_lsuf = 1; break;
5263 case QWORD_MNEM_SUFFIX: mnemsuf_check.no_qsuf = 1; break;
5264 }
5265 }
5266
5267 /* Must have right number of operands. */
5268 i.error = number_of_operands_mismatch;
5269
5270 for (t = current_templates->start; t < current_templates->end; t++)
5271 {
5272 addr_prefix_disp = -1;
5273
5274 if (i.operands != t->operands)
5275 continue;
5276
5277 /* Check processor support. */
5278 i.error = unsupported;
5279 found_cpu_match = (cpu_flags_match (t)
5280 == CPU_FLAGS_PERFECT_MATCH);
5281 if (!found_cpu_match)
5282 continue;
5283
5284 /* Check AT&T mnemonic. */
5285 i.error = unsupported_with_intel_mnemonic;
5286 if (intel_mnemonic && t->opcode_modifier.attmnemonic)
5287 continue;
5288
5289 /* Check AT&T/Intel syntax and Intel64/AMD64 ISA. */
5290 i.error = unsupported_syntax;
5291 if ((intel_syntax && t->opcode_modifier.attsyntax)
5292 || (!intel_syntax && t->opcode_modifier.intelsyntax)
5293 || (intel64 && t->opcode_modifier.amd64)
5294 || (!intel64 && t->opcode_modifier.intel64))
5295 continue;
5296
5297 /* Check the suffix, except for some instructions in intel mode. */
5298 i.error = invalid_instruction_suffix;
5299 if ((!intel_syntax || !t->opcode_modifier.ignoresize)
5300 && ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf)
5301 || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf)
5302 || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf)
5303 || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf)
5304 || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf)
5305 || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf)))
5306 continue;
5307 /* In Intel mode all mnemonic suffixes must be explicitly allowed. */
5308 if ((t->opcode_modifier.no_bsuf && mnemsuf_check.no_bsuf)
5309 || (t->opcode_modifier.no_wsuf && mnemsuf_check.no_wsuf)
5310 || (t->opcode_modifier.no_lsuf && mnemsuf_check.no_lsuf)
5311 || (t->opcode_modifier.no_ssuf && mnemsuf_check.no_ssuf)
5312 || (t->opcode_modifier.no_qsuf && mnemsuf_check.no_qsuf)
5313 || (t->opcode_modifier.no_ldsuf && mnemsuf_check.no_ldsuf))
5314 continue;
5315
5316 if (!operand_size_match (t))
5317 continue;
5318
5319 for (j = 0; j < MAX_OPERANDS; j++)
5320 operand_types[j] = t->operand_types[j];
5321
5322 /* In general, don't allow 64-bit operands in 32-bit mode. */
5323 if (i.suffix == QWORD_MNEM_SUFFIX
5324 && flag_code != CODE_64BIT
5325 && (intel_syntax
5326 ? (!t->opcode_modifier.ignoresize
5327 && !intel_float_operand (t->name))
5328 : intel_float_operand (t->name) != 2)
5329 && ((!operand_types[0].bitfield.regmmx
5330 && !operand_types[0].bitfield.regsimd)
5331 || (!operand_types[t->operands > 1].bitfield.regmmx
5332 && !operand_types[t->operands > 1].bitfield.regsimd))
5333 && (t->base_opcode != 0x0fc7
5334 || t->extension_opcode != 1 /* cmpxchg8b */))
5335 continue;
5336
5337 /* In general, don't allow 32-bit operands on pre-386. */
5338 else if (i.suffix == LONG_MNEM_SUFFIX
5339 && !cpu_arch_flags.bitfield.cpui386
5340 && (intel_syntax
5341 ? (!t->opcode_modifier.ignoresize
5342 && !intel_float_operand (t->name))
5343 : intel_float_operand (t->name) != 2)
5344 && ((!operand_types[0].bitfield.regmmx
5345 && !operand_types[0].bitfield.regsimd)
5346 || (!operand_types[t->operands > 1].bitfield.regmmx
5347 && !operand_types[t->operands > 1].bitfield.regsimd)))
5348 continue;
5349
5350 /* Do not verify operands when there are none. */
5351 else
5352 {
5353 if (!t->operands)
5354 /* We've found a match; break out of loop. */
5355 break;
5356 }
5357
5358 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
5359 into Disp32/Disp16/Disp32 operand. */
5360 if (i.prefix[ADDR_PREFIX] != 0)
5361 {
5362 /* There should be only one Disp operand. */
5363 switch (flag_code)
5364 {
5365 case CODE_16BIT:
5366 for (j = 0; j < MAX_OPERANDS; j++)
5367 {
5368 if (operand_types[j].bitfield.disp16)
5369 {
5370 addr_prefix_disp = j;
5371 operand_types[j].bitfield.disp32 = 1;
5372 operand_types[j].bitfield.disp16 = 0;
5373 break;
5374 }
5375 }
5376 break;
5377 case CODE_32BIT:
5378 for (j = 0; j < MAX_OPERANDS; j++)
5379 {
5380 if (operand_types[j].bitfield.disp32)
5381 {
5382 addr_prefix_disp = j;
5383 operand_types[j].bitfield.disp32 = 0;
5384 operand_types[j].bitfield.disp16 = 1;
5385 break;
5386 }
5387 }
5388 break;
5389 case CODE_64BIT:
5390 for (j = 0; j < MAX_OPERANDS; j++)
5391 {
5392 if (operand_types[j].bitfield.disp64)
5393 {
5394 addr_prefix_disp = j;
5395 operand_types[j].bitfield.disp64 = 0;
5396 operand_types[j].bitfield.disp32 = 1;
5397 break;
5398 }
5399 }
5400 break;
5401 }
5402 }
5403
5404 /* Force 0x8b encoding for "mov foo@GOT, %eax". */
5405 if (i.reloc[0] == BFD_RELOC_386_GOT32 && t->base_opcode == 0xa0)
5406 continue;
5407
5408 /* We check register size if needed. */
5409 check_register = t->opcode_modifier.checkregsize;
5410 overlap0 = operand_type_and (i.types[0], operand_types[0]);
5411 switch (t->operands)
5412 {
5413 case 1:
5414 if (!operand_type_match (overlap0, i.types[0]))
5415 continue;
5416 break;
5417 case 2:
5418 /* xchg %eax, %eax is a special case. It is an alias for nop
5419 only in 32bit mode and we can use opcode 0x90. In 64bit
5420 mode, we can't use 0x90 for xchg %eax, %eax since it should
5421 zero-extend %eax to %rax. */
5422 if (flag_code == CODE_64BIT
5423 && t->base_opcode == 0x90
5424 && operand_type_equal (&i.types [0], &acc32)
5425 && operand_type_equal (&i.types [1], &acc32))
5426 continue;
5427 /* If we want store form, we reverse direction of operands. */
5428 if (i.dir_encoding == dir_encoding_store
5429 && t->opcode_modifier.d)
5430 goto check_reverse;
5431 /* Fall through. */
5432
5433 case 3:
5434 /* If we want store form, we skip the current load. */
5435 if (i.dir_encoding == dir_encoding_store
5436 && i.mem_operands == 0
5437 && t->opcode_modifier.load)
5438 continue;
5439 /* Fall through. */
5440 case 4:
5441 case 5:
5442 overlap1 = operand_type_and (i.types[1], operand_types[1]);
5443 if (!operand_type_match (overlap0, i.types[0])
5444 || !operand_type_match (overlap1, i.types[1])
5445 || (check_register
5446 && !operand_type_register_match (i.types[0],
5447 operand_types[0],
5448 i.types[1],
5449 operand_types[1])))
5450 {
5451 /* Check if other direction is valid ... */
5452 if (!t->opcode_modifier.d)
5453 continue;
5454
5455 check_reverse:
5456 /* Try reversing direction of operands. */
5457 overlap0 = operand_type_and (i.types[0], operand_types[1]);
5458 overlap1 = operand_type_and (i.types[1], operand_types[0]);
5459 if (!operand_type_match (overlap0, i.types[0])
5460 || !operand_type_match (overlap1, i.types[1])
5461 || (check_register
5462 && !operand_type_register_match (i.types[0],
5463 operand_types[1],
5464 i.types[1],
5465 operand_types[0])))
5466 {
5467 /* Does not match either direction. */
5468 continue;
5469 }
5470 /* found_reverse_match holds which of D or FloatR
5471 we've found. */
5472 if (!t->opcode_modifier.d)
5473 found_reverse_match = 0;
5474 else if (operand_types[0].bitfield.tbyte)
5475 found_reverse_match = Opcode_FloatD;
5476 else
5477 found_reverse_match = Opcode_D;
5478 if (t->opcode_modifier.floatr)
5479 found_reverse_match |= Opcode_FloatR;
5480 }
5481 else
5482 {
5483 /* Found a forward 2 operand match here. */
5484 switch (t->operands)
5485 {
5486 case 5:
5487 overlap4 = operand_type_and (i.types[4],
5488 operand_types[4]);
5489 /* Fall through. */
5490 case 4:
5491 overlap3 = operand_type_and (i.types[3],
5492 operand_types[3]);
5493 /* Fall through. */
5494 case 3:
5495 overlap2 = operand_type_and (i.types[2],
5496 operand_types[2]);
5497 break;
5498 }
5499
5500 switch (t->operands)
5501 {
5502 case 5:
5503 if (!operand_type_match (overlap4, i.types[4])
5504 || !operand_type_register_match (i.types[3],
5505 operand_types[3],
5506 i.types[4],
5507 operand_types[4]))
5508 continue;
5509 /* Fall through. */
5510 case 4:
5511 if (!operand_type_match (overlap3, i.types[3])
5512 || (check_register
5513 && !operand_type_register_match (i.types[2],
5514 operand_types[2],
5515 i.types[3],
5516 operand_types[3])))
5517 continue;
5518 /* Fall through. */
5519 case 3:
5520 /* Here we make use of the fact that there are no
5521 reverse match 3 operand instructions. */
5522 if (!operand_type_match (overlap2, i.types[2])
5523 || (check_register
5524 && (!operand_type_register_match (i.types[0],
5525 operand_types[0],
5526 i.types[2],
5527 operand_types[2])
5528 || !operand_type_register_match (i.types[1],
5529 operand_types[1],
5530 i.types[2],
5531 operand_types[2]))))
5532 continue;
5533 break;
5534 }
5535 }
5536 /* Found either forward/reverse 2, 3 or 4 operand match here:
5537 slip through to break. */
5538 }
5539 if (!found_cpu_match)
5540 {
5541 found_reverse_match = 0;
5542 continue;
5543 }
5544
5545 /* Check if vector and VEX operands are valid. */
5546 if (check_VecOperands (t) || VEX_check_operands (t))
5547 {
5548 specific_error = i.error;
5549 continue;
5550 }
5551
5552 /* We've found a match; break out of loop. */
5553 break;
5554 }
5555
5556 if (t == current_templates->end)
5557 {
5558 /* We found no match. */
5559 const char *err_msg;
5560 switch (specific_error ? specific_error : i.error)
5561 {
5562 default:
5563 abort ();
5564 case operand_size_mismatch:
5565 err_msg = _("operand size mismatch");
5566 break;
5567 case operand_type_mismatch:
5568 err_msg = _("operand type mismatch");
5569 break;
5570 case register_type_mismatch:
5571 err_msg = _("register type mismatch");
5572 break;
5573 case number_of_operands_mismatch:
5574 err_msg = _("number of operands mismatch");
5575 break;
5576 case invalid_instruction_suffix:
5577 err_msg = _("invalid instruction suffix");
5578 break;
5579 case bad_imm4:
5580 err_msg = _("constant doesn't fit in 4 bits");
5581 break;
5582 case unsupported_with_intel_mnemonic:
5583 err_msg = _("unsupported with Intel mnemonic");
5584 break;
5585 case unsupported_syntax:
5586 err_msg = _("unsupported syntax");
5587 break;
5588 case unsupported:
5589 as_bad (_("unsupported instruction `%s'"),
5590 current_templates->start->name);
5591 return NULL;
5592 case invalid_vsib_address:
5593 err_msg = _("invalid VSIB address");
5594 break;
5595 case invalid_vector_register_set:
5596 err_msg = _("mask, index, and destination registers must be distinct");
5597 break;
5598 case unsupported_vector_index_register:
5599 err_msg = _("unsupported vector index register");
5600 break;
5601 case unsupported_broadcast:
5602 err_msg = _("unsupported broadcast");
5603 break;
5604 case broadcast_not_on_src_operand:
5605 err_msg = _("broadcast not on source memory operand");
5606 break;
5607 case broadcast_needed:
5608 err_msg = _("broadcast is needed for operand of such type");
5609 break;
5610 case unsupported_masking:
5611 err_msg = _("unsupported masking");
5612 break;
5613 case mask_not_on_destination:
5614 err_msg = _("mask not on destination operand");
5615 break;
5616 case no_default_mask:
5617 err_msg = _("default mask isn't allowed");
5618 break;
5619 case unsupported_rc_sae:
5620 err_msg = _("unsupported static rounding/sae");
5621 break;
5622 case rc_sae_operand_not_last_imm:
5623 if (intel_syntax)
5624 err_msg = _("RC/SAE operand must precede immediate operands");
5625 else
5626 err_msg = _("RC/SAE operand must follow immediate operands");
5627 break;
5628 case invalid_register_operand:
5629 err_msg = _("invalid register operand");
5630 break;
5631 }
5632 as_bad (_("%s for `%s'"), err_msg,
5633 current_templates->start->name);
5634 return NULL;
5635 }
5636
5637 if (!quiet_warnings)
5638 {
5639 if (!intel_syntax
5640 && (i.types[0].bitfield.jumpabsolute
5641 != operand_types[0].bitfield.jumpabsolute))
5642 {
5643 as_warn (_("indirect %s without `*'"), t->name);
5644 }
5645
5646 if (t->opcode_modifier.isprefix
5647 && t->opcode_modifier.ignoresize)
5648 {
5649 /* Warn them that a data or address size prefix doesn't
5650 affect assembly of the next line of code. */
5651 as_warn (_("stand-alone `%s' prefix"), t->name);
5652 }
5653 }
5654
5655 /* Copy the template we found. */
5656 i.tm = *t;
5657
5658 if (addr_prefix_disp != -1)
5659 i.tm.operand_types[addr_prefix_disp]
5660 = operand_types[addr_prefix_disp];
5661
5662 if (found_reverse_match)
5663 {
5664 /* If we found a reverse match we must alter the opcode
5665 direction bit. found_reverse_match holds bits to change
5666 (different for int & float insns). */
5667
5668 i.tm.base_opcode ^= found_reverse_match;
5669
5670 i.tm.operand_types[0] = operand_types[1];
5671 i.tm.operand_types[1] = operand_types[0];
5672 }
5673
5674 return t;
5675 }
5676
5677 static int
5678 check_string (void)
5679 {
5680 int mem_op = operand_type_check (i.types[0], anymem) ? 0 : 1;
5681 if (i.tm.operand_types[mem_op].bitfield.esseg)
5682 {
5683 if (i.seg[0] != NULL && i.seg[0] != &es)
5684 {
5685 as_bad (_("`%s' operand %d must use `%ses' segment"),
5686 i.tm.name,
5687 mem_op + 1,
5688 register_prefix);
5689 return 0;
5690 }
5691 /* There's only ever one segment override allowed per instruction.
5692 This instruction possibly has a legal segment override on the
5693 second operand, so copy the segment to where non-string
5694 instructions store it, allowing common code. */
5695 i.seg[0] = i.seg[1];
5696 }
5697 else if (i.tm.operand_types[mem_op + 1].bitfield.esseg)
5698 {
5699 if (i.seg[1] != NULL && i.seg[1] != &es)
5700 {
5701 as_bad (_("`%s' operand %d must use `%ses' segment"),
5702 i.tm.name,
5703 mem_op + 2,
5704 register_prefix);
5705 return 0;
5706 }
5707 }
5708 return 1;
5709 }
5710
5711 static int
5712 process_suffix (void)
5713 {
5714 /* If matched instruction specifies an explicit instruction mnemonic
5715 suffix, use it. */
5716 if (i.tm.opcode_modifier.size16)
5717 i.suffix = WORD_MNEM_SUFFIX;
5718 else if (i.tm.opcode_modifier.size32)
5719 i.suffix = LONG_MNEM_SUFFIX;
5720 else if (i.tm.opcode_modifier.size64)
5721 i.suffix = QWORD_MNEM_SUFFIX;
5722 else if (i.reg_operands)
5723 {
5724 /* If there's no instruction mnemonic suffix we try to invent one
5725 based on register operands. */
5726 if (!i.suffix)
5727 {
5728 /* We take i.suffix from the last register operand specified,
5729 Destination register type is more significant than source
5730 register type. crc32 in SSE4.2 prefers source register
5731 type. */
5732 if (i.tm.base_opcode == 0xf20f38f1)
5733 {
5734 if (i.types[0].bitfield.reg && i.types[0].bitfield.word)
5735 i.suffix = WORD_MNEM_SUFFIX;
5736 else if (i.types[0].bitfield.reg && i.types[0].bitfield.dword)
5737 i.suffix = LONG_MNEM_SUFFIX;
5738 else if (i.types[0].bitfield.reg && i.types[0].bitfield.qword)
5739 i.suffix = QWORD_MNEM_SUFFIX;
5740 }
5741 else if (i.tm.base_opcode == 0xf20f38f0)
5742 {
5743 if (i.types[0].bitfield.reg && i.types[0].bitfield.byte)
5744 i.suffix = BYTE_MNEM_SUFFIX;
5745 }
5746
5747 if (!i.suffix)
5748 {
5749 int op;
5750
5751 if (i.tm.base_opcode == 0xf20f38f1
5752 || i.tm.base_opcode == 0xf20f38f0)
5753 {
5754 /* We have to know the operand size for crc32. */
5755 as_bad (_("ambiguous memory operand size for `%s`"),
5756 i.tm.name);
5757 return 0;
5758 }
5759
5760 for (op = i.operands; --op >= 0;)
5761 if (!i.tm.operand_types[op].bitfield.inoutportreg
5762 && !i.tm.operand_types[op].bitfield.shiftcount)
5763 {
5764 if (!i.types[op].bitfield.reg)
5765 continue;
5766 if (i.types[op].bitfield.byte)
5767 i.suffix = BYTE_MNEM_SUFFIX;
5768 else if (i.types[op].bitfield.word)
5769 i.suffix = WORD_MNEM_SUFFIX;
5770 else if (i.types[op].bitfield.dword)
5771 i.suffix = LONG_MNEM_SUFFIX;
5772 else if (i.types[op].bitfield.qword)
5773 i.suffix = QWORD_MNEM_SUFFIX;
5774 else
5775 continue;
5776 break;
5777 }
5778 }
5779 }
5780 else if (i.suffix == BYTE_MNEM_SUFFIX)
5781 {
5782 if (intel_syntax
5783 && i.tm.opcode_modifier.ignoresize
5784 && i.tm.opcode_modifier.no_bsuf)
5785 i.suffix = 0;
5786 else if (!check_byte_reg ())
5787 return 0;
5788 }
5789 else if (i.suffix == LONG_MNEM_SUFFIX)
5790 {
5791 if (intel_syntax
5792 && i.tm.opcode_modifier.ignoresize
5793 && i.tm.opcode_modifier.no_lsuf)
5794 i.suffix = 0;
5795 else if (!check_long_reg ())
5796 return 0;
5797 }
5798 else if (i.suffix == QWORD_MNEM_SUFFIX)
5799 {
5800 if (intel_syntax
5801 && i.tm.opcode_modifier.ignoresize
5802 && i.tm.opcode_modifier.no_qsuf)
5803 i.suffix = 0;
5804 else if (!check_qword_reg ())
5805 return 0;
5806 }
5807 else if (i.suffix == WORD_MNEM_SUFFIX)
5808 {
5809 if (intel_syntax
5810 && i.tm.opcode_modifier.ignoresize
5811 && i.tm.opcode_modifier.no_wsuf)
5812 i.suffix = 0;
5813 else if (!check_word_reg ())
5814 return 0;
5815 }
5816 else if (intel_syntax && i.tm.opcode_modifier.ignoresize)
5817 /* Do nothing if the instruction is going to ignore the prefix. */
5818 ;
5819 else
5820 abort ();
5821 }
5822 else if (i.tm.opcode_modifier.defaultsize
5823 && !i.suffix
5824 /* exclude fldenv/frstor/fsave/fstenv */
5825 && i.tm.opcode_modifier.no_ssuf)
5826 {
5827 i.suffix = stackop_size;
5828 }
5829 else if (intel_syntax
5830 && !i.suffix
5831 && (i.tm.operand_types[0].bitfield.jumpabsolute
5832 || i.tm.opcode_modifier.jumpbyte
5833 || i.tm.opcode_modifier.jumpintersegment
5834 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
5835 && i.tm.extension_opcode <= 3)))
5836 {
5837 switch (flag_code)
5838 {
5839 case CODE_64BIT:
5840 if (!i.tm.opcode_modifier.no_qsuf)
5841 {
5842 i.suffix = QWORD_MNEM_SUFFIX;
5843 break;
5844 }
5845 /* Fall through. */
5846 case CODE_32BIT:
5847 if (!i.tm.opcode_modifier.no_lsuf)
5848 i.suffix = LONG_MNEM_SUFFIX;
5849 break;
5850 case CODE_16BIT:
5851 if (!i.tm.opcode_modifier.no_wsuf)
5852 i.suffix = WORD_MNEM_SUFFIX;
5853 break;
5854 }
5855 }
5856
5857 if (!i.suffix)
5858 {
5859 if (!intel_syntax)
5860 {
5861 if (i.tm.opcode_modifier.w)
5862 {
5863 as_bad (_("no instruction mnemonic suffix given and "
5864 "no register operands; can't size instruction"));
5865 return 0;
5866 }
5867 }
5868 else
5869 {
5870 unsigned int suffixes;
5871
5872 suffixes = !i.tm.opcode_modifier.no_bsuf;
5873 if (!i.tm.opcode_modifier.no_wsuf)
5874 suffixes |= 1 << 1;
5875 if (!i.tm.opcode_modifier.no_lsuf)
5876 suffixes |= 1 << 2;
5877 if (!i.tm.opcode_modifier.no_ldsuf)
5878 suffixes |= 1 << 3;
5879 if (!i.tm.opcode_modifier.no_ssuf)
5880 suffixes |= 1 << 4;
5881 if (flag_code == CODE_64BIT && !i.tm.opcode_modifier.no_qsuf)
5882 suffixes |= 1 << 5;
5883
5884 /* There are more than suffix matches. */
5885 if (i.tm.opcode_modifier.w
5886 || ((suffixes & (suffixes - 1))
5887 && !i.tm.opcode_modifier.defaultsize
5888 && !i.tm.opcode_modifier.ignoresize))
5889 {
5890 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
5891 return 0;
5892 }
5893 }
5894 }
5895
5896 /* Change the opcode based on the operand size given by i.suffix. */
5897 switch (i.suffix)
5898 {
5899 /* Size floating point instruction. */
5900 case LONG_MNEM_SUFFIX:
5901 if (i.tm.opcode_modifier.floatmf)
5902 {
5903 i.tm.base_opcode ^= 4;
5904 break;
5905 }
5906 /* fall through */
5907 case WORD_MNEM_SUFFIX:
5908 case QWORD_MNEM_SUFFIX:
5909 /* It's not a byte, select word/dword operation. */
5910 if (i.tm.opcode_modifier.w)
5911 {
5912 if (i.tm.opcode_modifier.shortform)
5913 i.tm.base_opcode |= 8;
5914 else
5915 i.tm.base_opcode |= 1;
5916 }
5917 /* fall through */
5918 case SHORT_MNEM_SUFFIX:
5919 /* Now select between word & dword operations via the operand
5920 size prefix, except for instructions that will ignore this
5921 prefix anyway. */
5922 if (i.tm.opcode_modifier.addrprefixop0)
5923 {
5924 /* The address size override prefix changes the size of the
5925 first operand. */
5926 if ((flag_code == CODE_32BIT
5927 && i.op->regs[0].reg_type.bitfield.word)
5928 || (flag_code != CODE_32BIT
5929 && i.op->regs[0].reg_type.bitfield.dword))
5930 if (!add_prefix (ADDR_PREFIX_OPCODE))
5931 return 0;
5932 }
5933 else if (i.suffix != QWORD_MNEM_SUFFIX
5934 && !i.tm.opcode_modifier.ignoresize
5935 && !i.tm.opcode_modifier.floatmf
5936 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
5937 || (flag_code == CODE_64BIT
5938 && i.tm.opcode_modifier.jumpbyte)))
5939 {
5940 unsigned int prefix = DATA_PREFIX_OPCODE;
5941
5942 if (i.tm.opcode_modifier.jumpbyte) /* jcxz, loop */
5943 prefix = ADDR_PREFIX_OPCODE;
5944
5945 if (!add_prefix (prefix))
5946 return 0;
5947 }
5948
5949 /* Set mode64 for an operand. */
5950 if (i.suffix == QWORD_MNEM_SUFFIX
5951 && flag_code == CODE_64BIT
5952 && !i.tm.opcode_modifier.norex64
5953 /* Special case for xchg %rax,%rax. It is NOP and doesn't
5954 need rex64. */
5955 && ! (i.operands == 2
5956 && i.tm.base_opcode == 0x90
5957 && i.tm.extension_opcode == None
5958 && operand_type_equal (&i.types [0], &acc64)
5959 && operand_type_equal (&i.types [1], &acc64)))
5960 i.rex |= REX_W;
5961
5962 break;
5963 }
5964
5965 return 1;
5966 }
5967
5968 static int
5969 check_byte_reg (void)
5970 {
5971 int op;
5972
5973 for (op = i.operands; --op >= 0;)
5974 {
5975 /* Skip non-register operands. */
5976 if (!i.types[op].bitfield.reg)
5977 continue;
5978
5979 /* If this is an eight bit register, it's OK. If it's the 16 or
5980 32 bit version of an eight bit register, we will just use the
5981 low portion, and that's OK too. */
5982 if (i.types[op].bitfield.byte)
5983 continue;
5984
5985 /* I/O port address operands are OK too. */
5986 if (i.tm.operand_types[op].bitfield.inoutportreg)
5987 continue;
5988
5989 /* crc32 doesn't generate this warning. */
5990 if (i.tm.base_opcode == 0xf20f38f0)
5991 continue;
5992
5993 if ((i.types[op].bitfield.word
5994 || i.types[op].bitfield.dword
5995 || i.types[op].bitfield.qword)
5996 && i.op[op].regs->reg_num < 4
5997 /* Prohibit these changes in 64bit mode, since the lowering
5998 would be more complicated. */
5999 && flag_code != CODE_64BIT)
6000 {
6001 #if REGISTER_WARNINGS
6002 if (!quiet_warnings)
6003 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6004 register_prefix,
6005 (i.op[op].regs + (i.types[op].bitfield.word
6006 ? REGNAM_AL - REGNAM_AX
6007 : REGNAM_AL - REGNAM_EAX))->reg_name,
6008 register_prefix,
6009 i.op[op].regs->reg_name,
6010 i.suffix);
6011 #endif
6012 continue;
6013 }
6014 /* Any other register is bad. */
6015 if (i.types[op].bitfield.reg
6016 || i.types[op].bitfield.regmmx
6017 || i.types[op].bitfield.regsimd
6018 || i.types[op].bitfield.sreg2
6019 || i.types[op].bitfield.sreg3
6020 || i.types[op].bitfield.control
6021 || i.types[op].bitfield.debug
6022 || i.types[op].bitfield.test)
6023 {
6024 as_bad (_("`%s%s' not allowed with `%s%c'"),
6025 register_prefix,
6026 i.op[op].regs->reg_name,
6027 i.tm.name,
6028 i.suffix);
6029 return 0;
6030 }
6031 }
6032 return 1;
6033 }
6034
6035 static int
6036 check_long_reg (void)
6037 {
6038 int op;
6039
6040 for (op = i.operands; --op >= 0;)
6041 /* Skip non-register operands. */
6042 if (!i.types[op].bitfield.reg)
6043 continue;
6044 /* Reject eight bit registers, except where the template requires
6045 them. (eg. movzb) */
6046 else if (i.types[op].bitfield.byte
6047 && (i.tm.operand_types[op].bitfield.reg
6048 || i.tm.operand_types[op].bitfield.acc)
6049 && (i.tm.operand_types[op].bitfield.word
6050 || i.tm.operand_types[op].bitfield.dword))
6051 {
6052 as_bad (_("`%s%s' not allowed with `%s%c'"),
6053 register_prefix,
6054 i.op[op].regs->reg_name,
6055 i.tm.name,
6056 i.suffix);
6057 return 0;
6058 }
6059 /* Warn if the e prefix on a general reg is missing. */
6060 else if ((!quiet_warnings || flag_code == CODE_64BIT)
6061 && i.types[op].bitfield.word
6062 && (i.tm.operand_types[op].bitfield.reg
6063 || i.tm.operand_types[op].bitfield.acc)
6064 && i.tm.operand_types[op].bitfield.dword)
6065 {
6066 /* Prohibit these changes in the 64bit mode, since the
6067 lowering is more complicated. */
6068 if (flag_code == CODE_64BIT)
6069 {
6070 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6071 register_prefix, i.op[op].regs->reg_name,
6072 i.suffix);
6073 return 0;
6074 }
6075 #if REGISTER_WARNINGS
6076 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6077 register_prefix,
6078 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
6079 register_prefix, i.op[op].regs->reg_name, i.suffix);
6080 #endif
6081 }
6082 /* Warn if the r prefix on a general reg is present. */
6083 else if (i.types[op].bitfield.qword
6084 && (i.tm.operand_types[op].bitfield.reg
6085 || i.tm.operand_types[op].bitfield.acc)
6086 && i.tm.operand_types[op].bitfield.dword)
6087 {
6088 if (intel_syntax
6089 && i.tm.opcode_modifier.toqword
6090 && !i.types[0].bitfield.regsimd)
6091 {
6092 /* Convert to QWORD. We want REX byte. */
6093 i.suffix = QWORD_MNEM_SUFFIX;
6094 }
6095 else
6096 {
6097 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6098 register_prefix, i.op[op].regs->reg_name,
6099 i.suffix);
6100 return 0;
6101 }
6102 }
6103 return 1;
6104 }
6105
6106 static int
6107 check_qword_reg (void)
6108 {
6109 int op;
6110
6111 for (op = i.operands; --op >= 0; )
6112 /* Skip non-register operands. */
6113 if (!i.types[op].bitfield.reg)
6114 continue;
6115 /* Reject eight bit registers, except where the template requires
6116 them. (eg. movzb) */
6117 else if (i.types[op].bitfield.byte
6118 && (i.tm.operand_types[op].bitfield.reg
6119 || i.tm.operand_types[op].bitfield.acc)
6120 && (i.tm.operand_types[op].bitfield.word
6121 || i.tm.operand_types[op].bitfield.dword))
6122 {
6123 as_bad (_("`%s%s' not allowed with `%s%c'"),
6124 register_prefix,
6125 i.op[op].regs->reg_name,
6126 i.tm.name,
6127 i.suffix);
6128 return 0;
6129 }
6130 /* Warn if the r prefix on a general reg is missing. */
6131 else if ((i.types[op].bitfield.word
6132 || i.types[op].bitfield.dword)
6133 && (i.tm.operand_types[op].bitfield.reg
6134 || i.tm.operand_types[op].bitfield.acc)
6135 && i.tm.operand_types[op].bitfield.qword)
6136 {
6137 /* Prohibit these changes in the 64bit mode, since the
6138 lowering is more complicated. */
6139 if (intel_syntax
6140 && i.tm.opcode_modifier.todword
6141 && !i.types[0].bitfield.regsimd)
6142 {
6143 /* Convert to DWORD. We don't want REX byte. */
6144 i.suffix = LONG_MNEM_SUFFIX;
6145 }
6146 else
6147 {
6148 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6149 register_prefix, i.op[op].regs->reg_name,
6150 i.suffix);
6151 return 0;
6152 }
6153 }
6154 return 1;
6155 }
6156
6157 static int
6158 check_word_reg (void)
6159 {
6160 int op;
6161 for (op = i.operands; --op >= 0;)
6162 /* Skip non-register operands. */
6163 if (!i.types[op].bitfield.reg)
6164 continue;
6165 /* Reject eight bit registers, except where the template requires
6166 them. (eg. movzb) */
6167 else if (i.types[op].bitfield.byte
6168 && (i.tm.operand_types[op].bitfield.reg
6169 || i.tm.operand_types[op].bitfield.acc)
6170 && (i.tm.operand_types[op].bitfield.word
6171 || i.tm.operand_types[op].bitfield.dword))
6172 {
6173 as_bad (_("`%s%s' not allowed with `%s%c'"),
6174 register_prefix,
6175 i.op[op].regs->reg_name,
6176 i.tm.name,
6177 i.suffix);
6178 return 0;
6179 }
6180 /* Warn if the e or r prefix on a general reg is present. */
6181 else if ((!quiet_warnings || flag_code == CODE_64BIT)
6182 && (i.types[op].bitfield.dword
6183 || i.types[op].bitfield.qword)
6184 && (i.tm.operand_types[op].bitfield.reg
6185 || i.tm.operand_types[op].bitfield.acc)
6186 && i.tm.operand_types[op].bitfield.word)
6187 {
6188 /* Prohibit these changes in the 64bit mode, since the
6189 lowering is more complicated. */
6190 if (flag_code == CODE_64BIT)
6191 {
6192 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6193 register_prefix, i.op[op].regs->reg_name,
6194 i.suffix);
6195 return 0;
6196 }
6197 #if REGISTER_WARNINGS
6198 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6199 register_prefix,
6200 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
6201 register_prefix, i.op[op].regs->reg_name, i.suffix);
6202 #endif
6203 }
6204 return 1;
6205 }
6206
6207 static int
6208 update_imm (unsigned int j)
6209 {
6210 i386_operand_type overlap = i.types[j];
6211 if ((overlap.bitfield.imm8
6212 || overlap.bitfield.imm8s
6213 || overlap.bitfield.imm16
6214 || overlap.bitfield.imm32
6215 || overlap.bitfield.imm32s
6216 || overlap.bitfield.imm64)
6217 && !operand_type_equal (&overlap, &imm8)
6218 && !operand_type_equal (&overlap, &imm8s)
6219 && !operand_type_equal (&overlap, &imm16)
6220 && !operand_type_equal (&overlap, &imm32)
6221 && !operand_type_equal (&overlap, &imm32s)
6222 && !operand_type_equal (&overlap, &imm64))
6223 {
6224 if (i.suffix)
6225 {
6226 i386_operand_type temp;
6227
6228 operand_type_set (&temp, 0);
6229 if (i.suffix == BYTE_MNEM_SUFFIX)
6230 {
6231 temp.bitfield.imm8 = overlap.bitfield.imm8;
6232 temp.bitfield.imm8s = overlap.bitfield.imm8s;
6233 }
6234 else if (i.suffix == WORD_MNEM_SUFFIX)
6235 temp.bitfield.imm16 = overlap.bitfield.imm16;
6236 else if (i.suffix == QWORD_MNEM_SUFFIX)
6237 {
6238 temp.bitfield.imm64 = overlap.bitfield.imm64;
6239 temp.bitfield.imm32s = overlap.bitfield.imm32s;
6240 }
6241 else
6242 temp.bitfield.imm32 = overlap.bitfield.imm32;
6243 overlap = temp;
6244 }
6245 else if (operand_type_equal (&overlap, &imm16_32_32s)
6246 || operand_type_equal (&overlap, &imm16_32)
6247 || operand_type_equal (&overlap, &imm16_32s))
6248 {
6249 if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
6250 overlap = imm16;
6251 else
6252 overlap = imm32s;
6253 }
6254 if (!operand_type_equal (&overlap, &imm8)
6255 && !operand_type_equal (&overlap, &imm8s)
6256 && !operand_type_equal (&overlap, &imm16)
6257 && !operand_type_equal (&overlap, &imm32)
6258 && !operand_type_equal (&overlap, &imm32s)
6259 && !operand_type_equal (&overlap, &imm64))
6260 {
6261 as_bad (_("no instruction mnemonic suffix given; "
6262 "can't determine immediate size"));
6263 return 0;
6264 }
6265 }
6266 i.types[j] = overlap;
6267
6268 return 1;
6269 }
6270
6271 static int
6272 finalize_imm (void)
6273 {
6274 unsigned int j, n;
6275
6276 /* Update the first 2 immediate operands. */
6277 n = i.operands > 2 ? 2 : i.operands;
6278 if (n)
6279 {
6280 for (j = 0; j < n; j++)
6281 if (update_imm (j) == 0)
6282 return 0;
6283
6284 /* The 3rd operand can't be immediate operand. */
6285 gas_assert (operand_type_check (i.types[2], imm) == 0);
6286 }
6287
6288 return 1;
6289 }
6290
6291 static int
6292 process_operands (void)
6293 {
6294 /* Default segment register this instruction will use for memory
6295 accesses. 0 means unknown. This is only for optimizing out
6296 unnecessary segment overrides. */
6297 const seg_entry *default_seg = 0;
6298
6299 if (i.tm.opcode_modifier.sse2avx && i.tm.opcode_modifier.vexvvvv)
6300 {
6301 unsigned int dupl = i.operands;
6302 unsigned int dest = dupl - 1;
6303 unsigned int j;
6304
6305 /* The destination must be an xmm register. */
6306 gas_assert (i.reg_operands
6307 && MAX_OPERANDS > dupl
6308 && operand_type_equal (&i.types[dest], &regxmm));
6309
6310 if (i.tm.operand_types[0].bitfield.acc
6311 && i.tm.operand_types[0].bitfield.xmmword)
6312 {
6313 if (i.tm.opcode_modifier.vexsources == VEX3SOURCES)
6314 {
6315 /* Keep xmm0 for instructions with VEX prefix and 3
6316 sources. */
6317 i.tm.operand_types[0].bitfield.acc = 0;
6318 i.tm.operand_types[0].bitfield.regsimd = 1;
6319 goto duplicate;
6320 }
6321 else
6322 {
6323 /* We remove the first xmm0 and keep the number of
6324 operands unchanged, which in fact duplicates the
6325 destination. */
6326 for (j = 1; j < i.operands; j++)
6327 {
6328 i.op[j - 1] = i.op[j];
6329 i.types[j - 1] = i.types[j];
6330 i.tm.operand_types[j - 1] = i.tm.operand_types[j];
6331 }
6332 }
6333 }
6334 else if (i.tm.opcode_modifier.implicit1stxmm0)
6335 {
6336 gas_assert ((MAX_OPERANDS - 1) > dupl
6337 && (i.tm.opcode_modifier.vexsources
6338 == VEX3SOURCES));
6339
6340 /* Add the implicit xmm0 for instructions with VEX prefix
6341 and 3 sources. */
6342 for (j = i.operands; j > 0; j--)
6343 {
6344 i.op[j] = i.op[j - 1];
6345 i.types[j] = i.types[j - 1];
6346 i.tm.operand_types[j] = i.tm.operand_types[j - 1];
6347 }
6348 i.op[0].regs
6349 = (const reg_entry *) hash_find (reg_hash, "xmm0");
6350 i.types[0] = regxmm;
6351 i.tm.operand_types[0] = regxmm;
6352
6353 i.operands += 2;
6354 i.reg_operands += 2;
6355 i.tm.operands += 2;
6356
6357 dupl++;
6358 dest++;
6359 i.op[dupl] = i.op[dest];
6360 i.types[dupl] = i.types[dest];
6361 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
6362 }
6363 else
6364 {
6365 duplicate:
6366 i.operands++;
6367 i.reg_operands++;
6368 i.tm.operands++;
6369
6370 i.op[dupl] = i.op[dest];
6371 i.types[dupl] = i.types[dest];
6372 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
6373 }
6374
6375 if (i.tm.opcode_modifier.immext)
6376 process_immext ();
6377 }
6378 else if (i.tm.operand_types[0].bitfield.acc
6379 && i.tm.operand_types[0].bitfield.xmmword)
6380 {
6381 unsigned int j;
6382
6383 for (j = 1; j < i.operands; j++)
6384 {
6385 i.op[j - 1] = i.op[j];
6386 i.types[j - 1] = i.types[j];
6387
6388 /* We need to adjust fields in i.tm since they are used by
6389 build_modrm_byte. */
6390 i.tm.operand_types [j - 1] = i.tm.operand_types [j];
6391 }
6392
6393 i.operands--;
6394 i.reg_operands--;
6395 i.tm.operands--;
6396 }
6397 else if (i.tm.opcode_modifier.implicitquadgroup)
6398 {
6399 unsigned int regnum, first_reg_in_group, last_reg_in_group;
6400
6401 /* The second operand must be {x,y,z}mmN, where N is a multiple of 4. */
6402 gas_assert (i.operands >= 2 && i.types[1].bitfield.regsimd);
6403 regnum = register_number (i.op[1].regs);
6404 first_reg_in_group = regnum & ~3;
6405 last_reg_in_group = first_reg_in_group + 3;
6406 if (regnum != first_reg_in_group)
6407 as_warn (_("source register `%s%s' implicitly denotes"
6408 " `%s%.3s%u' to `%s%.3s%u' source group in `%s'"),
6409 register_prefix, i.op[1].regs->reg_name,
6410 register_prefix, i.op[1].regs->reg_name, first_reg_in_group,
6411 register_prefix, i.op[1].regs->reg_name, last_reg_in_group,
6412 i.tm.name);
6413 }
6414 else if (i.tm.opcode_modifier.regkludge)
6415 {
6416 /* The imul $imm, %reg instruction is converted into
6417 imul $imm, %reg, %reg, and the clr %reg instruction
6418 is converted into xor %reg, %reg. */
6419
6420 unsigned int first_reg_op;
6421
6422 if (operand_type_check (i.types[0], reg))
6423 first_reg_op = 0;
6424 else
6425 first_reg_op = 1;
6426 /* Pretend we saw the extra register operand. */
6427 gas_assert (i.reg_operands == 1
6428 && i.op[first_reg_op + 1].regs == 0);
6429 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
6430 i.types[first_reg_op + 1] = i.types[first_reg_op];
6431 i.operands++;
6432 i.reg_operands++;
6433 }
6434
6435 if (i.tm.opcode_modifier.shortform)
6436 {
6437 if (i.types[0].bitfield.sreg2
6438 || i.types[0].bitfield.sreg3)
6439 {
6440 if (i.tm.base_opcode == POP_SEG_SHORT
6441 && i.op[0].regs->reg_num == 1)
6442 {
6443 as_bad (_("you can't `pop %scs'"), register_prefix);
6444 return 0;
6445 }
6446 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
6447 if ((i.op[0].regs->reg_flags & RegRex) != 0)
6448 i.rex |= REX_B;
6449 }
6450 else
6451 {
6452 /* The register or float register operand is in operand
6453 0 or 1. */
6454 unsigned int op;
6455
6456 if ((i.types[0].bitfield.reg && i.types[0].bitfield.tbyte)
6457 || operand_type_check (i.types[0], reg))
6458 op = 0;
6459 else
6460 op = 1;
6461 /* Register goes in low 3 bits of opcode. */
6462 i.tm.base_opcode |= i.op[op].regs->reg_num;
6463 if ((i.op[op].regs->reg_flags & RegRex) != 0)
6464 i.rex |= REX_B;
6465 if (!quiet_warnings && i.tm.opcode_modifier.ugh)
6466 {
6467 /* Warn about some common errors, but press on regardless.
6468 The first case can be generated by gcc (<= 2.8.1). */
6469 if (i.operands == 2)
6470 {
6471 /* Reversed arguments on faddp, fsubp, etc. */
6472 as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name,
6473 register_prefix, i.op[!intel_syntax].regs->reg_name,
6474 register_prefix, i.op[intel_syntax].regs->reg_name);
6475 }
6476 else
6477 {
6478 /* Extraneous `l' suffix on fp insn. */
6479 as_warn (_("translating to `%s %s%s'"), i.tm.name,
6480 register_prefix, i.op[0].regs->reg_name);
6481 }
6482 }
6483 }
6484 }
6485 else if (i.tm.opcode_modifier.modrm)
6486 {
6487 /* The opcode is completed (modulo i.tm.extension_opcode which
6488 must be put into the modrm byte). Now, we make the modrm and
6489 index base bytes based on all the info we've collected. */
6490
6491 default_seg = build_modrm_byte ();
6492 }
6493 else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32)
6494 {
6495 default_seg = &ds;
6496 }
6497 else if (i.tm.opcode_modifier.isstring)
6498 {
6499 /* For the string instructions that allow a segment override
6500 on one of their operands, the default segment is ds. */
6501 default_seg = &ds;
6502 }
6503
6504 if (i.tm.base_opcode == 0x8d /* lea */
6505 && i.seg[0]
6506 && !quiet_warnings)
6507 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
6508
6509 /* If a segment was explicitly specified, and the specified segment
6510 is not the default, use an opcode prefix to select it. If we
6511 never figured out what the default segment is, then default_seg
6512 will be zero at this point, and the specified segment prefix will
6513 always be used. */
6514 if ((i.seg[0]) && (i.seg[0] != default_seg))
6515 {
6516 if (!add_prefix (i.seg[0]->seg_prefix))
6517 return 0;
6518 }
6519 return 1;
6520 }
6521
6522 static const seg_entry *
6523 build_modrm_byte (void)
6524 {
6525 const seg_entry *default_seg = 0;
6526 unsigned int source, dest;
6527 int vex_3_sources;
6528
6529 /* The first operand of instructions with VEX prefix and 3 sources
6530 must be VEX_Imm4. */
6531 vex_3_sources = i.tm.opcode_modifier.vexsources == VEX3SOURCES;
6532 if (vex_3_sources)
6533 {
6534 unsigned int nds, reg_slot;
6535 expressionS *exp;
6536
6537 if (i.tm.opcode_modifier.veximmext
6538 && i.tm.opcode_modifier.immext)
6539 {
6540 dest = i.operands - 2;
6541 gas_assert (dest == 3);
6542 }
6543 else
6544 dest = i.operands - 1;
6545 nds = dest - 1;
6546
6547 /* There are 2 kinds of instructions:
6548 1. 5 operands: 4 register operands or 3 register operands
6549 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
6550 VexW0 or VexW1. The destination must be either XMM, YMM or
6551 ZMM register.
6552 2. 4 operands: 4 register operands or 3 register operands
6553 plus 1 memory operand, VexXDS, and VexImmExt */
6554 gas_assert ((i.reg_operands == 4
6555 || (i.reg_operands == 3 && i.mem_operands == 1))
6556 && i.tm.opcode_modifier.vexvvvv == VEXXDS
6557 && (i.tm.opcode_modifier.veximmext
6558 || (i.imm_operands == 1
6559 && i.types[0].bitfield.vec_imm4
6560 && (i.tm.opcode_modifier.vexw == VEXW0
6561 || i.tm.opcode_modifier.vexw == VEXW1)
6562 && i.tm.operand_types[dest].bitfield.regsimd)));
6563
6564 if (i.imm_operands == 0)
6565 {
6566 /* When there is no immediate operand, generate an 8bit
6567 immediate operand to encode the first operand. */
6568 exp = &im_expressions[i.imm_operands++];
6569 i.op[i.operands].imms = exp;
6570 i.types[i.operands] = imm8;
6571 i.operands++;
6572 /* If VexW1 is set, the first operand is the source and
6573 the second operand is encoded in the immediate operand. */
6574 if (i.tm.opcode_modifier.vexw == VEXW1)
6575 {
6576 source = 0;
6577 reg_slot = 1;
6578 }
6579 else
6580 {
6581 source = 1;
6582 reg_slot = 0;
6583 }
6584
6585 /* FMA swaps REG and NDS. */
6586 if (i.tm.cpu_flags.bitfield.cpufma)
6587 {
6588 unsigned int tmp;
6589 tmp = reg_slot;
6590 reg_slot = nds;
6591 nds = tmp;
6592 }
6593
6594 gas_assert (i.tm.operand_types[reg_slot].bitfield.regsimd);
6595 exp->X_op = O_constant;
6596 exp->X_add_number = register_number (i.op[reg_slot].regs) << 4;
6597 gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
6598 }
6599 else
6600 {
6601 unsigned int imm_slot;
6602
6603 if (i.tm.opcode_modifier.vexw == VEXW0)
6604 {
6605 /* If VexW0 is set, the third operand is the source and
6606 the second operand is encoded in the immediate
6607 operand. */
6608 source = 2;
6609 reg_slot = 1;
6610 }
6611 else
6612 {
6613 /* VexW1 is set, the second operand is the source and
6614 the third operand is encoded in the immediate
6615 operand. */
6616 source = 1;
6617 reg_slot = 2;
6618 }
6619
6620 if (i.tm.opcode_modifier.immext)
6621 {
6622 /* When ImmExt is set, the immediate byte is the last
6623 operand. */
6624 imm_slot = i.operands - 1;
6625 source--;
6626 reg_slot--;
6627 }
6628 else
6629 {
6630 imm_slot = 0;
6631
6632 /* Turn on Imm8 so that output_imm will generate it. */
6633 i.types[imm_slot].bitfield.imm8 = 1;
6634 }
6635
6636 gas_assert (i.tm.operand_types[reg_slot].bitfield.regsimd);
6637 i.op[imm_slot].imms->X_add_number
6638 |= register_number (i.op[reg_slot].regs) << 4;
6639 gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
6640 }
6641
6642 gas_assert (i.tm.operand_types[nds].bitfield.regsimd);
6643 i.vex.register_specifier = i.op[nds].regs;
6644 }
6645 else
6646 source = dest = 0;
6647
6648 /* i.reg_operands MUST be the number of real register operands;
6649 implicit registers do not count. If there are 3 register
6650 operands, it must be a instruction with VexNDS. For a
6651 instruction with VexNDD, the destination register is encoded
6652 in VEX prefix. If there are 4 register operands, it must be
6653 a instruction with VEX prefix and 3 sources. */
6654 if (i.mem_operands == 0
6655 && ((i.reg_operands == 2
6656 && i.tm.opcode_modifier.vexvvvv <= VEXXDS)
6657 || (i.reg_operands == 3
6658 && i.tm.opcode_modifier.vexvvvv == VEXXDS)
6659 || (i.reg_operands == 4 && vex_3_sources)))
6660 {
6661 switch (i.operands)
6662 {
6663 case 2:
6664 source = 0;
6665 break;
6666 case 3:
6667 /* When there are 3 operands, one of them may be immediate,
6668 which may be the first or the last operand. Otherwise,
6669 the first operand must be shift count register (cl) or it
6670 is an instruction with VexNDS. */
6671 gas_assert (i.imm_operands == 1
6672 || (i.imm_operands == 0
6673 && (i.tm.opcode_modifier.vexvvvv == VEXXDS
6674 || i.types[0].bitfield.shiftcount)));
6675 if (operand_type_check (i.types[0], imm)
6676 || i.types[0].bitfield.shiftcount)
6677 source = 1;
6678 else
6679 source = 0;
6680 break;
6681 case 4:
6682 /* When there are 4 operands, the first two must be 8bit
6683 immediate operands. The source operand will be the 3rd
6684 one.
6685
6686 For instructions with VexNDS, if the first operand
6687 an imm8, the source operand is the 2nd one. If the last
6688 operand is imm8, the source operand is the first one. */
6689 gas_assert ((i.imm_operands == 2
6690 && i.types[0].bitfield.imm8
6691 && i.types[1].bitfield.imm8)
6692 || (i.tm.opcode_modifier.vexvvvv == VEXXDS
6693 && i.imm_operands == 1
6694 && (i.types[0].bitfield.imm8
6695 || i.types[i.operands - 1].bitfield.imm8
6696 || i.rounding)));
6697 if (i.imm_operands == 2)
6698 source = 2;
6699 else
6700 {
6701 if (i.types[0].bitfield.imm8)
6702 source = 1;
6703 else
6704 source = 0;
6705 }
6706 break;
6707 case 5:
6708 if (is_evex_encoding (&i.tm))
6709 {
6710 /* For EVEX instructions, when there are 5 operands, the
6711 first one must be immediate operand. If the second one
6712 is immediate operand, the source operand is the 3th
6713 one. If the last one is immediate operand, the source
6714 operand is the 2nd one. */
6715 gas_assert (i.imm_operands == 2
6716 && i.tm.opcode_modifier.sae
6717 && operand_type_check (i.types[0], imm));
6718 if (operand_type_check (i.types[1], imm))
6719 source = 2;
6720 else if (operand_type_check (i.types[4], imm))
6721 source = 1;
6722 else
6723 abort ();
6724 }
6725 break;
6726 default:
6727 abort ();
6728 }
6729
6730 if (!vex_3_sources)
6731 {
6732 dest = source + 1;
6733
6734 /* RC/SAE operand could be between DEST and SRC. That happens
6735 when one operand is GPR and the other one is XMM/YMM/ZMM
6736 register. */
6737 if (i.rounding && i.rounding->operand == (int) dest)
6738 dest++;
6739
6740 if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
6741 {
6742 /* For instructions with VexNDS, the register-only source
6743 operand must be a 32/64bit integer, XMM, YMM, ZMM, or mask
6744 register. It is encoded in VEX prefix. We need to
6745 clear RegMem bit before calling operand_type_equal. */
6746
6747 i386_operand_type op;
6748 unsigned int vvvv;
6749
6750 /* Check register-only source operand when two source
6751 operands are swapped. */
6752 if (!i.tm.operand_types[source].bitfield.baseindex
6753 && i.tm.operand_types[dest].bitfield.baseindex)
6754 {
6755 vvvv = source;
6756 source = dest;
6757 }
6758 else
6759 vvvv = dest;
6760
6761 op = i.tm.operand_types[vvvv];
6762 op.bitfield.regmem = 0;
6763 if ((dest + 1) >= i.operands
6764 || ((!op.bitfield.reg
6765 || (!op.bitfield.dword && !op.bitfield.qword))
6766 && !op.bitfield.regsimd
6767 && !operand_type_equal (&op, &regmask)))
6768 abort ();
6769 i.vex.register_specifier = i.op[vvvv].regs;
6770 dest++;
6771 }
6772 }
6773
6774 i.rm.mode = 3;
6775 /* One of the register operands will be encoded in the i.tm.reg
6776 field, the other in the combined i.tm.mode and i.tm.regmem
6777 fields. If no form of this instruction supports a memory
6778 destination operand, then we assume the source operand may
6779 sometimes be a memory operand and so we need to store the
6780 destination in the i.rm.reg field. */
6781 if (!i.tm.operand_types[dest].bitfield.regmem
6782 && operand_type_check (i.tm.operand_types[dest], anymem) == 0)
6783 {
6784 i.rm.reg = i.op[dest].regs->reg_num;
6785 i.rm.regmem = i.op[source].regs->reg_num;
6786 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
6787 i.rex |= REX_R;
6788 if ((i.op[dest].regs->reg_flags & RegVRex) != 0)
6789 i.vrex |= REX_R;
6790 if ((i.op[source].regs->reg_flags & RegRex) != 0)
6791 i.rex |= REX_B;
6792 if ((i.op[source].regs->reg_flags & RegVRex) != 0)
6793 i.vrex |= REX_B;
6794 }
6795 else
6796 {
6797 i.rm.reg = i.op[source].regs->reg_num;
6798 i.rm.regmem = i.op[dest].regs->reg_num;
6799 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
6800 i.rex |= REX_B;
6801 if ((i.op[dest].regs->reg_flags & RegVRex) != 0)
6802 i.vrex |= REX_B;
6803 if ((i.op[source].regs->reg_flags & RegRex) != 0)
6804 i.rex |= REX_R;
6805 if ((i.op[source].regs->reg_flags & RegVRex) != 0)
6806 i.vrex |= REX_R;
6807 }
6808 if (flag_code != CODE_64BIT && (i.rex & (REX_R | REX_B)))
6809 {
6810 if (!i.types[0].bitfield.control
6811 && !i.types[1].bitfield.control)
6812 abort ();
6813 i.rex &= ~(REX_R | REX_B);
6814 add_prefix (LOCK_PREFIX_OPCODE);
6815 }
6816 }
6817 else
6818 { /* If it's not 2 reg operands... */
6819 unsigned int mem;
6820
6821 if (i.mem_operands)
6822 {
6823 unsigned int fake_zero_displacement = 0;
6824 unsigned int op;
6825
6826 for (op = 0; op < i.operands; op++)
6827 if (operand_type_check (i.types[op], anymem))
6828 break;
6829 gas_assert (op < i.operands);
6830
6831 if (i.tm.opcode_modifier.vecsib)
6832 {
6833 if (i.index_reg->reg_num == RegEiz
6834 || i.index_reg->reg_num == RegRiz)
6835 abort ();
6836
6837 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6838 if (!i.base_reg)
6839 {
6840 i.sib.base = NO_BASE_REGISTER;
6841 i.sib.scale = i.log2_scale_factor;
6842 i.types[op].bitfield.disp8 = 0;
6843 i.types[op].bitfield.disp16 = 0;
6844 i.types[op].bitfield.disp64 = 0;
6845 if (flag_code != CODE_64BIT || i.prefix[ADDR_PREFIX])
6846 {
6847 /* Must be 32 bit */
6848 i.types[op].bitfield.disp32 = 1;
6849 i.types[op].bitfield.disp32s = 0;
6850 }
6851 else
6852 {
6853 i.types[op].bitfield.disp32 = 0;
6854 i.types[op].bitfield.disp32s = 1;
6855 }
6856 }
6857 i.sib.index = i.index_reg->reg_num;
6858 if ((i.index_reg->reg_flags & RegRex) != 0)
6859 i.rex |= REX_X;
6860 if ((i.index_reg->reg_flags & RegVRex) != 0)
6861 i.vrex |= REX_X;
6862 }
6863
6864 default_seg = &ds;
6865
6866 if (i.base_reg == 0)
6867 {
6868 i.rm.mode = 0;
6869 if (!i.disp_operands)
6870 fake_zero_displacement = 1;
6871 if (i.index_reg == 0)
6872 {
6873 i386_operand_type newdisp;
6874
6875 gas_assert (!i.tm.opcode_modifier.vecsib);
6876 /* Operand is just <disp> */
6877 if (flag_code == CODE_64BIT)
6878 {
6879 /* 64bit mode overwrites the 32bit absolute
6880 addressing by RIP relative addressing and
6881 absolute addressing is encoded by one of the
6882 redundant SIB forms. */
6883 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6884 i.sib.base = NO_BASE_REGISTER;
6885 i.sib.index = NO_INDEX_REGISTER;
6886 newdisp = (!i.prefix[ADDR_PREFIX] ? disp32s : disp32);
6887 }
6888 else if ((flag_code == CODE_16BIT)
6889 ^ (i.prefix[ADDR_PREFIX] != 0))
6890 {
6891 i.rm.regmem = NO_BASE_REGISTER_16;
6892 newdisp = disp16;
6893 }
6894 else
6895 {
6896 i.rm.regmem = NO_BASE_REGISTER;
6897 newdisp = disp32;
6898 }
6899 i.types[op] = operand_type_and_not (i.types[op], anydisp);
6900 i.types[op] = operand_type_or (i.types[op], newdisp);
6901 }
6902 else if (!i.tm.opcode_modifier.vecsib)
6903 {
6904 /* !i.base_reg && i.index_reg */
6905 if (i.index_reg->reg_num == RegEiz
6906 || i.index_reg->reg_num == RegRiz)
6907 i.sib.index = NO_INDEX_REGISTER;
6908 else
6909 i.sib.index = i.index_reg->reg_num;
6910 i.sib.base = NO_BASE_REGISTER;
6911 i.sib.scale = i.log2_scale_factor;
6912 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6913 i.types[op].bitfield.disp8 = 0;
6914 i.types[op].bitfield.disp16 = 0;
6915 i.types[op].bitfield.disp64 = 0;
6916 if (flag_code != CODE_64BIT || i.prefix[ADDR_PREFIX])
6917 {
6918 /* Must be 32 bit */
6919 i.types[op].bitfield.disp32 = 1;
6920 i.types[op].bitfield.disp32s = 0;
6921 }
6922 else
6923 {
6924 i.types[op].bitfield.disp32 = 0;
6925 i.types[op].bitfield.disp32s = 1;
6926 }
6927 if ((i.index_reg->reg_flags & RegRex) != 0)
6928 i.rex |= REX_X;
6929 }
6930 }
6931 /* RIP addressing for 64bit mode. */
6932 else if (i.base_reg->reg_num == RegRip ||
6933 i.base_reg->reg_num == RegEip)
6934 {
6935 gas_assert (!i.tm.opcode_modifier.vecsib);
6936 i.rm.regmem = NO_BASE_REGISTER;
6937 i.types[op].bitfield.disp8 = 0;
6938 i.types[op].bitfield.disp16 = 0;
6939 i.types[op].bitfield.disp32 = 0;
6940 i.types[op].bitfield.disp32s = 1;
6941 i.types[op].bitfield.disp64 = 0;
6942 i.flags[op] |= Operand_PCrel;
6943 if (! i.disp_operands)
6944 fake_zero_displacement = 1;
6945 }
6946 else if (i.base_reg->reg_type.bitfield.word)
6947 {
6948 gas_assert (!i.tm.opcode_modifier.vecsib);
6949 switch (i.base_reg->reg_num)
6950 {
6951 case 3: /* (%bx) */
6952 if (i.index_reg == 0)
6953 i.rm.regmem = 7;
6954 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
6955 i.rm.regmem = i.index_reg->reg_num - 6;
6956 break;
6957 case 5: /* (%bp) */
6958 default_seg = &ss;
6959 if (i.index_reg == 0)
6960 {
6961 i.rm.regmem = 6;
6962 if (operand_type_check (i.types[op], disp) == 0)
6963 {
6964 /* fake (%bp) into 0(%bp) */
6965 i.types[op].bitfield.disp8 = 1;
6966 fake_zero_displacement = 1;
6967 }
6968 }
6969 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
6970 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
6971 break;
6972 default: /* (%si) -> 4 or (%di) -> 5 */
6973 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
6974 }
6975 i.rm.mode = mode_from_disp_size (i.types[op]);
6976 }
6977 else /* i.base_reg and 32/64 bit mode */
6978 {
6979 if (flag_code == CODE_64BIT
6980 && operand_type_check (i.types[op], disp))
6981 {
6982 i.types[op].bitfield.disp16 = 0;
6983 i.types[op].bitfield.disp64 = 0;
6984 if (i.prefix[ADDR_PREFIX] == 0)
6985 {
6986 i.types[op].bitfield.disp32 = 0;
6987 i.types[op].bitfield.disp32s = 1;
6988 }
6989 else
6990 {
6991 i.types[op].bitfield.disp32 = 1;
6992 i.types[op].bitfield.disp32s = 0;
6993 }
6994 }
6995
6996 if (!i.tm.opcode_modifier.vecsib)
6997 i.rm.regmem = i.base_reg->reg_num;
6998 if ((i.base_reg->reg_flags & RegRex) != 0)
6999 i.rex |= REX_B;
7000 i.sib.base = i.base_reg->reg_num;
7001 /* x86-64 ignores REX prefix bit here to avoid decoder
7002 complications. */
7003 if (!(i.base_reg->reg_flags & RegRex)
7004 && (i.base_reg->reg_num == EBP_REG_NUM
7005 || i.base_reg->reg_num == ESP_REG_NUM))
7006 default_seg = &ss;
7007 if (i.base_reg->reg_num == 5 && i.disp_operands == 0)
7008 {
7009 fake_zero_displacement = 1;
7010 i.types[op].bitfield.disp8 = 1;
7011 }
7012 i.sib.scale = i.log2_scale_factor;
7013 if (i.index_reg == 0)
7014 {
7015 gas_assert (!i.tm.opcode_modifier.vecsib);
7016 /* <disp>(%esp) becomes two byte modrm with no index
7017 register. We've already stored the code for esp
7018 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
7019 Any base register besides %esp will not use the
7020 extra modrm byte. */
7021 i.sib.index = NO_INDEX_REGISTER;
7022 }
7023 else if (!i.tm.opcode_modifier.vecsib)
7024 {
7025 if (i.index_reg->reg_num == RegEiz
7026 || i.index_reg->reg_num == RegRiz)
7027 i.sib.index = NO_INDEX_REGISTER;
7028 else
7029 i.sib.index = i.index_reg->reg_num;
7030 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
7031 if ((i.index_reg->reg_flags & RegRex) != 0)
7032 i.rex |= REX_X;
7033 }
7034
7035 if (i.disp_operands
7036 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
7037 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
7038 i.rm.mode = 0;
7039 else
7040 {
7041 if (!fake_zero_displacement
7042 && !i.disp_operands
7043 && i.disp_encoding)
7044 {
7045 fake_zero_displacement = 1;
7046 if (i.disp_encoding == disp_encoding_8bit)
7047 i.types[op].bitfield.disp8 = 1;
7048 else
7049 i.types[op].bitfield.disp32 = 1;
7050 }
7051 i.rm.mode = mode_from_disp_size (i.types[op]);
7052 }
7053 }
7054
7055 if (fake_zero_displacement)
7056 {
7057 /* Fakes a zero displacement assuming that i.types[op]
7058 holds the correct displacement size. */
7059 expressionS *exp;
7060
7061 gas_assert (i.op[op].disps == 0);
7062 exp = &disp_expressions[i.disp_operands++];
7063 i.op[op].disps = exp;
7064 exp->X_op = O_constant;
7065 exp->X_add_number = 0;
7066 exp->X_add_symbol = (symbolS *) 0;
7067 exp->X_op_symbol = (symbolS *) 0;
7068 }
7069
7070 mem = op;
7071 }
7072 else
7073 mem = ~0;
7074
7075 if (i.tm.opcode_modifier.vexsources == XOP2SOURCES)
7076 {
7077 if (operand_type_check (i.types[0], imm))
7078 i.vex.register_specifier = NULL;
7079 else
7080 {
7081 /* VEX.vvvv encodes one of the sources when the first
7082 operand is not an immediate. */
7083 if (i.tm.opcode_modifier.vexw == VEXW0)
7084 i.vex.register_specifier = i.op[0].regs;
7085 else
7086 i.vex.register_specifier = i.op[1].regs;
7087 }
7088
7089 /* Destination is a XMM register encoded in the ModRM.reg
7090 and VEX.R bit. */
7091 i.rm.reg = i.op[2].regs->reg_num;
7092 if ((i.op[2].regs->reg_flags & RegRex) != 0)
7093 i.rex |= REX_R;
7094
7095 /* ModRM.rm and VEX.B encodes the other source. */
7096 if (!i.mem_operands)
7097 {
7098 i.rm.mode = 3;
7099
7100 if (i.tm.opcode_modifier.vexw == VEXW0)
7101 i.rm.regmem = i.op[1].regs->reg_num;
7102 else
7103 i.rm.regmem = i.op[0].regs->reg_num;
7104
7105 if ((i.op[1].regs->reg_flags & RegRex) != 0)
7106 i.rex |= REX_B;
7107 }
7108 }
7109 else if (i.tm.opcode_modifier.vexvvvv == VEXLWP)
7110 {
7111 i.vex.register_specifier = i.op[2].regs;
7112 if (!i.mem_operands)
7113 {
7114 i.rm.mode = 3;
7115 i.rm.regmem = i.op[1].regs->reg_num;
7116 if ((i.op[1].regs->reg_flags & RegRex) != 0)
7117 i.rex |= REX_B;
7118 }
7119 }
7120 /* Fill in i.rm.reg or i.rm.regmem field with register operand
7121 (if any) based on i.tm.extension_opcode. Again, we must be
7122 careful to make sure that segment/control/debug/test/MMX
7123 registers are coded into the i.rm.reg field. */
7124 else if (i.reg_operands)
7125 {
7126 unsigned int op;
7127 unsigned int vex_reg = ~0;
7128
7129 for (op = 0; op < i.operands; op++)
7130 if (i.types[op].bitfield.reg
7131 || i.types[op].bitfield.regmmx
7132 || i.types[op].bitfield.regsimd
7133 || i.types[op].bitfield.regbnd
7134 || i.types[op].bitfield.regmask
7135 || i.types[op].bitfield.sreg2
7136 || i.types[op].bitfield.sreg3
7137 || i.types[op].bitfield.control
7138 || i.types[op].bitfield.debug
7139 || i.types[op].bitfield.test)
7140 break;
7141
7142 if (vex_3_sources)
7143 op = dest;
7144 else if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
7145 {
7146 /* For instructions with VexNDS, the register-only
7147 source operand is encoded in VEX prefix. */
7148 gas_assert (mem != (unsigned int) ~0);
7149
7150 if (op > mem)
7151 {
7152 vex_reg = op++;
7153 gas_assert (op < i.operands);
7154 }
7155 else
7156 {
7157 /* Check register-only source operand when two source
7158 operands are swapped. */
7159 if (!i.tm.operand_types[op].bitfield.baseindex
7160 && i.tm.operand_types[op + 1].bitfield.baseindex)
7161 {
7162 vex_reg = op;
7163 op += 2;
7164 gas_assert (mem == (vex_reg + 1)
7165 && op < i.operands);
7166 }
7167 else
7168 {
7169 vex_reg = op + 1;
7170 gas_assert (vex_reg < i.operands);
7171 }
7172 }
7173 }
7174 else if (i.tm.opcode_modifier.vexvvvv == VEXNDD)
7175 {
7176 /* For instructions with VexNDD, the register destination
7177 is encoded in VEX prefix. */
7178 if (i.mem_operands == 0)
7179 {
7180 /* There is no memory operand. */
7181 gas_assert ((op + 2) == i.operands);
7182 vex_reg = op + 1;
7183 }
7184 else
7185 {
7186 /* There are only 2 non-immediate operands. */
7187 gas_assert (op < i.imm_operands + 2
7188 && i.operands == i.imm_operands + 2);
7189 vex_reg = i.imm_operands + 1;
7190 }
7191 }
7192 else
7193 gas_assert (op < i.operands);
7194
7195 if (vex_reg != (unsigned int) ~0)
7196 {
7197 i386_operand_type *type = &i.tm.operand_types[vex_reg];
7198
7199 if ((!type->bitfield.reg
7200 || (!type->bitfield.dword && !type->bitfield.qword))
7201 && !type->bitfield.regsimd
7202 && !operand_type_equal (type, &regmask))
7203 abort ();
7204
7205 i.vex.register_specifier = i.op[vex_reg].regs;
7206 }
7207
7208 /* Don't set OP operand twice. */
7209 if (vex_reg != op)
7210 {
7211 /* If there is an extension opcode to put here, the
7212 register number must be put into the regmem field. */
7213 if (i.tm.extension_opcode != None)
7214 {
7215 i.rm.regmem = i.op[op].regs->reg_num;
7216 if ((i.op[op].regs->reg_flags & RegRex) != 0)
7217 i.rex |= REX_B;
7218 if ((i.op[op].regs->reg_flags & RegVRex) != 0)
7219 i.vrex |= REX_B;
7220 }
7221 else
7222 {
7223 i.rm.reg = i.op[op].regs->reg_num;
7224 if ((i.op[op].regs->reg_flags & RegRex) != 0)
7225 i.rex |= REX_R;
7226 if ((i.op[op].regs->reg_flags & RegVRex) != 0)
7227 i.vrex |= REX_R;
7228 }
7229 }
7230
7231 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
7232 must set it to 3 to indicate this is a register operand
7233 in the regmem field. */
7234 if (!i.mem_operands)
7235 i.rm.mode = 3;
7236 }
7237
7238 /* Fill in i.rm.reg field with extension opcode (if any). */
7239 if (i.tm.extension_opcode != None)
7240 i.rm.reg = i.tm.extension_opcode;
7241 }
7242 return default_seg;
7243 }
7244
7245 static void
7246 output_branch (void)
7247 {
7248 char *p;
7249 int size;
7250 int code16;
7251 int prefix;
7252 relax_substateT subtype;
7253 symbolS *sym;
7254 offsetT off;
7255
7256 code16 = flag_code == CODE_16BIT ? CODE16 : 0;
7257 size = i.disp_encoding == disp_encoding_32bit ? BIG : SMALL;
7258
7259 prefix = 0;
7260 if (i.prefix[DATA_PREFIX] != 0)
7261 {
7262 prefix = 1;
7263 i.prefixes -= 1;
7264 code16 ^= CODE16;
7265 }
7266 /* Pentium4 branch hints. */
7267 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
7268 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
7269 {
7270 prefix++;
7271 i.prefixes--;
7272 }
7273 if (i.prefix[REX_PREFIX] != 0)
7274 {
7275 prefix++;
7276 i.prefixes--;
7277 }
7278
7279 /* BND prefixed jump. */
7280 if (i.prefix[BND_PREFIX] != 0)
7281 {
7282 FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]);
7283 i.prefixes -= 1;
7284 }
7285
7286 if (i.prefixes != 0 && !intel_syntax)
7287 as_warn (_("skipping prefixes on this instruction"));
7288
7289 /* It's always a symbol; End frag & setup for relax.
7290 Make sure there is enough room in this frag for the largest
7291 instruction we may generate in md_convert_frag. This is 2
7292 bytes for the opcode and room for the prefix and largest
7293 displacement. */
7294 frag_grow (prefix + 2 + 4);
7295 /* Prefix and 1 opcode byte go in fr_fix. */
7296 p = frag_more (prefix + 1);
7297 if (i.prefix[DATA_PREFIX] != 0)
7298 *p++ = DATA_PREFIX_OPCODE;
7299 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
7300 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
7301 *p++ = i.prefix[SEG_PREFIX];
7302 if (i.prefix[REX_PREFIX] != 0)
7303 *p++ = i.prefix[REX_PREFIX];
7304 *p = i.tm.base_opcode;
7305
7306 if ((unsigned char) *p == JUMP_PC_RELATIVE)
7307 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, size);
7308 else if (cpu_arch_flags.bitfield.cpui386)
7309 subtype = ENCODE_RELAX_STATE (COND_JUMP, size);
7310 else
7311 subtype = ENCODE_RELAX_STATE (COND_JUMP86, size);
7312 subtype |= code16;
7313
7314 sym = i.op[0].disps->X_add_symbol;
7315 off = i.op[0].disps->X_add_number;
7316
7317 if (i.op[0].disps->X_op != O_constant
7318 && i.op[0].disps->X_op != O_symbol)
7319 {
7320 /* Handle complex expressions. */
7321 sym = make_expr_symbol (i.op[0].disps);
7322 off = 0;
7323 }
7324
7325 /* 1 possible extra opcode + 4 byte displacement go in var part.
7326 Pass reloc in fr_var. */
7327 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
7328 }
7329
7330 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7331 /* Return TRUE iff PLT32 relocation should be used for branching to
7332 symbol S. */
7333
7334 static bfd_boolean
7335 need_plt32_p (symbolS *s)
7336 {
7337 /* PLT32 relocation is ELF only. */
7338 if (!IS_ELF)
7339 return FALSE;
7340
7341 /* Since there is no need to prepare for PLT branch on x86-64, we
7342 can generate R_X86_64_PLT32, instead of R_X86_64_PC32, which can
7343 be used as a marker for 32-bit PC-relative branches. */
7344 if (!object_64bit)
7345 return FALSE;
7346
7347 /* Weak or undefined symbol need PLT32 relocation. */
7348 if (S_IS_WEAK (s) || !S_IS_DEFINED (s))
7349 return TRUE;
7350
7351 /* Non-global symbol doesn't need PLT32 relocation. */
7352 if (! S_IS_EXTERNAL (s))
7353 return FALSE;
7354
7355 /* Other global symbols need PLT32 relocation. NB: Symbol with
7356 non-default visibilities are treated as normal global symbol
7357 so that PLT32 relocation can be used as a marker for 32-bit
7358 PC-relative branches. It is useful for linker relaxation. */
7359 return TRUE;
7360 }
7361 #endif
7362
7363 static void
7364 output_jump (void)
7365 {
7366 char *p;
7367 int size;
7368 fixS *fixP;
7369 bfd_reloc_code_real_type jump_reloc = i.reloc[0];
7370
7371 if (i.tm.opcode_modifier.jumpbyte)
7372 {
7373 /* This is a loop or jecxz type instruction. */
7374 size = 1;
7375 if (i.prefix[ADDR_PREFIX] != 0)
7376 {
7377 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
7378 i.prefixes -= 1;
7379 }
7380 /* Pentium4 branch hints. */
7381 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
7382 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
7383 {
7384 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
7385 i.prefixes--;
7386 }
7387 }
7388 else
7389 {
7390 int code16;
7391
7392 code16 = 0;
7393 if (flag_code == CODE_16BIT)
7394 code16 = CODE16;
7395
7396 if (i.prefix[DATA_PREFIX] != 0)
7397 {
7398 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
7399 i.prefixes -= 1;
7400 code16 ^= CODE16;
7401 }
7402
7403 size = 4;
7404 if (code16)
7405 size = 2;
7406 }
7407
7408 if (i.prefix[REX_PREFIX] != 0)
7409 {
7410 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
7411 i.prefixes -= 1;
7412 }
7413
7414 /* BND prefixed jump. */
7415 if (i.prefix[BND_PREFIX] != 0)
7416 {
7417 FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]);
7418 i.prefixes -= 1;
7419 }
7420
7421 if (i.prefixes != 0 && !intel_syntax)
7422 as_warn (_("skipping prefixes on this instruction"));
7423
7424 p = frag_more (i.tm.opcode_length + size);
7425 switch (i.tm.opcode_length)
7426 {
7427 case 2:
7428 *p++ = i.tm.base_opcode >> 8;
7429 /* Fall through. */
7430 case 1:
7431 *p++ = i.tm.base_opcode;
7432 break;
7433 default:
7434 abort ();
7435 }
7436
7437 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7438 if (size == 4
7439 && jump_reloc == NO_RELOC
7440 && need_plt32_p (i.op[0].disps->X_add_symbol))
7441 jump_reloc = BFD_RELOC_X86_64_PLT32;
7442 #endif
7443
7444 jump_reloc = reloc (size, 1, 1, jump_reloc);
7445
7446 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
7447 i.op[0].disps, 1, jump_reloc);
7448
7449 /* All jumps handled here are signed, but don't use a signed limit
7450 check for 32 and 16 bit jumps as we want to allow wrap around at
7451 4G and 64k respectively. */
7452 if (size == 1)
7453 fixP->fx_signed = 1;
7454 }
7455
7456 static void
7457 output_interseg_jump (void)
7458 {
7459 char *p;
7460 int size;
7461 int prefix;
7462 int code16;
7463
7464 code16 = 0;
7465 if (flag_code == CODE_16BIT)
7466 code16 = CODE16;
7467
7468 prefix = 0;
7469 if (i.prefix[DATA_PREFIX] != 0)
7470 {
7471 prefix = 1;
7472 i.prefixes -= 1;
7473 code16 ^= CODE16;
7474 }
7475 if (i.prefix[REX_PREFIX] != 0)
7476 {
7477 prefix++;
7478 i.prefixes -= 1;
7479 }
7480
7481 size = 4;
7482 if (code16)
7483 size = 2;
7484
7485 if (i.prefixes != 0 && !intel_syntax)
7486 as_warn (_("skipping prefixes on this instruction"));
7487
7488 /* 1 opcode; 2 segment; offset */
7489 p = frag_more (prefix + 1 + 2 + size);
7490
7491 if (i.prefix[DATA_PREFIX] != 0)
7492 *p++ = DATA_PREFIX_OPCODE;
7493
7494 if (i.prefix[REX_PREFIX] != 0)
7495 *p++ = i.prefix[REX_PREFIX];
7496
7497 *p++ = i.tm.base_opcode;
7498 if (i.op[1].imms->X_op == O_constant)
7499 {
7500 offsetT n = i.op[1].imms->X_add_number;
7501
7502 if (size == 2
7503 && !fits_in_unsigned_word (n)
7504 && !fits_in_signed_word (n))
7505 {
7506 as_bad (_("16-bit jump out of range"));
7507 return;
7508 }
7509 md_number_to_chars (p, n, size);
7510 }
7511 else
7512 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
7513 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
7514 if (i.op[0].imms->X_op != O_constant)
7515 as_bad (_("can't handle non absolute segment in `%s'"),
7516 i.tm.name);
7517 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
7518 }
7519
7520 static void
7521 output_insn (void)
7522 {
7523 fragS *insn_start_frag;
7524 offsetT insn_start_off;
7525
7526 /* Tie dwarf2 debug info to the address at the start of the insn.
7527 We can't do this after the insn has been output as the current
7528 frag may have been closed off. eg. by frag_var. */
7529 dwarf2_emit_insn (0);
7530
7531 insn_start_frag = frag_now;
7532 insn_start_off = frag_now_fix ();
7533
7534 /* Output jumps. */
7535 if (i.tm.opcode_modifier.jump)
7536 output_branch ();
7537 else if (i.tm.opcode_modifier.jumpbyte
7538 || i.tm.opcode_modifier.jumpdword)
7539 output_jump ();
7540 else if (i.tm.opcode_modifier.jumpintersegment)
7541 output_interseg_jump ();
7542 else
7543 {
7544 /* Output normal instructions here. */
7545 char *p;
7546 unsigned char *q;
7547 unsigned int j;
7548 unsigned int prefix;
7549
7550 if (avoid_fence
7551 && i.tm.base_opcode == 0xfae
7552 && i.operands == 1
7553 && i.imm_operands == 1
7554 && (i.op[0].imms->X_add_number == 0xe8
7555 || i.op[0].imms->X_add_number == 0xf0
7556 || i.op[0].imms->X_add_number == 0xf8))
7557 {
7558 /* Encode lfence, mfence, and sfence as
7559 f0 83 04 24 00 lock addl $0x0, (%{re}sp). */
7560 offsetT val = 0x240483f0ULL;
7561 p = frag_more (5);
7562 md_number_to_chars (p, val, 5);
7563 return;
7564 }
7565
7566 /* Some processors fail on LOCK prefix. This options makes
7567 assembler ignore LOCK prefix and serves as a workaround. */
7568 if (omit_lock_prefix)
7569 {
7570 if (i.tm.base_opcode == LOCK_PREFIX_OPCODE)
7571 return;
7572 i.prefix[LOCK_PREFIX] = 0;
7573 }
7574
7575 /* Since the VEX/EVEX prefix contains the implicit prefix, we
7576 don't need the explicit prefix. */
7577 if (!i.tm.opcode_modifier.vex && !i.tm.opcode_modifier.evex)
7578 {
7579 switch (i.tm.opcode_length)
7580 {
7581 case 3:
7582 if (i.tm.base_opcode & 0xff000000)
7583 {
7584 prefix = (i.tm.base_opcode >> 24) & 0xff;
7585 goto check_prefix;
7586 }
7587 break;
7588 case 2:
7589 if ((i.tm.base_opcode & 0xff0000) != 0)
7590 {
7591 prefix = (i.tm.base_opcode >> 16) & 0xff;
7592 if (i.tm.cpu_flags.bitfield.cpupadlock)
7593 {
7594 check_prefix:
7595 if (prefix != REPE_PREFIX_OPCODE
7596 || (i.prefix[REP_PREFIX]
7597 != REPE_PREFIX_OPCODE))
7598 add_prefix (prefix);
7599 }
7600 else
7601 add_prefix (prefix);
7602 }
7603 break;
7604 case 1:
7605 break;
7606 case 0:
7607 /* Check for pseudo prefixes. */
7608 as_bad_where (insn_start_frag->fr_file,
7609 insn_start_frag->fr_line,
7610 _("pseudo prefix without instruction"));
7611 return;
7612 default:
7613 abort ();
7614 }
7615
7616 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
7617 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
7618 R_X86_64_GOTTPOFF relocation so that linker can safely
7619 perform IE->LE optimization. */
7620 if (x86_elf_abi == X86_64_X32_ABI
7621 && i.operands == 2
7622 && i.reloc[0] == BFD_RELOC_X86_64_GOTTPOFF
7623 && i.prefix[REX_PREFIX] == 0)
7624 add_prefix (REX_OPCODE);
7625 #endif
7626
7627 /* The prefix bytes. */
7628 for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++)
7629 if (*q)
7630 FRAG_APPEND_1_CHAR (*q);
7631 }
7632 else
7633 {
7634 for (j = 0, q = i.prefix; j < ARRAY_SIZE (i.prefix); j++, q++)
7635 if (*q)
7636 switch (j)
7637 {
7638 case REX_PREFIX:
7639 /* REX byte is encoded in VEX prefix. */
7640 break;
7641 case SEG_PREFIX:
7642 case ADDR_PREFIX:
7643 FRAG_APPEND_1_CHAR (*q);
7644 break;
7645 default:
7646 /* There should be no other prefixes for instructions
7647 with VEX prefix. */
7648 abort ();
7649 }
7650
7651 /* For EVEX instructions i.vrex should become 0 after
7652 build_evex_prefix. For VEX instructions upper 16 registers
7653 aren't available, so VREX should be 0. */
7654 if (i.vrex)
7655 abort ();
7656 /* Now the VEX prefix. */
7657 p = frag_more (i.vex.length);
7658 for (j = 0; j < i.vex.length; j++)
7659 p[j] = i.vex.bytes[j];
7660 }
7661
7662 /* Now the opcode; be careful about word order here! */
7663 if (i.tm.opcode_length == 1)
7664 {
7665 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
7666 }
7667 else
7668 {
7669 switch (i.tm.opcode_length)
7670 {
7671 case 4:
7672 p = frag_more (4);
7673 *p++ = (i.tm.base_opcode >> 24) & 0xff;
7674 *p++ = (i.tm.base_opcode >> 16) & 0xff;
7675 break;
7676 case 3:
7677 p = frag_more (3);
7678 *p++ = (i.tm.base_opcode >> 16) & 0xff;
7679 break;
7680 case 2:
7681 p = frag_more (2);
7682 break;
7683 default:
7684 abort ();
7685 break;
7686 }
7687
7688 /* Put out high byte first: can't use md_number_to_chars! */
7689 *p++ = (i.tm.base_opcode >> 8) & 0xff;
7690 *p = i.tm.base_opcode & 0xff;
7691 }
7692
7693 /* Now the modrm byte and sib byte (if present). */
7694 if (i.tm.opcode_modifier.modrm)
7695 {
7696 FRAG_APPEND_1_CHAR ((i.rm.regmem << 0
7697 | i.rm.reg << 3
7698 | i.rm.mode << 6));
7699 /* If i.rm.regmem == ESP (4)
7700 && i.rm.mode != (Register mode)
7701 && not 16 bit
7702 ==> need second modrm byte. */
7703 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
7704 && i.rm.mode != 3
7705 && !(i.base_reg && i.base_reg->reg_type.bitfield.word))
7706 FRAG_APPEND_1_CHAR ((i.sib.base << 0
7707 | i.sib.index << 3
7708 | i.sib.scale << 6));
7709 }
7710
7711 if (i.disp_operands)
7712 output_disp (insn_start_frag, insn_start_off);
7713
7714 if (i.imm_operands)
7715 output_imm (insn_start_frag, insn_start_off);
7716 }
7717
7718 #ifdef DEBUG386
7719 if (flag_debug)
7720 {
7721 pi ("" /*line*/, &i);
7722 }
7723 #endif /* DEBUG386 */
7724 }
7725
7726 /* Return the size of the displacement operand N. */
7727
7728 static int
7729 disp_size (unsigned int n)
7730 {
7731 int size = 4;
7732
7733 if (i.types[n].bitfield.disp64)
7734 size = 8;
7735 else if (i.types[n].bitfield.disp8)
7736 size = 1;
7737 else if (i.types[n].bitfield.disp16)
7738 size = 2;
7739 return size;
7740 }
7741
7742 /* Return the size of the immediate operand N. */
7743
7744 static int
7745 imm_size (unsigned int n)
7746 {
7747 int size = 4;
7748 if (i.types[n].bitfield.imm64)
7749 size = 8;
7750 else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s)
7751 size = 1;
7752 else if (i.types[n].bitfield.imm16)
7753 size = 2;
7754 return size;
7755 }
7756
7757 static void
7758 output_disp (fragS *insn_start_frag, offsetT insn_start_off)
7759 {
7760 char *p;
7761 unsigned int n;
7762
7763 for (n = 0; n < i.operands; n++)
7764 {
7765 if (operand_type_check (i.types[n], disp))
7766 {
7767 if (i.op[n].disps->X_op == O_constant)
7768 {
7769 int size = disp_size (n);
7770 offsetT val = i.op[n].disps->X_add_number;
7771
7772 val = offset_in_range (val >> i.memshift, size);
7773 p = frag_more (size);
7774 md_number_to_chars (p, val, size);
7775 }
7776 else
7777 {
7778 enum bfd_reloc_code_real reloc_type;
7779 int size = disp_size (n);
7780 int sign = i.types[n].bitfield.disp32s;
7781 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
7782 fixS *fixP;
7783
7784 /* We can't have 8 bit displacement here. */
7785 gas_assert (!i.types[n].bitfield.disp8);
7786
7787 /* The PC relative address is computed relative
7788 to the instruction boundary, so in case immediate
7789 fields follows, we need to adjust the value. */
7790 if (pcrel && i.imm_operands)
7791 {
7792 unsigned int n1;
7793 int sz = 0;
7794
7795 for (n1 = 0; n1 < i.operands; n1++)
7796 if (operand_type_check (i.types[n1], imm))
7797 {
7798 /* Only one immediate is allowed for PC
7799 relative address. */
7800 gas_assert (sz == 0);
7801 sz = imm_size (n1);
7802 i.op[n].disps->X_add_number -= sz;
7803 }
7804 /* We should find the immediate. */
7805 gas_assert (sz != 0);
7806 }
7807
7808 p = frag_more (size);
7809 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
7810 if (GOT_symbol
7811 && GOT_symbol == i.op[n].disps->X_add_symbol
7812 && (((reloc_type == BFD_RELOC_32
7813 || reloc_type == BFD_RELOC_X86_64_32S
7814 || (reloc_type == BFD_RELOC_64
7815 && object_64bit))
7816 && (i.op[n].disps->X_op == O_symbol
7817 || (i.op[n].disps->X_op == O_add
7818 && ((symbol_get_value_expression
7819 (i.op[n].disps->X_op_symbol)->X_op)
7820 == O_subtract))))
7821 || reloc_type == BFD_RELOC_32_PCREL))
7822 {
7823 offsetT add;
7824
7825 if (insn_start_frag == frag_now)
7826 add = (p - frag_now->fr_literal) - insn_start_off;
7827 else
7828 {
7829 fragS *fr;
7830
7831 add = insn_start_frag->fr_fix - insn_start_off;
7832 for (fr = insn_start_frag->fr_next;
7833 fr && fr != frag_now; fr = fr->fr_next)
7834 add += fr->fr_fix;
7835 add += p - frag_now->fr_literal;
7836 }
7837
7838 if (!object_64bit)
7839 {
7840 reloc_type = BFD_RELOC_386_GOTPC;
7841 i.op[n].imms->X_add_number += add;
7842 }
7843 else if (reloc_type == BFD_RELOC_64)
7844 reloc_type = BFD_RELOC_X86_64_GOTPC64;
7845 else
7846 /* Don't do the adjustment for x86-64, as there
7847 the pcrel addressing is relative to the _next_
7848 insn, and that is taken care of in other code. */
7849 reloc_type = BFD_RELOC_X86_64_GOTPC32;
7850 }
7851 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal,
7852 size, i.op[n].disps, pcrel,
7853 reloc_type);
7854 /* Check for "call/jmp *mem", "mov mem, %reg",
7855 "test %reg, mem" and "binop mem, %reg" where binop
7856 is one of adc, add, and, cmp, or, sbb, sub, xor
7857 instructions. Always generate R_386_GOT32X for
7858 "sym*GOT" operand in 32-bit mode. */
7859 if ((generate_relax_relocations
7860 || (!object_64bit
7861 && i.rm.mode == 0
7862 && i.rm.regmem == 5))
7863 && (i.rm.mode == 2
7864 || (i.rm.mode == 0 && i.rm.regmem == 5))
7865 && ((i.operands == 1
7866 && i.tm.base_opcode == 0xff
7867 && (i.rm.reg == 2 || i.rm.reg == 4))
7868 || (i.operands == 2
7869 && (i.tm.base_opcode == 0x8b
7870 || i.tm.base_opcode == 0x85
7871 || (i.tm.base_opcode & 0xc7) == 0x03))))
7872 {
7873 if (object_64bit)
7874 {
7875 fixP->fx_tcbit = i.rex != 0;
7876 if (i.base_reg
7877 && (i.base_reg->reg_num == RegRip
7878 || i.base_reg->reg_num == RegEip))
7879 fixP->fx_tcbit2 = 1;
7880 }
7881 else
7882 fixP->fx_tcbit2 = 1;
7883 }
7884 }
7885 }
7886 }
7887 }
7888
7889 static void
7890 output_imm (fragS *insn_start_frag, offsetT insn_start_off)
7891 {
7892 char *p;
7893 unsigned int n;
7894
7895 for (n = 0; n < i.operands; n++)
7896 {
7897 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
7898 if (i.rounding && (int) n == i.rounding->operand)
7899 continue;
7900
7901 if (operand_type_check (i.types[n], imm))
7902 {
7903 if (i.op[n].imms->X_op == O_constant)
7904 {
7905 int size = imm_size (n);
7906 offsetT val;
7907
7908 val = offset_in_range (i.op[n].imms->X_add_number,
7909 size);
7910 p = frag_more (size);
7911 md_number_to_chars (p, val, size);
7912 }
7913 else
7914 {
7915 /* Not absolute_section.
7916 Need a 32-bit fixup (don't support 8bit
7917 non-absolute imms). Try to support other
7918 sizes ... */
7919 enum bfd_reloc_code_real reloc_type;
7920 int size = imm_size (n);
7921 int sign;
7922
7923 if (i.types[n].bitfield.imm32s
7924 && (i.suffix == QWORD_MNEM_SUFFIX
7925 || (!i.suffix && i.tm.opcode_modifier.no_lsuf)))
7926 sign = 1;
7927 else
7928 sign = 0;
7929
7930 p = frag_more (size);
7931 reloc_type = reloc (size, 0, sign, i.reloc[n]);
7932
7933 /* This is tough to explain. We end up with this one if we
7934 * have operands that look like
7935 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
7936 * obtain the absolute address of the GOT, and it is strongly
7937 * preferable from a performance point of view to avoid using
7938 * a runtime relocation for this. The actual sequence of
7939 * instructions often look something like:
7940 *
7941 * call .L66
7942 * .L66:
7943 * popl %ebx
7944 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
7945 *
7946 * The call and pop essentially return the absolute address
7947 * of the label .L66 and store it in %ebx. The linker itself
7948 * will ultimately change the first operand of the addl so
7949 * that %ebx points to the GOT, but to keep things simple, the
7950 * .o file must have this operand set so that it generates not
7951 * the absolute address of .L66, but the absolute address of
7952 * itself. This allows the linker itself simply treat a GOTPC
7953 * relocation as asking for a pcrel offset to the GOT to be
7954 * added in, and the addend of the relocation is stored in the
7955 * operand field for the instruction itself.
7956 *
7957 * Our job here is to fix the operand so that it would add
7958 * the correct offset so that %ebx would point to itself. The
7959 * thing that is tricky is that .-.L66 will point to the
7960 * beginning of the instruction, so we need to further modify
7961 * the operand so that it will point to itself. There are
7962 * other cases where you have something like:
7963 *
7964 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
7965 *
7966 * and here no correction would be required. Internally in
7967 * the assembler we treat operands of this form as not being
7968 * pcrel since the '.' is explicitly mentioned, and I wonder
7969 * whether it would simplify matters to do it this way. Who
7970 * knows. In earlier versions of the PIC patches, the
7971 * pcrel_adjust field was used to store the correction, but
7972 * since the expression is not pcrel, I felt it would be
7973 * confusing to do it this way. */
7974
7975 if ((reloc_type == BFD_RELOC_32
7976 || reloc_type == BFD_RELOC_X86_64_32S
7977 || reloc_type == BFD_RELOC_64)
7978 && GOT_symbol
7979 && GOT_symbol == i.op[n].imms->X_add_symbol
7980 && (i.op[n].imms->X_op == O_symbol
7981 || (i.op[n].imms->X_op == O_add
7982 && ((symbol_get_value_expression
7983 (i.op[n].imms->X_op_symbol)->X_op)
7984 == O_subtract))))
7985 {
7986 offsetT add;
7987
7988 if (insn_start_frag == frag_now)
7989 add = (p - frag_now->fr_literal) - insn_start_off;
7990 else
7991 {
7992 fragS *fr;
7993
7994 add = insn_start_frag->fr_fix - insn_start_off;
7995 for (fr = insn_start_frag->fr_next;
7996 fr && fr != frag_now; fr = fr->fr_next)
7997 add += fr->fr_fix;
7998 add += p - frag_now->fr_literal;
7999 }
8000
8001 if (!object_64bit)
8002 reloc_type = BFD_RELOC_386_GOTPC;
8003 else if (size == 4)
8004 reloc_type = BFD_RELOC_X86_64_GOTPC32;
8005 else if (size == 8)
8006 reloc_type = BFD_RELOC_X86_64_GOTPC64;
8007 i.op[n].imms->X_add_number += add;
8008 }
8009 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
8010 i.op[n].imms, 0, reloc_type);
8011 }
8012 }
8013 }
8014 }
8015 \f
8016 /* x86_cons_fix_new is called via the expression parsing code when a
8017 reloc is needed. We use this hook to get the correct .got reloc. */
8018 static int cons_sign = -1;
8019
8020 void
8021 x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len,
8022 expressionS *exp, bfd_reloc_code_real_type r)
8023 {
8024 r = reloc (len, 0, cons_sign, r);
8025
8026 #ifdef TE_PE
8027 if (exp->X_op == O_secrel)
8028 {
8029 exp->X_op = O_symbol;
8030 r = BFD_RELOC_32_SECREL;
8031 }
8032 #endif
8033
8034 fix_new_exp (frag, off, len, exp, 0, r);
8035 }
8036
8037 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
8038 purpose of the `.dc.a' internal pseudo-op. */
8039
8040 int
8041 x86_address_bytes (void)
8042 {
8043 if ((stdoutput->arch_info->mach & bfd_mach_x64_32))
8044 return 4;
8045 return stdoutput->arch_info->bits_per_address / 8;
8046 }
8047
8048 #if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
8049 || defined (LEX_AT)
8050 # define lex_got(reloc, adjust, types) NULL
8051 #else
8052 /* Parse operands of the form
8053 <symbol>@GOTOFF+<nnn>
8054 and similar .plt or .got references.
8055
8056 If we find one, set up the correct relocation in RELOC and copy the
8057 input string, minus the `@GOTOFF' into a malloc'd buffer for
8058 parsing by the calling routine. Return this buffer, and if ADJUST
8059 is non-null set it to the length of the string we removed from the
8060 input line. Otherwise return NULL. */
8061 static char *
8062 lex_got (enum bfd_reloc_code_real *rel,
8063 int *adjust,
8064 i386_operand_type *types)
8065 {
8066 /* Some of the relocations depend on the size of what field is to
8067 be relocated. But in our callers i386_immediate and i386_displacement
8068 we don't yet know the operand size (this will be set by insn
8069 matching). Hence we record the word32 relocation here,
8070 and adjust the reloc according to the real size in reloc(). */
8071 static const struct {
8072 const char *str;
8073 int len;
8074 const enum bfd_reloc_code_real rel[2];
8075 const i386_operand_type types64;
8076 } gotrel[] = {
8077 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8078 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32,
8079 BFD_RELOC_SIZE32 },
8080 OPERAND_TYPE_IMM32_64 },
8081 #endif
8082 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real,
8083 BFD_RELOC_X86_64_PLTOFF64 },
8084 OPERAND_TYPE_IMM64 },
8085 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32,
8086 BFD_RELOC_X86_64_PLT32 },
8087 OPERAND_TYPE_IMM32_32S_DISP32 },
8088 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real,
8089 BFD_RELOC_X86_64_GOTPLT64 },
8090 OPERAND_TYPE_IMM64_DISP64 },
8091 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF,
8092 BFD_RELOC_X86_64_GOTOFF64 },
8093 OPERAND_TYPE_IMM64_DISP64 },
8094 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real,
8095 BFD_RELOC_X86_64_GOTPCREL },
8096 OPERAND_TYPE_IMM32_32S_DISP32 },
8097 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD,
8098 BFD_RELOC_X86_64_TLSGD },
8099 OPERAND_TYPE_IMM32_32S_DISP32 },
8100 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM,
8101 _dummy_first_bfd_reloc_code_real },
8102 OPERAND_TYPE_NONE },
8103 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real,
8104 BFD_RELOC_X86_64_TLSLD },
8105 OPERAND_TYPE_IMM32_32S_DISP32 },
8106 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32,
8107 BFD_RELOC_X86_64_GOTTPOFF },
8108 OPERAND_TYPE_IMM32_32S_DISP32 },
8109 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32,
8110 BFD_RELOC_X86_64_TPOFF32 },
8111 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
8112 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE,
8113 _dummy_first_bfd_reloc_code_real },
8114 OPERAND_TYPE_NONE },
8115 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32,
8116 BFD_RELOC_X86_64_DTPOFF32 },
8117 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
8118 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE,
8119 _dummy_first_bfd_reloc_code_real },
8120 OPERAND_TYPE_NONE },
8121 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE,
8122 _dummy_first_bfd_reloc_code_real },
8123 OPERAND_TYPE_NONE },
8124 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32,
8125 BFD_RELOC_X86_64_GOT32 },
8126 OPERAND_TYPE_IMM32_32S_64_DISP32 },
8127 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC,
8128 BFD_RELOC_X86_64_GOTPC32_TLSDESC },
8129 OPERAND_TYPE_IMM32_32S_DISP32 },
8130 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL,
8131 BFD_RELOC_X86_64_TLSDESC_CALL },
8132 OPERAND_TYPE_IMM32_32S_DISP32 },
8133 };
8134 char *cp;
8135 unsigned int j;
8136
8137 #if defined (OBJ_MAYBE_ELF)
8138 if (!IS_ELF)
8139 return NULL;
8140 #endif
8141
8142 for (cp = input_line_pointer; *cp != '@'; cp++)
8143 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
8144 return NULL;
8145
8146 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
8147 {
8148 int len = gotrel[j].len;
8149 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
8150 {
8151 if (gotrel[j].rel[object_64bit] != 0)
8152 {
8153 int first, second;
8154 char *tmpbuf, *past_reloc;
8155
8156 *rel = gotrel[j].rel[object_64bit];
8157
8158 if (types)
8159 {
8160 if (flag_code != CODE_64BIT)
8161 {
8162 types->bitfield.imm32 = 1;
8163 types->bitfield.disp32 = 1;
8164 }
8165 else
8166 *types = gotrel[j].types64;
8167 }
8168
8169 if (j != 0 && GOT_symbol == NULL)
8170 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
8171
8172 /* The length of the first part of our input line. */
8173 first = cp - input_line_pointer;
8174
8175 /* The second part goes from after the reloc token until
8176 (and including) an end_of_line char or comma. */
8177 past_reloc = cp + 1 + len;
8178 cp = past_reloc;
8179 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
8180 ++cp;
8181 second = cp + 1 - past_reloc;
8182
8183 /* Allocate and copy string. The trailing NUL shouldn't
8184 be necessary, but be safe. */
8185 tmpbuf = XNEWVEC (char, first + second + 2);
8186 memcpy (tmpbuf, input_line_pointer, first);
8187 if (second != 0 && *past_reloc != ' ')
8188 /* Replace the relocation token with ' ', so that
8189 errors like foo@GOTOFF1 will be detected. */
8190 tmpbuf[first++] = ' ';
8191 else
8192 /* Increment length by 1 if the relocation token is
8193 removed. */
8194 len++;
8195 if (adjust)
8196 *adjust = len;
8197 memcpy (tmpbuf + first, past_reloc, second);
8198 tmpbuf[first + second] = '\0';
8199 return tmpbuf;
8200 }
8201
8202 as_bad (_("@%s reloc is not supported with %d-bit output format"),
8203 gotrel[j].str, 1 << (5 + object_64bit));
8204 return NULL;
8205 }
8206 }
8207
8208 /* Might be a symbol version string. Don't as_bad here. */
8209 return NULL;
8210 }
8211 #endif
8212
8213 #ifdef TE_PE
8214 #ifdef lex_got
8215 #undef lex_got
8216 #endif
8217 /* Parse operands of the form
8218 <symbol>@SECREL32+<nnn>
8219
8220 If we find one, set up the correct relocation in RELOC and copy the
8221 input string, minus the `@SECREL32' into a malloc'd buffer for
8222 parsing by the calling routine. Return this buffer, and if ADJUST
8223 is non-null set it to the length of the string we removed from the
8224 input line. Otherwise return NULL.
8225
8226 This function is copied from the ELF version above adjusted for PE targets. */
8227
8228 static char *
8229 lex_got (enum bfd_reloc_code_real *rel ATTRIBUTE_UNUSED,
8230 int *adjust ATTRIBUTE_UNUSED,
8231 i386_operand_type *types)
8232 {
8233 static const struct
8234 {
8235 const char *str;
8236 int len;
8237 const enum bfd_reloc_code_real rel[2];
8238 const i386_operand_type types64;
8239 }
8240 gotrel[] =
8241 {
8242 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL,
8243 BFD_RELOC_32_SECREL },
8244 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
8245 };
8246
8247 char *cp;
8248 unsigned j;
8249
8250 for (cp = input_line_pointer; *cp != '@'; cp++)
8251 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
8252 return NULL;
8253
8254 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
8255 {
8256 int len = gotrel[j].len;
8257
8258 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
8259 {
8260 if (gotrel[j].rel[object_64bit] != 0)
8261 {
8262 int first, second;
8263 char *tmpbuf, *past_reloc;
8264
8265 *rel = gotrel[j].rel[object_64bit];
8266 if (adjust)
8267 *adjust = len;
8268
8269 if (types)
8270 {
8271 if (flag_code != CODE_64BIT)
8272 {
8273 types->bitfield.imm32 = 1;
8274 types->bitfield.disp32 = 1;
8275 }
8276 else
8277 *types = gotrel[j].types64;
8278 }
8279
8280 /* The length of the first part of our input line. */
8281 first = cp - input_line_pointer;
8282
8283 /* The second part goes from after the reloc token until
8284 (and including) an end_of_line char or comma. */
8285 past_reloc = cp + 1 + len;
8286 cp = past_reloc;
8287 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
8288 ++cp;
8289 second = cp + 1 - past_reloc;
8290
8291 /* Allocate and copy string. The trailing NUL shouldn't
8292 be necessary, but be safe. */
8293 tmpbuf = XNEWVEC (char, first + second + 2);
8294 memcpy (tmpbuf, input_line_pointer, first);
8295 if (second != 0 && *past_reloc != ' ')
8296 /* Replace the relocation token with ' ', so that
8297 errors like foo@SECLREL321 will be detected. */
8298 tmpbuf[first++] = ' ';
8299 memcpy (tmpbuf + first, past_reloc, second);
8300 tmpbuf[first + second] = '\0';
8301 return tmpbuf;
8302 }
8303
8304 as_bad (_("@%s reloc is not supported with %d-bit output format"),
8305 gotrel[j].str, 1 << (5 + object_64bit));
8306 return NULL;
8307 }
8308 }
8309
8310 /* Might be a symbol version string. Don't as_bad here. */
8311 return NULL;
8312 }
8313
8314 #endif /* TE_PE */
8315
8316 bfd_reloc_code_real_type
8317 x86_cons (expressionS *exp, int size)
8318 {
8319 bfd_reloc_code_real_type got_reloc = NO_RELOC;
8320
8321 intel_syntax = -intel_syntax;
8322
8323 exp->X_md = 0;
8324 if (size == 4 || (object_64bit && size == 8))
8325 {
8326 /* Handle @GOTOFF and the like in an expression. */
8327 char *save;
8328 char *gotfree_input_line;
8329 int adjust = 0;
8330
8331 save = input_line_pointer;
8332 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
8333 if (gotfree_input_line)
8334 input_line_pointer = gotfree_input_line;
8335
8336 expression (exp);
8337
8338 if (gotfree_input_line)
8339 {
8340 /* expression () has merrily parsed up to the end of line,
8341 or a comma - in the wrong buffer. Transfer how far
8342 input_line_pointer has moved to the right buffer. */
8343 input_line_pointer = (save
8344 + (input_line_pointer - gotfree_input_line)
8345 + adjust);
8346 free (gotfree_input_line);
8347 if (exp->X_op == O_constant
8348 || exp->X_op == O_absent
8349 || exp->X_op == O_illegal
8350 || exp->X_op == O_register
8351 || exp->X_op == O_big)
8352 {
8353 char c = *input_line_pointer;
8354 *input_line_pointer = 0;
8355 as_bad (_("missing or invalid expression `%s'"), save);
8356 *input_line_pointer = c;
8357 }
8358 }
8359 }
8360 else
8361 expression (exp);
8362
8363 intel_syntax = -intel_syntax;
8364
8365 if (intel_syntax)
8366 i386_intel_simplify (exp);
8367
8368 return got_reloc;
8369 }
8370
8371 static void
8372 signed_cons (int size)
8373 {
8374 if (flag_code == CODE_64BIT)
8375 cons_sign = 1;
8376 cons (size);
8377 cons_sign = -1;
8378 }
8379
8380 #ifdef TE_PE
8381 static void
8382 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED)
8383 {
8384 expressionS exp;
8385
8386 do
8387 {
8388 expression (&exp);
8389 if (exp.X_op == O_symbol)
8390 exp.X_op = O_secrel;
8391
8392 emit_expr (&exp, 4);
8393 }
8394 while (*input_line_pointer++ == ',');
8395
8396 input_line_pointer--;
8397 demand_empty_rest_of_line ();
8398 }
8399 #endif
8400
8401 /* Handle Vector operations. */
8402
8403 static char *
8404 check_VecOperations (char *op_string, char *op_end)
8405 {
8406 const reg_entry *mask;
8407 const char *saved;
8408 char *end_op;
8409
8410 while (*op_string
8411 && (op_end == NULL || op_string < op_end))
8412 {
8413 saved = op_string;
8414 if (*op_string == '{')
8415 {
8416 op_string++;
8417
8418 /* Check broadcasts. */
8419 if (strncmp (op_string, "1to", 3) == 0)
8420 {
8421 int bcst_type;
8422
8423 if (i.broadcast)
8424 goto duplicated_vec_op;
8425
8426 op_string += 3;
8427 if (*op_string == '8')
8428 bcst_type = BROADCAST_1TO8;
8429 else if (*op_string == '4')
8430 bcst_type = BROADCAST_1TO4;
8431 else if (*op_string == '2')
8432 bcst_type = BROADCAST_1TO2;
8433 else if (*op_string == '1'
8434 && *(op_string+1) == '6')
8435 {
8436 bcst_type = BROADCAST_1TO16;
8437 op_string++;
8438 }
8439 else
8440 {
8441 as_bad (_("Unsupported broadcast: `%s'"), saved);
8442 return NULL;
8443 }
8444 op_string++;
8445
8446 broadcast_op.type = bcst_type;
8447 broadcast_op.operand = this_operand;
8448 i.broadcast = &broadcast_op;
8449 }
8450 /* Check masking operation. */
8451 else if ((mask = parse_register (op_string, &end_op)) != NULL)
8452 {
8453 /* k0 can't be used for write mask. */
8454 if (!mask->reg_type.bitfield.regmask || mask->reg_num == 0)
8455 {
8456 as_bad (_("`%s%s' can't be used for write mask"),
8457 register_prefix, mask->reg_name);
8458 return NULL;
8459 }
8460
8461 if (!i.mask)
8462 {
8463 mask_op.mask = mask;
8464 mask_op.zeroing = 0;
8465 mask_op.operand = this_operand;
8466 i.mask = &mask_op;
8467 }
8468 else
8469 {
8470 if (i.mask->mask)
8471 goto duplicated_vec_op;
8472
8473 i.mask->mask = mask;
8474
8475 /* Only "{z}" is allowed here. No need to check
8476 zeroing mask explicitly. */
8477 if (i.mask->operand != this_operand)
8478 {
8479 as_bad (_("invalid write mask `%s'"), saved);
8480 return NULL;
8481 }
8482 }
8483
8484 op_string = end_op;
8485 }
8486 /* Check zeroing-flag for masking operation. */
8487 else if (*op_string == 'z')
8488 {
8489 if (!i.mask)
8490 {
8491 mask_op.mask = NULL;
8492 mask_op.zeroing = 1;
8493 mask_op.operand = this_operand;
8494 i.mask = &mask_op;
8495 }
8496 else
8497 {
8498 if (i.mask->zeroing)
8499 {
8500 duplicated_vec_op:
8501 as_bad (_("duplicated `%s'"), saved);
8502 return NULL;
8503 }
8504
8505 i.mask->zeroing = 1;
8506
8507 /* Only "{%k}" is allowed here. No need to check mask
8508 register explicitly. */
8509 if (i.mask->operand != this_operand)
8510 {
8511 as_bad (_("invalid zeroing-masking `%s'"),
8512 saved);
8513 return NULL;
8514 }
8515 }
8516
8517 op_string++;
8518 }
8519 else
8520 goto unknown_vec_op;
8521
8522 if (*op_string != '}')
8523 {
8524 as_bad (_("missing `}' in `%s'"), saved);
8525 return NULL;
8526 }
8527 op_string++;
8528
8529 /* Strip whitespace since the addition of pseudo prefixes
8530 changed how the scrubber treats '{'. */
8531 if (is_space_char (*op_string))
8532 ++op_string;
8533
8534 continue;
8535 }
8536 unknown_vec_op:
8537 /* We don't know this one. */
8538 as_bad (_("unknown vector operation: `%s'"), saved);
8539 return NULL;
8540 }
8541
8542 if (i.mask && i.mask->zeroing && !i.mask->mask)
8543 {
8544 as_bad (_("zeroing-masking only allowed with write mask"));
8545 return NULL;
8546 }
8547
8548 return op_string;
8549 }
8550
8551 static int
8552 i386_immediate (char *imm_start)
8553 {
8554 char *save_input_line_pointer;
8555 char *gotfree_input_line;
8556 segT exp_seg = 0;
8557 expressionS *exp;
8558 i386_operand_type types;
8559
8560 operand_type_set (&types, ~0);
8561
8562 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
8563 {
8564 as_bad (_("at most %d immediate operands are allowed"),
8565 MAX_IMMEDIATE_OPERANDS);
8566 return 0;
8567 }
8568
8569 exp = &im_expressions[i.imm_operands++];
8570 i.op[this_operand].imms = exp;
8571
8572 if (is_space_char (*imm_start))
8573 ++imm_start;
8574
8575 save_input_line_pointer = input_line_pointer;
8576 input_line_pointer = imm_start;
8577
8578 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
8579 if (gotfree_input_line)
8580 input_line_pointer = gotfree_input_line;
8581
8582 exp_seg = expression (exp);
8583
8584 SKIP_WHITESPACE ();
8585
8586 /* Handle vector operations. */
8587 if (*input_line_pointer == '{')
8588 {
8589 input_line_pointer = check_VecOperations (input_line_pointer,
8590 NULL);
8591 if (input_line_pointer == NULL)
8592 return 0;
8593 }
8594
8595 if (*input_line_pointer)
8596 as_bad (_("junk `%s' after expression"), input_line_pointer);
8597
8598 input_line_pointer = save_input_line_pointer;
8599 if (gotfree_input_line)
8600 {
8601 free (gotfree_input_line);
8602
8603 if (exp->X_op == O_constant || exp->X_op == O_register)
8604 exp->X_op = O_illegal;
8605 }
8606
8607 return i386_finalize_immediate (exp_seg, exp, types, imm_start);
8608 }
8609
8610 static int
8611 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
8612 i386_operand_type types, const char *imm_start)
8613 {
8614 if (exp->X_op == O_absent || exp->X_op == O_illegal || exp->X_op == O_big)
8615 {
8616 if (imm_start)
8617 as_bad (_("missing or invalid immediate expression `%s'"),
8618 imm_start);
8619 return 0;
8620 }
8621 else if (exp->X_op == O_constant)
8622 {
8623 /* Size it properly later. */
8624 i.types[this_operand].bitfield.imm64 = 1;
8625 /* If not 64bit, sign extend val. */
8626 if (flag_code != CODE_64BIT
8627 && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
8628 exp->X_add_number
8629 = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
8630 }
8631 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8632 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
8633 && exp_seg != absolute_section
8634 && exp_seg != text_section
8635 && exp_seg != data_section
8636 && exp_seg != bss_section
8637 && exp_seg != undefined_section
8638 && !bfd_is_com_section (exp_seg))
8639 {
8640 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
8641 return 0;
8642 }
8643 #endif
8644 else if (!intel_syntax && exp_seg == reg_section)
8645 {
8646 if (imm_start)
8647 as_bad (_("illegal immediate register operand %s"), imm_start);
8648 return 0;
8649 }
8650 else
8651 {
8652 /* This is an address. The size of the address will be
8653 determined later, depending on destination register,
8654 suffix, or the default for the section. */
8655 i.types[this_operand].bitfield.imm8 = 1;
8656 i.types[this_operand].bitfield.imm16 = 1;
8657 i.types[this_operand].bitfield.imm32 = 1;
8658 i.types[this_operand].bitfield.imm32s = 1;
8659 i.types[this_operand].bitfield.imm64 = 1;
8660 i.types[this_operand] = operand_type_and (i.types[this_operand],
8661 types);
8662 }
8663
8664 return 1;
8665 }
8666
8667 static char *
8668 i386_scale (char *scale)
8669 {
8670 offsetT val;
8671 char *save = input_line_pointer;
8672
8673 input_line_pointer = scale;
8674 val = get_absolute_expression ();
8675
8676 switch (val)
8677 {
8678 case 1:
8679 i.log2_scale_factor = 0;
8680 break;
8681 case 2:
8682 i.log2_scale_factor = 1;
8683 break;
8684 case 4:
8685 i.log2_scale_factor = 2;
8686 break;
8687 case 8:
8688 i.log2_scale_factor = 3;
8689 break;
8690 default:
8691 {
8692 char sep = *input_line_pointer;
8693
8694 *input_line_pointer = '\0';
8695 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
8696 scale);
8697 *input_line_pointer = sep;
8698 input_line_pointer = save;
8699 return NULL;
8700 }
8701 }
8702 if (i.log2_scale_factor != 0 && i.index_reg == 0)
8703 {
8704 as_warn (_("scale factor of %d without an index register"),
8705 1 << i.log2_scale_factor);
8706 i.log2_scale_factor = 0;
8707 }
8708 scale = input_line_pointer;
8709 input_line_pointer = save;
8710 return scale;
8711 }
8712
8713 static int
8714 i386_displacement (char *disp_start, char *disp_end)
8715 {
8716 expressionS *exp;
8717 segT exp_seg = 0;
8718 char *save_input_line_pointer;
8719 char *gotfree_input_line;
8720 int override;
8721 i386_operand_type bigdisp, types = anydisp;
8722 int ret;
8723
8724 if (i.disp_operands == MAX_MEMORY_OPERANDS)
8725 {
8726 as_bad (_("at most %d displacement operands are allowed"),
8727 MAX_MEMORY_OPERANDS);
8728 return 0;
8729 }
8730
8731 operand_type_set (&bigdisp, 0);
8732 if ((i.types[this_operand].bitfield.jumpabsolute)
8733 || (!current_templates->start->opcode_modifier.jump
8734 && !current_templates->start->opcode_modifier.jumpdword))
8735 {
8736 bigdisp.bitfield.disp32 = 1;
8737 override = (i.prefix[ADDR_PREFIX] != 0);
8738 if (flag_code == CODE_64BIT)
8739 {
8740 if (!override)
8741 {
8742 bigdisp.bitfield.disp32s = 1;
8743 bigdisp.bitfield.disp64 = 1;
8744 }
8745 }
8746 else if ((flag_code == CODE_16BIT) ^ override)
8747 {
8748 bigdisp.bitfield.disp32 = 0;
8749 bigdisp.bitfield.disp16 = 1;
8750 }
8751 }
8752 else
8753 {
8754 /* For PC-relative branches, the width of the displacement
8755 is dependent upon data size, not address size. */
8756 override = (i.prefix[DATA_PREFIX] != 0);
8757 if (flag_code == CODE_64BIT)
8758 {
8759 if (override || i.suffix == WORD_MNEM_SUFFIX)
8760 bigdisp.bitfield.disp16 = 1;
8761 else
8762 {
8763 bigdisp.bitfield.disp32 = 1;
8764 bigdisp.bitfield.disp32s = 1;
8765 }
8766 }
8767 else
8768 {
8769 if (!override)
8770 override = (i.suffix == (flag_code != CODE_16BIT
8771 ? WORD_MNEM_SUFFIX
8772 : LONG_MNEM_SUFFIX));
8773 bigdisp.bitfield.disp32 = 1;
8774 if ((flag_code == CODE_16BIT) ^ override)
8775 {
8776 bigdisp.bitfield.disp32 = 0;
8777 bigdisp.bitfield.disp16 = 1;
8778 }
8779 }
8780 }
8781 i.types[this_operand] = operand_type_or (i.types[this_operand],
8782 bigdisp);
8783
8784 exp = &disp_expressions[i.disp_operands];
8785 i.op[this_operand].disps = exp;
8786 i.disp_operands++;
8787 save_input_line_pointer = input_line_pointer;
8788 input_line_pointer = disp_start;
8789 END_STRING_AND_SAVE (disp_end);
8790
8791 #ifndef GCC_ASM_O_HACK
8792 #define GCC_ASM_O_HACK 0
8793 #endif
8794 #if GCC_ASM_O_HACK
8795 END_STRING_AND_SAVE (disp_end + 1);
8796 if (i.types[this_operand].bitfield.baseIndex
8797 && displacement_string_end[-1] == '+')
8798 {
8799 /* This hack is to avoid a warning when using the "o"
8800 constraint within gcc asm statements.
8801 For instance:
8802
8803 #define _set_tssldt_desc(n,addr,limit,type) \
8804 __asm__ __volatile__ ( \
8805 "movw %w2,%0\n\t" \
8806 "movw %w1,2+%0\n\t" \
8807 "rorl $16,%1\n\t" \
8808 "movb %b1,4+%0\n\t" \
8809 "movb %4,5+%0\n\t" \
8810 "movb $0,6+%0\n\t" \
8811 "movb %h1,7+%0\n\t" \
8812 "rorl $16,%1" \
8813 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
8814
8815 This works great except that the output assembler ends
8816 up looking a bit weird if it turns out that there is
8817 no offset. You end up producing code that looks like:
8818
8819 #APP
8820 movw $235,(%eax)
8821 movw %dx,2+(%eax)
8822 rorl $16,%edx
8823 movb %dl,4+(%eax)
8824 movb $137,5+(%eax)
8825 movb $0,6+(%eax)
8826 movb %dh,7+(%eax)
8827 rorl $16,%edx
8828 #NO_APP
8829
8830 So here we provide the missing zero. */
8831
8832 *displacement_string_end = '0';
8833 }
8834 #endif
8835 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
8836 if (gotfree_input_line)
8837 input_line_pointer = gotfree_input_line;
8838
8839 exp_seg = expression (exp);
8840
8841 SKIP_WHITESPACE ();
8842 if (*input_line_pointer)
8843 as_bad (_("junk `%s' after expression"), input_line_pointer);
8844 #if GCC_ASM_O_HACK
8845 RESTORE_END_STRING (disp_end + 1);
8846 #endif
8847 input_line_pointer = save_input_line_pointer;
8848 if (gotfree_input_line)
8849 {
8850 free (gotfree_input_line);
8851
8852 if (exp->X_op == O_constant || exp->X_op == O_register)
8853 exp->X_op = O_illegal;
8854 }
8855
8856 ret = i386_finalize_displacement (exp_seg, exp, types, disp_start);
8857
8858 RESTORE_END_STRING (disp_end);
8859
8860 return ret;
8861 }
8862
8863 static int
8864 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
8865 i386_operand_type types, const char *disp_start)
8866 {
8867 i386_operand_type bigdisp;
8868 int ret = 1;
8869
8870 /* We do this to make sure that the section symbol is in
8871 the symbol table. We will ultimately change the relocation
8872 to be relative to the beginning of the section. */
8873 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
8874 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
8875 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
8876 {
8877 if (exp->X_op != O_symbol)
8878 goto inv_disp;
8879
8880 if (S_IS_LOCAL (exp->X_add_symbol)
8881 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section
8882 && S_GET_SEGMENT (exp->X_add_symbol) != expr_section)
8883 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
8884 exp->X_op = O_subtract;
8885 exp->X_op_symbol = GOT_symbol;
8886 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
8887 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
8888 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
8889 i.reloc[this_operand] = BFD_RELOC_64;
8890 else
8891 i.reloc[this_operand] = BFD_RELOC_32;
8892 }
8893
8894 else if (exp->X_op == O_absent
8895 || exp->X_op == O_illegal
8896 || exp->X_op == O_big)
8897 {
8898 inv_disp:
8899 as_bad (_("missing or invalid displacement expression `%s'"),
8900 disp_start);
8901 ret = 0;
8902 }
8903
8904 else if (flag_code == CODE_64BIT
8905 && !i.prefix[ADDR_PREFIX]
8906 && exp->X_op == O_constant)
8907 {
8908 /* Since displacement is signed extended to 64bit, don't allow
8909 disp32 and turn off disp32s if they are out of range. */
8910 i.types[this_operand].bitfield.disp32 = 0;
8911 if (!fits_in_signed_long (exp->X_add_number))
8912 {
8913 i.types[this_operand].bitfield.disp32s = 0;
8914 if (i.types[this_operand].bitfield.baseindex)
8915 {
8916 as_bad (_("0x%lx out range of signed 32bit displacement"),
8917 (long) exp->X_add_number);
8918 ret = 0;
8919 }
8920 }
8921 }
8922
8923 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8924 else if (exp->X_op != O_constant
8925 && OUTPUT_FLAVOR == bfd_target_aout_flavour
8926 && exp_seg != absolute_section
8927 && exp_seg != text_section
8928 && exp_seg != data_section
8929 && exp_seg != bss_section
8930 && exp_seg != undefined_section
8931 && !bfd_is_com_section (exp_seg))
8932 {
8933 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
8934 ret = 0;
8935 }
8936 #endif
8937
8938 /* Check if this is a displacement only operand. */
8939 bigdisp = i.types[this_operand];
8940 bigdisp.bitfield.disp8 = 0;
8941 bigdisp.bitfield.disp16 = 0;
8942 bigdisp.bitfield.disp32 = 0;
8943 bigdisp.bitfield.disp32s = 0;
8944 bigdisp.bitfield.disp64 = 0;
8945 if (operand_type_all_zero (&bigdisp))
8946 i.types[this_operand] = operand_type_and (i.types[this_operand],
8947 types);
8948
8949 return ret;
8950 }
8951
8952 /* Return the active addressing mode, taking address override and
8953 registers forming the address into consideration. Update the
8954 address override prefix if necessary. */
8955
8956 static enum flag_code
8957 i386_addressing_mode (void)
8958 {
8959 enum flag_code addr_mode;
8960
8961 if (i.prefix[ADDR_PREFIX])
8962 addr_mode = flag_code == CODE_32BIT ? CODE_16BIT : CODE_32BIT;
8963 else
8964 {
8965 addr_mode = flag_code;
8966
8967 #if INFER_ADDR_PREFIX
8968 if (i.mem_operands == 0)
8969 {
8970 /* Infer address prefix from the first memory operand. */
8971 const reg_entry *addr_reg = i.base_reg;
8972
8973 if (addr_reg == NULL)
8974 addr_reg = i.index_reg;
8975
8976 if (addr_reg)
8977 {
8978 if (addr_reg->reg_num == RegEip
8979 || addr_reg->reg_num == RegEiz
8980 || addr_reg->reg_type.bitfield.dword)
8981 addr_mode = CODE_32BIT;
8982 else if (flag_code != CODE_64BIT
8983 && addr_reg->reg_type.bitfield.word)
8984 addr_mode = CODE_16BIT;
8985
8986 if (addr_mode != flag_code)
8987 {
8988 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
8989 i.prefixes += 1;
8990 /* Change the size of any displacement too. At most one
8991 of Disp16 or Disp32 is set.
8992 FIXME. There doesn't seem to be any real need for
8993 separate Disp16 and Disp32 flags. The same goes for
8994 Imm16 and Imm32. Removing them would probably clean
8995 up the code quite a lot. */
8996 if (flag_code != CODE_64BIT
8997 && (i.types[this_operand].bitfield.disp16
8998 || i.types[this_operand].bitfield.disp32))
8999 i.types[this_operand]
9000 = operand_type_xor (i.types[this_operand], disp16_32);
9001 }
9002 }
9003 }
9004 #endif
9005 }
9006
9007 return addr_mode;
9008 }
9009
9010 /* Make sure the memory operand we've been dealt is valid.
9011 Return 1 on success, 0 on a failure. */
9012
9013 static int
9014 i386_index_check (const char *operand_string)
9015 {
9016 const char *kind = "base/index";
9017 enum flag_code addr_mode = i386_addressing_mode ();
9018
9019 if (current_templates->start->opcode_modifier.isstring
9020 && !current_templates->start->opcode_modifier.immext
9021 && (current_templates->end[-1].opcode_modifier.isstring
9022 || i.mem_operands))
9023 {
9024 /* Memory operands of string insns are special in that they only allow
9025 a single register (rDI, rSI, or rBX) as their memory address. */
9026 const reg_entry *expected_reg;
9027 static const char *di_si[][2] =
9028 {
9029 { "esi", "edi" },
9030 { "si", "di" },
9031 { "rsi", "rdi" }
9032 };
9033 static const char *bx[] = { "ebx", "bx", "rbx" };
9034
9035 kind = "string address";
9036
9037 if (current_templates->start->opcode_modifier.repprefixok)
9038 {
9039 i386_operand_type type = current_templates->end[-1].operand_types[0];
9040
9041 if (!type.bitfield.baseindex
9042 || ((!i.mem_operands != !intel_syntax)
9043 && current_templates->end[-1].operand_types[1]
9044 .bitfield.baseindex))
9045 type = current_templates->end[-1].operand_types[1];
9046 expected_reg = hash_find (reg_hash,
9047 di_si[addr_mode][type.bitfield.esseg]);
9048
9049 }
9050 else
9051 expected_reg = hash_find (reg_hash, bx[addr_mode]);
9052
9053 if (i.base_reg != expected_reg
9054 || i.index_reg
9055 || operand_type_check (i.types[this_operand], disp))
9056 {
9057 /* The second memory operand must have the same size as
9058 the first one. */
9059 if (i.mem_operands
9060 && i.base_reg
9061 && !((addr_mode == CODE_64BIT
9062 && i.base_reg->reg_type.bitfield.qword)
9063 || (addr_mode == CODE_32BIT
9064 ? i.base_reg->reg_type.bitfield.dword
9065 : i.base_reg->reg_type.bitfield.word)))
9066 goto bad_address;
9067
9068 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
9069 operand_string,
9070 intel_syntax ? '[' : '(',
9071 register_prefix,
9072 expected_reg->reg_name,
9073 intel_syntax ? ']' : ')');
9074 return 1;
9075 }
9076 else
9077 return 1;
9078
9079 bad_address:
9080 as_bad (_("`%s' is not a valid %s expression"),
9081 operand_string, kind);
9082 return 0;
9083 }
9084 else
9085 {
9086 if (addr_mode != CODE_16BIT)
9087 {
9088 /* 32-bit/64-bit checks. */
9089 if ((i.base_reg
9090 && (addr_mode == CODE_64BIT
9091 ? !i.base_reg->reg_type.bitfield.qword
9092 : !i.base_reg->reg_type.bitfield.dword)
9093 && (i.index_reg
9094 || (i.base_reg->reg_num
9095 != (addr_mode == CODE_64BIT ? RegRip : RegEip))))
9096 || (i.index_reg
9097 && !i.index_reg->reg_type.bitfield.xmmword
9098 && !i.index_reg->reg_type.bitfield.ymmword
9099 && !i.index_reg->reg_type.bitfield.zmmword
9100 && ((addr_mode == CODE_64BIT
9101 ? !(i.index_reg->reg_type.bitfield.qword
9102 || i.index_reg->reg_num == RegRiz)
9103 : !(i.index_reg->reg_type.bitfield.dword
9104 || i.index_reg->reg_num == RegEiz))
9105 || !i.index_reg->reg_type.bitfield.baseindex)))
9106 goto bad_address;
9107
9108 /* bndmk, bndldx, and bndstx have special restrictions. */
9109 if (current_templates->start->base_opcode == 0xf30f1b
9110 || (current_templates->start->base_opcode & ~1) == 0x0f1a)
9111 {
9112 /* They cannot use RIP-relative addressing. */
9113 if (i.base_reg && i.base_reg->reg_num == RegRip)
9114 {
9115 as_bad (_("`%s' cannot be used here"), operand_string);
9116 return 0;
9117 }
9118
9119 /* bndldx and bndstx ignore their scale factor. */
9120 if (current_templates->start->base_opcode != 0xf30f1b
9121 && i.log2_scale_factor)
9122 as_warn (_("register scaling is being ignored here"));
9123 }
9124 }
9125 else
9126 {
9127 /* 16-bit checks. */
9128 if ((i.base_reg
9129 && (!i.base_reg->reg_type.bitfield.word
9130 || !i.base_reg->reg_type.bitfield.baseindex))
9131 || (i.index_reg
9132 && (!i.index_reg->reg_type.bitfield.word
9133 || !i.index_reg->reg_type.bitfield.baseindex
9134 || !(i.base_reg
9135 && i.base_reg->reg_num < 6
9136 && i.index_reg->reg_num >= 6
9137 && i.log2_scale_factor == 0))))
9138 goto bad_address;
9139 }
9140 }
9141 return 1;
9142 }
9143
9144 /* Handle vector immediates. */
9145
9146 static int
9147 RC_SAE_immediate (const char *imm_start)
9148 {
9149 unsigned int match_found, j;
9150 const char *pstr = imm_start;
9151 expressionS *exp;
9152
9153 if (*pstr != '{')
9154 return 0;
9155
9156 pstr++;
9157 match_found = 0;
9158 for (j = 0; j < ARRAY_SIZE (RC_NamesTable); j++)
9159 {
9160 if (!strncmp (pstr, RC_NamesTable[j].name, RC_NamesTable[j].len))
9161 {
9162 if (!i.rounding)
9163 {
9164 rc_op.type = RC_NamesTable[j].type;
9165 rc_op.operand = this_operand;
9166 i.rounding = &rc_op;
9167 }
9168 else
9169 {
9170 as_bad (_("duplicated `%s'"), imm_start);
9171 return 0;
9172 }
9173 pstr += RC_NamesTable[j].len;
9174 match_found = 1;
9175 break;
9176 }
9177 }
9178 if (!match_found)
9179 return 0;
9180
9181 if (*pstr++ != '}')
9182 {
9183 as_bad (_("Missing '}': '%s'"), imm_start);
9184 return 0;
9185 }
9186 /* RC/SAE immediate string should contain nothing more. */;
9187 if (*pstr != 0)
9188 {
9189 as_bad (_("Junk after '}': '%s'"), imm_start);
9190 return 0;
9191 }
9192
9193 exp = &im_expressions[i.imm_operands++];
9194 i.op[this_operand].imms = exp;
9195
9196 exp->X_op = O_constant;
9197 exp->X_add_number = 0;
9198 exp->X_add_symbol = (symbolS *) 0;
9199 exp->X_op_symbol = (symbolS *) 0;
9200
9201 i.types[this_operand].bitfield.imm8 = 1;
9202 return 1;
9203 }
9204
9205 /* Only string instructions can have a second memory operand, so
9206 reduce current_templates to just those if it contains any. */
9207 static int
9208 maybe_adjust_templates (void)
9209 {
9210 const insn_template *t;
9211
9212 gas_assert (i.mem_operands == 1);
9213
9214 for (t = current_templates->start; t < current_templates->end; ++t)
9215 if (t->opcode_modifier.isstring)
9216 break;
9217
9218 if (t < current_templates->end)
9219 {
9220 static templates aux_templates;
9221 bfd_boolean recheck;
9222
9223 aux_templates.start = t;
9224 for (; t < current_templates->end; ++t)
9225 if (!t->opcode_modifier.isstring)
9226 break;
9227 aux_templates.end = t;
9228
9229 /* Determine whether to re-check the first memory operand. */
9230 recheck = (aux_templates.start != current_templates->start
9231 || t != current_templates->end);
9232
9233 current_templates = &aux_templates;
9234
9235 if (recheck)
9236 {
9237 i.mem_operands = 0;
9238 if (i.memop1_string != NULL
9239 && i386_index_check (i.memop1_string) == 0)
9240 return 0;
9241 i.mem_operands = 1;
9242 }
9243 }
9244
9245 return 1;
9246 }
9247
9248 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
9249 on error. */
9250
9251 static int
9252 i386_att_operand (char *operand_string)
9253 {
9254 const reg_entry *r;
9255 char *end_op;
9256 char *op_string = operand_string;
9257
9258 if (is_space_char (*op_string))
9259 ++op_string;
9260
9261 /* We check for an absolute prefix (differentiating,
9262 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
9263 if (*op_string == ABSOLUTE_PREFIX)
9264 {
9265 ++op_string;
9266 if (is_space_char (*op_string))
9267 ++op_string;
9268 i.types[this_operand].bitfield.jumpabsolute = 1;
9269 }
9270
9271 /* Check if operand is a register. */
9272 if ((r = parse_register (op_string, &end_op)) != NULL)
9273 {
9274 i386_operand_type temp;
9275
9276 /* Check for a segment override by searching for ':' after a
9277 segment register. */
9278 op_string = end_op;
9279 if (is_space_char (*op_string))
9280 ++op_string;
9281 if (*op_string == ':'
9282 && (r->reg_type.bitfield.sreg2
9283 || r->reg_type.bitfield.sreg3))
9284 {
9285 switch (r->reg_num)
9286 {
9287 case 0:
9288 i.seg[i.mem_operands] = &es;
9289 break;
9290 case 1:
9291 i.seg[i.mem_operands] = &cs;
9292 break;
9293 case 2:
9294 i.seg[i.mem_operands] = &ss;
9295 break;
9296 case 3:
9297 i.seg[i.mem_operands] = &ds;
9298 break;
9299 case 4:
9300 i.seg[i.mem_operands] = &fs;
9301 break;
9302 case 5:
9303 i.seg[i.mem_operands] = &gs;
9304 break;
9305 }
9306
9307 /* Skip the ':' and whitespace. */
9308 ++op_string;
9309 if (is_space_char (*op_string))
9310 ++op_string;
9311
9312 if (!is_digit_char (*op_string)
9313 && !is_identifier_char (*op_string)
9314 && *op_string != '('
9315 && *op_string != ABSOLUTE_PREFIX)
9316 {
9317 as_bad (_("bad memory operand `%s'"), op_string);
9318 return 0;
9319 }
9320 /* Handle case of %es:*foo. */
9321 if (*op_string == ABSOLUTE_PREFIX)
9322 {
9323 ++op_string;
9324 if (is_space_char (*op_string))
9325 ++op_string;
9326 i.types[this_operand].bitfield.jumpabsolute = 1;
9327 }
9328 goto do_memory_reference;
9329 }
9330
9331 /* Handle vector operations. */
9332 if (*op_string == '{')
9333 {
9334 op_string = check_VecOperations (op_string, NULL);
9335 if (op_string == NULL)
9336 return 0;
9337 }
9338
9339 if (*op_string)
9340 {
9341 as_bad (_("junk `%s' after register"), op_string);
9342 return 0;
9343 }
9344 temp = r->reg_type;
9345 temp.bitfield.baseindex = 0;
9346 i.types[this_operand] = operand_type_or (i.types[this_operand],
9347 temp);
9348 i.types[this_operand].bitfield.unspecified = 0;
9349 i.op[this_operand].regs = r;
9350 i.reg_operands++;
9351 }
9352 else if (*op_string == REGISTER_PREFIX)
9353 {
9354 as_bad (_("bad register name `%s'"), op_string);
9355 return 0;
9356 }
9357 else if (*op_string == IMMEDIATE_PREFIX)
9358 {
9359 ++op_string;
9360 if (i.types[this_operand].bitfield.jumpabsolute)
9361 {
9362 as_bad (_("immediate operand illegal with absolute jump"));
9363 return 0;
9364 }
9365 if (!i386_immediate (op_string))
9366 return 0;
9367 }
9368 else if (RC_SAE_immediate (operand_string))
9369 {
9370 /* If it is a RC or SAE immediate, do nothing. */
9371 ;
9372 }
9373 else if (is_digit_char (*op_string)
9374 || is_identifier_char (*op_string)
9375 || *op_string == '"'
9376 || *op_string == '(')
9377 {
9378 /* This is a memory reference of some sort. */
9379 char *base_string;
9380
9381 /* Start and end of displacement string expression (if found). */
9382 char *displacement_string_start;
9383 char *displacement_string_end;
9384 char *vop_start;
9385
9386 do_memory_reference:
9387 if (i.mem_operands == 1 && !maybe_adjust_templates ())
9388 return 0;
9389 if ((i.mem_operands == 1
9390 && !current_templates->start->opcode_modifier.isstring)
9391 || i.mem_operands == 2)
9392 {
9393 as_bad (_("too many memory references for `%s'"),
9394 current_templates->start->name);
9395 return 0;
9396 }
9397
9398 /* Check for base index form. We detect the base index form by
9399 looking for an ')' at the end of the operand, searching
9400 for the '(' matching it, and finding a REGISTER_PREFIX or ','
9401 after the '('. */
9402 base_string = op_string + strlen (op_string);
9403
9404 /* Handle vector operations. */
9405 vop_start = strchr (op_string, '{');
9406 if (vop_start && vop_start < base_string)
9407 {
9408 if (check_VecOperations (vop_start, base_string) == NULL)
9409 return 0;
9410 base_string = vop_start;
9411 }
9412
9413 --base_string;
9414 if (is_space_char (*base_string))
9415 --base_string;
9416
9417 /* If we only have a displacement, set-up for it to be parsed later. */
9418 displacement_string_start = op_string;
9419 displacement_string_end = base_string + 1;
9420
9421 if (*base_string == ')')
9422 {
9423 char *temp_string;
9424 unsigned int parens_balanced = 1;
9425 /* We've already checked that the number of left & right ()'s are
9426 equal, so this loop will not be infinite. */
9427 do
9428 {
9429 base_string--;
9430 if (*base_string == ')')
9431 parens_balanced++;
9432 if (*base_string == '(')
9433 parens_balanced--;
9434 }
9435 while (parens_balanced);
9436
9437 temp_string = base_string;
9438
9439 /* Skip past '(' and whitespace. */
9440 ++base_string;
9441 if (is_space_char (*base_string))
9442 ++base_string;
9443
9444 if (*base_string == ','
9445 || ((i.base_reg = parse_register (base_string, &end_op))
9446 != NULL))
9447 {
9448 displacement_string_end = temp_string;
9449
9450 i.types[this_operand].bitfield.baseindex = 1;
9451
9452 if (i.base_reg)
9453 {
9454 base_string = end_op;
9455 if (is_space_char (*base_string))
9456 ++base_string;
9457 }
9458
9459 /* There may be an index reg or scale factor here. */
9460 if (*base_string == ',')
9461 {
9462 ++base_string;
9463 if (is_space_char (*base_string))
9464 ++base_string;
9465
9466 if ((i.index_reg = parse_register (base_string, &end_op))
9467 != NULL)
9468 {
9469 base_string = end_op;
9470 if (is_space_char (*base_string))
9471 ++base_string;
9472 if (*base_string == ',')
9473 {
9474 ++base_string;
9475 if (is_space_char (*base_string))
9476 ++base_string;
9477 }
9478 else if (*base_string != ')')
9479 {
9480 as_bad (_("expecting `,' or `)' "
9481 "after index register in `%s'"),
9482 operand_string);
9483 return 0;
9484 }
9485 }
9486 else if (*base_string == REGISTER_PREFIX)
9487 {
9488 end_op = strchr (base_string, ',');
9489 if (end_op)
9490 *end_op = '\0';
9491 as_bad (_("bad register name `%s'"), base_string);
9492 return 0;
9493 }
9494
9495 /* Check for scale factor. */
9496 if (*base_string != ')')
9497 {
9498 char *end_scale = i386_scale (base_string);
9499
9500 if (!end_scale)
9501 return 0;
9502
9503 base_string = end_scale;
9504 if (is_space_char (*base_string))
9505 ++base_string;
9506 if (*base_string != ')')
9507 {
9508 as_bad (_("expecting `)' "
9509 "after scale factor in `%s'"),
9510 operand_string);
9511 return 0;
9512 }
9513 }
9514 else if (!i.index_reg)
9515 {
9516 as_bad (_("expecting index register or scale factor "
9517 "after `,'; got '%c'"),
9518 *base_string);
9519 return 0;
9520 }
9521 }
9522 else if (*base_string != ')')
9523 {
9524 as_bad (_("expecting `,' or `)' "
9525 "after base register in `%s'"),
9526 operand_string);
9527 return 0;
9528 }
9529 }
9530 else if (*base_string == REGISTER_PREFIX)
9531 {
9532 end_op = strchr (base_string, ',');
9533 if (end_op)
9534 *end_op = '\0';
9535 as_bad (_("bad register name `%s'"), base_string);
9536 return 0;
9537 }
9538 }
9539
9540 /* If there's an expression beginning the operand, parse it,
9541 assuming displacement_string_start and
9542 displacement_string_end are meaningful. */
9543 if (displacement_string_start != displacement_string_end)
9544 {
9545 if (!i386_displacement (displacement_string_start,
9546 displacement_string_end))
9547 return 0;
9548 }
9549
9550 /* Special case for (%dx) while doing input/output op. */
9551 if (i.base_reg
9552 && operand_type_equal (&i.base_reg->reg_type,
9553 &reg16_inoutportreg)
9554 && i.index_reg == 0
9555 && i.log2_scale_factor == 0
9556 && i.seg[i.mem_operands] == 0
9557 && !operand_type_check (i.types[this_operand], disp))
9558 {
9559 i.types[this_operand] = inoutportreg;
9560 return 1;
9561 }
9562
9563 if (i386_index_check (operand_string) == 0)
9564 return 0;
9565 i.types[this_operand].bitfield.mem = 1;
9566 if (i.mem_operands == 0)
9567 i.memop1_string = xstrdup (operand_string);
9568 i.mem_operands++;
9569 }
9570 else
9571 {
9572 /* It's not a memory operand; argh! */
9573 as_bad (_("invalid char %s beginning operand %d `%s'"),
9574 output_invalid (*op_string),
9575 this_operand + 1,
9576 op_string);
9577 return 0;
9578 }
9579 return 1; /* Normal return. */
9580 }
9581 \f
9582 /* Calculate the maximum variable size (i.e., excluding fr_fix)
9583 that an rs_machine_dependent frag may reach. */
9584
9585 unsigned int
9586 i386_frag_max_var (fragS *frag)
9587 {
9588 /* The only relaxable frags are for jumps.
9589 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
9590 gas_assert (frag->fr_type == rs_machine_dependent);
9591 return TYPE_FROM_RELAX_STATE (frag->fr_subtype) == UNCOND_JUMP ? 4 : 5;
9592 }
9593
9594 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9595 static int
9596 elf_symbol_resolved_in_segment_p (symbolS *fr_symbol, offsetT fr_var)
9597 {
9598 /* STT_GNU_IFUNC symbol must go through PLT. */
9599 if ((symbol_get_bfdsym (fr_symbol)->flags
9600 & BSF_GNU_INDIRECT_FUNCTION) != 0)
9601 return 0;
9602
9603 if (!S_IS_EXTERNAL (fr_symbol))
9604 /* Symbol may be weak or local. */
9605 return !S_IS_WEAK (fr_symbol);
9606
9607 /* Global symbols with non-default visibility can't be preempted. */
9608 if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol)) != STV_DEFAULT)
9609 return 1;
9610
9611 if (fr_var != NO_RELOC)
9612 switch ((enum bfd_reloc_code_real) fr_var)
9613 {
9614 case BFD_RELOC_386_PLT32:
9615 case BFD_RELOC_X86_64_PLT32:
9616 /* Symbol with PLT relocation may be preempted. */
9617 return 0;
9618 default:
9619 abort ();
9620 }
9621
9622 /* Global symbols with default visibility in a shared library may be
9623 preempted by another definition. */
9624 return !shared;
9625 }
9626 #endif
9627
9628 /* md_estimate_size_before_relax()
9629
9630 Called just before relax() for rs_machine_dependent frags. The x86
9631 assembler uses these frags to handle variable size jump
9632 instructions.
9633
9634 Any symbol that is now undefined will not become defined.
9635 Return the correct fr_subtype in the frag.
9636 Return the initial "guess for variable size of frag" to caller.
9637 The guess is actually the growth beyond the fixed part. Whatever
9638 we do to grow the fixed or variable part contributes to our
9639 returned value. */
9640
9641 int
9642 md_estimate_size_before_relax (fragS *fragP, segT segment)
9643 {
9644 /* We've already got fragP->fr_subtype right; all we have to do is
9645 check for un-relaxable symbols. On an ELF system, we can't relax
9646 an externally visible symbol, because it may be overridden by a
9647 shared library. */
9648 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
9649 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9650 || (IS_ELF
9651 && !elf_symbol_resolved_in_segment_p (fragP->fr_symbol,
9652 fragP->fr_var))
9653 #endif
9654 #if defined (OBJ_COFF) && defined (TE_PE)
9655 || (OUTPUT_FLAVOR == bfd_target_coff_flavour
9656 && S_IS_WEAK (fragP->fr_symbol))
9657 #endif
9658 )
9659 {
9660 /* Symbol is undefined in this segment, or we need to keep a
9661 reloc so that weak symbols can be overridden. */
9662 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
9663 enum bfd_reloc_code_real reloc_type;
9664 unsigned char *opcode;
9665 int old_fr_fix;
9666
9667 if (fragP->fr_var != NO_RELOC)
9668 reloc_type = (enum bfd_reloc_code_real) fragP->fr_var;
9669 else if (size == 2)
9670 reloc_type = BFD_RELOC_16_PCREL;
9671 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9672 else if (need_plt32_p (fragP->fr_symbol))
9673 reloc_type = BFD_RELOC_X86_64_PLT32;
9674 #endif
9675 else
9676 reloc_type = BFD_RELOC_32_PCREL;
9677
9678 old_fr_fix = fragP->fr_fix;
9679 opcode = (unsigned char *) fragP->fr_opcode;
9680
9681 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
9682 {
9683 case UNCOND_JUMP:
9684 /* Make jmp (0xeb) a (d)word displacement jump. */
9685 opcode[0] = 0xe9;
9686 fragP->fr_fix += size;
9687 fix_new (fragP, old_fr_fix, size,
9688 fragP->fr_symbol,
9689 fragP->fr_offset, 1,
9690 reloc_type);
9691 break;
9692
9693 case COND_JUMP86:
9694 if (size == 2
9695 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
9696 {
9697 /* Negate the condition, and branch past an
9698 unconditional jump. */
9699 opcode[0] ^= 1;
9700 opcode[1] = 3;
9701 /* Insert an unconditional jump. */
9702 opcode[2] = 0xe9;
9703 /* We added two extra opcode bytes, and have a two byte
9704 offset. */
9705 fragP->fr_fix += 2 + 2;
9706 fix_new (fragP, old_fr_fix + 2, 2,
9707 fragP->fr_symbol,
9708 fragP->fr_offset, 1,
9709 reloc_type);
9710 break;
9711 }
9712 /* Fall through. */
9713
9714 case COND_JUMP:
9715 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
9716 {
9717 fixS *fixP;
9718
9719 fragP->fr_fix += 1;
9720 fixP = fix_new (fragP, old_fr_fix, 1,
9721 fragP->fr_symbol,
9722 fragP->fr_offset, 1,
9723 BFD_RELOC_8_PCREL);
9724 fixP->fx_signed = 1;
9725 break;
9726 }
9727
9728 /* This changes the byte-displacement jump 0x7N
9729 to the (d)word-displacement jump 0x0f,0x8N. */
9730 opcode[1] = opcode[0] + 0x10;
9731 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
9732 /* We've added an opcode byte. */
9733 fragP->fr_fix += 1 + size;
9734 fix_new (fragP, old_fr_fix + 1, size,
9735 fragP->fr_symbol,
9736 fragP->fr_offset, 1,
9737 reloc_type);
9738 break;
9739
9740 default:
9741 BAD_CASE (fragP->fr_subtype);
9742 break;
9743 }
9744 frag_wane (fragP);
9745 return fragP->fr_fix - old_fr_fix;
9746 }
9747
9748 /* Guess size depending on current relax state. Initially the relax
9749 state will correspond to a short jump and we return 1, because
9750 the variable part of the frag (the branch offset) is one byte
9751 long. However, we can relax a section more than once and in that
9752 case we must either set fr_subtype back to the unrelaxed state,
9753 or return the value for the appropriate branch. */
9754 return md_relax_table[fragP->fr_subtype].rlx_length;
9755 }
9756
9757 /* Called after relax() is finished.
9758
9759 In: Address of frag.
9760 fr_type == rs_machine_dependent.
9761 fr_subtype is what the address relaxed to.
9762
9763 Out: Any fixSs and constants are set up.
9764 Caller will turn frag into a ".space 0". */
9765
9766 void
9767 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT sec ATTRIBUTE_UNUSED,
9768 fragS *fragP)
9769 {
9770 unsigned char *opcode;
9771 unsigned char *where_to_put_displacement = NULL;
9772 offsetT target_address;
9773 offsetT opcode_address;
9774 unsigned int extension = 0;
9775 offsetT displacement_from_opcode_start;
9776
9777 opcode = (unsigned char *) fragP->fr_opcode;
9778
9779 /* Address we want to reach in file space. */
9780 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
9781
9782 /* Address opcode resides at in file space. */
9783 opcode_address = fragP->fr_address + fragP->fr_fix;
9784
9785 /* Displacement from opcode start to fill into instruction. */
9786 displacement_from_opcode_start = target_address - opcode_address;
9787
9788 if ((fragP->fr_subtype & BIG) == 0)
9789 {
9790 /* Don't have to change opcode. */
9791 extension = 1; /* 1 opcode + 1 displacement */
9792 where_to_put_displacement = &opcode[1];
9793 }
9794 else
9795 {
9796 if (no_cond_jump_promotion
9797 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
9798 as_warn_where (fragP->fr_file, fragP->fr_line,
9799 _("long jump required"));
9800
9801 switch (fragP->fr_subtype)
9802 {
9803 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
9804 extension = 4; /* 1 opcode + 4 displacement */
9805 opcode[0] = 0xe9;
9806 where_to_put_displacement = &opcode[1];
9807 break;
9808
9809 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
9810 extension = 2; /* 1 opcode + 2 displacement */
9811 opcode[0] = 0xe9;
9812 where_to_put_displacement = &opcode[1];
9813 break;
9814
9815 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
9816 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
9817 extension = 5; /* 2 opcode + 4 displacement */
9818 opcode[1] = opcode[0] + 0x10;
9819 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
9820 where_to_put_displacement = &opcode[2];
9821 break;
9822
9823 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
9824 extension = 3; /* 2 opcode + 2 displacement */
9825 opcode[1] = opcode[0] + 0x10;
9826 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
9827 where_to_put_displacement = &opcode[2];
9828 break;
9829
9830 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
9831 extension = 4;
9832 opcode[0] ^= 1;
9833 opcode[1] = 3;
9834 opcode[2] = 0xe9;
9835 where_to_put_displacement = &opcode[3];
9836 break;
9837
9838 default:
9839 BAD_CASE (fragP->fr_subtype);
9840 break;
9841 }
9842 }
9843
9844 /* If size if less then four we are sure that the operand fits,
9845 but if it's 4, then it could be that the displacement is larger
9846 then -/+ 2GB. */
9847 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
9848 && object_64bit
9849 && ((addressT) (displacement_from_opcode_start - extension
9850 + ((addressT) 1 << 31))
9851 > (((addressT) 2 << 31) - 1)))
9852 {
9853 as_bad_where (fragP->fr_file, fragP->fr_line,
9854 _("jump target out of range"));
9855 /* Make us emit 0. */
9856 displacement_from_opcode_start = extension;
9857 }
9858 /* Now put displacement after opcode. */
9859 md_number_to_chars ((char *) where_to_put_displacement,
9860 (valueT) (displacement_from_opcode_start - extension),
9861 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
9862 fragP->fr_fix += extension;
9863 }
9864 \f
9865 /* Apply a fixup (fixP) to segment data, once it has been determined
9866 by our caller that we have all the info we need to fix it up.
9867
9868 Parameter valP is the pointer to the value of the bits.
9869
9870 On the 386, immediates, displacements, and data pointers are all in
9871 the same (little-endian) format, so we don't need to care about which
9872 we are handling. */
9873
9874 void
9875 md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
9876 {
9877 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
9878 valueT value = *valP;
9879
9880 #if !defined (TE_Mach)
9881 if (fixP->fx_pcrel)
9882 {
9883 switch (fixP->fx_r_type)
9884 {
9885 default:
9886 break;
9887
9888 case BFD_RELOC_64:
9889 fixP->fx_r_type = BFD_RELOC_64_PCREL;
9890 break;
9891 case BFD_RELOC_32:
9892 case BFD_RELOC_X86_64_32S:
9893 fixP->fx_r_type = BFD_RELOC_32_PCREL;
9894 break;
9895 case BFD_RELOC_16:
9896 fixP->fx_r_type = BFD_RELOC_16_PCREL;
9897 break;
9898 case BFD_RELOC_8:
9899 fixP->fx_r_type = BFD_RELOC_8_PCREL;
9900 break;
9901 }
9902 }
9903
9904 if (fixP->fx_addsy != NULL
9905 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
9906 || fixP->fx_r_type == BFD_RELOC_64_PCREL
9907 || fixP->fx_r_type == BFD_RELOC_16_PCREL
9908 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
9909 && !use_rela_relocations)
9910 {
9911 /* This is a hack. There should be a better way to handle this.
9912 This covers for the fact that bfd_install_relocation will
9913 subtract the current location (for partial_inplace, PC relative
9914 relocations); see more below. */
9915 #ifndef OBJ_AOUT
9916 if (IS_ELF
9917 #ifdef TE_PE
9918 || OUTPUT_FLAVOR == bfd_target_coff_flavour
9919 #endif
9920 )
9921 value += fixP->fx_where + fixP->fx_frag->fr_address;
9922 #endif
9923 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9924 if (IS_ELF)
9925 {
9926 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
9927
9928 if ((sym_seg == seg
9929 || (symbol_section_p (fixP->fx_addsy)
9930 && sym_seg != absolute_section))
9931 && !generic_force_reloc (fixP))
9932 {
9933 /* Yes, we add the values in twice. This is because
9934 bfd_install_relocation subtracts them out again. I think
9935 bfd_install_relocation is broken, but I don't dare change
9936 it. FIXME. */
9937 value += fixP->fx_where + fixP->fx_frag->fr_address;
9938 }
9939 }
9940 #endif
9941 #if defined (OBJ_COFF) && defined (TE_PE)
9942 /* For some reason, the PE format does not store a
9943 section address offset for a PC relative symbol. */
9944 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
9945 || S_IS_WEAK (fixP->fx_addsy))
9946 value += md_pcrel_from (fixP);
9947 #endif
9948 }
9949 #if defined (OBJ_COFF) && defined (TE_PE)
9950 if (fixP->fx_addsy != NULL
9951 && S_IS_WEAK (fixP->fx_addsy)
9952 /* PR 16858: Do not modify weak function references. */
9953 && ! fixP->fx_pcrel)
9954 {
9955 #if !defined (TE_PEP)
9956 /* For x86 PE weak function symbols are neither PC-relative
9957 nor do they set S_IS_FUNCTION. So the only reliable way
9958 to detect them is to check the flags of their containing
9959 section. */
9960 if (S_GET_SEGMENT (fixP->fx_addsy) != NULL
9961 && S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_CODE)
9962 ;
9963 else
9964 #endif
9965 value -= S_GET_VALUE (fixP->fx_addsy);
9966 }
9967 #endif
9968
9969 /* Fix a few things - the dynamic linker expects certain values here,
9970 and we must not disappoint it. */
9971 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9972 if (IS_ELF && fixP->fx_addsy)
9973 switch (fixP->fx_r_type)
9974 {
9975 case BFD_RELOC_386_PLT32:
9976 case BFD_RELOC_X86_64_PLT32:
9977 /* Make the jump instruction point to the address of the operand. At
9978 runtime we merely add the offset to the actual PLT entry. */
9979 value = -4;
9980 break;
9981
9982 case BFD_RELOC_386_TLS_GD:
9983 case BFD_RELOC_386_TLS_LDM:
9984 case BFD_RELOC_386_TLS_IE_32:
9985 case BFD_RELOC_386_TLS_IE:
9986 case BFD_RELOC_386_TLS_GOTIE:
9987 case BFD_RELOC_386_TLS_GOTDESC:
9988 case BFD_RELOC_X86_64_TLSGD:
9989 case BFD_RELOC_X86_64_TLSLD:
9990 case BFD_RELOC_X86_64_GOTTPOFF:
9991 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
9992 value = 0; /* Fully resolved at runtime. No addend. */
9993 /* Fallthrough */
9994 case BFD_RELOC_386_TLS_LE:
9995 case BFD_RELOC_386_TLS_LDO_32:
9996 case BFD_RELOC_386_TLS_LE_32:
9997 case BFD_RELOC_X86_64_DTPOFF32:
9998 case BFD_RELOC_X86_64_DTPOFF64:
9999 case BFD_RELOC_X86_64_TPOFF32:
10000 case BFD_RELOC_X86_64_TPOFF64:
10001 S_SET_THREAD_LOCAL (fixP->fx_addsy);
10002 break;
10003
10004 case BFD_RELOC_386_TLS_DESC_CALL:
10005 case BFD_RELOC_X86_64_TLSDESC_CALL:
10006 value = 0; /* Fully resolved at runtime. No addend. */
10007 S_SET_THREAD_LOCAL (fixP->fx_addsy);
10008 fixP->fx_done = 0;
10009 return;
10010
10011 case BFD_RELOC_VTABLE_INHERIT:
10012 case BFD_RELOC_VTABLE_ENTRY:
10013 fixP->fx_done = 0;
10014 return;
10015
10016 default:
10017 break;
10018 }
10019 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
10020 *valP = value;
10021 #endif /* !defined (TE_Mach) */
10022
10023 /* Are we finished with this relocation now? */
10024 if (fixP->fx_addsy == NULL)
10025 fixP->fx_done = 1;
10026 #if defined (OBJ_COFF) && defined (TE_PE)
10027 else if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy))
10028 {
10029 fixP->fx_done = 0;
10030 /* Remember value for tc_gen_reloc. */
10031 fixP->fx_addnumber = value;
10032 /* Clear out the frag for now. */
10033 value = 0;
10034 }
10035 #endif
10036 else if (use_rela_relocations)
10037 {
10038 fixP->fx_no_overflow = 1;
10039 /* Remember value for tc_gen_reloc. */
10040 fixP->fx_addnumber = value;
10041 value = 0;
10042 }
10043
10044 md_number_to_chars (p, value, fixP->fx_size);
10045 }
10046 \f
10047 const char *
10048 md_atof (int type, char *litP, int *sizeP)
10049 {
10050 /* This outputs the LITTLENUMs in REVERSE order;
10051 in accord with the bigendian 386. */
10052 return ieee_md_atof (type, litP, sizeP, FALSE);
10053 }
10054 \f
10055 static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
10056
10057 static char *
10058 output_invalid (int c)
10059 {
10060 if (ISPRINT (c))
10061 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
10062 "'%c'", c);
10063 else
10064 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
10065 "(0x%x)", (unsigned char) c);
10066 return output_invalid_buf;
10067 }
10068
10069 /* REG_STRING starts *before* REGISTER_PREFIX. */
10070
10071 static const reg_entry *
10072 parse_real_register (char *reg_string, char **end_op)
10073 {
10074 char *s = reg_string;
10075 char *p;
10076 char reg_name_given[MAX_REG_NAME_SIZE + 1];
10077 const reg_entry *r;
10078
10079 /* Skip possible REGISTER_PREFIX and possible whitespace. */
10080 if (*s == REGISTER_PREFIX)
10081 ++s;
10082
10083 if (is_space_char (*s))
10084 ++s;
10085
10086 p = reg_name_given;
10087 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
10088 {
10089 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
10090 return (const reg_entry *) NULL;
10091 s++;
10092 }
10093
10094 /* For naked regs, make sure that we are not dealing with an identifier.
10095 This prevents confusing an identifier like `eax_var' with register
10096 `eax'. */
10097 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
10098 return (const reg_entry *) NULL;
10099
10100 *end_op = s;
10101
10102 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
10103
10104 /* Handle floating point regs, allowing spaces in the (i) part. */
10105 if (r == i386_regtab /* %st is first entry of table */)
10106 {
10107 if (is_space_char (*s))
10108 ++s;
10109 if (*s == '(')
10110 {
10111 ++s;
10112 if (is_space_char (*s))
10113 ++s;
10114 if (*s >= '0' && *s <= '7')
10115 {
10116 int fpr = *s - '0';
10117 ++s;
10118 if (is_space_char (*s))
10119 ++s;
10120 if (*s == ')')
10121 {
10122 *end_op = s + 1;
10123 r = (const reg_entry *) hash_find (reg_hash, "st(0)");
10124 know (r);
10125 return r + fpr;
10126 }
10127 }
10128 /* We have "%st(" then garbage. */
10129 return (const reg_entry *) NULL;
10130 }
10131 }
10132
10133 if (r == NULL || allow_pseudo_reg)
10134 return r;
10135
10136 if (operand_type_all_zero (&r->reg_type))
10137 return (const reg_entry *) NULL;
10138
10139 if ((r->reg_type.bitfield.dword
10140 || r->reg_type.bitfield.sreg3
10141 || r->reg_type.bitfield.control
10142 || r->reg_type.bitfield.debug
10143 || r->reg_type.bitfield.test)
10144 && !cpu_arch_flags.bitfield.cpui386)
10145 return (const reg_entry *) NULL;
10146
10147 if (r->reg_type.bitfield.tbyte
10148 && !cpu_arch_flags.bitfield.cpu8087
10149 && !cpu_arch_flags.bitfield.cpu287
10150 && !cpu_arch_flags.bitfield.cpu387)
10151 return (const reg_entry *) NULL;
10152
10153 if (r->reg_type.bitfield.regmmx && !cpu_arch_flags.bitfield.cpuregmmx)
10154 return (const reg_entry *) NULL;
10155
10156 if (r->reg_type.bitfield.xmmword && !cpu_arch_flags.bitfield.cpuregxmm)
10157 return (const reg_entry *) NULL;
10158
10159 if (r->reg_type.bitfield.ymmword && !cpu_arch_flags.bitfield.cpuregymm)
10160 return (const reg_entry *) NULL;
10161
10162 if (r->reg_type.bitfield.zmmword && !cpu_arch_flags.bitfield.cpuregzmm)
10163 return (const reg_entry *) NULL;
10164
10165 if (r->reg_type.bitfield.regmask
10166 && !cpu_arch_flags.bitfield.cpuregmask)
10167 return (const reg_entry *) NULL;
10168
10169 /* Don't allow fake index register unless allow_index_reg isn't 0. */
10170 if (!allow_index_reg
10171 && (r->reg_num == RegEiz || r->reg_num == RegRiz))
10172 return (const reg_entry *) NULL;
10173
10174 /* Upper 16 vector register is only available with VREX in 64bit
10175 mode. */
10176 if ((r->reg_flags & RegVRex))
10177 {
10178 if (i.vec_encoding == vex_encoding_default)
10179 i.vec_encoding = vex_encoding_evex;
10180
10181 if (!cpu_arch_flags.bitfield.cpuvrex
10182 || i.vec_encoding != vex_encoding_evex
10183 || flag_code != CODE_64BIT)
10184 return (const reg_entry *) NULL;
10185 }
10186
10187 if (((r->reg_flags & (RegRex64 | RegRex))
10188 || r->reg_type.bitfield.qword)
10189 && (!cpu_arch_flags.bitfield.cpulm
10190 || !operand_type_equal (&r->reg_type, &control))
10191 && flag_code != CODE_64BIT)
10192 return (const reg_entry *) NULL;
10193
10194 if (r->reg_type.bitfield.sreg3 && r->reg_num == RegFlat && !intel_syntax)
10195 return (const reg_entry *) NULL;
10196
10197 return r;
10198 }
10199
10200 /* REG_STRING starts *before* REGISTER_PREFIX. */
10201
10202 static const reg_entry *
10203 parse_register (char *reg_string, char **end_op)
10204 {
10205 const reg_entry *r;
10206
10207 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
10208 r = parse_real_register (reg_string, end_op);
10209 else
10210 r = NULL;
10211 if (!r)
10212 {
10213 char *save = input_line_pointer;
10214 char c;
10215 symbolS *symbolP;
10216
10217 input_line_pointer = reg_string;
10218 c = get_symbol_name (&reg_string);
10219 symbolP = symbol_find (reg_string);
10220 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
10221 {
10222 const expressionS *e = symbol_get_value_expression (symbolP);
10223
10224 know (e->X_op == O_register);
10225 know (e->X_add_number >= 0
10226 && (valueT) e->X_add_number < i386_regtab_size);
10227 r = i386_regtab + e->X_add_number;
10228 if ((r->reg_flags & RegVRex))
10229 i.vec_encoding = vex_encoding_evex;
10230 *end_op = input_line_pointer;
10231 }
10232 *input_line_pointer = c;
10233 input_line_pointer = save;
10234 }
10235 return r;
10236 }
10237
10238 int
10239 i386_parse_name (char *name, expressionS *e, char *nextcharP)
10240 {
10241 const reg_entry *r;
10242 char *end = input_line_pointer;
10243
10244 *end = *nextcharP;
10245 r = parse_register (name, &input_line_pointer);
10246 if (r && end <= input_line_pointer)
10247 {
10248 *nextcharP = *input_line_pointer;
10249 *input_line_pointer = 0;
10250 e->X_op = O_register;
10251 e->X_add_number = r - i386_regtab;
10252 return 1;
10253 }
10254 input_line_pointer = end;
10255 *end = 0;
10256 return intel_syntax ? i386_intel_parse_name (name, e) : 0;
10257 }
10258
10259 void
10260 md_operand (expressionS *e)
10261 {
10262 char *end;
10263 const reg_entry *r;
10264
10265 switch (*input_line_pointer)
10266 {
10267 case REGISTER_PREFIX:
10268 r = parse_real_register (input_line_pointer, &end);
10269 if (r)
10270 {
10271 e->X_op = O_register;
10272 e->X_add_number = r - i386_regtab;
10273 input_line_pointer = end;
10274 }
10275 break;
10276
10277 case '[':
10278 gas_assert (intel_syntax);
10279 end = input_line_pointer++;
10280 expression (e);
10281 if (*input_line_pointer == ']')
10282 {
10283 ++input_line_pointer;
10284 e->X_op_symbol = make_expr_symbol (e);
10285 e->X_add_symbol = NULL;
10286 e->X_add_number = 0;
10287 e->X_op = O_index;
10288 }
10289 else
10290 {
10291 e->X_op = O_absent;
10292 input_line_pointer = end;
10293 }
10294 break;
10295 }
10296 }
10297
10298 \f
10299 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10300 const char *md_shortopts = "kVQ:sqnO::";
10301 #else
10302 const char *md_shortopts = "qnO::";
10303 #endif
10304
10305 #define OPTION_32 (OPTION_MD_BASE + 0)
10306 #define OPTION_64 (OPTION_MD_BASE + 1)
10307 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
10308 #define OPTION_MARCH (OPTION_MD_BASE + 3)
10309 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
10310 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
10311 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
10312 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
10313 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
10314 #define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 9)
10315 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
10316 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
10317 #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
10318 #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
10319 #define OPTION_X32 (OPTION_MD_BASE + 14)
10320 #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
10321 #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
10322 #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
10323 #define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
10324 #define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
10325 #define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
10326 #define OPTION_MSHARED (OPTION_MD_BASE + 21)
10327 #define OPTION_MAMD64 (OPTION_MD_BASE + 22)
10328 #define OPTION_MINTEL64 (OPTION_MD_BASE + 23)
10329 #define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24)
10330
10331 struct option md_longopts[] =
10332 {
10333 {"32", no_argument, NULL, OPTION_32},
10334 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10335 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
10336 {"64", no_argument, NULL, OPTION_64},
10337 #endif
10338 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10339 {"x32", no_argument, NULL, OPTION_X32},
10340 {"mshared", no_argument, NULL, OPTION_MSHARED},
10341 #endif
10342 {"divide", no_argument, NULL, OPTION_DIVIDE},
10343 {"march", required_argument, NULL, OPTION_MARCH},
10344 {"mtune", required_argument, NULL, OPTION_MTUNE},
10345 {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC},
10346 {"msyntax", required_argument, NULL, OPTION_MSYNTAX},
10347 {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG},
10348 {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG},
10349 {"msse2avx", no_argument, NULL, OPTION_MSSE2AVX},
10350 {"msse-check", required_argument, NULL, OPTION_MSSE_CHECK},
10351 {"moperand-check", required_argument, NULL, OPTION_MOPERAND_CHECK},
10352 {"mavxscalar", required_argument, NULL, OPTION_MAVXSCALAR},
10353 {"madd-bnd-prefix", no_argument, NULL, OPTION_MADD_BND_PREFIX},
10354 {"mevexlig", required_argument, NULL, OPTION_MEVEXLIG},
10355 {"mevexwig", required_argument, NULL, OPTION_MEVEXWIG},
10356 # if defined (TE_PE) || defined (TE_PEP)
10357 {"mbig-obj", no_argument, NULL, OPTION_MBIG_OBJ},
10358 #endif
10359 {"momit-lock-prefix", required_argument, NULL, OPTION_MOMIT_LOCK_PREFIX},
10360 {"mfence-as-lock-add", required_argument, NULL, OPTION_MFENCE_AS_LOCK_ADD},
10361 {"mrelax-relocations", required_argument, NULL, OPTION_MRELAX_RELOCATIONS},
10362 {"mevexrcig", required_argument, NULL, OPTION_MEVEXRCIG},
10363 {"mamd64", no_argument, NULL, OPTION_MAMD64},
10364 {"mintel64", no_argument, NULL, OPTION_MINTEL64},
10365 {NULL, no_argument, NULL, 0}
10366 };
10367 size_t md_longopts_size = sizeof (md_longopts);
10368
10369 int
10370 md_parse_option (int c, const char *arg)
10371 {
10372 unsigned int j;
10373 char *arch, *next, *saved;
10374
10375 switch (c)
10376 {
10377 case 'n':
10378 optimize_align_code = 0;
10379 break;
10380
10381 case 'q':
10382 quiet_warnings = 1;
10383 break;
10384
10385 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10386 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
10387 should be emitted or not. FIXME: Not implemented. */
10388 case 'Q':
10389 break;
10390
10391 /* -V: SVR4 argument to print version ID. */
10392 case 'V':
10393 print_version_id ();
10394 break;
10395
10396 /* -k: Ignore for FreeBSD compatibility. */
10397 case 'k':
10398 break;
10399
10400 case 's':
10401 /* -s: On i386 Solaris, this tells the native assembler to use
10402 .stab instead of .stab.excl. We always use .stab anyhow. */
10403 break;
10404
10405 case OPTION_MSHARED:
10406 shared = 1;
10407 break;
10408 #endif
10409 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10410 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
10411 case OPTION_64:
10412 {
10413 const char **list, **l;
10414
10415 list = bfd_target_list ();
10416 for (l = list; *l != NULL; l++)
10417 if (CONST_STRNEQ (*l, "elf64-x86-64")
10418 || strcmp (*l, "coff-x86-64") == 0
10419 || strcmp (*l, "pe-x86-64") == 0
10420 || strcmp (*l, "pei-x86-64") == 0
10421 || strcmp (*l, "mach-o-x86-64") == 0)
10422 {
10423 default_arch = "x86_64";
10424 break;
10425 }
10426 if (*l == NULL)
10427 as_fatal (_("no compiled in support for x86_64"));
10428 free (list);
10429 }
10430 break;
10431 #endif
10432
10433 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10434 case OPTION_X32:
10435 if (IS_ELF)
10436 {
10437 const char **list, **l;
10438
10439 list = bfd_target_list ();
10440 for (l = list; *l != NULL; l++)
10441 if (CONST_STRNEQ (*l, "elf32-x86-64"))
10442 {
10443 default_arch = "x86_64:32";
10444 break;
10445 }
10446 if (*l == NULL)
10447 as_fatal (_("no compiled in support for 32bit x86_64"));
10448 free (list);
10449 }
10450 else
10451 as_fatal (_("32bit x86_64 is only supported for ELF"));
10452 break;
10453 #endif
10454
10455 case OPTION_32:
10456 default_arch = "i386";
10457 break;
10458
10459 case OPTION_DIVIDE:
10460 #ifdef SVR4_COMMENT_CHARS
10461 {
10462 char *n, *t;
10463 const char *s;
10464
10465 n = XNEWVEC (char, strlen (i386_comment_chars) + 1);
10466 t = n;
10467 for (s = i386_comment_chars; *s != '\0'; s++)
10468 if (*s != '/')
10469 *t++ = *s;
10470 *t = '\0';
10471 i386_comment_chars = n;
10472 }
10473 #endif
10474 break;
10475
10476 case OPTION_MARCH:
10477 saved = xstrdup (arg);
10478 arch = saved;
10479 /* Allow -march=+nosse. */
10480 if (*arch == '+')
10481 arch++;
10482 do
10483 {
10484 if (*arch == '.')
10485 as_fatal (_("invalid -march= option: `%s'"), arg);
10486 next = strchr (arch, '+');
10487 if (next)
10488 *next++ = '\0';
10489 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
10490 {
10491 if (strcmp (arch, cpu_arch [j].name) == 0)
10492 {
10493 /* Processor. */
10494 if (! cpu_arch[j].flags.bitfield.cpui386)
10495 continue;
10496
10497 cpu_arch_name = cpu_arch[j].name;
10498 cpu_sub_arch_name = NULL;
10499 cpu_arch_flags = cpu_arch[j].flags;
10500 cpu_arch_isa = cpu_arch[j].type;
10501 cpu_arch_isa_flags = cpu_arch[j].flags;
10502 if (!cpu_arch_tune_set)
10503 {
10504 cpu_arch_tune = cpu_arch_isa;
10505 cpu_arch_tune_flags = cpu_arch_isa_flags;
10506 }
10507 break;
10508 }
10509 else if (*cpu_arch [j].name == '.'
10510 && strcmp (arch, cpu_arch [j].name + 1) == 0)
10511 {
10512 /* ISA extension. */
10513 i386_cpu_flags flags;
10514
10515 flags = cpu_flags_or (cpu_arch_flags,
10516 cpu_arch[j].flags);
10517
10518 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
10519 {
10520 if (cpu_sub_arch_name)
10521 {
10522 char *name = cpu_sub_arch_name;
10523 cpu_sub_arch_name = concat (name,
10524 cpu_arch[j].name,
10525 (const char *) NULL);
10526 free (name);
10527 }
10528 else
10529 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
10530 cpu_arch_flags = flags;
10531 cpu_arch_isa_flags = flags;
10532 }
10533 else
10534 cpu_arch_isa_flags
10535 = cpu_flags_or (cpu_arch_isa_flags,
10536 cpu_arch[j].flags);
10537 break;
10538 }
10539 }
10540
10541 if (j >= ARRAY_SIZE (cpu_arch))
10542 {
10543 /* Disable an ISA extension. */
10544 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
10545 if (strcmp (arch, cpu_noarch [j].name) == 0)
10546 {
10547 i386_cpu_flags flags;
10548
10549 flags = cpu_flags_and_not (cpu_arch_flags,
10550 cpu_noarch[j].flags);
10551 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
10552 {
10553 if (cpu_sub_arch_name)
10554 {
10555 char *name = cpu_sub_arch_name;
10556 cpu_sub_arch_name = concat (arch,
10557 (const char *) NULL);
10558 free (name);
10559 }
10560 else
10561 cpu_sub_arch_name = xstrdup (arch);
10562 cpu_arch_flags = flags;
10563 cpu_arch_isa_flags = flags;
10564 }
10565 break;
10566 }
10567
10568 if (j >= ARRAY_SIZE (cpu_noarch))
10569 j = ARRAY_SIZE (cpu_arch);
10570 }
10571
10572 if (j >= ARRAY_SIZE (cpu_arch))
10573 as_fatal (_("invalid -march= option: `%s'"), arg);
10574
10575 arch = next;
10576 }
10577 while (next != NULL);
10578 free (saved);
10579 break;
10580
10581 case OPTION_MTUNE:
10582 if (*arg == '.')
10583 as_fatal (_("invalid -mtune= option: `%s'"), arg);
10584 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
10585 {
10586 if (strcmp (arg, cpu_arch [j].name) == 0)
10587 {
10588 cpu_arch_tune_set = 1;
10589 cpu_arch_tune = cpu_arch [j].type;
10590 cpu_arch_tune_flags = cpu_arch[j].flags;
10591 break;
10592 }
10593 }
10594 if (j >= ARRAY_SIZE (cpu_arch))
10595 as_fatal (_("invalid -mtune= option: `%s'"), arg);
10596 break;
10597
10598 case OPTION_MMNEMONIC:
10599 if (strcasecmp (arg, "att") == 0)
10600 intel_mnemonic = 0;
10601 else if (strcasecmp (arg, "intel") == 0)
10602 intel_mnemonic = 1;
10603 else
10604 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg);
10605 break;
10606
10607 case OPTION_MSYNTAX:
10608 if (strcasecmp (arg, "att") == 0)
10609 intel_syntax = 0;
10610 else if (strcasecmp (arg, "intel") == 0)
10611 intel_syntax = 1;
10612 else
10613 as_fatal (_("invalid -msyntax= option: `%s'"), arg);
10614 break;
10615
10616 case OPTION_MINDEX_REG:
10617 allow_index_reg = 1;
10618 break;
10619
10620 case OPTION_MNAKED_REG:
10621 allow_naked_reg = 1;
10622 break;
10623
10624 case OPTION_MSSE2AVX:
10625 sse2avx = 1;
10626 break;
10627
10628 case OPTION_MSSE_CHECK:
10629 if (strcasecmp (arg, "error") == 0)
10630 sse_check = check_error;
10631 else if (strcasecmp (arg, "warning") == 0)
10632 sse_check = check_warning;
10633 else if (strcasecmp (arg, "none") == 0)
10634 sse_check = check_none;
10635 else
10636 as_fatal (_("invalid -msse-check= option: `%s'"), arg);
10637 break;
10638
10639 case OPTION_MOPERAND_CHECK:
10640 if (strcasecmp (arg, "error") == 0)
10641 operand_check = check_error;
10642 else if (strcasecmp (arg, "warning") == 0)
10643 operand_check = check_warning;
10644 else if (strcasecmp (arg, "none") == 0)
10645 operand_check = check_none;
10646 else
10647 as_fatal (_("invalid -moperand-check= option: `%s'"), arg);
10648 break;
10649
10650 case OPTION_MAVXSCALAR:
10651 if (strcasecmp (arg, "128") == 0)
10652 avxscalar = vex128;
10653 else if (strcasecmp (arg, "256") == 0)
10654 avxscalar = vex256;
10655 else
10656 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg);
10657 break;
10658
10659 case OPTION_MADD_BND_PREFIX:
10660 add_bnd_prefix = 1;
10661 break;
10662
10663 case OPTION_MEVEXLIG:
10664 if (strcmp (arg, "128") == 0)
10665 evexlig = evexl128;
10666 else if (strcmp (arg, "256") == 0)
10667 evexlig = evexl256;
10668 else if (strcmp (arg, "512") == 0)
10669 evexlig = evexl512;
10670 else
10671 as_fatal (_("invalid -mevexlig= option: `%s'"), arg);
10672 break;
10673
10674 case OPTION_MEVEXRCIG:
10675 if (strcmp (arg, "rne") == 0)
10676 evexrcig = rne;
10677 else if (strcmp (arg, "rd") == 0)
10678 evexrcig = rd;
10679 else if (strcmp (arg, "ru") == 0)
10680 evexrcig = ru;
10681 else if (strcmp (arg, "rz") == 0)
10682 evexrcig = rz;
10683 else
10684 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg);
10685 break;
10686
10687 case OPTION_MEVEXWIG:
10688 if (strcmp (arg, "0") == 0)
10689 evexwig = evexw0;
10690 else if (strcmp (arg, "1") == 0)
10691 evexwig = evexw1;
10692 else
10693 as_fatal (_("invalid -mevexwig= option: `%s'"), arg);
10694 break;
10695
10696 # if defined (TE_PE) || defined (TE_PEP)
10697 case OPTION_MBIG_OBJ:
10698 use_big_obj = 1;
10699 break;
10700 #endif
10701
10702 case OPTION_MOMIT_LOCK_PREFIX:
10703 if (strcasecmp (arg, "yes") == 0)
10704 omit_lock_prefix = 1;
10705 else if (strcasecmp (arg, "no") == 0)
10706 omit_lock_prefix = 0;
10707 else
10708 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg);
10709 break;
10710
10711 case OPTION_MFENCE_AS_LOCK_ADD:
10712 if (strcasecmp (arg, "yes") == 0)
10713 avoid_fence = 1;
10714 else if (strcasecmp (arg, "no") == 0)
10715 avoid_fence = 0;
10716 else
10717 as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg);
10718 break;
10719
10720 case OPTION_MRELAX_RELOCATIONS:
10721 if (strcasecmp (arg, "yes") == 0)
10722 generate_relax_relocations = 1;
10723 else if (strcasecmp (arg, "no") == 0)
10724 generate_relax_relocations = 0;
10725 else
10726 as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg);
10727 break;
10728
10729 case OPTION_MAMD64:
10730 intel64 = 0;
10731 break;
10732
10733 case OPTION_MINTEL64:
10734 intel64 = 1;
10735 break;
10736
10737 case 'O':
10738 if (arg == NULL)
10739 {
10740 optimize = 1;
10741 /* Turn off -Os. */
10742 optimize_for_space = 0;
10743 }
10744 else if (*arg == 's')
10745 {
10746 optimize_for_space = 1;
10747 /* Turn on all encoding optimizations. */
10748 optimize = -1;
10749 }
10750 else
10751 {
10752 optimize = atoi (arg);
10753 /* Turn off -Os. */
10754 optimize_for_space = 0;
10755 }
10756 break;
10757
10758 default:
10759 return 0;
10760 }
10761 return 1;
10762 }
10763
10764 #define MESSAGE_TEMPLATE \
10765 " "
10766
10767 static char *
10768 output_message (FILE *stream, char *p, char *message, char *start,
10769 int *left_p, const char *name, int len)
10770 {
10771 int size = sizeof (MESSAGE_TEMPLATE);
10772 int left = *left_p;
10773
10774 /* Reserve 2 spaces for ", " or ",\0" */
10775 left -= len + 2;
10776
10777 /* Check if there is any room. */
10778 if (left >= 0)
10779 {
10780 if (p != start)
10781 {
10782 *p++ = ',';
10783 *p++ = ' ';
10784 }
10785 p = mempcpy (p, name, len);
10786 }
10787 else
10788 {
10789 /* Output the current message now and start a new one. */
10790 *p++ = ',';
10791 *p = '\0';
10792 fprintf (stream, "%s\n", message);
10793 p = start;
10794 left = size - (start - message) - len - 2;
10795
10796 gas_assert (left >= 0);
10797
10798 p = mempcpy (p, name, len);
10799 }
10800
10801 *left_p = left;
10802 return p;
10803 }
10804
10805 static void
10806 show_arch (FILE *stream, int ext, int check)
10807 {
10808 static char message[] = MESSAGE_TEMPLATE;
10809 char *start = message + 27;
10810 char *p;
10811 int size = sizeof (MESSAGE_TEMPLATE);
10812 int left;
10813 const char *name;
10814 int len;
10815 unsigned int j;
10816
10817 p = start;
10818 left = size - (start - message);
10819 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
10820 {
10821 /* Should it be skipped? */
10822 if (cpu_arch [j].skip)
10823 continue;
10824
10825 name = cpu_arch [j].name;
10826 len = cpu_arch [j].len;
10827 if (*name == '.')
10828 {
10829 /* It is an extension. Skip if we aren't asked to show it. */
10830 if (ext)
10831 {
10832 name++;
10833 len--;
10834 }
10835 else
10836 continue;
10837 }
10838 else if (ext)
10839 {
10840 /* It is an processor. Skip if we show only extension. */
10841 continue;
10842 }
10843 else if (check && ! cpu_arch[j].flags.bitfield.cpui386)
10844 {
10845 /* It is an impossible processor - skip. */
10846 continue;
10847 }
10848
10849 p = output_message (stream, p, message, start, &left, name, len);
10850 }
10851
10852 /* Display disabled extensions. */
10853 if (ext)
10854 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
10855 {
10856 name = cpu_noarch [j].name;
10857 len = cpu_noarch [j].len;
10858 p = output_message (stream, p, message, start, &left, name,
10859 len);
10860 }
10861
10862 *p = '\0';
10863 fprintf (stream, "%s\n", message);
10864 }
10865
10866 void
10867 md_show_usage (FILE *stream)
10868 {
10869 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10870 fprintf (stream, _("\
10871 -Q ignored\n\
10872 -V print assembler version number\n\
10873 -k ignored\n"));
10874 #endif
10875 fprintf (stream, _("\
10876 -n Do not optimize code alignment\n\
10877 -q quieten some warnings\n"));
10878 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10879 fprintf (stream, _("\
10880 -s ignored\n"));
10881 #endif
10882 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10883 || defined (TE_PE) || defined (TE_PEP))
10884 fprintf (stream, _("\
10885 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
10886 #endif
10887 #ifdef SVR4_COMMENT_CHARS
10888 fprintf (stream, _("\
10889 --divide do not treat `/' as a comment character\n"));
10890 #else
10891 fprintf (stream, _("\
10892 --divide ignored\n"));
10893 #endif
10894 fprintf (stream, _("\
10895 -march=CPU[,+EXTENSION...]\n\
10896 generate code for CPU and EXTENSION, CPU is one of:\n"));
10897 show_arch (stream, 0, 1);
10898 fprintf (stream, _("\
10899 EXTENSION is combination of:\n"));
10900 show_arch (stream, 1, 0);
10901 fprintf (stream, _("\
10902 -mtune=CPU optimize for CPU, CPU is one of:\n"));
10903 show_arch (stream, 0, 0);
10904 fprintf (stream, _("\
10905 -msse2avx encode SSE instructions with VEX prefix\n"));
10906 fprintf (stream, _("\
10907 -msse-check=[none|error|warning]\n\
10908 check SSE instructions\n"));
10909 fprintf (stream, _("\
10910 -moperand-check=[none|error|warning]\n\
10911 check operand combinations for validity\n"));
10912 fprintf (stream, _("\
10913 -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n\
10914 length\n"));
10915 fprintf (stream, _("\
10916 -mevexlig=[128|256|512] encode scalar EVEX instructions with specific vector\n\
10917 length\n"));
10918 fprintf (stream, _("\
10919 -mevexwig=[0|1] encode EVEX instructions with specific EVEX.W value\n\
10920 for EVEX.W bit ignored instructions\n"));
10921 fprintf (stream, _("\
10922 -mevexrcig=[rne|rd|ru|rz]\n\
10923 encode EVEX instructions with specific EVEX.RC value\n\
10924 for SAE-only ignored instructions\n"));
10925 fprintf (stream, _("\
10926 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
10927 fprintf (stream, _("\
10928 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
10929 fprintf (stream, _("\
10930 -mindex-reg support pseudo index registers\n"));
10931 fprintf (stream, _("\
10932 -mnaked-reg don't require `%%' prefix for registers\n"));
10933 fprintf (stream, _("\
10934 -madd-bnd-prefix add BND prefix for all valid branches\n"));
10935 fprintf (stream, _("\
10936 -mshared disable branch optimization for shared code\n"));
10937 # if defined (TE_PE) || defined (TE_PEP)
10938 fprintf (stream, _("\
10939 -mbig-obj generate big object files\n"));
10940 #endif
10941 fprintf (stream, _("\
10942 -momit-lock-prefix=[no|yes]\n\
10943 strip all lock prefixes\n"));
10944 fprintf (stream, _("\
10945 -mfence-as-lock-add=[no|yes]\n\
10946 encode lfence, mfence and sfence as\n\
10947 lock addl $0x0, (%%{re}sp)\n"));
10948 fprintf (stream, _("\
10949 -mrelax-relocations=[no|yes]\n\
10950 generate relax relocations\n"));
10951 fprintf (stream, _("\
10952 -mamd64 accept only AMD64 ISA\n"));
10953 fprintf (stream, _("\
10954 -mintel64 accept only Intel64 ISA\n"));
10955 }
10956
10957 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
10958 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10959 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
10960
10961 /* Pick the target format to use. */
10962
10963 const char *
10964 i386_target_format (void)
10965 {
10966 if (!strncmp (default_arch, "x86_64", 6))
10967 {
10968 update_code_flag (CODE_64BIT, 1);
10969 if (default_arch[6] == '\0')
10970 x86_elf_abi = X86_64_ABI;
10971 else
10972 x86_elf_abi = X86_64_X32_ABI;
10973 }
10974 else if (!strcmp (default_arch, "i386"))
10975 update_code_flag (CODE_32BIT, 1);
10976 else if (!strcmp (default_arch, "iamcu"))
10977 {
10978 update_code_flag (CODE_32BIT, 1);
10979 if (cpu_arch_isa == PROCESSOR_UNKNOWN)
10980 {
10981 static const i386_cpu_flags iamcu_flags = CPU_IAMCU_FLAGS;
10982 cpu_arch_name = "iamcu";
10983 cpu_sub_arch_name = NULL;
10984 cpu_arch_flags = iamcu_flags;
10985 cpu_arch_isa = PROCESSOR_IAMCU;
10986 cpu_arch_isa_flags = iamcu_flags;
10987 if (!cpu_arch_tune_set)
10988 {
10989 cpu_arch_tune = cpu_arch_isa;
10990 cpu_arch_tune_flags = cpu_arch_isa_flags;
10991 }
10992 }
10993 else if (cpu_arch_isa != PROCESSOR_IAMCU)
10994 as_fatal (_("Intel MCU doesn't support `%s' architecture"),
10995 cpu_arch_name);
10996 }
10997 else
10998 as_fatal (_("unknown architecture"));
10999
11000 if (cpu_flags_all_zero (&cpu_arch_isa_flags))
11001 cpu_arch_isa_flags = cpu_arch[flag_code == CODE_64BIT].flags;
11002 if (cpu_flags_all_zero (&cpu_arch_tune_flags))
11003 cpu_arch_tune_flags = cpu_arch[flag_code == CODE_64BIT].flags;
11004
11005 switch (OUTPUT_FLAVOR)
11006 {
11007 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
11008 case bfd_target_aout_flavour:
11009 return AOUT_TARGET_FORMAT;
11010 #endif
11011 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
11012 # if defined (TE_PE) || defined (TE_PEP)
11013 case bfd_target_coff_flavour:
11014 if (flag_code == CODE_64BIT)
11015 return use_big_obj ? "pe-bigobj-x86-64" : "pe-x86-64";
11016 else
11017 return "pe-i386";
11018 # elif defined (TE_GO32)
11019 case bfd_target_coff_flavour:
11020 return "coff-go32";
11021 # else
11022 case bfd_target_coff_flavour:
11023 return "coff-i386";
11024 # endif
11025 #endif
11026 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
11027 case bfd_target_elf_flavour:
11028 {
11029 const char *format;
11030
11031 switch (x86_elf_abi)
11032 {
11033 default:
11034 format = ELF_TARGET_FORMAT;
11035 break;
11036 case X86_64_ABI:
11037 use_rela_relocations = 1;
11038 object_64bit = 1;
11039 format = ELF_TARGET_FORMAT64;
11040 break;
11041 case X86_64_X32_ABI:
11042 use_rela_relocations = 1;
11043 object_64bit = 1;
11044 disallow_64bit_reloc = 1;
11045 format = ELF_TARGET_FORMAT32;
11046 break;
11047 }
11048 if (cpu_arch_isa == PROCESSOR_L1OM)
11049 {
11050 if (x86_elf_abi != X86_64_ABI)
11051 as_fatal (_("Intel L1OM is 64bit only"));
11052 return ELF_TARGET_L1OM_FORMAT;
11053 }
11054 else if (cpu_arch_isa == PROCESSOR_K1OM)
11055 {
11056 if (x86_elf_abi != X86_64_ABI)
11057 as_fatal (_("Intel K1OM is 64bit only"));
11058 return ELF_TARGET_K1OM_FORMAT;
11059 }
11060 else if (cpu_arch_isa == PROCESSOR_IAMCU)
11061 {
11062 if (x86_elf_abi != I386_ABI)
11063 as_fatal (_("Intel MCU is 32bit only"));
11064 return ELF_TARGET_IAMCU_FORMAT;
11065 }
11066 else
11067 return format;
11068 }
11069 #endif
11070 #if defined (OBJ_MACH_O)
11071 case bfd_target_mach_o_flavour:
11072 if (flag_code == CODE_64BIT)
11073 {
11074 use_rela_relocations = 1;
11075 object_64bit = 1;
11076 return "mach-o-x86-64";
11077 }
11078 else
11079 return "mach-o-i386";
11080 #endif
11081 default:
11082 abort ();
11083 return NULL;
11084 }
11085 }
11086
11087 #endif /* OBJ_MAYBE_ more than one */
11088 \f
11089 symbolS *
11090 md_undefined_symbol (char *name)
11091 {
11092 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
11093 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
11094 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
11095 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
11096 {
11097 if (!GOT_symbol)
11098 {
11099 if (symbol_find (name))
11100 as_bad (_("GOT already in symbol table"));
11101 GOT_symbol = symbol_new (name, undefined_section,
11102 (valueT) 0, &zero_address_frag);
11103 };
11104 return GOT_symbol;
11105 }
11106 return 0;
11107 }
11108
11109 /* Round up a section size to the appropriate boundary. */
11110
11111 valueT
11112 md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size)
11113 {
11114 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
11115 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
11116 {
11117 /* For a.out, force the section size to be aligned. If we don't do
11118 this, BFD will align it for us, but it will not write out the
11119 final bytes of the section. This may be a bug in BFD, but it is
11120 easier to fix it here since that is how the other a.out targets
11121 work. */
11122 int align;
11123
11124 align = bfd_get_section_alignment (stdoutput, segment);
11125 size = ((size + (1 << align) - 1) & (-((valueT) 1 << align)));
11126 }
11127 #endif
11128
11129 return size;
11130 }
11131
11132 /* On the i386, PC-relative offsets are relative to the start of the
11133 next instruction. That is, the address of the offset, plus its
11134 size, since the offset is always the last part of the insn. */
11135
11136 long
11137 md_pcrel_from (fixS *fixP)
11138 {
11139 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
11140 }
11141
11142 #ifndef I386COFF
11143
11144 static void
11145 s_bss (int ignore ATTRIBUTE_UNUSED)
11146 {
11147 int temp;
11148
11149 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11150 if (IS_ELF)
11151 obj_elf_section_change_hook ();
11152 #endif
11153 temp = get_absolute_expression ();
11154 subseg_set (bss_section, (subsegT) temp);
11155 demand_empty_rest_of_line ();
11156 }
11157
11158 #endif
11159
11160 void
11161 i386_validate_fix (fixS *fixp)
11162 {
11163 if (fixp->fx_subsy)
11164 {
11165 if (fixp->fx_subsy == GOT_symbol)
11166 {
11167 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
11168 {
11169 if (!object_64bit)
11170 abort ();
11171 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11172 if (fixp->fx_tcbit2)
11173 fixp->fx_r_type = (fixp->fx_tcbit
11174 ? BFD_RELOC_X86_64_REX_GOTPCRELX
11175 : BFD_RELOC_X86_64_GOTPCRELX);
11176 else
11177 #endif
11178 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
11179 }
11180 else
11181 {
11182 if (!object_64bit)
11183 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
11184 else
11185 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
11186 }
11187 fixp->fx_subsy = 0;
11188 }
11189 }
11190 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11191 else if (!object_64bit)
11192 {
11193 if (fixp->fx_r_type == BFD_RELOC_386_GOT32
11194 && fixp->fx_tcbit2)
11195 fixp->fx_r_type = BFD_RELOC_386_GOT32X;
11196 }
11197 #endif
11198 }
11199
11200 arelent *
11201 tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
11202 {
11203 arelent *rel;
11204 bfd_reloc_code_real_type code;
11205
11206 switch (fixp->fx_r_type)
11207 {
11208 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11209 case BFD_RELOC_SIZE32:
11210 case BFD_RELOC_SIZE64:
11211 if (S_IS_DEFINED (fixp->fx_addsy)
11212 && !S_IS_EXTERNAL (fixp->fx_addsy))
11213 {
11214 /* Resolve size relocation against local symbol to size of
11215 the symbol plus addend. */
11216 valueT value = S_GET_SIZE (fixp->fx_addsy) + fixp->fx_offset;
11217 if (fixp->fx_r_type == BFD_RELOC_SIZE32
11218 && !fits_in_unsigned_long (value))
11219 as_bad_where (fixp->fx_file, fixp->fx_line,
11220 _("symbol size computation overflow"));
11221 fixp->fx_addsy = NULL;
11222 fixp->fx_subsy = NULL;
11223 md_apply_fix (fixp, (valueT *) &value, NULL);
11224 return NULL;
11225 }
11226 #endif
11227 /* Fall through. */
11228
11229 case BFD_RELOC_X86_64_PLT32:
11230 case BFD_RELOC_X86_64_GOT32:
11231 case BFD_RELOC_X86_64_GOTPCREL:
11232 case BFD_RELOC_X86_64_GOTPCRELX:
11233 case BFD_RELOC_X86_64_REX_GOTPCRELX:
11234 case BFD_RELOC_386_PLT32:
11235 case BFD_RELOC_386_GOT32:
11236 case BFD_RELOC_386_GOT32X:
11237 case BFD_RELOC_386_GOTOFF:
11238 case BFD_RELOC_386_GOTPC:
11239 case BFD_RELOC_386_TLS_GD:
11240 case BFD_RELOC_386_TLS_LDM:
11241 case BFD_RELOC_386_TLS_LDO_32:
11242 case BFD_RELOC_386_TLS_IE_32:
11243 case BFD_RELOC_386_TLS_IE:
11244 case BFD_RELOC_386_TLS_GOTIE:
11245 case BFD_RELOC_386_TLS_LE_32:
11246 case BFD_RELOC_386_TLS_LE:
11247 case BFD_RELOC_386_TLS_GOTDESC:
11248 case BFD_RELOC_386_TLS_DESC_CALL:
11249 case BFD_RELOC_X86_64_TLSGD:
11250 case BFD_RELOC_X86_64_TLSLD:
11251 case BFD_RELOC_X86_64_DTPOFF32:
11252 case BFD_RELOC_X86_64_DTPOFF64:
11253 case BFD_RELOC_X86_64_GOTTPOFF:
11254 case BFD_RELOC_X86_64_TPOFF32:
11255 case BFD_RELOC_X86_64_TPOFF64:
11256 case BFD_RELOC_X86_64_GOTOFF64:
11257 case BFD_RELOC_X86_64_GOTPC32:
11258 case BFD_RELOC_X86_64_GOT64:
11259 case BFD_RELOC_X86_64_GOTPCREL64:
11260 case BFD_RELOC_X86_64_GOTPC64:
11261 case BFD_RELOC_X86_64_GOTPLT64:
11262 case BFD_RELOC_X86_64_PLTOFF64:
11263 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
11264 case BFD_RELOC_X86_64_TLSDESC_CALL:
11265 case BFD_RELOC_RVA:
11266 case BFD_RELOC_VTABLE_ENTRY:
11267 case BFD_RELOC_VTABLE_INHERIT:
11268 #ifdef TE_PE
11269 case BFD_RELOC_32_SECREL:
11270 #endif
11271 code = fixp->fx_r_type;
11272 break;
11273 case BFD_RELOC_X86_64_32S:
11274 if (!fixp->fx_pcrel)
11275 {
11276 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
11277 code = fixp->fx_r_type;
11278 break;
11279 }
11280 /* Fall through. */
11281 default:
11282 if (fixp->fx_pcrel)
11283 {
11284 switch (fixp->fx_size)
11285 {
11286 default:
11287 as_bad_where (fixp->fx_file, fixp->fx_line,
11288 _("can not do %d byte pc-relative relocation"),
11289 fixp->fx_size);
11290 code = BFD_RELOC_32_PCREL;
11291 break;
11292 case 1: code = BFD_RELOC_8_PCREL; break;
11293 case 2: code = BFD_RELOC_16_PCREL; break;
11294 case 4: code = BFD_RELOC_32_PCREL; break;
11295 #ifdef BFD64
11296 case 8: code = BFD_RELOC_64_PCREL; break;
11297 #endif
11298 }
11299 }
11300 else
11301 {
11302 switch (fixp->fx_size)
11303 {
11304 default:
11305 as_bad_where (fixp->fx_file, fixp->fx_line,
11306 _("can not do %d byte relocation"),
11307 fixp->fx_size);
11308 code = BFD_RELOC_32;
11309 break;
11310 case 1: code = BFD_RELOC_8; break;
11311 case 2: code = BFD_RELOC_16; break;
11312 case 4: code = BFD_RELOC_32; break;
11313 #ifdef BFD64
11314 case 8: code = BFD_RELOC_64; break;
11315 #endif
11316 }
11317 }
11318 break;
11319 }
11320
11321 if ((code == BFD_RELOC_32
11322 || code == BFD_RELOC_32_PCREL
11323 || code == BFD_RELOC_X86_64_32S)
11324 && GOT_symbol
11325 && fixp->fx_addsy == GOT_symbol)
11326 {
11327 if (!object_64bit)
11328 code = BFD_RELOC_386_GOTPC;
11329 else
11330 code = BFD_RELOC_X86_64_GOTPC32;
11331 }
11332 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
11333 && GOT_symbol
11334 && fixp->fx_addsy == GOT_symbol)
11335 {
11336 code = BFD_RELOC_X86_64_GOTPC64;
11337 }
11338
11339 rel = XNEW (arelent);
11340 rel->sym_ptr_ptr = XNEW (asymbol *);
11341 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
11342
11343 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
11344
11345 if (!use_rela_relocations)
11346 {
11347 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
11348 vtable entry to be used in the relocation's section offset. */
11349 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
11350 rel->address = fixp->fx_offset;
11351 #if defined (OBJ_COFF) && defined (TE_PE)
11352 else if (fixp->fx_addsy && S_IS_WEAK (fixp->fx_addsy))
11353 rel->addend = fixp->fx_addnumber - (S_GET_VALUE (fixp->fx_addsy) * 2);
11354 else
11355 #endif
11356 rel->addend = 0;
11357 }
11358 /* Use the rela in 64bit mode. */
11359 else
11360 {
11361 if (disallow_64bit_reloc)
11362 switch (code)
11363 {
11364 case BFD_RELOC_X86_64_DTPOFF64:
11365 case BFD_RELOC_X86_64_TPOFF64:
11366 case BFD_RELOC_64_PCREL:
11367 case BFD_RELOC_X86_64_GOTOFF64:
11368 case BFD_RELOC_X86_64_GOT64:
11369 case BFD_RELOC_X86_64_GOTPCREL64:
11370 case BFD_RELOC_X86_64_GOTPC64:
11371 case BFD_RELOC_X86_64_GOTPLT64:
11372 case BFD_RELOC_X86_64_PLTOFF64:
11373 as_bad_where (fixp->fx_file, fixp->fx_line,
11374 _("cannot represent relocation type %s in x32 mode"),
11375 bfd_get_reloc_code_name (code));
11376 break;
11377 default:
11378 break;
11379 }
11380
11381 if (!fixp->fx_pcrel)
11382 rel->addend = fixp->fx_offset;
11383 else
11384 switch (code)
11385 {
11386 case BFD_RELOC_X86_64_PLT32:
11387 case BFD_RELOC_X86_64_GOT32:
11388 case BFD_RELOC_X86_64_GOTPCREL:
11389 case BFD_RELOC_X86_64_GOTPCRELX:
11390 case BFD_RELOC_X86_64_REX_GOTPCRELX:
11391 case BFD_RELOC_X86_64_TLSGD:
11392 case BFD_RELOC_X86_64_TLSLD:
11393 case BFD_RELOC_X86_64_GOTTPOFF:
11394 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
11395 case BFD_RELOC_X86_64_TLSDESC_CALL:
11396 rel->addend = fixp->fx_offset - fixp->fx_size;
11397 break;
11398 default:
11399 rel->addend = (section->vma
11400 - fixp->fx_size
11401 + fixp->fx_addnumber
11402 + md_pcrel_from (fixp));
11403 break;
11404 }
11405 }
11406
11407 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
11408 if (rel->howto == NULL)
11409 {
11410 as_bad_where (fixp->fx_file, fixp->fx_line,
11411 _("cannot represent relocation type %s"),
11412 bfd_get_reloc_code_name (code));
11413 /* Set howto to a garbage value so that we can keep going. */
11414 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
11415 gas_assert (rel->howto != NULL);
11416 }
11417
11418 return rel;
11419 }
11420
11421 #include "tc-i386-intel.c"
11422
11423 void
11424 tc_x86_parse_to_dw2regnum (expressionS *exp)
11425 {
11426 int saved_naked_reg;
11427 char saved_register_dot;
11428
11429 saved_naked_reg = allow_naked_reg;
11430 allow_naked_reg = 1;
11431 saved_register_dot = register_chars['.'];
11432 register_chars['.'] = '.';
11433 allow_pseudo_reg = 1;
11434 expression_and_evaluate (exp);
11435 allow_pseudo_reg = 0;
11436 register_chars['.'] = saved_register_dot;
11437 allow_naked_reg = saved_naked_reg;
11438
11439 if (exp->X_op == O_register && exp->X_add_number >= 0)
11440 {
11441 if ((addressT) exp->X_add_number < i386_regtab_size)
11442 {
11443 exp->X_op = O_constant;
11444 exp->X_add_number = i386_regtab[exp->X_add_number]
11445 .dw2_regnum[flag_code >> 1];
11446 }
11447 else
11448 exp->X_op = O_illegal;
11449 }
11450 }
11451
11452 void
11453 tc_x86_frame_initial_instructions (void)
11454 {
11455 static unsigned int sp_regno[2];
11456
11457 if (!sp_regno[flag_code >> 1])
11458 {
11459 char *saved_input = input_line_pointer;
11460 char sp[][4] = {"esp", "rsp"};
11461 expressionS exp;
11462
11463 input_line_pointer = sp[flag_code >> 1];
11464 tc_x86_parse_to_dw2regnum (&exp);
11465 gas_assert (exp.X_op == O_constant);
11466 sp_regno[flag_code >> 1] = exp.X_add_number;
11467 input_line_pointer = saved_input;
11468 }
11469
11470 cfi_add_CFA_def_cfa (sp_regno[flag_code >> 1], -x86_cie_data_alignment);
11471 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
11472 }
11473
11474 int
11475 x86_dwarf2_addr_size (void)
11476 {
11477 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
11478 if (x86_elf_abi == X86_64_X32_ABI)
11479 return 4;
11480 #endif
11481 return bfd_arch_bits_per_address (stdoutput) / 8;
11482 }
11483
11484 int
11485 i386_elf_section_type (const char *str, size_t len)
11486 {
11487 if (flag_code == CODE_64BIT
11488 && len == sizeof ("unwind") - 1
11489 && strncmp (str, "unwind", 6) == 0)
11490 return SHT_X86_64_UNWIND;
11491
11492 return -1;
11493 }
11494
11495 #ifdef TE_SOLARIS
11496 void
11497 i386_solaris_fix_up_eh_frame (segT sec)
11498 {
11499 if (flag_code == CODE_64BIT)
11500 elf_section_type (sec) = SHT_X86_64_UNWIND;
11501 }
11502 #endif
11503
11504 #ifdef TE_PE
11505 void
11506 tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
11507 {
11508 expressionS exp;
11509
11510 exp.X_op = O_secrel;
11511 exp.X_add_symbol = symbol;
11512 exp.X_add_number = 0;
11513 emit_expr (&exp, size);
11514 }
11515 #endif
11516
11517 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11518 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
11519
11520 bfd_vma
11521 x86_64_section_letter (int letter, const char **ptr_msg)
11522 {
11523 if (flag_code == CODE_64BIT)
11524 {
11525 if (letter == 'l')
11526 return SHF_X86_64_LARGE;
11527
11528 *ptr_msg = _("bad .section directive: want a,l,w,x,M,S,G,T in string");
11529 }
11530 else
11531 *ptr_msg = _("bad .section directive: want a,w,x,M,S,G,T in string");
11532 return -1;
11533 }
11534
11535 bfd_vma
11536 x86_64_section_word (char *str, size_t len)
11537 {
11538 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
11539 return SHF_X86_64_LARGE;
11540
11541 return -1;
11542 }
11543
11544 static void
11545 handle_large_common (int small ATTRIBUTE_UNUSED)
11546 {
11547 if (flag_code != CODE_64BIT)
11548 {
11549 s_comm_internal (0, elf_common_parse);
11550 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
11551 }
11552 else
11553 {
11554 static segT lbss_section;
11555 asection *saved_com_section_ptr = elf_com_section_ptr;
11556 asection *saved_bss_section = bss_section;
11557
11558 if (lbss_section == NULL)
11559 {
11560 flagword applicable;
11561 segT seg = now_seg;
11562 subsegT subseg = now_subseg;
11563
11564 /* The .lbss section is for local .largecomm symbols. */
11565 lbss_section = subseg_new (".lbss", 0);
11566 applicable = bfd_applicable_section_flags (stdoutput);
11567 bfd_set_section_flags (stdoutput, lbss_section,
11568 applicable & SEC_ALLOC);
11569 seg_info (lbss_section)->bss = 1;
11570
11571 subseg_set (seg, subseg);
11572 }
11573
11574 elf_com_section_ptr = &_bfd_elf_large_com_section;
11575 bss_section = lbss_section;
11576
11577 s_comm_internal (0, elf_common_parse);
11578
11579 elf_com_section_ptr = saved_com_section_ptr;
11580 bss_section = saved_bss_section;
11581 }
11582 }
11583 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
GDB Binutils - Deliverables
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