1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright (C) 1989-2020 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 /* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
23 x86_64 support by Jan Hubicka (jh@suse.cz)
24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
29 #include "safe-ctype.h"
31 #include "dwarf2dbg.h"
32 #include "dw2gencfi.h"
33 #include "elf/x86-64.h"
34 #include "opcodes/i386-init.h"
39 #ifdef HAVE_SYS_PARAM_H
40 #include <sys/param.h>
43 #define INT_MAX (int) (((unsigned) (-1)) >> 1)
47 #ifndef INFER_ADDR_PREFIX
48 #define INFER_ADDR_PREFIX 1
52 #define DEFAULT_ARCH "i386"
57 #define INLINE __inline__
63 /* Prefixes will be emitted in the order defined below.
64 WAIT_PREFIX must be the first prefix since FWAIT is really is an
65 instruction, and so must come before any prefixes.
66 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
67 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
73 #define HLE_PREFIX REP_PREFIX
74 #define BND_PREFIX REP_PREFIX
76 #define REX_PREFIX 6 /* must come last. */
77 #define MAX_PREFIXES 7 /* max prefixes per opcode */
79 /* we define the syntax here (modulo base,index,scale syntax) */
80 #define REGISTER_PREFIX '%'
81 #define IMMEDIATE_PREFIX '$'
82 #define ABSOLUTE_PREFIX '*'
84 /* these are the instruction mnemonic suffixes in AT&T syntax or
85 memory operand size in Intel syntax. */
86 #define WORD_MNEM_SUFFIX 'w'
87 #define BYTE_MNEM_SUFFIX 'b'
88 #define SHORT_MNEM_SUFFIX 's'
89 #define LONG_MNEM_SUFFIX 'l'
90 #define QWORD_MNEM_SUFFIX 'q'
91 /* Intel Syntax. Use a non-ascii letter since since it never appears
93 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
95 #define END_OF_INSN '\0'
97 /* This matches the C -> StaticRounding alias in the opcode table. */
98 #define commutative staticrounding
101 'templates' is for grouping together 'template' structures for opcodes
102 of the same name. This is only used for storing the insns in the grand
103 ole hash table of insns.
104 The templates themselves start at START and range up to (but not including)
109 const insn_template
*start
;
110 const insn_template
*end
;
114 /* 386 operand encoding bytes: see 386 book for details of this. */
117 unsigned int regmem
; /* codes register or memory operand */
118 unsigned int reg
; /* codes register operand (or extended opcode) */
119 unsigned int mode
; /* how to interpret regmem & reg */
123 /* x86-64 extension prefix. */
124 typedef int rex_byte
;
126 /* 386 opcode byte to code indirect addressing. */
135 /* x86 arch names, types and features */
138 const char *name
; /* arch name */
139 unsigned int len
; /* arch string length */
140 enum processor_type type
; /* arch type */
141 i386_cpu_flags flags
; /* cpu feature flags */
142 unsigned int skip
; /* show_arch should skip this. */
146 /* Used to turn off indicated flags. */
149 const char *name
; /* arch name */
150 unsigned int len
; /* arch string length */
151 i386_cpu_flags flags
; /* cpu feature flags */
155 static void update_code_flag (int, int);
156 static void set_code_flag (int);
157 static void set_16bit_gcc_code_flag (int);
158 static void set_intel_syntax (int);
159 static void set_intel_mnemonic (int);
160 static void set_allow_index_reg (int);
161 static void set_check (int);
162 static void set_cpu_arch (int);
164 static void pe_directive_secrel (int);
166 static void signed_cons (int);
167 static char *output_invalid (int c
);
168 static int i386_finalize_immediate (segT
, expressionS
*, i386_operand_type
,
170 static int i386_finalize_displacement (segT
, expressionS
*, i386_operand_type
,
172 static int i386_att_operand (char *);
173 static int i386_intel_operand (char *, int);
174 static int i386_intel_simplify (expressionS
*);
175 static int i386_intel_parse_name (const char *, expressionS
*);
176 static const reg_entry
*parse_register (char *, char **);
177 static char *parse_insn (char *, char *);
178 static char *parse_operands (char *, const char *);
179 static void swap_operands (void);
180 static void swap_2_operands (int, int);
181 static enum flag_code
i386_addressing_mode (void);
182 static void optimize_imm (void);
183 static void optimize_disp (void);
184 static const insn_template
*match_template (char);
185 static int check_string (void);
186 static int process_suffix (void);
187 static int check_byte_reg (void);
188 static int check_long_reg (void);
189 static int check_qword_reg (void);
190 static int check_word_reg (void);
191 static int finalize_imm (void);
192 static int process_operands (void);
193 static const seg_entry
*build_modrm_byte (void);
194 static void output_insn (void);
195 static void output_imm (fragS
*, offsetT
);
196 static void output_disp (fragS
*, offsetT
);
198 static void s_bss (int);
200 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
201 static void handle_large_common (int small ATTRIBUTE_UNUSED
);
203 /* GNU_PROPERTY_X86_ISA_1_USED. */
204 static unsigned int x86_isa_1_used
;
205 /* GNU_PROPERTY_X86_FEATURE_2_USED. */
206 static unsigned int x86_feature_2_used
;
207 /* Generate x86 used ISA and feature properties. */
208 static unsigned int x86_used_note
= DEFAULT_X86_USED_NOTE
;
211 static const char *default_arch
= DEFAULT_ARCH
;
213 /* parse_register() returns this when a register alias cannot be used. */
214 static const reg_entry bad_reg
= { "<bad>", OPERAND_TYPE_NONE
, 0, 0,
215 { Dw2Inval
, Dw2Inval
} };
217 /* This struct describes rounding control and SAE in the instruction. */
231 static struct RC_Operation rc_op
;
233 /* The struct describes masking, applied to OPERAND in the instruction.
234 MASK is a pointer to the corresponding mask register. ZEROING tells
235 whether merging or zeroing mask is used. */
236 struct Mask_Operation
238 const reg_entry
*mask
;
239 unsigned int zeroing
;
240 /* The operand where this operation is associated. */
244 static struct Mask_Operation mask_op
;
246 /* The struct describes broadcasting, applied to OPERAND. FACTOR is
248 struct Broadcast_Operation
250 /* Type of broadcast: {1to2}, {1to4}, {1to8}, or {1to16}. */
253 /* Index of broadcasted operand. */
256 /* Number of bytes to broadcast. */
260 static struct Broadcast_Operation broadcast_op
;
265 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
266 unsigned char bytes
[4];
268 /* Destination or source register specifier. */
269 const reg_entry
*register_specifier
;
272 /* 'md_assemble ()' gathers together information and puts it into a
279 const reg_entry
*regs
;
284 operand_size_mismatch
,
285 operand_type_mismatch
,
286 register_type_mismatch
,
287 number_of_operands_mismatch
,
288 invalid_instruction_suffix
,
290 unsupported_with_intel_mnemonic
,
293 invalid_vsib_address
,
294 invalid_vector_register_set
,
295 unsupported_vector_index_register
,
296 unsupported_broadcast
,
299 mask_not_on_destination
,
302 rc_sae_operand_not_last_imm
,
303 invalid_register_operand
,
308 /* TM holds the template for the insn were currently assembling. */
311 /* SUFFIX holds the instruction size suffix for byte, word, dword
312 or qword, if given. */
315 /* OPERANDS gives the number of given operands. */
316 unsigned int operands
;
318 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
319 of given register, displacement, memory operands and immediate
321 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
323 /* TYPES [i] is the type (see above #defines) which tells us how to
324 use OP[i] for the corresponding operand. */
325 i386_operand_type types
[MAX_OPERANDS
];
327 /* Displacement expression, immediate expression, or register for each
329 union i386_op op
[MAX_OPERANDS
];
331 /* Flags for operands. */
332 unsigned int flags
[MAX_OPERANDS
];
333 #define Operand_PCrel 1
334 #define Operand_Mem 2
336 /* Relocation type for operand */
337 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
339 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
340 the base index byte below. */
341 const reg_entry
*base_reg
;
342 const reg_entry
*index_reg
;
343 unsigned int log2_scale_factor
;
345 /* SEG gives the seg_entries of this insn. They are zero unless
346 explicit segment overrides are given. */
347 const seg_entry
*seg
[2];
349 /* Copied first memory operand string, for re-checking. */
352 /* PREFIX holds all the given prefix opcodes (usually null).
353 PREFIXES is the number of prefix opcodes. */
354 unsigned int prefixes
;
355 unsigned char prefix
[MAX_PREFIXES
];
357 /* Register is in low 3 bits of opcode. */
358 bfd_boolean short_form
;
360 /* The operand to a branch insn indicates an absolute branch. */
361 bfd_boolean jumpabsolute
;
363 /* Has MMX register operands. */
364 bfd_boolean has_regmmx
;
366 /* Has XMM register operands. */
367 bfd_boolean has_regxmm
;
369 /* Has YMM register operands. */
370 bfd_boolean has_regymm
;
372 /* Has ZMM register operands. */
373 bfd_boolean has_regzmm
;
375 /* Has GOTPC or TLS relocation. */
376 bfd_boolean has_gotpc_tls_reloc
;
378 /* RM and SIB are the modrm byte and the sib byte where the
379 addressing modes of this insn are encoded. */
386 /* Masking attributes. */
387 struct Mask_Operation
*mask
;
389 /* Rounding control and SAE attributes. */
390 struct RC_Operation
*rounding
;
392 /* Broadcasting attributes. */
393 struct Broadcast_Operation
*broadcast
;
395 /* Compressed disp8*N attribute. */
396 unsigned int memshift
;
398 /* Prefer load or store in encoding. */
401 dir_encoding_default
= 0,
407 /* Prefer 8bit or 32bit displacement in encoding. */
410 disp_encoding_default
= 0,
415 /* Prefer the REX byte in encoding. */
416 bfd_boolean rex_encoding
;
418 /* Disable instruction size optimization. */
419 bfd_boolean no_optimize
;
421 /* How to encode vector instructions. */
424 vex_encoding_default
= 0,
432 const char *rep_prefix
;
435 const char *hle_prefix
;
437 /* Have BND prefix. */
438 const char *bnd_prefix
;
440 /* Have NOTRACK prefix. */
441 const char *notrack_prefix
;
444 enum i386_error error
;
447 typedef struct _i386_insn i386_insn
;
449 /* Link RC type with corresponding string, that'll be looked for in
458 static const struct RC_name RC_NamesTable
[] =
460 { rne
, STRING_COMMA_LEN ("rn-sae") },
461 { rd
, STRING_COMMA_LEN ("rd-sae") },
462 { ru
, STRING_COMMA_LEN ("ru-sae") },
463 { rz
, STRING_COMMA_LEN ("rz-sae") },
464 { saeonly
, STRING_COMMA_LEN ("sae") },
467 /* List of chars besides those in app.c:symbol_chars that can start an
468 operand. Used to prevent the scrubber eating vital white-space. */
469 const char extra_symbol_chars
[] = "*%-([{}"
478 #if (defined (TE_I386AIX) \
479 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
480 && !defined (TE_GNU) \
481 && !defined (TE_LINUX) \
482 && !defined (TE_NACL) \
483 && !defined (TE_FreeBSD) \
484 && !defined (TE_DragonFly) \
485 && !defined (TE_NetBSD)))
486 /* This array holds the chars that always start a comment. If the
487 pre-processor is disabled, these aren't very useful. The option
488 --divide will remove '/' from this list. */
489 const char *i386_comment_chars
= "#/";
490 #define SVR4_COMMENT_CHARS 1
491 #define PREFIX_SEPARATOR '\\'
494 const char *i386_comment_chars
= "#";
495 #define PREFIX_SEPARATOR '/'
498 /* This array holds the chars that only start a comment at the beginning of
499 a line. If the line seems to have the form '# 123 filename'
500 .line and .file directives will appear in the pre-processed output.
501 Note that input_file.c hand checks for '#' at the beginning of the
502 first line of the input file. This is because the compiler outputs
503 #NO_APP at the beginning of its output.
504 Also note that comments started like this one will always work if
505 '/' isn't otherwise defined. */
506 const char line_comment_chars
[] = "#/";
508 const char line_separator_chars
[] = ";";
510 /* Chars that can be used to separate mant from exp in floating point
512 const char EXP_CHARS
[] = "eE";
514 /* Chars that mean this number is a floating point constant
517 const char FLT_CHARS
[] = "fFdDxX";
519 /* Tables for lexical analysis. */
520 static char mnemonic_chars
[256];
521 static char register_chars
[256];
522 static char operand_chars
[256];
523 static char identifier_chars
[256];
524 static char digit_chars
[256];
526 /* Lexical macros. */
527 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
528 #define is_operand_char(x) (operand_chars[(unsigned char) x])
529 #define is_register_char(x) (register_chars[(unsigned char) x])
530 #define is_space_char(x) ((x) == ' ')
531 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
532 #define is_digit_char(x) (digit_chars[(unsigned char) x])
534 /* All non-digit non-letter characters that may occur in an operand. */
535 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
537 /* md_assemble() always leaves the strings it's passed unaltered. To
538 effect this we maintain a stack of saved characters that we've smashed
539 with '\0's (indicating end of strings for various sub-fields of the
540 assembler instruction). */
541 static char save_stack
[32];
542 static char *save_stack_p
;
543 #define END_STRING_AND_SAVE(s) \
544 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
545 #define RESTORE_END_STRING(s) \
546 do { *(s) = *--save_stack_p; } while (0)
548 /* The instruction we're assembling. */
551 /* Possible templates for current insn. */
552 static const templates
*current_templates
;
554 /* Per instruction expressionS buffers: max displacements & immediates. */
555 static expressionS disp_expressions
[MAX_MEMORY_OPERANDS
];
556 static expressionS im_expressions
[MAX_IMMEDIATE_OPERANDS
];
558 /* Current operand we are working on. */
559 static int this_operand
= -1;
561 /* We support four different modes. FLAG_CODE variable is used to distinguish
569 static enum flag_code flag_code
;
570 static unsigned int object_64bit
;
571 static unsigned int disallow_64bit_reloc
;
572 static int use_rela_relocations
= 0;
573 /* __tls_get_addr/___tls_get_addr symbol for TLS. */
574 static const char *tls_get_addr
;
576 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
577 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
578 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
580 /* The ELF ABI to use. */
588 static enum x86_elf_abi x86_elf_abi
= I386_ABI
;
591 #if defined (TE_PE) || defined (TE_PEP)
592 /* Use big object file format. */
593 static int use_big_obj
= 0;
596 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
597 /* 1 if generating code for a shared library. */
598 static int shared
= 0;
601 /* 1 for intel syntax,
603 static int intel_syntax
= 0;
605 static enum x86_64_isa
607 amd64
= 1, /* AMD64 ISA. */
608 intel64
/* Intel64 ISA. */
611 /* 1 for intel mnemonic,
612 0 if att mnemonic. */
613 static int intel_mnemonic
= !SYSV386_COMPAT
;
615 /* 1 if pseudo registers are permitted. */
616 static int allow_pseudo_reg
= 0;
618 /* 1 if register prefix % not required. */
619 static int allow_naked_reg
= 0;
621 /* 1 if the assembler should add BND prefix for all control-transferring
622 instructions supporting it, even if this prefix wasn't specified
624 static int add_bnd_prefix
= 0;
626 /* 1 if pseudo index register, eiz/riz, is allowed . */
627 static int allow_index_reg
= 0;
629 /* 1 if the assembler should ignore LOCK prefix, even if it was
630 specified explicitly. */
631 static int omit_lock_prefix
= 0;
633 /* 1 if the assembler should encode lfence, mfence, and sfence as
634 "lock addl $0, (%{re}sp)". */
635 static int avoid_fence
= 0;
637 /* 1 if lfence should be inserted after every load. */
638 static int lfence_after_load
= 0;
640 /* Non-zero if lfence should be inserted before indirect branch. */
641 static enum lfence_before_indirect_branch_kind
643 lfence_branch_none
= 0,
644 lfence_branch_register
,
645 lfence_branch_memory
,
648 lfence_before_indirect_branch
;
650 /* Non-zero if lfence should be inserted before ret. */
651 static enum lfence_before_ret_kind
653 lfence_before_ret_none
= 0,
654 lfence_before_ret_not
,
655 lfence_before_ret_or
,
656 lfence_before_ret_shl
660 /* Types of previous instruction is .byte or prefix. */
675 /* 1 if the assembler should generate relax relocations. */
677 static int generate_relax_relocations
678 = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS
;
680 static enum check_kind
686 sse_check
, operand_check
= check_warning
;
688 /* Non-zero if branches should be aligned within power of 2 boundary. */
689 static int align_branch_power
= 0;
691 /* Types of branches to align. */
692 enum align_branch_kind
694 align_branch_none
= 0,
695 align_branch_jcc
= 1,
696 align_branch_fused
= 2,
697 align_branch_jmp
= 3,
698 align_branch_call
= 4,
699 align_branch_indirect
= 5,
703 /* Type bits of branches to align. */
704 enum align_branch_bit
706 align_branch_jcc_bit
= 1 << align_branch_jcc
,
707 align_branch_fused_bit
= 1 << align_branch_fused
,
708 align_branch_jmp_bit
= 1 << align_branch_jmp
,
709 align_branch_call_bit
= 1 << align_branch_call
,
710 align_branch_indirect_bit
= 1 << align_branch_indirect
,
711 align_branch_ret_bit
= 1 << align_branch_ret
714 static unsigned int align_branch
= (align_branch_jcc_bit
715 | align_branch_fused_bit
716 | align_branch_jmp_bit
);
718 /* Types of condition jump used by macro-fusion. */
721 mf_jcc_jo
= 0, /* base opcode 0x70 */
722 mf_jcc_jc
, /* base opcode 0x72 */
723 mf_jcc_je
, /* base opcode 0x74 */
724 mf_jcc_jna
, /* base opcode 0x76 */
725 mf_jcc_js
, /* base opcode 0x78 */
726 mf_jcc_jp
, /* base opcode 0x7a */
727 mf_jcc_jl
, /* base opcode 0x7c */
728 mf_jcc_jle
, /* base opcode 0x7e */
731 /* Types of compare flag-modifying insntructions used by macro-fusion. */
734 mf_cmp_test_and
, /* test/cmp */
735 mf_cmp_alu_cmp
, /* add/sub/cmp */
736 mf_cmp_incdec
/* inc/dec */
739 /* The maximum padding size for fused jcc. CMP like instruction can
740 be 9 bytes and jcc can be 6 bytes. Leave room just in case for
742 #define MAX_FUSED_JCC_PADDING_SIZE 20
744 /* The maximum number of prefixes added for an instruction. */
745 static unsigned int align_branch_prefix_size
= 5;
748 1. Clear the REX_W bit with register operand if possible.
749 2. Above plus use 128bit vector instruction to clear the full vector
752 static int optimize
= 0;
755 1. Clear the REX_W bit with register operand if possible.
756 2. Above plus use 128bit vector instruction to clear the full vector
758 3. Above plus optimize "test{q,l,w} $imm8,%r{64,32,16}" to
761 static int optimize_for_space
= 0;
763 /* Register prefix used for error message. */
764 static const char *register_prefix
= "%";
766 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
767 leave, push, and pop instructions so that gcc has the same stack
768 frame as in 32 bit mode. */
769 static char stackop_size
= '\0';
771 /* Non-zero to optimize code alignment. */
772 int optimize_align_code
= 1;
774 /* Non-zero to quieten some warnings. */
775 static int quiet_warnings
= 0;
778 static const char *cpu_arch_name
= NULL
;
779 static char *cpu_sub_arch_name
= NULL
;
781 /* CPU feature flags. */
782 static i386_cpu_flags cpu_arch_flags
= CPU_UNKNOWN_FLAGS
;
784 /* If we have selected a cpu we are generating instructions for. */
785 static int cpu_arch_tune_set
= 0;
787 /* Cpu we are generating instructions for. */
788 enum processor_type cpu_arch_tune
= PROCESSOR_UNKNOWN
;
790 /* CPU feature flags of cpu we are generating instructions for. */
791 static i386_cpu_flags cpu_arch_tune_flags
;
793 /* CPU instruction set architecture used. */
794 enum processor_type cpu_arch_isa
= PROCESSOR_UNKNOWN
;
796 /* CPU feature flags of instruction set architecture used. */
797 i386_cpu_flags cpu_arch_isa_flags
;
799 /* If set, conditional jumps are not automatically promoted to handle
800 larger than a byte offset. */
801 static unsigned int no_cond_jump_promotion
= 0;
803 /* Encode SSE instructions with VEX prefix. */
804 static unsigned int sse2avx
;
806 /* Encode scalar AVX instructions with specific vector length. */
813 /* Encode VEX WIG instructions with specific vex.w. */
820 /* Encode scalar EVEX LIG instructions with specific vector length. */
828 /* Encode EVEX WIG instructions with specific evex.w. */
835 /* Value to encode in EVEX RC bits, for SAE-only instructions. */
836 static enum rc_type evexrcig
= rne
;
838 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
839 static symbolS
*GOT_symbol
;
841 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
842 unsigned int x86_dwarf2_return_column
;
844 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
845 int x86_cie_data_alignment
;
847 /* Interface to relax_segment.
848 There are 3 major relax states for 386 jump insns because the
849 different types of jumps add different sizes to frags when we're
850 figuring out what sort of jump to choose to reach a given label.
852 BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING are used to align
853 branches which are handled by md_estimate_size_before_relax() and
854 i386_generic_table_relax_frag(). */
857 #define UNCOND_JUMP 0
859 #define COND_JUMP86 2
860 #define BRANCH_PADDING 3
861 #define BRANCH_PREFIX 4
862 #define FUSED_JCC_PADDING 5
867 #define SMALL16 (SMALL | CODE16)
869 #define BIG16 (BIG | CODE16)
873 #define INLINE __inline__
879 #define ENCODE_RELAX_STATE(type, size) \
880 ((relax_substateT) (((type) << 2) | (size)))
881 #define TYPE_FROM_RELAX_STATE(s) \
883 #define DISP_SIZE_FROM_RELAX_STATE(s) \
884 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
886 /* This table is used by relax_frag to promote short jumps to long
887 ones where necessary. SMALL (short) jumps may be promoted to BIG
888 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
889 don't allow a short jump in a 32 bit code segment to be promoted to
890 a 16 bit offset jump because it's slower (requires data size
891 prefix), and doesn't work, unless the destination is in the bottom
892 64k of the code segment (The top 16 bits of eip are zeroed). */
894 const relax_typeS md_relax_table
[] =
897 1) most positive reach of this state,
898 2) most negative reach of this state,
899 3) how many bytes this mode will have in the variable part of the frag
900 4) which index into the table to try if we can't fit into this one. */
902 /* UNCOND_JUMP states. */
903 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
904 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
905 /* dword jmp adds 4 bytes to frag:
906 0 extra opcode bytes, 4 displacement bytes. */
908 /* word jmp adds 2 byte2 to frag:
909 0 extra opcode bytes, 2 displacement bytes. */
912 /* COND_JUMP states. */
913 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
914 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
915 /* dword conditionals adds 5 bytes to frag:
916 1 extra opcode byte, 4 displacement bytes. */
918 /* word conditionals add 3 bytes to frag:
919 1 extra opcode byte, 2 displacement bytes. */
922 /* COND_JUMP86 states. */
923 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
924 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
925 /* dword conditionals adds 5 bytes to frag:
926 1 extra opcode byte, 4 displacement bytes. */
928 /* word conditionals add 4 bytes to frag:
929 1 displacement byte and a 3 byte long branch insn. */
933 static const arch_entry cpu_arch
[] =
935 /* Do not replace the first two entries - i386_target_format()
936 relies on them being there in this order. */
937 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32
,
938 CPU_GENERIC32_FLAGS
, 0 },
939 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64
,
940 CPU_GENERIC64_FLAGS
, 0 },
941 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN
,
943 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN
,
945 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN
,
947 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386
,
949 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486
,
951 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM
,
953 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO
,
955 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM
,
957 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO
,
958 CPU_PENTIUMPRO_FLAGS
, 0 },
959 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO
,
961 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO
,
963 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4
,
965 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA
,
967 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA
,
968 CPU_NOCONA_FLAGS
, 0 },
969 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE
,
971 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE
,
973 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2
,
974 CPU_CORE2_FLAGS
, 1 },
975 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2
,
976 CPU_CORE2_FLAGS
, 0 },
977 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7
,
978 CPU_COREI7_FLAGS
, 0 },
979 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM
,
981 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM
,
983 { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU
,
984 CPU_IAMCU_FLAGS
, 0 },
985 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6
,
987 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6
,
989 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON
,
990 CPU_ATHLON_FLAGS
, 0 },
991 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8
,
993 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8
,
995 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8
,
997 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10
,
998 CPU_AMDFAM10_FLAGS
, 0 },
999 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD
,
1000 CPU_BDVER1_FLAGS
, 0 },
1001 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD
,
1002 CPU_BDVER2_FLAGS
, 0 },
1003 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD
,
1004 CPU_BDVER3_FLAGS
, 0 },
1005 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD
,
1006 CPU_BDVER4_FLAGS
, 0 },
1007 { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER
,
1008 CPU_ZNVER1_FLAGS
, 0 },
1009 { STRING_COMMA_LEN ("znver2"), PROCESSOR_ZNVER
,
1010 CPU_ZNVER2_FLAGS
, 0 },
1011 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT
,
1012 CPU_BTVER1_FLAGS
, 0 },
1013 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT
,
1014 CPU_BTVER2_FLAGS
, 0 },
1015 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN
,
1016 CPU_8087_FLAGS
, 0 },
1017 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN
,
1019 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN
,
1021 { STRING_COMMA_LEN (".687"), PROCESSOR_UNKNOWN
,
1023 { STRING_COMMA_LEN (".cmov"), PROCESSOR_UNKNOWN
,
1024 CPU_CMOV_FLAGS
, 0 },
1025 { STRING_COMMA_LEN (".fxsr"), PROCESSOR_UNKNOWN
,
1026 CPU_FXSR_FLAGS
, 0 },
1027 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN
,
1029 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN
,
1031 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN
,
1032 CPU_SSE2_FLAGS
, 0 },
1033 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN
,
1034 CPU_SSE3_FLAGS
, 0 },
1035 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN
,
1036 CPU_SSE4A_FLAGS
, 0 },
1037 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN
,
1038 CPU_SSSE3_FLAGS
, 0 },
1039 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN
,
1040 CPU_SSE4_1_FLAGS
, 0 },
1041 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN
,
1042 CPU_SSE4_2_FLAGS
, 0 },
1043 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN
,
1044 CPU_SSE4_2_FLAGS
, 0 },
1045 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN
,
1047 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN
,
1048 CPU_AVX2_FLAGS
, 0 },
1049 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN
,
1050 CPU_AVX512F_FLAGS
, 0 },
1051 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN
,
1052 CPU_AVX512CD_FLAGS
, 0 },
1053 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN
,
1054 CPU_AVX512ER_FLAGS
, 0 },
1055 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN
,
1056 CPU_AVX512PF_FLAGS
, 0 },
1057 { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN
,
1058 CPU_AVX512DQ_FLAGS
, 0 },
1059 { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN
,
1060 CPU_AVX512BW_FLAGS
, 0 },
1061 { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN
,
1062 CPU_AVX512VL_FLAGS
, 0 },
1063 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN
,
1065 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN
,
1066 CPU_VMFUNC_FLAGS
, 0 },
1067 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN
,
1069 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN
,
1070 CPU_XSAVE_FLAGS
, 0 },
1071 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN
,
1072 CPU_XSAVEOPT_FLAGS
, 0 },
1073 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN
,
1074 CPU_XSAVEC_FLAGS
, 0 },
1075 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN
,
1076 CPU_XSAVES_FLAGS
, 0 },
1077 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN
,
1079 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN
,
1080 CPU_PCLMUL_FLAGS
, 0 },
1081 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN
,
1082 CPU_PCLMUL_FLAGS
, 1 },
1083 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN
,
1084 CPU_FSGSBASE_FLAGS
, 0 },
1085 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN
,
1086 CPU_RDRND_FLAGS
, 0 },
1087 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN
,
1088 CPU_F16C_FLAGS
, 0 },
1089 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN
,
1090 CPU_BMI2_FLAGS
, 0 },
1091 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN
,
1093 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN
,
1094 CPU_FMA4_FLAGS
, 0 },
1095 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN
,
1097 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN
,
1099 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN
,
1100 CPU_MOVBE_FLAGS
, 0 },
1101 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN
,
1102 CPU_CX16_FLAGS
, 0 },
1103 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN
,
1105 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN
,
1106 CPU_LZCNT_FLAGS
, 0 },
1107 { STRING_COMMA_LEN (".popcnt"), PROCESSOR_UNKNOWN
,
1108 CPU_POPCNT_FLAGS
, 0 },
1109 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN
,
1111 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN
,
1113 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN
,
1114 CPU_INVPCID_FLAGS
, 0 },
1115 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN
,
1116 CPU_CLFLUSH_FLAGS
, 0 },
1117 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN
,
1119 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN
,
1120 CPU_SYSCALL_FLAGS
, 0 },
1121 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN
,
1122 CPU_RDTSCP_FLAGS
, 0 },
1123 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN
,
1124 CPU_3DNOW_FLAGS
, 0 },
1125 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN
,
1126 CPU_3DNOWA_FLAGS
, 0 },
1127 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN
,
1128 CPU_PADLOCK_FLAGS
, 0 },
1129 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN
,
1130 CPU_SVME_FLAGS
, 1 },
1131 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN
,
1132 CPU_SVME_FLAGS
, 0 },
1133 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN
,
1134 CPU_SSE4A_FLAGS
, 0 },
1135 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN
,
1137 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN
,
1139 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN
,
1141 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN
,
1143 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN
,
1144 CPU_RDSEED_FLAGS
, 0 },
1145 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN
,
1146 CPU_PRFCHW_FLAGS
, 0 },
1147 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN
,
1148 CPU_SMAP_FLAGS
, 0 },
1149 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN
,
1151 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN
,
1153 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN
,
1154 CPU_CLFLUSHOPT_FLAGS
, 0 },
1155 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN
,
1156 CPU_PREFETCHWT1_FLAGS
, 0 },
1157 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN
,
1159 { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN
,
1160 CPU_CLWB_FLAGS
, 0 },
1161 { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN
,
1162 CPU_AVX512IFMA_FLAGS
, 0 },
1163 { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN
,
1164 CPU_AVX512VBMI_FLAGS
, 0 },
1165 { STRING_COMMA_LEN (".avx512_4fmaps"), PROCESSOR_UNKNOWN
,
1166 CPU_AVX512_4FMAPS_FLAGS
, 0 },
1167 { STRING_COMMA_LEN (".avx512_4vnniw"), PROCESSOR_UNKNOWN
,
1168 CPU_AVX512_4VNNIW_FLAGS
, 0 },
1169 { STRING_COMMA_LEN (".avx512_vpopcntdq"), PROCESSOR_UNKNOWN
,
1170 CPU_AVX512_VPOPCNTDQ_FLAGS
, 0 },
1171 { STRING_COMMA_LEN (".avx512_vbmi2"), PROCESSOR_UNKNOWN
,
1172 CPU_AVX512_VBMI2_FLAGS
, 0 },
1173 { STRING_COMMA_LEN (".avx512_vnni"), PROCESSOR_UNKNOWN
,
1174 CPU_AVX512_VNNI_FLAGS
, 0 },
1175 { STRING_COMMA_LEN (".avx512_bitalg"), PROCESSOR_UNKNOWN
,
1176 CPU_AVX512_BITALG_FLAGS
, 0 },
1177 { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN
,
1178 CPU_CLZERO_FLAGS
, 0 },
1179 { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN
,
1180 CPU_MWAITX_FLAGS
, 0 },
1181 { STRING_COMMA_LEN (".ospke"), PROCESSOR_UNKNOWN
,
1182 CPU_OSPKE_FLAGS
, 0 },
1183 { STRING_COMMA_LEN (".rdpid"), PROCESSOR_UNKNOWN
,
1184 CPU_RDPID_FLAGS
, 0 },
1185 { STRING_COMMA_LEN (".ptwrite"), PROCESSOR_UNKNOWN
,
1186 CPU_PTWRITE_FLAGS
, 0 },
1187 { STRING_COMMA_LEN (".ibt"), PROCESSOR_UNKNOWN
,
1189 { STRING_COMMA_LEN (".shstk"), PROCESSOR_UNKNOWN
,
1190 CPU_SHSTK_FLAGS
, 0 },
1191 { STRING_COMMA_LEN (".gfni"), PROCESSOR_UNKNOWN
,
1192 CPU_GFNI_FLAGS
, 0 },
1193 { STRING_COMMA_LEN (".vaes"), PROCESSOR_UNKNOWN
,
1194 CPU_VAES_FLAGS
, 0 },
1195 { STRING_COMMA_LEN (".vpclmulqdq"), PROCESSOR_UNKNOWN
,
1196 CPU_VPCLMULQDQ_FLAGS
, 0 },
1197 { STRING_COMMA_LEN (".wbnoinvd"), PROCESSOR_UNKNOWN
,
1198 CPU_WBNOINVD_FLAGS
, 0 },
1199 { STRING_COMMA_LEN (".pconfig"), PROCESSOR_UNKNOWN
,
1200 CPU_PCONFIG_FLAGS
, 0 },
1201 { STRING_COMMA_LEN (".waitpkg"), PROCESSOR_UNKNOWN
,
1202 CPU_WAITPKG_FLAGS
, 0 },
1203 { STRING_COMMA_LEN (".cldemote"), PROCESSOR_UNKNOWN
,
1204 CPU_CLDEMOTE_FLAGS
, 0 },
1205 { STRING_COMMA_LEN (".movdiri"), PROCESSOR_UNKNOWN
,
1206 CPU_MOVDIRI_FLAGS
, 0 },
1207 { STRING_COMMA_LEN (".movdir64b"), PROCESSOR_UNKNOWN
,
1208 CPU_MOVDIR64B_FLAGS
, 0 },
1209 { STRING_COMMA_LEN (".avx512_bf16"), PROCESSOR_UNKNOWN
,
1210 CPU_AVX512_BF16_FLAGS
, 0 },
1211 { STRING_COMMA_LEN (".avx512_vp2intersect"), PROCESSOR_UNKNOWN
,
1212 CPU_AVX512_VP2INTERSECT_FLAGS
, 0 },
1213 { STRING_COMMA_LEN (".enqcmd"), PROCESSOR_UNKNOWN
,
1214 CPU_ENQCMD_FLAGS
, 0 },
1215 { STRING_COMMA_LEN (".serialize"), PROCESSOR_UNKNOWN
,
1216 CPU_SERIALIZE_FLAGS
, 0 },
1217 { STRING_COMMA_LEN (".rdpru"), PROCESSOR_UNKNOWN
,
1218 CPU_RDPRU_FLAGS
, 0 },
1219 { STRING_COMMA_LEN (".mcommit"), PROCESSOR_UNKNOWN
,
1220 CPU_MCOMMIT_FLAGS
, 0 },
1221 { STRING_COMMA_LEN (".sev_es"), PROCESSOR_UNKNOWN
,
1222 CPU_SEV_ES_FLAGS
, 0 },
1223 { STRING_COMMA_LEN (".tsxldtrk"), PROCESSOR_UNKNOWN
,
1224 CPU_TSXLDTRK_FLAGS
, 0 },
1227 static const noarch_entry cpu_noarch
[] =
1229 { STRING_COMMA_LEN ("no87"), CPU_ANY_X87_FLAGS
},
1230 { STRING_COMMA_LEN ("no287"), CPU_ANY_287_FLAGS
},
1231 { STRING_COMMA_LEN ("no387"), CPU_ANY_387_FLAGS
},
1232 { STRING_COMMA_LEN ("no687"), CPU_ANY_687_FLAGS
},
1233 { STRING_COMMA_LEN ("nocmov"), CPU_ANY_CMOV_FLAGS
},
1234 { STRING_COMMA_LEN ("nofxsr"), CPU_ANY_FXSR_FLAGS
},
1235 { STRING_COMMA_LEN ("nommx"), CPU_ANY_MMX_FLAGS
},
1236 { STRING_COMMA_LEN ("nosse"), CPU_ANY_SSE_FLAGS
},
1237 { STRING_COMMA_LEN ("nosse2"), CPU_ANY_SSE2_FLAGS
},
1238 { STRING_COMMA_LEN ("nosse3"), CPU_ANY_SSE3_FLAGS
},
1239 { STRING_COMMA_LEN ("nosse4a"), CPU_ANY_SSE4A_FLAGS
},
1240 { STRING_COMMA_LEN ("nossse3"), CPU_ANY_SSSE3_FLAGS
},
1241 { STRING_COMMA_LEN ("nosse4.1"), CPU_ANY_SSE4_1_FLAGS
},
1242 { STRING_COMMA_LEN ("nosse4.2"), CPU_ANY_SSE4_2_FLAGS
},
1243 { STRING_COMMA_LEN ("nosse4"), CPU_ANY_SSE4_1_FLAGS
},
1244 { STRING_COMMA_LEN ("noavx"), CPU_ANY_AVX_FLAGS
},
1245 { STRING_COMMA_LEN ("noavx2"), CPU_ANY_AVX2_FLAGS
},
1246 { STRING_COMMA_LEN ("noavx512f"), CPU_ANY_AVX512F_FLAGS
},
1247 { STRING_COMMA_LEN ("noavx512cd"), CPU_ANY_AVX512CD_FLAGS
},
1248 { STRING_COMMA_LEN ("noavx512er"), CPU_ANY_AVX512ER_FLAGS
},
1249 { STRING_COMMA_LEN ("noavx512pf"), CPU_ANY_AVX512PF_FLAGS
},
1250 { STRING_COMMA_LEN ("noavx512dq"), CPU_ANY_AVX512DQ_FLAGS
},
1251 { STRING_COMMA_LEN ("noavx512bw"), CPU_ANY_AVX512BW_FLAGS
},
1252 { STRING_COMMA_LEN ("noavx512vl"), CPU_ANY_AVX512VL_FLAGS
},
1253 { STRING_COMMA_LEN ("noavx512ifma"), CPU_ANY_AVX512IFMA_FLAGS
},
1254 { STRING_COMMA_LEN ("noavx512vbmi"), CPU_ANY_AVX512VBMI_FLAGS
},
1255 { STRING_COMMA_LEN ("noavx512_4fmaps"), CPU_ANY_AVX512_4FMAPS_FLAGS
},
1256 { STRING_COMMA_LEN ("noavx512_4vnniw"), CPU_ANY_AVX512_4VNNIW_FLAGS
},
1257 { STRING_COMMA_LEN ("noavx512_vpopcntdq"), CPU_ANY_AVX512_VPOPCNTDQ_FLAGS
},
1258 { STRING_COMMA_LEN ("noavx512_vbmi2"), CPU_ANY_AVX512_VBMI2_FLAGS
},
1259 { STRING_COMMA_LEN ("noavx512_vnni"), CPU_ANY_AVX512_VNNI_FLAGS
},
1260 { STRING_COMMA_LEN ("noavx512_bitalg"), CPU_ANY_AVX512_BITALG_FLAGS
},
1261 { STRING_COMMA_LEN ("noibt"), CPU_ANY_IBT_FLAGS
},
1262 { STRING_COMMA_LEN ("noshstk"), CPU_ANY_SHSTK_FLAGS
},
1263 { STRING_COMMA_LEN ("nomovdiri"), CPU_ANY_MOVDIRI_FLAGS
},
1264 { STRING_COMMA_LEN ("nomovdir64b"), CPU_ANY_MOVDIR64B_FLAGS
},
1265 { STRING_COMMA_LEN ("noavx512_bf16"), CPU_ANY_AVX512_BF16_FLAGS
},
1266 { STRING_COMMA_LEN ("noavx512_vp2intersect"),
1267 CPU_ANY_AVX512_VP2INTERSECT_FLAGS
},
1268 { STRING_COMMA_LEN ("noenqcmd"), CPU_ANY_ENQCMD_FLAGS
},
1269 { STRING_COMMA_LEN ("noserialize"), CPU_ANY_SERIALIZE_FLAGS
},
1270 { STRING_COMMA_LEN ("notsxldtrk"), CPU_ANY_TSXLDTRK_FLAGS
},
1274 /* Like s_lcomm_internal in gas/read.c but the alignment string
1275 is allowed to be optional. */
1278 pe_lcomm_internal (int needs_align
, symbolS
*symbolP
, addressT size
)
1285 && *input_line_pointer
== ',')
1287 align
= parse_align (needs_align
- 1);
1289 if (align
== (addressT
) -1)
1304 bss_alloc (symbolP
, size
, align
);
1309 pe_lcomm (int needs_align
)
1311 s_comm_internal (needs_align
* 2, pe_lcomm_internal
);
1315 const pseudo_typeS md_pseudo_table
[] =
1317 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
1318 {"align", s_align_bytes
, 0},
1320 {"align", s_align_ptwo
, 0},
1322 {"arch", set_cpu_arch
, 0},
1326 {"lcomm", pe_lcomm
, 1},
1328 {"ffloat", float_cons
, 'f'},
1329 {"dfloat", float_cons
, 'd'},
1330 {"tfloat", float_cons
, 'x'},
1332 {"slong", signed_cons
, 4},
1333 {"noopt", s_ignore
, 0},
1334 {"optim", s_ignore
, 0},
1335 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
1336 {"code16", set_code_flag
, CODE_16BIT
},
1337 {"code32", set_code_flag
, CODE_32BIT
},
1339 {"code64", set_code_flag
, CODE_64BIT
},
1341 {"intel_syntax", set_intel_syntax
, 1},
1342 {"att_syntax", set_intel_syntax
, 0},
1343 {"intel_mnemonic", set_intel_mnemonic
, 1},
1344 {"att_mnemonic", set_intel_mnemonic
, 0},
1345 {"allow_index_reg", set_allow_index_reg
, 1},
1346 {"disallow_index_reg", set_allow_index_reg
, 0},
1347 {"sse_check", set_check
, 0},
1348 {"operand_check", set_check
, 1},
1349 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1350 {"largecomm", handle_large_common
, 0},
1352 {"file", dwarf2_directive_file
, 0},
1353 {"loc", dwarf2_directive_loc
, 0},
1354 {"loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0},
1357 {"secrel32", pe_directive_secrel
, 0},
1362 /* For interface with expression (). */
1363 extern char *input_line_pointer
;
1365 /* Hash table for instruction mnemonic lookup. */
1366 static struct hash_control
*op_hash
;
1368 /* Hash table for register lookup. */
1369 static struct hash_control
*reg_hash
;
1371 /* Various efficient no-op patterns for aligning code labels.
1372 Note: Don't try to assemble the instructions in the comments.
1373 0L and 0w are not legal. */
1374 static const unsigned char f32_1
[] =
1376 static const unsigned char f32_2
[] =
1377 {0x66,0x90}; /* xchg %ax,%ax */
1378 static const unsigned char f32_3
[] =
1379 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1380 static const unsigned char f32_4
[] =
1381 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1382 static const unsigned char f32_6
[] =
1383 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1384 static const unsigned char f32_7
[] =
1385 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1386 static const unsigned char f16_3
[] =
1387 {0x8d,0x74,0x00}; /* lea 0(%si),%si */
1388 static const unsigned char f16_4
[] =
1389 {0x8d,0xb4,0x00,0x00}; /* lea 0W(%si),%si */
1390 static const unsigned char jump_disp8
[] =
1391 {0xeb}; /* jmp disp8 */
1392 static const unsigned char jump32_disp32
[] =
1393 {0xe9}; /* jmp disp32 */
1394 static const unsigned char jump16_disp32
[] =
1395 {0x66,0xe9}; /* jmp disp32 */
1396 /* 32-bit NOPs patterns. */
1397 static const unsigned char *const f32_patt
[] = {
1398 f32_1
, f32_2
, f32_3
, f32_4
, NULL
, f32_6
, f32_7
1400 /* 16-bit NOPs patterns. */
1401 static const unsigned char *const f16_patt
[] = {
1402 f32_1
, f32_2
, f16_3
, f16_4
1404 /* nopl (%[re]ax) */
1405 static const unsigned char alt_3
[] =
1407 /* nopl 0(%[re]ax) */
1408 static const unsigned char alt_4
[] =
1409 {0x0f,0x1f,0x40,0x00};
1410 /* nopl 0(%[re]ax,%[re]ax,1) */
1411 static const unsigned char alt_5
[] =
1412 {0x0f,0x1f,0x44,0x00,0x00};
1413 /* nopw 0(%[re]ax,%[re]ax,1) */
1414 static const unsigned char alt_6
[] =
1415 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1416 /* nopl 0L(%[re]ax) */
1417 static const unsigned char alt_7
[] =
1418 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1419 /* nopl 0L(%[re]ax,%[re]ax,1) */
1420 static const unsigned char alt_8
[] =
1421 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1422 /* nopw 0L(%[re]ax,%[re]ax,1) */
1423 static const unsigned char alt_9
[] =
1424 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1425 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1426 static const unsigned char alt_10
[] =
1427 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1428 /* data16 nopw %cs:0L(%eax,%eax,1) */
1429 static const unsigned char alt_11
[] =
1430 {0x66,0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1431 /* 32-bit and 64-bit NOPs patterns. */
1432 static const unsigned char *const alt_patt
[] = {
1433 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
1434 alt_9
, alt_10
, alt_11
1437 /* Genenerate COUNT bytes of NOPs to WHERE from PATT with the maximum
1438 size of a single NOP instruction MAX_SINGLE_NOP_SIZE. */
1441 i386_output_nops (char *where
, const unsigned char *const *patt
,
1442 int count
, int max_single_nop_size
)
1445 /* Place the longer NOP first. */
1448 const unsigned char *nops
;
1450 if (max_single_nop_size
< 1)
1452 as_fatal (_("i386_output_nops called to generate nops of at most %d bytes!"),
1453 max_single_nop_size
);
1457 nops
= patt
[max_single_nop_size
- 1];
1459 /* Use the smaller one if the requsted one isn't available. */
1462 max_single_nop_size
--;
1463 nops
= patt
[max_single_nop_size
- 1];
1466 last
= count
% max_single_nop_size
;
1469 for (offset
= 0; offset
< count
; offset
+= max_single_nop_size
)
1470 memcpy (where
+ offset
, nops
, max_single_nop_size
);
1474 nops
= patt
[last
- 1];
1477 /* Use the smaller one plus one-byte NOP if the needed one
1480 nops
= patt
[last
- 1];
1481 memcpy (where
+ offset
, nops
, last
);
1482 where
[offset
+ last
] = *patt
[0];
1485 memcpy (where
+ offset
, nops
, last
);
1490 fits_in_imm7 (offsetT num
)
1492 return (num
& 0x7f) == num
;
1496 fits_in_imm31 (offsetT num
)
1498 return (num
& 0x7fffffff) == num
;
1501 /* Genenerate COUNT bytes of NOPs to WHERE with the maximum size of a
1502 single NOP instruction LIMIT. */
1505 i386_generate_nops (fragS
*fragP
, char *where
, offsetT count
, int limit
)
1507 const unsigned char *const *patt
= NULL
;
1508 int max_single_nop_size
;
1509 /* Maximum number of NOPs before switching to jump over NOPs. */
1510 int max_number_of_nops
;
1512 switch (fragP
->fr_type
)
1517 case rs_machine_dependent
:
1518 /* Allow NOP padding for jumps and calls. */
1519 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
1520 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
)
1527 /* We need to decide which NOP sequence to use for 32bit and
1528 64bit. When -mtune= is used:
1530 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1531 PROCESSOR_GENERIC32, f32_patt will be used.
1532 2. For the rest, alt_patt will be used.
1534 When -mtune= isn't used, alt_patt will be used if
1535 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
1538 When -march= or .arch is used, we can't use anything beyond
1539 cpu_arch_isa_flags. */
1541 if (flag_code
== CODE_16BIT
)
1544 max_single_nop_size
= sizeof (f16_patt
) / sizeof (f16_patt
[0]);
1545 /* Limit number of NOPs to 2 in 16-bit mode. */
1546 max_number_of_nops
= 2;
1550 if (fragP
->tc_frag_data
.isa
== PROCESSOR_UNKNOWN
)
1552 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1553 switch (cpu_arch_tune
)
1555 case PROCESSOR_UNKNOWN
:
1556 /* We use cpu_arch_isa_flags to check if we SHOULD
1557 optimize with nops. */
1558 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1563 case PROCESSOR_PENTIUM4
:
1564 case PROCESSOR_NOCONA
:
1565 case PROCESSOR_CORE
:
1566 case PROCESSOR_CORE2
:
1567 case PROCESSOR_COREI7
:
1568 case PROCESSOR_L1OM
:
1569 case PROCESSOR_K1OM
:
1570 case PROCESSOR_GENERIC64
:
1572 case PROCESSOR_ATHLON
:
1574 case PROCESSOR_AMDFAM10
:
1576 case PROCESSOR_ZNVER
:
1580 case PROCESSOR_I386
:
1581 case PROCESSOR_I486
:
1582 case PROCESSOR_PENTIUM
:
1583 case PROCESSOR_PENTIUMPRO
:
1584 case PROCESSOR_IAMCU
:
1585 case PROCESSOR_GENERIC32
:
1592 switch (fragP
->tc_frag_data
.tune
)
1594 case PROCESSOR_UNKNOWN
:
1595 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1596 PROCESSOR_UNKNOWN. */
1600 case PROCESSOR_I386
:
1601 case PROCESSOR_I486
:
1602 case PROCESSOR_PENTIUM
:
1603 case PROCESSOR_IAMCU
:
1605 case PROCESSOR_ATHLON
:
1607 case PROCESSOR_AMDFAM10
:
1609 case PROCESSOR_ZNVER
:
1611 case PROCESSOR_GENERIC32
:
1612 /* We use cpu_arch_isa_flags to check if we CAN optimize
1614 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1619 case PROCESSOR_PENTIUMPRO
:
1620 case PROCESSOR_PENTIUM4
:
1621 case PROCESSOR_NOCONA
:
1622 case PROCESSOR_CORE
:
1623 case PROCESSOR_CORE2
:
1624 case PROCESSOR_COREI7
:
1625 case PROCESSOR_L1OM
:
1626 case PROCESSOR_K1OM
:
1627 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1632 case PROCESSOR_GENERIC64
:
1638 if (patt
== f32_patt
)
1640 max_single_nop_size
= sizeof (f32_patt
) / sizeof (f32_patt
[0]);
1641 /* Limit number of NOPs to 2 for older processors. */
1642 max_number_of_nops
= 2;
1646 max_single_nop_size
= sizeof (alt_patt
) / sizeof (alt_patt
[0]);
1647 /* Limit number of NOPs to 7 for newer processors. */
1648 max_number_of_nops
= 7;
1653 limit
= max_single_nop_size
;
1655 if (fragP
->fr_type
== rs_fill_nop
)
1657 /* Output NOPs for .nop directive. */
1658 if (limit
> max_single_nop_size
)
1660 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
1661 _("invalid single nop size: %d "
1662 "(expect within [0, %d])"),
1663 limit
, max_single_nop_size
);
1667 else if (fragP
->fr_type
!= rs_machine_dependent
)
1668 fragP
->fr_var
= count
;
1670 if ((count
/ max_single_nop_size
) > max_number_of_nops
)
1672 /* Generate jump over NOPs. */
1673 offsetT disp
= count
- 2;
1674 if (fits_in_imm7 (disp
))
1676 /* Use "jmp disp8" if possible. */
1678 where
[0] = jump_disp8
[0];
1684 unsigned int size_of_jump
;
1686 if (flag_code
== CODE_16BIT
)
1688 where
[0] = jump16_disp32
[0];
1689 where
[1] = jump16_disp32
[1];
1694 where
[0] = jump32_disp32
[0];
1698 count
-= size_of_jump
+ 4;
1699 if (!fits_in_imm31 (count
))
1701 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
1702 _("jump over nop padding out of range"));
1706 md_number_to_chars (where
+ size_of_jump
, count
, 4);
1707 where
+= size_of_jump
+ 4;
1711 /* Generate multiple NOPs. */
1712 i386_output_nops (where
, patt
, count
, limit
);
1716 operand_type_all_zero (const union i386_operand_type
*x
)
1718 switch (ARRAY_SIZE(x
->array
))
1729 return !x
->array
[0];
1736 operand_type_set (union i386_operand_type
*x
, unsigned int v
)
1738 switch (ARRAY_SIZE(x
->array
))
1754 x
->bitfield
.class = ClassNone
;
1755 x
->bitfield
.instance
= InstanceNone
;
1759 operand_type_equal (const union i386_operand_type
*x
,
1760 const union i386_operand_type
*y
)
1762 switch (ARRAY_SIZE(x
->array
))
1765 if (x
->array
[2] != y
->array
[2])
1769 if (x
->array
[1] != y
->array
[1])
1773 return x
->array
[0] == y
->array
[0];
1781 cpu_flags_all_zero (const union i386_cpu_flags
*x
)
1783 switch (ARRAY_SIZE(x
->array
))
1798 return !x
->array
[0];
1805 cpu_flags_equal (const union i386_cpu_flags
*x
,
1806 const union i386_cpu_flags
*y
)
1808 switch (ARRAY_SIZE(x
->array
))
1811 if (x
->array
[3] != y
->array
[3])
1815 if (x
->array
[2] != y
->array
[2])
1819 if (x
->array
[1] != y
->array
[1])
1823 return x
->array
[0] == y
->array
[0];
1831 cpu_flags_check_cpu64 (i386_cpu_flags f
)
1833 return !((flag_code
== CODE_64BIT
&& f
.bitfield
.cpuno64
)
1834 || (flag_code
!= CODE_64BIT
&& f
.bitfield
.cpu64
));
1837 static INLINE i386_cpu_flags
1838 cpu_flags_and (i386_cpu_flags x
, i386_cpu_flags y
)
1840 switch (ARRAY_SIZE (x
.array
))
1843 x
.array
[3] &= y
.array
[3];
1846 x
.array
[2] &= y
.array
[2];
1849 x
.array
[1] &= y
.array
[1];
1852 x
.array
[0] &= y
.array
[0];
1860 static INLINE i386_cpu_flags
1861 cpu_flags_or (i386_cpu_flags x
, i386_cpu_flags y
)
1863 switch (ARRAY_SIZE (x
.array
))
1866 x
.array
[3] |= y
.array
[3];
1869 x
.array
[2] |= y
.array
[2];
1872 x
.array
[1] |= y
.array
[1];
1875 x
.array
[0] |= y
.array
[0];
1883 static INLINE i386_cpu_flags
1884 cpu_flags_and_not (i386_cpu_flags x
, i386_cpu_flags y
)
1886 switch (ARRAY_SIZE (x
.array
))
1889 x
.array
[3] &= ~y
.array
[3];
1892 x
.array
[2] &= ~y
.array
[2];
1895 x
.array
[1] &= ~y
.array
[1];
1898 x
.array
[0] &= ~y
.array
[0];
1906 static const i386_cpu_flags avx512
= CPU_ANY_AVX512F_FLAGS
;
1908 #define CPU_FLAGS_ARCH_MATCH 0x1
1909 #define CPU_FLAGS_64BIT_MATCH 0x2
1911 #define CPU_FLAGS_PERFECT_MATCH \
1912 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_64BIT_MATCH)
1914 /* Return CPU flags match bits. */
1917 cpu_flags_match (const insn_template
*t
)
1919 i386_cpu_flags x
= t
->cpu_flags
;
1920 int match
= cpu_flags_check_cpu64 (x
) ? CPU_FLAGS_64BIT_MATCH
: 0;
1922 x
.bitfield
.cpu64
= 0;
1923 x
.bitfield
.cpuno64
= 0;
1925 if (cpu_flags_all_zero (&x
))
1927 /* This instruction is available on all archs. */
1928 match
|= CPU_FLAGS_ARCH_MATCH
;
1932 /* This instruction is available only on some archs. */
1933 i386_cpu_flags cpu
= cpu_arch_flags
;
1935 /* AVX512VL is no standalone feature - match it and then strip it. */
1936 if (x
.bitfield
.cpuavx512vl
&& !cpu
.bitfield
.cpuavx512vl
)
1938 x
.bitfield
.cpuavx512vl
= 0;
1940 cpu
= cpu_flags_and (x
, cpu
);
1941 if (!cpu_flags_all_zero (&cpu
))
1943 if (x
.bitfield
.cpuavx
)
1945 /* We need to check a few extra flags with AVX. */
1946 if (cpu
.bitfield
.cpuavx
1947 && (!t
->opcode_modifier
.sse2avx
1948 || (sse2avx
&& !i
.prefix
[DATA_PREFIX
]))
1949 && (!x
.bitfield
.cpuaes
|| cpu
.bitfield
.cpuaes
)
1950 && (!x
.bitfield
.cpugfni
|| cpu
.bitfield
.cpugfni
)
1951 && (!x
.bitfield
.cpupclmul
|| cpu
.bitfield
.cpupclmul
))
1952 match
|= CPU_FLAGS_ARCH_MATCH
;
1954 else if (x
.bitfield
.cpuavx512f
)
1956 /* We need to check a few extra flags with AVX512F. */
1957 if (cpu
.bitfield
.cpuavx512f
1958 && (!x
.bitfield
.cpugfni
|| cpu
.bitfield
.cpugfni
)
1959 && (!x
.bitfield
.cpuvaes
|| cpu
.bitfield
.cpuvaes
)
1960 && (!x
.bitfield
.cpuvpclmulqdq
|| cpu
.bitfield
.cpuvpclmulqdq
))
1961 match
|= CPU_FLAGS_ARCH_MATCH
;
1964 match
|= CPU_FLAGS_ARCH_MATCH
;
1970 static INLINE i386_operand_type
1971 operand_type_and (i386_operand_type x
, i386_operand_type y
)
1973 if (x
.bitfield
.class != y
.bitfield
.class)
1974 x
.bitfield
.class = ClassNone
;
1975 if (x
.bitfield
.instance
!= y
.bitfield
.instance
)
1976 x
.bitfield
.instance
= InstanceNone
;
1978 switch (ARRAY_SIZE (x
.array
))
1981 x
.array
[2] &= y
.array
[2];
1984 x
.array
[1] &= y
.array
[1];
1987 x
.array
[0] &= y
.array
[0];
1995 static INLINE i386_operand_type
1996 operand_type_and_not (i386_operand_type x
, i386_operand_type y
)
1998 gas_assert (y
.bitfield
.class == ClassNone
);
1999 gas_assert (y
.bitfield
.instance
== InstanceNone
);
2001 switch (ARRAY_SIZE (x
.array
))
2004 x
.array
[2] &= ~y
.array
[2];
2007 x
.array
[1] &= ~y
.array
[1];
2010 x
.array
[0] &= ~y
.array
[0];
2018 static INLINE i386_operand_type
2019 operand_type_or (i386_operand_type x
, i386_operand_type y
)
2021 gas_assert (x
.bitfield
.class == ClassNone
||
2022 y
.bitfield
.class == ClassNone
||
2023 x
.bitfield
.class == y
.bitfield
.class);
2024 gas_assert (x
.bitfield
.instance
== InstanceNone
||
2025 y
.bitfield
.instance
== InstanceNone
||
2026 x
.bitfield
.instance
== y
.bitfield
.instance
);
2028 switch (ARRAY_SIZE (x
.array
))
2031 x
.array
[2] |= y
.array
[2];
2034 x
.array
[1] |= y
.array
[1];
2037 x
.array
[0] |= y
.array
[0];
2045 static INLINE i386_operand_type
2046 operand_type_xor (i386_operand_type x
, i386_operand_type y
)
2048 gas_assert (y
.bitfield
.class == ClassNone
);
2049 gas_assert (y
.bitfield
.instance
== InstanceNone
);
2051 switch (ARRAY_SIZE (x
.array
))
2054 x
.array
[2] ^= y
.array
[2];
2057 x
.array
[1] ^= y
.array
[1];
2060 x
.array
[0] ^= y
.array
[0];
2068 static const i386_operand_type disp16
= OPERAND_TYPE_DISP16
;
2069 static const i386_operand_type disp32
= OPERAND_TYPE_DISP32
;
2070 static const i386_operand_type disp32s
= OPERAND_TYPE_DISP32S
;
2071 static const i386_operand_type disp16_32
= OPERAND_TYPE_DISP16_32
;
2072 static const i386_operand_type anydisp
= OPERAND_TYPE_ANYDISP
;
2073 static const i386_operand_type anyimm
= OPERAND_TYPE_ANYIMM
;
2074 static const i386_operand_type regxmm
= OPERAND_TYPE_REGXMM
;
2075 static const i386_operand_type regmask
= OPERAND_TYPE_REGMASK
;
2076 static const i386_operand_type imm8
= OPERAND_TYPE_IMM8
;
2077 static const i386_operand_type imm8s
= OPERAND_TYPE_IMM8S
;
2078 static const i386_operand_type imm16
= OPERAND_TYPE_IMM16
;
2079 static const i386_operand_type imm32
= OPERAND_TYPE_IMM32
;
2080 static const i386_operand_type imm32s
= OPERAND_TYPE_IMM32S
;
2081 static const i386_operand_type imm64
= OPERAND_TYPE_IMM64
;
2082 static const i386_operand_type imm16_32
= OPERAND_TYPE_IMM16_32
;
2083 static const i386_operand_type imm16_32s
= OPERAND_TYPE_IMM16_32S
;
2084 static const i386_operand_type imm16_32_32s
= OPERAND_TYPE_IMM16_32_32S
;
2095 operand_type_check (i386_operand_type t
, enum operand_type c
)
2100 return t
.bitfield
.class == Reg
;
2103 return (t
.bitfield
.imm8
2107 || t
.bitfield
.imm32s
2108 || t
.bitfield
.imm64
);
2111 return (t
.bitfield
.disp8
2112 || t
.bitfield
.disp16
2113 || t
.bitfield
.disp32
2114 || t
.bitfield
.disp32s
2115 || t
.bitfield
.disp64
);
2118 return (t
.bitfield
.disp8
2119 || t
.bitfield
.disp16
2120 || t
.bitfield
.disp32
2121 || t
.bitfield
.disp32s
2122 || t
.bitfield
.disp64
2123 || t
.bitfield
.baseindex
);
2132 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit/80bit size
2133 between operand GIVEN and opeand WANTED for instruction template T. */
2136 match_operand_size (const insn_template
*t
, unsigned int wanted
,
2139 return !((i
.types
[given
].bitfield
.byte
2140 && !t
->operand_types
[wanted
].bitfield
.byte
)
2141 || (i
.types
[given
].bitfield
.word
2142 && !t
->operand_types
[wanted
].bitfield
.word
)
2143 || (i
.types
[given
].bitfield
.dword
2144 && !t
->operand_types
[wanted
].bitfield
.dword
)
2145 || (i
.types
[given
].bitfield
.qword
2146 && !t
->operand_types
[wanted
].bitfield
.qword
)
2147 || (i
.types
[given
].bitfield
.tbyte
2148 && !t
->operand_types
[wanted
].bitfield
.tbyte
));
2151 /* Return 1 if there is no conflict in SIMD register between operand
2152 GIVEN and opeand WANTED for instruction template T. */
2155 match_simd_size (const insn_template
*t
, unsigned int wanted
,
2158 return !((i
.types
[given
].bitfield
.xmmword
2159 && !t
->operand_types
[wanted
].bitfield
.xmmword
)
2160 || (i
.types
[given
].bitfield
.ymmword
2161 && !t
->operand_types
[wanted
].bitfield
.ymmword
)
2162 || (i
.types
[given
].bitfield
.zmmword
2163 && !t
->operand_types
[wanted
].bitfield
.zmmword
));
2166 /* Return 1 if there is no conflict in any size between operand GIVEN
2167 and opeand WANTED for instruction template T. */
2170 match_mem_size (const insn_template
*t
, unsigned int wanted
,
2173 return (match_operand_size (t
, wanted
, given
)
2174 && !((i
.types
[given
].bitfield
.unspecified
2176 && !t
->operand_types
[wanted
].bitfield
.unspecified
)
2177 || (i
.types
[given
].bitfield
.fword
2178 && !t
->operand_types
[wanted
].bitfield
.fword
)
2179 /* For scalar opcode templates to allow register and memory
2180 operands at the same time, some special casing is needed
2181 here. Also for v{,p}broadcast*, {,v}pmov{s,z}*, and
2182 down-conversion vpmov*. */
2183 || ((t
->operand_types
[wanted
].bitfield
.class == RegSIMD
2184 && t
->operand_types
[wanted
].bitfield
.byte
2185 + t
->operand_types
[wanted
].bitfield
.word
2186 + t
->operand_types
[wanted
].bitfield
.dword
2187 + t
->operand_types
[wanted
].bitfield
.qword
2188 > !!t
->opcode_modifier
.broadcast
)
2189 ? (i
.types
[given
].bitfield
.xmmword
2190 || i
.types
[given
].bitfield
.ymmword
2191 || i
.types
[given
].bitfield
.zmmword
)
2192 : !match_simd_size(t
, wanted
, given
))));
2195 /* Return value has MATCH_STRAIGHT set if there is no size conflict on any
2196 operands for instruction template T, and it has MATCH_REVERSE set if there
2197 is no size conflict on any operands for the template with operands reversed
2198 (and the template allows for reversing in the first place). */
2200 #define MATCH_STRAIGHT 1
2201 #define MATCH_REVERSE 2
2203 static INLINE
unsigned int
2204 operand_size_match (const insn_template
*t
)
2206 unsigned int j
, match
= MATCH_STRAIGHT
;
2208 /* Don't check non-absolute jump instructions. */
2209 if (t
->opcode_modifier
.jump
2210 && t
->opcode_modifier
.jump
!= JUMP_ABSOLUTE
)
2213 /* Check memory and accumulator operand size. */
2214 for (j
= 0; j
< i
.operands
; j
++)
2216 if (i
.types
[j
].bitfield
.class != Reg
2217 && i
.types
[j
].bitfield
.class != RegSIMD
2218 && t
->opcode_modifier
.anysize
)
2221 if (t
->operand_types
[j
].bitfield
.class == Reg
2222 && !match_operand_size (t
, j
, j
))
2228 if (t
->operand_types
[j
].bitfield
.class == RegSIMD
2229 && !match_simd_size (t
, j
, j
))
2235 if (t
->operand_types
[j
].bitfield
.instance
== Accum
2236 && (!match_operand_size (t
, j
, j
) || !match_simd_size (t
, j
, j
)))
2242 if ((i
.flags
[j
] & Operand_Mem
) && !match_mem_size (t
, j
, j
))
2249 if (!t
->opcode_modifier
.d
)
2253 i
.error
= operand_size_mismatch
;
2257 /* Check reverse. */
2258 gas_assert (i
.operands
>= 2 && i
.operands
<= 3);
2260 for (j
= 0; j
< i
.operands
; j
++)
2262 unsigned int given
= i
.operands
- j
- 1;
2264 if (t
->operand_types
[j
].bitfield
.class == Reg
2265 && !match_operand_size (t
, j
, given
))
2268 if (t
->operand_types
[j
].bitfield
.class == RegSIMD
2269 && !match_simd_size (t
, j
, given
))
2272 if (t
->operand_types
[j
].bitfield
.instance
== Accum
2273 && (!match_operand_size (t
, j
, given
)
2274 || !match_simd_size (t
, j
, given
)))
2277 if ((i
.flags
[given
] & Operand_Mem
) && !match_mem_size (t
, j
, given
))
2281 return match
| MATCH_REVERSE
;
2285 operand_type_match (i386_operand_type overlap
,
2286 i386_operand_type given
)
2288 i386_operand_type temp
= overlap
;
2290 temp
.bitfield
.unspecified
= 0;
2291 temp
.bitfield
.byte
= 0;
2292 temp
.bitfield
.word
= 0;
2293 temp
.bitfield
.dword
= 0;
2294 temp
.bitfield
.fword
= 0;
2295 temp
.bitfield
.qword
= 0;
2296 temp
.bitfield
.tbyte
= 0;
2297 temp
.bitfield
.xmmword
= 0;
2298 temp
.bitfield
.ymmword
= 0;
2299 temp
.bitfield
.zmmword
= 0;
2300 if (operand_type_all_zero (&temp
))
2303 if (given
.bitfield
.baseindex
== overlap
.bitfield
.baseindex
)
2307 i
.error
= operand_type_mismatch
;
2311 /* If given types g0 and g1 are registers they must be of the same type
2312 unless the expected operand type register overlap is null.
2313 Some Intel syntax memory operand size checking also happens here. */
2316 operand_type_register_match (i386_operand_type g0
,
2317 i386_operand_type t0
,
2318 i386_operand_type g1
,
2319 i386_operand_type t1
)
2321 if (g0
.bitfield
.class != Reg
2322 && g0
.bitfield
.class != RegSIMD
2323 && (!operand_type_check (g0
, anymem
)
2324 || g0
.bitfield
.unspecified
2325 || (t0
.bitfield
.class != Reg
2326 && t0
.bitfield
.class != RegSIMD
)))
2329 if (g1
.bitfield
.class != Reg
2330 && g1
.bitfield
.class != RegSIMD
2331 && (!operand_type_check (g1
, anymem
)
2332 || g1
.bitfield
.unspecified
2333 || (t1
.bitfield
.class != Reg
2334 && t1
.bitfield
.class != RegSIMD
)))
2337 if (g0
.bitfield
.byte
== g1
.bitfield
.byte
2338 && g0
.bitfield
.word
== g1
.bitfield
.word
2339 && g0
.bitfield
.dword
== g1
.bitfield
.dword
2340 && g0
.bitfield
.qword
== g1
.bitfield
.qword
2341 && g0
.bitfield
.xmmword
== g1
.bitfield
.xmmword
2342 && g0
.bitfield
.ymmword
== g1
.bitfield
.ymmword
2343 && g0
.bitfield
.zmmword
== g1
.bitfield
.zmmword
)
2346 if (!(t0
.bitfield
.byte
& t1
.bitfield
.byte
)
2347 && !(t0
.bitfield
.word
& t1
.bitfield
.word
)
2348 && !(t0
.bitfield
.dword
& t1
.bitfield
.dword
)
2349 && !(t0
.bitfield
.qword
& t1
.bitfield
.qword
)
2350 && !(t0
.bitfield
.xmmword
& t1
.bitfield
.xmmword
)
2351 && !(t0
.bitfield
.ymmword
& t1
.bitfield
.ymmword
)
2352 && !(t0
.bitfield
.zmmword
& t1
.bitfield
.zmmword
))
2355 i
.error
= register_type_mismatch
;
2360 static INLINE
unsigned int
2361 register_number (const reg_entry
*r
)
2363 unsigned int nr
= r
->reg_num
;
2365 if (r
->reg_flags
& RegRex
)
2368 if (r
->reg_flags
& RegVRex
)
2374 static INLINE
unsigned int
2375 mode_from_disp_size (i386_operand_type t
)
2377 if (t
.bitfield
.disp8
)
2379 else if (t
.bitfield
.disp16
2380 || t
.bitfield
.disp32
2381 || t
.bitfield
.disp32s
)
2388 fits_in_signed_byte (addressT num
)
2390 return num
+ 0x80 <= 0xff;
2394 fits_in_unsigned_byte (addressT num
)
2400 fits_in_unsigned_word (addressT num
)
2402 return num
<= 0xffff;
2406 fits_in_signed_word (addressT num
)
2408 return num
+ 0x8000 <= 0xffff;
2412 fits_in_signed_long (addressT num ATTRIBUTE_UNUSED
)
2417 return num
+ 0x80000000 <= 0xffffffff;
2419 } /* fits_in_signed_long() */
2422 fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED
)
2427 return num
<= 0xffffffff;
2429 } /* fits_in_unsigned_long() */
2432 fits_in_disp8 (offsetT num
)
2434 int shift
= i
.memshift
;
2440 mask
= (1 << shift
) - 1;
2442 /* Return 0 if NUM isn't properly aligned. */
2446 /* Check if NUM will fit in 8bit after shift. */
2447 return fits_in_signed_byte (num
>> shift
);
2451 fits_in_imm4 (offsetT num
)
2453 return (num
& 0xf) == num
;
2456 static i386_operand_type
2457 smallest_imm_type (offsetT num
)
2459 i386_operand_type t
;
2461 operand_type_set (&t
, 0);
2462 t
.bitfield
.imm64
= 1;
2464 if (cpu_arch_tune
!= PROCESSOR_I486
&& num
== 1)
2466 /* This code is disabled on the 486 because all the Imm1 forms
2467 in the opcode table are slower on the i486. They're the
2468 versions with the implicitly specified single-position
2469 displacement, which has another syntax if you really want to
2471 t
.bitfield
.imm1
= 1;
2472 t
.bitfield
.imm8
= 1;
2473 t
.bitfield
.imm8s
= 1;
2474 t
.bitfield
.imm16
= 1;
2475 t
.bitfield
.imm32
= 1;
2476 t
.bitfield
.imm32s
= 1;
2478 else if (fits_in_signed_byte (num
))
2480 t
.bitfield
.imm8
= 1;
2481 t
.bitfield
.imm8s
= 1;
2482 t
.bitfield
.imm16
= 1;
2483 t
.bitfield
.imm32
= 1;
2484 t
.bitfield
.imm32s
= 1;
2486 else if (fits_in_unsigned_byte (num
))
2488 t
.bitfield
.imm8
= 1;
2489 t
.bitfield
.imm16
= 1;
2490 t
.bitfield
.imm32
= 1;
2491 t
.bitfield
.imm32s
= 1;
2493 else if (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
2495 t
.bitfield
.imm16
= 1;
2496 t
.bitfield
.imm32
= 1;
2497 t
.bitfield
.imm32s
= 1;
2499 else if (fits_in_signed_long (num
))
2501 t
.bitfield
.imm32
= 1;
2502 t
.bitfield
.imm32s
= 1;
2504 else if (fits_in_unsigned_long (num
))
2505 t
.bitfield
.imm32
= 1;
2511 offset_in_range (offsetT val
, int size
)
2517 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
2518 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
2519 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
2521 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
2527 /* If BFD64, sign extend val for 32bit address mode. */
2528 if (flag_code
!= CODE_64BIT
2529 || i
.prefix
[ADDR_PREFIX
])
2530 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
2531 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
2534 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
2536 char buf1
[40], buf2
[40];
2538 sprint_value (buf1
, val
);
2539 sprint_value (buf2
, val
& mask
);
2540 as_warn (_("%s shortened to %s"), buf1
, buf2
);
2555 a. PREFIX_EXIST if attempting to add a prefix where one from the
2556 same class already exists.
2557 b. PREFIX_LOCK if lock prefix is added.
2558 c. PREFIX_REP if rep/repne prefix is added.
2559 d. PREFIX_DS if ds prefix is added.
2560 e. PREFIX_OTHER if other prefix is added.
2563 static enum PREFIX_GROUP
2564 add_prefix (unsigned int prefix
)
2566 enum PREFIX_GROUP ret
= PREFIX_OTHER
;
2569 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
2570 && flag_code
== CODE_64BIT
)
2572 if ((i
.prefix
[REX_PREFIX
] & prefix
& REX_W
)
2573 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_R
)
2574 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_X
)
2575 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_B
))
2586 case DS_PREFIX_OPCODE
:
2589 case CS_PREFIX_OPCODE
:
2590 case ES_PREFIX_OPCODE
:
2591 case FS_PREFIX_OPCODE
:
2592 case GS_PREFIX_OPCODE
:
2593 case SS_PREFIX_OPCODE
:
2597 case REPNE_PREFIX_OPCODE
:
2598 case REPE_PREFIX_OPCODE
:
2603 case LOCK_PREFIX_OPCODE
:
2612 case ADDR_PREFIX_OPCODE
:
2616 case DATA_PREFIX_OPCODE
:
2620 if (i
.prefix
[q
] != 0)
2628 i
.prefix
[q
] |= prefix
;
2631 as_bad (_("same type of prefix used twice"));
2637 update_code_flag (int value
, int check
)
2639 PRINTF_LIKE ((*as_error
));
2641 flag_code
= (enum flag_code
) value
;
2642 if (flag_code
== CODE_64BIT
)
2644 cpu_arch_flags
.bitfield
.cpu64
= 1;
2645 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2649 cpu_arch_flags
.bitfield
.cpu64
= 0;
2650 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2652 if (value
== CODE_64BIT
&& !cpu_arch_flags
.bitfield
.cpulm
)
2655 as_error
= as_fatal
;
2658 (*as_error
) (_("64bit mode not supported on `%s'."),
2659 cpu_arch_name
? cpu_arch_name
: default_arch
);
2661 if (value
== CODE_32BIT
&& !cpu_arch_flags
.bitfield
.cpui386
)
2664 as_error
= as_fatal
;
2667 (*as_error
) (_("32bit mode not supported on `%s'."),
2668 cpu_arch_name
? cpu_arch_name
: default_arch
);
2670 stackop_size
= '\0';
2674 set_code_flag (int value
)
2676 update_code_flag (value
, 0);
2680 set_16bit_gcc_code_flag (int new_code_flag
)
2682 flag_code
= (enum flag_code
) new_code_flag
;
2683 if (flag_code
!= CODE_16BIT
)
2685 cpu_arch_flags
.bitfield
.cpu64
= 0;
2686 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2687 stackop_size
= LONG_MNEM_SUFFIX
;
2691 set_intel_syntax (int syntax_flag
)
2693 /* Find out if register prefixing is specified. */
2694 int ask_naked_reg
= 0;
2697 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2700 int e
= get_symbol_name (&string
);
2702 if (strcmp (string
, "prefix") == 0)
2704 else if (strcmp (string
, "noprefix") == 0)
2707 as_bad (_("bad argument to syntax directive."));
2708 (void) restore_line_pointer (e
);
2710 demand_empty_rest_of_line ();
2712 intel_syntax
= syntax_flag
;
2714 if (ask_naked_reg
== 0)
2715 allow_naked_reg
= (intel_syntax
2716 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
2718 allow_naked_reg
= (ask_naked_reg
< 0);
2720 expr_set_rank (O_full_ptr
, syntax_flag
? 10 : 0);
2722 identifier_chars
['%'] = intel_syntax
&& allow_naked_reg
? '%' : 0;
2723 identifier_chars
['$'] = intel_syntax
? '$' : 0;
2724 register_prefix
= allow_naked_reg
? "" : "%";
2728 set_intel_mnemonic (int mnemonic_flag
)
2730 intel_mnemonic
= mnemonic_flag
;
2734 set_allow_index_reg (int flag
)
2736 allow_index_reg
= flag
;
2740 set_check (int what
)
2742 enum check_kind
*kind
;
2747 kind
= &operand_check
;
2758 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2761 int e
= get_symbol_name (&string
);
2763 if (strcmp (string
, "none") == 0)
2765 else if (strcmp (string
, "warning") == 0)
2766 *kind
= check_warning
;
2767 else if (strcmp (string
, "error") == 0)
2768 *kind
= check_error
;
2770 as_bad (_("bad argument to %s_check directive."), str
);
2771 (void) restore_line_pointer (e
);
2774 as_bad (_("missing argument for %s_check directive"), str
);
2776 demand_empty_rest_of_line ();
2780 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED
,
2781 i386_cpu_flags new_flag ATTRIBUTE_UNUSED
)
2783 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2784 static const char *arch
;
2786 /* Intel LIOM is only supported on ELF. */
2792 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2793 use default_arch. */
2794 arch
= cpu_arch_name
;
2796 arch
= default_arch
;
2799 /* If we are targeting Intel MCU, we must enable it. */
2800 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_IAMCU
2801 || new_flag
.bitfield
.cpuiamcu
)
2804 /* If we are targeting Intel L1OM, we must enable it. */
2805 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_L1OM
2806 || new_flag
.bitfield
.cpul1om
)
2809 /* If we are targeting Intel K1OM, we must enable it. */
2810 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_K1OM
2811 || new_flag
.bitfield
.cpuk1om
)
2814 as_bad (_("`%s' is not supported on `%s'"), name
, arch
);
2819 set_cpu_arch (int dummy ATTRIBUTE_UNUSED
)
2823 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2826 int e
= get_symbol_name (&string
);
2828 i386_cpu_flags flags
;
2830 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
2832 if (strcmp (string
, cpu_arch
[j
].name
) == 0)
2834 check_cpu_arch_compatible (string
, cpu_arch
[j
].flags
);
2838 cpu_arch_name
= cpu_arch
[j
].name
;
2839 cpu_sub_arch_name
= NULL
;
2840 cpu_arch_flags
= cpu_arch
[j
].flags
;
2841 if (flag_code
== CODE_64BIT
)
2843 cpu_arch_flags
.bitfield
.cpu64
= 1;
2844 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2848 cpu_arch_flags
.bitfield
.cpu64
= 0;
2849 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2851 cpu_arch_isa
= cpu_arch
[j
].type
;
2852 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
2853 if (!cpu_arch_tune_set
)
2855 cpu_arch_tune
= cpu_arch_isa
;
2856 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
2861 flags
= cpu_flags_or (cpu_arch_flags
,
2864 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2866 if (cpu_sub_arch_name
)
2868 char *name
= cpu_sub_arch_name
;
2869 cpu_sub_arch_name
= concat (name
,
2871 (const char *) NULL
);
2875 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
2876 cpu_arch_flags
= flags
;
2877 cpu_arch_isa_flags
= flags
;
2881 = cpu_flags_or (cpu_arch_isa_flags
,
2883 (void) restore_line_pointer (e
);
2884 demand_empty_rest_of_line ();
2889 if (*string
== '.' && j
>= ARRAY_SIZE (cpu_arch
))
2891 /* Disable an ISA extension. */
2892 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
2893 if (strcmp (string
+ 1, cpu_noarch
[j
].name
) == 0)
2895 flags
= cpu_flags_and_not (cpu_arch_flags
,
2896 cpu_noarch
[j
].flags
);
2897 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2899 if (cpu_sub_arch_name
)
2901 char *name
= cpu_sub_arch_name
;
2902 cpu_sub_arch_name
= concat (name
, string
,
2903 (const char *) NULL
);
2907 cpu_sub_arch_name
= xstrdup (string
);
2908 cpu_arch_flags
= flags
;
2909 cpu_arch_isa_flags
= flags
;
2911 (void) restore_line_pointer (e
);
2912 demand_empty_rest_of_line ();
2916 j
= ARRAY_SIZE (cpu_arch
);
2919 if (j
>= ARRAY_SIZE (cpu_arch
))
2920 as_bad (_("no such architecture: `%s'"), string
);
2922 *input_line_pointer
= e
;
2925 as_bad (_("missing cpu architecture"));
2927 no_cond_jump_promotion
= 0;
2928 if (*input_line_pointer
== ','
2929 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
2934 ++input_line_pointer
;
2935 e
= get_symbol_name (&string
);
2937 if (strcmp (string
, "nojumps") == 0)
2938 no_cond_jump_promotion
= 1;
2939 else if (strcmp (string
, "jumps") == 0)
2942 as_bad (_("no such architecture modifier: `%s'"), string
);
2944 (void) restore_line_pointer (e
);
2947 demand_empty_rest_of_line ();
2950 enum bfd_architecture
2953 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2955 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2956 || flag_code
!= CODE_64BIT
)
2957 as_fatal (_("Intel L1OM is 64bit ELF only"));
2958 return bfd_arch_l1om
;
2960 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2962 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2963 || flag_code
!= CODE_64BIT
)
2964 as_fatal (_("Intel K1OM is 64bit ELF only"));
2965 return bfd_arch_k1om
;
2967 else if (cpu_arch_isa
== PROCESSOR_IAMCU
)
2969 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2970 || flag_code
== CODE_64BIT
)
2971 as_fatal (_("Intel MCU is 32bit ELF only"));
2972 return bfd_arch_iamcu
;
2975 return bfd_arch_i386
;
2981 if (!strncmp (default_arch
, "x86_64", 6))
2983 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2985 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2986 || default_arch
[6] != '\0')
2987 as_fatal (_("Intel L1OM is 64bit ELF only"));
2988 return bfd_mach_l1om
;
2990 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2992 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2993 || default_arch
[6] != '\0')
2994 as_fatal (_("Intel K1OM is 64bit ELF only"));
2995 return bfd_mach_k1om
;
2997 else if (default_arch
[6] == '\0')
2998 return bfd_mach_x86_64
;
3000 return bfd_mach_x64_32
;
3002 else if (!strcmp (default_arch
, "i386")
3003 || !strcmp (default_arch
, "iamcu"))
3005 if (cpu_arch_isa
== PROCESSOR_IAMCU
)
3007 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
3008 as_fatal (_("Intel MCU is 32bit ELF only"));
3009 return bfd_mach_i386_iamcu
;
3012 return bfd_mach_i386_i386
;
3015 as_fatal (_("unknown architecture"));
3021 const char *hash_err
;
3023 /* Support pseudo prefixes like {disp32}. */
3024 lex_type
['{'] = LEX_BEGIN_NAME
;
3026 /* Initialize op_hash hash table. */
3027 op_hash
= hash_new ();
3030 const insn_template
*optab
;
3031 templates
*core_optab
;
3033 /* Setup for loop. */
3035 core_optab
= XNEW (templates
);
3036 core_optab
->start
= optab
;
3041 if (optab
->name
== NULL
3042 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
3044 /* different name --> ship out current template list;
3045 add to hash table; & begin anew. */
3046 core_optab
->end
= optab
;
3047 hash_err
= hash_insert (op_hash
,
3049 (void *) core_optab
);
3052 as_fatal (_("can't hash %s: %s"),
3056 if (optab
->name
== NULL
)
3058 core_optab
= XNEW (templates
);
3059 core_optab
->start
= optab
;
3064 /* Initialize reg_hash hash table. */
3065 reg_hash
= hash_new ();
3067 const reg_entry
*regtab
;
3068 unsigned int regtab_size
= i386_regtab_size
;
3070 for (regtab
= i386_regtab
; regtab_size
--; regtab
++)
3072 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (void *) regtab
);
3074 as_fatal (_("can't hash %s: %s"),
3080 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
3085 for (c
= 0; c
< 256; c
++)
3090 mnemonic_chars
[c
] = c
;
3091 register_chars
[c
] = c
;
3092 operand_chars
[c
] = c
;
3094 else if (ISLOWER (c
))
3096 mnemonic_chars
[c
] = c
;
3097 register_chars
[c
] = c
;
3098 operand_chars
[c
] = c
;
3100 else if (ISUPPER (c
))
3102 mnemonic_chars
[c
] = TOLOWER (c
);
3103 register_chars
[c
] = mnemonic_chars
[c
];
3104 operand_chars
[c
] = c
;
3106 else if (c
== '{' || c
== '}')
3108 mnemonic_chars
[c
] = c
;
3109 operand_chars
[c
] = c
;
3112 if (ISALPHA (c
) || ISDIGIT (c
))
3113 identifier_chars
[c
] = c
;
3116 identifier_chars
[c
] = c
;
3117 operand_chars
[c
] = c
;
3122 identifier_chars
['@'] = '@';
3125 identifier_chars
['?'] = '?';
3126 operand_chars
['?'] = '?';
3128 digit_chars
['-'] = '-';
3129 mnemonic_chars
['_'] = '_';
3130 mnemonic_chars
['-'] = '-';
3131 mnemonic_chars
['.'] = '.';
3132 identifier_chars
['_'] = '_';
3133 identifier_chars
['.'] = '.';
3135 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
3136 operand_chars
[(unsigned char) *p
] = *p
;
3139 if (flag_code
== CODE_64BIT
)
3141 #if defined (OBJ_COFF) && defined (TE_PE)
3142 x86_dwarf2_return_column
= (OUTPUT_FLAVOR
== bfd_target_coff_flavour
3145 x86_dwarf2_return_column
= 16;
3147 x86_cie_data_alignment
= -8;
3151 x86_dwarf2_return_column
= 8;
3152 x86_cie_data_alignment
= -4;
3155 /* NB: FUSED_JCC_PADDING frag must have sufficient room so that it
3156 can be turned into BRANCH_PREFIX frag. */
3157 if (align_branch_prefix_size
> MAX_FUSED_JCC_PADDING_SIZE
)
3162 i386_print_statistics (FILE *file
)
3164 hash_print_statistics (file
, "i386 opcode", op_hash
);
3165 hash_print_statistics (file
, "i386 register", reg_hash
);
3170 /* Debugging routines for md_assemble. */
3171 static void pte (insn_template
*);
3172 static void pt (i386_operand_type
);
3173 static void pe (expressionS
*);
3174 static void ps (symbolS
*);
3177 pi (const char *line
, i386_insn
*x
)
3181 fprintf (stdout
, "%s: template ", line
);
3183 fprintf (stdout
, " address: base %s index %s scale %x\n",
3184 x
->base_reg
? x
->base_reg
->reg_name
: "none",
3185 x
->index_reg
? x
->index_reg
->reg_name
: "none",
3186 x
->log2_scale_factor
);
3187 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
3188 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
3189 fprintf (stdout
, " sib: base %x index %x scale %x\n",
3190 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
3191 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
3192 (x
->rex
& REX_W
) != 0,
3193 (x
->rex
& REX_R
) != 0,
3194 (x
->rex
& REX_X
) != 0,
3195 (x
->rex
& REX_B
) != 0);
3196 for (j
= 0; j
< x
->operands
; j
++)
3198 fprintf (stdout
, " #%d: ", j
+ 1);
3200 fprintf (stdout
, "\n");
3201 if (x
->types
[j
].bitfield
.class == Reg
3202 || x
->types
[j
].bitfield
.class == RegMMX
3203 || x
->types
[j
].bitfield
.class == RegSIMD
3204 || x
->types
[j
].bitfield
.class == RegMask
3205 || x
->types
[j
].bitfield
.class == SReg
3206 || x
->types
[j
].bitfield
.class == RegCR
3207 || x
->types
[j
].bitfield
.class == RegDR
3208 || x
->types
[j
].bitfield
.class == RegTR
3209 || x
->types
[j
].bitfield
.class == RegBND
)
3210 fprintf (stdout
, "%s\n", x
->op
[j
].regs
->reg_name
);
3211 if (operand_type_check (x
->types
[j
], imm
))
3213 if (operand_type_check (x
->types
[j
], disp
))
3214 pe (x
->op
[j
].disps
);
3219 pte (insn_template
*t
)
3222 fprintf (stdout
, " %d operands ", t
->operands
);
3223 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
3224 if (t
->extension_opcode
!= None
)
3225 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
3226 if (t
->opcode_modifier
.d
)
3227 fprintf (stdout
, "D");
3228 if (t
->opcode_modifier
.w
)
3229 fprintf (stdout
, "W");
3230 fprintf (stdout
, "\n");
3231 for (j
= 0; j
< t
->operands
; j
++)
3233 fprintf (stdout
, " #%d type ", j
+ 1);
3234 pt (t
->operand_types
[j
]);
3235 fprintf (stdout
, "\n");
3242 fprintf (stdout
, " operation %d\n", e
->X_op
);
3243 fprintf (stdout
, " add_number %ld (%lx)\n",
3244 (long) e
->X_add_number
, (long) e
->X_add_number
);
3245 if (e
->X_add_symbol
)
3247 fprintf (stdout
, " add_symbol ");
3248 ps (e
->X_add_symbol
);
3249 fprintf (stdout
, "\n");
3253 fprintf (stdout
, " op_symbol ");
3254 ps (e
->X_op_symbol
);
3255 fprintf (stdout
, "\n");
3262 fprintf (stdout
, "%s type %s%s",
3264 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
3265 segment_name (S_GET_SEGMENT (s
)));
3268 static struct type_name
3270 i386_operand_type mask
;
3273 const type_names
[] =
3275 { OPERAND_TYPE_REG8
, "r8" },
3276 { OPERAND_TYPE_REG16
, "r16" },
3277 { OPERAND_TYPE_REG32
, "r32" },
3278 { OPERAND_TYPE_REG64
, "r64" },
3279 { OPERAND_TYPE_ACC8
, "acc8" },
3280 { OPERAND_TYPE_ACC16
, "acc16" },
3281 { OPERAND_TYPE_ACC32
, "acc32" },
3282 { OPERAND_TYPE_ACC64
, "acc64" },
3283 { OPERAND_TYPE_IMM8
, "i8" },
3284 { OPERAND_TYPE_IMM8
, "i8s" },
3285 { OPERAND_TYPE_IMM16
, "i16" },
3286 { OPERAND_TYPE_IMM32
, "i32" },
3287 { OPERAND_TYPE_IMM32S
, "i32s" },
3288 { OPERAND_TYPE_IMM64
, "i64" },
3289 { OPERAND_TYPE_IMM1
, "i1" },
3290 { OPERAND_TYPE_BASEINDEX
, "BaseIndex" },
3291 { OPERAND_TYPE_DISP8
, "d8" },
3292 { OPERAND_TYPE_DISP16
, "d16" },
3293 { OPERAND_TYPE_DISP32
, "d32" },
3294 { OPERAND_TYPE_DISP32S
, "d32s" },
3295 { OPERAND_TYPE_DISP64
, "d64" },
3296 { OPERAND_TYPE_INOUTPORTREG
, "InOutPortReg" },
3297 { OPERAND_TYPE_SHIFTCOUNT
, "ShiftCount" },
3298 { OPERAND_TYPE_CONTROL
, "control reg" },
3299 { OPERAND_TYPE_TEST
, "test reg" },
3300 { OPERAND_TYPE_DEBUG
, "debug reg" },
3301 { OPERAND_TYPE_FLOATREG
, "FReg" },
3302 { OPERAND_TYPE_FLOATACC
, "FAcc" },
3303 { OPERAND_TYPE_SREG
, "SReg" },
3304 { OPERAND_TYPE_REGMMX
, "rMMX" },
3305 { OPERAND_TYPE_REGXMM
, "rXMM" },
3306 { OPERAND_TYPE_REGYMM
, "rYMM" },
3307 { OPERAND_TYPE_REGZMM
, "rZMM" },
3308 { OPERAND_TYPE_REGMASK
, "Mask reg" },
3312 pt (i386_operand_type t
)
3315 i386_operand_type a
;
3317 for (j
= 0; j
< ARRAY_SIZE (type_names
); j
++)
3319 a
= operand_type_and (t
, type_names
[j
].mask
);
3320 if (operand_type_equal (&a
, &type_names
[j
].mask
))
3321 fprintf (stdout
, "%s, ", type_names
[j
].name
);
3326 #endif /* DEBUG386 */
3328 static bfd_reloc_code_real_type
3329 reloc (unsigned int size
,
3332 bfd_reloc_code_real_type other
)
3334 if (other
!= NO_RELOC
)
3336 reloc_howto_type
*rel
;
3341 case BFD_RELOC_X86_64_GOT32
:
3342 return BFD_RELOC_X86_64_GOT64
;
3344 case BFD_RELOC_X86_64_GOTPLT64
:
3345 return BFD_RELOC_X86_64_GOTPLT64
;
3347 case BFD_RELOC_X86_64_PLTOFF64
:
3348 return BFD_RELOC_X86_64_PLTOFF64
;
3350 case BFD_RELOC_X86_64_GOTPC32
:
3351 other
= BFD_RELOC_X86_64_GOTPC64
;
3353 case BFD_RELOC_X86_64_GOTPCREL
:
3354 other
= BFD_RELOC_X86_64_GOTPCREL64
;
3356 case BFD_RELOC_X86_64_TPOFF32
:
3357 other
= BFD_RELOC_X86_64_TPOFF64
;
3359 case BFD_RELOC_X86_64_DTPOFF32
:
3360 other
= BFD_RELOC_X86_64_DTPOFF64
;
3366 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3367 if (other
== BFD_RELOC_SIZE32
)
3370 other
= BFD_RELOC_SIZE64
;
3373 as_bad (_("there are no pc-relative size relocations"));
3379 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
3380 if (size
== 4 && (flag_code
!= CODE_64BIT
|| disallow_64bit_reloc
))
3383 rel
= bfd_reloc_type_lookup (stdoutput
, other
);
3385 as_bad (_("unknown relocation (%u)"), other
);
3386 else if (size
!= bfd_get_reloc_size (rel
))
3387 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
3388 bfd_get_reloc_size (rel
),
3390 else if (pcrel
&& !rel
->pc_relative
)
3391 as_bad (_("non-pc-relative relocation for pc-relative field"));
3392 else if ((rel
->complain_on_overflow
== complain_overflow_signed
3394 || (rel
->complain_on_overflow
== complain_overflow_unsigned
3396 as_bad (_("relocated field and relocation type differ in signedness"));
3405 as_bad (_("there are no unsigned pc-relative relocations"));
3408 case 1: return BFD_RELOC_8_PCREL
;
3409 case 2: return BFD_RELOC_16_PCREL
;
3410 case 4: return BFD_RELOC_32_PCREL
;
3411 case 8: return BFD_RELOC_64_PCREL
;
3413 as_bad (_("cannot do %u byte pc-relative relocation"), size
);
3420 case 4: return BFD_RELOC_X86_64_32S
;
3425 case 1: return BFD_RELOC_8
;
3426 case 2: return BFD_RELOC_16
;
3427 case 4: return BFD_RELOC_32
;
3428 case 8: return BFD_RELOC_64
;
3430 as_bad (_("cannot do %s %u byte relocation"),
3431 sign
> 0 ? "signed" : "unsigned", size
);
3437 /* Here we decide which fixups can be adjusted to make them relative to
3438 the beginning of the section instead of the symbol. Basically we need
3439 to make sure that the dynamic relocations are done correctly, so in
3440 some cases we force the original symbol to be used. */
3443 tc_i386_fix_adjustable (fixS
*fixP ATTRIBUTE_UNUSED
)
3445 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3449 /* Don't adjust pc-relative references to merge sections in 64-bit
3451 if (use_rela_relocations
3452 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
3456 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
3457 and changed later by validate_fix. */
3458 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
3459 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
3462 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
3463 for size relocations. */
3464 if (fixP
->fx_r_type
== BFD_RELOC_SIZE32
3465 || fixP
->fx_r_type
== BFD_RELOC_SIZE64
3466 || fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
3467 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
3468 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32X
3469 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
3470 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
3471 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
3472 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
3473 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
3474 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
3475 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
3476 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
3477 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTDESC
3478 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_DESC_CALL
3479 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
3480 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
3481 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCRELX
3482 || fixP
->fx_r_type
== BFD_RELOC_X86_64_REX_GOTPCRELX
3483 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
3484 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
3485 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
3486 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
3487 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
3488 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
3489 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
3490 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
3491 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPC32_TLSDESC
3492 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSDESC_CALL
3493 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
3494 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
3501 intel_float_operand (const char *mnemonic
)
3503 /* Note that the value returned is meaningful only for opcodes with (memory)
3504 operands, hence the code here is free to improperly handle opcodes that
3505 have no operands (for better performance and smaller code). */
3507 if (mnemonic
[0] != 'f')
3508 return 0; /* non-math */
3510 switch (mnemonic
[1])
3512 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
3513 the fs segment override prefix not currently handled because no
3514 call path can make opcodes without operands get here */
3516 return 2 /* integer op */;
3518 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
3519 return 3; /* fldcw/fldenv */
3522 if (mnemonic
[2] != 'o' /* fnop */)
3523 return 3; /* non-waiting control op */
3526 if (mnemonic
[2] == 's')
3527 return 3; /* frstor/frstpm */
3530 if (mnemonic
[2] == 'a')
3531 return 3; /* fsave */
3532 if (mnemonic
[2] == 't')
3534 switch (mnemonic
[3])
3536 case 'c': /* fstcw */
3537 case 'd': /* fstdw */
3538 case 'e': /* fstenv */
3539 case 's': /* fsts[gw] */
3545 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
3546 return 0; /* fxsave/fxrstor are not really math ops */
3553 /* Build the VEX prefix. */
3556 build_vex_prefix (const insn_template
*t
)
3558 unsigned int register_specifier
;
3559 unsigned int implied_prefix
;
3560 unsigned int vector_length
;
3563 /* Check register specifier. */
3564 if (i
.vex
.register_specifier
)
3566 register_specifier
=
3567 ~register_number (i
.vex
.register_specifier
) & 0xf;
3568 gas_assert ((i
.vex
.register_specifier
->reg_flags
& RegVRex
) == 0);
3571 register_specifier
= 0xf;
3573 /* Use 2-byte VEX prefix by swapping destination and source operand
3574 if there are more than 1 register operand. */
3575 if (i
.reg_operands
> 1
3576 && i
.vec_encoding
!= vex_encoding_vex3
3577 && i
.dir_encoding
== dir_encoding_default
3578 && i
.operands
== i
.reg_operands
3579 && operand_type_equal (&i
.types
[0], &i
.types
[i
.operands
- 1])
3580 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3581 && (i
.tm
.opcode_modifier
.load
|| i
.tm
.opcode_modifier
.d
)
3584 unsigned int xchg
= i
.operands
- 1;
3585 union i386_op temp_op
;
3586 i386_operand_type temp_type
;
3588 temp_type
= i
.types
[xchg
];
3589 i
.types
[xchg
] = i
.types
[0];
3590 i
.types
[0] = temp_type
;
3591 temp_op
= i
.op
[xchg
];
3592 i
.op
[xchg
] = i
.op
[0];
3595 gas_assert (i
.rm
.mode
== 3);
3599 i
.rm
.regmem
= i
.rm
.reg
;
3602 if (i
.tm
.opcode_modifier
.d
)
3603 i
.tm
.base_opcode
^= (i
.tm
.base_opcode
& 0xee) != 0x6e
3604 ? Opcode_SIMD_FloatD
: Opcode_SIMD_IntD
;
3605 else /* Use the next insn. */
3609 /* Use 2-byte VEX prefix by swapping commutative source operands if there
3610 are no memory operands and at least 3 register ones. */
3611 if (i
.reg_operands
>= 3
3612 && i
.vec_encoding
!= vex_encoding_vex3
3613 && i
.reg_operands
== i
.operands
- i
.imm_operands
3614 && i
.tm
.opcode_modifier
.vex
3615 && i
.tm
.opcode_modifier
.commutative
3616 && (i
.tm
.opcode_modifier
.sse2avx
|| optimize
> 1)
3618 && i
.vex
.register_specifier
3619 && !(i
.vex
.register_specifier
->reg_flags
& RegRex
))
3621 unsigned int xchg
= i
.operands
- i
.reg_operands
;
3622 union i386_op temp_op
;
3623 i386_operand_type temp_type
;
3625 gas_assert (i
.tm
.opcode_modifier
.vexopcode
== VEX0F
);
3626 gas_assert (!i
.tm
.opcode_modifier
.sae
);
3627 gas_assert (operand_type_equal (&i
.types
[i
.operands
- 2],
3628 &i
.types
[i
.operands
- 3]));
3629 gas_assert (i
.rm
.mode
== 3);
3631 temp_type
= i
.types
[xchg
];
3632 i
.types
[xchg
] = i
.types
[xchg
+ 1];
3633 i
.types
[xchg
+ 1] = temp_type
;
3634 temp_op
= i
.op
[xchg
];
3635 i
.op
[xchg
] = i
.op
[xchg
+ 1];
3636 i
.op
[xchg
+ 1] = temp_op
;
3639 xchg
= i
.rm
.regmem
| 8;
3640 i
.rm
.regmem
= ~register_specifier
& 0xf;
3641 gas_assert (!(i
.rm
.regmem
& 8));
3642 i
.vex
.register_specifier
+= xchg
- i
.rm
.regmem
;
3643 register_specifier
= ~xchg
& 0xf;
3646 if (i
.tm
.opcode_modifier
.vex
== VEXScalar
)
3647 vector_length
= avxscalar
;
3648 else if (i
.tm
.opcode_modifier
.vex
== VEX256
)
3654 /* Determine vector length from the last multi-length vector
3657 for (op
= t
->operands
; op
--;)
3658 if (t
->operand_types
[op
].bitfield
.xmmword
3659 && t
->operand_types
[op
].bitfield
.ymmword
3660 && i
.types
[op
].bitfield
.ymmword
)
3667 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3672 case DATA_PREFIX_OPCODE
:
3675 case REPE_PREFIX_OPCODE
:
3678 case REPNE_PREFIX_OPCODE
:
3685 /* Check the REX.W bit and VEXW. */
3686 if (i
.tm
.opcode_modifier
.vexw
== VEXWIG
)
3687 w
= (vexwig
== vexw1
|| (i
.rex
& REX_W
)) ? 1 : 0;
3688 else if (i
.tm
.opcode_modifier
.vexw
)
3689 w
= i
.tm
.opcode_modifier
.vexw
== VEXW1
? 1 : 0;
3691 w
= (flag_code
== CODE_64BIT
? i
.rex
& REX_W
: vexwig
== vexw1
) ? 1 : 0;
3693 /* Use 2-byte VEX prefix if possible. */
3695 && i
.vec_encoding
!= vex_encoding_vex3
3696 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3697 && (i
.rex
& (REX_W
| REX_X
| REX_B
)) == 0)
3699 /* 2-byte VEX prefix. */
3703 i
.vex
.bytes
[0] = 0xc5;
3705 /* Check the REX.R bit. */
3706 r
= (i
.rex
& REX_R
) ? 0 : 1;
3707 i
.vex
.bytes
[1] = (r
<< 7
3708 | register_specifier
<< 3
3709 | vector_length
<< 2
3714 /* 3-byte VEX prefix. */
3719 switch (i
.tm
.opcode_modifier
.vexopcode
)
3723 i
.vex
.bytes
[0] = 0xc4;
3727 i
.vex
.bytes
[0] = 0xc4;
3731 i
.vex
.bytes
[0] = 0xc4;
3735 i
.vex
.bytes
[0] = 0x8f;
3739 i
.vex
.bytes
[0] = 0x8f;
3743 i
.vex
.bytes
[0] = 0x8f;
3749 /* The high 3 bits of the second VEX byte are 1's compliment
3750 of RXB bits from REX. */
3751 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3753 i
.vex
.bytes
[2] = (w
<< 7
3754 | register_specifier
<< 3
3755 | vector_length
<< 2
3760 static INLINE bfd_boolean
3761 is_evex_encoding (const insn_template
*t
)
3763 return t
->opcode_modifier
.evex
|| t
->opcode_modifier
.disp8memshift
3764 || t
->opcode_modifier
.broadcast
|| t
->opcode_modifier
.masking
3765 || t
->opcode_modifier
.sae
;
3768 static INLINE bfd_boolean
3769 is_any_vex_encoding (const insn_template
*t
)
3771 return t
->opcode_modifier
.vex
|| t
->opcode_modifier
.vexopcode
3772 || is_evex_encoding (t
);
3775 /* Build the EVEX prefix. */
3778 build_evex_prefix (void)
3780 unsigned int register_specifier
;
3781 unsigned int implied_prefix
;
3783 rex_byte vrex_used
= 0;
3785 /* Check register specifier. */
3786 if (i
.vex
.register_specifier
)
3788 gas_assert ((i
.vrex
& REX_X
) == 0);
3790 register_specifier
= i
.vex
.register_specifier
->reg_num
;
3791 if ((i
.vex
.register_specifier
->reg_flags
& RegRex
))
3792 register_specifier
+= 8;
3793 /* The upper 16 registers are encoded in the fourth byte of the
3795 if (!(i
.vex
.register_specifier
->reg_flags
& RegVRex
))
3796 i
.vex
.bytes
[3] = 0x8;
3797 register_specifier
= ~register_specifier
& 0xf;
3801 register_specifier
= 0xf;
3803 /* Encode upper 16 vector index register in the fourth byte of
3805 if (!(i
.vrex
& REX_X
))
3806 i
.vex
.bytes
[3] = 0x8;
3811 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3816 case DATA_PREFIX_OPCODE
:
3819 case REPE_PREFIX_OPCODE
:
3822 case REPNE_PREFIX_OPCODE
:
3829 /* 4 byte EVEX prefix. */
3831 i
.vex
.bytes
[0] = 0x62;
3834 switch (i
.tm
.opcode_modifier
.vexopcode
)
3850 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3852 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3854 /* The fifth bit of the second EVEX byte is 1's compliment of the
3855 REX_R bit in VREX. */
3856 if (!(i
.vrex
& REX_R
))
3857 i
.vex
.bytes
[1] |= 0x10;
3861 if ((i
.reg_operands
+ i
.imm_operands
) == i
.operands
)
3863 /* When all operands are registers, the REX_X bit in REX is not
3864 used. We reuse it to encode the upper 16 registers, which is
3865 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3866 as 1's compliment. */
3867 if ((i
.vrex
& REX_B
))
3870 i
.vex
.bytes
[1] &= ~0x40;
3874 /* EVEX instructions shouldn't need the REX prefix. */
3875 i
.vrex
&= ~vrex_used
;
3876 gas_assert (i
.vrex
== 0);
3878 /* Check the REX.W bit and VEXW. */
3879 if (i
.tm
.opcode_modifier
.vexw
== VEXWIG
)
3880 w
= (evexwig
== evexw1
|| (i
.rex
& REX_W
)) ? 1 : 0;
3881 else if (i
.tm
.opcode_modifier
.vexw
)
3882 w
= i
.tm
.opcode_modifier
.vexw
== VEXW1
? 1 : 0;
3884 w
= (flag_code
== CODE_64BIT
? i
.rex
& REX_W
: evexwig
== evexw1
) ? 1 : 0;
3886 /* Encode the U bit. */
3887 implied_prefix
|= 0x4;
3889 /* The third byte of the EVEX prefix. */
3890 i
.vex
.bytes
[2] = (w
<< 7 | register_specifier
<< 3 | implied_prefix
);
3892 /* The fourth byte of the EVEX prefix. */
3893 /* The zeroing-masking bit. */
3894 if (i
.mask
&& i
.mask
->zeroing
)
3895 i
.vex
.bytes
[3] |= 0x80;
3897 /* Don't always set the broadcast bit if there is no RC. */
3900 /* Encode the vector length. */
3901 unsigned int vec_length
;
3903 if (!i
.tm
.opcode_modifier
.evex
3904 || i
.tm
.opcode_modifier
.evex
== EVEXDYN
)
3908 /* Determine vector length from the last multi-length vector
3910 for (op
= i
.operands
; op
--;)
3911 if (i
.tm
.operand_types
[op
].bitfield
.xmmword
3912 + i
.tm
.operand_types
[op
].bitfield
.ymmword
3913 + i
.tm
.operand_types
[op
].bitfield
.zmmword
> 1)
3915 if (i
.types
[op
].bitfield
.zmmword
)
3917 i
.tm
.opcode_modifier
.evex
= EVEX512
;
3920 else if (i
.types
[op
].bitfield
.ymmword
)
3922 i
.tm
.opcode_modifier
.evex
= EVEX256
;
3925 else if (i
.types
[op
].bitfield
.xmmword
)
3927 i
.tm
.opcode_modifier
.evex
= EVEX128
;
3930 else if (i
.broadcast
&& (int) op
== i
.broadcast
->operand
)
3932 switch (i
.broadcast
->bytes
)
3935 i
.tm
.opcode_modifier
.evex
= EVEX512
;
3938 i
.tm
.opcode_modifier
.evex
= EVEX256
;
3941 i
.tm
.opcode_modifier
.evex
= EVEX128
;
3950 if (op
>= MAX_OPERANDS
)
3954 switch (i
.tm
.opcode_modifier
.evex
)
3956 case EVEXLIG
: /* LL' is ignored */
3957 vec_length
= evexlig
<< 5;
3960 vec_length
= 0 << 5;
3963 vec_length
= 1 << 5;
3966 vec_length
= 2 << 5;
3972 i
.vex
.bytes
[3] |= vec_length
;
3973 /* Encode the broadcast bit. */
3975 i
.vex
.bytes
[3] |= 0x10;
3979 if (i
.rounding
->type
!= saeonly
)
3980 i
.vex
.bytes
[3] |= 0x10 | (i
.rounding
->type
<< 5);
3982 i
.vex
.bytes
[3] |= 0x10 | (evexrcig
<< 5);
3985 if (i
.mask
&& i
.mask
->mask
)
3986 i
.vex
.bytes
[3] |= i
.mask
->mask
->reg_num
;
3990 process_immext (void)
3994 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
3995 which is coded in the same place as an 8-bit immediate field
3996 would be. Here we fake an 8-bit immediate operand from the
3997 opcode suffix stored in tm.extension_opcode.
3999 AVX instructions also use this encoding, for some of
4000 3 argument instructions. */
4002 gas_assert (i
.imm_operands
<= 1
4004 || (is_any_vex_encoding (&i
.tm
)
4005 && i
.operands
<= 4)));
4007 exp
= &im_expressions
[i
.imm_operands
++];
4008 i
.op
[i
.operands
].imms
= exp
;
4009 i
.types
[i
.operands
] = imm8
;
4011 exp
->X_op
= O_constant
;
4012 exp
->X_add_number
= i
.tm
.extension_opcode
;
4013 i
.tm
.extension_opcode
= None
;
4020 switch (i
.tm
.opcode_modifier
.hleprefixok
)
4025 as_bad (_("invalid instruction `%s' after `%s'"),
4026 i
.tm
.name
, i
.hle_prefix
);
4029 if (i
.prefix
[LOCK_PREFIX
])
4031 as_bad (_("missing `lock' with `%s'"), i
.hle_prefix
);
4035 case HLEPrefixRelease
:
4036 if (i
.prefix
[HLE_PREFIX
] != XRELEASE_PREFIX_OPCODE
)
4038 as_bad (_("instruction `%s' after `xacquire' not allowed"),
4042 if (i
.mem_operands
== 0 || !(i
.flags
[i
.operands
- 1] & Operand_Mem
))
4044 as_bad (_("memory destination needed for instruction `%s'"
4045 " after `xrelease'"), i
.tm
.name
);
4052 /* Try the shortest encoding by shortening operand size. */
4055 optimize_encoding (void)
4059 if (optimize_for_space
4060 && !is_any_vex_encoding (&i
.tm
)
4061 && i
.reg_operands
== 1
4062 && i
.imm_operands
== 1
4063 && !i
.types
[1].bitfield
.byte
4064 && i
.op
[0].imms
->X_op
== O_constant
4065 && fits_in_imm7 (i
.op
[0].imms
->X_add_number
)
4066 && (i
.tm
.base_opcode
== 0xa8
4067 || (i
.tm
.base_opcode
== 0xf6
4068 && i
.tm
.extension_opcode
== 0x0)))
4071 test $imm7, %r64/%r32/%r16 -> test $imm7, %r8
4073 unsigned int base_regnum
= i
.op
[1].regs
->reg_num
;
4074 if (flag_code
== CODE_64BIT
|| base_regnum
< 4)
4076 i
.types
[1].bitfield
.byte
= 1;
4077 /* Ignore the suffix. */
4079 /* Convert to byte registers. */
4080 if (i
.types
[1].bitfield
.word
)
4082 else if (i
.types
[1].bitfield
.dword
)
4086 if (!(i
.op
[1].regs
->reg_flags
& RegRex
) && base_regnum
< 4)
4091 else if (flag_code
== CODE_64BIT
4092 && !is_any_vex_encoding (&i
.tm
)
4093 && ((i
.types
[1].bitfield
.qword
4094 && i
.reg_operands
== 1
4095 && i
.imm_operands
== 1
4096 && i
.op
[0].imms
->X_op
== O_constant
4097 && ((i
.tm
.base_opcode
== 0xb8
4098 && i
.tm
.extension_opcode
== None
4099 && fits_in_unsigned_long (i
.op
[0].imms
->X_add_number
))
4100 || (fits_in_imm31 (i
.op
[0].imms
->X_add_number
)
4101 && ((i
.tm
.base_opcode
== 0x24
4102 || i
.tm
.base_opcode
== 0xa8)
4103 || (i
.tm
.base_opcode
== 0x80
4104 && i
.tm
.extension_opcode
== 0x4)
4105 || ((i
.tm
.base_opcode
== 0xf6
4106 || (i
.tm
.base_opcode
| 1) == 0xc7)
4107 && i
.tm
.extension_opcode
== 0x0)))
4108 || (fits_in_imm7 (i
.op
[0].imms
->X_add_number
)
4109 && i
.tm
.base_opcode
== 0x83
4110 && i
.tm
.extension_opcode
== 0x4)))
4111 || (i
.types
[0].bitfield
.qword
4112 && ((i
.reg_operands
== 2
4113 && i
.op
[0].regs
== i
.op
[1].regs
4114 && (i
.tm
.base_opcode
== 0x30
4115 || i
.tm
.base_opcode
== 0x28))
4116 || (i
.reg_operands
== 1
4118 && i
.tm
.base_opcode
== 0x30)))))
4121 andq $imm31, %r64 -> andl $imm31, %r32
4122 andq $imm7, %r64 -> andl $imm7, %r32
4123 testq $imm31, %r64 -> testl $imm31, %r32
4124 xorq %r64, %r64 -> xorl %r32, %r32
4125 subq %r64, %r64 -> subl %r32, %r32
4126 movq $imm31, %r64 -> movl $imm31, %r32
4127 movq $imm32, %r64 -> movl $imm32, %r32
4129 i
.tm
.opcode_modifier
.norex64
= 1;
4130 if (i
.tm
.base_opcode
== 0xb8 || (i
.tm
.base_opcode
| 1) == 0xc7)
4133 movq $imm31, %r64 -> movl $imm31, %r32
4134 movq $imm32, %r64 -> movl $imm32, %r32
4136 i
.tm
.operand_types
[0].bitfield
.imm32
= 1;
4137 i
.tm
.operand_types
[0].bitfield
.imm32s
= 0;
4138 i
.tm
.operand_types
[0].bitfield
.imm64
= 0;
4139 i
.types
[0].bitfield
.imm32
= 1;
4140 i
.types
[0].bitfield
.imm32s
= 0;
4141 i
.types
[0].bitfield
.imm64
= 0;
4142 i
.types
[1].bitfield
.dword
= 1;
4143 i
.types
[1].bitfield
.qword
= 0;
4144 if ((i
.tm
.base_opcode
| 1) == 0xc7)
4147 movq $imm31, %r64 -> movl $imm31, %r32
4149 i
.tm
.base_opcode
= 0xb8;
4150 i
.tm
.extension_opcode
= None
;
4151 i
.tm
.opcode_modifier
.w
= 0;
4152 i
.tm
.opcode_modifier
.modrm
= 0;
4156 else if (optimize
> 1
4157 && !optimize_for_space
4158 && !is_any_vex_encoding (&i
.tm
)
4159 && i
.reg_operands
== 2
4160 && i
.op
[0].regs
== i
.op
[1].regs
4161 && ((i
.tm
.base_opcode
& ~(Opcode_D
| 1)) == 0x8
4162 || (i
.tm
.base_opcode
& ~(Opcode_D
| 1)) == 0x20)
4163 && (flag_code
!= CODE_64BIT
|| !i
.types
[0].bitfield
.dword
))
4166 andb %rN, %rN -> testb %rN, %rN
4167 andw %rN, %rN -> testw %rN, %rN
4168 andq %rN, %rN -> testq %rN, %rN
4169 orb %rN, %rN -> testb %rN, %rN
4170 orw %rN, %rN -> testw %rN, %rN
4171 orq %rN, %rN -> testq %rN, %rN
4173 and outside of 64-bit mode
4175 andl %rN, %rN -> testl %rN, %rN
4176 orl %rN, %rN -> testl %rN, %rN
4178 i
.tm
.base_opcode
= 0x84 | (i
.tm
.base_opcode
& 1);
4180 else if (i
.reg_operands
== 3
4181 && i
.op
[0].regs
== i
.op
[1].regs
4182 && !i
.types
[2].bitfield
.xmmword
4183 && (i
.tm
.opcode_modifier
.vex
4184 || ((!i
.mask
|| i
.mask
->zeroing
)
4186 && is_evex_encoding (&i
.tm
)
4187 && (i
.vec_encoding
!= vex_encoding_evex
4188 || cpu_arch_isa_flags
.bitfield
.cpuavx512vl
4189 || i
.tm
.cpu_flags
.bitfield
.cpuavx512vl
4190 || (i
.tm
.operand_types
[2].bitfield
.zmmword
4191 && i
.types
[2].bitfield
.ymmword
))))
4192 && ((i
.tm
.base_opcode
== 0x55
4193 || i
.tm
.base_opcode
== 0x6655
4194 || i
.tm
.base_opcode
== 0x66df
4195 || i
.tm
.base_opcode
== 0x57
4196 || i
.tm
.base_opcode
== 0x6657
4197 || i
.tm
.base_opcode
== 0x66ef
4198 || i
.tm
.base_opcode
== 0x66f8
4199 || i
.tm
.base_opcode
== 0x66f9
4200 || i
.tm
.base_opcode
== 0x66fa
4201 || i
.tm
.base_opcode
== 0x66fb
4202 || i
.tm
.base_opcode
== 0x42
4203 || i
.tm
.base_opcode
== 0x6642
4204 || i
.tm
.base_opcode
== 0x47
4205 || i
.tm
.base_opcode
== 0x6647)
4206 && i
.tm
.extension_opcode
== None
))
4209 VOP, one of vandnps, vandnpd, vxorps, vxorpd, vpsubb, vpsubd,
4211 EVEX VOP %zmmM, %zmmM, %zmmN
4212 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
4213 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4214 EVEX VOP %ymmM, %ymmM, %ymmN
4215 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
4216 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4217 VEX VOP %ymmM, %ymmM, %ymmN
4218 -> VEX VOP %xmmM, %xmmM, %xmmN
4219 VOP, one of vpandn and vpxor:
4220 VEX VOP %ymmM, %ymmM, %ymmN
4221 -> VEX VOP %xmmM, %xmmM, %xmmN
4222 VOP, one of vpandnd and vpandnq:
4223 EVEX VOP %zmmM, %zmmM, %zmmN
4224 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
4225 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4226 EVEX VOP %ymmM, %ymmM, %ymmN
4227 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
4228 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4229 VOP, one of vpxord and vpxorq:
4230 EVEX VOP %zmmM, %zmmM, %zmmN
4231 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
4232 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4233 EVEX VOP %ymmM, %ymmM, %ymmN
4234 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
4235 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4236 VOP, one of kxord and kxorq:
4237 VEX VOP %kM, %kM, %kN
4238 -> VEX kxorw %kM, %kM, %kN
4239 VOP, one of kandnd and kandnq:
4240 VEX VOP %kM, %kM, %kN
4241 -> VEX kandnw %kM, %kM, %kN
4243 if (is_evex_encoding (&i
.tm
))
4245 if (i
.vec_encoding
!= vex_encoding_evex
)
4247 i
.tm
.opcode_modifier
.vex
= VEX128
;
4248 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4249 i
.tm
.opcode_modifier
.evex
= 0;
4251 else if (optimize
> 1)
4252 i
.tm
.opcode_modifier
.evex
= EVEX128
;
4256 else if (i
.tm
.operand_types
[0].bitfield
.class == RegMask
)
4258 i
.tm
.base_opcode
&= 0xff;
4259 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4262 i
.tm
.opcode_modifier
.vex
= VEX128
;
4264 if (i
.tm
.opcode_modifier
.vex
)
4265 for (j
= 0; j
< 3; j
++)
4267 i
.types
[j
].bitfield
.xmmword
= 1;
4268 i
.types
[j
].bitfield
.ymmword
= 0;
4271 else if (i
.vec_encoding
!= vex_encoding_evex
4272 && !i
.types
[0].bitfield
.zmmword
4273 && !i
.types
[1].bitfield
.zmmword
4276 && is_evex_encoding (&i
.tm
)
4277 && ((i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0x666f
4278 || (i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0xf36f
4279 || (i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0xf26f
4280 || (i
.tm
.base_opcode
& ~4) == 0x66db
4281 || (i
.tm
.base_opcode
& ~4) == 0x66eb)
4282 && i
.tm
.extension_opcode
== None
)
4285 VOP, one of vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16,
4286 vmovdqu32 and vmovdqu64:
4287 EVEX VOP %xmmM, %xmmN
4288 -> VEX vmovdqa|vmovdqu %xmmM, %xmmN (M and N < 16)
4289 EVEX VOP %ymmM, %ymmN
4290 -> VEX vmovdqa|vmovdqu %ymmM, %ymmN (M and N < 16)
4292 -> VEX vmovdqa|vmovdqu %xmmM, mem (M < 16)
4294 -> VEX vmovdqa|vmovdqu %ymmM, mem (M < 16)
4296 -> VEX mvmovdqa|vmovdquem, %xmmN (N < 16)
4298 -> VEX vmovdqa|vmovdqu mem, %ymmN (N < 16)
4299 VOP, one of vpand, vpandn, vpor, vpxor:
4300 EVEX VOP{d,q} %xmmL, %xmmM, %xmmN
4301 -> VEX VOP %xmmL, %xmmM, %xmmN (L, M, and N < 16)
4302 EVEX VOP{d,q} %ymmL, %ymmM, %ymmN
4303 -> VEX VOP %ymmL, %ymmM, %ymmN (L, M, and N < 16)
4304 EVEX VOP{d,q} mem, %xmmM, %xmmN
4305 -> VEX VOP mem, %xmmM, %xmmN (M and N < 16)
4306 EVEX VOP{d,q} mem, %ymmM, %ymmN
4307 -> VEX VOP mem, %ymmM, %ymmN (M and N < 16)
4309 for (j
= 0; j
< i
.operands
; j
++)
4310 if (operand_type_check (i
.types
[j
], disp
)
4311 && i
.op
[j
].disps
->X_op
== O_constant
)
4313 /* Since the VEX prefix has 2 or 3 bytes, the EVEX prefix
4314 has 4 bytes, EVEX Disp8 has 1 byte and VEX Disp32 has 4
4315 bytes, we choose EVEX Disp8 over VEX Disp32. */
4316 int evex_disp8
, vex_disp8
;
4317 unsigned int memshift
= i
.memshift
;
4318 offsetT n
= i
.op
[j
].disps
->X_add_number
;
4320 evex_disp8
= fits_in_disp8 (n
);
4322 vex_disp8
= fits_in_disp8 (n
);
4323 if (evex_disp8
!= vex_disp8
)
4325 i
.memshift
= memshift
;
4329 i
.types
[j
].bitfield
.disp8
= vex_disp8
;
4332 if ((i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0xf26f)
4333 i
.tm
.base_opcode
^= 0xf36f ^ 0xf26f;
4334 i
.tm
.opcode_modifier
.vex
4335 = i
.types
[0].bitfield
.ymmword
? VEX256
: VEX128
;
4336 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4337 /* VPAND, VPOR, and VPXOR are commutative. */
4338 if (i
.reg_operands
== 3 && i
.tm
.base_opcode
!= 0x66df)
4339 i
.tm
.opcode_modifier
.commutative
= 1;
4340 i
.tm
.opcode_modifier
.evex
= 0;
4341 i
.tm
.opcode_modifier
.masking
= 0;
4342 i
.tm
.opcode_modifier
.broadcast
= 0;
4343 i
.tm
.opcode_modifier
.disp8memshift
= 0;
4346 i
.types
[j
].bitfield
.disp8
4347 = fits_in_disp8 (i
.op
[j
].disps
->X_add_number
);
4351 /* Return non-zero for load instruction. */
4357 int any_vex_p
= is_any_vex_encoding (&i
.tm
);
4358 unsigned int base_opcode
= i
.tm
.base_opcode
| 1;
4362 /* Anysize insns: lea, invlpg, clflush, prefetchnta, prefetcht0,
4363 prefetcht1, prefetcht2, prefetchtw, bndmk, bndcl, bndcu, bndcn,
4364 bndstx, bndldx, prefetchwt1, clflushopt, clwb, cldemote. */
4365 if (i
.tm
.opcode_modifier
.anysize
)
4368 /* pop, popf, popa. */
4369 if (strcmp (i
.tm
.name
, "pop") == 0
4370 || i
.tm
.base_opcode
== 0x9d
4371 || i
.tm
.base_opcode
== 0x61)
4374 /* movs, cmps, lods, scas. */
4375 if ((i
.tm
.base_opcode
| 0xb) == 0xaf)
4379 if (base_opcode
== 0x6f
4380 || i
.tm
.base_opcode
== 0xd7)
4382 /* NB: For AMD-specific insns with implicit memory operands,
4383 they're intentionally not covered. */
4386 /* No memory operand. */
4387 if (!i
.mem_operands
)
4393 if (i
.tm
.base_opcode
== 0xae
4394 && i
.tm
.opcode_modifier
.vex
4395 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
4396 && i
.tm
.extension_opcode
== 2)
4401 /* test, not, neg, mul, imul, div, idiv. */
4402 if ((i
.tm
.base_opcode
== 0xf6 || i
.tm
.base_opcode
== 0xf7)
4403 && i
.tm
.extension_opcode
!= 1)
4407 if (base_opcode
== 0xff && i
.tm
.extension_opcode
<= 1)
4410 /* add, or, adc, sbb, and, sub, xor, cmp. */
4411 if (i
.tm
.base_opcode
>= 0x80 && i
.tm
.base_opcode
<= 0x83)
4414 /* bt, bts, btr, btc. */
4415 if (i
.tm
.base_opcode
== 0xfba
4416 && (i
.tm
.extension_opcode
>= 4 && i
.tm
.extension_opcode
<= 7))
4419 /* rol, ror, rcl, rcr, shl/sal, shr, sar. */
4420 if ((base_opcode
== 0xc1
4421 || (i
.tm
.base_opcode
>= 0xd0 && i
.tm
.base_opcode
<= 0xd3))
4422 && i
.tm
.extension_opcode
!= 6)
4425 /* cmpxchg8b, cmpxchg16b, xrstors. */
4426 if (i
.tm
.base_opcode
== 0xfc7
4427 && (i
.tm
.extension_opcode
== 1 || i
.tm
.extension_opcode
== 3))
4430 /* fxrstor, ldmxcsr, xrstor. */
4431 if (i
.tm
.base_opcode
== 0xfae
4432 && (i
.tm
.extension_opcode
== 1
4433 || i
.tm
.extension_opcode
== 2
4434 || i
.tm
.extension_opcode
== 5))
4437 /* lgdt, lidt, lmsw. */
4438 if (i
.tm
.base_opcode
== 0xf01
4439 && (i
.tm
.extension_opcode
== 2
4440 || i
.tm
.extension_opcode
== 3
4441 || i
.tm
.extension_opcode
== 6))
4445 if (i
.tm
.base_opcode
== 0xfc7
4446 && i
.tm
.extension_opcode
== 6)
4449 /* Check for x87 instructions. */
4450 if (i
.tm
.base_opcode
>= 0xd8 && i
.tm
.base_opcode
<= 0xdf)
4452 /* Skip fst, fstp, fstenv, fstcw. */
4453 if (i
.tm
.base_opcode
== 0xd9
4454 && (i
.tm
.extension_opcode
== 2
4455 || i
.tm
.extension_opcode
== 3
4456 || i
.tm
.extension_opcode
== 6
4457 || i
.tm
.extension_opcode
== 7))
4460 /* Skip fisttp, fist, fistp, fstp. */
4461 if (i
.tm
.base_opcode
== 0xdb
4462 && (i
.tm
.extension_opcode
== 1
4463 || i
.tm
.extension_opcode
== 2
4464 || i
.tm
.extension_opcode
== 3
4465 || i
.tm
.extension_opcode
== 7))
4468 /* Skip fisttp, fst, fstp, fsave, fstsw. */
4469 if (i
.tm
.base_opcode
== 0xdd
4470 && (i
.tm
.extension_opcode
== 1
4471 || i
.tm
.extension_opcode
== 2
4472 || i
.tm
.extension_opcode
== 3
4473 || i
.tm
.extension_opcode
== 6
4474 || i
.tm
.extension_opcode
== 7))
4477 /* Skip fisttp, fist, fistp, fbstp, fistp. */
4478 if (i
.tm
.base_opcode
== 0xdf
4479 && (i
.tm
.extension_opcode
== 1
4480 || i
.tm
.extension_opcode
== 2
4481 || i
.tm
.extension_opcode
== 3
4482 || i
.tm
.extension_opcode
== 6
4483 || i
.tm
.extension_opcode
== 7))
4490 dest
= i
.operands
- 1;
4492 /* Check fake imm8 operand and 3 source operands. */
4493 if ((i
.tm
.opcode_modifier
.immext
4494 || i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
)
4495 && i
.types
[dest
].bitfield
.imm8
)
4498 /* add, or, adc, sbb, and, sub, xor, cmp, test, xchg, xadd */
4500 && (base_opcode
== 0x1
4501 || base_opcode
== 0x9
4502 || base_opcode
== 0x11
4503 || base_opcode
== 0x19
4504 || base_opcode
== 0x21
4505 || base_opcode
== 0x29
4506 || base_opcode
== 0x31
4507 || base_opcode
== 0x39
4508 || (i
.tm
.base_opcode
>= 0x84 && i
.tm
.base_opcode
<= 0x87)
4509 || base_opcode
== 0xfc1))
4512 /* Check for load instruction. */
4513 return (i
.types
[dest
].bitfield
.class != ClassNone
4514 || i
.types
[dest
].bitfield
.instance
== Accum
);
4517 /* Output lfence, 0xfaee8, after instruction. */
4520 insert_lfence_after (void)
4522 if (lfence_after_load
&& load_insn_p ())
4524 /* There are also two REP string instructions that require
4525 special treatment. Specifically, the compare string (CMPS)
4526 and scan string (SCAS) instructions set EFLAGS in a manner
4527 that depends on the data being compared/scanned. When used
4528 with a REP prefix, the number of iterations may therefore
4529 vary depending on this data. If the data is a program secret
4530 chosen by the adversary using an LVI method,
4531 then this data-dependent behavior may leak some aspect
4533 if (((i
.tm
.base_opcode
| 0x1) == 0xa7
4534 || (i
.tm
.base_opcode
| 0x1) == 0xaf)
4535 && i
.prefix
[REP_PREFIX
])
4537 as_warn (_("`%s` changes flags which would affect control flow behavior"),
4540 char *p
= frag_more (3);
4547 /* Output lfence, 0xfaee8, before instruction. */
4550 insert_lfence_before (void)
4554 if (is_any_vex_encoding (&i
.tm
))
4557 if (i
.tm
.base_opcode
== 0xff
4558 && (i
.tm
.extension_opcode
== 2 || i
.tm
.extension_opcode
== 4))
4560 /* Insert lfence before indirect branch if needed. */
4562 if (lfence_before_indirect_branch
== lfence_branch_none
)
4565 if (i
.operands
!= 1)
4568 if (i
.reg_operands
== 1)
4570 /* Indirect branch via register. Don't insert lfence with
4571 -mlfence-after-load=yes. */
4572 if (lfence_after_load
4573 || lfence_before_indirect_branch
== lfence_branch_memory
)
4576 else if (i
.mem_operands
== 1
4577 && lfence_before_indirect_branch
!= lfence_branch_register
)
4579 as_warn (_("indirect `%s` with memory operand should be avoided"),
4586 if (last_insn
.kind
!= last_insn_other
4587 && last_insn
.seg
== now_seg
)
4589 as_warn_where (last_insn
.file
, last_insn
.line
,
4590 _("`%s` skips -mlfence-before-indirect-branch on `%s`"),
4591 last_insn
.name
, i
.tm
.name
);
4602 /* Output or/not/shl and lfence before near ret. */
4603 if (lfence_before_ret
!= lfence_before_ret_none
4604 && (i
.tm
.base_opcode
== 0xc2
4605 || i
.tm
.base_opcode
== 0xc3))
4607 if (last_insn
.kind
!= last_insn_other
4608 && last_insn
.seg
== now_seg
)
4610 as_warn_where (last_insn
.file
, last_insn
.line
,
4611 _("`%s` skips -mlfence-before-ret on `%s`"),
4612 last_insn
.name
, i
.tm
.name
);
4616 /* Near ret ingore operand size override under CPU64. */
4617 char prefix
= flag_code
== CODE_64BIT
4619 : i
.prefix
[DATA_PREFIX
] ? 0x66 : 0x0;
4621 if (lfence_before_ret
== lfence_before_ret_not
)
4623 /* not: 0xf71424, may add prefix
4624 for operand size override or 64-bit code. */
4625 p
= frag_more ((prefix
? 2 : 0) + 6 + 3);
4639 p
= frag_more ((prefix
? 1 : 0) + 4 + 3);
4642 if (lfence_before_ret
== lfence_before_ret_or
)
4644 /* or: 0x830c2400, may add prefix
4645 for operand size override or 64-bit code. */
4651 /* shl: 0xc1242400, may add prefix
4652 for operand size override or 64-bit code. */
4667 /* This is the guts of the machine-dependent assembler. LINE points to a
4668 machine dependent instruction. This function is supposed to emit
4669 the frags/bytes it assembles to. */
4672 md_assemble (char *line
)
4675 char mnemonic
[MAX_MNEM_SIZE
], mnem_suffix
;
4676 const insn_template
*t
;
4678 /* Initialize globals. */
4679 memset (&i
, '\0', sizeof (i
));
4680 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4681 i
.reloc
[j
] = NO_RELOC
;
4682 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
4683 memset (im_expressions
, '\0', sizeof (im_expressions
));
4684 save_stack_p
= save_stack
;
4686 /* First parse an instruction mnemonic & call i386_operand for the operands.
4687 We assume that the scrubber has arranged it so that line[0] is the valid
4688 start of a (possibly prefixed) mnemonic. */
4690 line
= parse_insn (line
, mnemonic
);
4693 mnem_suffix
= i
.suffix
;
4695 line
= parse_operands (line
, mnemonic
);
4697 xfree (i
.memop1_string
);
4698 i
.memop1_string
= NULL
;
4702 /* Now we've parsed the mnemonic into a set of templates, and have the
4703 operands at hand. */
4705 /* All Intel opcodes have reversed operands except for "bound", "enter",
4706 "monitor*", "mwait*", "tpause", and "umwait". We also don't reverse
4707 intersegment "jmp" and "call" instructions with 2 immediate operands so
4708 that the immediate segment precedes the offset, as it does when in AT&T
4712 && (strcmp (mnemonic
, "bound") != 0)
4713 && (strcmp (mnemonic
, "invlpga") != 0)
4714 && (strncmp (mnemonic
, "monitor", 7) != 0)
4715 && (strncmp (mnemonic
, "mwait", 5) != 0)
4716 && (strcmp (mnemonic
, "tpause") != 0)
4717 && (strcmp (mnemonic
, "umwait") != 0)
4718 && !(operand_type_check (i
.types
[0], imm
)
4719 && operand_type_check (i
.types
[1], imm
)))
4722 /* The order of the immediates should be reversed
4723 for 2 immediates extrq and insertq instructions */
4724 if (i
.imm_operands
== 2
4725 && (strcmp (mnemonic
, "extrq") == 0
4726 || strcmp (mnemonic
, "insertq") == 0))
4727 swap_2_operands (0, 1);
4732 /* Don't optimize displacement for movabs since it only takes 64bit
4735 && i
.disp_encoding
!= disp_encoding_32bit
4736 && (flag_code
!= CODE_64BIT
4737 || strcmp (mnemonic
, "movabs") != 0))
4740 /* Next, we find a template that matches the given insn,
4741 making sure the overlap of the given operands types is consistent
4742 with the template operand types. */
4744 if (!(t
= match_template (mnem_suffix
)))
4747 if (sse_check
!= check_none
4748 && !i
.tm
.opcode_modifier
.noavx
4749 && !i
.tm
.cpu_flags
.bitfield
.cpuavx
4750 && !i
.tm
.cpu_flags
.bitfield
.cpuavx512f
4751 && (i
.tm
.cpu_flags
.bitfield
.cpusse
4752 || i
.tm
.cpu_flags
.bitfield
.cpusse2
4753 || i
.tm
.cpu_flags
.bitfield
.cpusse3
4754 || i
.tm
.cpu_flags
.bitfield
.cpussse3
4755 || i
.tm
.cpu_flags
.bitfield
.cpusse4_1
4756 || i
.tm
.cpu_flags
.bitfield
.cpusse4_2
4757 || i
.tm
.cpu_flags
.bitfield
.cpupclmul
4758 || i
.tm
.cpu_flags
.bitfield
.cpuaes
4759 || i
.tm
.cpu_flags
.bitfield
.cpusha
4760 || i
.tm
.cpu_flags
.bitfield
.cpugfni
))
4762 (sse_check
== check_warning
4764 : as_bad
) (_("SSE instruction `%s' is used"), i
.tm
.name
);
4767 if (i
.tm
.opcode_modifier
.fwait
)
4768 if (!add_prefix (FWAIT_OPCODE
))
4771 /* Check if REP prefix is OK. */
4772 if (i
.rep_prefix
&& !i
.tm
.opcode_modifier
.repprefixok
)
4774 as_bad (_("invalid instruction `%s' after `%s'"),
4775 i
.tm
.name
, i
.rep_prefix
);
4779 /* Check for lock without a lockable instruction. Destination operand
4780 must be memory unless it is xchg (0x86). */
4781 if (i
.prefix
[LOCK_PREFIX
]
4782 && (!i
.tm
.opcode_modifier
.islockable
4783 || i
.mem_operands
== 0
4784 || (i
.tm
.base_opcode
!= 0x86
4785 && !(i
.flags
[i
.operands
- 1] & Operand_Mem
))))
4787 as_bad (_("expecting lockable instruction after `lock'"));
4791 /* Check for data size prefix on VEX/XOP/EVEX encoded and SIMD insns. */
4792 if (i
.prefix
[DATA_PREFIX
]
4793 && (is_any_vex_encoding (&i
.tm
)
4794 || i
.tm
.operand_types
[i
.imm_operands
].bitfield
.class >= RegMMX
4795 || i
.tm
.operand_types
[i
.imm_operands
+ 1].bitfield
.class >= RegMMX
))
4797 as_bad (_("data size prefix invalid with `%s'"), i
.tm
.name
);
4801 /* Check if HLE prefix is OK. */
4802 if (i
.hle_prefix
&& !check_hle ())
4805 /* Check BND prefix. */
4806 if (i
.bnd_prefix
&& !i
.tm
.opcode_modifier
.bndprefixok
)
4807 as_bad (_("expecting valid branch instruction after `bnd'"));
4809 /* Check NOTRACK prefix. */
4810 if (i
.notrack_prefix
&& !i
.tm
.opcode_modifier
.notrackprefixok
)
4811 as_bad (_("expecting indirect branch instruction after `notrack'"));
4813 if (i
.tm
.cpu_flags
.bitfield
.cpumpx
)
4815 if (flag_code
== CODE_64BIT
&& i
.prefix
[ADDR_PREFIX
])
4816 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
4817 else if (flag_code
!= CODE_16BIT
4818 ? i
.prefix
[ADDR_PREFIX
]
4819 : i
.mem_operands
&& !i
.prefix
[ADDR_PREFIX
])
4820 as_bad (_("16-bit address isn't allowed in MPX instructions"));
4823 /* Insert BND prefix. */
4824 if (add_bnd_prefix
&& i
.tm
.opcode_modifier
.bndprefixok
)
4826 if (!i
.prefix
[BND_PREFIX
])
4827 add_prefix (BND_PREFIX_OPCODE
);
4828 else if (i
.prefix
[BND_PREFIX
] != BND_PREFIX_OPCODE
)
4830 as_warn (_("replacing `rep'/`repe' prefix by `bnd'"));
4831 i
.prefix
[BND_PREFIX
] = BND_PREFIX_OPCODE
;
4835 /* Check string instruction segment overrides. */
4836 if (i
.tm
.opcode_modifier
.isstring
>= IS_STRING_ES_OP0
)
4838 gas_assert (i
.mem_operands
);
4839 if (!check_string ())
4841 i
.disp_operands
= 0;
4844 if (optimize
&& !i
.no_optimize
&& i
.tm
.opcode_modifier
.optimize
)
4845 optimize_encoding ();
4847 if (!process_suffix ())
4850 /* Update operand types. */
4851 for (j
= 0; j
< i
.operands
; j
++)
4852 i
.types
[j
] = operand_type_and (i
.types
[j
], i
.tm
.operand_types
[j
]);
4854 /* Make still unresolved immediate matches conform to size of immediate
4855 given in i.suffix. */
4856 if (!finalize_imm ())
4859 if (i
.types
[0].bitfield
.imm1
)
4860 i
.imm_operands
= 0; /* kludge for shift insns. */
4862 /* We only need to check those implicit registers for instructions
4863 with 3 operands or less. */
4864 if (i
.operands
<= 3)
4865 for (j
= 0; j
< i
.operands
; j
++)
4866 if (i
.types
[j
].bitfield
.instance
!= InstanceNone
4867 && !i
.types
[j
].bitfield
.xmmword
)
4870 /* ImmExt should be processed after SSE2AVX. */
4871 if (!i
.tm
.opcode_modifier
.sse2avx
4872 && i
.tm
.opcode_modifier
.immext
)
4875 /* For insns with operands there are more diddles to do to the opcode. */
4878 if (!process_operands ())
4881 else if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
4883 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
4884 as_warn (_("translating to `%sp'"), i
.tm
.name
);
4887 if (is_any_vex_encoding (&i
.tm
))
4889 if (!cpu_arch_flags
.bitfield
.cpui286
)
4891 as_bad (_("instruction `%s' isn't supported outside of protected mode."),
4896 /* Check for explicit REX prefix. */
4897 if (i
.prefix
[REX_PREFIX
] || i
.rex_encoding
)
4899 as_bad (_("REX prefix invalid with `%s'"), i
.tm
.name
);
4903 if (i
.tm
.opcode_modifier
.vex
)
4904 build_vex_prefix (t
);
4906 build_evex_prefix ();
4908 /* The individual REX.RXBW bits got consumed. */
4909 i
.rex
&= REX_OPCODE
;
4912 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
4913 instructions may define INT_OPCODE as well, so avoid this corner
4914 case for those instructions that use MODRM. */
4915 if (i
.tm
.base_opcode
== INT_OPCODE
4916 && !i
.tm
.opcode_modifier
.modrm
4917 && i
.op
[0].imms
->X_add_number
== 3)
4919 i
.tm
.base_opcode
= INT3_OPCODE
;
4923 if ((i
.tm
.opcode_modifier
.jump
== JUMP
4924 || i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
4925 || i
.tm
.opcode_modifier
.jump
== JUMP_DWORD
)
4926 && i
.op
[0].disps
->X_op
== O_constant
)
4928 /* Convert "jmp constant" (and "call constant") to a jump (call) to
4929 the absolute address given by the constant. Since ix86 jumps and
4930 calls are pc relative, we need to generate a reloc. */
4931 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
4932 i
.op
[0].disps
->X_op
= O_symbol
;
4935 /* For 8 bit registers we need an empty rex prefix. Also if the
4936 instruction already has a prefix, we need to convert old
4937 registers to new ones. */
4939 if ((i
.types
[0].bitfield
.class == Reg
&& i
.types
[0].bitfield
.byte
4940 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
4941 || (i
.types
[1].bitfield
.class == Reg
&& i
.types
[1].bitfield
.byte
4942 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
4943 || (((i
.types
[0].bitfield
.class == Reg
&& i
.types
[0].bitfield
.byte
)
4944 || (i
.types
[1].bitfield
.class == Reg
&& i
.types
[1].bitfield
.byte
))
4949 i
.rex
|= REX_OPCODE
;
4950 for (x
= 0; x
< 2; x
++)
4952 /* Look for 8 bit operand that uses old registers. */
4953 if (i
.types
[x
].bitfield
.class == Reg
&& i
.types
[x
].bitfield
.byte
4954 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
4956 gas_assert (!(i
.op
[x
].regs
->reg_flags
& RegRex
));
4957 /* In case it is "hi" register, give up. */
4958 if (i
.op
[x
].regs
->reg_num
> 3)
4959 as_bad (_("can't encode register '%s%s' in an "
4960 "instruction requiring REX prefix."),
4961 register_prefix
, i
.op
[x
].regs
->reg_name
);
4963 /* Otherwise it is equivalent to the extended register.
4964 Since the encoding doesn't change this is merely
4965 cosmetic cleanup for debug output. */
4967 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
4972 if (i
.rex
== 0 && i
.rex_encoding
)
4974 /* Check if we can add a REX_OPCODE byte. Look for 8 bit operand
4975 that uses legacy register. If it is "hi" register, don't add
4976 the REX_OPCODE byte. */
4978 for (x
= 0; x
< 2; x
++)
4979 if (i
.types
[x
].bitfield
.class == Reg
4980 && i
.types
[x
].bitfield
.byte
4981 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0
4982 && i
.op
[x
].regs
->reg_num
> 3)
4984 gas_assert (!(i
.op
[x
].regs
->reg_flags
& RegRex
));
4985 i
.rex_encoding
= FALSE
;
4994 add_prefix (REX_OPCODE
| i
.rex
);
4996 insert_lfence_before ();
4998 /* We are ready to output the insn. */
5001 insert_lfence_after ();
5003 last_insn
.seg
= now_seg
;
5005 if (i
.tm
.opcode_modifier
.isprefix
)
5007 last_insn
.kind
= last_insn_prefix
;
5008 last_insn
.name
= i
.tm
.name
;
5009 last_insn
.file
= as_where (&last_insn
.line
);
5012 last_insn
.kind
= last_insn_other
;
5016 parse_insn (char *line
, char *mnemonic
)
5019 char *token_start
= l
;
5022 const insn_template
*t
;
5028 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
5033 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
5035 as_bad (_("no such instruction: `%s'"), token_start
);
5040 if (!is_space_char (*l
)
5041 && *l
!= END_OF_INSN
5043 || (*l
!= PREFIX_SEPARATOR
5046 as_bad (_("invalid character %s in mnemonic"),
5047 output_invalid (*l
));
5050 if (token_start
== l
)
5052 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
5053 as_bad (_("expecting prefix; got nothing"));
5055 as_bad (_("expecting mnemonic; got nothing"));
5059 /* Look up instruction (or prefix) via hash table. */
5060 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
5062 if (*l
!= END_OF_INSN
5063 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
5064 && current_templates
5065 && current_templates
->start
->opcode_modifier
.isprefix
)
5067 if (!cpu_flags_check_cpu64 (current_templates
->start
->cpu_flags
))
5069 as_bad ((flag_code
!= CODE_64BIT
5070 ? _("`%s' is only supported in 64-bit mode")
5071 : _("`%s' is not supported in 64-bit mode")),
5072 current_templates
->start
->name
);
5075 /* If we are in 16-bit mode, do not allow addr16 or data16.
5076 Similarly, in 32-bit mode, do not allow addr32 or data32. */
5077 if ((current_templates
->start
->opcode_modifier
.size
== SIZE16
5078 || current_templates
->start
->opcode_modifier
.size
== SIZE32
)
5079 && flag_code
!= CODE_64BIT
5080 && ((current_templates
->start
->opcode_modifier
.size
== SIZE32
)
5081 ^ (flag_code
== CODE_16BIT
)))
5083 as_bad (_("redundant %s prefix"),
5084 current_templates
->start
->name
);
5087 if (current_templates
->start
->opcode_length
== 0)
5089 /* Handle pseudo prefixes. */
5090 switch (current_templates
->start
->base_opcode
)
5094 i
.disp_encoding
= disp_encoding_8bit
;
5098 i
.disp_encoding
= disp_encoding_32bit
;
5102 i
.dir_encoding
= dir_encoding_load
;
5106 i
.dir_encoding
= dir_encoding_store
;
5110 i
.vec_encoding
= vex_encoding_vex
;
5114 i
.vec_encoding
= vex_encoding_vex3
;
5118 i
.vec_encoding
= vex_encoding_evex
;
5122 i
.rex_encoding
= TRUE
;
5126 i
.no_optimize
= TRUE
;
5134 /* Add prefix, checking for repeated prefixes. */
5135 switch (add_prefix (current_templates
->start
->base_opcode
))
5140 if (current_templates
->start
->cpu_flags
.bitfield
.cpuibt
)
5141 i
.notrack_prefix
= current_templates
->start
->name
;
5144 if (current_templates
->start
->cpu_flags
.bitfield
.cpuhle
)
5145 i
.hle_prefix
= current_templates
->start
->name
;
5146 else if (current_templates
->start
->cpu_flags
.bitfield
.cpumpx
)
5147 i
.bnd_prefix
= current_templates
->start
->name
;
5149 i
.rep_prefix
= current_templates
->start
->name
;
5155 /* Skip past PREFIX_SEPARATOR and reset token_start. */
5162 if (!current_templates
)
5164 /* Deprecated functionality (new code should use pseudo-prefixes instead):
5165 Check if we should swap operand or force 32bit displacement in
5167 if (mnem_p
- 2 == dot_p
&& dot_p
[1] == 's')
5168 i
.dir_encoding
= dir_encoding_swap
;
5169 else if (mnem_p
- 3 == dot_p
5172 i
.disp_encoding
= disp_encoding_8bit
;
5173 else if (mnem_p
- 4 == dot_p
5177 i
.disp_encoding
= disp_encoding_32bit
;
5182 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
5185 if (!current_templates
)
5188 if (mnem_p
> mnemonic
)
5190 /* See if we can get a match by trimming off a suffix. */
5193 case WORD_MNEM_SUFFIX
:
5194 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
5195 i
.suffix
= SHORT_MNEM_SUFFIX
;
5198 case BYTE_MNEM_SUFFIX
:
5199 case QWORD_MNEM_SUFFIX
:
5200 i
.suffix
= mnem_p
[-1];
5202 current_templates
= (const templates
*) hash_find (op_hash
,
5205 case SHORT_MNEM_SUFFIX
:
5206 case LONG_MNEM_SUFFIX
:
5209 i
.suffix
= mnem_p
[-1];
5211 current_templates
= (const templates
*) hash_find (op_hash
,
5220 if (intel_float_operand (mnemonic
) == 1)
5221 i
.suffix
= SHORT_MNEM_SUFFIX
;
5223 i
.suffix
= LONG_MNEM_SUFFIX
;
5225 current_templates
= (const templates
*) hash_find (op_hash
,
5232 if (!current_templates
)
5234 as_bad (_("no such instruction: `%s'"), token_start
);
5239 if (current_templates
->start
->opcode_modifier
.jump
== JUMP
5240 || current_templates
->start
->opcode_modifier
.jump
== JUMP_BYTE
)
5242 /* Check for a branch hint. We allow ",pt" and ",pn" for
5243 predict taken and predict not taken respectively.
5244 I'm not sure that branch hints actually do anything on loop
5245 and jcxz insns (JumpByte) for current Pentium4 chips. They
5246 may work in the future and it doesn't hurt to accept them
5248 if (l
[0] == ',' && l
[1] == 'p')
5252 if (!add_prefix (DS_PREFIX_OPCODE
))
5256 else if (l
[2] == 'n')
5258 if (!add_prefix (CS_PREFIX_OPCODE
))
5264 /* Any other comma loses. */
5267 as_bad (_("invalid character %s in mnemonic"),
5268 output_invalid (*l
));
5272 /* Check if instruction is supported on specified architecture. */
5274 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
5276 supported
|= cpu_flags_match (t
);
5277 if (supported
== CPU_FLAGS_PERFECT_MATCH
)
5279 if (!cpu_arch_flags
.bitfield
.cpui386
&& (flag_code
!= CODE_16BIT
))
5280 as_warn (_("use .code16 to ensure correct addressing mode"));
5286 if (!(supported
& CPU_FLAGS_64BIT_MATCH
))
5287 as_bad (flag_code
== CODE_64BIT
5288 ? _("`%s' is not supported in 64-bit mode")
5289 : _("`%s' is only supported in 64-bit mode"),
5290 current_templates
->start
->name
);
5292 as_bad (_("`%s' is not supported on `%s%s'"),
5293 current_templates
->start
->name
,
5294 cpu_arch_name
? cpu_arch_name
: default_arch
,
5295 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
5301 parse_operands (char *l
, const char *mnemonic
)
5305 /* 1 if operand is pending after ','. */
5306 unsigned int expecting_operand
= 0;
5308 /* Non-zero if operand parens not balanced. */
5309 unsigned int paren_not_balanced
;
5311 while (*l
!= END_OF_INSN
)
5313 /* Skip optional white space before operand. */
5314 if (is_space_char (*l
))
5316 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
&& *l
!= '"')
5318 as_bad (_("invalid character %s before operand %d"),
5319 output_invalid (*l
),
5323 token_start
= l
; /* After white space. */
5324 paren_not_balanced
= 0;
5325 while (paren_not_balanced
|| *l
!= ',')
5327 if (*l
== END_OF_INSN
)
5329 if (paren_not_balanced
)
5332 as_bad (_("unbalanced parenthesis in operand %d."),
5335 as_bad (_("unbalanced brackets in operand %d."),
5340 break; /* we are done */
5342 else if (!is_operand_char (*l
) && !is_space_char (*l
) && *l
!= '"')
5344 as_bad (_("invalid character %s in operand %d"),
5345 output_invalid (*l
),
5352 ++paren_not_balanced
;
5354 --paren_not_balanced
;
5359 ++paren_not_balanced
;
5361 --paren_not_balanced
;
5365 if (l
!= token_start
)
5366 { /* Yes, we've read in another operand. */
5367 unsigned int operand_ok
;
5368 this_operand
= i
.operands
++;
5369 if (i
.operands
> MAX_OPERANDS
)
5371 as_bad (_("spurious operands; (%d operands/instruction max)"),
5375 i
.types
[this_operand
].bitfield
.unspecified
= 1;
5376 /* Now parse operand adding info to 'i' as we go along. */
5377 END_STRING_AND_SAVE (l
);
5379 if (i
.mem_operands
> 1)
5381 as_bad (_("too many memory references for `%s'"),
5388 i386_intel_operand (token_start
,
5389 intel_float_operand (mnemonic
));
5391 operand_ok
= i386_att_operand (token_start
);
5393 RESTORE_END_STRING (l
);
5399 if (expecting_operand
)
5401 expecting_operand_after_comma
:
5402 as_bad (_("expecting operand after ','; got nothing"));
5407 as_bad (_("expecting operand before ','; got nothing"));
5412 /* Now *l must be either ',' or END_OF_INSN. */
5415 if (*++l
== END_OF_INSN
)
5417 /* Just skip it, if it's \n complain. */
5418 goto expecting_operand_after_comma
;
5420 expecting_operand
= 1;
5427 swap_2_operands (int xchg1
, int xchg2
)
5429 union i386_op temp_op
;
5430 i386_operand_type temp_type
;
5431 unsigned int temp_flags
;
5432 enum bfd_reloc_code_real temp_reloc
;
5434 temp_type
= i
.types
[xchg2
];
5435 i
.types
[xchg2
] = i
.types
[xchg1
];
5436 i
.types
[xchg1
] = temp_type
;
5438 temp_flags
= i
.flags
[xchg2
];
5439 i
.flags
[xchg2
] = i
.flags
[xchg1
];
5440 i
.flags
[xchg1
] = temp_flags
;
5442 temp_op
= i
.op
[xchg2
];
5443 i
.op
[xchg2
] = i
.op
[xchg1
];
5444 i
.op
[xchg1
] = temp_op
;
5446 temp_reloc
= i
.reloc
[xchg2
];
5447 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
5448 i
.reloc
[xchg1
] = temp_reloc
;
5452 if (i
.mask
->operand
== xchg1
)
5453 i
.mask
->operand
= xchg2
;
5454 else if (i
.mask
->operand
== xchg2
)
5455 i
.mask
->operand
= xchg1
;
5459 if (i
.broadcast
->operand
== xchg1
)
5460 i
.broadcast
->operand
= xchg2
;
5461 else if (i
.broadcast
->operand
== xchg2
)
5462 i
.broadcast
->operand
= xchg1
;
5466 if (i
.rounding
->operand
== xchg1
)
5467 i
.rounding
->operand
= xchg2
;
5468 else if (i
.rounding
->operand
== xchg2
)
5469 i
.rounding
->operand
= xchg1
;
5474 swap_operands (void)
5480 swap_2_operands (1, i
.operands
- 2);
5484 swap_2_operands (0, i
.operands
- 1);
5490 if (i
.mem_operands
== 2)
5492 const seg_entry
*temp_seg
;
5493 temp_seg
= i
.seg
[0];
5494 i
.seg
[0] = i
.seg
[1];
5495 i
.seg
[1] = temp_seg
;
5499 /* Try to ensure constant immediates are represented in the smallest
5504 char guess_suffix
= 0;
5508 guess_suffix
= i
.suffix
;
5509 else if (i
.reg_operands
)
5511 /* Figure out a suffix from the last register operand specified.
5512 We can't do this properly yet, i.e. excluding special register
5513 instances, but the following works for instructions with
5514 immediates. In any case, we can't set i.suffix yet. */
5515 for (op
= i
.operands
; --op
>= 0;)
5516 if (i
.types
[op
].bitfield
.class != Reg
)
5518 else if (i
.types
[op
].bitfield
.byte
)
5520 guess_suffix
= BYTE_MNEM_SUFFIX
;
5523 else if (i
.types
[op
].bitfield
.word
)
5525 guess_suffix
= WORD_MNEM_SUFFIX
;
5528 else if (i
.types
[op
].bitfield
.dword
)
5530 guess_suffix
= LONG_MNEM_SUFFIX
;
5533 else if (i
.types
[op
].bitfield
.qword
)
5535 guess_suffix
= QWORD_MNEM_SUFFIX
;
5539 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
5540 guess_suffix
= WORD_MNEM_SUFFIX
;
5542 for (op
= i
.operands
; --op
>= 0;)
5543 if (operand_type_check (i
.types
[op
], imm
))
5545 switch (i
.op
[op
].imms
->X_op
)
5548 /* If a suffix is given, this operand may be shortened. */
5549 switch (guess_suffix
)
5551 case LONG_MNEM_SUFFIX
:
5552 i
.types
[op
].bitfield
.imm32
= 1;
5553 i
.types
[op
].bitfield
.imm64
= 1;
5555 case WORD_MNEM_SUFFIX
:
5556 i
.types
[op
].bitfield
.imm16
= 1;
5557 i
.types
[op
].bitfield
.imm32
= 1;
5558 i
.types
[op
].bitfield
.imm32s
= 1;
5559 i
.types
[op
].bitfield
.imm64
= 1;
5561 case BYTE_MNEM_SUFFIX
:
5562 i
.types
[op
].bitfield
.imm8
= 1;
5563 i
.types
[op
].bitfield
.imm8s
= 1;
5564 i
.types
[op
].bitfield
.imm16
= 1;
5565 i
.types
[op
].bitfield
.imm32
= 1;
5566 i
.types
[op
].bitfield
.imm32s
= 1;
5567 i
.types
[op
].bitfield
.imm64
= 1;
5571 /* If this operand is at most 16 bits, convert it
5572 to a signed 16 bit number before trying to see
5573 whether it will fit in an even smaller size.
5574 This allows a 16-bit operand such as $0xffe0 to
5575 be recognised as within Imm8S range. */
5576 if ((i
.types
[op
].bitfield
.imm16
)
5577 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
5579 i
.op
[op
].imms
->X_add_number
=
5580 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
5583 /* Store 32-bit immediate in 64-bit for 64-bit BFD. */
5584 if ((i
.types
[op
].bitfield
.imm32
)
5585 && ((i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1))
5588 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
5589 ^ ((offsetT
) 1 << 31))
5590 - ((offsetT
) 1 << 31));
5594 = operand_type_or (i
.types
[op
],
5595 smallest_imm_type (i
.op
[op
].imms
->X_add_number
));
5597 /* We must avoid matching of Imm32 templates when 64bit
5598 only immediate is available. */
5599 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
5600 i
.types
[op
].bitfield
.imm32
= 0;
5607 /* Symbols and expressions. */
5609 /* Convert symbolic operand to proper sizes for matching, but don't
5610 prevent matching a set of insns that only supports sizes other
5611 than those matching the insn suffix. */
5613 i386_operand_type mask
, allowed
;
5614 const insn_template
*t
;
5616 operand_type_set (&mask
, 0);
5617 operand_type_set (&allowed
, 0);
5619 for (t
= current_templates
->start
;
5620 t
< current_templates
->end
;
5623 allowed
= operand_type_or (allowed
, t
->operand_types
[op
]);
5624 allowed
= operand_type_and (allowed
, anyimm
);
5626 switch (guess_suffix
)
5628 case QWORD_MNEM_SUFFIX
:
5629 mask
.bitfield
.imm64
= 1;
5630 mask
.bitfield
.imm32s
= 1;
5632 case LONG_MNEM_SUFFIX
:
5633 mask
.bitfield
.imm32
= 1;
5635 case WORD_MNEM_SUFFIX
:
5636 mask
.bitfield
.imm16
= 1;
5638 case BYTE_MNEM_SUFFIX
:
5639 mask
.bitfield
.imm8
= 1;
5644 allowed
= operand_type_and (mask
, allowed
);
5645 if (!operand_type_all_zero (&allowed
))
5646 i
.types
[op
] = operand_type_and (i
.types
[op
], mask
);
5653 /* Try to use the smallest displacement type too. */
5655 optimize_disp (void)
5659 for (op
= i
.operands
; --op
>= 0;)
5660 if (operand_type_check (i
.types
[op
], disp
))
5662 if (i
.op
[op
].disps
->X_op
== O_constant
)
5664 offsetT op_disp
= i
.op
[op
].disps
->X_add_number
;
5666 if (i
.types
[op
].bitfield
.disp16
5667 && (op_disp
& ~(offsetT
) 0xffff) == 0)
5669 /* If this operand is at most 16 bits, convert
5670 to a signed 16 bit number and don't use 64bit
5672 op_disp
= (((op_disp
& 0xffff) ^ 0x8000) - 0x8000);
5673 i
.types
[op
].bitfield
.disp64
= 0;
5676 /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */
5677 if (i
.types
[op
].bitfield
.disp32
5678 && (op_disp
& ~(((offsetT
) 2 << 31) - 1)) == 0)
5680 /* If this operand is at most 32 bits, convert
5681 to a signed 32 bit number and don't use 64bit
5683 op_disp
&= (((offsetT
) 2 << 31) - 1);
5684 op_disp
= (op_disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
5685 i
.types
[op
].bitfield
.disp64
= 0;
5688 if (!op_disp
&& i
.types
[op
].bitfield
.baseindex
)
5690 i
.types
[op
].bitfield
.disp8
= 0;
5691 i
.types
[op
].bitfield
.disp16
= 0;
5692 i
.types
[op
].bitfield
.disp32
= 0;
5693 i
.types
[op
].bitfield
.disp32s
= 0;
5694 i
.types
[op
].bitfield
.disp64
= 0;
5698 else if (flag_code
== CODE_64BIT
)
5700 if (fits_in_signed_long (op_disp
))
5702 i
.types
[op
].bitfield
.disp64
= 0;
5703 i
.types
[op
].bitfield
.disp32s
= 1;
5705 if (i
.prefix
[ADDR_PREFIX
]
5706 && fits_in_unsigned_long (op_disp
))
5707 i
.types
[op
].bitfield
.disp32
= 1;
5709 if ((i
.types
[op
].bitfield
.disp32
5710 || i
.types
[op
].bitfield
.disp32s
5711 || i
.types
[op
].bitfield
.disp16
)
5712 && fits_in_disp8 (op_disp
))
5713 i
.types
[op
].bitfield
.disp8
= 1;
5715 else if (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
5716 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
)
5718 fix_new_exp (frag_now
, frag_more (0) - frag_now
->fr_literal
, 0,
5719 i
.op
[op
].disps
, 0, i
.reloc
[op
]);
5720 i
.types
[op
].bitfield
.disp8
= 0;
5721 i
.types
[op
].bitfield
.disp16
= 0;
5722 i
.types
[op
].bitfield
.disp32
= 0;
5723 i
.types
[op
].bitfield
.disp32s
= 0;
5724 i
.types
[op
].bitfield
.disp64
= 0;
5727 /* We only support 64bit displacement on constants. */
5728 i
.types
[op
].bitfield
.disp64
= 0;
5732 /* Return 1 if there is a match in broadcast bytes between operand
5733 GIVEN and instruction template T. */
5736 match_broadcast_size (const insn_template
*t
, unsigned int given
)
5738 return ((t
->opcode_modifier
.broadcast
== BYTE_BROADCAST
5739 && i
.types
[given
].bitfield
.byte
)
5740 || (t
->opcode_modifier
.broadcast
== WORD_BROADCAST
5741 && i
.types
[given
].bitfield
.word
)
5742 || (t
->opcode_modifier
.broadcast
== DWORD_BROADCAST
5743 && i
.types
[given
].bitfield
.dword
)
5744 || (t
->opcode_modifier
.broadcast
== QWORD_BROADCAST
5745 && i
.types
[given
].bitfield
.qword
));
5748 /* Check if operands are valid for the instruction. */
5751 check_VecOperands (const insn_template
*t
)
5756 /* Templates allowing for ZMMword as well as YMMword and/or XMMword for
5757 any one operand are implicity requiring AVX512VL support if the actual
5758 operand size is YMMword or XMMword. Since this function runs after
5759 template matching, there's no need to check for YMMword/XMMword in
5761 cpu
= cpu_flags_and (t
->cpu_flags
, avx512
);
5762 if (!cpu_flags_all_zero (&cpu
)
5763 && !t
->cpu_flags
.bitfield
.cpuavx512vl
5764 && !cpu_arch_flags
.bitfield
.cpuavx512vl
)
5766 for (op
= 0; op
< t
->operands
; ++op
)
5768 if (t
->operand_types
[op
].bitfield
.zmmword
5769 && (i
.types
[op
].bitfield
.ymmword
5770 || i
.types
[op
].bitfield
.xmmword
))
5772 i
.error
= unsupported
;
5778 /* Without VSIB byte, we can't have a vector register for index. */
5779 if (!t
->opcode_modifier
.vecsib
5781 && (i
.index_reg
->reg_type
.bitfield
.xmmword
5782 || i
.index_reg
->reg_type
.bitfield
.ymmword
5783 || i
.index_reg
->reg_type
.bitfield
.zmmword
))
5785 i
.error
= unsupported_vector_index_register
;
5789 /* Check if default mask is allowed. */
5790 if (t
->opcode_modifier
.nodefmask
5791 && (!i
.mask
|| i
.mask
->mask
->reg_num
== 0))
5793 i
.error
= no_default_mask
;
5797 /* For VSIB byte, we need a vector register for index, and all vector
5798 registers must be distinct. */
5799 if (t
->opcode_modifier
.vecsib
)
5802 || !((t
->opcode_modifier
.vecsib
== VecSIB128
5803 && i
.index_reg
->reg_type
.bitfield
.xmmword
)
5804 || (t
->opcode_modifier
.vecsib
== VecSIB256
5805 && i
.index_reg
->reg_type
.bitfield
.ymmword
)
5806 || (t
->opcode_modifier
.vecsib
== VecSIB512
5807 && i
.index_reg
->reg_type
.bitfield
.zmmword
)))
5809 i
.error
= invalid_vsib_address
;
5813 gas_assert (i
.reg_operands
== 2 || i
.mask
);
5814 if (i
.reg_operands
== 2 && !i
.mask
)
5816 gas_assert (i
.types
[0].bitfield
.class == RegSIMD
);
5817 gas_assert (i
.types
[0].bitfield
.xmmword
5818 || i
.types
[0].bitfield
.ymmword
);
5819 gas_assert (i
.types
[2].bitfield
.class == RegSIMD
);
5820 gas_assert (i
.types
[2].bitfield
.xmmword
5821 || i
.types
[2].bitfield
.ymmword
);
5822 if (operand_check
== check_none
)
5824 if (register_number (i
.op
[0].regs
)
5825 != register_number (i
.index_reg
)
5826 && register_number (i
.op
[2].regs
)
5827 != register_number (i
.index_reg
)
5828 && register_number (i
.op
[0].regs
)
5829 != register_number (i
.op
[2].regs
))
5831 if (operand_check
== check_error
)
5833 i
.error
= invalid_vector_register_set
;
5836 as_warn (_("mask, index, and destination registers should be distinct"));
5838 else if (i
.reg_operands
== 1 && i
.mask
)
5840 if (i
.types
[1].bitfield
.class == RegSIMD
5841 && (i
.types
[1].bitfield
.xmmword
5842 || i
.types
[1].bitfield
.ymmword
5843 || i
.types
[1].bitfield
.zmmword
)
5844 && (register_number (i
.op
[1].regs
)
5845 == register_number (i
.index_reg
)))
5847 if (operand_check
== check_error
)
5849 i
.error
= invalid_vector_register_set
;
5852 if (operand_check
!= check_none
)
5853 as_warn (_("index and destination registers should be distinct"));
5858 /* Check if broadcast is supported by the instruction and is applied
5859 to the memory operand. */
5862 i386_operand_type type
, overlap
;
5864 /* Check if specified broadcast is supported in this instruction,
5865 and its broadcast bytes match the memory operand. */
5866 op
= i
.broadcast
->operand
;
5867 if (!t
->opcode_modifier
.broadcast
5868 || !(i
.flags
[op
] & Operand_Mem
)
5869 || (!i
.types
[op
].bitfield
.unspecified
5870 && !match_broadcast_size (t
, op
)))
5873 i
.error
= unsupported_broadcast
;
5877 i
.broadcast
->bytes
= ((1 << (t
->opcode_modifier
.broadcast
- 1))
5878 * i
.broadcast
->type
);
5879 operand_type_set (&type
, 0);
5880 switch (i
.broadcast
->bytes
)
5883 type
.bitfield
.word
= 1;
5886 type
.bitfield
.dword
= 1;
5889 type
.bitfield
.qword
= 1;
5892 type
.bitfield
.xmmword
= 1;
5895 type
.bitfield
.ymmword
= 1;
5898 type
.bitfield
.zmmword
= 1;
5904 overlap
= operand_type_and (type
, t
->operand_types
[op
]);
5905 if (t
->operand_types
[op
].bitfield
.class == RegSIMD
5906 && t
->operand_types
[op
].bitfield
.byte
5907 + t
->operand_types
[op
].bitfield
.word
5908 + t
->operand_types
[op
].bitfield
.dword
5909 + t
->operand_types
[op
].bitfield
.qword
> 1)
5911 overlap
.bitfield
.xmmword
= 0;
5912 overlap
.bitfield
.ymmword
= 0;
5913 overlap
.bitfield
.zmmword
= 0;
5915 if (operand_type_all_zero (&overlap
))
5918 if (t
->opcode_modifier
.checkregsize
)
5922 type
.bitfield
.baseindex
= 1;
5923 for (j
= 0; j
< i
.operands
; ++j
)
5926 && !operand_type_register_match(i
.types
[j
],
5927 t
->operand_types
[j
],
5929 t
->operand_types
[op
]))
5934 /* If broadcast is supported in this instruction, we need to check if
5935 operand of one-element size isn't specified without broadcast. */
5936 else if (t
->opcode_modifier
.broadcast
&& i
.mem_operands
)
5938 /* Find memory operand. */
5939 for (op
= 0; op
< i
.operands
; op
++)
5940 if (i
.flags
[op
] & Operand_Mem
)
5942 gas_assert (op
< i
.operands
);
5943 /* Check size of the memory operand. */
5944 if (match_broadcast_size (t
, op
))
5946 i
.error
= broadcast_needed
;
5951 op
= MAX_OPERANDS
- 1; /* Avoid uninitialized variable warning. */
5953 /* Check if requested masking is supported. */
5956 switch (t
->opcode_modifier
.masking
)
5960 case MERGING_MASKING
:
5961 if (i
.mask
->zeroing
)
5964 i
.error
= unsupported_masking
;
5968 case DYNAMIC_MASKING
:
5969 /* Memory destinations allow only merging masking. */
5970 if (i
.mask
->zeroing
&& i
.mem_operands
)
5972 /* Find memory operand. */
5973 for (op
= 0; op
< i
.operands
; op
++)
5974 if (i
.flags
[op
] & Operand_Mem
)
5976 gas_assert (op
< i
.operands
);
5977 if (op
== i
.operands
- 1)
5979 i
.error
= unsupported_masking
;
5989 /* Check if masking is applied to dest operand. */
5990 if (i
.mask
&& (i
.mask
->operand
!= (int) (i
.operands
- 1)))
5992 i
.error
= mask_not_on_destination
;
5999 if (!t
->opcode_modifier
.sae
6000 || (i
.rounding
->type
!= saeonly
&& !t
->opcode_modifier
.staticrounding
))
6002 i
.error
= unsupported_rc_sae
;
6005 /* If the instruction has several immediate operands and one of
6006 them is rounding, the rounding operand should be the last
6007 immediate operand. */
6008 if (i
.imm_operands
> 1
6009 && i
.rounding
->operand
!= (int) (i
.imm_operands
- 1))
6011 i
.error
= rc_sae_operand_not_last_imm
;
6016 /* Check the special Imm4 cases; must be the first operand. */
6017 if (t
->cpu_flags
.bitfield
.cpuxop
&& t
->operands
== 5)
6019 if (i
.op
[0].imms
->X_op
!= O_constant
6020 || !fits_in_imm4 (i
.op
[0].imms
->X_add_number
))
6026 /* Turn off Imm<N> so that update_imm won't complain. */
6027 operand_type_set (&i
.types
[0], 0);
6030 /* Check vector Disp8 operand. */
6031 if (t
->opcode_modifier
.disp8memshift
6032 && i
.disp_encoding
!= disp_encoding_32bit
)
6035 i
.memshift
= t
->opcode_modifier
.broadcast
- 1;
6036 else if (t
->opcode_modifier
.disp8memshift
!= DISP8_SHIFT_VL
)
6037 i
.memshift
= t
->opcode_modifier
.disp8memshift
;
6040 const i386_operand_type
*type
= NULL
;
6043 for (op
= 0; op
< i
.operands
; op
++)
6044 if (i
.flags
[op
] & Operand_Mem
)
6046 if (t
->opcode_modifier
.evex
== EVEXLIG
)
6047 i
.memshift
= 2 + (i
.suffix
== QWORD_MNEM_SUFFIX
);
6048 else if (t
->operand_types
[op
].bitfield
.xmmword
6049 + t
->operand_types
[op
].bitfield
.ymmword
6050 + t
->operand_types
[op
].bitfield
.zmmword
<= 1)
6051 type
= &t
->operand_types
[op
];
6052 else if (!i
.types
[op
].bitfield
.unspecified
)
6053 type
= &i
.types
[op
];
6055 else if (i
.types
[op
].bitfield
.class == RegSIMD
6056 && t
->opcode_modifier
.evex
!= EVEXLIG
)
6058 if (i
.types
[op
].bitfield
.zmmword
)
6060 else if (i
.types
[op
].bitfield
.ymmword
&& i
.memshift
< 5)
6062 else if (i
.types
[op
].bitfield
.xmmword
&& i
.memshift
< 4)
6068 if (type
->bitfield
.zmmword
)
6070 else if (type
->bitfield
.ymmword
)
6072 else if (type
->bitfield
.xmmword
)
6076 /* For the check in fits_in_disp8(). */
6077 if (i
.memshift
== 0)
6081 for (op
= 0; op
< i
.operands
; op
++)
6082 if (operand_type_check (i
.types
[op
], disp
)
6083 && i
.op
[op
].disps
->X_op
== O_constant
)
6085 if (fits_in_disp8 (i
.op
[op
].disps
->X_add_number
))
6087 i
.types
[op
].bitfield
.disp8
= 1;
6090 i
.types
[op
].bitfield
.disp8
= 0;
6099 /* Check if encoding requirements are met by the instruction. */
6102 VEX_check_encoding (const insn_template
*t
)
6104 if (i
.vec_encoding
== vex_encoding_error
)
6106 i
.error
= unsupported
;
6110 if (i
.vec_encoding
== vex_encoding_evex
)
6112 /* This instruction must be encoded with EVEX prefix. */
6113 if (!is_evex_encoding (t
))
6115 i
.error
= unsupported
;
6121 if (!t
->opcode_modifier
.vex
)
6123 /* This instruction template doesn't have VEX prefix. */
6124 if (i
.vec_encoding
!= vex_encoding_default
)
6126 i
.error
= unsupported
;
6135 static const insn_template
*
6136 match_template (char mnem_suffix
)
6138 /* Points to template once we've found it. */
6139 const insn_template
*t
;
6140 i386_operand_type overlap0
, overlap1
, overlap2
, overlap3
;
6141 i386_operand_type overlap4
;
6142 unsigned int found_reverse_match
;
6143 i386_opcode_modifier suffix_check
;
6144 i386_operand_type operand_types
[MAX_OPERANDS
];
6145 int addr_prefix_disp
;
6146 unsigned int j
, size_match
, check_register
;
6147 enum i386_error specific_error
= 0;
6149 #if MAX_OPERANDS != 5
6150 # error "MAX_OPERANDS must be 5."
6153 found_reverse_match
= 0;
6154 addr_prefix_disp
= -1;
6156 /* Prepare for mnemonic suffix check. */
6157 memset (&suffix_check
, 0, sizeof (suffix_check
));
6158 switch (mnem_suffix
)
6160 case BYTE_MNEM_SUFFIX
:
6161 suffix_check
.no_bsuf
= 1;
6163 case WORD_MNEM_SUFFIX
:
6164 suffix_check
.no_wsuf
= 1;
6166 case SHORT_MNEM_SUFFIX
:
6167 suffix_check
.no_ssuf
= 1;
6169 case LONG_MNEM_SUFFIX
:
6170 suffix_check
.no_lsuf
= 1;
6172 case QWORD_MNEM_SUFFIX
:
6173 suffix_check
.no_qsuf
= 1;
6176 /* NB: In Intel syntax, normally we can check for memory operand
6177 size when there is no mnemonic suffix. But jmp and call have
6178 2 different encodings with Dword memory operand size, one with
6179 No_ldSuf and the other without. i.suffix is set to
6180 LONG_DOUBLE_MNEM_SUFFIX to skip the one with No_ldSuf. */
6181 if (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
)
6182 suffix_check
.no_ldsuf
= 1;
6185 /* Must have right number of operands. */
6186 i
.error
= number_of_operands_mismatch
;
6188 for (t
= current_templates
->start
; t
< current_templates
->end
; t
++)
6190 addr_prefix_disp
= -1;
6191 found_reverse_match
= 0;
6193 if (i
.operands
!= t
->operands
)
6196 /* Check processor support. */
6197 i
.error
= unsupported
;
6198 if (cpu_flags_match (t
) != CPU_FLAGS_PERFECT_MATCH
)
6201 /* Check AT&T mnemonic. */
6202 i
.error
= unsupported_with_intel_mnemonic
;
6203 if (intel_mnemonic
&& t
->opcode_modifier
.attmnemonic
)
6206 /* Check AT&T/Intel syntax. */
6207 i
.error
= unsupported_syntax
;
6208 if ((intel_syntax
&& t
->opcode_modifier
.attsyntax
)
6209 || (!intel_syntax
&& t
->opcode_modifier
.intelsyntax
))
6212 /* Check Intel64/AMD64 ISA. */
6216 /* Default: Don't accept Intel64. */
6217 if (t
->opcode_modifier
.isa64
== INTEL64
)
6221 /* -mamd64: Don't accept Intel64 and Intel64 only. */
6222 if (t
->opcode_modifier
.isa64
>= INTEL64
)
6226 /* -mintel64: Don't accept AMD64. */
6227 if (t
->opcode_modifier
.isa64
== AMD64
&& flag_code
== CODE_64BIT
)
6232 /* Check the suffix. */
6233 i
.error
= invalid_instruction_suffix
;
6234 if ((t
->opcode_modifier
.no_bsuf
&& suffix_check
.no_bsuf
)
6235 || (t
->opcode_modifier
.no_wsuf
&& suffix_check
.no_wsuf
)
6236 || (t
->opcode_modifier
.no_lsuf
&& suffix_check
.no_lsuf
)
6237 || (t
->opcode_modifier
.no_ssuf
&& suffix_check
.no_ssuf
)
6238 || (t
->opcode_modifier
.no_qsuf
&& suffix_check
.no_qsuf
)
6239 || (t
->opcode_modifier
.no_ldsuf
&& suffix_check
.no_ldsuf
))
6242 size_match
= operand_size_match (t
);
6246 /* This is intentionally not
6248 if (i.jumpabsolute != (t->opcode_modifier.jump == JUMP_ABSOLUTE))
6250 as the case of a missing * on the operand is accepted (perhaps with
6251 a warning, issued further down). */
6252 if (i
.jumpabsolute
&& t
->opcode_modifier
.jump
!= JUMP_ABSOLUTE
)
6254 i
.error
= operand_type_mismatch
;
6258 for (j
= 0; j
< MAX_OPERANDS
; j
++)
6259 operand_types
[j
] = t
->operand_types
[j
];
6261 /* In general, don't allow
6262 - 64-bit operands outside of 64-bit mode,
6263 - 32-bit operands on pre-386. */
6264 j
= i
.imm_operands
+ (t
->operands
> i
.imm_operands
+ 1);
6265 if (((i
.suffix
== QWORD_MNEM_SUFFIX
6266 && flag_code
!= CODE_64BIT
6267 && (t
->base_opcode
!= 0x0fc7
6268 || t
->extension_opcode
!= 1 /* cmpxchg8b */))
6269 || (i
.suffix
== LONG_MNEM_SUFFIX
6270 && !cpu_arch_flags
.bitfield
.cpui386
))
6272 ? (t
->opcode_modifier
.mnemonicsize
!= IGNORESIZE
6273 && !intel_float_operand (t
->name
))
6274 : intel_float_operand (t
->name
) != 2)
6275 && (t
->operands
== i
.imm_operands
6276 || (operand_types
[i
.imm_operands
].bitfield
.class != RegMMX
6277 && operand_types
[i
.imm_operands
].bitfield
.class != RegSIMD
6278 && operand_types
[i
.imm_operands
].bitfield
.class != RegMask
)
6279 || (operand_types
[j
].bitfield
.class != RegMMX
6280 && operand_types
[j
].bitfield
.class != RegSIMD
6281 && operand_types
[j
].bitfield
.class != RegMask
))
6282 && !t
->opcode_modifier
.vecsib
)
6285 /* Do not verify operands when there are none. */
6288 if (VEX_check_encoding (t
))
6290 specific_error
= i
.error
;
6294 /* We've found a match; break out of loop. */
6298 if (!t
->opcode_modifier
.jump
6299 || t
->opcode_modifier
.jump
== JUMP_ABSOLUTE
)
6301 /* There should be only one Disp operand. */
6302 for (j
= 0; j
< MAX_OPERANDS
; j
++)
6303 if (operand_type_check (operand_types
[j
], disp
))
6305 if (j
< MAX_OPERANDS
)
6307 bfd_boolean override
= (i
.prefix
[ADDR_PREFIX
] != 0);
6309 addr_prefix_disp
= j
;
6311 /* Address size prefix will turn Disp64/Disp32S/Disp32/Disp16
6312 operand into Disp32/Disp32/Disp16/Disp32 operand. */
6316 override
= !override
;
6319 if (operand_types
[j
].bitfield
.disp32
6320 && operand_types
[j
].bitfield
.disp16
)
6322 operand_types
[j
].bitfield
.disp16
= override
;
6323 operand_types
[j
].bitfield
.disp32
= !override
;
6325 operand_types
[j
].bitfield
.disp32s
= 0;
6326 operand_types
[j
].bitfield
.disp64
= 0;
6330 if (operand_types
[j
].bitfield
.disp32s
6331 || operand_types
[j
].bitfield
.disp64
)
6333 operand_types
[j
].bitfield
.disp64
&= !override
;
6334 operand_types
[j
].bitfield
.disp32s
&= !override
;
6335 operand_types
[j
].bitfield
.disp32
= override
;
6337 operand_types
[j
].bitfield
.disp16
= 0;
6343 /* Force 0x8b encoding for "mov foo@GOT, %eax". */
6344 if (i
.reloc
[0] == BFD_RELOC_386_GOT32
&& t
->base_opcode
== 0xa0)
6347 /* We check register size if needed. */
6348 if (t
->opcode_modifier
.checkregsize
)
6350 check_register
= (1 << t
->operands
) - 1;
6352 check_register
&= ~(1 << i
.broadcast
->operand
);
6357 overlap0
= operand_type_and (i
.types
[0], operand_types
[0]);
6358 switch (t
->operands
)
6361 if (!operand_type_match (overlap0
, i
.types
[0]))
6365 /* xchg %eax, %eax is a special case. It is an alias for nop
6366 only in 32bit mode and we can use opcode 0x90. In 64bit
6367 mode, we can't use 0x90 for xchg %eax, %eax since it should
6368 zero-extend %eax to %rax. */
6369 if (flag_code
== CODE_64BIT
6370 && t
->base_opcode
== 0x90
6371 && i
.types
[0].bitfield
.instance
== Accum
6372 && i
.types
[0].bitfield
.dword
6373 && i
.types
[1].bitfield
.instance
== Accum
6374 && i
.types
[1].bitfield
.dword
)
6376 /* xrelease mov %eax, <disp> is another special case. It must not
6377 match the accumulator-only encoding of mov. */
6378 if (flag_code
!= CODE_64BIT
6380 && t
->base_opcode
== 0xa0
6381 && i
.types
[0].bitfield
.instance
== Accum
6382 && (i
.flags
[1] & Operand_Mem
))
6387 if (!(size_match
& MATCH_STRAIGHT
))
6389 /* Reverse direction of operands if swapping is possible in the first
6390 place (operands need to be symmetric) and
6391 - the load form is requested, and the template is a store form,
6392 - the store form is requested, and the template is a load form,
6393 - the non-default (swapped) form is requested. */
6394 overlap1
= operand_type_and (operand_types
[0], operand_types
[1]);
6395 if (t
->opcode_modifier
.d
&& i
.reg_operands
== i
.operands
6396 && !operand_type_all_zero (&overlap1
))
6397 switch (i
.dir_encoding
)
6399 case dir_encoding_load
:
6400 if (operand_type_check (operand_types
[i
.operands
- 1], anymem
)
6401 || t
->opcode_modifier
.regmem
)
6405 case dir_encoding_store
:
6406 if (!operand_type_check (operand_types
[i
.operands
- 1], anymem
)
6407 && !t
->opcode_modifier
.regmem
)
6411 case dir_encoding_swap
:
6414 case dir_encoding_default
:
6417 /* If we want store form, we skip the current load. */
6418 if ((i
.dir_encoding
== dir_encoding_store
6419 || i
.dir_encoding
== dir_encoding_swap
)
6420 && i
.mem_operands
== 0
6421 && t
->opcode_modifier
.load
)
6426 overlap1
= operand_type_and (i
.types
[1], operand_types
[1]);
6427 if (!operand_type_match (overlap0
, i
.types
[0])
6428 || !operand_type_match (overlap1
, i
.types
[1])
6429 || ((check_register
& 3) == 3
6430 && !operand_type_register_match (i
.types
[0],
6435 /* Check if other direction is valid ... */
6436 if (!t
->opcode_modifier
.d
)
6440 if (!(size_match
& MATCH_REVERSE
))
6442 /* Try reversing direction of operands. */
6443 overlap0
= operand_type_and (i
.types
[0], operand_types
[i
.operands
- 1]);
6444 overlap1
= operand_type_and (i
.types
[i
.operands
- 1], operand_types
[0]);
6445 if (!operand_type_match (overlap0
, i
.types
[0])
6446 || !operand_type_match (overlap1
, i
.types
[i
.operands
- 1])
6448 && !operand_type_register_match (i
.types
[0],
6449 operand_types
[i
.operands
- 1],
6450 i
.types
[i
.operands
- 1],
6453 /* Does not match either direction. */
6456 /* found_reverse_match holds which of D or FloatR
6458 if (!t
->opcode_modifier
.d
)
6459 found_reverse_match
= 0;
6460 else if (operand_types
[0].bitfield
.tbyte
)
6461 found_reverse_match
= Opcode_FloatD
;
6462 else if (operand_types
[0].bitfield
.xmmword
6463 || operand_types
[i
.operands
- 1].bitfield
.xmmword
6464 || operand_types
[0].bitfield
.class == RegMMX
6465 || operand_types
[i
.operands
- 1].bitfield
.class == RegMMX
6466 || is_any_vex_encoding(t
))
6467 found_reverse_match
= (t
->base_opcode
& 0xee) != 0x6e
6468 ? Opcode_SIMD_FloatD
: Opcode_SIMD_IntD
;
6470 found_reverse_match
= Opcode_D
;
6471 if (t
->opcode_modifier
.floatr
)
6472 found_reverse_match
|= Opcode_FloatR
;
6476 /* Found a forward 2 operand match here. */
6477 switch (t
->operands
)
6480 overlap4
= operand_type_and (i
.types
[4],
6484 overlap3
= operand_type_and (i
.types
[3],
6488 overlap2
= operand_type_and (i
.types
[2],
6493 switch (t
->operands
)
6496 if (!operand_type_match (overlap4
, i
.types
[4])
6497 || !operand_type_register_match (i
.types
[3],
6504 if (!operand_type_match (overlap3
, i
.types
[3])
6505 || ((check_register
& 0xa) == 0xa
6506 && !operand_type_register_match (i
.types
[1],
6510 || ((check_register
& 0xc) == 0xc
6511 && !operand_type_register_match (i
.types
[2],
6518 /* Here we make use of the fact that there are no
6519 reverse match 3 operand instructions. */
6520 if (!operand_type_match (overlap2
, i
.types
[2])
6521 || ((check_register
& 5) == 5
6522 && !operand_type_register_match (i
.types
[0],
6526 || ((check_register
& 6) == 6
6527 && !operand_type_register_match (i
.types
[1],
6535 /* Found either forward/reverse 2, 3 or 4 operand match here:
6536 slip through to break. */
6539 /* Check if vector operands are valid. */
6540 if (check_VecOperands (t
))
6542 specific_error
= i
.error
;
6546 /* Check if VEX/EVEX encoding requirements can be satisfied. */
6547 if (VEX_check_encoding (t
))
6549 specific_error
= i
.error
;
6553 /* We've found a match; break out of loop. */
6557 if (t
== current_templates
->end
)
6559 /* We found no match. */
6560 const char *err_msg
;
6561 switch (specific_error
? specific_error
: i
.error
)
6565 case operand_size_mismatch
:
6566 err_msg
= _("operand size mismatch");
6568 case operand_type_mismatch
:
6569 err_msg
= _("operand type mismatch");
6571 case register_type_mismatch
:
6572 err_msg
= _("register type mismatch");
6574 case number_of_operands_mismatch
:
6575 err_msg
= _("number of operands mismatch");
6577 case invalid_instruction_suffix
:
6578 err_msg
= _("invalid instruction suffix");
6581 err_msg
= _("constant doesn't fit in 4 bits");
6583 case unsupported_with_intel_mnemonic
:
6584 err_msg
= _("unsupported with Intel mnemonic");
6586 case unsupported_syntax
:
6587 err_msg
= _("unsupported syntax");
6590 as_bad (_("unsupported instruction `%s'"),
6591 current_templates
->start
->name
);
6593 case invalid_vsib_address
:
6594 err_msg
= _("invalid VSIB address");
6596 case invalid_vector_register_set
:
6597 err_msg
= _("mask, index, and destination registers must be distinct");
6599 case unsupported_vector_index_register
:
6600 err_msg
= _("unsupported vector index register");
6602 case unsupported_broadcast
:
6603 err_msg
= _("unsupported broadcast");
6605 case broadcast_needed
:
6606 err_msg
= _("broadcast is needed for operand of such type");
6608 case unsupported_masking
:
6609 err_msg
= _("unsupported masking");
6611 case mask_not_on_destination
:
6612 err_msg
= _("mask not on destination operand");
6614 case no_default_mask
:
6615 err_msg
= _("default mask isn't allowed");
6617 case unsupported_rc_sae
:
6618 err_msg
= _("unsupported static rounding/sae");
6620 case rc_sae_operand_not_last_imm
:
6622 err_msg
= _("RC/SAE operand must precede immediate operands");
6624 err_msg
= _("RC/SAE operand must follow immediate operands");
6626 case invalid_register_operand
:
6627 err_msg
= _("invalid register operand");
6630 as_bad (_("%s for `%s'"), err_msg
,
6631 current_templates
->start
->name
);
6635 if (!quiet_warnings
)
6638 && (i
.jumpabsolute
!= (t
->opcode_modifier
.jump
== JUMP_ABSOLUTE
)))
6639 as_warn (_("indirect %s without `*'"), t
->name
);
6641 if (t
->opcode_modifier
.isprefix
6642 && t
->opcode_modifier
.mnemonicsize
== IGNORESIZE
)
6644 /* Warn them that a data or address size prefix doesn't
6645 affect assembly of the next line of code. */
6646 as_warn (_("stand-alone `%s' prefix"), t
->name
);
6650 /* Copy the template we found. */
6653 if (addr_prefix_disp
!= -1)
6654 i
.tm
.operand_types
[addr_prefix_disp
]
6655 = operand_types
[addr_prefix_disp
];
6657 if (found_reverse_match
)
6659 /* If we found a reverse match we must alter the opcode direction
6660 bit and clear/flip the regmem modifier one. found_reverse_match
6661 holds bits to change (different for int & float insns). */
6663 i
.tm
.base_opcode
^= found_reverse_match
;
6665 i
.tm
.operand_types
[0] = operand_types
[i
.operands
- 1];
6666 i
.tm
.operand_types
[i
.operands
- 1] = operand_types
[0];
6668 /* Certain SIMD insns have their load forms specified in the opcode
6669 table, and hence we need to _set_ RegMem instead of clearing it.
6670 We need to avoid setting the bit though on insns like KMOVW. */
6671 i
.tm
.opcode_modifier
.regmem
6672 = i
.tm
.opcode_modifier
.modrm
&& i
.tm
.opcode_modifier
.d
6673 && i
.tm
.operands
> 2U - i
.tm
.opcode_modifier
.sse2avx
6674 && !i
.tm
.opcode_modifier
.regmem
;
6683 unsigned int es_op
= i
.tm
.opcode_modifier
.isstring
- IS_STRING_ES_OP0
;
6684 unsigned int op
= i
.tm
.operand_types
[0].bitfield
.baseindex
? es_op
: 0;
6686 if (i
.seg
[op
] != NULL
&& i
.seg
[op
] != &es
)
6688 as_bad (_("`%s' operand %u must use `%ses' segment"),
6690 intel_syntax
? i
.tm
.operands
- es_op
: es_op
+ 1,
6695 /* There's only ever one segment override allowed per instruction.
6696 This instruction possibly has a legal segment override on the
6697 second operand, so copy the segment to where non-string
6698 instructions store it, allowing common code. */
6699 i
.seg
[op
] = i
.seg
[1];
6705 process_suffix (void)
6707 /* If matched instruction specifies an explicit instruction mnemonic
6709 if (i
.tm
.opcode_modifier
.size
== SIZE16
)
6710 i
.suffix
= WORD_MNEM_SUFFIX
;
6711 else if (i
.tm
.opcode_modifier
.size
== SIZE32
)
6712 i
.suffix
= LONG_MNEM_SUFFIX
;
6713 else if (i
.tm
.opcode_modifier
.size
== SIZE64
)
6714 i
.suffix
= QWORD_MNEM_SUFFIX
;
6715 else if (i
.reg_operands
6716 && (i
.operands
> 1 || i
.types
[0].bitfield
.class == Reg
)
6717 && !i
.tm
.opcode_modifier
.addrprefixopreg
)
6719 unsigned int numop
= i
.operands
;
6721 /* movsx/movzx want only their source operand considered here, for the
6722 ambiguity checking below. The suffix will be replaced afterwards
6723 to represent the destination (register). */
6724 if (((i
.tm
.base_opcode
| 8) == 0xfbe && i
.tm
.opcode_modifier
.w
)
6725 || (i
.tm
.base_opcode
== 0x63 && i
.tm
.cpu_flags
.bitfield
.cpu64
))
6728 /* crc32 needs REX.W set regardless of suffix / source operand size. */
6729 if (i
.tm
.base_opcode
== 0xf20f38f0
6730 && i
.tm
.operand_types
[1].bitfield
.qword
)
6733 /* If there's no instruction mnemonic suffix we try to invent one
6734 based on GPR operands. */
6737 /* We take i.suffix from the last register operand specified,
6738 Destination register type is more significant than source
6739 register type. crc32 in SSE4.2 prefers source register
6741 unsigned int op
= i
.tm
.base_opcode
!= 0xf20f38f0 ? i
.operands
: 1;
6744 if (i
.tm
.operand_types
[op
].bitfield
.instance
== InstanceNone
6745 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
6747 if (i
.types
[op
].bitfield
.class != Reg
)
6749 if (i
.types
[op
].bitfield
.byte
)
6750 i
.suffix
= BYTE_MNEM_SUFFIX
;
6751 else if (i
.types
[op
].bitfield
.word
)
6752 i
.suffix
= WORD_MNEM_SUFFIX
;
6753 else if (i
.types
[op
].bitfield
.dword
)
6754 i
.suffix
= LONG_MNEM_SUFFIX
;
6755 else if (i
.types
[op
].bitfield
.qword
)
6756 i
.suffix
= QWORD_MNEM_SUFFIX
;
6762 /* As an exception, movsx/movzx silently default to a byte source
6764 if ((i
.tm
.base_opcode
| 8) == 0xfbe && i
.tm
.opcode_modifier
.w
6765 && !i
.suffix
&& !intel_syntax
)
6766 i
.suffix
= BYTE_MNEM_SUFFIX
;
6768 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
6771 && i
.tm
.opcode_modifier
.mnemonicsize
== IGNORESIZE
6772 && i
.tm
.opcode_modifier
.no_bsuf
)
6774 else if (!check_byte_reg ())
6777 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
6780 && i
.tm
.opcode_modifier
.mnemonicsize
== IGNORESIZE
6781 && i
.tm
.opcode_modifier
.no_lsuf
6782 && !i
.tm
.opcode_modifier
.todword
6783 && !i
.tm
.opcode_modifier
.toqword
)
6785 else if (!check_long_reg ())
6788 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
6791 && i
.tm
.opcode_modifier
.mnemonicsize
== IGNORESIZE
6792 && i
.tm
.opcode_modifier
.no_qsuf
6793 && !i
.tm
.opcode_modifier
.todword
6794 && !i
.tm
.opcode_modifier
.toqword
)
6796 else if (!check_qword_reg ())
6799 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
6802 && i
.tm
.opcode_modifier
.mnemonicsize
== IGNORESIZE
6803 && i
.tm
.opcode_modifier
.no_wsuf
)
6805 else if (!check_word_reg ())
6808 else if (intel_syntax
6809 && i
.tm
.opcode_modifier
.mnemonicsize
== IGNORESIZE
)
6810 /* Do nothing if the instruction is going to ignore the prefix. */
6815 /* Undo the movsx/movzx change done above. */
6818 else if (i
.tm
.opcode_modifier
.mnemonicsize
== DEFAULTSIZE
6821 i
.suffix
= stackop_size
;
6822 if (stackop_size
== LONG_MNEM_SUFFIX
)
6824 /* stackop_size is set to LONG_MNEM_SUFFIX for the
6825 .code16gcc directive to support 16-bit mode with
6826 32-bit address. For IRET without a suffix, generate
6827 16-bit IRET (opcode 0xcf) to return from an interrupt
6829 if (i
.tm
.base_opcode
== 0xcf)
6831 i
.suffix
= WORD_MNEM_SUFFIX
;
6832 as_warn (_("generating 16-bit `iret' for .code16gcc directive"));
6834 /* Warn about changed behavior for segment register push/pop. */
6835 else if ((i
.tm
.base_opcode
| 1) == 0x07)
6836 as_warn (_("generating 32-bit `%s', unlike earlier gas versions"),
6841 && (i
.tm
.opcode_modifier
.jump
== JUMP_ABSOLUTE
6842 || i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
6843 || i
.tm
.opcode_modifier
.jump
== JUMP_INTERSEGMENT
6844 || (i
.tm
.base_opcode
== 0x0f01 /* [ls][gi]dt */
6845 && i
.tm
.extension_opcode
<= 3)))
6850 if (!i
.tm
.opcode_modifier
.no_qsuf
)
6852 if (i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
6853 || i
.tm
.opcode_modifier
.no_lsuf
)
6854 i
.suffix
= QWORD_MNEM_SUFFIX
;
6859 if (!i
.tm
.opcode_modifier
.no_lsuf
)
6860 i
.suffix
= LONG_MNEM_SUFFIX
;
6863 if (!i
.tm
.opcode_modifier
.no_wsuf
)
6864 i
.suffix
= WORD_MNEM_SUFFIX
;
6870 && (i
.tm
.opcode_modifier
.mnemonicsize
!= DEFAULTSIZE
6871 /* Also cover lret/retf/iret in 64-bit mode. */
6872 || (flag_code
== CODE_64BIT
6873 && !i
.tm
.opcode_modifier
.no_lsuf
6874 && !i
.tm
.opcode_modifier
.no_qsuf
))
6875 && i
.tm
.opcode_modifier
.mnemonicsize
!= IGNORESIZE
6876 /* Explicit sizing prefixes are assumed to disambiguate insns. */
6877 && !i
.prefix
[DATA_PREFIX
] && !(i
.prefix
[REX_PREFIX
] & REX_W
)
6878 /* Accept FLDENV et al without suffix. */
6879 && (i
.tm
.opcode_modifier
.no_ssuf
|| i
.tm
.opcode_modifier
.floatmf
))
6881 unsigned int suffixes
, evex
= 0;
6883 suffixes
= !i
.tm
.opcode_modifier
.no_bsuf
;
6884 if (!i
.tm
.opcode_modifier
.no_wsuf
)
6886 if (!i
.tm
.opcode_modifier
.no_lsuf
)
6888 if (!i
.tm
.opcode_modifier
.no_ldsuf
)
6890 if (!i
.tm
.opcode_modifier
.no_ssuf
)
6892 if (flag_code
== CODE_64BIT
&& !i
.tm
.opcode_modifier
.no_qsuf
)
6895 /* For [XYZ]MMWORD operands inspect operand sizes. While generally
6896 also suitable for AT&T syntax mode, it was requested that this be
6897 restricted to just Intel syntax. */
6898 if (intel_syntax
&& is_any_vex_encoding (&i
.tm
) && !i
.broadcast
)
6902 for (op
= 0; op
< i
.tm
.operands
; ++op
)
6904 if (is_evex_encoding (&i
.tm
)
6905 && !cpu_arch_flags
.bitfield
.cpuavx512vl
)
6907 if (i
.tm
.operand_types
[op
].bitfield
.ymmword
)
6908 i
.tm
.operand_types
[op
].bitfield
.xmmword
= 0;
6909 if (i
.tm
.operand_types
[op
].bitfield
.zmmword
)
6910 i
.tm
.operand_types
[op
].bitfield
.ymmword
= 0;
6911 if (!i
.tm
.opcode_modifier
.evex
6912 || i
.tm
.opcode_modifier
.evex
== EVEXDYN
)
6913 i
.tm
.opcode_modifier
.evex
= EVEX512
;
6916 if (i
.tm
.operand_types
[op
].bitfield
.xmmword
6917 + i
.tm
.operand_types
[op
].bitfield
.ymmword
6918 + i
.tm
.operand_types
[op
].bitfield
.zmmword
< 2)
6921 /* Any properly sized operand disambiguates the insn. */
6922 if (i
.types
[op
].bitfield
.xmmword
6923 || i
.types
[op
].bitfield
.ymmword
6924 || i
.types
[op
].bitfield
.zmmword
)
6926 suffixes
&= ~(7 << 6);
6931 if ((i
.flags
[op
] & Operand_Mem
)
6932 && i
.tm
.operand_types
[op
].bitfield
.unspecified
)
6934 if (i
.tm
.operand_types
[op
].bitfield
.xmmword
)
6936 if (i
.tm
.operand_types
[op
].bitfield
.ymmword
)
6938 if (i
.tm
.operand_types
[op
].bitfield
.zmmword
)
6940 if (is_evex_encoding (&i
.tm
))
6946 /* Are multiple suffixes / operand sizes allowed? */
6947 if (suffixes
& (suffixes
- 1))
6950 && (i
.tm
.opcode_modifier
.mnemonicsize
!= DEFAULTSIZE
6951 || operand_check
== check_error
))
6953 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
6956 if (operand_check
== check_error
)
6958 as_bad (_("no instruction mnemonic suffix given and "
6959 "no register operands; can't size `%s'"), i
.tm
.name
);
6962 if (operand_check
== check_warning
)
6963 as_warn (_("%s; using default for `%s'"),
6965 ? _("ambiguous operand size")
6966 : _("no instruction mnemonic suffix given and "
6967 "no register operands"),
6970 if (i
.tm
.opcode_modifier
.floatmf
)
6971 i
.suffix
= SHORT_MNEM_SUFFIX
;
6972 else if ((i
.tm
.base_opcode
| 8) == 0xfbe
6973 || (i
.tm
.base_opcode
== 0x63
6974 && i
.tm
.cpu_flags
.bitfield
.cpu64
))
6975 /* handled below */;
6977 i
.tm
.opcode_modifier
.evex
= evex
;
6978 else if (flag_code
== CODE_16BIT
)
6979 i
.suffix
= WORD_MNEM_SUFFIX
;
6980 else if (!i
.tm
.opcode_modifier
.no_lsuf
)
6981 i
.suffix
= LONG_MNEM_SUFFIX
;
6983 i
.suffix
= QWORD_MNEM_SUFFIX
;
6987 if ((i
.tm
.base_opcode
| 8) == 0xfbe
6988 || (i
.tm
.base_opcode
== 0x63 && i
.tm
.cpu_flags
.bitfield
.cpu64
))
6990 /* In Intel syntax, movsx/movzx must have a "suffix" (checked above).
6991 In AT&T syntax, if there is no suffix (warned about above), the default
6992 will be byte extension. */
6993 if (i
.tm
.opcode_modifier
.w
&& i
.suffix
&& i
.suffix
!= BYTE_MNEM_SUFFIX
)
6994 i
.tm
.base_opcode
|= 1;
6996 /* For further processing, the suffix should represent the destination
6997 (register). This is already the case when one was used with
6998 mov[sz][bw]*, but we need to replace it for mov[sz]x, or if there was
6999 no suffix to begin with. */
7000 if (i
.tm
.opcode_modifier
.w
|| i
.tm
.base_opcode
== 0x63 || !i
.suffix
)
7002 if (i
.types
[1].bitfield
.word
)
7003 i
.suffix
= WORD_MNEM_SUFFIX
;
7004 else if (i
.types
[1].bitfield
.qword
)
7005 i
.suffix
= QWORD_MNEM_SUFFIX
;
7007 i
.suffix
= LONG_MNEM_SUFFIX
;
7009 i
.tm
.opcode_modifier
.w
= 0;
7013 if (!i
.tm
.opcode_modifier
.modrm
&& i
.reg_operands
&& i
.tm
.operands
< 3)
7014 i
.short_form
= (i
.tm
.operand_types
[0].bitfield
.class == Reg
)
7015 != (i
.tm
.operand_types
[1].bitfield
.class == Reg
);
7017 /* Change the opcode based on the operand size given by i.suffix. */
7020 /* Size floating point instruction. */
7021 case LONG_MNEM_SUFFIX
:
7022 if (i
.tm
.opcode_modifier
.floatmf
)
7024 i
.tm
.base_opcode
^= 4;
7028 case WORD_MNEM_SUFFIX
:
7029 case QWORD_MNEM_SUFFIX
:
7030 /* It's not a byte, select word/dword operation. */
7031 if (i
.tm
.opcode_modifier
.w
)
7034 i
.tm
.base_opcode
|= 8;
7036 i
.tm
.base_opcode
|= 1;
7039 case SHORT_MNEM_SUFFIX
:
7040 /* Now select between word & dword operations via the operand
7041 size prefix, except for instructions that will ignore this
7043 if (i
.suffix
!= QWORD_MNEM_SUFFIX
7044 && i
.tm
.opcode_modifier
.mnemonicsize
!= IGNORESIZE
7045 && !i
.tm
.opcode_modifier
.floatmf
7046 && !is_any_vex_encoding (&i
.tm
)
7047 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
7048 || (flag_code
== CODE_64BIT
7049 && i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
)))
7051 unsigned int prefix
= DATA_PREFIX_OPCODE
;
7053 if (i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
) /* jcxz, loop */
7054 prefix
= ADDR_PREFIX_OPCODE
;
7056 if (!add_prefix (prefix
))
7060 /* Set mode64 for an operand. */
7061 if (i
.suffix
== QWORD_MNEM_SUFFIX
7062 && flag_code
== CODE_64BIT
7063 && !i
.tm
.opcode_modifier
.norex64
7064 && !i
.tm
.opcode_modifier
.vexw
7065 /* Special case for xchg %rax,%rax. It is NOP and doesn't
7067 && ! (i
.operands
== 2
7068 && i
.tm
.base_opcode
== 0x90
7069 && i
.tm
.extension_opcode
== None
7070 && i
.types
[0].bitfield
.instance
== Accum
7071 && i
.types
[0].bitfield
.qword
7072 && i
.types
[1].bitfield
.instance
== Accum
7073 && i
.types
[1].bitfield
.qword
))
7079 /* Select word/dword/qword operation with explict data sizing prefix
7080 when there are no suitable register operands. */
7081 if (i
.tm
.opcode_modifier
.w
7082 && (i
.prefix
[DATA_PREFIX
] || (i
.prefix
[REX_PREFIX
] & REX_W
))
7084 || (i
.reg_operands
== 1
7086 && (i
.tm
.operand_types
[0].bitfield
.instance
== RegC
7088 || i
.tm
.operand_types
[0].bitfield
.instance
== RegD
7089 || i
.tm
.operand_types
[1].bitfield
.instance
== RegD
7091 || i
.tm
.base_opcode
== 0xf20f38f0))))
7092 i
.tm
.base_opcode
|= 1;
7096 if (i
.tm
.opcode_modifier
.addrprefixopreg
)
7098 gas_assert (!i
.suffix
);
7099 gas_assert (i
.reg_operands
);
7101 if (i
.tm
.operand_types
[0].bitfield
.instance
== Accum
7104 /* The address size override prefix changes the size of the
7106 if (flag_code
== CODE_64BIT
7107 && i
.op
[0].regs
->reg_type
.bitfield
.word
)
7109 as_bad (_("16-bit addressing unavailable for `%s'"),
7114 if ((flag_code
== CODE_32BIT
7115 ? i
.op
[0].regs
->reg_type
.bitfield
.word
7116 : i
.op
[0].regs
->reg_type
.bitfield
.dword
)
7117 && !add_prefix (ADDR_PREFIX_OPCODE
))
7122 /* Check invalid register operand when the address size override
7123 prefix changes the size of register operands. */
7125 enum { need_word
, need_dword
, need_qword
} need
;
7127 if (flag_code
== CODE_32BIT
)
7128 need
= i
.prefix
[ADDR_PREFIX
] ? need_word
: need_dword
;
7129 else if (i
.prefix
[ADDR_PREFIX
])
7132 need
= flag_code
== CODE_64BIT
? need_qword
: need_word
;
7134 for (op
= 0; op
< i
.operands
; op
++)
7136 if (i
.types
[op
].bitfield
.class != Reg
)
7142 if (i
.op
[op
].regs
->reg_type
.bitfield
.word
)
7146 if (i
.op
[op
].regs
->reg_type
.bitfield
.dword
)
7150 if (i
.op
[op
].regs
->reg_type
.bitfield
.qword
)
7155 as_bad (_("invalid register operand size for `%s'"),
7166 check_byte_reg (void)
7170 for (op
= i
.operands
; --op
>= 0;)
7172 /* Skip non-register operands. */
7173 if (i
.types
[op
].bitfield
.class != Reg
)
7176 /* If this is an eight bit register, it's OK. If it's the 16 or
7177 32 bit version of an eight bit register, we will just use the
7178 low portion, and that's OK too. */
7179 if (i
.types
[op
].bitfield
.byte
)
7182 /* I/O port address operands are OK too. */
7183 if (i
.tm
.operand_types
[op
].bitfield
.instance
== RegD
7184 && i
.tm
.operand_types
[op
].bitfield
.word
)
7187 /* crc32 only wants its source operand checked here. */
7188 if (i
.tm
.base_opcode
== 0xf20f38f0 && op
)
7191 /* Any other register is bad. */
7192 as_bad (_("`%s%s' not allowed with `%s%c'"),
7193 register_prefix
, i
.op
[op
].regs
->reg_name
,
7194 i
.tm
.name
, i
.suffix
);
7201 check_long_reg (void)
7205 for (op
= i
.operands
; --op
>= 0;)
7206 /* Skip non-register operands. */
7207 if (i
.types
[op
].bitfield
.class != Reg
)
7209 /* Reject eight bit registers, except where the template requires
7210 them. (eg. movzb) */
7211 else if (i
.types
[op
].bitfield
.byte
7212 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
7213 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7214 && (i
.tm
.operand_types
[op
].bitfield
.word
7215 || i
.tm
.operand_types
[op
].bitfield
.dword
))
7217 as_bad (_("`%s%s' not allowed with `%s%c'"),
7219 i
.op
[op
].regs
->reg_name
,
7224 /* Error if the e prefix on a general reg is missing. */
7225 else if (i
.types
[op
].bitfield
.word
7226 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
7227 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7228 && i
.tm
.operand_types
[op
].bitfield
.dword
)
7230 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
7231 register_prefix
, i
.op
[op
].regs
->reg_name
,
7235 /* Warn if the r prefix on a general reg is present. */
7236 else if (i
.types
[op
].bitfield
.qword
7237 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
7238 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7239 && i
.tm
.operand_types
[op
].bitfield
.dword
)
7242 && i
.tm
.opcode_modifier
.toqword
7243 && i
.types
[0].bitfield
.class != RegSIMD
)
7245 /* Convert to QWORD. We want REX byte. */
7246 i
.suffix
= QWORD_MNEM_SUFFIX
;
7250 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
7251 register_prefix
, i
.op
[op
].regs
->reg_name
,
7260 check_qword_reg (void)
7264 for (op
= i
.operands
; --op
>= 0; )
7265 /* Skip non-register operands. */
7266 if (i
.types
[op
].bitfield
.class != Reg
)
7268 /* Reject eight bit registers, except where the template requires
7269 them. (eg. movzb) */
7270 else if (i
.types
[op
].bitfield
.byte
7271 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
7272 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7273 && (i
.tm
.operand_types
[op
].bitfield
.word
7274 || i
.tm
.operand_types
[op
].bitfield
.dword
))
7276 as_bad (_("`%s%s' not allowed with `%s%c'"),
7278 i
.op
[op
].regs
->reg_name
,
7283 /* Warn if the r prefix on a general reg is missing. */
7284 else if ((i
.types
[op
].bitfield
.word
7285 || i
.types
[op
].bitfield
.dword
)
7286 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
7287 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7288 && i
.tm
.operand_types
[op
].bitfield
.qword
)
7290 /* Prohibit these changes in the 64bit mode, since the
7291 lowering is more complicated. */
7293 && i
.tm
.opcode_modifier
.todword
7294 && i
.types
[0].bitfield
.class != RegSIMD
)
7296 /* Convert to DWORD. We don't want REX byte. */
7297 i
.suffix
= LONG_MNEM_SUFFIX
;
7301 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
7302 register_prefix
, i
.op
[op
].regs
->reg_name
,
7311 check_word_reg (void)
7314 for (op
= i
.operands
; --op
>= 0;)
7315 /* Skip non-register operands. */
7316 if (i
.types
[op
].bitfield
.class != Reg
)
7318 /* Reject eight bit registers, except where the template requires
7319 them. (eg. movzb) */
7320 else if (i
.types
[op
].bitfield
.byte
7321 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
7322 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7323 && (i
.tm
.operand_types
[op
].bitfield
.word
7324 || i
.tm
.operand_types
[op
].bitfield
.dword
))
7326 as_bad (_("`%s%s' not allowed with `%s%c'"),
7328 i
.op
[op
].regs
->reg_name
,
7333 /* Error if the e or r prefix on a general reg is present. */
7334 else if ((i
.types
[op
].bitfield
.dword
7335 || i
.types
[op
].bitfield
.qword
)
7336 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
7337 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7338 && i
.tm
.operand_types
[op
].bitfield
.word
)
7340 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
7341 register_prefix
, i
.op
[op
].regs
->reg_name
,
7349 update_imm (unsigned int j
)
7351 i386_operand_type overlap
= i
.types
[j
];
7352 if ((overlap
.bitfield
.imm8
7353 || overlap
.bitfield
.imm8s
7354 || overlap
.bitfield
.imm16
7355 || overlap
.bitfield
.imm32
7356 || overlap
.bitfield
.imm32s
7357 || overlap
.bitfield
.imm64
)
7358 && !operand_type_equal (&overlap
, &imm8
)
7359 && !operand_type_equal (&overlap
, &imm8s
)
7360 && !operand_type_equal (&overlap
, &imm16
)
7361 && !operand_type_equal (&overlap
, &imm32
)
7362 && !operand_type_equal (&overlap
, &imm32s
)
7363 && !operand_type_equal (&overlap
, &imm64
))
7367 i386_operand_type temp
;
7369 operand_type_set (&temp
, 0);
7370 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
7372 temp
.bitfield
.imm8
= overlap
.bitfield
.imm8
;
7373 temp
.bitfield
.imm8s
= overlap
.bitfield
.imm8s
;
7375 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
7376 temp
.bitfield
.imm16
= overlap
.bitfield
.imm16
;
7377 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
7379 temp
.bitfield
.imm64
= overlap
.bitfield
.imm64
;
7380 temp
.bitfield
.imm32s
= overlap
.bitfield
.imm32s
;
7383 temp
.bitfield
.imm32
= overlap
.bitfield
.imm32
;
7386 else if (operand_type_equal (&overlap
, &imm16_32_32s
)
7387 || operand_type_equal (&overlap
, &imm16_32
)
7388 || operand_type_equal (&overlap
, &imm16_32s
))
7390 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
7395 else if (i
.prefix
[REX_PREFIX
] & REX_W
)
7396 overlap
= operand_type_and (overlap
, imm32s
);
7397 else if (i
.prefix
[DATA_PREFIX
])
7398 overlap
= operand_type_and (overlap
,
7399 flag_code
!= CODE_16BIT
? imm16
: imm32
);
7400 if (!operand_type_equal (&overlap
, &imm8
)
7401 && !operand_type_equal (&overlap
, &imm8s
)
7402 && !operand_type_equal (&overlap
, &imm16
)
7403 && !operand_type_equal (&overlap
, &imm32
)
7404 && !operand_type_equal (&overlap
, &imm32s
)
7405 && !operand_type_equal (&overlap
, &imm64
))
7407 as_bad (_("no instruction mnemonic suffix given; "
7408 "can't determine immediate size"));
7412 i
.types
[j
] = overlap
;
7422 /* Update the first 2 immediate operands. */
7423 n
= i
.operands
> 2 ? 2 : i
.operands
;
7426 for (j
= 0; j
< n
; j
++)
7427 if (update_imm (j
) == 0)
7430 /* The 3rd operand can't be immediate operand. */
7431 gas_assert (operand_type_check (i
.types
[2], imm
) == 0);
7438 process_operands (void)
7440 /* Default segment register this instruction will use for memory
7441 accesses. 0 means unknown. This is only for optimizing out
7442 unnecessary segment overrides. */
7443 const seg_entry
*default_seg
= 0;
7445 if (i
.tm
.opcode_modifier
.sse2avx
)
7447 /* Legacy encoded insns allow explicit REX prefixes, so these prefixes
7449 i
.rex
|= i
.prefix
[REX_PREFIX
] & (REX_W
| REX_R
| REX_X
| REX_B
);
7450 i
.prefix
[REX_PREFIX
] = 0;
7454 if (i
.tm
.opcode_modifier
.sse2avx
&& i
.tm
.opcode_modifier
.vexvvvv
)
7456 unsigned int dupl
= i
.operands
;
7457 unsigned int dest
= dupl
- 1;
7460 /* The destination must be an xmm register. */
7461 gas_assert (i
.reg_operands
7462 && MAX_OPERANDS
> dupl
7463 && operand_type_equal (&i
.types
[dest
], ®xmm
));
7465 if (i
.tm
.operand_types
[0].bitfield
.instance
== Accum
7466 && i
.tm
.operand_types
[0].bitfield
.xmmword
)
7468 if (i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
)
7470 /* Keep xmm0 for instructions with VEX prefix and 3
7472 i
.tm
.operand_types
[0].bitfield
.instance
= InstanceNone
;
7473 i
.tm
.operand_types
[0].bitfield
.class = RegSIMD
;
7478 /* We remove the first xmm0 and keep the number of
7479 operands unchanged, which in fact duplicates the
7481 for (j
= 1; j
< i
.operands
; j
++)
7483 i
.op
[j
- 1] = i
.op
[j
];
7484 i
.types
[j
- 1] = i
.types
[j
];
7485 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
7486 i
.flags
[j
- 1] = i
.flags
[j
];
7490 else if (i
.tm
.opcode_modifier
.implicit1stxmm0
)
7492 gas_assert ((MAX_OPERANDS
- 1) > dupl
7493 && (i
.tm
.opcode_modifier
.vexsources
7496 /* Add the implicit xmm0 for instructions with VEX prefix
7498 for (j
= i
.operands
; j
> 0; j
--)
7500 i
.op
[j
] = i
.op
[j
- 1];
7501 i
.types
[j
] = i
.types
[j
- 1];
7502 i
.tm
.operand_types
[j
] = i
.tm
.operand_types
[j
- 1];
7503 i
.flags
[j
] = i
.flags
[j
- 1];
7506 = (const reg_entry
*) hash_find (reg_hash
, "xmm0");
7507 i
.types
[0] = regxmm
;
7508 i
.tm
.operand_types
[0] = regxmm
;
7511 i
.reg_operands
+= 2;
7516 i
.op
[dupl
] = i
.op
[dest
];
7517 i
.types
[dupl
] = i
.types
[dest
];
7518 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
7519 i
.flags
[dupl
] = i
.flags
[dest
];
7528 i
.op
[dupl
] = i
.op
[dest
];
7529 i
.types
[dupl
] = i
.types
[dest
];
7530 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
7531 i
.flags
[dupl
] = i
.flags
[dest
];
7534 if (i
.tm
.opcode_modifier
.immext
)
7537 else if (i
.tm
.operand_types
[0].bitfield
.instance
== Accum
7538 && i
.tm
.operand_types
[0].bitfield
.xmmword
)
7542 for (j
= 1; j
< i
.operands
; j
++)
7544 i
.op
[j
- 1] = i
.op
[j
];
7545 i
.types
[j
- 1] = i
.types
[j
];
7547 /* We need to adjust fields in i.tm since they are used by
7548 build_modrm_byte. */
7549 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
7551 i
.flags
[j
- 1] = i
.flags
[j
];
7558 else if (i
.tm
.opcode_modifier
.implicitquadgroup
)
7560 unsigned int regnum
, first_reg_in_group
, last_reg_in_group
;
7562 /* The second operand must be {x,y,z}mmN, where N is a multiple of 4. */
7563 gas_assert (i
.operands
>= 2 && i
.types
[1].bitfield
.class == RegSIMD
);
7564 regnum
= register_number (i
.op
[1].regs
);
7565 first_reg_in_group
= regnum
& ~3;
7566 last_reg_in_group
= first_reg_in_group
+ 3;
7567 if (regnum
!= first_reg_in_group
)
7568 as_warn (_("source register `%s%s' implicitly denotes"
7569 " `%s%.3s%u' to `%s%.3s%u' source group in `%s'"),
7570 register_prefix
, i
.op
[1].regs
->reg_name
,
7571 register_prefix
, i
.op
[1].regs
->reg_name
, first_reg_in_group
,
7572 register_prefix
, i
.op
[1].regs
->reg_name
, last_reg_in_group
,
7575 else if (i
.tm
.opcode_modifier
.regkludge
)
7577 /* The imul $imm, %reg instruction is converted into
7578 imul $imm, %reg, %reg, and the clr %reg instruction
7579 is converted into xor %reg, %reg. */
7581 unsigned int first_reg_op
;
7583 if (operand_type_check (i
.types
[0], reg
))
7587 /* Pretend we saw the extra register operand. */
7588 gas_assert (i
.reg_operands
== 1
7589 && i
.op
[first_reg_op
+ 1].regs
== 0);
7590 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
7591 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
7596 if (i
.tm
.opcode_modifier
.modrm
)
7598 /* The opcode is completed (modulo i.tm.extension_opcode which
7599 must be put into the modrm byte). Now, we make the modrm and
7600 index base bytes based on all the info we've collected. */
7602 default_seg
= build_modrm_byte ();
7604 else if (i
.types
[0].bitfield
.class == SReg
)
7606 if (flag_code
!= CODE_64BIT
7607 ? i
.tm
.base_opcode
== POP_SEG_SHORT
7608 && i
.op
[0].regs
->reg_num
== 1
7609 : (i
.tm
.base_opcode
| 1) == POP_SEG386_SHORT
7610 && i
.op
[0].regs
->reg_num
< 4)
7612 as_bad (_("you can't `%s %s%s'"),
7613 i
.tm
.name
, register_prefix
, i
.op
[0].regs
->reg_name
);
7616 if ( i
.op
[0].regs
->reg_num
> 3 && i
.tm
.opcode_length
== 1 )
7618 i
.tm
.base_opcode
^= POP_SEG_SHORT
^ POP_SEG386_SHORT
;
7619 i
.tm
.opcode_length
= 2;
7621 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
7623 else if ((i
.tm
.base_opcode
& ~0x3) == MOV_AX_DISP32
)
7627 else if (i
.tm
.opcode_modifier
.isstring
)
7629 /* For the string instructions that allow a segment override
7630 on one of their operands, the default segment is ds. */
7633 else if (i
.short_form
)
7635 /* The register or float register operand is in operand
7637 unsigned int op
= i
.tm
.operand_types
[0].bitfield
.class != Reg
;
7639 /* Register goes in low 3 bits of opcode. */
7640 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
7641 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
7643 if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
7645 /* Warn about some common errors, but press on regardless.
7646 The first case can be generated by gcc (<= 2.8.1). */
7647 if (i
.operands
== 2)
7649 /* Reversed arguments on faddp, fsubp, etc. */
7650 as_warn (_("translating to `%s %s%s,%s%s'"), i
.tm
.name
,
7651 register_prefix
, i
.op
[!intel_syntax
].regs
->reg_name
,
7652 register_prefix
, i
.op
[intel_syntax
].regs
->reg_name
);
7656 /* Extraneous `l' suffix on fp insn. */
7657 as_warn (_("translating to `%s %s%s'"), i
.tm
.name
,
7658 register_prefix
, i
.op
[0].regs
->reg_name
);
7663 if ((i
.seg
[0] || i
.prefix
[SEG_PREFIX
])
7664 && i
.tm
.base_opcode
== 0x8d /* lea */
7665 && !is_any_vex_encoding(&i
.tm
))
7667 if (!quiet_warnings
)
7668 as_warn (_("segment override on `%s' is ineffectual"), i
.tm
.name
);
7672 i
.prefix
[SEG_PREFIX
] = 0;
7676 /* If a segment was explicitly specified, and the specified segment
7677 is neither the default nor the one already recorded from a prefix,
7678 use an opcode prefix to select it. If we never figured out what
7679 the default segment is, then default_seg will be zero at this
7680 point, and the specified segment prefix will always be used. */
7682 && i
.seg
[0] != default_seg
7683 && i
.seg
[0]->seg_prefix
!= i
.prefix
[SEG_PREFIX
])
7685 if (!add_prefix (i
.seg
[0]->seg_prefix
))
7691 static INLINE
void set_rex_vrex (const reg_entry
*r
, unsigned int rex_bit
,
7692 bfd_boolean do_sse2avx
)
7694 if (r
->reg_flags
& RegRex
)
7696 if (i
.rex
& rex_bit
)
7697 as_bad (_("same type of prefix used twice"));
7700 else if (do_sse2avx
&& (i
.rex
& rex_bit
) && i
.vex
.register_specifier
)
7702 gas_assert (i
.vex
.register_specifier
== r
);
7703 i
.vex
.register_specifier
+= 8;
7706 if (r
->reg_flags
& RegVRex
)
7710 static const seg_entry
*
7711 build_modrm_byte (void)
7713 const seg_entry
*default_seg
= 0;
7714 unsigned int source
, dest
;
7717 vex_3_sources
= i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
;
7720 unsigned int nds
, reg_slot
;
7723 dest
= i
.operands
- 1;
7726 /* There are 2 kinds of instructions:
7727 1. 5 operands: 4 register operands or 3 register operands
7728 plus 1 memory operand plus one Imm4 operand, VexXDS, and
7729 VexW0 or VexW1. The destination must be either XMM, YMM or
7731 2. 4 operands: 4 register operands or 3 register operands
7732 plus 1 memory operand, with VexXDS. */
7733 gas_assert ((i
.reg_operands
== 4
7734 || (i
.reg_operands
== 3 && i
.mem_operands
== 1))
7735 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
7736 && i
.tm
.opcode_modifier
.vexw
7737 && i
.tm
.operand_types
[dest
].bitfield
.class == RegSIMD
);
7739 /* If VexW1 is set, the first non-immediate operand is the source and
7740 the second non-immediate one is encoded in the immediate operand. */
7741 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
7743 source
= i
.imm_operands
;
7744 reg_slot
= i
.imm_operands
+ 1;
7748 source
= i
.imm_operands
+ 1;
7749 reg_slot
= i
.imm_operands
;
7752 if (i
.imm_operands
== 0)
7754 /* When there is no immediate operand, generate an 8bit
7755 immediate operand to encode the first operand. */
7756 exp
= &im_expressions
[i
.imm_operands
++];
7757 i
.op
[i
.operands
].imms
= exp
;
7758 i
.types
[i
.operands
] = imm8
;
7761 gas_assert (i
.tm
.operand_types
[reg_slot
].bitfield
.class == RegSIMD
);
7762 exp
->X_op
= O_constant
;
7763 exp
->X_add_number
= register_number (i
.op
[reg_slot
].regs
) << 4;
7764 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
7768 gas_assert (i
.imm_operands
== 1);
7769 gas_assert (fits_in_imm4 (i
.op
[0].imms
->X_add_number
));
7770 gas_assert (!i
.tm
.opcode_modifier
.immext
);
7772 /* Turn on Imm8 again so that output_imm will generate it. */
7773 i
.types
[0].bitfield
.imm8
= 1;
7775 gas_assert (i
.tm
.operand_types
[reg_slot
].bitfield
.class == RegSIMD
);
7776 i
.op
[0].imms
->X_add_number
7777 |= register_number (i
.op
[reg_slot
].regs
) << 4;
7778 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
7781 gas_assert (i
.tm
.operand_types
[nds
].bitfield
.class == RegSIMD
);
7782 i
.vex
.register_specifier
= i
.op
[nds
].regs
;
7787 /* i.reg_operands MUST be the number of real register operands;
7788 implicit registers do not count. If there are 3 register
7789 operands, it must be a instruction with VexNDS. For a
7790 instruction with VexNDD, the destination register is encoded
7791 in VEX prefix. If there are 4 register operands, it must be
7792 a instruction with VEX prefix and 3 sources. */
7793 if (i
.mem_operands
== 0
7794 && ((i
.reg_operands
== 2
7795 && i
.tm
.opcode_modifier
.vexvvvv
<= VEXXDS
)
7796 || (i
.reg_operands
== 3
7797 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
7798 || (i
.reg_operands
== 4 && vex_3_sources
)))
7806 /* When there are 3 operands, one of them may be immediate,
7807 which may be the first or the last operand. Otherwise,
7808 the first operand must be shift count register (cl) or it
7809 is an instruction with VexNDS. */
7810 gas_assert (i
.imm_operands
== 1
7811 || (i
.imm_operands
== 0
7812 && (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
7813 || (i
.types
[0].bitfield
.instance
== RegC
7814 && i
.types
[0].bitfield
.byte
))));
7815 if (operand_type_check (i
.types
[0], imm
)
7816 || (i
.types
[0].bitfield
.instance
== RegC
7817 && i
.types
[0].bitfield
.byte
))
7823 /* When there are 4 operands, the first two must be 8bit
7824 immediate operands. The source operand will be the 3rd
7827 For instructions with VexNDS, if the first operand
7828 an imm8, the source operand is the 2nd one. If the last
7829 operand is imm8, the source operand is the first one. */
7830 gas_assert ((i
.imm_operands
== 2
7831 && i
.types
[0].bitfield
.imm8
7832 && i
.types
[1].bitfield
.imm8
)
7833 || (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
7834 && i
.imm_operands
== 1
7835 && (i
.types
[0].bitfield
.imm8
7836 || i
.types
[i
.operands
- 1].bitfield
.imm8
7838 if (i
.imm_operands
== 2)
7842 if (i
.types
[0].bitfield
.imm8
)
7849 if (is_evex_encoding (&i
.tm
))
7851 /* For EVEX instructions, when there are 5 operands, the
7852 first one must be immediate operand. If the second one
7853 is immediate operand, the source operand is the 3th
7854 one. If the last one is immediate operand, the source
7855 operand is the 2nd one. */
7856 gas_assert (i
.imm_operands
== 2
7857 && i
.tm
.opcode_modifier
.sae
7858 && operand_type_check (i
.types
[0], imm
));
7859 if (operand_type_check (i
.types
[1], imm
))
7861 else if (operand_type_check (i
.types
[4], imm
))
7875 /* RC/SAE operand could be between DEST and SRC. That happens
7876 when one operand is GPR and the other one is XMM/YMM/ZMM
7878 if (i
.rounding
&& i
.rounding
->operand
== (int) dest
)
7881 if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
7883 /* For instructions with VexNDS, the register-only source
7884 operand must be a 32/64bit integer, XMM, YMM, ZMM, or mask
7885 register. It is encoded in VEX prefix. */
7887 i386_operand_type op
;
7890 /* Check register-only source operand when two source
7891 operands are swapped. */
7892 if (!i
.tm
.operand_types
[source
].bitfield
.baseindex
7893 && i
.tm
.operand_types
[dest
].bitfield
.baseindex
)
7901 op
= i
.tm
.operand_types
[vvvv
];
7902 if ((dest
+ 1) >= i
.operands
7903 || ((op
.bitfield
.class != Reg
7904 || (!op
.bitfield
.dword
&& !op
.bitfield
.qword
))
7905 && op
.bitfield
.class != RegSIMD
7906 && !operand_type_equal (&op
, ®mask
)))
7908 i
.vex
.register_specifier
= i
.op
[vvvv
].regs
;
7914 /* One of the register operands will be encoded in the i.rm.reg
7915 field, the other in the combined i.rm.mode and i.rm.regmem
7916 fields. If no form of this instruction supports a memory
7917 destination operand, then we assume the source operand may
7918 sometimes be a memory operand and so we need to store the
7919 destination in the i.rm.reg field. */
7920 if (!i
.tm
.opcode_modifier
.regmem
7921 && operand_type_check (i
.tm
.operand_types
[dest
], anymem
) == 0)
7923 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
7924 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
7925 if (i
.op
[dest
].regs
->reg_type
.bitfield
.class == RegMMX
7926 || i
.op
[source
].regs
->reg_type
.bitfield
.class == RegMMX
)
7927 i
.has_regmmx
= TRUE
;
7928 else if (i
.op
[dest
].regs
->reg_type
.bitfield
.class == RegSIMD
7929 || i
.op
[source
].regs
->reg_type
.bitfield
.class == RegSIMD
)
7931 if (i
.types
[dest
].bitfield
.zmmword
7932 || i
.types
[source
].bitfield
.zmmword
)
7933 i
.has_regzmm
= TRUE
;
7934 else if (i
.types
[dest
].bitfield
.ymmword
7935 || i
.types
[source
].bitfield
.ymmword
)
7936 i
.has_regymm
= TRUE
;
7938 i
.has_regxmm
= TRUE
;
7940 set_rex_vrex (i
.op
[dest
].regs
, REX_R
, i
.tm
.opcode_modifier
.sse2avx
);
7941 set_rex_vrex (i
.op
[source
].regs
, REX_B
, FALSE
);
7945 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
7946 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
7947 set_rex_vrex (i
.op
[dest
].regs
, REX_B
, i
.tm
.opcode_modifier
.sse2avx
);
7948 set_rex_vrex (i
.op
[source
].regs
, REX_R
, FALSE
);
7950 if (flag_code
!= CODE_64BIT
&& (i
.rex
& REX_R
))
7952 if (i
.types
[!i
.tm
.opcode_modifier
.regmem
].bitfield
.class != RegCR
)
7955 add_prefix (LOCK_PREFIX_OPCODE
);
7959 { /* If it's not 2 reg operands... */
7964 unsigned int fake_zero_displacement
= 0;
7967 for (op
= 0; op
< i
.operands
; op
++)
7968 if (i
.flags
[op
] & Operand_Mem
)
7970 gas_assert (op
< i
.operands
);
7972 if (i
.tm
.opcode_modifier
.vecsib
)
7974 if (i
.index_reg
->reg_num
== RegIZ
)
7977 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
7980 i
.sib
.base
= NO_BASE_REGISTER
;
7981 i
.sib
.scale
= i
.log2_scale_factor
;
7982 i
.types
[op
].bitfield
.disp8
= 0;
7983 i
.types
[op
].bitfield
.disp16
= 0;
7984 i
.types
[op
].bitfield
.disp64
= 0;
7985 if (flag_code
!= CODE_64BIT
|| i
.prefix
[ADDR_PREFIX
])
7987 /* Must be 32 bit */
7988 i
.types
[op
].bitfield
.disp32
= 1;
7989 i
.types
[op
].bitfield
.disp32s
= 0;
7993 i
.types
[op
].bitfield
.disp32
= 0;
7994 i
.types
[op
].bitfield
.disp32s
= 1;
7997 i
.sib
.index
= i
.index_reg
->reg_num
;
7998 set_rex_vrex (i
.index_reg
, REX_X
, FALSE
);
8003 if (i
.base_reg
== 0)
8006 if (!i
.disp_operands
)
8007 fake_zero_displacement
= 1;
8008 if (i
.index_reg
== 0)
8010 i386_operand_type newdisp
;
8012 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
8013 /* Operand is just <disp> */
8014 if (flag_code
== CODE_64BIT
)
8016 /* 64bit mode overwrites the 32bit absolute
8017 addressing by RIP relative addressing and
8018 absolute addressing is encoded by one of the
8019 redundant SIB forms. */
8020 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
8021 i
.sib
.base
= NO_BASE_REGISTER
;
8022 i
.sib
.index
= NO_INDEX_REGISTER
;
8023 newdisp
= (!i
.prefix
[ADDR_PREFIX
] ? disp32s
: disp32
);
8025 else if ((flag_code
== CODE_16BIT
)
8026 ^ (i
.prefix
[ADDR_PREFIX
] != 0))
8028 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
8033 i
.rm
.regmem
= NO_BASE_REGISTER
;
8036 i
.types
[op
] = operand_type_and_not (i
.types
[op
], anydisp
);
8037 i
.types
[op
] = operand_type_or (i
.types
[op
], newdisp
);
8039 else if (!i
.tm
.opcode_modifier
.vecsib
)
8041 /* !i.base_reg && i.index_reg */
8042 if (i
.index_reg
->reg_num
== RegIZ
)
8043 i
.sib
.index
= NO_INDEX_REGISTER
;
8045 i
.sib
.index
= i
.index_reg
->reg_num
;
8046 i
.sib
.base
= NO_BASE_REGISTER
;
8047 i
.sib
.scale
= i
.log2_scale_factor
;
8048 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
8049 i
.types
[op
].bitfield
.disp8
= 0;
8050 i
.types
[op
].bitfield
.disp16
= 0;
8051 i
.types
[op
].bitfield
.disp64
= 0;
8052 if (flag_code
!= CODE_64BIT
|| i
.prefix
[ADDR_PREFIX
])
8054 /* Must be 32 bit */
8055 i
.types
[op
].bitfield
.disp32
= 1;
8056 i
.types
[op
].bitfield
.disp32s
= 0;
8060 i
.types
[op
].bitfield
.disp32
= 0;
8061 i
.types
[op
].bitfield
.disp32s
= 1;
8063 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
8067 /* RIP addressing for 64bit mode. */
8068 else if (i
.base_reg
->reg_num
== RegIP
)
8070 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
8071 i
.rm
.regmem
= NO_BASE_REGISTER
;
8072 i
.types
[op
].bitfield
.disp8
= 0;
8073 i
.types
[op
].bitfield
.disp16
= 0;
8074 i
.types
[op
].bitfield
.disp32
= 0;
8075 i
.types
[op
].bitfield
.disp32s
= 1;
8076 i
.types
[op
].bitfield
.disp64
= 0;
8077 i
.flags
[op
] |= Operand_PCrel
;
8078 if (! i
.disp_operands
)
8079 fake_zero_displacement
= 1;
8081 else if (i
.base_reg
->reg_type
.bitfield
.word
)
8083 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
8084 switch (i
.base_reg
->reg_num
)
8087 if (i
.index_reg
== 0)
8089 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
8090 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
8094 if (i
.index_reg
== 0)
8097 if (operand_type_check (i
.types
[op
], disp
) == 0)
8099 /* fake (%bp) into 0(%bp) */
8100 i
.types
[op
].bitfield
.disp8
= 1;
8101 fake_zero_displacement
= 1;
8104 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
8105 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
8107 default: /* (%si) -> 4 or (%di) -> 5 */
8108 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
8110 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
8112 else /* i.base_reg and 32/64 bit mode */
8114 if (flag_code
== CODE_64BIT
8115 && operand_type_check (i
.types
[op
], disp
))
8117 i
.types
[op
].bitfield
.disp16
= 0;
8118 i
.types
[op
].bitfield
.disp64
= 0;
8119 if (i
.prefix
[ADDR_PREFIX
] == 0)
8121 i
.types
[op
].bitfield
.disp32
= 0;
8122 i
.types
[op
].bitfield
.disp32s
= 1;
8126 i
.types
[op
].bitfield
.disp32
= 1;
8127 i
.types
[op
].bitfield
.disp32s
= 0;
8131 if (!i
.tm
.opcode_modifier
.vecsib
)
8132 i
.rm
.regmem
= i
.base_reg
->reg_num
;
8133 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
8135 i
.sib
.base
= i
.base_reg
->reg_num
;
8136 /* x86-64 ignores REX prefix bit here to avoid decoder
8138 if (!(i
.base_reg
->reg_flags
& RegRex
)
8139 && (i
.base_reg
->reg_num
== EBP_REG_NUM
8140 || i
.base_reg
->reg_num
== ESP_REG_NUM
))
8142 if (i
.base_reg
->reg_num
== 5 && i
.disp_operands
== 0)
8144 fake_zero_displacement
= 1;
8145 i
.types
[op
].bitfield
.disp8
= 1;
8147 i
.sib
.scale
= i
.log2_scale_factor
;
8148 if (i
.index_reg
== 0)
8150 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
8151 /* <disp>(%esp) becomes two byte modrm with no index
8152 register. We've already stored the code for esp
8153 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
8154 Any base register besides %esp will not use the
8155 extra modrm byte. */
8156 i
.sib
.index
= NO_INDEX_REGISTER
;
8158 else if (!i
.tm
.opcode_modifier
.vecsib
)
8160 if (i
.index_reg
->reg_num
== RegIZ
)
8161 i
.sib
.index
= NO_INDEX_REGISTER
;
8163 i
.sib
.index
= i
.index_reg
->reg_num
;
8164 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
8165 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
8170 && (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
8171 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
))
8175 if (!fake_zero_displacement
8179 fake_zero_displacement
= 1;
8180 if (i
.disp_encoding
== disp_encoding_8bit
)
8181 i
.types
[op
].bitfield
.disp8
= 1;
8183 i
.types
[op
].bitfield
.disp32
= 1;
8185 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
8189 if (fake_zero_displacement
)
8191 /* Fakes a zero displacement assuming that i.types[op]
8192 holds the correct displacement size. */
8195 gas_assert (i
.op
[op
].disps
== 0);
8196 exp
= &disp_expressions
[i
.disp_operands
++];
8197 i
.op
[op
].disps
= exp
;
8198 exp
->X_op
= O_constant
;
8199 exp
->X_add_number
= 0;
8200 exp
->X_add_symbol
= (symbolS
*) 0;
8201 exp
->X_op_symbol
= (symbolS
*) 0;
8209 if (i
.tm
.opcode_modifier
.vexsources
== XOP2SOURCES
)
8211 if (operand_type_check (i
.types
[0], imm
))
8212 i
.vex
.register_specifier
= NULL
;
8215 /* VEX.vvvv encodes one of the sources when the first
8216 operand is not an immediate. */
8217 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
8218 i
.vex
.register_specifier
= i
.op
[0].regs
;
8220 i
.vex
.register_specifier
= i
.op
[1].regs
;
8223 /* Destination is a XMM register encoded in the ModRM.reg
8225 i
.rm
.reg
= i
.op
[2].regs
->reg_num
;
8226 if ((i
.op
[2].regs
->reg_flags
& RegRex
) != 0)
8229 /* ModRM.rm and VEX.B encodes the other source. */
8230 if (!i
.mem_operands
)
8234 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
8235 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
8237 i
.rm
.regmem
= i
.op
[0].regs
->reg_num
;
8239 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
8243 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXLWP
)
8245 i
.vex
.register_specifier
= i
.op
[2].regs
;
8246 if (!i
.mem_operands
)
8249 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
8250 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
8254 /* Fill in i.rm.reg or i.rm.regmem field with register operand
8255 (if any) based on i.tm.extension_opcode. Again, we must be
8256 careful to make sure that segment/control/debug/test/MMX
8257 registers are coded into the i.rm.reg field. */
8258 else if (i
.reg_operands
)
8261 unsigned int vex_reg
= ~0;
8263 for (op
= 0; op
< i
.operands
; op
++)
8265 if (i
.types
[op
].bitfield
.class == Reg
8266 || i
.types
[op
].bitfield
.class == RegBND
8267 || i
.types
[op
].bitfield
.class == RegMask
8268 || i
.types
[op
].bitfield
.class == SReg
8269 || i
.types
[op
].bitfield
.class == RegCR
8270 || i
.types
[op
].bitfield
.class == RegDR
8271 || i
.types
[op
].bitfield
.class == RegTR
)
8273 if (i
.types
[op
].bitfield
.class == RegSIMD
)
8275 if (i
.types
[op
].bitfield
.zmmword
)
8276 i
.has_regzmm
= TRUE
;
8277 else if (i
.types
[op
].bitfield
.ymmword
)
8278 i
.has_regymm
= TRUE
;
8280 i
.has_regxmm
= TRUE
;
8283 if (i
.types
[op
].bitfield
.class == RegMMX
)
8285 i
.has_regmmx
= TRUE
;
8292 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
8294 /* For instructions with VexNDS, the register-only
8295 source operand is encoded in VEX prefix. */
8296 gas_assert (mem
!= (unsigned int) ~0);
8301 gas_assert (op
< i
.operands
);
8305 /* Check register-only source operand when two source
8306 operands are swapped. */
8307 if (!i
.tm
.operand_types
[op
].bitfield
.baseindex
8308 && i
.tm
.operand_types
[op
+ 1].bitfield
.baseindex
)
8312 gas_assert (mem
== (vex_reg
+ 1)
8313 && op
< i
.operands
);
8318 gas_assert (vex_reg
< i
.operands
);
8322 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXNDD
)
8324 /* For instructions with VexNDD, the register destination
8325 is encoded in VEX prefix. */
8326 if (i
.mem_operands
== 0)
8328 /* There is no memory operand. */
8329 gas_assert ((op
+ 2) == i
.operands
);
8334 /* There are only 2 non-immediate operands. */
8335 gas_assert (op
< i
.imm_operands
+ 2
8336 && i
.operands
== i
.imm_operands
+ 2);
8337 vex_reg
= i
.imm_operands
+ 1;
8341 gas_assert (op
< i
.operands
);
8343 if (vex_reg
!= (unsigned int) ~0)
8345 i386_operand_type
*type
= &i
.tm
.operand_types
[vex_reg
];
8347 if ((type
->bitfield
.class != Reg
8348 || (!type
->bitfield
.dword
&& !type
->bitfield
.qword
))
8349 && type
->bitfield
.class != RegSIMD
8350 && !operand_type_equal (type
, ®mask
))
8353 i
.vex
.register_specifier
= i
.op
[vex_reg
].regs
;
8356 /* Don't set OP operand twice. */
8359 /* If there is an extension opcode to put here, the
8360 register number must be put into the regmem field. */
8361 if (i
.tm
.extension_opcode
!= None
)
8363 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
8364 set_rex_vrex (i
.op
[op
].regs
, REX_B
,
8365 i
.tm
.opcode_modifier
.sse2avx
);
8369 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
8370 set_rex_vrex (i
.op
[op
].regs
, REX_R
,
8371 i
.tm
.opcode_modifier
.sse2avx
);
8375 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
8376 must set it to 3 to indicate this is a register operand
8377 in the regmem field. */
8378 if (!i
.mem_operands
)
8382 /* Fill in i.rm.reg field with extension opcode (if any). */
8383 if (i
.tm
.extension_opcode
!= None
)
8384 i
.rm
.reg
= i
.tm
.extension_opcode
;
8390 flip_code16 (unsigned int code16
)
8392 gas_assert (i
.tm
.operands
== 1);
8394 return !(i
.prefix
[REX_PREFIX
] & REX_W
)
8395 && (code16
? i
.tm
.operand_types
[0].bitfield
.disp32
8396 || i
.tm
.operand_types
[0].bitfield
.disp32s
8397 : i
.tm
.operand_types
[0].bitfield
.disp16
)
8402 output_branch (void)
8408 relax_substateT subtype
;
8412 code16
= flag_code
== CODE_16BIT
? CODE16
: 0;
8413 size
= i
.disp_encoding
== disp_encoding_32bit
? BIG
: SMALL
;
8416 if (i
.prefix
[DATA_PREFIX
] != 0)
8420 code16
^= flip_code16(code16
);
8422 /* Pentium4 branch hints. */
8423 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
8424 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
8429 if (i
.prefix
[REX_PREFIX
] != 0)
8435 /* BND prefixed jump. */
8436 if (i
.prefix
[BND_PREFIX
] != 0)
8442 if (i
.prefixes
!= 0)
8443 as_warn (_("skipping prefixes on `%s'"), i
.tm
.name
);
8445 /* It's always a symbol; End frag & setup for relax.
8446 Make sure there is enough room in this frag for the largest
8447 instruction we may generate in md_convert_frag. This is 2
8448 bytes for the opcode and room for the prefix and largest
8450 frag_grow (prefix
+ 2 + 4);
8451 /* Prefix and 1 opcode byte go in fr_fix. */
8452 p
= frag_more (prefix
+ 1);
8453 if (i
.prefix
[DATA_PREFIX
] != 0)
8454 *p
++ = DATA_PREFIX_OPCODE
;
8455 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
8456 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
8457 *p
++ = i
.prefix
[SEG_PREFIX
];
8458 if (i
.prefix
[BND_PREFIX
] != 0)
8459 *p
++ = BND_PREFIX_OPCODE
;
8460 if (i
.prefix
[REX_PREFIX
] != 0)
8461 *p
++ = i
.prefix
[REX_PREFIX
];
8462 *p
= i
.tm
.base_opcode
;
8464 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
8465 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, size
);
8466 else if (cpu_arch_flags
.bitfield
.cpui386
)
8467 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, size
);
8469 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, size
);
8472 sym
= i
.op
[0].disps
->X_add_symbol
;
8473 off
= i
.op
[0].disps
->X_add_number
;
8475 if (i
.op
[0].disps
->X_op
!= O_constant
8476 && i
.op
[0].disps
->X_op
!= O_symbol
)
8478 /* Handle complex expressions. */
8479 sym
= make_expr_symbol (i
.op
[0].disps
);
8483 /* 1 possible extra opcode + 4 byte displacement go in var part.
8484 Pass reloc in fr_var. */
8485 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
8488 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8489 /* Return TRUE iff PLT32 relocation should be used for branching to
8493 need_plt32_p (symbolS
*s
)
8495 /* PLT32 relocation is ELF only. */
8500 /* Don't emit PLT32 relocation on Solaris: neither native linker nor
8501 krtld support it. */
8505 /* Since there is no need to prepare for PLT branch on x86-64, we
8506 can generate R_X86_64_PLT32, instead of R_X86_64_PC32, which can
8507 be used as a marker for 32-bit PC-relative branches. */
8511 /* Weak or undefined symbol need PLT32 relocation. */
8512 if (S_IS_WEAK (s
) || !S_IS_DEFINED (s
))
8515 /* Non-global symbol doesn't need PLT32 relocation. */
8516 if (! S_IS_EXTERNAL (s
))
8519 /* Other global symbols need PLT32 relocation. NB: Symbol with
8520 non-default visibilities are treated as normal global symbol
8521 so that PLT32 relocation can be used as a marker for 32-bit
8522 PC-relative branches. It is useful for linker relaxation. */
8533 bfd_reloc_code_real_type jump_reloc
= i
.reloc
[0];
8535 if (i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
)
8537 /* This is a loop or jecxz type instruction. */
8539 if (i
.prefix
[ADDR_PREFIX
] != 0)
8541 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
8544 /* Pentium4 branch hints. */
8545 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
8546 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
8548 FRAG_APPEND_1_CHAR (i
.prefix
[SEG_PREFIX
]);
8557 if (flag_code
== CODE_16BIT
)
8560 if (i
.prefix
[DATA_PREFIX
] != 0)
8562 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
8564 code16
^= flip_code16(code16
);
8572 /* BND prefixed jump. */
8573 if (i
.prefix
[BND_PREFIX
] != 0)
8575 FRAG_APPEND_1_CHAR (i
.prefix
[BND_PREFIX
]);
8579 if (i
.prefix
[REX_PREFIX
] != 0)
8581 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
8585 if (i
.prefixes
!= 0)
8586 as_warn (_("skipping prefixes on `%s'"), i
.tm
.name
);
8588 p
= frag_more (i
.tm
.opcode_length
+ size
);
8589 switch (i
.tm
.opcode_length
)
8592 *p
++ = i
.tm
.base_opcode
>> 8;
8595 *p
++ = i
.tm
.base_opcode
;
8601 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8603 && jump_reloc
== NO_RELOC
8604 && need_plt32_p (i
.op
[0].disps
->X_add_symbol
))
8605 jump_reloc
= BFD_RELOC_X86_64_PLT32
;
8608 jump_reloc
= reloc (size
, 1, 1, jump_reloc
);
8610 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
8611 i
.op
[0].disps
, 1, jump_reloc
);
8613 /* All jumps handled here are signed, but don't use a signed limit
8614 check for 32 and 16 bit jumps as we want to allow wrap around at
8615 4G and 64k respectively. */
8617 fixP
->fx_signed
= 1;
8621 output_interseg_jump (void)
8629 if (flag_code
== CODE_16BIT
)
8633 if (i
.prefix
[DATA_PREFIX
] != 0)
8640 gas_assert (!i
.prefix
[REX_PREFIX
]);
8646 if (i
.prefixes
!= 0)
8647 as_warn (_("skipping prefixes on `%s'"), i
.tm
.name
);
8649 /* 1 opcode; 2 segment; offset */
8650 p
= frag_more (prefix
+ 1 + 2 + size
);
8652 if (i
.prefix
[DATA_PREFIX
] != 0)
8653 *p
++ = DATA_PREFIX_OPCODE
;
8655 if (i
.prefix
[REX_PREFIX
] != 0)
8656 *p
++ = i
.prefix
[REX_PREFIX
];
8658 *p
++ = i
.tm
.base_opcode
;
8659 if (i
.op
[1].imms
->X_op
== O_constant
)
8661 offsetT n
= i
.op
[1].imms
->X_add_number
;
8664 && !fits_in_unsigned_word (n
)
8665 && !fits_in_signed_word (n
))
8667 as_bad (_("16-bit jump out of range"));
8670 md_number_to_chars (p
, n
, size
);
8673 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
8674 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
8675 if (i
.op
[0].imms
->X_op
!= O_constant
)
8676 as_bad (_("can't handle non absolute segment in `%s'"),
8678 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
8681 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8686 asection
*seg
= now_seg
;
8687 subsegT subseg
= now_subseg
;
8689 unsigned int alignment
, align_size_1
;
8690 unsigned int isa_1_descsz
, feature_2_descsz
, descsz
;
8691 unsigned int isa_1_descsz_raw
, feature_2_descsz_raw
;
8692 unsigned int padding
;
8694 if (!IS_ELF
|| !x86_used_note
)
8697 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_X86
;
8699 /* The .note.gnu.property section layout:
8701 Field Length Contents
8704 n_descsz 4 The note descriptor size
8705 n_type 4 NT_GNU_PROPERTY_TYPE_0
8707 n_desc n_descsz The program property array
8711 /* Create the .note.gnu.property section. */
8712 sec
= subseg_new (NOTE_GNU_PROPERTY_SECTION_NAME
, 0);
8713 bfd_set_section_flags (sec
,
8720 if (get_elf_backend_data (stdoutput
)->s
->elfclass
== ELFCLASS64
)
8731 bfd_set_section_alignment (sec
, alignment
);
8732 elf_section_type (sec
) = SHT_NOTE
;
8734 /* GNU_PROPERTY_X86_ISA_1_USED: 4-byte type + 4-byte data size
8736 isa_1_descsz_raw
= 4 + 4 + 4;
8737 /* Align GNU_PROPERTY_X86_ISA_1_USED. */
8738 isa_1_descsz
= (isa_1_descsz_raw
+ align_size_1
) & ~align_size_1
;
8740 feature_2_descsz_raw
= isa_1_descsz
;
8741 /* GNU_PROPERTY_X86_FEATURE_2_USED: 4-byte type + 4-byte data size
8743 feature_2_descsz_raw
+= 4 + 4 + 4;
8744 /* Align GNU_PROPERTY_X86_FEATURE_2_USED. */
8745 feature_2_descsz
= ((feature_2_descsz_raw
+ align_size_1
)
8748 descsz
= feature_2_descsz
;
8749 /* Section size: n_namsz + n_descsz + n_type + n_name + n_descsz. */
8750 p
= frag_more (4 + 4 + 4 + 4 + descsz
);
8752 /* Write n_namsz. */
8753 md_number_to_chars (p
, (valueT
) 4, 4);
8755 /* Write n_descsz. */
8756 md_number_to_chars (p
+ 4, (valueT
) descsz
, 4);
8759 md_number_to_chars (p
+ 4 * 2, (valueT
) NT_GNU_PROPERTY_TYPE_0
, 4);
8762 memcpy (p
+ 4 * 3, "GNU", 4);
8764 /* Write 4-byte type. */
8765 md_number_to_chars (p
+ 4 * 4,
8766 (valueT
) GNU_PROPERTY_X86_ISA_1_USED
, 4);
8768 /* Write 4-byte data size. */
8769 md_number_to_chars (p
+ 4 * 5, (valueT
) 4, 4);
8771 /* Write 4-byte data. */
8772 md_number_to_chars (p
+ 4 * 6, (valueT
) x86_isa_1_used
, 4);
8774 /* Zero out paddings. */
8775 padding
= isa_1_descsz
- isa_1_descsz_raw
;
8777 memset (p
+ 4 * 7, 0, padding
);
8779 /* Write 4-byte type. */
8780 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 4,
8781 (valueT
) GNU_PROPERTY_X86_FEATURE_2_USED
, 4);
8783 /* Write 4-byte data size. */
8784 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 5, (valueT
) 4, 4);
8786 /* Write 4-byte data. */
8787 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 6,
8788 (valueT
) x86_feature_2_used
, 4);
8790 /* Zero out paddings. */
8791 padding
= feature_2_descsz
- feature_2_descsz_raw
;
8793 memset (p
+ isa_1_descsz
+ 4 * 7, 0, padding
);
8795 /* We probably can't restore the current segment, for there likely
8798 subseg_set (seg
, subseg
);
8803 encoding_length (const fragS
*start_frag
, offsetT start_off
,
8804 const char *frag_now_ptr
)
8806 unsigned int len
= 0;
8808 if (start_frag
!= frag_now
)
8810 const fragS
*fr
= start_frag
;
8815 } while (fr
&& fr
!= frag_now
);
8818 return len
- start_off
+ (frag_now_ptr
- frag_now
->fr_literal
);
8821 /* Return 1 for test, and, cmp, add, sub, inc and dec which may
8822 be macro-fused with conditional jumps.
8823 NB: If TEST/AND/CMP/ADD/SUB/INC/DEC is of RIP relative address,
8824 or is one of the following format:
8837 maybe_fused_with_jcc_p (enum mf_cmp_kind
* mf_cmp_p
)
8839 /* No RIP address. */
8840 if (i
.base_reg
&& i
.base_reg
->reg_num
== RegIP
)
8843 /* No VEX/EVEX encoding. */
8844 if (is_any_vex_encoding (&i
.tm
))
8847 /* add, sub without add/sub m, imm. */
8848 if (i
.tm
.base_opcode
<= 5
8849 || (i
.tm
.base_opcode
>= 0x28 && i
.tm
.base_opcode
<= 0x2d)
8850 || ((i
.tm
.base_opcode
| 3) == 0x83
8851 && (i
.tm
.extension_opcode
== 0x5
8852 || i
.tm
.extension_opcode
== 0x0)))
8854 *mf_cmp_p
= mf_cmp_alu_cmp
;
8855 return !(i
.mem_operands
&& i
.imm_operands
);
8858 /* and without and m, imm. */
8859 if ((i
.tm
.base_opcode
>= 0x20 && i
.tm
.base_opcode
<= 0x25)
8860 || ((i
.tm
.base_opcode
| 3) == 0x83
8861 && i
.tm
.extension_opcode
== 0x4))
8863 *mf_cmp_p
= mf_cmp_test_and
;
8864 return !(i
.mem_operands
&& i
.imm_operands
);
8867 /* test without test m imm. */
8868 if ((i
.tm
.base_opcode
| 1) == 0x85
8869 || (i
.tm
.base_opcode
| 1) == 0xa9
8870 || ((i
.tm
.base_opcode
| 1) == 0xf7
8871 && i
.tm
.extension_opcode
== 0))
8873 *mf_cmp_p
= mf_cmp_test_and
;
8874 return !(i
.mem_operands
&& i
.imm_operands
);
8877 /* cmp without cmp m, imm. */
8878 if ((i
.tm
.base_opcode
>= 0x38 && i
.tm
.base_opcode
<= 0x3d)
8879 || ((i
.tm
.base_opcode
| 3) == 0x83
8880 && (i
.tm
.extension_opcode
== 0x7)))
8882 *mf_cmp_p
= mf_cmp_alu_cmp
;
8883 return !(i
.mem_operands
&& i
.imm_operands
);
8886 /* inc, dec without inc/dec m. */
8887 if ((i
.tm
.cpu_flags
.bitfield
.cpuno64
8888 && (i
.tm
.base_opcode
| 0xf) == 0x4f)
8889 || ((i
.tm
.base_opcode
| 1) == 0xff
8890 && i
.tm
.extension_opcode
<= 0x1))
8892 *mf_cmp_p
= mf_cmp_incdec
;
8893 return !i
.mem_operands
;
8899 /* Return 1 if a FUSED_JCC_PADDING frag should be generated. */
8902 add_fused_jcc_padding_frag_p (enum mf_cmp_kind
* mf_cmp_p
)
8904 /* NB: Don't work with COND_JUMP86 without i386. */
8905 if (!align_branch_power
8906 || now_seg
== absolute_section
8907 || !cpu_arch_flags
.bitfield
.cpui386
8908 || !(align_branch
& align_branch_fused_bit
))
8911 if (maybe_fused_with_jcc_p (mf_cmp_p
))
8913 if (last_insn
.kind
== last_insn_other
8914 || last_insn
.seg
!= now_seg
)
8917 as_warn_where (last_insn
.file
, last_insn
.line
,
8918 _("`%s` skips -malign-branch-boundary on `%s`"),
8919 last_insn
.name
, i
.tm
.name
);
8925 /* Return 1 if a BRANCH_PREFIX frag should be generated. */
8928 add_branch_prefix_frag_p (void)
8930 /* NB: Don't work with COND_JUMP86 without i386. Don't add prefix
8931 to PadLock instructions since they include prefixes in opcode. */
8932 if (!align_branch_power
8933 || !align_branch_prefix_size
8934 || now_seg
== absolute_section
8935 || i
.tm
.cpu_flags
.bitfield
.cpupadlock
8936 || !cpu_arch_flags
.bitfield
.cpui386
)
8939 /* Don't add prefix if it is a prefix or there is no operand in case
8940 that segment prefix is special. */
8941 if (!i
.operands
|| i
.tm
.opcode_modifier
.isprefix
)
8944 if (last_insn
.kind
== last_insn_other
8945 || last_insn
.seg
!= now_seg
)
8949 as_warn_where (last_insn
.file
, last_insn
.line
,
8950 _("`%s` skips -malign-branch-boundary on `%s`"),
8951 last_insn
.name
, i
.tm
.name
);
8956 /* Return 1 if a BRANCH_PADDING frag should be generated. */
8959 add_branch_padding_frag_p (enum align_branch_kind
*branch_p
,
8960 enum mf_jcc_kind
*mf_jcc_p
)
8964 /* NB: Don't work with COND_JUMP86 without i386. */
8965 if (!align_branch_power
8966 || now_seg
== absolute_section
8967 || !cpu_arch_flags
.bitfield
.cpui386
)
8972 /* Check for jcc and direct jmp. */
8973 if (i
.tm
.opcode_modifier
.jump
== JUMP
)
8975 if (i
.tm
.base_opcode
== JUMP_PC_RELATIVE
)
8977 *branch_p
= align_branch_jmp
;
8978 add_padding
= align_branch
& align_branch_jmp_bit
;
8982 /* Because J<cc> and JN<cc> share same group in macro-fusible table,
8983 igore the lowest bit. */
8984 *mf_jcc_p
= (i
.tm
.base_opcode
& 0x0e) >> 1;
8985 *branch_p
= align_branch_jcc
;
8986 if ((align_branch
& align_branch_jcc_bit
))
8990 else if (is_any_vex_encoding (&i
.tm
))
8992 else if ((i
.tm
.base_opcode
| 1) == 0xc3)
8995 *branch_p
= align_branch_ret
;
8996 if ((align_branch
& align_branch_ret_bit
))
9001 /* Check for indirect jmp, direct and indirect calls. */
9002 if (i
.tm
.base_opcode
== 0xe8)
9005 *branch_p
= align_branch_call
;
9006 if ((align_branch
& align_branch_call_bit
))
9009 else if (i
.tm
.base_opcode
== 0xff
9010 && (i
.tm
.extension_opcode
== 2
9011 || i
.tm
.extension_opcode
== 4))
9013 /* Indirect call and jmp. */
9014 *branch_p
= align_branch_indirect
;
9015 if ((align_branch
& align_branch_indirect_bit
))
9022 && (i
.op
[0].disps
->X_op
== O_symbol
9023 || (i
.op
[0].disps
->X_op
== O_subtract
9024 && i
.op
[0].disps
->X_op_symbol
== GOT_symbol
)))
9026 symbolS
*s
= i
.op
[0].disps
->X_add_symbol
;
9027 /* No padding to call to global or undefined tls_get_addr. */
9028 if ((S_IS_EXTERNAL (s
) || !S_IS_DEFINED (s
))
9029 && strcmp (S_GET_NAME (s
), tls_get_addr
) == 0)
9035 && last_insn
.kind
!= last_insn_other
9036 && last_insn
.seg
== now_seg
)
9039 as_warn_where (last_insn
.file
, last_insn
.line
,
9040 _("`%s` skips -malign-branch-boundary on `%s`"),
9041 last_insn
.name
, i
.tm
.name
);
9051 fragS
*insn_start_frag
;
9052 offsetT insn_start_off
;
9053 fragS
*fragP
= NULL
;
9054 enum align_branch_kind branch
= align_branch_none
;
9055 /* The initializer is arbitrary just to avoid uninitialized error.
9056 it's actually either assigned in add_branch_padding_frag_p
9057 or never be used. */
9058 enum mf_jcc_kind mf_jcc
= mf_jcc_jo
;
9060 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9061 if (IS_ELF
&& x86_used_note
)
9063 if (i
.tm
.cpu_flags
.bitfield
.cpucmov
)
9064 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_CMOV
;
9065 if (i
.tm
.cpu_flags
.bitfield
.cpusse
)
9066 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE
;
9067 if (i
.tm
.cpu_flags
.bitfield
.cpusse2
)
9068 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE2
;
9069 if (i
.tm
.cpu_flags
.bitfield
.cpusse3
)
9070 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE3
;
9071 if (i
.tm
.cpu_flags
.bitfield
.cpussse3
)
9072 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSSE3
;
9073 if (i
.tm
.cpu_flags
.bitfield
.cpusse4_1
)
9074 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE4_1
;
9075 if (i
.tm
.cpu_flags
.bitfield
.cpusse4_2
)
9076 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE4_2
;
9077 if (i
.tm
.cpu_flags
.bitfield
.cpuavx
)
9078 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX
;
9079 if (i
.tm
.cpu_flags
.bitfield
.cpuavx2
)
9080 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX2
;
9081 if (i
.tm
.cpu_flags
.bitfield
.cpufma
)
9082 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_FMA
;
9083 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512f
)
9084 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512F
;
9085 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512cd
)
9086 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512CD
;
9087 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512er
)
9088 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512ER
;
9089 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512pf
)
9090 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512PF
;
9091 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512vl
)
9092 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512VL
;
9093 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512dq
)
9094 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512DQ
;
9095 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512bw
)
9096 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512BW
;
9097 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_4fmaps
)
9098 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_4FMAPS
;
9099 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_4vnniw
)
9100 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_4VNNIW
;
9101 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_bitalg
)
9102 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_BITALG
;
9103 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512ifma
)
9104 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_IFMA
;
9105 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512vbmi
)
9106 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_VBMI
;
9107 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_vbmi2
)
9108 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_VBMI2
;
9109 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_vnni
)
9110 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_VNNI
;
9111 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_bf16
)
9112 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_BF16
;
9114 if (i
.tm
.cpu_flags
.bitfield
.cpu8087
9115 || i
.tm
.cpu_flags
.bitfield
.cpu287
9116 || i
.tm
.cpu_flags
.bitfield
.cpu387
9117 || i
.tm
.cpu_flags
.bitfield
.cpu687
9118 || i
.tm
.cpu_flags
.bitfield
.cpufisttp
)
9119 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_X87
;
9121 || i
.tm
.base_opcode
== 0xf77 /* emms */
9122 || i
.tm
.base_opcode
== 0xf0e /* femms */
9123 || i
.tm
.base_opcode
== 0xf2a /* cvtpi2ps */
9124 || i
.tm
.base_opcode
== 0x660f2a /* cvtpi2pd */)
9125 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_MMX
;
9127 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XMM
;
9129 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_YMM
;
9131 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_ZMM
;
9132 if (i
.tm
.cpu_flags
.bitfield
.cpufxsr
)
9133 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_FXSR
;
9134 if (i
.tm
.cpu_flags
.bitfield
.cpuxsave
)
9135 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVE
;
9136 if (i
.tm
.cpu_flags
.bitfield
.cpuxsaveopt
)
9137 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVEOPT
;
9138 if (i
.tm
.cpu_flags
.bitfield
.cpuxsavec
)
9139 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVEC
;
9143 /* Tie dwarf2 debug info to the address at the start of the insn.
9144 We can't do this after the insn has been output as the current
9145 frag may have been closed off. eg. by frag_var. */
9146 dwarf2_emit_insn (0);
9148 insn_start_frag
= frag_now
;
9149 insn_start_off
= frag_now_fix ();
9151 if (add_branch_padding_frag_p (&branch
, &mf_jcc
))
9154 /* Branch can be 8 bytes. Leave some room for prefixes. */
9155 unsigned int max_branch_padding_size
= 14;
9157 /* Align section to boundary. */
9158 record_alignment (now_seg
, align_branch_power
);
9160 /* Make room for padding. */
9161 frag_grow (max_branch_padding_size
);
9163 /* Start of the padding. */
9168 frag_var (rs_machine_dependent
, max_branch_padding_size
, 0,
9169 ENCODE_RELAX_STATE (BRANCH_PADDING
, 0),
9172 fragP
->tc_frag_data
.mf_type
= mf_jcc
;
9173 fragP
->tc_frag_data
.branch_type
= branch
;
9174 fragP
->tc_frag_data
.max_bytes
= max_branch_padding_size
;
9178 if (i
.tm
.opcode_modifier
.jump
== JUMP
)
9180 else if (i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
9181 || i
.tm
.opcode_modifier
.jump
== JUMP_DWORD
)
9183 else if (i
.tm
.opcode_modifier
.jump
== JUMP_INTERSEGMENT
)
9184 output_interseg_jump ();
9187 /* Output normal instructions here. */
9191 unsigned int prefix
;
9192 enum mf_cmp_kind mf_cmp
;
9195 && (i
.tm
.base_opcode
== 0xfaee8
9196 || i
.tm
.base_opcode
== 0xfaef0
9197 || i
.tm
.base_opcode
== 0xfaef8))
9199 /* Encode lfence, mfence, and sfence as
9200 f0 83 04 24 00 lock addl $0x0, (%{re}sp). */
9201 offsetT val
= 0x240483f0ULL
;
9203 md_number_to_chars (p
, val
, 5);
9207 /* Some processors fail on LOCK prefix. This options makes
9208 assembler ignore LOCK prefix and serves as a workaround. */
9209 if (omit_lock_prefix
)
9211 if (i
.tm
.base_opcode
== LOCK_PREFIX_OPCODE
)
9213 i
.prefix
[LOCK_PREFIX
] = 0;
9217 /* Skip if this is a branch. */
9219 else if (add_fused_jcc_padding_frag_p (&mf_cmp
))
9221 /* Make room for padding. */
9222 frag_grow (MAX_FUSED_JCC_PADDING_SIZE
);
9227 frag_var (rs_machine_dependent
, MAX_FUSED_JCC_PADDING_SIZE
, 0,
9228 ENCODE_RELAX_STATE (FUSED_JCC_PADDING
, 0),
9231 fragP
->tc_frag_data
.mf_type
= mf_cmp
;
9232 fragP
->tc_frag_data
.branch_type
= align_branch_fused
;
9233 fragP
->tc_frag_data
.max_bytes
= MAX_FUSED_JCC_PADDING_SIZE
;
9235 else if (add_branch_prefix_frag_p ())
9237 unsigned int max_prefix_size
= align_branch_prefix_size
;
9239 /* Make room for padding. */
9240 frag_grow (max_prefix_size
);
9245 frag_var (rs_machine_dependent
, max_prefix_size
, 0,
9246 ENCODE_RELAX_STATE (BRANCH_PREFIX
, 0),
9249 fragP
->tc_frag_data
.max_bytes
= max_prefix_size
;
9252 /* Since the VEX/EVEX prefix contains the implicit prefix, we
9253 don't need the explicit prefix. */
9254 if (!i
.tm
.opcode_modifier
.vex
&& !i
.tm
.opcode_modifier
.evex
)
9256 switch (i
.tm
.opcode_length
)
9259 if (i
.tm
.base_opcode
& 0xff000000)
9261 prefix
= (i
.tm
.base_opcode
>> 24) & 0xff;
9262 if (!i
.tm
.cpu_flags
.bitfield
.cpupadlock
9263 || prefix
!= REPE_PREFIX_OPCODE
9264 || (i
.prefix
[REP_PREFIX
] != REPE_PREFIX_OPCODE
))
9265 add_prefix (prefix
);
9269 if ((i
.tm
.base_opcode
& 0xff0000) != 0)
9271 prefix
= (i
.tm
.base_opcode
>> 16) & 0xff;
9272 add_prefix (prefix
);
9278 /* Check for pseudo prefixes. */
9279 as_bad_where (insn_start_frag
->fr_file
,
9280 insn_start_frag
->fr_line
,
9281 _("pseudo prefix without instruction"));
9287 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
9288 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
9289 R_X86_64_GOTTPOFF relocation so that linker can safely
9290 perform IE->LE optimization. A dummy REX_OPCODE prefix
9291 is also needed for lea with R_X86_64_GOTPC32_TLSDESC
9292 relocation for GDesc -> IE/LE optimization. */
9293 if (x86_elf_abi
== X86_64_X32_ABI
9295 && (i
.reloc
[0] == BFD_RELOC_X86_64_GOTTPOFF
9296 || i
.reloc
[0] == BFD_RELOC_X86_64_GOTPC32_TLSDESC
)
9297 && i
.prefix
[REX_PREFIX
] == 0)
9298 add_prefix (REX_OPCODE
);
9301 /* The prefix bytes. */
9302 for (j
= ARRAY_SIZE (i
.prefix
), q
= i
.prefix
; j
> 0; j
--, q
++)
9304 FRAG_APPEND_1_CHAR (*q
);
9308 for (j
= 0, q
= i
.prefix
; j
< ARRAY_SIZE (i
.prefix
); j
++, q
++)
9314 FRAG_APPEND_1_CHAR (*q
);
9317 /* There should be no other prefixes for instructions
9322 /* For EVEX instructions i.vrex should become 0 after
9323 build_evex_prefix. For VEX instructions upper 16 registers
9324 aren't available, so VREX should be 0. */
9327 /* Now the VEX prefix. */
9328 p
= frag_more (i
.vex
.length
);
9329 for (j
= 0; j
< i
.vex
.length
; j
++)
9330 p
[j
] = i
.vex
.bytes
[j
];
9333 /* Now the opcode; be careful about word order here! */
9334 if (i
.tm
.opcode_length
== 1)
9336 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
9340 switch (i
.tm
.opcode_length
)
9344 *p
++ = (i
.tm
.base_opcode
>> 24) & 0xff;
9345 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
9349 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
9359 /* Put out high byte first: can't use md_number_to_chars! */
9360 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
9361 *p
= i
.tm
.base_opcode
& 0xff;
9364 /* Now the modrm byte and sib byte (if present). */
9365 if (i
.tm
.opcode_modifier
.modrm
)
9367 FRAG_APPEND_1_CHAR ((i
.rm
.regmem
<< 0
9370 /* If i.rm.regmem == ESP (4)
9371 && i.rm.mode != (Register mode)
9373 ==> need second modrm byte. */
9374 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
9376 && !(i
.base_reg
&& i
.base_reg
->reg_type
.bitfield
.word
))
9377 FRAG_APPEND_1_CHAR ((i
.sib
.base
<< 0
9379 | i
.sib
.scale
<< 6));
9382 if (i
.disp_operands
)
9383 output_disp (insn_start_frag
, insn_start_off
);
9386 output_imm (insn_start_frag
, insn_start_off
);
9389 * frag_now_fix () returning plain abs_section_offset when we're in the
9390 * absolute section, and abs_section_offset not getting updated as data
9391 * gets added to the frag breaks the logic below.
9393 if (now_seg
!= absolute_section
)
9395 j
= encoding_length (insn_start_frag
, insn_start_off
, frag_more (0));
9397 as_warn (_("instruction length of %u bytes exceeds the limit of 15"),
9401 /* NB: Don't add prefix with GOTPC relocation since
9402 output_disp() above depends on the fixed encoding
9403 length. Can't add prefix with TLS relocation since
9404 it breaks TLS linker optimization. */
9405 unsigned int max
= i
.has_gotpc_tls_reloc
? 0 : 15 - j
;
9406 /* Prefix count on the current instruction. */
9407 unsigned int count
= i
.vex
.length
;
9409 for (k
= 0; k
< ARRAY_SIZE (i
.prefix
); k
++)
9410 /* REX byte is encoded in VEX/EVEX prefix. */
9411 if (i
.prefix
[k
] && (k
!= REX_PREFIX
|| !i
.vex
.length
))
9414 /* Count prefixes for extended opcode maps. */
9416 switch (i
.tm
.opcode_length
)
9419 if (((i
.tm
.base_opcode
>> 16) & 0xff) == 0xf)
9422 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
9434 if (((i
.tm
.base_opcode
>> 8) & 0xff) == 0xf)
9443 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
)
9446 /* Set the maximum prefix size in BRANCH_PREFIX
9448 if (fragP
->tc_frag_data
.max_bytes
> max
)
9449 fragP
->tc_frag_data
.max_bytes
= max
;
9450 if (fragP
->tc_frag_data
.max_bytes
> count
)
9451 fragP
->tc_frag_data
.max_bytes
-= count
;
9453 fragP
->tc_frag_data
.max_bytes
= 0;
9457 /* Remember the maximum prefix size in FUSED_JCC_PADDING
9459 unsigned int max_prefix_size
;
9460 if (align_branch_prefix_size
> max
)
9461 max_prefix_size
= max
;
9463 max_prefix_size
= align_branch_prefix_size
;
9464 if (max_prefix_size
> count
)
9465 fragP
->tc_frag_data
.max_prefix_length
9466 = max_prefix_size
- count
;
9469 /* Use existing segment prefix if possible. Use CS
9470 segment prefix in 64-bit mode. In 32-bit mode, use SS
9471 segment prefix with ESP/EBP base register and use DS
9472 segment prefix without ESP/EBP base register. */
9473 if (i
.prefix
[SEG_PREFIX
])
9474 fragP
->tc_frag_data
.default_prefix
= i
.prefix
[SEG_PREFIX
];
9475 else if (flag_code
== CODE_64BIT
)
9476 fragP
->tc_frag_data
.default_prefix
= CS_PREFIX_OPCODE
;
9478 && (i
.base_reg
->reg_num
== 4
9479 || i
.base_reg
->reg_num
== 5))
9480 fragP
->tc_frag_data
.default_prefix
= SS_PREFIX_OPCODE
;
9482 fragP
->tc_frag_data
.default_prefix
= DS_PREFIX_OPCODE
;
9487 /* NB: Don't work with COND_JUMP86 without i386. */
9488 if (align_branch_power
9489 && now_seg
!= absolute_section
9490 && cpu_arch_flags
.bitfield
.cpui386
)
9492 /* Terminate each frag so that we can add prefix and check for
9494 frag_wane (frag_now
);
9501 pi ("" /*line*/, &i
);
9503 #endif /* DEBUG386 */
9506 /* Return the size of the displacement operand N. */
9509 disp_size (unsigned int n
)
9513 if (i
.types
[n
].bitfield
.disp64
)
9515 else if (i
.types
[n
].bitfield
.disp8
)
9517 else if (i
.types
[n
].bitfield
.disp16
)
9522 /* Return the size of the immediate operand N. */
9525 imm_size (unsigned int n
)
9528 if (i
.types
[n
].bitfield
.imm64
)
9530 else if (i
.types
[n
].bitfield
.imm8
|| i
.types
[n
].bitfield
.imm8s
)
9532 else if (i
.types
[n
].bitfield
.imm16
)
9538 output_disp (fragS
*insn_start_frag
, offsetT insn_start_off
)
9543 for (n
= 0; n
< i
.operands
; n
++)
9545 if (operand_type_check (i
.types
[n
], disp
))
9547 if (i
.op
[n
].disps
->X_op
== O_constant
)
9549 int size
= disp_size (n
);
9550 offsetT val
= i
.op
[n
].disps
->X_add_number
;
9552 val
= offset_in_range (val
>> (size
== 1 ? i
.memshift
: 0),
9554 p
= frag_more (size
);
9555 md_number_to_chars (p
, val
, size
);
9559 enum bfd_reloc_code_real reloc_type
;
9560 int size
= disp_size (n
);
9561 int sign
= i
.types
[n
].bitfield
.disp32s
;
9562 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
9565 /* We can't have 8 bit displacement here. */
9566 gas_assert (!i
.types
[n
].bitfield
.disp8
);
9568 /* The PC relative address is computed relative
9569 to the instruction boundary, so in case immediate
9570 fields follows, we need to adjust the value. */
9571 if (pcrel
&& i
.imm_operands
)
9576 for (n1
= 0; n1
< i
.operands
; n1
++)
9577 if (operand_type_check (i
.types
[n1
], imm
))
9579 /* Only one immediate is allowed for PC
9580 relative address. */
9581 gas_assert (sz
== 0);
9583 i
.op
[n
].disps
->X_add_number
-= sz
;
9585 /* We should find the immediate. */
9586 gas_assert (sz
!= 0);
9589 p
= frag_more (size
);
9590 reloc_type
= reloc (size
, pcrel
, sign
, i
.reloc
[n
]);
9592 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
9593 && (((reloc_type
== BFD_RELOC_32
9594 || reloc_type
== BFD_RELOC_X86_64_32S
9595 || (reloc_type
== BFD_RELOC_64
9597 && (i
.op
[n
].disps
->X_op
== O_symbol
9598 || (i
.op
[n
].disps
->X_op
== O_add
9599 && ((symbol_get_value_expression
9600 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
9602 || reloc_type
== BFD_RELOC_32_PCREL
))
9606 reloc_type
= BFD_RELOC_386_GOTPC
;
9607 i
.has_gotpc_tls_reloc
= TRUE
;
9608 i
.op
[n
].imms
->X_add_number
+=
9609 encoding_length (insn_start_frag
, insn_start_off
, p
);
9611 else if (reloc_type
== BFD_RELOC_64
)
9612 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
9614 /* Don't do the adjustment for x86-64, as there
9615 the pcrel addressing is relative to the _next_
9616 insn, and that is taken care of in other code. */
9617 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
9619 else if (align_branch_power
)
9623 case BFD_RELOC_386_TLS_GD
:
9624 case BFD_RELOC_386_TLS_LDM
:
9625 case BFD_RELOC_386_TLS_IE
:
9626 case BFD_RELOC_386_TLS_IE_32
:
9627 case BFD_RELOC_386_TLS_GOTIE
:
9628 case BFD_RELOC_386_TLS_GOTDESC
:
9629 case BFD_RELOC_386_TLS_DESC_CALL
:
9630 case BFD_RELOC_X86_64_TLSGD
:
9631 case BFD_RELOC_X86_64_TLSLD
:
9632 case BFD_RELOC_X86_64_GOTTPOFF
:
9633 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
9634 case BFD_RELOC_X86_64_TLSDESC_CALL
:
9635 i
.has_gotpc_tls_reloc
= TRUE
;
9640 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
9641 size
, i
.op
[n
].disps
, pcrel
,
9643 /* Check for "call/jmp *mem", "mov mem, %reg",
9644 "test %reg, mem" and "binop mem, %reg" where binop
9645 is one of adc, add, and, cmp, or, sbb, sub, xor
9646 instructions without data prefix. Always generate
9647 R_386_GOT32X for "sym*GOT" operand in 32-bit mode. */
9648 if (i
.prefix
[DATA_PREFIX
] == 0
9649 && (generate_relax_relocations
9652 && i
.rm
.regmem
== 5))
9654 || (i
.rm
.mode
== 0 && i
.rm
.regmem
== 5))
9655 && !is_any_vex_encoding(&i
.tm
)
9656 && ((i
.operands
== 1
9657 && i
.tm
.base_opcode
== 0xff
9658 && (i
.rm
.reg
== 2 || i
.rm
.reg
== 4))
9660 && (i
.tm
.base_opcode
== 0x8b
9661 || i
.tm
.base_opcode
== 0x85
9662 || (i
.tm
.base_opcode
& ~0x38) == 0x03))))
9666 fixP
->fx_tcbit
= i
.rex
!= 0;
9668 && (i
.base_reg
->reg_num
== RegIP
))
9669 fixP
->fx_tcbit2
= 1;
9672 fixP
->fx_tcbit2
= 1;
9680 output_imm (fragS
*insn_start_frag
, offsetT insn_start_off
)
9685 for (n
= 0; n
< i
.operands
; n
++)
9687 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
9688 if (i
.rounding
&& (int) n
== i
.rounding
->operand
)
9691 if (operand_type_check (i
.types
[n
], imm
))
9693 if (i
.op
[n
].imms
->X_op
== O_constant
)
9695 int size
= imm_size (n
);
9698 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
9700 p
= frag_more (size
);
9701 md_number_to_chars (p
, val
, size
);
9705 /* Not absolute_section.
9706 Need a 32-bit fixup (don't support 8bit
9707 non-absolute imms). Try to support other
9709 enum bfd_reloc_code_real reloc_type
;
9710 int size
= imm_size (n
);
9713 if (i
.types
[n
].bitfield
.imm32s
9714 && (i
.suffix
== QWORD_MNEM_SUFFIX
9715 || (!i
.suffix
&& i
.tm
.opcode_modifier
.no_lsuf
)))
9720 p
= frag_more (size
);
9721 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
9723 /* This is tough to explain. We end up with this one if we
9724 * have operands that look like
9725 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
9726 * obtain the absolute address of the GOT, and it is strongly
9727 * preferable from a performance point of view to avoid using
9728 * a runtime relocation for this. The actual sequence of
9729 * instructions often look something like:
9734 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
9736 * The call and pop essentially return the absolute address
9737 * of the label .L66 and store it in %ebx. The linker itself
9738 * will ultimately change the first operand of the addl so
9739 * that %ebx points to the GOT, but to keep things simple, the
9740 * .o file must have this operand set so that it generates not
9741 * the absolute address of .L66, but the absolute address of
9742 * itself. This allows the linker itself simply treat a GOTPC
9743 * relocation as asking for a pcrel offset to the GOT to be
9744 * added in, and the addend of the relocation is stored in the
9745 * operand field for the instruction itself.
9747 * Our job here is to fix the operand so that it would add
9748 * the correct offset so that %ebx would point to itself. The
9749 * thing that is tricky is that .-.L66 will point to the
9750 * beginning of the instruction, so we need to further modify
9751 * the operand so that it will point to itself. There are
9752 * other cases where you have something like:
9754 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
9756 * and here no correction would be required. Internally in
9757 * the assembler we treat operands of this form as not being
9758 * pcrel since the '.' is explicitly mentioned, and I wonder
9759 * whether it would simplify matters to do it this way. Who
9760 * knows. In earlier versions of the PIC patches, the
9761 * pcrel_adjust field was used to store the correction, but
9762 * since the expression is not pcrel, I felt it would be
9763 * confusing to do it this way. */
9765 if ((reloc_type
== BFD_RELOC_32
9766 || reloc_type
== BFD_RELOC_X86_64_32S
9767 || reloc_type
== BFD_RELOC_64
)
9769 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
9770 && (i
.op
[n
].imms
->X_op
== O_symbol
9771 || (i
.op
[n
].imms
->X_op
== O_add
9772 && ((symbol_get_value_expression
9773 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
9777 reloc_type
= BFD_RELOC_386_GOTPC
;
9779 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
9781 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
9782 i
.has_gotpc_tls_reloc
= TRUE
;
9783 i
.op
[n
].imms
->X_add_number
+=
9784 encoding_length (insn_start_frag
, insn_start_off
, p
);
9786 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
9787 i
.op
[n
].imms
, 0, reloc_type
);
9793 /* x86_cons_fix_new is called via the expression parsing code when a
9794 reloc is needed. We use this hook to get the correct .got reloc. */
9795 static int cons_sign
= -1;
9798 x86_cons_fix_new (fragS
*frag
, unsigned int off
, unsigned int len
,
9799 expressionS
*exp
, bfd_reloc_code_real_type r
)
9801 r
= reloc (len
, 0, cons_sign
, r
);
9804 if (exp
->X_op
== O_secrel
)
9806 exp
->X_op
= O_symbol
;
9807 r
= BFD_RELOC_32_SECREL
;
9811 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
9814 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
9815 purpose of the `.dc.a' internal pseudo-op. */
9818 x86_address_bytes (void)
9820 if ((stdoutput
->arch_info
->mach
& bfd_mach_x64_32
))
9822 return stdoutput
->arch_info
->bits_per_address
/ 8;
9825 #if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
9827 # define lex_got(reloc, adjust, types) NULL
9829 /* Parse operands of the form
9830 <symbol>@GOTOFF+<nnn>
9831 and similar .plt or .got references.
9833 If we find one, set up the correct relocation in RELOC and copy the
9834 input string, minus the `@GOTOFF' into a malloc'd buffer for
9835 parsing by the calling routine. Return this buffer, and if ADJUST
9836 is non-null set it to the length of the string we removed from the
9837 input line. Otherwise return NULL. */
9839 lex_got (enum bfd_reloc_code_real
*rel
,
9841 i386_operand_type
*types
)
9843 /* Some of the relocations depend on the size of what field is to
9844 be relocated. But in our callers i386_immediate and i386_displacement
9845 we don't yet know the operand size (this will be set by insn
9846 matching). Hence we record the word32 relocation here,
9847 and adjust the reloc according to the real size in reloc(). */
9848 static const struct {
9851 const enum bfd_reloc_code_real rel
[2];
9852 const i386_operand_type types64
;
9854 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9855 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32
,
9857 OPERAND_TYPE_IMM32_64
},
9859 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real
,
9860 BFD_RELOC_X86_64_PLTOFF64
},
9861 OPERAND_TYPE_IMM64
},
9862 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32
,
9863 BFD_RELOC_X86_64_PLT32
},
9864 OPERAND_TYPE_IMM32_32S_DISP32
},
9865 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real
,
9866 BFD_RELOC_X86_64_GOTPLT64
},
9867 OPERAND_TYPE_IMM64_DISP64
},
9868 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF
,
9869 BFD_RELOC_X86_64_GOTOFF64
},
9870 OPERAND_TYPE_IMM64_DISP64
},
9871 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real
,
9872 BFD_RELOC_X86_64_GOTPCREL
},
9873 OPERAND_TYPE_IMM32_32S_DISP32
},
9874 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD
,
9875 BFD_RELOC_X86_64_TLSGD
},
9876 OPERAND_TYPE_IMM32_32S_DISP32
},
9877 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM
,
9878 _dummy_first_bfd_reloc_code_real
},
9879 OPERAND_TYPE_NONE
},
9880 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real
,
9881 BFD_RELOC_X86_64_TLSLD
},
9882 OPERAND_TYPE_IMM32_32S_DISP32
},
9883 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32
,
9884 BFD_RELOC_X86_64_GOTTPOFF
},
9885 OPERAND_TYPE_IMM32_32S_DISP32
},
9886 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32
,
9887 BFD_RELOC_X86_64_TPOFF32
},
9888 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
9889 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE
,
9890 _dummy_first_bfd_reloc_code_real
},
9891 OPERAND_TYPE_NONE
},
9892 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32
,
9893 BFD_RELOC_X86_64_DTPOFF32
},
9894 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
9895 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE
,
9896 _dummy_first_bfd_reloc_code_real
},
9897 OPERAND_TYPE_NONE
},
9898 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE
,
9899 _dummy_first_bfd_reloc_code_real
},
9900 OPERAND_TYPE_NONE
},
9901 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32
,
9902 BFD_RELOC_X86_64_GOT32
},
9903 OPERAND_TYPE_IMM32_32S_64_DISP32
},
9904 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC
,
9905 BFD_RELOC_X86_64_GOTPC32_TLSDESC
},
9906 OPERAND_TYPE_IMM32_32S_DISP32
},
9907 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL
,
9908 BFD_RELOC_X86_64_TLSDESC_CALL
},
9909 OPERAND_TYPE_IMM32_32S_DISP32
},
9914 #if defined (OBJ_MAYBE_ELF)
9919 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
9920 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
9923 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
9925 int len
= gotrel
[j
].len
;
9926 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
9928 if (gotrel
[j
].rel
[object_64bit
] != 0)
9931 char *tmpbuf
, *past_reloc
;
9933 *rel
= gotrel
[j
].rel
[object_64bit
];
9937 if (flag_code
!= CODE_64BIT
)
9939 types
->bitfield
.imm32
= 1;
9940 types
->bitfield
.disp32
= 1;
9943 *types
= gotrel
[j
].types64
;
9946 if (j
!= 0 && GOT_symbol
== NULL
)
9947 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
9949 /* The length of the first part of our input line. */
9950 first
= cp
- input_line_pointer
;
9952 /* The second part goes from after the reloc token until
9953 (and including) an end_of_line char or comma. */
9954 past_reloc
= cp
+ 1 + len
;
9956 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
9958 second
= cp
+ 1 - past_reloc
;
9960 /* Allocate and copy string. The trailing NUL shouldn't
9961 be necessary, but be safe. */
9962 tmpbuf
= XNEWVEC (char, first
+ second
+ 2);
9963 memcpy (tmpbuf
, input_line_pointer
, first
);
9964 if (second
!= 0 && *past_reloc
!= ' ')
9965 /* Replace the relocation token with ' ', so that
9966 errors like foo@GOTOFF1 will be detected. */
9967 tmpbuf
[first
++] = ' ';
9969 /* Increment length by 1 if the relocation token is
9974 memcpy (tmpbuf
+ first
, past_reloc
, second
);
9975 tmpbuf
[first
+ second
] = '\0';
9979 as_bad (_("@%s reloc is not supported with %d-bit output format"),
9980 gotrel
[j
].str
, 1 << (5 + object_64bit
));
9985 /* Might be a symbol version string. Don't as_bad here. */
9994 /* Parse operands of the form
9995 <symbol>@SECREL32+<nnn>
9997 If we find one, set up the correct relocation in RELOC and copy the
9998 input string, minus the `@SECREL32' into a malloc'd buffer for
9999 parsing by the calling routine. Return this buffer, and if ADJUST
10000 is non-null set it to the length of the string we removed from the
10001 input line. Otherwise return NULL.
10003 This function is copied from the ELF version above adjusted for PE targets. */
10006 lex_got (enum bfd_reloc_code_real
*rel ATTRIBUTE_UNUSED
,
10007 int *adjust ATTRIBUTE_UNUSED
,
10008 i386_operand_type
*types
)
10010 static const struct
10014 const enum bfd_reloc_code_real rel
[2];
10015 const i386_operand_type types64
;
10019 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL
,
10020 BFD_RELOC_32_SECREL
},
10021 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
10027 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
10028 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
10031 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
10033 int len
= gotrel
[j
].len
;
10035 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
10037 if (gotrel
[j
].rel
[object_64bit
] != 0)
10040 char *tmpbuf
, *past_reloc
;
10042 *rel
= gotrel
[j
].rel
[object_64bit
];
10048 if (flag_code
!= CODE_64BIT
)
10050 types
->bitfield
.imm32
= 1;
10051 types
->bitfield
.disp32
= 1;
10054 *types
= gotrel
[j
].types64
;
10057 /* The length of the first part of our input line. */
10058 first
= cp
- input_line_pointer
;
10060 /* The second part goes from after the reloc token until
10061 (and including) an end_of_line char or comma. */
10062 past_reloc
= cp
+ 1 + len
;
10064 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
10066 second
= cp
+ 1 - past_reloc
;
10068 /* Allocate and copy string. The trailing NUL shouldn't
10069 be necessary, but be safe. */
10070 tmpbuf
= XNEWVEC (char, first
+ second
+ 2);
10071 memcpy (tmpbuf
, input_line_pointer
, first
);
10072 if (second
!= 0 && *past_reloc
!= ' ')
10073 /* Replace the relocation token with ' ', so that
10074 errors like foo@SECLREL321 will be detected. */
10075 tmpbuf
[first
++] = ' ';
10076 memcpy (tmpbuf
+ first
, past_reloc
, second
);
10077 tmpbuf
[first
+ second
] = '\0';
10081 as_bad (_("@%s reloc is not supported with %d-bit output format"),
10082 gotrel
[j
].str
, 1 << (5 + object_64bit
));
10087 /* Might be a symbol version string. Don't as_bad here. */
10093 bfd_reloc_code_real_type
10094 x86_cons (expressionS
*exp
, int size
)
10096 bfd_reloc_code_real_type got_reloc
= NO_RELOC
;
10098 intel_syntax
= -intel_syntax
;
10101 if (size
== 4 || (object_64bit
&& size
== 8))
10103 /* Handle @GOTOFF and the like in an expression. */
10105 char *gotfree_input_line
;
10108 save
= input_line_pointer
;
10109 gotfree_input_line
= lex_got (&got_reloc
, &adjust
, NULL
);
10110 if (gotfree_input_line
)
10111 input_line_pointer
= gotfree_input_line
;
10115 if (gotfree_input_line
)
10117 /* expression () has merrily parsed up to the end of line,
10118 or a comma - in the wrong buffer. Transfer how far
10119 input_line_pointer has moved to the right buffer. */
10120 input_line_pointer
= (save
10121 + (input_line_pointer
- gotfree_input_line
)
10123 free (gotfree_input_line
);
10124 if (exp
->X_op
== O_constant
10125 || exp
->X_op
== O_absent
10126 || exp
->X_op
== O_illegal
10127 || exp
->X_op
== O_register
10128 || exp
->X_op
== O_big
)
10130 char c
= *input_line_pointer
;
10131 *input_line_pointer
= 0;
10132 as_bad (_("missing or invalid expression `%s'"), save
);
10133 *input_line_pointer
= c
;
10135 else if ((got_reloc
== BFD_RELOC_386_PLT32
10136 || got_reloc
== BFD_RELOC_X86_64_PLT32
)
10137 && exp
->X_op
!= O_symbol
)
10139 char c
= *input_line_pointer
;
10140 *input_line_pointer
= 0;
10141 as_bad (_("invalid PLT expression `%s'"), save
);
10142 *input_line_pointer
= c
;
10149 intel_syntax
= -intel_syntax
;
10152 i386_intel_simplify (exp
);
10158 signed_cons (int size
)
10160 if (flag_code
== CODE_64BIT
)
10168 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
10175 if (exp
.X_op
== O_symbol
)
10176 exp
.X_op
= O_secrel
;
10178 emit_expr (&exp
, 4);
10180 while (*input_line_pointer
++ == ',');
10182 input_line_pointer
--;
10183 demand_empty_rest_of_line ();
10187 /* Handle Vector operations. */
10190 check_VecOperations (char *op_string
, char *op_end
)
10192 const reg_entry
*mask
;
10197 && (op_end
== NULL
|| op_string
< op_end
))
10200 if (*op_string
== '{')
10204 /* Check broadcasts. */
10205 if (strncmp (op_string
, "1to", 3) == 0)
10210 goto duplicated_vec_op
;
10213 if (*op_string
== '8')
10215 else if (*op_string
== '4')
10217 else if (*op_string
== '2')
10219 else if (*op_string
== '1'
10220 && *(op_string
+1) == '6')
10227 as_bad (_("Unsupported broadcast: `%s'"), saved
);
10232 broadcast_op
.type
= bcst_type
;
10233 broadcast_op
.operand
= this_operand
;
10234 broadcast_op
.bytes
= 0;
10235 i
.broadcast
= &broadcast_op
;
10237 /* Check masking operation. */
10238 else if ((mask
= parse_register (op_string
, &end_op
)) != NULL
)
10240 if (mask
== &bad_reg
)
10243 /* k0 can't be used for write mask. */
10244 if (mask
->reg_type
.bitfield
.class != RegMask
|| !mask
->reg_num
)
10246 as_bad (_("`%s%s' can't be used for write mask"),
10247 register_prefix
, mask
->reg_name
);
10253 mask_op
.mask
= mask
;
10254 mask_op
.zeroing
= 0;
10255 mask_op
.operand
= this_operand
;
10261 goto duplicated_vec_op
;
10263 i
.mask
->mask
= mask
;
10265 /* Only "{z}" is allowed here. No need to check
10266 zeroing mask explicitly. */
10267 if (i
.mask
->operand
!= this_operand
)
10269 as_bad (_("invalid write mask `%s'"), saved
);
10274 op_string
= end_op
;
10276 /* Check zeroing-flag for masking operation. */
10277 else if (*op_string
== 'z')
10281 mask_op
.mask
= NULL
;
10282 mask_op
.zeroing
= 1;
10283 mask_op
.operand
= this_operand
;
10288 if (i
.mask
->zeroing
)
10291 as_bad (_("duplicated `%s'"), saved
);
10295 i
.mask
->zeroing
= 1;
10297 /* Only "{%k}" is allowed here. No need to check mask
10298 register explicitly. */
10299 if (i
.mask
->operand
!= this_operand
)
10301 as_bad (_("invalid zeroing-masking `%s'"),
10310 goto unknown_vec_op
;
10312 if (*op_string
!= '}')
10314 as_bad (_("missing `}' in `%s'"), saved
);
10319 /* Strip whitespace since the addition of pseudo prefixes
10320 changed how the scrubber treats '{'. */
10321 if (is_space_char (*op_string
))
10327 /* We don't know this one. */
10328 as_bad (_("unknown vector operation: `%s'"), saved
);
10332 if (i
.mask
&& i
.mask
->zeroing
&& !i
.mask
->mask
)
10334 as_bad (_("zeroing-masking only allowed with write mask"));
10342 i386_immediate (char *imm_start
)
10344 char *save_input_line_pointer
;
10345 char *gotfree_input_line
;
10348 i386_operand_type types
;
10350 operand_type_set (&types
, ~0);
10352 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
10354 as_bad (_("at most %d immediate operands are allowed"),
10355 MAX_IMMEDIATE_OPERANDS
);
10359 exp
= &im_expressions
[i
.imm_operands
++];
10360 i
.op
[this_operand
].imms
= exp
;
10362 if (is_space_char (*imm_start
))
10365 save_input_line_pointer
= input_line_pointer
;
10366 input_line_pointer
= imm_start
;
10368 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
10369 if (gotfree_input_line
)
10370 input_line_pointer
= gotfree_input_line
;
10372 exp_seg
= expression (exp
);
10374 SKIP_WHITESPACE ();
10376 /* Handle vector operations. */
10377 if (*input_line_pointer
== '{')
10379 input_line_pointer
= check_VecOperations (input_line_pointer
,
10381 if (input_line_pointer
== NULL
)
10385 if (*input_line_pointer
)
10386 as_bad (_("junk `%s' after expression"), input_line_pointer
);
10388 input_line_pointer
= save_input_line_pointer
;
10389 if (gotfree_input_line
)
10391 free (gotfree_input_line
);
10393 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
10394 exp
->X_op
= O_illegal
;
10397 return i386_finalize_immediate (exp_seg
, exp
, types
, imm_start
);
10401 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
10402 i386_operand_type types
, const char *imm_start
)
10404 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_illegal
|| exp
->X_op
== O_big
)
10407 as_bad (_("missing or invalid immediate expression `%s'"),
10411 else if (exp
->X_op
== O_constant
)
10413 /* Size it properly later. */
10414 i
.types
[this_operand
].bitfield
.imm64
= 1;
10415 /* If not 64bit, sign extend val. */
10416 if (flag_code
!= CODE_64BIT
10417 && (exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
10419 = (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
10421 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
10422 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
10423 && exp_seg
!= absolute_section
10424 && exp_seg
!= text_section
10425 && exp_seg
!= data_section
10426 && exp_seg
!= bss_section
10427 && exp_seg
!= undefined_section
10428 && !bfd_is_com_section (exp_seg
))
10430 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
10434 else if (!intel_syntax
&& exp_seg
== reg_section
)
10437 as_bad (_("illegal immediate register operand %s"), imm_start
);
10442 /* This is an address. The size of the address will be
10443 determined later, depending on destination register,
10444 suffix, or the default for the section. */
10445 i
.types
[this_operand
].bitfield
.imm8
= 1;
10446 i
.types
[this_operand
].bitfield
.imm16
= 1;
10447 i
.types
[this_operand
].bitfield
.imm32
= 1;
10448 i
.types
[this_operand
].bitfield
.imm32s
= 1;
10449 i
.types
[this_operand
].bitfield
.imm64
= 1;
10450 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
10458 i386_scale (char *scale
)
10461 char *save
= input_line_pointer
;
10463 input_line_pointer
= scale
;
10464 val
= get_absolute_expression ();
10469 i
.log2_scale_factor
= 0;
10472 i
.log2_scale_factor
= 1;
10475 i
.log2_scale_factor
= 2;
10478 i
.log2_scale_factor
= 3;
10482 char sep
= *input_line_pointer
;
10484 *input_line_pointer
= '\0';
10485 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
10487 *input_line_pointer
= sep
;
10488 input_line_pointer
= save
;
10492 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
10494 as_warn (_("scale factor of %d without an index register"),
10495 1 << i
.log2_scale_factor
);
10496 i
.log2_scale_factor
= 0;
10498 scale
= input_line_pointer
;
10499 input_line_pointer
= save
;
10504 i386_displacement (char *disp_start
, char *disp_end
)
10508 char *save_input_line_pointer
;
10509 char *gotfree_input_line
;
10511 i386_operand_type bigdisp
, types
= anydisp
;
10514 if (i
.disp_operands
== MAX_MEMORY_OPERANDS
)
10516 as_bad (_("at most %d displacement operands are allowed"),
10517 MAX_MEMORY_OPERANDS
);
10521 operand_type_set (&bigdisp
, 0);
10523 || i
.types
[this_operand
].bitfield
.baseindex
10524 || (current_templates
->start
->opcode_modifier
.jump
!= JUMP
10525 && current_templates
->start
->opcode_modifier
.jump
!= JUMP_DWORD
))
10527 i386_addressing_mode ();
10528 override
= (i
.prefix
[ADDR_PREFIX
] != 0);
10529 if (flag_code
== CODE_64BIT
)
10533 bigdisp
.bitfield
.disp32s
= 1;
10534 bigdisp
.bitfield
.disp64
= 1;
10537 bigdisp
.bitfield
.disp32
= 1;
10539 else if ((flag_code
== CODE_16BIT
) ^ override
)
10540 bigdisp
.bitfield
.disp16
= 1;
10542 bigdisp
.bitfield
.disp32
= 1;
10546 /* For PC-relative branches, the width of the displacement may be
10547 dependent upon data size, but is never dependent upon address size.
10548 Also make sure to not unintentionally match against a non-PC-relative
10549 branch template. */
10550 static templates aux_templates
;
10551 const insn_template
*t
= current_templates
->start
;
10552 bfd_boolean has_intel64
= FALSE
;
10554 aux_templates
.start
= t
;
10555 while (++t
< current_templates
->end
)
10557 if (t
->opcode_modifier
.jump
10558 != current_templates
->start
->opcode_modifier
.jump
)
10560 if ((t
->opcode_modifier
.isa64
>= INTEL64
))
10561 has_intel64
= TRUE
;
10563 if (t
< current_templates
->end
)
10565 aux_templates
.end
= t
;
10566 current_templates
= &aux_templates
;
10569 override
= (i
.prefix
[DATA_PREFIX
] != 0);
10570 if (flag_code
== CODE_64BIT
)
10572 if ((override
|| i
.suffix
== WORD_MNEM_SUFFIX
)
10573 && (!intel64
|| !has_intel64
))
10574 bigdisp
.bitfield
.disp16
= 1;
10576 bigdisp
.bitfield
.disp32s
= 1;
10581 override
= (i
.suffix
== (flag_code
!= CODE_16BIT
10583 : LONG_MNEM_SUFFIX
));
10584 bigdisp
.bitfield
.disp32
= 1;
10585 if ((flag_code
== CODE_16BIT
) ^ override
)
10587 bigdisp
.bitfield
.disp32
= 0;
10588 bigdisp
.bitfield
.disp16
= 1;
10592 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
10595 exp
= &disp_expressions
[i
.disp_operands
];
10596 i
.op
[this_operand
].disps
= exp
;
10598 save_input_line_pointer
= input_line_pointer
;
10599 input_line_pointer
= disp_start
;
10600 END_STRING_AND_SAVE (disp_end
);
10602 #ifndef GCC_ASM_O_HACK
10603 #define GCC_ASM_O_HACK 0
10606 END_STRING_AND_SAVE (disp_end
+ 1);
10607 if (i
.types
[this_operand
].bitfield
.baseIndex
10608 && displacement_string_end
[-1] == '+')
10610 /* This hack is to avoid a warning when using the "o"
10611 constraint within gcc asm statements.
10614 #define _set_tssldt_desc(n,addr,limit,type) \
10615 __asm__ __volatile__ ( \
10616 "movw %w2,%0\n\t" \
10617 "movw %w1,2+%0\n\t" \
10618 "rorl $16,%1\n\t" \
10619 "movb %b1,4+%0\n\t" \
10620 "movb %4,5+%0\n\t" \
10621 "movb $0,6+%0\n\t" \
10622 "movb %h1,7+%0\n\t" \
10624 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
10626 This works great except that the output assembler ends
10627 up looking a bit weird if it turns out that there is
10628 no offset. You end up producing code that looks like:
10641 So here we provide the missing zero. */
10643 *displacement_string_end
= '0';
10646 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
10647 if (gotfree_input_line
)
10648 input_line_pointer
= gotfree_input_line
;
10650 exp_seg
= expression (exp
);
10652 SKIP_WHITESPACE ();
10653 if (*input_line_pointer
)
10654 as_bad (_("junk `%s' after expression"), input_line_pointer
);
10656 RESTORE_END_STRING (disp_end
+ 1);
10658 input_line_pointer
= save_input_line_pointer
;
10659 if (gotfree_input_line
)
10661 free (gotfree_input_line
);
10663 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
10664 exp
->X_op
= O_illegal
;
10667 ret
= i386_finalize_displacement (exp_seg
, exp
, types
, disp_start
);
10669 RESTORE_END_STRING (disp_end
);
10675 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
10676 i386_operand_type types
, const char *disp_start
)
10678 i386_operand_type bigdisp
;
10681 /* We do this to make sure that the section symbol is in
10682 the symbol table. We will ultimately change the relocation
10683 to be relative to the beginning of the section. */
10684 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
10685 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
10686 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
10688 if (exp
->X_op
!= O_symbol
)
10691 if (S_IS_LOCAL (exp
->X_add_symbol
)
10692 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
10693 && S_GET_SEGMENT (exp
->X_add_symbol
) != expr_section
)
10694 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
10695 exp
->X_op
= O_subtract
;
10696 exp
->X_op_symbol
= GOT_symbol
;
10697 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
10698 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
10699 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
10700 i
.reloc
[this_operand
] = BFD_RELOC_64
;
10702 i
.reloc
[this_operand
] = BFD_RELOC_32
;
10705 else if (exp
->X_op
== O_absent
10706 || exp
->X_op
== O_illegal
10707 || exp
->X_op
== O_big
)
10710 as_bad (_("missing or invalid displacement expression `%s'"),
10715 else if (flag_code
== CODE_64BIT
10716 && !i
.prefix
[ADDR_PREFIX
]
10717 && exp
->X_op
== O_constant
)
10719 /* Since displacement is signed extended to 64bit, don't allow
10720 disp32 and turn off disp32s if they are out of range. */
10721 i
.types
[this_operand
].bitfield
.disp32
= 0;
10722 if (!fits_in_signed_long (exp
->X_add_number
))
10724 i
.types
[this_operand
].bitfield
.disp32s
= 0;
10725 if (i
.types
[this_operand
].bitfield
.baseindex
)
10727 as_bad (_("0x%lx out range of signed 32bit displacement"),
10728 (long) exp
->X_add_number
);
10734 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
10735 else if (exp
->X_op
!= O_constant
10736 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
10737 && exp_seg
!= absolute_section
10738 && exp_seg
!= text_section
10739 && exp_seg
!= data_section
10740 && exp_seg
!= bss_section
10741 && exp_seg
!= undefined_section
10742 && !bfd_is_com_section (exp_seg
))
10744 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
10749 if (current_templates
->start
->opcode_modifier
.jump
== JUMP_BYTE
10750 /* Constants get taken care of by optimize_disp(). */
10751 && exp
->X_op
!= O_constant
)
10752 i
.types
[this_operand
].bitfield
.disp8
= 1;
10754 /* Check if this is a displacement only operand. */
10755 bigdisp
= i
.types
[this_operand
];
10756 bigdisp
.bitfield
.disp8
= 0;
10757 bigdisp
.bitfield
.disp16
= 0;
10758 bigdisp
.bitfield
.disp32
= 0;
10759 bigdisp
.bitfield
.disp32s
= 0;
10760 bigdisp
.bitfield
.disp64
= 0;
10761 if (operand_type_all_zero (&bigdisp
))
10762 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
10768 /* Return the active addressing mode, taking address override and
10769 registers forming the address into consideration. Update the
10770 address override prefix if necessary. */
10772 static enum flag_code
10773 i386_addressing_mode (void)
10775 enum flag_code addr_mode
;
10777 if (i
.prefix
[ADDR_PREFIX
])
10778 addr_mode
= flag_code
== CODE_32BIT
? CODE_16BIT
: CODE_32BIT
;
10779 else if (flag_code
== CODE_16BIT
10780 && current_templates
->start
->cpu_flags
.bitfield
.cpumpx
10781 /* Avoid replacing the "16-bit addressing not allowed" diagnostic
10782 from md_assemble() by "is not a valid base/index expression"
10783 when there is a base and/or index. */
10784 && !i
.types
[this_operand
].bitfield
.baseindex
)
10786 /* MPX insn memory operands with neither base nor index must be forced
10787 to use 32-bit addressing in 16-bit mode. */
10788 addr_mode
= CODE_32BIT
;
10789 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
10791 gas_assert (!i
.types
[this_operand
].bitfield
.disp16
);
10792 gas_assert (!i
.types
[this_operand
].bitfield
.disp32
);
10796 addr_mode
= flag_code
;
10798 #if INFER_ADDR_PREFIX
10799 if (i
.mem_operands
== 0)
10801 /* Infer address prefix from the first memory operand. */
10802 const reg_entry
*addr_reg
= i
.base_reg
;
10804 if (addr_reg
== NULL
)
10805 addr_reg
= i
.index_reg
;
10809 if (addr_reg
->reg_type
.bitfield
.dword
)
10810 addr_mode
= CODE_32BIT
;
10811 else if (flag_code
!= CODE_64BIT
10812 && addr_reg
->reg_type
.bitfield
.word
)
10813 addr_mode
= CODE_16BIT
;
10815 if (addr_mode
!= flag_code
)
10817 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
10819 /* Change the size of any displacement too. At most one
10820 of Disp16 or Disp32 is set.
10821 FIXME. There doesn't seem to be any real need for
10822 separate Disp16 and Disp32 flags. The same goes for
10823 Imm16 and Imm32. Removing them would probably clean
10824 up the code quite a lot. */
10825 if (flag_code
!= CODE_64BIT
10826 && (i
.types
[this_operand
].bitfield
.disp16
10827 || i
.types
[this_operand
].bitfield
.disp32
))
10828 i
.types
[this_operand
]
10829 = operand_type_xor (i
.types
[this_operand
], disp16_32
);
10839 /* Make sure the memory operand we've been dealt is valid.
10840 Return 1 on success, 0 on a failure. */
10843 i386_index_check (const char *operand_string
)
10845 const char *kind
= "base/index";
10846 enum flag_code addr_mode
= i386_addressing_mode ();
10848 if (current_templates
->start
->opcode_modifier
.isstring
10849 && !current_templates
->start
->cpu_flags
.bitfield
.cpupadlock
10850 && (current_templates
->end
[-1].opcode_modifier
.isstring
10851 || i
.mem_operands
))
10853 /* Memory operands of string insns are special in that they only allow
10854 a single register (rDI, rSI, or rBX) as their memory address. */
10855 const reg_entry
*expected_reg
;
10856 static const char *di_si
[][2] =
10862 static const char *bx
[] = { "ebx", "bx", "rbx" };
10864 kind
= "string address";
10866 if (current_templates
->start
->opcode_modifier
.repprefixok
)
10868 int es_op
= current_templates
->end
[-1].opcode_modifier
.isstring
10869 - IS_STRING_ES_OP0
;
10872 if (!current_templates
->end
[-1].operand_types
[0].bitfield
.baseindex
10873 || ((!i
.mem_operands
!= !intel_syntax
)
10874 && current_templates
->end
[-1].operand_types
[1]
10875 .bitfield
.baseindex
))
10877 expected_reg
= hash_find (reg_hash
, di_si
[addr_mode
][op
== es_op
]);
10880 expected_reg
= hash_find (reg_hash
, bx
[addr_mode
]);
10882 if (i
.base_reg
!= expected_reg
10884 || operand_type_check (i
.types
[this_operand
], disp
))
10886 /* The second memory operand must have the same size as
10890 && !((addr_mode
== CODE_64BIT
10891 && i
.base_reg
->reg_type
.bitfield
.qword
)
10892 || (addr_mode
== CODE_32BIT
10893 ? i
.base_reg
->reg_type
.bitfield
.dword
10894 : i
.base_reg
->reg_type
.bitfield
.word
)))
10897 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
10899 intel_syntax
? '[' : '(',
10901 expected_reg
->reg_name
,
10902 intel_syntax
? ']' : ')');
10909 as_bad (_("`%s' is not a valid %s expression"),
10910 operand_string
, kind
);
10915 if (addr_mode
!= CODE_16BIT
)
10917 /* 32-bit/64-bit checks. */
10919 && ((addr_mode
== CODE_64BIT
10920 ? !i
.base_reg
->reg_type
.bitfield
.qword
10921 : !i
.base_reg
->reg_type
.bitfield
.dword
)
10922 || (i
.index_reg
&& i
.base_reg
->reg_num
== RegIP
)
10923 || i
.base_reg
->reg_num
== RegIZ
))
10925 && !i
.index_reg
->reg_type
.bitfield
.xmmword
10926 && !i
.index_reg
->reg_type
.bitfield
.ymmword
10927 && !i
.index_reg
->reg_type
.bitfield
.zmmword
10928 && ((addr_mode
== CODE_64BIT
10929 ? !i
.index_reg
->reg_type
.bitfield
.qword
10930 : !i
.index_reg
->reg_type
.bitfield
.dword
)
10931 || !i
.index_reg
->reg_type
.bitfield
.baseindex
)))
10934 /* bndmk, bndldx, and bndstx have special restrictions. */
10935 if (current_templates
->start
->base_opcode
== 0xf30f1b
10936 || (current_templates
->start
->base_opcode
& ~1) == 0x0f1a)
10938 /* They cannot use RIP-relative addressing. */
10939 if (i
.base_reg
&& i
.base_reg
->reg_num
== RegIP
)
10941 as_bad (_("`%s' cannot be used here"), operand_string
);
10945 /* bndldx and bndstx ignore their scale factor. */
10946 if (current_templates
->start
->base_opcode
!= 0xf30f1b
10947 && i
.log2_scale_factor
)
10948 as_warn (_("register scaling is being ignored here"));
10953 /* 16-bit checks. */
10955 && (!i
.base_reg
->reg_type
.bitfield
.word
10956 || !i
.base_reg
->reg_type
.bitfield
.baseindex
))
10958 && (!i
.index_reg
->reg_type
.bitfield
.word
10959 || !i
.index_reg
->reg_type
.bitfield
.baseindex
10961 && i
.base_reg
->reg_num
< 6
10962 && i
.index_reg
->reg_num
>= 6
10963 && i
.log2_scale_factor
== 0))))
10970 /* Handle vector immediates. */
10973 RC_SAE_immediate (const char *imm_start
)
10975 unsigned int match_found
, j
;
10976 const char *pstr
= imm_start
;
10984 for (j
= 0; j
< ARRAY_SIZE (RC_NamesTable
); j
++)
10986 if (!strncmp (pstr
, RC_NamesTable
[j
].name
, RC_NamesTable
[j
].len
))
10990 rc_op
.type
= RC_NamesTable
[j
].type
;
10991 rc_op
.operand
= this_operand
;
10992 i
.rounding
= &rc_op
;
10996 as_bad (_("duplicated `%s'"), imm_start
);
10999 pstr
+= RC_NamesTable
[j
].len
;
11007 if (*pstr
++ != '}')
11009 as_bad (_("Missing '}': '%s'"), imm_start
);
11012 /* RC/SAE immediate string should contain nothing more. */;
11015 as_bad (_("Junk after '}': '%s'"), imm_start
);
11019 exp
= &im_expressions
[i
.imm_operands
++];
11020 i
.op
[this_operand
].imms
= exp
;
11022 exp
->X_op
= O_constant
;
11023 exp
->X_add_number
= 0;
11024 exp
->X_add_symbol
= (symbolS
*) 0;
11025 exp
->X_op_symbol
= (symbolS
*) 0;
11027 i
.types
[this_operand
].bitfield
.imm8
= 1;
11031 /* Only string instructions can have a second memory operand, so
11032 reduce current_templates to just those if it contains any. */
11034 maybe_adjust_templates (void)
11036 const insn_template
*t
;
11038 gas_assert (i
.mem_operands
== 1);
11040 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
11041 if (t
->opcode_modifier
.isstring
)
11044 if (t
< current_templates
->end
)
11046 static templates aux_templates
;
11047 bfd_boolean recheck
;
11049 aux_templates
.start
= t
;
11050 for (; t
< current_templates
->end
; ++t
)
11051 if (!t
->opcode_modifier
.isstring
)
11053 aux_templates
.end
= t
;
11055 /* Determine whether to re-check the first memory operand. */
11056 recheck
= (aux_templates
.start
!= current_templates
->start
11057 || t
!= current_templates
->end
);
11059 current_templates
= &aux_templates
;
11063 i
.mem_operands
= 0;
11064 if (i
.memop1_string
!= NULL
11065 && i386_index_check (i
.memop1_string
) == 0)
11067 i
.mem_operands
= 1;
11074 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
11078 i386_att_operand (char *operand_string
)
11080 const reg_entry
*r
;
11082 char *op_string
= operand_string
;
11084 if (is_space_char (*op_string
))
11087 /* We check for an absolute prefix (differentiating,
11088 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
11089 if (*op_string
== ABSOLUTE_PREFIX
)
11092 if (is_space_char (*op_string
))
11094 i
.jumpabsolute
= TRUE
;
11097 /* Check if operand is a register. */
11098 if ((r
= parse_register (op_string
, &end_op
)) != NULL
)
11100 i386_operand_type temp
;
11105 /* Check for a segment override by searching for ':' after a
11106 segment register. */
11107 op_string
= end_op
;
11108 if (is_space_char (*op_string
))
11110 if (*op_string
== ':' && r
->reg_type
.bitfield
.class == SReg
)
11112 switch (r
->reg_num
)
11115 i
.seg
[i
.mem_operands
] = &es
;
11118 i
.seg
[i
.mem_operands
] = &cs
;
11121 i
.seg
[i
.mem_operands
] = &ss
;
11124 i
.seg
[i
.mem_operands
] = &ds
;
11127 i
.seg
[i
.mem_operands
] = &fs
;
11130 i
.seg
[i
.mem_operands
] = &gs
;
11134 /* Skip the ':' and whitespace. */
11136 if (is_space_char (*op_string
))
11139 if (!is_digit_char (*op_string
)
11140 && !is_identifier_char (*op_string
)
11141 && *op_string
!= '('
11142 && *op_string
!= ABSOLUTE_PREFIX
)
11144 as_bad (_("bad memory operand `%s'"), op_string
);
11147 /* Handle case of %es:*foo. */
11148 if (*op_string
== ABSOLUTE_PREFIX
)
11151 if (is_space_char (*op_string
))
11153 i
.jumpabsolute
= TRUE
;
11155 goto do_memory_reference
;
11158 /* Handle vector operations. */
11159 if (*op_string
== '{')
11161 op_string
= check_VecOperations (op_string
, NULL
);
11162 if (op_string
== NULL
)
11168 as_bad (_("junk `%s' after register"), op_string
);
11171 temp
= r
->reg_type
;
11172 temp
.bitfield
.baseindex
= 0;
11173 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
11175 i
.types
[this_operand
].bitfield
.unspecified
= 0;
11176 i
.op
[this_operand
].regs
= r
;
11179 else if (*op_string
== REGISTER_PREFIX
)
11181 as_bad (_("bad register name `%s'"), op_string
);
11184 else if (*op_string
== IMMEDIATE_PREFIX
)
11187 if (i
.jumpabsolute
)
11189 as_bad (_("immediate operand illegal with absolute jump"));
11192 if (!i386_immediate (op_string
))
11195 else if (RC_SAE_immediate (operand_string
))
11197 /* If it is a RC or SAE immediate, do nothing. */
11200 else if (is_digit_char (*op_string
)
11201 || is_identifier_char (*op_string
)
11202 || *op_string
== '"'
11203 || *op_string
== '(')
11205 /* This is a memory reference of some sort. */
11208 /* Start and end of displacement string expression (if found). */
11209 char *displacement_string_start
;
11210 char *displacement_string_end
;
11213 do_memory_reference
:
11214 if (i
.mem_operands
== 1 && !maybe_adjust_templates ())
11216 if ((i
.mem_operands
== 1
11217 && !current_templates
->start
->opcode_modifier
.isstring
)
11218 || i
.mem_operands
== 2)
11220 as_bad (_("too many memory references for `%s'"),
11221 current_templates
->start
->name
);
11225 /* Check for base index form. We detect the base index form by
11226 looking for an ')' at the end of the operand, searching
11227 for the '(' matching it, and finding a REGISTER_PREFIX or ','
11229 base_string
= op_string
+ strlen (op_string
);
11231 /* Handle vector operations. */
11232 vop_start
= strchr (op_string
, '{');
11233 if (vop_start
&& vop_start
< base_string
)
11235 if (check_VecOperations (vop_start
, base_string
) == NULL
)
11237 base_string
= vop_start
;
11241 if (is_space_char (*base_string
))
11244 /* If we only have a displacement, set-up for it to be parsed later. */
11245 displacement_string_start
= op_string
;
11246 displacement_string_end
= base_string
+ 1;
11248 if (*base_string
== ')')
11251 unsigned int parens_balanced
= 1;
11252 /* We've already checked that the number of left & right ()'s are
11253 equal, so this loop will not be infinite. */
11257 if (*base_string
== ')')
11259 if (*base_string
== '(')
11262 while (parens_balanced
);
11264 temp_string
= base_string
;
11266 /* Skip past '(' and whitespace. */
11268 if (is_space_char (*base_string
))
11271 if (*base_string
== ','
11272 || ((i
.base_reg
= parse_register (base_string
, &end_op
))
11275 displacement_string_end
= temp_string
;
11277 i
.types
[this_operand
].bitfield
.baseindex
= 1;
11281 if (i
.base_reg
== &bad_reg
)
11283 base_string
= end_op
;
11284 if (is_space_char (*base_string
))
11288 /* There may be an index reg or scale factor here. */
11289 if (*base_string
== ',')
11292 if (is_space_char (*base_string
))
11295 if ((i
.index_reg
= parse_register (base_string
, &end_op
))
11298 if (i
.index_reg
== &bad_reg
)
11300 base_string
= end_op
;
11301 if (is_space_char (*base_string
))
11303 if (*base_string
== ',')
11306 if (is_space_char (*base_string
))
11309 else if (*base_string
!= ')')
11311 as_bad (_("expecting `,' or `)' "
11312 "after index register in `%s'"),
11317 else if (*base_string
== REGISTER_PREFIX
)
11319 end_op
= strchr (base_string
, ',');
11322 as_bad (_("bad register name `%s'"), base_string
);
11326 /* Check for scale factor. */
11327 if (*base_string
!= ')')
11329 char *end_scale
= i386_scale (base_string
);
11334 base_string
= end_scale
;
11335 if (is_space_char (*base_string
))
11337 if (*base_string
!= ')')
11339 as_bad (_("expecting `)' "
11340 "after scale factor in `%s'"),
11345 else if (!i
.index_reg
)
11347 as_bad (_("expecting index register or scale factor "
11348 "after `,'; got '%c'"),
11353 else if (*base_string
!= ')')
11355 as_bad (_("expecting `,' or `)' "
11356 "after base register in `%s'"),
11361 else if (*base_string
== REGISTER_PREFIX
)
11363 end_op
= strchr (base_string
, ',');
11366 as_bad (_("bad register name `%s'"), base_string
);
11371 /* If there's an expression beginning the operand, parse it,
11372 assuming displacement_string_start and
11373 displacement_string_end are meaningful. */
11374 if (displacement_string_start
!= displacement_string_end
)
11376 if (!i386_displacement (displacement_string_start
,
11377 displacement_string_end
))
11381 /* Special case for (%dx) while doing input/output op. */
11383 && i
.base_reg
->reg_type
.bitfield
.instance
== RegD
11384 && i
.base_reg
->reg_type
.bitfield
.word
11385 && i
.index_reg
== 0
11386 && i
.log2_scale_factor
== 0
11387 && i
.seg
[i
.mem_operands
] == 0
11388 && !operand_type_check (i
.types
[this_operand
], disp
))
11390 i
.types
[this_operand
] = i
.base_reg
->reg_type
;
11394 if (i386_index_check (operand_string
) == 0)
11396 i
.flags
[this_operand
] |= Operand_Mem
;
11397 if (i
.mem_operands
== 0)
11398 i
.memop1_string
= xstrdup (operand_string
);
11403 /* It's not a memory operand; argh! */
11404 as_bad (_("invalid char %s beginning operand %d `%s'"),
11405 output_invalid (*op_string
),
11410 return 1; /* Normal return. */
11413 /* Calculate the maximum variable size (i.e., excluding fr_fix)
11414 that an rs_machine_dependent frag may reach. */
11417 i386_frag_max_var (fragS
*frag
)
11419 /* The only relaxable frags are for jumps.
11420 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
11421 gas_assert (frag
->fr_type
== rs_machine_dependent
);
11422 return TYPE_FROM_RELAX_STATE (frag
->fr_subtype
) == UNCOND_JUMP
? 4 : 5;
11425 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11427 elf_symbol_resolved_in_segment_p (symbolS
*fr_symbol
, offsetT fr_var
)
11429 /* STT_GNU_IFUNC symbol must go through PLT. */
11430 if ((symbol_get_bfdsym (fr_symbol
)->flags
11431 & BSF_GNU_INDIRECT_FUNCTION
) != 0)
11434 if (!S_IS_EXTERNAL (fr_symbol
))
11435 /* Symbol may be weak or local. */
11436 return !S_IS_WEAK (fr_symbol
);
11438 /* Global symbols with non-default visibility can't be preempted. */
11439 if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol
)) != STV_DEFAULT
)
11442 if (fr_var
!= NO_RELOC
)
11443 switch ((enum bfd_reloc_code_real
) fr_var
)
11445 case BFD_RELOC_386_PLT32
:
11446 case BFD_RELOC_X86_64_PLT32
:
11447 /* Symbol with PLT relocation may be preempted. */
11453 /* Global symbols with default visibility in a shared library may be
11454 preempted by another definition. */
11459 /* Table 3-2. Macro-Fusible Instructions in Haswell Microarchitecture
11460 Note also work for Skylake and Cascadelake.
11461 ---------------------------------------------------------------------
11462 | JCC | ADD/SUB/CMP | INC/DEC | TEST/AND |
11463 | ------ | ----------- | ------- | -------- |
11465 | Jno | N | N | Y |
11466 | Jc/Jb | Y | N | Y |
11467 | Jae/Jnb | Y | N | Y |
11468 | Je/Jz | Y | Y | Y |
11469 | Jne/Jnz | Y | Y | Y |
11470 | Jna/Jbe | Y | N | Y |
11471 | Ja/Jnbe | Y | N | Y |
11473 | Jns | N | N | Y |
11474 | Jp/Jpe | N | N | Y |
11475 | Jnp/Jpo | N | N | Y |
11476 | Jl/Jnge | Y | Y | Y |
11477 | Jge/Jnl | Y | Y | Y |
11478 | Jle/Jng | Y | Y | Y |
11479 | Jg/Jnle | Y | Y | Y |
11480 --------------------------------------------------------------------- */
11482 i386_macro_fusible_p (enum mf_cmp_kind mf_cmp
, enum mf_jcc_kind mf_jcc
)
11484 if (mf_cmp
== mf_cmp_alu_cmp
)
11485 return ((mf_jcc
>= mf_jcc_jc
&& mf_jcc
<= mf_jcc_jna
)
11486 || mf_jcc
== mf_jcc_jl
|| mf_jcc
== mf_jcc_jle
);
11487 if (mf_cmp
== mf_cmp_incdec
)
11488 return (mf_jcc
== mf_jcc_je
|| mf_jcc
== mf_jcc_jl
11489 || mf_jcc
== mf_jcc_jle
);
11490 if (mf_cmp
== mf_cmp_test_and
)
11495 /* Return the next non-empty frag. */
11498 i386_next_non_empty_frag (fragS
*fragP
)
11500 /* There may be a frag with a ".fill 0" when there is no room in
11501 the current frag for frag_grow in output_insn. */
11502 for (fragP
= fragP
->fr_next
;
11504 && fragP
->fr_type
== rs_fill
11505 && fragP
->fr_fix
== 0);
11506 fragP
= fragP
->fr_next
)
11511 /* Return the next jcc frag after BRANCH_PADDING. */
11514 i386_next_fusible_jcc_frag (fragS
*maybe_cmp_fragP
, fragS
*pad_fragP
)
11516 fragS
*branch_fragP
;
11520 if (pad_fragP
->fr_type
== rs_machine_dependent
11521 && (TYPE_FROM_RELAX_STATE (pad_fragP
->fr_subtype
)
11522 == BRANCH_PADDING
))
11524 branch_fragP
= i386_next_non_empty_frag (pad_fragP
);
11525 if (branch_fragP
->fr_type
!= rs_machine_dependent
)
11527 if (TYPE_FROM_RELAX_STATE (branch_fragP
->fr_subtype
) == COND_JUMP
11528 && i386_macro_fusible_p (maybe_cmp_fragP
->tc_frag_data
.mf_type
,
11529 pad_fragP
->tc_frag_data
.mf_type
))
11530 return branch_fragP
;
11536 /* Classify BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING frags. */
11539 i386_classify_machine_dependent_frag (fragS
*fragP
)
11543 fragS
*branch_fragP
;
11545 unsigned int max_prefix_length
;
11547 if (fragP
->tc_frag_data
.classified
)
11550 /* First scan for BRANCH_PADDING and FUSED_JCC_PADDING. Convert
11551 FUSED_JCC_PADDING and merge BRANCH_PADDING. */
11552 for (next_fragP
= fragP
;
11553 next_fragP
!= NULL
;
11554 next_fragP
= next_fragP
->fr_next
)
11556 next_fragP
->tc_frag_data
.classified
= 1;
11557 if (next_fragP
->fr_type
== rs_machine_dependent
)
11558 switch (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
))
11560 case BRANCH_PADDING
:
11561 /* The BRANCH_PADDING frag must be followed by a branch
11563 branch_fragP
= i386_next_non_empty_frag (next_fragP
);
11564 next_fragP
->tc_frag_data
.u
.branch_fragP
= branch_fragP
;
11566 case FUSED_JCC_PADDING
:
11567 /* Check if this is a fused jcc:
11569 CMP like instruction
11573 cmp_fragP
= i386_next_non_empty_frag (next_fragP
);
11574 pad_fragP
= i386_next_non_empty_frag (cmp_fragP
);
11575 branch_fragP
= i386_next_fusible_jcc_frag (next_fragP
, pad_fragP
);
11578 /* The BRANCH_PADDING frag is merged with the
11579 FUSED_JCC_PADDING frag. */
11580 next_fragP
->tc_frag_data
.u
.branch_fragP
= branch_fragP
;
11581 /* CMP like instruction size. */
11582 next_fragP
->tc_frag_data
.cmp_size
= cmp_fragP
->fr_fix
;
11583 frag_wane (pad_fragP
);
11584 /* Skip to branch_fragP. */
11585 next_fragP
= branch_fragP
;
11587 else if (next_fragP
->tc_frag_data
.max_prefix_length
)
11589 /* Turn FUSED_JCC_PADDING into BRANCH_PREFIX if it isn't
11591 next_fragP
->fr_subtype
11592 = ENCODE_RELAX_STATE (BRANCH_PREFIX
, 0);
11593 next_fragP
->tc_frag_data
.max_bytes
11594 = next_fragP
->tc_frag_data
.max_prefix_length
;
11595 /* This will be updated in the BRANCH_PREFIX scan. */
11596 next_fragP
->tc_frag_data
.max_prefix_length
= 0;
11599 frag_wane (next_fragP
);
11604 /* Stop if there is no BRANCH_PREFIX. */
11605 if (!align_branch_prefix_size
)
11608 /* Scan for BRANCH_PREFIX. */
11609 for (; fragP
!= NULL
; fragP
= fragP
->fr_next
)
11611 if (fragP
->fr_type
!= rs_machine_dependent
11612 || (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
)
11616 /* Count all BRANCH_PREFIX frags before BRANCH_PADDING and
11617 COND_JUMP_PREFIX. */
11618 max_prefix_length
= 0;
11619 for (next_fragP
= fragP
;
11620 next_fragP
!= NULL
;
11621 next_fragP
= next_fragP
->fr_next
)
11623 if (next_fragP
->fr_type
== rs_fill
)
11624 /* Skip rs_fill frags. */
11626 else if (next_fragP
->fr_type
!= rs_machine_dependent
)
11627 /* Stop for all other frags. */
11630 /* rs_machine_dependent frags. */
11631 if (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
11634 /* Count BRANCH_PREFIX frags. */
11635 if (max_prefix_length
>= MAX_FUSED_JCC_PADDING_SIZE
)
11637 max_prefix_length
= MAX_FUSED_JCC_PADDING_SIZE
;
11638 frag_wane (next_fragP
);
11642 += next_fragP
->tc_frag_data
.max_bytes
;
11644 else if ((TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
11646 || (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
11647 == FUSED_JCC_PADDING
))
11649 /* Stop at BRANCH_PADDING and FUSED_JCC_PADDING. */
11650 fragP
->tc_frag_data
.u
.padding_fragP
= next_fragP
;
11654 /* Stop for other rs_machine_dependent frags. */
11658 fragP
->tc_frag_data
.max_prefix_length
= max_prefix_length
;
11660 /* Skip to the next frag. */
11661 fragP
= next_fragP
;
11665 /* Compute padding size for
11668 CMP like instruction
11670 COND_JUMP/UNCOND_JUMP
11675 COND_JUMP/UNCOND_JUMP
11679 i386_branch_padding_size (fragS
*fragP
, offsetT address
)
11681 unsigned int offset
, size
, padding_size
;
11682 fragS
*branch_fragP
= fragP
->tc_frag_data
.u
.branch_fragP
;
11684 /* The start address of the BRANCH_PADDING or FUSED_JCC_PADDING frag. */
11686 address
= fragP
->fr_address
;
11687 address
+= fragP
->fr_fix
;
11689 /* CMP like instrunction size. */
11690 size
= fragP
->tc_frag_data
.cmp_size
;
11692 /* The base size of the branch frag. */
11693 size
+= branch_fragP
->fr_fix
;
11695 /* Add opcode and displacement bytes for the rs_machine_dependent
11697 if (branch_fragP
->fr_type
== rs_machine_dependent
)
11698 size
+= md_relax_table
[branch_fragP
->fr_subtype
].rlx_length
;
11700 /* Check if branch is within boundary and doesn't end at the last
11702 offset
= address
& ((1U << align_branch_power
) - 1);
11703 if ((offset
+ size
) >= (1U << align_branch_power
))
11704 /* Padding needed to avoid crossing boundary. */
11705 padding_size
= (1U << align_branch_power
) - offset
;
11707 /* No padding needed. */
11710 /* The return value may be saved in tc_frag_data.length which is
11712 if (!fits_in_unsigned_byte (padding_size
))
11715 return padding_size
;
11718 /* i386_generic_table_relax_frag()
11720 Handle BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING frags to
11721 grow/shrink padding to align branch frags. Hand others to
11725 i386_generic_table_relax_frag (segT segment
, fragS
*fragP
, long stretch
)
11727 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
11728 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
)
11730 long padding_size
= i386_branch_padding_size (fragP
, 0);
11731 long grow
= padding_size
- fragP
->tc_frag_data
.length
;
11733 /* When the BRANCH_PREFIX frag is used, the computed address
11734 must match the actual address and there should be no padding. */
11735 if (fragP
->tc_frag_data
.padding_address
11736 && (fragP
->tc_frag_data
.padding_address
!= fragP
->fr_address
11740 /* Update the padding size. */
11742 fragP
->tc_frag_data
.length
= padding_size
;
11746 else if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
)
11748 fragS
*padding_fragP
, *next_fragP
;
11749 long padding_size
, left_size
, last_size
;
11751 padding_fragP
= fragP
->tc_frag_data
.u
.padding_fragP
;
11752 if (!padding_fragP
)
11753 /* Use the padding set by the leading BRANCH_PREFIX frag. */
11754 return (fragP
->tc_frag_data
.length
11755 - fragP
->tc_frag_data
.last_length
);
11757 /* Compute the relative address of the padding frag in the very
11758 first time where the BRANCH_PREFIX frag sizes are zero. */
11759 if (!fragP
->tc_frag_data
.padding_address
)
11760 fragP
->tc_frag_data
.padding_address
11761 = padding_fragP
->fr_address
- (fragP
->fr_address
- stretch
);
11763 /* First update the last length from the previous interation. */
11764 left_size
= fragP
->tc_frag_data
.prefix_length
;
11765 for (next_fragP
= fragP
;
11766 next_fragP
!= padding_fragP
;
11767 next_fragP
= next_fragP
->fr_next
)
11768 if (next_fragP
->fr_type
== rs_machine_dependent
11769 && (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
11774 int max
= next_fragP
->tc_frag_data
.max_bytes
;
11778 if (max
> left_size
)
11783 next_fragP
->tc_frag_data
.last_length
= size
;
11787 next_fragP
->tc_frag_data
.last_length
= 0;
11790 /* Check the padding size for the padding frag. */
11791 padding_size
= i386_branch_padding_size
11792 (padding_fragP
, (fragP
->fr_address
11793 + fragP
->tc_frag_data
.padding_address
));
11795 last_size
= fragP
->tc_frag_data
.prefix_length
;
11796 /* Check if there is change from the last interation. */
11797 if (padding_size
== last_size
)
11799 /* Update the expected address of the padding frag. */
11800 padding_fragP
->tc_frag_data
.padding_address
11801 = (fragP
->fr_address
+ padding_size
11802 + fragP
->tc_frag_data
.padding_address
);
11806 if (padding_size
> fragP
->tc_frag_data
.max_prefix_length
)
11808 /* No padding if there is no sufficient room. Clear the
11809 expected address of the padding frag. */
11810 padding_fragP
->tc_frag_data
.padding_address
= 0;
11814 /* Store the expected address of the padding frag. */
11815 padding_fragP
->tc_frag_data
.padding_address
11816 = (fragP
->fr_address
+ padding_size
11817 + fragP
->tc_frag_data
.padding_address
);
11819 fragP
->tc_frag_data
.prefix_length
= padding_size
;
11821 /* Update the length for the current interation. */
11822 left_size
= padding_size
;
11823 for (next_fragP
= fragP
;
11824 next_fragP
!= padding_fragP
;
11825 next_fragP
= next_fragP
->fr_next
)
11826 if (next_fragP
->fr_type
== rs_machine_dependent
11827 && (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
11832 int max
= next_fragP
->tc_frag_data
.max_bytes
;
11836 if (max
> left_size
)
11841 next_fragP
->tc_frag_data
.length
= size
;
11845 next_fragP
->tc_frag_data
.length
= 0;
11848 return (fragP
->tc_frag_data
.length
11849 - fragP
->tc_frag_data
.last_length
);
11851 return relax_frag (segment
, fragP
, stretch
);
11854 /* md_estimate_size_before_relax()
11856 Called just before relax() for rs_machine_dependent frags. The x86
11857 assembler uses these frags to handle variable size jump
11860 Any symbol that is now undefined will not become defined.
11861 Return the correct fr_subtype in the frag.
11862 Return the initial "guess for variable size of frag" to caller.
11863 The guess is actually the growth beyond the fixed part. Whatever
11864 we do to grow the fixed or variable part contributes to our
11868 md_estimate_size_before_relax (fragS
*fragP
, segT segment
)
11870 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
11871 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
11872 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
)
11874 i386_classify_machine_dependent_frag (fragP
);
11875 return fragP
->tc_frag_data
.length
;
11878 /* We've already got fragP->fr_subtype right; all we have to do is
11879 check for un-relaxable symbols. On an ELF system, we can't relax
11880 an externally visible symbol, because it may be overridden by a
11882 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
11883 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11885 && !elf_symbol_resolved_in_segment_p (fragP
->fr_symbol
,
11888 #if defined (OBJ_COFF) && defined (TE_PE)
11889 || (OUTPUT_FLAVOR
== bfd_target_coff_flavour
11890 && S_IS_WEAK (fragP
->fr_symbol
))
11894 /* Symbol is undefined in this segment, or we need to keep a
11895 reloc so that weak symbols can be overridden. */
11896 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
11897 enum bfd_reloc_code_real reloc_type
;
11898 unsigned char *opcode
;
11901 if (fragP
->fr_var
!= NO_RELOC
)
11902 reloc_type
= (enum bfd_reloc_code_real
) fragP
->fr_var
;
11903 else if (size
== 2)
11904 reloc_type
= BFD_RELOC_16_PCREL
;
11905 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11906 else if (need_plt32_p (fragP
->fr_symbol
))
11907 reloc_type
= BFD_RELOC_X86_64_PLT32
;
11910 reloc_type
= BFD_RELOC_32_PCREL
;
11912 old_fr_fix
= fragP
->fr_fix
;
11913 opcode
= (unsigned char *) fragP
->fr_opcode
;
11915 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
11918 /* Make jmp (0xeb) a (d)word displacement jump. */
11920 fragP
->fr_fix
+= size
;
11921 fix_new (fragP
, old_fr_fix
, size
,
11923 fragP
->fr_offset
, 1,
11929 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
11931 /* Negate the condition, and branch past an
11932 unconditional jump. */
11935 /* Insert an unconditional jump. */
11937 /* We added two extra opcode bytes, and have a two byte
11939 fragP
->fr_fix
+= 2 + 2;
11940 fix_new (fragP
, old_fr_fix
+ 2, 2,
11942 fragP
->fr_offset
, 1,
11946 /* Fall through. */
11949 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
11953 fragP
->fr_fix
+= 1;
11954 fixP
= fix_new (fragP
, old_fr_fix
, 1,
11956 fragP
->fr_offset
, 1,
11957 BFD_RELOC_8_PCREL
);
11958 fixP
->fx_signed
= 1;
11962 /* This changes the byte-displacement jump 0x7N
11963 to the (d)word-displacement jump 0x0f,0x8N. */
11964 opcode
[1] = opcode
[0] + 0x10;
11965 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
11966 /* We've added an opcode byte. */
11967 fragP
->fr_fix
+= 1 + size
;
11968 fix_new (fragP
, old_fr_fix
+ 1, size
,
11970 fragP
->fr_offset
, 1,
11975 BAD_CASE (fragP
->fr_subtype
);
11979 return fragP
->fr_fix
- old_fr_fix
;
11982 /* Guess size depending on current relax state. Initially the relax
11983 state will correspond to a short jump and we return 1, because
11984 the variable part of the frag (the branch offset) is one byte
11985 long. However, we can relax a section more than once and in that
11986 case we must either set fr_subtype back to the unrelaxed state,
11987 or return the value for the appropriate branch. */
11988 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
11991 /* Called after relax() is finished.
11993 In: Address of frag.
11994 fr_type == rs_machine_dependent.
11995 fr_subtype is what the address relaxed to.
11997 Out: Any fixSs and constants are set up.
11998 Caller will turn frag into a ".space 0". */
12001 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec ATTRIBUTE_UNUSED
,
12004 unsigned char *opcode
;
12005 unsigned char *where_to_put_displacement
= NULL
;
12006 offsetT target_address
;
12007 offsetT opcode_address
;
12008 unsigned int extension
= 0;
12009 offsetT displacement_from_opcode_start
;
12011 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
12012 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
12013 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
)
12015 /* Generate nop padding. */
12016 unsigned int size
= fragP
->tc_frag_data
.length
;
12019 if (size
> fragP
->tc_frag_data
.max_bytes
)
12025 const char *branch
= "branch";
12026 const char *prefix
= "";
12027 fragS
*padding_fragP
;
12028 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
)
12031 padding_fragP
= fragP
->tc_frag_data
.u
.padding_fragP
;
12032 switch (fragP
->tc_frag_data
.default_prefix
)
12037 case CS_PREFIX_OPCODE
:
12040 case DS_PREFIX_OPCODE
:
12043 case ES_PREFIX_OPCODE
:
12046 case FS_PREFIX_OPCODE
:
12049 case GS_PREFIX_OPCODE
:
12052 case SS_PREFIX_OPCODE
:
12057 msg
= _("%s:%u: add %d%s at 0x%llx to align "
12058 "%s within %d-byte boundary\n");
12060 msg
= _("%s:%u: add additional %d%s at 0x%llx to "
12061 "align %s within %d-byte boundary\n");
12065 padding_fragP
= fragP
;
12066 msg
= _("%s:%u: add %d%s-byte nop at 0x%llx to align "
12067 "%s within %d-byte boundary\n");
12071 switch (padding_fragP
->tc_frag_data
.branch_type
)
12073 case align_branch_jcc
:
12076 case align_branch_fused
:
12077 branch
= "fused jcc";
12079 case align_branch_jmp
:
12082 case align_branch_call
:
12085 case align_branch_indirect
:
12086 branch
= "indiret branch";
12088 case align_branch_ret
:
12095 fprintf (stdout
, msg
,
12096 fragP
->fr_file
, fragP
->fr_line
, size
, prefix
,
12097 (long long) fragP
->fr_address
, branch
,
12098 1 << align_branch_power
);
12100 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
)
12101 memset (fragP
->fr_opcode
,
12102 fragP
->tc_frag_data
.default_prefix
, size
);
12104 i386_generate_nops (fragP
, (char *) fragP
->fr_opcode
,
12106 fragP
->fr_fix
+= size
;
12111 opcode
= (unsigned char *) fragP
->fr_opcode
;
12113 /* Address we want to reach in file space. */
12114 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
12116 /* Address opcode resides at in file space. */
12117 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
12119 /* Displacement from opcode start to fill into instruction. */
12120 displacement_from_opcode_start
= target_address
- opcode_address
;
12122 if ((fragP
->fr_subtype
& BIG
) == 0)
12124 /* Don't have to change opcode. */
12125 extension
= 1; /* 1 opcode + 1 displacement */
12126 where_to_put_displacement
= &opcode
[1];
12130 if (no_cond_jump_promotion
12131 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
12132 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
12133 _("long jump required"));
12135 switch (fragP
->fr_subtype
)
12137 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
12138 extension
= 4; /* 1 opcode + 4 displacement */
12140 where_to_put_displacement
= &opcode
[1];
12143 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
12144 extension
= 2; /* 1 opcode + 2 displacement */
12146 where_to_put_displacement
= &opcode
[1];
12149 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
12150 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
12151 extension
= 5; /* 2 opcode + 4 displacement */
12152 opcode
[1] = opcode
[0] + 0x10;
12153 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
12154 where_to_put_displacement
= &opcode
[2];
12157 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
12158 extension
= 3; /* 2 opcode + 2 displacement */
12159 opcode
[1] = opcode
[0] + 0x10;
12160 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
12161 where_to_put_displacement
= &opcode
[2];
12164 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
12169 where_to_put_displacement
= &opcode
[3];
12173 BAD_CASE (fragP
->fr_subtype
);
12178 /* If size if less then four we are sure that the operand fits,
12179 but if it's 4, then it could be that the displacement is larger
12181 if (DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
) == 4
12183 && ((addressT
) (displacement_from_opcode_start
- extension
12184 + ((addressT
) 1 << 31))
12185 > (((addressT
) 2 << 31) - 1)))
12187 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
12188 _("jump target out of range"));
12189 /* Make us emit 0. */
12190 displacement_from_opcode_start
= extension
;
12192 /* Now put displacement after opcode. */
12193 md_number_to_chars ((char *) where_to_put_displacement
,
12194 (valueT
) (displacement_from_opcode_start
- extension
),
12195 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
12196 fragP
->fr_fix
+= extension
;
12199 /* Apply a fixup (fixP) to segment data, once it has been determined
12200 by our caller that we have all the info we need to fix it up.
12202 Parameter valP is the pointer to the value of the bits.
12204 On the 386, immediates, displacements, and data pointers are all in
12205 the same (little-endian) format, so we don't need to care about which
12206 we are handling. */
12209 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
12211 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
12212 valueT value
= *valP
;
12214 #if !defined (TE_Mach)
12215 if (fixP
->fx_pcrel
)
12217 switch (fixP
->fx_r_type
)
12223 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
12226 case BFD_RELOC_X86_64_32S
:
12227 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
12230 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
12233 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
12238 if (fixP
->fx_addsy
!= NULL
12239 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
12240 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
12241 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
12242 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
12243 && !use_rela_relocations
)
12245 /* This is a hack. There should be a better way to handle this.
12246 This covers for the fact that bfd_install_relocation will
12247 subtract the current location (for partial_inplace, PC relative
12248 relocations); see more below. */
12252 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
12255 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
12257 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12260 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
12262 if ((sym_seg
== seg
12263 || (symbol_section_p (fixP
->fx_addsy
)
12264 && sym_seg
!= absolute_section
))
12265 && !generic_force_reloc (fixP
))
12267 /* Yes, we add the values in twice. This is because
12268 bfd_install_relocation subtracts them out again. I think
12269 bfd_install_relocation is broken, but I don't dare change
12271 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
12275 #if defined (OBJ_COFF) && defined (TE_PE)
12276 /* For some reason, the PE format does not store a
12277 section address offset for a PC relative symbol. */
12278 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
12279 || S_IS_WEAK (fixP
->fx_addsy
))
12280 value
+= md_pcrel_from (fixP
);
12283 #if defined (OBJ_COFF) && defined (TE_PE)
12284 if (fixP
->fx_addsy
!= NULL
12285 && S_IS_WEAK (fixP
->fx_addsy
)
12286 /* PR 16858: Do not modify weak function references. */
12287 && ! fixP
->fx_pcrel
)
12289 #if !defined (TE_PEP)
12290 /* For x86 PE weak function symbols are neither PC-relative
12291 nor do they set S_IS_FUNCTION. So the only reliable way
12292 to detect them is to check the flags of their containing
12294 if (S_GET_SEGMENT (fixP
->fx_addsy
) != NULL
12295 && S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_CODE
)
12299 value
-= S_GET_VALUE (fixP
->fx_addsy
);
12303 /* Fix a few things - the dynamic linker expects certain values here,
12304 and we must not disappoint it. */
12305 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12306 if (IS_ELF
&& fixP
->fx_addsy
)
12307 switch (fixP
->fx_r_type
)
12309 case BFD_RELOC_386_PLT32
:
12310 case BFD_RELOC_X86_64_PLT32
:
12311 /* Make the jump instruction point to the address of the operand.
12312 At runtime we merely add the offset to the actual PLT entry.
12313 NB: Subtract the offset size only for jump instructions. */
12314 if (fixP
->fx_pcrel
)
12318 case BFD_RELOC_386_TLS_GD
:
12319 case BFD_RELOC_386_TLS_LDM
:
12320 case BFD_RELOC_386_TLS_IE_32
:
12321 case BFD_RELOC_386_TLS_IE
:
12322 case BFD_RELOC_386_TLS_GOTIE
:
12323 case BFD_RELOC_386_TLS_GOTDESC
:
12324 case BFD_RELOC_X86_64_TLSGD
:
12325 case BFD_RELOC_X86_64_TLSLD
:
12326 case BFD_RELOC_X86_64_GOTTPOFF
:
12327 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
12328 value
= 0; /* Fully resolved at runtime. No addend. */
12330 case BFD_RELOC_386_TLS_LE
:
12331 case BFD_RELOC_386_TLS_LDO_32
:
12332 case BFD_RELOC_386_TLS_LE_32
:
12333 case BFD_RELOC_X86_64_DTPOFF32
:
12334 case BFD_RELOC_X86_64_DTPOFF64
:
12335 case BFD_RELOC_X86_64_TPOFF32
:
12336 case BFD_RELOC_X86_64_TPOFF64
:
12337 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
12340 case BFD_RELOC_386_TLS_DESC_CALL
:
12341 case BFD_RELOC_X86_64_TLSDESC_CALL
:
12342 value
= 0; /* Fully resolved at runtime. No addend. */
12343 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
12347 case BFD_RELOC_VTABLE_INHERIT
:
12348 case BFD_RELOC_VTABLE_ENTRY
:
12355 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
12357 #endif /* !defined (TE_Mach) */
12359 /* Are we finished with this relocation now? */
12360 if (fixP
->fx_addsy
== NULL
)
12362 #if defined (OBJ_COFF) && defined (TE_PE)
12363 else if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
12366 /* Remember value for tc_gen_reloc. */
12367 fixP
->fx_addnumber
= value
;
12368 /* Clear out the frag for now. */
12372 else if (use_rela_relocations
)
12374 fixP
->fx_no_overflow
= 1;
12375 /* Remember value for tc_gen_reloc. */
12376 fixP
->fx_addnumber
= value
;
12380 md_number_to_chars (p
, value
, fixP
->fx_size
);
12384 md_atof (int type
, char *litP
, int *sizeP
)
12386 /* This outputs the LITTLENUMs in REVERSE order;
12387 in accord with the bigendian 386. */
12388 return ieee_md_atof (type
, litP
, sizeP
, FALSE
);
12391 static char output_invalid_buf
[sizeof (unsigned char) * 2 + 6];
12394 output_invalid (int c
)
12397 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
12400 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
12401 "(0x%x)", (unsigned char) c
);
12402 return output_invalid_buf
;
12405 /* Verify that @r can be used in the current context. */
12407 static bfd_boolean
check_register (const reg_entry
*r
)
12409 if (allow_pseudo_reg
)
12412 if (operand_type_all_zero (&r
->reg_type
))
12415 if ((r
->reg_type
.bitfield
.dword
12416 || (r
->reg_type
.bitfield
.class == SReg
&& r
->reg_num
> 3)
12417 || r
->reg_type
.bitfield
.class == RegCR
12418 || r
->reg_type
.bitfield
.class == RegDR
)
12419 && !cpu_arch_flags
.bitfield
.cpui386
)
12422 if (r
->reg_type
.bitfield
.class == RegTR
12423 && (flag_code
== CODE_64BIT
12424 || !cpu_arch_flags
.bitfield
.cpui386
12425 || cpu_arch_isa_flags
.bitfield
.cpui586
12426 || cpu_arch_isa_flags
.bitfield
.cpui686
))
12429 if (r
->reg_type
.bitfield
.class == RegMMX
&& !cpu_arch_flags
.bitfield
.cpummx
)
12432 if (!cpu_arch_flags
.bitfield
.cpuavx512f
)
12434 if (r
->reg_type
.bitfield
.zmmword
12435 || r
->reg_type
.bitfield
.class == RegMask
)
12438 if (!cpu_arch_flags
.bitfield
.cpuavx
)
12440 if (r
->reg_type
.bitfield
.ymmword
)
12443 if (!cpu_arch_flags
.bitfield
.cpusse
&& r
->reg_type
.bitfield
.xmmword
)
12448 if (r
->reg_type
.bitfield
.class == RegBND
&& !cpu_arch_flags
.bitfield
.cpumpx
)
12451 /* Don't allow fake index register unless allow_index_reg isn't 0. */
12452 if (!allow_index_reg
&& r
->reg_num
== RegIZ
)
12455 /* Upper 16 vector registers are only available with VREX in 64bit
12456 mode, and require EVEX encoding. */
12457 if (r
->reg_flags
& RegVRex
)
12459 if (!cpu_arch_flags
.bitfield
.cpuavx512f
12460 || flag_code
!= CODE_64BIT
)
12463 if (i
.vec_encoding
== vex_encoding_default
)
12464 i
.vec_encoding
= vex_encoding_evex
;
12465 else if (i
.vec_encoding
!= vex_encoding_evex
)
12466 i
.vec_encoding
= vex_encoding_error
;
12469 if (((r
->reg_flags
& (RegRex64
| RegRex
)) || r
->reg_type
.bitfield
.qword
)
12470 && (!cpu_arch_flags
.bitfield
.cpulm
|| r
->reg_type
.bitfield
.class != RegCR
)
12471 && flag_code
!= CODE_64BIT
)
12474 if (r
->reg_type
.bitfield
.class == SReg
&& r
->reg_num
== RegFlat
12481 /* REG_STRING starts *before* REGISTER_PREFIX. */
12483 static const reg_entry
*
12484 parse_real_register (char *reg_string
, char **end_op
)
12486 char *s
= reg_string
;
12488 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
12489 const reg_entry
*r
;
12491 /* Skip possible REGISTER_PREFIX and possible whitespace. */
12492 if (*s
== REGISTER_PREFIX
)
12495 if (is_space_char (*s
))
12498 p
= reg_name_given
;
12499 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
12501 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
12502 return (const reg_entry
*) NULL
;
12506 /* For naked regs, make sure that we are not dealing with an identifier.
12507 This prevents confusing an identifier like `eax_var' with register
12509 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
12510 return (const reg_entry
*) NULL
;
12514 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
12516 /* Handle floating point regs, allowing spaces in the (i) part. */
12517 if (r
== i386_regtab
/* %st is first entry of table */)
12519 if (!cpu_arch_flags
.bitfield
.cpu8087
12520 && !cpu_arch_flags
.bitfield
.cpu287
12521 && !cpu_arch_flags
.bitfield
.cpu387
12522 && !allow_pseudo_reg
)
12523 return (const reg_entry
*) NULL
;
12525 if (is_space_char (*s
))
12530 if (is_space_char (*s
))
12532 if (*s
>= '0' && *s
<= '7')
12534 int fpr
= *s
- '0';
12536 if (is_space_char (*s
))
12541 r
= (const reg_entry
*) hash_find (reg_hash
, "st(0)");
12546 /* We have "%st(" then garbage. */
12547 return (const reg_entry
*) NULL
;
12551 return r
&& check_register (r
) ? r
: NULL
;
12554 /* REG_STRING starts *before* REGISTER_PREFIX. */
12556 static const reg_entry
*
12557 parse_register (char *reg_string
, char **end_op
)
12559 const reg_entry
*r
;
12561 if (*reg_string
== REGISTER_PREFIX
|| allow_naked_reg
)
12562 r
= parse_real_register (reg_string
, end_op
);
12567 char *save
= input_line_pointer
;
12571 input_line_pointer
= reg_string
;
12572 c
= get_symbol_name (®_string
);
12573 symbolP
= symbol_find (reg_string
);
12574 if (symbolP
&& S_GET_SEGMENT (symbolP
) == reg_section
)
12576 const expressionS
*e
= symbol_get_value_expression (symbolP
);
12578 know (e
->X_op
== O_register
);
12579 know (e
->X_add_number
>= 0
12580 && (valueT
) e
->X_add_number
< i386_regtab_size
);
12581 r
= i386_regtab
+ e
->X_add_number
;
12582 if (!check_register (r
))
12584 as_bad (_("register '%s%s' cannot be used here"),
12585 register_prefix
, r
->reg_name
);
12588 *end_op
= input_line_pointer
;
12590 *input_line_pointer
= c
;
12591 input_line_pointer
= save
;
12597 i386_parse_name (char *name
, expressionS
*e
, char *nextcharP
)
12599 const reg_entry
*r
;
12600 char *end
= input_line_pointer
;
12603 r
= parse_register (name
, &input_line_pointer
);
12604 if (r
&& end
<= input_line_pointer
)
12606 *nextcharP
= *input_line_pointer
;
12607 *input_line_pointer
= 0;
12610 e
->X_op
= O_register
;
12611 e
->X_add_number
= r
- i386_regtab
;
12614 e
->X_op
= O_illegal
;
12617 input_line_pointer
= end
;
12619 return intel_syntax
? i386_intel_parse_name (name
, e
) : 0;
12623 md_operand (expressionS
*e
)
12626 const reg_entry
*r
;
12628 switch (*input_line_pointer
)
12630 case REGISTER_PREFIX
:
12631 r
= parse_real_register (input_line_pointer
, &end
);
12634 e
->X_op
= O_register
;
12635 e
->X_add_number
= r
- i386_regtab
;
12636 input_line_pointer
= end
;
12641 gas_assert (intel_syntax
);
12642 end
= input_line_pointer
++;
12644 if (*input_line_pointer
== ']')
12646 ++input_line_pointer
;
12647 e
->X_op_symbol
= make_expr_symbol (e
);
12648 e
->X_add_symbol
= NULL
;
12649 e
->X_add_number
= 0;
12654 e
->X_op
= O_absent
;
12655 input_line_pointer
= end
;
12662 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12663 const char *md_shortopts
= "kVQ:sqnO::";
12665 const char *md_shortopts
= "qnO::";
12668 #define OPTION_32 (OPTION_MD_BASE + 0)
12669 #define OPTION_64 (OPTION_MD_BASE + 1)
12670 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
12671 #define OPTION_MARCH (OPTION_MD_BASE + 3)
12672 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
12673 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
12674 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
12675 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
12676 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
12677 #define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 9)
12678 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
12679 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
12680 #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
12681 #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
12682 #define OPTION_X32 (OPTION_MD_BASE + 14)
12683 #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
12684 #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
12685 #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
12686 #define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
12687 #define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
12688 #define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
12689 #define OPTION_MSHARED (OPTION_MD_BASE + 21)
12690 #define OPTION_MAMD64 (OPTION_MD_BASE + 22)
12691 #define OPTION_MINTEL64 (OPTION_MD_BASE + 23)
12692 #define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24)
12693 #define OPTION_X86_USED_NOTE (OPTION_MD_BASE + 25)
12694 #define OPTION_MVEXWIG (OPTION_MD_BASE + 26)
12695 #define OPTION_MALIGN_BRANCH_BOUNDARY (OPTION_MD_BASE + 27)
12696 #define OPTION_MALIGN_BRANCH_PREFIX_SIZE (OPTION_MD_BASE + 28)
12697 #define OPTION_MALIGN_BRANCH (OPTION_MD_BASE + 29)
12698 #define OPTION_MBRANCHES_WITH_32B_BOUNDARIES (OPTION_MD_BASE + 30)
12699 #define OPTION_MLFENCE_AFTER_LOAD (OPTION_MD_BASE + 31)
12700 #define OPTION_MLFENCE_BEFORE_INDIRECT_BRANCH (OPTION_MD_BASE + 32)
12701 #define OPTION_MLFENCE_BEFORE_RET (OPTION_MD_BASE + 33)
12703 struct option md_longopts
[] =
12705 {"32", no_argument
, NULL
, OPTION_32
},
12706 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
12707 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
12708 {"64", no_argument
, NULL
, OPTION_64
},
12710 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12711 {"x32", no_argument
, NULL
, OPTION_X32
},
12712 {"mshared", no_argument
, NULL
, OPTION_MSHARED
},
12713 {"mx86-used-note", required_argument
, NULL
, OPTION_X86_USED_NOTE
},
12715 {"divide", no_argument
, NULL
, OPTION_DIVIDE
},
12716 {"march", required_argument
, NULL
, OPTION_MARCH
},
12717 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
12718 {"mmnemonic", required_argument
, NULL
, OPTION_MMNEMONIC
},
12719 {"msyntax", required_argument
, NULL
, OPTION_MSYNTAX
},
12720 {"mindex-reg", no_argument
, NULL
, OPTION_MINDEX_REG
},
12721 {"mnaked-reg", no_argument
, NULL
, OPTION_MNAKED_REG
},
12722 {"msse2avx", no_argument
, NULL
, OPTION_MSSE2AVX
},
12723 {"msse-check", required_argument
, NULL
, OPTION_MSSE_CHECK
},
12724 {"moperand-check", required_argument
, NULL
, OPTION_MOPERAND_CHECK
},
12725 {"mavxscalar", required_argument
, NULL
, OPTION_MAVXSCALAR
},
12726 {"mvexwig", required_argument
, NULL
, OPTION_MVEXWIG
},
12727 {"madd-bnd-prefix", no_argument
, NULL
, OPTION_MADD_BND_PREFIX
},
12728 {"mevexlig", required_argument
, NULL
, OPTION_MEVEXLIG
},
12729 {"mevexwig", required_argument
, NULL
, OPTION_MEVEXWIG
},
12730 # if defined (TE_PE) || defined (TE_PEP)
12731 {"mbig-obj", no_argument
, NULL
, OPTION_MBIG_OBJ
},
12733 {"momit-lock-prefix", required_argument
, NULL
, OPTION_MOMIT_LOCK_PREFIX
},
12734 {"mfence-as-lock-add", required_argument
, NULL
, OPTION_MFENCE_AS_LOCK_ADD
},
12735 {"mrelax-relocations", required_argument
, NULL
, OPTION_MRELAX_RELOCATIONS
},
12736 {"mevexrcig", required_argument
, NULL
, OPTION_MEVEXRCIG
},
12737 {"malign-branch-boundary", required_argument
, NULL
, OPTION_MALIGN_BRANCH_BOUNDARY
},
12738 {"malign-branch-prefix-size", required_argument
, NULL
, OPTION_MALIGN_BRANCH_PREFIX_SIZE
},
12739 {"malign-branch", required_argument
, NULL
, OPTION_MALIGN_BRANCH
},
12740 {"mbranches-within-32B-boundaries", no_argument
, NULL
, OPTION_MBRANCHES_WITH_32B_BOUNDARIES
},
12741 {"mlfence-after-load", required_argument
, NULL
, OPTION_MLFENCE_AFTER_LOAD
},
12742 {"mlfence-before-indirect-branch", required_argument
, NULL
,
12743 OPTION_MLFENCE_BEFORE_INDIRECT_BRANCH
},
12744 {"mlfence-before-ret", required_argument
, NULL
, OPTION_MLFENCE_BEFORE_RET
},
12745 {"mamd64", no_argument
, NULL
, OPTION_MAMD64
},
12746 {"mintel64", no_argument
, NULL
, OPTION_MINTEL64
},
12747 {NULL
, no_argument
, NULL
, 0}
12749 size_t md_longopts_size
= sizeof (md_longopts
);
12752 md_parse_option (int c
, const char *arg
)
12755 char *arch
, *next
, *saved
, *type
;
12760 optimize_align_code
= 0;
12764 quiet_warnings
= 1;
12767 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12768 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
12769 should be emitted or not. FIXME: Not implemented. */
12771 if ((arg
[0] != 'y' && arg
[0] != 'n') || arg
[1])
12775 /* -V: SVR4 argument to print version ID. */
12777 print_version_id ();
12780 /* -k: Ignore for FreeBSD compatibility. */
12785 /* -s: On i386 Solaris, this tells the native assembler to use
12786 .stab instead of .stab.excl. We always use .stab anyhow. */
12789 case OPTION_MSHARED
:
12793 case OPTION_X86_USED_NOTE
:
12794 if (strcasecmp (arg
, "yes") == 0)
12796 else if (strcasecmp (arg
, "no") == 0)
12799 as_fatal (_("invalid -mx86-used-note= option: `%s'"), arg
);
12804 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
12805 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
12808 const char **list
, **l
;
12810 list
= bfd_target_list ();
12811 for (l
= list
; *l
!= NULL
; l
++)
12812 if (CONST_STRNEQ (*l
, "elf64-x86-64")
12813 || strcmp (*l
, "coff-x86-64") == 0
12814 || strcmp (*l
, "pe-x86-64") == 0
12815 || strcmp (*l
, "pei-x86-64") == 0
12816 || strcmp (*l
, "mach-o-x86-64") == 0)
12818 default_arch
= "x86_64";
12822 as_fatal (_("no compiled in support for x86_64"));
12828 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12832 const char **list
, **l
;
12834 list
= bfd_target_list ();
12835 for (l
= list
; *l
!= NULL
; l
++)
12836 if (CONST_STRNEQ (*l
, "elf32-x86-64"))
12838 default_arch
= "x86_64:32";
12842 as_fatal (_("no compiled in support for 32bit x86_64"));
12846 as_fatal (_("32bit x86_64 is only supported for ELF"));
12851 default_arch
= "i386";
12854 case OPTION_DIVIDE
:
12855 #ifdef SVR4_COMMENT_CHARS
12860 n
= XNEWVEC (char, strlen (i386_comment_chars
) + 1);
12862 for (s
= i386_comment_chars
; *s
!= '\0'; s
++)
12866 i386_comment_chars
= n
;
12872 saved
= xstrdup (arg
);
12874 /* Allow -march=+nosse. */
12880 as_fatal (_("invalid -march= option: `%s'"), arg
);
12881 next
= strchr (arch
, '+');
12884 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
12886 if (strcmp (arch
, cpu_arch
[j
].name
) == 0)
12889 if (! cpu_arch
[j
].flags
.bitfield
.cpui386
)
12892 cpu_arch_name
= cpu_arch
[j
].name
;
12893 cpu_sub_arch_name
= NULL
;
12894 cpu_arch_flags
= cpu_arch
[j
].flags
;
12895 cpu_arch_isa
= cpu_arch
[j
].type
;
12896 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
12897 if (!cpu_arch_tune_set
)
12899 cpu_arch_tune
= cpu_arch_isa
;
12900 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
12904 else if (*cpu_arch
[j
].name
== '.'
12905 && strcmp (arch
, cpu_arch
[j
].name
+ 1) == 0)
12907 /* ISA extension. */
12908 i386_cpu_flags flags
;
12910 flags
= cpu_flags_or (cpu_arch_flags
,
12911 cpu_arch
[j
].flags
);
12913 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
12915 if (cpu_sub_arch_name
)
12917 char *name
= cpu_sub_arch_name
;
12918 cpu_sub_arch_name
= concat (name
,
12920 (const char *) NULL
);
12924 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
12925 cpu_arch_flags
= flags
;
12926 cpu_arch_isa_flags
= flags
;
12930 = cpu_flags_or (cpu_arch_isa_flags
,
12931 cpu_arch
[j
].flags
);
12936 if (j
>= ARRAY_SIZE (cpu_arch
))
12938 /* Disable an ISA extension. */
12939 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
12940 if (strcmp (arch
, cpu_noarch
[j
].name
) == 0)
12942 i386_cpu_flags flags
;
12944 flags
= cpu_flags_and_not (cpu_arch_flags
,
12945 cpu_noarch
[j
].flags
);
12946 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
12948 if (cpu_sub_arch_name
)
12950 char *name
= cpu_sub_arch_name
;
12951 cpu_sub_arch_name
= concat (arch
,
12952 (const char *) NULL
);
12956 cpu_sub_arch_name
= xstrdup (arch
);
12957 cpu_arch_flags
= flags
;
12958 cpu_arch_isa_flags
= flags
;
12963 if (j
>= ARRAY_SIZE (cpu_noarch
))
12964 j
= ARRAY_SIZE (cpu_arch
);
12967 if (j
>= ARRAY_SIZE (cpu_arch
))
12968 as_fatal (_("invalid -march= option: `%s'"), arg
);
12972 while (next
!= NULL
);
12978 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
12979 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
12981 if (strcmp (arg
, cpu_arch
[j
].name
) == 0)
12983 cpu_arch_tune_set
= 1;
12984 cpu_arch_tune
= cpu_arch
[j
].type
;
12985 cpu_arch_tune_flags
= cpu_arch
[j
].flags
;
12989 if (j
>= ARRAY_SIZE (cpu_arch
))
12990 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
12993 case OPTION_MMNEMONIC
:
12994 if (strcasecmp (arg
, "att") == 0)
12995 intel_mnemonic
= 0;
12996 else if (strcasecmp (arg
, "intel") == 0)
12997 intel_mnemonic
= 1;
12999 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg
);
13002 case OPTION_MSYNTAX
:
13003 if (strcasecmp (arg
, "att") == 0)
13005 else if (strcasecmp (arg
, "intel") == 0)
13008 as_fatal (_("invalid -msyntax= option: `%s'"), arg
);
13011 case OPTION_MINDEX_REG
:
13012 allow_index_reg
= 1;
13015 case OPTION_MNAKED_REG
:
13016 allow_naked_reg
= 1;
13019 case OPTION_MSSE2AVX
:
13023 case OPTION_MSSE_CHECK
:
13024 if (strcasecmp (arg
, "error") == 0)
13025 sse_check
= check_error
;
13026 else if (strcasecmp (arg
, "warning") == 0)
13027 sse_check
= check_warning
;
13028 else if (strcasecmp (arg
, "none") == 0)
13029 sse_check
= check_none
;
13031 as_fatal (_("invalid -msse-check= option: `%s'"), arg
);
13034 case OPTION_MOPERAND_CHECK
:
13035 if (strcasecmp (arg
, "error") == 0)
13036 operand_check
= check_error
;
13037 else if (strcasecmp (arg
, "warning") == 0)
13038 operand_check
= check_warning
;
13039 else if (strcasecmp (arg
, "none") == 0)
13040 operand_check
= check_none
;
13042 as_fatal (_("invalid -moperand-check= option: `%s'"), arg
);
13045 case OPTION_MAVXSCALAR
:
13046 if (strcasecmp (arg
, "128") == 0)
13047 avxscalar
= vex128
;
13048 else if (strcasecmp (arg
, "256") == 0)
13049 avxscalar
= vex256
;
13051 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg
);
13054 case OPTION_MVEXWIG
:
13055 if (strcmp (arg
, "0") == 0)
13057 else if (strcmp (arg
, "1") == 0)
13060 as_fatal (_("invalid -mvexwig= option: `%s'"), arg
);
13063 case OPTION_MADD_BND_PREFIX
:
13064 add_bnd_prefix
= 1;
13067 case OPTION_MEVEXLIG
:
13068 if (strcmp (arg
, "128") == 0)
13069 evexlig
= evexl128
;
13070 else if (strcmp (arg
, "256") == 0)
13071 evexlig
= evexl256
;
13072 else if (strcmp (arg
, "512") == 0)
13073 evexlig
= evexl512
;
13075 as_fatal (_("invalid -mevexlig= option: `%s'"), arg
);
13078 case OPTION_MEVEXRCIG
:
13079 if (strcmp (arg
, "rne") == 0)
13081 else if (strcmp (arg
, "rd") == 0)
13083 else if (strcmp (arg
, "ru") == 0)
13085 else if (strcmp (arg
, "rz") == 0)
13088 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg
);
13091 case OPTION_MEVEXWIG
:
13092 if (strcmp (arg
, "0") == 0)
13094 else if (strcmp (arg
, "1") == 0)
13097 as_fatal (_("invalid -mevexwig= option: `%s'"), arg
);
13100 # if defined (TE_PE) || defined (TE_PEP)
13101 case OPTION_MBIG_OBJ
:
13106 case OPTION_MOMIT_LOCK_PREFIX
:
13107 if (strcasecmp (arg
, "yes") == 0)
13108 omit_lock_prefix
= 1;
13109 else if (strcasecmp (arg
, "no") == 0)
13110 omit_lock_prefix
= 0;
13112 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg
);
13115 case OPTION_MFENCE_AS_LOCK_ADD
:
13116 if (strcasecmp (arg
, "yes") == 0)
13118 else if (strcasecmp (arg
, "no") == 0)
13121 as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg
);
13124 case OPTION_MLFENCE_AFTER_LOAD
:
13125 if (strcasecmp (arg
, "yes") == 0)
13126 lfence_after_load
= 1;
13127 else if (strcasecmp (arg
, "no") == 0)
13128 lfence_after_load
= 0;
13130 as_fatal (_("invalid -mlfence-after-load= option: `%s'"), arg
);
13133 case OPTION_MLFENCE_BEFORE_INDIRECT_BRANCH
:
13134 if (strcasecmp (arg
, "all") == 0)
13136 lfence_before_indirect_branch
= lfence_branch_all
;
13137 if (lfence_before_ret
== lfence_before_ret_none
)
13138 lfence_before_ret
= lfence_before_ret_shl
;
13140 else if (strcasecmp (arg
, "memory") == 0)
13141 lfence_before_indirect_branch
= lfence_branch_memory
;
13142 else if (strcasecmp (arg
, "register") == 0)
13143 lfence_before_indirect_branch
= lfence_branch_register
;
13144 else if (strcasecmp (arg
, "none") == 0)
13145 lfence_before_indirect_branch
= lfence_branch_none
;
13147 as_fatal (_("invalid -mlfence-before-indirect-branch= option: `%s'"),
13151 case OPTION_MLFENCE_BEFORE_RET
:
13152 if (strcasecmp (arg
, "or") == 0)
13153 lfence_before_ret
= lfence_before_ret_or
;
13154 else if (strcasecmp (arg
, "not") == 0)
13155 lfence_before_ret
= lfence_before_ret_not
;
13156 else if (strcasecmp (arg
, "shl") == 0 || strcasecmp (arg
, "yes") == 0)
13157 lfence_before_ret
= lfence_before_ret_shl
;
13158 else if (strcasecmp (arg
, "none") == 0)
13159 lfence_before_ret
= lfence_before_ret_none
;
13161 as_fatal (_("invalid -mlfence-before-ret= option: `%s'"),
13165 case OPTION_MRELAX_RELOCATIONS
:
13166 if (strcasecmp (arg
, "yes") == 0)
13167 generate_relax_relocations
= 1;
13168 else if (strcasecmp (arg
, "no") == 0)
13169 generate_relax_relocations
= 0;
13171 as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg
);
13174 case OPTION_MALIGN_BRANCH_BOUNDARY
:
13177 long int align
= strtoul (arg
, &end
, 0);
13182 align_branch_power
= 0;
13185 else if (align
>= 16)
13188 for (align_power
= 0;
13190 align
>>= 1, align_power
++)
13192 /* Limit alignment power to 31. */
13193 if (align
== 1 && align_power
< 32)
13195 align_branch_power
= align_power
;
13200 as_fatal (_("invalid -malign-branch-boundary= value: %s"), arg
);
13204 case OPTION_MALIGN_BRANCH_PREFIX_SIZE
:
13207 int align
= strtoul (arg
, &end
, 0);
13208 /* Some processors only support 5 prefixes. */
13209 if (*end
== '\0' && align
>= 0 && align
< 6)
13211 align_branch_prefix_size
= align
;
13214 as_fatal (_("invalid -malign-branch-prefix-size= value: %s"),
13219 case OPTION_MALIGN_BRANCH
:
13221 saved
= xstrdup (arg
);
13225 next
= strchr (type
, '+');
13228 if (strcasecmp (type
, "jcc") == 0)
13229 align_branch
|= align_branch_jcc_bit
;
13230 else if (strcasecmp (type
, "fused") == 0)
13231 align_branch
|= align_branch_fused_bit
;
13232 else if (strcasecmp (type
, "jmp") == 0)
13233 align_branch
|= align_branch_jmp_bit
;
13234 else if (strcasecmp (type
, "call") == 0)
13235 align_branch
|= align_branch_call_bit
;
13236 else if (strcasecmp (type
, "ret") == 0)
13237 align_branch
|= align_branch_ret_bit
;
13238 else if (strcasecmp (type
, "indirect") == 0)
13239 align_branch
|= align_branch_indirect_bit
;
13241 as_fatal (_("invalid -malign-branch= option: `%s'"), arg
);
13244 while (next
!= NULL
);
13248 case OPTION_MBRANCHES_WITH_32B_BOUNDARIES
:
13249 align_branch_power
= 5;
13250 align_branch_prefix_size
= 5;
13251 align_branch
= (align_branch_jcc_bit
13252 | align_branch_fused_bit
13253 | align_branch_jmp_bit
);
13256 case OPTION_MAMD64
:
13260 case OPTION_MINTEL64
:
13268 /* Turn off -Os. */
13269 optimize_for_space
= 0;
13271 else if (*arg
== 's')
13273 optimize_for_space
= 1;
13274 /* Turn on all encoding optimizations. */
13275 optimize
= INT_MAX
;
13279 optimize
= atoi (arg
);
13280 /* Turn off -Os. */
13281 optimize_for_space
= 0;
13291 #define MESSAGE_TEMPLATE \
13295 output_message (FILE *stream
, char *p
, char *message
, char *start
,
13296 int *left_p
, const char *name
, int len
)
13298 int size
= sizeof (MESSAGE_TEMPLATE
);
13299 int left
= *left_p
;
13301 /* Reserve 2 spaces for ", " or ",\0" */
13304 /* Check if there is any room. */
13312 p
= mempcpy (p
, name
, len
);
13316 /* Output the current message now and start a new one. */
13319 fprintf (stream
, "%s\n", message
);
13321 left
= size
- (start
- message
) - len
- 2;
13323 gas_assert (left
>= 0);
13325 p
= mempcpy (p
, name
, len
);
13333 show_arch (FILE *stream
, int ext
, int check
)
13335 static char message
[] = MESSAGE_TEMPLATE
;
13336 char *start
= message
+ 27;
13338 int size
= sizeof (MESSAGE_TEMPLATE
);
13345 left
= size
- (start
- message
);
13346 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
13348 /* Should it be skipped? */
13349 if (cpu_arch
[j
].skip
)
13352 name
= cpu_arch
[j
].name
;
13353 len
= cpu_arch
[j
].len
;
13356 /* It is an extension. Skip if we aren't asked to show it. */
13367 /* It is an processor. Skip if we show only extension. */
13370 else if (check
&& ! cpu_arch
[j
].flags
.bitfield
.cpui386
)
13372 /* It is an impossible processor - skip. */
13376 p
= output_message (stream
, p
, message
, start
, &left
, name
, len
);
13379 /* Display disabled extensions. */
13381 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
13383 name
= cpu_noarch
[j
].name
;
13384 len
= cpu_noarch
[j
].len
;
13385 p
= output_message (stream
, p
, message
, start
, &left
, name
,
13390 fprintf (stream
, "%s\n", message
);
13394 md_show_usage (FILE *stream
)
13396 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13397 fprintf (stream
, _("\
13398 -Qy, -Qn ignored\n\
13399 -V print assembler version number\n\
13402 fprintf (stream
, _("\
13403 -n Do not optimize code alignment\n\
13404 -q quieten some warnings\n"));
13405 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13406 fprintf (stream
, _("\
13409 #if defined BFD64 && (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
13410 || defined (TE_PE) || defined (TE_PEP))
13411 fprintf (stream
, _("\
13412 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
13414 #ifdef SVR4_COMMENT_CHARS
13415 fprintf (stream
, _("\
13416 --divide do not treat `/' as a comment character\n"));
13418 fprintf (stream
, _("\
13419 --divide ignored\n"));
13421 fprintf (stream
, _("\
13422 -march=CPU[,+EXTENSION...]\n\
13423 generate code for CPU and EXTENSION, CPU is one of:\n"));
13424 show_arch (stream
, 0, 1);
13425 fprintf (stream
, _("\
13426 EXTENSION is combination of:\n"));
13427 show_arch (stream
, 1, 0);
13428 fprintf (stream
, _("\
13429 -mtune=CPU optimize for CPU, CPU is one of:\n"));
13430 show_arch (stream
, 0, 0);
13431 fprintf (stream
, _("\
13432 -msse2avx encode SSE instructions with VEX prefix\n"));
13433 fprintf (stream
, _("\
13434 -msse-check=[none|error|warning] (default: warning)\n\
13435 check SSE instructions\n"));
13436 fprintf (stream
, _("\
13437 -moperand-check=[none|error|warning] (default: warning)\n\
13438 check operand combinations for validity\n"));
13439 fprintf (stream
, _("\
13440 -mavxscalar=[128|256] (default: 128)\n\
13441 encode scalar AVX instructions with specific vector\n\
13443 fprintf (stream
, _("\
13444 -mvexwig=[0|1] (default: 0)\n\
13445 encode VEX instructions with specific VEX.W value\n\
13446 for VEX.W bit ignored instructions\n"));
13447 fprintf (stream
, _("\
13448 -mevexlig=[128|256|512] (default: 128)\n\
13449 encode scalar EVEX instructions with specific vector\n\
13451 fprintf (stream
, _("\
13452 -mevexwig=[0|1] (default: 0)\n\
13453 encode EVEX instructions with specific EVEX.W value\n\
13454 for EVEX.W bit ignored instructions\n"));
13455 fprintf (stream
, _("\
13456 -mevexrcig=[rne|rd|ru|rz] (default: rne)\n\
13457 encode EVEX instructions with specific EVEX.RC value\n\
13458 for SAE-only ignored instructions\n"));
13459 fprintf (stream
, _("\
13460 -mmnemonic=[att|intel] "));
13461 if (SYSV386_COMPAT
)
13462 fprintf (stream
, _("(default: att)\n"));
13464 fprintf (stream
, _("(default: intel)\n"));
13465 fprintf (stream
, _("\
13466 use AT&T/Intel mnemonic\n"));
13467 fprintf (stream
, _("\
13468 -msyntax=[att|intel] (default: att)\n\
13469 use AT&T/Intel syntax\n"));
13470 fprintf (stream
, _("\
13471 -mindex-reg support pseudo index registers\n"));
13472 fprintf (stream
, _("\
13473 -mnaked-reg don't require `%%' prefix for registers\n"));
13474 fprintf (stream
, _("\
13475 -madd-bnd-prefix add BND prefix for all valid branches\n"));
13476 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13477 fprintf (stream
, _("\
13478 -mshared disable branch optimization for shared code\n"));
13479 fprintf (stream
, _("\
13480 -mx86-used-note=[no|yes] "));
13481 if (DEFAULT_X86_USED_NOTE
)
13482 fprintf (stream
, _("(default: yes)\n"));
13484 fprintf (stream
, _("(default: no)\n"));
13485 fprintf (stream
, _("\
13486 generate x86 used ISA and feature properties\n"));
13488 #if defined (TE_PE) || defined (TE_PEP)
13489 fprintf (stream
, _("\
13490 -mbig-obj generate big object files\n"));
13492 fprintf (stream
, _("\
13493 -momit-lock-prefix=[no|yes] (default: no)\n\
13494 strip all lock prefixes\n"));
13495 fprintf (stream
, _("\
13496 -mfence-as-lock-add=[no|yes] (default: no)\n\
13497 encode lfence, mfence and sfence as\n\
13498 lock addl $0x0, (%%{re}sp)\n"));
13499 fprintf (stream
, _("\
13500 -mrelax-relocations=[no|yes] "));
13501 if (DEFAULT_GENERATE_X86_RELAX_RELOCATIONS
)
13502 fprintf (stream
, _("(default: yes)\n"));
13504 fprintf (stream
, _("(default: no)\n"));
13505 fprintf (stream
, _("\
13506 generate relax relocations\n"));
13507 fprintf (stream
, _("\
13508 -malign-branch-boundary=NUM (default: 0)\n\
13509 align branches within NUM byte boundary\n"));
13510 fprintf (stream
, _("\
13511 -malign-branch=TYPE[+TYPE...] (default: jcc+fused+jmp)\n\
13512 TYPE is combination of jcc, fused, jmp, call, ret,\n\
13514 specify types of branches to align\n"));
13515 fprintf (stream
, _("\
13516 -malign-branch-prefix-size=NUM (default: 5)\n\
13517 align branches with NUM prefixes per instruction\n"));
13518 fprintf (stream
, _("\
13519 -mbranches-within-32B-boundaries\n\
13520 align branches within 32 byte boundary\n"));
13521 fprintf (stream
, _("\
13522 -mlfence-after-load=[no|yes] (default: no)\n\
13523 generate lfence after load\n"));
13524 fprintf (stream
, _("\
13525 -mlfence-before-indirect-branch=[none|all|register|memory] (default: none)\n\
13526 generate lfence before indirect near branch\n"));
13527 fprintf (stream
, _("\
13528 -mlfence-before-ret=[none|or|not|shl|yes] (default: none)\n\
13529 generate lfence before ret\n"));
13530 fprintf (stream
, _("\
13531 -mamd64 accept only AMD64 ISA [default]\n"));
13532 fprintf (stream
, _("\
13533 -mintel64 accept only Intel64 ISA\n"));
13536 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
13537 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
13538 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
13540 /* Pick the target format to use. */
13543 i386_target_format (void)
13545 if (!strncmp (default_arch
, "x86_64", 6))
13547 update_code_flag (CODE_64BIT
, 1);
13548 if (default_arch
[6] == '\0')
13549 x86_elf_abi
= X86_64_ABI
;
13551 x86_elf_abi
= X86_64_X32_ABI
;
13553 else if (!strcmp (default_arch
, "i386"))
13554 update_code_flag (CODE_32BIT
, 1);
13555 else if (!strcmp (default_arch
, "iamcu"))
13557 update_code_flag (CODE_32BIT
, 1);
13558 if (cpu_arch_isa
== PROCESSOR_UNKNOWN
)
13560 static const i386_cpu_flags iamcu_flags
= CPU_IAMCU_FLAGS
;
13561 cpu_arch_name
= "iamcu";
13562 cpu_sub_arch_name
= NULL
;
13563 cpu_arch_flags
= iamcu_flags
;
13564 cpu_arch_isa
= PROCESSOR_IAMCU
;
13565 cpu_arch_isa_flags
= iamcu_flags
;
13566 if (!cpu_arch_tune_set
)
13568 cpu_arch_tune
= cpu_arch_isa
;
13569 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
13572 else if (cpu_arch_isa
!= PROCESSOR_IAMCU
)
13573 as_fatal (_("Intel MCU doesn't support `%s' architecture"),
13577 as_fatal (_("unknown architecture"));
13579 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
13580 cpu_arch_isa_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
13581 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
13582 cpu_arch_tune_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
13584 switch (OUTPUT_FLAVOR
)
13586 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
13587 case bfd_target_aout_flavour
:
13588 return AOUT_TARGET_FORMAT
;
13590 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
13591 # if defined (TE_PE) || defined (TE_PEP)
13592 case bfd_target_coff_flavour
:
13593 if (flag_code
== CODE_64BIT
)
13594 return use_big_obj
? "pe-bigobj-x86-64" : "pe-x86-64";
13596 return use_big_obj
? "pe-bigobj-i386" : "pe-i386";
13597 # elif defined (TE_GO32)
13598 case bfd_target_coff_flavour
:
13599 return "coff-go32";
13601 case bfd_target_coff_flavour
:
13602 return "coff-i386";
13605 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
13606 case bfd_target_elf_flavour
:
13608 const char *format
;
13610 switch (x86_elf_abi
)
13613 format
= ELF_TARGET_FORMAT
;
13615 tls_get_addr
= "___tls_get_addr";
13619 use_rela_relocations
= 1;
13622 tls_get_addr
= "__tls_get_addr";
13624 format
= ELF_TARGET_FORMAT64
;
13626 case X86_64_X32_ABI
:
13627 use_rela_relocations
= 1;
13630 tls_get_addr
= "__tls_get_addr";
13632 disallow_64bit_reloc
= 1;
13633 format
= ELF_TARGET_FORMAT32
;
13636 if (cpu_arch_isa
== PROCESSOR_L1OM
)
13638 if (x86_elf_abi
!= X86_64_ABI
)
13639 as_fatal (_("Intel L1OM is 64bit only"));
13640 return ELF_TARGET_L1OM_FORMAT
;
13642 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
13644 if (x86_elf_abi
!= X86_64_ABI
)
13645 as_fatal (_("Intel K1OM is 64bit only"));
13646 return ELF_TARGET_K1OM_FORMAT
;
13648 else if (cpu_arch_isa
== PROCESSOR_IAMCU
)
13650 if (x86_elf_abi
!= I386_ABI
)
13651 as_fatal (_("Intel MCU is 32bit only"));
13652 return ELF_TARGET_IAMCU_FORMAT
;
13658 #if defined (OBJ_MACH_O)
13659 case bfd_target_mach_o_flavour
:
13660 if (flag_code
== CODE_64BIT
)
13662 use_rela_relocations
= 1;
13664 return "mach-o-x86-64";
13667 return "mach-o-i386";
13675 #endif /* OBJ_MAYBE_ more than one */
13678 md_undefined_symbol (char *name
)
13680 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
13681 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
13682 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
13683 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
13687 if (symbol_find (name
))
13688 as_bad (_("GOT already in symbol table"));
13689 GOT_symbol
= symbol_new (name
, undefined_section
,
13690 (valueT
) 0, &zero_address_frag
);
13697 /* Round up a section size to the appropriate boundary. */
13700 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
13702 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
13703 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
13705 /* For a.out, force the section size to be aligned. If we don't do
13706 this, BFD will align it for us, but it will not write out the
13707 final bytes of the section. This may be a bug in BFD, but it is
13708 easier to fix it here since that is how the other a.out targets
13712 align
= bfd_section_alignment (segment
);
13713 size
= ((size
+ (1 << align
) - 1) & (-((valueT
) 1 << align
)));
13720 /* On the i386, PC-relative offsets are relative to the start of the
13721 next instruction. That is, the address of the offset, plus its
13722 size, since the offset is always the last part of the insn. */
13725 md_pcrel_from (fixS
*fixP
)
13727 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
13733 s_bss (int ignore ATTRIBUTE_UNUSED
)
13737 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13739 obj_elf_section_change_hook ();
13741 temp
= get_absolute_expression ();
13742 subseg_set (bss_section
, (subsegT
) temp
);
13743 demand_empty_rest_of_line ();
13748 /* Remember constant directive. */
13751 i386_cons_align (int ignore ATTRIBUTE_UNUSED
)
13753 if (last_insn
.kind
!= last_insn_directive
13754 && (bfd_section_flags (now_seg
) & SEC_CODE
))
13756 last_insn
.seg
= now_seg
;
13757 last_insn
.kind
= last_insn_directive
;
13758 last_insn
.name
= "constant directive";
13759 last_insn
.file
= as_where (&last_insn
.line
);
13760 if (lfence_before_ret
!= lfence_before_ret_none
)
13762 if (lfence_before_indirect_branch
!= lfence_branch_none
)
13763 as_warn (_("constant directive skips -mlfence-before-ret "
13764 "and -mlfence-before-indirect-branch"));
13766 as_warn (_("constant directive skips -mlfence-before-ret"));
13768 else if (lfence_before_indirect_branch
!= lfence_branch_none
)
13769 as_warn (_("constant directive skips -mlfence-before-indirect-branch"));
13774 i386_validate_fix (fixS
*fixp
)
13776 if (fixp
->fx_subsy
)
13778 if (fixp
->fx_subsy
== GOT_symbol
)
13780 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
13784 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13785 if (fixp
->fx_tcbit2
)
13786 fixp
->fx_r_type
= (fixp
->fx_tcbit
13787 ? BFD_RELOC_X86_64_REX_GOTPCRELX
13788 : BFD_RELOC_X86_64_GOTPCRELX
);
13791 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
13796 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
13798 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
13800 fixp
->fx_subsy
= 0;
13803 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13804 else if (!object_64bit
)
13806 if (fixp
->fx_r_type
== BFD_RELOC_386_GOT32
13807 && fixp
->fx_tcbit2
)
13808 fixp
->fx_r_type
= BFD_RELOC_386_GOT32X
;
13814 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
13817 bfd_reloc_code_real_type code
;
13819 switch (fixp
->fx_r_type
)
13821 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13822 case BFD_RELOC_SIZE32
:
13823 case BFD_RELOC_SIZE64
:
13824 if (S_IS_DEFINED (fixp
->fx_addsy
)
13825 && !S_IS_EXTERNAL (fixp
->fx_addsy
))
13827 /* Resolve size relocation against local symbol to size of
13828 the symbol plus addend. */
13829 valueT value
= S_GET_SIZE (fixp
->fx_addsy
) + fixp
->fx_offset
;
13830 if (fixp
->fx_r_type
== BFD_RELOC_SIZE32
13831 && !fits_in_unsigned_long (value
))
13832 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
13833 _("symbol size computation overflow"));
13834 fixp
->fx_addsy
= NULL
;
13835 fixp
->fx_subsy
= NULL
;
13836 md_apply_fix (fixp
, (valueT
*) &value
, NULL
);
13840 /* Fall through. */
13842 case BFD_RELOC_X86_64_PLT32
:
13843 case BFD_RELOC_X86_64_GOT32
:
13844 case BFD_RELOC_X86_64_GOTPCREL
:
13845 case BFD_RELOC_X86_64_GOTPCRELX
:
13846 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
13847 case BFD_RELOC_386_PLT32
:
13848 case BFD_RELOC_386_GOT32
:
13849 case BFD_RELOC_386_GOT32X
:
13850 case BFD_RELOC_386_GOTOFF
:
13851 case BFD_RELOC_386_GOTPC
:
13852 case BFD_RELOC_386_TLS_GD
:
13853 case BFD_RELOC_386_TLS_LDM
:
13854 case BFD_RELOC_386_TLS_LDO_32
:
13855 case BFD_RELOC_386_TLS_IE_32
:
13856 case BFD_RELOC_386_TLS_IE
:
13857 case BFD_RELOC_386_TLS_GOTIE
:
13858 case BFD_RELOC_386_TLS_LE_32
:
13859 case BFD_RELOC_386_TLS_LE
:
13860 case BFD_RELOC_386_TLS_GOTDESC
:
13861 case BFD_RELOC_386_TLS_DESC_CALL
:
13862 case BFD_RELOC_X86_64_TLSGD
:
13863 case BFD_RELOC_X86_64_TLSLD
:
13864 case BFD_RELOC_X86_64_DTPOFF32
:
13865 case BFD_RELOC_X86_64_DTPOFF64
:
13866 case BFD_RELOC_X86_64_GOTTPOFF
:
13867 case BFD_RELOC_X86_64_TPOFF32
:
13868 case BFD_RELOC_X86_64_TPOFF64
:
13869 case BFD_RELOC_X86_64_GOTOFF64
:
13870 case BFD_RELOC_X86_64_GOTPC32
:
13871 case BFD_RELOC_X86_64_GOT64
:
13872 case BFD_RELOC_X86_64_GOTPCREL64
:
13873 case BFD_RELOC_X86_64_GOTPC64
:
13874 case BFD_RELOC_X86_64_GOTPLT64
:
13875 case BFD_RELOC_X86_64_PLTOFF64
:
13876 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
13877 case BFD_RELOC_X86_64_TLSDESC_CALL
:
13878 case BFD_RELOC_RVA
:
13879 case BFD_RELOC_VTABLE_ENTRY
:
13880 case BFD_RELOC_VTABLE_INHERIT
:
13882 case BFD_RELOC_32_SECREL
:
13884 code
= fixp
->fx_r_type
;
13886 case BFD_RELOC_X86_64_32S
:
13887 if (!fixp
->fx_pcrel
)
13889 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
13890 code
= fixp
->fx_r_type
;
13893 /* Fall through. */
13895 if (fixp
->fx_pcrel
)
13897 switch (fixp
->fx_size
)
13900 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
13901 _("can not do %d byte pc-relative relocation"),
13903 code
= BFD_RELOC_32_PCREL
;
13905 case 1: code
= BFD_RELOC_8_PCREL
; break;
13906 case 2: code
= BFD_RELOC_16_PCREL
; break;
13907 case 4: code
= BFD_RELOC_32_PCREL
; break;
13909 case 8: code
= BFD_RELOC_64_PCREL
; break;
13915 switch (fixp
->fx_size
)
13918 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
13919 _("can not do %d byte relocation"),
13921 code
= BFD_RELOC_32
;
13923 case 1: code
= BFD_RELOC_8
; break;
13924 case 2: code
= BFD_RELOC_16
; break;
13925 case 4: code
= BFD_RELOC_32
; break;
13927 case 8: code
= BFD_RELOC_64
; break;
13934 if ((code
== BFD_RELOC_32
13935 || code
== BFD_RELOC_32_PCREL
13936 || code
== BFD_RELOC_X86_64_32S
)
13938 && fixp
->fx_addsy
== GOT_symbol
)
13941 code
= BFD_RELOC_386_GOTPC
;
13943 code
= BFD_RELOC_X86_64_GOTPC32
;
13945 if ((code
== BFD_RELOC_64
|| code
== BFD_RELOC_64_PCREL
)
13947 && fixp
->fx_addsy
== GOT_symbol
)
13949 code
= BFD_RELOC_X86_64_GOTPC64
;
13952 rel
= XNEW (arelent
);
13953 rel
->sym_ptr_ptr
= XNEW (asymbol
*);
13954 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
13956 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
13958 if (!use_rela_relocations
)
13960 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
13961 vtable entry to be used in the relocation's section offset. */
13962 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
13963 rel
->address
= fixp
->fx_offset
;
13964 #if defined (OBJ_COFF) && defined (TE_PE)
13965 else if (fixp
->fx_addsy
&& S_IS_WEAK (fixp
->fx_addsy
))
13966 rel
->addend
= fixp
->fx_addnumber
- (S_GET_VALUE (fixp
->fx_addsy
) * 2);
13971 /* Use the rela in 64bit mode. */
13974 if (disallow_64bit_reloc
)
13977 case BFD_RELOC_X86_64_DTPOFF64
:
13978 case BFD_RELOC_X86_64_TPOFF64
:
13979 case BFD_RELOC_64_PCREL
:
13980 case BFD_RELOC_X86_64_GOTOFF64
:
13981 case BFD_RELOC_X86_64_GOT64
:
13982 case BFD_RELOC_X86_64_GOTPCREL64
:
13983 case BFD_RELOC_X86_64_GOTPC64
:
13984 case BFD_RELOC_X86_64_GOTPLT64
:
13985 case BFD_RELOC_X86_64_PLTOFF64
:
13986 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
13987 _("cannot represent relocation type %s in x32 mode"),
13988 bfd_get_reloc_code_name (code
));
13994 if (!fixp
->fx_pcrel
)
13995 rel
->addend
= fixp
->fx_offset
;
13999 case BFD_RELOC_X86_64_PLT32
:
14000 case BFD_RELOC_X86_64_GOT32
:
14001 case BFD_RELOC_X86_64_GOTPCREL
:
14002 case BFD_RELOC_X86_64_GOTPCRELX
:
14003 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
14004 case BFD_RELOC_X86_64_TLSGD
:
14005 case BFD_RELOC_X86_64_TLSLD
:
14006 case BFD_RELOC_X86_64_GOTTPOFF
:
14007 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
14008 case BFD_RELOC_X86_64_TLSDESC_CALL
:
14009 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
14012 rel
->addend
= (section
->vma
14014 + fixp
->fx_addnumber
14015 + md_pcrel_from (fixp
));
14020 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
14021 if (rel
->howto
== NULL
)
14023 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
14024 _("cannot represent relocation type %s"),
14025 bfd_get_reloc_code_name (code
));
14026 /* Set howto to a garbage value so that we can keep going. */
14027 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
14028 gas_assert (rel
->howto
!= NULL
);
14034 #include "tc-i386-intel.c"
14037 tc_x86_parse_to_dw2regnum (expressionS
*exp
)
14039 int saved_naked_reg
;
14040 char saved_register_dot
;
14042 saved_naked_reg
= allow_naked_reg
;
14043 allow_naked_reg
= 1;
14044 saved_register_dot
= register_chars
['.'];
14045 register_chars
['.'] = '.';
14046 allow_pseudo_reg
= 1;
14047 expression_and_evaluate (exp
);
14048 allow_pseudo_reg
= 0;
14049 register_chars
['.'] = saved_register_dot
;
14050 allow_naked_reg
= saved_naked_reg
;
14052 if (exp
->X_op
== O_register
&& exp
->X_add_number
>= 0)
14054 if ((addressT
) exp
->X_add_number
< i386_regtab_size
)
14056 exp
->X_op
= O_constant
;
14057 exp
->X_add_number
= i386_regtab
[exp
->X_add_number
]
14058 .dw2_regnum
[flag_code
>> 1];
14061 exp
->X_op
= O_illegal
;
14066 tc_x86_frame_initial_instructions (void)
14068 static unsigned int sp_regno
[2];
14070 if (!sp_regno
[flag_code
>> 1])
14072 char *saved_input
= input_line_pointer
;
14073 char sp
[][4] = {"esp", "rsp"};
14076 input_line_pointer
= sp
[flag_code
>> 1];
14077 tc_x86_parse_to_dw2regnum (&exp
);
14078 gas_assert (exp
.X_op
== O_constant
);
14079 sp_regno
[flag_code
>> 1] = exp
.X_add_number
;
14080 input_line_pointer
= saved_input
;
14083 cfi_add_CFA_def_cfa (sp_regno
[flag_code
>> 1], -x86_cie_data_alignment
);
14084 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
14088 x86_dwarf2_addr_size (void)
14090 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
14091 if (x86_elf_abi
== X86_64_X32_ABI
)
14094 return bfd_arch_bits_per_address (stdoutput
) / 8;
14098 i386_elf_section_type (const char *str
, size_t len
)
14100 if (flag_code
== CODE_64BIT
14101 && len
== sizeof ("unwind") - 1
14102 && strncmp (str
, "unwind", 6) == 0)
14103 return SHT_X86_64_UNWIND
;
14110 i386_solaris_fix_up_eh_frame (segT sec
)
14112 if (flag_code
== CODE_64BIT
)
14113 elf_section_type (sec
) = SHT_X86_64_UNWIND
;
14119 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
14123 exp
.X_op
= O_secrel
;
14124 exp
.X_add_symbol
= symbol
;
14125 exp
.X_add_number
= 0;
14126 emit_expr (&exp
, size
);
14130 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
14131 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
14134 x86_64_section_letter (int letter
, const char **ptr_msg
)
14136 if (flag_code
== CODE_64BIT
)
14139 return SHF_X86_64_LARGE
;
14141 *ptr_msg
= _("bad .section directive: want a,l,w,x,M,S,G,T in string");
14144 *ptr_msg
= _("bad .section directive: want a,w,x,M,S,G,T in string");
14149 x86_64_section_word (char *str
, size_t len
)
14151 if (len
== 5 && flag_code
== CODE_64BIT
&& CONST_STRNEQ (str
, "large"))
14152 return SHF_X86_64_LARGE
;
14158 handle_large_common (int small ATTRIBUTE_UNUSED
)
14160 if (flag_code
!= CODE_64BIT
)
14162 s_comm_internal (0, elf_common_parse
);
14163 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
14167 static segT lbss_section
;
14168 asection
*saved_com_section_ptr
= elf_com_section_ptr
;
14169 asection
*saved_bss_section
= bss_section
;
14171 if (lbss_section
== NULL
)
14173 flagword applicable
;
14174 segT seg
= now_seg
;
14175 subsegT subseg
= now_subseg
;
14177 /* The .lbss section is for local .largecomm symbols. */
14178 lbss_section
= subseg_new (".lbss", 0);
14179 applicable
= bfd_applicable_section_flags (stdoutput
);
14180 bfd_set_section_flags (lbss_section
, applicable
& SEC_ALLOC
);
14181 seg_info (lbss_section
)->bss
= 1;
14183 subseg_set (seg
, subseg
);
14186 elf_com_section_ptr
= &_bfd_elf_large_com_section
;
14187 bss_section
= lbss_section
;
14189 s_comm_internal (0, elf_common_parse
);
14191 elf_com_section_ptr
= saved_com_section_ptr
;
14192 bss_section
= saved_bss_section
;
14195 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */